init commit via android 4.4 uboot

2347 files changed, 558628 insertions, 0 deletions

diff --git a/board/AtmarkTechno/suzaku/Makefile b/board/AtmarkTechno/suzaku/Makefile
new file mode 100755
index 0000000..7a17067
--- /dev/null
+++ b/board/AtmarkTechno/suzaku/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/AtmarkTechno/suzaku/config.mk b/board/AtmarkTechno/suzaku/config.mk
new file mode 100755
index 0000000..7bbf2b1
--- /dev/null
+++ b/board/AtmarkTechno/suzaku/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2004 Atmark Techno, Inc.
+#
+# Yasushi SHOJI <yashi@atmark-techno.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x80F00000
+
+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
+PLATFORM_CPPFLAGS += -mno-xl-soft-div
+PLATFORM_CPPFLAGS += -mxl-barrel-shift
diff --git a/board/AtmarkTechno/suzaku/flash.c b/board/AtmarkTechno/suzaku/flash.c
new file mode 100755
index 0000000..49a0673
--- /dev/null
+++ b/board/AtmarkTechno/suzaku/flash.c
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+unsigned long flash_init(void)
+{
+	return 0;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	return 0;
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	return 0;
+}
diff --git a/board/AtmarkTechno/suzaku/suzaku.c b/board/AtmarkTechno/suzaku/suzaku.c
new file mode 100755
index 0000000..afe124a
--- /dev/null
+++ b/board/AtmarkTechno/suzaku/suzaku.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This is a board specific file.  It's OK to include board specific
+ * header files */
+#include <asm/suzaku.h>
+
+void do_reset(void)
+{
+	*((unsigned long *)(MICROBLAZE_SYSREG_BASE_ADDR)) = MICROBLAZE_SYSREG_RECONFIGURE;
+}
diff --git a/board/AtmarkTechno/suzaku/u-boot.lds b/board/AtmarkTechno/suzaku/u-boot.lds
new file mode 100755
index 0000000..00a8ef7
--- /dev/null
+++ b/board/AtmarkTechno/suzaku/u-boot.lds
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(microblaze)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text ALIGN(0x4):
+	{
+		__text_start = .;
+		cpu/microblaze/start.o (.text)
+		*(.text)
+		__text_end = .;
+	}
+
+	.rodata ALIGN(0x4):
+	{
+		__rodata_start = .;
+		*(.rodata)
+		__rodata_end = .;
+	}
+
+	.data ALIGN(0x4):
+	{
+		__data_start = .;
+		*(.data)
+		__data_end = .;
+	}
+
+	.u_boot_cmd ALIGN(0x4):
+	{
+		. = .;
+		__u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		__u_boot_cmd_end = .;
+	}
+
+	.bss ALIGN(0x4):
+	{
+		__bss_start = .;
+		*(.bss)
+		__bss_start = .;
+	}
+}
diff --git a/board/LEOX/elpt860/Makefile b/board/LEOX/elpt860/Makefile
new file mode 100755
index 0000000..3e73163
--- /dev/null
+++ b/board/LEOX/elpt860/Makefile
@@ -0,0 +1,48 @@
+
+#######################################################################
+#
+# Copyright (C) 2000, 2001, 2002, 2003
+# The LEOX team <team@leox.org>, http://www.leox.org
+#
+# LEOX.org is about the development of free hardware and software resources
+#   for system on chip.
+#
+# Description: U-Boot port on the LEOX's ELPT860 CPU board
+# ~~~~~~~~~~~
+#
+#######################################################################
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#######################################################################
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/LEOX/elpt860/README.LEOX b/board/LEOX/elpt860/README.LEOX
new file mode 100755
index 0000000..9052b09
--- /dev/null
+++ b/board/LEOX/elpt860/README.LEOX
@@ -0,0 +1,424 @@
+=============================================================================
+
+	     U-Boot port on the LEOX's ELPT860 CPU board
+	     -------------------------------------------
+
+LEOX.org is about the development of free hardware and software resources
+	 for system on chip.
+
+For more information, contact The LEOX team <team@leox.org>
+
+References:
+~~~~~~~~~~
+    1) Get the last stable release from denx.de:
+	   o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2
+    2) Get the current CVS snapshot:
+	   o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
+	   o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
+
+=============================================================================
+
+The ELPT860 CPU board has the following features:
+
+Processor:	- MPC860T @ 50MHz
+		- PowerPC Core
+		- 65 MIPS
+		- Caches: D->4KB, I->4KB
+		- CPM: 4 SCCs, 2 SMCs
+		- Ethernet 10/100
+		- SPI, I2C, PCMCIA, Parallel
+
+CPU board:	- DRAM:   16 MB
+		- FLASH: 512 KB + (2 * 4 MB)
+		- NVRAM: 128 KB
+		- 1 Serial link
+		- 2 Ethernet 10 BaseT Channels
+
+On power-up the processor jumps to the address of 0x02000100
+
+Thus, U-Boot is configured to reside in flash starting at the address of
+0x02001000.  The environment space is located in NVRAM separately from
+U-Boot, at the address of 0x03000000.
+
+=============================================================================
+
+			U-Boot test results
+
+=============================================================================
+
+
+##################################################
+# Operation on the serial console (SMC1)
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: help
+askenv  - get environment variables from stdin
+autoscr - run script from memory
+base    - print or set address offset
+bdinfo  - print Board Info structure
+bootm   - boot application image from memory
+bootp   - boot image via network using BootP/TFTP protocol
+bootd   - boot default, i.e., run 'bootcmd'
+cmp     - memory compare
+coninfo - print console devices and informations
+cp      - memory copy
+crc32   - checksum calculation
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+iminfo  - print header information for application image
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loop    - infinite loop on address range
+md      - memory display
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nm      - memory modify (constant address)
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sleep   - delay execution for some time
+tftpboot- boot image via network using TFTP protocol
+	       and env variables ipaddr and serverip
+version - print monitor version
+?       - alias for 'help'
+
+##################################################
+# Environment Variables (CFG_ENV_IS_IN_NVRAM)
+##############################
+
+LEOX_elpt860: printenv
+bootdelay=5
+loads_echo=1
+baudrate=9600
+stdin=serial
+stdout=serial
+stderr=serial
+ethaddr=00:03:ca:00:64:df
+ipaddr=192.168.0.30
+netmask=255.255.255.0
+serverip=192.168.0.1
+nfsserverip=192.168.0.1
+preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo
+gatewayip=192.168.0.1
+ramargs=setenv bootargs root=/dev/ram rw
+rootargs=setenv rootpath /tftp/${ipaddr}
+nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${nfsserverip}:${rootpath}
+addip=setenv bootargs ${bootargs} ip=${ipaddr}:${nfsserverip}:${gatewayip}:${netmask}:${hostname}:eth0:
+ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm
+nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm
+bootcmd=run ramboot
+clocks_in_mhz=1
+
+Environment size: 730/16380 bytes
+
+##################################################
+# Flash Memory Information
+##############################
+
+LEOX_elpt860: flinfo
+
+Bank # 1: AMD AM29F040   (4 Mbits)
+  Size: 512 KB in 8 Sectors
+  Sector Start Addresses:
+    02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000
+    02050000      02060000      02070000
+
+##################################################
+# Board Information Structure
+##############################
+
+LEOX_elpt860: bdinfo
+memstart    = 0x00000000
+memsize     = 0x01000000
+flashstart  = 0x02000000
+flashsize   = 0x00080000
+flashoffset = 0x00030000
+sramstart   = 0x00000000
+sramsize    = 0x00000000
+immr_base   = 0xFF000000
+bootflags   = 0x00000001
+intfreq     =     50 MHz
+busfreq     =     50 MHz
+ethaddr     = 00:03:ca:00:64:df
+IP addr     = 192.168.0.30
+baudrate    =   9600 bps
+
+##################################################
+# Image Download and run over serial port
+#    hello_world (S-Record image)
+#    ===> 1) Enter "loads" command into U-Boot monitor
+#    ===> 2) From TeraTerm's bar menu, Select 'File/Send file...'
+#            Then select 'hello_world.srec' with the file browser
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: loads
+## Ready for S-Record download ...
+S804040004F3050154000501709905014C000501388D
+## First Load Addr = 0x00040000
+## Last  Load Addr = 0x0005018B
+## Total Size      = 0x0001018C = 65932 Bytes
+## Start Addr      = 0x00040004
+LEOX_elpt860: go 40004 This is a test !!!
+## Starting application at 0x00040004 ...
+Hello World
+argc = 6
+argv[0] = "40004"
+argv[1] = "This"
+argv[2] = "is"
+argv[3] = "a"
+argv[4] = "test"
+argv[5] = "!!!"
+argv[6] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+
+##################################################
+# Image download and run over ethernet interface
+#    Linux-2.4.4 (uImage) + Root filesystem mounted over NFS
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: run nfsboot
+ARP broadcast 1
+TFTP from server 192.168.0.1; our IP address is 192.168.0.30
+Filename '/home/leox/uImage'.
+Load address: 0x400000
+Loading: #################################################################
+	 #############################
+done
+Bytes transferred = 477294 (7486e hex)
+## Booting image at 00400000 ...
+   Image Name:   Linux-2.4.4
+   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
+   Data Size:    477230 Bytes = 466 kB = 0 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Verifying Checksum ... OK
+   Uncompressing Kernel Image ... OK
+Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
+On node 0 totalpages: 4096
+zone(0): 4096 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0:
+rtsched version <20010618.1050.24>
+Decrementer Frequency: 3125000
+Warning: real time clock seems stuck!
+Calibrating delay loop... 49.76 BogoMIPS
+Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem)
+Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
+Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
+Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
+POSIX conformance testing by UNIFIX
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Starting kswapd v1.8
+CPM UART driver version 0.03
+ttyS0 on SMC1 at 0x0280, BRG1
+block: queued sectors max/low 9701kB/3233kB, 64 slots per queue
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 1024 bind 1024)
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+Looking up port of RPC 100003/2 on 192.168.0.1
+Looking up port of RPC 100005/2 on 192.168.0.1
+VFS: Mounted root (nfs filesystem).
+Freeing unused kernel memory: 44k init
+INIT: version 2.78 booting
+		Welcome to DENX Embedded Linux Environment
+		Press 'I' to enter interactive startup.
+Mounting proc filesystem:  [  OK  ]
+Configuring kernel parameters:  [  OK  ]
+Cannot access the Hardware Clock via any known method.
+Use the --debug option to see the details of our search for an access method.
+Setting clock : Wed Dec 31 19:00:11 EST 1969 [  OK  ]
+Activating swap partitions:  [  OK  ]
+Setting hostname 192.168.0.30:  [  OK  ]
+Finding module dependencies:
+[  OK  ]
+Checking filesystems
+Checking all file systems.
+[  OK  ]
+Mounting local filesystems:  [  OK  ]
+Enabling swap space:  [  OK  ]
+INIT: Entering runlevel: 3
+Entering non-interactive startup
+Starting system logger: [  OK  ]
+Starting kernel logger: [  OK  ]
+Starting xinetd: [  OK  ]
+
+192 login: root
+Last login: Wed Dec 31 19:00:41 on ttyS0
+bash-2.04#
+
+##################################################
+# Image download and run over ethernet interface
+#    Linux-2.4.4 + Root filesystem mounted from RAM (pMulti)
+##############################
+
+U-Boot 0.2.2 (Jan 19 2003 - 11:08:39)
+
+CPU:   XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present
+	 *** Warning: CPU Core has Silicon Bugs -- Check the Errata ***
+Board: ### No HW ID - assuming ELPT860
+DRAM:  16 MB
+FLASH: 512 kB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+
+Type "run nfsboot" to mount root filesystem over NFS
+
+Hit any key to stop autoboot:  0
+LEOX_elpt860: run ramboot
+ARP broadcast 1
+TFTP from server 192.168.0.1; our IP address is 192.168.0.30
+Filename '/home/leox/pMulti'.
+Load address: 0x400000
+Loading: #################################################################
+	 #################################################################
+	 #################################################################
+	 #################################################################
+	 #################################################################
+	 ########################################################
+done
+Bytes transferred = 1947816 (1db8a8 hex)
+## Booting image at 00400000 ...
+   Image Name:   linux-2.4.4-2002-03-21 Multiboot
+   Image Type:   PowerPC Linux Multi-File Image (gzip compressed)
+   Data Size:    1947752 Bytes = 1902 kB = 1 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Contents:
+   Image 0:   477230 Bytes = 466 kB = 0 MB
+   Image 1:  1470508 Bytes = 1436 kB = 1 MB
+   Verifying Checksum ... OK
+   Uncompressing Multi-File Image ... OK
+   Loading Ramdisk to 00e44000, end 00fab02c ... OK
+Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002
+On node 0 totalpages: 4096
+zone(0): 4096 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: root=/dev/ram rw
+rtsched version <20010618.1050.24>
+Decrementer Frequency: 3125000
+Warning: real time clock seems stuck!
+Calibrating delay loop... 49.76 BogoMIPS
+Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem)
+Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes)
+Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes)
+Page-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Inode-cache hash table entries: 1024 (order: 1, 8192 bytes)
+POSIX conformance testing by UNIFIX
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Starting kswapd v1.8
+CPM UART driver version 0.03
+ttyS0 on SMC1 at 0x0280, BRG1
+block: queued sectors max/low 8741kB/2913kB, 64 slots per queue
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df
+RAMDISK: Compressed image found at block 0
+Freeing initrd memory: 1436k freed
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 1024 bind 1024)
+IP-Config: Incomplete network configuration information.
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+VFS: Mounted root (ext2 filesystem).
+Freeing unused kernel memory: 44k iné
+init started:  BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname
+Configuring lo...
+Configuring eth0...
+Configuring Gateway...
+
+Please press Enter to activate this console.
+
+ELPT860 login: root
+Password:
+Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz)
+
+					      a8888b.
+					     d888888b.
+					     8P"YP"Y88
+     _      _                                8|o||o|88
+    | |    |_|                               8'    .88
+    | |     _ ____  _   _  _  _              8`._.' Y8.
+    | |    | |  _ \| | | |\ \/ /            d/      `8b.
+    | |___ | | | | | |_| |/    \          .dP   .     Y8b.
+    |_____||_|_| |_|\____|\_/\_/         d8:'   "   `::88b.
+					d8"           `Y88b
+				       :8P     '       :888
+					8a.    :      _a88P
+				      ._/"Yaa_ :    .| 88P|
+				      \    YP"      `| 8P  `.
+				      /     \._____.d|    .'
+				      `--..__)888888P`._.'
+login[21]: root login  on `ttyS0'
+
+
+
+BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash)
+Enter 'help' for a list of built-in commands.
+
+root@ELPT860:~ #
diff --git a/board/LEOX/elpt860/config.mk b/board/LEOX/elpt860/config.mk
new file mode 100755
index 0000000..defc360
--- /dev/null
+++ b/board/LEOX/elpt860/config.mk
@@ -0,0 +1,36 @@
+#######################################################################
+#
+# Copyright (C) 2000, 2001, 2002, 2003
+# The LEOX team <team@leox.org>, http://www.leox.org
+#
+# LEOX.org is about the development of free hardware and software resources
+#   for system on chip.
+#
+# Description: U-Boot port on the LEOX's ELPT860 CPU board
+# ~~~~~~~~~~~
+#
+#######################################################################
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#######################################################################
+
+#
+# ELPT860 board
+#
+
+TEXT_BASE = 0x02000000
+#TEXT_BASE = 0x00FB0000
diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c
new file mode 100755
index 0000000..775db73
--- /dev/null
+++ b/board/LEOX/elpt860/elpt860.c
@@ -0,0 +1,348 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+/*
+** Note 1: In this file, you have to provide the following functions:
+** ------
+**              int             board_early_init_f(void)
+**              int             checkboard(void)
+**              long int        initdram(int board_type)
+** called from 'board_init_f()' into 'common/board.c'
+**
+**              void            reset_phy(void)
+** called from 'board_init_r()' into 'common/board.c'
+*/
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint init_sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
+	0xFFFFFC04,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,	/* last */
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
+	0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04,	/* last */
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
+	0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05,	/* last */
+};
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+	0xFF0FFC00,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
+	0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
+	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
+	0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05,	/* last */
+	_NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
+	0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
+	0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
+	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04,	/* last */
+};
+
+/* ------------------------------------------------------------------------- */
+
+#define CFG_PC4    0x0800
+
+#define CFG_DS1    CFG_PC4
+
+/*
+ * Very early board init code (fpga boot, etc.)
+ */
+int board_early_init_f (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/*
+	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
+	 */
+	immr->im_ioport.iop_pcdat &= ~CFG_DS1;	/* PCDAT (DS1 = 0)                */
+	immr->im_ioport.iop_pcpar &= ~CFG_DS1;	/* PCPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_pcdir |= CFG_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
+
+	return (0);		/* success */
+}
+
+/*
+ * Check Board Identity:
+ *
+ * Test ELPT860 ID string
+ *
+ * Return 1 if no second DRAM bank, otherwise returns 0
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	if (!s || strncmp (s, "ELPT860", 7))
+		printf ("### No HW ID - assuming ELPT860\n");
+
+	return (0);		/* success */
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
+
+	/*
+	 * This sequence initializes SDRAM chips on ELPT860 board
+	 */
+	upmconfig (UPMA, (uint *) init_sdram_table,
+		   sizeof (init_sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = 0x0200;
+	memctl->memc_mamr = 0x18002111;
+
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = 0x80002000;	/* CS1: SDRAM bank 0 */
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	/*
+	 * The following value is used as an address (i.e. opcode) for
+	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+	 * the port size is 32bit the SDRAM does NOT "see" the lower two
+	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+	 * MICRON SDRAMs:
+	 * ->    0 00 010 0 010
+	 *       |  |   | |   +- Burst Length = 4
+	 *       |  |   | +----- Burst Type   = Sequential
+	 *       |  |   +------- CAS Latency  = 2
+	 *       |  +----------- Operating Mode = Standard
+	 *       +-------------- Write Burst Mode = Programmed Burst Length
+	 */
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002105;	/* CS1: SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL,
+			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL,
+			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {	/* leave configuration at 9 columns       */
+		size_b0 = size9;
+		/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
+	} else {		/* back to 8 columns                      */
+
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if (size_b0 < 0x02000000) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	{
+		unsigned long reg;
+
+		/* adjust refresh rate depending on SDRAM type, one bank */
+		reg = memctl->memc_mptpr;
+		reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+		memctl->memc_mptpr = reg;
+	}
+
+	udelay (10000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int
+dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define CFG_PA1     0x4000
+#define CFG_PA2     0x2000
+
+#define CFG_LBKs    (CFG_PA2 | CFG_PA1)
+
+void reset_phy (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/*
+	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
+	 *                                          and no AUI loopback
+	 */
+	immr->im_ioport.iop_padat &= ~CFG_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
+	immr->im_ioport.iop_papar &= ~CFG_LBKs;	/* PAPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_padir |= CFG_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
+}
diff --git a/board/LEOX/elpt860/flash.c b/board/LEOX/elpt860/flash.c
new file mode 100755
index 0000000..c1b3b85
--- /dev/null
+++ b/board/LEOX/elpt860/flash.c
@@ -0,0 +1,615 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+/*
+** Note 1: In this file, you have to provide the following variable:
+** ------
+**              flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]
+** 'flash_info_t' structure is defined into 'include/flash.h'
+** and defined as extern into 'common/cmd_flash.c'
+**
+** Note 2: In this file, you have to provide the following functions:
+** ------
+**              unsigned long   flash_init(void)
+** called from 'board_init_r()' into 'common/board.c'
+**
+**              void            flash_print_info(flash_info_t *info)
+** called from 'do_flinfo()' into 'common/cmd_flash.c'
+**
+**              int             flash_erase(flash_info_t *info,
+**                                          int           s_first,
+**                                          int           s_last)
+** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c'
+**
+**              int             write_buff (flash_info_t *info,
+**                                          uchar        *src,
+**                                          ulong         addr,
+**                                          ulong         cnt)
+** called from 'flash_write()' into 'common/cmd_flash.c'
+*/
+
+#include <common.h>
+#include <mpc8xx.h>
+
+
+#ifndef	CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Internal Functions
+ */
+static void   flash_get_offsets (ulong base, flash_info_t *info);
+static ulong  flash_get_size (volatile unsigned char *addr, flash_info_t *info);
+
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init (void)
+{
+  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+  volatile memctl8xx_t *memctl = &immap->im_memctl;
+  unsigned long         size_b0;
+  int i;
+
+  /* Init: no FLASHes known */
+  for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+    {
+      flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+  /* Static FLASH Bank configuration here - FIXME XXX */
+
+  size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM,
+			    &flash_info[0]);
+
+  if ( flash_info[0].flash_id == FLASH_UNKNOWN )
+    {
+      printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	      size_b0, size_b0<<20);
+    }
+
+  /* Remap FLASH according to real size */
+  memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+  memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
+
+  /* Re-do sizing to get full correct info */
+  size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE,
+			    &flash_info[0]);
+
+  flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+  /* monitor protection ON by default */
+  flash_protect (FLAG_PROTECT_SET,
+		 CFG_MONITOR_BASE,
+		 CFG_MONITOR_BASE + monitor_flash_len-1,
+		 &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+  /* ENV protection ON by default */
+  flash_protect(FLAG_PROTECT_SET,
+		CFG_ENV_ADDR,
+		CFG_ENV_ADDR + CFG_ENV_SIZE-1,
+		&flash_info[0]);
+#endif
+
+  flash_info[0].size = size_b0;
+
+  return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_get_offsets (ulong          base,
+		   flash_info_t  *info)
+{
+  int i;
+
+#define SECTOR_64KB    0x00010000
+
+  /* set up sector start adress table */
+  for (i = 0; i < info->sector_count; i++)
+    {
+      info->start[i] = base + (i * SECTOR_64KB);
+    }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info (flash_info_t *info)
+{
+  int i;
+
+  if ( info->flash_id == FLASH_UNKNOWN )
+    {
+      printf ("missing or unknown FLASH type\n");
+      return;
+    }
+
+  switch ( info->flash_id & FLASH_VENDMASK )
+    {
+    case FLASH_MAN_AMD:	printf ("AMD ");		break;
+    case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+    case FLASH_MAN_STM: printf ("STM (Thomson) ");      break;
+    default:		printf ("Unknown Vendor ");	break;
+    }
+
+  switch ( info->flash_id & FLASH_TYPEMASK )
+    {
+    case FLASH_AM040:   printf ("AM29F040   (4 Mbits)\n");
+      break;
+    default:	        printf ("Unknown Chip Type\n");
+      break;
+    }
+
+  printf ("  Size: %ld KB in %d Sectors\n",
+	  info->size >> 10, info->sector_count);
+
+  printf ("  Sector Start Addresses:");
+  for (i=0; i<info->sector_count; ++i)
+    {
+      if ((i % 5) == 0)
+	printf ("\n   ");
+      printf (" %08lX%s",
+	      info->start[i],
+	      info->protect[i] ? " (RO)" : "     "
+	      );
+    }
+  printf ("\n");
+
+  return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong
+flash_get_size (volatile unsigned char *addr,
+		flash_info_t           *info)
+{
+  short i;
+  uchar value;
+  ulong base = (ulong)addr;
+
+  /* Write auto select command: read Manufacturer ID */
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  addr[0x0555] = 0x90;
+
+  value = addr[0];
+
+  switch ( value )
+    {
+      /*    case AMD_MANUFACT: */
+    case 0x01:
+      info->flash_id = FLASH_MAN_AMD;
+      break;
+      /*    case FUJ_MANUFACT: */
+    case 0x04:
+      info->flash_id = FLASH_MAN_FUJ;
+      break;
+      /*    case STM_MANUFACT: */
+    case 0x20:
+      info->flash_id = FLASH_MAN_STM;
+      break;
+
+    default:
+      info->flash_id = FLASH_UNKNOWN;
+      info->sector_count = 0;
+      info->size = 0;
+      return (0);			/* no or unknown flash	*/
+    }
+
+  value = addr[1];			/* device ID		*/
+
+  switch ( value )
+    {
+    case STM_ID_F040B:
+    case AMD_ID_F040B:
+      info->flash_id += FLASH_AM040;    /* 4 Mbits = 512k * 8  */
+      info->sector_count = 8;
+      info->size = 0x00080000;
+      break;
+
+    default:
+      info->flash_id = FLASH_UNKNOWN;
+      return (0);			/* => no or unknown flash */
+    }
+
+  /* set up sector start adress table */
+  for (i = 0; i < info->sector_count; i++)
+    {
+      info->start[i] = base + (i * 0x00010000);
+    }
+
+  /* check for protected sectors */
+  for (i = 0; i < info->sector_count; i++)
+    {
+      /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+      /* D0 = 1 if protected */
+      addr = (volatile unsigned char *)(info->start[i]);
+      info->protect[i] = addr[2] & 1;
+    }
+
+  /*
+   * Prevent writes to uninitialized FLASH.
+   */
+  if ( info->flash_id != FLASH_UNKNOWN )
+    {
+      addr = (volatile unsigned char *)info->start[0];
+
+      *addr = 0xF0;	/* reset bank */
+    }
+
+  return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase (flash_info_t  *info,
+	     int            s_first,
+	     int            s_last)
+{
+  volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+  int flag, prot, sect, l_sect;
+  ulong start, now, last;
+
+  if ( (s_first < 0) || (s_first > s_last) )
+    {
+      if ( info->flash_id == FLASH_UNKNOWN )
+	{
+	  printf ("- missing\n");
+	}
+      else
+	{
+	  printf ("- no sectors to erase\n");
+	}
+      return ( 1 );
+    }
+
+  if ( (info->flash_id == FLASH_UNKNOWN) ||
+       (info->flash_id > FLASH_AMD_COMP) )
+    {
+      printf ("Can't erase unknown flash type %08lx - aborted\n",
+	      info->flash_id);
+      return ( 1 );
+    }
+
+  prot = 0;
+  for (sect=s_first; sect<=s_last; ++sect)
+    {
+      if ( info->protect[sect] )
+	{
+	  prot++;
+	}
+    }
+
+  if ( prot )
+    {
+      printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+    }
+  else
+    {
+      printf ("\n");
+    }
+
+  l_sect = -1;
+
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  addr[0x0555] = 0x80;
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+
+  /* Start erase on unprotected sectors */
+  for (sect = s_first; sect<=s_last; sect++)
+    {
+      if (info->protect[sect] == 0)    /* not protected */
+	{
+	  addr = (volatile unsigned char *)(info->start[sect]);
+	  addr[0] = 0x30;
+	  l_sect = sect;
+	}
+    }
+
+  /* re-enable interrupts if necessary */
+  if ( flag )
+    enable_interrupts();
+
+  /* wait at least 80us - let's wait 1 ms */
+  udelay (1000);
+
+  /*
+   * We wait for the last triggered sector
+   */
+  if ( l_sect < 0 )
+    goto DONE;
+
+  start = get_timer (0);
+  last  = start;
+  addr = (volatile unsigned char *)(info->start[l_sect]);
+  while ( (addr[0] & 0x80) != 0x80 )
+    {
+      if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT )
+	{
+	  printf ("Timeout\n");
+	  return ( 1 );
+	}
+      /* show that we're waiting */
+      if ( (now - last) > 1000 )     /* every second */
+	{
+	  putc ('.');
+	  last = now;
+	}
+    }
+
+DONE:
+  /* reset to read mode */
+  addr = (volatile unsigned char *)info->start[0];
+  addr[0] = 0xF0;	/* reset bank */
+
+  printf (" done\n");
+
+  return ( 0 );
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int
+write_buff (flash_info_t  *info,
+	    uchar         *src,
+	    ulong          addr,
+	    ulong          cnt)
+{
+  ulong cp, wp, data;
+  uchar bdata;
+  int i, l, rc;
+
+  if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 )
+    {
+      /* Width of the data bus: 8 bits */
+
+      wp = addr;
+
+      while ( cnt )
+	{
+	  bdata = *src++;
+
+	  if ( (rc = write_byte(info, wp, bdata)) != 0 )
+	    {
+	      return (rc);
+	    }
+
+	  ++wp;
+	  --cnt;
+	}
+
+      return ( 0 );
+    }
+  else
+    {
+      /* Width of the data bus: 32 bits */
+
+      wp = (addr & ~3);	/* get lower word aligned address */
+
+      /*
+       * handle unaligned start bytes
+       */
+      if ( (l = addr - wp) != 0 )
+	{
+	  data = 0;
+	  for (i=0, cp=wp; i<l; ++i, ++cp)
+	    {
+	      data = (data << 8) | (*(uchar *)cp);
+	    }
+	  for (; i<4 && cnt>0; ++i)
+	    {
+	      data = (data << 8) | *src++;
+	      --cnt;
+	      ++cp;
+	    }
+	  for (; cnt==0 && i<4; ++i, ++cp)
+	    {
+	      data = (data << 8) | (*(uchar *)cp);
+	    }
+
+	  if ( (rc = write_word(info, wp, data)) != 0 )
+	    {
+	      return (rc);
+	    }
+	  wp += 4;
+	}
+
+      /*
+       * handle word aligned part
+       */
+      while ( cnt >= 4 )
+	{
+	  data = 0;
+	  for (i=0; i<4; ++i)
+	    {
+	      data = (data << 8) | *src++;
+	    }
+	  if ( (rc = write_word(info, wp, data)) != 0 )
+	    {
+	      return (rc);
+	    }
+	  wp  += 4;
+	  cnt -= 4;
+	}
+
+      if ( cnt == 0 )
+	{
+	  return (0);
+	}
+
+      /*
+       * handle unaligned tail bytes
+       */
+      data = 0;
+      for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp)
+	{
+	  data = (data << 8) | *src++;
+	  --cnt;
+	}
+      for (; i<4; ++i, ++cp)
+	{
+	  data = (data << 8) | (*(uchar *)cp);
+	}
+
+      return (write_word(info, wp, data));
+    }
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word (flash_info_t  *info,
+	    ulong          dest,
+	    ulong          data)
+{
+  vu_long *addr = (vu_long*)(info->start[0]);
+  ulong start;
+  int flag;
+
+  /* Check if Flash is (sufficiently) erased */
+  if ( (*((vu_long *)dest) & data) != data )
+    {
+      return (2);
+    }
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+  addr[0x0555] = 0x00A000A0;
+
+  *((vu_long *)dest) = data;
+
+  /* re-enable interrupts if necessary */
+  if ( flag )
+    enable_interrupts();
+
+  /* data polling for D7 */
+  start = get_timer (0);
+  while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
+    {
+      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
+	{
+	  return (1);
+	}
+    }
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_byte (flash_info_t  *info,
+	    ulong          dest,
+	    uchar          data)
+{
+  volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+  ulong  start;
+  int    flag;
+
+  /* Check if Flash is (sufficiently) erased */
+  if ( (*((volatile unsigned char *)dest) & data) != data )
+    {
+      return (2);
+    }
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0xAA;
+  addr[0x02AA] = 0x55;
+  addr[0x0555] = 0xA0;
+
+  *((volatile unsigned char *)dest) = data;
+
+  /* re-enable interrupts if necessary */
+  if ( flag )
+    enable_interrupts();
+
+  /* data polling for D7 */
+  start = get_timer (0);
+  while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
+    {
+      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
+	{
+	  return (1);
+	}
+    }
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds
new file mode 100755
index 0000000..b09fc33
--- /dev/null
+++ b/board/LEOX/elpt860/u-boot.lds
@@ -0,0 +1,154 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o			(.text)
+    common/dlmalloc.o			(.text)
+    lib_ppc/ppcstring.o			(.text)
+    lib_generic/vsprintf.o		(.text)
+    lib_generic/crc32.o			(.text)
+    lib_generic/zlib.o			(.text)
+    lib_generic/string.o		(.text)
+    lib_ppc/cache.o			(.text)
+    lib_ppc/extable.o			(.text)
+    lib_ppc/time.o			(.text)
+    lib_ppc/ticks.o			(.text)
+
+    . = env_offset;
+    common/environment.o		(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug
new file mode 100755
index 0000000..6f5af91
--- /dev/null
+++ b/board/LEOX/elpt860/u-boot.lds.debug
@@ -0,0 +1,141 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
new file mode 100755
index 0000000..0934e1b
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2002
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include "articiaS.h"
+#include "memio.h"
+#include "via686.h"
+
+__asm(" .globl send_kb                                      \n
+	send_kb:                                            \n
+		lis     r9, 0xfe00                          \n
+							    \n
+		li      r4, 0x10        # retries           \n
+		mtctr   r4                                  \n
+							    \n
+	idle:                                               \n
+		lbz     r4, 0x64(r9)                        \n
+		andi.   r4, r4, 0x02                        \n
+		bne     idle                                \n
+							    \n
+	ready:                                              \n
+		stb     r3, 0x60(r9)                        \n
+							    \n
+	check:                                              \n
+		lbz     r4, 0x64(r9)                        \n
+		andi.   r4, r4, 0x01                        \n
+		beq     check                               \n
+							    \n
+		lbz     r4, 0x60(r9)                        \n
+		cmpwi   r4, 0xfa                            \n
+		beq     done                                \n
+							    \n
+		bdnz    idle                                \n
+							    \n
+		li      r3, 0                               \n
+		blr                                         \n
+							    \n
+	done:                                               \n
+		li      r3, 1                               \n
+		blr                                         \n
+							    \n
+	.globl test_kb                                      \n
+	test_kb:                                            \n
+		mflr    r10                                 \n
+		li      r3, 0xed                            \n
+		bl      send_kb                             \n
+		li      r3, 0x01                            \n
+		bl      send_kb                             \n
+		mtlr    r10                                 \n
+		blr                                         \n
+");
+
+
+int checkboard (void)
+{
+	printf ("Board: AmigaOneG3SE\n");
+	return 0;
+}
+
+long initdram (int board_type)
+{
+	return articiaS_ram_init ();
+}
+
+
+void after_reloc (ulong dest_addr, gd_t *gd)
+{
+/* HJF:	DECLARE_GLOBAL_DATA_PTR; */
+
+	board_init_r (gd, dest_addr);
+}
+
+
+int misc_init_r (void)
+{
+	extern pci_dev_t video_dev;
+	extern void drv_video_init (void);
+
+	if (video_dev != ~0)
+		drv_video_init ();
+
+	return (0);
+}
+
+
+void pci_init_board (void)
+{
+#ifndef CONFIG_RAMBOOT
+	articiaS_pci_init ();
+#endif
+}
diff --git a/board/MAI/AmigaOneG3SE/Makefile b/board/MAI/AmigaOneG3SE/Makefile
new file mode 100755
index 0000000..b1247fe
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COBJS	= $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \
+		via686.o i8259.o ../bios_emulator/x86interface.o 	\
+		../bios_emulator/bios.o ../bios_emulator/glue.o		\
+		interrupts.o ps2kbd.o video.o usb_uhci.o enet.o	        \
+		../menu/cmd_menu.o cmd_boota.o nvram.o
+
+AOBJS	= board_asm_init.o memio.o
+
+OBJS	= $(COBJS) $(AOBJS)
+
+EMUDIR  = ../bios_emulator/scitech/src/x86emu/
+EMUOBJ  = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \
+		$(EMUDIR)ops.o $(EMUDIR)sys.o
+EMUSRC = $(EMUOBJ:.o=.c)
+
+$(LIB):	.depend $(OBJS) $(EMUSRC)
+	make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
+	-rm $(LIB)
+	$(AR) crv $@ $(OBJS) $(EMUOBJ)
+
+
+#########################################################################
+
+.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
+	$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/MAI/AmigaOneG3SE/articiaS.c b/board/MAI/AmigaOneG3SE/articiaS.c
new file mode 100755
index 0000000..a4dad64
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/articiaS.c
@@ -0,0 +1,705 @@
+/*
+ * (C) Copyright 2002
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include "memio.h"
+#include "articiaS.h"
+#include "smbus.h"
+#include "via686.h"
+
+#undef DEBUG
+
+struct dimm_bank {
+	uint8 used;			/* Bank is populated */
+	uint32 rows;			/* Number of row addresses */
+	uint32 columns;			/* Number of column addresses */
+	uint8 registered;		/* SIMM is registered */
+	uint8 ecc;			/* SIMM has ecc */
+	uint8 burst_len;		/* Supported burst lengths */
+	uint32 cas_lat;			/* Supported CAS latencies */
+	uint32 cas_used;		/* CAS to use (not set by user) */
+	uint32 trcd;			/* RAS to CAS latency */
+	uint32 trp;			/* Precharge latency */
+	uint32 tclk_hi;			/* SDRAM cycle time (highest CAS latency) */
+	uint32 tclk_2hi;		/* SDRAM second highest CAS latency */
+	uint32 size;			/* Size of bank in bytes */
+	uint8 auto_refresh;		/* Module supports auto refresh */
+	uint32 refresh_time;		/* Refresh time (in ns) */
+};
+
+
+/*
+** Based in part on the evb64260 code
+*/
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+
+long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
+{
+    DECLARE_GLOBAL_DATA_PTR;
+	int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
+	uint32 busclock = gd->bus_clk;
+	uint32 memclock = busclock;
+	uint32 tmemclock = 1000000000 / (memclock / 100);
+	uint32 datawidth;
+
+	if (sm_get_data (rom, dimm_address) == 0) {
+		/* Nothing in slot, make both banks empty */
+		debug ("Slot %d: vacant\n", dimmNum);
+		banks[0].used = 0;
+		banks[1].used = 0;
+		return 0;
+	}
+
+	if (rom[2] != 0x04) {
+		debug ("Slot %d: No SDRAM\n", dimmNum);
+		banks[0].used = 0;
+		banks[1].used = 0;
+		return 0;
+	}
+
+	/* Determine number of banks/rows */
+	if (rom[5] == 1) {
+		banks[0].used = 1;
+		banks[1].used = 0;
+	} else {
+		banks[0].used = 1;
+		banks[1].used = 1;
+	}
+
+	/* Determine number of row addresses */
+	if (rom[3] & 0xf0) {
+		/* Different banks sizes */
+		banks[0].rows = rom[3] & 0x0f;
+		banks[1].rows = (rom[3] & 0xf0) >> 4;
+	} else {
+		/* Equal sized banks */
+		banks[0].rows = rom[3] & 0x0f;
+		banks[1].rows = banks[0].rows;
+	}
+
+	/* Determine number of column addresses */
+	if (rom[4] & 0xf0) {
+		/* Different bank sizes */
+		banks[0].columns = rom[4] & 0x0f;
+		banks[1].columns = (rom[4] & 0xf0) >> 4;
+	} else {
+		banks[0].columns = rom[4] & 0x0f;
+		banks[1].columns = banks[0].columns;
+	}
+
+	/* Check Jedec revision, and modify row/column accordingly */
+	if (rom[62] > 0x10) {
+		if (banks[0].rows <= 3)
+			banks[0].rows += 15;
+		if (banks[1].rows <= 3)
+			banks[1].rows += 15;
+		if (banks[0].columns <= 3)
+			banks[0].columns += 15;
+		if (banks[0].columns <= 3)
+			banks[0].columns += 15;
+	}
+
+	/* Check registered/unregisterd */
+	if (rom[21] & 0x12) {
+		banks[0].registered = 1;
+		banks[1].registered = 1;
+	} else {
+		banks[0].registered = 0;
+		banks[1].registered = 0;
+	}
+
+#ifdef CONFIG_ECC
+	/* Check parity/ECC */
+	banks[0].ecc = (rom[11] == 0x02);
+	banks[1].ecc = (rom[11] == 0x02);
+#endif
+
+	/* Find burst lengths supported */
+	banks[0].burst_len = rom[16] & 0x8f;
+	banks[1].burst_len = rom[16] & 0x8f;
+
+	/* Find possible cas latencies */
+	banks[0].cas_lat = rom[18] & 0x7F;
+	banks[1].cas_lat = rom[18] & 0x7F;
+
+	/* RAS/CAS latency */
+	banks[0].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
+	banks[1].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
+
+	/* Precharge latency */
+	banks[0].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
+	banks[1].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
+
+	/* highest CAS latency */
+	banks[0].tclk_hi = NS10to10PS (rom[9]);
+	banks[1].tclk_hi = NS10to10PS (rom[9]);
+
+	/* second highest CAS latency */
+	banks[0].tclk_2hi = NS10to10PS (rom[23]);
+	banks[1].tclk_2hi = NS10to10PS (rom[23]);
+
+	/* bank sizes */
+	datawidth = rom[13] & 0x7f;
+	banks[0].size =
+			(1L << (banks[0].rows + banks[0].columns)) *
+			/* FIXME datawidth */ 8 * rom[17];
+	if (rom[13] & 0x80)
+		banks[1].size = 2 * banks[0].size;
+	else
+		banks[1].size = (1L << (banks[1].rows + banks[1].columns)) *
+				/* FIXME datawidth */ 8 * rom[17];
+
+	/* Refresh */
+	if (rom[12] & 0x80) {
+		banks[0].auto_refresh = 1;
+		banks[1].auto_refresh = 1;
+	} else {
+		banks[0].auto_refresh = 0;
+		banks[1].auto_refresh = 0;
+	}
+
+	switch (rom[12] & 0x7f) {
+	case 0:
+		banks[0].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
+		banks[1].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
+		break;
+	case 1:
+		banks[0].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
+		banks[1].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
+		break;
+	case 2:
+		banks[0].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
+		banks[1].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
+		break;
+	case 3:
+		banks[0].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
+		banks[1].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
+		break;
+	case 4:
+		banks[0].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
+		banks[1].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
+		break;
+	case 5:
+		banks[0].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
+		banks[1].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
+		break;
+	default:
+		banks[0].refresh_time = 0x100;	/* Default of Articia S */
+		banks[1].refresh_time = 0x100;
+		break;
+	}
+
+#ifdef DEBUG
+	printf ("\nInformation for SIMM bank %ld:\n", dimmNum);
+	printf ("Number of banks: %ld\n", banks[0].used + banks[1].used);
+	printf ("Number of row addresses: %ld\n", banks[0].rows);
+	printf ("Number of coumns addresses: %ld\n", banks[0].columns);
+	printf ("SIMM is %sregistered\n",
+			banks[0].registered == 0 ? "not " : "");
+#ifdef CONFIG_ECC
+	printf ("SIMM %s ECC\n",
+			banks[0].ecc == 1 ? "supports" : "doesn't support");
+#endif
+	printf ("Supported burst lenghts: %s %s %s %s %s\n",
+			banks[0].burst_len & 0x08 ? "8" : " ",
+			banks[0].burst_len & 0x04 ? "4" : " ",
+			banks[0].burst_len & 0x02 ? "2" : " ",
+			banks[0].burst_len & 0x01 ? "1" : " ",
+			banks[0].burst_len & 0x80 ? "PAGE" : "    ");
+	printf ("Supported CAS latencies: %s %s %s\n",
+			banks[0].cas_lat & 0x04 ? "CAS 3" : "     ",
+			banks[0].cas_lat & 0x02 ? "CAS 2" : "     ",
+			banks[0].cas_lat & 0x01 ? "CAS 1" : "     ");
+	printf ("RAS to CAS latency: %ld\n", banks[0].trcd);
+	printf ("Precharge latency: %ld\n", banks[0].trp);
+	printf ("SDRAM highest CAS latency: %ld\n", banks[0].tclk_hi);
+	printf ("SDRAM 2nd highest CAS latency: %ld\n", banks[0].tclk_2hi);
+	printf ("SDRAM data width: %ld\n", datawidth);
+	printf ("Auto Refresh %ssupported\n",
+			banks[0].auto_refresh ? "" : "not ");
+	printf ("Refresh time: %ld clocks\n", banks[0].refresh_time);
+	if (banks[0].used)
+		printf ("Bank 0 size: %ld MB\n", banks[0].size / 1024 / 1024);
+	if (banks[1].used)
+		printf ("Bank 1 size: %ld MB\n", banks[1].size / 1024 / 1024);
+
+	printf ("\n");
+#endif
+
+	sm_term ();
+	return 1;
+}
+
+void select_cas (struct dimm_bank *banks, uint8 fast)
+{
+	if (!banks[0].used) {
+		banks[0].cas_used = 0;
+		banks[0].cas_used = 0;
+		return;
+	}
+
+	if (fast) {
+		/* Search for fast CAS */
+		uint32 i;
+		uint32 c = 0x01;
+
+		for (i = 1; i < 5; i++) {
+			if (banks[0].cas_lat & c) {
+				banks[0].cas_used = i;
+				banks[1].cas_used = i;
+				debug ("Using CAS %d (fast)\n", i);
+				return;
+			}
+			c <<= 1;
+		}
+
+		/* Default to CAS 3 */
+		banks[0].cas_used = 3;
+		banks[1].cas_used = 3;
+		debug ("Using CAS 3 (fast)\n");
+
+		return;
+	} else {
+		/* Search for slow cas */
+		uint32 i;
+		uint32 c = 0x08;
+
+		for (i = 4; i > 1; i--) {
+			if (banks[0].cas_lat & c) {
+				banks[0].cas_used = i;
+				banks[1].cas_used = i;
+				debug ("Using CAS %d (slow)\n", i);
+				return;
+			}
+			c >>= 1;
+		}
+
+		/* Default to CAS 3 */
+		banks[0].cas_used = 3;
+		banks[1].cas_used = 3;
+		debug ("Using CAS 3 (slow)\n");
+
+		return;
+	}
+
+	banks[0].cas_used = 3;
+	banks[1].cas_used = 3;
+	debug ("Using CAS 3\n");
+
+	return;
+}
+
+uint32 get_reg_setting (uint32 banks, uint32 rows, uint32 columns, uint32 size)
+{
+	uint32 i;
+
+	struct RowColumnSize {
+		uint32 banks;
+		uint32 rows;
+		uint32 columns;
+		uint32 size;
+		uint32 register_value;
+	};
+
+	struct RowColumnSize rcs_map[] = {
+		/*  Sbk Radr Cadr   MB     Value */
+		{1, 11, 8, 8, 0x00840f00},
+		{1, 11, 9, 16, 0x00925f00},
+		{1, 11, 10, 32, 0x00a64f00},
+		{2, 12, 8, 32, 0x00c55f00},
+		{2, 12, 9, 64, 0x00d66f00},
+		{2, 12, 10, 128, 0x00e77f00},
+		{2, 12, 11, 256, 0x00ff8f00},
+		{2, 13, 11, 512, 0x00ff9f00},
+		{0, 0, 0, 0, 0x00000000}
+	};
+
+
+	i = 0;
+
+	while (rcs_map[i].banks != 0) {
+		if (rows == rcs_map[i].rows
+			&& columns == rcs_map[i].columns
+			&& (size / 1024 / 1024) == rcs_map[i].size)
+			return rcs_map[i].register_value;
+
+		i++;
+	}
+
+	return 0;
+}
+
+uint32 burst_to_len (uint32 support)
+{
+	if (support & 0x80)
+		return 0x7;
+	else if (support & 0x8)
+		return 0x3;
+	else if (support & 0x4)
+		return 0x2;
+	else if (support & 0x2)
+		return 0x1;
+	else if (support & 0x1)
+		return 0x0;
+
+	return 0;
+}
+
+long articiaS_ram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	register uint32 i;
+	register uint32 value1;
+	register uint32 value2;
+	uint8 rom[128];
+	uint32 burst_len;
+	uint32 burst_support;
+	uint32 total_ram = 0;
+
+	struct dimm_bank banks[4];	/* FIXME: Move to initram */
+	uint32 busclock = gd->bus_clk;
+	uint32 memclock = busclock;
+	uint32 reg32;
+	uint32 refresh_clocks;
+	uint8 auto_refresh;
+
+	memset (banks, 0, sizeof (struct dimm_bank) * 4);
+
+	detect_sdram (rom, 0, &banks[0]);
+	detect_sdram (rom, 1, &banks[2]);
+
+	for (i = 0; i < 4; i++) {
+		total_ram = total_ram + (banks[i].used * banks[i].size);
+	}
+
+	pci_write_cfg_long (0, 0, GLOBALINFO0, 0x117430c0);
+	pci_write_cfg_long (0, 0, HBUSACR0, 0x1f0100b0);
+	pci_write_cfg_long (0, 0, SRAM_CR, 0x00f12000);	/* Note: Might also try 0x00f10000 (original: 0x00f12000) */
+	pci_write_cfg_byte (0, 0, DRAM_RAS_CTL0, 0x3f);
+	pci_write_cfg_byte (0, 0, DRAM_RAS_CTL1, 0x00);	/*  was: 0x04); */
+	pci_write_cfg_word (0, 0, DRAM_ECC0, 0x2020);	/*  was: 0x2400);  No ECC yet */
+
+	/* FIXME: Move this stuff to seperate function, like setup_dimm_bank */
+	if (banks[0].used) {
+		value1 = get_reg_setting (banks[0].used + banks[1].used,
+					  banks[0].rows, banks[0].columns,
+					  banks[0].size);
+	} else {
+		value1 = 0;
+	}
+
+	if (banks[1].used) {
+		value2 = get_reg_setting (banks[0].used + banks[1].used,
+					  banks[1].rows, banks[1].columns,
+					  banks[1].size);
+	} else {
+		value2 = 0;
+	}
+
+	pci_write_cfg_long (0, 0, DIMM0_B0_SCR0, value1);
+	pci_write_cfg_long (0, 0, DIMM0_B1_SCR0, value2);
+
+	debug ("DIMM0_B0_SCR0 = 0x%08x\n", value1);
+	debug ("DIMM0_B1_SCR0 = 0x%08x\n", value2);
+
+	if (banks[2].used) {
+		value1 = get_reg_setting (banks[2].used + banks[3].used,
+					  banks[2].rows, banks[2].columns,
+					  banks[2].size);
+	} else {
+		value1 = 0;
+	}
+
+	if (banks[3].used) {
+		value2 = get_reg_setting (banks[2].used + banks[3].used,
+					  banks[3].rows, banks[3].columns,
+					  banks[3].size);
+	} else {
+		value2 = 0;
+	}
+
+	pci_write_cfg_long (0, 0, DIMM1_B2_SCR0, value1);
+	pci_write_cfg_long (0, 0, DIMM1_B3_SCR0, value2);
+
+	debug ("DIMM0_B2_SCR0 = 0x%08x\n", value1);
+	debug ("DIMM0_B3_SCR0 = 0x%08x\n", value2);
+
+	pci_write_cfg_long (0, 0, DIMM2_B4_SCR0, 0);
+	pci_write_cfg_long (0, 0, DIMM2_B5_SCR0, 0);
+	pci_write_cfg_long (0, 0, DIMM3_B6_SCR0, 0);
+	pci_write_cfg_long (0, 0, DIMM3_B7_SCR0, 0);
+
+	/* Determine timing */
+	select_cas (&banks[0], 0);
+	select_cas (&banks[2], 0);
+
+	/* FIXME: What about write recovery */
+	/*                    Auto refresh    Precharge */
+#if 0
+	reg32 = (0x3 << 13) | (0x7 << 10) | ((banks[0].trp - 2) << 8) |
+	/*    Write recovery  CAS Latency */
+		(0x1 << 6) | (banks[0].cas_used << 4) |
+	/*      RAS/CAS latency */
+		((banks[0].trcd - 1) << 0);
+
+	reg32 |= ((0x3 << 13) | (0x7 << 10) | ((banks[2].trp - 2) << 8) |
+		  (0x1 << 6) | (banks[2].cas_used << 4) |
+		  ((banks[2].trcd - 1) << 0)) << 16;
+#else
+	if (100000000 == gd->bus_clk)
+		reg32 = 0x71737173;
+	else
+		reg32 = 0x69736973;
+#endif
+	pci_write_cfg_long (0, 0, DIMM0_TCR0, reg32);
+	debug ("DIMM0_TCR0 = 0x%08x\n", reg32);
+
+	/* Write default in DIMM2/3 (not used on A1) */
+	pci_write_cfg_long (0, 0, DIMM2_TCR0, 0x7d737d73);
+
+
+	/* Determine buffered/unbuffered mode for each SIMM. Uses first bank as reference (second, if present, uses the same) */
+	reg32 = pci_read_cfg_long (0, 0, DRAM_GCR0);
+	reg32 &= 0xFF00FFFF;
+
+#if 0
+	if (banks[0].used && banks[0].registered)
+		reg32 |= 0x1 << 16;
+
+	if (banks[2].used && banks[2].registered)
+		reg32 |= 0x1 << 18;
+#else
+	if (banks[0].registered || banks[2].registered)
+		reg32 |= 0x55 << 16;
+#endif
+	pci_write_cfg_long (0, 0, DRAM_GCR0, reg32);
+	debug ("DRAM_GCR0 = 0x%08x\n", reg32);
+
+	/* Determine refresh */
+	refresh_clocks = 0xffffffff;
+	auto_refresh = 1;
+
+	for (i = 0; i < 4; i++) {
+		if (banks[i].used) {
+			if (banks[i].auto_refresh == 0)
+				auto_refresh = 0;
+			if (banks[i].refresh_time < refresh_clocks)
+				refresh_clocks = banks[i].refresh_time;
+		}
+	}
+
+
+#if 1
+	/*  It seems this is suggested by the ArticiaS data book */
+	if (100000000 == gd->bus_clk)
+		refresh_clocks = 1561;
+	else
+		refresh_clocks = 2083;
+#endif
+
+
+	debug ("Refresh set to %ld clocks, auto refresh %s\n",
+		   refresh_clocks, auto_refresh ? "on" : "off");
+
+	pci_write_cfg_long (0, 0, DRAM_REFRESH0,
+			(1 << 16) | (1 << 15) | (auto_refresh << 12) |
+			(refresh_clocks));
+	debug ("DRAM_REFRESH0 = 0x%08x\n",
+			(1 << 16) | (1 << 15) | (auto_refresh << 12) |
+			(refresh_clocks));
+
+/*     pci_write_cfg_long(0, 0, DRAM_REFRESH0,   0x00019400);  */
+
+	/* Set mode registers */
+	/* FIXME: For now, set same burst len for all modules. Dunno if that's necessary */
+	/* Find a common burst len */
+	burst_support = 0xff;
+
+	if (banks[0].used)
+		burst_support = banks[0].burst_len;
+	if (banks[1].used)
+		burst_support = banks[1].burst_len;
+	if (banks[2].used)
+		burst_support = banks[2].burst_len;
+	if (banks[3].used)
+		burst_support = banks[3].burst_len;
+
+	/*
+	   ** Mode register:
+	   ** Bits         Use
+	   ** 0-2          Burst len
+	   ** 3            Burst type (0 = sequential, 1 = interleave)
+	   ** 4-6          CAS latency
+	   ** 7-8          Operation mode (0 = default, all others invalid)
+	   ** 9            Write burst
+	   ** 10-11        Reserved
+	   **
+	   ** Mode register burst table:
+	   ** A2 A1 A0     lenght
+	   ** 0  0  0      1
+	   ** 0  0  1      2
+	   ** 0  1  0      4
+	   ** 0  1  1      8
+	   ** 1  0  0      invalid
+	   ** 1  0  1      invalid
+	   ** 1  1  0      invalid
+	   ** 1  1  1      page (only valid for non-interleaved)
+	 */
+
+	burst_len = burst_to_len (burst_support);
+	burst_len = 2;				/* FIXME */
+
+	if (banks[0].used) {
+		pci_write_cfg_word (0, 0, DRAM_PCR0,
+			0x8000 | burst_len | (banks[0].cas_used << 4));
+		debug ("Mode bank 0: 0x%08x\n",
+			0x8000 | burst_len | (banks[0].cas_used << 4));
+	} else {
+		/*  Seems to be needed to disable the bank */
+		pci_write_cfg_word (0, 0, DRAM_PCR0, 0x0000 | 0x032);
+	}
+
+	if (banks[1].used) {
+		pci_write_cfg_word (0, 0, DRAM_PCR0,
+			0x9000 | burst_len | (banks[1].cas_used << 4));
+		debug ("Mode bank 1: 0x%08x\n",
+			0x8000 | burst_len | (banks[1].cas_used << 4));
+	} else {
+		/*  Seems to be needed to disable the bank */
+		pci_write_cfg_word (0, 0, DRAM_PCR0, 0x1000 | 0x032);
+	}
+
+
+	if (banks[2].used) {
+		pci_write_cfg_word (0, 0, DRAM_PCR0,
+			0xa000 | burst_len | (banks[2].cas_used << 4));
+		debug ("Mode bank 2: 0x%08x\n",
+			0x8000 | burst_len | (banks[2].cas_used << 4));
+	} else {
+		/*  Seems to be needed to disable the bank */
+		pci_write_cfg_word (0, 0, DRAM_PCR0, 0x2000 | 0x032);
+	}
+
+
+	if (banks[3].used) {
+		pci_write_cfg_word (0, 0, DRAM_PCR0,
+			0xb000 | burst_len | (banks[3].cas_used << 4));
+		debug ("Mode bank 3: 0x%08x\n",
+			0x8000 | burst_len | (banks[3].cas_used << 4));
+	} else {
+		/*  Seems to be needed to disable the bank */
+		pci_write_cfg_word (0, 0, DRAM_PCR0, 0x3000 | 0x032);
+	}
+
+
+	pci_write_cfg_word (0, 0, 0xba, 0x00);
+
+	return total_ram;
+}
+
+extern int drv_isa_kbd_init (void);
+
+int last_stage_init (void)
+{
+	drv_isa_kbd_init ();
+	return 0;
+}
+
+int overwrite_console (void)
+{
+	return (0);
+}
+
+#define in_8 read_byte
+#define out_8 write_byte
+
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+
+	asm volatile ("mfmsr %0":"=r" (msr):);
+
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	asm volatile ("mtmsr %0"::"r" (msr));
+}
+
+int board_early_init_f (void)
+{
+	unsigned char c_value = 0;
+	unsigned long msr;
+
+	/* Basic init of PS/2 keyboard (needed for some reason)... */
+	/* Ripped from John's code */
+	while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
+	out_8 ((unsigned char *) 0xfe000064, 0xaa);
+	while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
+	c_value = in_8 ((unsigned char *) 0xfe000060);
+	while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
+	out_8 ((unsigned char *) 0xfe000064, 0xab);
+	while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
+	c_value = in_8 ((unsigned char *) 0xfe000060);
+	while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
+	out_8 ((unsigned char *) 0xfe000064, 0xae);
+/*     while ((in_8((unsigned char *)0xfe000064) & 0x01) == 0); */
+/*     c_value = in_8((unsigned char *)0xfe000060); */
+
+	/*  Enable FPU */
+	msr = get_msr ();
+	set_msr (msr | MSR_FP);
+
+	via_calibrate_bus_freq ();
+
+	return 0;
+}
diff --git a/board/MAI/AmigaOneG3SE/articiaS.h b/board/MAI/AmigaOneG3SE/articiaS.h
new file mode 100755
index 0000000..ce20d03
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/articiaS.h
@@ -0,0 +1,142 @@
+#ifndef ARTICIAS_H
+#define ARTICIAS_H
+
+#include "short_types.h"
+#include <common.h>
+
+#define REG_GROUP       0xF0
+
+/* ArticiaS registers */
+#define GLOBALINFO0     0x50
+#define GLOBALINFO1     0x51
+#define GLOBALINFO2     0x52
+#define GLOBALINFO3     0x53
+#define GLOBALCTL0      0x54
+#define GLOBALCTL1      0x55
+#define NVRAMCTL        0x56
+#define PCI1ACR0        0x58
+#define PCI1ACR1        0x59
+#define PCI1ACR2        0x5a
+#define PCI1ACR3        0x5b
+#define HBUSACR0        0x5c
+#define HBUSACR1        0x5d
+#define HBUSACR2        0x5e
+#define HBUSACR3        0x5f
+#define HOSTINT0        0x68
+#define HOSTINT1        0x69
+#define HOSTINT2        0x6a
+#define HOSTINT3        0x6b
+#define HOSTRBCR        0x70
+#define XDBCR           0x74
+
+#define LBSBCR2         0xd2
+
+
+/* Memory controller */
+
+#define DIMM0_B0_SCR0   0x90
+#define DIMM0_B1_SCR0   0x94
+#define DIMM1_B2_SCR0   0x98
+#define DIMM1_B3_SCR0   0x9c
+#define DIMM2_B4_SCR0   0xa0
+#define DIMM2_B5_SCR0   0xa4
+#define DIMM3_B6_SCR0   0xa8
+#define DIMM3_B7_SCR0   0xac
+
+#define DIMM0_TCR0      0xb0
+#define DIMM1_TCR0      0xb2
+#define DIMM2_TCR0      0xb4
+#define DIMM3_TCR0      0xb6
+
+#define DRAM_REFRESH0   0xb8
+#define DRAM_GCR0       0xc0
+#define DRAM_PCR0       0xc6
+#define DRAM_ECC0       0xc4
+#define SRAM_CR         0xc8
+#define DRAM_RAS_CTL0   0xcc
+#define DRAM_RAS_CTL1   0xcd
+
+/* Bits for REG_GROUP */
+#define REG_GROUP_MULTI       (1<<1)
+#define REG_GROUP_SPECIAL     (1<<3)
+#define REG_GROUP_DIAG        (0x1<<4)
+#define REG_GROUP_POWER       (0x2<<4)
+
+
+#define GLOBALINFO0_BO        (1<<7)
+
+
+#define GLOBALINFO2_B1ARBITER (1<<6)
+
+
+#define HBUSACR0_CPUAPC       (1<<0)
+#define HBUSACR0_NUMREQ_2     (0<<1)
+#define HBUSACR0_NUMREQ_3     (1<<1)
+#define HBUSACR0_NUMREQ_4     (2<<1)
+#define HBUSACR0_NUMREQ_MASK  (7<<1)
+#define HBUSACR0_RAW          (1<<6)
+#define HBUSACR0_WAIT         (1<<7)
+#define HBUSACR0_RESERVED     (0x30)
+
+
+#define HBUSACR2_BURST        (1<<0)
+#define HBUSACR2_LAT          (1<<1)
+
+
+#define HBUSACR3_LMWC_SM      (1<<0)
+#define HBUSACR3_LMWC_PCI1    (1<<1)
+#define HBUSACR3_LMWC_PCI0    (1<<2)
+#define HBUSACR3_PMWC_PCI1    (1<<3)
+#define HBUSACR3_PMWC_PCI0    (1<<4)
+#define HBUSACR3_FKH          (1<<5)
+#define HBUSACR3_92H_EN       (1<<6)
+#define HBUSACR3_60H_64H_EN   (1<<7)
+
+
+#define HOSTRBCR_PREFETCH     (1<<4)
+
+
+#define XDBCR_HWTOXD          (1<<0)
+#define XDBCR_KBTOXD          (1<<1)
+#define XDBCR_RTCTOXD         (1<<2)
+#define XDBCR_SCALE_1_1       (0x0<<3)
+#define XDBCR_SCALE_2_2       (0x1<<3)
+#define XDBCR_SCALE_3_2       (0x2<<3)
+#define XDBCR_SCALE_4_4       (0x3<<3)
+#define XDBCR_SCALE_5_8       (0x4<<3)
+#define XDBCR_SCALE_6_8       (0x5<<3)
+#define XDBCR_SCALE_8_8       (0x6<<3)
+#define XDBCR_SCALE_0_16      (0x7<<3)
+#define XDBCR_XDPROM          (1<<7)
+
+
+#define LBSBCR2_1_RWAC        (1<<2)
+
+
+/* PCI controller */
+#define ARTICIAS_PCI_CFGADDR  0xfec00cf8
+#define ARTICIAS_PCI_CFGDATA  0xfee00cfc
+
+#define ARTICIAS_PCI_BUS       0x80000000
+#define ARTICIAS_PCI_MAXSIZE   0x7cffffff
+#define ARTICIAS_PCI_PHYS      0x80000000
+
+#define ARTICIAS_SYS_BUS       0x00000000
+#define ARTICIAS_SYS_MAXSIZE   0x7fffffff
+#define ARTICIAS_SYS_PHYS      0x00000000
+
+#define ARTICIAS_PCIIO_BUS     0x00800000
+#define ARTICIAS_PCIIO_MAXSIZE 0x003fffff
+#define ARTICIAS_PCIIO_PHYS    0xfe800000
+
+#define ARTICIAS_ISAIO_BUS     0x00002000
+#define ARTICIAS_ISAIO_MAXSIZE 0x0000d000
+#define ARTICIAS_ISAIO_PHYS    0xfe002000
+
+
+/* Prototypes */
+long articiaS_ram_init(void);
+void articiaS_pci_init(void);
+
+
+#endif
diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c
new file mode 100755
index 0000000..d2e9f29
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c
@@ -0,0 +1,576 @@
+/*
+ * (C) Copyright 2002
+ * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include "memio.h"
+#include "articiaS.h"
+
+#undef ARTICIA_PCI_DEBUG
+
+#ifdef  ARTICIA_PCI_DEBUG
+#define PRINTF(fmt,args...)     printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+struct pci_controller articiaS_hose;
+
+long irq_alloc(long wanted);
+
+static pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index);
+static int articiaS_init_vga(void);
+static void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table);
+unsigned char pci_irq_alloc(void);
+
+extern void via_cfgfunc_via686(struct pci_controller * host, pci_dev_t dev, struct pci_config_table *table);
+extern void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table);
+extern void via_init_irq_routing(uint8 []);
+extern void via_init_afterscan(void);
+
+#define cfgfunc_via686      1
+#define cfgfunc_dummy  2
+#define cfgfunc_ide_init    3
+
+static struct pci_config_table config_table[] =
+{
+    {
+	0x1106, PCI_ANY_ID, PCI_CLASS_BRIDGE_ISA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	(void *)cfgfunc_via686, {0, 0, 0}
+    },
+    {
+	0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,4,
+	(void *)cfgfunc_dummy, {0,0,0}
+    },
+    {
+	0x1106, 0x3068, PCI_ANY_ID, 0, 7, PCI_ANY_ID,
+	(void *)cfgfunc_dummy, {0,0,0}
+    },
+    {
+	0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,1,
+	(void *)cfgfunc_ide_init, {0,0,0}
+    },
+    {
+	0,
+    }
+};
+
+
+void pci_cfgfunc_dummy(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
+{
+
+
+}
+
+unsigned long irq_penalties[16] =
+{
+    1000,    /* 0:timer */
+    1000,    /* 1:keyboard */
+    1000,    /* 2:cascade */
+    50,      /* 3:serial (COM2) */
+    50,      /* 4:serial (COM1) */
+    4,       /* 5:USB2 */
+    100,     /* 6:floppy */
+    3,       /* 7:parallel */
+    50,      /* 8:AC97/MC97 */
+    0,       /* 9: */
+    3,       /* 10:: */
+    0,       /* 11: */
+    3,       /* 12: USB1 */
+    0,       /* 13: */
+    100,     /* 14: ide0 */
+    100,     /* 15: ide1 */
+};
+
+
+/*
+ * The following defines a hard-coded interrupt mapping for the
+ * know devices on the board.
+ * If a device isn't found here, assumed to be a device that's
+ * plugged into a PCI or AGP slot
+ * NOTE: This table is machine dependant.
+ */
+
+struct pci_irq_fixup_table
+{
+    uint8   bus;             /* Bus number */
+    uint8   device;          /* Device number */
+    uint8   func;            /* Function number */
+    uint8   interrupt;       /* Interrupt to use (0xff to disable) */
+};
+
+struct pci_irq_fixup_table fixuptab [] =
+{
+    { 0, 0, 0, 0xff},        /* Articia S host bridge */
+    { 0, 1, 0, 0xff},        /* Articia S AGP bridge */
+/*    { 0, 6, 0, 0x05},        /###* 3COM ethernet */
+    { 0, 7, 0, 0xff},        /* VIA southbridge */
+    { 0, 7, 1, 0x0e},        /* IDE controller in legacy mode */
+/*    { 0, 7, 2, 0x05},        /###* First USB controller */
+/*    { 0, 7, 3, 0x0c},        /###* Second USB controller (shares interrupt with ethernet) */
+    { 0, 7, 4, 0xff},        /* ACPI Power Management */
+/*    { 0, 7, 5, 0x08},        /###* AC97 */
+/*    { 0, 7, 6, 0x08},        /###* MC97 */
+    { 0xff, 0xff, 0xff, 0xff}
+};
+
+
+/*
+ * This table maps IRQ's to PCI interrupts
+ */
+
+uint8 pci_intmap[4] = {0, 0, 0, 0};
+
+/*
+ * Map PCI slots to interrupt routings
+ * This table lists the device number assigned to a card inserted
+ * into the slot, along with a permutation for the slot's IRQ routing.
+ * NOTE: This table is machine dependant.
+ */
+
+struct pci_slot_irq_routing
+{
+    uint8 bus;
+    uint8 device;
+
+    uint8 ints[4];
+};
+
+struct pci_slot_irq_routing amigaone_pci_routing[] =
+{
+    {0,  8,   {0, 1, 2, 3}},       /* Slot 1 (left of riser slot) */
+    {0,  9,   {1, 2, 3, 0}},       /* Slot 2 (middle slot) */
+    {0, 10,   {2, 3, 0, 1}},       /* Slot 3 (leftmost slot) */
+    {1,  0,   {1, 0, 2, 3}},       /* AGP slot (only IRQA and IRQB) */
+    {1,  1,   {1, 2, 3, 0}},       /* PCI slot on AGP bus */
+    {0,  6,   {3, 3, 3, 3}},       /* On board ethernet */
+    {0,  7,   {0, 1, 2, 3}},       /* Southbridge */
+    {0xff, 0, {0, 0, 0, 0}}
+};
+
+void articiaS_pci_irq_init(void)
+{
+    char *s;
+
+    s = getenv("pci_irqa");
+    if (s)
+	pci_intmap[0] = simple_strtoul (s, NULL, 10);
+    else
+	pci_intmap[0] = pci_irq_alloc();
+
+    s = getenv("pci_irqb");
+    if (s)
+	pci_intmap[1] = simple_strtoul (s, NULL, 10);
+    else
+	pci_intmap[1] = pci_irq_alloc();
+
+    s = getenv("pci_irqc");
+    if (s)
+	pci_intmap[2] = simple_strtoul (s, NULL, 10);
+    else
+	pci_intmap[2] = pci_irq_alloc();
+
+    s = getenv("pci_irqd");
+    if (s)
+	pci_intmap[3] = simple_strtoul (s, NULL, 10);
+    else
+	pci_intmap[3] = pci_irq_alloc();
+}
+
+
+unsigned char pci_irq_alloc(void)
+{
+    int i;
+    int interrupt = 10;
+    unsigned long min_penalty = 1000;
+
+    /* Search for the minimal penalty, favoring interrupts at the end */
+    for (i = 0; i < 16; i++)
+    {
+	if (irq_penalties[i] <= min_penalty)
+	{
+	    interrupt = i;
+	    min_penalty = irq_penalties[i];
+	}
+    }
+
+    PRINTF("pci_irq_alloc: Minimal penalty is %ld for %d\n", min_penalty, interrupt);
+
+    irq_penalties[interrupt]++;
+
+    return interrupt;
+}
+
+
+void articiaS_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+    int8 bus, device, func, pin, line;
+    int i;
+
+    bus = PCI_BUS(dev);
+    device = PCI_DEV(dev);
+    func = PCI_FUNC(dev);
+
+    PRINTF("Fixup irq of %d:%d.%d\n", bus, device, func);
+
+    /* Search for the device in the table */
+    for (i = 0; fixuptab[i].bus != 0xff; i++)
+    {
+	if (bus == fixuptab[i].bus && device == fixuptab[i].device && func == fixuptab[i].func)
+	{
+	    /* If the device needs an interrupt, write it */
+	    if (fixuptab[i].interrupt != 0xff)
+	    {
+		PRINTF("Assigning IRQ %d (fixed)\n", fixuptab[i].interrupt);
+		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, fixuptab[i].interrupt);
+	    }
+	    else
+	    {
+		/* Otherwise, see if it wants an interrupt, and disable it if needed */
+		pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+		if (pin)
+		{
+		    PRINTF("Disabling IRQ\n");
+		    pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0xff);
+		}
+	    }
+
+	    return;
+	}
+    }
+
+    /* If we get here, we have another PCI device in a slot... find the appropriate IRQ */
+
+    /* Find matching pin */
+    pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+    pin--;
+
+    /* Search for it's map */
+    for (i = 0; amigaone_pci_routing[i].bus != 0xff; i++)
+    {
+	if (bus == amigaone_pci_routing[i].bus && device == amigaone_pci_routing[i].device)
+	{
+	    line = pci_intmap[amigaone_pci_routing[i].ints[pin]];
+	    PRINTF("Assigning IRQ %d (pin %d)\n", line, pin);
+	    pci_write_config_byte(dev, PCI_INTERRUPT_LINE, line);
+	    return;
+	}
+    }
+
+    PRINTF("Unkonwn PCI device found\n");
+}
+
+void articiaS_pci_init (void)
+{
+    int i;
+    char *s;
+
+    PRINTF("atriciaS_pci_init\n");
+
+    /* Why aren't these relocated?? */
+    for (i=0; config_table[i].config_device; i++)
+    {
+	switch((int)config_table[i].config_device)
+	{
+	case cfgfunc_via686:     config_table[i].config_device = via_cfgfunc_via686;      break;
+	case cfgfunc_dummy:      config_table[i].config_device = pci_cfgfunc_dummy;       break;
+	case cfgfunc_ide_init:   config_table[i].config_device = via_cfgfunc_ide_init;    break;
+	default: PRINTF("Error: Unknown constant\n");
+	}
+    }
+
+    articiaS_hose.first_busno = 0;
+    articiaS_hose.last_busno = 0xff;
+    articiaS_hose.config_table = config_table;
+    articiaS_hose.fixup_irq = articiaS_pci_fixup_irq;
+
+    articiaS_pci_irq_init();
+
+    /* System memory */
+    pci_set_region(articiaS_hose.regions + 0,
+		   ARTICIAS_SYS_BUS,
+		   ARTICIAS_SYS_PHYS,
+		   ARTICIAS_SYS_MAXSIZE,
+		   PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+    /* PCI memory space */
+    pci_set_region(articiaS_hose.regions + 1,
+		   ARTICIAS_PCI_BUS,
+		   ARTICIAS_PCI_PHYS,
+		   ARTICIAS_PCI_MAXSIZE,
+		   PCI_REGION_MEM);
+
+    /* PCI io space */
+    pci_set_region(articiaS_hose.regions + 2,
+		   ARTICIAS_PCIIO_BUS,
+		   ARTICIAS_PCIIO_PHYS,
+		   ARTICIAS_PCIIO_MAXSIZE,
+		   PCI_REGION_IO);
+
+    /* PCI/ISA io space */
+    pci_set_region(articiaS_hose.regions + 3,
+		   ARTICIAS_ISAIO_BUS,
+		   ARTICIAS_ISAIO_PHYS,
+		   ARTICIAS_ISAIO_MAXSIZE,
+		   PCI_REGION_IO);
+
+
+    articiaS_hose.region_count = 4;
+
+    pci_setup_indirect(&articiaS_hose, ARTICIAS_PCI_CFGADDR, ARTICIAS_PCI_CFGDATA);
+    PRINTF("Registering articia hose...\n");
+    pci_register_hose(&articiaS_hose);
+    PRINTF("Enabling AGP...\n");
+    pci_write_config_byte(PCI_BDF(0,0,0), 0x58, 0x01);
+    PRINTF("Scanning bus...\n");
+    articiaS_hose.last_busno = pci_hose_scan(&articiaS_hose);
+
+    via_init_irq_routing(pci_intmap);
+
+    PRINTF("After-Scan results:\n");
+    PRINTF("Bus range: %d - %d\n", articiaS_hose.first_busno , articiaS_hose.last_busno);
+
+    via_init_afterscan();
+
+    pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);
+
+    s = getenv("as_irq");
+    if (s)
+    {
+	pci_write_config_byte(PCI_BDF(0,0,0), PCI_INTERRUPT_LINE, simple_strtoul (s, NULL, 10));
+    }
+
+    s = getenv("x86_run_bios");
+    if (!s || (s && strcmp(s, "on")==0))
+    {
+	if (articiaS_init_vga() == -1)
+	{
+	    /* If the VGA didn't init and we have stdout set to VGA, reset to serial */
+/* 	    s = getenv("stdout"); */
+/* 	    if (s && strcmp(s, "vga") == 0) */
+/* 	    { */
+/* 		setenv("stdout", "serial"); */
+/* 	    } */
+	}
+    }
+    pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);
+
+}
+
+pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index)
+{
+    unsigned int sub_bus, found_multi=0;
+    unsigned short vendor, class;
+    unsigned char header_type;
+    pci_dev_t dev;
+    u8 c1, c2;
+
+    sub_bus = bus;
+
+    for (dev =  PCI_BDF(bus,0,0);
+	 dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
+	 dev += PCI_BDF(0,0,1))
+    {
+	if ( dev == PCI_BDF(hose->first_busno,0,0) )
+	    continue;
+
+	if (PCI_FUNC(dev) && !found_multi)
+	    continue;
+
+	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
+
+	pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
+
+	if (vendor != 0xffff && vendor != 0x0000)
+	{
+
+	    if (!PCI_FUNC(dev))
+		found_multi = header_type & 0x80;
+	    pci_hose_read_config_byte(hose, dev, 0x0B, &c1);
+	    pci_hose_read_config_byte(hose, dev, 0x0A, &c2);
+	    class = c1<<8 | c2;
+	    /*printf("At %02x:%02x:%02x: class %x\n", */
+	    /*	   PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class); */
+	    if (class == find_class)
+	    {
+		if (index == 0)
+		    return dev;
+		else index--;
+	    }
+	}
+    }
+
+    return ~0;
+}
+
+
+/*
+ * For a given bus number, find the bridge on this hose that provides this
+ * bus number. The function scans for bridges and peeks config space offset
+ * 0x19 (PCI_SECONDARY_BUS).
+ */
+pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr)
+{
+    pci_dev_t dev;
+    int bus;
+    unsigned int found_multi=0;
+    unsigned char header_type;
+    unsigned short vendor;
+    unsigned char secondary_bus;
+
+    if (hose == NULL) hose = &articiaS_hose;
+
+    if (busnr < hose->first_busno || busnr > hose->last_busno) return PCI_ANY_ID; /* Not in range */
+
+    /*
+     * The bridge must be on a lower bus number
+     */
+    for (bus = hose->first_busno; bus < busnr; bus++)
+    {
+	for (dev =  PCI_BDF(bus,0,0);
+	     dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
+	     dev += PCI_BDF(0,0,1))
+	{
+	    if ( dev == PCI_BDF(hose->first_busno,0,0) )
+		continue;
+
+	    if (PCI_FUNC(dev) && !found_multi)
+		continue;
+
+	    pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
+
+	    pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
+
+	    if (vendor != 0xffff && vendor != 0x0000)
+	    {
+
+		if (!PCI_FUNC(dev))
+		    found_multi = header_type & 0x80;
+		if (header_type == 1) /* Bridge device header */
+		{
+		    pci_hose_read_config_byte(hose, dev, PCI_SECONDARY_BUS, &secondary_bus);
+		    if ((int)secondary_bus == busnr) return dev;
+		}
+
+	    }
+	}
+    }
+    return PCI_ANY_ID;
+}
+
+static short classes[] =
+{
+    PCI_CLASS_DISPLAY_VGA,
+    PCI_CLASS_DISPLAY_XGA,
+    PCI_CLASS_DISPLAY_3D,
+    PCI_CLASS_DISPLAY_OTHER,
+    ~0
+};
+
+extern int execute_bios(pci_dev_t gr_dev, void *);
+
+pci_dev_t video_dev;
+
+int articiaS_init_vga (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+    extern void shutdown_bios(void);
+    pci_dev_t dev = ~0;
+    int busnr = 0;
+    int classnr = 0;
+
+    video_dev = PCI_ANY_ID;
+
+    printf("VGA:   ");
+
+    PRINTF("Trying to initialize x86 VGA Card(s)\n");
+
+    while (dev == ~0)
+    {
+	PRINTF("Searching for class 0x%x on bus %d\n", classes[classnr], busnr);
+	/* Find the first of this class on this bus */
+	dev = pci_hose_find_class(&articiaS_hose, busnr, classes[classnr], 0);
+	if (dev != ~0)
+	{
+	    PRINTF("Found VGA Card at %02x:%02x:%02x\n", PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
+	    break;
+	}
+	busnr++;
+	if (busnr > articiaS_hose.last_busno)
+	{
+	    busnr = 0;
+	    classnr ++;
+	    if (classes[classnr] == ~0)
+	    {
+		printf("NOT PRESENT\n");
+		return -1;
+	    }
+	}
+    }
+
+    /*
+     * If we get here we have found the first graphics card.
+     * If the bus number is not 0, then it is probably behind a bridge, and the
+     * bridge needs to be told to forward VGA access.
+     */
+
+    if (PCI_BUS(dev) != 0)
+    {
+	pci_dev_t bridge;
+	PRINTF("Behind bridge, looking for bridge\n");
+	bridge = pci_find_bridge_for_bus(&articiaS_hose, PCI_BUS(dev));
+	if (dev != PCI_ANY_ID)
+	{
+	    unsigned char agp_control_0;
+	    PRINTF("Got the bridge at %02x:%02x:%02x\n",
+		   PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
+	    pci_hose_read_config_byte(&articiaS_hose, bridge, 0x3E, &agp_control_0);
+	    agp_control_0 |= 0x18;
+	    pci_hose_write_config_byte(&articiaS_hose, bridge, 0x3E, agp_control_0);
+	    PRINTF("Configured for VGA forwarding\n");
+	}
+    }
+
+    /*
+     * Now try to run the bios
+     */
+    PRINTF("Trying to run bios now\n");
+    if (execute_bios(dev, gd->relocaddr))
+    {
+	printf("OK\n");
+	video_dev = dev;
+    }
+    else
+    {
+	printf("ERROR\n");
+    }
+
+    PRINTF("Done scanning.\n");
+
+    shutdown_bios();
+
+    if (dev == PCI_ANY_ID) return -1;
+    else return 0;
+
+}
diff --git a/board/MAI/AmigaOneG3SE/board_asm_init.S b/board/MAI/AmigaOneG3SE/board_asm_init.S
new file mode 100755
index 0000000..086b19c
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/board_asm_init.S
@@ -0,0 +1,156 @@
+#include	"macros.h"
+
+
+#define GLOBALINFO0	      0x50
+#define GLOBALINFO0_BO        (1<<7)
+#define GLOBALINFO2_B1ARBITER (1<<6)
+#define HBUSACR0              0x5c
+#define HBUSACR2_BURST        (1<<0)
+#define HBUSACR2_LAT          (1<<1)
+
+#define RECEIVER_HOLDING 0
+#define TRANSMITTER_HOLDING 0
+#define INTERRUPT_ENABLE 1
+#define INTERRUPT_STATUS 2
+#define FIFO_CONTROL 2
+#define LINE_CONTROL 3
+#define MODEM_CONTROL 4
+#define LINE_STATUS 5
+#define MODEM_STATUS 6
+#define SCRATCH_PAD 7
+
+#define DIVISOR_LATCH_LSB 0
+#define DIVISOR_LATCH_MSB 1
+#define PRESCALER_DIVISION 5
+
+#define UART(x) (0x3f8+(x))
+
+#define GLOBALINFO0           0x50
+#define GLOBALINFO0_BO        (1<<7)
+#define GLOBALINFO2_B1ARBITER (1<<6)
+#define HBUSACR0              0x5c
+#define HBUSACR2_BURST        (1<<0)
+#define HBUSACR2_LAT          (1<<1)
+
+#define SUPERIO_1               ((7 << 3) | (0))
+#define SUPERIO_2               ((7 << 3) | (1))
+
+	.globl	board_asm_init
+
+board_asm_init:
+	mflr	r29
+	/* Set 'Must-set' register */
+	li	r3, 0
+	li	r4, 0
+	li	r5, 0x5e
+	bl	pci_read_cfg_byte
+	ori	r3, r3, (1<<1)
+	xori	r6, r3, (1<<1)
+	li	r3, 0
+	bl	pci_write_cfg_byte
+
+	li	r3, 0
+	li	r5, 0x52
+	bl	pci_read_cfg_byte
+	ori	r6, r3, (1<<6)
+	li	r3, 0
+	bl	pci_write_cfg_byte
+
+	li	r3, 0
+	li	r4, 0x08
+	li	r5, 0xd2
+	bl	pci_read_cfg_byte
+	ori	r6, r3, (1<<2)
+	li	r3, 0
+	bl	pci_write_cfg_byte
+
+
+	/* Do PCI reset */
+/*	li	r3, 0
+	li	r4, 0x38
+	li	r5, 0x47
+	bl	pci_read_cfg_byte
+	ori	r6, r3, 0x01
+	li	r3, 0
+	li	r4, 0x38
+	li	r5, 0x47
+	bl	pci_write_cfg_byte*/
+
+
+	/* Enable NVRAM for environment */
+	li	r3, 0
+	li	r4, 0
+	li	r5, 0x56
+	li	r6, 0x0B
+	bl	pci_write_cfg_byte
+
+
+	/* Init Super-I/O chips */
+
+	siowb	0x40, 0x08
+	siowb	0x41, 0x01
+	siowb	0x45, 0x80
+	siowb	0x46, 0x60
+	siowb	0x47, 0x20
+	siowb	0x48, 0x01
+	siowb	0x4a, 0xc4
+	siowb	0x50, 0x0e
+	siowb	0x51, 0x76
+	siowb	0x52, 0x34
+	siowb	0x54, 0x00
+	siowb	0x55, 0x90
+	siowb	0x56, 0x99
+	siowb	0x57, 0x90
+	siowb	0x85, 0x01
+
+	/* Enable configuration mode for SuperIO */
+	li	r3, 0
+	li	r4, (7<<3)
+	li	r5, 0x85
+	bl	pci_read_cfg_byte
+	ori	r6, r3, 0x02
+	mr	r31, r6
+	li	r3,0
+	bl	pci_write_cfg_byte
+
+	/* COM1 as 3f8 */
+	outb	0x3f0, 0xe7
+	outb	0x3f1, 0xfe
+
+	/* COM2 as 2f8 */
+	outb	0x3f0, 0xe8
+	outb	0x3f1, 0xeb
+
+	/* Enable */
+	outb	0x3f0, 0xe2
+	inb	r3, 0x3f1
+	ori	r3, r3, 0x0c
+	outb	0x3f0, 0xe2
+	outbr	0x3f1, r3
+
+	/* Disable configuration mode */
+	li	r3, 0
+	li	r4, (7<<3)
+	li	r5, 0x85
+	mr	r6, r31
+	bl	pci_write_cfg_byte
+
+	/* Set line control */
+	outb	UART(LINE_CONTROL), 0x83
+	outb	UART(DIVISOR_LATCH_LSB), 0x0c
+	outb	UART(DIVISOR_LATCH_MSB), 0x00
+	outb	UART(LINE_CONTROL), 0x3
+
+	mtlr	r29
+	blr
+
+
+	.globl	new_reset
+	.globl	new_reset_end
+new_reset:
+	li	r0, 0x100
+	oris	r0, r0, 0xFFF0
+	mtlr	r0
+	blr
+
+new_reset_end:
diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c
new file mode 100755
index 0000000..3e2835a
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/cmd_boota.c
@@ -0,0 +1,129 @@
+#include <common.h>
+#include <command.h>
+#include "../disk/part_amiga.h"
+#include <asm/cache.h>
+
+
+#undef BOOTA_DEBUG
+
+#ifdef BOOTA_DEBUG
+#define PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+struct block_header {
+	u32 id;
+	u32 summed_longs;
+	s32 chk_sum;
+};
+
+extern block_dev_desc_t *ide_get_dev (int dev);
+extern struct bootcode_block *get_bootcode (block_dev_desc_t * dev_desc);
+extern int sum_block (struct block_header *header);
+
+struct bootcode_block bblk;
+
+int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR;
+	unsigned char *base_address;
+	unsigned long offset;
+
+	unsigned long part_number = 0;
+	block_dev_desc_t *boot_disk;
+	char *s;
+	struct bootcode_block *boot_code;
+
+	/* Get parameters */
+
+	switch (argc) {
+	case 2:
+		load_address = (unsigned char *) simple_strtol (argv[1], NULL, 16);
+		part_number = 0;
+		break;
+	case 3:
+		load_address = (unsigned char *) simple_strtol (argv[1], NULL, 16);
+		part_number = simple_strtol (argv[2], NULL, 16);
+		break;
+	}
+
+	base_address = load_address;
+
+	PRINTF ("Loading boot code from disk %d to %p\n", part_number,
+			load_address);
+
+	/* Find the appropriate disk device */
+	boot_disk = ide_get_dev (part_number);
+	if (!boot_disk) {
+		PRINTF ("Unknown disk %d\n", part_number);
+		return 1;
+	}
+
+	/* Find the bootcode block */
+	boot_code = get_bootcode (boot_disk);
+	if (!boot_code) {
+		PRINTF ("Not a bootable disk %d\n", part_number);
+		return 1;
+	}
+
+	/* Only use the offset from the first block */
+	offset = boot_code->load_data[0];
+	memcpy (load_address, &boot_code->load_data[1], 122 * 4);
+	load_address += 122 * 4;
+
+	/* Setup for the loop */
+	bblk.next = boot_code->next;
+	boot_code = &bblk;
+
+	/* Scan the chain, and copy the loader succesively into the destination area */
+	while (0xffffffff != boot_code->next) {
+		PRINTF ("Loading block %d\n", boot_code->next);
+
+		/* Load block */
+		if (1 !=
+			boot_disk->block_read (boot_disk->dev, boot_code->next, 1,
+								   (ulong *) & bblk)) {
+			PRINTF ("Read error\n");
+			return 1;
+		}
+
+		/* check sum */
+		if (sum_block ((struct block_header *) (ulong *) & bblk) != 0) {
+			PRINTF ("Checksum error\n");
+			return 1;
+		}
+
+		/* Ok, concatenate it to the already loaded code */
+		memcpy (load_address, boot_code->load_data, 123 * 4);
+		load_address += 123 * 4;
+	}
+
+	printf ("Bootcode loaded to %p (size %d)\n", base_address,
+			load_address - base_address);
+	printf ("Entry point at %p\n", base_address + offset);
+
+	flush_cache (base_address, load_address - base_address);
+
+
+	s = getenv ("autostart");
+	if (s && strcmp (s, "yes") == 0) {
+		DECLARE_GLOBAL_DATA_PTR;
+
+		void (*boot) (bd_t *, char *, block_dev_desc_t *);
+		char *args;
+
+		boot = (void (*)(bd_t *, char *, block_dev_desc_t *)) (base_address + offset);
+		boot (gd->bd, getenv ("amiga_bootargs"), boot_disk);
+	}
+
+
+	return 0;
+}
+#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
+U_BOOT_CMD(
+	boota,   3,      1,      do_boota,
+	"boota   - boot an Amiga kernel\n",
+	"address disk"
+);
+#endif /* _CMD_BOOTA_H */
diff --git a/board/MAI/AmigaOneG3SE/config.mk b/board/MAI/AmigaOneG3SE/config.mk
new file mode 100755
index 0000000..930a793
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AmigaOneG3SE boards
+#
+
+X86EMU =  -I../bios_emulator/scitech/include -I../bios_emulator/scitech/src/x86emu
+
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) -Dprintk=printf #-DDEBUG
diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c
new file mode 100755
index 0000000..d4be889
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/enet.c
@@ -0,0 +1,884 @@
+/*
+ * (C) Copyright 2002
+ * Adam Kowalczyk, ACK Software Controls Inc. akowalczyk@cogeco.ca
+ *
+ * Some portions taken from 3c59x.c Written 1996-1999 by Donald Becker.
+ *
+ * Outline of the program based on eepro100.c which is
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include "articiaS.h"
+#include "memio.h"
+
+/* 3Com Ethernet PCI definitions*/
+
+/* #define PCI_VENDOR_ID_3COM		0x10B7 */
+#define PCI_DEVICE_ID_3COM_3C905C	0x9200
+
+/* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
+
+#define TotalReset 		(0<<11)
+#define SelectWindow 		(1<<11)
+#define StartCoax 		(2<<11)
+#define RxDisable 		(3<<11)
+#define RxEnable 		(4<<11)
+#define RxReset 		(5<<11)
+#define UpStall 		(6<<11)
+#define UpUnstall 		(6<<11)+1
+#define DownStall 		(6<<11)+2
+#define DownUnstall 		(6<<11)+3
+#define RxDiscard 		(8<<11)
+#define TxEnable 		(9<<11)
+#define TxDisable 		(10<<11)
+#define TxReset 		(11<<11)
+#define FakeIntr 		(12<<11)
+#define AckIntr 		(13<<11)
+#define SetIntrEnb 		(14<<11)
+#define SetStatusEnb 		(15<<11)
+#define SetRxFilter 		(16<<11)
+#define SetRxThreshold 		(17<<11)
+#define SetTxThreshold 		(18<<11)
+#define SetTxStart 		(19<<11)
+#define StartDMAUp 		(20<<11)
+#define StartDMADown 		(20<<11)+1
+#define StatsEnable		(21<<11)
+#define StatsDisable		(22<<11)
+#define StopCoax 		(23<<11)
+#define SetFilterBit 		(25<<11)
+
+/* The SetRxFilter command accepts the following classes */
+
+#define RxStation 		1
+#define RxMulticast		2
+#define RxBroadcast		4
+#define RxProm 			8
+
+/* 3Com status word defnitions */
+
+#define IntLatch 		0x0001
+#define HostError 		0x0002
+#define TxComplete 		0x0004
+#define TxAvailable 		0x0008
+#define RxComplete 		0x0010
+#define RxEarly 		0x0020
+#define IntReq 			0x0040
+#define StatsFull 		0x0080
+#define DMADone 		(1<<8)
+#define DownComplete 		(1<<9)
+#define UpComplete 		(1<<10)
+#define DMAInProgress 		(1<<11)			/* DMA controller is still busy.*/
+#define CmdInProgress 		(1<<12)           	/* EL3_CMD is still busy.*/
+
+/* Polling Registers */
+
+#define DnPoll			0x2d
+#define UpPoll			0x3d
+
+/* Register window 0 offets */
+
+#define Wn0EepromCmd 		10	          	/* Window 0: EEPROM command register. */
+#define Wn0EepromData 		12             		/* Window 0: EEPROM results register. */
+#define IntrStatus		0x0E	                /* Valid in all windows. */
+
+/* Register window 0 EEPROM bits */
+
+#define EEPROM_Read 		0x80
+#define EEPROM_WRITE 		0x40
+#define EEPROM_ERASE 		0xC0
+#define EEPROM_EWENB 		0x30            	/* Enable erasing/writing for 10 msec. */
+#define EEPROM_EWDIS 		0x00            	/* Disable EWENB before 10 msec timeout. */
+
+/* EEPROM locations. */
+
+#define PhysAddr01		0
+#define PhysAddr23		1
+#define PhysAddr45		2
+#define ModelID			3
+#define EtherLink3ID		7
+#define IFXcvrIO		8
+#define IRQLine			9
+#define NodeAddr01		10
+#define NodeAddr23		11
+#define NodeAddr45		12
+#define DriverTune		13
+#define Checksum		15
+
+/* Register window 1 offsets, the window used in normal operation */
+
+#define TX_FIFO 		0x10
+#define RX_FIFO 		0x10
+#define RxErrors 		0x14
+#define RxStatus 		0x18
+#define Timer			0x1A
+#define TxStatus 		0x1B
+#define TxFree 			0x1C	 		/* Remaining free bytes in Tx buffer. */
+
+/* Register Window 2 */
+
+#define Wn2_ResetOptions	12
+
+/* Register Window 3: MAC/config bits */
+
+#define Wn3_Config		0			/* Internal Configuration */
+#define Wn3_MAC_Ctrl		6
+#define Wn3_Options		8
+
+#define BFEXT(value, offset, bitcount)  					\
+	((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
+
+#define BFINS(lhs, rhs, offset, bitcount)                                       \
+	(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) |   		\
+	(((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
+
+#define RAM_SIZE(v)             BFEXT(v, 0, 3)
+#define RAM_WIDTH(v)    	BFEXT(v, 3, 1)
+#define RAM_SPEED(v)    	BFEXT(v, 4, 2)
+#define ROM_SIZE(v)             BFEXT(v, 6, 2)
+#define RAM_SPLIT(v)    	BFEXT(v, 16, 2)
+#define XCVR(v)                 BFEXT(v, 20, 4)
+#define AUTOSELECT(v)   	BFEXT(v, 24, 1)
+
+/* Register Window 4: Xcvr/media bits */
+
+#define Wn4_FIFODiag 		4
+#define Wn4_NetDiag 		6
+#define Wn4_PhysicalMgmt	8
+#define Wn4_Media 		10
+
+#define Media_SQE 		0x0008     		/* Enable SQE error counting for AUI. */
+#define Media_10TP 		0x00C0			/* Enable link beat and jabber for 10baseT. */
+#define Media_Lnk 		0x0080			/* Enable just link beat for 100TX/100FX. */
+#define Media_LnkBeat 		0x0800
+
+/* Register Window 7: Bus Master control */
+
+#define Wn7_MasterAddr 		0
+#define Wn7_MasterLen 		6
+#define Wn7_MasterStatus 	12
+
+/* Boomerang bus master control registers. */
+
+#define PktStatus 		0x20
+#define DownListPtr		0x24
+#define FragAddr 		0x28
+#define FragLen 		0x2c
+#define TxFreeThreshold 	0x2f
+#define UpPktStatus 		0x30
+#define UpListPtr 		0x38
+
+/* The Rx and Tx descriptor lists. */
+
+#define LAST_FRAG       0x80000000                      /* Last Addr/Len pair in descriptor. */
+#define DN_COMPLETE     0x00010000                      /* This packet has been downloaded */
+
+struct rx_desc_3com {
+	u32 next;                                       /* Last entry points to 0	   	*/
+	u32 status;					/* FSH -> Frame Start Header 		*/
+	u32 addr;                                       /* Up to 63 addr/len pairs possible 	*/
+	u32 length;                                     /* Set LAST_FRAG to indicate last pair	*/
+};
+
+/* Values for the Rx status entry. */
+
+#define RxDComplete		0x00008000
+#define RxDError		0x4000
+#define IPChksumErr		(1<<25)
+#define TCPChksumErr		(1<<26)
+#define UDPChksumErr		(1<<27)
+#define IPChksumValid		(1<<29)
+#define TCPChksumValid		(1<<30)
+#define UDPChksumValid		(1<<31)
+
+struct tx_desc_3com {
+	u32 next;                                       /* Last entry points to 0		*/
+	u32 status;                                     /* bits 0:12 length, others see below	*/
+	u32 addr;
+	u32 length;
+};
+
+/* Values for the Tx status entry. */
+
+#define CRCDisable		0x2000
+#define TxDComplete		0x8000
+#define AddIPChksum		0x02000000
+#define AddTCPChksum		0x04000000
+#define AddUDPChksum		0x08000000
+#define TxIntrUploaded		0x80000000              /* IRQ when in FIFO, but maybe not sent. */
+
+/* XCVR Types */
+
+#define XCVR_10baseT		0
+#define XCVR_AUI		1
+#define XCVR_10baseTOnly	2
+#define XCVR_10base2		3
+#define XCVR_100baseTx		4
+#define XCVR_100baseFx		5
+#define XCVR_MII		6
+#define XCVR_NWAY		8
+#define XCVR_ExtMII		9
+#define XCVR_Default		10			/* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
+
+struct descriptor {			    		/* A generic descriptor. */
+	u32 next;                                       /* Last entry points to 0	   	*/
+	u32 status;					/* FSH -> Frame Start Header 		*/
+	u32 addr;                                       /* Up to 63 addr/len pairs possible 	*/
+	u32 length;                                     /* Set LAST_FRAG to indicate last pair	*/
+};
+
+/* Misc. definitions */
+
+#define NUM_RX_DESC 		PKTBUFSRX * 10
+#define NUM_TX_DESC 		1            /* Number of TX descriptors   */
+
+#define TOUT_LOOP		1000000
+
+#define ETH_ALEN		6
+
+#define EL3WINDOW(dev, win_num) ETH_OUTW(dev, SelectWindow + (win_num), EL3_CMD)
+#define EL3_CMD 0x0e
+#define EL3_STATUS 0x0e
+
+
+#undef ETH_DEBUG
+
+#ifdef ETH_DEBUG
+#define PRINTF(fmt,args...)     printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+
+static struct rx_desc_3com *rx_ring;		 	/* RX descriptor ring         		*/
+static struct tx_desc_3com *tx_ring;		 	/* TX descriptor ring         		*/
+static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN];	/* storage for the incoming messages 	*/
+static int rx_next = 0;                      		/* RX descriptor ring pointer 		*/
+static int tx_next = 0;                      		/* TX descriptor ring pointer 		*/
+static int tx_threshold;
+
+static void  init_rx_ring(struct eth_device* dev);
+static void  purge_tx_ring(struct eth_device* dev);
+
+static void  read_hw_addr(struct eth_device* dev, bd_t * bis);
+
+static int eth_3com_init(struct eth_device* dev, bd_t *bis);
+static int eth_3com_send(struct eth_device* dev, volatile void *packet, int length);
+static int eth_3com_recv(struct eth_device* dev);
+static void eth_3com_halt(struct eth_device* dev);
+
+#define io_to_phys(a)	pci_io_to_phys((pci_dev_t)dev->priv, a)
+#define phys_to_io(a)	pci_phys_to_io((pci_dev_t)dev->priv, a)
+#define mem_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, a)
+#define phys_to_mem(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
+
+static inline int ETH_INL(struct eth_device* dev, u_long addr)
+{
+    __asm volatile ("eieio");
+	return le32_to_cpu(*(volatile u32 *)io_to_phys(addr + dev->iobase));
+}
+
+static inline int ETH_INW(struct eth_device* dev, u_long addr)
+{
+    __asm volatile ("eieio");
+	return le16_to_cpu(*(volatile u16 *)io_to_phys(addr + dev->iobase));
+}
+
+static inline int ETH_INB(struct eth_device* dev, u_long addr)
+{
+    __asm volatile ("eieio");
+	return *(volatile u8 *)io_to_phys(addr + dev->iobase);
+}
+
+static inline void ETH_OUTB(struct eth_device* dev, int command, u_long addr)
+{
+	*(volatile u8 *)io_to_phys(addr + dev->iobase) = command;
+    __asm volatile ("eieio");
+}
+
+static inline void ETH_OUTW(struct eth_device* dev, int command, u_long addr)
+{
+	*(volatile u16 *)io_to_phys(addr + dev->iobase) = cpu_to_le16(command);
+    __asm volatile ("eieio");
+}
+
+static inline void ETH_OUTL(struct eth_device* dev, int command, u_long addr)
+{
+	*(volatile u32 *)io_to_phys(addr + dev->iobase) = cpu_to_le32(command);
+    __asm volatile ("eieio");
+}
+
+static inline int ETH_STATUS(struct eth_device* dev)
+{
+    __asm volatile ("eieio");
+	return le16_to_cpu(*(volatile u16 *)io_to_phys(EL3_STATUS + dev->iobase));
+}
+
+static inline void ETH_CMD(struct eth_device* dev, int command)
+{
+	*(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command);
+    __asm volatile ("eieio");
+}
+
+/* Command register is always in the same spot in all the register windows */
+/* This function issues a command and waits for it so complete by checking the CmdInProgress bit */
+
+static int issue_and_wait(struct eth_device* dev, int command)
+{
+
+	int i, status;
+
+	ETH_CMD(dev, command);
+	for (i = 0; i < 2000; i++) {
+		status = ETH_STATUS(dev);
+		/*printf ("Issue: status 0x%4x.\n", status); */
+		if (!(status & CmdInProgress))
+			return 1;
+	}
+
+	/* OK, that didn't work.  Do it the slow way.  One second */
+	for (i = 0; i < 100000; i++) {
+		status = ETH_STATUS(dev);
+		/*printf ("Issue: status 0x%4x.\n", status); */
+			return 1;
+		udelay(10);
+	}
+	PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
+	return 0;
+}
+
+/* Determine network media type and set up 3com accordingly           */
+/* I think I'm going to start with something known first like 10baseT */
+
+static int auto_negotiate(struct eth_device* dev)
+{
+    int i;
+
+    EL3WINDOW(dev, 1);
+
+    /* Wait for Auto negotiation to complete */
+    for (i = 0; i <= 1000; i++)
+    {
+	if (ETH_INW(dev, 2) & 0x04)
+	    break;
+	udelay(100);
+
+	if (i == 1000)
+	{
+	    PRINTF("Error: Auto negotiation failed\n");
+	    return 0;
+	}
+    }
+
+
+    return 1;
+}
+
+void eth_interrupt(struct eth_device *dev)
+{
+    u16 status = ETH_STATUS(dev);
+
+    printf("eth0: status = 0x%04x\n", status);
+
+    if (!(status & IntLatch))
+	return;
+
+    if (status & (1<<6))
+    {
+	ETH_CMD(dev, AckIntr | (1<<6));
+	printf("Acknowledged Interrupt command\n");
+    }
+
+    if (status & DownComplete)
+    {
+	ETH_CMD(dev, AckIntr | DownComplete);
+	printf("Acknowledged DownComplete\n");
+    }
+
+    if (status & UpComplete)
+    {
+	ETH_CMD(dev, AckIntr | UpComplete);
+	printf("Acknowledged UpComplete\n");
+    }
+
+    ETH_CMD(dev, AckIntr | IntLatch);
+    printf("Acknowledged IntLatch\n");
+}
+
+int eth_3com_initialize(bd_t *bis)
+{
+	u32 eth_iobase = 0, status;
+	int card_number = 0, ret;
+	struct eth_device* dev;
+	pci_dev_t devno;
+	char *s;
+
+	s = getenv("3com_base");
+
+	/* Find ethernet controller on the PCI bus */
+
+	if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0)
+	{
+		PRINTF("Error: Cannot find the ethernet device on the PCI bus\n");
+		goto Done;
+	}
+
+	if (s)
+	{
+	    unsigned long base = atoi(s);
+	    pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01);
+	}
+
+	ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &eth_iobase);
+	eth_iobase &= ~0xf;
+
+	PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
+
+	pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	 /* Check if I/O accesses and Bus Mastering are enabled */
+
+	ret = pci_read_config_dword(devno, PCI_COMMAND, &status);
+
+	if (!(status & PCI_COMMAND_IO))
+	{
+		printf("Error: Cannot enable IO access.\n");
+		goto Done;
+	}
+
+	if (!(status & PCI_COMMAND_MEMORY))
+	{
+		printf("Error: Cannot enable MEMORY access.\n");
+		goto Done;
+	}
+
+	if (!(status & PCI_COMMAND_MASTER))
+	{
+		printf("Error: Cannot enable Bus Mastering.\n");
+		goto Done;
+	}
+
+	dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */
+
+	sprintf(dev->name, "3Com 3c920c#%d", card_number);
+	dev->iobase = eth_iobase;
+	dev->priv   = (void*) devno;
+	dev->init   = eth_3com_init;
+	dev->halt   = eth_3com_halt;
+	dev->send   = eth_3com_send;
+	dev->recv   = eth_3com_recv;
+
+	eth_register(dev);
+
+/* 	{ */
+/* 	    char interrupt; */
+/* 	    devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
+/* 	    pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
+
+/* 	    printf("Installing eth0 interrupt handler to %d\n", interrupt); */
+/* 	    irq_install_handler(interrupt, eth_interrupt, dev); */
+/* 	} */
+
+	card_number++;
+
+	/* Set the latency timer for value */
+	s = getenv("3com_latency");
+	if (s)
+	{
+	    ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s));
+	}
+	else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a);
+
+	read_hw_addr(dev, bis); 				/* get the MAC address from Window 2*/
+
+	/* Reset the ethernet controller */
+
+	PRINTF ("Issuing reset command....\n");
+	if (!issue_and_wait(dev, TotalReset))
+	{
+		printf("Error: Cannot reset ethernet controller.\n");
+		goto Done;
+	}
+	else
+		PRINTF ("Ethernet controller reset.\n");
+
+	/* allocate memory for rx and tx rings */
+
+	if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16)))
+	{
+		PRINTF ("Cannot allocate memory for RX_RING.....\n");
+		goto Done;
+	}
+
+	if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
+	{
+		PRINTF ("Cannot allocate memory for TX_RING.....\n");
+		goto Done;
+	}
+
+Done:
+	return status;
+}
+
+
+static int eth_3com_init(struct eth_device* dev, bd_t *bis)
+{
+	int i, status = 0;
+	int tx_cur, loop;
+	u16 status_enable, intr_enable;
+	struct descriptor *ias_cmd;
+
+	/* Determine what type of network the machine is connected to	*/
+	/* presently drops the connect to 10Mbps			*/
+
+	if (!auto_negotiate(dev))
+	{
+		printf("Error: Cannot determine network media.\n");
+		goto Done;
+	}
+
+	issue_and_wait(dev, TxReset);
+	issue_and_wait(dev, RxReset|0x04);
+
+	/* Switch to register set 7 for normal use. */
+	EL3WINDOW(dev, 7);
+
+	/* Initialize Rx and Tx rings */
+
+	init_rx_ring(dev);
+	purge_tx_ring(dev);
+
+	ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
+
+	issue_and_wait(dev,SetTxStart|0x07ff);
+
+	/* Below sets which indication bits to be seen. */
+
+	status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
+	ETH_CMD(dev, status_enable);
+
+	/* Below sets no bits are to cause an interrupt since this is just polling */
+
+	intr_enable   = SetIntrEnb;
+/*	intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
+	ETH_CMD(dev, intr_enable);
+	ETH_OUTB(dev, 127, UpPoll);
+
+	/* Ack all pending events, and set active indicator mask */
+
+	ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
+	ETH_CMD(dev, intr_enable);
+
+	/* Tell the adapter where the RX ring is located */
+
+	issue_and_wait(dev,UpStall);				/* Stall and set the UplistPtr 		*/
+	ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
+	ETH_CMD(dev, RxEnable); 				/* Enable the receiver. 		*/
+	issue_and_wait(dev,UpUnstall);
+
+	/* Send the Individual Address Setup frame */
+
+	tx_cur       = tx_next;
+	tx_next      = ((tx_next+1) % NUM_TX_DESC);
+
+	ias_cmd             = (struct descriptor *)&tx_ring[tx_cur];
+	ias_cmd->status     = cpu_to_le32(1<<31);		/* set DnIndicate bit. 			*/
+	ias_cmd->next       = 0;
+	ias_cmd->addr       = cpu_to_le32((u32)&bis->bi_enetaddr[0]);
+	ias_cmd->length     = cpu_to_le32(6 | LAST_FRAG);
+
+	/* Tell the adapter where the TX ring is located */
+
+	ETH_CMD(dev, TxEnable); 				/* Enable transmitter. 			*/
+	issue_and_wait(dev, DownStall);				/* Stall and set the DownListPtr. 	*/
+	ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
+	issue_and_wait(dev, DownUnstall);
+	for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
+	{
+		if (i >= TOUT_LOOP)
+		{
+			PRINTF("TX Ring status (Init):  0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
+			PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev));
+			goto Done;
+		}
+	}
+	if (ETH_STATUS(dev) & DownComplete)			/* If DownLoad Complete ACK the bit 	*/
+	{
+		ETH_CMD(dev, AckIntr | DownComplete);		/* acknowledge the indication bit	*/
+		issue_and_wait(dev, DownStall);			/* stall and clear DownListPtr 		*/
+		ETH_OUTL(dev, 0, DownListPtr);
+		issue_and_wait(dev, DownUnstall);
+	}
+	status = 1;
+
+Done:
+	return status;
+}
+
+int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
+{
+	int i, status = 0;
+	int tx_cur;
+
+	if (length <= 0)
+	{
+		PRINTF("eth: bad packet size: %d\n", length);
+		goto Done;
+	}
+
+	tx_cur  = tx_next;
+	tx_next = (tx_next+1) % NUM_TX_DESC;
+
+	tx_ring[tx_cur].status  = cpu_to_le32(1<<31);		/* set DnIndicate bit 			*/
+	tx_ring[tx_cur].next    = 0;
+	tx_ring[tx_cur].addr    = cpu_to_le32(((u32) packet));
+	tx_ring[tx_cur].length  = cpu_to_le32(length | LAST_FRAG);
+
+	/* Send the packet */
+
+	issue_and_wait(dev, DownStall);				/* stall and set the DownListPtr 	*/
+	ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr);
+	issue_and_wait(dev, DownUnstall);
+
+	for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
+	{
+		if (i >= TOUT_LOOP)
+		{
+			PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
+			goto Done;
+		}
+	}
+	if (ETH_STATUS(dev) & DownComplete)			/* If DownLoad Complete ACK the bit 	*/
+	{
+		ETH_CMD(dev, AckIntr | DownComplete);		/* acknowledge the indication bit	*/
+		issue_and_wait(dev, DownStall);			/* stall and clear DownListPtr 		*/
+		ETH_OUTL(dev, 0, DownListPtr);
+		issue_and_wait(dev, DownUnstall);
+	}
+	status=1;
+ Done:
+	return status;
+}
+
+void PrintPacket (uchar *packet, int length)
+{
+int loop;
+uchar *ptr;
+
+	printf ("Printing packet of length %x.\n\n", length);
+	ptr = packet;
+	for (loop = 1; loop <= length; loop++)
+	{
+		printf ("%2x ", *ptr++);
+		if ((loop % 40)== 0)
+			printf ("\n");
+	}
+}
+
+int eth_3com_recv(struct eth_device* dev)
+{
+	u16 stat = 0;
+	u32 status;
+	int rx_prev, length = 0;
+
+	while (!(ETH_STATUS(dev) & UpComplete))			/* wait on receipt of packet 	*/
+		;
+
+	status = le32_to_cpu(rx_ring[rx_next].status);		/* packet status		*/
+
+	while (status & (1<<15))
+	{
+		/* A packet has been received */
+
+		if (status & (1<<15))
+		{
+			/* A valid frame received  */
+
+			length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff;		/* length is in bits 0 - 12 	*/
+
+			/* Pass the packet up to the protocol layers */
+
+			NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
+			rx_ring[rx_next].status = 0;					/* clear the status word 	*/
+			ETH_CMD(dev, AckIntr | UpComplete);
+			issue_and_wait(dev, UpUnstall);
+		}
+		else
+		if (stat & HostError)
+		{
+			/* There was an error */
+
+			printf("Rx error status:  0x%4x\n", stat);
+			init_rx_ring(dev);
+			goto Done;
+		}
+
+		rx_prev = rx_next;
+		rx_next = (rx_next + 1) % NUM_RX_DESC;
+		stat = ETH_STATUS(dev);					/* register status 	*/
+		status = le32_to_cpu(rx_ring[rx_next].status);		/* packet status 	*/
+	}
+
+Done:
+	return length;
+}
+
+void eth_3com_halt(struct eth_device* dev)
+{
+	if (!(dev->iobase))
+	{
+		goto Done;
+	}
+
+	issue_and_wait(dev, DownStall);		/* shut down transmit and receive */
+	issue_and_wait(dev, UpStall);
+	issue_and_wait(dev, RxDisable);
+	issue_and_wait(dev, TxDisable);
+
+/*	free(tx_ring);				/###* release memory allocated to the DPD and UPD rings */
+/*	free(rx_ring); */
+
+Done:
+	return;
+}
+
+static void init_rx_ring(struct eth_device* dev)
+{
+	int i;
+
+	PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
+	issue_and_wait(dev, UpStall);
+
+	for (i = 0; i < NUM_RX_DESC; i++)
+	{
+		rx_ring[i].next    = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
+		rx_ring[i].status  = 0;
+		rx_ring[i].addr    = cpu_to_le32(((u32) &rx_buffer[i][0]));
+		rx_ring[i].length  = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG);
+	}
+	rx_next = 0;
+}
+
+static void purge_tx_ring(struct eth_device* dev)
+{
+	int i;
+
+	PRINTF("Purging tx_ring.\n");
+
+	tx_next      = 0;
+
+	for (i = 0; i < NUM_TX_DESC; i++)
+	{
+		tx_ring[i].next    = 0;
+		tx_ring[i].status  = 0;
+		tx_ring[i].addr    = 0;
+		tx_ring[i].length  = 0;
+	}
+}
+
+static void read_hw_addr(struct eth_device* dev, bd_t *bis)
+{
+	u8 hw_addr[ETH_ALEN];
+	unsigned int eeprom[0x40];
+	unsigned int checksum = 0;
+	int i, j, timer;
+
+	/* Read the station address from the EEPROM. */
+
+	EL3WINDOW(dev, 0);
+	for (i = 0; i < 0x40; i++)
+	{
+		ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
+		/* Pause for at least 162 us. for the read to take place. */
+		for (timer = 10; timer >= 0; timer--)
+		{
+			udelay(162);
+			if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
+				break;
+		}
+		eeprom[i] = ETH_INW(dev, Wn0EepromData);
+	}
+
+	/* Checksum calculation.  I'm not sure about this part and there seems to be a bug on the 3com side of things */
+
+	for (i = 0; i < 0x21; i++)
+		checksum  ^= eeprom[i];
+	checksum = (checksum ^ (checksum >> 8)) & 0xff;
+
+	if (checksum != 0xbb)
+		printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
+
+	for (i = 0, j = 0; i < 3; i++)
+	{
+		hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
+		hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
+	}
+
+	/*  MAC Address is in window 2, write value from EEPROM to window 2 */
+
+	EL3WINDOW(dev, 2);
+	for (i = 0; i < 6; i++)
+		ETH_OUTB(dev, hw_addr[i], i);
+
+	for (j = 0; j < ETH_ALEN; j+=2)
+	{
+		hw_addr[j]   = (u8)(ETH_INW(dev, j) & 0xff);
+		hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
+	}
+
+	for (i=0;i<ETH_ALEN;i++)
+	{
+		if (hw_addr[i] != bis->bi_enetaddr[i])
+		{
+/* 			printf("Warning: HW address don't match:\n"); */
+/* 			printf("Address in 3Com Window 2 is         " */
+/* 			       "%02X:%02X:%02X:%02X:%02X:%02X\n", */
+/* 			       hw_addr[0], hw_addr[1], hw_addr[2], */
+/* 			       hw_addr[3], hw_addr[4], hw_addr[5]); */
+/* 			printf("Address used by U-Boot is " */
+/* 			       "%02X:%02X:%02X:%02X:%02X:%02X\n", */
+/* 			       bis->bi_enetaddr[0], bis->bi_enetaddr[1],  */
+/* 			       bis->bi_enetaddr[2], bis->bi_enetaddr[3],  */
+/* 			       bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
+/* 			goto Done; */
+		    char buffer[256];
+		    if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 &&
+			bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 &&
+			bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
+		    {
+
+			sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
+				hw_addr[0], hw_addr[1], hw_addr[2],
+				hw_addr[3], hw_addr[4], hw_addr[5]);
+			setenv("ethaddr", buffer);
+		    }
+		}
+	}
+
+	for(i=0; i<ETH_ALEN; i++) dev->enetaddr[i] = hw_addr[i];
+
+Done:
+	return;
+}
diff --git a/board/MAI/AmigaOneG3SE/flash.c b/board/MAI/AmigaOneG3SE/flash.c
new file mode 100755
index 0000000..409b955
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/flash.c
@@ -0,0 +1,35 @@
+#include <common.h>
+#include <flash.h>
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+
+unsigned long flash_init(void)
+{
+    int i;
+
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+	flash_info[i].sector_count = 0;
+	flash_info[i].size = 0;
+    }
+
+
+    return 1;
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+    return 1;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+    printf("No flashrom installed\n");
+}
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    return 0;
+}
diff --git a/board/MAI/AmigaOneG3SE/flash_new.c b/board/MAI/AmigaOneG3SE/flash_new.c
new file mode 100755
index 0000000..d46bf46
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/flash_new.c
@@ -0,0 +1,651 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <asm/io.h>
+#include "memio.h"
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+
+static ulong flash_get_size (ulong addr, flash_info_t *info);
+static int flash_get_offsets (ulong base, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_reset (ulong addr);
+
+int flash_xd_nest;
+
+static void flash_to_xd(void)
+{
+    unsigned char x;
+
+    flash_xd_nest ++;
+
+    if (flash_xd_nest == 1)
+    {
+	DEBUGF("Flash on XD\n");
+	x = pci_read_cfg_byte(0, 0, 0x74);
+	pci_write_cfg_byte(0, 0, 0x74, x|1);
+    }
+}
+
+static void flash_to_mem(void)
+{
+    unsigned char x;
+
+    flash_xd_nest --;
+
+    if (flash_xd_nest == 0)
+    {
+	DEBUGF("Flash on memory bus\n");
+	x = pci_read_cfg_byte(0, 0, 0x74);
+	pci_write_cfg_byte(0, 0, 0x74, x&0xFE);
+    }
+}
+
+unsigned long flash_init_old(void)
+{
+    int i;
+
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+	flash_info[i].sector_count = 0;
+	flash_info[i].size = 0;
+    }
+
+
+    return 1;
+}
+
+unsigned long flash_init (void)
+{
+	unsigned int i;
+	unsigned long flash_size = 0;
+
+	flash_xd_nest = 0;
+
+	flash_to_xd();
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = 0;
+		flash_info[i].size = 0;
+	}
+
+	DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE);
+
+	flash_size = flash_get_size (CFG_FLASH_BASE, flash_info);
+
+	DEBUGF("## Flash bank size: %08lx\n", flash_size);
+
+	if (flash_size) {
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
+    CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			      &flash_info[0]);
+#endif
+
+	} else {
+		puts ("Warning: the BOOT Flash is not initialised !");
+	}
+
+	flash_to_mem();
+
+	return flash_size;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (ulong addr, flash_info_t *info)
+{
+	short i;
+	uchar value;
+	uchar *x = (uchar *)addr;
+
+	flash_to_xd();
+
+	/* Write auto select command: read Manufacturer ID */
+	x[0x0555] =  0xAA;
+	__asm volatile ("sync\n eieio");
+	x[0x02AA] =  0x55;
+	__asm volatile ("sync\n eieio");
+	x[0x0555] =  0x90;
+	__asm volatile ("sync\n eieio");
+
+	value = x[0];
+	__asm volatile ("sync\n eieio");
+
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
+
+	switch (value | (value << 16)) {
+		case AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+
+		case FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+
+		case STM_MANUFACT:
+			info->flash_id = FLASH_MAN_STM;
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			flash_reset (addr);
+			return 0;
+	}
+
+	value = x[1];
+	__asm volatile ("sync\n eieio");
+
+	DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value);
+
+	switch (value) {
+		case AMD_ID_F040B:
+			DEBUGF("Am29F040B\n");
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;			/* => 512 kB		*/
+
+		case AMD_ID_LV040B:
+			DEBUGF("Am29LV040B\n");
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;			/* => 512 kB		*/
+
+		case AMD_ID_LV400T:
+			DEBUGF("Am29LV400T\n");
+			info->flash_id += FLASH_AM400T;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;			/* => 1 MB		*/
+
+		case AMD_ID_LV400B:
+			DEBUGF("Am29LV400B\n");
+			info->flash_id += FLASH_AM400B;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;			/* => 1 MB		*/
+
+		case AMD_ID_LV800T:
+			DEBUGF("Am29LV800T\n");
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;			/* => 2 MB		*/
+
+		case AMD_ID_LV800B:
+			DEBUGF("Am29LV400B\n");
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;			/* => 2 MB		*/
+
+		case AMD_ID_LV160T:
+			DEBUGF("Am29LV160T\n");
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;			/* => 4 MB		*/
+
+		case AMD_ID_LV160B:
+			DEBUGF("Am29LV160B\n");
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;			/* => 4 MB		*/
+
+		case AMD_ID_LV320T:
+			DEBUGF("Am29LV320T\n");
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;			/* => 8 MB		*/
+
+#if 0
+		/* Has the same ID as AMD_ID_LV320T, to be fixed */
+		case AMD_ID_LV320B:
+			DEBUGF("Am29LV320B\n");
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;			/* => 8 MB		*/
+#endif
+
+		case AMD_ID_LV033C:
+			DEBUGF("Am29LV033C\n");
+			info->flash_id += FLASH_AM033C;
+			info->sector_count = 64;
+			info->size = 0x01000000;
+			break;			/* => 16Mb		*/
+
+		case STM_ID_F040B:
+			DEBUGF("M29F040B\n");
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;			/* => 512 kB		*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			flash_reset (addr);
+			flash_to_mem();
+			return (0);		/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	if (! flash_get_offsets (addr, info)) {
+		flash_reset (addr);
+		flash_to_mem();
+		return 0;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		value = in8(info->start[i] + 2);
+		iobarrier_rw();
+		info->protect[i] = (value & 1) != 0;
+	}
+
+	/*
+	 * Reset bank to read mode
+	 */
+	flash_reset (addr);
+
+	flash_to_mem();
+
+	return (info->size);
+}
+
+static int flash_get_offsets (ulong base, flash_info_t *info)
+{
+	unsigned int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			/* set sector offsets for uniform sector type	*/
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base + i * info->size /
+							    info->sector_count;
+			}
+			break;
+		default:
+			return 0;
+	}
+
+	return 1;
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile ulong addr = info->start[0];
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	flash_to_xd();
+
+	if (s_first < 0 || s_first > s_last) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		flash_to_mem();
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		flash_to_mem();
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x555, 0x80);
+	iobarrier_rw();
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = info->start[sect];
+			out8(addr, 0x30);
+			iobarrier_rw();
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = info->start[l_sect];
+
+	DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT);
+
+	while ((in8(addr) & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			flash_reset (info->start[0]);
+			flash_to_mem();
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+		iobarrier_rw();
+	}
+
+DONE:
+	/* reset to read mode */
+	flash_reset (info->start[0]);
+	flash_to_mem();
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	flash_to_xd();
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			flash_to_mem();
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			flash_to_mem();
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		flash_to_mem();
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+
+	flash_to_mem();
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile ulong addr = info->start[0];
+	ulong start;
+	int i;
+
+	flash_to_xd();
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((in32(dest) & data) != data) {
+		flash_to_mem();
+		return (2);
+	}
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *)&data;
+		int flag = disable_interrupts();
+
+		out8(addr + 0x555, 0xAA);
+		iobarrier_rw();
+		out8(addr + 0x2AA, 0x55);
+		iobarrier_rw();
+		out8(addr + 0x555, 0xA0);
+		iobarrier_rw();
+		out8(dest+i, data_ch[i]);
+		iobarrier_rw();
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				flash_reset (addr);
+				flash_to_mem();
+				return (1);
+			}
+			iobarrier_rw();
+		}
+	}
+
+	flash_reset (addr);
+	flash_to_mem();
+	return (0);
+}
+
+/*
+ * Reset bank to read mode
+ */
+static void flash_reset (ulong addr)
+{
+	flash_to_xd();
+	out8(addr, 0xF0);	/* reset bank */
+	iobarrier_rw();
+	flash_to_mem();
+}
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_STM:	printf ("SGS THOMSON ");	break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+				break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size % 0x100000 == 0) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size / 0x100000, info->sector_count);
+	} else if (info->size % 0x400 == 0) {
+		printf ("  Size: %ld KB in %d Sectors\n",
+			info->size / 0x400, info->sector_count);
+	} else {
+		printf ("  Size: %ld B in %d Sectors\n",
+			info->size, info->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
diff --git a/board/MAI/AmigaOneG3SE/i8259.c b/board/MAI/AmigaOneG3SE/i8259.c
new file mode 100755
index 0000000..34f489f
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/i8259.c
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2002
+ * John W. Linville, linville@tuxdriver.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "i8259.h"
+
+#undef  IRQ_DEBUG
+
+#ifdef  IRQ_DEBUG
+#define PRINTF(fmt,args...)     printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+static inline unsigned char read_byte(volatile unsigned char* from)
+{
+    int x;
+    asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from));
+    return (unsigned char)x;
+}
+
+static inline void write_byte(volatile unsigned char *to, int x)
+{
+    asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x));
+}
+
+static inline unsigned long read_long_little(volatile unsigned long *from)
+{
+    unsigned long x;
+    asm volatile ("lwbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m"(*from));
+    return (unsigned long)x;
+}
+
+#ifdef out8
+#undef out8
+#endif
+
+#ifdef in8
+#undef in8
+#endif
+
+#define out8(addr, byte) write_byte(0xFE000000 | addr, byte)
+#define in8(addr) read_byte(0xFE000000 | addr)
+
+/*
+ * This contains the irq mask for both 8259A irq controllers,
+ */
+static char cached_imr[2] = {0xff, 0xff};
+
+#define cached_imr1	(cached_imr[0])
+#define cached_imr2	(cached_imr[1])
+
+void i8259_init(void)
+{
+	char dummy;
+	PRINTF("Initializing Interrupt controller\n");
+	/* init master interrupt controller */
+	out8(0x20, 0x11); /* 0x19); /###* Start init sequence */
+	out8(0x21, 0x00); /* Vector base */
+	out8(0x21, 0x04); /* edge tiggered, Cascade (slave) on IRQ2 */
+	out8(0x21, 0x11); /* was: 0x01); /###* Select 8086 mode */
+
+	/* init slave interrupt controller */
+	out8(0xA0, 0x11); /* 0x19); /###* Start init sequence */
+	out8(0xA1, 0x08); /* Vector base */
+	out8(0xA1, 0x02); /* edge triggered, Cascade (slave) on IRQ2 */
+	out8(0xA1, 0x11); /* was: 0x01); /###* Select 8086 mode */
+
+	/* always read ISR */
+	out8(0x20, 0x0B);
+	dummy = in8(ISR_1);
+	out8(0xA0, 0x0B);
+	dummy = in8(ISR_2);
+
+/*     out8(0x43, 0x30); */
+/*     out8(0x40, 0); */
+/*     out8(0x40, 0); */
+/*     out8(0x43, 0x70); */
+/*     out8(0x41, 0); */
+/*     out8(0x41, 0); */
+/*     out8(0x43, 0xb0); */
+/*     out8(0x42, 0); */
+/*     out8(0x42, 0); */
+
+	/* Mask all interrupts */
+	out8(IMR_2, cached_imr2);
+	out8(IMR_1, cached_imr1);
+
+	i8259_unmask_irq(2);
+#if 0
+	{
+	    int i;
+	    for (i=0; i<16; i++)
+	    {
+		i8259_unmask_irq(i);
+	    }
+	}
+#endif
+}
+
+static volatile char *pci_intack = (void *)0xFEF00000;
+
+int i8259_irq(void)
+{
+	int irq;
+
+	irq = read_long_little(pci_intack) & 0xff;
+	if (irq==7) {
+		/*
+		 * This may be a spurious interrupt.
+		 *
+		 * Read the interrupt status register (ISR). If the most
+		 * significant bit is not set then there is no valid
+		 * interrupt.
+		 */
+		if(~in8(0x20)&0x80) {
+			irq = -1;
+		}
+	}
+
+	return irq;
+}
+int i8259_get_irq(struct pt_regs *regs)
+{
+	unsigned char irq;
+
+	/*
+	 * Perform an interrupt acknowledge cycle on controller 1
+	 */
+	out8(OCW3_1, 0x0C); /* prepare for poll */
+	irq = in8(IPL_1) & 7;
+	if (irq == 2) {
+		/*
+		 * Interrupt is cascaded so perform interrupt
+		 * acknowledge on controller 2
+		 */
+		out8(OCW3_2, 0x0C); /* prepare for poll */
+		irq = (in8(IPL_2) & 7) + 8;
+		if (irq == 15) {
+			/*
+			 * This may be a spurious interrupt
+			 *
+			 * Read the interrupt status register. If the most
+			 * significant bit is not set then there is no valid
+			 * interrupt
+			 */
+			out8(OCW3_2, 0x0b);
+			if (~(in8(ISR_2) & 0x80)) {
+				return -1;
+			}
+		}
+	} else if (irq == 7) {
+		/*
+		 * This may be a spurious interrupt
+		 *
+		 * Read the interrupt status register. If the most
+		 * significant bit is not set then there is no valid
+		 * interrupt
+		 */
+		out8(OCW3_1, 0x0b);
+		if (~(in8(ISR_1) & 0x80)) {
+			return -1;
+		}
+	}
+	return irq;
+}
+
+/*
+ * Careful! The 8259A is a fragile beast, it pretty
+ * much _has_ to be done exactly like this (mask it
+ * first, _then_ send the EOI, and the order of EOI
+ * to the two 8259s is important!
+ */
+void i8259_mask_and_ack(int irq)
+{
+	if (irq > 7) {
+		cached_imr2 |= (1 << (irq - 8));
+		in8(IMR_2); /* DUMMY */
+		out8(IMR_2, cached_imr2);
+		out8(OCW2_2, 0x20); /* Non-specific EOI */
+		out8(OCW2_1, 0x20); /* Non-specific EOI to cascade */
+	} else {
+		cached_imr1 |= (1 << irq);
+		in8(IMR_1); /* DUMMY */
+		out8(IMR_1, cached_imr1);
+		out8(OCW2_1, 0x20); /* Non-specific EOI */
+	}
+}
+
+void i8259_mask_irq(int irq)
+{
+	if (irq & 8) {
+		cached_imr2 |= (1 << (irq & 7));
+		out8(IMR_2, cached_imr2);
+	} else {
+		cached_imr1 |= (1 << irq);
+		out8(IMR_1, cached_imr1);
+	}
+}
+
+void i8259_unmask_irq(int irq)
+{
+	if (irq & 8) {
+		cached_imr2 &= ~(1 << (irq & 7));
+		out8(IMR_2, cached_imr2);
+	} else {
+		cached_imr1 &= ~(1 << irq);
+		out8(IMR_1, cached_imr1);
+	}
+}
diff --git a/board/MAI/AmigaOneG3SE/i8259.h b/board/MAI/AmigaOneG3SE/i8259.h
new file mode 100755
index 0000000..05c4052
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/i8259.h
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * John W. Linville, linville@tuxdriver.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define ICW1_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1
+#define ICW1_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1
+#define ICW2_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2
+#define ICW2_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2
+#define ICW3_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3
+#define ICW3_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3
+#define ICW4_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4
+#define ICW4_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4
+#define OCW1_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1
+#define OCW1_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1
+#define OCW2_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2
+#define OCW2_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2
+#define OCW3_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3
+#define OCW3_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3
+
+#define IMR_1   OCW1_1
+#define IMR_2   OCW1_2
+
+#define ISR_1   ICW1_1
+#define ISR_2   ICW1_2
+
+#define IPL_1   ICW1_1
+#define IPL_2   ICW1_2
+
+extern void i8259_init(void);
+
+extern int i8259_get_irq(struct pt_regs *regs);
+
+extern void i8259_mask_and_ack(int irq);
+
+extern void i8259_mask_irq(int irq);
+
+extern void i8259_unmask_irq(int irq);
diff --git a/board/MAI/AmigaOneG3SE/interrupts.c b/board/MAI/AmigaOneG3SE/interrupts.c
new file mode 100755
index 0000000..5b314a8
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/interrupts.c
@@ -0,0 +1,266 @@
+/*
+ * (C) Copyright 2002
+ * John W. Linville <linville@tuxdriver.com>
+ *
+ *    Copied and modified from original code by Josh Huber.  Original
+ *    copyright notice preserved below.
+ *
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * interrupts.c - just enough support for the decrementer/timer
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include "i8259.h"
+
+#undef DEBUG
+#ifdef  DEBUG
+#define PRINTF(fmt,args...)     printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+#define NR_IRQS	16
+
+void irq_alloc_init(void);
+long irq_alloc(long wanted);
+
+/****************************************************************************/
+
+unsigned decrementer_count;	     /* count value for 1e6/HZ microseconds */
+
+struct irq_action {
+    interrupt_handler_t *handler;
+    void *arg;
+    ulong count;
+};
+
+static struct irq_action irq_handlers[NR_IRQS];
+
+/****************************************************************************/
+
+static __inline__ unsigned long
+get_msr(void)
+{
+	unsigned long msr;
+
+	asm volatile("mfmsr %0" : "=r" (msr) :);
+	return msr;
+}
+
+static __inline__ void
+set_msr(unsigned long msr)
+{
+	asm volatile("mtmsr %0" : : "r" (msr));
+}
+
+static __inline__ unsigned long
+get_dec(void)
+{
+	unsigned long val;
+
+	asm volatile("mfdec %0" : "=r" (val) :);
+	return val;
+}
+
+
+static __inline__ void
+set_dec(unsigned long val)
+{
+	asm volatile("mtdec %0" : : "r" (val));
+}
+
+
+void
+enable_interrupts(void)
+{
+    set_msr (get_msr() | MSR_EE);
+}
+
+/* returns flag if MSR_EE was set before */
+int
+disable_interrupts(void)
+{
+    ulong msr;
+
+    msr = get_msr();
+    set_msr (msr & ~MSR_EE);
+    return ((msr & MSR_EE) != 0);
+}
+
+/****************************************************************************/
+
+int interrupt_init (void)
+{
+    extern void new_reset(void);
+    extern void new_reset_end(void);
+#ifdef DEBUG
+	puts("interrupt_init: setting decrementer_count\n");
+#endif
+	decrementer_count = get_tbclk() / CFG_HZ;
+
+#ifdef DEBUG
+	puts("interrupt_init: setting actual decremter\n");
+#endif
+	set_dec (get_tbclk() / CFG_HZ);
+
+#ifdef DEBUG
+	puts("interrupt_init: clearing external interrupt table\n");
+#endif
+	/* clear external interrupt table here */
+	memset(irq_handlers, 0, sizeof(irq_handlers));
+
+#ifdef DEBUG
+	puts("interrupt_init: initializing interrupt controller\n");
+#endif
+	i8259_init();
+
+#ifdef DEBUG
+	puts("Copying reset trampoline\n");
+#endif
+	/* WARNING: Assmues that the first megabyte is CACHEINHIBIT! */
+	memcpy((void *)0x100, new_reset, new_reset_end - new_reset);
+
+#ifdef DEBUG
+	PRINTF("interrupt_init: enabling interrupts (msr = %08x)\n",
+		get_msr());
+#endif
+	set_msr (get_msr() | MSR_EE);
+
+#ifdef DEBUG
+	PRINTF("interrupt_init: done. (msr = %08x)\n", get_msr());
+#endif
+
+}
+
+/****************************************************************************/
+
+/*
+ * Handle external interrupts
+ */
+void
+external_interrupt(struct pt_regs *regs)
+{
+    extern int i8259_irq(void);
+
+	int irq, unmask = 1;
+
+	irq = i8259_irq(); /*i8259_get_irq(regs); */
+/*	printf("irq = %d, handler at %p ack=%d\n", irq, irq_handlers[irq].handler, *(volatile unsigned char *)0xFEF00000); */
+	i8259_mask_and_ack(irq);
+
+	if (irq_handlers[irq].handler != NULL)
+		(*irq_handlers[irq].handler)(irq_handlers[irq].arg);
+	else {
+		PRINTF ("\nBogus External Interrupt IRQ %d\n", irq);
+		/*
+	 	* turn off the bogus interrupt, otherwise it
+	 	* might repeat forever
+	 	*/
+		unmask = 0;
+	}
+
+	if (unmask) i8259_unmask_irq(irq);
+}
+
+volatile ulong timestamp = 0;
+
+/*
+ * timer_interrupt - gets called when the decrementer overflows,
+ * with interrupts disabled.
+ * Trivial implementation - no need to be really accurate.
+ */
+void
+timer_interrupt(struct pt_regs *regs)
+{
+	set_dec(decrementer_count);
+	timestamp++;
+}
+
+/****************************************************************************/
+
+void
+reset_timer(void)
+{
+	timestamp = 0;
+}
+
+ulong
+get_timer(ulong base)
+{
+	return (timestamp - base);
+}
+
+void
+set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+/****************************************************************************/
+
+/*
+ * Install and free a interrupt handler.
+ */
+
+void
+irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
+{
+	if (irq < 0 || irq >= NR_IRQS) {
+		PRINTF("irq_install_handler: bad irq number %d\n", irq);
+		return;
+	}
+
+	if (irq_handlers[irq].handler != NULL)
+		PRINTF("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
+		       (ulong)handler, (ulong)irq_handlers[irq].handler);
+
+	irq_handlers[irq].handler = handler;
+	irq_handlers[irq].arg     = arg;
+
+	i8259_unmask_irq(irq);
+}
+
+void
+irq_free_handler(int irq)
+{
+	if (irq < 0 || irq >= NR_IRQS) {
+		PRINTF("irq_free_handler: bad irq number %d\n", irq);
+		return;
+	}
+
+	i8259_mask_irq(irq);
+
+	irq_handlers[irq].handler = NULL;
+	irq_handlers[irq].arg     = NULL;
+}
+
+/****************************************************************************/
+
+void
+do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+	puts("IRQ related functions are unimplemented currently.\n");
+}
diff --git a/board/MAI/AmigaOneG3SE/macros.h b/board/MAI/AmigaOneG3SE/macros.h
new file mode 100755
index 0000000..6020d7e
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/macros.h
@@ -0,0 +1,84 @@
+
+#ifndef _MACROS_H
+#define _MACROS_H
+
+	/*
+	** Load a long integer into a register
+	*/
+	.macro liw reg, value
+		lis \reg, \value@h
+		ori \reg, \reg, \value@l
+	.endm
+
+
+	/*
+	** Generate config_addr request
+	** This macro expects the values in registers:
+	** r3 - bus
+	** r4 - devfn
+	** r5 - offset
+	*/
+	.macro config_addr
+		rlwinm	r9, r5, 24, 0, 6
+		rlwinm	r8, r4, 16, 0, 31
+		rlwinm	r7, r3, 8, 0, 31
+		or	r9, r8, r9
+		or	r9, r7, r9
+		ori	r9, r9, 0x80
+		liw	r10, 0xfec00cf8
+		stw	r9, 0(r10)
+		eieio
+		sync
+	.endm
+
+
+	/*
+	** Generate config_data address
+	*/
+	.macro config_data mask
+		andi.	r9, r5, \mask
+		addi	r9, r9, 0xcfc
+		oris	r9, r9, 0xfee0
+	.endm
+
+
+	/*
+	** Write a byte value to an output port
+	*/
+	.macro outb port, value
+		lis     r2, 0xfe00
+		li      r0, \value
+		stb     r0, \port(r2)
+	.endm
+
+
+	/*
+	** Write a register byte value to an output port
+	*/
+	.macro outbr port, value
+		lis     r2, 0xfe00
+		stb     \value, \port(r2)
+	.endm
+
+
+	/*
+	** Read a byte value from a port into a specified register
+	*/
+	.macro inb reg, port
+		lis     r2, 0xfe00
+		lbz     \reg, \port(r2)
+	.endm
+
+
+	/*
+	** Write a byte to the SuperIO config area
+	*/
+	.macro siowb offset, value
+		li      r3, 0
+		li      r4, (7<<3)
+		li      r5, \offset
+		li      r6, \value
+		bl      pci_write_cfg_byte
+	.endm
+
+#endif
diff --git a/board/MAI/AmigaOneG3SE/memio.S b/board/MAI/AmigaOneG3SE/memio.S
new file mode 100755
index 0000000..980d343
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/memio.S
@@ -0,0 +1,67 @@
+#include	"macros.h"
+
+
+	.globl pci_read_cfg_byte
+
+pci_read_cfg_byte:
+	config_addr
+	config_data	3
+	eieio
+	sync
+	lbz	r3, 0(r9)
+	blr
+
+
+	.globl pci_write_cfg_byte
+
+pci_write_cfg_byte:
+	config_addr
+	config_data	3
+	stb	r6, 0(r9)
+	eieio
+	sync
+	blr
+
+
+	.globl pci_read_cfg_word
+
+pci_read_cfg_word:
+	config_addr
+	config_data	2
+	lhbrx	r3, 0, r9
+	eieio
+	sync
+	blr
+
+
+	.globl pci_write_cfg_word
+
+pci_write_cfg_word:
+	config_addr
+	config_data	2
+	sthbrx	r6, 0, r9
+	eieio
+	sync
+	blr
+
+
+	.globl pci_read_cfg_long
+
+pci_read_cfg_long:
+	config_addr
+	config_data	0
+	lwbrx	r3, 0, r9
+	eieio
+	sync
+	blr
+
+
+	.globl pci_write_cfg_long
+
+pci_write_cfg_long:
+	config_addr
+	config_data	0
+	stwbrx	r6, 0, r9
+	eieio
+	sync
+	blr
diff --git a/board/MAI/AmigaOneG3SE/memio.h b/board/MAI/AmigaOneG3SE/memio.h
new file mode 100755
index 0000000..f5ce303
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/memio.h
@@ -0,0 +1,113 @@
+/*
+ * Memory mapped IO
+ *
+ * (C) Copyright 2002
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ * You may also use this under a BSD license.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+#ifndef _MEMIO_H
+#define _MEMIO_H
+
+#include "short_types.h"
+
+#define IOBASE 0xFE000000
+
+#define in_byte(from) read_byte( (uint8 *)(IOBASE | (from)))
+#define in_word(from) read_word_little((uint16 *)(IOBASE | (from)))
+#define in_long(from) read_long_little((uint32 *)(IOBASE | (from)))
+#define out_byte(to, val) write_byte((uint8 *)(IOBASE | (to)), val)
+#define out_word(to, val) write_word_little((uint16 *)(IOBASE | (to)), val)
+#define out_long(to, val) write_long_little((uint32 *)(IOBASE | (to)), val)
+
+
+static inline uint8 read_byte(volatile uint8 *from)
+{
+    int x;
+    asm volatile ("lbz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from));
+    return (uint8)x;
+}
+
+
+static inline void write_byte(volatile uint8 *to, uint8 x)
+{
+    asm volatile ("stb %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x));
+}
+
+static inline uint16 read_word_little(volatile uint16 *from)
+{
+    int x;
+    asm volatile ("lhbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m" (*from));
+    return (uint16)x;
+}
+
+static inline uint16 read_word_big(volatile uint16 *from)
+{
+    int x;
+    asm volatile ("lhz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from));
+    return (uint16)x;
+}
+
+static inline void write_word_little(volatile uint16 *to, int x)
+{
+    asm volatile ("sthbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to));
+}
+
+static inline void write_word_big(volatile uint16 *to, int x)
+{
+    asm volatile ("sth %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x));
+}
+
+static inline uint32 read_long_little(volatile uint32 *from)
+{
+    unsigned long x;
+    asm volatile ("lwbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m"(*from));
+    return (uint32)x;
+}
+
+static inline uint32 read_long_big(volatile uint32 *from)
+{
+    unsigned long x;
+    asm volatile ("lwz %0,%1\n eieio\n sync" : "=r" (x) : "m" (*from));
+    return (uint32)x;
+}
+
+static inline void write_long_little(volatile uint32 *to, uint32 x)
+{
+    asm volatile ("stwbrx %1,0,%2\n eieio\n sync" : "=m" (*to) : "r" (x), "r" (to));
+}
+
+static inline void write_long_big(volatile uint32 *to, uint32 x)
+{
+    asm volatile ("stw %1,%0\n eieio\n sync" : "=m" (*to) : "r" (x));
+}
+
+#define CONFIG_ADDR(bus, devfn, offset) \
+    write_long_big((uint32 *)0xFEC00CF8,           \
+		   ((offset & 0xFC)<<24) | (devfn << 16)  \
+		   | (bus<<8) | 0x80);
+#define CONFIG_DATA(offset,mask) ((void *)(0xFEE00CFC+(offset & mask)))
+
+
+uint8 pci_read_cfg_byte(int32 bus, int32 devfn, int32 offset);
+void pci_write_cfg_byte(int32 bus, int32 devfn, int32 offset, uint8 x);
+uint16 pci_read_cfg_word(int32 bus, int32 devfn, int32 offset);
+void pci_write_cfg_word(int32 bus, int32 devfn, int32 offset, uint16 x);
+uint32 pci_read_cfg_long(int32 bus, int32 devfn, int32 offset);
+void pci_write_cfg_long(int32 bus, int32 devfn, int32 offset, uint32 x);
+
+
+#endif
diff --git a/board/MAI/AmigaOneG3SE/memory_dump b/board/MAI/AmigaOneG3SE/memory_dump
new file mode 100755
index 0000000..65e7936
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/memory_dump
@@ -0,0 +1,30 @@
+64 MB:
+0x00: 80 08 04 0c 09 01 40 00 01 a0 60 00 80 08 00 01
+0x10: 8f 04 04 01 01 00 06 a0 60 00 00 14 10 14 2d 10
+0x20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00
+0x30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 f2
+0x40: 7f 61 00 00 00 00 00 00 46 04 00 ff ff ff ff ff
+0x50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+0x60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+0x70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff 64 f4
+
+512 MB:
+0x00: 80 08 04 0d 0a 02 40 00 01 75 54 00 82 08 00 01
+0x10: 8f 04 04 01 01 00 0f 00 00 00 00 14 0f 14 2d 40
+0x20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00
+0x30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 d2
+0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 fd
+
+256 MB:
+0x00: 80 08 04 0c 0a 02 40 00 01 75 54 00 80 08 00 01
+0x10: 8f 04 06 01 01 00 0e a0 60 00 00 14 0f 14 2d 20
+0x20: 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00
+0x30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 b0
+0x40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+0x60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+0x70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 f6
+
diff --git a/board/MAI/AmigaOneG3SE/nvram.c b/board/MAI/AmigaOneG3SE/nvram.c
new file mode 100755
index 0000000..d37eec1
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/nvram.c
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2002
+ * Thomas Frieden, Hyperion Entertainment
+ * ThomasF@hyperion-entertainment.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "memio.h"
+
+void enable_nvram(void)
+{
+    pci_write_cfg_byte(0, 0, 0x56, 0x0b);
+}
+
+void disable_nvram(void)
+{
+    pci_write_cfg_byte(0, 0, 0x56, 0x0);
+}
diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.c b/board/MAI/AmigaOneG3SE/ps2kbd.c
new file mode 100755
index 0000000..cf4f4d0
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/ps2kbd.c
@@ -0,0 +1,690 @@
+/*
+ * (C) Copyright 2002
+ * John W. Linville, linville@tuxdriver.com
+ *
+ * Modified from code for support of MIP405 and PIP405 boards.  Previous
+ * copyright follows.
+ *
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Source partly derived from:
+ * linux/drivers/char/pc_keyb.c
+ *
+ *
+ */
+#include <common.h>
+#include <asm/processor.h>
+#include <devices.h>
+#include "ps2kbd.h"
+
+
+unsigned char kbd_read_status(void);
+unsigned char kbd_read_input(void);
+void kbd_send_data(unsigned char data);
+void i8259_mask_irq(unsigned int irq);
+void i8259_unmask_irq(unsigned int irq);
+
+/* used only by send_data - set by keyboard_interrupt */
+
+
+#undef KBG_DEBUG
+
+#ifdef KBG_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#define KBD_STAT_KOBF		0x01
+#define KBD_STAT_IBF		0x02
+#define KBD_STAT_SYS		0x04
+#define KBD_STAT_CD			0x08
+#define KBD_STAT_LOCK		0x10
+#define KBD_STAT_MOBF		0x20
+#define KBD_STAT_TI_OUT	0x40
+#define KBD_STAT_PARERR	0x80
+
+#define KBD_INIT_TIMEOUT 2000		/* Timeout in ms for initializing the keyboard */
+#define KBC_TIMEOUT 250			/* Timeout in ms for sending to keyboard controller */
+#define KBD_TIMEOUT 2000		/* Timeout in ms for keyboard command acknowledge */
+/*
+ *	Keyboard Controller Commands
+ */
+
+#define KBD_CCMD_READ_MODE			0x20	/* Read mode bits */
+#define KBD_CCMD_WRITE_MODE			0x60	/* Write mode bits */
+#define KBD_CCMD_GET_VERSION		0xA1	/* Get controller version */
+#define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
+#define KBD_CCMD_MOUSE_ENABLE		0xA8	/* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE			0xA9	/* Mouse interface test */
+#define KBD_CCMD_SELF_TEST			0xAA	/* Controller self test */
+#define KBD_CCMD_KBD_TEST				0xAB	/* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE		0xAD	/* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE			0xAE	/* Keyboard interface enable */
+#define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
+					   initiated by the auxiliary device */
+#define KBD_CCMD_WRITE_MOUSE		0xD4	/* Write the following byte to the mouse */
+
+/*
+ *	Keyboard Commands
+ */
+
+#define KBD_CMD_SET_LEDS				0xED	/* Set keyboard leds */
+#define KBD_CMD_SET_RATE				0xF3	/* Set typematic rate */
+#define KBD_CMD_ENABLE					0xF4	/* Enable scanning */
+#define KBD_CMD_DISABLE					0xF5	/* Disable scanning */
+#define KBD_CMD_RESET						0xFF	/* Reset */
+
+/*
+ *	Keyboard Replies
+ */
+
+#define KBD_REPLY_POR						0xAA	/* Power on reset */
+#define KBD_REPLY_ACK						0xFA	/* Command ACK */
+#define KBD_REPLY_RESEND				0xFE	/* Command NACK, send the cmd again */
+
+/*
+ *	Status Register Bits
+ */
+
+#define KBD_STAT_OBF 						0x01	/* Keyboard output buffer full */
+#define KBD_STAT_IBF 						0x02	/* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST				0x04	/* Self test successful */
+#define KBD_STAT_CMD						0x08	/* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED				0x10	/* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF			0x20	/* Mouse output buffer full */
+#define KBD_STAT_GTO 						0x40	/* General receive/xmit timeout */
+#define KBD_STAT_PERR 					0x80	/* Parity error */
+
+#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
+
+/*
+ *	Controller Mode Register Bits
+ */
+
+#define KBD_MODE_KBD_INT				0x01	/* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT			0x02	/* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS 						0x04	/* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK			0x08	/* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD		0x10	/* Disable keyboard interface */
+#define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
+#define KBD_MODE_KCC 						0x40	/* Scan code conversion to PC format */
+#define KBD_MODE_RFU						0x80
+
+
+#define KDB_DATA_PORT			0x60
+#define KDB_COMMAND_PORT	0x64
+
+#define 	LED_SCR		0x01	/* scroll lock led */
+#define 	LED_CAP		0x04	/* caps lock led */
+#define 	LED_NUM		0x02	/* num lock led */
+
+#define 	KBD_BUFFER_LEN 0x20  /* size of the keyboardbuffer */
+
+
+static volatile char kbd_buffer[KBD_BUFFER_LEN];
+static volatile int in_pointer = 0;
+static volatile int out_pointer = 0;
+
+
+static unsigned char num_lock = 0;
+static unsigned char caps_lock = 0;
+static unsigned char scroll_lock = 0;
+static unsigned char shift = 0;
+static unsigned char ctrl = 0;
+static unsigned char alt = 0;
+static unsigned char e0 = 0;
+static unsigned char leds = 0;
+
+#define DEVNAME "ps2kbd"
+
+/* Simple translation table for the keys */
+
+static unsigned char kbd_plain_xlate[] = {
+	0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t',	/* 0x00 - 0x0f */
+	 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's',	/* 0x10 - 0x1f */
+	 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v',	/* 0x20 - 0x2f */
+	 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
+	'\r',0xff,0xff
+	};
+
+static unsigned char kbd_shift_xlate[] = {
+	0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t',	/* 0x00 - 0x0f */
+	 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S',	/* 0x10 - 0x1f */
+	 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V',	/* 0x20 - 0x2f */
+	 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
+	'\r',0xff,0xff
+	};
+
+static unsigned char kbd_ctrl_xlate[] = {
+	0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t',	/* 0x00 - 0x0f */
+	0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13,	/* 0x10 - 0x1f */
+	0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16,	/* 0x20 - 0x2f */
+	0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
+	'\r',0xff,0xff
+	};
+
+/******************************************************************
+ * Init
+ ******************************************************************/
+
+int isa_kbd_init(void)
+{
+	char* result;
+	result=kbd_initialize();
+	if (result != NULL)
+	{
+	    result = kbd_initialize();
+	}
+	if(result==NULL) {
+		printf("AT Keyboard initialized\n");
+		irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
+		return (1);
+	}
+	else {
+		printf("%s\n",result);
+		return (-1);
+	}
+}
+
+#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console (void);
+#else
+int overwrite_console (void)
+{
+	return (0);
+}
+#endif
+
+int drv_isa_kbd_init (void)
+{
+	int error;
+  	device_t kbddev ;
+	char *stdinname  = getenv ("stdin");
+
+	if(isa_kbd_init()==-1)
+		return -1;
+  	memset (&kbddev, 0, sizeof(kbddev));
+  	strcpy(kbddev.name, DEVNAME);
+  	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+  	kbddev.putc = NULL ;
+	kbddev.puts = NULL ;
+	kbddev.getc = kbd_getc ;
+	kbddev.tstc = kbd_testc ;
+
+ 	error = device_register (&kbddev);
+	if(error==0) {
+		/* check if this is the standard input device */
+		if(strcmp(stdinname,DEVNAME)==0) {
+			/* reassign the console */
+			if(overwrite_console()) {
+				return 1;
+			}
+			error=console_assign(stdin,DEVNAME);
+			if(error==0)
+				return 1;
+			else
+				return error;
+		}
+		return 1;
+	}
+	return error;
+}
+
+/******************************************************************
+ * Queue handling
+ ******************************************************************/
+/* puts character in the queue and sets up the in and out pointer */
+void kbd_put_queue(char data)
+{
+	if((in_pointer+1)==KBD_BUFFER_LEN) {
+		if(out_pointer==0) {
+			return; /* buffer full */
+		} else{
+			in_pointer=0;
+		}
+	} else {
+		if((in_pointer+1)==out_pointer)
+			return; /* buffer full */
+		in_pointer++;
+	}
+	kbd_buffer[in_pointer]=data;
+	return;
+}
+
+/* test if a character is in the queue */
+int kbd_testc(void)
+{
+	if(in_pointer==out_pointer)
+		return(0); /* no data */
+	else
+		return(1);
+}
+/* gets the character from the queue */
+int kbd_getc(void)
+{
+	char c;
+
+	while(in_pointer==out_pointer);
+	if((out_pointer+1)==KBD_BUFFER_LEN)
+		out_pointer=0;
+	else
+		out_pointer++;
+	c=kbd_buffer[out_pointer];
+	return (int)c;
+
+}
+
+
+/* set LEDs */
+
+void kbd_set_leds(void)
+{
+	if(caps_lock==0)
+		leds&=~LED_CAP; /* switch caps_lock off */
+	else
+		leds|=LED_CAP; /* switch on LED */
+	if(num_lock==0)
+		leds&=~LED_NUM; /* switch LED off */
+	else
+		leds|=LED_NUM;  /* switch on LED */
+	if(scroll_lock==0)
+		leds&=~LED_SCR; /* switch LED off */
+	else
+		leds|=LED_SCR; /* switch on LED */
+	kbd_send_data(KBD_CMD_SET_LEDS);
+	kbd_send_data(leds);
+}
+
+
+void handle_keyboard_event(unsigned char scancode)
+{
+	unsigned char keycode;
+
+	/*  Convert scancode to keycode */
+	PRINTF("scancode %x\n",scancode);
+	if(scancode==0xe0) {
+		e0=1; /* special charakters */
+		return;
+	}
+	if(e0==1) {
+		e0=0; /* delete flag */
+		if(!(	((scancode&0x7F)==0x38)|| /* the right ctrl key */
+			((scancode&0x7F)==0x1D)|| /* the right alt key */
+			((scancode&0x7F)==0x35)||	/* the right '/' key */
+			((scancode&0x7F)==0x1C)||  /* the right enter key */
+			((scancode)==0x48)|| /* arrow up */
+			((scancode)==0x50)|| /* arrow down */
+			((scancode)==0x4b)|| /* arrow left */
+			((scancode)==0x4d)))  /* arrow right */
+			/* we swallow unknown e0 codes */
+			return;
+	}
+	/* special cntrl keys */
+	switch(scancode)
+	{
+	case 0x48:
+	    kbd_put_queue(27);
+	    kbd_put_queue(91);
+	    kbd_put_queue('A');
+	    return;
+	case 0x50:
+	    kbd_put_queue(27);
+	    kbd_put_queue(91);
+	    kbd_put_queue('B');
+	    return;
+	case 0x4b:
+	    kbd_put_queue(27);
+	    kbd_put_queue(91);
+	    kbd_put_queue('D');
+	    return;
+	case 0x4D:
+	    kbd_put_queue(27);
+	    kbd_put_queue(91);
+	    kbd_put_queue('C');
+	    return;
+	case 0x58: /* F12 key */
+	    if (ctrl == 1)
+	    {
+		extern int console_changed;
+		setenv("stdin", DEVNAME);
+		setenv("stdout", "vga");
+		console_changed = 1;
+	    }
+	    return;
+	case 0x2A:
+		case 0x36: /* shift pressed */
+			shift=1;
+			return; /* do nothing else */
+		case 0xAA:
+		case 0xB6: /* shift released */
+			shift=0;
+			return; /* do nothing else */
+		case 0x38: /* alt pressed */
+			alt=1;
+			return; /* do nothing else */
+		case 0xB8: /* alt released */
+			alt=0;
+			return; /* do nothing else */
+		case 0x1d: /* ctrl pressed */
+			ctrl=1;
+			return; /* do nothing else */
+		case 0x9d: /* ctrl released */
+			ctrl=0;
+			return; /* do nothing else */
+		case 0x46: /* scrollock pressed */
+			scroll_lock=~scroll_lock;
+			kbd_set_leds();
+			return; /* do nothing else */
+		case 0x3A: /* capslock pressed */
+			caps_lock=~caps_lock;
+			kbd_set_leds();
+			return;
+		case 0x45: /* numlock pressed */
+			num_lock=~num_lock;
+			kbd_set_leds();
+			return;
+		case 0xC6: /* scroll lock released */
+		case 0xC5: /* num lock released */
+		case 0xBA: /* caps lock released */
+			return; /* just swallow */
+	}
+	if((scancode&0x80)==0x80) /* key released */
+		return;
+	/* now, decide which table we need */
+	if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
+		PRINTF("unkown scancode %X\n",scancode);
+		return; /* swallow it */
+	}
+	/* setup plain code first */
+	keycode=kbd_plain_xlate[scancode];
+	if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
+		if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
+			PRINTF("unkown caps-locked scancode %X\n",scancode);
+			return; /* swallow it */
+		}
+		keycode=kbd_shift_xlate[scancode];
+		if(keycode<'A') { /* we only want the alphas capital */
+			keycode=kbd_plain_xlate[scancode];
+		}
+	}
+	if(shift==1) { /* shift overwrites caps_lock */
+		if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
+			PRINTF("unkown shifted scancode %X\n",scancode);
+			return; /* swallow it */
+		}
+		keycode=kbd_shift_xlate[scancode];
+	}
+	if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
+		if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
+			PRINTF("unkown ctrl scancode %X\n",scancode);
+			return; /* swallow it */
+		}
+		keycode=kbd_ctrl_xlate[scancode];
+	}
+	/* check if valid keycode */
+	if(keycode==0xff) {
+		PRINTF("unkown scancode %X\n",scancode);
+		return; /* swallow unknown codes */
+	}
+
+	kbd_put_queue(keycode);
+	PRINTF("%x\n",keycode);
+}
+
+/*
+ * This reads the keyboard status port, and does the
+ * appropriate action.
+ *
+ */
+unsigned char handle_kbd_event(void)
+{
+	unsigned char status = kbd_read_status();
+	unsigned int work = 10000;
+
+	while ((--work > 0) && (status & KBD_STAT_OBF)) {
+		unsigned char scancode;
+
+		scancode = kbd_read_input();
+
+		/* Error bytes must be ignored to make the
+		   Synaptics touchpads compaq use work */
+		/* Ignore error bytes */
+		if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
+		{
+			if (status & KBD_STAT_MOUSE_OBF)
+				; /* not supported: handle_mouse_event(scancode); */
+			else
+				handle_keyboard_event(scancode);
+		}
+		status = kbd_read_status();
+	}
+	if (!work)
+		PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
+	return status;
+}
+
+
+/******************************************************************************
+ * Lowlevel Part of keyboard section
+ */
+unsigned char kbd_read_status(void)
+{
+	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
+}
+
+unsigned char kbd_read_input(void)
+{
+	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
+}
+
+void kbd_write_command(unsigned char cmd)
+{
+	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
+}
+
+void kbd_write_output(unsigned char data)
+{
+	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
+}
+
+int kbd_read_data(void)
+{
+	int val;
+	unsigned char status;
+
+	val=-1;
+	status = kbd_read_status();
+	if (status & KBD_STAT_OBF) {
+		val = kbd_read_input();
+		if (status & (KBD_STAT_GTO | KBD_STAT_PERR))
+			val = -2;
+	}
+	return val;
+}
+
+int kbd_wait_for_input(void)
+{
+	unsigned long timeout;
+	int val;
+
+	timeout = KBD_TIMEOUT;
+	val=kbd_read_data();
+	while(val < 0)
+	{
+		if(timeout--==0)
+			return -1;
+		udelay(1000);
+		val=kbd_read_data();
+	}
+	return val;
+}
+
+
+int kb_wait(void)
+{
+	unsigned long timeout = KBC_TIMEOUT * 10;
+
+	do {
+		unsigned char status = handle_kbd_event();
+		if (!(status & KBD_STAT_IBF))
+			return 0; /* ok */
+		udelay(1000);
+		timeout--;
+	} while (timeout);
+	return 1;
+}
+
+void kbd_write_command_w(int data)
+{
+	if(kb_wait())
+		PRINTF("timeout in kbd_write_command_w\n");
+	kbd_write_command(data);
+}
+
+void kbd_write_output_w(int data)
+{
+	if(kb_wait())
+		PRINTF("timeout in kbd_write_output_w\n");
+	kbd_write_output(data);
+}
+
+void kbd_send_data(unsigned char data)
+{
+	unsigned char status;
+	i8259_mask_irq(KBD_INTERRUPT); /* disable interrupt */
+	kbd_write_output_w(data);
+	status = kbd_wait_for_input();
+	if (status == KBD_REPLY_ACK)
+		i8259_unmask_irq(KBD_INTERRUPT); /* enable interrupt */
+}
+
+
+char * kbd_initialize(void)
+{
+	int status;
+
+	in_pointer = 0; /* delete in Buffer */
+	out_pointer = 0;
+	/*
+	 * Test the keyboard interface.
+	 * This seems to be the only way to get it going.
+	 * If the test is successful a x55 is placed in the input buffer.
+	 */
+	kbd_write_command_w(KBD_CCMD_SELF_TEST);
+	if (kbd_wait_for_input() != 0x55)
+		return "Kbd:   failed self test";
+	/*
+	 * Perform a keyboard interface test.  This causes the controller
+	 * to test the keyboard clock and data lines.  The results of the
+	 * test are placed in the input buffer.
+	 */
+	kbd_write_command_w(KBD_CCMD_KBD_TEST);
+	if (kbd_wait_for_input() != 0x00)
+		return "Kbd:   interface failed self test";
+	/*
+	 * Enable the keyboard by allowing the keyboard clock to run.
+	 */
+	kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
+	status = kbd_wait_for_input();
+	/*
+	 * Reset keyboard. If the read times out
+	 * then the assumption is that no keyboard is
+	 * plugged into the machine.
+	 * This defaults the keyboard to scan-code set 2.
+	 *
+	 * Set up to try again if the keyboard asks for RESEND.
+	 */
+	do {
+		kbd_write_output_w(KBD_CMD_RESET);
+		status = kbd_wait_for_input();
+		if (status == KBD_REPLY_ACK)
+			break;
+		if (status != KBD_REPLY_RESEND)
+		{
+			PRINTF("status: %X\n",status);
+			return "Kbd:   reset failed, no ACK";
+		}
+	} while (1);
+	if (kbd_wait_for_input() != KBD_REPLY_POR)
+		return "Kbd:   reset failed, no POR";
+
+	/*
+	 * Set keyboard controller mode. During this, the keyboard should be
+	 * in the disabled state.
+	 *
+	 * Set up to try again if the keyboard asks for RESEND.
+	 */
+	do {
+		kbd_write_output_w(KBD_CMD_DISABLE);
+		status = kbd_wait_for_input();
+		if (status == KBD_REPLY_ACK)
+			break;
+		if (status != KBD_REPLY_RESEND)
+			return "Kbd:   disable keyboard: no ACK";
+	} while (1);
+
+	kbd_write_command_w(KBD_CCMD_WRITE_MODE);
+	kbd_write_output_w(KBD_MODE_KBD_INT
+			      | KBD_MODE_SYS
+			      | KBD_MODE_DISABLE_MOUSE
+			      | KBD_MODE_KCC);
+
+	/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
+	kbd_write_command_w(KBD_CCMD_READ_MODE);
+	if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
+		/*
+		 * If the controller does not support conversion,
+		 * Set the keyboard to scan-code set 1.
+		 */
+		kbd_write_output_w(0xF0);
+		kbd_wait_for_input();
+		kbd_write_output_w(0x01);
+		kbd_wait_for_input();
+	}
+	kbd_write_output_w(KBD_CMD_ENABLE);
+	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+		return "Kbd:   enable keyboard: no ACK";
+
+	/*
+	 * Finally, set the typematic rate to maximum.
+	 */
+	kbd_write_output_w(KBD_CMD_SET_RATE);
+	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+		return "Kbd:   Set rate: no ACK";
+	kbd_write_output_w(0x00);
+	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+		return "Kbd:   Set rate: no ACK";
+	return NULL;
+}
+
+void kbd_interrupt(void)
+{
+	handle_kbd_event();
+}
diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.h b/board/MAI/AmigaOneG3SE/ps2kbd.h
new file mode 100755
index 0000000..fc5c422
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/ps2kbd.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2002
+ * John W. Linville, linville@tuxdriver.com
+ *
+ * Modified from code for support of MIP405 and PIP405 boards.  Previous
+ * copyright follows.
+ *
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _KBD_H_
+#define _KBD_H_
+
+extern int kbd_testc(void);
+extern int kbd_getc(void);
+extern void kbd_interrupt(void);
+extern char *kbd_initialize(void);
+
+unsigned char kbd_is_init(void);
+#define KBD_INTERRUPT 1
+#endif
diff --git a/board/MAI/AmigaOneG3SE/serial.c b/board/MAI/AmigaOneG3SE/serial.c
new file mode 100755
index 0000000..e83fb46
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/serial.c
@@ -0,0 +1,247 @@
+#include <common.h>
+#include <ns16550.h>
+#include "short_types.h"
+#include "memio.h"
+#include "articiaS.h"
+
+#ifndef CFG_NS16550
+static uint32 ComPort1;
+
+uint16 SerialEcho = 1;
+
+
+#define RECEIVER_HOLDING 0
+#define TRANSMITTER_HOLDING 0
+#define INTERRUPT_ENABLE 1
+#define INTERRUPT_STATUS 2
+#define FIFO_CONTROL 2
+#define LINE_CONTROL 3
+#define MODEM_CONTROL 4
+#define LINE_STATUS 5
+#define MODEM_STATUS 6
+#define SCRATCH_PAD 7
+
+#define DIVISOR_LATCH_LSB 0
+#define DIVISOR_LATCH_MSB 1
+#define PRESCALER_DIVISION 5
+
+#define COM_WRITE_BYTE(reg, byte) out_byte((ComPort1+reg), byte)
+#define COM_READ_BYTE(reg) in_byte((ComPort1+reg))
+
+static int serial_init_done = 0;
+
+void serial_init (void)
+{
+#if 0
+	uint32 clock_divisor = 115200 / baudrate;
+	uint8 cfg;
+	uint8 a;
+	uint16 devfn = 7 << 3;
+
+	if (serial_init_done)
+		return;
+
+	/*  Enter configuration mode */
+	cfg = pci_read_cfg_byte (0, devfn, 0x85);
+	pci_write_cfg_byte (0, devfn, 0x85, cfg | 0x02);
+
+	/* Set serial port COM1 as 3F8 */
+	out_byte (0x3F0, 0xE7);
+	out_byte (0x3f1, 0xfe);
+
+	/* Set serial port COM2 as 2F8 */
+	out_byte (0x3f0, 0xe8);
+	out_byte (0x3f1, 0xeb);
+
+	/* Enable */
+	out_byte (0x3f0, 0xe2);
+	a = in_byte (0x3f1);
+	a |= 0xc;
+	out_byte (0x3f0, 0xe2);
+	out_byte (0x3f1, a);
+
+	/*  Reset the configuration mode */
+	pci_write_cfg_byte (0, devfn, 0x85, cfg);
+#endif
+
+	ComPort1 = 0x3F8;
+
+	/*  Disable interrupts */
+	COM_WRITE_BYTE (INTERRUPT_ENABLE, 0x00);
+
+	/*  Set baud rate */
+	/* COM_WRITE_BYTE(LINE_CONTROL, 0x83); */
+	/* COM_WRITE_BYTE(DIVISOR_LATCH_LSB, (uint8)(clock_divisor & 0xFF)); */
+	/* COM_WRITE_BYTE(DIVISOR_LATCH_MSB, (uint8)(clock_divisor >> 8)); */
+	/* __asm("eieio"); */
+
+	/*  Set 8-N-1 */
+	COM_WRITE_BYTE (LINE_CONTROL, 0x03);
+	__asm ("eieio");
+
+	/*  Disable FIFO */
+	COM_WRITE_BYTE (MODEM_CONTROL, 0x03);
+	COM_WRITE_BYTE (FIFO_CONTROL, 0x07);
+
+	__asm ("eieio");
+	serial_init_done = 1;
+}
+
+extern int console_changed;
+
+void serial_putc (const char sendme)
+{
+	if (sendme == '\n') {
+		while ((in_byte (0x3FD) & 0x40) == 0);
+		out_byte (0x3f8, 0x0D);
+	}
+
+	while ((in_byte (0x3FD) & 0x40) == 0);
+	out_byte (0x3f8, sendme);
+}
+
+int serial_getc (void)
+{
+#if 0
+	uint8 c;
+
+	for (;;) {
+		uint8 x = in_byte (0x3FD);
+
+		if (x & 0x01)
+			break;
+
+		if (x & 0x0C)
+			out_byte (0x3fd, 0x0c);
+	}
+
+	c = in_byte (0x3F8);
+
+	return c;
+#else
+	while ((in_byte (0x3FD) & 0x01) == 0) {
+		if (console_changed != 0) {
+			printf ("Console changed\n");
+			console_changed = 0;
+			return 0;
+		}
+	}
+	return in_byte (0x3F8);
+#endif
+}
+
+int serial_tstc (void)
+{
+	return (in_byte (0x03FD) & 0x01) != 0;
+}
+
+void serial_debug_putc (int c)
+{
+	serial_puts ("DBG");
+	serial_putc (c);
+	serial_putc (0x0d);
+	serial_putc (0x0A);
+}
+
+#else
+
+const NS16550_t Com0 = (NS16550_t) CFG_NS16550_COM1;
+const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2;
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	uint32 clock_divisor = 115200 / gd->baudrate;
+
+	NS16550_init (Com0, clock_divisor);
+	/* NS16550_reinit(Com1, clock_divisor); */
+	/* serial_puts("COM1: 3F8h initalized"); */
+
+	return (0);
+}
+
+#if 0
+void serial_putc (const char c)
+{
+	NS16550_putc (Com0, c);
+	if (c == '\n')
+		NS16550_putc (Com0, 0x0D);
+}
+
+int serial_getc (void)
+{
+	return (int) NS16550_getc (Com0);
+}
+
+int serial_tstc (void)
+{
+	return NS16550_tstc (Com0);
+}
+#else
+void serial_putc (const char sendme)
+{
+	if (sendme == '\n') {
+		while ((in_byte (0x3FD) & 0x40) == 0);
+		out_byte (0x3f8, 0x0D);
+	}
+
+	while ((in_byte (0x3FD) & 0x40) == 0);
+	out_byte (0x3f8, sendme);
+}
+
+
+extern int console_changed;
+
+int serial_getc (void)
+{
+#if 0
+	uint8 c;
+
+	for (;;) {
+		uint8 x = in_byte (0x3FD);
+
+		if (x & 0x01)
+			break;
+
+		if (x & 0x0C)
+			out_byte (0x3fd, 0x0c);
+	}
+
+	c = in_byte (0x3F8);
+
+	return c;
+#else
+	while ((in_byte (0x3FD) & 0x01) == 0) {
+		if (console_changed != 0) {
+			console_changed = 0;
+			return 0;
+		}
+	}
+
+	return in_byte (0x3F8);
+#endif
+}
+
+int serial_tstc (void)
+{
+	return (in_byte (0x03FD) & 0x01) != 0;
+}
+#endif
+
+#endif
+
+void serial_puts (const char *string)
+{
+	while (*string)
+		serial_putc (*string++);
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	uint32 clock_divisor = 115200 / gd->baudrate;
+
+	NS16550_init (Com0, clock_divisor);
+}
diff --git a/board/MAI/AmigaOneG3SE/short_types.h b/board/MAI/AmigaOneG3SE/short_types.h
new file mode 100755
index 0000000..1840d28
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/short_types.h
@@ -0,0 +1,36 @@
+/*
+ * short type names
+ *
+ * (C) Copyright 2002
+ * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SHORT_TYPES_H
+#define _SHORT_TYPES_H
+
+typedef unsigned long  uint32;
+typedef long           int32;
+typedef unsigned short uint16;
+typedef short          int16;
+typedef unsigned char  uint8;
+typedef signed char    int8;
+
+#endif
diff --git a/board/MAI/AmigaOneG3SE/smbus.c b/board/MAI/AmigaOneG3SE/smbus.c
new file mode 100755
index 0000000..de13977
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/smbus.c
@@ -0,0 +1,206 @@
+#include "memio.h"
+#include "articiaS.h"
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+
+void sm_write_mode(void)
+{
+    out_byte(0xA539, 0x00);
+    out_byte(0xA53A, 0x03);
+}
+
+void sm_read_mode(void)
+{
+    out_byte(0xA53A, 0x02);
+    out_byte(0xA539, 0x02);
+}
+
+void sm_write_byte(uint8 writeme)
+{
+    int i;
+    int level;
+
+    out_byte(0xA539, 0x00);
+
+    level = 0;
+
+    for (i=0; i<8; i++)
+    {
+	if ((writeme & 0x80) == (level<<7))
+	{
+	    /* Bit did not change, rewrite strobe */
+	    out_byte(0xA539, level | 0x02);
+	    out_byte(0xA539, level);
+	}
+	else
+	{
+	    /* Bit changed, set bit, then strobe */
+	    level = (writeme & 0x80) >> 7;
+	    out_byte(0xA539, level);
+	    out_byte(0xA539, level | 0x02);
+	    out_byte(0xA539, level);
+	}
+	writeme <<= 1;
+    }
+    out_byte(0xA539, 0x00);
+}
+
+uint8 sm_read_byte(void)
+{
+    uint8 retme, r;
+    int i;
+
+    retme = 0;
+    for (i=0; i<8; i++)
+    {
+	retme <<= 1;
+	out_byte(0xA539, 0x00);
+	out_byte(0xA539, 0x02);
+	r = in_byte(0xA538) & 0x01;
+	retme |= r;
+    }
+
+    return retme;
+}
+
+int sm_get_ack(void)
+{
+    uint8 r;
+    r = in_byte(0xA538);
+    if ((r&0x01) == 0) return TRUE;
+    else return FALSE;
+}
+
+void sm_write_ack(void)
+{
+    out_byte(0xA539, 0x00);
+    out_byte(0xA539, 0x02);
+    out_byte(0xA539, 0x00);
+}
+
+void sm_write_nack(void)
+{
+    out_byte(0xA539, 0x01);
+    out_byte(0xA539, 0x03);
+    out_byte(0xA539, 0x01);
+}
+
+void sm_send_start(void)
+{
+    out_byte(0xA539, 0x03);
+    out_byte(0xA539, 0x02);
+}
+
+void sm_send_stop(void)
+{
+    out_byte(0xA539, 0x02);
+    out_byte(0xA539, 0x03);
+}
+
+int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage)
+{
+    /* S Addr Wr */
+    sm_write_mode();
+    sm_send_start();
+    sm_write_byte((addr<<1));
+
+    /* [A] */
+    sm_read_mode();
+    if (sm_get_ack() == FALSE) return FALSE;
+
+    /* Comm */
+    sm_write_mode();
+    sm_write_byte(reg);
+
+    /* [A] */
+    sm_read_mode();
+    if (sm_get_ack() == FALSE) return FALSE;
+
+    /* S Addr Rd */
+    sm_write_mode();
+    sm_send_start();
+    sm_write_byte((addr<<1)|1);
+
+    /* [A] */
+    sm_read_mode();
+    if (sm_get_ack() == FALSE) return FALSE;
+
+    /* [Data] */
+    *storage = sm_read_byte();
+
+    /* NA */
+    sm_write_mode();
+    sm_write_nack();
+    sm_send_stop();
+
+    return TRUE;
+}
+
+void sm_init(void)
+{
+    /* Switch to PMC mode */
+    pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER));
+
+    /* Set GPIO Base */
+    pci_write_cfg_long(0, 0, 0x40, 0xa500);
+
+    /* Enable GPIO */
+    pci_write_cfg_byte(0, 0, 0x44, 0x11);
+
+    /* Set both GPIO 0 and 1 as output */
+    out_byte(0xA53A, 0x03);
+}
+
+
+void sm_term(void)
+{
+    /* Switch to normal mode */
+    pci_write_cfg_byte(0, 0, REG_GROUP, 0);
+}
+
+
+int sm_get_data(uint8 *DataArray, int dimm_socket)
+{
+    int j;
+
+#if 0
+    /* Switch to PMC mode */
+    pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER));
+
+    /* Set GPIO Base */
+    pci_write_cfg_long(0, 0, 0x40, 0xa500);
+
+    /* Enable GPIO */
+    pci_write_cfg_byte(0, 0, 0x44, 0x11);
+
+    /* Set both GPIO 0 and 1 as output */
+    out_byte(0xA53A, 0x03);
+#endif
+
+    sm_init();
+    /* Start reading the rom */
+
+    j = 0;
+
+    do
+    {
+	if (sm_read_byte_from_device(dimm_socket, (uint8)j, DataArray) == FALSE)
+	{
+	    sm_term();
+	    return FALSE;
+	}
+
+	DataArray++;
+	j++;
+    } while (j < 128);
+
+    sm_term();
+    return TRUE;
+}
diff --git a/board/MAI/AmigaOneG3SE/smbus.h b/board/MAI/AmigaOneG3SE/smbus.h
new file mode 100755
index 0000000..beeb6a0
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/smbus.h
@@ -0,0 +1,22 @@
+#ifndef _SMBUS_H_
+#define _SMBUS_H_
+
+#include "short_types.h"
+
+#define SM_DIMM0_ADDR 0x51
+#define SM_DIMM1_ADDR 0x52
+
+void sm_write_mode(void);
+void sm_read_mode(void);
+void sm_write_byte(uint8 writeme);
+uint8 sm_read_byte(void);
+int sm_get_ack(void);
+void sm_write_ack(void);
+void sm_write_nack(void);
+void sm_send_start(void);
+void sm_send_stop(void);
+int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage);
+int sm_get_data(uint8 *DataArray, int dimm_socket);
+void sm_init(void);
+void sm_term(void);
+#endif
diff --git a/board/MAI/AmigaOneG3SE/start.txt b/board/MAI/AmigaOneG3SE/start.txt
new file mode 100755
index 0000000..e421462
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/start.txt
@@ -0,0 +1,198 @@
+
+	/*------------------------------------------------------*/
+	/*              TERON Articia / SDRAM Init              */
+	/*------------------------------------------------------*/
+
+*       XD_CTL  = 0x81000000			(0x74)
+
+*       HBUS_ACC_CTL_0 &= 0xFFFFFDFF		(0x5c)
+		       /* host bus access ctl reg 2(5e) */
+		       /* set - CPU read from memory data one clock after data is latched */
+
+*       GLOBL_INFO_0 |= 0x00004000		(0x50)
+		      /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */
+
+	PCI_1_SB_CONFIG_0 |= 0x00000400         (0x80d0)
+			/* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */
+
+	MEM_RAS_CTL_0 |= 0x3f000000		(0xcc)
+		      &= 0x3fffffff
+		      /* RAS park control reg 0(cc), park access enable is set */
+
+	HOST_RDBUF_CTL |= 0x10000000		(0x70)
+		       &= 0x10ffffff
+		      /* host read buffer control reg, enable prefetch for CPU read from DRAM control */
+
+	HBUS_ACC_CTL_0 |= 0x0100001f		(0x5c)
+		       &= 0xf1ffffff
+		      /* host bus access control register, enable CPU address bus pipe control	*/
+		      /* two outstanding requests,  *** changed to 2 from 3				*/
+		      /* enable line merge write control for CPU write to system memory, PCI 1	*/
+		      /* and PCI 0 bus memory; enable page merge write control for write to		*/
+		      /* PCI bus 0 & bus 1 memory							*/
+
+	SRAM_CTL |= 0x00004000			(0xc8)
+		 &= 0xffbff7ff
+		      /* DRAM detail timing control register 1 (ca), bit 3 set to 0	*/
+		      /* DRAM start access latency control - wait for one clock	*/
+		      /* ff9f changed to ffbf						*/
+
+	DIM0_TIM_CTL_0 = 0x737d737d             (0xc9)
+		      /* DRAM timing control for dimm0 & dimm1; set wait one clock	*/
+		      /* cycle for next data access 					*/
+
+	DIM2_TIM_CTL_0 = 0x737d737d             (0xca)
+		      /* DRAM timing control for dimm2 & dimm3; set wait one clock	*/
+		      /* cycle for next data access 					*/
+
+	DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB    (0x90)
+		      /* set dimm0 bank0 for 128 MB	*/
+
+	DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB    (0x94)
+		      /* set dimm0 for  bank1		*/
+
+	DIM0_TIM_CTL_0 = 0xf3bf0000             (0xc9)
+		      /* dimm0 timing control register; RAS - CAS latency - 4 clock		*/
+		      /* CAS access latency - 3 wait; pre-charge latency - 3 wait		*/
+		      /* pre-charge command period control - 5 clock; wait one clock		*/
+		      /* cycle for next data access; read to write access latency control	*/
+		      /* - 2 clock cycles							*/
+
+	DRAM_GBL_CTL_0 |= 0x00000100            (0xc0)
+		       &= 0xffff01ff
+		      /* memory global control register - support buffer sdram on bank 0	*/
+
+	DRAM_ECC_CTL_0 |= 0x00260000		(0xc4)
+		       &= 0xff26ffff
+		      /* enable ECC; enable read, modify, write control	*/
+
+	DRAM_REF_CTL_0 = DRAM_REF_DATA          (0xb8)
+		      /* set DRAM refresh parameters *** changed to 00940100	*/
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	DRAM_ECC_CTL_0 |= 0x20243280		(0xc4)
+		      /* turn off ecc		*/
+		      /* for SDRAM bank 0	*/
+
+	DRAM_ECC_CTL_0 |= 0x20243290            (0xc4) ?
+		      /* for SDRAM bank 1	*/
+
+
+/* Additional Stuff...*/
+
+	GLOBL_CTRL |= 0x20000b00		(0x54)
+
+	PCI_0_SB_CONFIG |= 0x04100007		(0xd0)
+		      /* PCI 0 Side band config reg*/
+
+	0x8000083c |= 0x00080000
+		      /* Disable VGA decode on PCI Bus 1 */
+
+
+/*End Additional Stuff..*/
+
+	/*--------------------------------------------------------------*/
+	/*              TERON serial port initialization code           */
+	/*--------------------------------------------------------------*/
+
+	0x84380080 |= 0x00030000
+		     /* enable super IO configuration VIA chip Register 85	*/
+		     /* Enable super I/O config mode */
+
+	0xfe0003f0 = 0xe2
+	bl delay1
+
+	0xfe0003f1 = 0x0f
+	bl delay1
+		    /* enable com1 & com2, parallel port disabled */
+
+	0xfe0003f0 = 0xe7
+	bl delay1
+		    /* let's make com1 base as 0x3f8 */
+
+	0xfe0003f1 = 0xfe
+	bl delay1
+
+	0xfe0003f0 = 0xe8
+	bl delay1
+		    /* let's make com2 base as 0x2f8 */
+
+	0xfe0003f1 = 0xbe
+
+	0x84380080 &= 0xfffdffff
+		    /* closing super IO configuration VIA chip Register 85   */
+
+
+/* -------------------------------*/
+
+	0xfe0003fb = 0x83
+	bl delay1
+		   /*latch enable word length -8 bit */         /* set mslab bit	*/
+	0xfe0003f8 = 0x0c
+	bl delay1
+		   /* set baud rate lsb for 9600 baud	*/
+	0xfe0003f9 = 0x0
+	bl delay1
+		   /* set baud rate msb for 9600 baud	*/
+	0xfe0003fb  = 0x03
+	bl delay1
+		      /* reset mslab	*/
+
+	/*--------------------------------------------------------------*/
+	/*              END TERON Serial Port Initialization Code       */
+	/*--------------------------------------------------------------*/
+
+
+	/*--------------------------------------------------------------*/
+	/*      END TERON Articia / SDRAM Initialization code           */
+	/*--------------------------------------------------------------*/
+
+Proposed from Documentation:
+
+write dmem 0xfec00cf8 0x50000080
+write dmem 0xfee00cfc 0xc0305411
+
+      Writes to index 0x50-0x53.
+      0x50: Global Information Register 0
+	    0xC0 = Little Endian CPU, Sequential order Burst
+      0x51: Global Information Register 1
+	    Read only, 0x30 = Provides PowerPC and X86 support
+      0x52: Global Information Register 2
+	    0x05 = 64/128 bit CPU bus support
+      0x53: Global Information Register 3
+	    0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted
+
+write dmem 0xfec00cf8 0x5c000080
+write dmem 0xfee00cfc 0xb300011F
+
+write dmem 0xfec00cf8 0xc8000080
+write dmem 0xfee00cfc 0x0020f100
+
+write dmem 0xfec00cf8 0x90000080
+write dmem 0xfee00cfc 0x007fe700
+
+write dmem 0xfec00cf8 0x9400080
+write dmem 0xfee00cfc 0x007fe700
+
+write dmem 0xfec00cf8 0xb0000080
+write dmem 0xfee00cfc 0x737d737d
+
+write dmem 0xfec00cf8 0xb4000080
+write dmem 0xfee00cfc 0x737d737d
+
+write dmem 0xfec00cf8 0xc0000080
+write dmem 0xfee00cfc 0x40005500
+
+write dmem 0xfec00cf8 0xb8000080
+write dmem 0xfee00cfc 0x00940100
+
+write dmem 0xfec00cf8 0xc4000080
+write dmem 0xfee00cfc 0x00003280
+
+write dmem 0xfec00cf8 0xc4000080
+write dmem 0xfee00cfc 0x00003290
diff --git a/board/MAI/AmigaOneG3SE/todo.txt b/board/MAI/AmigaOneG3SE/todo.txt
new file mode 100755
index 0000000..df25e3d
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/todo.txt
@@ -0,0 +1,3 @@
+- Init interrupt controller
+- init sdram
+- init ide controller
\ No newline at end of file
diff --git a/board/MAI/AmigaOneG3SE/u-boot.lds b/board/MAI/AmigaOneG3SE/u-boot.lds
new file mode 100755
index 0000000..b36b3cb
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/u-boot.lds
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the AmigaOneG3SE Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = ALIGN(4) /*.*/ ;
+  PROVIDE (end = ALIGN(4) /*.*/);
+}
diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.c b/board/MAI/AmigaOneG3SE/usb_uhci.c
new file mode 100755
index 0000000..14e8043
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/usb_uhci.c
@@ -0,0 +1,1178 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+
+/**********************************************************************
+ * How it works:
+ * -------------
+ * The framelist / Transfer descriptor / Queue Heads are similar like
+ * in the linux usb_uhci.c.
+ *
+ * During initialization, the following skeleton is allocated in init_skel:
+ *
+ *         framespecific           |           common chain
+ *
+ * framelist[]
+ * [  0 ]-----> TD ---------\
+ * [  1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
+ *   ...        TD ---------/
+ * [1023]-----> TD --------/
+ *
+ *              ^^             ^^         ^^          ^^          ^^
+ *              7 TDs for      1 TD for   Start of    Start of    End Chain
+ *              INT (2-128ms)  1ms-INT    CTRL Chain  BULK Chain
+ *
+ *
+ * Since this is a bootloader, the isochronous transfer descriptor have been removed.
+ *
+ * Interrupt Transfers.
+ * --------------------
+ * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * will be inserted after the appropriate (depending the interval setting) skeleton TD.
+ * If an interrupt has been detected the dev->irqhandler is called. The status and number
+ * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
+ * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
+ * the interrupt TD will be reactivated.
+ *
+ * Control Transfers
+ * -----------------
+ * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ * Bulk Transfers
+ * --------------
+ * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ *
+ */
+
+#include <common.h>
+#include <pci.h>
+
+#ifdef CONFIG_USB_UHCI
+
+#include <usb.h>
+#include "usb_uhci.h"
+
+#define USB_MAX_TEMP_TD      128  /* number of temporary TDs for bulk and control transfers */
+#define USB_MAX_TEMP_INT_TD  32   /* number of temporary TDs for Interrupt transfers */
+
+
+/*#define USB_UHCI_DEBUG */
+
+#ifdef	USB_UHCI_DEBUG
+#define	USB_UHCI_PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define USB_UHCI_PRINTF(fmt,args...)
+#endif
+
+
+static int irqvec = -1;            /* irq vector, if -1 uhci is stopped / reseted */
+unsigned int usb_base_addr;       /* base address */
+
+static uhci_td_t td_int[8];        /* Interrupt Transfer descriptors */
+static uhci_qh_t qh_cntrl;         /* control Queue Head */
+static uhci_qh_t qh_bulk;          /*  bulk Queue Head */
+static uhci_qh_t qh_end;           /* end Queue Head */
+static uhci_td_t td_last;          /* last TD (linked with end chain) */
+
+/* temporary tds */
+static uhci_td_t tmp_td[USB_MAX_TEMP_TD];          /* temporary bulk/control td's  */
+static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD];  /* temporary interrupt td's  */
+
+static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */
+
+static struct virt_root_hub rh;   /* struct for root hub */
+
+/**********************************************************************
+ * some forward decleration
+ */
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+						void *buffer, int transfer_len,struct devrequest *setup);
+
+/* fill a td with the approproiate data. Link, status, info and buffer
+ * are used by the USB controller itselfes, dev is used to identify the
+ * "connected" device
+ */
+void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status,
+					unsigned long info, unsigned long buffer, unsigned long dev)
+{
+	td->link=swap_32(link);
+	td->status=swap_32(status);
+	td->info=swap_32(info);
+	td->buffer=swap_32(buffer);
+	td->dev_ptr=dev;
+}
+
+/* fill a qh with the approproiate data. Head and element are used by the USB controller
+ * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
+ * Please note, that after completion of the td chain, the entry element is removed /
+ * marked invalid by the USB controller.
+ */
+void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element)
+{
+	qh->head=swap_32(head);
+	qh->element=swap_32(element);
+	qh->dev_ptr=0L;
+}
+
+/* get the status of a td->status
+ */
+unsigned long usb_uhci_td_stat(unsigned long status)
+{
+	unsigned long result=0;
+	result |= (status & TD_CTRL_NAK)      ? USB_ST_NAK_REC : 0;
+	result |= (status & TD_CTRL_STALLED)  ? USB_ST_STALLED : 0;
+	result |= (status & TD_CTRL_DBUFERR)  ? USB_ST_BUF_ERR : 0;
+	result |= (status & TD_CTRL_BABBLE)   ? USB_ST_BABBLE_DET : 0;
+	result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
+	result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
+	result |= (status & TD_CTRL_ACTIVE)   ? USB_ST_NOT_PROC : 0;
+	return result;
+}
+
+/* get the status and the transfered len of a td chain.
+ * called from the completion handler
+ */
+int usb_get_td_status(uhci_td_t *td,struct usb_device *dev)
+{
+	unsigned long temp,info;
+	unsigned long stat;
+	uhci_td_t *mytd=td;
+
+	if(dev->devnum==rh.devnum)
+		return 0;
+	dev->act_len=0;
+	stat=0;
+	do {
+		temp=swap_32((unsigned long)mytd->status);
+		stat=usb_uhci_td_stat(temp);
+		info=swap_32((unsigned long)mytd->info);
+		if(((info & 0xff)!= USB_PID_SETUP) &&
+				(((info >> 21) & 0x7ff)!= 0x7ff) &&
+				(temp & 0x7FF)!=0x7ff)
+		{  /* if not setup and not null data pack */
+			dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */
+		}
+		if(stat) {           /* status no ok */
+			dev->status=stat;
+			return -1;
+		}
+		temp=swap_32((unsigned long)mytd->link);
+		mytd=(uhci_td_t *)(temp & 0xfffffff0);
+	}while((temp & 0x1)==0); /* process all TDs */
+	dev->status=stat;
+	return 0; /* Ok */
+}
+
+
+/*-------------------------------------------------------------------
+ *                         LOW LEVEL STUFF
+ *          assembles QHs und TDs for control, bulk and iso
+ *-------------------------------------------------------------------*/
+
+/* Submits a control message. That is a Setup, Data and Status transfer.
+ * Routine does not wait for completion.
+ */
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+										int transfer_len,struct devrequest *setup)
+{
+	unsigned long destination, status;
+	int maxsze = usb_maxpacket(dev, pipe);
+	unsigned long dataptr;
+	int len;
+	int pktsze;
+	int i=0;
+
+	if (!maxsze) {
+		USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe);
+		return -1;
+	}
+	if(((pipe>>8)&0x7f)==rh.devnum) {
+		/* this is the root hub -> redirect it */
+		return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup);
+	}
+	USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze);
+	/* The "pipe" thing contains the destination in bits 8--18 */
+	destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */
+	/* 3 errors */
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+	/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
+	/*  Build the TD for the control request, try forever, 8 bytes of data */
+	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev);
+#if 0
+	{
+		char *sp=(char *)setup;
+		printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
+		    sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]);
+	}
+#endif
+	dataptr = (unsigned long)buffer;
+	len=transfer_len;
+
+	/* If direction is "send", change the frame from SETUP (0x2D)
+	   to OUT (0xE1). Else change it from SETUP to IN (0x69). */
+	destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN);
+	while (len > 0) {
+		/* data stage */
+		pktsze = len;
+		i++;
+		if (pktsze > maxsze)
+			pktsze = maxsze;
+		destination ^= 1 << TD_TOKEN_TOGGLE;	/* toggle DATA0/1 */
+		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
+		tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
+
+		dataptr += pktsze;
+		len -= pktsze;
+	}
+
+	/*  Build the final TD for control status */
+	/* It's only IN if the pipe is out AND we aren't expecting data */
+
+	destination &= ~UHCI_PID;
+	if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0))
+		destination |= USB_PID_IN;
+	else
+		destination |= USB_PID_OUT;
+	destination |= 1 << TD_TOKEN_TOGGLE;	/* End in Data1 */
+	i++;
+	status &=~TD_CTRL_SPD;
+	/* no limit on errors on final packet , 0 bytes of data */
+	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev);
+	tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);	/* queue status td */
+	/*	usb_show_td(i+1);*/
+	USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i);
+	/* first mark the control QH element terminated */
+	qh_cntrl.element=0xffffffffL;
+	/* set qh active */
+	qh_cntrl.dev_ptr=(unsigned long)dev;
+	/* fill in tmp_td_chain */
+	qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]);
+	return 0;
+}
+
+/*-------------------------------------------------------------------
+ * Prepare TDs for bulk transfers.
+ */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len)
+{
+	unsigned long destination, status,info;
+	unsigned long dataptr;
+	int maxsze = usb_maxpacket(dev, pipe);
+	int len;
+	int i=0;
+
+	if(transfer_len < 0) {
+		printf("Negative transfer length in submit_bulk\n");
+		return -1;
+	}
+	if (!maxsze)
+		return -1;
+	/* The "pipe" thing contains the destination in bits 8--18. */
+	destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe);
+	/* 3 errors */
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+	/*	((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
+	/* Build the TDs for the bulk request */
+	len = transfer_len;
+	dataptr = (unsigned long)buffer;
+	do {
+		int pktsze = len;
+		if (pktsze > maxsze)
+			pktsze = maxsze;
+		/* pktsze bytes of data  */
+		info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) |
+			(usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE);
+
+		if((len-pktsze)==0)
+			status |= TD_CTRL_IOC;	/* last one generates INT */
+
+		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
+		if(i>0)
+			tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
+		i++;
+		dataptr += pktsze;
+		len -= pktsze;
+		usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+	} while (len > 0);
+	/* first mark the bulk QH element terminated */
+	qh_bulk.element=0xffffffffL;
+	/* set qh active */
+	qh_bulk.dev_ptr=(unsigned long)dev;
+	/* fill in tmp_td_chain */
+	qh_bulk.element=swap_32((unsigned long)&tmp_td[0]);
+	return 0;
+}
+
+
+/* search a free interrupt td
+ */
+uhci_td_t *uhci_alloc_int_td(void)
+{
+	int i;
+	for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
+		if(tmp_int_td[i].dev_ptr==0) /* no device assigned -> free TD */
+			return &tmp_int_td[i];
+	}
+	return NULL;
+}
+
+#if 0
+void uhci_show_temp_int_td(void)
+{
+	int i;
+	for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
+		if((tmp_int_td[i].dev_ptr&0x01)!=0x1L) /* no device assigned -> free TD */
+			printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr);
+	}
+	printf("all others temp_tds are free\n");
+}
+#endif
+/*-------------------------------------------------------------------
+ * submits USB interrupt (ie. polling ;-)
+ */
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval)
+{
+	int nint, n;
+	unsigned long status, destination;
+	unsigned long info,tmp;
+	uhci_td_t *mytd;
+	if (interval < 0 || interval >= 256)
+		return -1;
+
+	if (interval == 0)
+		nint = 0;
+	else {
+		for (nint = 0, n = 1; nint <= 8; nint++, n += n)	/* round interval down to 2^n */
+		 {
+			if(interval < n) {
+				interval = n / 2;
+				break;
+			}
+		}
+		nint--;
+	}
+
+	USB_UHCI_PRINTF("Rounded interval to %i, chain  %i\n", interval, nint);
+	mytd=uhci_alloc_int_td();
+	if(mytd==NULL) {
+		printf("No free INT TDs found\n");
+		return -1;
+	}
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
+/*		(urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
+*/
+
+	destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21);
+
+	info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
+	tmp = swap_32(td_int[nint].link);
+	usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev);
+	/* Link it */
+	tmp = swap_32((unsigned long)mytd);
+	td_int[nint].link=tmp;
+
+	usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+
+	return 0;
+}
+
+/**********************************************************************
+ * Low Level functions
+ */
+
+
+void reset_hc(void)
+{
+
+	/* Global reset for 100ms */
+	out16r( usb_base_addr + USBPORTSC1,0x0204);
+	out16r( usb_base_addr + USBPORTSC2,0x0204);
+	out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS);
+	/* Turn off all interrupts */
+	out16r(usb_base_addr + USBINTR,0);
+	wait_ms(50);
+	out16r( usb_base_addr + USBCMD,0);
+	wait_ms(10);
+}
+
+void start_hc(void)
+{
+	int timeout = 1000;
+
+	while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) {
+		if (!--timeout) {
+			printf("USBCMD_HCRESET timed out!\n");
+			break;
+		}
+	}
+	/* Turn on all interrupts */
+	out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP);
+	/* Start at frame 0 */
+	out16r(usb_base_addr + USBFRNUM,0);
+	/* set Framebuffer base address */
+	out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist);
+	/* Run and mark it configured with a 64-byte max packet */
+	out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
+}
+
+/* Initialize the skeleton
+ */
+void usb_init_skel(void)
+{
+	unsigned long temp;
+	int n;
+
+	for(n=0;n<USB_MAX_TEMP_INT_TD;n++)
+		tmp_int_td[n].dev_ptr=0L; /* no devices connected */
+	/* last td */
+	usb_fill_td(&td_last,UHCI_PTR_TERM,TD_CTRL_IOC ,0,0,0L);
+  /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */
+	/* End Queue Header */
+	usb_fill_qh(&qh_end,UHCI_PTR_TERM,(unsigned long)&td_last);
+	/* Bulk Queue Header */
+	temp=(unsigned long)&qh_end;
+	usb_fill_qh(&qh_bulk,temp | UHCI_PTR_QH,UHCI_PTR_TERM);
+	/* Control Queue Header */
+	temp=(unsigned long)&qh_bulk;
+	usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH,UHCI_PTR_TERM);
+	/* 1ms Interrupt td */
+	temp=(unsigned long)&qh_cntrl;
+	usb_fill_td(&td_int[0],temp | UHCI_PTR_QH,0,0,0,0L);
+	temp=(unsigned long)&td_int[0];
+	for(n=1; n<8; n++)
+		usb_fill_td(&td_int[n],temp,0,0,0,0L);
+	for (n = 0; n < 1024; n++) {
+	/* link all framelist pointers to one of the interrupts */
+		int m, o;
+		if ((n&127)==127)
+			framelist[n]= swap_32((unsigned long)&td_int[0]);
+		else
+			for (o = 1, m = 2; m <= 128; o++, m += m)
+				if ((n & (m - 1)) == ((m - 1) / 2))
+						framelist[n]= swap_32((unsigned long)&td_int[o]);
+	}
+}
+
+/* check the common skeleton for completed transfers, and update the status
+ * of the "connected" device. Called from the IRQ routine.
+ */
+void usb_check_skel(void)
+{
+	struct usb_device *dev;
+	/* start with the control qh */
+	if(qh_cntrl.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
+	{
+		dev=(struct usb_device *)qh_cntrl.dev_ptr;
+		usb_get_td_status(&tmp_td[0],dev); /* update status */
+		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+			qh_cntrl.dev_ptr=0;
+		}
+	}
+	/* now process the bulk */
+	if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
+	{
+		dev=(struct usb_device *)qh_bulk.dev_ptr;
+		usb_get_td_status(&tmp_td[0],dev); /* update status */
+		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+			qh_bulk.dev_ptr=0;
+		}
+	}
+}
+
+/* check the interrupt chain, ubdate the status of the appropriate device,
+ * call the appropriate irqhandler and reactivate the TD if the irqhandler
+ * returns with 1
+ */
+void usb_check_int_chain(void)
+{
+	int i,res;
+	unsigned long link,status;
+	struct usb_device *dev;
+	uhci_td_t *td,*prevtd;
+
+	for(i=0;i<8;i++) {
+		prevtd=&td_int[i]; /* the first previous td is the skeleton td */
+		link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
+		td=(uhci_td_t *)link; /* assign it */
+		/* all interrupt TDs are finally linked to the td_int[0].
+ 		 * so we process all until we find the td_int[0].
+		 * if int0 chain points to a QH, we're also done
+	   */
+		while(((i>0) && (link != (unsigned long)&td_int[0])) ||
+					((i==0) && !(swap_32(td->link) &  UHCI_PTR_QH)))
+		{
+			/* check if a device is assigned with this td */
+			status=swap_32(td->status);
+			if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) {
+				/* td is not active and a device is assigned -> call irqhandler */
+				dev=(struct usb_device *)td->dev_ptr;
+				dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */
+				dev->irq_status=usb_uhci_td_stat(status); /* get status */
+				res=dev->irq_handle(dev); /* call irqhandler */
+				if(res==1) {
+					/* reactivate */
+					status|=TD_CTRL_ACTIVE;
+					td->status=swap_32(status);
+					prevtd=td; /* previous td = this td */
+				}
+				else {
+					prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */
+					/* remove device pointer */
+					td->dev_ptr=0L;
+				}
+			} /* if we call the irq handler */
+			link=swap_32(td->link) & 0xfffffff0; /* next in chain */
+			td=(uhci_td_t *)link; /* assign it */
+		} /* process all td in this int chain */
+	} /* next interrupt chain */
+}
+
+
+/* usb interrupt service routine.
+ */
+void handle_usb_interrupt(void)
+{
+	unsigned short status;
+
+	/*
+	 * Read the interrupt status, and write it back to clear the
+	 * interrupt cause
+	 */
+
+	status = in16r(usb_base_addr + USBSTS);
+
+	if (!status)		/* shared interrupt, not mine */
+		return;
+	if (status != 1) {
+		/* remove host controller halted state */
+		if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) {
+			out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD));
+		}
+	}
+	usb_check_int_chain(); /* call interrupt handlers for int tds */
+	usb_check_skel(); /* call completion handler for common transfer routines */
+	out16r(usb_base_addr+USBSTS,status);
+}
+
+
+/* init uhci
+ */
+int usb_lowlevel_init(void)
+{
+	unsigned char temp;
+	int	busdevfunc;
+/*
+ * HJF - configure IRQ and base from variables optionally.
+ */
+	char *s;
+
+
+	busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */
+	if(busdevfunc==-1) {
+		printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID);
+		return -1;
+	}
+
+#if 1
+	s = getenv("usb_irq");
+	if (s)
+	{
+	    temp = atoi(s);
+	    pci_write_config_byte(busdevfunc, PCI_INTERRUPT_LINE, temp);
+	}
+	else
+#endif
+	    pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp);
+
+	s = getenv("usb_base");
+	if (s)
+	{
+	    unsigned long temp2;
+	    temp2 = atoi(s);
+	    pci_write_config_dword(busdevfunc, PCI_BASE_ADDRESS_4, temp2|0x01);
+	}
+
+	irqvec = temp;
+	irq_free_handler(irqvec);
+	USB_UHCI_PRINTF("Interrupt Line = %d\n",irqvec);
+	pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp);
+	USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp);
+	pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
+	USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
+	usb_base_addr&=0xFFFFFFF0;
+	usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS;
+	rh.devnum = 0;
+	usb_init_skel();
+	reset_hc();
+	start_hc();
+	irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL);
+	irq_install_handler(0, (interrupt_handler_t *)handle_usb_interrupt, NULL);
+
+	return 0;
+}
+
+/* stop uhci
+ */
+int usb_lowlevel_stop(void)
+{
+	if(irqvec==-1)
+		return 1;
+	irq_free_handler(irqvec);
+	irq_free_handler(0);
+	reset_hc();
+	irqvec=-1;
+	return 0;
+}
+
+/*******************************************************************************************
+ * Virtual Root Hub
+ * Since the uhci does not have a real HUB, we simulate one ;-)
+ */
+#undef	USB_RH_DEBUG
+
+#ifdef	USB_RH_DEBUG
+#define	USB_RH_PRINTF(fmt,args...)	printf (fmt ,##args)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex);
+static void usb_display_Req(unsigned short req);
+#else
+#define USB_RH_PRINTF(fmt,args...)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {}
+static void usb_display_Req(unsigned short req) {}
+#endif
+
+static unsigned char root_hub_dev_des[] =
+{
+	0x12,			/*  __u8  bLength; */
+	0x01,			/*  __u8  bDescriptorType; Device */
+	0x00,			/*  __u16 bcdUSB; v1.0 */
+	0x01,
+	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  bDeviceSubClass; */
+	0x00,			/*  __u8  bDeviceProtocol; */
+	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,			/*  __u16 idVendor; */
+	0x00,
+	0x00,			/*  __u16 idProduct; */
+	0x00,
+	0x00,			/*  __u16 bcdDevice; */
+	0x00,
+	0x01,			/*  __u8  iManufacturer; */
+	0x00,			/*  __u8  iProduct; */
+	0x00,			/*  __u8  iSerialNumber; */
+	0x01			/*  __u8  bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static unsigned char root_hub_config_des[] =
+{
+	0x09,			/*  __u8  bLength; */
+	0x02,			/*  __u8  bDescriptorType; Configuration */
+	0x19,			/*  __u16 wTotalLength; */
+	0x00,
+	0x01,			/*  __u8  bNumInterfaces; */
+	0x01,			/*  __u8  bConfigurationValue; */
+	0x00,			/*  __u8  iConfiguration; */
+	0x40,			/*  __u8  bmAttributes;
+				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,			/*  __u8  MaxPower; */
+
+     /* interface */
+	0x09,			/*  __u8  if_bLength; */
+	0x04,			/*  __u8  if_bDescriptorType; Interface */
+	0x00,			/*  __u8  if_bInterfaceNumber; */
+	0x00,			/*  __u8  if_bAlternateSetting; */
+	0x01,			/*  __u8  if_bNumEndpoints; */
+	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  if_bInterfaceSubClass; */
+	0x00,			/*  __u8  if_bInterfaceProtocol; */
+	0x00,			/*  __u8  if_iInterface; */
+
+     /* endpoint */
+	0x07,			/*  __u8  ep_bLength; */
+	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
+	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
+	0x08,			/*  __u16 ep_wMaxPacketSize; 8 Bytes */
+	0x00,
+	0xff			/*  __u8  ep_bInterval; 255 ms */
+};
+
+
+static unsigned char root_hub_hub_des[] =
+{
+	0x09,			/*  __u8  bLength; */
+	0x29,			/*  __u8  bDescriptorType; Hub-descriptor */
+	0x02,			/*  __u8  bNbrPorts; */
+	0x00,			/* __u16  wHubCharacteristics; */
+	0x00,
+	0x01,			/*  __u8  bPwrOn2pwrGood; 2ms */
+	0x00,			/*  __u8  bHubContrCurrent; 0 mA */
+	0x00,			/*  __u8  DeviceRemovable; *** 7 Ports max *** */
+	0xff			/*  __u8  PortPwrCtrlMask; *** 7 ports max *** */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+	28,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'U',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'C',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'I',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+};
+
+
+/*
+ * Root Hub Control Pipe (interrupt Pipes are not supported)
+ */
+
+
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd)
+{
+	void *data = buffer;
+	int leni = transfer_len;
+	int len = 0;
+	int status = 0;
+	int stat = 0;
+	int i;
+
+	unsigned short cstatus;
+
+	unsigned short bmRType_bReq;
+	unsigned short wValue;
+	unsigned short wIndex;
+	unsigned short wLength;
+
+	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+		printf("Root-Hub submit IRQ: NOT implemented\n");
+#if 0
+		uhci->rh.urb = urb;
+		uhci->rh.send = 1;
+		uhci->rh.interval = urb->interval;
+		rh_init_int_timer (urb);
+#endif
+		return 0;
+	}
+	bmRType_bReq = cmd->requesttype | cmd->request << 8;
+	wValue = swap_16(cmd->value);
+	wIndex = swap_16(cmd->index);
+	wLength = swap_16(cmd->length);
+	usb_display_Req(bmRType_bReq);
+	for (i = 0; i < 8; i++)
+		rh.c_p_r[i] = 0;
+	USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n",
+	     dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength);
+
+	switch (bmRType_bReq) {
+		/* Request Destination:
+		   without flags: Device,
+		   RH_INTERFACE: interface,
+		   RH_ENDPOINT: endpoint,
+		   RH_CLASS means HUB here,
+		   RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
+		 */
+
+	case RH_GET_STATUS:
+		*(unsigned short *) data = swap_16(1);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_INTERFACE:
+		*(unsigned short *) data = swap_16(0);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_ENDPOINT:
+		*(unsigned short *) data = swap_16(0);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_CLASS:
+		*(unsigned long *) data = swap_32(0);
+		len=4;
+		break;	/* hub power ** */
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+
+		status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
+		cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
+			((status & USBPORTSC_PEC) >> (3 - 1)) |
+			(rh.c_p_r[wIndex - 1] << (0 + 4));
+		status = (status & USBPORTSC_CCS) |
+			((status & USBPORTSC_PE) >> (2 - 1)) |
+			((status & USBPORTSC_SUSP) >> (12 - 2)) |
+			((status & USBPORTSC_PR) >> (9 - 4)) |
+			(1 << 8) |	/* power on ** */
+			((status & USBPORTSC_LSDA) << (-8 + 9));
+
+		*(unsigned short *) data = swap_16(status);
+		*(unsigned short *) (data + 2) = swap_16(cstatus);
+		len=4;
+		break;
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		switch (wValue) {
+		case (RH_ENDPOINT_STALL):
+			len=0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		switch (wValue) {
+		case (RH_C_HUB_OVER_CURRENT):
+			len=0;	/* hub power over current ** */
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		usb_display_wValue(wValue,wIndex);
+		switch (wValue) {
+		case (RH_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) & ~USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_SUSPEND):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) & ~USBPORTSC_SUSP;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_POWER):
+			len=0;	/* port power ** */
+			break;
+		case (RH_C_PORT_CONNECTION):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_CSC;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_C_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PEC;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_C_PORT_SUSPEND):
+/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
+			len=0;
+			break;
+		case (RH_C_PORT_OVER_CURRENT):
+			len=0;
+			break;
+		case (RH_C_PORT_RESET):
+			rh.c_p_r[wIndex - 1] = 0;
+			len=0;
+			break;
+		}
+		break;
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		usb_display_wValue(wValue,wIndex);
+		switch (wValue) {
+		case (RH_PORT_SUSPEND):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_SUSP;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_RESET):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PR;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			wait_ms(10);
+			status = (status & 0xfff5) & ~USBPORTSC_PR;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			udelay(10);
+			status = (status & 0xfff5) | USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			wait_ms(10);
+			status = (status & 0xfff5) | 0xa;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_POWER):
+			len=0;	/* port power ** */
+			break;
+		case (RH_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		}
+		break;
+
+	case RH_SET_ADDRESS:
+		rh.devnum = wValue;
+		len=0;
+		break;
+	case RH_GET_DESCRIPTOR:
+		switch ((wValue & 0xff00) >> 8) {
+		case (0x01):	/* device descriptor */
+			i=sizeof(root_hub_config_des);
+			status=i > wLength ? wLength : i;
+			len = leni > status ? status : leni;
+			memcpy (data, root_hub_dev_des, len);
+			break;
+		case (0x02):	/* configuration descriptor */
+			i=sizeof(root_hub_config_des);
+			status=i > wLength ? wLength : i;
+			len = leni > status ? status : leni;
+			memcpy (data, root_hub_config_des, len);
+			break;
+		case (0x03):	/*string descriptors */
+			if(wValue==0x0300) {
+				i=sizeof(root_hub_str_index0);
+				status = i > wLength ? wLength : i;
+				len = leni > status ? status : leni;
+				memcpy (data, root_hub_str_index0, len);
+				break;
+			}
+			if(wValue==0x0301) {
+				i=sizeof(root_hub_str_index1);
+				status = i > wLength ? wLength : i;
+				len = leni > status ? status : leni;
+				memcpy (data, root_hub_str_index1, len);
+				break;
+			}
+			stat = USB_ST_STALLED;
+		}
+		break;
+
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		root_hub_hub_des[2] = 2;
+		i=sizeof(root_hub_hub_des);
+		status= i > wLength ? wLength : i;
+		len = leni > status ? status : leni;
+		memcpy (data, root_hub_hub_des, len);
+		break;
+	case RH_GET_CONFIGURATION:
+		*(unsigned char *) data = 0x01;
+		len = 1;
+		break;
+	case RH_SET_CONFIGURATION:
+		len=0;
+		break;
+	default:
+		stat = USB_ST_STALLED;
+	}
+	USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat,
+	     in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2));
+	dev->act_len=len;
+	dev->status=stat;
+	return stat;
+
+}
+
+/********************************************************************************
+ * Some Debug Routines
+ */
+
+#ifdef	USB_RH_DEBUG
+
+static void usb_display_Req(unsigned short req)
+{
+	USB_RH_PRINTF("- Root-Hub Request: ");
+	switch (req) {
+	case RH_GET_STATUS:
+		USB_RH_PRINTF("Get Status ");
+		break;
+	case RH_GET_STATUS | RH_INTERFACE:
+		USB_RH_PRINTF("Get Status Interface ");
+		break;
+	case RH_GET_STATUS | RH_ENDPOINT:
+		USB_RH_PRINTF("Get Status Endpoint ");
+		break;
+	case RH_GET_STATUS | RH_CLASS:
+		USB_RH_PRINTF("Get Status Class");
+		break;	/* hub power ** */
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Get Status Class Others");
+		break;
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		USB_RH_PRINTF("Clear Feature Endpoint ");
+		break;
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		USB_RH_PRINTF("Clear Feature Class ");
+		break;
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Clear Feature Other Class ");
+		break;
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Set Feature Other Class ");
+		break;
+	case RH_SET_ADDRESS:
+		USB_RH_PRINTF("Set Address ");
+		break;
+	case RH_GET_DESCRIPTOR:
+		USB_RH_PRINTF("Get Descriptor ");
+		break;
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		USB_RH_PRINTF("Get Descriptor Class ");
+		break;
+	case RH_GET_CONFIGURATION:
+		USB_RH_PRINTF("Get Configuration ");
+		break;
+	case RH_SET_CONFIGURATION:
+		USB_RH_PRINTF("Get Configuration ");
+		break;
+	default:
+		USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req);
+	}
+	USB_RH_PRINTF("\n");
+
+}
+
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex)
+{
+	switch (wValue) {
+		case (RH_PORT_ENABLE):
+			USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex);
+			break;
+		case (RH_PORT_SUSPEND):
+			USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex);
+			break;
+		case (RH_PORT_POWER):
+			USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex);
+			break;
+		case (RH_C_PORT_CONNECTION):
+			USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_ENABLE):
+			USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_SUSPEND):
+			USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_OVER_CURRENT):
+			USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_RESET):
+			USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex);
+			break;
+		default:
+			USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex);
+			break;
+	}
+}
+
+#endif
+
+
+#ifdef	USB_UHCI_DEBUG
+
+static int usb_display_td(uhci_td_t *td)
+{
+	unsigned long tmp;
+	int valid;
+
+	printf("TD at %p:\n",td);
+
+	tmp=swap_32(td->link);
+	printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0,
+		((tmp & 0x4)==0x4) ? "Depth" : "Breath",
+		((tmp & 0x2)==0x2) ? "QH" : "TD",
+		((tmp & 0x1)==0x1) ? "invalid" : "valid");
+	valid=((tmp & 0x1)==0x0);
+	tmp=swap_32(td->status);
+	printf("     %s %ld Errors %s %s %s \n     %s %s %s %s %s %s\n     Len 0x%lX\n",
+		(((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable",
+		((tmp>>28)&0x3),
+		(((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed",
+		(((tmp>>25)&0x1)==0x1) ? "ISO " : "",
+		(((tmp>>24)&0x1)==0x1) ? "IOC " : "",
+		(((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ",
+		(((tmp>>22)&0x1)==0x1) ? "Stalled" : "",
+		(((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "",
+		(((tmp>>20)&0x1)==0x1) ? "Babble" : "",
+		(((tmp>>19)&0x1)==0x1) ? "NAK" : "",
+		(((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "",
+		(tmp&0x7ff));
+	tmp=swap_32(td->info);
+	printf("     MaxLen 0x%lX\n",((tmp>>21)&0x7FF));
+	printf("     %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "",
+		((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF);
+	tmp=swap_32(td->buffer);
+	printf("     Buffer 0x%08lX\n",tmp);
+	printf("     DEV %08lX\n",td->dev_ptr);
+	return valid;
+}
+
+
+void usb_show_td(int max)
+{
+	int i;
+	if(max>0) {
+		for(i=0;i<max;i++) {
+			usb_display_td(&tmp_td[i]);
+		}
+	}
+	else {
+		i=0;
+		do {
+			printf("tmp_td[%d]\n",i);
+		}while(usb_display_td(&tmp_td[i++]));
+	}
+}
+
+
+#endif
+#endif /* CONFIG_USB_UHCI */
+
+/* EOF */
diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.h b/board/MAI/AmigaOneG3SE/usb_uhci.h
new file mode 100755
index 0000000..3387157
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/usb_uhci.h
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_UHCI_H_
+#define _USB_UHCI_H_
+
+#undef USB_UHCI_VEND_ID
+#define USB_UHCI_VEND_ID PCI_VENDOR_ID_VIA
+#undef USB_UHCI_DEV_ID
+#define USB_UHCI_DEV_ID 0x3038
+
+/* Command register */
+#define USBCMD		0
+#define   USBCMD_RS       0x0001	/* Run/Stop */
+#define   USBCMD_HCRESET  0x0002	/* Host reset */
+#define   USBCMD_GRESET   0x0004	/* Global reset */
+#define   USBCMD_EGSM     0x0008	/* Global Suspend Mode */
+#define   USBCMD_FGR      0x0010	/* Force Global Resume */
+#define   USBCMD_SWDBG    0x0020	/* SW Debug mode */
+#define   USBCMD_CF       0x0040	/* Config Flag (sw only) */
+#define   USBCMD_MAXP     0x0080	/* Max Packet (0 = 32, 1 = 64) */
+
+/* Status register */
+#define USBSTS		2
+#define   USBSTS_USBINT   0x0001	/* Interrupt due to IOC */
+#define   USBSTS_ERROR    0x0002	/* Interrupt due to error */
+#define   USBSTS_RD       0x0004	/* Resume Detect */
+#define   USBSTS_HSE      0x0008	/* Host System Error - basically PCI problems */
+#define   USBSTS_HCPE     0x0010	/* Host Controller Process Error - the scripts were buggy */
+#define   USBSTS_HCH      0x0020	/* HC Halted */
+
+/* Interrupt enable register */
+#define USBINTR		4
+#define   USBINTR_TIMEOUT 0x0001	/* Timeout/CRC error enable */
+#define   USBINTR_RESUME  0x0002	/* Resume interrupt enable */
+#define   USBINTR_IOC     0x0004	/* Interrupt On Complete enable */
+#define   USBINTR_SP      0x0008	/* Short packet interrupt enable */
+
+#define USBFRNUM      6
+#define USBFLBASEADD  8
+#define USBSOF        12
+
+/* USB port status and control registers */
+#define USBPORTSC1	16
+#define USBPORTSC2	18
+#define   USBPORTSC_CCS   0x0001	/* Current Connect Status ("device present") */
+#define   USBPORTSC_CSC   0x0002	/* Connect Status Change */
+#define   USBPORTSC_PE    0x0004	/* Port Enable */
+#define   USBPORTSC_PEC   0x0008	/* Port Enable Change */
+#define   USBPORTSC_LS    0x0030	/* Line Status */
+#define   USBPORTSC_RD    0x0040	/* Resume Detect */
+#define   USBPORTSC_LSDA  0x0100	/* Low Speed Device Attached */
+#define   USBPORTSC_PR    0x0200	/* Port Reset */
+#define   USBPORTSC_SUSP  0x1000	/* Suspend */
+
+/* Legacy support register */
+#define USBLEGSUP 0xc0
+#define USBLEGSUP_DEFAULT 0x2000	/* only PIRQ enable set */
+
+#define UHCI_NULL_DATA_SIZE 0x7ff	/* for UHCI controller TD */
+#define UHCI_PID            0xff	/* PID MASK */
+
+#define UHCI_PTR_BITS       0x000F
+#define UHCI_PTR_TERM       0x0001
+#define UHCI_PTR_QH         0x0002
+#define UHCI_PTR_DEPTH      0x0004
+
+/* for TD <status>: */
+#define TD_CTRL_SPD         (1 << 29)	/* Short Packet Detect */
+#define TD_CTRL_C_ERR_MASK  (3 << 27)	/* Error Counter bits */
+#define TD_CTRL_LS          (1 << 26)	/* Low Speed Device */
+#define TD_CTRL_IOS         (1 << 25)	/* Isochronous Select */
+#define TD_CTRL_IOC         (1 << 24)	/* Interrupt on Complete */
+#define TD_CTRL_ACTIVE      (1 << 23)	/* TD Active */
+#define TD_CTRL_STALLED     (1 << 22)	/* TD Stalled */
+#define TD_CTRL_DBUFERR     (1 << 21)	/* Data Buffer Error */
+#define TD_CTRL_BABBLE      (1 << 20)	/* Babble Detected */
+#define TD_CTRL_NAK         (1 << 19)	/* NAK Received */
+#define TD_CTRL_CRCTIMEO    (1 << 18)	/* CRC/Time Out Error */
+#define TD_CTRL_BITSTUFF    (1 << 17)	/* Bit Stuff Error */
+#define TD_CTRL_ACTLEN_MASK 0x7ff	/* actual length, encoded as n - 1 */
+
+#define TD_CTRL_ANY_ERROR	(TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
+				 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
+
+#define TD_TOKEN_TOGGLE		19
+
+/* ------------------------------------------------------------------------------------
+   Virtual Root HUB
+   ------------------------------------------------------------------------------------ */
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+/* Our Vendor Specific feature */
+#define RH_REMOVE_EP               0x00
+
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+
+/* Transfer descriptor structure */
+typedef struct {
+	unsigned long link;     /* next td/qh (LE)*/
+	unsigned long status;   /* status of the td */
+	unsigned long info;     /* Max Lenght / Endpoint / device address and PID */
+	unsigned long buffer;   /* pointer to data buffer (LE) */
+	unsigned long dev_ptr;  /* pointer to the assigned device (BE) */
+	unsigned long res[3];   /* reserved (TDs must be 8Byte aligned) */
+} uhci_td_t, *puhci_td_t;
+
+/* Queue Header structure */
+typedef struct {
+	unsigned long head;       /* Next QH (LE)*/
+	unsigned long element;		/* Queue element pointer (LE) */
+	unsigned long res[5];     /* reserved */
+	unsigned long dev_ptr;    /* if 0 no tds have been assigned to this qh */
+} uhci_qh_t, *puhci_qh_t;
+
+struct virt_root_hub {
+	int devnum;		            /* Address of Root Hub endpoint */
+	int numports;             /* number of ports */
+	int c_p_r[8];             /* C_PORT_RESET */
+};
+
+
+#endif /* _USB_UHCI_H_ */
diff --git a/board/MAI/AmigaOneG3SE/via686.c b/board/MAI/AmigaOneG3SE/via686.c
new file mode 100755
index 0000000..c797e47
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/via686.c
@@ -0,0 +1,299 @@
+/*
+ * (C) Copyright 2002
+ * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <pci.h>
+#include <ata.h>
+#include "memio.h"
+#include "articiaS.h"
+#include "via686.h"
+#include "i8259.h"
+
+#undef VIA_DEBUG
+
+#ifdef  VIA_DEBUG
+#define PRINTF(fmt,args...)     printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+
+/*  Setup the ISA-to-PCI host bridge */
+void via_isa_init(pci_dev_t dev, struct pci_config_table *table)
+{
+    char regval;
+    if (PCI_FUNC(dev) == 0)
+    {
+	PRINTF("... PCI-to-ISA bridge, dev=0x%X\n", dev);
+
+	/*  Enable I/O Recovery time */
+	pci_write_config_byte(dev, 0x40, 0x08);
+
+	/*  Enable ISA refresh */
+	pci_write_config_byte(dev, 0x41, 0x41); /*  was 01 */
+
+	/*  Enable ISA line buffer */
+	pci_write_config_byte(dev, 0x45, 0x80);
+
+	/*  Gate INTR, and flush line buffer */
+	pci_write_config_byte(dev, 0x46, 0x60);
+
+	/*  Enable EISA ports 4D0/4D1. Do we need this ? */
+	pci_write_config_byte(dev, 0x47, 0xe6); /*  was 20 */
+
+	/*  512 K PCI Decode */
+	pci_write_config_byte(dev, 0x48, 0x01);
+
+	/*  Wait for PGNT before grant to ISA Master/DMA */
+	/*  ports 0-FF to SDBus */
+	/*  IRQ 14 and 15 for ide 0/1 */
+	pci_write_config_byte(dev, 0x4a, 0x04); /*  Was c4 */
+
+	/*  Plug'n'Play */
+	/*  Parallel DRQ 3, Floppy DRQ 2 (default) */
+	pci_write_config_byte(dev, 0x50, 0x0e);
+
+	/*  IRQ Routing for Floppy and Parallel port */
+	/*  IRQ 6 for floppy, IRQ 7 for parallel port */
+	pci_write_config_byte(dev, 0x51, 0x76);
+
+	/*  IRQ Routing for serial ports (take IRQ 3 and 4) */
+	pci_write_config_byte(dev, 0x52, 0x34);
+
+	/*  All IRQ's level triggered. */
+	pci_write_config_byte(dev, 0x54, 0x00);
+
+	/*  PCI IRQ's all at IRQ 9 */
+	pci_write_config_byte(dev, 0x55, 0x90);
+	pci_write_config_byte(dev, 0x56, 0x99);
+	pci_write_config_byte(dev, 0x57, 0x90);
+
+	/*  Enable Keyboard */
+	pci_read_config_byte(dev, 0x5A, &regval);
+	regval |= 0x01;
+	pci_write_config_byte(dev, 0x5A, regval);
+
+	pci_write_config_byte(dev, 0x80, 0);
+	pci_write_config_byte(dev, 0x85, 0x01);
+
+/* 	pci_write_config_byte(dev, 0x77, 0x00); */
+    }
+}
+
+/*
+ * Initialize PNP irq routing
+ */
+
+void via_init_irq_routing(uint8 irq_map[])
+{
+    char *s;
+    uint8 level_edge_bits = 0xf;
+
+    /* Set irq routings */
+    pci_write_cfg_byte(0, 7<<3, 0x55, irq_map[0]<<4);
+    pci_write_cfg_byte(0, 7<<3, 0x56, irq_map[1] | irq_map[2]<<4);
+    pci_write_cfg_byte(0, 7<<3, 0x57, irq_map[3]<<4);
+
+    /*
+     * Gather level/edge bits
+     * Default is to assume level triggered
+     */
+
+    s = getenv("pci_irqa_select");
+    if (s && strcmp(s, "level") == 0)
+	level_edge_bits &= ~0x01;
+
+    s = getenv("pci_irqb_select");
+    if (s && strcmp(s, "level") == 0)
+	level_edge_bits &= ~0x02;
+
+    s = getenv("pci_irqc_select");
+    if (s && strcmp(s, "level") == 0)
+	level_edge_bits &= ~0x04;
+
+    s = getenv("pci_irqd_select");
+    if (s && strcmp(s, "level") == 0)
+	level_edge_bits &= ~0x08;
+
+    PRINTF("IRQ map\n");
+    PRINTF("%d: %s\n", irq_map[0], level_edge_bits&0x1 ? "edge" : "level");
+    PRINTF("%d: %s\n", irq_map[1], level_edge_bits&0x2 ? "edge" : "level");
+    PRINTF("%d: %s\n", irq_map[2], level_edge_bits&0x4 ? "edge" : "level");
+    PRINTF("%d: %s\n", irq_map[3], level_edge_bits&0x8 ? "edge" : "level");
+    pci_write_cfg_byte(0, 7<<3, 0x54, level_edge_bits);
+
+    PRINTF("%02x %02x %02x %02x\n", pci_read_cfg_byte(0, 7<<3, 0x54),
+	   pci_read_cfg_byte(0, 7<<3, 0x55), pci_read_cfg_byte(0, 7<<3, 0x56),
+	   pci_read_cfg_byte(0, 7<<3, 0x57));
+}
+
+
+/*  Setup the IDE controller. This doesn't seem to work yet. I/O to an IDE controller port */
+/*  always return the last character output on the serial port (!) */
+/*  This function is called by the pnp-library when it encounters 0:7:1 */
+void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
+{
+    PRINTF("... IDE controller, dev=0x%X\n", dev);
+
+    /*  Enable both IDE channels. */
+    pci_write_config_byte(dev, 0x40, 0x03);
+    /*  udelay(10000); */
+    /*  udelay(10000); */
+
+    /*  Enable IO Space */
+    pci_write_config_word(dev, 0x04, 0x03);
+
+    /*  Set to compatibility mode */
+    pci_write_config_byte(dev, 0x09, 0x8A); /*  WAS: 0x8f); */
+
+    /*  Set to legacy interrupt mode */
+    pci_write_config_byte(dev, 0x3d, 0x00); /* WAS: 0x01); */
+
+}
+
+
+/*  Set the base address of the floppy controller to 0x3F0 */
+void via_fdc_init(pci_dev_t dev)
+{
+    unsigned char c;
+    /*  Enable Configuration mode */
+    pci_read_config_byte(dev, 0x85, &c);
+    c |= 0x02;
+    pci_write_config_byte(dev, 0x85, c);
+
+    /*  Set floppy controller port to 0x3F0. */
+    SIO_WRITE_CONFIG(0xE3, (0x3F<<2));
+
+    /*  Enable floppy controller */
+    SIO_READ_CONFIG(0xE2, c);
+    c |= 0x10;
+    SIO_WRITE_CONFIG(0xE2, c);
+
+    /*  Switch of configuration mode */
+    pci_read_config_byte(dev, 0x85, &c);
+    c &= ~0x02;
+    pci_write_config_byte(dev, 0x85, c);
+}
+
+/*  Init function 0 of the via southbridge. Called by the pnp-library */
+void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
+{
+    if (PCI_FUNC(dev) == 0)
+    {
+	/* FIXME: Try to generate a PCI reset */
+	/* unsigned char c; */
+	/* pci_read_config_byte(dev, 0x47, &c); */
+	/* pci_write_config_byte(dev, 0x47, c | 0x01); */
+
+	via_isa_init(dev, table);
+	via_fdc_init(dev);
+    }
+}
+
+__asm         ("    .globl via_calibrate_time_base \n"
+	       "via_calibrate_time_base: 	   \n"
+	       "   lis     9, 0xfe00		   \n"
+	       "   li      0, 0x00		   \n"
+	       "   mttbu   0			   \n"
+	       "   mttbl   0			   \n"
+	       "ctb_loop:			   \n"
+	       "   lbz     0, 0x61(9)		   \n"
+	       "   eieio			   \n"
+	       "   andi.   0, 0, 0x20		   \n"
+	       "   beq     ctb_loop		   \n"
+	       "ctb_done:			   \n"
+	       "   mftb    3			   \n"
+	       "   blr");
+
+extern unsigned long via_calibrate_time_base(void);
+
+void via_calibrate_bus_freq(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+    unsigned long tb;
+
+    /* This is 20 microseconds */
+    #define CALIBRATE_TIME 28636
+
+
+    /* Enable the timer (and disable speaker) */
+    unsigned char c;
+    c = in_byte(0x61);
+    out_byte(0x61, ((c & ~0x02) | 0x01));
+
+    /* Set timer 2 to low/high writing */
+    out_byte(0x43, 0xb0);
+    out_byte(0x42, CALIBRATE_TIME & 0xff);
+    out_byte(0x42, CALIBRATE_TIME >>8);
+
+    /* Read the time base */
+    tb = via_calibrate_time_base();
+
+    if (tb >= 700000)
+	gd->bus_clk = 133333333;
+    else
+	gd->bus_clk = 100000000;
+
+}
+
+
+void ide_led(uchar led, uchar status)
+{
+/*     unsigned char c = in_byte(0x92); */
+
+/*     if (!status) */
+/* 	out_byte(0x92, c | 0xC0); */
+/*     else */
+/* 	out_byte(0x92, c & ~0xC0); */
+}
+
+
+void via_init_afterscan(void)
+{
+    /* Modify IDE controller setup */
+    pci_write_cfg_byte(0, 7<<3|1, PCI_LATENCY_TIMER, 0x20);
+    pci_write_cfg_byte(0, 7<<3|1, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
+    pci_write_cfg_byte(0, 7<<3|1, PCI_INTERRUPT_LINE, 0xff);
+    pci_write_cfg_byte(0, 7<<3|1, 0x40, 0x0b);   /* FIXME: Might depend on drives connected */
+    pci_write_cfg_byte(0, 7<<3|1, 0x41, 0x42);   /* FIXME: Might depend on drives connected */
+    pci_write_cfg_byte(0, 7<<3|1, 0x43, 0x05);
+    pci_write_cfg_byte(0, 7<<3|1, 0x44, 0x18);
+    pci_write_cfg_byte(0, 7<<3|1, 0x45, 0x10);
+    pci_write_cfg_byte(0, 7<<3|1, 0x4e, 0x22);   /* FIXME: Not documented, but set in PC bios */
+    pci_write_cfg_byte(0, 7<<3|1, 0x4f, 0x20);   /* FIXME: Not documented */
+
+    /* Modify some values in the USB controller */
+    pci_write_cfg_byte(0, 7<<3|2, 0x05, 0x17);
+    pci_write_cfg_byte(0, 7<<3|2, 0x06, 0x01);
+    pci_write_cfg_byte(0, 7<<3|2, 0x41, 0x12);
+    pci_write_cfg_byte(0, 7<<3|2, 0x42, 0x03);
+    pci_write_cfg_byte(0, 7<<3|2, PCI_LATENCY_TIMER, 0x40);
+
+    pci_write_cfg_byte(0, 7<<3|3, 0x05, 0x17);
+    pci_write_cfg_byte(0, 7<<3|3, 0x06, 0x01);
+    pci_write_cfg_byte(0, 7<<3|3, 0x41, 0x12);
+    pci_write_cfg_byte(0, 7<<3|3, 0x42, 0x03);
+    pci_write_cfg_byte(0, 7<<3|3, PCI_LATENCY_TIMER, 0x40);
+
+
+}
diff --git a/board/MAI/AmigaOneG3SE/via686.h b/board/MAI/AmigaOneG3SE/via686.h
new file mode 100755
index 0000000..2a06a05
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/via686.h
@@ -0,0 +1,29 @@
+#ifndef VIA686_H_
+#define VIA686_H_
+
+
+#define CMOS_ADDR         0x70
+#define CMOS_DATA         0x71
+
+#define I8259_MASTER_CONTROL 0x20
+#define I8259_MASTER_MASK    0x21
+
+#define I8259_SLAVE_CONTROL  0xA0
+#define I8259_SLAVE_MASK     0xA1
+
+#define SIO_CONFIG_ADDR 0x3F0
+#define SIO_CONFIG_DATA 0x3F1
+
+#define SIO_WRITE_CONFIG(addr, byte) \
+   out_byte(SIO_CONFIG_ADDR, addr);  \
+   out_byte(SIO_CONFIG_DATA, byte);
+
+#define SIO_READ_CONFIG(addr, byte) \
+   out_byte(SIO_CONFIG_ADDR, addr); \
+   byte = in_byte(SIO_CONFIG_DATA);
+
+void via_init(void);
+
+void via_calibrate_bus_freq(void);
+
+#endif
diff --git a/board/MAI/AmigaOneG3SE/video.c b/board/MAI/AmigaOneG3SE/video.c
new file mode 100755
index 0000000..36e3c62
--- /dev/null
+++ b/board/MAI/AmigaOneG3SE/video.c
@@ -0,0 +1,539 @@
+/*
+ * (C) Copyright 2002
+ * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <devices.h>
+#include "memio.h"
+#include <part.h>
+
+unsigned char *cursor_position;
+unsigned int cursor_row;
+unsigned int cursor_col;
+
+unsigned char current_attr;
+
+unsigned int video_numrows = 25;
+unsigned int video_numcols = 80;
+unsigned int video_scrolls = 0;
+
+#define VIDEO_BASE (unsigned char *)0xFD0B8000
+#define VIDEO_ROWS video_numrows
+#define VIDEO_COLS video_numcols
+#define VIDEO_PITCH (2 * video_numcols)
+#define VIDEO_SIZE (video_numrows * video_numcols * 2)
+#define VIDEO_NAME "vga"
+
+void video_test(void);
+void video_putc(char ch);
+void video_puts(char *string);
+void video_scroll(int rows);
+void video_banner(void);
+int  video_init(void);
+int  video_start(void);
+int  video_rows(void);
+int  video_cols(void);
+
+char *prompt_string = "=>";
+
+void video_set_color(unsigned char attr)
+{
+    unsigned char *fb = (unsigned char *)VIDEO_BASE;
+    int i;
+
+    current_attr = video_get_attr();
+
+    for (i=0; i<VIDEO_SIZE; i+=2)
+    {
+	*(fb+i+1) = current_attr;
+    }
+}
+
+unsigned char video_get_attr(void)
+{
+    char *s;
+    unsigned char attr;
+
+    attr = 0x0f;
+
+    s = getenv("vga_fg_color");
+    if (s)
+    {
+	attr = atoi(s);
+    }
+
+    s = getenv("vga_bg_color");
+    if (s)
+    {
+	attr |= atoi(s)<<4;
+    }
+
+    return attr;
+}
+
+int video_inited = 0;
+
+int drv_video_init(void)
+{
+    int error, devices = 1 ;
+    device_t vgadev ;
+    if (video_inited) return 1;
+    video_inited = 1;
+    video_init();
+    memset (&vgadev, 0, sizeof(vgadev));
+
+    strcpy(vgadev.name, VIDEO_NAME);
+    vgadev.flags =  DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
+    vgadev.putc = video_putc;
+    vgadev.puts = video_puts;
+    vgadev.getc = NULL;
+    vgadev.tstc = NULL;
+    vgadev.start = video_start;
+
+    error = device_register (&vgadev);
+
+    if (error == 0)
+    {
+	char *s = getenv("stdout");
+	if (s && strcmp(s, VIDEO_NAME)==0)
+	{
+	    if (overwrite_console()) return 1;
+	    error = console_assign(stdout, VIDEO_NAME);
+	    if (error == 0) return 1;
+	    else return error;
+	}
+	return 1;
+    }
+
+    return error;
+}
+
+int video_init(void)
+{
+    cursor_position = VIDEO_BASE; /* Color text display base */
+    cursor_row = 0;
+    cursor_col = 0;
+    current_attr = video_get_attr(); /* Currently selected value for attribute. */
+/*    video_test(); */
+    video_set_color(current_attr);
+
+    return 0;
+}
+
+void video_set_cursor(int line, int column)
+{
+    unsigned short offset = line*video_numcols + column;
+    cursor_position = VIDEO_BASE +  line*VIDEO_PITCH + column*2;
+    out_byte(0x3D4, 0x0E);
+    out_byte(0x3D5, offset/256);
+    out_byte(0x3D4, 0x0F);
+    out_byte(0x3D5, offset%256);
+}
+
+void video_write_char(int character)
+{
+    *cursor_position = character;
+    *(cursor_position+1) = current_attr;
+}
+
+void video_test(void)
+{
+
+}
+
+void video_putc(char ch)
+{
+    switch(ch)
+    {
+    case '\n':
+	cursor_col = 0;
+	cursor_row += 1;
+	break;
+    case '\r':
+	cursor_col = 0;
+	break;
+    case '\b':
+	if (cursor_col) cursor_col--;
+	else return;
+	break;
+    case '\t':
+	cursor_col = (cursor_col/8+1)*8;
+	break;
+    default:
+	video_write_char(ch);
+	cursor_col++;
+	if (cursor_col > VIDEO_COLS-1)
+	{
+	    cursor_row++;
+	    cursor_col=0;
+	}
+    }
+
+    if (cursor_row > VIDEO_ROWS-1)
+	video_scroll(1);
+    video_set_cursor(cursor_row, cursor_col);
+}
+
+void video_scroll(int rows)
+{
+    unsigned short clear = ((unsigned short)current_attr) | (' '<<8);
+    unsigned short* addr16 = &((unsigned short *)VIDEO_BASE)[(VIDEO_ROWS-rows)*VIDEO_COLS];
+    int i;
+    char *s;
+
+    s = getenv("vga_askscroll");
+    video_scrolls += rows;
+
+    if (video_scrolls >= video_numrows)
+    {
+	if (s && strcmp(s, "yes"))
+	{
+	    while (-1 == tstc());
+	}
+
+	video_scrolls = 0;
+    }
+
+
+    memcpy(VIDEO_BASE, VIDEO_BASE+rows*(VIDEO_COLS*2), (VIDEO_ROWS-rows)*(VIDEO_COLS*2));
+    for (i = 0 ; i < rows * VIDEO_COLS ; i++)
+	addr16[i] = clear;
+    cursor_row-=rows;
+    cursor_col=0;
+}
+
+void video_puts(char *string)
+{
+    while (*string)
+    {
+	video_putc(*string);
+	string++;
+    }
+}
+
+int video_start(void)
+{
+    return 0;
+}
+
+unsigned char video_single_box[] =
+{
+    218, 196, 191,
+    179,      179,
+    192, 196, 217
+};
+
+unsigned char video_double_box[] =
+{
+    201, 205, 187,
+    186,      186,
+    200, 205, 188
+};
+
+unsigned char video_single_title[] =
+{
+    195, 196, 180, 180, 195
+};
+
+unsigned char video_double_title[] =
+{
+    204, 205, 185, 181, 198
+};
+
+#define SINGLE_BOX 0
+#define DOUBLE_BOX 1
+
+unsigned char *video_addr(int x, int y)
+{
+    return VIDEO_BASE + 2*(VIDEO_COLS*y) + 2*x;
+}
+
+void video_bios_print_string(char *s, int x, int y, int attr, int count)
+{
+    int cattr = current_attr;
+    if (attr != -1) current_attr = attr;
+    video_set_cursor(x,y);
+    while (count)
+    {
+	char c = *s++;
+	if (attr == -1) current_attr = *s++;
+	video_putc(c);
+	count--;
+    }
+}
+
+void video_draw_box(int style, int attr, char *title, int separate, int x, int y, int w, int h)
+{
+    unsigned char *fb, *fb2;
+    unsigned char *st = (style == SINGLE_BOX)?video_single_box : video_double_box;
+    unsigned char *ti = (style == SINGLE_BOX)?video_single_title : video_double_title;
+    int i;
+
+    fb = video_addr(x,y);
+    *(fb) = st[0];
+    *(fb+1) = attr;
+    fb += 2;
+
+    fb2 = video_addr(x,y+h-1);
+    *(fb2) = st[5];
+    *(fb2+1) = attr;
+    fb2 += 2;
+
+    for (i=0; i<w-2;i++)
+    {
+	*fb = st[1];
+	fb++;
+	*fb = attr;
+	fb++;
+
+	*fb2 = st[6];
+	fb2++;
+	*fb2 = attr;
+	fb2++;
+
+    }
+    *fb = st[2];
+    *(fb+1) = attr;
+
+    *fb2 = st[7];
+    *(fb2+1) = attr;
+
+    fb  = video_addr(x, y+1);
+    fb2 = video_addr(x+w-1, y+1);
+    for (i=0; i<h-2; i++)
+    {
+	*fb = st[3];
+	*(fb+1) = attr; fb += 2*VIDEO_COLS;
+
+	*fb2 = st[4];
+	*(fb2+1) = attr; fb2 += 2*VIDEO_COLS;
+    }
+
+    /* Draw title */
+    if (title)
+    {
+	if (separate == 0)
+	{
+	    fb = video_addr(x+1, y);
+	    *fb = ti[3];
+	    fb += 2;
+	    *fb = ' ';
+	    fb += 2;
+	    while (*title)
+	    {
+		*fb = *title;
+		fb ++;
+		*fb = attr;
+		fb++; title++;
+	    }
+	    *fb = ' ';
+	    fb += 2;
+	    *fb = ti[4];
+	}
+	else
+	{
+	    fb = video_addr(x, y+2);
+	    *fb = ti[0];
+	    fb += 2;
+	    for (i=0; i<w-2; i++)
+	    {
+		*fb = ti[1];
+		*(fb+1) = attr;
+		fb += 2;
+	    }
+	    *fb = ti[2];
+	    *(fb+1) = attr;
+	    fb = video_addr(x+1, y+1);
+	    for (i=0; i<w-2; i++)
+	    {
+		*fb = ' ';
+		*(fb+1) = attr;
+		fb += 2;
+	    }
+	    fb = video_addr(x+2, y+1);
+
+	    while (*title)
+	    {
+		*fb = *title;
+		*(fb+1) = attr;
+		fb += 2;
+		title++;
+	    }
+	}
+    }
+
+}
+
+void video_draw_text(int x, int y, int attr, char *text)
+{
+    unsigned char *fb = video_addr(x,y);
+    while (*text)
+    {
+	*fb++ = *text++;
+	*fb++ = attr;
+    }
+}
+
+void video_save_rect(int x, int y, int w, int h, void *save_area, int clearchar, int clearattr)
+{
+    unsigned char *save = (unsigned char *)save_area;
+    unsigned char *fb = video_addr(x,y);
+    int i,j;
+    for (i=0; i<h; i++)
+    {
+	unsigned char *fbb = fb;
+	for (j=0; j<w; j++)
+	{
+	    *save ++ = *fb;
+	    if (clearchar > 0) *fb = clearchar;
+	    fb ++;
+	    *save ++ = *fb;
+	    if (clearattr > 0) *fb = clearattr;
+	}
+	fb = fbb + 2*VIDEO_COLS;
+    }
+}
+
+void video_restore_rect(int x, int y, int w, int h, void *save_area)
+{
+    unsigned char *save = (unsigned char *)save_area;
+    unsigned char *fb = video_addr(x,y);
+    int i,j;
+    for (i=0; i<h; i++)
+    {
+	unsigned char *fbb = fb;
+	for (j=0; j<w; j++)
+	{
+	    *fb ++ = *save ++;
+	    *fb ++ = *save ++;
+	}
+	fb = fbb + 2*VIDEO_COLS;
+    }
+
+}
+
+int video_rows(void)
+{
+    return VIDEO_ROWS;
+}
+
+int video_cols(void)
+{
+    return VIDEO_COLS;
+}
+
+void video_size(int cols, int rows)
+{
+    video_numrows = rows;
+    video_numcols = cols;
+}
+
+void video_clear(void)
+{
+    unsigned short *fbb = (unsigned short *)0xFD0B8000;
+    int i,j;
+    unsigned short val = 0x2000 | current_attr;
+
+    for (i=0; i<video_rows(); i++)
+    {
+	for (j=0; j<video_cols(); j++)
+	{
+	    *fbb++ = val;
+	}
+    }
+    video_set_cursor(0,0);
+    cursor_row = 0;
+    cursor_col = 0;
+}
+
+#ifdef EASTEREGG
+int video_easteregg_active = 0;
+
+void video_easteregg(void)
+{
+    video_easteregg_active = 1;
+}
+#endif
+
+extern block_dev_desc_t * ide_get_dev(int dev);
+extern char version_string[];
+
+void video_banner(void)
+{
+    block_dev_desc_t *ide;
+    DECLARE_GLOBAL_DATA_PTR;
+    int i;
+    char *s;
+    int maxdev;
+
+
+    if (video_inited == 0) return;
+#ifdef EASTEREGG
+    if (video_easteregg_active)
+    {
+	prompt_string="";
+	video_clear();
+	printf("\n");
+	printf("    **** COMMODORE 64 BASIC X2 ****\n\n");
+	printf(" 64K RAM SYSTEM  38911 BASIC BYTES FREE\n\n");
+	printf("READY\n");
+    }
+    else
+    {
+#endif
+	s = getenv("ide_maxbus");
+	if (s)
+	    maxdev = atoi(s) * 2;
+	else
+	    maxdev = 4;
+
+	s = getenv("stdout");
+	if (s && strcmp(s, "serial") == 0)
+	    return;
+
+	video_clear();
+	printf("%s\n\nCPU: ", version_string);
+	checkcpu();
+	printf("DRAM: %ld MB\n", gd->bd->bi_memsize/(1024*1024));
+	printf("FSB: %ld MHz\n", gd->bd->bi_busfreq/1000000);
+
+	printf("\n---- Disk summary ----\n");
+	for (i = 0; i < maxdev; i++)
+	{
+	    ide = ide_get_dev(i);
+	    printf("Device %d: ", i);
+	    dev_print(ide);
+	}
+
+/*
+    video_draw_box(SINGLE_BOX, 0x0F, "Test 1", 0, 0,18, 72, 4);
+    video_draw_box(DOUBLE_BOX, 0x0F, "Test 2", 1, 4,10, 50, 6);
+    video_draw_box(DOUBLE_BOX, 0x0F, "Test 3", 0, 40, 3, 20, 5);
+
+    video_draw_text(1, 4, 0x2F, "Highlighted options");
+    video_draw_text(1, 5, 0x0F, "Non-selected option");
+    video_draw_text(1, 6, 0x07, "disabled option");
+*/
+#ifdef EASTEREGG
+    }
+#endif
+}
diff --git a/board/MAI/bios_emulator/bios.c b/board/MAI/bios_emulator/bios.c
new file mode 100755
index 0000000..d51eb64
--- /dev/null
+++ b/board/MAI/bios_emulator/bios.c
@@ -0,0 +1,335 @@
+/*
+ * Mostly done after the Scitech Bios emulation
+ * Written by Hans-Jörg Frieden
+ * Hyperion Entertainment
+ */
+#include "x86emu.h"
+#include "glue.h"
+
+#undef DEBUG
+#ifdef DEBUG
+#define PRINTF(fmt, args...) printf(fmt, ## args)
+#else
+#define PRINTF(fmt, args...)
+#endif
+
+#define BIOS_SEG 0xFFF0
+#define PCIBIOS_SUCCESSFUL 0
+#define PCIBIOS_DEVICE_NOT_FOUND 0x86
+
+typedef unsigned char UBYTE;
+typedef unsigned short UWORD;
+typedef unsigned long ULONG;
+
+typedef char BYTE;
+typedef short WORT;
+typedef long LONG;
+
+static inline UBYTE read_byte(volatile UBYTE* from)
+{
+    int x;
+    asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from));
+    return (UBYTE)x;
+}
+
+static inline void write_byte(volatile UBYTE *to, int x)
+{
+    asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x));
+}
+
+static inline UWORD read_word_little(volatile UWORD *from)
+{
+    int x;
+    asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from));
+    return (UWORD)x;
+}
+
+static inline UWORD read_word_big(volatile UWORD *from)
+{
+    int x;
+    asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from));
+    return (UWORD)x;
+}
+
+static inline void write_word_little(volatile UWORD *to, int x)
+{
+    asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to));
+}
+
+static inline void write_word_big(volatile UWORD *to, int x)
+{
+    asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x));
+}
+
+static inline ULONG read_long_little(volatile ULONG *from)
+{
+    unsigned long x;
+    asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from));
+    return (ULONG)x;
+}
+
+static inline ULONG read_long_big(volatile ULONG *from)
+{
+    unsigned long x;
+    asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from));
+    return (ULONG)x;
+}
+
+static inline void write_long_little(volatile ULONG *to, ULONG x)
+{
+    asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to));
+}
+
+static inline void write_long_big(volatile ULONG *to, ULONG x)
+{
+    asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x));
+}
+
+#define port_to_mem(from) (0xFE000000|(from))
+#define in_byte(from) read_byte( (UBYTE *)port_to_mem(from))
+#define in_word(from) read_word_little((UWORD *)port_to_mem(from))
+#define in_long(from) read_long_little((ULONG *)port_to_mem(from))
+#define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val)
+#define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val)
+#define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val)
+
+static void X86API undefined_intr(int intno)
+{
+    extern u16 A1_rdw(u32 addr);
+    if (A1_rdw(intno * 4 + 2) == BIOS_SEG)
+    {
+	PRINTF("Undefined interrupt %xh called AX = %xh, BX = %xh, CX = %xh, DX = %xh\n",
+	   intno, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+	X86EMU_halt_sys();
+    }
+    else
+    {
+	PRINTF("Calling interrupt %xh, AL=%xh, AH=%xh\n", intno, M.x86.R_AL, M.x86.R_AH);
+	X86EMU_prepareForInt(intno);
+    }
+}
+
+static void X86API int42(int intno);
+static void X86API int15(int intno);
+
+static void X86API int10(int intno)
+{
+    if (A1_rdw(intno*4+2) == BIOS_SEG)
+	int42(intno);
+    else
+    {
+	PRINTF("int10: branching to %04X:%04X, AL=%xh, AH=%xh\n", A1_rdw(intno*4+2), A1_rdw(intno*4),
+	       M.x86.R_AL, M.x86.R_AH);
+	X86EMU_prepareForInt(intno);
+    }
+}
+
+static void X86API int1A(int intno)
+{
+    int device;
+
+    switch(M.x86.R_AX)
+    {
+    case 0xB101: /* PCI Bios Present? */
+	M.x86.R_AL  = 0x00;
+	M.x86.R_EDX = 0x20494350;
+	M.x86.R_BX  = 0x0210;
+	M.x86.R_CL  = 3;
+	CLEAR_FLAG(F_CF);
+	break;
+    case 0xB102: /* Find device */
+	device = mypci_find_device(M.x86.R_DX, M.x86.R_CX, M.x86.R_SI);
+	if (device != -1)
+	{
+	    M.x86.R_AH = PCIBIOS_SUCCESSFUL;
+	    M.x86.R_BH = mypci_bus(device);
+	    M.x86.R_BL = mypci_devfn(device);
+	}
+	else
+	{
+	    M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND;
+	}
+	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
+	break;
+    case 0xB103: /* Find PCI class code */
+	M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND;
+	/*printf("Find by class not yet implmented"); */
+	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
+	break;
+    case 0xB108: /* read config byte */
+	M.x86.R_CL = mypci_read_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI);
+	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
+	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
+	/*printf("read_config_byte %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*	    M.x86.R_CL); */
+	break;
+    case 0xB109: /* read config word */
+	M.x86.R_CX = mypci_read_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI);
+	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
+	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
+	/*printf("read_config_word %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*	    M.x86.R_CX); */
+	break;
+    case 0xB10A: /* read config dword */
+	M.x86.R_ECX = mypci_read_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI);
+	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
+	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
+	/*printf("read_config_long %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*    M.x86.R_ECX); */
+	break;
+    case 0xB10B: /* write config byte */
+	mypci_write_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CL);
+	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
+	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
+	/*printf("write_config_byte %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*    M.x86.R_CL); */
+	break;
+    case 0xB10C: /* write config word */
+	mypci_write_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CX);
+	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
+	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
+	/*printf("write_config_word %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*	    M.x86.R_CX); */
+	break;
+    case 0xB10D: /* write config dword */
+	mypci_write_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_ECX);
+	M.x86.R_AH = PCIBIOS_SUCCESSFUL;
+	CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF);
+	/*printf("write_config_long %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */
+	/*	    M.x86.R_ECX); */
+	break;
+    default:
+	PRINTF("BIOS int %xh: Unknown function AX=%04xh\n", intno, M.x86.R_AX);
+
+    }
+}
+
+void bios_init(void)
+{
+    int i;
+    X86EMU_intrFuncs bios_intr_tab[256];
+
+    for (i=0; i<256; i++)
+    {
+	write_long_little(M.mem_base+i*4, BIOS_SEG<<16);
+	bios_intr_tab[i] = undefined_intr;
+    }
+
+    bios_intr_tab[0x10] = int10;
+    bios_intr_tab[0x1A] = int1A;
+    bios_intr_tab[0x42] = int42;
+    bios_intr_tab[0x15] = int15;
+
+    bios_intr_tab[0x6D] = int42;
+
+    X86EMU_setupIntrFuncs(bios_intr_tab);
+    video_init();
+}
+
+unsigned char setup_40x25[] =
+{
+    0x38, 0x28, 0x2d, 0x0a, 0x1f, 6, 0x19,
+    0x1c, 2, 7, 6, 7, 0, 0, 0, 0
+};
+
+unsigned char setup_80x25[] =
+{
+    0x71, 0x50, 0x5a, 0x0a, 0x1f, 6, 0x19,
+    0x1c, 2, 7, 6, 7, 0, 0, 0, 0
+};
+
+unsigned char setup_graphics[] =
+{
+    0x38, 0x28, 0x20, 0x0a, 0x7f, 6, 0x64,
+    0x70, 2, 1, 6, 7, 0, 0, 0, 0
+};
+
+unsigned char setup_bw[] =
+{
+    0x61, 0x50, 0x52, 0x0f, 0x19, 6, 0x19,
+    0x19, 2, 0x0d, 0x0b, 0x0c, 0, 0, 0, 0
+};
+
+unsigned char * setup_modes[] =
+{
+    setup_40x25,     /* mode 0: 40x25 bw text */
+    setup_40x25,     /* mode 1: 40x25 col text */
+    setup_80x25,     /* mode 2: 80x25 bw text */
+    setup_80x25,     /* mode 3: 80x25 col text */
+    setup_graphics,  /* mode 4: 320x200 col graphics */
+    setup_graphics,  /* mode 5: 320x200 bw graphics */
+    setup_graphics,  /* mode 6: 640x200 bw graphics */
+    setup_bw         /* mode 7: 80x25 mono text */
+};
+
+unsigned int setup_cols[] =
+{
+    40, 40, 80, 80, 40, 40, 80, 80
+};
+
+unsigned char setup_modesets[] =
+{
+     0x2C, 0x28, 0x2D, 0x29, 0x2A, 0x2E, 0x1E, 0x29
+};
+
+unsigned int setup_bufsize[] =
+{
+    2048, 2048, 4096, 2096, 16384, 16384, 16384, 4096
+};
+
+void bios_set_mode(int mode)
+{
+    int i;
+    unsigned char mode_set = setup_modesets[mode]; /* Control register value */
+    unsigned char *setup_regs = setup_modes[mode]; /* Register 3D4 Array */
+
+    /* Switch video off */
+    out_byte(0x3D8, mode_set & 0x37);
+
+    /* Set up parameters at 3D4h */
+    for (i=0; i<16; i++)
+    {
+	out_byte(0x3D4, (unsigned char)i);
+	out_byte(0x3D5, *setup_regs);
+	setup_regs++;
+    }
+
+    /* Enable video */
+    out_byte(0x3D8, mode_set);
+
+    /* Set overscan */
+    if (mode == 6) out_byte(0x3D9, 0x3F);
+    else           out_byte(0x3D9, 0x30);
+}
+
+static void bios_print_string(void)
+{
+    extern void video_bios_print_string(char *string, int x, int y, int attr, int count);
+    char *s = (char *)(M.x86.R_ES<<4) + M.x86.R_BP;
+    int attr;
+    if (M.x86.R_AL & 0x02) attr = - 1;
+    else                   attr = M.x86.R_BL;
+    video_bios_print_string(s, M.x86.R_DH, M.x86.R_DL, attr, M.x86.R_CX);
+}
+
+static void X86API int42(int intno)
+{
+    switch (M.x86.R_AH)
+    {
+    case 0x00:
+	bios_set_mode(M.x86.R_AL);
+	break;
+    case 0x13:
+	bios_print_string();
+	break;
+    default:
+	PRINTF("Warning: VIDEO BIOS interrupt %xh unimplemented function %xh, AL = %xh\n",
+	       intno, M.x86.R_AH, M.x86.R_AL);
+    }
+}
+
+static void X86API int15(int intno)
+{
+    PRINTF("Called interrupt 15h: AX = %xh, BX = %xh, CX = %xh, DX = %xh\n",
+	   M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+}
diff --git a/board/MAI/bios_emulator/glue.c b/board/MAI/bios_emulator/glue.c
new file mode 100755
index 0000000..b380f0d
--- /dev/null
+++ b/board/MAI/bios_emulator/glue.c
@@ -0,0 +1,515 @@
+#include <common.h>
+#include <pci.h>
+#include <74xx_7xx.h>
+
+
+#ifdef DEBUG
+#undef DEBUG
+#endif
+
+#ifdef DEBUG
+#define PRINTF(format, args...) _printf(format , ## args)
+#else
+#define PRINTF(format, argc...)
+#endif
+
+static pci_dev_t to_pci(int bus, int devfn)
+{
+    return PCI_BDF(bus, (devfn>>3), devfn&3);
+}
+
+int mypci_find_device(int vendor, int product, int index)
+{
+    return pci_find_device(vendor, product, index);
+}
+
+int mypci_bus(int device)
+{
+    return PCI_BUS(device);
+}
+
+int mypci_devfn(int device)
+{
+    return (PCI_DEV(device)<<3) | PCI_FUNC(device);
+}
+
+
+#define mypci_read_func(type, size)				\
+type mypci_read_cfg_##size##(int bus, int devfn, int offset)	\
+{								\
+    type c;							\
+    pci_read_config_##size##(to_pci(bus, devfn), offset, &c);	\
+    return c;							\
+}
+
+#define mypci_write_func(type, size)				\
+void mypci_write_cfg_##size##(int bus, int devfn, int offset, int value)	\
+{								\
+    pci_write_config_##size##(to_pci(bus, devfn), offset, value);	\
+}
+
+mypci_read_func(u8,byte);
+mypci_read_func(u16,word);
+
+mypci_write_func(u8,byte);
+mypci_write_func(u16,word);
+
+u32 mypci_read_cfg_long(int bus, int devfn, int offset)
+{
+    u32 c;
+    pci_read_config_dword(to_pci(bus, devfn), offset, &c);
+    return c;
+}
+
+void mypci_write_cfg_long(int bus, int devfn, int offset, int value)
+{
+    pci_write_config_dword(to_pci(bus, devfn), offset, value);
+}
+
+void _printf(const char *fmt, ...)
+{
+    va_list args;
+    char buf[CFG_PBSIZE];
+
+    va_start(args, fmt);
+    (void)vsprintf(buf, fmt, args);
+    va_end(args);
+
+    printf(buf);
+}
+
+char *_getenv(char *name)
+{
+    return getenv(name);
+}
+
+unsigned long get_bar_size(pci_dev_t dev, int offset)
+{
+    u32 bar_back, bar_value;
+
+    /*  Save old BAR value */
+    pci_read_config_dword(dev, offset, &bar_back);
+
+    /*  Write all 1's. */
+    pci_write_config_dword(dev, offset, ~0);
+
+    /*  Now read back the relevant bits */
+    pci_read_config_dword(dev, offset, &bar_value);
+
+    /*  Restore original value */
+    pci_write_config_dword(dev, offset, bar_back);
+
+    if (bar_value == 0) return 0xFFFFFFFF; /*  This BAR is disabled */
+
+    if ((bar_value & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY)
+    {
+	/*  This is a memory space BAR. Mask it out so we get the size of it */
+	return ~(bar_value & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+    }
+
+    /*  Not suitable */
+    return 0xFFFFFFFF;
+}
+
+void enable_compatibility_hole(void)
+{
+    u8 cfg;
+    pci_dev_t art = PCI_BDF(0,0,0);
+
+    pci_read_config_byte(art, 0x54, &cfg);
+    /* cfg |= 0x08; */
+    cfg |= 0x20;
+    pci_write_config_byte(art, 0x54, cfg);
+}
+
+void disable_compatibility_hole(void)
+{
+    u8 cfg;
+    pci_dev_t art = PCI_BDF(0,0,0);
+
+    pci_read_config_byte(art, 0x54, &cfg);
+    /* cfg &= ~0x08; */
+    cfg &= ~0x20;
+    pci_write_config_byte(art, 0x54, cfg);
+}
+
+void map_rom(pci_dev_t dev, u32 address)
+{
+    pci_write_config_dword(dev, PCI_ROM_ADDRESS, address|PCI_ROM_ADDRESS_ENABLE);
+}
+
+void unmap_rom(pci_dev_t dev)
+{
+    pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
+}
+
+void bat_map(u8 batnum, u32 address, u32 length)
+{
+    u32 temp = address;
+    address &= 0xFFFE0000;
+    temp    &= 0x0001FFFF;
+    length = (length - 1 ) >> 17;
+    length <<= 2;
+
+    switch (batnum)
+    {
+    case 0:
+	__asm volatile ("mtdbatu 0, %0" : : "r" (address | length | 3));
+	__asm volatile ("mtdbatl 0, %0" : : "r" (address | 0x22));
+	break;
+    case 1:
+	__asm volatile ("mtdbatu 1, %0" : : "r" (address | length | 3));
+	__asm volatile ("mtdbatl 1, %0" : : "r" (address | 0x22));
+	break;
+    case 2:
+	__asm volatile ("mtdbatu 2, %0" : : "r" (address | length | 3));
+	__asm volatile ("mtdbatl 2, %0" : : "r" (address | 0x22));
+	break;
+    case 3:
+	__asm volatile ("mtdbatu 3, %0" : : "r" (address | length | 3));
+	__asm volatile ("mtdbatl 3, %0" : : "r" (address | 0x22));
+	break;
+    }
+}
+
+int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size);
+
+int attempt_map_rom(pci_dev_t dev, void *copy_address)
+{
+    u32 rom_size      = 0;
+    u32 rom_address   = 0;
+    u32 bar_size      = 0;
+    u32 bar_backup    = 0;
+    int i,j;
+    void *image       = 0;
+    u32 image_size    = 0;
+    int did_correct   = 0;
+    u32 prefetch_addr = 0;
+    u32 prefetch_size = 0;
+    u32 prefetch_idx  = 0;
+
+    /*  Get the size of the expansion rom */
+    pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0xFFFFFFFF);
+    pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_size);
+    if ((rom_size & 0x01) == 0)
+    {
+	PRINTF("No ROM\n");
+	return 0;
+    }
+
+    rom_size &= 0xFFFFF800;
+    rom_size = (~rom_size)+1;
+
+    PRINTF("ROM Size is %dK\n", rom_size/1024);
+
+    /*
+     * Try to find a place for the ROM. We always attempt to use
+     * one of the card's bases for this, as this will be in any
+     * bridge's resource range as well as being free of conflicts
+     * with other cards. In a graphics card it is very unlikely
+     * that there won't be any base address that is large enough to
+     * hold the rom.
+     *
+     * FIXME: To work around this, theoretically the largest base
+     * could be used if none is found in the loop below.
+     */
+
+    for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4)
+    {
+	bar_size = get_bar_size(dev, i);
+	PRINTF("PCI_BASE_ADDRESS_%d is %dK large\n",
+	       (i - PCI_BASE_ADDRESS_0)/4,
+	       bar_size/1024);
+	if (bar_size != 0xFFFFFFFF && bar_size >= rom_size)
+	{
+	    PRINTF("Found a match for rom size\n");
+	    pci_read_config_dword(dev, i, &rom_address);
+	    rom_address &= 0xFFFFFFF0;
+	    if (rom_address != 0 && rom_address != 0xFFFFFFF0) break;
+	}
+    }
+
+    if (rom_address == 0 || rom_address == 0xFFFFFFF0)
+    {
+	PRINTF("No suitable rom address found\n");
+	return 0;
+    }
+
+    /*  Disable the BAR */
+    pci_read_config_dword(dev, i, &bar_backup);
+    pci_write_config_dword(dev, i, 0);
+
+    /*  Map ROM */
+    pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address | PCI_ROM_ADDRESS_ENABLE);
+
+    /*  Copy the rom to a place in the emulator space */
+    PRINTF("Claiming BAT 2\n");
+    bat_map(2, rom_address, rom_size);
+    /* show_bat_mapping(); */
+
+    if (0 == find_image(rom_address, rom_size, &image, &image_size))
+    {
+	PRINTF("No x86 BIOS image found\n");
+	return 0;
+    }
+
+    PRINTF("Copying %ld bytes from 0x%lx to 0x%lx\n", (long)image_size, (long)image, (long)copy_address);
+
+    /* memcpy(copy_address, rom_address, rom_size); */
+    {
+	unsigned char *from = (unsigned char *)image; /* rom_address; */
+	unsigned char *to = (unsigned char *)copy_address;
+	for (j=0; j<image_size /*rom_size*/; j++)
+	{
+	    *to++ = *from++;
+	}
+    }
+
+    PRINTF("Copy is done\n");
+
+    /*  Unmap the ROM and restore the BAR */
+    pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
+    pci_write_config_dword(dev, i, bar_backup);
+
+    /*  FIXME: Shouldn't be needed anymore*/
+    /* bat_map(2, 0x80000000, 256*1024*1024);
+       show_bat_mapping(); */
+
+    /*
+     * Since most cards can probably only do 16 bit IO addressing, we
+     * correct their IO base into an appropriate value.
+     * This should do for most.
+     */
+    for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4)
+    {
+	unsigned long value;
+	pci_read_config_dword(dev, i, &value);
+	if (value & 0x01) /*  IO */
+	{
+	    did_correct = 1;
+	    pci_write_config_dword(dev, i, 0x1001);
+	    break;
+	}
+
+	if (value & PCI_BASE_ADDRESS_MEM_PREFETCH)
+	{
+	    prefetch_idx = i;
+	    prefetch_addr = value & PCI_BASE_ADDRESS_MEM_MASK;
+	    prefetch_size = get_bar_size(dev, i);
+	}
+    }
+
+    if (1) /* did_correct) */
+    {
+	extern pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr);
+	int busnr = PCI_BUS(dev);
+	if (busnr)
+	{
+	    pci_dev_t bridge;
+	    PRINTF("Need to correct bridge device for IO range change\n");
+	    bridge = pci_find_bridge_for_bus(NULL, busnr);
+	    if (bridge == PCI_ANY_ID)
+	    {
+		PRINTF("Didn't find bridge. Hope that's OK\n");
+	    }
+	    else
+	    {
+		/*
+		 * Set upper I/O base/limit to 0
+		 */
+		pci_write_config_byte(bridge, 0x30, 0x00);
+		pci_write_config_byte(bridge, 0x31, 0x00);
+		pci_write_config_byte(bridge, 0x32, 0x00);
+		pci_write_config_byte(bridge, 0x33, 0x00);
+		if (did_correct)
+		{
+		    /*
+		     * set lower I/O base to 1000
+		     * That is, bits 0:3 are set to 0001 by default.
+		     * bits 7:4 contain I/O address bits 15:12
+		     * all others are assumed 0.
+		     */
+		    pci_write_config_byte(bridge, 0x1C, 0x11);
+		    /*
+		     * Set lower I/O limit to 1FFF
+		     * That is, bits 0:3 are reserved and always 0000
+		     * Bits 7:4 contain I/O address bits 15:12
+		     * All others are assumed F.
+		     */
+		    pci_write_config_byte(bridge, 0x1D, 0x10);
+		    pci_write_config_byte(bridge, 0x0D, 0x20);
+		    PRINTF("Corrected bridge resource range of bridge at %02x:%02x:%02x\n",
+			   PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
+
+		}
+		else
+		{
+		    /*
+		     * This card doesn't have I/O, we disable I/O forwarding
+		     */
+		    pci_write_config_byte(bridge, 0x1C, 0x11);
+		    pci_write_config_byte(bridge, 0x1D, 0x00);
+		    pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0);
+		    pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0);
+		    pci_write_config_dword(bridge, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+		    PRINTF("Disabled bridge resource range of bridge at %02x:%02x:%02x\n",
+			   PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
+
+		}
+	    }
+	    /*
+	     * Correct the prefetchable memory base, which is not set correctly by
+	     * the U-Boot autoconfig stuff
+	     */
+	    if (prefetch_idx)
+	    {
+/* 		PRINTF("Setting prefetchable range to %x, %x (%x and %x)\n", */
+/* 		       prefetch_addr, prefetch_addr+prefetch_size, */
+/* 		       prefetch_addr>>16, (prefetch_addr+prefetch_size)>>16); */
+/* 		pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, (prefetch_addr>>16)); */
+/* 		pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, (prefetch_addr+prefetch_size)>>16); */
+	    }
+
+	    pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, 0x1000);
+	    pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, 0x0000);
+
+	    pci_write_config_byte(bridge, 0xD0, 0x0A);
+	    pci_write_config_byte(bridge, 0xD3, 0x04);
+
+	    /*
+	     * Set the interrupt pin to 0
+	     */
+#if 0
+	    pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0);
+	    pci_write_config_byte(dev, PCI_INTERRUPT_PIN, 0);
+#endif
+	    pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0);
+	    pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0);
+
+	}
+    }
+
+    /* Finally, enable the card's IO and memory response */
+    pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+    pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0);
+    pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0);
+
+    return 1;
+}
+
+int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size)
+{
+    int i = 0;
+    unsigned char *rom = (unsigned char *)rom_address;
+    /* if (*rom != 0x55 || *(rom+1) != 0xAA) return 0; /* No bios rom this is, yes. */ */
+
+    for (;;)
+    {
+	unsigned short pci_data_offset = *(rom+0x18) + 256 * *(rom+0x19);
+	unsigned short pci_image_length = (*(rom+pci_data_offset+0x10) + 256 * *(rom+pci_data_offset+0x11)) * 512;
+	unsigned char pci_image_type = *(rom+pci_data_offset+0x14);
+	if (*rom != 0x55 || *(rom+1) != 0xAA)
+	{
+	    PRINTF("Invalid header this is\n");
+	    return 0;
+	}
+	PRINTF("Image %i: Type %d (%s)\n", i++, pci_image_type,
+	       pci_image_type==0 ? "x86" :
+	       pci_image_type==1 ? "OpenFirmware" :
+	       "Unknown");
+	if (pci_image_type == 0)
+	{
+	    *image = rom;
+	    *image_size = pci_image_length;
+	    return 1;
+	}
+
+	if (*(rom+pci_data_offset+0x15) & 0x80)
+	{
+	    PRINTF("LAST image encountered, no image found\n");
+	    return 0;
+	}
+
+	rom += pci_image_length;
+    }
+}
+
+void show_bat_mapping(void)
+{
+    u32 dbat0u, dbat0l, ibat0u, ibat0l;
+    u32 dbat1u, dbat1l, ibat1u, ibat1l;
+    u32 dbat2u, dbat2l, ibat2u, ibat2l;
+    u32 dbat3u, dbat3l, ibat3u, ibat3l;
+    u32 msr, hid0, l2cr_reg;
+
+    __asm volatile ("mfdbatu %0,0" : "=r" (dbat0u));
+    __asm volatile ("mfdbatl %0,0" : "=r" (dbat0l));
+    __asm volatile ("mfibatu %0,0" : "=r" (ibat0u));
+    __asm volatile ("mfibatl %0,0" : "=r" (ibat0l));
+
+    __asm volatile ("mfdbatu %0,1" : "=r" (dbat1u));
+    __asm volatile ("mfdbatl %0,1" : "=r" (dbat1l));
+    __asm volatile ("mfibatu %0,1" : "=r" (ibat1u));
+    __asm volatile ("mfibatl %0,1" : "=r" (ibat1l));
+
+    __asm volatile ("mfdbatu %0,2" : "=r" (dbat2u));
+    __asm volatile ("mfdbatl %0,2" : "=r" (dbat2l));
+    __asm volatile ("mfibatu %0,2" : "=r" (ibat2u));
+    __asm volatile ("mfibatl %0,2" : "=r" (ibat2l));
+
+    __asm volatile ("mfdbatu %0,3" : "=r" (dbat3u));
+    __asm volatile ("mfdbatl %0,3" : "=r" (dbat3l));
+    __asm volatile ("mfibatu %0,3" : "=r" (ibat3u));
+    __asm volatile ("mfibatl %0,3" : "=r" (ibat3l));
+
+    __asm volatile ("mfmsr %0"     : "=r" (msr));
+    __asm volatile ("mfspr %0,1008": "=r" (hid0));
+    __asm volatile ("mfspr %0,1017": "=r" (l2cr_reg));
+
+    printf("dbat0u: %08x dbat0l: %08x ibat0u: %08x ibat0l: %08x\n",
+	   dbat0u, dbat0l, ibat0u, ibat0l);
+    printf("dbat1u: %08x dbat1l: %08x ibat1u: %08x ibat1l: %08x\n",
+	   dbat1u, dbat1l, ibat1u, ibat1l);
+    printf("dbat2u: %08x dbat2l: %08x ibat2u: %08x ibat2l: %08x\n",
+	   dbat2u, dbat2l, ibat2u, ibat2l);
+    printf("dbat3u: %08x dbat3l: %08x ibat3u: %08x ibat3l: %08x\n",
+	   dbat3u, dbat3l, ibat3u, ibat3l);
+
+    printf("\nMSR: %08x   HID0: %08x   L2CR: %08x \n", msr,hid0, l2cr_reg);
+}
+
+
+void remove_init_data(void)
+{
+    char *s;
+
+    /*  Invalidate and disable data cache */
+    invalidate_l1_data_cache();
+    dcache_disable();
+
+    s = getenv("x86_cache");
+
+    if (!s)
+    {
+	icache_enable();
+	dcache_enable();
+    }
+    else if (s)
+    {
+	if (strcmp(s, "dcache")==0)
+	{
+	    dcache_enable();
+	}
+	else if (strcmp(s, "icache") == 0)
+	{
+	    icache_enable();
+	}
+	else if (strcmp(s, "on")== 0 || strcmp(s, "both") == 0)
+	{
+	    dcache_enable();
+	    icache_enable();
+	}
+    }
+
+    /*   show_bat_mapping();*/
+}
diff --git a/board/MAI/bios_emulator/glue.h b/board/MAI/bios_emulator/glue.h
new file mode 100755
index 0000000..585efe1
--- /dev/null
+++ b/board/MAI/bios_emulator/glue.h
@@ -0,0 +1,57 @@
+#ifndef GLUE_H
+#define GLUE_H
+
+typedef unsigned int pci_dev_t;
+
+int mypci_find_device(int vendor, int product, int index);
+int mypci_bus(int device);
+int mypci_devfn(int device);
+unsigned long get_bar_size(pci_dev_t dev, int offset);
+
+u8   mypci_read_cfg_byte(int bus, int devfn, int offset);
+u16  mypci_read_cfg_word(int bus, int devfn, int offset);
+u32  mypci_read_cfg_long(int bus, int devfn, int offset);
+
+void mypci_write_cfg_byte(int bus, int devfn, int offset, u8 value);
+void mypci_write_cfg_word(int bus, int devfn, int offset, u16 value);
+void mypci_write_cfg_long(int bus, int devfn, int offset, u32 value);
+
+void _printf(const char *fmt, ...);
+char *_getenv(char *name);
+
+void *malloc(size_t size);
+void memset(void *addr, int value, size_t size);
+void memcpy(void *to, void *from, size_t numbytes);
+int  strcmp(char *, char *);
+
+void enable_compatibility_hole(void);
+void disable_compatibility_hole(void);
+
+void map_rom(pci_dev_t dev, unsigned long address);
+void unmap_rom(pci_dev_t dev);
+int  attempt_map_rom(pci_dev_t dev, void *copy_address);
+
+#define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
+#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
+#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
+#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
+
+#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
+#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
+#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
+#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
+#define PCI_BUS(d)      (((d) >> 16) & 0xff)
+#define PCI_DEV(d)      (((d) >> 11) & 0x1f)
+#define PCI_FUNC(d)     (((d) >> 8) & 0x7)
+#define PCI_BDF(b,d,f)  ((b) << 16 | (d) << 11 | (f) << 8)
+
+#define PCI_ANY_ID (~0)
+#define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
+#define PCI_ROM_ADDRESS_ENABLE 0x01
+
+#define OFF(addr) ((addr) & 0xFFFF)
+#define SEG(addr) (((addr)>>4) &0xF000)
+
+#endif
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake
new file mode 100755
index 0000000..4d6ccb3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp
new file mode 100755
index 0000000..d372949
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo
new file mode 100755
index 0000000..6f65d41
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm
new file mode 100755
index 0000000..7de5030
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep b/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep
new file mode 100755
index 0000000..5451b22
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm
new file mode 100755
index 0000000..fbd3352
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm
new file mode 100755
index 0000000..dd14a7a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans b/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans
new file mode 100755
index 0000000..a1aea4f
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake
new file mode 100755
index 0000000..f198f29
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm
new file mode 100755
index 0000000..e312a0b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm
new file mode 100755
index 0000000..9fe81a3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/trans b/board/MAI/bios_emulator/scitech/bin-linux/libc/trans
new file mode 100755
index 0000000..e536c04
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin-linux/libc/trans
diff --git a/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat
new file mode 100755
index 0000000..776d138
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat
@@ -0,0 +1,28 @@
+@echo off
+REM Setup for compiling with Borland C++ 3.1.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC3;%BC3_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC3;%BC3_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC3_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC3.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_SNAP=
+PATH %SCITECH_BIN%;%BC3_PATH%\BIN;%DEFPATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC3_PATH%\BIN\turboc.cfg
+echo -L%LIB% >> %BC3_PATH%\BIN\turboc.cfg
+echo -L%LIB% > %BC3_PATH%\BIN\tlink.cfg
+
+echo Borland C++ 3.1 DOS compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat
new file mode 100755
index 0000000..d2939f4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat
@@ -0,0 +1,37 @@
+@echo off
+REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_VXD=
+SET USE_TNT=
+SET USE_BC5=
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC4
+PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto createfiles
+call win32sdk.bat borland
+
+:createfiles
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 4.5 32 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat
new file mode 100755
index 0000000..246517d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat
@@ -0,0 +1,32 @@
+@echo off
+REM Setup for compiling with Borland C++ 4.5 in 16 bit mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC4;%BC4_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC4;%BC4_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_BC5=
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC4
+PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg
+echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg
+echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg
+
+echo Borland C++ 4.5 16 bit DOS compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat
new file mode 100755
index 0000000..cbb2c79
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat
@@ -0,0 +1,33 @@
+@echo off
+REM Setup for compiling with Borland C++ 4.5 in 32 bit mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=
+SET USE_BC5=
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC4
+PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 4.5 32 bit DOS compilation configuration set up (DPMI32).
diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat
new file mode 100755
index 0000000..14d7c05
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat
@@ -0,0 +1,32 @@
+@echo off
+REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC4;%BC4_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC4;%BC4_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=
+SET USE_BC5=
+SET WIN32_GUI=
+SET USE_SNAP=1
+SET BC_LIBBASE=BC4
+PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 4.5 Snap compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat
new file mode 100755
index 0000000..50bd3cb
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat
@@ -0,0 +1,46 @@
+@echo off
+REM Setup for compiling with Borland C++ 4.5 in 32 bit mode with Phar Lap TNT
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=1
+SET USE_BC5=
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC4
+PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM If you set the following to a 1, a TNT DosStyle app will be created.
+REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
+REM run under real DOS when using our libraries, since we require access
+REM to functions that the Win32 API does not support (such as direct access
+REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
+REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
+REM work too well).
+REM
+REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
+REM and hence will never be able to run under Win95 or WinNT, only DOS.
+
+SET DOSSTYLE=
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 4.5 32 bit DOS compilation configuration set up (TNT).
diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat
new file mode 100755
index 0000000..4b59fa4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat
@@ -0,0 +1,32 @@
+@echo off
+REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows VxD mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC4;%BC4_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC4;%BC4_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=1
+SET USE_TNT=
+SET USE_BC5=
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC4
+PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 4.5 32-bit VxD compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat
new file mode 100755
index 0000000..4d799b4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat
@@ -0,0 +1,32 @@
+@echo off
+REM Setup for compiling with Borland C++ 4.5 in 16 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC4;%BC4_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC4;%BC4_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
+SET USE_DPMI16=
+SET USE_WIN16=1
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_BC5=
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC4
+PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg
+echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg
+echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg
+
+echo Borland C++ 4.5 16 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat
new file mode 100755
index 0000000..a6c199f
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat
@@ -0,0 +1,37 @@
+@echo off
+REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_VXD=
+SET USE_TNT=
+SET USE_BC5=
+SET WIN32_GUI=1
+SET USE_SNAP=
+SET BC_LIBBASE=BC4
+PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto createfiles
+call win32sdk.bat borland
+
+:createfiles
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 4.5 32 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat
new file mode 100755
index 0000000..6a0fde2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat
@@ -0,0 +1,40 @@
+@echo off
+REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET C_INCLUDE=%BC5_PATH%\INCLUDE
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto createfiles
+call win32sdk.bat borland
+
+:createfiles
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 5.0 32 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat
new file mode 100755
index 0000000..23b5038
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Borland C++ 5.0 in 16 bit mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC5;%BC5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC5;%BC5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg
+
+echo Borland C++ 5.0 16 bit DOS compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat
new file mode 100755
index 0000000..0521f93
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat
@@ -0,0 +1,35 @@
+@echo off
+REM Setup for compiling with Borland C++ 5.0 in 32 bit mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 5.0 32 bit DOS compilation configuration set up (DPMI32).
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat b/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat
new file mode 100755
index 0000000..e3241ff
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat
@@ -0,0 +1,35 @@
+@echo off
+REM Setup for compiling with Borland C++ 5.0 in 32 bit mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\SMX32\BC5;%BC5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\SMX32\BC5;%BC5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=1
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 5.0 32 bit SMX compilation configuration set up (SMX32).
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat
new file mode 100755
index 0000000..ab3acd2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC5;%BC5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC5;%BC5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=1
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 5.0 Snap compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat
new file mode 100755
index 0000000..4dcc372
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat
@@ -0,0 +1,48 @@
+@echo off
+REM Setup for compiling with Borland C++ 5.0 in 32 bit mode with Phar Lap TNT
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;%TNT_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=1
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM If you set the following to a 1, a TNT DosStyle app will be created.
+REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
+REM run under real DOS when using our libraries, since we require access
+REM to functions that the Win32 API does not support (such as direct access
+REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
+REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
+REM work too well).
+REM
+REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
+REM and hence will never be able to run under Win95 or WinNT, only DOS.
+
+SET DOSSTYLE=
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 5.0 32 bit DOS compilation configuration set up (TNT).
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat
new file mode 100755
index 0000000..2356911
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC5;%BC5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC5;%BC5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=1
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 5.0 32 bit Windows (VxD) compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat
new file mode 100755
index 0000000..cd79d86
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat
@@ -0,0 +1,34 @@
+ @echo off
+REM Setup for compiling with Borland C++ 5.0 in 16 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC5;%BC5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC5;%BC5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
+SET USE_DPMI16=
+SET USE_WIN16=1
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_BC5=1
+SET USE_SMX32=
+SET USE_SMX16=
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg
+
+echo Borland C++ 5.0 16 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat
new file mode 100755
index 0000000..8b8cec9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat
@@ -0,0 +1,40 @@
+@echo off
+REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET C_INCLUDE=%BC5_PATH%\INCLUDE
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=1
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto createfiles
+call win32sdk.bat borland
+
+:createfiles
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 5.0 32 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat
new file mode 100755
index 0000000..ebfeb2e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=1
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ 5.0 32 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat
new file mode 100755
index 0000000..6e09428
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat
@@ -0,0 +1,40 @@
+@echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET C_INCLUDE=%BCB5_PATH%\INCLUDE
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto createfiles
+call win32sdk.bat borland
+
+:createfiles
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat
new file mode 100755
index 0000000..aa13e7d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 16 bit mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BCB5;%BCB5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BCB5;%BCB5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\turboc.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\turboc.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink.cfg
+
+echo Borland C++ Builder 5.0 16 bit DOS compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat
new file mode 100755
index 0000000..d0017d4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat
@@ -0,0 +1,35 @@
+@echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BCB5;%BCB5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BCB5;%BCB5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ Builder 5.0 32 bit DOS compilation configuration set up (DPMI32).
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat
new file mode 100755
index 0000000..2b969a9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat
@@ -0,0 +1,35 @@
+@echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\SMX32\BCB5;%BCB5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\SMX32\BCB5;%BCB5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=1
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ Builder 5.0 32 bit SMX compilation configuration set up (SMX32).
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat
new file mode 100755
index 0000000..d7b8ff2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BCB5;%BCB5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BCB5;%BCB5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=1
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ Builder 5.0 Snap compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat
new file mode 100755
index 0000000..1de3601
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat
@@ -0,0 +1,48 @@
+@echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode with Phar Lap TNT
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BCB5;%BCB5_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BCB5;%BCB5_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;%TNT_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_DPMI16=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_TNT=1
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH%
+
+REM If you set the following to a 1, a TNT DosStyle app will be created.
+REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
+REM run under real DOS when using our libraries, since we require access
+REM to functions that the Win32 API does not support (such as direct access
+REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
+REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
+REM work too well).
+REM
+REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
+REM and hence will never be able to run under Win95 or WinNT, only DOS.
+
+SET DOSSTYLE=
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ Builder 5.0 32 bit DOS compilation configuration set up (TNT).
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat
new file mode 100755
index 0000000..28de58c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BCB5;%BCB5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BCB5;%BCB5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_VXD=1
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ Builder 5.0 32 bit Windows (VxD) compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat
new file mode 100755
index 0000000..c30d004
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat
@@ -0,0 +1,34 @@
+ @echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 16 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BCB5;%BCB5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BCB5;%BCB5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK
+SET USE_DPMI16=
+SET USE_WIN16=1
+SET USE_WIN32=
+SET USE_VXD=
+SET USE_BC5=1
+SET USE_SMX32=
+SET USE_SMX16=
+SET WIN32_GUI=
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\turboc.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\turboc.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink.cfg
+
+echo Borland C++ Builder 5.0 16 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat
new file mode 100755
index 0000000..18760e1
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat
@@ -0,0 +1,40 @@
+@echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET C_INCLUDE=%BCB5_PATH%\INCLUDE
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=1
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto createfiles
+call win32sdk.bat borland
+
+:createfiles
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat
new file mode 100755
index 0000000..198c1a2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode.
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_VXD=
+SET USE_TNT=
+SET USE_SMX32=
+SET USE_SMX16=
+SET USE_BC5=1
+SET WIN32_GUI=1
+SET USE_SNAP=
+SET BC_LIBBASE=BC5
+PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH%
+
+REM: Create Borland compile/link configuration scripts
+echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg
+echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg
+
+echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/build b/board/MAI/bios_emulator/scitech/bin/build
new file mode 100755
index 0000000..ff1973d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/build
@@ -0,0 +1,22 @@
+#! /bin/sh
+
+if [ $# -lt 1 ] || ( [ "$1" != gcc-linux ] && [ "$1" != qnx4 ] ) ; then
+	echo Usage: $0 compiler_name [DMAKE commands]
+	echo
+	echo Current compilers:
+	echo "  gcc-linux  - GNU C/C++ 2.7 or higher, 32 bit"
+	echo "  qnx4  - Watcom C/C++ 10.6 or higher, 32 bit"
+	exit 1
+fi
+
+unset DBG OPT OPT_SIZE BUILD_DLL IMPORT_DLL FPU CHECKS BETA
+. ${1}.sh
+
+shift
+dmake $* && exit 0
+
+echo *************************************************
+echo * An error occurred while building the library. *
+echo *************************************************
+exit 1
+
diff --git a/board/MAI/bios_emulator/scitech/bin/build.bat b/board/MAI/bios_emulator/scitech/bin/build.bat
new file mode 100755
index 0000000..ee29093
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/build.bat
@@ -0,0 +1,4 @@
+@echo off
+rem Disable checked build and build release code
+set CHECKED=
+call build_it.bat %1 %2 %3 %4 %5 %6 %7 %8 %9
diff --git a/board/MAI/bios_emulator/scitech/bin/build_db.bat b/board/MAI/bios_emulator/scitech/bin/build_db.bat
new file mode 100755
index 0000000..2b32529
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/build_db.bat
@@ -0,0 +1,4 @@
+@echo off
+rem Enable checked build and build debug code
+set CHECKED=1
+call build_it.bat %1 %2 %3 %4 %5 %6 %7 %8 %9
diff --git a/board/MAI/bios_emulator/scitech/bin/build_it.bat b/board/MAI/bios_emulator/scitech/bin/build_it.bat
new file mode 100755
index 0000000..5a619b4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/build_it.bat
@@ -0,0 +1,432 @@
+@echo off
+rem Generic batch file to build a version of the library. This batch file
+rem assumes that the correct batch files exist to setup the appropriate
+rem compilation environments, and that the DMAKE.EXE program is available
+rem somewhere on the path.
+rem
+rem Builds as release or debug depending on the value of the CHECKED
+rem environment variable.
+
+rem Unset all environment variables that change the compile process
+set DBG=
+set OPT=
+set OPT_SIZE=
+set BUILD_DLL=
+set IMPORT_DLL=
+set FPU=
+set CHECKS=
+set BETA=
+
+if %1==bc31-d16 goto bc31-d16
+if %1==bc45-d16 goto bc45-d16
+if %1==bc45-d32 goto bc45-d32
+if %1==bc45-tnt goto bc45-tnt
+if %1==bc45-w16 goto bc45-w16
+if %1==bc45-w32 goto bc45-w32
+if %1==bc45-c32 goto bc45-c32
+if %1==bc45-vxd goto bc45-vxd
+if %1==bc45-snp goto bc45-snp
+if %1==bc50-d16 goto bc50-d16
+if %1==bc50-d32 goto bc50-d32
+if %1==bc50-tnt goto bc50-tnt
+if %1==bc50-w16 goto bc50-w16
+if %1==bc50-w32 goto bc50-w32
+if %1==bc50-c32 goto bc50-c32
+if %1==bc50-vxd goto bc50-vxd
+if %1==bc50-snp goto bc50-snp
+if %1==gcc2-d32 goto gcc2-d32
+if %1==gcc2-w32 goto gcc2-w32
+if %1==gcc2-c32 goto gcc2-c32
+if %1==gcc2-linux goto gcc2-linux
+if %1==vc40-d16 goto vc40-d16
+if %1==vc40-tnt goto vc40-tnt
+if %1==vc40-w16 goto vc40-w16
+if %1==vc40-w32 goto vc40-w32
+if %1==vc40-c32 goto vc40-c32
+if %1==vc40-drv9x goto vc40-drv9x
+if %1==vc40-drvnt goto vc40-drvnt
+if %1==vc40-rtt goto vc40-rtt
+if %1==vc40-snp goto vc40-snp
+if %1==vc50-d16 goto vc50-d16
+if %1==vc50-tnt goto vc50-tnt
+if %1==vc50-w16 goto vc50-w16
+if %1==vc50-w32 goto vc50-w32
+if %1==vc50-c32 goto vc50-c32
+if %1==vc50-drv9x goto vc50-drv9x
+if %1==vc50-drvnt goto vc50-drvnt
+if %1==vc50-rtt goto vc50-rtt
+if %1==vc50-snp goto vc50-snp
+if %1==vc60-d16 goto vc60-d16
+if %1==vc60-tnt goto vc60-tnt
+if %1==vc60-w16 goto vc60-w16
+if %1==vc60-w32 goto vc60-w32
+if %1==vc60-c32 goto vc60-c32
+if %1==vc60-drv9x goto vc60-drv9x
+if %1==vc60-drvnt goto vc60-drvnt
+if %1==vc60-drvw2k goto vc60-drvw2k
+if %1==vc60-rtt goto vc60-rtt
+if %1==vc60-snp goto vc60-snp
+if %1==wc10ad16 goto wc10ad16
+if %1==wc10ad32 goto wc10ad32
+if %1==wc10atnt goto wc10atnt
+if %1==wc10aw16 goto wc10aw16
+if %1==wc10aw32 goto wc10aw32
+if %1==wc10ac32 goto wc10ac32
+if %1==wc10ao32 goto wc10ao32
+if %1==wc10ap32 goto wc10ap32
+if %1==wc10asnp goto wc10asnp
+if %1==wc10-d16 goto wc10-d16
+if %1==wc10-d32 goto wc10-d32
+if %1==wc10-tnt goto wc10-tnt
+if %1==wc10-w16 goto wc10-w16
+if %1==wc10-w32 goto wc10-w32
+if %1==wc10-c32 goto wc10-c32
+if %1==wc10-o32 goto wc10-o32
+if %1==wc10-p32 goto wc10-p32
+if %1==wc10-snp goto wc10-snp
+if %1==wc11-d16 goto wc11-d16
+if %1==wc11-d32 goto wc11-d32
+if %1==wc11-tnt goto wc11-tnt
+if %1==wc11-w16 goto wc11-w16
+if %1==wc11-w32 goto wc11-w32
+if %1==wc11-c32 goto wc11-c32
+if %1==wc11-o32 goto wc11-o32
+if %1==wc11-p32 goto wc11-p32
+if %1==wc11-snp goto wc11-snp
+
+echo Usage: BUILD 'compiler_name' [DMAKE commands]
+echo.
+echo Where 'compiler_name' is of the form comp-os, where
+echo 'comp' defines the compiler and 'os' defines the OS environment.
+echo For instance 'bc50-w32' is for Borland C++ 5.0 for Win32.
+echo The value of 'comp' can be any of the following:
+echo.
+echo    bc45 - Borland C++ 4.5x
+echo    bc50 - Borland C++ 5.x
+echo    vc40 - Visual C++ 4.x
+echo    vc50 - Visual C++ 5.x
+echo    vc60 - Visual C++ 6.x
+echo    wc10 - Watcom C++ 10.6
+echo    wc11 - Watcom C++ 11.0
+echo    gcc2 - GNU C/C++ 2.9x
+echo.
+echo The value of 'os' can be one of the following:
+echo.
+echo    d16   - 16-bit DOS
+echo    d32   - 32-bit DOS
+echo    w16   - 16-bit Windows GUI mode
+echo    c32   - 32-bit Windows console mode
+echo    w32   - 32-bit Windows GUI mode
+echo    o16   - 16-bit OS/2 console mode
+echo    o32   - 32-bit OS/2 console mode
+echo    p32   - 32-bit OS/2 Presentation Manager
+echo    snp   - 32-bit SciTech Snap application
+echo    linux - 32-bit Linux application
+goto end
+
+rem -------------------------------------------------------------------------
+rem Setup for the specified compiler
+
+:bc31-d16
+call bc31-d16.bat
+goto compileit
+
+:bc45-d16
+call bc45-d16.bat
+goto compileit
+
+:bc45-d32
+call bc45-d32.bat
+goto compileit
+
+:bc45-tnt
+call bc45-tnt.bat
+goto compileit
+
+:bc45-w16
+call bc45-w16.bat
+goto compileit
+
+:bc45-w32
+call bc45-w32.bat
+goto compileit
+
+:bc45-c32
+call bc45-c32.bat
+goto compileit
+
+:bc45-vxd
+call bc45-vxd.bat
+goto compileit
+
+:bc50-d16
+call bc50-d16.bat
+goto compileit
+
+:bc50-d32
+call bc50-d32.bat
+goto compileit
+
+:bc50-tnt
+call bc50-tnt.bat
+goto compileit
+
+:bc50-w16
+call bc50-w16.bat
+goto compileit
+
+:bc50-w32
+call bc50-w32.bat
+goto compileit
+
+:bc50-c32
+call bc50-c32.bat
+goto compileit
+
+:bc50-vxd
+call bc50-vxd.bat
+goto compileit
+
+:gcc2-d32
+call gcc2-d32.bat
+goto compileit
+
+:gcc2-w32
+call gcc2-w32.bat
+goto compileit
+
+:gcc2-c32
+call gcc2-c32.bat
+goto compileit
+
+:gcc2-linux
+call gcc2-linux.bat
+goto compileit
+
+:sc70-d16
+call sc70-d16.bat
+goto compileit
+
+:sc70-w16
+call sc70-w16.bat
+goto compileit
+
+:sc70-tnt
+call sc70-tnt.bat
+goto compileit
+
+:sc70-w32
+call sc70-w32.bat
+goto compileit
+
+:sc70-c32
+call sc70-c32.bat
+goto compileit
+
+:vc40-d16
+call vc40-d16.bat
+goto compileit
+
+:vc40-tnt
+call vc40-tnt.bat
+goto compileit
+
+:vc40-w16
+call vc40-w16.bat
+goto compileit
+
+:vc40-w32
+call vc40-w32.bat
+goto compileit
+
+:vc40-c32
+call vc40-c32.bat
+goto compileit
+
+:vc40-drv9x
+call vc40-drv9x.bat
+goto compileit
+
+:vc40-drvnt
+call vc40-drvnt.bat
+goto compileit
+
+:vc40-rtt
+call vc40-rtt.bat
+goto compileit
+
+:vc50-d16
+call vc50-d16.bat
+goto compileit
+
+:vc50-tnt
+call vc50-tnt.bat
+goto compileit
+
+:vc50-w16
+call vc50-w16.bat
+goto compileit
+
+:vc50-w32
+call vc50-w32.bat
+goto compileit
+
+:vc50-c32
+call vc50-c32.bat
+goto compileit
+
+:vc50-drv9x
+call vc50-drv9x.bat
+goto compileit
+
+:vc50-drvnt
+call vc50-drvnt.bat
+goto compileit
+
+:vc50-rtt
+call vc50-rtt.bat
+goto compileit
+
+:vc60-d16
+call vc60-d16.bat
+goto compileit
+
+:vc60-tnt
+call vc60-tnt.bat
+goto compileit
+
+:vc60-w16
+call vc60-w16.bat
+goto compileit
+
+:vc60-w32
+call vc60-w32.bat
+goto compileit
+
+:vc60-c32
+call vc60-c32.bat
+goto compileit
+
+:vc60-drv9x
+call vc60-drv9x.bat
+goto compileit
+
+:vc60-drvnt
+call vc60-drvnt.bat
+goto compileit
+
+:vc60-drvw2k
+call vc60-drvw2k.bat
+goto compileit
+
+:vc60-rtt
+call vc60-rtt.bat
+goto compileit
+
+:wc10ad16
+call wc10ad16.bat
+goto compileit
+
+:wc10ad32
+call wc10ad32.bat
+goto compileit
+
+:wc10atnt
+call wc10atnt.bat
+goto compileit
+
+:wc10aw16
+call wc10aw16.bat
+goto compileit
+
+:wc10aw32
+call wc10aw32.bat
+goto compileit
+
+:wc10ac32
+call wc10ac32.bat
+goto compileit
+
+:wc10ao32
+call wc10ao32.bat
+goto compileit
+
+:wc10ap32
+call wc10ap32.bat
+goto compileit
+
+:wc10-d16
+call wc10-d16.bat
+goto compileit
+
+:wc10-d32
+call wc10-d32.bat
+goto compileit
+
+:wc10-tnt
+call wc10-tnt.bat
+goto compileit
+
+:wc10-w16
+call wc10-w16.bat
+goto compileit
+
+:wc10-w32
+call wc10-w32.bat
+goto compileit
+
+:wc10-c32
+call wc10-c32.bat
+goto compileit
+
+:wc10-o32
+call wc10-o32.bat
+goto compileit
+
+:wc10-p32
+call wc10-p32.bat
+goto compileit
+
+:wc11-d16
+call wc11-d16.bat
+goto compileit
+
+:wc11-d32
+call wc11-d32.bat
+goto compileit
+
+:wc11-tnt
+call wc11-tnt.bat
+goto compileit
+
+:wc11-w16
+call wc11-w16.bat
+goto compileit
+
+:wc11-w32
+call wc11-w32.bat
+goto compileit
+
+:wc11-c32
+call wc11-c32.bat
+goto compileit
+
+:wc11-o32
+call wc11-o32.bat
+goto compileit
+
+:wc11-p32
+call wc11-p32.bat
+goto compileit
+
+:compileit
+k_rm -f *.lib *.a
+dmake %2 %3 %4 %5 %6 %7 %8 %9
+if errorlevel 1 goto errorend
+goto end
+
+:errorend
+echo *************************************************
+echo * An error occurred while building the library. *
+echo *************************************************
+:end
diff --git a/board/MAI/bios_emulator/scitech/bin/cddrv.bat b/board/MAI/bios_emulator/scitech/bin/cddrv.bat
new file mode 100755
index 0000000..b64f4d7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/cddrv.bat
@@ -0,0 +1,6 @@
+@echo off
+%1
+cd %3
+%4 %5 %6 %7 %8 %9
+%2
+
diff --git a/board/MAI/bios_emulator/scitech/bin/cdit b/board/MAI/bios_emulator/scitech/bin/cdit
new file mode 100755
index 0000000..b22023d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/cdit
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+cd $1
+PROG=$2
+shift 2
+rm -f *.lib *.a
+$PROG $*
+RET=$?
+cd ..
+exit $RET
diff --git a/board/MAI/bios_emulator/scitech/bin/cdit.bat b/board/MAI/bios_emulator/scitech/bin/cdit.bat
new file mode 100755
index 0000000..950b648
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/cdit.bat
@@ -0,0 +1,5 @@
+@echo off
+cd %1
+k_rm -f *.lib *.a
+shift 1
+%1 %2 %3 %4 %5 %6 %7 %8 %9
diff --git a/board/MAI/bios_emulator/scitech/bin/djgpp.env b/board/MAI/bios_emulator/scitech/bin/djgpp.env
new file mode 100755
index 0000000..5a2c3d8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/djgpp.env
@@ -0,0 +1,46 @@
+#= Don't edit this line unless you move djgpp.env outside
+#= of the djgpp installation directory.  If you do move
+#= it, set DJDIR to the directory you installed DJGPP in.
+#=
+DJDIR=%:/>DJGPP%
+
++USER=dosuser
++TMPDIR=%DJDIR%/tmp
++EMU387=%DJDIR%/bin/emu387.dxe
++LFN=y
+
+[bison]
+BISON_HAIRY=%DJDIR%/lib/bison.hai
+BISON_SIMPLE=%DJDIR%/lib/bison.sim
+
+[cpp]
+CPLUS_INCLUDE_PATH=%/>;CPLUS_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/lang/cxx;%DJDIR%/include;%DJDIR%/contrib/grx20/include
+C_INCLUDE_PATH=%/>;C_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/include;%DJDIR%/contrib/grx20/include
+OBJCPLUS_INCLUDE_PATH=%/>;OBJCPLUS_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc
+OBJC_INCLUDE_PATH=%/>;OBJC_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc
+
+[gcc]
+COMPILER_PATH=%/>;COMPILER_PATH%%DJDIR%/bin
+LIBRARY_PATH=%/>;LIBRARY_PATH%%DJDIR%/lib;%DJDIR%/contrib/grx20/lib;%SCITECH%/lib/release/dos32/dj2
+
+[info]
+INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info
+INFO_COLORS=0x1f.0x31
+
+[emacs]
+INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info
+
+[less]
+LESSBINFMT=*k<%X>
+LESSCHARDEF=8bcccbcc12bc5b95.b127.b
+LESS=%LESS% -h5$y5$Dd2.0$Du14.0$Ds4.7$Dk9.0$
+
+[locate]
++LOCATE_PATH=%DJDIR%/lib/locatedb.dat
+
+[ls]
++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08:
+[dir]
++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08:
+[vdir]
++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08:
diff --git a/board/MAI/bios_emulator/scitech/bin/djgpp_db.env b/board/MAI/bios_emulator/scitech/bin/djgpp_db.env
new file mode 100755
index 0000000..9b792c9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/djgpp_db.env
@@ -0,0 +1,46 @@
+#= Don't edit this line unless you move djgpp.env outside
+#= of the djgpp installation directory.  If you do move
+#= it, set DJDIR to the directory you installed DJGPP in.
+#=
+DJDIR=%:/>DJGPP%
+
++USER=dosuser
++TMPDIR=%DJDIR%/tmp
++EMU387=%DJDIR%/bin/emu387.dxe
++LFN=y
+
+[bison]
+BISON_HAIRY=%DJDIR%/lib/bison.hai
+BISON_SIMPLE=%DJDIR%/lib/bison.sim
+
+[cpp]
+CPLUS_INCLUDE_PATH=%/>;CPLUS_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/lang/cxx;%DJDIR%/include;%DJDIR%/contrib/grx20/include
+C_INCLUDE_PATH=%/>;C_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/include;%DJDIR%/contrib/grx20/include
+OBJCPLUS_INCLUDE_PATH=%/>;OBJCPLUS_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc
+OBJC_INCLUDE_PATH=%/>;OBJC_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc
+
+[gcc]
+COMPILER_PATH=%/>;COMPILER_PATH%%DJDIR%/bin
+LIBRARY_PATH=%/>;LIBRARY_PATH%%DJDIR%/lib;%DJDIR%/contrib/grx20/lib;%SCITECH%/lib/debug/dos32/dj2
+
+[info]
+INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info
+INFO_COLORS=0x1f.0x31
+
+[emacs]
+INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info
+
+[less]
+LESSBINFMT=*k<%X>
+LESSCHARDEF=8bcccbcc12bc5b95.b127.b
+LESS=%LESS% -h5$y5$Dd2.0$Du14.0$Ds4.7$Dk9.0$
+
+[locate]
++LOCATE_PATH=%DJDIR%/lib/locatedb.dat
+
+[ls]
++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08:
+[dir]
++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08:
+[vdir]
++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08:
diff --git a/board/MAI/bios_emulator/scitech/bin/findint3.bat b/board/MAI/bios_emulator/scitech/bin/findint3.bat
new file mode 100755
index 0000000..2e1506c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/findint3.bat
@@ -0,0 +1 @@
+perl c:\scitech\src\perl\findint3.per
diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh b/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh
new file mode 100755
index 0000000..61ffd93
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+# Setup for compiling with GCC/G++ for BeOS
+
+if [ "$CHECKED" = "1" ]; then
+    echo Checked debug build enabled.
+else
+    echo Release build enabled.
+fi
+
+export MAKESTARTUP=$SCITECH/makedefs/gcc_beos.mk
+export INCLUDE="-Iinclude -I$SCITECH/include -I$PRIVATE/include"
+export USE_X11=0
+export USE_BEOS=1
+
+echo GCC BeOS console compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh
new file mode 100755
index 0000000..3816a5d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+# Setup for compiling with GCC/G++ for FreeBSD
+
+if [ "$CHECKED" = "1" ]; then
+    echo Checked debug build enabled.
+else
+    echo Release build enabled.
+fi
+
+export MAKESTARTUP=$SCITECH/makedefs/gcc_freebsd.mk
+export INCLUDE="-Iinclude -I$SCITECH/include -I$PRIVATE/include"
+export USE_X11=1
+export USE_FREEBSD=1
+
+echo GCC FreeBSD console compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh b/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh
new file mode 100755
index 0000000..27a4c49
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh
@@ -0,0 +1,19 @@
+#! /bin/sh
+
+# Setup for compiling with GCC/G++ for Linux
+
+if [ "$CHECKED" = "1" ]; then
+    echo Checked debug build enabled.
+else
+    echo Release build enabled.
+fi
+
+export MAKESTARTUP=$SCITECH/makedefs/gcc_linux.mk
+export INCLUDE="include;$SCITECH/include;$PRIVATE/include"
+export USE_LINUX=1
+
+if [ "x$LIBC" = x ]; then
+	echo "GCC Linux console compilation environment set up (glib)"
+else
+	echo "GCC Linux console compilation environment set up (libc5)"
+fi
diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat
new file mode 100755
index 0000000..13c4783
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat
@@ -0,0 +1,26 @@
+@echo off
+REM Setup for compiling with GNU C compiler
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include
+set MAKESTARTUP=%SCITECH%\makedefs\gcc_win32.mk
+set MAKE_MODE=
+set USE_WIN16=
+set USE_WIN32=1
+set WIN32_GUI=
+set USE_SNAP=
+set GCC_LIBBASE=gcc2
+PATH %SCITECH_BIN%;%GCC2_PATH%\NATIVE\BIN;%DEFPATH%
+
+echo GCC 2.9.x 32-bit Win32 console compilation environment set up
+
diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat
new file mode 100755
index 0000000..97cb8bd
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat
@@ -0,0 +1,28 @@
+@echo off
+REM Setup for compiling with DJGPP 2.02
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\release\dos32\dj2
+%SCITECH%\bin-dos\k_cp %SCITECH%\BIN\DJGPP.ENV %DJ_PATH%\DJGPP.ENV
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\debug\dos32\dj2
+%SCITECH%\bin-dos\k_cp %SCITECH%\BIN\DJGPP_DB.ENV %DJ_PATH%\DJGPP.ENV
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set DJGPP=%DJ_PATH%\DJGPP.ENV
+set INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%DJ_PATH%\INCLUDE;
+set MAKESTARTUP=%SCITECH%\MAKEDEFS\DJ32.MK
+set USE_WIN16=
+set USE_WIN32=
+set WIN32_GUI=
+set USE_SNAP=
+set DJ_LIBBASE=dj2
+PATH %SCITECH_BIN%;%DJ_PATH%\BIN;%DEFPATH%
+
+echo DJGPP 2.02 32-bit DOS compilation environment set up (DPMI).
+
diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat
new file mode 100755
index 0000000..ceb2ab8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat
@@ -0,0 +1,26 @@
+@echo off
+REM Setup for compiling with GNU C cross-compiler
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include
+set MAKESTARTUP=%SCITECH%\MAKEDEFS\gcc_linux.mk
+set MAKE_MODE=UNIX
+set USE_WIN16=
+set USE_WIN32=
+set WIN32_GUI=
+set USE_SNAP=
+set GCC_LIBBASE=gcc2
+PATH %SCITECH_BIN%;%GCC2_PATH%\cross-linux\i386-redhat-linux\BIN;%DEFPATH%
+
+echo GCC 2.9.x 32-bit Linux console cross compilation environment set up
+
diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat
new file mode 100755
index 0000000..bdb31aa
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat
@@ -0,0 +1,26 @@
+@echo off
+REM Setup for compiling with GNU C compiler
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include
+set MAKESTARTUP=%SCITECH%\makedefs\gcc_win32.mk
+set MAKE_MODE=
+set USE_WIN16=
+set USE_WIN32=1
+set WIN32_GUI=1
+set USE_SNAP=
+set GCC_LIBBASE=gcc2
+PATH %SCITECH_BIN%;%GCC2_PATH%\NATIVE\BIN;%DEFPATH%
+
+echo GCC 2.9.x 32-bit Win32 GUI compilation environment set up
+
diff --git a/board/MAI/bios_emulator/scitech/bin/makelib.bat b/board/MAI/bios_emulator/scitech/bin/makelib.bat
new file mode 100755
index 0000000..6316734
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/makelib.bat
@@ -0,0 +1,97 @@
+call wc11-d32.bat
+
+cd c:\private\src\license
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\pm
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\console
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\nucleus
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\zlib
+dmake clean
+dmake depend
+dmake -u install
+
+cd c:\private\src\graphics\ref2d
+dmake clean
+dmake depend
+dmake -u install
+cd c:\private\src\drvlib
+dmake clean
+dmake depend
+dmake -u install
+
+call wc11-w32.bat
+
+cd c:\private\src\license
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\pm
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\console
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\nucleus
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\zlib
+dmake clean
+dmake depend
+dmake -u install
+
+cd c:\private\src\graphics\ref2d
+dmake clean
+dmake depend
+dmake -u install
+cd c:\private\src\drvlib
+dmake clean
+dmake depend
+dmake -u install
+
+call wc10-d32.bat
+
+cd c:\private\src\license
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\pm
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\console
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\nucleus
+dmake clean
+dmake depend
+dmake -u install
+cd c:\scitech\src\zlib
+dmake clean
+dmake depend
+dmake -u install
+
+cd c:\private\src\graphics\ref2d
+dmake clean
+dmake depend
+dmake -u install
+cd c:\private\src\drvlib
+dmake clean
+dmake depend
+dmake -u install
+
+cd \private\src\graphics\drivers
diff --git a/board/MAI/bios_emulator/scitech/bin/meltobjs.sh b/board/MAI/bios_emulator/scitech/bin/meltobjs.sh
new file mode 100755
index 0000000..fd1804b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/meltobjs.sh
@@ -0,0 +1,23 @@
+#! /bin/sh
+#
+# This script generates a single object file from a set of libraries (*.a files)
+# Usage: meltobjs.sh target.o library1.a library2.a ...
+#
+# (C) SciTech Software, Inc. 1998
+#
+
+TMPDIR=/tmp/melt$$
+TARGET=$1
+TARGETDIR=$PWD
+shift
+mkdir $TMPDIR
+
+cd $TMPDIR
+
+for a in $*
+do
+    ar x $a
+done
+ld -r -o $TARGETDIR/$TARGET *.o
+
+rm -fr $TMPDIR
\ No newline at end of file
diff --git a/board/MAI/bios_emulator/scitech/bin/ntddk.bat b/board/MAI/bios_emulator/scitech/bin/ntddk.bat
new file mode 100755
index 0000000..07c0d78
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/ntddk.bat
@@ -0,0 +1,42 @@
+@echo off
+REM: Set up environment variables for Microsoft Windows NT DDK development.
+REM: Note that we have hard coded this for Windows NT i386 development.
+
+SET USE_NTDRV=1
+SET USE_W2KDRV=
+SET BASEDIR=%NT_DDKROOT%
+SET PATH=%BASEDIR%\bin;%PATH%
+SET NTMAKEENV=%BASEDIR%\inc
+SET BUILD_MAKE_PROGRAM=nmake.exe
+SET BUILD_DEFAULT=-ei -nmake -i
+SET BUILD_DEFAULT_TARGETS=-386
+SET _OBJ_DIR=obj
+SET NEW_CRTS=1
+SET _NTROOT=%BASEDIR%
+SET INCLUDE=%BASEDIR%\inc;%INCLUDE%
+
+if .%CHECKED%==.1 goto checked
+
+REM: set up an NT free build environment
+SET DDKBUILDENV=free
+SET C_DEFINES=-D_IDWBUILD
+SET NTDBGFILES=1
+SET NTDEBUG=
+SET NTDEBUGTYPE=
+SET MSC_OPTIMIZATION=
+set LIB=%BASEDIR%\lib\i386\free;%SCITECH_LIB%\LIB\RELEASE\NTDRV\VC6;%MSVCDir%\LIB;.
+
+goto done
+
+:checked
+
+REM: set up an NT checked build environment
+SET DDKBUILDENV=checked
+SET C_DEFINES=-D_IDWBUILD -DRDRDBG -DSRVDBG
+SET NTDBGFILES=
+SET NTDEBUG=ntsd
+SET NTDEBUGTYPE=both
+SET MSC_OPTIMIZATION=/Od /Oi
+set LIB=%BASEDIR%\lib\i386\free;%SCITECH_LIB%\LIB\DEBUG\NTDRV\VC6;%MSVCDir%\LIB;.
+
+:done
diff --git a/board/MAI/bios_emulator/scitech/bin/qnx4.sh b/board/MAI/bios_emulator/scitech/bin/qnx4.sh
new file mode 100755
index 0000000..843c4d9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/qnx4.sh
@@ -0,0 +1,18 @@
+#! /bin/sh
+
+# Setup for compiling with Watcom C/C++ for QNX4
+
+if [ "$CHECKED" = "1" ]; then
+    echo Checked debug build enabled.
+else
+    echo Release build enabled.
+fi
+
+export MAKESTARTUP=$SCITECH/makedefs/qnx4.mk
+export INCLUDE="-I$SCITECH/include -I$PRIVATE/include -I/usr/include"
+export USE_QNX=1
+export USE_QNX4=1
+export WC_LIBBASE=wc10
+
+echo Qnx 4 console compilation environment set up
+
diff --git a/board/MAI/bios_emulator/scitech/bin/qnxnto.sh b/board/MAI/bios_emulator/scitech/bin/qnxnto.sh
new file mode 100755
index 0000000..c114f9e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/qnxnto.sh
@@ -0,0 +1,21 @@
+#! /bin/sh
+
+# Setup for compiling with Watcom C/C++ for QNX Neutrino
+
+if [ "$CHECKED" = "1" ]; then
+    echo Checked debug build enabled.
+else
+    echo Release build enabled.
+fi
+
+if [ X$GCC_PATH = "X" ]; then
+	export GCC_PATH=/usr/gcc/bin
+fi
+
+export MAKESTARTUP=$SCITECH/makedefs/qnxnto.mk
+export INCLUDE="-I$SCITECH/include -I$PRIVATE/include -I/usr/nto/include"
+export USE_BIOS=1	# VBIOS lib is tiny under Neutrino, always include it
+export USE_QNX=1
+export USE_QNXNTO=1
+
+echo Qnx Neutrino console compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh
new file mode 100755
index 0000000..0a272d6
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh
@@ -0,0 +1,42 @@
+#! /bin/sh
+
+# BeOS VERSION
+# Set the place where SciTech Software is installed, and where each
+# of the supported compilers is installed. These environment variables
+# are used by the batch files in the SCITECH\BIN directory.
+#
+# Modify the as appropriate for your compiler configuration (you should
+# only need to change things in this batch file).
+#
+# This version is for a normal BeOS installation.
+
+# The SCITECH variable points to where batch files, makefile startups,
+# include files and source files will be found when compiling.
+
+export SCITECH=$MGL_ROOT 
+
+# The SCITECH_LIB variable points to where the SciTech libraries live
+# for installation and linking. This allows you to have the source and
+# include files on local machines for compiling and have the libraries
+# located on a common network machine (for network builds).
+
+export SCITECH_LIB=$SCITECH
+
+# The PRIVATE variable points to where private source files reside that
+# do not live in the public source tree
+
+export PRIVATE=$HOME/private
+
+# The following define the locations of all the compilers that you may
+# be using. Change them to reflect where you have installed your
+# compilers.
+
+export GCC_PATH=/boot/develop/tools/gnupro/bin
+
+# Add the Scitech bin path to the current PATH
+export PATH=$SCITECH/bin:$SCITECH/bin-beos:$PATH
+#if [ "x$LIBC" = x ]; then
+#	export PATH=$PATH:$SCITECH/bin-beos/glibc
+#else
+#	export PATH=$PATH:$SCITECH/bin-beos/libc
+#fi
diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh
new file mode 100755
index 0000000..c920748
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh
@@ -0,0 +1,37 @@
+#! /bin/sh
+
+# LINUX VERSION
+# Set the place where SciTech Software is installed, and where each
+# of the supported compilers is installed. These environment variables
+# are used by the batch files in the SCITECH\BIN directory.
+#
+# Modify the as appropriate for your compiler configuration (you should
+# only need to change things in this batch file).
+#
+# This version is for a normal Linux installation.
+
+# The SCITECH variable points to where batch files, makefile startups,
+# include files and source files will be found when compiling.
+
+export SCITECH=$MGL_ROOT 
+
+# The SCITECH_LIB variable points to where the SciTech libraries live
+# for installation and linking. This allows you to have the source and
+# include files on local machines for compiling and have the libraries
+# located on a common network machine (for network builds).
+
+export SCITECH_LIB=$SCITECH
+
+# The PRIVATE variable points to where private source files reside that
+# do not live in the public source tree
+
+export PRIVATE=$HOME/private
+
+# The following define the locations of all the compilers that you may
+# be using. Change them to reflect where you have installed your
+# compilers.
+
+export GCC_PATH=/usr/bin
+
+# Add the Scitech bin path to the current PATH
+export PATH=$SCITECH/bin:$SCITECH/bin-freebsd:$PATH
diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh
new file mode 100755
index 0000000..35cbf1d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh
@@ -0,0 +1,43 @@
+#! /bin/sh
+
+# LINUX VERSION
+# Set the place where SciTech Software is installed, and where each
+# of the supported compilers is installed. These environment variables
+# are used by the batch files in the SCITECH\BIN directory.
+#
+# Modify the as appropriate for your compiler configuration (you should
+# only need to change things in this batch file).
+#
+# This version is for a normal Linux installation.
+
+# The SCITECH variable points to where batch files, makefile startups,
+# include files and source files will be found when compiling.
+
+export SCITECH=$MGL_ROOT 
+
+# The SCITECH_LIB variable points to where the SciTech libraries live
+# for installation and linking. This allows you to have the source and
+# include files on local machines for compiling and have the libraries
+# located on a common network machine (for network builds).
+
+export SCITECH_LIB=$SCITECH
+
+# The PRIVATE variable points to where private source files reside that
+# do not live in the public source tree
+
+export PRIVATE=$HOME/private
+
+# The following define the locations of all the compilers that you may
+# be using. Change them to reflect where you have installed your
+# compilers.
+
+export GCC_PATH=/usr/bin
+export TEMP=/tmp TMP=/tmp
+
+# Add the Scitech bin path to the current PATH
+export PATH=$SCITECH/bin:$SCITECH/bin-linux:$PATH
+if [ "x$LIBC" = x ]; then
+	export PATH=$SCITECH/bin-linux/glibc:$PATH
+else
+	export PATH=$SCITECH/bin-linux/libc:$PATH
+fi
diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh
new file mode 100755
index 0000000..1d73109
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh
@@ -0,0 +1,37 @@
+#! /bin/sh
+
+# QNX 4 VERSION
+# Set the place where SciTech Software is installed, and where each
+# of the supported compilers is installed. These environment variables
+# are used by the batch files in the SCITECH\BIN directory.
+#
+# Modify the as appropriate for your compiler configuration (you should
+# only need to change things in this batch file).
+#
+# This version is for a normal Linux installation.
+
+# The SCITECH variable points to where batch files, makefile startups,
+# include files and source files will be found when compiling.
+
+export SCITECH=$MGL_ROOT 
+
+# The SCITECH_LIB variable points to where the SciTech libraries live
+# for installation and linking. This allows you to have the source and
+# include files on local machines for compiling and have the libraries
+# located on a common network machine (for network builds).
+
+export SCITECH_LIB=$SCITECH
+
+# The PRIVATE variable points to where private source files reside that
+# do not live in the public source tree
+
+export PRIVATE=$HOME/private
+
+# The following define the locations of all the compilers that you may
+# be using. Change them to reflect where you have installed your
+# compilers.
+
+export WC10_PATH=/usr/watcom/10.6/usr
+
+# Add the Scitech bin path to the current PATH
+export PATH=$SCITECH/bin:$SCITECH/bin-qnx:$PATH
diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars.bat b/board/MAI/bios_emulator/scitech/bin/set-vars.bat
new file mode 100755
index 0000000..2a2101d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/set-vars.bat
@@ -0,0 +1,110 @@
+@echo off
+REM:=========================================================================
+REM: Master batch file to set up all necessary environment variables for
+REM: the SciTech makefile utilities. This batch file should be executed
+REM: *first* before any other batch files when you start a command shell.
+REM: You should not need to modify any batch files except this one to
+REM: configure the makefile utilities.
+REM:=========================================================================
+
+REM: Set the place where SciTech Software is installed, and where each
+REM: of the supported compilers is installed. These environment variables
+REM: are used by the batch files in the SCITECH\BIN directory.
+REM:
+REM: Modify the as appropriate for your compiler configuration (you should
+REM: only need to change things in this batch file).
+REM:
+REM: This version is for a normal MSDOS installation.
+
+REM: The SCITECH variable points to where batch files, makefile startups,
+REM: include files and source files will be found when compiling.
+
+SET SCITECH=c:\scitech
+
+REM: The SCITECH_LIB variable points to where the SciTech libraries live
+REM: for installation and linking. This allows you to have the source and
+REM: include files on local machines for compiling and have the libraries
+REM: located on a common network machine (for network builds).
+
+SET SCITECH_LIB=%SCITECH%
+
+REM: The PRIVATE variable points to where private source files reside that
+REM: do not live in the public source tree
+
+SET PRIVATE=c:\private
+
+REM: The following sets up the path to the SciTech command line utilities
+REM: for the development operating system. We select either DOS hosted
+REM: tools or Win32 hosted tools depending on whether you are running
+REM: on NT or not. Windows 9x users can use the Win32 hosted tools but
+REM: they run slower, but you will have long filenames if you do this.
+
+IF .%OS%==.Windows_NT goto Win32_path
+IF NOT .%WINDIR%==. goto Win32_path
+SET SCITECH_BIN=%SCITECH%\bin;%SCITECH%\bin-dos
+goto path_set
+
+REM: The following sets up the path to the SciTech command line utilities
+REM: for the development operating system. This version uses the Win32
+REM: hosted tools by default, so you can use long filenames.
+
+:Win32_path
+SET SCITECH_BIN=%SCITECH%\bin;%SCITECH%\bin-win32
+
+:path_set
+
+REM: Set the TMP variable for dmake if this is not already set
+
+SET TMP=%SCITECH%
+
+REM: Set the following environment variable to use the Netwide Assembler
+REM: (NASM) provided with the MGL tools to build all assembler modules.
+REM: If you have Turbo Assembler 4.0 or later and you wish to use it,
+REM: you can use it by removing the following line.
+
+SET USE_NASM=1
+
+REM: The following is used to set up DDK directories for device driver
+REM: development. They can safely be ignored unless you are using the
+REM: SciTech makefile utilities to build device drivers.
+
+SET DDKDRIVE=c:
+SET MSSDK=c:\c\win32sdk
+SET W95_DDKROOT=c:\c\95ddk
+SET W98_DDKROOT=c:\c\98ddk
+SET NT_DDKROOT=c:\c\ntddk
+SET W2K_DDKROOT=c:\c\2000ddk
+SET MASM_ROOT=c:\c\masm611
+SET VTOOLSD=c:\c\vtd95
+SET SOFTICE_PATH=c:\c\sint
+
+REM: The following define the locations of all the compilers that you may
+REM: be using. Change them to reflect where you have installed your
+REM: compilers.
+
+SET BC3_PATH=c:\c\bc3
+SET BC4_PATH=c:\c\bc45
+SET BC5_PATH=c:\c\bc50
+SET BCB5_PATH=c:\c\bcb50
+SET VC_PATH=c:\c\msvc
+SET VC4_PATH=c:\c\vc42
+SET VC5_PATH=c:\c\vc50
+SET VC6_PATH=c:\c\vc60
+SET SC70_PATH=c:\c\sc75
+SET WC10A_PATH=c:\c\wc10a
+SET WC10_PATH=c:\c\wc10
+SET WC11_PATH=c:\c\wc11
+SET TNT_PATH=c:\c\tnt
+SET DJ_PATH=c:\c\djgpp
+SET GCC2_PATH=c:\unix\usr
+
+REM: The following define the locations of the IDE and compiler path
+REM: tools for Visual C++. If you do a standard installation, you wont
+REM: need to change this. If however you did a custom install and changed
+REM: the paths to these directory, you will need to modify this to suit.
+
+SET VC5_MSDevDir=%VC5_PATH%\sharedide
+SET VC5_MSVCDir=%VC5_PATH%\vc
+SET VC6_MSDevDir=%VC6_PATH%\common\msdev98
+SET VC6_MSVCDir=%VC6_PATH%\vc98
+
diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat
new file mode 100755
index 0000000..71f7d8e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat
@@ -0,0 +1,36 @@
+@echo off
+REM Setup environment variables for Visual C++ 4.2 32 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC4_PATH%
+set C_INCLUDE=%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE;
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+set INIT=%VC4_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET WIN32_GUI=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=VC4
+PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto done
+call win32sdk.bat
+
+:done
+echo Visual C++ 4.2 32 bit Windows compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat
new file mode 100755
index 0000000..9817493
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat
@@ -0,0 +1,27 @@
+@echo off
+REM Setup environment variables for Visual C++ 1.52c 16 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC4;%VC_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC4;%VC_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC_PATH%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE;
+set INIT=%VC_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=VC4
+PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH%
+
+echo Visual C++ 1.52c 16 DOS bit compilation environment set up.
+
diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat
new file mode 100755
index 0000000..62e3521
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat
@@ -0,0 +1,21 @@
+@echo off
+REM Setup environment variables for Visual C++ 4.2 32 bit edition
+
+REM: First setup for Win32 console development
+call vc40-c32.bat > NUL
+
+REM: Extra stuff to set up for Windows 9x DDK development
+set MASTER_MAKE=1
+set DDKROOT=%W95_DDKROOT%
+set SDKROOT=%MSSDK%
+set C16_ROOT=%VC_PATH%
+set C32_ROOT=%VC4_PATH%
+
+if .%CHECKED%==.1 goto checked_build
+echo Release build enabled.
+goto done
+:checked_build
+echo Checked debug build enabled.
+goto done
+:done
+echo Visual C++ 4.2 Windows 9x driver compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat
new file mode 100755
index 0000000..83b6780
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat
@@ -0,0 +1,18 @@
+@echo off
+REM Setup environment variables for Visual C++ 4.2 32 bit edition
+
+REM: First setup for Win32 console development (with Platform SDK)
+call vc40-c32.bat sdk > NUL
+
+REM: Extra stuff to set up for Windows NT DDK development
+SET BASEDIR=%NT_DDKROOT%
+SET PATH=%NT_DDKROOT%\bin;%PATH%
+
+if .%CHECKED%==.1 goto checked_build
+echo Release build enabled.
+goto done
+:checked_build
+echo Checked debug build enabled.
+goto done
+:done
+echo Visual C++ 4.2 Windows NT driver compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat
new file mode 100755
index 0000000..7997044
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat
@@ -0,0 +1,31 @@
+@echo off
+REM Setup environment variables for Visual C++ 4.2 32 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC4_PATH%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE
+set INIT=%VC4_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=
+SET WIN32_GUI=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=1
+SET VC_LIBBASE=VC4
+PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+echo Visual C++ 4.2 Snap compilation environment set up
+
diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat
new file mode 100755
index 0000000..b0fc936
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat
@@ -0,0 +1,42 @@
+@echo off
+REM Setup environment variables for Visual C++ 4.2 32 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\COFFLIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\COFFLIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC4_PATH%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE;
+set INIT=%VC4_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_TNT=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=VC4
+PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+REM If you set the following to a 1, a TNT DosStyle app will be created.
+REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
+REM run under real DOS when using our libraries, since we require access
+REM to functions that the Win32 API does not support (such as direct access
+REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
+REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
+REM work too well).
+REM
+REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
+REM and hence will never be able to run under Win95 or WinNT, only DOS.
+
+SET DOSSTYLE=
+
+echo Visual C++ 4.2 32-bit DOS compilation environment set up (TNT).
diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat
new file mode 100755
index 0000000..2849a20
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat
@@ -0,0 +1,26 @@
+@echo off
+REM Setup environment variables for Visual C++ 1.52c 16 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC4;%VC_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC4;%VC_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC_PATH%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE;
+set INIT=%VC_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK
+SET USE_WIN16=1
+SET USE_WIN32=
+SET VC_LIBBASE=VC4
+SET USE_RTTARGET=
+SET USE_SNAP=
+PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH%
+
+echo Visual C++ 1.52c 16 bit Windows compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat
new file mode 100755
index 0000000..d93a624
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat
@@ -0,0 +1,37 @@
+@echo off
+REM Setup environment variables for Visual C++ 4.2 32 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC4_PATH%
+set C_INCLUDE=%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE;
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+set INIT=%VC4_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET WIN32_GUI=1
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=VC4
+PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto done
+call win32sdk.bat
+
+:done
+echo Visual C++ 4.2 32 bit Windows compilation environment set up
+
diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat
new file mode 100755
index 0000000..a420a54
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat
@@ -0,0 +1,20 @@
+@echo off
+REM Setup environment variables for Visual C++ 4.2 32 bit edition
+
+SET LIB=%VC4_PATH%\LIB;.
+SET TOOLROOTDIR=%VC4_PATH%
+SET INCLUDE=\xc\include;%VC4_PATH%\INCLUDE
+SET INIT=%VC4_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET WIN32_GUI=1
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=VC4
+PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%DEFPATH%
+
+echo Visual C++ 4.2 X11 compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat
new file mode 100755
index 0000000..62d27b9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat
@@ -0,0 +1,39 @@
+@echo off
+REM Setup environment variables for Visual C++ 5.0 32 bit edition
+
+SET MSDevDir=%VC5_MSDevDir%
+SET MSVCDir=%VC5_MSVCDir%
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%MSVCDir%
+set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE;
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+set INIT=%MSVCDir%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET WIN32_GUI=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc5
+PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto done
+call win32sdk.bat
+
+:done
+echo Visual C++ 5.0 32-bit Windows console compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat
new file mode 100755
index 0000000..c789c50
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat
@@ -0,0 +1,26 @@
+@echo off
+REM Setup environment variables for Visual C++ 1.52c 16 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC5;%VC_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC5;%VC_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC_PATH%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE;
+set INIT=%VC_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc5
+PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH%
+
+echo Visual C++ 1.52c 16-bit DOS compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat
new file mode 100755
index 0000000..27a4a14
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat
@@ -0,0 +1,21 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+REM: First setup for Win32 console development
+call vc60-c32.bat > NUL
+
+REM: Extra stuff to set up for Windows 9x DDK development
+set MASTER_MAKE=1
+set DDKROOT=%W95_DDKROOT%
+set SDKROOT=%MSSDK%
+set C16_ROOT=%VC_PATH%
+set C32_ROOT=%VC6_PATH%
+
+if .%CHECKED%==.1 goto checked_build
+echo Release build enabled.
+goto done
+:checked_build
+echo Checked debug build enabled.
+goto done
+:done
+echo Visual C++ 6.0 Windows 9x driver compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat
new file mode 100755
index 0000000..17b2f25
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat
@@ -0,0 +1,17 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+REM: First setup for Win32 console development (with Platform SDK)
+call vc60-c32.bat sdk > NUL
+
+REM: Now setup stuff for the NT DDK build environment
+call ntddk.bat
+
+if .%CHECKED%==.1 goto checked_build
+echo Release build enabled.
+goto done
+:checked_build
+echo Checked debug build enabled.
+goto done
+:done
+echo Visual C++ 6.0 Windows NT driver compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat
new file mode 100755
index 0000000..afb2fb1
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat
@@ -0,0 +1,30 @@
+@echo off
+REM Setup environment variables for Visual C++ 5.0 32 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC5_PATH%\VC
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC5_PATH%\VC\INCLUDE;%TNT_PATH%\INCLUDE;
+set INIT=%VC5_PATH%\VC
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=
+SET WIN32_GUI=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=1
+SET USE_SNAP=
+SET VC_LIBBASE=vc5
+PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+echo Visual C++ 5.0 RTTarget-32 compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat
new file mode 100755
index 0000000..22d2e13
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat
@@ -0,0 +1,33 @@
+@echo off REM Setup environment variables for Visual C++ 5.0 32 bit
+edition
+
+SET MSDevDir=%VC5_MSDevDir%
+SET MSVCDir=%VC5_MSVCDir%
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%MSVCDir%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE
+set INIT=%MSVCDir%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=
+SET WIN32_GUI=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=1
+SET VC_LIBBASE=vc5
+PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+echo Visual C++ 5.0 Snap compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat
new file mode 100755
index 0000000..6b09199
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat
@@ -0,0 +1,42 @@
+@echo off
+REM Setup environment variables for Visual C++ 5.0 32 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\COFFLIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\COFFLIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC5_PATH%\VC
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC5_PATH%\VC\INCLUDE;%TNT_PATH%\INCLUDE;
+set INIT=%VC5_PATH%\VC
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_TNT=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc5
+PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+REM If you set the following to a 1, a TNT DosStyle app will be created.
+REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
+REM run under real DOS when using our libraries, since we require access
+REM to functions that the Win32 API does not support (such as direct access
+REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
+REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
+REM work too well).
+REM
+REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
+REM and hence will never be able to run under Win95 or WinNT, only DOS.
+
+SET DOSSTYLE=
+
+echo Visual C++ 5.0 32-bit compilation environment set up (with TNT).
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat
new file mode 100755
index 0000000..52ab495
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat
@@ -0,0 +1,27 @@
+@echo off
+REM Setup environment variables for Visual C++ 1.52c 16 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC5;%VC_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC5;%VC_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC_PATH%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE;
+set INIT=%VC_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK
+SET USE_WIN16=1
+SET USE_WIN32=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc5
+PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH%
+
+echo Visual C++ 1.52c 16-bit Windows compilation environment set up.
+
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat
new file mode 100755
index 0000000..07bc5e5
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat
@@ -0,0 +1,39 @@
+@echo off
+REM Setup environment variables for Visual C++ 5.0 32 bit edition
+
+SET MSDevDir=%VC5_MSDevDir%
+SET MSVCDir=%VC5_MSVCDir%
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%MSVCDir%
+set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE;
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+set INIT=%MSVCDir%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET WIN32_GUI=1
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc5
+PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto done
+call win32sdk.bat
+
+:done
+echo Visual C++ 5.0 32-bit Windows console compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat
new file mode 100755
index 0000000..fe286bd
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat
@@ -0,0 +1,20 @@
+@echo off
+REM Setup environment variables for Visual C++ 5.0 32 bit edition
+
+SET LIB=%VC5_PATH%\VC\LIB;.
+SET TOOLROOTDIR=%VC5_PATH%\VC
+SET INCLUDE=\xc\include;%VC5_PATH%\VC\INCLUDE
+SET INIT=%VC5_PATH%\VC
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET WIN32_GUI=1
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc5
+PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%DEFPATH%
+
+echo Visual C++ 5.0 X11 compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat
new file mode 100755
index 0000000..e98417d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat
@@ -0,0 +1,39 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+SET MSDevDir=%VC6_MSDevDir%
+SET MSVCDir=%VC6_MSVCDir%
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%MSVCDir%
+set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+set INIT=%MSVCDir%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET WIN32_GUI=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc6
+PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto done
+call win32sdk.bat
+
+:done
+echo Visual C++ 6.0 32-bit Windows console compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat
new file mode 100755
index 0000000..10855e0
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat
@@ -0,0 +1,26 @@
+@echo off
+REM Setup environment variables for Visual C++ 1.52c 16 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC6;%VC_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC6;%VC_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC_PATH%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE;
+set INIT=%VC_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc6
+PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH%
+
+echo Visual C++ 1.52c 16-bit DOS compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat
new file mode 100755
index 0000000..27a4a14
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat
@@ -0,0 +1,21 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+REM: First setup for Win32 console development
+call vc60-c32.bat > NUL
+
+REM: Extra stuff to set up for Windows 9x DDK development
+set MASTER_MAKE=1
+set DDKROOT=%W95_DDKROOT%
+set SDKROOT=%MSSDK%
+set C16_ROOT=%VC_PATH%
+set C32_ROOT=%VC6_PATH%
+
+if .%CHECKED%==.1 goto checked_build
+echo Release build enabled.
+goto done
+:checked_build
+echo Checked debug build enabled.
+goto done
+:done
+echo Visual C++ 6.0 Windows 9x driver compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat
new file mode 100755
index 0000000..17b2f25
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat
@@ -0,0 +1,17 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+REM: First setup for Win32 console development (with Platform SDK)
+call vc60-c32.bat sdk > NUL
+
+REM: Now setup stuff for the NT DDK build environment
+call ntddk.bat
+
+if .%CHECKED%==.1 goto checked_build
+echo Release build enabled.
+goto done
+:checked_build
+echo Checked debug build enabled.
+goto done
+:done
+echo Visual C++ 6.0 Windows NT driver compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat
new file mode 100755
index 0000000..f304293
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat
@@ -0,0 +1,17 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+REM: First setup for Win32 console development (with Platform SDK)
+call vc60-c32.bat sdk > NUL
+
+REM: Now setup stuff for the NT DDK build environment
+call w2kddk.bat
+
+if .%CHECKED%==.1 goto checked_build
+echo Release build enabled.
+goto done
+:checked_build
+echo Checked debug build enabled.
+goto done
+:done
+echo Visual C++ 6.0 Windows Windows 2000 driver compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat
new file mode 100755
index 0000000..5348ef9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat
@@ -0,0 +1,33 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+SET MSDevDir=%VC6_MSDevDir%
+SET MSVCDir=%VC6_MSVCDir%
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%MSVCDir%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE
+set INIT=%MSVCDir%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=
+SET WIN32_GUI=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=1
+SET VC_LIBBASE=vc6
+PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+echo Visual C++ 6.0 Snap compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat
new file mode 100755
index 0000000..1d8b5e3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat
@@ -0,0 +1,42 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC6;%VC6_PATH%\VC98\LIB;%TNT_PATH%\COFFLIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC6;%VC6_PATH%\VC98\LIB;%TNT_PATH%\COFFLIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC6_PATH%\VC98
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC6_PATH%\VC98\INCLUDE;%TNT_PATH%\INCLUDE;
+set INIT=%VC6_PATH%\VC98
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_TNT=
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc6 PATH
+%SCITECH_BIN%;%VC6_PATH%\VC98\BIN;%VC6_PATH%\COMMON\MSDEV98\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+REM If you set the following to a 1, a TNT DosStyle app will be created.
+REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
+REM run under real DOS when using our libraries, since we require access
+REM to functions that the Win32 API does not support (such as direct access
+REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
+REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
+REM work too well).
+REM
+REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
+REM and hence will never be able to run under Win95 or WinNT, only DOS.
+
+SET DOSSTYLE=
+
+echo Visual C++ 6.0 32-bit compilation environment set up (with TNT).
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat
new file mode 100755
index 0000000..70175c3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat
@@ -0,0 +1,27 @@
+@echo off
+REM Setup environment variables for Visual C++ 1.52c 16 bit edition
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC6;%VC_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC6;%VC_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%VC_PATH%
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE;
+set INIT=%VC_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK
+SET USE_WIN16=1
+SET USE_WIN32=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc6
+PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH%
+
+echo Visual C++ 1.52c 16-bit Windows compilation environment set up.
+
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat
new file mode 100755
index 0000000..2f8e7ab
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat
@@ -0,0 +1,39 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+SET MSDevDir=%VC6_MSDevDir%
+SET MSVCDir=%VC6_MSVCDir%
+
+if .%CHECKED%==.1 goto checked_build
+set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+set TOOLROOTDIR=%MSVCDir%
+set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE
+set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+set INIT=%MSVCDir%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET WIN32_GUI=1
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc6
+PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto done
+call win32sdk.bat
+
+:done
+echo Visual C++ 6.0 32-bit Windows compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat
new file mode 100755
index 0000000..57b23d2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat
@@ -0,0 +1,20 @@
+@echo off
+REM Setup environment variables for Visual C++ 6.0 32 bit edition
+
+SET LIB=%VC6_PATH%\VC98\LIB;.
+SET TOOLROOTDIR=%VC6_PATH%\VC98
+SET INCLUDE=\xc\include;%VC6_PATH%\VC98\INCLUDE;
+SET INIT=%VC6_PATH%\VC98
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK
+SET USE_TNT=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET WIN32_GUI=1
+SET USE_VXD=
+SET USE_NTDRV=
+SET USE_RTTARGET=
+SET USE_SNAP=
+SET VC_LIBBASE=vc6
+PATH %SCITECH_BIN%;%VC6_PATH%\VC98\BIN;%VC6_PATH%\COMMON\MSDEV98\BIN;%DEFPATH%
+
+echo Visual C++ 6.0 X11 compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/w2kddk.bat b/board/MAI/bios_emulator/scitech/bin/w2kddk.bat
new file mode 100755
index 0000000..92858d1
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/w2kddk.bat
@@ -0,0 +1,42 @@
+@echo off
+REM: Set up environment variables for Microsoft Windows NT DDK development.
+REM: Note that we have hard coded this for Windows NT i386 development.
+
+SET USE_NTDRV=1
+SET USE_W2KDRV=1
+SET BASEDIR=%W2K_DDKROOT%
+SET PATH=%BASEDIR%\bin;%PATH%
+SET NTMAKEENV=%BASEDIR%\inc
+SET BUILD_MAKE_PROGRAM=nmake.exe
+SET BUILD_DEFAULT=-ei -nmake -i
+SET BUILD_DEFAULT_TARGETS=-386
+SET _OBJ_DIR=obj
+SET NEW_CRTS=1
+SET _NTROOT=%BASEDIR%
+SET INCLUDE=%BASEDIR%\inc;%BASEDIR%\inc\ddk;%INCLUDE%
+
+if .%CHECKED%==.1 goto checked
+
+REM: set up an NT free build environment
+SET DDKBUILDENV=free
+SET C_DEFINES=-D_IDWBUILD
+SET NTDBGFILES=1
+SET NTDEBUG=
+SET NTDEBUGTYPE=
+SET MSC_OPTIMIZATION=
+set LIB=%BASEDIR%\libfre\i386;%SCITECH_LIB%\LIB\RELEASE\W2KDRV\VC6;%MSVCDir%\LIB;.
+
+goto done
+
+:checked
+
+REM: set up an NT checked build environment
+SET DDKBUILDENV=checked
+SET C_DEFINES=-D_IDWBUILD -DRDRDBG -DSRVDBG
+SET NTDBGFILES=
+SET NTDEBUG=ntsd
+SET NTDEBUGTYPE=both
+SET MSC_OPTIMIZATION=/Od /Oi
+set LIB=%BASEDIR%\libchk\i386;%SCITECH_LIB%\LIB\DEBUG\W2KDRV\VC6;%MSVCDir%\LIB;.
+
+:done
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat
new file mode 100755
index 0000000..2d738f3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT;
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_WIN386=
+SET WIN32_GUI=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC10
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 Win32 console compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat
new file mode 100755
index 0000000..5c53a90
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat
@@ -0,0 +1,30 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (DOS4GW)
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC10;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC10;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\WIN;
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC10
+SET EDPATH=%WC10_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 16-bit DOS compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat
new file mode 100755
index 0000000..a5c7210
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (DOS4GW)
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC10
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 32-bit DOS compilation environment set up (DOS4GW)
+
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat
new file mode 100755
index 0000000..579dece
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat
@@ -0,0 +1,31 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 16-bit OS/2 mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\lib\release\os216\wc10;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\lib\debug\os216\wc10;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\eddat
+SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=1
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=wc10
+SET EDPATH=%WC10_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 16-bit OS/2 compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat
new file mode 100755
index 0000000..3404b42
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat
@@ -0,0 +1,31 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32-bit OS/2 mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\eddat
+SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=1
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=wc10
+SET EDPATH=%WC10_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 32-bit OS/2 console compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat
new file mode 100755
index 0000000..57057de
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat
@@ -0,0 +1,31 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32-bit OS/2 mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\eddat
+SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=1
+SET USE_OS2GUI=1
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=wc10
+SET EDPATH=%WC10_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 32-bit OS/2 GUI compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat
new file mode 100755
index 0000000..46f8659
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (QNX 4)
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\QNX4\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\QNX;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\QNX4\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\QNX;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\QH;
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=1
+SET WC_LIBBASE=WC10
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 32-bit QNX compilation environment set up
+
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat
new file mode 100755
index 0000000..1fde624
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET WIN32_GUI=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=1
+SET USE_QNX4=
+SET WC_LIBBASE=WC10
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 Snap compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat
new file mode 100755
index 0000000..d12f042
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat
@@ -0,0 +1,46 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode with Phar Lap TNT
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT;%TNT_PATH%\INCLUDE
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=1
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC10
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+REM If you set the following to a 1, a TNT DosStyle app will be created.
+REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
+REM run under real DOS when using our libraries, since we require access
+REM to functions that the Win32 API does not support (such as direct access
+REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
+REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
+REM work too well).
+REM
+REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
+REM and hence will never be able to run under Win95 or WinNT, only DOS.
+
+SET DOSSTYLE=1
+
+echo Watcom C/C++ 10.6 32-bit DOS compilation environment set up (TNT).
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat
new file mode 100755
index 0000000..e8ba871
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat
@@ -0,0 +1,32 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 16 bit Windows mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC10;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC10;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\WIN;
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK
+SET USE_WIN16=1
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC10
+SET EDPATH=%WC10_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 16-bit Windows compilation environment set up.
+
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat
new file mode 100755
index 0000000..839bdde
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT;
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_WIN386=
+SET WIN32_GUI=1
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC10
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 Win32 GUI compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat
new file mode 100755
index 0000000..fc783d8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat
@@ -0,0 +1,24 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode
+
+SET LIB=%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;.
+SET EDPATH=%WC10_PATH%\EDDAT
+SET INCLUDE=%WC10_PATH%\H;%WC10_PATH%\H\NT;
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_WIN386=
+SET WIN32_GUI=1
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC10
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.6 X11 compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat
new file mode 100755
index 0000000..6e0c24d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat
@@ -0,0 +1,33 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10A_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT;
+SET WATCOM=%WC10A_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_WIN386=
+SET WIN32_GUI=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET WC_LIBBASE=WC10A
+PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.0a Win32 console compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat
new file mode 100755
index 0000000..f9ecb67
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat
@@ -0,0 +1,29 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode (DOS4GW)
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC10A;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC10A;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10A_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\WIN;
+SET WATCOM=%WC10A_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET WC_LIBBASE=WC10A
+SET EDPATH=%WC10A_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.0a 16-bit DOS compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat
new file mode 100755
index 0000000..d52b79a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat
@@ -0,0 +1,32 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode (DOS4GW)
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10A_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;
+SET WATCOM=%WC10A_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET WC_LIBBASE=WC10A
+PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.0a 32-bit DOS compilation environment set up (DOS4GW)
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat
new file mode 100755
index 0000000..ba7351d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat
@@ -0,0 +1,30 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 16-bit OS/2 mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\lib\release\os216\wc10;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\lib\debug\os216\wc10;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10A_PATH%\eddat
+SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10A_PATH%\h\os2;%WC10A_PATH%\h
+SET WATCOM=%WC10A_PATH%
+SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=1
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET WC_LIBBASE=wc10
+SET EDPATH=%WC10A_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.0a 16-bit OS/2 compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat
new file mode 100755
index 0000000..f3caa59
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat
@@ -0,0 +1,30 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 32-bit OS/2 mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10AA_PATH%\eddat
+SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10AA_PATH%\h\os2;%WC10AA_PATH%\h
+SET WATCOM=%WC10AA_PATH%
+SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=1
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET WC_LIBBASE=WC10A
+SET EDPATH=%WC10AA_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10AA_PATH%\BINNT;%WC10AA6_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.0a 32-bit OS/2 console compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat
new file mode 100755
index 0000000..8d21c62
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat
@@ -0,0 +1,30 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 32-bit OS/2 mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10_PATH%\eddat
+SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h
+SET WATCOM=%WC10_PATH%
+SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=1
+SET USE_OS2GUI=1
+SET USE_SNAP=
+SET WC_LIBBASE=WC10A
+SET EDPATH=%WC10_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.0a 32-bit OS/2 GUI compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat b/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat
new file mode 100755
index 0000000..28f857c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat
@@ -0,0 +1,33 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10A_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE
+SET WATCOM=%WC10A_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_WIN386=
+SET WIN32_GUI=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=1
+SET WC_LIBBASE=WC10A
+PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.0a Snap compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat
new file mode 100755
index 0000000..a2b3219
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat
@@ -0,0 +1,45 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode with Phar Lap TNT
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10A_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT;%TNT_PATH%\INCLUDE
+SET WATCOM=%WC10A_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=1
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET WC_LIBBASE=WC10A
+PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+REM If you set the following to a 1, a TNT DosStyle app will be created.
+REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
+REM run under real DOS when using our libraries, since we require access
+REM to functions that the Win32 API does not support (such as direct access
+REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
+REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
+REM work too well).
+REM
+REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
+REM and hence will never be able to run under Win95 or WinNT, only DOS.
+
+SET DOSSTYLE=1
+
+echo Watcom C/C++ 10.0a 32-bit DOS compilation environment set up (TNT).
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat
new file mode 100755
index 0000000..94011cc
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat
@@ -0,0 +1,31 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 16 bit Windows mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC10A;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC10A;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10A_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\WIN;
+SET WATCOM=%WC10A_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK
+SET USE_WIN16=1
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET WC_LIBBASE=WC10A
+SET EDPATH=%WC10A_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.0a 16-bit Windows compilation environment set up.
+
diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat
new file mode 100755
index 0000000..1e14dbc
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat
@@ -0,0 +1,33 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC10A_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT;
+SET WATCOM=%WC10A_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_WIN386=
+SET WIN32_GUI=1
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET WC_LIBBASE=WC10A
+PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 10.0a Win32 GUI compilation environment set up
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat
new file mode 100755
index 0000000..e753129
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat
@@ -0,0 +1,40 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\EDDAT
+SET C_INCLUDE=%WC11_PATH%\H;%WC11_PATH%\H\NT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_WIN386=
+SET WIN32_GUI=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC11
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto done
+call win32sdk.bat
+
+:done
+echo Watcom C/C++ 11.0 Win32 console compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat
new file mode 100755
index 0000000..4338ada
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat
@@ -0,0 +1,30 @@
+@echo off
+REM SETup for compiling with Watcom C/C++ 11.0 in 16 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC11;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC11;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\WIN;
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC11
+SET EDPATH=%WC11_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 11.0 16-bit DOS compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat
new file mode 100755
index 0000000..e5a54d4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat
@@ -0,0 +1,33 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode (DOS4GW)
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC11
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 11.0 32-bit DOS compilation environment set up (DOS4GW).
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat
new file mode 100755
index 0000000..d46754a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat
@@ -0,0 +1,31 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 16-bit OS/2 mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\lib\release\os216\wc11;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\lib\debug\os216\wc11;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\eddat
+SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=1
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=wc11
+SET EDPATH=%WC11_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 11.0 16-bit OS/2 compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat
new file mode 100755
index 0000000..37f5dc7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat
@@ -0,0 +1,31 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 32-bit OS/2 mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\lib\release\os232\wc11;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\lib\debug\os232\wc11;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\eddat
+SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=1
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=wc11
+SET EDPATH=%WC11_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 11.0 32-bit OS/2 console compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat
new file mode 100755
index 0000000..348cbbd
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat
@@ -0,0 +1,31 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 32-bit OS/2 mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\lib\release\os232\wc11;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\lib\debug\os232\wc11;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\eddat
+SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=1
+SET USE_OS2GUI=1
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=wc11
+SET EDPATH=%WC11_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 11.0 32-bit OS/2 GUI compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat
new file mode 100755
index 0000000..1fd60fe
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode (QNX 4)
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\QNX4\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\QNX;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\QNX4\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\QNX;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\QH;
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=1
+SET WC_LIBBASE=WC11
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 11.0 32-bit QNX compilation environment set up
+
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat
new file mode 100755
index 0000000..6d2ac57
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET WIN32_GUI=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=1
+SET USE_QNX4=
+SET WC_LIBBASE=WC11
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 11.0 Snap compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat
new file mode 100755
index 0000000..44dbf24
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat
@@ -0,0 +1,46 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode with Phar Lap TNT
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;%TNT_PATH%\LIB;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;%TNT_PATH%\LIB;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\NT;%TNT_PATH%\INCLUDE
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=1
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC11
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+REM If you set the following to a 1, a TNT DosStyle app will be created.
+REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only*
+REM run under real DOS when using our libraries, since we require access
+REM to functions that the Win32 API does not support (such as direct access
+REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps
+REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't
+REM work too well).
+REM
+REM If you are using the RealTime DOS extender, your apps *must* be NtStyle,
+REM and hence will never be able to run under Win95 or WinNT, only DOS.
+
+SET DOSSTYLE=1
+
+echo Watcom C/C++ 11.0 32-bit DOS compilation environment set up (TNT).
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat
new file mode 100755
index 0000000..e65c70e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat
@@ -0,0 +1,31 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 16 bit Windows mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC11;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC11;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\WIN;
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK
+SET USE_WIN16=1
+SET USE_WIN32=
+SET USE_WIN386=
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC11
+SET EDPATH=%WC11_PATH%\EDDAT
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 11.0 16-bit Windows compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat
new file mode 100755
index 0000000..764cdbd
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat
@@ -0,0 +1,40 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\EDDAT
+SET C_INCLUDE=%WC11_PATH%\H;%WC11_PATH%\H\NT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE%
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_WIN386=
+SET WIN32_GUI=1
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC11
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+REM: Enable Win32 SDK if desired (sdk on command line)
+if NOT .%1%==.sdk goto done
+call win32sdk.bat
+
+:done
+echo Watcom C/C++ 11.0 Win32 GUI compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat
new file mode 100755
index 0000000..c2569a3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat
@@ -0,0 +1,34 @@
+@echo off
+REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode
+
+if .%CHECKED%==.1 goto checked_build
+SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;.
+echo Release build enabled.
+goto setvars
+
+:checked_build
+SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;.
+echo Checked debug build enabled.
+goto setvars
+
+:setvars
+SET EDPATH=%WC11_PATH%\EDDAT
+SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\NT;
+SET WATCOM=%WC11_PATH%
+SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK
+SET USE_TNT=
+SET USE_X32=
+SET USE_X32VM=
+SET USE_WIN16=
+SET USE_WIN32=1
+SET USE_WIN386=
+SET WIN32_GUI=1
+SET USE_OS216=
+SET USE_OS232=
+SET USE_OS2GUI=
+SET USE_SNAP=
+SET USE_QNX4=
+SET WC_LIBBASE=WC11
+PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH%
+
+echo Watcom C/C++ 11.0 Win32 GUI compilation environment set up.
diff --git a/board/MAI/bios_emulator/scitech/bin/win32sdk.bat b/board/MAI/bios_emulator/scitech/bin/win32sdk.bat
new file mode 100755
index 0000000..3c7f017
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/bin/win32sdk.bat
@@ -0,0 +1,20 @@
+@echo off
+REM: Set up environment variables for Microsoft Platform SDK development
+REM: Note that we have hard coded this for Windows NT i386 development.
+
+SET MSTOOLS=%MSSDK%
+SET DXSDKROOT=%MSTOOLS%
+SET INETSDK=%MSTOOLS%
+SET BKOFFICE=%MSTOOLS%
+SET BASEMAKE=%BKOFFICE%\INCLUDE\BKOffice.Mak
+SET INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%MSTOOLS%\INCLUDE;%C_INCLUDE%
+if .%1%==.borland goto borland
+SET LIB=%MSTOOLS%\LIB;%LIB%
+goto notborland
+:borland
+SET LIB=%MSTOOLS%\LIB\BORLAND;%LIB%
+:notborland
+SET PATH=%MSTOOLS%\Bin\;%MSTOOLS%\Bin\WinNT;%PATH%
+SET CPU=i386
+
+echo Microsoft Platform SDK support enbabled.
diff --git a/board/MAI/bios_emulator/scitech/include/biosemu.h b/board/MAI/bios_emulator/scitech/include/biosemu.h
new file mode 100755
index 0000000..82c33a7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/biosemu.h
@@ -0,0 +1,154 @@
+/****************************************************************************
+*
+*                        BIOS emulator and interface
+*                      to Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for the real mode x86 BIOS emulator, which is
+*               used to warmboot any number of VGA compatible PCI/AGP
+*               controllers under any OS, on any processor family that
+*               supports PCI. We also allow the user application to call
+*               real mode BIOS functions and Int 10h functions (including
+*               the VESA BIOS).
+*
+****************************************************************************/
+
+#ifndef __BIOSEMU_H
+#define __BIOSEMU_H
+
+#include "x86emu.h"
+#include "pmapi.h"
+#include "pcilib.h"
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+#pragma pack(1)
+
+/****************************************************************************
+REMARKS:
+Data structure used to describe the details specific to a particular VGA
+controller. This information is used to allow the VGA controller to be
+swapped on the fly within the BIOS emulator.
+
+HEADER:
+biosemu.h
+
+MEMBERS:
+pciInfo         - PCI device information block for the controller
+BIOSImage       - Pointer to a read/write copy of the BIOS image
+BIOSImageLen    - Length of the BIOS image
+LowMem          - Copy of key low memory areas
+****************************************************************************/
+typedef struct {
+    PCIDeviceInfo   *pciInfo;
+    void            *BIOSImage;
+    ulong           BIOSImageLen;
+    uchar           LowMem[1536];
+    } BE_VGAInfo;
+
+/****************************************************************************
+REMARKS:
+Data structure used to describe the details for the BIOS emulator system
+environment as used by the X86 emulator library.
+
+HEADER:
+biosemu.h
+
+MEMBERS:
+vgaInfo         - VGA BIOS information structure
+biosmem_base    - Base of the BIOS image
+biosmem_limit   - Limit of the BIOS image
+busmem_base     - Base of the VGA bus memory
+****************************************************************************/
+typedef struct {
+    BE_VGAInfo      vgaInfo;
+    ulong           biosmem_base;
+    ulong           biosmem_limit;
+    ulong           busmem_base;
+    } BE_sysEnv;
+
+/****************************************************************************
+REMARKS:
+Structure defining all the BIOS Emulator API functions as exported from
+the Binary Portable DLL.
+{secret}
+****************************************************************************/
+typedef struct {
+    ulong   dwSize;
+    ibool   (PMAPIP BE_init)(u32 debugFlags,int memSize,BE_VGAInfo *info);
+    void    (PMAPIP BE_setVGA)(BE_VGAInfo *info);
+    void    (PMAPIP BE_getVGA)(BE_VGAInfo *info);
+    void *  (PMAPIP BE_mapRealPointer)(uint r_seg,uint r_off);
+    void *  (PMAPIP BE_getVESABuf)(uint *len,uint *rseg,uint *roff);
+    void    (PMAPIP BE_callRealMode)(uint seg,uint off,RMREGS *regs,RMSREGS *sregs);
+    int     (PMAPIP BE_int86)(int intno,RMREGS *in,RMREGS *out);
+    int     (PMAPIP BE_int86x)(int intno,RMREGS *in,RMREGS *out,RMSREGS *sregs);
+    void *  reserved1;
+    void    (PMAPIP BE_exit)(void);
+    } BE_exports;
+
+/****************************************************************************
+REMARKS:
+Function pointer type for the Binary Portable DLL initialisation entry point.
+{secret}
+****************************************************************************/
+typedef BE_exports * (PMAPIP BE_initLibrary_t)(PM_imports *PMImp);
+
+#pragma pack()
+
+/*---------------------------- Global variables ---------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {                        /* Use "C" linkage when in C++ mode */
+#endif
+
+/* {secret} Global BIOS emulator system environment */
+extern BE_sysEnv _BE_env;
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+/* BIOS emulator library entry points */
+
+ibool   PMAPI BE_init(u32 debugFlags,int memSize,BE_VGAInfo *info);
+void    PMAPI BE_setVGA(BE_VGAInfo *info);
+void    PMAPI BE_getVGA(BE_VGAInfo *info);
+void    PMAPI BE_setDebugFlags(u32 debugFlags);
+void *  PMAPI BE_mapRealPointer(uint r_seg,uint r_off);
+void *  PMAPI BE_getVESABuf(uint *len,uint *rseg,uint *roff);
+void    PMAPI BE_callRealMode(uint seg,uint off,RMREGS *regs,RMSREGS *sregs);
+int     PMAPI BE_int86(int intno,RMREGS *in,RMREGS *out);
+int     PMAPI BE_int86x(int intno,RMREGS *in,RMREGS *out,RMSREGS *sregs);
+void    PMAPI BE_exit(void);
+
+#ifdef  __cplusplus
+}                                   /* End of "C" linkage for C++       */
+#endif
+
+#endif /* __BIOSEMU_H */
diff --git a/board/MAI/bios_emulator/scitech/include/event.h b/board/MAI/bios_emulator/scitech/include/event.h
new file mode 100755
index 0000000..beeac87
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/event.h
@@ -0,0 +1,696 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Header file for the SciTech cross platform event library
+*
+****************************************************************************/
+
+#ifndef __EVENT_H
+#define __EVENT_H
+
+#include "scitech.h"
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+#pragma pack(1)
+
+/* 'C' calling conventions always */
+
+#define EVTAPI  _ASMAPI
+#define EVTAPIP _ASMAPIP
+
+/* Event message masks for keyDown events */
+
+#define EVT_ASCIIMASK   0x00FF      /* ASCII code of key pressed        */
+#define EVT_SCANMASK    0xFF00      /* Scan code of key pressed         */
+#define EVT_COUNTMASK   0x7FFF0000L /* Count for KEYREPEAT's            */
+
+/* Macros to extract values from the message fields */
+
+#define EVT_asciiCode(m)    ( (uchar) (m & EVT_ASCIIMASK) )
+#define EVT_scanCode(m)     ( (uchar) ( (m & EVT_SCANMASK) >> 8 ) )
+#define EVT_repeatCount(m)  ( (short) ( (m & EVT_COUNTMASK) >> 16 ) )
+
+/****************************************************************************
+REMARKS:
+Defines the set of ASCII codes reported by the event library functions
+in the message field. Use the EVT_asciiCode macro to extract the code
+from the event structure.
+
+HEADER:
+event.h
+****************************************************************************/
+typedef enum {
+    ASCII_ctrlA             = 0x01,
+    ASCII_ctrlB             = 0x02,
+    ASCII_ctrlC             = 0x03,
+    ASCII_ctrlD             = 0x04,
+    ASCII_ctrlE             = 0x05,
+    ASCII_ctrlF             = 0x06,
+    ASCII_ctrlG             = 0x07,
+    ASCII_backspace         = 0x08,
+    ASCII_ctrlH             = 0x08,
+    ASCII_tab               = 0x09,
+    ASCII_ctrlI             = 0x09,
+    ASCII_ctrlJ             = 0x0A,
+    ASCII_ctrlK             = 0x0B,
+    ASCII_ctrlL             = 0x0C,
+    ASCII_enter             = 0x0D,
+    ASCII_ctrlM             = 0x0D,
+    ASCII_ctrlN             = 0x0E,
+    ASCII_ctrlO             = 0x0F,
+    ASCII_ctrlP             = 0x10,
+    ASCII_ctrlQ             = 0x11,
+    ASCII_ctrlR             = 0x12,
+    ASCII_ctrlS             = 0x13,
+    ASCII_ctrlT             = 0x14,
+    ASCII_ctrlU             = 0x15,
+    ASCII_ctrlV             = 0x16,
+    ASCII_ctrlW             = 0x17,
+    ASCII_ctrlX             = 0x18,
+    ASCII_ctrlY             = 0x19,
+    ASCII_ctrlZ             = 0x1A,
+    ASCII_esc               = 0x1B,
+    ASCII_space             = 0x20,
+    ASCII_exclamation       = 0x21, /* ! */
+    ASCII_quote             = 0x22, /* " */
+    ASCII_pound             = 0x23, /* # */
+    ASCII_dollar            = 0x24, /* $ */
+    ASCII_percent           = 0x25, /* % */
+    ASCII_ampersand         = 0x26, /* & */
+    ASCII_apostrophe        = 0x27, /* ' */
+    ASCII_leftBrace         = 0x28, /* ( */
+    ASCII_rightBrace        = 0x29, /* ) */
+    ASCII_times             = 0x2A, /* * */
+    ASCII_plus              = 0x2B, /* + */
+    ASCII_comma             = 0x2C, /* , */
+    ASCII_minus             = 0x2D, /* - */
+    ASCII_period            = 0x2E, /* . */
+    ASCII_divide            = 0x2F, /* / */
+    ASCII_0                 = 0x30,
+    ASCII_1                 = 0x31,
+    ASCII_2                 = 0x32,
+    ASCII_3                 = 0x33,
+    ASCII_4                 = 0x34,
+    ASCII_5                 = 0x35,
+    ASCII_6                 = 0x36,
+    ASCII_7                 = 0x37,
+    ASCII_8                 = 0x38,
+    ASCII_9                 = 0x39,
+    ASCII_colon             = 0x3A, /* : */
+    ASCII_semicolon         = 0x3B, /* ; */
+    ASCII_lessThan          = 0x3C, /* < */
+    ASCII_equals            = 0x3D, /* = */
+    ASCII_greaterThan       = 0x3E, /* > */
+    ASCII_question          = 0x3F, /* ? */
+    ASCII_at                = 0x40, /* @ */
+    ASCII_A                 = 0x41,
+    ASCII_B                 = 0x42,
+    ASCII_C                 = 0x43,
+    ASCII_D                 = 0x44,
+    ASCII_E                 = 0x45,
+    ASCII_F                 = 0x46,
+    ASCII_G                 = 0x47,
+    ASCII_H                 = 0x48,
+    ASCII_I                 = 0x49,
+    ASCII_J                 = 0x4A,
+    ASCII_K                 = 0x4B,
+    ASCII_L                 = 0x4C,
+    ASCII_M                 = 0x4D,
+    ASCII_N                 = 0x4E,
+    ASCII_O                 = 0x4F,
+    ASCII_P                 = 0x50,
+    ASCII_Q                 = 0x51,
+    ASCII_R                 = 0x52,
+    ASCII_S                 = 0x53,
+    ASCII_T                 = 0x54,
+    ASCII_U                 = 0x55,
+    ASCII_V                 = 0x56,
+    ASCII_W                 = 0x57,
+    ASCII_X                 = 0x58,
+    ASCII_Y                 = 0x59,
+    ASCII_Z                 = 0x5A,
+    ASCII_leftSquareBrace   = 0x5B, /* [ */
+    ASCII_backSlash         = 0x5C, /* \ */
+    ASCII_rightSquareBrace  = 0x5D, /* ] */
+    ASCII_caret             = 0x5E, /* ^ */
+    ASCII_underscore        = 0x5F, /* _ */
+    ASCII_leftApostrophe    = 0x60, /* ` */
+    ASCII_a                 = 0x61,
+    ASCII_b                 = 0x62,
+    ASCII_c                 = 0x63,
+    ASCII_d                 = 0x64,
+    ASCII_e                 = 0x65,
+    ASCII_f                 = 0x66,
+    ASCII_g                 = 0x67,
+    ASCII_h                 = 0x68,
+    ASCII_i                 = 0x69,
+    ASCII_j                 = 0x6A,
+    ASCII_k                 = 0x6B,
+    ASCII_l                 = 0x6C,
+    ASCII_m                 = 0x6D,
+    ASCII_n                 = 0x6E,
+    ASCII_o                 = 0x6F,
+    ASCII_p                 = 0x70,
+    ASCII_q                 = 0x71,
+    ASCII_r                 = 0x72,
+    ASCII_s                 = 0x73,
+    ASCII_t                 = 0x74,
+    ASCII_u                 = 0x75,
+    ASCII_v                 = 0x76,
+    ASCII_w                 = 0x77,
+    ASCII_x                 = 0x78,
+    ASCII_y                 = 0x79,
+    ASCII_z                 = 0x7A,
+    ASCII_leftCurlyBrace    = 0x7B, /* { */
+    ASCII_verticalBar       = 0x7C, /* | */
+    ASCII_rightCurlyBrace   = 0x7D, /* } */
+    ASCII_tilde             = 0x7E  /* ~ */
+    } EVT_asciiCodesType;
+
+/****************************************************************************
+REMARKS:
+Defines the set of scan codes reported by the event library functions
+in the message field. Use the EVT_scanCode macro to extract the code
+from the event structure. Note that the scan codes reported will be the
+same across all keyboards (assuming the placement of keys on a 101 key US
+keyboard), but the translated ASCII values may be different depending on
+the country code pages in use.
+
+NOTE:   Scan codes in the event library are not really hardware scan codes,
+	but rather virtual scan codes as generated by a low level keyboard
+	interface driver. All virtual codes begin with scan code 0x60 and
+	range up from there.
+
+HEADER:
+event.h
+****************************************************************************/
+typedef enum {
+    KB_padEnter             = 0x60, /* Keypad keys */
+    KB_padMinus             = 0x4A,
+    KB_padPlus              = 0x4E,
+    KB_padTimes             = 0x37,
+    KB_padDivide            = 0x61,
+    KB_padLeft              = 0x62,
+    KB_padRight             = 0x63,
+    KB_padUp                = 0x64,
+    KB_padDown              = 0x65,
+    KB_padInsert            = 0x66,
+    KB_padDelete            = 0x67,
+    KB_padHome              = 0x68,
+    KB_padEnd               = 0x69,
+    KB_padPageUp            = 0x6A,
+    KB_padPageDown          = 0x6B,
+    KB_padCenter            = 0x4C,
+    KB_F1                   = 0x3B, /* Function keys */
+    KB_F2                   = 0x3C,
+    KB_F3                   = 0x3D,
+    KB_F4                   = 0x3E,
+    KB_F5                   = 0x3F,
+    KB_F6                   = 0x40,
+    KB_F7                   = 0x41,
+    KB_F8                   = 0x42,
+    KB_F9                   = 0x43,
+    KB_F10                  = 0x44,
+    KB_F11                  = 0x57,
+    KB_F12                  = 0x58,
+    KB_left                 = 0x4B, /* Cursor control keys */
+    KB_right                = 0x4D,
+    KB_up                   = 0x48,
+    KB_down                 = 0x50,
+    KB_insert               = 0x52,
+    KB_delete               = 0x53,
+    KB_home                 = 0x47,
+    KB_end                  = 0x4F,
+    KB_pageUp               = 0x49,
+    KB_pageDown             = 0x51,
+    KB_capsLock             = 0x3A,
+    KB_numLock              = 0x45,
+    KB_scrollLock           = 0x46,
+    KB_leftShift            = 0x2A,
+    KB_rightShift           = 0x36,
+    KB_leftCtrl             = 0x1D,
+    KB_rightCtrl            = 0x6C,
+    KB_leftAlt              = 0x38,
+    KB_rightAlt             = 0x6D,
+    KB_leftWindows          = 0x5B,
+    KB_rightWindows         = 0x5C,
+    KB_menu                 = 0x5D,
+    KB_sysReq               = 0x54,
+    KB_esc                  = 0x01, /* Normal keyboard keys */
+    KB_1                    = 0x02,
+    KB_2                    = 0x03,
+    KB_3                    = 0x04,
+    KB_4                    = 0x05,
+    KB_5                    = 0x06,
+    KB_6                    = 0x07,
+    KB_7                    = 0x08,
+    KB_8                    = 0x09,
+    KB_9                    = 0x0A,
+    KB_0                    = 0x0B,
+    KB_minus                = 0x0C,
+    KB_equals               = 0x0D,
+    KB_backSlash            = 0x2B,
+    KB_backspace            = 0x0E,
+    KB_tab                  = 0x0F,
+    KB_Q                    = 0x10,
+    KB_W                    = 0x11,
+    KB_E                    = 0x12,
+    KB_R                    = 0x13,
+    KB_T                    = 0x14,
+    KB_Y                    = 0x15,
+    KB_U                    = 0x16,
+    KB_I                    = 0x17,
+    KB_O                    = 0x18,
+    KB_P                    = 0x19,
+    KB_leftSquareBrace      = 0x1A,
+    KB_rightSquareBrace     = 0x1B,
+    KB_enter                = 0x1C,
+    KB_A                    = 0x1E,
+    KB_S                    = 0x1F,
+    KB_D                    = 0x20,
+    KB_F                    = 0x21,
+    KB_G                    = 0x22,
+    KB_H                    = 0x23,
+    KB_J                    = 0x24,
+    KB_K                    = 0x25,
+    KB_L                    = 0x26,
+    KB_semicolon            = 0x27,
+    KB_apostrophe           = 0x28,
+    KB_Z                    = 0x2C,
+    KB_X                    = 0x2D,
+    KB_C                    = 0x2E,
+    KB_V                    = 0x2F,
+    KB_B                    = 0x30,
+    KB_N                    = 0x31,
+    KB_M                    = 0x32,
+    KB_comma                = 0x33,
+    KB_period               = 0x34,
+    KB_divide               = 0x35,
+    KB_space                = 0x39,
+    KB_tilde                = 0x29
+    } EVT_scanCodesType;
+
+/****************************************************************************
+REMARKS:
+Defines the mask for the joystick axes that are present
+
+HEADER:
+event.h
+
+MEMBERS:
+EVT_JOY_AXIS_X1     - Joystick 1, X axis is present
+EVT_JOY_AXIS_Y1     - Joystick 1, Y axis is present
+EVT_JOY_AXIS_X2     - Joystick 2, X axis is present
+EVT_JOY_AXIS_Y2     - Joystick 2, Y axis is present
+EVT_JOY_AXIS_ALL    - Mask for all axes
+****************************************************************************/
+typedef enum {
+    EVT_JOY_AXIS_X1     = 0x00000001,
+    EVT_JOY_AXIS_Y1     = 0x00000002,
+    EVT_JOY_AXIS_X2     = 0x00000004,
+    EVT_JOY_AXIS_Y2     = 0x00000008,
+    EVT_JOY_AXIS_ALL    = 0x0000000F
+    } EVT_eventJoyAxisType;
+
+/****************************************************************************
+REMARKS:
+Defines the event message masks for joystick events
+
+HEADER:
+event.h
+
+MEMBERS:
+EVT_JOY1_BUTTONA    - Joystick 1, button A is down
+EVT_JOY1_BUTTONB    - Joystick 1, button B is down
+EVT_JOY2_BUTTONA    - Joystick 2, button A is down
+EVT_JOY2_BUTTONB    - Joystick 2, button B is down
+****************************************************************************/
+typedef enum {
+    EVT_JOY1_BUTTONA    = 0x00000001,
+    EVT_JOY1_BUTTONB    = 0x00000002,
+    EVT_JOY2_BUTTONA    = 0x00000004,
+    EVT_JOY2_BUTTONB    = 0x00000008
+    } EVT_eventJoyMaskType;
+
+/****************************************************************************
+REMARKS:
+Defines the event message masks for mouse events
+
+HEADER:
+event.h
+
+MEMBERS:
+EVT_LEFTBMASK   - Left button is held down
+EVT_RIGHTBMASK  - Right button is held down
+EVT_MIDDLEBMASK - Middle button is held down
+EVT_BOTHBMASK   - Both left and right held down together
+EVT_ALLBMASK    - All buttons pressed
+EVT_DBLCLICK    - Set if mouse down event was a double click
+****************************************************************************/
+typedef enum {
+    EVT_LEFTBMASK   = 0x00000001,
+    EVT_RIGHTBMASK  = 0x00000002,
+    EVT_MIDDLEBMASK = 0x00000004,
+    EVT_BOTHBMASK   = 0x00000007,
+    EVT_ALLBMASK    = 0x00000007,
+    EVT_DBLCLICK    = 0x00010000
+    } EVT_eventMouseMaskType;
+
+/****************************************************************************
+REMARKS:
+Defines the event modifier masks. These are the masks used to extract
+the modifier information from the modifiers field of the event_t structure.
+Note that the values in the modifiers field represent the values of these
+modifier keys at the time the event occurred, not the time you decided
+to process the event.
+
+HEADER:
+event.h
+
+MEMBERS:
+EVT_LEFTBUT     - Set if left mouse button was down
+EVT_RIGHTBUT    - Set if right mouse button was down
+EVT_MIDDLEBUT   - Set if the middle button was down
+EVT_RIGHTSHIFT  - Set if right shift was down
+EVT_LEFTSHIFT   - Set if left shift was down
+EVT_RIGHTCTRL   - Set if right ctrl key was down
+EVT_RIGHTALT    - Set if right alt key was down
+EVT_LEFTCTRL    - Set if left ctrl key was down
+EVT_LEFTALT     - Set if left alt key was down
+EVT_SHIFTKEY    - Mask for any shift key down
+EVT_CTRLSTATE   - Set if ctrl key was down
+EVT_ALTSTATE    - Set if alt key was down
+EVT_CAPSLOCK    - Caps lock is active
+EVT_NUMLOCK     - Num lock is active
+EVT_SCROLLLOCK  - Scroll lock is active
+****************************************************************************/
+typedef enum {
+    EVT_LEFTBUT     = 0x00000001,
+    EVT_RIGHTBUT    = 0x00000002,
+    EVT_MIDDLEBUT   = 0x00000004,
+    EVT_RIGHTSHIFT  = 0x00000008,
+    EVT_LEFTSHIFT   = 0x00000010,
+    EVT_RIGHTCTRL   = 0x00000020,
+    EVT_RIGHTALT    = 0x00000040,
+    EVT_LEFTCTRL    = 0x00000080,
+    EVT_LEFTALT     = 0x00000100,
+    EVT_SHIFTKEY    = 0x00000018,
+    EVT_CTRLSTATE   = 0x000000A0,
+    EVT_ALTSTATE    = 0x00000140,
+    EVT_SCROLLLOCK  = 0x00000200,
+    EVT_NUMLOCK     = 0x00000400,
+    EVT_CAPSLOCK    = 0x00000800
+    } EVT_eventModMaskType;
+
+/****************************************************************************
+REMARKS:
+Defines the event codes returned in the event_t structures what field. Note
+that these are defined as a set of mutually exlusive bit fields, so you
+can test for multiple event types using the combined event masks defined
+in the EVT_eventMaskType enumeration.
+
+HEADER:
+event.h
+
+MEMBERS:
+EVT_NULLEVT     - A null event
+EVT_KEYDOWN     - Key down event
+EVT_KEYREPEAT   - Key repeat event
+EVT_KEYUP       - Key up event
+EVT_MOUSEDOWN   - Mouse down event
+EVT_MOUSEAUTO   - Mouse down autorepeat event
+EVT_MOUSEUP     - Mouse up event
+EVT_MOUSEMOVE   - Mouse movement event
+EVT_JOYCLICK    - Joystick button state change event
+EVT_JOYMOVE     - Joystick movement event
+EVT_USEREVT     - First user event
+****************************************************************************/
+typedef enum {
+    EVT_NULLEVT     = 0x00000000,
+    EVT_KEYDOWN     = 0x00000001,
+    EVT_KEYREPEAT   = 0x00000002,
+    EVT_KEYUP       = 0x00000004,
+    EVT_MOUSEDOWN   = 0x00000008,
+    EVT_MOUSEAUTO   = 0x00000010,
+    EVT_MOUSEUP     = 0x00000020,
+    EVT_MOUSEMOVE   = 0x00000040,
+    EVT_JOYCLICK    = 0x00000080,
+    EVT_JOYMOVE     = 0x00000100,
+    EVT_USEREVT     = 0x00000200
+    } EVT_eventType;
+
+/****************************************************************************
+REMARKS:
+Defines the event code masks you can use to test for multiple types of
+events, since the event codes are mutually exlusive bit fields.
+
+HEADER:
+event.h
+
+MEMBERS:
+EVT_KEYEVT      - Mask for any key event
+EVT_MOUSEEVT    - Mask for any mouse event
+EVT_MOUSECLICK  - Mask for any mouse click event
+EVT_JOYEVT      - Mask for any joystick event
+EVT_EVERYEVT    - Mask for any event
+****************************************************************************/
+typedef enum {
+    EVT_KEYEVT      = (EVT_KEYDOWN | EVT_KEYREPEAT | EVT_KEYUP),
+    EVT_MOUSEEVT    = (EVT_MOUSEDOWN | EVT_MOUSEAUTO | EVT_MOUSEUP | EVT_MOUSEMOVE),
+    EVT_MOUSECLICK  = (EVT_MOUSEDOWN | EVT_MOUSEUP),
+    EVT_JOYEVT      = (EVT_JOYCLICK | EVT_JOYMOVE),
+    EVT_EVERYEVT    = 0x7FFFFFFF
+    } EVT_eventMaskType;
+
+/****************************************************************************
+REMARKS:
+Structure describing the information contained in an event extracted from
+the event queue.
+
+HEADER:
+event.h
+
+MEMBERS:
+which       - Window identifier for message for use by high level window manager
+	      code (i.e. MegaVision GUI or Windows API).
+what        - Type of event that occurred. Will be one of the values defined by
+	      the EVT_eventType enumeration.
+when        - Time that the event occurred in milliseconds since startup
+where_x     - X coordinate of the mouse cursor location at the time of the event
+	      (in screen coordinates). For joystick events this represents
+	      the position of the first joystick X axis.
+where_y     - Y coordinate of the mouse cursor location at the time of the event
+	      (in screen coordinates). For joystick events this represents
+	      the position of the first joystick Y axis.
+relative_x  - Relative movement of the mouse cursor in the X direction (in
+	      units of mickeys, or 1/200th of an inch). For joystick events
+	      this represents the position of the second joystick X axis.
+relative_y  - Relative movement of the mouse cursor in the Y direction (in
+	      units of mickeys, or 1/200th of an inch). For joystick events
+	      this represents the position of the second joystick Y axis.
+message     - Event specific message for the event. For use events this can be
+	      any user specific information. For keyboard events this contains
+	      the ASCII code in bits 0-7, the keyboard scan code in bits 8-15 and
+	      the character repeat count in bits 16-30. You can use the
+	      EVT_asciiCode, EVT_scanCode and EVT_repeatCount macros to extract
+	      this information from the message field. For mouse events this
+	      contains information about which button was pressed, and will be a
+	      combination of the flags defined by the EVT_eventMouseMaskType
+	      enumeration. For joystick events, this conatins information
+	      about which buttons were pressed, and will be a combination of
+	      the flags defined by the EVT_eventJoyMaskType enumeration.
+modifiers   - Contains additional information about the state of the keyboard
+	      shift modifiers (Ctrl, Alt and Shift keys) when the event
+	      occurred. For mouse events it will also contain the state of
+	      the mouse buttons. Will be a combination of the values defined
+	      by the EVT_eventModMaskType enumeration.
+next        - Internal use; do not use.
+prev        - Internal use; do not use.
+****************************************************************************/
+typedef struct {
+    ulong       which;
+    ulong       what;
+    ulong       when;
+    int         where_x;
+    int         where_y;
+    int         relative_x;
+    int         relative_y;
+    ulong       message;
+    ulong       modifiers;
+    int         next;
+    int         prev;
+    } event_t;
+
+/****************************************************************************
+REMARKS:
+Structure describing an entry in the code page table. A table of translation
+codes for scan codes to ASCII codes is provided in this table to be used
+by the keyboard event libraries. On some OS'es the keyboard translation is
+handled by the OS, but for DOS and embedded systems you must register a
+different code page translation table if you want to support keyboards
+other than the US English keyboard (the default).
+
+NOTE:   Entries in code page tables *must* be in ascending order for the
+	scan codes as we do a binary search on the tables for the ASCII
+	code equivalents.
+
+HEADER:
+event.h
+
+MEMBERS:
+scanCode    - Scan code to translate (really the virtual scan code).
+asciiCode   - ASCII code for this scan code.
+****************************************************************************/
+typedef struct {
+    uchar       scanCode;
+    uchar       asciiCode;
+    } codepage_entry_t;
+
+/****************************************************************************
+REMARKS:
+Structure describing a complete code page translation table. The table
+contains translation tables for normal keys, shifted keys and ctrl keys.
+The Ctrl key always has precedence over the shift table, and the shift
+table is used when the shift key is down or the CAPSLOCK key is down.
+
+HEADER:
+event.h
+
+MEMBERS:
+name            - Name of the code page table (ie: "US English")
+normal          - Code page for translating normal keys
+normalLen       - Length of normal translation table
+caps            - Code page for translating keys when CAPSLOCK is down
+capsLen         - Length of CAPSLOCK translation table
+shift           - Code page for shifted keys (ie: shift key is held down)
+shiftLen        - Length of shifted translation table
+shiftCaps       - Code page for shifted keys when CAPSLOCK is down
+shiftCapsLen    - Length of shifted CAPSLOCK translation table
+ctrl            - Code page for ctrl'ed keys (ie: ctrl key is held down)
+ctrlLen         - Length of ctrl'ed translation table
+numPad          - Code page for NUMLOCK'ed keypad keys
+numPadLen       - Length of NUMLOCK'ed translation table
+****************************************************************************/
+typedef struct {
+    char                name[20];
+    codepage_entry_t    *normal;
+    int                 normalLen;
+    codepage_entry_t    *caps;
+    int                 capsLen;
+    codepage_entry_t    *shift;
+    int                 shiftLen;
+    codepage_entry_t    *shiftCaps;
+    int                 shiftCapsLen;
+    codepage_entry_t    *ctrl;
+    int                 ctrlLen;
+    codepage_entry_t    *numPad;
+    int                 numPadLen;
+    } codepage_t;
+
+/* {secret} */
+typedef ibool (EVTAPIP _EVT_userEventFilter)(event_t *evt);
+/* {secret} */
+typedef void (EVTAPIP _EVT_mouseMoveHandler)(int x,int y);
+/* {secret} */
+typedef void (EVTAPIP _EVT_heartBeatCallback)(void *params);
+
+/* Macro to find the size of a static array */
+
+#define EVT_ARR_SIZE(a)         (sizeof(a)/sizeof((a)[0]))
+
+#pragma pack()
+
+/*--------------------------- Global variables ----------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {            /* Use "C" linkage when in C++ mode */
+#endif
+
+/* Standard code page tables */
+
+extern codepage_t _CP_US_English;
+
+/*------------------------- Function Prototypes ---------------------------*/
+
+/* Public API functions for user applications */
+
+ibool   EVTAPI EVT_getNext(event_t *evt,ulong mask);
+ibool   EVTAPI EVT_peekNext(event_t *evt,ulong mask);
+ibool   EVTAPI EVT_post(ulong which,ulong what,ulong message,ulong modifiers);
+void    EVTAPI EVT_flush(ulong mask);
+void    EVTAPI EVT_halt(event_t *evt,ulong mask);
+ibool   EVTAPI EVT_isKeyDown(uchar scanCode);
+void    EVTAPI EVT_setMousePos(int x,int y);
+void    EVTAPI EVT_getMousePos(int *x,int *y);
+
+/* Function to enable/disable updating of keyboard LED status indicators */
+
+void    EVTAPI EVT_allowLEDS(ibool enable);
+
+/* Function to install a custom keyboard code page. Default is US English */
+
+codepage_t *EVTAPI EVT_getCodePage(void);
+void    EVTAPI EVT_setCodePage(codepage_t *page);
+
+/* Functions for fine grained joystick calibration */
+
+void    EVTAPI EVT_pollJoystick(void);
+int     EVTAPI EVT_joyIsPresent(void);
+void    EVTAPI EVT_joySetUpperLeft(void);
+void    EVTAPI EVT_joySetLowerRight(void);
+void    EVTAPI EVT_joySetCenter(void);
+
+/* Install user supplied event filter callback */
+
+void    EVTAPI EVT_setUserEventFilter(_EVT_userEventFilter filter);
+
+/* Install user supplied event heartbeat callback function */
+
+void    EVTAPI EVT_setHeartBeatCallback(_EVT_heartBeatCallback callback,void *params);
+void    EVTAPI EVT_getHeartBeatCallback(_EVT_heartBeatCallback *callback,void **params);
+
+/* Internal functions to initialise and kill the event manager. MGL
+ * applications should never call these functions directly as the MGL
+ * libraries do it for you.
+ */
+
+/* {secret} */
+void    EVTAPI EVT_init(_EVT_mouseMoveHandler mouseMove);
+/* {secret} */
+void    EVTAPI EVT_setMouseRange(int xRes,int yRes);
+/* {secret} */
+void    EVTAPI EVT_suspend(void);
+/* {secret} */
+void    EVTAPI EVT_resume(void);
+/* {secret} */
+void    EVTAPI EVT_exit(void);
+
+#ifdef  __cplusplus
+}                       /* End of "C" linkage for C++   */
+#endif  /* __cplusplus */
+
+#endif  /* __EVENT_H */
diff --git a/board/MAI/bios_emulator/scitech/include/mtrr.h b/board/MAI/bios_emulator/scitech/include/mtrr.h
new file mode 100755
index 0000000..b29812c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/mtrr.h
@@ -0,0 +1,72 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Include file defining the external ring 0 helper functions
+*               needed by the MTRR module. These functions may be included
+*               directly for native ring 0 device drivers, or they may
+*               be calls down to a ring 0 helper device driver where
+*               appropriate (or the entire MTRR module may be located in
+*               the device driver if the device driver is 32-bit).
+*
+****************************************************************************/
+
+#ifndef __MTRR_H
+#define __MTRR_H
+
+#include "scitech.h"
+
+/*--------------------------- Function Prototypes -------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {            /* Use "C" linkage when in C++ mode */
+#endif
+
+/* Internal functions (requires ring 0 access or helper functions!) */
+
+void    MTRR_init(void);
+int     MTRR_enableWriteCombine(ulong base,ulong size,uint type);
+
+/* External assembler helper functions */
+
+ibool   _ASMAPI _MTRR_isRing0(void);
+ulong   _ASMAPI _MTRR_disableInt(void);
+void    _ASMAPI _MTRR_restoreInt(ulong flags);
+ulong   _ASMAPI _MTRR_saveCR4(void);
+void    _ASMAPI _MTRR_restoreCR4(ulong cr4Val);
+uchar   _ASMAPI _MTRR_getCx86(uchar reg);
+void    _ASMAPI _MTRR_setCx86(uchar reg,uchar data);
+#ifdef  __16BIT__
+void    _ASMAPI _MTRR_readMSR(ulong reg, ulong far *eax, ulong far *edx);
+#else
+void    _ASMAPI _MTRR_readMSR(ulong reg, ulong *eax, ulong *edx);
+#endif
+void    _ASMAPI _MTRR_writeMSR(ulong reg, ulong eax, ulong edx);
+
+#ifdef  __cplusplus
+}                       /* End of "C" linkage for C++   */
+#endif
+
+#endif  /* __MTRR_H */
diff --git a/board/MAI/bios_emulator/scitech/include/pcilib.h b/board/MAI/bios_emulator/scitech/include/pcilib.h
new file mode 100755
index 0000000..238f8ef
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/pcilib.h
@@ -0,0 +1,413 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Header file for interface routines to the PCI bus.
+*
+****************************************************************************/
+
+#ifndef __PCILIB_H
+#define __PCILIB_H
+
+#include "scitech.h"
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+#pragma pack(1)
+
+/* Defines for PCIDeviceInfo.HeaderType */
+
+typedef enum {
+    PCI_deviceType                  = 0x00,
+    PCI_bridgeType                  = 0x01,
+    PCI_cardBusBridgeType           = 0x02,
+    PCI_multiFunctionType           = 0x80
+    } PCIHeaderTypeFlags;
+
+/* Defines for PCIDeviceInfo.Command */
+
+typedef enum {
+    PCI_enableIOSpace               = 0x0001,
+    PCI_enableMemorySpace           = 0x0002,
+    PCI_enableBusMaster             = 0x0004,
+    PCI_enableSpecialCylces         = 0x0008,
+    PCI_enableWriteAndInvalidate    = 0x0010,
+    PCI_enableVGACompatiblePalette  = 0x0020,
+    PCI_enableParity                = 0x0040,
+    PCI_enableWaitCycle             = 0x0080,
+    PCI_enableSerr                  = 0x0100,
+    PCI_enableFastBackToBack        = 0x0200
+    } PCICommandFlags;
+
+/* Defines for PCIDeviceInfo.Status */
+
+typedef enum {
+    PCI_statusCapabilitiesList      = 0x0010,
+    PCI_status66MhzCapable          = 0x0020,
+    PCI_statusUDFSupported          = 0x0040,
+    PCI_statusFastBackToBack        = 0x0080,
+    PCI_statusDataParityDetected    = 0x0100,
+    PCI_statusDevSel                = 0x0600,
+    PCI_statusSignaledTargetAbort   = 0x0800,
+    PCI_statusRecievedTargetAbort   = 0x1000,
+    PCI_statusRecievedMasterAbort   = 0x2000,
+    PCI_statusSignaledSystemError   = 0x4000,
+    PCI_statusDetectedParityError   = 0x8000
+    } PCIStatusFlags;
+
+/* PCI capability IDs */
+
+typedef enum {
+    PCI_capsPowerManagement         = 0x01,
+    PCI_capsAGP                     = 0x02,
+    PCI_capsMSI                     = 0x05
+    } PCICapsType;
+
+/* PCI AGP rate definitions */
+
+typedef enum {
+    PCI_AGPRate1X                   = 0x1,
+    PCI_AGPRate2X                   = 0x2,
+    PCI_AGPRate4X                   = 0x4
+    } PCIAGPRateType;
+
+/* NOTE: We define all bitfield's as uint's, specifically so that the IBM
+ *       Visual Age C++ compiler does not complain. We need them to be
+ *       32-bits wide, and this is the width of an unsigned integer, but
+ *       we can't use a ulong to make this explicit or we get errors.
+ */
+
+/* Structure defining a PCI slot identifier */
+
+typedef union {
+    struct {
+	uint    Zero:2;
+	uint    Register:6;
+	uint    Function:3;
+	uint    Device:5;
+	uint    Bus:8;
+	uint    Reserved:7;
+	uint    Enable:1;
+	} p;
+    ulong   i;
+    } PCIslot;
+
+/* Structure defining the regular (type 0) PCI configuration register
+ * layout. We use this in a union below so we can describe all types of
+ * PCI configuration spaces with a single structure.
+ */
+
+typedef struct {
+    ulong   BaseAddress10;
+    ulong   BaseAddress14;
+    ulong   BaseAddress18;
+    ulong   BaseAddress1C;
+    ulong   BaseAddress20;
+    ulong   BaseAddress24;
+    ulong   CardbusCISPointer;
+    ushort  SubSystemVendorID;
+    ushort  SubSystemID;
+    ulong   ROMBaseAddress;
+    uchar   CapabilitiesPointer;
+    uchar   reserved1;
+    uchar   reserved2;
+    uchar   reserved3;
+    ulong   reserved4;
+    uchar   InterruptLine;
+    uchar   InterruptPin;
+    uchar   MinimumGrant;
+    uchar   MaximumLatency;
+
+    /* These are not in the actual config space, but we enumerate them */
+    ulong   BaseAddress10Len;
+    ulong   BaseAddress14Len;
+    ulong   BaseAddress18Len;
+    ulong   BaseAddress1CLen;
+    ulong   BaseAddress20Len;
+    ulong   BaseAddress24Len;
+    ulong   ROMBaseAddressLen;
+    } PCIType0Info;
+
+/* Structure defining PCI to PCI bridge (type 1) PCI configuration register
+ * layout. We use this in a union below so we can describe all types of
+ * PCI configuration spaces with a single structure.
+ */
+
+typedef struct {
+    ulong   BaseAddress10;
+    ulong   BaseAddress14;
+    uchar   PrimaryBusNumber;
+    uchar   SecondayBusNumber;
+    uchar   SubordinateBusNumber;
+    uchar   SecondaryLatencyTimer;
+    uchar   IOBase;
+    uchar   IOLimit;
+    ushort  SecondaryStatus;
+    ushort  MemoryBase;
+    ushort  MemoryLimit;
+    ushort  PrefetchableMemoryBase;
+    ushort  PrefetchableMemoryLimit;
+    ulong   PrefetchableBaseHi;
+    ulong   PrefetchableLimitHi;
+    ushort  IOBaseHi;
+    ushort  IOLimitHi;
+    uchar   CapabilitiesPointer;
+    uchar   reserved1;
+    uchar   reserved2;
+    uchar   reserved3;
+    ulong   ROMBaseAddress;
+    uchar   InterruptLine;
+    uchar   InterruptPin;
+    ushort  BridgeControl;
+    } PCIType1Info;
+
+/* PCI to CardBus bridge (type 2) configuration information */
+typedef struct {
+    ulong   SocketRegistersBaseAddress;
+    uchar   CapabilitiesPointer;
+    uchar   reserved1;
+    ushort  SecondaryStatus;
+    uchar   PrimaryBus;
+    uchar   SecondaryBus;
+    uchar   SubordinateBus;
+    uchar   SecondaryLatency;
+    struct  {
+	ulong   Base;
+	ulong   Limit;
+	} Range[4];
+    uchar   InterruptLine;
+    uchar   InterruptPin;
+    ushort  BridgeControl;
+    } PCIType2Info;
+
+/* Structure defining the PCI configuration space information for a
+ * single PCI device on the PCI bus. We enumerate all this information
+ * for all PCI devices on the bus.
+ */
+
+typedef struct {
+    ulong               dwSize;
+    PCIslot             slot;
+    ulong               mech1;
+    ushort              VendorID;
+    ushort              DeviceID;
+    ushort              Command;
+    ushort              Status;
+    uchar               RevID;
+    uchar               Interface;
+    uchar               SubClass;
+    uchar               BaseClass;
+    uchar               CacheLineSize;
+    uchar               LatencyTimer;
+    uchar               HeaderType;
+    uchar               BIST;
+    union {
+	PCIType0Info    type0;
+	PCIType1Info    type1;
+	PCIType2Info    type2;
+	} u;
+    } PCIDeviceInfo;
+
+/* PCI Capability header structure. All PCI capabilities have the
+ * following header.
+ *
+ * capsID is used to identify the type of the structure as define above.
+ *
+ * next is the offset in PCI configuration space (0x40-0xFC) of the
+ * next capability structure in the list, or 0x00 if there are no more
+ * entries.
+ */
+
+typedef struct {
+    uchar   capsID;
+    uchar   next;
+    } PCICapsHeader;
+
+/* Structure defining the PCI AGP status register contents */
+
+typedef struct {
+    uint    rate:3;
+    uint    rsvd1:1;
+    uint    fastWrite:1;
+    uint    fourGB:1;
+    uint    rsvd2:3;
+    uint    sideBandAddressing:1;
+    uint    rsvd3:14;
+    uint    requestQueueDepthMaximum:8;
+    } PCIAGPStatus;
+
+/* Structure defining the PCI AGP command register contents */
+
+typedef struct {
+    uint    rate:3;
+    uint    rsvd1:1;
+    uint    fastWriteEnable:1;
+    uint    fourGBEnable:1;
+    uint    rsvd2:2;
+    uint    AGPEnable:1;
+    uint    SBAEnable:1;
+    uint    rsvd3:14;
+    uint    requestQueueDepth:8;
+    } PCIAGPCommand;
+
+/* AGP Capability structure */
+
+typedef struct {
+    PCICapsHeader   h;
+    ushort          majMin;
+    PCIAGPStatus    AGPStatus;
+    PCIAGPCommand   AGPCommand;
+    } PCIAGPCapability;
+
+/* Structure for obtaining the PCI IRQ routing information */
+
+typedef struct {
+    uchar   bus;
+    uchar   device;
+    uchar   linkA;
+    ushort  mapA;
+    uchar   linkB;
+    ushort  mapB;
+    uchar   linkC;
+    ushort  mapC;
+    uchar   linkD;
+    ushort  mapD;
+    uchar   slot;
+    uchar   reserved;
+    } PCIRouteInfo;
+
+typedef struct {
+    ushort          BufferSize;
+    PCIRouteInfo    *DataBuffer;
+    } PCIRoutingOptionsBuffer;
+
+#define NUM_PCI_REG                 (sizeof(PCIDeviceInfo) / 4) - 10
+#define PCI_BRIDGE_CLASS            0x06
+#define PCI_HOST_BRIDGE_SUBCLASS    0x00
+#define PCI_EARLY_VGA_CLASS         0x00
+#define PCI_EARLY_VGA_SUBCLASS      0x01
+#define PCI_DISPLAY_CLASS           0x03
+#define PCI_DISPLAY_VGA_SUBCLASS    0x00
+#define PCI_DISPLAY_XGA_SUBCLASS    0x01
+#define PCI_DISPLAY_OTHER_SUBCLASS  0x80
+#define PCI_MM_CLASS                0x04
+#define PCI_AUDIO_SUBCLASS          0x01
+
+/* Macros to detect specific classes of devices */
+
+#define PCI_IS_3DLABS_NONVGA_CLASS(pci) \
+   (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_OTHER_SUBCLASS) \
+ && ((pci)->VendorID == 0x3D3D || (pci)->VendorID == 0x104C))
+
+#define PCI_IS_DISPLAY_CLASS(pci) \
+   (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_VGA_SUBCLASS) \
+ || ((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_XGA_SUBCLASS) \
+ || ((pci)->BaseClass == PCI_EARLY_VGA_CLASS && (pci)->SubClass == PCI_EARLY_VGA_SUBCLASS) \
+ || PCI_IS_3DLABS_NONVGA_CLASS(pci))
+
+/* Function codes to pass to PCI_accessReg */
+
+#define PCI_READ_BYTE               0
+#define PCI_READ_WORD               1
+#define PCI_READ_DWORD              2
+#define PCI_WRITE_BYTE              3
+#define PCI_WRITE_WORD              4
+#define PCI_WRITE_DWORD             5
+
+/* Macros to read/write PCI registers. These assume a global PCI array
+ * of device information.
+ */
+
+#define PCI_readPCIRegB(index,device)   \
+    PCI_accessReg(index,0,0,&PCI[DeviceIndex[device]])
+
+#define PCI_readPCIRegW(index,device)   \
+    PCI_accessReg(index,0,1,&PCI[DeviceIndex[device]])
+
+#define PCI_readPCIRegL(index,device)   \
+    PCI_accessReg(index,0,2,&PCI[DeviceIndex[device]])
+
+#define PCI_writePCIRegB(index,value,device)    \
+    PCI_accessReg(index,value,3,&PCI[DeviceIndex[device]])
+
+#define PCI_writePCIRegW(index,value,device)    \
+    PCI_accessReg(index,value,4,&PCI[DeviceIndex[device]])
+
+#define PCI_writePCIRegL(index,value,device)    \
+    PCI_accessReg(index,value,5,&PCI[DeviceIndex[device]])
+
+#pragma pack()
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {                        /* Use "C" linkage when in C++ mode */
+#endif
+
+/* Function to determine the number of PCI devices in the system */
+
+int     _ASMAPI PCI_getNumDevices(void);
+
+/* Function to enumerate all device on the PCI bus */
+
+int     _ASMAPI PCI_enumerate(PCIDeviceInfo info[]);
+
+/* Function to access PCI configuration registers */
+
+ulong   _ASMAPI PCI_accessReg(int index,ulong value,int func,PCIDeviceInfo *info);
+
+/* Function to get PCI IRQ routing options for a card */
+
+int     _ASMAPI PCI_getIRQRoutingOptions(int numDevices,PCIRouteInfo *buffer);
+
+/* Function to re-route the PCI IRQ setting for a device */
+
+ibool   _ASMAPI PCI_setHardwareIRQ(PCIDeviceInfo *info,uint intPin,uint IRQ);
+
+/* Function to generate a special cyle on the specified PCI bus */
+
+void    _ASMAPI PCI_generateSpecialCyle(uint bus,ulong specialCycleData);
+
+/* Function to determine the size of a PCI base address register */
+
+ulong   _ASMAPI PCI_findBARSize(int bar,PCIDeviceInfo *pci);
+
+/* Function to read a block of PCI configuration space registers */
+
+void    _ASMAPI PCI_readRegBlock(PCIDeviceInfo *info,int index,void *dst,int count);
+
+/* Function to write a block of PCI configuration space registers */
+
+void    _ASMAPI PCI_writeRegBlock(PCIDeviceInfo *info,int index,void *src,int count);
+
+/* Function to return the 32-bit PCI BIOS entry point */
+
+ulong   _ASMAPI PCIBIOS_getEntry(void);
+
+#ifdef  __cplusplus
+}                                   /* End of "C" linkage for C++       */
+#endif
+
+#endif  /* __PCILIB_H */
diff --git a/board/MAI/bios_emulator/scitech/include/pm_help.h b/board/MAI/bios_emulator/scitech/include/pm_help.h
new file mode 100755
index 0000000..536a2ba
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/pm_help.h
@@ -0,0 +1,166 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32, OS/2
+*
+* Description:  Include file for the SciTech Portability Manager 32-bit
+*               helper VxD for Windows 9x for and the 16-bit ring 0
+*               helper device driver for OS/2.
+*
+*               This file documents all the public services used by the
+*               SciTech Portability Manager library and SciTech Nucleus
+*               loader library.
+*
+****************************************************************************/
+
+#ifndef __PMHELP_H
+#define __PMHELP_H
+
+/* Include version information */
+
+#include "sdd/sddver.h"
+#define PMHELP_Major            SDD_RELEASE_MAJOR
+#define PMHELP_Minor            SDD_RELEASE_MINOR
+#define PMHELP_VERSION          ((PMHELP_Major << 8) | PMHELP_Minor)
+
+#ifdef  __OS2__
+
+/****************************************************************************
+* Public OS/2 Support functions
+****************************************************************************/
+
+#include "scitech.h"
+#include "nucleus/graphics.h"
+
+/* Name of device driver */
+
+#define PMHELP_NAME                 (PSZ)"sddhelp$"
+
+/* Main IOCTL function to talk to device driver */
+
+#define PMHELP_IOCTL                0x0080
+
+/* Macro definition for defining IOCTL function control codes for the SDDHELP
+ * device driver for OS/2. Similar to that used for the DOS/Win32 version.
+ */
+
+#define PMHELP_CTL_CODE(name,value) \
+    PMHELP_##name = value
+
+typedef enum {
+    /* Version function used by all drivers */
+    PMHELP_CTL_CODE(GETVER                      ,0x0001),
+    PMHELP_CTL_CODE(MAPPHYS                     ,0x0002),
+    PMHELP_CTL_CODE(ALLOCLOCKED                 ,0x0003),
+    PMHELP_CTL_CODE(FREELOCKED                  ,0x0004),
+    PMHELP_CTL_CODE(GETGDT32                    ,0x0005),
+    PMHELP_CTL_CODE(MALLOCSHARED                ,0x0007),
+    PMHELP_CTL_CODE(FREESHARED                  ,0x0008),
+    PMHELP_CTL_CODE(MAPTOPROCESS                ,0x0009),
+    PMHELP_CTL_CODE(FREEPHYS                    ,0x000A),
+    PMHELP_CTL_CODE(FLUSHTLB                    ,0x000B),
+    PMHELP_CTL_CODE(SAVECR4                     ,0x000C),
+    PMHELP_CTL_CODE(RESTORECR4                  ,0x000D),
+    PMHELP_CTL_CODE(READMSR                     ,0x000E),
+    PMHELP_CTL_CODE(WRITEMSR                    ,0x000F),
+    PMHELP_CTL_CODE(GETPHYSICALADDR             ,0x0010),
+    PMHELP_CTL_CODE(GETPHYSICALADDRRANGE        ,0x0011),
+    PMHELP_CTL_CODE(LOCKPAGES                   ,0x0012),
+    PMHELP_CTL_CODE(UNLOCKPAGES                 ,0x0013),
+    PMHELP_CTL_CODE(GETSHAREDEXP                ,0x0042),
+    PMHELP_CTL_CODE(SETSHAREDEXP                ,0x0043),
+    PMHELP_CTL_CODE(GETSTACKSWITCHRTN           ,0x0044),
+    PMHELP_CTL_CODE(GETBUILDNO                  ,0x0050),
+    } PMHELP_ctlCodes;
+
+#else
+
+/****************************************************************************
+* Public DOS/Windows Support functions
+****************************************************************************/
+
+#ifdef  DEVICE_MAIN
+#include <vtoolsc.h>
+#define PMHELP_Init_Order   (VDD_INIT_ORDER-1)
+#define RETURN_LONGS(n)     *p->dioc_bytesret = (n) * sizeof(ulong)
+#endif  /* DEVICE_MAIN */
+#include "scitech.h"
+#include "nucleus/graphics.h"
+
+/* We connect to the SDDHELP.VXD module if it is staticly loaded (as part
+ * of SciTech Display Doctor), otherwise we dynamically load the PMHELP.VXD
+ * public helper VxD.
+ */
+
+#define PMHELP_DeviceID         0x0000
+#define SDDHELP_DeviceID        0x3DF8
+#define VXDLDR_DeviceID         0x0027
+#define SDDHELP_MODULE          "SDDHELP"
+#define SDDHELP_NAME            "SDDHELP.VXD"
+#define PMHELP_MODULE           "PMHELP"
+#define PMHELP_NAME             "PMHELP.VXD"
+#define PMHELP_DDBNAME          "pmhelp  "
+#define SDDHELP_MODULE_PATH     "\\\\.\\" SDDHELP_MODULE
+#define PMHELP_MODULE_PATH      "\\\\.\\" PMHELP_MODULE
+#define PMHELP_VXD_PATH         "\\\\.\\" PMHELP_NAME
+
+/* Macro definition for defining IOCTL function control codes for the PMHELP
+ * device drivers for Windows 9x and NT. This macro is basically derived from
+ * the CTL_CODE macro in the Windows 2000 DDK, but we hard code it here to
+ * avoid having to #include any of the Windows 2000 DDK header files. We also
+ * define both a 16-bit and 32-bit version of the control code within the same
+ * macro to simplify future additions.
+ *
+ * Essentially the Win32 macro would normally expand to the following:
+ *
+ *  CTL_CODE(FILE_DEVICE_VIDEO,0x800+value,METHOD_BUFFERED,FILE_ANY_ACCESS)
+ */
+
+#define PMHELP_CTL_CODE(name,value)                                             \
+    PMHELP_##name = value,                                                      \
+    PMHELP_##name##32 = ((0x23 << 16) | (0 << 14) | ((0x800+value) << 2) | (0))
+
+typedef enum {
+    /* Include all the control codes. We keep them in a separate header
+     * file so we can include them in multiple places to make this
+     * more versatile.
+     */
+    #include "pm_wctl.h"
+    } PMHELP_ctlCodes;
+
+/* For real mode VxD calls, we put the function number into the high
+ * order word of EAX, and a value of 0x4FFF in AX. This allows our
+ * VxD handler which is set up to handle Int 10's to recognise a native
+ * PMHELP API call from a real mode DOS program.
+ */
+
+#ifdef  REALMODE
+#define API_NUM(num)    (((ulong)(num) << 16) | 0x4FFF)
+#else
+#define API_NUM(num)    (num)
+#endif
+
+#endif  /* !__OS2__ */
+
+#endif  /* __PMHELP_H */
diff --git a/board/MAI/bios_emulator/scitech/include/pm_wctl.h b/board/MAI/bios_emulator/scitech/include/pm_wctl.h
new file mode 100755
index 0000000..20aa15e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/pm_wctl.h
@@ -0,0 +1,75 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32, OS/2
+*
+* Description:  Header file to define all the control codes for the DOS
+*               and Win32 device driver API's for calling from ring 3
+*               into the ring 0 device drivers.
+*
+****************************************************************************/
+
+/* Version function used by all drivers */
+PMHELP_CTL_CODE(GETVER                      ,0x0000),
+
+/* Functions used by obsolete 16-bit DOS TSR */
+PMHELP_CTL_CODE(RDREGB                      ,0x0003),
+PMHELP_CTL_CODE(WRREGB                      ,0x0004),
+PMHELP_CTL_CODE(RDREGW                      ,0x0005),
+PMHELP_CTL_CODE(WRREGW                      ,0x0006),
+PMHELP_CTL_CODE(RDREGL                      ,0x0008),
+PMHELP_CTL_CODE(WRREGL                      ,0x0009),
+
+/* Functions used by obsolete WinDirect */
+PMHELP_CTL_CODE(MAPPHYS                     ,0x000F),
+PMHELP_CTL_CODE(GETVESABUF                  ,0x0013),
+
+/* Functions used by PM library */
+PMHELP_CTL_CODE(DPMIINT86                   ,0x0014),
+PMHELP_CTL_CODE(INT86                       ,0x0015),
+PMHELP_CTL_CODE(INT86X                      ,0x0016),
+PMHELP_CTL_CODE(CALLREALMODE                ,0x0017),
+PMHELP_CTL_CODE(ALLOCLOCKED                 ,0x0018),
+PMHELP_CTL_CODE(FREELOCKED                  ,0x0019),
+PMHELP_CTL_CODE(ENABLELFBCOMB               ,0x001A),
+PMHELP_CTL_CODE(GETPHYSICALADDR             ,0x001B),
+PMHELP_CTL_CODE(MALLOCSHARED                ,0x001D),
+PMHELP_CTL_CODE(FREESHARED                  ,0x001F),
+PMHELP_CTL_CODE(LOCKDATAPAGES               ,0x0020),
+PMHELP_CTL_CODE(UNLOCKDATAPAGES             ,0x0021),
+PMHELP_CTL_CODE(LOCKCODEPAGES               ,0x0022),
+PMHELP_CTL_CODE(UNLOCKCODEPAGES             ,0x0023),
+PMHELP_CTL_CODE(GETCALLGATE                 ,0x0024),
+PMHELP_CTL_CODE(SETCNTPATH                  ,0x0025),
+PMHELP_CTL_CODE(GETPDB                      ,0x0026),
+PMHELP_CTL_CODE(FLUSHTLB                    ,0x0027),
+PMHELP_CTL_CODE(GETPHYSICALADDRRANGE        ,0x0028),
+PMHELP_CTL_CODE(ALLOCPAGE                   ,0x0029),
+PMHELP_CTL_CODE(FREEPAGE                    ,0x002A),
+PMHELP_CTL_CODE(ENABLERING3IOPL             ,0x002B),
+PMHELP_CTL_CODE(DISABLERING3IOPL            ,0x002C),
+PMHELP_CTL_CODE(GASETLOCALPATH              ,0x002D),
+PMHELP_CTL_CODE(GAGETEXPORTS                ,0x002E),
+PMHELP_CTL_CODE(GATHUNK                     ,0x002F),
+PMHELP_CTL_CODE(SETNUCLEUSPATH              ,0x0030),
diff --git a/board/MAI/bios_emulator/scitech/include/pmapi.h b/board/MAI/bios_emulator/scitech/include/pmapi.h
new file mode 100755
index 0000000..7ddace7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/pmapi.h
@@ -0,0 +1,1148 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Header file for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#ifndef __PMAPI_H
+#define __PMAPI_H
+
+#include "scitech.h"
+#include "pcilib.h"
+#include "ztimerc.h"
+#if !defined(__WIN32_VXD__) && !defined(__OS2_VDD__) && !defined(__NT_DRIVER__)
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+/*--------------------------- Macros and Typedefs -------------------------*/
+
+/* You will need to define one of the following before you compile this
+ * library for it to work correctly with the DOS extender that you are
+ * using when compiling for extended DOS:
+ *
+ *      TNT         - Phar Lap TNT DOS Extender
+ *      DOS4GW      - Rational DOS/4GW, DOS/4GW Pro, Causeway and PMODE/W
+ *      DJGPP       - DJGPP port of GNU C++
+ *
+ * If none is specified, we will automatically determine which operating
+ * system is being targetted and the following will be defined (provided by
+ * scitech.h header file):
+ *
+ *      __MSDOS16__     - Default for 16 bit MSDOS mode
+ *      __MSDOS32__     - Default for 32 bit MSDOS
+ *      __WINDOWS16__   - Default for 16 bit Windows
+ *      __WINDOWS32__   - Default for 32 bit Windows
+ *
+ * One of the following will be defined automatically for you to select
+ * which memory model is in effect:
+ *
+ *      REALMODE    - 16 bit real mode (large memory model)
+ *      PM286       - 16 protected mode (large memory model)
+ *      PM386       - 32 protected mode (flat memory model)
+ */
+
+#if defined(__UNIX__) && !defined(_MAX_PATH)
+#define _MAX_PATH 256
+#endif
+
+#if defined(TNT) || defined(DOSX) || defined(X32VM) || defined(DPMI32)      \
+    || defined(DOS4GW) || defined(DJGPP) || defined(__WINDOWS32__)          \
+    || defined(__MSDOS32__) || defined(__UNIX__) || defined(__WIN32_VXD__) \
+    || defined(__32BIT__) || defined(__SMX32__) || defined(__RTTARGET__)
+#define PM386
+#elif defined(DPMI16) || defined(__WINDOWS16__)
+#define PM286
+#else
+#define REALMODE
+#endif
+
+#pragma pack(1)
+
+/* Provide the typedefs for the PM_int386 functions, which issue native
+ * interrupts in real or protected mode and can pass extended registers
+ * around.
+ */
+
+struct _PMDWORDREGS {
+    ulong   eax,ebx,ecx,edx,esi,edi,cflag;
+    };
+
+struct _PMWORDREGS {
+    ushort  ax,ax_hi;
+    ushort  bx,bx_hi;
+    ushort  cx,cx_hi;
+    ushort  dx,dx_hi;
+    ushort  si,si_hi;
+    ushort  di,di_hi;
+    ushort  cflag,cflag_hi;
+    };
+
+struct _PMBYTEREGS {
+    uchar   al, ah; ushort ax_hi;
+    uchar   bl, bh; ushort bx_hi;
+    uchar   cl, ch; ushort cx_hi;
+    uchar   dl, dh; ushort dx_hi;
+    };
+
+typedef union {
+    struct  _PMDWORDREGS e;
+    struct  _PMWORDREGS  x;
+    struct  _PMBYTEREGS  h;
+    } PMREGS;
+
+typedef struct {
+    ushort  es;
+    ushort  cs;
+    ushort  ss;
+    ushort  ds;
+    ushort  fs;
+    ushort  gs;
+    } PMSREGS;
+
+/* Provide definitions for the real mode register structures passed to
+ * the PM_int86() and PM_int86x() routines. Note that we provide our own
+ * functions to do this for 16-bit code that calls the PM_int386 functions.
+ */
+
+typedef PMREGS  RMREGS;
+typedef PMSREGS RMSREGS;
+
+typedef struct {
+    long    edi;
+    long    esi;
+    long    ebp;
+    long    reserved;
+    long    ebx;
+    long    edx;
+    long    ecx;
+    long    eax;
+    short   flags;
+    short   es,ds,fs,gs,ip,cs,sp,ss;
+    } DPMI_regs;
+
+#ifdef  __MSDOS__
+/* Register structure passed to PM_VxDCall function */
+typedef struct {
+    ulong   eax;
+    ulong   ebx;
+    ulong   ecx;
+    ulong   edx;
+    ulong   esi;
+    ulong   edi;
+    ushort  ds,es;
+    } VXD_regs;
+#endif
+
+#define PM_MAX_DRIVE                3
+#define PM_MAX_PATH                 256
+#define PM_FILE_INVALID             (void*)0xFFFFFFFF
+
+/* Structure for generic directory traversal and management. Also the same
+ * values are passed to PM_setFileAttr to change the file attributes.
+ */
+
+typedef struct {
+    ulong   dwSize;
+    ulong   attrib;
+    ulong   sizeLo;
+    ulong   sizeHi;
+    char    name[PM_MAX_PATH];
+    } PM_findData;
+
+/* Macro to compute the byte offset of a field in a structure of type type */
+
+#define PM_FIELD_OFFSET(type,field) ((long)&(((type*)0)->field))
+
+/* Marcto to compute the address of the base of the structure given its type,
+ * and an address of a field within the structure.
+ */
+
+#define PM_CONTAINING_RECORD(address, type, field)      \
+    ((type*)(                                           \
+    (char*)(address) -                                  \
+    (char*)(&((type*)0)->field)))
+
+/* Flags stored in the PM_findData structure, and also values passed to
+ * PM_setFileAttr to change the file attributes.
+ */
+
+#define PM_FILE_NORMAL              0x00000000
+#define PM_FILE_READONLY            0x00000001
+#define PM_FILE_DIRECTORY           0x00000002
+#define PM_FILE_ARCHIVE             0x00000004
+#define PM_FILE_HIDDEN              0x00000008
+#define PM_FILE_SYSTEM              0x00000010
+
+/* Flags returned by the PM_splitpath function */
+
+#define PM_HAS_WILDCARDS 0x01
+#define PM_HAS_EXTENSION 0x02
+#define PM_HAS_FILENAME  0x04
+#define PM_HAS_DIRECTORY 0x08
+#define PM_HAS_DRIVE     0x10
+
+/* Structure passed to the PM_setFileTime functions */
+typedef struct {
+    short   sec;        /* Seconds */
+    short   min;        /* Minutes */
+    short   hour;       /* Hour (0--23) */
+    short   day;        /* Day of month (1--31) */
+    short   mon;        /* Month (0--11) */
+    short   year;       /* Year (calendar year minus 1900) */
+    } PM_time;
+
+/* Define a macro for creating physical base addresses from segment:offset */
+
+#define MK_PHYS(s,o)  (((ulong)(s) << 4) + (ulong)(o))
+
+/* Define the different types of modes supported. This is a global variable
+ * that can be used to determine the type at runtime which will contain
+ * one of these values.
+ */
+
+typedef enum {
+    PM_realMode,
+    PM_286,
+    PM_386
+    } PM_mode_enum;
+
+/* Define types passed to PM_enableWriteCombine */
+
+#define PM_MTRR_UNCACHABLE  0
+#define PM_MTRR_WRCOMB      1
+#define PM_MTRR_WRTHROUGH   4
+#define PM_MTRR_WRPROT      5
+#define PM_MTRR_WRBACK      6
+#define PM_MTRR_MAX         6
+
+/* Error codes returned by PM_enableWriteCombine */
+
+#define PM_MTRR_ERR_OK                  0
+#define PM_MTRR_NOT_SUPPORTED           -1
+#define PM_MTRR_ERR_PARAMS              -2
+#define PM_MTRR_ERR_NOT_4KB_ALIGNED     -3
+#define PM_MTRR_ERR_BELOW_1MB           -4
+#define PM_MTRR_ERR_NOT_ALIGNED         -5
+#define PM_MTRR_ERR_OVERLAP             -6
+#define PM_MTRR_ERR_TYPE_MISMATCH       -7
+#define PM_MTRR_ERR_NONE_FREE           -8
+#define PM_MTRR_ERR_NOWRCOMB            -9
+#define PM_MTRR_ERR_NO_OS_SUPPORT       -10
+
+/* Values passed to the PM_DMACProgram function */
+
+#define PM_DMA_READ_ONESHOT     0x44    /* One-shot DMA read        */
+#define PM_DMA_WRITE_ONESHOT    0x48    /* One-shot DMA write       */
+#define PM_DMA_READ_AUTOINIT    0x54    /* Auto-init DMA read       */
+#define PM_DMA_WRITE_AUTOINIT   0x58    /* Auto-init DMA write      */
+
+/* Flags passed to suspend application callback */
+
+#define PM_DEACTIVATE       1
+#define PM_REACTIVATE       2
+
+/* Return codes that the application can return from the suspend application
+ * callback registered with the PM library. See the MGL documentation for
+ * more details.
+ */
+#define PM_SUSPEND_APP      0
+#define PM_NO_SUSPEND_APP   1
+
+/****************************************************************************
+REMARKS:
+This enumeration defines the type values passed to the PM_agpReservePhysical
+function, to define how the physical memory mapping should be handled.
+
+The PM_agpUncached type indicates that the memory should be allocated as
+uncached memory.
+
+The PM_agpWriteCombine type indicates that write combining should be enabled
+for physical memory mapping. This is used for framebuffer write combing and
+speeds up direct framebuffer writes to the memory.
+
+The PM_agpIntelDCACHE type indicates that memory should come from the Intel
+i81x Display Cache (or DCACHE) memory pool. This flag is specific to the
+Intel i810 and i815 controllers, and should not be passed for any other
+controller type.
+
+HEADER:
+pmapi.h
+
+MEMBERS:
+PM_agpUncached      - Indicates that the memory should be uncached
+PM_agpWriteCombine  - Indicates that the memory should be write combined
+PM_agpIntelDCACHE   - Indicates that the memory should come from DCACHE pool
+****************************************************************************/
+typedef enum {
+    PM_agpUncached,
+    PM_agpWriteCombine,
+    PM_agpIntelDCACHE
+    } PM_agpMemoryType;
+
+/* Defines the size of an system memory page */
+
+#define PM_PAGE_SIZE        4096
+
+/* Type definition for a physical memory address */
+
+typedef unsigned long PM_physAddr;
+
+/* Define a bad physical address returned by map physical functions */
+
+#define PM_BAD_PHYS_ADDRESS 0xFFFFFFFF
+
+/* Type definition for the 12-byte lock handle for locking linear memory */
+
+typedef struct {
+    ulong   h[3];
+    } PM_lockHandle;
+
+/* 'C' calling conventions always       */
+
+#define PMAPI   _ASMAPI
+#define PMAPIP  _ASMAPIP
+
+/* Internal typedef to override DPMI_int86 handler */
+
+typedef ibool (PMAPIP DPMI_handler_t)(DPMI_regs *regs);
+void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler);
+
+/* Type definitions for a window handle for console modes */
+
+#if     defined(__DRIVER__) || defined(__WIN32_VXD__) || defined(__NT_DRIVER__)
+typedef void        *PM_HWND;   /* Pointer for portable drivers         */
+typedef void        *PM_MODULE; /* Module handle for portable drivers   */
+#elif   defined(__WINDOWS__)
+#ifdef  DECLARE_HANDLE
+typedef HWND        PM_HWND;    /* Real window handle                   */
+typedef HINSTANCE   PM_MODULE;  /* Win32 DLL handle                     */
+#else
+typedef void        *PM_HWND;   /* Place holder if windows.h not included */
+typedef void        *PM_MODULE; /* Place holder if windows.h not included */
+#endif
+#elif   defined(__USE_X11__)
+typedef struct {
+    Window      *window;
+    Display     *display;
+    } PM_HWND;                  /* X11 window handle */
+#elif   defined(__OS2__)
+typedef void    *PM_HWND;
+typedef void    *PM_MODULE;
+#elif   defined(__LINUX__)
+typedef int     PM_HWND;        /* Console id for fullscreen Linux */
+typedef void    *PM_MODULE;
+#elif   defined(__QNX__)
+typedef int     PM_HWND;        /* Console id for fullscreen QNX */
+typedef void    *PM_MODULE;
+#elif   defined(__RTTARGET__)
+typedef int     PM_HWND;        /* Placeholder for RTTarget-32 */
+typedef void    *PM_MODULE;
+#elif   defined(__REALDOS__)
+typedef int     PM_HWND;        /* Placeholder for fullscreen DOS */
+typedef void    *PM_MODULE;     /* Placeholder for fullscreen DOS */
+#elif   defined(__SMX32__)
+typedef int     PM_HWND;        /* Placeholder for fullscreen SMX */
+typedef void    *PM_MODULE;
+#elif   defined(__SNAP__)
+typedef void    *PM_HWND;
+typedef void    *PM_MODULE;
+#else
+#error  PM library not ported to this platform yet!
+#endif
+
+/* Type definition for code pointers */
+
+typedef void (*__codePtr)();
+
+/* Type definition for a C based interrupt handler */
+
+typedef void (PMAPIP PM_intHandler)(void);
+typedef ibool (PMAPIP PM_irqHandler)(void);
+
+/* Hardware IRQ handle used to save and restore the hardware IRQ */
+
+typedef void *PM_IRQHandle;
+
+/* Type definition for the fatal cleanup handler */
+
+typedef void (PMAPIP PM_fatalCleanupHandler)(void);
+
+/* Type defifinition for save state callback function */
+
+typedef int (PMAPIP PM_saveState_cb)(int flags);
+
+/* Type definintion for enum write combined callback function */
+
+typedef void (PMAPIP PM_enumWriteCombine_t)(ulong base,ulong length,uint type);
+
+/* Structure defining all the PM API functions as exported to
+ * the binary portable DLL's.
+ */
+
+typedef struct {
+    ulong   dwSize;
+    int     (PMAPIP PM_getModeType)(void);
+    void *  (PMAPIP PM_getBIOSPointer)(void);
+    void *  (PMAPIP PM_getA0000Pointer)(void);
+    void *  (PMAPIP PM_mapPhysicalAddr)(ulong base,ulong limit,ibool isCached);
+    void *  (PMAPIP PM_mallocShared)(long size);
+    void *  reserved1;
+    void    (PMAPIP PM_freeShared)(void *ptr);
+    void *  (PMAPIP PM_mapToProcess)(void *linear,ulong limit);
+    void *  (PMAPIP PM_mapRealPointer)(uint r_seg,uint r_off);
+    void *  (PMAPIP PM_allocRealSeg)(uint size,uint *r_seg,uint *r_off);
+    void    (PMAPIP PM_freeRealSeg)(void *mem);
+    void *  (PMAPIP PM_allocLockedMem)(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg);
+    void    (PMAPIP PM_freeLockedMem)(void *p,uint size,ibool contiguous);
+    void    (PMAPIP PM_callRealMode)(uint seg,uint off, RMREGS *regs,RMSREGS *sregs);
+    int     (PMAPIP PM_int86)(int intno, RMREGS *in, RMREGS *out);
+    int     (PMAPIP PM_int86x)(int intno, RMREGS *in, RMREGS *out,RMSREGS *sregs);
+    void    (PMAPIP DPMI_int86)(int intno, DPMI_regs *regs);
+    void    (PMAPIP PM_availableMemory)(ulong *physical,ulong *total);
+    void *  (PMAPIP PM_getVESABuf)(uint *len,uint *rseg,uint *roff);
+    long    (PMAPIP PM_getOSType)(void);
+    void    (PMAPIP PM_fatalError)(const char *msg);
+    void    (PMAPIP PM_setBankA)(int bank);
+    void    (PMAPIP PM_setBankAB)(int bank);
+    void    (PMAPIP PM_setCRTStart)(int x,int y,int waitVRT);
+    char *  (PMAPIP PM_getCurrentPath)(char *path,int maxLen);
+    const char * (PMAPIP PM_getVBEAFPath)(void);
+    const char * (PMAPIP PM_getNucleusPath)(void);
+    const char * (PMAPIP PM_getNucleusConfigPath)(void);
+    const char * (PMAPIP PM_getUniqueID)(void);
+    const char * (PMAPIP PM_getMachineName)(void);
+    ibool   (PMAPIP VF_available)(void);
+    void *  (PMAPIP VF_init)(ulong baseAddr,int bankSize,int codeLen,void *bankFunc);
+    void    (PMAPIP VF_exit)(void);
+    PM_HWND (PMAPIP PM_openConsole)(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen);
+    int     (PMAPIP PM_getConsoleStateSize)(void);
+    void    (PMAPIP PM_saveConsoleState)(void *stateBuf,PM_HWND hwndConsole);
+    void    (PMAPIP PM_restoreConsoleState)(const void *stateBuf,PM_HWND hwndConsole);
+    void    (PMAPIP PM_closeConsole)(PM_HWND hwndConsole);
+    void    (PMAPIP PM_setOSCursorLocation)(int x,int y);
+    void    (PMAPIP PM_setOSScreenWidth)(int width,int height);
+    int     (PMAPIP PM_enableWriteCombine)(ulong base,ulong length,uint type);
+    void    (PMAPIP PM_backslash)(char *filename);
+    int     (PMAPIP PM_lockDataPages)(void *p,uint len,PM_lockHandle *lockHandle);
+    int     (PMAPIP PM_unlockDataPages)(void *p,uint len,PM_lockHandle *lockHandle);
+    int     (PMAPIP PM_lockCodePages)(__codePtr p,uint len,PM_lockHandle *lockHandle);
+    int     (PMAPIP PM_unlockCodePages)(__codePtr p,uint len,PM_lockHandle *lockHandle);
+    ibool   (PMAPIP PM_setRealTimeClockHandler)(PM_intHandler ih,int frequency);
+    void    (PMAPIP PM_setRealTimeClockFrequency)(int frequency);
+    void    (PMAPIP PM_restoreRealTimeClockHandler)(void);
+    ibool   (PMAPIP PM_doBIOSPOST)(ushort axVal,ulong BIOSPhysAddr,void *BIOSPtr,ulong BIOSLen);
+    char    (PMAPIP PM_getBootDrive)(void);
+    void    (PMAPIP PM_freePhysicalAddr)(void *ptr,ulong limit);
+    uchar   (PMAPIP PM_inpb)(int port);
+    ushort  (PMAPIP PM_inpw)(int port);
+    ulong   (PMAPIP PM_inpd)(int port);
+    void    (PMAPIP PM_outpb)(int port,uchar val);
+    void    (PMAPIP PM_outpw)(int port,ushort val);
+    void    (PMAPIP PM_outpd)(int port,ulong val);
+    void *  reserved2;
+    void    (PMAPIP PM_setSuspendAppCallback)(PM_saveState_cb saveState);
+    ibool   (PMAPIP PM_haveBIOSAccess)(void);
+    int     (PMAPIP PM_kbhit)(void);
+    int     (PMAPIP PM_getch)(void);
+    ibool   (PMAPIP PM_findBPD)(const char *dllname,char *bpdpath);
+    ulong   (PMAPIP PM_getPhysicalAddr)(void *p);
+    void    (PMAPIP PM_sleep)(ulong milliseconds);
+    int     (PMAPIP PM_getCOMPort)(int port);
+    int     (PMAPIP PM_getLPTPort)(int port);
+    PM_MODULE (PMAPIP PM_loadLibrary)(const char *szDLLName);
+    void *  (PMAPIP PM_getProcAddress)(PM_MODULE hModule,const char *szProcName);
+    void    (PMAPIP PM_freeLibrary)(PM_MODULE hModule);
+    int     (PMAPIP PCI_enumerate)(PCIDeviceInfo info[]);
+    ulong   (PMAPIP PCI_accessReg)(int index,ulong value,int func,PCIDeviceInfo *info);
+    ibool   (PMAPIP PCI_setHardwareIRQ)(PCIDeviceInfo *info,uint intPin,uint IRQ);
+    void    (PMAPIP PCI_generateSpecialCyle)(uint bus,ulong specialCycleData);
+    void *  reserved3;
+    ulong   (PMAPIP PCIBIOS_getEntry)(void);
+    uint    (PMAPIP CPU_getProcessorType)(void);
+    ibool   (PMAPIP CPU_haveMMX)(void);
+    ibool   (PMAPIP CPU_have3DNow)(void);
+    ibool   (PMAPIP CPU_haveSSE)(void);
+    ibool   (PMAPIP CPU_haveRDTSC)(void);
+    ulong   (PMAPIP CPU_getProcessorSpeed)(ibool accurate);
+    void    (PMAPIP ZTimerInit)(void);
+    void    (PMAPIP LZTimerOn)(void);
+    ulong   (PMAPIP LZTimerLap)(void);
+    void    (PMAPIP LZTimerOff)(void);
+    ulong   (PMAPIP LZTimerCount)(void);
+    void    (PMAPIP LZTimerOnExt)(LZTimerObject *tm);
+    ulong   (PMAPIP LZTimerLapExt)(LZTimerObject *tm);
+    void    (PMAPIP LZTimerOffExt)(LZTimerObject *tm);
+    ulong   (PMAPIP LZTimerCountExt)(LZTimerObject *tm);
+    void    (PMAPIP ULZTimerOn)(void);
+    ulong   (PMAPIP ULZTimerLap)(void);
+    void    (PMAPIP ULZTimerOff)(void);
+    ulong   (PMAPIP ULZTimerCount)(void);
+    ulong   (PMAPIP ULZReadTime)(void);
+    ulong   (PMAPIP ULZElapsedTime)(ulong start,ulong finish);
+    void    (PMAPIP ULZTimerResolution)(ulong *resolution);
+    void *  (PMAPIP PM_findFirstFile)(const char *filename,PM_findData *findData);
+    ibool   (PMAPIP PM_findNextFile)(void *handle,PM_findData *findData);
+    void    (PMAPIP PM_findClose)(void *handle);
+    void    (PMAPIP PM_makepath)(char *p,const char *drive,const char *dir,const char *name,const char *ext);
+    int     (PMAPIP PM_splitpath)(const char *fn,char *drive,char *dir,char *name,char *ext);
+    ibool   (PMAPIP PM_driveValid)(char drive);
+    void    (PMAPIP PM_getdcwd)(int drive,char *dir,int len);
+    void    (PMAPIP PM_setFileAttr)(const char *filename,uint attrib);
+    ibool   (PMAPIP PM_mkdir)(const char *filename);
+    ibool   (PMAPIP PM_rmdir)(const char *filename);
+    uint    (PMAPIP PM_getFileAttr)(const char *filename);
+    ibool   (PMAPIP PM_getFileTime)(const char *filename,ibool gmtTime,PM_time *time);
+    ibool   (PMAPIP PM_setFileTime)(const char *filename,ibool gmtTime,PM_time *time);
+    char *  (PMAPIP CPU_getProcessorName)(void);
+    int     (PMAPIP PM_getVGAStateSize)(void);
+    void    (PMAPIP PM_saveVGAState)(void *stateBuf);
+    void    (PMAPIP PM_restoreVGAState)(const void *stateBuf);
+    void    (PMAPIP PM_vgaBlankDisplay)(void);
+    void    (PMAPIP PM_vgaUnblankDisplay)(void);
+    void    (PMAPIP PM_blockUntilTimeout)(ulong milliseconds);
+    void    (PMAPIP _PM_add64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result);
+    void    (PMAPIP _PM_sub64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result);
+    void    (PMAPIP _PM_mul64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result);
+    void    (PMAPIP _PM_div64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result);
+    void    (PMAPIP _PM_shr64)(u32 a_low,s32 a_high,s32 shift,__i64 *result);
+    void    (PMAPIP _PM_sar64)(u32 a_low,s32 a_high,s32 shift,__i64 *result);
+    void    (PMAPIP _PM_shl64)(u32 a_low,s32 a_high,s32 shift,__i64 *result);
+    void    (PMAPIP _PM_neg64)(u32 a_low,s32 a_high,__i64 *result);
+    ulong   (PMAPIP PCI_findBARSize)(int bar,PCIDeviceInfo *pci);
+    void    (PMAPIP PCI_readRegBlock)(PCIDeviceInfo *info,int index,void *dst,int count);
+    void    (PMAPIP PCI_writeRegBlock)(PCIDeviceInfo *info,int index,void *src,int count);
+    void    (PMAPIP PM_flushTLB)(void);
+    void    (PMAPIP PM_useLocalMalloc)(void * (*malloc)(size_t size),void * (*calloc)(size_t nelem,size_t size),void * (*realloc)(void *ptr,size_t size),void (*free)(void *p));
+    void *  (PMAPIP PM_malloc)(size_t size);
+    void *  (PMAPIP PM_calloc)(size_t nelem,size_t size);
+    void *  (PMAPIP PM_realloc)(void *ptr,size_t size);
+    void    (PMAPIP PM_free)(void *p);
+    ibool   (PMAPIP PM_getPhysicalAddrRange)(void *p,ulong length,ulong *physAddress);
+    void *  (PMAPIP PM_allocPage)(ibool locked);
+    void    (PMAPIP PM_freePage)(void *p);
+    ulong   (PMAPIP PM_agpInit)(void);
+    void    (PMAPIP PM_agpExit)(void);
+    ibool   (PMAPIP PM_agpReservePhysical)(ulong numPages,int type,void **physContext,PM_physAddr *physAddr);
+    ibool   (PMAPIP PM_agpReleasePhysical)(void *physContext);
+    ibool   (PMAPIP PM_agpCommitPhysical)(void *physContext,ulong numPages,ulong startOffset,PM_physAddr *physAddr);
+    ibool   (PMAPIP PM_agpFreePhysical)(void *physContext,ulong numPages,ulong startOffset);
+    int     (PMAPIP PCI_getNumDevices)(void);
+    void    (PMAPIP PM_setLocalBPDPath)(const char *path);
+    void *  (PMAPIP PM_loadDirectDraw)(int device);
+    void    (PMAPIP PM_unloadDirectDraw)(int device);
+    PM_HWND (PMAPIP PM_getDirectDrawWindow)(void);
+    void    (PMAPIP PM_doSuspendApp)(void);
+    } PM_imports;
+
+#pragma pack()
+
+/*---------------------------- Global variables ---------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {            /* Use "C" linkage when in C++ mode */
+#endif
+
+#ifdef  __WIN32_VXD__
+#define VESA_BUF_SIZE 1024
+extern uchar *_PM_rmBufAddr;
+#endif
+
+/* {secret} Pointer to global exports structure.
+ * Should not be used by application programs.
+ */
+extern PM_imports _VARAPI _PM_imports;
+
+/* {secret} */
+extern void * (*__PM_malloc)(size_t size);
+/* {secret} */
+extern void * (*__PM_calloc)(size_t nelem,size_t size);
+/* {secret} */
+extern void * (*__PM_realloc)(void *ptr,size_t size);
+/* {secret} */
+extern void (*__PM_free)(void *p);
+
+/*--------------------------- Function Prototypes -------------------------*/
+
+/* Routine to initialise the host side PM library. Note used from DLL's */
+
+void    PMAPI PM_init(void);
+
+/* Routine to return either PM_realMode, PM_286 or PM_386 */
+
+int     PMAPI PM_getModeType(void);
+
+/* Routine to return a selector to the BIOS data area at segment 0x40 */
+
+void *  PMAPI PM_getBIOSPointer(void);
+
+/* Routine to return a linear pointer to the VGA frame buffer memory */
+
+void *  PMAPI PM_getA0000Pointer(void);
+
+/* Routines to map/free physical memory into the current DS segment. In
+ * some environments (32-bit DOS is one), after the mapping has been
+ * allocated, it cannot be freed. Hence you should only allocate the
+ * mapping once and cache the value for use by other parts of your
+ * application. If the mapping cannot be createed, this function will
+ * return a NULL pointer.
+ *
+ * This routine will also work for memory addresses below 1Mb, but the
+ * mapped address cannot cross the 1Mb boundary.
+ */
+
+void *  PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached);
+void    PMAPI PM_freePhysicalAddr(void *ptr,ulong limit);
+
+/* Routine to determine the physical address of a linear address. It is
+ * up to the caller to ensure the entire address range for a linear
+ * block of memory is page aligned if that is required.
+ */
+
+ulong   PMAPI PM_getPhysicalAddr(void *p);
+ibool   PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress);
+
+/* Routines for memory allocation. By default these functions use the regular
+ * C runtime library malloc/free functions, but you can use the
+ * PM_useLocalMalloc function to override the default memory allocator with
+ * your own memory allocator. This will ensure that all memory allocation
+ * used by SciTech products will use your overridden memory allocator
+ * functions.
+ *
+ * Note that BPD files automatically map the C runtime library
+ * malloc/calloc/realloc/free calls from inside the BPD to the PM library
+ * versions by default.
+ */
+
+void    PMAPI PM_useLocalMalloc(void * (*malloc)(size_t size),void * (*calloc)(size_t nelem,size_t size),void * (*realloc)(void *ptr,size_t size),void (*free)(void *p));
+void *  PMAPI PM_malloc(size_t size);
+void *  PMAPI PM_calloc(size_t nelem,size_t size);
+void *  PMAPI PM_realloc(void *ptr,size_t size);
+void    PMAPI PM_free(void *p);
+
+/* Routine to allocate a memory block in the global shared region that
+ * is common to all tasks and accessible from ring 0 code.
+ */
+
+void *  PMAPI PM_mallocShared(long size);
+
+/* Routine to free the allocated shared memory block */
+
+void    PMAPI PM_freeShared(void *ptr);
+
+/* Attach a previously allocated linear mapping to a new process */
+
+void *  PMAPI PM_mapToProcess(void *linear,ulong limit);
+
+/* Macros to extract byte, word and long values from a char pointer */
+
+#define PM_getByte(p)       *((volatile uchar*)(p))
+#define PM_getWord(p)       *((volatile ushort*)(p))
+#define PM_getLong(p)       *((volatile ulong*)(p))
+#define PM_setByte(p,v)     PM_getByte(p) = (v)
+#define PM_setWord(p,v)     PM_getWord(p) = (v)
+#define PM_setLong(p,v)     PM_getLong(p) = (v)
+
+/* Routine for accessing a low 1Mb memory block. You dont need to free this
+ * pointer, but in 16 bit protected mode the selector allocated will be
+ * re-used the next time this routine is called.
+ */
+
+void *  PMAPI PM_mapRealPointer(uint r_seg,uint r_off);
+
+/* Routine to allocate a block of conventional memory below the 1Mb
+ * limit so that it can be accessed from real mode. Ensure that you free
+ * the segment when you are done with it.
+ *
+ * This routine returns a selector and offset to the segment that has been
+ * allocated, and also returns the real mode segment and offset which can
+ * be passed to real mode routines. Will return 0 if memory could not be
+ * allocated.
+ *
+ * Please note that with some DOS extenders, memory allocated with the
+ * following function cannot be freed, hence it will be allocated for the
+ * life of your program. Thus if you need to call a bunch of different
+ * real-mode routines in your program, allocate a single large buffer at
+ * program startup that can be re-used throughout the program execution.
+ */
+
+void *  PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off);
+void    PMAPI PM_freeRealSeg(void *mem);
+
+/* Routine to allocate a block of locked memory, and return both the
+ * linear and physical addresses of the memory. You should always
+ * allocate locked memory blocks in page sized chunks (ie: 4K on IA32).
+ * If the memory is not contiguous, you will need to use the
+ * PM_getPhysicalAddr function to get the physical address of linear
+ * pages within the memory block (the returned physical address will be
+ * for the first address in the memory block only).
+ */
+
+void *  PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg);
+void    PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous);
+
+/* Routine to allocate and free paged sized blocks of shared memory.
+ * Addressable from all processes, but not from a ring 0 context
+ * under OS/2. Note that under OS/2 PM_mapSharedPages must be called
+ * to map the memory blocks into the shared memory address space
+ * of each connecting process.
+ */
+
+void *  PMAPI PM_allocPage(ibool locked);
+void    PMAPI PM_freePage(void *p);
+#ifdef __OS2__
+void    PMAPI PM_mapSharedPages(void);
+#endif
+
+/* Routine to return true if we have access to the BIOS on the host OS */
+
+ibool   PMAPI PM_haveBIOSAccess(void);
+
+/* Routine to call a real mode assembly language procedure. Register
+ * values are passed in and out in the 'regs' and 'sregs' structures. We
+ * do not provide any method of copying data from the protected mode stack
+ * to the real mode stack, so if you need to pass data to real mode, you will
+ * need to write a real mode assembly language hook to recieve the values
+ * in registers, and to pass the data through a real mode block allocated
+ * with the PM_allocRealSeg() routine.
+ */
+
+void    PMAPI PM_callRealMode(uint seg,uint off, RMREGS *regs,RMSREGS *sregs);
+
+/* Routines to generate real mode interrupts using the same interface that
+ * is used by int86() and int86x() in realmode. This routine is need to
+ * call certain BIOS and DOS functions that are not supported by some
+ * DOS extenders. No translation is done on any of the register values,
+ * so they must be correctly set up and translated by the calling program.
+ *
+ * Normally the DOS extenders will allow you to use the normal int86()
+ * function directly and will pass on unhandled calls to real mode to be
+ * handled by the real mode handler. However calls to int86x() with real
+ * mode segment values to be loaded will cause a GPF if used with the
+ * standard int86x(), so you should use these routines if you know you
+ * want to call a real mode handler.
+ */
+
+int     PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out);
+int     PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,RMSREGS *sregs);
+
+/* Routine to generate a real mode interrupt. This is identical to the
+ * above function, but takes a DPMI_regs structure for the registers
+ * which has a lot more information. It is only available from 32-bit
+ * protected mode.
+ */
+
+void    PMAPI DPMI_int86(int intno, DPMI_regs *regs);
+
+/* Function to return the amount of available physical and total memory.
+ * The results of this function are *only* valid before you have made any
+ * calls to malloc() and free(). If you need to keep track of exactly how
+ * much memory is currently allocated, you need to call this function to
+ * get the total amount of memory available and then keep track of
+ * the available memory every time you call malloc() and free().
+ */
+
+void    PMAPI PM_availableMemory(ulong *physical,ulong *total);
+
+/* Return the address of a global VESA real mode transfer buffer for use
+ * by applications.
+ */
+
+void *  PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff);
+
+/* Handle fatal error conditions */
+
+void    PMAPI PM_fatalError(const char *msg);
+
+/* Function to set a cleanup error handler called when PM_fatalError
+ * is called. This allows us to the console back into a normal state
+ * if we get a failure from deep inside a BPD file. This function is
+ * not exported to BPD files, and is only used by code compiled for the
+ * OS.
+ */
+
+void    PMAPI PM_setFatalErrorCleanup(PM_fatalCleanupHandler cleanup);
+
+/* Return the OS type flag as defined in <drvlib/os/os.h> */
+
+long    PMAPI PM_getOSType(void);
+
+/* Functions to set a VBE bank via an Int 10h */
+
+void    PMAPI PM_setBankA(int bank);
+void    PMAPI PM_setBankAB(int bank);
+void    PMAPI PM_setCRTStart(int x,int y,int waitVRT);
+
+/* Return the current working directory */
+
+char *  PMAPI PM_getCurrentPath(char *path,int maxLen);
+
+/* Return paths to the VBE/AF and Nucleus directories */
+
+const char * PMAPI PM_getVBEAFPath(void);
+const char * PMAPI PM_getNucleusPath(void);
+const char * PMAPI PM_getNucleusConfigPath(void);
+
+/* Find the path to a binary portable DLL */
+
+void    PMAPI PM_setLocalBPDPath(const char *path);
+ibool   PMAPI PM_findBPD(const char *dllname,char *bpdpath);
+
+/* Returns the drive letter of the boot drive for DOS, OS/2 and Windows */
+
+char    PMAPI PM_getBootDrive(void);
+
+/* Return a network unique machine identifier as a string */
+
+const char * PMAPI PM_getUniqueID(void);
+
+/* Return the network machine name as a string */
+
+const char * PMAPI PM_getMachineName(void);
+
+/* Functions to install and remove the virtual linear framebuffer
+ * emulation code. For unsupported DOS extenders and when running under
+ * a DPMI host like Windows or OS/2, this function will return a NULL.
+ */
+
+ibool   PMAPI VF_available(void);
+void *  PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc);
+void    PMAPI VF_exit(void);
+
+/* Functions to wait for a keypress and read a key for command line
+ * environments such as DOS, Win32 console and Unix.
+ */
+
+int     PMAPI PM_kbhit(void);
+int     PMAPI PM_getch(void);
+
+/* Functions to create either a fullscreen or windowed console on the
+ * desktop, and to allow the resolution of fullscreen consoles to be
+ * changed on the fly without closing the console. For non-windowed
+ * environments (such as a Linux or OS/2 fullscreen console), these
+ * functions enable console graphics mode and restore console text mode.
+ *
+ * The suspend application callback is used to allow the application to
+ * save the state of the fullscreen console mode to allow temporary
+ * switching to another console or back to the regular GUI desktop. It
+ * is also called to restore the fullscreen graphics state after the
+ * fullscreen console regains the focus.
+ *
+ * The device parameter allows for the console to be opened on a different
+ * display controllers (0 is always the primary controller).
+ */
+
+PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen);
+int     PMAPI PM_getConsoleStateSize(void);
+void    PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole);
+void    PMAPI PM_setSuspendAppCallback(PM_saveState_cb saveState);
+void    PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole);
+void    PMAPI PM_closeConsole(PM_HWND hwndConsole);
+
+/* Functions to modify OS console information */
+
+void    PMAPI PM_setOSCursorLocation(int x,int y);
+void    PMAPI PM_setOSScreenWidth(int width,int height);
+
+/* Function to emable Intel PPro/PII write combining */
+
+int     PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type);
+int     PMAPI PM_enumWriteCombine(PM_enumWriteCombine_t callback);
+
+/* Function to add a path separator to the end of a filename (if not present) */
+
+void    PMAPI PM_backslash(char *filename);
+
+/* Routines to lock and unlock regions of memory under a virtual memory
+ * environment. These routines _must_ be used to lock all hardware
+ * and mouse interrupt handlers installed, _AND_ any global data that
+ * these handler manipulate, so that they will always be present in memory
+ * to handle the incoming interrupts.
+ *
+ * Note that it is important to call the correct routine depending on
+ * whether the area being locked is code or data, so that under 32 bit
+ * PM we will get the selector value correct.
+ */
+
+int     PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lockHandle);
+int     PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lockHandle);
+int     PMAPI PM_lockCodePages(__codePtr p,uint len,PM_lockHandle *lockHandle);
+int     PMAPI PM_unlockCodePages(__codePtr p,uint len,PM_lockHandle *lockHandle);
+
+/* Routines to install and remove Real Time Clock interrupt handlers. The
+ * frequency of the real time clock can be changed by calling
+ * PM_setRealTimeClockFrequeny, and the value can be any power of 2 value
+ * from 2Hz to 8192Hz.
+ *
+ * Note that you _must_ lock the memory containing the interrupt
+ * handlers with the PM_lockPages() function otherwise you may encounter
+ * problems in virtual memory environments.
+ *
+ * NOTE: User space versions of the PM library should fail these functions.
+ */
+
+ibool   PMAPI PM_setRealTimeClockHandler(PM_intHandler ih,int frequency);
+void    PMAPI PM_setRealTimeClockFrequency(int frequency);
+void    PMAPI PM_restoreRealTimeClockHandler(void);
+
+/* Routines to install and remove hardware interrupt handlers.
+ *
+ * Note that you _must_ lock the memory containing the interrupt
+ * handlers with the PM_lockPages() function otherwise you may encounter
+ * problems in virtual memory environments.
+ *
+ * NOTE: User space versions of the PM library should fail these functions.
+ */
+
+PM_IRQHandle PMAPI PM_setIRQHandler(int IRQ,PM_irqHandler ih);
+void    PMAPI PM_restoreIRQHandler(PM_IRQHandle irqHandle);
+
+/* Functions to program DMA using the legacy ISA DMA controller */
+
+void    PMAPI PM_DMACEnable(int channel);
+void    PMAPI PM_DMACDisable(int channel);
+void    PMAPI PM_DMACProgram(int channel,int mode,ulong bufferPhys,int count);
+ulong   PMAPI PM_DMACPosition(int channel);
+
+/* Function to post secondary graphics controllers using the BIOS */
+
+ibool   PMAPI PM_doBIOSPOST(ushort axVal,ulong BIOSPhysAddr,void *mappedBIOS,ulong BIOSLen);
+
+/* Function to init the AGP functions and return the AGP aperture size in MB */
+
+ulong   PMAPI PM_agpInit(void);
+void    PMAPI PM_agpExit(void);
+
+/* Functions to reserve and release physical AGP memory ranges */
+
+ibool   PMAPI PM_agpReservePhysical(ulong numPages,int type,void **physContext,PM_physAddr *physAddr);
+ibool   PMAPI PM_agpReleasePhysical(void *physContext);
+
+/* Functions to commit and free physical AGP memory ranges */
+
+ibool   PMAPI PM_agpCommitPhysical(void *physContext,ulong numPages,ulong startOffset,PM_physAddr *physAddr);
+ibool   PMAPI PM_agpFreePhysical(void *physContext,ulong numPages,ulong startOffset);
+
+/* Functions to do I/O port manipulation directly from C code. These
+ * functions are portable and will work on any processor architecture
+ * to access I/O space registers on PCI devices.
+ */
+
+uchar   PMAPI PM_inpb(int port);
+ushort  PMAPI PM_inpw(int port);
+ulong   PMAPI PM_inpd(int port);
+void    PMAPI PM_outpb(int port,uchar val);
+void    PMAPI PM_outpw(int port,ushort val);
+void    PMAPI PM_outpd(int port,ulong val);
+
+/* Functions to determine the I/O port locations for COM and LPT ports.
+ * The functions are zero based, so for COM1 or LPT1 pass in a value of 0,
+ * for COM2 or LPT2 pass in a value of 1 etc.
+ */
+
+int     PMAPI PM_getCOMPort(int port);
+int     PMAPI PM_getLPTPort(int port);
+
+/* Internal functions that need prototypes */
+
+void    PMAPI _PM_getRMvect(int intno, long *realisr);
+void    PMAPI _PM_setRMvect(int intno, long realisr);
+void    PMAPI _PM_freeMemoryMappings(void);
+
+/* Function to override the default debug log file location */
+
+void    PMAPI PM_setDebugLog(const char *logFilePath);
+
+/* Function to put the process to sleep for the specified milliseconds */
+
+void    PMAPI PM_sleep(ulong milliseconds);
+
+/* Function to block until 'milliseconds' have passed since last call */
+
+void    PMAPI PM_blockUntilTimeout(ulong milliseconds);
+
+/* Functions for directory traversal and management */
+
+void *  PMAPI PM_findFirstFile(const char *filename,PM_findData *findData);
+ibool   PMAPI PM_findNextFile(void *handle,PM_findData *findData);
+void    PMAPI PM_findClose(void *handle);
+void    PMAPI PM_makepath(char *p,const char *drive,const char *dir,const char *name,const char *ext);
+int     PMAPI PM_splitpath(const char *fn,char *drive,char *dir,char *name,char *ext);
+ibool   PMAPI PM_driveValid(char drive);
+void    PMAPI PM_getdcwd(int drive,char *dir,int len);
+uint    PMAPI PM_getFileAttr(const char *filename);
+void    PMAPI PM_setFileAttr(const char *filename,uint attrib);
+ibool   PMAPI PM_getFileTime(const char *filename,ibool gmTime,PM_time *time);
+ibool   PMAPI PM_setFileTime(const char *filename,ibool gmTime,PM_time *time);
+ibool   PMAPI PM_mkdir(const char *filename);
+ibool   PMAPI PM_rmdir(const char *filename);
+
+/* Functions to handle loading OS specific shared libraries */
+
+PM_MODULE PMAPI PM_loadLibrary(const char *szDLLName);
+void *  PMAPI PM_getProcAddress(PM_MODULE hModule,const char *szProcName);
+void    PMAPI PM_freeLibrary(PM_MODULE hModule);
+
+/* Functions and macros for 64-bit arithmetic */
+
+void    PMAPI _PM_add64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result);
+void    PMAPI _PM_sub64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result);
+void    PMAPI _PM_mul64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result);
+void    PMAPI _PM_div64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result);
+void    PMAPI _PM_shr64(u32 a_low,s32 a_high,s32 shift,__i64 *result);
+void    PMAPI _PM_sar64(u32 a_low,s32 a_high,s32 shift,__i64 *result);
+void    PMAPI _PM_shl64(u32 a_low,s32 a_high,s32 shift,__i64 *result);
+void    PMAPI _PM_neg64(u32 a_low,s32 a_high,__i64 *result);
+#ifdef __NATIVE_INT64__
+#define PM_add64(r,a,b)     (r) = (a) + (b)
+#define PM_add64_32(r,a,b)  (r) = (a) + (b)
+#define PM_sub64(r,a,b)     (r) = (a) - (b)
+#define PM_sub64_32(r,a,b)  (r) = (a) - (b)
+#define PM_mul64(r,a,b)     (r) = (a) * (b)
+#define PM_mul64_32(r,a,b)  (r) = (a) * (b)
+#define PM_div64(r,a,b)     (r) = (a) / (b)
+#define PM_div64_32(r,a,b)  (r) = (a) / (b)
+#define PM_shr64(r,a,s)     (r) = (a) >> (s)
+#define PM_sar64(r,a,s)     (r) = ((s64)(a)) >> (s)
+#define PM_shl64(r,a,s)     (r) = (u64)(a) << (s)
+#define PM_neg64(r,a,s)     (r) = -(a)
+#define PM_not64(r,a,s)     (r) = ~(a)
+#define PM_eq64(a,b)        (a) == (b)
+#define PM_gt64(a,b)        (a) > (b)
+#define PM_lt64(a,b)        (a) < (b)
+#define PM_geq64(a,b)       (a) >= (b)
+#define PM_leq64(a,b)       (a) <= (b)
+#define PM_64to32(a)        (u32)(a)
+#define PM_64tos32(a)       (s32)(a)
+#define PM_set64(a,b,c)     (a) = ((u64)(b) << 32) + (c)
+#define PM_set64_32(a,b)    (a) = (b)
+#else
+#define PM_add64(r,a,b)     _PM_add64((a).low,(a).high,(b).low,(b).high,&(r))
+#define PM_add64_32(r,a,b)  _PM_add64((a).low,(a).high,b,0,&(r))
+#define PM_sub64(r,a,b)     _PM_sub64((a).low,(a).high,(b).low,(b).high,&(r))
+#define PM_sub64_32(r,a,b)  _PM_sub64((a).low,(a).high,b,0,&(r))
+#define PM_mul64(r,a,b)     _PM_mul64((a).low,(a).high,(b).low,(b).high,&(r))
+#define PM_mul64_32(r,a,b)  _PM_mul64((a).low,(a).high,b,0,&(r))
+#define PM_div64(r,a,b)     _PM_div64((a).low,(a).high,(b).low,(b).high,&(r))
+#define PM_div64_32(r,a,b)  _PM_div64((a).low,(a).high,b,0,&(r))
+#define PM_shr64(r,a,s)     _PM_shr64((a).low,(a).high,s,&(r))
+#define PM_sar64(r,a,s)     _PM_sar64((a).low,(a).high,s,&(r))
+#define PM_shl64(r,a,s)     _PM_shl64((a).low,(a).high,s,&(r))
+#define PM_neg64(r,a,s)     _PM_neg64((a).low,(a).high,&(r))
+#define PM_not64(r,a,s)     (r).low = ~(a).low, (r).high = ~(a).high
+#define PM_eq64(a,b)        ((a).low == (b).low && (a).high == (b).high)
+#define PM_gt64(a,b)        (((a).high > (b).high) || ((a).high == (b).high && (a).low > (b).low))
+#define PM_lt64(a,b)        (((a).high < (b).high) || ((a).high == (b).high && (a).low < (b).low))
+#define PM_geq64(a,b)       (PM_eq64(a,b) || PM_gt64(a,b))
+#define PM_leq64(a,b)       (PM_eq64(a,b) || PM_lt64(a,b))
+#define PM_64to32(a)        (u32)(a.low)
+#define PM_64tos32(a)       ((a).high < 0) ? -(a).low : (a).low)
+#define PM_set64(a,b,c)     (a).high = (b), (a).low = (c)
+#define PM_set64_32(a,b)    (a).high = 0, (a).low = (b)
+#endif
+
+/* Function to enable IOPL access if required */
+
+int     PMAPI PM_setIOPL(int iopl);
+
+/* Function to flush the TLB and CPU caches */
+
+void    PMAPI PM_flushTLB(void);
+
+/* DOS specific fucntions */
+
+#ifdef  __MSDOS__
+uint    PMAPI PMHELP_getVersion(void);
+void    PMAPI PM_VxDCall(VXD_regs *regs);
+#endif
+
+/* Functions to save and restore the VGA hardware state */
+
+int     PMAPI PM_getVGAStateSize(void);
+void    PMAPI PM_saveVGAState(void *stateBuf);
+void    PMAPI PM_restoreVGAState(const void *stateBuf);
+void    PMAPI PM_vgaBlankDisplay(void);
+void    PMAPI PM_vgaUnblankDisplay(void);
+
+/* Functions to load and unload DirectDraw libraries. Only used on
+ * Windows platforms.
+ */
+
+void *  PMAPI PM_loadDirectDraw(int device);
+void    PMAPI PM_unloadDirectDraw(int device);
+PM_HWND PMAPI PM_getDirectDrawWindow(void);
+void    PMAPI PM_doSuspendApp(void);
+
+/* Functions to install, start, stop and remove NT services. Valid only
+ * for Win32 apps running on Windows NT.
+ */
+
+#ifdef __WINDOWS32__
+ulong   PMAPI PM_installService(const char *szDriverName,const char *szServiceName,const char *szLoadGroup,ulong dwServiceType);
+ulong   PMAPI PM_startService(const char *szServiceName);
+ulong   PMAPI PM_stopService(const char *szServiceName);
+ulong   PMAPI PM_removeService(const char *szServiceName);
+#endif
+
+/* Routines to generate native interrupts (ie: protected mode interrupts
+ * for protected mode apps) using an interface the same as that use by
+ * int86() and int86x() in realmode. These routines are required because
+ * many 32 bit compilers use different register structures and different
+ * functions causing major portability headaches. Thus we provide our
+ * own and solve it all in one fell swoop, and we also get a routine to
+ * put stuff into 32 bit registers from real mode ;-)
+ */
+
+void    PMAPI PM_segread(PMSREGS *sregs);
+int     PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out);
+int     PMAPI PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs);
+
+/* Call the X86 emulator or the real BIOS in our test harness */
+
+#if defined(TEST_HARNESS) && !defined(PMLIB)
+#define PM_mapRealPointer(r_seg,r_off)      _PM_imports.PM_mapRealPointer(r_seg,r_off)
+#define PM_getVESABuf(len,rseg,roff)        _PM_imports.PM_getVESABuf(len,rseg,roff)
+#define PM_callRealMode(seg,off,regs,sregs) _PM_imports.PM_callRealMode(seg,off,regs,sregs)
+#define PM_int86(intno,in,out)              _PM_imports.PM_int86(intno,in,out)
+#define PM_int86x(intno,in,out,sregs)       _PM_imports.PM_int86x(intno,in,out,sregs)
+#endif
+
+#ifdef  __cplusplus
+}                       /* End of "C" linkage for C++   */
+#endif
+
+/* Include OS extensions for interrupt handling */
+
+#if defined(__REALDOS__) || defined(__SMX32__)
+#include "pmint.h"
+#endif
+
+#endif /* __PMAPI_H */
diff --git a/board/MAI/bios_emulator/scitech/include/pmimp.h b/board/MAI/bios_emulator/scitech/include/pmimp.h
new file mode 100755
index 0000000..817f5e6
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/pmimp.h
@@ -0,0 +1,193 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Header file declaring all the PM imports structure for the
+*               current version of the PM library. Included in all code
+*               that needs to pass the PM imports to BPD files.
+*
+****************************************************************************/
+
+PM_imports  _VARAPI _PM_imports = {
+    sizeof(PM_imports),
+    PM_getModeType,
+    PM_getBIOSPointer,
+    PM_getA0000Pointer,
+    PM_mapPhysicalAddr,
+    PM_mallocShared,
+    NULL,
+    PM_freeShared,
+    PM_mapToProcess,
+    PM_mapRealPointer,
+    PM_allocRealSeg,
+    PM_freeRealSeg,
+    PM_allocLockedMem,
+    PM_freeLockedMem,
+    PM_callRealMode,
+    PM_int86,
+    PM_int86x,
+    DPMI_int86,
+    PM_availableMemory,
+    PM_getVESABuf,
+    PM_getOSType,
+    PM_fatalError,
+    PM_setBankA,
+    PM_setBankAB,
+    PM_setCRTStart,
+    PM_getCurrentPath,
+    PM_getVBEAFPath,
+    PM_getNucleusPath,
+    PM_getNucleusConfigPath,
+    PM_getUniqueID,
+    PM_getMachineName,
+    VF_available,
+    VF_init,
+    VF_exit,
+    PM_openConsole,
+    PM_getConsoleStateSize,
+    PM_saveConsoleState,
+    PM_restoreConsoleState,
+    PM_closeConsole,
+    PM_setOSCursorLocation,
+    PM_setOSScreenWidth,
+    PM_enableWriteCombine,
+    PM_backslash,
+    PM_lockDataPages,
+    PM_unlockDataPages,
+    PM_lockCodePages,
+    PM_unlockCodePages,
+    PM_setRealTimeClockHandler,
+    PM_setRealTimeClockFrequency,
+    PM_restoreRealTimeClockHandler,
+    PM_doBIOSPOST,
+    PM_getBootDrive,
+    PM_freePhysicalAddr,
+    PM_inpb,
+    PM_inpw,
+    PM_inpd,
+    PM_outpb,
+    PM_outpw,
+    PM_outpd,
+    NULL,
+    PM_setSuspendAppCallback,
+    PM_haveBIOSAccess,
+    PM_kbhit,
+    PM_getch,
+    PM_findBPD,
+    PM_getPhysicalAddr,
+    PM_sleep,
+    PM_getCOMPort,
+    PM_getLPTPort,
+    PM_loadLibrary,
+    PM_getProcAddress,
+    PM_freeLibrary,
+    PCI_enumerate,
+    PCI_accessReg,
+    PCI_setHardwareIRQ,
+    PCI_generateSpecialCyle,
+    NULL,
+    PCIBIOS_getEntry,
+    CPU_getProcessorType,
+    CPU_haveMMX,
+    CPU_have3DNow,
+    CPU_haveSSE,
+    CPU_haveRDTSC,
+    CPU_getProcessorSpeed,
+    ZTimerInit,
+    LZTimerOn,
+    LZTimerLap,
+    LZTimerOff,
+    LZTimerCount,
+    LZTimerOnExt,
+    LZTimerLapExt,
+    LZTimerOffExt,
+    LZTimerCountExt,
+    ULZTimerOn,
+    ULZTimerLap,
+    ULZTimerOff,
+    ULZTimerCount,
+    ULZReadTime,
+    ULZElapsedTime,
+    ULZTimerResolution,
+    PM_findFirstFile,
+    PM_findNextFile,
+    PM_findClose,
+    PM_makepath,
+    PM_splitpath,
+    PM_driveValid,
+    PM_getdcwd,
+    PM_setFileAttr,
+    PM_mkdir,
+    PM_rmdir,
+    PM_getFileAttr,
+    PM_getFileTime,
+    PM_setFileTime,
+    CPU_getProcessorName,
+    PM_getVGAStateSize,
+    PM_saveVGAState,
+    PM_restoreVGAState,
+    PM_vgaBlankDisplay,
+    PM_vgaUnblankDisplay,
+    PM_blockUntilTimeout,
+    _PM_add64,
+    _PM_sub64,
+    _PM_mul64,
+    _PM_div64,
+    _PM_shr64,
+    _PM_sar64,
+    _PM_shl64,
+    _PM_neg64,
+    PCI_findBARSize,
+    PCI_readRegBlock,
+    PCI_writeRegBlock,
+    PM_flushTLB,
+    PM_useLocalMalloc,
+    PM_malloc,
+    PM_calloc,
+    PM_realloc,
+    PM_free,
+    PM_getPhysicalAddrRange,
+    PM_allocPage,
+    PM_freePage,
+    PM_agpInit,
+    PM_agpExit,
+    PM_agpReservePhysical,
+    PM_agpReleasePhysical,
+    PM_agpCommitPhysical,
+    PM_agpFreePhysical,
+    PCI_getNumDevices,
+    PM_setLocalBPDPath,
+#ifdef __WINDOWS32__
+    PM_loadDirectDraw,
+    PM_unloadDirectDraw,
+    PM_getDirectDrawWindow,
+    PM_doSuspendApp,
+#else
+    NULL,
+    NULL,
+    NULL,
+    NULL,
+#endif
+    };
diff --git a/board/MAI/bios_emulator/scitech/include/pmint.h b/board/MAI/bios_emulator/scitech/include/pmint.h
new file mode 100755
index 0000000..7d76dad
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/pmint.h
@@ -0,0 +1,211 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Real mode and 16/32 bit Protected Mode
+*
+* Description:  Header file for the interrupt handling extensions to the OS
+*               Portability Manager Library. These extensions includes
+*               simplified interrupt handling, allowing all common interrupt
+*               handlers to be hooked and handled directly with normal C
+*               functions, both in 16 bit and 32 bit modes. Note however that
+*               simplified handling does not mean slow performance! All low
+*               level interrupt handling is done efficiently in assembler
+*               for speed (well actually necessary to insulate the
+*               application from the lack of far pointers in 32 bit PM). The
+*               interrupt handlers currently supported are:
+*
+*                   Mouse (0x33 callback)
+*                   Timer Tick (0x8)
+*                   Keyboard (0x9 and 0x15)
+*                   Control C/Break (0x23/0x1B)
+*                   Critical Error (0x24)
+*
+****************************************************************************/
+
+#ifndef __PMINT_H
+#define __PMINT_H
+
+/*--------------------------- Macros and Typedefs -------------------------*/
+
+#ifdef __SMX32__
+/* PC interrupts (Ensure consistent with pme.inc) */
+#define PM_IRQ0      0x40
+#define PM_IRQ1      (PM_IRQ0+1)
+#define PM_IRQ6      (PM_IRQ0+6)
+#define PM_IRQ14     (PM_IRQ0+14)
+#endif
+
+/* Define the different types of interrupt handlers that we support     */
+
+typedef uint    (PMAPIP PM_criticalHandler)(uint axValue,uint diValue);
+typedef void    (PMAPIP PM_breakHandler)(uint breakHit);
+typedef short   (PMAPIP PM_key15Handler)(short scanCode);
+typedef void    (PMAPIP PM_mouseHandler)(uint event, uint butstate,int x,int y,int mickeyX,int mickeyY);
+
+/* Create a type for representing far pointers in both 16 and 32 bit
+ * protected mode.
+ */
+
+#ifdef  PM386
+typedef struct {
+    long    off;
+    short   sel;
+    } PMFARPTR;
+#define PMNULL  {0,0}
+#else
+typedef void *PMFARPTR;
+#define PMNULL  NULL
+#endif
+
+/*--------------------------- Function Prototypes -------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {            /* Use "C" linkage when in C++ mode */
+#endif
+
+/* Routine to load save default data segment selector value into a code
+ * segment variable, and another to load the value into the DS register.
+ */
+
+void    PMAPI PM_loadDS(void);
+void    PMAPI PM_saveDS(void);
+
+/* Routine to install a mouse interrupt handling routine. The
+ * mouse handler routine is a normal C function, and the PM library
+ * will take care of passing the correct parameters to the function,
+ * and switching to a local stack.
+ *
+ * Note that you _must_ lock the memory containing the mouse interrupt
+ * handler with the PM_lockPages() function otherwise you may encounter
+ * problems in virtual memory environments.
+ */
+
+int     PMAPI PM_setMouseHandler(int mask,PM_mouseHandler mh);
+void    PMAPI PM_restoreMouseHandler(void);
+
+/* Routine to reset the mouse driver, and re-install the current
+ * mouse interrupt handler if one was currently installed (since the
+ * mouse reset will automatically remove this handler.
+ */
+
+void    PMAPI PM_resetMouseDriver(int hardReset);
+
+/* Routine to reset the mouse driver, and re-install the current
+ * mouse interrupt handler if one was currently installed (since the
+ * mouse reset will automatically remove this handler.
+ */
+
+void    PMAPI PM_resetMouseDriver(int hardReset);
+
+/* Routines to install and remove timer interrupt handlers.
+ *
+ * Note that you _must_ lock the memory containing the interrupt
+ * handlers with the PM_lockPages() function otherwise you may encounter
+ * problems in virtual memory environments.
+ */
+
+void    PMAPI PM_setTimerHandler(PM_intHandler ih);
+void    PMAPI PM_chainPrevTimer(void);
+void    PMAPI PM_restoreTimerHandler(void);
+
+/* Routines to install and keyboard interrupt handlers.
+ *
+ * Note that you _must_ lock the memory containing the interrupt
+ * handlers with the PM_lockPages() function otherwise you may encounter
+ * problems in virtual memory environments.
+ */
+
+void    PMAPI PM_setKeyHandler(PM_intHandler ih);
+void    PMAPI PM_chainPrevKey(void);
+void    PMAPI PM_restoreKeyHandler(void);
+
+/* Routines to hook and unhook the alternate Int 15h keyboard intercept
+ * callout routine. Your event handler will need to return the following:
+ *
+ *  scanCode    - Let the BIOS process scan code (chains to previous handler)
+ *  0           - You have processed the scan code so flush from BIOS
+ *
+ * Note that this is not available under all DOS extenders, but does
+ * work under real mode, DOS4GW and X32-VM. It does not work under the
+ * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know!
+ */
+
+void    PMAPI PM_setKey15Handler(PM_key15Handler ih);
+void    PMAPI PM_restoreKey15Handler(void);
+
+/* Routines to install and remove the control c/break interrupt handlers.
+ * Interrupt handling is performed by the PM/Pro library, and you can call
+ * the supplied routines to test the status of the Ctrl-C and Ctrl-Break
+ * flags. If you pass the value TRUE for 'clearFlag' to these routines,
+ * the internal flags will be reset in order to catch another Ctrl-C or
+ * Ctrl-Break interrupt.
+ */
+
+void    PMAPI PM_installBreakHandler(void);
+int     PMAPI PM_ctrlCHit(int clearFlag);
+int     PMAPI PM_ctrlBreakHit(int clearFlag);
+void    PMAPI PM_restoreBreakHandler(void);
+
+/* Routine to install an alternate break handler that will call your
+ * code directly. This is not available under all DOS extenders, but does
+ * work under real mode, DOS4GW and X32-VM. It does not work under the
+ * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know!
+ *
+ * Note that you should either install one or the other, but not both!
+ */
+
+void    PMAPI PM_installAltBreakHandler(PM_breakHandler bh);
+
+/* Routines to install and remove the critical error handler. The interrupt
+ * is handled by the PM/Pro library, and the operation will always be failed.
+ * You can check the status of the critical error handler with the
+ * appropriate function. If you pass the value TRUE for 'clearFlag', the
+ * internal flag will be reset ready to catch another critical error.
+ */
+
+void    PMAPI PM_installCriticalHandler(void);
+int     PMAPI PM_criticalError(int *axValue, int *diValue, int clearFlag);
+void    PMAPI PM_restoreCriticalHandler(void);
+
+/* Routine to install an alternate critical handler that will call your
+ * code directly. This is not available under all DOS extenders, but does
+ * work under real mode, DOS4GW and X32-VM. It does not work under the
+ * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know!
+ *
+ * Note that you should either install one or the other, but not both!
+ */
+
+void    PMAPI PM_installAltCriticalHandler(PM_criticalHandler);
+
+/* Functions to manage protected mode only interrupt handlers */
+
+void    PMAPI PM_getPMvect(int intno, PMFARPTR *isr);
+void    PMAPI PM_setPMvect(int intno, PM_intHandler ih);
+void    PMAPI PM_restorePMvect(int intno, PMFARPTR isr);
+
+#ifdef  __cplusplus
+}                       /* End of "C" linkage for C++   */
+#endif
+
+#endif /* __PMINT_H */
diff --git a/board/MAI/bios_emulator/scitech/include/scitech.h b/board/MAI/bios_emulator/scitech/include/scitech.h
new file mode 100755
index 0000000..8d5eee9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/scitech.h
@@ -0,0 +1,712 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  General header file for operating system portable code.
+*
+****************************************************************************/
+
+#ifndef __SCITECH_H
+#define __SCITECH_H
+
+/* We have the following defines to identify the compilation environment:
+ *
+ *  __16BIT__       Compiling for 16 bit code (any environment)
+ *  __32BIT__       Compiling for 32 bit code (any environment)
+ *  __MSDOS__       Compiling for MS-DOS (includes __WINDOWS16__, __WIN386__)
+ *  __REALDOS__     Compiling for MS-DOS (excludes __WINDOWS16__)
+ *  __MSDOS16__     Compiling for 16 bit MS-DOS
+ *  __MSDOS32__     Compiling for 32 bit MS-DOS
+ *  __WINDOWS__     Compiling for Windows
+ *  __WINDOWS16__   Compiling for 16 bit Windows (__MSDOS__ also defined)
+ *  __WINDOWS32__   Compiling for 32 bit Windows
+ *  __WIN32_VXD__   Compiling for a 32-bit C based VxD
+ *  __NT_DRIVER__   Compiling for a 32-bit C based NT device driver
+ *  __OS2__         Compiling for OS/2
+ *  __OS2_16__      Compiling for 16 bit OS/2
+ *  __OS2_32__      Compiling for 32 bit OS/2
+ *  __UNIX__        Compiling for Unix
+ *  __QNX__         Compiling for the QNX realtime OS (Unix compatible)
+ *  __LINUX__       Compiling for the Linux OS (Unix compatible)
+ *  __FREEBSD__     Compiling for the FreeBSD OS (Unix compatible)
+ *  __BEOS__        Compiling for the BeOS (Unix compatible)
+ *  __SMX32__       Compiling for the SMX 32-bit Real Time OS
+ *  __ENEA_OSE__    Compiling for the OSE embedded OS
+ *  __RTTARGET__    Compiling for the RTTarget 32-bit embedded OS
+ *  __MACOS__       Compiling for the MacOS platform (PowerPC)
+ *  __DRIVER__      Compiling for a 32-bit binary compatible driver
+ *  __CONSOLE__     Compiling for a fullscreen OS console mode
+ *  __SNAP__        Compiling as a Snap executeable or dynamic library
+ *
+ *  __INTEL__       Compiling for Intel CPU's
+ *  __ALPHA__       Compiling for DEC Alpha CPU's
+ *  __MIPS__        Compiling for MIPS CPU's
+ *  __PPC__         Compiling for PowerPC CPU's
+ *  __MC68K__       Compiling for Motorola 680x0
+ *
+ *  __BIG_ENDIAN__  Compiling for a big endian processor
+ *
+ */
+
+#ifdef  __SC__
+#if     __INTSIZE == 4
+#define __SC386__
+#endif
+#endif
+
+/* Determine some things that are compiler specific */
+
+#ifdef  __GNUC__
+#ifdef  __cplusplus
+/* G++ currently fucks this up! */
+#define __cdecl
+#define __stdcall
+#else
+#undef  __cdecl
+#undef  __stdcall
+#define __cdecl     __attribute__ ((cdecl))
+#define __stdcall   __attribute__ ((stdcall))
+#endif
+#define __FLAT__            /* GCC is always 32 bit flat model          */
+#define __HAS_BOOL__        /* Latest GNU C++ has ibool type            */
+#define __HAS_LONG_LONG__   /* GNU C supports long long type            */
+#include <stdio.h>          /* Bring in for definition of NULL          */
+#endif
+
+#ifdef  __BORLANDC__
+#if (__BORLANDC__ >= 0x500) || defined(CLASSLIB_DEFS_H)
+#define __HAS_BOOL__        /* Borland C++ 5.0 defines ibool type       */
+#endif
+#if (__BORLANDC__ >= 0x502) && !defined(VTOOLSD) && !defined(__SMX32__)
+#define __HAS_INT64__       /* Borland C++ 5.02 supports __int64 type   */
+#endif
+#endif
+
+#if defined(_MSC_VER) && !defined(__SC__) && !defined(VTOOLSD) && !defined(__SMX32__)
+#define __HAS_INT64__       /* Visual C++ supports __int64 type         */
+#endif
+
+#if defined(__WATCOMC__) && (__WATCOMC__ >= 1100) && !defined(VTOOLSD) && !defined(__SMX32__)
+#define __HAS_INT64__       /* Watcom C++ 11.0 supports __int64 type    */
+#endif
+
+/*---------------------------------------------------------------------------
+ * Determine the compile time environment. This must be done for each
+ * supported platform so that we can determine at compile time the target
+ * environment, hopefully without requiring #define's from the user.
+ *-------------------------------------------------------------------------*/
+
+/* 32-bit binary compatible driver. Compiled as Win32, but as OS neutral */
+#ifdef  __DRIVER__
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#undef  __WINDOWS__
+#undef  _WIN32
+#undef  __WIN32__
+#undef  __NT__
+
+/* 32-bit Snap exe or dll. Compiled as Win32, but as OS neutral */
+#elif   defined(__SNAP__)
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#undef  __WINDOWS__
+#undef  _WIN32
+#undef  __WIN32__
+#undef  __NT__
+
+/* 32-bit Windows VxD compile environment */
+#elif   defined(__vtoolsd_h_) || defined(VTOOLSD)
+#include <vtoolsc.h>
+#define __WIN32_VXD__
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#define _MAX_PATH   256
+#undef __WINDOWS32__
+
+/* 32-bit Windows NT driver compile environment: TODO!! */
+#elif   defined(__NT_DRIVER__)
+#include "ntdriver.h"
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#define _MAX_PATH   256
+#undef __WINDOWS32__
+
+/* 32-bit SMX compile environment */
+#elif   defined(__SMX32__)
+#ifndef __MSDOS__
+#define __MSDOS__
+#endif
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+
+/* 32-bit Enea OSE environment */
+#elif   defined(__ENEA_OSE__)
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+
+/* 32-bit RTTarget-32 environment */
+#elif   defined(__RTTARGET__)
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+
+/* 32-bit extended DOS compile environment */
+#elif   defined(__MSDOS__) || defined(__MSDOS32__) || defined(__DOS__) || defined(__DPMI32__) || (defined(M_I86) && (!defined(__SC386__) && !defined(M_I386))) || defined(TNT)
+#ifndef __MSDOS__
+#define __MSDOS__
+#endif
+#if     defined(__MSDOS32__) || defined(__386__) || defined(__FLAT__) || defined(__NT__) || defined(__SC386__)
+#ifndef __MSDOS32__
+#define __MSDOS32__
+#endif
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __REALDOS__
+#define __REALDOS__
+#endif
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+
+/* 16-bit Windows compile environment */
+#elif   (defined(_Windows) || defined(_WINDOWS)) && !defined(__DPMI16__)
+#ifndef __16BIT__
+#define __16BIT__
+#endif
+#ifndef __WINDOWS16__
+#define __WINDOWS16__
+#endif
+#ifndef __WINDOWS__
+#define __WINDOWS__
+#endif
+#ifndef __MSDOS__
+#define __MSDOS__
+#endif
+
+/* 16-bit DOS compile environment */
+#else
+#ifndef __16BIT__
+#define __16BIT__
+#endif
+#ifndef __MSDOS16__
+#define __MSDOS16__
+#endif
+#ifndef __REALDOS__
+#define __REALDOS__
+#endif
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+#endif
+
+/* 32-bit Windows compile environment */
+#elif   defined(WIN32) || defined(_WIN32) || defined(__WIN32__) || defined(__NT__)
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __WINDOWS32__
+#define __WINDOWS32__
+#endif
+#ifndef _WIN32
+#define _WIN32                  /* Microsoft Win32 SDK headers use _WIN32 */
+#endif
+#ifndef WIN32
+#define WIN32                   /* OpenGL headers use WIN32 */
+#endif
+#ifndef __WINDOWS__
+#define __WINDOWS__
+#endif
+
+/* 32-bit OS/2 VDD compile environment */
+/* We're assuming (for now) that CL386 must be used */
+#elif   defined(MSDOS) && defined(M_I386)
+/* fixes necessary to compile with CL386 */
+#define __cdecl  _cdecl
+typedef unsigned int size_t;
+
+#include <mvdm.h>
+
+/* This should probably be somewhere else...                 */
+/* Inline eligible functions (we have no CRT libs for CL386) */
+#pragma intrinsic (strcpy, strcmp, strlen, strcat)
+#pragma intrinsic (memcmp, memcpy, memset)
+
+#define __OS2_VDD__
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#define CCHMAXPATH  256
+#define _MAX_PATH   256
+#ifndef __OS2__
+#define __OS2__
+#endif
+#ifndef __OS2_32__
+#define __OS2_32__
+#endif
+
+/* 16-bit OS/2 compile environment */
+#elif   defined(__OS2_16__)
+#ifndef __OS2__
+#define __OS2__
+#endif
+#ifndef __16BIT__
+#define __16BIT__
+#endif
+#ifndef __OS2_PM__
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+#endif
+
+/* 32-bit OS/2 compile environment */
+#elif   defined(__OS2__) || defined(__OS2_32__)
+#ifndef __OS2__
+#define __OS2__
+#endif
+#ifndef __OS2_32__
+#define __OS2_32__
+#endif
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __OS2_PM__
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+#endif
+
+/* 32-bit QNX compile environment */
+#elif   defined(__QNX__)
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __UNIX__
+#define __UNIX__
+#endif
+#ifdef  __GNUC__
+#define stricmp strcasecmp
+#endif
+#if !defined(__PHOTON__) && !defined(__X11__)
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+#endif
+
+/* 32-bit Linux compile environment */
+#elif   defined(__LINUX__) || defined(linux)
+#ifndef __LINUX__
+#define __LINUX__
+#endif
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __UNIX__
+#define __UNIX__
+#endif
+#ifdef  __GNUC__
+#define stricmp strcasecmp
+#endif
+#ifndef __X11__
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+#endif
+
+/* 32-bit FreeBSD compile environment */
+#elif   defined(__FREEBSD__)
+#ifndef __FREEBSD__
+#define __FREEBSD__
+#endif
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __UNIX__
+#define __UNIX__
+#endif
+#ifdef  __GNUC__
+#define stricmp strcasecmp
+#endif
+#ifndef __X11__
+#ifndef __CONSOLE__
+#define __CONSOLE__
+#endif
+#endif
+
+/* 32-bit BeOS compile environment */
+#elif   defined(__BEOS__)
+#ifndef __32BIT__
+#define __32BIT__
+#endif
+#ifndef __UNIX__
+#define __UNIX__
+#endif
+#ifdef  __GNUC__
+#define stricmp strcasecmp
+#endif
+
+/* Unsupported OS! */
+#else
+#error  This platform is not currently supported!
+#endif
+
+/* Determine the CPU type that we are compiling for */
+
+#if     defined(__M_ALPHA) || defined(__ALPHA_) || defined(__ALPHA) || defined(__alpha)
+#ifndef __ALPHA__
+#define __ALPHA__
+#endif
+#elif   defined(__M_PPC) || defined(__POWERC)
+#ifndef __PPC__
+#define __PPC__
+#endif
+#elif   defined(__M_MRX000)
+#ifndef __MIPS__
+#define __MIPS__
+#endif
+#else
+#ifndef __INTEL__
+#define __INTEL__               /* Assume Intel if nothing found */
+#endif
+#endif
+
+/* We have the following defines to define the calling conventions for
+ * publicly accesible functions:
+ *
+ *  _PUBAPI  - Compiler default calling conventions for all public 'C' functions
+ *  _ASMAPI  - Calling conventions for all public assembler functions
+ *  _VARAPI  - Modifiers for variables; Watcom C++ mangles C++ globals
+ *  _STDCALL - Win32 __stdcall where possible, __cdecl if not supported
+ */
+
+#if defined(_MSC_VER) && defined(_WIN32) && !defined(__SC__)
+#define __PASCAL    __stdcall
+#else
+#define __PASCAL    __pascal
+#endif
+
+#if defined(NO_STDCALL)
+#define _STDCALL    __cdecl
+#else
+#define _STDCALL    __stdcall
+#endif
+
+#ifdef  __WATCOMC__
+#if (__WATCOMC__ >= 1050)
+#define _VARAPI     __cdecl
+#else
+#define _VARAPI
+#endif
+#else
+#define _VARAPI
+#endif
+
+#if defined(__IBMC__) || defined(__IBMCPP__)
+#define PTR_DECL_IN_FRONT
+#endif
+
+/* Define the calling conventions for all public functions. For simplicity
+ * we define all public functions as __cdecl calling conventions, so that
+ * they are the same across all compilers and runtime DLL's.
+ */
+
+#define _PUBAPI __cdecl
+#define _ASMAPI __cdecl
+
+/* Determine the syntax for declaring a function pointer with a
+ * calling conventions override. Most compilers require the calling
+ * convention to be declared in front of the '*', but others require
+ * it to be declared after the '*'. We handle both in here depending
+ * on what the compiler requires.
+ */
+
+#ifdef  PTR_DECL_IN_FRONT
+#define _PUBAPIP    * _PUBAPI
+#define _ASMAPIP    * _ASMAPI
+#else
+#define _PUBAPIP    _PUBAPI *
+#define _ASMAPIP    _ASMAPI *
+#endif
+
+/* Useful macros */
+
+#define PRIVATE static
+#define PUBLIC
+
+/* This HAS to be 0L for 16-bit real mode code to work!!! */
+
+#ifndef NULL
+#       define _NULL 0L
+#       define NULL _NULL
+#endif
+
+#ifndef MAX
+#       define MAX(a,b) ( ((a) > (b)) ? (a) : (b))
+#endif
+#ifndef MIN
+#       define MIN(a,b) ( ((a) < (b)) ? (a) : (b))
+#endif
+#ifndef ABS
+#       define ABS(a)   ((a) >= 0 ? (a) : -(a))
+#endif
+#ifndef SIGN
+#       define SIGN(a)  ((a) > 0 ? 1 : -1)
+#endif
+
+/* General typedefs */
+
+#ifndef __GENDEFS
+#define __GENDEFS
+#if defined(__BEOS__)
+#include <SupportDefs.h>
+#else
+#ifdef __LINUX__
+#include <sys/types.h>
+#ifdef __STRICT_ANSI__
+typedef unsigned short      ushort;
+typedef unsigned long       ulong;
+typedef unsigned int        uint;
+#endif
+#ifdef  __KERNEL__
+#define __GENDEFS_2
+#endif
+#else
+#if !(defined(__QNXNTO__) && defined(GENERAL_STRUCT))
+typedef unsigned short      ushort;
+typedef unsigned long       ulong;
+#endif
+typedef unsigned int        uint;
+#endif
+typedef unsigned char       uchar;
+#endif
+typedef int                 ibool;      /* Integer boolean type         */
+#ifdef  USE_BOOL                        /* Only for older code          */
+#ifndef __cplusplus
+#define bool                ibool       /* Standard C                   */
+#else
+#ifndef __HAS_BOOL__
+#define bool                ibool       /* Older C++ compilers          */
+#endif
+#endif  /* __cplusplus */
+#endif  /* USE_BOOL */
+#endif  /* __GENDEFS */
+
+/* More general typedefs compatible with Linux kernel code */
+
+#ifndef __GENDEFS_2
+#define __GENDEFS_2
+typedef char                s8;
+typedef unsigned char       u8;
+typedef short               s16;
+typedef unsigned short      u16;
+#ifdef  __16BIT__
+typedef long                s32;
+typedef unsigned long       u32;
+#else
+typedef int                 s32;
+typedef unsigned int        u32;
+#endif
+typedef struct {
+    u32 low;
+    s32 high;
+    } __i64;
+#ifdef  __HAS_LONG_LONG__
+#define __NATIVE_INT64__
+typedef long long           s64;
+typedef unsigned long long  u64;
+#elif   defined(__HAS_INT64__) && !defined(__16BIT__)
+#define __NATIVE_INT64__
+typedef __int64             s64;
+typedef unsigned __int64    u64;
+#else
+typedef __i64               s64;
+typedef __i64               u64;
+#endif
+#endif
+
+/* Boolean truth values */
+
+#undef  false
+#undef  true
+#undef  NO
+#undef  YES
+#undef  FALSE
+#undef  TRUE
+#define false       0
+#define true        1
+#define NO          0
+#define YES         1
+#define FALSE       0
+#define TRUE        1
+
+/* Inline debugger interrupts for Watcom C++ and Borland C++ */
+
+#ifdef  __WATCOMC__
+void DebugInt(void);
+#pragma aux DebugInt =              \
+    "int    3";
+void DebugVxD(void);
+#pragma aux DebugVxD =              \
+    "int    1";
+#elif   defined(__BORLANDC__)
+#define DebugInt()  __emit__(0xCC)
+#define DebugVxD()  {__emit__(0xCD); __emit__(0x01);}
+#elif   defined(_MSC_VER)
+#define DebugInt()  _asm int 0x3
+#define DebugVxD()  _asm int 0x1
+#elif   defined(__GNUC__)
+#define DebugInt()  asm volatile ("int $0x3")
+#define DebugVxD()  asm volatile ("int $0x1")
+#else
+void _ASMAPI DebugInt(void);
+void _ASMAPI DebugVxD(void);
+#endif
+
+/* Macros to break once and never break again */
+
+#define DebugIntOnce()              \
+{                                   \
+    static ibool firstTime = true;  \
+    if (firstTime) {                \
+	firstTime = false;          \
+	DebugInt();                 \
+	}                           \
+}
+
+#define DebugVxDOnce()              \
+{                                   \
+    static ibool firstTime = true;  \
+    if (firstTime) {                \
+	firstTime = false;          \
+	DebugVxD();                 \
+	}                           \
+}
+
+/* Macros for linux string compatibility functions */
+
+#ifdef  __LINUX__
+#define stricmp strcasecmp
+#define strnicmp strncasecmp
+#endif
+
+/* Macros for NT driver string compatibility functions */
+
+#ifdef __NT_DRIVER__
+#define stricmp _stricmp
+#define strnicmp _strnicmp
+#endif
+
+/* Get rid of some helaciously annoying Visual C++ warnings! */
+
+#if defined(_MSC_VER) && !defined(__MWERKS__) && !defined(__SC__)
+#pragma warning(disable:4761)   /* integral size mismatch in argument; conversion supplied */
+#pragma warning(disable:4244)   /* conversion from 'unsigned short ' to 'unsigned char ', possible loss of data */
+#pragma warning(disable:4018)   /* '<' : signed/unsigned mismatch */
+#pragma warning(disable:4305)   /* 'initializing' : truncation from 'const double' to 'float' */
+#endif
+
+/*---------------------------------------------------------------------------
+ * Set of debugging macros used by the libraries. If the debug flag is
+ * set, they are turned on depending on the setting of the flag. User code
+ * can override the default functions called when a check fails, and the
+ * MGL does this so it can restore the system from graphics mode to display
+ * an error message. These functions also log information to the
+ * scitech.log file in the root directory of the hard drive when problems
+ * show up.
+ *
+ * If you set the value of CHECKED to be 2, it will also enable code to
+ * insert hard coded debugger interrupt into the source code at the line of
+ * code where the check fail. This is useful if you run the code under a
+ * debugger as it will break inside the debugger before exiting with a
+ * failure condition.
+ *
+ * Also for code compiled to run under Windows, we also call the
+ * OutputDebugString function to send the message to the system debugger
+ * such as Soft-ICE or WDEB386. Hence if you get any non-fatal warnings you
+ * will see those on the debugger terminal as well as in the log file.
+ *-------------------------------------------------------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {            /* Use "C" linkage when in C++ mode */
+#endif
+
+extern void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line);
+void _CHK_defaultFail(int fatal,const char *msg,const char *cond,const char *file,int line);
+
+#ifdef  CHECKED
+#       define  CHK(x)      x
+#if     CHECKED > 1
+#       define  CHECK(p)                                            \
+	((p) ? (void)0 : DebugInt(),                                \
+	    _CHK_fail(1,"Check failed: '%s', file %s, line %d\n",   \
+	    #p, __FILE__, __LINE__))
+#       define  WARN(p)                                             \
+	((p) ? (void)0 : DebugInt(),                                \
+	    _CHK_fail(0,"Warning: '%s', file %s, line %d\n",        \
+	    #p, __FILE__, __LINE__))
+#else
+#       define  CHECK(p)                                            \
+	((p) ? (void)0 :                                            \
+	    _CHK_fail(1,"Check failed: '%s', file %s, line %d\n",   \
+	    #p, __FILE__, __LINE__))
+#       define  WARN(p)                                             \
+	((p) ? (void)0 :                                            \
+	    _CHK_fail(0,"Warning: '%s', file %s, line %d\n",        \
+	    #p, __FILE__, __LINE__))
+#endif
+#       define  LOGFATAL(msg)                                       \
+	    _CHK_fail(1,"Fatal error: '%s', file %s, line %d\n",    \
+	    msg, __FILE__, __LINE__)
+#       define  LOGWARN(msg)                                        \
+	    _CHK_fail(0,"Warning: '%s', file %s, line %d\n",        \
+	    msg, __FILE__, __LINE__)
+#else
+#       define  CHK(x)
+#       define  CHECK(p)        ((void)0)
+#       define  WARN(p)         ((void)0)
+#       define  LOGFATAL(msg)   ((void)0)
+#       define  LOGWARN(msg)    ((void)0)
+#endif
+
+#ifdef  __cplusplus
+}                       /* End of "C" linkage for C++   */
+#endif
+
+#endif  /* __SCITECH_H */
diff --git a/board/MAI/bios_emulator/scitech/include/scitech.mac b/board/MAI/bios_emulator/scitech/include/scitech.mac
new file mode 100755
index 0000000..27a2fc0
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/scitech.mac
@@ -0,0 +1,1321 @@
+;****************************************************************************
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    NetWide Assembler (NASM) or Turbo Assembler (TASM)
+;* Environment: Any Intel Environment
+;*
+;* Description: Macros to provide memory model independant assembly language
+;*              module for C programming. Supports the large and flat memory
+;*              models.
+;*
+;*              The defines that you should use when assembling modules that
+;*              use this macro package are:
+;*
+;*                  __LARGE__   Assemble for 16-bit large model
+;*                  __FLAT__    Assemble for 32-bit FLAT memory model
+;*                  __NOU__     No underscore for all external C labels
+;*                  __NOU_VAR__ No underscore for global variables only
+;*
+;*              The default settings are for 16-bit large memory model with
+;*              leading underscores for symbol names.
+;*
+;*              The main intent of the macro file is to enable programmers
+;*              to write _one_ set of source that can be assembled to run
+;*              in either 16 bit real and protected modes or 32 bit
+;*              protected mode without the need to riddle the code with
+;*              'if flatmodel' style conditional assembly (it is still there
+;*              but nicely hidden by a macro layer that enhances the
+;*              readability and understandability of the resulting code).
+;*
+;****************************************************************************
+
+; Include the appropriate version in here depending on the assembler. NASM
+; appears to always try and parse code, even if it is in a non-compiling
+; block of a ifdef expression, and hence crashes if we include the TASM
+; macro package in the same header file. Hence we split the macros up into
+; two separate header files.
+
+ifdef __NASM_MAJOR__
+
+;============================================================================
+; Macro package when compiling with NASM.
+;============================================================================
+
+; Turn off underscores for globals if disabled for all externals
+
+%ifdef  __NOU__
+%define __NOU_VAR__
+%endif
+
+; Define the __WINDOWS__ symbol if we are compiling for any Windows
+; environment
+
+%ifdef  __WINDOWS16__
+%define __WINDOWS__         1
+%endif
+%ifdef  __WINDOWS32__
+%define __WINDOWS__         1
+%define __WINDOWS32_386__   1
+%endif
+
+; Macros for accessing 'generic' registers
+
+%ifdef  __FLAT__
+%idefine _ax    eax
+%idefine _bx    ebx
+%idefine _cx    ecx
+%idefine _dx    edx
+%idefine _si    esi
+%idefine _di    edi
+%idefine _bp    ebp
+%idefine _sp    esp
+%idefine _es
+%idefine UCHAR  BYTE        ; Size of a character
+%idefine USHORT WORD        ; Size of a short
+%idefine UINT   DWORD       ; Size of an integer
+%idefine ULONG  DWORD       ; Size of a long
+%idefine BOOL   DWORD       ; Size of a boolean
+%idefine DPTR   DWORD       ; Size of a data pointer
+%idefine FDPTR  FWORD       ; Size of a far data pointer
+%idefine NDPTR  DWORD       ; Size of a near data pointer
+%idefine CPTR   DWORD       ; Size of a code pointer
+%idefine FCPTR  FWORD       ; Size of a far code pointer
+%idefine NCPTR  DWORD       ; Size of a near code pointer
+%idefine FPTR   NEAR        ; Distance for function pointers
+%idefine DUINT  dd          ; Declare a integer variable
+%idefine intsize 4
+%idefine flatmodel 1
+%else
+%idefine _ax    ax
+%idefine _bx    bx
+%idefine _cx    cx
+%idefine _dx    dx
+%idefine _si    si
+%idefine _di    di
+%idefine _bp    bp
+%idefine _sp    sp
+%idefine _es    es:
+%idefine UCHAR  BYTE        ; Size of a character
+%idefine USHORT WORD        ; Size of a short
+%idefine UINT   WORD        ; Size of an integer
+%idefine ULONG  DWORD       ; Size of a long
+%idefine BOOL   WORD        ; Size of a boolean
+%idefine DPTR   DWORD       ; Size of a data pointer
+%idefine FDPTR  DWORD       ; Size of a far data pointer
+%idefine NDPTR  WORD        ; Size of a near data pointer
+%idefine CPTR   DWORD       ; Size of a code pointer
+%idefine FCPTR  DWORD       ; Size of a far code pointer
+%idefine NCPTR  WORD        ; Size of a near code pointer
+%idefine FPTR   FAR         ; Distance for function pointers
+%idefine DUINT  dw          ; Declare a integer variable
+%idefine intsize 2
+%endif
+%idefine invert ~
+%idefine offset
+%idefine use_nasm
+
+; Convert all jumps to near jumps, since NASM does not so this automatically
+
+%idefine jo     jo near
+%idefine jno    jno near
+%idefine jz     jz near
+%idefine jnz    jnz near
+%idefine je     je near
+%idefine jne    jne near
+%idefine jb     jb  near
+%idefine jbe    jbe near
+%idefine ja     ja  near
+%idefine jae    jae near
+%idefine jl     jl  near
+%idefine jle    jle near
+%idefine jg     jg  near
+%idefine jge    jge near
+%idefine jc     jc  near
+%idefine jnc    jnc near
+%idefine js     js  near
+%idefine jns    jns near
+
+%ifdef  DOUBLE
+%idefine    REAL    QWORD
+%idefine    DREAL   dq
+%else
+%idefine    REAL    DWORD
+%idefine    DREAL   dd
+%endif
+
+; Boolean truth values (same as those in debug.h)
+
+%idefine False      0
+%idefine True       1
+%idefine No         0
+%idefine Yes        1
+%idefine Yes        1
+
+; Macro to be invoked at the start of all modules to set up segments for
+; later use. Does nothing for NASM.
+
+%imacro header 1
+%endmacro
+
+; Macro to begin a data segment
+
+%imacro begdataseg 1
+%ifdef __GNUC__
+segment .data public class=DATA use32 flat
+%else
+%ifdef flatmodel
+segment _DATA public align=4 class=DATA use32 flat
+%else
+segment _DATA public align=4 class=DATA use16
+%endif
+%endif
+%endmacro
+
+; Macro to end a data segment
+
+%imacro enddataseg 1
+%endmacro
+
+; Macro to begin a code segment
+
+%imacro begcodeseg 1
+%ifdef __PIC__
+%ifdef __LINUX__
+        extern _GLOBAL_OFFSET_TABLE_
+%else
+        extern __GLOBAL_OFFSET_TABLE_
+%endif
+%endif
+%ifdef __GNUC__
+segment .text public class=CODE use32 flat
+%else
+%ifdef flatmodel
+segment _TEXT public align=16 class=CODE use32 flat
+%else
+segment %1_TEXT public align=16 class=CODE use16
+%endif
+%endif
+%endmacro
+
+; Macro to begin a near code segment
+
+%imacro begcodeseg_near 0
+%ifdef __GNUC__
+segment .text public class=CODE use32 flat
+%else
+%ifdef flatmodel
+segment _TEXT public align=16 class=CODE use32 flat
+%else
+segment _TEXT public align=16 class=CODE use16
+%endif
+%endif
+%endmacro
+
+; Macro to end a code segment
+
+%imacro endcodeseg 1
+%endmacro
+
+; Macro to end a near code segment
+
+%imacro endcodeseg_near 0
+%endmacro
+
+; Macro for an extern C symbol. If the C compiler requires leading
+; underscores, then the underscores are added to the symbol names, otherwise
+; they are left off. The symbol name is referenced in the assembler code
+; using the non-underscored symbol name.
+
+%imacro cextern 2
+%ifdef  __NOU_VAR__
+extern %1
+%else
+extern _%1
+%define %1 _%1
+%endif
+%endmacro
+
+%imacro cexternfunc 2
+%ifdef  __NOU__
+extern %1
+%else
+extern _%1
+%define %1 _%1
+%endif
+%endmacro
+
+; Macro for a public C symbol. If the C compiler requires leading
+; underscores, then the underscores are added to the symbol names, otherwise
+; they are left off. The symbol name is referenced in the assembler code
+; using the non-underscored symbol name.
+
+%imacro cpublic 1
+%ifdef  __NOU_VAR__
+global %1
+%1:
+%else
+global _%1
+_%1:
+%define %1 _%1
+%endif
+%endmacro
+
+; Macro for an global C symbol. If the C compiler requires leading
+; underscores, then the underscores are added to the symbol names, otherwise
+; they are left off. The symbol name is referenced in the assembler code
+; using the non-underscored symbol name.
+
+%imacro cglobal 1
+%ifdef  __NOU_VAR__
+global %1
+%else
+global _%1
+%define %1 _%1
+%endif
+%endmacro
+
+; Macro for an global C function symbol. If the C compiler requires leading
+; underscores, then the underscores are added to the symbol names, otherwise
+; they are left off. The symbol name is referenced in the assembler code
+; using the non-underscored symbol name.
+
+%imacro cglobalfunc 1
+%ifdef __PIC__
+global %1:function
+%else
+%ifdef  __NOU__
+global %1
+%else
+global _%1
+%define %1 _%1
+%endif
+%endif
+%endmacro
+
+; Macro to start a C callable function. This will be a far function for
+; 16-bit code, and a near function for 32-bit code.
+
+%imacro cprocstatic 1
+%push cproc
+%1:
+%ifdef flatmodel
+%stacksize flat
+%define ret retn
+%else
+%stacksize large
+%define ret retf
+%endif
+%assign %$localsize 0
+%endmacro
+
+%imacro cprocstart 1
+%push cproc
+    cglobalfunc %1
+%1:
+%ifdef flatmodel
+%stacksize flat
+%define ret retn
+%else
+%stacksize large
+%define ret retf
+%endif
+%assign %$localsize 0
+%endmacro
+
+; This macro sets up a procedure to be exported from a 16 bit DLL. Since the
+; calling conventions are always _far _pascal for 16 bit DLL's, we actually
+; rename this routine with an extra underscore with 'C' calling conventions
+; and a small DLL stub will be provided by the high level code to call the
+; assembler routine.
+
+%imacro cprocstartdll16 1
+%ifdef  __WINDOWS16__
+cprocstart  _%1
+%else
+cprocstart  %1
+%endif
+%endmacro
+
+; Macro to start a C callable near function.
+
+%imacro cprocnear 1
+%push cproc
+    cglobalfunc %1
+%1:
+%define ret retn
+%ifdef flatmodel
+%stacksize flat
+%else
+%stacksize small
+%endif
+%assign %$localsize 0
+%endmacro
+
+; Macro to start a C callable far function.
+
+%imacro cprocfar 1
+%push cproc
+    cglobalfunc %1
+%1:
+%define ret retf
+%ifdef flatmodel
+%stacksize flat
+%else
+%stacksize large
+%endif
+%assign %$localsize 0
+%endmacro
+
+; Macro to end a C function
+
+%imacro cprocend 0
+%pop
+%endmacro
+
+; Macros for entering and exiting C callable functions. Note that we must
+; always save and restore the SI and DI registers for C functions, and for
+; 32 bit C functions we also need to save and restore EBX and clear the
+; direction flag.
+
+%imacro enter_c 0
+        push    _bp
+        mov     _bp,_sp
+%ifnidn %$localsize,0
+        sub     _sp,%$localsize
+%endif
+%ifdef  flatmodel
+        push    ebx
+%endif
+        push    _si
+        push    _di
+%endmacro
+
+%imacro leave_c 0
+        pop     _di
+        pop     _si
+%ifdef  flatmodel
+        pop     ebx
+        cld
+%endif
+%ifnidn %$localsize,0
+        mov     _sp,_bp
+%endif
+        pop     _bp
+%endmacro
+
+%imacro   use_ebx 0
+%ifdef flatmodel
+        push    ebx
+%endif
+%endmacro
+
+%imacro   unuse_ebx 0
+%ifdef flatmodel
+        pop     ebx
+%endif
+%endmacro
+
+; Macros for saving and restoring the value of DS,ES,FS,GS when it is to
+; be used in assembly routines. This evaluates to nothing in the flat memory
+; model, but is saves and restores DS in the large memory model.
+
+%imacro use_ds 0
+%ifndef flatmodel
+        push    ds
+%endif
+%endmacro
+
+%imacro unuse_ds 0
+%ifndef flatmodel
+        pop     ds
+%endif
+%endmacro
+
+%imacro use_es 0
+%ifndef flatmodel
+        push    es
+%endif
+%endmacro
+
+%imacro unuse_es 0
+%ifndef flatmodel
+        pop     es
+%endif
+%endmacro
+
+; Macros for loading the address of a data pointer into a segment and
+; index register pair. The %imacro explicitly loads DS or ES in the 16 bit
+; memory model, or it simply loads the offset into the register in the flat
+; memory model since DS and ES always point to all addressable memory. You
+; must use the correct _REG (ie: _BX) %imacros for documentation purposes.
+
+%imacro _lds    2
+%ifdef flatmodel
+        mov     %1,%2
+%else
+        lds     %1,%2
+%endif
+%endmacro
+
+%imacro   _les  2
+%ifdef flatmodel
+        mov     %1,%2
+%else
+        les     %1,%2
+%endif
+%endmacro
+
+; Macros for adding and subtracting a value from registers. Two value are
+; provided, one for 16 bit modes and another for 32 bit modes (the extended
+; register is used in 32 bit modes).
+
+%imacro   _add  3
+%ifdef flatmodel
+        add     e%1, %3
+%else
+        add     %1, %2
+%endif
+%endmacro
+
+%imacro _sub    3
+%ifdef flatmodel
+        sub     e%1, %3
+%else
+        sub     %1, %2
+%endif
+%endmacro
+
+; Macro to clear the high order word for the 32 bit extended registers.
+; This is used to convert an unsigned 16 bit value to an unsigned 32 bit
+; value, and will evaluate to nothing in 16 bit modes.
+
+%imacro clrhi   1
+%ifdef  flatmodel
+        movzx   e%1,%1
+%endif
+%endmacro
+
+%imacro sgnhi   1
+%ifdef  flatmodel
+        movsx   e%1,%1
+%endif
+%endmacro
+
+; Macro to load an extended register with an integer value in either mode
+
+%imacro loadint 2
+%ifdef flatmodel
+        mov     e%1,%2
+%else
+        xor     e%1,e%1
+        mov     %1,%2
+%endif
+%endmacro
+
+; Macros to load and store integer values with string instructions
+
+%imacro LODSINT 0
+%ifdef flatmodel
+        lodsd
+%else
+        lodsw
+%endif
+%endmacro
+
+%imacro STOSINT 0
+%ifdef flatmodel
+        stosd
+%else
+        stosw
+%endif
+%endmacro
+
+; Macros to provide resb, resw, resd compatibility with NASM
+
+%imacro dclb 1
+times %1 db 0
+%endmacro
+
+%imacro dclw 1
+times %1 dw 0
+%endmacro
+
+%imacro dcld 1
+times %1 dd 0
+%endmacro
+
+; Macro to get the addres of the GOT for Linux/FreeBSD shared
+; libraries into the EBX register.
+
+%imacro     get_GOT 1
+            call    %%getgot
+%%getgot:   pop     %1
+            add     %1,_GLOBAL_OFFSET_TABLE_+$$-%%getgot wrt ..gotpc
+%endmacro
+
+; Macro to get the address of a *local* variable that is global to
+; a single module in a manner that will work correctly when compiled
+; into a Linux shared library. Note that this will *not* work for
+; variables that are defined as global to all modules. For that
+; use the LEA_G macro
+
+%macro      LEA_L    2
+%ifdef __PIC__
+        get_GOT %1
+        lea     %1,[%1+%2 wrt ..gotoff]
+%else
+        lea     %1,[%2]
+%endif
+%endmacro
+
+; Same macro as above but for global variables public to *all*
+; modules.
+
+%macro      LEA_G    2
+%ifdef __PIC__
+        get_GOT %1
+        mov     %1,[%1+%2 wrt ..got]
+%else
+        lea     %1,[%2]
+%endif
+%endmacro
+
+; macros to declare assembler function stubs for function structures
+
+%imacro BEGIN_STUBS_DEF 2
+begdataseg  _STUBS
+%ifdef  __NOU_VAR__
+extern %1
+%define STUBS_START %1
+%else
+extern _%1
+%define STUBS_START _%1
+%endif
+enddataseg  _STUBS
+begcodeseg  _STUBS
+%assign off %2
+%endmacro
+
+%imacro   DECLARE_STUB  1
+%ifdef __PIC__
+        global %1:function
+%1:
+        get_GOT eax
+        mov     eax,[eax+STUBS_START wrt ..got]
+        jmp     [eax+off]
+%else
+%ifdef  __NOU__
+        global %1
+%1:
+%else
+        global _%1
+_%1:
+%endif
+        jmp     [DWORD STUBS_START+off]
+%endif
+%assign off off+4
+%endmacro
+
+%imacro   SKIP_STUB  1
+%assign off off+4
+%endmacro
+
+%imacro DECLARE_STDCALL 2
+%ifdef  STDCALL_MANGLE
+        global _%1@%2
+_%1@%2:
+%else
+%ifdef STDCALL_USCORE
+        global _%1
+_%1:
+%else
+        global %1
+%1:
+%endif
+%endif
+        jmp     [DWORD STUBS_START+off]
+%assign off off+4
+%endmacro
+
+%imacro   END_STUBS_DEF 0
+endcodeseg  _STUBS
+%endmacro
+
+; macros to declare assembler import stubs for binary loadable drivers
+
+%imacro BEGIN_IMPORTS_DEF   1
+BEGIN_STUBS_DEF %1,4
+%endmacro
+
+%imacro   DECLARE_IMP   2
+DECLARE_STUB    %1
+%endmacro
+
+%imacro   SKIP_IMP   2
+SKIP_STUB    %1
+%endmacro
+
+%imacro   SKIP_IMP2   1
+DECLARE_STUB    %1
+%endmacro
+
+%imacro   SKIP_IMP3   1
+SKIP_STUB    %1
+%endmacro
+
+%imacro   END_IMPORTS_DEF 0
+END_STUBS_DEF
+%endmacro
+
+else    ; __NASM_MAJOR__
+
+;============================================================================
+; Macro package when compiling with TASM.
+;============================================================================
+
+; Turn off underscores for globals if disabled for all externals
+
+ifdef   __NOU__
+__NOU_VAR__         = 1
+endif
+
+; Define the __WINDOWS__ symbol if we are compiling for any Windows
+; environment
+
+ifdef   __WINDOWS16__
+__WINDOWS__         = 1
+endif
+ifdef   __WINDOWS32__
+__WINDOWS__         = 1
+__WINDOWS32_386__   = 1
+endif
+ifdef   __WIN386__
+__WINDOWS__         = 1
+__WINDOWS32_386__   = 1
+endif
+ifdef   __VXD__
+__WINDOWS__         = 1
+__WINDOWS32_386__   = 1
+        MASM
+        .386
+        NO_SEGMENTS = 1
+        include vmm.inc         ; IGNORE DEPEND
+        include vsegment.inc    ; IGNORE DEPEND
+        IDEAL
+endif
+
+; Macros for accessing 'generic' registers
+
+ifdef   __FLAT__
+        _ax         EQU eax     ; EAX is used for accumulator
+        _bx         EQU ebx     ; EBX is used for accumulator
+        _cx         EQU ecx     ; ECX is used for looping
+        _dx         EQU edx     ; EDX is used for data register
+        _si         EQU esi     ; ESI is the source index register
+        _di         EQU edi     ; EDI is the destination index register
+        _bp         EQU ebp     ; EBP is used for base pointer register
+        _sp         EQU esp     ; ESP is used for stack pointer register
+        _es         EQU         ; ES and DS are the same in 32 bit PM
+        typedef UCHAR BYTE      ; Size of a character
+        typedef USHORT WORD     ; Size of a short
+        typedef UINT DWORD      ; Size of an integer
+        typedef ULONG DWORD     ; Size of a long
+        typedef BOOL DWORD      ; Size of a boolean
+        typedef DPTR DWORD      ; Size of a data pointer
+        typedef FDPTR FWORD     ; Size of a far data pointer
+        typedef NDPTR DWORD     ; Size of a near data pointer
+        typedef CPTR DWORD      ; Size of a code pointer
+        typedef FCPTR FWORD     ; Size of a far code pointer
+        typedef NCPTR DWORD     ; Size of a near code pointer
+        typedef DUINT DWORD     ; Declare a integer variable
+        FPTR        EQU NEAR    ; Distance for function pointers
+        intsize     =   4       ; Size of an integer
+        flatmodel   =   1       ; This is a flat memory model
+        P386                    ; Turn on 386 code generation
+        MODEL       FLAT        ; Set up for 32 bit simplified FLAT model
+else
+        _ax         EQU ax      ; AX is used for accumulator
+        _bx         EQU bx      ; BX is used for accumulator
+        _cx         EQU cx      ; CX is used for looping
+        _dx         EQU dx      ; DX is used for data register
+        _si         EQU si      ; SI is the source index register
+        _di         EQU di      ; DI is the destination index register
+        _bp         EQU bp      ; BP is used for base pointer register
+        _sp         EQU sp      ; SP is used for stack pointer register
+        _es         EQU es:     ; ES is used for segment override
+        typedef UCHAR BYTE      ; Size of a character
+        typedef USHORT WORD     ; Size of a short
+        typedef UINT WORD       ; Size of an integer
+        typedef ULONG DWORD     ; Size of a long
+        typedef BOOL WORD       ; Size of a boolean
+        typedef DPTR DWORD      ; Size of a data pointer
+        typedef FDPTR DWORD     ; Size of a far data pointer
+        typedef NDPTR WORD      ; Size of a near data pointer
+        typedef CPTR DWORD      ; Size of a code pointer
+        typedef FCPTR DWORD     ; Size of a far code pointer
+        typedef NCPTR WORD      ; Size of a near code pointer
+        typedef DUINT WORD      ; Declare a integer variable
+        FPTR        EQU FAR     ; Distance for function pointers
+        intsize     =   2       ; Size of an integer
+        P386                    ; Turn on 386 code generation
+endif
+        invert      EQU not
+
+; Provide a typedef for real floating point numbers
+
+ifdef   DOUBLE
+typedef REAL    QWORD
+typedef DREAL   QWORD
+else
+typedef REAL    DWORD
+typedef DREAL   DWORD
+endif
+
+; Macros to access the floating point stack registers to convert them
+; from NASM style to TASM style
+
+st0         EQU     st(0)
+st1         EQU     st(1)
+st2         EQU     st(2)
+st3         EQU     st(3)
+st4         EQU     st(4)
+st5         EQU     st(5)
+st6         EQU     st(6)
+st7         EQU     st(7)
+st8         EQU     st(8)
+
+; Boolean truth values (same as those in debug.h)
+
+ifndef  __VXD__
+False       =       0
+True        =       1
+No          =       0
+Yes         =       1
+Yes         =       1
+endif
+
+; Macros for the _DATA data segment. This segment contains initialised data.
+
+MACRO   begdataseg name
+ifdef   __VXD__
+        MASM
+VXD_LOCKED_DATA_SEG
+        IDEAL
+else
+ifdef   flatmodel
+        DATASEG
+else
+SEGMENT _DATA DWORD PUBLIC USE16 'DATA'
+endif
+endif
+ENDM
+
+MACRO   enddataseg name
+ifdef   __VXD__
+        MASM
+VXD_LOCKED_DATA_ENDS
+        IDEAL
+else
+ifndef  flatmodel
+ENDS    _DATA
+endif
+endif
+ENDM
+
+; Macro for the main code segment.
+
+MACRO   begcodeseg name
+ifdef   __VXD__
+        MASM
+VXD_LOCKED_CODE_SEG
+        IDEAL
+else
+ifdef   flatmodel
+        CODESEG
+        ASSUME  CS:FLAT,DS:FLAT,SS:FLAT
+else
+SEGMENT &name&_TEXT PARA PUBLIC USE16 'CODE'
+        ASSUME CS:&name&_TEXT,DS:_DATA
+endif
+endif
+ENDM
+
+; Macro for a near code segment
+
+MACRO   begcodeseg_near
+ifdef   flatmodel
+        CODESEG
+        ASSUME  CS:FLAT,DS:FLAT,SS:FLAT
+else
+SEGMENT _TEXT PARA PUBLIC USE16 'CODE'
+        ASSUME CS:_TEXT,DS:_DATA
+endif
+ENDM
+
+MACRO   endcodeseg name
+ifdef   __VXD__
+        MASM
+VXD_LOCKED_CODE_ENDS
+        IDEAL
+else
+ifndef  flatmodel
+ENDS    &name&_TEXT
+endif
+endif
+ENDM
+
+MACRO   endcodeseg_near
+ifndef  flatmodel
+ENDS    _TEXT
+endif
+ENDM
+
+; Macro to be invoked at the start of all modules to set up segments for
+; later use.
+
+MACRO   header name
+begdataseg name
+enddataseg name
+ENDM
+
+; Macro for an extern C symbol. If the C compiler requires leading
+; underscores, then the underscores are added to the symbol names, otherwise
+; they are left off. The symbol name is referenced in the assembler code
+; using the non-underscored symbol name.
+
+MACRO   cextern name,size
+ifdef   __NOU_VAR__
+        EXTRN   name:size
+else
+        EXTRN   _&name&:size
+name    EQU     _&name&
+endif
+ENDM
+
+MACRO   cexternfunc name,size
+ifdef   __NOU__
+        EXTRN   name:size
+else
+        EXTRN   _&name&:size
+name    EQU     _&name&
+endif
+ENDM
+
+MACRO   stdexternfunc   name,num_args,size
+ifdef   STDCALL_MANGLE
+        EXTRN   _&name&@&num_args&:size
+name    EQU     _&name&@&num_args
+else
+        EXTRN   name:size
+endif
+ENDM
+
+; Macro for a public C symbol. If the C compiler requires leading
+; underscores, then the underscores are added to the symbol names, otherwise
+; they are left off. The symbol name is referenced in the assembler code
+; using the non-underscored symbol name.
+
+MACRO   cpublic name
+ifdef   __NOU_VAR__
+name:
+        PUBLIC  name
+else
+_&name&:
+        PUBLIC  _&name&
+name    EQU     _&name&
+endif
+ENDM
+
+; Macro for an global C symbol. If the C compiler requires leading
+; underscores, then the underscores are added to the symbol names, otherwise
+; they are left off. The symbol name is referenced in the assembler code
+; using the non-underscored symbol name.
+
+MACRO   cglobal name
+ifdef   __NOU_VAR__
+        PUBLIC  name
+else
+        PUBLIC  _&name&
+name    EQU     _&name&
+endif
+ENDM
+
+; Macro for an global C function symbol. If the C compiler requires leading
+; underscores, then the underscores are added to the symbol names, otherwise
+; they are left off. The symbol name is referenced in the assembler code
+; using the non-underscored symbol name.
+
+MACRO   cglobalfunc name
+ifdef   __NOU__
+        PUBLIC  name
+else
+        PUBLIC  _&name&
+name    EQU     _&name&
+endif
+ENDM
+
+; Macro to start a C callable function. This will be a far function for
+; 16-bit code, and a near function for 32-bit code.
+
+MACRO   cprocstatic name        ; Set up model independant private proc
+ifdef flatmodel
+PROC    name NEAR
+else
+PROC    name FAR
+endif
+LocalSize   = 0
+ENDM
+
+MACRO   cprocstart name         ; Set up model independant proc
+ifdef flatmodel
+ifdef   __NOU__
+PROC    name NEAR
+else
+PROC    _&name& NEAR
+endif
+else
+ifdef   __NOU__
+PROC    name FAR
+else
+PROC    _&name& FAR
+endif
+endif
+LocalSize   = 0
+        cglobalfunc name
+ENDM
+
+MACRO   cprocnear name          ; Set up near proc
+ifdef   __NOU__
+PROC    name NEAR
+else
+PROC    _&name& NEAR
+endif
+LocalSize   = 0
+        cglobalfunc name
+ENDM
+
+MACRO   cprocfar name           ; Set up far proc
+ifdef   __NOU__
+PROC    name FAR
+else
+PROC    _&name& FAR
+endif
+LocalSize   = 0
+        cglobalfunc name
+ENDM
+
+MACRO   cprocend               ; End procedure macro
+ENDP
+ENDM
+
+; This macro sets up a procedure to be exported from a 16 bit DLL. Since the
+; calling conventions are always _far _pascal for 16 bit DLL's, we actually
+; rename this routine with an extra underscore with 'C' calling conventions
+; and a small DLL stub will be provided by the high level code to call the
+; assembler routine.
+
+MACRO   cprocstartdll16 name
+ifdef   __WINDOWS16__
+cprocstart  _&name&
+else
+cprocstart  name
+endif
+ENDM
+
+; Macros for entering and exiting C callable functions. Note that we must
+; always save and restore the SI and DI registers for C functions, and for
+; 32 bit C functions we also need to save and restore EBX and clear the
+; direction flag.
+
+MACRO   save_c_regs
+ifdef   flatmodel
+        push    ebx
+endif
+        push    _si
+        push    _di
+ENDM
+
+MACRO   enter_c
+        push    _bp
+        mov     _bp,_sp
+    IFDIFI  <LocalSize>,<0>
+        sub     _sp,LocalSize
+    ENDIF
+        save_c_regs
+ENDM
+
+MACRO   restore_c_regs
+        pop     _di
+        pop     _si
+ifdef   flatmodel
+        pop     ebx
+endif
+ENDM
+
+MACRO   leave_c
+        restore_c_regs
+        cld
+    IFDIFI  <LocalSize>,<0>
+        mov     _sp,_bp
+    ENDIF
+        pop     _bp
+ENDM
+
+MACRO   use_ebx
+ifdef flatmodel
+        push    ebx
+endif
+ENDM
+
+MACRO   unuse_ebx
+ifdef flatmodel
+        pop     ebx
+endif
+ENDM
+
+; Macros for saving and restoring the value of DS,ES,FS,GS when it is to
+; be used in assembly routines. This evaluates to nothing in the flat memory
+; model, but is saves and restores DS in the large memory model.
+
+MACRO   use_ds
+ifndef flatmodel
+        push    ds
+endif
+ENDM
+
+MACRO   unuse_ds
+ifndef flatmodel
+        pop     ds
+endif
+ENDM
+
+MACRO   use_es
+ifndef flatmodel
+        push    es
+endif
+ENDM
+
+MACRO   unuse_es
+ifndef flatmodel
+        pop     es
+endif
+ENDM
+
+; Macros for loading the address of a data pointer into a segment and
+; index register pair. The macro explicitly loads DS or ES in the 16 bit
+; memory model, or it simply loads the offset into the register in the flat
+; memory model since DS and ES always point to all addressable memory. You
+; must use the correct _REG (ie: _BX) macros for documentation purposes.
+
+MACRO   _lds    reg, addr
+ifdef flatmodel
+        mov     reg,addr
+else
+        lds     reg,addr
+endif
+ENDM
+
+MACRO   _les    reg, addr
+ifdef flatmodel
+        mov     reg,addr
+else
+        les     reg,addr
+endif
+ENDM
+
+; Macros for adding and subtracting a value from registers. Two value are
+; provided, one for 16 bit modes and another for 32 bit modes (the extended
+; register is used in 32 bit modes).
+
+MACRO   _add    reg, val16, val32
+ifdef flatmodel
+        add     e&reg&, val32
+else
+        add     reg, val16
+endif
+ENDM
+
+MACRO   _sub    reg, val16, val32
+ifdef flatmodel
+        sub     e&reg&, val32
+else
+        sub     reg, val16
+endif
+ENDM
+
+; Macro to clear the high order word for the 32 bit extended registers.
+; This is used to convert an unsigned 16 bit value to an unsigned 32 bit
+; value, and will evaluate to nothing in 16 bit modes.
+
+MACRO   clrhi   reg
+ifdef   flatmodel
+        movzx   e&reg&,reg
+endif
+ENDM
+
+MACRO   sgnhi   reg
+ifdef   flatmodel
+        movsx   e&reg&,reg
+endif
+ENDM
+
+; Macro to load an extended register with an integer value in either mode
+
+MACRO   loadint reg,val
+ifdef flatmodel
+        mov     e&reg&,val
+else
+        xor     e&reg&,e&reg&
+        mov     reg,val
+endif
+ENDM
+
+; Macros to load and store integer values with string instructions
+
+MACRO   LODSINT
+ifdef flatmodel
+        lodsd
+else
+        lodsw
+endif
+ENDM
+
+MACRO   STOSINT
+ifdef flatmodel
+        stosd
+else
+        stosw
+endif
+ENDM
+
+; Macros to provide resb, resw, resd compatibility with NASM
+
+MACRO   dclb    count
+db  count dup (0)
+ENDM
+
+MACRO   dclw    count
+dw  count dup (0)
+ENDM
+
+MACRO   dcld    count
+dd  count dup (0)
+ENDM
+
+; Macros to provide resb, resw, resd compatibility with NASM
+
+MACRO   resb    count
+db  count dup (?)
+ENDM
+
+MACRO   resw    count
+dw  count dup (?)
+ENDM
+
+MACRO   resd    count
+dd  count dup (?)
+ENDM
+
+; Macros to declare assembler stubs for function structures
+
+MACRO   BEGIN_STUBS_DEF name, firstOffset
+begdataseg  _STUBS
+ifdef   __NOU_VAR__
+        EXTRN   name:DWORD
+STUBS_START =   name
+else
+        EXTRN   _&name&:DWORD
+name    EQU     _&name&
+STUBS_START =   _&name
+endif
+enddataseg  _STUBS
+begcodeseg  _STUBS
+off = firstOffset
+ENDM
+
+MACRO   DECLARE_STUB    name
+ifdef   __NOU__
+name:
+        PUBLIC  name
+else
+_&name:
+        PUBLIC  _&name
+endif
+        jmp     [DWORD STUBS_START+off]
+off = off + 4
+ENDM
+
+MACRO   SKIP_STUB    name
+off = off + 4
+ENDM
+
+MACRO   DECLARE_STDCALL name,num_args
+ifdef   STDCALL_MANGLE
+_&name&@&num_args&:
+        PUBLIC  _&name&@&num_args&
+else
+name:
+        PUBLIC  name
+endif
+        jmp     [DWORD STUBS_START+off]
+off = off + 4
+ENDM
+
+MACRO   END_STUBS_DEF
+endcodeseg  _STUBS
+ENDM
+
+MACRO   BEGIN_IMPORTS_DEF   name
+BEGIN_STUBS_DEF name,4
+ENDM
+
+ifndef LOCAL_DECLARE_IMP
+MACRO   DECLARE_IMP name, numArgs
+DECLARE_STUB    name
+ENDM
+
+MACRO   SKIP_IMP name
+SKIP_STUB       name
+ENDM
+
+MACRO   SKIP_IMP2 name, numArgs
+DECLARE_STUB    name
+ENDM
+
+MACRO   SKIP_IMP3 name
+SKIP_STUB       name
+ENDM
+endif
+
+MACRO   END_IMPORTS_DEF
+END_STUBS_DEF
+ENDM
+
+MACRO   LEA_L    reg,name
+        lea     reg,[name]
+ENDM
+
+MACRO   LEA_G    reg,name
+        lea     reg,[name]
+ENDM
+
+endif
+
diff --git a/board/MAI/bios_emulator/scitech/include/x86emu.h b/board/MAI/bios_emulator/scitech/include/x86emu.h
new file mode 100755
index 0000000..1d87d4e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/x86emu.h
@@ -0,0 +1,194 @@
+/****************************************************************************
+*
+*                       Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                    Copyright (C) David Mosberger-Tang
+*                      Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for public specific functions.
+*               Any application linking against us should only
+*               include this header
+*
+****************************************************************************/
+
+#ifndef __X86EMU_X86EMU_H
+#define __X86EMU_X86EMU_H
+
+#ifdef SCITECH
+#include "scitech.h"
+#define X86API  _ASMAPI
+#define X86APIP _ASMAPIP
+typedef int X86EMU_pioAddr;
+#else
+#include "x86emu/types.h"
+#define X86API
+#define X86APIP *
+#endif
+#include "x86emu/regs.h"
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+#pragma pack(1)
+
+/****************************************************************************
+REMARKS:
+Data structure containing ponters to programmed I/O functions used by the
+emulator. This is used so that the user program can hook all programmed
+I/O for the emulator to handled as necessary by the user program. By
+default the emulator contains simple functions that do not do access the
+hardware in any way. To allow the emualtor access the hardware, you will
+need to override the programmed I/O functions using the X86EMU_setupPioFuncs
+function.
+
+HEADER:
+x86emu.h
+
+MEMBERS:
+inb     - Function to read a byte from an I/O port
+inw     - Function to read a word from an I/O port
+inl     - Function to read a dword from an I/O port
+outb    - Function to write a byte to an I/O port
+outw    - Function to write a word to an I/O port
+outl    - Function to write a dword to an I/O port
+****************************************************************************/
+typedef struct {
+    u8      (X86APIP inb)(X86EMU_pioAddr addr);
+    u16     (X86APIP inw)(X86EMU_pioAddr addr);
+    u32     (X86APIP inl)(X86EMU_pioAddr addr);
+    void    (X86APIP outb)(X86EMU_pioAddr addr, u8 val);
+    void    (X86APIP outw)(X86EMU_pioAddr addr, u16 val);
+    void    (X86APIP outl)(X86EMU_pioAddr addr, u32 val);
+    } X86EMU_pioFuncs;
+
+/****************************************************************************
+REMARKS:
+Data structure containing ponters to memory access functions used by the
+emulator. This is used so that the user program can hook all memory
+access functions as necessary for the emulator. By default the emulator
+contains simple functions that only access the internal memory of the
+emulator. If you need specialised functions to handle access to different
+types of memory (ie: hardware framebuffer accesses and BIOS memory access
+etc), you will need to override this using the X86EMU_setupMemFuncs
+function.
+
+HEADER:
+x86emu.h
+
+MEMBERS:
+rdb     - Function to read a byte from an address
+rdw     - Function to read a word from an address
+rdl     - Function to read a dword from an address
+wrb     - Function to write a byte to an address
+wrw     - Function to write a word to an address
+wrl     - Function to write a dword to an address
+****************************************************************************/
+typedef struct {
+    u8      (X86APIP rdb)(u32 addr);
+    u16     (X86APIP rdw)(u32 addr);
+    u32     (X86APIP rdl)(u32 addr);
+    void    (X86APIP wrb)(u32 addr, u8 val);
+    void    (X86APIP wrw)(u32 addr, u16 val);
+    void    (X86APIP wrl)(u32 addr, u32 val);
+    } X86EMU_memFuncs;
+
+/****************************************************************************
+  Here are the default memory read and write
+  function in case they are needed as fallbacks.
+***************************************************************************/
+extern u8 X86API rdb(u32 addr);
+extern u16 X86API rdw(u32 addr);
+extern u32 X86API rdl(u32 addr);
+extern void X86API wrb(u32 addr, u8 val);
+extern void X86API wrw(u32 addr, u16 val);
+extern void X86API wrl(u32 addr, u32 val);
+
+#pragma pack()
+
+/*--------------------- type definitions -----------------------------------*/
+
+typedef void (X86APIP X86EMU_intrFuncs)(int num);
+extern X86EMU_intrFuncs _X86EMU_intrTab[256];
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {                        /* Use "C" linkage when in C++ mode */
+#endif
+
+void    X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs);
+void    X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs);
+void    X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]);
+void    X86EMU_prepareForInt(int num);
+
+/* decode.c */
+
+void    X86EMU_exec(void);
+void    X86EMU_halt_sys(void);
+
+#ifdef  DEBUG
+#define HALT_SYS()  \
+    printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \
+    X86EMU_halt_sys()
+#else
+#define HALT_SYS()  X86EMU_halt_sys()
+#endif
+
+/* Debug options */
+
+#define DEBUG_DECODE_F          0x0001  /* print decoded instruction  */
+#define DEBUG_TRACE_F           0x0002  /* dump regs before/after execution */
+#define DEBUG_STEP_F            0x0004
+#define DEBUG_DISASSEMBLE_F     0x0008
+#define DEBUG_BREAK_F           0x0010
+#define DEBUG_SVC_F             0x0020
+#define DEBUG_SAVE_CS_IP        0x0040
+#define DEBUG_FS_F              0x0080
+#define DEBUG_PROC_F            0x0100
+#define DEBUG_SYSINT_F          0x0200 /* bios system interrupts. */
+#define DEBUG_TRACECALL_F       0x0400
+#define DEBUG_INSTRUMENT_F      0x0800
+#define DEBUG_MEM_TRACE_F       0x1000
+#define DEBUG_IO_TRACE_F        0x2000
+#define DEBUG_TRACECALL_REGS_F  0x4000
+#define DEBUG_DECODE_NOPRINT_F  0x8000
+#define DEBUG_EXIT              0x10000
+#define DEBUG_SYS_F             (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F)
+
+void    X86EMU_trace_regs(void);
+void    X86EMU_trace_xregs(void);
+void    X86EMU_dump_memory(u16 seg, u16 off, u32 amt);
+int     X86EMU_trace_on(void);
+int     X86EMU_trace_off(void);
+
+#ifdef  __cplusplus
+}                                   /* End of "C" linkage for C++       */
+#endif
+
+#endif /* __X86EMU_X86EMU_H */
diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h b/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h
new file mode 100755
index 0000000..777b03c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h
@@ -0,0 +1,115 @@
+/****************************************************************************
+*
+*                       Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                    Copyright (C) David Mosberger-Tang
+*                      Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for FPU register definitions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_FPU_REGS_H
+#define __X86EMU_FPU_REGS_H
+
+#ifdef X86_FPU_SUPPORT
+
+#pragma pack(1)
+
+/* Basic 8087 register can hold any of the following values: */
+
+union x86_fpu_reg_u {
+    s8                  tenbytes[10];
+    double              dval;
+    float               fval;
+    s16                 sval;
+    s32                 lval;
+    };
+
+struct x86_fpu_reg {
+    union x86_fpu_reg_u reg;
+    char                tag;
+    };
+
+/*
+ * Since we are not going to worry about the problems of aliasing
+ * registers, every time a register is modified, its result type is
+ * set in the tag fields for that register.  If some operation
+ * attempts to access the type in a way inconsistent with its current
+ * storage format, then we flag the operation.  If common, we'll
+ * attempt the conversion.
+ */
+
+#define  X86_FPU_VALID          0x80
+#define  X86_FPU_REGTYP(r)      ((r) & 0x7F)
+
+#define  X86_FPU_WORD           0x0
+#define  X86_FPU_SHORT          0x1
+#define  X86_FPU_LONG           0x2
+#define  X86_FPU_FLOAT          0x3
+#define  X86_FPU_DOUBLE         0x4
+#define  X86_FPU_LDBL           0x5
+#define  X86_FPU_BSD            0x6
+
+#define  X86_FPU_STKTOP  0
+
+struct x86_fpu_registers {
+    struct x86_fpu_reg  x86_fpu_stack[8];
+    int                 x86_fpu_flags;
+    int                 x86_fpu_config;         /* rounding modes, etc. */
+    short               x86_fpu_tos, x86_fpu_bos;
+    };
+
+#pragma pack()
+
+/*
+ * There are two versions of the following macro.
+ *
+ * One version is for opcode D9, for which there are more than 32
+ * instructions encoded in the second byte of the opcode.
+ *
+ * The other version, deals with all the other 7 i87 opcodes, for
+ * which there are only 32 strings needed to describe the
+ * instructions.
+ */
+
+#endif /* X86_FPU_SUPPORT */
+
+#ifdef DEBUG
+# define DECODE_PRINTINSTR32(t,mod,rh,rl)       \
+    DECODE_PRINTF(t[(mod<<3)+(rh)]);
+# define DECODE_PRINTINSTR256(t,mod,rh,rl)      \
+    DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]);
+#else
+# define DECODE_PRINTINSTR32(t,mod,rh,rl)
+# define DECODE_PRINTINSTR256(t,mod,rh,rl)
+#endif
+
+#endif /* __X86EMU_FPU_REGS_H */
diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/regs.h b/board/MAI/bios_emulator/scitech/include/x86emu/regs.h
new file mode 100755
index 0000000..a12017b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/x86emu/regs.h
@@ -0,0 +1,331 @@
+/****************************************************************************
+*
+*                       Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                    Copyright (C) David Mosberger-Tang
+*                      Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for x86 register definitions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_REGS_H
+#define __X86EMU_REGS_H
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+#pragma pack(1)
+
+/*
+ * General EAX, EBX, ECX, EDX type registers.  Note that for
+ * portability, and speed, the issue of byte swapping is not addressed
+ * in the registers.  All registers are stored in the default format
+ * available on the host machine.  The only critical issue is that the
+ * registers should line up EXACTLY in the same manner as they do in
+ * the 386.  That is:
+ *
+ * EAX & 0xff  === AL
+ * EAX & 0xffff == AX
+ *
+ * etc.  The result is that alot of the calculations can then be
+ * done using the native instruction set fully.
+ */
+
+#ifdef  __BIG_ENDIAN__
+
+typedef struct {
+    u32 e_reg;
+    } I32_reg_t;
+
+typedef struct {
+    u16 filler0, x_reg;
+    } I16_reg_t;
+
+typedef struct {
+    u8 filler0, filler1, h_reg, l_reg;
+    } I8_reg_t;
+
+#else /* !__BIG_ENDIAN__ */
+
+typedef struct {
+    u32 e_reg;
+    } I32_reg_t;
+
+typedef struct {
+    u16 x_reg;
+    } I16_reg_t;
+
+typedef struct {
+    u8 l_reg, h_reg;
+    } I8_reg_t;
+
+#endif /* BIG_ENDIAN */
+
+typedef union {
+    I32_reg_t   I32_reg;
+    I16_reg_t   I16_reg;
+    I8_reg_t    I8_reg;
+    } i386_general_register;
+
+struct i386_general_regs {
+    i386_general_register A, B, C, D;
+    };
+
+typedef struct i386_general_regs Gen_reg_t;
+
+struct i386_special_regs {
+    i386_general_register SP, BP, SI, DI, IP;
+    u32 FLAGS;
+    };
+
+/*
+ * Segment registers here represent the 16 bit quantities
+ * CS, DS, ES, SS.
+ */
+
+struct i386_segment_regs {
+    u16 CS, DS, SS, ES, FS, GS;
+    };
+
+/* 8 bit registers */
+#define R_AH  gen.A.I8_reg.h_reg
+#define R_AL  gen.A.I8_reg.l_reg
+#define R_BH  gen.B.I8_reg.h_reg
+#define R_BL  gen.B.I8_reg.l_reg
+#define R_CH  gen.C.I8_reg.h_reg
+#define R_CL  gen.C.I8_reg.l_reg
+#define R_DH  gen.D.I8_reg.h_reg
+#define R_DL  gen.D.I8_reg.l_reg
+
+/* 16 bit registers */
+#define R_AX  gen.A.I16_reg.x_reg
+#define R_BX  gen.B.I16_reg.x_reg
+#define R_CX  gen.C.I16_reg.x_reg
+#define R_DX  gen.D.I16_reg.x_reg
+
+/* 32 bit extended registers */
+#define R_EAX  gen.A.I32_reg.e_reg
+#define R_EBX  gen.B.I32_reg.e_reg
+#define R_ECX  gen.C.I32_reg.e_reg
+#define R_EDX  gen.D.I32_reg.e_reg
+
+/* special registers */
+#define R_SP  spc.SP.I16_reg.x_reg
+#define R_BP  spc.BP.I16_reg.x_reg
+#define R_SI  spc.SI.I16_reg.x_reg
+#define R_DI  spc.DI.I16_reg.x_reg
+#define R_IP  spc.IP.I16_reg.x_reg
+#define R_FLG spc.FLAGS
+
+/* special registers */
+#define R_SP  spc.SP.I16_reg.x_reg
+#define R_BP  spc.BP.I16_reg.x_reg
+#define R_SI  spc.SI.I16_reg.x_reg
+#define R_DI  spc.DI.I16_reg.x_reg
+#define R_IP  spc.IP.I16_reg.x_reg
+#define R_FLG spc.FLAGS
+
+/* special registers */
+#define R_ESP  spc.SP.I32_reg.e_reg
+#define R_EBP  spc.BP.I32_reg.e_reg
+#define R_ESI  spc.SI.I32_reg.e_reg
+#define R_EDI  spc.DI.I32_reg.e_reg
+#define R_EIP  spc.IP.I32_reg.e_reg
+#define R_EFLG spc.FLAGS
+
+/* segment registers */
+#define R_CS  seg.CS
+#define R_DS  seg.DS
+#define R_SS  seg.SS
+#define R_ES  seg.ES
+#define R_FS  seg.FS
+#define R_GS  seg.GS
+
+/* flag conditions   */
+#define FB_CF 0x0001            /* CARRY flag  */
+#define FB_PF 0x0004            /* PARITY flag */
+#define FB_AF 0x0010            /* AUX  flag   */
+#define FB_ZF 0x0040            /* ZERO flag   */
+#define FB_SF 0x0080            /* SIGN flag   */
+#define FB_TF 0x0100            /* TRAP flag   */
+#define FB_IF 0x0200            /* INTERRUPT ENABLE flag */
+#define FB_DF 0x0400            /* DIR flag    */
+#define FB_OF 0x0800            /* OVERFLOW flag */
+
+/* 80286 and above always have bit#1 set */
+#define F_ALWAYS_ON  (0x0002)   /* flag bits always on */
+
+/*
+ * Define a mask for only those flag bits we will ever pass back
+ * (via PUSHF)
+ */
+#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF)
+
+/* following bits masked in to a 16bit quantity */
+
+#define F_CF 0x0001             /* CARRY flag  */
+#define F_PF 0x0004             /* PARITY flag */
+#define F_AF 0x0010             /* AUX  flag   */
+#define F_ZF 0x0040             /* ZERO flag   */
+#define F_SF 0x0080             /* SIGN flag   */
+#define F_TF 0x0100             /* TRAP flag   */
+#define F_IF 0x0200             /* INTERRUPT ENABLE flag */
+#define F_DF 0x0400             /* DIR flag    */
+#define F_OF 0x0800             /* OVERFLOW flag */
+
+#define TOGGLE_FLAG(flag)       (M.x86.R_FLG ^= (flag))
+#define SET_FLAG(flag)          (M.x86.R_FLG |= (flag))
+#define CLEAR_FLAG(flag)        (M.x86.R_FLG &= ~(flag))
+#define ACCESS_FLAG(flag)       (M.x86.R_FLG & (flag))
+#define CLEARALL_FLAG(m)        (M.x86.R_FLG = 0)
+
+#define CONDITIONAL_SET_FLAG(COND,FLAG) \
+  if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG)
+
+#define F_PF_CALC 0x010000      /* PARITY flag has been calced    */
+#define F_ZF_CALC 0x020000      /* ZERO flag has been calced      */
+#define F_SF_CALC 0x040000      /* SIGN flag has been calced      */
+
+#define F_ALL_CALC      0xff0000        /* All have been calced   */
+
+/*
+ * Emulator machine state.
+ * Segment usage control.
+ */
+#define SYSMODE_SEG_DS_SS       0x00000001
+#define SYSMODE_SEGOVR_CS       0x00000002
+#define SYSMODE_SEGOVR_DS       0x00000004
+#define SYSMODE_SEGOVR_ES       0x00000008
+#define SYSMODE_SEGOVR_FS       0x00000010
+#define SYSMODE_SEGOVR_GS       0x00000020
+#define SYSMODE_SEGOVR_SS       0x00000040
+#define SYSMODE_PREFIX_REPE     0x00000080
+#define SYSMODE_PREFIX_REPNE    0x00000100
+#define SYSMODE_PREFIX_DATA     0x00000200
+#define SYSMODE_PREFIX_ADDR     0x00000400
+#define SYSMODE_INTR_PENDING    0x10000000
+#define SYSMODE_EXTRN_INTR      0x20000000
+#define SYSMODE_HALTED          0x40000000
+
+#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS      | \
+			 SYSMODE_SEGOVR_CS      | \
+			 SYSMODE_SEGOVR_DS      | \
+			 SYSMODE_SEGOVR_ES      | \
+			 SYSMODE_SEGOVR_FS      | \
+			 SYSMODE_SEGOVR_GS      | \
+			 SYSMODE_SEGOVR_SS)
+#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS      | \
+			 SYSMODE_SEGOVR_CS      | \
+			 SYSMODE_SEGOVR_DS      | \
+			 SYSMODE_SEGOVR_ES      | \
+			 SYSMODE_SEGOVR_FS      | \
+			 SYSMODE_SEGOVR_GS      | \
+			 SYSMODE_SEGOVR_SS      | \
+			 SYSMODE_PREFIX_DATA    | \
+			 SYSMODE_PREFIX_ADDR)
+
+#define  INTR_SYNCH           0x1
+#define  INTR_ASYNCH          0x2
+#define  INTR_HALTED          0x4
+
+typedef struct {
+    struct i386_general_regs    gen;
+    struct i386_special_regs    spc;
+    struct i386_segment_regs    seg;
+    /*
+     * MODE contains information on:
+     *  REPE prefix             2 bits  repe,repne
+     *  SEGMENT overrides       5 bits  normal,DS,SS,CS,ES
+     *  Delayed flag set        3 bits  (zero, signed, parity)
+     *  reserved                6 bits
+     *  interrupt #             8 bits  instruction raised interrupt
+     *  BIOS video segregs      4 bits
+     *  Interrupt Pending       1 bits
+     *  Extern interrupt        1 bits
+     *  Halted                  1 bits
+     */
+    long                        mode;
+    u8                          intno;
+    volatile int                intr;   /* mask of pending interrupts */
+    int                         debug;
+#ifdef DEBUG
+    int                         check;
+    u16                         saved_ip;
+    u16                         saved_cs;
+    int                         enc_pos;
+    int                         enc_str_pos;
+    char                        decode_buf[32]; /* encoded byte stream  */
+    char                        decoded_buf[256]; /* disassembled strings */
+#endif
+    } X86EMU_regs;
+
+/****************************************************************************
+REMARKS:
+Structure maintaining the emulator machine state.
+
+MEMBERS:
+x86             - X86 registers
+mem_base        - Base real mode memory for the emulator
+mem_size        - Size of the real mode memory block for the emulator
+****************************************************************************/
+typedef struct {
+    X86EMU_regs     x86;
+    unsigned long   mem_base;
+    unsigned long   mem_size;
+    void*           private;
+    } X86EMU_sysEnv;
+
+#pragma pack()
+
+/*----------------------------- Global Variables --------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {                        /* Use "C" linkage when in C++ mode */
+#endif
+
+/* Global emulator machine state.
+ *
+ * We keep it global to avoid pointer dereferences in the code for speed.
+ */
+
+extern    X86EMU_sysEnv _X86EMU_env;
+#define   M             _X86EMU_env
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+/* Function to log information at runtime */
+
+/*void    printk(const char *fmt, ...); */
+
+#ifdef  __cplusplus
+}                                   /* End of "C" linkage for C++       */
+#endif
+
+#endif /* __X86EMU_REGS_H */
diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/types.h b/board/MAI/bios_emulator/scitech/include/x86emu/types.h
new file mode 100755
index 0000000..0a17c54
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/include/x86emu/types.h
@@ -0,0 +1,70 @@
+/****************************************************************************
+*
+*                       Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*                    Copyright (C) David Mosberger-Tang
+*                      Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for x86 emulator type definitions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_TYPES_H
+#define __X86EMU_TYPES_H
+
+#include <sys/types.h>
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+/* Currently only for Linux/32bit */
+#if defined(__GNUC__) && !defined(NO_LONG_LONG)
+#define __HAS_LONG_LONG__
+#endif
+
+typedef unsigned char       u8;
+typedef unsigned short      u16;
+typedef unsigned int        u32;
+#ifdef __HAS_LONG_LONG__
+typedef unsigned long long  u64;
+#endif
+
+typedef char                s8;
+typedef short               s16;
+typedef long                s32;
+#ifdef __HAS_LONG_LONG__
+typedef long long           s64;
+#endif
+
+/*typedef unsigned int      uint;*/
+typedef int                 sint;
+
+typedef u16 X86EMU_pioAddr;
+
+#endif  /* __X86EMU_TYPES_H */
diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt
new file mode 100755
index 0000000..0d87eff
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt
@@ -0,0 +1 @@
+This file is just to ensure that the directory is created.
diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt
new file mode 100755
index 0000000..0d87eff
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt
@@ -0,0 +1 @@
+This file is just to ensure that the directory is created.
diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt
new file mode 100755
index 0000000..0d87eff
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt
@@ -0,0 +1 @@
+This file is just to ensure that the directory is created.
diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt
new file mode 100755
index 0000000..0d87eff
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt
@@ -0,0 +1 @@
+This file is just to ensure that the directory is created.
diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc16.mk b/board/MAI/bios_emulator/scitech/makedefs/bc16.mk
new file mode 100755
index 0000000..aa4fe76
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/bc16.mk
@@ -0,0 +1,137 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Borland C++ 4.x 16 bit version. Supports 16 bit DOS,
+#               DPMI16 DOS extender and 16 bit Windows development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : USE_WIN16 USE_BC5 BC_LIBBASE USE_WIN95
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := bcc
+   CFLAGS       := -ml -H=bcc.sym -i60 -d -dc -4 -f287
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx
+.ELSE
+   AS           := tasm
+.ENDIF
+   ASFLAGS      := /t /mx /m /iINCLUDE /iINCLUDE /i$(SCITECH)\INCLUDE
+   LD           := bclink tlink.exe
+   LDFLAGS      := -c
+   RC           := brc
+   RCFLAGS      :=
+.IF $(USE_BC5)
+.IF $(USE_WIN95)
+   WIN_VERSION  := -V4.0
+.ENDIF
+.ENDIF
+   LIBR         := tlib
+   LIBFLAGS     := /C /P32
+   ILIB         := implib
+   ILIBFLAGS    := -c
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -v
+   LDFLAGS      += -v
+   ASFLAGS      += /zi
+   LIBFLAGS     += /P128
+.ELSE
+   LDFLAGS      += -x
+   ASFLAGS      += /q
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += -O2 -k-
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -O1 -k-
+.END
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -DFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -DBETA
+.END
+
+# Optionally compile as Win16
+.IF $(USE_WIN16)
+.IF $(BUILD_DLL)
+   CFLAGS       += -WD -Fs- -DBUILD_DLL
+   ASFLAGS      += -DBUILD_DLL
+.ELSE
+   CFLAGS       += -W -Fs-
+.ENDIF
+   DEF_LIBS		:= import.lib mathwl.lib cwl.lib
+   DX_ASFLAGS   += -D__WINDOWS16__
+   LIB_OS       = WIN16
+.ELSE
+   USE_REALDOS	:= 1
+   DEF_LIBS     := mathl.lib fp87.lib cl.lib
+   LIB_OS       = DOS16
+.END
+
+# Place to look for PMODE library files
+
+.IF $(USE_DPMI16)
+PMLIB           := dpmi16\pm.lib
+.ELSE
+PMLIB           := pm.lib
+.END
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK	:= bc16.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc3.mk b/board/MAI/bios_emulator/scitech/makedefs/bc3.mk
new file mode 100755
index 0000000..133d80e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/bc3.mk
@@ -0,0 +1,102 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Borland C++ 3.1 version. Supports 16 bit DOS development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := bcc
+   CFLAGS       := -ml -H=bcc.sym -i60 -d
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx
+.ELSE
+   AS           := tasm
+.ENDIF
+   ASFLAGS      := /t /mx /m /iINCLUDE /i$(SCITECH)\INCLUDE
+   LD           := bclink tlink.exe
+   LDFLAGS      := -c
+   LIB          := tlib
+   LIBFLAGS     := /C
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -v
+   LDFLAGS      += -v
+   ASFLAGS      += /zi
+   LIBFLAGS     += /P128
+.ELSE
+   LDFLAGS      += -x
+   ASFLAGS      += /q
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += -3 -O2
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -3 -O1
+.END
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += -f287 -DFPU387
+   ASFLAGS      += -DFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -DBETA
+.END
+   USE_REALDOS	:= 1
+
+# Define the default libraries to link with
+   DEF_LIBS		:= mathl.lib cl.lib
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_DEST     := $(LIB_BASE_DIR)\dos16\bc3
+
+# Define which file contains our rules
+
+   RULES_MAK	:= bc3.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc32.mk b/board/MAI/bios_emulator/scitech/makedefs/bc32.mk
new file mode 100755
index 0000000..246de1d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/bc32.mk
@@ -0,0 +1,201 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Borland C++ 4.0 32 bit version. Supports Borland's DOS Power
+#               Pack DPMI32 DOS extender, Phar Lap's TNT DOS Extender and
+#               32 bit Windows development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : USE_SMX32 USE_TNT USE_WIN32 USE_BC5 USE_VXD BC_LIBBASE
+.IMPORT .IGNORE : VTOOLSD
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := bcc32
+.IF $(USE_VXD)
+   CFLAGS       := -4 -i60 -d -w-stu
+.ELSE
+   CFLAGS       := -4 -H=bcc32.sym -i60 -d -w-stu
+.ENDIF
+.IF $(USE_NASM)
+   AS			:= nasm
+   ASFLAGS      := -t -f obj -d__FLAT__ -iINCLUDE -i$(SCITECH)\INCLUDE
+.ELSE
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx
+.ELSE
+   AS           := tasm
+.ENDIF
+   ASFLAGS      := /t /mx /m /w-res /w-mcp /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.ENDIF
+   LD           := bclink tlink32.exe
+   LDFLAGS      := -c
+   RC           := brc32
+.IF $(USE_BC5)
+   WIN_VERSION  := -V4.0
+   RCFLAGS      := -32
+.ELSE
+   RCFLAGS      := -w32
+.ENDIF
+   LIB          := tlib
+   LIBFLAGS     := /C
+   ILIB         := implib
+   ILIBFLAGS    := -c
+   INTEL_X86	:= 1
+   NMSYM   		:= $(SOFTICE_PATH)\nmsym.exe
+   NMSYMFLAGS	:= /TRANSLATE:source,package,always /PROMPT /SOURCE:$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\win32
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -v
+   LDFLAGS      += -v
+   LIBFLAGS     += /P256
+.IF $(USE_NASM)
+   ASFLAGS      += -F borland -g
+.ELSE
+   ASFLAGS      += /zi
+.ENDIF
+.ELSE
+   LDFLAGS      += -x
+   LIBFLAGS		+= /P128
+.IF $(USE_NASM)
+   ASFLAGS      += -F null
+.ELSE
+   ASFLAGS      += /q
+.ENDIF
+.END
+
+# Optionally disable nagging warnings if MAX_WARN is not on
+.IF $(MAX_WARN)
+.ELSE
+   CFLAGS		+= -w-aus -w-par -w-hid -w-pia
+.ENDIF
+
+# Optionally turn on optimisations (-5 -O2 breaks BC++ 4.0-4.5 sometimes)
+.IF $(OPT)
+   CFLAGS       += -5 -O2 -k-
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -5 -O1 -k-
+.END
+
+# Optionally turn on direct i387 FPU instructions
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.END
+
+# Optionally use Phar Lap's TNT DOS Extender, otherwise use the DOS Power Pack
+.IF $(USE_TNT)
+   CFLAGS       += -D__MSDOS__
+   DX_CFLAGS    += -DTNT
+   DX_ASFLAGS   += -dTNT
+   LIB_OS       = DOS32
+   DEF_LIBS		:= import32.lib cw32.lib dosx32.lib tntapi.lib
+.ELIF $(USE_VXD)
+   LDFLAGS		+= -n -P- -x
+   CFLAGS       += -RT- -x- -Oi -VC -I$(VTOOLSD)\INCLUDE -DIS_32 -DWANTVXDWRAPS -DVTOOLSD -DWIN40 -DWIN40_OR_LATER -DDEFSEG=1 -zC_LTEXT -zALCODE -zR_LDATA -zTLCODE
+   DEF_LIBS		:= $(VTOOLSD)\lib\cfbc440d.lib $(VTOOLSD)\lib\wr0bc440.lib $(VTOOLSD)\lib\wr1bc440.lib $(VTOOLSD)\lib\wr2bc440.lib $(VTOOLSD)\lib\wr3bc440.lib $(VTOOLSD)\lib\rtbc440d.lib
+   DX_ASFLAGS   += -d__VXD__ -d__BORLANDC__=1 -I$(VTOOLSD)\INCLUDE -I$(VTOOLSD)\LIB\INCLUDE
+   LIB_OS       = VXD
+.ELIF $(USE_WIN32)
+.IF $(WIN32_GUI)
+.ELSE
+    CFLAGS       += -D__CONSOLE__
+.ENDIF
+.IF $(BUILD_DLL)
+   CFLAGS       += -WD -DBUILD_DLL
+   ASFLAGS      += -dBUILD_DLL
+.ELSE
+   CFLAGS       += -W -WM
+.ENDIF
+.IF $(USE_BC5)
+.ELSE
+   CFLAGS		+= -D_WIN32
+.ENDIF
+   DEF_LIBS		:= import32.lib cw32mt.lib
+   DX_ASFLAGS   += -d__WINDOWS32__
+   LIB_OS       = WIN32
+.ELIF $(USE_SMX32)
+   CFLAGS       += -D__SMX32__ -DPME32
+   DX_CFLAGS    +=
+   DX_ASFLAGS   += -d__SMX32__ -dDPMI32 -dPME32
+   USE_REALDOS	:= 1
+   LIB_OS       = SMX32
+   DEF_LIBS     := cw32mt.lib
+.ELSE
+   USE_DPMI32   := 1
+   CFLAGS       += -D__MSDOS__
+   DX_CFLAGS    += -WX -DDPMI32
+   DX_ASFLAGS   += -dDPMI32
+   USE_REALDOS	:= 1
+   LIB_OS       = DOS32
+   DEF_LIBS		:=
+.END
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Place to look for PMODE library files
+
+.IF $(USE_TNT)
+PMLIB           := $(LIB_BASE)\tnt\pm.lib
+.ELIF $(USE_DPMI32)
+PMLIB           := $(LIB_BASE)\dpmi32\pm.lib
+.ELSE
+PMLIB           := $(LIB_BASE)\pm.lib
+.END
+
+# Define which file contains our rules
+
+   RULES_MAK	:= bc32.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk b/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk
new file mode 100755
index 0000000..23aeb7c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk
@@ -0,0 +1,137 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Borland C++ 2.0 32-bit OS/2 version.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : USE_OS2GUI BC_LIBBASE
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := bcc
+   CFLAGS       := -w- -4 -H=bcc32.sym -i60 -d
+.IF $(USE_NASM)
+   AS           := nasm
+   ASFLAGS      := -t -f obj -d__FLAT__ -iINCLUDE -i$(SCITECH)\INCLUDE
+.ELSE
+   AS           := tasm
+   ASFLAGS      := /t /mx /m /D__FLAT__ /D__OS2__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.ENDIF
+   LD           := bclink tlink.exe
+   LDFLAGS      := -c
+   RC           := brcc
+   RCFLAGS      :=
+   LIB          := tlib
+   LIBFLAGS     := /C /P32
+   ILIB         := implib
+   ILIBFLAGS    := -c
+.IF $(USE_OS2GUI)
+   CFLAGS		+= -D__OS2_PM__
+.ENDIF
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -v
+   LDFLAGS      += -v
+   LIBFLAGS     += /P128
+.IF $(USE_NASM)
+   ASFLAGS      += -F borland
+.ELSE
+   ASFLAGS      += /zi
+.ENDIF
+.ELSE
+   LDFLAGS      += -x
+.IF $(USE_NASM)
+   ASFLAGS      += -F null
+.ELSE
+   ASFLAGS      += /q
+.ENDIF
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += -5 -O2 -k-
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -5 -O1 -k-
+.END
+
+# Optionally turn on direct i387 FPU instructions
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.END
+
+# Optionally use Phar Lap's TNT DOS Extender, otherwise use the DOS Power Pack
+.IF $(BUILD_DLL)
+   CFLAGS       += -sd -sm -DBUILD_DLL
+   ASFLAGS      += -dBUILD_DLL
+.ELSE
+   CFLAGS       += -sm
+.ENDIF
+   DEF_LIBS	:= os2.lib c2mt.lib
+   DX_ASFLAGS   += -d__OS2__
+   LIB_OS       = os232
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS          += -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Place to look for PMODE library files
+
+.IF $(USE_OS2GUI)
+DEF_LIBS        += pm_pm.lib
+.ELSE
+DEF_LIBS        += pm.lib
+.ENDIF
+
+# Define which file contains our rules
+
+   RULES_MAK	:= bcos2.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/cl16.mk b/board/MAI/bios_emulator/scitech/makedefs/cl16.mk
new file mode 100755
index 0000000..0f29a15
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/cl16.mk
@@ -0,0 +1,132 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Microsoft C 6.0 16 bit version. Supports 16 bit
+#               OS/2 development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : VC_LIBBASE
+.IMPORT .IGNORE : USE_MASM
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := cl       # C-compiler and flags
+   CFLAGS       := /w /Gs
+   ASFLAGS      := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx    # Assembler and flags
+.ELIF $(USE_MASM)
+   AS           := masm    # Assembler and flags
+   ASFLAGS      := /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.ELSE
+   AS           := tasm     # Assembler and flags
+.ENDIF
+   LD           := cl       # Loader and flags
+   LDFLAGS       = $(CFLAGS)
+   RC           := rc       # WIndows resource compiler
+   RCFLAGS      :=
+   LIB          := lib      # Librarian
+   LIBFLAGS     := /NOI /NOE
+   ILIB         := implib   # Import librarian
+   ILIBFLAGS    := /noignorecase
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += /Zi  # Turn on debugging for C compiler
+   ASFLAGS      += /zi      # Turn on debugging for assembler
+.ELSE
+   ASFLAGS      += /q       # Suppress object records not needed for linking
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += /Ox
+.END
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += /FPi87 /DFPU387
+   ASFLAGS      += /DFPU387 /DFPU_REG_RTN
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += /DBETA
+   ASFLAGS      += /DBETA
+.END
+
+# Use a larger stack during linking if requested ???? How the fuck do you
+# specify linker options on the CL command line?????
+
+.IF $(STKSIZE)
+.ENDIF
+
+# Optionally compile for 16 bit Windows
+.IF $(USE_WIN16)
+.IF $(BUILD_DLL)
+   CFLAGS       += /GD /Alfw /DBUILD_DLL
+   ASFLAGS      += -DBUILD_DLL
+.ELSE
+   CFLAGS       += /GA /AL
+.ENDIF
+   DX_ASFLAGS   += -D__WINDOWS16__
+   LIB_OS       = WIN16
+.ELSE
+   USE_REALDOS	:= 1
+   CFLAGS       += /AL
+   LIB_OS       = DOS16
+.END
+
+# Place to look for PMODE library files
+
+PMLIB           := pm.lib
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK	:= cl16.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/cl386.mk b/board/MAI/bios_emulator/scitech/makedefs/cl386.mk
new file mode 100755
index 0000000..52157f9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/cl386.mk
@@ -0,0 +1,120 @@
+#############################################################################
+#
+#                                       SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Microsoft 386 C 6.0 32 bit. Supports 32 bit
+#               OS/2 development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : CL_LIBBASE USE_VDD
+.IMPORT .IGNORE : USE_MASM
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := cl386       # C-compiler and flags
+   # NB: The -Zf flag is ABSOLUTELY NECESSARY to compile IBM's OS/2 headers.
+   #     It isn't documented anywhere but obviously adds support for 48-bit
+   #     far pointers (ie. _far is valid in 32-bit code). Great.
+   CFLAGS       := -G3s -Zf -D__386__
+   ASFLAGS      := /t /mx /m /oi /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx   # Assembler and flags
+.ELIF $(USE_MASM)
+   AS           := masm    # Assembler and flags
+   ASFLAGS      := /t /mx /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.ELSE
+   AS           := tasm     # Assembler and flags
+.ENDIF
+   LD           := link386  # Linker and flags
+   LDFLAGS       = $(CFLAGS)
+   RC           := rc       # Windows resource compiler
+   RCFLAGS      :=
+   LIB          := lib      # Librarian
+   LIBFLAGS     := /NOI /NOE
+   ILIB         := implib   # Import librarian
+   ILIBFLAGS    := /noignorecase
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -Zi      # Turn on debugging for C compiler
+   ASFLAGS      += /zi      # Turn on debugging for assembler
+.ELSE
+   ASFLAGS      += /q       # Suppress object records not needed for linking
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += /Ox
+.END
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += /FPi87 /DFPU387
+   ASFLAGS      += /DFPU387 /DFPU_REG_RTN
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += /DBETA
+   ASFLAGS      += /DBETA
+.END
+
+# Use a larger stack during linking if requested ???? How the fuck do you
+# specify linker options on the CL command line?????
+
+.IF $(STKSIZE)
+.ENDIF
+
+# Place to look for PMODE library files
+
+PMLIB           := pm.lib
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR    := $(SCITECH_LIB)\lib\debug
+CFLAGS                  += -DCHECKED=1
+.ELSE
+LIB_BASE_DIR    := $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_OS       = os232
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(CL_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK    := cl386.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/common.mk b/board/MAI/bios_emulator/scitech/makedefs/common.mk
new file mode 100755
index 0000000..d337152
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/common.mk
@@ -0,0 +1,180 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Common makefile targets used by all SciTech Software
+#               makefiles. This file includes targets for cleaning the
+#               current directory, and maintaining the source files with
+#               RCS.
+#
+#############################################################################
+
+# Override global OpenGL includes when compiling against MGL version
+
+.IF $(USE_MGL_OPENGL)
+.IF $(UNIX_HOST)
+CFLAGS		+= -I$(SCITECH)/include/mglgl
+DEPEND_INC	+= $(SCITECH)/include/mglgl
+.ELSE
+CFLAGS		+= -I$(SCITECH)\include\mglgl
+DEPEND_INC	+= $(SCITECH)\include/mglgl
+.ENDIF
+.ENDIF
+
+# Define where to install all compiled DLL files
+
+.IF $(UNIX_HOST)
+.IF $(CHECKED)
+DLL_DEST    := $(SCITECH_LIB)/redist/debug
+.ELSE
+DLL_DEST    := $(SCITECH_LIB)/redist/release
+.ENDIF
+.ELSE
+.IF $(CHECKED)
+DLL_DEST    := $(SCITECH_LIB)\redist\debug
+.ELSE
+DLL_DEST    := $(SCITECH_LIB)\redist\release
+.ENDIF
+.ENDIF
+
+# Target to build the library and DLL file if specified
+
+.IF $(LIBFILE)
+
+lib: $(LIBFILE)
+
+.IF $(DLLFILE)
+
+# Build and install a DLL file, or simply build import library and install
+
+.IF $(BUILD_DLL)
+
+$(DLLFILE): $(OBJECTS)
+$(LIBFILE): $(DLLFILE)
+install: $(LIBFILE) $(DLLFILE)
+	$(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER)
+	$(INSTALL) $(DLLFILE) $(DLL_DEST)
+.IF $(USE_SOFTICE)
+	$(INSTALL) $(DLLFILE:s/.dll/.nms) $(DLL_DEST)
+.ENDIF
+.ELSE
+
+$(LIBFILE): $(DLL_DEST)\$(DLLFILE)
+install: $(LIBFILE)
+	$(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER)
+
+.ENDIF
+.ELSE
+
+.IF $(BUILD_DLL)
+
+# Build and install a Unix shared library
+
+$(LIBFILE): $(OBJECTS)
+install: $(LIBFILE)
+	$(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER)
+	$(INSTALL) $(LIBFILE) $(DLL_DEST)/$(LIBFILE).$(VERSION)
+
+.ELSE
+
+# Build and install a normal library file
+
+.IF $(USE_DLL)
+.ELSE
+$(LIBFILE): $(OBJECTS)
+install: $(LIBFILE)
+	$(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER)
+.ENDIF
+.ENDIF
+.ENDIF
+.ENDIF
+
+# Build and install a VxD file, including debug information
+
+.IF $(VXDFILE)
+$(VXDFILE:s/.vxd/.dll): $(OBJECTS)
+$(VXDFILE): $(VXDFILE:s/.vxd/.dll)
+install: $(VXDFILE)
+	$(INSTALL) $(VXDFILE) $(DLL_DEST)
+.IF $(DBG)
+	$(INSTALL) $(VXDFILE:s/.vxd/.nms) $(DLL_DEST)
+.ENDIF
+.ENDIF
+
+# Clean up directory removing all files not needed to make the library.
+
+__CLEAN_FILES := *.obj *.o *.sym *.bak *.tdk *.swp *.map *.err *.csm *.lib *.aps *.nms *.sys
+__CLEAN_FILES += *.~* *.td *.tr *.tr? *.td? *.rws *.res *.exp *.ilk *.pdb *.pch *.a bcc32.*
+__CLEAN_FILES += $(LIBCLEAN)
+__CLEANEXE_FILES := $(__CLEAN_FILES) *$E *.drv *.rex *.dll *.vxd *.nms *.pel *.smf *.so.*
+
+.PHONY clean:
+	@$(RM) -f -S $(mktmp $(__CLEAN_FILES:t"\n"))
+
+.PHONY cleanexe:
+	@$(RM) -f -S $(mktmp $(__CLEANEXE_FILES:t"\n"))
+
+# Define the source directories to find common files
+
+.IF $(NO_SCITECH_COMMON)
+.ELSE
+.SOURCE:		   $(SCITECH)/src/common
+.ENDIF
+
+# Create the include file dependencies using the MKUTIL makedep program if
+# the list of dependent object files is defined
+
+.IF $(DEPEND_OBJ)
+depend:
+	@$(RM) -f makefile.dep
+.IF $(DEPEND_SRC)
+.IF $(DEPEND_INC)
+	@makedep -amakefile.dep -r -s -I@$(mktmp $(DEPEND_INC:s/\/\\)) -S@$(mktmp $(DEPEND_SRC:s/\/\\);$(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n)
+.ELSE
+	@makedep -amakefile.dep -r -s -S@$(mktmp $(DEPEND_SRC:s/\/\\);$(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n)
+.ENDIF
+.ELSE
+.IF $(DEPEND_INC)
+	@makedep -amakefile.dep -r -s -I@$(mktmp $(DEPEND_INC:s/\/\\)) -S@$(mktmp $(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n)
+.ELSE
+	@makedep -amakefile.dep -r -s -S@$(mktmp $(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n)
+.ENDIF
+.ENDIF
+	@$(ECHO) Object file dependency information generated.
+.ENDIF
+
+# Set up for compiling Snap executeables and dynamic link libraries
+
+.IF $(USE_SNAP)
+#CFLAGS     	+= -I$(PRIVATE)\include\drvlib -I$(SCITECH)\include\drvlib -D__SNAP__
+CFLAGS     	+= -D__SNAP__
+ASFLAGS   	+= -d__SNAP__
+#EXELIBS		+= snap$L
+.ENDIF
+
+# Include rule definitions for the compiler
+
+.INCLUDE: "$(SCITECH)/makedefs/rules/$(RULES_MAK)"
+
+# Include file dependencies
+
+.INCLUDE .IGNORE: "makefile.dep"
diff --git a/board/MAI/bios_emulator/scitech/makedefs/emx.mk b/board/MAI/bios_emulator/scitech/makedefs/emx.mk
new file mode 100755
index 0000000..f569790
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/emx.mk
@@ -0,0 +1,194 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               OS/2 version for EMX/GNU C/C++.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Disable warnings for macros redefined here that were given
+# on the command line.
+__.SILENT       := $(.SILENT)
+.SILENT         := yes
+
+# Import enivornment variables that we use common to all compilers
+.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB
+.IMPORT .IGNORE : DBG OPT OPT_SIZE CRTDLL SHW BETA CHECKED NO_EXCEPT NO_RTTI
+.IMPORT .IGNORE : FULLSCREEN SHOW_ARGS
+   TMPDIR       := $(TEMP)
+
+# Standard file suffix definitions
+   L            := .lib         # Libraries
+   E            := .exe         # Executables
+   O            := .obj         # Objects
+   A            := .asm         # Assembler sources
+   S            := .s           # GNU assembler sources
+   P            := .cpp         # C++ sources
+
+# File prefix/suffix definitions. The following prefixes are defined, and are
+# used primarily to abstract between the Unix style libXX.a naming convention
+# and the DOS/Windows/OS2 naming convention of XX.lib.
+   LP           :=              # LP - Library file prefix (name of file on disk)
+   LL           := -l           # Library link prefix (name of library on link command line)
+   LE           :=              # Library link suffix (extension of library on link command line)
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : EMX_LIBBASE USE_OS232 USE_OS2GUI
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# DMAKE uses this recipe to remove intermediate targets
+.REMOVE :; $(RM) -f $<
+
+# Turn warnings back to previous setting.
+.SILENT := $(__.SILENT)
+
+# We dont use TABS in our makefiles
+.NOTABS         := yes
+
+# Default commands for compiling, assembling linking and archiving.
+   CC           := gcc
+   CFLAGS       := -Zmt -Zomf -Wall -I. -I$(INCLUDE)
+   CXX          := gcc -x c++ -fno-exceptions -fno-rtti
+.IF $(USE_NASM)
+   AS           := nasm
+   ASFLAGS      := -t -f obj -F null -d__FLAT__ -d__NOU__ -iINCLUDE -i$(SCITECH)\INCLUDE
+.ELSE
+   AS           := tasm     # Assembler and flags
+   ASFLAGS      := /t /mx /m /oi /D__FLAT__ /D__NOU__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.ENDIF
+   LD           := gcc
+   LDXX         := gcc -x c++
+   LDFLAGS      := -L. -Zomf -Zmt
+   LIB          := emxomfar
+   LIBFLAGS     := -p32 rcv
+
+   YACC         := bison -y
+   LEX          := flex
+   SED          := sed
+
+# Optionally turn off exceptions and RTTI for C++ code
+.IF $(NO_EXCEPT)
+   CXX          += -fno-exceptions
+.ENDIF
+.IF $(NO_RTTI)
+   CXX          += -fno-rtti
+.ENDIF
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g
+.ELSE
+# Without -s, emx always runs LINK386 with the /DEBUG option
+   CFLAGS       += -s
+   LDFLAGS      += -s
+# NASM does not support debugging information yet
+   ASFLAGS      +=
+.ENDIF
+
+# Optionally turn on optimisations
+.IF $(OPT_MAX)
+   CFLAGS       += -O6
+.ELIF $(OPT)
+   CFLAGS       += -O3 -fomit-frame-pointer
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -Os
+.ENDIF
+
+# Optionally turn on direct i387 FPU instructions
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.ENDIF
+
+# Disable standard C runtime library
+.IF $(NO_RUNTIME)
+CFLAGS                  += -fno-builtin -nostdinc
+.ENDIF
+
+# Link against EMX DLLs (CRTDLL=1) or link with static C runtime libraries
+.IF $(CRTDLL)
+  LDFLAGS       += -Zcrtdll
+.ELSE
+  CFLAGS		+= -Zsys
+  LDFLAGS       += -Zsys
+.ENDIF
+
+# Target environment dependant flags
+   CFLAGS       += -D__OS2_32__
+   CFLAGS       += -D__OS2__
+   ASFLAGS      += -d__OS2__
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR    := $(SCITECH_LIB)/lib/debug
+CFLAGS          += -DCHECKED=1
+.ELSE
+LIB_BASE_DIR    := $(SCITECH_LIB)/lib/release
+.ENDIF
+
+# Define where to install library files
+   LIB_DEST     := $(LIB_BASE_DIR)\OS232\$(EMX_LIBBASE)
+   LDFLAGS      += -L$(LIB_DEST)
+
+# Build 32-bit OS/2 apps
+.IF $(BUILD_DLL)
+   CFLAGS       += -Zdll -DBUILD_DLL
+   LDFLAGS      += -Zdll
+   ASFLAGS      += -dBUILD_DLL
+.ELSE
+.IF $(USE_OS2GUI)
+   CFLAGS       += -D__OS2_PM__
+   LDFLAGS      += -Zlinker /PMTYPE:PM
+.ELSE
+.IF $(FULLSCREEN)
+   LDFLAGS      += -Zlinker /PMTYPE:NOVIO
+.ELSE
+   LDFLAGS      += -Zlinker /PMTYPE:VIO
+.ENDIF
+.ENDIF
+.ENDIF
+
+# Place to look for PMODE library files
+
+PMLIB           := -lpm
+
+# Define which file contains our rules
+
+   RULES_MAK    := emx.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk
new file mode 100755
index 0000000..0d62fdf
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk
@@ -0,0 +1,161 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               BeOS version for GNU C/C++.
+#
+#############################################################################
+
+# Disable warnings for macros redefined here that were given
+# on the command line.
+__.SILENT       := $(.SILENT)
+.SILENT         := yes
+
+# Import enivornment variables that we use common to all compilers
+.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB
+.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_X11 USE_LINUX
+.IMPORT .IGNORE : USE_EGCS USE_PGCC STATIC_LIBS LIBC
+   TMPDIR       := $(TEMP)
+
+# Standard file suffix definitions
+#
+# NOTE: BeOS does not require any extenion for executeable files, but you
+#       can use an extension if you wish. We use the .x extension for building
+#       executeable files so that we can use implicit rules to make the
+#       makefiles simpler and more portable between systems. When you install
+#       the files to a local bin directory, you will probably want to remove
+#       the .x extension.
+   L            := .a   	# Libraries
+   E            := .x   	# Executables
+   O            := .o   	# Objects
+   A            := .asm   	# Assembler sources
+   S            := .s       # GNU assembler sources
+   P            := .cpp   	# C++ sources
+
+# File prefix/suffix definitions. The following prefixes are defined, and are
+# used primarily to abstract between the Unix style libXX.a naming convention
+# and the DOS/Windows/OS2 naming convention of XX.lib.
+   LP           := lib      # LP - Library file prefix (name of file on disk)
+   LL           := -l		# Library link prefix (name of library on link command line)
+   LE           := 		    # Library link suffix (extension of library on link command line)
+
+# We use the Unix shell at all times
+   SHELLFLAGS   := -c
+
+# Definition of $(MAKE) macro for recursive makes.
+   MAKE = $(MAKECMD) $(MFLAGS)
+
+# Macro to install a library file
+   INSTALL      := cp
+
+# DMAKE uses this recipe to remove intermediate targets
+.REMOVE :; $(RM) -f $<
+
+# Turn warnings back to previous setting.
+.SILENT := $(__.SILENT)
+
+# We dont use TABS in our makefiles
+.NOTABS         := yes
+
+# Define that we are compiling for BeOS
+   USE_BEOS     := 1
+
+# Default commands for compiling, assembling linking and archiving.
+   CC           := gcc
+   CFLAGS       := -Wall -I. -Iinclude $(INCLUDE)
+   CXX          := g++
+   AS           := nasm
+   ASFLAGS      := -f elf -d__FLAT__ -iinclude -i$(SCITECH)/include -d__NOU__
+   LD           := gcc
+   LDFLAGS      := -L.
+   LIB          := ar
+   LIBFLAGS     := rcs
+
+# Link to static libraries if requested
+.IF $(STATIC_LIBS)
+   LDFLAGS      += -static
+.ENDIF
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g
+.ELSE
+# NASM does not support debugging information yet
+   ASFLAGS      +=
+.ENDIF
+
+# Optionally turn on optimisations
+.IF $(OPT_MAX)
+   CFLAGS       += -O6
+.ELIF $(OPT)
+   CFLAGS       += -O2
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -O1
+.ENDIF
+
+# Optionally turn on direct i387 FPU instructions
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.ENDIF
+
+# Disable standard C runtime library
+
+.IF $(NO_RUNTIME)
+CFLAGS			+= -fno-builtin -nostdinc
+.ENDIF
+
+# Target environment dependant flags
+   CFLAGS       += -D__BEOS__
+   ASFLAGS      += -d__BEOS__ -d__UNIX__
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/debug
+CFLAGS		+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/release
+.ENDIF
+
+# Define where to install library files
+LIB_DEST     := $(LIB_BASE_DIR)/beos/gcc
+LDFLAGS      += -L$(LIB_DEST)
+
+# Place to look for PMODE library files
+
+PMLIB           := -lpm
+
+# Define which file contains our rules
+
+   RULES_MAK	:= gcc_beos.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk
new file mode 100755
index 0000000..65589c8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk
@@ -0,0 +1,112 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               DJGPP V2 port of GNU C/C++ to DOS with DPMI only.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Override some file suffix definitions
+   L            := .a     # Libraries
+   O            := .o     # Objects
+
+# Override the file prefix/suffix definitions for library naming.
+   LP           := lib		# LP - Library file prefix (name of file on disk)
+   LL           := -l		# Library link prefix (name of library on link command line)
+   LE           :=			# Library link suffix (extension of library on link command line)
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : DJ_LIBBASE
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := gcc      # C-compiler and flags
+   CFLAGS       := -Wall
+   AS			:= nasm
+   ASFLAGS      := -t -f coff -F null -d__FLAT__ -d__GNUC__ -dSTDCALL_USCORE -iINCLUDE -i$(SCITECH)\INCLUDE
+   LD           := dj_ld    # Loader and flags
+   LDFLAGS      :=
+   LIB          := ar       # Librarian
+   LIBFLAGS     := rs
+   USE_NASM		:= 1
+   USE_GCC		:= 1
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g       # Turn on debugging for C compiler
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += -O2
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -O1
+.END
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.END
+
+# DOS extender dependant flags
+   DX_CFLAGS    +=
+   DX_ASFLAGS   += -dDJGPP
+   USE_REALDOS	:= 1
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_DEST     := $(LIB_BASE_DIR)\DOS32\$(DJ_LIBBASE)
+
+# Place to look for PMODE library files
+
+PMLIB           := -lpm
+
+# Define which file contains our rules
+
+   RULES_MAK	:= dj32.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk
new file mode 100755
index 0000000..0cb4b85
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk
@@ -0,0 +1,174 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Linux version for GNU C/C++.
+#
+#############################################################################
+
+# Disable warnings for macros redefined here that were given
+# on the command line.
+__.SILENT       := $(.SILENT)
+.SILENT         := yes
+
+# Import enivornment variables that we use common to all compilers
+.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB
+.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_X11 USE_FREEBSD
+.IMPORT .IGNORE : USE_EGCS USE_PGCC STATIC_LIBS
+   TMPDIR       := $(TEMP)
+
+# Standard file suffix definitions
+#
+# NOTE: Linux does not require any extenion for executeable files, but you
+#       can use an extension if you wish. We use the .x extension for building
+#       executeable files so that we can use implicit rules to make the
+#       makefiles simpler and more portable between systems. When you install
+#       the files to a local bin directory, you will probably want to remove
+#       the .x extension.
+   L            := .a   	# Libraries
+   E            := .x   	# Executables
+   O            := .o   	# Objects
+   A            := .asm   	# Assembler sources
+   S            := .s       # GNU assembler sources
+   P            := .cpp   	# C++ sources
+
+# File prefix/suffix definitions. The following prefixes are defined, and are
+# used primarily to abstract between the Unix style libXX.a naming convention
+# and the DOS/Windows/OS2 naming convention of XX.lib.
+   LP           := lib      # LP - Library file prefix (name of file on disk)
+   LL           := -l		# Library link prefix (name of library on link command line)
+   LE           := 		    # Library link suffix (extension of library on link command line)
+
+# We use the Unix shell at all times
+   SHELL		:= /bin/sh
+   SHELLFLAGS   := -c
+
+# Definition of $(MAKE) macro for recursive makes.
+   MAKE = $(MAKECMD) $(MFLAGS)
+
+# Macro to install a library file
+   INSTALL      := cp
+
+# DMAKE uses this recipe to remove intermediate targets
+.REMOVE :; $(RM) -f $<
+
+# Turn warnings back to previous setting.
+.SILENT := $(__.SILENT)
+
+# We dont use TABS in our makefiles
+.NOTABS         := yes
+
+# Define that we are compiling for FreeBSD
+   USE_LINUX    := 1
+
+# Default commands for compiling, assembling linking and archiving.
+.IF $(USE_EGCS)
+   CC           := egcs
+.ELIF $(USE_PGCC)
+   CC		:= pgcc
+.ELSE
+   CC           := gcc
+.ENDIF
+   CFLAGS       := -Wall -I. -Iinclude $(INCLUDE)
+   CXX          := g++
+   AS           := nasm
+# TODO: On earlier versions of FreeBSD (<3.0) a.out is used instead of ELF
+   ASFLAGS      := -f elf -d__FLAT__ -iinclude -i$(SCITECH)/include -d__NOU__
+   LD           := g++
+   LDFLAGS      := -L.
+   LIB          := ar
+   LIBFLAGS     := rcs
+
+# Link to static libraries if requested
+.IF $(STATIC_LIBS)
+   LDFLAGS      += -static
+.ENDIF
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g
+.ELSE
+# NASM does not support debugging information yet
+   ASFLAGS      +=
+.ENDIF
+
+# Optionally turn on optimisations
+.IF $(OPT_MAX)
+   CFLAGS       += -O6
+.ELIF $(OPT)
+   CFLAGS       += -O2
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -O1
+.ENDIF
+
+# Optionally turn on direct i387 FPU instructions
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.ENDIF
+
+# Disable standard C runtime library
+
+.IF $(NO_RUNTIME)
+CFLAGS			+= -fno-builtin -nostdinc
+.ENDIF
+
+# Compile flag for whether to build X11 or non-X11 lib
+.IF $(USE_X11)
+   CFLAGS       += -D__X11__
+.ENDIF
+
+# Target environment dependant flags
+   CFLAGS       += -D__FREEBSD__
+   ASFLAGS      += -d__FREEBSD__ -d__UNIX__
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/debug
+CFLAGS		+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/release
+.ENDIF
+
+# Define where to install library files
+   LIB_DEST     := $(LIB_BASE_DIR)/freebsd/gcc
+   LDFLAGS      += -L$(LIB_DEST)
+
+# Place to look for PMODE library files
+
+PMLIB           := -lpm
+
+# Define which file contains our rules
+
+   RULES_MAK	:= gcc_freebsd.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk
new file mode 100755
index 0000000..72c4ced
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk
@@ -0,0 +1,180 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Linux version for GNU C/C++.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)/makedefs/startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : GCC2_LIBBASE
+
+# Override some file suffix definitions
+   L            := .a     # Libraries
+   O            := .o     # Objects
+
+# Override the file prefix/suffix definitions for library naming.
+   LP           := lib		# LP - Library file prefix (name of file on disk)
+   LL           := -l		# Library link prefix (name of library on link command line)
+   LE           :=			# Library link suffix (extension of library on link command line)
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Define that we are compiling for Linux
+   USE_LINUX    := 1
+
+# Default commands for compiling, assembling linking and archiving.
+   CC           := gcc
+   CFLAGS       := -Wall -I. -Iinclude -I$(SCITECH:s,\,/)/include -I$(PRIVATE:s,\,/)/include
+   SHOW_CFLAGS	:= -c
+   CXX          := g++
+   AS           := nasm
+   ASFLAGS      := -t -f elf -d__FLAT__ -d__GNUC__ -iinclude -i$(SCITECH)/include -d__NOU__
+   SHOW_ASFLAGS	:= -f elf
+   LD           := gcc
+   LDXX			:= g++
+   LDFLAGS      := -L.
+   LIB          := ar
+   LIBFLAGS     := rcs
+   YACC			:= bison -y
+   LEX			:= flex
+   SED			:= sed
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g
+   SHOW_CFLAGS  += -g
+.ELSE
+# NASM does not support debugging information yet
+   ASFLAGS      +=
+.ENDIF
+
+# Optionally turn on optimisations
+.IF $(OPT_MAX)
+   CFLAGS       += -O6
+   SHOW_CFLAGS  += -O6
+.ELIF $(OPT)
+   CFLAGS       += -O2
+   SHOW_CFLAGS  += -O2
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -O1
+   SHOW_CFLAGS  += -O1
+.ENDIF
+
+# Optionally turn on direct i387 FPU instructions
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   SHOW_CFLAGS  += -DBETA
+   ASFLAGS      += -dBETA
+   SHOW_ASFLAGS += -dBETA
+.ENDIF
+
+# Disable standard C runtime library
+
+.IF $(NO_RUNTIME)
+CFLAGS			+= -fno-builtin -nostdinc
+.ENDIF
+
+# Compile flag for whether to build X11 or non-X11 lib
+.IF $(USE_X11)
+   CFLAGS       += -D__X11__
+.ENDIF
+
+# Target environment dependant flags
+   CFLAGS       += -D__LINUX__
+   ASFLAGS      += -d__LINUX__ -d__UNIX__
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/debug
+CFLAGS		    += -DCHECKED=1
+SHOW_CFLAGS	    += -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/release
+.ENDIF
+
+# Define where to install library files
+.IF $(LIBC)
+   LIB_DEST_SHARED  := $(LIB_BASE_DIR)/linux/gcc/libc.so
+   LIB_DEST_STATIC  := $(LIB_BASE_DIR)/linux/gcc/libc
+.ELSE
+   LIB_DEST_SHARED  := $(LIB_BASE_DIR)/linux/gcc/glibc.so
+   LIB_DEST_STATIC  := $(LIB_BASE_DIR)/linux/gcc/glibc
+.ENDIF
+
+# Link to static libraries if requested
+.IF $(STATIC_LIBS_ALL)
+   LDFLAGS      += -static
+   STATIC_LIBS  := 1
+.ENDIF
+
+# Link to static libraries if requested
+.IF $(STATIC_LIBS)
+   LDFLAGS      += -L$(LIB_DEST_STATIC)
+.ELSE
+   LDFLAGS      += -L$(LIB_DEST_SHARED) -L$(LIB_DEST_STATIC)
+.ENDIF
+
+# Optionally enable some  dynamic libraries to be built
+.IF $(BUILD_DLL)
+.IF $(VERSIONMAJ)
+.ELSE
+   VERSIONMAJ	:= 5
+   VERSIONMIN	:= 0
+.ENDIF
+   VERSION      := $(VERSIONMAJ).$(VERSIONMIN)
+   LIB		    := gcc -shared
+   LIBFLAGS	    :=
+   L		    := .so
+   CFLAGS	    += -fPIC
+   SHOW_CFLAGS	+= -fPIC
+   ASFLAGS      += -D__PIC__
+   SHOW_ASFLAGS += -D__PIC__
+   LIB_DEST     := $(LIB_DEST_SHARED)
+.ELSE
+   LIB_DEST     := $(LIB_DEST_STATIC)
+.ENDIF
+
+# Place to look for PMODE library files
+
+PMLIB           := -lpm
+
+# Define which file contains our rules
+
+   RULES_MAK	:= gcc_linux.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk
new file mode 100755
index 0000000..21ccf97
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk
@@ -0,0 +1,135 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Cygwin port of GNU C/C++ to Win32.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : GCC2_LIBBASE
+
+# Override some file suffix definitions
+   L            := .a     # Libraries
+   O            := .o     # Objects
+
+# Override the file prefix/suffix definitions for library naming.
+   LP           := lib		# LP - Library file prefix (name of file on disk)
+   LL           := -l		# Library link prefix (name of library on link command line)
+   LE           :=			# Library link suffix (extension of library on link command line)
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := gcc      # C-compiler and flags
+   CFLAGS       := -Wall -I. -Iinclude -I$(SCITECH:s,\,/)/include -I$(PRIVATE:s,\,/)/include
+   SHOW_CFLAGS	:= -c
+   CXX          := g++
+   AS			:= nasm
+   ASFLAGS      := -t -f coff -F null -d__FLAT__ -d__GNUC__ -dSTDCALL_USCORE -iINCLUDE -i$(SCITECH)\INCLUDE
+   SHOW_ASFLAGS	:= -f coff
+   LD           := gcc    	# Loader and flags
+   LDXX			:= g++
+.IF $(WIN32_GUI)
+   LDFLAGS      := -L. -mwindows -e _mainCRTStartup
+.ELSE
+   LDFLAGS      := -L.
+.ENDIF
+   RC           := windres
+   RCFLAGS		:= -O coff
+   LIB          := ar       # Librarian
+   LIBFLAGS     := rcs
+   YACC			:= bison -y
+   LEX			:= flex
+   SED			:= sed
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g
+   SHOW_CFLAGS  += -g
+.ELSE
+# NASM does not support debugging information yet
+   ASFLAGS      +=
+.ENDIF
+
+# Optionally turn on optimisations
+.IF $(OPT_MAX)
+   CFLAGS       += -O6
+   SHOW_CFLAGS  += -O6
+.ELIF $(OPT)
+   CFLAGS       += -O2
+   SHOW_CFLAGS  += -O2
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -O1
+   SHOW_CFLAGS  += -O1
+.ENDIF
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   SHOW_CFLAGS  += -DBETA
+   ASFLAGS      += -dBETA
+   SHOW_ASFLAGS += -dBETA
+.ENDIF
+
+# DOS extender dependant flags
+   DX_CFLAGS    +=
+   DX_ASFLAGS   += -dGCC_WIN32
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+SHOW_CFLAGS	    += -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_DEST     := $(LIB_BASE_DIR)\WIN32\$(GCC2_LIBBASE)
+   LDFLAGS      += -L$(LIB_DEST)
+
+# Place to look for PMODE library files
+
+PMLIB           := -lpm
+
+# Define which file contains our rules
+
+   RULES_MAK	:= gcc_win32.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/hc32.mk b/board/MAI/bios_emulator/scitech/makedefs/hc32.mk
new file mode 100755
index 0000000..f0b065a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/hc32.mk
@@ -0,0 +1,113 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Metaware High C/C++ 3.21 32 bit version. Supports Phar Lap's
+#               TNT DOS Extender.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := hc386    # C-compiler and flags
+   CFLAGS       :=
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx    # Assembler and flags
+.ELSE
+   AS           := tasm     # Assembler and flags
+.ENDIF
+   ASFLAGS      := /t /mx /m /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE
+   LD           := hc386
+   LDFLAGS       = $(CFLAGS)
+   LIB          := 386lib   # TNT 386|lib Librarian
+   LIBFLAGS     := -TC
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g       # Turn on debugging for C compiler
+   ASFLAGS      += /zi      # Turn on debugging for assembler
+.ELSE
+   ASFLAGS      += /q       # Suppress object records not needed for linking
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += -586 -O
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -586 -O1
+.ELSE
+   CFLAGS       += -O0
+.END
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -DFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -DBETA
+.END
+
+# DOS extender dependant flags
+   USE_TNT      := 1
+   USE_REALDOS	:= 1
+   DX_CFLAGS    += -DTNT
+   DX_ASFLAGS   += -DTNT
+   LDFLAGS      += -LH:\TNT\LIB
+
+# Place to look for PMODE library files
+
+PMLIB           := tnt\pm.lib
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\DOS32\HC
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK	:= hc32.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj b/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj
new file mode 100755
index 0000000..edd8809
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj
diff --git a/board/MAI/bios_emulator/scitech/makedefs/qnx4.mk b/board/MAI/bios_emulator/scitech/makedefs/qnx4.mk
new file mode 100755
index 0000000..f583af3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/qnx4.mk
@@ -0,0 +1,164 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               QNX version for Watcom C.
+#
+#############################################################################
+
+# Disable warnings for macros redefined here that were given
+# on the command line.
+__.SILENT       := $(.SILENT)
+.SILENT         := yes
+
+# Import enivornment variables that we use common to all compilers
+.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB
+.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_QNX USE_QNX4
+.IMPORT .IGNORE : USE_PHOTON USE_X11 USE_BIOS SHOW_ARGS MAX_WARN WC_LIBBASE
+   TMPDIR       := $(TEMP)
+
+# Standard file suffix definitions
+#
+# NOTE: Qnx does not require any extension for executeable files, but you
+#       can use an extension if you wish. We use the .x extension for building
+#       executeable files so that we can use implicit rules to make the
+#       makefiles simpler and more portable between systems. When you install
+#       the files to a local bin directory, you will probably want to remove
+#       the .x extension.
+   L            := .a   	# Libraries
+   E            := .exe   	# Executables
+   O            := .o   	# Objects
+   A            := .asm   	# Assembler sources
+   S            := .s       # GNU assembler sources
+   P            := .cpp   	# C++ sources
+
+# File prefix/suffix definitions. The following prefixes are defined, and are
+# used primarily to abstract between the Unix style libXX.a naming convention
+# and the DOS/Windows/OS2 naming convention of XX.lib.
+   LP           := lib      # LP - Library file prefix (name of file on disk)
+   LL           := -l		# Library link prefix (name of library on link command line)
+   LE           := 		    # Library link suffix (extension of library on link command line)
+
+# We use the Unix shell at all times
+   SHELL		:= /bin/sh
+   SHELLFLAGS   := -c
+
+# Definition of $(MAKE) macro for recursive makes.
+   MAKE = $(MAKECMD) $(MFLAGS)
+
+# Macro to install a library file
+   INSTALL      := cp
+
+# DMAKE uses this recipe to remove intermediate targets
+.REMOVE :; $(RM) -f $<
+
+# Turn warnings back to previous setting.
+.SILENT := $(__.SILENT)
+
+# We dont use TABS in our makefiles
+.NOTABS         := yes
+
+# Define that we are compiling for QNX
+   USE_QNX    	:= 1
+
+# Default commands for compiling, assembling linking and archiving.
+   CC           := wcc386
+   CFLAGS       := -I. -Iinclude $(INCLUDE)
+   CXX          := wpp386
+   AS           := nasm
+   ASFLAGS      := -t -f obj -d__FLAT__ -dSTDCALL_MANGLE -iinclude -i$(SCITECH)/include
+   LD           := cc
+   LDFLAGS      := -L.
+   LIB          := ar
+   LIBFLAGS     := rc
+
+# Set the compiler warning level
+.IF $(MAX_WARN)
+   CFLAGS       += -w4
+.ELSE
+   CFLAGS       += -w1
+.ENDIF
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -d2
+   LDFLAGS      += -g2
+.ELSE
+# NASM does not support debugging information yet
+   ASFLAGS      +=
+.ENDIF
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += -onatx-5r-fp5
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -onaslmr-5r-fp5
+.ELIF $(NOOPT)
+   CFLAGS       += -od-5r
+.END
+
+# Compile flag for whether to build photon or non-photon lib
+.IF $(USE_PHOTON)
+   CFLAGS       += -D__PHOTON__
+.ENDIF
+
+# Compile flag for whether to build X11 or non-X11 lib
+.IF $(USE_X11)
+   CFLAGS       += -D__X11__
+.ENDIF
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.ENDIF
+
+# Target environment dependant flags
+   CFLAGS       += -D__QNX__ -D__UNIX__
+   ASFLAGS      += -d__QNX__ -d__UNIX__
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+  LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/debug
+  CFLAGS		+= -DCHECKED=1
+.ELSE
+  LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)/qnx4/$(WC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+   LDFLAGS      += -L$(LIB_DEST)
+
+# Place to look for PMODE library files
+
+PMLIB           := -lpm
+
+# Define which file contains our rules
+
+   RULES_MAK	:= qnx4.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/qnxnto.mk b/board/MAI/bios_emulator/scitech/makedefs/qnxnto.mk
new file mode 100755
index 0000000..5168ed2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/qnxnto.mk
@@ -0,0 +1,157 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               QNX Neutrino version for GNU C/C++
+#
+#############################################################################
+
+# Disable warnings for macros redefined here that were given
+# on the command line.
+__.SILENT       := $(.SILENT)
+.SILENT         := yes
+
+# Import enivornment variables that we use common to all compilers
+.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB
+.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_QNX USE_QNXNTO
+.IMPORT .IGNORE : USE_EGCS USE_PHOTON USE_X11 USE_BIOS
+   TMPDIR       := $(TEMP)
+
+# Standard file suffix definitions
+#
+# NOTE: Qnx does not require any extension for executeable files, but you
+#       can use an extension if you wish. We use the .x extension for building
+#       executeable files so that we can use implicit rules to make the
+#       makefiles simpler and more portable between systems. When you install
+#       the files to a local bin directory, you will probably want to remove
+#       the .x extension.
+   L            := .a   	# Libraries
+   E            := .x   	# Executables
+   O            := .o   	# Objects
+   A            := .asm   	# Assembler sources
+   S            := .s       # GNU assembler sources
+   P            := .cpp   	# C++ sources
+
+# File prefix/suffix definitions. The following prefixes are defined, and are
+# used primarily to abstract between the Unix style libXX.a naming convention
+# and the DOS/Windows/OS2 naming convention of XX.lib.
+   LP           := lib      # LP - Library file prefix (name of file on disk)
+   LL           := -l		# Library link prefix (name of library on link command line)
+   LE           := 		    # Library link suffix (extension of library on link command line)
+
+# We use the Unix shell at all times
+   SHELL		:= /bin/sh
+   SHELLFLAGS   := -c
+
+# Definition of $(MAKE) macro for recursive makes.
+   MAKE = $(MAKECMD) $(MFLAGS)
+
+# Macro to install a library file
+   INSTALL      := cp
+
+# DMAKE uses this recipe to remove intermediate targets
+.REMOVE :; $(RM) -f $<
+
+# Turn warnings back to previous setting.
+.SILENT := $(__.SILENT)
+
+# We dont use TABS in our makefiles
+.NOTABS         := yes
+
+# Define that we are compiling for QNX
+   USE_QNX    	:= 1
+
+# Default commands for compiling, assembling linking and archiving.
+   CC           := qcc
+   CFLAGS       := -Vgcc_ntox86 -I. -Iinclude $(INCLUDE)
+   CPPFLAGS     := -Vgcc_ntox86 -I. -Iinclude $(INCLUDE)
+   CXX          := QCC
+   AS           := nasm
+   ASFLAGS      := -t -f elf -d__FLAT__ -d__GNUC__ -dSTDCALL_MANGLE -iinclude -i$(SCITECH)/include -d__NOU__
+   LD           := qcc
+   LDFLAGS      := -Vgcc_ntox86 -L. -lm
+   LIB          := ar
+   LIBFLAGS     := rc
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g2
+   LDFLAGS      += -g2
+.ELSE
+# NASM does not support debugging information yet
+   ASFLAGS      +=
+.ENDIF
+
+# Optionally turn on optimisations
+.IF $(OPT_MAX)
+   CFLAGS       += -Ot
+.ELIF $(OPT)
+   CFLAGS       += -O
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -Os
+.ENDIF
+
+# Compile flag for whether to build photon or non-photon lib
+.IF $(USE_PHOTON)
+   CFLAGS       += -D__PHOTON__
+.ENDIF
+
+# Compile flag for whether to build X11 or non-X11 lib
+.IF $(USE_X11)
+   CFLAGS       += -D__X11__
+.ENDIF
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.ENDIF
+
+# Target environment dependant flags
+   CFLAGS       += -D__QNX__ -D__UNIX__
+   ASFLAGS      += -d__QNX__ -d__UNIX__
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+  LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/debug
+  CFLAGS		+= -DCHECKED=1
+.ELSE
+  LIB_BASE_DIR	:= $(SCITECH_LIB)/lib/release
+.ENDIF
+
+# Define where to install library files
+   LIB_DEST	:= $(LIB_BASE_DIR)/qnxnto
+   LDFLAGS      += -L$(LIB_DEST)
+
+# Place to look for PMODE library files
+
+PMLIB           := -lpm
+
+# Define which file contains our rules
+
+   RULES_MAK	:= qnxnto.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bc16.mk
new file mode 100755
index 0000000..67ae910
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/bc16.mk
@@ -0,0 +1,69 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $<
+%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $<
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+%$D:      ; $(LD) $(mktmp $(LDFLAGS) -C -Twd c0dl.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(EXELIBS)\n$*.def)
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ $?
+.ELIF $(IMPORT_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ $?
+.ELSE
+%$L: ;
+    @$(RM) $@
+    $(LIBR) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_WIN16)
+%$E: ; $(LD) $(mktmp $(LDFLAGS) -C -Twe $(WIN_VERSION) c0wl.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(EXELIBS)\n$*.def)
+.ELSE
+%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tde c0l.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(PMLIB) $(DEF_LIBS) $(EXELIBS))
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bc3.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bc3.mk
new file mode 100755
index 0000000..d4d071c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/bc3.mk
@@ -0,0 +1,43 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) @$(mktmp $(CFLAGS)) -c $<
+%$O: %$P ; $(CC) @$(mktmp $(CFLAGS)) -c $<
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\)
+
+# Implicit rule for building a library file using response file
+%$L: ;
+    @$(RM) $@
+    $(LIBR) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n)
+
+# Implicit rule for building an executable file using response file
+%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tde c0l.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(EXELIBS))
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bc32.mk
new file mode 100755
index 0000000..e3ce25b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/bc32.mk
@@ -0,0 +1,151 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+.IF $(USE_VXD)
+
+# Implicit rule generation to build VxD's
+
+%$O: %.c ;
+	$(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\)
+	@$(VTOOLSD)\bin\segalias.exe -p $(VTOOLSD)\include\default.seg $@
+
+%$O: %$P ;
+	$(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\)
+	@$(VTOOLSD)\bin\segalias.exe -p $(VTOOLSD)\include\default.seg $@
+
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+
+%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n)
+
+%.dll: ;
+	@$(CP) $(mktmp EXPORTS\n_The_DDB @1) $*.def
+	tlink32.exe @$(mktmp $(LDFLAGS) -Tpd $(VTOOLSD:s/\/\\)\lib\icrtbc4.obj+\n$(&:s/\/\\)\n$*.dll\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS:s/\/\\)\n$*.def)
+	@$(RM) -S $(mktmp $*.def)
+
+%.vxd: %.dll ;
+	@$(CP) $(mktmp DYNAMIC\nATTRIB ICODE INIT\nATTRIB LCODE LOCKED\nATTRIB PCODE PAGEABLE\nATTRIB SCODE STATIC\nATTRIB DBOCODE DEBUG\nMERGE ICODE INITDAT0 INITDATA) $*.pel
+	@$(VTOOLSD)\bin\vxdver.exe $*.vrc $*.res
+	@$(VTOOLSD)\bin\pele.exe -d -s $*.smf -c $*.pel -o $@ -k 400 $*.dll
+	@$(VTOOLSD)\bin\sethdr.exe -n $* -x $@ -r $*.res
+.IF $(DBG)
+	$(NMSYM) /TRANS:source,package /SOURCE:$(VXDSOURCE) $*.smf
+.ENDIF
+	@$(RM) -S $(mktmp $*.pel)
+
+.ELSE
+
+# Implicit generation rules for making object files, libraries and exe's
+
+%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\)
+%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\)
+.IF $(USE_NASM)
+%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+.IF $(IMPORT_DLL)
+.ELSE
+.IF $(NO_RUNTIME)
+%$D: ; $(LD) $(mktmp $(LDFLAGS) -Tpd -aa $(&:s/\/\\)\n$@\n$*.map\n$(EXELIBS)\n$*.def)
+.ELSE
+%$D: ;
+	makedef $(@:b)
+	$(LD) $(mktmp $(LDFLAGS) -Tpd -aa c0d32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def)
+.IF $(DBG)
+.IF $(USE_SOFTICE)
+	$(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@
+	tdstrp32 $@
+.ENDIF
+.ENDIF
+.ENDIF
+.ENDIF
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ $?
+.ELIF $(IMPORT_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ $?
+.ELSE
+%$L: ;
+    @$(RM) $@
+    $(LIB) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+
+.IF $(USE_WIN32)
+.IF $(WIN32_GUI)
+%$E: ;
+	$(LD) $(mktmp $(LDFLAGS) -Tpe -aa $(WIN_VERSION) c0w32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def)
+.IF $(DBG)
+.IF $(USE_SOFTICE)
+	$(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@
+	tdstrp32 $@
+.ENDIF
+.ENDIF
+.ELSE
+%$E: ;
+	$(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def)
+.IF $(USE_SOFTICE)
+	$(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@
+	tdstrp32 $@
+.ENDIF
+.ENDIF
+.ELIF $(USE_TNT)
+%$E: ;
+	@$(CP) $(mktmp stub 'gotnt.exe') $*.def
+	@$(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def)
+.IF $(DOSSTYLE)
+	@markphar $@
+.ENDIF
+	@$(RM) -S $(mktmp $*.def)
+.ELIF $(USE_SMX32)
+%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def)
+.ELSE
+%$E: ; $(LD) $(mktmp $(LDFLAGS) -Tpe -ap c0x32.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS) $(PMLIB:s/\/\\) $(EXELIBS)\n$*.def)
+.END
+
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/bcos2.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/bcos2.mk
new file mode 100755
index 0000000..f473fec
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/bcos2.mk
@@ -0,0 +1,70 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\)
+%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) -c $(<:s,/,\)
+.IF $(USE_NASM)
+%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+%$D: ;
+	makedef $(@:b)
+	$(LD) $(mktmp $(LDFLAGS) -Tod -aa c02d.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(EXELIBS)\n$*.def)
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ $?
+.ELIF $(IMPORT_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ $?
+.ELSE
+%$L: ;
+    @$(RM) $@
+    $(LIB) $(LIBFLAGS) $@ @$(mktmp +$(&:t" &\n+")\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+
+.IF $(USE_OS2GUI)
+%$E: ; $(LD) $(mktmp $(LDFLAGS) -Toe -aa c02.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(EXELIBS)\n$*.def)
+.ELSE
+%$E: ; $(LD) $(mktmp $(LDFLAGS) -Toe -ap c02.obj+\n$(&:s/\/\\)\n$@\n$*.map\n$(DEF_LIBS:s/\/\\) $(EXELIBS)\n$*.def)
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/cl16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/cl16.mk
new file mode 100755
index 0000000..6489a3e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/cl16.mk
@@ -0,0 +1,67 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) /nologo $(CFLAGS) /c $<
+%$O: %$P ; $(CC) /nologo $(CFLAGS) /c $<
+%$O: %$A ; $(AS) $(ASFLAGS) $< $* NUL NUL
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+#%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS:s/\/\\) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS))
+#%$D: ; $(LD) $(LDFLAGS) /Fe$@ $& $(EXELIBS)
+%$D: ;  link @default.rsp
+
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L:      ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELIF $(IMPORT_DLL)
+%$L:      ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELSE
+%$L: ; $(LIB) /nologo $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+") &\n,,\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_WIN16)
+#%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS))
+%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS))
+.ELSE
+%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS))
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/cl386.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/cl386.mk
new file mode 100755
index 0000000..f50b274
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/cl386.mk
@@ -0,0 +1,69 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) -nologo $(CFLAGS) -c $<
+%$O: %$P ; $(CC) -nologo $(CFLAGS) -c $<
+%$O: %$A ; $(AS) $(ASFLAGS) $< $* NUL NUL
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+#%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS:s/\/\\) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS))
+#%$D: ; $(LD) $(LDFLAGS) /Fe$@ $& $(EXELIBS)
+%$D: ;  link386 @default.rsp
+
+# Implicit rule for building a device driver using a response file
+%.SYS: ;  link386 @default.rsp
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L:      ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELIF $(IMPORT_DLL)
+%$L:      ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELSE
+%$L: ; $(LIB) /nologo $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+") &\n,,\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_WIN16)
+#%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS))
+%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS))
+.ELSE
+%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS))
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/dj32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/dj32.mk
new file mode 100755
index 0000000..9f917bb
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/dj32.mk
@@ -0,0 +1,47 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\) -c) $(<:s,/,\)
+%$O: %$P ; $(CC) @$(mktmp $(CFLAGS:s/\/\\) -c) $(<:s,/,\)
+%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+
+# Implicit rule for building a library file using response file
+%$L:      ; $(LIB) $(LIBFLAGS) $@ @$(mktmp $(&:s/\/\\)\n)
+
+# Implicit rule for building an executable file using response file
+%$E:      ; $(LD) $(LDFLAGS) $@ @$(mktmp $(&:s/\/\\) $(EXELIBS) $(PMLIB) -lstdcxx -lm)
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/emx.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/emx.mk
new file mode 100755
index 0000000..26d223a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/emx.mk
@@ -0,0 +1,91 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#               OS/2 version for EMX/GNU C/C++.
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ;
+.IF $(SHOW_ARGS)
+	$(CC) -c $(CFLAGS) $(<:s,\,/)
+.ELSE
+	@echo $(CC) -c $(<:s,\,/)
+	@$(CC) -c $(CFLAGS) $(<:s,\,/)
+.ENDIF
+
+%$O: %$P ;
+.IF $(SHOW_ARGS)
+	$(CXX) -c $(CFLAGS) $(<:s,\,/)
+.ELSE
+	@echo $(CXX) -c $(<:s,\,/)
+	@$(CXX) -c $(CFLAGS) $(<:s,\,/)
+.ENDIF
+
+%$O: %$A ;
+.IF $(USE_NASM)
+.IF $(SHOW_ARGS)
+	$(AS) -o $@ $(ASFLAGS) $(<:s,\,/)
+.ELSE
+	@echo $(AS) $(<:s,\,/)
+	@$(AS) @$(mktmp -o $@ $(ASFLAGS)) $(<:s,\,/)
+.ENDIF
+.ELSE
+.IF $(SHOW_ARGS)
+
+    $(AS)  @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+	@echo $(AS) $(<:s,/,\)
+    $(AS)  @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+.ENDIF
+
+# Implicit rule for building a library file using response file
+%$L:     ;
+.IF $(SHOW_ARGS)
+	$(LIB) $(LIBFLAGS) $@ $(&:s,\,/)
+.ELSE
+	@echo $(LIB) $@
+	@$(LIB) $(LIBFLAGS) $@ @$(mktmp $(?:t"\n"))
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+%$E:     ;
+.IF $(SHOW_ARGS)
+	$(LD) $(LDFLAGS) -o $@ $(&:s,\,/) $(EXELIBS) $(PMLIB) -lgpp -lstdcpp
+.ELSE
+	@echo $(LD) $@
+	@$(LD) $(LDFLAGS) -o $@ $(&:s,\,/) $(EXELIBS) $(PMLIB) -lgpp -lstdcpp
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_beos.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_beos.mk
new file mode 100755
index 0000000..681b698
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_beos.mk
@@ -0,0 +1,47 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files from source files
+%$O: %.c ; $(CC) $(CFLAGS) -c $<
+%$O: %$P ; $(CXX) $(CFLAGS) -c $<
+%$O: %$A ; $(AS) $(ASFLAGS) $<
+
+# Implicit rule for building a library file
+%$L:     ; $(LIB) $(LIBFLAGS) $@ $&
+
+# Implicit rule for building an executable file
+%$E:     ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB)
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_freebsd.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_freebsd.mk
new file mode 100755
index 0000000..9b4d236
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_freebsd.mk
@@ -0,0 +1,47 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files from source files
+%$O: %.c ; $(CC) $(CFLAGS) -c $<
+%$O: %$P ; $(CXX) $(CFLAGS) -c $<
+%$O: %$A ; $(AS) -o $@ $(ASFLAGS) $<
+
+# Implicit rule for building a library file
+%$L:     ; $(LIB) $(LIBFLAGS) $@ $&
+
+# Implicit rule for building an executable file
+%$E:     ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_linux.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_linux.mk
new file mode 100755
index 0000000..5f91fe5
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_linux.mk
@@ -0,0 +1,93 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+.IF $(USE_CXX_LINKER)
+LD	:= $(LDXX)
+.ENDIF
+
+# Implicit generation rules for making object files from source files
+%$O: %.c ;
+.IF $(SHOW_ARGS)
+    $(CC) -c $(CFLAGS) $<
+.ELSE
+    @$(ECHO) $(CC) $(SHOW_CFLAGS) $<
+    @$(CC) -c $(CFLAGS) $<
+.ENDIF
+
+%$O: %$P ;
+.IF $(SHOW_ARGS)
+    $(CXX) -c $(CFLAGS) $<
+.ELSE
+    @$(ECHO) $(CXX) $(SHOW_CFLAGS) $<
+    @$(CXX) -c $(CFLAGS) $<
+.ENDIF
+
+%$O: %$A ;
+.IF $(SHOW_ARGS)
+    $(AS) -o $@ $(ASFLAGS) $<
+.ELSE
+    @$(ECHO) $(AS) $(SHOW_ASFLAGS) $<
+    @$(AS) @$(mktmp -o $@ $(ASFLAGS)) $<
+.ENDIF
+
+# Implicit rule for building a library file
+.IF $(BUILD_DLL)
+%$L:     ;
+.IF $(SHOW_ARGS)
+    $(LIB) $(LIBFLAGS) -Wl,-soname,$@.$(VERSIONMAJ) -o $@ $& $(LIBS)
+.ELSE
+    @$(ECHO) $(LIB) $@
+    @$(LIB) $(LIBFLAGS) -Wl,-soname,$@.$(VERSIONMAJ) -o $@ $& $(LIBS)
+.ENDIF
+.ELSE
+%$L:     ;
+.IF $(SHOW_ARGS)
+    $(LIB) $(LIBFLAGS) $@ $&
+.ELSE
+    @$(ECHO) $(LIB) $@
+    @$(LIB) $(LIBFLAGS) $@ $&
+.ENDIF
+.ENDIF
+
+# Implicit rule for building an executable file
+%$E:     ;
+.IF $(SHOW_ARGS)
+    $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm
+.ELSE
+    @$(ECHO) ld $@
+    @$(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_win32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_win32.mk
new file mode 100755
index 0000000..485d166
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/gcc_win32.mk
@@ -0,0 +1,90 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+.IF $(USE_CXX_LINKER)
+LD	:= $(LDXX)
+.ENDIF
+
+# Implicit generation rules for making object files from source files
+%$O: %.c ;
+.IF $(SHOW_ARGS)
+    $(CC) -c $(CFLAGS:s/\/\\) $(<:s,/,\)
+.ELSE
+    @$(ECHO) $(CC) $(SHOW_CFLAGS:s/\/\\) $(<:s,/,\)
+    @$(CC) -c $(CFLAGS:s/\/\\) $(<:s,/,\)
+.ENDIF
+
+%$O: %$P ;
+.IF $(SHOW_ARGS)
+    $(CXX) -c $(CFLAGS:s/\/\\) $(<:s,/,\)
+.ELSE
+    @$(ECHO) $(CXX) $(SHOW_CFLAGS:s/\/\\) $(<:s,/,\)
+    @$(CXX) -c $(CFLAGS:s/\/\\) $(<:s,/,\)
+.ENDIF
+
+%$O: %$A ;
+.IF $(SHOW_ARGS)
+    $(AS) -o $(ASFLAGS:s/\/\\) $(<:s,/,\)
+.ELSE
+    @$(ECHO) $(AS) $(SHOW_ASFLAGS:s/\/\\) $(<:s,/,\)
+    @$(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $< $(RCFLAGS) -o $@
+
+# Implicit rule for building a DLL
+# TODO!
+#%$D: ; +rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS))
+
+# Implicit rule for building a library file
+%$L:     ;
+.IF $(SHOW_ARGS)
+    $(LIB) $(LIBFLAGS) $@ $&
+.ELSE
+    @$(ECHO) $(LIB) $@
+    @$(LIB) $(LIBFLAGS) $@ @$(mktmp $(&:s/\/\\)\n)
+.ENDIF
+
+# Implicit rule for building an executable file
+%$E:     ;
+.IF $(SHOW_ARGS)
+    $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) -lm
+.ELSE
+    @$(ECHO) ld $@
+    @$(LD) $(LDFLAGS) -o $@ @$(mktmp $(&:s/\/\\) $(EXELIBS) $(PMLIB) -lm)
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/hc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/hc32.mk
new file mode 100755
index 0000000..011e9ab
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/hc32.mk
@@ -0,0 +1,51 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) $(CFLAGS) -c $<
+%$O: %$P ; $(CC) $(CFLAGS) -c $<
+.IF $(USE_NASM)
+%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+
+# Implicit rule for building a library file using response file
+%$L:      ; $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp -R $?)
+
+# Implicit rule for building an executable file using response file
+%$E:      ; $(LD) $(LDFLAGS) -o $@ @$(mktmp $(&:s/\/\\) $(PMLIB) $(EXELIBS) -ldosx32.lib)
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/qnx4.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/qnx4.mk
new file mode 100755
index 0000000..55dc035
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/qnx4.mk
@@ -0,0 +1,94 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Whether to link in real VBIOS library, or just the stub library
+
+.IF $(USE_BIOS)
+VBIOSLIB := -lvbios.lib
+.ELSE
+VBIOSLIB := -lvbstubs.lib
+.END
+
+# Require special privledges for Nucleus programs (requires root access)
+
+.IF $(USE_NUCLEUS)
+LDFLAGS		+= -T1
+.ENDIF
+
+# Implicit generation rules for making object files from source files
+%$O: %.c ;
+.IF $(SHOW_ARGS)
+    $(CC) $(CFLAGS) $<
+.ELSE
+    @echo $(CC) -c $<
+	+@$(CC) $(CFLAGS) $< > /dev/null
+.ENDIF
+
+%$O: %$P ;
+.IF $(SHOW_ARGS)
+	$(CXX) $(CFLAGS) $<
+.ELSE
+	@echo $(CXX) -c $<
+	+@$(CXX) $(CFLAGS) $< > /dev/null
+.ENDIF
+
+%$O: %$A ;
+.IF $(SHOW_ARGS)
+    $(AS) -o $@ $(ASFLAGS) $<
+.ELSE
+    @echo $(AS) $<
+	@$(AS) -o $@ $(ASFLAGS) $<
+.ENDIF
+
+# Implicit rule for building a library file
+%$L:     ;
+.IF $(SHOW_ARGS)
+    $(LIB) $(LIBFLAGS) -q $@ $&
+.ELSE
+    @echo $(LIB) $@
+	+@$(LIB) $(LIBFLAGS) -q $@ $& > /dev/null
+.ENDIF
+
+
+# Implicit rule for building an executable file
+%$E:     ;
+.IF $(SHOW_ARGS)
+	$(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB)
+.ELSE
+	@echo wlink $@
+	+@$(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB) > /dev/null
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/qnxnto.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/qnxnto.mk
new file mode 100755
index 0000000..c43ad1f
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/qnxnto.mk
@@ -0,0 +1,55 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Whether to link in real VBIOS library, or just the stub library
+
+.IF $(USE_BIOS)
+VBIOSLIB := -lvbios
+.ELSE
+VBIOSLIB := -lvbstubs
+.END
+
+# Implicit generation rules for making object files from source files
+%$O: %.c ; $(CC) $(CFLAGS) -c $<
+%$O: %$P ; $(CXX) $(CPPFLAGS) -c $<
+%$O: %$A ; $(AS) -o $@ $(ASFLAGS) $<
+
+# Implicit rule for building a library file
+%$L:     ; $(LIB) $(LIBFLAGS) $@ $&
+
+# Implicit rule for building an executable file
+%$E:     ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB)
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk
new file mode 100755
index 0000000..b33bcd8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk
@@ -0,0 +1,63 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) $(CFLAGS) -c $<
+%$O: %$P ; $(CC) $(CFLAGS) -c $<
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\)
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+%$D: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(EXELIBS))
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELIF $(IMPORT_DLL)
+%$L: ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELSE
+%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_WIN16)
+%$E: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(EXELIBS))
+.ELSE
+%$E: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(PMLIB) $(EXELIBS))
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk
new file mode 100755
index 0000000..2231906
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk
@@ -0,0 +1,69 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) $(CFLAGS) -c $<
+%$O: %$P ; $(CC) $(CFLAGS) -c $<
+.IF $(USE_NASM)
+%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+%$D: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(EXELIBS) kernel32.lib user32.lib gdi32.lib winmm.lib comdlg32.lib advapi32.lib)
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELIF $(IMPORT_DLL)
+%$L: ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELSE
+%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_TNT)
+%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(PMLIB) $(EXELIBS))
+.ELIF $(USE_WIN32)
+%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(EXELIBS) kernel32.lib user32.lib gdi32.lib winmm.lib comdlg32.lib advapi32.lib)
+.ELSE
+%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(PMLIB) $(EXELIBS))
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk
new file mode 100755
index 0000000..1a20319
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk
@@ -0,0 +1,82 @@
+#############################################################################
+#
+#                                       SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#                               build targets. We include them here at the end of the
+#                               makefile so the generic project makefiles can override
+#                               certain things with macros (such as linking C++ programs
+#                               differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC)  -c @$(mktmp $(CFLAGS:s/\/\\))  $(<:s,/,\)
+%$O: %$P ; $(CPP) -c @$(mktmp $(CFLAGS:s/\/\\))  $(<:s,/,\)
+.IF $(USE_NASM)
+%$O: %$A ; $(AS)  @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+%$O: %$A ; $(AS)  @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building help files
+%.hlp: %.ipf; $(IPFC) $(IPFCFLAGS) $<
+
+# Implicit rule for building a DLL using a response file
+.IF $(USE_OS2GUI)
+%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n)
+.ELSE
+%$D: ; $(LD) /nofree /nol @$(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n)
+.ENDIF
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELIF $(IMPORT_DLL)
+%$L: ; $(ILIB) $(ILIBFLAGS) $@ $?
+.ELSE
+%$L: ; $(LIB) $(LIBFLAGS) @$(mktmp $@-+$(?:t"&\n-+":s/\/\\);)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_OS2GUI)
+%$E: ;
+	rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n)
+.IF $(LXLITE)
+	lxlite $@
+.ENDIF
+.ELSE
+%$E: ;
+	rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n\n)
+.IF $(LXLITE)
+	lxlite $@
+.ENDIF
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk
new file mode 100755
index 0000000..2b41801
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk
@@ -0,0 +1,79 @@
+#############################################################################
+#
+#                                       SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#                               build targets. We include them here at the end of the
+#                               makefile so the generic project makefiles can override
+#                               certain things with macros (such as linking C++ programs
+#                               differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) -c @$(mktmp $(CFLAGS:s/\/\\))  $(<:s,/,\)
+%$O: %$P ; $(CPP) -c @$(mktmp $(CFLAGS:s/\/\\))  $(<:s,/,\)
+.IF $(USE_NASM)
+%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+.IF $(USE_OS2GUI)
+%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n)
+.ELSE
+%$D: ; $(LD) /nofree /nol @$(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n)
+.ENDIF
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ; $(ILIB) $(ILIBFLAGS) /out:$@ $?
+.ELIF $(IMPORT_DLL)
+%$L: ; $(ILIB) $(ILIBFLAGS) /out:$@ $?
+.ELSE
+%$L: ; $(LIB) $(LIBFLAGS) /nowarn:86 /out:$@ @$(mktmp $(?:t"\n":s/\/\\))
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_OS2GUI)
+%$E: ;
+	rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n)
+.IF $(LXLITE)
+	lxlite $@
+.ENDIF
+.ELSE
+%$E: ;
+	rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n\n)
+.IF $(LXLITE)
+	lxlite $@
+.ENDIF
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk
new file mode 100755
index 0000000..6ffc270
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk
@@ -0,0 +1,70 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) /nologo $(CFLAGS) /c $<
+%$O: %$P ; $(CC) /nologo $(CFLAGS) /c $<
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\)
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS))
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ $?
+.ELIF $(IMPORT_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ $?
+.ELSE
+%$L: ;
+    @$(RM) $@
+    $(LIB) $@ /nologo $(LIBFLAGS) @$(mktmp +$(&:t" &\n+") &\n,\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_WIN16)
+%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS))
+#%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS))
+.ELSE
+%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS))
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk
new file mode 100755
index 0000000..97f1a0c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk
@@ -0,0 +1,122 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Turn on pre-compiled headers as neccessary
+.IF $(PRECOMP_HDR)
+   CFLAGS       += -YX"$(PRECOMP_HDR)"
+.ENDIF
+
+# Turn on runtime type information as necessary
+.IF $(USE_RTTI)
+	CFLAGS		+= /GR
+.ENDIF
+
+# Turn on C++ exception handling as necessary
+.IF $(USE_CPPEXCEPT)
+	CFLAGS		+= /GX
+.ENDIF
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) /nologo @$(mktmp $(CFLAGS:s/\/\\)) /c $(<:s,/,\)
+%$O: %$P ; $(CC) /nologo @$(mktmp $(CFLAGS:s/\/\\)) /c $(<:s,/,\)
+.IF $(USE_NASM)
+%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rules for building NT device drivers
+
+%.sys: ;
+	$(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS))
+.IF $(DBG)
+.IF $(USE_SOFTICE)
+	$(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@
+.ENDIF
+.ENDIF
+
+# Implicit rule for building a DLL using a response file
+.IF $(IMPORT_DLL)
+.ELSE
+.IF $(NO_RUNTIME)
+%$D: ; $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS))
+.ELSE
+%$D: ;
+	makedef -v $*
+	$(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS))
+.IF $(DBG)
+.IF $(USE_SOFTICE)
+	$(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@
+.ENDIF
+.ENDIF
+.ENDIF
+.ENDIF
+
+# Implicit rule for building a library file using response file. Note that
+# we use a special .VCD file that contains the EXPORT definitions for the
+# Microsoft compiler, since the LIB utility automatically adds leading
+# underscores to exported functions.
+.IF $(IMPORT_DLL)
+%$L: ;
+	makedef -v $(?:b)
+    @$(RM) $@
+	$(ILIB) $(ILIBFLAGS) /DEF:$(?:b).def /OUT:$@
+.ELSE
+%$L: ;
+    @$(RM) $@
+    $(LIB) $(LIBFLAGS) /out:$@ @$(mktmp $(&:t"\n")\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_WIN32)
+%$E: ;
+	$(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS))
+.IF $(DBG)
+.IF $(USE_SOFTICE)
+	$(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@
+.ENDIF
+.ENDIF
+.ELSE
+%$E: ;
+	@$(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS))
+.IF $(DOSSTYLE)
+	@markphar $@
+.ENDIF
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk
new file mode 100755
index 0000000..d1ca917
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk
@@ -0,0 +1,79 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Implicit generation rules for making object files
+%$O: %.c ; $(CC) @$(mktmp $(CFLAGS)) $<
+%$O: %$P ; $(CPP) @$(mktmp $(CFLAGS)) $<
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\)
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ +$?
+.ELIF $(IMPORT_DLL)
+%$L: ;
+    @$(RM) $@
+    $(ILIB) $(ILIBFLAGS) $@ +$?
+.ELSE
+%$L: ;
+    @$(RM) $@
+    $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp +$(&:t"\n+":s/\/\\)\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_WIN16)
+.IF $(BUILD_DLL)
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS windows_dll\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+	@$(RM) -S $(mktmp $*.lnk)
+.ELSE
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS windows\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+	@$(RM) -S $(mktmp $*.lnk)
+.ENDIF
+.ELSE
+%$E: ;
+	@trimlib $(mktmp OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB) $(EXELIBS:t",")) $*.lnk
+	$(LD) $(LDFLAGS) @$*.lnk
+	@$(RM) -S $(mktmp $*.lnk)
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk
new file mode 100755
index 0000000..39b8819
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk
@@ -0,0 +1,264 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Rules makefile definitions, which define the rules used to
+#				build targets. We include them here at the end of the
+#				makefile so the generic project makefiles can override
+#				certain things with macros (such as linking C++ programs
+#				differently).
+#
+#############################################################################
+
+# Take out PMLIB if we don't need to link with it
+
+.IF $(NO_PMLIB)
+PMLIB :=
+.ENDIF
+
+# Use a larger stack during linking if requested, or use a default stack
+# of 200k. The usual default stack provided by Watcom C++ is *way* to small
+# for real 32 bit code development. We also need a *huge* stack for OpenGL
+# software rendering also!
+.IF $(USE_QNX4)
+    # Not necessary for QNX code.
+.ELSE
+.IF $(STKSIZE)
+    LDFLAGS		+= OP STACK=$(STKSIZE)
+.ELSE
+	LDFLAGS		+= OP STACK=204800
+.ENDIF
+.ENDIF
+
+# Turn on runtime type information as necessary
+.IF $(USE_RTTI)
+	CPFLAGS		+= -xr
+.ENDIF
+
+# Optionally turn on pre-compiled headers
+.IF $(PRECOMP_HDR)
+	CFLAGS		+= -fhq
+.ENDIF
+
+.IF $(USE_QNX)
+# Whether to link in real VBIOS library, or just the stub library
+.IF $(USE_BIOS)
+VBIOSLIB := vbios.lib,
+.ELSE
+VBIOSLIB := vbstubs.lib,
+.END
+# Require special privledges for Nucleus programs (requires root access)
+.IF $(USE_NUCLEUS)
+LDFLAGS		+= OP PRIV=1
+.ENDIF
+.ENDIF
+
+# Implicit generation rules for making object files
+.IF $(WC_LIBBASE) == WC10A
+%$O: %.c ; $(CC) $(CFLAGS) $(<:s,/,\)
+%$O: %$P ; $(CPP) $(CFLAGS) $(<:s,/,\)
+.ELSE
+%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\)
+%$O: %$P ; $(CPP) @$(mktmp $(CPFLAGS:s/\/\\) $(CFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+.IF $(USE_NASM)
+%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\)
+.ENDIF
+
+# Implit rule to compile .S assembler files. The first version
+# uses GAS directly and the second uses a pre-processor to
+# produce NASM code.
+
+.IF $(USE_GAS)
+.IF $(WC_LIBBASE) == WC11
+%$O: %$S ; $(GAS) -c @$(mktmp $(GAS_FLAGS:s/\/\\)) $(<:s,/,\)
+.ELSE
+# Black magic to build asm sources with Watcom 10.6 (requires sed)
+%$O: %$S ;
+	$(GAS) -c @$(mktmp $(GAS_FLAGS:s/\/\\)) $(<:s,/,\)
+	wdisasm \\ -a $(*:s,/,\).o > $(*:s,/,\).lst
+	sed -e "s/\.text/_TEXT/; s/\.data/_DATA/; s/\.bss/_BSS/; s/\.386/\.586/; s/lar *ecx,cx/lar ecx,ecx/" $(*:s,/,\).lst > $(*:s,/,\).asm
+	wasm \\ $(WFLAGS) -zq -fr=nul -fp3 -fo=$@ $(*:s,/,\).asm
+	$(RM) -S $(mktmp $(*:s,/,\).o)
+	$(RM) -S $(mktmp $(*:s,/,\).lst)
+	$(RM) -S $(mktmp $(*:s,/,\).asm)
+.ENDIF
+.ELSE
+%$O: %$S ;
+	@gcpp -DNASM_ASSEMBLER -D__WATCOMC__ -EP $(<:s,/,\) > $(*:s,/,\).asm
+	nasm @$(mktmp -f obj -o $@) $(*:s,/,\).asm
+	@$(RM) -S $(mktmp $(*:s,/,\).asm)
+.ENDIF
+
+# Special target to build dllstart.asm using Borland TASM
+dllstart.obj: dllstart.asm
+	$(DLL_TASM) @$(mktmp /t /mx /m /D__FLAT__ /i$(SCITECH)\INCLUDE /q) $(PRIVATE)\src\common\dllstart.asm
+
+# Implicit rule for building resource files
+%$R: %.rc ; $(RC) $(RCFLAGS) -r $<
+
+# Implicit rule for building a DLL using a response file
+.IF $(IMPORT_DLL)
+.ELSE
+.IF $(USE_OS232)
+%$D: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2 dll\nN $@\nF $(&:t",\n":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ELIF $(USE_WIN32)
+%$D: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt_dll\nN $@\nF $(&:t",\n":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ELSE
+%$D: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS win386\nN $*.rex\nF $(&:t",\n":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+	wbind $* -d -q -n
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ENDIF
+.ENDIF
+
+# Implicit rule for building a library file using response file
+.IF $(BUILD_DLL)
+%$L: ;
+	@$(RM) $@
+	$(ILIB) $(ILIBFLAGS) $@ +$?
+.ELIF $(IMPORT_DLL)
+%$L: ;
+	@$(RM) $@
+	$(ILIB) $(ILIBFLAGS) $@ +$?
+.ELSE
+%$L: ;
+    @$(RM) $@
+    $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp +$(&:t"\n+":s/\/\\)\n)
+.ENDIF
+
+# Implicit rule for building an executable file using response file
+.IF $(USE_X32)
+%$E: ;
+	@trimlib $(mktmp OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk
+	$(LD) $(LDFLAGS) @$*.lnk
+	x32fix $@
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ELIF $(USE_OS232)
+.IF $(USE_OS2GUI)
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2_pm\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.IF $(LXLITE)
+ 	lxlite $@
+.ENDIF
+.ELSE
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.IF $(LXLITE)
+ 	lxlite $@
+.ENDIF
+.ENDIF
+.ELIF $(USE_SNAP)
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(DEFLIBS)$(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ELIF $(USE_WIN32)
+.IF $(WIN32_GUI)
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS win95\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ELSE
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk
+	rclink $(LD) $(RC) $@ $*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ENDIF
+.ELIF $(USE_WIN386)
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet SYS win386\nN $*.rex\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk
+	rclink $(LD) wbind $*.rex $*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ELIF $(USE_TNT)
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR dosx32.lib,tntapi.lib,$(PMLIB)$(EXELIBS:t",")) $*.lnk
+	$(LD) @$*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.IF $(DOSSTYLE)
+	@markphar $@
+.ENDIF
+.ELIF $(USE_QNX4)
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(VBIOSLIB)$(EXELIBS:t",")) $*.lnk
+	@+if exist $*.exe attrib -s $*.exe > NUL
+	$(LD) @$*.lnk
+	@attrib +s $*.exe
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ELSE
+%$E: ;
+	@trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk
+	$(LD) @$*.lnk
+.IF $(LEAVE_LINKFILE)
+.ELSE
+	@$(RM) -S $(mktmp *.lnk)
+.ENDIF
+.ENDIF
diff --git a/board/MAI/bios_emulator/scitech/makedefs/sc16.mk b/board/MAI/bios_emulator/scitech/makedefs/sc16.mk
new file mode 100755
index 0000000..099ad45
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/sc16.mk
@@ -0,0 +1,128 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Symantec C++ 6.x/7.x 16 bit version. Supports 16 bit DOS
+#               and 16 bit Windows development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : SC_LIBBASE
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := sc       # C-compiler and flags
+   CFLAGS       := -ml -Jm
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx    # Assembler and flags
+.ELSE
+   AS           := tasm     # Assembler and flags
+.ENDIF
+   ASFLAGS      := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE
+   LD           := sc       # Loader and flags
+   LDFLAGS       = $(CFLAGS)
+   RC           := rcc      # WIndows resource compiler
+   RCFLAGS      :=          # Mark as Win32 compatible resources
+   LIB          := lib      # Librarian
+   LIBFLAGS     := /N /B
+   ILIB         := implib   # Import librarian
+   ILIBFLAGS    :=
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g       # Turn on debugging for C compiler
+.ELSE
+   ASFLAGS      += /q       # Suppress object records not needed for linking
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += -5 -o+all
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -5 -o+space
+.END
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += -ff -DFPU387
+   ASFLAGS      += -DFPU387 -DFPU_REG_RTN
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -DBETA
+.END
+
+# User a larger stack if requested
+
+.IF $(STKSIZE)
+    LDFLAGS     += =$(STKSIZE)
+.ENDIF
+
+# Optionally compile for 16 bit Windows
+.IF $(USE_WIN16)
+.IF $(BUILD_DLL)
+   CFLAGS       += -WD -DBUILD_DLL
+   ASFLAGS      += -DBUILD_DLL
+.ELSE
+   CFLAGS       += -WA
+.ENDIF
+   DX_ASFLAGS   += -D__WINDOWS16__
+   LIB_OS       = WIN16
+.ELSE
+   USE_REALDOS	:= 1
+   LIB_OS       = DOS16
+.END
+
+# Place to look for PMODE library files
+
+PMLIB           := pm.lib
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(SC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK	:= sc16.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/sc32.mk b/board/MAI/bios_emulator/scitech/makedefs/sc32.mk
new file mode 100755
index 0000000..9ca7570
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/sc32.mk
@@ -0,0 +1,178 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Symantec C++ 6.x/7.x 32 bit version. Supports the DOSX
+#               extender, FlashTek X32 and Phar Lap's TNT DOS Extender
+#               and 32 bit Windows development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : USE_TNT USE_X32 USE_X32VM SC_LIBBASE
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := sc       # C-compiler and flags
+   CFLAGS       := -Jm
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx    # Assembler and flags
+.ELSE
+   AS           := tasm     # Assembler and flags
+.ENDIF
+.IF $(USE_WIN32)
+   ASFLAGS      := /t /mx /m /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.ELSE
+   ASFLAGS      := /t /mx /m /DES_NOT_DS /D__COMM__ /i$(SCITECH)\INCLUDE
+.ENDIF
+   LD           := sc       # Loader and flags
+   LD_FLAGS      =
+   RC           := rcc      # WIndows resource compiler
+   RCFLAGS      := -32      # Mark as Win32 compatible resources
+   LIB          := lib      # Librarian
+   LIBFLAGS     := /N /B
+   ILIB         := implib   # Import librarian
+   ILIBFLAGS    :=
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -g       # Turn on debugging for C compiler (FlashView)
+.IF $(USE_TNT)
+   LDFLAGS      += -fullsym # Turn on debugging for TNT 386link linker
+.END
+.IF $(USE_X32) or $(USE_X32VM)
+   LDFLAGS      += -L/map   # Turn on debugging for FlashView debugger
+.END
+.ELSE
+   ASFLAGS      += /q       # Suppress object records not needed for linking
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += -5 -o+all
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -5 -o+space
+.END
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += -ff -DFPU387
+   ASFLAGS      += -DFPU387 -DFPU_REG_RTN
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -DBETA
+.END
+
+# User a larger stack if requested
+
+.IF $(STKSIZE)
+    LDFLAGS     += =$(STKSIZE)
+.ENDIF
+
+.IF $(USE_TNT)                  # Use Phar Lap's TNT DOS Extender
+   CFLAGS       += -mp
+   DX_CFLAGS    += -DTNT
+   ASFLAGS      += /D__FLAT__
+   DX_ASFLAGS   += -DTNT
+   LD           := 386link
+   LDFLAGS      += @sc32.dos -exe $@
+   LIB_OS       = DOS32
+.ELIF $(USE_X32VM)              # Use FlashTek X-32VM DOS extender
+   CFLAGS       += -mx
+   DX_CFLAGS    += -DX32VM
+   ASFLAGS      += /D__X386__
+   DX_ASFLAGS   += -DX32VM
+   LD           := sc
+   LDFLAGS      += $(CFLAGS) x32v.lib
+   LIB_OS       = DOS32
+.ELIF $(USE_X32)                # Use FlashTek X-32 DOS extender
+   CFLAGS       += -mx
+   DX_CFLAGS    += -DX32VM
+   ASFLAGS      += /D__X386__
+   DX_ASFLAGS   += -DX32VM
+   LD           := sc
+   LDFLAGS      += $(CFLAGS) x32.lib
+   LIB_OS       = DOS32
+.ELIF $(USE_WIN32)              # Build 32 bit Windows NT app
+.IF $(BUILD_DLL)
+   CFLAGS       += -WD -mn
+   ASFLAGS      += -DBUILD_DLL
+.ELSE
+   CFLAGS       += -WA -mn
+.ENDIF
+   DX_ASFLAGS   += -D__WINDOWS32__
+   LIB_OS       = WIN32
+.ELSE                           # Use default Symantec DOSX extender
+   USE_DOSX     := 1
+   USE_REALDOS	:= 1
+   CFLAGS       += -mx
+   DX_CFLAGS    += -DDOSX
+   ASFLAGS      += /D__X386__
+   DX_ASFLAGS   += -DDOSX
+   LD           := sc
+   LDFLAGS      += $(CFLAGS)
+   LIB_OS       = DOS32
+.END
+
+# Place to look for PMODE library files
+
+.IF $(USE_TNT)
+PMLIB           := tnt\pm.lib
+.ELIF $(USE_X32)
+PMLIB           := x32\pm.lib
+.ELSE
+PMLIB           := dosx\pm.lib
+.END
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(SC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK	:= sc32.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/startup.mk b/board/MAI/bios_emulator/scitech/makedefs/startup.mk
new file mode 100755
index 0000000..d8b2ba2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/startup.mk
@@ -0,0 +1,161 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Common startup script that defines all variables common to
+#				all startup scripts. These define the DMAKE runtime
+#				environment and the values are dependant on the version of
+#				DMAKE in use.
+#
+#############################################################################
+
+# Disable warnings for macros redefined here that were given
+# on the command line.
+__.SILENT       := $(.SILENT)
+.SILENT         := yes
+
+# Import enivornment variables that we use common to all compilers
+.IMPORT .IGNORE : TEMP SHELL COMSPEC INCLUDE LIB SCITECH PRIVATE SCITECH_LIB
+.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA USE_WIN32 FPU BUILD_DLL BUILD_FOR_DLL
+.IMPORT .IGNORE : IMPORT_DLL USE_TASMX WIN32_GUI USE_WIN16 USE_NASM CHECKED
+.IMPORT .IGNORE : OS2_SHELL SOFTICE_PATH MAX_WARN USE_SOFTICE USE_TASM32
+.IMPORT .IGNORE : DLL_START_TASM USE_SNAP USE_X11 USE_LINUX STATIC_LIBS LIBC
+.IMPORT .IGNORE : SHOW_ARGS BOOT_STRAP_DMAKE
+   TMPDIR := $(TEMP)
+
+# Determine if the host machine is a Windows/DOS or Unix box
+.IF $(COMSPEC)
+   WIN32_HOST   := 1
+.ELSE
+   USE_NASM     := 1
+   UNIX_HOST    := 1
+.ENDIF
+
+# Setup to either user NASM or TASM as the assembler
+.IF $(USE_NASM)
+.ELSE
+   USE_TASM		:= 1
+.ENDIF
+
+.IF $(UNIX_HOST)
+# Standard file suffix definitions
+#
+# NOTE: Linux/Unix does not require any extenion for executeable files, but you
+#       can use an extension if you wish. We use the .exe extension for building
+#       executeable files so that we can use implicit rules to make the
+#       makefiles simpler and more portable between systems (exe also makes it
+#       easier for cross-compile/debugging situations). When you install
+#       the files to a local bin directory, you will probably want to remove
+#       the .exe extension.
+   L            := .a   	# Libraries
+   E            := .exe   	# Executables for glibc
+   O            := .o   	# Objects
+   A            := .asm   	# Assembler sources
+   S            := .s       # GNU assembler sources
+   P            := .cpp   	# C++ sources
+
+# File prefix/suffix definitions. The following prefixes are defined, and are
+# used primarily to abstract between the Unix style libXX.a naming convention
+# and the DOS/Windows/OS2 naming convention of XX.lib.
+   LP           := lib      # LP - Library file prefix (name of file on disk)
+   LL           := -l		# Library link prefix (name of library on link command line)
+   LE           := 		    # Library link suffix (extension of library on link command line)
+
+# We use the Unix shell at all times
+   SHELL		:= /bin/sh
+   SHELLFLAGS   := -c
+
+.ELSE
+# Standard file DOS/Win/OS2 suffix definitions
+   L            := .lib   	# Libraries
+.IF $(USE_SNAP)
+   E            := .sxe   	# Snap Executables
+   D            := .sll  	# Snap Dynamic Link Library file
+.ELSE
+   E            := .exe   	# Executables
+   D            := .dll   	# Dynamic Link Library file
+.ENDIF
+   O            := .obj   	# Objects
+   A            := .asm   	# Assembler sources
+   P            := .cpp   	# C++ sources
+   R            := .res   	# Compiled resource file
+   S			:= .s		# Assyntax.h style assembler
+
+# File prefix/suffix definitions. The following prefixes are defined, and are
+# used primarily to abstract between the Unix style libXX.a naming convention
+# and the DOS/Windows/OS2 naming convention of XX.lib.
+   LP           := 			# LP - Library file prefix (name of file on disk)
+   LL           := 			# Library link prefix (name of library on link command line)
+   LE           := .lib		# Library link suffix (extension of library on link command line)
+
+# We use the DOS/Win/OS2 style shell at all times
+   SHELL        := $(COMSPEC)
+   GROUPSHELL   := $(SHELL)
+   SHELLFLAGS   := $(SWITCHAR)c
+   GROUPFLAGS   := $(SHELLFLAGS)
+   SHELLMETAS   := *"?<>
+.IF $(OS2_SHELL)
+   GROUPSUFFIX  := .cmd
+.ELSE
+   GROUPSUFFIX  := .bat
+.ENDIF
+   DIRSEPSTR    := \\
+   DIVFILE       = $(TMPFILE:s,/,\)
+
+.ENDIF
+
+# Standard Unix style shell commands. Since these do not exist on
+# regular DOS/Win/OS2 installations we use our own '' versions
+# instead. To boostrtap a new OS you may wish to use the regular
+# unix versions.
+
+.IF $(BOOT_STRAP_DMAKE)
+   CP			:= cp
+   MD			:= mkdir
+   RM			:= rm
+   ECHO			:= echo
+.ELSE
+   CP			:= k_cp
+   MD			:= k_md
+   RM			:= k_rm
+   ECHO			:= k_echo
+.ENDIF
+
+# Definition of $(MAKE) macro for recursive makes.
+   MAKE = $(MAKECMD) $(MFLAGS)
+
+# Macro to install a library file
+   INSTALL      := $(CP)
+
+# DMAKE uses this recipe to remove intermediate targets
+.REMOVE :; $(RM) -f $<
+
+# Turn warnings back to previous setting.
+.SILENT := $(__.SILENT)
+
+# We dont use TABS in our makefiles
+.NOTABS         := yes
diff --git a/board/MAI/bios_emulator/scitech/makedefs/va32.mk b/board/MAI/bios_emulator/scitech/makedefs/va32.mk
new file mode 100755
index 0000000..fbca523
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/va32.mk
@@ -0,0 +1,163 @@
+#############################################################################
+#
+#                                       SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               IBM VisualAge C++ 3.0 OS/2 32-bit version.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : VA_LIBBASE USE_OS232 USE_OS2GUI FULLSCREEN NOOPT MAX_WARN
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := icc
+   CPP          := icc
+   CFLAGS       := /Q /G5 /Gl+ /Fi /Si /J- /Ss+ /Sp1 /Gm+ /I.
+.IF $(USE_NASM)
+   AS           := nasm
+   ASFLAGS      := -t -f obj -F null -d__FLAT__ -dSTDCALL_MANGLE -d__NOU_VAR__ -iINCLUDE -i$(SCITECH)\INCLUDE
+.ELSE
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx
+.ELSE
+   AS           := tasm
+.ENDIF
+   ASFLAGS      := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.ENDIF
+   LD           := ilink
+   LDFLAGS       = /noi /exepack:2 /packcode /packdata /align:32 /map /noe
+   RC           := rc
+   RCFLAGS      := -n -x2
+   LIB          := ilib
+   LIBFLAGS     := /nologo
+   ILIB         := implib
+   ILIBFLAGS    := /nologo
+   IPFC         := ipfc
+   IPFCFLAGS    :=
+   IBMCOBJ      := 1
+
+# Set the compiler warning level
+.IF $(MAX_WARN)
+   CFLAGS       += /W3
+.ELSE
+   CFLAGS       += /W1
+.ENDIF
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += /Ti
+   LDFLAGS      += /DE
+.ELSE
+.IF $(USE_TASM)
+   ASFLAGS      += /q
+.ENDIF
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += /Gfi /O /Oi
+.ELIF $(OPT_SIZE)
+   CFLAGS       += /Gfi /O /Oc
+.ELIF $(NOOPT)
+   CFLAGS       += /O-
+.END
+
+# Optionally turn on direct i387 FPU instructions optimised for Pentium
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.END
+
+# Build 32-bit OS/2 apps
+.IF $(BUILD_DLL)
+   CFLAGS       += /Ge- /DBUILD_DLL
+   LDFLAGS      += /DLL /NOE
+   ASFLAGS      += -dBUILD_DLL
+.ELSE
+.IF $(USE_OS2GUI)
+   CFLAGS       += -D__OS2_PM__
+   LDFLAGS      += /PMTYPE:PM
+.ELSE
+.IF $(FULLSCREEN)
+   LDFLAGS      += /PMTYPE:NOVIO
+.ELSE
+   LDFLAGS      += /PMTYPE:VIO
+.ENDIF
+.ENDIF
+.ENDIF
+   DX_ASFLAGS   += -d__OS2__
+   LIB_OS       = os232
+
+# Place to look for PMODE library files
+
+.IF $(USE_OS2GUI)
+.IF $(USE_SDDPMDLL)
+#Note: This is OK for now but might need to be changed if the GUI PM library
+#      were really different
+PMLIB           := sddpmlib.lib
+.ELSE
+PMLIB           := pm_pm.lib
+.ENDIF
+.ELSE
+.IF $(USE_SDDPMDLL)
+PMLIB           := sddpmlib.lib
+.ELSE
+PMLIB           := pm.lib
+.ENDIF
+.ENDIF
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR    := $(SCITECH_LIB)\lib\debug
+CFLAGS          += /DCHECKED=1
+.ELSE
+LIB_BASE_DIR    := $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(VA_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK    := va32.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/va365.mk b/board/MAI/bios_emulator/scitech/makedefs/va365.mk
new file mode 100755
index 0000000..3a2eccb
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/va365.mk
@@ -0,0 +1,151 @@
+#############################################################################
+#
+#  					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               IBM VisualAge C++ 3.65 OS/2 32-bit version.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : VA_LIBBASE USE_OS232 USE_OS2GUI FULLSCREEN NOOPT MAX_WARN
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := icc
+   CPP          := icc
+   CFLAGS       := /Q /G5l /Fi /Si /J- /Ss+ /Sp1 /Gm+ /I.
+.IF $(USE_NASM)
+   AS           := nasm
+   ASFLAGS      := -t -f obj -F null -d__FLAT__ -dSTDCALL_MANGLE -d__NOU_VAR__ -iINCLUDE -i$(SCITECH)\INCLUDE
+.ELSE
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx
+.ELSE
+   AS           := tasm
+.ENDIF
+   ASFLAGS      := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE
+.ENDIF
+   LD           := ilink
+   LDFLAGS       = /noi /exepack /packcode /packdata /align:32 /map /noe
+   RC           := rc
+   RCFLAGS      := /nologo
+   LIB          := ilib
+   LIBFLAGS     := /nologo
+   ILIB         := implib
+   ILIBFLAGS    := /nologo
+   IBMCOBJ      := 1
+
+# Set the compiler warning level
+.IF $(MAX_WARN)
+   CFLAGS       += /W3
+.ELSE
+   CFLAGS       += /W1
+.ENDIF
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += /Ti
+   LDFLAGS      += /DE
+.ELSE
+.IF $(USE_TASM)
+   ASFLAGS      += /q
+.ENDIF
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += /Gfi /O /Oi
+.ELIF $(OPT_SIZE)
+   CFLAGS       += /Gfi /O /Oc
+.ELIF $(NOOPT)
+   CFLAGS       += /O-
+.END
+
+# Optionally turn on direct i387 FPU instructions optimised for Pentium
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.END
+
+# Build 32-bit OS/2 apps
+.IF $(BUILD_DLL)
+   CFLAGS       += /Gme- /DBUILD_DLL
+   LDFLAGS      += /DLL /NOE
+   ASFLAGS      += -dBUILD_DLL
+.ELSE
+.IF $(USE_OS2GUI)
+   CFLAGS       += -D__OS2_PM__
+   LDFLAGS      += /PMTYPE:PM
+.ELSE
+.IF $(FULLSCREEN)
+   LDFLAGS      += /PMTYPE:NOVIO
+.ELSE
+   LDFLAGS      += /PMTYPE:VIO
+.ENDIF
+.ENDIF
+.ENDIF
+   DX_ASFLAGS   += -d__OS2__
+   LIB_OS       = os232
+
+# Place to look for PMODE library files
+
+.IF $(USE_OS2GUI)
+PMLIB           := pm_pm.lib
+.ELSE
+PMLIB           := pm.lib
+.ENDIF
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR    := $(SCITECH_LIB)\lib\debug
+CFLAGS          += /DCHECKED=1
+.ELSE
+LIB_BASE_DIR    := $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(VA_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK    := va365.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/vc16.mk b/board/MAI/bios_emulator/scitech/makedefs/vc16.mk
new file mode 100755
index 0000000..913bf9c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/vc16.mk
@@ -0,0 +1,128 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Microsoft Visual C++ 1.x 16 bit version. Supports 16 bit
+#               DOS and Windows development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : VC_LIBBASE
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := cl       # C-compiler and flags
+   CFLAGS       := /YX /w /G3 /Gs
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx    # Assembler and flags
+.ELSE
+   AS           := tasm     # Assembler and flags
+.ENDIF
+   ASFLAGS      := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE
+   LD           := cl       # Loader and flags
+   LDFLAGS       = $(CFLAGS)
+   RC           := rc       # WIndows resource compiler
+   RCFLAGS      :=
+   LIB          := lib      # Librarian
+   LIBFLAGS     := /NOI /NOE
+   ILIB         := implib   # Import librarian
+   ILIBFLAGS    := /noignorecase
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += /Yd /Zi  # Turn on debugging for C compiler
+   ASFLAGS      += /zi      # Turn on debugging for assembler
+.ELSE
+   ASFLAGS      += /q       # Suppress object records not needed for linking
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += /Ox
+.END
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += /FPi87 /DFPU387
+   ASFLAGS      += /DFPU387 /DFPU_REG_RTN
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += /DBETA
+   ASFLAGS      += /DBETA
+.END
+
+# Use a larger stack during linking if requested ???? How the fuck do you
+# specify linker options on the CL command line?????
+
+.IF $(STKSIZE)
+.ENDIF
+
+# Optionally compile for 16 bit Windows
+.IF $(USE_WIN16)
+.IF $(BUILD_DLL)
+   CFLAGS       += /GD /Alfw /DBUILD_DLL
+   ASFLAGS      += -DBUILD_DLL
+.ELSE
+   CFLAGS       += /GA /AL
+.ENDIF
+   DX_ASFLAGS   += -D__WINDOWS16__
+   LIB_OS       = WIN16
+.ELSE
+   USE_REALDOS	:= 1
+   CFLAGS       += /AL
+   LIB_OS       = DOS16
+.END
+
+# Place to look for PMODE library files
+
+PMLIB           := pm.lib
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK	:= vc16.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/vc32.mk b/board/MAI/bios_emulator/scitech/makedefs/vc32.mk
new file mode 100755
index 0000000..11c9071
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/vc32.mk
@@ -0,0 +1,226 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Microsoft Visual C++ 2.x 32 bit version. Supports Phar Lap
+#               TNT DOS Extender and 32 bit Windows development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : TNT_PATH VC_LIBBASE DOSSTYLE USE_TNT USE_RTTARGET MSVCDIR
+.IMPORT .IGNORE : USE_VXD USE_NTDRV USE_W2KDRV NT_DDKROOT USE_RTTI USE_CPPEXCEPT
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := cl       # C-compiler and flags
+   CFLAGS       :=
+.IF $(USE_NASM)
+   AS			:= nasm
+   ASFLAGS      := -t -f win32 -F null -d__FLAT__ -dSTDCALL_MANGLE -iINCLUDE -i$(SCITECH)\INCLUDE
+.ELSE
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx    # Assembler and flags
+.ELSE
+   AS           := tasm     # Assembler and flags
+.ENDIF
+   ASFLAGS      := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /iINCLUDE /i$(SCITECH)\INCLUDE
+.ENDIF
+   LD           := cl
+.IF $(USE_WIN32)
+   LDFLAGS       = $(CFLAGS)
+.IF $(USE_NTDRV)
+   LDENDFLAGS   = -link /INCREMENTAL:NO /DRIVER /SUBSYSTEM:NATIVE,4.00 /VERSION:4.00 /MACHINE:I386 /NODEFAULTLIB /DEBUGTYPE:CV /PDB:NONE /ALIGN:0x20 /BASE:0x10000 /ENTRY:DriverEntry@8
+	#/MERGE:_page=page /MERGE:_text=.text /MERGE:.rdata=.text
+.ELIF $(WIN32_GUI)
+   LDENDFLAGS   = -link /INCREMENTAL:NO /DEF:$(@:b).def /SUBSYSTEM:WINDOWS /MACHINE:I386 /DEBUGTYPE:CV /PDB:NONE
+.ELSE
+   LDENDFLAGS   = -link /INCREMENTAL:NO /SUBSYSTEM:CONSOLE /MACHINE:I386 /DEBUGTYPE:CV /PDB:NONE
+.ENDIF
+.ELSE
+   LDFLAGS       = $(CFLAGS)
+   LDENDFLAGS   := -link -stub:$(TNT_PATH:s/\/\\)\\bin\\gotnt.exe /PDB:NONE
+.ENDIF
+   RC           := rc       # Watcom resource compiler
+   RCFLAGS      :=          # Mark as Win32 compatible resources
+   LIB          := lib      # Librarian
+   LIBFLAGS     :=
+   ILIB         := lib      # Import librarian
+   ILIBFLAGS    := /MACHINE:IX86
+   INTEL_X86	:= 1
+   NMSYM   		:= $(SOFTICE_PATH)\nmsym.exe
+.IF $(USE_NTDRV)
+   NMSYMFLAGS	:= /TRANSLATE:source,package,always /PROMPT /SOURCE:$(MSVCDIR)\crt\src\intel;$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\ntdrv
+.ELSE
+   NMSYMFLAGS	:= /TRANSLATE:source,package,always /PROMPT /SOURCE:$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\win32
+.ENDIF
+
+# Set the compiler warning level
+.IF $(MAX_WARN)
+   CFLAGS       += -W3
+.ELSE
+   CFLAGS       += -W1
+.ENDIF
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += /Yd /Zi  # Turn on debugging for C compiler
+.IF $(USE_TASM)
+   ASFLAGS      += /zi      # Turn on debugging for assembler
+.ENDIF
+.ELSE
+.IF $(USE_TASM)
+   ASFLAGS      += /q       # Suppress object records not needed for linking
+.ENDIF
+.END
+
+# Optionally turn on optimisations
+.IF $(VC_LIBBASE) == vc5
+.IF $(OPT)
+   CFLAGS       += /G6 /O2 /Ox /Oi-
+.ELIF $(OPT_SIZE)
+   CFLAGS       += /G6 /O1
+.END
+.ELSE
+.IF $(OPT)
+   CFLAGS       += /G5 /O2 /Ox
+.ELIF $(OPT_SIZE)
+   CFLAGS       += /G5 /O1
+.END
+.ENDIF
+
+# Optionally turn on direct i387 FPU instructions
+
+.IF $(FPU)
+   CFLAGS       += /DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += /DBETA
+   ASFLAGS      += -dBETA
+.END
+
+# Use a larger stack during linking if requested, or use a default stack
+# of 50k. The usual default stack provided by Visual C++ is *way* to small
+# for real 32 bit code development.
+
+.IF $(USE_WIN32)
+	# Not necessary for Win32 code.
+.ELSE
+.IF $(STKSIZE)
+	LDENDFLAGS  += /STACK:$(STKSIZE)
+.ELSE
+	LDENDFLAGS  += /STACK:51200
+.ENDIF
+.ENDIF
+
+# DOS extender dependant flags
+.IF $(USE_NTDRV)				# Build 32 bit Windows NT driver
+   CFLAGS       += /LD /Zl /Gy /Gz /GF /D__NT_DRIVER__ /D_X86_=1 /Di386=1
+.IF $(DBG)
+   CFLAGS       += /QIf
+.ENDIF
+   ASFLAGS      +=
+   DEF_LIBS		:= int64.lib ntoskrnl.lib hal.lib
+   DX_ASFLAGS   += -d__NT_DRIVER__
+.IF $(USE_W2KDRV)				# Build 32 bit Windows 2000 driver
+   LIB_OS       = W2KDRV
+.ELSE
+   LIB_OS       = NTDRV
+.ENDIF
+.ELIF $(USE_WIN32)              # Build 32 bit Windows NT app
+.IF $(WIN32_GUI)
+.ELSE
+    CFLAGS       += -D__CONSOLE__
+.ENDIF
+.IF $(BUILD_DLL)
+   CFLAGS       += /MT /LD /DBUILD_DLL
+   ASFLAGS      += -dBUILD_DLL
+.IF $(NO_RUNTIME)
+   LDENDFLAGS   += /NODEFAULTLIB
+   CFLAGS 		+= /Zl
+   DEF_LIBS		:=
+.ELSE
+   DEF_LIBS		:= kernel32.lib user32.lib gdi32.lib advapi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib ole32.lib oleaut32.lib version.lib winspool.lib uuid.lib odbc32.lib odbccp32.lib wsock32.lib rpcrt4.lib
+.ENDIF
+.ELSE
+   CFLAGS       += /MT
+   DEF_LIBS		:= kernel32.lib user32.lib gdi32.lib advapi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib ole32.lib oleaut32.lib version.lib winspool.lib uuid.lib odbc32.lib odbccp32.lib wsock32.lib rpcrt4.lib
+.ENDIF
+   DX_ASFLAGS   += -d__WINDOWS32__
+   LIB_OS       = WIN32
+.ELIF $(USE_RTTARGET)
+   CFLAGS       += -D__RTTARGET__
+   DX_CFLAGS    +=
+   DX_ASFLAGS   += -d__RTTARGET__
+   USE_REALDOS	:=
+   LIB_OS       = RTT32
+   DEF_LIBS     := cw32mt.lib
+.ELSE
+   USE_TNT      := 1
+   USE_REALDOS	:= 1
+   CFLAGS       += /MT /D__MSDOS32__
+   DX_CFLAGS    += -DTNT
+   DX_ASFLAGS   += -dTNT
+   LIB_OS       = DOS32
+   DEF_LIBS		:= dosx32.lib tntapi.lib
+.ENDIF
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= /DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Place to look for PMODE library files
+
+.IF $(USE_TNT)
+PMLIB           := $(LIB_BASE:s/\/\\)\\tnt\\pm.lib
+.ELSE
+PMLIB           := $(LIB_BASE:s/\/\\)\\pm.lib
+.ENDIF
+
+# Define which file contains our rules
+
+   RULES_MAK	:= vc32.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/wc16.mk b/board/MAI/bios_emulator/scitech/makedefs/wc16.mk
new file mode 100755
index 0000000..e316f4c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/wc16.mk
@@ -0,0 +1,141 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Watcom C++ 10.x 16 bit version. Supports 16-bit DOS,
+#               16-bit Windows development and 16-bit OS/2 development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : WC_LIBBASE USE_WIN16 USE_OS216 USE_OS2GUI
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := wcc      # C-compiler and flags
+   CPP          := wpp      # C++-compiler and flags
+   CFLAGS       := -ml-zq-j-w2-s-fh -fhq
+.IF $(USE_TASM32)
+   AS           := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx    # Assembler and flags
+.ELSE
+   AS           := tasm     # Assembler and flags
+.ENDIF
+   AS           := tasm     # Assembler and flags
+   ASFLAGS      := /t /mx /m /D__LARGE__ /iINCLUDE /i$(SCITECH)\INCLUDE
+   LD           := wlink    # Loader and flags
+   LDFLAGS       =
+   RC           := wrc      # Watcom resource compiler
+   RCFLAGS      := /bt=windows
+   LIB          := wlib     # Librarian
+   LIBFLAGS     := -q
+   ILIB         := wlib     # Import librarian
+   ILIBFLAGS    := -c
+
+# Optionally turn on debugging information
+.IF $(DBG)
+   CFLAGS       += -d2      # Turn on debugging for C compiler
+   LIBFLAGS     += -p=128   # Larger page size for libraries with debug info!
+   ASFLAGS      += /zi      # Turn on debugging for assembler
+   LDFLAGS      += D A      # Turn on debugging for linker
+.ELSE
+   ASFLAGS      += /q       # Suppress object records not needed for linking
+.END
+
+# Optionally turn on optimisations
+.IF $(OPT)
+   CFLAGS       += -onatx-5
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -onaslmr-5
+.END
+
+# Optionally turn on direct i387 FPU instructions optimised for Pentium
+
+.IF $(FPU)
+   CFLAGS       += -fpi87-fp5-DFPU387
+   ASFLAGS      += -DFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -DBETA
+.END
+
+# Use a larger stack during linking if requested
+
+.IF $(STKSIZE)
+    LDFLAGS     += OP STACK=$(STKSIZE)
+.ENDIF
+
+.IF $(USE_OS216)
+.IF $(BUILD_DLL)
+    CFLAGS       += -bd-bt=os2-DBUILD_DLL
+    ASFLAGS      += -DBUILD_DLL
+.ELSE
+    CFLAGS       += -bt=os2
+.ENDIF
+    DX_ASFLAGS   += -D__OS216__
+    LIB_OS       = os216
+.ELIF $(USE_WIN16)
+.IF $(BUILD_DLL)
+    CFLAGS       += -bd-bt=windows-D_WINDOWS-DBUILD_DLL
+    ASFLAGS      += -DBUILD_DLL
+.ELSE
+    CFLAGS       += -bt=windows-D_WINDOWS
+.ENDIF
+    DX_ASFLAGS   += -D__WINDOWS16__
+    LIB_OS       = WIN16
+.ELSE
+    USE_REALDOS  := 1
+	LIB_OS       = DOS16
+.END
+
+# Place to look for PMODE library files
+
+PMLIB           := pm.lib,
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(WC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+# Define which file contains our rules
+
+   RULES_MAK	:= wc16.mk
diff --git a/board/MAI/bios_emulator/scitech/makedefs/wc32.mk b/board/MAI/bios_emulator/scitech/makedefs/wc32.mk
new file mode 100755
index 0000000..e5175ca
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/makedefs/wc32.mk
@@ -0,0 +1,353 @@
+#############################################################################
+#
+#					SciTech Multi-platform Graphics Library
+#
+#  ========================================================================
+#
+#    The contents of this file are subject to the SciTech MGL Public
+#    License Version 1.0 (the "License"); you may not use this file
+#    except in compliance with the License. You may obtain a copy of
+#    the License at http://www.scitechsoft.com/mgl-license.txt
+#
+#    Software distributed under the License is distributed on an
+#    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+#    implied. See the License for the specific language governing
+#    rights and limitations under the License.
+#
+#    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+#
+#    The Initial Developer of the Original Code is SciTech Software, Inc.
+#    All Rights Reserved.
+#
+#  ========================================================================
+#
+# Descripton:   Generic DMAKE startup makefile definitions file. Assumes
+#               that the SCITECH environment variable has been set to point
+#               to where all our stuff is installed. You should not need
+#               to change anything in this file.
+#
+#               Watcom C++ 10.x 32 bit version. Supports Rational's DOS4GW
+#               DOS Extender, PMODE/W, Causeway, FlashTek's X32-VM,
+#               Phar Lap's TNT DOS Extender, 32-bit Windows development and
+#				32-bit OS/2 development.
+#
+#############################################################################
+
+# Include standard startup script definitions
+.IMPORT: SCITECH
+.INCLUDE: "$(SCITECH)\makedefs\startup.mk"
+
+# Import enivornment variables that we use
+.IMPORT .IGNORE : USE_TNT USE_X32 USE_X32VM USE_PMODEW STKCALL USE_CAUSEWAY
+.IMPORT .IGNORE : USE_WIN386 USE_OS232 USE_OS2GUI WC_LIBBASE NOOPT DOSSTYLE
+.IMPORT .IGNORE : OS2_SHELL USE_CODEVIEW USE_DOS32A USE_QNX4 LEAVE_LINKFILE
+
+# We are compiling for a 32 bit envionment
+   _32BIT_      := 1
+
+# Setup special environment for QNX 4 (Unix'ish)
+.IF $(USE_QNX4)
+   USE_QNX    	:= 1
+   L            := .a   	# Libraries
+   LP           := lib      # LP - Library file prefix (name of file on disk)
+   LL           := lib		# Library link prefix (name of library on link command line)
+   LE           := .a	    # Library link suffix (extension of library on link command line)
+.ENDIF
+
+# Default commands for compiling, assembling linking and archiving
+   CC           := wcc386
+   CPP          := wpp386
+   CFLAGS       := -zq-j-s-fpi87
+.IF $(USE_NASM)
+   AS			:= nasm
+   ASFLAGS      := -t -f obj -d__FLAT__ -dSTDCALL_MANGLE -iINCLUDE -i$(SCITECH)\INCLUDE
+.ELSE
+.IF $(USE_TASM32)
+   AS           := tasm32
+   DLL_TASM     := tasm32
+.ELIF $(USE_TASMX)
+   AS           := tasmx
+   DLL_TASM     := tasmx
+.ELSE
+   AS           := tasm
+   DLL_TASM     := tasm
+.ENDIF
+   ASFLAGS      := /t /mx /m /w-res /w-mcp /D__FLAT__ /DSTDCALL_MANGLE /iINCLUDE /i$(SCITECH)\INCLUDE
+   GAS			:= gcc
+   GAS_FLAGS 	:= -D__WATCOMC__ -D__SW_3S -D__SW_S -U__GNUC__ -UDJGPP -U__unix__ -Wall -I. -I$(SCITECH)\include -x assembler-with-cpp
+.ENDIF
+   LD           := wlink
+   LDFLAGS       =
+.IF $(USE_OS232)
+   RC           := rc
+.ELSE
+   RC           := wrc
+.ENDIF
+.IF $(USE_WIN32)
+   RCFLAGS      := -q /bt=nt
+.ELIF $(USE_OS232)
+.IF $(USE_OS2GUI)
+   CFLAGS		+= -D__OS2_PM__
+.ENDIF
+.ELSE
+   RCFLAGS      := -q
+.ENDIF
+   LIB          := wlib
+   LIBFLAGS     := -q
+   ILIB         := wlib
+   ILIBFLAGS    := -c
+   INTEL_X86	:= 1
+
+# Set the compiler warning level
+.IF $(MAX_WARN)
+   CFLAGS       += -w4
+.ELSE
+   CFLAGS       += -w1
+.ENDIF
+
+# Optionally turn on debugging information (Codeview format)
+.IF $(DBG)
+.IF $(USE_WIN32)
+.IF $(USE_CODEVIEW)
+   CFLAGS       += -d2 -hc
+   LDFLAGS      += D CODEVIEW OPT CVPACK
+.ELSE
+   CFLAGS       += -d2
+   LDFLAGS		+= D A
+.ENDIF
+.ELSE
+   CFLAGS       += -d2
+   LDFLAGS		+= D A
+.ENDIF
+   LIBFLAGS     += -p=768
+.IF $(USE_NASM)
+   ASFLAGS      += -F borland -g
+.ELSE
+.IF $(USE_TASM32)
+   ASFLAGS      += /q		# TASM32 fucks up Watcom C++ debug info
+.ELIF $(OS2_SHELL)
+   ASFLAGS      += /q		# TASM for OS/2 fucks up Watcom C++ debug info
+.ELSE
+   ASFLAGS      += /zi
+.ENDIF
+.ENDIF
+.ELSE
+.IF $(USE_NASM)
+   ASFLAGS      += -F null
+.ELSE
+   ASFLAGS      += /q
+.ENDIF
+.END
+
+# Optionally turn on optimisations (with or without stack conventions)
+.IF $(STKCALL)
+.IF $(OPT)
+   CFLAGS       += -onatx-5s-fp5
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -onaslmr-5s-fp5
+.ELIF $(NOOPT)
+   CFLAGS       += -od-5s
+.ELSE
+   CFLAGS       += -3s
+.END
+.ELSE
+.IF $(OPT)
+   CFLAGS       += -onatx-5r-fp5
+.ELIF $(OPT_SIZE)
+   CFLAGS       += -onaslmr-5r-fp5
+.ELIF $(NOOPT)
+   CFLAGS       += -od-5r
+.END
+.END
+
+# Optionally turn on direct i387 FPU instructions optimised for Pentium
+.IF $(FPU)
+   CFLAGS       += -DFPU387
+   ASFLAGS      += -dFPU387
+.END
+
+# Optionally compile a beta release version of a product
+.IF $(BETA)
+   CFLAGS       += -DBETA
+   ASFLAGS      += -dBETA
+.END
+
+.IF $(USE_TNT)                  # Use Phar Lap's TNT DOS Extender
+	CFLAGS       += -bt=nt -DTNT
+	ASFLAGS   	 += -dTNT
+	LDFLAGS      += SYS NT OP STUB=GOTNT.EXE
+	LIB_OS       = DOS32
+.ELIF $(USE_X32VM)              # Use FlashTek X-32VM DOS extender
+	CFLAGS       += -bt=dos
+	LDFLAGS      += SYS X32RV
+    DX_CFLAGS    += -DX32VM
+	DX_ASFLAGS   += -dX32VM
+    LIB_OS       = DOS32
+.ELIF $(USE_X32)                # Use FlashTek X-32 DOS extender
+	CFLAGS       += -bt=dos
+	LDFLAGS      += SYS X32R
+    DX_CFLAGS    += -DX32VM
+	DX_ASFLAGS   += -dX32VM
+    LIB_OS       = DOS32
+.ELIF $(USE_QNX4)               # Build QNX 4 app
+	CFLAGS       += -bt=qnx386
+	LDFLAGS      += SYS QNX386FLAT OP CASEEXACT OP OFFSET=40k OP STACK=32k
+    CFLAGS    	 += -D__QNX__ -D__UNIX__
+	ASFLAGS   	 += -d__QNX__ -d__UNIX__
+    LIB_OS       = QNX4
+.ELIF $(USE_OS232)
+.IF $(BUILD_DLL)
+	CFLAGS       += -bm-bd-bt=os2-sg-DBUILD_DLL
+	ASFLAGS      += -dBUILD_DLL
+.ELSE
+	CFLAGS       += -bm-bt=os2-sg
+.ENDIF
+	DX_ASFLAGS   += -d__OS2__
+    LIB_OS       = os232
+.ELIF $(USE_SNAP)               # Build 32 bit Snap app
+.IF $(BUILD_DLL)
+	CFLAGS       += -bm-bd-bt=nt-DBUILD_DLL
+	ASFLAGS      += -dBUILD_DLL
+.ELSE
+	CFLAGS       += -bm-bt=nt-D_WIN32
+.ENDIF
+	LDFLAGS	     += OP nodefaultlibs
+.IF $(STKCALL)
+	DEFLIBS		 := clib3s.lib,math3s.lib,noemu387.lib,
+.ELSE
+	DEFLIBS		 := clib3r.lib,math3r.lib,noemu387.lib,
+.ENDIF
+	LIB_OS       = SNAP
+.ELIF $(USE_WIN32)              # Build 32 bit Windows NT app
+.IF $(WIN32_GUI)
+.ELSE
+    CFLAGS       += -D__CONSOLE__
+.ENDIF
+.IF $(BUILD_DLL)
+	CFLAGS       += -bm-bd-bt=nt-sg-DBUILD_DLL -D_WIN32
+	ASFLAGS      += -dBUILD_DLL
+.ELSE
+	CFLAGS       += -bm-bt=nt-sg-D_WIN32
+.ENDIF
+	DX_ASFLAGS   += -d__WINDOWS32__
+	LIB_OS       = WIN32
+    DEFLIBS	     := kernel32.lib,user32.lib,gdi32.lib,advapi32.lib,shell32.lib,winmm.lib,comdlg32.lib,comctl32.lib,ole32.lib,oleaut32.lib,version.lib,winspool.lib,uuid.lib,wsock32.lib,rpcrt4.lib,
+.ELIF $(USE_WIN386)             # Build 32 bit Win386 extended app
+.IF $(BUILD_DLL)
+    CFLAGS       += -bd-bt=windows-DBUILD_DLL
+	ASFLAGS      += -dBUILD_DLL
+.ELSE
+    CFLAGS       += -bt=windows
+.ENDIF
+	DX_ASFLAGS   += -d__WIN386__
+    LIB_OS       = WIN386
+.ELIF $(USE_PMODEW)             # PMODE/W
+	CFLAGS       += -bt=dos
+	USE_DOS4GW   := 1
+	USE_REALDOS  := 1
+	LDFLAGS      += SYS PMODEW
+	DX_CFLAGS    += -DDOS4GW
+	DX_ASFLAGS   += -dDOS4GW
+	LIB_OS       = DOS32
+.ELIF $(USE_CAUSEWAY)           # Causeway
+	CFLAGS       += -bt=dos
+	USE_DOS4GW   := 1
+	USE_REALDOS  := 1
+	LDFLAGS      += SYS CAUSEWAY
+	DX_CFLAGS    += -DDOS4GW
+	DX_ASFLAGS   += -dDOS4GW
+	LIB_OS       = DOS32
+.ELIF $(USE_DOS32A)             # DOS32/A
+	CFLAGS       += -bt=dos
+	USE_DOS4GW   := 1
+	USE_REALDOS  := 1
+	LDFLAGS      += SYS DOS32A
+	DX_CFLAGS    += -DDOS4GW
+	DX_ASFLAGS   += -dDOS4GW
+	LIB_OS       = DOS32
+.ELSE                           # Use DOS4GW
+	CFLAGS       += -bt=dos
+	USE_DOS4GW   := 1
+	USE_REALDOS  := 1
+	LDFLAGS      += SYS DOS4G
+	DX_CFLAGS    += -DDOS4GW
+	DX_ASFLAGS   += -dDOS4GW
+	LIB_OS       = DOS32
+.END
+
+# Disable linking to default C runtime library and PM library
+
+.IF $(NO_RUNTIME)
+LDFLAGS			 += OP nodefaultlibs
+DEFLIBS          :=
+.ELSE
+
+# Place to look for PM library files
+
+.IF $(USE_SNAP)               	# Build 32 bit Snap app or dll
+PMLIB           :=
+.ELIF $(USE_WIN32)
+.IF $(STKCALL)
+PMLIB           := spm.lib,
+.ELSE
+PMLIB           := pm.lib,
+.ENDIF
+.ELIF $(USE_OS232)
+.IF $(STKCALL)
+.IF $(USE_OS2GUI)
+PMLIB           := spm_pm.lib,
+.ELSE
+PMLIB           := spm.lib,
+.ENDIF
+.ELSE
+.IF $(USE_OS2GUI)
+PMLIB           := pm_pm.lib,
+.ELSE
+PMLIB           := pm.lib,
+.ENDIF
+.ENDIF
+.ELIF $(USE_QNX4)
+.IF $(STKCALL)
+PMLIB           := libspm.a,
+.ELSE
+PMLIB           := libpm.a,
+.ENDIF
+.ELIF $(USE_TNT)
+.IF $(STKCALL)
+PMLIB           := tnt\spm.lib,
+.ELSE
+PMLIB           := tnt\pm.lib,
+.ENDIF
+.ELIF $(USE_X32)
+.IF $(STKCALL)
+PMLIB           := x32\spm.lib,
+.ELSE
+PMLIB           := x32\pm.lib,
+.ENDIF
+.ELSE
+.IF $(STKCALL)
+PMLIB           := dos4gw\spm.lib,
+.ELSE
+PMLIB           := dos4gw\pm.lib,
+.ENDIF
+.ENDIF
+.ENDIF
+
+# Define the base directory for library files
+
+.IF $(CHECKED)
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\debug
+CFLAGS			+= -DCHECKED=1
+.ELSE
+LIB_BASE_DIR	:= $(SCITECH_LIB)\lib\release
+.ENDIF
+
+# Define where to install library files
+   LIB_BASE     := $(LIB_BASE_DIR)\$(LIB_OS)\$(WC_LIBBASE)
+   LIB_DEST     := $(LIB_BASE)
+
+    LDFLAGS += op map
+
+# Define which file contains our rules
+
+   RULES_MAK	:= wc32.mk
diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/besys.c b/board/MAI/bios_emulator/scitech/src/biosemu/besys.c
new file mode 100755
index 0000000..1512ce9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/biosemu/besys.c
@@ -0,0 +1,408 @@
+/****************************************************************************
+*
+*                        BIOS emulator and interface
+*                      to Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  This file includes BIOS emulator I/O and memory access
+*               functions.
+*
+****************************************************************************/
+
+#include "biosemui.h"
+
+/*------------------------------- Macros ----------------------------------*/
+
+/* Macros to read and write values to x86 bus memory. Replace these as
+ * necessary if you need to do something special to access memory over
+ * the bus on a particular processor family.
+ */
+
+#define readb(base,off)     *((u8*)((u32)(base) + (off)))
+#define readw(base,off)     *((u16*)((u32)(base) + (off)))
+#define readl(base,off)     *((u32*)((u32)(base) + (off)))
+#define writeb(v,base,off)  *((u8*)((u32)(base) + (off))) = (v)
+#define writew(v,base,off)  *((u16*)((u32)(base) + (off))) = (v)
+#define writel(v,base,off)  *((u32*)((u32)(base) + (off))) = (v)
+
+/*----------------------------- Implementation ----------------------------*/
+
+#ifdef DEBUG
+# define DEBUG_MEM()        (M.x86.debug & DEBUG_MEM_TRACE_F)
+#else
+# define DEBUG_MEM()
+#endif
+
+/****************************************************************************
+PARAMETERS:
+addr    - Emulator memory address to read
+
+RETURNS:
+Byte value read from emulator memory.
+
+REMARKS:
+Reads a byte value from the emulator memory. We have three distinct memory
+regions that are handled differently, which this function handles.
+****************************************************************************/
+u8 X86API BE_rdb(
+    u32 addr)
+{
+    u8 val = 0;
+
+    if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
+	val = *(u8*)(_BE_env.biosmem_base + addr - 0xC0000);
+	}
+    else if (addr >= 0xA0000 && addr <= 0xFFFFF) {
+	val = readb(_BE_env.busmem_base, addr - 0xA0000);
+	}
+    else if (addr > M.mem_size - 1) {
+DB(     printk("mem_read: address %#lx out of range!\n", addr);)
+	HALT_SYS();
+	}
+    else {
+	val = *(u8*)(M.mem_base + addr);
+	}
+DB( if (DEBUG_MEM())
+	printk("%#08x 1 -> %#x\n", addr, val);)
+    return val;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr    - Emulator memory address to read
+
+RETURNS:
+Word value read from emulator memory.
+
+REMARKS:
+Reads a word value from the emulator memory. We have three distinct memory
+regions that are handled differently, which this function handles.
+****************************************************************************/
+u16 X86API BE_rdw(
+    u32 addr)
+{
+    u16 val = 0;
+
+    if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+	    addr -= 0xC0000;
+	    val = ( *(u8*)(_BE_env.biosmem_base + addr) |
+		   (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8));
+	    }
+	else
+#endif
+	    val = *(u16*)(_BE_env.biosmem_base + addr - 0xC0000);
+	}
+    else if (addr >= 0xA0000 && addr <= 0xFFFFF) {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+	    addr -= 0xA0000;
+	    val = ( readb(_BE_env.busmem_base, addr) |
+		   (readb(_BE_env.busmem_base, addr + 1) << 8));
+	    }
+	else
+#endif
+	    val = readw(_BE_env.busmem_base, addr - 0xA0000);
+	}
+    else if (addr > M.mem_size - 2) {
+DB(     printk("mem_read: address %#lx out of range!\n", addr);)
+	HALT_SYS();
+	}
+    else {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+	    val = ( *(u8*)(M.mem_base + addr) |
+		   (*(u8*)(M.mem_base + addr + 1) << 8));
+	    }
+	else
+#endif
+	    val = *(u16*)(M.mem_base + addr);
+	}
+DB( if (DEBUG_MEM())
+	printk("%#08x 2 -> %#x\n", addr, val);)
+    return val;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr    - Emulator memory address to read
+
+RETURNS:
+Long value read from emulator memory.
+
+REMARKS:
+Reads a long value from the emulator memory. We have three distinct memory
+regions that are handled differently, which this function handles.
+****************************************************************************/
+u32 X86API BE_rdl(
+    u32 addr)
+{
+    u32 val = 0;
+
+    if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x3) {
+	    addr -= 0xC0000;
+	    val = ( *(u8*)(_BE_env.biosmem_base + addr + 0) |
+		   (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8) |
+		   (*(u8*)(_BE_env.biosmem_base + addr + 2) << 16) |
+		   (*(u8*)(_BE_env.biosmem_base + addr + 3) << 24));
+	    }
+	else
+#endif
+	    val = *(u32*)(_BE_env.biosmem_base + addr - 0xC0000);
+	}
+    else if (addr >= 0xA0000 && addr <= 0xFFFFF) {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x3) {
+	    addr -= 0xA0000;
+	    val = ( readb(_BE_env.busmem_base, addr) |
+		   (readb(_BE_env.busmem_base, addr + 1) <<  8) |
+		   (readb(_BE_env.busmem_base, addr + 2) << 16) |
+		   (readb(_BE_env.busmem_base, addr + 3) << 24));
+	    }
+	else
+#endif
+	    val = readl(_BE_env.busmem_base, addr - 0xA0000);
+	}
+    else if (addr > M.mem_size - 4) {
+DB(     printk("mem_read: address %#lx out of range!\n", addr);)
+	HALT_SYS();
+	}
+    else {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x3) {
+	    val = ( *(u8*)(M.mem_base + addr + 0) |
+		   (*(u8*)(M.mem_base + addr + 1) << 8) |
+		   (*(u8*)(M.mem_base + addr + 2) << 16) |
+		   (*(u8*)(M.mem_base + addr + 3) << 24));
+	    }
+	else
+#endif
+	    val = *(u32*)(M.mem_base + addr);
+	}
+DB( if (DEBUG_MEM())
+	printk("%#08x 4 -> %#x\n", addr, val);)
+    return val;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr    - Emulator memory address to read
+val     - Value to store
+
+REMARKS:
+Writes a byte value to emulator memory. We have three distinct memory
+regions that are handled differently, which this function handles.
+****************************************************************************/
+void X86API BE_wrb(
+    u32 addr,
+    u8 val)
+{
+DB( if (DEBUG_MEM())
+	printk("%#08x 1 <- %#x\n", addr, val);)
+    if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
+	*(u8*)(_BE_env.biosmem_base + addr - 0xC0000) = val;
+	}
+    else if (addr >= 0xA0000 && addr <= 0xFFFFF) {
+	writeb(val, _BE_env.busmem_base, addr - 0xA0000);
+	}
+    else if (addr > M.mem_size-1) {
+DB(     printk("mem_write: address %#lx out of range!\n", addr);)
+	HALT_SYS();
+	}
+    else {
+	*(u8*)(M.mem_base + addr) = val;
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+addr    - Emulator memory address to read
+val     - Value to store
+
+REMARKS:
+Writes a word value to emulator memory. We have three distinct memory
+regions that are handled differently, which this function handles.
+****************************************************************************/
+void X86API BE_wrw(
+    u32 addr,
+    u16 val)
+{
+DB( if (DEBUG_MEM())
+	printk("%#08x 2 <- %#x\n", addr, val);)
+    if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+	    addr -= 0xC0000;
+	    *(u8*)(_BE_env.biosmem_base + addr + 0) = (val >> 0) & 0xff;
+	    *(u8*)(_BE_env.biosmem_base + addr + 1) = (val >> 8) & 0xff;
+	    }
+	else
+#endif
+	    *(u16*)(_BE_env.biosmem_base + addr - 0xC0000) = val;
+	}
+    else if (addr >= 0xA0000 && addr <= 0xFFFFF) {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+	    addr -= 0xA0000;
+	    writeb(val >> 0, _BE_env.busmem_base, addr);
+	    writeb(val >> 8, _BE_env.busmem_base, addr + 1);
+	    }
+	else
+#endif
+	    writew(val, _BE_env.busmem_base, addr - 0xA0000);
+	}
+    else if (addr > M.mem_size-2) {
+DB(     printk("mem_write: address %#lx out of range!\n", addr);)
+	HALT_SYS();
+	}
+    else {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+	    *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff;
+	    *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff;
+	    }
+	else
+#endif
+	    *(u16*)(M.mem_base + addr) = val;
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+addr    - Emulator memory address to read
+val     - Value to store
+
+REMARKS:
+Writes a long value to emulator memory. We have three distinct memory
+regions that are handled differently, which this function handles.
+****************************************************************************/
+void X86API BE_wrl(
+    u32 addr,
+    u32 val)
+{
+DB( if (DEBUG_MEM())
+	printk("%#08x 4 <- %#x\n", addr, val);)
+    if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+	    addr -= 0xC0000;
+	    *(u8*)(M.mem_base + addr + 0) = (val >>  0) & 0xff;
+	    *(u8*)(M.mem_base + addr + 1) = (val >>  8) & 0xff;
+	    *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff;
+	    *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff;
+	    }
+	else
+#endif
+	    *(u32*)(M.mem_base + addr - 0xC0000) = val;
+	}
+    else if (addr >= 0xA0000 && addr <= 0xFFFFF) {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x3) {
+	    addr -= 0xA0000;
+	    writeb(val >>  0, _BE_env.busmem_base, addr);
+	    writeb(val >>  8, _BE_env.busmem_base, addr + 1);
+	    writeb(val >> 16, _BE_env.busmem_base, addr + 1);
+	    writeb(val >> 24, _BE_env.busmem_base, addr + 1);
+	    }
+	else
+#endif
+	    writel(val, _BE_env.busmem_base, addr - 0xA0000);
+	}
+    else if (addr > M.mem_size-4) {
+DB(     printk("mem_write: address %#lx out of range!\n", addr);)
+	HALT_SYS();
+	}
+    else {
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+	    *(u8*)(M.mem_base + addr + 0) = (val >>  0) & 0xff;
+	    *(u8*)(M.mem_base + addr + 1) = (val >>  8) & 0xff;
+	    *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff;
+	    *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff;
+	    }
+	else
+#endif
+	    *(u32*)(M.mem_base + addr) = val;
+	}
+}
+
+/* Debug functions to do ISA/PCI bus port I/O */
+
+#ifdef  DEBUG
+#define DEBUG_IO()          (M.x86.debug & DEBUG_IO_TRACE_F)
+
+u8 X86API BE_inb(int port)
+{
+    u8 val = PM_inpb(port);
+    if (DEBUG_IO())
+	printk("%04X:%04X:  inb.%04X -> %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val);
+    return val;
+}
+
+u16 X86API BE_inw(int port)
+{
+    u16 val = PM_inpw(port);
+    if (DEBUG_IO())
+	printk("%04X:%04X:  inw.%04X -> %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val);
+    return val;
+}
+
+u32 X86API BE_inl(int port)
+{
+    u32 val = PM_inpd(port);
+    if (DEBUG_IO())
+	printk("%04X:%04X:  inl.%04X -> %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val);
+    return val;
+}
+
+void X86API BE_outb(int port, u8 val)
+{
+    if (DEBUG_IO())
+	printk("%04X:%04X: outb.%04X <- %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val);
+    PM_outpb(port,val);
+}
+
+void X86API BE_outw(int port, u16 val)
+{
+    if (DEBUG_IO())
+	printk("%04X:%04X: outw.%04X <- %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val);
+    PM_outpw(port,val);
+}
+
+void X86API BE_outl(int port, u32 val)
+{
+    if (DEBUG_IO())
+	printk("%04X:%04X: outl.%04X <- %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val);
+    PM_outpd(port,val);
+}
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/bios.c b/board/MAI/bios_emulator/scitech/src/biosemu/bios.c
new file mode 100755
index 0000000..c0f4a4b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/biosemu/bios.c
@@ -0,0 +1,250 @@
+/****************************************************************************
+*
+*                        BIOS emulator and interface
+*                      to Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Module implementing the BIOS specific functions.
+*
+****************************************************************************/
+
+#include "biosemui.h"
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+intno   - Interrupt number being serviced
+
+REMARKS:
+Handler for undefined interrupts.
+****************************************************************************/
+static void X86API undefined_intr(
+    int intno)
+{
+    if (BE_rdw(intno * 4 + 2) == BIOS_SEG)
+	printk("biosEmu: undefined interrupt %xh called!\n",intno);
+    else
+	X86EMU_prepareForInt(intno);
+}
+
+/****************************************************************************
+PARAMETERS:
+intno   - Interrupt number being serviced
+
+REMARKS:
+This function handles the default system BIOS Int 10h (the default is stored
+in the Int 42h vector by the system BIOS at bootup). We only need to handle
+a small number of special functions used by the BIOS during POST time.
+****************************************************************************/
+static void X86API int42(
+    int intno)
+{
+    if (M.x86.R_AH == 0x12 && M.x86.R_BL == 0x32) {
+	if (M.x86.R_AL == 0) {
+	    /* Enable CPU accesses to video memory */
+	    PM_outpb(0x3c2, PM_inpb(0x3cc) | (u8)0x02);
+	    return;
+	    }
+	else if (M.x86.R_AL == 1) {
+	    /* Disable CPU accesses to video memory */
+	    PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8)~0x02);
+	    return;
+	    }
+#ifdef  DEBUG
+	else {
+	    printk("biosEmu/bios.int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",M.x86.R_AL);
+	    }
+#endif
+	}
+#ifdef  DEBUG
+    else {
+	printk("biosEmu/bios.int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",M.x86.R_AH, M.x86.R_AL, M.x86.R_BL);
+	}
+#endif
+}
+
+/****************************************************************************
+PARAMETERS:
+intno   - Interrupt number being serviced
+
+REMARKS:
+This function handles the default system BIOS Int 10h. If the POST code
+has not yet re-vectored the Int 10h BIOS interrupt vector, we handle this
+by simply calling the int42 interrupt handler above. Very early in the
+BIOS POST process, the vector gets replaced and we simply let the real
+mode interrupt handler process the interrupt.
+****************************************************************************/
+static void X86API int10(
+    int intno)
+{
+    if (BE_rdw(intno * 4 + 2) == BIOS_SEG)
+	int42(intno);
+    else
+	X86EMU_prepareForInt(intno);
+}
+
+/* Result codes returned by the PCI BIOS */
+
+#define SUCCESSFUL          0x00
+#define FUNC_NOT_SUPPORT    0x81
+#define BAD_VENDOR_ID       0x83
+#define DEVICE_NOT_FOUND    0x86
+#define BAD_REGISTER_NUMBER 0x87
+#define SET_FAILED          0x88
+#define BUFFER_TOO_SMALL    0x89
+
+/****************************************************************************
+PARAMETERS:
+intno   - Interrupt number being serviced
+
+REMARKS:
+This function handles the default Int 1Ah interrupt handler for the real
+mode code, which provides support for the PCI BIOS functions. Since we only
+want to allow the real mode BIOS code *only* see the PCI config space for
+its own device, we only return information for the specific PCI config
+space that we have passed in to the init function. This solves problems
+when using the BIOS to warm boot a secondary adapter when there is an
+identical adapter before it on the bus (some BIOS'es get confused in this
+case).
+****************************************************************************/
+static void X86API int1A(
+    unused)
+{
+    u16 pciSlot;
+
+    /* Fail if no PCI device information has been registered */
+    if (!_BE_env.vgaInfo.pciInfo)
+	return;
+    pciSlot = (u16)(_BE_env.vgaInfo.pciInfo->slot.i >> 8);
+    switch (M.x86.R_AX) {
+	case 0xB101:                    /* PCI bios present? */
+	    M.x86.R_AL  = 0x00;         /* no config space/special cycle generation support */
+	    M.x86.R_EDX = 0x20494350;   /* " ICP" */
+	    M.x86.R_BX  = 0x0210;       /* Version 2.10 */
+	    M.x86.R_CL  = 0;            /* Max bus number in system */
+	    CLEAR_FLAG(F_CF);
+	    break;
+	case 0xB102:                    /* Find PCI device */
+	    M.x86.R_AH = DEVICE_NOT_FOUND;
+	    if (M.x86.R_DX == _BE_env.vgaInfo.pciInfo->VendorID &&
+		    M.x86.R_CX == _BE_env.vgaInfo.pciInfo->DeviceID &&
+		    M.x86.R_SI == 0) {
+		M.x86.R_AH = SUCCESSFUL;
+		M.x86.R_BX = pciSlot;
+		}
+	    CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
+	    break;
+	case 0xB103:                    /* Find PCI class code */
+	    M.x86.R_AH = DEVICE_NOT_FOUND;
+	    if (M.x86.R_CL == _BE_env.vgaInfo.pciInfo->Interface &&
+		    M.x86.R_CH == _BE_env.vgaInfo.pciInfo->SubClass &&
+		    (u8)(M.x86.R_ECX >> 16) == _BE_env.vgaInfo.pciInfo->BaseClass) {
+		M.x86.R_AH = SUCCESSFUL;
+		M.x86.R_BX = pciSlot;
+		}
+	    CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
+	    break;
+	case 0xB108:                    /* Read configuration byte */
+	    M.x86.R_AH = BAD_REGISTER_NUMBER;
+	    if (M.x86.R_BX == pciSlot) {
+		M.x86.R_AH = SUCCESSFUL;
+		M.x86.R_CL = (u8)PCI_accessReg(M.x86.R_DI,0,PCI_READ_BYTE,_BE_env.vgaInfo.pciInfo);
+		}
+	    CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
+	    break;
+	case 0xB109:                    /* Read configuration word */
+	    M.x86.R_AH = BAD_REGISTER_NUMBER;
+	    if (M.x86.R_BX == pciSlot) {
+		M.x86.R_AH = SUCCESSFUL;
+		M.x86.R_CX = (u16)PCI_accessReg(M.x86.R_DI,0,PCI_READ_WORD,_BE_env.vgaInfo.pciInfo);
+		}
+	    CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
+	    break;
+	case 0xB10A:                    /* Read configuration dword */
+	    M.x86.R_AH = BAD_REGISTER_NUMBER;
+	    if (M.x86.R_BX == pciSlot) {
+		M.x86.R_AH = SUCCESSFUL;
+		M.x86.R_ECX = (u32)PCI_accessReg(M.x86.R_DI,0,PCI_READ_DWORD,_BE_env.vgaInfo.pciInfo);
+		}
+	    CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
+	    break;
+	case 0xB10B:                    /* Write configuration byte */
+	    M.x86.R_AH = BAD_REGISTER_NUMBER;
+	    if (M.x86.R_BX == pciSlot) {
+		M.x86.R_AH = SUCCESSFUL;
+		PCI_accessReg(M.x86.R_DI,M.x86.R_CL,PCI_WRITE_BYTE,_BE_env.vgaInfo.pciInfo);
+		}
+	    CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
+	    break;
+	case 0xB10C:                    /* Write configuration word */
+	    M.x86.R_AH = BAD_REGISTER_NUMBER;
+	    if (M.x86.R_BX == pciSlot) {
+		M.x86.R_AH = SUCCESSFUL;
+		PCI_accessReg(M.x86.R_DI,M.x86.R_CX,PCI_WRITE_WORD,_BE_env.vgaInfo.pciInfo);
+		}
+	    CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
+	    break;
+	case 0xB10D:                    /* Write configuration dword */
+	    M.x86.R_AH = BAD_REGISTER_NUMBER;
+	    if (M.x86.R_BX == pciSlot) {
+		M.x86.R_AH = SUCCESSFUL;
+		PCI_accessReg(M.x86.R_DI,M.x86.R_ECX,PCI_WRITE_DWORD,_BE_env.vgaInfo.pciInfo);
+		}
+	    CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
+	    break;
+	default:
+	    printk("biosEmu/bios.int1a: unknown function AX=%#04x\n", M.x86.R_AX);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the BIOS emulation functions for the specific
+PCI display device. We insulate the real mode BIOS from any other devices
+on the bus, so that it will work correctly thinking that it is the only
+device present on the bus (ie: avoiding any adapters present in from of
+the device we are trying to control).
+****************************************************************************/
+void _BE_bios_init(
+    u32 *intrTab)
+{
+    int                 i;
+    X86EMU_intrFuncs    bios_intr_tab[256];
+
+    for (i = 0; i < 256; ++i) {
+	intrTab[i] = BIOS_SEG << 16;
+	bios_intr_tab[i] = undefined_intr;
+	}
+    bios_intr_tab[0x10] = int10;
+    bios_intr_tab[0x1A] = int1A;
+    bios_intr_tab[0x42] = int42;
+    X86EMU_setupIntrFuncs(bios_intr_tab);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c b/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c
new file mode 100755
index 0000000..0052709
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c
@@ -0,0 +1,445 @@
+/****************************************************************************
+*
+*                        BIOS emulator and interface
+*                      to Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Module implementing the system specific functions. This
+*               module is always compiled and linked in the OS depedent
+*               libraries, and never in a binary portable driver.
+*
+****************************************************************************/
+
+#include "biosemui.h"
+#include <string.h>
+#include <stdlib.h>
+
+/*------------------------- Global Variables ------------------------------*/
+
+BE_sysEnv           _BE_env;
+#ifdef  __DRIVER__
+PM_imports  _VARAPI _PM_imports;
+#endif
+static X86EMU_memFuncs _BE_mem = {
+    BE_rdb,
+    BE_rdw,
+    BE_rdl,
+    BE_wrb,
+    BE_wrw,
+    BE_wrl,
+    };
+#ifdef  DEBUG
+static X86EMU_pioFuncs _BE_pio = {
+    BE_inb,
+    BE_inw,
+    BE_inl,
+    BE_outb,
+    BE_outw,
+    BE_outl,
+    };
+#else
+static X86EMU_pioFuncs _BE_pio = {
+    (void*)PM_inpb,
+    (void*)PM_inpw,
+    (void*)PM_inpd,
+    (void*)PM_outpb,
+    (void*)PM_outpw,
+    (void*)PM_outpd,
+    };
+#endif
+
+/*-------------------------- Implementation -------------------------------*/
+
+#define OFF(addr)       (u16)(((addr) >> 0) & 0xffff)
+#define SEG(addr)       (u16)(((addr) >> 4) & 0xf000)
+
+/****************************************************************************
+PARAMETERS:
+debugFlags  - Flags to enable debugging options (debug builds only)
+memSize     - Amount of memory to allocate for real mode machine
+info        - Pointer to default VGA device information
+
+REMARKS:
+This functions initialises the BElib, and uses the passed in
+BIOS image as the BIOS that is used and emulated at 0xC0000.
+****************************************************************************/
+ibool PMAPI BE_init(
+    u32 debugFlags,
+    int memSize,
+    BE_VGAInfo *info)
+{
+#ifndef __DRIVER__
+    PM_init();
+#endif
+    memset(&M,0,sizeof(M));
+    if (memSize < 20480)
+	PM_fatalError("Emulator requires at least 20Kb of memory!\n");
+    if ((M.mem_base = (unsigned long)malloc(memSize)) == NULL)
+	PM_fatalError("Out of memory!");
+    M.mem_size = memSize;
+    _BE_env.busmem_base = (ulong)PM_mapPhysicalAddr(0xA0000,0x5FFFF,true);
+    M.x86.debug = debugFlags;
+    _BE_bios_init((u32*)info->LowMem);
+    X86EMU_setupMemFuncs(&_BE_mem);
+    X86EMU_setupPioFuncs(&_BE_pio);
+    BE_setVGA(info);
+    return true;
+}
+
+/****************************************************************************
+PARAMETERS:
+debugFlags  - Flags to enable debugging options (debug builds only)
+
+REMARKS:
+This function allows the application to enable logging and debug flags
+on a function call basis, so we can specifically enable logging only
+for specific functions that are causing problems in debug mode.
+****************************************************************************/
+void PMAPI BE_setDebugFlags(
+    u32 debugFlags)
+{
+    M.x86.debug = debugFlags;
+}
+
+/****************************************************************************
+PARAMETERS:
+info        - Pointer to VGA device information to make current
+
+REMARKS:
+This function sets the VGA BIOS functions in the emulator to point to the
+specific VGA BIOS in use. This includes swapping the BIOS interrupt
+vectors, BIOS image and BIOS data area to the new BIOS. This allows the
+real mode BIOS to be swapped without resetting the entire emulator.
+****************************************************************************/
+void PMAPI BE_setVGA(
+    BE_VGAInfo *info)
+{
+    _BE_env.vgaInfo.pciInfo = info->pciInfo;
+    _BE_env.vgaInfo.BIOSImage = info->BIOSImage;
+    if (info->BIOSImage) {
+	_BE_env.biosmem_base = (ulong)info->BIOSImage;
+	_BE_env.biosmem_limit = 0xC0000 + info->BIOSImageLen-1;
+	}
+    else {
+	_BE_env.biosmem_base = _BE_env.busmem_base + 0x20000;
+	_BE_env.biosmem_limit = 0xC7FFF;
+	}
+    if (*((u32*)info->LowMem) == 0)
+	_BE_bios_init((u32*)info->LowMem);
+    memcpy((u8*)M.mem_base,info->LowMem,sizeof(info->LowMem));
+}
+
+/****************************************************************************
+PARAMETERS:
+info        - Pointer to VGA device information to retrieve current
+
+REMARKS:
+This function returns the VGA BIOS functions currently active in the
+emulator, so they can be restored at a later date.
+****************************************************************************/
+void PMAPI BE_getVGA(
+    BE_VGAInfo *info)
+{
+    info->pciInfo = _BE_env.vgaInfo.pciInfo;
+    info->BIOSImage = _BE_env.vgaInfo.BIOSImage;
+    memcpy(info->LowMem,(u8*)M.mem_base,sizeof(info->LowMem));
+}
+
+/****************************************************************************
+PARAMETERS:
+r_seg   - Segment for pointer to convert
+r_off   - Offset for pointer to convert
+
+REMARKS:
+This function maps a real mode pointer in the emulator memory to a protected
+mode pointer that can be used to directly access the memory.
+
+NOTE:   The memory is *always* in little endian format, son on non-x86
+	systems you will need to do endian translations to access this
+	memory.
+****************************************************************************/
+void * PMAPI BE_mapRealPointer(
+    uint r_seg,
+    uint r_off)
+{
+    u32 addr = ((u32)r_seg << 4) + r_off;
+
+    if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
+	return (void*)(_BE_env.biosmem_base + addr - 0xC0000);
+	}
+    else if (addr >= 0xA0000 && addr <= 0xFFFFF) {
+	return (void*)(_BE_env.busmem_base + addr - 0xA0000);
+	}
+    return (void*)(M.mem_base + addr);
+}
+
+/****************************************************************************
+PARAMETERS:
+len     - Return the length of the VESA buffer
+rseg    - Place to store VESA buffer segment
+roff    - Place to store VESA buffer offset
+
+REMARKS:
+This function returns the address of the VESA transfer buffer in real
+mode emulator memory. The VESA transfer buffer is always 1024 bytes long,
+and located at 15Kb into the start of the real mode memory (16Kb is where
+we put the real mode code we execute for issuing interrupts).
+
+NOTE:   The memory is *always* in little endian format, son on non-x86
+	systems you will need to do endian translations to access this
+	memory.
+****************************************************************************/
+void * PMAPI BE_getVESABuf(
+    uint *len,
+    uint *rseg,
+    uint *roff)
+{
+    *len = 1024;
+    *rseg = SEG(0x03C00);
+    *roff = OFF(0x03C00);
+    return (void*)(M.mem_base + ((u32)*rseg << 4) + *roff);
+}
+
+/****************************************************************************
+REMARKS:
+Cleans up and exits the emulator.
+****************************************************************************/
+void PMAPI BE_exit(void)
+{
+    free((void*)M.mem_base);
+    PM_freePhysicalAddr((void*)_BE_env.busmem_base,0x5FFFF);
+}
+
+/****************************************************************************
+PARAMETERS:
+seg     - Segment of code to call
+off     - Offset of code to call
+regs    - Real mode registers to load
+sregs   - Real mode segment registers to load
+
+REMARKS:
+This functions calls a real mode far function at the specified address,
+and loads all the x86 registers from the passed in registers structure.
+On exit the registers returned from the call are returned in the same
+structures.
+****************************************************************************/
+void PMAPI BE_callRealMode(
+    uint seg,
+    uint off,
+    RMREGS *regs,
+    RMSREGS *sregs)
+{
+    M.x86.R_EAX = regs->e.eax;
+    M.x86.R_EBX = regs->e.ebx;
+    M.x86.R_ECX = regs->e.ecx;
+    M.x86.R_EDX = regs->e.edx;
+    M.x86.R_ESI = regs->e.esi;
+    M.x86.R_EDI = regs->e.edi;
+    M.x86.R_DS = sregs->ds;
+    M.x86.R_ES = sregs->es;
+    M.x86.R_FS = sregs->fs;
+    M.x86.R_GS = sregs->gs;
+    M.x86.R_CS = (u16)seg;
+    M.x86.R_IP = (u16)off;
+    M.x86.R_SS = SEG(M.mem_size - 1);
+    M.x86.R_SP = OFF(M.mem_size - 1);
+    X86EMU_exec();
+    regs->e.cflag = M.x86.R_EFLG & F_CF;
+    regs->e.eax = M.x86.R_EAX;
+    regs->e.ebx = M.x86.R_EBX;
+    regs->e.ecx = M.x86.R_ECX;
+    regs->e.edx = M.x86.R_EDX;
+    regs->e.esi = M.x86.R_ESI;
+    regs->e.edi = M.x86.R_EDI;
+    sregs->ds = M.x86.R_DS;
+    sregs->es = M.x86.R_ES;
+    sregs->fs = M.x86.R_FS;
+    sregs->gs = M.x86.R_GS;
+}
+
+/****************************************************************************
+PARAMETERS:
+intno   - Interrupt number to execute
+in      - Real mode registers to load
+out     - Place to store resulting real mode registers
+
+REMARKS:
+This functions calls a real mode interrupt function at the specified address,
+and loads all the x86 registers from the passed in registers structure.
+On exit the registers returned from the call are returned in out stucture.
+****************************************************************************/
+int PMAPI BE_int86(
+    int intno,
+    RMREGS *in,
+    RMREGS *out)
+{
+    M.x86.R_EAX = in->e.eax;
+    M.x86.R_EBX = in->e.ebx;
+    M.x86.R_ECX = in->e.ecx;
+    M.x86.R_EDX = in->e.edx;
+    M.x86.R_ESI = in->e.esi;
+    M.x86.R_EDI = in->e.edi;
+    ((u8*)M.mem_base)[0x4000] = 0xCD;
+    ((u8*)M.mem_base)[0x4001] = (u8)intno;
+    ((u8*)M.mem_base)[0x4002] = 0xC3;
+    M.x86.R_CS = SEG(0x04000);
+    M.x86.R_IP = OFF(0x04000);
+    M.x86.R_SS = SEG(M.mem_size - 1);
+    M.x86.R_SP = OFF(M.mem_size - 1);
+    X86EMU_exec();
+    out->e.cflag = M.x86.R_EFLG & F_CF;
+    out->e.eax = M.x86.R_EAX;
+    out->e.ebx = M.x86.R_EBX;
+    out->e.ecx = M.x86.R_ECX;
+    out->e.edx = M.x86.R_EDX;
+    out->e.esi = M.x86.R_ESI;
+    out->e.edi = M.x86.R_EDI;
+    return out->x.ax;
+}
+
+/****************************************************************************
+PARAMETERS:
+intno   - Interrupt number to execute
+in      - Real mode registers to load
+out     - Place to store resulting real mode registers
+sregs   - Real mode segment registers to load
+
+REMARKS:
+This functions calls a real mode interrupt function at the specified address,
+and loads all the x86 registers from the passed in registers structure.
+On exit the registers returned from the call are returned in out stucture.
+****************************************************************************/
+int PMAPI BE_int86x(
+    int intno,
+    RMREGS *in,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    M.x86.R_EAX = in->e.eax;
+    M.x86.R_EBX = in->e.ebx;
+    M.x86.R_ECX = in->e.ecx;
+    M.x86.R_EDX = in->e.edx;
+    M.x86.R_ESI = in->e.esi;
+    M.x86.R_EDI = in->e.edi;
+    M.x86.R_DS = sregs->ds;
+    M.x86.R_ES = sregs->es;
+    M.x86.R_FS = sregs->fs;
+    M.x86.R_GS = sregs->gs;
+    ((u8*)M.mem_base)[0x4000] = 0xCD;
+    ((u8*)M.mem_base)[0x4001] = (u8)intno;
+    ((u8*)M.mem_base)[0x4002] = 0xC3;
+    M.x86.R_CS = SEG(0x04000);
+    M.x86.R_IP = OFF(0x04000);
+    M.x86.R_SS = SEG(M.mem_size - 1);
+    M.x86.R_SP = OFF(M.mem_size - 1);
+    X86EMU_exec();
+    out->e.cflag = M.x86.R_EFLG & F_CF;
+    out->e.eax = M.x86.R_EAX;
+    out->e.ebx = M.x86.R_EBX;
+    out->e.ecx = M.x86.R_ECX;
+    out->e.edx = M.x86.R_EDX;
+    out->e.esi = M.x86.R_ESI;
+    out->e.edi = M.x86.R_EDI;
+    sregs->ds = M.x86.R_DS;
+    sregs->es = M.x86.R_ES;
+    sregs->fs = M.x86.R_FS;
+    sregs->gs = M.x86.R_GS;
+    return out->x.ax;
+}
+
+#ifdef  __DRIVER__
+
+/****************************************************************************
+REMARKS:
+Empty log function for binary portable DLL. The BPD is compiled without
+debug information, so very little is logged anyway so it is simpler this
+way.
+****************************************************************************/
+void printk(const char *msg, ...)
+{
+}
+
+/****************************************************************************
+REMARKS:
+Fatal error handler called when a non-imported function is called by the
+driver. We leave this to a runtime error so that older applications and
+shell drivers will work with newer bpd drivers provided no newer functions
+are required by the driver itself. If they are, the application or shell
+driver needs to be recompiled.
+****************************************************************************/
+static void _PM_fatalErrorHandler(void)
+{
+    PM_fatalError("Unsupported PM_imports import function called! Please re-compile!\n");
+}
+
+/****************************************************************************
+PARAMETERS:
+beImp   - BE library imports
+beImp   - Generic emulator imports
+
+RETURNS:
+Pointer to exported function list
+
+REMARKS:
+This function initialises the BIOS emulator library and returns the list of
+loader library exported functions.
+{secret}
+****************************************************************************/
+BE_exports * _CEXPORT BE_initLibrary(
+    PM_imports *pmImp)
+{
+    static BE_exports _BE_exports = {
+	sizeof(BE_exports),
+	BE_init,
+	BE_setVGA,
+	BE_getVGA,
+	BE_mapRealPointer,
+	BE_getVESABuf,
+	BE_callRealMode,
+	BE_int86,
+	BE_int86x,
+	NULL,
+	BE_exit,
+	};
+    int     i,max;
+    ulong   *p;
+
+    /* Initialize all default imports to point to fatal error handler */
+    /* for upwards compatibility. */
+    max = sizeof(_PM_imports)/sizeof(BE_initLibrary_t);
+    for (i = 0,p = (ulong*)&_PM_imports; i < max; i++)
+	*p++ = (ulong)_PM_fatalErrorHandler;
+
+    /* Now copy all our imported functions */
+    memcpy(&_PM_imports,pmImp,MIN(sizeof(_PM_imports),pmImp->dwSize));
+    return &_BE_exports;
+}
+
+#endif  /* __DRIVER__ */
diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h b/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h
new file mode 100755
index 0000000..23edebc
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h
@@ -0,0 +1,79 @@
+/****************************************************************************
+*
+*                        BIOS emulator and interface
+*                      to Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Internal header file for the BIOS emulator library.
+*
+****************************************************************************/
+
+#ifndef __BIOSEMUI_H
+#define __BIOSEMUI_H
+
+#include <biosemu.h>
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+#ifdef DEBUG
+#define DB(x)   x
+#else
+#define DB(x)
+#endif
+
+#define BIOS_SEG        0xfff0
+
+#define M               _X86EMU_env
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+/* bios.c */
+
+void    _BE_bios_init(u32 *intrTab);
+void    _BE_setup_funcs(void);
+
+/* besys.c */
+
+u8      X86API BE_rdb(u32 addr);
+u16     X86API BE_rdw(u32 addr);
+u32     X86API BE_rdl(u32 addr);
+void    X86API BE_wrb(u32 addr,u8 val);
+void    X86API BE_wrw(u32 addr,u16 val);
+void    X86API BE_wrl(u32 addr,u32 val);
+#ifdef  DEBUG
+u8      X86API BE_inb(int port);
+u16     X86API BE_inw(int port);
+u32     X86API BE_inl(int port);
+void    X86API BE_outb(int port, u8 val);
+void    X86API BE_outw(int port, u16 val);
+void    X86API BE_outl(int port, u32 val);
+#endif
+
+#endif /* __BIOSEMUI_H */
diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/makefile b/board/MAI/bios_emulator/scitech/src/biosemu/makefile
new file mode 100755
index 0000000..80730b2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/biosemu/makefile
@@ -0,0 +1,99 @@
+#############################################################################
+#
+#                        BIOS emulator and interface
+#                      to Realmode X86 Emulator Library
+#
+#               Copyright (C) 1996-1999 SciTech Software, Inc.
+#
+#  ========================================================================
+#
+#  Permission to use, copy, modify, distribute, and sell this software and
+#  its documentation for any purpose is hereby granted without fee,
+#  provided that the above copyright notice appear in all copies and that
+#  both that copyright notice and this permission notice appear in
+#  supporting documentation, and that the name of the authors not be used
+#  in advertising or publicity pertaining to distribution of the software
+#  without specific, written prior permission.  The authors makes no
+#  representations about the suitability of this software for any purpose.
+#  It is provided "as is" without express or implied warranty.
+#
+#  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+#  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+#  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+#  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+#  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+#  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+#  PERFORMANCE OF THIS SOFTWARE.
+#
+#  ========================================================================
+#
+# Descripton:   Generic makefile for the x86emu library. Requires
+#               the SciTech Software makefile definitions package to be
+#               installed, which uses the DMAKE make program.
+#
+#############################################################################
+
+.IMPORT .IGNORE: DEBUG
+
+#----------------------------------------------------------------------------
+# Define the lists of object files
+#----------------------------------------------------------------------------
+
+DLL_OBJS        = dllstart$O _pm_imp$O
+BIOS_OBJS       = biosemu$O bios$O besys$O
+X86_OBJS        = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O
+CFLAGS          += -DSCITECH -I$(SCITECH)\src\x86emu
+
+.IF $(BUILD_DLL)
+
+CFLAGS          += -I$(PRIVATE)\include\drvlib -I$(SCITECH)\include\drvlib -D__DRIVER__
+ASFLAGS         += -d__DRIVER__
+EXELIBS         = drvlib$L
+
+.ELSE
+
+.IF $(DEBUG)
+CFLAGS          += -DDEBUG
+.ENDIF
+OBJECTS         = $(BIOS_OBJS) $(X86_OBJS)
+LIBCLEAN        = *.dll *.lib *.a
+LIBFILE         = $(LP)biosemu$L
+
+.ENDIF
+
+#----------------------------------------------------------------------------
+# Sample test programs
+#----------------------------------------------------------------------------
+
+all: $(LIBFILE) warmboot$E
+
+warmboot$E: warmboot$O $(LIBFILE)
+
+#----------------------------------------------------------------------------
+# Target to build the Binary Portable DLL target
+#----------------------------------------------------------------------------
+
+biosemu.dll: $(DLL_OBJS) $(BIOS_OBJS) $(X86_OBJS)
+
+#----------------------------------------------------------------------------
+# Target to build all Intel binary drivers
+#----------------------------------------------------------------------------
+
+.PHONY mkdrv:
+    @build wc11-w32 biosemu.dll -u BUILD_DLL=1 NO_RUNTIME=1 OPT=1
+    @$(CP) biosemu.dll $(PRIVATE)\nucleus\graphics\biosemu.bpd
+    @dmake cleanexe
+
+.PHONY db:
+    @build wc11-w32 biosemu.dll BUILD_DLL=1 NO_RUNTIME=1 OPT=1
+    @$(CP) biosemu.dll $(PRIVATE)\nucleus\graphics\biosemu.bpd
+
+#----------------------------------------------------------------------------
+# Define the list of object files to create dependency information for
+#----------------------------------------------------------------------------
+
+DEPEND_OBJ      = warmboot$O $(BIOS_OBJS) $(X86_OBJS) $(DLL_OBJS)
+DEPEND_SRC      = $(SCITECH)/src/x86emu;$(PRIVATE)/src/common
+.SOURCE:          $(SCITECH)/src/x86emu $(PRIVATE)/src/common
+
+.INCLUDE: "$(SCITECH)/makedefs/common.mk"
diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross b/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross
new file mode 100755
index 0000000..9141003
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross
@@ -0,0 +1,10 @@
+CC = ppc-elf32-gcc
+AR = ppc-elf32-ar
+
+CFLAGS = -D__DRIVER__ -I../../include -DDEBUG -I.
+
+BIOS_OBJS = biosemu.o bios.o besys.o
+X86_OBJS = sys.o decode.o ops.o prim_ops.o fpu.o debug.o
+
+libbios.a: $(BIOS_OBJS)
+	$(AR) rcs libbios.a $(BIOS_OBJS)
\ No newline at end of file
diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c b/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c
new file mode 100755
index 0000000..98d5fb8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c
@@ -0,0 +1,569 @@
+/****************************************************************************
+*
+*                        BIOS emulator and interface
+*                      to Realmode X86 Emulator Library
+*
+*               Copyright (C) 1996-1999 SciTech Software, Inc.
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+* Developer:    Kendall Bennett
+*
+* Description:  Module to implement warm booting of all PCI/AGP controllers
+*               on the bus. We use the x86 real mode emulator to run the
+*               BIOS on the primary and secondary controllers to bring
+*               the cards up.
+*
+****************************************************************************/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+#include "biosemu.h"
+#ifndef _MAX_PATH
+#define _MAX_PATH 256
+#endif
+
+/*------------------------- Global Variables ------------------------------*/
+
+static PCIDeviceInfo    PCI[MAX_PCI_DEVICES];
+static int              NumPCI = -1;
+static int              BridgeIndex[MAX_PCI_DEVICES] = {0};
+static int              NumBridges;
+static PCIBridgeInfo    *AGPBridge = NULL;
+static int              DeviceIndex[MAX_PCI_DEVICES] = {0};
+static int              NumDevices;
+static u32              debugFlags = 0;
+static BE_VGAInfo       VGAInfo[MAX_PCI_DEVICES] = {{0}};
+static ibool            useV86 = false;
+static ibool            forcePost = false;
+
+/* Length of the BIOS image */
+
+#define MAX_BIOSLEN         (64 * 1024L)
+#define FINAL_BIOSLEN       (32 * 1024L)
+
+/* Macro to determine if the VGA is enabled and responding */
+
+#define VGA_NOT_ACTIVE()    (forcePost || (PM_inpb(0x3CC) == 0xFF) || ((PM_inpb(0x3CC) & 0x2) == 0))
+
+#define ENABLE_DEVICE(device)   \
+    PCI_writePCIRegB(0x4,PCI[DeviceIndex[device]].Command | 0x7,device)
+
+#define DISABLE_DEVICE(device)  \
+    PCI_writePCIRegB(0x4,0,device)
+
+/* Macros to enable and disable AGP VGA resources */
+
+#define ENABLE_AGP_VGA()    \
+    PCI_accessReg(0x3E,AGPBridge->BridgeControl | 0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge)
+
+#define DISABLE_AGP_VGA()   \
+    PCI_accessReg(0x3E,AGPBridge->BridgeControl & ~0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge)
+
+#define RESTORE_AGP_VGA()   \
+    PCI_accessReg(0x3E,AGPBridge->BridgeControl,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge)
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+RETURNS:
+The address to use to map the secondary BIOS (PCI/AGP devices)
+
+REMARKS:
+Searches all the PCI base address registers for the device looking for a
+memory mapping that is large enough to hold our ROM BIOS. We usually end up
+finding the framebuffer mapping (usually BAR 0x10), and we use this mapping
+to map the BIOS for the device into. We use a mapping that is already
+assigned to the device to ensure the memory range will be passed through
+by any PCI->PCI or AGP->PCI bridge that may be present.
+
+NOTE: Usually this function is only used for AGP devices, but it may be
+      used for PCI devices that have already been POST'ed and the BIOS
+      ROM base address has been zero'ed out.
+****************************************************************************/
+static ulong PCI_findBIOSAddr(
+    int device)
+{
+    ulong   base,size;
+    int     bar;
+
+    for (bar = 0x10; bar <= 0x14; bar++) {
+	base = PCI_readPCIRegL(bar,device) & ~0xFF;
+	if (!(base & 0x1)) {
+	    PCI_writePCIRegL(bar,0xFFFFFFFF,device);
+	    size = PCI_readPCIRegL(bar,device) & ~0xFF;
+	    size = ~size+1;
+	    PCI_writePCIRegL(bar,0,device);
+	    if (size >= MAX_BIOSLEN)
+		return base;
+	    }
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Re-writes the PCI base address registers for the secondary PCI controller
+with the values from our initial PCI bus enumeration. This fixes up the
+values after we have POST'ed the secondary display controller BIOS, which
+may have incorrectly re-programmed the base registers the same as the
+primary display controller (the case for identical S3 cards).
+****************************************************************************/
+static void _PCI_fixupSecondaryBARs(void)
+{
+    int i;
+
+    for (i = 0; i < NumDevices; i++) {
+	PCI_writePCIRegL(0x10,PCI[DeviceIndex[i]].BaseAddress10,i);
+	PCI_writePCIRegL(0x14,PCI[DeviceIndex[i]].BaseAddress14,i);
+	PCI_writePCIRegL(0x18,PCI[DeviceIndex[i]].BaseAddress18,i);
+	PCI_writePCIRegL(0x1C,PCI[DeviceIndex[i]].BaseAddress1C,i);
+	PCI_writePCIRegL(0x20,PCI[DeviceIndex[i]].BaseAddress20,i);
+	PCI_writePCIRegL(0x24,PCI[DeviceIndex[i]].BaseAddress24,i);
+	}
+}
+
+/****************************************************************************
+RETURNS:
+True if successfully initialised, false if not.
+
+REMARKS:
+This function executes the BIOS POST code on the controller. We assume that
+at this stage the controller has its I/O and memory space enabled and
+that all other controllers are in a disabled state.
+****************************************************************************/
+static void PCI_doBIOSPOST(
+    int device,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS,
+    ulong BIOSLen)
+{
+    RMREGS          regs;
+    RMSREGS         sregs;
+
+    /* Determine the value to store in AX for BIOS POST */
+    regs.x.ax = (u16)(PCI[DeviceIndex[device]].slot.i >> 8);
+    if (useV86) {
+	/* Post the BIOS using the PM functions (ie: v86 mode on Linux) */
+	if (!PM_doBIOSPOST(regs.x.ax,BIOSPhysAddr,mappedBIOS,BIOSLen)) {
+	    /* If the PM function fails, this probably means are we are on */
+	    /* DOS and can't re-map the real mode 0xC0000 region. In thise */
+	    /* case if the device is the primary, we can use the real */
+	    /* BIOS at 0xC0000 directly. */
+	    if (device == 0)
+		PM_doBIOSPOST(regs.x.ax,0xC0000,mappedBIOS,BIOSLen);
+	    }
+	}
+    else {
+	/* Setup the X86 emulator for the VGA BIOS */
+	BE_setVGA(&VGAInfo[device]);
+
+	/* Execute the BIOS POST code */
+	BE_callRealMode(0xC000,0x0003,&regs,&sregs);
+
+	/* Cleanup and exit */
+	BE_getVGA(&VGAInfo[device]);
+	}
+}
+
+/****************************************************************************
+RETURNS:
+True if successfully initialised, false if not.
+
+REMARKS:
+Loads and POST's the secondary controllers BIOS, directly from the BIOS
+image we can extract over the PCI bus.
+****************************************************************************/
+static ibool PCI_postControllers(void)
+{
+    int     device;
+    ulong   BIOSImageLen,mappedBIOSPhys;
+    uchar   *mappedBIOS,*copyOfBIOS;
+    char    filename[_MAX_PATH];
+    FILE    *f;
+
+    /* Disable the primary display controller and AGP VGA pass-through */
+    DISABLE_DEVICE(0);
+    if (AGPBridge)
+	DISABLE_AGP_VGA();
+
+    /* Now POST all the secondary controllers */
+    for (device = 0; device < NumDevices; device++) {
+	/* Skip the device if it is not enabled (probably an ISA device) */
+	if (DeviceIndex[device] == -1)
+	    continue;
+
+	/* Enable secondary display controller. If the secondary controller */
+	/* is on the AGP bus, then enable VGA resources for the AGP device. */
+	ENABLE_DEVICE(device);
+	if (AGPBridge && AGPBridge->SecondayBusNumber == PCI[DeviceIndex[device]].slot.p.Bus)
+	    ENABLE_AGP_VGA();
+
+	/* Check if the controller has already been POST'ed */
+	if (VGA_NOT_ACTIVE()) {
+	    /* Find a viable place to map the secondary PCI BIOS image and map it */
+	    printk("Device %d not enabled, so attempting warm boot it\n", device);
+
+	    /* For AGP devices (and PCI devices that do have the ROM base */
+	    /* address zero'ed out) we have to map the BIOS to a location */
+	    /* that is passed by the AGP bridge to the bus. Some AGP devices */
+	    /* have the ROM base address already set up for us, and some */
+	    /* do not (we map to one of the existing BAR locations in */
+	    /* this case). */
+	    mappedBIOS = NULL;
+	    if (PCI[DeviceIndex[device]].ROMBaseAddress != 0)
+		mappedBIOSPhys = PCI[DeviceIndex[device]].ROMBaseAddress & ~0xF;
+	    else
+		mappedBIOSPhys = PCI_findBIOSAddr(device);
+	    printk("Mapping BIOS image to 0x%08X\n", mappedBIOSPhys);
+	    mappedBIOS = PM_mapPhysicalAddr(mappedBIOSPhys,MAX_BIOSLEN-1,false);
+	    PCI_writePCIRegL(0x30,mappedBIOSPhys | 0x1,device);
+	    BIOSImageLen = mappedBIOS[2] * 512;
+	    if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL)
+		return false;
+	    memcpy(copyOfBIOS,mappedBIOS,BIOSImageLen);
+	    PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1);
+
+	    /* Allocate memory to store copy of BIOS from secondary controllers */
+	    VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]];
+	    VGAInfo[device].BIOSImage = copyOfBIOS;
+	    VGAInfo[device].BIOSImageLen = BIOSImageLen;
+
+	    /* Restore device mappings */
+	    PCI_writePCIRegL(0x30,PCI[DeviceIndex[device]].ROMBaseAddress,device);
+	    PCI_writePCIRegL(0x10,PCI[DeviceIndex[device]].BaseAddress10,device);
+	    PCI_writePCIRegL(0x14,PCI[DeviceIndex[device]].BaseAddress14,device);
+
+	    /* Now execute the BIOS POST for the device */
+	    if (copyOfBIOS[0] == 0x55 && copyOfBIOS[1] == 0xAA) {
+		printk("Executing BIOS POST for controller.\n");
+		PCI_doBIOSPOST(device,mappedBIOSPhys,copyOfBIOS,BIOSImageLen);
+		}
+
+	    /* Reset the size of the BIOS image to the final size */
+	    VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN;
+
+	    /* Save the BIOS and interrupt vector information to disk */
+	    sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device);
+	    if ((f = fopen(filename,"wb")) != NULL) {
+		fwrite(copyOfBIOS,1,FINAL_BIOSLEN,f);
+		fwrite(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f);
+		fclose(f);
+		}
+	    }
+	else {
+	    /* Allocate memory to store copy of BIOS from secondary controllers */
+	    if ((copyOfBIOS = malloc(FINAL_BIOSLEN)) == NULL)
+		return false;
+	    VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]];
+	    VGAInfo[device].BIOSImage = copyOfBIOS;
+	    VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN;
+
+	    /* Load the BIOS and interrupt vector information from disk */
+	    sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device);
+	    if ((f = fopen(filename,"rb")) != NULL) {
+		fread(copyOfBIOS,1,FINAL_BIOSLEN,f);
+		fread(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f);
+		fclose(f);
+		}
+	    }
+
+	/* Fix up all the secondary PCI base address registers */
+	/* (restores them all from the values we read previously) */
+	_PCI_fixupSecondaryBARs();
+
+	/* Disable the secondary controller and AGP VGA pass-through */
+	DISABLE_DEVICE(device);
+	if (AGPBridge)
+	    DISABLE_AGP_VGA();
+	}
+
+    /* Reenable primary display controller and reset AGP bridge control */
+    if (AGPBridge)
+	RESTORE_AGP_VGA();
+    ENABLE_DEVICE(0);
+
+    /* Free physical BIOS image mapping */
+    PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1);
+
+    /* Restore the X86 emulator BIOS info to primary controller */
+    if (!useV86)
+	BE_setVGA(&VGAInfo[0]);
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Enumerates the PCI bus and dumps the PCI configuration information to the
+log file.
+****************************************************************************/
+static void EnumeratePCI(void)
+{
+    int             i,index;
+    PCIBridgeInfo   *info;
+
+    printk("Displaying enumeration of PCI bus (%d devices, %d display devices)\n",
+	NumPCI, NumDevices);
+    for (index = 0; index < NumDevices; index++)
+	printk("  Display device %d is PCI device %d\n",index,DeviceIndex[index]);
+    printk("\n");
+    printk("Bus Slot Fnc DeviceID  SubSystem Rev Class IRQ Int Cmd\n");
+    for (i = 0; i < NumPCI; i++) {
+	printk("%2d   %2d  %2d  %04X:%04X %04X:%04X %02X  %02X:%02X %02X  %02X  %04X   ",
+	    PCI[i].slot.p.Bus,
+	    PCI[i].slot.p.Device,
+	    PCI[i].slot.p.Function,
+	    PCI[i].VendorID,
+	    PCI[i].DeviceID,
+	    PCI[i].SubSystemVendorID,
+	    PCI[i].SubSystemID,
+	    PCI[i].RevID,
+	    PCI[i].BaseClass,
+	    PCI[i].SubClass,
+	    PCI[i].InterruptLine,
+	    PCI[i].InterruptPin,
+	    PCI[i].Command);
+	for (index = 0; index < NumDevices; index++) {
+	    if (DeviceIndex[index] == i)
+		break;
+	    }
+	if (index < NumDevices)
+	    printk("<- %d\n", index);
+	else
+	    printk("\n");
+	}
+    printk("\n");
+    printk("DeviceID  Stat Ifc Cch Lat Hdr BIST\n");
+    for (i = 0; i < NumPCI; i++) {
+	printk("%04X:%04X %04X  %02X  %02X  %02X  %02X  %02X   ",
+	    PCI[i].VendorID,
+	    PCI[i].DeviceID,
+	    PCI[i].Status,
+	    PCI[i].Interface,
+	    PCI[i].CacheLineSize,
+	    PCI[i].LatencyTimer,
+	    PCI[i].HeaderType,
+	    PCI[i].BIST);
+	for (index = 0; index < NumDevices; index++) {
+	    if (DeviceIndex[index] == i)
+		break;
+	    }
+	if (index < NumDevices)
+	    printk("<- %d\n", index);
+	else
+	    printk("\n");
+	}
+    printk("\n");
+    printk("DeviceID  Base10h  Base14h  Base18h  Base1Ch  Base20h  Base24h  ROMBase\n");
+    for (i = 0; i < NumPCI; i++) {
+	printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ",
+	    PCI[i].VendorID,
+	    PCI[i].DeviceID,
+	    PCI[i].BaseAddress10,
+	    PCI[i].BaseAddress14,
+	    PCI[i].BaseAddress18,
+	    PCI[i].BaseAddress1C,
+	    PCI[i].BaseAddress20,
+	    PCI[i].BaseAddress24,
+	    PCI[i].ROMBaseAddress);
+	for (index = 0; index < NumDevices; index++) {
+	    if (DeviceIndex[index] == i)
+		break;
+	    }
+	if (index < NumDevices)
+	    printk("<- %d\n", index);
+	else
+	    printk("\n");
+	}
+    printk("\n");
+    printk("DeviceID  BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n");
+    for (i = 0; i < NumPCI; i++) {
+	printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ",
+	    PCI[i].VendorID,
+	    PCI[i].DeviceID,
+	    PCI[i].BaseAddress10Len,
+	    PCI[i].BaseAddress14Len,
+	    PCI[i].BaseAddress18Len,
+	    PCI[i].BaseAddress1CLen,
+	    PCI[i].BaseAddress20Len,
+	    PCI[i].BaseAddress24Len,
+	    PCI[i].ROMBaseAddressLen);
+	for (index = 0; index < NumDevices; index++) {
+	    if (DeviceIndex[index] == i)
+		break;
+	    }
+	if (index < NumDevices)
+	    printk("<- %d\n", index);
+	else
+	    printk("\n");
+	}
+    printk("\n");
+    printk("Displaying enumeration of %d bridge devices\n",NumBridges);
+    printk("\n");
+    printk("DeviceID  P# S# B# IOB  IOL  MemBase  MemLimit PreBase  PreLimit Ctrl\n");
+    for (i = 0; i < NumBridges; i++) {
+	info = (PCIBridgeInfo*)&PCI[BridgeIndex[i]];
+	printk("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n",
+	    info->VendorID,
+	    info->DeviceID,
+	    info->PrimaryBusNumber,
+	    info->SecondayBusNumber,
+	    info->SubordinateBusNumber,
+	    ((u16)info->IOBase << 8) & 0xF000,
+	    info->IOLimit ?
+		((u16)info->IOLimit << 8) | 0xFFF : 0,
+	    ((u32)info->MemoryBase << 16) & 0xFFF00000,
+	    info->MemoryLimit ?
+		((u32)info->MemoryLimit << 16) | 0xFFFFF : 0,
+	    ((u32)info->PrefetchableMemoryBase << 16) & 0xFFF00000,
+	    info->PrefetchableMemoryLimit ?
+		((u32)info->PrefetchableMemoryLimit << 16) | 0xFFFFF : 0,
+	    info->BridgeControl);
+	}
+    printk("\n");
+}
+
+/****************************************************************************
+RETURNS:
+Number of display devices found.
+
+REMARKS:
+This function enumerates the number of available display devices on the
+PCI bus, and returns the number found.
+****************************************************************************/
+static int PCI_enumerateDevices(void)
+{
+    int             i,j;
+    PCIBridgeInfo   *info;
+
+    /* If this is the first time we have been called, enumerate all */
+    /* devices on the PCI bus. */
+    if (NumPCI == -1) {
+	for (i = 0; i < MAX_PCI_DEVICES; i++)
+	    PCI[i].dwSize = sizeof(PCI[i]);
+	if ((NumPCI = PCI_enumerate(PCI,MAX_PCI_DEVICES)) == 0)
+	    return -1;
+
+	/* Build a list of all PCI bridge devices */
+	for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) {
+	    if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) {
+		if (NumBridges < MAX_PCI_DEVICES)
+		    BridgeIndex[NumBridges++] = i;
+		}
+	    }
+
+	/* Now build a list of all display class devices */
+	for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) {
+	    if (PCI_IS_DISPLAY_CLASS(&PCI[i])) {
+		if ((PCI[i].Command & 0x3) == 0x3) {
+		    DeviceIndex[0] = i;
+		    }
+		else {
+		    if (NumDevices < MAX_PCI_DEVICES)
+			DeviceIndex[NumDevices++] = i;
+		    }
+		if (PCI[i].slot.p.Bus != 0) {
+		    /* This device is on a different bus than the primary */
+		    /* PCI bus, so it is probably an AGP device. Find the */
+		    /* AGP bus device that controls that bus so we can */
+		    /* control it. */
+		    for (j = 0; j < NumBridges; j++) {
+			info = (PCIBridgeInfo*)&PCI[BridgeIndex[j]];
+			if (info->SecondayBusNumber == PCI[i].slot.p.Bus) {
+			    AGPBridge = info;
+			    break;
+			    }
+			}
+		    }
+		}
+	    }
+
+	/* Enumerate all PCI and bridge devices to log file */
+	EnumeratePCI();
+	}
+    return NumDevices;
+}
+
+FILE *logfile;
+
+void printk(const char *fmt, ...)
+{
+    va_list argptr;
+    va_start(argptr, fmt);
+    vfprintf(logfile, fmt, argptr);
+    fflush(logfile);
+    va_end(argptr);
+}
+
+int main(int argc,char *argv[])
+{
+    while (argc > 1) {
+	if (stricmp(argv[1],"-usev86") == 0) {
+	    useV86 = true;
+	    }
+	else if (stricmp(argv[1],"-force") == 0) {
+	    forcePost = true;
+	    }
+#ifdef  DEBUG
+	else if (stricmp(argv[1],"-decode") == 0) {
+	    debugFlags |= DEBUG_DECODE_F;
+	    }
+	else if (stricmp(argv[1],"-iotrace") == 0) {
+	    debugFlags |= DEBUG_IO_TRACE_F;
+	    }
+#endif
+	else {
+	    printf("Usage: warmboot [-usev86] [-force] [-decode] [-iotrace]\n");
+	    exit(-1);
+	    }
+	argc--;
+	argv++;
+	}
+    if ((logfile = fopen("warmboot.log","w")) == NULL)
+	exit(1);
+
+    PM_init();
+    if (!useV86) {
+	/* Initialise the x86 BIOS emulator */
+	BE_init(false,debugFlags,65536,&VGAInfo[0]);
+	}
+
+    /* Enumerate all devices (which POST's them at the same time) */
+    if (PCI_enumerateDevices() < 1) {
+	printk("No PCI display devices found!\n");
+	return -1;
+	}
+
+    /* Post all the display controller BIOS'es */
+    PCI_postControllers();
+
+    /* Cleanup and exit the emulator */
+    if (!useV86)
+	BE_exit();
+    fclose(logfile);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm
new file mode 100755
index 0000000..61a9024
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm
@@ -0,0 +1,51 @@
+;****************************************************************************
+;*
+;*                     SciTech Nucleus Audio Architecture
+;*
+;*               Copyright (C) 1991-1998 SciTech Software, Inc.
+;*                            All rights reserved.
+;*
+;*  ======================================================================
+;*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+;*  |                                                                    |
+;*  |This copyrighted computer code contains proprietary technology      |
+;*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+;*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+;*  |                                                                    |
+;*  |The contents of this file are subject to the SciTech Nucleus        |
+;*  |License; you may *not* use this file or related software except in  |
+;*  |compliance with the License. You may obtain a copy of the License   |
+;*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+;*  |                                                                    |
+;*  |Software distributed under the License is distributed on an         |
+;*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+;*  |implied. See the License for the specific language governing        |
+;*  |rights and limitations under the License.                           |
+;*  |                                                                    |
+;*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+;*  ======================================================================
+;*
+;* Language:    TASM 4.0 or NASM
+;* Environment: IBM PC 32 bit Protected Mode.
+;*
+;* Description: Module to implement the import stubs for all the Nucleus
+;*              Audio API functions for Intel binary compatible drivers.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+BEGIN_IMPORTS_DEF   _AA_exports
+SKIP_IMP    AA_status                     ; Implemented in C code
+SKIP_IMP    AA_errorMsg                   ; Implemented in C code
+SKIP_IMP    AA_getDaysLeft                ; Implemented in C code
+SKIP_IMP    AA_registerLicense            ; Implemented in C code
+SKIP_IMP    AA_enumerateDevices           ; Implemented in C code
+SKIP_IMP    AA_loadDriver                 ; Implemented in C code
+DECLARE_IMP AA_unloadDriver
+DECLARE_IMP AA_saveOptions
+END_IMPORTS_DEF
+
+        END
diff --git a/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm
new file mode 100755
index 0000000..5317600
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm
@@ -0,0 +1,136 @@
+;****************************************************************************
+;*
+;*                  SciTech Nucleus Graphics Architecture
+;*
+;*               Copyright (C) 1991-1998 SciTech Software, Inc.
+;*                            All rights reserved.
+;*
+;*  ======================================================================
+;*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+;*  |                                                                    |
+;*  |This copyrighted computer code contains proprietary technology      |
+;*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+;*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+;*  |                                                                    |
+;*  |The contents of this file are subject to the SciTech Nucleus        |
+;*  |License; you may *not* use this file or related software except in  |
+;*  |compliance with the License. You may obtain a copy of the License   |
+;*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+;*  |                                                                    |
+;*  |Software distributed under the License is distributed on an         |
+;*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+;*  |implied. See the License for the specific language governing        |
+;*  |rights and limitations under the License.                           |
+;*  |                                                                    |
+;*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+;*  ======================================================================
+;*
+;* Language:    TASM 4.0 or NASM
+;* Environment: IBM PC 32 bit Protected Mode.
+;*
+;* Description: Module to implement the import stubs for all the Nucleus
+;*              Graphics API functions for Intel binary compatible drivers.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+BEGIN_IMPORTS_DEF   __GA_exports
+SKIP_IMP    GA_status,0                     ; Implemented in C code
+SKIP_IMP    GA_errorMsg,1                   ; Implemented in C code
+SKIP_IMP    GA_getDaysLeft,1                ; Implemented in C code
+SKIP_IMP    GA_registerLicense,2            ; Implemented in C code
+SKIP_IMP    GA_enumerateDevices,1           ; Implemented in C code
+SKIP_IMP    GA_loadDriver,2                 ; Implemented in C code
+DECLARE_IMP GA_setActiveDevice,1
+SKIP_IMP    GA_reserved1,0                  ; Implemented in C code
+DECLARE_IMP GA_unloadDriver,1
+DECLARE_IMP REF2D_loadDriver,6
+DECLARE_IMP REF2D_unloadDriver,2
+DECLARE_IMP GA_loadRef2d,5
+DECLARE_IMP GA_unloadRef2d,1
+DECLARE_IMP GA_softStereoInit,1
+DECLARE_IMP GA_softStereoOn,0
+DECLARE_IMP GA_softStereoScheduleFlip,2
+DECLARE_IMP GA_softStereoGetFlipStatus,0
+DECLARE_IMP GA_softStereoWaitTillFlipped,0
+DECLARE_IMP GA_softStereoOff,0
+DECLARE_IMP GA_softStereoExit,0
+DECLARE_IMP GA_saveModeProfile,2
+DECLARE_IMP GA_saveOptions,2
+DECLARE_IMP GA_saveCRTCTimings,1
+DECLARE_IMP GA_restoreCRTCTimings,1
+DECLARE_IMP DDC_init,1
+DECLARE_IMP DDC_readEDID,5
+DECLARE_IMP EDID_parse,3
+DECLARE_IMP MCS_begin,1
+DECLARE_IMP MCS_getCapabilitiesString,2
+DECLARE_IMP MCS_isControlSupported,1
+DECLARE_IMP MCS_enableControl,2
+DECLARE_IMP MCS_getControlMax,2
+DECLARE_IMP MCS_getControlValue,2
+DECLARE_IMP MCS_getControlValues,3
+DECLARE_IMP MCS_setControlValue,2
+DECLARE_IMP MCS_setControlValues,3
+DECLARE_IMP MCS_resetControl,1
+DECLARE_IMP MCS_saveCurrentSettings,0
+DECLARE_IMP MCS_getTimingReport,3
+DECLARE_IMP MCS_getSelfTestReport,3
+DECLARE_IMP MCS_end,0
+SKIP_IMP    GA_loadInGUI,1                  ; Implemented in C code
+DECLARE_IMP DDC_writeEDID,6
+DECLARE_IMP GA_useDoubleScan,1
+DECLARE_IMP GA_getMaxRefreshRate,4
+DECLARE_IMP GA_computeCRTCTimings,6
+DECLARE_IMP GA_addMode,5
+DECLARE_IMP GA_addRefresh,5
+DECLARE_IMP GA_delMode,5
+DECLARE_IMP N_getLogName,0
+SKIP_IMP2   N_log
+DECLARE_IMP MDBX_getErrCode,0
+DECLARE_IMP MDBX_getErrorMsg,0
+DECLARE_IMP MDBX_open,1
+DECLARE_IMP MDBX_close,0
+DECLARE_IMP MDBX_first,1
+DECLARE_IMP MDBX_last,1
+DECLARE_IMP MDBX_next,1
+DECLARE_IMP MDBX_prev,1
+DECLARE_IMP MDBX_insert,1
+DECLARE_IMP MDBX_update,1
+DECLARE_IMP MDBX_flush,0
+DECLARE_IMP MDBX_importINF,2
+SKIP_IMP    GA_getGlobalOptions,2           ; Implemented in C code
+DECLARE_IMP GA_setGlobalOptions,1
+DECLARE_IMP GA_saveGlobalOptions,1
+DECLARE_IMP GA_getInternalName,1
+DECLARE_IMP GA_getNucleusConfigPath,0
+DECLARE_IMP GA_getFakePCIID,0
+SKIP_IMP    GA_loadLibrary,3                ; Implemented in C code
+SKIP_IMP    GA_isOEMVersion,1               ; Implemented in C code
+DECLARE_IMP GA_isLiteVersion,1
+DECLARE_IMP GA_getDisplaySerialNo,1
+DECLARE_IMP GA_getDisplayUserName,1
+SKIP_IMP    GA_getCurrentDriver,1           ; Implemented in C code
+SKIP_IMP    GA_getCurrentRef2d,1            ; Implemented in C code
+SKIP_IMP    GA_getLicensedDevices,1         ; Implemented in C code
+DECLARE_IMP DDC_initExt,2
+DECLARE_IMP MCS_beginExt,2
+DECLARE_IMP GA_loadRegionMgr,3
+DECLARE_IMP GA_unloadRegionMgr,1
+DECLARE_IMP GA_getProcAddress,2
+DECLARE_IMP GA_enableVBEMode,5
+DECLARE_IMP GA_disableVBEMode,5
+DECLARE_IMP GA_loadModeProfile,2
+DECLARE_IMP GA_getCRTCTimings,4
+DECLARE_IMP GA_setCRTCTimings,4
+DECLARE_IMP GA_setDefaultRefresh,6
+DECLARE_IMP GA_saveMonitorInfo,2
+DECLARE_IMP GA_detectPnPMonitor,3
+SKIP_IMP3   GA_queryFunctions
+SKIP_IMP3   REF2D_queryFunctions
+END_IMPORTS_DEF
+
+        END
+
diff --git a/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm b/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm
new file mode 100755
index 0000000..0194a62
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm
@@ -0,0 +1,248 @@
+;****************************************************************************
+;*
+;*                  SciTech Nucleus Graphics Architecture
+;*
+;*               Copyright (C) 1991-1998 SciTech Software, Inc.
+;*                            All rights reserved.
+;*
+;*  ======================================================================
+;*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+;*  |                                                                    |
+;*  |This copyrighted computer code contains proprietary technology      |
+;*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+;*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+;*  |                                                                    |
+;*  |The contents of this file are subject to the SciTech Nucleus        |
+;*  |License; you may *not* use this file or related software except in  |
+;*  |compliance with the License. You may obtain a copy of the License   |
+;*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+;*  |                                                                    |
+;*  |Software distributed under the License is distributed on an         |
+;*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+;*  |implied. See the License for the specific language governing        |
+;*  |rights and limitations under the License.                           |
+;*  |                                                                    |
+;*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+;*  ======================================================================
+;*
+;* Language:    80386 Assembler, NASM or TASM
+;* Environment: IBM PC 32 bit Protected Mode.
+;*
+;* Description: Assembly support functions for the Nucleus library for
+;*              the high resolution timing support functions provided by
+;*              the Intel Pentium and compatible processors.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+header  _gatimer
+
+begcodeseg  _gatimer
+
+ifdef   USE_NASM
+%macro mCPU_ID 0
+db  00Fh,0A2h
+%endmacro
+else
+MACRO   mCPU_ID
+db  00Fh,0A2h
+ENDM
+endif
+
+ifdef   USE_NASM
+%macro mRDTSC 0
+db  00Fh,031h
+%endmacro
+else
+MACRO   mRDTSC
+db  00Fh,031h
+ENDM
+endif
+
+;----------------------------------------------------------------------------
+; bool _GA_haveCPUID(void)
+;----------------------------------------------------------------------------
+; Determines if we have support for the CPUID instruction.
+;----------------------------------------------------------------------------
+cprocstart  _GA_haveCPUID
+
+        enter_c
+        pushfd                      ; Get original EFLAGS
+        pop     eax
+        mov     ecx, eax
+        xor     eax, 200000h        ; Flip ID bit in EFLAGS
+        push    eax                 ; Save new EFLAGS value on stack
+        popfd                       ; Replace current EFLAGS value
+        pushfd                      ; Get new EFLAGS
+        pop     eax                 ; Store new EFLAGS in EAX
+        xor     eax, ecx            ; Can not toggle ID bit,
+        jnz     @@1                 ; Processor=80486
+        mov     eax,0               ; We dont have CPUID support
+        jmp     @@Done
+@@1:    mov     eax,1               ; We have CPUID support
+@@Done: leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uint _GA_getCPUIDFeatures(void)
+;----------------------------------------------------------------------------
+; Determines the CPU type using the CPUID instruction.
+;----------------------------------------------------------------------------
+cprocstart  _GA_getCPUIDFeatures
+
+        enter_c
+
+        xor     eax, eax            ; Set up for CPUID instruction
+        mCPU_ID                     ; Get and save vendor ID
+        cmp     eax, 1              ; Make sure 1 is valid input for CPUID
+        jl      @@Fail              ; We dont have the CPUID instruction
+        xor     eax, eax
+        inc     eax
+        mCPU_ID                     ; Get family/model/stepping/features
+        mov     eax, edx
+@@Done: leave_c
+        ret
+
+@@Fail: xor     eax,eax
+        jmp     @@Done
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void  _GA_readTimeStamp(GA_largeInteger *time)
+;----------------------------------------------------------------------------
+; Reads the time stamp counter and returns the 64-bit result.
+;----------------------------------------------------------------------------
+cprocstart  _GA_readTimeStamp
+
+        mRDTSC
+        mov     ecx,[esp+4]     ; Access directly without stack frame
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; N_uint32 GA_TimerDifference(GA_largeInteger *a,GA_largeInteger *b)
+;----------------------------------------------------------------------------
+; Computes the difference between two 64-bit numbers (a-b)
+;----------------------------------------------------------------------------
+cprocstart  GA_TimerDifference
+
+        ARG     a:DPTR, b:DPTR, t:DPTR
+
+        enter_c
+
+        mov     ecx,[a]
+        mov     eax,[ecx]       ; EAX := b.low
+        mov     ecx,[b]
+        sub     eax,[ecx]
+        mov     edx,eax         ; EDX := low difference
+        mov     ecx,[a]
+        mov     eax,[ecx+4]     ; ECX := b.high
+        mov     ecx,[b]
+        sbb     eax,[ecx+4]     ; EAX := high difference
+        mov     eax,edx         ; Return low part
+
+        leave_c
+        ret
+
+cprocend
+
+; Macro to delay briefly to ensure that enough time has elapsed between
+; successive I/O accesses so that the device being accessed can respond
+; to both accesses even on a very fast PC.
+
+ifdef   USE_NASM
+%macro  DELAY_TIMER 0
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+%endmacro
+else
+macro   DELAY_TIMER
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+endm
+endif
+
+;----------------------------------------------------------------------------
+; void _OS_delay8253(N_uint32 microSeconds);
+;----------------------------------------------------------------------------
+; Delays for the specified number of microseconds, by directly programming
+; the 8253 timer chips.
+;----------------------------------------------------------------------------
+cprocstart  _OS_delay8253
+
+        ARG     microSec:UINT
+
+        enter_c
+
+; Start timer 2 counting
+
+        mov     _ax,[microSec]      ; EAX := count in microseconds
+        mov     ecx,1196
+        mul     ecx
+        mov     ecx,1000
+        div     ecx
+        mov     ecx,eax             ; ECX := count in timer ticks
+        in      al,61h
+        or      al,1
+        out     61h,al
+
+; Set the timer 2 count to 0 again to start the timing interval.
+
+        mov     al,10110100b        ; set up to load initial (timer 2)
+        out     43h,al              ; timer count
+        DELAY_TIMER
+        sub     al,al
+        out     42h,al              ; load count lsb
+        DELAY_TIMER
+        out     42h,al              ; load count msb
+        xor     di,di               ; Allow max 64K loop iterations
+
+@@LoopStart:
+        dec     di                  ; This is a guard against the possibility that
+        jz      @@LoopEnd           ; someone eg. stopped the timer behind our back.
+                                    ; After 64K iterations we bail out no matter what
+                                    ; (and hope it wasn't too soon)
+        mov     al,00000000b        ; latch timer 0
+        out     43h,al
+        DELAY_TIMER
+        in      al,42h              ; least significant byte
+        DELAY_TIMER
+        mov     ah,al
+        in      al,42h              ; most significant byte
+        xchg    ah,al
+        neg     ax                  ; Convert from countdown remaining
+                                    ;  to elapsed count
+        cmp     ax,cx               ; Has delay expired?
+        jb      @@LoopStart         ; No, so loop till done
+
+; Stop timer 2 from counting
+@@LoopEnd:
+        in      al,61H
+        and     al,0FEh
+        out     61H,al
+
+; Some programs have a problem if we change the control port; better change it
+; to something they expect (mode 3 - square wave generator)...
+        mov     al,0B6h
+        out     43h,al
+
+        leave_c
+        ret
+
+cprocend
+
+endcodeseg  _gatimer
+
+        END
+
diff --git a/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm
new file mode 100755
index 0000000..d4b1179
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm
@@ -0,0 +1,195 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*               Copyright (C) 1991-1998 SciTech Software, Inc.
+;*                            All rights reserved.
+;*
+;*  ======================================================================
+;*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+;*  |                                                                    |
+;*  |This copyrighted computer code contains proprietary technology      |
+;*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+;*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+;*  |                                                                    |
+;*  |The contents of this file are subject to the SciTech Nucleus        |
+;*  |License; you may *not* use this file or related software except in  |
+;*  |compliance with the License. You may obtain a copy of the License   |
+;*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+;*  |                                                                    |
+;*  |Software distributed under the License is distributed on an         |
+;*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+;*  |implied. See the License for the specific language governing        |
+;*  |rights and limitations under the License.                           |
+;*  |                                                                    |
+;*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+;*  ======================================================================
+;*
+;* Language:    TASM 4.0 or NASM
+;* Environment: IBM PC 32 bit Protected Mode.
+;*
+;* Description: Module to implement the import stubs for all the PM
+;*              API functions for Intel binary portable drivers.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+BEGIN_IMPORTS_DEF   _PM_imports
+DECLARE_IMP PM_getModeType,0
+DECLARE_IMP PM_getBIOSPointer,0
+DECLARE_IMP PM_getA0000Pointer,0
+DECLARE_IMP PM_mapPhysicalAddr,0
+DECLARE_IMP PM_mallocShared,0
+SKIP_IMP    _PM_reserved1,0
+DECLARE_IMP PM_freeShared,0
+DECLARE_IMP PM_mapToProcess,0
+DECLARE_IMP PM_mapRealPointer,0
+DECLARE_IMP PM_allocRealSeg,0
+DECLARE_IMP PM_freeRealSeg,0
+DECLARE_IMP PM_allocLockedMem,0
+DECLARE_IMP PM_freeLockedMem,0
+DECLARE_IMP PM_callRealMode,0
+DECLARE_IMP PM_int86,0
+DECLARE_IMP PM_int86x,0
+DECLARE_IMP DPMI_int86,0
+DECLARE_IMP PM_availableMemory,0
+DECLARE_IMP PM_getVESABuf,0
+DECLARE_IMP PM_getOSType,0
+DECLARE_IMP PM_fatalError,0
+DECLARE_IMP PM_setBankA,0
+DECLARE_IMP PM_setBankAB,0
+DECLARE_IMP PM_setCRTStart,0
+DECLARE_IMP PM_getCurrentPat,0
+DECLARE_IMP PM_getVBEAFPath,0
+DECLARE_IMP PM_getNucleusPath,0
+DECLARE_IMP PM_getNucleusConfigPath,0
+DECLARE_IMP PM_getUniqueID,0
+DECLARE_IMP PM_getMachineName,0
+DECLARE_IMP VF_available,0
+DECLARE_IMP VF_init,0
+DECLARE_IMP VF_exit,0
+DECLARE_IMP PM_openConsole,0
+DECLARE_IMP PM_getConsoleStateSize,0
+DECLARE_IMP PM_saveConsoleState,0
+DECLARE_IMP PM_restoreConsoleState,0
+DECLARE_IMP PM_closeConsole,0
+DECLARE_IMP PM_setOSCursorLocation,0
+DECLARE_IMP PM_setOSScreenWidth,0
+DECLARE_IMP PM_enableWriteCombine,0
+DECLARE_IMP PM_backslash,0
+DECLARE_IMP PM_lockDataPages,0
+DECLARE_IMP PM_unlockDataPages,0
+DECLARE_IMP PM_lockCodePages,0
+DECLARE_IMP PM_unlockCodePages,0
+DECLARE_IMP PM_setRealTimeClockHandler,0
+DECLARE_IMP PM_setRealTimeClockFrequency,0
+DECLARE_IMP PM_restoreRealTimeClockHandler,0
+DECLARE_IMP PM_doBIOSPOST,0
+DECLARE_IMP PM_getBootDrive,0
+DECLARE_IMP PM_freePhysicalAddr,0
+DECLARE_IMP PM_inpb,0
+DECLARE_IMP PM_inpw,0
+DECLARE_IMP PM_inpd,0
+DECLARE_IMP PM_outpb,0
+DECLARE_IMP PM_outpw,0
+DECLARE_IMP PM_outpd,0
+SKIP_IMP    _PM_reserved2,0
+DECLARE_IMP PM_setSuspendAppCallback,0
+DECLARE_IMP PM_haveBIOSAccess,0
+DECLARE_IMP PM_kbhit,0
+DECLARE_IMP PM_getch,0
+DECLARE_IMP PM_findBPD,0
+DECLARE_IMP PM_getPhysicalAddr,0
+DECLARE_IMP PM_sleep,0
+DECLARE_IMP PM_getCOMPort,0
+DECLARE_IMP PM_getLPTPort,0
+DECLARE_IMP PM_loadLibrary,0
+DECLARE_IMP PM_getProcAddress,0
+DECLARE_IMP PM_freeLibrary,0
+DECLARE_IMP PCI_enumerate,0
+DECLARE_IMP PCI_accessReg,0
+DECLARE_IMP PCI_setHardwareIRQ,0
+DECLARE_IMP PCI_generateSpecialCyle,0
+SKIP_IMP    _PM_reserved3,0
+DECLARE_IMP PCIBIOS_getEntry,0
+DECLARE_IMP CPU_getProcessorType,0
+DECLARE_IMP CPU_haveMMX,0
+DECLARE_IMP CPU_have3DNow,0
+DECLARE_IMP CPU_haveSSE,0
+DECLARE_IMP CPU_haveRDTSC,0
+DECLARE_IMP CPU_getProcessorSpeed,0
+DECLARE_IMP ZTimerInit,0
+DECLARE_IMP LZTimerOn,0
+DECLARE_IMP LZTimerLap,0
+DECLARE_IMP LZTimerOff,0
+DECLARE_IMP LZTimerCount,0
+DECLARE_IMP LZTimerOnExt,0
+DECLARE_IMP LZTimerLapExt,0
+DECLARE_IMP LZTimerOffExt,0
+DECLARE_IMP LZTimerCountExt,0
+DECLARE_IMP ULZTimerOn,0
+DECLARE_IMP ULZTimerLap,0
+DECLARE_IMP ULZTimerOff,0
+DECLARE_IMP ULZTimerCount,0
+DECLARE_IMP ULZReadTime,0
+DECLARE_IMP ULZElapsedTime,0
+DECLARE_IMP ULZTimerResolution,0
+DECLARE_IMP PM_findFirstFile,0
+DECLARE_IMP PM_findNextFile,0
+DECLARE_IMP PM_findClose,0
+DECLARE_IMP PM_makepath,0
+DECLARE_IMP PM_splitpath,0
+DECLARE_IMP PM_driveValid,0
+DECLARE_IMP PM_getdcwd,0
+DECLARE_IMP PM_setFileAttr,0
+DECLARE_IMP PM_mkdir,0
+DECLARE_IMP PM_rmdir,0
+DECLARE_IMP PM_getFileAttr,0
+DECLARE_IMP PM_getFileTime,0
+DECLARE_IMP PM_setFileTime,0
+DECLARE_IMP CPU_getProcessorName,0
+DECLARE_IMP PM_getVGAStateSize,0
+DECLARE_IMP PM_saveVGAState,0
+DECLARE_IMP PM_restoreVGAState,0
+DECLARE_IMP PM_vgaBlankDisplay,0
+DECLARE_IMP PM_vgaUnblankDisplay,0
+DECLARE_IMP PM_blockUntilTimeout,0
+DECLARE_IMP _PM_add64,0
+DECLARE_IMP _PM_sub64,0
+DECLARE_IMP _PM_mul64,0
+DECLARE_IMP _PM_div64,0
+DECLARE_IMP _PM_shr64,0
+DECLARE_IMP _PM_sar64,0
+DECLARE_IMP _PM_shl64,0
+DECLARE_IMP _PM_neg64,0
+DECLARE_IMP PCI_findBARSize,0
+DECLARE_IMP PCI_readRegBlock,0
+DECLARE_IMP PCI_writeRegBlock,0
+DECLARE_IMP PM_flushTLB,0
+DECLARE_IMP PM_useLocalMalloc,0
+DECLARE_IMP PM_malloc,0
+DECLARE_IMP PM_calloc,0
+DECLARE_IMP PM_realloc,0
+DECLARE_IMP PM_free,0
+DECLARE_IMP PM_getPhysicalAddrRange,0
+DECLARE_IMP PM_allocPage,0
+DECLARE_IMP PM_freePage,0
+DECLARE_IMP PM_agpInit,0
+DECLARE_IMP PM_agpExit,0
+DECLARE_IMP PM_agpReservePhysical,0
+DECLARE_IMP PM_agpReleasePhysical,0
+DECLARE_IMP PM_agpCommitPhysical,0
+DECLARE_IMP PM_agpFreePhysical,0
+DECLARE_IMP PCI_getNumDevices,0
+DECLARE_IMP PM_setLocalBPDPath,0
+DECLARE_IMP PM_loadDirectDraw,0
+DECLARE_IMP PM_unloadDirectDraw,0
+DECLARE_IMP PM_getDirectDrawWindow,0
+DECLARE_IMP PM_doSuspendApp,0
+END_IMPORTS_DEF
+
+        END
+
diff --git a/board/MAI/bios_emulator/scitech/src/common/aabeos.c b/board/MAI/bios_emulator/scitech/src/common/aabeos.c
new file mode 100755
index 0000000..ad5698a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aabeos.c
@@ -0,0 +1,92 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the Linux operating system.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+#include <sys/time.h>
+
+static ibool            haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+GA_sharedInfo * NAPI GA_getSharedInfo(
+    int device)
+{
+    (void)device;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp)
+{
+    (void)gaExp;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	haveRDTSC = true;
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else {
+	struct timeval t;
+	gettimeofday(&t, NULL);
+	value->low = t.tv_sec*1000000 + t.tv_usec;
+	value->high = 0;
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/aados.c b/board/MAI/bios_emulator/scitech/src/common/aados.c
new file mode 100755
index 0000000..342d2f3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aados.c
@@ -0,0 +1,64 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  MSDOS
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the MSDOS operating system.
+*
+****************************************************************************/
+
+#include "pm_help.h"
+#include "pmapi.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the DOS
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    _GA_readTimeStamp(value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/aalib.c b/board/MAI/bios_emulator/scitech/src/common/aalib.c
new file mode 100755
index 0000000..5003b22
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aalib.c
@@ -0,0 +1,225 @@
+/****************************************************************************
+*
+*                     SciTech Nucleus Audio Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Any 32-bit protected mode environment
+*
+* Description:  C module for the Graphics Accelerator Driver API. Uses
+*               the SciTech PM library for interfacing with DOS
+*               extender specific functions.
+*
+****************************************************************************/
+
+#include "nucleus/audio.h"
+#ifdef __WIN32_VXD__
+#include "sdd/sddhelp.h"
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+/*---------------------------- Global Variables ---------------------------*/
+
+#ifdef  TEST_HARNESS
+extern PM_imports   _VARAPI _PM_imports;
+#else
+AA_exports  _VARAPI _AA_exports;
+static int          loaded = false;
+static PE_MODULE    *hModBPD = NULL;
+
+#ifdef  __DRIVER__
+extern PM_imports _PM_imports;
+#else
+#include "pmimp.h"
+#endif
+
+static N_imports _N_imports = {
+    sizeof(N_imports),
+    _OS_delay,
+    };
+
+#ifdef  __DRIVER__
+extern AA_imports _AA_imports;
+#else
+static AA_imports _AA_imports = {
+    sizeof(AA_imports),
+    };
+#endif
+#endif
+
+/*----------------------------- Implementation ----------------------------*/
+
+#define DLL_NAME        "audio.bpd"
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Fatal error handler for non-exported AA_exports.
+****************************************************************************/
+static void _AA_fatalErrorHandler(void)
+{
+    PM_fatalError("Unsupported Nucleus export function called! Please upgrade your copy of Nucleus!\n");
+}
+
+/****************************************************************************
+REMARKS:
+Loads the Nucleus binary portable DLL into memory and initilises it.
+****************************************************************************/
+static ibool LoadDriver(void)
+{
+    AA_initLibrary_t    AA_initLibrary;
+    AA_exports          *aaExp;
+    char                filename[PM_MAX_PATH];
+    char                bpdpath[PM_MAX_PATH];
+    int                 i,max;
+    ulong               *p;
+
+    /* Check if we have already loaded the driver */
+    if (loaded)
+	return true;
+    PM_init();
+    _AA_exports.dwSize = sizeof(_AA_exports);
+
+    /* Open the BPD file */
+    if (!PM_findBPD(DLL_NAME,bpdpath))
+	return false;
+    strcpy(filename,bpdpath);
+    strcat(filename,DLL_NAME);
+    if ((hModBPD = PE_loadLibrary(filename,false)) == NULL)
+	return false;
+    if ((AA_initLibrary = (AA_initLibrary_t)PE_getProcAddress(hModBPD,"_AA_initLibrary")) == NULL)
+	return false;
+    bpdpath[strlen(bpdpath)-1] = 0;
+    if (strcmp(bpdpath,PM_getNucleusPath()) == 0)
+	strcpy(bpdpath,PM_getNucleusConfigPath());
+    else {
+	PM_backslash(bpdpath);
+	strcat(bpdpath,"config");
+	}
+    if ((aaExp = AA_initLibrary(bpdpath,filename,&_PM_imports,&_N_imports,&_AA_imports)) == NULL)
+	PM_fatalError("AA_initLibrary failed!\n");
+
+    /* Initialize all default imports to point to fatal error handler
+     * for upwards compatibility, and copy the exported functions.
+     */
+    max = sizeof(_AA_exports)/sizeof(AA_initLibrary_t);
+    for (i = 0,p = (ulong*)&_AA_exports; i < max; i++)
+	*p++ = (ulong)_AA_fatalErrorHandler;
+    memcpy(&_AA_exports,aaExp,MIN(sizeof(_AA_exports),aaExp->dwSize));
+    loaded = true;
+    return true;
+}
+
+/* The following are stub entry points that the application calls to
+ * initialise the Nucleus loader library, and we use this to load our
+ * driver DLL from disk and initialise the library using it.
+ */
+
+/* {secret} */
+int NAPI AA_status(void)
+{
+    if (!loaded)
+	return nDriverNotFound;
+    return _AA_exports.AA_status();
+}
+
+/* {secret} */
+const char * NAPI AA_errorMsg(
+    N_int32 status)
+{
+    if (!loaded)
+	return "Unable to load Nucleus device driver!";
+    return _AA_exports.AA_errorMsg(status);
+}
+
+/* {secret} */
+int NAPI AA_getDaysLeft(void)
+{
+    if (!LoadDriver())
+	return -1;
+    return _AA_exports.AA_getDaysLeft();
+}
+
+/* {secret} */
+int NAPI AA_registerLicense(uchar *license)
+{
+    if (!LoadDriver())
+	return 0;
+    return _AA_exports.AA_registerLicense(license);
+}
+
+/* {secret} */
+int NAPI AA_enumerateDevices(void)
+{
+    if (!LoadDriver())
+	return 0;
+    return _AA_exports.AA_enumerateDevices();
+}
+
+/* {secret} */
+AA_devCtx * NAPI AA_loadDriver(N_int32 deviceIndex)
+{
+    if (!LoadDriver())
+	return NULL;
+    return _AA_exports.AA_loadDriver(deviceIndex);
+}
+#endif
+
+typedef struct {
+    N_uint32    low;
+    N_uint32    high;
+    } AA_largeInteger;
+
+void    NAPI _OS_delay8253(N_uint32 microSeconds);
+ibool   NAPI _GA_haveCPUID(void);
+uint    NAPI _GA_getCPUIDFeatures(void);
+void    NAPI _GA_readTimeStamp(AA_largeInteger *time);
+#define CPU_HaveRDTSC   0x00000010
+
+/****************************************************************************
+REMARKS:
+This function delays for the specified number of microseconds
+****************************************************************************/
+void NAPI _OS_delay(
+    N_uint32 microSeconds)
+{
+    static ibool    inited = false;
+    LZTimerObject   tm;
+
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) {
+	if (!inited) {
+	    ZTimerInit();
+	    inited = true;
+	    }
+	LZTimerOnExt(&tm);
+	while (LZTimerLapExt(&tm) < microSeconds)
+	    ;
+	LZTimerOnExt(&tm);
+	}
+    else
+	_OS_delay8253(microSeconds);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/aalinux.c b/board/MAI/bios_emulator/scitech/src/common/aalinux.c
new file mode 100755
index 0000000..d3d468e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aalinux.c
@@ -0,0 +1,94 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the Linux operating system.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+#include <sys/time.h>
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static ibool        haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+GA_sharedInfo * NAPI GA_getSharedInfo(
+    int device)
+{
+    (void)device;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp)
+{
+    (void)gaExp;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	haveRDTSC = true;
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else {
+	struct timeval t;
+	gettimeofday(&t, NULL);
+	value->low = t.tv_sec*1000000 + t.tv_usec;
+	value->high = 0;
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/aaos2.c b/board/MAI/bios_emulator/scitech/src/common/aaos2.c
new file mode 100755
index 0000000..0ec8c9f
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aaos2.c
@@ -0,0 +1,124 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  OS/2 32-bit
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the OS/2 operating system environments.
+*
+****************************************************************************/
+
+#include "pm_help.h"
+#define INCL_DOSERRORS
+#define INCL_DOS
+#define INCL_SUB
+#define INCL_VIO
+#define INCL_KBD
+#include <os2.h>
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static HFILE        hSDDHelp;
+static ulong        outLen;         /* Must not cross 64Kb boundary!    */
+static ulong        result;         /* Must not cross 64Kb boundary!    */
+static ibool        haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+This function returns a pointer to the common graphics driver loaded in the
+helper VxD. The memory for the VxD is shared between all processes via
+the VxD, so that the VxD, 16-bit code and 32-bit code all see the same
+state when accessing the graphics binary portable driver.
+****************************************************************************/
+GA_sharedInfo * NAPI GA_getSharedInfo(
+    int device)
+{
+    /* Initialise the PM library and connect to our runtime DLL's */
+    PM_init();
+
+    /* Open our helper device driver */
+    if (DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0,
+	    FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE,
+	    NULL))
+	PM_fatalError("Unable to open SDDHELP$ helper device driver!");
+    outLen = sizeof(result);
+    DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,PMHELP_GETSHAREDINFO,
+	NULL, 0, NULL,
+	&result, outLen, &outLen);
+    DosClose(hSDDHelp);
+    if (result) {
+	/* We have found the shared Nucleus packet. Because not all processes
+	 * map to SDDPMI.DLL, we need to ensure that we connect to this
+	 * DLL so that it gets mapped into our address space (that is
+	 * where the shared Nucleus packet is located). Simply doing a
+	 * DosLoadModule on it is enough for this.
+	 */
+	HMODULE hModSDDPMI;
+	char    buf[80];
+	DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"SDDPMI.DLL",&hModSDDPMI);
+	}
+    return (GA_sharedInfo*)result;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp)
+{
+    (void)gaExp;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	haveRDTSC = true;
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else
+	DosTmrQueryTime((QWORD*)value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/aaqnx.c b/board/MAI/bios_emulator/scitech/src/common/aaqnx.c
new file mode 100755
index 0000000..13531be
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aaqnx.c
@@ -0,0 +1,95 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the QNX operating system.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+#include <time.h>
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static ibool        haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+GA_sharedInfo * NAPI GA_getSharedInfo(
+    int device)
+{
+    (void)device;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp)
+{
+    (void)gaExp;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	haveRDTSC = true;
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else {
+	struct timespec ts;
+
+	clock_gettime(CLOCK_REALTIME, &ts);
+	value->low = (ts.tv_nsec / 1000 + ts.tv_sec * 1000000);
+	value->high = 0;
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/aartt.c b/board/MAI/bios_emulator/scitech/src/common/aartt.c
new file mode 100755
index 0000000..1a5a67a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aartt.c
@@ -0,0 +1,89 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  RTTarget-32
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the RTTarget-32 operating system environments.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+
+/*------------------------- Global Variables ------------------------------*/
+
+static ibool            haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+GA_sharedInfo * NAPI GA_getSharedInfo(
+    int device)
+{
+    (void)device;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp)
+{
+    (void)gaExp;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) {
+	haveRDTSC = true;
+	return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/aasmx.c b/board/MAI/bios_emulator/scitech/src/common/aasmx.c
new file mode 100755
index 0000000..163060f
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aasmx.c
@@ -0,0 +1,83 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  smx32
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the smx32 platform -- no vxD support.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "nucleus/graphics.h"
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+GA_sharedInfo * NAPI GA_getSharedInfo(
+    int device)
+{
+    (void)device;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp)
+{
+    (void)gaExp;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    _GA_readTimeStamp(value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/aavxd.c b/board/MAI/bios_emulator/scitech/src/common/aavxd.c
new file mode 100755
index 0000000..221b02b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aavxd.c
@@ -0,0 +1,90 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32 VxD
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the Win32 VxD's.
+*
+****************************************************************************/
+
+#include "sdd/sddhelp.h"
+
+/*------------------------- Global Variables ------------------------------*/
+
+static ibool            haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+Return the internal shared info structure.
+****************************************************************************/
+GA_sharedInfo * NAPI GA_getSharedInfo(
+    int device)
+{
+    static GA_sharedInfo shared = {0,-1};
+    return &shared;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp)
+{
+    (void)gaExp;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) {
+	haveRDTSC = true;
+	}
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else
+	VTD_Get_Real_Time(&value->high,&value->low);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/aawin32.c b/board/MAI/bios_emulator/scitech/src/common/aawin32.c
new file mode 100755
index 0000000..541df4a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/aawin32.c
@@ -0,0 +1,264 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the Win32 operating system environments.
+*
+****************************************************************************/
+
+#include "pm_help.h"
+#include "pmapi.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#define STRICT
+#define WIN32_LEAN_AND_MEAN
+#include <windows.h>
+
+/*------------------------- Global Variables ------------------------------*/
+
+#if GA_MAX_DEVICES > 4
+#error GA_MAX_DEVICES has changed!
+#endif
+
+static ibool            haveRDTSC;
+static GA_largeInteger  countFreq;
+static GA_loadDriver_t  ORG_GA_loadDriver;
+extern HANDLE           _PM_hDevice;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+DESCRIPTION:
+Get the current graphics driver imports from the VxD
+
+REMARKS:
+This function returns a pointer to the common graphics driver loaded in the
+helper VxD. The memory for the VxD is shared between all processes via
+the VxD, so that the VxD, 16-bit code and 32-bit code all see the same
+state when accessing the graphics binary portable driver.
+****************************************************************************/
+GA_sharedInfo * NAPI GA_getSharedInfo(
+    int device)
+{
+    DWORD   inBuf[1];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[2];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    PM_init();
+    inBuf[0] = device;
+    if (DeviceIoControl(_PM_hDevice, PMHELP_GETSHAREDINFO32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL)) {
+	return (GA_sharedInfo*)outBuf[0];
+	}
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp)
+{
+    (void)gaExp;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the software stereo module by either calling
+the Nucleus libraries directly, or calling into the VxD if we are running
+on the shared Nucleus libraries loaded by the Windows VxD.
+****************************************************************************/
+static ibool NAPI _GA_softStereoInit(
+    GA_devCtx *dc)
+{
+    if (_PM_hDevice) {
+	DWORD   inBuf[1];   /* Buffer to send data to VxD       */
+	DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+	DWORD   count;      /* Count of bytes returned from VxD */
+
+	inBuf[0] = (ulong)dc;
+	if (DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOINIT32, inBuf, sizeof(inBuf),
+		outBuf, sizeof(outBuf), &count, NULL)) {
+	    return outBuf[0];
+	    }
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function turns on software stereo mode, either directly or via the VxD.
+****************************************************************************/
+static void NAPI _GA_softStereoOn(void)
+{
+    if (_PM_hDevice) {
+	DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOON32, NULL, 0,
+	    NULL, 0, NULL, NULL);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+This function schedules a software stereo mode page flip, either directly
+or via the VxD.
+****************************************************************************/
+static void NAPI _GA_softStereoScheduleFlip(
+    N_uint32 leftAddr,
+    N_uint32 rightAddr)
+{
+    if (_PM_hDevice) {
+	DWORD   inBuf[2];   /* Buffer to send data to VxD       */
+	DWORD   count;      /* Count of bytes returned from VxD */
+
+	inBuf[0] = (ulong)leftAddr;
+	inBuf[1] = (ulong)rightAddr;
+	DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOFLIP32, inBuf, sizeof(inBuf),
+	    NULL, 0, &count, NULL);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+This function turns off software stereo mode, either directly or via the VxD.
+****************************************************************************/
+static N_int32 NAPI _GA_softStereoGetFlipStatus(void)
+{
+    if (_PM_hDevice) {
+	DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+	DWORD   count;      /* Count of bytes returned from VxD */
+
+	if (DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOFLIPSTATUS32, NULL, 0,
+		outBuf, sizeof(outBuf), &count, NULL)) {
+	    return outBuf[0];
+	    }
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+This function turns off software stereo mode, either directly or via the VxD.
+****************************************************************************/
+static void NAPI _GA_softStereoWaitTillFlipped(void)
+{
+    while (!_GA_softStereoGetFlipStatus())
+	;
+}
+
+/****************************************************************************
+REMARKS:
+This function turns off software stereo mode, either directly or via the VxD.
+****************************************************************************/
+static void NAPI _GA_softStereoOff(void)
+{
+    if (_PM_hDevice) {
+	DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOOFF32, NULL, 0,
+	    NULL, 0, NULL, NULL);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+This function disable the software stereo handler, either directly or via
+the VxD.
+****************************************************************************/
+static void NAPI _GA_softStereoExit(void)
+{
+    if (_PM_hDevice) {
+	DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOEXIT32, NULL, 0,
+	    NULL, 0, NULL, NULL);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+We hook this function in here so that we can avoid the memory detect and
+other destructive sequences in the drivers if we are loading the driver
+from a Win32 application (our display drivers in contrast load them inside
+the VxD directly, but the control panel applets use this function).
+****************************************************************************/
+static GA_devCtx * NAPI _GA_loadDriver(
+    N_int32 deviceIndex,
+    N_int32 shared)
+{
+    GA_devCtx   *dc;
+    DWORD       inBuf[1];
+    DWORD       outBuf[1];
+    N_int32     totalMemory = 0,oldIOPL;
+
+    if (deviceIndex >= GA_MAX_DEVICES)
+	PM_fatalError("DeviceIndex too large in GA_loadDriver!");
+    PM_init();
+    inBuf[0] = deviceIndex;
+    if (DeviceIoControl(_PM_hDevice, PMHELP_GETMEMSIZE32,
+	    inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), NULL, NULL))
+	totalMemory = outBuf[0];
+    if (totalMemory == 0)
+	totalMemory = 8192;
+    _GA_exports.GA_forceMemSize(totalMemory,shared);
+    oldIOPL = PM_setIOPL(3);
+    dc = ORG_GA_loadDriver(deviceIndex,shared);
+    PM_setIOPL(oldIOPL);
+    return dc;
+}
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) {
+	haveRDTSC = true;
+	return true;
+	}
+    else if (QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq)) {
+	haveRDTSC = false;
+	return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else
+	QueryPerformanceCounter((LARGE_INTEGER*)value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/agplib.c b/board/MAI/bios_emulator/scitech/src/common/agplib.c
new file mode 100755
index 0000000..476eedc
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/agplib.c
@@ -0,0 +1,219 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Any 32-bit protected mode environment
+*
+* Description:  C module for the Graphics Accelerator Driver API. Uses
+*               the SciTech PM library for interfacing with DOS
+*               extender specific functions.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+#include "nucleus/agp.h"
+
+/*---------------------------- Global Variables ---------------------------*/
+
+#ifndef DEBUG_AGP_DRIVER
+static AGP_exports  _AGP_exports;
+static int          loaded = false;
+static PE_MODULE    *hModBPD = NULL;
+
+static N_imports _N_imports = {
+    sizeof(N_imports),
+    _OS_delay,
+    };
+
+static AGP_imports _AGP_imports = {
+    sizeof(AGP_imports),
+    };
+#endif
+
+#include "pmimp.h"
+
+/*----------------------------- Implementation ----------------------------*/
+
+#define DLL_NAME        "agp.bpd"
+
+#ifndef DEBUG_AGP_DRIVER
+/****************************************************************************
+REMARKS:
+Fatal error handler for non-exported GA_exports.
+****************************************************************************/
+static void _AGP_fatalErrorHandler(void)
+{
+    PM_fatalError("Unsupported AGP export function called! Please upgrade your copy of AGP!\n");
+}
+
+/****************************************************************************
+PARAMETERS:
+shared  - True to load the driver into shared memory.
+
+REMARKS:
+Loads the Nucleus binary portable DLL into memory and initilises it.
+****************************************************************************/
+static ibool LoadDriver(void)
+{
+    AGP_initLibrary_t   AGP_initLibrary;
+    AGP_exports         *agpExp;
+    char                filename[PM_MAX_PATH];
+    char                bpdpath[PM_MAX_PATH];
+    int                 i,max;
+    ulong               *p;
+
+    /* Check if we have already loaded the driver */
+    if (loaded)
+	return true;
+    PM_init();
+
+    /* Open the BPD file */
+    if (!PM_findBPD(DLL_NAME,bpdpath))
+	return false;
+    strcpy(filename,bpdpath);
+    strcat(filename,DLL_NAME);
+    if ((hModBPD = PE_loadLibrary(filename,false)) == NULL)
+	return false;
+    if ((AGP_initLibrary = (AGP_initLibrary_t)PE_getProcAddress(hModBPD,"_AGP_initLibrary")) == NULL)
+	return false;
+    bpdpath[strlen(bpdpath)-1] = 0;
+    if (strcmp(bpdpath,PM_getNucleusPath()) == 0)
+	strcpy(bpdpath,PM_getNucleusConfigPath());
+    else {
+	PM_backslash(bpdpath);
+	strcat(bpdpath,"config");
+	}
+    if ((agpExp = AGP_initLibrary(bpdpath,filename,GA_getSystemPMImports(),&_N_imports,&_AGP_imports)) == NULL)
+	PM_fatalError("AGP_initLibrary failed!\n");
+    _AGP_exports.dwSize = sizeof(_AGP_exports);
+    max = sizeof(_AGP_exports)/sizeof(AGP_initLibrary_t);
+    for (i = 0,p = (ulong*)&_AGP_exports; i < max; i++)
+	*p++ = (ulong)_AGP_fatalErrorHandler;
+    memcpy(&_AGP_exports,agpExp,MIN(sizeof(_AGP_exports),agpExp->dwSize));
+    loaded = true;
+    return true;
+}
+
+/* The following are stub entry points that the application calls to
+ * initialise the Nucleus loader library, and we use this to load our
+ * driver DLL from disk and initialise the library using it.
+ */
+
+/* {secret} */
+int NAPI AGP_status(void)
+{
+    if (!loaded)
+	return nDriverNotFound;
+    return _AGP_exports.AGP_status();
+}
+
+/* {secret} */
+const char * NAPI AGP_errorMsg(
+    N_int32 status)
+{
+    if (!loaded)
+	return "Unable to load Nucleus device driver!";
+    return _AGP_exports.AGP_errorMsg(status);
+}
+
+/* {secret} */
+AGP_devCtx * NAPI AGP_loadDriver(N_int32 deviceIndex)
+{
+    if (!LoadDriver())
+	return NULL;
+    return _AGP_exports.AGP_loadDriver(deviceIndex);
+}
+
+/* {secret} */
+void NAPI AGP_unloadDriver(
+    AGP_devCtx *dc)
+{
+    if (loaded)
+	_AGP_exports.AGP_unloadDriver(dc);
+}
+
+/* {secret} */
+void NAPI AGP_getGlobalOptions(
+    AGP_globalOptions *options)
+{
+    if (LoadDriver())
+	_AGP_exports.AGP_getGlobalOptions(options);
+}
+
+/* {secret} */
+void NAPI AGP_setGlobalOptions(
+    AGP_globalOptions *options)
+{
+    if (LoadDriver())
+	_AGP_exports.AGP_setGlobalOptions(options);
+}
+
+/* {secret} */
+void NAPI AGP_saveGlobalOptions(
+    AGP_globalOptions *options)
+{
+    if (loaded)
+	_AGP_exports.AGP_saveGlobalOptions(options);
+}
+#endif
+
+/* {secret} */
+void NAPI _OS_delay8253(N_uint32 microSeconds);
+
+/****************************************************************************
+REMARKS:
+This function delays for the specified number of microseconds
+****************************************************************************/
+void NAPI _OS_delay(
+    N_uint32 microSeconds)
+{
+    static ibool    inited = false;
+    static ibool    haveRDTSC;
+    LZTimerObject   tm;
+
+    if (!inited) {
+#ifndef __WIN32_VXD__
+	/* This has been causing problems in VxD's for some reason, so for now */
+	/* we avoid using it. */
+	if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) {
+	    ZTimerInit();
+	    haveRDTSC = true;
+	    }
+	else
+#endif
+	    haveRDTSC = false;
+	inited = true;
+	}
+    if (haveRDTSC) {
+	LZTimerOnExt(&tm);
+	while (LZTimerLapExt(&tm) < microSeconds)
+	    ;
+	LZTimerOnExt(&tm);
+	}
+    else
+	_OS_delay8253(microSeconds);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/center.c b/board/MAI/bios_emulator/scitech/src/common/center.c
new file mode 100755
index 0000000..68e17c2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/center.c
@@ -0,0 +1,122 @@
+/****************************************************************************
+*
+*                  Display Doctor Windows Interface Code
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code is a proprietary trade secret of     |
+*  |SciTech Software, Inc., located at 505 Wall Street, Chico, CA 95928 |
+*  |USA (www.scitechsoft.com).  ANY UNAUTHORIZED POSSESSION, USE,       |
+*  |VIEWING, COPYING, MODIFICATION OR DISSEMINATION OF THIS CODE IS     |
+*  |STRICTLY PROHIBITED BY LAW.  Unless you have current, express       |
+*  |written authorization from SciTech to possess or use this code, you |
+*  |may be subject to civil and/or criminal penalties.                  |
+*  |                                                                    |
+*  |If you received this code in error or you would like to report      |
+*  |improper use, please immediately contact SciTech Software, Inc. at  |
+*  |530-894-8400.                                                       |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     C++ 3.0
+* Environment:  Win16
+*
+* Description:  Dialog driven configuration program for UniVBE and
+*               WinDirect Professional products.
+*
+****************************************************************************/
+
+#include "center.h"
+
+/*------------------------------ Implementation ---------------------------*/
+
+void _EXPORT CenterWindow(HWND hWndCenter, HWND parent, BOOL repaint)
+/****************************************************************************
+*
+* Function:     CenterWindow
+* Parameters:   hWndCenter  - Window to center
+*               parent      - Handle for parent window
+*               repaint     - true if window should be re-painted
+*
+* Description:  Centers the specified window within the bounds of the
+*               specified parent window. If the parent window is NULL, then
+*               we center it using the Desktop window.
+*
+****************************************************************************/
+{
+    HWND    hWndParent = (parent ? parent : GetDesktopWindow());
+    RECT    RectParent;
+    RECT    RectCenter;
+    int     CenterX,CenterY,Height,Width;
+
+    GetWindowRect(hWndParent, &RectParent);
+    GetWindowRect(hWndCenter, &RectCenter);
+
+    Width = (RectCenter.right - RectCenter.left);
+    Height = (RectCenter.bottom - RectCenter.top);
+    CenterX = ((RectParent.right - RectParent.left) - Width) / 2;
+    CenterY = ((RectParent.bottom - RectParent.top) - Height) / 2;
+
+    if ((CenterX < 0) || (CenterY < 0)) {
+	/* The Center Window is smaller than the parent window. */
+	if (hWndParent != GetDesktopWindow()) {
+	    /* If the parent window is not the desktop use the desktop size. */
+	    CenterX = (GetSystemMetrics(SM_CXSCREEN) - Width) / 2;
+	    CenterY = (GetSystemMetrics(SM_CYSCREEN) - Height) / 2;
+	    }
+	CenterX = (CenterX < 0) ? 0: CenterX;
+	CenterY = (CenterY < 0) ? 0: CenterY;
+	}
+    else {
+	CenterX += RectParent.left;
+	CenterY += RectParent.top;
+	}
+
+    /* Copy the values into RectCenter */
+    RectCenter.left = CenterX;
+    RectCenter.right = CenterX + Width;
+    RectCenter.top = CenterY;
+    RectCenter.bottom = CenterY + Height;
+
+    /* Move the window to the new location */
+    MoveWindow(hWndCenter, RectCenter.left, RectCenter.top,
+	    (RectCenter.right - RectCenter.left),
+	    (RectCenter.bottom - RectCenter.top), repaint);
+}
+
+void _EXPORT CenterLogo(HWND hWndLogo, HWND hWndParent, int CenterY)
+/****************************************************************************
+*
+* Function:     CenterLogo
+* Parameters:   hWndLogo    - Window to center
+*               hWndParent  - Handle for parent window
+*               CenterY     - Top coordinate for logo
+*
+* Description:  Centers the specified window within the bounds of the
+*               specified parent window in the horizontal direction only.
+*
+****************************************************************************/
+{
+    RECT    RectParent;
+    RECT    RectCenter;
+    int     CenterX,Height,Width;
+
+    GetWindowRect(hWndParent, &RectParent);
+    GetWindowRect(hWndLogo, &RectCenter);
+    Width = (RectCenter.right - RectCenter.left);
+    Height = (RectCenter.bottom - RectCenter.top);
+    CenterX = ((RectParent.right - RectParent.left) - Width) / 2;
+
+    /* Copy the values into RectCenter */
+    RectCenter.left = CenterX;
+    RectCenter.right = CenterX + Width;
+    RectCenter.top = CenterY;
+    RectCenter.bottom = CenterY + Height;
+
+    /* Move the window to the new location */
+    MoveWindow(hWndLogo, RectCenter.left, RectCenter.top,
+	    (RectCenter.right - RectCenter.left),
+	    (RectCenter.bottom - RectCenter.top), false);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/cmdline.c b/board/MAI/bios_emulator/scitech/src/common/cmdline.c
new file mode 100755
index 0000000..531e5e1
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/cmdline.c
@@ -0,0 +1,428 @@
+/****************************************************************************
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  This module contains code to parse the command line,
+*               extracting options and parameters in standard System V
+*               style.
+*
+****************************************************************************/
+
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h>
+#include "cmdline.h"
+
+/*------------------------- Global variables ------------------------------*/
+
+int     nextargv    =   1;          /* Index into argv array            */
+char    *nextchar   =   NULL;       /* Pointer to next character        */
+
+/*-------------------------- Implementation -------------------------------*/
+
+#define IS_SWITCH_CHAR(c)       ((c) == '-')
+#define IS_NOT_SWITCH_CHAR(c)   ((c) != '-')
+
+/****************************************************************************
+DESCRIPTION:
+Parse the command line for specific options
+
+HEADER:
+cmdline.h
+
+PARAMETERS:
+argc        - Value passed to program through argc variable
+argv        - Pointer to the argv array passed to the program
+format      - A string representing the expected format of the command line
+argument    - Pointer to optional argument on command line
+
+RETURNS:
+Character code representing the next option parsed from the command line by
+getcmdopt. Returns ALLDONE (-1) when there are no more parameters to be parsed
+on the command line, PARAMETER (-2) when the argument being parsed is a
+parameter and not an option switch and lastly INVALID (-3) if an error
+occured while parsing the command line.
+
+REMARKS:
+Function to parse the command line option switches in UNIX System V style.
+When getcmdopt is called, it returns the character code of the next valid
+option that is parsed from the command line as specified by the Format
+string. The format string should be in the following form:
+
+    "abcd:e:f:"
+
+where a,b and c represent single switch style options and the character
+code returned by getcmdopt is the only value returned. Also d, e and f
+represent options that expect arguments immediately after them on the
+command line. The argument that follows the option on the command line is
+returned via a reference in the pointer argument. Thus a valid command line
+for this format string might be:
+
+    myprogram -adlines -b -f format infile outfile
+
+where a and b will be returned as single character options with no argument,
+while d is returned with the argument lines and f is returned with the
+argument format.
+
+When getcmdopt returns with PARAMETER (we attempted to parse a paramter, not
+an option), the global variable NextArgv will hold an index in the argv
+array to the argument on the command line AFTER the options, ie in the
+above example the string 'infile'. If the parameter is successfully used,
+NextArgv should be incremented and getcmdopt can be called again to parse any
+more options. Thus you can also have options interspersed throught the
+command line. eg:
+
+    myprogram -adlines infile -b outfile -f format
+
+can be made to be a valid form of the above command line.
+****************************************************************************/
+int getcmdopt(
+    int argc,
+    char **argv,
+    char *format,
+    char **argument)
+{
+    char    ch;
+    char    *formatchar;
+
+    if (argc > nextargv) {
+	if (nextchar == NULL) {
+	    nextchar = argv[nextargv];      /* Index next argument      */
+	    if (nextchar == NULL) {
+		nextargv++;
+		return ALLDONE;             /* No more options          */
+		}
+	    if (IS_NOT_SWITCH_CHAR(*nextchar)) {
+		nextchar = NULL;
+		return PARAMETER;           /* We have a parameter      */
+		}
+	    nextchar++;                     /* Move past switch operator */
+	    if (IS_SWITCH_CHAR(*nextchar)) {
+		nextchar = NULL;
+		return INVALID;             /* Ignore rest of line      */
+		}
+	    }
+	if ((ch = *(nextchar++)) == 0) {
+	    nextchar = NULL;
+	    return INVALID;                 /* No options on line       */
+	    }
+
+	if (ch == ':' ||  (formatchar = strchr(format, ch)) == NULL)
+	    return INVALID;
+
+	if (*(++formatchar) == ':') {   /* Expect an argument after option */
+	    nextargv++;
+	    if (*nextchar == 0) {
+		if (argc <= nextargv)
+		    return INVALID;
+		nextchar = argv[nextargv++];
+		}
+	    *argument = nextchar;
+	    nextchar = NULL;
+	    }
+	else {                      /* We have a switch style option    */
+	    if (*nextchar == 0) {
+		nextargv++;
+		nextchar = NULL;
+		}
+	    *argument = NULL;
+	    }
+	return ch;                  /* return the option specifier      */
+	}
+    nextchar = NULL;
+    nextargv++;
+    return ALLDONE;                 /* no arguments on command line     */
+}
+
+/****************************************************************************
+PARAMETERS:
+optarr      - Description for the option we are parsing
+argument    - String to parse
+
+RETURNS:
+INVALID on error, ALLDONE on success.
+
+REMARKS:
+Parses the argument string depending on the type of argument that is
+expected, filling in the argument for that option. Note that to parse a
+string, we simply return a pointer to argument.
+****************************************************************************/
+static int parse_option(
+    Option *optarr,
+    char *argument)
+{
+    int     num_read;
+
+    switch ((int)(optarr->type)) {
+	case OPT_INTEGER:
+	    num_read = sscanf(argument,"%d",(int*)optarr->arg);
+	    break;
+	case OPT_HEX:
+	    num_read = sscanf(argument,"%x",(int*)optarr->arg);
+	    break;
+	case OPT_OCTAL:
+	    num_read = sscanf(argument,"%o",(int*)optarr->arg);
+	    break;
+	case OPT_UNSIGNED:
+	    num_read = sscanf(argument,"%u",(uint*)optarr->arg);
+	    break;
+	case OPT_LINTEGER:
+	    num_read = sscanf(argument,"%ld",(long*)optarr->arg);
+	    break;
+	case OPT_LHEX:
+	    num_read = sscanf(argument,"%lx",(long*)optarr->arg);
+	    break;
+	case OPT_LOCTAL:
+	    num_read = sscanf(argument,"%lo",(long*)optarr->arg);
+	    break;
+	case OPT_LUNSIGNED:
+	    num_read = sscanf(argument,"%lu",(ulong*)optarr->arg);
+	    break;
+	case OPT_FLOAT:
+	    num_read = sscanf(argument,"%f",(float*)optarr->arg);
+	    break;
+	case OPT_DOUBLE:
+	    num_read = sscanf(argument,"%lf",(double*)optarr->arg);
+	    break;
+	case OPT_LDOUBLE:
+	    num_read = sscanf(argument,"%Lf",(long double*)optarr->arg);
+	    break;
+	case OPT_STRING:
+	    num_read = 1;           /* This always works    */
+	    *((char**)optarr->arg) = argument;
+	    break;
+	default:
+	    return INVALID;
+	}
+
+    if (num_read == 0)
+	return INVALID;
+    else
+	return ALLDONE;
+}
+
+/****************************************************************************
+HEADER:
+cmdline.h
+
+PARAMETERS:
+argc        - Number of arguments on command line
+argv        - Array of command line arguments
+num_opt     - Number of options in option array
+optarr      - Array to specify how to parse the command line
+do_param    - Routine to handle a command line parameter
+
+RETURNS:
+ALLDONE, INVALID or HELP
+
+REMARKS:
+Function to parse the command line according to a table of options. This
+routine calls getcmdopt above to parse each individual option and attempts
+to parse each option into a variable of the specified type. The routine
+can parse integers and long integers in either decimal, octal, hexadecimal
+notation, unsigned integers and unsigned longs, strings and option switches.
+Option switches are simply boolean variables that get turned on if the
+switch was parsed.
+
+Parameters are extracted from the command line by calling a user supplied
+routine do_param() to handle each parameter as it is encountered. The
+routine do_param() should accept a pointer to the parameter on the command
+line and an integer representing how many parameters have been encountered
+(ie: 1 if this is the first parameter, 10 if it is the 10th etc), and return
+ALLDONE upon successfully parsing it or INVALID if the parameter was invalid.
+
+We return either ALLDONE if all the options were successfully parsed,
+INVALID if an invalid option was encountered or HELP if any of -h, -H or
+-? were present on the command line.
+****************************************************************************/
+int getargs(
+    int argc,
+    char *argv[],
+    int num_opt,
+    Option optarr[],
+    int (*do_param)(
+	char *param,
+	int num))
+{
+    int     i,opt;
+    char    *argument;
+    int     param_num = 1;
+    char    cmdstr[MAXARG*2 + 4];
+
+    /* Build the command string from the array of options   */
+
+    strcpy(cmdstr,"hH?");
+    for (i = 0,opt = 3; i < num_opt; i++,opt++) {
+	cmdstr[opt] = optarr[i].opt;
+	if (optarr[i].type != OPT_SWITCH) {
+	    cmdstr[++opt] = ':';
+	    }
+	}
+    cmdstr[opt] = '\0';
+
+    for (;;) {
+	opt = getcmdopt(argc,argv,cmdstr,&argument);
+	switch (opt) {
+	    case 'H':
+	    case 'h':
+	    case '?':
+		return HELP;
+	    case ALLDONE:
+		return ALLDONE;
+	    case INVALID:
+		return INVALID;
+	    case PARAMETER:
+		if (do_param == NULL)
+		    return INVALID;
+		if (do_param(argv[nextargv],param_num) == INVALID)
+		    return INVALID;
+		nextargv++;
+		param_num++;
+		break;
+	    default:
+
+		/* Search for the option in the option array. We are
+		 * guaranteed to find it.
+		 */
+
+		for (i = 0; i < num_opt; i++) {
+		    if (optarr[i].opt == opt)
+			break;
+		    }
+		if (optarr[i].type == OPT_SWITCH)
+		    *((ibool*)optarr[i].arg) = true;
+		else {
+		    if (parse_option(&optarr[i],argument) == INVALID)
+			return INVALID;
+		    }
+		break;
+	    }
+	}
+}
+
+/****************************************************************************
+HEADER:
+cmdline.h
+
+PARAMETERS:
+num_opt - Number of options in the table
+optarr  - Table of option descriptions
+
+REMARKS:
+Prints the description of each option in a standard format to the standard
+output device. The description for each option is obtained from the table
+of options.
+****************************************************************************/
+void print_desc(
+    int num_opt,
+    Option optarr[])
+{
+    int     i;
+
+    for (i = 0; i < num_opt; i++) {
+	if (optarr[i].type == OPT_SWITCH)
+	    printf("  -%c       %s\n",optarr[i].opt,optarr[i].desc);
+	else
+	    printf("  -%c<arg>  %s\n",optarr[i].opt,optarr[i].desc);
+	}
+}
+
+/****************************************************************************
+HEADER:
+cmdline.h
+
+PARAMETERS:
+moduleName  - Module name for program
+cmdLine     - Command line to parse
+pargc       - Pointer to 'argc' parameter
+pargv       - Pointer to 'argv' parameter
+maxArgc     - Maximum argv array index
+
+REMARKS:
+Parses a command line from a single string into the C style 'argc' and
+'argv' format. Most useful for Windows programs where the command line
+is passed in verbatim.
+****************************************************************************/
+int parse_commandline(
+    char *moduleName,
+    char *cmdLine,
+    int *pargc,
+    char *argv[],
+    int maxArgv)
+{
+    static char str[512];
+    static char filename[260];
+    char        *prevWord = NULL;
+    ibool        inQuote = FALSE;
+    ibool        noStrip = FALSE;
+    int         argc;
+
+    argc = 0;
+    strcpy(filename,moduleName);
+    argv[argc++] = filename;
+    cmdLine = strncpy(str, cmdLine, sizeof(str)-1);
+    while (*cmdLine) {
+	switch (*cmdLine) {
+	    case '"' :
+		if (prevWord != NULL) {
+		    if (inQuote) {
+			if (!noStrip)
+			    *cmdLine = '\0';
+			argv [argc++] = prevWord;
+			prevWord = NULL;
+			}
+		    else
+			noStrip = TRUE;
+		    }
+		inQuote = !inQuote;
+		break;
+	    case ' ' :
+	    case '\t' :
+		if (!inQuote) {
+		    if (prevWord != NULL) {
+			*cmdLine = '\0';
+			argv [argc++] = prevWord;
+			prevWord = NULL;
+			noStrip = FALSE;
+			}
+		    }
+		break;
+	    default :
+		if (prevWord == NULL)
+		    prevWord = cmdLine;
+		break;
+		}
+	if (argc >= maxArgv - 1)
+	    break;
+	cmdLine++;
+	}
+
+    if ((prevWord != NULL || (inQuote && prevWord != NULL)) && argc < maxArgv - 1) {
+	*cmdLine = '\0';
+	argv [argc++] = prevWord;
+	}
+    argv[argc] = NULL;
+
+    /* Return updated parameters */
+    return (*pargc = argc);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/gabeos.c b/board/MAI/bios_emulator/scitech/src/common/gabeos.c
new file mode 100755
index 0000000..a934bd1
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gabeos.c
@@ -0,0 +1,146 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the Linux operating system.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+#include <sys/time.h>
+
+static ibool            haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    PM_setLocalBPDPath(path);
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+In order to support deploying new Nucleus drivers that may require updated
+PM library functions, we check here to see if there is a system wide version
+of the PM functions available. If so we return those functions for use with
+the system wide Nucleus drivers, otherwise the compiled in version of the PM
+library is used with the application local version of Nucleus.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    /* TODO: We may very well want to provide a system shared library */
+    /*       that eports the PM functions required by the Nucleus library */
+    /*       for BeOS here. That will eliminate fatal errors loading new */
+    /*       drivers on BeOS! */
+    return &_PM_imports;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    (void)gaExp;
+    (void)shared;
+    return false;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	haveRDTSC = true;
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else {
+	struct timeval t;
+	gettimeofday(&t, NULL);
+	value->low = t.tv_sec*1000000 + t.tv_usec;
+	value->high = 0;
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/gados.c b/board/MAI/bios_emulator/scitech/src/common/gados.c
new file mode 100755
index 0000000..d2be776
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gados.c
@@ -0,0 +1,135 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  MSDOS
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the MSDOS operating system.
+*
+****************************************************************************/
+
+#include "pm_help.h"
+#include "pmapi.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    PM_setLocalBPDPath(path);
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+Nothing to do here for DOS. Basically since DOS has no system wide shared
+library mechanism we are essentially screwed if the binary API changes.
+By default for 32-bit DOS apps the local Nucleus drivers should always be
+used in preference to the system wide Nucleus drivers.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    return &_PM_imports;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    (void)gaExp;
+    (void)shared;
+    return false;
+}
+
+#if !defined(TEST_HARNESS) && !defined(VBETEST)
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the DOS
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    _GA_readTimeStamp(value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/galib.c b/board/MAI/bios_emulator/scitech/src/common/galib.c
new file mode 100755
index 0000000..f2eacc3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/galib.c
@@ -0,0 +1,268 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Any 32-bit protected mode environment
+*
+* Description:  C module for the Graphics Accelerator Driver API. Uses
+*               the SciTech PM library for interfacing with DOS
+*               extender specific functions.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__)
+#include "sdd/sddhelp.h"
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+/*---------------------------- Global Variables ---------------------------*/
+
+#ifndef TEST_HARNESS
+GA_exports  _VARAPI __GA_exports;
+static int          loaded = false;
+static PE_MODULE    *hModBPD = NULL;
+
+static N_imports _N_imports = {
+    sizeof(N_imports),
+    _OS_delay,
+    };
+
+static GA_imports _GA_imports = {
+    sizeof(GA_imports),
+    GA_getSharedInfo,
+    GA_TimerInit,
+    GA_TimerRead,
+    GA_TimerDifference,
+    };
+#endif
+
+/*----------------------------- Implementation ----------------------------*/
+
+#define DLL_NAME        "graphics.bpd"
+
+/****************************************************************************
+REMARKS:
+This function is no longer used but we must implement it and return NULL
+for compatibility with older binary drivers.
+****************************************************************************/
+GA_sharedInfo * NAPI GA_getSharedInfo(
+    int device)
+{
+    return NULL;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Fatal error handler for non-exported GA_exports.
+****************************************************************************/
+static void _GA_fatalErrorHandler(void)
+{
+    PM_fatalError("Unsupported Nucleus export function called! Please upgrade your copy of Nucleus!\n");
+}
+
+/****************************************************************************
+PARAMETERS:
+shared  - True to load the driver into shared memory.
+
+REMARKS:
+Loads the Nucleus binary portable DLL into memory and initilises it.
+****************************************************************************/
+static ibool LoadDriver(
+    ibool shared)
+{
+    GA_initLibrary_t    GA_initLibrary;
+    GA_exports          *gaExp;
+    char                filename[PM_MAX_PATH];
+    char                bpdpath[PM_MAX_PATH];
+    int                 i,max;
+    ulong               *p;
+
+    /* Check if we have already loaded the driver */
+    if (loaded)
+	return true;
+    PM_init();
+
+    /* First try to see if we can find the system wide shared exports
+     * if they are available. Under OS/2 this connects to our global
+     * shared Nucleus loader in SDDPMI.DLL.
+     */
+    __GA_exports.dwSize = sizeof(__GA_exports);
+    if (GA_getSharedExports(&__GA_exports,shared))
+	return loaded = true;
+
+    /* Open the BPD file */
+    if (!PM_findBPD(DLL_NAME,bpdpath))
+	return false;
+    strcpy(filename,bpdpath);
+    strcat(filename,DLL_NAME);
+    if ((hModBPD = PE_loadLibrary(filename,shared)) == NULL)
+	return false;
+    if ((GA_initLibrary = (GA_initLibrary_t)PE_getProcAddress(hModBPD,"_GA_initLibrary")) == NULL)
+	return false;
+    bpdpath[strlen(bpdpath)-1] = 0;
+    if (strcmp(bpdpath,PM_getNucleusPath()) == 0)
+	strcpy(bpdpath,PM_getNucleusConfigPath());
+    else {
+	PM_backslash(bpdpath);
+	strcat(bpdpath,"config");
+	}
+    if ((gaExp = GA_initLibrary(shared,bpdpath,filename,GA_getSystemPMImports(),&_N_imports,&_GA_imports)) == NULL)
+	PM_fatalError("GA_initLibrary failed!\n");
+
+    /* Initialize all default imports to point to fatal error handler
+     * for upwards compatibility, and copy the exported functions.
+     */
+    max = sizeof(__GA_exports)/sizeof(GA_initLibrary_t);
+    for (i = 0,p = (ulong*)&__GA_exports; i < max; i++)
+	*p++ = (ulong)_GA_fatalErrorHandler;
+    memcpy(&__GA_exports,gaExp,MIN(sizeof(__GA_exports),gaExp->dwSize));
+    loaded = true;
+    return true;
+}
+
+/* The following are stub entry points that the application calls to
+ * initialise the Nucleus loader library, and we use this to load our
+ * driver DLL from disk and initialise the library using it.
+ */
+
+/* {secret} */
+int NAPI GA_status(void)
+{
+    if (!loaded)
+	return nDriverNotFound;
+    return __GA_exports.GA_status();
+}
+
+/* {secret} */
+const char * NAPI GA_errorMsg(
+    N_int32 status)
+{
+    if (!loaded)
+	return "Unable to load Nucleus device driver!";
+    return __GA_exports.GA_errorMsg(status);
+}
+
+/* {secret} */
+int NAPI GA_getDaysLeft(N_int32 shared)
+{
+    if (!LoadDriver(shared))
+	return -1;
+    return __GA_exports.GA_getDaysLeft(shared);
+}
+
+/* {secret} */
+int NAPI GA_registerLicense(uchar *license,N_int32 shared)
+{
+    if (!LoadDriver(shared))
+	return 0;
+    return __GA_exports.GA_registerLicense(license,shared);
+}
+
+/* {secret} */
+ibool NAPI GA_loadInGUI(N_int32 shared)
+{
+    if (!LoadDriver(shared))
+	return false;
+    return __GA_exports.GA_loadInGUI(shared);
+}
+
+/* {secret} */
+int NAPI GA_enumerateDevices(N_int32 shared)
+{
+    if (!LoadDriver(shared))
+	return 0;
+    return __GA_exports.GA_enumerateDevices(shared);
+}
+
+/* {secret} */
+GA_devCtx * NAPI GA_loadDriver(N_int32 deviceIndex,N_int32 shared)
+{
+    if (!LoadDriver(shared))
+	return NULL;
+    return __GA_exports.GA_loadDriver(deviceIndex,shared);
+}
+
+/* {secret} */
+void NAPI GA_getGlobalOptions(
+    GA_globalOptions *options,
+    ibool shared)
+{
+    if (LoadDriver(shared))
+	__GA_exports.GA_getGlobalOptions(options,shared);
+}
+
+/* {secret} */
+PE_MODULE * NAPI GA_loadLibrary(
+    const char *szBPDName,
+    ulong *size,
+    ibool shared)
+{
+    if (!LoadDriver(shared))
+	return NULL;
+    return __GA_exports.GA_loadLibrary(szBPDName,size,shared);
+}
+
+/* {secret} */
+GA_devCtx * NAPI GA_getCurrentDriver(
+    N_int32 deviceIndex)
+{
+    /* Bail for older drivers that didn't export this function! */
+    if (!__GA_exports.GA_getCurrentDriver)
+	return NULL;
+    return __GA_exports.GA_getCurrentDriver(deviceIndex);
+}
+
+/* {secret} */
+REF2D_driver * NAPI GA_getCurrentRef2d(
+    N_int32 deviceIndex)
+{
+    /* Bail for older drivers that didn't export this function! */
+    if (!__GA_exports.GA_getCurrentRef2d)
+	return NULL;
+    return __GA_exports.GA_getCurrentRef2d(deviceIndex);
+}
+
+/* {secret} */
+int NAPI GA_isOEMVersion(ibool shared)
+{
+    if (!LoadDriver(shared))
+	return 0;
+    return __GA_exports.GA_isOEMVersion(shared);
+}
+
+/* {secret} */
+N_uint32 * NAPI GA_getLicensedDevices(ibool shared)
+{
+    if (!LoadDriver(shared))
+	return 0;
+    return __GA_exports.GA_getLicensedDevices(shared);
+}
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/common/galinux.c b/board/MAI/bios_emulator/scitech/src/common/galinux.c
new file mode 100755
index 0000000..47e4e85
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/galinux.c
@@ -0,0 +1,148 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the Linux operating system.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+#include <sys/time.h>
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static ibool        haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    PM_setLocalBPDPath(path);
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+In order to support deploying new Nucleus drivers that may require updated
+PM library functions, we check here to see if there is a system wide version
+of the PM functions available. If so we return those functions for use with
+the system wide Nucleus drivers, otherwise the compiled in version of the PM
+library is used with the application local version of Nucleus.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    /* TODO: We may very well want to provide a system shared library */
+    /*       that eports the PM functions required by the Nucleus library */
+    /*       for Linux here. That will eliminate fatal errors loading new */
+    /*       drivers on Linux! */
+    return &_PM_imports;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    (void)gaExp;
+    (void)shared;
+    return false;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	haveRDTSC = true;
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else {
+	struct timeval t;
+	gettimeofday(&t, NULL);
+	value->low = t.tv_sec*1000000 + t.tv_usec;
+	value->high = 0;
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/gantdrv.c b/board/MAI/bios_emulator/scitech/src/common/gantdrv.c
new file mode 100755
index 0000000..050f737
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gantdrv.c
@@ -0,0 +1,136 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  NT device driver
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the NT device drivers.
+*
+****************************************************************************/
+
+#include "sdd/sddhelp.h"
+
+/*------------------------- Global Variables ------------------------------*/
+
+static ibool            haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    PM_setLocalBPDPath(path);
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    return &_PM_imports;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    (void)gaExp;
+    (void)shared;
+    return false;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) {
+	haveRDTSC = true;
+	}
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else
+	KeQuerySystemTime((LARGE_INTEGER*)value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/gaos2.c b/board/MAI/bios_emulator/scitech/src/common/gaos2.c
new file mode 100755
index 0000000..26e6503
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gaos2.c
@@ -0,0 +1,248 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  OS/2 32-bit
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the OS/2 operating system environments.
+*
+****************************************************************************/
+
+#include "pm_help.h"
+#define INCL_DOSERRORS
+#define INCL_DOS
+#define INCL_SUB
+#define INCL_VIO
+#define INCL_KBD
+#include <os2.h>
+
+/*--------------------------- Global variables ----------------------------*/
+
+static ibool    haveRDTSC = false;
+static ulong    parms[3];       /* Must not cross 64Kb boundary!    */
+static ulong    result[4];      /* Must not cross 64Kb boundary!    */
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+func        - Helper device driver function to call
+
+RETURNS:
+First return value from the device driver in parmsOut[0]
+
+REMARKS:
+Function to open our helper device driver, call it and close the file
+handle. Note that we have to open the device driver for every call because
+of two problems:
+
+ 1. We cannot open a single file handle in a DLL that is shared amongst
+    programs, since every process must have it's own open file handle.
+
+ 2. For some reason there appears to be a limit of about 12 open file
+    handles on a device driver in the system. Hence when we open more
+    than about 12 file handles things start to go very strange.
+
+Hence we simply open the file handle every time that we need to call the
+device driver to work around these problems.
+****************************************************************************/
+static ulong CallSDDHelp(
+    int func)
+{
+    static ulong    inLen;          /* Must not cross 64Kb boundary!    */
+    static ulong    outLen;         /* Must not cross 64Kb boundary!    */
+    HFILE           hSDDHelp;
+
+    /* If this code in here fails, we are screwed! Many of our drivers
+     * use this code and don't have a C library, so we simply assume we
+     * can't fail here.
+     */
+    DosOpen(PMHELP_NAME,&hSDDHelp,&result[0],0,0,
+	    FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE,
+	    NULL);
+    DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,func,
+	     &parms, inLen = sizeof(parms), &inLen,
+	    &result, outLen = sizeof(result), &outLen);
+    DosClose(hSDDHelp);
+    return result[0];
+}
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    PM_setLocalBPDPath(path);
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+For OS/2 we don't need to do anything special because Nucleus is always
+loaded via the shared SDDPMI driver when SDD is loaded so we don't need
+a system wide PM library imports function.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    return &_PM_imports;
+}
+
+/****************************************************************************
+PARAMETERS:
+gaExp   - Place to store the exported functions
+shared  - True if connecting to the shared, global Nucleus driver
+
+REMARKS:
+For OS/2 if SDD is loaded we *always* connect to the shared Nucleus functions
+contained within the SDDPMI driver. This allows the Nucleus functions contained
+within this driver to be utilised by all Nucleus apps in the system and
+maintains a consistent state between versions.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    /* In test harness mode, we need to load a local copy of Nucleus */
+#if !defined (TEST_HARNESS) || defined (DEBUG_SDDPMI)
+    HMODULE     hModSDDPMI;
+    char        buf[80];
+    GA_exports  *exp;
+
+    /* Initialise the PM library and connect to our runtime DLL's */
+    PM_init();
+    if (CallSDDHelp(PMHELP_GETSHAREDEXP) != 0) {
+	/* We have found the shared Nucleus exports. Because not all processes
+	 * map to SDDPMI.DLL, we need to ensure that we connect to this
+	 * DLL so that it gets mapped into our address space (that is
+	 * where the shared Nucleus loader code is located). Simply doing a
+	 * DosLoadModule on it is enough for this.
+	 */
+	DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"SDDPMI.DLL",&hModSDDPMI);
+	exp = (GA_exports*)result[0];
+	memcpy(gaExp,exp,MIN(gaExp->dwSize,exp->dwSize));
+	return true;
+	}
+#endif
+    (void)shared;
+    return false;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	haveRDTSC = true;
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else
+	DosTmrQueryTime((QWORD*)value);
+}
+
+/****************************************************************************
+REMARKS:
+On OS/2, we need special memory allocation functions if we build SDDPMI in
+test harness mode. But if we build GATest etc. in test mode, we want to use
+the normal C runtime functions, so route them back here.
+****************************************************************************/
+
+#if defined (TEST_HARNESS) && !defined (DEBUG_SDDPMI)
+
+/* Undefine these macros first or we'll recurse to hell! */
+#undef malloc
+#undef calloc
+#undef realloc
+#undef free
+
+void *SDDPMI_malloc(size_t size) {
+    return malloc(size);
+}
+
+void *SDDPMI_calloc(size_t num, size_t size) {
+    return calloc(num, size);
+}
+
+void SDDPMI_free(void *ptr) {
+    free(ptr);
+}
+
+void *SDDPMI_realloc(void *ptr, size_t size) {
+    return realloc(ptr, size);
+}
+
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/common/gaqnx.c b/board/MAI/bios_emulator/scitech/src/common/gaqnx.c
new file mode 100755
index 0000000..525d662
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gaqnx.c
@@ -0,0 +1,149 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the QNX operating system.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+#include <time.h>
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static ibool        haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    PM_setLocalBPDPath(path);
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+In order to support deploying new Nucleus drivers that may require updated
+PM library functions, we check here to see if there is a system wide version
+of the PM functions available. If so we return those functions for use with
+the system wide Nucleus drivers, otherwise the compiled in version of the PM
+library is used with the application local version of Nucleus.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    /* TODO: We may very well want to provide a system shared library */
+    /*       that eports the PM functions required by the Nucleus library */
+    /*       for QNX here. That will eliminate fatal errors loading new */
+    /*       drivers on QNX! */
+    return &_PM_imports;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    (void)gaExp;
+    (void)shared;
+    return false;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	haveRDTSC = true;
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else {
+	struct timespec ts;
+
+	clock_gettime(CLOCK_REALTIME, &ts);
+	value->low = (ts.tv_nsec / 1000 + ts.tv_sec * 1000000);
+	value->high = 0;
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/gartt.c b/board/MAI/bios_emulator/scitech/src/common/gartt.c
new file mode 100755
index 0000000..3a41f59
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gartt.c
@@ -0,0 +1,139 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  RTTarget-32
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the RTTarget-32 operating system environments.
+*
+****************************************************************************/
+
+#include "nucleus/graphics.h"
+
+/*------------------------- Global Variables ------------------------------*/
+
+static ibool            haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    PM_setLocalBPDPath(path);
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+In order to support deploying new Nucleus drivers that may require updated
+PM library functions, we check here to see if there is a system wide version
+of the PM functions available. If so we return those functions for use with
+the system wide Nucleus drivers, otherwise the compiled in version of the PM
+library is used with the application local version of Nucleus.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    return &_PM_imports;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    (void)gaExp;
+    (void)shared;
+    return false;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) {
+	haveRDTSC = true;
+	return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/gasmx.c b/board/MAI/bios_emulator/scitech/src/common/gasmx.c
new file mode 100755
index 0000000..ae31941
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gasmx.c
@@ -0,0 +1,133 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  smx32
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the smx32 platform -- no vxD support.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "nucleus/graphics.h"
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    PM_setLocalBPDPath(path);
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+In order to support deploying new Nucleus drivers that may require updated
+PM library functions, we check here to see if there is a system wide version
+of the PM functions available. If so we return those functions for use with
+the system wide Nucleus drivers, otherwise the compiled in version of the PM
+library is used with the application local version of Nucleus.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    return &_PM_imports;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    (void)gaExp;
+    (void)shared;
+    return false;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    _GA_readTimeStamp(value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/gavxd.c b/board/MAI/bios_emulator/scitech/src/common/gavxd.c
new file mode 100755
index 0000000..fc8ba8d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gavxd.c
@@ -0,0 +1,136 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32 VxD
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the Win32 VxD's.
+*
+****************************************************************************/
+
+#include "sdd/sddhelp.h"
+
+/*------------------------- Global Variables ------------------------------*/
+
+static ibool            haveRDTSC;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    PM_setLocalBPDPath(path);
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    return &_PM_imports;
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    (void)gaExp;
+    (void)shared;
+    return false;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) {
+	haveRDTSC = true;
+	}
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else
+	VTD_Get_Real_Time(&value->high,&value->low);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/gawin32.c b/board/MAI/bios_emulator/scitech/src/common/gawin32.c
new file mode 100755
index 0000000..6944334
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gawin32.c
@@ -0,0 +1,255 @@
+/****************************************************************************
+*
+*                   SciTech Nucleus Graphics Architecture
+*
+*               Copyright (C) 1991-1998 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code contains proprietary technology      |
+*  |owned by SciTech Software, Inc., located at 505 Wall Street,        |
+*  |Chico, CA 95928 USA (http://www.scitechsoft.com).                   |
+*  |                                                                    |
+*  |The contents of this file are subject to the SciTech Nucleus        |
+*  |License; you may *not* use this file or related software except in  |
+*  |compliance with the License. You may obtain a copy of the License   |
+*  |at http://www.scitechsoft.com/nucleus-license.txt                   |
+*  |                                                                    |
+*  |Software distributed under the License is distributed on an         |
+*  |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or      |
+*  |implied. See the License for the specific language governing        |
+*  |rights and limitations under the License.                           |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32
+*
+* Description:  OS specific Nucleus Graphics Architecture services for
+*               the Win32 operating system environments.
+*
+****************************************************************************/
+
+#include "pm_help.h"
+#include "pmapi.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#define STRICT
+#define WIN32_LEAN_AND_MEAN
+#include <windows.h>
+
+/*------------------------- Global Variables ------------------------------*/
+
+#define DLL_NAME        "nga_w32.dll"
+
+extern HANDLE           _PM_hDevice;
+static HMODULE          hModDLL = NULL;
+static ibool            useRing0Driver = false;
+static ibool            haveRDTSC;
+static GA_largeInteger  countFreq;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+Loads the shared "nga_w32.dll" library from disk and connects to it. This
+library is *always* located in the same directory as the Nucleus
+graphics.bpd file.
+****************************************************************************/
+static ibool LoadSharedDLL(void)
+{
+    char                filename[PM_MAX_PATH];
+    char                bpdpath[PM_MAX_PATH];
+
+    /* Check if we have already loaded the DLL */
+    if (hModDLL)
+	return true;
+    PM_init();
+
+    /* Open the DLL file */
+    if (!PM_findBPD(DLL_NAME,bpdpath))
+	return false;
+    strcpy(filename,bpdpath);
+    strcat(filename,DLL_NAME);
+    if ((hModDLL = LoadLibrary(filename)) == NULL)
+	return false;
+    return true;
+}
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable.
+
+Note that for Win32 we also call into the loaded PMHELP device driver
+as necessary to change the local Nucleus path for system wide Nucleus
+drivers.
+****************************************************************************/
+void NAPI GA_setLocalPath(
+    const char *path)
+{
+    DWORD   inBuf[1];
+    DWORD   outBuf[1],outCnt;
+
+    PM_setLocalBPDPath(path);
+    if (_PM_hDevice != INVALID_HANDLE_VALUE) {
+	inBuf[0] = (DWORD)path;
+	DeviceIoControl(_PM_hDevice, PMHELP_GASETLOCALPATH32,
+	    inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &outCnt, NULL);
+	}
+}
+
+/****************************************************************************
+RETURNS:
+Pointer to the system wide PM library imports, or the internal version if none
+
+REMARKS:
+In order to support deploying new Nucleus drivers that may require updated
+PM library functions, we check here to see if there is a system wide version
+of the PM functions available. If so we return those functions for use with
+the system wide Nucleus drivers, otherwise the compiled in version of the PM
+library is used with the application local version of Nucleus.
+****************************************************************************/
+PM_imports * NAPI GA_getSystemPMImports(void)
+{
+    PM_imports * pmImp;
+    PM_imports * (NAPIP _GA_getSystemPMImports)(void);
+
+    if (LoadSharedDLL()) {
+	/* Note that Visual C++ build DLL's with only a single underscore in front
+	 * of the exported name while Watcom C provides two of them. We check for
+	 * both to allow working with either compiled DLL.
+	 */
+	if ((_GA_getSystemPMImports = (void*)GetProcAddress(hModDLL,"_GA_getSystemPMImports")) != NULL) {
+	    if ((_GA_getSystemPMImports = (void*)GetProcAddress(hModDLL,"__GA_getSystemPMImports")) != NULL) {
+		pmImp = _GA_getSystemPMImports();
+		memcpy(&_PM_imports,pmImp,MIN(_PM_imports.dwSize,pmImp->dwSize));
+		return pmImp;
+		}
+	    }
+	}
+    return &_PM_imports;
+}
+
+/****************************************************************************
+PARAMETERS:
+gaExp   - Place to store the exported functions
+shared  - True if connecting to the shared, global Nucleus driver
+
+REMARKS:
+For Win32 if we are connecting to the shared, global Nucleus driver (loaded
+at ring 0) then we need to load a special nga_w32.dll library which contains
+thunks to call down into the Ring 0 device driver as necessary. If we are
+connecting to the application local Nucleus drivers (ie: Nucleus on DirectDraw
+emulation layer) then we do nothing here.
+****************************************************************************/
+ibool NAPI GA_getSharedExports(
+    GA_exports *gaExp,
+    ibool shared)
+{
+    GA_exports * exp;
+    GA_exports * (NAPIP _GA_getSystemGAExports)(void);
+
+    useRing0Driver = false;
+    if (shared) {
+	if (!LoadSharedDLL())
+	    PM_fatalError("Unable to load " DLL_NAME "!");
+	if ((_GA_getSystemGAExports = (void*)GetProcAddress(hModDLL,"_GA_getSystemGAExports")) == NULL)
+	    if ((_GA_getSystemGAExports = (void*)GetProcAddress(hModDLL,"__GA_getSystemGAExports")) == NULL)
+		PM_fatalError("Unable to load " DLL_NAME "!");
+	exp = _GA_getSystemGAExports();
+	memcpy(gaExp,exp,MIN(gaExp->dwSize,exp->dwSize));
+	useRing0Driver = true;
+	return true;
+	}
+    return false;
+}
+
+#ifndef TEST_HARNESS
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI GA_queryFunctions(
+    GA_devCtx *dc,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    static ibool (NAPIP _GA_queryFunctions)(GA_devCtx *dc,N_uint32 id,void _FAR_ *funcs) = NULL;
+
+    if (useRing0Driver) {
+	/* Call the version in nga_w32.dll if it is loaded */
+	if (!_GA_queryFunctions) {
+	    if ((_GA_queryFunctions = (void*)GetProcAddress(hModDLL,"_GA_queryFunctions")) == NULL)
+		if ((_GA_queryFunctions = (void*)GetProcAddress(hModDLL,"__GA_queryFunctions")) == NULL)
+		    PM_fatalError("Unable to get exports from " DLL_NAME "!");
+	    }
+	return _GA_queryFunctions(dc,id,funcs);
+	}
+    return __GA_exports.GA_queryFunctions(dc,id,funcs);
+}
+
+/****************************************************************************
+REMARKS:
+Nothing special for this OS
+****************************************************************************/
+ibool NAPI REF2D_queryFunctions(
+    REF2D_driver *ref2d,
+    N_uint32 id,
+    void _FAR_ *funcs)
+{
+    static ibool (NAPIP _REF2D_queryFunctions)(REF2D_driver *ref2d,N_uint32 id,void _FAR_ *funcs) = NULL;
+
+    if (useRing0Driver) {
+	/* Call the version in nga_w32.dll if it is loaded */
+	if (!_REF2D_queryFunctions) {
+	    if ((_REF2D_queryFunctions = (void*)GetProcAddress(hModDLL,"_REF2D_queryFunctions")) == NULL)
+		if ((_REF2D_queryFunctions = (void*)GetProcAddress(hModDLL,"__REF2D_queryFunctions")) == NULL)
+		    PM_fatalError("Unable to get exports from " DLL_NAME "!");
+	    }
+	return _REF2D_queryFunctions(ref2d,id,funcs);
+	}
+    return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function initialises the high precision timing functions for the
+Nucleus loader library.
+****************************************************************************/
+ibool NAPI GA_TimerInit(void)
+{
+    if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) {
+	haveRDTSC = true;
+	return true;
+	}
+    else if (QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq)) {
+	haveRDTSC = false;
+	return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+This function reads the high resolution timer.
+****************************************************************************/
+void NAPI GA_TimerRead(
+    GA_largeInteger *value)
+{
+    if (haveRDTSC)
+	_GA_readTimeStamp(value);
+    else
+	QueryPerformanceCounter((LARGE_INTEGER*)value);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c b/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c
new file mode 100755
index 0000000..1d547e9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c
@@ -0,0 +1,436 @@
+/****************************************************************************
+*
+*                   VESA Generalized Timing Formula (GTF)
+*                               Version 1.1
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Developed by: SciTech Software, Inc.
+*
+* Language:     ANSI C
+* Environment:  Any.
+*
+* Description:  C module for generating GTF compatible timings given a set
+*               of input requirements. Translated from the original GTF
+*               1.14 spreadsheet definition.
+*
+*               Compile with #define TESTING to build a command line test
+*               program.
+*
+*               NOTE: The code in here has been written for clarity and
+*                     to follow the original GTF spec as closely as
+*                     possible.
+*
+****************************************************************************/
+
+#include "gtf.h"
+#ifndef __WIN32_VXD__
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <math.h>
+#endif
+
+/*------------------------- Global Variables ------------------------------*/
+
+static GTF_constants GC = {
+    1.8,                    /* Margin size as percentage of display     */
+    8,                      /* Character cell granularity               */
+    1,                      /* Minimum front porch in lines/chars       */
+    3,                      /* Width of V sync in lines                 */
+    8,                      /* Width of H sync as percent of total      */
+    550,                    /* Minimum vertical sync + back porch (us)  */
+    600,                    /* Blanking formula gradient                */
+    40,                     /* Blanking formula offset                  */
+    128,                    /* Blanking formula scaling factor          */
+    20,                     /* Blanking formula scaling factor weight   */
+    };
+
+/*-------------------------- Implementation -------------------------------*/
+
+#ifdef __WIN32_VXD__
+/* These functions are not supported in a VxD, so we stub them out so this
+ * module will at least compile. Calling the functions in here will do
+ * something wierd!
+ */
+double sqrt(double x)
+{ return x; }
+
+double floor(double x)
+{ return x; }
+
+double pow(double x,double y)
+{ return x*y; }
+#endif
+
+static double round(double v)
+{
+    return floor(v + 0.5);
+}
+
+static void GetInternalConstants(GTF_constants *c)
+/****************************************************************************
+*
+* Function:     GetInternalConstants
+* Parameters:   c   - Place to store the internal constants
+*
+* Description:  Calculates the rounded, internal set of GTF constants.
+*               These constants are different to the real GTF constants
+*               that can be set up for the monitor. The calculations to
+*               get these real constants are defined in the 'Work Area'
+*               after the constants are defined in the Excel spreadsheet.
+*
+****************************************************************************/
+{
+    c->margin = GC.margin;
+    c->cellGran = round(GC.cellGran);
+    c->minPorch = round(GC.minPorch);
+    c->vSyncRqd = round(GC.vSyncRqd);
+    c->hSync = GC.hSync;
+    c->minVSyncBP = GC.minVSyncBP;
+    if (GC.k == 0)
+	c->k = 0.001;
+    else
+	c->k = GC.k;
+    c->m = (c->k / 256) * GC.m;
+    c->c = (GC.c - GC.j) * (c->k / 256) + GC.j;
+    c->j = GC.j;
+}
+
+void GTF_calcTimings(double hPixels,double vLines,double freq,
+    int type,ibool wantMargins,ibool wantInterlace,GTF_timings *t)
+/****************************************************************************
+*
+* Function:     GTF_calcTimings
+* Parameters:   hPixels     - X resolution
+*               vLines      - Y resolution
+*               freq        - Frequency (Hz, KHz or MHz depending on type)
+*               type        - 1 - vertical, 2 - horizontal, 3 - dot clock
+*               margins     - True if margins should be generated
+*               interlace   - True if interlaced timings to be generated
+*               t           - Place to store the resulting timings
+*
+* Description:  Calculates a set of GTF timing parameters given a specified
+*               resolution and vertical frequency. The horizontal frequency
+*               and dot clock will be automatically generated by this
+*               routines.
+*
+*               For interlaced modes the CRTC parameters are calculated for
+*               a single field, so will be half what would be used in
+*               a non-interlaced mode.
+*
+****************************************************************************/
+{
+    double          interlace,vFieldRate,hPeriod;
+    double          topMarginLines,botMarginLines;
+    double          leftMarginPixels,rightMarginPixels;
+    double          hPeriodEst,vSyncBP,vBackPorch;
+    double          vTotalLines,vFieldRateEst;
+    double          hTotalPixels,hTotalActivePixels,hBlankPixels;
+    double          idealDutyCycle,hSyncWidth,hSyncBP,hBackPorch;
+    double          idealHPeriod;
+    double          vFreq,hFreq,dotClock;
+    GTF_constants   c;
+
+    /* Get rounded GTF constants used for internal calculations */
+    GetInternalConstants(&c);
+
+    /* Move input parameters into appropriate variables */
+    vFreq = hFreq = dotClock = freq;
+
+    /* Round pixels to character cell granularity */
+    hPixels = round(hPixels / c.cellGran) * c.cellGran;
+
+    /* For interlaced mode halve the vertical parameters, and double
+     * the required field refresh rate.
+     */
+    vFieldRate = vFreq;
+    interlace = 0;
+    if (wantInterlace)
+	dotClock *= 2;
+
+    /* Determine the lines for margins */
+    if (wantMargins) {
+	topMarginLines = round(c.margin / 100 * vLines);
+	botMarginLines = round(c.margin / 100 * vLines);
+	}
+    else {
+	topMarginLines = 0;
+	botMarginLines = 0;
+	}
+
+    if (type != GTF_lockPF) {
+	if (type == GTF_lockVF) {
+	    /* Estimate the horizontal period */
+	    hPeriodEst = ((1/vFieldRate) - (c.minVSyncBP/1000000)) /
+		(vLines + (2*topMarginLines) + c.minPorch + interlace) * 1000000;
+
+	    /* Find the number of lines in vSync + back porch */
+	    vSyncBP = round(c.minVSyncBP / hPeriodEst);
+	    }
+	else if (type == GTF_lockHF) {
+	    /* Find the number of lines in vSync + back porch */
+	    vSyncBP = round((c.minVSyncBP * hFreq) / 1000);
+	    }
+
+	/* Find the number of lines in the V back porch alone */
+	vBackPorch = vSyncBP - c.vSyncRqd;
+
+	/* Find the total number of lines in the vertical period */
+	vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP
+	    + interlace + c.minPorch;
+
+	if (type == GTF_lockVF) {
+	    /* Estimate the vertical frequency */
+	    vFieldRateEst = 1000000 / (hPeriodEst * vTotalLines);
+
+	    /* Find the actual horizontal period */
+	    hPeriod = (hPeriodEst * vFieldRateEst) / vFieldRate;
+
+	    /* Find the actual vertical field frequency */
+	    vFieldRate = 1000000 / (hPeriod * vTotalLines);
+	    }
+	else if (type == GTF_lockHF) {
+	    /* Find the actual vertical field frequency */
+	    vFieldRate = (hFreq / vTotalLines) * 1000;
+	    }
+	}
+
+    /* Find the number of pixels in the left and right margins */
+    if (wantMargins) {
+	leftMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran);
+	rightMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran);
+	}
+    else {
+	leftMarginPixels = 0;
+	rightMarginPixels = 0;
+	}
+
+    /* Find the total number of active pixels in image + margins */
+    hTotalActivePixels = hPixels + leftMarginPixels + rightMarginPixels;
+
+    if (type == GTF_lockVF) {
+	/* Find the ideal blanking duty cycle */
+	idealDutyCycle = c.c - ((c.m * hPeriod) / 1000);
+	}
+    else if (type == GTF_lockHF) {
+	/* Find the ideal blanking duty cycle */
+	idealDutyCycle = c.c - (c.m / hFreq);
+	}
+    else if (type == GTF_lockPF) {
+	/* Find ideal horizontal period from blanking duty cycle formula */
+	idealHPeriod = (((c.c - 100) + (sqrt((pow(100-c.c,2)) +
+	    (0.4 * c.m * (hTotalActivePixels + rightMarginPixels +
+	    leftMarginPixels) / dotClock)))) / (2 * c.m)) * 1000;
+
+	/* Find the ideal blanking duty cycle */
+	idealDutyCycle = c.c - ((c.m * idealHPeriod) / 1000);
+	}
+
+    /* Find the number of pixels in blanking time */
+    hBlankPixels = round((hTotalActivePixels * idealDutyCycle) /
+	((100 - idealDutyCycle) * c.cellGran)) * c.cellGran;
+
+    /* Find the total number of pixels */
+    hTotalPixels = hTotalActivePixels + hBlankPixels;
+
+    /* Find the horizontal back porch */
+    hBackPorch = round((hBlankPixels / 2) / c.cellGran) * c.cellGran;
+
+    /* Find the horizontal sync width */
+    hSyncWidth = round(((c.hSync/100) * hTotalPixels) / c.cellGran) * c.cellGran;
+
+    /* Find the horizontal sync + back porch */
+    hSyncBP = hBackPorch + hSyncWidth;
+
+    if (type == GTF_lockPF) {
+	/* Find the horizontal frequency */
+	hFreq = (dotClock / hTotalPixels) * 1000;
+
+	/* Find the number of lines in vSync + back porch */
+	vSyncBP = round((c.minVSyncBP * hFreq) / 1000);
+
+	/* Find the number of lines in the V back porch alone */
+	vBackPorch = vSyncBP - c.vSyncRqd;
+
+	/* Find the total number of lines in the vertical period */
+	vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP
+	    + interlace + c.minPorch;
+
+	/* Find the actual vertical field frequency */
+	vFieldRate = (hFreq / vTotalLines) * 1000;
+	}
+    else {
+	if (type == GTF_lockVF) {
+	    /* Find the horizontal frequency */
+	    hFreq = 1000 / hPeriod;
+	    }
+	else if (type == GTF_lockHF) {
+	    /* Find the horizontal frequency */
+	    hPeriod = 1000 / hFreq;
+	    }
+
+	/* Find the pixel clock frequency */
+	dotClock = hTotalPixels / hPeriod;
+	}
+
+    /* Return the computed frequencies */
+    t->vFreq = vFieldRate;
+    t->hFreq = hFreq;
+    t->dotClock = dotClock;
+
+    /* Determine the vertical timing parameters */
+    t->h.hTotal = (int)hTotalPixels;
+    t->h.hDisp = (int)hTotalActivePixels;
+    t->h.hSyncStart = t->h.hTotal - (int)hSyncBP;
+    t->h.hSyncEnd = t->h.hTotal - (int)hBackPorch;
+    t->h.hFrontPorch = t->h.hSyncStart - t->h.hDisp;
+    t->h.hSyncWidth = (int)hSyncWidth;
+    t->h.hBackPorch = (int)hBackPorch;
+
+    /* Determine the vertical timing parameters */
+    t->v.vTotal = (int)vTotalLines;
+    t->v.vDisp = (int)vLines;
+    t->v.vSyncStart = t->v.vTotal - (int)vSyncBP;
+    t->v.vSyncEnd = t->v.vTotal - (int)vBackPorch;
+    t->v.vFrontPorch = t->v.vSyncStart - t->v.vDisp;
+    t->v.vSyncWidth = (int)c.vSyncRqd;
+    t->v.vBackPorch = (int)vBackPorch;
+    if (wantInterlace) {
+	/* Halve the timings for interlaced modes */
+	t->v.vTotal /= 2;
+	t->v.vDisp /= 2;
+	t->v.vSyncStart /= 2;
+	t->v.vSyncEnd /= 2;
+	t->v.vFrontPorch /= 2;
+	t->v.vSyncWidth /= 2;
+	t->v.vBackPorch /= 2;
+	t->dotClock /= 2;
+	}
+
+    /* Mark as GTF timing using the sync polarities */
+    t->interlace = (wantInterlace) ? 'I' : 'N';
+    t->hSyncPol = '-';
+    t->vSyncPol = '+';
+}
+
+void GTF_getConstants(GTF_constants *constants)
+{ *constants = GC; }
+
+void GTF_setConstants(GTF_constants *constants)
+{ GC = *constants; }
+
+#ifdef  TESTING_GTF
+
+void main(int argc,char *argv[])
+{
+    FILE        *f;
+    double      xPixels,yPixels,freq;
+    ibool       interlace;
+    GTF_timings t;
+
+    if (argc != 5 && argc != 6) {
+	printf("Usage: GTFCALC <xPixels> <yPixels> <freq> [[Hz] [KHz] [MHz]] [I]\n");
+	printf("\n");
+	printf("where <xPixels> is the horizontal resolution of the mode, <yPixels> is the\n");
+	printf("vertical resolution of the mode. The <freq> value will be the frequency to\n");
+	printf("drive the calculations, and will be either the vertical frequency (in Hz)\n");
+	printf("the horizontal frequency (in KHz) or the dot clock (in MHz). To generate\n");
+	printf("timings for an interlaced mode, add 'I' to the end of the command line.\n");
+	printf("\n");
+	printf("For example to generate timings for 640x480 at 60Hz vertical:\n");
+	printf("\n");
+	printf("    GTFCALC 640 480 60 Hz\n");
+	printf("\n");
+	printf("For example to generate timings for 640x480 at 31.5KHz horizontal:\n");
+	printf("\n");
+	printf("    GTFCALC 640 480 31.5 KHz\n");
+	printf("\n");
+	printf("For example to generate timings for 640x480 with a 25.175Mhz dot clock:\n");
+	printf("\n");
+	printf("    GTFCALC 640 480 25.175 MHz\n");
+	printf("\n");
+	printf("GTFCALC will print a summary of the results found, and dump the CRTC\n");
+	printf("values to the UVCONFIG.CRT file in the format used by SciTech Display Doctor.\n");
+	exit(1);
+	}
+
+    /* Get values from command line */
+    xPixels = atof(argv[1]);
+    yPixels = atof(argv[2]);
+    freq = atof(argv[3]);
+    interlace = ((argc == 6) && (argv[5][0] == 'I'));
+
+    /* Compute the CRTC timings */
+    if (toupper(argv[4][0]) == 'H')
+	GTF_calcTimings(xPixels,yPixels,freq,GTF_lockVF,false,interlace,&t);
+    else if (toupper(argv[4][0]) == 'K')
+	GTF_calcTimings(xPixels,yPixels,freq,GTF_lockHF,false,interlace,&t);
+    else if (toupper(argv[4][0]) == 'M')
+	GTF_calcTimings(xPixels,yPixels,freq,GTF_lockPF,false,interlace,&t);
+    else {
+	printf("Unknown command line!\n");
+	exit(1);
+	}
+
+    /* Dump summary info to standard output */
+    printf("CRTC values for %.0fx%.0f @ %.2f %s\n", xPixels, yPixels, freq, argv[4]);
+    printf("\n");
+    printf("  hTotal      = %-4d    vTotal      = %-4d\n",
+	t.h.hTotal, t.v.vTotal);
+    printf("  hDisp       = %-4d    vDisp       = %-4d\n",
+	t.h.hDisp, t.v.vDisp);
+    printf("  hSyncStart  = %-4d    vSyncStart  = %-4d\n",
+	t.h.hSyncStart, t.v.vSyncStart);
+    printf("  hSyncEnd    = %-4d    vSyncEnd    = %-4d\n",
+	t.h.hSyncEnd, t.v.vSyncEnd);
+    printf("  hFrontPorch = %-4d    vFrontPorch = %-4d\n",
+	t.h.hFrontPorch, t.v.vFrontPorch);
+    printf("  hSyncWidth  = %-4d    vSyncWidth  = %-4d\n",
+	t.h.hSyncWidth, t.v.vSyncWidth);
+    printf("  hBackPorch  = %-4d    vBackPorch  = %-4d\n",
+	t.h.hBackPorch, t.v.vBackPorch);
+    printf("\n");
+    printf("  Interlaced  = %s\n", (t.interlace == 'I') ? "Yes" : "No");
+    printf("  H sync pol  = %c\n", t.hSyncPol);
+    printf("  V sync pol  = %c\n", t.vSyncPol);
+    printf("\n");
+    printf("  Vert freq   = %.2f Hz\n", t.vFreq);
+    printf("  Horiz freq  = %.2f KHz\n", t.hFreq);
+    printf("  Dot Clock   = %.2f Mhz\n",    t.dotClock);
+
+    /* Dump to file in format used by SciTech Display Doctor */
+    if ((f = fopen("UVCONFIG.CRT","w")) != NULL) {
+	fprintf(f, "[%.0f %.0f]\n", xPixels, yPixels);
+	fprintf(f, "%d %d %d %d '%c' %s\n",
+	    t.h.hTotal, t.h.hDisp,
+	    t.h.hSyncStart, t.h.hSyncEnd,
+	    t.hSyncPol, (t.interlace == 'I') ? "I" : "NI");
+	fprintf(f, "%d %d %d %d '%c'\n",
+	    t.v.vTotal, t.v.vDisp,
+	    t.v.vSyncStart, t.v.vSyncEnd,
+	    t.vSyncPol);
+	fprintf(f, "%.2f\n", t.dotClock);
+	fclose(f);
+	}
+}
+
+#endif  /* TESTING */
diff --git a/board/MAI/bios_emulator/scitech/src/common/libcimp.c b/board/MAI/bios_emulator/scitech/src/common/libcimp.c
new file mode 100755
index 0000000..ab73ad5
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/libcimp.c
@@ -0,0 +1,827 @@
+/****************************************************************************
+*
+*                       SciTech MGL Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Module to implement a the OS specific side of the Binary
+*               Portable DLL C runtime library. The functions in here
+*               are imported into the Binary Portable DLL's to implement
+*               OS specific services.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__)
+#include "drvlib/peloader.h"
+#include "drvlib/attrib.h"
+#include "drvlib/libc/init.h"
+#define __BUILDING_PE_LOADER__
+#include "drvlib/libc/file.h"
+#if defined(__WIN32_VXD__)
+#include "vxdfile.h"
+#endif
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <time.h>
+#include <signal.h>
+#include <fcntl.h>
+#if defined(__GNUC__) || defined(__UNIX__)
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#else
+#include <io.h>
+#endif
+#include "drvlib/attrib.h"
+#include "drvlib/libc/init.h"
+#define __BUILDING_PE_LOADER__
+#include "drvlib/libc/file.h"
+#if defined(__WINDOWS__) || defined(TNT) || defined(__RTTARGET__)
+#define WIN32_LEAN_AND_MEAN
+#define STRICT
+#include <windows.h>
+#endif
+#ifdef  __MSDOS__
+#include <dos.h>
+#endif
+#ifdef  __OS2__
+#define INCL_DOS
+#define INCL_DOSERRORS
+#define INCL_SUB
+#include <os2.h>
+#endif
+#endif
+
+/* No text or binary modes for Unix */
+
+#ifndef O_BINARY
+#define O_BINARY    0
+#define O_TEXT      0
+#endif
+
+/*--------------------------- Global variables ----------------------------*/
+
+#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__)
+#define MAX_FILES   16
+static FILE *openHandles[MAX_FILES] = {NULL};
+#endif
+
+/* <stdlib.h> stub functions */
+void    _CDECL stub_abort(void);
+int     _CDECL stub_atexit(void (*)(void));
+void *  _CDECL stub_calloc(size_t _nelem, size_t _size);
+void    _CDECL stub_exit(int _status);
+void    _CDECL stub_free(void *_ptr);
+char *  _CDECL stub_getenv(const char *_name);
+void *  _CDECL stub_malloc(size_t _size);
+void *  _CDECL stub_realloc(void *_ptr, size_t _size);
+int     _CDECL stub_system(const char *_s);
+int     _CDECL stub_putenv(const char *_val);
+
+/* <libc/file.h> stub functions */
+int     _CDECL stub_open(const char *_path, int _oflag, unsigned _mode);
+int     _CDECL stub_access(const char *_path, int _amode);
+int     _CDECL stub_close(int _fildes);
+off_t   _CDECL stub_lseek(int _fildes, off_t _offset, int _whence);
+size_t  _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte);
+int     _CDECL stub_unlink(const char *_path);
+size_t  _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte);
+int     _CDECL stub_isatty(int _fildes);
+
+/* <stdio.h> stub functions */
+int     _CDECL stub_remove(const char *_filename);
+int     _CDECL stub_rename(const char *_old, const char *_new);
+
+/* <time.h> stub functions */
+time_t  _CDECL stub_time(time_t *_tod);
+
+/* <signal.h> stub functions */
+int     _CDECL stub_raise(int);
+void *  _CDECL stub_signal(int, void *);
+
+/* <drvlib/attrib.h> functions */
+#define stub_OS_setfileattr    _OS_setfileattr
+#define stub_OS_getcurrentdate _OS_getcurrentdate
+
+LIBC_imports    _VARAPI ___imports = {
+    sizeof(LIBC_imports),
+
+    /* <stdlib.h> exports */
+    stub_abort,
+    stub_atexit,
+    stub_calloc,
+    stub_exit,
+    stub_free,
+    stub_getenv,
+    stub_malloc,
+    stub_realloc,
+    stub_system,
+    stub_putenv,
+
+    /* <libc/file.h> exports */
+    stub_open,
+    stub_access,
+    stub_close,
+    stub_lseek,
+    stub_read,
+    stub_unlink,
+    stub_write,
+    stub_isatty,
+
+    /* <stdio.h> exports */
+    stub_remove,
+    stub_rename,
+
+    /* <signal.h> functions */
+    stub_raise,
+    stub_signal,
+
+    /* <time.h> exports */
+    stub_time,
+
+    /* <drvlib/attrib.h> exports */
+    stub_OS_setfileattr,
+    stub_OS_getcurrentdate,
+    };
+
+/*---------------------- Stub function implementation ---------------------*/
+
+/* <stdlib.h> stub functions */
+void _CDECL stub_abort(void)
+{
+#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__)
+    abort();
+#endif
+}
+
+int _CDECL stub_atexit(void (*func)(void))
+{
+#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__)
+    return atexit((void(*)(void))func);
+#else
+    return -1;
+#endif
+}
+
+void * _CDECL stub_calloc(size_t _nelem, size_t _size)
+{ return __PM_calloc(_nelem,_size); }
+
+void _CDECL stub_exit(int _status)
+{
+#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__)
+    exit(_status);
+#endif
+}
+
+void _CDECL stub_free(void *_ptr)
+{ __PM_free(_ptr); }
+
+char * _CDECL stub_getenv(const char *_name)
+{
+#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__)
+    return NULL;
+#else
+    return getenv(_name);
+#endif
+}
+
+void * _CDECL stub_malloc(size_t _size)
+{ return __PM_malloc(_size); }
+
+void * _CDECL stub_realloc(void *_ptr, size_t _size)
+{ return __PM_realloc(_ptr,_size); }
+
+int _CDECL stub_system(const char *_s)
+{
+#if defined(__WINDOWS__) || defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) || defined(__RTTARGET__)
+    (void)_s;
+    return -1;
+#else
+    return system(_s);
+#endif
+}
+
+int _CDECL stub_putenv(const char *_val)
+{
+#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__)
+    return -1;
+#else
+    return putenv((char*)_val);
+#endif
+}
+
+time_t _CDECL stub_time(time_t *_tod)
+{
+#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__)
+    return 0;
+#else
+    return time(_tod);
+#endif
+}
+
+#if     defined(__MSDOS__)
+
+#if defined(TNT) && defined(_MSC_VER)
+
+void _CDECL _OS_setfileattr(const char *filename,unsigned attrib)
+{ SetFileAttributes((LPSTR)filename, (DWORD)attrib); }
+
+#else
+
+void _CDECL _OS_setfileattr(const char *filename,unsigned attrib)
+{ _dos_setfileattr(filename,attrib); }
+
+#endif
+
+#elif   defined(__WIN32_VXD__)
+
+#define USE_LOCAL_FILEIO
+#define USE_LOCAL_GETDATE
+
+/* <libc/file.h> stub functions */
+int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode)
+{
+    char    mode[10];
+    int     i;
+
+    /* Find an empty file handle to use */
+    for (i = 3; i < MAX_FILES; i++) {
+	if (!openHandles[i])
+	    break;
+	}
+    if (openHandles[i])
+	return -1;
+
+    /* Find the open flags to use */
+    if (_oflag & ___O_TRUNC)
+	strcpy(mode,"w");
+    else if (_oflag & ___O_CREAT)
+	strcpy(mode,"a");
+    else
+	strcpy(mode,"r");
+    if (_oflag & ___O_BINARY)
+	strcat(mode,"b");
+    if (_oflag & ___O_TEXT)
+	strcat(mode,"t");
+
+    /* Open the file and store the file handle */
+    if ((openHandles[i] = fopen(_path,mode)) == NULL)
+	return -1;
+    return i;
+}
+
+int _CDECL stub_access(const char *_path, int _amode)
+{ return -1; }
+
+int _CDECL stub_close(int _fildes)
+{
+    if (_fildes >= 3 && openHandles[_fildes]) {
+	fclose(openHandles[_fildes]);
+	openHandles[_fildes] = NULL;
+	}
+    return 0;
+}
+
+off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence)
+{
+    if (_fildes >= 3) {
+	fseek(openHandles[_fildes],_offset,_whence);
+	return ftell(openHandles[_fildes]);
+	}
+    return 0;
+}
+
+size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte)
+{
+    if (_fildes >= 3)
+	return fread(_buf,1,_nbyte,openHandles[_fildes]);
+    return 0;
+}
+
+int _CDECL stub_unlink(const char *_path)
+{
+    WORD error;
+
+    if (initComplete) {
+	if (R0_DeleteFile((char*)_path,0,&error))
+	    return 0;
+	return -1;
+	}
+    else
+	return i_remove(_path);
+}
+
+size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte)
+{
+    if (_fildes >= 3)
+	return fwrite(_buf,1,_nbyte,openHandles[_fildes]);
+    return _nbyte;
+}
+
+int _CDECL stub_isatty(int _fildes)
+{ return 0; }
+
+/* <stdio.h> stub functions */
+int _CDECL stub_remove(const char *_filename)
+{ return stub_unlink(_filename); }
+
+int _CDECL stub_rename(const char *_old, const char *_new)
+{ return -1; }
+
+void _CDECL _OS_setfileattr(const char *filename,unsigned attrib)
+{
+    WORD error;
+    if (initComplete)
+	R0_SetFileAttributes((char*)filename,attrib,&error);
+}
+
+/* Return the current date in days since 1/1/1980 */
+ulong _CDECL _OS_getcurrentdate(void)
+{
+    DWORD   date;
+    VTD_Get_Date_And_Time(&date);
+    return date;
+}
+
+#elif   defined(__NT_DRIVER__)
+
+#define USE_LOCAL_FILEIO
+#define USE_LOCAL_GETDATE
+
+/* <libc/file.h> stub functions */
+int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode)
+{
+    char    mode[10];
+    int     i;
+
+    /* Find an empty file handle to use */
+    for (i = 3; i < MAX_FILES; i++) {
+	if (!openHandles[i])
+	    break;
+	}
+    if (openHandles[i])
+	return -1;
+
+    /* Find the open flags to use */
+    if (_oflag & ___O_TRUNC)
+	strcpy(mode,"w");
+    else if (_oflag & ___O_CREAT)
+	strcpy(mode,"a");
+    else
+	strcpy(mode,"r");
+    if (_oflag & ___O_BINARY)
+	strcat(mode,"b");
+    if (_oflag & ___O_TEXT)
+	strcat(mode,"t");
+
+    /* Open the file and store the file handle */
+    if ((openHandles[i] = fopen(_path,mode)) == NULL)
+	return -1;
+    return i;
+}
+
+int _CDECL stub_close(int _fildes)
+{
+    if (_fildes >= 3 && openHandles[_fildes]) {
+	fclose(openHandles[_fildes]);
+	openHandles[_fildes] = NULL;
+	}
+    return 0;
+}
+
+off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence)
+{
+    if (_fildes >= 3) {
+	fseek(openHandles[_fildes],_offset,_whence);
+	return ftell(openHandles[_fildes]);
+	}
+    return 0;
+}
+
+size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte)
+{
+    if (_fildes >= 3)
+	return fread(_buf,1,_nbyte,openHandles[_fildes]);
+    return 0;
+}
+
+size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte)
+{
+    if (_fildes >= 3)
+	return fwrite(_buf,1,_nbyte,openHandles[_fildes]);
+    return _nbyte;
+}
+
+int _CDECL stub_access(const char *_path, int _amode)
+{ return -1; }
+
+int _CDECL stub_isatty(int _fildes)
+{ return 0; }
+
+int _CDECL stub_unlink(const char *_path)
+{
+    /* TODO: Implement this! */
+    return -1;
+}
+
+/* <stdio.h> stub functions */
+int _CDECL stub_remove(const char *_filename)
+{ return stub_unlink(_filename); }
+
+int _CDECL stub_rename(const char *_old, const char *_new)
+{
+    /* TODO: Implement this! */
+    return -1;
+}
+
+void _CDECL _OS_setfileattr(const char *filename,unsigned attrib)
+{
+    uint _attr = 0;
+    if (attrib & __A_RDONLY)
+	_attr |= FILE_ATTRIBUTE_READONLY;
+    if (attrib & __A_HIDDEN)
+	_attr |= FILE_ATTRIBUTE_HIDDEN;
+    if (attrib & __A_SYSTEM)
+	_attr |= FILE_ATTRIBUTE_SYSTEM;
+    PM_setFileAttr(filename,_attr);
+}
+
+/* Return the current date in days since 1/1/1980 */
+ulong _CDECL _OS_getcurrentdate(void)
+{
+    TIME_FIELDS tm;
+    _int64      count,count_1_1_1980;
+
+    tm.Year         = 1980;
+    tm.Month        = 1;
+    tm.Day          = 1;
+    tm.Hour         = 0;
+    tm.Minute       = 0;
+    tm.Second       = 0;
+    tm.Milliseconds = 0;
+    tm.Weekday      = 0;
+    RtlTimeFieldsToTime(&tm,(PLARGE_INTEGER)&count_1_1_1980);
+    KeQuerySystemTime((PLARGE_INTEGER)&count);
+    return (ulong)( (count - count_1_1_1980) / ((_int64)24 * (_int64)3600 * (_int64)10000000) );
+}
+
+#elif   defined(__WINDOWS32__) || defined(__RTTARGET__)
+
+void _CDECL _OS_setfileattr(const char *filename,unsigned attrib)
+{ SetFileAttributes((LPSTR)filename, (DWORD)attrib); }
+
+#elif   defined(__OS2__)
+
+#define USE_LOCAL_FILEIO
+
+#ifndef W_OK
+#define W_OK                    0x02
+#endif
+
+void _CDECL _OS_setfileattr(const char *filename,unsigned attrib)
+{
+    FILESTATUS3 s;
+    if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s)))
+	return;
+    s.attrFile = attrib;
+    DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s),0L);
+}
+
+/* <libc/file.h> stub functions */
+
+#define BUF_SIZE    4096
+
+/* Note: the implementation of the standard Unix-ish handle-based I/O isn't
+ *       complete - but that wasn't the intent either. Note also that we
+ *       don't presently support text file I/O, so all text files end
+ *       up in Unix format (and are not translated!).
+ */
+int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode)
+{
+    HFILE   handle;
+    ULONG   error, actiontaken, openflag, openmode;
+    char    path[PM_MAX_PATH];
+
+    /* Determine open flags */
+    if (_oflag & ___O_CREAT) {
+	if (_oflag & ___O_EXCL)
+	    openflag = OPEN_ACTION_FAIL_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW;
+	else if (_oflag & ___O_TRUNC)
+	    openflag = OPEN_ACTION_REPLACE_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW;
+	else
+	    openflag = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW;
+	}
+    else if (_oflag & ___O_TRUNC)
+	openflag = OPEN_ACTION_REPLACE_IF_EXISTS;
+    else
+	openflag = OPEN_ACTION_OPEN_IF_EXISTS;
+
+    /* Determine open mode flags */
+    if (_oflag & ___O_RDONLY)
+	openmode = OPEN_ACCESS_READONLY | OPEN_SHARE_DENYNONE;
+    else if (_oflag & ___O_WRONLY)
+	openmode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_DENYWRITE;
+    else
+	openmode = OPEN_ACCESS_READWRITE | OPEN_SHARE_DENYWRITE;
+
+    /* Copy the path to a variable on the stack. We need to do this
+     * for OS/2 as when the drivers are loaded into shared kernel
+     * memory, we can't pass an address from that memory range to
+     * this function.
+     */
+    strcpy(path,_path);
+    if (DosOpen(path, &handle, &actiontaken, 0, FILE_NORMAL,
+	    openflag, openmode, NULL) != NO_ERROR)
+	return -1;
+
+    /* Handle append mode of operation */
+    if (_oflag & ___O_APPEND) {
+	if (DosSetFilePtr(handle, 0, FILE_END, &error) != NO_ERROR)
+	    return -1;
+	}
+    return handle;
+}
+
+int _CDECL stub_access(const char *_path, int _amode)
+{
+    char        path[PM_MAX_PATH];
+    FILESTATUS  fs;
+
+    /* Copy the path to a variable on the stack. We need to do this
+     * for OS/2 as when the drivers are loaded into shared kernel
+     * memory, we can't pass an address from that memory range to
+     * this function.
+     */
+    strcpy(path,_path);
+    if (DosQueryPathInfo(path, FIL_STANDARD, &fs, sizeof(fs)) != NO_ERROR)
+	return -1;
+    if ((_amode & W_OK) && (fs.attrFile & FILE_READONLY))
+	return -1;
+    return 0;
+}
+
+int _CDECL stub_close(int _fildes)
+{
+    if (DosClose(_fildes) != NO_ERROR)
+	return -1;
+    return 0;
+}
+
+off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence)
+{
+    ULONG  cbActual, origin;
+
+    switch (_whence) {
+	case SEEK_CUR:
+	    origin = FILE_CURRENT;
+	    break;
+	case SEEK_END:
+	    origin = FILE_END;
+	    break;
+	default:
+	    origin = FILE_BEGIN;
+	}
+    if (DosSetFilePtr(_fildes, _offset, origin, &cbActual) != NO_ERROR)
+	return -1;
+    return cbActual;
+}
+
+size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte)
+{
+    ULONG   cbActual = 0,cbRead;
+    uchar   *p = _buf;
+    uchar   file_io_buf[BUF_SIZE];
+
+    /* We need to perform the physical read in chunks into a
+     * a temporary static buffer, since the buffer passed in may be
+     * in kernel space and will cause DosRead to bail internally.
+     */
+    while (_nbyte > BUF_SIZE) {
+	if (DosRead(_fildes, file_io_buf, BUF_SIZE, &cbRead) != NO_ERROR)
+	    return -1;
+	cbActual += cbRead;
+	memcpy(p,file_io_buf,BUF_SIZE);
+	p += BUF_SIZE;
+	_nbyte -= BUF_SIZE;
+	}
+    if (_nbyte) {
+	if (DosRead(_fildes, file_io_buf, _nbyte, &cbRead) != NO_ERROR)
+	    return -1;
+	cbActual += cbRead;
+	memcpy(p,file_io_buf,_nbyte);
+	}
+    return cbActual;
+}
+
+size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte)
+{
+    ULONG   cbActual = 0,cbWrite;
+    uchar   *p = (PVOID)_buf;
+    uchar   file_io_buf[BUF_SIZE];
+
+    /* We need to perform the physical write in chunks from a
+     * a temporary static buffer, since the buffer passed in may be
+     * in kernel space and will cause DosWrite to bail internally.
+     */
+    while (_nbyte > BUF_SIZE) {
+	memcpy(file_io_buf,p,BUF_SIZE);
+	if (DosWrite(_fildes, file_io_buf, BUF_SIZE, &cbWrite) != NO_ERROR)
+	    return -1;
+	cbActual += cbWrite;
+	p += BUF_SIZE;
+	_nbyte -= BUF_SIZE;
+	}
+    if (_nbyte) {
+	memcpy(file_io_buf,p,_nbyte);
+	if (DosWrite(_fildes, file_io_buf, _nbyte, &cbWrite) != NO_ERROR)
+	    return -1;
+	cbActual += cbWrite;
+	}
+    return cbActual;
+}
+
+int _CDECL stub_unlink(const char *_path)
+{
+    char    path[PM_MAX_PATH];
+
+    /* Copy the path to a variable on the stack. We need to do this
+     * for OS/2 as when the drivers are loaded into shared kernel
+     * memory, we can't pass an address from that memory range to
+     * this function.
+     */
+    strcpy(path,_path);
+    if (DosDelete(path) != NO_ERROR)
+	return -1;
+    return 0;
+}
+
+int _CDECL stub_isatty(int _fildes)
+{
+    ULONG  htype, flags;
+
+    if (DosQueryHType(_fildes, &htype, &flags) != NO_ERROR)
+	return 0;
+    return ((htype & 0xFF) == HANDTYPE_DEVICE);
+}
+
+/* <stdio.h> stub functions */
+int _CDECL stub_remove(const char *_path)
+{
+    char    path[PM_MAX_PATH];
+
+    /* Copy the path to a variable on the stack. We need to do this
+     * for OS/2 as when the drivers are loaded into shared kernel
+     * memory, we can't pass an address from that memory range to
+     * this function.
+     */
+    strcpy(path,_path);
+    if (DosDelete(path) != NO_ERROR)
+	return -1;
+    return 0;
+}
+
+int _CDECL stub_rename(const char *_old, const char *_new)
+{
+    char    old[PM_MAX_PATH];
+    char    new[PM_MAX_PATH];
+
+    /* Copy the path to a variable on the stack. We need to do this
+     * for OS/2 as when the drivers are loaded into shared kernel
+     * memory, we can't pass an address from that memory range to
+     * this function.
+     */
+    strcpy(old,_old);
+    strcpy(new,_new);
+    if (DosMove(old, new) != NO_ERROR)
+	return -1;
+    return 0;
+}
+
+#else
+
+void _CDECL _OS_setfileattr(const char *filename,unsigned attrib)
+{ /* Unable to set hidden, system attributes on Unix. */ }
+
+#endif
+
+#ifndef USE_LOCAL_FILEIO
+
+/* <libc/file.h> stub functions */
+int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode)
+{
+    int oflag_tab[] = {
+	___O_RDONLY,    O_RDONLY,
+	___O_WRONLY,    O_WRONLY,
+	___O_RDWR,      O_RDWR,
+	___O_BINARY,    O_BINARY,
+	___O_TEXT,      O_TEXT,
+	___O_CREAT,     O_CREAT,
+	___O_EXCL,      O_EXCL,
+	___O_TRUNC,     O_TRUNC,
+	___O_APPEND,    O_APPEND,
+	};
+    int i,oflag = 0;
+
+    /* Translate the oflag's to the OS dependent versions */
+    for (i = 0; i < sizeof(oflag_tab) / sizeof(int); i += 2) {
+	if (_oflag & oflag_tab[i])
+	    oflag |= oflag_tab[i+1];
+	}
+    return open(_path,oflag,_mode);
+}
+
+int _CDECL stub_access(const char *_path, int _amode)
+{ return access(_path,_amode); }
+
+int _CDECL stub_close(int _fildes)
+{ return close(_fildes); }
+
+off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence)
+{ return lseek(_fildes,_offset,_whence); }
+
+size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte)
+{ return read(_fildes,_buf,_nbyte); }
+
+int _CDECL stub_unlink(const char *_path)
+{ return unlink(_path); }
+
+size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte)
+{ return write(_fildes,_buf,_nbyte); }
+
+int _CDECL stub_isatty(int _fildes)
+{ return isatty(_fildes); }
+
+/* <stdio.h> stub functions */
+int _CDECL stub_remove(const char *_filename)
+{ return remove(_filename); }
+
+int _CDECL stub_rename(const char *_old, const char *_new)
+{ return rename(_old,_new); }
+
+#endif
+
+#ifndef USE_LOCAL_GETDATE
+
+/* Return the current date in days since 1/1/1980 */
+ulong _CDECL _OS_getcurrentdate(void)
+{
+    struct tm refTime;
+    refTime.tm_year = 80;
+    refTime.tm_mon  = 0;
+    refTime.tm_mday = 1;
+    refTime.tm_hour = 0;
+    refTime.tm_min  = 0;
+    refTime.tm_sec  = 0;
+    refTime.tm_isdst = -1;
+    return (time(NULL) - mktime(&refTime)) / (24 * 3600L);
+}
+
+#endif
+
+int _CDECL stub_raise(int sig)
+{
+#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__)
+    return -1;
+#else
+    return raise(sig);
+#endif
+}
+
+#ifdef __WINDOWS32__
+typedef void (*__code_ptr)(int);
+#else
+typedef void (*__code_ptr)();
+#endif
+
+void * _CDECL stub_signal(int sig, void *handler)
+{
+#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__)
+    return NULL;
+#else
+    return (void*)signal(sig,(__code_ptr)handler);
+#endif
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/makefile b/board/MAI/bios_emulator/scitech/src/common/makefile
new file mode 100755
index 0000000..5aac038
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/makefile
@@ -0,0 +1,18 @@
+#############################################################################
+#
+#                   Copyright (C) 1996 SciTech Software.
+#                           All rights reserved.
+#
+# Descripton:   Makefile for UniVBE(tm), UniPOWER(tm), UVBELib(tm) and
+#               DPMSLib library files. Requires Borland C++ 4.52 to build
+#               some components.
+#
+# $Date: 2002/10/02 15:35:20 $ $Author: hfrieden $
+#
+#############################################################################
+
+CFLAGS += -DTESTING_GTF
+
+gtfcalc$E:  gtfcalc$O
+
+.INCLUDE: "$(SCITECH)/makedefs/common.mk"
diff --git a/board/MAI/bios_emulator/scitech/src/common/peloader.c b/board/MAI/bios_emulator/scitech/src/common/peloader.c
new file mode 100755
index 0000000..a134bb0
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/peloader.c
@@ -0,0 +1,586 @@
+/****************************************************************************
+*
+*                       SciTech MGL Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Module to implement a simple Portable Binary DLL loader
+*               library. This library can be used to load PE DLL's under
+*               any Intel based OS, provided the DLL's do not have any
+*               imports in the import table.
+*
+*               NOTE: This loader module expects the DLL's to be built with
+*                     Watcom C++ and may produce unexpected results with
+*                     DLL's linked by another compiler.
+*
+****************************************************************************/
+
+#include "drvlib/peloader.h"
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "drvlib/libc/init.h"
+#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED)
+#define WIN32_LEAN_AND_MEAN
+#define STRICT
+#include <windows.h>
+#endif
+#include "drvlib/pe.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+static int          result = PE_ok;
+
+/*------------------------- Implementation --------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+f           - Handle to open file to read driver from
+startOffset - Offset to the start of the driver within the file
+
+RETURNS:
+Handle to loaded PE DLL, or NULL on failure.
+
+REMARKS:
+This function loads a Portable Binary DLL library from disk, relocates
+the code and returns a handle to the loaded library. This function is the
+same as the regular PE_loadLibrary except that it take a handle to an
+open file and an offset within that file for the DLL to load.
+****************************************************************************/
+static int PE_readHeader(
+    FILE *f,
+    long startOffset,
+    FILE_HDR *filehdr,
+    OPTIONAL_HDR *opthdr)
+{
+    EXE_HDR exehdr;
+    ulong   offset,signature;
+
+    /* Read the EXE header and check for valid header signature */
+    result = PE_invalidDLLImage;
+    fseek(f, startOffset, SEEK_SET);
+    if (fread(&exehdr, 1, sizeof(exehdr), f) != sizeof(exehdr))
+	return false;
+    if (exehdr.signature != 0x5A4D)
+	return false;
+
+    /* Now seek to the start of the PE header defined at offset 0x3C
+     * in the MS-DOS EXE header, and read the signature and check it.
+     */
+    fseek(f, startOffset+0x3C, SEEK_SET);
+    if (fread(&offset, 1, sizeof(offset), f) != sizeof(offset))
+	return false;
+    fseek(f, startOffset+offset, SEEK_SET);
+    if (fread(&signature, 1, sizeof(signature), f) != sizeof(signature))
+	return false;
+    if (signature != 0x00004550)
+	return false;
+
+    /* Now read the PE file header and check that it is correct */
+    if (fread(filehdr, 1, sizeof(*filehdr), f) != sizeof(*filehdr))
+	return false;
+    if (filehdr->Machine != IMAGE_FILE_MACHINE_I386)
+	return false;
+    if (!(filehdr->Characteristics & IMAGE_FILE_32BIT_MACHINE))
+	return false;
+    if (!(filehdr->Characteristics & IMAGE_FILE_DLL))
+	return false;
+    if (fread(opthdr, 1, sizeof(*opthdr), f) != sizeof(*opthdr))
+	return false;
+    if (opthdr->Magic != 0x10B)
+	return false;
+
+    /* Success, so return true! */
+    return true;
+}
+
+/****************************************************************************
+PARAMETERS:
+f           - Handle to open file to read driver from
+startOffset - Offset to the start of the driver within the file
+
+RETURNS:
+Size of the DLL file on disk, or -1 on error
+
+REMARKS:
+This function scans the headers for a Portable Binary DLL to determine the
+length of the DLL file on disk.
+{secret}
+****************************************************************************/
+ulong PEAPI PE_getFileSize(
+    FILE *f,
+    ulong startOffset)
+{
+    FILE_HDR        filehdr;
+    OPTIONAL_HDR    opthdr;
+    SECTION_HDR     secthdr;
+    ulong           size;
+    int             i;
+
+    /* Read the PE file headers from disk */
+    if (!PE_readHeader(f,startOffset,&filehdr,&opthdr))
+	return 0xFFFFFFFF;
+
+    /* Scan all the section headers summing up the total size */
+    size = opthdr.SizeOfHeaders;
+    for (i = 0; i < filehdr.NumberOfSections; i++) {
+	if (fread(&secthdr, 1, sizeof(secthdr), f) != sizeof(secthdr))
+	    return 0xFFFFFFFF;
+	size += secthdr.SizeOfRawData;
+	}
+    return size;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Loads a Portable Binary DLL into memory from an open file
+
+HEADER:
+peloader.h
+
+PARAMETERS:
+f           - Handle to open file to read driver from
+startOffset - Offset to the start of the driver within the file
+size        - Place to store the size of the driver loaded
+shared      - True to load module into shared memory
+
+RETURNS:
+Handle to loaded PE DLL, or NULL on failure.
+
+REMARKS:
+This function loads a Portable Binary DLL library from disk, relocates
+the code and returns a handle to the loaded library. This function is the
+same as the regular PE_loadLibrary except that it take a handle to an
+open file and an offset within that file for the DLL to load.
+
+SEE ALSO:
+PE_loadLibrary, PE_getProcAddress, PE_freeLibrary
+****************************************************************************/
+PE_MODULE * PEAPI PE_loadLibraryExt(
+    FILE *f,
+    ulong startOffset,
+    ulong *size,
+    ibool shared)
+{
+    FILE_HDR        filehdr;
+    OPTIONAL_HDR    opthdr;
+    SECTION_HDR     secthdr;
+    ulong           offset,pageOffset;
+    ulong           text_off,text_addr,text_size;
+    ulong           data_off,data_addr,data_size,data_end;
+    ulong           export_off,export_addr,export_size,export_end;
+    ulong           reloc_off,reloc_size;
+    ulong           image_size;
+    int             i,delta,numFixups;
+    ushort          relocType,*fixup;
+    PE_MODULE       *hMod = NULL;
+    void            *reloc = NULL;
+    BASE_RELOCATION *baseReloc;
+    InitLibC_t      InitLibC;
+
+    /* Read the PE file headers from disk */
+    if (!PE_readHeader(f,startOffset,&filehdr,&opthdr))
+	return NULL;
+
+    /* Scan all the section headers and find the necessary sections */
+    text_off = data_off = reloc_off = export_off = 0;
+    text_addr = text_size = 0;
+    data_addr = data_size = data_end = 0;
+    export_addr = export_size = export_end = 0;
+    reloc_size = 0;
+    for (i = 0; i < filehdr.NumberOfSections; i++) {
+	if (fread(&secthdr, 1, sizeof(secthdr), f) != sizeof(secthdr))
+	    goto Error;
+	if (strcmp(secthdr.Name, ".edata") == 0 || strcmp(secthdr.Name, ".rdata") == 0) {
+	    /* Exports section */
+	    export_off = secthdr.PointerToRawData;
+	    export_addr = secthdr.VirtualAddress;
+	    export_size = secthdr.SizeOfRawData;
+	    export_end = export_addr + export_size;
+	    }
+	else if (strcmp(secthdr.Name, ".idata") == 0) {
+	    /* Imports section, ignore */
+	    }
+	else if (strcmp(secthdr.Name, ".reloc") == 0) {
+	    /* Relocations section */
+	    reloc_off = secthdr.PointerToRawData;
+	    reloc_size = secthdr.SizeOfRawData;
+	    }
+	else if (!text_off && secthdr.Characteristics & IMAGE_SCN_CNT_CODE) {
+	    /* Code section */
+	    text_off = secthdr.PointerToRawData;
+	    text_addr = secthdr.VirtualAddress;
+	    text_size = secthdr.SizeOfRawData;
+	    }
+	else if (!data_off && secthdr.Characteristics & IMAGE_SCN_CNT_INITIALIZED_DATA) {
+	    /* Data section */
+	    data_off = secthdr.PointerToRawData;
+	    data_addr = secthdr.VirtualAddress;
+	    data_size = secthdr.SizeOfRawData;
+	    data_end = data_addr + data_size;
+	    }
+	}
+
+    /* Check to make sure that we have all the sections we need */
+    if (!text_off || !data_off || !export_off || !reloc_off) {
+	result = PE_invalidDLLImage;
+	goto Error;
+	}
+
+    /* Find the size of the image to load allocate memory for it */
+    image_size = MAX(export_end,data_end) - text_addr;
+    *size = sizeof(PE_MODULE) + image_size + 4096;
+    if (shared)
+	hMod = PM_mallocShared(*size);
+    else
+	hMod = PM_malloc(*size);
+    reloc = PM_malloc(reloc_size);
+    if (!hMod || !reloc) {
+	result = PE_outOfMemory;
+	goto Error;
+	}
+
+    hMod->text = (uchar*)ROUND_4K((ulong)hMod + sizeof(PE_MODULE));
+    hMod->data = (uchar*)((ulong)hMod->text + (data_addr - text_addr));
+    hMod->export = (uchar*)((ulong)hMod->text + (export_addr - text_addr));
+    hMod->textBase = text_addr;
+    hMod->dataBase = data_addr;
+    hMod->exportBase = export_addr;
+    hMod->exportDir = opthdr.DataDirectory[0].RelVirtualAddress - export_addr;
+    hMod->shared = shared;
+
+    /* Now read the section images from disk */
+    result = PE_invalidDLLImage;
+    fseek(f, startOffset+text_off, SEEK_SET);
+    if (fread(hMod->text, 1, text_size, f) != text_size)
+	goto Error;
+    fseek(f, startOffset+data_off, SEEK_SET);
+    if (fread(hMod->data, 1, data_size, f) != data_size)
+	goto Error;
+    fseek(f, startOffset+export_off, SEEK_SET);
+    if (fread(hMod->export, 1, export_size, f) != export_size)
+	goto Error;
+    fseek(f, startOffset+reloc_off, SEEK_SET);
+    if (fread(reloc, 1, reloc_size, f) != reloc_size)
+	goto Error;
+
+    /* Now perform relocations on all sections in the image */
+    delta = (ulong)hMod->text - opthdr.ImageBase - text_addr;
+    baseReloc = (BASE_RELOCATION*)reloc;
+    for (;;) {
+	/* Check for termination condition */
+	if (!baseReloc->PageRVA || !baseReloc->BlockSize)
+	    break;
+
+	/* Do fixups */
+	pageOffset = baseReloc->PageRVA - hMod->textBase;
+	numFixups = (baseReloc->BlockSize - sizeof(BASE_RELOCATION)) / sizeof(ushort);
+	fixup = (ushort*)(baseReloc + 1);
+	for (i = 0; i < numFixups; i++) {
+	    relocType = *fixup >> 12;
+	    if (relocType) {
+		offset = pageOffset + (*fixup & 0x0FFF);
+		*(ulong*)(hMod->text + offset) += delta;
+		}
+	    fixup++;
+	    }
+
+	/* Move to next relocation block */
+	baseReloc = (BASE_RELOCATION*)((ulong)baseReloc + baseReloc->BlockSize);
+	}
+
+    /* Initialise the C runtime library for the loaded DLL */
+    result = PE_unableToInitLibC;
+    if ((InitLibC = (InitLibC_t)PE_getProcAddress(hMod,"_InitLibC")) == NULL)
+	goto Error;
+    if (!InitLibC(&___imports,PM_getOSType()))
+	goto Error;
+
+    /* Clean up, close the file and return the loaded module handle */
+    PM_free(reloc);
+    result = PE_ok;
+    return hMod;
+
+Error:
+    if (shared)
+	PM_freeShared(hMod);
+    else
+	PM_free(hMod);
+    PM_free(reloc);
+    return NULL;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Loads a Portable Binary DLL into memory
+
+HEADER:
+peloader.h
+
+PARAMETERS:
+szDLLName   - Name of the PE DLL library to load
+shared      - True to load module into shared memory
+
+RETURNS:
+Handle to loaded PE DLL, or NULL on failure.
+
+REMARKS:
+This function loads a Portable Binary DLL library from disk, relocates
+the code and returns a handle to the loaded library. This function
+will only work on DLL's that do not have any imports, since we don't
+resolve import dependencies in this function.
+
+SEE ALSO:
+PE_getProcAddress, PE_freeLibrary
+****************************************************************************/
+PE_MODULE * PEAPI PE_loadLibrary(
+    const char *szDLLName,
+    ibool shared)
+{
+    PE_MODULE   *hMod;
+
+#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED)
+    if (!shared) {
+	PM_MODULE       hInst;
+	InitLibC_t      InitLibC;
+
+	/* For Win32 if are building checked libraries for debugging, we use
+	 * the real Win32 DLL functions so that we can debug the resulting DLL
+	 * files with the Win32 debuggers. Note that we can't do this if
+	 * we need to load the files into a shared memory context.
+	 */
+	if ((hInst = PM_loadLibrary(szDLLName)) == NULL) {
+	    result = PE_fileNotFound;
+	    return NULL;
+	    }
+
+	/* Initialise the C runtime library for the loaded DLL */
+	result = PE_unableToInitLibC;
+	if ((InitLibC = (void*)PM_getProcAddress(hInst,"_InitLibC")) == NULL)
+	    return NULL;
+	if (!InitLibC(&___imports,PM_getOSType()))
+	    return NULL;
+
+	/* Allocate the PE_MODULE structure */
+	if ((hMod = PM_malloc(sizeof(*hMod))) == NULL)
+	    return NULL;
+	hMod->text = (void*)hInst;
+	hMod->shared = -1;
+
+	/* DLL loaded successfully so return module handle */
+	result = PE_ok;
+	return hMod;
+	}
+    else
+#endif
+	{
+	FILE        *f;
+	ulong       size;
+
+	/* Attempt to open the file on disk */
+	if (shared < 0)
+	    shared = 0;
+	if ((f = fopen(szDLLName,"rb")) == NULL) {
+	    result = PE_fileNotFound;
+	    return NULL;
+	    }
+	hMod = PE_loadLibraryExt(f,0,&size,shared);
+	fclose(f);
+	return hMod;
+	}
+}
+
+/****************************************************************************
+DESCRIPTION:
+Loads a Portable Binary DLL into memory
+
+HEADER:
+peloader.h
+
+PARAMETERS:
+szDLLName   - Name of the PE DLL library to load
+shared      - True to load module into shared memory
+
+RETURNS:
+Handle to loaded PE DLL, or NULL on failure.
+
+REMARKS:
+This function is the same as the regular PE_loadLibrary function, except
+that it looks for the drivers in the MGL_ROOT/drivers directory or a
+/drivers directory relative to the current directory.
+
+SEE ALSO:
+PE_loadLibraryMGL, PE_getProcAddress, PE_freeLibrary
+****************************************************************************/
+PE_MODULE * PEAPI PE_loadLibraryMGL(
+    const char *szDLLName,
+    ibool shared)
+{
+#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__)
+    PE_MODULE   *hMod;
+#endif
+    char        path[256] = "";
+
+    /* We look in the 'drivers' directory, optionally under the MGL_ROOT
+     * environment variable directory.
+     */
+#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__)
+    if (getenv("MGL_ROOT")) {
+	strcpy(path,getenv("MGL_ROOT"));
+	PM_backslash(path);
+	}
+    strcat(path,"drivers");
+    PM_backslash(path);
+    strcat(path,szDLLName);
+    if ((hMod = PE_loadLibrary(path,shared)) != NULL)
+	return hMod;
+#endif
+    strcpy(path,"drivers");
+    PM_backslash(path);
+    strcat(path,szDLLName);
+    return PE_loadLibrary(path,shared);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Gets a function address from a Portable Binary DLL
+
+HEADER:
+peloader.h
+
+PARAMETERS:
+hModule     - Handle to a loaded PE DLL library
+szProcName  - Name of the function to get the address of
+
+RETURNS:
+Pointer to the function, or NULL on failure.
+
+REMARKS:
+This function searches for the named, exported function in a loaded PE
+DLL library, and returns the address of the function. If the function is
+not found in the library, this function return NULL.
+
+SEE ALSO:
+PE_loadLibrary, PE_freeLibrary
+****************************************************************************/
+void * PEAPI PE_getProcAddress(
+    PE_MODULE *hModule,
+    const char *szProcName)
+{
+#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED)
+    if (hModule->shared == -1)
+	return (void*)PM_getProcAddress(hModule->text,szProcName);
+    else
+#endif
+	{
+	uint                i;
+	EXPORT_DIRECTORY    *exports;
+	ulong               funcOffset;
+	ulong               *AddressTable;
+	ulong               *NameTable;
+	ushort              *OrdinalTable;
+	char                *name;
+
+	/* Find the address of the export tables from the export section */
+	if (!hModule)
+	    return NULL;
+	exports = (EXPORT_DIRECTORY*)(hModule->export + hModule->exportDir);
+	AddressTable = (ulong*)(hModule->export + exports->AddressTableRVA - hModule->exportBase);
+	NameTable = (ulong*)(hModule->export + exports->NameTableRVA - hModule->exportBase);
+	OrdinalTable = (ushort*)(hModule->export + exports->OrdinalTableRVA - hModule->exportBase);
+
+	/* Search the export name table to find the function name */
+	for (i = 0; i < exports->NumberOfNamePointers; i++) {
+	    name = (char*)(hModule->export + NameTable[i] - hModule->exportBase);
+	    if (strcmp(name,szProcName) == 0)
+		break;
+	    }
+	if (i == exports->NumberOfNamePointers)
+	    return NULL;
+	funcOffset = AddressTable[OrdinalTable[i]];
+	if (!funcOffset)
+	    return NULL;
+	return (void*)(hModule->text + funcOffset - hModule->textBase);
+	}
+}
+
+/****************************************************************************
+DESCRIPTION:
+Frees a loaded Portable Binary DLL
+
+HEADER:
+peloader.h
+
+PARAMETERS:
+hModule     - Handle to a loaded PE DLL library to free
+
+REMARKS:
+This function frees a loaded PE DLL library from memory.
+
+SEE ALSO:
+PE_getProcAddress, PE_loadLibrary
+****************************************************************************/
+void PEAPI PE_freeLibrary(
+    PE_MODULE *hModule)
+{
+    TerminateLibC_t TerminateLibC;
+
+#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED)
+    if (hModule->shared == -1) {
+	/* Run the C runtime library exit code on module unload */
+	if ((TerminateLibC = (TerminateLibC_t)PM_getProcAddress(hModule->text,"_TerminateLibC")) != NULL)
+	    TerminateLibC();
+	PM_freeLibrary(hModule->text);
+	PM_free(hModule);
+	}
+    else
+#endif
+	{
+	if (hModule) {
+	    /* Run the C runtime library exit code on module unload */
+	    if ((TerminateLibC = (TerminateLibC_t)PE_getProcAddress(hModule,"_TerminateLibC")) != NULL)
+		TerminateLibC();
+	    if (hModule->shared)
+		PM_freeShared(hModule);
+	    else
+		PM_free(hModule);
+	    }
+	}
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns the error code for the last operation
+
+HEADER:
+peloader.h
+
+RETURNS:
+Error code for the last operation.
+
+SEE ALSO:
+PE_getProcAddress, PE_loadLibrary
+****************************************************************************/
+int PEAPI PE_getError(void)
+{
+    return result;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/common/vesavbe.c b/board/MAI/bios_emulator/scitech/src/common/vesavbe.c
new file mode 100755
index 0000000..a669e5c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/common/vesavbe.c
@@ -0,0 +1,1214 @@
+/****************************************************************************
+*
+*           The SuperVGA Kit - UniVBE Software Development Kit
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  IBM PC Real Mode and 16/32 bit Protected Mode.
+*
+* Description:  Module to implement a C callable interface to the standard
+*               VESA VBE routines. You should rip out this module and use it
+*               directly in your own applications, or you can use the
+*               high level SDK functions.
+*
+*               MUST be compiled in the LARGE or FLAT models.
+*
+****************************************************************************/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "vesavbe.h"
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+
+/*---------------------------- Global Variables ---------------------------*/
+
+#define VBE_SUCCESS     0x004F
+#define MAX_LIN_PTRS    10
+
+static uint         VESABuf_len = 1024;/* Length of the VESABuf buffer  */
+static ibool        haveRiva128;    /* True if we have a Riva128        */
+static VBE_state    defState = {0}; /* Default state buffer             */
+static VBE_state    *state = &defState; /* Pointer to current buffer    */
+static int          VBE_shared = 0;
+#ifndef REALMODE
+static char         localBuf[512];  /* Global PM string translate buf   */
+#define MAX_LOCAL_BUF &localBuf[511]
+#endif
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* static function in WinDirect for passing 32-bit registers to BIOS */
+int PMAPI WD_int386(int intno, RMREGS *in, RMREGS *out);
+
+void VBEAPI VBE_init(void)
+/****************************************************************************
+*
+* Function:     VBE_init
+*
+* Description:  Initialises the VBE transfer buffer in real mode DC.memory.
+*               This routine is called by the VESAVBE module every time
+*               it needs to use the transfer buffer, so we simply allocate
+*               it once and then return.
+*
+****************************************************************************/
+{
+    if (!state->VESABuf_ptr) {
+	/* Allocate a global buffer for communicating with the VESA VBE */
+	if ((state->VESABuf_ptr = PM_getVESABuf(&VESABuf_len, &state->VESABuf_rseg, &state->VESABuf_roff)) == NULL)
+	    PM_fatalError("VESAVBE.C: Real mode memory allocation failed!");
+	}
+}
+
+void * VBEAPI VBE_getRMBuf(uint *len,uint *rseg,uint *roff)
+/****************************************************************************
+*
+* Function:     VBE_getRMBuf
+*
+* Description:  This function returns the location and length of the real
+*               mode memory buffer for calling real mode functions.
+*
+****************************************************************************/
+{
+    *len = VESABuf_len;
+    *rseg = state->VESABuf_rseg;
+    *roff = state->VESABuf_roff;
+    return state->VESABuf_ptr;
+}
+
+void VBEAPI VBE_setStateBuffer(VBE_state *s)
+/****************************************************************************
+*
+* Function:     VBE_setStateBuffer
+*
+* Description:  This functions sets the internal state buffer for the
+*               VBE module to the passed in buffer. By default the internal
+*               global buffer is used, but you must use separate buffers
+*               for each device in a multi-controller environment.
+*
+****************************************************************************/
+{
+    state = s;
+}
+
+void VBEAPI VBE_callESDI(RMREGS *regs, void *buffer, int size)
+/****************************************************************************
+*
+* Function:     VBE_callESDI
+* Parameters:   regs    - Registers to load when calling VBE
+*               buffer  - Buffer to copy VBE info block to
+*               size    - Size of buffer to fill
+*
+* Description:  Calls the VESA VBE and passes in a buffer for the VBE to
+*               store information in, which is then copied into the users
+*               buffer space. This works in protected mode as the buffer
+*               passed to the VESA VBE is allocated in conventional
+*               memory, and is then copied into the users memory block.
+*
+****************************************************************************/
+{
+    RMSREGS sregs;
+
+    if (!state->VESABuf_ptr)
+	PM_fatalError("You *MUST* call VBE_init() before you can call the VESAVBE.C module!");
+    sregs.es = (ushort)state->VESABuf_rseg;
+    regs->x.di = (ushort)state->VESABuf_roff;
+    memcpy(state->VESABuf_ptr, buffer, size);
+    PM_int86x(0x10, regs, regs, &sregs);
+    memcpy(buffer, state->VESABuf_ptr, size);
+}
+
+#ifndef REALMODE
+static char *VBE_copyStrToLocal(char *p,char *realPtr,char *max)
+/****************************************************************************
+*
+* Function:     VBE_copyStrToLocal
+* Parameters:   p       - Flat model buffer to copy to
+*               realPtr - Real mode pointer to copy
+* Returns:      Pointer to the next byte after string
+*
+* Description:  Copies the string from the real mode location pointed to
+*               by 'realPtr' into the flat model buffer pointed to by
+*               'p'. We return a pointer to the next byte past the copied
+*               string.
+*
+****************************************************************************/
+{
+    uchar   *v;
+
+    v = PM_mapRealPointer((uint)((ulong)realPtr >> 16), (uint)((ulong)realPtr & 0xFFFF));
+    while (*v != 0 && p < max)
+	*p++ = *v++;
+    *p++ = 0;
+    return p;
+}
+
+static void VBE_copyShortToLocal(ushort *p,ushort *realPtr)
+/****************************************************************************
+*
+* Function:     VBE_copyShortToLocal
+* Parameters:   p       - Flat model buffer to copy to
+*               realPtr - Real mode pointer to copy
+*
+* Description:  Copies the mode table from real mode memory to the flat
+*               model buffer.
+*
+****************************************************************************/
+{
+    ushort  *v;
+
+    v = PM_mapRealPointer((uint)((ulong)realPtr >> 16),(uint)((ulong)realPtr & 0xFFFF));
+    while (*v != 0xFFFF)
+	*p++ = *v++;
+    *p = 0xFFFF;
+}
+#endif
+
+int VBEAPI VBE_detectEXT(VBE_vgaInfo *vgaInfo,ibool forceUniVBE)
+/****************************************************************************
+*
+* Function:     VBE_detect
+* Parameters:   vgaInfo - Place to store the VGA information block
+* Returns:      VBE version number, or 0 if not detected.
+*
+* Description:  Detects if a VESA VBE is out there and functioning
+*               correctly. If we detect a VBE interface we return the
+*               VGAInfoBlock returned by the VBE and the VBE version number.
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F00;     /* Get SuperVGA information */
+    if (forceUniVBE) {
+	regs.x.bx = 0x1234;
+	regs.x.cx = 0x4321;
+	}
+    else {
+	regs.x.bx = 0;
+	regs.x.cx = 0;
+	}
+    strncpy(vgaInfo->VESASignature,"VBE2",4);
+    VBE_callESDI(&regs, vgaInfo, sizeof(*vgaInfo));
+    if (regs.x.ax != VBE_SUCCESS)
+	return 0;
+    if (strncmp(vgaInfo->VESASignature,"VESA",4) != 0)
+	return 0;
+
+    /* Check for bogus BIOSes that return a VBE version number that is
+     * not correct, and fix it up. We also check the OemVendorNamePtr for a
+     * valid value, and if it is invalid then we also reset to VBE 1.2.
+     */
+    if (vgaInfo->VESAVersion >= 0x200 && vgaInfo->OemVendorNamePtr == 0)
+	vgaInfo->VESAVersion = 0x102;
+#ifndef REALMODE
+    /* Relocate all the indirect information (mode tables, OEM strings
+     * etc) from the low 1Mb memory region into a static buffer in
+     * our default data segment. We do this to insulate the application
+     * from mapping the strings from real mode to protected mode.
+     */
+    {
+	char *p,*p2;
+     p2 = VBE_copyStrToLocal(localBuf,vgaInfo->OemStringPtr,MAX_LOCAL_BUF);
+     vgaInfo->OemStringPtr = localBuf;
+     if (vgaInfo->VESAVersion >= 0x200) {
+	 p = VBE_copyStrToLocal(p2,vgaInfo->OemVendorNamePtr,MAX_LOCAL_BUF);
+	 vgaInfo->OemVendorNamePtr = p2;
+	 p2 = VBE_copyStrToLocal(p,vgaInfo->OemProductNamePtr,MAX_LOCAL_BUF);
+	 vgaInfo->OemProductNamePtr = p;
+	 p = VBE_copyStrToLocal(p2,vgaInfo->OemProductRevPtr,MAX_LOCAL_BUF);
+	 vgaInfo->OemProductRevPtr = p2;
+	 VBE_copyShortToLocal((ushort*)p,vgaInfo->VideoModePtr);
+	 vgaInfo->VideoModePtr = (ushort*)p;
+	 }
+     else {
+	 VBE_copyShortToLocal((ushort*)p2,vgaInfo->VideoModePtr);
+	 vgaInfo->VideoModePtr = (ushort*)p2;
+	 }
+    }
+#endif
+    state->VBEMemory = vgaInfo->TotalMemory * 64;
+
+    /* Check for Riva128 based cards since they have broken triple buffering
+     * and stereo support.
+     */
+    haveRiva128 = false;
+    if (vgaInfo->VESAVersion >= 0x300 &&
+	   (strstr(vgaInfo->OemStringPtr,"NVidia") != NULL ||
+	    strstr(vgaInfo->OemStringPtr,"Riva") != NULL)) {
+	haveRiva128 = true;
+	}
+
+    /* Check for Matrox G400 cards which claim to be VBE 3.0
+     * compliant yet they don't implement the refresh rate control
+     * functions.
+     */
+    if (vgaInfo->VESAVersion >= 0x300 && (strcmp(vgaInfo->OemProductNamePtr,"Matrox G400") == 0))
+	vgaInfo->VESAVersion = 0x200;
+    return (state->VBEVersion = vgaInfo->VESAVersion);
+}
+
+int VBEAPI VBE_detect(VBE_vgaInfo *vgaInfo)
+/****************************************************************************
+*
+* Function:     VBE_detect
+* Parameters:   vgaInfo - Place to store the VGA information block
+* Returns:      VBE version number, or 0 if not detected.
+*
+* Description:  Detects if a VESA VBE is out there and functioning
+*               correctly. If we detect a VBE interface we return the
+*               VGAInfoBlock returned by the VBE and the VBE version number.
+*
+****************************************************************************/
+{
+    return VBE_detectEXT(vgaInfo,false);
+}
+
+ibool VBEAPI VBE_getModeInfo(int mode,VBE_modeInfo *modeInfo)
+/****************************************************************************
+*
+* Function:     VBE_getModeInfo
+* Parameters:   mode        - VBE mode to get information for
+*               modeInfo    - Place to store VBE mode information
+* Returns:      True on success, false if function failed.
+*
+* Description:  Obtains information about a specific video mode from the
+*               VBE. You should use this function to find the video mode
+*               you wish to set, as the new VBE 2.0 mode numbers may be
+*               completely arbitrary.
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+    int     bits;
+
+    regs.x.ax = 0x4F01;             /* Get mode information         */
+    regs.x.cx = (ushort)mode;
+    VBE_callESDI(&regs, modeInfo, sizeof(*modeInfo));
+    if (regs.x.ax != VBE_SUCCESS)
+	return false;
+    if ((modeInfo->ModeAttributes & vbeMdAvailable) == 0)
+	return false;
+
+    /* Map out triple buffer and stereo flags for NVidia Riva128
+     * chips.
+     */
+    if (haveRiva128) {
+	modeInfo->ModeAttributes &= ~vbeMdTripleBuf;
+	modeInfo->ModeAttributes &= ~vbeMdStereo;
+	}
+
+    /* Support old style RGB definitions for VBE 1.1 BIOSes */
+    bits = modeInfo->BitsPerPixel;
+    if (modeInfo->MemoryModel == vbeMemPK && bits > 8) {
+	modeInfo->MemoryModel = vbeMemRGB;
+	switch (bits) {
+	    case 15:
+		modeInfo->RedMaskSize = 5;
+		modeInfo->RedFieldPosition = 10;
+		modeInfo->GreenMaskSize = 5;
+		modeInfo->GreenFieldPosition = 5;
+		modeInfo->BlueMaskSize = 5;
+		modeInfo->BlueFieldPosition = 0;
+		modeInfo->RsvdMaskSize = 1;
+		modeInfo->RsvdFieldPosition = 15;
+		break;
+	    case 16:
+		modeInfo->RedMaskSize = 5;
+		modeInfo->RedFieldPosition = 11;
+		modeInfo->GreenMaskSize = 5;
+		modeInfo->GreenFieldPosition = 5;
+		modeInfo->BlueMaskSize = 5;
+		modeInfo->BlueFieldPosition = 0;
+		modeInfo->RsvdMaskSize = 0;
+		modeInfo->RsvdFieldPosition = 0;
+		break;
+	    case 24:
+		modeInfo->RedMaskSize = 8;
+		modeInfo->RedFieldPosition = 16;
+		modeInfo->GreenMaskSize = 8;
+		modeInfo->GreenFieldPosition = 8;
+		modeInfo->BlueMaskSize = 8;
+		modeInfo->BlueFieldPosition = 0;
+		modeInfo->RsvdMaskSize = 0;
+		modeInfo->RsvdFieldPosition = 0;
+		break;
+	    }
+	}
+
+    /* Convert the 32k direct color modes of VBE 1.2+ BIOSes to
+     * be recognised as 15 bits per pixel modes.
+     */
+    if (bits == 16 && modeInfo->RsvdMaskSize == 1)
+	modeInfo->BitsPerPixel = 15;
+
+    /* Fix up bogus BIOS'es that report incorrect reserved pixel masks
+     * for 32K color modes. Quite a number of BIOS'es have this problem,
+     * and this affects our OS/2 drivers in VBE fallback mode.
+     */
+    if (bits == 15 && (modeInfo->RsvdMaskSize != 1 || modeInfo->RsvdFieldPosition != 15)) {
+	modeInfo->RsvdMaskSize = 1;
+	modeInfo->RsvdFieldPosition = 15;
+	}
+    return true;
+}
+
+long VBEAPI VBE_getPageSize(VBE_modeInfo *mi)
+/****************************************************************************
+*
+* Function:     VBE_getPageSize
+* Parameters:   mi  - Pointer to mode information block
+* Returns:      Caculated page size in bytes rounded to correct boundary
+*
+* Description:  Computes the page size in bytes for the specified mode
+*               information block, rounded up to the appropriate boundary
+*               (8k, 16k, 32k or 64k). Pages >= 64k in size are always
+*               rounded to the nearest 64k boundary (so the start of a
+*               page is always bank aligned).
+*
+****************************************************************************/
+{
+    long size;
+
+    size = (long)mi->BytesPerScanLine * (long)mi->YResolution;
+    if (mi->BitsPerPixel == 4) {
+	/* We have a 16 color video mode, so round up the page size to
+	 * 8k, 16k, 32k or 64k boundaries depending on how large it is.
+	 */
+
+	size = (size + 0x1FFFL) & 0xFFFFE000L;
+	if (size != 0x2000) {
+	    size = (size + 0x3FFFL) & 0xFFFFC000L;
+	    if (size != 0x4000) {
+		size = (size + 0x7FFFL) & 0xFFFF8000L;
+		if (size != 0x8000)
+		    size = (size + 0xFFFFL) & 0xFFFF0000L;
+		}
+	    }
+	}
+    else size = (size + 0xFFFFL) & 0xFFFF0000L;
+    return size;
+}
+
+ibool VBEAPI VBE_setVideoModeExt(int mode,VBE_CRTCInfo *crtc)
+/****************************************************************************
+*
+* Function:     VBE_setVideoModeExt
+* Parameters:   mode    - SuperVGA video mode to set.
+* Returns:      True if the mode was set, false if not.
+*
+* Description:  Attempts to set the specified video mode. This version
+*               includes support for the VBE/Core 3.0 refresh rate control
+*               mechanism.
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    if (state->VBEVersion < 0x200 && mode < 0x100) {
+	/* Some VBE implementations barf terribly if you try to set non-VBE
+	 * video modes with the VBE set mode call. VBE 2.0 implementations
+	 * must be able to handle this.
+	 */
+	regs.h.al = (ushort)mode;
+	regs.h.ah = 0;
+	PM_int86(0x10,&regs,&regs);
+	}
+    else {
+	if (state->VBEVersion < 0x300 && (mode & vbeRefreshCtrl))
+	    return false;
+	regs.x.ax = 0x4F02;
+	regs.x.bx = (ushort)mode;
+	if ((mode & vbeRefreshCtrl) && crtc)
+	    VBE_callESDI(&regs, crtc, sizeof(*crtc));
+	else
+	    PM_int86(0x10,&regs,&regs);
+	if (regs.x.ax != VBE_SUCCESS)
+	    return false;
+	}
+    return true;
+}
+
+ibool VBEAPI VBE_setVideoMode(int mode)
+/****************************************************************************
+*
+* Function:     VBE_setVideoMode
+* Parameters:   mode    - SuperVGA video mode to set.
+* Returns:      True if the mode was set, false if not.
+*
+* Description:  Attempts to set the specified video mode.
+*
+****************************************************************************/
+{
+    return VBE_setVideoModeExt(mode,NULL);
+}
+
+int VBEAPI VBE_getVideoMode(void)
+/****************************************************************************
+*
+* Function:     VBE_getVideoMode
+* Returns:      Current video mode
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F03;
+    PM_int86(0x10,&regs,&regs);
+    if (regs.x.ax != VBE_SUCCESS)
+	return -1;
+    return regs.x.bx;
+}
+
+ibool VBEAPI VBE_setBank(int window,int bank)
+/****************************************************************************
+*
+* Function:     VBE_setBank
+* Parameters:   window  - Window to set
+*               bank    - Bank number to set window to
+* Returns:      True on success, false on failure.
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F05;
+    regs.h.bh = 0;
+    regs.h.bl = window;
+    regs.x.dx = bank;
+    PM_int86(0x10,&regs,&regs);
+    return regs.x.ax == VBE_SUCCESS;
+}
+
+int VBEAPI VBE_getBank(int window)
+/****************************************************************************
+*
+* Function:     VBE_setBank
+* Parameters:   window  - Window to read
+* Returns:      Bank number for the window (-1 on failure)
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F05;
+    regs.h.bh = 1;
+    regs.h.bl = window;
+    PM_int86(0x10,&regs,&regs);
+    if (regs.x.ax != VBE_SUCCESS)
+	return -1;
+    return regs.x.dx;
+}
+
+ibool VBEAPI VBE_setPixelsPerLine(int pixelsPerLine,int *newBytes,
+    int *newPixels,int *maxScanlines)
+/****************************************************************************
+*
+* Function:     VBE_setPixelsPerLine
+* Parameters:   pixelsPerLine   - Pixels per scanline
+*               newBytes        - Storage for bytes per line value set
+*               newPixels       - Storage for pixels per line value set
+*               maxScanLines    - Storage for maximum number of scanlines
+* Returns:      True on success, false on failure
+*
+* Description:  Sets the scanline length for the video mode to the specified
+*               number of pixels per scanline. If you need more granularity
+*               in TrueColor modes, use the VBE_setBytesPerLine routine
+*               (only valid for VBE 2.0).
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F06;
+    regs.h.bl = 0;
+    regs.x.cx = pixelsPerLine;
+    PM_int86(0x10,&regs,&regs);
+    *newBytes = regs.x.bx;
+    *newPixels = regs.x.cx;
+    *maxScanlines = regs.x.dx;
+    return regs.x.ax == VBE_SUCCESS;
+}
+
+ibool VBEAPI VBE_setBytesPerLine(int bytesPerLine,int *newBytes,
+    int *newPixels,int *maxScanlines)
+/****************************************************************************
+*
+* Function:     VBE_setBytesPerLine
+* Parameters:   pixelsPerLine   - Pixels per scanline
+*               newBytes        - Storage for bytes per line value set
+*               newPixels       - Storage for pixels per line value set
+*               maxScanLines    - Storage for maximum number of scanlines
+* Returns:      True on success, false on failure
+*
+* Description:  Sets the scanline length for the video mode to the specified
+*               number of bytes per scanline (valid for VBE 2.0 only).
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F06;
+    regs.h.bl = 2;
+    regs.x.cx = bytesPerLine;
+    PM_int86(0x10,&regs,&regs);
+    *newBytes = regs.x.bx;
+    *newPixels = regs.x.cx;
+    *maxScanlines = regs.x.dx;
+    return regs.x.ax == VBE_SUCCESS;
+}
+
+ibool VBEAPI VBE_getScanlineLength(int *bytesPerLine,int *pixelsPerLine,
+    int *maxScanlines)
+/****************************************************************************
+*
+* Function:     VBE_getScanlineLength
+* Parameters:   bytesPerLine    - Storage for bytes per scanline
+*               pixelsPerLine   - Storage for pixels per scanline
+*               maxScanLines    - Storage for maximum number of scanlines
+* Returns:      True on success, false on failure
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F06;
+    regs.h.bl = 1;
+    PM_int86(0x10,&regs,&regs);
+    *bytesPerLine = regs.x.bx;
+    *pixelsPerLine = regs.x.cx;
+    *maxScanlines = regs.x.dx;
+    return regs.x.ax == VBE_SUCCESS;
+}
+
+ibool VBEAPI VBE_getMaxScanlineLength(int *maxBytes,int *maxPixels)
+/****************************************************************************
+*
+* Function:     VBE_getMaxScanlineLength
+* Parameters:   maxBytes    - Maximum scanline width in bytes
+*               maxPixels   - Maximum scanline width in pixels
+* Returns:      True if successful, false if function failed
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F06;
+    regs.h.bl = 3;
+    PM_int86(0x10,&regs,&regs);
+    *maxBytes = regs.x.bx;
+    *maxPixels = regs.x.cx;
+    return regs.x.ax == VBE_SUCCESS;
+}
+
+ibool VBEAPI VBE_setDisplayStart(int x,int y,ibool waitVRT)
+/****************************************************************************
+*
+* Function:     VBE_setDisplayStart
+* Parameters:   x,y     - Position of the first pixel to display
+*               waitVRT - True to wait for retrace, false if not
+* Returns:      True if function was successful.
+*
+* Description:  Sets the new starting display position to implement
+*               hardware scrolling.
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F07;
+    if (waitVRT)
+	regs.x.bx = 0x80;
+    else regs.x.bx = 0x00;
+    regs.x.cx = x;
+    regs.x.dx = y;
+    PM_int86(0x10,&regs,&regs);
+    return regs.x.ax == VBE_SUCCESS;
+}
+
+ibool VBEAPI VBE_getDisplayStart(int *x,int *y)
+/****************************************************************************
+*
+* Function:     VBE_getDisplayStart
+* Parameters:   x,y - Place to store starting address value
+* Returns:      True if function was successful.
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F07;
+    regs.x.bx = 0x01;
+    PM_int86(0x10,&regs,&regs);
+    *x = regs.x.cx;
+    *y = regs.x.dx;
+    return regs.x.ax == VBE_SUCCESS;
+}
+
+ibool VBEAPI VBE_setDisplayStartAlt(ulong startAddr,ibool waitVRT)
+/****************************************************************************
+*
+* Function:     VBE_setDisplayStartAlt
+* Parameters:   startAddr   - 32-bit starting address in display memory
+*               waitVRT     - True to wait for vertical retrace, false if not
+* Returns:      True if function was successful, false if not supported.
+*
+* Description:  Sets the new starting display position to the specified
+*               32-bit display start address. Note that this function is
+*               different the the version above, since it takes a 32-bit
+*               byte offset in video memory as the starting address which
+*               gives the programmer maximum control over the stat address.
+*
+*               NOTE: Requires VBE/Core 3.0
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    if (state->VBEVersion >= 0x300) {
+	regs.x.ax = 0x4F07;
+	regs.x.bx = waitVRT ? 0x82 : 0x02;
+	regs.e.ecx = startAddr;
+	PM_int86(0x10,&regs,&regs);
+	return regs.x.ax == VBE_SUCCESS;
+	}
+    return false;
+}
+
+int VBEAPI VBE_getDisplayStartStatus(void)
+/****************************************************************************
+*
+* Function:     VBE_getDisplayStartStatus
+* Returns:      0 if last flip not occurred, 1 if already flipped
+*               -1 if not supported
+*
+* Description:  Returns the status of the previous display start request.
+*               If this function is supported the programmer can implement
+*               hardware triple buffering using this function.
+*
+*               NOTE: Requires VBE/Core 3.0
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    if (state->VBEVersion >= 0x300) {
+	regs.x.ax = 0x4F07;
+	regs.x.bx = 0x0004;
+	PM_int86(0x10,&regs,&regs);
+	if (regs.x.ax == VBE_SUCCESS)
+	    return (regs.x.cx != 0);
+	}
+    return -1;
+}
+
+ibool VBEAPI VBE_enableStereoMode(void)
+/****************************************************************************
+*
+* Function:     VBE_enableStereoMode
+* Returns:      True if stereo mode enabled, false if not supported.
+*
+* Description:  Puts the system into hardware stereo mode for LC shutter
+*               glasses, where the display swaps between two display start
+*               addresses every vertical retrace.
+*
+*               NOTE: Requires VBE/Core 3.0
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    if (state->VBEVersion >= 0x300) {
+	regs.x.ax = 0x4F07;
+	regs.x.bx = 0x0005;
+	PM_int86(0x10,&regs,&regs);
+	return regs.x.ax == VBE_SUCCESS;
+	}
+    return false;
+}
+
+ibool VBEAPI VBE_disableStereoMode(void)
+/****************************************************************************
+*
+* Function:     VBE_disableStereoMode
+* Returns:      True if stereo mode disabled, false if not supported.
+*
+* Description:  Puts the system back into normal, non-stereo display mode
+*               after having stereo mode enabled.
+*
+*               NOTE: Requires VBE/Core 3.0
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    if (state->VBEVersion >= 0x300) {
+	regs.x.ax = 0x4F07;
+	regs.x.bx = 0x0006;
+	PM_int86(0x10,&regs,&regs);
+	return regs.x.ax == VBE_SUCCESS;
+	}
+    return false;
+}
+
+ibool VBEAPI VBE_setStereoDisplayStart(ulong leftAddr,ulong rightAddr,
+    ibool waitVRT)
+/****************************************************************************
+*
+* Function:     VBE_setStereoDisplayStart
+* Parameters:   leftAddr    - 32-bit start address for left image
+*               rightAddr   - 32-bit start address for right image
+*               waitVRT     - True to wait for vertical retrace, false if not
+* Returns:      True if function was successful, false if not supported.
+*
+* Description:  Sets the new starting display position to the specified
+*               32-bit display start address. Note that this function is
+*               different the the version above, since it takes a 32-bit
+*               byte offset in video memory as the starting address which
+*               gives the programmer maximum control over the stat address.
+*
+*               NOTE: Requires VBE/Core 3.0
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    if (state->VBEVersion >= 0x300) {
+	regs.x.ax = 0x4F07;
+	regs.x.bx = waitVRT ? 0x83 : 0x03;
+	regs.e.ecx = leftAddr;
+	regs.e.edx = rightAddr;
+	PM_int86(0x10,&regs,&regs);
+	return regs.x.ax == VBE_SUCCESS;
+	}
+    return false;
+}
+
+ulong VBEAPI VBE_getClosestClock(ushort mode,ulong pixelClock)
+/****************************************************************************
+*
+* Function:     VBE_getClosestClock
+* Parameters:   mode        - VBE mode to be used (include vbeLinearBuffer)
+*               pixelClock  - Desired pixel clock
+* Returns:      Closest pixel clock to desired clock (-1 if not supported)
+*
+* Description:  Calls the VBE/Core 3.0 interface to determine the closest
+*               pixel clock to the requested value. The BIOS will always
+*               search for a pixel clock that is no more than 1% below the
+*               requested clock or somewhere higher than the clock. If the
+*               clock is higher note that it may well be many Mhz higher
+*               that requested and the application will have to check that
+*               the returned value is suitable for it's needs. This function
+*               returns the actual pixel clock that will be programmed by
+*               the hardware.
+*
+*               Note that if the pixel clock will be used with a linear
+*               framebuffer mode, make sure you pass in the linear
+*               framebuffer flag to this function.
+*
+*               NOTE: Requires VBE/Core 3.0
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    if (state->VBEVersion >= 0x300) {
+	regs.x.ax = 0x4F0B;
+	regs.h.bl = 0x00;
+	regs.e.ecx = pixelClock;
+	regs.x.dx = mode;
+	PM_int86(0x10,&regs,&regs);
+	if (regs.x.ax == VBE_SUCCESS)
+	    return regs.e.ecx;
+	}
+    return -1;
+}
+
+ibool VBEAPI VBE_setDACWidth(int width)
+/****************************************************************************
+*
+* Function:     VBE_setDACWidth
+* Parameters:   width   - Width to set the DAC to
+* Returns:      True on success, false on failure
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F08;
+    regs.h.bl = 0x00;
+    regs.h.bh = width;
+    PM_int86(0x10,&regs,&regs);
+    return regs.x.ax == VBE_SUCCESS;
+}
+
+int VBEAPI VBE_getDACWidth(void)
+/****************************************************************************
+*
+* Function:     VBE_getDACWidth
+* Returns:      Current width of the palette DAC
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F08;
+    regs.h.bl = 0x01;
+    PM_int86(0x10,&regs,&regs);
+    if (regs.x.ax != VBE_SUCCESS)
+	return -1;
+    return regs.h.bh;
+}
+
+ibool VBEAPI VBE_setPalette(int start,int num,VBE_palette *pal,ibool waitVRT)
+/****************************************************************************
+*
+* Function:     VBE_setPalette
+* Parameters:   start   - Starting palette index to program
+*               num     - Number of palette indexes to program
+*               pal     - Palette buffer containing values
+*               waitVRT - Wait for vertical retrace flag
+* Returns:      True on success, false on failure
+*
+* Description:  Sets a block of palette registers by calling the VBE 2.0
+*               BIOS. This function will fail on VBE 1.2 implementations.
+*
+****************************************************************************/
+{
+    RMREGS  regs;
+
+    regs.x.ax = 0x4F09;
+    regs.h.bl = waitVRT ? 0x80 : 0x00;
+    regs.x.cx = num;
+    regs.x.dx = start;
+    VBE_callESDI(&regs, pal, sizeof(VBE_palette) * num);
+    return regs.x.ax == VBE_SUCCESS;
+}
+
+void * VBEAPI VBE_getBankedPointer(VBE_modeInfo *modeInfo)
+/****************************************************************************
+*
+* Function:     VBE_getBankedPointer
+* Parameters:   modeInfo    - Mode info block for video mode
+* Returns:      Selector to the linear framebuffer (0 on failure)
+*
+* Description:  Returns a near pointer to the VGA framebuffer area.
+*
+****************************************************************************/
+{
+    /* We just map the pointer every time, since the pointer will always
+     * be in real mode memory, so we wont actually be mapping any real
+     * memory.
+     *
+     * NOTE: We cannot currently map a near pointer to the banked frame
+     *       buffer for Watcom Win386, so we create a 16:16 far pointer to
+     *       the video memory. All the assembler code will render to the
+     *       video memory by loading the selector rather than using a
+     *       near pointer.
+     */
+    ulong seg = (ushort)modeInfo->WinASegment;
+    if (seg != 0) {
+	if (seg == 0xA000)
+	    return (void*)PM_getA0000Pointer();
+	else
+	    return (void*)PM_mapPhysicalAddr(seg << 4,0xFFFF,true);
+	}
+    return NULL;
+}
+
+#ifndef REALMODE
+
+void * VBEAPI VBE_getLinearPointer(VBE_modeInfo *modeInfo)
+/****************************************************************************
+*
+* Function:     VBE_getLinearPointer
+* Parameters:   modeInfo    - Mode info block for video mode
+* Returns:      Selector to the linear framebuffer (0 on failure)
+*
+* Description:  Returns a near pointer to the linear framebuffer for the video
+*               mode.
+*
+****************************************************************************/
+{
+    static ulong physPtr[MAX_LIN_PTRS] = {0};
+    static void *linPtr[MAX_LIN_PTRS] = {0};
+    static int numPtrs = 0;
+    int i;
+
+    /* Search for an already mapped pointer */
+    for (i = 0; i < numPtrs; i++) {
+	if (physPtr[i] == modeInfo->PhysBasePtr)
+	    return linPtr[i];
+	}
+    if (numPtrs < MAX_LIN_PTRS) {
+	physPtr[numPtrs] = modeInfo->PhysBasePtr;
+	linPtr[numPtrs] = PM_mapPhysicalAddr(modeInfo->PhysBasePtr,(state->VBEMemory * 1024L)-1,true);
+	return linPtr[numPtrs++];
+	}
+    return NULL;
+}
+
+static void InitPMCode(void)
+/****************************************************************************
+*
+* Function:     InitPMCode  - 32 bit protected mode version
+*
+* Description:  Finds the address of and relocates the protected mode
+*               code block from the VBE 2.0 into a local memory block. The
+*               memory block is allocated with malloc() and must be freed
+*               with VBE_freePMCode() after graphics processing is complete.
+*
+*               Note that this buffer _must_ be recopied after each mode set,
+*               as the routines will change depending on the underlying
+*               video mode.
+*
+****************************************************************************/
+{
+    RMREGS      regs;
+    RMSREGS     sregs;
+    uchar       *code;
+    int         pmLen;
+
+    if (!state->pmInfo && state->VBEVersion >= 0x200) {
+	regs.x.ax = 0x4F0A;
+	regs.x.bx = 0;
+	PM_int86x(0x10,&regs,&regs,&sregs);
+	if (regs.x.ax != VBE_SUCCESS)
+	    return;
+	if (VBE_shared)
+	    state->pmInfo = PM_mallocShared(regs.x.cx);
+	else
+	    state->pmInfo = PM_malloc(regs.x.cx);
+	if (state->pmInfo == NULL)
+	    return;
+	state->pmInfo32 = state->pmInfo;
+	pmLen = regs.x.cx;
+
+	/* Relocate the block into our local data segment */
+	code = PM_mapRealPointer(sregs.es,regs.x.di);
+	memcpy(state->pmInfo,code,pmLen);
+
+	/* Now do a sanity check on the information we recieve to ensure
+	 * that is is correct. Some BIOS return totally bogus information
+	 * in here (Matrox is one)! Under DOS this works OK, but under OS/2
+	 * we are screwed.
+	 */
+	if (state->pmInfo->setWindow >= pmLen ||
+	    state->pmInfo->setDisplayStart >= pmLen ||
+	    state->pmInfo->setPalette >= pmLen ||
+	    state->pmInfo->IOPrivInfo >= pmLen) {
+	    if (VBE_shared)
+		PM_freeShared(state->pmInfo);
+	    else
+		PM_free(state->pmInfo);
+	    state->pmInfo32 = state->pmInfo = NULL;
+	    return;
+	    }
+
+	/* Read the IO priveledge info and determine if we need to
+	 * pass a selector to MMIO registers to the bank switch code.
+	 * Since we no longer support selector allocation, we no longer
+	 * support this mechanism so we disable the protected mode
+	 * interface in this case.
+	 */
+	if (state->pmInfo->IOPrivInfo && !state->MMIOSel) {
+	    ushort *p = (ushort*)((uchar*)state->pmInfo + state->pmInfo->IOPrivInfo);
+	    while (*p != 0xFFFF)
+		p++;
+	    p++;
+	    if (*p != 0xFFFF)
+		VBE_freePMCode();
+	    }
+	}
+}
+
+void * VBEAPI VBE_getSetBank(void)
+/****************************************************************************
+*
+* Function:     VBE_getSetBank
+* Returns:      Pointer to the 32 VBE 2.0 bit bank switching routine.
+*
+****************************************************************************/
+{
+    if (state->VBEVersion >= 0x200) {
+	InitPMCode();
+	if (state->pmInfo)
+	    return (uchar*)state->pmInfo + state->pmInfo->setWindow;
+	}
+    return NULL;
+}
+
+void * VBEAPI VBE_getSetDisplayStart(void)
+/****************************************************************************
+*
+* Function:     VBE_getSetDisplayStart
+* Returns:      Pointer to the 32 VBE 2.0 bit CRT start address routine.
+*
+****************************************************************************/
+{
+    if (state->VBEVersion >= 0x200) {
+	InitPMCode();
+	if (state->pmInfo)
+	    return (uchar*)state->pmInfo + state->pmInfo->setDisplayStart;
+	}
+    return NULL;
+}
+
+void * VBEAPI VBE_getSetPalette(void)
+/****************************************************************************
+*
+* Function:     VBE_getSetPalette
+* Returns:      Pointer to the 32 VBE 2.0 bit palette programming routine.
+*
+****************************************************************************/
+{
+    if (state->VBEVersion >= 0x200) {
+	InitPMCode();
+	if (state->pmInfo)
+	    return (uchar*)state->pmInfo + state->pmInfo->setPalette;
+	}
+    return NULL;
+}
+
+void VBEAPI VBE_freePMCode(void)
+/****************************************************************************
+*
+* Function:     VBE_freePMCode
+*
+* Description:  This routine frees the protected mode code blocks that
+*               we copied from the VBE 2.0 interface. This routine must
+*               be after you have finished graphics processing to free up
+*               the memory occupied by the routines. This is necessary
+*               because the PM info memory block must be re-copied after
+*               every video mode set from the VBE 2.0 implementation.
+*
+****************************************************************************/
+{
+    if (state->pmInfo) {
+	if (VBE_shared)
+	    PM_freeShared(state->pmInfo);
+	else
+	    PM_free(state->pmInfo);
+	state->pmInfo = NULL;
+	state->pmInfo32 = NULL;
+	}
+}
+
+void VBEAPI VBE_sharePMCode(void)
+/****************************************************************************
+*
+* Function:     VBE_sharePMCode
+*
+* Description:  Enables internal sharing of the PM code buffer for OS/2.
+*
+****************************************************************************/
+{
+    VBE_shared = true;
+}
+
+/* Set of code stubs used to build the final bank switch code */
+
+#define VBE20_adjustOffset  7
+
+static uchar VBE20A_bankFunc32_Start[] = {
+    0x53,0x51,                  /*  push    ebx,ecx     */
+    0x8B,0xD0,                  /*  mov     edx,eax     */
+    0x33,0xDB,                  /*  xor     ebx,ebx     */
+    0xB1,0x00,                  /*  mov     cl,0        */
+    0xD2,0xE2,                  /*  shl     dl,cl       */
+    };
+
+static uchar VBE20_bankFunc32_End[] = {
+    0x59,0x5B,                  /*  pop     ecx,ebx     */
+    };
+
+static uchar bankFunc32[100];
+
+#define copy(p,b,a) memcpy(b,a,sizeof(a)); (p) = (b) + sizeof(a)
+
+ibool VBEAPI VBE_getBankFunc32(int *codeLen,void **bankFunc,int dualBanks,
+    int bankAdjust)
+/****************************************************************************
+*
+* Function:     VBE_getBankFunc32
+* Parameters:   codeLen     - Place to store length of code
+*               bankFunc    - Place to store pointer to bank switch code
+*               dualBanks   - True if dual banks are in effect
+*               bankAdjust  - Bank shift adjustment factor
+* Returns:      True on success, false if not compatible.
+*
+* Description:  Creates a local 32 bit bank switch function from the
+*               VBE 2.0 bank switch code that is compatible with the
+*               virtual flat framebuffer devices (does not have a return
+*               instruction at the end and takes the bank number in EAX
+*               not EDX). Note that this 32 bit code cannot include int 10h
+*               instructions, so we can only do this if we have VBE 2.0
+*               or later.
+*
+*               Note that we need to know the length of the 32 bit
+*               bank switch function, which the standard VBE 2.0 spec
+*               does not provide. In order to support this we have
+*               extended the VBE 2.0 state->pmInfo structure in UniVBE 5.2 in a
+*               way to support this, and we hope that this will become
+*               a VBE 2.0 ammendment.
+*
+*               Note also that we cannot run the linear framebuffer
+*               emulation code with bank switching routines that require
+*               a selector to the memory mapped registers passed in ES.
+*
+****************************************************************************/
+{
+    int     len;
+    uchar   *code;
+    uchar   *p;
+
+    InitPMCode();
+    if (state->VBEVersion >= 0x200 && state->pmInfo32 && !state->MMIOSel) {
+	code = (uchar*)state->pmInfo32 + state->pmInfo32->setWindow;
+	if (state->pmInfo32->extensionSig == VBE20_EXT_SIG)
+	    len = state->pmInfo32->setWindowLen-1;
+	else {
+	    /* We are running on a system without the UniVBE 5.2 extension.
+	     * We do as best we can by scanning through the code for the
+	     * ret function to determine the length. This is not foolproof,
+	     * but is the best we can do.
+	     */
+	    p = code;
+	    while (*p != 0xC3)
+		p++;
+	    len = p - code;
+	    }
+	if ((len + sizeof(VBE20A_bankFunc32_Start) + sizeof(VBE20_bankFunc32_End)) > sizeof(bankFunc32))
+	    PM_fatalError("32-bit bank switch function too long!");
+	copy(p,bankFunc32,VBE20A_bankFunc32_Start);
+	memcpy(p,code,len);
+	p += len;
+	copy(p,p,VBE20_bankFunc32_End);
+	*codeLen = p - bankFunc32;
+	bankFunc32[VBE20_adjustOffset] = (uchar)bankAdjust;
+	*bankFunc = bankFunc32;
+	return true;
+	}
+    return false;
+}
+
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c
new file mode 100755
index 0000000..cb3afe2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c
@@ -0,0 +1,80 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE ***
+*
+* Description:  Module to implement OS specific services to measure the
+*               CPU frequency.
+*
+****************************************************************************/
+
+#include <OS.h>
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Increase the thread priority to maximum, if possible.
+****************************************************************************/
+static int SetMaxThreadPriority(void)
+{
+    thread_id thid = find_thread(NULL);
+    thread_info tinfo;
+    get_thread_info(thid, &tinfo);
+    set_thread_priority(thid, B_REAL_TIME_PRIORITY);
+    return tinfo.priority;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the original thread priority.
+****************************************************************************/
+static void RestoreThreadPriority(
+    int priority)
+{
+    thread_id thid = find_thread(NULL);
+    set_thread_priority(thid, priority);
+}
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    /* TODO: Return the frequency of the counter in here. You should try to */
+    /*       normalise this value to be around 100,000 ticks per second. */
+    freq->low = 1000000;
+    freq->high = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+
+TODO: Implement this to read the counter. It should be done as a macro
+      for accuracy.
+****************************************************************************/
+#define GetCounter(t) { *((bigtime_t*) t) = system_time(); }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/event.c b/board/MAI/bios_emulator/scitech/src/pm/beos/event.c
new file mode 100755
index 0000000..93c6c0a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/beos/event.c
@@ -0,0 +1,199 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  BeOS
+*
+* Description:  BeOS implementation for the SciTech cross platform
+*               event library.
+*
+****************************************************************************/
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static ushort       keyUpMsg[256] = {0};/* Table of key up messages     */
+static int          rangeX,rangeY;      /* Range of mouse coordinates   */
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* These are not used under non-DOS systems */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flags)
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Scan code to test
+
+REMARKS:
+This macro determines if a specified key is currently down at the
+time that the call is made.
+****************************************************************************/
+#define _EVT_isKeyDown(scanCode)    (keyUpMsg[scanCode] != 0)
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{
+    /* TODO: Implement this for your OS! */
+}
+
+/****************************************************************************
+REMARKS:
+Pumps all messages in the application message queue into our event queue.
+****************************************************************************/
+static void _EVT_pumpMessages(void)
+{
+    /* TODO: The purpose of this function is to read all keyboard and mouse */
+    /*       events from the OS specific event queue, translate them and post */
+    /*       them into the SciTech event queue. */
+    /* */
+    /* NOTE: There are a couple of important things that this function must */
+    /*       take care of: */
+    /* */
+    /*  1. Support for KEYDOWN, KEYREPEAT and KEYUP is required. */
+    /* */
+    /*  2. Support for reading hardware scan code as well as ASCII */
+    /*     translated values is required. Games use the scan codes rather */
+    /*     than ASCII values. Scan codes go into the high order byte of the */
+    /*     keyboard message field. */
+    /* */
+    /*  3. Support for at least reading mouse motion data (mickeys) from the */
+    /*     mouse is required. Using the mickey values, we can then translate */
+    /*     to mouse cursor coordinates scaled to the range of the current */
+    /*     graphics display mode. Mouse values are scaled based on the */
+    /*     global 'rangeX' and 'rangeY'. */
+    /* */
+    /*  4. Support for a timestamp for the events is required, which is */
+    /*     defined as the number of milliseconds since some event (usually */
+    /*     system startup). This is the timestamp when the event occurred */
+    /*     (ie: at interrupt time) not when it was stuff into the SciTech */
+    /*     event queue. */
+    /* */
+    /*  5. Support for mouse double click events. If the OS has a native */
+    /*     mechanism to determine this, it should be used. Otherwise the */
+    /*     time stamp information will be used by the generic event code */
+    /*     to generate double click events. */
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort()
+{
+    EVT_exit();
+    PM_fatalError("Unhandled exception!");
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    /* Initialise the event queue */
+    _mouseMove = mouseMove;
+    initEventQueue();
+    memset(keyUpMsg,0,sizeof(keyUpMsg));
+
+    /* TODO: Do any OS specific initialisation here */
+
+    /* Catch program termination signals so we can clean up properly */
+    signal(SIGABRT, _EVT_abort);
+    signal(SIGFPE, _EVT_abort);
+    signal(SIGINT, _EVT_abort);
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    rangeX = xRes;
+    rangeY = yRes;
+}
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for non DOS systems */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for non DOS systems */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+    /* Restore signal handlers */
+    signal(SIGABRT, SIG_DFL);
+    signal(SIGFPE, SIG_DFL);
+    signal(SIGINT, SIG_DFL);
+
+    /* TODO: Do any OS specific cleanup in here */
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h
new file mode 100755
index 0000000..043d73e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h
@@ -0,0 +1,32 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  BeOS
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+/* This is where you include OS specific headers for the event handling */
+/* library. */
diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c b/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c
new file mode 100755
index 0000000..2dcb1b8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c
@@ -0,0 +1,539 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  BeOS
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/* TODO: Include any BeOS specific headers here! */
+
+/*--------------------------- Global variables ----------------------------*/
+
+static void (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+void PMAPI PM_init(void)
+{
+    /* TODO: Do any initialisation in here. This includes getting IOPL */
+    /*       access for the process calling PM_init. This will get called */
+    /*       more than once. */
+
+    /* TODO: If you support the supplied MTRR register stuff (you need to */
+    /*       be at ring 0 for this!), you should initialise it in here. */
+
+/* MTRR_init(); */
+}
+
+long PMAPI PM_getOSType(void)
+{ return _OS_BEOS; }
+
+int PMAPI PM_getModeType(void)
+{ return PM_386; }
+
+void PMAPI PM_backslash(char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '/') {
+	s[pos] = '/';
+	s[pos+1] = '\0';
+	}
+}
+
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+void PMAPI PM_fatalError(const char *msg)
+{
+    /* TODO: If you are running in a GUI environment without a console, */
+    /*       this needs to be changed to bring up a fatal error message */
+    /*       box and terminate the program. */
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+    fprintf(stderr,"%s\n", msg);
+    exit(1);
+}
+
+void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff)
+{
+    /* No BIOS access for the BeOS */
+    return NULL;
+}
+
+int PMAPI PM_kbhit(void)
+{
+    /* TODO: This function checks if a key is available to be read. This */
+    /*       should be implemented, but is mostly used by the test programs */
+    /*       these days. */
+    return true;
+}
+
+int PMAPI PM_getch(void)
+{
+    /* TODO: This returns the ASCII code of the key pressed. This */
+    /*       should be implemented, but is mostly used by the test programs */
+    /*       these days. */
+    return 0xD;
+}
+
+int PMAPI PM_openConsole(void)
+{
+    /* TODO: Opens up a fullscreen console for graphics output. If your */
+    /*       console does not have graphics/text modes, this can be left */
+    /*       empty. The main purpose of this is to disable console switching */
+    /*       when in graphics modes if you can switch away from fullscreen */
+    /*       consoles (if you want to allow switching, this can be done */
+    /*       elsewhere with a full save/restore state of the graphics mode). */
+    return 0;
+}
+
+int PMAPI PM_getConsoleStateSize(void)
+{
+    /* TODO: Returns the size of the console state buffer used to save the */
+    /*       state of the console before going into graphics mode. This is */
+    /*       used to restore the console back to normal when we are done. */
+    return 1;
+}
+
+void PMAPI PM_saveConsoleState(void *stateBuf,int console_id)
+{
+    /* TODO: Saves the state of the console into the state buffer. This is */
+    /*       used to restore the console back to normal when we are done. */
+    /*       We will always restore 80x25 text mode after being in graphics */
+    /*       mode, so if restoring text mode is all you need to do this can */
+    /*       be left empty. */
+}
+
+void PMAPI PM_restoreConsoleState(const void *stateBuf,int console_id)
+{
+    /* TODO: Restore the state of the console from the state buffer. This is */
+    /*       used to restore the console back to normal when we are done. */
+    /*       We will always restore 80x25 text mode after being in graphics */
+    /*       mode, so if restoring text mode is all you need to do this can */
+    /*       be left empty. */
+}
+
+void PMAPI PM_closeConsole(int console_id)
+{
+    /* TODO: Close the console when we are done, going back to text mode. */
+}
+
+void PM_setOSCursorLocation(int x,int y)
+{
+    /* TODO: Set the OS console cursor location to the new value. This is */
+    /*       generally used for new OS ports (used mostly for DOS). */
+}
+
+void PM_setOSScreenWidth(int width,int height)
+{
+    /* TODO: Set the OS console screen width. This is generally unused for */
+    /*       new OS ports. */
+}
+
+ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency)
+{
+    /* TODO: Install a real time clock interrupt handler. Normally this */
+    /*       will not be supported from most OS'es in user land, so an */
+    /*       alternative mechanism is needed to enable software stereo. */
+    /*       Hence leave this unimplemented unless you have a high priority */
+    /*       mechanism to call the 32-bit callback when the real time clock */
+    /*       interrupt fires. */
+    return false;
+}
+
+void PMAPI PM_setRealTimeClockFrequency(int frequency)
+{
+    /* TODO: Set the real time clock interrupt frequency. Used for stereo */
+    /*       LC shutter glasses when doing software stereo. Usually sets */
+    /*       the frequency to around 2048 Hz. */
+}
+
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    /* TODO: Restores the real time clock handler. */
+}
+
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    return getcwd(path,maxLen);
+}
+
+char PMAPI PM_getBootDrive(void)
+{ return '/'; }
+
+const char * PMAPI PM_getVBEAFPath(void)
+{ return PM_getNucleusConfigPath(); }
+
+const char * PMAPI PM_getNucleusPath(void)
+{
+    char *env = getenv("NUCLEUS_PATH");
+    return env ? env : "/usr/lib/nucleus";
+}
+
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+const char * PMAPI PM_getUniqueID(void)
+{
+    /* TODO: Return a unique ID for the machine. If a unique ID is not */
+    /*       available, return the machine name. */
+    static char buf[128];
+    gethostname(buf, 128);
+    return buf;
+}
+
+const char * PMAPI PM_getMachineName(void)
+{
+    /* TODO: Return the network machine name for the machine. */
+    static char buf[128];
+    gethostname(buf, 128);
+    return buf;
+}
+
+void * PMAPI PM_getBIOSPointer(void)
+{
+    /* No BIOS access on the BeOS */
+    return NULL;
+}
+
+void * PMAPI PM_getA0000Pointer(void)
+{
+    static void *bankPtr;
+    if (!bankPtr)
+	bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true);
+    return bankPtr;
+}
+
+void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{
+    /* TODO: This function maps a physical memory address to a linear */
+    /*       address in the address space of the calling process. */
+
+    /* NOTE: This function *must* be able to handle any phsyical base */
+    /*       address, and hence you will have to handle rounding of */
+    /*       the physical base address to a page boundary (ie: 4Kb on */
+    /*       x86 CPU's) to be able to properly map in the memory */
+    /*       region. */
+
+    /* NOTE: If possible the isCached bit should be used to ensure that */
+    /*       the PCD (Page Cache Disable) and PWT (Page Write Through) */
+    /*       bits are set to disable caching for a memory mapping used */
+    /*       for MMIO register access. We also disable caching using */
+    /*       the MTRR registers for Pentium Pro and later chipsets so if */
+    /*       MTRR support is enabled for your OS then you can safely ignore */
+    /*       the isCached flag and always enable caching in the page */
+    /*       tables. */
+    return NULL;
+}
+
+void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit)
+{
+    /* TODO: This function will free a physical memory mapping previously */
+    /*       allocated with PM_mapPhysicalAddr() if at all possible. If */
+    /*       you can't free physical memory mappings, simply do nothing. */
+}
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{
+    /* TODO: This function should find the physical address of a linear */
+    /*       address. */
+    return 0xFFFFFFFFUL;
+}
+
+void PMAPI PM_sleep(ulong milliseconds)
+{
+    /* TODO: Put the process to sleep for milliseconds */
+}
+
+int PMAPI PM_getCOMPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	}
+    return 0;
+}
+
+int PMAPI PM_getLPTPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+void * PMAPI PM_mallocShared(long size)
+{
+    /* TODO: This is used to allocate memory that is shared between process */
+    /*       that all access the common Nucleus drivers via a common display */
+    /*       driver DLL. If your OS does not support shared memory (or if */
+    /*       the display driver does not need to allocate shared memory */
+    /*       for each process address space), this should just call PM_malloc. */
+    return PM_malloc(size);
+}
+
+void PMAPI PM_freeShared(void *ptr)
+{
+    /* TODO: Free the shared memory block. This will be called in the context */
+    /*       of the original calling process that allocated the shared */
+    /*       memory with PM_mallocShared. Simply call free if you do not */
+    /*       need this. */
+    PM_free(ptr);
+}
+
+void * PMAPI PM_mapToProcess(void *base,ulong limit)
+{
+    /* TODO: This function is used to map a physical memory mapping */
+    /*       previously allocated with PM_mapPhysicalAddr into the */
+    /*       address space of the calling process. If the memory mapping */
+    /*       allocated by PM_mapPhysicalAddr is global to all processes, */
+    /*       simply return the pointer. */
+    return base;
+}
+
+void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off)
+{
+    /* No BIOS access on the BeOS */
+    return NULL;
+}
+
+void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off)
+{
+    /* No BIOS access on the BeOS */
+    return NULL;
+}
+
+void PMAPI PM_freeRealSeg(void *mem)
+{
+    /* No BIOS access on the BeOS */
+}
+
+void PMAPI DPMI_int86(int intno, DPMI_regs *regs)
+{
+    /* No BIOS access on the BeOS */
+}
+
+int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out)
+{
+    /* No BIOS access on the BeOS */
+    return 0;
+}
+
+int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,
+    RMSREGS *sregs)
+{
+    /* No BIOS access on the BeOS */
+    return 0;
+}
+
+void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in,
+    RMSREGS *sregs)
+{
+    /* No BIOS access on the BeOS */
+}
+
+void PMAPI PM_availableMemory(ulong *physical,ulong *total)
+{
+    /* TODO: Report the amount of available memory, both the amount of */
+    /*       physical memory left and the amount of virtual memory left. */
+    /*       If the OS does not provide these services, report 0's. */
+    *physical = *total = 0;
+}
+
+void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg)
+{
+    /* TODO: Allocate a block of locked, physical memory of the specified */
+    /*       size. This is used for bus master operations. If this is not */
+    /*       supported by the OS, return NULL and bus mastering will not */
+    /*       be used. */
+    return NULL;
+}
+
+void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous)
+{
+    /* TODO: Free a memory block allocated with PM_allocLockedMem. */
+}
+
+void PMAPI PM_setBankA(int bank)
+{
+    /* No BIOS access on the BeOS */
+}
+
+void PMAPI PM_setBankAB(int bank)
+{
+    /* No BIOS access on the BeOS */
+}
+
+void PMAPI PM_setCRTStart(int x,int y,int waitVRT)
+{
+    /* No BIOS access on the BeOS */
+}
+
+ibool PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type)
+{
+    /* TODO: This function should enable Pentium Pro and Pentium II MTRR */
+    /*       write combining for the passed in physical memory base address */
+    /*       and length. Normally this is done via calls to an OS specific */
+    /*       device driver as this can only be done at ring 0. */
+    /* */
+    /* NOTE: This is a *very* important function to implement! If you do */
+    /*       not implement, graphics performance on the latest Intel chips */
+    /*       will be severly impaired. For sample code that can be used */
+    /*       directly in a ring 0 device driver, see the MSDOS implementation */
+    /*       which includes assembler code to do this directly (if the */
+    /*       program is running at ring 0). */
+    return false;
+}
+
+ibool PMAPI PM_doBIOSPOST(ushort axVal,ulong BIOSPhysAddr,void *mappedBIOS)
+{
+    /* TODO: This function is used to run the BIOS POST code on a secondary */
+    /*       controller to initialise it for use. This is not necessary */
+    /*       for multi-controller operation, but it will make it a lot */
+    /*       more convenicent for end users (otherwise they have to boot */
+    /*       the system once with the secondary controller as primary, and */
+    /*       then boot with both controllers installed). */
+    /* */
+    /*       Even if you don't support full BIOS access, it would be */
+    /*       adviseable to be able to POST the secondary controllers in the */
+    /*       system using this function as a minimum requirement. Some */
+    /*       graphics hardware has registers that contain values that only */
+    /*       the BIOS knows about, which makes bring up a card from cold */
+    /*       reset difficult if the BIOS has not POST'ed it. */
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+ulong PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    (void)filename;
+    (void)findData;
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    ulong handle,
+    PM_findData *findData)
+{
+    (void)handle;
+    (void)findData;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    ulong handle)
+{
+    (void)handle;
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    if (drive == 3)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    (void)drive;
+    getcwd(dir,len);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+    /* TODO: Set the file attributes for a file */
+    (void)filename;
+    (void)attrib;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c
new file mode 100755
index 0000000..579ef2c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c
@@ -0,0 +1,49 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    baseAddr = baseAddr;
+    bankSize = bankSize;
+    codeLen = codeLen;
+    bankFunc = bankFunc;
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c
new file mode 100755
index 0000000..a528b73
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c
@@ -0,0 +1,111 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE ***
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+void _ZTimerInit(void)
+{
+    /* TODO: Do any specific internal initialisation in here */
+}
+
+/****************************************************************************
+REMARKS:
+Start the Zen Timer counting.
+****************************************************************************/
+static void _LZTimerOn(
+    LZTimerObject *tm)
+{
+    /* TODO: Start the Zen Timer counting. This should be a macro if */
+    /*       possible. */
+}
+
+/****************************************************************************
+REMARKS:
+Compute the lap time since the timer was started.
+****************************************************************************/
+static ulong _LZTimerLap(
+    LZTimerObject *tm)
+{
+    /* TODO: Compute the lap time between the current time and when the */
+    /*       timer was started. */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Stop the Zen Timer counting.
+****************************************************************************/
+static void _LZTimerOff(
+    LZTimerObject *tm)
+{
+    /* TODO: Stop the timer counting. Should be a macro if possible. */
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time in microseconds between start and end timings.
+****************************************************************************/
+static ulong _LZTimerCount(
+    LZTimerObject *tm)
+{
+    /* TODO: Compute the elapsed time and return it. Always microseconds. */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION 1
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer from the OS
+****************************************************************************/
+static ulong _ULZReadTime(void)
+{
+    /* TODO: Read the long period timer from the OS. The resolution of this */
+    /*       timer should be around 1/20 of a second for timing long */
+    /*       periods if possible. */
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong _ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c b/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c
new file mode 100755
index 0000000..9aa8714
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c
@@ -0,0 +1,285 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Keyboard translation code pages for US English keyboards.
+*
+****************************************************************************/
+
+#include "event.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+/* This table is used for all normal key translations, and is the fallback
+ * table if the key is not found in any of the other translation tables.
+ * If the code is not found in this table, the ASCII code is set to 0 to
+ * indicate that there is no ASCII code equivalent for this key.
+ */
+static codepage_entry_t US_normal[] = {
+    {0x01,  0x1B},
+    {0x02,  '1'},
+    {0x03,  '2'},
+    {0x04,  '3'},
+    {0x05,  '4'},
+    {0x06,  '5'},
+    {0x07,  '6'},
+    {0x08,  '7'},
+    {0x09,  '8'},
+    {0x0A,  '9'},
+    {0x0B,  '0'},
+    {0x0C,  '-'},
+    {0x0D,  '='},
+    {0x0E,  0x08},
+    {0x0F,  0x09},
+    {0x10,  'q'},
+    {0x11,  'w'},
+    {0x12,  'e'},
+    {0x13,  'r'},
+    {0x14,  't'},
+    {0x15,  'y'},
+    {0x16,  'u'},
+    {0x17,  'i'},
+    {0x18,  'o'},
+    {0x19,  'p'},
+    {0x1A,  '['},
+    {0x1B,  ']'},
+    {0x1C,  0x0D},
+    {0x1E,  'a'},
+    {0x1F,  's'},
+    {0x20,  'd'},
+    {0x21,  'f'},
+    {0x22,  'g'},
+    {0x23,  'h'},
+    {0x24,  'j'},
+    {0x25,  'k'},
+    {0x26,  'l'},
+    {0x27,  ';'},
+    {0x28,  '\''},
+    {0x29,  '`'},
+    {0x2B,  '\\'},
+    {0x2C,  'z'},
+    {0x2D,  'x'},
+    {0x2E,  'c'},
+    {0x2F,  'v'},
+    {0x30,  'b'},
+    {0x31,  'n'},
+    {0x32,  'm'},
+    {0x33,  ','},
+    {0x34,  '.'},
+    {0x35,  '/'},
+    {0x37,  '*'},           /* Keypad */
+    {0x39,  ' '},
+    {0x4A,  '-'},           /* Keypad */
+    {0x4E,  '+'},           /* Keypad */
+    {0x60,  0x0D},          /* Keypad */
+    {0x61,  '/'},           /* Keypad */
+    };
+
+/* This table is used for when CAPSLOCK is active and the shift or ctrl
+ * keys are not down. If the code is not found in this table, the normal
+ * table above is then searched.
+ */
+static codepage_entry_t US_caps[] = {
+    {0x10,  'Q'},
+    {0x11,  'W'},
+    {0x12,  'E'},
+    {0x13,  'R'},
+    {0x14,  'T'},
+    {0x15,  'Y'},
+    {0x16,  'U'},
+    {0x17,  'I'},
+    {0x18,  'O'},
+    {0x19,  'P'},
+    {0x1E,  'A'},
+    {0x1F,  'S'},
+    {0x20,  'D'},
+    {0x21,  'F'},
+    {0x22,  'G'},
+    {0x23,  'H'},
+    {0x24,  'J'},
+    {0x25,  'K'},
+    {0x26,  'L'},
+    {0x2C,  'Z'},
+    {0x2D,  'X'},
+    {0x2E,  'C'},
+    {0x2F,  'V'},
+    {0x30,  'B'},
+    {0x31,  'N'},
+    {0x32,  'M'},
+    };
+
+/* This table is used for when shift key is down, but the ctrl key is not
+ * down and CAPSLOCK is not active. If the code is not found in this table,
+ * the normal table above is then searched.
+ */
+static codepage_entry_t US_shift[] = {
+    {0x02,  '!'},
+    {0x03,  '@'},
+    {0x04,  '#'},
+    {0x05,  '$'},
+    {0x06,  '%'},
+    {0x07,  '^'},
+    {0x08,  '&'},
+    {0x09,  '*'},
+    {0x0A,  '('},
+    {0x0B,  ')'},
+    {0x0C,  '_'},
+    {0x0D,  '+'},
+    {0x10,  'Q'},
+    {0x11,  'W'},
+    {0x12,  'E'},
+    {0x13,  'R'},
+    {0x14,  'T'},
+    {0x15,  'Y'},
+    {0x16,  'U'},
+    {0x17,  'I'},
+    {0x18,  'O'},
+    {0x19,  'P'},
+    {0x1A,  '{'},
+    {0x1B,  '}'},
+    {0x1E,  'A'},
+    {0x1F,  'S'},
+    {0x20,  'D'},
+    {0x21,  'F'},
+    {0x22,  'G'},
+    {0x23,  'H'},
+    {0x24,  'J'},
+    {0x25,  'K'},
+    {0x26,  'L'},
+    {0x27,  ':'},
+    {0x28,  '"'},
+    {0x29,  '~'},
+    {0x2B,  '|'},
+    {0x2C,  'Z'},
+    {0x2D,  'X'},
+    {0x2E,  'C'},
+    {0x2F,  'V'},
+    {0x30,  'B'},
+    {0x31,  'N'},
+    {0x32,  'M'},
+    {0x33,  '<'},
+    {0x34,  '>'},
+    {0x35,  '?'},
+    };
+
+/* This table is used for when CAPSLOCK is active and the shift key is
+ * down, but the ctrl key is not. If the code is not found in this table,
+ * the shift table above is then searched.
+ */
+static codepage_entry_t US_shiftCaps[] = {
+    {0x10,  'q'},
+    {0x11,  'w'},
+    {0x12,  'e'},
+    {0x13,  'r'},
+    {0x14,  't'},
+    {0x15,  'y'},
+    {0x16,  'u'},
+    {0x17,  'i'},
+    {0x18,  'o'},
+    {0x19,  'p'},
+    {0x1E,  'a'},
+    {0x1F,  's'},
+    {0x20,  'd'},
+    {0x21,  'f'},
+    {0x22,  'g'},
+    {0x23,  'h'},
+    {0x24,  'j'},
+    {0x25,  'k'},
+    {0x26,  'l'},
+    {0x2C,  'z'},
+    {0x2D,  'x'},
+    {0x2E,  'c'},
+    {0x2F,  'v'},
+    {0x30,  'b'},
+    {0x31,  'n'},
+    {0x32,  'm'},
+    };
+
+/* This table is used for all key translations when the ctrl key is down,
+ * regardless of the state of the shift key and CAPSLOCK. If the code is
+ * not found in this table, the ASCII code is set to 0 to indicate that
+ * there is no ASCII code equivalent for this key.
+ */
+static codepage_entry_t US_ctrl[] = {
+    {0x01,  0x1B},
+    {0x06,  0x1E},
+    {0x0C,  0x1F},
+    {0x0E,  0x7F},
+    {0x10,  0x11},
+    {0x11,  0x17},
+    {0x12,  0x05},
+    {0x13,  0x12},
+    {0x14,  0x14},
+    {0x15,  0x19},
+    {0x16,  0x16},
+    {0x17,  0x09},
+    {0x18,  0x0F},
+    {0x19,  0x10},
+    {0x1A,  0x1B},
+    {0x1B,  0x1D},
+    {0x1C,  0x0A},
+    {0x1E,  0x01},
+    {0x1F,  0x13},
+    {0x20,  0x04},
+    {0x21,  0x06},
+    {0x22,  0x07},
+    {0x23,  0x08},
+    {0x24,  0x0A},
+    {0x25,  0x0B},
+    {0x26,  0x0C},
+    {0x2B,  0x1C},
+    {0x2C,  0x1A},
+    {0x2D,  0x18},
+    {0x2E,  0x03},
+    {0x2F,  0x16},
+    {0x30,  0x02},
+    {0x31,  0x0E},
+    {0x32,  0x0D},
+    {0x39,  ' '},
+    };
+
+static codepage_entry_t US_numPad[] = {
+    {0x4C,  '5'},
+    {0x62,  '4'},
+    {0x63,  '6'},
+    {0x64,  '8'},
+    {0x65,  '2'},
+    {0x66,  '0'},
+    {0x67,  '.'},
+    {0x68,  '7'},
+    {0x69,  '1'},
+    {0x6A,  '9'},
+    {0x6B,  '3'},
+    };
+
+codepage_t _CP_US_English = {
+    "US English",
+    US_normal,      EVT_ARR_SIZE(US_normal),
+    US_caps,        EVT_ARR_SIZE(US_caps),
+    US_shift,       EVT_ARR_SIZE(US_shift),
+    US_shiftCaps,   EVT_ARR_SIZE(US_shiftCaps),
+    US_ctrl,        EVT_ARR_SIZE(US_ctrl),
+    US_numPad,      EVT_ARR_SIZE(US_numPad),
+    };
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common.c b/board/MAI/bios_emulator/scitech/src/pm/common.c
new file mode 100755
index 0000000..d5a8e8f
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common.c
@@ -0,0 +1,480 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Module containing code common to all platforms.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#if defined(__WIN32_VXD__) || defined(__OS2_VDD__) || defined(__NT_DRIVER__)
+#include "sdd/sddhelp.h"
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#endif
+
+/*---------------------------- Global variables ---------------------------*/
+
+/* {secret} */
+long _VARAPI    ___drv_os_type = _OS_UNSUPPORTED;
+static char     localBPDPath[PM_MAX_PATH] = "";
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+path    - Local path to the Nucleus BPD driver files.
+
+REMARKS:
+This function is used by the application program to override the location
+of the Nucleus driver files that are loaded. Normally the loader code
+will look in the system Nucleus directories first, then in the 'drivers'
+directory relative to the current working directory, and finally relative
+to the MGL_ROOT environment variable. By default the local BPD path is
+always set to the current directory if not initialised.
+****************************************************************************/
+void PMAPI PM_setLocalBPDPath(
+    const char *path)
+{
+    PM_init();
+    strncpy(localBPDPath,path,sizeof(localBPDPath));
+    localBPDPath[sizeof(localBPDPath)-1] = 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+bpdpath     - Place to store the actual path to the file
+cachedpath  - Place to store the cached BPD driver path
+trypath     - Path to try to find the BPD file in
+subpath     - Optional sub path to append to trypath
+dllname     - Name of the Binary Portable DLL to load
+
+RETURNS:
+True if found, false if not.
+
+REMARKS:
+Trys the specified path to see if the BPD file can be found or not. If so,
+the path used is returned in bpdpath and cachedpath.
+****************************************************************************/
+static ibool TryPath(
+    char *bpdpath,
+    char *cachedpath,
+    const char *trypath,
+    const char *subpath,
+    const char *dllname)
+{
+    char    filename[256];
+    FILE    *f;
+
+    strcpy(bpdpath, trypath);
+    PM_backslash(bpdpath);
+    strcat(bpdpath,subpath);
+    PM_backslash(bpdpath);
+    strcpy(filename,bpdpath);
+    strcat(filename,dllname);
+    if ((f = fopen(filename,"rb")) == NULL)
+	return false;
+    if (cachedpath)
+	strcpy(cachedpath,bpdpath);
+    fclose(f);
+    return true;
+}
+
+/****************************************************************************
+RETURNS:
+True if local override enabled, false if not.
+
+REMARKS:
+Tests to see if the local override option is enabled, and if so it will
+look for the Nucleus drivers in the local application directories in
+preference to the Nucleus system directories.
+****************************************************************************/
+static ibool GetLocalOverride(void)
+{
+    char            filename[256];
+    FILE            *f;
+    static ibool    local_override = -1;
+
+    if (local_override == -1) {
+	local_override = false;
+	strcpy(filename,PM_getNucleusPath());
+	PM_backslash(filename);
+	strcat(filename,"graphics.ini");
+	if ((f = fopen(filename,"r")) != NULL) {
+	    while (!feof(f) && fgets(filename,sizeof(filename),f)) {
+		if (strnicmp(filename,"uselocal",8) == 0) {
+		    local_override = ((*(filename+9) - '0') == 1);
+		    break;
+		    }
+		}
+	    fclose(f);
+	    }
+	}
+    return local_override;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Sets the location of the debug log file.
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+dllname - Name of the Binary Portable DLL to load
+bpdpath - Place to store the actual path to the file
+
+RETURNS:
+True if found, false if not.
+
+REMARKS:
+Finds the location of a specific Binary Portable DLL, by searching all
+the standard SciTech Nucleus driver locations.
+****************************************************************************/
+ibool PMAPI PM_findBPD(
+    const char *dllname,
+    char *bpdpath)
+{
+    static char cachedpath[PM_MAX_PATH] = "";
+
+    /* On the first call determine the path to the Nucleus drivers */
+    if (cachedpath[0] == 0) {
+	/* First try in the global system Nucleus driver path if
+	 * the local override setting is not enabled.
+	 */
+	PM_init();
+	if (!GetLocalOverride()) {
+	    if (TryPath(bpdpath,cachedpath,PM_getNucleusPath(),"",dllname))
+		return true;
+	    }
+
+	/* Next try in the local application directory if available */
+	if (localBPDPath[0] != 0) {
+	    if (TryPath(bpdpath,cachedpath,localBPDPath,"",dllname))
+		return true;
+	    }
+	else {
+#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__)
+	    char    *mgl_root;
+	    if ((mgl_root = getenv("MGL_ROOT")) != NULL) {
+		if (TryPath(bpdpath,cachedpath,mgl_root,"drivers",dllname))
+		    return true;
+		}
+#endif
+	    PM_getCurrentPath(bpdpath,PM_MAX_PATH);
+	    if (TryPath(bpdpath,cachedpath,bpdpath,"drivers",dllname))
+		return true;
+	    }
+
+	/* Finally try in the global system path again so that we
+	 * will still find the drivers in the global system path if
+	 * the local override option is on, but the application does
+	 * not have any local override drivers.
+	 */
+	if (TryPath(bpdpath,cachedpath,PM_getNucleusPath(),"",dllname))
+	    return true;
+
+	/* Whoops, we can't find the BPD file! */
+	return false;
+	}
+
+    /* Always try in the previously discovered path */
+    return TryPath(bpdpath,NULL,cachedpath,"",dllname);
+}
+
+/****************************************************************************
+REMARKS:
+Copies a string into another, and returns dest + strlen(src).
+****************************************************************************/
+static char *_stpcpy(
+    char *_dest,
+    const char *_src)
+{
+    if (!_dest || !_src)
+	return 0;
+    while ((*_dest++ = *_src++) != 0)
+	;
+    return --_dest;
+}
+
+/****************************************************************************
+REMARKS:
+Copies a string into another, stopping at the maximum length. The string
+is properly terminated (unlike strncpy).
+****************************************************************************/
+static void safe_strncpy(
+    char *dst,
+    const char *src,
+    unsigned maxlen)
+{
+    if (dst) {
+	if(strlen(src) >= maxlen) {
+	    strncpy(dst, src, maxlen);
+	    dst[maxlen] = 0;
+	    }
+	else
+	    strcpy(dst, src);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Determins if the dot separator is present in the string.
+****************************************************************************/
+static int findDot(
+    char *p)
+{
+    if (*(p-1) == '.')
+	p--;
+    switch (*--p) {
+	case ':':
+	    if (*(p-2) != '\0')
+		break;
+	case '/':
+	case '\\':
+	case '\0':
+	    return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Make a full pathname from split components.
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+path    - Place to store full path
+drive   - Drive component for path
+dir     - Directory component for path
+name    - Filename component for path
+ext     - Extension component for path
+
+REMARKS:
+Function to make a full pathname from split components. Under Unix the
+drive component will usually be empty. If the drive, dir, name, or ext
+parameters are null or empty, they are not inserted in the path string.
+Otherwise, if the drive doesn't end with a colon, one is inserted in the
+path. If the dir doesn't end in a slash, one is inserted in the path.
+If the ext doesn't start with a dot, one is inserted in the path.
+
+The maximum sizes for the path string is given by the constant PM_MAX_PATH,
+which includes space for the null-terminator.
+
+SEE ALSO:
+PM_splitPath
+****************************************************************************/
+void PMAPI PM_makepath(
+    char *path,
+    const char *drive,
+    const char *dir,
+    const char *name,
+    const char *ext)
+{
+    if (drive && *drive) {
+	*path++ = *drive;
+	*path++ = ':';
+	}
+    if (dir && *dir) {
+	path = _stpcpy(path,dir);
+	if (*(path-1) != '\\' && *(path-1) != '/')
+#ifdef  __UNIX__
+	    *path++ = '/';
+#else
+	    *path++ = '\\';
+#endif
+	}
+    if (name)
+	path = _stpcpy(path,name);
+    if (ext && *ext) {
+	if (*ext != '.')
+	    *path++ = '.';
+	path = _stpcpy(path,ext);
+	}
+    *path = 0;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Split a full pathname into components.
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+path    - Full path to split
+drive   - Drive component for path
+dir     - Directory component for path
+name    - Filename component for path
+ext     - Extension component for path
+
+RETURNS:
+Flags indicating what components were parsed.
+
+REMARKS:
+Function to split a full pathmame into separate components in the form
+
+    X:\DIR\SUBDIR\NAME.EXT
+
+and splits path into its four components. It then stores those components
+in the strings pointed to by drive, dir, name and ext. (Each component is
+required but can be a NULL, which means the corresponding component will be
+parsed but not stored).
+
+The maximum sizes for these strings are given by the constants PM_MAX_DRIVE
+and PM_MAX_PATH. PM_MAX_DRIVE is always 4, and PM_MAX_PATH is usually at
+least 256 characters. Under Unix the dir, name and ext components may be
+up to the full path in length.
+
+SEE ALSO:
+PM_makePath
+****************************************************************************/
+int PMAPI PM_splitpath(
+    const char *path,
+    char *drive,
+    char *dir,
+    char *name,
+    char *ext)
+{
+    char    *p;
+    int     temp,ret;
+    char    buf[PM_MAX_PATH+2];
+
+    /* Set all string to default value zero */
+    ret = 0;
+    if (drive)  *drive = 0;
+    if (dir)    *dir = 0;
+    if (name)   *name = 0;
+    if (ext)    *ext = 0;
+
+    /* Copy filename into template up to PM_MAX_PATH characters */
+    p = buf;
+    if ((temp = strlen(path)) > PM_MAX_PATH)
+	temp = PM_MAX_PATH;
+    *p++ = 0;
+    strncpy(p, path, temp);
+    *(p += temp) = 0;
+
+    /* Split the filename and fill corresponding nonzero pointers */
+    temp = 0;
+    for (;;) {
+	switch (*--p) {
+	    case '.':
+		if (!temp && (*(p+1) == '\0'))
+		    temp = findDot(p);
+		if ((!temp) && ((ret & PM_HAS_EXTENSION) == 0)) {
+		    ret |= PM_HAS_EXTENSION;
+		    safe_strncpy(ext, p, PM_MAX_PATH - 1);
+		    *p = 0;
+		    }
+		continue;
+	    case ':':
+		if (p != &buf[2])
+		    continue;
+	    case '\0':
+		if (temp) {
+		    if (*++p)
+			ret |= PM_HAS_DIRECTORY;
+		    safe_strncpy(dir, p, PM_MAX_PATH - 1);
+		    *p-- = 0;
+		    break;
+		    }
+	    case '/':
+	    case '\\':
+		if (!temp) {
+		    temp++;
+		    if (*++p)
+			ret |= PM_HAS_FILENAME;
+		    safe_strncpy(name, p, PM_MAX_PATH - 1);
+		    *p-- = 0;
+		    if (*p == 0 || (*p == ':' && p == &buf[2]))
+			break;
+		    }
+		continue;
+	    case '*':
+	    case '?':
+		if (!temp)
+		    ret |= PM_HAS_WILDCARDS;
+	    default:
+		continue;
+	    }
+	break;
+	}
+    if (*p == ':') {
+	if (buf[1])
+	    ret |= PM_HAS_DRIVE;
+	safe_strncpy(drive, &buf[1], PM_MAX_DRIVE - 1);
+	}
+    return ret;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Block until a specific time has elapsed since the last call
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+milliseconds    - Number of milliseconds for delay
+
+REMARKS:
+This function will block the calling thread or process until the specified
+number of milliseconds have passed since the /last/ call to this function.
+The first time this function is called, it will return immediately. On
+subsquent calls it will block until the specified time has elapsed, or it
+will return immediately if the time has already elapsed.
+
+This function is useful to provide constant time functionality in a
+program, such as a frame rate limiter for graphics applications etc.
+
+SEE ALSO:
+PM_sleep
+****************************************************************************/
+void PMAPI PM_blockUntilTimeout(
+    ulong milliseconds)
+{
+    ulong                   microseconds = milliseconds * 1000L,msDelay;
+    static LZTimerObject    tm;
+    static ibool            firstTime = true;
+
+    if (firstTime) {
+	firstTime = false;
+	LZTimerOnExt(&tm);
+	}
+    else {
+	if ((msDelay = (microseconds - LZTimerLapExt(&tm)) / 1000L) > 0)
+	    PM_sleep(msDelay);
+	while (LZTimerLapExt(&tm) < microseconds)
+	    ;
+	LZTimerOffExt(&tm);
+	LZTimerOnExt(&tm);
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm
new file mode 100755
index 0000000..60ebed7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm
@@ -0,0 +1,600 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    NASM or TASM Assembler
+;* Environment: Intel 32 bit Protected Mode.
+;*
+;* Description: Code to determine the Intel processor type.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"
+
+header      _cpuinfo
+
+begdataseg  _cpuinfo                ; Start of data segment
+
+cache_id    db  "01234567890123456"
+intel_id    db  "GenuineIntel"      ; Intel vendor ID
+cyrix_id    db  "CyrixInstead"      ; Cyrix vendor ID
+amd_id      db  "AuthenticAMD"      ; AMD vendor ID
+idt_id      db  "CentaurHauls"      ; IDT vendor ID
+
+CPU_IDT     EQU 01000h              ; Flag for IDT processors
+CPU_Cyrix   EQU 02000h              ; Flag for Cyrix processors
+CPU_AMD     EQU 04000h              ; Flag for AMD processors
+CPU_Intel   EQU 08000h              ; Flag for Intel processors
+
+enddataseg  _cpuinfo
+
+begcodeseg  _cpuinfo                ; Start of code segment
+
+ifdef   USE_NASM
+%macro mCPU_ID 0
+db  00Fh,0A2h
+%endmacro
+else
+MACRO   mCPU_ID
+db  00Fh,0A2h
+ENDM
+endif
+
+ifdef   USE_NASM
+%macro mRDTSC 0
+db  00Fh,031h
+%endmacro
+else
+MACRO   mRDTSC
+db  00Fh,031h
+ENDM
+endif
+
+;----------------------------------------------------------------------------
+; bool _CPU_check80386(void)
+;----------------------------------------------------------------------------
+; Determines if we have an i386 processor.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_check80386
+
+        enter_c
+
+        xor     edx,edx             ; EDX = 0, not an 80386
+        mov     bx, sp
+ifdef   USE_NASM
+        and     sp, ~3
+else
+        and     sp, not 3
+endif
+        pushfd                      ; Push original EFLAGS
+        pop     eax                 ; Get original EFLAGS
+        mov     ecx, eax            ; Save original EFLAGS
+        xor     eax, 40000h         ; Flip AC bit in EFLAGS
+        push    eax                 ; Save new EFLAGS value on
+                                    ;   stack
+        popfd                       ; Replace current EFLAGS value
+        pushfd                      ; Get new EFLAGS
+        pop     eax                 ; Store new EFLAGS in EAX
+        xor     eax, ecx            ; Can't toggle AC bit,
+                                    ;   processor=80386
+        jnz     @@Done              ; Jump if not an 80386 processor
+        inc     edx                 ; We have an 80386
+
+@@Done: push    ecx
+        popfd
+        mov     sp, bx
+        mov     eax, edx
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; bool _CPU_check80486(void)
+;----------------------------------------------------------------------------
+; Determines if we have an i486 processor.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_check80486
+
+        enter_c
+
+; Distinguish between the i486 and Pentium by the ability to set the ID flag
+; in the EFLAGS register. If the ID flag is set, then we can use the CPUID
+; instruction to determine the final version of the chip. Otherwise we
+; simply have an 80486.
+
+; Distinguish between the i486 and Pentium by the ability to set the ID flag
+; in the EFLAGS register. If the ID flag is set, then we can use the CPUID
+; instruction to determine the final version of the chip. Otherwise we
+; simply have an 80486.
+
+        pushfd                      ; Get original EFLAGS
+        pop     eax
+        mov     ecx, eax
+        xor     eax, 200000h        ; Flip ID bit in EFLAGS
+        push    eax                 ; Save new EFLAGS value on stack
+        popfd                       ; Replace current EFLAGS value
+        pushfd                      ; Get new EFLAGS
+        pop     eax                 ; Store new EFLAGS in EAX
+        xor     eax, ecx            ; Can not toggle ID bit,
+        jnz     @@1                 ; Processor=80486
+        mov     eax,1               ; We dont have a Pentium
+        jmp     @@Done
+@@1:    mov     eax,0               ; We have Pentium or later
+@@Done: leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; bool _CPU_checkClone(void)
+;----------------------------------------------------------------------------
+; Checks if the i386 or i486 processor is a clone or genuine Intel.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_checkClone
+
+        enter_c
+
+        mov     ax,5555h            ; Check to make sure this is a 32-bit processor
+        xor     dx,dx
+        mov     cx,2h
+        div     cx                  ; Perform Division
+        clc
+        jnz     @@NoClone
+        jmp     @@Clone
+@@NoClone:
+        stc
+@@Clone:
+        pushfd
+        pop     eax                 ; Get the flags
+        and     eax,1
+        xor     eax,1               ; EAX=0 is probably Intel, EAX=1 is a Clone
+
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; bool _CPU_haveCPUID(void)
+;----------------------------------------------------------------------------
+; Determines if we have support for the CPUID instruction.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_haveCPUID
+
+        enter_c
+
+ifdef flatmodel
+        pushfd                      ; Get original EFLAGS
+        pop     eax
+        mov     ecx, eax
+        xor     eax, 200000h        ; Flip ID bit in EFLAGS
+        push    eax                 ; Save new EFLAGS value on stack
+        popfd                       ; Replace current EFLAGS value
+        pushfd                      ; Get new EFLAGS
+        pop     eax                 ; Store new EFLAGS in EAX
+        xor     eax, ecx            ; Can not toggle ID bit,
+        jnz     @@1                 ; Processor=80486
+        mov     eax,0               ; We dont have CPUID support
+        jmp     @@Done
+@@1:    mov     eax,1               ; We have CPUID support
+else
+        mov     eax,0               ; CPUID requires 32-bit pmode
+endif
+@@Done: leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uint _CPU_checkCPUID(void)
+;----------------------------------------------------------------------------
+; Determines the CPU type using the CPUID instruction.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_checkCPUID
+
+        enter_c
+
+        xor     eax, eax            ; Set up for CPUID instruction
+        mCPU_ID                     ; Get and save vendor ID
+        cmp     eax, 1              ; Make sure 1 is valid input for CPUID
+        jl      @@Fail              ; We dont have the CPUID instruction
+        xor     eax,eax             ; Assume vendor is unknown
+
+; Check for GenuineIntel processors
+
+        LEA_L   esi,intel_id
+        cmp     [DWORD esi], ebx
+        jne     @@NotIntel
+        cmp     [DWORD esi+4], edx
+        jne     @@NotIntel
+        cmp     [DWORD esi+8], ecx
+        jne     @@NotIntel
+        mov     eax,CPU_Intel       ; Flag that we have GenuineIntel
+        jmp     @@FoundVendor
+
+; Check for CyrixInstead processors
+
+@@NotIntel:
+        LEA_L   esi,cyrix_id
+        cmp     [DWORD esi], ebx
+        jne     @@NotCyrix
+        cmp     [DWORD esi+4], edx
+        jne     @@NotCyrix
+        cmp     [DWORD esi+8], ecx
+        jne     @@NotCyrix
+        mov     eax,CPU_Cyrix       ; Flag that we have CyrixInstead
+        jmp     @@FoundVendor
+
+; Check for AuthenticAMD processors
+
+@@NotCyrix:
+        LEA_L   esi,amd_id
+        cmp     [DWORD esi], ebx
+        jne     @@NotAMD
+        cmp     [DWORD esi+4], edx
+        jne     @@NotAMD
+        cmp     [DWORD esi+8], ecx
+        jne     @@NotAMD
+        mov     eax,CPU_AMD         ; Flag that we have AuthenticAMD
+        jmp     @@FoundVendor
+
+; Check for CentaurHauls processors
+
+@@NotAMD:
+        LEA_L   esi,idt_id
+        cmp     [DWORD esi], ebx
+        jne     @@NotIDT
+        cmp     [DWORD esi+4], edx
+        jne     @@NotIDT
+        cmp     [DWORD esi+8], ecx
+        jne     @@NotIDT
+        mov     eax,CPU_IDT         ; Flag that we have AuthenticIDT
+        jmp     @@FoundVendor
+
+@@NotIDT:
+
+@@FoundVendor:
+        push    eax
+        xor     eax, eax
+        inc     eax
+        mCPU_ID                     ; Get family/model/stepping/features
+        and     eax, 0F00h
+        shr     eax, 8              ; Isolate family
+        and     eax, 0Fh
+        pop     ecx
+        or      eax,ecx             ; Combine in the clone flag
+@@Done: leave_c
+        ret
+
+@@Fail: xor     eax,eax
+        jmp     @@Done
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uint _CPU_getCPUIDModel(void)
+;----------------------------------------------------------------------------
+; Determines the CPU type using the CPUID instruction.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_getCPUIDModel
+
+        enter_c
+
+        xor     eax, eax            ; Set up for CPUID instruction
+        mCPU_ID                     ; Get and save vendor ID
+        cmp     eax, 1              ; Make sure 1 is valid input for CPUID
+        jl      @@Fail              ; We dont have the CPUID instruction
+        xor     eax, eax
+        inc     eax
+        mCPU_ID                     ; Get family/model/stepping/features
+        and     eax, 0F0h
+        shr     eax, 4              ; Isolate model
+@@Done: leave_c
+        ret
+
+@@Fail: xor     eax,eax
+        jmp     @@Done
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uint _CPU_getCPUIDStepping(void)
+;----------------------------------------------------------------------------
+; Determines the CPU type using the CPUID instruction.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_getCPUIDStepping
+
+        enter_c
+
+        xor     eax, eax            ; Set up for CPUID instruction
+        mCPU_ID                     ; Get and save vendor ID
+        cmp     eax, 1              ; Make sure 1 is valid input for CPUID
+        jl      @@Fail              ; We dont have the CPUID instruction
+        xor     eax, eax
+        inc     eax
+        mCPU_ID                     ; Get family/model/stepping/features
+        and     eax, 00Fh           ; Isolate stepping
+@@Done: leave_c
+        ret
+
+@@Fail: xor     eax,eax
+        jmp     @@Done
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uint _CPU_getCPUIDFeatures(void)
+;----------------------------------------------------------------------------
+; Determines the CPU type using the CPUID instruction.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_getCPUIDFeatures
+
+        enter_c
+
+        xor     eax, eax            ; Set up for CPUID instruction
+        mCPU_ID                     ; Get and save vendor ID
+        cmp     eax, 1              ; Make sure 1 is valid input for CPUID
+        jl      @@Fail              ; We dont have the CPUID instruction
+        xor     eax, eax
+        inc     eax
+        mCPU_ID                     ; Get family/model/stepping/features
+        mov     eax, edx
+@@Done: leave_c
+        ret
+
+@@Fail: xor     eax,eax
+        jmp     @@Done
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uint _CPU_getCacheSize(void)
+;----------------------------------------------------------------------------
+; Determines the CPU cache size for Intel processors
+;----------------------------------------------------------------------------
+cprocstart  _CPU_getCacheSize
+
+        enter_c
+        xor     eax, eax            ; Set up for CPUID instruction
+        mCPU_ID                     ; Get and save vendor ID
+        cmp     eax,2               ; Make sure 2 is valid input for CPUID
+        jl      @@Fail              ; We dont have the CPUID instruction
+        mov     eax,2
+        mCPU_ID                     ; Get cache descriptors
+        LEA_L   esi,cache_id        ; Get address of cache ID (-fPIC aware)
+        shr     eax,8
+        mov     [esi+0],eax
+        mov     [esi+3],ebx
+        mov     [esi+7],ecx
+        mov     [esi+11],edx
+        xor     eax,eax
+        LEA_L   esi,cache_id        ; Get address of cache ID (-fPIC aware)
+        mov     edi,15
+@@ScanLoop:
+        cmp     [BYTE esi],41h
+        mov     eax,128
+        je      @@Done
+        cmp     [BYTE esi],42h
+        mov     eax,256
+        je      @@Done
+        cmp     [BYTE esi],43h
+        mov     eax,512
+        je      @@Done
+        cmp     [BYTE esi],44h
+        mov     eax,1024
+        je      @@Done
+        cmp     [BYTE esi],45h
+        mov     eax,2048
+        je      @@Done
+        inc     esi
+        dec     edi
+        jnz     @@ScanLoop
+
+@@Done: leave_c
+        ret
+
+@@Fail: xor     eax,eax
+        jmp     @@Done
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uint _CPU_have3DNow(void)
+;----------------------------------------------------------------------------
+; Determines the CPU type using the CPUID instruction.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_have3DNow
+
+        enter_c
+
+        mov     eax,80000000h       ; Query for extended functions
+        mCPU_ID                     ; Get extended function limit
+        cmp     eax,80000001h
+        jbe     @@Fail              ; Nope, we dont have function 800000001h
+        mov     eax,80000001h       ; Setup extended function 800000001h
+        mCPU_ID                     ; and get the information
+        test    edx,80000000h       ; Bit 31 is set if 3DNow! present
+        jz      @@Fail              ; Nope, we dont have 3DNow support
+        mov     eax,1               ; Yep, we have 3DNow! support!
+@@Done: leave_c
+        ret
+
+@@Fail: xor     eax,eax
+        jmp     @@Done
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _CPU_quickRDTSC(void)
+;----------------------------------------------------------------------------
+; Reads the time stamp counter and returns the low order 32-bits
+;----------------------------------------------------------------------------
+cprocstart  _CPU_quickRDTSC
+
+        mRDTSC
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _CPU_runBSFLoop(ulong interations)
+;----------------------------------------------------------------------------
+; Runs a loop of BSF instructions for the specified number of iterations
+;----------------------------------------------------------------------------
+cprocstart  _CPU_runBSFLoop
+
+        ARG     iterations:ULONG
+
+        push    _bp
+        mov     _bp,_sp
+        push    _bx
+
+        mov     edx,[iterations]
+        mov     eax,80000000h
+        mov     ebx,edx
+
+        ALIGN   4
+
+@@loop: bsf     ecx,eax
+        dec     ebx
+        jnz     @@loop
+
+        pop     _bx
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void  _CPU_readTimeStamp(CPU_largeInteger *time);
+;----------------------------------------------------------------------------
+; Reads the time stamp counter and returns the 64-bit result.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_readTimeStamp
+
+        mRDTSC
+        mov     ecx,[esp+4]     ; Access directly without stack frame
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _CPU_diffTime64(CPU_largeInteger *t1,CPU_largeInteger *t2,CPU_largeInteger *t)
+;----------------------------------------------------------------------------
+; Computes the difference between two 64-bit numbers.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_diffTime64
+
+        ARG     t1:DPTR, t2:DPTR, t:DPTR
+
+        enter_c
+
+        mov     ecx,[t2]
+        mov     eax,[ecx]       ; EAX := t2.low
+        mov     ecx,[t1]
+        sub     eax,[ecx]
+        mov     edx,eax         ; EDX := low difference
+        mov     ecx,[t2]
+        mov     eax,[ecx+4]     ; ECX := t2.high
+        mov     ecx,[t1]
+        sbb     eax,[ecx+4]     ; EAX := high difference
+
+        mov     ebx,[t]         ; Store the result
+        mov     [ebx],edx       ; Store low part
+        mov     [ebx+4],eax     ; Store high part
+        mov     eax,edx         ; Return low part
+ifndef flatmodel
+        shld    edx,eax,16      ; Return in DX:AX
+endif
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _CPU_calcMicroSec(CPU_largeInteger *count,ulong freq);
+;----------------------------------------------------------------------------
+; Computes the value in microseconds for the elapsed time with maximum
+; precision. The formula we use is:
+;
+;   us = (((diff * 0x100000) / freq) * 1000000) / 0x100000)
+;
+; The power of two multiple before the first divide allows us to scale the
+; 64-bit difference using simple shifts, and then the divide brings the
+; final result into the range to fit into a 32-bit integer.
+;----------------------------------------------------------------------------
+cprocstart  _CPU_calcMicroSec
+
+        ARG     count:DPTR, freq:ULONG
+
+        enter_c
+
+        mov     ecx,[count]
+        mov     eax,[ecx]       ; EAX := low part
+        mov     edx,[ecx+4]     ; EDX := high part
+        shld    edx,eax,20
+        shl     eax,20          ; diff * 0x100000
+        div     [DWORD freq]    ; (diff * 0x100000) / freq
+        mov     ecx,1000000
+        xor     edx,edx
+        mul     ecx             ; ((diff * 0x100000) / freq) * 1000000)
+        shrd    eax,edx,20      ; ((diff * 0x100000) / freq) * 1000000) / 0x100000
+ifndef flatmodel
+        shld    edx,eax,16      ; Return in DX:AX
+endif
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _CPU_mulDiv(ulong a,ulong b,ulong c);
+;----------------------------------------------------------------------------
+; Computes the following with 64-bit integer precision:
+;
+;   result = (a * b) / c
+;
+;----------------------------------------------------------------------------
+cprocstart  _CPU_mulDiv
+
+        ARG     a:ULONG, b:ULONG, c:ULONG
+
+        enter_c
+        mov     eax,[a]
+        imul    [ULONG b]
+        idiv    [ULONG c]
+ifndef flatmodel
+        shld    edx,eax,16      ; Return in DX:AX
+endif
+        leave_c
+        ret
+
+cprocend
+
+endcodeseg  _cpuinfo
+
+        END
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm
new file mode 100755
index 0000000..2b6e1e8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm
@@ -0,0 +1,246 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: 16/32 bit Ring 0 device driver
+;*
+;* Description: Assembler support routines for ISA DMA controller.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+header      _dma                ; Set up memory model
+
+begdataseg  _dma                ; Start of data segment
+
+cpublic _PM_DMADataStart
+
+; DMA register I/O addresses for channels 0-7 (except 4)
+
+DMAC_page       db 087h,083h,081h,082h, -1,08Bh,089h,08Ah
+DMAC_addr       db 000h,002h,004h,006h, -1,0C4h,0C8h,0CCh
+DMAC_cnt        db 001h,003h,005h,007h, -1,0C6h,0CAh,0CEh
+DMAC_mask       db 00Ah,00Ah,00Ah,00Ah, -1,0D4h,0D4h,0D4h
+DMAC_mode       db 00Bh,00Bh,00Bh,00Bh, -1,0D6h,0D6h,0D6h
+DMAC_FF         db 00Ch,00Ch,00Ch,00Ch, -1,0D8h,0D8h,0D8h
+
+cpublic _PM_DMADataEnd
+
+enddataseg  _dma
+
+begcodeseg  _dma                ; Start of code segment
+
+ifdef   flatmodel
+
+cpublic _PM_DMACodeStart
+
+;----------------------------------------------------------------------------
+; void PM_DMACDisable(int channel);
+;----------------------------------------------------------------------------
+; Masks DMA channel, inhibiting DMA transfers
+;----------------------------------------------------------------------------
+cprocstart  PM_DMACDisable
+
+        ARG     channel:UINT
+
+        push    ebp
+        mov     ebp,esp
+        mov     ecx,[channel]       ; ECX indexes DMAC register tables
+        mov     dh,0                ; DH = 0 for DMAC register port access
+        mov     al,cl
+        and     al,11b
+        or      al,100b             ; AL = (channel & 3) | "set mask bit"
+        mov     dl,[DMAC_mask+ecx]
+        out     dx,al
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_DMACEnable(int channel);
+;----------------------------------------------------------------------------
+; Unmasks DMA channel, enabling DMA transfers
+;----------------------------------------------------------------------------
+cprocstart  PM_DMACEnable
+
+        ARG     channel:UINT
+
+        push    ebp
+        mov     ebp,esp
+        mov     ecx,[channel]       ; ECX indexes DMAC register tables
+        mov     dh,0                ; DH = 0 for DMAC register port access
+        mov     al,cl
+        and     al,11b              ; AL = (channel & 3), "set mask bit"=0
+        mov     dl,[DMAC_mask+ecx]
+        out     dx,al
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_DMACProgram(int channel,int mode,ulong bufferPhys,int count);
+;----------------------------------------------------------------------------
+; Purpose: Program DMA controller to perform transfer from first 16MB
+; based on previously selected mode and channel. DMA transfer may be enabled
+; by subsequent call to PM_DMACEnable.
+;
+; Entry:    channel - DMA channel in use (0-7)
+;           mode    - Selected DMAMODE type for transfer
+;           buffer  - 32-bit physical address of DMA buffer
+;           count   - DMA byte count (1-65536 bytes)
+;----------------------------------------------------------------------------
+cprocstart  PM_DMACProgram
+
+        ARG     channel:UINT, mode:UINT, bufferPhys:ULONG, count:UINT
+
+        enter_c
+        pushfd
+        cli                         ; Disable interrupts
+
+; Mask DMA channel to disable it
+
+        mov     ebx,[channel]       ; EBX indexes DMAC register tables
+        mov     dh,0                ; DH = 0 for DMAC register port access
+        mov     al,bl
+        and     al,11b
+        or      al,100b             ; AL = (channel & 3) | "set mask bit"
+        mov     dl,[DMAC_mask+ebx]
+        out     dx,al
+
+; Generate IOW to clear FF toggle state
+
+        mov     al,0
+        mov     dl,[DMAC_FF+ebx]
+        out     dx,al
+
+; Compute buffer address to program
+
+        mov     eax,[bufferPhys]    ; AX := DMA address offset
+        mov     ecx,eax
+        shr     ecx,16              ; CL := bufferPhys >> 16 (DMA page)
+        mov     esi,[count]         ; ESI = # of bytes to transfer
+        cmp     ebx,4               ; 16-bit channel?
+        jb      @@WriteDMAC         ; No, program DMAC
+        shr     eax,1               ; Yes, convert address and count
+        shr     esi,1               ; to 16-bit, 128K/page format
+
+; Set the DMA address word (bits 0-15)
+
+@@WriteDMAC:
+        mov     dl,[DMAC_addr+ebx]
+        out     dx,al
+        mov     al,ah
+        out     dx,al
+
+; Set DMA transfer count
+
+        mov     eax,esi
+        dec     eax                 ; ESI = # of bytes to transfer - 1
+        mov     dl,[DMAC_cnt+ebx]
+        out     dx,al
+        mov     al,ah
+        out     dx,al
+
+; Set DMA page byte (bits 16-23)
+
+        mov     al,cl
+        mov     dl,[DMAC_page+ebx]
+        out     dx,al
+
+; Set the DMA channel mode
+
+        mov     al,bl
+        and     al,11b
+        or      al,[BYTE mode]      ; EAX = (channel & 3) | mode
+        mov     dl,[DMAC_mode+ebx]
+        out     dx,al
+
+        pop     eax                 ; SMP safe interrupt state restore!
+        test    eax,200h
+        jz      @@1
+        sti
+@@1:    leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong PMAPI PM_DMACPosition(int channel);
+;----------------------------------------------------------------------------
+; Returns the current position in a dma transfer. Interrupts should be
+; disabled before calling this function.
+;----------------------------------------------------------------------------
+cprocstart  PM_DMACPosition
+
+        ARG     channel:UINT
+
+        enter_c
+        mov     ecx,[channel]       ; ECX indexes DMAC register tables
+        mov     dh,0                ; DH = 0 for DMAC register port access
+
+; Generate IOW to clear FF toggle state
+
+        mov     al,0
+        mov     dl,[DMAC_FF+ebx]
+        out     dx,al
+        xor     eax,eax
+        xor     ecx,ecx
+
+; Now read the current position for the channel
+
+@@ReadLoop:
+        mov     dl,[DMAC_cnt+ebx]
+        out     dx,al
+        in      al,dx
+        mov     cl,al
+        in      al,dx
+        mov     ch,al               ; ECX := first count read
+        in      al,dx
+        mov     ah,al
+        in      al,dx
+        xchg    al,ah               ; EAX := second count read
+        sub     ecx,eax
+        cmp     ecx,40h
+        jg      @@ReadLoop
+        cmp     ebx,4               ; 16-bit channel?
+        jb      @@Exit              ; No, we are done
+        shl     eax,1               ; Yes, adjust to byte address
+
+@@Exit: leave_c
+        ret
+
+cprocend
+
+
+cpublic _PM_DMACodeEnd
+
+endif
+
+endcodeseg  _dma
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm
new file mode 100755
index 0000000..fdec1b5
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm
@@ -0,0 +1,309 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    NASM or TASM Assembler
+;* Environment: Intel 32 bit Protected Mode.
+;*
+;* Description: Code for 64-bit arhithmetic
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"
+
+header      _int64
+
+begcodeseg  _int64                  ; Start of code segment
+
+a_low       EQU 04h                 ; Access a_low directly on stack
+a_high      EQU 08h                 ; Access a_high directly on stack
+b_low       EQU 0Ch                 ; Access b_low directly on stack
+shift       EQU 0Ch                 ; Access shift directly on stack
+result_2    EQU 0Ch                 ; Access result directly on stack
+b_high      EQU 10h                 ; Access b_high directly on stack
+result_3    EQU 10h                 ; Access result directly on stack
+result_4    EQU 14h                 ; Access result directly on stack
+
+;----------------------------------------------------------------------------
+; void _PM_add64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result);
+;----------------------------------------------------------------------------
+; Adds two 64-bit numbers.
+;----------------------------------------------------------------------------
+cprocstart  _PM_add64
+
+        mov     eax,[esp+a_low]
+        add     eax,[esp+b_low]
+        mov     edx,[esp+a_high]
+        adc     edx,[esp+b_high]
+        mov     ecx,[esp+result_4]
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _PM_sub64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result);
+;----------------------------------------------------------------------------
+; Subtracts two 64-bit numbers.
+;----------------------------------------------------------------------------
+cprocstart  _PM_sub64
+
+        mov     eax,[esp+a_low]
+        sub     eax,[esp+b_low]
+        mov     edx,[esp+a_high]
+        sbb     edx,[esp+b_high]
+        mov     ecx,[esp+result_4]
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _PM_mul64(u32 a_high,u32 a_low,u32 b_high,u32 b_low,__u64 *result);
+;----------------------------------------------------------------------------
+; Multiples two 64-bit numbers.
+;----------------------------------------------------------------------------
+cprocstart  _PM_mul64
+
+        mov     eax,[esp+a_high]
+        mov     ecx,[esp+b_high]
+        or      ecx,eax
+        mov     ecx,[esp+b_low]
+        jnz     @@FullMultiply
+        mov     eax,[esp+a_low]         ; EDX:EAX = b.low * a.low
+        mul     ecx
+        mov     ecx,[esp+result_4]
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+@@FullMultiply:
+        push    ebx
+        mul     ecx                     ; EDX:EAX = a.high * b.low
+        mov     ebx,eax
+        mov     eax,[esp+a_low+4]
+        mul     [DWORD esp+b_high+4]    ; EDX:EAX = b.high * a.low
+        add     ebx,eax
+        mov     eax,[esp+a_low+4]
+        mul     ecx                     ; EDX:EAX = a.low * b.low
+        add     edx,ebx
+        pop     ebx
+        mov     ecx,[esp+result_4]
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _PM_div64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result);
+;----------------------------------------------------------------------------
+; Divides two 64-bit numbers.
+;----------------------------------------------------------------------------
+cprocstart  _PM_div64
+
+        push    edi
+        push    esi
+        push    ebx
+        xor     edi,edi
+        mov     eax,[esp+a_high+0Ch]
+        or      eax,eax
+        jns     @@ANotNeg
+
+; Dividend is negative, so negate it and save result for later
+
+        inc     edi
+        mov     edx,[esp+a_low+0Ch]
+        neg     eax
+        neg     edx
+        sbb     eax,0
+        mov     [esp+a_high+0Ch],eax
+        mov     [esp+a_low+0Ch],edx
+
+@@ANotNeg:
+        mov     eax,[esp+b_high+0Ch]
+        or      eax,eax
+        jns     @@BNotNeg
+
+; Divisor is negative, so negate it and save result for later
+
+        inc     edi
+        mov     edx,[esp+b_low+0Ch]
+        neg     eax
+        neg     edx
+        sbb     eax,0
+        mov     [esp+b_high+0Ch],eax
+        mov     [esp+b_low+0Ch],edx
+
+@@BNotNeg:
+        or      eax,eax
+        jnz     @@BHighNotZero
+
+; b.high is zero, so handle this faster
+
+        mov     ecx,[esp+b_low+0Ch]
+        mov     eax,[esp+a_high+0Ch]
+        xor     edx,edx
+        div     ecx
+        mov     ebx,eax
+        mov     eax,[esp+a_low+0Ch]
+        div     ecx
+        mov     edx,ebx
+        jmp     @@BHighZero
+
+@@BHighNotZero:
+        mov     ebx,eax
+        mov     ecx,[esp+b_low+0Ch]
+        mov     edx,[esp+a_high+0Ch]
+        mov     eax,[esp+a_low+0Ch]
+
+; Shift values right until b.high becomes zero
+
+@@ShiftLoop:
+        shr     ebx,1
+        rcr     ecx,1
+        shr     edx,1
+        rcr     eax,1
+        or      ebx,ebx
+        jnz     @@ShiftLoop
+
+; Now complete the divide process
+
+        div     ecx
+        mov     esi,eax
+        mul     [DWORD esp+b_high+0Ch]
+        mov     ecx,eax
+        mov     eax,[esp+b_low+0Ch]
+        mul     esi
+        add     edx,ecx
+        jb      @@8
+        cmp     edx,[esp+a_high+0Ch]
+        ja      @@8
+        jb      @@9
+        cmp     eax,[esp+a_low+0Ch]
+        jbe     @@9
+@@8:    dec     esi
+@@9:    xor     edx,edx
+        mov     eax,esi
+
+@@BHighZero:
+        dec     edi
+        jnz     @@Done
+
+; The result needs to be negated as either a or b was negative
+
+        neg     edx
+        neg     eax
+        sbb     edx,0
+
+@@Done: pop     ebx
+        pop     esi
+        pop     edi
+        mov     ecx,[esp+result_4]
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; __i64 _PM_shr64(u32 a_low,s32 a_high,s32 shift,__u64 *result);
+;----------------------------------------------------------------------------
+; Shift a 64-bit number right
+;----------------------------------------------------------------------------
+cprocstart  _PM_shr64
+
+        mov     eax,[esp+a_low]
+        mov     edx,[esp+a_high]
+        mov     cl,[esp+shift]
+        shrd    edx,eax,cl
+        mov     ecx,[esp+result_3]
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; __i64 _PM_sar64(u32 a_low,s32 a_high,s32 shift,__u64 *result);
+;----------------------------------------------------------------------------
+; Shift a 64-bit number right (signed)
+;----------------------------------------------------------------------------
+cprocstart  _PM_sar64
+
+        mov     eax,[esp+a_low]
+        mov     edx,[esp+a_high]
+        mov     cl,[esp+shift]
+        sar     edx,cl
+        rcr     eax,cl
+        mov     ecx,[esp+result_3]
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; __i64 _PM_shl64(u32 a_low,s32 a_high,s32 shift,__u64 *result);
+;----------------------------------------------------------------------------
+; Shift a 64-bit number left
+;----------------------------------------------------------------------------
+cprocstart  _PM_shl64
+
+        mov     eax,[esp+a_low]
+        mov     edx,[esp+a_high]
+        mov     cl,[esp+shift]
+        shld    edx,eax,cl
+        mov     ecx,[esp+result_3]
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; __i64 _PM_neg64(u32 a_low,s32 a_high,__u64 *result);
+;----------------------------------------------------------------------------
+; Shift a 64-bit number left
+;----------------------------------------------------------------------------
+cprocstart  _PM_neg64
+
+        mov     eax,[esp+a_low]
+        mov     edx,[esp+a_high]
+        neg     eax
+        neg     edx
+        sbb     eax,0
+        mov     ecx,[esp+result_2]
+        mov     [ecx],eax
+        mov     [ecx+4],edx
+        ret
+
+cprocend
+
+
+endcodeseg  _int64
+
+        END
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm
new file mode 100755
index 0000000..0ff1ecf
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm
@@ -0,0 +1,230 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler
+;* Environment: Intel x86, any OS
+;*
+;* Description: Assembly language support routines for reading analogue
+;*              joysticks.
+;*
+;****************************************************************************
+
+        ideal
+
+include "scitech.mac"           ; Memory model macros
+
+ifdef flatmodel
+
+header  _joy                    ; Set up memory model
+
+begcodeseg  _joy                ; Start of code segment
+
+;----------------------------------------------------------------------------
+; initTimer
+;----------------------------------------------------------------------------
+; Sets up 8253 timer 2 (PC speaker) to start timing, but not produce output.
+;----------------------------------------------------------------------------
+cprocstatic initTimer
+
+; Start timer 2 counting
+
+        in      al,61h
+        and     al,0FDh             ; Disable speaker output (just in case)
+        or      al,1
+        out     61h,al
+
+; Set the timer 2 count to 0 again to start the timing interval.
+
+        mov     al,10110100b        ; set up to load initial (timer 2)
+        out     43h,al              ; timer count
+        sub     al,al
+        out     42h,al              ; load count lsb
+        out     42h,al              ; load count msb
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; readTimer2
+;----------------------------------------------------------------------------
+; Reads the number of ticks from the 8253 timer chip using channel 2 (PC
+; speaker). This is non-destructive and does not screw up other libraries.
+;----------------------------------------------------------------------------
+cprocstatic readTimer
+
+        xor     al,al               ; Latch timer 0 command
+        out     43h,al              ; Latch timer
+        in      al,42h              ; least significant byte
+        mov     ah,al
+        in      al,42h              ; most significant byte
+        xchg    ah,al
+        and     eax,0FFFFh
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; exitTimer
+;----------------------------------------------------------------------------
+; Stops the 8253 timer 2 (PC speaker) counting
+;----------------------------------------------------------------------------
+cprocstatic exitTimer
+
+; Stop timer 2 from counting
+
+        push    eax
+        in      al,61h
+        and     al,0FEh
+        out     61h,al
+        
+; Some programs have a problem if we change the control port; better change it
+; to something they expect (mode 3 - square wave generator)...
+        mov     al,0B6h
+        out     43h,al
+        
+        pop     eax
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int _EVT_readJoyAxis(int jmask,int *axis);
+;----------------------------------------------------------------------------
+; Function to poll the joystick to read the current axis positions.
+;----------------------------------------------------------------------------
+cprocstart  _EVT_readJoyAxis
+
+        ARG     jmask:UINT, axis:DPTR
+
+        LOCAL   firstTick:UINT, lastTick:UINT, totalTicks:UINT = LocalSize
+
+        enter_c
+
+        mov     ebx,[jmask]
+        mov     edi,[axis]
+        mov     ecx,(1193180/100)
+        and     ebx,01111b          ; Mask out supported axes
+        mov     dx,201h             ; DX := joystick I/O port
+        call    initTimer           ; Start timer 2 counting
+        call    readTimer           ; Returns counter in EAX
+        mov     [lastTick],eax
+
+@@WaitStable:
+        in      al,dx
+        and     al,bl               ; Wait for the axes in question to be
+        jz      @@Stable            ;  done reading...
+        call    readTimer           ; Returns counter in EAX
+        xchg    eax,[lastTick]
+        cmp     eax,[lastTick]
+        jb      @@1
+        sub     eax,[lastTick]
+@@1:    add     [totalTicks],eax
+        cmp     [totalTicks],ecx    ; Check for timeout
+        jae     @@Stable
+        jmp     @@WaitStable
+
+@@Stable:
+        mov     al,0FFh
+        out     dx,al               ; Start joystick reading
+        call    initTimer           ; Start timer 2 counting
+        call    readTimer           ; Returns counter in EAX
+        mov     [firstTick],eax     ; Store initial count
+        mov     [lastTick],eax
+        mov     [DWORD totalTicks],0
+        cli
+
+@@PollLoop:
+        in      al,dx               ; Read Joystick port
+        not     al
+        and     al,bl               ; Mask off channels we don't want to read
+        jnz     @@AxisFlipped       ; See if any of the channels flipped
+        call    readTimer           ; Returns counter in EAX
+        xchg    eax,[lastTick]
+        cmp     eax,[lastTick]
+        jb      @@2
+        sub     eax,[lastTick]
+@@2:    add     [totalTicks],eax
+        cmp     [totalTicks],ecx    ; Check for timeout
+        jae     @@TimedOut
+        jmp     @@PollLoop
+
+@@AxisFlipped:
+        xor     esi,esi
+        mov     ah,1
+        test    al,ah
+        jnz     @@StoreCount        ; Joystick 1, X axis flipped
+        add     esi,4
+        mov     ah,2
+        test    al,ah
+        jnz     @@StoreCount        ; Joystick 1, Y axis flipped
+        add     esi,4
+        mov     ah,4
+        test    al,ah
+        jnz     @@StoreCount        ; Joystick 2, X axis flipped
+        add     esi,4               ; Joystick 2, Y axis flipped
+        mov     ah,8
+
+@@StoreCount:
+        or      bh,ah               ; Indicate this axis is active
+        xor     bl,ah               ; Unmark the channels that just tripped
+        call    readTimer           ; Returns counter in EAX
+        xchg    eax,[lastTick]
+        cmp     eax,[lastTick]
+        jb      @@3
+        sub     eax,[lastTick]
+@@3:    add     [totalTicks],eax
+        mov     eax,[totalTicks]
+        mov     [edi+esi],eax       ; Record the time this channel flipped
+        cmp     bl,0                ; If there are more channels to read,
+        jne     @@PollLoop          ;   keep looping
+
+@@TimedOut:
+        sti
+        call    exitTimer           ; Stop timer 2 counting
+        movzx   eax,bh              ; Return the mask of working axes
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int _EVT_readJoyButtons(void);
+;----------------------------------------------------------------------------
+; Function to poll the current joystick buttons
+;----------------------------------------------------------------------------
+cprocstart  _EVT_readJoyButtons
+
+        mov     dx,0201h
+        in      al,dx
+        shr     al,4
+        not     al
+        and     eax,0Fh
+        ret
+
+cprocend
+
+endcodeseg  _joy
+
+endif
+
+        END                         ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm
new file mode 100755
index 0000000..1e0a696
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm
@@ -0,0 +1,272 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: 16/32 bit Ring 0 device driver
+;*
+;* Description: Assembler support routines for the Memory Type Range Register
+;*              (MTRR) module.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+header      _mtrr               ; Set up memory model
+
+begdataseg  _mtrr
+
+ifdef   DOS4GW
+    cextern _PM_haveCauseWay,UINT
+endif
+
+enddataseg  _mtrr
+
+begcodeseg  _mtrr               ; Start of code segment
+
+P586
+
+;----------------------------------------------------------------------------
+; ibool _MTRR_isRing0(void);
+;----------------------------------------------------------------------------
+; Checks to see if we are running at ring 0. This check is only relevant
+; for 32-bit DOS4GW and compatible programs. If we are not running under
+; DOS4GW, then we simply assume we are a ring 0 device driver.
+;----------------------------------------------------------------------------
+cprocnear   _MTRR_isRing0
+
+; Are we running under CauseWay?
+
+ifdef   DOS4GW
+        enter_c
+        mov     ax,cs
+        and     eax,3
+        xor     eax,3
+        jnz     @@Exit
+
+; CauseWay runs the apps at ring 3, but implements support for specific
+; ring 0 instructions that we need to get stuff done under real DOS.
+
+        mov     eax,1
+        cmp     [UINT _PM_haveCauseWay],0
+        jnz     @@Exit
+@@Fail: xor     eax,eax
+@@Exit: leave_c
+        ret
+else
+ifdef __SMX32__
+        mov     eax,1                   ; SMX is ring 0!
+        ret
+else
+ifdef __VXD__
+        mov     eax,1                   ; VxD is ring 0!
+        ret
+else
+ifdef __NT_DRIVER__
+        mov     eax,1                   ; NT/W2K is ring 0!
+        ret
+else
+else
+        xor     eax,eax                 ; Assume ring 3 for 32-bit DOS
+        ret
+endif
+endif
+endif
+endif
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _MTRR_disableInt(void);
+;----------------------------------------------------------------------------
+; Return processor interrupt status and disable interrupts.
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_disableInt
+
+        pushfd                  ; Put flag word on stack
+        cli                     ; Disable interrupts!
+        pop     eax             ; deposit flag word in return register
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _MTRR_restoreInt(ulong ps);
+;----------------------------------------------------------------------------
+; Restore processor interrupt status.
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_restoreInt
+
+        ARG     ps:ULONG
+
+        push    ebp
+        mov     ebp,esp         ; Set up stack frame
+        mov     ecx,[ps]
+        test    ecx,200h        ; SMP safe interrupt flag restore!
+        jz      @@1
+        sti
+@@1:    pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _MTRR_saveCR4(void);
+;----------------------------------------------------------------------------
+; Save the value of CR4 and clear the Page Global Enable (bit 7). We also
+; disable and flush the caches.
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_saveCR4
+
+        enter_c
+
+; Save value of CR4 and clear Page Global Enable (bit 7)
+
+        mov     ebx,cr4
+        mov     eax,ebx
+        and     al,7Fh
+        mov     cr4,eax
+
+; Disable and flush caches
+
+        mov     eax,cr0
+        or      eax,40000000h
+        wbinvd
+        mov     cr0,eax
+        wbinvd
+
+; Return value from CR4
+
+        mov     eax,ebx
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _MTRR_restoreCR4(ulong cr4Val)
+;----------------------------------------------------------------------------
+; Save the value of CR4 and clear the Page Global Enable (bit 7). We also
+; disable and flush the caches.
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_restoreCR4
+
+        ARG     cr4Val:ULONG
+
+        enter_c
+
+; Enable caches
+
+        mov     eax,cr0
+        and     eax,0BFFFFFFFh
+        mov     cr0,eax
+        mov     eax,[cr4Val]
+        mov     cr4,eax
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uchar _MTRR_getCx86(uchar reg);
+;----------------------------------------------------------------------------
+; Read a Cyrix CPU indexed register
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_getCx86
+
+        ARG     reg:UCHAR
+
+        enter_c
+        mov     al,[reg]
+        out     22h,al
+        in      al,23h
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uchar _MTRR_setCx86(uchar reg,uchar val);
+;----------------------------------------------------------------------------
+; Write a Cyrix CPU indexed register
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_setCx86
+
+        ARG     reg:UCHAR, val:UCHAR
+
+        enter_c
+        mov     al,[reg]
+        out     22h,al
+        mov     al,[val]
+        out     23h,al
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _MTRR_readMSR(uong reg, ulong FAR *eax, ulong FAR *edx);
+;----------------------------------------------------------------------------
+; Writes the specific Machine Status Register used on the newer Intel
+; Pentium Pro and Pentium II motherboards.
+;----------------------------------------------------------------------------
+cprocnear   _MTRR_readMSR
+
+        ARG     reg:ULONG, v_eax:DPTR, v_edx:DPTR
+
+        enter_c
+        mov     ecx,[reg]
+        rdmsr
+        mov     ebx,[v_eax]
+        mov     [ebx],eax
+        mov     ebx,[v_edx]
+        mov     [ebx],edx
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _MTRR_writeMSR(uong reg, ulong eax, ulong edx);
+;----------------------------------------------------------------------------
+; Writes the specific Machine Status Register used on the newer Intel
+; Pentium Pro and Pentium II motherboards.
+;----------------------------------------------------------------------------
+cprocnear   _MTRR_writeMSR
+
+        ARG     reg:ULONG, v_eax:ULONG, v_edx:ULONG
+
+        enter_c
+        mov     ecx,[reg]
+        mov     eax,[v_eax]
+        mov     edx,[v_edx]
+        wrmsr
+        leave_c
+        ret
+
+cprocend
+
+endcodeseg  _mtrr
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm
new file mode 100755
index 0000000..5b8dbcc
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm
@@ -0,0 +1,358 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: Any
+;*
+;* Description: Helper assembler functions for PCI access module.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+header  _pcilib
+
+begcodeseg  _pcilib
+
+ifdef flatmodel
+
+;----------------------------------------------------------------------------
+; uchar _ASMAPI _BIOS32_service(
+;   ulong service,
+;   ulong func,
+;   ulong *physBase,
+;   ulong *length,
+;   ulong *serviceOffset,
+;   PCIBIOS_entry entry);
+;----------------------------------------------------------------------------
+; Call the BIOS32 services directory
+;----------------------------------------------------------------------------
+cprocstart   _BIOS32_service
+
+        ARG     service:ULONG, func:ULONG, physBase:DPTR, len:DPTR, off:DPTR, entry:QWORD
+
+        enter_c
+        mov     eax,[service]
+        mov     ebx,[func]
+ifdef   USE_NASM
+        call far dword [entry]
+else
+        call    [FWORD entry]
+endif
+        mov     esi,[physBase]
+        mov     [esi],ebx
+        mov     esi,[len]
+        mov     [esi],ecx
+        mov     esi,[off]
+        mov     [esi],edx
+        leave_c
+        ret
+
+cprocend
+
+endif
+
+;----------------------------------------------------------------------------
+; ushort _ASMAPI _PCIBIOS_isPresent(ulong i_eax,ulong *o_edx,ushort *oeax,
+;   uchar *o_cl,PCIBIOS_entry entry)
+;----------------------------------------------------------------------------
+; Call the PCI BIOS to determine if it is present.
+;----------------------------------------------------------------------------
+cprocstart   _PCIBIOS_isPresent
+
+        ARG     i_eax:ULONG, o_edx:DPTR, oeax:DPTR, o_cl:DPTR, entry:QWORD
+
+        enter_c
+        mov     eax,[i_eax]
+ifdef   flatmodel
+ifdef   USE_NASM
+        call far dword [entry]
+else
+        call    [FWORD entry]
+endif
+else
+        int     1Ah
+endif
+        _les    _si,[o_edx]
+        mov     [_ES _si],edx
+        _les    _si,[oeax]
+        mov     [_ES _si],ax
+        _les    _si,[o_cl]
+        mov     [_ES _si],cl
+        mov     ax,bx
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _PCIBIOS_service(ulong r_eax,ulong r_ebx,ulong r_edi,ulong r_ecx,
+;   PCIBIOS_entry entry)
+;----------------------------------------------------------------------------
+; Call the PCI BIOS services, either via the 32-bit protected mode entry
+; point or via the Int 1Ah 16-bit interrupt.
+;----------------------------------------------------------------------------
+cprocstart   _PCIBIOS_service
+
+        ARG     r_eax:ULONG, r_ebx:ULONG, r_edi:ULONG, r_ecx:ULONG, entry:QWORD
+
+        enter_c
+        mov     eax,[r_eax]
+        mov     ebx,[r_ebx]
+        mov     edi,[r_edi]
+        mov     ecx,[r_ecx]
+ifdef   flatmodel
+ifdef   USE_NASM
+        call far dword [entry]
+else
+        call    [FWORD entry]
+endif
+else
+        int     1Ah
+endif
+        mov     eax,ecx
+ifndef  flatmodel
+        shld    edx,eax,16      ; Return result in DX:AX
+endif
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int _PCIBIOS_getRouting(PCIRoutingOptionsBuffer *buf,PCIBIOS_entry entry);
+;----------------------------------------------------------------------------
+; Get the routing options for PCI devices
+;----------------------------------------------------------------------------
+cprocstart   _PCIBIOS_getRouting
+
+        ARG     buf:DPTR, entry:QWORD
+
+        enter_c
+        mov     eax,0B10Eh
+        mov     bx,0
+        _les    _di,[buf]
+ifdef   flatmodel
+ifdef   USE_NASM
+        call far dword [entry]
+else
+        call    [FWORD entry]
+endif
+else
+        int     1Ah
+endif
+        movzx   eax,ah
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ibool _PCIBIOS_setIRQ(int busDev,int intPin,int IRQ,PCIBIOS_entry entry);
+;----------------------------------------------------------------------------
+; Change the IRQ routing for the PCI device
+;----------------------------------------------------------------------------
+cprocstart   _PCIBIOS_setIRQ
+
+        ARG     busDev:UINT, intPin:UINT, IRQ:UINT, entry:QWORD
+
+        enter_c
+        mov     eax,0B10Fh
+        mov     bx,[USHORT busDev]
+        mov     cl,[BYTE intPin]
+        mov     ch,[BYTE IRQ]
+ifdef   flatmodel
+ifdef   USE_NASM
+        call far dword [entry]
+else
+        call    [FWORD entry]
+endif
+else
+        int     1Ah
+endif
+        mov     eax,1
+        jnc     @@1
+        xor     eax,eax         ; Function failed!
+@@1:    leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _PCIBIOS_specialCycle(int bus,ulong data,PCIBIOS_entry entry);
+;----------------------------------------------------------------------------
+; Generate a special cycle via the PCI BIOS.
+;----------------------------------------------------------------------------
+cprocstart   _PCIBIOS_specialCycle
+
+        ARG     bus:UINT, data:ULONG, entry:QWORD
+
+        enter_c
+        mov     eax,0B106h
+        mov     bh,[BYTE bus]
+        mov     ecx,[data]
+ifdef   flatmodel
+ifdef   USE_NASM
+        call far dword [entry]
+else
+        call    [FWORD entry]
+endif
+else
+        int     1Ah
+endif
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ushort _PCI_getCS(void)
+;----------------------------------------------------------------------------
+cprocstart   _PCI_getCS
+
+        mov     ax,cs
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_inpb(int port)
+;----------------------------------------------------------------------------
+; Reads a byte from the specified port
+;----------------------------------------------------------------------------
+cprocstart  PM_inpb
+
+        ARG     port:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        xor     _ax,_ax
+        mov     _dx,[port]
+        in      al,dx
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_inpw(int port)
+;----------------------------------------------------------------------------
+; Reads a word from the specified port
+;----------------------------------------------------------------------------
+cprocstart  PM_inpw
+
+        ARG     port:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        xor     _ax,_ax
+        mov     _dx,[port]
+        in      ax,dx
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong PM_inpd(int port)
+;----------------------------------------------------------------------------
+; Reads a word from the specified port
+;----------------------------------------------------------------------------
+cprocstart  PM_inpd
+
+        ARG     port:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        mov     _dx,[port]
+        in      eax,dx
+ifndef flatmodel
+        shld    edx,eax,16      ; DX:AX = result
+endif
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_outpb(int port,int value)
+;----------------------------------------------------------------------------
+; Write a byte to the specified port.
+;----------------------------------------------------------------------------
+cprocstart  PM_outpb
+
+        ARG     port:UINT, value:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        mov     _dx,[port]
+        mov     _ax,[value]
+        out     dx,al
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_outpw(int port,int value)
+;----------------------------------------------------------------------------
+; Write a word to the specified port.
+;----------------------------------------------------------------------------
+cprocstart  PM_outpw
+
+        ARG     port:UINT, value:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        mov     _dx,[port]
+        mov     _ax,[value]
+        out     dx,ax
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_outpd(int port,ulong value)
+;----------------------------------------------------------------------------
+; Write a word to the specified port.
+;----------------------------------------------------------------------------
+cprocstart  PM_outpd
+
+        ARG     port:UINT, value:ULONG
+
+        push    _bp
+        mov     _bp,_sp
+        mov     _dx,[port]
+        mov     eax,[value]
+        out     dx,eax
+        pop     _bp
+        ret
+
+cprocend
+
+endcodeseg  _pcilib
+
+        END
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/agp.c b/board/MAI/bios_emulator/scitech/src/pm/common/agp.c
new file mode 100755
index 0000000..d53bc88
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/agp.c
@@ -0,0 +1,189 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Ring 0 device driver
+*
+* Description:  Generic module to implement AGP support functions using the
+*               SciTech Nucleus AGP support drivers. If the OS provides
+*               native AGP support, this module should *NOT* be used. Instead
+*               wrappers should be placed around the OS support functions
+*               to implement this functionality.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#ifndef REALMODE
+#include "nucleus/agp.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+static AGP_devCtx       *agp;
+static AGP_driverFuncs  driver;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+RETURNS:
+Size of AGP aperture in MB on success, 0 on failure.
+
+REMARKS:
+This function initialises the AGP driver in the system and returns the
+size of the available AGP aperture in megabytes.
+****************************************************************************/
+ulong PMAPI PM_agpInit(void)
+{
+    if ((agp = AGP_loadDriver(0)) == NULL)
+	return 0;
+    driver.dwSize = sizeof(driver);
+    if (!agp->QueryFunctions(AGP_GET_DRIVERFUNCS,&driver))
+	return 0;
+    switch (driver.GetApertureSize()) {
+	case agpSize4MB:    return 4;
+	case agpSize8MB:    return 8;
+	case agpSize16MB:   return 16;
+	case agpSize32MB:   return 32;
+	case agpSize64MB:   return 64;
+	case agpSize128MB:  return 128;
+	case agpSize256MB:  return 256;
+	case agpSize512MB:  return 512;
+	case agpSize1GB:    return 1024;
+	case agpSize2GB:    return 2048;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+This function closes down the loaded AGP driver.
+****************************************************************************/
+void PMAPI PM_agpExit(void)
+{
+    AGP_unloadDriver(agp);
+}
+
+/****************************************************************************
+PARAMETERS:
+numPages    - Number of memory pages that should be reserved
+type        - Type of memory to allocate
+physContext - Returns the physical context handle for the mapping
+physAddr    - Returns the physical address for the mapping
+
+RETURNS:
+True on success, false on failure.
+
+REMARKS:
+This function reserves a range of physical memory addresses on the system
+bus which the AGP controller will respond to. If this function succeeds,
+the AGP controller can respond to the reserved physical address range on
+the bus. However you must first call AGP_commitPhysical to cause this memory
+to actually be committed for use before it can be accessed.
+****************************************************************************/
+ibool PMAPI PM_agpReservePhysical(
+    ulong numPages,
+    int type,
+    void **physContext,
+    PM_physAddr *physAddr)
+{
+    switch (type) {
+	case PM_agpUncached:
+	    type = agpUncached;
+	    break;
+	case PM_agpWriteCombine:
+	    type = agpWriteCombine;
+	    break;
+	case PM_agpIntelDCACHE:
+	    type = agpIntelDCACHE;
+	    break;
+	default:
+	    return false;
+	}
+    return driver.ReservePhysical(numPages,type,physContext,physAddr) == nOK;
+}
+
+/****************************************************************************
+PARAMETERS:
+physContext - Physical AGP context to release
+
+RETURNS:
+True on success, false on failure.
+
+REMARKS:
+This function releases a range of physical memory addresses on the system
+bus which the AGP controller will respond to. All committed memory for
+the physical address range covered by the context will be released.
+****************************************************************************/
+ibool PMAPI PM_agpReleasePhysical(
+    void *physContext)
+{
+    return driver.ReleasePhysical(physContext) == nOK;
+}
+
+/****************************************************************************
+PARAMETERS:
+physContext - Physical AGP context to commit memory for
+numPages    - Number of pages to be committed
+startOffset - Offset in pages into the reserved physical context
+physAddr    - Returns the physical address of the committed memory
+
+RETURNS:
+True on success, false on failure.
+
+REMARKS:
+This function commits into the specified physical context that was previously
+reserved by a call to ReservePhysical. You can use the startOffset and
+numPages parameters to only commit portions of the reserved memory range at
+a time.
+****************************************************************************/
+ibool PMAPI PM_agpCommitPhysical(
+    void *physContext,
+    ulong numPages,
+    ulong startOffset,
+    PM_physAddr *physAddr)
+{
+    return driver.CommitPhysical(physContext,numPages,startOffset,physAddr) == nOK;
+}
+
+/****************************************************************************
+PARAMETERS:
+physContext - Physical AGP context to free memory for
+numPages    - Number of pages to be freed
+startOffset - Offset in pages into the reserved physical context
+
+RETURNS:
+True on success, false on failure.
+
+REMARKS:
+This function frees memory previously committed by the CommitPhysical
+function. Note that you can free a portion of a memory range that was
+previously committed if you wish.
+****************************************************************************/
+ibool PMAPI PM_agpFreePhysical(
+    void *physContext,
+    ulong numPages,
+    ulong startOffset)
+{
+    return driver.FreePhysical(physContext,numPages,startOffset) == nOK;
+}
+
+#endif  /* !REALMODE */
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c b/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c
new file mode 100755
index 0000000..36867bd
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c
@@ -0,0 +1,449 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Direct keyboard event handling module. This module contains
+*               code to process raw scan code information, convert it to
+*               virtual scan codes and do code page translation to ASCII
+*               for different international keyboard layouts.
+*
+****************************************************************************/
+
+/*---------------------------- Implementation -----------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Keyboard scan code to translate
+table       - Code page table to search
+count       - Number of entries in the code page table
+
+REMARKS:
+This function translates the scan codes from keyboard scan codes to ASCII
+codes using a binary search on the code page table.
+****************************************************************************/
+static uchar translateScan(
+    uchar scanCode,
+    codepage_entry_t *table,
+    int count)
+{
+    codepage_entry_t    *test;
+    int                 n,pivot,val;
+
+    for (n = count; n > 0; ) {
+	pivot = n >> 1;
+	test = table + pivot;
+	val = scanCode - test->scanCode;
+	if (val < 0)
+	    n = pivot;
+	else if (val == 0)
+	    return test->asciiCode;
+	else {
+	    table = test + 1;
+	    n -= pivot + 1;
+	    }
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+{secret}
+****************************************************************************/
+void _EVT_maskKeyCode(
+    event_t *evt)
+{
+    int ascii,scan = EVT_scanCode(evt->message);
+
+    evt->message &= ~0xFF;
+    if (evt->modifiers & EVT_NUMLOCK) {
+	if ((ascii = translateScan(scan,EVT.codePage->numPad,EVT.codePage->numPadLen)) != 0) {
+	    evt->message |= ascii;
+	    return;
+	    }
+	}
+    if (evt->modifiers & EVT_CTRLSTATE) {
+	evt->message |= translateScan(scan,EVT.codePage->ctrl,EVT.codePage->ctrlLen);
+	return;
+	}
+    if (evt->modifiers & EVT_CAPSLOCK) {
+	if (evt->modifiers & EVT_SHIFTKEY) {
+	    if ((ascii = translateScan(scan,EVT.codePage->shiftCaps,EVT.codePage->shiftCapsLen)) != 0) {
+		evt->message |= ascii;
+		return;
+		}
+	    }
+	else {
+	    if ((ascii = translateScan(scan,EVT.codePage->caps,EVT.codePage->capsLen)) != 0) {
+		evt->message |= ascii;
+		return;
+		}
+	    }
+	}
+    if (evt->modifiers & EVT_SHIFTKEY) {
+	if ((ascii = translateScan(scan,EVT.codePage->shift,EVT.codePage->shiftLen)) != 0) {
+	    evt->message |= ascii;
+	    return;
+	    }
+	}
+    evt->message |= translateScan(scan,EVT.codePage->normal,EVT.codePage->normalLen);
+}
+
+/****************************************************************************
+REMARKS:
+Returns true if the key with the specified scan code is being held down.
+****************************************************************************/
+static ibool _EVT_isKeyDown(
+    uchar scanCode)
+{
+    if (scanCode > 0x7F)
+	return false;
+    else
+	return EVT.keyTable[scanCode] != 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+what        - Event code
+message     - Event message (ASCII code and scan code)
+
+REMARKS:
+Adds a new keyboard event to the event queue. This routine is called from
+within the keyboard interrupt subroutine!
+
+NOTE:   Interrupts are OFF when this routine is called by the keyboard ISR,
+	and we leave them OFF the entire time.
+****************************************************************************/
+static void addKeyEvent(
+    uint what,
+    uint message)
+{
+    event_t evt;
+
+    if (EVT.count < EVENTQSIZE) {
+	/* Save information in event record */
+	evt.when = _EVT_getTicks();
+	evt.what = what;
+	evt.message = message | 0x10000UL;
+	evt.where_x = 0;
+	evt.where_y = 0;
+	evt.relative_x = 0;
+	evt.relative_y = 0;
+	evt.modifiers = EVT.keyModifiers;
+	if (evt.what == EVT_KEYREPEAT) {
+	    if (EVT.oldKey != -1)
+		EVT.evtq[EVT.oldKey].message += 0x10000UL;
+	    else {
+		EVT.oldKey = EVT.freeHead;
+		addEvent(&evt);         /* Add to tail of event queue   */
+		}
+	    }
+	else {
+#ifdef __QNX__
+	    _EVT_maskKeyCode(&evt);
+#endif
+	    addEvent(&evt);             /* Add to tail of event queue   */
+	    }
+	EVT.oldMove = -1;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+This function waits for the keyboard controller to set the ready-for-write
+bit.
+****************************************************************************/
+static int kbWaitForWriteReady(void)
+{
+    int timeout = 8192;
+    while ((timeout > 0) && (PM_inpb(0x64) & 0x02))
+	timeout--;
+    return (timeout > 0);
+}
+
+/****************************************************************************
+REMARKS:
+This function waits for the keyboard controller to set the ready-for-read
+bit.
+****************************************************************************/
+static int kbWaitForReadReady(void)
+{
+    int timeout = 8192;
+    while ((timeout > 0) && (!(PM_inpb(0x64) & 0x01)))
+	timeout--;
+    return (timeout > 0);
+}
+
+/****************************************************************************
+PARAMETERS:
+data    - Data to send to the keyboard
+
+REMARKS:
+This function sends a data byte to the keyboard controller.
+****************************************************************************/
+static int kbSendData(
+    uchar data)
+{
+    int resends = 4;
+    int timeout, temp;
+
+    do {
+	if (!kbWaitForWriteReady())
+	    return 0;
+	PM_outpb(0x60,data);
+	timeout = 8192;
+	while (--timeout > 0) {
+	    if (!kbWaitForReadReady())
+		return 0;
+	    temp = PM_inpb(0x60);
+	    if (temp == 0xFA)
+		return 1;
+	    if (temp == 0xFE)
+		break;
+	    }
+	} while ((resends-- > 0) && (timeout > 0));
+    return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+modifiers   - Keyboard modifier flags
+
+REMARKS:
+This function re-programs the LED's on the keyboard to the values stored
+in the passed in modifier flags. If the 'allowLEDS' flag is false, this
+function does nothing.
+****************************************************************************/
+static void setLEDS(
+    uint modifiers)
+{
+    if (EVT.allowLEDS) {
+	if (!kbSendData(0xED) || !kbSendData((modifiers>>9) & 7)) {
+	    kbSendData(0xF4);
+	    }
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Function to process raw scan codes read from the keyboard controller.
+
+NOTE:   Interrupts are OFF when this routine is called by the keyboard ISR,
+	and we leave them OFF the entire time.
+{secret}
+****************************************************************************/
+void processRawScanCode(
+    int scan)
+{
+    static int  pauseLoop = 0;
+    static int  extended = 0;
+    int         what;
+
+    if (pauseLoop) {
+	/* Skip scan codes until the pause key sequence has been read */
+	pauseLoop--;
+	}
+    else if (scan == 0xE0) {
+	/* This signals the start of an extended scan code sequence */
+	extended = 1;
+	}
+    else if (scan == 0xE1) {
+	/* The Pause key sends a strange scan code sequence, which is:
+	 *
+	 *  E1 1D 52 E1 9D D2
+	 *
+	 * However there is never any release code nor any auto-repeat for
+	 * this key. For this reason we simply ignore the key and skip the
+	 * next 5 scan codes read from the keyboard.
+	 */
+	pauseLoop = 5;
+	}
+    else {
+	/* Process the scan code normally (it may be an extended code
+	 * however!). Bit 7 means key was released, and bits 0-6 are the
+	 * scan code.
+	 */
+	what = (scan & 0x80) ? EVT_KEYUP : EVT_KEYDOWN;
+	scan &= 0x7F;
+	if (extended) {
+	    extended = 0;
+	    if (scan == 0x2A || scan == 0x36) {
+		/* Ignore these extended scan code sequences. These are
+		 * used by the keyboard controller to wrap around certain
+		 * key sequences for the keypad (and when NUMLOCK is down
+		 * internally).
+		 */
+		return;
+		}
+
+	    /* Convert extended codes for key sequences that we map to
+	     * virtual scan codes so the user can detect them in their
+	     * code.
+	     */
+	    switch (scan) {
+		case KB_leftCtrl:   scan = KB_rightCtrl;    break;
+		case KB_leftAlt:    scan = KB_rightAlt;     break;
+		case KB_divide:     scan = KB_padDivide;    break;
+		case KB_enter:      scan = KB_padEnter;     break;
+		case KB_padTimes:   scan = KB_sysReq;       break;
+		}
+	    }
+	else {
+	    /* Convert regular scan codes for key sequences that we map to
+	     * virtual scan codes so the user can detect them in their
+	     * code.
+	     */
+	    switch (scan) {
+		case KB_left:       scan = KB_padLeft;      break;
+		case KB_right:      scan = KB_padRight;     break;
+		case KB_up:         scan = KB_padUp;        break;
+		case KB_down:       scan = KB_padDown;      break;
+		case KB_insert:     scan = KB_padInsert;    break;
+		case KB_delete:     scan = KB_padDelete;    break;
+		case KB_home:       scan = KB_padHome;      break;
+		case KB_end:        scan = KB_padEnd;       break;
+		case KB_pageUp:     scan = KB_padPageUp;    break;
+		case KB_pageDown:   scan = KB_padPageDown;  break;
+		}
+	    }
+
+	/* Determine if the key is an UP, DOWN or REPEAT and maintain the
+	 * up/down status of all keys in our global key array.
+	 */
+	if (what == EVT_KEYDOWN) {
+	    if (EVT.keyTable[scan])
+		what = EVT_KEYREPEAT;
+	    else
+		EVT.keyTable[scan] = scan;
+	    }
+	else {
+	    EVT.keyTable[scan] = 0;
+	    }
+
+	/* Handle shift key modifiers */
+	if (what != EVT_KEYREPEAT) {
+	    switch (scan) {
+		case KB_capsLock:
+		    if (what == EVT_KEYDOWN)
+			EVT.keyModifiers ^= EVT_CAPSLOCK;
+		    setLEDS(EVT.keyModifiers);
+		    break;
+		case KB_numLock:
+		    if (what == EVT_KEYDOWN)
+			EVT.keyModifiers ^= EVT_NUMLOCK;
+		    setLEDS(EVT.keyModifiers);
+		    break;
+		case KB_scrollLock:
+		    if (what == EVT_KEYDOWN)
+			EVT.keyModifiers ^= EVT_SCROLLLOCK;
+		    setLEDS(EVT.keyModifiers);
+		    break;
+		case KB_leftShift:
+		    if (what == EVT_KEYUP)
+			EVT.keyModifiers &= ~EVT_LEFTSHIFT;
+		    else
+			EVT.keyModifiers |= EVT_LEFTSHIFT;
+		    break;
+		case KB_rightShift:
+		    if (what == EVT_KEYUP)
+			EVT.keyModifiers &= ~EVT_RIGHTSHIFT;
+		    else
+			EVT.keyModifiers |= EVT_RIGHTSHIFT;
+		    break;
+		case KB_leftCtrl:
+		    if (what == EVT_KEYUP)
+			EVT.keyModifiers &= ~EVT_LEFTCTRL;
+		    else
+			EVT.keyModifiers |= EVT_LEFTCTRL;
+		    break;
+		case KB_rightCtrl:
+		    if (what == EVT_KEYUP)
+			EVT.keyModifiers &= ~EVT_RIGHTCTRL;
+		    else
+			EVT.keyModifiers |= EVT_RIGHTCTRL;
+		    break;
+		case KB_leftAlt:
+		    if (what == EVT_KEYUP)
+			EVT.keyModifiers &= ~EVT_LEFTALT;
+		    else
+			EVT.keyModifiers |= EVT_LEFTALT;
+		    break;
+		case KB_rightAlt:
+		    if (what == EVT_KEYUP)
+			EVT.keyModifiers &= ~EVT_RIGHTALT;
+		    else
+			EVT.keyModifiers |= EVT_RIGHTALT;
+		    break;
+#ifdef SUPPORT_CTRL_ALT_DEL
+		case KB_delete:
+		    if ((EVT.keyModifiers & EVT_CTRLSTATE) && (EVT.keyModifiers & EVT_ALTSTATE))
+			Reboot();
+		    break;
+#endif
+		}
+	    }
+
+	/* Add the untranslated key code to the event queue. All
+	 * translation to ASCII from the key codes occurs when the key
+	 * is extracted from the queue, saving time in the low level
+	 * interrupt handler.
+	 */
+	addKeyEvent(what,scan << 8);
+	}
+}
+
+/****************************************************************************
+DESCRIPTION:
+Enables/disables the update of the keyboard LED status indicators.
+
+HEADER:
+event.h
+
+PARAMETERS:
+enable  - True to enable, false to disable
+
+REMARKS:
+Enables the update of the keyboard LED status indicators. Sometimes it may
+be convenient in the application to turn off the updating of the LED
+status indicators (such as if a game is using the CAPSLOCK key for some
+function). Passing in a value of FALSE to this function will turn off all
+the LEDS, and stop updating them when the internal status changes (note
+however that internally we still keep track of the toggle key status!).
+****************************************************************************/
+void EVTAPI EVT_allowLEDS(
+    ibool enable)
+{
+    EVT.allowLEDS = true;
+    if (enable)
+	setLEDS(EVT.keyModifiers);
+    else
+	setLEDS(0);
+    EVT.allowLEDS = enable;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c b/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c
new file mode 100755
index 0000000..83ef221
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c
@@ -0,0 +1,205 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Module for implementing the PM library overrideable memory
+*               allocator functions.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+void * (*__PM_malloc)(size_t size)              = malloc;
+void * (*__PM_calloc)(size_t nelem,size_t size) = calloc;
+void * (*__PM_realloc)(void *ptr,size_t size)   = realloc;
+void (*__PM_free)(void *p)                      = free;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+DESCRIPTION:
+Use local memory allocation routines.
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+malloc  - Pointer to new malloc routine to use
+calloc  - Pointer to new caalloc routine to use
+realloc - Pointer to new realloc routine to use
+free    - Pointer to new free routine to use
+
+REMARKS:
+Tells the PM library to use a set of user specified memory allocation
+routines instead of using the normal malloc/calloc/realloc/free standard
+C library functions. This is useful if you wish to use a third party
+debugging malloc library or perhaps a set of faster memory allocation
+functions with the PM library, or any apps that use the PM library (such as
+the MGL). Once you have registered your memory allocation routines, all
+calls to PM_malloc, PM_calloc, PM_realloc and PM_free will be revectored to
+your local memory allocation routines.
+
+This is also useful if you need to keep track of just how much physical
+memory your program has been using. You can use the PM_availableMemory
+function to find out how much physical memory is available when the program
+starts, and then you can use your own local memory allocation routines to
+keep track of how much memory has been used and freed.
+
+NOTE: This function should be called right at the start of your application,
+      before you initialise any other components or libraries.
+
+NOTE: Code compiled into Binary Portable DLL's and Drivers automatically
+      end up calling these functions via the BPD C runtime library.
+
+SEE ALSO:
+PM_malloc, PM_calloc, PM_realloc, PM_free, PM_availableMemory
+****************************************************************************/
+void PMAPI PM_useLocalMalloc(
+    void * (*malloc)(size_t size),
+    void * (*calloc)(size_t nelem,size_t size),
+    void * (*realloc)(void *ptr,size_t size),
+    void (*free)(void *p))
+{
+    __PM_malloc = malloc;
+    __PM_calloc = calloc;
+    __PM_realloc = realloc;
+    __PM_free = free;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Allocate a block of memory.
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+size    - Size of block to allocate in bytes
+
+RETURNS:
+Pointer to allocated block, or NULL if out of memory.
+
+REMARKS:
+Allocates a block of memory of length size. If you have changed the memory
+allocation routines with the PM_useLocalMalloc function, then calls to this
+function will actually make calls to the local memory allocation routines
+that you have registered.
+
+SEE ALSO:
+PM_calloc, PM_realloc, PM_free, PM_useLocalMalloc
+****************************************************************************/
+void * PMAPI PM_malloc(
+    size_t size)
+{
+    return __PM_malloc(size);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Allocate and clear a large memory block.
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+nelem   - number of contiguous size-byte units to allocate
+size    - size of unit in bytes
+
+RETURNS:
+Pointer to allocated memory if successful, NULL if out of memory.
+
+REMARKS:
+Allocates a block of memory of length (size * nelem), and clears the
+allocated area with zeros (0). If you have changed the memory allocation
+routines with the PM_useLocalMalloc function, then calls to this function
+will actually make calls to the local memory allocation routines that you
+have registered.
+
+SEE ALSO:
+PM_malloc, PM_realloc, PM_free, PM_useLocalMalloc
+****************************************************************************/
+void * PMAPI PM_calloc(
+    size_t nelem,
+    size_t size)
+{
+    return __PM_calloc(nelem,size);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Re-allocate a block of memory
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+ptr     - Pointer to block to resize
+size    - size of unit in bytes
+
+RETURNS:
+Pointer to allocated memory if successful, NULL if out of memory.
+
+REMARKS:
+This function reallocates a block of memory that has been previously been
+allocated to the new of size. The new size may be smaller or larger than
+the original block of memory. If you have changed the memory allocation
+routines with the PM_useLocalMalloc function, then calls to this function
+will actually make calls to the local memory allocation routines that you
+have registered.
+
+SEE ALSO:
+PM_malloc, PM_calloc, PM_free, PM_useLocalMalloc
+****************************************************************************/
+void * PMAPI PM_realloc(
+    void *ptr,
+    size_t size)
+{
+    return __PM_realloc(ptr,size);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Frees a block of memory.
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+p   - Pointer to memory block to free
+
+REMARKS:
+Frees a block of memory previously allocated with either PM_malloc,
+PM_calloc or PM_realloc.
+
+SEE ALSO:
+PM_malloc, PM_calloc, PM_realloc, PM_useLocalMalloc
+****************************************************************************/
+void PMAPI PM_free(
+    void *p)
+{
+    __PM_free(p);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c b/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c
new file mode 100755
index 0000000..eed5f45
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c
@@ -0,0 +1,867 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*               Heavily based on code copyright (C) Richard Gooch
+*
+* Language:     ANSI C
+* Environment:  32-bit Ring 0 device driver
+*
+* Description:  Generic Memory Type Range Register (MTRR) functions to
+*               manipulate the MTRR registers on supported CPU's. This code
+*               *must* run at ring 0, so you can't normally include this
+*               code directly in normal applications (the except is DOS4GW
+*               apps which run at ring 0 under real DOS). Thus this code
+*               will normally be compiled into a ring 0 device driver for
+*               the target operating system.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "ztimerc.h"
+#include "mtrr.h"
+
+#ifndef REALMODE
+
+/*--------------------------- Global variables ----------------------------*/
+
+/* Intel pre-defined MTRR registers */
+
+#define NUM_FIXED_RANGES        88
+#define INTEL_cap_MSR           0x0FE
+#define INTEL_defType_MSR       0x2FF
+#define INTEL_fix64K_00000_MSR  0x250
+#define INTEL_fix16K_80000_MSR  0x258
+#define INTEL_fix16K_A0000_MSR  0x259
+#define INTEL_fix4K_C0000_MSR   0x268
+#define INTEL_fix4K_C8000_MSR   0x269
+#define INTEL_fix4K_D0000_MSR   0x26A
+#define INTEL_fix4K_D8000_MSR   0x26B
+#define INTEL_fix4K_E0000_MSR   0x26C
+#define INTEL_fix4K_E8000_MSR   0x26D
+#define INTEL_fix4K_F0000_MSR   0x26E
+#define INTEL_fix4K_F8000_MSR   0x26F
+
+/* Macros to find the address of a paricular MSR register */
+
+#define INTEL_physBase_MSR(reg) (0x200 + 2 * (reg))
+#define INTEL_physMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+/* Cyrix CPU configuration register indexes */
+#define CX86_CCR0 0xC0
+#define CX86_CCR1 0xC1
+#define CX86_CCR2 0xC2
+#define CX86_CCR3 0xC3
+#define CX86_CCR4 0xE8
+#define CX86_CCR5 0xE9
+#define CX86_CCR6 0xEA
+#define CX86_DIR0 0xFE
+#define CX86_DIR1 0xFF
+#define CX86_ARR_BASE 0xC4
+#define CX86_RCR_BASE 0xDC
+
+/* Structure to maintain machine state while updating MTRR registers */
+
+typedef struct {
+    ulong   flags;
+    ulong   defTypeLo;
+    ulong   defTypeHi;
+    ulong   cr4Val;
+    ulong   ccr3;
+    } MTRRContext;
+
+static int      numMTRR = -1;
+static int      cpuFamily,cpuType,cpuStepping;
+static void     (*getMTRR)(uint reg,ulong *base,ulong *size,int *type) = NULL;
+static void     (*setMTRR)(uint reg,ulong base,ulong size,int type) = NULL;
+static int      (*getFreeRegion)(ulong base,ulong size) = NULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+RETURNS:
+Returns non-zero if we have the write-combining memory type
+****************************************************************************/
+static int MTRR_haveWriteCombine(void)
+{
+    ulong   config,dummy;
+
+    switch (cpuFamily) {
+	case CPU_AMD:
+	    if (cpuType < CPU_AMDAthlon) {
+		/* AMD K6-2 stepping 8 and later support the MTRR registers.
+		 * The earlier K6-2 steppings (300Mhz models) do not
+		 * support MTRR's.
+		 */
+		if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8))
+		    return 0;
+		return 1;
+		}
+	    /* Fall through for AMD Athlon which uses P6 style MTRR's */
+	case CPU_Intel:
+	    _MTRR_readMSR(INTEL_cap_MSR,&config,&dummy);
+	    return (config & (1 << 10));
+	case CPU_Cyrix:
+	    /* Cyrix 6x86 and later support the MTRR registers */
+	    if (cpuType < CPU_Cyrix6x86)
+		return 0;
+	    return 1;
+	}
+    return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+
+RETURNS:
+The index of the region on success, else -1 on error.
+
+REMARKS:
+Generic function to find the location of a free MTRR register to be used
+for creating a new mapping.
+****************************************************************************/
+static int GENERIC_getFreeRegion(
+    ulong base,
+    ulong size)
+{
+    int     i,ltype;
+    ulong   lbase,lsize;
+
+    for (i = 0; i < numMTRR; i++) {
+	getMTRR(i,&lbase,&lsize,&ltype);
+	if (lsize < 1)
+	    return i;
+	}
+    (void)base;
+    (void)size;
+    return -1;
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+
+RETURNS:
+The index of the region on success, else -1 on error.
+
+REMARKS:
+Generic function to find the location of a free MTRR register to be used
+for creating a new mapping.
+****************************************************************************/
+static int AMDK6_getFreeRegion(
+    ulong base,
+    ulong size)
+{
+    int     i,ltype;
+    ulong   lbase,lsize;
+
+    for (i = 0; i < numMTRR; i++) {
+	getMTRR(i,&lbase,&lsize,&ltype);
+	if (lsize < 1)
+	    return i;
+	}
+    (void)base;
+    (void)size;
+    return -1;
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+
+RETURNS:
+The index of the region on success, else -1 on error.
+
+REMARKS:
+Cyrix specific function to find the location of a free MTRR register to be
+used for creating a new mapping.
+****************************************************************************/
+static int CYRIX_getFreeRegion(
+    ulong base,
+    ulong size)
+{
+    int     i,ltype;
+    ulong   lbase, lsize;
+
+    if (size > 0x2000000UL) {
+	/* If we are to set up a region >32M then look at ARR7 immediately */
+	getMTRR(7,&lbase,&lsize,&ltype);
+	if (lsize < 1)
+	    return 7;
+	}
+    else {
+	/* Check ARR0-6 registers */
+	for (i = 0; i < 7; i++) {
+	    getMTRR(i,&lbase,&lsize,&ltype);
+	    if (lsize < 1)
+		return i;
+	    }
+	/* Try ARR7 but its size must be at least 256K */
+	getMTRR(7,&lbase,&lsize,&ltype);
+	if ((lsize < 1) && (size >= 0x40000))
+	    return i;
+	}
+    (void)base;
+    return -1;
+}
+
+/****************************************************************************
+PARAMETERS:
+c   - Place to store the machine context across the call
+
+REMARKS:
+Puts the processor into a state where MTRRs can be safely updated
+****************************************************************************/
+static void MTRR_beginUpdate(
+    MTRRContext *c)
+{
+    c->flags = _MTRR_disableInt();
+    if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) {
+	switch (cpuFamily) {
+	    case CPU_Intel:
+	    case CPU_AMD:
+		/* Disable MTRRs, and set the default type to uncached */
+		c->cr4Val = _MTRR_saveCR4();
+		_MTRR_readMSR(INTEL_defType_MSR,&c->defTypeLo,&c->defTypeHi);
+		_MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo & 0xF300UL,c->defTypeHi);
+		break;
+	    case CPU_Cyrix:
+		c->ccr3 = _MTRR_getCx86(CX86_CCR3);
+		_MTRR_setCx86(CX86_CCR3, (uchar)((c->ccr3 & 0x0F) | 0x10));
+		break;
+	    }
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+c   - Place to restore the machine context from
+
+REMARKS:
+Restores the processor after updating any of the registers
+****************************************************************************/
+static void MTRR_endUpdate(
+    MTRRContext *c)
+{
+    if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) {
+	PM_flushTLB();
+	switch (cpuFamily) {
+	    case CPU_Intel:
+	    case CPU_AMD:
+		_MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo,c->defTypeHi);
+		_MTRR_restoreCR4(c->cr4Val);
+		break;
+	    case CPU_Cyrix:
+		_MTRR_setCx86(CX86_CCR3,(uchar)c->ccr3);
+		break;
+	    }
+	}
+
+    /* Re-enable interrupts (if enabled previously) */
+    _MTRR_restoreInt(c->flags);
+}
+
+/****************************************************************************
+PARAMETERS:
+reg     - MTRR register to read
+base    - Place to store the starting physical base address of the region
+size    - Place to store the size in bytes of the region
+type    - Place to store the type of the MTRR register
+
+REMARKS:
+Intel specific function to read the value of a specific MTRR register.
+****************************************************************************/
+static void INTEL_getMTRR(
+    uint reg,
+    ulong *base,
+    ulong *size,
+    int *type)
+{
+    ulong hi,maskLo,baseLo;
+
+    _MTRR_readMSR(INTEL_physMask_MSR(reg),&maskLo,&hi);
+    if ((maskLo & 0x800) == 0) {
+	/* MTRR is disabled, so it is free */
+	*base = 0;
+	*size = 0;
+	*type = 0;
+	return;
+	}
+    _MTRR_readMSR(INTEL_physBase_MSR(reg),&baseLo,&hi);
+    maskLo = (maskLo & 0xFFFFF000UL);
+    *size = ~(maskLo - 1);
+    *base = (baseLo & 0xFFFFF000UL);
+    *type = (baseLo & 0xFF);
+}
+
+/****************************************************************************
+PARAMETERS:
+reg     - MTRR register to set
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+REMARKS:
+Intel specific function to set the value of a specific MTRR register to
+the passed in base, size and type.
+****************************************************************************/
+static void INTEL_setMTRR(
+    uint reg,
+    ulong base,
+    ulong size,
+    int type)
+{
+    MTRRContext c;
+
+    MTRR_beginUpdate(&c);
+    if (size == 0) {
+	/* The invalid bit is kept in the mask, so we simply clear the
+	 * relevant mask register to disable a range.
+	 */
+	_MTRR_writeMSR(INTEL_physMask_MSR(reg),0,0);
+	}
+    else {
+	_MTRR_writeMSR(INTEL_physBase_MSR(reg),base | type,0);
+	_MTRR_writeMSR(INTEL_physMask_MSR(reg),~(size - 1) | 0x800,0);
+	}
+    MTRR_endUpdate(&c);
+}
+
+/****************************************************************************
+REMARKS:
+Disabled banked write combing for Intel processors. We always disable this
+because it invariably causes problems with older hardware.
+****************************************************************************/
+static void INTEL_disableBankedWriteCombine(void)
+{
+    MTRRContext c;
+
+    MTRR_beginUpdate(&c);
+    _MTRR_writeMSR(INTEL_fix16K_A0000_MSR,0,0);
+    MTRR_endUpdate(&c);
+}
+
+/****************************************************************************
+PARAMETERS:
+reg     - MTRR register to set
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+REMARKS:
+Intel specific function to set the value of a specific MTRR register to
+the passed in base, size and type.
+****************************************************************************/
+static void AMD_getMTRR(
+    uint reg,
+    ulong *base,
+    ulong *size,
+    int *type)
+{
+    ulong   low,high;
+
+    /*  Upper dword is region 1, lower is region 0  */
+    _MTRR_readMSR(0xC0000085, &low, &high);
+    if (reg == 1)
+	low = high;
+
+    /* Find the base and type for the region */
+    *base = low & 0xFFFE0000;
+    *type = 0;
+    if (low & 1)
+	*type = PM_MTRR_UNCACHABLE;
+    if (low & 2)
+	*type = PM_MTRR_WRCOMB;
+    if ((low & 3) == 0) {
+	*size = 0;
+	return;
+	}
+
+    /* This needs a little explaining. The size is stored as an
+     * inverted mask of bits of 128K granularity 15 bits long offset
+     * 2 bits
+     *
+     * So to get a size we do invert the mask and add 1 to the lowest
+     * mask bit (4 as its 2 bits in). This gives us a size we then shift
+     * to turn into 128K blocks
+     *
+     *  eg              111 1111 1111 1100      is 512K
+     *
+     *  invert          000 0000 0000 0011
+     *  +1              000 0000 0000 0100
+     *  *128K   ...
+     */
+    low = (~low) & 0x0FFFC;
+    *size = (low + 4) << 15;
+}
+
+/****************************************************************************
+PARAMETERS:
+reg     - MTRR register to set
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+REMARKS:
+Intel specific function to set the value of a specific MTRR register to
+the passed in base, size and type.
+****************************************************************************/
+static void AMD_setMTRR(
+    uint reg,
+    ulong base,
+    ulong size,
+    int type)
+{
+    ulong       low,high,newVal;
+    MTRRContext c;
+
+    MTRR_beginUpdate(&c);
+    _MTRR_readMSR(0xC0000085, &low, &high);
+    if (size == 0) {
+	/* Clear register to disable */
+	if (reg)
+	    high = 0;
+	else
+	    low = 0;
+	}
+    else {
+	/* Set the register to the base (already shifted for us), the
+	 * type (off by one) and an inverted bitmask of the size
+	 * The size is the only odd bit. We are fed say 512K
+	 * We invert this and we get 111 1111 1111 1011 but
+	 * if you subtract one and invert you get the desired
+	 * 111 1111 1111 1100 mask
+	 */
+	newVal = (((~(size-1)) >> 15) & 0x0001FFFC) | base | (type+1);
+	if (reg)
+	    high = newVal;
+	else
+	    low = newVal;
+	}
+
+    /* The writeback rule is quite specific. See the manual. Its
+     * disable local interrupts, write back the cache, set the MTRR
+     */
+    PM_flushTLB();
+    _MTRR_writeMSR(0xC0000085, low, high);
+    MTRR_endUpdate(&c);
+}
+
+/****************************************************************************
+PARAMETERS:
+reg     - MTRR register to set
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+REMARKS:
+Intel specific function to set the value of a specific MTRR register to
+the passed in base, size and type.
+****************************************************************************/
+static void CYRIX_getMTRR(
+    uint reg,
+    ulong *base,
+    ulong *size,
+    int *type)
+{
+    MTRRContext c;
+    uchar       arr = CX86_ARR_BASE + reg*3;
+    uchar       rcr,shift;
+
+    /* Save flags and disable interrupts */
+    MTRR_beginUpdate(&c);
+    ((uchar*)base)[3]  = _MTRR_getCx86(arr);
+    ((uchar*)base)[2]  = _MTRR_getCx86((uchar)(arr+1));
+    ((uchar*)base)[1]  = _MTRR_getCx86((uchar)(arr+2));
+    rcr = _MTRR_getCx86((uchar)(CX86_RCR_BASE + reg));
+    MTRR_endUpdate(&c);
+
+    /* Enable interrupts if it was enabled previously */
+    shift = ((uchar*)base)[1] & 0x0f;
+    *base &= 0xFFFFF000UL;
+
+    /* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
+     * Note: shift==0xF means 4G, this is unsupported.
+     */
+    if (shift)
+	*size = (reg < 7 ? 0x800UL : 0x20000UL) << shift;
+    else
+	*size = 0;
+
+    /* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */
+    if (reg < 7) {
+	switch (rcr) {
+	    case  1: *type = PM_MTRR_UNCACHABLE; break;
+	    case  8: *type = PM_MTRR_WRBACK;     break;
+	    case  9: *type = PM_MTRR_WRCOMB;     break;
+	    case 24:
+	    default: *type = PM_MTRR_WRTHROUGH;  break;
+	    }
+	}
+    else {
+	switch (rcr) {
+	    case  0: *type = PM_MTRR_UNCACHABLE; break;
+	    case  8: *type = PM_MTRR_WRCOMB;     break;
+	    case  9: *type = PM_MTRR_WRBACK;     break;
+	    case 25:
+	    default: *type = PM_MTRR_WRTHROUGH;  break;
+	    }
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+reg     - MTRR register to set
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+REMARKS:
+Intel specific function to set the value of a specific MTRR register to
+the passed in base, size and type.
+****************************************************************************/
+static void CYRIX_setMTRR(
+    uint reg,
+    ulong base,
+    ulong size,
+    int type)
+{
+    MTRRContext c;
+    uchar       arr = CX86_ARR_BASE + reg*3;
+    uchar       arr_type,arr_size;
+
+    /* Count down from 32M (ARR0-ARR6) or from 2G (ARR7) */
+    size >>= (reg < 7 ? 12 : 18);
+    size &= 0x7FFF; /* Make sure arr_size <= 14 */
+    for (arr_size = 0; size; arr_size++, size >>= 1)
+	;
+    if (reg < 7) {
+	switch (type) {
+	    case PM_MTRR_UNCACHABLE:    arr_type =  1; break;
+	    case PM_MTRR_WRCOMB:        arr_type =  9; break;
+	    case PM_MTRR_WRTHROUGH:     arr_type = 24; break;
+	    default:                    arr_type =  8; break;
+	    }
+	}
+    else {
+	switch (type) {
+	    case PM_MTRR_UNCACHABLE:    arr_type =  0; break;
+	    case PM_MTRR_WRCOMB:        arr_type =  8; break;
+	    case PM_MTRR_WRTHROUGH:     arr_type = 25; break;
+	    default:                    arr_type =  9; break;
+	    }
+	}
+    MTRR_beginUpdate(&c);
+    _MTRR_setCx86((uchar)arr,     ((uchar*)&base)[3]);
+    _MTRR_setCx86((uchar)(arr+1), ((uchar*)&base)[2]);
+    _MTRR_setCx86((uchar)(arr+2), (uchar)((((uchar*)&base)[1]) | arr_size));
+    _MTRR_setCx86((uchar)(CX86_RCR_BASE + reg), (uchar)arr_type);
+    MTRR_endUpdate(&c);
+}
+
+/****************************************************************************
+REMARKS:
+On Cyrix 6x86(MX) and MII the ARR3 is special: it has connection
+with the SMM (System Management Mode) mode. So we need the following:
+Check whether SMI_LOCK (CCR3 bit 0) is set
+  if it is set, ARR3 cannot be changed  (it cannot be changed until the
+    next processor reset)
+  if it is reset, then we can change it, set all the needed bits:
+   - disable access to SMM memory through ARR3 range (CCR1 bit 7 reset)
+   - disable access to SMM memory (CCR1 bit 2 reset)
+   - disable SMM mode (CCR1 bit 1 reset)
+   - disable write protection of ARR3 (CCR6 bit 1 reset)
+   - (maybe) disable ARR3
+Just to be sure, we enable ARR usage by the processor (CCR5 bit 5 set)
+****************************************************************************/
+static void CYRIX_initARR(void)
+{
+    MTRRContext c;
+    uchar       ccr[7];
+    int         ccrc[7] = { 0, 0, 0, 0, 0, 0, 0 };
+
+    /* Begin updating */
+    MTRR_beginUpdate(&c);
+
+    /* Save all CCRs locally */
+    ccr[0] = _MTRR_getCx86(CX86_CCR0);
+    ccr[1] = _MTRR_getCx86(CX86_CCR1);
+    ccr[2] = _MTRR_getCx86(CX86_CCR2);
+    ccr[3] = (uchar)c.ccr3;
+    ccr[4] = _MTRR_getCx86(CX86_CCR4);
+    ccr[5] = _MTRR_getCx86(CX86_CCR5);
+    ccr[6] = _MTRR_getCx86(CX86_CCR6);
+    if (ccr[3] & 1)
+	ccrc[3] = 1;
+    else {
+	/* Disable SMM mode (bit 1), access to SMM memory (bit 2) and
+	 * access to SMM memory through ARR3 (bit 7).
+	 */
+	if (ccr[6] & 0x02) {
+	    ccr[6] &= 0xFD;
+	    ccrc[6] = 1;        /* Disable write protection of ARR3. */
+	    _MTRR_setCx86(CX86_CCR6,ccr[6]);
+	    }
+	}
+
+    /* If we changed CCR1 in memory, change it in the processor, too. */
+    if (ccrc[1])
+	_MTRR_setCx86(CX86_CCR1,ccr[1]);
+
+    /* Enable ARR usage by the processor */
+    if (!(ccr[5] & 0x20)) {
+	ccr[5] |= 0x20;
+	ccrc[5] = 1;
+	_MTRR_setCx86(CX86_CCR5,ccr[5]);
+	}
+
+    /* We are finished updating */
+    MTRR_endUpdate(&c);
+}
+
+/****************************************************************************
+REMARKS:
+Initialise the MTRR module, by detecting the processor type and determining
+if the processor supports the MTRR functionality.
+****************************************************************************/
+void MTRR_init(void)
+{
+    int     i,cpu,ltype;
+    ulong   eax,edx,lbase,lsize;
+
+    /* Check that we have a compatible CPU */
+    if (numMTRR == -1) {
+	numMTRR = 0;
+	if (!_MTRR_isRing0())
+	    return;
+	cpu = CPU_getProcessorType();
+	cpuFamily = cpu & CPU_familyMask;
+	cpuType = cpu & CPU_mask;
+	cpuStepping = (cpu & CPU_steppingMask) >> CPU_steppingShift;
+	switch (cpuFamily) {
+	    case CPU_Intel:
+		/* Intel Pentium Pro and later support the MTRR registers */
+		if (cpuType < CPU_PentiumPro)
+		    return;
+		_MTRR_readMSR(INTEL_cap_MSR,&eax,&edx);
+		numMTRR = eax & 0xFF;
+		getMTRR = INTEL_getMTRR;
+		setMTRR = INTEL_setMTRR;
+		getFreeRegion = GENERIC_getFreeRegion;
+		INTEL_disableBankedWriteCombine();
+		break;
+	    case CPU_AMD:
+		/* AMD K6-2 and later support the MTRR registers */
+		if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8))
+		    return;
+		if (cpuType < CPU_AMDAthlon) {
+		    numMTRR = 2;        /* AMD CPU's have 2 MTRR's */
+		    getMTRR = AMD_getMTRR;
+		    setMTRR = AMD_setMTRR;
+		    getFreeRegion = AMDK6_getFreeRegion;
+
+		    /* For some reason some IBM systems with K6-2 processors
+		     * have write combined enabled for the system BIOS
+		     * region from 0xE0000 to 0xFFFFFF. We need *both* MTRR's
+		     * for our own graphics drivers, so if we detect any
+		     * regions below the 1Meg boundary, we remove them
+		     * so we can use this MTRR register ourselves.
+		     */
+		    for (i = 0; i < numMTRR; i++) {
+			getMTRR(i,&lbase,&lsize,&ltype);
+			if (lbase < 0x100000)
+			    setMTRR(i,0,0,0);
+			}
+		    }
+		else {
+		    /* AMD Athlon uses P6 style MTRR's */
+		    _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx);
+		    numMTRR = eax & 0xFF;
+		    getMTRR = INTEL_getMTRR;
+		    setMTRR = INTEL_setMTRR;
+		    getFreeRegion = GENERIC_getFreeRegion;
+		    INTEL_disableBankedWriteCombine();
+		    }
+		break;
+	    case CPU_Cyrix:
+		/* Cyrix 6x86 and later support the MTRR registers */
+		if (cpuType < CPU_Cyrix6x86 || cpuType >= CPU_CyrixMediaGX)
+		    return;
+		numMTRR = 8;        /* Cyrix CPU's have 8 ARR's */
+		getMTRR = CYRIX_getMTRR;
+		setMTRR = CYRIX_setMTRR;
+		getFreeRegion = CYRIX_getFreeRegion;
+		CYRIX_initARR();
+		break;
+	    default:
+		return;
+	    }
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+RETURNS:
+Error code describing the result.
+
+REMARKS:
+Function to enable write combining for the specified region of memory.
+****************************************************************************/
+int MTRR_enableWriteCombine(
+    ulong base,
+    ulong size,
+    uint type)
+{
+    int     i;
+    int     ltype;
+    ulong   lbase,lsize,last;
+
+    /* Check that we have a CPU that supports MTRR's and type is valid */
+    if (numMTRR <= 0) {
+	if (!_MTRR_isRing0())
+	    return PM_MTRR_ERR_NO_OS_SUPPORT;
+	return PM_MTRR_NOT_SUPPORTED;
+	}
+    if (type >= PM_MTRR_MAX)
+	return PM_MTRR_ERR_PARAMS;
+
+    /* If the type is WC, check that this processor supports it */
+    if (!MTRR_haveWriteCombine())
+	return PM_MTRR_ERR_NOWRCOMB;
+
+    /* Adjust the boundaries depending on the CPU type */
+    switch (cpuFamily) {
+	case CPU_AMD:
+	    if (cpuType < CPU_AMDAthlon) {
+		/* Apply the K6 block alignment and size rules. In order:
+		 *  o Uncached or gathering only
+		 *  o 128K or bigger block
+		 *  o Power of 2 block
+		 *  o base suitably aligned to the power
+		 */
+		if (type > PM_MTRR_WRCOMB && (size < (1 << 17) || (size & ~(size-1))-size || (base & (size-1))))
+		    return PM_MTRR_ERR_NOT_ALIGNED;
+		break;
+		}
+	    /* Fall through for AMD Athlon which uses P6 style MTRR's */
+	case CPU_Intel:
+	case CPU_Cyrix:
+	    if ((base & 0xFFF) || (size & 0xFFF)) {
+		/* Base and size must be multiples of 4Kb */
+		return PM_MTRR_ERR_NOT_4KB_ALIGNED;
+		}
+	    if (base < 0x100000) {
+		/* Base must be >= 1Mb */
+		return PM_MTRR_ERR_BELOW_1MB;
+		}
+
+	    /* Check upper bits of base and last are equal and lower bits
+	     * are 0 for base and 1 for last
+	     */
+	    last = base + size - 1;
+	    for (lbase = base; !(lbase & 1) && (last & 1); lbase = lbase >> 1, last = last >> 1)
+		;
+	    if (lbase != last) {
+		/* Base is not aligned on the correct boundary */
+		return PM_MTRR_ERR_NOT_ALIGNED;
+		}
+	    break;
+	default:
+	    return PM_MTRR_NOT_SUPPORTED;
+	}
+
+    /* Search for existing MTRR */
+    for (i = 0; i < numMTRR; ++i) {
+	getMTRR(i,&lbase,&lsize,&ltype);
+	if (lbase == 0 && lsize == 0)
+	    continue;
+	if (base > lbase + (lsize-1))
+	    continue;
+	if ((base < lbase) && (base+size-1 < lbase))
+	    continue;
+
+	/* Check that we don't overlap an existing region */
+	if (type != PM_MTRR_UNCACHABLE) {
+	    if ((base < lbase) || (base+size-1 > lbase+lsize-1))
+		return PM_MTRR_ERR_OVERLAP;
+	    }
+	else if (base == lbase && size == lsize) {
+	    /* The region already exists so leave it alone */
+	    return PM_MTRR_ERR_OK;
+	    }
+
+	/* New region is enclosed by an existing region, so only allow
+	 * a new type to be created if we are setting a region to be
+	 * uncacheable (such as MMIO registers within a framebuffer).
+	 */
+	if (ltype != (int)type) {
+	    if (type == PM_MTRR_UNCACHABLE)
+		continue;
+	    return PM_MTRR_ERR_TYPE_MISMATCH;
+	    }
+	return PM_MTRR_ERR_OK;
+	}
+
+    /* Search for an empty MTRR */
+    if ((i = getFreeRegion(base,size)) < 0)
+	return PM_MTRR_ERR_NONE_FREE;
+    setMTRR(i,base,size,type);
+    return PM_MTRR_ERR_OK;
+}
+
+/****************************************************************************
+PARAMETERS:
+callback    - Function to callback with write combine information
+
+REMARKS:
+Function to enumerate all write combine regions currently enabled for the
+processor.
+****************************************************************************/
+int PMAPI PM_enumWriteCombine(
+    PM_enumWriteCombine_t callback)
+{
+    int     i,ltype;
+    ulong   lbase,lsize;
+
+    /* Check that we have a CPU that supports MTRR's and type is valid */
+    if (numMTRR <= 0) {
+	if (!_MTRR_isRing0())
+	    return PM_MTRR_ERR_NO_OS_SUPPORT;
+	return PM_MTRR_NOT_SUPPORTED;
+	}
+
+    /* Enumerate all existing MTRR's */
+    for (i = 0; i < numMTRR; ++i) {
+	getMTRR(i,&lbase,&lsize,&ltype);
+	callback(lbase,lsize,ltype);
+	}
+    return PM_MTRR_ERR_OK;
+}
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c b/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c
new file mode 100755
index 0000000..1d542fc
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c
@@ -0,0 +1,747 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Module for interfacing to the PCI bus and configuration
+*               space registers.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "pcilib.h"
+#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__)
+#include <string.h>
+#endif
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+#pragma pack(1)
+
+/* Length of the memory mapping for the PCI BIOS */
+
+#define BIOS_LIMIT          (128 * 1024L - 1)
+
+/* Macros for accessing the PCI BIOS functions from 32-bit protected mode */
+
+#define BIOS32_SIGNATURE    (((ulong)'_' << 0) + ((ulong)'3' << 8) + ((ulong)'2' << 16) + ((ulong)'_' << 24))
+#define PCI_SIGNATURE       (((ulong)'P' << 0) + ((ulong)'C' << 8) + ((ulong)'I' << 16) + ((ulong)' ' << 24))
+#define PCI_SERVICE         (((ulong)'$' << 0) + ((ulong)'P' << 8) + ((ulong)'C' << 16) + ((ulong)'I' << 24))
+#define PCI_BIOS_PRESENT    0xB101
+#define FIND_PCI_DEVICE     0xB102
+#define FIND_PCI_CLASS      0xB103
+#define GENERATE_SPECIAL    0xB106
+#define READ_CONFIG_BYTE    0xB108
+#define READ_CONFIG_WORD    0xB109
+#define READ_CONFIG_DWORD   0xB10A
+#define WRITE_CONFIG_BYTE   0xB10B
+#define WRITE_CONFIG_WORD   0xB10C
+#define WRITE_CONFIG_DWORD  0xB10D
+#define GET_IRQ_ROUTING_OPT 0xB10E
+#define SET_PCI_IRQ         0xB10F
+
+/* This is the standard structure used to identify the entry point to the
+ * BIOS32 Service Directory, as documented in PCI 2.1 BIOS Specicition.
+ */
+
+typedef union {
+    struct {
+	ulong signature;        /* _32_                                 */
+	ulong entry;            /* 32 bit physical address              */
+	uchar revision;         /* Revision level, 0                    */
+	uchar length;           /* Length in paragraphs should be 01    */
+	uchar checksum;         /* All bytes must add up to zero        */
+	uchar reserved[5];      /* Must be zero                         */
+	} fields;
+    char chars[16];
+    } PCI_bios32;
+
+/* Structure for a far pointer to call the PCI BIOS services with */
+
+typedef struct {
+    ulong   address;
+    ushort  segment;
+    } PCIBIOS_entry;
+
+/* Macros to copy a structure that includes dwSize members */
+
+#define COPY_STRUCTURE(d,s) memcpy(d,s,MIN((s)->dwSize,(d)->dwSize))
+
+#pragma pack()
+
+/*--------------------------- Global variables ----------------------------*/
+
+static uchar            *BIOSImage = NULL;  /* BIOS image mapping       */
+static int              PCIBIOSVersion = -1;/* PCI BIOS version         */
+static PCIBIOS_entry    PCIEntry;           /* PCI services entry point */
+static ulong            PCIPhysEntry = 0;   /* Physical address         */
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* External assembler helper functions */
+
+uchar   _ASMAPI _BIOS32_service(ulong service,ulong function,ulong *physBase,ulong *length,ulong *serviceOffset,PCIBIOS_entry entry);
+ushort  _ASMAPI _PCIBIOS_isPresent(ulong i_eax,ulong *o_edx,ushort *o_ax,uchar *o_cl,PCIBIOS_entry entry);
+ulong   _ASMAPI _PCIBIOS_service(ulong r_eax,ulong r_ebx,ulong r_edi,ulong r_ecx,PCIBIOS_entry entry);
+int     _ASMAPI _PCIBIOS_getRouting(PCIRoutingOptionsBuffer *buf,PCIBIOS_entry entry);
+ibool   _ASMAPI _PCIBIOS_setIRQ(int busDev,int intPin,int IRQ,PCIBIOS_entry entry);
+ulong   _ASMAPI _PCIBIOS_specialCycle(int bus,ulong data,PCIBIOS_entry entry);
+ushort  _ASMAPI _PCI_getCS(void);
+
+/****************************************************************************
+REMARKS:
+This functions returns the physical address of the PCI BIOS entry point.
+****************************************************************************/
+ulong _ASMAPI PCIBIOS_getEntry(void)
+{ return PCIPhysEntry; }
+
+/****************************************************************************
+PARAMETERS:
+hwType  - Place to store the PCI hardware access mechanism flags
+lastBus - Place to store the index of the last PCI bus in the system
+
+RETURNS:
+Version number of the PCI BIOS found.
+
+REMARKS:
+This function determines if the PCI BIOS is present in the system, and if
+so returns the information returned by the PCI BIOS detect function.
+****************************************************************************/
+static int PCIBIOS_detect(
+    uchar *hwType,
+    uchar *lastBus)
+{
+    ulong   signature;
+    ushort  stat,version;
+
+#ifndef __16BIT__
+    PCIBIOS_entry   BIOSEntry = {0};
+    uchar           *BIOSEnd;
+    PCI_bios32      *BIOSDir;
+    ulong           physBase,length,offset;
+
+    /* Bail if we have already detected no BIOS is present */
+    if (PCIBIOSVersion == 0)
+	return 0;
+
+    /* First scan the memory from 0xE0000 to 0xFFFFF looking for the
+     * BIOS32 service directory, so we can determine if we can call it
+     * from 32-bit protected mode.
+     */
+    if (PCIBIOSVersion == -1) {
+	PCIBIOSVersion = 0;
+	BIOSImage = PM_mapPhysicalAddr(0xE0000,BIOS_LIMIT,false);
+	if (!BIOSImage)
+	    return 0;
+	BIOSEnd = BIOSImage + 0x20000;
+	for (BIOSDir = (PCI_bios32*)BIOSImage; BIOSDir < (PCI_bios32*)BIOSEnd; BIOSDir++) {
+	    uchar   sum;
+	    int     i,length;
+
+	    if (BIOSDir->fields.signature != BIOS32_SIGNATURE)
+		continue;
+	    length = BIOSDir->fields.length * 16;
+	    if (!length)
+		continue;
+	    for (sum = i = 0; i < length ; i++)
+		sum += BIOSDir->chars[i];
+	    if (sum != 0)
+		continue;
+	    BIOSEntry.address = (ulong)BIOSImage + (BIOSDir->fields.entry - 0xE0000);
+	    BIOSEntry.segment = _PCI_getCS();
+	    break;
+	    }
+
+	/* If we found the BIOS32 directory, call it to get the address of the
+	 * PCI services.
+	 */
+	if (BIOSEntry.address == 0)
+	    return 0;
+	if (_BIOS32_service(PCI_SERVICE,0,&physBase,&length,&offset,BIOSEntry) != 0)
+	    return 0;
+	PCIPhysEntry = physBase + offset;
+	PCIEntry.address = (ulong)BIOSImage + (PCIPhysEntry - 0xE0000);
+	PCIEntry.segment = _PCI_getCS();
+	}
+#endif
+    /* We found the BIOS entry, so now do the version check */
+    version = _PCIBIOS_isPresent(PCI_BIOS_PRESENT,&signature,&stat,lastBus,PCIEntry);
+    if (version > 0 && ((stat >> 8) == 0) && signature == PCI_SIGNATURE) {
+	*hwType = stat & 0xFF;
+	return PCIBIOSVersion = version;
+	}
+    return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+info    - Array of PCIDeviceInfo structures to check against
+index   - Index of the current device to check
+
+RETURNS:
+True if the device is a duplicate, false if not.
+
+REMARKS:
+This function goes through the list of all devices preceeding the newly
+found device in the info structure, and checks that the device is not a
+duplicate of a previous device. Some devices incorrectly enumerate
+themselves at different function addresses so we check here to exclude
+those cases.
+****************************************************************************/
+static ibool CheckDuplicate(
+    PCIDeviceInfo *info,
+    PCIDeviceInfo *prev)
+{
+    /* Ignore devices with a vendor ID of 0 */
+    if (info->VendorID == 0)
+	return true;
+
+    /* NOTE: We only check against the current device on
+     *       the bus to ensure that we do not exclude
+     *       multiple controllers of the same device ID.
+     */
+    if (info->slot.p.Bus == prev->slot.p.Bus &&
+	info->slot.p.Device == prev->slot.p.Device &&
+	info->DeviceID == prev->DeviceID)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+PARAMETERS:
+info        - Array of PCIDeviceInfo structures to fill in
+maxDevices  - Maximum number of of devices to enumerate into array
+
+RETURNS:
+Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI.
+
+REMARKS:
+Function to enumerate all available devices on the PCI bus into an array
+of configuration information blocks.
+****************************************************************************/
+static int PCI_enumerateMech1(
+    PCIDeviceInfo info[])
+{
+    int             bus,device,function,i,numFound = 0;
+    ulong           *lp,tmp;
+    PCIslot         slot = {{0,0,0,0,0,0,1}};
+    PCIDeviceInfo   pci,prev = {0};
+
+    /* Try PCI access mechanism 1 */
+    PM_outpb(0xCFB,0x01);
+    tmp = PM_inpd(0xCF8);
+    PM_outpd(0xCF8,slot.i);
+    if ((PM_inpd(0xCF8) == slot.i) && (PM_inpd(0xCFC) != 0xFFFFFFFFUL)) {
+	/* PCI access mechanism 1 - the preferred mechanism */
+	for (bus = 0; bus < 8; bus++) {
+	    slot.p.Bus = bus;
+	    for (device = 0; device < 32; device++) {
+		slot.p.Device = device;
+		for (function = 0; function < 8; function++) {
+		    slot.p.Function = function;
+		    slot.p.Register = 0;
+		    PM_outpd(0xCF8,slot.i);
+		    if (PM_inpd(0xCFC) != 0xFFFFFFFFUL) {
+			memset(&pci,0,sizeof(pci));
+			pci.dwSize = sizeof(pci);
+			pci.mech1 = 1;
+			pci.slot = slot;
+			lp = (ulong*)&(pci.VendorID);
+			for (i = 0; i < NUM_PCI_REG; i++, lp++) {
+			    slot.p.Register = i;
+			    PM_outpd(0xCF8,slot.i);
+			    *lp = PM_inpd(0xCFC);
+			    }
+			if (!CheckDuplicate(&pci,&prev)) {
+			    if (info)
+				COPY_STRUCTURE(&info[numFound],&pci);
+			    ++numFound;
+			    }
+			prev = pci;
+			}
+		    }
+		}
+	    }
+
+	/* Disable PCI config cycle on exit */
+	PM_outpd(0xCF8,0);
+	return numFound;
+	}
+    PM_outpd(0xCF8,tmp);
+
+    /* No hardware access mechanism 1 found */
+    return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+info        - Array of PCIDeviceInfo structures to fill in
+maxDevices  - Maximum number of of devices to enumerate into array
+
+RETURNS:
+Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI.
+
+REMARKS:
+Function to enumerate all available devices on the PCI bus into an array
+of configuration information blocks.
+****************************************************************************/
+static int PCI_enumerateMech2(
+    PCIDeviceInfo info[])
+{
+    int             bus,device,function,i,numFound = 0;
+    ushort          deviceIO;
+    ulong           *lp;
+    PCIslot         slot = {{0,0,0,0,0,0,1}};
+    PCIDeviceInfo   pci,prev = {0};
+
+    /* Try PCI access mechanism 2 */
+    PM_outpb(0xCFB,0x00);
+    PM_outpb(0xCF8,0x00);
+    PM_outpb(0xCFA,0x00);
+    if (PM_inpb(0xCF8) == 0x00 && PM_inpb(0xCFB) == 0x00) {
+	/* PCI access mechanism 2 - the older mechanism for legacy busses */
+	for (bus = 0; bus < 2; bus++) {
+	    slot.p.Bus = bus;
+	    PM_outpb(0xCFA,(uchar)bus);
+	    for (device = 0; device < 16; device++) {
+		slot.p.Device = device;
+		deviceIO = 0xC000 + (device << 8);
+		for (function = 0; function < 8; function++) {
+		    slot.p.Function = function;
+		    slot.p.Register = 0;
+		    PM_outpb(0xCF8,(uchar)((function << 1) | 0x10));
+		    if (PM_inpd(deviceIO) != 0xFFFFFFFFUL) {
+			memset(&pci,0,sizeof(pci));
+			pci.dwSize = sizeof(pci);
+			pci.mech1 = 0;
+			pci.slot = slot;
+			lp = (ulong*)&(pci.VendorID);
+			for (i = 0; i < NUM_PCI_REG; i++, lp++) {
+			    slot.p.Register = i;
+			    *lp = PM_inpd(deviceIO + (i << 2));
+			    }
+			if (!CheckDuplicate(&pci,&prev)) {
+			    if (info)
+				COPY_STRUCTURE(&info[numFound],&pci);
+			    ++numFound;
+			    }
+			prev = pci;
+			}
+		    }
+		}
+	    }
+
+	/* Disable PCI config cycle on exit */
+	PM_outpb(0xCF8,0);
+	return numFound;
+	}
+
+    /* No hardware access mechanism 2 found */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+This functions reads a configuration dword via the PCI BIOS.
+****************************************************************************/
+static ulong PCIBIOS_readDWORD(
+    int index,
+    ulong slot)
+{
+    return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,slot >> 8,index,0,PCIEntry);
+}
+
+/****************************************************************************
+PARAMETERS:
+info        - Array of PCIDeviceInfo structures to fill in
+maxDevices  - Maximum number of of devices to enumerate into array
+
+RETURNS:
+Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI.
+
+REMARKS:
+Function to enumerate all available devices on the PCI bus into an array
+of configuration information blocks.
+****************************************************************************/
+static int PCI_enumerateBIOS(
+    PCIDeviceInfo info[])
+{
+    uchar           hwType,lastBus;
+    int             bus,device,function,i,numFound = 0;
+    ulong           *lp;
+    PCIslot         slot = {{0,0,0,0,0,0,1}};
+    PCIDeviceInfo   pci,prev = {0};
+
+    if (PCIBIOS_detect(&hwType,&lastBus)) {
+	/* PCI BIOS access - the ultimate fallback */
+	for (bus = 0; bus <= lastBus; bus++) {
+	    slot.p.Bus = bus;
+	    for (device = 0; device < 32; device++) {
+		slot.p.Device = device;
+		for (function = 0; function < 8; function++) {
+		    slot.p.Function = function;
+		    if (PCIBIOS_readDWORD(0,slot.i) != 0xFFFFFFFFUL) {
+			memset(&pci,0,sizeof(pci));
+			pci.dwSize = sizeof(pci);
+			pci.mech1 = 2;
+			pci.slot = slot;
+			lp = (ulong*)&(pci.VendorID);
+			for (i = 0; i < NUM_PCI_REG; i++, lp++)
+			    *lp = PCIBIOS_readDWORD(i << 2,slot.i);
+			if (!CheckDuplicate(&pci,&prev)) {
+			    if (info)
+				COPY_STRUCTURE(&info[numFound],&pci);
+			    ++numFound;
+			    }
+			prev = pci;
+			}
+		    }
+		}
+	    }
+	}
+
+    /* Return number of devices found */
+    return numFound;
+}
+
+/****************************************************************************
+PARAMETERS:
+info        - Array of PCIDeviceInfo structures to fill in
+maxDevices  - Maximum number of of devices to enumerate into array
+
+RETURNS:
+Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI.
+
+REMARKS:
+Function to enumerate all available devices on the PCI bus into an array
+of configuration information blocks.
+****************************************************************************/
+int _ASMAPI PCI_enumerate(
+    PCIDeviceInfo info[])
+{
+    int numFound;
+
+    /* First try via the direct access mechanisms which are faster if we
+     * have them (nearly always). The BIOS is used as a fallback, and for
+     * stuff we can't do directly.
+     */
+    if ((numFound = PCI_enumerateMech1(info)) == 0) {
+	if ((numFound = PCI_enumerateMech2(info)) == 0) {
+	    if ((numFound = PCI_enumerateBIOS(info)) == 0)
+		return 0;
+	    }
+	}
+    return numFound;
+}
+
+/****************************************************************************
+PARAMETERS:
+info        - Array of PCIDeviceInfo structures to fill in
+maxDevices  - Maximum number of of devices to enumerate into array
+
+RETURNS:
+Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI.
+
+REMARKS:
+Function to enumerate all available devices on the PCI bus into an array
+of configuration information blocks.
+****************************************************************************/
+int _ASMAPI PCI_getNumDevices(void)
+{
+    return PCI_enumerate(NULL);
+}
+
+/****************************************************************************
+PARAMETERS:
+bar - Base address to measure
+pci - PCI device to access
+
+RETURNS:
+Size of the PCI base address in bytes
+
+REMARKS:
+This function measures the size of the PCI base address register in bytes,
+by writing all F's to the register, and reading the value back. The size
+of the base address is determines by the bits that are hardwired to zero's.
+****************************************************************************/
+ulong _ASMAPI PCI_findBARSize(
+    int bar,
+    PCIDeviceInfo *pci)
+{
+    ulong   base,size = 0;
+
+    base = PCI_accessReg(bar,0,PCI_READ_DWORD,pci);
+    if (base && !(base & 0x1)) {
+	/* For some strange reason some devices don't properly decode
+	 * their base address registers (Intel PCI/PCI bridges!), and
+	 * we read completely bogus values. We check for that here
+	 * and clear out those BAR's.
+	 *
+	 * We check for that here because at least the low 12 bits
+	 * of the address range must be zeros, since the page size
+	 * on IA32 processors is always 4Kb.
+	 */
+	if ((base & 0xFFF) == 0) {
+	    PCI_accessReg(bar,0xFFFFFFFF,PCI_WRITE_DWORD,pci);
+	    size = PCI_accessReg(bar,0,PCI_READ_DWORD,pci) & ~0xFF;
+	    size = ~size+1;
+	    PCI_accessReg(bar,base,PCI_WRITE_DWORD,pci);
+	    }
+	}
+    pci->slot.p.Register = 0;
+    return size;
+}
+
+/****************************************************************************
+PARAMETERS:
+index   - DWORD index of the register to access
+value   - Value to write to the register for write access
+func    - Function to implement
+
+RETURNS:
+The value read from the register for read operations
+
+REMARKS:
+The function code are defined as follows
+
+code    - function
+0       - Read BYTE
+1       - Read WORD
+2       - Read DWORD
+3       - Write BYTE
+4       - Write WORD
+5       - Write DWORD
+****************************************************************************/
+ulong _ASMAPI PCI_accessReg(
+    int index,
+    ulong value,
+    int func,
+    PCIDeviceInfo *info)
+{
+    int iobase;
+
+    if (info->mech1 == 2) {
+	/* Use PCI BIOS access since we dont have direct hardware access */
+	switch (func) {
+	    case PCI_READ_BYTE:
+		return (uchar)_PCIBIOS_service(READ_CONFIG_BYTE,info->slot.i >> 8,index,0,PCIEntry);
+	    case PCI_READ_WORD:
+		return (ushort)_PCIBIOS_service(READ_CONFIG_WORD,info->slot.i >> 8,index,0,PCIEntry);
+	    case PCI_READ_DWORD:
+		return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,info->slot.i >> 8,index,0,PCIEntry);
+	    case PCI_WRITE_BYTE:
+		_PCIBIOS_service(WRITE_CONFIG_BYTE,info->slot.i >> 8,index,value,PCIEntry);
+		break;
+	    case PCI_WRITE_WORD:
+		_PCIBIOS_service(WRITE_CONFIG_WORD,info->slot.i >> 8,index,value,PCIEntry);
+		break;
+	    case PCI_WRITE_DWORD:
+		_PCIBIOS_service(WRITE_CONFIG_DWORD,info->slot.i >> 8,index,value,PCIEntry);
+		break;
+	    }
+	}
+    else {
+	/* Use direct hardware access mechanisms */
+	if (info->mech1) {
+	    /* PCI access mechanism 1 */
+	    iobase = 0xCFC + (index & 3);
+	    info->slot.p.Register = index >> 2;
+	    PM_outpd(0xCF8,info->slot.i);
+	    }
+	else {
+	    /* PCI access mechanism 2 */
+	    PM_outpb(0xCF8,(uchar)((info->slot.p.Function << 1) | 0x10));
+	    PM_outpb(0xCFA,(uchar)info->slot.p.Bus);
+	    iobase = 0xC000 + (info->slot.p.Device << 8) + index;
+	    }
+	switch (func) {
+	    case PCI_READ_BYTE:
+	    case PCI_READ_WORD:
+	    case PCI_READ_DWORD:    value = PM_inpd(iobase);        break;
+	    case PCI_WRITE_BYTE:    PM_outpb(iobase,(uchar)value);  break;
+	    case PCI_WRITE_WORD:    PM_outpw(iobase,(ushort)value); break;
+	    case PCI_WRITE_DWORD:   PM_outpd(iobase,(ulong)value);  break;
+	    }
+	PM_outpd(0xCF8,0);
+	}
+    return value;
+}
+
+/****************************************************************************
+PARAMETERS:
+numDevices  - Number of devices to query info for
+
+RETURNS:
+0 on success, -1 on error, number of devices to enumerate if numDevices = 0
+
+REMARKS:
+This function reads the PCI routing information. If you pass a value of
+0 for numDevices, this function will return with the number of devices
+needed in the routing buffer that will be filled in by the BIOS.
+****************************************************************************/
+ibool _ASMAPI PCI_getIRQRoutingOptions(
+    int numDevices,
+    PCIRouteInfo *buffer)
+{
+    PCIRoutingOptionsBuffer buf;
+    int                     ret;
+
+    if (PCIPhysEntry) {
+	buf.BufferSize = numDevices * sizeof(PCIRouteInfo);
+	buf.DataBuffer = buffer;
+	if ((ret = _PCIBIOS_getRouting(&buf,PCIEntry)) == 0x89)
+	    return buf.BufferSize / sizeof(PCIRouteInfo);
+	if (ret != 0)
+	    return -1;
+	return 0;
+	}
+
+    /* We currently only support this via the PCI BIOS functions */
+    return -1;
+}
+
+/****************************************************************************
+PARAMETERS:
+info    - PCI device information for the specified device
+intPin  - Value to store in the PCI InterruptPin register
+IRQ     - New ISA IRQ to map the PCI interrupt to (0-15)
+
+RETURNS:
+True on success, or false if this function failed.
+
+REMARKS:
+This function changes the PCI IRQ routing for the specified device to the
+desired PCI interrupt and the desired ISA bus compatible IRQ. This function
+may not be supported by the PCI BIOS, in which case this function will
+fail.
+****************************************************************************/
+ibool _ASMAPI PCI_setHardwareIRQ(
+    PCIDeviceInfo *info,
+    uint intPin,
+    uint IRQ)
+{
+    if (PCIPhysEntry) {
+	if (_PCIBIOS_setIRQ(info->slot.i >> 8,intPin,IRQ,PCIEntry)) {
+	    info->u.type0.InterruptPin = intPin;
+	    info->u.type0.InterruptLine = IRQ;
+	    return true;
+	    }
+	return false;
+	}
+
+    /* We currently only support this via the PCI BIOS functions */
+    return false;
+}
+
+/****************************************************************************
+PARAMETERS:
+bus                 - Bus number to generate the special cycle for
+specialCycleData    - Data to send for the special cyle
+
+REMARKS:
+This function generates a special cycle on the specified bus using with
+the specified data.
+****************************************************************************/
+void _ASMAPI PCI_generateSpecialCyle(
+    uint bus,
+    ulong specialCycleData)
+{
+    if (PCIPhysEntry)
+	_PCIBIOS_specialCycle(bus,specialCycleData,PCIEntry);
+    /* We currently only support this via the PCI BIOS functions */
+}
+
+/****************************************************************************
+PARAMETERS:
+info    - PCI device information block for device to access
+index   - Index of register to start reading from
+dst     - Place to store the values read from configuration space
+count   - Count of bytes to read from configuration space
+
+REMARKS:
+This function is used to read a block of PCI configuration space registers
+from the configuration space into the passed in data block. This function
+will properly handle reading non-DWORD aligned data from the configuration
+space correctly.
+****************************************************************************/
+void _ASMAPI PCI_readRegBlock(
+    PCIDeviceInfo *info,
+    int index,
+    void *dst,
+    int count)
+{
+    uchar   *pb;
+    ulong   *pd;
+    int     i;
+    int     startCount = (index & 3);
+    int     middleCount = (count - startCount) >> 2;
+    int     endCount = count - middleCount * 4 - startCount;
+
+    for (i = 0,pb = dst; i < startCount; i++, index++) {
+	*pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info);
+	}
+    for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) {
+	*pd++ = (ulong)PCI_accessReg(index,0,PCI_READ_DWORD,info);
+	}
+    for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) {
+	*pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info);
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+info    - PCI device information block for device to access
+index   - Index of register to start reading from
+dst     - Place to store the values read from configuration space
+count   - Count of bytes to read from configuration space
+
+REMARKS:
+This function is used to write a block of PCI configuration space registers
+to the configuration space from the passed in data block. This function
+will properly handle writing non-DWORD aligned data to the configuration
+space correctly.
+****************************************************************************/
+void _ASMAPI PCI_writeRegBlock(
+    PCIDeviceInfo *info,
+    int index,
+    void *src,
+    int count)
+{
+    uchar   *pb;
+    ulong   *pd;
+    int     i;
+    int     startCount = (index & 3);
+    int     middleCount = (count - startCount) >> 2;
+    int     endCount = count - middleCount * 4 - startCount;
+
+    for (i = 0,pb = src; i < startCount; i++, index++) {
+	PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info);
+	}
+    for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) {
+	PCI_accessReg(index,*pd++,PCI_WRITE_DWORD,info);
+	}
+    for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) {
+	PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info);
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c b/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c
new file mode 100755
index 0000000..c3a66a7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c
@@ -0,0 +1,306 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Module containing Unix I/O functions.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <dirent.h>
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* {secret} */
+typedef struct {
+    DIR     *d;
+    char    path[PM_MAX_PATH];
+    char    mask[PM_MAX_PATH];
+    } PM_findHandle;
+
+/****************************************************************************
+REMARKS:
+Internal function to convert the find data to the generic interface.
+****************************************************************************/
+static void convertFindData(
+    PM_findData *findData,
+    struct dirent *blk,
+    const char *path)
+{
+    ulong       dwSize = findData->dwSize;
+    struct stat st;
+    char        filename[PM_MAX_PATH];
+
+    memset(findData,0,findData->dwSize);
+    findData->dwSize = dwSize;
+    strcpy(filename,path);
+    PM_backslash(filename);
+    strcat(filename,blk->d_name);
+    stat(filename,&st);
+    if (!(st.st_mode & S_IWRITE))
+	findData->attrib |= PM_FILE_READONLY;
+    if (st.st_mode & S_IFDIR)
+	findData->attrib |= PM_FILE_DIRECTORY;
+    findData->sizeLo = st.st_size;
+    findData->sizeHi = 0;
+    strncpy(findData->name,blk->d_name,PM_MAX_PATH);
+    findData->name[PM_MAX_PATH-1] = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Determines if a file name matches the passed in pattern.
+****************************************************************************/
+static ibool filematch(
+    char *pattern,
+    char *dirpath,
+    struct dirent *dire)
+{
+    struct stat st;
+    int         i = 0,j = 0,lastchar = '\0';
+    char        fullpath[PM_MAX_PATH];
+
+    strcpy(fullpath,dirpath);
+    PM_backslash(fullpath);
+    strcat(fullpath, dire->d_name);
+    if (stat(fullpath, &st) != 0)
+	return false;
+    for (; i < (int)strlen(dire->d_name) && j < (int)strlen(pattern); i++, j++) {
+	if (pattern[j] == '*' && lastchar != '\\') {
+	    if (pattern[j+1] == '\0')
+		return true;
+	    while (dire->d_name[i++] != pattern[j+1]) {
+		if (dire->d_name[i] == '\0')
+		    return false;
+		}
+	    i -= 2;
+	    }
+	else if (dire->d_name[i] != pattern[j] &&
+		!(pattern[j] == '?' && lastchar != '\\'))
+	    return false;
+	lastchar = pattern[i];
+	}
+    if (j == (int)strlen(pattern) && i == (int)strlen(dire->d_name))
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+void * PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    PM_findHandle   *d;
+    struct dirent   *dire;
+    char            name[PM_MAX_PATH];
+    char            ext[PM_MAX_PATH];
+
+    if ((d = PM_malloc(sizeof(*d))) == NULL)
+	return PM_FILE_INVALID;
+    PM_splitpath(filename,NULL,d->path,name,ext);
+    strcpy(d->mask,name);
+    strcat(d->mask,ext);
+    if (strlen(d->path) == 0)
+	strcpy(d->path, ".");
+    if (d->path[strlen(d->path)-1] == '/')
+	d->path[strlen(d->path)-1] = 0;
+    if ((d->d = opendir(d->path)) != NULL) {
+	while ((dire = readdir(d->d)) != NULL) {
+	    if (filematch(d->mask,d->path,dire)) {
+		convertFindData(findData,dire,d->path);
+		return d;
+		}
+	    }
+	closedir(d->d);
+	}
+    PM_free(d);
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    void *handle,
+    PM_findData *findData)
+{
+    PM_findHandle   *d = handle;
+    struct dirent   *dire;
+
+    while ((dire = readdir(d->d)) != NULL) {
+	if (filematch(d->mask,d->path,dire)) {
+	    convertFindData(findData,dire,d->path);
+	    return true;
+	    }
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    void *handle)
+{
+    PM_findHandle   *d = handle;
+
+    closedir(d->d);
+    free(d);
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    if (drive == 3)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    (void)drive;
+    getcwd(dir,len);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+    struct stat st;
+    mode_t      mode;
+
+    stat(filename,&st);
+    mode = st.st_mode;
+    if (attrib & PM_FILE_READONLY)
+	mode &= ~S_IWRITE;
+    else
+	mode |= S_IWRITE;
+    chmod(filename,mode);
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file attributes for a specific file.
+****************************************************************************/
+uint PMAPI PM_getFileAttr(
+    const char *filename)
+{
+    struct stat st;
+
+    stat(filename,&st);
+    if (st.st_mode & S_IWRITE)
+	return 0;
+    return PM_FILE_READONLY;
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+    return mkdir(filename,0x1FF) == 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+    return rmdir(filename) == 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_getFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this! */
+    (void)filename;
+    (void)gmTime;
+    (void)time;
+    PM_fatalError("PM_getFileTime not implemented yet!");
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to set the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_setFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this! */
+    (void)filename;
+    (void)gmTime;
+    (void)time;
+    PM_fatalError("PM_setFileTime not implemented yet!");
+    return false;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c b/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c
new file mode 100755
index 0000000..8056e9a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c
@@ -0,0 +1,377 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*                   Portions copyright (C) Josh Vanderhoof
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Functions to save and restore the VGA hardware state.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__)
+#include "sdd/sddhelp.h"
+#else
+#include <string.h>
+#endif
+
+/*--------------------------- Global variables ----------------------------*/
+
+/* VGA index register ports */
+#define CRT_I   0x3D4       /* CRT Controller Index                     */
+#define ATT_IW  0x3C0       /* Attribute Controller Index & Data        */
+#define GRA_I   0x3CE       /* Graphics Controller Index                */
+#define SEQ_I   0x3C4       /* Sequencer Index                          */
+
+/* VGA data register ports */
+#define CRT_D   0x3D5       /* CRT Controller Data Register             */
+#define ATT_R   0x3C1       /* Attribute Controller Data Read Register  */
+#define GRA_D   0x3CF       /* Graphics Controller Data Register        */
+#define SEQ_D   0x3C5       /* Sequencer Data Register                  */
+#define MIS_R   0x3CC       /* Misc Output Read Register                */
+#define MIS_W   0x3C2       /* Misc Output Write Register               */
+#define IS1_R   0x3DA       /* Input Status Register 1                  */
+#define PEL_IW  0x3C8       /* PEL Write Index                          */
+#define PEL_IR  0x3C7       /* PEL Read Index                           */
+#define PEL_D   0x3C9       /* PEL Data Register                        */
+
+/* standard VGA indexes max counts */
+#define CRT_C   24          /* 24  CRT Controller Registers             */
+#define ATT_C   21          /* 21  Attribute Controller Registers       */
+#define GRA_C   9           /* 9   Graphics Controller Registers        */
+#define SEQ_C   5           /* 5   Sequencer Registers                  */
+#define MIS_C   1           /* 1   Misc Output Register                 */
+#define PAL_C   768         /* 768 Palette Registers                    */
+#define FONT_C  8192        /* Total size of character generator RAM    */
+
+/* VGA registers saving indexes */
+#define CRT     0           /* CRT Controller Registers start           */
+#define ATT     (CRT+CRT_C) /* Attribute Controller Registers start     */
+#define GRA     (ATT+ATT_C) /* Graphics Controller Registers start      */
+#define SEQ     (GRA+GRA_C) /* Sequencer Registers                      */
+#define MIS     (SEQ+SEQ_C) /* General Registers                        */
+#define PAL     (MIS+MIS_C) /* VGA Palette Registers                    */
+#define FONT    (PAL+PAL_C) /* VGA font data                            */
+
+/* Macros for port I/O with arguments reversed */
+
+#define _port_out(v,p)  PM_outpb(p,(uchar)(v))
+#define _port_in(p)     PM_inpb(p)
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Returns the size of the VGA state buffer.
+****************************************************************************/
+int PMAPI PM_getVGAStateSize(void)
+{
+    return CRT_C + ATT_C + GRA_C + SEQ_C + MIS_C + PAL_C + FONT_C;
+}
+
+/****************************************************************************
+REMARKS:
+Delay for a short period of time.
+****************************************************************************/
+static void vga_delay(void)
+{
+    int i;
+
+    /* For the loop here we program the POST register. The length of this
+     * delay is dependant only on ISA bus speed, but it is enough for
+     * what we need.
+     */
+    for (i = 0; i <= 10; i++)
+	PM_outpb(0x80, 0);
+}
+
+/****************************************************************************
+PARAMETERS:
+port    - I/O port to read value from
+index   - Port index to read
+
+RETURNS:
+Byte read from 'port' register 'index'.
+****************************************************************************/
+static ushort vga_rdinx(
+    ushort port,
+    ushort index)
+{
+    PM_outpb(port,(uchar)index);
+    return PM_inpb(port+1);
+}
+
+/****************************************************************************
+PARAMETERS:
+port    - I/O port to write to
+index   - Port index to write
+value   - Byte to write to port
+
+REMARKS:
+Writes a byte value to the 'port' register 'index'.
+****************************************************************************/
+static void vga_wrinx(
+    ushort port,
+    ushort index,
+    ushort value)
+{
+    PM_outpb(port,(uchar)index);
+    PM_outpb(port+1,(uchar)value);
+}
+
+/****************************************************************************
+REMARKS:
+Save the color palette values
+****************************************************************************/
+static void vga_savepalette(
+    uchar *pal)
+{
+    int i;
+
+    _port_out(0, PEL_IR);
+    for (i = 0; i < 768; i++) {
+	vga_delay();
+	*pal++ = _port_in(PEL_D);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Restore the color palette values
+****************************************************************************/
+static void vga_restorepalette(
+    const uchar *pal)
+{
+    int i;
+
+    /* restore saved palette */
+    _port_out(0, PEL_IW);
+    for (i = 0; i < 768; i++) {
+	vga_delay();
+	_port_out(*pal++, PEL_D);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Read the font data from the VGA character generator RAM
+****************************************************************************/
+static void vga_saveFont(
+    uchar *data)
+{
+    uchar   *A0000Ptr = PM_getA0000Pointer();
+    uchar   save[7];
+
+    /* Enable access to character generator RAM */
+    save[0] = (uchar)vga_rdinx(SEQ_I,0x00);
+    save[1] = (uchar)vga_rdinx(SEQ_I,0x02);
+    save[2] = (uchar)vga_rdinx(SEQ_I,0x04);
+    save[3] = (uchar)vga_rdinx(SEQ_I,0x00);
+    save[4] = (uchar)vga_rdinx(GRA_I,0x04);
+    save[5] = (uchar)vga_rdinx(GRA_I,0x05);
+    save[6] = (uchar)vga_rdinx(GRA_I,0x06);
+    vga_wrinx(SEQ_I,0x00,0x01);
+    vga_wrinx(SEQ_I,0x02,0x04);
+    vga_wrinx(SEQ_I,0x04,0x07);
+    vga_wrinx(SEQ_I,0x00,0x03);
+    vga_wrinx(GRA_I,0x04,0x02);
+    vga_wrinx(GRA_I,0x05,0x00);
+    vga_wrinx(GRA_I,0x06,0x00);
+
+    /* Copy character generator RAM */
+    memcpy(data,A0000Ptr,FONT_C);
+
+    /* Restore VGA state */
+    vga_wrinx(SEQ_I,0x00,save[0]);
+    vga_wrinx(SEQ_I,0x02,save[1]);
+    vga_wrinx(SEQ_I,0x04,save[2]);
+    vga_wrinx(SEQ_I,0x00,save[3]);
+    vga_wrinx(GRA_I,0x04,save[4]);
+    vga_wrinx(GRA_I,0x05,save[5]);
+    vga_wrinx(GRA_I,0x06,save[6]);
+}
+
+/****************************************************************************
+REMARKS:
+Downloads the font data to the VGA character generator RAM
+****************************************************************************/
+static void vga_restoreFont(
+    const uchar *data)
+{
+    uchar   *A0000Ptr = PM_getA0000Pointer();
+
+    /* Enable access to character generator RAM */
+    vga_wrinx(SEQ_I,0x00,0x01);
+    vga_wrinx(SEQ_I,0x02,0x04);
+    vga_wrinx(SEQ_I,0x04,0x07);
+    vga_wrinx(SEQ_I,0x00,0x03);
+    vga_wrinx(GRA_I,0x04,0x02);
+    vga_wrinx(GRA_I,0x05,0x00);
+    vga_wrinx(GRA_I,0x06,0x00);
+
+    /* Copy font back to character generator RAM */
+    memcpy(A0000Ptr,data,FONT_C);
+}
+
+/****************************************************************************
+REMARKS:
+Save the state of all VGA compatible registers
+****************************************************************************/
+void PMAPI PM_saveVGAState(
+    void *stateBuf)
+{
+    uchar   *regs = stateBuf;
+    int     i;
+
+    /* Save state of VGA registers */
+    for (i = 0; i < CRT_C; i++) {
+	_port_out(i, CRT_I);
+	regs[CRT + i] = _port_in(CRT_D);
+	}
+    for (i = 0; i < ATT_C; i++) {
+	_port_in(IS1_R);
+	vga_delay();
+	_port_out(i, ATT_IW);
+	vga_delay();
+	regs[ATT + i] = _port_in(ATT_R);
+	vga_delay();
+	}
+    for (i = 0; i < GRA_C; i++) {
+	_port_out(i, GRA_I);
+	regs[GRA + i] = _port_in(GRA_D);
+	}
+    for (i = 0; i < SEQ_C; i++) {
+	_port_out(i, SEQ_I);
+	regs[SEQ + i] = _port_in(SEQ_D);
+	}
+    regs[MIS] = _port_in(MIS_R);
+
+    /* Save the VGA palette values */
+    vga_savepalette(&regs[PAL]);
+
+    /* Save the VGA character generator RAM */
+    vga_saveFont(&regs[FONT]);
+
+    /* Turn the VGA display back on */
+    PM_vgaUnblankDisplay();
+}
+
+/****************************************************************************
+REMARKS:
+Retore the state of all VGA compatible registers
+****************************************************************************/
+void PMAPI PM_restoreVGAState(
+    const void *stateBuf)
+{
+    const uchar *regs = stateBuf;
+    int         i;
+
+    /* Blank the display before we start the restore */
+    PM_vgaBlankDisplay();
+
+    /* Restore the VGA character generator RAM */
+    vga_restoreFont(&regs[FONT]);
+
+    /* Restore the VGA palette values */
+    vga_restorepalette(&regs[PAL]);
+
+    /* Restore the state of the VGA compatible registers */
+    _port_out(regs[MIS], MIS_W);
+
+    /* Delay to allow clock change to settle */
+    for (i = 0; i < 10; i++)
+	vga_delay();
+
+    /* Synchronous reset on */
+    _port_out(0x00,SEQ_I);
+    _port_out(0x01,SEQ_D);
+
+    /* Write seqeuencer registers */
+    _port_out(1, SEQ_I);
+    _port_out(regs[SEQ + 1] | 0x20, SEQ_D);
+    for (i = 2; i < SEQ_C; i++) {
+	_port_out(i, SEQ_I);
+	_port_out(regs[SEQ + i], SEQ_D);
+	}
+
+    /* Synchronous reset off */
+    _port_out(0x00,SEQ_I);
+    _port_out(0x03,SEQ_D);
+
+    /* Deprotect CRT registers 0-7 and write CRTC */
+    _port_out(0x11, CRT_I);
+    _port_out(_port_in(CRT_D) & 0x7F, CRT_D);
+    for (i = 0; i < CRT_C; i++) {
+	_port_out(i, CRT_I);
+	_port_out(regs[CRT + i], CRT_D);
+	}
+    for (i = 0; i < GRA_C; i++) {
+	_port_out(i, GRA_I);
+	_port_out(regs[GRA + i], GRA_D);
+	}
+    for (i = 0; i < ATT_C; i++) {
+	_port_in(IS1_R);        /* reset flip-flop */
+	vga_delay();
+	_port_out(i, ATT_IW);
+	vga_delay();
+	_port_out(regs[ATT + i], ATT_IW);
+	vga_delay();
+	}
+
+    /* Ensure the VGA screen is turned on */
+    PM_vgaUnblankDisplay();
+}
+
+/****************************************************************************
+REMARKS:
+Disables the VGA display for screen output making it blank.
+****************************************************************************/
+void PMAPI PM_vgaBlankDisplay(void)
+{
+    /* Turn screen off */
+    _port_out(0x01, SEQ_I);
+    _port_out(_port_in(SEQ_D) | 0x20, SEQ_D);
+
+    /* Disable video output */
+    _port_in(IS1_R);
+    vga_delay();
+     _port_out(0x00, ATT_IW);
+}
+
+/****************************************************************************
+REMARKS:
+Enables the VGA display for screen output.
+****************************************************************************/
+void PMAPI PM_vgaUnblankDisplay(void)
+{
+    /* Turn screen back on */
+    _port_out(0x01, SEQ_I);
+    _port_out(_port_in(SEQ_D) & 0xDF, SEQ_D);
+
+    /* Enable video output */
+    _port_in(IS1_R);
+    vga_delay();
+    _port_out(0x20, ATT_IW);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c
new file mode 100755
index 0000000..ac62e81
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c
@@ -0,0 +1,808 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Main module to implement the Zen Timer support functions.
+*
+****************************************************************************/
+
+#include "ztimer.h"
+#include "pmapi.h"
+#include "oshdr.h"
+#if !defined(__WIN32_VXD__) && !defined(__OS2_VDD__) && !defined(__NT_DRIVER__)
+#include <stdio.h>
+#include <string.h>
+#endif
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* External Intel assembler functions */
+#ifdef  __INTEL__
+/* {secret} */
+ibool   _ASMAPI _CPU_haveCPUID(void);
+/* {secret} */
+ibool   _ASMAPI _CPU_check80386(void);
+/* {secret} */
+ibool   _ASMAPI _CPU_check80486(void);
+/* {secret} */
+uint    _ASMAPI _CPU_checkCPUID(void);
+/* {secret} */
+uint    _ASMAPI _CPU_getCPUIDModel(void);
+/* {secret} */
+uint    _ASMAPI _CPU_getCPUIDStepping(void);
+/* {secret} */
+uint    _ASMAPI _CPU_getCPUIDFeatures(void);
+/* {secret} */
+uint    _ASMAPI _CPU_getCacheSize(void);
+/* {secret} */
+uint    _ASMAPI _CPU_have3DNow(void);
+/* {secret} */
+ibool   _ASMAPI _CPU_checkClone(void);
+/* {secret} */
+void    _ASMAPI _CPU_readTimeStamp(CPU_largeInteger *time);
+/* {secret} */
+void    _ASMAPI _CPU_runBSFLoop(ulong iterations);
+/* {secret} */
+ulong   _ASMAPI _CPU_mulDiv(ulong a,ulong b,ulong c);
+/* {secret} */
+void ZTimerQuickInit(void);
+#define CPU_HaveMMX     0x00800000
+#define CPU_HaveRDTSC   0x00000010
+#define CPU_HaveSSE     0x02000000
+#endif
+
+#if     defined(__SMX32__)
+#include "smx/cpuinfo.c"
+#elif   defined(__RTTARGET__)
+#include "rttarget/cpuinfo.c"
+#elif   defined(__REALDOS__)
+#include "dos/cpuinfo.c"
+#elif   defined(__NT_DRIVER__)
+#include "ntdrv/cpuinfo.c"
+#elif   defined(__WIN32_VXD__)
+#include "vxd/cpuinfo.c"
+#elif   defined(__WINDOWS32__)
+#include "win32/cpuinfo.c"
+#elif   defined(__OS2_VDD__)
+#include "vdd/cpuinfo.c"
+#elif   defined(__OS2__)
+#include "os2/cpuinfo.c"
+#elif   defined(__LINUX__)
+#include "linux/cpuinfo.c"
+#elif   defined(__QNX__)
+#include "qnx/cpuinfo.c"
+#elif   defined(__BEOS__)
+#include "beos/cpuinfo.c"
+#else
+#error  CPU library not ported to this platform yet!
+#endif
+
+/*------------------------ Public interface routines ----------------------*/
+
+/****************************************************************************
+REMARKS:
+Read an I/O port location.
+****************************************************************************/
+static uchar rdinx(
+    int port,
+    int index)
+{
+    PM_outpb(port,(uchar)index);
+    return PM_inpb(port+1);
+}
+
+/****************************************************************************
+REMARKS:
+Write an I/O port location.
+****************************************************************************/
+static void wrinx(
+    ushort port,
+    ushort index,
+    ushort value)
+{
+    PM_outpb(port,(uchar)index);
+    PM_outpb(port+1,(uchar)value);
+}
+
+/****************************************************************************
+REMARKS:
+Enables the Cyrix CPUID instruction to properly detect MediaGX and 6x86
+processors.
+****************************************************************************/
+static void _CPU_enableCyrixCPUID(void)
+{
+    uchar   ccr3;
+
+    PM_init();
+    ccr3 = rdinx(0x22,0xC3);
+    wrinx(0x22,0xC3,(uchar)(ccr3 | 0x10));
+    wrinx(0x22,0xE8,(uchar)(rdinx(0x22,0xE8) | 0x80));
+    wrinx(0x22,0xC3,ccr3);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns the type of processor in the system.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+Numerical identifier for the installed processor
+
+REMARKS:
+Returns the type of processor in the system. Note that if the CPU is an
+unknown Pentium family processor that we don't have an enumeration for,
+the return value will be greater than or equal to the value of CPU_UnkPentium
+(depending on the value returned by the CPUID instruction).
+
+SEE ALSO:
+CPU_getProcessorSpeed, CPU_haveMMX, CPU_getProcessorName
+****************************************************************************/
+uint ZAPI CPU_getProcessorType(void)
+{
+#if     defined(__INTEL__)
+    uint            cpu,vendor,model,cacheSize;
+    static ibool    firstTime = true;
+
+    if (_CPU_haveCPUID()) {
+	cpu = _CPU_checkCPUID();
+	vendor = cpu & ~CPU_mask;
+	if (vendor == CPU_Intel) {
+	    /* Check for Intel processors */
+	    switch (cpu & CPU_mask) {
+		case 4: cpu = CPU_i486;         break;
+		case 5: cpu = CPU_Pentium;      break;
+		case 6:
+		    if ((model = _CPU_getCPUIDModel()) == 1)
+			cpu = CPU_PentiumPro;
+		    else if (model <= 6) {
+			cacheSize = _CPU_getCacheSize();
+			if ((model == 5 && cacheSize == 0) ||
+			    (model == 5 && cacheSize == 256) ||
+			    (model == 6 && cacheSize == 128))
+			    cpu = CPU_Celeron;
+			else
+			    cpu = CPU_PentiumII;
+			}
+		    else if (model >= 7) {
+			/* Model 7 == Pentium III */
+			/* Model 8 == Celeron/Pentium III Coppermine */
+			cacheSize = _CPU_getCacheSize();
+			if ((model == 8 && cacheSize == 128))
+			    cpu = CPU_Celeron;
+			else
+			    cpu = CPU_PentiumIII;
+			}
+		    break;
+		default:
+		    cpu = CPU_UnkIntel;
+		}
+	    }
+	else if (vendor == CPU_Cyrix) {
+	    /* Check for Cyrix processors */
+	    switch (cpu & CPU_mask) {
+		case 4:
+		    if ((model = _CPU_getCPUIDModel()) == 4)
+			cpu = CPU_CyrixMediaGX;
+		    else
+			cpu = CPU_UnkCyrix;
+		    break;
+		case 5:
+		    if ((model = _CPU_getCPUIDModel()) == 2)
+			cpu = CPU_Cyrix6x86;
+		    else if (model == 4)
+			cpu = CPU_CyrixMediaGXm;
+		    else
+			cpu = CPU_UnkCyrix;
+		    break;
+		case 6:
+		    if ((model = _CPU_getCPUIDModel()) <= 1)
+			cpu = CPU_Cyrix6x86MX;
+		    else
+			cpu = CPU_UnkCyrix;
+		    break;
+		default:
+		    cpu = CPU_UnkCyrix;
+		}
+	    }
+	else if (vendor == CPU_AMD) {
+	    /* Check for AMD processors */
+	    switch (cpu & CPU_mask) {
+		case 4:
+		    if ((model = _CPU_getCPUIDModel()) == 0)
+			cpu = CPU_AMDAm5x86;
+		    else
+			cpu = CPU_AMDAm486;
+		    break;
+		case 5:
+		    if ((model = _CPU_getCPUIDModel()) <= 3)
+			cpu = CPU_AMDK5;
+		    else if (model <= 7)
+			cpu = CPU_AMDK6;
+		    else if (model == 8)
+			cpu = CPU_AMDK6_2;
+		    else if (model == 9)
+			cpu = CPU_AMDK6_III;
+		    else if (model == 13) {
+			if (_CPU_getCPUIDStepping() <= 3)
+			    cpu = CPU_AMDK6_IIIplus;
+			else
+			    cpu = CPU_AMDK6_2plus;
+			}
+		    else
+			cpu = CPU_UnkAMD;
+		    break;
+		case 6:
+		    if ((model = _CPU_getCPUIDModel()) == 3)
+			cpu = CPU_AMDDuron;
+		    else
+			cpu = CPU_AMDAthlon;
+		    break;
+		default:
+		    cpu = CPU_UnkAMD;
+		}
+	    }
+	else if (vendor == CPU_IDT) {
+	    /* Check for IDT WinChip processors */
+	    switch (cpu & CPU_mask) {
+		case 5:
+		    if ((model = _CPU_getCPUIDModel()) <= 4)
+			cpu = CPU_WinChipC6;
+		    else if (model == 8)
+			cpu = CPU_WinChip2;
+		    else
+			cpu = CPU_UnkIDT;
+		    break;
+		default:
+		    cpu = CPU_UnkIDT;
+		}
+	    }
+	else {
+	    /* Assume a Pentium compatible Intel clone */
+	    cpu = CPU_Pentium;
+	    }
+	return cpu | vendor | (_CPU_getCPUIDStepping() << CPU_steppingShift);
+	}
+    else {
+	if (_CPU_check80386())
+	    cpu = CPU_i386;
+	else  if (_CPU_check80486()) {
+	    /* If we get here we may have a Cyrix processor so we can try
+	     * enabling the CPUID instruction and trying again.
+	     */
+	    if (firstTime) {
+		firstTime = false;
+		_CPU_enableCyrixCPUID();
+		return CPU_getProcessorType();
+		}
+	    cpu = CPU_i486;
+	    }
+	else
+	    cpu = CPU_Pentium;
+	if (!_CPU_checkClone())
+	    return cpu | CPU_Intel;
+	return cpu;
+	}
+#elif   defined(__ALPHA__)
+    return CPU_Alpha;
+#elif   defined(__MIPS__)
+    return CPU_Mips;
+#elif   defined(__PPC__)
+    return CPU_PowerPC;
+#endif
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns true if the processor supports Intel MMX extensions.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+True if MMX is available, false if not.
+
+REMARKS:
+This function determines if the processor supports the Intel MMX extended
+instruction set.
+
+SEE ALSO:
+CPU_getProcessorType, CPU_getProcessorSpeed, CPU_have3DNow, CPU_haveSSE,
+CPU_getProcessorName
+****************************************************************************/
+ibool ZAPI CPU_haveMMX(void)
+{
+#ifdef  __INTEL__
+    if (_CPU_haveCPUID())
+	return (_CPU_getCPUIDFeatures() & CPU_HaveMMX) != 0;
+    return false;
+#else
+    return false;
+#endif
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns true if the processor supports AMD 3DNow! extensions.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+True if 3DNow! is available, false if not.
+
+REMARKS:
+This function determines if the processor supports the AMD 3DNow! extended
+instruction set.
+
+SEE ALSO:
+CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_haveSSE,
+CPU_getProcessorName
+****************************************************************************/
+ibool ZAPI CPU_have3DNow(void)
+{
+#ifdef  __INTEL__
+    if (_CPU_haveCPUID())
+	return _CPU_have3DNow();
+    return false;
+#else
+    return false;
+#endif
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns true if the processor supports Intel KNI extensions.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+True if Intel KNI is available, false if not.
+
+REMARKS:
+This function determines if the processor supports the Intel KNI extended
+instruction set.
+
+SEE ALSO:
+CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_have3DNow,
+CPU_getProcessorName
+****************************************************************************/
+ibool ZAPI CPU_haveSSE(void)
+{
+#ifdef  __INTEL__
+    if (_CPU_haveCPUID())
+	return (_CPU_getCPUIDFeatures() & CPU_HaveSSE) != 0;
+    return false;
+#else
+    return false;
+#endif
+}
+
+/****************************************************************************
+RETURNS:
+True if the RTSC instruction is available, false if not.
+
+REMARKS:
+This function determines if the processor supports the Intel RDTSC
+instruction, for high precision timing. If the processor is not an Intel or
+Intel clone CPU, this function will always return false.
+
+DESCRIPTION:
+Returns true if the processor supports RDTSC extensions.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+True if RTSC is available, false if not.
+
+REMARKS:
+This function determines if the processor supports the RDTSC instruction
+for reading the processor time stamp counter.
+
+SEE ALSO:
+CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_have3DNow,
+CPU_getProcessorName
+****************************************************************************/
+ibool ZAPI CPU_haveRDTSC(void)
+{
+#ifdef  __INTEL__
+    if (_CPU_haveCPUID())
+	return (_CPU_getCPUIDFeatures() & CPU_HaveRDTSC) != 0;
+    return false;
+#else
+    return false;
+#endif
+}
+
+#ifdef  __INTEL__
+
+#define ITERATIONS      16000
+#define SAMPLINGS       2
+#define INNER_LOOPS     400
+
+/****************************************************************************
+REMARKS:
+If processor does not support time stamp reading, but is at least a 386 or
+above, utilize method of timing a loop of BSF instructions which take a
+known number of cycles to run on i386(tm), i486(tm), and Pentium(R)
+processors.
+****************************************************************************/
+static ulong GetBSFCpuSpeed(
+    ulong cycles)
+{
+    CPU_largeInteger t0,t1,count_freq;
+    ulong   ticks;              /* Microseconds elapsed during test     */
+    ulong   current;            /* Variable to store time elapsed       */
+    int     i,j,iPriority;
+    ulong   lowest  = (ulong)-1;
+
+    iPriority = SetMaxThreadPriority();
+    GetCounterFrequency(&count_freq);
+    for (i = 0; i < SAMPLINGS; i++) {
+	GetCounter(&t0);
+	for (j = 0; j < INNER_LOOPS; j++)
+	    _CPU_runBSFLoop(ITERATIONS);
+	GetCounter(&t1);
+	current = t1.low - t0.low;
+	if (current < lowest)
+	    lowest = current;
+	}
+    RestoreThreadPriority(iPriority);
+
+    /* Compute frequency */
+    ticks = _CPU_mulDiv(lowest,1000000,count_freq.low);
+    if ((ticks % count_freq.low) > (count_freq.low/2))
+	ticks++;            /* Round up if necessary */
+    if (ticks == 0)
+	return 0;
+    return ((cycles*INNER_LOOPS)/ticks);
+}
+
+#define TOLERANCE       1
+
+/****************************************************************************
+REMARKS:
+On processors supporting the Read Time Stamp opcode, compare elapsed
+time on the High-Resolution Counter with elapsed cycles on the Time
+Stamp Register.
+
+The inner loop runs up to 20 times oruntil the average of the previous
+three calculated frequencies is within 1 MHz of each of the individual
+calculated frequencies. This resampling increases the accuracy of the
+results since outside factors could affect this calculation.
+****************************************************************************/
+static ulong GetRDTSCCpuSpeed(
+    ibool accurate)
+{
+    CPU_largeInteger    t0,t1,s0,s1,count_freq;
+    u64                 stamp0, stamp1, ticks0, ticks1;
+    u64                 total_cycles, cycles, hz, freq;
+    u64                 total_ticks, ticks;
+    int                 tries,iPriority;
+    ulong               maxCount;
+
+    PM_set64_32(total_cycles,0);
+    PM_set64_32(total_ticks,0);
+    maxCount = accurate ? 600000 : 30000;
+    iPriority = SetMaxThreadPriority();
+    GetCounterFrequency(&count_freq);
+    PM_set64(freq,count_freq.high,count_freq.low);
+    for (tries = 0; tries < 3; tries++) {
+	/* Loop until 100 ticks have passed since last read of hi-res
+	 * counter. This accounts for overhead later.
+	 */
+	GetCounter(&t0);
+	t1.low = t0.low;
+	t1.high = t0.high;
+	while ((t1.low - t0.low) < 100) {
+	    GetCounter(&t1);
+	    _CPU_readTimeStamp(&s0);
+	    }
+
+	/* Loop until 30000 ticks have passed since last read of hi-res counter.
+	 * This allows for elapsed time for sampling. For a hi-res frequency
+	 * of 1MHz, this is about 0.03 of a second. The frequency reported
+	 * by the OS dependent code should be tuned to provide a good
+	 * sample period depending on the accuracy of the OS timers (ie:
+	 * if the accuracy is lower, lower the frequency to spend more time
+	 * in the inner loop to get better accuracy).
+	 */
+	t0.low = t1.low;
+	t0.high = t1.high;
+	while ((t1.low - t0.low) < maxCount) {
+	    GetCounter(&t1);
+	    _CPU_readTimeStamp(&s1);
+	    }
+
+	/* Find the difference during the timing loop */
+	PM_set64(stamp0,s0.high,s0.low);
+	PM_set64(stamp1,s1.high,s1.low);
+	PM_set64(ticks0,t0.high,t0.low);
+	PM_set64(ticks1,t1.high,t1.low);
+	PM_sub64(cycles,stamp1,stamp0);
+	PM_sub64(ticks,ticks1,ticks0);
+
+	/* Sum up the results */
+	PM_add64(total_ticks,total_ticks,ticks);
+	PM_add64(total_cycles,total_cycles,cycles);
+	}
+    RestoreThreadPriority(iPriority);
+
+    /* Compute frequency in Hz */
+    PM_mul64(hz,total_cycles,freq);
+    PM_div64(hz,hz,total_ticks);
+    return PM_64to32(hz);
+}
+
+#endif  /* __INTEL__ */
+
+/****************************************************************************
+DESCRIPTION:
+Returns the speed of the processor in MHz.
+
+HEADER:
+ztimer.h
+
+PARAMETERS:
+accurate    - True of the speed should be measured accurately
+
+RETURNS:
+Processor speed in MHz.
+
+REMARKS:
+This function returns the speed of the CPU in MHz. Note that if the speed
+cannot be determined, this function will return 0.
+
+If the accurate parameter is set to true, this function will spend longer
+profiling the speed of the CPU, and will not round the CPU speed that is
+reported. This is important for highly accurate timing using the Pentium
+RDTSC instruction, but it does take a lot longer for the profiling to
+produce accurate results.
+
+SEE ALSO:
+CPU_getProcessorSpeedInHz, CPU_getProcessorType, CPU_haveMMX,
+CPU_getProcessorName
+****************************************************************************/
+ulong ZAPI CPU_getProcessorSpeed(
+    ibool accurate)
+{
+#if defined(__INTEL__)
+    /* Number of cycles needed to execute a single BSF instruction on i386+
+     * processors.
+     */
+    ulong   cpuSpeed;
+    uint    i;
+    static  ulong intel_cycles[] = {
+	115,47,43,
+	};
+    static  ulong cyrix_cycles[] = {
+	38,38,52,52,
+	};
+    static  ulong amd_cycles[] = {
+	49,
+	};
+    static  ulong known_speeds[] = {
+	1000,950,900,850,800,750,700,650,600,550,500,450,433,400,350,
+	333,300,266,233,200,166,150,133,120,100,90,75,66,60,50,33,20,0,
+	};
+
+    if (CPU_haveRDTSC()) {
+	cpuSpeed = (GetRDTSCCpuSpeed(accurate) + 500000) / 1000000;
+	}
+    else {
+	int type = CPU_getProcessorType();
+	int processor = type & CPU_mask;
+	int vendor = type & CPU_familyMask;
+	if (vendor == CPU_Intel)
+	    cpuSpeed = GetBSFCpuSpeed(ITERATIONS * intel_cycles[processor - CPU_i386]);
+	else if (vendor == CPU_Cyrix)
+	    cpuSpeed = GetBSFCpuSpeed(ITERATIONS * cyrix_cycles[processor - CPU_Cyrix6x86]);
+	else if (vendor == CPU_AMD)
+	    cpuSpeed = GetBSFCpuSpeed(ITERATIONS * amd_cycles[0]);
+	else
+	    return 0;
+	}
+
+    /* Now normalise the results given known processors speeds, if the
+     * speed we measure is within 2MHz of the expected values
+     */
+    if (!accurate) {
+	for (i = 0; known_speeds[i] != 0; i++) {
+	    if (cpuSpeed >= (known_speeds[i]-3) && cpuSpeed <= (known_speeds[i]+3)) {
+		return known_speeds[i];
+		}
+	    }
+	}
+    return cpuSpeed;
+#else
+    return 0;
+#endif
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns the speed of the processor in Hz.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+Accurate processor speed in Hz.
+
+REMARKS:
+This function returns the accurate speed of the CPU in Hz. Note that if the
+speed cannot be determined, this function will return 0.
+
+This function is similar to the CPU_getProcessorSpeed function, except that
+it attempts to accurately measure the CPU speed in Hz. This is used
+internally in the Zen Timer libraries to provide accurate real world timing
+information. This is important for highly accurate timing using the Pentium
+RDTSC instruction, but it does take a lot longer for the profiling to
+produce accurate results.
+
+SEE ALSO:
+CPU_getProcessorSpeed, CPU_getProcessorType, CPU_haveMMX,
+CPU_getProcessorName
+****************************************************************************/
+ulong ZAPI CPU_getProcessorSpeedInHZ(
+    ibool accurate)
+{
+#if defined(__INTEL__)
+    if (CPU_haveRDTSC()) {
+	return GetRDTSCCpuSpeed(accurate);
+	}
+    return CPU_getProcessorSpeed(false) * 1000000;
+#else
+    return 0;
+#endif
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns a string defining the speed and name of the processor.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+Processor name string.
+
+REMARKS:
+This function returns an English string describing the speed and name of the
+CPU.
+
+SEE ALSO:
+CPU_getProcessorType, CPU_haveMMX, CPU_getProcessorName
+****************************************************************************/
+char * ZAPI CPU_getProcessorName(void)
+{
+#if defined(__INTEL__)
+    static int  cpu,speed = -1;
+    static char name[80];
+
+    if (speed == -1) {
+	cpu = CPU_getProcessorType();
+	speed = CPU_getProcessorSpeed(false);
+	}
+    sprintf(name,"%d MHz ", speed);
+    switch (cpu & CPU_mask) {
+	case CPU_i386:
+	    strcat(name,"Intel i386 processor");
+	    break;
+	case CPU_i486:
+	    strcat(name,"Intel i486 processor");
+	    break;
+	case CPU_Pentium:
+	    strcat(name,"Intel Pentium processor");
+	    break;
+	case CPU_PentiumPro:
+	    strcat(name,"Intel Pentium Pro processor");
+	    break;
+	case CPU_PentiumII:
+	    strcat(name,"Intel Pentium II processor");
+	    break;
+	case CPU_Celeron:
+	    strcat(name,"Intel Celeron processor");
+	    break;
+	case CPU_PentiumIII:
+	    strcat(name,"Intel Pentium III processor");
+	    break;
+	case CPU_UnkIntel:
+	    strcat(name,"Unknown Intel processor");
+	    break;
+	case CPU_Cyrix6x86:
+	    strcat(name,"Cyrix 6x86 processor");
+	    break;
+	case CPU_Cyrix6x86MX:
+	    strcat(name,"Cyrix 6x86MX processor");
+	    break;
+	case CPU_CyrixMediaGX:
+	    strcat(name,"Cyrix MediaGX processor");
+	    break;
+	case CPU_CyrixMediaGXm:
+	    strcat(name,"Cyrix MediaGXm processor");
+	    break;
+	case CPU_UnkCyrix:
+	    strcat(name,"Unknown Cyrix processor");
+	    break;
+	case CPU_AMDAm486:
+	    strcat(name,"AMD Am486 processor");
+	    break;
+	case CPU_AMDAm5x86:
+	    strcat(name,"AMD Am5x86 processor");
+	    break;
+	case CPU_AMDK5:
+	    strcat(name,"AMD K5 processor");
+	    break;
+	case CPU_AMDK6:
+	    strcat(name,"AMD K6 processor");
+	    break;
+	case CPU_AMDK6_2:
+	    strcat(name,"AMD K6-2 processor");
+	    break;
+	case CPU_AMDK6_III:
+	    strcat(name,"AMD K6-III processor");
+	    break;
+	case CPU_AMDK6_2plus:
+	    strcat(name,"AMD K6-2+ processor");
+	    break;
+	case CPU_AMDK6_IIIplus:
+	    strcat(name,"AMD K6-III+ processor");
+	    break;
+	case CPU_UnkAMD:
+	    strcat(name,"Unknown AMD processor");
+	    break;
+	case CPU_AMDAthlon:
+	    strcat(name,"AMD Athlon processor");
+	    break;
+	case CPU_AMDDuron:
+	    strcat(name,"AMD Duron processor");
+	    break;
+	case CPU_WinChipC6:
+	    strcat(name,"IDT WinChip C6 processor");
+	    break;
+	case CPU_WinChip2:
+	    strcat(name,"IDT WinChip 2 processor");
+	    break;
+	case CPU_UnkIDT:
+	    strcat(name,"Unknown IDT processor");
+	    break;
+	default:
+	    strcat(name,"Unknown processor");
+	}
+    if (CPU_haveMMX())
+	strcat(name," with MMX(R)");
+    if (CPU_have3DNow())
+	strcat(name,", 3DNow!(R)");
+    if (CPU_haveSSE())
+	strcat(name,", SSE(R)");
+    return name;
+#else
+    return "Unknown";
+#endif
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/debug.c b/board/MAI/bios_emulator/scitech/src/pm/debug.c
new file mode 100755
index 0000000..751bf09
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/debug.c
@@ -0,0 +1,107 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Main module containing debug checking features.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#ifdef  __WIN32_VXD__
+#include "vxdfile.h"
+#elif defined(__NT_DRIVER__)
+#include "ntdriver.h"
+#elif defined(__OS2_VDD__)
+#include "vddfile.h"
+#else
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#endif
+
+/*---------------------------- Global variables ---------------------------*/
+
+/* {secret} */
+void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line) = _CHK_defaultFail;
+static char logFile[256] = "";
+
+/*----------------------------- Implementation ----------------------------*/
+
+#ifdef  CHECKED
+void _CHK_defaultFail(
+    int fatal,
+    const char *msg,
+    const char *cond,
+    const char *file,
+    int line)
+{
+    FILE    *f;
+    char    buf[256];
+
+    if (logFile[0] == 0) {
+	strcpy(logFile,PM_getNucleusPath());
+	PM_backslash(logFile);
+	strcat(logFile,"scitech.log");
+	}
+    if ((f = fopen(logFile,"a+")) != NULL) {
+#if defined(__WIN32_VXD__) || defined(__OS2_VDD__) || defined(__NT_DRIVER__)
+	sprintf(buf,msg,cond,file,line);
+	fwrite(buf,1,strlen(buf),f);
+#else
+	fprintf(f,msg,cond,file,line);
+#endif
+	fclose(f);
+	}
+    if (fatal) {
+	sprintf(buf,"Check failed: check '%s' for details", logFile);
+	PM_fatalError(buf);
+	}
+}
+#endif
+
+/****************************************************************************
+DESCRIPTION:
+Sets the location of the debug log file.
+
+HEADER:
+pmapi.h
+
+PARAMETERS:
+logFilePath - Full file and path name to debug log file.
+
+REMARKS:
+Sets the name and location of the debug log file. The debug log file is
+created and written to when runtime checks, warnings and failure conditions
+are logged to disk when code is compiled in CHECKED mode. By default the
+log file is called 'scitech.log' and goes into the current SciTech Nucleus
+path for the application. You can use this function to set the filename
+and location of the debug log file to your own application specific
+directory.
+****************************************************************************/
+void PMAPI PM_setDebugLog(
+    const char *logFilePath)
+{
+    strcpy(logFile,logFilePath);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm
new file mode 100755
index 0000000..36dcaab
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm
@@ -0,0 +1,194 @@
+;****************************************************************************
+;*
+;*                  SciTech Multi-platform Graphics Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler
+;* Environment: IBM PC (MS DOS)
+;*
+;* Description: Assembly language support routines for the event module.
+;*
+;****************************************************************************
+
+        ideal
+
+include "scitech.mac"           ; Memory model macros
+
+ifdef flatmodel
+
+header  _event                  ; Set up memory model
+
+begdataseg  _event
+
+    cextern  _EVT_biosPtr,DPTR
+
+ifdef   USE_NASM
+%define KB_HEAD     WORD esi+01Ah   ; Keyboard buffer head in BIOS data area
+%define KB_TAIL     WORD esi+01Ch   ; Keyboard buffer tail in BIOS data area
+%define KB_START    WORD esi+080h   ; Start of keyboard buffer in BIOS data area
+%define KB_END      WORD esi+082h   ; End of keyboard buffer in BIOS data area
+else
+KB_HEAD     EQU WORD esi+01Ah       ; Keyboard buffer head in BIOS data area
+KB_TAIL     EQU WORD esi+01Ch       ; Keyboard buffer tail in BIOS data area
+KB_START    EQU WORD esi+080h       ; Start of keyboard buffer in BIOS data area
+KB_END      EQU WORD esi+082h       ; End of keyboard buffer in BIOS data area
+endif
+
+enddataseg  _event
+
+begcodeseg  _event              ; Start of code segment
+
+    cpublic _EVT_codeStart
+
+;----------------------------------------------------------------------------
+; int _EVT_getKeyCode(void)
+;----------------------------------------------------------------------------
+; Returns the key code for the next available key by extracting it from
+; the BIOS keyboard buffer.
+;----------------------------------------------------------------------------
+cprocstart  _EVT_getKeyCode
+
+        enter_c
+
+        mov     esi,[_EVT_biosPtr]
+        xor     ebx,ebx
+        xor     eax,eax
+        mov     bx,[KB_HEAD]
+        cmp     bx,[KB_TAIL]
+        jz      @@Done
+        xor     eax,eax
+        mov     ax,[esi+ebx]    ; EAX := character from keyboard buffer
+        inc     _bx
+        inc     _bx
+        cmp     bx,[KB_END]     ; Hit the end of the keyboard buffer?
+        jl      @@1
+        mov     bx,[KB_START]
+@@1:    mov     [KB_HEAD],bx    ; Update keyboard buffer head pointer
+
+@@Done: leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _EVT_pumpMessages(void)
+;----------------------------------------------------------------------------
+; This function would normally do nothing, however due to strange bugs
+; in the Windows 3.1 and OS/2 DOS boxes, we don't get any hardware keyboard
+; interrupts unless we periodically call the BIOS keyboard functions. Hence
+; this function gets called every time that we check for events, and works
+; around this problem (in essence it tells the DOS VDM to pump the
+; keyboard events to our program ;-).
+;
+; Note that this bug is not present under Win 9x DOS boxes.
+;----------------------------------------------------------------------------
+cprocstart  _EVT_pumpMessages
+
+        mov     ah,11h          ; Function - Check keyboard status
+        int     16h             ; Call BIOS
+        
+        mov     ax, 0Bh         ; Reset Move Mouse
+        int     33h
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int _EVT_disableInt(void);
+;----------------------------------------------------------------------------
+; Return processor interrupt status and disable interrupts.
+;----------------------------------------------------------------------------
+cprocstart  _EVT_disableInt
+
+        pushf                   ; Put flag word on stack
+        cli                     ; Disable interrupts!
+        pop     eax             ; deposit flag word in return register
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _EVT_restoreInt(int ps);
+;----------------------------------------------------------------------------
+; Restore processor interrupt status.
+;----------------------------------------------------------------------------
+cprocstart  _EVT_restoreInt
+
+        ARG     ps:UINT
+
+        push    ebp
+        mov     ebp,esp         ; Set up stack frame
+        push    [DWORD ps]
+        popf                    ; Restore processor status (and interrupts)
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int EVT_rdinx(int port,int index)
+;----------------------------------------------------------------------------
+; Reads an indexed register value from an I/O port.
+;----------------------------------------------------------------------------
+cprocstart  EVT_rdinx
+
+        ARG     port:UINT, index:UINT
+
+        push    ebp
+        mov     ebp,esp
+        mov     edx,[port]
+        mov     al,[BYTE index]
+        out     dx,al
+        inc     dx
+        in      al,dx
+        movzx   eax,al
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void EVT_wrinx(int port,int index,int value)
+;----------------------------------------------------------------------------
+; Writes an indexed register value to an I/O port.
+;----------------------------------------------------------------------------
+cprocstart  EVT_wrinx
+
+        ARG     port:UINT, index:UINT, value:UINT
+
+        push    ebp
+        mov     ebp,esp
+        mov     edx,[port]
+        mov     al,[BYTE index]
+        mov     ah,[BYTE value]
+        out     dx,ax
+        pop     ebp
+        ret
+
+cprocend
+
+    cpublic _EVT_codeEnd
+
+endcodeseg  _event
+
+endif
+
+        END                         ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm
new file mode 100755
index 0000000..a4a9c79
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm
@@ -0,0 +1,438 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    NASM or TASM Assembler
+;* Environment: IBM PC (MS DOS)
+;*
+;* Description: Uses the 8253 timer and the BIOS time-of-day count to time
+;*              the performance of code that takes less than an hour to
+;*              execute.
+;*
+;*              The routines in this package only works with interrupts
+;*              enabled, and in fact will explicitly turn interrupts on
+;*              in order to ensure we get accurate results from the timer.
+;*
+;*  Externally 'C' callable routines:
+;*
+;*  LZ_timerOn:     Saves the BIOS time of day count and starts the
+;*                  long period Zen Timer.
+;*
+;*  LZ_timerLap:    Latches the current count, and keeps the timer running
+;*
+;*  LZ_timerOff:    Stops the long-period Zen Timer and saves the timer
+;*                  count and the BIOS time of day count.
+;*
+;*  LZ_timerCount:  Returns an unsigned long representing the timed count
+;*                  in microseconds. If more than an hour passed during
+;*                  the timing interval, LZ_timerCount will return the
+;*                  value 0xFFFFFFFF (an invalid count).
+;*
+;*  Note:   If either more than an hour passes between calls to LZ_timerOn
+;*          and LZ_timerOff, an error is reported. For timing code that takes
+;*          more than a few minutes to execute, use the low resolution
+;*          Ultra Long Period Zen Timer code, which should be accurate
+;*          enough for most purposes.
+;*
+;*  Note:   Each block of code being timed should ideally be run several
+;*          times, with at least two similar readings required to
+;*          establish a true measurement, in order to eliminate any
+;*          variability caused by interrupts.
+;*
+;*  Note:   Interrupts must not be disabled for more than 54 ms at a
+;*          stretch during the timing interval. Because interrupts are
+;*          enabled, key, mice, and other devices that generate interrupts
+;*          should not be used during the timing interval.
+;*
+;*  Note:   Any extra code running off the timer interrupt (such as
+;*          some memory resident utilities) will increase the time
+;*          measured by the Zen Timer.
+;*
+;*  Note:   These routines can introduce inaccuracies of up to a few
+;*          tenths of a second into the system clock count for each
+;*          code section being timed. Consequently, it's a good idea to
+;*          reboot at the conclusion of timing sessions. (The
+;*          battery-backed clock, if any, is not affected by the Zen
+;*          timer.)
+;*
+;*  All registers and all flags are preserved by all routines, except
+;*  interrupts which are always turned on
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"
+
+;****************************************************************************
+;
+; Equates used by long period Zen Timer
+;
+;****************************************************************************
+
+; Base address of 8253 timer chip
+
+BASE_8253       equ     40h
+
+; The address of the timer 0 count registers in the 8253
+
+TIMER_0_8253    equ     BASE_8253 + 0
+
+; The address of the mode register in the 8253
+
+MODE_8253       equ     BASE_8253 + 3
+
+; The address of the BIOS timer count variable in the BIOS data area.
+
+TIMER_COUNT     equ     6Ch
+
+; Macro to delay briefly to ensure that enough time has elapsed between
+; successive I/O accesses so that the device being accessed can respond
+; to both accesses even on a very fast PC.
+
+ifdef   USE_NASM
+%macro  DELAY 0
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+%endmacro
+else
+macro   DELAY
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+endm
+endif
+
+header      _lztimer
+
+begdataseg  _lztimer
+
+        cextern  _ZTimerBIOSPtr,DPTR
+
+StartBIOSCount      dd  0       ; Starting BIOS count dword
+EndBIOSCount        dd  0       ; Ending BIOS count dword
+EndTimedCount       dw  0       ; Timer 0 count at the end of timing period
+
+enddataseg  _lztimer
+
+begcodeseg  _lztimer                ; Start of code segment
+
+;----------------------------------------------------------------------------
+; void LZ_timerOn(void);
+;----------------------------------------------------------------------------
+; Starts the Long period Zen timer counting.
+;----------------------------------------------------------------------------
+cprocstart  LZ_timerOn
+
+; Set the timer 0 of the 8253 to mode 2 (divide-by-N), to cause
+; linear counting rather than count-by-two counting. Also stops
+; timer 0 until the timer count is loaded, except on PS/2 computers.
+
+        mov     al,00110100b        ; mode 2
+        out     MODE_8253,al
+
+; Set the timer count to 0, so we know we won't get another timer
+; interrupt right away. Note: this introduces an inaccuracy of up to 54 ms
+; in the system clock count each time it is executed.
+
+        DELAY
+        sub     al,al
+        out     TIMER_0_8253,al     ; lsb
+        DELAY
+        out     TIMER_0_8253,al     ; msb
+
+; Store the timing start BIOS count
+
+        use_es
+ifdef   flatmodel
+        mov     ebx,[_ZTimerBIOSPtr]
+else
+        les     bx,[_ZTimerBIOSPtr]
+endif
+        cli                         ; No interrupts while we grab the count
+        mov     eax,[_ES _bx+TIMER_COUNT]
+        sti
+        mov     [StartBIOSCount],eax
+        unuse_es
+
+; Set the timer count to 0 again to start the timing interval.
+
+        mov     al,00110100b        ; set up to load initial
+        out     MODE_8253,al        ; timer count
+        DELAY
+        sub     al,al
+        out     TIMER_0_8253,al     ; load count lsb
+        DELAY
+        out     TIMER_0_8253,al     ; load count msb
+
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void LZ_timerOff(void);
+;----------------------------------------------------------------------------
+; Stops the long period Zen timer and saves count.
+;----------------------------------------------------------------------------
+cprocstart  LZ_timerOff
+
+; Latch the timer count.
+
+        mov     al,00000000b        ; latch timer 0
+        out     MODE_8253,al
+        cli                         ; Stop the BIOS count
+
+; Read the BIOS count. (Since interrupts are disabled, the BIOS
+; count won't change).
+
+        use_es
+ifdef   flatmodel
+        mov     ebx,[_ZTimerBIOSPtr]
+else
+        les     bx,[_ZTimerBIOSPtr]
+endif
+        mov     eax,[_ES _bx+TIMER_COUNT]
+        mov     [EndBIOSCount],eax
+        unuse_es
+
+; Read out the count we latched earlier.
+
+        in      al,TIMER_0_8253     ; least significant byte
+        DELAY
+        mov     ah,al
+        in      al,TIMER_0_8253     ; most significant byte
+        xchg    ah,al
+        neg     ax                  ; Convert from countdown remaining
+                                    ;  to elapsed count
+        mov     [EndTimedCount],ax
+        sti                         ; Let the BIOS count continue
+
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; unsigned long LZ_timerLap(void)
+;----------------------------------------------------------------------------
+; Latches the current count and converts it to a microsecond timing value,
+; but leaves the timer still running. We dont check for and overflow,
+; where the time has gone over an hour in this routine, since we want it
+; to execute as fast as possible.
+;----------------------------------------------------------------------------
+cprocstart  LZ_timerLap
+
+        push    ebx                 ; Save EBX for 32 bit code
+
+; Latch the timer count.
+
+        mov     al,00000000b        ; latch timer 0
+        out     MODE_8253,al
+        cli                         ; Stop the BIOS count
+
+; Read the BIOS count. (Since interrupts are disabled, the BIOS
+; count wont change).
+
+        use_es
+ifdef   flatmodel
+        mov     ebx,[_ZTimerBIOSPtr]
+else
+        les     bx,[_ZTimerBIOSPtr]
+endif
+        mov     eax,[_ES _bx+TIMER_COUNT]
+        mov     [EndBIOSCount],eax
+        unuse_es
+
+; Read out the count we latched earlier.
+
+        in      al,TIMER_0_8253     ; least significant byte
+        DELAY
+        mov     ah,al
+        in      al,TIMER_0_8253     ; most significant byte
+        xchg    ah,al
+        neg     ax                  ; Convert from countdown remaining
+                                    ;  to elapsed count
+        mov     [EndTimedCount],ax
+        sti                         ; Let the BIOS count continue
+
+; See if a midnight boundary has passed and adjust the finishing BIOS
+; count by the number of ticks in 24 hours. We wont be able to detect
+; more than 24 hours, but at least we can time across a midnight
+; boundary
+
+        mov     eax,[EndBIOSCount]      ; Is end < start?
+        cmp     eax,[StartBIOSCount]
+        jae     @@CalcBIOSTime          ; No, calculate the time taken
+
+; Adjust the finishing time by adding the number of ticks in 24 hours
+; (1573040).
+
+        add     [DWORD EndBIOSCount],1800B0h
+
+; Convert the BIOS time to microseconds
+
+@@CalcBIOSTime:
+        mov     ax,[WORD EndBIOSCount]
+        sub     ax,[WORD StartBIOSCount]
+        mov     dx,54925            ; Number of microseconds each
+                                    ;  BIOS count represents.
+        mul     dx
+        mov     bx,ax               ; set aside BIOS count in
+        mov     cx,dx               ;  microseconds
+
+; Convert timer count to microseconds
+
+        push    _si
+        mov     ax,[EndTimedCount]
+        mov     si,8381
+        mul     si
+        mov     si,10000
+        div     si                  ; * 0.8381 = * 8381 / 10000
+        pop     _si
+
+; Add the timer and BIOS counts together to get an overall time in
+; microseconds.
+
+        add     ax,bx
+        adc     cx,0
+ifdef flatmodel
+        shl     ecx,16
+        mov     cx,ax
+        mov     eax,ecx             ; EAX := timer count
+else
+        mov     dx,cx
+endif
+        pop     ebx                 ; Restore EBX for 32 bit code
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; unsigned long LZ_timerCount(void);
+;----------------------------------------------------------------------------
+; Returns an unsigned long representing the net time in microseconds.
+;
+; If an hour has passed while timing, we return 0xFFFFFFFF as the count
+; (which is not a possible count in itself).
+;----------------------------------------------------------------------------
+cprocstart  LZ_timerCount
+
+        push    ebx                 ; Save EBX for 32 bit code
+
+; See if a midnight boundary has passed and adjust the finishing BIOS
+; count by the number of ticks in 24 hours. We wont be able to detect
+; more than 24 hours, but at least we can time across a midnight
+; boundary
+
+        mov     eax,[EndBIOSCount]      ; Is end < start?
+        cmp     eax,[StartBIOSCount]
+        jae     @@CheckForHour          ; No, check for hour passing
+
+; Adjust the finishing time by adding the number of ticks in 24 hours
+; (1573040).
+
+        add     [DWORD EndBIOSCount],1800B0h
+
+; See if more than an hour passed during timing. If so, notify the user.
+
+@@CheckForHour:
+        mov     ax,[WORD StartBIOSCount+2]
+        cmp     ax,[WORD EndBIOSCount+2]
+        jz      @@CalcBIOSTime      ; Hour count didn't change, so
+                                    ;  everything is fine
+
+        inc     ax
+        cmp     ax,[WORD EndBIOSCount+2]
+        jnz     @@TestTooLong       ; Two hour boundaries passed, so the
+                                    ;  results are no good
+        mov     ax,[WORD EndBIOSCount]
+        cmp     ax,[WORD StartBIOSCount]
+        jb      @@CalcBIOSTime      ; a single hour boundary passed. That's
+                                    ; OK, so long as the total time wasn't
+                                    ; more than an hour.
+
+; Over an hour elapsed passed during timing, which renders
+; the results invalid. Notify the user. This misses the case where a
+; multiple of 24 hours has passed, but we'll rely on the perspicacity of
+; the user to detect that case :-).
+
+@@TestTooLong:
+ifdef   flatmodel
+        mov     eax,0FFFFFFFFh
+else
+        mov     ax,0FFFFh
+        mov     dx,0FFFFh
+endif
+        jmp     short @@Done
+
+; Convert the BIOS time to microseconds
+
+@@CalcBIOSTime:
+        mov     ax,[WORD EndBIOSCount]
+        sub     ax,[WORD StartBIOSCount]
+        mov     dx,54925            ; Number of microseconds each
+                                    ;  BIOS count represents.
+        mul     dx
+        mov     bx,ax               ; set aside BIOS count in
+        mov     cx,dx               ;  microseconds
+
+; Convert timer count to microseconds
+
+        push    _si
+        mov     ax,[EndTimedCount]
+        mov     si,8381
+        mul     si
+        mov     si,10000
+        div     si                  ; * 0.8381 = * 8381 / 10000
+        pop     _si
+
+; Add the timer and BIOS counts together to get an overall time in
+; microseconds.
+
+        add     ax,bx
+        adc     cx,0
+ifdef flatmodel
+        shl     ecx,16
+        mov     cx,ax
+        mov     eax,ecx             ; EAX := timer count
+else
+        mov     dx,cx
+endif
+
+@@Done: pop     ebx                 ; Restore EBX for 32 bit code
+        ret
+
+cprocend
+
+cprocstart   LZ_disable
+        cli
+        ret
+cprocend
+
+cprocstart   LZ_enable
+        sti
+        ret
+cprocend
+
+endcodeseg  _lztimer
+
+        END
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm
new file mode 100755
index 0000000..42b5cf3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm
@@ -0,0 +1,656 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: IBM PC Real mode and 16/32 bit protected mode
+;*
+;* Description: Low level assembly support for the PM library specific to
+;*              MSDOS.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"               ; Memory model macros
+
+header      _pmdos                  ; Set up memory model
+
+begdataseg  _pmdos
+
+ifndef  flatmodel
+
+struc   rmregs_s
+ax          dw  ?
+ax_high     dw  ?
+bx          dw  ?
+bx_high     dw  ?
+cx          dw  ?
+cx_high     dw  ?
+dx          dw  ?
+dx_high     dw  ?
+si          dw  ?
+si_high     dw  ?
+di          dw  ?
+di_high     dw  ?
+cflag       dw  ?
+cflag_high  dw  ?
+ends    rmregs_s
+RMREGS  = (rmregs_s PTR es:bx)
+
+struc   rmsregs_s
+es      dw  ?
+cs      dw  ?
+ss      dw  ?
+ds      dw  ?
+ends    rmsregs_s
+RMSREGS = (rmsregs_s PTR es:bx)
+
+endif   ; !flatmodel
+
+ifdef flatmodel
+    cextern _PM_savedDS,USHORT
+    cextern _PM_VXD_off,UINT
+    cextern _PM_VXD_sel,UINT
+ifdef   DOS4GW
+    cextern _PM_haveCauseWay,UINT
+endif
+endif
+intel_id        db  "GenuineIntel"  ; Intel vendor ID
+
+PMHELP_GETPDB       EQU 0026h
+PMHELP_FLUSHTLB     EQU 0027h
+
+enddataseg  _pmdos
+
+P586
+
+begcodeseg  _pmdos                  ; Start of code segment
+
+ifndef  flatmodel
+
+;----------------------------------------------------------------------------
+; void PM_callRealMode(unsigned s,unsigned o, RMREGS *regs,
+;   RMSREGS *sregs)
+;----------------------------------------------------------------------------
+; Calls a real mode procedure, loading the appropriate registers values
+; from the passed in structures. Only the DS and ES register are loaded
+; from the SREGS structure.
+;----------------------------------------------------------------------------
+cprocstart  PM_callRealMode
+
+        ARG     s:WORD, o:WORD, regs:DWORD, sregs:DWORD
+
+        LOCAL   addr:DWORD, bxVal:WORD, esVal:WORD, flags:WORD = LocalSize
+
+        enter_c
+        push    ds
+        push    es
+
+        mov     ax,[o]              ; Build the address to call in 'addr'
+        mov     [WORD addr],ax
+        mov     ax,[s]
+        mov     [WORD addr+2],ax
+
+        les     bx,[sregs]
+        mov     ax,[RMSREGS.ds]
+        mov     ds,ax               ; DS := passed in value
+        mov     ax,[RMSREGS.es]
+        mov     [esVal],ax
+        les     bx,[regs]
+        mov     ax,[RMREGS.bx]
+        mov     [bxVal],ax
+        mov     ax,[RMREGS.ax]      ; AX := passed in value
+        mov     cx,[RMREGS.cx]      ; CX := passed in value
+        mov     dx,[RMREGS.dx]      ; DX := passed in value
+        mov     si,[RMREGS.si]      ; SI := passed in value
+        mov     di,[RMREGS.di]      ; DI := passed in value
+        push    bp
+        push    [esVal]
+        pop     es                  ; ES := passed in value
+        mov     bx,[bxVal]          ; BX := passed in value
+
+        call    [addr]              ; Call the specified routine
+
+        pushf                       ; Save flags for later
+        pop     [flags]
+
+        pop     bp
+        push    es
+        pop     [esVal]
+        push    bx
+        pop     [bxVal]
+        les     bx,[sregs]
+        push    ds
+        pop     [RMSREGS.ds]        ; Save value of DS
+        push    [esVal]
+        pop     [RMSREGS.es]        ; Save value of ES
+        les     bx,[regs]
+        mov     [RMREGS.ax],ax      ; Save value of AX
+        mov     [RMREGS.cx],cx      ; Save value of CX
+        mov     [RMREGS.dx],dx      ; Save value of DX
+        mov     [RMREGS.si],si      ; Save value of SI
+        mov     [RMREGS.di],di      ; Save value of DI
+        mov     ax,[flags]          ; Return flags
+        and     ax,1h               ; Isolate carry flag
+        mov     [RMREGS.cflag],ax   ; Save carry flag status
+        mov     ax,[bxVal]
+        mov     [RMREGS.bx],ax      ; Save value of BX
+
+        pop     es
+        pop     ds
+        leave_c
+        ret
+
+cprocend
+
+endif
+
+;----------------------------------------------------------------------------
+; void PM_segread(PMSREGS *sregs)
+;----------------------------------------------------------------------------
+; Read the current value of all segment registers
+;----------------------------------------------------------------------------
+cprocstartdll16 PM_segread
+
+        ARG     sregs:DPTR
+
+        enter_c
+
+        mov     ax,es
+        _les    _si,[sregs]
+        mov     [_ES _si],ax
+        mov     [_ES _si+2],cs
+        mov     [_ES _si+4],ss
+        mov     [_ES _si+6],ds
+        mov     [_ES _si+8],fs
+        mov     [_ES _si+10],gs
+
+        leave_c
+        ret
+
+cprocend
+
+; Create a table of the 256 different interrupt calls that we can jump
+; into
+
+ifdef   USE_NASM
+
+%assign intno 0
+
+intTable:
+%rep    256
+        db      0CDh
+        db      intno
+%assign intno   intno + 1
+        ret
+        nop
+%endrep
+
+else
+
+intno = 0
+
+intTable:
+        REPT    256
+        db      0CDh
+        db      intno
+intno = intno + 1
+        ret
+        nop
+        ENDM
+
+endif
+
+;----------------------------------------------------------------------------
+; _PM_genInt    - Generate the appropriate interrupt
+;----------------------------------------------------------------------------
+cprocnear   _PM_genInt
+
+        push    _ax                     ; Save _ax
+        push    _bx                     ; Save _bx
+ifdef flatmodel
+        mov     ebx,[UINT esp+12]       ; EBX := interrupt number
+else
+        mov     bx,sp                   ; Make sure ESP is zeroed
+        mov     bx,[UINT ss:bx+6]       ; BX := interrupt number
+endif
+        mov     _ax,offset intTable     ; Point to interrupt generation table
+        shl     _bx,2                   ; _BX := index into table
+        add     _ax,_bx                 ; _AX := pointer to interrupt code
+ifdef flatmodel
+        xchg    eax,[esp+4]             ; Restore eax, and set for int
+else
+        mov     bx,sp
+        xchg    ax,[ss:bx+2]            ; Restore ax, and set for int
+endif
+        pop     _bx                     ; restore _bx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs)
+;----------------------------------------------------------------------------
+; Issues a software interrupt in protected mode. This routine has been
+; written to allow user programs to load CS and DS with different values
+; other than the default.
+;----------------------------------------------------------------------------
+cprocstartdll16 PM_int386x
+
+        ARG     intno:UINT, inptr:DPTR, outptr:DPTR, sregs:DPTR
+
+        LOCAL   flags:UINT, sv_ds:UINT, sv_esi:ULONG = LocalSize
+
+        enter_c
+        push    ds
+        push    es                  ; Save segment registers
+        push    fs
+        push    gs
+
+        _lds    _si,[sregs]         ; DS:_SI -> Load segment registers
+        mov     es,[_si]
+        mov     bx,[_si+6]
+        mov     [sv_ds],_bx         ; Save value of user DS on stack
+        mov     fs,[_si+8]
+        mov     gs,[_si+10]
+
+        _lds    _si,[inptr]         ; Load CPU registers
+        mov     eax,[_si]
+        mov     ebx,[_si+4]
+        mov     ecx,[_si+8]
+        mov     edx,[_si+12]
+        mov     edi,[_si+20]
+        mov     esi,[_si+16]
+
+        push    ds                  ; Save value of DS
+        push    _bp                 ; Some interrupts trash this!
+        clc                         ; Generate the interrupt
+        push    [UINT intno]
+        mov     ds,[WORD sv_ds]     ; Set value of user's DS selector
+        call    _PM_genInt
+        pop     _bp                 ; Pop intno from stack (flags unchanged)
+        pop     _bp                 ; Restore value of stack frame pointer
+        pop     ds                  ; Restore value of DS
+
+        pushf                       ; Save flags for later
+        pop     [UINT flags]
+        push    esi                 ; Save ESI for later
+        pop     [DWORD sv_esi]
+        push    ds                  ; Save DS for later
+        pop     [UINT sv_ds]
+
+        _lds    _si,[outptr]        ; Save CPU registers
+        mov     [_si],eax
+        mov     [_si+4],ebx
+        mov     [_si+8],ecx
+        mov     [_si+12],edx
+        push    [DWORD sv_esi]
+        pop     [DWORD _si+16]
+        mov     [_si+20],edi
+
+        mov     _bx,[flags]         ; Return flags
+        and     ebx,1h              ; Isolate carry flag
+        mov     [_si+24],ebx        ; Save carry flag status
+
+        _lds    _si,[sregs]         ; Save segment registers
+        mov     [_si],es
+        mov     _bx,[sv_ds]
+        mov     [_si+6],bx          ; Get returned DS from stack
+        mov     [_si+8],fs
+        mov     [_si+10],gs
+
+        pop     gs                  ; Restore segment registers
+        pop     fs
+        pop     es
+        pop     ds
+        leave_c
+        ret
+
+cprocend
+
+ifndef flatmodel
+_PM_savedDS     dw  _DATA           ; Saved value of DS
+endif
+
+;----------------------------------------------------------------------------
+; void PM_saveDS(void)
+;----------------------------------------------------------------------------
+; Save the value of DS into a section of the code segment, so that we can
+; quickly load this value at a later date in the PM_loadDS() routine from
+; inside interrupt handlers etc. The method to do this is different
+; depending on the DOS extender being used.
+;----------------------------------------------------------------------------
+cprocstartdll16 PM_saveDS
+
+ifdef flatmodel
+        mov     [_PM_savedDS],ds    ; Store away in data segment
+endif
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_loadDS(void)
+;----------------------------------------------------------------------------
+; Routine to load the DS register with the default value for the current
+; DOS extender. Only the DS register is loaded, not the ES register, so
+; if you wish to call C code, you will need to also load the ES register
+; in 32 bit protected mode.
+;----------------------------------------------------------------------------
+cprocstartdll16 PM_loadDS
+
+        mov     ds,[cs:_PM_savedDS] ; We can access the proper DS through CS
+        ret
+
+cprocend
+
+ifdef flatmodel
+
+;----------------------------------------------------------------------------
+; ibool DPMI_allocateCallback(void (*pmcode)(), void *rmregs, long *RMCB)
+;----------------------------------------------------------------------------
+cprocstart  _DPMI_allocateCallback
+
+        ARG     pmcode:CPTR, rmregs:DPTR, RMCB:DPTR
+
+        enter_c
+        push    ds
+        push    es
+
+        push    cs
+        pop     ds
+        mov     esi,[pmcode]    ; DS:ESI -> protected mode code to call
+        mov     edi,[rmregs]    ; ES:EDI -> real mode register buffer
+        mov     ax,303h         ; AX := allocate realmode callback function
+        int     31h
+        mov     eax,0           ; Return failure!
+        jc      @@Fail
+
+        mov     eax,[RMCB]
+        shl     ecx,16
+        mov     cx,dx
+        mov     [es:eax],ecx    ; Return real mode address
+        mov     eax,1           ; Return success!
+
+@@Fail: pop     es
+        pop     ds
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void DPMI_freeCallback(long RMCB)
+;----------------------------------------------------------------------------
+cprocstart  _DPMI_freeCallback
+
+        ARG     RMCB:ULONG
+
+        enter_c
+
+        mov     cx,[WORD RMCB+2]
+        mov     dx,[WORD RMCB]  ; CX:DX := real mode callback
+        mov     ax,304h
+        int     31h
+
+        leave_c
+        ret
+
+cprocend
+
+endif
+
+; Macro to delay briefly to ensure that enough time has elapsed between
+; successive I/O accesses so that the device being accessed can respond
+; to both accesses even on a very fast PC.
+
+ifdef   USE_NASM
+%macro  DELAY 0
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+%endmacro
+%macro  IODELAYN 1
+%rep    %1
+        DELAY
+%endrep
+%endmacro
+else
+macro   DELAY
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+endm
+macro   IODELAYN    N
+    rept    N
+        DELAY
+    endm
+endm
+endif
+
+;----------------------------------------------------------------------------
+; uchar _PM_readCMOS(int index)
+;----------------------------------------------------------------------------
+; Read the value of a specific CMOS register. We do this with both
+; normal interrupts and NMI disabled.
+;----------------------------------------------------------------------------
+cprocstart  _PM_readCMOS
+
+        ARG     index:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        pushfd
+        mov     al,[BYTE index]
+        or      al,80h              ; Add disable NMI flag
+        cli
+        out     70h,al
+        IODELAYN 5
+        in      al,71h
+        mov     ah,al
+        xor     al,al
+        IODELAYN 5
+        out     70h,al              ; Re-enable NMI
+        sti
+        mov     al,ah               ; Return value in AL
+        popfd
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _PM_writeCMOS(int index,uchar value)
+;----------------------------------------------------------------------------
+; Read the value of a specific CMOS register. We do this with both
+; normal interrupts and NMI disabled.
+;----------------------------------------------------------------------------
+cprocstart  _PM_writeCMOS
+
+        ARG     index:UINT, value:UCHAR
+
+        push    _bp
+        mov     _bp,_sp
+        pushfd
+        mov     al,[BYTE index]
+        or      al,80h              ; Add disable NMI flag
+        cli
+        out     70h,al
+        IODELAYN 5
+        mov     al,[value]
+        out     71h,al
+        xor     al,al
+        IODELAYN 5
+        out     70h,al              ; Re-enable NMI
+        sti
+        popfd
+        pop     _bp
+        ret
+
+cprocend
+
+ifdef   flatmodel
+
+;----------------------------------------------------------------------------
+; int _PM_pagingEnabled(void)
+;----------------------------------------------------------------------------
+; Returns 1 if paging is enabled, 0 if not or -1 if not at ring 0
+;----------------------------------------------------------------------------
+cprocstart  _PM_pagingEnabled
+
+        mov     eax,-1
+ifdef   DOS4GW
+        mov     cx,cs
+        and     ecx,3
+        jz      @@Ring0
+        cmp     [UINT _PM_haveCauseWay],0
+        jnz     @@Ring0
+        jmp     @@Exit
+
+@@Ring0:
+        mov     eax,cr0                 ; Load CR0
+        shr     eax,31                  ; Isolate paging enabled bit
+endif
+@@Exit: ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; _PM_getPDB - Return the Page Table Directory Base address
+;----------------------------------------------------------------------------
+cprocstart  _PM_getPDB
+
+ifdef   DOS4GW
+        mov     ax,cs
+        and     eax,3
+        jz      @@Ring0
+        cmp     [UINT _PM_haveCauseWay],0
+        jnz     @@Ring0
+endif
+
+; Call VxD if running at ring 3 in a DOS box
+
+        cmp     [WORD _PM_VXD_sel],0
+        jz      @@Fail
+        mov     eax,PMHELP_GETPDB
+ifdef   USE_NASM
+        call    far dword [_PM_VXD_off]
+else
+        call    [FCPTR _PM_VXD_off]
+endif
+        ret
+
+@@Ring0:
+ifdef   DOS4GW
+        mov     eax,cr3
+        and     eax,0FFFFF000h
+        ret
+endif
+@@Fail: xor     eax,eax
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_flushTLB - Flush the Translation Lookaside buffer
+;----------------------------------------------------------------------------
+cprocstart  PM_flushTLB
+
+        mov     ax,cs
+        and     eax,3
+        jz      @@Ring0
+ifdef   DOS4GW
+        cmp     [UINT _PM_haveCauseWay],0
+        jnz     @@Ring0
+endif
+
+; Call VxD if running at ring 3 in a DOS box
+
+        cmp     [WORD _PM_VXD_sel],0
+        jz      @@Fail
+        mov     eax,PMHELP_FLUSHTLB
+ifdef   USE_NASM
+        call    far dword [_PM_VXD_off]
+else
+        call    [FCPTR _PM_VXD_off]
+endif
+        ret
+
+@@Ring0:
+ifdef   DOS4GW
+        wbinvd                  ; Flush the CPU cache
+        mov     eax,cr3
+        mov     cr3,eax         ; Flush the TLB
+endif
+@@Fail: ret
+
+cprocend
+
+endif
+
+;----------------------------------------------------------------------------
+; void _PM_VxDCall(VXD_regs far *r,uint off,uint sel);
+;----------------------------------------------------------------------------
+cprocstart  _PM_VxDCall
+
+        ARG     r:DPTR, off:UINT, sel:UINT
+
+        enter_c
+
+; Load all registers from the registers structure
+
+        mov     ebx,[r]
+        mov     eax,[ebx+0]
+        mov     ecx,[ebx+8]
+        mov     edx,[ebx+12]
+        mov     esi,[ebx+16]
+        mov     edi,[ebx+20]
+        mov     ebx,[ebx+4]         ; Trashes BX structure pointer!
+
+; Call the VxD entry point (on stack)
+
+ifdef   USE_NASM
+        call far dword [off]
+else
+        call    [FCPTR off]
+endif
+
+; Save all registers back in the structure
+
+        push    ebx                 ; Push EBX onto stack for later
+        mov     ebx,[r]
+        mov     [ebx+0],eax
+        mov     [ebx+8],ecx
+        mov     [ebx+12],edx
+        mov     [ebx+16],esi
+        mov     [ebx+20],edi
+        pop     [DWORD ebx+4]       ; Save value of EBX from stack
+
+        leave_c
+        ret
+
+cprocend
+
+endcodeseg  _pmdos
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm
new file mode 100755
index 0000000..5c741f3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm
@@ -0,0 +1,1105 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: IBM PC Real mode and 16/32 bit protected mode
+;*
+;* Description: Low level assembly support for the PM library specific to
+;*              MSDOS interrupt handling.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+header      _pmdos              ; Set up memory model
+
+; Define the size of our local stacks. For real mode code they cant be
+; that big, but for 32 bit protected mode code we can make them nice and
+; large so that complex C functions can be used.
+
+ifdef flatmodel
+MOUSE_STACK EQU 4096
+TIMER_STACK EQU 4096
+KEY_STACK   EQU 1024
+INT10_STACK EQU 1024
+IRQ_STACK   EQU 1024
+else
+MOUSE_STACK EQU 1024
+TIMER_STACK EQU 512
+KEY_STACK   EQU 256
+INT10_STACK EQU 256
+IRQ_STACK   EQU 256
+endif
+
+ifdef   USE_NASM
+
+; Macro to load DS and ES registers with correct value.
+
+%imacro   LOAD_DS 0
+%ifdef  flatmodel
+        mov     ds,[cs:_PM_savedDS]
+        mov     es,[cs:_PM_savedDS]
+%else
+        push    ax
+        mov     ax,_DATA
+        mov     ds,ax
+        pop     ax
+%endif
+%endmacro
+
+; Note that interrupts we disable interrupts during the following stack
+; %imacro for correct operation, but we do not enable them again. Normally
+; these %imacros are used within interrupt handlers so interrupts should
+; already be off. We turn them back on explicitly later if the user code
+; needs them to be back on.
+
+; Macro to switch to a new local stack.
+
+%imacro NEWSTK  1
+        cli
+        mov     [seg_%1],ss
+        mov     [ptr_%1],_sp
+        mov     [TempSeg],ds
+        mov     ss,[TempSeg]
+        mov     _sp,offset %1
+%endmacro
+
+; %imacro to switch back to the old stack.
+
+%imacro   RESTSTK   1
+        cli
+        mov     ss,[seg_%1]
+        mov     _sp,[ptr_%1]
+%endmacro
+
+; %imacro to swap the current stack with the one saved away.
+
+%imacro SWAPSTK 1
+        cli
+        mov     ax,ss
+        xchg    ax,[seg_%1]
+        mov     ss,ax
+        xchg    _sp,[ptr_%1]
+%endmacro
+
+else
+
+; Macro to load DS and ES registers with correct value.
+
+MACRO   LOAD_DS
+ifdef   flatmodel
+        mov     ds,[cs:_PM_savedDS]
+        mov     es,[cs:_PM_savedDS]
+else
+        push    ax
+        mov     ax,_DATA
+        mov     ds,ax
+        pop     ax
+endif
+ENDM
+
+; Note that interrupts we disable interrupts during the following stack
+; macro for correct operation, but we do not enable them again. Normally
+; these macros are used within interrupt handlers so interrupts should
+; already be off. We turn them back on explicitly later if the user code
+; needs them to be back on.
+
+; Macro to switch to a new local stack.
+
+MACRO   NEWSTK  stkname
+        cli
+        mov     [seg_&stkname&],ss
+        mov     [ptr_&stkname&],_sp
+        mov     [TempSeg],ds
+        mov     ss,[TempSeg]
+        mov     _sp,offset stkname
+ENDM
+
+; Macro to switch back to the old stack.
+
+MACRO   RESTSTK stkname
+        cli
+        mov     ss,[seg_&stkname&]
+        mov     _sp,[ptr_&stkname&]
+ENDM
+
+; Macro to swap the current stack with the one saved away.
+
+MACRO   SWAPSTK stkname
+        cli
+        mov     ax,ss
+        xchg    ax,[seg_&stkname&]
+        mov     ss,ax
+        xchg    _sp,[ptr_&stkname&]
+ENDM
+
+endif
+
+begdataseg  _pmdos
+
+ifdef flatmodel
+    cextern _PM_savedDS,USHORT
+endif
+    cextern _PM_critHandler,CPTR
+    cextern _PM_breakHandler,CPTR
+    cextern _PM_timerHandler,CPTR
+    cextern _PM_rtcHandler,CPTR
+    cextern _PM_keyHandler,CPTR
+    cextern _PM_key15Handler,CPTR
+    cextern _PM_mouseHandler,CPTR
+    cextern _PM_int10Handler,CPTR
+
+    cextern _PM_ctrlCPtr,DPTR
+    cextern _PM_ctrlBPtr,DPTR
+    cextern _PM_critPtr,DPTR
+
+    cextern _PM_prevTimer,FCPTR
+    cextern _PM_prevRTC,FCPTR
+    cextern _PM_prevKey,FCPTR
+    cextern _PM_prevKey15,FCPTR
+    cextern _PM_prevBreak,FCPTR
+    cextern _PM_prevCtrlC,FCPTR
+    cextern _PM_prevCritical,FCPTR
+    cextern _PM_prevRealTimer,ULONG
+    cextern _PM_prevRealRTC,ULONG
+    cextern _PM_prevRealKey,ULONG
+    cextern _PM_prevRealKey15,ULONG
+    cextern _PM_prevRealInt10,ULONG
+
+cpublic _PM_pmdosDataStart
+
+; Allocate space for all of the local stacks that we need. These stacks
+; are not very large, but should be large enough for most purposes
+; (generally you want to handle these interrupts quickly, simply storing
+; the information for later and then returning). If you need bigger
+; stacks then change the appropriate value in here.
+
+            ALIGN   4
+            dclb MOUSE_STACK    ; Space for local stack (small)
+MsStack:                        ; Stack starts at end!
+ptr_MsStack DUINT   0           ; Place to store old stack offset
+seg_MsStack dw      0           ; Place to store old stack segment
+
+            ALIGN   4
+            dclb INT10_STACK    ; Space for local stack (small)
+Int10Stack:                     ; Stack starts at end!
+ptr_Int10Stack  DUINT   0       ; Place to store old stack offset
+seg_Int10Stack  dw      0       ; Place to store old stack segment
+
+            ALIGN   4
+            dclb TIMER_STACK    ; Space for local stack (small)
+TmStack:                        ; Stack starts at end!
+ptr_TmStack DUINT   0           ; Place to store old stack offset
+seg_TmStack dw      0           ; Place to store old stack segment
+
+            ALIGN   4
+            dclb TIMER_STACK    ; Space for local stack (small)
+RtcStack:                       ; Stack starts at end!
+ptr_RtcStack DUINT  0           ; Place to store old stack offset
+seg_RtcStack dw     0           ; Place to store old stack segment
+RtcInside   dw      0           ; Are we still handling current interrupt
+
+            ALIGN   4
+            dclb KEY_STACK      ; Space for local stack (small)
+KyStack:                        ; Stack starts at end!
+ptr_KyStack DUINT   0           ; Place to store old stack offset
+seg_KyStack dw      0           ; Place to store old stack segment
+KyInside    dw      0           ; Are we still handling current interrupt
+
+            ALIGN   4
+            dclb KEY_STACK      ; Space for local stack (small)
+Ky15Stack:                      ; Stack starts at end!
+ptr_Ky15Stack   DUINT   0       ; Place to store old stack offset
+seg_Ky15Stack   dw      0       ; Place to store old stack segment
+
+TempSeg     dw      0           ; Place to store stack segment
+
+cpublic _PM_pmdosDataEnd
+
+enddataseg  _pmdos
+
+begcodeseg  _pmdos              ; Start of code segment
+
+cpublic _PM_pmdosCodeStart
+
+;----------------------------------------------------------------------------
+; PM_mouseISR - Mouse interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Interrupt subroutine called by the mouse driver upon interrupts, to
+; dispatch control to high level C based subroutines. Interrupts are on
+; when we call the user code.
+;
+; It is _extremely_ important to save the state of the extended registers
+; as these may well be trashed by the routines called from here and not
+; restored correctly by the mouse interface module.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. For mouse handlers this is not a
+;       problem, as the mouse driver arbitrates calls to the user mouse
+;       handler for us.
+;
+; Entry:    AX  - Condition mask giving reason for call
+;           BX  - Mouse button state
+;           CX  - Horizontal cursor coordinate
+;           DX  - Vertical cursor coordinate
+;           SI  - Horizontal mickey value
+;           DI  - Vertical mickey value
+;
+;----------------------------------------------------------------------------
+ifdef   DJGPP
+cprocstart  _PM_mouseISR
+else
+cprocfar    _PM_mouseISR
+endif
+
+        push    ds              ; Save value of DS
+        push    es
+        pushad                  ; Save _all_ extended registers
+        cld                     ; Clear direction flag
+
+        LOAD_DS                 ; Load DS register
+        NEWSTK  MsStack         ; Switch to local stack
+
+; Call the installed high level C code routine
+
+        clrhi   dx              ; Clear out high order values
+        clrhi   cx
+        clrhi   bx
+        clrhi   ax
+        sgnhi   si
+        sgnhi   di
+
+        push    _di
+        push    _si
+        push    _dx
+        push    _cx
+        push    _bx
+        push    _ax
+        sti                     ; Enable interrupts
+        call    [CPTR _PM_mouseHandler]
+        _add    sp,12,24
+
+        RESTSTK MsStack         ; Restore previous stack
+
+        popad                   ; Restore all extended registers
+        pop     es
+        pop     ds
+        ret                     ; We are done!!
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_timerISR - Timer interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the timer interrupt, to dispatch control
+; to high level C based subroutines. We save the state of all registers
+; in this routine, and switch to a local stack. Interrupts are *off*
+; when we call the user code.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. Make sure your C code executes as
+;       quickly as possible, since a timer overrun will simply hang the
+;       system.
+;----------------------------------------------------------------------------
+cprocfar    _PM_timerISR
+
+        push    ds              ; Save value of DS
+        push    es
+        pushad                  ; Save _all_ extended registers
+        cld                     ; Clear direction flag
+
+        LOAD_DS                 ; Load DS register
+
+        NEWSTK  TmStack         ; Switch to local stack
+        call    [CPTR _PM_timerHandler]
+        RESTSTK TmStack         ; Restore previous stack
+
+        popad                   ; Restore all extended registers
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_chainPrevTimer - Chain to previous timer interrupt and return
+;----------------------------------------------------------------------------
+; Chains to the previous timer interrupt routine and returns control
+; back to the high level interrupt handler.
+;----------------------------------------------------------------------------
+cprocstart  PM_chainPrevTimer
+
+ifdef   TNT
+        push    eax
+        push    ebx
+        push    ecx
+        pushfd                  ; Push flags on stack to simulate interrupt
+        mov     ax,250Eh        ; Call real mode procedure function
+        mov     ebx,[_PM_prevRealTimer]
+        mov     ecx,1           ; Copy real mode flags to real mode stack
+        int     21h             ; Call the real mode code
+        popfd
+        pop     ecx
+        pop     ebx
+        pop     eax
+        ret
+else
+        SWAPSTK TmStack         ; Swap back to previous stack
+        pushf                   ; Save state of interrupt flag
+        pushf                   ; Push flags on stack to simulate interrupt
+ifdef   USE_NASM
+        call far dword [_PM_prevTimer]
+else
+        call    [_PM_prevTimer]
+endif
+        popf                    ; Restore state of interrupt flag
+        SWAPSTK TmStack         ; Swap back to C stack again
+        ret
+endif
+
+cprocend
+
+; Macro to delay briefly to ensure that enough time has elapsed between
+; successive I/O accesses so that the device being accessed can respond
+; to both accesses even on a very fast PC.
+
+ifdef   USE_NASM
+%macro  DELAY 0
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+%endmacro
+%macro  IODELAYN 1
+%rep    %1
+        DELAY
+%endrep
+%endmacro
+else
+macro   DELAY
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+endm
+macro   IODELAYN    N
+    rept    N
+        DELAY
+    endm
+endm
+endif
+
+;----------------------------------------------------------------------------
+; PM_rtcISR - Real time clock interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the timer interrupt, to dispatch control
+; to high level C based subroutines. We save the state of all registers
+; in this routine, and switch to a local stack. Interrupts are *off*
+; when we call the user code.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. Make sure your C code executes as
+;       quickly as possible, since a timer overrun will simply hang the
+;       system.
+;----------------------------------------------------------------------------
+cprocfar    _PM_rtcISR
+
+        push    ds                  ; Save value of DS
+        push    es
+        pushad                      ; Save _all_ extended registers
+        cld                         ; Clear direction flag
+
+; Clear priority interrupt controller and re-enable interrupts so we
+; dont lock things up for long.
+
+        mov     al,20h
+        out     0A0h,al
+        out     020h,al
+
+; Clear real-time clock timeout
+
+        in      al,70h              ; Read CMOS index register
+        push    _ax                 ;  and save for later
+        IODELAYN 3
+        mov     al,0Ch
+        out     70h,al
+        IODELAYN 5
+        in      al,71h
+
+; Call the C interrupt handler function
+
+        LOAD_DS                     ; Load DS register
+        cmp     [BYTE RtcInside],1  ; Check for mutual exclusion
+        je      @@Exit
+        mov     [BYTE RtcInside],1
+        NEWSTK  RtcStack            ; Switch to local stack
+        sti                         ; Re-enable interrupts
+        call    [CPTR _PM_rtcHandler]
+        RESTSTK RtcStack            ; Restore previous stack
+        mov     [BYTE RtcInside],0
+
+@@Exit: pop     _ax
+        out     70h,al              ; Restore CMOS index register
+        popad                       ; Restore all extended registers
+        pop     es
+        pop     ds
+        iret                        ; Return from interrupt
+
+cprocend
+
+ifdef flatmodel
+;----------------------------------------------------------------------------
+; PM_irqISRTemplate - Hardware interrupt handler IRQ template
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for any interrupt, to dispatch control
+; to high level C based subroutines. We save the state of all registers
+; in this routine, and switch to a local stack. Interrupts are *off*
+; when we call the user code.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. Make sure your C code executes as
+;       quickly as possible.
+;----------------------------------------------------------------------------
+cprocfar    _PM_irqISRTemplate
+
+        push    ebx
+        mov     ebx,0           ; Relocation adjustment factor
+        jmp     __IRQEntry
+
+; Global variables stored in the IRQ thunk code segment
+
+_CHandler       dd      0       ; Pointer to C interrupt handler
+_PrevIRQ        dd      0       ; Previous IRQ handler
+                dd      0
+_IRQ            dd      0       ; IRQ we are hooked for
+ptr_IRQStack    DUINT   0       ; Place to store old stack offset
+seg_IRQStack    dw      0       ; Place to store old stack segment
+_Inside         db      0       ; Mutual exclusion flag
+        ALIGN   4
+        dclb IRQ_STACK          ; Space for local stack
+_IRQStack:                      ; Stack starts at end!
+
+; Check for and reject spurious IRQ 7 signals
+
+__IRQEntry:
+        cmp     [BYTE cs:ebx+_IRQ],7    ; Spurious IRQs occur only on IRQ 7
+        jmp     @@ValidIRQ
+        push    eax
+        mov     al,1011b            ; OCW3: read ISR
+        out     20h,al              ; (Intel Peripheral Components, 1991,
+        in      al,20h              ; p. 3-188)
+        shl     al,1                ; Set C = bit 7 (IRQ 7) of ISR register
+        pop     eax
+        jc      @@ValidIRQ
+        iret                        ; Return from interrupt
+
+; Save all registers for duration of IRQ handler
+
+@@ValidIRQ:
+        push    ds                  ; Save value of DS
+        push    es
+        pushad                      ; Save _all_ extended registers
+        cld                         ; Clear direction flag
+        LOAD_DS                     ; Load DS register
+
+; Send an EOI to the PIC
+
+        mov     al,20h              ; Send EOI to PIC
+        cmp     [BYTE ebx+_IRQ],8   ; Clear PIC1 first if IRQ >= 8
+        jb      @@1
+        out     0A0h,al
+@@1:    out     20h,al
+
+; Check for mutual exclusion
+
+        cmp     [BYTE ebx+_Inside],1
+        je      @@ChainOldHandler
+        mov     [BYTE ebx+_Inside],1
+
+; Call the C interrupt handler function
+
+        mov     [ebx+seg_IRQStack],ss   ; Switch to local stack
+        mov     [ebx+ptr_IRQStack],esp
+        mov     [TempSeg],ds
+        mov     ss,[TempSeg]
+        lea     esp,[ebx+_IRQStack]
+        sti                             ; Re-enable interrupts
+        push    ebx
+        call    [DWORD ebx+_CHandler]
+        pop     ebx
+        cli
+        mov     ss,[ebx+seg_IRQStack]   ; Restore previous stack
+        mov     esp,[ebx+ptr_IRQStack]
+        or      eax,eax
+        jz      @@ChainOldHandler   ; Chain if not handled for shared IRQ
+
+@@Exit: mov     [BYTE ebx+_Inside],0
+        popad                       ; Restore all extended registers
+        pop     es
+        pop     ds
+        pop     ebx
+        iret                        ; Return from interrupt
+
+@@ChainOldHandler:
+        cmp     [DWORD ebx+_PrevIRQ],0
+        jz      @@Exit
+        mov     [BYTE ebx+_Inside],0
+        mov     eax,[DWORD ebx+_PrevIRQ]
+        mov     ebx,[DWORD ebx+_PrevIRQ+4]
+        mov     [DWORD _PrevIRQ],eax
+        mov     [DWORD _PrevIRQ+4],ebx
+        popad                       ; Restore all extended registers
+        pop     es
+        pop     ds
+        pop     ebx
+        jmp     [cs:_PrevIRQ]       ; Chain to previous IRQ handler
+
+cprocend
+cpublic _PM_irqISRTemplateEnd
+endif
+
+;----------------------------------------------------------------------------
+; PM_keyISR - keyboard interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the keyboard interrupt, to dispatch control
+; to high level C based subroutines. We save the state of all registers
+; in this routine, and switch to a local stack. Interrupts are *off*
+; when we call the user code.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. However we ensure within this routine
+;       mutual exclusion to the keyboard handling routine.
+;----------------------------------------------------------------------------
+cprocfar    _PM_keyISR
+
+        push    ds              ; Save value of DS
+        push    es
+        pushad                  ; Save _all_ extended registers
+        cld                     ; Clear direction flag
+
+        LOAD_DS                 ; Load DS register
+
+        cmp     [BYTE KyInside],1   ; Check for mutual exclusion
+        je      @@Reissued
+
+        mov     [BYTE KyInside],1
+        NEWSTK  KyStack         ; Switch to local stack
+        call    [CPTR _PM_keyHandler]   ; Call C code
+        RESTSTK KyStack         ; Restore previous stack
+        mov     [BYTE KyInside],0
+
+@@Exit: popad                   ; Restore all extended registers
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+; When the BIOS keyboard handler needs to change the SHIFT status lights
+; on the keyboard, in the process of doing this the keyboard controller
+; re-issues another interrupt, while the current handler is still executing.
+; If we recieve another interrupt while still handling the current one,
+; then simply chain directly to the previous handler.
+;
+; Note that for most DOS extenders, the real mode interrupt handler that we
+; install takes care of this for us.
+
+@@Reissued:
+ifdef   TNT
+        push    eax
+        push    ebx
+        push    ecx
+        pushfd                  ; Push flags on stack to simulate interrupt
+        mov     ax,250Eh        ; Call real mode procedure function
+        mov     ebx,[_PM_prevRealKey]
+        mov     ecx,1           ; Copy real mode flags to real mode stack
+        int     21h             ; Call the real mode code
+        popfd
+        pop     ecx
+        pop     ebx
+        pop     eax
+else
+        pushf
+ifdef   USE_NASM
+        call far dword [_PM_prevKey]
+else
+        call    [_PM_prevKey]
+endif
+endif
+        jmp     @@Exit
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_chainPrevkey - Chain to previous key interrupt and return
+;----------------------------------------------------------------------------
+; Chains to the previous key interrupt routine and returns control
+; back to the high level interrupt handler.
+;----------------------------------------------------------------------------
+cprocstart  PM_chainPrevKey
+
+ifdef   TNT
+        push    eax
+        push    ebx
+        push    ecx
+        pushfd                  ; Push flags on stack to simulate interrupt
+        mov     ax,250Eh        ; Call real mode procedure function
+        mov     ebx,[_PM_prevRealKey]
+        mov     ecx,1           ; Copy real mode flags to real mode stack
+        int     21h             ; Call the real mode code
+        popfd
+        pop     ecx
+        pop     ebx
+        pop     eax
+        ret
+else
+
+; YIKES! For some strange reason, when execution returns from the
+; previous keyboard handler, interrupts are re-enabled!! Since we expect
+; interrupts to remain off during the duration of our handler, this can
+; cause havoc. However our stack macros always turn off interrupts, so they
+; will be off when we exit this routine. Obviously there is a tiny weeny
+; window when interrupts will be enabled, but there is nothing we can
+; do about this.
+
+        SWAPSTK KyStack         ; Swap back to previous stack
+        pushf                   ; Push flags on stack to simulate interrupt
+ifdef   USE_NASM
+        call far dword [_PM_prevKey]
+else
+        call    [_PM_prevKey]
+endif
+        SWAPSTK KyStack         ; Swap back to C stack again
+        ret
+endif
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_key15ISR - Int 15h keyboard interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; This routine gets called if we have been called to handle the Int 15h
+; keyboard interrupt callout from real mode.
+;
+;   Entry:  AX  - Hardware scan code to process
+;   Exit:   AX  - Hardware scan code to process (0 to ignore)
+;----------------------------------------------------------------------------
+cprocfar    _PM_key15ISR
+
+        push    ds
+        push    es
+        LOAD_DS
+        cmp     ah,4Fh
+        jnz     @@NotOurs       ; Quit if not keyboard callout
+
+        pushad
+        cld                     ; Clear direction flag
+        xor     ah,ah           ; AX := scan code
+        NEWSTK  Ky15Stack       ; Switch to local stack
+        push    _ax
+        call    [CPTR _PM_key15Handler] ; Call C code
+        _add    sp,2,4
+        RESTSTK Ky15Stack       ; Restore previous stack
+        test    ax,ax
+        jz      @@1
+        stc                     ; Set carry to process as normal
+        jmp     @@2
+@@1:    clc                     ; Clear carry to ignore scan code
+@@2:    popad
+        jmp     @@Exit          ; We are done
+
+@@NotOurs:
+ifdef   TNT
+        push    eax
+        push    ebx
+        push    ecx
+        pushfd                  ; Push flags on stack to simulate interrupt
+        mov     ax,250Eh        ; Call real mode procedure function
+        mov     ebx,[_PM_prevRealKey15]
+        mov     ecx,1           ; Copy real mode flags to real mode stack
+        int     21h             ; Call the real mode code
+        popfd
+        pop     ecx
+        pop     ebx
+        pop     eax
+else
+        pushf
+ifdef   USE_NASM
+        call far dword [_PM_prevKey15]
+else
+        call    [_PM_prevKey15]
+endif
+endif
+@@Exit: pop     es
+        pop     ds
+ifdef flatmodel
+        retf    4
+else
+        retf    2
+endif
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_breakISR - Control Break interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the Ctrl-Break interrupt. We simply set
+; the Ctrl-Break flag to a 1 and leave (note that this is accessed through
+; a far pointer, as it may well be located in conventional memory).
+;----------------------------------------------------------------------------
+cprocfar    _PM_breakISR
+
+        sti
+        push    ds              ; Save value of DS
+        push    es
+        push    _bx
+
+        LOAD_DS                 ; Load DS register
+ifdef flatmodel
+        mov     ebx,[_PM_ctrlBPtr]
+else
+        les     bx,[_PM_ctrlBPtr]
+endif
+        mov     [UINT _ES _bx],1
+
+; Run alternate break handler code if installed
+
+        cmp     [CPTR _PM_breakHandler],0
+        je      @@Exit
+
+        pushad
+        mov     _ax,1
+        push    _ax
+        call    [CPTR _PM_breakHandler] ; Call C code
+        pop     _ax
+        popad
+
+@@Exit: pop     _bx
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_ctrlBreakHit(int clearFlag)
+;----------------------------------------------------------------------------
+; Returns the current state of the Ctrl-Break flag and possibly clears it.
+;----------------------------------------------------------------------------
+cprocstart  PM_ctrlBreakHit
+
+        ARG     clearFlag:UINT
+
+        enter_c
+        pushf                   ; Save interrupt status
+        push    es
+ifdef flatmodel
+        mov     ebx,[_PM_ctrlBPtr]
+else
+        les     bx,[_PM_ctrlBPtr]
+endif
+        cli                     ; No interrupts thanks!
+        mov     _ax,[_ES _bx]
+        test    [BYTE clearFlag],1
+        jz      @@Done
+        mov     [UINT _ES _bx],0
+
+@@Done: pop     es
+        popf                    ; Restore interrupt status
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_ctrlCISR - Control Break interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the Ctrl-C interrupt. We simply set
+; the Ctrl-C flag to a 1 and leave (note that this is accessed through
+; a far pointer, as it may well be located in conventional memory).
+;----------------------------------------------------------------------------
+cprocfar    _PM_ctrlCISR
+
+        sti
+        push    ds              ; Save value of DS
+        push    es
+        push    _bx
+
+        LOAD_DS                 ; Load DS register
+ifdef flatmodel
+        mov     ebx,[_PM_ctrlCPtr]
+else
+        les     bx,[_PM_ctrlCPtr]
+endif
+        mov     [UINT _ES _bx],1
+
+; Run alternate break handler code if installed
+
+        cmp     [CPTR _PM_breakHandler],0
+        je      @@Exit
+
+        pushad
+        mov     _ax,0
+        push    _ax
+        call    [CPTR _PM_breakHandler] ; Call C code
+        pop     _ax
+        popad
+
+@@Exit: pop     _bx
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+        iretd
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_ctrlCHit(int clearFlag)
+;----------------------------------------------------------------------------
+; Returns the current state of the Ctrl-C flag and possibly clears it.
+;----------------------------------------------------------------------------
+cprocstart  PM_ctrlCHit
+
+        ARG     clearFlag:UINT
+
+        enter_c
+        pushf                   ; Save interrupt status
+        push    es
+ifdef flatmodel
+        mov     ebx,[_PM_ctrlCPtr]
+else
+        les     bx,[_PM_ctrlCPtr]
+endif
+        cli                     ; No interrupts thanks!
+        mov     _ax,[_ES _bx]
+        test    [BYTE clearFlag],1
+        jz      @@Done
+        mov     [UINT _ES _bx],0
+
+@@Done:
+        pop     es
+        popf                    ; Restore interrupt status
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_criticalISR - Control Error handler interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Interrupt handler for the MSDOS Critical Error interrupt, to dispatch
+; control to high level C based subroutines. We save the state of all
+; registers in this routine, and switch to a local stack. We also pass
+; the values of the AX and DI registers to the as pointers, so that the
+; values can be modified before returning to MSDOS.
+;----------------------------------------------------------------------------
+cprocfar    _PM_criticalISR
+
+        sti
+        push    ds              ; Save value of DS
+        push    es
+        push    _bx             ; Save register values changed
+        cld                     ; Clear direction flag
+
+        LOAD_DS                 ; Load DS register
+ifdef flatmodel
+        mov     ebx,[_PM_critPtr]
+else
+        les     bx,[_PM_critPtr]
+endif
+        mov     [_ES _bx],ax
+        mov     [_ES _bx+2],di
+
+; Run alternate critical handler code if installed
+
+        cmp     [CPTR _PM_critHandler],0
+        je      @@NoAltHandler
+
+        pushad
+        push    _di
+        push    _ax
+        call    [CPTR _PM_critHandler]  ; Call C code
+        _add    sp,4,8
+        popad
+
+        pop     _bx
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+@@NoAltHandler:
+        mov     ax,3            ; Tell MSDOS to fail the operation
+        pop     _bx
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_criticalError(int *axVal,int *diVal,int clearFlag)
+;----------------------------------------------------------------------------
+; Returns the current state of the critical error flags, and the values that
+; MSDOS passed in the AX and DI registers to our handler.
+;----------------------------------------------------------------------------
+cprocstart  PM_criticalError
+
+        ARG     axVal:DPTR, diVal:DPTR, clearFlag:UINT
+
+        enter_c
+        pushf                   ; Save interrupt status
+        push    es
+ifdef flatmodel
+        mov     ebx,[_PM_critPtr]
+else
+        les     bx,[_PM_critPtr]
+endif
+        cli                     ; No interrupts thanks!
+        xor     _ax,_ax
+        xor     _di,_di
+        mov     ax,[_ES _bx]
+        mov     di,[_ES _bx+2]
+        test    [BYTE clearFlag],1
+        jz      @@NoClear
+        mov     [ULONG _ES _bx],0
+@@NoClear:
+        _les    _bx,[axVal]
+        mov     [_ES _bx],_ax
+        _les    _bx,[diVal]
+        mov     [_ES _bx],_di
+        pop     es
+        popf                    ; Restore interrupt status
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setMouseHandler(int mask, PM_mouseHandler mh)
+;----------------------------------------------------------------------------
+cprocstart  _PM_setMouseHandler
+
+        ARG     mouseMask:UINT
+
+        enter_c
+        push    es
+
+        mov     ax,0Ch          ; AX := Function 12 - install interrupt sub
+        mov     _cx,[mouseMask] ; CX := mouse mask
+        mov     _dx,offset _PM_mouseISR
+        push    cs
+        pop     es              ; ES:_DX -> mouse handler
+        int     33h             ; Call mouse driver
+
+        pop     es
+        leave_c
+        ret
+
+cprocend
+
+ifdef flatmodel
+
+;----------------------------------------------------------------------------
+; void PM_mousePMCB(void)
+;----------------------------------------------------------------------------
+; Mouse realmode callback routine. Upon entry to this routine, we recieve
+; the following from the DPMI server:
+;
+;   Entry:  DS:_SI  -> Real mode stack at time of call
+;           ES:_DI  -> Real mode register data structure
+;           SS:_SP  -> Locked protected mode stack to use
+;----------------------------------------------------------------------------
+cprocfar    _PM_mousePMCB
+
+        pushad
+        mov     eax,[es:_di+1Ch]    ; Load register values from real mode
+        mov     ebx,[es:_di+10h]
+        mov     ecx,[es:_di+18h]
+        mov     edx,[es:_di+14h]
+        mov     esi,[es:_di+04h]
+        mov     edi,[es:_di]
+        call    _PM_mouseISR        ; Call the mouse handler
+        popad
+
+        mov     ax,[ds:_si]
+        mov     [es:_di+2Ah],ax     ; Plug in return IP address
+        mov     ax,[ds:_si+2]
+        mov     [es:_di+2Ch],ax     ; Plug in return CS value
+        add     [WORD es:_di+2Eh],4 ; Remove return address from stack
+        iret                        ; Go back to real mode!
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_int10PMCB(void)
+;----------------------------------------------------------------------------
+; int10 realmode callback routine. Upon entry to this routine, we recieve
+; the following from the DPMI server:
+;
+;   Entry:  DS:ESI  -> Real mode stack at time of call
+;           ES:EDI  -> Real mode register data structure
+;           SS:ESP  -> Locked protected mode stack to use
+;----------------------------------------------------------------------------
+cprocfar        _PM_int10PMCB
+
+        pushad
+        push    ds
+        push    es
+        push    fs
+
+        pushfd
+        pop     eax
+        mov     [es:edi+20h],ax     ; Save return flag status
+        mov     ax,[ds:esi]
+        mov     [es:edi+2Ah],ax     ; Plug in return IP address
+        mov     ax,[ds:esi+2]
+        mov     [es:edi+2Ch],ax     ; Plug in return CS value
+        add     [WORD es:edi+2Eh],4 ; Remove return address from stack
+
+; Call the install int10 handler in protected mode. This function gets called
+; with DS set to the current data selector, and ES:EDI pointing the the
+; real mode DPMI register structure at the time of the interrupt. The
+; handle must be written in assembler to be able to extract the real mode
+; register values from the structure
+
+        push    es
+        pop     fs                  ; FS:EDI -> real mode registers
+        LOAD_DS
+        NEWSTK  Int10Stack          ; Switch to local stack
+
+        call    [_PM_int10Handler]
+
+        RESTSTK Int10Stack          ; Restore previous stack
+        pop     fs
+        pop     es
+        pop     ds
+        popad
+        iret                        ; Go back to real mode!
+
+cprocend
+
+endif
+
+cpublic _PM_pmdosCodeEnd
+
+endcodeseg  _pmdos
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm
new file mode 100755
index 0000000..34985a9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm
@@ -0,0 +1,652 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;*            Based on original code Copyright 1994 Otto Chrons
+;*
+;* Language:    80386 Assembler, TASM 4.0 or later
+;* Environment: IBM PC 32 bit protected mode
+;*
+;* Description: Low level page fault handler for virtual linear framebuffers.
+;*
+;****************************************************************************
+
+        IDEAL
+        JUMPS
+
+include "scitech.mac"           ; Memory model macros
+
+header      _vflat              ; Set up memory model
+
+VFLAT_START     EQU 0F0000000h
+VFLAT_END       EQU 0F03FFFFFh
+PAGE_PRESENT    EQU 1
+PAGE_NOTPRESENT EQU 0
+PAGE_READ       EQU 0
+PAGE_WRITE      EQU 2
+
+ifdef   DOS4GW
+
+;----------------------------------------------------------------------------
+; DOS4G/W flat linear framebuffer emulation.
+;----------------------------------------------------------------------------
+
+begdataseg  _vflat
+
+; Near pointers to the page directory base and our page tables. All of
+; this memory is always located in the first Mb of DOS memory.
+
+PDBR            dd  0               ; Page directory base register (CR3)
+accessPageAddr  dd  0
+accessPageTable dd  0
+
+; CauseWay page directory & 1st page table linear addresses.
+
+CauseWayDIRLinear dd 0
+CauseWay1stLinear dd 0
+
+; Place to store a copy of the original Page Table Directory before we
+; intialised our virtual buffer code.
+
+pageDirectory:  resd 1024           ; Saved page table directory
+
+ValidCS         dw  0               ; Valid CS for page faults
+Ring0CS         dw  0               ; Our ring 0 code selector
+LastPage        dd  0               ; Last page we mapped in
+BankFuncBuf:    resb 101            ; Place to store bank switch code
+BankFuncPtr     dd  offset BankFuncBuf
+
+INT14Gate:
+INT14Offset     dd      0           ; eip of original vector
+INT14Selector   dw      0           ; cs of original vector
+
+        cextern _PM_savedDS,USHORT
+        cextern VF_haveCauseWay,BOOL
+
+enddataseg  _vflat
+
+begcodeseg  _vflat              ; Start of code segment
+
+        cextern VF_malloc,FPTR
+
+;----------------------------------------------------------------------------
+; PF_handler64k - Page fault handler for 64k banks
+;----------------------------------------------------------------------------
+; The handler below is a 32 bit ring 0 page fault handler.  It receives
+; control immediately after any page fault or after an IRQ6 (hardware
+; interrupt). This provides the fastest possible handling of page faults
+; since it jump directly here.  If this is a page fault, the number
+; immediately on the stack will be an error code, at offset 4 will be
+; the eip of the faulting instruction, at offset 8 will be the cs of the
+; faulting instruction.  If it is a hardware interrupt, it will not have
+; the error code and the eflags will be at offset 8.
+;----------------------------------------------------------------------------
+cprocfar    PF_handler64k
+
+; Check if this is a processor exeception or a page fault
+
+        push    eax
+        mov     ax,[cs:ValidCS]     ; Use CS override to access data
+        cmp     [ss:esp+12],ax      ; Is this a page fault?
+        jne     @@ToOldHandler      ; Nope, jump to the previous handler
+
+; Get address of page fault and check if within our handlers range
+
+        mov     eax,cr2             ; EBX has page fault linear address
+        cmp     eax,VFLAT_START     ; Is the fault less than ours?
+        jb      @@ToOldHandler      ; Yep, go to previous handler
+        cmp     eax,VFLAT_END       ; Is the fault more than ours?
+        jae     @@ToOldHandler      ; Yep, go to previous handler
+
+; This is our page fault, so we need to handle it
+
+        pushad
+        push    ds
+        push    es
+        mov     ebx,eax             ; EBX := page fault address
+        and     ebx,invert 0FFFFh   ; Mask to 64k bank boundary
+        mov     ds,[cs:_PM_savedDS]; Load segment registers
+        mov     es,[cs:_PM_savedDS]
+
+; Map in the page table for our virtual framebuffer area for modification
+
+        mov     edi,[PDBR]          ; EDI points to page directory
+        mov     edx,ebx             ; EDX = linear address
+        shr     edx,22              ; EDX = offset to page directory
+        mov     edx,[edx*4+edi]     ; EDX = physical page table address
+        mov     eax,edx
+        mov     edx,[accessPageTable]
+        or      eax,7
+        mov     [edx],eax
+        mov     eax,cr3
+        mov     cr3,eax             ; Update page table cache
+
+; Mark all pages valid for the new page fault area
+
+        mov     esi,ebx             ; ESI := linear address for page
+        shr     esi,10
+        and     esi,0FFFh           ; Offset into page table
+        add     esi,[accessPageAddr]
+ifdef   USE_NASM
+%assign off 0
+%rep 16
+        or      [DWORD esi+off],0000000001h ; Enable pages
+%assign off off+4
+%endrep
+else
+off = 0
+REPT    16
+        or      [DWORD esi+off],0000000001h ; Enable pages
+off = off+4
+ENDM
+endif
+
+; Mark all pages invalid for the previously mapped area
+
+        xchg    esi,[LastPage]      ; Save last page for next page fault
+        test    esi,esi
+        jz      @@DoneMapping       ; Dont update if first time round
+ifdef   USE_NASM
+%assign off 0
+%rep 16
+        or      [DWORD esi+off],0FFFFFFFEh  ; Disable pages
+%assign off off+4
+%endrep
+else
+off = 0
+REPT    16
+        and     [DWORD esi+off],0FFFFFFFEh  ; Disable pages
+off = off+4
+ENDM
+endif
+
+@@DoneMapping:
+        mov     eax,cr3
+        mov     cr3,eax             ; Flush the TLB
+
+; Now program the new SuperVGA starting bank address
+
+        mov     eax,ebx             ; EAX := page fault address
+        shr     eax,16
+        and     eax,0FFh            ; Mask to 0-255
+        call    [BankFuncPtr]       ; Call the bank switch function
+
+        pop     es
+        pop     ds
+        popad
+        pop     eax
+        add     esp,4               ; Pop the error code from stack
+        iretd                       ; Return to faulting instruction
+
+@@ToOldHandler:
+        pop     eax
+ifdef   USE_NASM
+        jmp far dword [cs:INT14Gate]; Chain to previous handler
+else
+        jmp     [FWORD cs:INT14Gate]; Chain to previous handler
+endif
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PF_handler4k  - Page fault handler for 4k banks
+;----------------------------------------------------------------------------
+; The handler below is a 32 bit ring 0 page fault handler.  It receives
+; control immediately after any page fault or after an IRQ6 (hardware
+; interrupt). This provides the fastest possible handling of page faults
+; since it jump directly here.  If this is a page fault, the number
+; immediately on the stack will be an error code, at offset 4 will be
+; the eip of the faulting instruction, at offset 8 will be the cs of the
+; faulting instruction.  If it is a hardware interrupt, it will not have
+; the error code and the eflags will be at offset 8.
+;----------------------------------------------------------------------------
+cprocfar    PF_handler4k
+
+; Fill in when we have tested all the 64Kb code
+
+ifdef   USE_NASM
+        jmp far dword [cs:INT14Gate]; Chain to previous handler
+else
+        jmp     [FWORD cs:INT14Gate]; Chain to previous handler
+endif
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void InstallFaultHandler(void *baseAddr,int bankSize)
+;----------------------------------------------------------------------------
+; Installes the page fault handler directly int the interrupt descriptor
+; table for maximum performance. This of course requires ring 0 access,
+; but none of this stuff will run without ring 0!
+;----------------------------------------------------------------------------
+cprocstart  InstallFaultHandler
+
+        ARG     baseAddr:ULONG, bankSize:UINT
+
+        enter_c
+
+        mov     [DWORD LastPage],0  ; No pages have been mapped
+        mov     ax,cs
+        mov     [ValidCS],ax        ; Save CS value for page faults
+
+; Put address of our page fault handler into the IDT directly
+
+        sub     esp,6               ; Allocate space on stack
+ifdef   USE_NASM
+        sidt    [ss:esp]            ; Store pointer to IDT
+else
+        sidt    [FWORD ss:esp]      ; Store pointer to IDT
+endif
+        pop     ax                  ; add esp,2
+        pop     eax                 ; Absolute address of IDT
+        add     eax,14*8            ; Point to Int #14
+
+; Note that Interrupt gates do not have the high and low word of the
+; offset in adjacent words in memory, there are 4 bytes separating them.
+
+        mov     ecx,[eax]           ; Get cs and low 16 bits of offset
+        mov     edx,[eax+6]         ; Get high 16 bits of offset in dx
+        shl     edx,16
+        mov     dx,cx               ; edx has offset
+        mov     [INT14Offset],edx   ; Save offset
+        shr     ecx,16
+        mov     [INT14Selector],cx  ; Save original cs
+        mov     [eax+2],cs          ; Install new cs
+        mov     edx,offset PF_handler64k
+        cmp     [UINT bankSize],4
+        jne     @@1
+        mov     edx,offset PF_handler4k
+@@1:    mov     [eax],dx            ; Install low word of offset
+        shr     edx,16
+        mov     [eax+6],dx          ; Install high word of offset
+
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void RemoveFaultHandler(void)
+;----------------------------------------------------------------------------
+; Closes down the virtual framebuffer services and restores the previous
+; page fault handler.
+;----------------------------------------------------------------------------
+cprocstart  RemoveFaultHandler
+
+        enter_c
+
+; Remove page fault handler from IDT
+
+        sub     esp,6               ; Allocate space on stack
+ifdef   USE_NASM
+        sidt    [ss:esp]            ; Store pointer to IDT
+else
+        sidt    [FWORD ss:esp]      ; Store pointer to IDT
+endif
+
+        pop     ax                  ; add esp,2
+        pop     eax                 ; Absolute address of IDT
+        add     eax,14*8            ; Point to Int #14
+        mov     cx,[INT14Selector]
+        mov     [eax+2],cx          ; Restore original CS
+        mov     edx,[INT14Offset]
+        mov     [eax],dx            ; Install low word of offset
+        shr     edx,16
+        mov     [eax+6],dx          ; Install high word of offset
+
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void InstallBankFunc(int codeLen,void *bankFunc)
+;----------------------------------------------------------------------------
+; Installs the bank switch function by relocating it into our data segment
+; and making it into a callable function. We do it this way to make the
+; code identical to the way that the VflatD devices work under Windows.
+;----------------------------------------------------------------------------
+cprocstart  InstallBankFunc
+
+        ARG     codeLen:UINT, bankFunc:DPTR
+
+        enter_c
+
+        mov     esi,[bankFunc]      ; Copy the code into buffer
+        mov     edi,offset BankFuncBuf
+        mov     ecx,[codeLen]
+    rep movsb
+        mov     [BYTE edi],0C3h     ; Terminate the function with a near ret
+
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int InitPaging(void)
+;----------------------------------------------------------------------------
+; Initializes paging system. If paging is not enabled, builds a page table
+; directory and page tables for physical memory
+;
+;   Exit:       0   - Successful
+;               -1  - Couldn't initialize paging mechanism
+;----------------------------------------------------------------------------
+cprocstart  InitPaging
+
+        push    ebx
+        push    ecx
+        push    edx
+        push    esi
+        push    edi
+
+; Are we running under CauseWay?
+
+        mov     ax,0FFF9h
+        int     31h
+        jc      @@NotCauseway
+        cmp     ecx,"CAUS"
+        jnz     @@NotCauseway
+        cmp     edx,"EWAY"
+        jnz     @@NotCauseway
+
+        mov     [BOOL VF_haveCauseWay],1
+        mov     [CauseWayDIRLinear],esi
+        mov     [CauseWay1stLinear],edi
+
+; Check for DPMI
+
+        mov     ax,0ff00h
+        push    es
+        int     31h
+        pop     es
+        shr     edi,2
+        and     edi,3
+        cmp     edi,2
+        jz      @@ErrExit               ; Not supported under DPMI
+
+        mov     eax,[CauseWayDIRLinear]
+        jmp     @@CopyCR3
+
+@@NotCauseway:
+        mov     ax,cs
+        test    ax,3                    ; Which ring are we running
+        jnz     @@ErrExit               ; Needs zero ring to access
+                                        ; page tables (CR3)
+        mov     eax,cr0                 ; Load CR0
+        test    eax,80000000h           ; Is paging enabled?
+        jz      @@ErrExit               ; No, we must have paging!
+
+        mov     eax,cr3                 ; Load directory address
+        and     eax,0FFFFF000h
+
+@@CopyCR3:
+        mov     [PDBR],eax              ; Save it
+        mov     esi,eax
+        mov     edi,offset pageDirectory
+        mov     ecx,1024
+        cld
+        rep     movsd                   ; Copy the original page table directory
+        cmp     [DWORD accessPageAddr],0; Check if we have allocated page
+        jne     @@HaveRealMem           ; table already (we cant free it)
+
+        mov     eax,0100h               ; DPMI DOS allocate
+        mov     ebx,8192/16
+        int     31h                     ; Allocate 8192 bytes
+        and     eax,0FFFFh
+        shl     eax,4                   ; EAX points to newly allocated memory
+        add     eax,4095
+        and     eax,0FFFFF000h          ; Page align
+        mov     [accessPageAddr],eax
+
+@@HaveRealMem:
+        mov     eax,[accessPageAddr]    ; EAX -> page table in 1st Mb
+        shr     eax,12
+        and     eax,3FFh                ; Page table offset
+        shl     eax,2
+        cmp     [BOOL VF_haveCauseWay],0
+        jz      @@NotCW0
+        mov     ebx,[CauseWay1stLinear]
+        jmp     @@Put1st
+
+@@NotCW0:
+        mov     ebx,[PDBR]
+        mov     ebx,[ebx]
+        and     ebx,0FFFFF000h          ; Page table for 1st megabyte
+
+@@Put1st:
+        add     eax,ebx
+        mov     [accessPageTable],eax
+        sub     eax,eax                 ; No error
+        jmp     @@Exit
+
+@@ErrExit:
+        mov     eax,-1
+
+@@Exit: pop     edi
+        pop     esi
+        pop     edx
+        pop     ecx
+        pop     ebx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void ClosePaging(void)
+;----------------------------------------------------------------------------
+; Closes the paging system
+;----------------------------------------------------------------------------
+cprocstart  ClosePaging
+
+        push    eax
+        push    ecx
+        push    edx
+        push    esi
+        push    edi
+
+        mov     eax,[accessPageAddr]
+        call    AccessPage              ; Restore AccessPage mapping
+        mov     edi,[PDBR]
+        mov     esi,offset pageDirectory
+        mov     ecx,1024
+        cld
+        rep     movsd                   ; Restore the original page table directory
+
+@@Exit: pop     edi
+        pop     esi
+        pop     edx
+        pop     ecx
+        pop     eax
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; long AccessPage(long phys)
+;----------------------------------------------------------------------------
+; Maps a known page to given physical memory
+;   Entry:      EAX - Physical memory
+;   Exit:       EAX - Linear memory address of mapped phys mem
+;----------------------------------------------------------------------------
+cprocstatic     AccessPage
+
+        push    edx
+        mov     edx,[accessPageTable]
+        or      eax,7
+        mov     [edx],eax
+        mov     eax,cr3
+        mov     cr3,eax                 ; Update page table cache
+        mov     eax,[accessPageAddr]
+        pop     edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; long GetPhysicalAddress(long linear)
+;----------------------------------------------------------------------------
+; Returns the physical address of linear address
+;   Entry:      EAX - Linear address to convert
+;   Exit:       EAX - Physical address
+;----------------------------------------------------------------------------
+cprocstatic     GetPhysicalAddress
+
+        push    ebx
+        push    edx
+        mov     edx,eax
+        shr     edx,22                  ; EDX is the directory offset
+        mov     ebx,[PDBR]
+        mov     edx,[edx*4+ebx]         ; Load page table address
+        push    eax
+        mov     eax,edx
+        call    AccessPage              ; Access the page table
+        mov     edx,eax
+        pop     eax
+        shr     eax,12
+        and     eax,03FFh               ; EAX offset into page table
+        mov     eax,[edx+eax*4]         ; Load physical address
+        and     eax,0FFFFF000h
+        pop     edx
+        pop     ebx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void CreatePageTable(long pageDEntry)
+;----------------------------------------------------------------------------
+; Creates a page table for specific address (4MB)
+;       Entry:  EAX - Page directory entry (top 10-bits of address)
+;----------------------------------------------------------------------------
+cprocstatic     CreatePageTable
+
+        push    ebx
+        push    ecx
+        push    edx
+        push    edi
+        mov     ebx,eax                 ; Save address
+        mov     eax,8192
+        push    eax
+        call    VF_malloc              ; Allocate page table directory
+        add     esp,4
+        add     eax,0FFFh
+        and     eax,0FFFFF000h          ; Page align (4KB)
+        mov     edi,eax                 ; Save page table linear address
+        sub     eax,eax                 ; Fill with zero
+        mov     ecx,1024
+        cld
+        rep     stosd                   ; Clear page table
+        sub     edi,4096
+        mov     eax,edi
+        call    GetPhysicalAddress
+        mov     edx,[PDBR]
+        or      eax,7                   ; Present/write/user bit
+        mov     [edx+ebx*4],eax         ; Save physical address into page directory
+        mov     eax,cr3
+        mov     cr3,eax                 ; Update page table cache
+        pop     edi
+        pop     edx
+        pop     ecx
+        pop     ebx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags);
+;----------------------------------------------------------------------------
+; Maps physical memory into linear memory
+;   Entry:      pAddr   - Physical address
+;               lAddr   - Linear address
+;               pages   - Number of 4K pages to map
+;               flags   - Page flags
+;                           bit 0   =       present
+;                           bit 1   =       Read(0)/Write(1)
+;----------------------------------------------------------------------------
+cprocstart  MapPhysical2Linear
+
+        ARG     pAddr:ULONG, lAddr:ULONG, pages:UINT, pflags:UINT
+
+        enter_c
+
+        and     [ULONG pAddr],0FFFFF000h; Page boundary
+        and     [ULONG lAddr],0FFFFF000h; Page boundary
+        mov     ecx,[pflags]
+        and     ecx,11b                 ; Just two bits
+        or      ecx,100b                ; Supervisor bit
+        mov     [pflags],ecx
+
+        mov     edx,[lAddr]
+        shr     edx,22                  ; EDX = Directory
+        mov     esi,[PDBR]
+        mov     edi,[pages]             ; EDI page count
+        mov     ebx,[lAddr]
+
+@@CreateLoop:
+        mov     ecx,[esi+edx*4]         ; Load page table address
+        test    ecx,1                   ; Is it present?
+        jnz     @@TableOK
+        mov     eax,edx
+        call    CreatePageTable         ; Create a page table
+@@TableOK:
+        mov     eax,ebx
+        shr     eax,12
+        and     eax,3FFh
+        sub     eax,1024
+        neg     eax                     ; EAX = page count in this table
+        inc     edx                     ; Next table
+        mov     ebx,0                   ; Next time we'll map 1K pages
+        sub     edi,eax                 ; Subtract mapped pages from page count
+        jns     @@CreateLoop            ; Create more tables if necessary
+
+        mov     ecx,[pages]             ; ECX = Page count
+        mov     esi,[lAddr]
+        shr     esi,12                  ; Offset part isn't needed
+        mov     edi,[pAddr]
+@@MappingLoop:
+        mov     eax,esi
+        shr     eax,10                  ; EAX = offset to page directory
+        mov     ebx,[PDBR]
+        mov     eax,[eax*4+ebx]         ; EAX = page table address
+        call    AccessPage
+        mov     ebx,esi
+        and     ebx,3FFh                ; EBX = offset to page table
+        mov     edx,edi
+        add     edi,4096                ; Next physical address
+        inc     esi                     ; Next linear page
+        or      edx,[pflags]            ; Update flags...
+        mov     [eax+ebx*4],edx         ; Store page table entry
+        loop    @@MappingLoop
+        mov     eax,cr3
+        mov     cr3,eax                 ; Update page table cache
+
+        leave_c
+        ret
+
+cprocend
+
+endcodeseg  _vflat
+
+endif
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c
new file mode 100755
index 0000000..ee117c7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c
@@ -0,0 +1,72 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  DOS
+*
+* Description:  MSDOS specific code for the CPU detection module.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* External timing function */
+
+void __ZTimerInit(void);
+
+/****************************************************************************
+REMARKS:
+Do nothing for DOS because we don't have thread priorities.
+****************************************************************************/
+#define SetMaxThreadPriority()      0
+
+/****************************************************************************
+REMARKS:
+Do nothing for DOS because we don't have thread priorities.
+****************************************************************************/
+#define RestoreThreadPriority(i)    (void)(i)
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    ulong   resolution;
+
+    __ZTimerInit();
+    ULZTimerResolution(&resolution);
+    freq->low = (ulong)(10000000000.0 / resolution);
+    freq->high = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)                   \
+{                                       \
+    (t)->low = ULZReadTime() * 10000L;  \
+    (t)->high = 0;                      \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/event.c b/board/MAI/bios_emulator/scitech/src/pm/dos/event.c
new file mode 100755
index 0000000..a969d11
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/event.c
@@ -0,0 +1,494 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit DOS
+*
+* Description:  32-bit DOS implementation for the SciTech cross platform
+*               event library.
+*
+****************************************************************************/
+
+/*--------------------------- Global variables ----------------------------*/
+
+ibool _VARAPI   _EVT_useEvents = true;  /* True to use event handling   */
+ibool _VARAPI   _EVT_installed = 0;     /* Event handers installed?     */
+uchar _VARAPI   *_EVT_biosPtr = NULL;   /* Pointer to the BIOS data area */
+static ibool    haveMouse = false;      /* True if we have a mouse      */
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* External assembler functions */
+
+void    EVTAPI _EVT_pollJoystick(void);
+uint    EVTAPI _EVT_disableInt(void);
+uint    EVTAPI _EVT_restoreInt(uint flags);
+void    EVTAPI _EVT_codeStart(void);
+void    EVTAPI _EVT_codeEnd(void);
+void    EVTAPI _EVT_cCodeStart(void);
+void    EVTAPI _EVT_cCodeEnd(void);
+int     EVTAPI _EVT_getKeyCode(void);
+void    EVTAPI _EVT_pumpMessages(void);
+int     EVTAPI EVT_rdinx(int port,int index);
+void    EVTAPI EVT_wrinx(int port,int index,int value);
+
+#ifdef NO_KEYBOARD_INTERRUPT
+/****************************************************************************
+REMARKS:
+This function is used to pump all keyboard messages from the BIOS keyboard
+handler into our event queue. This can be used to avoid using the
+installable keyboard handler if this is causing problems.
+****************************************************************************/
+static void EVTAPI _EVT_pumpMessages(void)
+{
+    RMREGS  regs;
+	uint    key,ps;
+
+	/* Since the keyboard ISR has not been installed if NO_IDE_BUG has
+	 * been defined, we first check for any pending keyboard events
+	 * here, and if there are some insert them into the event queue to
+	 * be picked up later - what a kludge.
+	 */
+	while ((key = _EVT_getKeyCode()) != 0) {
+		ps = _EVT_disableInt();
+		addKeyEvent(EVT_KEYDOWN, key);
+		_EVT_restoreInt(ps);
+		}
+
+    regs.x.ax = 0x0B;           /* Reset Move Mouse */
+    PM_int86(0x33,&regs,&regs);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{
+    return (ulong)PM_getLong(_EVT_biosPtr+0x6C) * 55UL;
+}
+
+/****************************************************************************
+REMARKS:
+Reboots the machine from DOS (warm boot)
+****************************************************************************/
+static void Reboot(void)
+{
+    PMREGS  regs;
+    PMSREGS sregs;
+
+    ushort *rebootType = PM_mapRealPointer(0x40,0x72);
+    *rebootType = 0x1234;
+    PM_callRealMode(0xFFFF,0x0000,&regs,&sregs);
+}
+
+/****************************************************************************
+REMARKS:
+Include generic raw scancode keyboard module.
+****************************************************************************/
+#define SUPPORT_CTRL_ALT_DEL
+#include "common/keyboard.c"
+
+/****************************************************************************
+REMARKS:
+This function fools the DOS mouse driver into thinking that it is running
+in graphics mode, rather than text mode so we always get virtual coordinates
+correctly rather than character coordinates.
+****************************************************************************/
+int _EVT_foolMouse(void)
+{
+    int oldmode = PM_getByte(_EVT_biosPtr+0x49);
+    PM_setByte(_EVT_biosPtr+0x49,0x10);
+    oldmode |= (EVT_rdinx(0x3C4,0x2) << 8);
+    return oldmode;
+}
+
+/****************************************************************************
+REMARKS:
+This function unfools the DOS mouse driver after we have finished calling it.
+****************************************************************************/
+void _EVT_unfoolMouse(
+    int oldmode)
+{
+    PM_setByte(_EVT_biosPtr+0x49,oldmode);
+
+    /* Some mouse drivers reset the plane mask register for VGA plane 4
+     * modes, which screws up the display on some VGA compatible controllers
+     * in SuperVGA modes. We reset the value back again in here to solve
+     * the problem.
+     */
+    EVT_wrinx(0x3C4,0x2,oldmode >> 8);
+}
+
+/****************************************************************************
+REMARKS:
+Determines if we have a mouse attached and functioning.
+****************************************************************************/
+static ibool detectMouse(void)
+{
+    RMREGS  regs;
+    RMSREGS sregs;
+    uchar   *p;
+    ibool   retval;
+
+    regs.x.ax = 0x3533;                 /* Get interrupt vector 0x33    */
+    PM_int86x(0x21,&regs,&regs,&sregs);
+
+    /* Check that interrupt vector 0x33 is not a zero, and that the first
+     * instruction in the interrupt vector is not an IRET instruction
+     */
+    p = PM_mapRealPointer(sregs.es, regs.x.bx);
+    retval = ((sregs.es != 0) || (regs.x.bx != 0)) && (PM_getByte(p) != 207);
+    return retval;
+}
+
+/****************************************************************************
+PARAMETERS:
+what        - Event code
+message     - Event message
+x,y         - Mouse position at time of event
+but_stat    - Mouse button status at time of event
+
+REMARKS:
+Adds a new mouse event to the event queue. This routine is called from within
+the mouse interrupt subroutine, so it must be efficient.
+
+NOTE:   Interrupts MUST be OFF while this routine is called to ensure we have
+	mutually exclusive access to our internal data structures for
+	interrupt driven systems (like under DOS).
+****************************************************************************/
+static void addMouseEvent(
+    uint what,
+    uint message,
+    int x,
+    int y,
+    int mickeyX,
+    int mickeyY,
+    uint but_stat)
+{
+    event_t evt;
+
+    if (EVT.count < EVENTQSIZE) {
+	/* Save information in event record. */
+	evt.when = _EVT_getTicks();
+	evt.what = what;
+	evt.message = message;
+	evt.modifiers = but_stat;
+	evt.where_x = x;                /* Save mouse event position    */
+	evt.where_y = y;
+	evt.relative_x = mickeyX;
+	evt.relative_y = mickeyY;
+	evt.modifiers |= EVT.keyModifiers;
+	addEvent(&evt);                 /* Add to tail of event queue   */
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+mask        - Event mask
+butstate    - Button state
+x           - Mouse x coordinate
+y           - Mouse y coordinate
+
+REMARKS:
+Mouse event handling routine. This gets called when a mouse event occurs,
+and we call the addMouseEvent() routine to add the appropriate mouse event
+to the event queue.
+
+Note: Interrupts are ON when this routine is called by the mouse driver code.
+****************************************************************************/
+static void EVTAPI mouseISR(
+    uint mask,
+    uint butstate,
+    int x,
+    int y,
+    int mickeyX,
+    int mickeyY)
+{
+    uint    ps;
+    uint    buttonMask;
+
+    if (mask & 1) {
+	/* Save the current mouse coordinates */
+	EVT.mx = x; EVT.my = y;
+
+	/* If the last event was a movement event, then modify the last
+	 * event rather than post a new one, so that the queue will not
+	 * become saturated. Before we modify the data structures, we
+	 * MUST ensure that interrupts are off.
+	 */
+	ps = _EVT_disableInt();
+	if (EVT.oldMove != -1) {
+	    EVT.evtq[EVT.oldMove].where_x = x;  /* Modify existing one  */
+	    EVT.evtq[EVT.oldMove].where_y = y;
+	    EVT.evtq[EVT.oldMove].relative_x += mickeyX;
+	    EVT.evtq[EVT.oldMove].relative_y += mickeyY;
+	    }
+	else {
+	    EVT.oldMove = EVT.freeHead;         /* Save id of this move event   */
+	    addMouseEvent(EVT_MOUSEMOVE,0,x,y,mickeyX,mickeyY,butstate);
+	    }
+	_EVT_restoreInt(ps);
+	}
+    if (mask & 0x2A) {
+	ps = _EVT_disableInt();
+	buttonMask = 0;
+	if (mask & 2)  buttonMask |= EVT_LEFTBMASK;
+	if (mask & 8)  buttonMask |= EVT_RIGHTBMASK;
+	if (mask & 32) buttonMask |= EVT_MIDDLEBMASK;
+	addMouseEvent(EVT_MOUSEDOWN,buttonMask,x,y,0,0,butstate);
+	EVT.oldMove = -1;
+	_EVT_restoreInt(ps);
+	}
+    if (mask & 0x54) {
+	ps = _EVT_disableInt();
+	buttonMask = 0;
+	if (mask & 2)  buttonMask |= EVT_LEFTBMASK;
+	if (mask & 8)  buttonMask |= EVT_RIGHTBMASK;
+	if (mask & 32) buttonMask |= EVT_MIDDLEBMASK;
+	addMouseEvent(EVT_MOUSEUP,buttonMask,x,y,0,0,butstate);
+	EVT.oldMove = -1;
+	_EVT_restoreInt(ps);
+	}
+    EVT.oldKey = -1;
+}
+
+/****************************************************************************
+REMARKS:
+Keyboard interrupt handler function.
+
+NOTE:   Interrupts are OFF when this routine is called by the keyboard ISR,
+	and we leave them OFF the entire time.
+****************************************************************************/
+static void EVTAPI keyboardISR(void)
+{
+    processRawScanCode(PM_inpb(0x60));
+    PM_outpb(0x20,0x20);
+}
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort()
+{
+    EVT_exit();
+    PM_fatalError("Unhandled exception!");
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    int     i;
+
+    PM_init();
+    EVT.mouseMove = mouseMove;
+    _EVT_biosPtr = PM_getBIOSPointer();
+    EVT_resume();
+
+    /* Grab all characters pending in the keyboard buffer and stuff
+     * them into our event buffer. This allows us to pick up any keypresses
+     * while the program is initialising.
+     */
+    while ((i = _EVT_getKeyCode()) != 0)
+	addKeyEvent(EVT_KEYDOWN,i);
+}
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVTAPI EVT_resume(void)
+{
+    static int      locked = 0;
+    int             stat;
+    uchar           mods;
+    PM_lockHandle   lh; /* Unused in DOS */
+
+    if (_EVT_useEvents) {
+	/* Initialise the event queue and enable our interrupt handlers */
+	initEventQueue();
+#ifndef NO_KEYBOARD_INTERRUPT
+	PM_setKeyHandler(keyboardISR);
+#endif
+#ifndef NO_MOUSE_INTERRUPT
+	if ((haveMouse = detectMouse()) != 0) {
+	    int oldmode = _EVT_foolMouse();
+	    PM_setMouseHandler(0xFFFF,mouseISR);
+	    _EVT_unfoolMouse(oldmode);
+	    }
+#endif
+
+	/* Read the keyboard modifier flags from the BIOS to get the
+	 * correct initialisation state. The only state we care about is
+	 * the correct toggle state flags such as SCROLLLOCK, NUMLOCK and
+	 * CAPSLOCK.
+	 */
+	EVT.keyModifiers = 0;
+	mods = PM_getByte(_EVT_biosPtr+0x17);
+	if (mods & 0x10)
+	    EVT.keyModifiers |= EVT_SCROLLLOCK;
+	if (mods & 0x20)
+	    EVT.keyModifiers |= EVT_NUMLOCK;
+	if (mods & 0x40)
+	    EVT.keyModifiers |= EVT_CAPSLOCK;
+
+	/* Lock all of the code and data used by our protected mode interrupt
+	 * handling routines, so that it will continue to work correctly
+	 * under real mode.
+	 */
+	if (!locked) {
+	    /* It is difficult to ensure that we lock our global data, so we
+	     * do this by taking the address of a variable locking all data
+	     * 2Kb on either side. This should properly cover the global data
+	     * used by the module (the other alternative is to declare the
+	     * variables in assembler, in which case we know it will be
+	     * correct).
+	     */
+	    stat  = !PM_lockDataPages(&EVT,sizeof(EVT),&lh);
+	    stat |= !PM_lockDataPages(&_EVT_biosPtr,sizeof(_EVT_biosPtr),&lh);
+	    stat |= !PM_lockCodePages((__codePtr)_EVT_cCodeStart,(int)_EVT_cCodeEnd-(int)_EVT_cCodeStart,&lh);
+	    stat |= !PM_lockCodePages((__codePtr)_EVT_codeStart,(int)_EVT_codeEnd-(int)_EVT_codeStart,&lh);
+	    if (stat) {
+		PM_fatalError("Page locking services failed - interrupt handling not safe!");
+		exit(1);
+		}
+	    locked = 1;
+	    }
+
+	/* Catch program termination signals so we can clean up properly */
+	signal(SIGABRT, _EVT_abort);
+	signal(SIGFPE, _EVT_abort);
+	signal(SIGINT, _EVT_abort);
+	_EVT_installed = true;
+	}
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    RMREGS  regs;
+
+    if (haveMouse) {
+	int oldmode = _EVT_foolMouse();
+	PM_resetMouseDriver(1);
+	regs.x.ax = 7;  /* Mouse function 7 - Set horizontal min and max */
+	regs.x.cx = 0;
+	regs.x.dx = xRes;
+	PM_int86(0x33,&regs,&regs);
+	regs.x.ax = 8;  /* Mouse function 8 - Set vertical min and max   */
+	regs.x.cx = 0;
+	regs.x.dx = yRes;
+	PM_int86(0x33,&regs,&regs);
+	_EVT_unfoolMouse(oldmode);
+	}
+}
+
+/****************************************************************************
+REMARKS
+Modifes the mouse coordinates as necessary if scaling to OS coordinates,
+and sets the OS mouse cursor position.
+****************************************************************************/
+void _EVT_setMousePos(
+    int *x,
+    int *y)
+{
+    RMREGS  regs;
+
+    if (haveMouse) {
+	int oldmode = _EVT_foolMouse();
+	regs.x.ax = 4;      /* Mouse function 4 - Set mouse position    */
+	regs.x.cx = *x;     /* New horizontal coordinate                */
+	regs.x.dx = *y;     /* New vertical coordinate                  */
+	PM_int86(0x33,&regs,&regs);
+	_EVT_unfoolMouse(oldmode);
+	}
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVTAPI EVT_suspend(void)
+{
+    uchar   mods;
+
+    if (_EVT_installed) {
+	/* Restore the interrupt handlers */
+	PM_restoreKeyHandler();
+	if (haveMouse)
+	    PM_restoreMouseHandler();
+	signal(SIGABRT, SIG_DFL);
+	signal(SIGFPE, SIG_DFL);
+	signal(SIGINT, SIG_DFL);
+
+	/* Set the keyboard modifier flags in the BIOS to our values */
+	EVT_allowLEDS(true);
+	mods = PM_getByte(_EVT_biosPtr+0x17) & ~0x70;
+	if (EVT.keyModifiers & EVT_SCROLLLOCK)
+	    mods |= 0x10;
+	if (EVT.keyModifiers & EVT_NUMLOCK)
+	    mods |= 0x20;
+	if (EVT.keyModifiers & EVT_CAPSLOCK)
+	    mods |= 0x40;
+	PM_setByte(_EVT_biosPtr+0x17,mods);
+
+	/* Flag that we are no longer installed */
+	_EVT_installed = false;
+	}
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVTAPI EVT_exit(void)
+{
+    EVT_suspend();
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h
new file mode 100755
index 0000000..35e8e00
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h
@@ -0,0 +1,29 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit DOS
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c b/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c
new file mode 100755
index 0000000..2ad9e34
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c
@@ -0,0 +1,2243 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  16/32 bit DOS
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "ztimerc.h"
+#include "mtrr.h"
+#include "pm_help.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <dos.h>
+#include <conio.h>
+#ifdef  __GNUC__
+#include <unistd.h>
+#include <sys/nearptr.h>
+#include <sys/stat.h>
+#else
+#include <direct.h>
+#endif
+#ifdef  __BORLANDC__
+#pragma warn -par
+#endif
+
+/*--------------------------- Global variables ----------------------------*/
+
+typedef struct {
+    int     oldMode;
+    int     old50Lines;
+    } DOS_stateBuf;
+
+#define MAX_RM_BLOCKS   10
+
+static struct {
+    void    *p;
+    uint    tag;
+    } rmBlocks[MAX_RM_BLOCKS];
+
+static uint     VESABuf_len = 1024;     /* Length of the VESABuf buffer     */
+static void     *VESABuf_ptr = NULL;    /* Near pointer to VESABuf          */
+static uint     VESABuf_rseg;           /* Real mode segment of VESABuf     */
+static uint     VESABuf_roff;           /* Real mode offset of VESABuf      */
+static void     (PMAPIP fatalErrorCleanup)(void) = NULL;
+ushort _VARAPI  _PM_savedDS = 0;
+#ifdef  DOS4GW
+static ulong    PDB = 0,*pPDB = NULL;
+#endif
+#ifndef REALMODE
+static char     VXD_name[] = PMHELP_NAME;
+static char     VXD_module[] = PMHELP_MODULE;
+static char     VXD_DDBName[] = PMHELP_DDBNAME;
+static uint     VXD_version = -1;
+static uint     VXD_loadOff = 0;
+static uint     VXD_loadSel = 0;
+uint _VARAPI    _PM_VXD_off = 0;
+uint _VARAPI    _PM_VXD_sel = 0;
+int _VARAPI     _PM_haveCauseWay = -1;
+
+/* Memory mapping cache */
+
+#define MAX_MEMORY_MAPPINGS 100
+typedef struct {
+    ulong   physical;
+    ulong   linear;
+    ulong   limit;
+    } mmapping;
+static mmapping     maps[MAX_MEMORY_MAPPINGS] = {0};
+static int          numMaps = 0;
+
+/* Page sized block cache */
+
+#define PAGES_PER_BLOCK     100
+#define FREELIST_NEXT(p)    (*(void**)(p))
+typedef struct pageblock {
+    struct pageblock    *next;
+    struct pageblock    *prev;
+    void                *freeListStart;
+    void                *freeList;
+    void                *freeListEnd;
+    int                 freeCount;
+    } pageblock;
+static pageblock    *pageBlocks = NULL;
+#endif
+
+/* Start of all page tables in CauseWay */
+
+#define CW_PAGE_TABLE_START (1024UL*4096UL*1023UL)
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* External assembler functions */
+
+ulong   _ASMAPI _PM_getPDB(void);
+int     _ASMAPI _PM_pagingEnabled(void);
+void    _ASMAPI _PM_VxDCall(VXD_regs *regs,uint off,uint sel);
+
+#ifndef REALMODE
+/****************************************************************************
+REMARKS:
+Exit function to unload the dynamically loaded VxD
+****************************************************************************/
+static void UnloadVxD(void)
+{
+    PMSREGS     sregs;
+    VXD_regs    r;
+
+    r.eax = 2;
+    r.ebx = 0;
+    r.edx = (uint)VXD_module;
+    PM_segread(&sregs);
+#ifdef  __16BIT__
+    r.ds = ((ulong)VXD_module) >> 16;
+#else
+    r.ds = sregs.ds;
+#endif
+    r.es = sregs.es;
+    _PM_VxDCall(&r,VXD_loadOff,VXD_loadSel);
+}
+
+/****************************************************************************
+REMARKS:
+External function to call the PMHELP helper VxD.
+****************************************************************************/
+void PMAPI PM_VxDCall(
+    VXD_regs *regs)
+{
+    if (_PM_VXD_sel != 0 || _PM_VXD_off != 0)
+	_PM_VxDCall(regs,_PM_VXD_off,_PM_VXD_sel);
+}
+
+/****************************************************************************
+RETURNS:
+BCD coded version number of the VxD, or 0 if not loaded (ie: 0x202 - 2.2)
+
+REMARKS:
+This function gets the version number for the VxD that we have connected to.
+****************************************************************************/
+uint PMAPI PMHELP_getVersion(void)
+{
+    VXD_regs    r;
+
+    /* Call the helper VxD to determine the version number */
+    if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) {
+	memset(&r,0,sizeof(r));
+	r.eax = API_NUM(PMHELP_GETVER);
+	_PM_VxDCall(&r,_PM_VXD_off,_PM_VXD_sel);
+	return VXD_version = (uint)r.eax;
+	}
+    return VXD_version = 0;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Connects to the helper VxD and returns the version number
+
+RETURNS:
+True if the VxD was found and loaded, false otherwise.
+
+REMARKS:
+This function connects to the VxD (loading it if it is dynamically loadable)
+and returns the version number of the VxD.
+****************************************************************************/
+static ibool PMHELP_connect(void)
+{
+    PMREGS      regs;
+    PMSREGS     sregs;
+    VXD_regs    r;
+
+    /* Bail early if we have alread connected */
+    if (VXD_version != -1)
+	return VXD_version != 0;
+
+    /* Get the static SDDHELP.VXD entry point if available */
+    PM_segread(&sregs);
+    regs.x.ax = 0x1684;
+    regs.x.bx = SDDHELP_DeviceID;
+    regs.x.di = 0;
+    sregs.es = 0;
+    PM_int386x(0x2F,&regs,&regs,&sregs);
+    _PM_VXD_sel = sregs.es;
+    _PM_VXD_off = regs.x.di;
+    if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) {
+	if (PMHELP_getVersion() >= PMHELP_VERSION)
+	    return true;
+	}
+
+    /* If we get here, then either SDDHELP.VXD is not loaded, or it is an
+     * earlier version. In this case try to dynamically load the PMHELP.VXD
+     * helper VxD instead.
+     */
+    PM_segread(&sregs);
+    regs.x.ax = 0x1684;
+    regs.x.bx = VXDLDR_DeviceID;
+    regs.x.di = 0;
+    sregs.es = 0;
+    PM_int386x(0x2F,&regs,&regs,&sregs);
+    VXD_loadSel = sregs.es;
+    VXD_loadOff = regs.x.di;
+    if (VXD_loadSel == 0 && VXD_loadOff == 0)
+	return VXD_version = 0;
+    r.eax = 1;
+    r.ebx = 0;
+    r.edx = (uint)VXD_name;
+    PM_segread(&sregs);
+    r.ds = sregs.ds;
+    r.es = sregs.es;
+    _PM_VxDCall(&r,VXD_loadOff,VXD_loadSel);
+    if (r.eax != 0)
+	return VXD_version = 0;
+
+    /* Get the dynamic VxD entry point so we can call it */
+    atexit(UnloadVxD);
+    PM_segread(&sregs);
+    regs.x.ax = 0x1684;
+    regs.x.bx = 0;
+    regs.e.edi = (uint)VXD_DDBName;
+    PM_int386x(0x2F,&regs,&regs,&sregs);
+    _PM_VXD_sel = sregs.es;
+    _PM_VXD_off = regs.x.di;
+    if (_PM_VXD_sel == 0 && _PM_VXD_off == 0)
+	return VXD_version = 0;
+    if (PMHELP_getVersion() >= PMHELP_VERSION)
+	return true;
+    return VXD_version = 0;
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+Initialise the PM library. First we try to connect to a static SDDHELP.VXD
+helper VxD, and check that it is a version we can use. If not we try to
+dynamically load the PMHELP.VXD helper VxD
+****************************************************************************/
+void PMAPI PM_init(void)
+{
+#ifndef REALMODE
+    PMREGS  regs;
+
+    /* Check if we are running under CauseWay under real DOS */
+    if (_PM_haveCauseWay == -1) {
+	/* Check if we are running under DPMI in which case we will not be
+	 * able to use our special ring 0 CauseWay functions.
+	 */
+	_PM_haveCauseWay = false;
+	regs.x.ax = 0xFF00;
+	PM_int386(0x31,&regs,&regs);
+	if (regs.x.cflag || !(regs.e.edi & 8)) {
+	    /* We are not under DPMI, so now check if CauseWay is active */
+	    regs.x.ax = 0xFFF9;
+	    PM_int386(0x31,&regs,&regs);
+	    if (!regs.x.cflag && regs.e.ecx == 0x43415553 && regs.e.edx == 0x45574159)
+		_PM_haveCauseWay = true;
+	    }
+
+	/* Now connect to PMHELP.VXD and initialise MTRR module */
+	if (!PMHELP_connect())
+	    MTRR_init();
+	}
+#endif
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+RETURNS:
+Error code describing the result.
+
+REMARKS:
+Function to enable write combining for the specified region of memory.
+****************************************************************************/
+int PMAPI PM_enableWriteCombine(
+    ulong base,
+    ulong size,
+    uint type)
+{
+#ifndef REALMODE
+    VXD_regs    regs;
+
+    if (PMHELP_connect()) {
+	memset(&regs,0,sizeof(regs));
+	regs.eax = API_NUM(PMHELP_ENABLELFBCOMB);
+	regs.ebx = base;
+	regs.ecx = size;
+	regs.edx = type;
+	_PM_VxDCall(&regs,_PM_VXD_off,_PM_VXD_sel);
+	return regs.eax;
+	}
+    return MTRR_enableWriteCombine(base,size,type);
+#else
+    return PM_MTRR_NOT_SUPPORTED;
+#endif
+}
+
+ibool PMAPI PM_haveBIOSAccess(void)
+{ return true; }
+
+long PMAPI PM_getOSType(void)
+{ return _OS_DOS; }
+
+int PMAPI PM_getModeType(void)
+{
+#if defined(REALMODE)
+    return PM_realMode;
+#elif defined(PM286)
+    return PM_286;
+#elif defined(PM386)
+    return PM_386;
+#endif
+}
+
+void PMAPI PM_backslash(char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '\\') {
+	s[pos] = '\\';
+	s[pos+1] = '\0';
+	}
+}
+
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+void PMAPI PM_fatalError(const char *msg)
+{
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+    fprintf(stderr,"%s\n", msg);
+    exit(1);
+}
+
+static void ExitVBEBuf(void)
+{
+    if (VESABuf_ptr)
+	PM_freeRealSeg(VESABuf_ptr);
+    VESABuf_ptr = 0;
+}
+
+void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff)
+{
+    if (!VESABuf_ptr) {
+	/* Allocate a global buffer for communicating with the VESA VBE */
+	if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL)
+	    return NULL;
+	atexit(ExitVBEBuf);
+	}
+    *len = VESABuf_len;
+    *rseg = VESABuf_rseg;
+    *roff = VESABuf_roff;
+    return VESABuf_ptr;
+}
+
+int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return PM_int386x(intno,in,out,&sregs);
+}
+
+/* Routines to set and get the real mode interrupt vectors, by making
+ * direct real mode calls to DOS and bypassing the DOS extenders API.
+ * This is the safest way to handle this, as some servers try to be
+ * smart about changing real mode vectors.
+ */
+
+void PMAPI _PM_getRMvect(int intno, long *realisr)
+{
+    RMREGS  regs;
+    RMSREGS sregs;
+
+    PM_saveDS();
+    regs.h.ah = 0x35;
+    regs.h.al = intno;
+    PM_int86x(0x21, &regs, &regs, &sregs);
+    *realisr = ((long)sregs.es << 16) | regs.x.bx;
+}
+
+void PMAPI _PM_setRMvect(int intno, long realisr)
+{
+    RMREGS  regs;
+    RMSREGS sregs;
+
+    PM_saveDS();
+    regs.h.ah = 0x25;
+    regs.h.al = intno;
+    sregs.ds = (int)(realisr >> 16);
+    regs.x.dx = (int)(realisr & 0xFFFF);
+    PM_int86x(0x21, &regs, &regs, &sregs);
+}
+
+void PMAPI _PM_addRealModeBlock(void *mem,uint tag)
+{
+    int i;
+
+    for (i = 0; i < MAX_RM_BLOCKS; i++) {
+	if (rmBlocks[i].p == NULL) {
+	    rmBlocks[i].p = mem;
+	    rmBlocks[i].tag = tag;
+	    return;
+	    }
+	}
+    PM_fatalError("To many real mode memory block allocations!");
+}
+
+uint PMAPI _PM_findRealModeBlock(void *mem)
+{
+    int i;
+
+    for (i = 0; i < MAX_RM_BLOCKS; i++) {
+	if (rmBlocks[i].p == mem)
+	    return rmBlocks[i].tag;
+	}
+    PM_fatalError("Could not find prior real mode memory block allocation!");
+    return 0;
+}
+
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    return getcwd(path,maxLen);
+}
+
+char PMAPI PM_getBootDrive(void)
+{ return 'C'; }
+
+const char * PMAPI PM_getVBEAFPath(void)
+{ return "c:\\"; }
+
+const char * PMAPI PM_getNucleusPath(void)
+{
+    static char path[256];
+    char        *env;
+
+    if ((env = getenv("NUCLEUS_PATH")) != NULL)
+	return env;
+    if ((env = getenv("WINBOOTDIR")) != NULL) {
+	/* Running in a Windows 9x DOS box or DOS mode */
+	strcpy(path,env);
+	strcat(path,"\\system\\nucleus");
+	return path;
+	}
+    if ((env = getenv("SystemRoot")) != NULL) {
+	/* Running in an NT/2K DOS box */
+	strcpy(path,env);
+	strcat(path,"\\system32\\nucleus");
+	return path;
+	}
+    return "c:\\nucleus";
+}
+
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+const char * PMAPI PM_getUniqueID(void)
+{ return "DOS"; }
+
+const char * PMAPI PM_getMachineName(void)
+{ return "DOS"; }
+
+int PMAPI PM_kbhit(void)
+{
+    return kbhit();
+}
+
+int PMAPI PM_getch(void)
+{
+    return getch();
+}
+
+PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen)
+{
+    /* Not used for DOS */
+    (void)hwndUser;
+    (void)device;
+    (void)xRes;
+    (void)yRes;
+    (void)bpp;
+    (void)fullScreen;
+    return 0;
+}
+
+int PMAPI PM_getConsoleStateSize(void)
+{
+    return sizeof(DOS_stateBuf);
+}
+
+void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole)
+{
+    RMREGS          regs;
+    DOS_stateBuf    *sb = stateBuf;
+
+    /* Save the old video mode state */
+    regs.h.ah = 0x0F;
+    PM_int86(0x10,&regs,&regs);
+    sb->oldMode = regs.h.al & 0x7F;
+    sb->old50Lines = false;
+    if (sb->oldMode == 0x3) {
+	regs.x.ax = 0x1130;
+	regs.x.bx = 0;
+	regs.x.dx = 0;
+	PM_int86(0x10,&regs,&regs);
+	sb->old50Lines = (regs.h.dl == 42 || regs.h.dl == 49);
+	}
+    (void)hwndConsole;
+}
+
+void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags))
+{
+    /* Not used for DOS */
+    (void)saveState;
+}
+
+void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole)
+{
+    RMREGS              regs;
+    const DOS_stateBuf  *sb = stateBuf;
+
+    /* Retore 50 line mode if set */
+    if (sb->old50Lines) {
+	regs.x.ax = 0x1112;
+	regs.x.bx = 0;
+	PM_int86(0x10,&regs,&regs);
+	}
+    (void)hwndConsole;
+}
+
+void PMAPI PM_closeConsole(PM_HWND hwndConsole)
+{
+    /* Not used for DOS */
+    (void)hwndConsole;
+}
+
+void PMAPI PM_setOSCursorLocation(int x,int y)
+{
+    uchar *_biosPtr = PM_getBIOSPointer();
+    PM_setByte(_biosPtr+0x50,x);
+    PM_setByte(_biosPtr+0x51,y);
+}
+
+void PMAPI PM_setOSScreenWidth(int width,int height)
+{
+    uchar *_biosPtr = PM_getBIOSPointer();
+    PM_setWord(_biosPtr+0x4A,width);
+    PM_setWord(_biosPtr+0x4C,width*2);
+    PM_setByte(_biosPtr+0x84,height-1);
+    if (height > 25) {
+	PM_setWord(_biosPtr+0x60,0x0607);
+	PM_setByte(_biosPtr+0x85,0x08);
+	}
+    else {
+	PM_setWord(_biosPtr+0x60,0x0D0E);
+	PM_setByte(_biosPtr+0x85,0x016);
+	}
+}
+
+void * PMAPI PM_mallocShared(long size)
+{
+    return PM_malloc(size);
+}
+
+void PMAPI PM_freeShared(void *ptr)
+{
+    PM_free(ptr);
+}
+
+#define GetRMVect(intno,isr)    *(isr) = ((ulong*)rmZeroPtr)[intno]
+#define SetRMVect(intno,isr)    ((ulong*)rmZeroPtr)[intno] = (isr)
+
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS,
+    ulong BIOSLen)
+{
+    static int      firstTime = true;
+    static uchar    *rmZeroPtr;
+    long            Current10,Current6D,Current42;
+    RMREGS          regs;
+    RMSREGS         sregs;
+
+    /* Create a zero memory mapping for us to use */
+    if (firstTime) {
+	rmZeroPtr = PM_mapPhysicalAddr(0,0x7FFF,true);
+	firstTime = false;
+	}
+
+    /* Remap the secondary BIOS to 0xC0000 physical */
+    if (BIOSPhysAddr != 0xC0000L || BIOSLen > 32768) {
+	/* DOS cannot virtually remap the BIOS, so we can only work if all
+	 * the secondary controllers are identical, and we then use the
+	 * BIOS on the first controller for all the remaining controllers.
+	 *
+	 * For OS'es that do virtual memory, and remapping of 0xC0000
+	 * physical (perhaps a copy on write mapping) should be all that
+	 * is needed.
+	 */
+	return false;
+	}
+
+    /* Save current handlers of int 10h and 6Dh */
+    GetRMVect(0x10,&Current10);
+    GetRMVect(0x6D,&Current6D);
+
+    /* POST the secondary BIOS */
+    GetRMVect(0x42,&Current42);
+    SetRMVect(0x10,Current42);  /* Restore int 10h to STD-BIOS */
+    regs.x.ax = axVal;
+    PM_callRealMode(0xC000,0x0003,&regs,&sregs);
+
+    /* Restore current handlers */
+    SetRMVect(0x10,Current10);
+    SetRMVect(0x6D,Current6D);
+
+    /* Second the primary BIOS mappin 1:1 for 0xC0000 physical */
+    if (BIOSPhysAddr != 0xC0000L) {
+	/* DOS does not support this */
+	(void)mappedBIOS;
+	}
+    return true;
+}
+
+void PMAPI PM_sleep(ulong milliseconds)
+{
+    ulong           microseconds = milliseconds * 1000L;
+    LZTimerObject   tm;
+
+    LZTimerOnExt(&tm);
+    while (LZTimerLapExt(&tm) < microseconds)
+	;
+    LZTimerOffExt(&tm);
+}
+
+int PMAPI PM_getCOMPort(int port)
+{
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	}
+    return 0;
+}
+
+int PMAPI PM_getLPTPort(int port)
+{
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    (void)szDLLName;
+    return NULL;
+}
+
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    (void)hModule;
+}
+
+int PMAPI PM_setIOPL(
+    int level)
+{
+    return level;
+}
+
+/****************************************************************************
+REMARKS:
+Internal function to convert the find data to the generic interface.
+****************************************************************************/
+static void convertFindData(
+    PM_findData *findData,
+    struct find_t *blk)
+{
+    ulong   dwSize = findData->dwSize;
+
+    memset(findData,0,findData->dwSize);
+    findData->dwSize = dwSize;
+    if (blk->attrib & _A_RDONLY)
+	findData->attrib |= PM_FILE_READONLY;
+    if (blk->attrib & _A_SUBDIR)
+	findData->attrib |= PM_FILE_DIRECTORY;
+    if (blk->attrib & _A_ARCH)
+	findData->attrib |= PM_FILE_ARCHIVE;
+    if (blk->attrib & _A_HIDDEN)
+	findData->attrib |= PM_FILE_HIDDEN;
+    if (blk->attrib & _A_SYSTEM)
+	findData->attrib |= PM_FILE_SYSTEM;
+    findData->sizeLo = blk->size;
+    strncpy(findData->name,blk->name,PM_MAX_PATH);
+    findData->name[PM_MAX_PATH-1] = 0;
+}
+
+#define FIND_MASK   (_A_RDONLY | _A_ARCH | _A_SUBDIR | _A_HIDDEN | _A_SYSTEM)
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+void * PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    struct find_t *blk;
+
+    if ((blk = PM_malloc(sizeof(*blk))) == NULL)
+	return PM_FILE_INVALID;
+    if (_dos_findfirst((char*)filename,FIND_MASK,blk) == 0) {
+	convertFindData(findData,blk);
+	return blk;
+	}
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    void *handle,
+    PM_findData *findData)
+{
+    struct find_t *blk = handle;
+
+    if (_dos_findnext(blk) == 0) {
+	convertFindData(findData,blk);
+	return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    void *handle)
+{
+    PM_free(handle);
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    RMREGS  regs;
+    regs.h.dl = (uchar)(drive - 'A' + 1);
+    regs.h.ah = 0x36;               /* Get disk information service */
+    PM_int86(0x21,&regs,&regs);
+    return regs.x.ax != 0xFFFF;     /* AX = 0xFFFF if disk is invalid */
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    uint oldDrive,maxDrives;
+    _dos_getdrive(&oldDrive);
+    _dos_setdrive(drive,&maxDrives);
+    getcwd(dir,len);
+    _dos_setdrive(oldDrive,&maxDrives);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+#if defined(TNT) && defined(_MSC_VER)
+    DWORD attr = 0;
+
+    if (attrib & PM_FILE_READONLY)
+	attr |= FILE_ATTRIBUTE_READONLY;
+    if (attrib & PM_FILE_ARCHIVE)
+	attr |= FILE_ATTRIBUTE_ARCHIVE;
+    if (attrib & PM_FILE_HIDDEN)
+	attr |= FILE_ATTRIBUTE_HIDDEN;
+    if (attrib & PM_FILE_SYSTEM)
+	attr |= FILE_ATTRIBUTE_SYSTEM;
+    SetFileAttributes((LPSTR)filename, attr);
+#else
+    uint attr = 0;
+
+    if (attrib & PM_FILE_READONLY)
+	attr |= _A_RDONLY;
+    if (attrib & PM_FILE_ARCHIVE)
+	attr |= _A_ARCH;
+    if (attrib & PM_FILE_HIDDEN)
+	attr |= _A_HIDDEN;
+    if (attrib & PM_FILE_SYSTEM)
+	attr |= _A_SYSTEM;
+    _dos_setfileattr(filename,attr);
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+#ifdef  __GNUC__
+    return mkdir(filename,S_IRUSR) == 0;
+#else
+    return mkdir(filename) == 0;
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+    return rmdir(filename) == 0;
+}
+
+/*-------------------------------------------------------------------------*/
+/* Generic DPMI routines common to 16/32 bit code                          */
+/*-------------------------------------------------------------------------*/
+
+#ifndef REALMODE
+ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit)
+{
+    PMREGS  r;
+    int     i;
+    ulong   baseAddr,baseOfs,roundedLimit;
+
+    /* We can't map memory below 1Mb, but the linear address are already
+     * mapped 1:1 for this memory anyway so we just return the base address.
+     */
+    if (physAddr < 0x100000L)
+	return physAddr;
+
+    /* Search table of existing mappings to see if we have already mapped
+     * a region of memory that will serve this purpose. We do this because
+     * DPMI 0.9 does not allow us to free physical memory mappings, and if
+     * the mappings get re-used in the program we want to avoid allocating
+     * more mappings than necessary.
+     */
+    for (i = 0; i < numMaps; i++) {
+	if (maps[i].physical == physAddr && maps[i].limit == limit)
+	    return maps[i].linear;
+	}
+
+    /* Find a free slot in our physical memory mapping table */
+    for (i = 0; i < numMaps; i++) {
+	if (maps[i].limit == 0)
+	    break;
+	}
+    if (i == numMaps) {
+	i = numMaps++;
+	if (i == MAX_MEMORY_MAPPINGS)
+	    return NULL;
+	}
+
+    /* Round the physical address to a 4Kb boundary and the limit to a
+     * 4Kb-1 boundary before passing the values to DPMI as some extenders
+     * will fail the calls unless this is the case. If we round the
+     * physical address, then we also add an extra offset into the address
+     * that we return.
+     */
+    baseOfs = physAddr & 4095;
+    baseAddr = physAddr & ~4095;
+    roundedLimit = ((limit+baseOfs+1+4095) & ~4095)-1;
+    r.x.ax = 0x800;
+    r.x.bx = baseAddr >> 16;
+    r.x.cx = baseAddr & 0xFFFF;
+    r.x.si = roundedLimit >> 16;
+    r.x.di = roundedLimit & 0xFFFF;
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag)
+	return 0xFFFFFFFFUL;
+    maps[i].physical = physAddr;
+    maps[i].limit = limit;
+    maps[i].linear = ((ulong)r.x.bx << 16) + r.x.cx + baseOfs;
+    return maps[i].linear;
+}
+
+int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr)
+{
+    PMREGS  r;
+
+    r.x.ax = 7;                     /* DPMI set selector base address   */
+    r.x.bx = sel;
+    r.x.cx = linAddr >> 16;
+    r.x.dx = linAddr & 0xFFFF;
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag)
+	return 0;
+    return 1;
+}
+
+ulong PMAPI DPMI_getSelectorBase(ushort sel)
+{
+    PMREGS  r;
+
+    r.x.ax = 6;                     /* DPMI get selector base address   */
+    r.x.bx = sel;
+    PM_int386(0x31, &r, &r);
+    return ((ulong)r.x.cx << 16) + r.x.dx;
+}
+
+int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit)
+{
+    PMREGS  r;
+
+    r.x.ax = 8;                     /* DPMI set selector limit          */
+    r.x.bx = sel;
+    r.x.cx = limit >> 16;
+    r.x.dx = limit & 0xFFFF;
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag)
+	return 0;
+    return 1;
+}
+
+uint PMAPI DPMI_createSelector(ulong base,ulong limit)
+{
+    uint    sel;
+    PMREGS  r;
+
+    /* Allocate 1 descriptor */
+    r.x.ax = 0;
+    r.x.cx = 1;
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag) return 0;
+    sel = r.x.ax;
+
+    /* Set the descriptor access rights (for a 32 bit page granular
+     * segment).
+     */
+    if (limit >= 0x10000L) {
+	r.x.ax = 9;
+	r.x.bx = sel;
+	r.x.cx = 0x40F3;
+	PM_int386(0x31, &r, &r);
+	}
+
+    /* Map physical memory and create selector */
+    if ((base = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFFUL)
+	return 0;
+    if (!DPMI_setSelectorBase(sel,base))
+	return 0;
+    if (!DPMI_setSelectorLimit(sel,limit))
+	return 0;
+    return sel;
+}
+
+void PMAPI DPMI_freeSelector(uint sel)
+{
+    PMREGS  r;
+
+    r.x.ax = 1;
+    r.x.bx = sel;
+    PM_int386(0x31, &r, &r);
+}
+
+int PMAPI DPMI_lockLinearPages(ulong linear,ulong len)
+{
+    PMREGS  r;
+
+    r.x.ax = 0x600;                     /* DPMI Lock Linear Region      */
+    r.x.bx = (linear >> 16);            /* Linear address in BX:CX      */
+    r.x.cx = (linear & 0xFFFF);
+    r.x.si = (len >> 16);               /* Length in SI:DI              */
+    r.x.di = (len & 0xFFFF);
+    PM_int386(0x31, &r, &r);
+    return (!r.x.cflag);
+}
+
+int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len)
+{
+    PMREGS  r;
+
+    r.x.ax = 0x601;                     /* DPMI Unlock Linear Region    */
+    r.x.bx = (linear >> 16);            /* Linear address in BX:CX      */
+    r.x.cx = (linear & 0xFFFF);
+    r.x.si = (len >> 16);               /* Length in SI:DI              */
+    r.x.di = (len & 0xFFFF);
+    PM_int386(0x31, &r, &r);
+    return (!r.x.cflag);
+}
+
+/****************************************************************************
+REMARKS:
+Adjust the page table caching bits directly. Requires ring 0 access and
+only works with DOS4GW and compatible extenders (CauseWay also works since
+it has direct support for the ring 0 instructions we need from ring 3). Will
+not work in a DOS box, but we call into the ring 0 helper VxD so we should
+never get here in a DOS box anyway (assuming the VxD is present). If we
+do get here and we are in windows, this code will be skipped.
+****************************************************************************/
+static void PM_adjustPageTables(
+    ulong linear,
+    ulong limit,
+    ibool isCached)
+{
+#ifdef  DOS4GW
+    int     startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage;
+    ulong   andMask,orMask,pageTable,*pPageTable;
+
+    andMask = ~0x18;
+    orMask = (isCached) ? 0x00 : 0x18;
+    if (_PM_pagingEnabled() == 1 && (PDB = _PM_getPDB()) != 0) {
+	if (_PM_haveCauseWay) {
+	    /* CauseWay is a little different in the page table handling.
+	     * The code that we use for DOS4G/W does not appear to work
+	     * with CauseWay correctly as it does not appear to allow us
+	     * to map the page tables directly. Instead we can directly
+	     * access the page table entries in extended memory where
+	     * CauseWay always locates them (starting at 1024*4096*1023)
+	     */
+	    startPage = (linear >> 12);
+	    endPage = ((linear+limit) >> 12);
+	    pPageTable = (ulong*)CW_PAGE_TABLE_START;
+	    for (iPage = startPage; iPage <= endPage; iPage++)
+		pPageTable[iPage] = (pPageTable[iPage] & andMask) | orMask;
+	    }
+	else {
+	    pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF);
+	    if (pPDB) {
+		startPDB = (linear >> 22) & 0x3FF;
+		startPage = (linear >> 12) & 0x3FF;
+		endPDB = ((linear+limit) >> 22) & 0x3FF;
+		endPage = ((linear+limit) >> 12) & 0x3FF;
+		for (iPDB = startPDB; iPDB <= endPDB; iPDB++) {
+		    pageTable = pPDB[iPDB] & ~0xFFF;
+		    pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF);
+		    start = (iPDB == startPDB) ? startPage : 0;
+		    end = (iPDB == endPDB) ? endPage : 0x3FF;
+		    for (iPage = start; iPage <= end; iPage++)
+			pPageTable[iPage] = (pPageTable[iPage] & andMask) | orMask;
+		    }
+		}
+	    }
+	PM_flushTLB();
+	}
+#endif
+}
+
+void * PMAPI DPMI_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{
+    PMSREGS     sregs;
+    ulong       linAddr;
+    ulong       DSBaseAddr;
+
+    /* Get the base address for the default DS selector */
+    PM_segread(&sregs);
+    DSBaseAddr = DPMI_getSelectorBase(sregs.ds);
+    if ((base < 0x100000) && (DSBaseAddr == 0)) {
+	/* DS is zero based, so we can directly access the first 1Mb of
+	 * system memory (like under DOS4GW).
+	 */
+	return (void*)base;
+	}
+
+    /* Map the memory to a linear address using DPMI function 0x800 */
+    if ((linAddr = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFF) {
+	if (base >= 0x100000)
+	    return NULL;
+	/* If the linear address mapping fails but we are trying to
+	 * map an area in the first 1Mb of system memory, then we must
+	 * be running under a Windows or OS/2 DOS box. Under these
+	 * environments we can use the segment wrap around as a fallback
+	 * measure, as this does work properly.
+	 */
+	linAddr = base;
+	}
+
+    /* Now expand the default DS selector to 4Gb so we can access it */
+    if (!DPMI_setSelectorLimit(sregs.ds,0xFFFFFFFFUL))
+	return NULL;
+
+    /* Finally enable caching for the page tables that we just mapped in,
+     * since DOS4GW and PMODE/W create the page table entries without
+     * caching enabled which hurts the performance of the linear framebuffer
+     * as it disables write combining on Pentium Pro and above processors.
+     *
+     * For those processors cache disabling is better handled through the
+     * MTRR registers anyway (we can write combine a region but disable
+     * caching) so that MMIO register regions do not screw up.
+     */
+    if (DSBaseAddr == 0)
+	PM_adjustPageTables(linAddr,limit,isCached);
+
+    /* Now return the base address of the memory into the default DS */
+    return (void*)(linAddr - DSBaseAddr);
+}
+
+#if defined(PM386)
+
+/* Some DOS extender implementations do not directly support calling a
+ * real mode procedure from protected mode. However we can simulate what
+ * we need temporarily hooking the INT 6Ah vector with a small real mode
+ * stub that will call our real mode code for us.
+ */
+
+static uchar int6AHandler[] = {
+    0x00,0x00,0x00,0x00,        /*  __PMODE_callReal variable           */
+    0xFB,                       /*  sti                                 */
+    0x2E,0xFF,0x1E,0x00,0x00,   /*  call    [cs:__PMODE_callReal]       */
+    0xCF,                       /*  iretf                               */
+    };
+static uchar *crPtr = NULL; /* Pointer to of int 6A handler         */
+static uint crRSeg,crROff;  /* Real mode seg:offset of handler      */
+
+void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in,
+    RMSREGS *sregs)
+{
+    uchar   *p;
+    uint    oldSeg,oldOff;
+
+    if (!crPtr) {
+	/* Allocate and copy the memory block only once */
+	crPtr = PM_allocRealSeg(sizeof(int6AHandler), &crRSeg, &crROff);
+	memcpy(crPtr,int6AHandler,sizeof(int6AHandler));
+	}
+    PM_setWord(crPtr,off);              /* Plug in address to call  */
+    PM_setWord(crPtr+2,seg);
+    p = PM_mapRealPointer(0,0x6A * 4);
+    oldOff = PM_getWord(p);             /* Save old handler address */
+    oldSeg = PM_getWord(p+2);
+    PM_setWord(p,crROff+4);             /* Hook 6A handler          */
+    PM_setWord(p+2,crRSeg);
+    PM_int86x(0x6A, in, in, sregs);     /* Call real mode code      */
+    PM_setWord(p,oldOff);               /* Restore old handler      */
+    PM_setWord(p+2,oldSeg);
+}
+
+#endif  /* PM386 */
+
+#endif  /* !REALMODE */
+
+/****************************************************************************
+REMARKS:
+Allocates a block of locked, physically contiguous memory. The memory
+may be required to be below the 16Meg boundary.
+****************************************************************************/
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16Meg)
+{
+    uchar           *p,*roundedP;
+    uint            r_seg,r_off;
+    uint            roundedSize = (size + 4 + 0xFFF) & ~0xFFF;
+    PM_lockHandle   lh; /* Unused in DOS */
+#ifndef REALMODE
+    VXD_regs        regs;
+
+    /* If we have connected to our helper VxD in a Windows DOS box, use the
+     * helper VxD services to allocate the memory that we need.
+     */
+    if (VXD_version) {
+	memset(&regs,0,sizeof(regs));
+	regs.eax = API_NUM(PMHELP_ALLOCLOCKED);
+	regs.ebx = size;
+	regs.ecx = (ulong)physAddr;
+	regs.edx = contiguous | (below16Meg << 8);
+	_PM_VxDCall(&regs,_PM_VXD_off,_PM_VXD_sel);
+	return (void*)regs.eax;
+	}
+
+    /* If the memory is not contiguous, we simply need to allocate it
+     * using regular memory allocation services, and lock it down
+     * in memory.
+     *
+     * For contiguous memory blocks, the only way to guarantee contiguous physical
+     * memory addresses under DOS is to allocate the memory below the
+     * 1Meg boundary as real mode memory.
+     *
+     * Note that we must page align the memory block, and we also must
+     * keep track of the non-aligned pointer so we can properly free
+     * it later. Hence we actually allocate 4 bytes more than the
+     * size rounded up to the next 4K boundary.
+     */
+    if (!contiguous)
+	p = PM_malloc(roundedSize);
+    else
+#endif
+	p = PM_allocRealSeg(roundedSize,&r_seg,&r_off);
+    if (p == NULL)
+	return NULL;
+    roundedP = (void*)(((ulong)p + 0xFFF) & ~0xFFF);
+    *((ulong*)(roundedP + size)) = (ulong)p;
+    PM_lockDataPages(roundedP,size,&lh);
+    if ((*physAddr = PM_getPhysicalAddr(roundedP)) == 0xFFFFFFFF) {
+	PM_freeLockedMem(roundedP,size,contiguous);
+	return NULL;
+	}
+
+    /* Disable caching for the memory since it is probably a DMA buffer */
+#ifndef REALMODE
+    PM_adjustPageTables((ulong)roundedP,size-1,false);
+#endif
+    return roundedP;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of locked memory.
+****************************************************************************/
+void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous)
+{
+#ifndef REALMODE
+    VXD_regs        regs;
+    PM_lockHandle   lh; /* Unused in DOS */
+
+    if (!p)
+	return;
+    if (VXD_version) {
+	memset(&regs,0,sizeof(regs));
+	regs.eax = API_NUM(PMHELP_FREELOCKED);
+	regs.ebx = (ulong)p;
+	regs.ecx = size;
+	regs.edx = contiguous;
+	_PM_VxDCall(&regs,_PM_VXD_off,_PM_VXD_sel);
+	return;
+	}
+    PM_unlockDataPages(p,size,&lh);
+    if (!contiguous)
+	free(*((void**)((uchar*)p + size)));
+    else
+#endif
+	PM_freeRealSeg(*((void**)((char*)p + size)));
+}
+
+#ifndef REALMODE
+/****************************************************************************
+REMARKS:
+Allocates a new block of pages for the page block manager.
+****************************************************************************/
+static pageblock *PM_addNewPageBlock(void)
+{
+    int         i,size;
+    pageblock   *newBlock;
+    char        *p,*next;
+
+    /* Allocate memory for the new page block, and add to head of list */
+    size = PAGES_PER_BLOCK * PM_PAGE_SIZE + (PM_PAGE_SIZE-1) + sizeof(pageblock);
+    if ((newBlock = PM_malloc(size)) == NULL)
+	return NULL;
+    newBlock->prev = NULL;
+    newBlock->next = pageBlocks;
+    if (pageBlocks)
+	pageBlocks->prev = newBlock;
+    pageBlocks = newBlock;
+
+    /* Initialise the page aligned free list for the page block */
+    newBlock->freeCount = PAGES_PER_BLOCK;
+    newBlock->freeList = p = (char*)(((ulong)(newBlock + 1) + (PM_PAGE_SIZE-1)) & ~(PM_PAGE_SIZE-1));
+    newBlock->freeListStart = newBlock->freeList;
+    newBlock->freeListEnd = p + (PAGES_PER_BLOCK-1) * PM_PAGE_SIZE;
+    for (i = 0; i < PAGES_PER_BLOCK; i++,p = next)
+	FREELIST_NEXT(p) = next = p + PM_PAGE_SIZE;
+    FREELIST_NEXT(p - PM_PAGE_SIZE) = NULL;
+    return newBlock;
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+Allocates a page aligned and page sized block of memory
+****************************************************************************/
+void * PMAPI PM_allocPage(
+    ibool locked)
+{
+#ifndef REALMODE
+    VXD_regs        regs;
+    pageblock       *block;
+    void            *p;
+    PM_lockHandle   lh; /* Unused in DOS */
+
+    /* Call the helper VxD for this service if we are running in a DOS box */
+    if (VXD_version) {
+	memset(&regs,0,sizeof(regs));
+	regs.eax = API_NUM(PMHELP_ALLOCPAGE);
+	regs.ebx = locked;
+	_PM_VxDCall(&regs,_PM_VXD_off,_PM_VXD_sel);
+	return (void*)regs.eax;
+	}
+
+    /* Scan the block list looking for any free blocks. Allocate a new
+     * page block if no free blocks are found.
+     */
+    for (block = pageBlocks; block != NULL; block = block->next) {
+	if (block->freeCount)
+	    break;
+	}
+    if (block == NULL && (block = PM_addNewPageBlock()) == NULL)
+	return NULL;
+    block->freeCount--;
+    p = block->freeList;
+    block->freeList = FREELIST_NEXT(p);
+    if (locked)
+	PM_lockDataPages(p,PM_PAGE_SIZE,&lh);
+    return p;
+#else
+    return NULL;
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Free a page aligned and page sized block of memory
+****************************************************************************/
+void PMAPI PM_freePage(
+    void *p)
+{
+#ifndef REALMODE
+    VXD_regs    regs;
+    pageblock   *block;
+
+    /* Call the helper VxD for this service if we are running in a DOS box */
+    if (VXD_version) {
+	memset(&regs,0,sizeof(regs));
+	regs.eax = API_NUM(PMHELP_FREEPAGE);
+	regs.ebx = (ulong)p;
+	_PM_VxDCall(&regs,_PM_VXD_off,_PM_VXD_sel);
+	return;
+	}
+
+    /* First find the page block that this page belongs to */
+    for (block = pageBlocks; block != NULL; block = block->next) {
+	if (p >= block->freeListStart && p <= block->freeListEnd)
+	    break;
+	}
+    CHECK(block != NULL);
+
+    /* Now free the block by adding it to the free list */
+    FREELIST_NEXT(p) = block->freeList;
+    block->freeList = p;
+    if (++block->freeCount == PAGES_PER_BLOCK) {
+	/* If all pages in the page block are now free, free the entire
+	 * page block itself.
+	 */
+	if (block == pageBlocks) {
+	    /* Delete from head */
+	    pageBlocks = block->next;
+	    if (block->next)
+		block->next->prev = NULL;
+	    }
+	else {
+	    /* Delete from middle of list */
+	    CHECK(block->prev != NULL);
+	    block->prev->next = block->next;
+	    if (block->next)
+		block->next->prev = block->prev;
+	    }
+	PM_free(block);
+	}
+#else
+    (void)p;
+#endif
+}
+
+/*-------------------------------------------------------------------------*/
+/* DOS Real Mode support.                                                  */
+/*-------------------------------------------------------------------------*/
+
+#ifdef REALMODE
+
+#ifndef MK_FP
+#define MK_FP(s,o)  ( (void far *)( ((ulong)(s) << 16) + \
+		    (ulong)(o) ))
+#endif
+
+void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off)
+{ return MK_FP(r_seg,r_off); }
+
+void * PMAPI PM_getBIOSPointer(void)
+{
+    return MK_FP(0x40,0);
+}
+
+void * PMAPI PM_getA0000Pointer(void)
+{
+    return MK_FP(0xA000,0);
+}
+
+void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{
+    uint sel = base >> 4;
+    uint off = base & 0xF;
+    limit = limit;
+    return MK_FP(sel,off);
+}
+
+void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit)
+{ ptr = ptr; }
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{
+    return ((((ulong)p >> 16) << 4) + (ushort)p);
+}
+
+ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress)
+{ return false; }
+
+void * PMAPI PM_mapToProcess(void *base,ulong limit)
+{ return (void*)base; }
+
+void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off)
+{
+    /* Call malloc() to allocate the memory for us */
+    void *p = PM_malloc(size);
+    *r_seg = FP_SEG(p);
+    *r_off = FP_OFF(p);
+    return p;
+}
+
+void PMAPI PM_freeRealSeg(void *mem)
+{
+    if (mem) PM_free(mem);
+}
+
+int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out)
+{
+    return PM_int386(intno,in,out);
+}
+
+int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,
+    RMSREGS *sregs)
+{
+    return PM_int386x(intno,in,out,sregs);
+}
+
+void PMAPI PM_availableMemory(ulong *physical,ulong *total)
+{
+    PMREGS regs;
+
+    regs.h.ah = 0x48;
+    regs.x.bx = 0xFFFF;
+    PM_int86(0x21,&regs,&regs);
+    *physical = *total = regs.x.bx * 16UL;
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* Phar Lap TNT DOS Extender support.                                      */
+/*-------------------------------------------------------------------------*/
+
+#ifdef TNT
+
+#include <pldos32.h>
+#include <pharlap.h>
+#include <hw386.h>
+
+static uchar *zeroPtr = NULL;
+
+void * PMAPI PM_getBIOSPointer(void)
+{
+    if (!zeroPtr)
+	zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true);
+    return (void*)(zeroPtr + 0x400);
+}
+
+void * PMAPI PM_getA0000Pointer(void)
+{
+    static void *bankPtr;
+    if (!bankPtr)
+	bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true);
+    return bankPtr;
+}
+
+void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{
+    CONFIG_INF  config;
+    ULONG       offset;
+    int         err;
+    ulong       baseAddr,baseOfs,newLimit;
+    VXD_regs    regs;
+
+    /* If we have connected to our helper VxD in a Windows DOS box, use
+     * the helper VxD services to map memory instead of the DPMI services.
+     * We do this because the helper VxD can properly disable caching
+     * where necessary, which we can only do directly here if we are
+     * running at ring 0 (ie: under real DOS).
+     */
+    if (VXD_version == -1)
+	PM_init();
+    if (VXD_version) {
+	memset(&regs,0,sizeof(regs));
+	regs.eax = API_NUM(PMHELP_MAPPHYS);
+	regs.ebx = base;
+	regs.ecx = limit;
+	regs.edx = isCached;
+	_PM_VxDCall(&regs,_PM_VXD_off,_PM_VXD_sel);
+	return (void*)regs.eax;
+	}
+
+    /* Round the physical address to a 4Kb boundary and the limit to a
+     * 4Kb-1 boundary before passing the values to TNT. If we round the
+     * physical address, then we also add an extra offset into the address
+     * that we return.
+     */
+    baseOfs = base & 4095;
+    baseAddr = base & ~4095;
+    newLimit = ((limit+baseOfs+1+4095) & ~4095)-1;
+    _dx_config_inf(&config, (UCHAR*)&config);
+    err = _dx_map_phys(config.c_ds_sel,baseAddr,(newLimit + 4095) / 4096,&offset);
+    if (err == 130) {
+	/* If the TNT function failed, we are running in a DPMI environment
+	 * and this function does not work. However we know how to handle
+	 * DPMI properly, so we use our generic DPMI functions to do
+	 * what the TNT runtime libraries can't.
+	 */
+	return DPMI_mapPhysicalAddr(base,limit,isCached);
+	}
+    if (err == 0)
+	return (void*)(offset + baseOfs);
+    return NULL;
+}
+
+void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit)
+{
+}
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{ return 0xFFFFFFFFUL; }
+
+ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress)
+{ return false; }
+
+void * PMAPI PM_mapToProcess(void *base,ulong limit)
+{ return (void*)base; }
+
+void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off)
+{
+    if (!zeroPtr)
+	zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF);
+    return (void*)(zeroPtr + MK_PHYS(r_seg,r_off));
+}
+
+void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off)
+{
+    USHORT  addr,t;
+    void    *p;
+
+    if (_dx_real_alloc((size + 0xF) >> 4,&addr,&t) != 0)
+	return 0;
+    *r_seg = addr;                  /* Real mode segment address    */
+    *r_off = 0;                     /* Real mode segment offset     */
+    p = PM_mapRealPointer(*r_seg,*r_off);
+    _PM_addRealModeBlock(p,addr);
+    return p;
+}
+
+void PMAPI PM_freeRealSeg(void *mem)
+{
+    if (mem) _dx_real_free(_PM_findRealModeBlock(mem));
+}
+
+#define INDPMI(reg)     rmregs.reg = regs->reg
+#define OUTDPMI(reg)    regs->reg = rmregs.reg
+
+void PMAPI DPMI_int86(int intno, DPMI_regs *regs)
+{
+    SWI_REGS    rmregs;
+
+    memset(&rmregs, 0, sizeof(rmregs));
+    INDPMI(eax); INDPMI(ebx); INDPMI(ecx); INDPMI(edx); INDPMI(esi); INDPMI(edi);
+
+    _dx_real_int(intno,&rmregs);
+
+    OUTDPMI(eax); OUTDPMI(ebx); OUTDPMI(ecx); OUTDPMI(edx); OUTDPMI(esi); OUTDPMI(edi);
+    regs->flags = rmregs.flags;
+}
+
+#define IN(reg)     rmregs.reg = in->e.reg
+#define OUT(reg)    out->e.reg = rmregs.reg
+
+int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out)
+{
+    SWI_REGS    rmregs;
+
+    memset(&rmregs, 0, sizeof(rmregs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+
+    _dx_real_int(intno,&rmregs);
+
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+    out->x.cflag = rmregs.flags & 0x1;
+    return out->x.ax;
+}
+
+int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,
+    RMSREGS *sregs)
+{
+    SWI_REGS    rmregs;
+
+    memset(&rmregs, 0, sizeof(rmregs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+    rmregs.es = sregs->es;
+    rmregs.ds = sregs->ds;
+
+    _dx_real_int(intno,&rmregs);
+
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+    sregs->es = rmregs.es;
+    sregs->cs = rmregs.cs;
+    sregs->ss = rmregs.ss;
+    sregs->ds = rmregs.ds;
+    out->x.cflag = rmregs.flags & 0x1;
+    return out->x.ax;
+}
+
+void PMAPI PM_availableMemory(ulong *physical,ulong *total)
+{
+    PMREGS  r;
+    uint    data[25];
+
+    r.x.ax = 0x2520;                /* Get free memory info */
+    r.x.bx = 0;
+    r.e.edx = (uint)data;
+    PM_int386(0x21, &r, &r);
+    *physical = data[21] * 4096;
+    *total = data[23] * 4096;
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* Symantec C++ DOSX and FlashTek X-32/X-32VM support                      */
+/*-------------------------------------------------------------------------*/
+
+#if defined(DOSX) || defined(X32VM)
+
+#ifdef  X32VM
+#include <x32.h>
+
+#define _x386_mk_protected_ptr(p)   _x32_mk_protected_ptr((void*)p)
+#define _x386_free_protected_ptr(p) _x32_free_protected_ptr(p)
+#define _x386_zero_base_ptr         _x32_zero_base_ptr
+#else
+extern void *_x386_zero_base_ptr;
+#endif
+
+void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off)
+{
+    return (void*)((ulong)_x386_zero_base_ptr + MK_PHYS(r_seg,r_off));
+}
+
+void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off)
+{
+    PMREGS  r;
+
+    r.h.ah = 0x48;                  /* DOS function 48h - allocate mem  */
+    r.x.bx = (size + 0xF) >> 4;     /* Number of paragraphs to allocate */
+    PM_int386(0x21, &r, &r);        /* Call DOS extender                */
+    if (r.x.cflag)
+	return 0;                   /* Could not allocate the memory    */
+    *r_seg = r.e.eax;
+    *r_off = 0;
+    return PM_mapRealPointer(*r_seg,*r_off);
+}
+
+void PMAPI PM_freeRealSeg(void *mem)
+{
+    /* Cannot de-allocate this memory */
+    mem = mem;
+}
+
+#pragma pack(1)
+
+typedef struct {
+    ushort  intno;
+    ushort  ds;
+    ushort  es;
+    ushort  fs;
+    ushort  gs;
+    ulong   eax;
+    ulong   edx;
+    } _RMREGS;
+
+#pragma pack()
+
+#define IN(reg)     regs.e.reg = in->e.reg
+#define OUT(reg)    out->e.reg = regs.e.reg
+
+int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out)
+{
+    _RMREGS rmregs;
+    PMREGS  regs;
+    PMSREGS pmsregs;
+
+    rmregs.intno = intno;
+    rmregs.eax = in->e.eax;
+    rmregs.edx = in->e.edx;
+    IN(ebx); IN(ecx); IN(esi); IN(edi);
+    regs.x.ax = 0x2511;
+    regs.e.edx = (uint)(&rmregs);
+    PM_segread(&pmsregs);
+    PM_int386x(0x21,&regs,&regs,&pmsregs);
+
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(esi); OUT(edi);
+    out->x.dx = rmregs.edx;
+    out->x.cflag = regs.x.cflag;
+    return out->x.ax;
+}
+
+int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, RMSREGS *sregs)
+{
+    _RMREGS rmregs;
+    PMREGS  regs;
+    PMSREGS pmsregs;
+
+    rmregs.intno = intno;
+    rmregs.eax = in->e.eax;
+    rmregs.edx = in->e.edx;
+    rmregs.es = sregs->es;
+    rmregs.ds = sregs->ds;
+    IN(ebx); IN(ecx); IN(esi); IN(edi);
+    regs.x.ax = 0x2511;
+    regs.e.edx = (uint)(&rmregs);
+    PM_segread(&pmsregs);
+    PM_int386x(0x21,&regs,&regs,&pmsregs);
+
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(esi); OUT(edi);
+    sregs->es = rmregs.es;
+    sregs->ds = rmregs.ds;
+    out->x.dx = rmregs.edx;
+    out->x.cflag = regs.x.cflag;
+    return out->x.ax;
+}
+
+void * PMAPI PM_getBIOSPointer(void)
+{
+    return (void*)((ulong)_x386_zero_base_ptr + 0x400);
+}
+
+void * PMAPI PM_getA0000Pointer(void)
+{
+    return (void*)((ulong)_x386_zero_base_ptr + 0xA0000);
+}
+
+void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{
+    VXD_regs    regs;
+
+    /* If we have connected to our helper VxD in a Windows DOS box, use
+     * the helper VxD services to map memory instead of the DPMI services.
+     * We do this because the helper VxD can properly disable caching
+     * where necessary, which we can only do directly here if we are
+     * running at ring 0 (ie: under real DOS).
+     */
+    if (VXD_version == -1)
+	PM_init();
+    if (VXD_version) {
+	memset(&regs,0,sizeof(regs));
+	regs.eax = API_NUM(PMHELP_MAPPHYS);
+	regs.ebx = base;
+	regs.ecx = limit;
+	regs.edx = isCached;
+	_PM_VxDCall(&regs,_PM_VXD_off,_PM_VXD_sel);
+	return (void*)regs.eax;
+	}
+
+    if (base > 0x100000)
+	return _x386_map_physical_address((void*)base,limit);
+    return (void*)((ulong)_x386_zero_base_ptr + base);
+}
+
+void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit)
+{
+    /* Mapping cannot be freed */
+}
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{ return 0xFFFFFFFFUL; }
+
+ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress)
+{ return false; }
+
+void * PMAPI PM_mapToProcess(void *base,ulong limit)
+{ return (void*)base; }
+
+ulong _cdecl _X32_getPhysMem(void);
+
+void PMAPI PM_availableMemory(ulong *physical,ulong *total)
+{
+    PMREGS  regs;
+
+    /* Get total memory available, including virtual memory */
+    regs.x.ax = 0x350B;
+    PM_int386(0x21,&regs,&regs);
+    *total = regs.e.eax;
+
+    /* Get physical memory available */
+    *physical = _X32_getPhysMem();
+    if (*physical > *total)
+	*physical = *total;
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* Borland's DPMI32, Watcom DOS4GW and DJGPP DPMI support routines         */
+/*-------------------------------------------------------------------------*/
+
+#if defined(DPMI32) || defined(DOS4GW) || defined(DJGPP)
+
+void * PMAPI PM_getBIOSPointer(void)
+{
+    return PM_mapPhysicalAddr(0x400,0xFFFF,true);
+}
+
+void * PMAPI PM_getA0000Pointer(void)
+{
+    return PM_mapPhysicalAddr(0xA0000,0xFFFF,true);
+}
+
+void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{
+    VXD_regs    regs;
+
+#ifdef  DJGPP
+    /* Enable near pointers for DJGPP V2 */
+    __djgpp_nearptr_enable();
+#endif
+    /* If we have connected to our helper VxD in a Windows DOS box, use
+     * the helper VxD services to map memory instead of the DPMI services.
+     * We do this because the helper VxD can properly disable caching
+     * where necessary, which we can only do directly here if we are
+     * running at ring 0 (ie: under real DOS).
+     */
+    if (VXD_version == -1)
+	PM_init();
+    if (VXD_version) {
+	memset(&regs,0,sizeof(regs));
+	regs.eax = API_NUM(PMHELP_MAPPHYS);
+	regs.ebx = base;
+	regs.ecx = limit;
+	regs.edx = isCached;
+	_PM_VxDCall(&regs,_PM_VXD_off,_PM_VXD_sel);
+	return (void*)regs.eax;
+	}
+    return DPMI_mapPhysicalAddr(base,limit,isCached);
+}
+
+void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit)
+{
+    /* Mapping cannot be freed */
+    (void)ptr;
+    (void)limit;
+}
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{
+    ulong   physAddr;
+    if (!PM_getPhysicalAddrRange(p,1,&physAddr))
+	return 0xFFFFFFFF;
+    return physAddr | ((ulong)p & 0xFFF);
+}
+
+ibool PMAPI PM_getPhysicalAddrRange(
+    void *p,
+    ulong length,
+    ulong *physAddress)
+{
+    VXD_regs    regs;
+    ulong       pte;
+    PMSREGS     sregs;
+    ulong       DSBaseAddr;
+
+    /* If we have connected to our helper VxD in a Windows DOS box, use the
+     * helper VxD services to find the physical address of an address.
+     */
+    if (VXD_version) {
+	memset(&regs,0,sizeof(regs));
+	regs.eax = API_NUM(PMHELP_GETPHYSICALADDRRANGE);
+	regs.ebx = (ulong)p;
+	regs.ecx = (ulong)length;
+	regs.edx = (ulong)physAddress;
+	_PM_VxDCall(&regs,_PM_VXD_off,_PM_VXD_sel);
+	return regs.eax;
+	}
+
+    /* Find base address for default DS selector */
+    PM_segread(&sregs);
+    DSBaseAddr = DPMI_getSelectorBase(sregs.ds);
+
+    /* Otherwise directly access the page tables to determine the
+     * physical memory address. Note that we touch the memory before
+     * calling, otherwise the memory may not be paged in correctly.
+     */
+    pte = *((ulong*)p);
+#ifdef  DOS4GW
+    if (_PM_pagingEnabled() == 0) {
+	int     count;
+	ulong   linAddr = (ulong)p;
+
+	/* When paging is disabled physical=linear */
+	for (count = (length+0xFFF) >> 12; count > 0; count--) {
+	    *physAddress++ = linAddr;
+	    linAddr += 4096;
+	    }
+	return true;
+	}
+    else if ((PDB = _PM_getPDB()) != 0 && DSBaseAddr == 0) {
+	int     startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage;
+	ulong   pageTable,*pPageTable,linAddr = (ulong)p;
+	ulong   limit = length-1;
+
+	pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF);
+	if (pPDB) {
+	    startPDB = (linAddr >> 22) & 0x3FFL;
+	    startPage = (linAddr >> 12) & 0x3FFL;
+	    endPDB = ((linAddr+limit) >> 22) & 0x3FFL;
+	    endPage = ((linAddr+limit) >> 12) & 0x3FFL;
+	    for (iPDB = startPDB; iPDB <= endPDB; iPDB++) {
+		pageTable = pPDB[iPDB] & ~0xFFFL;
+		pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF);
+		start = (iPDB == startPDB) ? startPage : 0;
+		end = (iPDB == endPDB) ? endPage : 0x3FFL;
+		for (iPage = start; iPage <= end; iPage++)
+		    *physAddress++ = (pPageTable[iPage] & ~0xFFF);
+		}
+	    return true;
+	    }
+	}
+#endif
+    return false;
+}
+
+void * PMAPI PM_mapToProcess(void *base,ulong limit)
+{
+    (void)limit;
+    return (void*)base;
+}
+
+void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off)
+{
+    static uchar *zeroPtr = NULL;
+
+    if (!zeroPtr)
+	zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true);
+    return (void*)(zeroPtr + MK_PHYS(r_seg,r_off));
+}
+
+void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off)
+{
+    PMREGS      r;
+    void        *p;
+
+    r.x.ax = 0x100;                 /* DPMI allocate DOS memory         */
+    r.x.bx = (size + 0xF) >> 4;     /* number of paragraphs             */
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag)
+	return NULL;                /* DPMI call failed                 */
+    *r_seg = r.x.ax;                /* Real mode segment                */
+    *r_off = 0;
+    p = PM_mapRealPointer(*r_seg,*r_off);
+    _PM_addRealModeBlock(p,r.x.dx);
+    return p;
+}
+
+void PMAPI PM_freeRealSeg(void *mem)
+{
+    PMREGS  r;
+
+    if (mem) {
+	r.x.ax = 0x101;                     /* DPMI free DOS memory         */
+	r.x.dx = _PM_findRealModeBlock(mem);/* DX := selector from 0x100    */
+	PM_int386(0x31, &r, &r);
+	}
+}
+
+static DPMI_handler_t   DPMI_int10 = NULL;
+
+void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler)
+{
+    DPMI_int10 = handler;
+}
+
+void PMAPI DPMI_int86(int intno, DPMI_regs *regs)
+{
+    PMREGS      r;
+    PMSREGS     sr;
+
+    if (intno == 0x10 && DPMI_int10) {
+	if (DPMI_int10(regs))
+	    return;
+	}
+    PM_segread(&sr);
+    r.x.ax = 0x300;                 /* DPMI issue real interrupt    */
+    r.h.bl = intno;
+    r.h.bh = 0;
+    r.x.cx = 0;
+    sr.es = sr.ds;
+    r.e.edi = (uint)regs;
+    PM_int386x(0x31, &r, &r, &sr);  /* Issue the interrupt          */
+}
+
+#define IN(reg)     rmregs.reg = in->e.reg
+#define OUT(reg)    out->e.reg = rmregs.reg
+
+int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out)
+{
+    DPMI_regs   rmregs;
+
+    memset(&rmregs, 0, sizeof(rmregs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+
+    DPMI_int86(intno,&rmregs);      /* DPMI issue real interrupt    */
+
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+    out->x.cflag = rmregs.flags & 0x1;
+    return out->x.ax;
+}
+
+int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,
+    RMSREGS *sregs)
+{
+    DPMI_regs   rmregs;
+
+    memset(&rmregs, 0, sizeof(rmregs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+    rmregs.es = sregs->es;
+    rmregs.ds = sregs->ds;
+
+    DPMI_int86(intno,&rmregs);      /* DPMI issue real interrupt    */
+
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+    sregs->es = rmregs.es;
+    sregs->cs = rmregs.cs;
+    sregs->ss = rmregs.ss;
+    sregs->ds = rmregs.ds;
+    out->x.cflag = rmregs.flags & 0x1;
+    return out->x.ax;
+}
+
+#pragma pack(1)
+
+typedef struct {
+	uint    LargestBlockAvail;
+	uint    MaxUnlockedPage;
+	uint    LargestLockablePage;
+	uint    LinAddrSpace;
+	uint    NumFreePagesAvail;
+	uint    NumPhysicalPagesFree;
+	uint    TotalPhysicalPages;
+	uint    FreeLinAddrSpace;
+	uint    SizeOfPageFile;
+	uint    res[3];
+	} MemInfo;
+
+#pragma pack()
+
+void PMAPI PM_availableMemory(ulong *physical,ulong *total)
+{
+    PMREGS  r;
+    PMSREGS sr;
+    MemInfo memInfo;
+
+    PM_segread(&sr);
+    r.x.ax = 0x500;                 /* DPMI get free memory info */
+    sr.es = sr.ds;
+    r.e.edi = (uint)&memInfo;
+    PM_int386x(0x31, &r, &r, &sr);  /* Issue the interrupt */
+    *physical = memInfo.NumPhysicalPagesFree * 4096;
+    *total = memInfo.LargestBlockAvail;
+    if (*total < *physical)
+	*physical = *total;
+}
+
+#endif
+
+#ifndef __16BIT__
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankA(
+    int bank)
+{
+    DPMI_regs   regs;
+    memset(&regs, 0, sizeof(regs));
+    regs.eax = 0x4F05;
+    regs.ebx = 0x0000;
+    regs.edx = bank;
+    DPMI_int86(0x10,&regs);
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankAB(
+    int bank)
+{
+    DPMI_regs   regs;
+    memset(&regs, 0, sizeof(regs));
+    regs.eax = 0x4F05;
+    regs.ebx = 0x0000;
+    regs.edx = bank;
+    DPMI_int86(0x10,&regs);
+    regs.eax = 0x4F05;
+    regs.ebx = 0x0001;
+    regs.edx = bank;
+    DPMI_int86(0x10,&regs);
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display start address.
+****************************************************************************/
+void PMAPI PM_setCRTStart(
+    int x,
+    int y,
+    int waitVRT)
+{
+    DPMI_regs   regs;
+    memset(&regs, 0, sizeof(regs));
+    regs.eax = 0x4F07;
+    regs.ebx = waitVRT;
+    regs.ecx = x;
+    regs.edx = y;
+    DPMI_int86(0x10,&regs);
+}
+
+#endif
+
+/****************************************************************************
+REMARKS:
+Function to get the file attributes for a specific file.
+****************************************************************************/
+uint PMAPI PM_getFileAttr(
+    const char *filename)
+{
+    /* TODO: Implement this! */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_getFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this! */
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to set the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_setFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this! */
+    return false;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c b/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c
new file mode 100755
index 0000000..eecc2da
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c
@@ -0,0 +1,1637 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  16/32 bit DOS
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <dos.h>
+
+/*--------------------------- Global variables ----------------------------*/
+
+#ifndef REALMODE
+static int  globalDataStart;
+#endif
+
+PM_criticalHandler  _VARAPI _PM_critHandler = NULL;
+PM_breakHandler     _VARAPI _PM_breakHandler = NULL;
+PM_intHandler       _VARAPI _PM_timerHandler = NULL;
+PM_intHandler       _VARAPI _PM_rtcHandler = NULL;
+PM_intHandler       _VARAPI _PM_keyHandler = NULL;
+PM_key15Handler     _VARAPI _PM_key15Handler = NULL;
+PM_mouseHandler     _VARAPI _PM_mouseHandler = NULL;
+PM_intHandler       _VARAPI _PM_int10Handler = NULL;
+int                 _VARAPI _PM_mouseMask;
+
+uchar *     _VARAPI _PM_ctrlCPtr;               /* Location of Ctrl-C flag      */
+uchar *     _VARAPI _PM_ctrlBPtr;               /* Location of Ctrl-Break flag  */
+uchar *     _VARAPI _PM_critPtr;                /* Location of Critical error Bf*/
+PMFARPTR    _VARAPI _PM_prevTimer = PMNULL;     /* Previous timer handler       */
+PMFARPTR    _VARAPI _PM_prevRTC = PMNULL;       /* Previous RTC handler         */
+PMFARPTR    _VARAPI _PM_prevKey = PMNULL;       /* Previous key handler         */
+PMFARPTR    _VARAPI _PM_prevKey15 = PMNULL;     /* Previous key15 handler       */
+PMFARPTR    _VARAPI _PM_prevBreak = PMNULL;     /* Previous break handler       */
+PMFARPTR    _VARAPI _PM_prevCtrlC = PMNULL;     /* Previous CtrlC handler       */
+PMFARPTR    _VARAPI _PM_prevCritical = PMNULL;  /* Previous critical handler    */
+long        _VARAPI _PM_prevRealTimer;          /* Previous real mode timer     */
+long        _VARAPI _PM_prevRealRTC;            /* Previous real mode RTC       */
+long        _VARAPI _PM_prevRealKey;            /* Previous real mode key       */
+long        _VARAPI _PM_prevRealKey15;          /* Previous real mode key15     */
+long        _VARAPI _PM_prevRealInt10;          /* Previous real mode int 10h   */
+static uchar        _PM_oldCMOSRegA;            /* CMOS register A contents     */
+static uchar        _PM_oldCMOSRegB;            /* CMOS register B contents     */
+static uchar        _PM_oldRTCPIC2;             /* Mask value for RTC IRQ8      */
+
+/* Structure to maintain information about hardware interrupt handlers,
+ * include a copy of the hardware IRQ assembler thunk (one for each
+ * hooked interrupt handler).
+ */
+
+typedef struct {
+    uchar       IRQ;
+    uchar       IRQVect;
+    uchar       prevPIC;
+    uchar       prevPIC2;
+    PMFARPTR    prevHandler;
+    long        prevRealhandler;
+    uchar       thunk[1];
+    /* IRQ assembler thunk follows ... */
+    } _PM_IRQHandle;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* Globals for locking interrupt handlers in _pmdos.asm */
+
+#ifndef REALMODE
+extern int  _VARAPI _PM_pmdosDataStart;
+extern int  _VARAPI _PM_pmdosDataEnd;
+extern int  _VARAPI _PM_DMADataStart;
+extern int  _VARAPI _PM_DMADataEnd;
+void _ASMAPI _PM_pmdosCodeStart(void);
+void _ASMAPI _PM_pmdosCodeEnd(void);
+void _ASMAPI _PM_DMACodeStart(void);
+void _ASMAPI _PM_DMACodeEnd(void);
+#endif
+
+/* Protected mode interrupt handlers, also called by PM callbacks below */
+
+void _ASMAPI _PM_timerISR(void);
+void _ASMAPI _PM_rtcISR(void);
+void _ASMAPI _PM_irqISRTemplate(void);
+void _ASMAPI _PM_irqISRTemplateEnd(void);
+void _ASMAPI _PM_keyISR(void);
+void _ASMAPI _PM_key15ISR(void);
+void _ASMAPI _PM_breakISR(void);
+void _ASMAPI _PM_ctrlCISR(void);
+void _ASMAPI _PM_criticalISR(void);
+void _ASMAPI _PM_mouseISR(void);
+void _ASMAPI _PM_int10PMCB(void);
+
+/* Protected mode DPMI callback handlers */
+
+void _ASMAPI _PM_mousePMCB(void);
+
+/* Routine to install a mouse handler function */
+
+void _ASMAPI _PM_setMouseHandler(int mask);
+
+/* Routine to allocate DPMI real mode callback routines */
+
+ibool _ASMAPI _DPMI_allocateCallback(void (_ASMAPI *pmcode)(),void *rmregs,long *RMCB);
+void _ASMAPI _DPMI_freeCallback(long RMCB);
+
+/* DPMI helper functions in PMLITE.C */
+
+ulong   PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit);
+int     PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr);
+ulong   PMAPI DPMI_getSelectorBase(ushort sel);
+int     PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit);
+uint    PMAPI DPMI_createSelector(ulong base,ulong limit);
+void    PMAPI DPMI_freeSelector(uint sel);
+int     PMAPI DPMI_lockLinearPages(ulong linear,ulong len);
+int     PMAPI DPMI_unlockLinearPages(ulong linear,ulong len);
+
+/* Functions to read and write CMOS registers */
+
+uchar   PMAPI _PM_readCMOS(int index);
+void    PMAPI _PM_writeCMOS(int index,uchar value);
+
+/*-------------------------------------------------------------------------*/
+/* Generic routines common to all environments                             */
+/*-------------------------------------------------------------------------*/
+
+void PMAPI PM_resetMouseDriver(int hardReset)
+{
+    RMREGS          regs;
+    PM_mouseHandler oldHandler = _PM_mouseHandler;
+
+    PM_restoreMouseHandler();
+    regs.x.ax = hardReset ? 0 : 33;
+    PM_int86(0x33, &regs, &regs);
+    if (oldHandler)
+	PM_setMouseHandler(_PM_mouseMask, oldHandler);
+}
+
+void PMAPI PM_setRealTimeClockFrequency(int frequency)
+{
+    static short convert[] = {
+	8192,
+	4096,
+	2048,
+	1024,
+	512,
+	256,
+	128,
+	64,
+	32,
+	16,
+	8,
+	4,
+	2,
+	-1,
+	};
+    int i;
+
+    /* First clear any pending RTC timeout if not cleared */
+    _PM_readCMOS(0x0C);
+    if (frequency == 0) {
+	/* Disable RTC timout */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F);
+	}
+    else {
+	/* Convert frequency value to RTC clock indexes */
+	for (i = 0; convert[i] != -1; i++) {
+	    if (convert[i] == frequency)
+		break;
+	    }
+
+	/* Set RTC timout value and enable timeout */
+	_PM_writeCMOS(0x0A,0x20 | (i+3));
+	_PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40);
+	}
+}
+
+#ifndef REALMODE
+
+static void PMAPI lockPMHandlers(void)
+{
+    static int      locked = 0;
+    int             stat;
+    PM_lockHandle   lh; /* Unused in DOS */
+
+    /* Lock all of the code and data used by our protected mode interrupt
+     * handling routines, so that it will continue to work correctly
+     * under real mode.
+     */
+    if (!locked) {
+	PM_saveDS();
+	stat  = !PM_lockDataPages(&globalDataStart-2048,4096,&lh);
+	stat |= !PM_lockDataPages(&_PM_pmdosDataStart,(int)&_PM_pmdosDataEnd - (int)&_PM_pmdosDataStart,&lh);
+	stat |= !PM_lockCodePages((__codePtr)_PM_pmdosCodeStart,(int)_PM_pmdosCodeEnd-(int)_PM_pmdosCodeStart,&lh);
+	stat |= !PM_lockDataPages(&_PM_DMADataStart,(int)&_PM_DMADataEnd - (int)&_PM_DMADataStart,&lh);
+	stat |= !PM_lockCodePages((__codePtr)_PM_DMACodeStart,(int)_PM_DMACodeEnd-(int)_PM_DMACodeStart,&lh);
+	if (stat) {
+	    printf("Page locking services failed - interrupt handling not safe!\n");
+	    exit(1);
+	    }
+	locked = 1;
+	}
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* DOS Real Mode support.                                                  */
+/*-------------------------------------------------------------------------*/
+
+#ifdef REALMODE
+
+#ifndef MK_FP
+#define MK_FP(s,o)  ( (void far *)( ((ulong)(s) << 16) + \
+		    (ulong)(o) ))
+#endif
+
+int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh)
+{
+    PM_saveDS();
+    _PM_mouseHandler = mh;
+    _PM_setMouseHandler(_PM_mouseMask = mask);
+    return 1;
+}
+
+void PMAPI PM_restoreMouseHandler(void)
+{
+    union REGS      regs;
+
+    if (_PM_mouseHandler) {
+	regs.x.ax = 33;
+	int86(0x33, &regs, &regs);
+	_PM_mouseHandler = NULL;
+	}
+}
+
+void PMAPI PM_setTimerHandler(PM_intHandler th)
+{
+    _PM_getRMvect(0x8, (long*)&_PM_prevTimer);
+    _PM_timerHandler = th;
+    _PM_setRMvect(0x8, (long)_PM_timerISR);
+}
+
+void PMAPI PM_restoreTimerHandler(void)
+{
+    if (_PM_timerHandler) {
+	_PM_setRMvect(0x8, (long)_PM_prevTimer);
+	_PM_timerHandler = NULL;
+	}
+}
+
+ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency)
+{
+    /* Save the old CMOS real time clock values */
+    _PM_oldCMOSRegA = _PM_readCMOS(0x0A);
+    _PM_oldCMOSRegB = _PM_readCMOS(0x0B);
+
+    /* Set the real time clock interrupt handler */
+    _PM_getRMvect(0x70, (long*)&_PM_prevRTC);
+    _PM_rtcHandler = th;
+    _PM_setRMvect(0x70, (long)_PM_rtcISR);
+
+    /* Program the real time clock default frequency */
+    PM_setRealTimeClockFrequency(frequency);
+
+    /* Unmask IRQ8 in the PIC2 */
+    _PM_oldRTCPIC2 = PM_inpb(0xA1);
+    PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE);
+    return true;
+}
+
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    if (_PM_rtcHandler) {
+	/* Restore CMOS registers and mask RTC clock */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB);
+	PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE));
+
+	/* Restore the interrupt vector */
+	_PM_setRMvect(0x70, (long)_PM_prevRTC);
+	_PM_rtcHandler = NULL;
+	}
+}
+
+void PMAPI PM_setKeyHandler(PM_intHandler kh)
+{
+    _PM_getRMvect(0x9, (long*)&_PM_prevKey);
+    _PM_keyHandler = kh;
+    _PM_setRMvect(0x9, (long)_PM_keyISR);
+}
+
+void PMAPI PM_restoreKeyHandler(void)
+{
+    if (_PM_keyHandler) {
+	_PM_setRMvect(0x9, (long)_PM_prevKey);
+	_PM_keyHandler = NULL;
+	}
+}
+
+void PMAPI PM_setKey15Handler(PM_key15Handler kh)
+{
+    _PM_getRMvect(0x15, (long*)&_PM_prevKey15);
+    _PM_key15Handler = kh;
+    _PM_setRMvect(0x15, (long)_PM_key15ISR);
+}
+
+void PMAPI PM_restoreKey15Handler(void)
+{
+    if (_PM_key15Handler) {
+	_PM_setRMvect(0x15, (long)_PM_prevKey15);
+	_PM_key15Handler = NULL;
+	}
+}
+
+void PMAPI PM_installAltBreakHandler(PM_breakHandler bh)
+{
+    static int  ctrlCFlag,ctrlBFlag;
+
+    _PM_ctrlCPtr = (uchar*)&ctrlCFlag;
+    _PM_ctrlBPtr = (uchar*)&ctrlBFlag;
+    _PM_getRMvect(0x1B, (long*)&_PM_prevBreak);
+    _PM_getRMvect(0x23, (long*)&_PM_prevCtrlC);
+    _PM_breakHandler = bh;
+    _PM_setRMvect(0x1B, (long)_PM_breakISR);
+    _PM_setRMvect(0x23, (long)_PM_ctrlCISR);
+}
+
+void PMAPI PM_installBreakHandler(void)
+{
+    PM_installAltBreakHandler(NULL);
+}
+
+void PMAPI PM_restoreBreakHandler(void)
+{
+    if (_PM_prevBreak) {
+	_PM_setRMvect(0x1B, (long)_PM_prevBreak);
+	_PM_setRMvect(0x23, (long)_PM_prevCtrlC);
+	_PM_prevBreak = NULL;
+	_PM_breakHandler = NULL;
+	}
+}
+
+void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch)
+{
+    static  short critBuf[2];
+
+    _PM_critPtr = (uchar*)critBuf;
+    _PM_getRMvect(0x24, (long*)&_PM_prevCritical);
+    _PM_critHandler = ch;
+    _PM_setRMvect(0x24, (long)_PM_criticalISR);
+}
+
+void PMAPI PM_installCriticalHandler(void)
+{
+    PM_installAltCriticalHandler(NULL);
+}
+
+void PMAPI PM_restoreCriticalHandler(void)
+{
+    if (_PM_prevCritical) {
+	_PM_setRMvect(0x24, (long)_PM_prevCritical);
+	_PM_prevCritical = NULL;
+	_PM_critHandler = NULL;
+	}
+}
+
+int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;      /* Do nothing for real mode */
+    return 1;
+}
+
+int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;      /* Do nothing for real mode */
+    return 1;
+}
+
+int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;      /* Do nothing for real mode */
+    return 1;
+}
+
+int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;      /* Do nothing for real mode */
+    return 1;
+}
+
+void PMAPI PM_getPMvect(int intno, PMFARPTR *isr)
+{
+    long t;
+    _PM_getRMvect(intno,&t);
+    *isr = (void*)t;
+}
+
+void PMAPI PM_setPMvect(int intno, PM_intHandler isr)
+{
+    PM_saveDS();
+    _PM_setRMvect(intno,(long)isr);
+}
+
+void PMAPI PM_restorePMvect(int intno, PMFARPTR isr)
+{
+    _PM_setRMvect(intno,(long)isr);
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* Phar Lap TNT DOS Extender support.                                      */
+/*-------------------------------------------------------------------------*/
+
+#ifdef TNT
+
+#include <pldos32.h>
+#include <pharlap.h>
+#include <hw386.h>
+
+static long prevRealBreak;      /* Previous real mode break handler     */
+static long prevRealCtrlC;      /* Previous real mode CtrlC handler     */
+static long prevRealCritical;   /* Prev real mode critical handler      */
+static uchar *mousePtr;
+
+/* The following real mode routine is used to call a 32 bit protected
+ * mode FAR function from real mode. We use this for passing up control
+ * from the real mode mouse callback to our protected mode code.
+ */
+
+static UCHAR realHandler[] = {      /* Real mode code generic handler   */
+    0x00,0x00,0x00,0x00,            /* __PM_callProtp                   */
+    0x00,0x00,                      /* __PM_protCS                      */
+    0x00,0x00,0x00,0x00,            /* __PM_protHandler                 */
+    0x66,0x60,                      /*  pushad                          */
+    0x1E,                           /*  push    ds                      */
+    0x6A,0x00,                      /*  push    0                       */
+    0x6A,0x00,                      /*  push    0                       */
+    0x2E,0xFF,0x36,0x04,0x00,       /*  push    [cs:__PM_protCS]        */
+    0x66,0x2E,0xFF,0x36,0x06,0x00,  /*  push    [cs:__PM_protHandler]   */
+    0x2E,0xFF,0x1E,0x00,0x00,       /*  call    [cs:__PM_callProtp]     */
+    0x83,0xC4,0x0A,                 /*  add     sp,10                   */
+    0x1F,                           /*  pop     ds                      */
+    0x66,0x61,                      /*  popad                           */
+    0xCB,                           /*  retf                            */
+    };
+
+/* The following functions installs the above realmode callback mechanism
+ * in real mode memory for calling the protected mode routine.
+ */
+
+uchar * installCallback(void (PMAPI *pmCB)(),uint *rseg, uint *roff)
+{
+    CONFIG_INF  config;
+    REALPTR     realBufAdr,callProtp;
+    ULONG       bufSize;
+    FARPTR      protBufAdr;
+    uchar       *p;
+
+    /* Get address of real mode routine to call up to protected mode    */
+    _dx_rmlink_get(&callProtp, &realBufAdr, &bufSize, &protBufAdr);
+    _dx_config_inf(&config, (UCHAR*)&config);
+
+    /* Fill in the values in the real mode code segment so that it will
+     * call the correct routine.
+     */
+    *((REALPTR*)&realHandler[0]) = callProtp;
+    *((USHORT*)&realHandler[4]) = config.c_cs_sel;
+    *((ULONG*)&realHandler[6]) = (ULONG)pmCB;
+
+    /* Copy the real mode handler to real mode memory   */
+    if ((p = PM_allocRealSeg(sizeof(realHandler),rseg,roff)) == NULL)
+	return NULL;
+    memcpy(p,realHandler,sizeof(realHandler));
+
+    /* Skip past global variabls in real mode code segment */
+    *roff += 0x0A;
+    return p;
+}
+
+int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh)
+{
+    RMREGS      regs;
+    RMSREGS     sregs;
+    uint        rseg,roff;
+
+    lockPMHandlers();           /* Ensure our handlers are locked   */
+
+    if ((mousePtr = installCallback(_PM_mouseISR, &rseg, &roff)) == NULL)
+	return 0;
+    _PM_mouseHandler = mh;
+
+    /* Install the real mode mouse handler  */
+    sregs.es = rseg;
+    regs.x.dx = roff;
+    regs.x.cx = _PM_mouseMask = mask;
+    regs.x.ax = 0xC;
+    PM_int86x(0x33, &regs, &regs, &sregs);
+    return 1;
+}
+
+void PMAPI PM_restoreMouseHandler(void)
+{
+    RMREGS  regs;
+
+    if (_PM_mouseHandler) {
+	regs.x.ax = 33;
+	PM_int86(0x33, &regs, &regs);
+	PM_freeRealSeg(mousePtr);
+	_PM_mouseHandler = NULL;
+	}
+}
+
+void PMAPI PM_getPMvect(int intno, PMFARPTR *isr)
+{
+    FARPTR  ph;
+
+    _dx_pmiv_get(intno, &ph);
+    isr->sel = FP_SEL(ph);
+    isr->off = FP_OFF(ph);
+}
+
+void PMAPI PM_setPMvect(int intno, PM_intHandler isr)
+{
+    CONFIG_INF  config;
+    FARPTR      ph;
+
+    PM_saveDS();
+    _dx_config_inf(&config, (UCHAR*)&config);
+    FP_SET(ph,(uint)isr,config.c_cs_sel);
+    _dx_pmiv_set(intno,ph);
+}
+
+void PMAPI PM_restorePMvect(int intno, PMFARPTR isr)
+{
+    FARPTR  ph;
+
+    FP_SET(ph,isr.off,isr.sel);
+    _dx_pmiv_set(intno,ph);
+}
+
+static void getISR(int intno, PMFARPTR *pmisr, long *realisr)
+{
+    PM_getPMvect(intno,pmisr);
+    _PM_getRMvect(intno, realisr);
+}
+
+static void restoreISR(int intno, PMFARPTR pmisr, long realisr)
+{
+    _PM_setRMvect(intno,realisr);
+    PM_restorePMvect(intno,pmisr);
+}
+
+static void setISR(int intno, void (PMAPI *isr)())
+{
+    CONFIG_INF  config;
+    FARPTR      ph;
+
+    lockPMHandlers();           /* Ensure our handlers are locked   */
+
+    _dx_config_inf(&config, (UCHAR*)&config);
+    FP_SET(ph,(uint)isr,config.c_cs_sel);
+    _dx_apmiv_set(intno,ph);
+}
+
+void PMAPI PM_setTimerHandler(PM_intHandler th)
+{
+    getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer);
+    _PM_timerHandler = th;
+    setISR(0x8, _PM_timerISR);
+}
+
+void PMAPI PM_restoreTimerHandler(void)
+{
+    if (_PM_timerHandler) {
+	restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer);
+	_PM_timerHandler = NULL;
+	}
+}
+
+ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency)
+{
+    /* Save the old CMOS real time clock values */
+    _PM_oldCMOSRegA = _PM_readCMOS(0x0A);
+    _PM_oldCMOSRegB = _PM_readCMOS(0x0B);
+
+    /* Set the real time clock interrupt handler */
+    getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC);
+    _PM_rtcHandler = th;
+    setISR(0x70, _PM_rtcISR);
+
+    /* Program the real time clock default frequency */
+    PM_setRealTimeClockFrequency(frequency);
+
+    /* Unmask IRQ8 in the PIC2 */
+    _PM_oldRTCPIC2 = PM_inpb(0xA1);
+    PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE);
+    return true;
+}
+
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    if (_PM_rtcHandler) {
+	/* Restore CMOS registers and mask RTC clock */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB);
+	PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE));
+
+	/* Restore the interrupt vector */
+	restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC);
+	_PM_rtcHandler = NULL;
+	}
+}
+
+void PMAPI PM_setKeyHandler(PM_intHandler kh)
+{
+    getISR(0x9, &_PM_prevKey, &_PM_prevRealKey);
+    _PM_keyHandler = kh;
+    setISR(0x9, _PM_keyISR);
+}
+
+void PMAPI PM_restoreKeyHandler(void)
+{
+    if (_PM_keyHandler) {
+	restoreISR(0x9, _PM_prevKey, _PM_prevRealKey);
+	_PM_keyHandler = NULL;
+	}
+}
+
+void PMAPI PM_setKey15Handler(PM_key15Handler kh)
+{
+    getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15);
+    _PM_key15Handler = kh;
+    setISR(0x15, _PM_key15ISR);
+}
+
+void PMAPI PM_restoreKey15Handler(void)
+{
+    if (_PM_key15Handler) {
+	restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15);
+	_PM_key15Handler = NULL;
+	}
+}
+
+void PMAPI PM_installAltBreakHandler(PM_breakHandler bh)
+{
+    static int  ctrlCFlag,ctrlBFlag;
+
+    _PM_ctrlCPtr = (uchar*)&ctrlCFlag;
+    _PM_ctrlBPtr = (uchar*)&ctrlBFlag;
+    getISR(0x1B, &_PM_prevBreak, &prevRealBreak);
+    getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC);
+    _PM_breakHandler = bh;
+    setISR(0x1B, _PM_breakISR);
+    setISR(0x23, _PM_ctrlCISR);
+}
+
+void PMAPI PM_installBreakHandler(void)
+{
+    PM_installAltBreakHandler(NULL);
+}
+
+void PMAPI PM_restoreBreakHandler(void)
+{
+    if (_PM_prevBreak.sel) {
+	restoreISR(0x1B, _PM_prevBreak, prevRealBreak);
+	restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC);
+	_PM_prevBreak.sel = 0;
+	_PM_breakHandler = NULL;
+	}
+}
+
+void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch)
+{
+    static short    critBuf[2];
+
+    _PM_critPtr = (uchar*)critBuf;
+    getISR(0x24, &_PM_prevCritical, &prevRealCritical);
+    _PM_critHandler = ch;
+    setISR(0x24, _PM_criticalISR);
+}
+
+void PMAPI PM_installCriticalHandler(void)
+{
+    PM_installAltCriticalHandler(NULL);
+}
+
+void PMAPI PM_restoreCriticalHandler(void)
+{
+    if (_PM_prevCritical.sel) {
+	restoreISR(0x24, _PM_prevCritical, prevRealCritical);
+	_PM_prevCritical.sel = 0;
+	_PM_critHandler = NULL;
+	}
+}
+
+int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    return (_dx_lock_pgsn(p,len) == 0);
+}
+
+int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    return (_dx_ulock_pgsn(p,len) == 0);
+}
+
+int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    CONFIG_INF  config;
+    FARPTR      fp;
+
+    _dx_config_inf(&config, (UCHAR*)&config);
+    FP_SET(fp,p,config.c_cs_sel);
+    return (_dx_lock_pgs(fp,len) == 0);
+}
+
+int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    CONFIG_INF  config;
+    FARPTR      fp;
+
+    _dx_config_inf(&config, (UCHAR*)&config);
+    FP_SET(fp,p,config.c_cs_sel);
+    return (_dx_ulock_pgs(fp,len) == 0);
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* Symantec C++ DOSX and FlashTek X-32/X-32VM support                      */
+/*-------------------------------------------------------------------------*/
+
+#if defined(DOSX) || defined(X32VM)
+
+#ifdef  X32VM
+#include <x32.h>
+#endif
+
+static long prevRealBreak;      /* Previous real mode break handler     */
+static long prevRealCtrlC;      /* Previous real mode CtrlC handler     */
+static long prevRealCritical;   /* Prev real mode critical handler      */
+
+static uint mouseSel = 0,mouseOff;
+
+/* The following real mode routine is used to call a 32 bit protected
+ * mode FAR function from real mode. We use this for passing up control
+ * from the real mode mouse callback to our protected mode code.
+ */
+
+static char realHandler[] = {       /* Real mode code generic handler   */
+    0x00,0x00,0x00,0x00,            /* __PM_callProtp                   */
+    0x00,0x00,                      /* __PM_protCS                      */
+    0x00,0x00,0x00,0x00,            /* __PM_protHandler                 */
+    0x1E,                           /*  push    ds                      */
+    0x6A,0x00,                      /*  push    0                       */
+    0x6A,0x00,                      /*  push    0                       */
+    0x2E,0xFF,0x36,0x04,0x00,       /*  push    [cs:__PM_protCS]        */
+    0x66,0x2E,0xFF,0x36,0x06,0x00,  /*  push    [cs:__PM_protHandler]   */
+    0x2E,0xFF,0x1E,0x00,0x00,       /*  call    [cs:__PM_callProtp]     */
+    0x83,0xC4,0x0A,                 /*  add     sp,10                   */
+    0x1F,                           /*  pop     ds                      */
+    0xCB,                           /*  retf                            */
+    };
+
+/* The following functions installs the above realmode callback mechanism
+ * in real mode memory for calling the protected mode routine.
+ */
+
+int installCallback(void (PMAPI *pmCB)(),uint *psel, uint *poff,
+    uint *rseg, uint *roff)
+{
+    PMREGS          regs;
+    PMSREGS         sregs;
+
+    regs.x.ax = 0x250D;
+    PM_segread(&sregs);
+    PM_int386x(0x21,&regs,&regs,&sregs);    /* Get RM callback address  */
+
+    /* Fill in the values in the real mode code segment so that it will
+     * call the correct routine.
+     */
+    *((ulong*)&realHandler[0]) = regs.e.eax;
+    *((ushort*)&realHandler[4]) = sregs.cs;
+    *((ulong*)&realHandler[6]) = (ulong)pmCB;
+
+    /* Copy the real mode handler to real mode memory (only allocate the
+     * buffer once since we cant dealloate it with X32).
+     */
+    if (*psel == 0) {
+	if (!PM_allocRealSeg(sizeof(realHandler),psel,poff,rseg,roff))
+	    return 0;
+	}
+    PM_memcpyfn(*psel,*poff,realHandler,sizeof(realHandler));
+
+    /* Skip past global variables in real mode code segment */
+    *roff += 0x0A;
+    return 1;
+}
+
+int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh)
+{
+    RMREGS      regs;
+    RMSREGS     sregs;
+    uint    rseg,roff;
+
+    lockPMHandlers();           /* Ensure our handlers are locked   */
+
+    if (!installCallback(_PM_mouseISR, &mouseSel, &mouseOff, &rseg, &roff))
+	return 0;
+    _PM_mouseHandler = mh;
+
+    /* Install the real mode mouse handler  */
+    sregs.es = rseg;
+    regs.x.dx = roff;
+    regs.x.cx = _PM_mouseMask = mask;
+    regs.x.ax = 0xC;
+    PM_int86x(0x33, &regs, &regs, &sregs);
+    return 1;
+}
+
+void PMAPI PM_restoreMouseHandler(void)
+{
+    RMREGS  regs;
+
+    if (_PM_mouseHandler) {
+	regs.x.ax = 33;
+	PM_int86(0x33, &regs, &regs);
+	_PM_mouseHandler = NULL;
+	}
+}
+
+void PMAPI PM_getPMvect(int intno, PMFARPTR *isr)
+{
+    PMREGS  regs;
+    PMSREGS sregs;
+
+    PM_segread(&sregs);
+    regs.x.ax = 0x2502;         /* Get PM interrupt vector              */
+    regs.x.cx = intno;
+    PM_int386x(0x21, &regs, &regs, &sregs);
+    isr->sel = sregs.es;
+    isr->off = regs.e.ebx;
+}
+
+void PMAPI PM_setPMvect(int intno, PM_intHandler isr)
+{
+    PMFARPTR    pmisr;
+    PMSREGS     sregs;
+
+    PM_saveDS();
+    PM_segread(&sregs);
+    pmisr.sel = sregs.cs;
+    pmisr.off = (uint)isr;
+    PM_restorePMvect(intno, pmisr);
+}
+
+void PMAPI PM_restorePMvect(int intno, PMFARPTR isr)
+{
+    PMREGS  regs;
+    PMSREGS sregs;
+
+    PM_segread(&sregs);
+    regs.x.ax = 0x2505;         /* Set PM interrupt vector              */
+    regs.x.cx = intno;
+    sregs.ds = isr.sel;
+    regs.e.edx = isr.off;
+    PM_int386x(0x21, &regs, &regs, &sregs);
+}
+
+static void getISR(int intno, PMFARPTR *pmisr, long *realisr)
+{
+    PM_getPMvect(intno,pmisr);
+    _PM_getRMvect(intno,realisr);
+}
+
+static void restoreISR(int intno, PMFARPTR pmisr, long realisr)
+{
+    PMREGS  regs;
+    PMSREGS sregs;
+
+    PM_segread(&sregs);
+    regs.x.ax = 0x2507;         /* Set real and PM vectors              */
+    regs.x.cx = intno;
+    sregs.ds = pmisr.sel;
+    regs.e.edx = pmisr.off;
+    regs.e.ebx = realisr;
+    PM_int386x(0x21, &regs, &regs, &sregs);
+}
+
+static void setISR(int intno, void *isr)
+{
+    PMREGS  regs;
+    PMSREGS sregs;
+
+    lockPMHandlers();           /* Ensure our handlers are locked       */
+
+    PM_segread(&sregs);
+    regs.x.ax = 0x2506;         /* Hook real and protected vectors      */
+    regs.x.cx = intno;
+    sregs.ds = sregs.cs;
+    regs.e.edx = (uint)isr;
+    PM_int386x(0x21, &regs, &regs, &sregs);
+}
+
+void PMAPI PM_setTimerHandler(PM_intHandler th)
+{
+    getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer);
+    _PM_timerHandler = th;
+    setISR(0x8, _PM_timerISR);
+}
+
+void PMAPI PM_restoreTimerHandler(void)
+{
+    if (_PM_timerHandler) {
+	restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer);
+	_PM_timerHandler = NULL;
+	}
+}
+
+ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency)
+{
+    /* Save the old CMOS real time clock values */
+    _PM_oldCMOSRegA = _PM_readCMOS(0x0A);
+    _PM_oldCMOSRegB = _PM_readCMOS(0x0B);
+
+    /* Set the real time clock interrupt handler */
+    getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC);
+    _PM_rtcHandler = th;
+    setISR(0x70, _PM_rtcISR);
+
+    /* Program the real time clock default frequency */
+    PM_setRealTimeClockFrequency(frequency);
+
+    /* Unmask IRQ8 in the PIC2 */
+    _PM_oldRTCPIC2 = PM_inpb(0xA1);
+    PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE);
+    return true;
+}
+
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    if (_PM_rtcHandler) {
+	/* Restore CMOS registers and mask RTC clock */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB);
+	PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE));
+
+	/* Restore the interrupt vector */
+	restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC);
+	_PM_rtcHandler = NULL;
+	}
+}
+
+void PMAPI PM_setKeyHandler(PM_intHandler kh)
+{
+    getISR(0x9, &_PM_prevKey, &_PM_prevRealKey);
+    _PM_keyHandler = kh;
+    setISR(0x9, _PM_keyISR);
+}
+
+void PMAPI PM_restoreKeyHandler(void)
+{
+    if (_PM_keyHandler) {
+	restoreISR(0x9, _PM_prevKey, _PM_prevRealKey);
+	_PM_keyHandler = NULL;
+	}
+}
+
+void PMAPI PM_setKey15Handler(PM_key15Handler kh)
+{
+    getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15);
+    _PM_key15Handler = kh;
+    setISR(0x15, _PM_key15ISR);
+}
+
+void PMAPI PM_restoreKey15Handler(void)
+{
+    if (_PM_key15Handler) {
+	restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15);
+	_PM_key15Handler = NULL;
+	}
+}
+
+void PMAPI PM_installAltBreakHandler(PM_breakHandler bh)
+{
+    static int  ctrlCFlag,ctrlBFlag;
+
+    _PM_ctrlCPtr = (uchar*)&ctrlCFlag;
+    _PM_ctrlBPtr = (uchar*)&ctrlBFlag;
+    getISR(0x1B, &_PM_prevBreak, &prevRealBreak);
+    getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC);
+    _PM_breakHandler = bh;
+    setISR(0x1B, _PM_breakISR);
+    setISR(0x23, _PM_ctrlCISR);
+}
+
+void PMAPI PM_installBreakHandler(void)
+{
+    PM_installAltBreakHandler(NULL);
+}
+
+void PMAPI PM_restoreBreakHandler(void)
+{
+    if (_PM_prevBreak.sel) {
+	restoreISR(0x1B, _PM_prevBreak, prevRealBreak);
+	restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC);
+	_PM_prevBreak.sel = 0;
+	_PM_breakHandler = NULL;
+	}
+}
+
+void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch)
+{
+    static short    critBuf[2];
+
+    _PM_critPtr = (uchar*)critBuf;
+    getISR(0x24, &_PM_prevCritical, &prevRealCritical);
+    _PM_critHandler = ch;
+    setISR(0x24, _PM_criticalISR);
+}
+
+void PMAPI PM_installCriticalHandler(void)
+{
+    PM_installAltCriticalHandler(NULL);
+}
+
+void PMAPI PM_restoreCriticalHandler(void)
+{
+    if (_PM_prevCritical.sel) {
+	restoreISR(0x24, _PM_prevCritical, prevRealCritical);
+	_PM_prevCritical.sel = 0;
+	_PM_critHandler = NULL;
+	}
+}
+
+int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    return (_x386_memlock(p,len) == 0);
+}
+
+int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    return (_x386_memunlock(p,len) == 0);
+}
+
+int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    return (_x386_memlock(p,len) == 0);
+}
+
+int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    return (_x386_memunlock(p,len) == 0);
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* Borland's DPMI32 DOS Power Pack Extender support.                       */
+/*-------------------------------------------------------------------------*/
+
+#ifdef  DPMI32
+#define GENERIC_DPMI32          /* Use generic 32 bit DPMI routines */
+
+void PMAPI PM_getPMvect(int intno, PMFARPTR *isr)
+{
+    PMREGS  regs;
+
+    regs.x.ax = 0x204;
+    regs.h.bl = intno;
+    PM_int386(0x31,&regs,&regs);
+    isr->sel = regs.x.cx;
+    isr->off = regs.e.edx;
+}
+
+void PMAPI PM_setPMvect(int intno, PM_intHandler isr)
+{
+    PMSREGS sregs;
+    PMREGS  regs;
+
+    PM_saveDS();
+    regs.x.ax = 0x205;          /* Set protected mode vector        */
+    regs.h.bl = intno;
+    PM_segread(&sregs);
+    regs.x.cx = sregs.cs;
+    regs.e.edx = (uint)isr;
+    PM_int386(0x31,&regs,&regs);
+}
+
+void PMAPI PM_restorePMvect(int intno, PMFARPTR isr)
+{
+    PMREGS  regs;
+
+    regs.x.ax = 0x205;
+    regs.h.bl = intno;
+    regs.x.cx = isr.sel;
+    regs.e.edx = isr.off;
+    PM_int386(0x31,&regs,&regs);
+}
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* Watcom C/C++ with Rational DOS/4GW support.                             */
+/*-------------------------------------------------------------------------*/
+
+#ifdef  DOS4GW
+#define GENERIC_DPMI32          /* Use generic 32 bit DPMI routines */
+
+#define MOUSE_SUPPORTED         /* DOS4GW directly supports mouse   */
+
+/* We use the normal DOS services to save and restore interrupts handlers
+ * for Watcom C++, because using the direct DPMI functions does not
+ * appear to work properly. At least if we use the DPMI functions, we
+ * dont get the auto-passup feature that we need to correctly trap
+ * real and protected mode interrupts without installing Bi-model
+ * interrupt handlers.
+ */
+
+void PMAPI PM_getPMvect(int intno, PMFARPTR *isr)
+{
+    PMREGS  regs;
+    PMSREGS sregs;
+
+    PM_segread(&sregs);
+    regs.h.ah = 0x35;
+    regs.h.al = intno;
+    PM_int386x(0x21,&regs,&regs,&sregs);
+    isr->sel = sregs.es;
+    isr->off = regs.e.ebx;
+}
+
+void PMAPI PM_setPMvect(int intno, PM_intHandler isr)
+{
+    PMREGS  regs;
+    PMSREGS sregs;
+
+    PM_saveDS();
+    PM_segread(&sregs);
+    regs.h.ah = 0x25;
+    regs.h.al = intno;
+    sregs.ds = sregs.cs;
+    regs.e.edx = (uint)isr;
+    PM_int386x(0x21,&regs,&regs,&sregs);
+}
+
+void PMAPI PM_restorePMvect(int intno, PMFARPTR isr)
+{
+    PMREGS  regs;
+    PMSREGS sregs;
+
+    PM_segread(&sregs);
+    regs.h.ah = 0x25;
+    regs.h.al = intno;
+    sregs.ds = isr.sel;
+    regs.e.edx = isr.off;
+    PM_int386x(0x21,&regs,&regs,&sregs);
+}
+
+int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh)
+{
+    lockPMHandlers();           /* Ensure our handlers are locked   */
+
+    _PM_mouseHandler = mh;
+    _PM_setMouseHandler(_PM_mouseMask = mask);
+    return 1;
+}
+
+void PMAPI PM_restoreMouseHandler(void)
+{
+    PMREGS  regs;
+
+    if (_PM_mouseHandler) {
+	regs.x.ax = 33;
+	PM_int386(0x33, &regs, &regs);
+	_PM_mouseHandler = NULL;
+	}
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* DJGPP port of GNU C++ support.                                          */
+/*-------------------------------------------------------------------------*/
+
+#ifdef DJGPP
+#define GENERIC_DPMI32          /* Use generic 32 bit DPMI routines */
+
+void PMAPI PM_getPMvect(int intno, PMFARPTR *isr)
+{
+    PMREGS  regs;
+
+    regs.x.ax = 0x204;
+    regs.h.bl = intno;
+    PM_int386(0x31,&regs,&regs);
+    isr->sel = regs.x.cx;
+    isr->off = regs.e.edx;
+}
+
+void PMAPI PM_setPMvect(int intno, PM_intHandler isr)
+{
+    PMSREGS sregs;
+    PMREGS  regs;
+
+    PM_saveDS();
+    regs.x.ax = 0x205;          /* Set protected mode vector        */
+    regs.h.bl = intno;
+    PM_segread(&sregs);
+    regs.x.cx = sregs.cs;
+    regs.e.edx = (uint)isr;
+    PM_int386(0x31,&regs,&regs);
+}
+
+void PMAPI PM_restorePMvect(int intno, PMFARPTR isr)
+{
+    PMREGS  regs;
+
+    regs.x.ax = 0x205;
+    regs.h.bl = intno;
+    regs.x.cx = isr.sel;
+    regs.e.edx = isr.off;
+    PM_int386(0x31,&regs,&regs);
+}
+
+#endif
+
+/*-------------------------------------------------------------------------*/
+/* Generic 32 bit DPMI routines                                            */
+/*-------------------------------------------------------------------------*/
+
+#if defined(GENERIC_DPMI32)
+
+static long prevRealBreak;      /* Previous real mode break handler     */
+static long prevRealCtrlC;      /* Previous real mode CtrlC handler     */
+static long prevRealCritical;   /* Prev real mode critical handler      */
+
+#ifndef MOUSE_SUPPORTED
+
+/* The following real mode routine is used to call a 32 bit protected
+ * mode FAR function from real mode. We use this for passing up control
+ * from the real mode mouse callback to our protected mode code.
+ */
+
+static long mouseRMCB;          /* Mouse real mode callback address     */
+static uchar *mousePtr;
+static char mouseRegs[0x32];    /* Real mode regs for mouse callback    */
+static uchar mouseHandler[] = {
+    0x00,0x00,0x00,0x00,        /* _realRMCB                            */
+    0x2E,0xFF,0x1E,0x00,0x00,   /*  call    [cs:_realRMCB]              */
+    0xCB,                       /*  retf                                */
+    };
+
+int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh)
+{
+    RMREGS      regs;
+    RMSREGS     sregs;
+    uint        rseg,roff;
+
+    lockPMHandlers();           /* Ensure our handlers are locked   */
+
+    /* Copy the real mode handler to real mode memory   */
+    if ((mousePtr = PM_allocRealSeg(sizeof(mouseHandler),&rseg,&roff)) == NULL)
+	return 0;
+    memcpy(mousePtr,mouseHandler,sizeof(mouseHandler));
+    if (!_DPMI_allocateCallback(_PM_mousePMCB, mouseRegs, &mouseRMCB))
+	PM_fatalError("Unable to allocate real mode callback!\n");
+    PM_setLong(mousePtr,mouseRMCB);
+
+    /* Install the real mode mouse handler  */
+    _PM_mouseHandler = mh;
+    sregs.es = rseg;
+    regs.x.dx = roff+4;
+    regs.x.cx = _PM_mouseMask = mask;
+    regs.x.ax = 0xC;
+    PM_int86x(0x33, &regs, &regs, &sregs);
+    return 1;
+}
+
+void PMAPI PM_restoreMouseHandler(void)
+{
+    RMREGS  regs;
+
+    if (_PM_mouseHandler) {
+	regs.x.ax = 33;
+	PM_int86(0x33, &regs, &regs);
+	PM_freeRealSeg(mousePtr);
+	_DPMI_freeCallback(mouseRMCB);
+	_PM_mouseHandler = NULL;
+	}
+}
+
+#endif
+
+static void getISR(int intno, PMFARPTR *pmisr, long *realisr)
+{
+    PM_getPMvect(intno,pmisr);
+    _PM_getRMvect(intno,realisr);
+}
+
+static void restoreISR(int intno, PMFARPTR pmisr, long realisr)
+{
+    _PM_setRMvect(intno,realisr);
+    PM_restorePMvect(intno,pmisr);
+}
+
+static void setISR(int intno, void (* PMAPI pmisr)())
+{
+    lockPMHandlers();           /* Ensure our handlers are locked   */
+    PM_setPMvect(intno,pmisr);
+}
+
+void PMAPI PM_setTimerHandler(PM_intHandler th)
+{
+    getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer);
+    _PM_timerHandler = th;
+    setISR(0x8, _PM_timerISR);
+}
+
+void PMAPI PM_restoreTimerHandler(void)
+{
+    if (_PM_timerHandler) {
+	restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer);
+	_PM_timerHandler = NULL;
+	}
+}
+
+ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency)
+{
+    /* Save the old CMOS real time clock values */
+    _PM_oldCMOSRegA = _PM_readCMOS(0x0A);
+    _PM_oldCMOSRegB = _PM_readCMOS(0x0B);
+
+    /* Set the real time clock interrupt handler */
+    getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC);
+    _PM_rtcHandler = th;
+    setISR(0x70, _PM_rtcISR);
+
+    /* Program the real time clock default frequency */
+    PM_setRealTimeClockFrequency(frequency);
+
+    /* Unmask IRQ8 in the PIC2 */
+    _PM_oldRTCPIC2 = PM_inpb(0xA1);
+    PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE);
+    return true;
+}
+
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    if (_PM_rtcHandler) {
+	/* Restore CMOS registers and mask RTC clock */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB);
+	PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE));
+
+	/* Restore the interrupt vector */
+	restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC);
+	_PM_rtcHandler = NULL;
+	}
+}
+
+PM_IRQHandle PMAPI PM_setIRQHandler(
+    int IRQ,
+    PM_irqHandler ih)
+{
+    int             thunkSize,PICmask,chainPrevious;
+    ulong           offsetAdjust;
+    _PM_IRQHandle   *handle;
+
+    thunkSize = (ulong)_PM_irqISRTemplateEnd - (ulong)_PM_irqISRTemplate;
+    if ((handle = PM_malloc(sizeof(_PM_IRQHandle) + thunkSize)) == NULL)
+	return NULL;
+    handle->IRQ = IRQ;
+    handle->prevPIC = PM_inpb(0x21);
+    handle->prevPIC2 = PM_inpb(0xA1);
+    if (IRQ < 8) {
+	handle->IRQVect = (IRQ + 8);
+	PICmask = (1 << IRQ);
+	chainPrevious = ((handle->prevPIC & PICmask) == 0);
+	}
+    else {
+	handle->IRQVect = (0x60 + IRQ + 8);
+	PICmask = ((1 << IRQ) | 0x4);
+	chainPrevious = ((handle->prevPIC2 & (PICmask >> 8)) == 0);
+	}
+
+    /* Copy and setup the assembler thunk */
+    offsetAdjust = (ulong)handle->thunk - (ulong)_PM_irqISRTemplate;
+    memcpy(handle->thunk,_PM_irqISRTemplate,thunkSize);
+    *((ulong*)&handle->thunk[2]) = offsetAdjust;
+    *((ulong*)&handle->thunk[11+0]) = (ulong)ih;
+    if (chainPrevious) {
+	*((ulong*)&handle->thunk[11+4]) = handle->prevHandler.off;
+	*((ulong*)&handle->thunk[11+8]) = handle->prevHandler.sel;
+	}
+    else {
+	*((ulong*)&handle->thunk[11+4]) = 0;
+	*((ulong*)&handle->thunk[11+8]) = 0;
+	}
+    *((ulong*)&handle->thunk[11+12]) = IRQ;
+
+    /* Set the real time clock interrupt handler */
+    getISR(handle->IRQVect, &handle->prevHandler, &handle->prevRealhandler);
+    setISR(handle->IRQVect, (PM_intHandler)handle->thunk);
+
+    /* Unmask the IRQ in the PIC */
+    PM_outpb(0xA1,handle->prevPIC2 & ~(PICmask >> 8));
+    PM_outpb(0x21,handle->prevPIC & ~PICmask);
+    return handle;
+}
+
+void PMAPI PM_restoreIRQHandler(
+    PM_IRQHandle irqHandle)
+{
+    int             PICmask;
+    _PM_IRQHandle   *handle = irqHandle;
+
+    /* Restore PIC mask for the interrupt */
+    if (handle->IRQ < 8)
+	PICmask = (1 << handle->IRQ);
+    else
+	PICmask = ((1 << handle->IRQ) | 0x4);
+    PM_outpb(0xA1,(PM_inpb(0xA1) & ~(PICmask >> 8)) | (handle->prevPIC2 & (PICmask >> 8)));
+    PM_outpb(0x21,(PM_inpb(0x21) & ~PICmask) | (handle->prevPIC & PICmask));
+
+    /* Restore the interrupt vector */
+    restoreISR(handle->IRQVect, handle->prevHandler, handle->prevRealhandler);
+
+    /* Finally free the thunk */
+    PM_free(handle);
+}
+
+void PMAPI PM_setKeyHandler(PM_intHandler kh)
+{
+    getISR(0x9, &_PM_prevKey, &_PM_prevRealKey);
+    _PM_keyHandler = kh;
+    setISR(0x9, _PM_keyISR);
+}
+
+void PMAPI PM_restoreKeyHandler(void)
+{
+    if (_PM_keyHandler) {
+	restoreISR(0x9, _PM_prevKey, _PM_prevRealKey);
+	_PM_keyHandler = NULL;
+	}
+}
+
+void PMAPI PM_setKey15Handler(PM_key15Handler kh)
+{
+    getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15);
+    _PM_key15Handler = kh;
+    setISR(0x15, _PM_key15ISR);
+}
+
+void PMAPI PM_restoreKey15Handler(void)
+{
+    if (_PM_key15Handler) {
+	restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15);
+	_PM_key15Handler = NULL;
+	}
+}
+
+/* Real mode Ctrl-C and Ctrl-Break handler. This handler simply sets a
+ * flag in the real mode code segment and exit. We save the location
+ * of this flag in real mode memory so that both the real mode and
+ * protected mode code will be modifying the same flags.
+ */
+
+#ifndef DOS4GW
+static uchar ctrlHandler[] = {
+    0x00,0x00,0x00,0x00,            /*  ctrlBFlag                       */
+    0x66,0x2E,0xC7,0x06,0x00,0x00,
+    0x01,0x00,0x00,0x00,            /*  mov     [cs:ctrlBFlag],1        */
+    0xCF,                           /*  iretf                           */
+    };
+#endif
+
+void PMAPI PM_installAltBreakHandler(PM_breakHandler bh)
+{
+#ifndef DOS4GW
+    uint    rseg,roff;
+#else
+    static int  ctrlCFlag,ctrlBFlag;
+
+    _PM_ctrlCPtr = (uchar*)&ctrlCFlag;
+    _PM_ctrlBPtr = (uchar*)&ctrlBFlag;
+#endif
+
+    getISR(0x1B, &_PM_prevBreak, &prevRealBreak);
+    getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC);
+    _PM_breakHandler = bh;
+    setISR(0x1B, _PM_breakISR);
+    setISR(0x23, _PM_ctrlCISR);
+
+#ifndef DOS4GW
+    /* Hook the real mode vectors for these handlers, as these are not
+     * normally reflected by the DPMI server up to protected mode
+     */
+    _PM_ctrlBPtr = PM_allocRealSeg(sizeof(ctrlHandler)*2, &rseg, &roff);
+    memcpy(_PM_ctrlBPtr,ctrlHandler,sizeof(ctrlHandler));
+    memcpy(_PM_ctrlBPtr+sizeof(ctrlHandler),ctrlHandler,sizeof(ctrlHandler));
+    _PM_ctrlCPtr = _PM_ctrlBPtr + sizeof(ctrlHandler);
+    _PM_setRMvect(0x1B,((long)rseg << 16) | (roff+4));
+    _PM_setRMvect(0x23,((long)rseg << 16) | (roff+sizeof(ctrlHandler)+4));
+#endif
+}
+
+void PMAPI PM_installBreakHandler(void)
+{
+    PM_installAltBreakHandler(NULL);
+}
+
+void PMAPI PM_restoreBreakHandler(void)
+{
+    if (_PM_prevBreak.sel) {
+	restoreISR(0x1B, _PM_prevBreak, prevRealBreak);
+	restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC);
+	_PM_prevBreak.sel = 0;
+	_PM_breakHandler = NULL;
+#ifndef DOS4GW
+	PM_freeRealSeg(_PM_ctrlBPtr);
+#endif
+	}
+}
+
+/* Real mode Critical Error handler. This handler simply saves the AX and
+ * DI values in the real mode code segment and exits. We save the location
+ * of this flag in real mode memory so that both the real mode and
+ * protected mode code will be modifying the same flags.
+ */
+
+#ifndef DOS4GW
+static uchar criticalHandler[] = {
+    0x00,0x00,                      /*  axCode                          */
+    0x00,0x00,                      /*  diCode                          */
+    0x2E,0xA3,0x00,0x00,            /*  mov     [cs:axCode],ax          */
+    0x2E,0x89,0x3E,0x02,0x00,       /*  mov     [cs:diCode],di          */
+    0xB8,0x03,0x00,                 /*  mov     ax,3                    */
+    0xCF,                           /*  iretf                           */
+    };
+#endif
+
+void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch)
+{
+#ifndef DOS4GW
+    uint    rseg,roff;
+#else
+    static  short   critBuf[2];
+
+    _PM_critPtr = (uchar*)critBuf;
+#endif
+
+    getISR(0x24, &_PM_prevCritical, &prevRealCritical);
+    _PM_critHandler = ch;
+    setISR(0x24, _PM_criticalISR);
+
+#ifndef DOS4GW
+    /* Hook the real mode vector, as this is not normally reflected by the
+     * DPMI server up to protected mode.
+     */
+    _PM_critPtr = PM_allocRealSeg(sizeof(criticalHandler)*2, &rseg, &roff);
+    memcpy(_PM_critPtr,criticalHandler,sizeof(criticalHandler));
+    _PM_setRMvect(0x24,((long)rseg << 16) | (roff+4));
+#endif
+}
+
+void PMAPI PM_installCriticalHandler(void)
+{
+    PM_installAltCriticalHandler(NULL);
+}
+
+void PMAPI PM_restoreCriticalHandler(void)
+{
+    if (_PM_prevCritical.sel) {
+	restoreISR(0x24, _PM_prevCritical, prevRealCritical);
+	PM_freeRealSeg(_PM_critPtr);
+	_PM_prevCritical.sel = 0;
+	_PM_critHandler = NULL;
+	}
+}
+
+int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len);
+}
+
+int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len);
+}
+
+int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.cs),len);
+}
+
+int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.cs),len);
+}
+
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c
new file mode 100755
index 0000000..c3e9b6c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c
@@ -0,0 +1,251 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit DOS
+*
+* Description:  Main C module for the VFlat framebuffer routines. The page
+*               fault handler is always installed to handle up to a 4Mb
+*               framebuffer with a window size of 4Kb or 64Kb in size.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include <stdlib.h>
+#include <dos.h>
+
+/*-------------------------------------------------------------------------*/
+/* DOS4G/W, PMODE/W and CauseWay support.                                  */
+/*-------------------------------------------------------------------------*/
+
+#if defined(DOS4GW)
+
+#define VFLAT_START_ADDR    0xF0000000U
+#define VFLAT_END_ADDR      0xF03FFFFFU
+#define VFLAT_LIMIT         (VFLAT_END_ADDR - VFLAT_START_ADDR)
+#define PAGE_PRESENT        1
+#define PAGE_NOTPRESENT     0
+#define PAGE_READ           0
+#define PAGE_WRITE          2
+
+PRIVATE ibool   installed = false;
+PRIVATE ibool   haveDPMI = false;
+PUBLIC  ibool   _ASMAPI VF_haveCauseWay = false;
+PUBLIC  uchar * _ASMAPI VF_zeroPtr = NULL;
+
+/* Low level assembler code */
+
+int     _ASMAPI InitPaging(void);
+void    _ASMAPI ClosePaging(void);
+void    _ASMAPI MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags);
+void    _ASMAPI InstallFaultHandler(ulong baseAddr,int bankSize);
+void    _ASMAPI RemoveFaultHandler(void);
+void    _ASMAPI InstallBankFunc(int codeLen,void *bankFunc);
+
+void * _ASMAPI VF_malloc(uint size)
+{ return PM_malloc(size); }
+
+void _ASMAPI VF_free(void *p)
+{ PM_free(p); }
+
+PRIVATE ibool CheckDPMI(void)
+/****************************************************************************
+*
+* Function:     CheckDPMI
+* Returns:      True if we are running under DPMI
+*
+****************************************************************************/
+{
+    PMREGS  regs;
+
+    if (haveDPMI)
+	return true;
+
+    /* Check if we are running under DPMI in which case we will not be
+     * able to install our page fault handlers. We can however use the
+     * DVA.386 or VFLATD.386 virtual device drivers if they are present.
+     */
+    regs.x.ax = 0xFF00;
+    PM_int386(0x31,&regs,&regs);
+    if (!regs.x.cflag && (regs.e.edi & 8))
+	return (haveDPMI = true);
+    return false;
+}
+
+ibool PMAPI VF_available(void)
+/****************************************************************************
+*
+* Function:     VF_available
+* Returns:      True if virtual buffer is available, false if not.
+*
+****************************************************************************/
+{
+    if (!VF_zeroPtr)
+	VF_zeroPtr = PM_mapPhysicalAddr(0,0xFFFFFFFF,true);
+    if (CheckDPMI())
+	return false;
+
+    /* Standard DOS4GW, PMODE/W and Causeway */
+    if (InitPaging() == -1)
+	return false;
+    ClosePaging();
+    return true;
+}
+
+void * PMAPI InitDPMI(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+/****************************************************************************
+*
+* Function:     InitDOS4GW
+* Parameters:   baseAddr    - Base address of framebuffer bank window
+*               bankSize    - Physical size of banks in Kb (4 or 64)
+*               codeLen     - Length of 32 bit bank switch function
+*               bankFunc    - Pointer to protected mode bank function
+* Returns:      Near pointer to virtual framebuffer, or NULL on failure.
+*
+* Description:  Installs the virtual linear framebuffer handling for
+*               DPMI environments. This requires the DVA.386 or VFLATD.386
+*               virtual device drivers to be installed and functioning.
+*
+****************************************************************************/
+{
+    (void)baseAddr;
+    (void)bankSize;
+    (void)codeLen;
+    (void)bankFunc;
+    return NULL;
+}
+
+void * PMAPI InitDOS4GW(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+/****************************************************************************
+*
+* Function:     InitDOS4GW
+* Parameters:   baseAddr    - Base address of framebuffer bank window
+*               bankSize    - Physical size of banks in Kb (4 or 64)
+*               codeLen     - Length of 32 bit bank switch function
+*               bankFunc    - Pointer to protected mode bank function
+* Returns:      Near pointer to virtual framebuffer, or NULL on failure.
+*
+* Description:  Installs the virtual linear framebuffer handling for
+*               the DOS4GW extender.
+*
+****************************************************************************/
+{
+    int     i;
+
+    if (InitPaging() == -1)
+	return NULL;            /* Cannot do hardware paging!       */
+
+    /* Map 4MB of video memory into linear address space (read/write) */
+    if (bankSize == 64) {
+	for (i = 0; i < 64; i++) {
+	    MapPhysical2Linear(baseAddr,VFLAT_START_ADDR+(i<<16),16,
+		PAGE_WRITE | PAGE_NOTPRESENT);
+	    }
+	}
+    else {
+	for (i = 0; i < 1024; i++) {
+	    MapPhysical2Linear(baseAddr,VFLAT_START_ADDR+(i<<12),1,
+		PAGE_WRITE | PAGE_NOTPRESENT);
+	    }
+	}
+
+    /* Install our page fault handler and banks switch function */
+    InstallFaultHandler(baseAddr,bankSize);
+    InstallBankFunc(codeLen,bankFunc);
+    installed = true;
+    return (void*)VFLAT_START_ADDR;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+/****************************************************************************
+*
+* Function:     VF_init
+* Parameters:   baseAddr    - Base address of framebuffer bank window
+*               bankSize    - Physical size of banks in Kb (4 or 64)
+*               codeLen     - Length of 32 bit bank switch function
+*               bankFunc    - Pointer to protected mode bank function
+* Returns:      Near pointer to virtual framebuffer, or NULL on failure.
+*
+* Description:  Installs the virtual linear framebuffer handling.
+*
+****************************************************************************/
+{
+    if (installed)
+	return (void*)VFLAT_START_ADDR;
+    if (codeLen > 100)
+	return NULL;                /* Bank function is too large!      */
+    if (!VF_zeroPtr)
+	VF_zeroPtr = PM_mapPhysicalAddr(0,0xFFFFFFFF,true);
+    if (CheckDPMI())
+	return InitDPMI(baseAddr,bankSize,codeLen,bankFunc);
+    return InitDOS4GW(baseAddr,bankSize,codeLen,bankFunc);
+}
+
+void PMAPI VF_exit(void)
+/****************************************************************************
+*
+* Function:     VF_exit
+*
+* Description:  Closes down the virtual framebuffer services and
+*               restores the previous page fault handler.
+*
+****************************************************************************/
+{
+    if (installed) {
+	if (haveDPMI) {
+	    /* DPMI support */
+	    }
+	else {
+	    /* Standard DOS4GW and PMODE/W support */
+	    RemoveFaultHandler();
+	    ClosePaging();
+	    }
+	installed = false;
+	}
+}
+
+/*-------------------------------------------------------------------------*/
+/* Support mapped out for other compilers.                                 */
+/*-------------------------------------------------------------------------*/
+
+#else
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    (void)baseAddr;
+    (void)bankSize;
+    (void)codeLen;
+    (void)bankFunc;
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
+
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c
new file mode 100755
index 0000000..53ab16c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c
@@ -0,0 +1,111 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  MSDOS
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+
+/*---------------------------- Global variables ---------------------------*/
+
+uchar * _VARAPI _ZTimerBIOSPtr;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* External assembler functions */
+
+void    _ASMAPI LZ_timerOn(void);
+ulong   _ASMAPI LZ_timerLap(void);
+void    _ASMAPI LZ_timerOff(void);
+ulong   _ASMAPI LZ_timerCount(void);
+void    _ASMAPI LZ_disable(void);
+void    _ASMAPI LZ_enable(void);
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+void __ZTimerInit(void)
+{
+    _ZTimerBIOSPtr = PM_getBIOSPointer();
+}
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOn(tm)     LZ_timerOn()
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerLap(tm)        LZ_timerLap()
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOff(tm)        LZ_timerOff()
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerCount(tm)  LZ_timerCount()
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION     54925
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer value from the BIOS timer tick.
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{
+    ulong   ticks;
+    LZ_disable();            /* Turn of interrupts               */
+    ticks = PM_getLong(_ZTimerBIOSPtr+0x6C);
+    LZ_enable();             /* Turn on interrupts again         */
+    return ticks;
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{
+    if (finish < start)
+	finish += 1573040L;         /* Number of ticks in 24 hours      */
+    return finish - start;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/event.c b/board/MAI/bios_emulator/scitech/src/pm/event.c
new file mode 100755
index 0000000..b6f4586
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/event.c
@@ -0,0 +1,1115 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Main implementation for the SciTech cross platform event
+*               library. This module contains all the generic cross platform
+*               code, and pulls in modules specific to each target OS
+*               environment.
+*
+****************************************************************************/
+
+#include "event.h"
+#include "pmapi.h"
+#include <time.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include "oshdr.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+#define EVENTQSIZE      100     /* Number of events in event queue      */
+#define JOY_NUM_AXES    4       /* Number of joystick axes supported    */
+
+static struct {
+    int         mx,my;              /* Current mouse position           */
+    int         head;               /* Head of event queue              */
+    int         tail;               /* Tail of event queue              */
+    int         freeHead;           /* Head of free list                */
+    int         count;              /* No. of items currently in queue  */
+    event_t     evtq[EVENTQSIZE];   /* The queue structure itself       */
+    int         oldMove;            /* Previous movement event          */
+    int         oldKey;             /* Previous key repeat event        */
+    int         oldJoyMove;         /* Previous joystick movement event */
+    int         joyMask;            /* Mask of joystick axes present    */
+    int         joyMin[JOY_NUM_AXES];
+    int         joyCenter[JOY_NUM_AXES];
+    int         joyMax[JOY_NUM_AXES];
+    int         joyPrev[JOY_NUM_AXES];
+    int         joyButState;
+    ulong       doubleClick;
+    ulong       autoRepeat;
+    ulong       autoDelay;
+    ulong       autoTicks;
+    ulong       doubleClickThresh;
+    ulong       firstAuto;
+    int         autoMouse_x;
+    int         autoMouse_y;
+    event_t     downMouse;
+    ulong       keyModifiers;       /* Current keyboard modifiers       */
+    uchar       keyTable[128];      /* Table of key up/down flags       */
+    ibool       allowLEDS;          /* True if LEDS should change       */
+    _EVT_userEventFilter    userEventCallback;
+    _EVT_mouseMoveHandler   mouseMove;
+    _EVT_heartBeatCallback  heartBeat;
+    void                    *heartBeatParams;
+    codepage_t              *codePage;
+    } EVT;
+
+/*---------------------------- Implementation -----------------------------*/
+
+#if defined(__REALDOS__) || defined(__SMX32__)
+/* {secret} */
+void EVTAPI _EVT_cCodeStart(void) {}
+#endif
+
+/* External assembler functions */
+
+int EVTAPI _EVT_readJoyAxis(int mask,int *axis);
+int EVTAPI _EVT_readJoyButtons(void);
+
+/* Forward declaration */
+
+ulong _EVT_getTicks(void);
+
+/****************************************************************************
+PARAMETERS:
+evt - Event to add to the event queue
+
+REMARKS:
+Adds an event to the event queue by tacking it onto the tail of the event
+queue. This routine assumes that at least one spot is available on the
+freeList for the event to be inserted.
+
+NOTE:   Interrupts MUST be OFF while this routine is called to ensure we have
+	mutually exclusive access to our internal data structures for
+	interrupt driven systems (like under DOS).
+****************************************************************************/
+static void addEvent(
+    event_t *evt)
+{
+    int evtID;
+
+    /* Check for mouse double click events */
+    if (evt->what & EVT_MOUSEEVT) {
+	EVT.autoMouse_x = evt->where_x;
+	EVT.autoMouse_y = evt->where_y;
+	if ((evt->what & EVT_MOUSEDOWN) && !(evt->message & EVT_DBLCLICK)) {
+	    /* Determine if the last mouse event was a double click event */
+	    uint diff_x = ABS(evt->where_x - EVT.downMouse.where_x);
+	    uint diff_y = ABS(evt->where_y - EVT.downMouse.where_y);
+	    if ((evt->message == EVT.downMouse.message)
+		&& ((evt->when - EVT.downMouse.when) <= EVT.doubleClick)
+		&& (diff_x <= EVT.doubleClickThresh)
+		&& (diff_y <= EVT.doubleClickThresh)) {
+		evt->message |= EVT_DBLCLICK;
+		EVT.downMouse = *evt;
+		EVT.downMouse.when = 0;
+		}
+	    else
+		EVT.downMouse = *evt;
+	    EVT.autoTicks = _EVT_getTicks();
+	    }
+	else if (evt->what & EVT_MOUSEUP) {
+	    EVT.downMouse.what = EVT_NULLEVT;
+	    EVT.firstAuto = true;
+	    }
+	}
+
+    /* Call user supplied callback to modify the event if desired */
+    if (EVT.userEventCallback) {
+	if (!EVT.userEventCallback(evt))
+	    return;
+	}
+
+    /* Get spot to place the event from the free list */
+    evtID = EVT.freeHead;
+    EVT.freeHead = EVT.evtq[EVT.freeHead].next;
+
+    /* Add to the EVT.tail of the event queue   */
+    evt->next = -1;
+    evt->prev = EVT.tail;
+    if (EVT.tail != -1)
+	EVT.evtq[EVT.tail].next = evtID;
+    else
+	EVT.head = evtID;
+    EVT.tail = evtID;
+    EVT.evtq[evtID] = *evt;
+    EVT.count++;
+}
+
+/****************************************************************************
+REMARKS:
+Internal function to initialise the event queue to the empty state.
+****************************************************************************/
+static void initEventQueue(void)
+{
+    int i;
+
+    /* Build free list, and initialize global data structures */
+    for (i = 0; i < EVENTQSIZE; i++)
+	EVT.evtq[i].next = i+1;
+    EVT.evtq[EVENTQSIZE-1].next = -1;       /* Terminate list           */
+    EVT.count = EVT.freeHead = 0;
+    EVT.head = EVT.tail = -1;
+    EVT.oldMove = -1;
+    EVT.oldKey = -1;
+    EVT.oldJoyMove = -1;
+    EVT.joyButState = 0;
+    EVT.mx = EVT.my = 0;
+    EVT.keyModifiers = 0;
+    EVT.allowLEDS = true;
+
+    /* Set default values for mouse double click and mouse auto events */
+    EVT.doubleClick = 440;
+    EVT.autoRepeat = 55;
+    EVT.autoDelay = 330;
+    EVT.autoTicks = 0;
+    EVT.doubleClickThresh = 5;
+    EVT.firstAuto = true;
+    EVT.autoMouse_x = EVT.autoMouse_y = 0;
+    memset(&EVT.downMouse,0,sizeof(EVT.downMouse));
+
+    /* Setup default pointers for event library */
+    EVT.userEventCallback = NULL;
+    EVT.codePage = &_CP_US_English;
+
+    /* Initialise the joystick module and do basic calibration (which assumes
+     * the joystick is centered.
+     */
+    EVT.joyMask = EVT_joyIsPresent();
+}
+
+#if defined(NEED_SCALE_JOY_AXIS) || !defined(USE_OS_JOYSTICK)
+/****************************************************************************
+REMARKS:
+This function scales a joystick axis value to normalised form.
+****************************************************************************/
+static int scaleJoyAxis(
+    int raw,
+    int axis)
+{
+    int scaled,range;
+
+    /* Make sure the joystick is calibrated properly */
+    if (EVT.joyCenter[axis] - EVT.joyMin[axis] < 5)
+	return raw;
+    if (EVT.joyMax[axis] - EVT.joyCenter[axis] < 5)
+	return raw;
+
+    /* Now scale the coordinates to -128 to 127 */
+    raw -= EVT.joyCenter[axis];
+    if (raw < 0)
+	range = EVT.joyCenter[axis]-EVT.joyMin[axis];
+    else
+	range = EVT.joyMax[axis]-EVT.joyCenter[axis];
+    scaled = (raw * 128) / range;
+    if (scaled < -128)
+	scaled = -128;
+    if (scaled > 127)
+	scaled = 127;
+    return scaled;
+}
+#endif
+
+#if     defined(__SMX32__)
+#include "smx/event.c"
+#elif   defined(__RTTARGET__)
+#include "rttarget/event.c"
+#elif   defined(__REALDOS__)
+#include "dos/event.c"
+#elif   defined(__WINDOWS32__)
+#include "win32/event.c"
+#elif   defined(__OS2__)
+#if     defined(__OS2_PM__)
+#include "os2pm/event.c"
+#else
+#include "os2/event.c"
+#endif
+#elif   defined(__LINUX__)
+#if     defined(__USE_X11__)
+#include "x11/event.c"
+#else
+#include "linux/event.c"
+#endif
+#elif   defined(__QNX__)
+#if     defined(__USE_PHOTON__)
+#include "photon/event.c"
+#elif   defined(__USE_X11__)
+#include "x11/event.c"
+#else
+#include "qnx/event.c"
+#endif
+#elif   defined(__BEOS__)
+#include "beos/event.c"
+#else
+#error  Event library not ported to this platform yet!
+#endif
+
+/*------------------------ Public interface routines ----------------------*/
+
+/* If USE_OS_JOYSTICK is defined, the OS specific libraries will implement
+ * the joystick code rather than using the generic OS portable version.
+ */
+
+#ifndef USE_OS_JOYSTICK
+/****************************************************************************
+DESCRIPTION:
+Returns the mask indicating what joystick axes are attached.
+
+HEADER:
+event.h
+
+REMARKS:
+This function is used to detect the attached joysticks, and determine
+what axes are present and functioning. This function will re-detect any
+attached joysticks when it is called, so if the user forgot to attach
+the joystick when the application started, you can call this function to
+re-detect any newly attached joysticks.
+
+SEE ALSO:
+EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent
+****************************************************************************/
+int EVTAPI EVT_joyIsPresent(void)
+{
+    int mask,i;
+
+    memset(EVT.joyMin,0,sizeof(EVT.joyMin));
+    memset(EVT.joyCenter,0,sizeof(EVT.joyCenter));
+    memset(EVT.joyMax,0,sizeof(EVT.joyMax));
+    memset(EVT.joyPrev,0,sizeof(EVT.joyPrev));
+    EVT.joyButState = 0;
+#ifdef __LINUX__
+    PM_init();
+#endif
+    mask = _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter);
+    if (mask) {
+	for (i = 0; i < JOY_NUM_AXES; i++)
+	    EVT.joyMax[i] = EVT.joyCenter[i]*2;
+	}
+    return mask;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Polls the joystick for position and button information.
+
+HEADER:
+event.h
+
+REMARKS:
+This routine is used to poll analogue joysticks for button and position
+information. It should be called once for each main loop of the user
+application, just before processing all pending events via EVT_getNext.
+All information polled from the joystick will be posted to the event
+queue for later retrieval.
+
+Note:   Most analogue joysticks will provide readings that change even
+	though the joystick has not moved. Hence if you call this routine
+	you will likely get an EVT_JOYMOVE event every time through your
+	event loop.
+
+SEE ALSO:
+EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight,
+EVT_joySetCenter, EVT_joyIsPresent
+****************************************************************************/
+void EVTAPI EVT_pollJoystick(void)
+{
+    event_t evt;
+    int     i,axis[JOY_NUM_AXES],newButState,mask,moved,ps;
+
+    if (EVT.joyMask) {
+	/* Read joystick axes and post movement events if they have
+	 * changed since the last time we polled. Until the events are
+	 * actually flushed, we keep modifying the same joystick movement
+	 * event, so you won't get multiple movement event
+	 */
+	mask = _EVT_readJoyAxis(EVT.joyMask,axis);
+	newButState = _EVT_readJoyButtons();
+	moved = false;
+	for (i = 0; i < JOY_NUM_AXES; i++) {
+	    if (mask & (EVT_JOY_AXIS_X1 << i))
+		axis[i] = scaleJoyAxis(axis[i],i);
+	    else
+		axis[i] = EVT.joyPrev[i];
+	    if (axis[i] != EVT.joyPrev[i])
+		moved = true;
+	    }
+	if (moved) {
+	    memcpy(EVT.joyPrev,axis,sizeof(EVT.joyPrev));
+	    ps = _EVT_disableInt();
+	    if (EVT.oldJoyMove != -1) {
+		/* Modify the existing joystick movement event */
+		EVT.evtq[EVT.oldJoyMove].message = newButState;
+		EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0];
+		EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1];
+		EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2];
+		EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3];
+		}
+	    else if (EVT.count < EVENTQSIZE) {
+		/* Add a new joystick movement event */
+		EVT.oldJoyMove = EVT.freeHead;
+		memset(&evt,0,sizeof(evt));
+		evt.what = EVT_JOYMOVE;
+		evt.message = EVT.joyButState;
+		evt.where_x = EVT.joyPrev[0];
+		evt.where_y = EVT.joyPrev[1];
+		evt.relative_x = EVT.joyPrev[2];
+		evt.relative_y = EVT.joyPrev[3];
+		addEvent(&evt);
+		}
+	    _EVT_restoreInt(ps);
+	    }
+
+	/* Read the joystick buttons, and post events to reflect the change
+	 * in state for the joystick buttons.
+	 */
+	if (newButState != EVT.joyButState) {
+	    if (EVT.count < EVENTQSIZE) {
+		/* Add a new joystick click event */
+		ps = _EVT_disableInt();
+		memset(&evt,0,sizeof(evt));
+		evt.what = EVT_JOYCLICK;
+		evt.message = newButState;
+		EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0];
+		EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1];
+		EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2];
+		EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3];
+		addEvent(&evt);
+		_EVT_restoreInt(ps);
+		}
+	    EVT.joyButState = newButState;
+	    }
+	}
+}
+
+/****************************************************************************
+DESCRIPTION:
+Calibrates the joystick upper left position
+
+HEADER:
+event.h
+
+REMARKS:
+This function can be used to zero in on better joystick calibration factors,
+which may work better than the default simplistic calibration (which assumes
+the joystick is centered when the event library is initialised).
+To use this function, ask the user to hold the stick in the upper left
+position and then have them press a key or button. and then call this
+function. This function will then read the joystick and update the
+calibration factors.
+
+Usually, assuming that the stick was centered when the event library was
+initialized, you really only need to call EVT_joySetLowerRight since the
+upper left position is usually always 0,0 on most joysticks. However, the
+safest procedure is to call all three calibration functions.
+
+SEE ALSO:
+EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent
+****************************************************************************/
+void EVTAPI EVT_joySetUpperLeft(void)
+{
+    _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMin);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Calibrates the joystick lower right position
+
+HEADER:
+event.h
+
+REMARKS:
+This function can be used to zero in on better joystick calibration factors,
+which may work better than the default simplistic calibration (which assumes
+the joystick is centered when the event library is initialised).
+To use this function, ask the user to hold the stick in the lower right
+position and then have them press a key or button. and then call this
+function. This function will then read the joystick and update the
+calibration factors.
+
+Usually, assuming that the stick was centered when the event library was
+initialized, you really only need to call EVT_joySetLowerRight since the
+upper left position is usually always 0,0 on most joysticks. However, the
+safest procedure is to call all three calibration functions.
+
+SEE ALSO:
+EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent
+****************************************************************************/
+void EVTAPI EVT_joySetLowerRight(void)
+{
+    _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMax);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Calibrates the joystick center position
+
+HEADER:
+event.h
+
+REMARKS:
+This function can be used to zero in on better joystick calibration factors,
+which may work better than the default simplistic calibration (which assumes
+the joystick is centered when the event library is initialised).
+To use this function, ask the user to hold the stick in the center
+position and then have them press a key or button. and then call this
+function. This function will then read the joystick and update the
+calibration factors.
+
+Usually, assuming that the stick was centered when the event library was
+initialized, you really only need to call EVT_joySetLowerRight since the
+upper left position is usually always 0,0 on most joysticks. However, the
+safest procedure is to call all three calibration functions.
+
+SEE ALSO:
+EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter
+****************************************************************************/
+void EVTAPI EVT_joySetCenter(void)
+{
+    _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter);
+}
+#endif
+
+/****************************************************************************
+DESCRIPTION:
+Posts a user defined event to the event queue
+
+HEADER:
+event.h
+
+RETURNS:
+True if event was posted, false if event queue is full.
+
+PARAMETERS:
+what        - Type code for message to post
+message     - Event specific message to post
+modifiers   - Event specific modifier flags to post
+
+REMARKS:
+This routine is used to post user defined events to the event queue.
+
+SEE ALSO:
+EVT_flush, EVT_getNext, EVT_peekNext, EVT_halt
+****************************************************************************/
+ibool EVTAPI EVT_post(
+    ulong which,
+    ulong what,
+    ulong message,
+    ulong modifiers)
+{
+    event_t evt;
+    uint    ps;
+
+    if (EVT.count < EVENTQSIZE) {
+	/* Save information in event record */
+	ps = _EVT_disableInt();
+	evt.which = which;
+	evt.when = _EVT_getTicks();
+	evt.what = what;
+	evt.message = message;
+	evt.modifiers = modifiers;
+	addEvent(&evt);             /* Add to EVT.tail of event queue   */
+	_EVT_restoreInt(ps);
+	return true;
+	}
+    else
+	return false;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Flushes all events of a specified type from the event queue.
+
+PARAMETERS:
+mask    - Mask specifying the types of events that should be removed
+
+HEADER:
+event.h
+
+REMARKS:
+Flushes (removes) all pending events of the specified type from the event
+queue. You may combine the masks for different event types with a simple
+logical OR.
+
+SEE ALSO:
+EVT_getNext, EVT_halt, EVT_peekNext
+****************************************************************************/
+void EVTAPI EVT_flush(
+    ulong mask)
+{
+    event_t evt;
+
+    do {                            /* Flush all events */
+	EVT_getNext(&evt,mask);
+	} while (evt.what != EVT_NULLEVT);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Halts until and event of the specified type is recieved.
+
+HEADER:
+event.h
+
+PARAMETERS:
+evt     - Pointer to
+mask    - Mask specifying the types of events that should be removed
+
+REMARKS:
+This functions halts exceution until an event of the specified type is
+recieved into the event queue. It does not flush the event queue of events
+before performing the busy loop. However this function does throw away
+any events other than the ones you have requested via the event mask, to
+avoid the event queue filling up with unwanted events (like EVT_KEYUP or
+EVT_MOUSEMOVE events).
+
+SEE ALSO:
+EVT_getNext, EVT_flush, EVT_peekNext
+****************************************************************************/
+void EVTAPI EVT_halt(
+    event_t *evt,
+    ulong mask)
+{
+    do {                            /* Wait for an event    */
+	if (mask & (EVT_JOYEVT))
+	    EVT_pollJoystick();
+	EVT_getNext(evt,EVT_EVERYEVT);
+	} while (!(evt->what & mask));
+}
+
+/****************************************************************************
+DESCRIPTION:
+Peeks at the next pending event in the event queue.
+
+HEADER:
+event.h
+
+RETURNS:
+True if an event is pending, false if not.
+
+PARAMETERS:
+evt     - Pointer to structure to return the event info in
+mask    - Mask specifying the types of events that should be removed
+
+REMARKS:
+Peeks at the next pending event of the specified type in the event queue. The
+mask parameter is used to specify the type of events to be peeked at, and
+can be any logical combination of any of the flags defined by the
+EVT_eventType enumeration.
+
+In contrast to EVT_getNext, the event is not removed from the event queue.
+You may combine the masks for different event types with a simple logical OR.
+
+SEE ALSO:
+EVT_flush, EVT_getNext, EVT_halt
+****************************************************************************/
+ibool EVTAPI EVT_peekNext(
+    event_t *evt,
+    ulong mask)
+{
+    int     evtID;
+    uint    ps;
+
+    if (EVT.heartBeat)
+	EVT.heartBeat(EVT.heartBeatParams);
+    _EVT_pumpMessages();                /* Pump all messages into queue */
+    EVT.mouseMove(EVT.mx,EVT.my);       /* Move the mouse cursor        */
+    evt->what = EVT_NULLEVT;            /* Default to null event        */
+    if (EVT.count) {
+	/* It is possible that an event be posted while we are trying
+	 * to access the event queue. This would create problems since
+	 * we may end up with invalid data for our event queue pointers. To
+	 * alleviate this, all interrupts are suspended while we manipulate
+	 * our pointers.
+	 */
+	ps = _EVT_disableInt();             /* disable interrupts       */
+	for (evtID = EVT.head; evtID != -1; evtID = EVT.evtq[evtID].next) {
+	    if (EVT.evtq[evtID].what & mask)
+		break;                      /* Found an event           */
+	    }
+	if (evtID == -1) {
+	    _EVT_restoreInt(ps);
+	    return false;                   /* Event was not found      */
+	    }
+	*evt = EVT.evtq[evtID];                 /* Return the event         */
+	_EVT_restoreInt(ps);
+	if (evt->what & EVT_KEYEVT)
+	    _EVT_maskKeyCode(evt);
+	}
+    return evt->what != EVT_NULLEVT;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Retrieves the next pending event from the event queue.
+
+PARAMETERS:
+evt     - Pointer to structure to return the event info in
+mask    - Mask specifying the types of events that should be removed
+
+HEADER:
+event.h
+
+RETURNS:
+True if an event was pending, false if not.
+
+REMARKS:
+Retrieves the next pending event from the event queue, and stores it in a
+event_t structure. The mask parameter is used to specify the type of events
+to be removed, and can be any logical combination of any of the flags defined
+by the EVT_eventType enumeration.
+
+The what field of the event contains the event code of the event that was
+extracted. All application specific events should begin with the EVT_USEREVT
+code and build from there. Since the event code is stored in an integer,
+there is a maximum of 32 different event codes that can be distinguished.
+You can store extra information about the event in the message field to
+distinguish between events of the same class (for instance the button used in
+a EVT_MOUSEDOWN event).
+
+If an event of the specified type was not in the event queue, the what field
+of the event will be set to NULLEVT, and the return value will return false.
+
+Note:   You should /always/ use the EVT_EVERYEVT mask for extracting events
+	from your main event loop handler. Using a mask for only a specific
+	type of event for long periods of time will cause the event queue to
+	fill up with events of the type you are ignoring, eventually causing
+	the application to hang when the event queue becomes full.
+
+SEE ALSO:
+EVT_flush, EVT_halt, EVT_peekNext
+****************************************************************************/
+ibool EVTAPI EVT_getNext(
+    event_t *evt,
+    ulong mask)
+{
+    int     evtID,next,prev;
+    uint    ps;
+
+    if (EVT.heartBeat)
+	EVT.heartBeat(EVT.heartBeatParams);
+    _EVT_pumpMessages();                /* Pump all messages into queue */
+    EVT.mouseMove(EVT.mx,EVT.my);       /* Move the mouse cursor        */
+    evt->what = EVT_NULLEVT;            /* Default to null event        */
+    if (EVT.count) {
+	/* It is possible that an event be posted while we are trying
+	 * to access the event queue. This would create problems since
+	 * we may end up with invalid data for our event queue pointers. To
+	 * alleviate this, all interrupts are suspended while we manipulate
+	 * our pointers.
+	 */
+	ps = _EVT_disableInt();             /* disable interrupts       */
+	for (evtID = EVT.head; evtID != -1; evtID = EVT.evtq[evtID].next) {
+	    if (EVT.evtq[evtID].what & mask)
+		break;                      /* Found an event           */
+	    }
+	if (evtID == -1) {
+	    _EVT_restoreInt(ps);
+	    return false;                   /* Event was not found      */
+	    }
+	next = EVT.evtq[evtID].next;
+	prev = EVT.evtq[evtID].prev;
+	if (prev != -1)
+	    EVT.evtq[prev].next = next;
+	else
+	    EVT.head = next;
+	if (next != -1)
+	    EVT.evtq[next].prev = prev;
+	else
+	    EVT.tail = prev;
+	*evt = EVT.evtq[evtID];                 /* Return the event         */
+	EVT.evtq[evtID].next = EVT.freeHead;        /* and return to free list  */
+	EVT.freeHead = evtID;
+	EVT.count--;
+	if (evt->what == EVT_MOUSEMOVE)
+	    EVT.oldMove = -1;
+	if (evt->what == EVT_KEYREPEAT)
+	    EVT.oldKey = -1;
+	if (evt->what == EVT_JOYMOVE)
+	    EVT.oldJoyMove = -1;
+	_EVT_restoreInt(ps);                /* enable interrupts        */
+	if (evt->what & EVT_KEYEVT)
+	    _EVT_maskKeyCode(evt);
+	}
+
+    /* If there is no event pending, check if we should generate an auto
+     * mouse down event if the mouse is still currently down.
+     */
+    if (evt->what == EVT_NULLEVT && EVT.autoRepeat && (mask & EVT_MOUSEAUTO) && (EVT.downMouse.what & EVT_MOUSEDOWN)) {
+	ulong ticks = _EVT_getTicks();
+	if ((ticks - EVT.autoTicks) >= (EVT.autoRepeat + (EVT.firstAuto ? EVT.autoDelay : 0))) {
+	    evt->what = EVT_MOUSEAUTO;
+	    evt->message = EVT.downMouse.message;
+	    evt->modifiers = EVT.downMouse.modifiers;
+	    evt->where_x = EVT.autoMouse_x;
+	    evt->where_y = EVT.autoMouse_y;
+	    evt->relative_x = 0;
+	    evt->relative_y = 0;
+	    EVT.autoTicks = evt->when = ticks;
+	    EVT.firstAuto = false;
+	    }
+	}
+    return evt->what != EVT_NULLEVT;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Installs a user supplied event filter callback for event handling.
+
+HEADER:
+event.h
+
+PARAMETERS:
+userEventFilter - Address of user supplied event filter callback
+
+REMARKS:
+This function allows the application programmer to install an event filter
+callback for event handling. Once you install your callback, the MGL
+event handling routines will call your callback with a pointer to the
+new event that will be placed into the event queue. Your callback can the
+modify the contents of the event before it is placed into the queue (for
+instance adding custom information or perhaps high precision timing
+information).
+
+If your callback returns FALSE, the event will be ignore and will not be
+posted to the event queue. You should always return true from your event
+callback unless you plan to use the events immediately that they are
+recieved.
+
+Note:   Your event callback may be called in response to a hardware
+	interrupt and will be executing in the context of the hardware
+	interrupt handler under MSDOS (ie: keyboard interrupt or mouse
+	interrupt). For this reason the code pages for the callback that
+	you register must be locked in memory with the PM_lockCodePages
+	function. You must also lock down any data pages that your function
+	needs to reference as well.
+
+Note:   You can also use this filter callback to process events at the
+	time they are activated by the user (ie: when the user hits the
+	key or moves the mouse), but make sure your code runs as fast as
+	possible as it will be executing inside the context of an interrupt
+	handler on some systems.
+
+SEE ALSO:
+EVT_getNext, EVT_peekNext
+****************************************************************************/
+void EVTAPI EVT_setUserEventFilter(
+    _EVT_userEventFilter filter)
+{
+    EVT.userEventCallback = filter;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Installs a user supplied event heartbeat callback function.
+
+HEADER:
+event.h
+
+PARAMETERS:
+callback    - Address of user supplied event heartbeat callback
+params      - Parameters to pass to the event heartbeat function
+
+REMARKS:
+This function allows the application programmer to install an event heatbeat
+function that gets called every time that EVT_getNext or EVT_peekNext
+is called. This is primarily useful for simulating text mode cursors inside
+event handling code when running in graphics modes as opposed to hardware
+text modes.
+
+SEE ALSO:
+EVT_getNext, EVT_peekNext, EVT_getHeartBeatCallback
+****************************************************************************/
+void EVTAPI EVT_setHeartBeatCallback(
+    _EVT_heartBeatCallback callback,
+    void *params)
+{
+    EVT.heartBeat = callback;
+    EVT.heartBeatParams = params;
+}
+
+
+/****************************************************************************
+DESCRIPTION:
+Returns the current user supplied event heartbeat callback function.
+
+HEADER:
+event.h
+
+PARAMETERS:
+callback    - Place to store the address of user supplied event heartbeat callback
+params      - Place to store the parameters to pass to the event heartbeat function
+
+REMARKS:
+This function retrieves the current event heatbeat function that gets called
+every time that EVT_getNext or EVT_peekNext is called.
+
+SEE ALSO:
+EVT_getNext, EVT_peekNext, EVT_setHeartBeatCallback
+****************************************************************************/
+void EVTAPI EVT_getHeartBeatCallback(
+    _EVT_heartBeatCallback *callback,
+    void **params)
+{
+    *callback = EVT.heartBeat;
+    *params = EVT.heartBeatParams;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Determines if a specified key is currently down.
+
+PARAMETERS:
+scanCode    - Scan code to test
+
+RETURNS:
+True of the specified key is currently held down.
+
+HEADER:
+event.h
+
+REMARKS:
+This function determines if a specified key is currently down at the
+time that the call is made. You simply need to pass in the scan code of
+the key that you wish to test, and the MGL will tell you if it is currently
+down or not. The MGL does this by keeping track of the up and down state
+of all the keys.
+****************************************************************************/
+ibool EVTAPI EVT_isKeyDown(
+    uchar scanCode)
+{
+    return _EVT_isKeyDown(scanCode);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Set the mouse position for the event module
+
+PARAMETERS:
+x   - X coordinate to move the mouse cursor position to
+y   - Y coordinate to move the mouse cursor position to
+
+HEADER:
+event.h
+
+REMARKS:
+This function moves the mouse cursor position for the event module to the
+specified location.
+
+SEE ALSO:
+EVT_getMousePos
+****************************************************************************/
+void EVTAPI EVT_setMousePos(
+    int x,
+    int y)
+{
+    EVT.mx = x;
+    EVT.my = y;
+    _EVT_setMousePos(&EVT.mx,&EVT.my);
+    EVT.mouseMove(EVT.mx,EVT.my);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns the current mouse cursor location.
+
+HEADER:
+event.h
+
+PARAMETERS:
+x   - Place to store value for mouse x coordinate (screen coordinates)
+y   - Place to store value for mouse y coordinate (screen coordinates)
+
+REMARKS:
+Obtains the current mouse cursor position in screen coordinates. Normally the
+mouse cursor location is tracked using the mouse movement events that are
+posted to the event queue when the mouse moves, however this routine
+provides an alternative method of polling the mouse cursor location.
+
+SEE ALSO:
+EVT_setMousePos
+****************************************************************************/
+void EVTAPI EVT_getMousePos(
+    int *x,
+    int *y)
+{
+    *x = EVT.mx;
+    *y = EVT.my;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns the currently active code page for translation of keyboard characters.
+
+HEADER:
+event.h
+
+RETURNS:
+Pointer to the currently active code page translation table.
+
+REMARKS:
+This function is returns a pointer to the currently active code page
+translation table. See EVT_setCodePage for more information.
+
+SEE ALSO:
+EVT_setCodePage
+****************************************************************************/
+codepage_t * EVTAPI EVT_getCodePage(void)
+{
+    return EVT.codePage;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Sets the currently active code page for translation of keyboard characters.
+
+HEADER:
+event.h
+
+PARAMETERS:
+page    - New code page to make active
+
+REMARKS:
+This function is used to set a new code page translation table that is used
+to translate virtual scan code values to ASCII characters for different
+keyboard configurations. The default is usually US English, although if
+possible the PM library will auto-detect the correct code page translation
+for the target OS if OS services are available to determine what type of
+keyboard is currently attached.
+
+SEE ALSO:
+EVT_getCodePage
+****************************************************************************/
+void EVTAPI EVT_setCodePage(
+    codepage_t *page)
+{
+    EVT.codePage = page;
+}
+
+/* The following contains fake C prototypes and documentation for the
+ * macro functions in the event.h header file. These exist soley so
+ * that DocJet will correctly pull in the documentation for these functions.
+ */
+#ifdef  INCLUDE_DOC_FUNCTIONS
+
+/****************************************************************************
+DESCRIPTION:
+Macro to extract the ASCII code from a message.
+
+PARAMETERS:
+message - Message to extract ASCII code from
+
+RETURNS:
+ASCII code extracted from the message.
+
+HEADER:
+event.h
+
+REMARKS:
+Macro to extract the ASCII code from the message field of the event_t
+structure. You pass the message field to the macro as the parameter and
+the ASCII code is the result, for example:
+
+    event_t EVT.myEvent;
+    uchar   code;
+    code = EVT_asciiCode(EVT.myEvent.message);
+
+SEE ALSO:
+EVT_scanCode, EVT_repeatCount
+****************************************************************************/
+uchar EVT_asciiCode(
+    ulong message);
+
+/****************************************************************************
+DESCRIPTION:
+Macro to extract the keyboard scan code from a message.
+
+HEADER:
+event.h
+
+PARAMETERS:
+message - Message to extract scan code from
+
+RETURNS:
+Keyboard scan code extracted from the message.
+
+REMARKS:
+Macro to extract the keyboard scan code from the message field of the event
+structure. You pass the message field to the macro as the parameter and
+the scan code is the result, for example:
+
+    event_t EVT.myEvent;
+    uchar   code;
+    code = EVT_scanCode(EVT.myEvent.message);
+
+NOTE:   Scan codes in the event library are not really hardware scan codes,
+	but rather virtual scan codes as generated by a low level keyboard
+	interface driver. All virtual scan code values are defined by the
+	EVT_scanCodesType enumeration, and will be identical across all
+	supports OS'es and platforms.
+
+SEE ALSO:
+EVT_asciiCode, EVT_repeatCount
+****************************************************************************/
+uchar EVT_scanCode(
+    ulong message);
+
+/****************************************************************************
+DESCRIPTION:
+Macro to extract the repeat count from a message.
+
+HEADER:
+event.h
+
+PARAMETERS:
+message - Message to extract repeat count from
+
+RETURNS:
+Repeat count extracted from the message.
+
+REMARKS:
+Macro to extract the repeat count from the message field of the event
+structure. The repeat count is the number of times that the key repeated
+before there was another keyboard event to be place in the queue, and
+allows the event handling code to avoid keyboard buffer overflow
+conditions when a single key is held down by the user. If you are processing
+a key repeat code, you will probably want to check this field to see how
+many key repeats you should process for this message.
+
+SEE ALSO:
+EVT_asciiCode, EVT_repeatCount
+****************************************************************************/
+short EVT_repeatCount(
+    ulong message);
+
+#endif  /* DOC FUNCTIONS */
+
+#if defined(__REALDOS__) || defined(__SMX32__)
+/* {secret} */
+void EVTAPI _EVT_cCodeEnd(void) {}
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c
new file mode 100755
index 0000000..e88d210
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c
@@ -0,0 +1,68 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux
+*
+* Description:  Linux specific code for the CPU detection module.
+*
+****************************************************************************/
+
+#include <ztimer.h>
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+TODO: We should implement this for Linux!
+****************************************************************************/
+#define SetMaxThreadPriority()  0
+
+/****************************************************************************
+REMARKS:
+TODO: We should implement this for Linux!
+****************************************************************************/
+#define RestoreThreadPriority(i)
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    freq->low = 1000000;
+    freq->high = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)                           \
+{                                               \
+    struct timeval tv;                          \
+    gettimeofday(&tv,NULL);                     \
+    (t)->low = tv.tv_sec*1000000 + tv.tv_usec;  \
+    (t)->high = 0;                              \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/event.c b/board/MAI/bios_emulator/scitech/src/pm/linux/event.c
new file mode 100755
index 0000000..ce38732
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/linux/event.c
@@ -0,0 +1,1360 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux
+*
+* Description:  Linux fullscreen console implementation for the SciTech
+*               cross platform event library.
+*               Portions ripped straigth from the gpm source code for mouse
+*               handling.
+*
+****************************************************************************/
+
+/*---------------------------- Global Variables ---------------------------*/
+
+extern int              _PM_console_fd;
+static ushort           keyUpMsg[256] = {0};
+static int              _EVT_mouse_fd = 0;
+static int              range_x, range_y;
+static int              opt_baud = 1200, opt_sample = 100;
+#ifdef USE_OS_JOYSTICK
+static short            *axis0 = NULL, *axis1 = NULL;
+static uchar            *buts0 = NULL, *buts1 = NULL;
+static int              joystick0_fd = 0, joystick1_fd = 0;
+static int              js_version = 0;
+#endif
+
+/* This defines the supported mouse drivers */
+
+typedef enum {
+    EVT_noMouse = -1,
+    EVT_microsoft = 0,
+    EVT_ps2,
+    EVT_mousesystems,
+    EVT_gpm,
+    EVT_MMseries,
+    EVT_logitech,
+    EVT_busmouse,
+    EVT_mouseman,
+    EVT_intellimouse,
+    EVT_intellimouse_ps2,
+    } mouse_drivers_t;
+
+static mouse_drivers_t mouse_driver = EVT_noMouse;
+static char mouse_dev[20] = "/dev/mouse";
+
+typedef struct {
+    char    *name;
+    int     flags;
+    void    (*init)(void);
+    uchar   proto[4];
+    int     packet_len;
+    int     read;
+    } mouse_info;
+
+#define STD_FLG (CREAD | CLOCAL | HUPCL)
+
+static void _EVT_mouse_init(void);
+static void _EVT_logitech_init(void);
+static void _EVT_pnpmouse_init(void);
+
+mouse_info mouse_infos[] = {
+    {"Microsoft",       CS7 | B1200 | STD_FLG,              _EVT_mouse_init,    {0x40, 0x40, 0x40, 0x00}, 3, 1},
+    {"PS2",             STD_FLG,                            NULL,               {0xc0, 0x00, 0x00, 0x00}, 3, 1},
+    {"MouseSystems",    CS8 | CSTOPB | STD_FLG,             _EVT_mouse_init,    {0xf8, 0x80, 0x00, 0x00}, 5, 5},
+    {"GPM",             CS8 | CSTOPB | STD_FLG,             NULL,               {0xf8, 0x80, 0x00, 0x00}, 5, 5},
+    {"MMSeries",        CS8 | PARENB | PARODD | STD_FLG,    _EVT_mouse_init,    {0xe0, 0x80, 0x80, 0x00}, 3, 1},
+    {"Logitech",        CS8 | CSTOPB | STD_FLG,             _EVT_logitech_init, {0xe0, 0x80, 0x80, 0x00}, 3, 3},
+    {"BusMouse",        STD_FLG,                            NULL,               {0xf8, 0x80, 0x00, 0x00}, 3, 3},
+    {"MouseMan",        CS7 | STD_FLG,                      _EVT_mouse_init,    {0x40, 0x40, 0x40, 0x00}, 3, 1},
+    {"IntelliMouse",    CS7 | STD_FLG,                      _EVT_pnpmouse_init, {0xc0, 0x40, 0xc0, 0x00}, 4, 1},
+    {"IMPS2",           CS7 | STD_FLG,                      NULL,               {0xc0, 0x40, 0xc0, 0x00}, 4, 1}, /* ? */
+    };
+
+#define NB_MICE (sizeof(mouse_infos)/sizeof(mouse_info))
+
+/* The name of the environment variables that are used to change the defaults above */
+
+#define ENV_MOUSEDRV "MGL_MOUSEDRV"
+#define ENV_MOUSEDEV "MGL_MOUSEDEV"
+#define ENV_MOUSESPD "MGL_MOUSESPD"
+#define ENV_JOYDEV0  "MGL_JOYDEV1"
+#define ENV_JOYDEV1  "MGL_JOYDEV2"
+
+/* Scancode mappings on Linux for special keys */
+
+typedef struct {
+    int scan;
+    int map;
+    } keymap;
+
+/* TODO: Fix this and set it up so we can do a binary search! */
+
+keymap keymaps[] = {
+    {96, KB_padEnter},
+    {74, KB_padMinus},
+    {78, KB_padPlus},
+    {55, KB_padTimes},
+    {98, KB_padDivide},
+    {71, KB_padHome},
+    {72, KB_padUp},
+    {73, KB_padPageUp},
+    {75, KB_padLeft},
+    {76, KB_padCenter},
+    {77, KB_padRight},
+    {79, KB_padEnd},
+    {80, KB_padDown},
+    {81, KB_padPageDown},
+    {82, KB_padInsert},
+    {83, KB_padDelete},
+    {105,KB_left},
+    {108,KB_down},
+    {106,KB_right},
+    {103,KB_up},
+    {110,KB_insert},
+    {102,KB_home},
+    {104,KB_pageUp},
+    {111,KB_delete},
+    {107,KB_end},
+    {109,KB_pageDown},
+    {125,KB_leftWindows},
+    {126,KB_rightWindows},
+    {127,KB_menu},
+    {100,KB_rightAlt},
+    {97,KB_rightCtrl},
+    };
+
+/* And the keypad with num lock turned on (changes the ASCII code only) */
+
+keymap keypad[] = {
+    {71, ASCII_7},
+    {72, ASCII_8},
+    {73, ASCII_9},
+    {75, ASCII_4},
+    {76, ASCII_5},
+    {77, ASCII_6},
+    {79, ASCII_1},
+    {80, ASCII_2},
+    {81, ASCII_3},
+    {82, ASCII_0},
+    {83, ASCII_period},
+    };
+
+#define NB_KEYMAPS (sizeof(keymaps)/sizeof(keymaps[0]))
+#define NB_KEYPAD (sizeof(keypad)/sizeof(keypad[0]))
+
+typedef struct {
+    int     sample;
+    char    code[2];
+    } sample_rate;
+
+sample_rate sampletab[]={
+    {  0,"O"},
+    { 15,"J"},
+    { 27,"K"},
+    { 42,"L"},
+    { 60,"R"},
+    { 85,"M"},
+    {125,"Q"},
+    {1E9,"N"},
+    };
+
+/* Number of keycodes to read at a time from the console */
+
+#define KBDREADBUFFERSIZE 32
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* These are not used under Linux */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flaps)
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Scan code to test
+
+REMARKS:
+This macro determines if a specified key is currently down at the
+time that the call is made.
+****************************************************************************/
+#define _EVT_isKeyDown(scanCode)    (keyUpMsg[scanCode] != 0)
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{
+    static uint     starttime = 0;
+    struct timeval  t;
+
+    gettimeofday(&t, NULL);
+    if (starttime == 0)
+      starttime = t.tv_sec * 1000 + (t.tv_usec/1000);
+    return ((t.tv_sec * 1000 + (t.tv_usec/1000)) - starttime);
+}
+
+/****************************************************************************
+REMARKS:
+Small Unix function that checks for availability on a file using select()
+****************************************************************************/
+static ibool dataReady(
+    int fd)
+{
+    static struct timeval   t = { 0L, 0L };
+    fd_set                  fds;
+
+    FD_ZERO(&fds);
+    FD_SET(fd, &fds);
+    return select(fd+1, &fds, NULL, NULL, &t) > 0;
+}
+
+/****************************************************************************
+REMARKS:
+Reads mouse data according to the selected mouse driver.
+****************************************************************************/
+static ibool readMouseData(
+    int *buttons,
+    int *dx,
+    int *dy)
+{
+    static uchar    data[32],prev = 0;
+    int             cnt = 0,ret;
+    mouse_info      *drv;
+
+    /* Read the first byte to check for the protocol */
+    drv = &mouse_infos[mouse_driver];
+    if (read(_EVT_mouse_fd, data, drv->read) != drv->read) {
+	perror("read");
+	return false;
+	}
+    if ((data[0] & drv->proto[0]) != drv->proto[1])
+	return false;
+
+    /* Load a whole protocol packet */
+    cnt += drv->read;
+    while (cnt < drv->packet_len) {
+	ret = read(_EVT_mouse_fd, data+cnt, drv->read);
+	if (ret == drv->read)
+	    cnt += ret;
+	else {
+	    perror("read");
+	    return false;
+	    }
+	}
+    if ((data[1] & drv->proto[2]) != drv->proto[3])
+	return false;
+
+    /* Now decode the protocol packet */
+    switch (mouse_driver) {
+	case EVT_microsoft:
+	    if (data[0] == 0x40 && !(prev|data[1]|data[2]))
+		*buttons = 2;   /* Third button on MS compatible mouse */
+	    else
+		*buttons= ((data[0] & 0x20) >> 3) | ((data[0] & 0x10) >> 4);
+	    prev = *buttons;
+	    *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F));
+	    *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F));
+	    break;
+	case EVT_ps2:
+	    *buttons = !!(data[0]&1) * 4 + !!(data[0]&2) * 1 + !!(data[0]&4) * 2;
+	    if (data[1] != 0)
+		*dx = (data[0] & 0x10) ? data[1]-256 : data[1];
+	    else
+		*dx = 0;
+	    if (data[2] != 0)
+		*dy = -((data[0] & 0x20) ? data[2]-256 : data[2]);
+	    else
+		*dy = 0;
+	    break;
+	case EVT_mousesystems: case EVT_gpm:
+	    *buttons = (~data[0]) & 0x07;
+	    *dx = (char)(data[1]) + (char)(data[3]);
+	    *dy = -((char)(data[2]) + (char)(data[4]));
+	    break;
+	case EVT_logitech:
+	    *buttons= data[0] & 0x07;
+	    *dx = (data[0] & 0x10) ?   data[1] : - data[1];
+	    *dy = (data[0] & 0x08) ? - data[2] :   data[2];
+	    break;
+	case EVT_busmouse:
+	    *buttons= (~data[0]) & 0x07;
+	    *dx = (char)data[1];
+	    *dy = -(char)data[2];
+	    break;
+	case EVT_MMseries:
+	    *buttons = data[0] & 0x07;
+	    *dx = (data[0] & 0x10) ?   data[1] : - data[1];
+	    *dy = (data[0] & 0x08) ? - data[2] :   data[2];
+	    break;
+	case EVT_intellimouse:
+	    *buttons = ((data[0] & 0x20) >> 3)  /* left */
+		     | ((data[3] & 0x10) >> 3)  /* middle */
+		     | ((data[0] & 0x10) >> 4); /* right */
+	    *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F));
+	    *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F));
+	    break;
+	case EVT_intellimouse_ps2:
+	    *buttons = (data[0] & 0x04) >> 1 /* Middle */
+		| (data[0] & 0x02) >> 1 /* Right */
+		| (data[0] & 0x01) << 2; /* Left */
+	    *dx = (data[0] & 0x10) ?    data[1]-256  :  data[1];
+	    *dy = (data[0] & 0x20) ?  -(data[2]-256) : -data[2];
+	    break;
+	case EVT_mouseman: {
+	    static int      getextra;
+	    static uchar    prev=0;
+	    uchar           b;
+
+	    /* The damned MouseMan has 3/4 bytes packets. The extra byte
+	     * is only there if the middle button is active.
+	     * I get the extra byte as a packet with magic numbers in it.
+	     * and then switch to 4-byte mode.
+	     */
+	    if (data[1] == 0xAA && data[2] == 0x55) {
+		/* Got unexpected fourth byte */
+		if ((b = (*data>>4)) > 0x3)
+		    return false;  /* just a sanity check */
+		*dx = *dy = 0;
+		drv->packet_len=4;
+		getextra=0;
+		}
+	    else {
+		/* Got 3/4, as expected */
+		/* Motion is independent of packetlen... */
+		*dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F));
+		*dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F));
+		prev = ((data[0] & 0x20) >> 3) | ((data[0] & 0x10) >> 4);
+		if (drv->packet_len==4)
+		    b = data[3]>>4;
+		}
+	    if (drv->packet_len == 4) {
+		if (b == 0) {
+		    drv->packet_len = 3;
+		    getextra = 1;
+		    }
+		else {
+		    if (b & 0x2)
+			prev |= 2;
+		    }
+		}
+	    *buttons = prev;
+
+	    /* This "chord-middle" behaviour was reported by David A. van Leeuwen */
+	    if (((prev ^ *buttons) & 5) == 5)
+		*buttons = *buttons ? 2 : 0;
+	    prev = *buttons;
+	    break;
+	    }
+	case EVT_noMouse:
+	    return false;
+	    break;
+	}
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Map a keypress via the key mapping table
+****************************************************************************/
+static int getKeyMapping(
+    keymap *tab,
+    int nb,
+    int key)
+{
+    int i;
+
+    for(i = 0; i < nb; i++) {
+	if (tab[i].scan == key)
+	    return tab[i].map;
+	}
+    return key;
+}
+
+#ifdef USE_OS_JOYSTICK
+
+static char js0_axes = 0, js0_buttons = 0;
+static char js1_axes = 0, js1_buttons = 0;
+static char joystick0_dev[20] = "/dev/js0";
+static char joystick1_dev[20] = "/dev/js1";
+
+/****************************************************************************
+REMARKS:
+Create a joystick event from the joystick data
+****************************************************************************/
+static void makeJoyEvent(
+    event_t *evt)
+{
+    evt->message = 0;
+    if (buts0 && axis0) {
+	if (buts0[0]) evt->message |= EVT_JOY1_BUTTONA;
+	if (buts0[1]) evt->message |= EVT_JOY1_BUTTONB;
+	evt->where_x = axis0[0];
+	evt->where_y = axis0[1];
+	}
+    else
+	evt->where_x = evt->where_y = 0;
+    if (buts1 && axis1) {
+	if (buts1[0]) evt->message |= EVT_JOY2_BUTTONA;
+	if (buts1[1]) evt->message |= EVT_JOY2_BUTTONB;
+	evt->where_x = axis1[0];
+	evt->where_y = axis1[1];
+	}
+    else
+	evt->where_x = evt->where_y = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the joystick axis data
+****************************************************************************/
+int EVTAPI _EVT_readJoyAxis(
+    int jmask,
+    int *axis)
+{
+    int mask = 0;
+
+    if ((js_version & ~0xffff) == 0) {
+	/* Old 0.x driver */
+	struct JS_DATA_TYPE js;
+	if (joystick0_fd && read(joystick0_fd, &js, JS_RETURN) == JS_RETURN) {
+	    if (jmask & EVT_JOY_AXIS_X1)
+		axis[0] = js.x;
+	    if (jmask & EVT_JOY_AXIS_Y1)
+		axis[1] = js.y;
+	    mask |= EVT_JOY_AXIS_X1|EVT_JOY_AXIS_Y1;
+	    }
+	if (joystick1_fd && read(joystick1_fd, &js, JS_RETURN) == JS_RETURN) {
+	    if (jmask & EVT_JOY_AXIS_X2)
+		axis[2] = js.x;
+	    if (jmask & EVT_JOY_AXIS_Y2)
+		axis[3] = js.y;
+	    mask |= EVT_JOY_AXIS_X2|EVT_JOY_AXIS_Y2;
+	    }
+	}
+    else {
+	if (axis0) {
+	    if (jmask & EVT_JOY_AXIS_X1)
+		axis[0] = axis0[0];
+	    if (jmask & EVT_JOY_AXIS_Y1)
+		axis[1] = axis0[1];
+	    mask |= EVT_JOY_AXIS_X1 | EVT_JOY_AXIS_Y1;
+	    }
+	if (axis1) {
+	    if (jmask & EVT_JOY_AXIS_X2)
+		axis[2] = axis1[0];
+	    if (jmask & EVT_JOY_AXIS_Y2)
+		axis[3] = axis1[1];
+	    mask |= EVT_JOY_AXIS_X2 | EVT_JOY_AXIS_Y2;
+	    }
+	}
+    return mask;
+}
+
+/****************************************************************************
+REMARKS:
+Read the joystick button data
+****************************************************************************/
+int EVTAPI _EVT_readJoyButtons(void)
+{
+    int buts = 0;
+
+    if ((js_version & ~0xffff) == 0) {
+	/* Old 0.x driver */
+	struct JS_DATA_TYPE js;
+	if (joystick0_fd && read(joystick0_fd, &js, JS_RETURN) == JS_RETURN)
+	    buts = js.buttons;
+	if (joystick1_fd && read(joystick1_fd, &js, JS_RETURN) == JS_RETURN)
+	    buts |= js.buttons << 2;
+	}
+    else {
+	if (buts0)
+	    buts |= EVT_JOY1_BUTTONA*buts0[0] + EVT_JOY1_BUTTONB*buts0[1];
+	if (buts1)
+	    buts |= EVT_JOY2_BUTTONA*buts1[0] + EVT_JOY2_BUTTONB*buts1[1];
+	}
+    return buts;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns the mask indicating what joystick axes are attached.
+
+HEADER:
+event.h
+
+REMARKS:
+This function is used to detect the attached joysticks, and determine
+what axes are present and functioning. This function will re-detect any
+attached joysticks when it is called, so if the user forgot to attach
+the joystick when the application started, you can call this function to
+re-detect any newly attached joysticks.
+
+SEE ALSO:
+EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent
+****************************************************************************/
+int EVTAPI EVT_joyIsPresent(void)
+{
+    static int      mask = 0;
+    int             i;
+    char            *tmp, name0[128], name1[128];
+    static ibool    inited = false;
+
+    if (inited)
+	return mask;
+    memset(EVT.joyMin,0,sizeof(EVT.joyMin));
+    memset(EVT.joyCenter,0,sizeof(EVT.joyCenter));
+    memset(EVT.joyMax,0,sizeof(EVT.joyMax));
+    memset(EVT.joyPrev,0,sizeof(EVT.joyPrev));
+    EVT.joyButState = 0;
+    if ((tmp = getenv(ENV_JOYDEV0)) != NULL)
+	strcpy(joystick0_dev,tmp);
+    if ((tmp = getenv(ENV_JOYDEV1)) != NULL)
+	strcpy(joystick1_dev,tmp);
+    if ((joystick0_fd = open(joystick0_dev, O_RDONLY)) < 0)
+	joystick0_fd = 0;
+    if ((joystick1_fd = open(joystick1_dev, O_RDONLY)) < 0)
+	joystick1_fd = 0;
+    if (!joystick0_fd && !joystick1_fd) /* No joysticks detected */
+	return 0;
+    inited = true;
+    if (ioctl(joystick0_fd ? joystick0_fd : joystick1_fd, JSIOCGVERSION, &js_version) < 0)
+	return 0;
+
+    /* Initialise joystick 0 */
+    if (joystick0_fd) {
+	ioctl(joystick0_fd, JSIOCGNAME(sizeof(name0)), name0);
+	if (js_version & ~0xffff) {
+	    struct js_event js;
+
+	    ioctl(joystick0_fd, JSIOCGAXES, &js0_axes);
+	    ioctl(joystick0_fd, JSIOCGBUTTONS, &js0_buttons);
+	    axis0 = PM_calloc((int)js0_axes, sizeof(short));
+	    buts0 = PM_malloc((int)js0_buttons);
+	    /* Read the initial events */
+	    while(dataReady(joystick0_fd)
+		  && read(joystick0_fd, &js, sizeof(struct js_event)) == sizeof(struct js_event)
+		  && (js.type & JS_EVENT_INIT)
+		  ) {
+		if (js.type & JS_EVENT_BUTTON)
+		    buts0[js.number] = js.value;
+		else if (js.type & JS_EVENT_AXIS)
+		    axis0[js.number] = scaleJoyAxis(js.value,js.number);
+		}
+	    }
+	else {
+	    js0_axes = 2;
+	    js0_buttons = 2;
+	    axis0 = PM_calloc((int)js0_axes, sizeof(short));
+	    buts0 = PM_malloc((int)js0_buttons);
+	    }
+	}
+
+    /* Initialise joystick 1 */
+    if (joystick1_fd) {
+	ioctl(joystick1_fd, JSIOCGNAME(sizeof(name1)), name1);
+	if (js_version & ~0xffff) {
+	    struct js_event js;
+
+	    ioctl(joystick1_fd, JSIOCGAXES, &js1_axes);
+	    ioctl(joystick1_fd, JSIOCGBUTTONS, &js1_buttons);
+	    axis1 = PM_calloc((int)js1_axes, sizeof(short));
+	    buts1 = PM_malloc((int)js1_buttons);
+	    /* Read the initial events */
+	    while(dataReady(joystick1_fd)
+		  && read(joystick1_fd, &js, sizeof(struct js_event))==sizeof(struct js_event)
+		  && (js.type & JS_EVENT_INIT)
+		  ) {
+		if (js.type & JS_EVENT_BUTTON)
+		    buts1[js.number] = js.value;
+		else if (js.type & JS_EVENT_AXIS)
+		    axis1[js.number] = scaleJoyAxis(js.value,js.number<<2);
+		}
+	    }
+	else {
+	    js1_axes = 2;
+	    js1_buttons = 2;
+	    axis1 = PM_calloc((int)js1_axes, sizeof(short));
+	    buts1 = PM_malloc((int)js1_buttons);
+	    }
+	}
+
+#ifdef  CHECKED
+    fprintf(stderr,"Using joystick driver version %d.%d.%d\n",
+	    js_version >> 16, (js_version >> 8) & 0xff, js_version & 0xff);
+    if (joystick0_fd)
+	fprintf(stderr,"Joystick 1 (%s): %s\n", joystick0_dev, name0);
+    if (joystick1_fd)
+	fprintf(stderr,"Joystick 2 (%s): %s\n", joystick1_dev, name1);
+#endif
+    mask = _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter);
+    if (mask) {
+	for (i = 0; i < JOY_NUM_AXES; i++)
+	    EVT.joyMax[i] = EVT.joyCenter[i]*2;
+	}
+    return mask;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Polls the joystick for position and button information.
+
+HEADER:
+event.h
+
+REMARKS:
+This routine is used to poll analogue joysticks for button and position
+information. It should be called once for each main loop of the user
+application, just before processing all pending events via EVT_getNext.
+All information polled from the joystick will be posted to the event
+queue for later retrieval.
+
+Note:   Most analogue joysticks will provide readings that change even
+	though the joystick has not moved. Hence if you call this routine
+	you will likely get an EVT_JOYMOVE event every time through your
+	event loop.
+
+SEE ALSO:
+EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight,
+EVT_joySetCenter, EVT_joyIsPresent
+****************************************************************************/
+void EVTAPI EVT_pollJoystick(void)
+{
+    event_t evt;
+    int     i,axis[JOY_NUM_AXES],newButState,mask,moved,ps;
+
+    if ((js_version & ~0xFFFF) == 0 && EVT.joyMask) {
+	/* Read joystick axes and post movement events if they have
+	 * changed since the last time we polled. Until the events are
+	 * actually flushed, we keep modifying the same joystick movement
+	 * event, so you won't get multiple movement event
+	 */
+	mask = _EVT_readJoyAxis(EVT.joyMask,axis);
+	newButState = _EVT_readJoyButtons();
+	moved = false;
+	for (i = 0; i < JOY_NUM_AXES; i++) {
+	    if (mask & (EVT_JOY_AXIS_X1 << i))
+		axis[i] = scaleJoyAxis(axis[i],i);
+	    else
+		axis[i] = EVT.joyPrev[i];
+	    if (axis[i] != EVT.joyPrev[i])
+		moved = true;
+	    }
+	if (moved) {
+	    memcpy(EVT.joyPrev,axis,sizeof(EVT.joyPrev));
+	    ps = _EVT_disableInt();
+	    if (EVT.oldJoyMove != -1) {
+		/* Modify the existing joystick movement event */
+		EVT.evtq[EVT.oldJoyMove].message = newButState;
+		EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0];
+		EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1];
+		EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2];
+		EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3];
+		}
+	    else if (EVT.count < EVENTQSIZE) {
+		/* Add a new joystick movement event */
+		EVT.oldJoyMove = EVT.freeHead;
+		memset(&evt,0,sizeof(evt));
+		evt.what = EVT_JOYMOVE;
+		evt.message = EVT.joyButState;
+		evt.where_x = EVT.joyPrev[0];
+		evt.where_y = EVT.joyPrev[1];
+		evt.relative_x = EVT.joyPrev[2];
+		evt.relative_y = EVT.joyPrev[3];
+		addEvent(&evt);
+		}
+	    _EVT_restoreInt(ps);
+	    }
+
+	/* Read the joystick buttons, and post events to reflect the change
+	 * in state for the joystick buttons.
+	 */
+	if (newButState != EVT.joyButState) {
+	    if (EVT.count < EVENTQSIZE) {
+		/* Add a new joystick movement event */
+		ps = _EVT_disableInt();
+		memset(&evt,0,sizeof(evt));
+		evt.what = EVT_JOYCLICK;
+		evt.message = newButState;
+		EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0];
+		EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1];
+		EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2];
+		EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3];
+		addEvent(&evt);
+		_EVT_restoreInt(ps);
+		}
+	    EVT.joyButState = newButState;
+	    }
+	}
+}
+
+/****************************************************************************
+DESCRIPTION:
+Calibrates the joystick upper left position
+
+HEADER:
+event.h
+
+REMARKS:
+This function can be used to zero in on better joystick calibration factors,
+which may work better than the default simplistic calibration (which assumes
+the joystick is centered when the event library is initialised).
+To use this function, ask the user to hold the stick in the upper left
+position and then have them press a key or button. and then call this
+function. This function will then read the joystick and update the
+calibration factors.
+
+Usually, assuming that the stick was centered when the event library was
+initialized, you really only need to call EVT_joySetLowerRight since the
+upper left position is usually always 0,0 on most joysticks. However, the
+safest procedure is to call all three calibration functions.
+
+SEE ALSO:
+EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent
+****************************************************************************/
+void EVTAPI EVT_joySetUpperLeft(void)
+{
+    _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMin);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Calibrates the joystick lower right position
+
+HEADER:
+event.h
+
+REMARKS:
+This function can be used to zero in on better joystick calibration factors,
+which may work better than the default simplistic calibration (which assumes
+the joystick is centered when the event library is initialised).
+To use this function, ask the user to hold the stick in the lower right
+position and then have them press a key or button. and then call this
+function. This function will then read the joystick and update the
+calibration factors.
+
+Usually, assuming that the stick was centered when the event library was
+initialized, you really only need to call EVT_joySetLowerRight since the
+upper left position is usually always 0,0 on most joysticks. However, the
+safest procedure is to call all three calibration functions.
+
+SEE ALSO:
+EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent
+****************************************************************************/
+void EVTAPI EVT_joySetLowerRight(void)
+{
+    _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMax);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Calibrates the joystick center position
+
+HEADER:
+event.h
+
+REMARKS:
+This function can be used to zero in on better joystick calibration factors,
+which may work better than the default simplistic calibration (which assumes
+the joystick is centered when the event library is initialised).
+To use this function, ask the user to hold the stick in the center
+position and then have them press a key or button. and then call this
+function. This function will then read the joystick and update the
+calibration factors.
+
+Usually, assuming that the stick was centered when the event library was
+initialized, you really only need to call EVT_joySetLowerRight since the
+upper left position is usually always 0,0 on most joysticks. However, the
+safest procedure is to call all three calibration functions.
+
+SEE ALSO:
+EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter
+****************************************************************************/
+void EVTAPI EVT_joySetCenter(void)
+{
+    _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter);
+}
+#endif
+
+/****************************************************************************
+REMARKS:
+Pumps all messages in the message queue from Linux into our event queue.
+****************************************************************************/
+static void _EVT_pumpMessages(void)
+{
+    event_t                 evt;
+    int                     i,numkeys, c;
+    ibool                   release;
+    static struct kbentry   ke;
+    static char             buf[KBDREADBUFFERSIZE];
+    static ushort           repeatKey[128] = {0};
+
+    /* Poll keyboard events */
+    while (dataReady(_PM_console_fd) && (numkeys = read(_PM_console_fd, buf, KBDREADBUFFERSIZE)) > 0) {
+	for (i = 0; i < numkeys; i++) {
+	    c = buf[i];
+	    release = c & 0x80;
+	    c &= 0x7F;
+
+	    /* TODO:    This is wrong! We need this to be the time stamp at */
+	    /*          ** interrupt ** time!! One solution would be to */
+	    /*          put the keyboard and mouse polling loops into */
+	    /*          a separate thread that can block on I/O to the */
+	    /*          necessay file descriptor. */
+	    evt.when = _EVT_getTicks();
+
+	    if (release) {
+		/* Key released */
+		evt.what = EVT_KEYUP;
+		switch (c) {
+		    case KB_leftShift:
+			_PM_modifiers &= ~EVT_LEFTSHIFT;
+			break;
+		    case KB_rightShift:
+			_PM_modifiers &= ~EVT_RIGHTSHIFT;
+			break;
+		    case 29:
+			_PM_modifiers &= ~(EVT_LEFTCTRL|EVT_CTRLSTATE);
+			break;
+		    case 97:            /* Control */
+			_PM_modifiers &= ~EVT_CTRLSTATE;
+			break;
+		    case 56:
+			_PM_modifiers &= ~(EVT_LEFTALT|EVT_ALTSTATE);
+			break;
+		    case 100:
+			_PM_modifiers &= ~EVT_ALTSTATE;
+			break;
+		    default:
+		    }
+		evt.modifiers = _PM_modifiers;
+		evt.message = keyUpMsg[c];
+		if (EVT.count < EVENTQSIZE)
+		    addEvent(&evt);
+		keyUpMsg[c] = 0;
+		repeatKey[c] = 0;
+		}
+	    else {
+		/* Key pressed */
+		evt.what = EVT_KEYDOWN;
+		switch (c) {
+		    case KB_leftShift:
+			_PM_modifiers |= EVT_LEFTSHIFT;
+			break;
+		    case KB_rightShift:
+			_PM_modifiers |= EVT_RIGHTSHIFT;
+			break;
+		    case 29:
+			_PM_modifiers |= EVT_LEFTCTRL|EVT_CTRLSTATE;
+			break;
+		    case 97:            /* Control */
+			_PM_modifiers |= EVT_CTRLSTATE;
+			break;
+		    case 56:
+			_PM_modifiers |= EVT_LEFTALT|EVT_ALTSTATE;
+			break;
+		    case 100:
+			_PM_modifiers |= EVT_ALTSTATE;
+			break;
+		    case KB_capsLock:   /* Caps Lock */
+			_PM_leds ^= LED_CAP;
+			ioctl(_PM_console_fd, KDSETLED, _PM_leds);
+			break;
+		    case KB_numLock:    /* Num Lock */
+			_PM_leds ^= LED_NUM;
+			ioctl(_PM_console_fd, KDSETLED, _PM_leds);
+			break;
+		    case KB_scrollLock: /* Scroll Lock */
+			_PM_leds ^= LED_SCR;
+			ioctl(_PM_console_fd, KDSETLED, _PM_leds);
+			break;
+		    default:
+		    }
+		evt.modifiers = _PM_modifiers;
+		if (keyUpMsg[c]) {
+		    evt.what = EVT_KEYREPEAT;
+		    evt.message = keyUpMsg[c] | (repeatKey[c]++ << 16);
+		    }
+		else {
+		    int asc;
+
+		    evt.message = getKeyMapping(keymaps, NB_KEYMAPS, c) << 8;
+		    ke.kb_index = c;
+		    ke.kb_table = 0;
+		    if ((_PM_modifiers & EVT_SHIFTKEY) || (_PM_leds & LED_CAP))
+			ke.kb_table |= K_SHIFTTAB;
+		    if (_PM_modifiers & (EVT_LEFTALT | EVT_ALTSTATE))
+			ke.kb_table |= K_ALTTAB;
+		    if (ioctl(_PM_console_fd, KDGKBENT, (unsigned long)&ke)<0)
+			perror("ioctl(KDGKBENT)");
+		    if ((_PM_leds & LED_NUM) && (getKeyMapping(keypad, NB_KEYPAD, c)!=c)) {
+			asc = getKeyMapping(keypad, NB_KEYPAD, c);
+			}
+		    else {
+			switch (c) {
+			    case 14:
+				asc = ASCII_backspace;
+				break;
+			    case 15:
+				asc = ASCII_tab;
+				break;
+			    case 28:
+			    case 96:
+				asc = ASCII_enter;
+				break;
+			    case 1:
+				asc = ASCII_esc;
+			    default:
+				asc = ke.kb_value & 0xFF;
+				if (asc < 0x1B)
+				    asc = 0;
+				break;
+			    }
+			}
+		    if ((_PM_modifiers & (EVT_CTRLSTATE|EVT_LEFTCTRL)) && isalpha(asc))
+			evt.message |= toupper(asc) - 'A' + 1;
+		    else
+			evt.message |= asc;
+		    keyUpMsg[c] = evt.message;
+		    repeatKey[c]++;
+		    }
+		if (EVT.count < EVENTQSIZE)
+		    addEvent(&evt);
+		}
+	    }
+	}
+
+    /* Poll mouse events */
+    if (_EVT_mouse_fd) {
+	int         dx, dy, buts;
+	static int  oldbuts;
+
+	while (dataReady(_EVT_mouse_fd)) {
+	    if (readMouseData(&buts, &dx, &dy)) {
+		EVT.mx += dx;
+		EVT.my += dy;
+		if (EVT.mx < 0) EVT.mx = 0;
+		if (EVT.my < 0) EVT.my = 0;
+		if (EVT.mx > range_x) EVT.mx = range_x;
+		if (EVT.my > range_y) EVT.my = range_y;
+		evt.where_x = EVT.mx;
+		evt.where_y = EVT.my;
+		evt.relative_x = dx;
+		evt.relative_y = dy;
+
+		/* TODO:    This is wrong! We need this to be the time stamp at */
+		/*          ** interrupt ** time!! One solution would be to */
+		/*          put the keyboard and mouse polling loops into */
+		/*          a separate thread that can block on I/O to the */
+		/*          necessay file descriptor. */
+		evt.when = _EVT_getTicks();
+		evt.modifiers = _PM_modifiers;
+		if (buts & 4)
+		    evt.modifiers |= EVT_LEFTBUT;
+		if (buts & 1)
+		    evt.modifiers |= EVT_RIGHTBUT;
+		if (buts & 2)
+		    evt.modifiers |= EVT_MIDDLEBUT;
+
+		/* Left click events */
+		if ((buts&4) != (oldbuts&4)) {
+		    if (buts&4)
+			evt.what = EVT_MOUSEDOWN;
+		    else
+			evt.what = EVT_MOUSEUP;
+		    evt.message = EVT_LEFTBMASK;
+		    EVT.oldMove = -1;
+		    if (EVT.count < EVENTQSIZE)
+			addEvent(&evt);
+		    }
+
+		/* Right click events */
+		if ((buts&1) != (oldbuts&1)) {
+		    if (buts&1)
+			evt.what = EVT_MOUSEDOWN;
+		    else
+			evt.what = EVT_MOUSEUP;
+		    evt.message = EVT_RIGHTBMASK;
+		    EVT.oldMove = -1;
+		    if (EVT.count < EVENTQSIZE)
+			addEvent(&evt);
+		    }
+
+		/* Middle click events */
+		if ((buts&2) != (oldbuts&2)) {
+		    if (buts&2)
+			evt.what = EVT_MOUSEDOWN;
+		    else
+			evt.what = EVT_MOUSEUP;
+		    evt.message = EVT_MIDDLEBMASK;
+		    EVT.oldMove = -1;
+		    if (EVT.count < EVENTQSIZE)
+			addEvent(&evt);
+		    }
+
+		/* Mouse movement event */
+		if (dx || dy) {
+		    evt.what = EVT_MOUSEMOVE;
+		    evt.message = 0;
+		    if (EVT.oldMove != -1) {
+			/* Modify existing movement event */
+			EVT.evtq[EVT.oldMove].where_x = evt.where_x;
+			EVT.evtq[EVT.oldMove].where_y = evt.where_y;
+			}
+		    else {
+			/* Save id of this movement event */
+			EVT.oldMove = EVT.freeHead;
+			if (EVT.count < EVENTQSIZE)
+			    addEvent(&evt);
+			}
+		    }
+		oldbuts = buts;
+		}
+	    }
+	}
+
+#ifdef USE_OS_JOYSTICK
+    /* Poll joystick events using the 1.x joystick driver API in the 2.2 kernels */
+    if (js_version & ~0xffff) {
+	static struct js_event  js;
+
+	/* Read joystick axis 0 */
+	evt.when = 0;
+	evt.modifiers = _PM_modifiers;
+	if (joystick0_fd && dataReady(joystick0_fd) &&
+		read(joystick0_fd, &js, sizeof(js)) == sizeof(js)) {
+	    if (js.type & JS_EVENT_BUTTON) {
+		if (js.number < 2) { /* Only 2 buttons for now :( */
+		    buts0[js.number] = js.value;
+		    evt.what = EVT_JOYCLICK;
+		    makeJoyEvent(&evt);
+		    if (EVT.count < EVENTQSIZE)
+			addEvent(&evt);
+		    }
+		}
+	    else if (js.type & JS_EVENT_AXIS) {
+		axis0[js.number] = scaleJoyAxis(js.value,js.number);
+		evt.what = EVT_JOYMOVE;
+		if (EVT.oldJoyMove != -1) {
+		    makeJoyEvent(&EVT.evtq[EVT.oldJoyMove]);
+		    }
+		else if (EVT.count < EVENTQSIZE) {
+		    EVT.oldJoyMove = EVT.freeHead;
+		    makeJoyEvent(&evt);
+		    addEvent(&evt);
+		    }
+		}
+	    }
+
+	/* Read joystick axis 1 */
+	if (joystick1_fd && dataReady(joystick1_fd) &&
+		read(joystick1_fd, &js, sizeof(js))==sizeof(js)) {
+	    if (js.type & JS_EVENT_BUTTON) {
+		if (js.number < 2) { /* Only 2 buttons for now :( */
+		    buts1[js.number] = js.value;
+		    evt.what = EVT_JOYCLICK;
+		    makeJoyEvent(&evt);
+		    if (EVT.count < EVENTQSIZE)
+			addEvent(&evt);
+		    }
+		}
+	    else if (js.type & JS_EVENT_AXIS) {
+		axis1[js.number] = scaleJoyAxis(js.value,js.number<<2);
+		evt.what = EVT_JOYMOVE;
+		if (EVT.oldJoyMove != -1) {
+		    makeJoyEvent(&EVT.evtq[EVT.oldJoyMove]);
+		    }
+		else if (EVT.count < EVENTQSIZE) {
+		    EVT.oldJoyMove = EVT.freeHead;
+		    makeJoyEvent(&evt);
+		    addEvent(&evt);
+		    }
+		}
+	    }
+	}
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift _PM_modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Set the speed of the serial port
+****************************************************************************/
+static int setspeed(
+    int fd,
+    int old,
+    int new,
+    unsigned short flags)
+{
+    struct termios tty;
+    char *c;
+
+    tcgetattr(fd, &tty);
+    tty.c_iflag = IGNBRK | IGNPAR;
+    tty.c_oflag = 0;
+    tty.c_lflag = 0;
+    tty.c_line = 0;
+    tty.c_cc[VTIME] = 0;
+    tty.c_cc[VMIN] = 1;
+    switch (old) {
+	case 9600:  tty.c_cflag = flags | B9600; break;
+	case 4800:  tty.c_cflag = flags | B4800; break;
+	case 2400:  tty.c_cflag = flags | B2400; break;
+	case 1200:
+	default:    tty.c_cflag = flags | B1200; break;
+	}
+    tcsetattr(fd, TCSAFLUSH, &tty);
+    switch (new) {
+	case 9600:  c = "*q";  tty.c_cflag = flags | B9600; break;
+	case 4800:  c = "*p";  tty.c_cflag = flags | B4800; break;
+	case 2400:  c = "*o";  tty.c_cflag = flags | B2400; break;
+	case 1200:
+	default:    c = "*n";  tty.c_cflag = flags | B1200; break;
+	}
+    write(fd, c, 2);
+    usleep(100000);
+    tcsetattr(fd, TCSAFLUSH, &tty);
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Generic mouse driver init code
+****************************************************************************/
+static void _EVT_mouse_init(void)
+{
+    int i;
+
+    /* Change from any available speed to the chosen one */
+    for (i = 9600; i >= 1200; i /= 2)
+	setspeed(_EVT_mouse_fd, i, opt_baud, mouse_infos[mouse_driver].flags);
+}
+
+/****************************************************************************
+REMARKS:
+Logitech mouse driver init code
+****************************************************************************/
+static void _EVT_logitech_init(void)
+{
+    int         i;
+    struct stat buf;
+    int         busmouse;
+
+    /* is this a serial- or a bus- mouse? */
+    if (fstat(_EVT_mouse_fd,&buf) == -1)
+	perror("fstat");
+    i = MAJOR(buf.st_rdev);
+    if (stat("/dev/ttyS0",&buf) == -1)
+	perror("stat");
+    busmouse=(i != MAJOR(buf.st_rdev));
+
+    /* Fix the howmany field, so that serial mice have 1, while busmice have 3 */
+    mouse_infos[mouse_driver].read = busmouse ? 3 : 1;
+
+    /* Change from any available speed to the chosen one */
+    for (i = 9600; i >= 1200; i /= 2)
+	setspeed(_EVT_mouse_fd, i, opt_baud, mouse_infos[mouse_driver].flags);
+
+    /* This stuff is peculiar of logitech mice, also for the serial ones */
+    write(_EVT_mouse_fd, "S", 1);
+    setspeed(_EVT_mouse_fd, opt_baud, opt_baud,CS8 |PARENB |PARODD |CREAD |CLOCAL |HUPCL);
+
+    /* Configure the sample rate */
+    for (i = 0; opt_sample <= sampletab[i].sample; i++)
+	;
+    write(_EVT_mouse_fd,sampletab[i].code,1);
+}
+
+/****************************************************************************
+REMARKS:
+Microsoft Intellimouse init code
+****************************************************************************/
+static void _EVT_pnpmouse_init(void)
+{
+    struct termios tty;
+
+    tcgetattr(_EVT_mouse_fd, &tty);
+    tty.c_iflag = IGNBRK | IGNPAR;
+    tty.c_oflag = 0;
+    tty.c_lflag = 0;
+    tty.c_line = 0;
+    tty.c_cc[VTIME] = 0;
+    tty.c_cc[VMIN] = 1;
+    tty.c_cflag = mouse_infos[mouse_driver].flags | B1200;
+    tcsetattr(_EVT_mouse_fd, TCSAFLUSH, &tty); /* set parameters */
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    int         i;
+    char        *tmp;
+
+    /* Initialise the event queue */
+    EVT.mouseMove = mouseMove;
+    initEventQueue();
+    for (i = 0; i < 256; i++)
+	keyUpMsg[i] = 0;
+
+    /* Keyboard initialization */
+    if (_PM_console_fd == -1)
+	PM_fatalError("You must first call PM_openConsole to use the EVT functions!");
+    _PM_keyboard_rawmode();
+    fcntl(_PM_console_fd,F_SETFL,fcntl(_PM_console_fd,F_GETFL) | O_NONBLOCK);
+
+    /* Mouse initialization */
+    if ((tmp = getenv(ENV_MOUSEDRV)) != NULL) {
+	for (i = 0; i < NB_MICE; i++) {
+	    if (!strcasecmp(tmp, mouse_infos[i].name)) {
+		mouse_driver = i;
+		break;
+		}
+	    }
+	if (i == NB_MICE) {
+	    fprintf(stderr,"Unknown mouse driver: %s\n", tmp);
+	    mouse_driver = EVT_noMouse;
+	    _EVT_mouse_fd = 0;
+	    }
+	}
+    if (mouse_driver != EVT_noMouse) {
+	if (mouse_driver == EVT_gpm)
+	    strcpy(mouse_dev,"/dev/gpmdata");
+	if ((tmp = getenv(ENV_MOUSEDEV)) != NULL)
+	    strcpy(mouse_dev,tmp);
+#ifdef  CHECKED
+	fprintf(stderr,"Using the %s MGL mouse driver on %s.\n", mouse_infos[mouse_driver].name, mouse_dev);
+#endif
+	if ((_EVT_mouse_fd = open(mouse_dev, O_RDWR)) < 0) {
+	    perror("open");
+	    fprintf(stderr, "Unable to open mouse device %s, dropping mouse support.\n", mouse_dev);
+	    sleep(1);
+	    mouse_driver = EVT_noMouse;
+	    _EVT_mouse_fd = 0;
+	    }
+	else {
+	    char c;
+
+	    /* Init and flush the mouse pending input queue */
+	    if (mouse_infos[mouse_driver].init)
+		mouse_infos[mouse_driver].init();
+	    while(dataReady(_EVT_mouse_fd) && read(_EVT_mouse_fd, &c, 1) == 1)
+		;
+	    }
+	}
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    range_x = xRes;
+    range_y = yRes;
+}
+
+/****************************************************************************
+REMARKS
+Modifes the mouse coordinates as necessary if scaling to OS coordinates,
+and sets the OS mouse cursor position.
+****************************************************************************/
+#define _EVT_setMousePos(x,y)
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for Linux */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for Linux */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+    /* Restore signal handlers */
+    _PM_restore_kb_mode();
+    if (_EVT_mouse_fd) {
+	close(_EVT_mouse_fd);
+	_EVT_mouse_fd = 0;
+	}
+#ifdef USE_OS_JOYSTICK
+    if (joystick0_fd) {
+	close(joystick0_fd);
+	free(axis0);
+	free(buts0);
+	joystick0_fd = 0;
+	}
+    if (joystick1_fd) {
+	close(joystick1_fd);
+	free(axis1);
+	free(buts1);
+	joystick1_fd = 0;
+	}
+#endif
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga b/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga
new file mode 100755
index 0000000..c0358a0
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga
@@ -0,0 +1,1058 @@
+/****************************************************************************
+*
+*           The SuperVGA Kit - UniVBE Software Development Kit
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  IBM PC (MS DOS)
+*
+* Description:  Routines to provide a Linux event queue, which automatically
+*               handles keyboard and mouse events for the Linux compatability
+*               libraries. Based on the event handling code in the MGL.
+*
+****************************************************************************/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <ctype.h>
+#include <termios.h>
+#include <signal.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <errno.h>
+#include <sys/time.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <linux/keyboard.h>
+#include <linux/kd.h>
+#include <linux/vt.h>
+#include <gpm.h>
+#include "pm.h"
+#include "vesavbe.h"
+#include "wdirect.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+#define EVENTQSIZE  100             /* Number of events in event queue  */
+
+static int      head = -1;          /* Head of event queue              */
+static int      tail = -1;          /* Tail of event queue              */
+static int      freeHead = -1;      /* Head of free list                */
+static int      count = 0;          /* No. of items currently in queue  */
+static WD_event evtq[EVENTQSIZE];   /* The queue structure itself      */
+static int      oldMove = -1;       /* Previous movement event          */
+static int      oldKey = -1;        /* Previous key repeat event        */
+static int      mx,my;              /* Current mouse position           */
+static int      xRes,yRes;          /* Screen resolution coordinates    */
+static void     *stateBuf;          /* Pointer to console state buffer  */
+static int      conn;               /* GPM file descriptor for mouse handling */
+static int      tty_fd;             /* File descriptor for /dev/console */
+extern int      tty_vc;             /* Virtual console ID, from the PM/Pro library */
+static ibool    key_down[128];      /* State of all keyboard keys       */
+static struct termios old_conf;     /* Saved terminal configuration     */
+static int      oldkbmode;          /* and previous keyboard mode       */
+struct vt_mode  oldvtmode;          /* Old virtual terminal mode        */
+static int      old_flags;          /* Old flags for fcntl              */
+static ulong    key_modifiers;      /* Keyboard modifiers               */
+static int      forbid_vt_release=0;/* Flag to forbid release of VT     */
+static int      forbid_vt_acquire=0;/* Flag to forbid cature of VT      */
+static int      oldmode;            /* Old SVGA mode saved for VT switch*/
+static int      initmode;           /* Initial text mode                */
+static ibool    installed = false;  /* True if we are installed         */
+static void     (_ASMAPI *moveCursor)(int x,int y) = NULL;
+static int      (_ASMAPI *suspendAppCallback)(int flags) = NULL;
+
+#if 0
+/* Keyboard Translation table from scancodes to ASCII */
+
+static uchar keyTable[128] =
+"\0\0331234567890-=\010"
+"\011qwertyuiop[]\015"
+"\0asdfghjkl;'`\0\\"
+"zxcvbnm,./\0*\0 \0"
+"\0\0\0\0\0\0\0\0\0\0\0\0"      /* Function keys */
+"789-456+1230.\0\0\0\0\0"       /* Keypad keys */
+"\0\0\0\0\0\0\0\015\0/";
+
+static uchar keyTableShifted[128] =
+"\0\033!@#$%^&*()_+\010"
+"\011QWERTYUIOP{}\015"
+"\0ASDFGHJKL:\"~\0|"
+"ZXCVBNM<>?\0*\0 \0"
+"\0\0\0\0\0\0\0\0\0\0\0\0"      /* Function keys */
+"789-456+1230.\0\0\0\0\0"       /* Keypad keys */
+"\0\0\0\0\0\0\0\015\0/";
+#endif
+
+/* Macros to keep track of the CAPS and NUM lock states */
+
+#define EVT_CAPSSTATE   0x0100
+#define EVT_NUMSTATE    0x0200
+
+/* Helper macros for dealing with timers */
+
+#define TICKS_TO_USEC(t) ((t)*65536.0/1.193180)
+#define USEC_TO_TICKS(u) ((u)*1.193180/65536.0)
+
+/* Number of keycodes to read at a time from the console */
+
+#define KBDREADBUFFERSIZE 32
+
+/*---------------------------- Implementation -----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Returns the current time stamp in units of 18.2 ticks per second.
+****************************************************************************/
+static ulong getTimeStamp(void)
+{
+    return (ulong)(clock() / (CLOCKS_PER_SEC / 18.2));
+}
+
+/****************************************************************************
+PARAMETERS:
+evt - Event to place onto event queue
+
+REMARKS:
+Adds an event to the event queue by tacking it onto the tail of the event
+queue. This routine assumes that at least one spot is available on the
+freeList for the event to be inserted.
+****************************************************************************/
+static void addEvent(
+    WD_event *evt)
+{
+    int         evtID;
+
+    /* Get spot to place the event from the free list */
+    evtID = freeHead;
+    freeHead = evtq[freeHead].next;
+
+    /* Add to the tail of the event queue   */
+    evt->next = -1;
+    evt->prev = tail;
+    if (tail != -1)
+        evtq[tail].next = evtID;
+    else
+        head = evtID;
+    tail = evtID;
+    evtq[evtID] = *evt;
+    count++;
+}
+
+/****************************************************************************
+PARAMETERS:
+what        - Event code
+message     - Event message
+modifiers   - keyboard modifiers
+x           - Mouse X position at time of event
+y           - Mouse Y position at time of event
+but_stat    - Mouse button status at time of event
+
+REMARKS:
+Adds a new mouse event to the event queue. This routine is called from
+within the mouse interrupt subroutine, so it must be efficient.
+****************************************************************************/
+static void addMouseEvent(
+    uint what,
+    uint message,
+    int x,
+    int y,
+    uint but_stat)
+{
+    WD_event    evt;
+
+    if (count < EVENTQSIZE) {
+        evt.what = what;
+        evt.when = getTimeStamp();
+        evt.message = message;
+        evt.modifiers = but_stat | key_modifiers;
+        evt.where_x = x;
+        evt.where_y = y;
+        fprintf(stderr, "(%d,%d), buttons %ld\n", x,y, evt.modifiers);
+        addEvent(&evt);                 /* Add to tail of event queue   */
+        }
+}
+
+/****************************************************************************
+PARAMETERS:
+scancode    - Raw keyboard scan code
+modifiers   - Keyboard modifiers flags
+
+REMARKS:
+Converts the raw scan code into the appropriate ASCII code using the scan
+code and the keyboard modifier flags.
+****************************************************************************/
+static ulong getKeyMessage(
+    uint scancode,
+    ulong modifiers)
+{
+    ushort  code = scancode << 8;
+    ushort  ascii;
+    struct kbentry ke;
+
+    ke.kb_index = scancode;
+
+    /* Find the basic ASCII code for the scan code */
+    if (modifiers & EVT_CAPSSTATE) {
+        if (modifiers & EVT_SHIFTKEY)
+          ke.kb_table = K_NORMTAB;
+        //          ascii = tolower(keyTableShifted[scancode]);
+        else
+          ke.kb_table = K_SHIFTTAB;
+        //          ascii = toupper(keyTable[scancode]);
+        }
+    else {
+        if (modifiers & EVT_SHIFTKEY)
+          ke.kb_table = K_SHIFTTAB;
+          // ascii = keyTableShifted[scancode];
+        else
+          ke.kb_table = K_NORMTAB;
+          // ascii = keyTable[scancode];
+        }
+    if(modifiers & EVT_ALTSTATE)
+      ke.kb_table |= K_ALTTAB;
+
+    if (ioctl(tty_fd, KDGKBENT, (unsigned long)&ke)) {
+        fprintf(stderr, "KDGKBENT at index %d in table %d: ",
+            scancode, ke.kb_table);
+        return 0;
+    }
+    ascii = ke.kb_value;
+
+    /* Add ASCII code if key is not alt'ed or ctrl'ed */
+    if (!(modifiers & (EVT_ALTSTATE | EVT_CTRLSTATE)))
+        code |= ascii;
+
+    return code;
+}
+
+/****************************************************************************
+PARAMETERS:
+what        - Event code
+scancode    - Raw scancode of keyboard event to add
+
+REMARKS:
+Adds a new keyboard event to the event queue. We only take KEYUP and
+KEYDOWN event codes, however if a key is already down we convert the KEYDOWN
+to a KEYREPEAT.
+****************************************************************************/
+static void addKeyEvent(
+    uint what,
+    uint scancode)
+{
+    WD_event    evt;
+
+    if (count < EVENTQSIZE) {
+        evt.what = what;
+        evt.when = getTimeStamp();
+        evt.message = getKeyMessage(scancode,key_modifiers) | 0x10000UL;
+        evt.where_x = evt.where_y = 0;
+        evt.modifiers = key_modifiers;
+        if (evt.what == EVT_KEYUP)
+            key_down[scancode] = false;
+        else if (evt.what == EVT_KEYDOWN) {
+            if (key_down[scancode]) {
+                if (oldKey != -1) {
+                    evtq[oldKey].message += 0x10000UL;
+                    }
+                else {
+                    evt.what = EVT_KEYREPEAT;
+                    oldKey = freeHead;
+                    addEvent(&evt);
+                    oldMove = -1;
+                    }
+                return;
+                }
+            key_down[scancode] = true;
+            }
+
+        addEvent(&evt);
+        oldMove = -1;
+        }
+}
+
+/****************************************************************************
+PARAMETERS:
+sig - Signal being sent to this signal handler
+
+REMARKS:
+Signal handler for the timer. This routine takes care of periodically
+posting timer events to the event queue.
+****************************************************************************/
+void timerHandler(
+    int sig)
+{
+    WD_event    evt;
+
+    if (sig == SIGALRM) {
+        if (count < EVENTQSIZE) {
+            evt.when = getTimeStamp();
+            evt.what = EVT_TIMERTICK;
+            evt.message = 0;
+            evt.where_x = evt.where_y = 0;
+            evt.modifiers = 0;
+            addEvent(&evt);
+            oldMove = -1;
+            oldKey = -1;
+            }
+        signal(SIGALRM, timerHandler);
+        }
+}
+
+/****************************************************************************
+REMARKS:
+Restore the terminal to normal operation on exit
+****************************************************************************/
+static void restore_term(void)
+{
+    RMREGS  regs;
+
+    if (installed) {
+        /* Restore text mode and the state of the console */
+        regs.x.ax = 0x3;
+        PM_int86(0x10,&regs,&regs);
+        PM_restoreConsoleState(stateBuf,tty_fd);
+
+        /* Restore console to normal operation */
+        ioctl(tty_fd, VT_SETMODE, &oldvtmode);
+        ioctl(tty_fd, KDSKBMODE, oldkbmode);
+        tcsetattr(tty_fd, TCSAFLUSH, &old_conf);
+        fcntl(tty_fd,F_SETFL,old_flags &= ~O_NONBLOCK);
+        PM_closeConsole(tty_fd);
+
+        /* Close the mouse driver */
+        close(conn);
+
+        /* Flag that we are not no longer installed */
+        installed = false;
+        }
+}
+
+/****************************************************************************
+REMARKS:
+Signal handler to capture forced program termination conditions so that
+we can clean up properly.
+****************************************************************************/
+static void exitHandler(int sig)
+{
+    exit(-1);
+}
+
+/****************************************************************************
+REMARKS:
+Sleep until the virtual terminal is active
+****************************************************************************/
+void wait_vt_active(void)
+{
+    while (ioctl(tty_fd, VT_WAITACTIVE, tty_vc) < 0) {
+        if ((errno != EAGAIN) && (errno != EINTR)) {
+            perror("ioctl(VT_WAITACTIVE)");
+            exit(1);
+            }
+        usleep(150000);
+        }
+}
+
+/****************************************************************************
+REMARKS:
+Signal handler called when our virtual terminal has been released and we are
+losing the active focus.
+****************************************************************************/
+static void release_vt_signal(int n)
+{
+    forbid_vt_acquire = 1;
+    if (forbid_vt_release) {
+        forbid_vt_acquire = 0;
+        ioctl(tty_fd, VT_RELDISP, 0);
+        return;
+        }
+
+    // TODO: Call the user supplied suspendAppCallback and restore text
+    //       mode (saving the existing mode so we can restore it).
+    //
+    //       Also if the suspendAppCallback is NULL then we have to
+    //       ignore the switch request!
+    if(suspendAppCallback){
+      oldmode = VBE_getVideoMode();
+      suspendAppCallback(true);
+      VBE_setVideoMode(initmode);
+    }
+
+    ioctl(tty_fd, VT_RELDISP, 1);
+    forbid_vt_acquire = 0;
+    wait_vt_active();
+}
+
+/****************************************************************************
+REMARKS:
+Signal handler called when our virtual terminal has been re-aquired and we
+are now regaiing the active focus.
+****************************************************************************/
+static void acquire_vt_signal(int n)
+{
+    forbid_vt_release = 1;
+    if (forbid_vt_acquire) {
+        forbid_vt_release = 0;
+        return;
+        }
+
+    // TODO: Restore the old display mode, call the user suspendAppCallback
+    //       and and we will be back in graphics mode.
+
+    if(suspendAppCallback){
+      VBE_setVideoMode(oldmode);
+      suspendAppCallback(false);
+    }
+
+    ioctl(tty_fd, VT_RELDISP, VT_ACKACQ);
+    forbid_vt_release = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to set the action for a specific signal to call our signal handler.
+****************************************************************************/
+static void set_sigaction(int sig,void (*handler)(int))
+{
+    struct sigaction    siga;
+
+    siga.sa_handler = handler;
+    siga.sa_flags = SA_RESTART;
+    memset(&(siga.sa_mask), 0, sizeof(sigset_t));
+    sigaction(sig, &siga, NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Function to take over control of VT switching so that we can capture
+virtual terminal release and aquire signals, allowing us to properly
+support VT switching while in graphics modes.
+****************************************************************************/
+static void take_vt_control(void)
+{
+    struct vt_mode      vtmode;
+
+    ioctl(tty_fd, VT_GETMODE, &vtmode);
+    oldvtmode = vtmode;
+    vtmode.mode = VT_PROCESS;
+    vtmode.relsig = SIGUSR1;
+    vtmode.acqsig = SIGUSR2;
+    set_sigaction(SIGUSR1, release_vt_signal);
+    set_sigaction(SIGUSR2, acquire_vt_signal);
+    ioctl(tty_fd, VT_SETMODE, &oldvtmode);
+}
+
+/****************************************************************************
+REMARKS:
+Set the shift keyboard LED's based on the current keyboard modifiers flags.
+****************************************************************************/
+static void updateLEDStatus(void)
+{
+    int state = 0;
+    if (key_modifiers & EVT_CAPSSTATE)
+        state |= LED_CAP;
+    if (key_modifiers & EVT_NUMSTATE)
+        state |= LED_NUM;
+    ioctl(tty_fd,KDSETLED,state);
+}
+
+/****************************************************************************
+PARAMETERS:
+scancode    - Raw scan code to handle
+
+REMARKS:
+Handles the shift key modifiers and keeps track of the shift key states
+so that we can return the correct ASCII codes for the keyboard.
+****************************************************************************/
+static void toggleModifiers(
+    int scancode)
+{
+    static int caps_down = 0,num_down = 0;
+
+    if (scancode & 0x80) {
+        /* Handle key-release function */
+        scancode &= 0x7F;
+        if (scancode == 0x2A || scancode == 0x36)
+            key_modifiers &= ~EVT_SHIFTKEY;
+        else if (scancode == 0x1D || scancode == 0x61)
+            key_modifiers &= ~EVT_CTRLSTATE;
+        else if (scancode == 0x38 || scancode == 0x64)
+            key_modifiers &= ~EVT_ALTSTATE;
+        else if (scancode == 0x3A)
+            caps_down = false;
+        else if (scancode == 0x45)
+            num_down = false;
+        }
+    else {
+        /* Handle key-down function */
+        scancode &= 0x7F;
+        if (scancode == 0x2A || scancode == 0x36)
+            key_modifiers |= EVT_SHIFTKEY;
+        else if (scancode == 0x1D || scancode == 0x61)
+            key_modifiers |= EVT_CTRLSTATE;
+        else if (scancode == 0x38 || scancode == 0x64)
+            key_modifiers |= EVT_ALTSTATE;
+        else if (scancode == 0x3A) {
+            if (!caps_down) {
+                key_modifiers ^= EVT_CAPSSTATE;
+                updateLEDStatus();
+                }
+            caps_down = true;
+            }
+        else if (scancode == 0x45) {
+            if (!num_down) {
+                key_modifiers ^= EVT_NUMSTATE;
+                updateLEDStatus();
+                }
+            num_down = true;
+            }
+        }
+}
+
+/***************************************************************************
+REMARKS:
+Returns the number of bits that have changed from 0 to 1
+(a negative value means the number of bits that have changed from 1 to 0) 
+ **************************************************************************/
+static int compareBits(short a, short b)
+{
+    int ret = 0;
+    if( (a&1) != (b&1) ) ret += (b&1) ? 1 : -1;
+    if( (a&2) != (b&2) ) ret += (b&2) ? 1 : -1;
+    if( (a&4) != (b&4) ) ret += (b&4) ? 1 : -1;
+    return ret;
+}
+
+/***************************************************************************
+REMARKS:
+Turns off all keyboard state because we can't rely on them anymore as soon
+as we switch VT's
+***************************************************************************/
+static void keyboard_clearstate(void)
+{
+  key_modifiers = 0;
+  memset(key_down, 0, sizeof(key_down));
+}
+
+/****************************************************************************
+REMARKS:
+Pumps all events from the console event queue into the WinDirect event queue.
+****************************************************************************/
+static void pumpEvents(void)
+{
+    static uchar    buf[KBDREADBUFFERSIZE];
+    static char     data[5];
+    static int      old_buts, old_mx, old_my;
+    static struct timeval t;
+    fd_set fds;
+    int             numkeys,i;
+    int             dx, dy, buts;
+
+    /* Read all pending keypresses from keyboard buffer and process */
+    while ((numkeys = read(tty_fd, buf, KBDREADBUFFERSIZE)) > 0) {
+        for (i = 0; i < numkeys; i++) {
+            toggleModifiers(buf[i]);
+            if (key_modifiers & EVT_ALTSTATE){
+              int fkey = 0;
+
+              // Do VT switching here for Alt+Fx keypresses
+              switch(buf[i] & 0x7F){
+              case 59 ... 68: /* F1 to F10 */
+                fkey = (buf[i] & 0x7F) - 58;
+                break;
+              case 87: /* F11 */
+              case 88: /* F12 */
+                fkey = (buf[i] & 0x7F) - 76;
+                break;
+              }
+              if(fkey){
+                struct vt_stat vts;
+                ioctl(tty_fd, VT_GETSTATE, &vts);
+                
+                if(fkey != vts.v_active){
+                  keyboard_clearstate();
+                  ioctl(tty_fd, VT_ACTIVATE, fkey);
+                }
+              }
+            }
+
+            if (buf[i] & 0x80)
+                addKeyEvent(EVT_KEYUP,buf[i] & 0x7F);
+            else
+                addKeyEvent(EVT_KEYDOWN,buf[i] & 0x7F);
+            }
+
+        // TODO: If we want to handle VC switching we will need to do it
+        //       in here so that we can switch away from the VC and then
+        //       switch back to it later. Right now VC switching is disabled
+        //       and in order to enable it we need to save/restore the state
+        //       of the graphics screen (using the suspendAppCallback and
+        //       saving/restoring the state of the current display mode).
+
+        }
+
+    /* Read all pending mouse events and process them */
+    if(conn > 0){
+        FD_ZERO(&fds);
+        FD_SET(conn, &fds);
+        t.tv_sec = t.tv_usec = 0L;
+        while (select(conn+1, &fds, NULL, NULL, &t) > 0) {
+            if(read(conn, data, 5) == 5){
+                buts = (~data[0]) & 0x07;
+                dx = (char)(data[1]) + (char)(data[3]);
+                dy = -((char)(data[2]) + (char)(data[4]));
+                
+                mx += dx; my += dy;
+                
+                if (dx || dy)
+                    addMouseEvent(EVT_MOUSEMOVE, 0, mx, my, buts);
+                
+                if (buts != old_buts){
+                    int c = compareBits(buts,old_buts);
+                    if(c>0)
+                        addMouseEvent(EVT_MOUSEDOWN, 0, mx, my, buts);
+                    else if(c<0)
+                        addMouseEvent(EVT_MOUSEUP, 0, mx, my, buts);
+                }
+                old_mx = mx; old_my = my;
+                old_buts = buts;
+                FD_SET(conn, &fds);
+                t.tv_sec = t.tv_usec = 0L;
+            }
+        }
+    }
+}
+
+/*------------------------ Public interface routines ----------------------*/
+
+/****************************************************************************
+PARAMETERS:
+which       - Which code for event to post
+what        - Event code for event to post
+message     - Event message
+modifiers   - Shift key/mouse button modifiers
+
+RETURNS:
+True if the event was posted, false if queue is full.
+
+REMARKS:
+Posts an event to the event queue. This routine can be used to post any type
+of event into the queue.
+****************************************************************************/
+ibool _WDAPI WD_postEvent(
+    ulong which,
+    uint what,
+    ulong message,
+    ulong modifiers)
+{
+    WD_event    evt;
+
+    if (count < EVENTQSIZE) {
+        /* Save information in event record */
+        evt.which = which;
+        evt.what = what;
+        evt.when = getTimeStamp();
+        evt.message = message;
+        evt.modifiers = modifiers;
+        addEvent(&evt);             /* Add to tail of event queue   */
+        return true;
+        }
+    else
+        return false;
+}
+
+/****************************************************************************
+PARAMETERS:
+mask    - Event mask to use
+
+REMARKS:
+Flushes all the event specified in 'mask' from the event queue.
+****************************************************************************/
+void _WDAPI WD_flushEvent(
+    uint mask)
+{
+    WD_event    evt;
+
+    do {                            /* Flush all events */
+        WD_getEvent(&evt,mask);
+        } while (evt.what != EVT_NULLEVT);
+}
+
+/****************************************************************************
+PARAMETERS:
+evt     - Place to store event
+mask    - Event mask to use
+
+REMARKS:
+Halts program execution until a specified event occurs. The event is
+returned. All pending events not in the specified mask will be ignored and
+removed from the queue.
+****************************************************************************/
+void _WDAPI WD_haltEvent(
+    WD_event *evt,
+    uint mask)
+{
+    do {                            /* Wait for an event    */
+        WD_getEvent(evt,EVT_EVERYEVT);
+        } while (!(evt->what & mask));
+}
+
+/****************************************************************************
+PARAMETERS:
+evt     - Place to store event
+mask    - Event mask to use
+
+RETURNS:
+True if an event was pending.
+
+REMARKS:
+Retrieves the next pending event defined in 'mask' from the event queue.
+The event queue is adjusted to reflect the new state after the event has
+been removed.
+****************************************************************************/
+ibool _WDAPI WD_getEvent(
+    WD_event *evt,
+    uint mask)
+{
+    int     evtID,next,prev;
+
+    pumpEvents();
+    if (moveCursor)
+        moveCursor(mx,my);                  /* Move the mouse cursor    */
+    evt->what = EVT_NULLEVT;                /* Default to null event    */
+
+    if (count) {
+        for (evtID = head; evtID != -1; evtID = evtq[evtID].next) {
+            if (evtq[evtID].what & mask)
+                break;                      /* Found an event           */
+            }
+        if (evtID == -1)
+            return false;                   /* Event was not found      */
+        next = evtq[evtID].next;
+        prev = evtq[evtID].prev;
+        if (prev != -1)
+            evtq[prev].next = next;
+        else
+            head = next;
+        if (next != -1)
+            evtq[next].prev = prev;
+        else
+            tail = prev;
+        *evt = evtq[evtID];                 /* Return the event         */
+        evtq[evtID].next = freeHead;        /* and return to free list  */
+        freeHead = evtID;
+        count--;
+        if (evt->what == EVT_MOUSEMOVE)
+            oldMove = -1;
+        if (evt->what == EVT_KEYREPEAT)
+            oldKey = -1;
+        }
+    return evt->what != EVT_NULLEVT;
+}
+
+/****************************************************************************
+PARAMETERS:
+evt     - Place to store event
+mask    - Event mask to use
+
+RETURNS:
+True if an event is pending.
+
+REMARKS:
+Peeks at the next pending event defined in 'mask' in the event queue. The
+event is not removed from the event queue.
+****************************************************************************/
+ibool _WDAPI WD_peekEvent(
+    WD_event *evt,
+    uint mask)
+{
+    int     evtID;
+
+    pumpEvents();
+    if (moveCursor)
+        moveCursor(mx,my);                  /* Move the mouse cursor    */
+    evt->what = EVT_NULLEVT;                /* Default to null event    */
+
+    if (count) {
+        for (evtID = head; evtID != -1; evtID = evtq[evtID].next) {
+            if (evtq[evtID].what & mask)
+                break;                      /* Found an event           */
+            }
+        if (evtID == -1)
+            return false;                   /* Event was not found      */
+
+        *evt = evtq[evtID];                 /* Return the event         */
+        }
+    return evt->what != EVT_NULLEVT;
+}
+
+/****************************************************************************
+PARAMETERS:
+hwndMain    - Handle to main window
+_xRes       - X resolution of graphics mode to be used
+_yRes       - Y resolulion of graphics mode to be used
+
+RETURNS:
+Handle to the fullscreen event window if (we return hwndMain on Linux)
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling
+ISR to be called whenever any button's are pressed or released. We also
+build the free list of events in the event queue.
+****************************************************************************/
+WD_HWND _WDAPI WD_startFullScreen(
+    WD_HWND hwndMain,
+    int _xRes,
+    int _yRes)
+{
+    int             i;
+    struct termios  conf;
+    if (!installed) {
+        Gpm_Connect gpm;
+
+        /* Build free list, and initialise global data structures */
+        for (i = 0; i < EVENTQSIZE; i++)
+            evtq[i].next = i+1;
+        evtq[EVENTQSIZE-1].next = -1;       /* Terminate list           */
+        count = freeHead = 0;
+        head = tail = -1;
+        oldMove = -1;
+        oldKey = -1;
+        xRes = _xRes;
+        yRes = _yRes;
+
+        /* Open the console device and initialise it for raw mode */
+        tty_fd = PM_openConsole();
+
+        /* Wait until virtual terminal is active and take over control */
+        wait_vt_active();
+        take_vt_control();
+
+        /* Initialise keyboard handling to raw mode */
+        if (ioctl(tty_fd, KDGKBMODE, &oldkbmode)) {
+            printf("WD_startFullScreen: cannot get keyboard mode.\n");
+            exit(-1);
+            }
+        old_flags = fcntl(tty_fd,F_GETFL);
+        fcntl(tty_fd,F_SETFL,old_flags |= O_NONBLOCK);
+        tcgetattr(tty_fd, &conf);
+        old_conf = conf;
+        conf.c_lflag &= ~(ICANON | ECHO | ECHOE | ECHOK | ECHONL | NOFLSH | ISIG);
+        conf.c_iflag &= ~(ISTRIP | IGNCR | ICRNL | INLCR | BRKINT | PARMRK | INPCK | IUCLC | IXON | IXOFF);
+        conf.c_iflag  |= (IGNBRK | IGNPAR);
+        conf.c_cc[VMIN] = 1;
+        conf.c_cc[VTIME] = 0;
+        conf.c_cc[VSUSP] = 0;
+        tcsetattr(tty_fd, TCSAFLUSH, &conf);
+        ioctl(tty_fd, KDSKBMODE, K_MEDIUMRAW);
+
+        /* Clear the keyboard state information */
+        memset(key_down, 0, sizeof(key_down));
+        ioctl(tty_fd,KDSETLED,key_modifiers = 0);
+
+        /* Initialize the mouse connection 
+           The user *MUST* run gpm with the  option -R for this to work (or have a MouseSystems mouse)
+        */
+        if(Gpm_Open(&gpm,0) > 0){ /* GPM available */
+            if ((conn = open(GPM_NODE_FIFO,O_RDONLY|O_SYNC)) < 0)
+                fprintf(stderr,"WD_startFullScreen: Can't open mouse connection.\n");
+        }else{
+            fprintf(stderr,"Warning: when not using gpm -R, only MouseSystems mice are currently supported.\n");
+            if ((conn = open("/dev/mouse",O_RDONLY|O_SYNC)) < 0)
+                fprintf(stderr,"WD_startFullScreen: Can't open /dev/mouse.\n");
+        }
+        Gpm_Close();
+
+        /* TODO: Scale the mouse coordinates to the specific resolution */
+
+        /* Save the state of the console */
+        if ((stateBuf = malloc(PM_getConsoleStateSize())) == NULL) {
+            printf("Out of memory!\n");
+            exit(-1);
+            }
+        PM_saveConsoleState(stateBuf,tty_fd);
+        initmode = VBE_getVideoMode();
+
+        /* Initialize the signal handler for timer events */
+        signal(SIGALRM, timerHandler);
+
+        /* Capture termination signals so we can clean up properly */
+        signal(SIGTERM, exitHandler);
+        signal(SIGINT, exitHandler);
+        signal(SIGQUIT, exitHandler);
+        atexit(restore_term);
+
+        /* Signal that we are installed */
+        installed = true;
+        }
+    return hwndMain;
+}
+
+/****************************************************************************
+REMARKS:
+Lets the library know when fullscreen graphics mode has been initialized so
+that we can properly scale the mouse driver coordinates.
+****************************************************************************/
+void _WDAPI WD_inFullScreen(void)
+{
+    /* Nothing to do in here */
+}
+
+/****************************************************************************
+REMARKS:
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void _WDAPI WD_restoreGDI(void)
+{
+    restore_term();
+}
+
+/****************************************************************************
+PARAMETERS:
+ticks   - Number of ticks between timer tick messages
+
+RETURNS:
+Previous value for the timer tick event spacing.
+
+REMARKS:
+The event module will automatically generate periodic timer tick events for
+you, with 'ticks' between each event posting. If you set the value of
+'ticks' to 0, the timer tick events are turned off.
+****************************************************************************/
+int _WDAPI WD_setTimerTick(
+    int ticks)
+{
+    int                 old;
+    struct itimerval    tim;
+    long                ms = TICKS_TO_USEC(ticks);
+
+    getitimer(ITIMER_REAL, &tim);
+    old = USEC_TO_TICKS(tim.it_value.tv_sec*1000000.0 + tim.it_value.tv_usec);
+    tim.it_interval.tv_sec  = ms / 1000000;
+    tim.it_interval.tv_usec = ms % 1000000;
+    setitimer(ITIMER_REAL, &tim, NULL);
+    return old;
+}
+
+/****************************************************************************
+PARAMETERS:
+saveState   - Address of suspend app callback to register
+
+REMARKS:
+Registers a user application supplied suspend application callback so that
+we can properly handle virtual terminal switching.
+****************************************************************************/
+void _WDAPI WD_setSuspendAppCallback(
+    int (_ASMAPI *saveState)(int flags))
+{
+  suspendAppCallback = saveState;
+}
+
+/****************************************************************************
+PARAMETERS:
+x   - New X coordinate to move the mouse cursor to
+y   - New Y coordinate to move the mouse cursor to
+
+REMARKS:
+Moves to mouse cursor to the specified coordinate.
+****************************************************************************/
+void _WDAPI WD_setMousePos(
+    int x,
+    int y)
+{
+    mx = x;
+    my = y;
+}
+
+/****************************************************************************
+PARAMETERS:
+x   - Place to store X coordinate of mouse cursor
+y   - Place to store Y coordinate of mouse cursor
+
+REMARKS:
+Reads the current mouse cursor location int *screen* coordinates.
+****************************************************************************/
+void _WDAPI WD_getMousePos(
+    int *x,
+    int *y)
+{
+    *x = mx;
+    *y = my;
+}
+
+/****************************************************************************
+PARAMETERS:
+mcb - Address of mouse callback function
+
+REMARKS:
+Registers an application supplied mouse callback function that is called
+whenever the mouse cursor moves.
+****************************************************************************/
+void _WDAPI WD_setMouseCallback(
+    void (_ASMAPI *mcb)(int x,int y))
+{
+    moveCursor = mcb;
+}
+
+/****************************************************************************
+PARAMETERS:
+xRes    - New X resolution of graphics mode
+yRes    - New Y resolution of graphics mode
+
+REMARKS:
+This is called to inform the event handling code that the screen resolution
+has changed so that the mouse coordinates can be scaled appropriately.
+****************************************************************************/
+void _WDAPI WD_changeResolution(
+    int xRes,
+    int yRes)
+{
+    //  Gpm_FitValues(xRes, yRes);  // ??
+}
+
+/****************************************************************************
+PARAMETERS:
+scancode    - Scan code to check if a key is down
+
+REMARKS:
+Determines if a particular key is down based on the scan code for the key.
+****************************************************************************/
+ibool _WDAPI WD_isKeyDown(
+    uchar scancode)
+{   
+    return key_down[scancode];
+}
+
+/****************************************************************************
+REMARKS:
+Determines if the application needs to run in safe mode. Not necessary for
+anything but broken Windows 95 display drivers so we return false for
+Linux.
+****************************************************************************/
+int _WDAPI WD_isSafeMode(void)
+{
+    return false;
+}
+
+
diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h
new file mode 100755
index 0000000..eadedfb
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h
@@ -0,0 +1,60 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux
+*
+* Description:  Include all the OS specific header files.
+*
+****************************************************************************/
+
+#include <fcntl.h>
+#include <sys/time.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+#include <time.h>
+#include <linux/keyboard.h>
+#include <linux/kd.h>
+#include <linux/vt.h>
+#include <linux/fs.h>
+#ifdef USE_OS_JOYSTICK
+#include <linux/joystick.h>
+#endif
+#include <termios.h>
+#include <signal.h>
+#include <unistd.h>
+#include <ctype.h>
+#include <stdlib.h>
+
+/* Internal global variables */
+
+extern int _PM_console_fd,_PM_leds,_PM_modifiers;
+
+/* Internal function prototypes */
+
+void _PM_restore_kb_mode(void);
+void _PM_keyboard_rawmode(void);
+
+/* Linux needs the generic joystick scaling code */
+
+#define NEED_SCALE_JOY_AXIS
diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c b/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c
new file mode 100755
index 0000000..c12a835
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c
@@ -0,0 +1,1809 @@
+;/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*                   Portions copyright (C) Josh Vanderhoof
+*
+* Language:     ANSI C
+* Environment:  Linux
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <sys/kd.h>
+#include <sys/ioctl.h>
+#include <sys/stat.h>
+#include <sys/vt.h>
+#include <sys/wait.h>
+#include <sys/types.h>
+#include <sys/time.h>
+#include <unistd.h>
+#include <termios.h>
+#include <fcntl.h>
+#include <syscall.h>
+#include <signal.h>
+#include <time.h>
+#include <ctype.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#ifdef ENABLE_MTRR
+#include <asm/mtrr.h>
+#endif
+#include <asm/vm86.h>
+#ifdef __GLIBC__
+#include <sys/perm.h>
+#endif
+
+/*--------------------------- Global variables ----------------------------*/
+
+#define REAL_MEM_BASE       ((void *)0x10000)
+#define REAL_MEM_SIZE       0x10000
+#define REAL_MEM_BLOCKS     0x100
+#define DEFAULT_VM86_FLAGS  (IF_MASK | IOPL_MASK)
+#define DEFAULT_STACK_SIZE  0x1000
+#define RETURN_TO_32_INT    255
+
+/* Quick and dirty fix for vm86() syscall from lrmi 0.6 */
+static int
+vm86(struct vm86_struct *vm)
+    {
+    int r;
+#ifdef __PIC__
+    asm volatile (
+     "pushl %%ebx\n\t"
+     "movl %2, %%ebx\n\t"
+     "int $0x80\n\t"
+     "popl %%ebx"
+     : "=a" (r)
+     : "0" (113), "r" (vm));
+#else
+    asm volatile (
+     "int $0x80"
+     : "=a" (r)
+     : "0" (113), "b" (vm));
+#endif
+    return r;
+    }
+
+
+static struct {
+    int                 ready;
+    unsigned short      ret_seg, ret_off;
+    unsigned short      stack_seg, stack_off;
+    struct vm86_struct  vm;
+    } context = {0};
+
+struct mem_block {
+    unsigned int size : 20;
+    unsigned int free : 1;
+    };
+
+static struct {
+    int ready;
+    int count;
+    struct mem_block blocks[REAL_MEM_BLOCKS];
+    } mem_info = {0};
+
+int                     _PM_console_fd = -1;
+int                     _PM_leds = 0,_PM_modifiers = 0;
+static ibool            inited = false;
+static int              tty_vc = 0;
+static int              console_count = 0;
+static int              startup_vc;
+static int              fd_mem = 0;
+static ibool            in_raw_mode = false;
+#ifdef ENABLE_MTRR
+static int              mtrr_fd;
+#endif
+static uint VESABuf_len = 1024;     /* Length of the VESABuf buffer     */
+static void *VESABuf_ptr = NULL;    /* Near pointer to VESABuf          */
+static uint VESABuf_rseg;           /* Real mode segment of VESABuf     */
+static uint VESABuf_roff;           /* Real mode offset of VESABuf      */
+#ifdef TRACE_IO
+static ulong            traceAddr;
+#endif
+
+static void (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+#ifdef  TRACE_IO
+extern void printk(char *msg,...);
+#endif
+
+static inline void port_out(int value, int port)
+{
+#ifdef TRACE_IO
+    printk("%04X:%04X: outb.%04X <- %02X\n", traceAddr >> 16, traceAddr & 0xFFFF, (ushort)port, (uchar)value);
+#endif
+    asm volatile ("outb %0,%1"
+	  ::"a" ((unsigned char) value), "d"((unsigned short) port));
+}
+
+static inline void port_outw(int value, int port)
+{
+#ifdef TRACE_IO
+    printk("%04X:%04X: outw.%04X <- %04X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ushort)value);
+#endif
+    asm volatile ("outw %0,%1"
+	 ::"a" ((unsigned short) value), "d"((unsigned short) port));
+}
+
+static inline void port_outl(int value, int port)
+{
+#ifdef TRACE_IO
+    printk("%04X:%04X: outl.%04X <- %08X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ulong)value);
+#endif
+    asm volatile ("outl %0,%1"
+	 ::"a" ((unsigned long) value), "d"((unsigned short) port));
+}
+
+static inline unsigned int port_in(int port)
+{
+    unsigned char value;
+    asm volatile ("inb %1,%0"
+	      :"=a" ((unsigned char)value)
+	      :"d"((unsigned short) port));
+#ifdef TRACE_IO
+    printk("%04X:%04X:  inb.%04X -> %02X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (uchar)value);
+#endif
+    return value;
+}
+
+static inline unsigned int port_inw(int port)
+{
+    unsigned short value;
+    asm volatile ("inw %1,%0"
+	      :"=a" ((unsigned short)value)
+	      :"d"((unsigned short) port));
+#ifdef TRACE_IO
+    printk("%04X:%04X:  inw.%04X -> %04X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ushort)value);
+#endif
+    return value;
+}
+
+static inline unsigned int port_inl(int port)
+{
+    unsigned long value;
+    asm volatile ("inl %1,%0"
+	      :"=a" ((unsigned long)value)
+	      :"d"((unsigned short) port));
+#ifdef TRACE_IO
+    printk("%04X:%04X:  inl.%04X -> %08X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ulong)value);
+#endif
+    return value;
+}
+
+static int real_mem_init(void)
+{
+    void    *m;
+    int     fd_zero;
+
+    if (mem_info.ready)
+	return 1;
+
+    if ((fd_zero = open("/dev/zero", O_RDONLY)) == -1)
+	PM_fatalError("You must have root privledges to run this program!");
+    if ((m = mmap((void *)REAL_MEM_BASE, REAL_MEM_SIZE,
+	    PROT_READ | PROT_WRITE | PROT_EXEC,
+	    MAP_FIXED | MAP_PRIVATE, fd_zero, 0)) == (void *)-1) {
+	close(fd_zero);
+	PM_fatalError("You must have root privledges to run this program!");
+	}
+    mem_info.ready = 1;
+    mem_info.count = 1;
+    mem_info.blocks[0].size = REAL_MEM_SIZE;
+    mem_info.blocks[0].free = 1;
+    return 1;
+}
+
+static void insert_block(int i)
+{
+    memmove(
+	mem_info.blocks + i + 1,
+	mem_info.blocks + i,
+	(mem_info.count - i) * sizeof(struct mem_block));
+    mem_info.count++;
+}
+
+static void delete_block(int i)
+{
+    mem_info.count--;
+
+    memmove(
+	mem_info.blocks + i,
+	mem_info.blocks + i + 1,
+	(mem_info.count - i) * sizeof(struct mem_block));
+}
+
+static inline void set_bit(unsigned int bit, void *array)
+{
+    unsigned char *a = array;
+    a[bit / 8] |= (1 << (bit % 8));
+}
+
+static inline unsigned int get_int_seg(int i)
+{
+    return *(unsigned short *)(i * 4 + 2);
+}
+
+static inline unsigned int get_int_off(int i)
+{
+    return *(unsigned short *)(i * 4);
+}
+
+static inline void pushw(unsigned short i)
+{
+    struct vm86_regs *r = &context.vm.regs;
+    r->esp -= 2;
+    *(unsigned short *)(((unsigned int)r->ss << 4) + r->esp) = i;
+}
+
+ibool PMAPI PM_haveBIOSAccess(void)
+{ return true; }
+
+void PMAPI PM_init(void)
+{
+    void    *m;
+    uint    r_seg,r_off;
+
+    if (inited)
+	return;
+
+    /* Map the Interrupt Vectors (0x0 - 0x400) + BIOS data (0x400 - 0x502)
+     * and the physical framebuffer and ROM images from (0xa0000 - 0x100000)
+     */
+    real_mem_init();
+    if (!fd_mem && (fd_mem = open("/dev/mem", O_RDWR)) == -1) {
+	PM_fatalError("You must have root privileges to run this program!");
+	}
+    if ((m = mmap((void *)0, 0x502,
+	    PROT_READ | PROT_WRITE | PROT_EXEC,
+	    MAP_FIXED | MAP_PRIVATE, fd_mem, 0)) == (void *)-1) {
+	PM_fatalError("You must have root privileges to run this program!");
+	}
+    if ((m = mmap((void *)0xA0000, 0xC0000 - 0xA0000,
+	    PROT_READ | PROT_WRITE,
+	    MAP_FIXED | MAP_SHARED, fd_mem, 0xA0000)) == (void *)-1) {
+	PM_fatalError("You must have root privileges to run this program!");
+	}
+    if ((m = mmap((void *)0xC0000, 0xD0000 - 0xC0000,
+	    PROT_READ | PROT_WRITE | PROT_EXEC,
+	    MAP_FIXED | MAP_PRIVATE, fd_mem, 0xC0000)) == (void *)-1) {
+	PM_fatalError("You must have root privileges to run this program!");
+	}
+    if ((m = mmap((void *)0xD0000, 0x100000 - 0xD0000,
+	    PROT_READ | PROT_WRITE,
+	    MAP_FIXED | MAP_SHARED, fd_mem, 0xD0000)) == (void *)-1) {
+	PM_fatalError("You must have root privileges to run this program!");
+	}
+    inited = 1;
+
+    /* Allocate a stack */
+    m = PM_allocRealSeg(DEFAULT_STACK_SIZE,&r_seg,&r_off);
+    context.stack_seg = r_seg;
+    context.stack_off = r_off+DEFAULT_STACK_SIZE;
+
+    /* Allocate the return to 32 bit routine */
+    m = PM_allocRealSeg(2,&r_seg,&r_off);
+    context.ret_seg = r_seg;
+    context.ret_off = r_off;
+    ((uchar*)m)[0] = 0xCD;         /* int opcode */
+    ((uchar*)m)[1] = RETURN_TO_32_INT;
+    memset(&context.vm, 0, sizeof(context.vm));
+
+    /* Enable kernel emulation of all ints except RETURN_TO_32_INT */
+    memset(&context.vm.int_revectored, 0, sizeof(context.vm.int_revectored));
+    set_bit(RETURN_TO_32_INT, &context.vm.int_revectored);
+    context.ready = 1;
+#ifdef ENABLE_MTRR
+    mtrr_fd =  open("/dev/cpu/mtrr", O_RDWR, 0);
+    if (mtrr_fd < 0)
+       mtrr_fd =  open("/proc/mtrr", O_RDWR, 0);
+#endif
+    /* Enable I/O permissions to directly access I/O ports. We break the
+     * allocation into two parts, one for the ports from 0-0x3FF and
+     * another for the remaining ports up to 0xFFFF. Standard Linux kernels
+     * only allow the first 0x400 ports to be enabled, so to enable all
+     * 65536 ports you need a patched kernel that will enable the full
+     * 8Kb I/O permissions bitmap.
+     */
+#ifndef TRACE_IO
+    ioperm(0x0,0x400,1);
+    ioperm(0x400,0x10000-0x400,1);
+#endif
+    iopl(3);
+}
+
+long PMAPI PM_getOSType(void)
+{ return _OS_LINUX; }
+
+int PMAPI PM_getModeType(void)
+{ return PM_386; }
+
+void PMAPI PM_backslash(char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '/') {
+	s[pos] = '/';
+	s[pos+1] = '\0';
+	}
+}
+
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+void PMAPI PM_fatalError(const char *msg)
+{
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+    fprintf(stderr,"%s\n", msg);
+    fflush(stderr);
+    exit(1);
+}
+
+static void ExitVBEBuf(void)
+{
+    if (VESABuf_ptr)
+	PM_freeRealSeg(VESABuf_ptr);
+    VESABuf_ptr = 0;
+}
+
+void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff)
+{
+    if (!VESABuf_ptr) {
+	/* Allocate a global buffer for communicating with the VESA VBE */
+	if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL)
+	    return NULL;
+	atexit(ExitVBEBuf);
+	}
+    *len = VESABuf_len;
+    *rseg = VESABuf_rseg;
+    *roff = VESABuf_roff;
+    return VESABuf_ptr;
+}
+
+/* New raw console based getch and kbhit functions */
+
+#define KB_CAPS     LED_CAP /* 4 */
+#define KB_NUMLOCK  LED_NUM /* 2 */
+#define KB_SCROLL   LED_SCR /* 1 */
+#define KB_SHIFT    8
+#define KB_CONTROL  16
+#define KB_ALT      32
+
+/* Structure used to save the keyboard mode to disk. We save it to disk
+ * so that we can properly restore the mode later if the program crashed.
+ */
+
+typedef struct {
+    struct termios  termios;
+    int             kb_mode;
+    int             leds;
+    int             flags;
+    int             startup_vc;
+    } keyboard_mode;
+
+/* Name of the file used to save keyboard mode information */
+
+#define KBMODE_DAT  "kbmode.dat"
+
+/****************************************************************************
+REMARKS:
+Open the keyboard mode file on disk.
+****************************************************************************/
+static FILE *open_kb_mode(
+    char *mode,
+    char *path)
+{
+    if (!PM_findBPD("graphics.bpd",path))
+	return NULL;
+    PM_backslash(path);
+    strcat(path,KBMODE_DAT);
+    return fopen(path,mode);
+}
+
+/****************************************************************************
+REMARKS:
+Restore the keyboard to normal mode
+****************************************************************************/
+void _PM_restore_kb_mode(void)
+{
+    FILE            *kbmode;
+    keyboard_mode   mode;
+    char            path[PM_MAX_PATH];
+
+    if (_PM_console_fd != -1 && (kbmode = open_kb_mode("rb",path)) != NULL) {
+	if (fread(&mode,1,sizeof(mode),kbmode) == sizeof(mode)) {
+	    if (mode.startup_vc > 0)
+		ioctl(_PM_console_fd, VT_ACTIVATE, mode.startup_vc);
+	    ioctl(_PM_console_fd, KDSKBMODE, mode.kb_mode);
+	    ioctl(_PM_console_fd, KDSETLED, mode.leds);
+	    tcsetattr(_PM_console_fd, TCSAFLUSH, &mode.termios);
+	    fcntl(_PM_console_fd,F_SETFL,mode.flags);
+	    }
+	fclose(kbmode);
+	unlink(path);
+	in_raw_mode = false;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _PM_abort(
+    int signo)
+{
+    char    buf[80];
+
+    sprintf(buf,"Terminating on signal %d",signo);
+    _PM_restore_kb_mode();
+    PM_fatalError(buf);
+}
+
+/****************************************************************************
+REMARKS:
+Put the keyboard into raw mode
+****************************************************************************/
+void _PM_keyboard_rawmode(void)
+{
+    struct termios conf;
+    FILE            *kbmode;
+    keyboard_mode   mode;
+    char            path[PM_MAX_PATH];
+    int             i;
+    static int sig_list[] = {
+	SIGHUP,
+	SIGINT,
+	SIGQUIT,
+	SIGILL,
+	SIGTRAP,
+	SIGABRT,
+	SIGIOT,
+	SIGBUS,
+	SIGFPE,
+	SIGKILL,
+	SIGSEGV,
+	SIGTERM,
+	};
+
+    if ((kbmode = open_kb_mode("rb",path)) == NULL) {
+	if ((kbmode = open_kb_mode("wb",path)) == NULL)
+	    PM_fatalError("Unable to open kbmode.dat file for writing!");
+	if (ioctl(_PM_console_fd, KDGKBMODE, &mode.kb_mode))
+	    perror("KDGKBMODE");
+	ioctl(_PM_console_fd, KDGETLED, &mode.leds);
+	_PM_leds = mode.leds & 0xF;
+	_PM_modifiers = 0;
+	tcgetattr(_PM_console_fd, &mode.termios);
+	conf = mode.termios;
+	conf.c_lflag &= ~(ICANON | ECHO | ISIG);
+	conf.c_iflag &= ~(ISTRIP | IGNCR | ICRNL | INLCR | BRKINT | PARMRK | INPCK | IUCLC | IXON | IXOFF);
+	conf.c_iflag  |= (IGNBRK | IGNPAR);
+	conf.c_cc[VMIN] = 1;
+	conf.c_cc[VTIME] = 0;
+	conf.c_cc[VSUSP] = 0;
+	tcsetattr(_PM_console_fd, TCSAFLUSH, &conf);
+	mode.flags = fcntl(_PM_console_fd,F_GETFL);
+	if (ioctl(_PM_console_fd, KDSKBMODE, K_MEDIUMRAW))
+	    perror("KDSKBMODE");
+	atexit(_PM_restore_kb_mode);
+	for (i = 0; i < sizeof(sig_list)/sizeof(sig_list[0]); i++)
+	    signal(sig_list[i], _PM_abort);
+	mode.startup_vc = startup_vc;
+	if (fwrite(&mode,1,sizeof(mode),kbmode) != sizeof(mode))
+	    PM_fatalError("Error writing kbmode.dat!");
+	fclose(kbmode);
+	in_raw_mode = true;
+	}
+}
+
+int PMAPI PM_kbhit(void)
+{
+    fd_set s;
+    struct timeval tv = { 0, 0 };
+
+    if (console_count == 0)
+	PM_fatalError("You *must* open a console before using PM_kbhit!");
+    if (!in_raw_mode)
+	_PM_keyboard_rawmode();
+    FD_ZERO(&s);
+    FD_SET(_PM_console_fd, &s);
+    return select(_PM_console_fd+1, &s, NULL, NULL, &tv) > 0;
+}
+
+int PMAPI PM_getch(void)
+{
+    static uchar    c;
+    int release;
+    static struct kbentry ke;
+
+    if (console_count == 0)
+	PM_fatalError("You *must* open a console before using PM_getch!");
+    if (!in_raw_mode)
+	_PM_keyboard_rawmode();
+    while (read(_PM_console_fd, &c, 1) > 0) {
+	release = c & 0x80;
+	c &= 0x7F;
+	if (release) {
+	    switch(c){
+		case 42: case 54: /* Shift */
+		    _PM_modifiers &= ~KB_SHIFT;
+		    break;
+		case 29: case 97: /* Control */
+		    _PM_modifiers &= ~KB_CONTROL;
+		    break;
+		case 56: case 100: /* Alt / AltGr */
+		    _PM_modifiers &= ~KB_ALT;
+		    break;
+		}
+	    continue;
+	    }
+	switch (c) {
+	    case 42: case 54: /* Shift */
+		_PM_modifiers |= KB_SHIFT;
+		 break;
+	    case 29: case 97: /* Control */
+		_PM_modifiers |= KB_CONTROL;
+		break;
+	    case 56: case 100: /* Alt / AltGr */
+		_PM_modifiers |= KB_ALT;
+		break;
+	    case 58: /* Caps Lock */
+		_PM_modifiers ^= KB_CAPS;
+		ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7);
+		break;
+	    case 69: /* Num Lock */
+		_PM_modifiers ^= KB_NUMLOCK;
+		ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7);
+		break;
+	    case 70: /* Scroll Lock */
+		_PM_modifiers ^= KB_SCROLL;
+		ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7);
+		break;
+	    case 28:
+		return 0x1C;
+	    default:
+		ke.kb_index = c;
+		ke.kb_table = 0;
+		if ((_PM_modifiers & KB_SHIFT) || (_PM_modifiers & KB_CAPS))
+		    ke.kb_table |= K_SHIFTTAB;
+		if (_PM_modifiers & KB_ALT)
+		    ke.kb_table |= K_ALTTAB;
+		ioctl(_PM_console_fd, KDGKBENT, (ulong)&ke);
+		c = ke.kb_value & 0xFF;
+		return c;
+	    }
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Sleep until the virtual terminal is active
+****************************************************************************/
+static void wait_vt_active(
+    int _PM_console_fd)
+{
+    while (ioctl(_PM_console_fd, VT_WAITACTIVE, tty_vc) < 0) {
+	if ((errno != EAGAIN) && (errno != EINTR)) {
+	    perror("ioctl(VT_WAITACTIVE)");
+	    exit(1);
+	    }
+	usleep(150000);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Checks the owner of the specified virtual console.
+****************************************************************************/
+static int check_owner(
+    int vc)
+{
+    struct stat sbuf;
+    char fname[30];
+
+    sprintf(fname, "/dev/tty%d", vc);
+    if ((stat(fname, &sbuf) >= 0) && (getuid() == sbuf.st_uid))
+	return 1;
+    printf("You must be the owner of the current console to use this program.\n");
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Checks if the console is currently in graphics mode, and if so we forcibly
+restore it back to text mode again. This handles the case when a Nucleus or
+MGL program crashes and leaves the console in graphics mode. Running the
+textmode utility (or any other Nucleus/MGL program) via a telnet session
+into the machine will restore it back to normal.
+****************************************************************************/
+static void restore_text_console(
+    int console_id)
+{
+    if (ioctl(console_id, KDSETMODE, KD_TEXT) < 0)
+	LOGWARN("ioctl(KDSETMODE) failed");
+    _PM_restore_kb_mode();
+}
+
+/****************************************************************************
+REMARKS:
+Opens up the console device for output by finding an appropriate virutal
+console that we can run on.
+****************************************************************************/
+PM_HWND PMAPI PM_openConsole(
+    PM_HWND hwndUser,
+    int device,
+    int xRes,
+    int yRes,
+    int bpp,
+    ibool fullScreen)
+{
+    struct vt_mode  vtm;
+    struct vt_stat  vts;
+    struct stat     sbuf;
+    char            fname[30];
+
+    /* Check if we have already opened the console */
+    if (console_count++)
+	return _PM_console_fd;
+
+    /* Now, it would be great if we could use /dev/tty and see what it is
+     * connected to. Alas, we cannot find out reliably what VC /dev/tty is
+     * bound to. Thus we parse stdin through stderr for a reliable VC.
+     */
+    startup_vc = 0;
+    for (_PM_console_fd = 0; _PM_console_fd < 3; _PM_console_fd++) {
+	if (fstat(_PM_console_fd, &sbuf) < 0)
+	    continue;
+	if (ioctl(_PM_console_fd, VT_GETMODE, &vtm) < 0)
+	    continue;
+	if ((sbuf.st_rdev & 0xFF00) != 0x400)
+	    continue;
+	if (!(sbuf.st_rdev & 0xFF))
+	    continue;
+	tty_vc = sbuf.st_rdev & 0xFF;
+	restore_text_console(_PM_console_fd);
+	return _PM_console_fd;
+	}
+    if ((_PM_console_fd = open("/dev/console", O_RDWR)) < 0) {
+	printf("open_dev_console: can't open /dev/console \n");
+	exit(1);
+	}
+    if (ioctl(_PM_console_fd, VT_OPENQRY, &tty_vc) < 0)
+	goto Error;
+    if (tty_vc <= 0)
+	goto Error;
+    sprintf(fname, "/dev/tty%d", tty_vc);
+    close(_PM_console_fd);
+
+    /* Change our control terminal */
+    setsid();
+
+    /* We must use RDWR to allow for output... */
+    if (((_PM_console_fd = open(fname, O_RDWR)) >= 0) &&
+	    (ioctl(_PM_console_fd, VT_GETSTATE, &vts) >= 0)) {
+	if (!check_owner(vts.v_active))
+	    goto Error;
+	restore_text_console(_PM_console_fd);
+
+	/* Success, redirect all stdios */
+	fflush(stdin);
+	fflush(stdout);
+	fflush(stderr);
+	close(0);
+	close(1);
+	close(2);
+	dup(_PM_console_fd);
+	dup(_PM_console_fd);
+	dup(_PM_console_fd);
+
+	/* clear screen and switch to it */
+	fwrite("\e[H\e[J", 6, 1, stderr);
+	fflush(stderr);
+	if (tty_vc != vts.v_active) {
+	    startup_vc = vts.v_active;
+	    ioctl(_PM_console_fd, VT_ACTIVATE, tty_vc);
+	    wait_vt_active(_PM_console_fd);
+	    }
+	}
+    return _PM_console_fd;
+
+Error:
+    if (_PM_console_fd > 2)
+	close(_PM_console_fd);
+    console_count = 0;
+    PM_fatalError(
+	"Not running in a graphics capable console,\n"
+	"and unable to find one.\n");
+    return -1;
+}
+
+#define FONT_C  0x10000     /* 64KB for font data                       */
+
+/****************************************************************************
+REMARKS:
+Returns the size of the console state buffer.
+****************************************************************************/
+int PMAPI PM_getConsoleStateSize(void)
+{
+    if (!inited)
+	PM_init();
+    return PM_getVGAStateSize() + FONT_C*2;
+}
+
+/****************************************************************************
+REMARKS:
+Save the state of the Linux console.
+****************************************************************************/
+void PMAPI PM_saveConsoleState(void *stateBuf,int console_id)
+{
+    uchar   *regs = stateBuf;
+
+    /* Save the current console font */
+    if (ioctl(console_id,GIO_FONT,&regs[PM_getVGAStateSize()]) < 0)
+	perror("ioctl(GIO_FONT)");
+
+    /* Inform the Linux console that we are going into graphics mode */
+    if (ioctl(console_id, KDSETMODE, KD_GRAPHICS) < 0)
+	perror("ioctl(KDSETMODE)");
+
+    /* Save state of VGA registers */
+    PM_saveVGAState(stateBuf);
+}
+
+void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags))
+{
+    /* TODO: Implement support for allowing console switching! */
+}
+
+/****************************************************************************
+REMARKS:
+Restore the state of the Linux console.
+****************************************************************************/
+void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND console_id)
+{
+    const uchar *regs = stateBuf;
+
+    /* Restore the state of the VGA compatible registers */
+    PM_restoreVGAState(stateBuf);
+
+    /* Inform the Linux console that we are back from graphics modes */
+    if (ioctl(console_id, KDSETMODE, KD_TEXT) < 0)
+	LOGWARN("ioctl(KDSETMODE) failed");
+
+    /* Restore the old console font */
+    if (ioctl(console_id,PIO_FONT,&regs[PM_getVGAStateSize()]) < 0)
+	LOGWARN("ioctl(KDSETMODE) failed");
+
+    /* Coming back from graphics mode on Linux also restored the previous
+     * text mode console contents, so we need to clear the screen to get
+     * around this since the cursor does not get homed by our code.
+     */
+    fflush(stdout);
+    fflush(stderr);
+    printf("\033[H\033[J");
+    fflush(stdout);
+}
+
+/****************************************************************************
+REMARKS:
+Close the Linux console and put it back to normal.
+****************************************************************************/
+void PMAPI PM_closeConsole(PM_HWND _PM_console_fd)
+{
+    /* Restore console to normal operation */
+    if (--console_count == 0) {
+	/* Re-activate the original virtual console */
+	if (startup_vc > 0)
+	    ioctl(_PM_console_fd, VT_ACTIVATE, startup_vc);
+
+	/* Close the console file descriptor */
+	if (_PM_console_fd > 2)
+	    close(_PM_console_fd);
+	_PM_console_fd = -1;
+	}
+}
+
+void PM_setOSCursorLocation(int x,int y)
+{
+    /* Nothing to do in here */
+}
+
+/****************************************************************************
+REMARKS:
+Set the screen width and height for the Linux console.
+****************************************************************************/
+void PM_setOSScreenWidth(int width,int height)
+{
+    struct winsize  ws;
+    struct vt_sizes vs;
+
+    /* Resize the software terminal */
+    ws.ws_col = width;
+    ws.ws_row = height;
+    ioctl(_PM_console_fd, TIOCSWINSZ, &ws);
+
+    /* And the hardware */
+    vs.v_rows = height;
+    vs.v_cols = width;
+    vs.v_scrollsize = 0;
+    ioctl(_PM_console_fd, VT_RESIZE, &vs);
+}
+
+ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency)
+{
+    /* TODO: Implement this for Linux */
+    return false;
+}
+
+void PMAPI PM_setRealTimeClockFrequency(int frequency)
+{
+    /* TODO: Implement this for Linux */
+}
+
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    /* TODO: Implement this for Linux */
+}
+
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    return getcwd(path,maxLen);
+}
+
+char PMAPI PM_getBootDrive(void)
+{ return '/'; }
+
+const char * PMAPI PM_getVBEAFPath(void)
+{ return PM_getNucleusConfigPath(); }
+
+const char * PMAPI PM_getNucleusPath(void)
+{
+    char *env = getenv("NUCLEUS_PATH");
+    return env ? env : "/usr/lib/nucleus";
+}
+
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+const char * PMAPI PM_getUniqueID(void)
+{
+    static char buf[128];
+    gethostname(buf, 128);
+    return buf;
+}
+
+const char * PMAPI PM_getMachineName(void)
+{
+    static char buf[128];
+    gethostname(buf, 128);
+    return buf;
+}
+
+void * PMAPI PM_getBIOSPointer(void)
+{
+    static uchar *zeroPtr = NULL;
+    if (!zeroPtr)
+	zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true);
+    return (void*)(zeroPtr + 0x400);
+}
+
+void * PMAPI PM_getA0000Pointer(void)
+{
+    /* PM_init maps in the 0xA0000 framebuffer region 1:1 with our
+     * address mapping, so we can return the address here.
+     */
+    if (!inited)
+	PM_init();
+    return (void*)(0xA0000);
+}
+
+void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{
+    uchar   *p;
+    ulong   baseAddr,baseOfs;
+
+    if (!inited)
+	PM_init();
+    if (base >= 0xA0000 && base < 0x100000)
+	return (void*)base;
+    if (!fd_mem && (fd_mem = open("/dev/mem", O_RDWR)) == -1)
+	return NULL;
+
+    /* Round the physical address to a 4Kb boundary and the limit to a
+     * 4Kb-1 boundary before passing the values to mmap. If we round the
+     * physical address, then we also add an extra offset into the address
+     * that we return.
+     */
+    baseOfs = base & 4095;
+    baseAddr = base & ~4095;
+    limit = ((limit+baseOfs+1+4095) & ~4095)-1;
+    if ((p = mmap(0, limit+1,
+	    PROT_READ | PROT_WRITE, MAP_SHARED,
+	    fd_mem, baseAddr)) == (void *)-1)
+	return NULL;
+    return (void*)(p+baseOfs);
+}
+
+void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit)
+{
+    if ((ulong)ptr >= 0x100000)
+	munmap(ptr,limit+1);
+}
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{
+    /* TODO: This function should find the physical address of a linear */
+    /*       address. */
+    return 0xFFFFFFFFUL;
+}
+
+ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress)
+{
+    /* TODO: This function should find a range of physical addresses */
+    /*       for a linear address. */
+    return false;
+}
+
+void PMAPI PM_sleep(ulong milliseconds)
+{
+    /* TODO: Put the process to sleep for milliseconds */
+}
+
+int PMAPI PM_getCOMPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	}
+    return 0;
+}
+
+int PMAPI PM_getLPTPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+void * PMAPI PM_mallocShared(long size)
+{
+    return PM_malloc(size);
+}
+
+void PMAPI PM_freeShared(void *ptr)
+{
+    PM_free(ptr);
+}
+
+void * PMAPI PM_mapToProcess(void *base,ulong limit)
+{ return (void*)base; }
+
+void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off)
+{
+    /* PM_init maps in the 0xA0000-0x100000 region 1:1 with our
+     * address mapping, as well as all memory blocks in a 1:1 address
+     * mapping so we can simply return the physical address in here.
+     */
+    if (!inited)
+	PM_init();
+    return (void*)MK_PHYS(r_seg,r_off);
+}
+
+void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off)
+{
+    int     i;
+    char    *r = (char *)REAL_MEM_BASE;
+
+    if (!inited)
+	PM_init();
+    if (!mem_info.ready)
+	return NULL;
+    if (mem_info.count == REAL_MEM_BLOCKS)
+	return NULL;
+    size = (size + 15) & ~15;
+    for (i = 0; i < mem_info.count; i++) {
+	if (mem_info.blocks[i].free && size < mem_info.blocks[i].size) {
+	    insert_block(i);
+	    mem_info.blocks[i].size = size;
+	    mem_info.blocks[i].free = 0;
+	    mem_info.blocks[i + 1].size -= size;
+	    *r_seg = (uint)(r) >> 4;
+	    *r_off = (uint)(r) & 0xF;
+	    return (void *)r;
+	    }
+	r += mem_info.blocks[i].size;
+	}
+    return NULL;
+}
+
+void PMAPI PM_freeRealSeg(void *mem)
+{
+    int     i;
+    char    *r = (char *)REAL_MEM_BASE;
+
+    if (!mem_info.ready)
+	return;
+    i = 0;
+    while (mem != (void *)r) {
+	r += mem_info.blocks[i].size;
+	i++;
+	if (i == mem_info.count)
+	    return;
+	}
+    mem_info.blocks[i].free = 1;
+    if (i + 1 < mem_info.count && mem_info.blocks[i + 1].free) {
+	mem_info.blocks[i].size += mem_info.blocks[i + 1].size;
+	delete_block(i + 1);
+	}
+    if (i - 1 >= 0 && mem_info.blocks[i - 1].free) {
+	mem_info.blocks[i - 1].size += mem_info.blocks[i].size;
+	delete_block(i);
+	}
+}
+
+#define DIRECTION_FLAG  (1 << 10)
+
+static void em_ins(int size)
+{
+    unsigned int edx, edi;
+
+    edx = context.vm.regs.edx & 0xffff;
+    edi = context.vm.regs.edi & 0xffff;
+    edi += (unsigned int)context.vm.regs.ds << 4;
+    if (context.vm.regs.eflags & DIRECTION_FLAG) {
+	if (size == 4)
+	    asm volatile ("std; insl; cld"
+	     : "=D" (edi) : "d" (edx), "0" (edi));
+	else if (size == 2)
+	    asm volatile ("std; insw; cld"
+	     : "=D" (edi) : "d" (edx), "0" (edi));
+	else
+	    asm volatile ("std; insb; cld"
+	     : "=D" (edi) : "d" (edx), "0" (edi));
+	}
+    else {
+	if (size == 4)
+	    asm volatile ("cld; insl"
+	     : "=D" (edi) : "d" (edx), "0" (edi));
+	else if (size == 2)
+	    asm volatile ("cld; insw"
+	     : "=D" (edi) : "d" (edx), "0" (edi));
+	else
+	    asm volatile ("cld; insb"
+	     : "=D" (edi) : "d" (edx), "0" (edi));
+	}
+    edi -= (unsigned int)context.vm.regs.ds << 4;
+    context.vm.regs.edi &= 0xffff0000;
+    context.vm.regs.edi |= edi & 0xffff;
+}
+
+static void em_rep_ins(int size)
+{
+    unsigned int ecx, edx, edi;
+
+    ecx = context.vm.regs.ecx & 0xffff;
+    edx = context.vm.regs.edx & 0xffff;
+    edi = context.vm.regs.edi & 0xffff;
+    edi += (unsigned int)context.vm.regs.ds << 4;
+    if (context.vm.regs.eflags & DIRECTION_FLAG) {
+	if (size == 4)
+	    asm volatile ("std; rep; insl; cld"
+	     : "=D" (edi), "=c" (ecx)
+	     : "d" (edx), "0" (edi), "1" (ecx));
+	else if (size == 2)
+	    asm volatile ("std; rep; insw; cld"
+	     : "=D" (edi), "=c" (ecx)
+	     : "d" (edx), "0" (edi), "1" (ecx));
+	else
+	    asm volatile ("std; rep; insb; cld"
+	     : "=D" (edi), "=c" (ecx)
+	     : "d" (edx), "0" (edi), "1" (ecx));
+	}
+    else {
+	if (size == 4)
+	    asm volatile ("cld; rep; insl"
+	     : "=D" (edi), "=c" (ecx)
+	     : "d" (edx), "0" (edi), "1" (ecx));
+	else if (size == 2)
+	    asm volatile ("cld; rep; insw"
+	     : "=D" (edi), "=c" (ecx)
+	     : "d" (edx), "0" (edi), "1" (ecx));
+	else
+	    asm volatile ("cld; rep; insb"
+	     : "=D" (edi), "=c" (ecx)
+	     : "d" (edx), "0" (edi), "1" (ecx));
+	}
+
+    edi -= (unsigned int)context.vm.regs.ds << 4;
+    context.vm.regs.edi &= 0xffff0000;
+    context.vm.regs.edi |= edi & 0xffff;
+    context.vm.regs.ecx &= 0xffff0000;
+    context.vm.regs.ecx |= ecx & 0xffff;
+}
+
+static void em_outs(int size)
+{
+    unsigned int edx, esi;
+
+    edx = context.vm.regs.edx & 0xffff;
+    esi = context.vm.regs.esi & 0xffff;
+    esi += (unsigned int)context.vm.regs.ds << 4;
+    if (context.vm.regs.eflags & DIRECTION_FLAG) {
+	if (size == 4)
+	    asm volatile ("std; outsl; cld"
+	     : "=S" (esi) : "d" (edx), "0" (esi));
+	else if (size == 2)
+	    asm volatile ("std; outsw; cld"
+	     : "=S" (esi) : "d" (edx), "0" (esi));
+	else
+	    asm volatile ("std; outsb; cld"
+	     : "=S" (esi) : "d" (edx), "0" (esi));
+	}
+    else {
+	if (size == 4)
+	    asm volatile ("cld; outsl"
+	     : "=S" (esi) : "d" (edx), "0" (esi));
+	else if (size == 2)
+	    asm volatile ("cld; outsw"
+	     : "=S" (esi) : "d" (edx), "0" (esi));
+	else
+	    asm volatile ("cld; outsb"
+	     : "=S" (esi) : "d" (edx), "0" (esi));
+	}
+
+    esi -= (unsigned int)context.vm.regs.ds << 4;
+    context.vm.regs.esi &= 0xffff0000;
+    context.vm.regs.esi |= esi & 0xffff;
+}
+
+static void em_rep_outs(int size)
+{
+    unsigned int ecx, edx, esi;
+
+    ecx = context.vm.regs.ecx & 0xffff;
+    edx = context.vm.regs.edx & 0xffff;
+    esi = context.vm.regs.esi & 0xffff;
+    esi += (unsigned int)context.vm.regs.ds << 4;
+    if (context.vm.regs.eflags & DIRECTION_FLAG) {
+	if (size == 4)
+	    asm volatile ("std; rep; outsl; cld"
+	     : "=S" (esi), "=c" (ecx)
+	     : "d" (edx), "0" (esi), "1" (ecx));
+	else if (size == 2)
+	    asm volatile ("std; rep; outsw; cld"
+	     : "=S" (esi), "=c" (ecx)
+	     : "d" (edx), "0" (esi), "1" (ecx));
+	else
+	    asm volatile ("std; rep; outsb; cld"
+	     : "=S" (esi), "=c" (ecx)
+	     : "d" (edx), "0" (esi), "1" (ecx));
+	}
+    else {
+	if (size == 4)
+	    asm volatile ("cld; rep; outsl"
+	     : "=S" (esi), "=c" (ecx)
+	     : "d" (edx), "0" (esi), "1" (ecx));
+	else if (size == 2)
+	    asm volatile ("cld; rep; outsw"
+	     : "=S" (esi), "=c" (ecx)
+	     : "d" (edx), "0" (esi), "1" (ecx));
+	else
+	    asm volatile ("cld; rep; outsb"
+	     : "=S" (esi), "=c" (ecx)
+	     : "d" (edx), "0" (esi), "1" (ecx));
+	}
+
+    esi -= (unsigned int)context.vm.regs.ds << 4;
+    context.vm.regs.esi &= 0xffff0000;
+    context.vm.regs.esi |= esi & 0xffff;
+    context.vm.regs.ecx &= 0xffff0000;
+    context.vm.regs.ecx |= ecx & 0xffff;
+}
+
+static int emulate(void)
+{
+    unsigned char *insn;
+    struct {
+	unsigned int size : 1;
+	unsigned int rep : 1;
+	} prefix = { 0, 0 };
+    int i = 0;
+
+    insn = (unsigned char *)((unsigned int)context.vm.regs.cs << 4);
+    insn += context.vm.regs.eip;
+
+    while (1) {
+#ifdef TRACE_IO
+	traceAddr = ((ulong)context.vm.regs.cs << 16) + context.vm.regs.eip + i;
+#endif
+	if (insn[i] == 0x66) {
+	    prefix.size = 1 - prefix.size;
+	    i++;
+	    }
+	else if (insn[i] == 0xf3) {
+	    prefix.rep = 1;
+	    i++;
+	    }
+	else if (insn[i] == 0xf0 || insn[i] == 0xf2
+	     || insn[i] == 0x26 || insn[i] == 0x2e
+	     || insn[i] == 0x36 || insn[i] == 0x3e
+	     || insn[i] == 0x64 || insn[i] == 0x65
+	     || insn[i] == 0x67) {
+	    /* these prefixes are just ignored */
+	    i++;
+	    }
+	else if (insn[i] == 0x6c) {
+	    if (prefix.rep)
+		em_rep_ins(1);
+	    else
+		em_ins(1);
+	    i++;
+	    break;
+	    }
+	else if (insn[i] == 0x6d) {
+	    if (prefix.rep) {
+		if (prefix.size)
+		    em_rep_ins(4);
+		else
+		    em_rep_ins(2);
+		}
+	    else {
+		if (prefix.size)
+		    em_ins(4);
+		else
+		    em_ins(2);
+		}
+	    i++;
+	    break;
+	    }
+	else if (insn[i] == 0x6e) {
+	    if (prefix.rep)
+		em_rep_outs(1);
+	    else
+		em_outs(1);
+	    i++;
+	    break;
+	    }
+	else if (insn[i] == 0x6f) {
+	    if (prefix.rep) {
+		if (prefix.size)
+		    em_rep_outs(4);
+		else
+		    em_rep_outs(2);
+		}
+	    else {
+		if (prefix.size)
+		    em_outs(4);
+		else
+		    em_outs(2);
+		}
+	    i++;
+	    break;
+	    }
+	else if (insn[i] == 0xec) {
+	    *((uchar*)&context.vm.regs.eax) = port_in(context.vm.regs.edx);
+	    i++;
+	    break;
+	    }
+	else if (insn[i] == 0xed) {
+	    if (prefix.size)
+		*((ulong*)&context.vm.regs.eax) = port_inl(context.vm.regs.edx);
+	    else
+		*((ushort*)&context.vm.regs.eax) = port_inw(context.vm.regs.edx);
+	    i++;
+	    break;
+	    }
+	else if (insn[i] == 0xee) {
+	    port_out(context.vm.regs.eax,context.vm.regs.edx);
+	    i++;
+	    break;
+	    }
+	else if (insn[i] == 0xef) {
+	    if (prefix.size)
+		port_outl(context.vm.regs.eax,context.vm.regs.edx);
+	    else
+		port_outw(context.vm.regs.eax,context.vm.regs.edx);
+	    i++;
+	    break;
+	    }
+	else
+	    return 0;
+	}
+
+    context.vm.regs.eip += i;
+    return 1;
+}
+
+static void debug_info(int vret)
+{
+    int i;
+    unsigned char *p;
+
+    fputs("vm86() failed\n", stderr);
+    fprintf(stderr, "return = 0x%x\n", vret);
+    fprintf(stderr, "eax = 0x%08lx\n", context.vm.regs.eax);
+    fprintf(stderr, "ebx = 0x%08lx\n", context.vm.regs.ebx);
+    fprintf(stderr, "ecx = 0x%08lx\n", context.vm.regs.ecx);
+    fprintf(stderr, "edx = 0x%08lx\n", context.vm.regs.edx);
+    fprintf(stderr, "esi = 0x%08lx\n", context.vm.regs.esi);
+    fprintf(stderr, "edi = 0x%08lx\n", context.vm.regs.edi);
+    fprintf(stderr, "ebp = 0x%08lx\n", context.vm.regs.ebp);
+    fprintf(stderr, "eip = 0x%08lx\n", context.vm.regs.eip);
+    fprintf(stderr, "cs  = 0x%04x\n", context.vm.regs.cs);
+    fprintf(stderr, "esp = 0x%08lx\n", context.vm.regs.esp);
+    fprintf(stderr, "ss  = 0x%04x\n", context.vm.regs.ss);
+    fprintf(stderr, "ds  = 0x%04x\n", context.vm.regs.ds);
+    fprintf(stderr, "es  = 0x%04x\n", context.vm.regs.es);
+    fprintf(stderr, "fs  = 0x%04x\n", context.vm.regs.fs);
+    fprintf(stderr, "gs  = 0x%04x\n", context.vm.regs.gs);
+    fprintf(stderr, "eflags  = 0x%08lx\n", context.vm.regs.eflags);
+    fputs("cs:ip = [ ", stderr);
+    p = (unsigned char *)((context.vm.regs.cs << 4) + (context.vm.regs.eip & 0xffff));
+    for (i = 0; i < 16; ++i)
+	    fprintf(stderr, "%02x ", (unsigned int)p[i]);
+    fputs("]\n", stderr);
+    fflush(stderr);
+}
+
+static int run_vm86(void)
+{
+    unsigned int vret;
+
+    for (;;) {
+	vret = vm86(&context.vm);
+	if (VM86_TYPE(vret) == VM86_INTx) {
+	    unsigned int v = VM86_ARG(vret);
+	    if (v == RETURN_TO_32_INT)
+		return 1;
+	    pushw(context.vm.regs.eflags);
+	    pushw(context.vm.regs.cs);
+	    pushw(context.vm.regs.eip);
+	    context.vm.regs.cs = get_int_seg(v);
+	    context.vm.regs.eip = get_int_off(v);
+	    context.vm.regs.eflags &= ~(VIF_MASK | TF_MASK);
+	    continue;
+	    }
+	if (VM86_TYPE(vret) != VM86_UNKNOWN)
+	    break;
+	if (!emulate())
+	    break;
+	}
+    debug_info(vret);
+    return 0;
+}
+
+#define IND(ereg) context.vm.regs.ereg = regs->ereg
+#define OUTD(ereg) regs->ereg = context.vm.regs.ereg
+
+void PMAPI DPMI_int86(int intno, DPMI_regs *regs)
+{
+    if (!inited)
+	PM_init();
+    memset(&context.vm.regs, 0, sizeof(context.vm.regs));
+    IND(eax); IND(ebx); IND(ecx); IND(edx); IND(esi); IND(edi);
+    context.vm.regs.eflags = DEFAULT_VM86_FLAGS;
+    context.vm.regs.cs = get_int_seg(intno);
+    context.vm.regs.eip = get_int_off(intno);
+    context.vm.regs.ss = context.stack_seg;
+    context.vm.regs.esp = context.stack_off;
+    pushw(DEFAULT_VM86_FLAGS);
+    pushw(context.ret_seg);
+    pushw(context.ret_off);
+    run_vm86();
+    OUTD(eax); OUTD(ebx); OUTD(ecx); OUTD(edx); OUTD(esi); OUTD(edi);
+    regs->flags = context.vm.regs.eflags;
+}
+
+#define IN(ereg) context.vm.regs.ereg = in->e.ereg
+#define OUT(ereg) out->e.ereg = context.vm.regs.ereg
+
+int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out)
+{
+    if (!inited)
+	PM_init();
+    memset(&context.vm.regs, 0, sizeof(context.vm.regs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+    context.vm.regs.eflags = DEFAULT_VM86_FLAGS;
+    context.vm.regs.cs = get_int_seg(intno);
+    context.vm.regs.eip = get_int_off(intno);
+    context.vm.regs.ss = context.stack_seg;
+    context.vm.regs.esp = context.stack_off;
+    pushw(DEFAULT_VM86_FLAGS);
+    pushw(context.ret_seg);
+    pushw(context.ret_off);
+    run_vm86();
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+    out->x.cflag = context.vm.regs.eflags & 1;
+    return out->x.ax;
+}
+
+int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,
+    RMSREGS *sregs)
+{
+    if (!inited)
+	PM_init();
+    if (intno == 0x21) {
+	time_t today = time(NULL);
+	struct tm *t;
+	t = localtime(&today);
+	out->x.cx = t->tm_year + 1900;
+	out->h.dh = t->tm_mon + 1;
+	out->h.dl = t->tm_mday;
+	}
+    else {
+	unsigned int seg, off;
+	seg = get_int_seg(intno);
+	off = get_int_off(intno);
+	memset(&context.vm.regs, 0, sizeof(context.vm.regs));
+	IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+	context.vm.regs.eflags = DEFAULT_VM86_FLAGS;
+	context.vm.regs.cs = seg;
+	context.vm.regs.eip = off;
+	context.vm.regs.es = sregs->es;
+	context.vm.regs.ds = sregs->ds;
+	context.vm.regs.fs = sregs->fs;
+	context.vm.regs.gs = sregs->gs;
+	context.vm.regs.ss = context.stack_seg;
+	context.vm.regs.esp = context.stack_off;
+	pushw(DEFAULT_VM86_FLAGS);
+	pushw(context.ret_seg);
+	pushw(context.ret_off);
+	run_vm86();
+	OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+	sregs->es = context.vm.regs.es;
+	sregs->ds = context.vm.regs.ds;
+	sregs->fs = context.vm.regs.fs;
+	sregs->gs = context.vm.regs.gs;
+	out->x.cflag = context.vm.regs.eflags & 1;
+	}
+    return out->e.eax;
+}
+
+#define OUTR(ereg) in->e.ereg = context.vm.regs.ereg
+
+void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in,
+    RMSREGS *sregs)
+{
+    if (!inited)
+	PM_init();
+    memset(&context.vm.regs, 0, sizeof(context.vm.regs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+    context.vm.regs.eflags = DEFAULT_VM86_FLAGS;
+    context.vm.regs.cs = seg;
+    context.vm.regs.eip = off;
+    context.vm.regs.ss = context.stack_seg;
+    context.vm.regs.esp = context.stack_off;
+    context.vm.regs.es = sregs->es;
+    context.vm.regs.ds = sregs->ds;
+    context.vm.regs.fs = sregs->fs;
+    context.vm.regs.gs = sregs->gs;
+    pushw(DEFAULT_VM86_FLAGS);
+    pushw(context.ret_seg);
+    pushw(context.ret_off);
+    run_vm86();
+    OUTR(eax); OUTR(ebx); OUTR(ecx); OUTR(edx); OUTR(esi); OUTR(edi);
+    sregs->es = context.vm.regs.es;
+    sregs->ds = context.vm.regs.ds;
+    sregs->fs = context.vm.regs.fs;
+    sregs->gs = context.vm.regs.gs;
+    in->x.cflag = context.vm.regs.eflags & 1;
+}
+
+void PMAPI PM_availableMemory(ulong *physical,ulong *total)
+{
+    FILE    *mem = fopen("/proc/meminfo","r");
+    char    buf[1024];
+
+    fgets(buf,1024,mem);
+    fgets(buf,1024,mem);
+    sscanf(buf,"Mem: %*d %*d %ld", physical);
+    fgets(buf,1024,mem);
+    sscanf(buf,"Swap: %*d %*d %ld", total);
+    fclose(mem);
+    *total += *physical;
+}
+
+void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16M)
+{
+    /* TODO: Implement this for Linux */
+    return NULL;
+}
+
+void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous)
+{
+    /* TODO: Implement this for Linux */
+}
+
+void * PMAPI PM_allocPage(
+    ibool locked)
+{
+    /* TODO: Implement this for Linux */
+    return NULL;
+}
+
+void PMAPI PM_freePage(
+    void *p)
+{
+    /* TODO: Implement this for Linux */
+}
+
+void PMAPI PM_setBankA(int bank)
+{
+    if (!inited)
+	PM_init();
+    memset(&context.vm.regs, 0, sizeof(context.vm.regs));
+    context.vm.regs.eax = 0x4F05;
+    context.vm.regs.ebx = 0x0000;
+    context.vm.regs.edx = bank;
+    context.vm.regs.eflags = DEFAULT_VM86_FLAGS;
+    context.vm.regs.cs = get_int_seg(0x10);
+    context.vm.regs.eip = get_int_off(0x10);
+    context.vm.regs.ss = context.stack_seg;
+    context.vm.regs.esp = context.stack_off;
+    pushw(DEFAULT_VM86_FLAGS);
+    pushw(context.ret_seg);
+    pushw(context.ret_off);
+    run_vm86();
+}
+
+void PMAPI PM_setBankAB(int bank)
+{
+    if (!inited)
+	PM_init();
+    memset(&context.vm.regs, 0, sizeof(context.vm.regs));
+    context.vm.regs.eax = 0x4F05;
+    context.vm.regs.ebx = 0x0000;
+    context.vm.regs.edx = bank;
+    context.vm.regs.eflags = DEFAULT_VM86_FLAGS;
+    context.vm.regs.cs = get_int_seg(0x10);
+    context.vm.regs.eip = get_int_off(0x10);
+    context.vm.regs.ss = context.stack_seg;
+    context.vm.regs.esp = context.stack_off;
+    pushw(DEFAULT_VM86_FLAGS);
+    pushw(context.ret_seg);
+    pushw(context.ret_off);
+    run_vm86();
+    context.vm.regs.eax = 0x4F05;
+    context.vm.regs.ebx = 0x0001;
+    context.vm.regs.edx = bank;
+    context.vm.regs.eflags = DEFAULT_VM86_FLAGS;
+    context.vm.regs.cs = get_int_seg(0x10);
+    context.vm.regs.eip = get_int_off(0x10);
+    context.vm.regs.ss = context.stack_seg;
+    context.vm.regs.esp = context.stack_off;
+    pushw(DEFAULT_VM86_FLAGS);
+    pushw(context.ret_seg);
+    pushw(context.ret_off);
+    run_vm86();
+}
+
+void PMAPI PM_setCRTStart(int x,int y,int waitVRT)
+{
+    if (!inited)
+	PM_init();
+    memset(&context.vm.regs, 0, sizeof(context.vm.regs));
+    context.vm.regs.eax = 0x4F07;
+    context.vm.regs.ebx = waitVRT;
+    context.vm.regs.ecx = x;
+    context.vm.regs.edx = y;
+    context.vm.regs.eflags = DEFAULT_VM86_FLAGS;
+    context.vm.regs.cs = get_int_seg(0x10);
+    context.vm.regs.eip = get_int_off(0x10);
+    context.vm.regs.ss = context.stack_seg;
+    context.vm.regs.esp = context.stack_off;
+    pushw(DEFAULT_VM86_FLAGS);
+    pushw(context.ret_seg);
+    pushw(context.ret_off);
+    run_vm86();
+}
+
+int PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type)
+{
+#ifdef ENABLE_MTRR
+    struct mtrr_sentry sentry;
+
+    if (mtrr_fd < 0)
+	return PM_MTRR_ERR_NO_OS_SUPPORT;
+    sentry.base = base;
+    sentry.size = length;
+    sentry.type = type;
+    if (ioctl(mtrr_fd, MTRRIOC_ADD_ENTRY, &sentry) == -1) {
+	/* TODO: Need to decode MTRR error codes!! */
+	return PM_MTRR_NOT_SUPPORTED;
+	}
+    return PM_MTRR_ERR_OK;
+#else
+    return PM_MTRR_ERR_NO_OS_SUPPORT;
+#endif
+}
+
+/****************************************************************************
+PARAMETERS:
+callback    - Function to callback with write combine information
+
+REMARKS:
+Function to enumerate all write combine regions currently enabled for the
+processor.
+****************************************************************************/
+int PMAPI PM_enumWriteCombine(
+    PM_enumWriteCombine_t callback)
+{
+#ifdef ENABLE_MTRR
+    struct mtrr_gentry gentry;
+
+    if (mtrr_fd < 0)
+	return PM_MTRR_ERR_NO_OS_SUPPORT;
+
+    for (gentry.regnum = 0; ioctl (mtrr_fd, MTRRIOC_GET_ENTRY, &gentry) == 0;
+	 ++gentry.regnum) {
+	if (gentry.size > 0) {
+	    /* WARNING: This code assumes that the types in pmapi.h match the ones */
+	    /* in the Linux kernel (mtrr.h) */
+	    callback(gentry.base, gentry.size, gentry.type);
+	}
+    }
+
+    return PM_MTRR_ERR_OK;
+#else
+    return PM_MTRR_ERR_NO_OS_SUPPORT;
+#endif
+}
+
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *copyOfBIOS,
+    ulong BIOSLen)
+{
+    char        *bios_ptr = (char*)0xC0000;
+    char        *old_bios;
+    ulong       Current10, Current6D, *rvec = 0;
+    RMREGS      regs;
+    RMSREGS     sregs;
+
+    /* The BIOS is mapped to 0xC0000 with a private memory mapping enabled
+     * which means we have a copy on write scheme. Hence we simply copy
+     * the secondary BIOS image over the top of the old one.
+     */
+    if (!inited)
+	PM_init();
+    if ((old_bios = PM_malloc(BIOSLen)) == NULL)
+	return false;
+    if (BIOSPhysAddr != 0xC0000) {
+	memcpy(old_bios,bios_ptr,BIOSLen);
+	memcpy(bios_ptr,copyOfBIOS,BIOSLen);
+	}
+
+    /* The interrupt vectors should already be mmap()'ed from 0-0x400 in PM_init */
+    Current10 = rvec[0x10];
+    Current6D = rvec[0x6D];
+
+    /* POST the secondary BIOS */
+    rvec[0x10] = rvec[0x42]; /* Restore int 10h to STD-BIOS */
+    regs.x.ax = axVal;
+    PM_callRealMode(0xC000,0x0003,&regs,&sregs);
+
+    /* Restore interrupt vectors */
+    rvec[0x10] = Current10;
+    rvec[0x6D] = Current6D;
+
+    /* Restore original BIOS image */
+    if (BIOSPhysAddr != 0xC0000)
+	memcpy(bios_ptr,old_bios,BIOSLen);
+    PM_free(old_bios);
+    return true;
+}
+
+int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;
+    return 1;
+}
+
+int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;
+    return 1;
+}
+
+int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;
+    return 1;
+}
+
+int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;
+    return 1;
+}
+
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    /* TODO: Implement this to load shared libraries! */
+    (void)szDLLName;
+    return NULL;
+}
+
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    /* TODO: Implement this! */
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    /* TODO: Implement this! */
+    (void)hModule;
+}
+
+int PMAPI PM_setIOPL(
+    int level)
+{
+    /* TODO: Move the IOPL switching into this function!! */
+    return level;
+}
+
+void PMAPI PM_flushTLB(void)
+{
+    /* Do nothing on Linux. */
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c
new file mode 100755
index 0000000..579ef2c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c
@@ -0,0 +1,49 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    baseAddr = baseAddr;
+    bankSize = bankSize;
+    codeLen = codeLen;
+    bankFunc = bankFunc;
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c
new file mode 100755
index 0000000..1b9bae2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c
@@ -0,0 +1,95 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux
+*
+* Description:  Linux specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+#include <unistd.h>
+#include <sys/time.h>
+#include "pmapi.h"
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+void __ZTimerInit(void)
+{
+}
+
+/****************************************************************************
+REMARKS:
+Use the gettimeofday() function to get microsecond precision (probably less
+though)
+****************************************************************************/
+static inline ulong __ULZReadTime(void)
+{
+    struct timeval t;
+    gettimeofday(&t, NULL);
+    return t.tv_sec*1000000 + t.tv_usec;
+}
+
+/****************************************************************************
+REMARKS:
+Start the Zen Timer counting.
+****************************************************************************/
+#define __LZTimerOn(tm)     tm->start.low = __ULZReadTime()
+
+/****************************************************************************
+REMARKS:
+Compute the lap time since the timer was started.
+****************************************************************************/
+#define __LZTimerLap(tm)        (__ULZReadTime() - tm->start.low)
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOff(tm)        tm->end.low = __ULZReadTime()
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerCount(tm)  (tm->end.low - tm->start.low)
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION 1
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/makefile b/board/MAI/bios_emulator/scitech/src/pm/makefile
new file mode 100755
index 0000000..265f0e3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/makefile
@@ -0,0 +1,290 @@
+#############################################################################
+#
+#                   Copyright (C) 1996 SciTech Software.
+#                           All rights reserved.
+#
+# Descripton:   Generic makefile for the PM library. Builds the library
+#               file and all test programs.
+#
+#############################################################################
+
+.IMPORT .IGNORE : DEBUG_AGP_DRIVER TEST_HARNESS DEBUG_SDDPMI
+
+#----------------------------------------------------------------------------
+# Add DOS extender dependant flags to command line
+#----------------------------------------------------------------------------
+
+CFLAGS          += $(DX_CFLAGS)
+ASFLAGS         += $(DX_ASFLAGS)
+NO_PMLIB        := 1
+
+#----------------------------------------------------------------------------
+# Include definitions specific for the target system
+#----------------------------------------------------------------------------
+
+.IF $(USE_VXD)
+
+# Building for Win32 VxD (minimal PM library implementation)
+
+LIBNAME         = pm
+OBJECTS         = pm$O vflat$O ztimer$O cpuinfo$O mtrr$O fileio$O pcilib$O \
+                  agp$O malloc$O vgastate$O gavxd$O _pm$O _mtrr$O _cpuinfo$O \
+                  _int64$O _pcihelp$O
+DEPEND_SRC      := vxd;common;codepage;tests
+.SOURCE:           vxd common codepage tests
+
+.ELIF $(USE_NTDRV)
+
+# Building for NT device drivers (minimal PM library implementation)
+
+LIBNAME         = pm
+OBJECTS         = pm$O vflat$O ztimer$O cpuinfo$O mtrr$O mem$O irq$O int86$O \
+                  stdio$O stdlib$O pcilib$O agp$O malloc$O vgastate$O gantdrv$O \
+                  _pm$O _mtrr$O _cpuinfo$O _int64$O _pcihelp$O _irq$O
+DEPEND_SRC      := ntdrv;common;codepage;tests
+.SOURCE:           ntdrv common codepage tests
+
+.ELIF $(USE_WIN32)
+
+# Building for Win32
+
+CFLAGS          += -DUSE_OS_JOYSTICK
+LIBNAME         = pm
+OBJECTS         = pm$O vflat$O event$O ddraw$O ztimer$O cpuinfo$O pcilib$O \
+                  agp$O malloc$O vgastate$O gawin32$O ntservc$O _joy$O _cpuinfo$O \
+                  _int64$O _pcihelp$O
+DEPEND_SRC      := win32;common;codepage;tests
+.SOURCE:           win32 common codepage tests
+
+.ELIF $(USE_OS232)
+
+# Building for OS/2
+
+.IF $(USE_OS2GUI)
+LIBNAME         = pm_pm
+.ELSE
+LIBNAME         = pm
+.ENDIF
+OBJECTS         = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \
+                  agp$O malloc$O vgastate$O gaos2$O _pmos2$O _joy$O _cpuinfo$O \
+                  _int64$O _pcihelp$O dossctl$O
+DEPEND_SRC      := os2;common;codepage;tests
+.SOURCE:           os2 common codepage tests
+
+.ELIF $(USE_QNX)
+
+# Building for QNX
+
+USE_BIOS        := 1
+.IF $(USE_PHOTON)
+LIBNAME         = pm_ph
+.ELIF $(USE_X11)
+LIBNAME         = pm_x11
+.ELSE
+LIBNAME         = pm
+.ENDIF
+OBJECTS         = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \
+                  agp$O malloc$O mtrrqnx$O unixio$O vgastate$O gaqnx$O _joy$O \
+                  _mtrrqnx$O _cpuinfo$O _int64$O _pcihelp$O
+DEPEND_SRC      := qnx;common;codepage;tests
+.SOURCE:           qnx common codepage tests
+
+# Indicate that this program uses Nucleus device drivers (so needs I/O access)
+USE_NUCLEUS     := 1
+
+.ELIF $(USE_LINUX)
+
+# Building for Linux
+
+CFLAGS          += -DENABLE_MTRR -DUSE_OS_JOYSTICK
+.IF $(USE_X11)
+LIBNAME         = pm_x11
+.ELSE
+LIBNAME         = pm
+.ENDIF
+OBJECTS         = pm$O vflat$O event$O ztimer$O cpuinfo$O pcilib$O \
+                  agp$O malloc$O unixio$O vgastate$O galinux$O _cpuinfo$O \
+                  _int64$O _pcihelp$O
+DEPEND_SRC      := linux;common;codepage;tests;x11
+.SOURCE:           linux common codepage tests x11
+
+# Building a shared library
+.IF $(SOFILE)
+LIB             := ld
+LIBFLAGS        := -r -o
+CFLAGS          += -fPIC
+.ENDIF
+
+.ELIF $(USE_BEOS)
+
+# Building for BeOS GUI
+
+LIBNAME         = pm
+OBJECTS         = pm$O vflat$O event$O ztimer$O cpuinfo$O pcilib$O \
+                  agp$O malloc$O vgastate$O gabeos$O _joy$O _cpuinfo$O \
+                  _int64$O _pcihelp$O
+DEPEND_SRC      := beos;common;codepage;tests
+.SOURCE:           beos common codepage tests
+
+.ELIF $(USE_SMX32)
+
+# Building for SMX
+
+LIBNAME         = pm
+OBJECTS         = pm$O pmsmx$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \
+                  agp$O malloc$O vgastate$O gasmx$O _pm$O _pmsmx$O _mtrr$O _event$O \
+                  _joy$O _cpuinfo$O _int64$O _pcihelp$O _lztimer$O
+DEPEND_SRC      := smx;common;codepage;tests
+.SOURCE:           smx common codepage tests
+
+.ELIF $(USE_RTTARGET)
+
+# Building for RTTarget-32
+
+LIBNAME         = pm
+OBJECTS         = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \
+                  agp$O malloc$O vgastate$O gartt$O _mtrr$O _joy$O _cpuinfo$O \
+                  _int64$O _pcihelp$O
+DEPEND_SRC      := rttarget;common;codepage;tests
+.SOURCE:           rttarget common codepage tests
+
+.ELSE
+
+# Building for MSDOS
+
+LIBNAME         = pm
+OBJECTS         = pm$O pmdos$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O \
+                  agp$O malloc$O pcilib$O vgastate$O gados$O \
+                  _pm$O _pmdos$O _mtrr$O _vflat$O _event$O _joy$O _pcihelp$O \
+                  _cpuinfo$O _int64$O _lztimer$O _dma$O
+DEPEND_SRC      := dos;common;codepage;tests
+.SOURCE:           dos common codepage tests
+
+.ENDIF
+
+# Object modules for keyboard code pages
+
+OBJECTS         += us_eng$O
+
+# Common object modules
+
+OBJECTS         += common$O
+.IF $(CHECKED)
+OBJECTS         += debug$O
+.ENDIF
+
+# Nucleus loader library object modules. Note that when compiling a test harness
+# library we need to exclude the Nucleus loader library.
+
+.IF $(TEST_HARNESS)
+CFLAGS          += -DTEST_HARNESS -DPMLIB
+LIBNAME         = pm_test
+.ELSE
+OBJECTS         += galib$O _ga_imp$O
+.ENDIF
+
+.IF $(DEBUG_SDDPMI)
+CFLAGS          += -DDEBUG_SDDPMI
+.ENDIF
+
+# AGP library object modules
+
+.IF $(DEBUG_AGP_DRIVER)
+CFLAGS          += -DDEBUG_AGP_DRIVER
+OBJECTS         += agplib$O
+.ELSE
+OBJECTS         += agplib$O peloader$O libcimp$O _gatimer$O
+.ENDIF
+
+#----------------------------------------------------------------------------
+# Name of library and generic object files required to build it
+#----------------------------------------------------------------------------
+
+.IF $(STKCALL)
+LIBFILE         = s$(LP)$(LIBNAME)$L
+.ELSE
+LIBFILE         = $(LP)$(LIBNAME)$L
+.ENDIF
+LIBCLEAN        = *.lib *.a
+
+#----------------------------------------------------------------------------
+# Change destination for library file depending the extender being used. This
+# is only necessary for DOS extender since the file go into a subdirectory
+# in the normal library directory, one for each supported extender. Other
+# OS'es put the file into the regular library directory, since there is
+# only one per OS in this case.
+#----------------------------------------------------------------------------
+
+MK_PMODE        = 1
+
+.IF $(TEST_HARNESS)
+LIB_DEST        := $(LIB_BASE)
+.ELIF $(USE_TNT)
+LIB_DEST        := $(LIB_BASE)\tnt
+.ELIF $(USE_DOS4GW)
+LIB_DEST        := $(LIB_BASE)\dos4gw
+.ELIF $(USE_X32)
+LIB_DEST        := $(LIB_BASE)\x32
+.ELIF $(USE_DPMI16)
+LIB_DEST        := $(LIB_BASE)\dpmi16
+.ELIF $(USE_DPMI32)
+LIB_DEST        := $(LIB_BASE)\dpmi32
+.ELIF $(USE_DOSX)
+LIB_DEST        := $(LIB_BASE)\dosx
+.END
+
+#----------------------------------------------------------------------------
+# Names of all executable files built
+#----------------------------------------------------------------------------
+
+.IF $(USE_REALDOS)
+EXEFILES        = memtest$E biosptr$E video$E isvesa$E callreal$E       \
+                  mouse$E tick$E key$E key15$E brk$E altbrk$E           \
+                  critical$E altcrit$E vftest$E rtc$E getch$E           \
+                  cpu$E timerc$E timercpp$E showpci$E uswc$E block$E
+.ELSE
+EXEFILES        = memtest$E video$E isvesa$E callreal$E vftest$E getch$E \
+                  cpu$E timerc$E timercpp$E showpci$E uswc$E block$E \
+                  save$E restore$E
+.ENDIF
+
+all: $(EXEFILES)
+
+$(EXEFILES): $(LIBFILE)
+
+memtest$E:  memtest$O
+biosptr$E:  biosptr$O
+video$E:    video$O
+isvesa$E:   isvesa$O
+mouse$E:    mouse$O
+tick$E:     tick$O
+key$E:      key$O
+key15$E:    key15$O
+brk$E:      brk$O
+altbrk$E:   altbrk$O
+critical$E: critical$O
+altcrit$E:  altcrit$O
+callreal$E: callreal$O
+vftest$E:   vftest$O
+rtc$E:      rtc$O
+getch$E:    getch$O
+cpu$E:      cpu$O
+timerc$E:   timerc$O
+timercpp$E: timercpp$O
+showpci$E:  showpci$O
+uswc$E:     uswc$O
+block$E:    block$O
+save$E:     save$O
+restore$E:  restore$O
+test$E:     test$O _test$O
+
+#----------------------------------------------------------------------------
+# Define the list of object files to create dependency information for
+#----------------------------------------------------------------------------
+
+DEPEND_OBJ      := $(OBJECTS) memtest$O biosptr$O video$O isvesa$O mouse$O  \
+                   tick$O key$O key$O brk$O altbrk$O critical$O altcrit$O   \
+                   callreal$O vftest$O getch$O timercpp$O
+
+.INCLUDE: "$(SCITECH)/makedefs/common.mk"
+
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm
new file mode 100755
index 0000000..11824a0
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm
@@ -0,0 +1,288 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: 32-bit Windows NT device driver
+;*
+;* Description: Low level assembly support for the PM library specific to
+;*              Windows NT device drivers.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+header      _irq                ; Set up memory model
+
+begdataseg  _irq
+
+    cextern _PM_rtcHandler,CPTR
+    cextern _PM_prevRTC,FCPTR
+
+RtcInside   dw      0           ; Are we still handling current interrupt
+sidtBuf     df      0           ; Buffer for sidt instruction
+
+enddataseg  _irq
+
+begcodeseg  _irq                ; Start of code segment
+
+cpublic _PM_irqCodeStart
+
+; Macro to delay briefly to ensure that enough time has elapsed between
+; successive I/O accesses so that the device being accessed can respond
+; to both accesses even on a very fast PC.
+
+ifdef   USE_NASM
+%macro  DELAY 0
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+%endmacro
+%macro  IODELAYN 1
+%rep    %1
+        DELAY
+%endrep
+%endmacro
+else
+macro   DELAY
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+endm
+macro   IODELAYN    N
+    rept    N
+        DELAY
+    endm
+endm
+endif
+
+;----------------------------------------------------------------------------
+; PM_rtcISR - Real time clock interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the timer interrupt, to dispatch control
+; to high level C based subroutines. We save the state of all registers
+; in this routine, and switch to a local stack. Interrupts are *off*
+; when we call the user code.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. Make sure your C code executes as
+;       quickly as possible, since a timer overrun will simply hang the
+;       system.
+;----------------------------------------------------------------------------
+cprocfar    _PM_rtcISR
+
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+; If we enable interrupts and call into any C based interrupt handling code,
+; we need to setup a bunch of important information for the NT kernel. The
+; code below takes care of this housekeeping for us (see Undocumented NT for
+; details). If we don't do this housekeeping and interrupts are enabled,
+; the kernel will become very unstable and crash within 10 seconds or so.
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+        pushad
+        pushfd
+        push    fs
+
+        mov     ebx,00000030h
+        mov     fs,bx
+        sub     esp,50h
+        mov     ebp,esp
+
+; Setup the exception frame to NULL
+
+        mov     ebx,[DWORD cs:0FFDFF000h]
+        mov     [DWORD ds:0FFDFF000h], 0FFFFFFFFh
+        mov     [DWORD ebp],ebx
+
+; Save away the existing KSS ebp
+
+        mov     esi,[DWORD cs:0FFDFF124h]
+        mov     ebx,[DWORD esi+00000128h]
+        mov     [DWORD ebp+4h],ebx
+        mov     [DWORD esi+00000128h],ebp
+
+; Save away the kernel time and the thread mode (kernel/user)
+
+        mov     edi,[DWORD esi+00000137h]
+        mov     [DWORD ebp+8h],edi
+
+; Set the thread mode (kernel/user) based on the code selector
+
+        mov     ebx,[DWORD ebp+7Ch]
+        and     ebx,01
+        mov     [BYTE esi+00000137h],bl
+
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+; End of special interrupt Prolog code
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+; Clear priority interrupt controller and re-enable interrupts so we
+; dont lock things up for long.
+
+        mov     al,20h
+        out     0A0h,al
+        out     020h,al
+
+; Clear real-time clock timeout
+
+        in      al,70h              ; Read CMOS index register
+        push    eax                 ;  and save for later
+        IODELAYN 3
+        mov     al,0Ch
+        out     70h,al
+        IODELAYN 5
+        in      al,71h
+
+; Call the C interrupt handler function
+
+        cmp     [BYTE RtcInside],1  ; Check for mutual exclusion
+        je      @@Exit
+        mov     [BYTE RtcInside],1
+        sti                         ; Enable interrupts
+        cld                         ; Clear direction flag for C code
+        call    [CPTR _PM_rtcHandler]
+        cli                         ; Disable interrupts on exit!
+        mov     [BYTE RtcInside],0
+
+@@Exit: pop     eax
+        out     70h,al              ; Restore CMOS index register
+
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+; Start of special epilog code to restore stuff on exit from handler
+;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+; Restore the KSS ebp
+
+        mov     esi,[DWORD cs:0FFDFF124h]
+        mov     ebx,[DWORD ebp+4]
+        mov     [DWORD esi+00000128h],ebx
+
+; Restore the exception frame
+
+        mov     ebx,[DWORD ebp]
+        mov     [DWORD fs:00000000],ebx
+
+; Restore the thread mode
+
+        mov     ebx,[DWORD ebp+8h]
+        mov     esi,[DWORD fs:00000124h]
+        mov     [BYTE esi+00000137h],bl
+        add     esp, 50h
+        pop     fs
+        popfd
+        popad
+
+; Return from interrupt
+
+        iret
+
+cprocend
+
+cpublic _PM_irqCodeEnd
+
+;----------------------------------------------------------------------------
+; void _PM_getISR(int irq,PMFARPTR *handler);
+;----------------------------------------------------------------------------
+; Function to return the specific IRQ handler direct from the IDT.
+;----------------------------------------------------------------------------
+cprocstart  _PM_getISR
+
+        ARG     idtEntry:UINT, handler:DPTR
+
+        enter_c 0
+        mov     ecx,[handler]           ; Get address of handler to fill in
+        sidt    [sidtBuf]               ; Get IDTR register into sidtBuf
+        mov     eax,[DWORD sidtBuf+2]   ; Get address of IDT into EAX
+        mov     ebx,[idtEntry]
+        lea     eax,[eax+ebx*8]         ; Get entry in the IDT
+        movzx   edx,[WORD eax+6]        ; Get high order 16-bits
+        shl     edx,16                  ; Move into top 16-bits of address
+        mov     dx,[WORD eax]           ; Get low order 16-bits
+        mov     [DWORD ecx],edx         ; Store linear address of handler
+        mov     dx,[WORD eax+2]         ; Get selector value
+        mov     [WORD ecx+4],dx         ; Store selector value
+        leave_c
+        ret
+
+cprocend    _PM_getISR
+
+;----------------------------------------------------------------------------
+; void _PM_setISR(int irq,void *handler);
+;----------------------------------------------------------------------------
+; Function to set the specific IRQ handler direct in the IDT.
+;----------------------------------------------------------------------------
+cprocstart  _PM_setISR
+
+        ARG     irq:UINT, handler:CPTR
+
+        enter_c 0
+        mov     ecx,[handler]           ; Get address of new handler
+        mov     dx,cs                   ; Get selector for new handler
+        sidt    [sidtBuf]               ; Get IDTR register into sidtBuf
+        mov     eax,[DWORD sidtBuf+2]   ; Get address of IDT into EAX
+        mov     ebx,[idtEntry]
+        lea     eax,[eax+ebx*8]         ; Get entry in the IDT
+        cli
+        mov     [WORD eax+2],dx         ; Store code segment selector
+        mov     [WORD eax],cx           ; Store low order bits of handler
+        shr     ecx,16
+        mov     [WORD eax+6],cx         ; Store high order bits of handler
+        sti
+        leave_c
+        ret
+
+cprocend    _PM_setISR
+
+;----------------------------------------------------------------------------
+; void _PM_restoreISR(int irq,PMFARPTR *handler);
+;----------------------------------------------------------------------------
+; Function to set the specific IRQ handler direct in the IDT.
+;----------------------------------------------------------------------------
+cprocstart  _PM_restoreISR
+
+        ARG     irq:UINT, handler:CPTR
+
+        enter_c 0
+        mov     ecx,[handler]
+        mov     dx,[WORD ecx+4]         ; Get selector for old handler
+        mov     ecx,[DWORD ecx]         ; Get address of old handler
+        sidt    [sidtBuf]               ; Get IDTR register into sidtBuf
+        mov     eax,[DWORD sidtBuf+2]   ; Get address of IDT into EAX
+        mov     ebx,[idtEntry]
+        lea     eax,[eax+ebx*8]         ; Get entry in the IDT
+        cli
+        mov     [WORD eax+2],dx         ; Store code segment selector
+        mov     [WORD eax],cx           ; Store low order bits of handler
+        shr     ecx,16
+        mov     [WORD eax+6],cx         ; Store high order bits of handler
+        sti
+        leave_c
+        ret
+
+cprocend    _PM_restoreISR
+
+endcodeseg  _irq
+
+        END                     ; End of module
+
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm
new file mode 100755
index 0000000..6cb276d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm
@@ -0,0 +1,281 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: 32-bit Windows NT device driver
+;*
+;* Description: Low level assembly support for the PM library specific to
+;*              Windows NT device drivers.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"               ; Memory model macros
+
+header      _pm                     ; Set up memory model
+
+P586
+
+begdataseg
+
+; Watcom C++ externals required to link when compiling floating point
+; C code. They are not actually used in the code because we compile with
+; inline floating point instructions, however the compiler still generates
+; the references in the object modules.
+
+__8087      dd  0
+            PUBLIC  __8087
+__imthread:
+__fltused:
+_fltused_   dd  0
+            PUBLIC  __imthread
+            PUBLIC  _fltused_
+            PUBLIC  __fltused
+
+enddataseg
+
+begcodeseg  _pm                 ; Start of code segment
+
+;----------------------------------------------------------------------------
+; void PM_segread(PMSREGS *sregs)
+;----------------------------------------------------------------------------
+; Read the current value of all segment registers
+;----------------------------------------------------------------------------
+cprocstart  PM_segread
+
+        ARG     sregs:DPTR
+
+        enter_c
+
+        mov     ax,es
+        _les    _si,[sregs]
+        mov     [_ES _si],ax
+        mov     [_ES _si+2],cs
+        mov     [_ES _si+4],ss
+        mov     [_ES _si+6],ds
+        mov     [_ES _si+8],fs
+        mov     [_ES _si+10],gs
+
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs)
+;----------------------------------------------------------------------------
+; Issues a software interrupt in protected mode. This routine has been
+; written to allow user programs to load CS and DS with different values
+; other than the default.
+;----------------------------------------------------------------------------
+cprocstart  PM_int386x
+
+; Not used for NT device drivers
+
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setBankA(int bank)
+;----------------------------------------------------------------------------
+cprocstart      PM_setBankA
+
+; Not used for NT device drivers
+
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setBankAB(int bank)
+;----------------------------------------------------------------------------
+cprocstart      PM_setBankAB
+
+; Not used for NT device drivers
+
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setCRTStart(int x,int y,int waitVRT)
+;----------------------------------------------------------------------------
+cprocstart      PM_setCRTStart
+
+; Not used for NT device drivers
+
+        ret
+
+cprocend
+
+; Macro to delay briefly to ensure that enough time has elapsed between
+; successive I/O accesses so that the device being accessed can respond
+; to both accesses even on a very fast PC.
+
+ifdef   USE_NASM
+%macro  DELAY 0
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+%endmacro
+%macro  IODELAYN 1
+%rep    %1
+        DELAY
+%endrep
+%endmacro
+else
+macro   DELAY
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+endm
+macro   IODELAYN    N
+    rept    N
+        DELAY
+    endm
+endm
+endif
+
+;----------------------------------------------------------------------------
+; uchar _PM_readCMOS(int index)
+;----------------------------------------------------------------------------
+; Read the value of a specific CMOS register. We do this with both
+; normal interrupts and NMI disabled.
+;----------------------------------------------------------------------------
+cprocstart  _PM_readCMOS
+
+        ARG     index:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        pushfd
+        mov     al,[BYTE index]
+        or      al,80h              ; Add disable NMI flag
+        cli
+        out     70h,al
+        IODELAYN 5
+        in      al,71h
+        mov     ah,al
+        xor     al,al
+        IODELAYN 5
+        out     70h,al              ; Re-enable NMI
+        mov     al,ah               ; Return value in AL
+        popfd
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _PM_writeCMOS(int index,uchar value)
+;----------------------------------------------------------------------------
+; Read the value of a specific CMOS register. We do this with both
+; normal interrupts and NMI disabled.
+;----------------------------------------------------------------------------
+cprocstart  _PM_writeCMOS
+
+        ARG     index:UINT, value:UCHAR
+
+        push    _bp
+        mov     _bp,_sp
+        pushfd
+        mov     al,[BYTE index]
+        or      al,80h              ; Add disable NMI flag
+        cli
+        out     70h,al
+        IODELAYN 5
+        mov     al,[value]
+        out     71h,al
+        xor     al,al
+        IODELAYN 5
+        out     70h,al              ; Re-enable NMI
+        popfd
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; double _ftol(double f)
+;----------------------------------------------------------------------------
+; Calls to __ftol are generated by the Borland C++ compiler for code
+; that needs to convert a floating point type to an integral type.
+;
+; Input: floating point number on the top of the '87.
+;
+; Output: a (signed or unsigned) long in EAX
+; All other registers preserved.
+;-----------------------------------------------------------------------
+cprocstart  _ftol
+
+        LOCAL   temp1:WORD, temp2:QWORD = LocalSize
+
+        push    ebp
+        mov     ebp,esp
+        sub     esp,LocalSize
+
+        fstcw   [temp1]                 ; save the control word
+        fwait
+        mov     al,[BYTE temp1+1]
+        or      [BYTE temp1+1],0Ch      ; set rounding control to chop
+        fldcw   [temp1]
+        fistp   [temp2]                 ; convert to 64-bit integer
+        mov     [BYTE temp1+1],al
+        fldcw   [temp1]                 ; restore the control word
+        mov     eax,[DWORD temp2]       ; return LS 32 bits
+        mov     edx,[DWORD temp2+4]     ;        MS 32 bits
+
+        mov     esp,ebp
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; _PM_getPDB - Return the Page Table Directory Base address
+;----------------------------------------------------------------------------
+cprocstart  _PM_getPDB
+
+        mov     eax,cr3
+        and     eax,0FFFFF000h
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; Flush the Translation Lookaside buffer
+;----------------------------------------------------------------------------
+cprocstart  PM_flushTLB
+
+        wbinvd                  ; Flush the CPU cache
+        mov     eax,cr3
+        mov     cr3,eax         ; Flush the TLB
+        ret
+
+cprocend
+
+endcodeseg  _pm
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c
new file mode 100755
index 0000000..d15b07c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c
@@ -0,0 +1,64 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows VxD
+*
+* Description:  VxD specific code for the CPU detection module.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Do nothing for VxD's
+****************************************************************************/
+#define SetMaxThreadPriority()      0
+
+/****************************************************************************
+REMARKS:
+Do nothing for VxD's
+****************************************************************************/
+#define RestoreThreadPriority(i)    (void)(i)
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    KeQueryPerformanceCounter((LARGE_INTEGER*)freq);
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)                                       \
+{                                                           \
+    LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL);     \
+    (t)->low = lt.LowPart;                                  \
+    (t)->high = lt.HighPart;                                \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c
new file mode 100755
index 0000000..c82648b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c
@@ -0,0 +1,251 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows NT device drivers.
+*
+* Description:  Implementation for the real mode software interrupt
+*               handling functions.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "sdd/sddhelp.h"
+#include "mtrr.h"
+#include "oshdr.h"
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+We do have limited BIOS access under Windows NT device drivers.
+****************************************************************************/
+ibool PMAPI PM_haveBIOSAccess(void)
+{
+    /* Return false unless we have full buffer passing! */
+    return false;
+}
+
+/****************************************************************************
+PARAMETERS:
+len     - Place to store the length of the buffer
+rseg    - Place to store the real mode segment of the buffer
+roff    - Place to store the real mode offset of the buffer
+
+REMARKS:
+This function returns the address and length of the global VESA transfer
+buffer that is used for communicating with the VESA BIOS functions from
+Win16 and Win32 programs under Windows.
+****************************************************************************/
+void * PMAPI PM_getVESABuf(
+    uint *len,
+    uint *rseg,
+    uint *roff)
+{
+    /* No buffers supported under Windows NT (Windows XP has them however if */
+    /* we ever decide to support this!) */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Issue a protected mode software interrupt.
+****************************************************************************/
+int PMAPI PM_int386(
+    int intno,
+    PMREGS *in,
+    PMREGS *out)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return PM_int386x(intno,in,out,&sregs);
+}
+
+/****************************************************************************
+REMARKS:
+Map a real mode pointer to a protected mode pointer.
+****************************************************************************/
+void * PMAPI PM_mapRealPointer(
+    uint r_seg,
+    uint r_off)
+{
+    /* Not used for Windows NT drivers! */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of real mode memory
+****************************************************************************/
+void * PMAPI PM_allocRealSeg(
+    uint size,
+    uint *r_seg,
+    uint *r_off)
+{
+    /* Not supported in NT drivers */
+    (void)size;
+    (void)r_seg;
+    (void)r_off;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of real mode memory.
+****************************************************************************/
+void PMAPI PM_freeRealSeg(
+    void *mem)
+{
+    /* Not supported in NT drivers */
+    (void)mem;
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt (parameters in DPMI compatible structure)
+****************************************************************************/
+void PMAPI DPMI_int86(
+    int intno,
+    DPMI_regs *regs)
+{
+    /* Not used in NT drivers */
+}
+
+/****************************************************************************
+REMARKS:
+Call a V86 real mode function with the specified register values
+loaded before the call. The call returns with a far ret.
+****************************************************************************/
+void PMAPI PM_callRealMode(
+    uint seg,
+    uint off,
+    RMREGS *regs,
+    RMSREGS *sregs)
+{
+    /* TODO!! */
+#if 0
+    CLIENT_STRUCT saveRegs;
+
+    /* Bail if we do not have BIOS access (ie: the VxD was dynamically
+     * loaded, and not statically loaded.
+     */
+    if (!_PM_haveBIOS)
+	return;
+
+    TRACE("SDDHELP: Entering PM_callRealMode()\n");
+    Begin_Nest_V86_Exec();
+    LoadV86Registers(&saveRegs,regs,sregs);
+    Simulate_Far_Call(seg, off);
+    Resume_Exec();
+    ReadV86Registers(&saveRegs,regs,sregs);
+    End_Nest_Exec();
+    TRACE("SDDHELP: Exiting PM_callRealMode()\n");
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Issue a V86 real mode interrupt with the specified register values
+loaded before the interrupt.
+****************************************************************************/
+int PMAPI PM_int86(
+    int intno,
+    RMREGS *in,
+    RMREGS *out)
+{
+    /* TODO!! */
+#if 0
+    RMSREGS         sregs = {0};
+    CLIENT_STRUCT   saveRegs;
+    ushort          oldDisable;
+
+    /* Disable pass-up to our VxD handler so we directly call BIOS */
+    TRACE("SDDHELP: Entering PM_int86()\n");
+    if (disableTSRFlag) {
+	oldDisable = *disableTSRFlag;
+	*disableTSRFlag = 0;
+	}
+    Begin_Nest_V86_Exec();
+    LoadV86Registers(&saveRegs,in,&sregs);
+    Exec_Int(intno);
+    ReadV86Registers(&saveRegs,out,&sregs);
+    End_Nest_Exec();
+
+    /* Re-enable pass-up to our VxD handler if previously enabled */
+    if (disableTSRFlag)
+	*disableTSRFlag = oldDisable;
+
+    TRACE("SDDHELP: Exiting PM_int86()\n");
+#else
+    *out = *in;
+#endif
+    return out->x.ax;
+}
+
+/****************************************************************************
+REMARKS:
+Issue a V86 real mode interrupt with the specified register values
+loaded before the interrupt.
+****************************************************************************/
+int PMAPI PM_int86x(
+    int intno,
+    RMREGS *in,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    /* TODO!! */
+#if 0
+    CLIENT_STRUCT   saveRegs;
+    ushort          oldDisable;
+
+    /* Bail if we do not have BIOS access (ie: the VxD was dynamically
+     * loaded, and not statically loaded.
+     */
+    if (!_PM_haveBIOS) {
+	*out = *in;
+	return out->x.ax;
+	}
+
+    /* Disable pass-up to our VxD handler so we directly call BIOS */
+    TRACE("SDDHELP: Entering PM_int86x()\n");
+    if (disableTSRFlag) {
+	oldDisable = *disableTSRFlag;
+	*disableTSRFlag = 0;
+	}
+    Begin_Nest_V86_Exec();
+    LoadV86Registers(&saveRegs,in,sregs);
+    Exec_Int(intno);
+    ReadV86Registers(&saveRegs,out,sregs);
+    End_Nest_Exec();
+
+    /* Re-enable pass-up to our VxD handler if previously enabled */
+    if (disableTSRFlag)
+	*disableTSRFlag = oldDisable;
+
+    TRACE("SDDHELP: Exiting PM_int86x()\n");
+#else
+    *out = *in;
+#endif
+    return out->x.ax;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c
new file mode 100755
index 0000000..9cd5204
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c
@@ -0,0 +1,142 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows NT device drivers.
+*
+* Description:  Implementation for the NT driver IRQ management functions
+*               for the PM library.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "pmint.h"
+#include "drvlib/os/os.h"
+#include "sdd/sddhelp.h"
+#include "mtrr.h"
+#include "oshdr.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+static int          globalDataStart;
+static uchar        _PM_oldCMOSRegA;
+static uchar        _PM_oldCMOSRegB;
+static uchar        _PM_oldRTCPIC2;
+static ulong        RTC_idtEntry;
+PM_intHandler       _PM_rtcHandler = NULL;
+PMFARPTR    _VARAPI _PM_prevRTC = PMNULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* Functions to read and write CMOS registers */
+
+uchar   _ASMAPI _PM_readCMOS(int index);
+void    _ASMAPI _PM_writeCMOS(int index,uchar value);
+void    _ASMAPI _PM_rtcISR(void);
+void    _ASMAPI _PM_getISR(int irq,PMFARPTR *handler);
+void    _ASMAPI _PM_setISR(int irq,void *handler);
+void    _ASMAPI _PM_restoreISR(int irq,PMFARPTR *handler);
+void    _ASMAPI _PM_irqCodeStart(void);
+void    _ASMAPI _PM_irqCodeEnd(void);
+
+/****************************************************************************
+REMARKS:
+Set the real time clock frequency (for stereo modes).
+****************************************************************************/
+void PMAPI PM_setRealTimeClockFrequency(
+    int frequency)
+{
+    static short convert[] = {
+	8192,
+	4096,
+	2048,
+	1024,
+	512,
+	256,
+	128,
+	64,
+	32,
+	16,
+	8,
+	4,
+	2,
+	-1,
+	};
+    int i;
+
+    /* First clear any pending RTC timeout if not cleared */
+    _PM_readCMOS(0x0C);
+    if (frequency == 0) {
+	/* Disable RTC timout */
+	_PM_writeCMOS(0x0A,(uchar)_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,(uchar)(_PM_oldCMOSRegB & 0x0F));
+	}
+    else {
+	/* Convert frequency value to RTC clock indexes */
+	for (i = 0; convert[i] != -1; i++) {
+	    if (convert[i] == frequency)
+		break;
+	    }
+
+	/* Set RTC timout value and enable timeout */
+	_PM_writeCMOS(0x0A,(uchar)(0x20 | (i+3)));
+	_PM_writeCMOS(0x0B,(uchar)((_PM_oldCMOSRegB & 0x0F) | 0x40));
+	}
+}
+
+ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency)
+{
+    static ibool    locked = false;
+
+    /* Save the old CMOS real time clock values */
+    _PM_oldCMOSRegA = _PM_readCMOS(0x0A);
+    _PM_oldCMOSRegB = _PM_readCMOS(0x0B);
+
+    /* Install the interrupt handler */
+    RTC_idtEntry = 0x38;
+    _PM_getISR(RTC_idtEntry, &_PM_prevRTC);
+    _PM_rtcHandler = th;
+    _PM_setISR(RTC_idtEntry, _PM_rtcISR);
+
+    /* Program the real time clock default frequency */
+    PM_setRealTimeClockFrequency(frequency);
+
+    /* Unmask IRQ8 in the PIC2 */
+    _PM_oldRTCPIC2 = PM_inpb(0xA1);
+    PM_outpb(0xA1,(uchar)(_PM_oldRTCPIC2 & 0xFE));
+    return true;
+}
+
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    if (_PM_rtcHandler) {
+	/* Restore CMOS registers and mask RTC clock */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB);
+	PM_outpb(0xA1,(uchar)((PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)));
+
+	/* Restore the interrupt vector */
+	_PM_restoreISR(RTC_idtEntry, &_PM_prevRTC);
+	_PM_rtcHandler = NULL;
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c
new file mode 100755
index 0000000..3128c6a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c
@@ -0,0 +1,518 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows NT device drivers.
+*
+* Description:  Implementation for the NT driver memory management functions
+*               for the PM library.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "sdd/sddhelp.h"
+#include "mtrr.h"
+#include "oshdr.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+#define MAX_MEMORY_SHARED           100
+#define MAX_MEMORY_MAPPINGS         100
+#define MAX_MEMORY_LOCKED           100
+
+typedef struct {
+    void    *linear;
+    ulong   length;
+    PMDL    pMdl;
+    } memshared;
+
+typedef struct {
+    void    *linear;
+    void    *mmIoMapped;
+    ulong   length;
+    PMDL    pMdl;
+    } memlocked;
+
+typedef struct {
+    ulong   physical;
+    ulong   linear;
+    ulong   length;
+    ibool   isCached;
+    } mmapping;
+
+static int          numMappings = 0;
+static memshared    shared[MAX_MEMORY_MAPPINGS] = {0};
+static mmapping     maps[MAX_MEMORY_MAPPINGS];
+static memlocked    locked[MAX_MEMORY_LOCKED];
+
+/*----------------------------- Implementation ----------------------------*/
+
+ulong   PMAPI _PM_getPDB(void);
+
+/* Page table entry flags */
+
+#define PAGE_FLAGS_PRESENT			0x00000001
+#define PAGE_FLAGS_WRITEABLE		0x00000002
+#define PAGE_FLAGS_USER				0x00000004
+#define PAGE_FLAGS_WRITE_THROUGH	0x00000008
+#define PAGE_FLAGS_CACHE_DISABLE	0x00000010
+#define PAGE_FLAGS_ACCESSED			0x00000020
+#define PAGE_FLAGS_DIRTY			0x00000040
+#define PAGE_FLAGS_4MB	            0x00000080
+
+/****************************************************************************
+PARAMETERS:
+base        - Physical base address of the memory to maps in
+limit       - Limit of physical memory to region to maps in
+
+RETURNS:
+Linear address of the newly mapped memory.
+
+REMARKS:
+Maps a physical memory range to a linear memory range.
+****************************************************************************/
+static ulong _PM_mapPhysicalToLinear(
+    ulong base,
+    ulong limit,
+    ibool isCached)
+{
+    ulong               length = limit+1;
+    PHYSICAL_ADDRESS    paIoBase = {0};
+
+    /* NT loves large Ints */
+    paIoBase = RtlConvertUlongToLargeInteger( base );
+
+    /* Map IO space into Kernel */
+    if (isCached)
+	return (ULONG)MmMapIoSpace(paIoBase, length, MmCached );
+    else
+	return (ULONG)MmMapIoSpace(paIoBase, length, MmNonCached );
+}
+
+/****************************************************************************
+REMARKS:
+Adjust the page table caching bits directly. Requires ring 0 access and
+only works with DOS4GW and compatible extenders (CauseWay also works since
+it has direct support for the ring 0 instructions we need from ring 3). Will
+not work in a DOS box, but we call into the ring 0 helper VxD so we should
+never get here in a DOS box anyway (assuming the VxD is present). If we
+do get here and we are in windows, this code will be skipped.
+****************************************************************************/
+static void _PM_adjustPageTables(
+    ulong linear,
+    ulong limit,
+	ibool isGlobal,
+    ibool isCached)
+{
+    int     startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage;
+    ulong   pageTable,*pPDB,*pPageTable;
+	ulong	mask = 0xFFFFFFFF;
+	ulong	bits = 0x00000000;
+
+	/* Enable user level access for page table entry */
+	if (isGlobal) {
+		mask &= ~PAGE_FLAGS_USER;
+		bits |= PAGE_FLAGS_USER;
+		}
+
+	/* Disable PCD bit if page table entry should be uncached */
+	if (!isCached) {
+		mask &= ~(PAGE_FLAGS_CACHE_DISABLE | PAGE_FLAGS_WRITE_THROUGH);
+		bits |= (PAGE_FLAGS_CACHE_DISABLE | PAGE_FLAGS_WRITE_THROUGH);
+		}
+
+    pPDB = (ulong*)_PM_mapPhysicalToLinear(_PM_getPDB(),0xFFF,true);
+    if (pPDB) {
+	startPDB = (linear >> 22) & 0x3FF;
+	startPage = (linear >> 12) & 0x3FF;
+	endPDB = ((linear+limit) >> 22) & 0x3FF;
+	endPage = ((linear+limit) >> 12) & 0x3FF;
+	for (iPDB = startPDB; iPDB <= endPDB; iPDB++) {
+	    /* Set the bits in the page directory entry - required as per */
+	    /* Pentium 4 manual. This also takes care of the 4MB page entries */
+	    pPDB[iPDB] = (pPDB[iPDB] & mask) | bits;
+	    if (!(pPDB[iPDB] & PAGE_FLAGS_4MB)) {
+		/* If we are dealing with 4KB pages then we need to iterate */
+		/* through each of the page table entries */
+		pageTable = pPDB[iPDB] & ~0xFFF;
+		pPageTable = (ulong*)_PM_mapPhysicalToLinear(pageTable,0xFFF,true);
+		start = (iPDB == startPDB) ? startPage : 0;
+		end = (iPDB == endPDB) ? endPage : 0x3FF;
+		for (iPage = start; iPage <= end; iPage++) {
+		    pPageTable[iPage] = (pPageTable[iPage] & mask) | bits;
+		    }
+		MmUnmapIoSpace(pPageTable,0xFFF);
+		}
+	    }
+	MmUnmapIoSpace(pPDB,0xFFF);
+	PM_flushTLB();
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of shared memory. For NT we allocate shared memory
+as locked, global memory that is accessible from any memory context
+(including interrupt time context), which allows us to load our important
+data structure and code such that we can access it directly from a ring
+0 interrupt context.
+****************************************************************************/
+void * PMAPI PM_mallocShared(
+    long size)
+{
+    int         i;
+
+    /* First find a free slot in our shared memory table */
+    for (i = 0; i < MAX_MEMORY_SHARED; i++) {
+	if (shared[i].linear == 0)
+	    break;
+	}
+    if (i == MAX_MEMORY_SHARED)
+	return NULL;
+
+    /* Allocate the paged pool */
+    shared[i].linear = ExAllocatePool(PagedPool, size);
+
+    /* Create a list to manage this allocation */
+    shared[i].pMdl = IoAllocateMdl(shared[i].linear,size,FALSE,FALSE,(PIRP) NULL);
+
+    /* Lock this allocation in memory */
+    MmProbeAndLockPages(shared[i].pMdl,KernelMode,IoModifyAccess);
+
+    /* Modify bits to grant user access */
+    _PM_adjustPageTables((ulong)shared[i].linear, size, true, true);
+    return (void*)shared[i].linear;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of shared memory
+****************************************************************************/
+void PMAPI PM_freeShared(
+    void *p)
+{
+    int i;
+
+    /* Find a shared memory block in our table and free it */
+    for (i = 0; i < MAX_MEMORY_SHARED; i++) {
+	if (shared[i].linear == p) {
+	    /* Unlock what we locked */
+	    MmUnlockPages(shared[i].pMdl);
+
+	    /* Free our MDL */
+	    IoFreeMdl(shared[i].pMdl);
+
+	    /* Free our mem */
+	    ExFreePool(shared[i].linear);
+
+	    /* Flag that is entry is available */
+	    shared[i].linear = 0;
+	    break;
+	    }
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Map a physical address to a linear address in the callers process.
+****************************************************************************/
+void * PMAPI PM_mapPhysicalAddr(
+    ulong base,
+    ulong limit,
+    ibool isCached)
+{
+    ulong   linear,length = limit+1;
+    int     i;
+
+    /* Search table of existing mappings to see if we have already mapped */
+    /* a region of memory that will serve this purpose. */
+    for (i = 0; i < numMappings; i++) {
+	if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) {
+	    _PM_adjustPageTables((ulong)maps[i].linear, maps[i].length, true, isCached);
+	    return (void*)maps[i].linear;
+	    }
+	}
+    if (numMappings == MAX_MEMORY_MAPPINGS)
+	return NULL;
+
+    /* We did not find any previously mapped memory region, so maps it in. */
+    if ((linear = _PM_mapPhysicalToLinear(base,limit,isCached)) == 0xFFFFFFFF)
+	return NULL;
+    maps[numMappings].physical = base;
+    maps[numMappings].length = length;
+    maps[numMappings].linear = linear;
+    maps[numMappings].isCached = isCached;
+    numMappings++;
+
+    /* Grant user access to this I/O space */
+    _PM_adjustPageTables((ulong)linear, length, true, isCached);
+    return (void*)linear;
+}
+
+/****************************************************************************
+REMARKS:
+Free a physical address mapping allocated by PM_mapPhysicalAddr.
+****************************************************************************/
+void PMAPI PM_freePhysicalAddr(
+    void *ptr,
+    ulong limit)
+{
+    /* We don't free the memory mappings in here because we cache all */
+    /* the memory mappings we create in the system for later use. */
+}
+
+/****************************************************************************
+REMARKS:
+Called when the device driver unloads to free all the page table mappings!
+****************************************************************************/
+void PMAPI _PM_freeMemoryMappings(void)
+{
+    int i;
+
+    for (i = 0; i < numMappings; i++)
+	MmUnmapIoSpace((void *)maps[i].linear,maps[i].length);
+}
+
+/****************************************************************************
+REMARKS:
+Find the physical address of a linear memory address in current process.
+****************************************************************************/
+ulong PMAPI PM_getPhysicalAddr(
+    void *p)
+{
+    PHYSICAL_ADDRESS    paOurAddress;
+
+    paOurAddress = MmGetPhysicalAddress(p);
+    return paOurAddress.LowPart;
+}
+
+/****************************************************************************
+REMARKS:
+Find the physical address of a linear memory address in current process.
+****************************************************************************/
+ibool PMAPI PM_getPhysicalAddrRange(
+    void *p,
+    ulong length,
+    ulong *physAddress)
+{
+    int     i;
+    ulong   linear = (ulong)p & ~0xFFF;
+
+    for (i = (length + 0xFFF) >> 12; i > 0; i--) {
+	if ((*physAddress++ = PM_getPhysicalAddr((void*)linear)) == 0xFFFFFFFF)
+	    return false;
+	linear += 4096;
+	}
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Allocates a block of locked physical memory.
+****************************************************************************/
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16M)
+{
+    int                 i;
+    PHYSICAL_ADDRESS    paOurAddress;
+
+    /* First find a free slot in our shared memory table */
+    for (i = 0; i < MAX_MEMORY_LOCKED; i++) {
+	if (locked[i].linear == 0)
+	    break;
+	}
+    if (i == MAX_MEMORY_LOCKED)
+	return NULL;
+
+    /* HighestAcceptableAddress - Specifies the highest valid physical address */
+    /* the driver can use. For example, if a device can only reference physical */
+    /* memory in the lower 16MB, this value would be set to 0x00000000FFFFFF. */
+    paOurAddress.HighPart = 0;
+    if (below16M)
+	paOurAddress.LowPart = 0x00FFFFFF;
+    else
+	paOurAddress.LowPart = 0xFFFFFFFF;
+
+    if (contiguous) {
+	/* Allocate from the non-paged pool (unfortunately 4MB pages) */
+	locked[i].linear = MmAllocateContiguousMemory(size, paOurAddress);
+	if (!locked[i].linear)
+	    return NULL;
+
+	/* Flag no MDL */
+	locked[i].pMdl = NULL;
+
+	/* Map the physical address for the memory so we can manage */
+	/* the page tables in 4KB chunks mapped into user space. */
+
+	/* TODO: Map this with the physical address to the linear addresss */
+	locked[i].mmIoMapped = locked[i].linear;
+
+	/* Modify bits to grant user access, flag not cached */
+	_PM_adjustPageTables((ulong)locked[i].mmIoMapped, size, true, false);
+	return (void*)locked[i].mmIoMapped;
+	}
+    else {
+	/* Allocate from the paged pool */
+	locked[i].linear = ExAllocatePool(PagedPool, size);
+	if (!locked[i].linear)
+	    return NULL;
+
+	/* Create a list to manage this allocation */
+	locked[i].pMdl = IoAllocateMdl(locked[i].linear,size,FALSE,FALSE,(PIRP) NULL);
+
+	/* Lock this allocation in memory */
+	MmProbeAndLockPages(locked[i].pMdl,KernelMode,IoModifyAccess);
+
+	/* Modify bits to grant user access, flag not cached */
+	_PM_adjustPageTables((ulong)locked[i].linear, size, true, false);
+	return (void*)locked[i].linear;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Frees a block of locked physical memory.
+****************************************************************************/
+void PMAPI PM_freeLockedMem(
+    void *p,
+    uint size,
+    ibool contiguous)
+{
+    int i;
+
+    /* Find a locked memory block in our table and free it */
+    for (i = 0; i < MAX_MEMORY_LOCKED; i++) {
+	if (locked[i].linear == p) {
+	    /* An Mdl indicates that we used the paged pool, and locked it, */
+	    /* so now we have to unlock, free the MDL, and free paged */
+	    if (locked[i].pMdl) {
+		/* Unlock what we locked and free the Mdl */
+		MmUnlockPages(locked[i].pMdl);
+		IoFreeMdl(locked[i].pMdl);
+		ExFreePool(locked[i].linear);
+		}
+	    else {
+		/* TODO: Free the mmIoMap mapping for the memory! */
+
+		/* Free non-paged pool */
+		MmFreeContiguousMemory(locked[i].linear);
+		}
+
+	    /* Flag that is entry is available */
+	    locked[i].linear = 0;
+	    break;
+	    }
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Allocates a page aligned and page sized block of memory
+****************************************************************************/
+void * PMAPI PM_allocPage(
+    ibool locked)
+{
+    /* Allocate the memory from the non-paged pool if we want the memory */
+    /* to be locked. */
+    return ExAllocatePool(
+	locked ? NonPagedPoolCacheAligned : PagedPoolCacheAligned,
+	PAGE_SIZE);
+}
+
+/****************************************************************************
+REMARKS:
+Free a page aligned and page sized block of memory
+****************************************************************************/
+void PMAPI PM_freePage(
+    void *p)
+{
+    if (p) ExFreePool(p);
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockDataPages(
+    void *p,
+    uint len,
+    PM_lockHandle *lh)
+{
+    MDL *pMdl;
+
+    /* Create a list to manage this allocation */
+    if ((pMdl = IoAllocateMdl(p,len,FALSE,FALSE,(PIRP)NULL)) == NULL)
+	return false;
+
+    /* Lock this allocation in memory */
+    MmProbeAndLockPages(pMdl,KernelMode,IoModifyAccess);
+    *((PMDL*)(&lh->h)) = pMdl;
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockDataPages(
+    void *p,
+    uint len,
+    PM_lockHandle *lh)
+{
+    if (p && lh) {
+	/* Unlock what we locked */
+	MDL *pMdl = *((PMDL*)(&lh->h));
+	MmUnlockPages(pMdl);
+	IoFreeMdl(pMdl);
+	}
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockCodePages(
+    void (*p)(),
+    uint len,
+    PM_lockHandle *lh)
+{
+    return PM_lockDataPages((void*)p,len,lh);
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockCodePages(
+    void (*p)(),
+    uint len,
+    PM_lockHandle *lh)
+{
+    return PM_unlockDataPages((void*)p,len,lh);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h
new file mode 100755
index 0000000..65b7bae
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h
@@ -0,0 +1,45 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows NT drivers
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+#ifndef __NTDRV_OSHDR_H
+#define __NTDRV_OSHDR_H
+
+/*--------------------------- Macros and Typedefs -------------------------*/
+
+/*---------------------------- Global variables ---------------------------*/
+
+/*--------------------------- Function Prototypes -------------------------*/
+
+/* Internal unicode string handling functions */
+
+UNICODE_STRING *    _PM_CStringToUnicodeString(const char *cstr);
+void                _PM_FreeUnicodeString(UNICODE_STRING *uniStr);
+
+#endif  /* __NTDRV_OSHDR_H */
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c
new file mode 100755
index 0000000..c660631
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c
@@ -0,0 +1,933 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows NT device drivers.
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "sdd/sddhelp.h"
+#include "mtrr.h"
+#include "oshdr.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+char                _PM_cntPath[PM_MAX_PATH] = "";
+char                _PM_nucleusPath[PM_MAX_PATH] = "";
+static void (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+static char *szNTWindowsKey     = "\\REGISTRY\\Machine\\Software\\Microsoft\\Windows NT\\CurrentVersion";
+static char *szNTSystemRoot     = "SystemRoot";
+static char *szMachineNameKey   = "\\REGISTRY\\Machine\\System\\CurrentControlSet\\control\\ComputerName\\ComputerName";
+static char *szMachineNameKeyNT = "\\REGISTRY\\Machine\\System\\CurrentControlSet\\control\\ComputerName\\ActiveComputerName";
+static char *szMachineName      = "ComputerName";
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the PM library.
+****************************************************************************/
+void PMAPI PM_init(void)
+{
+    /* Initialiase the MTRR module */
+    MTRR_init();
+}
+
+/****************************************************************************
+REMARKS:
+Return the operating system type identifier.
+****************************************************************************/
+long PMAPI PM_getOSType(void)
+{
+    return _OS_WINNTDRV;
+}
+
+/****************************************************************************
+REMARKS:
+Return the runtime type identifier.
+****************************************************************************/
+int PMAPI PM_getModeType(void)
+{
+    return PM_386;
+}
+
+/****************************************************************************
+REMARKS:
+Add a file directory separator to the end of the filename.
+****************************************************************************/
+void PMAPI PM_backslash(char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '\\') {
+	s[pos] = '\\';
+	s[pos+1] = '\0';
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Add a user defined PM_fatalError cleanup function.
+****************************************************************************/
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+/****************************************************************************
+REMARKS:
+Handle fatal errors internally in the driver.
+****************************************************************************/
+void PMAPI PM_fatalError(
+    const char *msg)
+{
+    ULONG   BugCheckCode = 0;
+    ULONG   MoreBugCheckData[4] = {0};
+    char    *p;
+    ULONG   len;
+
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+
+#ifdef DBG	/* Send output to debugger, just return so as not to force a reboot */
+#pragma message("INFO: building for debug, PM_fatalError() re-routed")
+	DBGMSG2("SDDHELP> PM_fatalError(): ERROR: %s\n", msg);
+	return ;
+#endif
+    /* KeBugCheckEx brings down the system in a controlled */
+    /* manner when the caller discovers an unrecoverable */
+    /* inconsistency that would corrupt the system if */
+    /* the caller continued to run. */
+    /* */
+    /* hack - dump the first 20 chars in hex using the variables */
+    /*      provided - Each ULONG is equal to four characters... */
+    for(len = 0; len < 20; len++)
+	if (msg[len] == (char)0)
+	    break;
+
+    /* This looks bad but it's quick and reliable... */
+    p = (char *)&BugCheckCode;
+    if(len > 0) p[3] = msg[0];
+    if(len > 1) p[2] = msg[1];
+    if(len > 2) p[1] = msg[2];
+    if(len > 3) p[0] = msg[3];
+
+    p = (char *)&MoreBugCheckData[0];
+    if(len > 4) p[3] = msg[4];
+    if(len > 5) p[2] = msg[5];
+    if(len > 6) p[1] = msg[6];
+    if(len > 7) p[0] = msg[7];
+
+    p = (char *)&MoreBugCheckData[1];
+    if(len > 8) p[3] = msg[8];
+    if(len > 9) p[2] = msg[9];
+    if(len > 10) p[1] = msg[10];
+    if(len > 11) p[0] = msg[11];
+
+    p = (char *)&MoreBugCheckData[2];
+    if(len > 12) p[3] = msg[12];
+    if(len > 13) p[2] = msg[13];
+    if(len > 14) p[1] = msg[14];
+    if(len > 15) p[0] = msg[15];
+
+    p = (char *)&MoreBugCheckData[3];
+    if(len > 16) p[3] = msg[16];
+    if(len > 17) p[2] = msg[17];
+    if(len > 18) p[1] = msg[18];
+    if(len > 19) p[0] = msg[19];
+
+    /* Halt the system! */
+    KeBugCheckEx(BugCheckCode, MoreBugCheckData[0], MoreBugCheckData[1], MoreBugCheckData[2], MoreBugCheckData[3]);
+}
+
+/****************************************************************************
+REMARKS:
+Return the current operating system path or working directory.
+****************************************************************************/
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    strncpy(path,_PM_cntPath,maxLen);
+    path[maxLen-1] = 0;
+    return path;
+}
+
+/****************************************************************************
+PARAMETERS:
+szKey       - Key to query (can contain version number formatting)
+szValue     - Value to get information for
+value       - Place to store the registry key data read
+size        - Size of the string buffer to read into
+
+RETURNS:
+true if the key was found, false if not.
+****************************************************************************/
+static ibool REG_queryString(
+    char *szKey,
+    const char *szValue,
+    char *value,
+    DWORD size)
+{
+    ibool                           status;
+    NTSTATUS                        rval;
+    ULONG                           length;
+    HANDLE                          Handle;
+    OBJECT_ATTRIBUTES               keyAttributes;
+    UNICODE_STRING                  *uniKey = NULL;
+    UNICODE_STRING                  *uniValue = NULL;
+    PKEY_VALUE_FULL_INFORMATION		fullInfo = NULL;
+    STRING                          stringdata;
+    UNICODE_STRING                  unidata;
+
+    /* Convert strings to UniCode */
+    status = false;
+    if ((uniKey = _PM_CStringToUnicodeString(szKey)) == NULL)
+	goto Exit;
+    if ((uniValue = _PM_CStringToUnicodeString(szValue)) == NULL)
+	goto Exit;
+
+    /* Open the key */
+    InitializeObjectAttributes( &keyAttributes,
+				uniKey,
+				OBJ_CASE_INSENSITIVE,
+				NULL,
+				NULL );
+    rval = ZwOpenKey( &Handle,
+		      KEY_ALL_ACCESS,
+		      &keyAttributes );
+    if (!NT_SUCCESS(rval))
+	goto Exit;
+
+    /* Query the value */
+    length = sizeof (KEY_VALUE_FULL_INFORMATION)
+	   + size * sizeof(WCHAR);
+    if ((fullInfo = ExAllocatePool (PagedPool, length)) == NULL)
+	goto Exit;
+    RtlZeroMemory(fullInfo, length);
+    rval = ZwQueryValueKey (Handle,
+			    uniValue,
+			    KeyValueFullInformation,
+			    fullInfo,
+			    length,
+			    &length);
+    if (NT_SUCCESS (rval)) {
+	/* Create the UniCode string so we can convert it */
+	unidata.Buffer = (PWCHAR)(((PCHAR)fullInfo) + fullInfo->DataOffset);
+	unidata.Length = (USHORT)fullInfo->DataLength;
+	unidata.MaximumLength = (USHORT)fullInfo->DataLength + sizeof(WCHAR);
+
+	/* Convert unicode univalue to ansi string. */
+	rval = RtlUnicodeStringToAnsiString(&stringdata, &unidata, TRUE);
+	if (NT_SUCCESS(rval)) {
+	    strcpy(value,stringdata.Buffer);
+	    status = true;
+	    }
+	}
+
+Exit:
+    if (fullInfo) ExFreePool(fullInfo);
+    if (uniKey) _PM_FreeUnicodeString(uniKey);
+    if (uniValue) _PM_FreeUnicodeString(uniValue);
+    return status;
+}
+
+/****************************************************************************
+REMARKS:
+Return the drive letter for the boot drive.
+****************************************************************************/
+char PMAPI PM_getBootDrive(void)
+{
+    char path[256];
+    if (REG_queryString(szNTWindowsKey,szNTSystemRoot,path,sizeof(path)))
+	return 'c';
+    return path[0];
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the VBE/AF driver files.
+****************************************************************************/
+const char * PMAPI PM_getVBEAFPath(void)
+{
+    return "c:\\";
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus driver files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusPath(void)
+{
+    static char path[256];
+
+    if (strlen(_PM_nucleusPath) > 0) {
+	strcpy(path,_PM_nucleusPath);
+	PM_backslash(path);
+	return path;
+	}
+    if (!REG_queryString(szNTWindowsKey,szNTSystemRoot,path,sizeof(path)))
+	strcpy(path,"c:\\winnt");
+    PM_backslash(path);
+    strcat(path,"system32\\nucleus");
+    return path;
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus configuration files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+/****************************************************************************
+REMARKS:
+Return a unique identifier for the machine if possible.
+****************************************************************************/
+const char * PMAPI PM_getUniqueID(void)
+{
+    return PM_getMachineName();
+}
+
+/****************************************************************************
+REMARKS:
+Get the name of the machine on the network.
+****************************************************************************/
+const char * PMAPI PM_getMachineName(void)
+{
+    static char name[256];
+
+    if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name)))
+	return name;
+    if (REG_queryString(szMachineNameKeyNT,szMachineName,name,sizeof(name)))
+	return name;
+    return "Unknown";
+}
+
+/****************************************************************************
+REMARKS:
+Check if a key has been pressed.
+****************************************************************************/
+int PMAPI PM_kbhit(void)
+{
+    /* Not used in NT drivers */
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Wait for and return the next keypress.
+****************************************************************************/
+int PMAPI PM_getch(void)
+{
+    /* Not used in NT drivers */
+    return 0xD;
+}
+
+/****************************************************************************
+REMARKS:
+Open a console for output to the screen, creating the main event handling
+window if necessary.
+****************************************************************************/
+PM_HWND PMAPI PM_openConsole(
+    PM_HWND hwndUser,
+    int device,
+    int xRes,
+    int yRes,
+    int bpp,
+    ibool fullScreen)
+{
+    /* Not used in NT drivers */
+    (void)hwndUser;
+    (void)device;
+    (void)xRes;
+    (void)yRes;
+    (void)bpp;
+    (void)fullScreen;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Find the size of the console state buffer.
+****************************************************************************/
+int PMAPI PM_getConsoleStateSize(void)
+{
+    /* Not used in NT drivers */
+    return 1;
+}
+
+/****************************************************************************
+REMARKS:
+Save the state of the console.
+****************************************************************************/
+void PMAPI PM_saveConsoleState(
+    void *stateBuf,
+    PM_HWND hwndConsole)
+{
+    /* Not used in NT drivers */
+    (void)stateBuf;
+    (void)hwndConsole;
+}
+
+/****************************************************************************
+REMARKS:
+Set the suspend application callback for the fullscreen console.
+****************************************************************************/
+void PMAPI PM_setSuspendAppCallback(
+    PM_saveState_cb saveState)
+{
+    /* Not used in NT drivers */
+    (void)saveState;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the console state.
+****************************************************************************/
+void PMAPI PM_restoreConsoleState(
+    const void *stateBuf,
+    PM_HWND hwndConsole)
+{
+    /* Not used in NT drivers */
+    (void)stateBuf;
+    (void)hwndConsole;
+}
+
+/****************************************************************************
+REMARKS:
+Close the fullscreen console.
+****************************************************************************/
+void PMAPI PM_closeConsole(
+    PM_HWND hwndConsole)
+{
+    /* Not used in NT drivers */
+    (void)hwndConsole;
+}
+
+/****************************************************************************
+REMARKS:
+Set the location of the OS console cursor.
+****************************************************************************/
+void PMAPI PM_setOSCursorLocation(
+    int x,
+    int y)
+{
+    /* Nothing to do for Windows */
+    (void)x;
+    (void)y;
+}
+
+/****************************************************************************
+REMARKS:
+Set the width of the OS console.
+****************************************************************************/
+void PMAPI PM_setOSScreenWidth(
+    int width,
+    int height)
+{
+    /* Nothing to do for Windows */
+    (void)width;
+    (void)height;
+}
+
+/****************************************************************************
+REMARKS:
+Maps a shared memory block into process address space. Does nothing since
+the memory blocks are already globally mapped into all processes.
+****************************************************************************/
+void * PMAPI PM_mapToProcess(
+    void *base,
+    ulong limit)
+{
+    /* Not used anymore */
+    (void)base;
+    (void)limit;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Execute the POST on the secondary BIOS for a controller.
+****************************************************************************/
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS,
+    ulong BIOSLen)
+{
+    /* This may not be possible in NT and should be done by the OS anyway */
+    (void)axVal;
+    (void)BIOSPhysAddr;
+    (void)mappedBIOS;
+    (void)BIOSLen;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to the real mode BIOS data area.
+****************************************************************************/
+void * PMAPI PM_getBIOSPointer(void)
+{
+    /* Note that on NT this probably does not do what we expect! */
+    return PM_mapPhysicalAddr(0x400, 0x1000, true);
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to 0xA0000 physical VGA graphics framebuffer.
+****************************************************************************/
+void * PMAPI PM_getA0000Pointer(void)
+{
+    return PM_mapPhysicalAddr(0xA0000,0xFFFF,false);
+}
+
+/****************************************************************************
+REMARKS:
+Sleep for the specified number of milliseconds.
+****************************************************************************/
+void PMAPI PM_sleep(
+    ulong milliseconds)
+{
+    /* We never use this in NT drivers */
+    (void)milliseconds;
+}
+
+/****************************************************************************
+REMARKS:
+Return the base I/O port for the specified COM port.
+****************************************************************************/
+int PMAPI PM_getCOMPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	case 2: return 0x3E8;
+	case 3: return 0x2E8;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Return the base I/O port for the specified LPT port.
+****************************************************************************/
+int PMAPI PM_getLPTPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Returns available memory. Not possible under Windows.
+****************************************************************************/
+void PMAPI PM_availableMemory(
+    ulong *physical,
+    ulong *total)
+{
+    *physical = *total = 0;
+}
+
+/****************************************************************************
+REMARKS:
+OS specific shared libraries not supported inside a VxD
+****************************************************************************/
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    /* Not used in NT drivers */
+    (void)szDLLName;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+OS specific shared libraries not supported inside a VxD
+****************************************************************************/
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    /* Not used in NT drivers */
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+OS specific shared libraries not supported inside a VxD
+****************************************************************************/
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    /* Not used in NT drivers */
+    (void)hModule;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+void *PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    /* TODO: This function should start a directory enumeration search */
+    /*       given the filename (with wildcards). The data should be */
+    /*       converted and returned in the findData standard form. */
+    (void)filename;
+    (void)findData;
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    void *handle,
+    PM_findData *findData)
+{
+    /* TODO: This function should find the next file in directory enumeration */
+    /*       search given the search criteria defined in the call to */
+    /*       PM_findFirstFile. The data should be converted and returned */
+    /*       in the findData standard form. */
+    (void)handle;
+    (void)findData;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    void *handle)
+{
+    /* TODO: This function should close the find process. This may do */
+    /*       nothing for some OS'es. */
+    (void)handle;
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    /* Not supported in NT drivers */
+    (void)drive;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    /* Not supported in NT drivers */
+    (void)drive;
+    (void)dir;
+    (void)len;
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+RETURNS:
+Error code describing the result.
+
+REMARKS:
+Function to enable write combining for the specified region of memory.
+****************************************************************************/
+int PMAPI PM_enableWriteCombine(
+    ulong base,
+    ulong size,
+    uint type)
+{
+    return MTRR_enableWriteCombine(base,size,type);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+    NTSTATUS                status;
+    ACCESS_MASK             DesiredAccess = GENERIC_READ | GENERIC_WRITE;
+    OBJECT_ATTRIBUTES       ObjectAttributes;
+    ULONG                   ShareAccess = FILE_SHARE_READ;
+    ULONG                   CreateDisposition = FILE_OPEN;
+    HANDLE                  FileHandle = NULL;
+    UNICODE_STRING          *uniFile = NULL;
+    IO_STATUS_BLOCK         IoStatusBlock;
+    FILE_BASIC_INFORMATION  FileBasic;
+    char                    kernelFilename[PM_MAX_PATH+5];
+    ULONG                   FileAttributes = 0;
+
+    /* Convert file attribute flags */
+    if (attrib & PM_FILE_READONLY)
+	FileAttributes |= FILE_ATTRIBUTE_READONLY;
+    if (attrib & PM_FILE_ARCHIVE)
+	FileAttributes |= FILE_ATTRIBUTE_ARCHIVE;
+    if (attrib & PM_FILE_HIDDEN)
+	FileAttributes |= FILE_ATTRIBUTE_HIDDEN;
+    if (attrib & PM_FILE_SYSTEM)
+	FileAttributes |= FILE_ATTRIBUTE_SYSTEM;
+
+    /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */
+    strcpy(kernelFilename, "\\??\\");
+    strcat(kernelFilename, filename);
+
+    /* Convert filename string to ansi string */
+    if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL)
+	goto Exit;
+
+    /* Must open a file to query it's attributes */
+    InitializeObjectAttributes (&ObjectAttributes,
+				uniFile,
+				OBJ_CASE_INSENSITIVE,
+				NULL,
+				NULL );
+    status = ZwCreateFile( &FileHandle,
+			    DesiredAccess | SYNCHRONIZE,
+			    &ObjectAttributes,
+			    &IoStatusBlock,
+			    NULL,                  /*AllocationSize  OPTIONAL, */
+			    FILE_ATTRIBUTE_NORMAL,
+			    ShareAccess,
+			    CreateDisposition,
+			    FILE_RANDOM_ACCESS,        /*CreateOptions, */
+			    NULL,                  /*EaBuffer  OPTIONAL, */
+			    0                      /*EaLength (required if EaBuffer) */
+			    );
+    if (!NT_SUCCESS (status))
+	goto Exit;
+
+    /* Query timestamps */
+    status = ZwQueryInformationFile(FileHandle,
+				    &IoStatusBlock,
+				    &FileBasic,
+				    sizeof(FILE_BASIC_INFORMATION),
+				    FileBasicInformation
+				    );
+    if (!NT_SUCCESS (status))
+	goto Exit;
+
+    /* Change the four bits we change */
+    FileBasic.FileAttributes &= ~(FILE_ATTRIBUTE_READONLY | FILE_ATTRIBUTE_ARCHIVE
+				  | FILE_ATTRIBUTE_HIDDEN | FILE_ATTRIBUTE_SYSTEM);
+    FileBasic.FileAttributes |= FileAttributes;
+
+    /* Set timestamps */
+    ZwSetInformationFile(   FileHandle,
+			    &IoStatusBlock,
+			    &FileBasic,
+			    sizeof(FILE_BASIC_INFORMATION),
+			    FileBasicInformation
+			    );
+
+Exit:
+    if (FileHandle) ZwClose(FileHandle);
+    if (uniFile) _PM_FreeUnicodeString(uniFile);
+    return;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file attributes for a specific file.
+****************************************************************************/
+uint PMAPI PM_getFileAttr(
+    const char *filename)
+{
+    NTSTATUS                status;
+    ACCESS_MASK             DesiredAccess = GENERIC_READ | GENERIC_WRITE;
+    OBJECT_ATTRIBUTES       ObjectAttributes;
+    ULONG                   ShareAccess = FILE_SHARE_READ;
+    ULONG                   CreateDisposition = FILE_OPEN;
+    HANDLE                  FileHandle = NULL;
+    UNICODE_STRING          *uniFile = NULL;
+    IO_STATUS_BLOCK         IoStatusBlock;
+    FILE_BASIC_INFORMATION  FileBasic;
+    char                    kernelFilename[PM_MAX_PATH+5];
+    ULONG                   FileAttributes = 0;
+    uint                    retval = 0;
+
+    /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */
+    strcpy(kernelFilename, "\\??\\");
+    strcat(kernelFilename, filename);
+
+    /* Convert filename string to ansi string */
+    if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL)
+	goto Exit;
+
+    /* Must open a file to query it's attributes */
+    InitializeObjectAttributes (&ObjectAttributes,
+				uniFile,
+				OBJ_CASE_INSENSITIVE,
+				NULL,
+				NULL );
+    status = ZwCreateFile( &FileHandle,
+			   DesiredAccess | SYNCHRONIZE,
+			   &ObjectAttributes,
+			   &IoStatusBlock,
+			   NULL,                  /*AllocationSize  OPTIONAL, */
+			   FILE_ATTRIBUTE_NORMAL,
+			   ShareAccess,
+			   CreateDisposition,
+			   FILE_RANDOM_ACCESS,        /*CreateOptions, */
+			   NULL,                  /*EaBuffer  OPTIONAL, */
+			   0                      /*EaLength (required if EaBuffer) */
+			   );
+    if (!NT_SUCCESS (status))
+	goto Exit;
+
+    /* Query timestamps */
+    status = ZwQueryInformationFile(FileHandle,
+				    &IoStatusBlock,
+				    &FileBasic,
+				    sizeof(FILE_BASIC_INFORMATION),
+				    FileBasicInformation
+				    );
+    if (!NT_SUCCESS (status))
+	goto Exit;
+
+    /* Translate the file attributes */
+    if (FileBasic.FileAttributes & FILE_ATTRIBUTE_READONLY)
+	retval |= PM_FILE_READONLY;
+    if (FileBasic.FileAttributes & FILE_ATTRIBUTE_ARCHIVE)
+	retval |= PM_FILE_ARCHIVE;
+    if (FileBasic.FileAttributes & FILE_ATTRIBUTE_HIDDEN)
+	retval |= PM_FILE_HIDDEN;
+    if (FileBasic.FileAttributes & FILE_ATTRIBUTE_SYSTEM)
+	retval |= PM_FILE_SYSTEM;
+
+Exit:
+    if (FileHandle) ZwClose(FileHandle);
+    if (uniFile) _PM_FreeUnicodeString(uniFile);
+    return retval;
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+    /* Not supported in NT drivers */
+    (void)filename;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+    /* Not supported in NT drivers */
+    (void)filename;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_getFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* Not supported in NT drivers */
+    (void)filename;
+    (void)gmTime;
+    (void)time;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to set the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_setFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* Not supported in NT drivers */
+    (void)filename;
+    (void)gmTime;
+    (void)time;
+    return false;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c
new file mode 100755
index 0000000..658f1c8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c
@@ -0,0 +1,330 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows NT driver
+*
+* Description:  C library compatible I/O functions for use within a Windows
+*               NT driver.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "oshdr.h"
+
+/*------------------------ Main Code Implementation -----------------------*/
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fopen function.
+****************************************************************************/
+FILE * fopen(
+    const char *filename,
+    const char *mode)
+{
+    ACCESS_MASK                 DesiredAccess;      /* for ZwCreateFile... */
+    OBJECT_ATTRIBUTES           ObjectAttributes;
+    ULONG                       ShareAccess;
+    ULONG                       CreateDisposition;
+    NTSTATUS                    status;
+    HANDLE                      FileHandle;
+    UNICODE_STRING              *uniFile = NULL;
+    PWCHAR                      bufFile = NULL;
+    IO_STATUS_BLOCK             IoStatusBlock;
+    FILE_STANDARD_INFORMATION   FileInformation;
+    FILE_POSITION_INFORMATION   FilePosition;
+    char                        kernelFilename[PM_MAX_PATH+5];
+    FILE                        *f;
+
+    /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */
+    strcpy(kernelFilename, "\\??\\");
+    strcat(kernelFilename, filename);
+    if ((f = PM_malloc(sizeof(FILE))) == NULL)
+	goto Error;
+    f->offset = 0;
+    f->text = (mode[1] == 't' || mode[2] == 't');
+    f->writemode = (mode[0] == 'w') || (mode[0] == 'a');
+    if (mode[0] == 'r') {
+	/* omode = OPEN_ACCESS_READONLY | OPEN_SHARE_COMPATIBLE; */
+	/* action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_FAIL; */
+	DesiredAccess = GENERIC_READ;
+	ShareAccess = FILE_SHARE_READ | FILE_SHARE_WRITE;
+	CreateDisposition = FILE_OPEN;
+	}
+    else if (mode[0] == 'w') {
+	/* omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_COMPATIBLE; */
+	/* action = ACTION_IFEXISTS_TRUNCATE | ACTION_IFNOTEXISTS_CREATE; */
+	DesiredAccess = GENERIC_WRITE;
+	ShareAccess = FILE_SHARE_READ | FILE_SHARE_WRITE;
+	CreateDisposition = FILE_SUPERSEDE;
+	}
+    else {
+	/* omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_COMPATIBLE; */
+	/* action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_CREATE; */
+	DesiredAccess = GENERIC_READ | GENERIC_WRITE;
+	ShareAccess = FILE_SHARE_READ;
+	CreateDisposition = FILE_OPEN_IF;
+	}
+
+    /* Convert filename string to ansi string and then to UniCode string */
+    if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL)
+	return NULL;
+
+    /* Create the file */
+    InitializeObjectAttributes (&ObjectAttributes,
+				uniFile,
+				OBJ_CASE_INSENSITIVE,
+				NULL,
+				NULL);
+    status = ZwCreateFile( &FileHandle,
+			    DesiredAccess | SYNCHRONIZE,
+			    &ObjectAttributes,
+			    &IoStatusBlock,
+			    NULL,                   /* AllocationSize  OPTIONAL, */
+			    FILE_ATTRIBUTE_NORMAL,
+			    ShareAccess,
+			    CreateDisposition,
+			    FILE_RANDOM_ACCESS,     /* CreateOptions, */
+			    NULL,                   /* EaBuffer  OPTIONAL, */
+			    0                       /* EaLength (required if EaBuffer) */
+			    );
+    if (!NT_SUCCESS (status))
+	goto Error;
+    f->handle = (int)FileHandle;
+
+    /* Determine size of the file */
+    status = ZwQueryInformationFile(  FileHandle,
+				      &IoStatusBlock,
+				      &FileInformation,
+				      sizeof(FILE_STANDARD_INFORMATION),
+				      FileStandardInformation
+				      );
+    if (!NT_SUCCESS (status))
+	goto Error;
+    f->filesize = FileInformation.EndOfFile.LowPart;
+
+    /* Move to the end of the file if we are appending */
+    if (mode[0] == 'a') {
+	FilePosition.CurrentByteOffset.HighPart = 0;
+	FilePosition.CurrentByteOffset.LowPart = f->filesize;
+	status = ZwSetInformationFile(  FileHandle,
+					&IoStatusBlock,
+					&FilePosition,
+					sizeof(FILE_POSITION_INFORMATION),
+					FilePositionInformation
+					);
+	if (!NT_SUCCESS (status))
+	    goto Error;
+	}
+    return f;
+
+Error:
+    if (f) PM_free(f);
+    if (uniFile) _PM_FreeUnicodeString(uniFile);
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fread function.
+****************************************************************************/
+size_t fread(
+    void *ptr,
+    size_t size,
+    size_t n,
+    FILE *f)
+{
+    NTSTATUS        status;
+    IO_STATUS_BLOCK IoStatusBlock;
+    LARGE_INTEGER   ByteOffset;
+
+    /* Read any extra bytes from the file */
+    ByteOffset.HighPart = 0;
+    ByteOffset.LowPart = f->offset;
+    status = ZwReadFile( (HANDLE)f->handle,
+			 NULL,              /*IN HANDLE  Event  OPTIONAL, */
+			 NULL,              /*  IN PIO_APC_ROUTINE  ApcRoutine  OPTIONAL, */
+			 NULL,              /*  IN PVOID  ApcContext  OPTIONAL, */
+			 &IoStatusBlock,
+			 ptr,               /*  OUT PVOID  Buffer, */
+			 size * n,          /*IN ULONG  Length, */
+			 &ByteOffset,       /*OPTIONAL, */
+			 NULL               /*IN PULONG  Key  OPTIONAL */
+			 );
+    if (!NT_SUCCESS (status))
+	return 0;
+    f->offset += IoStatusBlock.Information;
+    return IoStatusBlock.Information / size;
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fwrite function.
+****************************************************************************/
+size_t fwrite(
+    const void *ptr,
+    size_t size,
+    size_t n,
+    FILE *f)
+{
+    NTSTATUS        status;
+    IO_STATUS_BLOCK IoStatusBlock;
+    LARGE_INTEGER   ByteOffset;
+
+    if (!f->writemode)
+	return 0;
+    ByteOffset.HighPart = 0;
+    ByteOffset.LowPart = f->offset;
+    status = ZwWriteFile( (HANDLE)f->handle,
+			  NULL,             /*IN HANDLE  Event  OPTIONAL, */
+			  NULL,             /*  IN PIO_APC_ROUTINE  ApcRoutine  OPTIONAL, */
+			  NULL,             /*  IN PVOID  ApcContext  OPTIONAL, */
+			  &IoStatusBlock,
+			  (void*)ptr,       /*  OUT PVOID  Buffer, */
+			  size * n,         /*IN ULONG  Length, */
+			  &ByteOffset,      /*OPTIONAL, */
+			  NULL              /*IN PULONG  Key  OPTIONAL */
+			  );
+    if (!NT_SUCCESS (status))
+	return 0;
+    f->offset += IoStatusBlock.Information;
+    if (f->offset > f->filesize)
+	f->filesize = f->offset;
+    return IoStatusBlock.Information / size;
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fflush function.
+****************************************************************************/
+int fflush(
+    FILE *f)
+{
+    /* Nothing to do here as we are not doing buffered I/O */
+    (void)f;
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fseek function.
+****************************************************************************/
+int fseek(
+    FILE *f,
+    long int offset,
+    int whence)
+{
+    NTSTATUS                    status;
+    FILE_POSITION_INFORMATION   FilePosition;
+    IO_STATUS_BLOCK             IoStatusBlock;
+
+    if (whence == 0)
+	f->offset = offset;
+    else if (whence == 1)
+	f->offset += offset;
+    else if (whence == 2)
+	f->offset = f->filesize + offset;
+    FilePosition.CurrentByteOffset.HighPart = 0;
+    FilePosition.CurrentByteOffset.LowPart = f->offset;
+    status = ZwSetInformationFile( (HANDLE)f->handle,
+				   &IoStatusBlock,
+				   &FilePosition,
+				   sizeof(FILE_POSITION_INFORMATION),
+				   FilePositionInformation
+				   );
+    if (!NT_SUCCESS (status))
+	return -1;
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C ftell function.
+****************************************************************************/
+long ftell(
+    FILE *f)
+{
+    return f->offset;
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C feof function.
+****************************************************************************/
+int feof(
+    FILE *f)
+{
+    return (f->offset == f->filesize);
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fgets function.
+****************************************************************************/
+char *fgets(
+    char *s,
+    int n,
+    FILE *f)
+{
+    int     len;
+    char    *cs;
+
+    /* Read the entire buffer into memory (our functions are unbuffered!) */
+    if ((len = fread(s,1,n,f)) == 0)
+	return NULL;
+
+    /* Search for '\n' or end of string */
+    if (n > len)
+	n = len;
+    cs = s;
+    while (--n > 0) {
+	if (*cs == '\n')
+	    break;
+	cs++;
+	}
+    *cs = '\0';
+    return s;
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fputs function.
+****************************************************************************/
+int fputs(
+    const char *s,
+    FILE *f)
+{
+    return fwrite(s,1,strlen(s),f);
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fclose function.
+****************************************************************************/
+int fclose(
+    FILE *f)
+{
+    ZwClose((HANDLE)f->handle);
+    PM_free(f);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c
new file mode 100755
index 0000000..bbf0cbf
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c
@@ -0,0 +1,139 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows NT driver
+*
+* Description:  C library compatible stdlib.h functions for use within a
+*               Windows NT driver.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "oshdr.h"
+
+/*------------------------ Main Code Implementation -----------------------*/
+
+/****************************************************************************
+REMARKS:
+PM_malloc override function for Nucleus drivers loaded in NT drivers's.
+****************************************************************************/
+void * malloc(
+    size_t size)
+{
+    return PM_mallocShared(size);
+}
+
+/****************************************************************************
+REMARKS:
+calloc library function for Nucleus drivers loaded in NT drivers's.
+****************************************************************************/
+void * calloc(
+    size_t nelem,
+    size_t size)
+{
+    void *p = PM_mallocShared(nelem * size);
+    if (p)
+	memset(p,0,nelem * size);
+    return p;
+}
+
+/****************************************************************************
+REMARKS:
+PM_realloc override function for Nucleus drivers loaded in VxD's.
+****************************************************************************/
+void * realloc(
+    void *ptr,
+    size_t size)
+{
+    void *p = PM_mallocShared(size);
+    if (p) {
+	memcpy(p,ptr,size);
+	PM_freeShared(ptr);
+	}
+    return p;
+}
+
+/****************************************************************************
+REMARKS:
+PM_free override function for Nucleus drivers loaded in VxD's.
+****************************************************************************/
+void free(
+    void *p)
+{
+    PM_freeShared(p);
+}
+
+/****************************************************************************
+PARAMETERS:
+cstr    - C style ANSI string to convert
+
+RETURNS:
+Pointer to the UniCode string structure or NULL on failure to allocate memory
+
+REMARKS:
+Converts a C style string to a UniCode string structure that can be passed
+directly to NT kernel functions.
+****************************************************************************/
+UNICODE_STRING *_PM_CStringToUnicodeString(
+    const char *cstr)
+{
+    int             length;
+    ANSI_STRING     ansiStr;
+    UNICODE_STRING  *uniStr;
+
+    /* Allocate memory for the string structure */
+    if ((uniStr = ExAllocatePool(NonPagedPool, sizeof(UNICODE_STRING))) == NULL)
+	return NULL;
+
+    /* Allocate memory for the wide string itself */
+    length = (strlen(cstr) * sizeof(WCHAR)) + sizeof(WCHAR);
+    if ((uniStr->Buffer = ExAllocatePool(NonPagedPool, length)) == NULL) {
+	ExFreePool(uniStr);
+	return NULL;
+	}
+    RtlZeroMemory(uniStr->Buffer, length);
+    uniStr->Length = 0;
+    uniStr->MaximumLength = (USHORT)length;
+
+    /* Convert filename string to ansi string and then to UniCode string */
+    RtlInitAnsiString(&ansiStr, cstr);
+    RtlAnsiStringToUnicodeString(uniStr, &ansiStr, FALSE);
+    return uniStr;
+}
+
+/****************************************************************************
+PARAMETERS:
+uniStr  - UniCode string structure to free
+
+REMARKS:
+Frees a string allocated by the above _PM_CStringToUnicodeString function.
+****************************************************************************/
+void _PM_FreeUnicodeString(
+    UNICODE_STRING *uniStr)
+{
+    if (uniStr) {
+	ExFreePool(uniStr->Buffer);
+	ExFreePool(uniStr);
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c
new file mode 100755
index 0000000..901ce1c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c
@@ -0,0 +1,45 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c
new file mode 100755
index 0000000..f4c4bd4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c
@@ -0,0 +1,123 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows VxD
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+/*---------------------------- Global variables ---------------------------*/
+
+static CPU_largeInteger countFreq;
+static ulong            start,finish;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+static void __ZTimerInit(void)
+{
+    KeQueryPerformanceCounter((LARGE_INTEGER*)&countFreq);
+}
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+static void __LZTimerOn(
+    LZTimerObject *tm)
+{
+    LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL);
+    tm->start.low = lt.LowPart;
+    tm->start.high = lt.HighPart;
+}
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+static ulong __LZTimerLap(
+    LZTimerObject *tm)
+{
+    LARGE_INTEGER       tmLap = KeQueryPerformanceCounter(NULL);
+    CPU_largeInteger    tmCount;
+
+    _CPU_diffTime64(&tm->start,(CPU_largeInteger*)&tmLap,&tmCount);
+    return _CPU_calcMicroSec(&tmCount,countFreq.low);
+}
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+static void __LZTimerOff(
+    LZTimerObject *tm)
+{
+    LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL);
+    tm->end.low = lt.LowPart;
+    tm->end.high = lt.HighPart;
+}
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+static ulong __LZTimerCount(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger    tmCount;
+
+    _CPU_diffTime64(&tm->start,&tm->end,&tmCount);
+    return _CPU_calcMicroSec(&tmCount,countFreq.low);
+}
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION     1
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer value from the BIOS timer tick.
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{
+    LARGE_INTEGER count;
+    KeQuerySystemTime(&count);
+    return (ulong)(*((_int64*)&count) / 10);
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm b/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm
new file mode 100755
index 0000000..761f0f4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm
@@ -0,0 +1,180 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: OS/2 32 bit protected mode
+;*
+;* Description: Low level assembly support for the PM library specific
+;*              to OS/2
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"               ; Memory model macros
+
+header      _pmos2                  ; Set up memory model
+
+begdataseg  _pmos2
+
+        cglobal _PM_ioentry
+        cglobal _PM_gdt
+_PM_ioentry     dd  0               ; Offset to call gate
+_PM_gdt         dw  0               ; Selector to call gate
+
+enddataseg  _pmos2
+
+begcodeseg  _pmos2                  ; Start of code segment
+
+;----------------------------------------------------------------------------
+; int PM_setIOPL(int iopl)
+;----------------------------------------------------------------------------
+; Change the IOPL level for the 32-bit task. Returns the previous level
+; so it can be restored for the task correctly.
+;----------------------------------------------------------------------------
+cprocstart  PM_setIOPL
+
+        ARG     iopl:UINT
+
+        enter_c
+        pushfd                      ; Save the old EFLAGS for later
+        mov     ecx,[iopl]          ; ECX := IOPL level
+        xor     ebx,ebx             ; Change IOPL level function code (0)
+ifdef   USE_NASM
+        call far dword [_PM_ioentry]
+else
+        call    [FWORD _PM_ioentry]
+endif
+        pop     eax
+        and     eax,0011000000000000b
+        shr     eax,12
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _PM_setGDTSelLimit(ushort selector, ulong limit);
+;----------------------------------------------------------------------------
+; Change the GDT selector limit to given value. Used to change selector
+; limits to address the entire system address space.
+;----------------------------------------------------------------------------
+cprocstart  _PM_setGDTSelLimit
+
+        ARG     selector:USHORT, limit:UINT
+        
+        enter_c
+        sub     esp,20              ; Make room for selector data on stack
+        mov     ecx,esp             ; ECX := selector data structure
+        mov     bx,[selector]       ; Fill out the data structure
+        and     bx,0FFF8h           ; Kick out the LDT/GDT and DPL bits     
+        mov     [WORD ecx],bx
+        mov     ebx,[limit]
+        mov     [DWORD ecx+4],ebx
+        mov     ebx,5               ; Set GDT selector limit function code      
+ifdef   USE_NASM
+        call far dword [_PM_ioentry]
+else
+        call    [FWORD _PM_ioentry]
+endif
+        add     esp,20
+        leave_c
+        ret
+
+cprocend    
+
+;----------------------------------------------------------------------------
+; uchar _MTRR_getCx86(uchar reg);
+;----------------------------------------------------------------------------
+; Read a Cyrix CPU indexed register
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_getCx86
+
+        ARG     reg:UCHAR
+
+        enter_c
+        mov     al,[reg]
+        out     22h,al
+        in      al,23h
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uchar _MTRR_setCx86(uchar reg,uchar val);
+;----------------------------------------------------------------------------
+; Write a Cyrix CPU indexed register
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_setCx86
+
+        ARG     reg:UCHAR, val:UCHAR
+
+        enter_c
+        mov     al,[reg]
+        out     22h,al
+        mov     al,[val]
+        out     23h,al
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _MTRR_disableInt(void);
+;----------------------------------------------------------------------------
+; Return processor interrupt status and disable interrupts.
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_disableInt
+
+; Do nothing!
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _MTRR_restoreInt(ulong ps);
+;----------------------------------------------------------------------------
+; Restore processor interrupt status.
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_restoreInt
+
+; Do nothing!
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void DebugInt(void)
+;----------------------------------------------------------------------------
+cprocstart  DebugInt
+
+        int     3
+        ret
+
+cprocend
+
+endcodeseg  _pmos2
+
+        END                         ; End of module
+        
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c
new file mode 100755
index 0000000..7de400d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c
@@ -0,0 +1,66 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  OS/2
+*
+* Description:  OS/2 specific code for the CPU detection module.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+TODO: This should be implemented for OS/2!
+****************************************************************************/
+#define SetMaxThreadPriority()  0
+
+/****************************************************************************
+REMARKS:
+TODO: This should be implemented for OS/2!
+****************************************************************************/
+#define RestoreThreadPriority(i)
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    freq->low = 100000;
+    freq->high = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)                                                       \
+{                                                                           \
+    ULONG   count;                                                          \
+    DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) );   \
+    (t)->low = count * 100;                                                 \
+    (t)->high = 0;                                                          \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj b/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj
new file mode 100755
index 0000000..5533346
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/event.c b/board/MAI/bios_emulator/scitech/src/pm/os2/event.c
new file mode 100755
index 0000000..91cc19b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/event.c
@@ -0,0 +1,565 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  IBM PC (OS/2)
+*
+* Description:  OS/2 implementation for the SciTech cross platform
+*               event library.
+*
+****************************************************************************/
+
+/*---------------------------- Global Variables ---------------------------*/
+
+/* Define generous keyboard monitor circular buffer size to minimize
+ * the danger of losing keystrokes
+ */
+#define KEYBUFSIZE  (EVENTQSIZE + 10)
+
+static int      oldMouseState;          /* Old mouse state               */
+static ulong    oldKeyMessage;          /* Old keyboard state            */
+static ushort   keyUpMsg[256] = {0};    /* Table of key up messages      */
+static int      rangeX,rangeY;          /* Range of mouse coordinates    */
+HMOU            _EVT_hMouse;            /* Handle to the mouse driver    */
+HMONITOR        _EVT_hKbdMon;           /* Handle to the keyboard driver */
+TID             kbdMonTID = 0;          /* Keyboard monitor thread ID    */
+HEV             hevStart;               /* Start event semaphore handle  */
+BOOL            bMonRunning;            /* Flag set if monitor thread OK */
+HMTX            hmtxKeyBuf;             /* Mutex protecting key buffer   */
+KEYPACKET       keyMonPkts[KEYBUFSIZE]; /* Array of monitor key packets  */
+int             kpHead = 0;             /* Key packet buffer head        */
+int             kpTail = 0;             /* Key packet buffer tail        */
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* These are not used under OS/2 */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flags)
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Scan code to test
+
+REMARKS:
+This macro determines if a specified key is currently down at the
+time that the call is made.
+****************************************************************************/
+#define _EVT_isKeyDown(scanCode)    (keyUpMsg[scanCode] != 0)
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{
+    ULONG   count;
+    DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) );
+    return count;
+}
+
+/****************************************************************************
+REMARKS:
+Converts a mickey movement value to a pixel adjustment value.
+****************************************************************************/
+static int MickeyToPixel(
+    int mickey)
+{
+    /* TODO: We can add some code in here to handle 'acceleration' for */
+    /*       the mouse cursor. For now just use the mickeys. */
+    return mickey;
+}
+
+/* Some useful defines any typedefs used in the keyboard handling */
+#define KEY_RELEASE             0x40
+
+/****************************************************************************
+REMARKS:
+Pumps all messages in the message queue from OS/2 into our event queue.
+****************************************************************************/
+static void _EVT_pumpMessages(void)
+{
+    KBDINFO         keyInfo;        /* Must not cross a 64K boundary */
+    KBDKEYINFO      key;            /* Must not cross a 64K boundary */
+    MOUQUEINFO      mqueue;         /* Must not cross a 64K boundary */
+    MOUEVENTINFO    mouse;          /* Must not cross a 64K boundary */
+    ushort          mWait;          /* Must not cross a 64K boundary */
+    KEYPACKET       kp;             /* Must not cross a 64K boundary */
+    event_t         evt;
+    int             scan;
+    ibool           noInput = TRUE; /* Flag to determine if any input was available */
+
+    /* First of all, check if we should do any session switch work */
+    __PM_checkConsoleSwitch();
+
+    /* Pump all keyboard messages from our circular buffer */
+    for (;;) {
+	/* Check that the monitor thread is still running */
+	if (!bMonRunning)
+	    PM_fatalError("Keyboard monitor thread died!");
+
+	/* Protect keypacket buffer with mutex */
+	DosRequestMutexSem(hmtxKeyBuf, SEM_INDEFINITE_WAIT);
+	if (kpHead == kpTail) {
+	    DosReleaseMutexSem(hmtxKeyBuf);
+	    break;
+	    }
+
+	noInput = FALSE;
+
+	/* Read packet from circular buffer and remove it */
+	memcpy(&kp, &keyMonPkts[kpTail], sizeof(KEYPACKET));
+	if (++kpTail == KEYBUFSIZE)
+	    kpTail = 0;
+	DosReleaseMutexSem(hmtxKeyBuf);
+
+	/* Compensate for the 0xE0 character */
+	if (kp.XlatedScan && kp.XlatedChar == 0xE0)
+	    kp.XlatedChar = 0;
+
+	/* Determine type of keyboard event */
+	memset(&evt,0,sizeof(evt));
+	if (kp.KbdDDFlagWord & KEY_RELEASE)
+	    evt.what = EVT_KEYUP;
+	else
+	    evt.what = EVT_KEYDOWN;
+
+	/* Convert keyboard codes */
+	scan = kp.MonFlagWord >> 8;
+	if (evt.what == EVT_KEYUP) {
+	    /* Get message for keyup code from table of cached down values */
+	    evt.message = keyUpMsg[scan];
+	    keyUpMsg[scan] = 0;
+	    oldKeyMessage = -1;
+	    }
+	else {
+	    evt.message = ((ulong)scan << 8) | kp.XlatedChar;
+	    if (evt.message == keyUpMsg[scan]) {
+		evt.what = EVT_KEYREPEAT;
+		evt.message |= 0x10000;
+		}
+	    oldKeyMessage = evt.message & 0x0FFFF;
+	    keyUpMsg[scan] = (ushort)evt.message;
+	    }
+
+	 /* Convert shift state modifiers */
+	 if (kp.u.ShiftState & 0x0001)
+	     evt.modifiers |= EVT_RIGHTSHIFT;
+	 if (kp.u.ShiftState & 0x0002)
+	     evt.modifiers |= EVT_LEFTSHIFT;
+	 if (kp.u.ShiftState & 0x0100)
+	     evt.modifiers |= EVT_LEFTCTRL;
+	 if (kp.u.ShiftState & 0x0200)
+	     evt.modifiers |= EVT_LEFTALT;
+	 if (kp.u.ShiftState & 0x0400)
+	     evt.modifiers |= EVT_RIGHTCTRL;
+	 if (kp.u.ShiftState & 0x0800)
+	     evt.modifiers |= EVT_RIGHTALT;
+	 EVT.oldMove = -1;
+
+	 /* Add time stamp and add the event to the queue */
+	 evt.when = key.time;
+	 if (EVT.count < EVENTQSIZE)
+	     addEvent(&evt);
+	 }
+
+    /* Don't just flush because that terminally confuses the monitor */
+    do {
+	KbdCharIn(&key, IO_NOWAIT, 0);
+	} while (key.fbStatus & KBDTRF_FINAL_CHAR_IN);
+
+    /* Pump all mouse messages */
+    KbdGetStatus(&keyInfo,0);
+    /* Check return code - mouse may not be operational!! */
+    if (MouGetNumQueEl(&mqueue,_EVT_hMouse) == NO_ERROR) {
+	while (mqueue.cEvents) {
+	    while (mqueue.cEvents--) {
+		memset(&evt,0,sizeof(evt));
+		mWait = MOU_NOWAIT;
+		MouReadEventQue(&mouse,&mWait,_EVT_hMouse);
+
+		/* Update the mouse position. We get the mouse coordinates
+		 * in mickeys so we have to translate these into pixels and
+		 * move our mouse position. If we don't do this, OS/2 gives
+		 * us the coordinates in character positions since it still
+		 * thinks we are in text mode!
+		 */
+		EVT.mx += MickeyToPixel(mouse.col);
+		EVT.my += MickeyToPixel(mouse.row);
+		if (EVT.mx < 0) EVT.mx = 0;
+		if (EVT.my < 0) EVT.my = 0;
+		if (EVT.mx > rangeX)    EVT.mx = rangeX;
+		if (EVT.my > rangeY)    EVT.my = rangeY;
+		evt.where_x = EVT.mx;
+		evt.where_y = EVT.my;
+		evt.relative_x = mouse.col;
+		evt.relative_y = mouse.row;
+		evt.when = key.time;
+		if (mouse.fs & (MOUSE_BN1_DOWN | MOUSE_MOTION_WITH_BN1_DOWN))
+		    evt.modifiers |= EVT_LEFTBUT;
+		if (mouse.fs & (MOUSE_BN2_DOWN | MOUSE_MOTION_WITH_BN2_DOWN))
+		    evt.modifiers |= EVT_RIGHTBUT;
+		if (mouse.fs & (MOUSE_BN3_DOWN | MOUSE_MOTION_WITH_BN3_DOWN))
+		    evt.modifiers |= EVT_MIDDLEBUT;
+		if (keyInfo.fsState & 0x0001)
+		    evt.modifiers |= EVT_RIGHTSHIFT;
+		if (keyInfo.fsState & 0x0002)
+		    evt.modifiers |= EVT_LEFTSHIFT;
+		if (keyInfo.fsState & 0x0100)
+		    evt.modifiers |= EVT_LEFTCTRL;
+		if (keyInfo.fsState & 0x0200)
+		    evt.modifiers |= EVT_LEFTALT;
+		if (keyInfo.fsState & 0x0400)
+		    evt.modifiers |= EVT_RIGHTCTRL;
+		if (keyInfo.fsState & 0x0800)
+		    evt.modifiers |= EVT_RIGHTALT;
+
+		/* Check for left mouse click events */
+		/* 0x06 == (MOUSE_BN1_DOWN | MOUSE_MOTION_WITH_BN1_DOWN) */
+		if (((mouse.fs & 0x0006) && !(oldMouseState & 0x0006))
+			|| (!(mouse.fs & 0x0006) && (oldMouseState & 0x0006))) {
+		    if (mouse.fs & 0x0006)
+			evt.what = EVT_MOUSEDOWN;
+		    else
+			evt.what = EVT_MOUSEUP;
+		    evt.message = EVT_LEFTBMASK;
+		    EVT.oldMove = -1;
+		    if (EVT.count < EVENTQSIZE)
+			addEvent(&evt);
+		    }
+
+		/* Check for right mouse click events */
+		/* 0x0018 == (MOUSE_BN2_DOWN | MOUSE_MOTION_WITH_BN2_DOWN) */
+		if (((mouse.fs & 0x0018) && !(oldMouseState & 0x0018))
+			|| (!(mouse.fs & 0x0018) && (oldMouseState & 0x0018))) {
+		    if (mouse.fs & 0x0018)
+			evt.what = EVT_MOUSEDOWN;
+		    else
+			evt.what = EVT_MOUSEUP;
+		    evt.message = EVT_RIGHTBMASK;
+		    EVT.oldMove = -1;
+		    if (EVT.count < EVENTQSIZE)
+			addEvent(&evt);
+		    }
+
+		/* Check for middle mouse click events */
+		/* 0x0060 == (MOUSE_BN3_DOWN | MOUSE_MOTION_WITH_BN3_DOWN) */
+		if (((mouse.fs & 0x0060) && !(oldMouseState & 0x0060))
+			|| (!(mouse.fs & 0x0060) && (oldMouseState & 0x0060))) {
+		    if (mouse.fs & 0x0060)
+			evt.what = EVT_MOUSEDOWN;
+		    else
+			evt.what = EVT_MOUSEUP;
+		    evt.message = EVT_MIDDLEBMASK;
+		    EVT.oldMove = -1;
+		    if (EVT.count < EVENTQSIZE)
+			addEvent(&evt);
+		    }
+
+		/* Check for mouse movement event */
+		if (mouse.fs & 0x002B) {
+		    evt.what = EVT_MOUSEMOVE;
+		    if (EVT.oldMove != -1) {
+			EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one  */
+			EVT.evtq[EVT.oldMove].where_y = evt.where_y;
+			}
+		    else {
+			EVT.oldMove = EVT.freeHead; /* Save id of this move event   */
+			if (EVT.count < EVENTQSIZE)
+			    addEvent(&evt);
+			}
+		    }
+
+		/* Save current mouse state */
+		oldMouseState = mouse.fs;
+		}
+	    MouGetNumQueEl(&mqueue,_EVT_hMouse);
+	    }
+	    noInput = FALSE;
+	}
+
+    /* If there was no input available, give up the current timeslice
+     * Note: DosSleep(0) will effectively do nothing if no other thread is ready. Hence
+     * DosSleep(0) will still use 100% CPU _but_ should not interfere with other programs.
+     */
+    if (noInput)
+	DosSleep(0);
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Keyboard monitor thread. Needed to catch both keyup and keydown events.
+****************************************************************************/
+static void _kbdMonThread(
+    void *params)
+{
+    APIRET       rc;
+    KEYPACKET    kp;
+    USHORT       count = sizeof(KEYPACKET);
+    MONBUF       monInbuf;
+    MONBUF       monOutbuf;
+    int          kpNew;
+
+    /* Raise thread priority for higher responsiveness */
+    DosSetPriority(PRTYS_THREAD, PRTYC_TIMECRITICAL, 0, 0);
+    monInbuf.cb  = sizeof(monInbuf) - sizeof(monInbuf.cb);
+    monOutbuf.cb = sizeof(monOutbuf) - sizeof(monOutbuf.cb);
+    bMonRunning = FALSE;
+
+    /* Register the buffers to be used for monitoring for current session */
+    if (DosMonReg(_EVT_hKbdMon, &monInbuf, (ULONG*)&monOutbuf,MONITOR_END, -1)) {
+	DosPostEventSem(hevStart);  /* unblock the main thread */
+	return;
+	}
+
+    /* Unblock the main thread and tell it we're OK*/
+    bMonRunning = TRUE;
+    DosPostEventSem(hevStart);
+    while (bMonRunning) {  /* Start an endless loop */
+	/* Read data from keyboard driver */
+	rc = DosMonRead((PBYTE)&monInbuf, IO_WAIT, (PBYTE)&kp, (PUSHORT)&count);
+	if (rc) {
+#ifdef CHECKED
+	    if (bMonRunning)
+		printf("Error in DosMonRead, rc = %ld\n", rc);
+#endif
+	    bMonRunning = FALSE;
+	    return;
+	    }
+
+	/* Pass FLUSH packets immediately */
+	if (kp.MonFlagWord & 4) {
+#ifdef CHECKED
+	    printf("Flush packet!\n");
+#endif
+	    DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count);
+	    continue;
+	    }
+
+	/*TODO: to be removed */
+	/* Skip extended scancodes & some others */
+	if (((kp.MonFlagWord >> 8) == 0xE0) || ((kp.KbdDDFlagWord & 0x0F) == 0x0F)) {
+	    DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count);
+	    continue;
+	    }
+
+/*      printf("RawScan = %X, XlatedScan = %X, fbStatus = %X, KbdDDFlags = %X\n", */
+/*          kp.MonFlagWord >> 8, kp.XlatedScan, kp.u.ShiftState, kp.KbdDDFlagWord); */
+
+	/* Protect access to buffer with mutex semaphore */
+	rc = DosRequestMutexSem(hmtxKeyBuf, 1000);
+	if (rc) {
+#ifdef CHECKED
+	    printf("Can't get access to mutex, rc = %ld\n", rc);
+#endif
+	    bMonRunning = FALSE;
+	    return;
+	    }
+
+	/* Store packet in circular buffer, drop it if it's full */
+	kpNew = kpHead + 1;
+	if (kpNew == KEYBUFSIZE)
+	    kpNew = 0;
+	if (kpNew != kpTail) {
+	    memcpy(&keyMonPkts[kpHead], &kp, sizeof(KEYPACKET));
+	    /* TODO: fix this! */
+	    /* Convert break to make code */
+	    keyMonPkts[kpHead].MonFlagWord &= 0x7FFF;
+	    kpHead = kpNew;
+	    }
+	DosReleaseMutexSem(hmtxKeyBuf);
+
+	/* Finally write the packet */
+	rc = DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count);
+	if (rc) {
+#ifdef CHECKED
+	    if (bMonRunning)
+		printf("Error in DosMonWrite, rc = %ld\n", rc);
+#endif
+	    bMonRunning = FALSE;
+	    return;
+	    }
+	}
+    (void)params;
+}
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort(
+    int signal)
+{
+    EVT_exit();
+    PM_fatalError("Unhandled exception!");
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    ushort  stat;
+
+    /* Initialise the event queue */
+    PM_init();
+    EVT.mouseMove = mouseMove;
+    initEventQueue();
+    oldMouseState = 0;
+    oldKeyMessage = 0;
+    memset(keyUpMsg,0,sizeof(keyUpMsg));
+
+    /* Open the mouse driver, and set it up to report events in mickeys */
+    MouOpen(NULL,&_EVT_hMouse);
+    stat = 0x7F;
+    MouSetEventMask(&stat,_EVT_hMouse);
+    stat = (MOU_NODRAW | MOU_MICKEYS) << 8;
+    MouSetDevStatus(&stat,_EVT_hMouse);
+
+    /* Open the keyboard monitor  */
+    if (DosMonOpen((PSZ)"KBD$", &_EVT_hKbdMon))
+	PM_fatalError("Unable to open keyboard monitor!");
+
+    /* Create event semaphore, the monitor will post it when it's initalized */
+    if (DosCreateEventSem(NULL, &hevStart, 0, FALSE))
+	PM_fatalError("Unable to create event semaphore!");
+
+    /* Create mutex semaphore protecting the keypacket buffer */
+    if (DosCreateMutexSem(NULL, &hmtxKeyBuf, 0, FALSE))
+	PM_fatalError("Unable to create mutex semaphore!");
+
+    /* Start keyboard monitor thread, use 32K stack */
+    kbdMonTID = _beginthread(_kbdMonThread, NULL, 0x8000, NULL);
+
+    /* Now block until the monitor thread is up and running */
+    /* Give the thread one second */
+    DosWaitEventSem(hevStart, 1000);
+    if (!bMonRunning) {  /* Check the thread is OK */
+	DosMonClose(_EVT_hKbdMon);
+	PM_fatalError("Keyboard monitor thread didn't initialize!");
+	}
+
+    /* Catch program termination signals so we can clean up properly */
+    signal(SIGABRT, _EVT_abort);
+    signal(SIGFPE, _EVT_abort);
+    signal(SIGINT, _EVT_abort);
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    rangeX = xRes;
+    rangeY = yRes;
+}
+
+/****************************************************************************
+REMARKS
+Modifes the mouse coordinates as necessary if scaling to OS coordinates,
+and sets the OS mouse cursor position.
+****************************************************************************/
+#define _EVT_setMousePos(x,y)
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for OS/2 */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for OS/2 */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+    APIRET   rc;
+
+    /* Restore signal handlers */
+    signal(SIGABRT, SIG_DFL);
+    signal(SIGFPE, SIG_DFL);
+    signal(SIGINT, SIG_DFL);
+
+    /* Close the mouse driver */
+    MouClose(_EVT_hMouse);
+
+    /* Stop the keyboard monitor thread and close the monitor */
+    bMonRunning = FALSE;
+    rc = DosKillThread(kbdMonTID);
+#ifdef CHECKED
+    if (rc)
+	printf("DosKillThread failed, rc = %ld\n", rc);
+#endif
+    rc = DosMonClose(_EVT_hKbdMon);
+#ifdef CHECKED
+    if (rc) {
+	printf("DosMonClose failed, rc = %ld\n", rc);
+	}
+#endif
+    DosCloseEventSem(hevStart);
+    DosCloseMutexSem(hmtxKeyBuf);
+    KbdFlushBuffer(0);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h b/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h
new file mode 100755
index 0000000..28d39fb
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h
@@ -0,0 +1,165 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit OS/2
+*
+* Description:  Include file to include all OS/2 keyboard monitor stuff.
+*
+****************************************************************************/
+
+/* Monitors stuff */
+
+#define MONITOR_DEFAULT 0x0000
+#define MONITOR_BEGIN        1
+#define MONITOR_END          2
+
+typedef SHANDLE   HMONITOR;
+typedef HMONITOR *PHMONITOR;
+
+typedef struct _KEYPACKET {
+  USHORT  MonFlagWord;
+  UCHAR   XlatedChar;
+  UCHAR   XlatedScan;
+  UCHAR   DBCSStatus;
+  UCHAR   DBCSShift;
+
+  union
+  {
+    USHORT  ShiftState;
+    USHORT  LayerIndex;
+  } u;
+
+  ULONG   Milliseconds;
+  USHORT  KbdDDFlagWord;
+} KEYPACKET;
+
+typedef struct _MLNPACKET {
+  USHORT  MonFlagWord;
+  USHORT  IOCTL;
+  USHORT  CPId;
+  USHORT  CPIndex;
+  ULONG   Reserved;
+  USHORT  KbdDDFlagWord;
+} MLNPACKET;
+
+/* DBCSStatus */
+
+#define SF_SHIFTS              1  /* If set to 1, shift status returned without a character */
+#define SF_NOTCHAR             2  /* 0 - Scan code is a character */
+				  /* 1 - Scan code is not a character; */
+				  /*     instead it is an extended key code from the keyboard. */
+#define SF_IMMEDIATE          32  /* If set to 1, immediate conversion requested */
+#define SF_TYPEMASK          192  /* Has the following values: */
+				  /* 00 - Undefined */
+				  /* 01 - Final character; interim character flag is turned off */
+				  /* 10 - Interim character */
+				  /* 11 - Final character; interim character flag is turned on. */
+/* MonFlagWord */
+
+#define MF_OPEN                1  /* open */
+#define MF_CLOSE               2  /* close */
+#define MF_FLUSH               4  /* is flush packet */
+
+/* KbdDDFlagWord */
+
+#define KF_NOTSQPACKET      1024  /* Don't put this packet in SQ buffer */
+#define KF_ACCENTEDKEY       512  /* Key was translated using previous accent. */
+#define KF_MULTIMAKE         256  /* Key was repeated make of a toggle key. */
+#define KF_SECONDARYKEY      128  /* Previous scan code was the E0 prefix code. */
+#define KF_KEYBREAK           64  /* This is the break of the key. */
+#define KF_KEYTYPEMASK        63  /* Isolates the Key Type field of DDFlags. */
+#define KF_UNDEFKEY           63  /* Key packet is undefined */
+#define KF_SYSREQKEY          23  /* This key packet is the SysReq key (4990) */
+#define KF_PRINTFLUSHKEY      22  /* This packet is Ct-Alt-PrtScr */
+#define KF_PSPRINTECHOKEY     21  /* This packet is Ctl-P */
+#define KF_PRINTECHOKEY       20  /* This packet is Ctl-PrtScr */
+#define KF_PRTSCRKEY          19  /* This packet is PrtScr */
+#define KF_PSBREAKKEY         18  /* This packet is Ctl-C */
+#define KF_BREAKKEY           17  /* This packet is Ctl-Break */
+#define KF_ACCENTKEY          16  /* This packet is an accent key */
+#define KF_XRORPNOT           13  /* This packet is a Read or Peek Notification Pct. */
+#define KF_MLNOTIFICATION     14  /* packet is a Multi-Layer NLS packet */
+#define KF_HOTKEYPACKET       12  /* This packet is the hot key. */
+#define KF_BADKEYCOMBO        11  /* Accent/char combo undefined, beep only. */
+#define KF_WAKEUPKEY          10  /* This packet is one following PAUSEKEY */
+#define KF_PSPAUSEKEY          9  /* This packet is Ctl-S */
+#define KF_PAUSEKEY            8  /* This packet is Ctl-Numlock or PAUSE */
+#define KF_SHIFTMASK           7  /* Key is a shift Key */
+#define KF_DUMPKEY             6  /* This packet is Ctl-Numlock-NumLock */
+#define KF_REBOOTKEY           5  /* This packet is Ctl-Alt-Del */
+#define KF_RESENDCODE          4  /* This packet is resend code from controller */
+#define KF_OVERRUNCODE         3  /* This packet is overrun code from controller */
+#define KF_SECPREFIXCODE       2  /* This packet is E0/E1 scan code */
+#define KF_ACKCODE             1  /* This packet is ack code from keyboard */
+
+
+typedef struct _MONBUF {
+  USHORT    cb;
+  KEYPACKET Buffer;
+  BYTE      Reserved[20];
+} MONBUF;
+
+#define RS_SYSREG      32768  /* Bit 15  SysReq key down */
+#define RS_CAPSLOCK    16384  /* Bit 14  Caps Lock key down */
+#define RS_NUMLOCK      8192  /* Bit 13  NumLock key down */
+#define RS_SCROLLLOCK   4096  /* Bit 12  Scroll Lock key down */
+#define RS_RALT         2048  /* Bit 11  Right Alt key down */
+#define RS_RCONTROL     1024  /* Bit 10  Right Ctrl key down */
+#define RS_LALT          512  /* Bit  9  Left Alt key down */
+#define RS_LCONTROL      256  /* Bit  8  Left Ctrl key down */
+#define RS_INSERT        128  /* Bit  7  Insert on */
+#define RS_CAPS           64  /* Bit  6  Caps Lock on */
+#define RS_NUM            32  /* Bit  5  NumLock on */
+#define RS_SCROLL         16  /* Bit  4  Scroll Lock on */
+#define RS_ALT             8  /* Bit  3  Either Alt key down */
+#define RS_CONTROL         4  /* Bit  2  Either Ctrl key down */
+#define RS_LSHIFT          2  /* Bit  1  Left Shift key down */
+#define RS_RSHIFT          1  /* Bit  0  Right Shift key down */
+
+
+#define CS_RCONTROL     91    /* Right Control */
+#define CS_LSHIFT       42    /* Left Shift */
+#define CS_RSHIFT       54    /* Right Shift */
+#define CS_LALT         56    /* Left Alt */
+#define CS_RALT         94    /* Right Alt */
+
+
+/* DosMon* prototypes */
+#ifdef __EMX__
+    #define  APIRET16        USHORT
+    #define  APIENTRY16
+#else
+    #define  DosMonOpen      DOS16MONOPEN
+    #define  DosMonClose     DOS16MONCLOSE
+    #define  DosMonReg       DOS16MONREG
+    #define  DosMonRead      DOS16MONREAD
+    #define  DosMonWrite     DOS16MONWRITE
+    #define  DosGetInfoSeg   DOS16GETINFOSEG
+#endif
+
+APIRET16 APIENTRY16 DosMonOpen   (PSZ pszDevName, PHMONITOR phmon);
+APIRET16 APIENTRY16 DosMonClose  (HMONITOR hmon);
+APIRET16 APIENTRY16 DosMonReg    (HMONITOR hmon, MONBUF *pbInBuf, /*MONBUF*/ULONG *pbOutBuf, USHORT fPosition, USHORT usIndex);
+APIRET16 APIENTRY16 DosMonRead   (PBYTE pbInBuf, USHORT fWait, PBYTE pbDataBuf, PUSHORT pcbData);
+APIRET16 APIENTRY16 DosMonWrite  (PBYTE pbOutBuf, PBYTE pbDataBuf, USHORT cbData);
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h
new file mode 100755
index 0000000..e7aa1c6
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h
@@ -0,0 +1,41 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit OS/2
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+#define INCL_DOSPROFILE
+#define INCL_DOSERRORS
+#define INCL_DOS
+#define INCL_SUB
+#define INCL_VIO
+#define INCL_KBD
+#include <os2.h>
+#include <process.h>
+#include "os2/mon.h"
+
+void __PM_checkConsoleSwitch(void);
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c b/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c
new file mode 100755
index 0000000..756eead
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c
@@ -0,0 +1,2008 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit OS/2
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "pm_help.h"
+#include "mtrr.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <process.h>
+#ifndef __EMX__
+#include <direct.h>
+#endif
+#define INCL_DOSERRORS
+#define INCL_DOS
+#define INCL_SUB
+#define INCL_VIO
+#define INCL_KBD
+#include <os2.h>
+
+/* Semaphore for communication with our background daemon */
+#define SHAREDSEM   ((PSZ)"\\SEM32\\SDD\\DAEMON")
+#define DAEMON_NAME "SDDDAEMN.EXE"
+
+/*--------------------------- Global variables ----------------------------*/
+
+/* Public structures used to communicate with VIDEOPMI for implementing
+ * the ability to call the real mode BIOS functions.
+ */
+
+typedef struct _VIDEOMODEINFO {
+    ULONG   miModeId;
+    USHORT  usType;
+    USHORT  usInt10ModeSet;
+    USHORT  usXResolution;
+    USHORT  usYResolution;
+    ULONG   ulBufferAddress;
+    ULONG   ulApertureSize;
+    BYTE    bBitsPerPixel;
+    BYTE    bBitPlanes;
+    BYTE    bXCharSize;
+    BYTE    bYCharSize;
+    USHORT  usBytesPerScanLine;
+    USHORT  usTextRows;
+    ULONG   ulPageLength;
+    ULONG   ulSaveSize;
+    BYTE    bVrtRefresh;
+    BYTE    bHrtRefresh;
+    BYTE    bVrtPolPos;
+    BYTE    bHrtPolPos;
+    CHAR    bRedMaskSize;
+    CHAR    bRedFieldPosition;
+    CHAR    bGreenMaskSize;
+    CHAR    bGreenFieldPosition;
+    CHAR    bBlueMaskSize;
+    CHAR    bBlueFieldPosition;
+    CHAR    bRsvdMaskSize;
+    CHAR    bRsvdFieldPosition;
+    ULONG   ulColors;
+    ULONG   ulReserved[3];
+    } VIDEOMODEINFO, FAR *PVIDEOMODEINFO;
+
+typedef struct _ADAPTERINFO {
+    ULONG       ulAdapterID;
+    CHAR        szOEMString[128];
+    CHAR        szDACString[128];
+    CHAR        szRevision[128];
+    ULONG       ulTotalMemory;
+    ULONG       ulMMIOBaseAddress;
+    ULONG       ulPIOBaseAddress;
+    BYTE        bBusType;
+    BYTE        bEndian;
+    USHORT      usDeviceBusID;
+    USHORT      usVendorBusID;
+    USHORT      SlotID;
+    } ADAPTERINFO, FAR *PADAPTERINFO;
+
+typedef struct _VIDEO_ADAPTER {
+    void            *hvideo;
+    ADAPTERINFO     Adapter;
+    VIDEOMODEINFO   ModeInfo;
+    } VIDEO_ADAPTER, FAR *PVIDEO_ADAPTER;
+
+/* PMIREQUEST_SOFTWAREINT structures from OS/2 DDK */
+
+typedef struct {
+    ULONG ulFlags;                              /* VDM initialization type */
+#define VDM_POSTLOAD                    0x1     /* adapter just loaded, used internally for initialization */
+#define VDM_INITIALIZE                  0x2     /* force initialization of a permanently open VDM, even if previously initialized */
+#define VDM_TERMINATE_POSTINITIALIZE    0x6     /*start VDM with initialization, but close it afterwards (includes VDM_INITIALIZE) */
+#define VDM_QUERY_CAPABILITY            0x10    /* query the current int 10 capability */
+#define VDM_FULL_VDM_CREATED            0x20    /* a full VDM is created */
+#define VDM_MINI_VDM_CREATED            0x40    /* a mini VDM is created */
+#define VDM_MINI_VDM_SUPPORTED          0x80    /* mini VDM support is available */
+    PCHAR szName;                               /* VDM initialization program */
+    PCHAR szArgs;                               /* VDM initialization arguments */
+    }INITVDM;
+
+typedef struct {
+    BYTE bBufferType;
+#define BUFFER_NONE     0
+#define INPUT_BUFFER    1
+#define OUTPUT_BUFFER   2
+    BYTE bReserved;
+    BYTE bSelCRF;
+    BYTE bOffCRF;
+    PVOID pAddress;
+    ULONG ulSize;
+    } BUFFER, *PBUFFER;
+
+typedef struct vcrf_s {
+    ULONG reg_eax;
+    ULONG reg_ebx;
+    ULONG reg_ecx;
+    ULONG reg_edx;
+    ULONG reg_ebp;
+    ULONG reg_esi;
+    ULONG reg_edi;
+    ULONG reg_ds;
+    ULONG reg_es;
+    ULONG reg_fs;
+    ULONG reg_gs;
+    ULONG reg_cs;
+    ULONG reg_eip;
+    ULONG reg_eflag;
+    ULONG reg_ss;
+    ULONG reg_esp;
+    } VCRF;
+
+typedef struct {
+    ULONG   ulBIOSIntNo;
+    VCRF    aCRF;
+    BUFFER  pB[2];
+    } INTCRF;
+
+#define PMIREQUEST_LOADPMIFILE          21
+#define PMIREQUEST_IDENTIFYADAPTER      22
+#define PMIREQUEST_SOFTWAREINT          23
+
+#ifdef  PTR_DECL_IN_FRONT
+#define EXPENTRYP   * EXPENTRY
+#else
+#define EXPENTRYP   EXPENTRY *
+#endif
+
+/* Entry point to VIDEOPMI32Request. This may be overridden by external
+ * code that has already loaded VIDEOPMI to avoid loading it twice.
+ */
+
+APIRET (EXPENTRYP PM_VIDEOPMI32Request)(PVIDEO_ADAPTER, ULONG, PVOID, PVOID) = NULL;
+static ibool        haveInt10 = -1; /* True if we have Int 10 support   */
+static ibool        useVPMI = true; /* False if VIDEOPMI unavailable    */
+static VIDEO_ADAPTER Adapter;       /* Video adapter for VIDEOPMI       */
+static uchar        RMBuf[1024];    /* Fake real mode transfer buffer   */
+static uint         VESABuf_len = 1024;/* Length of the VESABuf buffer  */
+static void         *VESABuf_ptr = NULL;/* Near pointer to VESABuf      */
+static uint         VESABuf_rseg;   /* Real mode segment of VESABuf     */
+static uint         VESABuf_roff;   /* Real mode offset of VESABuf      */
+static uchar *      lowMem = NULL;
+static ibool        isSessionSwitching = false;
+static ulong        parmsIn[4];     /* Must not cross 64Kb boundary!    */
+static ulong        parmsOut[4];    /* Must not cross 64Kb boundary!    */
+extern ushort       _PM_gdt;
+static void (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+/* DosSysCtl prototype. It is not declared in the headers but it is in the
+ * standard import libraries (DOSCALLS.876). Funny.
+ */
+APIRET APIENTRY DosSysCtl(ULONG ulFunction, PVOID pvData);
+
+/* This is the stack size for the threads that track the session switch event */
+#define SESSION_SWITCH_STACK_SIZE   32768
+
+typedef struct {
+    VIOMODEINFO     vmi;
+    USHORT          CursorX;
+    USHORT          CursorY;
+    UCHAR           FrameBuffer[1];
+    } CONSOLE_SAVE;
+
+typedef struct _SESWITCHREC {
+    /* The following variable is volatile because of PM_SUSPEND_APP         */
+    volatile int    Flags;          /* -1 or PM_DEACTIVATE or PM_REACTIVATE */
+    PM_saveState_cb Callback;       /* Save/restore context callback        */
+    HMTX            Mutex;          /* Exclusive access mutex               */
+    HEV             Event;          /* Posted after callback is called      */
+    } SESWITCHREC;
+
+/* Page sized block cache */
+
+#define PAGES_PER_BLOCK     32
+#define PAGE_BLOCK_SIZE     (PAGES_PER_BLOCK * PM_PAGE_SIZE + (PM_PAGE_SIZE-1) + sizeof(pageblock))
+#define FREELIST_NEXT(p)    (*(void**)(p))
+typedef struct pageblock {
+    struct pageblock    *next;
+    struct pageblock    *prev;
+    void                *freeListStart;
+    void                *freeList;
+    void                *freeListEnd;
+    int                 freeCount;
+    PM_lockHandle       lockHandle;
+    } pageblock;
+
+static pageblock    *pageBlocks = NULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+func        - Helper device driver function to call
+
+RETURNS:
+First return value from the device driver in parmsOut[0]
+
+REMARKS:
+Function to open our helper device driver, call it and close the file
+handle. Note that we have to open the device driver for every call because
+of two problems:
+
+ 1. We cannot open a single file handle in a DLL that is shared amongst
+    programs, since every process must have it's own open file handle.
+
+ 2. For some reason there appears to be a limit of about 12 open file
+    handles on a device driver in the system. Hence when we open more
+    than about 12 file handles things start to go very strange.
+
+Hence we simply open the file handle every time that we need to call the
+device driver to work around these problems.
+****************************************************************************/
+static ulong CallSDDHelp(
+    int func)
+{
+    static ulong    inLen;          /* Must not cross 64Kb boundary!    */
+    static ulong    outLen;         /* Must not cross 64Kb boundary!    */
+    HFILE           hSDDHelp;
+    ULONG           rc;
+    ulong           result;
+
+    if ((rc = DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0,
+	    FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE,
+	    NULL)) != 0) {
+	if (rc == 4) {  /* Did we run out of file handles? */
+	    ULONG   ulNewFHs;
+	    LONG    lAddFHs = 5;
+
+	    if (DosSetRelMaxFH(&lAddFHs, &ulNewFHs) != 0)
+		PM_fatalError("Failed to raise the file handles limit!");
+	    else {
+		if ((rc = DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0,
+			FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE,
+			NULL)) != 0) {
+		    PM_fatalError("Unable to open SDDHELP$ helper device driver! (#2)");
+		    }
+		}
+	    }
+	else
+	    PM_fatalError("Unable to open SDDHELP$ helper device driver!");
+	}
+    if (DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,func,
+	    &parmsIn, inLen = sizeof(parmsIn), &inLen,
+	    &parmsOut, outLen = sizeof(parmsOut), &outLen) != 0)
+	PM_fatalError("Failure calling SDDHELP$ helper device driver!");
+    DosClose(hSDDHelp);
+    return parmsOut[0];
+}
+
+/****************************************************************************
+REMARKS:
+Determine if we're running on a DBCS system.
+****************************************************************************/
+ibool __IsDBCSSystem(void)
+{
+    CHAR        achDBCSInfo[12];
+    COUNTRYCODE ccStruct = {0, 0};
+
+    memset(achDBCSInfo, 0, 12);
+
+    /* Get the DBCS vector - if it's not empty, we're on DBCS */
+    DosQueryDBCSEnv(sizeof(achDBCSInfo), &ccStruct, achDBCSInfo);
+    if (achDBCSInfo[0] != 0)
+	return true;
+    else
+	return false;
+}
+
+/****************************************************************************
+REMARKS:
+Determine if PMSHELL is running - if it isn't, we can't use certain calls
+****************************************************************************/
+ibool __isShellLoaded(void)
+{
+    PVOID   ptr;
+
+    if (DosGetNamedSharedMem(&ptr, (PSZ)"\\SHAREMEM\\PMGLOBAL.MEM", PAG_READ) == NO_ERROR) {
+	DosFreeMem(ptr);
+	return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Initialise the PM library and connect to our helper device driver. If we
+cannot connect to our helper device driver, we bail out with an error
+message.
+****************************************************************************/
+void PMAPI PM_init(void)
+{
+    if (!lowMem) {
+	/* Obtain the 32->16 callgate from the device driver to enable IOPL */
+	if ((_PM_gdt = CallSDDHelp(PMHELP_GETGDT32)) == 0)
+	    PM_fatalError("Unable to obtain call gate selector!");
+
+	PM_setIOPL(3);
+
+	/* Map the first Mb of physical memory into lowMem */
+	if ((lowMem = PM_mapPhysicalAddr(0,0xFFFFF,true)) == NULL)
+	    PM_fatalError("Unable to map first Mb physical memory!");
+
+	/* Initialise the MTRR interface functions */
+	MTRR_init();
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Initialise the PM library for BIOS access via VIDEOPMI. This should work
+with any GRADD driver, including SDD/2.
+****************************************************************************/
+static ibool InitInt10(void)
+{
+    HMODULE     hModGENPMI,hModSDDPMI,hModVideoPMI;
+    CHAR        buf[80],path[_MAX_PATH];
+    HEV         hevDaemon = NULLHANDLE;
+    RESULTCODES resCodes;
+
+    if (haveInt10 == -1) {
+	/* Connect to VIDEOPMI and get entry point. Note that we only
+	 * do this if GENPMI or SDDPMI are already loaded, since we need
+	 * a GRADD based driver for this to work.
+	 */
+	PM_init();
+	haveInt10 = false;
+	if (DosQueryModuleHandle((PSZ)"GENPMI.DLL",&hModGENPMI) != 0)
+	    hModGENPMI = NULLHANDLE;
+	if (DosQueryModuleHandle((PSZ)"SDDPMI.DLL",&hModSDDPMI) != 0)
+	    hModSDDPMI = NULLHANDLE;
+	if (hModGENPMI || hModSDDPMI) {
+	    if (DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"VIDEOPMI.DLL",&hModVideoPMI) == 0) {
+		if (DosQueryProcAddr(hModVideoPMI,0,(PSZ)"VIDEOPMI32Request",(void*)&PM_VIDEOPMI32Request) != 0)
+		    PM_fatalError("Unable to get VIDEOPMI32Request entry point!");
+		strcpy(path,"X:\\OS2\\SVGADATA.PMI");
+		path[0] = PM_getBootDrive();
+		if (PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_LOADPMIFILE,path,NULL) != 0) {
+		    DosFreeModule(hModVideoPMI);
+		    PM_VIDEOPMI32Request = NULL;
+		    haveInt10 = false;
+		    }
+		else {
+		    /* Attempt to initialise the full VDM in the system. This will only
+		     * work if VPRPMI.SYS is loaded, but it provides support for passing
+		     * values in ES/DS/ESI/EDI between the BIOS which does not work with
+		     * kernel VDM's in fixpacks earlier than FP15. FP15 and later and
+		     * the new Warp 4.51 and Warp Server convenience packs should work
+		     * fine with the kernel mini-VDM.
+		     *
+		     * Also the full VDM is the only solution for really old kernels
+		     * (but GRADD won't run on them so this is superfluous ;-).
+		     */
+		    INITVDM InitVDM = {VDM_INITIALIZE,NULL,NULL};
+		    PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&InitVDM,NULL);
+		    haveInt10 = true;
+		    }
+		}
+	    }
+	else {
+	    /* A GRADD driver isn't loaded, hence we can't use VIDEOPMI. But we will try
+	     * to access the mini-VDM directly, first verifying that the support is
+	     * available in the kernel (it should be for kernels that support GRADD).
+	     * This may be needed in a command line boot or if non-GRADD driver is
+	     * used (Matrox or classic VGA).
+	     * Note: because of problems with mini-VDM support in the kernel, we have to
+	     * spawn a daemon process that will do the actual mini-VDM access for us.
+	     */
+	     /* Try to open shared semaphore to see if our daemon is already up */
+	    if (DosOpenEventSem(SHAREDSEM, &hevDaemon) == NO_ERROR) {
+		if (DosWaitEventSem(hevDaemon, 1) == NO_ERROR) {
+		    /* If semaphore is posted, all is well */
+		    useVPMI   = false;
+		    haveInt10 = true;
+		    }
+		}
+	    else {
+		/* Create shared event semaphore */
+		if (DosCreateEventSem(SHAREDSEM, &hevDaemon, DC_SEM_SHARED, FALSE) == NO_ERROR) {
+		    PM_findBPD(DAEMON_NAME, path);
+		    strcat(path, DAEMON_NAME);
+		    if (DosExecPgm(buf, sizeof(buf), EXEC_BACKGROUND, (PSZ)DAEMON_NAME,
+			NULL, &resCodes, (PSZ)path) == NO_ERROR) {
+			/* The daemon was successfully spawned, now give it a sec to come up */
+			if (DosWaitEventSem(hevDaemon, 2000) == NO_ERROR) {
+			    /* It's up! */
+			    useVPMI   = false;
+			    haveInt10 = true;
+			    }
+			}
+		    }
+		}
+	    }
+	}
+    return haveInt10;
+}
+
+/****************************************************************************
+REMARKS:
+We "probably" have BIOS access under OS/2 but we have to verify/initialize it
+first.
+****************************************************************************/
+ibool PMAPI PM_haveBIOSAccess(void)
+{
+    return InitInt10();
+}
+
+/****************************************************************************
+REMARKS:
+Return the operating system type identifier.
+****************************************************************************/
+long PMAPI PM_getOSType(void)
+{
+    return _OS_OS2;
+}
+
+/****************************************************************************
+REMARKS:
+Return the runtime type identifier.
+****************************************************************************/
+int PMAPI PM_getModeType(void)
+{
+    return PM_386;
+}
+
+/****************************************************************************
+REMARKS:
+Add a file directory separator to the end of the filename.
+****************************************************************************/
+void PMAPI PM_backslash(
+    char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '\\') {
+	s[pos] = '\\';
+	s[pos+1] = '\0';
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Add a user defined PM_fatalError cleanup function.
+****************************************************************************/
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+/****************************************************************************
+REMARKS:
+Report a fatal error condition and halt the program.
+****************************************************************************/
+void PMAPI PM_fatalError(
+    const char *msg)
+{
+    /* Be prepare to be called recursively (failed to fail situation :-) */
+    static int fatalErrorCount = 0;
+    if (fatalErrorCount++ == 0) {
+	if (fatalErrorCleanup)
+	    fatalErrorCleanup();
+	}
+    fprintf(stderr,"%s\n", msg);
+    exit(1);
+}
+
+/****************************************************************************
+REMARKS:
+Allocate the real mode VESA transfer buffer for communicating with the BIOS.
+****************************************************************************/
+void * PMAPI PM_getVESABuf(
+    uint *len,
+    uint *rseg,
+    uint *roff)
+{
+    if (!VESABuf_ptr) {
+	/* Allocate a global buffer for communicating with the VESA VBE */
+	if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL)
+	    return NULL;
+	}
+    *len = VESABuf_len;
+    *rseg = VESABuf_rseg;
+    *roff = VESABuf_roff;
+    return VESABuf_ptr;
+}
+
+/****************************************************************************
+REMARKS:
+Check if a key has been pressed.
+****************************************************************************/
+int PMAPI PM_kbhit(void)
+{
+    KBDKEYINFO   key;            /* Must not cross a 64K boundary    */
+
+    KbdPeek(&key, 0);
+    return (key.fbStatus & KBDTRF_FINAL_CHAR_IN);
+}
+
+/****************************************************************************
+REMARKS:
+Wait for and return the next keypress.
+****************************************************************************/
+int PMAPI PM_getch(void)
+{
+    KBDKEYINFO   key;            /* Must not cross a 64K boundary    */
+
+    KbdCharIn(&key,IO_WAIT,0);
+    return key.chChar;
+}
+
+/****************************************************************************
+REMARKS:
+Open a fullscreen console for output to the screen. This requires that
+the application be a fullscreen VIO program.
+****************************************************************************/
+PM_HWND PMAPI PM_openConsole(
+    PM_HWND hwndUser,
+    int device,
+    int xRes,
+    int yRes,
+    int bpp,
+    ibool fullScreen)
+{
+    (void)hwndUser;
+    (void)device;
+    (void)xRes;
+    (void)yRes;
+    (void)bpp;
+    (void)fullScreen;
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Find the size of the console state buffer.
+****************************************************************************/
+int PMAPI PM_getConsoleStateSize(void)
+{
+    VIOMODEINFO vmi;
+    vmi.cb = sizeof (VIOMODEINFO);
+    VioGetMode (&vmi, (HVIO)0);
+    return sizeof (CONSOLE_SAVE) - 1 + vmi.col * vmi.row * 2;
+}
+
+/****************************************************************************
+REMARKS:
+Save the state of the console.
+****************************************************************************/
+void PMAPI PM_saveConsoleState(
+    void *stateBuf,
+    PM_HWND hwndConsole)
+{
+    USHORT          fblen;
+    CONSOLE_SAVE    *cs = (CONSOLE_SAVE*)stateBuf;
+    VIOMODEINFO     vmi;
+
+    /* The reason for the VIOMODEINFO juggling is 16-bit code. Because the user
+     * allocates the state buffer, cd->vmi might be crossing the 64K boundary and
+     * the 16-bit API would fail. If we create another copy on stack, the compiler
+     * should ensure that the 64K boundary will not be crossed (it adjusts the stack
+     * if it should cross).
+     */
+    vmi.cb = sizeof(VIOMODEINFO);
+    VioGetMode(&vmi,(HVIO)0);
+    memcpy(&cs->vmi, &vmi, sizeof(VIOMODEINFO));
+    VioGetCurPos(&cs->CursorY, &cs->CursorX, (HVIO)0);
+    fblen = cs->vmi.col * cs->vmi.row * 2;
+    VioReadCellStr((PCH)cs->FrameBuffer, &fblen, 0, 0, (HVIO)0);
+}
+
+/* Global variable to communicate between threads */
+static SESWITCHREC SesSwitchRec = { -1 };
+
+/****************************************************************************
+REMARKS:
+Called by external routines at least once per frame to check whenever a
+session save/restore should be performed. Since we receive such notifications
+asyncronously, we can't perform all required operations at that time.
+****************************************************************************/
+void __PM_checkConsoleSwitch(void)
+{
+    int             Flags, Mode;
+    PM_saveState_cb Callback;
+
+    /* Quick optimized path for most common case */
+    if (SesSwitchRec.Flags == -1)
+	return;
+
+again:
+    if (DosRequestMutexSem(SesSwitchRec.Mutex, 100))
+	return;
+    Flags = SesSwitchRec.Flags;
+    Callback = SesSwitchRec.Callback;
+    SesSwitchRec.Flags = -1;
+    DosReleaseMutexSem(SesSwitchRec.Mutex);
+
+    isSessionSwitching = true;            /* Prevent VIO calls */
+    Mode = Callback(Flags);
+    isSessionSwitching = false;
+    DosPostEventSem(SesSwitchRec.Event);
+    if (Flags == PM_DEACTIVATE && Mode == PM_SUSPEND_APP)
+	/* Suspend application until we switch back to our application */
+	for (;;) {
+	    DosSleep (500);
+	    /* SesSwitchRec.Flags is volatile so optimizer
+	     * won't load it into a register
+	     */
+	    if (SesSwitchRec.Flags != -1)
+		goto again;
+	    }
+}
+
+/****************************************************************************
+REMARKS:
+Waits until main thread processes the session switch event.
+****************************************************************************/
+static void _PM_SessionSwitchEvent(
+    PM_saveState_cb saveState,
+    int flags)
+{
+    ULONG Count;
+
+    if (DosRequestMutexSem(SesSwitchRec.Mutex, 10000))
+	return;
+
+    /* We're going to wait on that semaphore */
+    DosResetEventSem(SesSwitchRec.Event, &Count);
+    SesSwitchRec.Callback = saveState;
+    SesSwitchRec.Flags = flags;
+    DosReleaseMutexSem(SesSwitchRec.Mutex);
+
+    /* Now wait until all required operations are complete */
+    DosWaitEventSem (SesSwitchRec.Event, 10000);
+}
+
+/****************************************************************************
+REMARKS:
+This is the thread responsible for tracking switches back to our
+fullscreen session.
+****************************************************************************/
+static void _PM_ConsoleSwitch(
+    PM_saveState_cb saveState)
+{
+    USHORT NotifyType;
+
+    for (;;) {
+	if (VioModeWait(VMWR_POPUP, &NotifyType, 0) != 0)
+	    break;
+	_PM_SessionSwitchEvent(saveState, PM_REACTIVATE);
+	}
+    VioModeUndo(UNDOI_RELEASEOWNER, UNDOK_ERRORCODE, (HVIO)0);
+}
+
+/****************************************************************************
+REMARKS:
+This is the thread responsible for tracking screen popups (usually fatal
+error handler uses them).
+****************************************************************************/
+static void _PM_ConsolePopup(
+    PM_saveState_cb saveState)
+{
+    USHORT NotifyType;
+    for (;;) {
+	if (VioSavRedrawWait(VSRWI_SAVEANDREDRAW, &NotifyType, 0) != 0)
+	    break;
+	if (NotifyType == VSRWN_SAVE)
+	    _PM_SessionSwitchEvent(saveState, PM_DEACTIVATE);
+	else if (NotifyType == VSRWN_REDRAW)
+	    _PM_SessionSwitchEvent(saveState, PM_REACTIVATE);
+	}
+    VioSavRedrawUndo(UNDOI_RELEASEOWNER, UNDOK_ERRORCODE, (HVIO)0);
+}
+
+/****************************************************************************
+REMARKS:
+Set the suspend application callback for the fullscreen console.
+****************************************************************************/
+void PMAPI PM_setSuspendAppCallback(
+    PM_saveState_cb saveState)
+{
+    /* If PM isn't loaded, this stuff will cause crashes! */
+    if (__isShellLoaded()) {
+	if (saveState) {
+	    /* Create the threads responsible for tracking console switches */
+	    SesSwitchRec.Flags = -1;
+	    DosCreateMutexSem(NULL, &SesSwitchRec.Mutex, 0, FALSE);
+	    DosCreateEventSem(NULL, &SesSwitchRec.Event, 0, FALSE);
+	    _beginthread ((void(*)(void*))_PM_ConsoleSwitch,NULL,SESSION_SWITCH_STACK_SIZE, (void*)saveState);
+	    _beginthread ((void(*)(void*))_PM_ConsolePopup,NULL,SESSION_SWITCH_STACK_SIZE, (void*)saveState);
+	    }
+	else {
+	    /* Kill the threads responsible for tracking console switches */
+	    VioModeUndo(UNDOI_RELEASEOWNER, UNDOK_TERMINATE, (HVIO)0);
+	    VioSavRedrawUndo(UNDOI_RELEASEOWNER, UNDOK_TERMINATE, (HVIO)0);
+	    DosCloseEventSem(SesSwitchRec.Event);
+	    DosCloseMutexSem(SesSwitchRec.Mutex);
+	    }
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Restore the console state.
+****************************************************************************/
+void PMAPI PM_restoreConsoleState(
+    const void *stateBuf,
+    PM_HWND hwndConsole)
+{
+    CONSOLE_SAVE *cs = (CONSOLE_SAVE *)stateBuf;
+    VIOMODEINFO  vmi;
+
+    if (!cs)
+	return;
+
+    memcpy(&vmi, &cs->vmi, sizeof (VIOMODEINFO));
+    VioSetMode(&vmi, (HVIO)0);
+    VioSetCurPos(cs->CursorY, cs->CursorX, (HVIO)0);
+    VioWrtCellStr((PCH)cs->FrameBuffer, cs->vmi.col * cs->vmi.row * 2,0, 0, (HVIO)0);
+}
+
+/****************************************************************************
+REMARKS:
+Close the fullscreen console.
+****************************************************************************/
+void PMAPI PM_closeConsole(
+    PM_HWND hwndConsole)
+{
+    /* Kill the threads responsible for tracking console switches */
+    PM_setSuspendAppCallback(NULL);
+    (void)hwndConsole;
+}
+
+/****************************************************************************
+REMARKS:
+Set the location of the OS console cursor.
+****************************************************************************/
+void PM_setOSCursorLocation(
+    int x,
+    int y)
+{
+    /* If session switch is in progress, calling into VIO causes deadlocks! */
+    /* Also this call to VIO screws up our console library on DBCS boxes... */
+    if (!isSessionSwitching && !__IsDBCSSystem())
+	VioSetCurPos(y,x,0);
+}
+
+/****************************************************************************
+REMARKS:
+Set the width of the OS console.
+****************************************************************************/
+void PM_setOSScreenWidth(
+    int width,
+    int height)
+{
+    /* Nothing to do in here */
+    (void)width;
+    (void)height;
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock handler (used for software stereo modes).
+****************************************************************************/
+ibool PMAPI PM_setRealTimeClockHandler(
+    PM_intHandler ih,
+    int frequency)
+{
+    /* TODO: Implement this! */
+    (void)ih;
+    (void)frequency;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock frequency (for stereo modes).
+****************************************************************************/
+void PMAPI PM_setRealTimeClockFrequency(
+    int frequency)
+{
+    /* TODO: Implement this! */
+    (void)frequency;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the original real time clock handler.
+****************************************************************************/
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    /* TODO: Implement this! */
+}
+
+/****************************************************************************
+REMARKS:
+Return the current operating system path or working directory.
+****************************************************************************/
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    return getcwd(path,maxLen);
+}
+
+/****************************************************************************
+REMARKS:
+Return the drive letter for the boot drive.
+****************************************************************************/
+char PMAPI PM_getBootDrive(void)
+{
+    ulong   boot = 3;
+    DosQuerySysInfo(QSV_BOOT_DRIVE,QSV_BOOT_DRIVE,&boot,sizeof(boot));
+    return (char)('a' + boot - 1);
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the VBE/AF driver files.
+****************************************************************************/
+const char * PMAPI PM_getVBEAFPath(void)
+{
+    static char path[CCHMAXPATH];
+    strcpy(path,"x:\\");
+    path[0] = PM_getBootDrive();
+    return path;
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus driver files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusPath(void)
+{
+    static char path[CCHMAXPATH];
+    if (getenv("NUCLEUS_PATH") != NULL)
+	return getenv("NUCLEUS_PATH");
+    strcpy(path,"x:\\os2\\drivers");
+    path[0] = PM_getBootDrive();
+    PM_backslash(path);
+    strcat(path,"nucleus");
+    return path;
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus configuration files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[CCHMAXPATH];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+/****************************************************************************
+REMARKS:
+Return a unique identifier for the machine if possible.
+****************************************************************************/
+const char * PMAPI PM_getUniqueID(void)
+{
+    return PM_getMachineName();
+}
+
+/****************************************************************************
+REMARKS:
+Get the name of the machine on the network.
+****************************************************************************/
+const char * PMAPI PM_getMachineName(void)
+{
+    static char name[40],*env;
+
+    if ((env = getenv("HOSTNAME")) != NULL) {
+	strncpy(name,env,sizeof(name));
+	name[sizeof(name)-1] = 0;
+	return name;
+	}
+    return "OS2";
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to the real mode BIOS data area.
+****************************************************************************/
+void * PMAPI PM_getBIOSPointer(void)
+{
+    PM_init();
+    return lowMem + 0x400;
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to 0xA0000 physical VGA graphics framebuffer.
+****************************************************************************/
+void * PMAPI PM_getA0000Pointer(void)
+{
+    PM_init();
+    return lowMem + 0xA0000;
+}
+
+/****************************************************************************
+REMARKS:
+Map a physical address to a linear address in the callers process.
+****************************************************************************/
+void * PMAPI PM_mapPhysicalAddr(
+    ulong base,
+    ulong limit,
+    ibool isCached)
+{
+    ulong   baseAddr,baseOfs,linear;
+
+    /* Round the physical address to a 4Kb boundary and the limit to a
+     * 4Kb-1 boundary before passing the values to mmap. If we round the
+     * physical address, then we also add an extra offset into the address
+     * that we return.
+     */
+    baseOfs = base & 4095;
+    baseAddr = base & ~4095;
+    limit = ((limit+baseOfs+1+4095) & ~4095)-1;
+    parmsIn[0] = baseAddr;
+    parmsIn[1] = limit;
+    parmsIn[2] = isCached;
+    if ((linear = CallSDDHelp(PMHELP_MAPPHYS)) == 0)
+	return NULL;
+    return (void*)(linear + baseOfs);
+}
+
+/****************************************************************************
+REMARKS:
+Free a physical address mapping allocated by PM_mapPhysicalAddr.
+****************************************************************************/
+void PMAPI PM_freePhysicalAddr(
+    void *ptr,
+    ulong limit)
+{
+    parmsIn[0] = (ulong)ptr;
+    parmsIn[1] = limit;
+    CallSDDHelp(PMHELP_FREEPHYS);
+}
+
+/****************************************************************************
+REMARKS:
+Find the physical address of a linear memory address in current process.
+****************************************************************************/
+ulong PMAPI PM_getPhysicalAddr(
+    void *p)
+{
+    parmsIn[0] = (ulong)p;
+    return CallSDDHelp(PMHELP_GETPHYSICALADDR);
+}
+
+/****************************************************************************
+REMARKS:
+Find the physical address of a linear memory address in current process.
+****************************************************************************/
+ibool PMAPI PM_getPhysicalAddrRange(
+    void *p,
+    ulong length,
+    ulong *physAddress)
+{
+    parmsIn[0] = (ulong)p;
+    parmsIn[1] = (ulong)length;
+    parmsIn[2] = (ulong)physAddress;
+    return CallSDDHelp(PMHELP_GETPHYSICALADDRRANGE);
+}
+
+/****************************************************************************
+REMARKS:
+Sleep for the specified number of milliseconds.
+****************************************************************************/
+void PMAPI PM_sleep(
+    ulong milliseconds)
+{
+    DosSleep(milliseconds);
+}
+
+/****************************************************************************
+REMARKS:
+Return the base I/O port for the specified COM port.
+****************************************************************************/
+int PMAPI PM_getCOMPort(
+    int port)
+{
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Return the base I/O port for the specified LPT port.
+****************************************************************************/
+int PMAPI PM_getLPTPort(
+    int port)
+{
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of shared memory. For Win9x we allocate shared memory
+as locked, global memory that is accessible from any memory context
+(including interrupt time context), which allows us to load our important
+data structure and code such that we can access it directly from a ring
+0 interrupt context.
+****************************************************************************/
+void * PMAPI PM_mallocShared(
+    long size)
+{
+    parmsIn[0] = size;
+    return (void*)CallSDDHelp(PMHELP_MALLOCSHARED);
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of shared memory.
+****************************************************************************/
+void PMAPI PM_freeShared(
+    void *ptr)
+{
+    parmsIn[0] = (ulong)ptr;
+    CallSDDHelp(PMHELP_FREESHARED);
+}
+
+/****************************************************************************
+REMARKS:
+Map a linear memory address to the calling process address space. The
+address will have been allocated in another process using the
+PM_mapPhysicalAddr function.
+****************************************************************************/
+void * PMAPI PM_mapToProcess(
+    void *base,
+    ulong limit)
+{
+    ulong   baseAddr,baseOfs;
+
+    /* Round the physical address to a 4Kb boundary and the limit to a
+     * 4Kb-1 boundary before passing the values to mmap. If we round the
+     * physical address, then we also add an extra offset into the address
+     * that we return.
+     */
+    baseOfs = (ulong)base & 4095;
+    baseAddr = (ulong)base & ~4095;
+    limit = ((limit+baseOfs+1+4095) & ~4095)-1;
+    parmsIn[0] = (ulong)baseAddr;
+    parmsIn[1] = limit;
+    return (void*)(CallSDDHelp(PMHELP_MAPTOPROCESS)+baseOfs);
+}
+
+/****************************************************************************
+REMARKS:
+Map a real mode pointer to a protected mode pointer.
+****************************************************************************/
+void * PMAPI PM_mapRealPointer(
+    uint r_seg,
+    uint r_off)
+{
+    if (r_seg == 0xFFFF)
+	return &RMBuf[r_off];
+    return lowMem + MK_PHYS(r_seg,r_off);
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of real mode memory
+****************************************************************************/
+void * PMAPI PM_allocRealSeg(
+    uint size,
+    uint *r_seg,
+    uint *r_off)
+{
+    if (size > sizeof(RMBuf))
+	return NULL;
+    *r_seg = 0xFFFF;
+    *r_off = 0x0000;
+    return &RMBuf;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of real mode memory.
+****************************************************************************/
+void PMAPI PM_freeRealSeg(
+    void *mem)
+{
+    /* Nothing to do in here */
+    (void)mem;
+}
+
+#define INDPMI(reg)     rmregs.aCRF.reg_##reg = regs->reg
+#define OUTDPMI(reg)    regs->reg = rmregs.aCRF.reg_##reg
+
+#define REG_OFFSET(field)  (((ULONG)&(((VCRF*)0)->field))  / sizeof(ULONG))
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt (parameters in DPMI compatible structure)
+****************************************************************************/
+void PMAPI DPMI_int86(
+    int intno,
+    DPMI_regs *regs)
+{
+    INTCRF  rmregs;
+    ulong   eax = 0;
+
+    if (!InitInt10())
+	return;
+    memset(&rmregs, 0, sizeof(rmregs));
+    rmregs.ulBIOSIntNo = intno;
+    INDPMI(eax); INDPMI(ebx); INDPMI(ecx); INDPMI(edx); INDPMI(esi); INDPMI(edi);
+    rmregs.aCRF.reg_ds = regs->ds;
+    rmregs.aCRF.reg_es = regs->es;
+    if (intno == 0x10) {
+	eax = rmregs.aCRF.reg_eax;
+	switch (eax & 0xFFFF) {
+	    case 0x4F00:
+		/* We have to hack the way this function works, due to
+		 * some bugs in the IBM mini-VDM BIOS support. Specifically
+		 * we need to make the input buffer and output buffer the
+		 * 'same' buffer, and that ES:SI points to the output
+		 * buffer (ignored by the BIOS). The data will end up
+		 * being returned in the input buffer, except for the
+		 * first four bytes ('VESA') that will not be returned.
+		 */
+		rmregs.pB[0].bBufferType = INPUT_BUFFER;
+		rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es);
+		rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi);
+		rmregs.pB[0].pAddress = RMBuf;
+		rmregs.pB[0].ulSize = 4;
+		rmregs.pB[1].bBufferType = OUTPUT_BUFFER;
+		rmregs.pB[1].bSelCRF = REG_OFFSET(reg_es);
+		rmregs.pB[1].bOffCRF = REG_OFFSET(reg_esi);
+		rmregs.pB[1].pAddress = ((PBYTE)RMBuf)+4;
+		rmregs.pB[1].ulSize = 512-4;
+		break;
+	    case 0x4F01:
+		rmregs.pB[0].bBufferType = OUTPUT_BUFFER;
+		rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es);
+		rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi);
+		rmregs.pB[0].pAddress = RMBuf;
+		rmregs.pB[0].ulSize = 256;
+		break;
+	    case 0x4F02:
+		rmregs.pB[0].bBufferType = INPUT_BUFFER;
+		rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es);
+		rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi);
+		rmregs.pB[0].pAddress = RMBuf;
+		rmregs.pB[0].ulSize = 256;
+		break;
+	    case 0x4F09:
+		rmregs.pB[0].bBufferType = INPUT_BUFFER;
+		rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es);
+		rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi);
+		rmregs.pB[0].pAddress = RMBuf;
+		rmregs.pB[0].ulSize = 1024;
+		break;
+	    case 0x4F0A:
+		/* Due to bugs in the mini-VDM in OS/2, the 0x4F0A protected
+		 * mode interface functions will not work (we never get any
+		 * selectors returned), so we fail this function here. The
+		 * rest of the VBE/Core driver will work properly if this
+		 * function is failed, because the VBE 2.0 and 3.0 specs
+		 * allow for this.
+		 */
+		regs->eax = 0x014F;
+		return;
+	    }
+	}
+    if (useVPMI)
+	PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,NULL,&rmregs);
+    else {
+	DosSysCtl(6, &rmregs);
+	}
+
+    OUTDPMI(eax); OUTDPMI(ebx); OUTDPMI(ecx); OUTDPMI(edx); OUTDPMI(esi); OUTDPMI(edi);
+    if (((regs->eax & 0xFFFF) == 0x004F) && ((eax & 0xFFFF) == 0x4F00)) {
+	/* Hack to fix up the missing 'VESA' string for mini-VDM */
+	memcpy(RMBuf,"VESA",4);
+	}
+    regs->ds = rmregs.aCRF.reg_ds;
+    regs->es = rmregs.aCRF.reg_es;
+    regs->flags = rmregs.aCRF.reg_eflag;
+}
+
+#define IN(reg)     rmregs.reg = in->e.reg
+#define OUT(reg)    out->e.reg = rmregs.reg
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt.
+****************************************************************************/
+int PMAPI PM_int86(
+    int intno,
+    RMREGS *in,
+    RMREGS *out)
+{
+    DPMI_regs   rmregs;
+
+    memset(&rmregs, 0, sizeof(rmregs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+    DPMI_int86(intno,&rmregs);
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+    out->x.cflag = rmregs.flags & 0x1;
+    return out->x.ax;
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt.
+****************************************************************************/
+int PMAPI PM_int86x(
+    int intno,
+    RMREGS *in,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    DPMI_regs   rmregs;
+
+    memset(&rmregs, 0, sizeof(rmregs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+    rmregs.es = sregs->es;
+    rmregs.ds = sregs->ds;
+    DPMI_int86(intno,&rmregs);
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+    sregs->es = rmregs.es;
+    sregs->cs = rmregs.cs;
+    sregs->ss = rmregs.ss;
+    sregs->ds = rmregs.ds;
+    out->x.cflag = rmregs.flags & 0x1;
+    return out->x.ax;
+}
+
+/****************************************************************************
+REMARKS:
+Call a real mode far function.
+****************************************************************************/
+void PMAPI PM_callRealMode(
+    uint seg,
+    uint off,
+    RMREGS *in,
+    RMSREGS *sregs)
+{
+    PM_fatalError("PM_callRealMode not supported on OS/2!");
+}
+
+/****************************************************************************
+REMARKS:
+Return the amount of available memory.
+****************************************************************************/
+void PMAPI PM_availableMemory(
+    ulong *physical,
+    ulong *total)
+{
+    /* Unable to get reliable values from OS/2 for this */
+    *physical = *total = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of locked, physical memory for DMA operations.
+****************************************************************************/
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16M)
+{
+    parmsIn[0] = size;
+    parmsIn[1] = contiguous;
+    parmsIn[2] = below16M;
+    CallSDDHelp(PMHELP_ALLOCLOCKED);
+    *physAddr = parmsOut[1];
+    return (void*)parmsOut[0];
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of locked physical memory.
+****************************************************************************/
+void PMAPI PM_freeLockedMem(
+    void *p,
+    uint size,
+    ibool contiguous)
+{
+    parmsIn[0] = (ulong)p;
+    CallSDDHelp(PMHELP_FREELOCKED);
+}
+
+/****************************************************************************
+REMARKS:
+Allocates a new block of pages for the page block manager.
+****************************************************************************/
+static pageblock *PM_addNewPageBlock(void)
+{
+    int         i;
+    pageblock   *newBlock;
+    char        *p,*next;
+
+    /* Allocate memory for the new page block, and add to head of list */
+    if (DosAllocSharedMem((void**)&newBlock,NULL,PAGE_BLOCK_SIZE,OBJ_GETTABLE | PAG_READ | PAG_WRITE | PAG_COMMIT))
+	return NULL;
+    if (!PM_lockDataPages(newBlock,PAGE_BLOCK_SIZE,&newBlock->lockHandle))
+	return NULL;
+    newBlock->prev = NULL;
+    newBlock->next = pageBlocks;
+    if (pageBlocks)
+	pageBlocks->prev = newBlock;
+    pageBlocks = newBlock;
+
+    /* Initialise the page aligned free list for the page block */
+    newBlock->freeCount = PAGES_PER_BLOCK;
+    newBlock->freeList = p = (char*)(((ulong)(newBlock + 1) + (PM_PAGE_SIZE-1)) & ~(PM_PAGE_SIZE-1));
+    newBlock->freeListStart = newBlock->freeList;
+    newBlock->freeListEnd = p + (PAGES_PER_BLOCK-1) * PM_PAGE_SIZE;
+    for (i = 0; i < PAGES_PER_BLOCK; i++,p = next)
+	FREELIST_NEXT(p) = next = p + PM_PAGE_SIZE;
+    FREELIST_NEXT(p - PM_PAGE_SIZE) = NULL;
+    return newBlock;
+}
+
+/****************************************************************************
+REMARKS:
+Allocates a page aligned and page sized block of memory
+****************************************************************************/
+void * PMAPI PM_allocPage(
+    ibool locked)
+{
+    pageblock   *block;
+    void        *p;
+
+    /* Scan the block list looking for any free blocks. Allocate a new
+     * page block if no free blocks are found.
+     */
+    for (block = pageBlocks; block != NULL; block = block->next) {
+	if (block->freeCount)
+	    break;
+	}
+    if (block == NULL && (block = PM_addNewPageBlock()) == NULL)
+	return NULL;
+    block->freeCount--;
+    p = block->freeList;
+    block->freeList = FREELIST_NEXT(p);
+    (void)locked;
+    return p;
+}
+
+/****************************************************************************
+REMARKS:
+Free a page aligned and page sized block of memory
+****************************************************************************/
+void PMAPI PM_freePage(
+    void *p)
+{
+    pageblock   *block;
+
+    /* First find the page block that this page belongs to */
+    for (block = pageBlocks; block != NULL; block = block->next) {
+	if (p >= block->freeListStart && p <= block->freeListEnd)
+	    break;
+	}
+    CHECK(block != NULL);
+
+    /* Now free the block by adding it to the free list */
+    FREELIST_NEXT(p) = block->freeList;
+    block->freeList = p;
+    if (++block->freeCount == PAGES_PER_BLOCK) {
+	/* If all pages in the page block are now free, free the entire
+	 * page block itself.
+	 */
+	if (block == pageBlocks) {
+	    /* Delete from head */
+	    pageBlocks = block->next;
+	    if (block->next)
+		block->next->prev = NULL;
+	    }
+	else {
+	    /* Delete from middle of list */
+	    CHECK(block->prev != NULL);
+	    block->prev->next = block->next;
+	    if (block->next)
+		block->next->prev = block->prev;
+	    }
+
+	/* Unlock the memory and free it */
+	PM_unlockDataPages(block,PAGE_BLOCK_SIZE,&block->lockHandle);
+	DosFreeMem(block);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Map in all the shared memory blocks for managing the memory pages above.
+****************************************************************************/
+void PMAPI PM_mapSharedPages(void)
+{
+    pageblock   *block;
+
+    /* Map all the page blocks above into the shared memory for process */
+    for (block = pageBlocks; block != NULL; block = block->next) {
+	DosGetSharedMem(block, PAG_READ | PAG_WRITE);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockDataPages(
+    void *p,
+    uint len,
+    PM_lockHandle *lockHandle)
+{
+    parmsIn[0] = (ulong)p;
+    parmsIn[1] = len;
+    CallSDDHelp(PMHELP_LOCKPAGES);
+    lockHandle->h[0] = parmsOut[1];
+    lockHandle->h[1] = parmsOut[2];
+    lockHandle->h[2] = parmsOut[3];
+    return parmsOut[0];
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockDataPages(
+    void *p,
+    uint len,
+    PM_lockHandle *lockHandle)
+{
+    parmsIn[0] = lockHandle->h[0];
+    parmsIn[1] = lockHandle->h[1];
+    parmsIn[2] = lockHandle->h[2];
+    return CallSDDHelp(PMHELP_UNLOCKPAGES);
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockCodePages(
+    void (*p)(),
+    uint len,
+    PM_lockHandle *lockHandle)
+{
+    parmsIn[0] = (ulong)p;
+    parmsIn[1] = len;
+    CallSDDHelp(PMHELP_LOCKPAGES);
+    lockHandle->h[0] = parmsOut[1];
+    lockHandle->h[1] = parmsOut[2];
+    lockHandle->h[2] = parmsOut[3];
+    return parmsOut[0];
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockCodePages(
+    void (*p)(),
+    uint len,
+    PM_lockHandle *lockHandle)
+{
+    parmsIn[0] = lockHandle->h[0];
+    parmsIn[1] = lockHandle->h[1];
+    parmsIn[2] = lockHandle->h[2];
+    return CallSDDHelp(PMHELP_UNLOCKPAGES);
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankA(
+    int bank)
+{
+    INTCRF  rmregs;
+
+    if (!InitInt10())
+	return;
+    memset(&rmregs, 0, sizeof(rmregs));
+    rmregs.ulBIOSIntNo = 0x10;
+    rmregs.aCRF.reg_eax = 0x4F05;
+    rmregs.aCRF.reg_ebx = 0x0000;
+    rmregs.aCRF.reg_edx = bank;
+    PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankAB(
+    int bank)
+{
+    INTCRF  rmregs;
+
+    if (!InitInt10())
+	return;
+    memset(&rmregs, 0, sizeof(rmregs));
+    rmregs.ulBIOSIntNo = 0x10;
+    rmregs.aCRF.reg_eax = 0x4F05;
+    rmregs.aCRF.reg_ebx = 0x0000;
+    rmregs.aCRF.reg_edx = bank;
+    PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL);
+    rmregs.ulBIOSIntNo = 0x10;
+    rmregs.aCRF.reg_eax = 0x4F05;
+    rmregs.aCRF.reg_ebx = 0x0001;
+    rmregs.aCRF.reg_edx = bank;
+    PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display start address.
+****************************************************************************/
+void PMAPI PM_setCRTStart(
+    int x,
+    int y,
+    int waitVRT)
+{
+    INTCRF  rmregs;
+
+    if (!InitInt10())
+	return;
+    memset(&rmregs, 0, sizeof(rmregs));
+    rmregs.ulBIOSIntNo = 0x10;
+    rmregs.aCRF.reg_eax = 0x4F07;
+    rmregs.aCRF.reg_ebx = waitVRT;
+    rmregs.aCRF.reg_ecx = x;
+    rmregs.aCRF.reg_edx = y;
+    PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Execute the POST on the secondary BIOS for a controller.
+****************************************************************************/
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS,
+    ulong BIOSLen)
+{
+    (void)axVal;
+    (void)BIOSPhysAddr;
+    (void)mappedBIOS;
+    (void)BIOSLen;
+    return false;
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+RETURNS:
+Error code describing the result.
+
+REMARKS:
+Function to enable write combining for the specified region of memory.
+****************************************************************************/
+int PMAPI PM_enableWriteCombine(
+    ulong base,
+    ulong size,
+    uint type)
+{
+    return MTRR_enableWriteCombine(base,size,type);
+}
+
+/* TODO: Move the MTRR helper stuff into the call gate, or better yet */
+/*       entirely into the ring 0 helper driver!! */
+
+/* MTRR helper functions. To make it easier to implement the MTRR support
+ * under OS/2, we simply put our ring 0 helper functions into the
+ * helper device driver rather than the entire MTRR module. This makes
+ * it easier to maintain the MTRR support since we don't need to deal
+ * with 16-bit ring 0 code in the MTRR library.
+ */
+
+/****************************************************************************
+REMARKS:
+Flush the translation lookaside buffer.
+****************************************************************************/
+void PMAPI PM_flushTLB(void)
+{
+    CallSDDHelp(PMHELP_FLUSHTLB);
+}
+
+/****************************************************************************
+REMARKS:
+Return true if ring 0 (or if we can call the helpers functions at ring 0)
+****************************************************************************/
+ibool _ASMAPI _MTRR_isRing0(void)
+{
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Read and return the value of the CR4 register
+****************************************************************************/
+ulong _ASMAPI _MTRR_saveCR4(void)
+{
+    return CallSDDHelp(PMHELP_SAVECR4);
+}
+
+/****************************************************************************
+REMARKS:
+Restore the value of the CR4 register
+****************************************************************************/
+void _ASMAPI _MTRR_restoreCR4(ulong cr4Val)
+{
+    parmsIn[0] = cr4Val;
+    CallSDDHelp(PMHELP_RESTORECR4);
+}
+
+/****************************************************************************
+REMARKS:
+Read a machine status register for the CPU.
+****************************************************************************/
+void _ASMAPI _MTRR_readMSR(
+    ulong reg,
+    ulong *eax,
+    ulong *edx)
+{
+    parmsIn[0] = reg;
+    CallSDDHelp(PMHELP_READMSR);
+    *eax = parmsOut[0];
+    *edx = parmsOut[1];
+}
+
+/****************************************************************************
+REMARKS:
+Write a machine status register for the CPU.
+****************************************************************************/
+void _ASMAPI _MTRR_writeMSR(
+    ulong reg,
+    ulong eax,
+    ulong edx)
+{
+    parmsIn[0] = reg;
+    parmsIn[1] = eax;
+    parmsIn[2] = edx;
+    CallSDDHelp(PMHELP_WRITEMSR);
+}
+
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    /* TODO: Implement this to load shared libraries! */
+    (void)szDLLName;
+    return NULL;
+}
+
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    /* TODO: Implement this! */
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    /* TODO: Implement this! */
+    (void)hModule;
+}
+
+/****************************************************************************
+REMARKS:
+Internal function to convert the find data to the generic interface.
+****************************************************************************/
+static void convertFindData(
+    PM_findData *findData,
+    FILEFINDBUF3 *blk)
+{
+    ulong   dwSize = findData->dwSize;
+
+    memset(findData,0,findData->dwSize);
+    findData->dwSize = dwSize;
+    if (blk->attrFile & FILE_READONLY)
+	findData->attrib |= PM_FILE_READONLY;
+    if (blk->attrFile & FILE_DIRECTORY)
+	findData->attrib |= PM_FILE_DIRECTORY;
+    if (blk->attrFile & FILE_ARCHIVED)
+	findData->attrib |= PM_FILE_ARCHIVE;
+    if (blk->attrFile & FILE_HIDDEN)
+	findData->attrib |= PM_FILE_HIDDEN;
+    if (blk->attrFile & FILE_SYSTEM)
+	findData->attrib |= PM_FILE_SYSTEM;
+    findData->sizeLo = blk->cbFile;
+    findData->sizeHi = 0;
+    strncpy(findData->name,blk->achName,PM_MAX_PATH);
+    findData->name[PM_MAX_PATH-1] = 0;
+}
+
+#define FIND_MASK   (FILE_ARCHIVED | FILE_DIRECTORY | FILE_SYSTEM | FILE_HIDDEN | FILE_READONLY)
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+void *PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    FILEFINDBUF3    blk;
+    HDIR            hdir = HDIR_CREATE;
+    ulong           count = 1;
+
+    if (DosFindFirst((PSZ)filename,&hdir,FIND_MASK,&blk,sizeof(blk),&count,FIL_STANDARD) == NO_ERROR) {
+	convertFindData(findData,&blk);
+	return (void*)hdir;
+	}
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    void *handle,
+    PM_findData *findData)
+{
+    FILEFINDBUF3    blk;
+    ulong           count = 1;
+
+    if (DosFindNext((HDIR)handle,&blk,sizeof(blk),&count) == NO_ERROR) {
+	convertFindData(findData,&blk);
+	return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    void *handle)
+{
+    DosFindClose((HDIR)handle);
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    0   - Current drive
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    ulong   cntDisk,cntDriveMap;
+    ibool   valid;
+
+    DosQueryCurrentDisk(&cntDisk,&cntDriveMap);
+    valid = (DosSetDefaultDisk(drive) == NO_ERROR);
+    DosSetDefaultDisk(cntDisk);
+    return valid;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    ulong length = len;
+
+    DosQueryCurrentDir(drive, (PSZ)dir, &length);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+    FILESTATUS3 s;
+
+    if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s)))
+	return;
+    s.attrFile = 0;
+    if (attrib & PM_FILE_READONLY)
+	s.attrFile |= FILE_READONLY;
+    if (attrib & PM_FILE_ARCHIVE)
+	s.attrFile |= FILE_ARCHIVED;
+    if (attrib & PM_FILE_HIDDEN)
+	s.attrFile |= FILE_HIDDEN;
+    if (attrib & PM_FILE_SYSTEM)
+	s.attrFile |= FILE_SYSTEM;
+    DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s),0L);
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file attributes for a specific file.
+****************************************************************************/
+uint PMAPI PM_getFileAttr(
+    const char *filename)
+{
+    FILESTATUS3 fs3;
+    uint        retval = 0;
+
+    if (DosQueryPathInfo((PSZ)filename, FIL_STANDARD, &fs3, sizeof(FILESTATUS3)))
+	return 0;
+    if (fs3.attrFile & FILE_READONLY)
+	retval |= PM_FILE_READONLY;
+    if (fs3.attrFile & FILE_ARCHIVED)
+	retval |= PM_FILE_ARCHIVE;
+    if (fs3.attrFile & FILE_HIDDEN)
+	retval |= PM_FILE_HIDDEN;
+    if (fs3.attrFile & FILE_SYSTEM)
+	retval |= PM_FILE_SYSTEM;
+    return retval;
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+    return DosCreateDir((PSZ)filename,NULL) == NO_ERROR;
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+    return DosDeleteDir((PSZ)filename) == NO_ERROR;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_getFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    FILESTATUS3 fs3;
+    struct tm   tc;
+    struct tm   *ret;
+    time_t      tt;
+
+    if (DosQueryPathInfo((PSZ)filename, FIL_STANDARD, &fs3, sizeof(FILESTATUS3)))
+	return false;
+    if (gmTime) {
+	tc.tm_year = fs3.fdateLastWrite.year + 80;
+	tc.tm_mon = fs3.fdateLastWrite.month - 1;
+	tc.tm_mday = fs3.fdateLastWrite.day;
+	tc.tm_hour = fs3.ftimeLastWrite.hours;
+	tc.tm_min = fs3.ftimeLastWrite.minutes;
+	tc.tm_sec = fs3.ftimeLastWrite.twosecs * 2;
+	if((tt = mktime(&tc)) == -1)
+	    return false;
+	if(!(ret = gmtime(&tt)))
+	    return false;
+	time->sec = ret->tm_sec;
+	time->day = ret->tm_mday;
+	time->mon = ret->tm_mon + 1;
+	time->year = ret->tm_year - 80;
+	time->min = ret->tm_min;
+	time->hour = ret->tm_hour;
+	}
+    else {
+	time->sec = fs3.ftimeLastWrite.twosecs * 2;
+	time->day = fs3.fdateLastWrite.day;
+	time->mon = fs3.fdateLastWrite.month;
+	time->year = fs3.fdateLastWrite.year;
+	time->min = fs3.ftimeLastWrite.minutes;
+	time->hour = fs3.ftimeLastWrite.hours;
+	}
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Function to set the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_setFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    FILESTATUS3 fs3;
+    struct tm   tc;
+    struct tm   *ret;
+    time_t      tt;
+
+    if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&fs3,sizeof(fs3)))
+	return false;
+    if (gmTime) {
+	tc.tm_year = time->year + 80;
+	tc.tm_mon = time->mon - 1;
+	tc.tm_mday = time->day;
+	tc.tm_hour = time->hour;
+	tc.tm_min = time->min;
+	tc.tm_sec = time->sec;
+	if((tt = mktime(&tc)) == -1)
+	    return false;
+	ret = localtime(&tt);
+	fs3.ftimeLastWrite.twosecs = ret->tm_sec / 2;
+	fs3.fdateLastWrite.day = ret->tm_mday;
+	fs3.fdateLastWrite.month = ret->tm_mon + 1;
+	fs3.fdateLastWrite.year = ret->tm_year - 80;
+	fs3.ftimeLastWrite.minutes = ret->tm_min;
+	fs3.ftimeLastWrite.hours = ret->tm_hour;
+	}
+    else {
+	fs3.ftimeLastWrite.twosecs = time->sec / 2;
+	fs3.fdateLastWrite.day = time->day;
+	fs3.fdateLastWrite.month = time->mon;
+	fs3.fdateLastWrite.year = time->year;
+	fs3.ftimeLastWrite.minutes = time->min;
+	fs3.ftimeLastWrite.hours = time->hour;
+	}
+    memcpy(&fs3.fdateLastAccess, &fs3.fdateLastWrite, sizeof(FDATE));
+    memcpy(&fs3.fdateCreation, &fs3.fdateLastWrite, sizeof(FDATE));
+    memcpy(&fs3.ftimeLastAccess, &fs3.ftimeLastWrite, sizeof(FTIME));
+    memcpy(&fs3.ftimeCreation, &fs3.ftimeLastWrite, sizeof(FTIME));
+    DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&fs3,sizeof(FILESTATUS3),0L);
+    return true;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c
new file mode 100755
index 0000000..579ef2c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c
@@ -0,0 +1,49 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    baseAddr = baseAddr;
+    bankSize = bankSize;
+    codeLen = codeLen;
+    bankFunc = bankFunc;
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c
new file mode 100755
index 0000000..30ffe43
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c
@@ -0,0 +1,110 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  OS/2
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+/*---------------------------- Global variables ---------------------------*/
+
+static ulong    frequency;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+void __ZTimerInit(void)
+{
+    DosTmrQueryFreq(&frequency);
+}
+
+/****************************************************************************
+REMARKS:
+Start the Zen Timer counting.
+****************************************************************************/
+#define __LZTimerOn(tm) DosTmrQueryTime((QWORD*)&tm->start)
+
+/****************************************************************************
+REMARKS:
+Compute the lap time since the timer was started.
+****************************************************************************/
+static ulong __LZTimerLap(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger    tmLap,tmCount;
+
+    DosTmrQueryTime((QWORD*)&tmLap);
+    _CPU_diffTime64(&tm->start,&tmLap,&tmCount);
+    return _CPU_calcMicroSec(&tmCount,frequency);
+}
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOff(tm)    DosTmrQueryTime((QWORD*)&tm->end)
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+static ulong __LZTimerCount(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger tmCount;
+
+    _CPU_diffTime64(&tm->start,&tm->end,&tmCount);
+    return _CPU_calcMicroSec(&tmCount,frequency);
+}
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION     1000
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer value from the BIOS timer tick.
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{
+    ULONG   count;
+    DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) );
+    return count;
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c b/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c
new file mode 100755
index 0000000..7af20a9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c
@@ -0,0 +1,170 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  IBM PC (OS/2)
+*
+* Description:  OS/2 implementation for the SciTech cross platform
+*               event library.
+*
+****************************************************************************/
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static int          oldMouseState;      /* Old mouse state              */
+static ulong        oldKeyMessage;      /* Old keyboard state           */
+static ushort       keyUpMsg[256] = {0};/* Table of key up messages     */
+static int          rangeX,rangeY;      /* Range of mouse coordinates   */
+HMOU                _EVT_hMouse;        /* Handle to the mouse driver   */
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* These are not used under OS/2 */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flags)
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Scan code to test
+
+REMARKS:
+This macro determines if a specified key is currently down at the
+time that the call is made.
+****************************************************************************/
+#define _EVT_isKeyDown(scanCode)    (keyUpMsg[scanCode] != 0)
+
+/****************************************************************************
+REMARKS:
+Pumps all messages in the message queue from OS/2 into our event queue.
+****************************************************************************/
+static void _EVT_pumpMessages(void)
+{
+    /* TODO: Implement this for OS/2 Presentation Manager apps! */
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort()
+{
+    EVT_exit();
+    PM_fatalError("Unhandled exception!");
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    /* Initialise the event queue */
+    EVT.mouseMove = mouseMove;
+    initEventQueue();
+    oldMouseState = 0;
+    oldKeyMessage = 0;
+    memset(keyUpMsg,0,sizeof(keyUpMsg));
+
+    /* TODO: OS/2 PM specific initialisation code! */
+
+    /* Catch program termination signals so we can clean up properly */
+    signal(SIGABRT, _EVT_abort);
+    signal(SIGFPE, _EVT_abort);
+    signal(SIGINT, _EVT_abort);
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    rangeX = xRes;
+    rangeY = yRes;
+}
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for OS/2 */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for OS/2 */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+    /* Restore signal handlers */
+    signal(SIGABRT, SIG_DFL);
+    signal(SIGFPE, SIG_DFL);
+    signal(SIGINT, SIG_DFL);
+
+    /* TODO: OS/2 PM specific exit code */
+}
+
+/****************************************************************************
+REMARKS
+Modifes the mouse coordinates as necessary if scaling to OS coordinates,
+and sets the OS mouse cursor position.
+****************************************************************************/
+#define _EVT_setMousePos(x,y)
diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h
new file mode 100755
index 0000000..0b69f82
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h
@@ -0,0 +1,36 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit OS/2
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+#define INCL_DOSERRORS
+#define INCL_DOS
+#define INCL_SUB
+#define INCL_VIO
+#define INCL_KBD
+#include <os2.h>
diff --git a/board/MAI/bios_emulator/scitech/src/pm/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/oshdr.h
new file mode 100755
index 0000000..404e5c9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/oshdr.h
@@ -0,0 +1,70 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Header file to pull in OS specific headers for the target
+*               OS environment.
+*
+****************************************************************************/
+
+#if     defined(__SMX32__)
+#include "smx/oshdr.h"
+#elif   defined(__RTTARGET__)
+#include "rttarget/oshdr.h"
+#elif   defined(__REALDOS__)
+#include "dos/oshdr.h"
+#elif   defined(__WIN32_VXD__)
+#include "vxd/oshdr.h"
+#elif   defined(__NT_DRIVER__)
+#include "ntdrv/oshdr.h"
+#elif   defined(__WINDOWS32__)
+#include "win32/oshdr.h"
+#elif   defined(__OS2_VDD__)
+#include "vxd/oshdr.h"
+#elif   defined(__OS2__)
+#if     defined(__OS2_PM__)
+#include "os2pm/oshdr.h"
+#else
+#include "os2/oshdr.h"
+#endif
+#elif   defined(__LINUX__)
+#if     defined(__USE_X11__)
+#include "x11/oshdr.h"
+#else
+#include "linux/oshdr.h"
+#endif
+#elif   defined(__QNX__)
+#if     defined(__USE_PHOTON__)
+#include "photon/oshdr.h"
+#elif   defined(__USE_X11__)
+#include "x11/oshdr.h"
+#else
+#include "qnx/oshdr.h"
+#endif
+#elif   defined(__BEOS__)
+#include "beos/oshdr.h"
+#else
+#error  PM library not ported to this platform yet!
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/pm/photon/event.c b/board/MAI/bios_emulator/scitech/src/pm/photon/event.c
new file mode 100755
index 0000000..581da16
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/photon/event.c
@@ -0,0 +1,268 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX Photon GUI
+*
+* Description:  QNX fullscreen console implementation for the SciTech
+*               cross platform event library.
+*
+****************************************************************************/
+
+/*--------------------------- Global variables ----------------------------*/
+
+static ushort       keyUpMsg[256] = {0};/* Table of key up messages     */
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* These are not used under Linux */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flags)
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Scan code to test
+
+REMARKS:
+This macro determines if a specified key is currently down at the
+time that the call is made.
+****************************************************************************/
+static ibool _EVT_isKeyDown(
+    uchar scancode)
+{
+    return (KeyState[(scancode & 0xf8) >> 3] & (1 << (scancode & 0x7)) ?
+	true : false);
+}
+
+/****************************************************************************
+REMARKS:
+Retrieves all events from the mouse/keyboard event queue and stuffs them
+into the MGL event queue for further processing.
+****************************************************************************/
+static void _EVT_pumpMessages(void)
+{
+    int         pid;
+    uint            msg, but_stat, message;
+    uchar           evt[sizeof (PhEvent_t) + 1024];
+    PhEvent_t       *event = (void *)evt;
+    PhKeyEvent_t        *key;
+    PhPointerEvent_t    *mouse;
+    static int      extended;
+    event_t         _evt;
+
+    while (count < EVENTQSIZE) {
+	uint    mods = 0, keyp = 0;
+
+	pid = Creceive(0, &msg, sizeof (msg));
+
+	if (pid == -1)
+	    return;
+
+	if (PhEventRead(pid, event, sizeof (evt)) == Ph_EVENT_MSG) {
+	    memset(&evt, 0, sizeof (evt));
+	    if (event->type == Ph_EV_KEY) {
+		key = PhGetData(event);
+
+		if (key->key_flags & KEY_SCAN_VALID) {
+		    keyp = key->key_scan;
+		    if (key->key_flags & KEY_DOWN)
+			KeyState[(keyp & 0xf800) >> 11]
+			    |= 1 << ((keyp & 0x700) >> 8);
+		    else
+			KeyState[(keyp & 0xf800) >> 11]
+			    &= ~(1 << ((keyp & 0x700) >> 8));
+		}
+		if ((key->key_flags & KEY_SYM_VALID) || extended)
+		    keyp |= key->key_sym;
+
+		/* No way to tell left from right... */
+		if (key->key_mods & KEYMOD_SHIFT)
+		    mods = (EVT_LEFTSHIFT | EVT_RIGHTSHIFT);
+		if (key->key_mods & KEYMOD_CTRL)
+		    mods |= (EVT_CTRLSTATE | EVT_LEFTCTRL);
+		if (key->key_mods & KEYMOD_ALT)
+		    mods |= (EVT_ALTSTATE | EVT_LEFTALT);
+
+		_evt.when = evt->timestamp;
+		if (key->key_flags & KEY_REPEAT) {
+		    _evt.what = EVT_KEYREPEAT;
+		    _evt.message = 0x10000;
+		    }
+		else if (key->key_flags & KEY_DOWN)
+		    _evt.what = EVT_KEYDOWN;
+		else
+		    _evt.what = EVT_KEYUP;
+		_evt.modifiers = mods;
+		_evt.message |= keyp;
+
+		addEvent(&_evt);
+
+		switch(key->key_scan & 0xff00) {
+		    case 0xe000:
+			extended = 1;
+			break;
+		    case 0xe001:
+			extended = 2;
+			break;
+		    default:
+			if (extended)
+			    extended--;
+		    }
+		}
+	    else if (event->type & Ph_EV_PTR_ALL) {
+		but_stat = message = 0;
+		mouse = PhGetData(event);
+
+		if (mouse->button_state & Ph_BUTTON_3)
+		    but_stat = EVT_LEFTBUT;
+		if (mouse->buttons & Ph_BUTTON_3)
+		    message = EVT_LEFTBMASK;
+
+		if (mouse->button_state & Ph_BUTTON_1)
+		    but_stat |= EVT_RIGHTBUT;
+		if (mouse->buttons & Ph_BUTTON_1)
+		    message |= EVT_RIGHTBMASK;
+
+		_evt.when = evt->timestamp;
+		if (event->type & Ph_EV_PTR_MOTION) {
+		    _evt.what = EVT_MOUSEMOVE;
+		    _evt.where_x = mouse->pos.x;
+		    _evt.where_y = mouse->pos.y;
+		    _evt.modifiers = but_stat;
+		    addEvent(&_evt);
+		    }
+		if (event->type & Ph_EV_BUT_PRESS)
+		    _evt.what = EVT_MOUSEDOWN;
+		else
+		    _evt.what = EVT_MOUSEUP;
+		_evt.where_x = mouse->pos.x;
+		_evt.where_y = mouse->pos.y;
+		_evt.modifiers = but_stat;
+		_evt.message = message;
+		addEvent(&_evt);
+		}
+	    }
+	else
+	    return;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort(
+    int signo)
+{
+    char    buf[80];
+
+    EVT_exit();
+    sprintf(buf,"Terminating on signal %d",signo);
+    PM_fatalError(buf);
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    int         i;
+
+    /* Initialise the event queue */
+    _mouseMove = mouseMove;
+    initEventQueue();
+    memset((void *)KeyState, 0, sizeof (KeyState));
+
+    /* Catch program termination signals so we can clean up properly */
+    signal(SIGABRT, _EVT_abort);
+    signal(SIGFPE, _EVT_abort);
+    signal(SIGINT, _EVT_abort);
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    /* TODO: Need to call Input to change the coordinates that it returns */
+    /*       for mouse events!! */
+}
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for Photon */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for Photon */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+    /* Restore signal handlers */
+    signal(SIGABRT, SIG_DFL);
+    signal(SIGFPE, SIG_DFL);
+    signal(SIGINT, SIG_DFL);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h
new file mode 100755
index 0000000..3c72563
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h
@@ -0,0 +1,38 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX Photon GUI
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+#include <sys/mouse.h>
+#include <sys/keyboard.h>
+#include <sys/fd.h>
+#include <sys/stat.h>
+#include <conio.h>
+#include <process.h>
+#include <sys/kernel.h>
+#include <Ph.h>
diff --git a/board/MAI/bios_emulator/scitech/src/pm/pm.vpw b/board/MAI/bios_emulator/scitech/src/pm/pm.vpw
new file mode 100755
index 0000000..26e68a7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/pm.vpw
@@ -0,0 +1,43 @@
+[Dependencies]

+[CurrentProject]

+curproj=pmlinux.vpj

+[ProjectFiles]

+pmcommon.vpj

+pmdos.vpj

+pmlinux.vpj

+pmqnx.vpj

+pmvxd.vpj

+pmwin32.vpj

+z_samples.vpj

+..\a-global includes.vpj

+[TreeExpansion]

+"..\a-global includes.vpj" 0

+pmcommon.vpj 0

+pmdos.vpj 0

+pmlinux.vpj 0

+pmqnx.vpj 0

+pmvxd.vpj 0

+pmwin32.vpj 0

+z_samples.vpj 1 1

+[State]

+SCREEN: 1280 1024 0 0 960 746 0 0 M 0 0 0 0 977 631

+CWD: C:\scitech\src\pm

+FILEHIST: 9

+C:\scitech\makedefs\gcc_win32.mk

+C:\scitech\bin\gcc2-w32.bat

+C:\scitech\bin\gcc2-c32.bat

+C:\scitech\bin\gcc2-linux.bat

+C:\scitech\makedefs\gcc_linux.mk

+C:\scitech\src\pm\linux\event.c

+C:\scitech\src\pm\linux\oshdr.h

+C:\scitech\src\pm\event.c

+C:\scitech\src\pm\pmlinux.vpj

+[ProjectDates]

+pmcommon.vpj=20010517164335290

+pmdos.vpj=20010517164335290

+pmlinux.vpj=20010620175829812

+pmqnx.vpj=20010517164335290

+pmvxd.vpj=20010517164335306

+pmwin32.vpj=20010517164335306

+z_samples.vpj=20010517164335306

+..\a-global includes.vpj=20010517164334978

diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj
new file mode 100755
index 0000000..48b872d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj
@@ -0,0 +1,45 @@
+[COMPILER]

+version=5.0b

+MACRO=\n

+activeconfig=,wc10-d32

+FILTERNAME=Source Files\nInclude Files\nAssembler Files\nOther Files\n

+FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n*.*\n

+FILTERASSOCIATEFILETYPES=0 0 0 0 

+FILTERAPPCOMMAND=\n\n\n\n

+vcsproject=SCC:Perforce SCM://depot

+vcslocalpath=SCC:Perforce SCM:c:\

+compile=concur|capture|hide|:Compile:&Compile,

+make=concur|capture|hide|clear|saveall|:Build:&Build,

+rebuild=concur|capture|hide|clear|saveall|:Rebuild:&Rebuild,

+debug=concur|capture|hide|savenone|:Debug:&Debug,

+execute=hide|savenone|:Execute:E&xecute,

+user1=hide|:User 1:User 1,

+user2=hide|:User 2:User 2,

+workingdir=.

+includedirs=%(SCITECH)\include;%(PRIVATE)\include

+reffile=

+[FILES]

+common.c

+cpuinfo.c

+debug.c

+event.c

+makefile

+oshdr.h

+ztimer.c

+..\common\agplib.c

+codepage\us_eng.c

+common\_cpuinfo.asm

+common\_dma.asm

+common\_int64.asm

+common\_joy.asm

+common\_mtrr.asm

+common\_pcilib.asm

+common\agp.c

+common\keyboard.c

+common\malloc.c

+common\mtrr.c

+common\pcilib.c

+common\unixio.c

+common\vgastate.c

+[ASSOCIATION]

+[CONFIGURATIONS]

diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj
new file mode 100755
index 0000000..1157513
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj
@@ -0,0 +1,41 @@
+[SciTech]

+compiler=wc10- 

+targetos=d32 

+[COMPILER]

+version=5.0b

+MACRO=enable_current_compiler\n

+activeconfig=,TEST_HARNESS=1

+FILTERNAME=Source Files\nInclude Files\nAssembler Files\n

+FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n

+FILTERASSOCIATEFILETYPES=0 0 0 

+FILTERAPPCOMMAND=\n\n\n

+vcsproject=SCC:Perforce SCM://depot

+vcslocalpath=SCC:Perforce SCM:c:\

+compile=concur|capture|clear|:Compile:&Compile,dmake %n.obj -u %b

+make=concur|capture|clear|saveall|:Build:&Build,dmake install %b

+rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u %b

+debug=concur|capture|hide|savenone|:Debug:&Debug,

+execute=hide|savenone|nochangedir|:Execute:E&xecute,

+user1=hide|:User 1:User 1,

+user2=hide|:User 2:User 2,

+usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe

+workingdir=.

+includedirs=%(SCITECH)\include;%(PRIVATE)\include

+reffile=

+[FILES]

+dos\_event.asm

+dos\_lztimer.asm

+dos\_pm.asm

+dos\_pmdos.asm

+dos\_vflat.asm

+dos\cpuinfo.c

+dos\event.c

+dos\oshdr.h

+dos\pm.c

+dos\pmdos.c

+dos\vflat.c

+dos\ztimer.c

+[ASSOCIATION]

+[CONFIGURATIONS]

+config=,NORMAL_BUILD=1

+config=,TEST_HARNESS=1

diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj
new file mode 100755
index 0000000..0bfbf84
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj
@@ -0,0 +1,35 @@
+[SciTech]

+compiler=gcc2-

+targetos=linux

+[COMPILER]

+version=5.0b

+MACRO=enable_current_compiler\n

+FILTERNAME=Source Files\nInclude Files\nAssembler Files\n

+FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n

+FILTERASSOCIATEFILETYPES=0 0 0

+FILTERAPPCOMMAND=\n\n\n

+vcsproject=SCC:Perforce SCM://depot

+vcslocalpath=SCC:Perforce SCM:c:\

+activeconfig=,install BUILD_DLL=1

+compile=concur|capture|clear|:Compile:&Compile,dmake %n.o -u

+make=concur|capture|clear|saveall|:Build:&Build,dmake %b

+rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake -u %b

+debug=concur|capture|hide|savenone|:Debug:&Debug,

+execute=hide|savenone|nochangedir|:Execute:E&xecute,

+user1=hide|:User 1:User 1,

+user2=hide|:User 2:User 2,

+usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe

+workingdir=.

+includedirs=%(SCITECH)\include;%(PRIVATE)\include

+reffile=

+[FILES]

+linux\cpuinfo.c

+linux\event.c

+linux\oshdr.h

+linux\pm.c

+linux\vflat.c

+linux\ztimer.c

+[ASSOCIATION]

+[CONFIGURATIONS]

+config=,install BUILD_DLL=1

+config=,install

diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj
new file mode 100755
index 0000000..3ec35a7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj
@@ -0,0 +1,39 @@
+[SciTech]

+compiler=vc60- 

+targetos=drvw2k

+[COMPILER]

+version=5.0b

+MACRO=enable_current_compiler\n

+activeconfig=,wc10-d32

+FILTERNAME=Source Files\nInclude Files\nAssembler Files\n

+FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n

+FILTERASSOCIATEFILETYPES=0 0 0

+FILTERAPPCOMMAND=\n\n\n

+vcsproject=SCC:Perforce SCM://depot

+vcslocalpath=SCC:Perforce SCM:c:\

+compile=concur|capture|:Compile:&Compile,dmake %n.obj

+make=concur|capture|clear|saveall|:Build:&Build,dmake install

+rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u

+debug=concur|capture|hide|savenone|:Debug:&Debug,

+execute=hide|savenone|nochangedir|:Execute:E&xecute,

+user1=hide|:User 1:User 1,

+user2=hide|:User 2:User 2,

+usertool_clean_directory=concur|capture|hide|savenone|:Clean Directory:&Clean Directory,dmake cleanexe

+workingdir=.

+includedirs=%(SCITECH)\include;%(PRIVATE)\include

+reffile=

+[FILES]

+..\..\include\ntdriver.h

+ntdrv\_pm.asm

+ntdrv\cpuinfo.c

+ntdrv\int86.c

+ntdrv\irq.c

+ntdrv\mem.c

+ntdrv\oshdr.h

+ntdrv\pm.c

+ntdrv\stdio.c

+ntdrv\stdlib.c

+ntdrv\vflat.c

+ntdrv\ztimer.c

+[ASSOCIATION]

+[CONFIGURATIONS]

diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj
new file mode 100755
index 0000000..d541702
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj
@@ -0,0 +1,35 @@
+[SciTech]

+compiler=wc10-

+targetos=qnx

+[COMPILER]

+version=5.0b

+MACRO=enable_current_compiler\n

+activeconfig=,wc10-d32

+FILTERNAME=Source Files\nInclude Files\nAssembler Files\n

+FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n

+FILTERASSOCIATEFILETYPES=0 0 0

+FILTERAPPCOMMAND=\n\n\n

+vcsproject=SCC:Perforce SCM://depot

+vcslocalpath=SCC:Perforce SCM:c:\

+compile=concur|capture|clear|:Compile:&Compile,dmake %n.obj

+make=concur|capture|clear|saveall|:Build:&Build,dmake install

+rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u

+debug=concur|capture|hide|savenone|:Debug:&Debug,

+execute=hide|savenone|nochangedir|:Execute:E&xecute,

+user1=hide|:User 1:User 1,

+user2=hide|:User 2:User 2,

+usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe

+workingdir=.

+includedirs=%(SCITECH)\include;%(PRIVATE)\include

+reffile=

+[FILES]

+qnx\_mtrrqnx.asm

+qnx\cpuinfo.c

+qnx\event.c

+qnx\mtrrqnx.c

+qnx\oshdr.h

+qnx\pm.c

+qnx\vflat.c

+qnx\ztimer.c

+[ASSOCIATION]

+[CONFIGURATIONS]

diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj
new file mode 100755
index 0000000..1fcf911
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj
@@ -0,0 +1,34 @@
+[SciTech]

+compiler=bc50-

+targetos=vxd

+[COMPILER]

+version=5.0b

+MACRO=enable_current_compiler\n

+activeconfig=,wc10-d32

+FILTERNAME=Source Files\nInclude Files\nAssembler Files\n

+FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n

+FILTERASSOCIATEFILETYPES=0 0 0 

+FILTERAPPCOMMAND=\n\n\n

+vcsproject=SCC:Perforce SCM://depot

+vcslocalpath=SCC:Perforce SCM:c:\

+compile=concur|capture|nochangedir|:Compile:&Compile,dmake %n.obj

+make=concur|capture|clear|saveall|nochangedir|:Build:&Build,dmake install

+rebuild=concur|capture|clear|saveall|nochangedir|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u

+debug=concur|capture|hide|savenone|nochangedir|:Debug:&Debug,

+execute=hide|savenone|nochangedir|:Execute:E&xecute,

+user1=hide|:User 1:User 1,

+user2=hide|:User 2:User 2,

+usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:&Clean Directory,dmake cleanexe

+workingdir=.

+includedirs=%(SCITECH)\include;%(PRIVATE)\include

+reffile=

+[FILES]

+vxd\_pm.asm

+vxd\cpuinfo.c

+vxd\fileio.c

+vxd\oshdr.h

+vxd\pm.c

+vxd\vflat.c

+vxd\ztimer.c

+[ASSOCIATION]

+[CONFIGURATIONS]

diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj
new file mode 100755
index 0000000..ace6822
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj
@@ -0,0 +1,35 @@
+[SciTech]

+compiler=vc60- 

+targetos=c32 

+[COMPILER]

+version=5.0b

+MACRO=enable_current_compiler\n

+activeconfig=,wc10-d32

+FILTERNAME=Source Files\nInclude Files\nAssembler Files\n

+FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n

+FILTERASSOCIATEFILETYPES=0 0 0 

+FILTERAPPCOMMAND=\n\n\n

+vcsproject=SCC:Perforce SCM://depot

+vcslocalpath=SCC:Perforce SCM:c:\

+compile=concur|capture|:Compile:&Compile,dmake %n.obj

+make=concur|capture|clear|saveall|:Build:&Build,dmake install

+rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u

+debug=concur|capture|hide|savenone|:Debug:&Debug,

+execute=hide|savenone|nochangedir|:Execute:E&xecute,

+user1=hide|:User 1:User 1,

+user2=hide|:User 2:User 2,

+usertool_clean_directory=concur|capture|savenone|:Clean Directory:&Clean Directory,dmake cleanexe

+workingdir=.

+includedirs=%(SCITECH)\include;%(PRIVATE)\include

+reffile=

+[FILES]

+win32\_pmwin32.asm

+win32\cpuinfo.c

+win32\ddraw.c

+win32\event.c

+win32\oshdr.h

+win32\pm.c

+win32\vflat.c

+win32\ztimer.c

+[ASSOCIATION]

+[CONFIGURATIONS]

diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm b/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm
new file mode 100755
index 0000000..5a3fe10
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm
@@ -0,0 +1,226 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    NASM
+;* Environment: QNX
+;*
+;* Description: Assembler support routines for the Memory Type Range Register
+;*              (MTRR) module for QNX.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+header      _mtrrqnx                ; Set up memory model
+
+begdataseg  _mtrrqnx                ; Start of code segment
+
+ifdef   USE_NASM
+%define R0_FLUSH_TLB    0
+%define R0_SAVE_CR4     1
+%define R0_RESTORE_CR4  2
+%define R0_READ_MSR     3
+%define R0_WRITE_MSR    4
+else
+R0_FLUSH_TLB        EQU 0
+R0_SAVE_CR4         EQU 1
+R0_RESTORE_CR4      EQU 2
+R0_READ_MSR         EQU 3
+R0_WRITE_MSR        EQU 4
+endif
+
+cpublic _PM_R0
+_PM_R0_service      dd  0
+_PM_R0_reg          dd  0
+_PM_R0_eax          dd  0
+_PM_R0_edx          dd  0
+
+enddataseg  _mtrrqnx                ; Start of code segment
+
+begcodeseg  _mtrrqnx                ; Start of code segment
+
+P586
+
+;----------------------------------------------------------------------------
+; ulong _MTRR_disableInt(void);
+;----------------------------------------------------------------------------
+; Return processor interrupt status and disable interrupts.
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_disableInt
+
+        pushfd                  ; Put flag word on stack
+;       cli                     ; Disable interrupts!
+        pop     eax             ; deposit flag word in return register
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _MTRR_restoreInt(ulong ps);
+;----------------------------------------------------------------------------
+; Restore processor interrupt status.
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_restoreInt
+
+        ARG     ps:ULONG
+
+        push    ebp
+        mov     ebp,esp         ; Set up stack frame
+        push    [ULONG ps]
+        popfd                   ; Restore processor status (and interrupts)
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uchar _MTRR_getCx86(uchar reg);
+;----------------------------------------------------------------------------
+; Read a Cyrix CPU indexed register
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_getCx86
+
+        ARG     reg:UCHAR
+
+        enter_c
+        mov     al,[reg]
+        out     22h,al
+        in      al,23h
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; uchar _MTRR_setCx86(uchar reg,uchar val);
+;----------------------------------------------------------------------------
+; Write a Cyrix CPU indexed register
+;----------------------------------------------------------------------------
+cprocstart  _MTRR_setCx86
+
+        ARG     reg:UCHAR, val:UCHAR
+
+        enter_c
+        mov     al,[reg]
+        out     22h,al
+        mov     al,[val]
+        out     23h,al
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; ulong _PM_ring0_isr(void);
+;----------------------------------------------------------------------------
+; Ring 0 clock interrupt handler that we use to execute the MTRR support
+; code.
+;----------------------------------------------------------------------------
+cprocnear   _PM_ring0_isr
+
+;--------------------------------------------------------
+; void PM_flushTLB(void);
+;--------------------------------------------------------
+        pushad
+        cmp     [DWORD _PM_R0_service],R0_FLUSH_TLB
+        jne     @@1
+        wbinvd                  ; Flush the CPU cache
+        mov     eax,cr3         
+        mov     cr3,eax         ; Flush the TLB
+        jmp     @@Exit
+
+;--------------------------------------------------------
+; ulong _MTRR_saveCR4(void);
+;--------------------------------------------------------
+@@1:    cmp     [DWORD _PM_R0_service],R0_SAVE_CR4
+        jne     @@2
+
+; Save value of CR4 and clear Page Global Enable (bit 7)
+
+        mov     ebx,cr4
+        mov     eax,ebx
+        and     al,7Fh
+        mov     cr4,eax
+
+; Disable and flush caches
+
+        mov     eax,cr0
+        or      eax,40000000h
+        wbinvd
+        mov     cr0,eax
+        wbinvd
+
+; Return value from CR4
+
+        mov     [_PM_R0_reg],ebx
+        jmp     @@Exit
+
+;--------------------------------------------------------
+; void _MTRR_restoreCR4(ulong cr4Val)
+;--------------------------------------------------------
+@@2:    cmp     [DWORD _PM_R0_service],R0_RESTORE_CR4
+        jne     @@3
+
+        mov     eax,cr0
+        and     eax,0BFFFFFFFh
+        mov     cr0,eax
+        mov     eax,[_PM_R0_reg]
+        mov     cr4,eax
+        jmp     @@Exit
+
+;--------------------------------------------------------
+; void _MTRR_readMSR(int reg, ulong FAR *eax, ulong FAR *edx);
+;--------------------------------------------------------
+@@3:    cmp     [DWORD _PM_R0_service],R0_READ_MSR
+        jne     @@4
+
+        mov     ecx,[_PM_R0_reg]
+        rdmsr
+        mov     [_PM_R0_eax],eax
+        mov     [_PM_R0_edx],edx
+        jmp     @@Exit
+
+;--------------------------------------------------------
+; void _MTRR_writeMSR(int reg, ulong eax, ulong edx);
+;--------------------------------------------------------
+@@4:    cmp     [DWORD _PM_R0_service],R0_WRITE_MSR
+        jne     @@Exit
+
+        mov     ecx,[_PM_R0_reg]
+        mov     eax,[_PM_R0_eax]
+        mov     edx,[_PM_R0_edx]
+        wrmsr
+        jmp     @@Exit
+
+@@Exit: mov     [DWORD _PM_R0_service],-1
+        popad
+        mov     eax,0
+        retf
+
+cprocend
+
+endcodeseg  _mtrrqnx
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c
new file mode 100755
index 0000000..a878254
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c
@@ -0,0 +1,64 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX
+*
+* Description:  QNX specific code for the CPU detection module.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+TODO: We should implement this for QNX!
+****************************************************************************/
+#define SetMaxThreadPriority()  0
+
+/****************************************************************************
+REMARKS:
+TODO: We should implement this for QNX!
+****************************************************************************/
+#define RestoreThreadPriority(i)
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    freq->low = CLOCKS_PER_SEC * 1000;
+    freq->high = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)           \
+{                               \
+    (t)->low = clock() * 1000;  \
+    (t)->high = 0;              \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c
new file mode 100755
index 0000000..45cd514
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c
@@ -0,0 +1,601 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX
+*
+* Description:  QNX fullscreen console implementation for the SciTech
+*               cross platform event library.
+*
+****************************************************************************/
+
+#include <errno.h>
+#include <unistd.h>
+
+/*--------------------------- Global variables ----------------------------*/
+
+#ifndef __QNXNTO__
+static struct _mouse_ctrl   *_PM_mouse_ctl;
+static int          _PM_keyboard_fd = -1;
+/*static int            _PM_modifiers, _PM_leds; */
+#else
+static int          kbd_fd = -1, mouse_fd = -1;
+#endif
+static int          kill_pid = 0;
+static ushort       keyUpMsg[256] = {0};/* Table of key up messages     */
+static int          rangeX,rangeY;      /* Range of mouse coordinates   */
+
+#define TIME_TO_MSEC(__t)   ((__t).tv_nsec / 1000000 + (__t).tv_sec * 1000)
+
+#define LED_NUM         1
+#define LED_CAP         2
+#define LED_SCR         4
+
+/* Scancode mappings on QNX for special keys */
+
+typedef struct {
+    int scan;
+    int map;
+    } keymap;
+
+/* TODO: Fix this and set it up so we can do a binary search! */
+
+keymap keymaps[] = {
+    {96, KB_padEnter},
+    {74, KB_padMinus},
+    {78, KB_padPlus},
+    {55, KB_padTimes},
+    {98, KB_padDivide},
+    {71, KB_padHome},
+    {72, KB_padUp},
+    {73, KB_padPageUp},
+    {75, KB_padLeft},
+    {76, KB_padCenter},
+    {77, KB_padRight},
+    {79, KB_padEnd},
+    {80, KB_padDown},
+    {81, KB_padPageDown},
+    {82, KB_padInsert},
+    {83, KB_padDelete},
+    {105,KB_left},
+    {108,KB_down},
+    {106,KB_right},
+    {103,KB_up},
+    {110,KB_insert},
+    {102,KB_home},
+    {104,KB_pageUp},
+    {111,KB_delete},
+    {107,KB_end},
+    {109,KB_pageDown},
+    {125,KB_leftWindows},
+    {126,KB_rightWindows},
+    {127,KB_menu},
+    {100,KB_rightAlt},
+    {97,KB_rightCtrl},
+    };
+
+/* And the keypad with num lock turned on (changes the ASCII code only) */
+
+keymap keypad[] = {
+    {71, ASCII_7},
+    {72, ASCII_8},
+    {73, ASCII_9},
+    {75, ASCII_4},
+    {76, ASCII_5},
+    {77, ASCII_6},
+    {79, ASCII_1},
+    {80, ASCII_2},
+    {81, ASCII_3},
+    {82, ASCII_0},
+    {83, ASCII_period},
+    };
+
+#define NB_KEYMAPS (sizeof(keymaps)/sizeof(keymaps[0]))
+#define NB_KEYPAD (sizeof(keypad)/sizeof(keypad[0]))
+
+/*---------------------------- Implementation -----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Include generic raw scancode keyboard module.
+****************************************************************************/
+#include "common/keyboard.c"
+
+/* These are not used under QNX */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flags)
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{
+    struct timespec t;
+    clock_gettime(CLOCK_REALTIME,&t);
+    return (t.tv_nsec / 1000000 + t.tv_sec * 1000);
+}
+
+/****************************************************************************
+REMARKS:
+Converts a mickey movement value to a pixel adjustment value.
+****************************************************************************/
+static int MickeyToPixel(
+    int mickey)
+{
+    /* TODO: We can add some code in here to handle 'acceleration' for */
+    /*       the mouse cursor. For now just use the mickeys. */
+    return mickey;
+}
+
+#ifdef __QNXNTO__
+/****************************************************************************
+REMARKS:
+Retrieves all events from the mouse/keyboard event queue and stuffs them
+into the MGL event queue for further processing.
+****************************************************************************/
+static void _EVT_pumpMessages(void)
+{
+    int         rc1, rc2;
+    struct _keyboard_packet key;
+    struct _mouse_packet    ms;
+    static long     old_buttons = 0;
+    uint            message = 0, but_stat = 0, mods = 0;
+    event_t         evt;
+
+    while (EVT.count < EVENTQSIZE) {
+	rc1 = read(kbd_fd, (void *)&key, sizeof(key));
+	if (rc1 == -1) {
+	    if (errno == EAGAIN)
+		rc1 = 0;
+	    else {
+		perror("getEvents");
+		PM_fatalError("Keyboard error");
+		}
+	    }
+	if (rc1 > 0) {
+	    memset(&evt, 0, sizeof(evt));
+	    if (key.data.modifiers & KEYMOD_SHIFT)
+		mods |= EVT_LEFTSHIFT;
+	    if (key.data.modifiers & KEYMOD_CTRL)
+		mods |= EVT_CTRLSTATE;
+	    if (key.data.modifiers & KEYMOD_ALT)
+		mods |= EVT_ALTSTATE;
+
+	    /* Now store the keyboard event data */
+	    evt.when = TIME_TO_MSEC(key.time);
+	    if (key.data.flags & KEY_SCAN_VALID)
+		evt.message |= (key.data.key_scan & 0x7F) << 8;
+	    if ((key.data.flags & KEY_SYM_VALID) &&
+		(((key.data.key_sym & 0xff00) == 0xf000 &&
+		(key.data.key_sym & 0xff) < 0x20) ||
+		key.data.key_sym < 0x80))
+		evt.message |= (key.data.key_sym & 0xFF);
+	    evt.modifiers = mods;
+	    if (key.data.flags & KEY_DOWN) {
+		evt.what = EVT_KEYDOWN;
+		keyUpMsg[evt.message >> 8] = (ushort)evt.message;
+		}
+	    else if (key.data.flags & KEY_REPEAT) {
+		evt.message |= 0x10000;
+		evt.what = EVT_KEYREPEAT;
+		}
+	    else {
+		evt.what = EVT_KEYUP;
+		evt.message = keyUpMsg[evt.message >> 8];
+		if (evt.message == 0)
+		    continue;
+		keyUpMsg[evt.message >> 8] = 0;
+		}
+
+	    /* Now add the new event to the event queue */
+	    addEvent(&evt);
+	    }
+	rc2 = read(mouse_fd, (void *)&ms, sizeof (ms));
+	if (rc2 == -1) {
+	    if (errno == EAGAIN)
+		rc2 = 0;
+	    else {
+		perror("getEvents");
+		PM_fatalError("Mouse error");
+		}
+	    }
+	if (rc2 > 0) {
+	    memset(&evt, 0, sizeof(evt));
+	    ms.hdr.buttons &=
+		(_POINTER_BUTTON_LEFT | _POINTER_BUTTON_RIGHT);
+	    if (ms.hdr.buttons & _POINTER_BUTTON_LEFT)
+		but_stat = EVT_LEFTBUT;
+	    if ((ms.hdr.buttons & _POINTER_BUTTON_LEFT) !=
+		(old_buttons & _POINTER_BUTTON_LEFT))
+		message = EVT_LEFTBMASK;
+	    if (ms.hdr.buttons & _POINTER_BUTTON_RIGHT)
+		but_stat |= EVT_RIGHTBUT;
+	    if ((ms.hdr.buttons & _POINTER_BUTTON_RIGHT) !=
+		(old_buttons & _POINTER_BUTTON_RIGHT))
+		message |= EVT_RIGHTBMASK;
+	    if (ms.dx || ms.dy) {
+		ms.dy = -ms.dy;
+		EVT.mx += MickeyToPixel(ms.dx);
+		EVT.my += MickeyToPixel(ms.dy);
+		if (EVT.mx < 0) EVT.mx = 0;
+		if (EVT.my < 0) EVT.my = 0;
+		if (EVT.mx > rangeX)    EVT.mx = rangeX;
+		if (EVT.my > rangeY)    EVT.my = rangeY;
+		evt.what = EVT_MOUSEMOVE;
+		evt.when = TIME_TO_MSEC(ms.hdr.time);
+		evt.where_x = EVT.mx;
+		evt.where_y = EVT.my;
+		evt.relative_x = ms.dx;
+		evt.relative_y = ms.dy;
+		evt.modifiers = but_stat;
+		addEvent(&evt);
+		}
+	    evt.what = ms.hdr.buttons < old_buttons ?
+		EVT_MOUSEUP : EVT_MOUSEDOWN;
+	    evt.when = TIME_TO_MSEC(ms.hdr.time);
+	    evt.where_x = EVT.mx;
+	    evt.where_y = EVT.my;
+	    evt.relative_x = ms.dx;
+	    evt.relative_y = ms.dy;
+	    evt.modifiers = but_stat;
+	    evt.message = message;
+	    if (ms.hdr.buttons != old_buttons) {
+		addEvent(&evt);
+		old_buttons = ms.hdr.buttons;
+		}
+	    }
+	if (rc1 + rc2 == 0)
+	    break;
+	}
+}
+#else
+/****************************************************************************
+REMARKS:
+Retrieves all events from the mouse/keyboard event queue and stuffs them
+into the MGL event queue for further processing.
+****************************************************************************/
+static void _EVT_pumpMessages(void)
+{
+    struct mouse_event      ev;
+    int             rc;
+    static long         old_buttons = 0;
+    uint                message = 0, but_stat = 0;
+    event_t             evt;
+    char                buf[32];
+    int             numkeys, i;
+
+    /* Poll keyboard events */
+    while ((numkeys = read(_PM_keyboard_fd, buf, sizeof buf)) > 0) {
+	for (i = 0; i < numkeys; i++) {
+	    processRawScanCode(buf[i]);
+	    }
+	}
+
+    if (_PM_mouse_ctl == NULL)
+	return;
+
+    /* Gobble pending mouse events */
+    while (EVT.count < EVENTQSIZE) {
+	rc = mouse_read(_PM_mouse_ctl, &ev, 1, 0, NULL);
+	if (rc == -1) {
+	    perror("getEvents");
+	    PM_fatalError("Mouse error (Input terminated?)");
+	    }
+	if (rc == 0)
+	    break;
+
+	message = 0, but_stat = 0;
+	memset(&evt, 0, sizeof(evt));
+
+	ev.buttons &= (_MOUSE_LEFT | _MOUSE_RIGHT);
+	if (ev.buttons & _MOUSE_LEFT)
+	    but_stat = EVT_LEFTBUT;
+	if ((ev.buttons & _MOUSE_LEFT) != (old_buttons & _MOUSE_LEFT))
+	    message = EVT_LEFTBMASK;
+	if (ev.buttons & _MOUSE_RIGHT)
+	    but_stat |= EVT_RIGHTBUT;
+	if ((ev.buttons & _MOUSE_RIGHT) != (old_buttons & _MOUSE_RIGHT))
+	    message |= EVT_RIGHTBMASK;
+	if (ev.dx || ev.dy) {
+	    ev.dy = -ev.dy;
+	    EVT.mx += MickeyToPixel(ev.dx);
+	    EVT.my += MickeyToPixel(ev.dy);
+	    if (EVT.mx < 0) EVT.mx = 0;
+	    if (EVT.my < 0) EVT.my = 0;
+	    if (EVT.mx > rangeX)    EVT.mx = rangeX;
+	    if (EVT.my > rangeY)    EVT.my = rangeY;
+	    evt.what = EVT_MOUSEMOVE;
+	    evt.when = ev.timestamp*100;
+	    evt.where_x = EVT.mx;
+	    evt.where_y = EVT.my;
+	    evt.relative_x = ev.dx;
+	    evt.relative_y = ev.dy;
+	    evt.modifiers = but_stat;
+	    addEvent(&evt);
+	    }
+	evt.what = ev.buttons < old_buttons ? EVT_MOUSEUP : EVT_MOUSEDOWN;
+	evt.when = ev.timestamp*100;
+	evt.where_x = EVT.mx;
+	evt.where_y = EVT.my;
+	evt.relative_x = ev.dx;
+	evt.relative_y = ev.dy;
+	evt.modifiers = but_stat;
+	evt.message = message;
+	if (ev.buttons != old_buttons) {
+	    addEvent(&evt);
+	    old_buttons = ev.buttons;
+	    }
+	}
+}
+#endif  /* __QNXNTO__ */
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort(
+    int signo)
+{
+    char    buf[80];
+
+    EVT_exit();
+    sprintf(buf,"Terminating on signal %d",signo);
+    PM_fatalError(buf);
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    int         i;
+    struct stat st;
+    char        *iarg[16];
+#ifdef __QNXNTO__
+    char        buf[128];
+    FILE        *p;
+    int         argno,len;
+#endif
+
+#ifdef __QNXNTO__
+    ThreadCtl(_NTO_TCTL_IO, 0); /* So joystick code won't blow up */
+#endif
+
+    /* Initialise the event queue */
+    EVT.mouseMove = mouseMove;
+    initEventQueue();
+    memset(keyUpMsg,0,sizeof(keyUpMsg));
+
+#ifdef __QNXNTO__
+    /*
+     * User may already have input running with the right parameters.
+     * Thus they could start input at boot time, using the output of
+     * inputtrap, passing the the -r flag to make it run as a resource
+     * manager.
+     */
+    if ((mouse_fd = open("/dev/mouse0", O_RDONLY | O_NONBLOCK)) < 0) {
+	/* Run inputtrap to get the args for input */
+	if ((p = popen("inputtrap", "r")) == NULL)
+	    PM_fatalError("Error running 'inputtrap'");
+	fgets(buf, sizeof(buf), p);
+	pclose(p);
+
+	/* Build the argument list */
+	len = strlen(buf);
+	iarg[0] = buf;
+	for (i = 0, argno = 0; i < len && argno < 15;) {
+	    if (argno == 1) {
+		/*
+		 * Add flags to input's arg list.
+		 * '-r' means run as resource
+		 * manager, providing the /dev/mouse
+		 * and /dev/keyboard interfaces.
+		 * '-P' supresses the /dev/photon
+		 * mechanism.
+		 */
+		iarg[argno++] = "-Pr";
+		continue;
+		}
+	    while (buf[i] == ' ')
+		i++;
+	    if (buf[i] == '\0' || buf[i] == '\n')
+		break;
+	    iarg[argno++] = &buf[i];
+	    while (buf[i] != ' '
+		&& buf[i] != '\0' && buf[i] != '\n')
+		i++;
+	    buf[i++] = '\0';
+	    }
+	iarg[argno] = NULL;
+
+	if ((kill_pid = spawnvp(P_NOWAITO, iarg[0], iarg)) == -1) {
+	    perror("spawning input resmgr");
+	    PM_fatalError("Could not start input resmgr");
+	    }
+	for (i = 0; i < 10; i++) {
+	    if (stat("/dev/mouse0", &st) == 0)
+		break;
+	    sleep(1);
+	    }
+	if ((mouse_fd = open("/dev/mouse0", O_RDONLY|O_NONBLOCK)) < 0) {
+	    perror("/dev/mouse0");
+	    PM_fatalError("Could not open /dev/mouse0");
+	    }
+	}
+    if ((kbd_fd = open("/dev/keyboard0", O_RDONLY|O_NONBLOCK)) < 0) {
+	perror("/dev/keyboard0");
+	PM_fatalError("Could not open /dev/keyboard0");
+	}
+#else
+    /* Connect to Input/Mouse for event handling */
+    if (_PM_mouse_ctl == NULL) {
+	_PM_mouse_ctl = mouse_open(0, "/dev/mouse", 0);
+
+	/* "Mouse" is not running; attempt to start it */
+	if (_PM_mouse_ctl == NULL) {
+	    iarg[0] = "mousetrap";
+	    iarg[1] = "start";
+	    iarg[2] = NULL;
+	    if ((kill_pid = spawnvp(P_NOWAITO, iarg[0], (void*)iarg)) == -1)
+		perror("spawn (mousetrap)");
+	    else {
+		for (i = 0; i < 10; i++) {
+		    if (stat("/dev/mouse", &st) == 0)
+			break;
+		    sleep(1);
+		    }
+		_PM_mouse_ctl = mouse_open(0, "/dev/mouse", 0);
+		}
+	    }
+	}
+    if (_PM_keyboard_fd == -1)
+	_PM_keyboard_fd = open("/dev/kbd", O_RDONLY|O_NONBLOCK);
+#endif
+
+    /* Catch program termination signals so we can clean up properly */
+    signal(SIGABRT, _EVT_abort);
+    signal(SIGFPE, _EVT_abort);
+    signal(SIGINT, _EVT_abort);
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    rangeX = xRes;
+    rangeY = yRes;
+}
+
+/****************************************************************************
+REMARKS
+Modifes the mouse coordinates as necessary if scaling to OS coordinates,
+and sets the OS mouse cursor position.
+****************************************************************************/
+#define _EVT_setMousePos(x,y)
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for QNX */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for QNX */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+#ifdef __QNXNTO__
+    char    c;
+    int flags;
+
+    if (kbd_fd != -1) {
+	close(kbd_fd);
+	kbd_fd = -1;
+	}
+    if (mouse_fd != -1) {
+	close(mouse_fd);
+	mouse_fd = -1;
+	}
+#endif
+
+    /* Restore signal handlers */
+    signal(SIGABRT, SIG_DFL);
+    signal(SIGFPE, SIG_DFL);
+    signal(SIGINT, SIG_DFL);
+
+#ifndef __QNXNTO__
+    /* Kill the Input/Mouse driver if we have spawned it */
+    if (_PM_mouse_ctl != NULL) {
+	struct _fd_entry    fde;
+	uint            pid = 0;
+
+	/* Find out the pid of the mouse driver */
+	if (kill_pid > 0) {
+	    if (qnx_fd_query(0,
+		0, _PM_mouse_ctl->fd, &fde) != -1)
+		pid = fde.pid;
+	    }
+	mouse_close(_PM_mouse_ctl);
+	_PM_mouse_ctl = NULL;
+
+	if (pid > 0) {
+	    /* For some reasons the PID's are different under QNX4,
+	     * so we use the old mechanism to kill the mouse server.
+	     */
+	    kill(pid, SIGTERM);
+	    kill_pid = 0;
+	    }
+	}
+#endif
+    if (kill_pid > 0) {
+	kill(kill_pid, SIGTERM);
+	kill_pid = 0;
+	}
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c
new file mode 100755
index 0000000..f960c75
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c
@@ -0,0 +1,182 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX
+*
+* Description:  MTRR helper functions module. To make it easier to implement
+*               the MTRR support under QNX, we simply put our ring 0 helper
+*               functions into stubs that run them at ring 0 using whatever
+*               mechanism is available.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include <stdio.h>
+#include <sys/mman.h>
+#include <time.h>
+#ifdef __QNXNTO__
+#include <sys/neutrino.h>
+#include <sys/syspage.h>
+#else
+#include <i86.h>
+#include <sys/irqinfo.h>
+#endif
+
+/*--------------------------- Global variables ----------------------------*/
+
+#define R0_FLUSH_TLB    0
+#define R0_SAVE_CR4     1
+#define R0_RESTORE_CR4  2
+#define R0_READ_MSR     3
+#define R0_WRITE_MSR    4
+
+typedef struct {
+    int     service;
+    int     reg;
+    ulong   eax;
+    ulong   edx;
+    } R0_data;
+
+extern volatile R0_data _PM_R0;
+
+/*----------------------------- Implementation ----------------------------*/
+
+#ifdef __QNXNTO__
+const struct sigevent * _ASMAPI _PM_ring0_isr(void *arg, int id);
+#else
+pid_t far _ASMAPI _PM_ring0_isr();
+#endif
+
+/****************************************************************************
+REMARKS:
+Return true if ring 0 (or if we can call the helpers functions at ring 0)
+****************************************************************************/
+ibool _ASMAPI _MTRR_isRing0(void)
+{
+#ifdef __QNXNTO__
+    return false;   /* Not implemented yet! */
+#else
+    return true;
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Function to execute a service at ring 0. This is done using the clock
+interrupt handler since the code we attach to it will always run at ring 0.
+****************************************************************************/
+static void CallRing0(void)
+{
+#ifdef __QNXNTO__
+    uint    clock_intno = SYSPAGE_ENTRY(qtime)->intr;
+#else
+    uint    clock_intno = 0;    /* clock irq */
+#endif
+    int     intrid;
+
+#ifdef __QNXNTO__
+    mlock((void*)&_PM_R0, sizeof(_PM_R0));
+    ThreadCtl(_NTO_TCTL_IO, 0);
+#endif
+#ifdef __QNXNTO__
+    if ((intrid = InterruptAttach(_NTO_INTR_CLASS_EXTERNAL | clock_intno,
+	_PM_ring0_isr, (void*)&_PM_R0, sizeof(_PM_R0), _NTO_INTR_FLAGS_END)) == -1) {
+#else
+    if ((intrid = qnx_hint_attach(clock_intno, _PM_ring0_isr, FP_SEG(&_PM_R0))) == -1) {
+#endif
+	perror("Attach");
+	exit(-1);
+	}
+    while (_PM_R0.service != -1)
+	;
+#ifdef __QNXNTO__
+    InterruptDetachId(intrid);
+#else
+    qnx_hint_detach(intrid);
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Flush the translation lookaside buffer.
+****************************************************************************/
+void PMAPI PM_flushTLB(void)
+{
+    _PM_R0.service = R0_FLUSH_TLB;
+    CallRing0();
+}
+
+/****************************************************************************
+REMARKS:
+Read and return the value of the CR4 register
+****************************************************************************/
+ulong _ASMAPI _MTRR_saveCR4(void)
+{
+    _PM_R0.service = R0_SAVE_CR4;
+    CallRing0();
+    return _PM_R0.reg;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the value of the CR4 register
+****************************************************************************/
+void _ASMAPI _MTRR_restoreCR4(ulong cr4Val)
+{
+    _PM_R0.service = R0_RESTORE_CR4;
+    _PM_R0.reg = cr4Val;
+    CallRing0();
+}
+
+/****************************************************************************
+REMARKS:
+Read a machine status register for the CPU.
+****************************************************************************/
+void _ASMAPI _MTRR_readMSR(
+    int reg,
+    ulong *eax,
+    ulong *edx)
+{
+    _PM_R0.service = R0_READ_MSR;
+    _PM_R0.reg = reg;
+    CallRing0();
+    *eax = _PM_R0.eax;
+    *edx = _PM_R0.edx;
+}
+
+/****************************************************************************
+REMARKS:
+Write a machine status register for the CPU.
+****************************************************************************/
+void _ASMAPI _MTRR_writeMSR(
+    int reg,
+    ulong eax,
+    ulong edx)
+{
+    _PM_R0.service = R0_WRITE_MSR;
+    _PM_R0.reg = reg;
+    _PM_R0.eax = eax;
+    _PM_R0.edx = edx;
+    CallRing0();
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h
new file mode 100755
index 0000000..0961193
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h
@@ -0,0 +1,103 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <process.h>
+#include <time.h>
+#ifndef __QNXNTO__
+#include <sys/mouse.h>
+#include <sys/keyboard.h>
+#include <sys/fd.h>
+#include <conio.h>
+#else
+#include <sys/dcmd_input.h>
+
+/* Things 'borrowed' from photon/keycodes.h */
+
+/*
+ * Keyboard modifiers
+ */
+#define KEYMODBIT_SHIFT                                         0
+#define KEYMODBIT_CTRL                                          1
+#define KEYMODBIT_ALT                                           2
+#define KEYMODBIT_ALTGR                                         3
+#define KEYMODBIT_SHL3                                          4
+#define KEYMODBIT_MOD6                                          5
+#define KEYMODBIT_MOD7                                          6
+#define KEYMODBIT_MOD8                                          7
+
+#define KEYMODBIT_SHIFT_LOCK                                    8
+#define KEYMODBIT_CTRL_LOCK                                     9
+#define KEYMODBIT_ALT_LOCK                                      10
+#define KEYMODBIT_ALTGR_LOCK                                    11
+#define KEYMODBIT_SHL3_LOCK                                     12
+#define KEYMODBIT_MOD6_LOCK                                     13
+#define KEYMODBIT_MOD7_LOCK                                     14
+#define KEYMODBIT_MOD8_LOCK                                     15
+
+#define KEYMODBIT_CAPS_LOCK                                     16
+#define KEYMODBIT_NUM_LOCK                                      17
+#define KEYMODBIT_SCROLL_LOCK                                   18
+
+#define KEYMOD_SHIFT                                            (1 << KEYMODBIT_SHIFT)
+#define KEYMOD_CTRL                                             (1 << KEYMODBIT_CTRL)
+#define KEYMOD_ALT                                              (1 << KEYMODBIT_ALT)
+#define KEYMOD_ALTGR                                            (1 << KEYMODBIT_ALTGR)
+#define KEYMOD_SHL3                                             (1 << KEYMODBIT_SHL3)
+#define KEYMOD_MOD6                                             (1 << KEYMODBIT_MOD6)
+#define KEYMOD_MOD7                                             (1 << KEYMODBIT_MOD7)
+#define KEYMOD_MOD8                                             (1 << KEYMODBIT_MOD8)
+
+#define KEYMOD_SHIFT_LOCK                                       (1 << KEYMODBIT_SHIFT_LOCK)
+#define KEYMOD_CTRL_LOCK                                        (1 << KEYMODBIT_CTRL_LOCK)
+#define KEYMOD_ALT_LOCK                                         (1 << KEYMODBIT_ALT_LOCK)
+#define KEYMOD_ALTGR_LOCK                                       (1 << KEYMODBIT_ALTGR_LOCK)
+#define KEYMOD_SHL3_LOCK                                        (1 << KEYMODBIT_SHL3_LOCK)
+#define KEYMOD_MOD6_LOCK                                        (1 << KEYMODBIT_MOD6_LOCK)
+#define KEYMOD_MOD7_LOCK                                        (1 << KEYMODBIT_MOD7_LOCK)
+#define KEYMOD_MOD8_LOCK                                        (1 << KEYMODBIT_MOD8_LOCK)
+
+#define KEYMOD_CAPS_LOCK                                        (1 << KEYMODBIT_CAPS_LOCK)
+#define KEYMOD_NUM_LOCK                                         (1 << KEYMODBIT_NUM_LOCK)
+#define KEYMOD_SCROLL_LOCK                                      (1 << KEYMODBIT_SCROLL_LOCK)
+
+/*
+ * Keyboard flags
+ */
+#define KEY_DOWN                                                0x00000001      /* Key was pressed down */
+#define KEY_REPEAT                                              0x00000002      /* Key was repeated */
+#define KEY_SCAN_VALID                                          0x00000020      /* Scancode is valid */
+#define KEY_SYM_VALID                                           0x00000040      /* Key symbol is valid */
+#define KEY_CAP_VALID                                           0x00000080      /* Key cap is valid */
+#define KEY_DEAD                                                0x40000000      /* Key symbol is a DEAD key */
+#define KEY_OEM_CAP                                             0x80000000      /* Key cap is an OEM scan code from keyboard */
+
+#endif  /* __QNXNTO__ */
diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c
new file mode 100755
index 0000000..c993ee0
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c
@@ -0,0 +1,891 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "mtrr.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+#include <termios.h>
+#include <fcntl.h>
+#include <malloc.h>
+#include <sys/mman.h>
+#include "qnx/vbios.h"
+#ifndef __QNXNTO__
+#include <sys/seginfo.h>
+#include <sys/console.h>
+#include <conio.h>
+#include <i86.h>
+#else
+#include <sys/neutrino.h>
+#include <sys/dcmd_chr.h>
+#endif
+
+/*--------------------------- Global variables ----------------------------*/
+
+static uint VESABuf_len = 1024;     /* Length of the VESABuf buffer     */
+static void *VESABuf_ptr = NULL;    /* Near pointer to VESABuf          */
+static uint VESABuf_rseg;           /* Real mode segment of VESABuf     */
+static uint VESABuf_roff;           /* Real mode offset of VESABuf      */
+static VBIOSregs_t  *VRegs = NULL;  /* Pointer to VBIOS registers       */
+static int raw_count = 0;
+static struct _console_ctrl *cc = NULL;
+static int console_count = 0;
+static int rmbuf_inuse = 0;
+
+static void (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+void PMAPI PM_init(void)
+{
+    char *force;
+
+    if (VRegs == NULL) {
+#ifdef  __QNXNTO__
+	ThreadCtl(_NTO_TCTL_IO, 0); /* Get IO privilidge */
+#endif
+	force = getenv("VBIOS_METHOD");
+	VRegs = VBIOSinit(force ? atoi(force) : 0);
+	}
+#ifndef  __QNXNTO__
+    MTRR_init();
+#endif
+}
+
+ibool PMAPI PM_haveBIOSAccess(void)
+{ return VRegs != NULL; }
+
+long PMAPI PM_getOSType(void)
+{ return _OS_QNX; }
+
+int PMAPI PM_getModeType(void)
+{ return PM_386; }
+
+void PMAPI PM_backslash(char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '/') {
+	s[pos] = '/';
+	s[pos+1] = '\0';
+	}
+}
+
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+void PMAPI PM_fatalError(const char *msg)
+{
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+    fprintf(stderr,"%s\n", msg);
+    exit(1);
+}
+
+static void ExitVBEBuf(void)
+{
+    if (VESABuf_ptr)
+	PM_freeRealSeg(VESABuf_ptr);
+    VESABuf_ptr = 0;
+}
+
+void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff)
+{
+    if (!VESABuf_ptr) {
+	/* Allocate a global buffer for communicating with the VESA VBE */
+	if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL)
+	    return NULL;
+	atexit(ExitVBEBuf);
+	}
+    *len = VESABuf_len;
+    *rseg = VESABuf_rseg;
+    *roff = VESABuf_roff;
+    return VESABuf_ptr;
+}
+
+static int term_raw(void)
+{
+    struct termios  termios_p;
+
+    if (raw_count++ > 0)
+	return 0;
+
+    /* Go into "raw" input mode */
+    if (tcgetattr(STDIN_FILENO, &termios_p))
+	return -1;
+
+    termios_p.c_cc[VMIN] =  1;
+    termios_p.c_cc[VTIME] =  0;
+    termios_p.c_lflag &= ~( ECHO|ICANON|ISIG|ECHOE|ECHOK|ECHONL);
+    tcsetattr(STDIN_FILENO, TCSADRAIN, &termios_p);
+    return 0;
+}
+
+static void term_restore(void)
+{
+    struct termios  termios_p;
+
+    if (raw_count-- != 1)
+	return;
+
+    tcgetattr(STDIN_FILENO, &termios_p);
+    termios_p.c_lflag |= (ECHO|ICANON|ISIG|ECHOE|ECHOK|ECHONL);
+    termios_p.c_oflag |= (OPOST);
+    tcsetattr(STDIN_FILENO, TCSADRAIN, &termios_p);
+}
+
+int PMAPI PM_kbhit(void)
+{
+    int blocking, c;
+
+    if (term_raw() == -1)
+	return 0;
+
+    /* Go into non blocking mode */
+    blocking = fcntl(STDIN_FILENO, F_GETFL) | O_NONBLOCK;
+    fcntl(STDIN_FILENO, F_SETFL, blocking);
+    c = getc(stdin);
+
+    /* restore blocking mode */
+    fcntl(STDIN_FILENO, F_SETFL, blocking & ~O_NONBLOCK);
+    term_restore();
+    if (c != EOF) {
+	ungetc(c, stdin);
+	return c;
+	}
+    clearerr(stdin);
+    return 0;
+}
+
+int PMAPI PM_getch(void)
+{
+    int c;
+
+    if (term_raw() == -1)
+	return (0);
+    c = getc(stdin);
+#if defined(__QNX__) && !defined(__QNXNTO__)
+    if (c == 0xA)
+	c = 0x0D;
+    else if (c == 0x7F)
+	c = 0x08;
+#endif
+    term_restore();
+    return c;
+}
+
+PM_HWND PMAPI PM_openConsole(
+    PM_HWND hwndUser,
+    int device,
+    int xRes,
+    int yRes,
+    int bpp,
+    ibool fullScreen)
+{
+#ifndef __QNXNTO__
+    int fd;
+
+    if (console_count++)
+	return 0;
+    if ((fd = open("/dev/con1", O_RDWR)) == -1)
+	return -1;
+    cc = console_open(fd, O_RDWR);
+    close(fd);
+    if (cc == NULL)
+	return -1;
+#endif
+    return 1;
+}
+
+int PMAPI PM_getConsoleStateSize(void)
+{
+    return PM_getVGAStateSize() + sizeof(int) * 3;
+}
+
+void PMAPI PM_saveConsoleState(void *stateBuf,int console_id)
+{
+#ifdef __QNXNTO__
+    int     fd;
+    int     flags;
+
+    if ((fd = open("/dev/con1", O_RDWR)) == -1)
+	return;
+    flags = _CONCTL_INVISIBLE_CHG | _CONCTL_INVISIBLE;
+    devctl(fd, DCMD_CHR_SERCTL, &flags, sizeof flags, 0);
+    close(fd);
+#else
+    uchar   *buf = &((uchar*)stateBuf)[PM_getVGAStateSize()];
+
+    /* Save QNX 4 console state */
+    console_read(cc, -1, 0, NULL, 0,
+	(int *)buf+1, (int *)buf+2, NULL);
+    *(int *)buf = console_ctrl(cc, -1,
+	CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE,
+	CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE);
+
+    /* Save state of VGA registers */
+    PM_saveVGAState(stateBuf);
+#endif
+}
+
+void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags))
+{
+    /* TODO: Implement support for console switching if possible */
+}
+
+void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole)
+{
+#ifdef __QNXNTO__
+    int     fd;
+    int     flags;
+
+    if ((fd = open("/dev/con1", O_RDWR)) == -1)
+	return;
+    flags = _CONCTL_INVISIBLE_CHG;
+    devctl(fd, DCMD_CHR_SERCTL, &flags, sizeof flags, 0);
+    close(fd);
+#else
+    uchar   *buf = &((uchar*)stateBuf)[PM_getVGAStateSize()];
+
+    /* Restore the state of the VGA compatible registers */
+    PM_restoreVGAState(stateBuf);
+
+    /* Restore QNX 4 console state */
+    console_ctrl(cc, -1, *(int *)buf,
+	CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE);
+    console_write(cc, -1, 0, NULL, 0,
+	(int *)buf+1, (int *)buf+2, NULL);
+#endif
+}
+
+void PMAPI PM_closeConsole(PM_HWND hwndConsole)
+{
+#ifndef __QNXNTO__
+    if (--console_count == 0) {
+	console_close(cc);
+	cc = NULL;
+	}
+#endif
+}
+
+void PM_setOSCursorLocation(int x,int y)
+{
+    if (!cc)
+	return;
+#ifndef __QNXNTO__
+    console_write(cc, -1, 0, NULL, 0, &y, &x, NULL);
+#endif
+}
+
+void PM_setOSScreenWidth(int width,int height)
+{
+}
+
+ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency)
+{
+    /* TODO: Implement this for QNX */
+    return false;
+}
+
+void PMAPI PM_setRealTimeClockFrequency(int frequency)
+{
+    /* TODO: Implement this for QNX */
+}
+
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    /* TODO: Implement this for QNX */
+}
+
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    return getcwd(path,maxLen);
+}
+
+char PMAPI PM_getBootDrive(void)
+{ return '/'; }
+
+const char * PMAPI PM_getVBEAFPath(void)
+{ return PM_getNucleusConfigPath(); }
+
+const char * PMAPI PM_getNucleusPath(void)
+{
+    char *env = getenv("NUCLEUS_PATH");
+#ifdef __QNXNTO__
+#ifdef __X86__
+    return env ? env : "/nto/scitech/x86/bin";
+#elif defined (__PPC__)
+    return env ? env : "/nto/scitech/ppcbe/bin";
+#elif defined (__MIPS__)
+#ifdef __BIGENDIAN__
+    return env ? env : "/nto/scitech/mipsbe/bin";
+#else
+    return env ? env : "/nto/scitech/mipsle/bin";
+#endif
+#elif defined (__SH__)
+#ifdef __BIGENDIAN__
+    return env ? env : "/nto/scitech/shbe/bin";
+#else
+    return env ? env : "/nto/scitech/shle/bin";
+#endif
+#elif defined (__ARM__)
+    return env ? env : "/nto/scitech/armle/bin";
+#endif
+#else   /* QNX 4 */
+    return env ? env : "/qnx4/scitech/bin";
+#endif
+}
+
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[512];
+    char        *env;
+#ifdef __QNXNTO__
+    char temp[64];
+    gethostname(temp, sizeof (temp));
+    temp[sizeof (temp) - 1] = '\0';     /* Paranoid */
+    sprintf(path,"/etc/config/scitech/%s/config", temp);
+#else
+    sprintf(path,"/etc/config/scitech/%d/config", getnid());
+#endif
+    if ((env = getenv("NUCLEUS_PATH")) != NULL) {
+	strcpy(path,env);
+	PM_backslash(path);
+	strcat(path,"config");
+	}
+    return path;
+}
+
+const char * PMAPI PM_getUniqueID(void)
+{
+    static char buf[128];
+#ifdef __QNXNTO__
+    gethostname(buf, sizeof (buf));
+#else
+    sprintf(buf,"node%d", getnid());
+#endif
+    return buf;
+}
+
+const char * PMAPI PM_getMachineName(void)
+{
+    static char buf[128];
+#ifdef __QNXNTO__
+    gethostname(buf, sizeof (buf));
+#else
+    sprintf(buf,"node%d", getnid());
+#endif
+    return buf;
+}
+
+void * PMAPI PM_getBIOSPointer(void)
+{
+    return PM_mapRealPointer(0, 0x400);
+}
+
+void * PMAPI PM_getA0000Pointer(void)
+{
+    static void *ptr = NULL;
+    void *freeptr;
+    unsigned offset, i, maplen;
+
+    if (ptr != NULL)
+	return ptr;
+
+    /* Some trickery is required to get the linear address 64K aligned */
+    for (i = 0; i < 5; i++) {
+	ptr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true);
+	offset = 0x10000 - ((unsigned)ptr % 0x10000);
+	if (!offset)
+	    break;
+	munmap(ptr, 0x10000);
+	maplen = 0x10000 + offset;
+	freeptr = PM_mapPhysicalAddr(0xA0000-offset, maplen-1,true);
+	ptr = (void *)(offset + (unsigned)freeptr);
+	if (0x10000 - ((unsigned)ptr % 0x10000))
+	    break;
+	munmap(freeptr, maplen);
+	}
+    if (i == 5) {
+	printf("Could not get a 64K aligned linear address for A0000 region\n");
+	exit(1);
+	}
+    return ptr;
+}
+
+void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{
+    uchar_t *p;
+    unsigned o;
+    unsigned prot = PROT_READ|PROT_WRITE|(isCached?0:PROT_NOCACHE);
+#ifdef __PAGESIZE
+    int pagesize = __PAGESIZE;
+#else
+    int pagesize = 4096;
+#endif
+    int rounddown = base % pagesize;
+#ifndef __QNXNTO__
+    static int __VidFD = -1;
+#endif
+
+    if (rounddown) {
+	if (base < rounddown)
+	    return NULL;
+	base -= rounddown;
+	limit += rounddown;
+	}
+
+#ifndef __QNXNTO__
+    if (__VidFD < 0) {
+	if ((__VidFD = shm_open( "Physical", O_RDWR, 0777 )) == -1) {
+	    perror( "Cannot open Physical memory" );
+	    exit(1);
+	    }
+	}
+    o = base & 0xFFF;
+    limit = (limit + o + 0xFFF) & ~0xFFF;
+    if ((int)(p = mmap( 0, limit, prot, MAP_SHARED,
+	    __VidFD, base )) == -1 ) {
+	return NULL;
+	}
+    p += o;
+#else
+    if ((p = mmap(0, limit, prot, MAP_PHYS | MAP_SHARED,
+	    NOFD, base)) == MAP_FAILED) {
+	return (void *)-1;
+	}
+#endif
+    return (p + rounddown);
+}
+
+void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit)
+{
+    munmap(ptr,limit+1);
+}
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{
+    /* TODO: This function should find the physical address of a linear */
+    /*       address. */
+    return 0xFFFFFFFFUL;
+}
+
+ibool PMAPI PM_getPhysicalAddrRange(
+    void *p,
+    ulong length,
+    ulong *physAddress)
+{
+    /* TODO: Implement this! */
+    return false;
+}
+
+void PMAPI PM_sleep(ulong milliseconds)
+{
+    /* TODO: Put the process to sleep for milliseconds */
+}
+
+int PMAPI PM_getCOMPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	}
+    return 0;
+}
+
+int PMAPI PM_getLPTPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+void * PMAPI PM_mallocShared(long size)
+{
+    return PM_malloc(size);
+}
+
+void PMAPI PM_freeShared(void *ptr)
+{
+    PM_free(ptr);
+}
+
+void * PMAPI PM_mapToProcess(void *base,ulong limit)
+{ return (void*)base; }
+
+void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off)
+{
+    void *p;
+
+    PM_init();
+
+    if ((p = VBIOSgetmemptr(r_seg, r_off, VRegs)) == (void *)-1)
+	return NULL;
+    return p;
+}
+
+void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off)
+{
+    if (size > 1024) {
+	printf("PM_allocRealSeg: can't handle %d bytes\n", size);
+	return 0;
+	}
+    if (rmbuf_inuse != 0) {
+	printf("PM_allocRealSeg: transfer area already in use\n");
+	return 0;
+	}
+    PM_init();
+    rmbuf_inuse = 1;
+    *r_seg = VBIOS_TransBufVSeg(VRegs);
+    *r_off = VBIOS_TransBufVOff(VRegs);
+    return (void*)VBIOS_TransBufPtr(VRegs);
+}
+
+void PMAPI PM_freeRealSeg(void *mem)
+{
+    if (rmbuf_inuse == 0) {
+	printf("PM_freeRealSeg: nothing was allocated\n");
+	return;
+	}
+    rmbuf_inuse = 0;
+}
+
+void PMAPI DPMI_int86(int intno, DPMI_regs *regs)
+{
+    PM_init();
+    if (VRegs == NULL)
+	return;
+
+    VRegs->l.eax = regs->eax;
+    VRegs->l.ebx = regs->ebx;
+    VRegs->l.ecx = regs->ecx;
+    VRegs->l.edx = regs->edx;
+    VRegs->l.esi = regs->esi;
+    VRegs->l.edi = regs->edi;
+
+    VBIOSint(intno, VRegs, 1024);
+
+    regs->eax = VRegs->l.eax;
+    regs->ebx = VRegs->l.ebx;
+    regs->ecx = VRegs->l.ecx;
+    regs->edx = VRegs->l.edx;
+    regs->esi = VRegs->l.esi;
+    regs->edi = VRegs->l.edi;
+    regs->flags = VRegs->w.flags & 0x1;
+}
+
+int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out)
+{
+    PM_init();
+    if (VRegs == NULL)
+	return 0;
+
+    VRegs->l.eax = in->e.eax;
+    VRegs->l.ebx = in->e.ebx;
+    VRegs->l.ecx = in->e.ecx;
+    VRegs->l.edx = in->e.edx;
+    VRegs->l.esi = in->e.esi;
+    VRegs->l.edi = in->e.edi;
+
+    VBIOSint(intno, VRegs, 1024);
+
+    out->e.eax = VRegs->l.eax;
+    out->e.ebx = VRegs->l.ebx;
+    out->e.ecx = VRegs->l.ecx;
+    out->e.edx = VRegs->l.edx;
+    out->e.esi = VRegs->l.esi;
+    out->e.edi = VRegs->l.edi;
+    out->x.cflag = VRegs->w.flags & 0x1;
+
+    return out->x.ax;
+}
+
+int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,
+    RMSREGS *sregs)
+{
+    PM_init();
+    if (VRegs == NULL)
+	return 0;
+
+    if (intno == 0x21) {
+	time_t today = time(NULL);
+	struct tm *t;
+	t = localtime(&today);
+	out->x.cx = t->tm_year + 1900;
+	out->h.dh = t->tm_mon + 1;
+	out->h.dl = t->tm_mday;
+	return 0;
+	}
+    else {
+	VRegs->l.eax = in->e.eax;
+	VRegs->l.ebx = in->e.ebx;
+	VRegs->l.ecx = in->e.ecx;
+	VRegs->l.edx = in->e.edx;
+	VRegs->l.esi = in->e.esi;
+	VRegs->l.edi = in->e.edi;
+	VRegs->w.es = sregs->es;
+	VRegs->w.ds = sregs->ds;
+
+	VBIOSint(intno, VRegs, 1024);
+
+	out->e.eax = VRegs->l.eax;
+	out->e.ebx = VRegs->l.ebx;
+	out->e.ecx = VRegs->l.ecx;
+	out->e.edx = VRegs->l.edx;
+	out->e.esi = VRegs->l.esi;
+	out->e.edi = VRegs->l.edi;
+	out->x.cflag = VRegs->w.flags & 0x1;
+	sregs->es = VRegs->w.es;
+	sregs->ds = VRegs->w.ds;
+
+	return out->x.ax;
+	}
+}
+
+void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in,
+    RMSREGS *sregs)
+{
+    PM_init();
+    if (VRegs == NULL)
+	return;
+
+    VRegs->l.eax = in->e.eax;
+    VRegs->l.ebx = in->e.ebx;
+    VRegs->l.ecx = in->e.ecx;
+    VRegs->l.edx = in->e.edx;
+    VRegs->l.esi = in->e.esi;
+    VRegs->l.edi = in->e.edi;
+    VRegs->w.es = sregs->es;
+    VRegs->w.ds = sregs->ds;
+
+    VBIOScall(seg, off, VRegs, 1024);
+
+    in->e.eax = VRegs->l.eax;
+    in->e.ebx = VRegs->l.ebx;
+    in->e.ecx = VRegs->l.ecx;
+    in->e.edx = VRegs->l.edx;
+    in->e.esi = VRegs->l.esi;
+    in->e.edi = VRegs->l.edi;
+    in->x.cflag = VRegs->w.flags & 0x1;
+    sregs->es = VRegs->w.es;
+    sregs->ds = VRegs->w.ds;
+}
+
+void PMAPI PM_availableMemory(ulong *physical,ulong *total)
+{
+#ifndef __QNXNTO__
+    *physical = *total = _memavl();
+#endif
+}
+
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16M)
+{
+    /* TODO: Implement this on QNX */
+    return NULL;
+}
+
+void PMAPI PM_freeLockedMem(
+    void *p,
+    uint size,
+    ibool contiguous)
+{
+    /* TODO: Implement this on QNX */
+}
+
+void * PMAPI PM_allocPage(
+    ibool locked)
+{
+    /* TODO: Implement this on QNX */
+    return NULL;
+}
+
+void PMAPI PM_freePage(
+    void *p)
+{
+    /* TODO: Implement this on QNX */
+}
+
+void PMAPI PM_setBankA(int bank)
+{
+    PM_init();
+    if (VRegs == NULL)
+	return;
+
+    VRegs->l.eax = 0x4F05;
+    VRegs->l.ebx = 0x0000;
+    VRegs->l.edx = bank;
+    VBIOSint(0x10, VRegs, 1024);
+}
+
+void PMAPI PM_setBankAB(int bank)
+{
+    PM_init();
+    if (VRegs == NULL)
+	return;
+
+    VRegs->l.eax = 0x4F05;
+    VRegs->l.ebx = 0x0000;
+    VRegs->l.edx = bank;
+    VBIOSint(0x10, VRegs, 1024);
+
+    VRegs->l.eax = 0x4F05;
+    VRegs->l.ebx = 0x0001;
+    VRegs->l.edx = bank;
+    VBIOSint(0x10, VRegs, 1024);
+}
+
+void PMAPI PM_setCRTStart(int x,int y,int waitVRT)
+{
+    PM_init();
+    if (VRegs == NULL)
+	return;
+
+    VRegs->l.eax = 0x4F07;
+    VRegs->l.ebx = waitVRT;
+    VRegs->l.ecx = x;
+    VRegs->l.edx = y;
+    VBIOSint(0x10, VRegs, 1024);
+}
+
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *copyOfBIOS,
+    ulong BIOSLen)
+{
+    (void)axVal;
+    (void)BIOSPhysAddr;
+    (void)copyOfBIOS;
+    (void)BIOSLen;
+    return false;
+}
+
+int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;
+    return 1;
+}
+
+int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;
+    return 1;
+}
+
+int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;
+    return 1;
+}
+
+int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    p = p;  len = len;
+    return 1;
+}
+
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    /* TODO: Implement this to load shared libraries! */
+    (void)szDLLName;
+    return NULL;
+}
+
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    /* TODO: Implement this! */
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    /* TODO: Implement this! */
+    (void)hModule;
+}
+
+int PMAPI PM_setIOPL(
+    int level)
+{
+    /* QNX handles IOPL selection at the program link level. */
+    return level;
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+RETURNS:
+Error code describing the result.
+
+REMARKS:
+Function to enable write combining for the specified region of memory.
+****************************************************************************/
+int PMAPI PM_enableWriteCombine(
+    ulong base,
+    ulong size,
+    uint type)
+{
+#ifndef  __QNXNTO__
+    return MTRR_enableWriteCombine(base,size,type);
+#else
+    return PM_MTRR_NOT_SUPPORTED;
+#endif
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c
new file mode 100755
index 0000000..579ef2c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c
@@ -0,0 +1,49 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    baseAddr = baseAddr;
+    bankSize = bankSize;
+    codeLen = codeLen;
+    bankFunc = bankFunc;
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c
new file mode 100755
index 0000000..d274097
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c
@@ -0,0 +1,91 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  QNX
+*
+* Description:  QNX specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+void __ZTimerInit(void)
+{
+}
+
+/****************************************************************************
+REMARKS:
+Use the gettimeofday() function to get microsecond precision (probably less
+though)
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{
+    struct timespec ts;
+    clock_gettime(CLOCK_REALTIME, &ts);
+    return (ts.tv_nsec / 1000 + ts.tv_sec * 1000000);
+}
+
+/****************************************************************************
+REMARKS:
+Start the Zen Timer counting.
+****************************************************************************/
+#define __LZTimerOn(tm)     tm->start.low = __ULZReadTime()
+
+/****************************************************************************
+REMARKS:
+Compute the lap time since the timer was started.
+****************************************************************************/
+#define __LZTimerLap(tm)        (__ULZReadTime() - tm->start.low)
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOff(tm)        tm->end.low = __ULZReadTime()
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerCount(tm)  (tm->end.low - tm->start.low)
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION 1
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c
new file mode 100755
index 0000000..4f32c3e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c
@@ -0,0 +1,94 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  RTTarget-32
+*
+* Description:  Module to implement OS specific services to measure the
+*               CPU frequency.
+*
+****************************************************************************/
+
+/*---------------------------- Global variables ---------------------------*/
+
+static ibool havePerformanceCounter;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Increase the thread priority to maximum, if possible.
+****************************************************************************/
+static int SetMaxThreadPriority(void)
+{
+    int     oldPriority;
+    HANDLE  hThread = GetCurrentThread();
+
+    oldPriority = GetThreadPriority(hThread);
+    if (oldPriority != THREAD_PRIORITY_ERROR_RETURN)
+	SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL);
+    return oldPriority;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the original thread priority.
+****************************************************************************/
+static void RestoreThreadPriority(
+    int oldPriority)
+{
+    HANDLE  hThread = GetCurrentThread();
+
+    if (oldPriority != THREAD_PRIORITY_ERROR_RETURN)
+	SetThreadPriority(hThread, oldPriority);
+}
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    if (!QueryPerformanceFrequency((LARGE_INTEGER*)freq)) {
+	havePerformanceCounter = false;
+	freq->low = 100000;
+	freq->high = 0;
+	}
+    else
+	havePerformanceCounter = true;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)                                       \
+{                                                           \
+    if (havePerformanceCounter)                             \
+	QueryPerformanceCounter((LARGE_INTEGER*)t);         \
+    else {                                                  \
+	(t)->low = timeGetTime() * 100;                     \
+	(t)->high = 0;                                      \
+	}                                                   \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c
new file mode 100755
index 0000000..962a14a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c
@@ -0,0 +1,287 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  RTTarget-32
+*
+* Description:  Win32 implementation for the SciTech cross platform
+*               event library.
+*
+****************************************************************************/
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static ushort   keyUpMsg[256] = {0};    /* Table of key up messages     */
+static int      rangeX,rangeY;          /* Range of mouse coordinates   */
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* These are not used under Win32 */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flags)
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Scan code to test
+
+REMARKS:
+This macro determines if a specified key is currently down at the
+time that the call is made.
+****************************************************************************/
+#define _EVT_isKeyDown(scanCode)    (keyUpMsg[scanCode] != 0)
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{ return timeGetTime(); }
+
+/****************************************************************************
+REMARKS:
+Pumps all messages in the message queue from Win32 into our event queue.
+****************************************************************************/
+void _EVT_pumpMessages(void)
+{
+    MSG     msg;
+    MSG     charMsg;
+    event_t evt;
+
+    while (PeekMessage(&msg,NULL,0,0,PM_REMOVE)) {
+	memset(&evt,0,sizeof(evt));
+	switch (msg.message) {
+	    case WM_MOUSEMOVE:
+		evt.what = EVT_MOUSEMOVE;
+		break;
+	    case WM_LBUTTONDBLCLK:
+		evt.what = EVT_MOUSEDOWN;
+		evt.message = EVT_LEFTBMASK | EVT_DBLCLICK;
+		break;
+	    case WM_LBUTTONDOWN:
+		evt.what = EVT_MOUSEDOWN;
+		evt.message = EVT_LEFTBMASK;
+		break;
+	    case WM_LBUTTONUP:
+		evt.what = EVT_MOUSEUP;
+		evt.message = EVT_LEFTBMASK;
+		break;
+	    case WM_RBUTTONDBLCLK:
+		evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK;
+		evt.message = EVT_RIGHTBMASK;
+		break;
+	    case WM_RBUTTONDOWN:
+		evt.what = EVT_MOUSEDOWN;
+		evt.message = EVT_RIGHTBMASK;
+		break;
+	    case WM_RBUTTONUP:
+		evt.what = EVT_MOUSEUP;
+		evt.message = EVT_RIGHTBMASK;
+		break;
+	    case WM_KEYDOWN:
+	    case WM_SYSKEYDOWN:
+		if (HIWORD(msg.lParam) & KF_REPEAT) {
+		    evt.what = EVT_KEYREPEAT;
+		    }
+		else {
+		    evt.what = EVT_KEYDOWN;
+		    }
+		break;
+	    case WM_KEYUP:
+	    case WM_SYSKEYUP:
+		evt.what = EVT_KEYUP;
+		break;
+	    }
+
+	/* Convert mouse event modifier flags */
+	if (evt.what & EVT_MOUSEEVT) {
+	    evt.where_x = msg.pt.x;
+	    evt.where_y = msg.pt.y;
+	    if (evt.what == EVT_MOUSEMOVE) {
+		if (oldMove != -1) {
+		    evtq[oldMove].where_x = evt.where_x;/* Modify existing one  */
+		    evtq[oldMove].where_y = evt.where_y;
+		    evt.what = 0;
+		    }
+		else {
+		    oldMove = freeHead; /* Save id of this move event   */
+		    }
+		}
+	    else
+		oldMove = -1;
+	    if (msg.wParam & MK_LBUTTON)
+		evt.modifiers |= EVT_LEFTBUT;
+	    if (msg.wParam & MK_RBUTTON)
+		evt.modifiers |= EVT_RIGHTBUT;
+	    if (msg.wParam & MK_SHIFT)
+		evt.modifiers |= EVT_SHIFTKEY;
+	    if (msg.wParam & MK_CONTROL)
+		evt.modifiers |= EVT_CTRLSTATE;
+	    }
+
+	/* Convert keyboard codes */
+	TranslateMessage(&msg);
+	if (evt.what & EVT_KEYEVT) {
+	    int scanCode = (msg.lParam >> 16) & 0xFF;
+	    if (evt.what == EVT_KEYUP) {
+		/* Get message for keyup code from table of cached down values */
+		evt.message = keyUpMsg[scanCode];
+		keyUpMsg[scanCode] = 0;
+		}
+	    else {
+		if (PeekMessage(&charMsg,NULL,WM_CHAR,WM_CHAR,PM_REMOVE))
+		    evt.message = charMsg.wParam;
+		if (PeekMessage(&charMsg,NULL,WM_SYSCHAR,WM_SYSCHAR,PM_REMOVE))
+		    evt.message = charMsg.wParam;
+		evt.message |= ((msg.lParam >> 8) & 0xFF00);
+		keyUpMsg[scanCode] = (ushort)evt.message;
+		}
+	    if (evt.what == EVT_KEYREPEAT)
+		evt.message |= (msg.lParam << 16);
+	    if (HIWORD(msg.lParam) & KF_ALTDOWN)
+		evt.modifiers |= EVT_ALTSTATE;
+	    if (GetKeyState(VK_SHIFT) & 0x8000U)
+		evt.modifiers |= EVT_SHIFTKEY;
+	    if (GetKeyState(VK_CONTROL) & 0x8000U)
+		evt.modifiers |= EVT_CTRLSTATE;
+	    oldMove = -1;
+	    }
+
+	if (evt.what != 0) {
+	    /* Add time stamp and add the event to the queue */
+	    evt.when = msg.time;
+	    if (count < EVENTQSIZE) {
+		addEvent(&evt);
+		}
+	    }
+	DispatchMessage(&msg);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort()
+{
+    EVT_exit();
+    PM_fatalError("Unhandled exception!");
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    /* Initialise the event queue */
+    _mouseMove = mouseMove;
+    initEventQueue();
+    memset(keyUpMsg,0,sizeof(keyUpMsg));
+
+    /* Catch program termination signals so we can clean up properly */
+    signal(SIGABRT, _EVT_abort);
+    signal(SIGFPE, _EVT_abort);
+    signal(SIGINT, _EVT_abort);
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    rangeX = xRes;
+    rangeY = yRes;
+}
+
+/****************************************************************************
+REMARKS
+Modifes the mouse coordinates as necessary if scaling to OS coordinates,
+and sets the OS mouse cursor position.
+****************************************************************************/
+void _EVT_setMousePos(
+    int *x,
+    int *y)
+{
+    SetCursorPos(*x,*y);
+}
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for Win32 */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for Win32 */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+    /* Restore signal handlers */
+    signal(SIGABRT, SIG_DFL);
+    signal(SIGFPE, SIG_DFL);
+    signal(SIGINT, SIG_DFL);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h
new file mode 100755
index 0000000..1352dad
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h
@@ -0,0 +1,34 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  RTTarget-32
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+#define WIN32_LEAN_AND_MEAN
+#define STRICT
+#include <windows.h>
+#include <mmsystem.h>
diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c
new file mode 100755
index 0000000..47d7ed6
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c
@@ -0,0 +1,701 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  RTTarget-32
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#define WIN32_LEAN_AND_MEAN
+#define STRICT
+#include <windows.h>
+#include <mmsystem.h>
+#ifdef  __BORLANDC__
+#pragma warn -par
+#endif
+
+/*--------------------------- Global variables ----------------------------*/
+
+static void     (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+void MTRR_init(void);
+
+/****************************************************************************
+REMARKS:
+Initialise the PM library.
+****************************************************************************/
+void PMAPI PM_init(void)
+{
+    /* TODO: dO any special init code in here. */
+    MTRR_init();
+}
+
+/****************************************************************************
+REMARKS:
+Return the operating system type identifier.
+****************************************************************************/
+long PMAPI PM_getOSType(void)
+{
+    return _OS_RTTARGET;
+}
+
+/****************************************************************************
+REMARKS:
+Return the runtime type identifier.
+****************************************************************************/
+int PMAPI PM_getModeType(void)
+{
+    return PM_386;
+}
+
+/****************************************************************************
+REMARKS:
+Add a file directory separator to the end of the filename.
+****************************************************************************/
+void PMAPI PM_backslash(
+    char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '\\') {
+	s[pos] = '\\';
+	s[pos+1] = '\0';
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Add a user defined PM_fatalError cleanup function.
+****************************************************************************/
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+/****************************************************************************
+REMARKS:
+Report a fatal error condition and halt the program.
+****************************************************************************/
+void PMAPI PM_fatalError(
+    const char *msg)
+{
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+    /* TODO: Display a fatal error message and exit! */
+/*  MessageBox(NULL,msg,"Fatal Error!", MB_ICONEXCLAMATION); */
+    exit(1);
+}
+
+/****************************************************************************
+REMARKS:
+Allocate the real mode VESA transfer buffer for communicating with the BIOS.
+****************************************************************************/
+void * PMAPI PM_getVESABuf(
+    uint *len,
+    uint *rseg,
+    uint *roff)
+{
+    /* No BIOS access for the RTTarget */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Check if a key has been pressed.
+****************************************************************************/
+int PMAPI PM_kbhit(void)
+{
+    /* TODO: Need to check if a key is waiting on the keyboard queue */
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Wait for and return the next keypress.
+****************************************************************************/
+int PMAPI PM_getch(void)
+{
+    /* TODO: Need to obtain the next keypress, and block until one is hit */
+    return 0xD;
+}
+
+/****************************************************************************
+REMARKS:
+Set the location of the OS console cursor.
+****************************************************************************/
+void PM_setOSCursorLocation(
+    int x,
+    int y)
+{
+    /* Nothing to do for RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Set the width of the OS console.
+****************************************************************************/
+void PM_setOSScreenWidth(
+    int width,
+    int height)
+{
+    /* Nothing to do for RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock handler (used for software stereo modes).
+****************************************************************************/
+ibool PMAPI PM_setRealTimeClockHandler(
+    PM_intHandler ih,
+    int frequency)
+{
+    /* Not supported for RTTarget-32 */
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock frequency (for stereo modes).
+****************************************************************************/
+void PMAPI PM_setRealTimeClockFrequency(
+    int frequency)
+{
+    /* Not supported under RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Restore the original real time clock handler.
+****************************************************************************/
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    /* Not supported under RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Return the current operating system path or working directory.
+****************************************************************************/
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    return getcwd(path,maxLen);
+}
+
+/****************************************************************************
+REMARKS:
+Return the drive letter for the boot drive.
+****************************************************************************/
+char PMAPI PM_getBootDrive(void)
+{
+    return 'c';
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the VBE/AF driver files.
+****************************************************************************/
+const char * PMAPI PM_getVBEAFPath(void)
+{
+    return "c:\\";
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus driver files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusPath(void)
+{
+    /* TODO: Point this at the path when the Nucleus drivers will be found */
+    return "c:\\nucleus";
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus configuration files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+/****************************************************************************
+REMARKS:
+Return a unique identifier for the machine if possible.
+****************************************************************************/
+const char * PMAPI PM_getUniqueID(void)
+{
+    return PM_getMachineName();
+}
+
+/****************************************************************************
+REMARKS:
+Get the name of the machine on the network.
+****************************************************************************/
+const char * PMAPI PM_getMachineName(void)
+{
+    /* Not necessary for RTTarget-32 */
+    return "Unknown";
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to the real mode BIOS data area.
+****************************************************************************/
+void * PMAPI PM_getBIOSPointer(void)
+{
+    /* Not used for RTTarget-32 */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to 0xA0000 physical VGA graphics framebuffer.
+****************************************************************************/
+void * PMAPI PM_getA0000Pointer(void)
+{
+    static void *bankPtr;
+    if (!bankPtr)
+	bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true);
+    return bankPtr;
+}
+
+/****************************************************************************
+REMARKS:
+Map a physical address to a linear address in the callers process.
+****************************************************************************/
+void * PMAPI PM_mapPhysicalAddr(
+    ulong base,
+    ulong limit,
+    ibool isCached)
+{
+    /* TODO: Map a physical memory address to a linear address */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a physical address mapping allocated by PM_mapPhysicalAddr.
+****************************************************************************/
+void PMAPI PM_freePhysicalAddr(
+    void *ptr,
+    ulong limit)
+{
+    /* TODO: Free the physical address mapping */
+}
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{
+    /* TODO: This function should find the physical address of a linear */
+    /*       address. */
+    return 0xFFFFFFFFUL;
+}
+
+void PMAPI PM_sleep(ulong milliseconds)
+{
+    Sleep(milliseconds);
+}
+
+int PMAPI PM_getCOMPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	}
+    return 0;
+}
+
+int PMAPI PM_getLPTPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of (unnamed) shared memory.
+****************************************************************************/
+void * PMAPI PM_mallocShared(
+    long size)
+{
+    return PM_malloc(size);
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of shared memory.
+****************************************************************************/
+void PMAPI PM_freeShared(
+    void *ptr)
+{
+    PM_free(ptr);
+}
+
+/****************************************************************************
+REMARKS:
+Map a linear memory address to the calling process address space. The
+address will have been allocated in another process using the
+PM_mapPhysicalAddr function.
+****************************************************************************/
+void * PMAPI PM_mapToProcess(
+    void *base,
+    ulong limit)
+{
+    return base;
+}
+
+/****************************************************************************
+REMARKS:
+Map a real mode pointer to a protected mode pointer.
+****************************************************************************/
+void * PMAPI PM_mapRealPointer(
+    uint r_seg,
+    uint r_off)
+{
+    /* Not used for RTTarget-32 */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of real mode memory
+****************************************************************************/
+void * PMAPI PM_allocRealSeg(
+    uint size,
+    uint *r_seg,
+    uint *r_off)
+{
+    /* Not used for RTTarget-32 */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of real mode memory.
+****************************************************************************/
+void PMAPI PM_freeRealSeg(
+    void *mem)
+{
+    /* Not used for RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt (parameters in DPMI compatible structure)
+****************************************************************************/
+void PMAPI DPMI_int86(
+    int intno,
+    DPMI_regs *regs)
+{
+    /* Not used for RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt.
+****************************************************************************/
+int PMAPI PM_int86(
+    int intno,
+    RMREGS *in,
+    RMREGS *out)
+{
+    /* Not used for RTTarget-32 */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt.
+****************************************************************************/
+int PMAPI PM_int86x(
+    int intno,
+    RMREGS *in,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    /* Not used for RTTarget-32 */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Call a real mode far function.
+****************************************************************************/
+void PMAPI PM_callRealMode(
+    uint seg,
+    uint off,
+    RMREGS *in,
+    RMSREGS *sregs)
+{
+    /* Not used for RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Return the amount of available memory.
+****************************************************************************/
+void PMAPI PM_availableMemory(
+    ulong *physical,
+    ulong *total)
+{
+    /* TODO: Figure out how to determine the available memory. Not entirely */
+    /*       critical so returning 0 is OK. */
+    *physical = *total = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of locked, physical memory for DMA operations.
+****************************************************************************/
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16M)
+{
+    /* TODO: Allocate a block of locked, phsyically contigous memory for DMA */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of locked physical memory.
+****************************************************************************/
+void PMAPI PM_freeLockedMem(
+    void *p,
+    uint size,
+
+    ibool contiguous)
+{
+    /* TODO: Free a locked memory buffer */
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankA(
+    int bank)
+{
+    /* Not used for RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankAB(
+    int bank)
+{
+    /* Not used for RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display start address.
+****************************************************************************/
+void PMAPI PM_setCRTStart(
+    int x,
+    int y,
+    int waitVRT)
+{
+    /* Not used for RTTarget-32 */
+}
+
+/****************************************************************************
+REMARKS:
+Execute the POST on the secondary BIOS for a controller.
+****************************************************************************/
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS)
+{
+    /* Not used for RTTarget-32 */
+    return false;
+}
+
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    /* TODO: Implement this to load shared libraries! */
+    (void)szDLLName;
+    return NULL;
+}
+
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    /* TODO: Implement this! */
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    /* TODO: Implement this! */
+    (void)hModule;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+ulong PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    /* TODO: This function should start a directory enumeration search */
+    /*       given the filename (with wildcards). The data should be */
+    /*       converted and returned in the findData standard form. */
+    (void)filename;
+    (void)findData;
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    ulong handle,
+    PM_findData *findData)
+{
+    /* TODO: This function should find the next file in directory enumeration */
+    /*       search given the search criteria defined in the call to */
+    /*       PM_findFirstFile. The data should be converted and returned */
+    /*       in the findData standard form. */
+    (void)handle;
+    (void)findData;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    ulong handle)
+{
+    /* TODO: This function should close the find process. This may do */
+    /*       nothing for some OS'es. */
+    (void)handle;
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    if (drive == 3)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    (void)drive;
+    getcwd(dir,len);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+    /* TODO: Set the file attributes for a file */
+    (void)filename;
+    (void)attrib;
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+    return mkdir(filename) == 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+    return rmdir(filename) == 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c
new file mode 100755
index 0000000..dd9dfe6
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c
@@ -0,0 +1,48 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  RTTarget-32
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#ifdef  __BORLANDC__
+#pragma warn -par
+#endif
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c
new file mode 100755
index 0000000..80c184d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c
@@ -0,0 +1,136 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  RTTarget-32
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+/*---------------------------- Global variables ---------------------------*/
+
+static CPU_largeInteger countFreq;
+static ibool            havePerformanceCounter;
+static ulong            start,finish;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+void __ZTimerInit(void)
+{
+#ifdef  NO_ASSEMBLER
+    havePerformanceCounter = false;
+#else
+    havePerformanceCounter = QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq);
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Start the Zen Timer counting.
+****************************************************************************/
+static void __LZTimerOn(
+    LZTimerObject *tm)
+{
+    if (havePerformanceCounter)
+	QueryPerformanceCounter((LARGE_INTEGER*)&tm->start);
+    else
+	tm->start.low = timeGetTime();
+}
+
+/****************************************************************************
+REMARKS:
+Compute the lap time since the timer was started.
+****************************************************************************/
+static ulong __LZTimerLap(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger    tmLap,tmCount;
+
+    if (havePerformanceCounter) {
+	QueryPerformanceCounter((LARGE_INTEGER*)&tmLap);
+	_CPU_diffTime64(&tm->start,&tmLap,&tmCount);
+	return _CPU_calcMicroSec(&tmCount,countFreq.low);
+	}
+    else {
+	tmLap.low = timeGetTime();
+	return (tmLap.low - tm->start.low) * 1000L;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Stop the Zen Timer counting.
+****************************************************************************/
+static void __LZTimerOff(
+    LZTimerObject *tm)
+{
+    if (havePerformanceCounter)
+	QueryPerformanceCounter((LARGE_INTEGER*)&tm->end);
+    else
+	tm->end.low = timeGetTime();
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time in microseconds between start and end timings.
+****************************************************************************/
+static ulong __LZTimerCount(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger    tmCount;
+
+    if (havePerformanceCounter) {
+	_CPU_diffTime64(&tm->start,&tm->end,&tmCount);
+	return _CPU_calcMicroSec(&tmCount,countFreq.low);
+	}
+    else
+	return (tm->end.low - tm->start.low) * 1000L;
+}
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION     1000
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer from the OS
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{ return timeGetTime(); }
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm
new file mode 100755
index 0000000..da62b1f
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm
@@ -0,0 +1,175 @@
+;****************************************************************************
+;*
+;*                  SciTech Multi-platform Graphics Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler
+;* Environment: IBM PC (MS DOS)
+;*
+;* Description: Assembly language support routines for the event module.
+;*
+;****************************************************************************
+
+        ideal
+
+include "scitech.mac"           ; Memory model macros
+
+ifdef flatmodel
+
+header  _event                  ; Set up memory model
+
+begdataseg  _event
+
+    cextern  _EVT_biosPtr,DPTR
+
+    cpublic _EVT_dataStart
+
+ifdef   USE_NASM
+%define KB_HEAD     WORD esi+01Ah   ; Keyboard buffer head in BIOS data area
+%define KB_TAIL     WORD esi+01Ch   ; Keyboard buffer tail in BIOS data area
+%define KB_START    WORD esi+080h   ; Start of keyboard buffer in BIOS data area
+%define KB_END      WORD esi+082h   ; End of keyboard buffer in BIOS data area
+else
+KB_HEAD     EQU WORD esi+01Ah       ; Keyboard buffer head in BIOS data area
+KB_TAIL     EQU WORD esi+01Ch       ; Keyboard buffer tail in BIOS data area
+KB_START    EQU WORD esi+080h       ; Start of keyboard buffer in BIOS data area
+KB_END      EQU WORD esi+082h       ; End of keyboard buffer in BIOS data area
+endif
+
+    cpublic _EVT_dataEnd
+
+enddataseg  _event
+
+begcodeseg  _event              ; Start of code segment
+
+    cpublic _EVT_codeStart
+
+;----------------------------------------------------------------------------
+; int _EVT_getKeyCode(void)
+;----------------------------------------------------------------------------
+; Returns the key code for the next available key by extracting it from
+; the BIOS keyboard buffer.
+;----------------------------------------------------------------------------
+cprocstart  _EVT_getKeyCode
+
+        enter_c
+
+        mov     esi,[_EVT_biosPtr]
+        xor     ebx,ebx
+        xor     eax,eax
+        mov     bx,[KB_HEAD]
+        cmp     bx,[KB_TAIL]
+        jz      @@Done
+        xor     eax,eax
+        mov     ax,[esi+ebx]    ; EAX := character from keyboard buffer
+        inc     _bx
+        inc     _bx
+        cmp     bx,[KB_END]     ; Hit the end of the keyboard buffer?
+        jl      @@1
+        mov     bx,[KB_START]
+@@1:    mov     [KB_HEAD],bx    ; Update keyboard buffer head pointer
+
+@@Done: leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int _EVT_disableInt(void);
+;----------------------------------------------------------------------------
+; Return processor interrupt status and disable interrupts.
+;----------------------------------------------------------------------------
+cprocstart  _EVT_disableInt
+
+        pushf                   ; Put flag word on stack
+        cli                     ; Disable interrupts!
+        pop     eax             ; deposit flag word in return register
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _EVT_restoreInt(int ps);
+;----------------------------------------------------------------------------
+; Restore processor interrupt status.
+;----------------------------------------------------------------------------
+cprocstart  _EVT_restoreInt
+
+        ARG     ps:UINT
+
+        push    ebp
+        mov     ebp,esp         ; Set up stack frame
+        push    [DWORD ps]
+        popf                    ; Restore processor status (and interrupts)
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int EVT_rdinx(int port,int index)
+;----------------------------------------------------------------------------
+; Reads an indexed register value from an I/O port.
+;----------------------------------------------------------------------------
+cprocstart  EVT_rdinx
+
+        ARG     port:UINT, index:UINT
+
+        push    ebp
+        mov     ebp,esp
+        mov     edx,[port]
+        mov     al,[BYTE index]
+        out     dx,al
+        inc     dx
+        in      al,dx
+        movzx   eax,al
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void EVT_wrinx(int port,int index,int value)
+;----------------------------------------------------------------------------
+; Writes an indexed register value to an I/O port.
+;----------------------------------------------------------------------------
+cprocstart  EVT_wrinx
+
+        ARG     port:UINT, index:UINT, value:UINT
+
+        push    ebp
+        mov     ebp,esp
+        mov     edx,[port]
+        mov     al,[BYTE index]
+        mov     ah,[BYTE value]
+        out     dx,ax
+        pop     ebp
+        ret
+
+cprocend
+
+    cpublic _EVT_codeEnd
+
+endcodeseg  _event
+
+endif
+
+        END                         ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm
new file mode 100755
index 0000000..068eea6
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm
@@ -0,0 +1,58 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    NASM or TASM Assembler
+;* Environment: smx 32 bit intel CPU
+;*
+;* Description: SMX does not support 486's, so this module is not necessary.
+;*
+;*  All registers and all flags are preserved by all routines, except
+;*  interrupts which are always turned on
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"
+
+header      _lztimer
+
+begdataseg  _lztimer
+
+enddataseg  _lztimer
+
+begcodeseg  _lztimer                ; Start of code segment
+
+cprocstart   LZ_disable
+        cli
+        ret
+cprocend
+
+cprocstart   LZ_enable
+        sti
+        ret
+cprocend
+
+endcodeseg  _lztimer
+
+        END
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm
new file mode 100755
index 0000000..1c7cb21
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm
@@ -0,0 +1,448 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: 32-bit SMX embedded systems development
+;*
+;* Description: Low level assembly support for the PM library specific to
+;*              SMX.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"               ; Memory model macros
+
+header      _pm                     ; Set up memory model
+
+begdataseg  _pm
+
+    cextern _PM_savedDS,USHORT
+
+intel_id        db  "GenuineIntel"  ; Intel vendor ID
+
+enddataseg  _pm
+
+begcodeseg  _pm                 ; Start of code segment
+
+;----------------------------------------------------------------------------
+; void PM_segread(PMSREGS *sregs)
+;----------------------------------------------------------------------------
+; Read the current value of all segment registers
+;----------------------------------------------------------------------------
+cprocstartdll16 PM_segread
+
+        ARG     sregs:DPTR
+
+        enter_c
+
+        mov     ax,es
+        _les    _si,[sregs]
+        mov     [_ES _si],ax
+        mov     [_ES _si+2],cs
+        mov     [_ES _si+4],ss
+        mov     [_ES _si+6],ds
+        mov     [_ES _si+8],fs
+        mov     [_ES _si+10],gs
+
+        leave_c
+        ret
+
+cprocend
+
+; Create a table of the 256 different interrupt calls that we can jump
+; into
+
+ifdef   USE_NASM
+
+%assign intno 0
+
+intTable:
+%rep    256
+        db      0CDh
+        db      intno
+%assign intno   intno + 1
+        ret
+        nop
+%endrep
+
+else
+
+intno = 0
+
+intTable:
+        REPT    256
+        db      0CDh
+        db      intno
+intno = intno + 1
+        ret
+        nop
+        ENDM
+
+endif
+
+;----------------------------------------------------------------------------
+; _PM_genInt    - Generate the appropriate interrupt
+;----------------------------------------------------------------------------
+cprocnear   _PM_genInt
+
+        push    _ax                     ; Save _ax
+        push    _bx                     ; Save _bx
+        mov     ebx,[UINT esp+12]       ; EBX := interrupt number
+        mov     _ax,offset intTable     ; Point to interrupt generation table
+        shl     _bx,2                   ; _BX := index into table
+        add     _ax,_bx                 ; _AX := pointer to interrupt code
+        xchg    eax,[esp+4]             ; Restore eax, and set for int
+        pop     _bx                     ; restore _bx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs)
+;----------------------------------------------------------------------------
+; Issues a software interrupt in protected mode. This routine has been
+; written to allow user programs to load CS and DS with different values
+; other than the default.
+;----------------------------------------------------------------------------
+cprocstartdll16 PM_int386x
+
+        ARG     intno:UINT, inptr:DPTR, outptr:DPTR, sregs:DPTR
+
+        LOCAL   flags:UINT, sv_ds:UINT, sv_esi:ULONG = LocalSize
+
+        enter_c
+        push    ds
+        push    es                  ; Save segment registers
+        push    fs
+        push    gs
+
+        _lds    _si,[sregs]         ; DS:_SI -> Load segment registers
+        mov     es,[_si]
+        mov     bx,[_si+6]
+        mov     [sv_ds],_bx         ; Save value of user DS on stack
+        mov     fs,[_si+8]
+        mov     gs,[_si+10]
+
+        _lds    _si,[inptr]         ; Load CPU registers
+        mov     eax,[_si]
+        mov     ebx,[_si+4]
+        mov     ecx,[_si+8]
+        mov     edx,[_si+12]
+        mov     edi,[_si+20]
+        mov     esi,[_si+16]
+
+        push    ds                  ; Save value of DS
+        push    _bp                 ; Some interrupts trash this!
+        clc                         ; Generate the interrupt
+        push    [UINT intno]
+        mov     ds,[WORD sv_ds]     ; Set value of user's DS selector
+        call    _PM_genInt
+        pop     _bp                 ; Pop intno from stack (flags unchanged)
+        pop     _bp                 ; Restore value of stack frame pointer
+        pop     ds                  ; Restore value of DS
+
+        pushf                       ; Save flags for later
+        pop     [UINT flags]
+        push    esi                 ; Save ESI for later
+        pop     [DWORD sv_esi]
+        push    ds                  ; Save DS for later
+        pop     [UINT sv_ds]
+
+        _lds    _si,[outptr]        ; Save CPU registers
+        mov     [_si],eax
+        mov     [_si+4],ebx
+        mov     [_si+8],ecx
+        mov     [_si+12],edx
+        push    [DWORD sv_esi]
+        pop     [DWORD _si+16]
+        mov     [_si+20],edi
+
+        mov     _bx,[flags]         ; Return flags
+        and     ebx,1h              ; Isolate carry flag
+        mov     [_si+24],ebx        ; Save carry flag status
+
+        _lds    _si,[sregs]         ; Save segment registers
+        mov     [_si],es
+        mov     _bx,[sv_ds]
+        mov     [_si+6],bx          ; Get returned DS from stack
+        mov     [_si+8],fs
+        mov     [_si+10],gs
+
+        pop     gs                  ; Restore segment registers
+        pop     fs
+        pop     es
+        pop     ds
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_saveDS(void)
+;----------------------------------------------------------------------------
+; Save the value of DS into a section of the code segment, so that we can
+; quickly load this value at a later date in the PM_loadDS() routine from
+; inside interrupt handlers etc. The method to do this is different
+; depending on the DOS extender being used.
+;----------------------------------------------------------------------------
+cprocstartdll16 PM_saveDS
+
+        mov     [_PM_savedDS],ds    ; Store away in data segment
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_loadDS(void)
+;----------------------------------------------------------------------------
+; Routine to load the DS register with the default value for the current
+; DOS extender. Only the DS register is loaded, not the ES register, so
+; if you wish to call C code, you will need to also load the ES register
+; in 32 bit protected mode.
+;----------------------------------------------------------------------------
+cprocstartdll16 PM_loadDS
+
+        mov     ds,[cs:_PM_savedDS] ; We can access the proper DS through CS
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setBankA(int bank)
+;----------------------------------------------------------------------------
+cprocstart      PM_setBankA
+
+        ARG     bank:UINT
+
+        push    ebp
+        mov     ebp,esp
+        push    ebx
+        mov     _bx,0
+        mov     _ax,4F05h
+        mov     _dx,[bank]
+        int     10h
+        pop     ebx
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setBankAB(int bank)
+;----------------------------------------------------------------------------
+cprocstart      PM_setBankAB
+
+        ARG     bank:UINT
+
+        push    ebp
+        mov     ebp,esp
+        push    ebx
+        mov     _bx,0
+        mov     _ax,4F05h
+        mov     _dx,[bank]
+        int     10h
+        mov     _bx,1
+        mov     _ax,4F05h
+        mov     _dx,[bank]
+        int     10h
+        pop     ebx
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setCRTStart(int x,int y,int waitVRT)
+;----------------------------------------------------------------------------
+cprocstart      PM_setCRTStart
+
+        ARG     x:UINT, y:UINT, waitVRT:UINT
+
+        push    ebp
+        mov     ebp,esp
+        push    ebx
+        mov     _bx,[waitVRT]
+        mov     _cx,[x]
+        mov     _dx,[y]
+        mov     _ax,4F07h
+        int     10h
+        pop     ebx
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int _PM_inp(int port)
+;----------------------------------------------------------------------------
+; Reads a byte from the specified port
+;----------------------------------------------------------------------------
+cprocstart  _PM_inp
+
+        ARG     port:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        xor     _ax,_ax
+        mov     _dx,[port]
+        in      al,dx
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _PM_outp(int port,int value)
+;----------------------------------------------------------------------------
+; Write a byte to the specified port.
+;----------------------------------------------------------------------------
+cprocstart  _PM_outp
+
+        ARG     port:UINT, value:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        mov     _dx,[port]
+        mov     _ax,[value]
+        out     dx,al
+        pop     _bp
+        ret
+
+cprocend
+
+; Macro to delay briefly to ensure that enough time has elapsed between
+; successive I/O accesses so that the device being accessed can respond
+; to both accesses even on a very fast PC.
+
+ifdef   USE_NASM
+%macro  DELAY 0
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+%endmacro
+%macro  IODELAYN 1
+%rep    %1
+        DELAY
+%endrep
+%endmacro
+else
+macro   DELAY
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+endm
+macro   IODELAYN    N
+    rept    N
+        DELAY
+    endm
+endm
+endif
+
+;----------------------------------------------------------------------------
+; uchar _PM_readCMOS(int index)
+;----------------------------------------------------------------------------
+; Read the value of a specific CMOS register. We do this with both
+; normal interrupts and NMI disabled.
+;----------------------------------------------------------------------------
+cprocstart  _PM_readCMOS
+
+        ARG     index:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        pushfd
+        mov     al,[BYTE index]
+        or      al,80h              ; Add disable NMI flag
+        cli
+        out     70h,al
+        IODELAYN 5
+        in      al,71h
+        mov     ah,al
+        xor     al,al
+        IODELAYN 5
+        out     70h,al              ; Re-enable NMI
+        sti
+        mov     al,ah               ; Return value in AL
+        popfd
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _PM_writeCMOS(int index,uchar value)
+;----------------------------------------------------------------------------
+; Read the value of a specific CMOS register. We do this with both
+; normal interrupts and NMI disabled.
+;----------------------------------------------------------------------------
+cprocstart  _PM_writeCMOS
+
+        ARG     index:UINT, value:UCHAR
+
+        push    _bp
+        mov     _bp,_sp
+        pushfd
+        mov     al,[BYTE index]
+        or      al,80h              ; Add disable NMI flag
+        cli
+        out     70h,al
+        IODELAYN 5
+        mov     al,[value]
+        out     71h,al
+        xor     al,al
+        IODELAYN 5
+        out     70h,al              ; Re-enable NMI
+        sti
+        popfd
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; _PM_getPDB - Return the Page Table Directory Base address
+;----------------------------------------------------------------------------
+cprocstart  _PM_getPDB
+
+        mov     eax,cr3
+        and     eax,0FFFFF000h
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; _PM_flushTLB - Flush the Translation Lookaside buffer
+;----------------------------------------------------------------------------
+cprocstart  PM_flushTLB
+
+        wbinvd                  ; Flush the CPU cache
+        mov     eax,cr3         
+        mov     cr3,eax         ; Flush the TLB
+        ret
+
+cprocend
+
+endcodeseg  _pm
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm
new file mode 100755
index 0000000..8352ce3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm
@@ -0,0 +1,933 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: 32-bit SMX embedded systems development
+;*
+;* Description: Low level assembly support for the PM library specific to
+;*              SMX interrupt handling.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"           ; Memory model macros
+
+header      _pmsmx              ; Set up memory model
+
+; Define the size of our local stacks. For real mode code they cant be
+; that big, but for 32 bit protected mode code we can make them nice and
+; large so that complex C functions can be used.
+
+MOUSE_STACK EQU 4096
+TIMER_STACK EQU 4096
+KEY_STACK   EQU 1024
+INT10_STACK EQU 1024
+
+ifdef   USE_NASM
+
+; Macro to load DS and ES registers with correct value.
+
+%imacro   LOAD_DS 0
+        mov     ds,[cs:_PM_savedDS]
+        mov     es,[cs:_PM_savedDS]
+%endmacro
+
+; Note that interrupts we disable interrupts during the following stack
+; %imacro for correct operation, but we do not enable them again. Normally
+; these %imacros are used within interrupt handlers so interrupts should
+; already be off. We turn them back on explicitly later if the user code
+; needs them to be back on.
+
+; Macro to switch to a new local stack.
+
+%imacro NEWSTK  1
+        cli
+        mov     [seg_%1],ss
+        mov     [ptr_%1],_sp
+        mov     [TempSeg],ds
+        mov     ss,[TempSeg]
+        mov     _sp,offset %1
+%endmacro
+
+; %imacro to switch back to the old stack.
+
+%imacro   RESTSTK   1
+        cli
+        mov     ss,[seg_%1]
+        mov     _sp,[ptr_%1]
+%endmacro
+
+; %imacro to swap the current stack with the one saved away.
+
+%imacro SWAPSTK 1
+        cli
+        mov     ax,ss
+        xchg    ax,[seg_%1]
+        mov     ss,ax
+        xchg    _sp,[ptr_%1]
+%endmacro
+
+else
+
+; Macro to load DS and ES registers with correct value.
+
+MACRO   LOAD_DS
+        mov     ds,[cs:_PM_savedDS]
+        mov     es,[cs:_PM_savedDS]
+ENDM
+
+; Note that interrupts we disable interrupts during the following stack
+; macro for correct operation, but we do not enable them again. Normally
+; these macros are used within interrupt handlers so interrupts should
+; already be off. We turn them back on explicitly later if the user code
+; needs them to be back on.
+
+; Macro to switch to a new local stack.
+
+MACRO   NEWSTK  stkname
+        cli
+        mov     [seg_&stkname&],ss
+        mov     [ptr_&stkname&],_sp
+        mov     [TempSeg],ds
+        mov     ss,[TempSeg]
+        mov     _sp,offset stkname
+ENDM
+
+; Macro to switch back to the old stack.
+
+MACRO   RESTSTK stkname
+        cli
+        mov     ss,[seg_&stkname&]
+        mov     _sp,[ptr_&stkname&]
+ENDM
+
+; Macro to swap the current stack with the one saved away.
+
+MACRO   SWAPSTK stkname
+        cli
+        mov     ax,ss
+        xchg    ax,[seg_&stkname&]
+        mov     ss,ax
+        xchg    _sp,[ptr_&stkname&]
+ENDM
+
+endif
+
+begdataseg  _pmsmx
+
+    cextern _PM_savedDS,USHORT
+    cextern _PM_critHandler,CPTR
+    cextern _PM_breakHandler,CPTR
+    cextern _PM_timerHandler,CPTR
+    cextern _PM_rtcHandler,CPTR
+    cextern _PM_keyHandler,CPTR
+    cextern _PM_key15Handler,CPTR
+    cextern _PM_mouseHandler,CPTR
+    cextern _PM_int10Handler,CPTR
+
+    cextern _PM_ctrlCPtr,DPTR
+    cextern _PM_ctrlBPtr,DPTR
+    cextern _PM_critPtr,DPTR
+
+    cextern _PM_prevTimer,FCPTR
+    cextern _PM_prevRTC,FCPTR
+    cextern _PM_prevKey,FCPTR
+    cextern _PM_prevKey15,FCPTR
+    cextern _PM_prevBreak,FCPTR
+    cextern _PM_prevCtrlC,FCPTR
+    cextern _PM_prevCritical,FCPTR
+    cextern _PM_prevRealTimer,ULONG
+    cextern _PM_prevRealRTC,ULONG
+    cextern _PM_prevRealKey,ULONG
+    cextern _PM_prevRealKey15,ULONG
+    cextern _PM_prevRealInt10,ULONG
+
+cpublic _PM_pmsmxDataStart
+
+; Allocate space for all of the local stacks that we need. These stacks
+; are not very large, but should be large enough for most purposes
+; (generally you want to handle these interrupts quickly, simply storing
+; the information for later and then returning). If you need bigger
+; stacks then change the appropriate value in here.
+
+            ALIGN   4
+            dclb MOUSE_STACK    ; Space for local stack (small)
+MsStack:                        ; Stack starts at end!
+ptr_MsStack DUINT   0           ; Place to store old stack offset
+seg_MsStack dw      0           ; Place to store old stack segment
+
+            ALIGN   4
+            dclb INT10_STACK    ; Space for local stack (small)
+Int10Stack:                     ; Stack starts at end!
+ptr_Int10Stack  DUINT   0       ; Place to store old stack offset
+seg_Int10Stack  dw      0       ; Place to store old stack segment
+
+            ALIGN   4
+            dclb TIMER_STACK    ; Space for local stack (small)
+TmStack:                        ; Stack starts at end!
+ptr_TmStack DUINT   0           ; Place to store old stack offset
+seg_TmStack dw      0           ; Place to store old stack segment
+
+            ALIGN   4
+            dclb TIMER_STACK    ; Space for local stack (small)
+RtcStack:                       ; Stack starts at end!
+ptr_RtcStack DUINT  0           ; Place to store old stack offset
+seg_RtcStack dw     0           ; Place to store old stack segment
+RtcInside   dw      0           ; Are we still handling current interrupt
+
+            ALIGN   4
+            dclb KEY_STACK      ; Space for local stack (small)
+KyStack:                        ; Stack starts at end!
+ptr_KyStack DUINT   0           ; Place to store old stack offset
+seg_KyStack dw      0           ; Place to store old stack segment
+KyInside    dw      0           ; Are we still handling current interrupt
+
+            ALIGN   4
+            dclb KEY_STACK      ; Space for local stack (small)
+Ky15Stack:                      ; Stack starts at end!
+ptr_Ky15Stack   DUINT   0       ; Place to store old stack offset
+seg_Ky15Stack   dw      0       ; Place to store old stack segment
+
+TempSeg     dw      0           ; Place to store stack segment
+
+cpublic _PM_pmsmxDataEnd
+
+enddataseg  _pmsmx
+
+begcodeseg  _pmsmx              ; Start of code segment
+
+cpublic _PM_pmsmxCodeStart
+
+;----------------------------------------------------------------------------
+; PM_mouseISR - Mouse interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Interrupt subroutine called by the mouse driver upon interrupts, to
+; dispatch control to high level C based subroutines. Interrupts are on
+; when we call the user code.
+;
+; It is _extremely_ important to save the state of the extended registers
+; as these may well be trashed by the routines called from here and not
+; restored correctly by the mouse interface module.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. For mouse handlers this is not a
+;       problem, as the mouse driver arbitrates calls to the user mouse
+;       handler for us.
+;
+; Entry:    AX  - Condition mask giving reason for call
+;           BX  - Mouse button state
+;           CX  - Horizontal cursor coordinate
+;           DX  - Vertical cursor coordinate
+;           SI  - Horizontal mickey value
+;           DI  - Vertical mickey value
+;
+;----------------------------------------------------------------------------
+cprocfar    _PM_mouseISR
+
+        push    ds              ; Save value of DS
+        push    es
+        pushad                  ; Save _all_ extended registers
+        cld                     ; Clear direction flag
+
+        LOAD_DS                 ; Load DS register
+        NEWSTK  MsStack         ; Switch to local stack
+
+; Call the installed high level C code routine
+
+        clrhi   dx              ; Clear out high order values
+        clrhi   cx
+        clrhi   bx
+        clrhi   ax
+        sgnhi   si
+        sgnhi   di
+
+        push    _di
+        push    _si
+        push    _dx
+        push    _cx
+        push    _bx
+        push    _ax
+        sti                     ; Enable interrupts
+        call    [CPTR _PM_mouseHandler]
+        _add    sp,12,24
+
+        RESTSTK MsStack         ; Restore previous stack
+
+        popad                   ; Restore all extended registers
+        pop     es
+        pop     ds
+        ret                     ; We are done!!
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_timerISR - Timer interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the timer interrupt, to dispatch control
+; to high level C based subroutines. We save the state of all registers
+; in this routine, and switch to a local stack. Interrupts are *off*
+; when we call the user code.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. Make sure your C code executes as
+;       quickly as possible, since a timer overrun will simply hang the
+;       system.
+;----------------------------------------------------------------------------
+cprocfar    _PM_timerISR
+
+        push    ds              ; Save value of DS
+        push    es
+        pushad                  ; Save _all_ extended registers
+        cld                     ; Clear direction flag
+
+        LOAD_DS                 ; Load DS register
+
+        NEWSTK  TmStack         ; Switch to local stack
+        call    [CPTR _PM_timerHandler]
+        RESTSTK TmStack         ; Restore previous stack
+
+        popad                   ; Restore all extended registers
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_chainPrevTimer - Chain to previous timer interrupt and return
+;----------------------------------------------------------------------------
+; Chains to the previous timer interrupt routine and returns control
+; back to the high level interrupt handler.
+;----------------------------------------------------------------------------
+cprocstart  PM_chainPrevTimer
+
+ifdef   TNT
+        push    eax
+        push    ebx
+        push    ecx
+        pushfd                  ; Push flags on stack to simulate interrupt
+        mov     ax,250Eh        ; Call real mode procedure function
+        mov     ebx,[_PM_prevRealTimer]
+        mov     ecx,1           ; Copy real mode flags to real mode stack
+        int     21h             ; Call the real mode code
+        popfd
+        pop     ecx
+        pop     ebx
+        pop     eax
+        ret
+else
+        SWAPSTK TmStack         ; Swap back to previous stack
+        pushf                   ; Save state of interrupt flag
+        pushf                   ; Push flags on stack to simulate interrupt
+ifdef   USE_NASM
+        call far dword [_PM_prevTimer]
+else
+        call    [_PM_prevTimer]
+endif
+        popf                    ; Restore state of interrupt flag
+        SWAPSTK TmStack         ; Swap back to C stack again
+        ret
+endif
+
+cprocend
+
+; Macro to delay briefly to ensure that enough time has elapsed between
+; successive I/O accesses so that the device being accessed can respond
+; to both accesses even on a very fast PC.
+
+ifdef   USE_NASM
+%macro  DELAY 0
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+%endmacro
+%macro  IODELAYN 1
+%rep    %1
+        DELAY
+%endrep
+%endmacro
+else
+macro   DELAY
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+endm
+macro   IODELAYN    N
+    rept    N
+        DELAY
+    endm
+endm
+endif
+
+;----------------------------------------------------------------------------
+; PM_rtcISR - Real time clock interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the timer interrupt, to dispatch control
+; to high level C based subroutines. We save the state of all registers
+; in this routine, and switch to a local stack. Interrupts are *off*
+; when we call the user code.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. Make sure your C code executes as
+;       quickly as possible, since a timer overrun will simply hang the
+;       system.
+;----------------------------------------------------------------------------
+cprocfar    _PM_rtcISR
+
+        push    ds                  ; Save value of DS
+        push    es
+        pushad                      ; Save _all_ extended registers
+        cld                         ; Clear direction flag
+
+; Clear priority interrupt controller and re-enable interrupts so we
+; dont lock things up for long.
+
+        mov     al,20h
+        out     0A0h,al
+        out     020h,al
+
+; Clear real-time clock timeout
+
+        in      al,70h              ; Read CMOS index register
+        push    _ax                 ;  and save for later
+        IODELAYN 3
+        mov     al,0Ch
+        out     70h,al
+        IODELAYN 5
+        in      al,71h
+
+; Call the C interrupt handler function
+
+        LOAD_DS                     ; Load DS register
+        cmp     [BYTE RtcInside],1  ; Check for mutual exclusion
+        je      @@Exit
+        mov     [BYTE RtcInside],1
+        sti                         ; Re-enable interrupts
+        NEWSTK  RtcStack            ; Switch to local stack
+        call    [CPTR _PM_rtcHandler]
+        RESTSTK RtcStack            ; Restore previous stack
+        mov     [BYTE RtcInside],0
+
+@@Exit: pop     _ax
+        out     70h,al              ; Restore CMOS index register
+        popad                       ; Restore all extended registers
+        pop     es
+        pop     ds
+        iret                        ; Return from interrupt
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_keyISR - keyboard interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the keyboard interrupt, to dispatch control
+; to high level C based subroutines. We save the state of all registers
+; in this routine, and switch to a local stack. Interrupts are *off*
+; when we call the user code.
+;
+; NOTE: This routine switches to a local stack before calling any C code,
+;       and hence is _not_ re-entrant. However we ensure within this routine
+;       mutual exclusion to the keyboard handling routine.
+;----------------------------------------------------------------------------
+cprocfar    _PM_keyISR
+
+        push    ds              ; Save value of DS
+        push    es
+        pushad                  ; Save _all_ extended registers
+        cld                     ; Clear direction flag
+
+        LOAD_DS                 ; Load DS register
+
+        cmp     [BYTE KyInside],1   ; Check for mutual exclusion
+        je      @@Reissued
+
+        mov     [BYTE KyInside],1
+        NEWSTK  KyStack         ; Switch to local stack
+        call    [CPTR _PM_keyHandler]   ; Call C code
+        RESTSTK KyStack         ; Restore previous stack
+        mov     [BYTE KyInside],0
+
+@@Exit: popad                   ; Restore all extended registers
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+; When the BIOS keyboard handler needs to change the SHIFT status lights
+; on the keyboard, in the process of doing this the keyboard controller
+; re-issues another interrupt, while the current handler is still executing.
+; If we recieve another interrupt while still handling the current one,
+; then simply chain directly to the previous handler.
+;
+; Note that for most DOS extenders, the real mode interrupt handler that we
+; install takes care of this for us.
+
+@@Reissued:
+ifdef   TNT
+        push    eax
+        push    ebx
+        push    ecx
+        pushfd                  ; Push flags on stack to simulate interrupt
+        mov     ax,250Eh        ; Call real mode procedure function
+        mov     ebx,[_PM_prevRealKey]
+        mov     ecx,1           ; Copy real mode flags to real mode stack
+        int     21h             ; Call the real mode code
+        popfd
+        pop     ecx
+        pop     ebx
+        pop     eax
+else
+        pushf
+ifdef   USE_NASM
+        call far dword [_PM_prevKey]
+else
+        call    [_PM_prevKey]
+endif
+endif
+        jmp     @@Exit
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_chainPrevkey - Chain to previous key interrupt and return
+;----------------------------------------------------------------------------
+; Chains to the previous key interrupt routine and returns control
+; back to the high level interrupt handler.
+;----------------------------------------------------------------------------
+cprocstart  PM_chainPrevKey
+
+ifdef   TNT
+        push    eax
+        push    ebx
+        push    ecx
+        pushfd                  ; Push flags on stack to simulate interrupt
+        mov     ax,250Eh        ; Call real mode procedure function
+        mov     ebx,[_PM_prevRealKey]
+        mov     ecx,1           ; Copy real mode flags to real mode stack
+        int     21h             ; Call the real mode code
+        popfd
+        pop     ecx
+        pop     ebx
+        pop     eax
+        ret
+else
+
+; YIKES! For some strange reason, when execution returns from the
+; previous keyboard handler, interrupts are re-enabled!! Since we expect
+; interrupts to remain off during the duration of our handler, this can
+; cause havoc. However our stack macros always turn off interrupts, so they
+; will be off when we exit this routine. Obviously there is a tiny weeny
+; window when interrupts will be enabled, but there is nothing we can
+; do about this.
+
+        SWAPSTK KyStack         ; Swap back to previous stack
+        pushf                   ; Push flags on stack to simulate interrupt
+ifdef   USE_NASM
+        call far dword [_PM_prevKey]
+else
+        call    [_PM_prevKey]
+endif
+        SWAPSTK KyStack         ; Swap back to C stack again
+        ret
+endif
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_key15ISR - Int 15h keyboard interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; This routine gets called if we have been called to handle the Int 15h
+; keyboard interrupt callout from real mode.
+;
+;   Entry:  AX  - Hardware scan code to process
+;   Exit:   AX  - Hardware scan code to process (0 to ignore)
+;----------------------------------------------------------------------------
+cprocfar    _PM_key15ISR
+
+        push    ds
+        push    es
+        LOAD_DS
+        cmp     ah,4Fh
+        jnz     @@NotOurs       ; Quit if not keyboard callout
+
+        pushad
+        cld                     ; Clear direction flag
+        xor     ah,ah           ; AX := scan code
+        NEWSTK  Ky15Stack       ; Switch to local stack
+        push    _ax
+        call    [CPTR _PM_key15Handler] ; Call C code
+        _add    sp,2,4
+        RESTSTK Ky15Stack       ; Restore previous stack
+        test    ax,ax
+        jz      @@1
+        stc                     ; Set carry to process as normal
+        jmp     @@2
+@@1:    clc                     ; Clear carry to ignore scan code
+@@2:    popad
+        jmp     @@Exit          ; We are done
+
+@@NotOurs:
+ifdef   TNT
+        push    eax
+        push    ebx
+        push    ecx
+        pushfd                  ; Push flags on stack to simulate interrupt
+        mov     ax,250Eh        ; Call real mode procedure function
+        mov     ebx,[_PM_prevRealKey15]
+        mov     ecx,1           ; Copy real mode flags to real mode stack
+        int     21h             ; Call the real mode code
+        popfd
+        pop     ecx
+        pop     ebx
+        pop     eax
+else
+        pushf
+ifdef   USE_NASM
+        call far dword [_PM_prevKey15]
+else
+        call    [_PM_prevKey15]
+endif
+endif
+@@Exit: pop     es
+        pop     ds
+        retf    4
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_breakISR - Control Break interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the Ctrl-Break interrupt. We simply set
+; the Ctrl-Break flag to a 1 and leave (note that this is accessed through
+; a far pointer, as it may well be located in conventional memory).
+;----------------------------------------------------------------------------
+cprocfar    _PM_breakISR
+
+        sti
+        push    ds              ; Save value of DS
+        push    es
+        push    _bx
+
+        LOAD_DS                 ; Load DS register
+        mov     ebx,[_PM_ctrlBPtr]
+        mov     [UINT _ES _bx],1
+
+; Run alternate break handler code if installed
+
+        cmp     [CPTR _PM_breakHandler],0
+        je      @@Exit
+
+        pushad
+        mov     _ax,1
+        push    _ax
+        call    [CPTR _PM_breakHandler] ; Call C code
+        pop     _ax
+        popad
+
+@@Exit: pop     _bx
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_ctrlBreakHit(int clearFlag)
+;----------------------------------------------------------------------------
+; Returns the current state of the Ctrl-Break flag and possibly clears it.
+;----------------------------------------------------------------------------
+cprocstart  PM_ctrlBreakHit
+
+        ARG     clearFlag:UINT
+
+        enter_c
+        pushf                   ; Save interrupt status
+        push    es
+        mov     ebx,[_PM_ctrlBPtr]
+        cli                     ; No interrupts thanks!
+        mov     _ax,[_ES _bx]
+        test    [BYTE clearFlag],1
+        jz      @@Done
+        mov     [UINT _ES _bx],0
+
+@@Done: pop     es
+        popf                    ; Restore interrupt status
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_ctrlCISR - Control Break interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Hardware interrupt handler for the Ctrl-C interrupt. We simply set
+; the Ctrl-C flag to a 1 and leave (note that this is accessed through
+; a far pointer, as it may well be located in conventional memory).
+;----------------------------------------------------------------------------
+cprocfar    _PM_ctrlCISR
+
+        sti
+        push    ds              ; Save value of DS
+        push    es
+        push    _bx
+
+        LOAD_DS                 ; Load DS register
+        mov     ebx,[_PM_ctrlCPtr]
+        mov     [UINT _ES _bx],1
+
+; Run alternate break handler code if installed
+
+        cmp     [CPTR _PM_breakHandler],0
+        je      @@Exit
+
+        pushad
+        mov     _ax,0
+        push    _ax
+        call    [CPTR _PM_breakHandler] ; Call C code
+        pop     _ax
+        popad
+
+@@Exit: pop     _bx
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+        iretd
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_ctrlCHit(int clearFlag)
+;----------------------------------------------------------------------------
+; Returns the current state of the Ctrl-C flag and possibly clears it.
+;----------------------------------------------------------------------------
+cprocstart  PM_ctrlCHit
+
+        ARG     clearFlag:UINT
+
+        enter_c
+        pushf                   ; Save interrupt status
+        push    es
+        mov     ebx,[_PM_ctrlCPtr]
+        cli                     ; No interrupts thanks!
+        mov     _ax,[_ES _bx]
+        test    [BYTE clearFlag],1
+        jz      @@Done
+        mov     [UINT _ES _bx],0
+
+@@Done:
+        pop     es
+        popf                    ; Restore interrupt status
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PM_criticalISR - Control Error handler interrupt subroutine dispatcher
+;----------------------------------------------------------------------------
+; Interrupt handler for the MSDOS Critical Error interrupt, to dispatch
+; control to high level C based subroutines. We save the state of all
+; registers in this routine, and switch to a local stack. We also pass
+; the values of the AX and DI registers to the as pointers, so that the
+; values can be modified before returning to MSDOS.
+;----------------------------------------------------------------------------
+cprocfar    _PM_criticalISR
+
+        sti
+        push    ds              ; Save value of DS
+        push    es
+        push    _bx             ; Save register values changed
+        cld                     ; Clear direction flag
+
+        LOAD_DS                 ; Load DS register
+        mov     ebx,[_PM_critPtr]
+        mov     [_ES _bx],ax
+        mov     [_ES _bx+2],di
+
+; Run alternate critical handler code if installed
+
+        cmp     [CPTR _PM_critHandler],0
+        je      @@NoAltHandler
+
+        pushad
+        push    _di
+        push    _ax
+        call    [CPTR _PM_critHandler]  ; Call C code
+        _add    sp,4,8
+        popad
+
+        pop     _bx
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+@@NoAltHandler:
+        mov     ax,3            ; Tell MSDOS to fail the operation
+        pop     _bx
+        pop     es
+        pop     ds
+        iret                    ; Return from interrupt
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_criticalError(int *axVal,int *diVal,int clearFlag)
+;----------------------------------------------------------------------------
+; Returns the current state of the critical error flags, and the values that
+; MSDOS passed in the AX and DI registers to our handler.
+;----------------------------------------------------------------------------
+cprocstart  PM_criticalError
+
+        ARG     axVal:DPTR, diVal:DPTR, clearFlag:UINT
+
+        enter_c
+        pushf                   ; Save interrupt status
+        push    es
+        mov     ebx,[_PM_critPtr]
+        cli                     ; No interrupts thanks!
+        xor     _ax,_ax
+        xor     _di,_di
+        mov     ax,[_ES _bx]
+        mov     di,[_ES _bx+2]
+        test    [BYTE clearFlag],1
+        jz      @@NoClear
+        mov     [ULONG _ES _bx],0
+@@NoClear:
+        _les    _bx,[axVal]
+        mov     [_ES _bx],_ax
+        _les    _bx,[diVal]
+        mov     [_ES _bx],_di
+        pop     es
+        popf                    ; Restore interrupt status
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setMouseHandler(int mask, PM_mouseHandler mh)
+;----------------------------------------------------------------------------
+cprocstart  _PM_setMouseHandler
+
+        ARG     mouseMask:UINT
+
+        enter_c
+        push    es
+
+        mov     ax,0Ch          ; AX := Function 12 - install interrupt sub
+        mov     _cx,[mouseMask] ; CX := mouse mask
+        mov     _dx,offset _PM_mouseISR
+        push    cs
+        pop     es              ; ES:_DX -> mouse handler
+        int     33h             ; Call mouse driver
+
+        pop     es
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_mousePMCB(void)
+;----------------------------------------------------------------------------
+; Mouse realmode callback routine. Upon entry to this routine, we recieve
+; the following from the DPMI server:
+;
+;   Entry:  DS:_SI  -> Real mode stack at time of call
+;           ES:_DI  -> Real mode register data structure
+;           SS:_SP  -> Locked protected mode stack to use
+;----------------------------------------------------------------------------
+cprocfar    _PM_mousePMCB
+
+        pushad
+        mov     eax,[es:_di+1Ch]    ; Load register values from real mode
+        mov     ebx,[es:_di+10h]
+        mov     ecx,[es:_di+18h]
+        mov     edx,[es:_di+14h]
+        mov     esi,[es:_di+04h]
+        mov     edi,[es:_di]
+        call    _PM_mouseISR        ; Call the mouse handler
+        popad
+
+        mov     ax,[ds:_si]
+        mov     [es:_di+2Ah],ax     ; Plug in return IP address
+        mov     ax,[ds:_si+2]
+        mov     [es:_di+2Ch],ax     ; Plug in return CS value
+        add     [WORD es:_di+2Eh],4 ; Remove return address from stack
+        iret                        ; Go back to real mode!
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_int10PMCB(void)
+;----------------------------------------------------------------------------
+; int10 realmode callback routine. Upon entry to this routine, we recieve
+; the following from the DPMI server:
+;
+;   Entry:  DS:ESI  -> Real mode stack at time of call
+;           ES:EDI  -> Real mode register data structure
+;           SS:ESP  -> Locked protected mode stack to use
+;----------------------------------------------------------------------------
+cprocfar        _PM_int10PMCB
+
+        pushad
+        push    ds
+        push    es
+        push    fs
+
+        pushfd
+        pop     eax
+        mov     [es:edi+20h],ax     ; Save return flag status
+        mov     ax,[ds:esi]
+        mov     [es:edi+2Ah],ax     ; Plug in return IP address
+        mov     ax,[ds:esi+2]
+        mov     [es:edi+2Ch],ax     ; Plug in return CS value
+        add     [WORD es:edi+2Eh],4 ; Remove return address from stack
+
+; Call the install int10 handler in protected mode. This function gets called
+; with DS set to the current data selector, and ES:EDI pointing the the
+; real mode DPMI register structure at the time of the interrupt. The
+; handle must be written in assembler to be able to extract the real mode
+; register values from the structure
+
+        push    es
+        pop     fs                  ; FS:EDI -> real mode registers
+        LOAD_DS
+        NEWSTK  Int10Stack          ; Switch to local stack
+
+        call    [_PM_int10Handler]
+
+        RESTSTK Int10Stack          ; Restore previous stack
+        pop     fs
+        pop     es
+        pop     ds
+        popad
+        iret                        ; Go back to real mode!
+
+cprocend
+
+cpublic _PM_pmsmxCodeEnd
+
+endcodeseg  _pmsmx
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm
new file mode 100755
index 0000000..34985a9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm
@@ -0,0 +1,652 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;*            Based on original code Copyright 1994 Otto Chrons
+;*
+;* Language:    80386 Assembler, TASM 4.0 or later
+;* Environment: IBM PC 32 bit protected mode
+;*
+;* Description: Low level page fault handler for virtual linear framebuffers.
+;*
+;****************************************************************************
+
+        IDEAL
+        JUMPS
+
+include "scitech.mac"           ; Memory model macros
+
+header      _vflat              ; Set up memory model
+
+VFLAT_START     EQU 0F0000000h
+VFLAT_END       EQU 0F03FFFFFh
+PAGE_PRESENT    EQU 1
+PAGE_NOTPRESENT EQU 0
+PAGE_READ       EQU 0
+PAGE_WRITE      EQU 2
+
+ifdef   DOS4GW
+
+;----------------------------------------------------------------------------
+; DOS4G/W flat linear framebuffer emulation.
+;----------------------------------------------------------------------------
+
+begdataseg  _vflat
+
+; Near pointers to the page directory base and our page tables. All of
+; this memory is always located in the first Mb of DOS memory.
+
+PDBR            dd  0               ; Page directory base register (CR3)
+accessPageAddr  dd  0
+accessPageTable dd  0
+
+; CauseWay page directory & 1st page table linear addresses.
+
+CauseWayDIRLinear dd 0
+CauseWay1stLinear dd 0
+
+; Place to store a copy of the original Page Table Directory before we
+; intialised our virtual buffer code.
+
+pageDirectory:  resd 1024           ; Saved page table directory
+
+ValidCS         dw  0               ; Valid CS for page faults
+Ring0CS         dw  0               ; Our ring 0 code selector
+LastPage        dd  0               ; Last page we mapped in
+BankFuncBuf:    resb 101            ; Place to store bank switch code
+BankFuncPtr     dd  offset BankFuncBuf
+
+INT14Gate:
+INT14Offset     dd      0           ; eip of original vector
+INT14Selector   dw      0           ; cs of original vector
+
+        cextern _PM_savedDS,USHORT
+        cextern VF_haveCauseWay,BOOL
+
+enddataseg  _vflat
+
+begcodeseg  _vflat              ; Start of code segment
+
+        cextern VF_malloc,FPTR
+
+;----------------------------------------------------------------------------
+; PF_handler64k - Page fault handler for 64k banks
+;----------------------------------------------------------------------------
+; The handler below is a 32 bit ring 0 page fault handler.  It receives
+; control immediately after any page fault or after an IRQ6 (hardware
+; interrupt). This provides the fastest possible handling of page faults
+; since it jump directly here.  If this is a page fault, the number
+; immediately on the stack will be an error code, at offset 4 will be
+; the eip of the faulting instruction, at offset 8 will be the cs of the
+; faulting instruction.  If it is a hardware interrupt, it will not have
+; the error code and the eflags will be at offset 8.
+;----------------------------------------------------------------------------
+cprocfar    PF_handler64k
+
+; Check if this is a processor exeception or a page fault
+
+        push    eax
+        mov     ax,[cs:ValidCS]     ; Use CS override to access data
+        cmp     [ss:esp+12],ax      ; Is this a page fault?
+        jne     @@ToOldHandler      ; Nope, jump to the previous handler
+
+; Get address of page fault and check if within our handlers range
+
+        mov     eax,cr2             ; EBX has page fault linear address
+        cmp     eax,VFLAT_START     ; Is the fault less than ours?
+        jb      @@ToOldHandler      ; Yep, go to previous handler
+        cmp     eax,VFLAT_END       ; Is the fault more than ours?
+        jae     @@ToOldHandler      ; Yep, go to previous handler
+
+; This is our page fault, so we need to handle it
+
+        pushad
+        push    ds
+        push    es
+        mov     ebx,eax             ; EBX := page fault address
+        and     ebx,invert 0FFFFh   ; Mask to 64k bank boundary
+        mov     ds,[cs:_PM_savedDS]; Load segment registers
+        mov     es,[cs:_PM_savedDS]
+
+; Map in the page table for our virtual framebuffer area for modification
+
+        mov     edi,[PDBR]          ; EDI points to page directory
+        mov     edx,ebx             ; EDX = linear address
+        shr     edx,22              ; EDX = offset to page directory
+        mov     edx,[edx*4+edi]     ; EDX = physical page table address
+        mov     eax,edx
+        mov     edx,[accessPageTable]
+        or      eax,7
+        mov     [edx],eax
+        mov     eax,cr3
+        mov     cr3,eax             ; Update page table cache
+
+; Mark all pages valid for the new page fault area
+
+        mov     esi,ebx             ; ESI := linear address for page
+        shr     esi,10
+        and     esi,0FFFh           ; Offset into page table
+        add     esi,[accessPageAddr]
+ifdef   USE_NASM
+%assign off 0
+%rep 16
+        or      [DWORD esi+off],0000000001h ; Enable pages
+%assign off off+4
+%endrep
+else
+off = 0
+REPT    16
+        or      [DWORD esi+off],0000000001h ; Enable pages
+off = off+4
+ENDM
+endif
+
+; Mark all pages invalid for the previously mapped area
+
+        xchg    esi,[LastPage]      ; Save last page for next page fault
+        test    esi,esi
+        jz      @@DoneMapping       ; Dont update if first time round
+ifdef   USE_NASM
+%assign off 0
+%rep 16
+        or      [DWORD esi+off],0FFFFFFFEh  ; Disable pages
+%assign off off+4
+%endrep
+else
+off = 0
+REPT    16
+        and     [DWORD esi+off],0FFFFFFFEh  ; Disable pages
+off = off+4
+ENDM
+endif
+
+@@DoneMapping:
+        mov     eax,cr3
+        mov     cr3,eax             ; Flush the TLB
+
+; Now program the new SuperVGA starting bank address
+
+        mov     eax,ebx             ; EAX := page fault address
+        shr     eax,16
+        and     eax,0FFh            ; Mask to 0-255
+        call    [BankFuncPtr]       ; Call the bank switch function
+
+        pop     es
+        pop     ds
+        popad
+        pop     eax
+        add     esp,4               ; Pop the error code from stack
+        iretd                       ; Return to faulting instruction
+
+@@ToOldHandler:
+        pop     eax
+ifdef   USE_NASM
+        jmp far dword [cs:INT14Gate]; Chain to previous handler
+else
+        jmp     [FWORD cs:INT14Gate]; Chain to previous handler
+endif
+
+cprocend
+
+;----------------------------------------------------------------------------
+; PF_handler4k  - Page fault handler for 4k banks
+;----------------------------------------------------------------------------
+; The handler below is a 32 bit ring 0 page fault handler.  It receives
+; control immediately after any page fault or after an IRQ6 (hardware
+; interrupt). This provides the fastest possible handling of page faults
+; since it jump directly here.  If this is a page fault, the number
+; immediately on the stack will be an error code, at offset 4 will be
+; the eip of the faulting instruction, at offset 8 will be the cs of the
+; faulting instruction.  If it is a hardware interrupt, it will not have
+; the error code and the eflags will be at offset 8.
+;----------------------------------------------------------------------------
+cprocfar    PF_handler4k
+
+; Fill in when we have tested all the 64Kb code
+
+ifdef   USE_NASM
+        jmp far dword [cs:INT14Gate]; Chain to previous handler
+else
+        jmp     [FWORD cs:INT14Gate]; Chain to previous handler
+endif
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void InstallFaultHandler(void *baseAddr,int bankSize)
+;----------------------------------------------------------------------------
+; Installes the page fault handler directly int the interrupt descriptor
+; table for maximum performance. This of course requires ring 0 access,
+; but none of this stuff will run without ring 0!
+;----------------------------------------------------------------------------
+cprocstart  InstallFaultHandler
+
+        ARG     baseAddr:ULONG, bankSize:UINT
+
+        enter_c
+
+        mov     [DWORD LastPage],0  ; No pages have been mapped
+        mov     ax,cs
+        mov     [ValidCS],ax        ; Save CS value for page faults
+
+; Put address of our page fault handler into the IDT directly
+
+        sub     esp,6               ; Allocate space on stack
+ifdef   USE_NASM
+        sidt    [ss:esp]            ; Store pointer to IDT
+else
+        sidt    [FWORD ss:esp]      ; Store pointer to IDT
+endif
+        pop     ax                  ; add esp,2
+        pop     eax                 ; Absolute address of IDT
+        add     eax,14*8            ; Point to Int #14
+
+; Note that Interrupt gates do not have the high and low word of the
+; offset in adjacent words in memory, there are 4 bytes separating them.
+
+        mov     ecx,[eax]           ; Get cs and low 16 bits of offset
+        mov     edx,[eax+6]         ; Get high 16 bits of offset in dx
+        shl     edx,16
+        mov     dx,cx               ; edx has offset
+        mov     [INT14Offset],edx   ; Save offset
+        shr     ecx,16
+        mov     [INT14Selector],cx  ; Save original cs
+        mov     [eax+2],cs          ; Install new cs
+        mov     edx,offset PF_handler64k
+        cmp     [UINT bankSize],4
+        jne     @@1
+        mov     edx,offset PF_handler4k
+@@1:    mov     [eax],dx            ; Install low word of offset
+        shr     edx,16
+        mov     [eax+6],dx          ; Install high word of offset
+
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void RemoveFaultHandler(void)
+;----------------------------------------------------------------------------
+; Closes down the virtual framebuffer services and restores the previous
+; page fault handler.
+;----------------------------------------------------------------------------
+cprocstart  RemoveFaultHandler
+
+        enter_c
+
+; Remove page fault handler from IDT
+
+        sub     esp,6               ; Allocate space on stack
+ifdef   USE_NASM
+        sidt    [ss:esp]            ; Store pointer to IDT
+else
+        sidt    [FWORD ss:esp]      ; Store pointer to IDT
+endif
+
+        pop     ax                  ; add esp,2
+        pop     eax                 ; Absolute address of IDT
+        add     eax,14*8            ; Point to Int #14
+        mov     cx,[INT14Selector]
+        mov     [eax+2],cx          ; Restore original CS
+        mov     edx,[INT14Offset]
+        mov     [eax],dx            ; Install low word of offset
+        shr     edx,16
+        mov     [eax+6],dx          ; Install high word of offset
+
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void InstallBankFunc(int codeLen,void *bankFunc)
+;----------------------------------------------------------------------------
+; Installs the bank switch function by relocating it into our data segment
+; and making it into a callable function. We do it this way to make the
+; code identical to the way that the VflatD devices work under Windows.
+;----------------------------------------------------------------------------
+cprocstart  InstallBankFunc
+
+        ARG     codeLen:UINT, bankFunc:DPTR
+
+        enter_c
+
+        mov     esi,[bankFunc]      ; Copy the code into buffer
+        mov     edi,offset BankFuncBuf
+        mov     ecx,[codeLen]
+    rep movsb
+        mov     [BYTE edi],0C3h     ; Terminate the function with a near ret
+
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int InitPaging(void)
+;----------------------------------------------------------------------------
+; Initializes paging system. If paging is not enabled, builds a page table
+; directory and page tables for physical memory
+;
+;   Exit:       0   - Successful
+;               -1  - Couldn't initialize paging mechanism
+;----------------------------------------------------------------------------
+cprocstart  InitPaging
+
+        push    ebx
+        push    ecx
+        push    edx
+        push    esi
+        push    edi
+
+; Are we running under CauseWay?
+
+        mov     ax,0FFF9h
+        int     31h
+        jc      @@NotCauseway
+        cmp     ecx,"CAUS"
+        jnz     @@NotCauseway
+        cmp     edx,"EWAY"
+        jnz     @@NotCauseway
+
+        mov     [BOOL VF_haveCauseWay],1
+        mov     [CauseWayDIRLinear],esi
+        mov     [CauseWay1stLinear],edi
+
+; Check for DPMI
+
+        mov     ax,0ff00h
+        push    es
+        int     31h
+        pop     es
+        shr     edi,2
+        and     edi,3
+        cmp     edi,2
+        jz      @@ErrExit               ; Not supported under DPMI
+
+        mov     eax,[CauseWayDIRLinear]
+        jmp     @@CopyCR3
+
+@@NotCauseway:
+        mov     ax,cs
+        test    ax,3                    ; Which ring are we running
+        jnz     @@ErrExit               ; Needs zero ring to access
+                                        ; page tables (CR3)
+        mov     eax,cr0                 ; Load CR0
+        test    eax,80000000h           ; Is paging enabled?
+        jz      @@ErrExit               ; No, we must have paging!
+
+        mov     eax,cr3                 ; Load directory address
+        and     eax,0FFFFF000h
+
+@@CopyCR3:
+        mov     [PDBR],eax              ; Save it
+        mov     esi,eax
+        mov     edi,offset pageDirectory
+        mov     ecx,1024
+        cld
+        rep     movsd                   ; Copy the original page table directory
+        cmp     [DWORD accessPageAddr],0; Check if we have allocated page
+        jne     @@HaveRealMem           ; table already (we cant free it)
+
+        mov     eax,0100h               ; DPMI DOS allocate
+        mov     ebx,8192/16
+        int     31h                     ; Allocate 8192 bytes
+        and     eax,0FFFFh
+        shl     eax,4                   ; EAX points to newly allocated memory
+        add     eax,4095
+        and     eax,0FFFFF000h          ; Page align
+        mov     [accessPageAddr],eax
+
+@@HaveRealMem:
+        mov     eax,[accessPageAddr]    ; EAX -> page table in 1st Mb
+        shr     eax,12
+        and     eax,3FFh                ; Page table offset
+        shl     eax,2
+        cmp     [BOOL VF_haveCauseWay],0
+        jz      @@NotCW0
+        mov     ebx,[CauseWay1stLinear]
+        jmp     @@Put1st
+
+@@NotCW0:
+        mov     ebx,[PDBR]
+        mov     ebx,[ebx]
+        and     ebx,0FFFFF000h          ; Page table for 1st megabyte
+
+@@Put1st:
+        add     eax,ebx
+        mov     [accessPageTable],eax
+        sub     eax,eax                 ; No error
+        jmp     @@Exit
+
+@@ErrExit:
+        mov     eax,-1
+
+@@Exit: pop     edi
+        pop     esi
+        pop     edx
+        pop     ecx
+        pop     ebx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void ClosePaging(void)
+;----------------------------------------------------------------------------
+; Closes the paging system
+;----------------------------------------------------------------------------
+cprocstart  ClosePaging
+
+        push    eax
+        push    ecx
+        push    edx
+        push    esi
+        push    edi
+
+        mov     eax,[accessPageAddr]
+        call    AccessPage              ; Restore AccessPage mapping
+        mov     edi,[PDBR]
+        mov     esi,offset pageDirectory
+        mov     ecx,1024
+        cld
+        rep     movsd                   ; Restore the original page table directory
+
+@@Exit: pop     edi
+        pop     esi
+        pop     edx
+        pop     ecx
+        pop     eax
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; long AccessPage(long phys)
+;----------------------------------------------------------------------------
+; Maps a known page to given physical memory
+;   Entry:      EAX - Physical memory
+;   Exit:       EAX - Linear memory address of mapped phys mem
+;----------------------------------------------------------------------------
+cprocstatic     AccessPage
+
+        push    edx
+        mov     edx,[accessPageTable]
+        or      eax,7
+        mov     [edx],eax
+        mov     eax,cr3
+        mov     cr3,eax                 ; Update page table cache
+        mov     eax,[accessPageAddr]
+        pop     edx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; long GetPhysicalAddress(long linear)
+;----------------------------------------------------------------------------
+; Returns the physical address of linear address
+;   Entry:      EAX - Linear address to convert
+;   Exit:       EAX - Physical address
+;----------------------------------------------------------------------------
+cprocstatic     GetPhysicalAddress
+
+        push    ebx
+        push    edx
+        mov     edx,eax
+        shr     edx,22                  ; EDX is the directory offset
+        mov     ebx,[PDBR]
+        mov     edx,[edx*4+ebx]         ; Load page table address
+        push    eax
+        mov     eax,edx
+        call    AccessPage              ; Access the page table
+        mov     edx,eax
+        pop     eax
+        shr     eax,12
+        and     eax,03FFh               ; EAX offset into page table
+        mov     eax,[edx+eax*4]         ; Load physical address
+        and     eax,0FFFFF000h
+        pop     edx
+        pop     ebx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void CreatePageTable(long pageDEntry)
+;----------------------------------------------------------------------------
+; Creates a page table for specific address (4MB)
+;       Entry:  EAX - Page directory entry (top 10-bits of address)
+;----------------------------------------------------------------------------
+cprocstatic     CreatePageTable
+
+        push    ebx
+        push    ecx
+        push    edx
+        push    edi
+        mov     ebx,eax                 ; Save address
+        mov     eax,8192
+        push    eax
+        call    VF_malloc              ; Allocate page table directory
+        add     esp,4
+        add     eax,0FFFh
+        and     eax,0FFFFF000h          ; Page align (4KB)
+        mov     edi,eax                 ; Save page table linear address
+        sub     eax,eax                 ; Fill with zero
+        mov     ecx,1024
+        cld
+        rep     stosd                   ; Clear page table
+        sub     edi,4096
+        mov     eax,edi
+        call    GetPhysicalAddress
+        mov     edx,[PDBR]
+        or      eax,7                   ; Present/write/user bit
+        mov     [edx+ebx*4],eax         ; Save physical address into page directory
+        mov     eax,cr3
+        mov     cr3,eax                 ; Update page table cache
+        pop     edi
+        pop     edx
+        pop     ecx
+        pop     ebx
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags);
+;----------------------------------------------------------------------------
+; Maps physical memory into linear memory
+;   Entry:      pAddr   - Physical address
+;               lAddr   - Linear address
+;               pages   - Number of 4K pages to map
+;               flags   - Page flags
+;                           bit 0   =       present
+;                           bit 1   =       Read(0)/Write(1)
+;----------------------------------------------------------------------------
+cprocstart  MapPhysical2Linear
+
+        ARG     pAddr:ULONG, lAddr:ULONG, pages:UINT, pflags:UINT
+
+        enter_c
+
+        and     [ULONG pAddr],0FFFFF000h; Page boundary
+        and     [ULONG lAddr],0FFFFF000h; Page boundary
+        mov     ecx,[pflags]
+        and     ecx,11b                 ; Just two bits
+        or      ecx,100b                ; Supervisor bit
+        mov     [pflags],ecx
+
+        mov     edx,[lAddr]
+        shr     edx,22                  ; EDX = Directory
+        mov     esi,[PDBR]
+        mov     edi,[pages]             ; EDI page count
+        mov     ebx,[lAddr]
+
+@@CreateLoop:
+        mov     ecx,[esi+edx*4]         ; Load page table address
+        test    ecx,1                   ; Is it present?
+        jnz     @@TableOK
+        mov     eax,edx
+        call    CreatePageTable         ; Create a page table
+@@TableOK:
+        mov     eax,ebx
+        shr     eax,12
+        and     eax,3FFh
+        sub     eax,1024
+        neg     eax                     ; EAX = page count in this table
+        inc     edx                     ; Next table
+        mov     ebx,0                   ; Next time we'll map 1K pages
+        sub     edi,eax                 ; Subtract mapped pages from page count
+        jns     @@CreateLoop            ; Create more tables if necessary
+
+        mov     ecx,[pages]             ; ECX = Page count
+        mov     esi,[lAddr]
+        shr     esi,12                  ; Offset part isn't needed
+        mov     edi,[pAddr]
+@@MappingLoop:
+        mov     eax,esi
+        shr     eax,10                  ; EAX = offset to page directory
+        mov     ebx,[PDBR]
+        mov     eax,[eax*4+ebx]         ; EAX = page table address
+        call    AccessPage
+        mov     ebx,esi
+        and     ebx,3FFh                ; EBX = offset to page table
+        mov     edx,edi
+        add     edi,4096                ; Next physical address
+        inc     esi                     ; Next linear page
+        or      edx,[pflags]            ; Update flags...
+        mov     [eax+ebx*4],edx         ; Store page table entry
+        loop    @@MappingLoop
+        mov     eax,cr3
+        mov     cr3,eax                 ; Update page table cache
+
+        leave_c
+        ret
+
+cprocend
+
+endcodeseg  _vflat
+
+endif
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c
new file mode 100755
index 0000000..5447e57
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c
@@ -0,0 +1,72 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit SMX embedded systems development.
+*
+* Description:  SMX specific code for the CPU detection module.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* External timing function */
+
+void __ZTimerInit(void);
+
+/****************************************************************************
+REMARKS:
+Do nothing for DOS because we don't have thread priorities.
+****************************************************************************/
+#define SetMaxThreadPriority()      0
+
+/****************************************************************************
+REMARKS:
+Do nothing for DOS because we don't have thread priorities.
+****************************************************************************/
+#define RestoreThreadPriority(i)    (void)(i)
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    ulong resolution;
+
+    __ZTimerInit();
+    ULZTimerResolution(&resolution);
+    freq->low = (ulong)(10000000000.0 / resolution);
+    freq->high = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)                   \
+{                                       \
+    (t)->low = ULZReadTime() * 10000L;  \
+    (t)->high = 0;                      \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/event.c b/board/MAI/bios_emulator/scitech/src/pm/smx/event.c
new file mode 100755
index 0000000..533c261
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/event.c
@@ -0,0 +1,368 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit SMX embedded systems development
+*
+* Description:  32-bit SMX implementation for the SciTech cross platform
+*               event library.
+*
+****************************************************************************/
+
+#include "smx/ps2mouse.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+ibool _VARAPI   _EVT_useEvents = true;  /* True to use event handling   */
+ibool _VARAPI   _EVT_installed = 0;     /* Event handers installed?     */
+uchar _VARAPI   *_EVT_biosPtr = NULL;   /* Pointer to the BIOS data area */
+static ibool    haveMouse = false;      /* True if we have a mouse      */
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* External assembler functions */
+
+void    EVTAPI _EVT_pollJoystick(void);
+uint    EVTAPI _EVT_disableInt(void);
+uint    EVTAPI _EVT_restoreInt(uint flags);
+void    EVTAPI _EVT_codeStart(void);
+void    EVTAPI _EVT_codeEnd(void);
+void    EVTAPI _EVT_cCodeStart(void);
+void    EVTAPI _EVT_cCodeEnd(void);
+int     EVTAPI _EVT_getKeyCode(void);
+int     EVTAPI EVT_rdinx(int port,int index);
+void    EVTAPI EVT_wrinx(int port,int index,int value);
+
+/****************************************************************************
+REMARKS:
+Do nothing for DOS, because we are fully interrupt driven.
+****************************************************************************/
+#define _EVT_pumpMessages()
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{
+    return (ulong)PM_getLong(_EVT_biosPtr+0x6C) * 55UL;
+}
+
+/****************************************************************************
+REMARKS:
+Include generic raw scancode keyboard module.
+****************************************************************************/
+#include "common/keyboard.c"
+
+/****************************************************************************
+REMARKS:
+Determines if we have a mouse attached and functioning.
+****************************************************************************/
+static ibool detectMouse(void)
+{
+   return(ps2Query());
+}
+
+/****************************************************************************
+PARAMETERS:
+what        - Event code
+message     - Event message
+x,y         - Mouse position at time of event
+but_stat    - Mouse button status at time of event
+
+REMARKS:
+Adds a new mouse event to the event queue. This routine is called from within
+the mouse interrupt subroutine, so it must be efficient.
+
+NOTE:   Interrupts MUST be OFF while this routine is called to ensure we have
+	mutually exclusive access to our internal data structures for
+	interrupt driven systems (like under DOS).
+****************************************************************************/
+static void addMouseEvent(
+    uint what,
+    uint message,
+    int x,
+    int y,
+    int mickeyX,
+    int mickeyY,
+    uint but_stat)
+{
+    event_t evt;
+
+    if (EVT.count < EVENTQSIZE) {
+	/* Save information in event record. */
+	evt.when = _EVT_getTicks();
+	evt.what = what;
+	evt.message = message;
+	evt.modifiers = but_stat;
+	evt.where_x = x;                /* Save mouse event position    */
+	evt.where_y = y;
+	evt.relative_x = mickeyX;
+	evt.relative_y = mickeyY;
+	evt.modifiers |= EVT.keyModifiers;
+	addEvent(&evt);                 /* Add to tail of event queue   */
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+mask        - Event mask
+butstate    - Button state
+x           - Mouse x coordinate
+y           - Mouse y coordinate
+
+REMARKS:
+Mouse event handling routine. This gets called when a mouse event occurs,
+and we call the addMouseEvent() routine to add the appropriate mouse event
+to the event queue.
+
+Note: Interrupts are ON when this routine is called by the mouse driver code.
+/*AM: NOTE: This function has not actually been ported from DOS yet and should not */
+/*AM: be installed until it is. */
+****************************************************************************/
+static void EVTAPI mouseISR(
+    uint mask,
+    uint butstate,
+    int x,
+    int y,
+    int mickeyX,
+    int mickeyY)
+{
+    RMREGS  regs;
+    uint    ps;
+
+    if (mask & 1) {
+	/* Save the current mouse coordinates */
+	EVT.mx = x; EVT.my = y;
+
+	/* If the last event was a movement event, then modify the last
+	 * event rather than post a new one, so that the queue will not
+	 * become saturated. Before we modify the data structures, we
+	 * MUST ensure that interrupts are off.
+	 */
+	ps = _EVT_disableInt();
+	if (EVT.oldMove != -1) {
+	    EVT.evtq[EVT.oldMove].where_x = x;          /* Modify existing one  */
+	    EVT.evtq[EVT.oldMove].where_y = y;
+	    EVT.evtq[EVT.oldMove].relative_x += mickeyX;
+	    EVT.evtq[EVT.oldMove].relative_y += mickeyY;
+	    }
+	else {
+	    EVT.oldMove = EVT.freeHead;         /* Save id of this move event   */
+	    addMouseEvent(EVT_MOUSEMOVE,0,x,y,mickeyX,mickeyY,butstate);
+	    }
+	_EVT_restoreInt(ps);
+	}
+    if (mask & 0x2A) {
+	ps = _EVT_disableInt();
+	addMouseEvent(EVT_MOUSEDOWN,mask >> 1,x,y,0,0,butstate);
+	EVT.oldMove = -1;
+	_EVT_restoreInt(ps);
+	}
+    if (mask & 0x54) {
+	ps = _EVT_disableInt();
+	addMouseEvent(EVT_MOUSEUP,mask >> 2,x,y,0,0,butstate);
+	EVT.oldMove = -1;
+	_EVT_restoreInt(ps);
+	}
+    EVT.oldKey = -1;
+}
+
+/****************************************************************************
+REMARKS:
+Keyboard interrupt handler function.
+
+NOTE:   Interrupts are OFF when this routine is called by the keyboard ISR,
+	and we leave them OFF the entire time. This has been modified to work
+      in conjunction with smx keyboard handler.
+****************************************************************************/
+static void EVTAPI keyboardISR(void)
+{
+   PM_chainPrevKey();
+    processRawScanCode(PM_inpb(0x60));
+    PM_outpb(0x20,0x20);
+}
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort()
+{
+    EVT_exit();
+    PM_fatalError("Unhandled exception!");
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    int     i;
+
+    EVT.mouseMove = mouseMove;
+    _EVT_biosPtr = PM_getBIOSPointer();
+    EVT_resume();
+}
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVTAPI EVT_resume(void)
+{
+    static int      locked = 0;
+    int             stat;
+    uchar           mods;
+    PM_lockHandle   lh;
+
+    if (_EVT_useEvents) {
+	/* Initialise the event queue and enable our interrupt handlers */
+	initEventQueue();
+	PM_setKeyHandler(keyboardISR);
+	if ((haveMouse = detectMouse()) != 0)
+	    PM_setMouseHandler(0xFFFF,mouseISR);
+
+	/* Read the keyboard modifier flags from the BIOS to get the
+	 * correct initialisation state. The only state we care about is
+	 * the correct toggle state flags such as SCROLLLOCK, NUMLOCK and
+	 * CAPSLOCK.
+	 */
+	EVT.keyModifiers = 0;
+	mods = PM_getByte(_EVT_biosPtr+0x17);
+	if (mods & 0x10)
+	    EVT.keyModifiers |= EVT_SCROLLLOCK;
+	if (mods & 0x20)
+	    EVT.keyModifiers |= EVT_NUMLOCK;
+	if (mods & 0x40)
+	    EVT.keyModifiers |= EVT_CAPSLOCK;
+
+	/* Lock all of the code and data used by our protected mode interrupt
+	 * handling routines, so that it will continue to work correctly
+	 * under real mode.
+	 */
+	if (!locked) {
+	    /* It is difficult to ensure that we lock our global data, so we
+	     * do this by taking the address of a variable locking all data
+	     * 2Kb on either side. This should properly cover the global data
+	     * used by the module (the other alternative is to declare the
+	     * variables in assembler, in which case we know it will be
+	     * correct).
+	     */
+	    stat  = !PM_lockDataPages(&EVT,sizeof(EVT),&lh);
+	    stat |= !PM_lockDataPages(&_EVT_biosPtr,sizeof(_EVT_biosPtr),&lh);
+	    stat |= !PM_lockCodePages((__codePtr)_EVT_cCodeStart,(int)_EVT_cCodeEnd-(int)_EVT_cCodeStart,&lh);
+	    stat |= !PM_lockCodePages((__codePtr)_EVT_codeStart,(int)_EVT_codeEnd-(int)_EVT_codeStart,&lh);
+	    if (stat) {
+		PM_fatalError("Page locking services failed - interrupt handling not safe!");
+		exit(1);
+		}
+	    locked = 1;
+	    }
+
+	_EVT_installed = true;
+	}
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    if (haveMouse) {
+	ps2MouseStop();
+	ps2MouseStart( 0, xRes, 0, yRes, -1, -1, -1);
+	}
+}
+
+/****************************************************************************
+REMARKS
+Modifes the mouse coordinates as necessary if scaling to OS coordinates,
+and sets the OS mouse cursor position.
+****************************************************************************/
+void _EVT_setMousePos(
+    int *x,
+    int *y)
+{
+    if (haveMouse)
+	ps2MouseMove(*x, *y);
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVTAPI EVT_suspend(void)
+{
+    uchar   mods;
+
+    if (_EVT_installed) {
+	PM_restoreKeyHandler();
+    if (haveMouse)
+	PM_restoreMouseHandler();
+
+	/* Set the keyboard modifier flags in the BIOS to our values */
+	EVT_allowLEDS(true);
+	mods = PM_getByte(_EVT_biosPtr+0x17) & ~0x70;
+	if (EVT.keyModifiers & EVT_SCROLLLOCK)
+	    mods |= 0x10;
+	if (EVT.keyModifiers & EVT_NUMLOCK)
+	    mods |= 0x20;
+	if (EVT.keyModifiers & EVT_CAPSLOCK)
+	    mods |= 0x40;
+	PM_setByte(_EVT_biosPtr+0x17,mods);
+
+	/* Flag that we are no longer installed */
+	_EVT_installed = false;
+	}
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVTAPI EVT_exit(void)
+{
+    EVT_suspend();
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h
new file mode 100755
index 0000000..3ff8daa
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h
@@ -0,0 +1,29 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit SMX embedded systems development.
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c b/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c
new file mode 100755
index 0000000..99ee3d4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c
@@ -0,0 +1,1187 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32 bit SMX embedded systems development.
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "ztimerc.h"
+#include "event.h"
+#include "mtrr.h"
+#include "pm_help.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <dos.h>
+#include <conio.h>
+#ifdef  __GNUC__
+#include <unistd.h>
+#include <sys/nearptr.h>
+#include <sys/stat.h>
+#else
+#include <direct.h>
+#endif
+#ifdef  __BORLANDC__
+#pragma warn -par
+#endif
+
+/*--------------------------- Global variables ----------------------------*/
+
+typedef struct {
+    int     oldMode;
+    int     old50Lines;
+    } DOS_stateBuf;
+
+#define MAX_RM_BLOCKS   10
+
+static struct {
+    void    *p;
+    uint    tag;
+    } rmBlocks[MAX_RM_BLOCKS];
+
+static uint     VESABuf_len = 1024;     /* Length of the VESABuf buffer     */
+static void     *VESABuf_ptr = NULL;    /* Near pointer to VESABuf          */
+static uint     VESABuf_rseg;           /* Real mode segment of VESABuf     */
+static uint     VESABuf_roff;           /* Real mode offset of VESABuf      */
+static void     (PMAPIP fatalErrorCleanup)(void) = NULL;
+ushort _VARAPI  _PM_savedDS = 0;
+static ulong    PDB = 0,*pPDB = NULL;
+static uint     VXD_version = -1;
+
+/*----------------------------- Implementation ----------------------------*/
+
+ulong   _ASMAPI _PM_getPDB(void);
+void    _ASMAPI _PM_VxDCall(VXD_regs *regs,uint off,uint sel);
+
+/****************************************************************************
+REMARKS:
+External function to call the PMHELP helper VxD.
+****************************************************************************/
+void PMAPI PM_VxDCall(
+    VXD_regs *regs)
+{
+}
+
+/****************************************************************************
+RETURNS:
+BCD coded version number of the VxD, or 0 if not loaded (ie: 0x202 - 2.2)
+
+REMARKS:
+This function gets the version number for the VxD that we have connected to.
+****************************************************************************/
+uint PMAPI PMHELP_getVersion(void)
+{
+    return VXD_version = 0;
+}
+
+void PMAPI PM_init(void)
+{
+#ifndef REALMODE
+    MTRR_init();
+#endif
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+RETURNS:
+Error code describing the result.
+
+REMARKS:
+Function to enable write combining for the specified region of memory.
+****************************************************************************/
+int PMAPI PM_enableWriteCombine(
+    ulong base,
+    ulong size,
+    uint type)
+{
+#ifndef REALMODE
+    return MTRR_enableWriteCombine(base,size,type);
+#else
+    return PM_MTRR_NOT_SUPPORTED;
+#endif
+}
+
+ibool PMAPI PM_haveBIOSAccess(void)
+{ return false; }
+
+long PMAPI PM_getOSType(void)
+{ return _OS_SMX; }
+
+int PMAPI PM_getModeType(void)
+{ return PM_386; }
+
+void PMAPI PM_backslash(char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '\\') {
+	s[pos] = '\\';
+	s[pos+1] = '\0';
+	}
+}
+
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+void MGLOutput(char *);
+
+void PMAPI PM_fatalError(const char *msg)
+{
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+    MGLOutput(msg);
+/* No support for fprintf() under smx currently! */
+/*  fprintf(stderr,"%s\n", msg); */
+    exit(1);
+}
+
+static void ExitVBEBuf(void)
+{
+    if (VESABuf_ptr)
+	PM_freeRealSeg(VESABuf_ptr);
+    VESABuf_ptr = 0;
+}
+
+void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff)
+{
+    if (!VESABuf_ptr) {
+	/* Allocate a global buffer for communicating with the VESA VBE */
+	if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL)
+	    return NULL;
+	atexit(ExitVBEBuf);
+	}
+    *len = VESABuf_len;
+    *rseg = VESABuf_rseg;
+    *roff = VESABuf_roff;
+    return VESABuf_ptr;
+}
+
+int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return PM_int386x(intno,in,out,&sregs);
+}
+
+/* Routines to set and get the real mode interrupt vectors, by making
+ * direct real mode calls to DOS and bypassing the DOS extenders API.
+ * This is the safest way to handle this, as some servers try to be
+ * smart about changing real mode vectors.
+ */
+
+void PMAPI _PM_getRMvect(int intno, long *realisr)
+{
+    RMREGS  regs;
+    RMSREGS sregs;
+
+    PM_saveDS();
+    regs.h.ah = 0x35;
+    regs.h.al = intno;
+    PM_int86x(0x21, &regs, &regs, &sregs);
+    *realisr = ((long)sregs.es << 16) | regs.x.bx;
+}
+
+void PMAPI _PM_setRMvect(int intno, long realisr)
+{
+    RMREGS  regs;
+    RMSREGS sregs;
+
+    PM_saveDS();
+    regs.h.ah = 0x25;
+    regs.h.al = intno;
+    sregs.ds = (int)(realisr >> 16);
+    regs.x.dx = (int)(realisr & 0xFFFF);
+    PM_int86x(0x21, &regs, &regs, &sregs);
+}
+
+void PMAPI _PM_addRealModeBlock(void *mem,uint tag)
+{
+    int i;
+
+    for (i = 0; i < MAX_RM_BLOCKS; i++) {
+	if (rmBlocks[i].p == NULL) {
+	    rmBlocks[i].p = mem;
+	    rmBlocks[i].tag = tag;
+	    return;
+	    }
+	}
+    PM_fatalError("To many real mode memory block allocations!");
+}
+
+uint PMAPI _PM_findRealModeBlock(void *mem)
+{
+    int i;
+
+    for (i = 0; i < MAX_RM_BLOCKS; i++) {
+	if (rmBlocks[i].p == mem)
+	    return rmBlocks[i].tag;
+	}
+    PM_fatalError("Could not find prior real mode memory block allocation!");
+    return 0;
+}
+
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    return getcwd(path,maxLen);
+}
+
+char PMAPI PM_getBootDrive(void)
+{ return 'C'; }
+
+const char * PMAPI PM_getVBEAFPath(void)
+{ return "c:\\"; }
+
+const char * PMAPI PM_getNucleusPath(void)
+{
+    static char path[256];
+    char        *env;
+
+    if ((env = getenv("NUCLEUS_PATH")) != NULL)
+	return env;
+    return "c:\\nucleus";
+}
+
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+const char * PMAPI PM_getUniqueID(void)
+{ return "SMX"; }
+
+const char * PMAPI PM_getMachineName(void)
+{ return "SMX"; }
+
+int PMAPI PM_kbhit(void)
+{
+    int     hit;
+    event_t evt;
+
+    hit = EVT_peekNext(&evt,EVT_KEYDOWN | EVT_KEYREPEAT);
+    EVT_flush(~(EVT_KEYDOWN | EVT_KEYREPEAT));
+    return hit;
+}
+
+int PMAPI PM_getch(void)
+{
+   event_t evt;
+
+    EVT_halt(&evt,EVT_KEYDOWN);
+   return EVT_asciiCode(evt.message);
+}
+
+PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen)
+{
+    /* Not used for SMX */
+    (void)hwndUser;
+    (void)device;
+    (void)xRes;
+    (void)yRes;
+    (void)bpp;
+    (void)fullScreen;
+    return 0;
+}
+
+int PMAPI PM_getConsoleStateSize(void)
+{
+    return sizeof(DOS_stateBuf);
+}
+
+void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole)
+{
+    RMREGS          regs;
+    DOS_stateBuf    *sb = stateBuf;
+
+    /* Save the old video mode state */
+    regs.h.ah = 0x0F;
+    PM_int86(0x10,&regs,&regs);
+    sb->oldMode = regs.h.al & 0x7F;
+    sb->old50Lines = false;
+    if (sb->oldMode == 0x3) {
+	regs.x.ax = 0x1130;
+	regs.x.bx = 0;
+	regs.x.dx = 0;
+	PM_int86(0x10,&regs,&regs);
+	sb->old50Lines = (regs.h.dl == 42 || regs.h.dl == 49);
+	}
+    (void)hwndConsole;
+}
+
+void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags))
+{
+    /* Not used for SMX */
+    (void)saveState;
+}
+
+void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole)
+{
+    RMREGS              regs;
+    const DOS_stateBuf  *sb = stateBuf;
+
+    /* Retore 50 line mode if set */
+    if (sb->old50Lines) {
+	regs.x.ax = 0x1112;
+	regs.x.bx = 0;
+	PM_int86(0x10,&regs,&regs);
+	}
+    (void)hwndConsole;
+}
+
+void PMAPI PM_closeConsole(PM_HWND hwndConsole)
+{
+    /* Not used for SMX */
+    (void)hwndConsole;
+}
+
+void PMAPI PM_setOSCursorLocation(int x,int y)
+{
+    uchar *_biosPtr = PM_getBIOSPointer();
+    PM_setByte(_biosPtr+0x50,x);
+    PM_setByte(_biosPtr+0x51,y);
+}
+
+void PMAPI PM_setOSScreenWidth(int width,int height)
+{
+    uchar *_biosPtr = PM_getBIOSPointer();
+    PM_setWord(_biosPtr+0x4A,width);
+    PM_setWord(_biosPtr+0x4C,width*2);
+    PM_setByte(_biosPtr+0x84,height-1);
+    if (height > 25) {
+	PM_setWord(_biosPtr+0x60,0x0607);
+	PM_setByte(_biosPtr+0x85,0x08);
+	}
+    else {
+	PM_setWord(_biosPtr+0x60,0x0D0E);
+	PM_setByte(_biosPtr+0x85,0x016);
+	}
+}
+
+void * PMAPI PM_mallocShared(long size)
+{
+    return PM_malloc(size);
+}
+
+void PMAPI PM_freeShared(void *ptr)
+{
+    PM_free(ptr);
+}
+
+#define GetRMVect(intno,isr)    *(isr) = ((ulong*)rmZeroPtr)[intno]
+#define SetRMVect(intno,isr)    ((ulong*)rmZeroPtr)[intno] = (isr)
+
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS,
+    ulong BIOSLen)
+{
+    static int      firstTime = true;
+    static uchar    *rmZeroPtr;
+    long            Current10,Current6D,Current42;
+    RMREGS          regs;
+    RMSREGS         sregs;
+
+    /* Create a zero memory mapping for us to use */
+    if (firstTime) {
+	rmZeroPtr = PM_mapPhysicalAddr(0,0x7FFF,true);
+	firstTime = false;
+	}
+
+    /* Remap the secondary BIOS to 0xC0000 physical */
+    if (BIOSPhysAddr != 0xC0000L || BIOSLen > 32768) {
+	/* SMX cannot virtually remap the BIOS, so we can only work if all
+	 * the secondary controllers are identical, and we then use the
+	 * BIOS on the first controller for all the remaining controllers.
+	 *
+	 * For OS'es that do virtual memory, and remapping of 0xC0000
+	 * physical (perhaps a copy on write mapping) should be all that
+	 * is needed.
+	 */
+	return false;
+	}
+
+    /* Save current handlers of int 10h and 6Dh */
+    GetRMVect(0x10,&Current10);
+    GetRMVect(0x6D,&Current6D);
+
+    /* POST the secondary BIOS */
+    GetRMVect(0x42,&Current42);
+    SetRMVect(0x10,Current42);  /* Restore int 10h to STD-BIOS */
+    regs.x.ax = axVal;
+    PM_callRealMode(0xC000,0x0003,&regs,&sregs);
+
+    /* Restore current handlers */
+    SetRMVect(0x10,Current10);
+    SetRMVect(0x6D,Current6D);
+
+    /* Second the primary BIOS mappin 1:1 for 0xC0000 physical */
+    if (BIOSPhysAddr != 0xC0000L) {
+	/* SMX does not support this */
+	(void)mappedBIOS;
+	}
+    return true;
+}
+
+void PMAPI PM_sleep(ulong milliseconds)
+{
+    ulong           microseconds = milliseconds * 1000L;
+    LZTimerObject   tm;
+
+    LZTimerOnExt(&tm);
+    while (LZTimerLapExt(&tm) < microseconds)
+	;
+    LZTimerOffExt(&tm);
+}
+
+int PMAPI PM_getCOMPort(int port)
+{
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	}
+    return 0;
+}
+
+int PMAPI PM_getLPTPort(int port)
+{
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    (void)szDLLName;
+    return NULL;
+}
+
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    (void)hModule;
+}
+
+int PMAPI PM_setIOPL(
+    int level)
+{
+    return level;
+}
+
+/****************************************************************************
+REMARKS:
+Internal function to convert the find data to the generic interface.
+****************************************************************************/
+static void convertFindData(
+    PM_findData *findData,
+    struct find_t *blk)
+{
+    ulong   dwSize = findData->dwSize;
+
+    memset(findData,0,findData->dwSize);
+    findData->dwSize = dwSize;
+    if (blk->attrib & _A_RDONLY)
+	findData->attrib |= PM_FILE_READONLY;
+    if (blk->attrib & _A_SUBDIR)
+	findData->attrib |= PM_FILE_DIRECTORY;
+    if (blk->attrib & _A_ARCH)
+	findData->attrib |= PM_FILE_ARCHIVE;
+    if (blk->attrib & _A_HIDDEN)
+	findData->attrib |= PM_FILE_HIDDEN;
+    if (blk->attrib & _A_SYSTEM)
+	findData->attrib |= PM_FILE_SYSTEM;
+    findData->sizeLo = blk->size;
+    strncpy(findData->name,blk->name,PM_MAX_PATH);
+    findData->name[PM_MAX_PATH-1] = 0;
+}
+
+#define FIND_MASK   (_A_RDONLY | _A_ARCH | _A_SUBDIR | _A_HIDDEN | _A_SYSTEM)
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+void * PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    struct find_t *blk;
+
+    if ((blk = PM_malloc(sizeof(*blk))) == NULL)
+	return PM_FILE_INVALID;
+    if (_dos_findfirst((char*)filename,FIND_MASK,blk) == 0) {
+	convertFindData(findData,blk);
+	return blk;
+	}
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    void *handle,
+    PM_findData *findData)
+{
+    struct find_t *blk = handle;
+
+    if (_dos_findnext(blk) == 0) {
+	convertFindData(findData,blk);
+	return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    void *handle)
+{
+    PM_free(handle);
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    RMREGS  regs;
+    regs.h.dl = (uchar)(drive - 'A' + 1);
+    regs.h.ah = 0x36;               /* Get disk information service */
+    PM_int86(0x21,&regs,&regs);
+    return regs.x.ax != 0xFFFF;     /* AX = 0xFFFF if disk is invalid */
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    uint oldDrive,maxDrives;
+    _dos_getdrive(&oldDrive);
+    _dos_setdrive(drive,&maxDrives);
+    getcwd(dir,len);
+    _dos_setdrive(oldDrive,&maxDrives);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+#if defined(TNT) && defined(_MSC_VER)
+    DWORD attr = 0;
+
+    if (attrib & PM_FILE_READONLY)
+	attr |= FILE_ATTRIBUTE_READONLY;
+    if (attrib & PM_FILE_ARCHIVE)
+	attr |= FILE_ATTRIBUTE_ARCHIVE;
+    if (attrib & PM_FILE_HIDDEN)
+	attr |= FILE_ATTRIBUTE_HIDDEN;
+    if (attrib & PM_FILE_SYSTEM)
+	attr |= FILE_ATTRIBUTE_SYSTEM;
+    SetFileAttributes((LPSTR)filename, attr);
+#else
+    uint attr = 0;
+
+    if (attrib & PM_FILE_READONLY)
+	attr |= _A_RDONLY;
+    if (attrib & PM_FILE_ARCHIVE)
+	attr |= _A_ARCH;
+    if (attrib & PM_FILE_HIDDEN)
+	attr |= _A_HIDDEN;
+    if (attrib & PM_FILE_SYSTEM)
+	attr |= _A_SYSTEM;
+    _dos_setfileattr(filename,attr);
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+#ifdef  __GNUC__
+    return mkdir(filename,S_IRUSR) == 0;
+#else
+/*AM:   return mkdir(filename) == 0; */
+    return(false);
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+/*AM:   return rmdir(filename) == 0; */
+    return(false);
+}
+
+/****************************************************************************
+REMARKS:
+Allocates a block of locked, physically contiguous memory. The memory
+may be required to be below the 16Meg boundary.
+****************************************************************************/
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16M)
+{
+    void            *p;
+    uint            r_seg,r_off;
+    PM_lockHandle   lh;
+
+    /* Under DOS the only way to know the physical memory address is to
+     * allocate the memory below the 1Meg boundary as real mode memory.
+     * We also allocate 4095 bytes more memory than we need, so we can
+     * properly page align the start of the memory block for DMA operations.
+     */
+    if (size > 4096)
+	return NULL;
+    if ((p = PM_allocRealSeg((size + 0xFFF) & ~0xFFF,&r_seg,&r_off)) == NULL)
+	return NULL;
+    *physAddr = ((r_seg << 4) + r_off + 0xFFF) & ~0xFFF;
+    PM_lockDataPages(p,size*2,&lh);
+    return p;
+}
+
+void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous)
+{
+    (void)size;
+    PM_freeRealSeg(p);
+}
+
+/*-------------------------------------------------------------------------*/
+/* Generic DPMI routines common to 16/32 bit code                          */
+/*-------------------------------------------------------------------------*/
+
+ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit)
+{
+    PMREGS  r;
+    ulong   physOfs;
+
+    if (physAddr < 0x100000L) {
+	/* We can't map memory below 1Mb, but the linear address are already
+	 * mapped 1:1 for this memory anyway so we just return the base address.
+	 */
+	return physAddr;
+	}
+
+    /* Round the physical address to a 4Kb boundary and the limit to a
+     * 4Kb-1 boundary before passing the values to DPMI as some extenders
+     * will fail the calls unless this is the case. If we round the
+     * physical address, then we also add an extra offset into the address
+     * that we return.
+     */
+    physOfs = physAddr & 4095;
+    physAddr = physAddr & ~4095;
+    limit = ((limit+physOfs+1+4095) & ~4095)-1;
+
+    r.x.ax = 0x800;                 /* DPMI map physical to linear      */
+    r.x.bx = physAddr >> 16;
+    r.x.cx = physAddr & 0xFFFF;
+    r.x.si = limit >> 16;
+    r.x.di = limit & 0xFFFF;
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag)
+	return 0xFFFFFFFFUL;
+    return ((ulong)r.x.bx << 16) + r.x.cx + physOfs;
+}
+
+int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr)
+{
+    PMREGS  r;
+
+    r.x.ax = 7;                     /* DPMI set selector base address   */
+    r.x.bx = sel;
+    r.x.cx = linAddr >> 16;
+    r.x.dx = linAddr & 0xFFFF;
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag)
+	return 0;
+    return 1;
+}
+
+ulong PMAPI DPMI_getSelectorBase(ushort sel)
+{
+    PMREGS  r;
+
+    r.x.ax = 6;                     /* DPMI get selector base address   */
+    r.x.bx = sel;
+    PM_int386(0x31, &r, &r);
+    return ((ulong)r.x.cx << 16) + r.x.dx;
+}
+
+int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit)
+{
+    PMREGS  r;
+
+    r.x.ax = 8;                     /* DPMI set selector limit          */
+    r.x.bx = sel;
+    r.x.cx = limit >> 16;
+    r.x.dx = limit & 0xFFFF;
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag)
+	return 0;
+    return 1;
+}
+
+uint PMAPI DPMI_createSelector(ulong base,ulong limit)
+{
+    uint    sel;
+    PMREGS  r;
+
+    /* Allocate 1 descriptor */
+    r.x.ax = 0;
+    r.x.cx = 1;
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag) return 0;
+    sel = r.x.ax;
+
+    /* Set the descriptor access rights (for a 32 bit page granular
+     * segment, ring 0).
+     */
+    r.x.ax = 9;
+    r.x.bx = sel;
+    r.x.cx = 0x4093;
+    PM_int386(0x31, &r, &r);
+
+    /* Map physical memory and create selector */
+    if ((base = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFFUL)
+	return 0;
+    if (!DPMI_setSelectorBase(sel,base))
+	return 0;
+    if (!DPMI_setSelectorLimit(sel,limit))
+	return 0;
+    return sel;
+}
+
+void PMAPI DPMI_freeSelector(uint sel)
+{
+    PMREGS  r;
+
+    r.x.ax = 1;
+    r.x.bx = sel;
+    PM_int386(0x31, &r, &r);
+}
+
+int PMAPI DPMI_lockLinearPages(ulong linear,ulong len)
+{
+    PMREGS  r;
+
+    r.x.ax = 0x600;                     /* DPMI Lock Linear Region      */
+    r.x.bx = (linear >> 16);            /* Linear address in BX:CX      */
+    r.x.cx = (linear & 0xFFFF);
+    r.x.si = (len >> 16);               /* Length in SI:DI              */
+    r.x.di = (len & 0xFFFF);
+    PM_int386(0x31, &r, &r);
+    return (!r.x.cflag);
+}
+
+int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len)
+{
+    PMREGS  r;
+
+    r.x.ax = 0x601;                     /* DPMI Unlock Linear Region    */
+    r.x.bx = (linear >> 16);            /* Linear address in BX:CX      */
+    r.x.cx = (linear & 0xFFFF);
+    r.x.si = (len >> 16);               /* Length in SI:DI              */
+    r.x.di = (len & 0xFFFF);
+    PM_int386(0x31, &r, &r);
+    return (!r.x.cflag);
+}
+
+void * PMAPI DPMI_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{
+    PMSREGS sregs;
+    ulong   linAddr;
+    ulong   DSBaseAddr;
+
+    /* Get the base address for the default DS selector */
+    PM_segread(&sregs);
+    DSBaseAddr = DPMI_getSelectorBase(sregs.ds);
+    if ((base < 0x100000) && (DSBaseAddr == 0)) {
+	/* DS is zero based, so we can directly access the first 1Mb of
+	 * system memory (like under DOS4GW).
+	 */
+	return (void*)base;
+	}
+
+    /* Map the memory to a linear address using DPMI function 0x800 */
+    if ((linAddr = DPMI_mapPhysicalToLinear(base,limit)) == 0) {
+	if (base >= 0x100000)
+	    return NULL;
+	/* If the linear address mapping fails but we are trying to
+	 * map an area in the first 1Mb of system memory, then we must
+	 * be running under a Windows or OS/2 DOS box. Under these
+	 * environments we can use the segment wrap around as a fallback
+	 * measure, as this does work properly.
+	 */
+	linAddr = base;
+	}
+
+    /* Now expand the default DS selector to 4Gb so we can access it */
+    if (!DPMI_setSelectorLimit(sregs.ds,0xFFFFFFFFUL))
+	return NULL;
+
+    /* Finally enable caching for the page tables that we just mapped in,
+     * since DOS4GW and PMODE/W create the page table entries without
+     * caching enabled which hurts the performance of the linear framebuffer
+     * as it disables write combining on Pentium Pro and above processors.
+     *
+     * For those processors cache disabling is better handled through the
+     * MTRR registers anyway (we can write combine a region but disable
+     * caching) so that MMIO register regions do not screw up.
+     */
+    if (isCached) {
+	if ((PDB = _PM_getPDB()) != 0 && DSBaseAddr == 0) {
+	    int     startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage;
+	    ulong   pageTable,*pPageTable;
+	    if (!pPDB) {
+		if (PDB >= 0x100000)
+		    pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF);
+		else
+		    pPDB = (ulong*)PDB;
+		}
+	    if (pPDB) {
+		startPDB = (linAddr >> 22) & 0x3FF;
+		startPage = (linAddr >> 12) & 0x3FF;
+		endPDB = ((linAddr+limit) >> 22) & 0x3FF;
+		endPage = ((linAddr+limit) >> 12) & 0x3FF;
+		for (iPDB = startPDB; iPDB <= endPDB; iPDB++) {
+		    pageTable = pPDB[iPDB] & ~0xFFF;
+		    if (pageTable >= 0x100000)
+			pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF);
+		    else
+			pPageTable = (ulong*)pageTable;
+		    start = (iPDB == startPDB) ? startPage : 0;
+		    end = (iPDB == endPDB) ? endPage : 0x3FF;
+		    for (iPage = start; iPage <= end; iPage++)
+			pPageTable[iPage] &= ~0x18;
+		    }
+		}
+	    }
+	}
+
+    /* Now return the base address of the memory into the default DS */
+    return (void*)(linAddr - DSBaseAddr);
+}
+
+/* Some DOS extender implementations do not directly support calling a
+ * real mode procedure from protected mode. However we can simulate what
+ * we need temporarily hooking the INT 6Ah vector with a small real mode
+ * stub that will call our real mode code for us.
+ */
+
+static uchar int6AHandler[] = {
+    0x00,0x00,0x00,0x00,        /*  __PMODE_callReal variable           */
+    0xFB,                       /*  sti                                 */
+    0x2E,0xFF,0x1E,0x00,0x00,   /*  call    [cs:__PMODE_callReal]       */
+    0xCF,                       /*  iretf                               */
+    };
+static uchar *crPtr = NULL; /* Pointer to of int 6A handler         */
+static uint crRSeg,crROff;  /* Real mode seg:offset of handler      */
+
+void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in,
+    RMSREGS *sregs)
+{
+    uchar   *p;
+    uint    oldSeg,oldOff;
+
+    if (!crPtr) {
+	/* Allocate and copy the memory block only once */
+	crPtr = PM_allocRealSeg(sizeof(int6AHandler), &crRSeg, &crROff);
+	memcpy(crPtr,int6AHandler,sizeof(int6AHandler));
+	}
+    PM_setWord(crPtr,off);              /* Plug in address to call  */
+    PM_setWord(crPtr+2,seg);
+    p = PM_mapRealPointer(0,0x6A * 4);
+    oldOff = PM_getWord(p);             /* Save old handler address */
+    oldSeg = PM_getWord(p+2);
+    PM_setWord(p,crROff+4);             /* Hook 6A handler          */
+    PM_setWord(p+2,crRSeg);
+    PM_int86x(0x6A, in, in, sregs);     /* Call real mode code      */
+    PM_setWord(p,oldOff);               /* Restore old handler      */
+    PM_setWord(p+2,oldSeg);
+}
+
+void * PMAPI PM_getBIOSPointer(void)
+{ return PM_mapPhysicalAddr(0x400,0xFFFF,true); }
+
+void * PMAPI PM_getA0000Pointer(void)
+{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); }
+
+void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached)
+{ return DPMI_mapPhysicalAddr(base,limit,isCached); }
+
+void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit)
+{
+    /* Mapping cannot be free */
+}
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{
+    /* TODO: This function should find the physical address of a linear */
+    /*       address. */
+    (void)p;
+    return 0xFFFFFFFFUL;
+}
+
+void * PMAPI PM_mapToProcess(void *base,ulong limit)
+{
+    (void)limit;
+    return (void*)base;
+}
+
+void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off)
+{
+    static uchar *zeroPtr = NULL;
+
+    if (!zeroPtr)
+	zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true);
+    return (void*)(zeroPtr + MK_PHYS(r_seg,r_off));
+}
+
+void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off)
+{
+    PMREGS      r;
+    void        *p;
+
+    r.x.ax = 0x100;                 /* DPMI allocate DOS memory         */
+    r.x.bx = (size + 0xF) >> 4;     /* number of paragraphs             */
+    PM_int386(0x31, &r, &r);
+    if (r.x.cflag)
+	return NULL;                /* DPMI call failed                 */
+    *r_seg = r.x.ax;                /* Real mode segment                */
+    *r_off = 0;
+    p = PM_mapRealPointer(*r_seg,*r_off);
+    _PM_addRealModeBlock(p,r.x.dx);
+    return p;
+}
+
+void PMAPI PM_freeRealSeg(void *mem)
+{
+    PMREGS  r;
+
+    r.x.ax = 0x101;                     /* DPMI free DOS memory         */
+    r.x.dx = _PM_findRealModeBlock(mem);/* DX := selector from 0x100    */
+    PM_int386(0x31, &r, &r);
+}
+
+static DPMI_handler_t   DPMI_int10 = NULL;
+
+void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler)
+{
+    DPMI_int10 = handler;
+}
+
+void PMAPI DPMI_int86(int intno, DPMI_regs *regs)
+{
+    PMREGS      r;
+    PMSREGS     sr;
+
+    if (intno == 0x10 && DPMI_int10) {
+	if (DPMI_int10(regs))
+	    return;
+	}
+    PM_segread(&sr);
+    r.x.ax = 0x300;                 /* DPMI issue real interrupt    */
+    r.h.bl = intno;
+    r.h.bh = 0;
+    r.x.cx = 0;
+    sr.es = sr.ds;
+    r.e.edi = (uint)regs;
+    PM_int386x(0x31, &r, &r, &sr);  /* Issue the interrupt          */
+}
+
+#define IN(reg)     rmregs.reg = in->e.reg
+#define OUT(reg)    out->e.reg = rmregs.reg
+
+int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out)
+{
+    DPMI_regs   rmregs;
+
+    memset(&rmregs, 0, sizeof(rmregs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+
+/* These real mode ints may cause crashes. */
+/*AM:   DPMI_int86(intno,&rmregs);      /###* DPMI issue real interrupt    */
+
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+    out->x.cflag = rmregs.flags & 0x1;
+    return out->x.ax;
+}
+
+int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,
+    RMSREGS *sregs)
+{
+    DPMI_regs   rmregs;
+
+    memset(&rmregs, 0, sizeof(rmregs));
+    IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi);
+    rmregs.es = sregs->es;
+    rmregs.ds = sregs->ds;
+
+/*AM:   DPMI_int86(intno,&rmregs);      /###* DPMI issue real interrupt    */
+
+    OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi);
+    sregs->es = rmregs.es;
+    sregs->cs = rmregs.cs;
+    sregs->ss = rmregs.ss;
+    sregs->ds = rmregs.ds;
+    out->x.cflag = rmregs.flags & 0x1;
+    return out->x.ax;
+}
+
+#pragma pack(1)
+
+typedef struct {
+	uint    LargestBlockAvail;
+	uint    MaxUnlockedPage;
+	uint    LargestLockablePage;
+	uint    LinAddrSpace;
+	uint    NumFreePagesAvail;
+	uint    NumPhysicalPagesFree;
+	uint    TotalPhysicalPages;
+	uint    FreeLinAddrSpace;
+	uint    SizeOfPageFile;
+	uint    res[3];
+	} MemInfo;
+
+#pragma pack()
+
+void PMAPI PM_availableMemory(ulong *physical,ulong *total)
+{
+    PMREGS  r;
+    PMSREGS sr;
+    MemInfo memInfo;
+
+    PM_segread(&sr);
+    r.x.ax = 0x500;                 /* DPMI get free memory info */
+    sr.es = sr.ds;
+    r.e.edi = (uint)&memInfo;
+    PM_int386x(0x31, &r, &r, &sr);  /* Issue the interrupt */
+    *physical = memInfo.NumPhysicalPagesFree * 4096;
+    *total = memInfo.LargestBlockAvail;
+    if (*total < *physical)
+	*physical = *total;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file attributes for a specific file.
+****************************************************************************/
+uint PMAPI PM_getFileAttr(
+    const char *filename)
+{
+    /* TODO: Implement this! */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_getFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this! */
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to set the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_setFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this! */
+    return false;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c b/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c
new file mode 100755
index 0000000..98e31bc
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c
@@ -0,0 +1,471 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit SMX embedded systems development
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <dos.h>
+#include "smx/ps2mouse.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+static int  globalDataStart;
+
+PM_criticalHandler  _VARAPI _PM_critHandler = NULL;
+PM_breakHandler     _VARAPI _PM_breakHandler = NULL;
+PM_intHandler       _VARAPI _PM_timerHandler = NULL;
+PM_intHandler       _VARAPI _PM_rtcHandler = NULL;
+PM_intHandler       _VARAPI _PM_keyHandler = NULL;
+PM_key15Handler     _VARAPI _PM_key15Handler = NULL;
+PM_mouseHandler     _VARAPI _PM_mouseHandler = NULL;
+PM_intHandler       _VARAPI _PM_int10Handler = NULL;
+int                 _VARAPI _PM_mouseMask;
+
+uchar *     _VARAPI _PM_ctrlCPtr;               /* Location of Ctrl-C flag      */
+uchar *     _VARAPI _PM_ctrlBPtr;               /* Location of Ctrl-Break flag  */
+uchar *     _VARAPI _PM_critPtr;                /* Location of Critical error Bf*/
+PMFARPTR    _VARAPI _PM_prevTimer = PMNULL;     /* Previous timer handler       */
+PMFARPTR    _VARAPI _PM_prevRTC = PMNULL;       /* Previous RTC handler         */
+PMFARPTR    _VARAPI _PM_prevKey = PMNULL;       /* Previous key handler         */
+PMFARPTR    _VARAPI _PM_prevKey15 = PMNULL;     /* Previous key15 handler       */
+PMFARPTR    _VARAPI _PM_prevBreak = PMNULL;     /* Previous break handler       */
+PMFARPTR    _VARAPI _PM_prevCtrlC = PMNULL;     /* Previous CtrlC handler       */
+PMFARPTR    _VARAPI _PM_prevCritical = PMNULL;  /* Previous critical handler    */
+long        _VARAPI _PM_prevRealTimer;          /* Previous real mode timer     */
+long        _VARAPI _PM_prevRealRTC;            /* Previous real mode RTC       */
+long        _VARAPI _PM_prevRealKey;            /* Previous real mode key       */
+long        _VARAPI _PM_prevRealKey15;          /* Previous real mode key15     */
+long        _VARAPI _PM_prevRealInt10;          /* Previous real mode int 10h   */
+static uchar        _PM_oldCMOSRegA;            /* CMOS register A contents     */
+static uchar        _PM_oldCMOSRegB;            /* CMOS register B contents     */
+static uchar        _PM_oldRTCPIC2;             /* Mask value for RTC IRQ8      */
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* Globals for locking interrupt handlers in _pmsmx.asm */
+
+extern int  _ASMAPI _PM_pmsmxDataStart;
+extern int  _ASMAPI _PM_pmsmxDataEnd;
+void _ASMAPI _PM_pmsmxCodeStart(void);
+void _ASMAPI _PM_pmsmxCodeEnd(void);
+
+/* Protected mode interrupt handlers, also called by PM callbacks below */
+
+void _ASMAPI _PM_timerISR(void);
+void _ASMAPI _PM_rtcISR(void);
+void _ASMAPI _PM_keyISR(void);
+void _ASMAPI _PM_key15ISR(void);
+void _ASMAPI _PM_breakISR(void);
+void _ASMAPI _PM_ctrlCISR(void);
+void _ASMAPI _PM_criticalISR(void);
+void _ASMAPI _PM_mouseISR(void);
+void _ASMAPI _PM_int10PMCB(void);
+
+/* Protected mode DPMI callback handlers */
+
+void _ASMAPI _PM_mousePMCB(void);
+
+/* Routine to install a mouse handler function */
+
+void _ASMAPI _PM_setMouseHandler(int mask);
+
+/* Routine to allocate DPMI real mode callback routines */
+
+void _ASMAPI _DPMI_allocateCallback(void (_ASMAPI *pmcode)(),void *rmregs,long *RMCB);
+void _ASMAPI _DPMI_freeCallback(long RMCB);
+
+/* DPMI helper functions in PMLITE.C */
+
+ulong   PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit);
+int     PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr);
+ulong   PMAPI DPMI_getSelectorBase(ushort sel);
+int     PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit);
+uint    PMAPI DPMI_createSelector(ulong base,ulong limit);
+void    PMAPI DPMI_freeSelector(uint sel);
+int     PMAPI DPMI_lockLinearPages(ulong linear,ulong len);
+int     PMAPI DPMI_unlockLinearPages(ulong linear,ulong len);
+
+/* Functions to read and write CMOS registers */
+
+uchar   PMAPI _PM_readCMOS(int index);
+void    PMAPI _PM_writeCMOS(int index,uchar value);
+
+/*-------------------------------------------------------------------------*/
+/* Generic routines common to all environments                             */
+/*-------------------------------------------------------------------------*/
+
+void PMAPI PM_resetMouseDriver(int hardReset)
+{
+    ps2MouseReset();
+}
+
+void PMAPI PM_setRealTimeClockFrequency(int frequency)
+{
+    static short convert[] = {
+	8192,
+	4096,
+	2048,
+	1024,
+	512,
+	256,
+	128,
+	64,
+	32,
+	16,
+	8,
+	4,
+	2,
+	-1,
+	};
+    int i;
+
+    /* First clear any pending RTC timeout if not cleared */
+    _PM_readCMOS(0x0C);
+    if (frequency == 0) {
+	/* Disable RTC timout */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F);
+	}
+    else {
+	/* Convert frequency value to RTC clock indexes */
+	for (i = 0; convert[i] != -1; i++) {
+	    if (convert[i] == frequency)
+		break;
+	    }
+
+	/* Set RTC timout value and enable timeout */
+	_PM_writeCMOS(0x0A,(_PM_oldCMOSRegA & 0xF0) | (i+3));
+	_PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40);
+	}
+}
+
+static void PMAPI lockPMHandlers(void)
+{
+    static int      locked = 0;
+    int             stat = 0;
+    PM_lockHandle   lh;
+
+    /* Lock all of the code and data used by our protected mode interrupt
+     * handling routines, so that it will continue to work correctly
+     * under real mode.
+     */
+    if (!locked) {
+	PM_saveDS();
+	stat  = !PM_lockDataPages(&globalDataStart-2048,4096,&lh);
+	stat |= !PM_lockDataPages(&_PM_pmsmxDataStart,(int)&_PM_pmsmxDataEnd - (int)&_PM_pmsmxDataStart,&lh);
+	stat |= !PM_lockCodePages((__codePtr)_PM_pmsmxCodeStart,(int)_PM_pmsmxCodeEnd-(int)_PM_pmsmxCodeStart,&lh);
+	if (stat) {
+	    printf("Page locking services failed - interrupt handling not safe!\n");
+	    exit(1);
+	    }
+	locked = 1;
+	}
+}
+
+void PMAPI PM_getPMvect(int intno, PMFARPTR *isr)
+{
+    PMREGS  regs;
+
+    regs.x.ax = 0x204;
+    regs.h.bl = intno;
+    PM_int386(0x31,&regs,&regs);
+    isr->sel = regs.x.cx;
+    isr->off = regs.e.edx;
+}
+
+void PMAPI PM_setPMvect(int intno, PM_intHandler isr)
+{
+    PMSREGS sregs;
+    PMREGS  regs;
+
+    PM_saveDS();
+    regs.x.ax = 0x205;          /* Set protected mode vector        */
+    regs.h.bl = intno;
+    PM_segread(&sregs);
+    regs.x.cx = sregs.cs;
+    regs.e.edx = (uint)isr;
+    PM_int386(0x31,&regs,&regs);
+}
+
+void PMAPI PM_restorePMvect(int intno, PMFARPTR isr)
+{
+    PMREGS  regs;
+
+    regs.x.ax = 0x205;
+    regs.h.bl = intno;
+    regs.x.cx = isr.sel;
+    regs.e.edx = isr.off;
+    PM_int386(0x31,&regs,&regs);
+}
+
+static long prevRealBreak;      /* Previous real mode break handler     */
+static long prevRealCtrlC;      /* Previous real mode CtrlC handler     */
+static long prevRealCritical;   /* Prev real mode critical handler      */
+
+int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh)
+{
+    lockPMHandlers();           /* Ensure our handlers are locked   */
+
+    _PM_mouseHandler = mh;
+    return 0;
+}
+
+void PMAPI PM_restoreMouseHandler(void)
+{
+    if (_PM_mouseHandler)
+	_PM_mouseHandler = NULL;
+}
+
+static void getISR(int intno, PMFARPTR *pmisr, long *realisr)
+{
+    PM_getPMvect(intno,pmisr);
+}
+
+static void restoreISR(int intno, PMFARPTR pmisr, long realisr)
+{
+    PM_restorePMvect(intno,pmisr);
+}
+
+static void setISR(int intno, void (* PMAPI pmisr)())
+{
+    lockPMHandlers();           /* Ensure our handlers are locked   */
+    PM_setPMvect(intno,pmisr);
+}
+
+void PMAPI PM_setTimerHandler(PM_intHandler th)
+{
+    getISR(PM_IRQ0, &_PM_prevTimer, &_PM_prevRealTimer);
+    _PM_timerHandler = th;
+    setISR(PM_IRQ0, _PM_timerISR);
+}
+
+void PMAPI PM_restoreTimerHandler(void)
+{
+    if (_PM_timerHandler) {
+	restoreISR(PM_IRQ0, _PM_prevTimer, _PM_prevRealTimer);
+	_PM_timerHandler = NULL;
+	}
+}
+
+ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency)
+{
+    /* Save the old CMOS real time clock values */
+    _PM_oldCMOSRegA = _PM_readCMOS(0x0A);
+    _PM_oldCMOSRegB = _PM_readCMOS(0x0B);
+
+    /* Set the real time clock interrupt handler */
+    getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC);
+    _PM_rtcHandler = th;
+    setISR(0x70, _PM_rtcISR);
+
+    /* Program the real time clock default frequency */
+    PM_setRealTimeClockFrequency(frequency);
+
+    /* Unmask IRQ8 in the PIC2 */
+    _PM_oldRTCPIC2 = PM_inpb(0xA1);
+    PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE);
+    return true;
+}
+
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    if (_PM_rtcHandler) {
+	/* Restore CMOS registers and mask RTC clock */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB);
+	PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE));
+
+	/* Restore the interrupt vector */
+	restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC);
+	_PM_rtcHandler = NULL;
+	}
+}
+
+void PMAPI PM_setKeyHandler(PM_intHandler kh)
+{
+    getISR(PM_IRQ1, &_PM_prevKey, &_PM_prevRealKey);
+    _PM_keyHandler = kh;
+    setISR(PM_IRQ1, _PM_keyISR);
+}
+
+void PMAPI PM_restoreKeyHandler(void)
+{
+    if (_PM_keyHandler) {
+	restoreISR(PM_IRQ1, _PM_prevKey, _PM_prevRealKey);
+	_PM_keyHandler = NULL;
+	}
+}
+
+void PMAPI PM_setKey15Handler(PM_key15Handler kh)
+{
+    getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15);
+    _PM_key15Handler = kh;
+    setISR(0x15, _PM_key15ISR);
+}
+
+void PMAPI PM_restoreKey15Handler(void)
+{
+    if (_PM_key15Handler) {
+	restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15);
+	_PM_key15Handler = NULL;
+	}
+}
+
+/* Real mode Ctrl-C and Ctrl-Break handler. This handler simply sets a
+ * flag in the real mode code segment and exit. We save the location
+ * of this flag in real mode memory so that both the real mode and
+ * protected mode code will be modifying the same flags.
+ */
+
+static uchar ctrlHandler[] = {
+    0x00,0x00,0x00,0x00,            /*  ctrlBFlag                       */
+    0x66,0x2E,0xC7,0x06,0x00,0x00,
+    0x01,0x00,0x00,0x00,            /*  mov     [cs:ctrlBFlag],1        */
+    0xCF,                           /*  iretf                           */
+    };
+
+void PMAPI PM_installAltBreakHandler(PM_breakHandler bh)
+{
+    uint    rseg,roff;
+
+    getISR(0x1B, &_PM_prevBreak, &prevRealBreak);
+    getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC);
+    _PM_breakHandler = bh;
+    setISR(0x1B, _PM_breakISR);
+    setISR(0x23, _PM_ctrlCISR);
+
+    /* Hook the real mode vectors for these handlers, as these are not
+     * normally reflected by the DPMI server up to protected mode
+     */
+    _PM_ctrlBPtr = PM_allocRealSeg(sizeof(ctrlHandler)*2, &rseg, &roff);
+    memcpy(_PM_ctrlBPtr,ctrlHandler,sizeof(ctrlHandler));
+    memcpy(_PM_ctrlBPtr+sizeof(ctrlHandler),ctrlHandler,sizeof(ctrlHandler));
+    _PM_ctrlCPtr = _PM_ctrlBPtr + sizeof(ctrlHandler);
+    _PM_setRMvect(0x1B,((long)rseg << 16) | (roff+4));
+    _PM_setRMvect(0x23,((long)rseg << 16) | (roff+sizeof(ctrlHandler)+4));
+}
+
+void PMAPI PM_installBreakHandler(void)
+{
+    PM_installAltBreakHandler(NULL);
+}
+
+void PMAPI PM_restoreBreakHandler(void)
+{
+    if (_PM_prevBreak.sel) {
+	restoreISR(0x1B, _PM_prevBreak, prevRealBreak);
+	restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC);
+	_PM_prevBreak.sel = 0;
+	_PM_breakHandler = NULL;
+	PM_freeRealSeg(_PM_ctrlBPtr);
+	}
+}
+
+/* Real mode Critical Error handler. This handler simply saves the AX and
+ * DI values in the real mode code segment and exits. We save the location
+ * of this flag in real mode memory so that both the real mode and
+ * protected mode code will be modifying the same flags.
+ */
+
+static uchar criticalHandler[] = {
+    0x00,0x00,                      /*  axCode                          */
+    0x00,0x00,                      /*  diCode                          */
+    0x2E,0xA3,0x00,0x00,            /*  mov     [cs:axCode],ax          */
+    0x2E,0x89,0x3E,0x02,0x00,       /*  mov     [cs:diCode],di          */
+    0xB8,0x03,0x00,                 /*  mov     ax,3                    */
+    0xCF,                           /*  iretf                           */
+    };
+
+void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch)
+{
+    uint    rseg,roff;
+
+    getISR(0x24, &_PM_prevCritical, &prevRealCritical);
+    _PM_critHandler = ch;
+    setISR(0x24, _PM_criticalISR);
+
+    /* Hook the real mode vector, as this is not normally reflected by the
+     * DPMI server up to protected mode.
+     */
+    _PM_critPtr = PM_allocRealSeg(sizeof(criticalHandler)*2, &rseg, &roff);
+    memcpy(_PM_critPtr,criticalHandler,sizeof(criticalHandler));
+    _PM_setRMvect(0x24,((long)rseg << 16) | (roff+4));
+}
+
+void PMAPI PM_installCriticalHandler(void)
+{
+    PM_installAltCriticalHandler(NULL);
+}
+
+void PMAPI PM_restoreCriticalHandler(void)
+{
+    if (_PM_prevCritical.sel) {
+	restoreISR(0x24, _PM_prevCritical, prevRealCritical);
+	PM_freeRealSeg(_PM_critPtr);
+	_PM_prevCritical.sel = 0;
+	_PM_critHandler = NULL;
+	}
+}
+
+int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len);
+}
+
+int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len);
+}
+
+int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+/*AM: causes minor glitch with */
+/*AM: older versions pmEasy which don't allow DPMI 06 on */
+/*AM: Code selector 0x0C -- assume base is 0 which it should be. */
+    return DPMI_lockLinearPages((uint)p,len);
+}
+
+int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    PMSREGS sregs;
+    PM_segread(&sregs);
+    return DPMI_unlockLinearPages((uint)p,len);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c
new file mode 100755
index 0000000..579ef2c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c
@@ -0,0 +1,49 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    baseAddr = baseAddr;
+    bankSize = bankSize;
+    codeLen = codeLen;
+    bankFunc = bankFunc;
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c
new file mode 100755
index 0000000..7941192
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c
@@ -0,0 +1,115 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit SMX embedded systems development
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*     LZTimer not supported for smx (as needed for i486 processors), only
+*     ULZTimer is supported at this time.
+*
+****************************************************************************/
+
+/*---------------------------- Global smx variables -----------------------*/
+
+extern ulong      _cdecl etime;     /* elapsed time */
+extern ulong      _cdecl xticks_per_second(void);
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* External assembler functions */
+
+void    _ASMAPI LZ_disable(void);
+void    _ASMAPI LZ_enable(void);
+
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+void __ZTimerInit(void)
+{
+}
+
+ulong reterr(void)
+{
+   PM_fatalError("Zen Timer not supported for smx.");
+   return(0);
+}
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOn(tm)     PM_fatalError("Zen Timer not supported for smx.")
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerLap(tm)    reterr()
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOff(tm)    PM_fatalError("Zen Timer not supported for smx.")
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerCount(tm)  reterr()
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as seconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION     (ulong)(1000000/xticks_per_second())
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer value from the smx timer tick.
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{
+    ulong   ticks;
+    LZ_disable();            /* Turn of interrupts               */
+    ticks = etime;
+    LZ_enable();             /* Turn on interrupts again         */
+    return ticks;
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{
+    if (finish < start)
+	finish += xticks_per_second() * 3600 *24;       /* Number of ticks in 24 hours      */
+    return finish - start;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c
new file mode 100755
index 0000000..0615e90
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c
@@ -0,0 +1,79 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE ***
+*
+* Description:  Module to implement OS specific services to measure the
+*               CPU frequency.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Increase the thread priority to maximum, if possible.
+****************************************************************************/
+static int SetMaxThreadPriority(void)
+{
+    /* TODO: If you have thread priorities, increase it to maximum for the */
+    /*       thread for timing the CPU frequency. */
+    return oldPriority;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the original thread priority.
+****************************************************************************/
+static void RestoreThreadPriority(
+    int priority)
+{
+    /* TODO: Restore the original thread priority on exit. */
+}
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    /* TODO: Return the frequency of the counter in here. You should try to */
+    /*       normalise this value to be around 100,000 ticks per second. */
+    freq->low = 0;
+    freq->high = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+
+TODO: Implement this to read the counter. It should be done as a macro
+      for accuracy.
+****************************************************************************/
+#define GetCounter(t)               \
+{                                   \
+    (t)->low = 0;                   \
+    (t)->high = 0;                  \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/event.c b/board/MAI/bios_emulator/scitech/src/pm/stub/event.c
new file mode 100755
index 0000000..204c492
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/stub/event.c
@@ -0,0 +1,199 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE ***
+*
+* Description:  **** implementation for the SciTech cross platform
+*               event library.
+*
+****************************************************************************/
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static ushort       keyUpMsg[256] = {0};/* Table of key up messages     */
+static int          rangeX,rangeY;      /* Range of mouse coordinates   */
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* These are not used under non-DOS systems */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flags)
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Scan code to test
+
+REMARKS:
+This macro determines if a specified key is currently down at the
+time that the call is made.
+****************************************************************************/
+#define _EVT_isKeyDown(scanCode)    (keyUpMsg[scanCode] != 0)
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{
+    /* TODO: Implement this for your OS! */
+}
+
+/****************************************************************************
+REMARKS:
+Pumps all messages in the application message queue into our event queue.
+****************************************************************************/
+static void _EVT_pumpMessages(void)
+{
+    /* TODO: The purpose of this function is to read all keyboard and mouse */
+    /*       events from the OS specific event queue, translate them and post */
+    /*       them into the SciTech event queue. */
+    /* */
+    /* NOTE: There are a couple of important things that this function must */
+    /*       take care of: */
+    /* */
+    /*  1. Support for KEYDOWN, KEYREPEAT and KEYUP is required. */
+    /* */
+    /*  2. Support for reading hardware scan code as well as ASCII */
+    /*     translated values is required. Games use the scan codes rather */
+    /*     than ASCII values. Scan codes go into the high order byte of the */
+    /*     keyboard message field. */
+    /* */
+    /*  3. Support for at least reading mouse motion data (mickeys) from the */
+    /*     mouse is required. Using the mickey values, we can then translate */
+    /*     to mouse cursor coordinates scaled to the range of the current */
+    /*     graphics display mode. Mouse values are scaled based on the */
+    /*     global 'rangeX' and 'rangeY'. */
+    /* */
+    /*  4. Support for a timestamp for the events is required, which is */
+    /*     defined as the number of milliseconds since some event (usually */
+    /*     system startup). This is the timestamp when the event occurred */
+    /*     (ie: at interrupt time) not when it was stuff into the SciTech */
+    /*     event queue. */
+    /* */
+    /*  5. Support for mouse double click events. If the OS has a native */
+    /*     mechanism to determine this, it should be used. Otherwise the */
+    /*     time stamp information will be used by the generic event code */
+    /*     to generate double click events. */
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort()
+{
+    EVT_exit();
+    PM_fatalError("Unhandled exception!");
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    /* Initialise the event queue */
+    _mouseMove = mouseMove;
+    initEventQueue();
+    memset(keyUpMsg,0,sizeof(keyUpMsg));
+
+    /* TODO: Do any OS specific initialisation here */
+
+    /* Catch program termination signals so we can clean up properly */
+    signal(SIGABRT, _EVT_abort);
+    signal(SIGFPE, _EVT_abort);
+    signal(SIGINT, _EVT_abort);
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    rangeX = xRes;
+    rangeY = yRes;
+}
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for non DOS systems */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for non DOS systems */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+    /* Restore signal handlers */
+    signal(SIGABRT, SIG_DFL);
+    signal(SIGFPE, SIG_DFL);
+    signal(SIGINT, SIG_DFL);
+
+    /* TODO: Do any OS specific cleanup in here */
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h
new file mode 100755
index 0000000..1395cbc
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h
@@ -0,0 +1,33 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  BeOS
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+/* TODO: This is where you include OS specific headers for the event handling */
+/*       library. You may leave this empty if you have no OS specific headers */
+/*       to include. */
diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c b/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c
new file mode 100755
index 0000000..5f278c3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c
@@ -0,0 +1,980 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE ***
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/* TODO: Include any OS specific headers here! */
+
+/*--------------------------- Global variables ----------------------------*/
+
+/* TODO: If you support access to the BIOS, the following VESABuf globals */
+/*       keep track of a single VESA transfer buffer. If you don't support */
+/*       access to the BIOS, remove these variables. */
+
+static uint VESABuf_len = 1024;     /* Length of the VESABuf buffer     */
+static void *VESABuf_ptr = NULL;    /* Near pointer to VESABuf          */
+static uint VESABuf_rseg;           /* Real mode segment of VESABuf     */
+static uint VESABuf_roff;           /* Real mode offset of VESABuf      */
+
+static void (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the PM library.
+****************************************************************************/
+void PMAPI PM_init(void)
+{
+    /* TODO: Do any initialisation in here. This includes getting IOPL */
+    /*       access for the process calling PM_init. This will get called */
+    /*       more than once. */
+
+    /* TODO: If you support the supplied MTRR register stuff (you need to */
+    /*       be at ring 0 for this!), you should initialise it in here. */
+
+/* MTRR_init(); */
+}
+
+/****************************************************************************
+REMARKS:
+Return the operating system type identifier.
+****************************************************************************/
+long PMAPI PM_getOSType(void)
+{
+    /* TODO: Change this to return the define for your OS from drvlib/os.h */
+    return _OS_MYOS;
+}
+
+/****************************************************************************
+REMARKS:
+Return the runtime type identifier (always PM_386 for protected mode)
+****************************************************************************/
+int PMAPI PM_getModeType(void)
+{ return PM_386; }
+
+/****************************************************************************
+REMARKS:
+Add a file directory separator to the end of the filename.
+****************************************************************************/
+void PMAPI PM_backslash(
+    char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '/') {
+	s[pos] = '/';
+	s[pos+1] = '\0';
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Add a user defined PM_fatalError cleanup function.
+****************************************************************************/
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+/****************************************************************************
+REMARKS:
+Report a fatal error condition and halt the program.
+****************************************************************************/
+void PMAPI PM_fatalError(
+    const char *msg)
+{
+    /* TODO: If you are running in a GUI environment without a console, */
+    /*       this needs to be changed to bring up a fatal error message */
+    /*       box and terminate the program. */
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+    fprintf(stderr,"%s\n", msg);
+    exit(1);
+}
+
+/****************************************************************************
+REMARKS:
+Exit handler to kill the VESA transfer buffer.
+****************************************************************************/
+static void ExitVBEBuf(void)
+{
+    /* TODO: If you do not have BIOS access, remove this function. */
+    if (VESABuf_ptr)
+	PM_freeRealSeg(VESABuf_ptr);
+    VESABuf_ptr = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate the real mode VESA transfer buffer for communicating with the BIOS.
+****************************************************************************/
+void * PMAPI PM_getVESABuf(
+    uint *len,
+    uint *rseg,
+    uint *roff)
+{
+    /* TODO: If you do not have BIOS access, simply delete the guts of */
+    /*       this function and return NULL. */
+    if (!VESABuf_ptr) {
+	/* Allocate a global buffer for communicating with the VESA VBE */
+	if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL)
+	    return NULL;
+	atexit(ExitVBEBuf);
+	}
+    *len = VESABuf_len;
+    *rseg = VESABuf_rseg;
+    *roff = VESABuf_roff;
+    return VESABuf_ptr;
+}
+
+/****************************************************************************
+REMARKS:
+Check if a key has been pressed.
+****************************************************************************/
+int PMAPI PM_kbhit(void)
+{
+    /* TODO: This function checks if a key is available to be read. This */
+    /*       should be implemented, but is mostly used by the test programs */
+    /*       these days. */
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Wait for and return the next keypress.
+****************************************************************************/
+int PMAPI PM_getch(void)
+{
+    /* TODO: This returns the ASCII code of the key pressed. This */
+    /*       should be implemented, but is mostly used by the test programs */
+    /*       these days. */
+    return 0xD;
+}
+
+/****************************************************************************
+REMARKS:
+Open a fullscreen console mode for output.
+****************************************************************************/
+int PMAPI PM_openConsole(void)
+{
+    /* TODO: Opens up a fullscreen console for graphics output. If your */
+    /*       console does not have graphics/text modes, this can be left */
+    /*       empty. The main purpose of this is to disable console switching */
+    /*       when in graphics modes if you can switch away from fullscreen */
+    /*       consoles (if you want to allow switching, this can be done */
+    /*       elsewhere with a full save/restore state of the graphics mode). */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Return the size of the state buffer used to save the console state.
+****************************************************************************/
+int PMAPI PM_getConsoleStateSize(void)
+{
+    /* TODO: Returns the size of the console state buffer used to save the */
+    /*       state of the console before going into graphics mode. This is */
+    /*       used to restore the console back to normal when we are done. */
+    return 1;
+}
+
+/****************************************************************************
+REMARKS:
+Save the state of the console into the state buffer.
+****************************************************************************/
+void PMAPI PM_saveConsoleState(
+    void *stateBuf,
+    int console_id)
+{
+    /* TODO: Saves the state of the console into the state buffer. This is */
+    /*       used to restore the console back to normal when we are done. */
+    /*       We will always restore 80x25 text mode after being in graphics */
+    /*       mode, so if restoring text mode is all you need to do this can */
+    /*       be left empty. */
+}
+
+/****************************************************************************
+REMARKS:
+Restore the state of the console from the state buffer.
+****************************************************************************/
+void PMAPI PM_restoreConsoleState(
+    const void *stateBuf,
+    int console_id)
+{
+    /* TODO: Restore the state of the console from the state buffer. This is */
+    /*       used to restore the console back to normal when we are done. */
+    /*       We will always restore 80x25 text mode after being in graphics */
+    /*       mode, so if restoring text mode is all you need to do this can */
+    /*       be left empty. */
+}
+
+/****************************************************************************
+REMARKS:
+Close the console and return to non-fullscreen console mode.
+****************************************************************************/
+void PMAPI PM_closeConsole(
+    int console_id)
+{
+    /* TODO: Close the console when we are done, going back to text mode. */
+}
+
+/****************************************************************************
+REMARKS:
+Set the location of the OS console cursor.
+****************************************************************************/
+void PM_setOSCursorLocation(
+    int x,
+    int y)
+{
+    /* TODO: Set the OS console cursor location to the new value. This is */
+    /*       generally used for new OS ports (used mostly for DOS). */
+}
+
+/****************************************************************************
+REMARKS:
+Set the width of the OS console.
+****************************************************************************/
+void PM_setOSScreenWidth(
+    int width,
+    int height)
+{
+    /* TODO: Set the OS console screen width. This is generally unused for */
+    /*       new OS ports. */
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock handler (used for software stereo modes).
+****************************************************************************/
+ibool PMAPI PM_setRealTimeClockHandler(
+    PM_intHandler ih,
+    int frequency)
+{
+    /* TODO: Install a real time clock interrupt handler. Normally this */
+    /*       will not be supported from most OS'es in user land, so an */
+    /*       alternative mechanism is needed to enable software stereo. */
+    /*       Hence leave this unimplemented unless you have a high priority */
+    /*       mechanism to call the 32-bit callback when the real time clock */
+    /*       interrupt fires. */
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock frequency (for stereo modes).
+****************************************************************************/
+void PMAPI PM_setRealTimeClockFrequency(
+    int frequency)
+{
+    /* TODO: Set the real time clock interrupt frequency. Used for stereo */
+    /*       LC shutter glasses when doing software stereo. Usually sets */
+    /*       the frequency to around 2048 Hz. */
+}
+
+/****************************************************************************
+REMARKS:
+Restore the original real time clock handler.
+****************************************************************************/
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    /* TODO: Restores the real time clock handler. */
+}
+
+/****************************************************************************
+REMARKS:
+Return the current operating system path or working directory.
+****************************************************************************/
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    return getcwd(path,maxLen);
+}
+
+/****************************************************************************
+REMARKS:
+Return the drive letter for the boot drive.
+****************************************************************************/
+char PMAPI PM_getBootDrive(void)
+{
+    /* TODO: Return the boot drive letter for the OS. Normally this is 'c' */
+    /*       for DOS based OS'es and '/' for Unices. */
+    return '/';
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the VBE/AF driver files (legacy and not used).
+****************************************************************************/
+const char * PMAPI PM_getVBEAFPath(void)
+{
+    return PM_getNucleusConfigPath();
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus driver files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusPath(void)
+{
+    /* TODO: Change this to the default path to Nucleus driver files. The */
+    /*       following is the default for Unices. */
+    char *env = getenv("NUCLEUS_PATH");
+    return env ? env : "/usr/lib/nucleus";
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus configuration files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+/****************************************************************************
+REMARKS:
+Return a unique identifier for the machine if possible.
+****************************************************************************/
+const char * PMAPI PM_getUniqueID(void)
+{
+    /* TODO: Return a unique ID for the machine. If a unique ID is not */
+    /*       available, return the machine name. */
+    static char buf[128];
+    gethostname(buf, 128);
+    return buf;
+}
+
+/****************************************************************************
+REMARKS:
+Get the name of the machine on the network.
+****************************************************************************/
+const char * PMAPI PM_getMachineName(void)
+{
+    /* TODO: Return the network machine name for the machine. */
+    static char buf[128];
+    gethostname(buf, 128);
+    return buf;
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to the real mode BIOS data area.
+****************************************************************************/
+void * PMAPI PM_getBIOSPointer(void)
+{
+    /* TODO: This returns a pointer to the real mode BIOS data area. If you */
+    /*       do not support BIOS access, you can simply return NULL here. */
+    if (!zeroPtr)
+	zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true);
+    return (void*)(zeroPtr + 0x400);
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to 0xA0000 physical VGA graphics framebuffer.
+****************************************************************************/
+void * PMAPI PM_getA0000Pointer(void)
+{
+    static void *bankPtr;
+    if (!bankPtr)
+	bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true);
+    return bankPtr;
+}
+
+/****************************************************************************
+REMARKS:
+Map a physical address to a linear address in the callers process.
+****************************************************************************/
+void * PMAPI PM_mapPhysicalAddr(
+    ulong base,
+    ulong limit,
+    ibool isCached)
+{
+    /* TODO: This function maps a physical memory address to a linear */
+    /*       address in the address space of the calling process. */
+
+    /* NOTE: This function *must* be able to handle any phsyical base */
+    /*       address, and hence you will have to handle rounding of */
+    /*       the physical base address to a page boundary (ie: 4Kb on */
+    /*       x86 CPU's) to be able to properly map in the memory */
+    /*       region. */
+
+    /* NOTE: If possible the isCached bit should be used to ensure that */
+    /*       the PCD (Page Cache Disable) and PWT (Page Write Through) */
+    /*       bits are set to disable caching for a memory mapping used */
+    /*       for MMIO register access. We also disable caching using */
+    /*       the MTRR registers for Pentium Pro and later chipsets so if */
+    /*       MTRR support is enabled for your OS then you can safely ignore */
+    /*       the isCached flag and always enable caching in the page */
+    /*       tables. */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a physical address mapping allocated by PM_mapPhysicalAddr.
+****************************************************************************/
+void PMAPI PM_freePhysicalAddr(
+    void *ptr,
+    ulong limit)
+{
+    /* TODO: This function will free a physical memory mapping previously */
+    /*       allocated with PM_mapPhysicalAddr() if at all possible. If */
+    /*       you can't free physical memory mappings, simply do nothing. */
+}
+
+/****************************************************************************
+REMARKS:
+Find the physical address of a linear memory address in current process.
+****************************************************************************/
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{
+    /* TODO: This function should find the physical address of a linear */
+    /*       address. */
+    return 0xFFFFFFFFUL;
+}
+
+void PMAPI PM_sleep(ulong milliseconds)
+{
+    /* TODO: Put the process to sleep for milliseconds */
+}
+
+int PMAPI PM_getCOMPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	}
+    return 0;
+}
+
+int PMAPI PM_getLPTPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of (unnamed) shared memory.
+****************************************************************************/
+void * PMAPI PM_mallocShared(
+    long size)
+{
+    /* TODO: This is used to allocate memory that is shared between process */
+    /*       that all access the common Nucleus drivers via a common display */
+    /*       driver DLL. If your OS does not support shared memory (or if */
+    /*       the display driver does not need to allocate shared memory */
+    /*       for each process address space), this should just call PM_malloc. */
+    return PM_malloc(size);
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of shared memory.
+****************************************************************************/
+void PMAPI PM_freeShared(
+    void *ptr)
+{
+    /* TODO: Free the shared memory block. This will be called in the context */
+    /*       of the original calling process that allocated the shared */
+    /*       memory with PM_mallocShared. Simply call PM_free if you do not */
+    /*       need this. */
+    PM_free(ptr);
+}
+
+/****************************************************************************
+REMARKS:
+Map a linear memory address to the calling process address space. The
+address will have been allocated in another process using the
+PM_mapPhysicalAddr function.
+****************************************************************************/
+void * PMAPI PM_mapToProcess(
+    void *base,
+    ulong limit)
+{
+    /* TODO: This function is used to map a physical memory mapping */
+    /*       previously allocated with PM_mapPhysicalAddr into the */
+    /*       address space of the calling process. If the memory mapping */
+    /*       allocated by PM_mapPhysicalAddr is global to all processes, */
+    /*       simply return the pointer. */
+
+    /* NOTE: This function must also handle rounding to page boundaries, */
+    /*       since this function is used to map in shared memory buffers */
+    /*       allocated with PM_mapPhysicalAddr(). Hence if you aligned */
+    /*       the physical address above, then you also need to do it here. */
+    return base;
+}
+
+/****************************************************************************
+REMARKS:
+Map a real mode pointer to a protected mode pointer.
+****************************************************************************/
+void * PMAPI PM_mapRealPointer(
+    uint r_seg,
+    uint r_off)
+{
+    /* TODO: This function maps a real mode memory pointer into the */
+    /*       calling processes address space as a 32-bit near pointer. If */
+    /*       you do not support BIOS access, simply return NULL here. */
+    if (!zeroPtr)
+	zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF);
+    return (void*)(zeroPtr + MK_PHYS(r_seg,r_off));
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of real mode memory
+****************************************************************************/
+void * PMAPI PM_allocRealSeg(
+    uint size,
+    uint *r_seg,
+    uint *r_off)
+{
+    /* TODO: This function allocates a block of real mode memory for the */
+    /*       calling process used to communicate with real mode BIOS */
+    /*       functions. If you do not support BIOS access, simply return */
+    /*       NULL here. */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of real mode memory.
+****************************************************************************/
+void PMAPI PM_freeRealSeg(
+    void *mem)
+{
+    /* TODO: Frees a previously allocated real mode memory block. If you */
+    /*       do not support BIOS access, this function should be empty. */
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt (parameters in DPMI compatible structure)
+****************************************************************************/
+void PMAPI DPMI_int86(
+    int intno,
+    DPMI_regs *regs)
+{
+    /* TODO: This function calls the real mode BIOS using the passed in */
+    /*       register structure. If you do not support real mode BIOS */
+    /*       access, this function should be empty. */
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt.
+****************************************************************************/
+int PMAPI PM_int86(
+    int intno,
+    RMREGS *in,
+    RMREGS *out)
+{
+    /* TODO: This function calls the real mode BIOS using the passed in */
+    /*       register structure. If you do not support real mode BIOS */
+    /*       access, this function should return 0. */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt.
+****************************************************************************/
+int PMAPI PM_int86x(
+    int intno,
+    RMREGS *in,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    /* TODO: This function calls the real mode BIOS using the passed in */
+    /*       register structure. If you do not support real mode BIOS */
+    /*       access, this function should return 0. */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Call a real mode far function.
+****************************************************************************/
+void PMAPI PM_callRealMode(
+    uint seg,
+    uint off,
+    RMREGS *in,
+    RMSREGS *sregs)
+{
+    /* TODO: This function calls a real mode far function with a far call. */
+    /*       If you do not support BIOS access, this function should be */
+    /*       empty. */
+}
+
+/****************************************************************************
+REMARKS:
+Return the amount of available memory.
+****************************************************************************/
+void PMAPI PM_availableMemory(
+    ulong *physical,
+    ulong *total)
+{
+    /* TODO: Report the amount of available memory, both the amount of */
+    /*       physical memory left and the amount of virtual memory left. */
+    /*       If the OS does not provide these services, report 0's. */
+    *physical = *total = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of locked, physical memory for DMA operations.
+****************************************************************************/
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16M)
+{
+    /* TODO: Allocate a block of locked, physical memory of the specified */
+    /*       size. This is used for bus master operations. If this is not */
+    /*       supported by the OS, return NULL and bus mastering will not */
+    /*       be used. */
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of locked physical memory.
+****************************************************************************/
+void PMAPI PM_freeLockedMem(
+    void *p,
+    uint size,
+    ibool contiguous)
+{
+    /* TODO: Free a memory block allocated with PM_allocLockedMem. */
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankA(
+    int bank)
+{
+    RMREGS  regs;
+
+    /* TODO: This does a bank switch function by calling the real mode */
+    /*       VESA BIOS. If you do not support BIOS access, this function should */
+    /*       be empty. */
+    regs.x.ax = 0x4F05;
+    regs.x.bx = 0x0000;
+    regs.x.dx = bank;
+    PM_int86(0x10,&regs,&regs);
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankAB(
+    int bank)
+{
+    RMREGS  regs;
+
+    /* TODO: This does a bank switch function by calling the real mode */
+    /*       VESA BIOS. If you do not support BIOS access, this function should */
+    /*       be empty. */
+    regs.x.ax = 0x4F05;
+    regs.x.bx = 0x0000;
+    regs.x.dx = bank;
+    PM_int86(0x10,&regs,&regs);
+    regs.x.ax = 0x4F05;
+    regs.x.bx = 0x0001;
+    regs.x.dx = bank;
+    PM_int86(0x10,&regs,&regs);
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display start address.
+****************************************************************************/
+void PMAPI PM_setCRTStart(
+    int x,
+    int y,
+    int waitVRT)
+{
+    RMREGS  regs;
+
+    /* TODO: This changes the display start address by calling the real mode */
+    /*       VESA BIOS. If you do not support BIOS access, this function */
+    /*       should be empty. */
+    regs.x.ax = 0x4F07;
+    regs.x.bx = waitVRT;
+    regs.x.cx = x;
+    regs.x.dx = y;
+    PM_int86(0x10,&regs,&regs);
+}
+
+/****************************************************************************
+REMARKS:
+Enable write combining for the memory region.
+****************************************************************************/
+ibool PMAPI PM_enableWriteCombine(
+    ulong base,
+    ulong length,
+    uint type)
+{
+    /* TODO: This function should enable Pentium Pro and Pentium II MTRR */
+    /*       write combining for the passed in physical memory base address */
+    /*       and length. Normally this is done via calls to an OS specific */
+    /*       device driver as this can only be done at ring 0. */
+    /* */
+    /* NOTE: This is a *very* important function to implement! If you do */
+    /*       not implement, graphics performance on the latest Intel chips */
+    /*       will be severly impaired. For sample code that can be used */
+    /*       directly in a ring 0 device driver, see the MSDOS implementation */
+    /*       which includes assembler code to do this directly (if the */
+    /*       program is running at ring 0). */
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Execute the POST on the secondary BIOS for a controller.
+****************************************************************************/
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS)
+{
+    /* TODO: This function is used to run the BIOS POST code on a secondary */
+    /*       controller to initialise it for use. This is not necessary */
+    /*       for multi-controller operation, but it will make it a lot */
+    /*       more convenicent for end users (otherwise they have to boot */
+    /*       the system once with the secondary controller as primary, and */
+    /*       then boot with both controllers installed). */
+    /* */
+    /*       Even if you don't support full BIOS access, it would be */
+    /*       adviseable to be able to POST the secondary controllers in the */
+    /*       system using this function as a minimum requirement. Some */
+    /*       graphics hardware has registers that contain values that only */
+    /*       the BIOS knows about, which makes bring up a card from cold */
+    /*       reset difficult if the BIOS has not POST'ed it. */
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Load an OS specific shared library or DLL. If the OS does not support
+shared libraries, simply return NULL.
+****************************************************************************/
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    /* TODO: This function should load a native shared library from disk */
+    /*       given the path to the library. */
+    (void)szDLLName;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Get the address of a named procedure from a shared library.
+****************************************************************************/
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    /* TODO: This function should return the address of a named procedure */
+    /*       from a native shared library. */
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Unload a shared library.
+****************************************************************************/
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    /* TODO: This function free a previously loaded native shared library. */
+    (void)hModule;
+}
+
+/****************************************************************************
+REMARKS:
+Enable requested I/O privledge level (usually only to set to a value of
+3, and then restore it back again). If the OS is protected this function
+must be implemented in order to enable I/O port access for ring 3
+applications. The function should return the IOPL level active before
+the switch occurred so it can be properly restored.
+****************************************************************************/
+int PMAPI PM_setIOPL(
+    int level)
+{
+    /* TODO: This function should enable IOPL for the task (if IOPL is */
+    /*       not always enabled for the app through some other means). */
+    return level;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+void *PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    /* TODO: This function should start a directory enumeration search */
+    /*       given the filename (with wildcards). The data should be */
+    /*       converted and returned in the findData standard form. */
+    (void)filename;
+    (void)findData;
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    void *handle,
+    PM_findData *findData)
+{
+    /* TODO: This function should find the next file in directory enumeration */
+    /*       search given the search criteria defined in the call to */
+    /*       PM_findFirstFile. The data should be converted and returned */
+    /*       in the findData standard form. */
+    (void)handle;
+    (void)findData;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    void *handle)
+{
+    /* TODO: This function should close the find process. This may do */
+    /*       nothing for some OS'es. */
+    (void)handle;
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    if (drive == 3)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    (void)drive;
+    getcwd(dir,len);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+    /* TODO: Set the file attributes for a file */
+    (void)filename;
+    (void)attrib;
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+    return mkdir(filename) == 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+    return rmdir(filename) == 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c
new file mode 100755
index 0000000..579ef2c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c
@@ -0,0 +1,49 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    baseAddr = baseAddr;
+    bankSize = bankSize;
+    codeLen = codeLen;
+    bankFunc = bankFunc;
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c
new file mode 100755
index 0000000..820e292
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c
@@ -0,0 +1,111 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE ***
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+void __ZTimerInit(void)
+{
+    /* TODO: Do any specific internal initialisation in here */
+}
+
+/****************************************************************************
+REMARKS:
+Start the Zen Timer counting.
+****************************************************************************/
+static void __LZTimerOn(
+    LZTimerObject *tm)
+{
+    /* TODO: Start the Zen Timer counting. This should be a macro if */
+    /*       possible. */
+}
+
+/****************************************************************************
+REMARKS:
+Compute the lap time since the timer was started.
+****************************************************************************/
+static ulong __LZTimerLap(
+    LZTimerObject *tm)
+{
+    /* TODO: Compute the lap time between the current time and when the */
+    /*       timer was started. */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Stop the Zen Timer counting.
+****************************************************************************/
+static void __LZTimerOff(
+    LZTimerObject *tm)
+{
+    /* TODO: Stop the timer counting. Should be a macro if possible. */
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time in microseconds between start and end timings.
+****************************************************************************/
+static ulong __LZTimerCount(
+    LZTimerObject *tm)
+{
+    /* TODO: Compute the elapsed time and return it. Always microseconds. */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION     1
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer from the OS
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{
+    /* TODO: Read the long period timer from the OS. The resolution of this */
+    /*       timer should be around 1/20 of a second for timing long */
+    /*       periods if possible. */
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c b/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c
new file mode 100755
index 0000000..ba90262
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c
@@ -0,0 +1,90 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to install a C based
+*               control C/break interrupt handler. Note that this
+*               alternate version does not work with all extenders.
+*
+*               Functions tested:   PM_installAltBreakHandler()
+*                                   PM_restoreBreakHandler()
+*
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+volatile int breakHit = false;
+volatile int ctrlCHit = false;
+
+#pragma off (check_stack)           /* No stack checking under Watcom   */
+
+void PMAPI breakHandler(uint bHit)
+{
+    if (bHit)
+	breakHit = true;
+    else
+	ctrlCHit = true;
+}
+
+int main(void)
+{
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    PM_installAltBreakHandler(breakHandler);
+    printf("Control C/Break interrupt handler installed\n");
+    while (1) {
+	if (ctrlCHit) {
+	    printf("Code termimated with Ctrl-C.\n");
+	    break;
+	    }
+	if (breakHit) {
+	    printf("Code termimated with Ctrl-Break.\n");
+	    break;
+	    }
+	if (PM_kbhit() && PM_getch() == 0x1B) {
+	    printf("No break code detected!\n");
+	    break;
+	    }
+	printf("Hit Ctrl-C or Ctrl-Break to exit!\n");
+	}
+
+    PM_restoreBreakHandler();
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c b/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c
new file mode 100755
index 0000000..e137307
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c
@@ -0,0 +1,85 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to install a C based
+*               critical error handler.
+*
+*               Functions tested:   PM_installCriticalHandler()
+*                                   PM_criticalError()
+*                                   PM_restoreCriticalHandler()
+*
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+volatile uint criticalError = false;
+volatile uint axValue;
+volatile uint diValue;
+
+#pragma off (check_stack)           /* No stack checking under Watcom   */
+
+uint PMAPI criticalHandler(uint axVal,uint diVal)
+{
+    criticalError = true;
+    axValue = axVal;
+    diValue = diVal;
+    return 3;       /* Tell MS-DOS to fail the operation */
+}
+
+int main(void)
+{
+    FILE    *f;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    PM_installAltCriticalHandler(criticalHandler);
+    printf("Critical Error handler installed - trying to read from A: drive...\n");
+    f = fopen("a:\bog.bog","rb");
+    if (f) fclose(f);
+    if (criticalError) {
+	printf("Critical error occured on INT 21h function %02X!\n",
+	    axValue >> 8);
+	}
+    else
+	printf("Critical error was not caught!\n");
+    PM_restoreCriticalHandler();
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c b/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c
new file mode 100755
index 0000000..5fa3382
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c
@@ -0,0 +1,92 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to manipulate the
+*               BIOS data area from protected mode using the PM
+*               library. Compile and link with the appropriate command
+*               line for your DOS extender.
+*
+*               Functions tested:   PM_getBIOSSelector()
+*                                   PM_getLong()
+*                                   PM_getByte()
+*                                   PM_getWord()
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+/* Macros to obtain values from the BIOS data area */
+
+#define TICKS()     PM_getLong(bios+0x6C)
+#define KB_STAT     PM_getByte(bios+0x17)
+#define KB_HEAD     PM_getWord(bios+0x1A)
+#define KB_TAIL     PM_getWord(bios+0x1C)
+
+/* Macros for working with the keyboard buffer */
+
+#define KB_HIT()    (KB_HEAD != KB_TAIL)
+#define CTRL()      (KB_STAT & 4)
+#define SHIFT()     (KB_STAT & 2)
+#define ESC         0x1B
+
+/* Selector for BIOS data area */
+
+uchar *bios;
+
+int main(void)
+{
+    int c,done = 0;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    bios = PM_getBIOSPointer();
+    printf("Hit any key to test, Ctrl-Shift-Esc to quit\n");
+    while (!done) {
+	if (KB_HIT()) {
+	    c = PM_getch();
+	    if (c == 0) PM_getch();
+	    printf("TIME=%-8lX ST=%02X CHAR=%02X ", TICKS(), KB_STAT, c);
+	    printf("\n");
+	    if ((c == ESC) && SHIFT() && CTRL())/* Ctrl-Shift-Esc */
+		break;
+	    }
+	}
+
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/block.c b/board/MAI/bios_emulator/scitech/src/pm/tests/block.c
new file mode 100755
index 0000000..15d503c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/block.c
@@ -0,0 +1,69 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Test program for the PM_blockUntilTimeout function.
+*
+****************************************************************************/
+
+#include <stdio.h>
+#include "pmapi.h"
+
+#define DELAY_MSECS 1100
+#define LOOPS       5
+
+/*-------------------------- Implementation -------------------------------*/
+
+/* The following routine takes a long count in microseconds and outputs
+ * a string representing the count in seconds. It could be modified to
+ * return a pointer to a static string representing the count rather
+ * than printing it out.
+ */
+
+void ReportTime(ulong count)
+{
+    ulong   secs;
+
+    secs = count / 1000000L;
+    count = count - secs * 1000000L;
+    printf("Time taken: %lu.%06lu seconds\n",secs,count);
+}
+
+int main(void)
+{
+    int i;
+
+    printf("Detecting processor information ...");
+    fflush(stdout);
+    printf("\n\n%s\n", CPU_getProcessorName());
+    ZTimerInit();
+    LZTimerOn();
+    for (i = 0; i < LOOPS; i++) {
+	PM_blockUntilTimeout(DELAY_MSECS);
+	ReportTime(LZTimerLap());
+	}
+    LZTimerOff();
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c b/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c
new file mode 100755
index 0000000..10b6446
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c
@@ -0,0 +1,78 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to install a C based
+*               control C/break interrupt handler.
+*
+*               Functions tested:   PM_installBreakHandler()
+*                                   PM_ctrlCHit()
+*                                   PM_ctrlBreakHit()
+*                                   PM_restoreBreakHandler()
+*
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+int main(void)
+{
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    PM_installBreakHandler();
+    printf("Control C/Break interrupt handler installed\n");
+    while (1) {
+	if (PM_ctrlCHit(1)) {
+	    printf("Code termimated with Ctrl-C.\n");
+	    break;
+	    }
+	if (PM_ctrlBreakHit(1)) {
+	    printf("Code termimated with Ctrl-Break.\n");
+	    break;
+	    }
+	if (PM_kbhit() && PM_getch() == 0x1B) {
+	    printf("No break code detected!\n");
+	    break;
+	    }
+	printf("Hit Ctrl-C or Ctrl-Break to exit!\n");
+	}
+
+    PM_restoreBreakHandler();
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c b/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c
new file mode 100755
index 0000000..4d37cab
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c
@@ -0,0 +1,107 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to call a real mode
+*               procedure. We simply copy a terribly simple assembly
+*               language routine into a real mode block that we allocate,
+*               and then attempt to call the routine and verify that it
+*               was successful.
+*
+*               Functions tested:   PM_allocRealSeg()
+*                                   PM_freeRealSeg()
+*                                   PM_callRealMode()
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include "pmapi.h"
+
+/* Block of real mode code we will eventually call */
+
+static unsigned char realModeCode[] = {
+    0x93,           /*  xchg    ax,bx   */
+    0x87, 0xCA,     /*  xchg    cx,dx   */
+    0xCB            /*  retf            */
+    };
+
+int main(void)
+{
+    RMREGS          regs;
+    RMSREGS         sregs;
+    uchar           *p;
+    unsigned        r_seg,r_off;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    /* Allocate a the block of real mode memory */
+    if ((p = PM_allocRealSeg(sizeof(realModeCode), &r_seg, &r_off)) == NULL) {
+	printf("Unable to allocate real mode memory!\n");
+	exit(1);
+	}
+
+    /* Copy the real mode code */
+    memcpy(p,realModeCode,sizeof(realModeCode));
+
+    /* Now call the real mode code */
+    regs.x.ax = 1;
+    regs.x.bx = 2;
+    regs.x.cx = 3;
+    regs.x.dx = 4;
+    regs.x.si = 5;
+    regs.x.di = 6;
+    sregs.es = 7;
+    sregs.ds = 8;
+    PM_callRealMode(r_seg,r_off,&regs,&sregs);
+    if (regs.x.ax != 2 || regs.x.bx != 1 || regs.x.cx != 4 || regs.x.dx != 3
+	    || regs.x.si != 5 || regs.x.di != 6 || sregs.es != 7
+	    || sregs.ds != 8) {
+	printf("Real mode call failed!\n");
+	printf("\n");
+	printf("ax = %04X, bx = %04X, cx = %04X, dx = %04X\n",
+	    regs.x.ax,regs.x.bx,regs.x.cx,regs.x.dx);
+	printf("si = %04X, di = %04X, es = %04X, ds = %04X\n",
+	    regs.x.si,regs.x.di,sregs.es,sregs.ds);
+	}
+    else
+	printf("Real mode call succeeded!\n");
+
+    /* Free the memory we allocated */
+    PM_freeRealSeg(p);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c b/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c
new file mode 100755
index 0000000..5933ac9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c
@@ -0,0 +1,100 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Main module for building checked builds of products with
+*               assertions and trace code.
+*
+****************************************************************************/
+
+#include "scitech.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#ifdef  __WINDOWS__
+#define WIN32_LEAN_AND_MEAN
+#define STRICT
+#include <windows.h>
+#endif
+
+#ifdef  CHECKED
+
+/*---------------------------- Global variables ---------------------------*/
+
+#define LOGFILE "\\scitech.log"
+
+void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line) = _CHK_defaultFail;
+
+/*---------------------------- Implementation -----------------------------*/
+
+/****************************************************************************
+DESCRIPTION:
+Handles fatal error and warning conditions for checked builds.
+
+HEADER:
+scitech.h
+
+REMARKS:
+This function is called whenever an inline check or warning fails in any
+of the SciTech runtime libraries. Warning conditions simply cause the
+condition to be logged to the log file and send to the system debugger
+under Window. Fatal error conditions do all of the above, and then
+terminate the program with a fatal error conditions.
+
+This handler may be overriden by the user code if necessary to replace it
+with a different handler (the MGL for instance overrides this and replaces
+it with a handler that does an MGL_exit() before terminating the application
+so that it will clean up correctly.
+****************************************************************************/
+void _CHK_defaultFail(
+    int fatal,
+    const char *msg,
+    const char *cond,
+    const char *file,
+    int line)
+{
+    char    buf[256];
+    FILE    *log = fopen(LOGFILE, "at+");
+
+    sprintf(buf,msg,cond,file,line);
+    if (log) {
+	fputs(buf,log);
+	fflush(log);
+	fclose(log);
+#ifdef  __WINDOWS__
+	OutputDebugStr(buf);
+#endif
+	}
+    if (fatal) {
+#ifdef  __WINDOWS__
+	MessageBox(NULL, buf,"Fatal Error!",MB_ICONEXCLAMATION);
+#else
+	fputs(buf,stderr);
+#endif
+	exit(-1);
+	}
+}
+
+#endif  /* CHECKED */
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c b/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c
new file mode 100755
index 0000000..30e5dd3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c
@@ -0,0 +1,46 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Test program for the CPU detection code.
+*
+****************************************************************************/
+
+#include "ztimer.h"
+#include "pmapi.h"
+#include <stdio.h>
+#include <stdlib.h>
+
+/*----------------------------- Implementation ----------------------------*/
+
+int main(void)
+{
+    printf("Detecting processor information ...");
+    fflush(stdout);
+    printf("\n\n%s\n", CPU_getProcessorName());
+    if (CPU_haveRDTSC())
+	printf("\nProcessor supports Read Time Stamp Counter performance timer.\n");
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c b/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c
new file mode 100755
index 0000000..60f1251
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c
@@ -0,0 +1,70 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to install a C based
+*               critical error handler.
+*
+*               Functions tested:   PM_installAltCriticalHandler()
+*                                   PM_restoreCriticalHandler()
+*
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+int main(void)
+{
+    FILE    *f;
+    int     axcode,dicode;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    PM_installCriticalHandler();
+    printf("Critical Error handler installed - trying to read from A: drive...\n");
+    f = fopen("a:\bog.bog","rb");
+    if (f) fclose(f);
+    if (PM_criticalError(&axcode,&dicode,1)) {
+	printf("Critical error occured on INT 21h function %02X!\n",
+	    axcode >> 8);
+	}
+    else printf("Critical error was not caught!\n");
+    PM_restoreCriticalHandler();
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c b/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c
new file mode 100755
index 0000000..06c2180
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c
@@ -0,0 +1,501 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Test program to test out the cross platform event handling
+*               library.
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <ctype.h>
+#include "pmapi.h"
+#include "event.h"
+
+/* Translation table for key codes */
+
+typedef struct {
+    int     code;
+    char    *name;
+    } KeyEntry;
+
+KeyEntry ASCIICodes[] = {
+    {ASCII_ctrlA            ,"ASCII_ctrlA"},
+    {ASCII_ctrlB            ,"ASCII_ctrlB"},
+    {ASCII_ctrlC            ,"ASCII_ctrlC"},
+    {ASCII_ctrlD            ,"ASCII_ctrlD"},
+    {ASCII_ctrlE            ,"ASCII_ctrlE"},
+    {ASCII_ctrlF            ,"ASCII_ctrlF"},
+    {ASCII_ctrlG            ,"ASCII_ctrlG"},
+    {ASCII_backspace        ,"ASCII_backspace"},
+    {ASCII_ctrlH            ,"ASCII_ctrlH"},
+    {ASCII_tab              ,"ASCII_tab"},
+    {ASCII_ctrlI            ,"ASCII_ctrlI"},
+    {ASCII_ctrlJ            ,"ASCII_ctrlJ"},
+    {ASCII_ctrlK            ,"ASCII_ctrlK"},
+    {ASCII_ctrlL            ,"ASCII_ctrlL"},
+    {ASCII_enter            ,"ASCII_enter"},
+    {ASCII_ctrlM            ,"ASCII_ctrlM"},
+    {ASCII_ctrlN            ,"ASCII_ctrlN"},
+    {ASCII_ctrlO            ,"ASCII_ctrlO"},
+    {ASCII_ctrlP            ,"ASCII_ctrlP"},
+    {ASCII_ctrlQ            ,"ASCII_ctrlQ"},
+    {ASCII_ctrlR            ,"ASCII_ctrlR"},
+    {ASCII_ctrlS            ,"ASCII_ctrlS"},
+    {ASCII_ctrlT            ,"ASCII_ctrlT"},
+    {ASCII_ctrlU            ,"ASCII_ctrlU"},
+    {ASCII_ctrlV            ,"ASCII_ctrlV"},
+    {ASCII_ctrlW            ,"ASCII_ctrlW"},
+    {ASCII_ctrlX            ,"ASCII_ctrlX"},
+    {ASCII_ctrlY            ,"ASCII_ctrlY"},
+    {ASCII_ctrlZ            ,"ASCII_ctrlZ"},
+    {ASCII_esc              ,"ASCII_esc"},
+    {ASCII_space            ,"ASCII_space"},
+    {ASCII_exclamation      ,"ASCII_exclamation"},
+    {ASCII_quote            ,"ASCII_quote"},
+    {ASCII_pound            ,"ASCII_pound"},
+    {ASCII_dollar           ,"ASCII_dollar"},
+    {ASCII_percent          ,"ASCII_percent"},
+    {ASCII_ampersand        ,"ASCII_ampersand"},
+    {ASCII_apostrophe       ,"ASCII_apostrophe"},
+    {ASCII_leftBrace        ,"ASCII_leftBrace"},
+    {ASCII_rightBrace       ,"ASCII_rightBrace"},
+    {ASCII_times            ,"ASCII_times"},
+    {ASCII_plus             ,"ASCII_plus"},
+    {ASCII_comma            ,"ASCII_comma"},
+    {ASCII_minus            ,"ASCII_minus"},
+    {ASCII_period           ,"ASCII_period"},
+    {ASCII_divide           ,"ASCII_divide"},
+    {ASCII_0                ,"ASCII_0"},
+    {ASCII_1                ,"ASCII_1"},
+    {ASCII_2                ,"ASCII_2"},
+    {ASCII_3                ,"ASCII_3"},
+    {ASCII_4                ,"ASCII_4"},
+    {ASCII_5                ,"ASCII_5"},
+    {ASCII_6                ,"ASCII_6"},
+    {ASCII_7                ,"ASCII_7"},
+    {ASCII_8                ,"ASCII_8"},
+    {ASCII_9                ,"ASCII_9"},
+    {ASCII_colon            ,"ASCII_colon"},
+    {ASCII_semicolon        ,"ASCII_semicolon"},
+    {ASCII_lessThan         ,"ASCII_lessThan"},
+    {ASCII_equals           ,"ASCII_equals"},
+    {ASCII_greaterThan      ,"ASCII_greaterThan"},
+    {ASCII_question         ,"ASCII_question"},
+    {ASCII_at               ,"ASCII_at"},
+    {ASCII_A                ,"ASCII_A"},
+    {ASCII_B                ,"ASCII_B"},
+    {ASCII_C                ,"ASCII_C"},
+    {ASCII_D                ,"ASCII_D"},
+    {ASCII_E                ,"ASCII_E"},
+    {ASCII_F                ,"ASCII_F"},
+    {ASCII_G                ,"ASCII_G"},
+    {ASCII_H                ,"ASCII_H"},
+    {ASCII_I                ,"ASCII_I"},
+    {ASCII_J                ,"ASCII_J"},
+    {ASCII_K                ,"ASCII_K"},
+    {ASCII_L                ,"ASCII_L"},
+    {ASCII_M                ,"ASCII_M"},
+    {ASCII_N                ,"ASCII_N"},
+    {ASCII_O                ,"ASCII_O"},
+    {ASCII_P                ,"ASCII_P"},
+    {ASCII_Q                ,"ASCII_Q"},
+    {ASCII_R                ,"ASCII_R"},
+    {ASCII_S                ,"ASCII_S"},
+    {ASCII_T                ,"ASCII_T"},
+    {ASCII_U                ,"ASCII_U"},
+    {ASCII_V                ,"ASCII_V"},
+    {ASCII_W                ,"ASCII_W"},
+    {ASCII_X                ,"ASCII_X"},
+    {ASCII_Y                ,"ASCII_Y"},
+    {ASCII_Z                ,"ASCII_Z"},
+    {ASCII_leftSquareBrace  ,"ASCII_leftSquareBrace"},
+    {ASCII_backSlash        ,"ASCII_backSlash"},
+    {ASCII_rightSquareBrace ,"ASCII_rightSquareBrace"},
+    {ASCII_caret            ,"ASCII_caret"},
+    {ASCII_underscore       ,"ASCII_underscore"},
+    {ASCII_leftApostrophe   ,"ASCII_leftApostrophe"},
+    {ASCII_a                ,"ASCII_a"},
+    {ASCII_b                ,"ASCII_b"},
+    {ASCII_c                ,"ASCII_c"},
+    {ASCII_d                ,"ASCII_d"},
+    {ASCII_e                ,"ASCII_e"},
+    {ASCII_f                ,"ASCII_f"},
+    {ASCII_g                ,"ASCII_g"},
+    {ASCII_h                ,"ASCII_h"},
+    {ASCII_i                ,"ASCII_i"},
+    {ASCII_j                ,"ASCII_j"},
+    {ASCII_k                ,"ASCII_k"},
+    {ASCII_l                ,"ASCII_l"},
+    {ASCII_m                ,"ASCII_m"},
+    {ASCII_n                ,"ASCII_n"},
+    {ASCII_o                ,"ASCII_o"},
+    {ASCII_p                ,"ASCII_p"},
+    {ASCII_q                ,"ASCII_q"},
+    {ASCII_r                ,"ASCII_r"},
+    {ASCII_s                ,"ASCII_s"},
+    {ASCII_t                ,"ASCII_t"},
+    {ASCII_u                ,"ASCII_u"},
+    {ASCII_v                ,"ASCII_v"},
+    {ASCII_w                ,"ASCII_w"},
+    {ASCII_x                ,"ASCII_x"},
+    {ASCII_y                ,"ASCII_y"},
+    {ASCII_z                ,"ASCII_z"},
+    {ASCII_leftCurlyBrace   ,"ASCII_leftCurlyBrace"},
+    {ASCII_verticalBar      ,"ASCII_verticalBar"},
+    {ASCII_rightCurlyBrace  ,"ASCII_rightCurlyBrace"},
+    {ASCII_tilde            ,"ASCII_tilde"},
+    {0                      ,"ASCII_unknown"},
+    };
+
+KeyEntry ScanCodes[] = {
+    {KB_padEnter            ,"KB_padEnter"},
+    {KB_padMinus            ,"KB_padMinus"},
+    {KB_padPlus             ,"KB_padPlus"},
+    {KB_padTimes            ,"KB_padTimes"},
+    {KB_padDivide           ,"KB_padDivide"},
+    {KB_padLeft             ,"KB_padLeft"},
+    {KB_padRight            ,"KB_padRight"},
+    {KB_padUp               ,"KB_padUp"},
+    {KB_padDown             ,"KB_padDown"},
+    {KB_padInsert           ,"KB_padInsert"},
+    {KB_padDelete           ,"KB_padDelete"},
+    {KB_padHome             ,"KB_padHome"},
+    {KB_padEnd              ,"KB_padEnd"},
+    {KB_padPageUp           ,"KB_padPageUp"},
+    {KB_padPageDown         ,"KB_padPageDown"},
+    {KB_padCenter           ,"KB_padCenter"},
+    {KB_F1                  ,"KB_F1"},
+    {KB_F2                  ,"KB_F2"},
+    {KB_F3                  ,"KB_F3"},
+    {KB_F4                  ,"KB_F4"},
+    {KB_F5                  ,"KB_F5"},
+    {KB_F6                  ,"KB_F6"},
+    {KB_F7                  ,"KB_F7"},
+    {KB_F8                  ,"KB_F8"},
+    {KB_F9                  ,"KB_F9"},
+    {KB_F10                 ,"KB_F10"},
+    {KB_F11                 ,"KB_F11"},
+    {KB_F12                 ,"KB_F12"},
+    {KB_left                ,"KB_left"},
+    {KB_right               ,"KB_right"},
+    {KB_up                  ,"KB_up"},
+    {KB_down                ,"KB_down"},
+    {KB_insert              ,"KB_insert"},
+    {KB_delete              ,"KB_delete"},
+    {KB_home                ,"KB_home"},
+    {KB_end                 ,"KB_end"},
+    {KB_pageUp              ,"KB_pageUp"},
+    {KB_pageDown            ,"KB_pageDown"},
+    {KB_capsLock            ,"KB_capsLock"},
+    {KB_numLock             ,"KB_numLock"},
+    {KB_scrollLock          ,"KB_scrollLock"},
+    {KB_leftShift           ,"KB_leftShift"},
+    {KB_rightShift          ,"KB_rightShift"},
+    {KB_leftCtrl            ,"KB_leftCtrl"},
+    {KB_rightCtrl           ,"KB_rightCtrl"},
+    {KB_leftAlt             ,"KB_leftAlt"},
+    {KB_rightAlt            ,"KB_rightAlt"},
+    {KB_leftWindows         ,"KB_leftWindows"},
+    {KB_rightWindows        ,"KB_rightWindows"},
+    {KB_menu                ,"KB_menu"},
+    {KB_sysReq              ,"KB_sysReq"},
+    {KB_esc                 ,"KB_esc"},
+    {KB_1                   ,"KB_1"},
+    {KB_2                   ,"KB_2"},
+    {KB_3                   ,"KB_3"},
+    {KB_4                   ,"KB_4"},
+    {KB_5                   ,"KB_5"},
+    {KB_6                   ,"KB_6"},
+    {KB_7                   ,"KB_7"},
+    {KB_8                   ,"KB_8"},
+    {KB_9                   ,"KB_9"},
+    {KB_0                   ,"KB_0"},
+    {KB_minus               ,"KB_minus"},
+    {KB_equals              ,"KB_equals"},
+    {KB_backSlash           ,"KB_backSlash"},
+    {KB_backspace           ,"KB_backspace"},
+    {KB_tab                 ,"KB_tab"},
+    {KB_Q                   ,"KB_Q"},
+    {KB_W                   ,"KB_W"},
+    {KB_E                   ,"KB_E"},
+    {KB_R                   ,"KB_R"},
+    {KB_T                   ,"KB_T"},
+    {KB_Y                   ,"KB_Y"},
+    {KB_U                   ,"KB_U"},
+    {KB_I                   ,"KB_I"},
+    {KB_O                   ,"KB_O"},
+    {KB_P                   ,"KB_P"},
+    {KB_leftSquareBrace     ,"KB_leftSquareBrace"},
+    {KB_rightSquareBrace    ,"KB_rightSquareBrace"},
+    {KB_enter               ,"KB_enter"},
+    {KB_A                   ,"KB_A"},
+    {KB_S                   ,"KB_S"},
+    {KB_D                   ,"KB_D"},
+    {KB_F                   ,"KB_F"},
+    {KB_G                   ,"KB_G"},
+    {KB_H                   ,"KB_H"},
+    {KB_J                   ,"KB_J"},
+    {KB_K                   ,"KB_K"},
+    {KB_L                   ,"KB_L"},
+    {KB_semicolon           ,"KB_semicolon"},
+    {KB_apostrophe          ,"KB_apostrophe"},
+    {KB_Z                   ,"KB_Z"},
+    {KB_X                   ,"KB_X"},
+    {KB_C                   ,"KB_C"},
+    {KB_V                   ,"KB_V"},
+    {KB_B                   ,"KB_B"},
+    {KB_N                   ,"KB_N"},
+    {KB_M                   ,"KB_M"},
+    {KB_comma               ,"KB_comma"},
+    {KB_period              ,"KB_period"},
+    {KB_divide              ,"KB_divide"},
+    {KB_space               ,"KB_space"},
+    {KB_tilde               ,"KB_tilde"},
+    {0                      ,"KB_unknown"},
+    };
+
+/****************************************************************************
+PARAMETERS:
+x   - X coordinate of the mouse cursor position (screen coordinates)
+y   - Y coordinate of the mouse cursor position (screen coordinates)
+
+REMARKS:
+This gets called periodically to move the mouse. It will get called when
+the mouse may not have actually moved, so check if it has before redrawing
+it.
+****************************************************************************/
+void EVTAPI moveMouse(
+    int x,
+    int y)
+{
+}
+
+/****************************************************************************
+PARAMETERS:
+code    - Code to translate
+keys    - Table of translation key values to look up
+
+REMARKS:
+Simple function to look up the printable name for the keyboard code.
+****************************************************************************/
+KeyEntry *FindKey(
+    int code,
+    KeyEntry *keys)
+{
+    KeyEntry    *key;
+
+    for (key = keys; key->code != 0; key++) {
+	if (key->code == code)
+	    break;
+	}
+    return key;
+}
+
+/****************************************************************************
+PARAMETERS:
+evt - Event to display modifiers for
+
+REMARKS:
+Function to display shift modifiers flags
+****************************************************************************/
+void DisplayModifiers(
+    event_t *evt)
+{
+    if (evt->modifiers & EVT_LEFTBUT)
+	printf(", LBUT");
+    if (evt->modifiers & EVT_RIGHTBUT)
+	printf(", RBUT");
+    if (evt->modifiers & EVT_MIDDLEBUT)
+	printf(", MBUT");
+    if (evt->modifiers & EVT_SHIFTKEY) {
+	if (evt->modifiers & EVT_LEFTSHIFT)
+	    printf(", LSHIFT");
+	if (evt->modifiers & EVT_RIGHTSHIFT)
+	    printf(", RSHIFT");
+	}
+    if (evt->modifiers & EVT_CTRLSTATE) {
+	if (evt->modifiers & EVT_LEFTCTRL)
+	    printf(", LCTRL");
+	if (evt->modifiers & EVT_RIGHTCTRL)
+	    printf(", RCTRL");
+	}
+    if (evt->modifiers & EVT_ALTSTATE) {
+	if (evt->modifiers & EVT_LEFTALT)
+	    printf(", LALT");
+	if (evt->modifiers & EVT_RIGHTALT)
+	    printf(", RALT");
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+msg - Message to display for type of event
+evt - Event to display
+
+REMARKS:
+Function to display the status of the keyboard event to the screen.
+****************************************************************************/
+void DisplayKey(
+    char *msg,
+    event_t *evt)
+{
+    KeyEntry    *ascii,*scan;
+    char        ch = EVT_asciiCode(evt->message);
+
+    ascii = FindKey(ch,ASCIICodes);
+    scan = FindKey(EVT_scanCode(evt->message),ScanCodes);
+    printf("%s: 0x%04X -> %s, %s, '%c'",
+	msg, (int)evt->message & 0xFFFF, scan->name, ascii->name, isprint(ch) ? ch : ' ');
+    DisplayModifiers(evt);
+    printf("\n");
+}
+
+/****************************************************************************
+PARAMETERS:
+msg - Message to display for type of event
+evt - Event to display
+
+REMARKS:
+Function to display the status of the mouse event to the screen.
+****************************************************************************/
+void DisplayMouse(
+    char *msg,
+    event_t *evt)
+{
+    printf("%s: ", msg);
+    if (evt->message & EVT_LEFTBMASK)
+	printf("LEFT ");
+    if (evt->message & EVT_RIGHTBMASK)
+	printf("RIGHT ");
+    if (evt->message & EVT_MIDDLEBMASK)
+	printf("MIDDLE ");
+    printf("abs(%d,%d), rel(%d,%d)", evt->where_x, evt->where_y, evt->relative_x, evt->relative_y);
+    DisplayModifiers(evt);
+    if (evt->message & EVT_DBLCLICK)
+	printf(", DBLCLICK");
+    printf("\n");
+}
+
+/****************************************************************************
+PARAMETERS:
+msg - Message to display for type of event
+evt - Event to display
+
+REMARKS:
+Function to display the status of the joystick event to the screen.
+****************************************************************************/
+void DisplayJoy(
+    char *msg,
+    event_t *evt)
+{
+    printf("%s: Joy1(%4d,%4d,%c%c), Joy2(%4d,%4d,%c%c)\n", msg,
+	evt->where_x,evt->where_y,
+	(evt->message & EVT_JOY1_BUTTONA) ? 'A' : 'a',
+	(evt->message & EVT_JOY1_BUTTONB) ? 'B' : 'b',
+	evt->relative_x,evt->relative_y,
+	(evt->message & EVT_JOY2_BUTTONA) ? 'A' : 'a',
+	(evt->message & EVT_JOY2_BUTTONB) ? 'B' : 'b');
+}
+
+/****************************************************************************
+REMARKS:
+Joystick calibration routine
+****************************************************************************/
+void CalibrateJoy(void)
+{
+  event_t evt;
+  if(EVT_joyIsPresent()){
+    printf("Joystick Calibration\nMove the joystick to the upper left corner and press any button.\n");
+    EVT_halt(&evt, EVT_JOYCLICK);
+    EVT_halt(&evt, EVT_JOYCLICK);
+    EVT_joySetUpperLeft();
+    printf("Move the joystick to the lower right corner and press any button.\n");
+    EVT_halt(&evt, EVT_JOYCLICK);
+    EVT_halt(&evt, EVT_JOYCLICK);
+    EVT_joySetLowerRight();
+    printf("Move the joystick to center position and press any button.\n");
+    EVT_halt(&evt, EVT_JOYCLICK);
+    EVT_halt(&evt, EVT_JOYCLICK);
+    EVT_joySetCenter();
+    printf("Joystick calibrated\n");
+  }
+}
+
+/****************************************************************************
+REMARKS:
+Main program entry point
+****************************************************************************/
+int main(void)
+{
+    event_t     evt;
+    ibool       done = false;
+    PM_HWND     hwndConsole;
+
+    hwndConsole = PM_openConsole(0,0,0,0,0,true);
+    EVT_init(&moveMouse);
+    EVT_setMouseRange(1024,768);
+    CalibrateJoy();
+    do {
+	EVT_pollJoystick();
+	if (EVT_getNext(&evt,EVT_EVERYEVT)) {
+	    switch (evt.what) {
+		case EVT_KEYDOWN:
+		    DisplayKey("EVT_KEYDOWN  ", &evt);
+		    if (EVT_scanCode(evt.message) == KB_esc)
+			done = true;
+		    break;
+		case EVT_KEYREPEAT:
+		    DisplayKey("EVT_KEYREPEAT", &evt);
+		    break;
+		case EVT_KEYUP:
+		    DisplayKey("EVT_KEYUP    ", &evt);
+		    break;
+		case EVT_MOUSEDOWN:
+		    DisplayMouse("EVT_MOUSEDOWN", &evt);
+		    break;
+		case EVT_MOUSEAUTO:
+		    DisplayMouse("EVT_MOUSEAUTO", &evt);
+		    break;
+		case EVT_MOUSEUP:
+		    DisplayMouse("EVT_MOUSEUP  ", &evt);
+		    break;
+		case EVT_MOUSEMOVE:
+		    DisplayMouse("EVT_MOUSEMOVE", &evt);
+		    break;
+		case EVT_JOYCLICK:
+		    DisplayJoy("EVT_JOYCLICK ", &evt);
+		    break;
+		case EVT_JOYMOVE:
+		    DisplayJoy("EVT_JOYMOVE  ", &evt);
+		    break;
+		}
+	    }
+	} while (!done);
+    EVT_exit();
+    PM_closeConsole(hwndConsole);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c b/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c
new file mode 100755
index 0000000..67ad245
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c
@@ -0,0 +1,110 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to allocate real mode
+*               memory and to call real mode interrupt handlers such as
+*               the VESA VBE BIOS from protected mode. Compile and link
+*               with the appropriate command line for your DOS extender.
+*
+*               Functions tested:   PM_getVESABuf()
+*                                   PM_mapRealPointer()
+*                                   PM_int86x()
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include "pmapi.h"
+
+/* SuperVGA information block */
+
+#pragma pack(1)
+
+typedef struct {
+    char    VESASignature[4];       /* 'VESA' 4 byte signature          */
+    short   VESAVersion;            /* VBE version number               */
+    ulong   OEMStringPtr;           /* Far pointer to OEM string        */
+    ulong   Capabilities;           /* Capabilities of video card       */
+    ulong   VideoModePtr;           /* Far pointer to supported modes   */
+    short   TotalMemory;            /* Number of 64kb memory blocks     */
+    char    reserved[236];          /* Pad to 256 byte block size       */
+    } VgaInfoBlock;
+
+#pragma pack()
+
+int main(void)
+{
+    RMREGS          regs;
+    RMSREGS         sregs;
+    VgaInfoBlock    vgaInfo;
+    ushort          *mode;
+    uint            vgLen;
+    uchar           *vgPtr;
+    unsigned        r_vgseg,r_vgoff;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    /* Allocate a 256 byte block of real memory for communicating with
+     * the VESA BIOS.
+     */
+    if ((vgPtr = PM_getVESABuf(&vgLen,&r_vgseg,&r_vgoff)) == NULL) {
+	printf("Unable to allocate VESA memory buffer!\n");
+	exit(1);
+	}
+
+    /* Call the VESA VBE to see if it is out there */
+    regs.x.ax = 0x4F00;
+    regs.x.di = r_vgoff;
+    sregs.es = r_vgseg;
+    memcpy(vgPtr,"VBE2",4);
+    PM_int86x(0x10, &regs, &regs, &sregs);
+    memcpy(&vgaInfo,vgPtr,sizeof(VgaInfoBlock));
+    if (regs.x.ax == 0x4F && strncmp(vgaInfo.VESASignature,"VESA",4) == 0) {
+	printf("VESA VBE version %d.%d BIOS detected\n\n",
+	    vgaInfo.VESAVersion >> 8, vgaInfo.VESAVersion & 0xF);
+	printf("Available video modes:\n");
+	mode = PM_mapRealPointer(vgaInfo.VideoModePtr >> 16, vgaInfo.VideoModePtr & 0xFFFF);
+	while (*mode != 0xFFFF) {
+	    printf("    %04hXh (%08X)\n", *mode, (int)mode);
+	    mode++;
+	    }
+	}
+    else
+	printf("VESA VBE not found\n");
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/key.c b/board/MAI/bios_emulator/scitech/src/pm/tests/key.c
new file mode 100755
index 0000000..dba8885
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/key.c
@@ -0,0 +1,92 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to install a C based
+*               keyboard interrupt handler.
+*
+*               Functions tested:   PM_setKeyHandler()
+*                                   PM_chainPrevKey()
+*                                   PM_restoreKeyHandler()
+*
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+volatile long count = 0;
+
+#pragma off (check_stack)           /* No stack checking under Watcom   */
+
+void PMAPI keyHandler(void)
+{
+    count++;
+    PM_chainPrevKey();  /* Chain to previous handler    */
+}
+
+int main(void)
+{
+    int             ch;
+    PM_lockHandle   lh;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    /* Install our timer handler and lock handler pages in memory. It is
+     * difficult to get the size of a function in C, but we know our
+     * function is well less than 100 bytes (and an entire 4k page will
+     * need to be locked by the server anyway).
+     */
+    PM_lockCodePages((__codePtr)keyHandler,100,&lh);
+    PM_lockDataPages((void*)&count,sizeof(count),&lh);
+    PM_installBreakHandler();           /* We *DONT* want Ctrl-Breaks! */
+    PM_setKeyHandler(keyHandler);
+    printf("Keyboard interrupt handler installed - Type some characters and\n");
+    printf("hit ESC to exit\n");
+    while ((ch = PM_getch()) != 0x1B) {
+	printf("%c", ch);
+	fflush(stdout);
+	}
+
+    PM_restoreKeyHandler();
+    PM_restoreBreakHandler();
+    PM_unlockDataPages((void*)&count,sizeof(count),&lh);
+    PM_unlockCodePages((__codePtr)keyHandler,100,&lh);
+    printf("\n\nKeyboard handler was called %ld times\n", count);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c b/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c
new file mode 100755
index 0000000..b0b94be
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c
@@ -0,0 +1,96 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to install a C based
+*               keyboard Int 15h interrupt handler. This is an alternate
+*               way to intercept scancodes from the keyboard by hooking
+*               the Int 15h keyboard intercept callout.
+*
+*               Functions tested:   PM_setKey15Handler()
+*                                   PM_restoreKey15Handler()
+*
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+volatile long count = 0;
+volatile short lastScanCode = 0;
+
+#pragma off (check_stack)           /* No stack checking under Watcom   */
+
+short PMAPI keyHandler(short scanCode)
+{
+    count++;
+    lastScanCode = scanCode;
+    return scanCode;            /* Let BIOS process as normal */
+}
+
+int main(void)
+{
+    int             ch;
+    PM_lockHandle   lh;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    /* Install our timer handler and lock handler pages in memory. It is
+     * difficult to get the size of a function in C, but we know our
+     * function is well less than 100 bytes (and an entire 4k page will
+     * need to be locked by the server anyway).
+     */
+    PM_lockCodePages((__codePtr)keyHandler,100,&lh);
+    PM_lockDataPages((void*)&count,sizeof(count),&lh);
+    PM_installBreakHandler();       /* We *DONT* want Ctrl-Break's! */
+    PM_setKey15Handler(keyHandler);
+    printf("Keyboard interrupt handler installed - Type some characters and\n");
+    printf("hit ESC to exit\n");
+    while ((ch = PM_getch()) != 0x1B) {
+	printf("%c", ch);
+	fflush(stdout);
+	}
+
+    PM_restoreKey15Handler();
+    PM_restoreBreakHandler();
+    PM_unlockDataPages((void*)&count,sizeof(count),&lh);
+    PM_unlockCodePages((__codePtr)keyHandler,100,&lh);
+    printf("\n\nKeyboard handler was called %ld times\n", count);
+    printf("Last scan code %04X\n", lastScanCode);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c b/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c
new file mode 100755
index 0000000..a2c655b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c
@@ -0,0 +1,106 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to determine just how much memory can be
+*               allocated with the compiler in use. Compile and link
+*               with the appropriate command line for your DOS extender.
+*
+*               Functions tested:   PM_malloc()
+*                                   PM_availableMemory()
+*
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <math.h>
+#include "pmapi.h"
+
+#ifdef  __16BIT__
+#define MAXALLOC    64
+#else
+#define MAXALLOC    2000
+#endif
+
+int main(void)
+{
+    int     i;
+    ulong   allocs;
+    ulong   physical,total;
+    char    *p,*pa[MAXALLOC];
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    printf("Memory available at start:\n");
+    PM_availableMemory(&physical,&total);
+    printf("   Physical memory:           %ld Kb\n", physical / 1024);
+    printf("   Total (including virtual): %ld Kb\n", total / 1024);
+    printf("\n");
+    for (allocs = i = 0; i < MAXALLOC; i++) {
+	if ((pa[i] = PM_malloc(10*1024)) != 0) {    /* in 10k blocks    */
+	    p = pa[allocs];
+	    memset(p, 0, 10*1024); /* touch every byte              */
+	    *p = 'x';           /* do something, anything with      */
+	    p[1023] = 'y';      /* the allocated memory             */
+	    allocs++;
+	    printf("Allocated %lu bytes\r", 10*(allocs << 10));
+	    }
+	else break;
+	if (PM_kbhit() && (PM_getch() == 0x1B))
+	    break;
+	}
+
+    printf("\n\nAllocated total of %lu bytes\n", 10 * (allocs << 10));
+
+    printf("\nMemory available at end:\n");
+    PM_availableMemory(&physical,&total);
+    printf("   Physical memory:           %ld Kb\n", physical / 1024);
+    printf("   Total (including virtual): %ld Kb\n", total / 1024);
+
+    for (i = allocs-1; i >= 0; i--)
+	PM_free(pa[i]);
+
+    printf("\nMemory available after freeing all blocks (note that under protected mode\n");
+    printf("this will most likely not be correct after freeing blocks):\n\n");
+    PM_availableMemory(&physical,&total);
+    printf("   Physical memory:           %ld Kb\n", physical / 1024);
+    printf("   Total (including virtual): %ld Kb\n", total / 1024);
+
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c b/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c
new file mode 100755
index 0000000..2765a0d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c
@@ -0,0 +1,109 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to install an assembly
+*               language mouse interrupt handler. We use assembly language
+*               as it must be a far function and should swap to a local
+*               32 bit stack if it is going to call any C based code (which
+*               we do in this example).
+*
+*               Functions tested:   PM_installMouseHandler()
+*                                   PM_int86()
+*
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+volatile long count = 0;
+
+#pragma off (check_stack)           /* No stack checking under Watcom   */
+
+void PMAPI mouseHandler(
+    uint mask,
+    uint butstate,
+    int x,
+    int y,
+    int mickeyX,
+    int mickeyY)
+{
+    mask = mask;                /* We dont use any of the parameters    */
+    butstate = butstate;
+    x = x;
+    y = y;
+    mickeyX = mickeyX;
+    mickeyY = mickeyY;
+    count++;
+}
+
+int main(void)
+{
+    RMREGS          regs;
+    PM_lockHandle   lh;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    regs.x.ax = 33;     /* Mouse function 33 - Software reset       */
+    PM_int86(0x33,&regs,&regs);
+    if (regs.x.bx == 0) {
+	printf("No mouse installed.\n");
+	exit(1);
+	}
+
+    /* Install our mouse handler and lock handler pages in memory. It is
+     * difficult to get the size of a function in C, but we know our
+     * function is well less than 100 bytes (and an entire 4k page will
+     * need to be locked by the server anyway).
+     */
+    PM_lockCodePages((__codePtr)mouseHandler,100,&lh);
+    PM_lockDataPages((void*)&count,sizeof(count),&lh);
+    if (!PM_setMouseHandler(0xFFFF, mouseHandler)) {
+	printf("Unable to install mouse handler!\n");
+	exit(1);
+	}
+    printf("Mouse handler installed - Hit any key to exit\n");
+    PM_getch();
+
+    PM_restoreMouseHandler();
+    PM_unlockDataPages((void*)&count,sizeof(count),&lh);
+    PM_unlockCodePages((__codePtr)mouseHandler,100,&lh);
+    printf("Mouse handler was called %ld times\n", count);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c b/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c
new file mode 100755
index 0000000..e00be75
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c
@@ -0,0 +1,81 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux/QNX
+*
+* Description:  Program to restore the console state state from a previously
+*               saved state if the program crashed while the console
+*               was in graphics mode.
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+void setVideoMode(int mode)
+{
+    RMREGS r;
+
+    r.x.ax = mode;
+    PM_int86(0x10, &r, &r);
+}
+
+int main(void)
+{
+    PM_HWND hwndConsole;
+    ulong   stateSize;
+    void    *stateBuf;
+    FILE    *f;
+
+    /* Write the saved console state buffer to disk */
+    if ((f = fopen("/etc/pmsave.dat","rb")) == NULL) {
+	printf("Unable to open /etc/pmsave.dat for reading!\n");
+	return -1;
+	}
+    fread(&stateSize,1,sizeof(stateSize),f);
+    if (stateSize != PM_getConsoleStateSize()) {
+	printf("Size mismatch in /etc/pmsave.dat!\n");
+	return -1;
+	}
+    if ((stateBuf = PM_malloc(stateSize)) == NULL) {
+	printf("Unable to allocate console state buffer!\n");
+	return -1;
+	}
+    fread(stateBuf,1,stateSize,f);
+    fclose(f);
+
+    /* Open the console */
+    hwndConsole = PM_openConsole(0,0,0,0,0,true);
+
+    /* Forcibly set 80x25 text mode using the BIOS */
+    setVideoMode(0x3);
+
+    /* Restore the previous console state */
+    PM_restoreConsoleState(stateBuf,0);
+    PM_closeConsole(hwndConsole);
+    PM_free(stateBuf);
+    printf("Console state successfully restored from /etc/pmsave.dat\n");
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c
new file mode 100755
index 0000000..acef922
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c
@@ -0,0 +1,92 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to install a C based
+*               Real Time Clock interrupt handler.
+*
+*               Functions tested:   PM_setRealTimeClockHandler()
+*                                   PM_restoreRealTimeClockHandler()
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+volatile long count = 0;
+
+#pragma off (check_stack)           /* No stack checking under Watcom   */
+
+void PMAPI RTCHandler(void)
+{
+    count++;
+}
+
+int main(void)
+{
+    long            oldCount;
+    PM_lockHandle   lh;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    /* Install our timer handler and lock handler pages in memory. It is
+     * difficult to get the size of a function in C, but we know our
+     * function is well less than 100 bytes (and an entire 4k page will
+     * need to be locked by the server anyway).
+     */
+    PM_lockCodePages((__codePtr)RTCHandler,100,&lh);
+    PM_lockDataPages((void*)&count,sizeof(count),&lh);
+    PM_installBreakHandler();           /* We *DONT* want Ctrl-Breaks! */
+    PM_setRealTimeClockHandler(RTCHandler,128);
+    printf("RealTimeClock interrupt handler installed - Hit ESC to exit\n");
+    oldCount = count;
+    while (1) {
+	if (PM_kbhit() && (PM_getch() == 0x1B))
+	    break;
+	if (count != oldCount) {
+	    printf("Tick, Tock: %ld\n", count);
+	    oldCount = count;
+	    }
+	}
+
+    PM_restoreRealTimeClockHandler();
+    PM_restoreBreakHandler();
+    PM_unlockDataPages((void*)&count,sizeof(count),&lh);
+    PM_unlockCodePages((__codePtr)RTCHandler,100,&lh);
+    printf("RealTimeClock handler was called %ld times\n", count);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/save.c b/board/MAI/bios_emulator/scitech/src/pm/tests/save.c
new file mode 100755
index 0000000..f732456
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/save.c
@@ -0,0 +1,69 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Linux/QNX
+*
+* Description:  Program to save the console state state so that it can
+*               be later restored if the program crashed while the console
+*               was in graphics mode.
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+int main(void)
+{
+    PM_HWND hwndConsole;
+    ulong   stateSize;
+    void    *stateBuf;
+    FILE    *f;
+
+    /* Allocate a buffer to save console state and save the state */
+    hwndConsole = PM_openConsole(0,0,0,0,0,true);
+    stateSize = PM_getConsoleStateSize();
+    if ((stateBuf = PM_malloc(stateSize)) == NULL) {
+	PM_closeConsole(hwndConsole);
+	printf("Unable to allocate console state buffer!\n");
+	return -1;
+	}
+    PM_saveConsoleState(stateBuf,0);
+
+    /* Restore the console state on exit */
+    PM_restoreConsoleState(stateBuf,0);
+    PM_closeConsole(hwndConsole);
+
+    /* Write the saved console state buffer to disk */
+    if ((f = fopen("/etc/pmsave.dat","wb")) == NULL)
+	printf("Unable to open /etc/pmsave/dat for writing!\n");
+    else {
+	fwrite(&stateSize,1,sizeof(stateSize),f);
+	fwrite(stateBuf,1,stateSize,f);
+	fclose(f);
+	printf("Console state successfully saved to /etc/pmsave.dat\n");
+	}
+    PM_free(stateBuf);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c b/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c
new file mode 100755
index 0000000..be275e1
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c
@@ -0,0 +1,253 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to test the PCI library functions.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "pcilib.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+
+/*------------------------- Global Variables ------------------------------*/
+
+static int              NumPCI = -1;
+static PCIDeviceInfo    *PCI;
+static int              *BridgeIndex;
+static int              *DeviceIndex;
+static int              NumBridges;
+static PCIDeviceInfo    *AGPBridge = NULL;
+static int              NumDevices;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+REMARKS:
+Enumerates the PCI bus and dumps the PCI configuration information to the
+log file.
+****************************************************************************/
+static void EnumeratePCI(void)
+{
+    int             i,index;
+    PCIDeviceInfo   *info;
+
+    printf("Displaying enumeration of PCI bus (%d devices, %d display devices)\n",
+	NumPCI, NumDevices);
+    for (index = 0; index < NumDevices; index++)
+	printf("  Display device %d is PCI device %d\n",index,DeviceIndex[index]);
+    printf("\n");
+    printf("Bus Slot Fnc DeviceID  SubSystem Rev Class IRQ Int Cmd\n");
+    for (i = 0; i < NumPCI; i++) {
+	printf("%2d   %2d  %2d  %04X:%04X %04X:%04X %02X  %02X:%02X %02X  %02X  %04X   ",
+	    PCI[i].slot.p.Bus,
+	    PCI[i].slot.p.Device,
+	    PCI[i].slot.p.Function,
+	    PCI[i].VendorID,
+	    PCI[i].DeviceID,
+	    PCI[i].u.type0.SubSystemVendorID,
+	    PCI[i].u.type0.SubSystemID,
+	    PCI[i].RevID,
+	    PCI[i].BaseClass,
+	    PCI[i].SubClass,
+	    PCI[i].u.type0.InterruptLine,
+	    PCI[i].u.type0.InterruptPin,
+	    PCI[i].Command);
+	for (index = 0; index < NumDevices; index++) {
+	    if (DeviceIndex[index] == i)
+		break;
+	    }
+	if (index < NumDevices)
+	    printf("<- %d\n", index);
+	else
+	    printf("\n");
+	}
+    printf("\n");
+    printf("DeviceID  Stat Ifc Cch Lat Hdr BIST\n");
+    for (i = 0; i < NumPCI; i++) {
+	printf("%04X:%04X %04X  %02X  %02X  %02X  %02X  %02X   ",
+	    PCI[i].VendorID,
+	    PCI[i].DeviceID,
+	    PCI[i].Status,
+	    PCI[i].Interface,
+	    PCI[i].CacheLineSize,
+	    PCI[i].LatencyTimer,
+	    PCI[i].HeaderType,
+	    PCI[i].BIST);
+	for (index = 0; index < NumDevices; index++) {
+	    if (DeviceIndex[index] == i)
+		break;
+	    }
+	if (index < NumDevices)
+	    printf("<- %d\n", index);
+	else
+	    printf("\n");
+	}
+    printf("\n");
+    printf("DeviceID  Base10h  Base14h  Base18h  Base1Ch  Base20h  Base24h  ROMBase\n");
+    for (i = 0; i < NumPCI; i++) {
+	printf("%04X:%04X %08lX %08lX %08lX %08lX %08lX %08lX %08lX ",
+	    PCI[i].VendorID,
+	    PCI[i].DeviceID,
+	    PCI[i].u.type0.BaseAddress10,
+	    PCI[i].u.type0.BaseAddress14,
+	    PCI[i].u.type0.BaseAddress18,
+	    PCI[i].u.type0.BaseAddress1C,
+	    PCI[i].u.type0.BaseAddress20,
+	    PCI[i].u.type0.BaseAddress24,
+	    PCI[i].u.type0.ROMBaseAddress);
+	for (index = 0; index < NumDevices; index++) {
+	    if (DeviceIndex[index] == i)
+		break;
+	    }
+	if (index < NumDevices)
+	    printf("<- %d\n", index);
+	else
+	    printf("\n");
+	}
+    printf("\n");
+    printf("DeviceID  BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n");
+    for (i = 0; i < NumPCI; i++) {
+	printf("%04X:%04X %08lX %08lX %08lX %08lX %08lX %08lX %08lX ",
+	    PCI[i].VendorID,
+	    PCI[i].DeviceID,
+	    PCI[i].u.type0.BaseAddress10Len,
+	    PCI[i].u.type0.BaseAddress14Len,
+	    PCI[i].u.type0.BaseAddress18Len,
+	    PCI[i].u.type0.BaseAddress1CLen,
+	    PCI[i].u.type0.BaseAddress20Len,
+	    PCI[i].u.type0.BaseAddress24Len,
+	    PCI[i].u.type0.ROMBaseAddressLen);
+	for (index = 0; index < NumDevices; index++) {
+	    if (DeviceIndex[index] == i)
+		break;
+	    }
+	if (index < NumDevices)
+	    printf("<- %d\n", index);
+	else
+	    printf("\n");
+	}
+    printf("\n");
+    printf("Displaying enumeration of %d bridge devices\n",NumBridges);
+    printf("\n");
+    printf("DeviceID  P# S# B# IOB  IOL  MemBase  MemLimit PreBase  PreLimit Ctrl\n");
+    for (i = 0; i < NumBridges; i++) {
+	info = (PCIDeviceInfo*)&PCI[BridgeIndex[i]];
+	printf("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n",
+	    info->VendorID,
+	    info->DeviceID,
+	    info->u.type1.PrimaryBusNumber,
+	    info->u.type1.SecondayBusNumber,
+	    info->u.type1.SubordinateBusNumber,
+	    ((u16)info->u.type1.IOBase << 8) & 0xF000,
+	    info->u.type1.IOLimit ?
+		((u16)info->u.type1.IOLimit << 8) | 0xFFF : 0,
+	    ((u32)info->u.type1.MemoryBase << 16) & 0xFFF00000,
+	    info->u.type1.MemoryLimit ?
+		((u32)info->u.type1.MemoryLimit << 16) | 0xFFFFF : 0,
+	    ((u32)info->u.type1.PrefetchableMemoryBase << 16) & 0xFFF00000,
+	    info->u.type1.PrefetchableMemoryLimit ?
+		((u32)info->u.type1.PrefetchableMemoryLimit << 16) | 0xFFFFF : 0,
+	    info->u.type1.BridgeControl);
+	}
+    printf("\n");
+}
+
+/****************************************************************************
+RETURNS:
+Number of display devices found.
+
+REMARKS:
+This function enumerates the number of available display devices on the
+PCI bus, and returns the number found.
+****************************************************************************/
+static int PCI_enumerateDevices(void)
+{
+    int             i,j;
+    PCIDeviceInfo   *info;
+
+    /* If this is the first time we have been called, enumerate all */
+    /* devices on the PCI bus. */
+    if (NumPCI == -1) {
+	if ((NumPCI = PCI_getNumDevices()) == 0)
+	    return -1;
+	PCI = malloc(NumPCI * sizeof(PCI[0]));
+	BridgeIndex = malloc(NumPCI * sizeof(BridgeIndex[0]));
+	DeviceIndex = malloc(NumPCI * sizeof(DeviceIndex[0]));
+	if (!PCI || !BridgeIndex || !DeviceIndex)
+	    return -1;
+	for (i = 0; i < NumPCI; i++)
+	    PCI[i].dwSize = sizeof(PCI[i]);
+	if (PCI_enumerate(PCI) == 0)
+	    return -1;
+
+	/* Build a list of all PCI bridge devices */
+	for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) {
+	    if (PCI[i].BaseClass == PCI_BRIDGE_CLASS)
+		BridgeIndex[NumBridges++] = i;
+	    }
+
+	/* Now build a list of all display class devices */
+	for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) {
+	    if (PCI_IS_DISPLAY_CLASS(&PCI[i])) {
+		if ((PCI[i].Command & 0x3) == 0x3)
+		    DeviceIndex[0] = i;
+		else
+		    DeviceIndex[NumDevices++] = i;
+		if (PCI[i].slot.p.Bus != 0) {
+		    /* This device is on a different bus than the primary */
+		    /* PCI bus, so it is probably an AGP device. Find the */
+		    /* AGP bus device that controls that bus so we can */
+		    /* control it. */
+		    for (j = 0; j < NumBridges; j++) {
+			info = (PCIDeviceInfo*)&PCI[BridgeIndex[j]];
+			if (info->u.type1.SecondayBusNumber == PCI[i].slot.p.Bus) {
+			    AGPBridge = info;
+			    break;
+			    }
+			}
+		    }
+		}
+	    }
+
+	/* Enumerate all PCI and bridge devices to standard output */
+	EnumeratePCI();
+	}
+    return NumDevices;
+}
+
+int main(void)
+{
+    /* Enumerate all PCI devices */
+    PM_init();
+    if (PCI_enumerateDevices() < 1) {
+	printf("No PCI display devices found!\n");
+	return -1;
+	}
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c b/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c
new file mode 100755
index 0000000..378725e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c
@@ -0,0 +1,94 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to install a C based
+*               timer interrupt handler.
+*
+*               Functions tested:   PM_setTimerHandler()
+*                                   PM_chainPrevTimer();
+*                                   PM_restoreTimerHandler()
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+volatile long count = 0;
+
+#pragma off (check_stack)           /* No stack checking under Watcom   */
+
+void PMAPI timerHandler(void)
+{
+    PM_chainPrevTimer();        /* Chain to previous handler */
+    count++;
+}
+
+int main(void)
+{
+    long            oldCount;
+    PM_lockHandle   lh;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    /* Install our timer handler and lock handler pages in memory. It is
+     * difficult to get the size of a function in C, but we know our
+     * function is well less than 100 bytes (and an entire 4k page will
+     * need to be locked by the server anyway).
+     */
+    PM_lockCodePages((__codePtr)timerHandler,100,&lh);
+    PM_lockDataPages((void*)&count,sizeof(count),&lh);
+    PM_installBreakHandler();           /* We *DONT* want Ctrl-Breaks! */
+    PM_setTimerHandler(timerHandler);
+    printf("Timer interrupt handler installed - Hit ESC to exit\n");
+    oldCount = count;
+    while (1) {
+	if (PM_kbhit() && (PM_getch() == 0x1B))
+	    break;
+	if (count != oldCount) {
+	    printf("Tick, Tock: %ld\n", count);
+	    oldCount = count;
+	    }
+	}
+
+    PM_restoreTimerHandler();
+    PM_restoreBreakHandler();
+    PM_unlockDataPages((void*)&count,sizeof(count),&lh);
+    PM_unlockCodePages((__codePtr)timerHandler,100,&lh);
+    printf("Timer handler was called %ld times\n", count);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c
new file mode 100755
index 0000000..7fa77b7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c
@@ -0,0 +1,87 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Test program for the Zen Timer Library.
+*
+****************************************************************************/
+
+#include <stdio.h>
+#include "pmapi.h"
+#include "ztimer.h"
+
+#define DELAY_SECS  10
+
+/*-------------------------- Implementation -------------------------------*/
+
+/* The following routine takes a long count in microseconds and outputs
+ * a string representing the count in seconds. It could be modified to
+ * return a pointer to a static string representing the count rather
+ * than printing it out.
+ */
+
+void ReportTime(ulong count)
+{
+    ulong   secs;
+
+    secs = count / 1000000L;
+    count = count - secs * 1000000L;
+    printf("Time taken: %lu.%06lu seconds\n",secs,count);
+}
+
+int     i,j;                                /* NON register variables! */
+
+int main(void)
+{
+#ifdef  LONG_TEST
+    ulong   start,finish;
+#endif
+
+    printf("Processor type: %d %ld MHz\n", CPU_getProcessorType(), CPU_getProcessorSpeed(true));
+
+    ZTimerInit();
+
+    /* Test the long period Zen Timer (we don't check for overflow coz
+     * it would take tooooo long!)
+     */
+
+    LZTimerOn();
+    for (j = 0; j < 10; j++)
+	for (i = 0; i < 20000; i++)
+	    i = i;
+    LZTimerOff();
+    ReportTime(LZTimerCount());
+
+    /* Test the ultra long period Zen Timer */
+#ifdef LONG_TEST
+    start = ULZReadTime();
+    delay(DELAY_SECS * 1000);
+    finish = ULZReadTime();
+    printf("Delay of %d secs took %d 1/10ths of a second\n",
+	DELAY_SECS,ULZElapsedTime(start,finish));
+#endif
+
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp b/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp
new file mode 100755
index 0000000..1258a4b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp
@@ -0,0 +1,107 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     C++ 3.0
+* Environment:  Any
+*
+* Description:  Test program for the Zen Timer Library C++ interface.
+*
+****************************************************************************/
+
+#include <iostream.h>
+#include "pmapi.h"
+#include "ztimer.h"
+
+/*-------------------------- Implementation -------------------------------*/
+
+int     i,j,k;                              /* NON register variables! */
+
+void dummy() {}
+
+int main(void)
+{
+    LZTimer     ltimer;
+    ULZTimer    ultimer;
+
+    ZTimerInit();
+
+    /* Test the long period Zen Timer (we don't check for overflow coz
+     * it would take tooooo long!)
+     */
+
+    cout << endl;
+    ultimer.restart();
+    ltimer.start();
+    for (j = 0; j < 10; j++)
+        for (i = 0; i < 20000; i++)
+            dummy();
+    ltimer.stop();
+    ultimer.stop();
+    cout << "LCount:  " << ltimer.count() << endl;
+    cout << "Time:    " << ltimer << " secs\n";
+    cout << "ULCount: " << ultimer.count() << endl;
+    cout << "ULTime:  " << ultimer << " secs\n";
+
+    cout << endl << "Timing ... \n";
+    ultimer.restart();
+    ltimer.restart();
+    for (j = 0; j < 200; j++)
+        for (i = 0; i < 20000; i++)
+            dummy();
+    ltimer.stop();
+    ultimer.stop();
+    cout << "LCount:  " << ltimer.count() << endl;
+    cout << "Time:    " << ltimer << " secs\n";
+    cout << "ULCount: " << ultimer.count() << endl;
+    cout << "ULTime:  " << ultimer << " secs\n";
+
+    /* Test the lap function of the long period Zen Timer */
+
+    cout << endl << "Timing ... \n";
+    ultimer.restart();
+    ltimer.restart();
+    for (j = 0; j < 20; j++) {
+        for (k = 0; k < 10; k++)
+            for (i = 0; i < 20000; i++)
+                dummy();
+        cout << "lap: " << ltimer.lap() << endl;
+        }
+    ltimer.stop();
+    ultimer.stop();
+    cout << "LCount:  " << ltimer.count() << endl;
+    cout << "Time:    " << ltimer << " secs\n";
+    cout << "ULCount: " << ultimer.count() << endl;
+    cout << "ULTime:  " << ultimer << " secs\n";
+
+#ifdef  LONG_TEST
+    /* Test the ultra long period Zen Timer */
+
+    ultimer.start();
+    delay(DELAY_SECS * 1000);
+    ultimer.stop();
+    cout << "Delay of " << DELAY_SECS << " secs took " << ultimer.count()
+         << " 1/10ths of a second\n";
+    cout << "Time: " << ultimer << " secs\n";
+#endif
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c
new file mode 100755
index 0000000..f0c7bd6
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c
@@ -0,0 +1,311 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Simple test program to test the write combine functions.
+*
+*               Note that this program should never be used in a production
+*               environment, because write combining needs to be handled
+*               with more intimate knowledge of the display hardware than
+*               you can obtain by simply examining the PCI configuration
+*               space.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "pcilib.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+
+/*------------------------- Global Variables ------------------------------*/
+
+static int              NumPCI = -1;
+static PCIDeviceInfo    *PCI;
+static int              *BridgeIndex;
+static int              *DeviceIndex;
+static int              NumBridges;
+static PCIDeviceInfo    *AGPBridge = NULL;
+static int              NumDevices;
+
+/*-------------------------- Implementation -------------------------------*/
+
+/****************************************************************************
+RETURNS:
+Number of display devices found.
+
+REMARKS:
+This function enumerates the number of available display devices on the
+PCI bus, and returns the number found.
+****************************************************************************/
+static int PCI_enumerateDevices(void)
+{
+    int             i,j;
+    PCIDeviceInfo   *info;
+
+    /* If this is the first time we have been called, enumerate all */
+    /* devices on the PCI bus. */
+    if (NumPCI == -1) {
+	if ((NumPCI = PCI_getNumDevices()) == 0)
+	    return -1;
+	PCI = malloc(NumPCI * sizeof(PCI[0]));
+	BridgeIndex = malloc(NumPCI * sizeof(BridgeIndex[0]));
+	DeviceIndex = malloc(NumPCI * sizeof(DeviceIndex[0]));
+	if (!PCI || !BridgeIndex || !DeviceIndex)
+	    return -1;
+	for (i = 0; i < NumPCI; i++)
+	    PCI[i].dwSize = sizeof(PCI[i]);
+	if (PCI_enumerate(PCI) == 0)
+	    return -1;
+
+	/* Build a list of all PCI bridge devices */
+	for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) {
+	    if (PCI[i].BaseClass == PCI_BRIDGE_CLASS)
+		BridgeIndex[NumBridges++] = i;
+	    }
+
+	/* Now build a list of all display class devices */
+	for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) {
+	    if (PCI_IS_DISPLAY_CLASS(&PCI[i])) {
+		if ((PCI[i].Command & 0x3) == 0x3)
+		    DeviceIndex[0] = i;
+		else
+		    DeviceIndex[NumDevices++] = i;
+		if (PCI[i].slot.p.Bus != 0) {
+		    /* This device is on a different bus than the primary */
+		    /* PCI bus, so it is probably an AGP device. Find the */
+		    /* AGP bus device that controls that bus so we can */
+		    /* control it. */
+		    for (j = 0; j < NumBridges; j++) {
+			info = (PCIDeviceInfo*)&PCI[BridgeIndex[j]];
+			if (info->u.type1.SecondayBusNumber == PCI[i].slot.p.Bus) {
+			    AGPBridge = info;
+			    break;
+			    }
+			}
+		    }
+		}
+	    }
+	}
+    return NumDevices;
+}
+
+/****************************************************************************
+REMARKS:
+Enumerates useful information about attached display devices.
+****************************************************************************/
+static void ShowDisplayDevices(void)
+{
+    int i,index;
+
+    printf("Displaying enumeration of %d PCI display devices\n", NumDevices);
+    printf("\n");
+    printf("DeviceID  SubSystem  Base10h  (length  )  Base14h  (length  )\n");
+    for (index = 0; index < NumDevices; index++) {
+	i = DeviceIndex[index];
+	printf("%04X:%04X %04X:%04X  %08lX (%6ld KB) %08lX (%6ld KB)\n",
+	    PCI[i].VendorID,
+	    PCI[i].DeviceID,
+	    PCI[i].u.type0.SubSystemVendorID,
+	    PCI[i].u.type0.SubSystemID,
+	    PCI[i].u.type0.BaseAddress10,
+	    PCI[i].u.type0.BaseAddress10Len / 1024,
+	    PCI[i].u.type0.BaseAddress14,
+	    PCI[i].u.type0.BaseAddress14Len / 1024);
+	}
+    printf("\n");
+}
+
+/****************************************************************************
+REMARKS:
+Dumps the value for a write combine region to the display.
+****************************************************************************/
+static char *DecodeWCType(
+    uint type)
+{
+    static char *names[] = {
+	"UNCACHABLE",
+	"WRCOMB",
+	"UNKNOWN",
+	"UNKNOWN",
+	"WRTHROUGH",
+	"WRPROT",
+	"WRBACK",
+	};
+    if (type <= PM_MTRR_MAX)
+	return names[type];
+    return "UNKNOWN";
+}
+
+/****************************************************************************
+REMARKS:
+Dumps the value for a write combine region to the display.
+****************************************************************************/
+static void PMAPI EnumWriteCombine(
+    ulong base,
+    ulong length,
+    uint type)
+{
+    printf("%08lX %-10ld %s\n", base, length / 1024, DecodeWCType(type));
+}
+
+/****************************************************************************
+PARAMETERS:
+err - Error to log
+
+REMARKS:
+Function to log an error message if the MTRR write combining attempt failed.
+****************************************************************************/
+static void LogMTRRError(
+    int err)
+{
+    if (err == PM_MTRR_ERR_OK)
+	return;
+    switch (err) {
+	case PM_MTRR_NOT_SUPPORTED:
+	    printf("Failed: MTRR is not supported by host CPU\n");
+	    break;
+	case PM_MTRR_ERR_PARAMS:
+	    printf("Failed: Invalid parameters passed to PM_enableWriteCombined!\n");
+	    break;
+	case PM_MTRR_ERR_NOT_4KB_ALIGNED:
+	    printf("Failed: Address is not 4Kb aligned!\n");
+	    break;
+	case PM_MTRR_ERR_BELOW_1MB:
+	    printf("Failed: Addresses below 1Mb cannot be write combined!\n");
+	    break;
+	case PM_MTRR_ERR_NOT_ALIGNED:
+	    printf("Failed: Address is not correctly aligned for processor!\n");
+	    break;
+	case PM_MTRR_ERR_OVERLAP:
+	    printf("Failed: Address overlaps an existing region!\n");
+	    break;
+	case PM_MTRR_ERR_TYPE_MISMATCH:
+	    printf("Failed: Adress is contained with existing region, but type is different!\n");
+	    break;
+	case PM_MTRR_ERR_NONE_FREE:
+	    printf("Failed: Out of MTRR registers!\n");
+	    break;
+	case PM_MTRR_ERR_NOWRCOMB:
+	    printf("Failed: This processor does not support write combining!\n");
+	    break;
+	case PM_MTRR_ERR_NO_OS_SUPPORT:
+	    printf("Failed: MTRR is not supported by host OS\n");
+	    break;
+	default:
+	    printf("Failed: UNKNOWN ERROR!\n");
+	    break;
+	}
+    exit(-1);
+}
+
+/****************************************************************************
+REMARKS:
+Shows all write combine regions.
+****************************************************************************/
+static void ShowWriteCombine(void)
+{
+    printf("Base     Length(KB) Type\n");
+    LogMTRRError(PM_enumWriteCombine(EnumWriteCombine));
+    printf("\n");
+}
+
+/****************************************************************************
+REMARKS:
+Dumps the value for a write combine region to the display.
+****************************************************************************/
+static void EnableWriteCombine(void)
+{
+    int i,index;
+
+    for (index = 0; index < NumDevices; index++) {
+	i = DeviceIndex[index];
+	if (PCI[i].u.type0.BaseAddress10 & 0x8) {
+	    LogMTRRError(PM_enableWriteCombine(
+		PCI[i].u.type0.BaseAddress10 & 0xFFFFFFF0,
+		PCI[i].u.type0.BaseAddress10Len,
+		PM_MTRR_WRCOMB));
+	    }
+	if (PCI[i].u.type0.BaseAddress14 & 0x8) {
+	    LogMTRRError(PM_enableWriteCombine(
+		PCI[i].u.type0.BaseAddress14 & 0xFFFFFFF0,
+		PCI[i].u.type0.BaseAddress14Len,
+		PM_MTRR_WRCOMB));
+	    }
+	}
+    printf("\n");
+    ShowDisplayDevices();
+    ShowWriteCombine();
+}
+
+/****************************************************************************
+REMARKS:
+Dumps the value for a write combine region to the display.
+****************************************************************************/
+static void DisableWriteCombine(void)
+{
+    int i,index;
+
+    for (index = 0; index < NumDevices; index++) {
+	i = DeviceIndex[index];
+	if (PCI[i].u.type0.BaseAddress10 & 0x8) {
+	    LogMTRRError(PM_enableWriteCombine(
+		PCI[i].u.type0.BaseAddress10 & 0xFFFFFFF0,
+		PCI[i].u.type0.BaseAddress10Len,
+		PM_MTRR_UNCACHABLE));
+	    }
+	if (PCI[i].u.type0.BaseAddress14 & 0x8) {
+	    LogMTRRError(PM_enableWriteCombine(
+		PCI[i].u.type0.BaseAddress14 & 0xFFFFFFF0,
+		PCI[i].u.type0.BaseAddress14Len,
+		PM_MTRR_UNCACHABLE));
+	    }
+	}
+    printf("\n");
+    ShowDisplayDevices();
+    ShowWriteCombine();
+}
+
+int main(int argc,char *argv[])
+{
+    PM_init();
+    if (PCI_enumerateDevices() < 1) {
+	printf("No PCI display devices found!\n");
+	return -1;
+	}
+    if (argc < 2) {
+	printf("usage: uswc [-show -on -off]\n\n");
+	ShowDisplayDevices();
+	return -1;
+	}
+    if (stricmp(argv[1],"-show") == 0)
+	ShowWriteCombine();
+    else if (stricmp(argv[1],"-on") == 0)
+	EnableWriteCombine();
+    else if (stricmp(argv[1],"-off") == 0)
+	DisableWriteCombine();
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c b/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c
new file mode 100755
index 0000000..b7e3bb7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c
@@ -0,0 +1,78 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Filename:     $Workfile$
+* Version:      $Revision: 1.1 $
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to test the VFlat virtual framebuffer functions.
+*
+*               Functions tested:   VF_available()
+*                                   VF_init()
+*                                   VF_exit()
+*
+* $Date: 2002/10/02 15:35:21 $ $Author: hfrieden $
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+uchar code[] = {
+    0xC3,                   /* ret          */
+    };
+
+int main(void)
+{
+    void    *vfBuffer;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    if (!VF_available()) {
+	printf("Virtual Linear Framebuffer not available.\n");
+	exit(1);
+	}
+
+    vfBuffer = VF_init(0xA0000,64,sizeof(code),code);
+    if (!vfBuffer) {
+	printf("Failure to initialise Virtual Linear Framebuffer!\n");
+	exit(1);
+	}
+    VF_exit();
+    printf("Virtual Linear Framebuffer set up successfully!\n");
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/video.c b/board/MAI/bios_emulator/scitech/src/pm/tests/video.c
new file mode 100755
index 0000000..92adcdd
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/tests/video.c
@@ -0,0 +1,199 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  any
+*
+* Description:  Test program to check the ability to generate real mode
+*               interrupts and to be able to obtain direct access to the
+*               video memory from protected mode. Compile and link with
+*               the appropriate command line for your DOS extender.
+*
+*               Functions tested:   PM_getBIOSSelector()
+*                                   PM_mapPhysicalAddr()
+*                                   PM_int86()
+*
+****************************************************************************/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pmapi.h"
+
+uchar   *bios;          /* Pointer to BIOS data area        */
+uchar   *videoPtr;      /* Pointer to VGA framebuffer       */
+void    *stateBuf;      /* Console state save buffer        */
+
+/* Routine to return the current video mode number */
+
+int getVideoMode(void)
+{
+    return PM_getByte(bios+0x49);
+}
+
+/* Routine to set a specified video mode */
+
+void setVideoMode(int mode)
+{
+    RMREGS r;
+
+    r.x.ax = mode;
+    PM_int86(0x10, &r, &r);
+}
+
+/* Routine to clear a rectangular region on the display by calling the
+ * video BIOS.
+ */
+
+void clearScreen(int startx, int starty, int endx, int endy, unsigned char attr)
+{
+    RMREGS r;
+
+    r.x.ax = 0x0600;
+    r.h.bh = attr;
+    r.h.cl = startx;
+    r.h.ch = starty;
+    r.h.dl = endx;
+    r.h.dh = endy;
+    PM_int86(0x10, &r, &r);
+}
+
+/* Routine to fill a rectangular region on the display using direct
+ * video writes.
+ */
+
+#define SCREEN(x,y) (videoPtr + ((y) * 160) + ((x) << 1))
+
+void fill(int startx, int starty, int endx, int endy, unsigned char c,
+    unsigned char attr)
+{
+    unsigned char   *v;
+    int             x,y;
+
+    for (y = starty; y <= endy; y++) {
+	v = SCREEN(startx,y);
+	for (x = startx; x <= endx; x++) {
+	    *v++ = c;
+	    *v++ = attr;
+	    }
+	}
+}
+
+/* Routine to display a single character using direct video writes */
+
+void writeChar(int x, int y, unsigned char c, unsigned char attr)
+{
+    unsigned char *v = SCREEN(x,y);
+    *v++ = c;
+    *v = attr;
+}
+
+/* Routine to draw a border around a rectangular area using direct video
+ * writes.
+ */
+
+static unsigned char border_chars[] = {
+    186, 205, 201, 187, 200, 188        /* double box chars */
+    };
+
+void border(int startx, int starty, int endx, int endy, unsigned char attr)
+{
+    unsigned char   *v;
+    unsigned char   *b;
+    int             i;
+
+    b = border_chars;
+
+    for (i = starty+1; i < endy; i++) {
+	writeChar(startx, i, *b, attr);
+	writeChar(endx, i, *b, attr);
+	}
+    b++;
+    for (i = startx+1, v = SCREEN(startx+1, starty); i < endx; i++) {
+	*v++ = *b;
+	*v++ = attr;
+	}
+    for (i = startx+1, v = SCREEN(startx+1, endy); i < endx; i++) {
+	*v++ = *b;
+	*v++ = attr;
+	}
+    b++;
+    writeChar(startx, starty, *b++, attr);
+    writeChar(endx, starty, *b++, attr);
+    writeChar(startx, endy, *b++, attr);
+    writeChar(endx, endy, *b++, attr);
+}
+
+int main(void)
+{
+    int     orgMode;
+    PM_HWND hwndConsole;
+
+    printf("Program running in ");
+    switch (PM_getModeType()) {
+	case PM_realMode:
+	    printf("real mode.\n\n");
+	    break;
+	case PM_286:
+	    printf("16 bit protected mode.\n\n");
+	    break;
+	case PM_386:
+	    printf("32 bit protected mode.\n\n");
+	    break;
+	}
+
+    hwndConsole = PM_openConsole(0,0,0,0,0,true);
+    printf("Hit any key to start 80x25 text mode and perform some direct video output.\n");
+    PM_getch();
+
+    /* Allocate a buffer to save console state and save the state */
+    if ((stateBuf = PM_malloc(PM_getConsoleStateSize())) == NULL) {
+	printf("Unable to allocate console state buffer!\n");
+	exit(1);
+	}
+    PM_saveConsoleState(stateBuf,0);
+    bios = PM_getBIOSPointer();
+    orgMode = getVideoMode();
+    setVideoMode(0x3);
+    if ((videoPtr = PM_mapPhysicalAddr(0xB8000,0xFFFF,true)) == NULL) {
+	printf("Unable to obtain pointer to framebuffer!\n");
+	exit(1);
+	}
+
+    /* Draw some text on the screen */
+    fill(0, 0, 79, 24, 176, 0x1E);
+    border(0, 0, 79, 24, 0x1F);
+    PM_getch();
+    clearScreen(0, 0, 79, 24, 0x7);
+
+    /* Restore the console state on exit */
+    PM_restoreConsoleState(stateBuf,0);
+    PM_free(stateBuf);
+    PM_closeConsole(hwndConsole);
+
+    /* Display useful status information */
+    printf("\n");
+    printf("Original Video Mode = %02X\n", orgMode);
+    printf("BIOS Pointer = %08X\n", (int)bios);
+    printf("Video Memory = %08X\n", (int)videoPtr);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c
new file mode 100755
index 0000000..3460b72
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c
@@ -0,0 +1,66 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit OS/2 VDD
+*
+* Description:  VDD specific code for the CPU detection module.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Do nothing for VDD's
+****************************************************************************/
+#define SetMaxThreadPriority()      0
+
+/****************************************************************************
+REMARKS:
+Do nothing for VDD's
+****************************************************************************/
+#define RestoreThreadPriority(i)    (void)(i)
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    freq->low  = 100000;
+    freq->high = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)                              \
+{                                                  \
+    ULONG   count;                                 \
+    count = VDHQuerySysValue(0, VDHGSV_MSECSBOOT); \
+    (t)->low  = count * 100;                       \
+    (t)->high = 0;                                 \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c
new file mode 100755
index 0000000..93742de
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c
@@ -0,0 +1,359 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit OS/2 VDD
+*
+* Description:  C library compatible I/O functions for use within a VDD.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "vddfile.h"
+
+/*------------------------ Main Code Implementation -----------------------*/
+
+#define EOF -1
+
+/* NB: none of the file VDHs are available during the DOS session          */
+/* initialzation context!                                                  */
+
+/* Macros for Open/Close APIs to allow using this module in both VDDs and  */
+/* normal OS/2 applications. Unfortunately VDHRead/Write/Seek don't map to */
+/* their Dos* counterparts so cleanly.                                     */
+#ifdef __OS2_VDD__
+#define _OS2Open    VDHOpen
+#define _OS2Close   VDHClose
+#else
+#define _OS2Open    DosOpen
+#define _OS2Close   DosClose
+#endif
+
+/****************************************************************************
+REMARKS:
+VDD implementation of the ANSI C fopen function.
+****************************************************************************/
+FILE * fopen(
+    const char *filename,
+    const char *mode)
+{
+    FILE    *f = PM_malloc(sizeof(FILE));
+    long    oldpos;
+    ULONG   rc, ulAction;
+    ULONG   omode, oflags;
+
+    if (f != NULL) {
+	f->offset = 0;
+	f->text = (mode[1] == 't' || mode[2] == 't');
+	f->writemode = (mode[0] == 'w') || (mode[0] == 'a');
+	f->unputc = EOF;
+	f->endp = f->buf + sizeof(f->buf);
+	f->curp = f->startp = f->buf;
+
+	if (mode[0] == 'r') {
+	    #ifdef __OS2_VDD__
+	    omode  = VDHOPEN_ACCESS_READONLY | VDHOPEN_SHARE_DENYNONE;
+	    oflags = VDHOPEN_ACTION_OPEN_IF_EXISTS | VDHOPEN_ACTION_FAIL_IF_NEW;
+	    #else
+	    omode  = OPEN_ACCESS_READONLY | OPEN_SHARE_DENYNONE;
+	    oflags = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_FAIL_IF_NEW;
+	    #endif
+	    }
+	else if (mode[0] == 'w') {
+	    #ifdef __OS2_VDD__
+	    omode  = VDHOPEN_ACCESS_WRITEONLY | VDHOPEN_SHARE_DENYWRITE;
+	    oflags = VDHOPEN_ACTION_REPLACE_IF_EXISTS | VDHOPEN_ACTION_CREATE_IF_NEW;
+	    #else
+	    omode  = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_DENYWRITE;
+	    oflags = OPEN_ACTION_REPLACE_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW;
+	    #endif
+	    }
+	else {
+	    #ifdef __OS2_VDD__
+	    omode  = VDHOPEN_ACCESS_READWRITE | VDHOPEN_SHARE_DENYWRITE;
+	    oflags = VDHOPEN_ACTION_OPEN_IF_EXISTS | VDHOPEN_ACTION_CREATE_IF_NEW;
+	    #else
+	    omode  = OPEN_ACCESS_READWRITE | OPEN_SHARE_DENYWRITE;
+	    oflags = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW;
+	    #endif
+	    }
+	rc = _OS2Open((PSZ)filename, (PHFILE)&f->handle, &ulAction, 0, VDHOPEN_FILE_NORMAL, oflags, omode, NULL);
+	if (rc != 0) {
+	    PM_free(f);
+	    return NULL;
+	    }
+
+	#ifdef __OS2_VDD__
+	f->filesize = VDHSeek((HFILE)f->handle, 0, VDHSK_END_OF_FILE);
+	#else
+	rc = DosSetFilePtr((HFILE)f->handle, 0, FILE_END, &f->filesize);
+	#endif
+
+	if (mode[0] == 'a')
+	    fseek(f,0,2);
+    }
+    return f;
+}
+
+/****************************************************************************
+REMARKS:
+VDD implementation of the ANSI C fread function. Note that unlike Windows VxDs,
+OS/2 VDDs are not limited to 64K reads or writes.
+****************************************************************************/
+size_t fread(
+    void *ptr,
+    size_t size,
+    size_t n,
+    FILE *f)
+{
+    char    *buf = ptr;
+    int     bytes,readbytes,totalbytes = 0;
+
+    /* First copy any data already read into our buffer */
+    if ((bytes = (f->curp - f->startp)) > 0) {
+	memcpy(buf,f->curp,bytes);
+	f->startp = f->curp = f->buf;
+	buf += bytes;
+	totalbytes += bytes;
+	bytes = (size * n) - bytes;
+	}
+    else
+	bytes = size * n;
+    if (bytes) {
+	#ifdef __OS2_VDD__
+	readbytes = VDHRead((HFILE)f->handle, buf, bytes);
+	#else
+	DosRead((HFILE)f->handle, buf, bytes, &readbytes);
+	#endif
+	totalbytes += readbytes;
+	f->offset += readbytes;
+	}
+    return totalbytes / size;
+}
+
+/****************************************************************************
+REMARKS:
+VDD implementation of the ANSI C fwrite function.
+****************************************************************************/
+size_t fwrite(
+    void *ptr,
+    size_t size,
+    size_t n,
+    FILE *f)
+{
+    char        *buf = ptr;
+    int         bytes,writtenbytes,totalbytes = 0;
+
+    /* Flush anything already in the buffer */
+    if (!f->writemode)
+	return 0;
+    fflush(f);
+    bytes = size * n;
+    #ifdef __OS2_VDD__
+    writtenbytes = VDHWrite((HFILE)f->handle, buf, bytes);
+    #else
+    DosWrite((HFILE)f->handle, buf, bytes, &writtenbytes);
+    #endif
+    totalbytes += writtenbytes;
+    f->offset += writtenbytes;
+    if (f->offset > f->filesize)
+	f->filesize = f->offset;
+    return totalbytes / size;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fflush function.
+****************************************************************************/
+int fflush(
+    FILE *f)
+{
+    ULONG     bytes;
+
+    /* First copy any data already written into our buffer */
+    if (f->writemode && (bytes = (f->curp - f->startp)) > 0) {
+	#ifdef __OS2_VDD__
+	bytes = VDHWrite((HFILE)f->handle, f->startp, bytes);
+	#else
+	DosWrite((HFILE)f->handle, f->startp, bytes, &bytes);
+	#endif
+	f->offset += bytes;
+	if (f->offset > f->filesize)
+	    f->filesize = f->offset;
+	f->startp = f->curp = f->buf;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+VDD implementation of the ANSI C fseek function.
+****************************************************************************/
+int fseek(
+    FILE *f,
+    long int offset,
+    int whence)
+{
+    fflush(f);
+
+    if (whence == 0)
+	f->offset = offset;
+    else if (whence == 1)
+	f->offset += offset;
+    else if (whence == 2)
+	f->offset = f->filesize + offset;
+
+    #ifdef __OS2_VDD__
+    VDHSeek((HFILE)f->handle, f->offset, VDHSK_ABSOLUTE);
+    #else
+    DosSetFilePtr((HFILE)f->handle, f->offset, FILE_BEGIN, NULL);
+    #endif
+
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+VDD implementation of the ANSI C ftell function.
+****************************************************************************/
+long ftell(
+    FILE *f)
+{
+    long    offset;
+
+    offset = (f->curp - f->startp);
+    offset += f->offset;
+    return offset;
+}
+
+/****************************************************************************
+REMARKS:
+VDD implementation of the ANSI C feof function.
+****************************************************************************/
+int feof(
+    FILE *f)
+{
+    return (f->offset == f->filesize);
+}
+
+/****************************************************************************
+REMARKS:
+Read a single character from the input file buffer, including translation
+of the character in text transation modes.
+****************************************************************************/
+static int __getc(
+    FILE *f)
+{
+    int c;
+
+    if (f->unputc != EOF) {
+	c = f->unputc;
+	f->unputc = EOF;
+	}
+    else {
+	if (f->startp == f->curp) {
+	    int bytes = fread(f->buf,1,sizeof(f->buf),f);
+	    if (bytes == 0)
+		return EOF;
+	    f->curp = f->startp + bytes;
+	    }
+	c = *f->startp++;
+	if (f->text && c == '\r') {
+	    int nc = __getc(f);
+	    if (nc != '\n')
+		f->unputc = nc;
+	    }
+	}
+    return c;
+}
+
+/****************************************************************************
+REMARKS:
+Write a single character from to input buffer, including translation of the
+character in text transation modes.
+****************************************************************************/
+static int __putc(int c,FILE *f)
+{
+    int count = 1;
+    if (f->text && c == '\n') {
+	__putc('\r',f);
+	count = 2;
+	}
+    if (f->curp == f->endp)
+	fflush(f);
+    *f->curp++ = c;
+    return count;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fgets function.
+****************************************************************************/
+char *fgets(
+    char *s,
+    int n,
+    FILE *f)
+{
+    int c = 0;
+    char *cs;
+
+    cs = s;
+    while (--n > 0 && (c = __getc(f)) != EOF) {
+	*cs++ = c;
+	if (c == '\n')
+	    break;
+	}
+    if (c == EOF && cs == s)
+	return NULL;
+    *cs = '\0';
+    return s;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fputs function.
+****************************************************************************/
+int fputs(
+    const char *s,
+    FILE *f)
+{
+    int r = 0;
+    int c;
+
+    while ((c = *s++) != 0)
+	r = __putc(c, f);
+    return r;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fclose function.
+****************************************************************************/
+int fclose(
+    FILE *f)
+{
+    fflush(f);
+    _OS2Close((HFILE)f->handle);
+    PM_free(f);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h
new file mode 100755
index 0000000..03286bd
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h
@@ -0,0 +1,29 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit OS/2 VDD
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c
new file mode 100755
index 0000000..6688bab
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c
@@ -0,0 +1,1050 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit OS/2 VDD
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "sdd/sddhelp.h"
+#include "mtrr.h"
+
+#define TRACE(a)
+
+/*--------------------------- Global variables ----------------------------*/
+
+#define MAX_MEMORY_SHARED           100
+#define MAX_MEMORY_MAPPINGS         100
+
+/* TODO: I think the global and linear members will be the same, but not sure yet. */
+typedef struct {
+    void    *linear;
+    ulong   global;
+    ulong   length;
+    int     npages;
+    } memshared;
+
+typedef struct {
+    ulong   physical;
+    ulong   linear;
+    ulong   length;
+    int     npages;
+    ibool   isCached;
+    } mmapping;
+
+static int          numMappings = 0;
+static memshared    shared[MAX_MEMORY_MAPPINGS] = {0};
+static mmapping     maps[MAX_MEMORY_MAPPINGS];
+ibool               _PM_haveBIOS = TRUE;
+char                _PM_cntPath[PM_MAX_PATH] = "";     /* there just isn't any */
+uchar               *_PM_rmBufAddr = NULL;
+ushort _VARAPI      PM_savedDS = 0;   /* why can't I use the underscore prefix? */
+
+HVDHSEM             hevFarCallRet = NULL;
+HVDHSEM             hevIRet       = NULL;
+HHOOK               hhookUserReturnHook = NULL;
+HHOOK               hhookUserIRetHook   = NULL;
+
+static void (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* Functions to read and write CMOS registers */
+
+ulong   PMAPI _PM_getPDB(void);
+uchar   PMAPI _PM_readCMOS(int index);
+void    PMAPI _PM_writeCMOS(int index,uchar value);
+
+VOID HOOKENTRY UserReturnHook(PVOID pRefData, PCRF pcrf);
+VOID HOOKENTRY UserIRetHook(PVOID pRefData, PCRF pcrf);
+
+void PMAPI PM_init(void)
+{
+    MTRR_init();
+
+    /* Initialize VDD-specific data */
+    /* Note: PM_init must be (obviously) called in VDM task context! */
+    VDHCreateSem(&hevFarCallRet, VDH_EVENTSEM);
+    VDHCreateSem(&hevIRet, VDH_EVENTSEM);
+    hhookUserReturnHook = VDHAllocHook(VDH_RETURN_HOOK, (PFNARM)UserReturnHook, 0);
+    hhookUserIRetHook   = VDHAllocHook(VDH_RETURN_HOOK, (PFNARM)UserIRetHook, 0);
+
+    if ((hevIRet == NULL) || (hevFarCallRet == NULL) ||
+	(hhookUserReturnHook == NULL) || (hhookUserIRetHook == NULL)) {
+	/* something failed, we can't go on */
+	/* TODO: take some action here! */
+	}
+}
+
+/* Do some cleaning up */
+void PMAPI PM_exit(void)
+{
+    /* Note: Hooks allocated during or after VDM creation are deallocated automatically */
+    if (hevIRet != NULL)
+	VDHDestroySem(hevIRet);
+
+    if (hevFarCallRet != NULL)
+	VDHDestroySem(hevFarCallRet);
+}
+
+ibool PMAPI PM_haveBIOSAccess(void)
+{ return _PM_haveBIOS; }
+
+long PMAPI PM_getOSType(void)
+{ return /*_OS_OS2VDD*/ _OS_OS2; }  /*FIX!! */
+
+int PMAPI PM_getModeType(void)
+{ return PM_386; }
+
+void PMAPI PM_backslash(char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '\\') {
+	s[pos] = '\\';
+	s[pos+1] = '\0';
+	}
+}
+
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+void PMAPI PM_fatalError(const char *msg)
+{
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+/*    Fatal_Error_Handler(msg,0);  TODO: implement somehow! */
+}
+
+/****************************************************************************
+PARAMETERS:
+len     - Place to store the length of the buffer
+rseg    - Place to store the real mode segment of the buffer
+roff    - Place to store the real mode offset of the buffer
+
+REMARKS:
+This function returns the address and length of the global VESA transfer
+buffer.
+****************************************************************************/
+void * PMAPI PM_getVESABuf(
+    uint *len,
+    uint *rseg,
+    uint *roff)
+{
+    if (_PM_rmBufAddr) {
+	*len = 0; /*VESA_BUF_SIZE; */
+	*rseg = (ulong)(_PM_rmBufAddr) >> 4;
+	*roff = (ulong)(_PM_rmBufAddr) & 0xF;
+	return _PM_rmBufAddr;
+	}
+    return NULL;
+}
+
+int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out)
+{
+    /* Unused in VDDs */
+    return 0;
+}
+
+char * PMAPI PM_getCurrentPath(char *path,int maxLen)
+{
+    strncpy(path, _PM_cntPath, maxLen);
+    path[maxLen - 1] = 0;
+    return path;
+}
+
+char PMAPI PM_getBootDrive(void)
+{
+    ulong   boot = 3;
+    boot = VDHQuerySysValue(0, VDHGSV_BOOTDRV);
+    return (char)('a' + boot - 1);
+}
+
+const char * PMAPI PM_getVBEAFPath(void)
+{
+    static char path[CCHMAXPATH];
+    strcpy(path,"x:\\");
+    path[0] = PM_getBootDrive();
+    return path;
+}
+
+const char * PMAPI PM_getNucleusPath(void)
+{
+	static char path[CCHMAXPATH];
+	strcpy(path,"x:\\os2\\drivers");
+	path[0] = PM_getBootDrive();
+	PM_backslash(path);
+	strcat(path,"nucleus");
+	return path;
+}
+
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+const char * PMAPI PM_getUniqueID(void)
+{ return PM_getMachineName(); }
+
+const char * PMAPI PM_getMachineName(void)
+{
+    return "Unknown";
+}
+
+int PMAPI PM_kbhit(void)
+{ return 1; }
+
+int PMAPI PM_getch(void)
+{ return 0; }
+
+PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen)
+{
+    /* Unused in VDDs */
+    return NULL;
+}
+
+int PMAPI PM_getConsoleStateSize(void)
+{
+    /* Unused in VDDs */
+    return 1;
+}
+
+void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole)
+{
+    /* Unused in VDDs */
+}
+
+void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags))
+{
+    /* Unused in VDDs */
+}
+
+void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole)
+{
+    /* Unused in VDDs */
+}
+
+void PMAPI PM_closeConsole(PM_HWND hwndConsole)
+{
+    /* Unused in VDDs */
+}
+
+void PMAPI PM_setOSCursorLocation(int x,int y)
+{
+    uchar *_biosPtr = PM_getBIOSPointer();
+    PM_setByte(_biosPtr+0x50,x);
+    PM_setByte(_biosPtr+0x51,y);
+}
+
+void PMAPI PM_setOSScreenWidth(int width,int height)
+{
+    uchar *_biosPtr = PM_getBIOSPointer();
+    PM_setByte(_biosPtr+0x4A,width);
+    PM_setByte(_biosPtr+0x84,height-1);
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of shared memory. For OS/2 VDD we allocate shared memory
+as locked, global memory that is accessible from any memory context
+(including interrupt time context), which allows us to load our important
+data structure and code such that we can access it directly from a ring
+0 interrupt context.
+****************************************************************************/
+void * PMAPI PM_mallocShared(long size)
+{
+    ULONG       nPages = (size + 0xFFF) >> 12;
+    int         i;
+
+    /* First find a free slot in our shared memory table */
+    for (i = 0; i < MAX_MEMORY_SHARED; i++) {
+	if (shared[i].linear == 0)
+	    break;
+	}
+    if (i < MAX_MEMORY_SHARED) {
+	shared[i].linear = VDHAllocPages(NULL, nPages, VDHAP_SYSTEM | VDHAP_FIXED);
+	shared[i].npages = nPages;
+	shared[i].global = (ULONG)shared[i].linear;
+	return (void*)shared[i].global;
+	}
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of shared memory
+****************************************************************************/
+void PMAPI PM_freeShared(void *p)
+{
+    int i;
+
+    /* Find a shared memory block in our table and free it */
+    for (i = 0; i < MAX_MEMORY_SHARED; i++) {
+	if (shared[i].global == (ulong)p) {
+	    VDHFreePages(shared[i].linear);
+	    shared[i].linear = 0;
+	    break;
+	    }
+	}
+}
+
+void * PMAPI PM_mapToProcess(void *base,ulong limit)
+{ return (void*)base; }
+
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS,
+    ulong BIOSLen)
+{
+    /* TODO: Figure out how to do this */
+    return false;
+}
+
+void * PMAPI PM_getBIOSPointer(void)
+{ return (void*)0x400; }
+
+void * PMAPI PM_getA0000Pointer(void)
+{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); }
+
+/****************************************************************************
+PARAMETERS:
+base        - Physical base address of the memory to maps in
+limit       - Limit of physical memory to region to maps in
+
+RETURNS:
+Linear address of the newly mapped memory.
+
+REMARKS:
+Maps a physical memory range to a linear memory range.
+****************************************************************************/
+ulong MapPhysicalToLinear(
+    ulong base,
+    ulong limit,
+    int *npages)
+{
+    ulong   linear,length = limit+1;
+    int     i,ppage,flags;
+#if 0
+    ppage = base >> 12;
+    *npages = (length + (base & 0xFFF) + 4095) >> 12;
+    flags = PR_FIXED | PR_STATIC;
+    if (base == 0xA0000) {
+	/* We require the linear address to be aligned to a 64Kb boundary
+	 * for mapping the banked framebuffer (so we can do efficient
+	 * carry checking for bank changes in the assembler code). The only
+	 * way to ensure this is to force the linear address to be aligned
+	 * to a 4Mb boundary.
+	 */
+	flags |= PR_4MEG;
+	}
+    if ((linear = (ulong)PageReserve(PR_SYSTEM,*npages,flags)) == (ulong)-1)
+	return 0;
+    if (!PageCommitPhys(linear >> 12,*npages,ppage,PC_INCR | PC_USER | PC_WRITEABLE))
+	return 0;
+#endif
+    return linear + (base & 0xFFF);
+}
+
+/****************************************************************************
+PARAMETERS:
+base        - Physical base address of the memory to map in
+limit       - Limit of physical memory to region to map in
+isCached    - True if the memory should be cached, false if not
+
+RETURNS:
+Linear address of the newly mapped memory.
+
+REMARKS:
+This function maps physical memory to linear memory, which can then be used
+to create a selector or used directly from 32-bit protected mode programs.
+This is better than DPMI 0x800, since it allows you to maps physical
+memory below 1Mb, which gets this memory out of the way of the Windows VxD's
+sticky paws.
+
+NOTE:   If the memory is not expected to be cached, this function will
+	directly re-program the PCD (Page Cache Disable) bit in the
+	page tables. There does not appear to be a mechanism in the VMM
+	to control this bit via the regular interface.
+****************************************************************************/
+void * PMAPI PM_mapPhysicalAddr(
+    ulong base,
+    ulong limit,
+    ibool isCached)
+{
+    ulong   linear,length = limit+1;
+    int     i,npages;
+    ulong   PDB,*pPDB;
+
+    /* Search table of existing mappings to see if we have already mapped
+     * a region of memory that will serve this purpose.
+     */
+    for (i = 0; i < numMappings; i++) {
+	if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached)
+	    return (void*)maps[i].linear;
+	}
+    if (numMappings == MAX_MEMORY_MAPPINGS)
+	return NULL;
+
+    /* We did not find any previously mapped memory region, so map it in.
+     * Note that we do not use MapPhysToLinear, since this function appears
+     * to have problems mapping memory in the 1Mb physical address space.
+     * Hence we use PageReserve and PageCommitPhys.
+     */
+    if ((linear = MapPhysicalToLinear(base,limit,&npages)) == 0)
+	return NULL;
+    maps[numMappings].physical = base;
+    maps[numMappings].length = length;
+    maps[numMappings].linear = linear;
+    maps[numMappings].npages = npages;
+    maps[numMappings].isCached = isCached;
+    numMappings++;
+
+#if 0
+    /* Finally disable caching where necessary */
+    if (!isCached && (PDB = _PM_getPDB()) != 0) {
+	int     startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage;
+	ulong   pageTable,*pPageTable;
+
+	if (PDB >= 0x100000)
+	    pPDB = (ulong*)MapPhysicalToLinear(PDB,0xFFF,&npages);
+	else
+	    pPDB = (ulong*)PDB;
+	if (pPDB) {
+	    startPDB = (linear >> 22) & 0x3FF;
+	    startPage = (linear >> 12) & 0x3FF;
+	    endPDB = ((linear+limit) >> 22) & 0x3FF;
+	    endPage = ((linear+limit) >> 12) & 0x3FF;
+	    for (iPDB = startPDB; iPDB <= endPDB; iPDB++) {
+		pageTable = pPDB[iPDB] & ~0xFFF;
+		if (pageTable >= 0x100000)
+		    pPageTable = (ulong*)MapPhysicalToLinear(pageTable,0xFFF,&npages);
+		else
+		    pPageTable = (ulong*)pageTable;
+		start = (iPDB == startPDB) ? startPage : 0;
+		end = (iPDB == endPDB) ? endPage : 0x3FF;
+		for (iPage = start; iPage <= end; iPage++)
+		    pPageTable[iPage] |= 0x10;
+		PageFree((ulong)pPageTable,PR_STATIC);
+		}
+	    PageFree((ulong)pPDB,PR_STATIC);
+	    }
+	}
+#endif
+    return (void*)linear;
+}
+
+void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit)
+{
+    /* We never free the mappings */
+}
+
+void PMAPI PM_sleep(ulong milliseconds)
+{
+    /* We never sleep in a VDD */
+}
+
+int PMAPI PM_getCOMPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	}
+    return 0;
+}
+
+int PMAPI PM_getLPTPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+ulong PMAPI PM_getPhysicalAddr(void *p)
+{
+	/* TODO: This function should find the physical address of a linear */
+	/*               address. */
+	return 0xFFFFFFFFUL;
+}
+
+void PMAPI _PM_freeMemoryMappings(void)
+{
+    int i;
+/*    for (i = 0; i < numMappings; i++) */
+/*        PageFree(maps[i].linear,PR_STATIC); */
+}
+
+void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off)
+{ return (void*)MK_PHYS(r_seg,r_off); }
+
+void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off)
+{ return NULL; }
+
+void PMAPI PM_freeRealSeg(void *mem)
+{ }
+
+void PMAPI DPMI_int86(int intno, DPMI_regs *regs)
+{
+    /* Unsed in VDDs */
+}
+
+/****************************************************************************
+REMARKS:
+Load the V86 registers in the client state, and save the original state
+before loading the registers.
+****************************************************************************/
+static void LoadV86Registers(
+    PCRF saveRegs,
+    RMREGS *in,
+    RMSREGS *sregs)
+{
+    PCRF            pcrf;     /* current client register frame */
+
+    /* get pointer to registers */
+    pcrf = (PCRF)VDHQuerySysValue(CURRENT_VDM, VDHLSV_PCRF);
+
+    /* Note: We could do VDHPushRegs instead but this should be safer as it */
+    /* doesn't rely on the VDM session having enough free stack space. */
+    *saveRegs = *pcrf;        /* save all registers */
+
+    pcrf->crf_eax = in->e.eax;    /* load new values */
+    pcrf->crf_ebx = in->e.ebx;
+    pcrf->crf_ecx = in->e.ecx;
+    pcrf->crf_edx = in->e.edx;
+    pcrf->crf_esi = in->e.esi;
+    pcrf->crf_edi = in->e.edi;
+    pcrf->crf_es  = sregs->es;
+    pcrf->crf_ds  = sregs->ds;
+
+}
+
+/****************************************************************************
+REMARKS:
+Read the V86 registers from the client state and restore the original state.
+****************************************************************************/
+static void ReadV86Registers(
+    PCRF saveRegs,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    PCRF            pcrf;     /* current client register frame */
+
+    /* get pointer to registers */
+    pcrf = (PCRF)VDHQuerySysValue(CURRENT_VDM, VDHLSV_PCRF);
+
+    /* read new register values */
+    out->e.eax = pcrf->crf_eax;
+    out->e.ebx = pcrf->crf_ebx;
+    out->e.ecx = pcrf->crf_ecx;
+    out->e.edx = pcrf->crf_edx;
+    out->e.esi = pcrf->crf_esi;
+    out->e.edi = pcrf->crf_edi;
+    sregs->es  = pcrf->crf_es;
+    sregs->ds  = pcrf->crf_ds;
+
+    /* restore original client registers */
+    *pcrf = *saveRegs;
+}
+
+/****************************************************************************
+REMARKS: Used for far calls into V86 code
+****************************************************************************/
+VOID HOOKENTRY UserReturnHook(
+  PVOID pRefData,
+  PCRF pcrf )
+{
+    VDHPostEventSem(hevFarCallRet);
+}
+
+/****************************************************************************
+REMARKS: Used for calling BIOS interrupts
+****************************************************************************/
+VOID HOOKENTRY UserIRetHook(
+  PVOID pRefData,
+  PCRF pcrf )
+{
+    VDHPostEventSem(hevIRet);
+}
+
+/****************************************************************************
+REMARKS:
+Call a V86 real mode function with the specified register values
+loaded before the call. The call returns with a far ret.
+Must be called from within a DOS session context!
+****************************************************************************/
+void PMAPI PM_callRealMode(
+    uint seg,
+    uint off,
+    RMREGS *regs,
+    RMSREGS *sregs)
+{
+    CRF   saveRegs;
+    FPFN  fnAddress;
+    ULONG rc;
+
+    TRACE("SDDHELP: Entering PM_callRealMode()\n");
+    LoadV86Registers(SSToDS(&saveRegs),regs,sregs);
+
+    /* set up return hook for call */
+    rc = VDHArmReturnHook(hhookUserReturnHook, VDHARH_CSEIP_HOOK);
+
+    VDHResetEventSem(hevFarCallRet);
+
+    /* the address is a 16:32 pointer */
+    OFFSETOF32(fnAddress)  = off;
+    SEGMENTOF32(fnAddress) = seg;
+    rc = VDHPushFarCall(fnAddress);
+    VDHYield(0);
+
+    /* wait until the V86 call returns - our return hook posts the semaphore */
+    rc = VDHWaitEventSem(hevFarCallRet, SEM_INDEFINITE_WAIT);
+
+    ReadV86Registers(SSToDS(&saveRegs),regs,sregs);
+    TRACE("SDDHELP: Exiting PM_callRealMode()\n");
+}
+
+/****************************************************************************
+REMARKS:
+Issue a V86 real mode interrupt with the specified register values
+loaded before the interrupt.
+Must be called from within a DOS session context!
+****************************************************************************/
+int PMAPI PM_int86(
+    int intno,
+    RMREGS *in,
+    RMREGS *out)
+{
+    RMSREGS    sregs = {0};
+    CRF        saveRegs;
+    ushort     oldDisable;
+    ULONG      rc;
+
+    memset(SSToDS(&sregs), 0, sizeof(sregs));
+
+#if 0   /* do we need this?? */
+    /* Disable pass-up to our VDD handler so we directly call BIOS */
+    TRACE("SDDHELP: Entering PM_int86()\n");
+    if (disableTSRFlag) {
+	oldDisable = *disableTSRFlag;
+	*disableTSRFlag = 0;
+	}
+#endif
+
+    LoadV86Registers(SSToDS(&saveRegs), in, SSToDS(&sregs));
+
+    VDHResetEventSem(hevIRet);
+    rc = VDHPushInt(intno);
+
+    /* set up return hook for interrupt */
+    rc = VDHArmReturnHook(hhookUserIRetHook, VDHARH_NORMAL_IRET);
+
+    VDHYield(0);
+
+    /* wait until the V86 IRETs - our return hook posts the semaphore */
+    rc = VDHWaitEventSem(hevIRet, 5000); /*SEM_INDEFINITE_WAIT); */
+
+    ReadV86Registers(SSToDS(&saveRegs), out, SSToDS(&sregs));
+
+#if 0
+    /* Re-enable pass-up to our VDD handler if previously enabled */
+    if (disableTSRFlag)
+	*disableTSRFlag = oldDisable;
+#endif
+
+    TRACE("SDDHELP: Exiting PM_int86()\n");
+    return out->x.ax;
+
+}
+
+/****************************************************************************
+REMARKS:
+Issue a V86 real mode interrupt with the specified register values
+loaded before the interrupt.
+****************************************************************************/
+int PMAPI PM_int86x(
+    int intno,
+    RMREGS *in,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    CRF             saveRegs;
+    ushort          oldDisable;
+    ULONG       rc;
+
+#if 0
+    /* Disable pass-up to our VxD handler so we directly call BIOS */
+    TRACE("SDDHELP: Entering PM_int86x()\n");
+    if (disableTSRFlag) {
+	oldDisable = *disableTSRFlag;
+	*disableTSRFlag = 0;
+	}
+#endif
+    LoadV86Registers(SSToDS(&saveRegs), in, sregs);
+
+    VDHResetEventSem(hevIRet);
+    rc = VDHPushInt(intno);
+
+    /* set up return hook for interrupt */
+    rc = VDHArmReturnHook(hhookUserIRetHook, VDHARH_NORMAL_IRET);
+
+    VDHYield(0);
+
+    /* wait until the V86 IRETs - our return hook posts the semaphore */
+    rc = VDHWaitEventSem(hevIRet, 5000); /*SEM_INDEFINITE_WAIT); */
+
+    ReadV86Registers(SSToDS(&saveRegs), out, sregs);
+
+#if 0
+    /* Re-enable pass-up to our VxD handler if previously enabled */
+    if (disableTSRFlag)
+	*disableTSRFlag = oldDisable;
+#endif
+
+    TRACE("SDDHELP: Exiting PM_int86x()\n");
+    return out->x.ax;
+}
+
+void PMAPI PM_availableMemory(ulong *physical,ulong *total)
+{ *physical = *total = 0; }
+
+/****************************************************************************
+REMARKS:
+Allocates a block of locked physical memory.
+****************************************************************************/
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16M)
+{
+    ULONG       flags = VDHAP_SYSTEM;
+    ULONG       nPages = (size + 0xFFF) >> 12;
+
+    flags |= (physAddr != NULL) ? VDHAP_PHYSICAL : VDHAP_FIXED;
+
+    return VDHAllocPages(physAddr, nPages, VDHAP_SYSTEM | VDHAP_PHYSICAL);
+}
+
+/****************************************************************************
+REMARKS:
+Frees a block of locked physical memory.
+****************************************************************************/
+void PMAPI PM_freeLockedMem(
+    void *p,
+    uint size,
+    ibool contiguous)
+{
+    if (p)
+	VDHFreePages((PVOID)p);
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    ULONG  lockHandle;
+
+    /* TODO: the lock handle is essential for the unlock operation!! */
+    lockHandle = VDHLockMem(p, len, 0, (PVOID)VDHLM_NO_ADDR, NULL);
+
+    if (lockHandle != NULL)
+       return 0;
+    else
+       return 1;
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    /* TODO: implement - use a table of lock handles? */
+    /* VDHUnlockPages(lockHandle); */
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    return PM_lockDataPages((void*)p,len,lh);
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    return PM_unlockDataPages((void*)p,len,lh);
+}
+
+/****************************************************************************
+REMARKS:
+OS specific shared libraries not supported inside a VDD
+****************************************************************************/
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    (void)szDLLName;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+OS specific shared libraries not supported inside a VDD
+****************************************************************************/
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+OS specific shared libraries not supported inside a VDD
+****************************************************************************/
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    (void)hModule;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+void *PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    /* TODO: This function should start a directory enumeration search */
+    /*       given the filename (with wildcards). The data should be */
+    /*       converted and returned in the findData standard form. */
+    (void)filename;
+    (void)findData;
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    void *handle,
+    PM_findData *findData)
+{
+    /* TODO: This function should find the next file in directory enumeration */
+    /*       search given the search criteria defined in the call to */
+    /*       PM_findFirstFile. The data should be converted and returned */
+    /*       in the findData standard form. */
+    (void)handle;
+    (void)findData;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    void *handle)
+{
+    /* TODO: This function should close the find process. This may do */
+    /*       nothing for some OS'es. */
+    (void)handle;
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    /* Not applicable in a VDD */
+    (void)drive;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    /* Not applicable in a VDD */
+    (void)drive;
+    (void)dir;
+    (void)len;
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+RETURNS:
+Error code describing the result.
+
+REMARKS:
+Function to enable write combining for the specified region of memory.
+****************************************************************************/
+int PMAPI PM_enableWriteCombine(
+    ulong base,
+    ulong size,
+    uint type)
+{
+    return MTRR_enableWriteCombine(base,size,type);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+    /* TODO: Implement this ? */
+    (void)filename;
+    (void)attrib;
+    PM_fatalError("PM_setFileAttr not implemented!");
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file attributes for a specific file.
+****************************************************************************/
+uint PMAPI PM_getFileAttr(
+    const char *filename)
+{
+    /* TODO: Implement this ? */
+    (void)filename;
+    PM_fatalError("PM_getFileAttr not implemented!");
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+    /* TODO: Implement this ? */
+    (void)filename;
+    PM_fatalError("PM_mkdir not implemented!");
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+    /* TODO: Implement this ? */
+    (void)filename;
+    PM_fatalError("PM_rmdir not implemented!");
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_getFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this ? */
+    (void)filename;
+    (void)gmTime;
+    (void)time;
+    PM_fatalError("PM_getFileTime not implemented!");
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to set the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_setFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this ? */
+    (void)filename;
+    (void)gmTime;
+    (void)time;
+    PM_fatalError("PM_setFileTime not implemented!");
+    return false;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c
new file mode 100755
index 0000000..2163928
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c
@@ -0,0 +1,45 @@
+/****************************************************************************
+*
+*                                       SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:             ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+	return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+	return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c
new file mode 100755
index 0000000..631f655
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c
@@ -0,0 +1,103 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit OS/2 VDD
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+/*---------------------------- Global variables ---------------------------*/
+
+static ulong    frequency = 1193180;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+#define __ZTimerInit()
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOn(tm)     VTD_Get_Real_Time(&tm->start.high,&tm->start.low)
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+static ulong __LZTimerLap(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger    lap,count;
+    VTD_Get_Real_Time(&lap.high,&lap.low);
+    _CPU_diffTime64(&tm->start,&lap,&count);
+    return _CPU_calcMicroSec(&count,frequency);
+}
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOff(tm)    VTD_Get_Real_Time(&tm->end.high,&tm->end.low)
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+static ulong __LZTimerCount(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger tmCount;
+    _CPU_diffTime64(&tm->start,&tm->end,&tmCount);
+    return _CPU_calcMicroSec(&tmCount,frequency);
+}
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION     1000
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer value from the BIOS timer tick.
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{
+    return VDHQuerySysValue(0, VDHGSV_MSECSBOOT);
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm
new file mode 100755
index 0000000..64a7cec
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm
@@ -0,0 +1,299 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: 32-bit Windows VxD
+;*
+;* Description: Low level assembly support for the PM library specific to
+;*              Windows VxDs.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"               ; Memory model macros
+
+header      _pm                     ; Set up memory model
+
+begdataseg  _pm
+
+    cextern _PM_savedDS,USHORT
+
+enddataseg  _pm
+
+P586
+
+begcodeseg  _pm                 ; Start of code segment
+
+;----------------------------------------------------------------------------
+; void PM_segread(PMSREGS *sregs)
+;----------------------------------------------------------------------------
+; Read the current value of all segment registers
+;----------------------------------------------------------------------------
+cprocstart  PM_segread
+
+        ARG     sregs:DPTR
+
+        enter_c
+
+        mov     ax,es
+        _les    _si,[sregs]
+        mov     [_ES _si],ax
+        mov     [_ES _si+2],cs
+        mov     [_ES _si+4],ss
+        mov     [_ES _si+6],ds
+        mov     [_ES _si+8],fs
+        mov     [_ES _si+10],gs
+
+        leave_c
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs)
+;----------------------------------------------------------------------------
+; Issues a software interrupt in protected mode. This routine has been
+; written to allow user programs to load CS and DS with different values
+; other than the default.
+;----------------------------------------------------------------------------
+cprocstart  PM_int386x
+
+; Not used for VxDs
+
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_saveDS(void)
+;----------------------------------------------------------------------------
+; Save the value of DS into a section of the code segment, so that we can
+; quickly load this value at a later date in the PM_loadDS() routine from
+; inside interrupt handlers etc. The method to do this is different
+; depending on the DOS extender being used.
+;----------------------------------------------------------------------------
+cprocstart  PM_saveDS
+
+        mov     [_PM_savedDS],ds    ; Store away in data segment
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_loadDS(void)
+;----------------------------------------------------------------------------
+; Routine to load the DS register with the default value for the current
+; DOS extender. Only the DS register is loaded, not the ES register, so
+; if you wish to call C code, you will need to also load the ES register
+; in 32 bit protected mode.
+;----------------------------------------------------------------------------
+cprocstart  PM_loadDS
+
+        mov     ds,[cs:_PM_savedDS] ; We can access the proper DS through CS
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setBankA(int bank)
+;----------------------------------------------------------------------------
+cprocstart      PM_setBankA
+
+; Not used for VxDs
+
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setBankAB(int bank)
+;----------------------------------------------------------------------------
+cprocstart      PM_setBankAB
+
+; Not used for VxDs
+
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void PM_setCRTStart(int x,int y,int waitVRT)
+;----------------------------------------------------------------------------
+cprocstart      PM_setCRTStart
+
+; Not used for VxDs
+
+        ret
+
+cprocend
+
+; Macro to delay briefly to ensure that enough time has elapsed between
+; successive I/O accesses so that the device being accessed can respond
+; to both accesses even on a very fast PC.
+
+ifdef   USE_NASM
+%macro  DELAY 0
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+%endmacro
+%macro  IODELAYN 1
+%rep    %1
+        DELAY
+%endrep
+%endmacro
+else
+macro   DELAY
+        jmp     short $+2
+        jmp     short $+2
+        jmp     short $+2
+endm
+macro   IODELAYN    N
+    rept    N
+        DELAY
+    endm
+endm
+endif
+
+;----------------------------------------------------------------------------
+; uchar _PM_readCMOS(int index)
+;----------------------------------------------------------------------------
+; Read the value of a specific CMOS register. We do this with both
+; normal interrupts and NMI disabled.
+;----------------------------------------------------------------------------
+cprocstart  _PM_readCMOS
+
+        ARG     index:UINT
+
+        push    _bp
+        mov     _bp,_sp
+        pushfd
+        mov     al,[BYTE index]
+        or      al,80h              ; Add disable NMI flag
+        cli
+        out     70h,al
+        IODELAYN 5
+        in      al,71h
+        mov     ah,al
+        xor     al,al
+        IODELAYN 5
+        out     70h,al              ; Re-enable NMI
+        mov     al,ah               ; Return value in AL
+        popfd
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; void _PM_writeCMOS(int index,uchar value)
+;----------------------------------------------------------------------------
+; Read the value of a specific CMOS register. We do this with both
+; normal interrupts and NMI disabled.
+;----------------------------------------------------------------------------
+cprocstart  _PM_writeCMOS
+
+        ARG     index:UINT, value:UCHAR
+
+        push    _bp
+        mov     _bp,_sp
+        pushfd
+        mov     al,[BYTE index]
+        or      al,80h              ; Add disable NMI flag
+        cli
+        out     70h,al
+        IODELAYN 5
+        mov     al,[value]
+        out     71h,al
+        xor     al,al
+        IODELAYN 5
+        out     70h,al              ; Re-enable NMI
+        popfd
+        pop     _bp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; double _ftol(double f)
+;----------------------------------------------------------------------------
+; Calls to __ftol are generated by the Borland C++ compiler for code
+; that needs to convert a floating point type to an integral type.
+;
+; Input: floating point number on the top of the '87.
+;
+; Output: a (signed or unsigned) long in EAX
+; All other registers preserved.
+;-----------------------------------------------------------------------
+cprocstart  _ftol
+
+        LOCAL   temp1:WORD, temp2:QWORD = LocalSize
+
+        push    ebp
+        mov     ebp,esp
+        sub     esp,LocalSize
+
+        fstcw   [temp1]                 ; save the control word
+        fwait
+        mov     al,[BYTE temp1+1]
+        or      [BYTE temp1+1],0Ch      ; set rounding control to chop
+        fldcw   [temp1]
+        fistp   [temp2]                 ; convert to 64-bit integer
+        mov     [BYTE temp1+1],al
+        fldcw   [temp1]                 ; restore the control word
+        mov     eax,[DWORD temp2]       ; return LS 32 bits
+        mov     edx,[DWORD temp2+4]     ;        MS 32 bits
+
+        mov     esp,ebp
+        pop     ebp
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; _PM_getPDB - Return the Page Table Directory Base address
+;----------------------------------------------------------------------------
+cprocstart  _PM_getPDB
+
+        mov     eax,cr3
+        and     eax,0FFFFF000h
+        ret
+
+cprocend
+
+;----------------------------------------------------------------------------
+; Flush the Translation Lookaside buffer
+;----------------------------------------------------------------------------
+cprocstart  PM_flushTLB
+
+        wbinvd                  ; Flush the CPU cache
+        mov     eax,cr3
+        mov     cr3,eax         ; Flush the TLB
+        ret
+
+cprocend
+
+endcodeseg  _pm
+
+        END                     ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c
new file mode 100755
index 0000000..3c7eaae
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c
@@ -0,0 +1,66 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows VxD
+*
+* Description:  VxD specific code for the CPU detection module.
+*
+****************************************************************************/
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Do nothing for VxD's
+****************************************************************************/
+#define SetMaxThreadPriority()      0
+
+/****************************************************************************
+REMARKS:
+Do nothing for VxD's
+****************************************************************************/
+#define RestoreThreadPriority(i)    (void)(i)
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    freq->low = 1193180;
+    freq->high = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)                           \
+{                                               \
+    CPU_largeInteger count;                     \
+    VTD_Get_Real_Time(&count.high,&count.low);  \
+    (t)->low = count.low;                       \
+    (t)->high = count.high;                     \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c
new file mode 100755
index 0000000..3c6ce99
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c
@@ -0,0 +1,304 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows VxD
+*
+* Description:  C library compatible I/O functions for use within a VxD.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "vxdfile.h"
+
+/*------------------------ Main Code Implementation -----------------------*/
+
+#define EOF -1
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fopen function.
+****************************************************************************/
+FILE * fopen(
+    const char *filename,
+    const char *mode)
+{
+    FILE    *f = PM_malloc(sizeof(FILE));
+    long    oldpos;
+
+    if (f) {
+	f->offset = 0;
+	f->text = (mode[1] == 't' || mode[2] == 't');
+	f->writemode = (mode[0] == 'w') || (mode[0] == 'a');
+	if (initComplete) {
+	    WORD    omode,error;
+	    BYTE    action;
+
+	    if (mode[0] == 'r') {
+		omode = OPEN_ACCESS_READONLY | OPEN_SHARE_COMPATIBLE;
+		action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_FAIL;
+		}
+	    else if (mode[0] == 'w') {
+		omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_COMPATIBLE;
+		action = ACTION_IFEXISTS_TRUNCATE | ACTION_IFNOTEXISTS_CREATE;
+		}
+	    else {
+		omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_COMPATIBLE;
+		action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_CREATE;
+		}
+	    f->handle = (int)R0_OpenCreateFile(false,(char*)filename,omode,ATTR_NORMAL,action,0,&error,&action);
+	    if (f->handle == 0) {
+		PM_free(f);
+		return NULL;
+		}
+	    f->filesize = R0_GetFileSize((HANDLE)f->handle,&error);
+	    if (mode[0] == 'a')
+		fseek(f,0,2);
+	    }
+	else {
+	    int oflag,pmode;
+
+	    if (mode[0] == 'r') {
+		pmode = _S_IREAD;
+		oflag = _O_RDONLY;
+		}
+	    else if (mode[0] == 'w') {
+		pmode = _S_IWRITE;
+		oflag = _O_WRONLY | _O_CREAT | _O_TRUNC;
+		}
+	    else {
+		pmode = _S_IWRITE;
+		oflag = _O_RDWR | _O_CREAT | _O_APPEND;
+		}
+	    if (f->text)
+		oflag |= _O_TEXT;
+	    else
+		oflag |= _O_BINARY;
+	    if ((f->handle = i_open(filename,oflag,pmode)) == -1) {
+		PM_free(f);
+		return NULL;
+		}
+	    oldpos = i_lseek(f->handle,0,1);
+	    f->filesize = i_lseek(f->handle,0,2);
+	    i_lseek(f->handle,oldpos,0);
+	    }
+	}
+    return f;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fread function. Note that the VxD file I/O
+functions are layered on DOS, so can only read up to 64K at a time. Since
+we are expected to handle much larger chunks than this, we handle larger
+blocks automatically in here.
+****************************************************************************/
+size_t fread(
+    void *ptr,
+    size_t size,
+    size_t n,
+    FILE *f)
+{
+    char    *buf = ptr;
+    WORD    error;
+    int     bytes = size * n;
+    int     readbytes,totalbytes = 0;
+
+    while (bytes > 0x10000) {
+	if (initComplete) {
+	    readbytes  = R0_ReadFile(false,(HANDLE)f->handle,buf,0x8000,f->offset,&error);
+	    readbytes += R0_ReadFile(false,(HANDLE)f->handle,buf+0x8000,0x8000,f->offset+0x8000,&error);
+	    }
+	else {
+	    readbytes  = i_read(f->handle,buf,0x8000);
+	    readbytes += i_read(f->handle,buf+0x8000,0x8000);
+	    }
+	totalbytes += readbytes;
+	f->offset += readbytes;
+	buf += 0x10000;
+	bytes -= 0x10000;
+	}
+    if (bytes) {
+	if (initComplete)
+	    readbytes = R0_ReadFile(false,(HANDLE)f->handle,buf,bytes,f->offset,&error);
+	else
+	    readbytes = i_read(f->handle,buf,bytes);
+	totalbytes += readbytes;
+	f->offset += readbytes;
+	}
+    return totalbytes / size;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fwrite function. Note that the VxD file I/O
+functions are layered on DOS, so can only read up to 64K at a time. Since
+we are expected to handle much larger chunks than this, we handle larger
+blocks automatically in here.
+****************************************************************************/
+size_t fwrite(
+    const void *ptr,
+    size_t size,
+    size_t n,
+    FILE *f)
+{
+    const char  *buf = ptr;
+    WORD        error;
+    int         bytes = size * n;
+    int         writtenbytes,totalbytes = 0;
+
+    if (!f->writemode)
+	return 0;
+    while (bytes > 0x10000) {
+	if (initComplete) {
+	    writtenbytes  = R0_WriteFile(false,(HANDLE)f->handle,buf,0x8000,f->offset,&error);
+	    writtenbytes += R0_WriteFile(false,(HANDLE)f->handle,buf+0x8000,0x8000,f->offset+0x8000,&error);
+	    }
+	else {
+	    writtenbytes  = i_write(f->handle,buf,0x8000);
+	    writtenbytes += i_write(f->handle,buf+0x8000,0x8000);
+	    }
+	totalbytes += writtenbytes;
+	f->offset += writtenbytes;
+	buf += 0x10000;
+	bytes -= 0x10000;
+	}
+    if (initComplete)
+	writtenbytes = R0_WriteFile(false,(HANDLE)f->handle,buf,bytes,f->offset,&error);
+    else
+	writtenbytes = i_write(f->handle,buf,bytes);
+    totalbytes += writtenbytes;
+    f->offset += writtenbytes;
+    if (f->offset > f->filesize)
+	f->filesize = f->offset;
+    return totalbytes / size;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fflush function.
+****************************************************************************/
+int fflush(
+    FILE *f)
+{
+    /* Nothing to do since we are not doing buffered file I/O */
+    (void)f;
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fseek function.
+****************************************************************************/
+int fseek(
+    FILE *f,
+    long int offset,
+    int whence)
+{
+    if (whence == 0)
+	f->offset = offset;
+    else if (whence == 1)
+	f->offset += offset;
+    else if (whence == 2)
+	f->offset = f->filesize + offset;
+    if (!initComplete)
+	i_lseek(f->handle,f->offset,0);
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C ftell function.
+****************************************************************************/
+long ftell(
+    FILE *f)
+{
+    return f->offset;
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C feof function.
+****************************************************************************/
+int feof(
+    FILE *f)
+{
+    return (f->offset == f->filesize);
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fgets function.
+****************************************************************************/
+char *fgets(
+    char *s,
+    int n,
+    FILE *f)
+{
+    int     len;
+    char    *cs;
+
+    /* Read the entire buffer into memory (our functions are unbuffered!) */
+    if ((len = fread(s,1,n,f)) == 0)
+	return NULL;
+
+    /* Search for '\n' or end of string */
+    if (n > len)
+	n = len;
+    cs = s;
+    while (--n > 0) {
+	if (*cs == '\n')
+	    break;
+	cs++;
+	}
+    *cs = '\0';
+    return s;
+}
+
+/****************************************************************************
+REMARKS:
+NT driver implementation of the ANSI C fputs function.
+****************************************************************************/
+int fputs(
+    const char *s,
+    FILE *f)
+{
+    return fwrite(s,1,strlen(s),f);
+}
+
+/****************************************************************************
+REMARKS:
+VxD implementation of the ANSI C fclose function.
+****************************************************************************/
+int fclose(
+    FILE *f)
+{
+    WORD error;
+
+    if (initComplete)
+	R0_CloseFile((HANDLE)f->handle,&error);
+    else
+	i_close(f->handle);
+    PM_free(f);
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h
new file mode 100755
index 0000000..7efc0f9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h
@@ -0,0 +1,29 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows VxD
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c
new file mode 100755
index 0000000..4cb7f19
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c
@@ -0,0 +1,1359 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows VxD
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "sdd/sddhelp.h"
+#include "mtrr.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+#define MAX_MEMORY_SHARED           100
+#define MAX_MEMORY_MAPPINGS         100
+
+typedef struct {
+    void    *linear;
+    ulong   global;
+    ulong   length;
+    int     npages;
+    } memshared;
+
+typedef struct {
+    ulong   physical;
+    ulong   linear;
+    ulong   length;
+    int     npages;
+    ibool   isCached;
+    } mmapping;
+
+static int          numMappings = 0;
+static memshared    shared[MAX_MEMORY_MAPPINGS] = {0};
+static mmapping     maps[MAX_MEMORY_MAPPINGS];
+extern ibool        _PM_haveBIOS;
+char                _PM_cntPath[PM_MAX_PATH] = "";
+char                _PM_nucleusPath[PM_MAX_PATH] = "";
+uchar               *_PM_rmBufAddr = NULL;
+ushort _VARAPI      _PM_savedDS = 0;
+static uchar        _PM_oldCMOSRegA;
+static uchar        _PM_oldCMOSRegB;
+PM_intHandler       _PM_rtcHandler = NULL;
+IRQHANDLE           RTCIRQHandle = 0;
+VPICD_HWInt_THUNK   RTCInt_Thunk;
+
+static char *szWindowsKey       = "Software\\Microsoft\\Windows\\CurrentVersion";
+static char *szSystemRoot       = "SystemRoot";
+static char *szMachineNameKey   = "System\\CurrentControlSet\\control\\ComputerName\\ComputerName";
+static char *szMachineName      = "ComputerName";
+static void (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* Functions to read and write CMOS registers */
+
+ulong   PMAPI _PM_getPDB(void);
+uchar   PMAPI _PM_readCMOS(int index);
+void    PMAPI _PM_writeCMOS(int index,uchar value);
+
+/****************************************************************************
+REMARKS:
+PM_malloc override function for Nucleus drivers loaded in VxD's.
+****************************************************************************/
+void * VXD_malloc(
+    size_t size)
+{
+    return PM_mallocShared(size);
+}
+
+/****************************************************************************
+REMARKS:
+PM_calloc override function for Nucleus drivers loaded in VxD's.
+****************************************************************************/
+void * VXD_calloc(
+    size_t nelem,
+    size_t size)
+{
+    void *p = PM_mallocShared(nelem * size);
+    if (p)
+	memset(p,0,nelem * size);
+    return p;
+}
+
+/****************************************************************************
+REMARKS:
+PM_realloc override function for Nucleus drivers loaded in VxD's.
+****************************************************************************/
+void * VXD_realloc(
+    void *ptr,
+    size_t size)
+{
+    void *p = PM_mallocShared(size);
+    if (p) {
+	memcpy(p,ptr,size);
+	PM_freeShared(ptr);
+	}
+    return p;
+}
+
+/****************************************************************************
+REMARKS:
+PM_free override function for Nucleus drivers loaded in VxD's.
+****************************************************************************/
+void VXD_free(
+    void *p)
+{
+    PM_freeShared(p);
+}
+
+/****************************************************************************
+REMARKS:
+Initialise the PM library.
+****************************************************************************/
+void PMAPI PM_init(void)
+{
+    /* Override the default memory allocators for all Nucleus drivers
+     * loaded in SDDHELP/PMHELP. We do this so that we can ensure all memory
+     * dynamically allocated by Nucleus drivers and internal C runtime
+     * library functions are shared memory blocks that all processes
+     * connecting to SDDHELP can see.
+     */
+    PM_useLocalMalloc(VXD_malloc,VXD_calloc,VXD_realloc,VXD_free);
+
+    /* Initialiase the MTRR module */
+    MTRR_init();
+}
+
+ibool PMAPI PM_haveBIOSAccess(void)
+{ return _PM_haveBIOS; }
+
+long PMAPI PM_getOSType(void)
+{ return _OS_WIN32VXD; }
+
+int PMAPI PM_getModeType(void)
+{ return PM_386; }
+
+void PMAPI PM_backslash(char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '\\') {
+	s[pos] = '\\';
+	s[pos+1] = '\0';
+	}
+}
+
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+void PMAPI PM_fatalError(const char *msg)
+{
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+    Fatal_Error_Handler(msg,0);
+}
+
+/****************************************************************************
+PARAMETERS:
+len     - Place to store the length of the buffer
+rseg    - Place to store the real mode segment of the buffer
+roff    - Place to store the real mode offset of the buffer
+
+REMARKS:
+This function returns the address and length of the global VESA transfer
+buffer that is used for communicating with the VESA BIOS functions from
+Win16 and Win32 programs under Windows.
+****************************************************************************/
+void * PMAPI PM_getVESABuf(
+    uint *len,
+    uint *rseg,
+    uint *roff)
+{
+    /* If the VxD is dynamically loaded we will not have a real mode
+     * transfer buffer to return, so we fail the call.
+     */
+    if (_PM_rmBufAddr) {
+	*len = VESA_BUF_SIZE;
+	*rseg = (ulong)(_PM_rmBufAddr) >> 4;
+	*roff = (ulong)(_PM_rmBufAddr) & 0xF;
+	return _PM_rmBufAddr;
+	}
+    return NULL;
+}
+
+int PMAPI PM_int386(
+    int intno,
+    PMREGS *in,
+    PMREGS *out)
+{
+    /* Unused in VxDs */
+    return 0;
+}
+
+void PMAPI _PM_getRMvect(
+    int intno,
+    long *realisr)
+{
+    WORD    seg;
+    DWORD   off;
+
+    Get_V86_Int_Vector(intno,&seg,&off);
+    *realisr = ((long)seg << 16) | (off & 0xFFFF);
+}
+
+void PMAPI _PM_setRMvect(
+    int intno,
+    long realisr)
+{
+    Set_V86_Int_Vector(intno,realisr >> 16,realisr & 0xFFFF);
+}
+
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    strncpy(path,_PM_cntPath,maxLen);
+    path[maxLen-1] = 0;
+    return path;
+}
+
+char PMAPI PM_getBootDrive(void)
+{ return 'c'; }
+
+const char * PMAPI PM_getVBEAFPath(void)
+{ return "c:\\"; }
+
+/****************************************************************************
+PARAMETERS:
+szKey       - Key to query (can contain version number formatting)
+szValue     - Value to get information for
+value       - Place to store the registry key data read
+size        - Size of the string buffer to read into
+
+RETURNS:
+true if the key was found, false if not.
+****************************************************************************/
+static ibool REG_queryString(
+    char *szKey,
+    char *szValue,
+    char *value,
+    ulong size)
+{
+    HKEY    hKey;
+    ulong   type;
+    ibool   status = false;
+
+    memset(value,0,sizeof(value));
+    if (RegOpenKey(HKEY_LOCAL_MACHINE,szKey,&hKey) == ERROR_SUCCESS) {
+	if (RegQueryValueEx(hKey,(PCHAR)szValue,(ulong*)NULL,(ulong*)&type,value,(ulong*)&size) == ERROR_SUCCESS)
+	    status = true;
+	RegCloseKey(hKey);
+	}
+    return status;
+}
+
+const char * PMAPI PM_getNucleusPath(void)
+{
+    static char path[256];
+
+    if (strlen(_PM_nucleusPath) > 0) {
+	strcpy(path,_PM_nucleusPath);
+	PM_backslash(path);
+	return path;
+	}
+    if (!REG_queryString(szWindowsKey,szSystemRoot,path,sizeof(path)))
+	strcpy(path,"c:\\windows");
+    PM_backslash(path);
+    strcat(path,"system\\nucleus");
+    return path;
+}
+
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+const char * PMAPI PM_getUniqueID(void)
+{ return PM_getMachineName(); }
+
+const char * PMAPI PM_getMachineName(void)
+{
+    static char name[256];
+    if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name)))
+	return name;
+    return "Unknown";
+}
+
+int PMAPI PM_kbhit(void)
+{ return 1; }
+
+int PMAPI PM_getch(void)
+{ return 0; }
+
+PM_HWND PMAPI PM_openConsole(
+    PM_HWND hwndUser,
+    int device,
+    int xRes,
+    int yRes,
+    int bpp,
+    ibool fullScreen)
+{
+    /* Unused in VxDs */
+    return NULL;
+}
+
+int PMAPI PM_getConsoleStateSize(void)
+{
+    /* Unused in VxDs */
+    return 1;
+}
+
+void PMAPI PM_saveConsoleState(
+    void *stateBuf,
+    PM_HWND hwndConsole)
+{
+    /* Unused in VxDs */
+}
+
+void PMAPI PM_setSuspendAppCallback(
+    int (_ASMAPIP saveState)(
+	int flags))
+{
+    /* Unused in VxDs */
+}
+
+void PMAPI PM_restoreConsoleState(
+    const void *stateBuf,
+    PM_HWND hwndConsole)
+{
+    /* Unused in VxDs */
+}
+
+void PMAPI PM_closeConsole(
+    PM_HWND hwndConsole)
+{
+    /* Unused in VxDs */
+}
+
+void PM_setOSCursorLocation(
+    int x,
+    int y)
+{
+    uchar *_biosPtr = PM_getBIOSPointer();
+    PM_setByte(_biosPtr+0x50,x);
+    PM_setByte(_biosPtr+0x51,y);
+}
+
+void PM_setOSScreenWidth(
+    int width,
+    int height)
+{
+    uchar *_biosPtr = PM_getBIOSPointer();
+    PM_setByte(_biosPtr+0x4A,width);
+    PM_setByte(_biosPtr+0x84,height-1);
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of shared memory. For Win9x we allocate shared memory
+as locked, global memory that is accessible from any memory context
+(including interrupt time context), which allows us to load our important
+data structure and code such that we can access it directly from a ring
+0 interrupt context.
+****************************************************************************/
+void * PMAPI PM_mallocShared(
+    long size)
+{
+    MEMHANDLE   hMem;
+    DWORD       pgNum,nPages = (size + 0xFFF) >> 12;
+    int         i;
+
+    /* First find a free slot in our shared memory table */
+    for (i = 0; i < MAX_MEMORY_SHARED; i++) {
+	if (shared[i].linear == 0)
+	    break;
+	}
+    if (i < MAX_MEMORY_SHARED) {
+	PageAllocate(nPages,PG_SYS,0,0,0,0,NULL,0,&hMem,&shared[i].linear);
+	shared[i].npages = nPages;
+	pgNum = (ulong)shared[i].linear >> 12;
+	shared[i].global = LinPageLock(pgNum,nPages,PAGEMAPGLOBAL);
+	return (void*)shared[i].global;
+	}
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of shared memory
+****************************************************************************/
+void PMAPI PM_freeShared(void *p)
+{
+    int i;
+
+    /* Find a shared memory block in our table and free it */
+    for (i = 0; i < MAX_MEMORY_SHARED; i++) {
+	if (shared[i].global == (ulong)p) {
+	    LinPageUnLock(shared[i].global >> 12,shared[i].npages,PAGEMAPGLOBAL);
+	    PageFree((ulong)shared[i].linear,0);
+	    shared[i].linear = 0;
+	    break;
+	    }
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Maps a shared memory block into process address space. Does nothing since
+the memory blocks are already globally7 mapped into all processes.
+****************************************************************************/
+void * PMAPI PM_mapToProcess(
+    void *base,
+    ulong limit)
+{
+    return (void*)base;
+}
+
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS,
+    ulong BIOSLen)
+{
+    /* TODO: Figure out how to do this */
+    return false;
+}
+
+void * PMAPI PM_getBIOSPointer(void)
+{ return (void*)0x400; }
+
+void * PMAPI PM_getA0000Pointer(void)
+{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); }
+
+/****************************************************************************
+PARAMETERS:
+base        - Physical base address of the memory to maps in
+limit       - Limit of physical memory to region to maps in
+
+RETURNS:
+Linear address of the newly mapped memory.
+
+REMARKS:
+Maps a physical memory range to a linear memory range.
+****************************************************************************/
+ulong _PM_mapPhysicalToLinear(
+    ulong base,
+    ulong limit,
+    int *npages)
+{
+    ulong   linear,length = limit+1;
+    int     i,ppage,flags;
+
+    if (base < 0x100000) {
+	/* Windows 9x is zero based for the first meg of memory */
+	return base;
+	}
+    ppage = base >> 12;
+    *npages = (length + (base & 0xFFF) + 4095) >> 12;
+    flags = PR_FIXED | PR_STATIC;
+    if (base == 0xA0000) {
+	/* We require the linear address to be aligned to a 64Kb boundary
+	 * for mapping the banked framebuffer (so we can do efficient
+	 * carry checking for bank changes in the assembler code). The only
+	 * way to ensure this is to force the linear address to be aligned
+	 * to a 4Mb boundary.
+	 */
+	flags |= PR_4MEG;
+	}
+    if ((linear = (ulong)PageReserve(PR_SYSTEM,*npages,flags)) == (ulong)-1)
+	return 0xFFFFFFFF;
+    if (!PageCommitPhys(linear >> 12,*npages,ppage,PC_INCR | PC_USER | PC_WRITEABLE))
+	return 0xFFFFFFFF;
+    return linear + (base & 0xFFF);
+}
+
+/* Page table flags */
+
+#define PAGE_FLAGS_PRESENT			0x00000001
+#define PAGE_FLAGS_WRITEABLE		0x00000002
+#define PAGE_FLAGS_USER				0x00000004
+#define PAGE_FLAGS_WRITE_THROUGH	0x00000008
+#define PAGE_FLAGS_CACHE_DISABLE	0x00000010
+#define PAGE_FLAGS_ACCESSED			0x00000020
+#define PAGE_FLAGS_DIRTY			0x00000040
+#define PAGE_FLAGS_4MB	            0x00000080
+
+/****************************************************************************
+PARAMETERS:
+base        - Physical base address of the memory to maps in
+limit       - Limit of physical memory to region to maps in
+isCached    - True if the memory should be cached, false if not
+
+RETURNS:
+Linear address of the newly mapped memory.
+
+REMARKS:
+This function maps physical memory to linear memory, which can then be used
+to create a selector or used directly from 32-bit protected mode programs.
+This is better than DPMI 0x800, since it allows you to maps physical
+memory below 1Mb, which gets this memory out of the way of the Windows VDD's
+sticky paws.
+
+NOTE:   If the memory is not expected to be cached, this function will
+	directly re-program the PCD (Page Cache Disable) bit in the
+	page tables. There does not appear to be a mechanism in the VMM
+	to control this bit via the regular interface.
+****************************************************************************/
+void * PMAPI PM_mapPhysicalAddr(
+    ulong base,
+    ulong limit,
+    ibool isCached)
+{
+    ulong   linear,length = limit+1;
+    int     i,npages;
+    ulong   PDB,*pPDB;
+
+    /* Search table of existing mappings to see if we have already mapped
+     * a region of memory that will serve this purpose.
+     */
+    for (i = 0; i < numMappings; i++) {
+	if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached)
+	    return (void*)maps[i].linear;
+	}
+    if (numMappings == MAX_MEMORY_MAPPINGS)
+	return NULL;
+
+    /* We did not find any previously mapped memory region, so maps it in.
+     * Note that we do not use MapPhysToLinear, since this function appears
+     * to have problems mapping memory in the 1Mb physical address space.
+     * Hence we use PageReserve and PageCommitPhys.
+     */
+    if ((linear = _PM_mapPhysicalToLinear(base,limit,&npages)) == 0xFFFFFFFF)
+	return NULL;
+    maps[numMappings].physical = base;
+    maps[numMappings].length = length;
+    maps[numMappings].linear = linear;
+    maps[numMappings].npages = npages;
+    maps[numMappings].isCached = isCached;
+    numMappings++;
+
+    /* Finally disable caching where necessary */
+    if (!isCached && (PDB = _PM_getPDB()) != 0) {
+	int     startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage;
+	ulong   pageTable,*pPageTable;
+	pPDB = (ulong*)_PM_mapPhysicalToLinear(PDB,0xFFF,&npages);
+	if (pPDB) {
+	    startPDB = (linear >> 22) & 0x3FF;
+	    startPage = (linear >> 12) & 0x3FF;
+	    endPDB = ((linear+limit) >> 22) & 0x3FF;
+	    endPage = ((linear+limit) >> 12) & 0x3FF;
+	    for (iPDB = startPDB; iPDB <= endPDB; iPDB++) {
+		/* Set the bits in the page directory entry - required as per */
+		/* Pentium 4 manual. This also takes care of the 4MB page entries */
+		pPDB[iPDB] = pPDB[iPDB] |= (PAGE_FLAGS_WRITE_THROUGH | PAGE_FLAGS_CACHE_DISABLE);
+		if (!(pPDB[iPDB] & PAGE_FLAGS_4MB)) {
+		    /* If we are dealing with 4KB pages then we need to iterate */
+		    /* through each of the page table entries */
+		    pageTable = pPDB[iPDB] & ~0xFFF;
+		    pPageTable = (ulong*)_PM_mapPhysicalToLinear(pageTable,0xFFF,&npages);
+		    start = (iPDB == startPDB) ? startPage : 0;
+		    end = (iPDB == endPDB) ? endPage : 0x3FF;
+		    for (iPage = start; iPage <= end; iPage++)
+			pPageTable[iPage] |= (PAGE_FLAGS_WRITE_THROUGH | PAGE_FLAGS_CACHE_DISABLE);
+		    PageFree((ulong)pPageTable,PR_STATIC);
+		    }
+		}
+	    PageFree((ulong)pPDB,PR_STATIC);
+	    PM_flushTLB();
+	    }
+	}
+    return (void*)linear;
+}
+
+void PMAPI PM_freePhysicalAddr(
+    void *ptr,
+    ulong limit)
+{
+    /* We never free the mappings */
+}
+
+void PMAPI PM_sleep(ulong milliseconds)
+{
+    /* We never sleep in a VxD */
+}
+
+int PMAPI PM_getCOMPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	case 2: return 0x3E8;
+	case 3: return 0x2E8;
+	}
+    return 0;
+}
+
+int PMAPI PM_getLPTPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+ulong PMAPI PM_getPhysicalAddr(
+    void *p)
+{
+    DWORD   pte;
+
+    /* Touch the memory before calling CopyPageTable. For some reason */
+    /* we need to do this on Windows 9x, otherwise the memory may not */
+    /* be paged in correctly. Of course if the passed in pointer is */
+    /* invalid, this function will fault, but we shouldn't be passed bogus */
+    /* pointers anyway ;-) */
+    pte = *((ulong*)p);
+
+    /* Return assembled address value only if VMM service succeeds */
+    if (CopyPageTable(((DWORD)p) >> 12, 1, (PVOID*)&pte, 0))
+	return (pte & ~0xFFF) | (((DWORD)p) & 0xFFF);
+
+    /* Return failure to the caller! */
+    return 0xFFFFFFFFUL;
+}
+
+ibool PMAPI PM_getPhysicalAddrRange(
+    void *p,
+    ulong length,
+    ulong *physAddress)
+{
+    int     i;
+    ulong   linear = (ulong)p & ~0xFFF;
+
+    for (i = (length + 0xFFF) >> 12; i > 0; i--) {
+	if ((*physAddress++ = PM_getPhysicalAddr((void*)linear)) == 0xFFFFFFFF)
+	    return false;
+	linear += 4096;
+	}
+    return true;
+}
+
+void PMAPI _PM_freeMemoryMappings(void)
+{
+    int i;
+    for (i = 0; i < numMappings; i++)
+	PageFree(maps[i].linear,PR_STATIC);
+}
+
+void * PMAPI PM_mapRealPointer(
+    uint r_seg,
+    uint r_off)
+{
+    return (void*)MK_PHYS(r_seg,r_off);
+}
+
+void * PMAPI PM_allocRealSeg(
+    uint size,
+    uint *r_seg,
+    uint *r_off)
+{
+    return NULL;
+}
+
+void PMAPI PM_freeRealSeg(
+    void *mem)
+{
+}
+
+void PMAPI DPMI_int86(
+    int intno,
+    DPMI_regs *regs)
+{
+    /* Unsed in VxD's */
+}
+
+/****************************************************************************
+REMARKS:
+Load the V86 registers in the client state, and save the original state
+before loading the registers.
+****************************************************************************/
+static void LoadV86Registers(
+    CLIENT_STRUCT *saveRegs,
+    RMREGS *in,
+    RMSREGS *sregs)
+{
+    CLIENT_STRUCT   newRegs;
+
+    Save_Client_State(saveRegs);
+    newRegs = *saveRegs;
+    newRegs.CRS.Client_EAX = in->e.eax;
+    newRegs.CRS.Client_EBX = in->e.ebx;
+    newRegs.CRS.Client_ECX = in->e.ecx;
+    newRegs.CRS.Client_EDX = in->e.edx;
+    newRegs.CRS.Client_ESI = in->e.esi;
+    newRegs.CRS.Client_EDI = in->e.edi;
+    newRegs.CRS.Client_ES = sregs->es;
+    newRegs.CRS.Client_DS = sregs->ds;
+    Restore_Client_State(&newRegs);
+}
+
+/****************************************************************************
+REMARKS:
+Read the V86 registers from the client state and restore the original state.
+****************************************************************************/
+static void ReadV86Registers(
+    CLIENT_STRUCT *saveRegs,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    CLIENT_STRUCT   newRegs;
+
+    Save_Client_State(&newRegs);
+    out->e.eax = newRegs.CRS.Client_EAX;
+    out->e.ebx = newRegs.CRS.Client_EBX;
+    out->e.ecx = newRegs.CRS.Client_ECX;
+    out->e.edx = newRegs.CRS.Client_EDX;
+    out->e.esi = newRegs.CRS.Client_ESI;
+    out->e.edi = newRegs.CRS.Client_EDI;
+    sregs->es = newRegs.CRS.Client_ES;
+    sregs->ds = newRegs.CRS.Client_DS;
+    Restore_Client_State(saveRegs);
+}
+
+/****************************************************************************
+REMARKS:
+Call a V86 real mode function with the specified register values
+loaded before the call. The call returns with a far ret.
+****************************************************************************/
+void PMAPI PM_callRealMode(
+    uint seg,
+    uint off,
+    RMREGS *regs,
+    RMSREGS *sregs)
+{
+    CLIENT_STRUCT saveRegs;
+
+    /* Bail if we do not have BIOS access (ie: the VxD was dynamically
+     * loaded, and not statically loaded.
+     */
+    if (!_PM_haveBIOS)
+	return;
+
+    _TRACE("SDDHELP: Entering PM_callRealMode()\n");
+    Begin_Nest_V86_Exec();
+    LoadV86Registers(&saveRegs,regs,sregs);
+    Simulate_Far_Call(seg, off);
+    Resume_Exec();
+    ReadV86Registers(&saveRegs,regs,sregs);
+    End_Nest_Exec();
+    _TRACE("SDDHELP: Exiting PM_callRealMode()\n");
+}
+
+/****************************************************************************
+REMARKS:
+Issue a V86 real mode interrupt with the specified register values
+loaded before the interrupt.
+****************************************************************************/
+int PMAPI PM_int86(
+    int intno,
+    RMREGS *in,
+    RMREGS *out)
+{
+    RMSREGS         sregs = {0};
+    CLIENT_STRUCT   saveRegs;
+    ushort          oldDisable;
+
+    /* Bail if we do not have BIOS access (ie: the VxD was dynamically
+     * loaded, and not statically loaded.
+     */
+    if (!_PM_haveBIOS) {
+	*out = *in;
+	return out->x.ax;
+	}
+
+    /* Disable pass-up to our VxD handler so we directly call BIOS */
+    _TRACE("SDDHELP: Entering PM_int86()\n");
+    if (disableTSRFlag) {
+	oldDisable = *disableTSRFlag;
+	*disableTSRFlag = 0;
+	}
+    Begin_Nest_V86_Exec();
+    LoadV86Registers(&saveRegs,in,&sregs);
+    Exec_Int(intno);
+    ReadV86Registers(&saveRegs,out,&sregs);
+    End_Nest_Exec();
+
+    /* Re-enable pass-up to our VxD handler if previously enabled */
+    if (disableTSRFlag)
+	*disableTSRFlag = oldDisable;
+
+    _TRACE("SDDHELP: Exiting PM_int86()\n");
+    return out->x.ax;
+}
+
+/****************************************************************************
+REMARKS:
+Issue a V86 real mode interrupt with the specified register values
+loaded before the interrupt.
+****************************************************************************/
+int PMAPI PM_int86x(
+    int intno,
+    RMREGS *in,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    CLIENT_STRUCT   saveRegs;
+    ushort          oldDisable;
+
+    /* Bail if we do not have BIOS access (ie: the VxD was dynamically
+     * loaded, and not statically loaded.
+     */
+    if (!_PM_haveBIOS) {
+	*out = *in;
+	return out->x.ax;
+	}
+
+    /* Disable pass-up to our VxD handler so we directly call BIOS */
+    _TRACE("SDDHELP: Entering PM_int86x()\n");
+    if (disableTSRFlag) {
+	oldDisable = *disableTSRFlag;
+	*disableTSRFlag = 0;
+	}
+    Begin_Nest_V86_Exec();
+    LoadV86Registers(&saveRegs,in,sregs);
+    Exec_Int(intno);
+    ReadV86Registers(&saveRegs,out,sregs);
+    End_Nest_Exec();
+
+    /* Re-enable pass-up to our VxD handler if previously enabled */
+    if (disableTSRFlag)
+	*disableTSRFlag = oldDisable;
+
+    _TRACE("SDDHELP: Exiting PM_int86x()\n");
+    return out->x.ax;
+}
+
+/****************************************************************************
+REMARKS:
+Returns available memory. Not possible under Windows.
+****************************************************************************/
+void PMAPI PM_availableMemory(
+    ulong *physical,
+    ulong *total)
+{
+    *physical = *total = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocates a block of locked physical memory.
+****************************************************************************/
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16M)
+{
+    MEMHANDLE   hMem;
+    DWORD       nPages = (size + 0xFFF) >> 12;
+    DWORD       flags = PAGEFIXED | PAGEUSEALIGN | (contiguous ? PAGECONTIG : 0);
+    DWORD       maxPhys = below16M ? 0x00FFFFFF : 0xFFFFFFFF;
+    void        *p;
+
+    /* TODO: This may need to be modified if the memory needs to be globally */
+    /*       accessible. Check how we implemented PM_mallocShared() as we */
+    /*       may need to do something similar in here. */
+    PageAllocate(nPages,PG_SYS,0,0,0,maxPhys,physAddr,flags,&hMem,&p);
+
+    /* TODO: We may need to modify the memory blocks to disable caching via */
+    /*       the page tables (PCD|PWT) since DMA memory blocks *cannot* be */
+    /*       cached! */
+    return p;
+}
+
+/****************************************************************************
+REMARKS:
+Frees a block of locked physical memory.
+****************************************************************************/
+void PMAPI PM_freeLockedMem(
+    void *p,
+    uint size,
+    ibool contiguous)
+{
+    if (p)
+	PageFree((ulong)p,0);
+}
+
+/****************************************************************************
+REMARKS:
+Allocates a page aligned and page sized block of memory
+****************************************************************************/
+void * PMAPI PM_allocPage(
+    ibool locked)
+{
+    MEMHANDLE   hMem;
+    void        *p;
+
+    /* TODO: This will need to be modified if the memory needs to be globally */
+    /*       accessible. Check how we implemented PM_mallocShared() as we */
+    /*       may need to do something similar in here. */
+    PageAllocate(1,PG_SYS,0,0,0,0,0,PAGEFIXED,&hMem,&p);
+    return p;
+}
+
+/****************************************************************************
+REMARKS:
+Free a page aligned and page sized block of memory
+****************************************************************************/
+void PMAPI PM_freePage(
+    void *p)
+{
+    if (p)
+	PageFree((ulong)p,0);
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockDataPages(
+    void *p,
+    uint len,
+    PM_lockHandle *lh)
+{
+    DWORD pgNum = (ulong)p >> 12;
+    DWORD nPages = (len + (ulong)p - (pgNum << 12) + 0xFFF) >> 12;
+    return LinPageLock(pgNum,nPages,0);
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockDataPages(
+    void *p,
+    uint len,
+    PM_lockHandle *lh)
+{
+    DWORD pgNum = (ulong)p >> 12;
+    DWORD nPages = (len + (ulong)p - (pgNum << 12) + 0xFFF) >> 12;
+    return LinPageUnLock(pgNum,nPages,0);
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockCodePages(
+    void (*p)(),
+    uint len,
+    PM_lockHandle *lh)
+{
+    return PM_lockDataPages((void*)p,len,lh);
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockCodePages(
+    void (*p)(),
+    uint len,
+    PM_lockHandle *lh)
+{
+    return PM_unlockDataPages((void*)p,len,lh);
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock frequency (for stereo modes).
+****************************************************************************/
+void PMAPI PM_setRealTimeClockFrequency(
+    int frequency)
+{
+    static short convert[] = {
+	8192,
+	4096,
+	2048,
+	1024,
+	512,
+	256,
+	128,
+	64,
+	32,
+	16,
+	8,
+	4,
+	2,
+	-1,
+	};
+    int i;
+
+    /* First clear any pending RTC timeout if not cleared */
+    _PM_readCMOS(0x0C);
+    if (frequency == 0) {
+	/* Disable RTC timout */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F);
+	}
+    else {
+	/* Convert frequency value to RTC clock indexes */
+	for (i = 0; convert[i] != -1; i++) {
+	    if (convert[i] == frequency)
+		break;
+	    }
+
+	/* Set RTC timout value and enable timeout */
+	_PM_writeCMOS(0x0A,0x20 | (i+3));
+	_PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Real time clock interrupt handler, which calls the user registered C code.
+****************************************************************************/
+static BOOL __stdcall RTCInt_Handler(
+    VMHANDLE hVM,
+    IRQHANDLE hIRQ)
+{
+    static char inside = 0;
+
+    /* Clear priority interrupt controller and re-enable interrupts so we
+     * dont lock things up for long.
+     */
+    VPICD_Phys_EOI(hIRQ);
+
+    /* Clear real-time clock timeout */
+    _PM_readCMOS(0x0C);
+
+    /* Now call the C based interrupt handler (but check for mutual
+     * exclusion since we may still be servicing an old interrupt when a
+     * new one comes along; if that happens we ignore the old one).
+     */
+    if (!inside) {
+	inside = 1;
+	enable();
+	_PM_rtcHandler();
+	inside = 0;
+	}
+    return TRUE;
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock handler (used for software stereo modes).
+****************************************************************************/
+ibool PMAPI PM_setRealTimeClockHandler(
+    PM_intHandler ih,
+    int frequency)
+{
+    struct VPICD_IRQ_Descriptor IRQdesc;
+
+    /* Save the old CMOS real time clock values */
+    _PM_oldCMOSRegA = _PM_readCMOS(0x0A);
+    _PM_oldCMOSRegB = _PM_readCMOS(0x0B);
+
+    /* Set the real time clock interrupt handler */
+    CHECK(ih != NULL);
+    _PM_rtcHandler = ih;
+    IRQdesc.VID_IRQ_Number      = 0x8;
+    IRQdesc.VID_Options         = 0;
+    IRQdesc.VID_Hw_Int_Proc     = (DWORD)VPICD_Thunk_HWInt(RTCInt_Handler, &RTCInt_Thunk);
+    IRQdesc.VID_EOI_Proc        = 0;
+    IRQdesc.VID_Virt_Int_Proc   = 0;
+    IRQdesc.VID_Mask_Change_Proc= 0;
+    IRQdesc.VID_IRET_Proc       = 0;
+    IRQdesc.VID_IRET_Time_Out   = 500;
+    if ((RTCIRQHandle = VPICD_Virtualize_IRQ(&IRQdesc)) == 0)
+	return false;
+
+    /* Program the real time clock default frequency */
+    PM_setRealTimeClockFrequency(frequency);
+
+    /* Unmask IRQ8 in the PIC */
+    VPICD_Physically_Unmask(RTCIRQHandle);
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the original real time clock handler.
+****************************************************************************/
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    if (RTCIRQHandle) {
+	/* Restore CMOS registers and mask RTC clock */
+	_PM_writeCMOS(0x0A,_PM_oldCMOSRegA);
+	_PM_writeCMOS(0x0B,_PM_oldCMOSRegB);
+
+	/* Restore the interrupt vector */
+	VPICD_Set_Auto_Masking(RTCIRQHandle);
+	VPICD_Force_Default_Behavior(RTCIRQHandle);
+	RTCIRQHandle = 0;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+OS specific shared libraries not supported inside a VxD
+****************************************************************************/
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    (void)szDLLName;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+OS specific shared libraries not supported inside a VxD
+****************************************************************************/
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    (void)hModule;
+    (void)szProcName;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+OS specific shared libraries not supported inside a VxD
+****************************************************************************/
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    (void)hModule;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+void *PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    /* TODO: This function should start a directory enumeration search */
+    /*       given the filename (with wildcards). The data should be */
+    /*       converted and returned in the findData standard form. */
+    (void)filename;
+    (void)findData;
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    void *handle,
+    PM_findData *findData)
+{
+    /* TODO: This function should find the next file in directory enumeration */
+    /*       search given the search criteria defined in the call to */
+    /*       PM_findFirstFile. The data should be converted and returned */
+    /*       in the findData standard form. */
+    (void)handle;
+    (void)findData;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    void *handle)
+{
+    /* TODO: This function should close the find process. This may do */
+    /*       nothing for some OS'es. */
+    (void)handle;
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    /* Not supported in a VxD */
+    (void)drive;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    /* Not supported in a VxD */
+    (void)drive;
+    (void)dir;
+    (void)len;
+}
+
+/****************************************************************************
+PARAMETERS:
+base    - The starting physical base address of the region
+size    - The size in bytes of the region
+type    - Type to place into the MTRR register
+
+RETURNS:
+Error code describing the result.
+
+REMARKS:
+Function to enable write combining for the specified region of memory.
+****************************************************************************/
+int PMAPI PM_enableWriteCombine(
+    ulong base,
+    ulong size,
+    uint type)
+{
+    return MTRR_enableWriteCombine(base,size,type);
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+    /* TODO: Implement this */
+    (void)filename;
+    (void)attrib;
+    PM_fatalError("PM_setFileAttr not implemented yet!");
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file attributes for a specific file.
+****************************************************************************/
+uint PMAPI PM_getFileAttr(
+    const char *filename)
+{
+    /* TODO: Implement this */
+    (void)filename;
+    PM_fatalError("PM_getFileAttr not implemented yet!");
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+    /* TODO: Implement this */
+    (void)filename;
+    PM_fatalError("PM_mkdir not implemented yet!");
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+    /* TODO: Implement this */
+    (void)filename;
+    PM_fatalError("PM_rmdir not implemented yet!");
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_getFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this! */
+    (void)filename;
+    (void)gmTime;
+    (void)time;
+    PM_fatalError("PM_getFileTime not implemented yet!");
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to set the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_setFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    /* TODO: Implement this! */
+    (void)filename;
+    (void)gmTime;
+    (void)time;
+    PM_fatalError("PM_setFileTime not implemented yet!");
+    return false;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c
new file mode 100755
index 0000000..901ce1c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c
@@ -0,0 +1,45 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc)
+{
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c
new file mode 100755
index 0000000..76df48c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c
@@ -0,0 +1,105 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  32-bit Windows VxD
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+/*---------------------------- Global variables ---------------------------*/
+
+static ulong    frequency = 1193180;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+#define __ZTimerInit()
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOn(tm)     VTD_Get_Real_Time(&tm->start.high,&tm->start.low)
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+static ulong __LZTimerLap(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger    lap,count;
+    VTD_Get_Real_Time(&lap.high,&lap.low);
+    _CPU_diffTime64(&tm->start,&lap,&count);
+    return _CPU_calcMicroSec(&count,frequency);
+}
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+#define __LZTimerOff(tm)    VTD_Get_Real_Time(&tm->end.high,&tm->end.low)
+
+/****************************************************************************
+REMARKS:
+Call the assembler Zen Timer functions to do the timing.
+****************************************************************************/
+static ulong __LZTimerCount(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger tmCount;
+    _CPU_diffTime64(&tm->start,&tm->end,&tmCount);
+    return _CPU_calcMicroSec(&tmCount,frequency);
+}
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION     1000
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer value from the BIOS timer tick.
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{
+    CPU_largeInteger count;
+    VTD_Get_Real_Time(&count.high,&count.low);
+    return (count.low * 1000.0 / frequency);
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm b/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm
new file mode 100755
index 0000000..7c242b5
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm
@@ -0,0 +1,78 @@
+;****************************************************************************
+;*
+;*                  SciTech OS Portability Manager Library
+;*
+;*  ========================================================================
+;*
+;*    The contents of this file are subject to the SciTech MGL Public
+;*    License Version 1.0 (the "License"); you may not use this file
+;*    except in compliance with the License. You may obtain a copy of
+;*    the License at http://www.scitechsoft.com/mgl-license.txt
+;*
+;*    Software distributed under the License is distributed on an
+;*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+;*    implied. See the License for the specific language governing
+;*    rights and limitations under the License.
+;*
+;*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+;*
+;*    The Initial Developer of the Original Code is SciTech Software, Inc.
+;*    All Rights Reserved.
+;*
+;*  ========================================================================
+;*
+;* Language:    80386 Assembler, TASM 4.0 or NASM
+;* Environment: Win32
+;*
+;* Description: Low level assembly support for the PM library specific
+;*              to Windows.
+;*
+;****************************************************************************
+
+        IDEAL
+
+include "scitech.mac"               ; Memory model macros
+
+header      _pmwin32                    ; Set up memory model
+
+begdataseg  _pmwin32
+
+        cglobal _PM_ioentry
+        cglobal _PM_gdt
+_PM_ioentry     dd  0               ; Offset to call gate
+_PM_gdt         dw  0               ; Selector to call gate
+
+enddataseg  _pmwin32
+
+begcodeseg  _pmwin32                    ; Start of code segment
+
+;----------------------------------------------------------------------------
+; int PM_setIOPL(int iopl)
+;----------------------------------------------------------------------------
+; Change the IOPL level for the 32-bit task. Returns the previous level
+; so it can be restored for the task correctly.
+;----------------------------------------------------------------------------
+cprocstart  _PM_setIOPLViaCallGate
+
+        ARG     iopl:UINT
+
+        enter_c
+        pushfd                      ; Save the old EFLAGS for later
+        mov     ecx,[iopl]          ; ECX := IOPL level
+        xor     ebx,ebx             ; Change IOPL level function code
+ifdef   USE_NASM
+        call far dword [_PM_ioentry]
+else
+        call    [FWORD _PM_ioentry]
+endif
+        pop     eax
+        and     eax,0011000000000000b
+        shr     eax,12
+        leave_c
+        ret
+
+cprocend
+
+endcodeseg  _pmwin32
+
+        END                         ; End of module
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c
new file mode 100755
index 0000000..7da9752
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c
@@ -0,0 +1,94 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32
+*
+* Description:  Module to implement OS specific services to measure the
+*               CPU frequency.
+*
+****************************************************************************/
+
+/*---------------------------- Global variables ---------------------------*/
+
+static ibool havePerformanceCounter;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Increase the thread priority to maximum, if possible.
+****************************************************************************/
+static int SetMaxThreadPriority(void)
+{
+    int     oldPriority;
+    HANDLE  hThread = GetCurrentThread();
+
+    oldPriority = GetThreadPriority(hThread);
+    if (oldPriority != THREAD_PRIORITY_ERROR_RETURN)
+	SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL);
+    return oldPriority;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the original thread priority.
+****************************************************************************/
+static void RestoreThreadPriority(
+    int oldPriority)
+{
+    HANDLE  hThread = GetCurrentThread();
+
+    if (oldPriority != THREAD_PRIORITY_ERROR_RETURN)
+	SetThreadPriority(hThread, oldPriority);
+}
+
+/****************************************************************************
+REMARKS:
+Initialise the counter and return the frequency of the counter.
+****************************************************************************/
+static void GetCounterFrequency(
+    CPU_largeInteger *freq)
+{
+    if (!QueryPerformanceFrequency((LARGE_INTEGER*)freq)) {
+	havePerformanceCounter = false;
+	freq->low = 100000;
+	freq->high = 0;
+	}
+    else
+	havePerformanceCounter = true;
+}
+
+/****************************************************************************
+REMARKS:
+Read the counter and return the counter value.
+****************************************************************************/
+#define GetCounter(t)                                       \
+{                                                           \
+    if (havePerformanceCounter)                             \
+	QueryPerformanceCounter((LARGE_INTEGER*)t);         \
+    else {                                                  \
+	(t)->low = timeGetTime() * 100;                     \
+	(t)->high = 0;                                      \
+	}                                                   \
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c
new file mode 100755
index 0000000..d6c3f60
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c
@@ -0,0 +1,582 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32
+*
+* Description:  Win32 implementation for the SciTech cross platform
+*               event library.
+*
+****************************************************************************/
+
+#include "event.h"
+#include "pmapi.h"
+#include "win32/oshdr.h"
+#include "nucleus/graphics.h"
+
+/*---------------------------- Global Variables ---------------------------*/
+
+/* Publicly accessible variables */
+
+int                 _PM_deskX,_PM_deskY;/* Desktop dimentions           */
+HWND                _PM_hwndConsole;    /* Window handle for console    */
+#ifdef  __INTEL__
+uint                _PM_cw_default;     /* Default FPU control word     */
+#endif
+
+/* Private internal variables */
+
+static HINSTANCE    hInstApp = NULL;/* Application instance handle      */
+static HWND         hwndUser = NULL;/* User window handle               */
+static HINSTANCE    hInstDD = NULL; /* Handle to DirectDraw DLL         */
+static LPDIRECTDRAW lpDD = NULL;    /* DirectDraw object                */
+static LONG         oldWndStyle;    /* Info about old user window       */
+static LONG         oldExWndStyle;  /* Info about old user window       */
+static int          oldWinPosX;     /* Old window position X coordinate */
+static int          oldWinPosY;     /* Old window pisition Y coordinate */
+static int          oldWinSizeX;    /* Old window size X                */
+static int          oldWinSizeY;    /* Old window size Y                */
+static WNDPROC      oldWinProc = NULL;
+static PM_saveState_cb suspendApp = NULL;
+static ibool        waitActive = false;
+static ibool        isFullScreen = false;
+static ibool        backInGDI = false;
+
+/* Internal strings */
+
+static char *szWinClassName     = "SciTechDirectDrawWindow";
+static char *szAutoPlayKey      = "Software\\Microsoft\\Windows\\CurrentVersion\\Policies\\Explorer";
+static char *szAutoPlayValue    = "NoDriveTypeAutoRun";
+
+/* Dynalinks to DirectDraw functions */
+
+static HRESULT (WINAPI *pDirectDrawCreate)(GUID FAR *lpGUID, LPDIRECTDRAW FAR *lplpDD, IUnknown FAR *pUnkOuter);
+
+/*---------------------------- Implementation -----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Temporarily disables AutoPlay operation while we are running in fullscreen
+graphics modes.
+****************************************************************************/
+static void DisableAutoPlay(void)
+{
+    DWORD   dwAutoPlay,dwSize = sizeof(dwAutoPlay);
+    HKEY    hKey;
+
+    if (RegOpenKeyEx(HKEY_CURRENT_USER,szAutoPlayKey,0,KEY_EXECUTE | KEY_WRITE,&hKey) == ERROR_SUCCESS) {
+	RegQueryValueEx(hKey,szAutoPlayValue,NULL,NULL,(void*)&dwAutoPlay,&dwSize);
+	dwAutoPlay |= AUTOPLAY_DRIVE_CDROM;
+	RegSetValueEx(hKey,szAutoPlayValue,0,REG_DWORD,(void*)&dwAutoPlay,dwSize);
+	RegCloseKey(hKey);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Re-enables AutoPlay operation when we return to regular GDI mode.
+****************************************************************************/
+static void RestoreAutoPlay(void)
+{
+    DWORD   dwAutoPlay,dwSize = sizeof(dwAutoPlay);
+    HKEY    hKey;
+
+    if (RegOpenKeyEx(HKEY_CURRENT_USER,szAutoPlayKey,0,KEY_EXECUTE | KEY_WRITE,&hKey) == ERROR_SUCCESS) {
+	RegQueryValueEx(hKey,szAutoPlayValue,NULL,NULL,(void*)&dwAutoPlay,&dwSize);
+	dwAutoPlay &= ~AUTOPLAY_DRIVE_CDROM;
+	RegSetValueEx(hKey,szAutoPlayValue,0,REG_DWORD,(void*)&dwAutoPlay,dwSize);
+	RegCloseKey(hKey);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Suspends the application by switching back to the GDI desktop, allowing
+normal application code to be processed, and then waiting for the
+application activate command to bring us back to fullscreen mode with our
+window minimised.
+****************************************************************************/
+static void LeaveFullScreen(void)
+{
+    int retCode = PM_SUSPEND_APP;
+
+    if (backInGDI)
+	return;
+    if (suspendApp)
+	retCode = suspendApp(PM_DEACTIVATE);
+    RestoreAutoPlay();
+    backInGDI = true;
+
+    /* Now process messages normally until we are re-activated */
+    waitActive = true;
+    if (retCode != PM_NO_SUSPEND_APP) {
+	while (waitActive) {
+	    _EVT_pumpMessages();
+	    Sleep(200);
+	    }
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Reactivate all the surfaces for DirectDraw and set the system back up for
+fullscreen rendering.
+****************************************************************************/
+static void RestoreFullScreen(void)
+{
+    static ibool    firstTime = true;
+
+    if (firstTime) {
+	/* Clear the message queue while waiting for the surfaces to be
+	 * restored.
+	 */
+	firstTime = false;
+	while (1) {
+	    /* Continue looping until out application has been restored
+	     * and we have reset the display mode.
+	     */
+	    _EVT_pumpMessages();
+	    if (GetActiveWindow() == _PM_hwndConsole) {
+		if (suspendApp)
+		    suspendApp(PM_REACTIVATE);
+		DisableAutoPlay();
+		backInGDI = false;
+		waitActive = false;
+		firstTime = true;
+		return;
+		}
+	    Sleep(200);
+	    }
+	}
+}
+
+/****************************************************************************
+REMARKS:
+This function suspends the application by switching back to the GDI desktop,
+allowing normal application code to be processed and then waiting for the
+application activate command to bring us back to fullscreen mode with our
+window minimised.
+
+This version only gets called if we have not captured the screen switch in
+our activate message loops and will occur if the DirectDraw drivers lose a
+surface for some reason while rendering. This should not normally happen,
+but it is included just to be sure (it can happen on WinNT/2000 if the user
+hits the Ctrl-Alt-Del key combination). Note that this code will always
+spin loop, and we cannot disable the spin looping from this version (ie:
+if the user hits Ctrl-Alt-Del under WinNT/2000 the application main loop
+will cease to be executed until the user switches back to the application).
+****************************************************************************/
+void PMAPI PM_doSuspendApp(void)
+{
+    static  ibool firstTime = true;
+
+    /* Call system DLL version if found */
+    if (_PM_imports.PM_doSuspendApp != PM_doSuspendApp) {
+	_PM_imports.PM_doSuspendApp();
+	return;
+	}
+
+    if (firstTime) {
+	if (suspendApp)
+	    suspendApp(PM_DEACTIVATE);
+	RestoreAutoPlay();
+	firstTime = false;
+	backInGDI = true;
+	}
+    RestoreFullScreen();
+    firstTime = true;
+}
+
+/****************************************************************************
+REMARKS:
+Main Window proc for the full screen DirectDraw Window that we create while
+running in full screen mode. Here we capture all mouse and keyboard events
+for the window and plug them into our event queue.
+****************************************************************************/
+static LONG CALLBACK PM_winProc(
+    HWND hwnd,
+    UINT msg,
+    WPARAM wParam,
+    LONG lParam)
+{
+    switch (msg) {
+	case WM_SYSCHAR:
+	    /* Stop Alt-Space from pausing our application */
+	    return 0;
+	case WM_KEYDOWN:
+	case WM_SYSKEYDOWN:
+	    if (HIWORD(lParam) & KF_REPEAT) {
+		if (msg == WM_SYSKEYDOWN)
+		    return 0;
+		break;
+		}
+	    /* Fall through for keydown events */
+	case WM_KEYUP:
+	case WM_SYSKEYUP:
+	    if (msg == WM_SYSKEYDOWN || msg == WM_SYSKEYUP) {
+		if ((HIWORD(lParam) & KF_ALTDOWN) && wParam == VK_RETURN)
+		    break;
+		/* We ignore the remainder of the system keys to stop the
+		 * system menu from being activated from the keyboard and pausing
+		 * our app while fullscreen (ie: pressing the Alt key).
+		 */
+		return 0;
+		}
+	    break;
+	case WM_SYSCOMMAND:
+	    switch (wParam & ~0x0F) {
+		case SC_SCREENSAVE:
+		case SC_MONITORPOWER:
+		    /* Ignore screensaver requests in fullscreen modes */
+		    return 0;
+		}
+	    break;
+	case WM_SIZE:
+	    if (waitActive && backInGDI && (wParam != SIZE_MINIMIZED)) {
+		/* Start the re-activation process */
+		PostMessage(hwnd,WM_DO_SUSPEND_APP,WM_PM_RESTORE_FULLSCREEN,0);
+		}
+	    else if (!waitActive && isFullScreen && !backInGDI && (wParam == SIZE_MINIMIZED)) {
+		/* Start the de-activation process */
+		PostMessage(hwnd,WM_DO_SUSPEND_APP,WM_PM_LEAVE_FULLSCREEN,0);
+		}
+	    break;
+	case WM_DO_SUSPEND_APP:
+	    switch (wParam) {
+				case WM_PM_RESTORE_FULLSCREEN:
+					RestoreFullScreen();
+					break;
+				case WM_PM_LEAVE_FULLSCREEN:
+					LeaveFullScreen();
+					break;
+		}
+	    return 0;
+	}
+    if (oldWinProc)
+	return oldWinProc(hwnd,msg,wParam,lParam);
+    return DefWindowProc(hwnd,msg,wParam,lParam);
+}
+
+/****************************************************************************
+PARAMETERS:
+hwnd    - User window to convert
+width   - Window of the fullscreen window
+height  - Height of the fullscreen window
+
+RETURNS:
+Handle to converted fullscreen Window.
+
+REMARKS:
+This function takes the original user window handle and modifies the size,
+position and attributes for the window to convert it into a fullscreen
+window that we can use.
+****************************************************************************/
+static PM_HWND _PM_convertUserWindow(
+    HWND hwnd,
+    int width,
+    int height)
+{
+    RECT    window;
+
+    GetWindowRect(hwnd,&window);
+    oldWinPosX = window.left;
+    oldWinPosY = window.top;
+    oldWinSizeX = window.right - window.left;
+    oldWinSizeY = window.bottom - window.top;
+    oldWndStyle = SetWindowLong(hwnd,GWL_STYLE,WS_POPUP | WS_SYSMENU);
+    oldExWndStyle = SetWindowLong(hwnd,GWL_EXSTYLE,WS_EX_APPWINDOW);
+    ShowWindow(hwnd,SW_SHOW);
+    MoveWindow(hwnd,0,0,width,height,TRUE);
+    SetWindowPos(hwnd,HWND_TOPMOST,0,0,0,0,SWP_NOMOVE | SWP_NOSIZE);
+    oldWinProc = (WNDPROC)SetWindowLong(hwnd,GWL_WNDPROC, (LPARAM)PM_winProc);
+    return hwnd;
+}
+
+/****************************************************************************
+PARAMETERS:
+hwnd    - User window to restore
+
+REMARKS:
+This function restores the original attributes of the user window and put's
+it back into it's original state before it was converted to a fullscreen
+window.
+****************************************************************************/
+static void _PM_restoreUserWindow(
+    HWND hwnd)
+{
+    SetWindowLong(hwnd,GWL_WNDPROC, (LPARAM)oldWinProc);
+    SetWindowLong(hwnd,GWL_EXSTYLE,oldExWndStyle);
+    SetWindowLong(hwnd,GWL_STYLE,oldWndStyle);
+    SetWindowPos(hwnd,HWND_NOTOPMOST,0,0,0,0,SWP_NOMOVE | SWP_NOSIZE);
+    ShowWindow(hwnd,SW_SHOW);
+    MoveWindow(hwnd,oldWinPosX,oldWinPosY,oldWinSizeX,oldWinSizeY,TRUE);
+    oldWinProc = NULL;
+}
+
+/****************************************************************************
+PARAMETERS:
+device  - Index of the device to load DirectDraw for (0 for primary)
+
+REMARKS:
+Attempts to dynamically load the DirectDraw DLL's and create the DirectDraw
+objects that we need.
+****************************************************************************/
+void * PMAPI PM_loadDirectDraw(
+    int device)
+{
+    HDC         hdc;
+    int         bits;
+
+    /* Call system DLL version if found */
+    if (_PM_imports.PM_loadDirectDraw != PM_loadDirectDraw)
+	return _PM_imports.PM_loadDirectDraw(device);
+
+    /* TODO: Handle multi-monitor!! */
+    if (device != 0)
+	return NULL;
+
+    /* Load the DirectDraw DLL if not presently loaded */
+    GET_DEFAULT_CW();
+    if (!hInstDD) {
+	hdc = GetDC(NULL);
+	bits = GetDeviceCaps(hdc,BITSPIXEL);
+	ReleaseDC(NULL,hdc);
+	if (bits < 8)
+	    return NULL;
+	if ((hInstDD = LoadLibrary("ddraw.dll")) == NULL)
+	    return NULL;
+	pDirectDrawCreate = (void*)GetProcAddress(hInstDD,"DirectDrawCreate");
+	if (!pDirectDrawCreate)
+	    return NULL;
+	}
+
+    /* Create the DirectDraw object */
+    if (!lpDD && pDirectDrawCreate(NULL, &lpDD, NULL) != DD_OK) {
+	lpDD = NULL;
+	return NULL;
+	}
+    RESET_DEFAULT_CW();
+    return lpDD;
+}
+
+/****************************************************************************
+PARAMETERS:
+device  - Index of the device to unload DirectDraw for (0 for primary)
+
+REMARKS:
+Frees any DirectDraw objects for the device. We never actually explicitly
+unload the ddraw.dll library, since unloading and reloading it is
+unnecessary since we only want to unload it when the application exits and
+that happens automatically.
+****************************************************************************/
+void PMAPI PM_unloadDirectDraw(
+    int device)
+{
+    /* Call system DLL version if found */
+    if (_PM_imports.PM_unloadDirectDraw != PM_unloadDirectDraw) {
+	_PM_imports.PM_unloadDirectDraw(device);
+	return;
+	}
+    if (lpDD) {
+	IDirectDraw_Release(lpDD);
+	lpDD = NULL;
+	}
+    (void)device;
+}
+
+/****************************************************************************
+REMARKS:
+Open a console for output to the screen, creating the main event handling
+window if necessary.
+****************************************************************************/
+PM_HWND PMAPI PM_openConsole(
+    PM_HWND hWndUser,
+    int device,
+    int xRes,
+    int yRes,
+    int bpp,
+    ibool fullScreen)
+{
+    WNDCLASS        cls;
+    static ibool    classRegistered = false;
+
+    /* Call system DLL version if found */
+    GA_getSystemPMImports();
+    if (_PM_imports.PM_openConsole != PM_openConsole) {
+	if (fullScreen) {
+	    _PM_deskX = xRes;
+	    _PM_deskY = yRes;
+	    }
+	return _PM_imports.PM_openConsole(hWndUser,device,xRes,yRes,bpp,fullScreen);
+	}
+
+    /* Create the fullscreen window if necessary */
+    hwndUser = hWndUser;
+    if (fullScreen) {
+	if (!classRegistered) {
+	    /* Create a Window class for the fullscreen window in here, since
+	     * we need to register one that will do all our event handling for
+	     * us.
+	     */
+	    hInstApp            = GetModuleHandle(NULL);
+	    cls.hCursor         = LoadCursor(NULL,IDC_ARROW);
+	    cls.hIcon           = LoadIcon(hInstApp,MAKEINTRESOURCE(1));
+	    cls.lpszMenuName    = NULL;
+	    cls.lpszClassName   = szWinClassName;
+	    cls.hbrBackground   = GetStockObject(BLACK_BRUSH);
+	    cls.hInstance       = hInstApp;
+	    cls.style           = CS_DBLCLKS;
+	    cls.lpfnWndProc     = PM_winProc;
+	    cls.cbWndExtra      = 0;
+	    cls.cbClsExtra      = 0;
+	    if (!RegisterClass(&cls))
+		return NULL;
+	    classRegistered = true;
+	    }
+	_PM_deskX = xRes;
+	_PM_deskY = yRes;
+	if (!hwndUser) {
+	    char windowTitle[80];
+	    if (LoadString(hInstApp,1,windowTitle,sizeof(windowTitle)) == 0)
+		strcpy(windowTitle,"MGL Fullscreen Application");
+	    _PM_hwndConsole = CreateWindowEx(WS_EX_APPWINDOW,szWinClassName,
+		windowTitle,WS_POPUP | WS_SYSMENU,0,0,xRes,yRes,
+		NULL,NULL,hInstApp,NULL);
+	    }
+	else {
+	    _PM_hwndConsole = _PM_convertUserWindow(hwndUser,xRes,yRes);
+	    }
+	ShowCursor(false);
+	isFullScreen = true;
+	}
+    else {
+	_PM_hwndConsole = hwndUser;
+	isFullScreen = false;
+	}
+    SetFocus(_PM_hwndConsole);
+    SetForegroundWindow(_PM_hwndConsole);
+    DisableAutoPlay();
+    (void)bpp;
+    return _PM_hwndConsole;
+}
+
+/****************************************************************************
+REMARKS:
+Find the size of the console state buffer.
+****************************************************************************/
+int PMAPI PM_getConsoleStateSize(void)
+{
+    /* Call system DLL version if found */
+    if (_PM_imports.PM_getConsoleStateSize != PM_getConsoleStateSize)
+	return _PM_imports.PM_getConsoleStateSize();
+
+    /* Not used in Windows */
+    return 1;
+}
+
+/****************************************************************************
+REMARKS:
+Save the state of the console.
+****************************************************************************/
+void PMAPI PM_saveConsoleState(
+    void *stateBuf,
+    PM_HWND hwndConsole)
+{
+    /* Call system DLL version if found */
+    if (_PM_imports.PM_saveConsoleState != PM_saveConsoleState) {
+	_PM_imports.PM_saveConsoleState(stateBuf,hwndConsole);
+	return;
+	}
+
+    /* Not used in Windows */
+    (void)stateBuf;
+    (void)hwndConsole;
+}
+
+/****************************************************************************
+REMARKS:
+Set the suspend application callback for the fullscreen console.
+****************************************************************************/
+void PMAPI PM_setSuspendAppCallback(
+    PM_saveState_cb saveState)
+{
+    /* Call system DLL version if found */
+    if (_PM_imports.PM_setSuspendAppCallback != PM_setSuspendAppCallback) {
+	_PM_imports.PM_setSuspendAppCallback(saveState);
+	return;
+	}
+    suspendApp = saveState;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the console state.
+****************************************************************************/
+void PMAPI PM_restoreConsoleState(
+    const void *stateBuf,
+    PM_HWND hwndConsole)
+{
+    /* Call system DLL version if found */
+    if (_PM_imports.PM_restoreConsoleState != PM_restoreConsoleState) {
+	_PM_imports.PM_restoreConsoleState(stateBuf,hwndConsole);
+	return;
+	}
+
+    /* Not used in Windows */
+    (void)stateBuf;
+    (void)hwndConsole;
+}
+
+/****************************************************************************
+REMARKS:
+Close the fullscreen console.
+****************************************************************************/
+void PMAPI PM_closeConsole(
+    PM_HWND hwndConsole)
+{
+    /* Call system DLL version if found */
+    if (_PM_imports.PM_closeConsole != PM_closeConsole) {
+	_PM_imports.PM_closeConsole(hwndConsole);
+	return;
+	}
+    ShowCursor(true);
+    RestoreAutoPlay();
+    if (hwndUser)
+	_PM_restoreUserWindow(hwndConsole);
+    else
+	DestroyWindow(hwndConsole);
+    hwndUser = NULL;
+    _PM_hwndConsole = NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Return the DirectDraw window handle used by the application.
+****************************************************************************/
+PM_HWND PMAPI PM_getDirectDrawWindow(void)
+{
+    /* Call system DLL version if found */
+    if (_PM_imports.PM_getDirectDrawWindow != PM_getDirectDrawWindow)
+	return _PM_imports.PM_getDirectDrawWindow();
+    return _PM_hwndConsole;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c
new file mode 100755
index 0000000..86448e3
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c
@@ -0,0 +1,459 @@
+/****************************************************************************
+*
+*                   SciTech Multi-platform Graphics Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32
+*
+* Description:  Win32 implementation for the SciTech cross platform
+*               event library.
+*
+****************************************************************************/
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static ushort   keyUpMsg[256] = {0};    /* Table of key up messages     */
+static int      rangeX,rangeY;          /* Range of mouse coordinates   */
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* These are not used under Win32 */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flags)  (void)(flags)
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Scan code to test
+
+REMARKS:
+This macro determines if a specified key is currently down at the
+time that the call is made.
+****************************************************************************/
+#define _EVT_isKeyDown(scanCode)    (keyUpMsg[scanCode] != 0)
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{ return timeGetTime(); }
+
+/****************************************************************************
+REMARKS:
+Pumps all messages in the message queue from Win32 into our event queue.
+****************************************************************************/
+void _EVT_pumpMessages(void)
+{
+    MSG     msg;
+    MSG     charMsg;
+    event_t evt;
+
+    /* TODO: Add support for DirectInput! We can't support relative mouse */
+    /*       movement motion counters without DirectInput ;-(. */
+    while (PeekMessage(&msg,NULL,0,0,PM_REMOVE)) {
+	memset(&evt,0,sizeof(evt));
+	switch (msg.message) {
+	    case WM_MOUSEMOVE:
+		evt.what = EVT_MOUSEMOVE;
+		break;
+	    case WM_LBUTTONDBLCLK:
+		evt.what = EVT_MOUSEDOWN;
+		evt.message = EVT_LEFTBMASK | EVT_DBLCLICK;
+		break;
+	    case WM_LBUTTONDOWN:
+		evt.what = EVT_MOUSEDOWN;
+		evt.message = EVT_LEFTBMASK;
+		break;
+	    case WM_LBUTTONUP:
+		evt.what = EVT_MOUSEUP;
+		evt.message = EVT_LEFTBMASK;
+		break;
+	    case WM_RBUTTONDBLCLK:
+		evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK;
+		evt.message = EVT_RIGHTBMASK;
+		break;
+	    case WM_RBUTTONDOWN:
+		evt.what = EVT_MOUSEDOWN;
+		evt.message = EVT_RIGHTBMASK;
+		break;
+	    case WM_RBUTTONUP:
+		evt.what = EVT_MOUSEUP;
+		evt.message = EVT_RIGHTBMASK;
+		break;
+	    case WM_MBUTTONDBLCLK:
+		evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK;
+		evt.message = EVT_MIDDLEBMASK;
+		break;
+	    case WM_MBUTTONDOWN:
+		evt.what = EVT_MOUSEDOWN;
+		evt.message = EVT_MIDDLEBMASK;
+		break;
+	    case WM_MBUTTONUP:
+		evt.what = EVT_MOUSEUP;
+		evt.message = EVT_MIDDLEBMASK;
+		break;
+	    case WM_KEYDOWN:
+	    case WM_SYSKEYDOWN:
+		if (HIWORD(msg.lParam) & KF_REPEAT) {
+		    evt.what = EVT_KEYREPEAT;
+		    }
+		else {
+		    evt.what = EVT_KEYDOWN;
+		    }
+		break;
+	    case WM_KEYUP:
+	    case WM_SYSKEYUP:
+		evt.what = EVT_KEYUP;
+		break;
+	    }
+
+	/* Convert mouse event modifier flags */
+	if (evt.what & EVT_MOUSEEVT) {
+	    if (_PM_deskX) {
+		evt.where_x = ((long)msg.pt.x * rangeX) / _PM_deskX;
+		evt.where_y = ((long)msg.pt.y * rangeY) / _PM_deskY;
+		}
+	    else {
+		ScreenToClient(_PM_hwndConsole, &msg.pt);
+		evt.where_x = msg.pt.x;
+		evt.where_y = msg.pt.y;
+		}
+	    if (evt.what == EVT_MOUSEMOVE) {
+		/* Save the current mouse position */
+		EVT.mx = evt.where_x;
+		EVT.my = evt.where_y;
+		if (EVT.oldMove != -1) {
+		    EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one  */
+		    EVT.evtq[EVT.oldMove].where_y = evt.where_y;
+/*                  EVT.evtq[EVT.oldMove].relative_x += mickeyX;    // TODO! */
+/*                  EVT.evtq[EVT.oldMove].relative_y += mickeyY;    // TODO! */
+		    evt.what = 0;
+		    }
+		else {
+		    EVT.oldMove = EVT.freeHead; /* Save id of this move event   */
+/*                  evt.relative_x = mickeyX;    // TODO! */
+/*                  evt.relative_y = mickeyY;    // TODO! */
+		    }
+		}
+	    else
+		EVT.oldMove = -1;
+	    if (msg.wParam & MK_LBUTTON)
+		evt.modifiers |= EVT_LEFTBUT;
+	    if (msg.wParam & MK_RBUTTON)
+		evt.modifiers |= EVT_RIGHTBUT;
+	    if (msg.wParam & MK_MBUTTON)
+		evt.modifiers |= EVT_MIDDLEBUT;
+	    if (msg.wParam & MK_SHIFT)
+		evt.modifiers |= EVT_SHIFTKEY;
+	    if (msg.wParam & MK_CONTROL)
+		evt.modifiers |= EVT_CTRLSTATE;
+	    }
+
+	/* Convert keyboard codes */
+	TranslateMessage(&msg);
+	if (evt.what & EVT_KEYEVT) {
+	    int scanCode = (msg.lParam >> 16) & 0xFF;
+	    if (evt.what == EVT_KEYUP) {
+		/* Get message for keyup code from table of cached down values */
+		evt.message = keyUpMsg[scanCode];
+		keyUpMsg[scanCode] = 0;
+		}
+	    else {
+		if (PeekMessage(&charMsg,NULL,WM_CHAR,WM_CHAR,PM_REMOVE))
+		    evt.message = charMsg.wParam;
+		if (PeekMessage(&charMsg,NULL,WM_SYSCHAR,WM_SYSCHAR,PM_REMOVE))
+		    evt.message = charMsg.wParam;
+		evt.message |= ((msg.lParam >> 8) & 0xFF00);
+		keyUpMsg[scanCode] = (ushort)evt.message;
+		}
+	    if (evt.what == EVT_KEYREPEAT)
+		evt.message |= (msg.lParam << 16);
+	    if (HIWORD(msg.lParam) & KF_ALTDOWN)
+		evt.modifiers |= EVT_ALTSTATE;
+	    if (GetKeyState(VK_SHIFT) & 0x8000U)
+		evt.modifiers |= EVT_SHIFTKEY;
+	    if (GetKeyState(VK_CONTROL) & 0x8000U)
+		evt.modifiers |= EVT_CTRLSTATE;
+	    EVT.oldMove = -1;
+	    }
+
+	if (evt.what != 0) {
+	    /* Add time stamp and add the event to the queue */
+	    evt.when = msg.time;
+	    if (EVT.count < EVENTQSIZE)
+		addEvent(&evt);
+	    }
+	DispatchMessage(&msg);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort(
+    int signal)
+{
+    (void)signal;
+    EVT_exit();
+    PM_fatalError("Unhandled exception!");
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+void EVTAPI EVT_init(
+    _EVT_mouseMoveHandler mouseMove)
+{
+    /* Initialise the event queue */
+    EVT.mouseMove = mouseMove;
+    initEventQueue();
+    memset(keyUpMsg,0,sizeof(keyUpMsg));
+
+    /* Catch program termination signals so we can clean up properly */
+    signal(SIGABRT, _EVT_abort);
+    signal(SIGFPE, _EVT_abort);
+    signal(SIGINT, _EVT_abort);
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    rangeX = xRes;
+    rangeY = yRes;
+}
+
+/****************************************************************************
+REMARKS
+Modifes the mouse coordinates as necessary if scaling to OS coordinates,
+and sets the OS mouse cursor position.
+****************************************************************************/
+void _EVT_setMousePos(
+    int *x,
+    int *y)
+{
+    /* Scale coordinates up to desktop coordinates first */
+    int scaledX = (*x * _PM_deskX) / rangeX;
+    int scaledY = (*y * _PM_deskY) / rangeY;
+
+    /* Scale coordinates back to screen coordinates again */
+    *x = (scaledX * rangeX) / _PM_deskX;
+    *y = (scaledY * rangeY) / _PM_deskY;
+    SetCursorPos(scaledX,scaledY);
+}
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for Win32 */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for Win32 */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+    /* Restore signal handlers */
+    signal(SIGABRT, SIG_DFL);
+    signal(SIGFPE, SIG_DFL);
+    signal(SIGINT, SIG_DFL);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns the mask indicating what joystick axes are attached.
+
+HEADER:
+event.h
+
+REMARKS:
+This function is used to detect the attached joysticks, and determine
+what axes are present and functioning. This function will re-detect any
+attached joysticks when it is called, so if the user forgot to attach
+the joystick when the application started, you can call this function to
+re-detect any newly attached joysticks.
+
+SEE ALSO:
+EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent
+****************************************************************************/
+int EVTAPI EVT_joyIsPresent(void)
+{
+    /* TODO: Implement joystick code based on DirectX! */
+    return 0;
+}
+
+/****************************************************************************
+DESCRIPTION:
+Polls the joystick for position and button information.
+
+HEADER:
+event.h
+
+REMARKS:
+This routine is used to poll analogue joysticks for button and position
+information. It should be called once for each main loop of the user
+application, just before processing all pending events via EVT_getNext.
+All information polled from the joystick will be posted to the event
+queue for later retrieval.
+
+Note:   Most analogue joysticks will provide readings that change even
+	though the joystick has not moved. Hence if you call this routine
+	you will likely get an EVT_JOYMOVE event every time through your
+	event loop.
+
+SEE ALSO:
+EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight,
+EVT_joySetCenter, EVT_joyIsPresent
+****************************************************************************/
+void EVTAPI EVT_pollJoystick(void)
+{
+}
+
+/****************************************************************************
+DESCRIPTION:
+Calibrates the joystick upper left position
+
+HEADER:
+event.h
+
+REMARKS:
+This function can be used to zero in on better joystick calibration factors,
+which may work better than the default simplistic calibration (which assumes
+the joystick is centered when the event library is initialised).
+To use this function, ask the user to hold the stick in the upper left
+position and then have them press a key or button. and then call this
+function. This function will then read the joystick and update the
+calibration factors.
+
+Usually, assuming that the stick was centered when the event library was
+initialized, you really only need to call EVT_joySetLowerRight since the
+upper left position is usually always 0,0 on most joysticks. However, the
+safest procedure is to call all three calibration functions.
+
+SEE ALSO:
+EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent
+****************************************************************************/
+void EVTAPI EVT_joySetUpperLeft(void)
+{
+}
+
+/****************************************************************************
+DESCRIPTION:
+Calibrates the joystick lower right position
+
+HEADER:
+event.h
+
+REMARKS:
+This function can be used to zero in on better joystick calibration factors,
+which may work better than the default simplistic calibration (which assumes
+the joystick is centered when the event library is initialised).
+To use this function, ask the user to hold the stick in the lower right
+position and then have them press a key or button. and then call this
+function. This function will then read the joystick and update the
+calibration factors.
+
+Usually, assuming that the stick was centered when the event library was
+initialized, you really only need to call EVT_joySetLowerRight since the
+upper left position is usually always 0,0 on most joysticks. However, the
+safest procedure is to call all three calibration functions.
+
+SEE ALSO:
+EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent
+****************************************************************************/
+void EVTAPI EVT_joySetLowerRight(void)
+{
+}
+
+/****************************************************************************
+DESCRIPTION:
+Calibrates the joystick center position
+
+HEADER:
+event.h
+
+REMARKS:
+This function can be used to zero in on better joystick calibration factors,
+which may work better than the default simplistic calibration (which assumes
+the joystick is centered when the event library is initialised).
+To use this function, ask the user to hold the stick in the center
+position and then have them press a key or button. and then call this
+function. This function will then read the joystick and update the
+calibration factors.
+
+Usually, assuming that the stick was centered when the event library was
+initialized, you really only need to call EVT_joySetLowerRight since the
+upper left position is usually always 0,0 on most joysticks. However, the
+safest procedure is to call all three calibration functions.
+
+SEE ALSO:
+EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter
+****************************************************************************/
+void EVTAPI EVT_joySetCenter(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c
new file mode 100755
index 0000000..59d9aa0
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c
@@ -0,0 +1,258 @@
+/****************************************************************************
+*
+*                         SciTech Display Doctor
+*
+*               Copyright (C) 1991-2001 SciTech Software, Inc.
+*                            All rights reserved.
+*
+*  ======================================================================
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  |                                                                    |
+*  |This copyrighted computer code is a proprietary trade secret of     |
+*  |SciTech Software, Inc., located at 505 Wall Street, Chico, CA 95928 |
+*  |USA (www.scitechsoft.com).  ANY UNAUTHORIZED POSSESSION, USE,       |
+*  |VIEWING, COPYING, MODIFICATION OR DISSEMINATION OF THIS CODE IS     |
+*  |STRICTLY PROHIBITED BY LAW.  Unless you have current, express       |
+*  |written authorization from SciTech to possess or use this code, you |
+*  |may be subject to civil and/or criminal penalties.                  |
+*  |                                                                    |
+*  |If you received this code in error or you would like to report      |
+*  |improper use, please immediately contact SciTech Software, Inc. at  |
+*  |530-894-8400.                                                       |
+*  |                                                                    |
+*  |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW|
+*  ======================================================================
+*
+* Language:     ANSI C
+* Environment:  Windows NT, Windows 2K or Windows XP.
+*
+* Description:  Main module to do the installation of the SDD and GLDirect
+*               device driver components under Windows NT/2K/XP.
+*
+****************************************************************************/
+
+#include "pmapi.h"
+#include "win32/oshdr.h"
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+szDriverName    - Actual name of the driver to install in the system
+szServiceName   - Name of the service to create
+szLoadGroup     - Load group for the driver (NULL for normal drivers)
+dwServiceType   - Service type to create
+
+RETURNS:
+True on success, false on failure.
+
+REMARKS:
+This function does all the work to install the driver into the system.
+The driver is not however activated; for that you must use the Start_SddFilt
+function.
+****************************************************************************/
+ulong PMAPI PM_installService(
+    const char *szDriverName,
+    const char *szServiceName,
+    const char *szLoadGroup,
+    ulong dwServiceType)
+{
+    SC_HANDLE   scmHandle;
+    SC_HANDLE   driverHandle;
+    char        szDriverPath[MAX_PATH];
+    HKEY        key;
+    char        keyPath[MAX_PATH];
+    ulong       status;
+
+    /* Obtain a handle to the service control manager requesting all access */
+    if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL)
+	return GetLastError();
+
+    /* Find the path to the driver in system directory */
+    GetSystemDirectory(szDriverPath, sizeof(szDriverPath));
+    strcat(szDriverPath, "\\drivers\\");
+    strcat(szDriverPath, szDriverName);
+
+    /* Create the service with the Service Control Manager. */
+    driverHandle = CreateService(scmHandle,
+				 szServiceName,
+				 szServiceName,
+				 SERVICE_ALL_ACCESS,
+				 dwServiceType,
+				 SERVICE_BOOT_START,
+				 SERVICE_ERROR_NORMAL,
+				 szDriverPath,
+				 szLoadGroup,
+				 NULL,
+				 NULL,
+				 NULL,
+				 NULL);
+
+    /* Check to see if the driver could actually be installed. */
+    if (!driverHandle) {
+	status = GetLastError();
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+
+    /* Get a handle to the key for driver so that it can be altered in the */
+    /* next step. */
+    strcpy(keyPath, "SYSTEM\\CurrentControlSet\\Services\\");
+    strcat(keyPath, szServiceName);
+    if ((status = RegOpenKeyEx(HKEY_LOCAL_MACHINE,keyPath,0,KEY_ALL_ACCESS,&key)) != ERROR_SUCCESS) {
+	/* A problem has occured. Delete the service so that it is not installed. */
+	status = GetLastError();
+	DeleteService(driverHandle);
+	CloseServiceHandle(driverHandle);
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+
+    /* Delete the ImagePath value in the newly created key so that the */
+    /* system looks for the driver in the normal location. */
+    if ((status = RegDeleteValue(key, "ImagePath")) != ERROR_SUCCESS) {
+	/* A problem has occurred. Delete the service so that it is not */
+	/* installed and will not try to start. */
+	RegCloseKey(key);
+	DeleteService(driverHandle);
+	CloseServiceHandle(driverHandle);
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+
+    /* Clean up and exit */
+    RegCloseKey(key);
+    CloseServiceHandle(driverHandle);
+    CloseServiceHandle(scmHandle);
+    return ERROR_SUCCESS;
+}
+
+/****************************************************************************
+PARAMETERS:
+szServiceName   - Name of the service to start
+
+RETURNS:
+True on success, false on failure.
+
+REMARKS:
+This function is used to start the specified service and make it active.
+****************************************************************************/
+ulong PMAPI PM_startService(
+    const char *szServiceName)
+{
+    SC_HANDLE       scmHandle;
+    SC_HANDLE       driverHandle;
+    SERVICE_STATUS	serviceStatus;
+    ulong           status;
+
+    /* Obtain a handle to the service control manager requesting all access */
+    if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL)
+	return GetLastError();
+
+    /* Open the service with the Service Control Manager. */
+    if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) {
+	status = GetLastError();
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+
+    /* Start the service */
+    if (!StartService(driverHandle,0,NULL)) {
+	status = GetLastError();
+	CloseServiceHandle(driverHandle);
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+
+    /* Query the service to make sure it is there */
+    if (!QueryServiceStatus(driverHandle,&serviceStatus)) {
+	status = GetLastError();
+	CloseServiceHandle(driverHandle);
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+    CloseServiceHandle(driverHandle);
+    CloseServiceHandle(scmHandle);
+    return ERROR_SUCCESS;
+}
+
+/****************************************************************************
+PARAMETERS:
+szServiceName   - Name of the service to stop
+
+RETURNS:
+True on success, false on failure.
+
+REMARKS:
+This function is used to stop the specified service and disable it.
+****************************************************************************/
+ulong PMAPI PM_stopService(
+    const char *szServiceName)
+{
+    SC_HANDLE       scmHandle;
+    SC_HANDLE       driverHandle;
+    SERVICE_STATUS	serviceStatus;
+    ulong           status;
+
+    /* Obtain a handle to the service control manager requesting all access */
+    if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL)
+	return GetLastError();
+
+    /* Open the service with the Service Control Manager. */
+    if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) {
+	status = GetLastError();
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+
+    /* Stop the service from running */
+    if (!ControlService(driverHandle, SERVICE_CONTROL_STOP, &serviceStatus)) {
+	status = GetLastError();
+	CloseServiceHandle(driverHandle);
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+    CloseServiceHandle(driverHandle);
+    CloseServiceHandle(scmHandle);
+    return ERROR_SUCCESS;
+}
+
+/****************************************************************************
+PARAMETERS:
+szServiceName   - Name of the service to remove
+
+RETURNS:
+True on success, false on failure.
+
+REMARKS:
+This function is used to remove a service completely from the system.
+****************************************************************************/
+ulong PMAPI PM_removeService(
+    const char *szServiceName)
+{
+    SC_HANDLE   scmHandle;
+    SC_HANDLE   driverHandle;
+    ulong       status;
+
+    /* Obtain a handle to the service control manager requesting all access */
+    if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL)
+	return GetLastError();
+
+    /* Open the service with the Service Control Manager. */
+    if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) {
+	status = GetLastError();
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+
+    /* Remove the service */
+    if (!DeleteService(driverHandle)) {
+	status = GetLastError();
+	CloseServiceHandle(driverHandle);
+	CloseServiceHandle(scmHandle);
+	return status;
+	}
+    CloseServiceHandle(driverHandle);
+    CloseServiceHandle(scmHandle);
+    return ERROR_SUCCESS;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h
new file mode 100755
index 0000000..0c59e90
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h
@@ -0,0 +1,79 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+#define WIN32_LEAN_AND_MEAN
+#define STRICT
+#include <windows.h>
+#include <mmsystem.h>
+#include <float.h>
+#define NONAMELESSUNION
+#include "pm/ddraw.h"
+
+/* Macros to save and restore the default control word. Windows 9x has
+ * some bugs in it such that calls to load any DLL's which load 16-bit
+ * DLL's cause the floating point control word to get trashed. We fix
+ * this by saving and restoring the control word across problematic
+ * calls.
+ */
+
+#if defined(__INTEL__)
+#define GET_DEFAULT_CW()                    \
+{                                           \
+    if (_PM_cw_default == 0)                \
+	_PM_cw_default = _control87(0,0);   \
+}
+#define RESET_DEFAULT_CW()                  \
+    _control87(_PM_cw_default,0xFFFFFFFF)
+#else
+#define GET_DEFAULT_CW()
+#define RESET_DEFAULT_CW()
+#endif
+
+/* Custom window messages */
+
+#define	WM_DO_SUSPEND_APP			WM_USER
+#define	WM_PM_LEAVE_FULLSCREEN	    0
+#define	WM_PM_RESTORE_FULLSCREEN	1
+
+/* Macro for disabling AutoPlay on a use system */
+
+#define AUTOPLAY_DRIVE_CDROM    0x20
+
+/*--------------------------- Global Variables ----------------------------*/
+
+#ifdef  __INTEL__
+extern uint     _PM_cw_default;         /* Default FPU control word     */
+#endif
+extern int      _PM_deskX,_PM_deskY;    /* Desktop dimensions           */
+extern HWND     _PM_hwndConsole;        /* Window handle for console    */
+
+/*-------------------------- Internal Functions ---------------------------*/
+
+void _EVT_pumpMessages(void);
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c b/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c
new file mode 100755
index 0000000..1ffdbcc
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c
@@ -0,0 +1,1459 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32
+*
+* Description:  Implementation for the OS Portability Manager Library, which
+*               contains functions to implement OS specific services in a
+*               generic, cross platform API. Porting the OS Portability
+*               Manager library is the first step to porting any SciTech
+*               products to a new platform.
+*
+****************************************************************************/
+
+#define WIN32_LEAN_AND_MEAN
+#define STRICT
+#include <windows.h>
+#include <mmsystem.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <direct.h>
+#include "pmapi.h"
+#include "drvlib/os/os.h"
+#include "pm_help.h"
+
+/*--------------------------- Global variables ----------------------------*/
+
+ibool           _PM_haveWinNT;      /* True if we are running on NT     */
+static uint     VESABuf_len = 1024; /* Length of the VESABuf buffer     */
+static void     *VESABuf_ptr = NULL;/* Near pointer to VESABuf          */
+static uint     VESABuf_rseg;       /* Real mode segment of VESABuf     */
+static uint     VESABuf_roff;       /* Real mode offset of VESABuf      */
+HANDLE          _PM_hDevice = NULL; /* Handle to Win32 VxD              */
+static ibool    inited = false;     /* Flags if we are initialised      */
+static void     (PMAPIP fatalErrorCleanup)(void) = NULL;
+
+static char *szMachineNameKey   = "System\\CurrentControlSet\\control\\ComputerName\\ComputerName";
+static char *szMachineNameKeyNT = "System\\CurrentControlSet\\control\\ComputerName\\ActiveComputerName";
+static char *szMachineName      = "ComputerName";
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* Macro to check for a valid, loaded version of PMHELP. We check this
+ * on demand when we need these services rather than when PM_init() is
+ * called because if we are running on DirectDraw we don't need PMHELP.VXD.
+ */
+
+#define CHECK_FOR_PMHELP()                                                  \
+{                                                                           \
+    if (_PM_hDevice == INVALID_HANDLE_VALUE)                                \
+	if (_PM_haveWinNT)                                                  \
+	    PM_fatalError("Unable to connect to PMHELP.SYS or SDDHELP.SYS!"); \
+	else                                                                  \
+	    PM_fatalError("Unable to connect to PMHELP.VXD or SDDHELP.VXD!"); \
+}
+
+/****************************************************************************
+REMARKS:
+Initialise the PM library and connect to our helper device driver. If we
+cannot connect to our helper device driver, we bail out with an error
+message. Our Windows 9x VxD is dynamically loadable, so it can be loaded
+after the system has started.
+****************************************************************************/
+void PMAPI PM_init(void)
+{
+    DWORD   inBuf[1];   /* Buffer to receive data from VxD  */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+    char    cntPath[PM_MAX_PATH];
+    char    *env;
+
+    /* Create a file handle for the static VxD if possible, otherwise
+     * dynamically load the PMHELP helper VxD. Note that if an old version
+     * of SDD is loaded, we use the PMHELP VxD instead.
+     */
+    if (!inited) {
+	/* Determine if we are running under Windows NT or not and
+	 * set the global OS type variable.
+	 */
+	_PM_haveWinNT = false;
+	if ((GetVersion() & 0x80000000UL) == 0)
+	    _PM_haveWinNT = true;
+	___drv_os_type = (_PM_haveWinNT) ? _OS_WINNT : _OS_WIN95;
+
+	/* Now try to connect to SDDHELP.VXD or SDDHELP.SYS */
+	_PM_hDevice = CreateFile(SDDHELP_MODULE_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0);
+	if (_PM_hDevice != INVALID_HANDLE_VALUE) {
+	    if (!DeviceIoControl(_PM_hDevice, PMHELP_GETVER32, NULL, 0,
+		    outBuf, sizeof(outBuf), &count, NULL) || outBuf[0] < PMHELP_VERSION) {
+		/* Old version of SDDHELP loaded, so use PMHELP instead */
+		CloseHandle(_PM_hDevice);
+		_PM_hDevice = INVALID_HANDLE_VALUE;
+		}
+	    }
+	if (_PM_hDevice == INVALID_HANDLE_VALUE) {
+	    /* First try to see if there is a currently loaded PMHELP driver.
+	     * This is usually the case when we are running under Windows NT/2K.
+	     */
+	    _PM_hDevice = CreateFile(PMHELP_MODULE_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0);
+	    if (_PM_hDevice == INVALID_HANDLE_VALUE) {
+		/* The driver was not staticly loaded, so try creating a file handle
+		 * to a dynamic version of the VxD if possible. Note that on WinNT/2K we
+		 * cannot support dynamically loading the drivers.
+		 */
+		_PM_hDevice = CreateFile(PMHELP_VXD_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0);
+		}
+	    }
+	if (_PM_hDevice != INVALID_HANDLE_VALUE) {
+	    /* Call the driver to determine the version number */
+	    if (!DeviceIoControl(_PM_hDevice, PMHELP_GETVER32, inBuf, sizeof(inBuf),
+		    outBuf, sizeof(outBuf), &count, NULL) || outBuf[0] < PMHELP_VERSION) {
+		if (_PM_haveWinNT)
+		    PM_fatalError("Older version of PMHELP.SYS found!");
+		else
+		    PM_fatalError("Older version of PMHELP.VXD found!");
+		}
+
+	    /* Now set the current path inside the VxD so it knows what the
+	     * current directory is for loading Nucleus drivers.
+	     */
+	    inBuf[0] = (ulong)PM_getCurrentPath(cntPath,sizeof(cntPath));
+	    if (!DeviceIoControl(_PM_hDevice, PMHELP_SETCNTPATH32, inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &count, NULL))
+		PM_fatalError("Unable to set VxD current path!");
+
+	    /* Now pass down the NUCLEUS_PATH environment variable to the device
+	     * driver so it can use this value if it is found.
+	     */
+	    if ((env = getenv("NUCLEUS_PATH")) != NULL) {
+		inBuf[0] = (ulong)env;
+		if (!DeviceIoControl(_PM_hDevice, PMHELP_SETNUCLEUSPATH32, inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &count, NULL))
+		    PM_fatalError("Unable to set VxD Nucleus path!");
+		}
+
+	    /* Enable IOPL for ring-3 code by default if driver is present */
+	    if (_PM_haveWinNT)
+		PM_setIOPL(3);
+	    }
+
+	/* Indicate that we have been initialised */
+	inited = true;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+We do have BIOS access under Windows 9x, but not under Windows NT.
+****************************************************************************/
+int PMAPI PM_setIOPL(
+    int iopl)
+{
+    DWORD       inBuf[1];   /* Buffer to receive data from VxD  */
+    DWORD       outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD       count;      /* Count of bytes returned from VxD */
+    static int  cntIOPL = 0;
+    int         oldIOPL = cntIOPL;
+
+    /* Enable I/O by adjusting the I/O permissions map on Windows NT */
+    if (_PM_haveWinNT) {
+	CHECK_FOR_PMHELP();
+	if (iopl == 3)
+	    DeviceIoControl(_PM_hDevice, PMHELP_ENABLERING3IOPL, inBuf, sizeof(inBuf),outBuf, sizeof(outBuf), &count, NULL);
+	else
+	    DeviceIoControl(_PM_hDevice, PMHELP_DISABLERING3IOPL, inBuf, sizeof(inBuf),outBuf, sizeof(outBuf), &count, NULL);
+	cntIOPL = iopl;
+	return oldIOPL;
+	}
+
+    /* We always have IOPL on Windows 9x */
+    return 3;
+}
+
+/****************************************************************************
+REMARKS:
+We do have BIOS access under Windows 9x, but not under Windows NT.
+****************************************************************************/
+ibool PMAPI PM_haveBIOSAccess(void)
+{
+    if (PM_getOSType() == _OS_WINNT)
+	return false;
+    else
+	return _PM_hDevice != INVALID_HANDLE_VALUE;
+}
+
+/****************************************************************************
+REMARKS:
+Return the operating system type identifier.
+****************************************************************************/
+long PMAPI PM_getOSType(void)
+{
+    if ((GetVersion() & 0x80000000UL) == 0)
+	return ___drv_os_type = _OS_WINNT;
+    else
+	return ___drv_os_type = _OS_WIN95;
+}
+
+/****************************************************************************
+REMARKS:
+Return the runtime type identifier.
+****************************************************************************/
+int PMAPI PM_getModeType(void)
+{
+    return PM_386;
+}
+
+/****************************************************************************
+REMARKS:
+Add a file directory separator to the end of the filename.
+****************************************************************************/
+void PMAPI PM_backslash(
+    char *s)
+{
+    uint pos = strlen(s);
+    if (s[pos-1] != '\\') {
+	s[pos] = '\\';
+	s[pos+1] = '\0';
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Add a user defined PM_fatalError cleanup function.
+****************************************************************************/
+void PMAPI PM_setFatalErrorCleanup(
+    void (PMAPIP cleanup)(void))
+{
+    fatalErrorCleanup = cleanup;
+}
+
+/****************************************************************************
+REMARKS:
+Report a fatal error condition and halt the program.
+****************************************************************************/
+void PMAPI PM_fatalError(
+    const char *msg)
+{
+    if (fatalErrorCleanup)
+	fatalErrorCleanup();
+    MessageBox(NULL,msg,"Fatal Error!", MB_ICONEXCLAMATION);
+    exit(1);
+}
+
+/****************************************************************************
+REMARKS:
+Allocate the real mode VESA transfer buffer for communicating with the BIOS.
+****************************************************************************/
+void * PMAPI PM_getVESABuf(
+    uint *len,
+    uint *rseg,
+    uint *roff)
+{
+    DWORD   outBuf[4];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    /* We require the helper VxD to be loaded staticly in order to support
+     * the VESA transfer buffer. We do not support dynamically allocating
+     * real mode memory buffers from Win32 programs (we need a 16-bit DLL
+     * for this, and Windows 9x becomes very unstable if you free the
+     * memory blocks out of order).
+     */
+    if (!inited)
+	PM_init();
+    if (!VESABuf_ptr) {
+	CHECK_FOR_PMHELP();
+	if (DeviceIoControl(_PM_hDevice, PMHELP_GETVESABUF32, NULL, 0,
+		outBuf, sizeof(outBuf), &count, NULL)) {
+	    if (!outBuf[0])
+		return NULL;
+	    VESABuf_ptr = (void*)outBuf[0];
+	    VESABuf_len = outBuf[1];
+	    VESABuf_rseg = outBuf[2];
+	    VESABuf_roff = outBuf[3];
+	    }
+	}
+    *len = VESABuf_len;
+    *rseg = VESABuf_rseg;
+    *roff = VESABuf_roff;
+    return VESABuf_ptr;
+}
+
+/****************************************************************************
+REMARKS:
+Check if a key has been pressed.
+****************************************************************************/
+int PMAPI PM_kbhit(void)
+{
+    /* Not used in Windows */
+    return true;
+}
+
+/****************************************************************************
+REMARKS:
+Wait for and return the next keypress.
+****************************************************************************/
+int PMAPI PM_getch(void)
+{
+    /* Not used in Windows */
+    return 0xD;
+}
+
+/****************************************************************************
+REMARKS:
+Set the location of the OS console cursor.
+****************************************************************************/
+void PM_setOSCursorLocation(
+    int x,
+    int y)
+{
+    /* Nothing to do for Windows */
+    (void)x;
+    (void)y;
+}
+
+/****************************************************************************
+REMARKS:
+Set the width of the OS console.
+****************************************************************************/
+void PM_setOSScreenWidth(
+    int width,
+    int height)
+{
+    /* Nothing to do for Windows */
+    (void)width;
+    (void)height;
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock handler (used for software stereo modes).
+****************************************************************************/
+ibool PMAPI PM_setRealTimeClockHandler(
+    PM_intHandler ih,
+    int frequency)
+{
+    /* We do not support this from Win32 programs. Rather the VxD handles
+     * this stuff it will take care of hooking the stereo flip functions at
+     * the VxD level.
+     */
+    (void)ih;
+    (void)frequency;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Set the real time clock frequency (for stereo modes).
+****************************************************************************/
+void PMAPI PM_setRealTimeClockFrequency(
+    int frequency)
+{
+    /* Not supported under Win32 */
+    (void)frequency;
+}
+
+/****************************************************************************
+REMARKS:
+Restore the original real time clock handler.
+****************************************************************************/
+void PMAPI PM_restoreRealTimeClockHandler(void)
+{
+    /* Not supported under Win32 */
+}
+
+/****************************************************************************
+REMARKS:
+Return the current operating system path or working directory.
+****************************************************************************/
+char * PMAPI PM_getCurrentPath(
+    char *path,
+    int maxLen)
+{
+    return getcwd(path,maxLen);
+}
+
+/****************************************************************************
+REMARKS:
+Query a string from the registry (extended version).
+****************************************************************************/
+static ibool REG_queryStringEx(
+    HKEY hKey,
+    const char *szValue,
+    char *value,
+    ulong size)
+{
+    DWORD   type;
+
+    if (RegQueryValueEx(hKey,(PCHAR)szValue,(PDWORD)NULL,(PDWORD)&type,(LPBYTE)value,(PDWORD)&size) == ERROR_SUCCESS)
+	return true;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Query a string from the registry.
+****************************************************************************/
+static ibool REG_queryString(
+    const char *szKey,
+    const char *szValue,
+    char *value,
+    DWORD size)
+{
+    HKEY    hKey;
+    ibool   status = false;
+
+    memset(value,0,sizeof(value));
+    if (RegOpenKey(HKEY_LOCAL_MACHINE,szKey,&hKey) == ERROR_SUCCESS) {
+	status = REG_queryStringEx(hKey,szValue,value,size);
+	RegCloseKey(hKey);
+	}
+    return status;
+}
+
+/****************************************************************************
+REMARKS:
+Return the drive letter for the boot drive.
+****************************************************************************/
+char PMAPI PM_getBootDrive(void)
+{
+    static char path[256];
+    GetSystemDirectory(path,sizeof(path));
+    return path[0];
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the VBE/AF driver files.
+****************************************************************************/
+const char * PMAPI PM_getVBEAFPath(void)
+{
+    return "c:\\";
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus driver files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusPath(void)
+{
+    static char path[256];
+    char        *env;
+
+    if ((env = getenv("NUCLEUS_PATH")) != NULL)
+	return env;
+    GetSystemDirectory(path,sizeof(path));
+    strcat(path,"\\nucleus");
+    return path;
+}
+
+/****************************************************************************
+REMARKS:
+Return the path to the Nucleus configuration files.
+****************************************************************************/
+const char * PMAPI PM_getNucleusConfigPath(void)
+{
+    static char path[256];
+    strcpy(path,PM_getNucleusPath());
+    PM_backslash(path);
+    strcat(path,"config");
+    return path;
+}
+
+/****************************************************************************
+REMARKS:
+Return a unique identifier for the machine if possible.
+****************************************************************************/
+const char * PMAPI PM_getUniqueID(void)
+{
+    return PM_getMachineName();
+}
+
+/****************************************************************************
+REMARKS:
+Get the name of the machine on the network.
+****************************************************************************/
+const char * PMAPI PM_getMachineName(void)
+{
+    static char name[256];
+
+    if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name)))
+	return name;
+    if (REG_queryString(szMachineNameKeyNT,szMachineName,name,sizeof(name)))
+	return name;
+    return "Unknown";
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to the real mode BIOS data area.
+****************************************************************************/
+void * PMAPI PM_getBIOSPointer(void)
+{
+    if (_PM_haveWinNT) {
+	/* On Windows NT we have to map it physically directly */
+	    return PM_mapPhysicalAddr(0x400, 0x1000, true);
+	}
+    else {
+	/* For Windows 9x we can access this memory directly */
+	return (void*)0x400;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Return a pointer to 0xA0000 physical VGA graphics framebuffer.
+****************************************************************************/
+void * PMAPI PM_getA0000Pointer(void)
+{
+    if (_PM_haveWinNT) {
+	/* On Windows NT we have to map it physically directly */
+	    return PM_mapPhysicalAddr(0xA0000, 0x0FFFF, false);
+	}
+    else {
+	/* Always use the 0xA0000 linear address so that we will use
+	 * whatever page table mappings are set up for us (ie: for virtual
+	 * bank switching.
+	 */
+	return (void*)0xA0000;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Map a physical address to a linear address in the callers process.
+****************************************************************************/
+void * PMAPI PM_mapPhysicalAddr(
+    ulong base,
+    ulong limit,
+    ibool isCached)
+{
+    DWORD   inBuf[3];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = base;
+    inBuf[1] = limit;
+    inBuf[2] = isCached;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_MAPPHYS32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return (void*)outBuf[0];
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a physical address mapping allocated by PM_mapPhysicalAddr.
+****************************************************************************/
+void PMAPI PM_freePhysicalAddr(
+    void *ptr,
+    ulong limit)
+{
+    /* We never free the mappings under Win32 (the VxD tracks them and
+     * reissues the same mappings until the system is rebooted).
+     */
+    (void)ptr;
+    (void)limit;
+}
+
+/****************************************************************************
+REMARKS:
+Find the physical address of a linear memory address in current process.
+****************************************************************************/
+ulong PMAPI PM_getPhysicalAddr(
+    void *p)
+{
+    DWORD   inBuf[1];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = (ulong)p;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_GETPHYSICALADDR32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return 0xFFFFFFFFUL;
+}
+
+/****************************************************************************
+REMARKS:
+Find the physical address of a linear memory address in current process.
+****************************************************************************/
+ibool PMAPI PM_getPhysicalAddrRange(
+    void *p,
+    ulong length,
+    ulong *physAddress)
+{
+    DWORD   inBuf[3];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = (ulong)p;
+    inBuf[1] = (ulong)length;
+    inBuf[2] = (ulong)physAddress;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_GETPHYSICALADDRRANGE32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Sleep for the specified number of milliseconds.
+****************************************************************************/
+void PMAPI PM_sleep(
+    ulong milliseconds)
+{
+    Sleep(milliseconds);
+}
+
+/****************************************************************************
+REMARKS:
+Return the base I/O port for the specified COM port.
+****************************************************************************/
+int PMAPI PM_getCOMPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3F8;
+	case 1: return 0x2F8;
+	case 2: return 0x3E8;
+	case 3: return 0x2E8;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Return the base I/O port for the specified LPT port.
+****************************************************************************/
+int PMAPI PM_getLPTPort(int port)
+{
+    /* TODO: Re-code this to determine real values using the Plug and Play */
+    /*       manager for the OS. */
+    switch (port) {
+	case 0: return 0x3BC;
+	case 1: return 0x378;
+	case 2: return 0x278;
+	}
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of shared memory. For Win9x we allocate shared memory
+as locked, global memory that is accessible from any memory context
+(including interrupt time context), which allows us to load our important
+data structure and code such that we can access it directly from a ring
+0 interrupt context.
+****************************************************************************/
+void * PMAPI PM_mallocShared(
+    long size)
+{
+    DWORD   inBuf[1];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    inBuf[0] = size;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_MALLOCSHARED32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return (void*)outBuf[0];
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of shared memory.
+****************************************************************************/
+void PMAPI PM_freeShared(
+    void *ptr)
+{
+    DWORD   inBuf[1];   /* Buffer to send data to VxD       */
+
+    inBuf[0] = (ulong)ptr;
+    CHECK_FOR_PMHELP();
+    DeviceIoControl(_PM_hDevice, PMHELP_FREESHARED32, inBuf, sizeof(inBuf), NULL, 0, NULL, NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Map a linear memory address to the calling process address space. The
+address will have been allocated in another process using the
+PM_mapPhysicalAddr function.
+****************************************************************************/
+void * PMAPI PM_mapToProcess(
+    void *base,
+    ulong limit)
+{
+    (void)base;
+    (void)limit;
+    return base;
+}
+
+/****************************************************************************
+REMARKS:
+Map a real mode pointer to a protected mode pointer.
+****************************************************************************/
+void * PMAPI PM_mapRealPointer(
+    uint r_seg,
+    uint r_off)
+{
+    return (void*)(MK_PHYS(r_seg,r_off));
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of real mode memory
+****************************************************************************/
+void * PMAPI PM_allocRealSeg(
+    uint size,
+    uint *r_seg,
+    uint *r_off)
+{
+    /* We do not support dynamically allocating real mode memory buffers
+     * from Win32 programs (we need a 16-bit DLL for this, and Windows
+     * 9x becomes very unstable if you free the memory blocks out of order).
+     */
+    (void)size;
+    (void)r_seg;
+    (void)r_off;
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of real mode memory.
+****************************************************************************/
+void PMAPI PM_freeRealSeg(
+    void *mem)
+{
+    /* Not supported in Windows */
+    (void)mem;
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt (parameters in DPMI compatible structure)
+****************************************************************************/
+void PMAPI DPMI_int86(
+    int intno,
+    DPMI_regs *regs)
+{
+    DWORD   inBuf[2];   /* Buffer to send data to VxD       */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = intno;
+    inBuf[1] = (ulong)regs;
+    CHECK_FOR_PMHELP();
+    DeviceIoControl(_PM_hDevice, PMHELP_DPMIINT8632, inBuf, sizeof(inBuf),
+	NULL, 0, &count, NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt.
+****************************************************************************/
+int PMAPI PM_int86(
+    int intno,
+    RMREGS *in,
+    RMREGS *out)
+{
+    DWORD   inBuf[3];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = intno;
+    inBuf[1] = (ulong)in;
+    inBuf[2] = (ulong)out;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_INT8632, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Issue a real mode interrupt.
+****************************************************************************/
+int PMAPI PM_int86x(
+    int intno,
+    RMREGS *in,
+    RMREGS *out,
+    RMSREGS *sregs)
+{
+    DWORD   inBuf[4];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = intno;
+    inBuf[1] = (ulong)in;
+    inBuf[2] = (ulong)out;
+    inBuf[3] = (ulong)sregs;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_INT86X32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Call a real mode far function.
+****************************************************************************/
+void PMAPI PM_callRealMode(
+    uint seg,
+    uint off,
+    RMREGS *in,
+    RMSREGS *sregs)
+{
+    DWORD   inBuf[4];   /* Buffer to send data to VxD       */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = seg;
+    inBuf[1] = off;
+    inBuf[2] = (ulong)in;
+    inBuf[3] = (ulong)sregs;
+    CHECK_FOR_PMHELP();
+    DeviceIoControl(_PM_hDevice, PMHELP_CALLREALMODE32, inBuf, sizeof(inBuf),
+	NULL, 0, &count, NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Return the amount of available memory.
+****************************************************************************/
+void PMAPI PM_availableMemory(
+    ulong *physical,
+    ulong *total)
+{
+    /* We don't support this under Win32 at the moment */
+    *physical = *total = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Allocate a block of locked, physical memory for DMA operations.
+****************************************************************************/
+void * PMAPI PM_allocLockedMem(
+    uint size,
+    ulong *physAddr,
+    ibool contiguous,
+    ibool below16M)
+{
+    DWORD   inBuf[4];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = size;
+    inBuf[1] = (ulong)physAddr;
+    inBuf[2] = (ulong)contiguous;
+    inBuf[3] = (ulong)below16M;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_ALLOCLOCKED32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return (void*)outBuf[0];
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a block of locked physical memory.
+****************************************************************************/
+void PMAPI PM_freeLockedMem(
+    void *p,
+    uint size,
+    ibool contiguous)
+{
+    DWORD   inBuf[3];   /* Buffer to send data to VxD       */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = (ulong)p;
+    inBuf[1] = size;
+    inBuf[2] = contiguous;
+    CHECK_FOR_PMHELP();
+    DeviceIoControl(_PM_hDevice, PMHELP_FREELOCKED32, inBuf, sizeof(inBuf),
+	NULL, 0, &count, NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Allocates a page aligned and page sized block of memory
+****************************************************************************/
+void * PMAPI PM_allocPage(
+    ibool locked)
+{
+    DWORD   inBuf[2];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = locked;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_ALLOCPAGE32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return (void*)outBuf[0];
+    return NULL;
+}
+
+/****************************************************************************
+REMARKS:
+Free a page aligned and page sized block of memory
+****************************************************************************/
+void PMAPI PM_freePage(
+    void *p)
+{
+    DWORD   inBuf[1];   /* Buffer to send data to VxD       */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = (ulong)p;
+    CHECK_FOR_PMHELP();
+    DeviceIoControl(_PM_hDevice, PMHELP_FREEPAGE32, inBuf, sizeof(inBuf),
+	NULL, 0, &count, NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    DWORD   inBuf[2];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    inBuf[0] = (ulong)p;
+    inBuf[1] = len;
+    inBuf[2] = (ulong)lh;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_LOCKDATAPAGES32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh)
+{
+    DWORD   inBuf[2];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    inBuf[0] = (ulong)p;
+    inBuf[1] = len;
+    inBuf[2] = (ulong)lh;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_UNLOCKDATAPAGES32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Lock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    DWORD   inBuf[2];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    inBuf[0] = (ulong)p;
+    inBuf[1] = len;
+    inBuf[2] = (ulong)lh;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_LOCKCODEPAGES32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Unlock linear memory so it won't be paged.
+****************************************************************************/
+int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh)
+{
+    DWORD   inBuf[2];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    inBuf[0] = (ulong)p;
+    inBuf[1] = len;
+    inBuf[2] = (ulong)lh;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_UNLOCKCODEPAGES32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankA(
+    int bank)
+{
+    RMREGS  regs;
+    regs.x.ax = 0x4F05;
+    regs.x.bx = 0x0000;
+    regs.x.dx = bank;
+    PM_int86(0x10,&regs,&regs);
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display banks.
+****************************************************************************/
+void PMAPI PM_setBankAB(
+    int bank)
+{
+    RMREGS  regs;
+    regs.x.ax = 0x4F05;
+    regs.x.bx = 0x0000;
+    regs.x.dx = bank;
+    PM_int86(0x10,&regs,&regs);
+    regs.x.ax = 0x4F05;
+    regs.x.bx = 0x0001;
+    regs.x.dx = bank;
+    PM_int86(0x10,&regs,&regs);
+}
+
+/****************************************************************************
+REMARKS:
+Call the VBE/Core software interrupt to change display start address.
+****************************************************************************/
+void PMAPI PM_setCRTStart(
+    int x,
+    int y,
+    int waitVRT)
+{
+    RMREGS  regs;
+    regs.x.ax = 0x4F07;
+    regs.x.bx = waitVRT;
+    regs.x.cx = x;
+    regs.x.dx = y;
+    PM_int86(0x10,&regs,&regs);
+}
+
+/****************************************************************************
+REMARKS:
+Enable write combining for the memory region.
+****************************************************************************/
+ibool PMAPI PM_enableWriteCombine(
+    ulong base,
+    ulong length,
+    uint type)
+{
+    DWORD   inBuf[3];   /* Buffer to send data to VxD       */
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    if (!inited)
+	PM_init();
+    inBuf[0] = base;
+    inBuf[1] = length;
+    inBuf[2] = type;
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_ENABLELFBCOMB32, inBuf, sizeof(inBuf),
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Get the page directory base register value
+****************************************************************************/
+ulong PMAPI _PM_getPDB(void)
+{
+    DWORD   outBuf[1];  /* Buffer to receive data from VxD  */
+    DWORD   count;      /* Count of bytes returned from VxD */
+
+    CHECK_FOR_PMHELP();
+    if (DeviceIoControl(_PM_hDevice, PMHELP_GETPDB32, NULL, 0,
+	    outBuf, sizeof(outBuf), &count, NULL))
+	return outBuf[0];
+    return 0;
+}
+
+/****************************************************************************
+REMARKS:
+Flush the translation lookaside buffer.
+****************************************************************************/
+void PMAPI PM_flushTLB(void)
+{
+    CHECK_FOR_PMHELP();
+    DeviceIoControl(_PM_hDevice, PMHELP_FLUSHTLB32, NULL, 0, NULL, 0, NULL, NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Execute the POST on the secondary BIOS for a controller.
+****************************************************************************/
+ibool PMAPI PM_doBIOSPOST(
+    ushort axVal,
+    ulong BIOSPhysAddr,
+    void *mappedBIOS,
+    ulong BIOSLen)
+{
+    /* This is never done by Win32 programs, but rather done by the VxD
+     * when the system boots.
+     */
+    (void)axVal;
+    (void)BIOSPhysAddr;
+    (void)mappedBIOS;
+    (void)BIOSLen;
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Load an OS specific shared library or DLL. If the OS does not support
+shared libraries, simply return NULL.
+****************************************************************************/
+PM_MODULE PMAPI PM_loadLibrary(
+    const char *szDLLName)
+{
+    return (PM_MODULE)LoadLibrary(szDLLName);
+}
+
+/****************************************************************************
+REMARKS:
+Get the address of a named procedure from a shared library.
+****************************************************************************/
+void * PMAPI PM_getProcAddress(
+    PM_MODULE hModule,
+    const char *szProcName)
+{
+    return (void*)GetProcAddress((HINSTANCE)hModule,szProcName);
+}
+
+/****************************************************************************
+REMARKS:
+Unload a shared library.
+****************************************************************************/
+void PMAPI PM_freeLibrary(
+    PM_MODULE hModule)
+{
+    FreeLibrary((HINSTANCE)hModule);
+}
+
+/****************************************************************************
+REMARKS:
+Internal function to convert the find data to the generic interface.
+****************************************************************************/
+static void convertFindData(
+    PM_findData *findData,
+    WIN32_FIND_DATA *blk)
+{
+    ulong   dwSize = findData->dwSize;
+
+    memset(findData,0,findData->dwSize);
+    findData->dwSize = dwSize;
+    if (blk->dwFileAttributes & FILE_ATTRIBUTE_READONLY)
+	findData->attrib |= PM_FILE_READONLY;
+    if (blk->dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY)
+	findData->attrib |= PM_FILE_DIRECTORY;
+    if (blk->dwFileAttributes & FILE_ATTRIBUTE_ARCHIVE)
+	findData->attrib |= PM_FILE_ARCHIVE;
+    if (blk->dwFileAttributes & FILE_ATTRIBUTE_HIDDEN)
+	findData->attrib |= PM_FILE_HIDDEN;
+    if (blk->dwFileAttributes & FILE_ATTRIBUTE_SYSTEM)
+	findData->attrib |= PM_FILE_SYSTEM;
+    findData->sizeLo = blk->nFileSizeLow;
+    findData->sizeHi = blk->nFileSizeHigh;
+    strncpy(findData->name,blk->cFileName,PM_MAX_PATH);
+    findData->name[PM_MAX_PATH-1] = 0;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the first file matching a search criteria in a directory.
+****************************************************************************/
+void *PMAPI PM_findFirstFile(
+    const char *filename,
+    PM_findData *findData)
+{
+    WIN32_FIND_DATA blk;
+    HANDLE          hfile;
+
+    if ((hfile = FindFirstFile(filename,&blk)) != INVALID_HANDLE_VALUE) {
+	convertFindData(findData,&blk);
+	return (void*)hfile;
+	}
+    return PM_FILE_INVALID;
+}
+
+/****************************************************************************
+REMARKS:
+Function to find the next file matching a search criteria in a directory.
+****************************************************************************/
+ibool PMAPI PM_findNextFile(
+    void *handle,
+    PM_findData *findData)
+{
+    WIN32_FIND_DATA blk;
+
+    if (FindNextFile((HANDLE)handle,&blk)) {
+	convertFindData(findData,&blk);
+	return true;
+	}
+    return false;
+}
+
+/****************************************************************************
+REMARKS:
+Function to close the find process
+****************************************************************************/
+void PMAPI PM_findClose(
+    void *handle)
+{
+    FindClose((HANDLE)handle);
+}
+
+/****************************************************************************
+REMARKS:
+Function to determine if a drive is a valid drive or not. Under Unix this
+function will return false for anything except a value of 3 (considered
+the root drive, and equivalent to C: for non-Unix systems). The drive
+numbering is:
+
+    1   - Drive A:
+    2   - Drive B:
+    3   - Drive C:
+    etc
+
+****************************************************************************/
+ibool PMAPI PM_driveValid(
+    char drive)
+{
+    char    buf[5];
+    int     type;
+
+    sprintf(buf,"%c:\\", drive);
+    return ((type = GetDriveType(buf)) != 0 && type != 1);
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the current working directory for the specififed drive.
+Under Unix this will always return the current working directory regardless
+of what the value of 'drive' is.
+****************************************************************************/
+void PMAPI PM_getdcwd(
+    int drive,
+    char *dir,
+    int len)
+{
+    /* NT stores the current directory for drive N in the magic environment */
+    /* variable =N: so we simply look for that environment variable. */
+    char envname[4];
+
+    envname[0] = '=';
+    envname[1] = drive - 1 + 'A';
+    envname[2] = ':';
+    envname[3] = '\0';
+    if (GetEnvironmentVariable(envname,dir,len) == 0) {
+	/* The current directory or the drive has not been set yet, so */
+	/* simply set it to the root. */
+	dir[0] = envname[1];
+	dir[1] = ':';
+	dir[2] = '\\';
+	dir[3] = '\0';
+	SetEnvironmentVariable(envname,dir);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Function to change the file attributes for a specific file.
+****************************************************************************/
+void PMAPI PM_setFileAttr(
+    const char *filename,
+    uint attrib)
+{
+    DWORD attr = 0;
+
+    if (attrib & PM_FILE_READONLY)
+	attr |= FILE_ATTRIBUTE_READONLY;
+    if (attrib & PM_FILE_ARCHIVE)
+	attr |= FILE_ATTRIBUTE_ARCHIVE;
+    if (attrib & PM_FILE_HIDDEN)
+	attr |= FILE_ATTRIBUTE_HIDDEN;
+    if (attrib & PM_FILE_SYSTEM)
+	attr |= FILE_ATTRIBUTE_SYSTEM;
+    SetFileAttributes((LPSTR)filename, attr);
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file attributes for a specific file.
+****************************************************************************/
+uint PMAPI PM_getFileAttr(
+    const char *filename)
+{
+    DWORD   attr = GetFileAttributes(filename);
+    uint    attrib = 0;
+
+    if (attr & FILE_ATTRIBUTE_READONLY)
+	attrib |= PM_FILE_READONLY;
+    if (attr & FILE_ATTRIBUTE_ARCHIVE)
+	attrib |= PM_FILE_ARCHIVE;
+    if (attr & FILE_ATTRIBUTE_HIDDEN)
+	attrib |= PM_FILE_HIDDEN;
+    if (attr & FILE_ATTRIBUTE_SYSTEM)
+	attrib |= PM_FILE_SYSTEM;
+    return attrib;
+}
+
+/****************************************************************************
+REMARKS:
+Function to create a directory.
+****************************************************************************/
+ibool PMAPI PM_mkdir(
+    const char *filename)
+{
+    return CreateDirectory(filename,NULL);
+}
+
+/****************************************************************************
+REMARKS:
+Function to remove a directory.
+****************************************************************************/
+ibool PMAPI PM_rmdir(
+    const char *filename)
+{
+    return RemoveDirectory(filename);
+}
+
+/****************************************************************************
+REMARKS:
+Function to get the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_getFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    HFILE       f;
+    OFSTRUCT    of;
+    FILETIME    utcTime,localTime;
+    SYSTEMTIME  sysTime;
+    ibool       status = false;
+
+    of.cBytes = sizeof(of);
+    if ((f = OpenFile(filename,&of,OF_READ)) == HFILE_ERROR)
+	return false;
+    if (!GetFileTime((HANDLE)f,NULL,NULL,&utcTime))
+	goto Exit;
+    if (!gmTime) {
+	if (!FileTimeToLocalFileTime(&utcTime,&localTime))
+	    goto Exit;
+	}
+    else
+	localTime = utcTime;
+    if (!FileTimeToSystemTime(&localTime,&sysTime))
+	goto Exit;
+    time->year = sysTime.wYear;
+    time->mon = sysTime.wMonth-1;
+    time->day = sysTime.wYear;
+    time->hour = sysTime.wHour;
+    time->min = sysTime.wMinute;
+    time->sec = sysTime.wSecond;
+    status = true;
+
+Exit:
+    CloseHandle((HANDLE)f);
+    return status;
+}
+
+/****************************************************************************
+REMARKS:
+Function to set the file time and date for a specific file.
+****************************************************************************/
+ibool PMAPI PM_setFileTime(
+    const char *filename,
+    ibool gmTime,
+    PM_time *time)
+{
+    HFILE       f;
+    OFSTRUCT    of;
+    FILETIME    utcTime,localTime;
+    SYSTEMTIME  sysTime;
+    ibool       status = false;
+
+    of.cBytes = sizeof(of);
+    if ((f = OpenFile(filename,&of,OF_WRITE)) == HFILE_ERROR)
+	return false;
+    sysTime.wYear = time->year;
+    sysTime.wMonth = time->mon+1;
+    sysTime.wYear = time->day;
+    sysTime.wHour = time->hour;
+    sysTime.wMinute = time->min;
+    sysTime.wSecond = time->sec;
+    if (!SystemTimeToFileTime(&sysTime,&localTime))
+	goto Exit;
+    if (!gmTime) {
+	if (!LocalFileTimeToFileTime(&localTime,&utcTime))
+	    goto Exit;
+	}
+    else
+	utcTime = localTime;
+    if (!SetFileTime((HANDLE)f,NULL,NULL,&utcTime))
+	goto Exit;
+    status = true;
+
+Exit:
+    CloseHandle((HANDLE)f);
+    return status;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c
new file mode 100755
index 0000000..70491cd
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c
@@ -0,0 +1,53 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Dummy module; no virtual framebuffer for this OS
+*
+****************************************************************************/
+
+#include "pmapi.h"
+
+ibool PMAPI VF_available(void)
+{
+    return false;
+}
+
+void * PMAPI VF_init(
+    ulong baseAddr,
+    int bankSize,
+    int codeLen,
+    void *bankFunc)
+{
+    (void)baseAddr;
+    (void)bankSize;
+    (void)codeLen;
+    (void)bankFunc;
+    return NULL;
+}
+
+void PMAPI VF_exit(void)
+{
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c
new file mode 100755
index 0000000..5a901a4
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c
@@ -0,0 +1,136 @@
+/****************************************************************************
+*
+*                         Ultra Long Period Timer
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Win32
+*
+* Description:  OS specific implementation for the Zen Timer functions.
+*
+****************************************************************************/
+
+/*---------------------------- Global variables ---------------------------*/
+
+static CPU_largeInteger countFreq;
+static ibool            havePerformanceCounter;
+static ulong            start,finish;
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Initialise the Zen Timer module internals.
+****************************************************************************/
+void __ZTimerInit(void)
+{
+#ifdef  NO_ASSEMBLER
+    havePerformanceCounter = false;
+#else
+    havePerformanceCounter = QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq);
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Start the Zen Timer counting.
+****************************************************************************/
+static void __LZTimerOn(
+    LZTimerObject *tm)
+{
+    if (havePerformanceCounter)
+	QueryPerformanceCounter((LARGE_INTEGER*)&tm->start);
+    else
+	tm->start.low = timeGetTime();
+}
+
+/****************************************************************************
+REMARKS:
+Compute the lap time since the timer was started.
+****************************************************************************/
+static ulong __LZTimerLap(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger    tmLap,tmCount;
+
+    if (havePerformanceCounter) {
+	QueryPerformanceCounter((LARGE_INTEGER*)&tmLap);
+	_CPU_diffTime64(&tm->start,&tmLap,&tmCount);
+	return _CPU_calcMicroSec(&tmCount,countFreq.low);
+	}
+    else {
+	tmLap.low = timeGetTime();
+	return (tmLap.low - tm->start.low) * 1000L;
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Stop the Zen Timer counting.
+****************************************************************************/
+static void __LZTimerOff(
+    LZTimerObject *tm)
+{
+    if (havePerformanceCounter)
+	QueryPerformanceCounter((LARGE_INTEGER*)&tm->end);
+    else
+	tm->end.low = timeGetTime();
+}
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time in microseconds between start and end timings.
+****************************************************************************/
+static ulong __LZTimerCount(
+    LZTimerObject *tm)
+{
+    CPU_largeInteger    tmCount;
+
+    if (havePerformanceCounter) {
+	_CPU_diffTime64(&tm->start,&tm->end,&tmCount);
+	return _CPU_calcMicroSec(&tmCount,countFreq.low);
+	}
+    else
+	return (tm->end.low - tm->start.low) * 1000L;
+}
+
+/****************************************************************************
+REMARKS:
+Define the resolution of the long period timer as microseconds per timer tick.
+****************************************************************************/
+#define ULZTIMER_RESOLUTION     1000
+
+/****************************************************************************
+REMARKS:
+Read the Long Period timer from the OS
+****************************************************************************/
+static ulong __ULZReadTime(void)
+{ return timeGetTime(); }
+
+/****************************************************************************
+REMARKS:
+Compute the elapsed time from the BIOS timer tick. Note that we check to see
+whether a midnight boundary has passed, and if so adjust the finish time to
+account for this. We cannot detect if more that one midnight boundary has
+passed, so if this happens we will be generating erronous results.
+****************************************************************************/
+ulong __ULZElapsedTime(ulong start,ulong finish)
+{ return finish - start; }
diff --git a/board/MAI/bios_emulator/scitech/src/pm/x11/event.c b/board/MAI/bios_emulator/scitech/src/pm/x11/event.c
new file mode 100755
index 0000000..b34bfac
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/x11/event.c
@@ -0,0 +1,307 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Unix / X11
+*
+* Description:  X11 event queue implementation for the MGL.
+*               This can be used both for windowed and fullscreen (DGA) modes.
+*
+****************************************************************************/
+
+/*---------------------------- Global Variables ---------------------------*/
+
+static ushort       keyUpMsg[256] = {0};/* Table of key up messages     */
+static int          rangeX,rangeY;      /* Range of mouse coordinates   */
+
+static Display  *_EVT_dpy;
+static Window    _EVT_win;
+
+typedef struct {
+  int keycode;
+  int scancode;
+} xkeymap;
+
+xkeymap xkeymaps[] = {
+  { 9, KB_esc},
+  {24, KB_Q},
+  {25, KB_W},
+  {26, KB_E},
+  {27, KB_R},
+  {28, KB_T},
+  {29, KB_Y},
+  {30, KB_U},
+  {31, KB_I},
+  {32, KB_O},
+  {33, KB_P},
+};
+
+/*---------------------------- Implementation -----------------------------*/
+
+/* These are not used under non-DOS systems */
+#define _EVT_disableInt()       1
+#define _EVT_restoreInt(flags)
+
+/****************************************************************************
+PARAMETERS:
+scanCode    - Scan code to test
+
+REMARKS:
+This macro determines if a specified key is currently down at the
+time that the call is made.
+****************************************************************************/
+#define _EVT_isKeyDown(scanCode)    (keyUpMsg[scanCode] != 0)
+
+/****************************************************************************
+REMARKS:
+This function is used to return the number of ticks since system
+startup in milliseconds. This should be the same value that is placed into
+the time stamp fields of events, and is used to implement auto mouse down
+events.
+****************************************************************************/
+ulong _EVT_getTicks(void)
+{
+  static unsigned starttime = 0;
+  struct timeval t;
+
+  gettimeofday(&t, NULL);
+  if (starttime == 0)
+    starttime = t.tv_sec * 1000 + (t.tv_usec/1000);
+  return ((t.tv_sec * 1000 + (t.tv_usec/1000)) - starttime);
+}
+
+static int getScancode(int keycode)
+{
+  return keycode-8;
+}
+
+/****************************************************************************
+REMARKS:
+Pumps all messages in the application message queue into our event queue.
+****************************************************************************/
+#ifdef X11_CORE
+static void _EVT_pumpX11Messages(void)
+#else
+static void _EVT_pumpMessages(void)
+#endif
+{
+  /* TODO: The purpose of this function is to read all keyboard and mouse */
+  /*         events from the OS specific event queue, translate them and post */
+  /*         them into the SciTech event queue. */
+  event_t evt;
+  XEvent  ev;
+  static int old_mx = 0, old_my = 0, buts = 0, c;
+  char buf[2];
+
+  while (XPending(_EVT_dpy) && XNextEvent(_EVT_dpy,&ev)) {
+    evt.when = _MGL_getTicks();
+
+    switch(ev.type){
+    case KeyPress:
+      c = getScancode(ev.xkey.keycode);
+      evt.what = EVT_KEYDOWN;
+      evt.message = c << 8;
+      XLookupString(&ev.xkey, buf, 2, NULL, NULL);
+      evt.message |= buf[0];
+      break;
+    case KeyRelease:
+      c = getScancode(ev.xkey.keycode);
+      evt.what = EVT_KEYUP;
+      evt.message = keyUpMsg[c];
+      if(count < EVENTQSIZE)
+	addEvent(&evt);
+      keyUpMsg[c] = 0;
+      repeatKey[c] = 0;
+      break;
+    case ButtonPress:
+      evt.what = EVT_MOUSEDOWN;
+      if(ev.xbutton.button == 1){
+	buts |= EVT_LEFTBUT;
+	evt.message = EVT_LEFTBMASK;
+      }else if(ev.xbutton.button == 2){
+	buts |= EVT_MIDDLEBUT;
+	evt.message = EVT_MIDDLEBMASK;
+      }else if(ev.xbutton.button == 3){
+	buts |= EVT_RIGHTBUT;
+	evt.message = EVT_RIGHTBMASK;
+      }
+      evt.modifiers = modifiers | buts;
+
+      break;
+    case ButtonRelease:
+      evt.what = EVT_MOUSEUP;
+      if(ev.xbutton.button == 1){
+	buts &= ~EVT_LEFTBUT;
+	evt.message = EVT_LEFTBMASK;
+      }else if(ev.xbutton.button == 2){
+	buts &= ~EVT_MIDDLEBUT;
+	evt.message = EVT_MIDDLEBMASK;
+      }else if(ev.xbutton.button == 3){
+	buts &= ~EVT_RIGHTBUT;
+	evt.message = EVT_RIGHTBMASK;
+      }
+      evt.modifiers = modifiers | buts;
+
+      break;
+    case MotionNotify:
+      evt.what = EVT_MOUSEMOVE;
+      evt.where_x = ev.xmotion.x;
+      evt.where_y = ev.xmotion.y;
+      evt.relative_x = evt.where_x - old_mx;
+      evt.relative_y = evt.where_y - old_my;
+      old_mx = evt.where_x;
+      old_my = evt.where_y;
+      break;
+    }
+    if (count < EVENTQSIZE)
+      addEvent(&evt);
+  }
+
+}
+
+/****************************************************************************
+REMARKS:
+This macro/function is used to converts the scan codes reported by the
+keyboard to our event libraries normalised format. We only have one scan
+code for the 'A' key, and use shift modifiers to determine if it is a
+Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way,
+but the OS gives us 'cooked' scan codes, we have to translate them back
+to the raw format.
+****************************************************************************/
+#define _EVT_maskKeyCode(evt)
+
+/****************************************************************************
+REMARKS:
+Safely abort the event module upon catching a fatal error.
+****************************************************************************/
+void _EVT_abort()
+{
+    EVT_exit();
+    PM_fatalError("Unhandled exception!");
+}
+
+/****************************************************************************
+PARAMETERS:
+mouseMove   - Callback function to call wheneve the mouse needs to be moved
+
+REMARKS:
+Initiliase the event handling module. Here we install our mouse handling ISR
+to be called whenever any button's are pressed or released. We also build
+the free list of events in the event queue.
+
+We use handler number 2 of the mouse libraries interrupt handlers for our
+event handling routines.
+****************************************************************************/
+#ifdef X11_CORE
+void EVTAPI EVT_initX11(
+#else
+void EVTAPI EVT_init(
+#endif
+    _EVT_mouseMoveHandler mouseMove)
+{
+  int result, i,j,k;
+  XDeviceInfoPtr    list,slist;
+
+  /* Initialise the event queue */
+  _mouseMove = mouseMove;
+  initEventQueue();
+  memset(keyUpMsg,0,sizeof(keyUpMsg));
+
+
+  /* query server for input extensions */
+  result =XQueryExtension(_EVT_dpy,"XInputExtension",&i,&j,&k);
+  if(!result) {
+    fprintf(stderr,"Your server doesn't support XInput Extensions\n");
+    fprintf(stderr,"X11 Joystick disabled\n");
+  }
+  list = XListInputDevices(_EVT_dpy,&result);
+  if (!list) {
+    fprintf(stderr,"No extended input devices found !!\n");
+    fprintf(stderr,"X11 Joystick disabled\n");
+  }
+
+
+  /* Catch program termination signals so we can clean up properly */
+  signal(SIGABRT, _EVT_abort);
+  signal(SIGFPE, _EVT_abort);
+  signal(SIGINT, _EVT_abort);
+}
+
+/****************************************************************************
+REMARKS
+Changes the range of coordinates returned by the mouse functions to the
+specified range of values. This is used when changing between graphics
+modes set the range of mouse coordinates for the new display mode.
+****************************************************************************/
+void EVTAPI EVT_setMouseRange(
+    int xRes,
+    int yRes)
+{
+    rangeX = xRes;
+    rangeY = yRes;
+}
+
+/****************************************************************************
+REMARKS:
+Initiailises the internal event handling modules. The EVT_suspend function
+can be called to suspend event handling (such as when shelling out to DOS),
+and this function can be used to resume it again later.
+****************************************************************************/
+void EVT_resume(void)
+{
+    /* Do nothing for non DOS systems */
+}
+
+/****************************************************************************
+REMARKS
+Suspends all of our event handling operations. This is also used to
+de-install the event handling code.
+****************************************************************************/
+void EVT_suspend(void)
+{
+    /* Do nothing for non DOS systems */
+}
+
+/****************************************************************************
+REMARKS
+Exits the event module for program terminatation.
+****************************************************************************/
+void EVT_exit(void)
+{
+    /* Restore signal handlers */
+    signal(SIGABRT, SIG_DFL);
+    signal(SIGFPE, SIG_DFL);
+    signal(SIGINT, SIG_DFL);
+
+    /* TODO: Do any OS specific cleanup in here */
+}
+
+/****************************************************************************
+REMARKS
+Sets the current X11 display
+****************************************************************************/
+void EVT_setX11Display(Display *dpy, Window win)
+{
+  _EVT_dpy = dpy;
+  _EVT_win = win;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h
new file mode 100755
index 0000000..45d7451
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h
@@ -0,0 +1,38 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  BeOS
+*
+* Description:  Include file to include all OS specific header files.
+*
+****************************************************************************/
+
+#include <X11/Xlib.h>
+#include <X11/keysym.h>
+#include <time.h>
+#include <signal.h>
+#ifdef USE_OS_JOYSTICK
+#include <X11/extensions/XI.h>
+#include <X11/extensions/XInput.h>
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj b/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj
new file mode 100755
index 0000000..0c6c80f
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj
@@ -0,0 +1,74 @@
+[SciTech]

+compiler=wc10- 

+targetos=d32 

+[COMPILER]

+version=5.0b

+MACRO=enable_current_compiler\n

+activeconfig=,getch.exe

+FILTERNAME=Source Files\n

+FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n

+FILTERASSOCIATEFILETYPES=0 

+FILTERAPPCOMMAND=\n

+vcsproject=SCC:Perforce SCM://depot

+vcslocalpath=SCC:Perforce SCM:c:\

+compile=concur|capture|:Compile:&Compile,dmake %n.obj

+make=concur|capture|clear|saveall|:Build:&Build,dmake %b

+rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake -u %b

+debug=concur|capture|savenone|nochangedir|:Debug:&Debug,wdn %b

+execute=hide|savenone|nochangedir|:Execute:E&xecute,

+user1=hide|nochangedir|:User 1:User 1,

+user2=hide|nochangedir|:User 2:User 2,

+usertool_build_all=concur|capture|clear|savenone|:Build All:Build All,dmake all

+usertool_rebuild_all=concur|capture|clear|savenone|:Rebuild All:Rebuild All,dmake -u all

+usertool_clean_directory=concur|capture|savenone|:Clean Directory:&Clean Directory,dmake cleanexe

+workingdir=.

+includedirs=%(SCITECH)\include;%(PRIVATE)\include

+reffile=

+[FILES]

+tests\altbrk.c

+tests\altcrit.c

+tests\biosptr.c

+tests\block.c

+tests\brk.c

+tests\callreal.c

+tests\checks.c

+tests\cpu.c

+tests\critical.c

+tests\getch.c

+tests\isvesa.c

+tests\key.c

+tests\key15.c

+tests\memtest.c

+tests\mouse.c

+tests\rtc.c

+tests\showpci.c

+tests\tick.c

+tests\timerc.c

+tests\timercpp.cpp

+tests\uswc.c

+tests\vftest.c

+tests\video.c

+[ASSOCIATION]

+[CONFIGURATIONS]

+config=,altbrk.exe

+config=,altcrit.exe

+config=,biosptr.exe

+config=,block.exe

+config=,brk.exe

+config=,callreal.exe

+config=,cpu.exe

+config=,critical.exe

+config=,getch.exe

+config=,isvesa.exe

+config=,key.exe

+config=,key15.exe

+config=,memtest.exe

+config=,mouse.exe

+config=,rtc.exe

+config=,showpci.exe

+config=,tick.exe

+config=,timerc.exe

+config=,timercpp.exe

+config=,uswc.exe

+config=,vftest.exe

+config=,video.exe

diff --git a/board/MAI/bios_emulator/scitech/src/pm/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/ztimer.c
new file mode 100755
index 0000000..5acf7b1
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/pm/ztimer.c
@@ -0,0 +1,516 @@
+/****************************************************************************
+*
+*                   SciTech OS Portability Manager Library
+*
+*  ========================================================================
+*
+*    The contents of this file are subject to the SciTech MGL Public
+*    License Version 1.0 (the "License"); you may not use this file
+*    except in compliance with the License. You may obtain a copy of
+*    the License at http://www.scitechsoft.com/mgl-license.txt
+*
+*    Software distributed under the License is distributed on an
+*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+*    implied. See the License for the specific language governing
+*    rights and limitations under the License.
+*
+*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
+*
+*    The Initial Developer of the Original Code is SciTech Software, Inc.
+*    All Rights Reserved.
+*
+*  ========================================================================
+*
+* Language:     ANSI C
+* Environment:  Any
+*
+* Description:  Module to implement high precision timing on each OS.
+*
+****************************************************************************/
+
+#include "ztimer.h"
+#include "pmapi.h"
+#include "oshdr.h"
+
+/*---------------------------- Global variables ---------------------------*/
+
+static LZTimerObject    LZTimer;
+static ulong            start,finish;
+#ifdef  __INTEL__
+static long             cpuSpeed = -1;
+static ibool            haveRDTSC = false;
+#endif
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* External Intel assembler functions */
+#ifdef  __INTEL__
+/* {secret} */
+void  _ASMAPI _CPU_readTimeStamp(CPU_largeInteger *time);
+/* {secret} */
+ulong _ASMAPI _CPU_diffTime64(CPU_largeInteger *t1,CPU_largeInteger *t2,CPU_largeInteger *t);
+/* {secret} */
+ulong _ASMAPI _CPU_calcMicroSec(CPU_largeInteger *count,ulong freq);
+#endif
+
+#if     defined(__SMX32__)
+#include "smx/ztimer.c"
+#elif   defined(__RTTARGET__)
+#include "rttarget/ztimer.c"
+#elif   defined(__REALDOS__)
+#include "dos/ztimer.c"
+#elif   defined(__NT_DRIVER__)
+#include "ntdrv/ztimer.c"
+#elif   defined(__WIN32_VXD__)
+#include "vxd/ztimer.c"
+#elif   defined(__WINDOWS32__)
+#include "win32/ztimer.c"
+#elif   defined(__OS2_VDD__)
+#include "vdd/ztimer.c"
+#elif   defined(__OS2__)
+#include "os2/ztimer.c"
+#elif   defined(__LINUX__)
+#include "linux/ztimer.c"
+#elif   defined(__QNX__)
+#include "qnx/ztimer.c"
+#elif   defined(__BEOS__)
+#include "beos/ztimer.c"
+#else
+#error  Timer library not ported to this platform yet!
+#endif
+
+/*------------------------ Public interface routines ----------------------*/
+
+/****************************************************************************
+DESCRIPTION:
+Initializes the Zen Timer library (extended)
+
+PARAMETERS:
+accurate    - True of the speed should be measured accurately
+
+HEADER:
+ztimer.h
+
+REMARKS:
+This function initializes the Zen Timer library, and /must/ be called before
+any of the remaining Zen Timer library functions are called. The accurate
+parameter is used to determine whether highly accurate timing should be
+used or not. If high accuracy is needed, more time is spent profiling the
+actual speed of the CPU so that we can obtain highly accurate timing
+results, but the time spent in the initialisation routine will be
+significantly longer (on the order of 5 seconds).
+****************************************************************************/
+void ZAPI ZTimerInitExt(
+    ibool accurate)
+{
+    if (cpuSpeed == -1) {
+	__ZTimerInit();
+#ifdef  __INTEL__
+	cpuSpeed = CPU_getProcessorSpeedInHZ(accurate);
+	haveRDTSC = CPU_haveRDTSC() && (cpuSpeed > 0);
+#endif
+	}
+}
+
+/****************************************************************************
+DESCRIPTION:
+Initializes the Zen Timer library.
+
+HEADER:
+ztimer.h
+
+REMARKS:
+This function initializes the Zen Timer library, and /must/ be called before
+any of the remaining Zen Timer library functions are called.
+****************************************************************************/
+void ZAPI ZTimerInit(void)
+{
+    ZTimerInitExt(false);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Starts the Long Period Zen Timer counting.
+
+HEADER:
+ztimer.h
+
+PARAMETERS:
+tm  - Timer object to start timing with
+
+REMARKS:
+Starts the Long Period Zen Timer counting. Once you have started the timer,
+you can stop it with LZTimerOff or you can latch the current count with
+LZTimerLap.
+
+The Long Period Zen Timer uses a number of different high precision timing
+mechanisms to obtain microsecond accurate timings results whenever possible.
+The following different techniques are used depending on the operating
+system, runtime environment and CPU on the target machine. If the target
+system has a Pentium CPU installed which supports the Read Time Stamp
+Counter instruction (RDTSC), the Zen Timer library will use this to
+obtain the maximum timing precision available.
+
+Under 32-bit Windows, if the Pentium RDTSC instruction is not available, we
+first try to use the Win32 QueryPerformanceCounter API, and if that is not
+available we fall back on the timeGetTime API which is always supported.
+
+Under 32-bit DOS, if the Pentium RDTSC instruction is not available, we
+then do all timing using the old style 8253 timer chip. The 8253 timer
+routines provide highly accurate timings results in pure DOS mode, however
+in a DOS box under Windows or other Operating Systems the virtualization
+of the timer can produce inaccurate results.
+
+Note: Because the Long Period Zen Timer stores the results in a 32-bit
+      unsigned integer, you can only time periods of up to 2^32 microseconds,
+      or about 1hr 20mins. For timing longer periods use the Ultra Long
+      Period Zen Timer.
+
+SEE ALSO:
+LZTimerOff, LZTimerLap, LZTimerCount
+****************************************************************************/
+void ZAPI LZTimerOnExt(
+    LZTimerObject *tm)
+{
+#ifdef  __INTEL__
+    if (haveRDTSC) {
+	_CPU_readTimeStamp(&tm->start);
+	}
+    else
+#endif
+	__LZTimerOn(tm);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns the current count for the Long Period Zen Timer and keeps it
+running.
+
+HEADER:
+ztimer.h
+
+PARAMETERS:
+tm  - Timer object to do lap timing with
+
+RETURNS:
+Count that has elapsed in microseconds.
+
+REMARKS:
+Returns the current count that has elapsed since the last call to
+LZTimerOn in microseconds. The time continues to run after this function is
+called so you can call this function repeatedly.
+
+SEE ALSO:
+LZTimerOn, LZTimerOff, LZTimerCount
+****************************************************************************/
+ulong ZAPI LZTimerLapExt(
+    LZTimerObject *tm)
+{
+#ifdef  __INTEL__
+    CPU_largeInteger    tmLap,tmCount;
+
+    if (haveRDTSC) {
+	_CPU_readTimeStamp(&tmLap);
+	_CPU_diffTime64(&tm->start,&tmLap,&tmCount);
+	return _CPU_calcMicroSec(&tmCount,cpuSpeed);
+	}
+    else
+#endif
+	return __LZTimerLap(tm);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Stops the Long Period Zen Timer counting.
+
+HEADER:
+ztimer.h
+
+PARAMETERS:
+tm  - Timer object to stop timing with
+
+REMARKS:
+Stops the Long Period Zen Timer counting and latches the count. Once you
+have stopped the timer you can read the count with LZTimerCount. If you need
+highly accurate timing, you should use the on and off functions rather than
+the lap function since the lap function does not subtract the overhead of
+the function calls from the timed count.
+
+SEE ALSO:
+LZTimerOn, LZTimerLap, LZTimerCount
+****************************************************************************/
+void ZAPI LZTimerOffExt(
+    LZTimerObject *tm)
+{
+#ifdef  __INTEL__
+    if (haveRDTSC) {
+	_CPU_readTimeStamp(&tm->end);
+	}
+    else
+#endif
+	__LZTimerOff(tm);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Returns the current count for the Long Period Zen Timer.
+
+HEADER:
+ztimer.h
+
+PARAMETERS:
+tm  - Timer object to compute the elapsed time with.
+
+RETURNS:
+Count that has elapsed in microseconds.
+
+REMARKS:
+Returns the current count that has elapsed between calls to
+LZTimerOn and LZTimerOff in microseconds.
+
+SEE ALSO:
+LZTimerOn, LZTimerOff, LZTimerLap
+****************************************************************************/
+ulong ZAPI LZTimerCountExt(
+    LZTimerObject *tm)
+{
+#ifdef  __INTEL__
+    CPU_largeInteger    tmCount;
+
+    if (haveRDTSC) {
+	_CPU_diffTime64(&tm->start,&tm->end,&tmCount);
+	return _CPU_calcMicroSec(&tmCount,cpuSpeed);
+	}
+    else
+#endif
+	return __LZTimerCount(tm);
+}
+
+/****************************************************************************
+DESCRIPTION:
+Starts the Long Period Zen Timer counting.
+
+HEADER:
+ztimer.h
+
+REMARKS:
+Obsolete function. You should use the LZTimerOnExt function instead
+which allows for multiple timers running at the same time.
+****************************************************************************/
+void ZAPI LZTimerOn(void)
+{ LZTimerOnExt(&LZTimer); }
+
+/****************************************************************************
+DESCRIPTION:
+Returns the current count for the Long Period Zen Timer and keeps it
+running.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+Count that has elapsed in microseconds.
+
+REMARKS:
+Obsolete function. You should use the LZTimerLapExt function instead
+which allows for multiple timers running at the same time.
+****************************************************************************/
+ulong ZAPI LZTimerLap(void)
+{ return LZTimerLapExt(&LZTimer); }
+
+/****************************************************************************
+DESCRIPTION:
+Stops the Long Period Zen Timer counting.
+
+HEADER:
+ztimer.h
+
+REMARKS:
+Obsolete function. You should use the LZTimerOffExt function instead
+which allows for multiple timers running at the same time.
+****************************************************************************/
+void ZAPI LZTimerOff(void)
+{ LZTimerOffExt(&LZTimer); }
+
+/****************************************************************************
+DESCRIPTION:
+Returns the current count for the Long Period Zen Timer.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+Count that has elapsed in microseconds.
+
+REMARKS:
+Obsolete function. You should use the LZTimerCountExt function instead
+which allows for multiple timers running at the same time.
+****************************************************************************/
+ulong ZAPI LZTimerCount(void)
+{ return LZTimerCountExt(&LZTimer); }
+
+/****************************************************************************
+DESCRIPTION:
+Starts the Ultra Long Period Zen Timer counting.
+
+HEADER:
+ztimer.h
+
+REMARKS:
+Starts the Ultra Long Period Zen Timer counting. Once you have started the
+timer, you can stop it with ULZTimerOff or you can latch the current count
+with ULZTimerLap.
+
+The Ultra Long Period Zen Timer uses the available operating system services
+to obtain accurate timings results with as much precision as the operating
+system provides, but with enough granularity to time longer periods of
+time than the Long Period Zen Timer. Note that the resolution of the timer
+ticks is not constant between different platforms, and you should use the
+ULZTimerResolution function to determine the number of seconds in a single
+tick of the timer, and use this to convert the timer counts to seconds.
+
+Under 32-bit Windows, we use the timeGetTime function which provides a
+resolution of 1 millisecond (0.001 of a second). Given that the timer
+count is returned as an unsigned 32-bit integer, this we can time intervals
+that are a maximum of 2^32 milliseconds in length (or about 1,200 hours or
+50 days!).
+
+Under 32-bit DOS, we use the system timer tick which runs at 18.2 times per
+second. Given that the timer count is returned as an unsigned 32-bit integer,
+this we can time intervals that are a maximum of 2^32 * (1/18.2) in length
+(or about 65,550 hours or 2731 days!).
+
+SEE ALSO:
+ULZTimerOff, ULZTimerLap, ULZTimerCount, ULZElapsedTime, ULZReadTime
+****************************************************************************/
+void ZAPI ULZTimerOn(void)
+{ start = __ULZReadTime(); }
+
+/****************************************************************************
+DESCRIPTION:
+Returns the current count for the Ultra Long Period Zen Timer and keeps it
+running.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+Count that has elapsed in resolution counts.
+
+REMARKS:
+Returns the current count that has elapsed since the last call to
+ULZTimerOn in microseconds. The time continues to run after this function is
+called so you can call this function repeatedly.
+
+SEE ALSO:
+ULZTimerOn, ULZTimerOff, ULZTimerCount
+****************************************************************************/
+ulong ZAPI ULZTimerLap(void)
+{ return (__ULZReadTime() - start); }
+
+/****************************************************************************
+DESCRIPTION:
+Stops the Long Period Zen Timer counting.
+
+HEADER:
+ztimer.h
+
+REMARKS:
+Stops the Ultra Long Period Zen Timer counting and latches the count. Once
+you have stopped the timer you can read the count with ULZTimerCount.
+
+SEE ALSO:
+ULZTimerOn, ULZTimerLap, ULZTimerCount
+****************************************************************************/
+void ZAPI ULZTimerOff(void)
+{ finish = __ULZReadTime(); }
+
+/****************************************************************************
+DESCRIPTION:
+Returns the current count for the Ultra Long Period Zen Timer.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+Count that has elapsed in resolution counts.
+
+REMARKS:
+Returns the current count that has elapsed between calls to
+ULZTimerOn and ULZTimerOff in resolution counts.
+
+SEE ALSO:
+ULZTimerOn, ULZTimerOff, ULZTimerLap, ULZTimerResolution
+****************************************************************************/
+ulong ZAPI ULZTimerCount(void)
+{ return (finish - start); }
+
+/****************************************************************************
+DESCRIPTION:
+Reads the current time from the Ultra Long Period Zen Timer.
+
+HEADER:
+ztimer.h
+
+RETURNS:
+Current timer value in resolution counts.
+
+REMARKS:
+Reads the current Ultra Long Period Zen Timer and returns it’s current
+count. You can use the ULZElapsedTime function to find the elapsed time
+between two timer count readings.
+
+SEE ALSO:
+ULZElapsedTime, ULZTimerResolution
+****************************************************************************/
+ulong ZAPI ULZReadTime(void)
+{ return __ULZReadTime(); }
+
+/****************************************************************************
+DESCRIPTION:
+Compute the elapsed time between two timer counts.
+
+HEADER:
+ztimer.h
+
+PARAMETERS:
+start   - Starting time for elapsed count
+finish  - Ending time for elapsed count
+
+RETURNS:
+Elapsed timer in resolution counts.
+
+REMARKS:
+Returns the elapsed time for the Ultra Long Period Zen Timer in units of the
+timers resolution (1/18th of a second under DOS). This function correctly
+computes the difference even if a midnight boundary has been crossed
+during the timing period.
+
+SEE ALSO:
+ULZReadTime, ULZTimerResolution
+****************************************************************************/
+ulong ZAPI ULZElapsedTime(
+    ulong start,
+    ulong finish)
+{ return __ULZElapsedTime(start,finish); }
+
+/****************************************************************************
+DESCRIPTION:
+Returns the resolution of the Ultra Long Period Zen Timer.
+
+HEADER:
+ztimer.h
+
+PARAMETERS:
+resolution   - Place to store the timer in microseconds per timer count.
+
+REMARKS:
+Returns the resolution of the Ultra Long Period Zen Timer as a 32-bit
+integer value measured in microseconds per timer count.
+
+SEE ALSO:
+ULZReadTime, ULZElapsedTime, ULZTimerCount
+****************************************************************************/
+void ZAPI ULZTimerResolution(
+	ulong *resolution)
+{ *resolution = ULZTIMER_RESOLUTION; }
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h b/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h
new file mode 100755
index 0000000..77c545a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h
@@ -0,0 +1,450 @@
+/* $XConsortium: AsmMacros.h /main/13 1996/10/25 11:33:12 kaleb $ */
+/*
+ * (c) Copyright 1993,1994 by David Wexelblat <dwex@xfree86.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of David Wexelblat shall not be
+ * used in advertising or otherwise to promote the sale, use or other dealings
+ * in this Software without prior written authorization from David Wexelblat.
+ *
+ */
+/*
+ * Copyright 1997
+ * Digital Equipment Corporation. All rights reserved.
+ * This software is furnished under license and may be used and copied only in
+ * accordance with the following terms and conditions.  Subject to these
+ * conditions, you may download, copy, install, use, modify and distribute
+ * this software in source and/or binary form. No title or ownership is
+ * transferred hereby.
+ *
+ * 1) Any source code used, modified or distributed must reproduce and retain
+ *    this copyright notice and list of conditions as they appear in the source
+ *    file.
+ *
+ * 2) No right is granted to use any trade name, trademark, or logo of Digital
+ *    Equipment Corporation. Neither the "Digital Equipment Corporation" name
+ *    nor any trademark or logo of Digital Equipment Corporation may be used
+ *    to endorse or promote products derived from this software without the
+ *    prior written permission of Digital Equipment Corporation.
+ *
+ * 3) This software is provided "AS-IS" and any express or implied warranties,
+ *    including but not limited to, any implied warranties of merchantability,
+ *    fitness for a particular purpose, or non-infringement are disclaimed. In
+ *    no event shall DIGITAL be liable for any damages whatsoever, and in
+ *    particular, DIGITAL shall not be liable for special, indirect,
+ *    consequential, or incidental damages or damages for
+ *    lost profits, loss of revenue or loss of use, whether such damages arise
+ *    in contract,
+ *    negligence, tort, under statute, in equity, at law or otherwise, even if
+ *    advised of the possibility of such damage.
+ *
+ */
+
+/* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/AsmMacros.h,v 3.14 1999/09/25 14:36:58 dawes Exp $ */
+
+#if defined(__GNUC__)
+#if defined(linux) && (defined(__alpha__) || defined(__ia64__))
+#undef inb
+#define inb _inb
+#undef inw
+#define inw _inw
+#undef inl
+#define inl _inl
+#undef outb
+#define outb(p,v) _outb((v),(p))
+#undef outw
+#define outw(p,v) _outw((v),(p))
+#undef outl
+#define outl(p,v) _outl((v),(p))
+#else
+#if defined(__sparc__)
+#ifndef ASI_PL
+#define ASI_PL 0x88
+#endif
+
+static __inline__ void
+outb(port, val)
+unsigned long port;
+char val;
+{
+  __asm__ __volatile__("stba %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL));
+}
+
+static __inline__ void
+outw(port, val)
+unsigned long port;
+char val;
+{
+  __asm__ __volatile__("stha %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL));
+}
+
+static __inline__ void
+outl(port, val)
+unsigned long port;
+char val;
+{
+  __asm__ __volatile__("sta %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL));
+}
+
+static __inline__ unsigned int
+inb(port)
+unsigned long port;
+{
+   unsigned char ret;
+   __asm__ __volatile__("lduba [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL));
+   return ret;
+}
+
+static __inline__ unsigned int
+inw(port)
+unsigned long port;
+{
+   unsigned char ret;
+   __asm__ __volatile__("lduha [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL));
+   return ret;
+}
+
+static __inline__ unsigned int
+inl(port)
+unsigned long port;
+{
+   unsigned char ret;
+   __asm__ __volatile__("lda [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL));
+   return ret;
+}
+#else
+#ifdef __arm32__
+unsigned int IOPortBase;  /* Memory mapped I/O port area */
+
+static __inline__ void
+outb(port, val)
+     short port;
+     char val;
+{
+     if ((unsigned short)port >= 0x400) return;
+
+    *(volatile unsigned char*)(((unsigned short)(port))+IOPortBase) = val;
+}
+
+static __inline__ void
+outw(port, val)
+     short port;
+     short val;
+{
+     if ((unsigned short)port >= 0x400) return;
+
+    *(volatile unsigned short*)(((unsigned short)(port))+IOPortBase) = val;
+}
+
+static __inline__ void
+outl(port, val)
+     short port;
+     int val;
+{
+     if ((unsigned short)port >= 0x400) return;
+
+    *(volatile unsigned long*)(((unsigned short)(port))+IOPortBase) = val;
+}
+
+static __inline__ unsigned int
+inb(port)
+     short port;
+{
+     if ((unsigned short)port >= 0x400) return((unsigned int)-1);
+
+    return(*(volatile unsigned char*)(((unsigned short)(port))+IOPortBase));
+}
+
+static __inline__ unsigned int
+inw(port)
+     short port;
+{
+     if ((unsigned short)port >= 0x400) return((unsigned int)-1);
+
+    return(*(volatile unsigned short*)(((unsigned short)(port))+IOPortBase));
+}
+
+static __inline__ unsigned int
+inl(port)
+     short port;
+{
+     if ((unsigned short)port >= 0x400) return((unsigned int)-1);
+
+    return(*(volatile unsigned long*)(((unsigned short)(port))+IOPortBase));
+}
+#else /* __arm32__ */
+#if defined(Lynx) && defined(__powerpc__)
+extern unsigned char *ioBase;
+
+static volatile void
+eieio()
+{
+    __asm__ __volatile__ ("eieio");
+}
+
+static void
+outb(port, value)
+short port;
+unsigned char value;
+{
+    *(uchar *)(ioBase + port) = value; eieio();
+}
+
+static void
+outw(port, value)
+short port;
+unsigned short value;
+{
+    *(unsigned short *)(ioBase + port) = value; eieio();
+}
+
+static void
+outl(port, value)
+short port;
+unsigned long value;
+{
+    *(unsigned long *)(ioBase + port) = value; eieio();
+}
+
+static unsigned char
+inb(port)
+short port;
+{
+    unsigned char val;
+
+    val = *((unsigned char *)(ioBase + port)); eieio();
+    return(val);
+}
+
+static unsigned short
+inw(port)
+short port;
+{
+    unsigned short val;
+
+    val = *((unsigned short *)(ioBase + port)); eieio();
+    return(val);
+}
+
+static unsigned long
+inl(port)
+short port;
+{
+    unsigned long val;
+
+    val = *((unsigned long *)(ioBase + port)); eieio();
+    return(val);
+}
+
+#else
+#if defined(__FreeBSD__) && defined(__alpha__)
+
+#include <sys/types.h>
+
+extern void outb(u_int32_t port, u_int8_t val);
+extern void outw(u_int32_t port, u_int16_t val);
+extern void outl(u_int32_t port, u_int32_t val);
+extern u_int8_t inb(u_int32_t port);
+extern u_int16_t inw(u_int32_t port);
+extern u_int32_t inl(u_int32_t port);
+
+#else
+#ifdef GCCUSESGAS
+static __inline__ void
+outb(port, val)
+short port;
+char val;
+{
+   __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port));
+}
+
+static __inline__ void
+outw(port, val)
+short port;
+short val;
+{
+   __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port));
+}
+
+static __inline__ void
+outl(port, val)
+short port;
+unsigned int val;
+{
+   __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port));
+}
+
+static __inline__ unsigned int
+inb(port)
+short port;
+{
+   unsigned char ret;
+   __asm__ __volatile__("inb %1,%0" :
+       "=a" (ret) :
+       "d" (port));
+   return ret;
+}
+
+static __inline__ unsigned int
+inw(port)
+short port;
+{
+   unsigned short ret;
+   __asm__ __volatile__("inw %1,%0" :
+       "=a" (ret) :
+       "d" (port));
+   return ret;
+}
+
+static __inline__ unsigned int
+inl(port)
+short port;
+{
+   unsigned int ret;
+   __asm__ __volatile__("inl %1,%0" :
+       "=a" (ret) :
+       "d" (port));
+   return ret;
+}
+
+#else /* GCCUSESGAS */
+
+static __inline__ void
+outb(port, val)
+     short port;
+     char val;
+{
+  __asm__ __volatile__("out%B0 (%1)" : :"a" (val), "d" (port));
+}
+
+static __inline__ void
+outw(port, val)
+     short port;
+     short val;
+{
+  __asm__ __volatile__("out%W0 (%1)" : :"a" (val), "d" (port));
+}
+
+static __inline__ void
+outl(port, val)
+     short port;
+     unsigned int val;
+{
+  __asm__ __volatile__("out%L0 (%1)" : :"a" (val), "d" (port));
+}
+
+static __inline__ unsigned int
+inb(port)
+     short port;
+{
+  unsigned int ret;
+  __asm__ __volatile__("in%B0 (%1)" :
+		   "=a" (ret) :
+		   "d" (port));
+  return ret;
+}
+
+static __inline__ unsigned int
+inw(port)
+     short port;
+{
+  unsigned int ret;
+  __asm__ __volatile__("in%W0 (%1)" :
+		   "=a" (ret) :
+		   "d" (port));
+  return ret;
+}
+
+static __inline__ unsigned int
+inl(port)
+     short port;
+{
+  unsigned int ret;
+  __asm__ __volatile__("in%L0 (%1)" :
+		   "=a" (ret) :
+		   "d" (port));
+  return ret;
+}
+
+#endif /* GCCUSESGAS */
+#endif /* Lynx && __powerpc__ */
+#endif /* arm32 */
+#endif /* linux && __sparc__ */
+#endif /* linux && __alpha__ */
+#endif /* __FreeBSD__ && __alpha__ */
+
+#if defined(linux) || defined(__arm32__) || (defined(Lynx) && defined(__powerpc__))
+
+#define intr_disable()
+#define intr_enable()
+
+#else
+
+static __inline__ void
+intr_disable()
+{
+  __asm__ __volatile__("cli");
+}
+
+static __inline__ void
+intr_enable()
+{
+  __asm__ __volatile__("sti");
+}
+
+#endif /* else !linux && !__arm32__ */
+
+#else /* __GNUC__ */
+
+#if defined(_MINIX) && defined(_ACK)
+
+/* inb, outb, inw and outw are defined in the library */
+/* ... but I've no idea if the same is true for inl & outl */
+
+u8_t inb(U16_t);
+void outb(U16_t, U8_t);
+u16_t inw(U16_t);
+void outw(U16_t, U16_t);
+u32_t inl(U16_t);
+void outl(U16_t, U32_t);
+
+#else /* not _MINIX and _ACK */
+
+# if defined(__STDC__) && (__STDC__ == 1)
+#  ifndef NCR
+#  define asm __asm
+#  endif
+# endif
+# ifdef SVR4
+#  include <sys/types.h>
+#  ifndef __USLC__
+#   define __USLC__
+#  endif
+# endif
+#ifndef SCO325
+# include <sys/inline.h>
+#else
+# include "../common/scoasm.h"
+#endif
+#define intr_disable() asm("cli")
+#define intr_enable()  asm("sti")
+
+#endif /* _MINIX and _ACK */
+#endif /* __GNUC__ */
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/README b/board/MAI/bios_emulator/scitech/src/v86bios/README
new file mode 100755
index 0000000..cb65674
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/README
@@ -0,0 +1,32 @@
+
+This is a preliminary version of a VGA softbooter for LINUX.
+
+It makes use of the of the vm86() call and is therefore only
+usable on ix86 systems.
+There are plans to port this program to use a x86 emulator
+like x86emu. Also it may be ported to other operating systems.
+
+So far it has been tested on a small number of cards. It might
+well be that it will fail on your card.
+
+If you need to make modifications to the programs to be able
+to boot your card please let the author know.
+
+So far there is no command line interface. All options need
+to be hardcoded. You can do this by editing debug.h. You can
+turn on a bunch of debug output. Other options allow you to
+boot the primary card (CONFIG_ACTIVE_DEVICE), save the bios
+to a file (SAVE_BIOS), and map the original system bios
+(MAP_SYS_BIOS).
+
+The author wants to thank
+ Hans Lermen   (dosemu)
+ and
+ Kendall Bennett (x86emu)
+for their support.
+
+Parts of the code - especially in v86.c and io.c - are based on code
+taken from dosemu. Parts of the code in int.c are based on code taken
+from x86emu
+
+Egbert Eich.  <Egbert.Eich@Physik.TU-Darmstadt.DE>
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr b/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr
new file mode 100755
index 0000000..9d2a80d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr
@@ -0,0 +1,15 @@
+/.*\(0x3da.*/||/.*\(0x3ba.*/ { 
+        if (v_3da != 1) print "_v_retrace_";
+        v_3da = 1;
+        next;        
+        }
+/.*\(0x42.*/||/.*\(0x43.*/ {
+        if (v_4x != 1) print "_timer_";
+        v_4x = 1;
+        next;
+}
+{
+    print;
+    v_3da = 0;
+    v_4x = 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c b/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c
new file mode 100755
index 0000000..6b12dff
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c
@@ -0,0 +1,415 @@
+#include <unistd.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/stat.h>
+#include <getopt.h>
+#if defined(__alpha__) || defined (__ia64__)
+#include <sys/io.h>
+#elif defined(HAVE_SYS_PERM)
+#include <sys/perm.h>
+#endif
+#include "debug.h"
+#include "v86bios.h"
+#include "pci.h"
+#include "AsmMacros.h"
+
+#define SIZE 0x100000
+#define VRAM_START 0xA0000
+#define VRAM_SIZE 0x1FFFF
+#define V_BIOS_SIZE 0x1FFFF
+#define BIOS_START 0x7C00            /* default BIOS entry */
+#define BIOS_MEM 0x600
+
+CARD8 code[] = { 0xcd, 0x10, 0xf4 };
+struct config Config;
+
+static int map(void);
+static void unmap(void);
+static void runBIOS(int argc, char **argv);
+static int map_vram(void);
+static void unmap_vram(void);
+static int copy_vbios(memType base);
+static int copy_sys_bios(void);
+static CARD32 setup_int_vect(void);
+static void update_bios_vars(void);
+static int chksum(CARD8 *start);
+static void setup_bios_regs(i86biosRegsPtr regs, int argc, char **argv);
+static void print_regs(i86biosRegsPtr regs);
+void dprint(unsigned long start, unsigned long size);
+
+void loadCodeToMem(unsigned char *ptr, CARD8 *code);
+
+static int vram_mapped = 0;
+static char* bios_var;
+
+
+int
+main(int argc,char **argv)
+{
+    CARD32 vbios_base;
+
+    Config.PrintPort = PRINT_PORT;
+    Config.IoStatistics = IO_STATISTICS;
+    Config.PrintIrq = PRINT_IRQ;
+    Config.PrintPci = PRINT_PCI;
+    Config.ShowAllDev = SHOW_ALL_DEV;
+    Config.PrintIp = PRINT_IP;
+    Config.SaveBios = SAVE_BIOS;
+    Config.Trace = TRACE;
+    Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY;
+    Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE;
+    Config.MapSysBios = MAP_SYS_BIOS;
+    Config.Resort = RESORT;
+    Config.FixRom = FIX_ROM;
+    Config.NoConsole = NO_CONSOLE;
+    Config.Verbose = VERBOSE;
+
+    if (!map())
+    exit(1);
+    if (!copy_sys_bios())
+    exit(1);
+    if (!(vbios_base = setup_int_vect()))
+    exit(1);
+    if (!map_vram())
+    exit(1);
+    if (!copy_vbios(vbios_base))
+    exit(1);
+
+    iopl(3);
+    setup_io();
+    runBIOS(argc,argv);
+    update_bios_vars();
+    unmap_vram();
+    iopl(0);
+    unmap();
+    printf("done !\n");
+    exit (1);
+}
+
+int
+map(void)
+{
+    void* mem;
+
+    mem = mmap(0, (size_t)SIZE,
+	       PROT_EXEC | PROT_READ | PROT_WRITE,
+	       MAP_FIXED | MAP_PRIVATE | MAP_ANON,
+	       -1, 0 );
+    if (mem != 0) {
+	perror("anonymous map");
+	return (0);
+    }
+    memset(mem,0,SIZE);
+
+    loadCodeToMem((unsigned char *) BIOS_START, code);
+    return (1);
+}
+
+static int
+copy_sys_bios(void)
+{
+#define SYS_BIOS 0xF0000
+    int mem_fd;
+
+    if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) {
+	perror("opening memory");
+	return (0);
+    }
+
+    if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS)
+	goto Error;
+    if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF)
+	goto Error;
+
+    close(mem_fd);
+    return (1);
+
+Error:
+    perror("sys_bios");
+    close(mem_fd);
+    return (0);
+}
+
+static int
+map_vram(void)
+{
+    int mem_fd;
+
+#ifdef __ia64__
+    if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0)
+#else
+    if ((mem_fd = open(MEM_FILE,O_RDWR))<0)
+#endif
+      {
+	perror("opening memory");
+	return 0;
+    }
+
+#ifndef __alpha__
+    if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE,
+		     PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED,
+		     mem_fd, VRAM_START) == (void *) -1)
+#else
+	 if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */
+	 if (!_bus_base_sparse()) sparse_shift = 0;
+	 if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift),
+						 PROT_READ | PROT_WRITE,
+						 MAP_SHARED,
+						 mem_fd, (VRAM_START << sparse_shift)
+						 | _bus_base_sparse())) == (void *) -1)
+#endif
+      {
+	perror("mmap error in map_hardware_ram");
+	    close(mem_fd);
+	    return (0);
+	}
+    vram_mapped = 1;
+    close(mem_fd);
+    return (1);
+}
+
+static int
+copy_vbios(memType v_base)
+{
+    int mem_fd;
+    unsigned char *tmp;
+    int size;
+
+    if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) {
+	perror("opening memory");
+	return (0);
+    }
+
+    if (lseek(mem_fd,(off_t) v_base, SEEK_SET) != (off_t) v_base) {
+	  fprintf(stderr,"Cannot lseek\n");
+	  goto Error;
+      }
+    tmp = (unsigned char *)malloc(3);
+    if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) {
+	    fprintf(stderr,"Cannot read\n");
+	goto Error;
+    }
+    if (lseek(mem_fd,(off_t) v_base,SEEK_SET) != (off_t) v_base)
+	goto Error;
+
+    if (*tmp != 0x55 || *(tmp+1) != 0xAA ) {
+	fprintf(stderr,"No bios found at: 0x%lx\n",v_base);
+	goto Error;
+    }
+#ifdef DEBUG
+	dprint((unsigned long)tmp,0x100);
+#endif
+    size = *(tmp+2) * 512;
+
+    if (read(mem_fd, (char *)v_base, (size_t) size) != (size_t) size) {
+	    fprintf(stderr,"Cannot read\n");
+	goto Error;
+    }
+    free(tmp);
+    close(mem_fd);
+    if (!chksum((CARD8*)v_base))
+	return (0);
+
+    return (1);
+
+Error:
+    perror("v_bios");
+    close(mem_fd);
+    return (0);
+}
+
+static void
+unmap(void)
+{
+    munmap(0,SIZE);
+}
+
+static void
+unmap_vram(void)
+{
+    if (!vram_mapped) return;
+
+    munmap((void*)VRAM_START,VRAM_SIZE);
+    vram_mapped = 0;
+}
+
+static void
+runBIOS(int argc, char ** argv)
+{
+    i86biosRegs bRegs;
+#ifdef V86BIOS_DEBUG
+    printf("starting BIOS\n");
+#endif
+    setup_bios_regs(&bRegs, argc, argv);
+    do_x86(BIOS_START,&bRegs);
+    print_regs(&bRegs);
+#ifdef V86BIOS_DEBUG
+    printf("done\n");
+#endif
+}
+
+static CARD32
+setup_int_vect(void)
+{
+    int mem_fd;
+    CARD32 vbase;
+    void *map;
+
+    if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) {
+    perror("opening memory");
+    return (0);
+    }
+
+    if ((map = mmap((void *) 0, (size_t) 0x2000,
+	 PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED,
+	 mem_fd, 0)) == (void *)-1)   {
+    perror("mmap error in map_hardware_ram");
+    close(mem_fd);
+    return (0);
+    }
+
+    close(mem_fd);
+    memcpy(0,map,BIOS_MEM);
+    munmap(map,0x2000);
+    /*
+     * create a backup copy of the bios variables to write back the
+     * modified values
+     */
+    bios_var = (char *)malloc(BIOS_MEM);
+    memcpy(bios_var,0,BIOS_MEM);
+
+    vbase = (*((CARD16*)(0x10 << 2) + 1)) << 4;
+    fprintf(stderr,"vbase: 0x%x\n",vbase);
+    return vbase;
+}
+
+static void
+update_bios_vars(void)
+{
+    int mem_fd;
+    void *map;
+    memType i;
+
+#ifdef __ia64__
+    if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0)
+#else
+    if ((mem_fd = open(MEM_FILE,O_RDWR))<0)
+#endif
+      {
+	perror("opening memory");
+	return;
+      }
+
+    if ((map = mmap((void *) 0, (size_t) 0x2000,
+	 PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED,
+	 mem_fd, 0)) == (void *)-1)   {
+    perror("mmap error in map_hardware_ram");
+    close(mem_fd);
+    return;
+    }
+
+    for (i = 0; i < BIOS_MEM; i++) {
+    if (bios_var[i] != *(CARD8*)i)
+	*((CARD8*)map + i) = *(CARD8*)i;
+    }
+
+    munmap(map,0x2000);
+    close(mem_fd);
+}
+
+
+static void
+setup_bios_regs(i86biosRegsPtr regs, int argc, char **argv)
+{
+    int c;
+
+    regs->ax = 0;
+    regs->bx = 0;
+    regs->cx = 0;
+    regs->dx = 0;
+    regs->es = 0;
+    regs->di = 0;
+    opterr = 0;
+    while ((c = getopt(argc,argv,"a:b:c:d:e:i:")) != EOF) {
+    switch (c) {
+    case 'a':
+	regs->ax = strtol(optarg,NULL,0);
+	break;
+    case 'b':
+	regs->bx = strtol(optarg,NULL,0);
+	break;
+    case 'c':
+	regs->cx = strtol(optarg,NULL,0);
+	break;
+    case 'd':
+	regs->dx = strtol(optarg,NULL,0);
+	break;
+    case 'e':
+	regs->es = strtol(optarg,NULL,0);
+	break;
+    case 'i':
+	regs->di = strtol(optarg,NULL,0);
+	break;
+    }
+    }
+}
+
+
+static int
+chksum(CARD8 *start)
+{
+  CARD16 size;
+  CARD8 val = 0;
+  int i;
+
+  size = *(start+2) * 512;
+  for (i = 0; i<size; i++)
+    val += *(start + i);
+
+  if (!val)
+    return 1;
+
+    fprintf(stderr,"BIOS cksum wrong!\n");
+  return 0;
+}
+
+static void
+print_regs(i86biosRegsPtr regs)
+{
+    printf("ax=%x bx=%x cx=%x dx=%x es=%x di=%x\n",(CARD16)regs->ax,
+       (CARD16)regs->bx,(CARD16)regs->cx,(CARD16)regs->dx,
+       (CARD16)regs->es,(CARD16)regs->di);
+}
+
+void
+loadCodeToMem(unsigned char *ptr, CARD8 code[])
+{
+    int i;
+    CARD8 val;
+
+    for ( i=0;;i++) {
+	val = code[i];
+	*ptr++ = val;
+	if (val == 0xf4) break;
+    }
+    return;
+}
+
+void
+dprint(unsigned long start, unsigned long size)
+{
+    int i,j;
+    char *c = (char *)start;
+
+    for (j = 0; j < (size >> 4); j++) {
+	printf ("\n0x%lx:  ",(unsigned long)c);
+	for (i = 0; i<16; i++)
+	    printf("%x ",(unsigned char) (*(c++)));
+    }
+    printf("\n");
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/command.c b/board/MAI/bios_emulator/scitech/src/v86bios/command.c
new file mode 100755
index 0000000..e2bce6d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/command.c
@@ -0,0 +1,38 @@
+#include <stdio.h>
+#include <readline/readline.h>
+#include <readline/history.h>
+#include <malloc.h>
+
+#define PROMPT ">"
+
+
+void
+getline(char *buf,int *num,int max_num)
+{
+    static int line_len = 0;
+    static char *line = NULL;
+    static char *line_pointer = NULL;
+    static int len = 0;
+    int tmp_len;
+    char *buff;
+
+    if (len <= 0) {
+    buff = readline(PROMPT);
+    add_history(buff);
+
+    if ((tmp_len = strlen(buff)) > line_len) {
+	free(line);
+	line = malloc(tmp_len);
+	line_len = tmp_len;
+    }
+    sprintf(line,"%s\n",buff);
+    free(buff);
+    line_pointer = line;
+    len = strlen(line);
+    }
+
+    *num = max_num > len? len : max_num;
+    strncpy(buf,line_pointer,*num);
+    line_pointer = line_pointer + *num;
+    len = len - *num;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/console.c b/board/MAI/bios_emulator/scitech/src/v86bios/console.c
new file mode 100755
index 0000000..5e9c924
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/console.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <sys/ioctl.h>
+#include <sys/vt.h>
+#include <sys/kd.h>
+#include <stdio.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include "debug.h"
+#include "v86bios.h"
+
+console
+open_console(void)
+{
+    int fd;
+    int VTno;
+    char VTname[11];
+    console Con = {-1,-1};
+    struct vt_stat vts;
+
+    if (NO_CONSOLE)
+	    return Con;
+
+    if ((fd = open("/dev/tty0",O_WRONLY,0)) < 0)
+	return Con;
+
+    if ((ioctl(fd, VT_OPENQRY, &VTno) < 0) || (VTno == -1)) {
+	fprintf(stderr,"cannot get a vt\n");
+	return Con;
+    }
+
+    close(fd);
+    sprintf(VTname,"/dev/tty%i",VTno);
+
+    if ((fd = open(VTname, O_RDWR|O_NDELAY, 0)) < 0) {
+	fprintf(stderr,"cannot open console\n");
+	return Con;
+    }
+
+    if (ioctl(fd, VT_GETSTATE, &vts) == 0)
+	Con.vt = vts.v_active;
+
+    if (ioctl(fd, VT_ACTIVATE, VTno) != 0) {
+	fprintf(stderr,"cannot activate console\n");
+	close(fd);
+	return Con;
+    }
+    if (ioctl(fd, VT_WAITACTIVE, VTno) != 0) {
+	fprintf(stderr,"wait for active console failed\n");
+	close(fd);
+	return Con;
+    }
+#if 0
+    if (ioctl(fd, KDSETMODE, KD_GRAPHICS) < 0) {
+	close(fd);
+	return Con;
+    }
+#endif
+    Con.fd = fd;
+    return Con;
+}
+
+void
+close_console(console Con)
+{
+    if (Con.fd == -1)
+	return;
+
+#if 0
+    ioctl(Con.fd, KDSETMODE, KD_TEXT);
+#endif
+    if (Con.vt >=0)
+	ioctl(Con.fd, VT_ACTIVATE, Con.vt);
+
+    close(Con.fd);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/debug.h b/board/MAI/bios_emulator/scitech/src/v86bios/debug.h
new file mode 100755
index 0000000..c5c906b
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/debug.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+/*#define V86BIOS_DEBUG */
+
+/*
+ * uncomment the following if needed
+ * should be command line options
+ */
+
+#define PRINT_PORT 0
+#define IO_STATISTICS 0
+#define PRINT_IRQ 0
+#define PRINT_PCI 1
+#define PRINT_IP 0    /* print IP address with PIO information */
+#define TRACE 0       /* turn on debugger in x86emu            */
+		      /* requires x86emu compiled with -DDEBUG */
+
+/*
+ * these should not be here.
+ * Should be converted to command line options.
+ */
+#define CONFIG_ACTIVE_ONLY 0
+#define CONFIG_ACTIVE_DEVICE 1
+#define SAVE_BIOS 0
+#define MAP_SYS_BIOS 1
+#define RESORT 1
+#define FIX_ROM 0
+#define NO_CONSOLE 0
+#define SHOW_ALL_DEV 0
+#define VERBOSE 0
+
+/*#define V_BIOS 0xe0000 */
+/*#define V_BIOS 0xe4000 */
+
+
+#if (PRINT_IO == 1) && (PRINT_PORT == 0)
+# define PRINT_IO 0
+#endif
+#if (IO_STATISTICS == 1) && (PRINT_PORT == 0)
+# define IO_STATISTICS 0
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards b/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards
new file mode 100755
index 0000000..943d44e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards
@@ -0,0 +1,76 @@
+What I had to do to make cards happy:
+
+1. Tseng ET4000 W32P
+This card wants to call the original system BIOS video routines.
+It sets the int 0x42 vector to F000:F065, the entry point to the
+system bios video routines. 
+CAVE: don't catch int 0x42 and use the vbios int 0x10 routines. 
+At early stage during initialization they call int 0x42. This 
+causes an infinite loop.
+
+2. ATi Mach64 Rage IIc AGP
+This card does similar things like the Tseng ET4000 W32P.
+However it doesn't have the problem with the ininite loop.
+
+3. Elsa Victory II-A16 AGP Banshee
+This card is very clever: It knows it is an AGP card. Therefore
+it knows it is behind a PCI-PCI bridge. It also knows that noone
+else is behind this bridge. Therefore it start reprogramming the
+bridge! For this it assumes the AGP bridge is on bus 1.
+
+4. Elsa Gloria Synergy 8 ViVo AGP PM2
+This card likes to see a complete interrupt vector table. If
+we fill this table with 0 the VBIOS detects this and quits 
+initialization.
+
+5. Dimond Viper 330 AGP NVIDIA Riva 128.
+This card has a similar problem like the Elsa Gloria. It wants
+to read the system BIOS date at 0xffffd.
+
+6. Matrox Mystique PCI 
+This card reads the IO port 0x62. If it doesn't like what it sees
+it loops forever. To keep the card happy put 0xfc into 0xffffe.
+This location holds the system model id. 0xfc means IBM-AT.
+ One can make an interesting observation: this card likes to know 
+with whom it has to share the system. Therefore it accesses PCI 
+config space of all the other cards. It does this bypassing the 
+PCI BIOS by reading the PCI access ports directly.
+
+7. Matrox G100 AGP
+This card has the same problem as the Mystique. 
+
+Apperantly this works now. However not all combinations of cards are
+checked, yet.
+
+Further notes:
+the IO register 0x42-0x43 as well as 0x61-0x63 are of special interest
+for many graphic cards. They should be emulated.
+The so called "Industry Standard BIOS Entry Points" to int 0x42 (0xFF065)
+and to int 0x1a (0xFFE6E) should be filled with useful code. This code
+needs to return as if it was called as int.
+The subvendor ID PCI registers might cause problems. On some chipsets
+they are programmed in a non-obivous non-PCI conformant way.
+V_Bioses are seen to modify the following int:
+0x10 (default video), 0x1f(font table), 0x42(copy of default video), 
+0x43 (??), 0x6d (copy of default video - same as 0x10?)
+
+TODO:
+Int 0x6d needs to be done.
+All interrupts where there is no default industry standard entry point
+should point to an unused location in the 0xF000 segmant (possibly 
+0xF0000). This way they could be trapped. A trap handler for
+a. int 0x42 and int 0x1a needs to be implemented.
+The default "industry entry point" for video and PCI (0xFFE6E) should
+also be implemented. (any others?) They should either be routed to
+int 0x42(0x6d?) (video) and 0x1A (PCI) or some other interrupts to
+trap them. Mapping of system bios might not be a good idea. Maybe
+the system bios area should just be filled with "hlt" to trap any
+access there.
+Handling of timer IO registers 0x42, 0x43 and IO registers 0x61, 0x62.
+
+Find documentation:
+- on interrupt vector table
+- on industry standard entry points to the system bios
+- on IO registers 0x61 and 0x62
+
+
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/hexdump b/board/MAI/bios_emulator/scitech/src/v86bios/hexdump
new file mode 100755
index 0000000..4f359e5
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/hexdump
@@ -0,0 +1,3 @@
+"%06.6_ax  "  16/1 "%02x " 
+"  " 16/1 "%_p" 
+"\n"
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/int.c b/board/MAI/bios_emulator/scitech/src/v86bios/int.c
new file mode 100755
index 0000000..3504c6c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/int.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "debug.h"
+#if defined(__alpha__) || defined (__ia64__)
+#include <sys/io.h>
+#endif
+
+#include "v86bios.h"
+#include "AsmMacros.h"
+#include "pci.h"
+
+static int int1A_handler(struct regs86 *regs);
+static int int42_handler(int num, struct regs86 *regs);
+
+int
+int_handler(int num, struct regs86 *regs)
+{
+    switch (num) {
+    case 0x10:
+    case 0x42:
+	return (int42_handler(num,regs));
+    case 0x1A:
+	return (int1A_handler(regs));
+    default:
+	return 0;
+    }
+    return 0;
+}
+
+static int
+int42_handler(int num,struct regs86 *regs)
+{
+    unsigned char c;
+    CARD32 val;
+
+    i_printf("int 0x%x: ax:0x%lx bx:0x%lx cx:0x%lx dx:0x%lx\n",num,
+	   regs->eax,regs->ebx, regs->ecx, regs->edx);
+
+    /*
+     * video bios has modified these -
+     * leave it to the video bios to do this
+     */
+
+    val = getIntVect(num);
+    if (val != 0xF000F065)
+      return 0;
+
+    if ((regs->ebx & 0xff) == 0x32) {
+	switch (regs->eax & 0xFFFF) {
+	case 0x1200:
+	    i_printf("enabling video\n");
+	    c = inb(0x3cc);
+	    c |= 0x02;
+	    outb(0x3c2,c);
+	    return 1;
+	case 0x1201:
+	    i_printf("disabling video\n");
+	    c = inb(0x3cc);
+	    c &= ~0x02;
+	    outb(0x3c2,c);
+	    return 1;
+	default:
+	}
+    }
+    if (num == 0x42)
+	return 1;
+    else
+	return 0;
+}
+
+#define SUCCESSFUL              0x00
+#define DEVICE_NOT_FOUND        0x86
+#define BAD_REGISTER_NUMBER     0x87
+
+static int
+int1A_handler(struct regs86 *regs)
+{
+    CARD32 Slot;
+    PciStructPtr pPci;
+
+    if (! CurrentPci) return 0; /* oops */
+
+    i_printf("int 0x1a: ax=0x%lx bx=0x%lx cx=0x%lx dx=0x%lx di=0x%lx"
+	 " si=0x%lx\n", regs->eax,regs->ebx,regs->ecx,regs->edx,
+	 regs->edi,regs->esi);
+    switch (regs->eax & 0xFFFF) {
+    case 0xb101:
+	regs->eax  &= 0xFF00;   /* no config space/special cycle support */
+	regs->edx = 0x20494350; /* " ICP" */
+	regs->ebx  = 0x0210;    /* Version 2.10 */
+	regs->ecx  &= 0xFF00;
+	regs->ecx |= (pciMaxBus & 0xFF);   /* Max bus number in system */
+	regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	i_printf("ax=0x%lx dx=0x%lx bx=0x%lx cx=0x%lx flags=0x%lx\n",
+		 regs->eax,regs->edx,regs->ebx,regs->ecx,regs->eflags);
+	return 1;
+    case 0xb102:
+	if (((regs->edx & 0xFFFF) == CurrentPci->VendorID) &&
+	    ((regs->ecx & 0xFFFF) == CurrentPci->DeviceID) &&
+	    (regs->esi == 0)) {
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	    regs->ebx = pciSlotBX(CurrentPci);
+	}
+	else if (Config.ShowAllDev &&
+	     (pPci = findPciDevice(regs->edx,regs->ecx,regs->esi)) != NULL) {
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	    regs->ebx = pciSlotBX(pPci);
+	} else  {
+	    regs->eax = (regs->eax & 0x00FF) | (DEVICE_NOT_FOUND << 8);
+	    regs->eflags |= ((unsigned long)0x01); /* set carry flag */
+	}
+	i_printf("ax=0x%lx bx=0x%lx flags=0x%lx\n",
+		 regs->eax,regs->ebx,regs->eflags);
+	return 1;
+    case 0xb103:
+	if (((regs->ecx & 0xFF) == CurrentPci->Interface) &&
+	    (((regs->ecx & 0xFF00) >> 8) == CurrentPci->SubClass) &&
+	    (((regs->ecx & 0xFFFF0000) >> 16) == CurrentPci->BaseClass) &&
+	    ((regs->esi & 0xff) == 0)) {
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->ebx = pciSlotBX(CurrentPci);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	}
+	else if (Config.ShowAllDev
+	     && (pPci = findPciClass(regs->ecx & 0xFF, (regs->ecx & 0xff00) >> 8,
+			 (regs->ecx & 0xffff0000) >> 16, regs->esi)) != NULL) {
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->ebx = pciSlotBX(pPci);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	} else {
+	    regs->eax = (regs->eax & 0x00FF) | (DEVICE_NOT_FOUND << 8);
+	    regs->eflags |= ((unsigned long)0x01); /* set carry flag */
+	}
+	i_printf("ax=0x%lx flags=0x%lx\n",regs->eax,regs->eflags);
+	return 1;
+    case 0xb108:
+	i_printf("Slot=0x%x\n",CurrentPci->Slot.l);
+	if ((Slot = findPci(regs->ebx))) {
+	    regs->ecx &= 0xFFFFFF00;
+	    regs->ecx |= PciRead8(regs->edi,Slot);
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	} else {
+	    regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8);
+	    regs->eflags |= ((unsigned long)0x01); /* set carry flag */
+	}
+	i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n",
+		 regs->eax,regs->ecx,regs->eflags);
+	return 1;
+    case 0xb109:
+	i_printf("Slot=0x%x\n",CurrentPci->Slot.l);
+	if ((Slot = findPci(regs->ebx))) {
+	    regs->ecx &= 0xFFFF0000;
+	    regs->ecx |= PciRead16(regs->edi,Slot);
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	} else {
+	    regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8);
+	    regs->eflags |= ((unsigned long)0x01); /* set carry flag */
+	}
+	i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n",
+		 regs->eax,regs->ecx,regs->eflags);
+	return 1;
+    case 0xb10a:
+	i_printf("Slot=0x%x\n",CurrentPci->Slot.l);
+	if ((Slot = findPci(regs->ebx))) {
+	    regs->ecx &= 0;
+	    regs->ecx |= PciRead32(regs->edi,Slot);
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	} else {
+	    regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8);
+	    regs->eflags |= ((unsigned long)0x01); /* set carry flag */
+	}
+	i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n",
+		 regs->eax,regs->ecx,regs->eflags);
+	return 1;
+    case 0xb10b:
+	i_printf("Slot=0x%x\n",CurrentPci->Slot.l);
+	if ((Slot = findPci(regs->ebx))) {
+	    PciWrite8(regs->edi,(CARD8)regs->ecx,Slot);
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	} else {
+	    regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8);
+	    regs->eflags |= ((unsigned long)0x01); /* set carry flag */
+	}
+	i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags);
+	return 1;
+    case 0xb10c:
+	i_printf("Slot=0x%x\n",CurrentPci->Slot.l);
+	if ((Slot = findPci(regs->ebx))) {
+	    PciWrite16(regs->edi,(CARD16)regs->ecx,Slot);
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	} else {
+	    regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8);
+	    regs->eflags |= ((unsigned long)0x01); /* set carry flag */
+	}
+	i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags);
+	return 1;
+    case 0xb10d:
+	i_printf("Slot=0x%x\n",CurrentPci->Slot.l);
+	if ((Slot = findPci(regs->ebx))) {
+	    PciWrite32(regs->edi,(CARD32)regs->ecx,Slot);
+	    regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8);
+	    regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */
+	} else {
+	    regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8);
+	    regs->eflags |= ((unsigned long)0x01); /* set carry flag */
+	}
+	i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags);
+	return 1;
+    default:
+	return 0;
+    }
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/io.c b/board/MAI/bios_emulator/scitech/src/v86bios/io.c
new file mode 100755
index 0000000..f35b43e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/io.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "debug.h"
+
+#include <stdio.h>
+#if defined(__alpha__) || defined (__ia64__)
+#include <sys/io.h>
+#endif
+#include "AsmMacros.h"
+#include "v86bios.h"
+#include "pci.h"
+
+int r_inb = 0, r_inw = 0, r_inl = 0, r_outb = 0, r_outw = 0, r_outl = 0;
+int in_b = 0, in_w = 0, in_l = 0, out_b = 0, out_w = 0, out_l = 0;
+
+
+int
+port_rep_inb(CARD16 port, CARD8 *base, int d_f, CARD32 count)
+{
+    register int inc = d_f ? -1 : 1;
+    CARD8 *dst = base;
+
+    p_printf(" rep_insb(%#x) %d bytes at %p %s",
+	     port, count, base, d_f?"up":"down");
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    r_inb++;
+    while (count--) {
+	*dst = inb(port);
+	dst += inc;
+    }
+    return (dst-base);
+}
+
+int
+port_rep_inw(CARD16 port, CARD16 *base, int d_f, CARD32 count)
+{
+    register int inc = d_f ? -1 : 1;
+    CARD16 *dst = base;
+
+    p_printf(" rep_insw(%#x) %d bytes at %p %s",
+	     port, count, base, d_f?"up":"down");
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    r_inw++;
+    while (count--) {
+	*dst = inw(port);
+	dst += inc;
+    }
+    return (dst-base);
+}
+
+int
+port_rep_inl(CARD16 port, CARD32 *base, int d_f, CARD32 count)
+{
+    register int inc = d_f ? -1 : 1;
+    CARD32 *dst = base;
+
+    p_printf(" rep_insl(%#x) %d bytes at %p %s",
+	     port, count, base, d_f?"up":"down");
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    r_inl++;
+    while (count--) {
+	*dst = inl(port);
+	dst += inc;
+    }
+    return (dst-base);
+}
+
+int
+port_rep_outb(CARD16 port, CARD8 *base, int d_f, CARD32 count)
+{
+    register int inc = d_f ? -1 : 1;
+    CARD8 *dst = base;
+
+    p_printf(" rep_outb(%#x) %d bytes at %p %s",
+	     port, count, base, d_f?"up":"down");
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    r_outb++;
+    while (count--) {
+	outb(port,*dst);
+	dst += inc;
+    }
+    return (dst-base);
+}
+
+int
+port_rep_outw(CARD16 port, CARD16 *base, int d_f, CARD32 count)
+{
+    register int inc = d_f ? -1 : 1;
+    CARD16 *dst = base;
+
+    p_printf(" rep_outw(%#x) %d bytes at %p %s",
+	     port, count, base, d_f?"up":"down");
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    r_outw++;
+    while (count--) {
+	outw(port,*dst);
+	dst += inc;
+    }
+    return (dst-base);
+}
+
+int
+port_rep_outl(CARD16 port, CARD32 *base, int d_f, CARD32 count)
+{
+    register int inc = d_f ? -1 : 1;
+    CARD32 *dst = base;
+
+    p_printf(" rep_outl(%#x) %d bytes at %p %s",
+	     port, count, base, d_f?"up":"down");
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    r_outl++;
+    while (count--) {
+	outl(port,*dst);
+	dst += inc;
+    }
+    return (dst-base);
+}
+
+CARD8
+p_inb(CARD16 port)
+{
+    CARD8 val = 0;
+    in_b++;
+    val = inb(port);
+    p_printf(" inb(%#x) = %2.2x",port,val);
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    return val;
+}
+
+CARD16
+p_inw(CARD16 port)
+{
+    CARD16 val = 0;
+    in_w++;
+    val = inw(port);
+    p_printf(" inw(%#x) = %4.4x",port,val);
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    return val;
+}
+
+CARD32
+p_inl(CARD16 port)
+{
+    CARD32 val = 0;
+    in_l++;
+#ifdef NEED_PCI_IO
+    if (cfg1in(port,&val))
+	return val;
+    else
+#endif
+    val = inl(port);
+    p_printf(" inl(%#x) = %8.8x",port,val);
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    return val;
+}
+
+void
+p_outb(CARD16 port, CARD8 val)
+{
+    out_b++;
+    p_printf(" outb(%#x, %2.2x)",port,val);
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    outb(port,val);
+}
+
+void
+p_outw(CARD16 port, CARD16 val)
+{
+    out_w++;
+    p_printf(" outw(%#x, %4.4x)",port,val);
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+    outw(port,val);
+}
+
+void
+p_outl(CARD16 port, CARD32 val)
+{
+    out_l++;
+    p_printf(" outl(%#x, %8.8x)",port,val);
+    if (Config.PrintIp)
+	p_printf(" %x\n",getIP());
+    else p_printf("\n");
+
+#ifdef NEED_PCI_IO
+    if (cfg1out(port,val))
+	return;
+#endif
+    outl(port,val);
+}
+
+void
+io_statistics(void)
+{
+    p_printf("rep: inb: %i, inw: %i, inl: %i, outb: %i, outw: %i, outl: %i\n",
+	 r_inb,r_inw,r_inl,r_outb,r_outw,r_outl);
+    p_printf("inb: %i, inw: %i, inl: %i, outb: %i, outw: %i, outl: %i\n",
+	 in_b,in_w,in_l,out_b,out_w,out_l);
+}
+
+void
+clear_stat(void)
+{
+    r_inb = r_inw = r_inl = r_outb = r_outw = r_outl = 0;
+    in_b = in_w = in_l = out_b = out_w = out_l = 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/lex.l b/board/MAI/bios_emulator/scitech/src/v86bios/lex.l
new file mode 100755
index 0000000..3a3391c
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/lex.l
@@ -0,0 +1,79 @@
+%{
+#include "parser.h"
+
+#include <string.h>
+#include <stdio.h>
+
+ void getline(char *buf,int *num,int max_num);
+    
+#define YY_INPUT(buf,result,max_size) {\
+      getline(buf,&result,max_size);\
+      }
+
+ void
+ yyerror (char *s)  
+ {
+     printf ("%s\n", s);
+ }
+
+%}
+
+DIGIT [0-9a-fA-F]
+
+%%
+
+"0x"?{DIGIT}+ { yylval = strtol(yytext,NULL,0); return TOK_NUM; }
+"ax"          { return TOK_REG_AX; }
+"bx"          { return TOK_REG_BX; }
+"cx"          { return TOK_REG_CX; }
+"dx"          { return TOK_REG_DX; }
+"di"          { return TOK_REG_SI; }
+"si"          { return TOK_REG_DI; }
+"ds"          { return TOK_SEG_DS; }
+"es"          { return TOK_SEG_ES; }
+":"           { return TOK_SEP;}
+"$"{DIGIT}{1,2} { yylval = strtol(yytext+1,NULL,0); return TOK_VAR; }
+"$mem"        { return TOK_VAR_MEM; }
+[ \t]+
+"#".*[\n]   { return TOK_END; }
+"boot"        { return TOK_COMMAND_BOOT; }
+"do"          { return TOK_COMMAND_EXEC; }
+"\"".*"\""    { yylval = (unsigned long) yytext; return TOK_STRING; }
+"byte"        { return TOK_BYTE; }
+"word"        { return TOK_WORD; }
+"long"        { return TOK_LONG; }
+"setmem"      { return TOK_COMMAND_MEMSET; }
+"dumpmem"     { return TOK_COMMAND_MEMDUMP; }
+"quit"        { return TOK_COMMAND_QUIT; }
+"\n"          { return TOK_END; }
+"select"      { return TOK_SELECT; }
+"isa"         { return TOK_ISA; }
+"pci"         { return TOK_PCI; }
+"pport"       { return TOK_PRINT_PORT; }
+"iostat"      { return TOK_IOSTAT; }
+"pirq"        { return TOK_PRINT_IRQ; }
+"ppci"        { return TOK_PPCI; }
+"pip"         { return TOK_PIP; }
+"trace"       { return TOK_TRACE; }
+"on"          { return TOK_ON; }
+"off"         { return TOK_OFF; }
+"verbose"     { return TOK_VERBOSE; }
+"log"         { return TOK_LOG; }
+"print"       { return TOK_STDOUT; }
+"clstat"      { return TOK_CLSTAT; }
+"hlt"         { return TOK_HLT; }
+"del"         { return TOK_DEL; }
+"ioperm"      { return TOK_IOPERM; }
+"lpci"        { return TOK_DUMP_PCI; }
+"bootbios"    { return TOK_BOOT_BIOS; }
+"?"           { return '?'; }
+.             { return TOK_ERROR; }
+    
+%%
+
+
+
+
+
+
+
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/main.c b/board/MAI/bios_emulator/scitech/src/v86bios/main.c
new file mode 100755
index 0000000..15f9115
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/main.c
@@ -0,0 +1,616 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#define DELETE
+#include <unistd.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/stat.h>
+#if defined(__alpha__) || defined (__ia64__)
+#include <sys/io.h>
+#elif defined(HAVE_SYS_PERM)
+#include <sys/perm.h>
+#endif
+#include "debug.h"
+#include "v86bios.h"
+#include "pci.h"
+#include "AsmMacros.h"
+
+#define SIZE 0x100000
+#define VRAM_START 0xA0000
+#define VRAM_SIZE 0x1FFFF
+#define V_BIOS_SIZE 0x1FFFF
+#define BIOS_START 0x7C00            /* default BIOS entry */
+
+/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0, 0xf4 }; */
+#define VB_X(x) (V_BIOS >> x) & 0xFF
+CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xf4 };
+/*CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xb8, 0x03, 0x00, */
+/*0xcd, 0x10, 0xf4 }; */
+/*CARD8 code[] = {  0xb8 , 0xf0 , 0xf0 ,0xf4 }; */
+
+static void sig_handler(int);
+static int map(void);
+static void unmap(void);
+static void bootBIOS(CARD16 ax);
+static int map_vram(void);
+static void unmap_vram(void);
+static int copy_vbios(void);
+static int copy_sys_bios(void);
+static void save_bios_to_file(void);
+static int setup_system_bios(void);
+static void setup_int_vect(void);
+static int chksum(CARD8 *start);
+static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax);
+
+void loadCodeToMem(unsigned char *ptr, CARD8 *code);
+void dprint(unsigned long start, unsigned long size);
+
+static int vram_mapped = 0;
+static CARD8 save_msr;
+static CARD8 save_pos102;
+static CARD8 save_vse;
+static CARD8 save_46e8;
+console Console;
+struct config Config;
+
+
+int
+main(void)
+{
+    int Active_is_Pci = 0;
+#ifdef DELETE
+    Config.PrintPort = PRINT_PORT;
+    Config.IoStatistics = IO_STATISTICS;
+    Config.PrintIrq = PRINT_IRQ;
+    Config.PrintPci = PRINT_PCI;
+    Config.ShowAllDev = SHOW_ALL_DEV;
+    Config.PrintIp = PRINT_IP;
+    Config.SaveBios = SAVE_BIOS;
+    Config.Trace = TRACE;
+    Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY;
+    Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE;
+    Config.MapSysBios = MAP_SYS_BIOS;
+    Config.Resort = RESORT;
+    Config.FixRom = FIX_ROM;
+    Config.NoConsole = NO_CONSOLE;
+    Config.Verbose = VERBOSE;
+
+    if (!map())
+	exit(1);
+
+    if (!setup_system_bios())
+	exit(1);
+
+    iopl(3);
+    setup_io();
+
+    scan_pci();
+    if (!CurrentPci && !Config.ConfigActiveDevice && !Config.ConfigActiveOnly)
+	exit (1);
+#endif
+    Console = open_console();
+
+    if (Config.ConfigActiveOnly) {
+	CARD16 ax;
+	int activePci = 0;
+	int error = 0;
+
+	while (CurrentPci) {
+	    if (CurrentPci->active) {
+		activePci = 1;
+			    if (!(mapPciRom(NULL) && chksum((CARD8*)V_BIOS)))
+				error = 1;
+			    break;
+	    }
+	    CurrentPci = CurrentPci->next;
+	}
+	ax = ((CARD16)(CurrentPci->bus) << 8)
+	    | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7);
+	P_printf("ax: 0x%x\n",ax);
+	setup_int_vect();
+	if (!error && (activePci || copy_vbios())) {
+
+	    if (Config.SaveBios) save_bios_to_file();
+	    if  (map_vram()) {
+		printf("initializing ISA\n");
+			    bootBIOS(0);
+	    }
+	}
+	unmap_vram();
+	sleep(1);
+    } else {
+	/* disable primary card */
+	save_msr = inb(0x3CC);
+	save_vse = inb(0x3C3);
+	save_46e8 = inb(0x46e8);
+	save_pos102 = inb(0x102);
+
+	signal(2,sig_handler);
+	signal(11,sig_handler);
+
+	outb(0x3C2,~(CARD8)0x03 & save_msr);
+	outb(0x3C3,~(CARD8)0x01 & save_vse);
+	outb(0x46e8, ~(CARD8)0x08 & save_46e8);
+	outb(0x102, ~(CARD8)0x01 & save_pos102);
+
+	pciVideoDisable();
+
+	while (CurrentPci) {
+	    CARD16 ax;
+
+	    if (CurrentPci->active) {
+		Active_is_Pci = 1;
+		if (!Config.ConfigActiveDevice) {
+		    CurrentPci = CurrentPci->next;
+		    continue;
+		}
+	    }
+
+	    EnableCurrent();
+
+	    if (CurrentPci->active) {
+		outb(0x102, save_pos102);
+		outb(0x46e8, save_46e8);
+		outb(0x3C3, save_vse);
+		outb(0x3C2, save_msr);
+	    }
+
+	    /* clear interrupt vectors */
+	    setup_int_vect();
+
+	    ax = ((CARD16)(CurrentPci->bus) << 8)
+		| (CurrentPci->dev << 3) | (CurrentPci->func & 0x7);
+	    P_printf("ax: 0x%x\n",ax);
+
+	    if (!((mapPciRom(NULL) && chksum((CARD8*)V_BIOS))
+		  || (CurrentPci->active && copy_vbios()))) {
+		CurrentPci = CurrentPci->next;
+		continue;
+	    }
+	    if (!map_vram()) {
+		CurrentPci = CurrentPci->next;
+		continue;
+	    }
+	    if (Config.SaveBios) save_bios_to_file();
+	    printf("initializing PCI bus: %i dev: %i func: %i\n",CurrentPci->bus,
+		   CurrentPci->dev,CurrentPci->func);
+	    bootBIOS(ax);
+	    unmap_vram();
+
+	    CurrentPci = CurrentPci->next;
+	}
+
+	/* We have an ISA device - configure if requested */
+	if (!Active_is_Pci && Config.ConfigActiveDevice) {
+	    pciVideoDisable();
+
+	    outb(0x102, save_pos102);
+	    outb(0x46e8, save_46e8);
+	    outb(0x3C3, save_vse);
+	    outb(0x3C2, save_msr);
+
+	    setup_int_vect();
+	    if (copy_vbios()) {
+
+		if (Config.SaveBios) save_bios_to_file();
+		if  (map_vram()) {
+		    printf("initializing ISA\n");
+		    bootBIOS(0);
+		}
+	    }
+
+	    unmap_vram();
+	    sleep(1);
+	}
+
+	pciVideoRestore();
+
+	outb(0x102, save_pos102);
+	outb(0x46e8, save_46e8);
+	outb(0x3C3, save_vse);
+	outb(0x3C2, save_msr);
+    }
+
+    close_console(Console);
+#ifdef DELETE
+    iopl(0);
+    unmap();
+
+    printf("done !\n");
+#endif
+    if (Config.IoStatistics)
+	io_statistics();
+#ifdef DELETE
+    exit(0);
+#endif
+}
+
+int
+map(void)
+{
+    void* mem;
+
+    mem = mmap(0, (size_t)SIZE,
+	       PROT_EXEC | PROT_READ | PROT_WRITE,
+	       MAP_FIXED | MAP_PRIVATE | MAP_ANON,
+	       -1, 0 );
+    if (mem != 0) {
+	perror("anonymous map");
+	return (0);
+    }
+    memset(mem,0,SIZE);
+
+    loadCodeToMem((unsigned char *) BIOS_START, code);
+    return (1);
+}
+
+static void
+unmap(void)
+{
+    munmap(0,SIZE);
+}
+
+static void
+bootBIOS(CARD16 ax)
+{
+    i86biosRegs bRegs;
+#ifdef V86BIOS_DEBUG
+    printf("starting BIOS\n");
+#endif
+    setup_bios_regs(&bRegs, ax);
+    do_x86(BIOS_START,&bRegs);
+#ifdef V86BIOS_DEBUG
+    printf("done\n");
+#endif
+}
+
+static int
+map_vram(void)
+{
+    int mem_fd;
+
+#ifdef __ia64__
+    if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0)
+#else
+    if ((mem_fd = open(MEM_FILE,O_RDWR))<0)
+#endif
+      {
+	perror("opening memory");
+	return 0;
+    }
+
+#ifndef __alpha__
+    if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE,
+		     PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED,
+		     mem_fd, VRAM_START) == (void *) -1)
+#else
+	 if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */
+	 if (!_bus_base_sparse()) sparse_shift = 0;
+	 if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift),
+						 PROT_READ | PROT_WRITE,
+						 MAP_SHARED,
+						 mem_fd, (VRAM_START << sparse_shift)
+						 | _bus_base_sparse())) == (void *) -1)
+#endif
+      {
+	perror("mmap error in map_hardware_ram");
+	    close(mem_fd);
+	    return (0);
+	}
+    vram_mapped = 1;
+    close(mem_fd);
+    return (1);
+}
+
+static void
+unmap_vram(void)
+{
+    if (!vram_mapped) return;
+
+    munmap((void*)VRAM_START,VRAM_SIZE);
+    vram_mapped = 0;
+}
+
+static int
+copy_vbios(void)
+{
+    int mem_fd;
+    unsigned char *tmp;
+    int size;
+
+    if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) {
+	perror("opening memory");
+	return (0);
+    }
+
+    if (lseek(mem_fd,(off_t) V_BIOS, SEEK_SET) != (off_t) V_BIOS) {
+	  fprintf(stderr,"Cannot lseek\n");
+	  goto Error;
+      }
+    tmp = (unsigned char *)malloc(3);
+    if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) {
+	    fprintf(stderr,"Cannot read\n");
+	goto Error;
+    }
+    if (lseek(mem_fd,(off_t) V_BIOS,SEEK_SET) != (off_t) V_BIOS)
+	goto Error;
+
+    if (*tmp != 0x55 || *(tmp+1) != 0xAA ) {
+#ifdef DEBUG
+	dprint((unsigned long)tmp,0x100);
+#endif
+	fprintf(stderr,"No bios found at: 0x%x\n",V_BIOS);
+	goto Error;
+    }
+    size = *(tmp+2) * 512;
+
+    if (read(mem_fd, (char *)V_BIOS, (size_t) size) != (size_t) size) {
+	    fprintf(stderr,"Cannot read\n");
+	goto Error;
+    }
+    free(tmp);
+    close(mem_fd);
+    if (!chksum((CARD8)V_BIOS))
+	return (0);
+
+    return (1);
+
+Error:
+    perror("v_bios");
+    close(mem_fd);
+    return (0);
+}
+
+static int
+copy_sys_bios(void)
+{
+#define SYS_BIOS 0xF0000
+    int mem_fd;
+
+    if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) {
+	perror("opening memory");
+	return (0);
+    }
+
+    if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS)
+	goto Error;
+    if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF)
+	goto Error;
+
+    close(mem_fd);
+    return (1);
+
+Error:
+    perror("sys_bios");
+    close(mem_fd);
+    return (0);
+}
+
+void
+loadCodeToMem(unsigned char *ptr, CARD8 code[])
+{
+    int i;
+    CARD8 val;
+
+    for ( i=0;;i++) {
+	val = code[i];
+	*ptr++ = val;
+	if (val == 0xf4) break;
+    }
+    return;
+}
+
+void
+dprint(unsigned long start, unsigned long size)
+{
+    int i,j;
+    char *c = (char *)start;
+
+    for (j = 0; j < (size >> 4); j++) {
+    char *d = c;
+    printf("\n0x%lx:  ",(unsigned long)c);
+    for (i = 0; i<16; i++)
+	printf("%2.2x ",(unsigned char) (*(c++)));
+    c = d;
+    for (i = 0; i<16; i++) {
+	printf("%c",((((CARD8)(*c)) > 32) && (((CARD8)(*c)) < 128)) ?
+	   (unsigned char) (*(c)): '.');
+	c++;
+    }
+    }
+    printf("\n");
+}
+
+static void
+save_bios_to_file(void)
+{
+    static int num = 0;
+    int size, count;
+    char file_name[256];
+    int fd;
+
+    sprintf(file_name,"bios_%i.fil",num);
+    if ((fd =  open(file_name,O_WRONLY | O_CREAT | O_TRUNC,00644)) == -1)
+	return;
+    size = (*(unsigned char*)(V_BIOS + 2)) * 512;
+#ifdef V86BIOS_DEBUG
+    dprint(V_BIOS,20);
+#endif
+    if ((count = write(fd,(void *)(V_BIOS),size)) != size)
+	fprintf(stderr,"only saved %i of %i bytes\n",size,count);
+    num++;
+}
+
+static void
+sig_handler(int unused)
+{
+    fflush(stdout);
+    fflush(stderr);
+
+    /* put system back in a save state */
+    unmap_vram();
+    pciVideoRestore();
+    outb(0x102, save_pos102);
+    outb(0x46e8, save_46e8);
+    outb(0x3C3, save_vse);
+    outb(0x3C2, save_msr);
+
+    close_console(Console);
+    iopl(0);
+    unmap();
+
+    exit(1);
+}
+
+/*
+ * For initialization we just pass ax to the BIOS.
+ * PCI BIOSes need this. All other register are set 0.
+ */
+static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax)
+{
+    regs->ax = ax;
+    regs->bx = 0;
+    regs->cx = 0;
+    regs->dx = 0;
+    regs->es = 0;
+    regs->di = 0;
+}
+
+/*
+ * here we are really paranoid about faking a "real"
+ * BIOS. Most of this information was pulled from
+ * dosem.
+ */
+static void
+setup_int_vect(void)
+{
+    const CARD16 cs = 0x0000;
+    const CARD16 ip = 0x0;
+    int i;
+
+    /* let the int vects point to the SYS_BIOS seg */
+    for (i=0; i<0x80; i++) {
+	((CARD16*)0)[i<<1] = ip;
+	((CARD16*)0)[(i<<1)+1] = cs;
+    }
+    /* video interrupts default location */
+    ((CARD16*)0)[(0x42<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x42<<1] = 0xf065;
+    ((CARD16*)0)[(0x10<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x10<<1] = 0xf065;
+    /* video param table default location (int 1d) */
+    ((CARD16*)0)[(0x1d<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x1d<<1] = 0xf0A4;
+    /* font tables default location (int 1F) */
+    ((CARD16*)0)[(0x1f<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x1f<<1] = 0xfa6e;
+
+    /* int 11 default location */
+    ((CARD16*)0)[(0x11<1)+1] = 0xf000;
+    ((CARD16*)0)[0x11<<1] = 0xf84d;
+    /* int 12 default location */
+    ((CARD16*)0)[(0x12<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x12<<1] = 0xf841;
+    /* int 15 default location */
+    ((CARD16*)0)[(0x15<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x15<<1] = 0xf859;
+    /* int 1A default location */
+    ((CARD16*)0)[(0x1a<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x1a<<1] = 0xff6e;
+    /* int 05 default location */
+    ((CARD16*)0)[(0x05<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x05<<1] = 0xff54;
+    /* int 08 default location */
+    ((CARD16*)0)[(0x8<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x8<<1] = 0xfea5;
+    /* int 13 default location (fdd) */
+    ((CARD16*)0)[(0x13<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x13<<1] = 0xec59;
+    /* int 0E default location */
+    ((CARD16*)0)[(0xe<<1)+1] = 0xf000;
+    ((CARD16*)0)[0xe<<1] = 0xef57;
+    /* int 17 default location */
+    ((CARD16*)0)[(0x17<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x17<<1] = 0xefd2;
+    /* fdd table default location (int 1e) */
+    ((CARD16*)0)[(0x1e<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x1e<<1] = 0xefc7;
+}
+
+static int
+setup_system_bios(void)
+{
+    char *date = "06/01/99";
+    char *eisa_ident = "PCI/ISA";
+
+#if MAP_SYS_BIOS
+    if (!copy_sys_bios()) return 0;
+    return 1;
+#endif
+/*    memset((void *)0xF0000,0xf4,0xfff7); */
+
+    /*
+     * we trap the "industry standard entry points" to the BIOS
+     * and all other locations by filling them with "hlt"
+     * TODO: implement hlt-handler for these
+     */
+    memset((void *)0xF0000,0xf4,0x10000);
+
+    /*
+     * TODO: we should copy the fdd table (0xfec59-0xfec5b)
+     * the video parameter table (0xf0ac-0xf0fb)
+     * and the font tables (0xfa6e-0xfe6d)
+     * from the original bios here
+     */
+
+    /* set bios date */
+    strcpy((char *)0xFFFF5,date);
+    /* set up eisa ident string */
+    strcpy((char *)0xFFFD9,eisa_ident);
+    /* write system model id for IBM-AT */
+    ((char *)0)[0xFFFFE] = 0xfc;
+
+    return 1;
+}
+
+static int
+chksum(CARD8 *start)
+{
+  CARD16 size;
+  CARD8 val = 0;
+  int i;
+
+  size = *(start+2) * 512;
+  for (i = 0; i<size; i++)
+    val += *(start + i);
+
+  if (!val)
+    return 1;
+
+    fprintf(stderr,"BIOS cksum wrong!\n");
+  return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/makefile.linux b/board/MAI/bios_emulator/scitech/src/v86bios/makefile.linux
new file mode 100755
index 0000000..5dfe306
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/makefile.linux
@@ -0,0 +1,59 @@
+CFLAGS=-g -I/usr/include -I../../include/ -O0 -Wall
+CC=gcc
+
+.y.c:
+    bison -d -o $@ $<
+.l.c:
+    flex -o$@ $< 
+
+SRCS = main.c io.c x86emu.c int.c pci.c
+OBJS = main.o io.o x86emu.o int.o pci.o
+
+all : vbios.vm86 v86bios.vm86 cbios.vm86 cbios.x86emu vbios.x86emu v86bios.x86emu 
+#all :  cbios.x86emu vbios.x86emu v86bios.x86emu 
+
+parser.c : parser.y
+lex.c : lex.l
+cbios.o : cbios.c v86bios.h debug.h
+main.o : main.c v86bios.h pci.h debug.h
+io.o : v86bios.h AsmMacros.h debug.h
+mem.o : mem.c debug.h v86bios.h
+int.o : int.c v86bios.h debug.h
+pci.o : pci.c pci.h debug.h
+console.o : console.c v86bios.h debug.h
+v86.o : v86.c debug.h
+parser.o : parser.c
+lex.o : lex.c
+v86bios.o: v86bios.c v86bios.h pci.h debug.h
+logging.o: logging.c v86bios.h
+x86emu.o : x86emu.c v86bios.h debug.h
+    $(CC) -c -DX86EMU $(CFLAGS) $*.c
+
+vbios.x86emu : main.o x86emu.o io.o int.o pci.o console.o mem.o logging.o
+    gcc -Wl,-defsym -Wl,printk=lprintf -o vbios.x86emu main.o \
+    x86emu.o io.o int.o pci.o console.o mem.o logging.o \
+    -L../x86emu -lx86emud -lc 
+vbios.vm86 : main.o v86.o io.o int.o pci.o console.o logging.o
+    gcc -o vbios.vm86 main.o v86.o io.o int.o pci.o console.o \
+    logging.o -lc 
+cbios.x86emu : cbios.o x86emu.o io.o int.o pci.o console.o mem.o logging.o
+    gcc -Wl,-defsym -Wl,printk=lprintf -o cbios.x86emu cbios.o \
+    x86emu.o io.o int.o pci.o console.o mem.o logging.o \
+    -L../x86emu -lx86emud -lc 
+cbios.vm86 : cbios.o v86.o io.o int.o pci.o console.o logging.o
+    gcc -o cbios.vm86 cbios.o v86.o io.o int.o pci.o console.o \
+    logging.o -lc 
+v86bios.vm86: command.o parser.o lex.o v86bios.o v86.o io.o int.o pci.o console.o logging.o
+     gcc -o v86bios.vm86 command.o parser.o lex.o v86bios.o v86.o io.o \
+     int.o pci.o console.o logging.o -L/usr/lib/curses -lfl \
+     -lreadline -lc -lncurses /usr/lib/libc.a
+v86bios.x86emu: command.o parser.o lex.o v86bios.o x86emu.o io.o int.o pci.o console.o logging.o
+    gcc -Wl,-defsym -Wl,printk=lprintf -o v86bios.x86emu \
+    command.o parser.o lex.o v86bios.o x86emu.o io.o \
+    int.o pci.o console.o logging.o -L/usr/lib/curses -lfl \
+    -lreadline -lc -lncurses  /usr/lib/libc.a -L../x86emu -lx86emud
+
+clean:
+    rm -f *.o vbios.x86emu vbios.vm86 cbios.x86emu cbios.vm86 parser.c \
+    lex.c parser.h v86bios.x86emu v86bios.vm86
+
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/mem.c b/board/MAI/bios_emulator/scitech/src/v86bios/mem.c
new file mode 100755
index 0000000..24c1aef
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/mem.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "debug.h"
+#include "v86bios.h"
+#include "x86emu.h"
+
+#ifdef __alpha__
+
+void* vram_map = 0;
+int sparse_shift = 5;
+
+#define mem_barrier()        __asm__ __volatile__("mb"  : : : "memory")
+
+#define vuip    volatile unsigned int *
+
+CARD8
+mem_rb(CARD32 addr)
+{
+  unsigned long result, shift;
+#if 1
+  if (addr >= 0xA0000 && addr <= 0xBFFFF) {
+    addr -= 0xA0000;
+    shift = (addr & 0x3) * 8;
+    result = *(vuip) ((unsigned long)vram_map + (addr << sparse_shift));
+    result >>= shift;
+    return 0xffUL & result;
+  } else
+#endif
+    return rdb(addr);
+}
+
+CARD16
+mem_rw(CARD32 addr)
+{
+  unsigned long result, shift;
+#if 1
+  if (addr >= 0xA0000 && addr <= 0xBFFFF) {
+    addr -= 0xA0000;
+    shift = (addr & 0x2) * 8;
+    result = *(vuip)((unsigned long)vram_map+(addr<<sparse_shift)
+	     +(1<<(sparse_shift-2)));
+    result >>= shift;
+    return 0xffffUL & result;
+  } else
+#endif
+    return rdw(addr);
+}
+
+CARD32
+mem_rl(CARD32 addr)
+{
+  unsigned long result;
+#if 1
+  if (addr >= 0xA0000 && addr <= 0xBFFFF) {
+    addr -= 0xA0000;
+    result = *(vuip)((unsigned long)vram_map+(addr<<sparse_shift)+(3<<(sparse_shift-2)));
+    return result;
+  } else
+#endif
+    return rdl(addr);
+}
+
+void
+mem_wb(CARD32 addr, CARD8 val)
+{
+    unsigned int b = val & 0xffU;
+#if 1
+  if (addr >= 0xA0000 && addr <= 0xBFFFF) {
+    addr -= 0xA0000;
+    *(vuip) ((unsigned long)vram_map + (addr << sparse_shift)) = b * 0x01010101;
+    mem_barrier();
+  } else
+#endif
+    wrb(addr,val);
+}
+
+void
+mem_ww(CARD32 addr, CARD16 val)
+{
+  unsigned int w = val & 0xffffU;
+#if 1
+  if (addr >= 0xA0000 && addr <= 0xBFFFF) {
+    addr -= 0xA0000;
+    *(vuip)((unsigned long)vram_map+(addr<<sparse_shift)
+	+(1<<(sparse_shift-2))) = w * 0x00010001;
+    mem_barrier();
+  } else
+#endif
+    wrw(addr,val);
+}
+
+void
+mem_wl(CARD32 addr, CARD32 val)
+{
+#if 1
+  if (addr >= 0xA0000 && addr <= 0xBFFFF) {
+    addr -= 0xA0000;
+    *(vuip)((unsigned long)vram_map+(addr<<sparse_shift)
+	+(3<<(sparse_shift-2))) = val;
+    mem_barrier();
+  } else
+#endif
+    wrl(addr,val);
+}
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/parser.y b/board/MAI/bios_emulator/scitech/src/v86bios/parser.y
new file mode 100755
index 0000000..21c4023
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/parser.y
@@ -0,0 +1,498 @@
+%{
+#include <malloc.h>
+#include <string.h>
+#include "v86bios.h"
+#include "pci.h"
+    
+#define YYSTYPE unsigned long
+    
+#define MAX_VAR 0x20
+
+    CARD32 var[MAX_VAR];
+    CARD32 var_mem;
+
+
+i86biosRegs regs = { 00 };
+
+enum mem_type { BYTE, WORD, LONG, STRING };
+union mem_val {
+   CARD32 integer;
+   char *ptr;
+} rec;
+
+struct mem {
+    enum mem_type type;
+        union mem_val val;
+    struct mem *next;
+}; 
+
+ 
+struct device Device = {FALSE,NONE,{0}};
+
+extern void yyerror(char *s);
+extern int yylex( void  );
+ 
+static void boot(void);
+static void dump_mem(CARD32 addr, int len);
+static void exec_int(int num);
+static void *add_to_list(enum mem_type type, union mem_val *rec, void *next);
+static void do_list(struct mem *list, memType addr);
+static char * normalize_string(char *ptr);
+%}
+
+%token TOK_NUM
+%token TOK_REG_AX
+%token TOK_REG_BX
+%token TOK_REG_CX
+%token TOK_REG_DX
+%token TOK_REG_DI
+%token TOK_REG_SI
+%token TOK_SEG_DS
+%token TOK_SEG_ES
+%token TOK_SEP
+%token TOK_VAR
+%token TOK_VAR_MEM
+%token TOK_COMMAND_BOOT
+%token TOK_COMMAND_EXEC
+%token TOK_SELECT
+%token TOK_STRING
+%token TOK_MODIFIER_BYTE
+%token TOK_MODIFIER_WORD
+%token TOK_MODIFIER_LONG
+%token TOK_MODIFIER_MEMSET
+%token TOK_COMMAND_MEMSET
+%token TOK_COMMAND_MEMDUMP
+%token TOK_COMMAND_QUIT
+%token TOK_ERROR
+%token TOK_END
+%token TOK_ISA
+%token TOK_PCI
+%token TOK_BYTE
+%token TOK_WORD
+%token TOK_LONG
+%token TOK_PRINT_PORT
+%token TOK_IOSTAT
+%token TOK_PRINT_IRQ
+%token TOK_PPCI
+%token TOK_PIP
+%token TOK_TRACE
+%token TOK_ON
+%token TOK_OFF
+%token TOK_VERBOSE
+%token TOK_LOG
+%token TOK_LOGOFF
+%token TOK_CLSTAT
+%token TOK_STDOUT
+%token TOK_HLT
+%token TOK_DEL
+%token TOK_IOPERM
+%token TOK_DUMP_PCI
+%token TOK_BOOT_BIOS
+%%
+input:        | input line  
+line:          end |  com_reg | com_var | com_select
+              | com_boot | com_memset | com_memdump  | com_quit 
+              | com_exec | hlp | config | verbose | logging | print | clstat 
+              | com_hlt | ioperm | list_pci | boot_bios 
+              | error end  { printf("unknown command\n"); }
+;
+end:           TOK_END
+;
+com_reg:        reg_off val end { *(CARD16*)$1 = $2 & 0xffff; }
+              | reg_seg TOK_SEP reg_off val end {
+                               *(CARD16*)$1 = ($4 & 0xf0000) >> 4;
+                                       *(CARD16*)$3 = ($4 & 0x0ffff);
+                                        }
+              |  reg_off '?' end { printf("0x%x\n",*(CARD16*)$1);}
+              |  reg_seg TOK_SEP reg_off '?' end
+                                     { printf("0x%x:0x%x\n",*(CARD16*)$1,
+                          *(CARD16*)$3); }
+;
+register_read:  reg_seg TOK_SEP reg_off { $$ = (((*(CARD16*)$1) << 4) 
+                                                | ((*(CARD16*)$3) & 0xffff));
+                                        }
+              | reg_off          { $$ = ((*(CARD16*)$1) & 0xffff); }
+;
+reg_off:        TOK_REG_AX  { $$ = (unsigned long)&(regs.ax); }
+              | TOK_REG_BX  { $$ = (unsigned long)&(regs.bx); }
+              | TOK_REG_CX  { $$ = (unsigned long)&(regs.cx); }
+              | TOK_REG_DX  { $$ = (unsigned long)&(regs.dx); }
+              | TOK_REG_DI  { $$ = (unsigned long)&(regs.di); }
+              | TOK_REG_SI  { $$ = (unsigned long)&(regs.si); }
+;
+reg_seg:        TOK_SEG_DS  { $$ = (unsigned long)&(regs.ds); }
+              | TOK_SEG_ES  { $$ = (unsigned long)&(regs.es); }
+;
+com_var:        TOK_VAR_MEM '?' end { printf("var mem: 0x%x\n",var_mem); }
+          | TOK_VAR '?' end { if ($1 < MAX_VAR)
+          printf("var[%i]: 0x%x\n",(int)$1,var[$1]);
+          else
+          printf("var index %i out of range\n",(int)$1); }
+          | TOK_VAR_MEM val end { var_mem = $2; }    
+              | TOK_VAR val end    { if ($1 <= MAX_VAR)
+                                 var[$1] = $2;
+                              else 
+                                     printf("var index %i out of range\n",(int)$1); }
+              | TOK_VAR error  end { printf("$i val\n"); }
+              | TOK_VAR_MEM error  end { printf("$i val\n"); }
+;
+com_boot:       TOK_COMMAND_BOOT  end { boot(); }
+                TOK_COMMAND_BOOT error end { boot(); }
+;
+com_select:     TOK_SELECT TOK_ISA end { Device.booted = FALSE;
+                                         Device.type = ISA;
+                     CurrentPci = NULL; }   
+              | TOK_SELECT TOK_PCI val TOK_SEP val TOK_SEP val end
+                                    { Device.booted = FALSE;
+                      Device.type = PCI; 
+                                      Device.loc.pci.bus = $3;
+                                      Device.loc.pci.dev = $5; 
+                                      Device.loc.pci.func = $7; }
+              | TOK_SELECT '?' end
+                                   { switch (Device.type) {
+                                     case ISA:
+                                       printf("isa\n");
+                                       break;
+                                     case PCI:
+                                      printf("pci: %x:%x:%x\n",Device.loc.pci.bus,
+                                              Device.loc.pci.dev,
+                          Device.loc.pci.func);
+                                      break;
+                                 default:
+                                      printf("no device selected\n");
+                                      break;
+                                     }
+                                    }
+              | TOK_SELECT error end { printf("select ? | isa "
+                                         "| pci:bus:dev:func\n"); }
+;
+com_quit:       TOK_COMMAND_QUIT end { return 0; }
+              | TOK_COMMAND_QUIT error end { logoff(); return 0; }
+;
+com_exec:       TOK_COMMAND_EXEC end { exec_int(0x10); }
+          | TOK_COMMAND_EXEC val end { exec_int($2); }
+          | TOK_COMMAND_EXEC error end { exec_int(0x10); }
+;
+com_memdump:    TOK_COMMAND_MEMDUMP val val end { dump_mem($2,$3); }
+              | TOK_COMMAND_MEMDUMP  error  end { printf("memdump start len\n"); }
+
+    
+;
+com_memset:     TOK_COMMAND_MEMSET val list end { do_list((struct mem*)$3,$2);}
+              | TOK_COMMAND_MEMSET error end { printf("setmem addr [byte val] "
+                                                   "[word val] [long val] "
+                                                   "[\"string\"]\n"); }
+;
+list:                              { $$ = 0; } 
+              | TOK_BYTE val list { rec.integer = $2;
+          $$ = (unsigned long)add_to_list(BYTE,&rec,(void*)$3); }
+              | TOK_WORD val list { rec.integer = $2; 
+          $$ = (unsigned long) add_to_list(WORD,&rec,(void*)$3); }
+              | TOK_LONG val list { rec.integer = $2; 
+          $$ = (unsigned long) add_to_list(LONG,&rec,(void*)$3); }
+              | TOK_STRING list { rec.ptr = (void*)$1; 
+          $$ = (unsigned long) add_to_list(STRING,&rec,(void*)$2); }
+;
+val:            TOK_VAR  {  if ($1 > MAX_VAR) {
+                             printf("variable index out of range\n");
+                             $$=0;
+                             } else 
+                            $$ = var[$1]; } 
+              | TOK_NUM  {  $$ = $1; }
+              | register_read
+; 
+bool:           TOK_ON   {  $$ = 1; }
+              | TOK_OFF  {  $$ = 0; }
+;
+config:         TOK_PRINT_PORT bool end { Config.PrintPort = $2; } 
+              | TOK_PRINT_PORT '?' end  { printf("print port %s\n",
+                                      Config.PrintPort?"on":"off"); }
+          | TOK_PRINT_PORT error end { printf("pport on | off | ?\n") } 
+              | TOK_PRINT_IRQ bool end  { Config.PrintIrq = $2; } 
+              | TOK_PRINT_IRQ '?' end   { printf("print irq %s\n",  
+                                          Config.PrintIrq?"on":"off"); } 
+          | TOK_PRINT_IRQ error end { printf("pirq on | off | ?\n") } 
+              | TOK_PPCI bool end       { Config.PrintPci = $2; } 
+              | TOK_PPCI '?' end        { printf("print PCI %s\n",
+                                          Config.PrintPci?"on":"off"); } 
+          | TOK_PPCI error end      { printf("ppci on | off | ?\n") } 
+              | TOK_PIP bool end        { Config.PrintIp = $2; } 
+              | TOK_PIP '?' end         { printf("printip %s\n",
+                                      Config.PrintIp?"on":"off"); } 
+          | TOK_PIP error end       { printf("pip on | off | ?\n") } 
+              | TOK_IOSTAT bool end     { Config.IoStatistics = $2; } 
+              | TOK_IOSTAT '?' end      { printf("io statistics %s\n",
+                                      Config.IoStatistics?"on":"off"); } 
+          | TOK_IOSTAT error end    { printf("iostat on | off | ?\n") } 
+              | TOK_TRACE bool end      { Config.Trace = $2; } 
+              | TOK_TRACE '?' end       { printf("trace %s\n",
+                                      Config.Trace ?"on":"off"); } 
+          | TOK_TRACE error end { printf("trace on | off | ?\n") } 
+;
+verbose:        TOK_VERBOSE val end     { Config.Verbose = $2; }
+          | TOK_VERBOSE '?' end     { printf("verbose: %i\n",
+                            Config.Verbose); }
+          | TOK_VERBOSE error end   { printf("verbose val | ?\n"); }
+;
+logging:        TOK_LOG TOK_STRING end  { logon(normalize_string((char*)$2)); }
+          | TOK_LOG '?' end         { if (logging) printf("logfile: %s\n",
+                            logfile);
+                      else printf("no logging\n?"); }
+          | TOK_LOG TOK_OFF end          { logoff(); }
+          | TOK_LOG error end       { printf("log \"<filename>\" | ? |"
+                         " off\n"); }
+;
+clstat:         TOK_CLSTAT end          { clear_stat(); }
+          | TOK_CLSTAT error end    { printf("clstat\n"); } 
+;
+print:          TOK_STDOUT bool end     { nostdout = !$2; }
+                  | TOK_STDOUT '?' end      { printf("print %s\n",nostdout ?
+                        "no":"yes"); }
+          | TOK_STDOUT error end    { printf("print on | off\n"); }
+;
+com_hlt:            TOK_HLT val end         { add_hlt($2); }    
+          | TOK_HLT TOK_DEL val end { del_hlt($3); }
+          | TOK_HLT TOK_DEL end     { del_hlt(21); }
+              | TOK_HLT '?' end         { list_hlt(); }
+          | TOK_HLT error end       { printf(
+                                               "hlt val | del [val] | ?\n"); }
+;
+ioperm:         TOK_IOPERM val val val end { int i,max;
+                                             if ($2 >= 0) {
+                                 max = $2 + $3 - 1;
+                             if (max > IOPERM_BITS) 
+                             max = IOPERM_BITS;
+                                 for (i = $2;i <= max; i++)
+                                ioperm_list[i] 
+                                                                = $4>0 ? 1 : 0;
+                          }
+                                           }
+          | TOK_IOPERM '?' end { int i,start;
+                     for (i=0; i <= IOPERM_BITS; i++) {
+                    if (ioperm_list[i]) {
+                       start = i;
+                       for (; i <= IOPERM_BITS; i++) 
+                        if (!ioperm_list[i]) {
+                         printf("ioperm on in "
+                         "0x%x+0x%x\n", start,i-start);
+                         break;
+                        }
+                         }
+                     }
+                                  }
+          | TOK_IOPERM error end { printf("ioperm start len val\n"); }
+;
+list_pci:      TOK_DUMP_PCI end       { list_pci(); }
+             | TOK_DUMP_PCI error end { list_pci(); }
+;
+boot_bios:     TOK_BOOT_BIOS '?' end { if (!BootBios) printf("No Boot BIOS\n");
+                                   else printf("BootBIOS from: %i:%i:%i\n",
+                           BootBios->bus, BootBios->dev,
+                           BootBios->func); }
+             | TOK_BOOT_BIOS error end { printf ("bootbios bus:dev:num\n"); }
+;
+hlp:         '?'  { printf("Command list:\n");
+                    printf(" select isa | pci bus:dev:func\n");
+            printf(" boot\n");
+            printf(" seg:reg val | reg val \n");
+            printf(" $x val | $mem val\n");
+            printf(" setmem addr list; addr := val\n");
+            printf(" dumpmem addr len; addr,len := val\n");
+            printf(" do [val]\n");
+            printf(" quit\n");
+            printf(" ?\n");
+            printf(" seg := ds | es;"
+               " reg := ax | bx | cx | dx | si \n");
+            printf(" val := var | <hex-number> | seg:reg | seg\n");
+            printf(" var := $x | $mem; x := 0..20\n");
+            printf(" list := byte val | word val | long val "
+               "| \"string\"\n");
+                printf(" pport on | off | ?\n");
+                printf(" ppci on | off | ?\n");
+                printf(" pirq on | off | ?\n");
+                printf(" pip on | off | ?\n");
+                printf(" trace on | off | ?\n");
+                printf(" iostat on | off | ?\n");
+            printf(" verbose val\n");
+            printf(" log \"<filename>\" | off | ?\n");
+            printf(" print on | off\n");
+            printf(" hlt val | del [val] | ?\n");
+            printf(" clstat\n");
+            printf(" lpci\n");
+            printf ("bootbios ?\n");
+}
+;
+
+%%
+
+static void
+dump_mem(CARD32 addr, int len)
+{
+    dprint(addr,len);
+}
+
+static void
+exec_int(int num)
+{
+    if (num == 0x10) {  /* video interrupt */
+    if (Device.type == NONE) {
+        CurrentPci = PciList;
+        while (CurrentPci) {
+        if (CurrentPci->active)
+            break;
+        CurrentPci = CurrentPci->next;
+        }
+        if (!CurrentPci)
+        Device.type = ISA;
+        else {
+        Device.type = PCI;
+        Device.loc.pci.dev = CurrentPci->dev;
+        Device.loc.pci.bus = CurrentPci->bus;
+        Device.loc.pci.func = CurrentPci->func;
+        }
+    }
+        if (Device.type != ISA) {
+       if (!Device.booted) {
+              if (!CurrentPci || (Device.type == PCI
+               && (!CurrentPci->active
+                   && (Device.loc.pci.dev != CurrentPci->dev
+                 || Device.loc.pci.bus != CurrentPci->bus
+                 || Device.loc.pci.func != CurrentPci->func)))) {
+                printf("boot the device fist\n");
+            return;
+          }
+           }
+    } else
+       CurrentPci = NULL;
+    } else {
+    Device.booted = FALSE; /* we need this for sanity! */
+    }
+    
+    runINT(num,&regs);
+}
+
+static void
+boot(void)
+{
+    if (Device.type == NONE) {
+    printf("select a device fist\n");
+    return;
+    }
+    
+    call_boot(&Device);
+}
+
+static void *
+add_to_list(enum mem_type type, union mem_val *rec, void *next)
+{
+    struct mem *mem_rec = (struct mem *) malloc(sizeof(mem_rec));
+
+    mem_rec->type = type;
+    mem_rec->next = next;
+    
+    switch (type) {
+    case BYTE:
+    case WORD:
+    case LONG:
+    mem_rec->val.integer = rec->integer;
+       break;
+    case STRING:
+    mem_rec->val.ptr = normalize_string(rec->ptr);
+    break;
+    }
+    return mem_rec;
+}
+
+static int
+validRange(int addr,int len)
+{
+    int end = addr + len;
+
+    if (addr < 0x1000 || end > 0xc0000)
+    return 0;
+    return 1;
+}
+
+static void
+do_list(struct mem *list, memType addr)
+{
+   struct mem *prev;
+   int len;
+   
+   while (list) {
+    switch (list->type) {
+         case BYTE:
+         if (!validRange(addr,1)) goto error;
+         *(CARD8*)addr = list->val.integer;
+         addr =+ 1;
+             break;     
+         case WORD:
+         if (!validRange(addr,2)) goto error;
+         *(CARD16*)addr = list->val.integer;
+         addr =+ 2;
+             break;     
+         case LONG:
+         if (!validRange(addr,4)) goto error;
+         *(CARD32*)addr = list->val.integer;
+         addr =+ 4;
+             break;
+         case STRING:
+         len = strlen((char*)list->val.ptr);
+         if (!validRange(addr,len)) goto error;
+         memcpy((CARD8*)addr,(void*)list->val.ptr,len);
+         addr =+ len;
+             free(list->val.ptr);
+             break;
+       }     
+       prev = list;
+       list = list->next;
+       free(prev);
+       continue;
+   error:
+       printf("address out of range\n");
+       while (list) {
+       prev = list;
+       list = list->next;
+       free(prev);
+       }
+       break;
+   }
+}
+
+static char *
+normalize_string(char *ptr)
+{
+    int i = 0, j = 0, c = 0, esc= 0;
+    int size;
+    char *mem_ptr;
+    
+    size = strlen(ptr);
+    mem_ptr = malloc(size);
+    while (1) {
+        switch (*(ptr + i)) {
+        case '\\':
+            if (esc) {
+                *(mem_ptr + j++) = *(ptr + i);
+                esc = 0;
+            } else 
+                esc = 1;
+            break;
+        case '\"':
+            if (esc) {
+                *(mem_ptr + j++) = *(ptr + i);
+                esc = 0;
+            } else 
+                c++;
+            break;
+        default:
+            *(mem_ptr + j++) = *(ptr + i);
+            break;
+        }
+        if (c > 1) {
+            *(mem_ptr + j) = '\0';     
+            break;
+        }
+        i++;
+    }
+    return mem_ptr;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/pci.c b/board/MAI/bios_emulator/scitech/src/v86bios/pci.c
new file mode 100755
index 0000000..b58a571
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/pci.c
@@ -0,0 +1,902 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "debug.h"
+#include <fcntl.h>
+#include <unistd.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <string.h>
+#if defined (__alpha__) || defined (__ia64__)
+#include <sys/io.h>
+#endif
+#include "AsmMacros.h"
+
+#include "pci.h"
+
+/*
+ * I'm rather simple mindend - therefore I do a poor man's
+ * pci scan without all the fancy stuff that is done in
+ * scanpci. However that's all we need.
+ */
+
+PciStructPtr PciStruct = NULL;
+PciBusPtr PciBuses = NULL;
+PciStructPtr CurrentPci = NULL;
+PciStructPtr PciList = NULL;
+PciStructPtr BootBios = NULL;
+int pciMaxBus = 0;
+
+static CARD32 PciCfg1Addr;
+
+static void readConfigSpaceCfg1(CARD32 bus, CARD32 dev, CARD32 func,
+		CARD32 *reg);
+static int checkSlotCfg1(CARD32 bus, CARD32 dev, CARD32 func);
+static int checkSlotCfg2(CARD32 bus, int dev);
+static void readConfigSpaceCfg2(CARD32 bus, int dev, CARD32 *reg);
+static CARD8 interpretConfigSpace(CARD32 *reg, int busidx,
+		  CARD8 dev, CARD8 func);
+static CARD32 findBIOSMap(PciStructPtr pciP, CARD32 *biosSize);
+static void restoreMem(PciStructPtr pciP);
+
+
+#ifdef __alpha__
+#define PCI_BUS_FROM_TAG(tag)  (((tag) & 0x00ff0000) >> 16)
+#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00) >> 8)
+
+#include <asm/unistd.h>
+
+CARD32
+axpPciCfgRead(CARD32 tag)
+{
+    int bus, dfn;
+    CARD32 val = 0xffffffff;
+
+    bus = PCI_BUS_FROM_TAG(tag);
+    dfn = PCI_DFN_FROM_TAG(tag);
+
+    syscall(__NR_pciconfig_read, bus, dfn, tag & 0xff, 4, &val);
+    return(val);
+}
+
+void
+axpPciCfgWrite(CARD32 tag, CARD32 val)
+{
+    int bus, dfn;
+
+    bus = PCI_BUS_FROM_TAG(tag);
+    dfn = PCI_DFN_FROM_TAG(tag);
+
+    syscall(__NR_pciconfig_write, bus, dfn, tag & 0xff, 4, &val);
+}
+
+static CARD32 (*readPci)(CARD32 reg) = axpPciCfgRead;
+static void (*writePci)(CARD32 reg, CARD32 val) = axpPciCfgWrite;
+#else
+static CARD32 readPciCfg1(CARD32 reg);
+static void writePciCfg1(CARD32 reg, CARD32 val);
+static CARD32 readPciCfg2(CARD32 reg);
+static void writePciCfg2(CARD32 reg, CARD32 val);
+
+static CARD32 (*readPci)(CARD32 reg) = readPciCfg1;
+static void (*writePci)(CARD32 reg, CARD32 val) = writePciCfg1;
+#endif
+
+#if defined(__alpha__) || defined(__sparc__)
+#define PCI_EN 0x00000000
+#else
+#define PCI_EN 0x80000000
+#endif
+
+
+static int numbus;
+static int hostbridges = 1;
+static unsigned long pciMinMemReg = ~0;
+
+
+void
+scan_pci(void)
+{
+    unsigned short configtype;
+
+    CARD32 reg[64];
+    int busidx;
+    CARD8 cardnum;
+    CARD8 func;
+    int idx;
+
+    int i;
+    PciStructPtr pci1;
+    PciBusPtr pci_b1,pci_b2;
+
+#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc__) || defined(__ia64__)
+    configtype = 1;
+#else
+    CARD8 tmp1, tmp2;
+    CARD32 tmp32_1, tmp32_2;
+    outb(PCI_MODE2_ENABLE_REG, 0x00);
+    outb(PCI_MODE2_FORWARD_REG, 0x00);
+    tmp1 = inb(PCI_MODE2_ENABLE_REG);
+    tmp2 = inb(PCI_MODE2_FORWARD_REG);
+    if ((tmp1 == 0x00) && (tmp2 == 0x00)) {
+	configtype = 2;
+	readPci = readPciCfg2;
+	writePci = writePciCfg2;
+	P_printf("PCI says configuration type 2\n");
+    } else {
+	tmp32_1 = inl(PCI_MODE1_ADDRESS_REG);
+	outl(PCI_MODE1_ADDRESS_REG, PCI_EN);
+	tmp32_2 = inl(PCI_MODE1_ADDRESS_REG);
+	outl(PCI_MODE1_ADDRESS_REG, tmp32_1);
+	if (tmp32_2 == PCI_EN) {
+	    configtype = 1;
+	    P_printf("PCI says configuration type 1\n");
+	} else {
+	    P_printf("No PCI !\n");
+	    return;
+	}
+    }
+#endif
+
+    if (configtype == 1) {
+	P_printf("PCI probing configuration type 1\n");
+	busidx = 0;
+	numbus = 1;
+	idx = 0;
+	do {
+	    P_printf("\nProbing for devices on PCI bus %d:\n", busidx);
+	    for (cardnum = 0; cardnum < MAX_DEV_PER_VENDOR_CFG1; cardnum++) {
+		func = 0;
+		do {
+		    /* loop over the different functions, if present */
+		    if (!checkSlotCfg1(busidx,cardnum,func))
+			break;
+		    readConfigSpaceCfg1(busidx,cardnum,func,reg);
+
+		    func = interpretConfigSpace(reg,busidx,
+						cardnum,func);
+
+		    if (idx++ > MAX_PCI_DEVICES)
+			continue;
+		} while (func < 8);
+	    }
+	} while (++busidx < PCI_MAXBUS);
+#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc__) || defined(__ia64__)
+	/* don't use outl()  ;-) */
+#else
+	outl(PCI_MODE1_ADDRESS_REG, 0);
+#endif
+    } else {
+	int slot;
+
+	P_printf("PCI probing configuration type 2\n");
+	busidx = 0;
+	numbus = 1;
+	idx = 0;
+	do {
+	    for (slot=0xc0; slot<0xd0; i++) {
+		if (!checkSlotCfg2(busidx,slot))
+		    break;
+		readConfigSpaceCfg2(busidx,slot,reg);
+
+		interpretConfigSpace(reg,busidx,
+				     slot,0);
+		if (idx++ > MAX_PCI_DEVICES)
+		    continue;
+	    }
+	}  while (++busidx < PCI_MAXBUS);
+    }
+
+
+    pciMaxBus = numbus - 1;
+    P_printf("Number of buses in system: %i\n",pciMaxBus + 1);
+    P_printf("Min PCI mem address: 0x%lx\n",pciMinMemReg);
+
+    /* link buses */
+    pci_b1 = PciBuses;
+    while (pci_b1) {
+	pci_b2 = PciBuses;
+	pci_b1->pBus = NULL;
+	while (pci_b2) {
+	    if (pci_b1->primary == pci_b2->secondary)
+		pci_b1->pBus = pci_b2;
+	    pci_b2 = pci_b2->next;
+	}
+	pci_b1 = pci_b1->next;
+    }
+    pci1 = PciStruct;
+    while (pci1) {
+	pci_b2 = PciBuses;
+	pci1->pBus = NULL;
+	while (pci_b2) {
+	    if (pci1->bus == pci_b2->secondary)
+		pci1->pBus = pci_b2;
+	    pci_b2 = pci_b2->next;
+	}
+	pci1 = pci1->next;
+    }
+    if (RESORT) {
+	PciStructPtr tmp = PciStruct, tmp1;
+	PciStruct = NULL;
+	while (tmp) {
+	    tmp1 = tmp->next;
+	    tmp->next = PciStruct;
+	    PciStruct = tmp;
+	    tmp = tmp1;
+	}
+    }
+    PciList = CurrentPci = PciStruct;
+}
+
+#ifndef __alpha__
+static CARD32
+readPciCfg1(CARD32 reg)
+{
+    CARD32 val;
+
+    outl(PCI_MODE1_ADDRESS_REG, reg);
+    val = inl(PCI_MODE1_DATA_REG);
+    outl(PCI_MODE1_ADDRESS_REG, 0);
+    P_printf("reading: 0x%x from 0x%x\n",val,reg);
+    return val;
+}
+
+static void
+writePciCfg1(CARD32 reg, CARD32 val)
+{
+    P_printf("writing: 0x%x to 0x%x\n",val,reg);
+    outl(PCI_MODE1_ADDRESS_REG, reg);
+    outl(PCI_MODE1_DATA_REG,val);
+    outl(PCI_MODE1_ADDRESS_REG, 0);
+}
+
+static CARD32
+readPciCfg2(CARD32 reg)
+{
+    CARD32 val;
+    CARD8 bus = (reg >> 16) & 0xff;
+    CARD8 dev = (reg >> 11) & 0x1f;
+    CARD8 num = reg & 0xff;
+
+    outb(PCI_MODE2_ENABLE_REG, 0xF1);
+    outb(PCI_MODE2_FORWARD_REG, bus);
+    val = inl((dev << 8) + num);
+    outb(PCI_MODE2_ENABLE_REG, 0x00);
+    P_printf("reading: 0x%x from 0x%x\n",val,reg);
+    return val;
+}
+
+static void
+writePciCfg2(CARD32 reg, CARD32 val)
+{
+    CARD8 bus = (reg >> 16) & 0xff;
+    CARD8 dev = (reg >> 11) & 0x1f;
+    CARD8 num = reg & 0xff;
+
+    P_printf("writing: 0x%x to 0x%x\n",val,reg);
+    outb(PCI_MODE2_ENABLE_REG, 0xF1);
+    outb(PCI_MODE2_FORWARD_REG, bus);
+    outl((dev << 8) + num,val);
+    outb(PCI_MODE2_ENABLE_REG, 0x00);
+}
+#endif
+
+void
+pciVideoDisable(void)
+{
+    /* disable VGA routing on bridges */
+    PciBusPtr pbp = PciBuses;
+    PciStructPtr pcp = PciStruct;
+
+    while (pbp) {
+	writePci(pbp->Slot.l | 0x3c, pbp->bctl & ~(CARD32)(8<<16));
+	pbp = pbp->next;
+    }
+    /* disable display devices */
+    while (pcp) {
+	writePci(pcp->Slot.l | 0x04, pcp->cmd_st & ~(CARD32)3);
+	writePci(pcp->Slot.l | 0x30, pcp->RomBase & ~(CARD32)1);
+	pcp = pcp->next;
+    }
+}
+
+void
+pciVideoRestore(void)
+{
+    /* disable VGA routing on bridges */
+    PciBusPtr pbp = PciBuses;
+    PciStructPtr pcp = PciStruct;
+
+    while (pbp) {
+	writePci(pbp->Slot.l | 0x3c, pbp->bctl);
+	pbp = pbp->next;
+    }
+    /* disable display devices */
+    while (pcp) {
+	writePci(pcp->Slot.l | 0x04, pcp->cmd_st);
+	writePci(pcp->Slot.l | 0x30, pcp->RomBase);
+	pcp = pcp->next;
+    }
+}
+
+void
+EnableCurrent()
+{
+    PciBusPtr pbp;
+    PciStructPtr pcp = CurrentPci;
+
+    pciVideoDisable();
+
+    pbp = pcp->pBus;
+    while (pbp) { /* enable bridges */
+	writePci(pbp->Slot.l | 0x3c, pbp->bctl | (CARD32)(8<<16));
+	pbp = pbp->pBus;
+    }
+    writePci(pcp->Slot.l | 0x04, pcp->cmd_st | (CARD32)3);
+    writePci(pcp->Slot.l | 0x30, pcp->RomBase | (CARD32)1);
+}
+
+CARD8
+PciRead8(int offset, CARD32 Slot)
+{
+    int shift = offset & 0x3;
+    offset = offset & 0xFC;
+    return ((readPci(Slot | offset) >> (shift << 3)) & 0xff);
+}
+
+CARD16
+PciRead16(int offset, CARD32 Slot)
+{
+    int shift = offset & 0x2;
+    offset = offset & 0xFC;
+    return ((readPci(Slot | offset) >> (shift << 3)) & 0xffff);
+}
+
+CARD32
+PciRead32(int offset, CARD32 Slot)
+{
+    offset = offset & 0xFC;
+    return (readPci(Slot | offset));
+}
+
+void
+PciWrite8(int offset, CARD8 byte, CARD32 Slot)
+{
+    CARD32 val;
+    int shift = offset & 0x3;
+    offset = offset & 0xFC;
+    val = readPci(Slot | offset);
+    val &= ~(CARD32)(0xff << (shift << 3));
+    val |= byte << (shift << 3);
+    writePci(Slot | offset, val);
+}
+
+void
+PciWrite16(int offset, CARD16 word, CARD32 Slot)
+{
+    CARD32 val;
+    int shift = offset & 0x2;
+    offset = offset & 0xFC;
+    val = readPci(Slot | offset);
+    val &= ~(CARD32)(0xffff << (shift << 3));
+    val |= word << (shift << 3);
+    writePci(Slot | offset, val);
+}
+
+void
+PciWrite32(int offset, CARD32 lg, CARD32 Slot)
+{
+    offset = offset & 0xFC;
+    writePci(Slot | offset, lg);
+}
+
+int
+mapPciRom(PciStructPtr pciP)
+{
+    unsigned long RomBase = 0;
+    int mem_fd;
+    unsigned char *mem, *ptr;
+    unsigned char *scratch = NULL;
+    int length = 0;
+    CARD32 biosSize = 0x1000000;
+    CARD32 enablePci;
+
+    if (!pciP)
+      pciP = CurrentPci;
+
+    if (FIX_ROM) {
+	RomBase = findBIOSMap(pciP, &biosSize);
+	if (!RomBase) {
+	    fprintf(stderr,"Cannot remap BIOS of %i:%i:%i "
+		    "- trying preset address\n",pciP->bus,pciP->dev,
+		    pciP->func);
+	    RomBase = pciP->RomBase & ~(CARD32)0xFF;
+	}
+    }  else {
+	RomBase = pciP->RomBase & ~(CARD32)0xFF;
+	if (~RomBase + 1 < biosSize || !RomBase)
+	    RomBase = findBIOSMap(pciP, &biosSize);
+    }
+
+    P_printf("RomBase: 0x%lx\n",RomBase);
+
+    if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) {
+	perror("opening memory");
+	restoreMem(pciP);
+	return (0);
+    }
+
+    PciWrite32(0x30,RomBase | 1,pciP->Slot.l);
+
+#ifdef __alpha__
+    mem = ptr = (unsigned char *)mmap(0, biosSize, PROT_READ,
+				      MAP_SHARED, mem_fd, RomBase | _bus_base());
+#else
+    mem = ptr = (unsigned char *)mmap(0, biosSize, PROT_READ,
+				      MAP_SHARED, mem_fd, RomBase);
+#endif
+    if (pciP != CurrentPci) {
+      enablePci = PciRead32(0x4,pciP->Slot.l);
+      PciWrite32(0x4,enablePci | 0x2,pciP->Slot.l);
+    }
+
+#ifdef PRINT_PCI
+    dprint((unsigned long)ptr,0x30);
+#endif
+    while ( *ptr == 0x55 && *(ptr+1) == 0xAA) {
+	unsigned short data_off = *(ptr+0x18) | (*(ptr+0x19)<< 8);
+	unsigned char *data = ptr + data_off;
+	unsigned char type;
+	int i;
+
+	if (*data!='P' || *(data+1)!='C' || *(data+2)!='I' || *(data+3)!='R') {
+	    break;
+	}
+	type = *(data + 0x14);
+	P_printf("data segment in BIOS: 0x%x, type: 0x%x ",data_off,type);
+
+	if (type != 0)  { /* not PC-AT image: find next one */
+	    unsigned int image_length;
+	    unsigned char indicator = *(data + 0x15);
+	    if (indicator & 0x80) /* last image */
+		break;
+	    image_length = (*(data + 0x10)
+			    | (*(data + 0x11) << 8)) << 9;
+	    P_printf("data image length: 0x%x, ind: 0x%x\n",
+		     image_length,indicator);
+	    ptr = ptr + image_length;
+	    continue;
+	}
+	/* OK, we have a PC Image */
+	length = (*(ptr + 2) << 9);
+	P_printf("BIOS length: 0x%x\n",length);
+	scratch = (unsigned char *)malloc(length);
+	/* don't use memcpy() here: Reading from bus! */
+	for (i=0;i<length;i++)
+	    *(scratch + i)=*(ptr + i);
+	break;
+    }
+
+    if (pciP != CurrentPci)
+      PciWrite32(0x4,enablePci,pciP->Slot.l);
+
+    /* unmap/close/disable PCI bios mem */
+    munmap(mem, biosSize);
+    close(mem_fd);
+    /* disable and restore mapping */
+    writePci(pciP->Slot.l | 0x30, pciP->RomBase & ~(CARD32)1);
+
+    if (scratch && length) {
+	memcpy((unsigned char *)V_BIOS, scratch, length);
+	free(scratch);
+    }
+
+    restoreMem(pciP);
+    return length;
+}
+
+CARD32
+findPci(CARD16 slotBX)
+{
+    CARD32 slot = slotBX << 8;
+
+    if (slot == (CurrentPci->Slot.l & ~PCI_EN))
+	return (CurrentPci->Slot.l | PCI_EN);
+    else {
+#if !SHOW_ALL_DEV
+	PciBusPtr pBus = CurrentPci->pBus;
+	while (pBus) {
+	  /*      fprintf(stderr,"slot: 0x%x  bridge: 0x%x\n",slot, pBus->Slot.l); */
+	    if (slot == (pBus->Slot.l & ~PCI_EN))
+		return pBus->Slot.l | PCI_EN;
+	    pBus = pBus->next;
+	}
+#else
+	PciStructPtr pPci = PciStruct;
+	while (pPci) {
+	  /*fprintf(stderr,"slot: 0x%x  bridge: 0x%x\n",slot, pPci->Slot.l); */
+	    if (slot == (pPci->Slot.l & ~PCI_EN))
+		return pPci->Slot.l | PCI_EN;
+	    pPci = pPci->next;
+	}
+#endif
+    }
+    return 0;
+}
+
+CARD16
+pciSlotBX(PciStructPtr pPci)
+{
+    return (CARD16)((pPci->Slot.l >> 8) & 0xFFFF);
+}
+
+PciStructPtr
+findPciDevice(CARD16 vendorID, CARD16 deviceID, char n)
+{
+    PciStructPtr pPci = CurrentPci;
+    n++;
+
+    while (pPci)  {
+	if ((pPci->VendorID == vendorID) && (pPci->DeviceID == deviceID)) {
+	if (!(--n)) break;
+	}
+    pPci = pPci->next;
+    }
+    return pPci;
+}
+
+PciStructPtr
+findPciClass(CARD8 intf, CARD8 subClass, CARD16 class, char n)
+{
+    PciStructPtr pPci = CurrentPci;
+    n++;
+
+    while (pPci)  {
+	if ((pPci->Interface == intf) && (pPci->SubClass == subClass)
+	 && (pPci->BaseClass == class)) {
+	if (!(--n)) break;
+	}
+    pPci = pPci->next;
+    }
+    return pPci;
+}
+
+static void
+readConfigSpaceCfg1(CARD32 bus, CARD32 dev, CARD32 func, CARD32 *reg)
+{
+    CARD32   config_cmd = PCI_EN | (bus<<16) |
+      (dev<<11) | (func<<8);
+    int i;
+
+    for (i = 0; i<64;i+=4) {
+#ifdef __alpha__
+	reg[i] = axpPciCfgRead(config_cmd | i);
+#else
+	outl(PCI_MODE1_ADDRESS_REG, config_cmd | i);
+	reg[i] = inl(PCI_MODE1_DATA_REG);
+#endif
+
+#ifdef V86BIOS_DEBUG
+	P_printf("0x%lx\n",reg[i]);
+#endif
+    }
+}
+
+static int
+checkSlotCfg1(CARD32 bus, CARD32 dev, CARD32 func)
+{
+    CARD32    config_cmd = PCI_EN | (bus<<16) |
+      (dev<<11) | (func<<8);
+    CARD32 reg;
+#ifdef __alpha__
+	reg = axpPciCfgRead(config_cmd);
+#else
+	outl(PCI_MODE1_ADDRESS_REG, config_cmd);
+	reg = inl(PCI_MODE1_DATA_REG);
+#endif
+    if (reg != 0xFFFFFFFF)
+	return 1;
+    else
+	return 0;
+}
+
+static int
+checkSlotCfg2(CARD32 bus, int dev)
+{
+    CARD32 val;
+
+    outb(PCI_MODE2_ENABLE_REG, 0xF1);
+    outb(PCI_MODE2_FORWARD_REG, bus);
+    val = inl(dev << 8);
+    outb(PCI_MODE2_FORWARD_REG, 0x00);
+    outb(PCI_MODE2_ENABLE_REG, 0x00);
+    if (val == 0xFFFFFFFF)
+	return 0;
+    if (val == 0xF0F0F0F0)
+	return 0;
+    return 1;
+}
+
+static void
+readConfigSpaceCfg2(CARD32 bus, int dev, CARD32 *reg)
+{
+    int i;
+
+    outb(PCI_MODE2_ENABLE_REG, 0xF1);
+    outb(PCI_MODE2_FORWARD_REG, bus);
+    for (i = 0; i<64;i+=4) {
+	reg[i] = inl((dev << 8) + i);
+#ifdef V86BIOS_DEBUG
+	P_printf("0x%lx\n",reg[i]);
+#endif
+    }
+    outb(PCI_MODE2_ENABLE_REG, 0x00);
+}
+
+static CARD8
+interpretConfigSpace(CARD32 *reg, int busidx, CARD8 dev, CARD8 func)
+{
+    CARD32 config_cmd;
+    CARD16 vendor, device;
+    CARD8 baseclass, subclass;
+    CARD8 primary, secondary;
+    CARD8 header, interface;
+    int i;
+
+    config_cmd = PCI_EN | busidx<<16 |
+	(dev<<11) | (func<<8);
+
+    for (i = 0x10; i < 0x28; i+=4) {
+	if (IS_MEM32(reg[i]))
+	    if ((reg[i] & 0xFFFFFFF0) < pciMinMemReg)
+		pciMinMemReg = (reg[i] & 0xFFFFFFF0);
+#ifdef __alpha__
+	if (IS_MEM64(reg[i])) {
+		unsigned long addr = reg[i] |
+	      (unsigned long)(reg[i+4]) << 32;
+	    if ((addr & ~0xfL) < pciMinMemReg)
+		pciMinMemReg = (addr & ~0xfL);
+	    i+=4;
+	}
+#endif
+    }
+    vendor = reg[0] & 0xFFFF;
+    device = reg[0] >> 16;
+    P_printf("bus: %i card: %i func %i reg0: 0x%x ", busidx,dev,func,reg[0]);
+    baseclass = reg[8] >> 24;
+    subclass = (reg[8] >> 16) & 0xFF;
+    interface = (reg[8] >> 8) & 0xFF;
+
+    header = (reg[0x0c] >> 16) & 0xff;
+    P_printf("bc 0x%x, sub 0x%x, if 0x%x, hdr 0x%x\n",
+	     baseclass,subclass,interface,header);
+    if (BRIDGE_CLASS(baseclass)) {
+	if (BRIDGE_PCI_CLASS(subclass)) {
+	    PciBusPtr pbp = malloc(sizeof(PciBusRec));
+	    P_printf("Pci-Pci Bridge found; ");
+	    primary = reg[0x18] & 0xFF;
+	    secondary = (reg[0x18] >> 8) & 0xFF;
+	    P_printf("primary: 0x%x secondary: 0x%x\n",
+		     primary,secondary);
+	    pbp->bctl = reg[0x3c];
+	    pbp->primary = primary;
+	    pbp->secondary = secondary;
+	    pbp->Slot.l = config_cmd;
+	    pbp->next = PciBuses;
+	    PciBuses = pbp;
+	    numbus++;
+	} else if (BRIDGE_HOST_CLASS(subclass)
+		   && (hostbridges++ > 1)) {
+	    numbus++;
+	}
+    } else if (VIDEO_CLASS(baseclass,subclass)) {
+	PciStructPtr pcp = malloc(sizeof(PciStructRec));
+	P_printf("Display adapter found\n");
+	pcp->RomBase = reg[0x30];
+	pcp->cmd_st = reg[4];
+	pcp->active = (reg[4] & 0x03) == 3 ? 1 : 0;
+	pcp->VendorID = vendor;
+	pcp->DeviceID = device;
+	pcp->Interface = interface;
+	pcp->BaseClass = baseclass;
+	pcp->SubClass = subclass;
+	pcp->Slot.l = config_cmd;
+	pcp->bus = busidx;
+	pcp->dev = dev;
+	pcp->func = func;
+	pcp->next = PciStruct;
+	PciStruct = pcp;
+    }
+    if ((func == 0)
+	&& ((header & PCI_MULTIFUNC_DEV) == 0))
+	func = 8;
+    else
+	func++;
+    return func;
+}
+
+static CARD32 remapMEM_val;
+static int remapMEM_num;
+
+static int /* map it on some other video device */
+remapMem(PciStructPtr pciP, int num, CARD32 size)
+{
+    PciStructPtr pciPtr = PciStruct;
+    int i;
+    CARD32 org;
+    CARD32 val;
+    CARD32 size_n;
+
+    org = PciRead32(num + 0x10,pciP->Slot.l);
+
+    while (pciPtr) {
+	for (i = 0; i < 20; i=i+4) {
+
+	    val = PciRead32(i + 0x10,pciPtr->Slot.l);
+	    /* don't map it on itself */
+	    if ((org & 0xfffffff0) == (val & 0xfffffff0))
+		continue;
+	    if (val && !(val & 1))
+		PciWrite32(i + 0x10,0xffffffff,pciPtr->Slot.l);
+	    else
+		continue;
+	    size_n = PciRead32(i + 0x10,pciPtr->Slot.l);
+	    PciWrite32(i + 0x10,val,pciPtr->Slot.l);
+	    size_n = ~(CARD32)(size_n  & 0xfffffff0) + 1;
+
+	    if (size_n >= size) {
+		PciWrite32(num + 0x10,val,pciP->Slot.l);
+		return 1;
+	    }
+	}
+	pciPtr = pciPtr->next;
+    }
+    /* last resort: try to go below lowest PCI mem address */
+    val = ((pciMinMemReg & ~(CARD32)(size - 1)) - size);
+    if (val > 0x7fffffff) {
+	PciWrite32(num + 0x10,val, pciP->Slot.l);
+	return 1;
+    }
+
+    return 0;
+}
+
+static void
+restoreMem(PciStructPtr pciP)
+{
+    if (remapMEM_val == 0) return;
+    PciWrite32(remapMEM_num + 0x10,remapMEM_val,pciP->Slot.l);
+    return;
+}
+
+static CARD32
+findBIOSMap(PciStructPtr pciP, CARD32 *biosSize)
+{
+    PciStructPtr pciPtr = PciStruct;
+    int i;
+    CARD32 val;
+    CARD32 size;
+
+    PciWrite32(0x30,0xffffffff,pciP->Slot.l);
+    *biosSize = PciRead32(0x30,pciP->Slot.l);
+    P_printf("bios size: 0x%x\n",*biosSize);
+    PciWrite32(0x30,pciP->RomBase,pciP->Slot.l);
+    *biosSize = ~(*biosSize & 0xFFFFFF00) + 1;
+    P_printf("bios size masked: 0x%x\n",*biosSize);
+    if (*biosSize > (1024 * 1024 * 16)) {
+      *biosSize = 1024 * 1024 * 16;
+      P_printf("fixing broken BIOS size: 0x%x\n",*biosSize);
+    }
+    while (pciPtr) {
+	if (pciPtr->bus != pciP->bus) {
+	    pciPtr = pciPtr->next;
+	    continue;
+	}
+	for (i = 0; i < 20; i=i+4) {
+
+	    val = PciRead32(i + 0x10,pciPtr->Slot.l);
+	    if (!(val & 1))
+
+	    PciWrite32(i + 0x10,0xffffffff,pciPtr->Slot.l);
+	    else
+		continue;
+	    size = PciRead32(i + 0x10,pciPtr->Slot.l);
+	    PciWrite32(i + 0x10,val,pciPtr->Slot.l);
+	    size = ~(CARD32)(size & 0xFFFFFFF0) + 1;
+#ifdef V86_BIOS_DEBUG
+	    P_printf("size: 0x%x\n",size);
+#endif
+	    if (size >= *biosSize) {
+		if (pciP == pciPtr) { /* if same device remap ram*/
+		    if (!(remapMem(pciP,i,size)))
+			continue;
+		    remapMEM_val = val;
+		    remapMEM_num = i;
+		} else {
+		    remapMEM_val = 0;
+		}
+		return val & 0xFFFFFF00;
+	    }
+	}
+	pciPtr = pciPtr->next;
+    }
+    remapMEM_val = 0;
+    /* very last resort */
+    if (pciP->bus == 0 && (pciMinMemReg > *biosSize))
+      return (pciMinMemReg - size) & ~(size - 1);
+
+    return 0;
+}
+
+int
+cfg1out(CARD16 addr, CARD32 val)
+{
+  if (addr == 0xCF8) {
+    PciCfg1Addr = val;
+    return 1;
+  } else if (addr == 0xCFC) {
+    writePci(PciCfg1Addr, val);
+    return 1;
+  }
+  return 0;
+}
+
+int
+cfg1in(CARD16 addr, CARD32 *val)
+{
+  if (addr == 0xCF8) {
+    *val = PciCfg1Addr;
+    return 1;
+  } else if (addr == 0xCFC) {
+    *val = readPci(PciCfg1Addr);
+    return 1;
+  }
+  return 0;
+}
+
+void
+list_pci(void)
+{
+    PciStructPtr pci = PciList;
+
+    while (pci) {
+    printf("[0x%x:0x%x:0x%x] vendor: 0x%4.4x dev: 0x%4.4x class: 0x%4.4x"
+	   " subclass: 0x%4.4x\n",pci->bus,pci->dev,pci->func,
+	   pci->VendorID,pci->DeviceID,pci->BaseClass,pci->SubClass);
+    pci = pci->next;
+    }
+}
+
+PciStructPtr
+findPciByIDs(int bus, int dev, int func)
+{
+  PciStructPtr pciP = PciList;
+
+  while (pciP) {
+    if (pciP->bus == bus && pciP->dev == dev && pciP->func == func)
+      return pciP;
+    pciP = pciP->next;
+  }
+  return NULL;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/pci.h b/board/MAI/bios_emulator/scitech/src/v86bios/pci.h
new file mode 100755
index 0000000..58ad522
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/pci.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "v86bios.h"
+
+#ifndef V86_PCI_H
+#define V86_PCI_H
+
+typedef union {
+    struct {
+	unsigned int    zero:2;
+	unsigned int    reg:6;
+	unsigned int    func:3;
+	unsigned int    dev:5;
+	unsigned int    bus:8;
+	unsigned int    reserved:7;
+	unsigned int    enable:1;
+    } pci;
+    CARD32 l;
+} PciSlot;
+
+typedef struct pciBusRec {
+    CARD8 primary;
+    CARD8 secondary;
+    CARD32 bctl;
+    PciSlot Slot;
+    struct pciBusRec *next;
+    struct pciBusRec *pBus;
+} PciBusRec, *PciBusPtr;
+
+typedef struct pciStructRec {
+    CARD16 VendorID;
+    CARD16 DeviceID;
+    CARD8 Interface;
+    CARD8 BaseClass;
+    CARD8 SubClass;
+    CARD32 RomBase;
+    CARD32 bus;
+    CARD8 dev;
+    CARD8 func;
+    CARD32 cmd_st;
+    int active;
+    PciSlot Slot;
+    struct pciStructRec *next;
+    PciBusPtr pBus;
+} PciStructRec , *PciStructPtr;
+
+
+extern PciStructPtr CurrentPci;
+extern PciStructPtr PciList;
+extern PciStructPtr BootBios;
+extern int pciMaxBus;
+
+extern CARD32 findPci(CARD16 slotBX);
+extern CARD16 pciSlotBX(PciStructPtr);
+PciStructPtr findPciDevice(CARD16 vendorID, CARD16 deviceID, char n);
+PciStructPtr findPciClass(CARD8 intf, CARD8 subClass, CARD16 class, char n);
+
+extern CARD8 PciRead8(int offset, CARD32 slot);
+extern CARD16 PciRead16(int offset, CARD32 slot);
+extern CARD32 PciRead32(int offset, CARD32 slot);
+
+extern void PciWrite8(int offset,CARD8 byte, CARD32 slot);
+extern void PciWrite16(int offset,CARD16 word, CARD32 slot);
+extern void PciWrite32(int offset,CARD32 lg, CARD32 slot);
+
+extern void scan_pci(void);
+extern void pciVideoDisable(void);
+extern void pciVideoRestore(void);
+extern void EnableCurrent(void);
+extern int mapPciRom(PciStructPtr pciP);
+extern int cfg1out(CARD16 addr, CARD32 val);
+extern int cfg1in(CARD16 addr, CARD32 *val);
+extern void list_pci(void);
+extern PciStructPtr findPciByIDs(int bus, int dev, int func);
+
+#define PCI_MODE2_ENABLE_REG  0xCF8
+#define PCI_MODE2_FORWARD_REG  0xCFA
+#define PCI_MODE1_ADDRESS_REG  0xCF8
+#define PCI_MODE1_DATA_REG  0xCFC
+#if defined(__alpha__) || defined(__sparc__)
+#define PCI_EN 0x00000000
+#else
+#define PCI_EN 0x80000000
+#endif
+#define MAX_DEV_PER_VENDOR_CFG1  32
+#define BRIDGE_CLASS(x) (x == 0x06)
+#define BRIDGE_PCI_CLASS(x) (x == 0x04)
+#define BRIDGE_HOST_CLASS(x) (x == 0x00)
+#define PCI_CLASS_PREHISTORIC 0x00
+#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
+#define PCI_CLASS_DISPLAY 0x03
+#define PCI_SUBCLASS_DISPLAY_VGA 0x00
+#define PCI_SUBCLASS_DISPLAY_XGA 0x01
+#define PCI_SUBCLASS_DISPLAY_MISC 0x80
+#define VIDEO_CLASS(b,s) \
+    (((b) == PCI_CLASS_PREHISTORIC && (s) == PCI_SUBCLASS_PREHISTORIC_VGA) || \
+     ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_VGA) ||\
+     ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_XGA) ||\
+     ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_MISC))
+#define PCI_MULTIFUNC_DEV  0x80
+#define MAX_PCI_DEVICES   64
+#define PCI_MAXBUS 16
+#define PCI_IS_MEM 0x00000001
+#define MAX_PCI_ROM_SIZE (1024 * 1024 * 16)
+
+#define IS_MEM32(x) ((x & 0x7) == 0 && x != 0)
+#define IS_MEM64(x) ((x & 0x7) == 0x4)
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86.c b/board/MAI/bios_emulator/scitech/src/v86bios/v86.c
new file mode 100755
index 0000000..4deed04
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/v86.c
@@ -0,0 +1,562 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "debug.h"
+#include <sys/vm86.h>
+#include <unistd.h>
+#include <errno.h>
+#include <asm/unistd.h>
+#include <stdio.h>
+#include <string.h>
+#include <signal.h>
+#include <setjmp.h>
+#include "v86bios.h"
+#include "AsmMacros.h"
+
+struct vm86_struct vm86s;
+
+static int vm86_GP_fault(void);
+static int vm86_do_int(int num);
+static void dump_code(void);
+static void dump_registers(void);
+static void stack_trace(void);
+static int vm86_rep(struct vm86_struct *ptr);
+
+#define CPU_REG(x) (vm86s.regs.##x)
+#define CPU_REG_LW(reg)      (*((CARD16 *)&CPU_REG(reg)))
+#define CPU_REG_HW(reg)      (*((CARD16 *)&CPU_REG(reg) + 1))
+#define CPU_REG_LB(reg)      (*(CARD8 *)&CPU_REG(e##reg))
+#define SEG_ADR(type, seg, reg)  type((CPU_REG_LW(seg) << 4) \
+				      + CPU_REG_LW(e##reg))
+#define DF (1 << 10)
+
+struct pio P;
+
+
+void
+setup_io(void)
+{
+    if (!Config.PrintPort && !Config.IoStatistics) {
+    P.inb = (CARD8(*)(CARD16))inb;
+    P.inw = (CARD16(*)(CARD16))inw;
+    P.inl = (CARD32(*)(CARD16))inl;
+    P.outb = (void(*)(CARD16,CARD8))outb;
+    P.outw = (void(*)(CARD16,CARD16))outw;
+    P.outl = (void(*)(CARD16,CARD32))outl;
+    } else {
+    P.inb = p_inb;
+    P.inw = p_inw;
+    P.inl = p_inl;
+    P.outb = p_outb;
+    P.outw = p_outw;
+    P.outl = p_outl;
+    }
+}
+
+
+static void
+setup_vm86(unsigned long bios_start, i86biosRegsPtr regs)
+{
+    CARD32 eip;
+    CARD16 cs;
+
+    vm86s.flags = VM86_SCREEN_BITMAP;
+    vm86s.flags = 0;
+    vm86s.screen_bitmap = 0;
+    vm86s.cpu_type = CPU_586;
+    memset(&vm86s.int_revectored, 0xff,sizeof(vm86s.int_revectored)) ;
+    memset(&vm86s.int21_revectored, 0xff,sizeof(vm86s.int21_revectored)) ;
+
+    eip = bios_start & 0xFFFF;
+    cs = (bios_start & 0xFF0000) >> 4;
+
+    CPU_REG(eax) = regs->ax;
+    CPU_REG(ebx) = regs->bx;
+    CPU_REG(ecx) = regs->cx;
+    CPU_REG(edx) = regs->dx;
+    CPU_REG(esi) = 0;
+    CPU_REG(edi) = regs->di;
+    CPU_REG(ebp) = 0;
+    CPU_REG(eip) = eip;
+    CPU_REG(cs) = cs;
+    CPU_REG(esp) = 0x100;
+    CPU_REG(ss) = 0x30;               /* This is the standard pc bios stack */
+    CPU_REG(es) = regs->es;
+    CPU_REG(ds) = 0x40;               /* standard pc ds */
+    CPU_REG(fs) = 0;
+    CPU_REG(gs) = 0;
+    CPU_REG(eflags) |= (VIF_MASK | VIP_MASK);
+}
+
+void
+collect_bios_regs(i86biosRegsPtr regs)
+{
+    regs->ax = CPU_REG(eax);
+    regs->bx = CPU_REG(ebx);
+    regs->cx = CPU_REG(ecx);
+    regs->dx = CPU_REG(edx);
+    regs->es = CPU_REG(es);
+    regs->ds = CPU_REG(ds);
+    regs->di = CPU_REG(edi);
+    regs->si = CPU_REG(esi);
+}
+
+static int
+do_vm86(void)
+{
+    int retval;
+
+#ifdef V86BIOS_DEBUG
+    dump_registers();
+#endif
+/*    retval = SYS_vm86old(&vm86s); */
+/*    retval = syscall(SYS_vm86old,&vm86s); */
+
+    retval = vm86_rep(&vm86s);
+
+    switch (VM86_TYPE(retval)) {
+    case VM86_UNKNOWN:
+	if (!vm86_GP_fault()) return 0;
+	break;
+    case VM86_STI:
+	fprintf(stderr,"vm86_sti :-((\n");
+	stack_trace();
+	dump_code();
+	return 0;
+    case VM86_INTx:
+	if (!vm86_do_int(VM86_ARG(retval))) {
+	    fprintf(stderr,"\nUnknown vm86_int: %X\n\n",VM86_ARG(retval));
+	    dump_registers();
+	    return 0;
+	}
+	/* I'm not sure yet what to do if we can handle ints */
+	break;
+    case VM86_SIGNAL:
+	fprintf(stderr,"received signal\n");
+	return 0;
+    default:
+	fprintf(stderr,"unknown type(0x%x)=0x%x\n",
+		VM86_ARG(retval),VM86_TYPE(retval));
+	dump_registers();
+	dump_code();
+	stack_trace();
+	return 0;
+    }
+
+    return 1;
+}
+
+static jmp_buf x86_esc;
+static void
+vmexit(int unused)
+{
+    longjmp(x86_esc,1);
+}
+
+void
+do_x86(unsigned long bios_start, i86biosRegsPtr regs)
+{
+    static void (*org_handler)(int);
+
+    setup_vm86(bios_start, regs);
+    if (setjmp(x86_esc) == 0) {
+	org_handler = signal(2,vmexit);
+	while(do_vm86()) {};
+	signal(2,org_handler);
+	collect_bios_regs(regs);
+    } else {
+	signal(2,org_handler);
+	printf("interrupted at 0x%x\n",((CARD16)CPU_REG(cs)) << 4
+	   | (CARD16)CPU_REG(eip));
+    }
+}
+
+/* get the linear address */
+#define LIN_PREF_SI  ((pref_seg << 4) + CPU_REG_LW(esi))
+
+#define LWECX       (prefix66 ^ prefix67 ? CPU_REG(ecx) : CPU_REG_LW(ecx))
+
+static int
+vm86_GP_fault(void)
+{
+    unsigned char *csp, *lina;
+    CARD32 org_eip;
+    int pref_seg;
+    int done,is_rep,prefix66,prefix67;
+
+
+    csp = lina = SEG_ADR((unsigned char *), cs, ip);
+#ifdef V86BIOS_DEBUG
+    printf("exception: \n");
+    dump_code();
+#endif
+
+    is_rep = 0;
+    prefix66 = prefix67 = 0;
+    pref_seg = -1;
+
+    /* eat up prefixes */
+    done = 0;
+    do {
+	switch (*(csp++)) {
+	case 0x66:      /* operand prefix */  prefix66=1; break;
+	case 0x67:      /* address prefix */  prefix67=1; break;
+	case 0x2e:      /* CS */              pref_seg=CPU_REG(cs); break;
+	case 0x3e:      /* DS */              pref_seg=CPU_REG(ds); break;
+	case 0x26:      /* ES */              pref_seg=CPU_REG(es); break;
+	case 0x36:      /* SS */              pref_seg=CPU_REG(ss); break;
+	case 0x65:      /* GS */              pref_seg=CPU_REG(gs); break;
+	case 0x64:      /* FS */              pref_seg=CPU_REG(fs); break;
+	case 0xf2:      /* repnz */
+	case 0xf3:      /* rep */             is_rep=1; break;
+	default: done=1;
+	}
+    } while (!done);
+    csp--;   /* oops one too many */
+    org_eip = CPU_REG(eip);
+    CPU_REG_LW(eip) += (csp - lina);
+
+    switch (*csp) {
+
+    case 0x6c:                    /* insb */
+	/* NOTE: ES can't be overwritten; prefixes 66,67 should use esi,edi,ecx
+	 * but is anyone using extended regs in real mode? */
+	/* WARNING: no test for DI wrapping! */
+	CPU_REG_LW(edi) += port_rep_inb(CPU_REG_LW(edx),
+					SEG_ADR((CARD8 *),es,di),
+					CPU_REG_LW(eflags)&DF,
+					(is_rep? LWECX:1));
+	if (is_rep) LWECX = 0;
+	CPU_REG_LW(eip)++;
+	break;
+
+    case 0x6d:                  /* (rep) insw / insd */
+	/* NOTE: ES can't be overwritten */
+	/* WARNING: no test for _DI wrapping! */
+	if (prefix66) {
+	    CPU_REG_LW(edi) += port_rep_inl(CPU_REG_LW(edx),
+					    SEG_ADR((CARD32 *),es,di),
+					    CPU_REG_LW(eflags)&DF,
+					    (is_rep? LWECX:1));
+	}
+	else {
+	    CPU_REG_LW(edi) += port_rep_inw(CPU_REG_LW(edx),
+					    SEG_ADR((CARD16 *),es,di),
+					    CPU_REG_LW(eflags)&DF,
+					    (is_rep? LWECX:1));
+	}
+	if (is_rep) LWECX = 0;
+	CPU_REG_LW(eip)++;
+	break;
+
+    case 0x6e:                  /* (rep) outsb */
+	if (pref_seg < 0) pref_seg = CPU_REG_LW(ds);
+	/* WARNING: no test for _SI wrapping! */
+	CPU_REG_LW(esi) += port_rep_outb(CPU_REG_LW(edx),(CARD8*)LIN_PREF_SI,
+					 CPU_REG_LW(eflags)&DF,
+					 (is_rep? LWECX:1));
+	if (is_rep) LWECX = 0;
+	CPU_REG_LW(eip)++;
+	break;
+
+    case 0x6f:                  /* (rep) outsw / outsd */
+	if (pref_seg < 0) pref_seg = CPU_REG_LW(ds);
+	/* WARNING: no test for _SI wrapping! */
+	if (prefix66) {
+	    CPU_REG_LW(esi) += port_rep_outl(CPU_REG_LW(edx),
+					     (CARD32 *)LIN_PREF_SI,
+					     CPU_REG_LW(eflags)&DF,
+					     (is_rep? LWECX:1));
+	}
+	else {
+	    CPU_REG_LW(esi) += port_rep_outw(CPU_REG_LW(edx),
+					     (CARD16 *)LIN_PREF_SI,
+					     CPU_REG_LW(eflags)&DF,
+					     (is_rep? LWECX:1));
+	}
+	if (is_rep) LWECX = 0;
+	CPU_REG_LW(eip)++;
+	break;
+
+    case 0xe5:                  /* inw xx, inl xx */
+	if (prefix66) CPU_REG(eax) = P.inl((int) csp[1]);
+	else CPU_REG_LW(eax) = P.inw((int) csp[1]);
+	CPU_REG_LW(eip) += 2;
+	break;
+    case 0xe4:                  /* inb xx */
+	CPU_REG_LW(eax) &= ~(CARD32)0xff;
+	CPU_REG_LB(ax) |= P.inb((int) csp[1]);
+	CPU_REG_LW(eip) += 2;
+	break;
+    case 0xed:                  /* inw dx, inl dx */
+	if (prefix66) CPU_REG(eax) = P.inl(CPU_REG_LW(edx));
+	else CPU_REG_LW(eax) = P.inw(CPU_REG_LW(edx));
+	CPU_REG_LW(eip) += 1;
+	break;
+    case 0xec:                  /* inb dx */
+	CPU_REG_LW(eax) &= ~(CARD32)0xff;
+	CPU_REG_LB(ax) |= P.inb(CPU_REG_LW(edx));
+	CPU_REG_LW(eip) += 1;
+	break;
+
+    case 0xe7:                  /* outw xx */
+	if (prefix66) P.outl((int)csp[1], CPU_REG(eax));
+	else P.outw((int)csp[1], CPU_REG_LW(eax));
+	CPU_REG_LW(eip) += 2;
+	break;
+    case 0xe6:                  /* outb xx */
+	P.outb((int) csp[1], CPU_REG_LB(ax));
+	CPU_REG_LW(eip) += 2;
+	break;
+    case 0xef:                  /* outw dx */
+	if (prefix66) P.outl(CPU_REG_LW(edx), CPU_REG(eax));
+	else P.outw(CPU_REG_LW(edx), CPU_REG_LW(eax));
+	CPU_REG_LW(eip) += 1;
+	break;
+    case 0xee:                  /* outb dx */
+	P.outb(CPU_REG_LW(edx), CPU_REG_LB(ax));
+	CPU_REG_LW(eip) += 1;
+	break;
+
+    case 0xf4:
+#ifdef V86BIOS_DEBUG
+	printf("hlt at %p\n", lina);
+#endif
+	return 0;
+
+    case 0x0f:
+	fprintf(stderr,"CPU 0x0f Trap at eip=0x%lx\n",CPU_REG(eip));
+	goto op0ferr;
+	break;
+
+    case 0xf0:                  /* lock */
+    default:
+	fprintf(stderr,"unknown reason for exception\n");
+	dump_registers();
+	stack_trace();
+    op0ferr:
+	dump_code();
+	fprintf(stderr,"cannot continue\n");
+	return 0;
+    }                           /* end of switch() */
+    return 1;
+}
+
+static int
+vm86_do_int(int num)
+{
+    int val;
+    struct regs86 regs;
+
+    i_printf("int 0x%x received: ax:0x%lx",num,CPU_REG(eax));
+    if (Config.PrintIp)
+	i_printf(" at: 0x%x\n",getIP());
+    else
+	i_printf("\n");
+
+    /* try to run bios interrupt */
+
+    /* if not installed fall back */
+#define COPY(x) regs.##x = CPU_REG(x)
+#define COPY_R(x) CPU_REG(x) = regs.##x
+
+    COPY(eax);
+    COPY(ebx);
+    COPY(ecx);
+    COPY(edx);
+    COPY(esi);
+    COPY(edi);
+    COPY(ebp);
+    COPY(eip);
+    COPY(esp);
+    COPY(cs);
+    COPY(ss);
+    COPY(ds);
+    COPY(es);
+    COPY(fs);
+    COPY(gs);
+    COPY(eflags);
+
+    if (!(val = int_handler(num,&regs)))
+	if (!(val = run_bios_int(num,&regs)))
+	    return val;
+
+    COPY_R(eax);
+    COPY_R(ebx);
+    COPY_R(ecx);
+    COPY_R(edx);
+    COPY_R(esi);
+    COPY_R(edi);
+    COPY_R(ebp);
+    COPY_R(eip);
+    COPY_R(esp);
+    COPY_R(cs);
+    COPY_R(ss);
+    COPY_R(ds);
+    COPY_R(es);
+    COPY_R(fs);
+    COPY_R(gs);
+    COPY_R(eflags);
+
+    return val;
+#undef COPY
+#undef COPY_R
+}
+
+static void
+dump_code(void)
+{
+    int i;
+    unsigned char *lina = SEG_ADR((unsigned char *), cs, ip);
+
+    fprintf(stderr,"code at 0x%8.8x: ",(CARD32)lina);
+    for (i=0; i<0x10; i++)
+	fprintf(stderr,"%2.2x ",*(lina + i));
+    fprintf(stderr,"\n                    ");
+    for (; i<0x20; i++)
+	fprintf(stderr,"%2.2x ",*(lina + i));
+    fprintf(stderr,"\n");
+}
+
+#define PRINT(x) fprintf(stderr,#x":%4.4x ",CPU_REG_LW(x))
+#define PRINT_FLAGS(x) fprintf(stderr,#x":%8.8x ",CPU_REG_LW(x))
+static void
+dump_registers(void)
+{
+    PRINT(eip);
+    PRINT(eax);
+    PRINT(ebx);
+    PRINT(ecx);
+    PRINT(edx);
+    PRINT(esi);
+    PRINT(edi);
+    PRINT(ebp);
+    fprintf(stderr,"\n");
+    PRINT(esp);
+    PRINT(cs);
+    PRINT(ss);
+    PRINT(es);
+    PRINT(ds);
+    PRINT(fs);
+    PRINT(gs);
+    PRINT_FLAGS(eflags);
+    fprintf(stderr,"\n");
+}
+
+static void
+stack_trace(void)
+{
+    int i;
+    unsigned char *stack = SEG_ADR((unsigned char *), ss, sp);
+
+    fprintf(stderr,"stack at 0x%8.8lx:\n",(unsigned long)stack);
+    for (i=0; i < 0x10; i++)
+	fprintf(stderr,"%2.2x ",*(stack + i));
+    fprintf(stderr,"\n");
+
+}
+
+static int
+vm86_rep(struct vm86_struct *ptr)
+{
+
+    int __res;
+
+    __asm__ __volatile__("int $0x80\n"
+			 :"=a" (__res):"a" ((int)113),
+			 "b" ((struct vm86_struct *)ptr));
+
+	    if ((__res) < 0) {
+		errno = -__res;
+		__res=-1;
+	    }
+	    else errno = 0;
+	    return __res;
+}
+
+#define pushw(base, ptr, val) \
+__asm__ __volatile__( \
+	"decw %w0\n\t" \
+	"movb %h2,(%1,%0)\n\t" \
+	"decw %w0\n\t" \
+	"movb %b2,(%1,%0)" \
+	: "=r" (ptr) \
+	: "r" (base), "q" (val), "0" (ptr))
+
+int
+run_bios_int(int num, struct regs86 *regs)
+{
+    CARD16 *ssp;
+    CARD32 sp;
+    CARD32 eflags;
+
+#ifdef V86BIOS_DEBUG
+    static int firsttime = 1;
+#endif
+    /* check if bios vector is initialized */
+    if (((CARD16*)0)[(num<<1)+1] == 0x0000) { /* SYS_BIOS_SEG ?*/
+#ifdef V86BIOS_DEBUG
+	i_printf("card BIOS not loaded\n");
+#endif
+	return 0;
+    }
+
+#ifdef V86BIOS_DEBUG
+    if (firsttime) {
+	dprint(0,0x3D0);
+	firsttime = 0;
+    }
+#endif
+
+    i_printf("calling card BIOS at: ");
+    ssp = (CARD16*)(CPU_REG(ss)<<4);
+    sp = (CARD32) CPU_REG_LW(esp);
+
+    eflags = regs->eflags;
+    eflags = ((eflags & VIF_MASK) != 0)
+	? (eflags | IF_MASK) : (eflags & ~(CARD32) IF_MASK);
+    pushw(ssp, sp, eflags);
+    pushw(ssp, sp, regs->cs);
+    pushw(ssp, sp, (CARD16)regs->eip);
+    regs->esp -= 6;
+    regs->cs = ((CARD16 *) 0)[(num << 1) + 1];
+    regs->eip = (regs->eip & 0xFFFF0000) | ((CARD16 *) 0)[num << 1];
+    i_printf("0x%x:%lx\n",regs->cs,regs->eip);
+#ifdef V86BIOS_DEBUG
+    dump_code();
+#endif
+    regs->eflags = regs->eflags
+		       & ~(VIF_MASK | TF_MASK | IF_MASK | NT_MASK);
+    return 1;
+}
+
+CARD32
+getIntVect(int num)
+{
+    return ((CARD32*)0)[num];
+}
+
+CARD32
+getIP(void)
+{
+    return (CPU_REG(cs) << 4) + CPU_REG(eip);
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c
new file mode 100755
index 0000000..101c1f2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c
@@ -0,0 +1,933 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#define DELETE
+#include <unistd.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/stat.h>
+#include <readline/readline.h>
+#include <readline/history.h>
+#if defined(__alpha__) || defined (__ia64__)
+#include <sys/io.h>
+#elif defined(HAVE_SYS_PERM)
+#include <sys/perm.h>
+#endif
+#include "debug.h"
+#include "v86bios.h"
+#include "pci.h"
+#include "AsmMacros.h"
+
+#define SIZE 0x100000
+#define VRAM_START 0xA0000
+#define VRAM_SIZE 0x1FFFF
+#define V_BIOS_SIZE 0x1FFFF
+#define BIOS_START 0x7C00            /* default BIOS entry */
+#define BIOS_MEM 0x600
+
+/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0, 0xf4 }; */
+#define VB_X(x) (V_BIOS >> x) & 0xFF
+CARD8 code[] = { 6, 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xf4 };
+/*CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xb8, 0x03, 0x00, */
+/*0xcd, 0x10, 0xf4 }; */
+/*CARD8 code[] = {  0xb8 , 0xf0 , 0xf0 ,0xf4 }; */
+
+int ioperm_list[IOPERM_BITS] = {0,};
+
+static void sig_handler(int);
+static int map(void);
+static void unmap(void);
+static void bootBIOS(CARD16 ax);
+static int map_vram(void);
+static void unmap_vram(void);
+static int copy_vbios(memType v_base);
+static int copy_sys_bios(void);
+static void save_bios_to_file(void);
+static int setup_system_bios(void);
+static CARD32 setup_int_vect(void);
+#ifdef __ia32__
+static CARD32 setup_primary_int_vect(void);
+#endif
+static int chksum(CARD8 *start);
+static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax);
+static void print_regs(i86biosRegsPtr regs);
+static void print_usage(void);
+static void set_hlt(Bool set);
+static void set_ioperm(void);
+
+extern void yyparse();
+
+void loadCodeToMem(unsigned char *ptr, CARD8 *code);
+void dprint(unsigned long start, unsigned long size);
+
+static int vram_mapped = 0;
+static char* bios_var = NULL;
+static CARD8 save_msr;
+static CARD8 save_pos102;
+static CARD8 save_vse;
+static CARD8 save_46e8;
+static haltpoints hltp[20] = { {0, 0}, };
+
+console Console = {-1,-1};
+struct config Config;
+
+int main(int argc,char **argv)
+{
+    int c;
+
+    Config.PrintPort = PRINT_PORT;
+    Config.IoStatistics = IO_STATISTICS;
+    Config.PrintIrq = PRINT_IRQ;
+    Config.PrintPci = PRINT_PCI;
+    Config.ShowAllDev = SHOW_ALL_DEV;
+    Config.PrintIp = PRINT_IP;
+    Config.SaveBios = SAVE_BIOS;
+    Config.Trace = TRACE;
+    Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY;  /* boot */
+    Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; /* boot */
+    Config.MapSysBios = MAP_SYS_BIOS;
+    Config.Resort = RESORT;  /* boot */
+    Config.FixRom = FIX_ROM;
+    Config.NoConsole = NO_CONSOLE;
+    Config.BootOnly = FALSE;
+    Config.Verbose = VERBOSE;
+
+    opterr = 0;
+    while ((c = getopt(argc,argv,"psicaPStAdbrfnv:?")) != EOF) {
+    switch(c) {
+    case 'p':
+	Config.PrintPort = TRUE;
+	break;
+    case 's':
+	Config.IoStatistics = TRUE;
+	break;
+    case 'i':
+	Config.PrintIrq = TRUE;
+	break;
+    case 'c':
+	Config.PrintPci = TRUE;
+	break;
+    case 'a':
+	Config.ShowAllDev = TRUE;
+	break;
+    case 'P':
+	Config.PrintIp = TRUE;
+	break;
+    case 'S':
+	Config.SaveBios = TRUE;
+	break;
+    case 't':
+	Config.Trace = TRUE;
+	break;
+    case 'A':
+	Config.ConfigActiveOnly = TRUE;
+	break;
+    case 'd':
+	Config.ConfigActiveDevice = TRUE;
+	break;
+    case 'b':
+	Config.MapSysBios = TRUE;
+	break;
+    case 'r':
+	Config.Resort = TRUE;
+	break;
+    case 'f':
+	Config.FixRom = TRUE;
+	break;
+    case 'n':
+	Config.NoConsole = TRUE;
+	break;
+    case 'v':
+	Config.Verbose = strtol(optarg,NULL,0);
+	break;
+    case '?':
+	print_usage();
+	break;
+    default:
+	break;
+    }
+    }
+
+
+    if (!map())
+    exit(1);
+
+    if (!setup_system_bios())
+    exit(1);
+
+    iopl(3);
+
+    scan_pci();
+
+    save_msr = inb(0x3CC);
+    save_vse = inb(0x3C3);
+    save_46e8 = inb(0x46e8);
+    save_pos102 = inb(0x102);
+
+    if (Config.BootOnly) {
+
+    if (!CurrentPci && !Config.ConfigActiveDevice
+	&& !Config.ConfigActiveOnly) {
+	iopl(0);
+	unmap();
+	exit (1);
+    }
+    call_boot(NULL);
+    } else {
+    using_history();
+    yyparse();
+    }
+
+    unmap();
+
+    pciVideoRestore();
+
+    outb(0x102, save_pos102);
+    outb(0x46e8, save_46e8);
+    outb(0x3C3, save_vse);
+    outb(0x3C2, save_msr);
+
+    iopl(0);
+
+    close_console(Console);
+
+    exit(0);
+}
+
+
+void
+call_boot(struct device *dev)
+{
+    int Active_is_Pci = 0;
+    CARD32 vbios_base;
+
+    CurrentPci = PciList;
+    Console = open_console();
+
+    set_ioperm();
+
+
+    signal(2,sig_handler);
+    signal(11,sig_handler);
+
+    /* disable primary card */
+    pciVideoRestore(); /* reset PCI state to see primary card */
+    outb(0x3C2,~(CARD8)0x03 & save_msr);
+    outb(0x3C3,~(CARD8)0x01 & save_vse);
+    outb(0x46e8, ~(CARD8)0x08 & save_46e8);
+    outb(0x102, ~(CARD8)0x01 & save_pos102);
+
+    pciVideoDisable();
+
+    while (CurrentPci) {
+    CARD16 ax;
+
+    if (CurrentPci->active) {
+	Active_is_Pci = 1;
+	if (!Config.ConfigActiveDevice && !dev) {
+	CurrentPci = CurrentPci->next;
+	continue;
+	}
+    } else if (Config.ConfigActiveOnly && !dev) {
+	CurrentPci = CurrentPci->next;
+	continue;
+    }
+    if (dev && ((dev->type != PCI)
+	    || (dev->type == PCI
+	    && (dev->loc.pci.dev != CurrentPci->dev
+		|| dev->loc.pci.bus != CurrentPci->bus
+		|| dev->loc.pci.func != CurrentPci->func)))) {
+	CurrentPci = CurrentPci->next;
+	continue;
+    }
+
+    EnableCurrent();
+
+    if (CurrentPci->active) {
+	outb(0x102, save_pos102);
+	outb(0x46e8, save_46e8);
+	outb(0x3C3, save_vse);
+	outb(0x3C2, save_msr);
+    }
+
+    /* clear interrupt vectors */
+#ifdef __ia32__
+    vbios_base = CurrentPci->active ? setup_primary_int_vect()
+	: setup_int_vect();
+#else
+    vbios_base = setup_int_vect();
+#endif
+    ax = ((CARD16)(CurrentPci->bus) << 8)
+	| (CurrentPci->dev << 3) | (CurrentPci->func & 0x7);
+    if (Config.Verbose > 1) P_printf("ax: 0x%x\n",ax);
+
+    BootBios = findPciByIDs(CurrentPci->bus,CurrentPci->dev,
+		   CurrentPci->func);
+    if (!((mapPciRom(BootBios) && chksum((CARD8*)V_BIOS))
+	  || (CurrentPci->active && copy_vbios(vbios_base)))) {
+	CurrentPci = CurrentPci->next;
+	continue;
+    }
+    if (!map_vram()) {
+	CurrentPci = CurrentPci->next;
+	continue;
+    }
+    if (Config.SaveBios) save_bios_to_file();
+    printf("initializing PCI bus: %i dev: %i func: %i\n",CurrentPci->bus,
+	   CurrentPci->dev,CurrentPci->func);
+    bootBIOS(ax);
+    unmap_vram();
+
+    if (CurrentPci->active)
+	close_console(Console);
+
+    if (dev) return;
+
+    CurrentPci = CurrentPci->next;
+    }
+
+    /* We have an ISA device - configure if requested */
+    if (!Active_is_Pci /* no isa card in system! */
+    && ((!dev && (Config.ConfigActiveDevice || Config.ConfigActiveOnly))
+	|| (dev && dev->type == ISA))) {
+
+    pciVideoDisable();
+
+    if (!dev || dev->type == ISA) {
+	outb(0x102, save_pos102);
+	outb(0x46e8, save_46e8);
+	outb(0x3C3, save_vse);
+	outb(0x3C2, save_msr);
+
+#ifdef __ia32__
+	vbios_base = setup_primary_int_vect();
+#else
+	vbios_base = setup_int_vect();
+#endif
+	if (copy_vbios(vbios_base)) {
+
+	if (Config.SaveBios) save_bios_to_file();
+	if  (map_vram()) {
+	    printf("initializing ISA bus\n");
+	    bootBIOS(0);
+	}
+	}
+
+	unmap_vram();
+	sleep(1);
+	close_console(Console);
+    }
+    }
+
+
+}
+
+int
+map(void)
+{
+    void* mem;
+    mem = mmap(0, (size_t)SIZE,
+	       PROT_EXEC | PROT_READ | PROT_WRITE,
+	       MAP_FIXED | MAP_PRIVATE | MAP_ANON,
+	       -1, 0 );
+    if (mem != 0) {
+	perror("anonymous map");
+	return (0);
+    }
+    memset(mem,0,SIZE);
+
+    return (1);
+}
+
+static void
+unmap(void)
+{
+    munmap(0,SIZE);
+}
+
+static void
+bootBIOS(CARD16 ax)
+{
+    i86biosRegs bRegs;
+#ifdef V86BIOS_DEBUG
+    printf("starting BIOS\n");
+#endif
+    setup_io();
+    setup_bios_regs(&bRegs, ax);
+    loadCodeToMem((unsigned char *) BIOS_START, code);
+    do_x86(BIOS_START,&bRegs);
+#ifdef V86BIOS_DEBUG
+    printf("done\n");
+#endif
+}
+
+static int
+map_vram(void)
+{
+    int mem_fd;
+
+#ifdef __ia64__
+    if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0)
+#else
+    if ((mem_fd = open(MEM_FILE,O_RDWR))<0)
+#endif
+	{
+	perror("opening memory");
+	return 0;
+    }
+
+#ifdef __alpha__
+       if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */
+	 if (!_bus_base_sparse()) sparse_shift = 0;
+	 if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift),
+						 PROT_READ | PROT_WRITE,
+						 MAP_SHARED,
+						 mem_fd, (VRAM_START << sparse_shift)
+						 | _bus_base_sparse())) == (void *) -1)
+#else
+      if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE,
+			 PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED,
+			 mem_fd, VRAM_START) == (void *) -1)
+#endif
+      {
+	perror("mmap error in map_hardware_ram (1)");
+	    close(mem_fd);
+	    return (0);
+	}
+    vram_mapped = 1;
+    close(mem_fd);
+    return (1);
+}
+
+static void
+unmap_vram(void)
+{
+    if (!vram_mapped) return;
+
+    munmap((void*)VRAM_START,VRAM_SIZE);
+    vram_mapped = 0;
+}
+
+static int
+copy_vbios(memType v_base)
+{
+    int mem_fd;
+    unsigned char *tmp;
+    int size;
+
+    if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) {
+	perror("opening memory");
+	return (0);
+    }
+
+    if (lseek(mem_fd,(off_t) v_base, SEEK_SET) != (off_t) v_base) {
+	  fprintf(stderr,"Cannot lseek\n");
+	  goto Error;
+      }
+    tmp = (unsigned char *)malloc(3);
+    if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) {
+	    fprintf(stderr,"Cannot read\n");
+	goto Error;
+    }
+    if (lseek(mem_fd,(off_t) v_base,SEEK_SET) != (off_t) v_base)
+	goto Error;
+
+    if (*tmp != 0x55 || *(tmp+1) != 0xAA ) {
+	fprintf(stderr,"No bios found at: 0x%lx\n",v_base);
+	goto Error;
+    }
+#ifdef DEBUG
+	dprint((unsigned long)tmp,0x100);
+#endif
+    size = *(tmp+2) * 512;
+
+    if (read(mem_fd, (char *)v_base, (size_t) size) != (size_t) size) {
+	    fprintf(stderr,"Cannot read\n");
+	goto Error;
+    }
+    free(tmp);
+    close(mem_fd);
+    if (!chksum((CARD8*)v_base))
+	return (0);
+
+    return (1);
+
+Error:
+    perror("v_bios");
+    close(mem_fd);
+    return (0);
+}
+
+static int
+copy_sys_bios(void)
+{
+#define SYS_BIOS 0xF0000
+    int mem_fd;
+
+    if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) {
+	perror("opening memory");
+	return (0);
+    }
+
+    if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS)
+	goto Error;
+    if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF)
+	goto Error;
+
+    close(mem_fd);
+    return (1);
+
+Error:
+    perror("sys_bios");
+    close(mem_fd);
+    return (0);
+}
+
+void
+loadCodeToMem(unsigned char *ptr, CARD8 code[])
+{
+    int i;
+    CARD8 val;
+    int size = code[0];
+
+    for ( i=1;i<=size;i++) {
+	val = code[i];
+	*ptr++ = val;
+    }
+    return;
+}
+
+void
+dprint(unsigned long start, unsigned long size)
+{
+    int i,j;
+    char *c = (char *)start;
+
+    for (j = 0; j < (size >> 4); j++) {
+    char *d = c;
+    printf("\n0x%lx:  ",(unsigned long)c);
+    for (i = 0; i<16; i++)
+	printf("%2.2x ",(unsigned char) (*(c++)));
+    c = d;
+    for (i = 0; i<16; i++) {
+	printf("%c",((((CARD8)(*c)) > 32) && (((CARD8)(*c)) < 128)) ?
+	   (unsigned char) (*(c)): '.');
+	c++;
+    }
+    }
+    printf("\n");
+}
+
+static void
+save_bios_to_file(void)
+{
+    static int num = 0;
+    int size, count;
+    char file_name[256];
+    int fd;
+
+    sprintf(file_name,"bios_%i.fil",num);
+    if ((fd =  open(file_name,O_WRONLY | O_CREAT | O_TRUNC,00644)) == -1)
+	return;
+    size = (*(unsigned char*)(V_BIOS + 2)) * 512;
+#ifdef V86BIOS_DEBUG
+    dprint(V_BIOS,20);
+#endif
+    if ((count = write(fd,(void *)(V_BIOS),size)) != size)
+	fprintf(stderr,"only saved %i of %i bytes\n",size,count);
+    num++;
+}
+
+static void
+sig_handler(int unused)
+{
+    fflush(stdout);
+    fflush(stderr);
+
+    /* put system back in a save state */
+    unmap_vram();
+    pciVideoRestore();
+    outb(0x102, save_pos102);
+    outb(0x46e8, save_46e8);
+    outb(0x3C3, save_vse);
+    outb(0x3C2, save_msr);
+
+    close_console(Console);
+    iopl(0);
+    unmap();
+
+    exit(1);
+}
+
+/*
+ * For initialization we just pass ax to the BIOS.
+ * PCI BIOSes need this. All other register are set 0.
+ */
+static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax)
+{
+    regs->ax = ax;
+    regs->bx = 0;
+    regs->cx = 0;
+    regs->dx = 0;
+    regs->es = 0;
+    regs->ds = 0x40;               /* standard pc ds */
+    regs->si = 0;
+    regs->di = 0;
+}
+
+/*
+ * here we are really paranoid about faking a "real"
+ * BIOS. Most of this information was pulled from
+ * dosem.
+ */
+
+#ifdef __ia32__
+static CARD32
+setup_primary_int_vect(void)
+{
+    int mem_fd;
+    CARD32 vbase;
+    void *map;
+
+    if ((mem_fd = open(MEM_FILE,O_RDWR))<0)
+	    {
+    perror("opening memory");
+    return (0);
+    }
+
+    if ((map = mmap((void *) 0, (size_t) 0x2000,
+	 PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED,
+	 mem_fd, 0)) == (void *)-1)   {
+    perror("mmap error in map_hardware_ram (2)");
+    close(mem_fd);
+    return (0);
+    }
+
+    close(mem_fd);
+    memcpy(0,map,BIOS_MEM);
+    munmap(map,0x2000);
+    /*
+     * create a backup copy of the bios variables to write back the
+     * modified values
+     */
+    if (!bios_var)
+    bios_var = (char *)malloc(BIOS_MEM);
+    memcpy(bios_var,0,BIOS_MEM);
+
+    vbase = (*((CARD16*)(0x10 << 2) + 1)) << 4;
+    if (Config.Verbose > 0) printf("vbase: 0x%x\n",vbase);
+    return vbase;
+}
+#endif
+
+static CARD32
+setup_int_vect(void)
+{
+    const CARD16 cs = 0x0;
+    const CARD16 ip = 0x0;
+    int i;
+
+    /* let the int vects point to the SYS_BIOS seg */
+    for (i=0; i<0x80; i++) {
+	((CARD16*)0)[i<<1] = ip;
+	((CARD16*)0)[(i<<1)+1] = cs;
+    }
+    /* video interrupts default location */
+    ((CARD16*)0)[(0x42<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x42<<1] = 0xf065;
+    ((CARD16*)0)[(0x10<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x10<<1] = 0xf065;
+    /* video param table default location (int 1d) */
+    ((CARD16*)0)[(0x1d<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x1d<<1] = 0xf0A4;
+    /* font tables default location (int 1F) */
+    ((CARD16*)0)[(0x1f<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x1f<<1] = 0xfa6e;
+
+    /* int 11 default location */
+    ((CARD16*)0)[(0x11<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x11<<1] = 0xf84d;
+    /* int 12 default location */
+    ((CARD16*)0)[(0x12<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x12<<1] = 0xf841;
+    /* int 15 default location */
+    ((CARD16*)0)[(0x15<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x15<<1] = 0xf859;
+    /* int 1A default location */
+    ((CARD16*)0)[(0x1a<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x1a<<1] = 0xff6e;
+    /* int 05 default location */
+    ((CARD16*)0)[(0x05<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x05<<1] = 0xff54;
+    /* int 08 default location */
+    ((CARD16*)0)[(0x8<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x8<<1] = 0xfea5;
+    /* int 13 default location (fdd) */
+    ((CARD16*)0)[(0x13<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x13<<1] = 0xec59;
+    /* int 0E default location */
+    ((CARD16*)0)[(0xe<<1)+1] = 0xf000;
+    ((CARD16*)0)[0xe<<1] = 0xef57;
+    /* int 17 default location */
+    ((CARD16*)0)[(0x17<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x17<<1] = 0xefd2;
+    /* fdd table default location (int 1e) */
+    ((CARD16*)0)[(0x1e<<1)+1] = 0xf000;
+    ((CARD16*)0)[0x1e<<1] = 0xefc7;
+    return V_BIOS;
+}
+
+static int
+setup_system_bios(void)
+{
+    char *date = "06/01/99";
+    char *eisa_ident = "PCI/ISA";
+
+    if (Config.MapSysBios) {
+
+	if (!copy_sys_bios()) return 0;
+	return 1;
+
+    } else {
+
+/*    memset((void *)0xF0000,0xf4,0xfff7); */
+
+	/*
+	 * we trap the "industry standard entry points" to the BIOS
+	 * and all other locations by filling them with "hlt"
+	 * TODO: implement hlt-handler for these
+	 */
+	memset((void *)0xF0000,0xf4,0x10000);
+
+	/*
+	 * TODO: we should copy the fdd table (0xfec59-0xfec5b)
+	 * the video parameter table (0xf0ac-0xf0fb)
+	 * and the font tables (0xfa6e-0xfe6d)
+	 * from the original bios here
+	 */
+
+	/* set bios date */
+	strcpy((char *)0xFFFF5,date);
+	/* set up eisa ident string */
+	strcpy((char *)0xFFFD9,eisa_ident);
+	/* write system model id for IBM-AT */
+	((char *)0)[0xFFFFE] = 0xfc;
+
+	return 1;
+    }
+
+}
+
+static void
+update_bios_vars(void)
+{
+    int mem_fd;
+    void *map;
+    memType i;
+
+#ifdef __ia64__
+    if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0)
+#else
+    if ((mem_fd = open(MEM_FILE,O_RDWR))<0)
+#endif
+	    {
+    perror("opening memory");
+    return;
+    }
+
+    if ((map = mmap((void *) 0, (size_t) 0x2000,
+	 PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED,
+	 mem_fd, 0)) == (void *)-1)   {
+    perror("mmap error in map_hardware_ram (3)");
+    close(mem_fd);
+    return;
+    }
+
+    for (i = 0; i < BIOS_MEM; i++) {
+    if (bios_var[i] != *(CARD8*)i)
+	*((CARD8*)map + i) = *(CARD8*)i;
+    }
+
+    munmap(map,0x2000);
+    close(mem_fd);
+}
+
+static int
+chksum(CARD8 *start)
+{
+  CARD16 size;
+  CARD8 val = 0;
+  int i;
+
+  size = *(start+2) * 512;
+  for (i = 0; i<size; i++)
+    val += *(start + i);
+
+  if (!val)
+    return 1;
+
+    fprintf(stderr,"BIOS cksum wrong!\n");
+  return 0;
+}
+
+void
+runINT(int num, i86biosRegsPtr Regs)
+{
+    Bool isVideo = FALSE;
+    CARD8 code_int[] = { 3, 0xcd, 0x00, 0xf4 };
+
+    code_int[2] = (CARD8) num;
+
+    if (num == 0x10)
+    isVideo = TRUE;
+
+    if (!setup_system_bios())
+    return;
+
+    if ((isVideo && (!CurrentPci || CurrentPci->active)) || !isVideo) {
+    CARD32 vbios_base;
+
+#ifdef __ia32__
+    if (!(vbios_base = setup_primary_int_vect()))
+#else
+    if (!(vbios_base = setup_int_vect()))
+#endif
+	return;
+    if (!copy_vbios(vbios_base))
+	return;
+    }
+
+    if (!map_vram())
+    return;
+
+#ifdef V86BIOS_DEBUG
+	printf("starting BIOS\n");
+#endif
+    loadCodeToMem((unsigned char *) BIOS_START, code_int);
+    setup_io();
+    print_regs(Regs);
+    set_ioperm();
+    set_hlt(TRUE);
+    do_x86(BIOS_START,Regs);
+    set_hlt(FALSE);
+    print_regs(Regs);
+
+#ifdef V86BIOS_DEBUG
+    printf("done\n");
+#endif
+
+    if ((isVideo && (!CurrentPci || CurrentPci->active)) || !isVideo)
+    update_bios_vars();
+}
+
+static void
+print_regs(i86biosRegsPtr regs)
+{
+    printf("ax=%x bx=%x cx=%x dx=%x ds=%x es=%x di=%x si=%x\n",
+       (CARD16)regs->ax,(CARD16)regs->bx,(CARD16)regs->cx,(CARD16)regs->dx,
+       (CARD16)regs->ds,(CARD16)regs->es,(CARD16)regs->di,
+       (CARD16)regs->si);
+}
+
+static void
+print_usage(void)
+{
+}
+
+void
+add_hlt(unsigned long val)
+{
+    int i;
+
+    if (val < BIOS_MEM || (val > VRAM_START && val < (VRAM_START + VRAM_SIZE))
+    || val >= SIZE) {
+    printf("address out of range\n");
+    return;
+    }
+
+    for (i=0; i<20; i++) {
+    if (hltp[i].address == 0) {
+	hltp[i].address = (void*)val;
+	break;
+    }
+    }
+    if (i == 20) printf("no more hltpoints available\n");
+}
+
+void
+del_hlt(int val)
+{
+    if (val == 21) { /* delete all */
+    int i;
+    printf("clearing all hltpoints\n");
+    for (i=0; i <20; i++)
+	hltp[i].address = NULL;
+    } else if (val >= 0 &&  val <20)
+    hltp[val].address = NULL;
+    else printf("hltpoint %i out of range: valid range 0-19\n",val);
+}
+
+void
+list_hlt()
+{
+    int i;
+    for (i=0; i<20; i++)
+    if (hltp[i].address)
+	printf("hltpoint[%i]: 0x%lx\n",i,(unsigned long)hltp[i].address);
+}
+
+static void
+set_hlt(Bool set)
+{
+    int i;
+    for (i=0; i<20; i++)
+    if (hltp[i].address) {
+	if (set) {
+	hltp[i].orgval = *(CARD8*)hltp[i].address;
+	*(CARD8*)hltp[i].address = 0xf4;
+	} else
+	*(CARD8*)hltp[i].address = hltp[i].orgval;
+    }
+}
+
+static void
+set_ioperm(void)
+{
+    int i, start;
+
+    ioperm(0,IOPERM_BITS,0);
+
+    for (i = 0; i < IOPERM_BITS;i++)
+    if (ioperm_list[i]) {
+	start = i;
+	for (;i < IOPERM_BITS; i++) {
+	if (!ioperm_list[i]) {
+	    ioperm(start,i - start, 1);
+	    break;
+	}
+	}
+    }
+}
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h
new file mode 100755
index 0000000..a8f3f8e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef V86_BIOS_H
+#define V86_BIOS_H
+
+#if defined (__i386__) || defined (__i486__) || defined (__i586__) || defined (__i686__) || defined (__k6__)
+# ifndef __ia32__
+#  define __ia32__
+# endif
+#endif
+
+#include <stdio.h>
+
+#define p_printf(f,a...) do {if (Config.PrintPort) lprintf(f,##a);} \
+			 while(0)
+#define i_printf(f,a...) do  {if (Config.PrintIrq) lprintf(f,##a);} \
+			  while(0)
+#define P_printf(f,a...) do {if (Config.PrintPci) lprintf(f,##a);} \
+			  while(0)
+
+typedef unsigned char CARD8;
+typedef unsigned short CARD16;
+typedef unsigned int CARD32;
+#if defined (__alpha__) || defined (__ia64__)
+typedef unsigned long memType;
+#else
+typedef unsigned int memType;
+#endif
+
+typedef int Bool;
+
+#define FALSE 0
+#define TRUE 1
+
+struct config {
+    Bool PrintPort;
+    Bool IoStatistics;
+    Bool PrintIrq;
+    Bool PrintPci;
+    Bool ShowAllDev;
+    Bool PrintIp;
+    Bool SaveBios;
+    Bool Trace;
+    Bool ConfigActiveOnly;
+    Bool ConfigActiveDevice;
+    Bool MapSysBios;
+    Bool Resort;
+    Bool FixRom;
+    Bool NoConsole;
+    Bool BootOnly;
+    int  Verbose;
+};
+
+struct pio {
+    CARD8 (*inb)(CARD16);
+    CARD16 (*inw)(CARD16);
+    CARD32 (*inl)(CARD16);
+    void (*outb)(CARD16,CARD8);
+    void (*outw)(CARD16,CARD16);
+    void (*outl)(CARD16,CARD32);
+};
+
+struct regs86 {
+	long ebx;
+	long ecx;
+	long edx;
+	long esi;
+	long edi;
+	long ebp;
+	long eax;
+	long eip;
+	long esp;
+	unsigned short cs;
+	unsigned short ss;
+	unsigned short es;
+	unsigned short ds;
+	unsigned short fs;
+	unsigned short gs;
+    long eflags;
+};
+
+typedef struct {
+    CARD32 ax;
+    CARD32 bx;
+    CARD32 cx;
+    CARD32 dx;
+    CARD32 cs;
+    CARD32 es;
+    CARD32 ds;
+    CARD32 si;
+    CARD32 di;
+} i86biosRegs, *i86biosRegsPtr;
+
+typedef struct {
+    int fd;
+    int vt;
+} console;
+
+typedef struct {
+    void* address;
+    CARD8 orgval;
+} haltpoints;
+
+enum dev_type {  NONE, ISA, PCI };
+struct device {
+    Bool booted;
+    enum dev_type type;
+    union {
+      int none;
+      struct pci {
+	int bus;
+	int dev;
+	int func;
+      } pci;
+    } loc;
+};
+
+extern struct device Device;
+
+#ifdef __alpha__
+unsigned long _bus_base(void);
+extern void* vram_map;
+extern int sparse_shift;
+#endif
+
+extern struct pio P;
+extern struct config Config;
+#define IOPERM_BITS 1024
+extern int ioperm_list[IOPERM_BITS];
+
+extern void setup_io(void);
+extern void do_x86(unsigned long bios_start,i86biosRegsPtr regs);
+extern int run_bios_int(int num, struct regs86 *regs);
+extern CARD32 getIntVect(int num);
+CARD32 getIP(void);
+
+extern void call_boot(struct device *dev);
+extern void runINT(int num,i86biosRegsPtr Regs);
+extern void add_hlt(unsigned long addr);
+extern void del_hlt(int addr);
+extern void list_hlt();
+
+extern int port_rep_inb(CARD16 port, CARD8 *base, int d_f, CARD32 count);
+extern int port_rep_inw(CARD16 port, CARD16 *base, int d_f, CARD32 count);
+extern int port_rep_inl(CARD16 port, CARD32 *base, int d_f, CARD32 count);
+extern int port_rep_outb(CARD16 port, CARD8 *base, int d_f, CARD32 count);
+extern int port_rep_outw(CARD16 port, CARD16 *base, int d_f, CARD32 count);
+extern int port_rep_outl(CARD16 port, CARD32 *base, int d_f, CARD32 count);
+extern CARD8 p_inb(CARD16 port);
+extern CARD16 p_inw(CARD16 port);
+extern CARD32 p_inl(CARD16 port);
+extern void p_outb(CARD16 port, CARD8 val);
+extern void p_outw(CARD16 port, CARD16 val);
+extern void p_outl(CARD16 port, CARD32 val);
+#ifdef __alpha__
+extern CARD8 a_inb(CARD16 port);
+extern CARD16 a_inw(CARD16 port);
+extern void a_outb(CARD16 port, CARD8 val);
+extern void a_outw(CARD16 port, CARD16 val);
+#endif
+#ifdef __alpha__
+CARD8 mem_rb(CARD32 addr);
+CARD16 mem_rw(CARD32 addr);
+CARD32 mem_rl(CARD32 addr);
+void mem_wb(CARD32 addr, CARD8 val);
+void mem_ww(CARD32 addr, CARD16 val);
+void mem_wl(CARD32 addr, CARD32 val);
+#endif
+extern void io_statistics(void);
+extern void clear_stat(void);
+extern int int_handler(int num, struct regs86 *regs);
+
+extern console open_console(void);
+extern void close_console(console);
+
+extern void dprint(unsigned long start, unsigned long size);
+
+extern Bool logging;
+extern Bool nostdout;
+extern char* logfile;
+extern void logon(void* ptr);
+extern void logoff();
+extern void lprintf(const char *f, ...);
+
+#define MEM_FILE "/dev/mem"
+#define DEFAULT_V_BIOS 0xc0000
+#ifndef V_BIOS
+#define V_BIOS DEFAULT_V_BIOS
+#endif
+
+#ifdef __alpha__
+#define NEED_PCI_IO
+#endif
+
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/working_cards b/board/MAI/bios_emulator/scitech/src/v86bios/working_cards
new file mode 100755
index 0000000..7753f24
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/working_cards
@@ -0,0 +1,7 @@
+David Monro:                    Trident TGUI 9440
+                                Virge/VX (Diamond Stealth 3D 3400)   
+                                Riva TNT (Diamond Viper V550)   no vbios?
+Jarno Paananen <jpaana@s2.org>: Guillemot Maxigamer Xentor 32 
+                                (NVIDIA TNT2 Ultra)
+                                Creative Graphics Blaster Exxtreme 
+                                (Permedia 2) 
diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c b/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c
new file mode 100755
index 0000000..b5c99d7
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright 1999 Egbert Eich
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of the authors not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission.  The authors makes no representations
+ * about the suitability of this software for any purpose.  It is provided
+ * "as is" without express or implied warranty.
+ *
+ * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "debug.h"
+
+#define IF_MASK     0x00000200
+#define VIF_MASK    0x00080000  /* virtual interrupt flag */
+#define VIP_MASK    0x00100000  /* virtual interrupt pending */
+
+#include </usr/include/unistd.h>
+#include <errno.h>
+#include <asm/unistd.h>
+/*#include <syscall-list.h> */
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+#ifdef __alpha__
+#include <sys/io.h>
+#endif
+#include <signal.h>
+#include <setjmp.h>
+#include "AsmMacros.h"
+#include "v86bios.h"
+# define DEBUG
+#include "x86emu.h"
+#undef DEBUG
+
+#define M            _X86EMU_env
+#define CPU_REG(reg) M.x86.R_##reg
+
+struct pio P;
+
+void
+setup_io(void)
+{
+    if (!Config.PrintPort && !Config.IoStatistics) {
+
+#if defined (__i386__)
+    P.inb = (u8(*)(u16))inb;
+    P.inw = (u16(*)(u16))inw;
+    P.outb = (void(*)(u16,u8))outb;
+    P.outw = (void(*)(u16,u16))outw;
+#else
+    P.inb = p_inb;
+    P.inw = p_inw;
+    P.outb = p_outb;
+    P.outw = p_outw;
+#endif
+#if defined (__i386__) && ! defined(NEED_PCI_IO)
+    P.inl = (u32(*)(u16))inl;
+    P.outl = (void(*)(u16,u32))outl;
+#else
+    P.inl = p_inl;
+    P.outl = p_outl;
+#endif
+    } else {
+    P.inb = p_inb;
+    P.inw = p_inw;
+    P.inl = p_inl;
+    P.outb = p_outb;
+    P.outw = p_outw;
+    P.outl = p_outl;
+    }
+}
+
+void
+x86emu_do_int(int num)
+{
+    struct regs86 regs;
+
+    i_printf("int 0x%x received: ax:0x%x",num,CPU_REG(AX));
+    if (Config.PrintIp)
+	i_printf(" at: 0x%x\n",getIP());
+    else
+	i_printf("\n");
+
+    /* try to run bios interrupt */
+
+    /* if not installed fall back */
+#define COPY(x,y) regs.y = M.x86.x
+#define COPY_R(x,y) M.x86.x = regs.y
+
+    COPY(R_EAX,eax);
+    COPY(R_EBX,ebx);
+    COPY(R_ECX,ecx);
+    COPY(R_EDX,edx);
+    COPY(R_ESI,esi);
+    COPY(R_EDI,edi);
+    COPY(R_EBP,ebp);
+    COPY(R_EIP,eip);
+    COPY(R_ESP,esp);
+    COPY(R_CS,cs);
+    COPY(R_SS,ss);
+    COPY(R_DS,ds);
+    COPY(R_ES,es);
+    COPY(R_FS,fs);
+    COPY(R_GS,gs);
+    COPY(R_EFLG,eflags);
+
+    if (!(int_handler(num,&regs))) {
+	if (!run_bios_int(num,&regs))
+	    goto unknown_int;
+	else
+	    return;
+    }
+
+    COPY_R(R_EAX,eax);
+    COPY_R(R_EBX,ebx);
+    COPY_R(R_ECX,ecx);
+    COPY_R(R_EDX,edx);
+    COPY_R(R_ESI,esi);
+    COPY_R(R_EDI,edi);
+    COPY_R(R_EBP,ebp);
+    COPY_R(R_EIP,eip);
+    COPY_R(R_ESP,esp);
+    COPY_R(R_CS,cs);
+    COPY_R(R_SS,ss);
+    COPY_R(R_DS,ds);
+    COPY_R(R_ES,es);
+    COPY_R(R_FS,fs);
+    COPY_R(R_GS,gs);
+    COPY_R(R_EFLG,eflags);
+    return;
+
+ unknown_int:
+    fprintf(stderr,"\nUnknown vm86_int: %X\n\n",num);
+    X86EMU_halt_sys();
+    return;
+
+#undef COPY
+#undef COPY_R
+}
+
+void
+setup_x86emu(unsigned long bios_start, i86biosRegsPtr regs)
+{
+    int i;
+    CARD32 eip;
+    CARD16 cs;
+    X86EMU_intrFuncs intFuncs[256];
+
+    X86EMU_pioFuncs pioFuncs = {
+	(u8(*)(u16))P.inb,
+	(u16(*)(u16))P.inw,
+	(u32(*)(u16))P.inl,
+	(void(*)(u16,u8))P.outb,
+	(void(*)(u16,u16))P.outw,
+	(void(*)(u16,u32))P.outl
+    };
+#ifdef __alpha__
+    X86EMU_memFuncs memFuncs = {
+      (u8(*)(u32))mem_rb,
+      (u16(*)(u32))mem_rw,
+      (u32(*)(u32))mem_rl,
+      (void(*)(u32,u8))mem_wb,
+      (void(*)(u32,u16))mem_ww,
+      (void(*)(u32,u32))mem_wl
+    };
+#endif
+    M.mem_base = 0;
+    M.mem_size = 1024*1024 + 1024;
+    /*  M.x86.debug = DEBUG_DISASSEMBLE_F | DEBUG_TRACE_F | DEBUG_DECODE_F; */
+    /*  M.x86.debug |= DEBUG_DECODE_F |  DEBUG_TRACE_F; */
+/*
+ * For single step tracing compile x86emu with option -DDEBUG
+ */
+    M.x86.debug = 0;
+    if (Config.PrintIp)
+	M.x86.debug = DEBUG_SAVE_CS_IP;
+
+    if (Config.Trace)
+	X86EMU_trace_on();
+
+    X86EMU_setupPioFuncs(&pioFuncs);
+#ifdef __alpha__
+    X86EMU_setupMemFuncs(&memFuncs);
+#endif
+    for (i=0;i<256;i++)
+	intFuncs[i] = x86emu_do_int;
+    X86EMU_setupIntrFuncs(intFuncs);
+
+    eip = bios_start & 0xFFFF;
+    cs = (bios_start & 0xFF0000) >> 4;
+
+    CPU_REG(EAX) = regs->ax;
+    CPU_REG(EBX) = regs->bx;
+    CPU_REG(ECX) = regs->cx;
+    CPU_REG(EDX) = regs->dx;
+    CPU_REG(ESI) = regs->si;
+    CPU_REG(EDI) = regs->di;
+    CPU_REG(EBP) = 0;
+    CPU_REG(EIP) = eip;
+    CPU_REG(CS) = cs;
+    CPU_REG(SP) = 0x100;
+    CPU_REG(SS) = 0x30;               /* This is the standard pc bios stack */
+    CPU_REG(ES) = regs->es;
+    CPU_REG(DS) = regs->ds;
+    CPU_REG(FS) = 0;
+    CPU_REG(GS) = 0;
+    CPU_REG(EFLG) |= (VIF_MASK | VIP_MASK | IF_MASK | 0x2);
+}
+
+void
+collect_bios_regs(i86biosRegsPtr regs)
+{
+    regs->ax = CPU_REG(EAX);
+    regs->bx = CPU_REG(EBX);
+    regs->cx = CPU_REG(ECX);
+    regs->dx = CPU_REG(EDX);
+    regs->es = CPU_REG(ES);
+    regs->ds = CPU_REG(DS);
+    regs->di = CPU_REG(EDI);
+    regs->si = CPU_REG(ESI);
+}
+
+static void
+do_x86emu(void)
+{
+    X86EMU_exec();
+}
+
+static jmp_buf x86_esc;
+static void
+vmexit(int unused)
+{
+    longjmp(x86_esc,1);
+}
+
+void
+do_x86(unsigned long bios_start, i86biosRegsPtr regs)
+{
+    static void (*org_handler)(int);
+
+    setup_x86emu(bios_start,regs);
+    if (setjmp(x86_esc) == 0) {
+	org_handler = signal(2,vmexit);
+	do_x86emu();
+	signal(2,org_handler);
+	collect_bios_regs(regs);
+    } else {
+	signal(2,org_handler);
+	printf("interrupted at 0x%x\n",((CARD16)CPU_REG(CS)) << 4
+	       | (CARD16)CPU_REG(EIP));
+    }
+}
+
+int
+run_bios_int(int num, struct regs86 *regs)
+{
+#ifdef V86BIOS_DEBUG
+    static int firsttime = 1;
+#endif
+    /* check if bios vector is initialized */
+    if (((CARD16*)0)[(num<<1)+1] == 0x0000) { /* SYS_BIOS_SEG ?*/
+#ifdef V86BIOS_DEBUG
+	i_printf("card BIOS not loaded\n");
+#endif
+	return 0;
+    }
+
+#ifdef V86BIOS_DEBUG
+    if (firsttime) {
+	dprint(0,0x3D0);
+	firsttime = 0;
+    }
+#endif
+
+    i_printf("calling card BIOS at: ");
+    i_printf("0x%x:%x\n",((CARD16 *) 0)[(num << 1) + 1],
+	     (CARD32)((CARD16 *) 0)[num << 1]);
+    X86EMU_prepareForInt(num);
+
+    return 1;
+}
+
+CARD32
+getIntVect(int num)
+{
+  return ((CARD32*)0)[num];
+}
+#if 0
+void
+printk(const char *fmt, ...)
+{
+    va_list argptr;
+    va_start(argptr, fmt);
+    vfprintf(stdout, fmt, argptr);
+    fflush(stdout);
+    va_end(argptr);
+}
+#endif
+
+CARD32
+getIP(void)
+{
+    return (M.x86.saved_cs << 4) + M.x86.saved_ip;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE b/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE
new file mode 100755
index 0000000..a3ede4a
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE
@@ -0,0 +1,17 @@
+                         License information
+                         -------------------
+
+The x86emu library is under a BSD style license, comaptible
+with the XFree86 and X licenses used by XFree86. The
+original x86emu libraries were under the GNU General Public
+License. Due to license incompatibilities between the GPL
+and the XFree86 license, the original authors of the code
+decided to allow a license change. If you have submitted
+code to the original x86emu project, and you don't agree
+with the license change, please contact us and let you
+know. Your code will be removed to comply with your wishes.
+
+If you have any questions about this, please send email to
+x86emu@linuxlabs.com or KendallB@scitechsoft.com for
+clarification.
+
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/debug.c b/board/MAI/bios_emulator/scitech/src/x86emu/debug.c
new file mode 100755
index 0000000..235e6ac
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/debug.c
@@ -0,0 +1,443 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  This file contains the code to handle debugging of the
+*				emulator.
+*
+****************************************************************************/
+
+#include "x86emu/x86emui.h"
+#include <stdarg.h>
+#include <stdlib.h>
+
+/*----------------------------- Implementation ----------------------------*/
+
+#ifdef DEBUG
+
+static void     print_encoded_bytes (u16 s, u16 o);
+static void     print_decoded_instruction (void);
+static int      parse_line (char *s, int *ps, int *n);
+
+/* should look something like debug's output. */
+void X86EMU_trace_regs (void)
+{
+	if (DEBUG_TRACE()) {
+		x86emu_dump_regs();
+    }
+	if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) {
+		printk("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip);
+		print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip);
+		print_decoded_instruction();
+    }
+}
+
+void X86EMU_trace_xregs (void)
+{
+	if (DEBUG_TRACE()) {
+		x86emu_dump_xregs();
+    }
+}
+
+void x86emu_just_disassemble (void)
+{
+    /*
+     * This routine called if the flag DEBUG_DISASSEMBLE is set kind
+     * of a hack!
+     */
+	printk("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip);
+	print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip);
+	print_decoded_instruction();
+}
+
+static void disassemble_forward (u16 seg, u16 off, int n)
+{
+	X86EMU_sysEnv tregs;
+	int i;
+	u8 op1;
+    /*
+     * hack, hack, hack.  What we do is use the exact machinery set up
+     * for execution, except that now there is an additional state
+     * flag associated with the "execution", and we are using a copy
+     * of the register struct.  All the major opcodes, once fully
+     * decoded, have the following two steps: TRACE_REGS(r,m);
+     * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to
+     * the preprocessor.  The TRACE_REGS macro expands to:
+     *
+     * if (debug&DEBUG_DISASSEMBLE)
+     *     {just_disassemble(); goto EndOfInstruction;}
+     *     if (debug&DEBUG_TRACE) trace_regs(r,m);
+     *
+     * ......  and at the last line of the routine.
+     *
+     * EndOfInstruction: end_instr();
+     *
+     * Up to the point where TRACE_REG is expanded, NO modifications
+     * are done to any register EXCEPT the IP register, for fetch and
+     * decoding purposes.
+     *
+     * This was done for an entirely different reason, but makes a
+     * nice way to get the system to help debug codes.
+     */
+	tregs = M;
+    tregs.x86.R_IP = off;
+    tregs.x86.R_CS = seg;
+
+    /* reset the decoding buffers */
+    tregs.x86.enc_str_pos = 0;
+    tregs.x86.enc_pos = 0;
+
+    /* turn on the "disassemble only, no execute" flag */
+    tregs.x86.debug |= DEBUG_DISASSEMBLE_F;
+
+    /* DUMP NEXT n instructions to screen in straight_line fashion */
+    /*
+     * This looks like the regular instruction fetch stream, except
+     * that when this occurs, each fetched opcode, upon seeing the
+     * DEBUG_DISASSEMBLE flag set, exits immediately after decoding
+     * the instruction.  XXX --- CHECK THAT MEM IS NOT AFFECTED!!!
+     * Note the use of a copy of the register structure...
+     */
+    for (i=0; i<n; i++) {
+		op1 = (*sys_rdb)(((u32)M.x86.R_CS<<4) + (M.x86.R_IP++));
+		(x86emu_optab[op1])(op1);
+    }
+    /* end major hack mode. */
+}
+
+void x86emu_check_ip_access (void)
+{
+    /* NULL as of now */
+}
+
+void x86emu_check_sp_access (void)
+{
+}
+
+void x86emu_check_mem_access (u32 dummy)
+{
+	/*  check bounds, etc */
+}
+
+void x86emu_check_data_access (uint dummy1, uint dummy2)
+{
+	/*  check bounds, etc */
+}
+
+void x86emu_inc_decoded_inst_len (int x)
+{
+	M.x86.enc_pos += x;
+}
+
+void x86emu_decode_printf (char *x)
+{
+	sprintf(M.x86.decoded_buf+M.x86.enc_str_pos,"%s",x);
+	M.x86.enc_str_pos += strlen(x);
+}
+
+void x86emu_decode_printf2 (char *x, int y)
+{
+	char temp[100];
+	sprintf(temp,x,y);
+	sprintf(M.x86.decoded_buf+M.x86.enc_str_pos,"%s",temp);
+	M.x86.enc_str_pos += strlen(temp);
+}
+
+void x86emu_end_instr (void)
+{
+	M.x86.enc_str_pos = 0;
+	M.x86.enc_pos = 0;
+}
+
+static void print_encoded_bytes (u16 s, u16 o)
+{
+    int i;
+    char buf1[64];
+	for (i=0; i< M.x86.enc_pos; i++) {
+		sprintf(buf1+2*i,"%02x", fetch_data_byte_abs(s,o+i));
+    }
+	printk("%-20s",buf1);
+}
+
+static void print_decoded_instruction (void)
+{
+	printk("%s", M.x86.decoded_buf);
+}
+
+void x86emu_print_int_vect (u16 iv)
+{
+	u16 seg,off;
+
+	if (iv > 256) return;
+	seg   = fetch_data_word_abs(0,iv*4);
+	off   = fetch_data_word_abs(0,iv*4+2);
+	printk("%04x:%04x ", seg, off);
+}
+
+void X86EMU_dump_memory (u16 seg, u16 off, u32 amt)
+{
+    u32 start = off & 0xfffffff0;
+    u32 end  = (off+16) & 0xfffffff0;
+    u32 i;
+    u32 current;
+
+    current = start;
+    while (end <= off + amt) {
+	printk("%04x:%04x ", seg, start);
+	for (i=start; i< off; i++)
+	    printk("   ");
+	for (       ; i< end; i++)
+	    printk("%02x ", fetch_data_byte_abs(seg,i));
+	printk("\n");
+	start = end;
+	end = start + 16;
+    }
+}
+
+void x86emu_single_step (void)
+{
+    char s[1024];
+    int ps[10];
+    int ntok;
+    int cmd;
+    int done;
+		int segment;
+    int offset;
+    static int breakpoint;
+    static int noDecode = 1;
+
+    char *p;
+
+    if (DEBUG_BREAK()) {
+	if (M.x86.saved_ip != breakpoint) {
+	    return;
+	} else {
+	    M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F;
+	    M.x86.debug |= DEBUG_TRACE_F;
+	    M.x86.debug &= ~DEBUG_BREAK_F;
+	    print_decoded_instruction ();
+	    X86EMU_trace_regs();
+	}
+    }
+
+    done=0;
+    offset = M.x86.saved_ip;
+    while (!done) {
+	printk("-");
+	/*p = fgets(s, 1023, stdin); */
+	cons_gets(s);
+	cmd = parse_line(s, ps, &ntok);
+	switch(cmd) {
+	case 'u':
+	    disassemble_forward(M.x86.saved_cs,(u16)offset,10);
+	    break;
+	case 'd':
+	    if (ntok == 2) {
+		segment = M.x86.saved_cs;
+		offset = ps[1];
+		X86EMU_dump_memory(segment,(u16)offset,16);
+		offset += 16;
+	    } else if (ntok == 3) {
+		segment = ps[1];
+		offset = ps[2];
+		X86EMU_dump_memory(segment,(u16)offset,16);
+		offset += 16;
+	    } else {
+		segment = M.x86.saved_cs;
+		X86EMU_dump_memory(segment,(u16)offset,16);
+		offset += 16;
+	    }
+	    break;
+	case 'c':
+	    M.x86.debug ^= DEBUG_TRACECALL_F;
+	    break;
+	case 's':
+	    M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F;
+	    break;
+	case 'r':
+	    X86EMU_trace_regs();
+	    break;
+	case 'x':
+	    X86EMU_trace_xregs();
+	    break;
+	case 'g':
+	    if (ntok == 2) {
+		breakpoint = ps[1];
+		printk("breakpoint set to 0x%X\n", breakpoint);
+		if (noDecode) {
+		    M.x86.debug |= DEBUG_DECODE_NOPRINT_F;
+		} else {
+		    M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F;
+		}
+		M.x86.debug &= ~DEBUG_TRACE_F;
+		M.x86.debug |= DEBUG_BREAK_F;
+		done = 1;
+	    }
+	    break;
+	case 'q':
+	    M.x86.debug |= DEBUG_EXIT;
+	    return;
+	case 'P':
+	    noDecode = (noDecode)?0:1;
+	    printk("Toggled decoding to %s\n",(noDecode)?"FALSE":"TRUE");
+	    break;
+	case 't':
+	case 0:
+	    done = 1;
+	    break;
+	}
+    }
+}
+
+int X86EMU_trace_on(void)
+{
+	return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F;
+}
+
+int X86EMU_trace_off(void)
+{
+	return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F);
+}
+
+static int parse_line (char *s, int *ps, int *n)
+{
+    int cmd;
+
+    *n = 0;
+    while(*s == ' ' || *s == '\t') s++;
+    ps[*n] = *s;
+    switch (*s) {
+      case '\n':
+	*n += 1;
+	return 0;
+      default:
+	cmd = *s;
+	*n += 1;
+    }
+
+	while (1) {
+		while (*s != ' ' && *s != '\t' && *s != '\n')  s++;
+
+		if (*s == '\n')
+			return cmd;
+
+		while(*s == ' ' || *s == '\t') s++;
+
+		ps[*n]=atoi(s);
+		/*sscanf(s,"%x",&ps[*n]); */
+		*n += 1;
+	}
+}
+
+#endif /* DEBUG */
+
+void x86emu_dump_stack(void)
+{
+    int i;
+    printk("Stack: ");
+    for (i = 0; i<16; i++)
+    {
+	u8 x = fetch_data_byte_abs(M.x86.R_SS, M.x86.R_SP + i);
+	printk("%02x ", (int)x);
+    }
+    printk("\n");
+}
+
+void x86emu_dump_regs (void)
+{
+	printk("\tAX=%04x  ", M.x86.R_AX );
+	printk("BX=%04x  ", M.x86.R_BX );
+	printk("CX=%04x  ", M.x86.R_CX );
+	printk("DX=%04x  ", M.x86.R_DX );
+	printk("SP=%04x  ", M.x86.R_SP );
+	printk("BP=%04x  ", M.x86.R_BP );
+	printk("SI=%04x  ", M.x86.R_SI );
+	printk("DI=%04x\n", M.x86.R_DI );
+	printk("\tDS=%04x  ", M.x86.R_DS );
+	printk("ES=%04x  ", M.x86.R_ES );
+	printk("SS=%04x  ", M.x86.R_SS );
+	printk("CS=%04x  ", M.x86.R_CS );
+	printk("IP=%04x   ", M.x86.R_IP );
+	if (ACCESS_FLAG(F_OF))    printk("OV ");     /* CHECKED... */
+	else                        printk("NV ");
+	if (ACCESS_FLAG(F_DF))    printk("DN ");
+	else                        printk("UP ");
+	if (ACCESS_FLAG(F_IF))    printk("EI ");
+	else                        printk("DI ");
+	if (ACCESS_FLAG(F_SF))    printk("NG ");
+	else                        printk("PL ");
+	if (ACCESS_FLAG(F_ZF))    printk("ZR ");
+	else                        printk("NZ ");
+	if (ACCESS_FLAG(F_AF))    printk("AC ");
+	else                        printk("NA ");
+	if (ACCESS_FLAG(F_PF))    printk("PE ");
+	else                        printk("PO ");
+	if (ACCESS_FLAG(F_CF))    printk("CY ");
+	else                        printk("NC ");
+	printk("\n");
+	/*x86emu_dump_stack(); */
+}
+
+void x86emu_dump_xregs (void)
+{
+	printk("\tEAX=%08x  ", M.x86.R_EAX );
+	printk("EBX=%08x  ", M.x86.R_EBX );
+	printk("ECX=%08x  ", M.x86.R_ECX );
+	printk("EDX=%08x  \n", M.x86.R_EDX );
+	printk("\tESP=%08x  ", M.x86.R_ESP );
+	printk("EBP=%08x  ", M.x86.R_EBP );
+	printk("ESI=%08x  ", M.x86.R_ESI );
+	printk("EDI=%08x\n", M.x86.R_EDI );
+	printk("\tDS=%04x  ", M.x86.R_DS );
+	printk("ES=%04x  ", M.x86.R_ES );
+	printk("SS=%04x  ", M.x86.R_SS );
+	printk("CS=%04x  ", M.x86.R_CS );
+	printk("EIP=%08x\n\t", M.x86.R_EIP );
+	if (ACCESS_FLAG(F_OF))    printk("OV ");     /* CHECKED... */
+	else                        printk("NV ");
+	if (ACCESS_FLAG(F_DF))    printk("DN ");
+	else                        printk("UP ");
+	if (ACCESS_FLAG(F_IF))    printk("EI ");
+	else                        printk("DI ");
+	if (ACCESS_FLAG(F_SF))    printk("NG ");
+	else                        printk("PL ");
+	if (ACCESS_FLAG(F_ZF))    printk("ZR ");
+	else                        printk("NZ ");
+	if (ACCESS_FLAG(F_AF))    printk("AC ");
+	else                        printk("NA ");
+	if (ACCESS_FLAG(F_PF))    printk("PE ");
+	else                        printk("PO ");
+	if (ACCESS_FLAG(F_CF))    printk("CY ");
+	else                        printk("NC ");
+	printk("\n");
+}
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/decode.c b/board/MAI/bios_emulator/scitech/src/x86emu/decode.c
new file mode 100755
index 0000000..832b1f5
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/decode.c
@@ -0,0 +1,970 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  This file includes subroutines which are related to
+*				instruction decoding and accessess of immediate data via IP.  etc.
+*
+****************************************************************************/
+
+#include "x86emu/x86emui.h"
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+REMARKS:
+Handles any pending asychronous interrupts.
+****************************************************************************/
+static void x86emu_intr_handle(void)
+{
+	u8	intno;
+
+	if (M.x86.intr & INTR_SYNCH) {
+		intno = M.x86.intno;
+		if (_X86EMU_intrTab[intno]) {
+			(*_X86EMU_intrTab[intno])(intno);
+		} else {
+			push_word((u16)M.x86.R_FLG);
+			CLEAR_FLAG(F_IF);
+			CLEAR_FLAG(F_TF);
+			push_word(M.x86.R_CS);
+			M.x86.R_CS = mem_access_word(intno * 4 + 2);
+			push_word(M.x86.R_IP);
+			M.x86.R_IP = mem_access_word(intno * 4);
+			M.x86.intr = 0;
+		}
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+intrnum - Interrupt number to raise
+
+REMARKS:
+Raise the specified interrupt to be handled before the execution of the
+next instruction.
+****************************************************************************/
+void x86emu_intr_raise(
+	u8 intrnum)
+{
+	M.x86.intno = intrnum;
+	M.x86.intr |= INTR_SYNCH;
+}
+
+/****************************************************************************
+REMARKS:
+Main execution loop for the emulator. We return from here when the system
+halts, which is normally caused by a stack fault when we return from the
+original real mode call.
+****************************************************************************/
+void X86EMU_exec(void)
+{
+    u8 op1;
+
+    M.x86.intr = 0;
+    DB(x86emu_end_instr();)
+
+    for (;;) {
+	DB(if (CHECK_IP_FETCH()) x86emu_check_ip_access();)
+	/* If debugging, save the IP and CS values. */
+	SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP);
+	INC_DECODED_INST_LEN(1);
+	if (M.x86.intr) {
+	    if (M.x86.intr & INTR_HALTED) {
+		DB(	printk("halted\n"); X86EMU_trace_regs();)
+		    return;
+	    }
+	    if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) ||
+		!ACCESS_FLAG(F_IF)) {
+		x86emu_intr_handle();
+	    }
+	}
+	op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
+	(*x86emu_optab[op1])(op1);
+	if (M.x86.debug & DEBUG_EXIT) {
+	    M.x86.debug &= ~DEBUG_EXIT;
+	    return;
+	}
+    }
+}
+
+/****************************************************************************
+REMARKS:
+Halts the system by setting the halted system flag.
+****************************************************************************/
+void X86EMU_halt_sys(void)
+{
+	M.x86.intr |= INTR_HALTED;
+}
+
+/****************************************************************************
+PARAMETERS:
+mod		- Mod value from decoded byte
+regh	- Reg h value from decoded byte
+regl	- Reg l value from decoded byte
+
+REMARKS:
+Raise the specified interrupt to be handled before the execution of the
+next instruction.
+
+NOTE: Do not inline this function, as (*sys_rdb) is already inline!
+****************************************************************************/
+void fetch_decode_modrm(
+	int *mod,
+	int *regh,
+	int *regl)
+{
+	int fetched;
+
+DB(	if (CHECK_IP_FETCH())
+	  x86emu_check_ip_access();)
+	fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
+	INC_DECODED_INST_LEN(1);
+	*mod  = (fetched >> 6) & 0x03;
+	*regh = (fetched >> 3) & 0x07;
+    *regl = (fetched >> 0) & 0x07;
+}
+
+/****************************************************************************
+RETURNS:
+Immediate byte value read from instruction queue
+
+REMARKS:
+This function returns the immediate byte from the instruction queue, and
+moves the instruction pointer to the next value.
+
+NOTE: Do not inline this function, as (*sys_rdb) is already inline!
+****************************************************************************/
+u8 fetch_byte_imm(void)
+{
+	u8 fetched;
+
+DB(	if (CHECK_IP_FETCH())
+		x86emu_check_ip_access();)
+	fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
+	INC_DECODED_INST_LEN(1);
+	return fetched;
+}
+
+/****************************************************************************
+RETURNS:
+Immediate word value read from instruction queue
+
+REMARKS:
+This function returns the immediate byte from the instruction queue, and
+moves the instruction pointer to the next value.
+
+NOTE: Do not inline this function, as (*sys_rdw) is already inline!
+****************************************************************************/
+u16 fetch_word_imm(void)
+{
+	u16	fetched;
+
+DB(	if (CHECK_IP_FETCH())
+		x86emu_check_ip_access();)
+	fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP));
+	M.x86.R_IP += 2;
+	INC_DECODED_INST_LEN(2);
+	return fetched;
+}
+
+/****************************************************************************
+RETURNS:
+Immediate lone value read from instruction queue
+
+REMARKS:
+This function returns the immediate byte from the instruction queue, and
+moves the instruction pointer to the next value.
+
+NOTE: Do not inline this function, as (*sys_rdw) is already inline!
+****************************************************************************/
+u32 fetch_long_imm(void)
+{
+	u32 fetched;
+
+DB(	if (CHECK_IP_FETCH())
+	  x86emu_check_ip_access();)
+	fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP));
+	M.x86.R_IP += 4;
+	INC_DECODED_INST_LEN(4);
+	return fetched;
+}
+
+/****************************************************************************
+RETURNS:
+Value of the default data segment
+
+REMARKS:
+Inline function that returns the default data segment for the current
+instruction.
+
+On the x86 processor, the default segment is not always DS if there is
+no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to
+addresses relative to SS (ie: on the stack). So, at the minimum, all
+decodings of addressing modes would have to set/clear a bit describing
+whether the access is relative to DS or SS.  That is the function of the
+cpu-state-varible M.x86.mode. There are several potential states:
+
+	repe prefix seen  (handled elsewhere)
+	repne prefix seen  (ditto)
+
+	cs segment override
+	ds segment override
+	es segment override
+	fs segment override
+	gs segment override
+	ss segment override
+
+	ds/ss select (in absense of override)
+
+Each of the above 7 items are handled with a bit in the mode field.
+****************************************************************************/
+_INLINE u32 get_data_segment(void)
+{
+#define	GET_SEGMENT(segment)
+	switch (M.x86.mode & SYSMODE_SEGMASK) {
+	  case 0:					/* default case: use ds register */
+	  case SYSMODE_SEGOVR_DS:
+	  case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS:
+		return  M.x86.R_DS;
+	  case SYSMODE_SEG_DS_SS:	/* non-overridden, use ss register */
+		return  M.x86.R_SS;
+	  case SYSMODE_SEGOVR_CS:
+	  case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS:
+		return  M.x86.R_CS;
+	  case SYSMODE_SEGOVR_ES:
+	  case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS:
+		return  M.x86.R_ES;
+	  case SYSMODE_SEGOVR_FS:
+	  case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS:
+		return  M.x86.R_FS;
+	  case SYSMODE_SEGOVR_GS:
+	  case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS:
+		return  M.x86.R_GS;
+	  case SYSMODE_SEGOVR_SS:
+	  case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS:
+		return  M.x86.R_SS;
+	  default:
+#ifdef	DEBUG
+		printk("error: should not happen:  multiple overrides.\n");
+#endif
+		HALT_SYS();
+		return 0;
+	}
+}
+
+/****************************************************************************
+PARAMETERS:
+offset	- Offset to load data from
+
+RETURNS:
+Byte value read from the absolute memory location.
+
+NOTE: Do not inline this function as (*sys_rdX) is already inline!
+****************************************************************************/
+u8 fetch_data_byte(
+	uint offset)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access((u16)get_data_segment(), offset);
+#endif
+	return (*sys_rdb)((get_data_segment() << 4) + offset);
+}
+
+/****************************************************************************
+PARAMETERS:
+offset	- Offset to load data from
+
+RETURNS:
+Word value read from the absolute memory location.
+
+NOTE: Do not inline this function as (*sys_rdX) is already inline!
+****************************************************************************/
+u16 fetch_data_word(
+	uint offset)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access((u16)get_data_segment(), offset);
+#endif
+	return (*sys_rdw)((get_data_segment() << 4) + offset);
+}
+
+/****************************************************************************
+PARAMETERS:
+offset	- Offset to load data from
+
+RETURNS:
+Long value read from the absolute memory location.
+
+NOTE: Do not inline this function as (*sys_rdX) is already inline!
+****************************************************************************/
+u32 fetch_data_long(
+	uint offset)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access((u16)get_data_segment(), offset);
+#endif
+	return (*sys_rdl)((get_data_segment() << 4) + offset);
+}
+
+/****************************************************************************
+PARAMETERS:
+segment	- Segment to load data from
+offset	- Offset to load data from
+
+RETURNS:
+Byte value read from the absolute memory location.
+
+NOTE: Do not inline this function as (*sys_rdX) is already inline!
+****************************************************************************/
+u8 fetch_data_byte_abs(
+	uint segment,
+	uint offset)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access(segment, offset);
+#endif
+	return (*sys_rdb)(((u32)segment << 4) + offset);
+}
+
+/****************************************************************************
+PARAMETERS:
+segment	- Segment to load data from
+offset	- Offset to load data from
+
+RETURNS:
+Word value read from the absolute memory location.
+
+NOTE: Do not inline this function as (*sys_rdX) is already inline!
+****************************************************************************/
+u16 fetch_data_word_abs(
+	uint segment,
+	uint offset)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access(segment, offset);
+#endif
+	return (*sys_rdw)(((u32)segment << 4) + offset);
+}
+
+/****************************************************************************
+PARAMETERS:
+segment	- Segment to load data from
+offset	- Offset to load data from
+
+RETURNS:
+Long value read from the absolute memory location.
+
+NOTE: Do not inline this function as (*sys_rdX) is already inline!
+****************************************************************************/
+u32 fetch_data_long_abs(
+	uint segment,
+	uint offset)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access(segment, offset);
+#endif
+	return (*sys_rdl)(((u32)segment << 4) + offset);
+}
+
+/****************************************************************************
+PARAMETERS:
+offset	- Offset to store data at
+val		- Value to store
+
+REMARKS:
+Writes a word value to an segmented memory location. The segment used is
+the current 'default' segment, which may have been overridden.
+
+NOTE: Do not inline this function as (*sys_wrX) is already inline!
+****************************************************************************/
+void store_data_byte(
+	uint offset,
+	u8 val)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access((u16)get_data_segment(), offset);
+#endif
+	(*sys_wrb)((get_data_segment() << 4) + offset, val);
+}
+
+/****************************************************************************
+PARAMETERS:
+offset	- Offset to store data at
+val		- Value to store
+
+REMARKS:
+Writes a word value to an segmented memory location. The segment used is
+the current 'default' segment, which may have been overridden.
+
+NOTE: Do not inline this function as (*sys_wrX) is already inline!
+****************************************************************************/
+void store_data_word(
+	uint offset,
+	u16 val)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access((u16)get_data_segment(), offset);
+#endif
+	(*sys_wrw)((get_data_segment() << 4) + offset, val);
+}
+
+/****************************************************************************
+PARAMETERS:
+offset	- Offset to store data at
+val		- Value to store
+
+REMARKS:
+Writes a long value to an segmented memory location. The segment used is
+the current 'default' segment, which may have been overridden.
+
+NOTE: Do not inline this function as (*sys_wrX) is already inline!
+****************************************************************************/
+void store_data_long(
+	uint offset,
+	u32 val)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access((u16)get_data_segment(), offset);
+#endif
+	(*sys_wrl)((get_data_segment() << 4) + offset, val);
+}
+
+/****************************************************************************
+PARAMETERS:
+segment	- Segment to store data at
+offset	- Offset to store data at
+val		- Value to store
+
+REMARKS:
+Writes a byte value to an absolute memory location.
+
+NOTE: Do not inline this function as (*sys_wrX) is already inline!
+****************************************************************************/
+void store_data_byte_abs(
+	uint segment,
+	uint offset,
+	u8 val)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access(segment, offset);
+#endif
+	(*sys_wrb)(((u32)segment << 4) + offset, val);
+}
+
+/****************************************************************************
+PARAMETERS:
+segment	- Segment to store data at
+offset	- Offset to store data at
+val		- Value to store
+
+REMARKS:
+Writes a word value to an absolute memory location.
+
+NOTE: Do not inline this function as (*sys_wrX) is already inline!
+****************************************************************************/
+void store_data_word_abs(
+	uint segment,
+	uint offset,
+	u16 val)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access(segment, offset);
+#endif
+	(*sys_wrw)(((u32)segment << 4) + offset, val);
+}
+
+/****************************************************************************
+PARAMETERS:
+segment	- Segment to store data at
+offset	- Offset to store data at
+val		- Value to store
+
+REMARKS:
+Writes a long value to an absolute memory location.
+
+NOTE: Do not inline this function as (*sys_wrX) is already inline!
+****************************************************************************/
+void store_data_long_abs(
+	uint segment,
+	uint offset,
+	u32 val)
+{
+#ifdef DEBUG
+	if (CHECK_DATA_ACCESS())
+		x86emu_check_data_access(segment, offset);
+#endif
+	(*sys_wrl)(((u32)segment << 4) + offset, val);
+}
+
+/****************************************************************************
+PARAMETERS:
+reg	- Register to decode
+
+RETURNS:
+Pointer to the appropriate register
+
+REMARKS:
+Return a pointer to the register given by the R/RM field of the
+modrm byte, for byte operands. Also enables the decoding of instructions.
+****************************************************************************/
+u8* decode_rm_byte_register(
+	int reg)
+{
+	switch (reg) {
+      case 0:
+		DECODE_PRINTF("AL");
+		return &M.x86.R_AL;
+	  case 1:
+		DECODE_PRINTF("CL");
+		return &M.x86.R_CL;
+	  case 2:
+		DECODE_PRINTF("DL");
+		return &M.x86.R_DL;
+	  case 3:
+		DECODE_PRINTF("BL");
+		return &M.x86.R_BL;
+	  case 4:
+		DECODE_PRINTF("AH");
+		return &M.x86.R_AH;
+	  case 5:
+		DECODE_PRINTF("CH");
+		return &M.x86.R_CH;
+	  case 6:
+		DECODE_PRINTF("DH");
+		return &M.x86.R_DH;
+	  case 7:
+		DECODE_PRINTF("BH");
+		return &M.x86.R_BH;
+	}
+	HALT_SYS();
+	return NULL;                /* NOT REACHED OR REACHED ON ERROR */
+}
+
+/****************************************************************************
+PARAMETERS:
+reg	- Register to decode
+
+RETURNS:
+Pointer to the appropriate register
+
+REMARKS:
+Return a pointer to the register given by the R/RM field of the
+modrm byte, for word operands.  Also enables the decoding of instructions.
+****************************************************************************/
+u16* decode_rm_word_register(
+	int reg)
+{
+	switch (reg) {
+	  case 0:
+		DECODE_PRINTF("AX");
+		return &M.x86.R_AX;
+	  case 1:
+		DECODE_PRINTF("CX");
+		return &M.x86.R_CX;
+	  case 2:
+		DECODE_PRINTF("DX");
+		return &M.x86.R_DX;
+	  case 3:
+		DECODE_PRINTF("BX");
+		return &M.x86.R_BX;
+	  case 4:
+		DECODE_PRINTF("SP");
+		return &M.x86.R_SP;
+	  case 5:
+		DECODE_PRINTF("BP");
+		return &M.x86.R_BP;
+	  case 6:
+		DECODE_PRINTF("SI");
+		return &M.x86.R_SI;
+	  case 7:
+		DECODE_PRINTF("DI");
+		return &M.x86.R_DI;
+	}
+	HALT_SYS();
+    return NULL;                /* NOTREACHED OR REACHED ON ERROR */
+}
+
+/****************************************************************************
+PARAMETERS:
+reg	- Register to decode
+
+RETURNS:
+Pointer to the appropriate register
+
+REMARKS:
+Return a pointer to the register given by the R/RM field of the
+modrm byte, for dword operands.  Also enables the decoding of instructions.
+****************************************************************************/
+u32* decode_rm_long_register(
+	int reg)
+{
+    switch (reg) {
+      case 0:
+		DECODE_PRINTF("EAX");
+		return &M.x86.R_EAX;
+	  case 1:
+		DECODE_PRINTF("ECX");
+		return &M.x86.R_ECX;
+	  case 2:
+		DECODE_PRINTF("EDX");
+		return &M.x86.R_EDX;
+	  case 3:
+		DECODE_PRINTF("EBX");
+		return &M.x86.R_EBX;
+	  case 4:
+		DECODE_PRINTF("ESP");
+		return &M.x86.R_ESP;
+	  case 5:
+		DECODE_PRINTF("EBP");
+		return &M.x86.R_EBP;
+	  case 6:
+		DECODE_PRINTF("ESI");
+		return &M.x86.R_ESI;
+	  case 7:
+		DECODE_PRINTF("EDI");
+		return &M.x86.R_EDI;
+	}
+	HALT_SYS();
+    return NULL;                /* NOTREACHED OR REACHED ON ERROR */
+}
+
+/****************************************************************************
+PARAMETERS:
+reg	- Register to decode
+
+RETURNS:
+Pointer to the appropriate register
+
+REMARKS:
+Return a pointer to the register given by the R/RM field of the
+modrm byte, for word operands, modified from above for the weirdo
+special case of segreg operands.  Also enables the decoding of instructions.
+****************************************************************************/
+u16* decode_rm_seg_register(
+	int reg)
+{
+	switch (reg) {
+	  case 0:
+		DECODE_PRINTF("ES");
+		return &M.x86.R_ES;
+	  case 1:
+		DECODE_PRINTF("CS");
+		return &M.x86.R_CS;
+	  case 2:
+		DECODE_PRINTF("SS");
+		return &M.x86.R_SS;
+	  case 3:
+		DECODE_PRINTF("DS");
+		return &M.x86.R_DS;
+	  case 4:
+	  case 5:
+	  case 6:
+	  case 7:
+		DECODE_PRINTF("ILLEGAL SEGREG");
+		break;
+	}
+	HALT_SYS();
+	return NULL;                /* NOT REACHED OR REACHED ON ERROR */
+}
+
+/****************************************************************************
+PARAMETERS:
+rm	- RM value to decode
+
+RETURNS:
+Offset in memory for the address decoding
+
+REMARKS:
+Return the offset given by mod=00 addressing.  Also enables the
+decoding of instructions.
+
+NOTE: 	The code which specifies the corresponding segment (ds vs ss)
+		below in the case of [BP+..].  The assumption here is that at the
+		point that this subroutine is called, the bit corresponding to
+		SYSMODE_SEG_DS_SS will be zero.  After every instruction
+		except the segment override instructions, this bit (as well
+		as any bits indicating segment overrides) will be clear.  So
+		if a SS access is needed, set this bit.  Otherwise, DS access
+		occurs (unless any of the segment override bits are set).
+****************************************************************************/
+unsigned decode_rm00_address(
+	int rm)
+{
+	unsigned offset;
+
+	if (M.x86.mode & SYSMODE_PREFIX_ADDR)
+	{
+	    switch (rm) {
+	    case 0:
+		DECODE_PRINTF("[EAX]");
+		return M.x86.R_EAX;
+	    case 1:
+		DECODE_PRINTF("[ECX]");
+		return M.x86.R_ECX;
+	    case 2:
+		DECODE_PRINTF("[EDX]");
+/*		M.x86.mode |= SYSMODE_SEG_DS_SS; */
+		return M.x86.R_EDX;
+	    case 3:
+		DECODE_PRINTF("[EBX]");
+/*		M.x86.mode |= SYSMODE_SEG_DS_SS; */
+		return M.x86.R_EBX;
+	    case 4:
+		printk("Unsupported SIB encoding\n");
+		HALT_SYS();
+		return 0;
+	    case 5:
+		offset = fetch_long_imm();
+		DECODE_PRINTF2("[%08x]", offset);
+		return offset;
+	    case 6:
+		DECODE_PRINTF("[ESI]");
+		return M.x86.R_ESI;
+	    case 7:
+		DECODE_PRINTF("[EDI]");
+		return M.x86.R_EDI;
+	    }
+	}
+	else
+	{
+	    switch (rm) {
+	    case 0:
+		DECODE_PRINTF("[BX+SI]");
+		return M.x86.R_BX + M.x86.R_SI;
+	    case 1:
+		DECODE_PRINTF("[BX+DI]");
+		return M.x86.R_BX + M.x86.R_DI;
+	    case 2:
+		DECODE_PRINTF("[BP+SI]");
+		M.x86.mode |= SYSMODE_SEG_DS_SS;
+		return M.x86.R_BP + M.x86.R_SI;
+	    case 3:
+		DECODE_PRINTF("[BP+DI]");
+		M.x86.mode |= SYSMODE_SEG_DS_SS;
+		return M.x86.R_BP + M.x86.R_DI;
+	    case 4:
+		DECODE_PRINTF("[SI]");
+		return M.x86.R_SI;
+	    case 5:
+		DECODE_PRINTF("[DI]");
+		return M.x86.R_DI;
+	    case 6:
+		offset = fetch_word_imm();
+		DECODE_PRINTF2("[%04x]", offset);
+		return offset;
+	    case 7:
+		DECODE_PRINTF("[BX]");
+		return M.x86.R_BX;
+	    }
+	}
+	HALT_SYS();
+    return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+rm	- RM value to decode
+
+RETURNS:
+Offset in memory for the address decoding
+
+REMARKS:
+Return the offset given by mod=01 addressing.  Also enables the
+decoding of instructions.
+****************************************************************************/
+unsigned decode_rm01_address(
+	int rm)
+{
+    int displacement = (s8)fetch_byte_imm();
+    if (M.x86.mode & SYSMODE_PREFIX_ADDR)
+    {
+	switch (rm)
+	{
+	case 0:
+	    DECODE_PRINTF2("%d[EAX}", displacement);
+	    return M.x86.R_EAX + displacement;
+	case 1:
+	    DECODE_PRINTF2("%d[ECX]", displacement);
+	    return M.x86.R_ECX + displacement;
+	case 2:
+	    DECODE_PRINTF2("%d[EDX]", displacement);
+	    return M.x86.R_EDX + displacement;
+	case 3:
+	    DECODE_PRINTF2("%d[EBX]", displacement);
+	    return M.x86.R_EBX + displacement;
+	case 4:
+	    printk("Unsupported SIB addressing mode\n");
+	    HALT_SYS();
+	    return 0;
+	case 5:
+	    DECODE_PRINTF2("%d[EBP]", displacement);
+	    return M.x86.R_EBP + displacement;
+	case 6:
+	    DECODE_PRINTF2("%d[ESI]", displacement);
+	    return M.x86.R_ESI + displacement;
+	case 7:
+	    DECODE_PRINTF2("%d[EDI]", displacement);
+	    return M.x86.R_EDI + displacement;
+	}
+    }
+    else
+    {
+	switch (rm) {
+	case 0:
+	    DECODE_PRINTF2("%d[BX+SI]", displacement);
+	    return M.x86.R_BX + M.x86.R_SI + displacement;
+	case 1:
+	    DECODE_PRINTF2("%d[BX+DI]", displacement);
+	    return M.x86.R_BX + M.x86.R_DI + displacement;
+	case 2:
+	    DECODE_PRINTF2("%d[BP+SI]", displacement);
+	    M.x86.mode |= SYSMODE_SEG_DS_SS;
+	    return M.x86.R_BP + M.x86.R_SI + displacement;
+	case 3:
+	    DECODE_PRINTF2("%d[BP+DI]", displacement);
+	    M.x86.mode |= SYSMODE_SEG_DS_SS;
+	    return M.x86.R_BP + M.x86.R_DI + displacement;
+	case 4:
+	    DECODE_PRINTF2("%d[SI]", displacement);
+	    return M.x86.R_SI + displacement;
+	case 5:
+	    DECODE_PRINTF2("%d[DI]", displacement);
+	    return M.x86.R_DI + displacement;
+	case 6:
+	    DECODE_PRINTF2("%d[BP]", displacement);
+	    M.x86.mode |= SYSMODE_SEG_DS_SS;
+	    return M.x86.R_BP + displacement;
+	case 7:
+	    DECODE_PRINTF2("%d[BX]", displacement);
+	    return M.x86.R_BX + displacement;
+	}
+	HALT_SYS();
+    }
+    return 0;                   /* SHOULD NOT HAPPEN */
+}
+
+/****************************************************************************
+PARAMETERS:
+rm	- RM value to decode
+
+RETURNS:
+Offset in memory for the address decoding
+
+REMARKS:
+Return the offset given by mod=10 addressing.  Also enables the
+decoding of instructions.
+****************************************************************************/
+unsigned decode_rm10_address(
+	int rm)
+{
+    if (M.x86.mode & SYSMODE_PREFIX_ADDR)
+    {
+	int displacement = (s32)fetch_long_imm();
+	switch (rm)
+	{
+	case 0:
+	    DECODE_PRINTF2("%d[EAX}", displacement);
+	    return M.x86.R_EAX + displacement;
+	case 1:
+	    DECODE_PRINTF2("%d[ECX]", displacement);
+	    return M.x86.R_ECX + displacement;
+	case 2:
+	    DECODE_PRINTF2("%d[EDX]", displacement);
+	    return M.x86.R_EDX + displacement;
+	case 3:
+	    DECODE_PRINTF2("%d[EBX]", displacement);
+	    return M.x86.R_EBX + displacement;
+	case 4:
+	    printk("Unsupported SIB addressing mode\n");
+	    HALT_SYS();
+	    return 0;
+	case 5:
+	    DECODE_PRINTF2("%d[EBP]", displacement);
+	    return M.x86.R_EBP + displacement;
+	case 6:
+	    DECODE_PRINTF2("%d[ESI]", displacement);
+	    return M.x86.R_ESI + displacement;
+	case 7:
+	    DECODE_PRINTF2("%d[EDI]", displacement);
+	    return M.x86.R_EDI + displacement;
+	}
+    }
+    else
+    {
+	int displacement = (s16)fetch_word_imm();
+	switch (rm) {
+	case 0:
+	    DECODE_PRINTF2("%d[BX+SI]", displacement);
+	    return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff;
+	case 1:
+	    DECODE_PRINTF2("%d[BX+DI]", displacement);
+	    return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff;
+	case 2:
+	    DECODE_PRINTF2("%d[BP+SI]", displacement);
+	    M.x86.mode |= SYSMODE_SEG_DS_SS;
+	    return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff;
+	case 3:
+	    DECODE_PRINTF2("%d[BP+DI]", displacement);
+	    M.x86.mode |= SYSMODE_SEG_DS_SS;
+	    return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff;
+	case 4:
+	    DECODE_PRINTF2("%d[SI]", displacement);
+	    return (M.x86.R_SI + displacement) & 0xffff;
+	case 5:
+	    DECODE_PRINTF2("%d[DI]", displacement);
+	    return (M.x86.R_DI + displacement) & 0xffff;
+	case 6:
+	    DECODE_PRINTF2("%d[BP]", displacement);
+	    M.x86.mode |= SYSMODE_SEG_DS_SS;
+	    return (M.x86.R_BP + displacement) & 0xffff;
+	case 7:
+	    DECODE_PRINTF2("%d[BX]", displacement);
+	    return (M.x86.R_BX + displacement) & 0xffff;
+	}
+    }
+    HALT_SYS();
+    return 0;
+    /*NOTREACHED */
+}
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c b/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c
new file mode 100755
index 0000000..7f7c345
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c
@@ -0,0 +1,945 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  This file contains the code to implement the decoding and
+*               emulation of the FPU instructions.
+*
+****************************************************************************/
+
+#include "x86emu/x86emui.h"
+
+/*----------------------------- Implementation ----------------------------*/
+
+/* opcode=0xd8 */
+void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("ESC D8\n");
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR_NO_TRACE();
+}
+
+#ifdef DEBUG
+
+static char *x86emu_fpu_op_d9_tab[] = {
+    "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ",
+    "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t",
+
+    "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ",
+    "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t",
+
+    "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ",
+    "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t",
+};
+
+static char *x86emu_fpu_op_d9_tab1[] = {
+    "FLD\t", "FLD\t", "FLD\t", "FLD\t",
+    "FLD\t", "FLD\t", "FLD\t", "FLD\t",
+
+    "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t",
+    "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t",
+
+    "FNOP", "ESC_D9", "ESC_D9", "ESC_D9",
+    "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9",
+
+    "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t",
+    "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t",
+
+    "FCHS", "FABS", "ESC_D9", "ESC_D9",
+    "FTST", "FXAM", "ESC_D9", "ESC_D9",
+
+    "FLD1", "FLDL2T", "FLDL2E", "FLDPI",
+    "FLDLG2", "FLDLN2", "FLDZ", "ESC_D9",
+
+    "F2XM1", "FYL2X", "FPTAN", "FPATAN",
+    "FXTRACT", "ESC_D9", "FDECSTP", "FINCSTP",
+
+    "FPREM", "FYL2XP1", "FSQRT", "ESC_D9",
+    "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9",
+};
+
+#endif /* DEBUG */
+
+/* opcode=0xd9 */
+void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+	uint destoffset;
+    u8 stkelem;
+
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (mod != 3) {
+	DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl);
+    } else {
+	DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]);
+    }
+#endif
+    switch (mod) {
+      case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 3:                   /* register to register */
+		stkelem = (u8)rl;
+		if (rh < 4) {
+				DECODE_PRINTF2("ST(%d)\n", stkelem);
+		} else {
+				DECODE_PRINTF("\n");
+		}
+	break;
+    }
+#ifdef X86EMU_FPU_PRESENT
+    /* execute */
+    switch (mod) {
+      case 3:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem);
+	    break;
+	  case 1:
+	    x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem);
+	    break;
+	  case 2:
+	    switch (rl) {
+	      case 0:
+		x86emu_fpu_R_nop();
+		break;
+	      default:
+		x86emu_fpu_illegal();
+		break;
+	    }
+	  case 3:
+	    x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem);
+	    break;
+	  case 4:
+	    switch (rl) {
+	    case 0:
+		x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP);
+		break;
+	    case 1:
+		x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP);
+		break;
+	    case 4:
+		x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP);
+		break;
+	    case 5:
+		x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP);
+		break;
+	    default:
+		/* 2,3,6,7 */
+		x86emu_fpu_illegal();
+		break;
+	    }
+	    break;
+
+	  case 5:
+	    switch (rl) {
+	      case 0:
+		x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP);
+		break;
+	      case 1:
+		x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP);
+		break;
+	      case 2:
+		x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP);
+		break;
+	      case 3:
+		x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP);
+		break;
+	      case 4:
+		x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP);
+		break;
+	      case 5:
+		x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP);
+		break;
+	      case 6:
+		x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP);
+		break;
+	      default:
+		/* 7 */
+		x86emu_fpu_illegal();
+		break;
+	    }
+	    break;
+
+	  case 6:
+	    switch (rl) {
+	      case 0:
+		x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP);
+		break;
+	      case 1:
+		x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP);
+		break;
+	      case 2:
+		x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP);
+		break;
+	      case 3:
+		x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP);
+		break;
+	      case 4:
+		x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP);
+		break;
+	      case 5:
+		x86emu_fpu_illegal();
+		break;
+	      case 6:
+		x86emu_fpu_R_decstp();
+		break;
+	      case 7:
+		x86emu_fpu_R_incstp();
+		break;
+	    }
+	    break;
+
+	  case 7:
+	    switch (rl) {
+	      case 0:
+		x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP);
+		break;
+	      case 1:
+		x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP);
+		break;
+	      case 2:
+		x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP);
+		break;
+	      case 3:
+		x86emu_fpu_illegal();
+		break;
+	      case 4:
+		x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP);
+		break;
+	      case 5:
+		x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP);
+		break;
+	      case 6:
+	      case 7:
+	      default:
+		x86emu_fpu_illegal();
+		break;
+	    }
+	    break;
+
+	  default:
+	    switch (rh) {
+	      case 0:
+		x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset);
+		break;
+	      case 1:
+		x86emu_fpu_illegal();
+		break;
+	      case 2:
+		x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset);
+		break;
+	      case 3:
+		x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset);
+		break;
+	      case 4:
+		x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset);
+		break;
+	      case 5:
+		x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset);
+		break;
+	      case 6:
+		x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset);
+		break;
+	      case 7:
+		x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset);
+		break;
+	    }
+	}
+    }
+#endif /* X86EMU_FPU_PRESENT */
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR_NO_TRACE();
+}
+
+#ifdef DEBUG
+
+char *x86emu_fpu_op_da_tab[] = {
+    "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ",
+    "FICOMP\tDWORD PTR ",
+    "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ",
+    "FIDIVR\tDWORD PTR ",
+
+    "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ",
+    "FICOMP\tDWORD PTR ",
+    "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ",
+    "FIDIVR\tDWORD PTR ",
+
+    "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ",
+    "FICOMP\tDWORD PTR ",
+    "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ",
+    "FIDIVR\tDWORD PTR ",
+
+    "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ",
+    "ESC_DA     ", "ESC_DA ", "ESC_DA   ", "ESC_DA ",
+};
+
+#endif /* DEBUG */
+
+/* opcode=0xda */
+void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+	uint destoffset;
+    u8 stkelem;
+
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl);
+    switch (mod) {
+      case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 3:           /* register to register */
+		stkelem = (u8)rl;
+	DECODE_PRINTF2("\tST(%d),ST\n", stkelem);
+	break;
+    }
+#ifdef X86EMU_FPU_PRESENT
+    switch (mod) {
+      case 3:
+	x86emu_fpu_illegal();
+	break;
+      default:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 1:
+	    x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 2:
+	    x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 3:
+	    x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 4:
+	    x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 5:
+	    x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 6:
+	    x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 7:
+	    x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	}
+    }
+#endif
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR_NO_TRACE();
+}
+
+#ifdef DEBUG
+
+char *x86emu_fpu_op_db_tab[] = {
+    "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ",
+    "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ",
+
+    "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ",
+    "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ",
+
+    "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ",
+    "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ",
+};
+
+#endif /* DEBUG */
+
+/* opcode=0xdb */
+void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+	uint destoffset;
+
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (mod != 3) {
+	DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl);
+    } else if (rh == 4) {       /* === 11 10 0 nnn */
+	switch (rl) {
+	  case 0:
+	    DECODE_PRINTF("FENI\n");
+	    break;
+	  case 1:
+	    DECODE_PRINTF("FDISI\n");
+	    break;
+	  case 2:
+	    DECODE_PRINTF("FCLEX\n");
+	    break;
+	  case 3:
+	    DECODE_PRINTF("FINIT\n");
+	    break;
+	}
+    } else {
+	DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl));
+    }
+#endif /* DEBUG */
+    switch (mod) {
+      case 0:
+	destoffset = decode_rm00_address(rl);
+	break;
+      case 1:
+	destoffset = decode_rm01_address(rl);
+	break;
+      case 2:
+	destoffset = decode_rm10_address(rl);
+	break;
+      case 3:                   /* register to register */
+	break;
+    }
+#ifdef X86EMU_FPU_PRESENT
+    /* execute */
+    switch (mod) {
+      case 3:
+	switch (rh) {
+	  case 4:
+	    switch (rl) {
+	      case 0:
+		x86emu_fpu_R_feni();
+		break;
+	      case 1:
+		x86emu_fpu_R_fdisi();
+		break;
+	      case 2:
+		x86emu_fpu_R_fclex();
+		break;
+	      case 3:
+		x86emu_fpu_R_finit();
+		break;
+	      default:
+		x86emu_fpu_illegal();
+		break;
+	    }
+	    break;
+	  default:
+	    x86emu_fpu_illegal();
+	    break;
+	}
+	break;
+      default:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 1:
+	    x86emu_fpu_illegal();
+	    break;
+	  case 2:
+	    x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 3:
+	    x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset);
+	    break;
+	  case 4:
+	    x86emu_fpu_illegal();
+	    break;
+	  case 5:
+	    x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset);
+	    break;
+		      case 6:
+	    x86emu_fpu_illegal();
+	    break;
+	  case 7:
+	    x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset);
+	    break;
+	}
+    }
+#endif
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR_NO_TRACE();
+}
+
+#ifdef DEBUG
+char *x86emu_fpu_op_dc_tab[] = {
+    "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ",
+    "FCOMP\tQWORD PTR ",
+    "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ",
+    "FDIVR\tQWORD PTR ",
+
+    "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ",
+    "FCOMP\tQWORD PTR ",
+    "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ",
+    "FDIVR\tQWORD PTR ",
+
+    "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ",
+    "FCOMP\tQWORD PTR ",
+    "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ",
+    "FDIVR\tQWORD PTR ",
+
+    "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t",
+    "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t",
+};
+#endif /* DEBUG */
+
+/* opcode=0xdc */
+void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+	uint destoffset;
+    u8 stkelem;
+
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl);
+    switch (mod) {
+      case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 3:                   /* register to register */
+		stkelem = (u8)rl;
+	DECODE_PRINTF2("\tST(%d),ST\n", stkelem);
+	break;
+    }
+#ifdef X86EMU_FPU_PRESENT
+    /* execute */
+    switch (mod) {
+      case 3:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 1:
+	    x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 2:
+	    x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 3:
+	    x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 4:
+	    x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 5:
+	    x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 6:
+	    x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 7:
+	    x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	}
+	break;
+      default:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 1:
+	    x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 2:
+	    x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 3:
+	    x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 4:
+	    x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 5:
+	    x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 6:
+	    x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 7:
+	    x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	}
+    }
+#endif
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR_NO_TRACE();
+}
+
+#ifdef DEBUG
+
+static char *x86emu_fpu_op_dd_tab[] = {
+    "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ",
+    "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t",
+
+    "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ",
+    "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t",
+
+    "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ",
+    "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t",
+
+    "FFREE\t", "FXCH\t", "FST\t", "FSTP\t",
+    "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,",
+};
+
+#endif /* DEBUG */
+
+/* opcode=0xdd */
+void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+	uint destoffset;
+    u8 stkelem;
+
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl);
+    switch (mod) {
+      case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 3:                   /* register to register */
+		stkelem = (u8)rl;
+	DECODE_PRINTF2("\tST(%d),ST\n", stkelem);
+	break;
+    }
+#ifdef X86EMU_FPU_PRESENT
+    switch (mod) {
+      case 3:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_R_ffree(stkelem);
+	    break;
+	  case 1:
+	    x86emu_fpu_R_fxch(stkelem);
+	    break;
+	  case 2:
+	    x86emu_fpu_R_fst(stkelem);  /* register version */
+	    break;
+	  case 3:
+	    x86emu_fpu_R_fstp(stkelem); /* register version */
+	    break;
+	  default:
+	    x86emu_fpu_illegal();
+	    break;
+	}
+	break;
+      default:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 1:
+	    x86emu_fpu_illegal();
+	    break;
+	  case 2:
+	    x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 3:
+	    x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset);
+	    break;
+	  case 4:
+	    x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 5:
+	    x86emu_fpu_illegal();
+	    break;
+	  case 6:
+	    x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 7:
+	    x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset);
+	    break;
+	}
+    }
+#endif
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR_NO_TRACE();
+}
+
+#ifdef DEBUG
+
+static char *x86emu_fpu_op_de_tab[] =
+{
+    "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ",
+    "FICOMP\tWORD PTR ",
+    "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ",
+    "FIDIVR\tWORD PTR ",
+
+    "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ",
+    "FICOMP\tWORD PTR ",
+    "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ",
+    "FIDIVR\tWORD PTR ",
+
+    "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ",
+    "FICOMP\tWORD PTR ",
+    "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ",
+    "FIDIVR\tWORD PTR ",
+
+    "FADDP\t", "FMULP\t", "FCOMP\t", "FCOMPP\t",
+    "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t",
+};
+
+#endif /* DEBUG */
+
+/* opcode=0xde */
+void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+	uint destoffset;
+    u8 stkelem;
+
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl);
+    switch (mod) {
+      case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 3:                   /* register to register */
+		stkelem = (u8)rl;
+	DECODE_PRINTF2("\tST(%d),ST\n", stkelem);
+	break;
+    }
+#ifdef X86EMU_FPU_PRESENT
+    switch (mod) {
+      case 3:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 1:
+	    x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 2:
+	    x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 3:
+	    if (stkelem == 1)
+	      x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP);
+	    else
+	      x86emu_fpu_illegal();
+	    break;
+	  case 4:
+	    x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 5:
+	    x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 6:
+	    x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	  case 7:
+	    x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP);
+	    break;
+	}
+	break;
+      default:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 1:
+	    x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 2:
+	    x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 3:
+	    x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 4:
+	    x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 5:
+	    x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 6:
+	    x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 7:
+	    x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset);
+	    break;
+	}
+    }
+#endif
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR_NO_TRACE();
+}
+
+#ifdef DEBUG
+
+static char *x86emu_fpu_op_df_tab[] = {
+    /* mod == 00 */
+    "FILD\tWORD PTR ", "ESC_DF\t39\n", "FIST\tWORD PTR ", "FISTP\tWORD PTR ",
+    "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ",
+    "FISTP\tQWORD PTR ",
+
+    /* mod == 01 */
+    "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ",
+    "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ",
+    "FISTP\tQWORD PTR ",
+
+    /* mod == 10 */
+    "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ",
+    "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ",
+    "FISTP\tQWORD PTR ",
+
+    /* mod == 11 */
+    "FFREE\t", "FXCH\t", "FST\t", "FSTP\t",
+    "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F,"
+};
+
+#endif /* DEBUG */
+
+/* opcode=0xdf */
+void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+	uint destoffset;
+    u8 stkelem;
+
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl);
+    switch (mod) {
+      case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	break;
+      case 3:                   /* register to register */
+		stkelem = (u8)rl;
+	DECODE_PRINTF2("\tST(%d)\n", stkelem);
+	break;
+    }
+#ifdef X86EMU_FPU_PRESENT
+    switch (mod) {
+      case 3:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_R_ffree(stkelem);
+	    break;
+	  case 1:
+	    x86emu_fpu_R_fxch(stkelem);
+	    break;
+	  case 2:
+	    x86emu_fpu_R_fst(stkelem);  /* register version */
+	    break;
+	  case 3:
+	    x86emu_fpu_R_fstp(stkelem); /* register version */
+	    break;
+	  default:
+	    x86emu_fpu_illegal();
+	    break;
+	}
+	break;
+      default:
+	switch (rh) {
+	  case 0:
+	    x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 1:
+	    x86emu_fpu_illegal();
+	    break;
+	  case 2:
+	    x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 3:
+	    x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset);
+	    break;
+	  case 4:
+	    x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset);
+	    break;
+	  case 5:
+	    x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset);
+	    break;
+	  case 6:
+	    x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset);
+	    break;
+	  case 7:
+	    x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset);
+	    break;
+	}
+    }
+#endif
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR_NO_TRACE();
+}
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile b/board/MAI/bios_emulator/scitech/src/x86emu/makefile
new file mode 100755
index 0000000..8ce2e9e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile
@@ -0,0 +1,63 @@
+#############################################################################
+#
+#						Realmode X86 Emulator Library
+#
+#            	Copyright (C) 1996-1999 SciTech Software, Inc.
+#
+#  ========================================================================
+#
+#  Permission to use, copy, modify, distribute, and sell this software and
+#  its documentation for any purpose is hereby granted without fee,
+#  provided that the above copyright notice appear in all copies and that
+#  both that copyright notice and this permission notice appear in
+#  supporting documentation, and that the name of the authors not be used
+#  in advertising or publicity pertaining to distribution of the software
+#  without specific, written prior permission.  The authors makes no
+#  representations about the suitability of this software for any purpose.
+#  It is provided "as is" without express or implied warranty.
+#
+#  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+#  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+#  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+#  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+#  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+#  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+#  PERFORMANCE OF THIS SOFTWARE.
+#
+#  ========================================================================
+#
+# Descripton:   Generic makefile for the x86emu library. Requires
+#               the SciTech Software makefile definitions package to be
+#               installed, which uses the DMAKE make program.
+#
+#############################################################################
+
+.IMPORT .IGNORE: DEBUG
+
+#----------------------------------------------------------------------------
+# Define the lists of object files
+#----------------------------------------------------------------------------
+
+OBJECTS			= sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O
+CFLAGS      	+= -DSCITECH
+.IF $(DEBUG)
+CFLAGS			+= -DDEBUG
+.ENDIF
+LIBCLEAN  		= *.dll *.lib *.a
+LIBFILE 		= $(LP)x86emu$L
+
+#----------------------------------------------------------------------------
+# Sample test programs
+#----------------------------------------------------------------------------
+
+all: $(LIBFILE)
+
+validate$E: validate$O $(LIBFILE)
+
+#----------------------------------------------------------------------------
+# Define the list of object files to create dependency information for
+#----------------------------------------------------------------------------
+
+DEPEND_OBJ      =  validate$O $(OBJECTS)
+
+.INCLUDE: "$(SCITECH)/makedefs/common.mk"
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross
new file mode 100755
index 0000000..0bce9a9
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross
@@ -0,0 +1,82 @@
+#############################################################################
+#
+#						Realmode X86 Emulator Library
+#
+#            	Copyright (C) 1996-1999 SciTech Software, Inc.
+#
+#  ========================================================================
+#
+#  Permission to use, copy, modify, distribute, and sell this software and
+#  its documentation for any purpose is hereby granted without fee,
+#  provided that the above copyright notice appear in all copies and that
+#  both that copyright notice and this permission notice appear in
+#  supporting documentation, and that the name of the authors not be used
+#  in advertising or publicity pertaining to distribution of the software
+#  without specific, written prior permission.  The authors makes no
+#  representations about the suitability of this software for any purpose.
+#  It is provided "as is" without express or implied warranty.
+#
+#  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+#  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+#  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+#  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+#  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+#  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+#  PERFORMANCE OF THIS SOFTWARE.
+#
+#  ========================================================================
+#
+# Descripton:   Linux specific makefile for the x86emu library.
+#
+#############################################################################
+
+CC = $(CROSS_COMPILE)gcc
+AR = $(CROSS_COMPILE)ar
+
+TARGETLIB = libx86emu.a
+TARGETDEBUGLIB =libx86emud.a
+
+OBJS=\
+decode.o \
+fpu.o \
+ops.o \
+ops2.o \
+prim_ops.o \
+sys.o
+
+DEBUGOBJS=debug.d \
+          decode.d \
+	  fpu.d \
+	  ops.d \
+	  ops2.d \
+	  prim_ops.d \
+	  sys.d
+
+.SUFFIXES: .d
+
+all: $(TARGETLIB) $(TARGETDEBUGLIB)
+
+$(TARGETLIB): $(OBJS)
+	$(AR) rv $(TARGETLIB) $(OBJS)
+
+$(TARGETDEBUGLIB): $(DEBUGOBJS)
+	$(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
+
+INCS   = -I. -Ix86emu -I../../include
+CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -fPIC -ffixed-r14 -meabi
+CDEBUGFLAGS = -DDEBUG
+
+.c.o:
+	$(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c
+
+.c.d:
+	$(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c
+
+.cpp.o:
+	$(CC) -c $(CFLAGS) $(INCS) $*.cpp
+
+clean:
+	rm -f *.a *.o *.d
+
+validate:	validate.o libx86emu.a
+	$(CC) -o validate validate.o -lx86emu -L.
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux
new file mode 100755
index 0000000..f74b88d
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux
@@ -0,0 +1,81 @@
+#############################################################################
+#
+#						Realmode X86 Emulator Library
+#
+#            	Copyright (C) 1996-1999 SciTech Software, Inc.
+#
+#  ========================================================================
+#
+#  Permission to use, copy, modify, distribute, and sell this software and
+#  its documentation for any purpose is hereby granted without fee,
+#  provided that the above copyright notice appear in all copies and that
+#  both that copyright notice and this permission notice appear in
+#  supporting documentation, and that the name of the authors not be used
+#  in advertising or publicity pertaining to distribution of the software
+#  without specific, written prior permission.  The authors makes no
+#  representations about the suitability of this software for any purpose.
+#  It is provided "as is" without express or implied warranty.
+#
+#  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+#  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+#  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+#  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+#  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+#  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+#  PERFORMANCE OF THIS SOFTWARE.
+#
+#  ========================================================================
+#
+# Descripton:   Linux specific makefile for the x86emu library.
+#
+#############################################################################
+
+TARGETLIB = libx86emu.a
+TARGETDEBUGLIB =libx86emud.a
+
+OBJS=\
+decode.o \
+fpu.o \
+ops.o \
+ops2.o \
+prim_ops.o \
+pregs.o \
+sys.o
+
+DEBUGOBJS=debug.d \
+          decode.d \
+	  fpu.d \
+	  ops.d \
+	  ops2.d \
+	  prim_ops.d \
+	  pregs.d \
+	  sys.d
+
+.SUFFIXES: .d
+
+all: $(TARGETLIB) $(TARGETDEBUGLIB)
+
+$(TARGETLIB): $(OBJS)
+	ar rv $(TARGETLIB) $(OBJS)
+
+$(TARGETDEBUGLIB): $(DEBUGOBJS)
+	ar rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
+
+INCS   = -I. -Ix86emu -I../../include
+CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG
+CDEBUGFLAGS = -DDEBUG
+
+.c.o:
+	gcc -g -O -Wall -c $(CFLAGS) $(INCS) $*.c
+
+.c.d:
+	gcc -g -O -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c
+
+.cpp.o:
+	gcc -c $(CFLAGS) $(INCS) $*.cpp
+
+clean:
+	rm -f *.a *.o *.d
+
+validate:	validate.o libx86emu.a
+	gcc -o validate validate.o -lx86emu -L.
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot
new file mode 100755
index 0000000..af9ae1f
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot
@@ -0,0 +1,80 @@
+#############################################################################
+#
+#						Realmode X86 Emulator Library
+#
+#            	Copyright (C) 1996-1999 SciTech Software, Inc.
+#
+#  ========================================================================
+#
+#  Permission to use, copy, modify, distribute, and sell this software and
+#  its documentation for any purpose is hereby granted without fee,
+#  provided that the above copyright notice appear in all copies and that
+#  both that copyright notice and this permission notice appear in
+#  supporting documentation, and that the name of the authors not be used
+#  in advertising or publicity pertaining to distribution of the software
+#  without specific, written prior permission.  The authors makes no
+#  representations about the suitability of this software for any purpose.
+#  It is provided "as is" without express or implied warranty.
+#
+#  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+#  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+#  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+#  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+#  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+#  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+#  PERFORMANCE OF THIS SOFTWARE.
+#
+#  ========================================================================
+#
+# Descripton:   Linux specific makefile for the x86emu library.
+#
+#############################################################################
+CC = $(CROSS_COMPILE)gcc
+AR = $(CROSS_COMPILE)ar
+TARGETLIB = libx86emu.a
+TARGETDEBUGLIB =libx86emud.a
+
+OBJS=\
+decode.o \
+fpu.o \
+ops.o \
+ops2.o \
+prim_ops.o \
+sys.o
+
+DEBUGOBJS=debug.d \
+          decode.d \
+	  fpu.d \
+	  ops.d \
+	  ops2.d \
+	  prim_ops.d \
+	  sys.d
+
+.SUFFIXES: .d
+
+all: $(TARGETLIB) $(TARGETDEBUGLIB)
+
+$(TARGETLIB): $(OBJS)
+	$(AR) rv $(TARGETLIB) $(OBJS)
+
+$(TARGETDEBUGLIB): $(DEBUGOBJS)
+	$(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
+
+INCS   = -I. -Ix86emu -I../../include
+CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char  -fomit-frame-pointer -fPIC -ffixed-r14 -meabi
+CDEBUGFLAGS = -DDEBUG
+
+.c.o:
+	$(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c
+
+.c.d:
+	$(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c
+
+.cpp.o:
+	$(CC) -c $(CFLAGS) $(INCS) $*.cpp
+
+clean:
+	rm -f *.a *.o *.d
+
+validate:	validate.o libx86emu.a
+	$(CC) -o validate validate.o -lx86emu -L.
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/ops.c b/board/MAI/bios_emulator/scitech/src/x86emu/ops.c
new file mode 100755
index 0000000..2d4f93e
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/ops.c
@@ -0,0 +1,11701 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  This file includes subroutines to implement the decoding
+*               and emulation of all the x86 processor instructions.
+*
+* There are approximately 250 subroutines in here, which correspond
+* to the 256 byte-"opcodes" found on the 8086.  The table which
+* dispatches this is found in the files optab.[ch].
+*
+* Each opcode proc has a comment preceeding it which gives it's table
+* address.  Several opcodes are missing (undefined) in the table.
+*
+* Each proc includes information for decoding (DECODE_PRINTF and
+* DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc
+* functions (START_OF_INSTR, END_OF_INSTR).
+*
+* Many of the procedures are *VERY* similar in coding.  This has
+* allowed for a very large amount of code to be generated in a fairly
+* short amount of time (i.e. cut, paste, and modify).  The result is
+* that much of the code below could have been folded into subroutines
+* for a large reduction in size of this file.  The downside would be
+* that there would be a penalty in execution speed.  The file could
+* also have been *MUCH* larger by inlining certain functions which
+* were called.  This could have resulted even faster execution.  The
+* prime directive I used to decide whether to inline the code or to
+* modularize it, was basically: 1) no unnecessary subroutine calls,
+* 2) no routines more than about 200 lines in size, and 3) modularize
+* any code that I might not get right the first time.  The fetch_*
+* subroutines fall into the latter category.  The The decode_* fall
+* into the second category.  The coding of the "switch(mod){ .... }"
+* in many of the subroutines below falls into the first category.
+* Especially, the coding of {add,and,or,sub,...}_{byte,word}
+* subroutines are an especially glaring case of the third guideline.
+* Since so much of the code is cloned from other modules (compare
+* opcode #00 to opcode #01), making the basic operations subroutine
+* calls is especially important; otherwise mistakes in coding an
+* "add" would represent a nightmare in maintenance.
+*
+****************************************************************************/
+
+#include "x86emu/x86emui.h"
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+op1 - Instruction op code
+
+REMARKS:
+Handles illegal opcodes.
+****************************************************************************/
+void x86emuOp_illegal_op(
+    u8 op1)
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("ILLEGAL X86 OPCODE\n");
+    TRACE_REGS();
+    printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n",
+	M.x86.R_CS, M.x86.R_IP-1,op1);
+    HALT_SYS();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x00
+****************************************************************************/
+void x86emuOp_add_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+    u8 *destreg, *srcreg;
+    u8 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADD\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = add_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = add_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = add_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = add_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x01
+****************************************************************************/
+void x86emuOp_add_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADD\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = add_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = add_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = add_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = add_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = add_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = add_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x02
+****************************************************************************/
+void x86emuOp_add_byte_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint srcoffset;
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADD\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = add_byte(*destreg, srcval);
+	break;
+    case 1:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = add_byte(*destreg, srcval);
+	break;
+    case 2:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = add_byte(*destreg, srcval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = add_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x03
+****************************************************************************/
+void x86emuOp_add_word_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADD\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_word(*destreg, srcval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_word(*destreg, srcval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_word(*destreg, srcval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = add_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x04
+****************************************************************************/
+void x86emuOp_add_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADD\tAL,");
+    srcval = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    M.x86.R_AL = add_byte(M.x86.R_AL, srcval);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x05
+****************************************************************************/
+void x86emuOp_add_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("ADD\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("ADD\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = add_long(M.x86.R_EAX, srcval);
+    } else {
+	M.x86.R_AX = add_word(M.x86.R_AX, (u16)srcval);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x06
+****************************************************************************/
+void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("PUSH\tES\n");
+    TRACE_AND_STEP();
+    push_word(M.x86.R_ES);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x07
+****************************************************************************/
+void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("POP\tES\n");
+    TRACE_AND_STEP();
+    M.x86.R_ES = pop_word();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x08
+****************************************************************************/
+void x86emuOp_or_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint destoffset;
+    u8 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("OR\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = or_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = or_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = or_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = or_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x09
+****************************************************************************/
+void x86emuOp_or_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("OR\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = or_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = or_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = or_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = or_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = or_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = or_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0a
+****************************************************************************/
+void x86emuOp_or_byte_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint srcoffset;
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("OR\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = or_byte(*destreg, srcval);
+	break;
+    case 1:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = or_byte(*destreg, srcval);
+	break;
+    case 2:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = or_byte(*destreg, srcval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = or_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0b
+****************************************************************************/
+void x86emuOp_or_word_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("OR\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_word(*destreg, srcval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_word(*destreg, srcval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_word(*destreg, srcval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = or_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0c
+****************************************************************************/
+void x86emuOp_or_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("OR\tAL,");
+    srcval = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    M.x86.R_AL = or_byte(M.x86.R_AL, srcval);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0d
+****************************************************************************/
+void x86emuOp_or_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("OR\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("OR\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = or_long(M.x86.R_EAX, srcval);
+    } else {
+	M.x86.R_AX = or_word(M.x86.R_AX, (u16)srcval);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0e
+****************************************************************************/
+void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("PUSH\tCS\n");
+    TRACE_AND_STEP();
+    push_word(M.x86.R_CS);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f. Escape for two-byte opcode (286 or better)
+****************************************************************************/
+void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1))
+{
+    u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
+    INC_DECODED_INST_LEN(1);
+    (*x86emu_optab2[op2])(op2);
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x10
+****************************************************************************/
+void x86emuOp_adc_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint destoffset;
+    u8 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADC\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = adc_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = adc_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = adc_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = adc_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x11
+****************************************************************************/
+void x86emuOp_adc_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADC\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = adc_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = adc_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = adc_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = adc_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = adc_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = adc_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x12
+****************************************************************************/
+void x86emuOp_adc_byte_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint srcoffset;
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADC\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = adc_byte(*destreg, srcval);
+	break;
+    case 1:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = adc_byte(*destreg, srcval);
+	break;
+    case 2:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = adc_byte(*destreg, srcval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = adc_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x13
+****************************************************************************/
+void x86emuOp_adc_word_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADC\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_word(*destreg, srcval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_word(*destreg, srcval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_word(*destreg, srcval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = adc_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x14
+****************************************************************************/
+void x86emuOp_adc_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("ADC\tAL,");
+    srcval = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    M.x86.R_AL = adc_byte(M.x86.R_AL, srcval);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x15
+****************************************************************************/
+void x86emuOp_adc_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("ADC\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("ADC\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = adc_long(M.x86.R_EAX, srcval);
+    } else {
+	M.x86.R_AX = adc_word(M.x86.R_AX, (u16)srcval);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x16
+****************************************************************************/
+void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("PUSH\tSS\n");
+    TRACE_AND_STEP();
+    push_word(M.x86.R_SS);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x17
+****************************************************************************/
+void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("POP\tSS\n");
+    TRACE_AND_STEP();
+    M.x86.R_SS = pop_word();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x18
+****************************************************************************/
+void x86emuOp_sbb_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint destoffset;
+    u8 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SBB\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = sbb_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = sbb_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = sbb_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sbb_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x19
+****************************************************************************/
+void x86emuOp_sbb_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SBB\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sbb_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sbb_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sbb_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sbb_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sbb_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sbb_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x1a
+****************************************************************************/
+void x86emuOp_sbb_byte_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint srcoffset;
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SBB\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sbb_byte(*destreg, srcval);
+	break;
+    case 1:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sbb_byte(*destreg, srcval);
+	break;
+    case 2:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sbb_byte(*destreg, srcval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sbb_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x1b
+****************************************************************************/
+void x86emuOp_sbb_word_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SBB\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_word(*destreg, srcval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_word(*destreg, srcval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_word(*destreg, srcval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sbb_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x1c
+****************************************************************************/
+void x86emuOp_sbb_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SBB\tAL,");
+    srcval = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    M.x86.R_AL = sbb_byte(M.x86.R_AL, srcval);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x1d
+****************************************************************************/
+void x86emuOp_sbb_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("SBB\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("SBB\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = sbb_long(M.x86.R_EAX, srcval);
+    } else {
+	M.x86.R_AX = sbb_word(M.x86.R_AX, (u16)srcval);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x1e
+****************************************************************************/
+void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("PUSH\tDS\n");
+    TRACE_AND_STEP();
+    push_word(M.x86.R_DS);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x1f
+****************************************************************************/
+void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("POP\tDS\n");
+    TRACE_AND_STEP();
+    M.x86.R_DS = pop_word();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x20
+****************************************************************************/
+void x86emuOp_and_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint destoffset;
+    u8 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("AND\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = and_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = and_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = and_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = and_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x21
+****************************************************************************/
+void x86emuOp_and_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("AND\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = and_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = and_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = and_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = and_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = and_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = and_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x22
+****************************************************************************/
+void x86emuOp_and_byte_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint srcoffset;
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("AND\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = and_byte(*destreg, srcval);
+	break;
+    case 1:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = and_byte(*destreg, srcval);
+	break;
+    case 2:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = and_byte(*destreg, srcval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = and_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x23
+****************************************************************************/
+void x86emuOp_and_word_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("AND\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_word(*destreg, srcval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_long(*destreg, srcval);
+	    break;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_word(*destreg, srcval);
+	    break;
+	}
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_word(*destreg, srcval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = and_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x24
+****************************************************************************/
+void x86emuOp_and_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("AND\tAL,");
+    srcval = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    M.x86.R_AL = and_byte(M.x86.R_AL, srcval);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x25
+****************************************************************************/
+void x86emuOp_and_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("AND\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("AND\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = and_long(M.x86.R_EAX, srcval);
+    } else {
+	M.x86.R_AX = and_word(M.x86.R_AX, (u16)srcval);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x26
+****************************************************************************/
+void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("ES:\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_SEGOVR_ES;
+    /*
+     * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4
+     * opcode subroutines we do not want to do this.
+     */
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x27
+****************************************************************************/
+void x86emuOp_daa(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("DAA\n");
+    TRACE_AND_STEP();
+    M.x86.R_AL = daa_byte(M.x86.R_AL);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x28
+****************************************************************************/
+void x86emuOp_sub_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint destoffset;
+    u8 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SUB\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = sub_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = sub_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = sub_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sub_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x29
+****************************************************************************/
+void x86emuOp_sub_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SUB\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sub_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sub_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sub_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sub_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sub_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = sub_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x2a
+****************************************************************************/
+void x86emuOp_sub_byte_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint srcoffset;
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SUB\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sub_byte(*destreg, srcval);
+	break;
+    case 1:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sub_byte(*destreg, srcval);
+	break;
+    case 2:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sub_byte(*destreg, srcval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = sub_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x2b
+****************************************************************************/
+void x86emuOp_sub_word_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SUB\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_word(*destreg, srcval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_word(*destreg, srcval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_word(*destreg, srcval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = sub_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x2c
+****************************************************************************/
+void x86emuOp_sub_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SUB\tAL,");
+    srcval = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    M.x86.R_AL = sub_byte(M.x86.R_AL, srcval);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x2d
+****************************************************************************/
+void x86emuOp_sub_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("SUB\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("SUB\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = sub_long(M.x86.R_EAX, srcval);
+    } else {
+	M.x86.R_AX = sub_word(M.x86.R_AX, (u16)srcval);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x2e
+****************************************************************************/
+void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("CS:\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_SEGOVR_CS;
+    /* note no DECODE_CLEAR_SEGOVR here. */
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x2f
+****************************************************************************/
+void x86emuOp_das(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("DAS\n");
+    TRACE_AND_STEP();
+    M.x86.R_AL = das_byte(M.x86.R_AL);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x30
+****************************************************************************/
+void x86emuOp_xor_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint destoffset;
+    u8 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("XOR\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = xor_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = xor_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = xor_byte(destval, *srcreg);
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = xor_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x31
+****************************************************************************/
+void x86emuOp_xor_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("XOR\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = xor_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = xor_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = xor_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = xor_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = xor_long(destval, *srcreg);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = xor_word(destval, *srcreg);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x32
+****************************************************************************/
+void x86emuOp_xor_byte_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint srcoffset;
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("XOR\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = xor_byte(*destreg, srcval);
+	break;
+    case 1:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = xor_byte(*destreg, srcval);
+	break;
+    case 2:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = xor_byte(*destreg, srcval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = xor_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x33
+****************************************************************************/
+void x86emuOp_xor_word_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("XOR\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_word(*destreg, srcval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_word(*destreg, srcval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_word(*destreg, srcval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = xor_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x34
+****************************************************************************/
+void x86emuOp_xor_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("XOR\tAL,");
+    srcval = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    M.x86.R_AL = xor_byte(M.x86.R_AL, srcval);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x35
+****************************************************************************/
+void x86emuOp_xor_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("XOR\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("XOR\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = xor_long(M.x86.R_EAX, srcval);
+    } else {
+	M.x86.R_AX = xor_word(M.x86.R_AX, (u16)srcval);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x36
+****************************************************************************/
+void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("SS:\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_SEGOVR_SS;
+    /* no DECODE_CLEAR_SEGOVR ! */
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x37
+****************************************************************************/
+void x86emuOp_aaa(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("AAA\n");
+    TRACE_AND_STEP();
+    M.x86.R_AX = aaa_word(M.x86.R_AX);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x38
+****************************************************************************/
+void x86emuOp_cmp_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+    u8 *destreg, *srcreg;
+    u8 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("CMP\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	cmp_byte(destval, *srcreg);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	cmp_byte(destval, *srcreg);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	cmp_byte(destval, *srcreg);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	cmp_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x39
+****************************************************************************/
+void x86emuOp_cmp_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("CMP\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_long(destval, *srcreg);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_word(destval, *srcreg);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_long(destval, *srcreg);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_word(destval, *srcreg);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_long(destval, *srcreg);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_word(destval, *srcreg);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x3a
+****************************************************************************/
+void x86emuOp_cmp_byte_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint srcoffset;
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("CMP\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	cmp_byte(*destreg, srcval);
+	break;
+    case 1:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	cmp_byte(*destreg, srcval);
+	break;
+    case 2:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	cmp_byte(*destreg, srcval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	cmp_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x3b
+****************************************************************************/
+void x86emuOp_cmp_word_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("CMP\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_word(*destreg, srcval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_word(*destreg, srcval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_long(*destreg, srcval);
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_word(*destreg, srcval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    cmp_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x3c
+****************************************************************************/
+void x86emuOp_cmp_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("CMP\tAL,");
+    srcval = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    cmp_byte(M.x86.R_AL, srcval);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x3d
+****************************************************************************/
+void x86emuOp_cmp_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("CMP\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("CMP\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	cmp_long(M.x86.R_EAX, srcval);
+    } else {
+	cmp_word(M.x86.R_AX, (u16)srcval);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x3e
+****************************************************************************/
+void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("DS:\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_SEGOVR_DS;
+    /* NO DECODE_CLEAR_SEGOVR! */
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x3f
+****************************************************************************/
+void x86emuOp_aas(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("AAS\n");
+    TRACE_AND_STEP();
+    M.x86.R_AX = aas_word(M.x86.R_AX);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x40
+****************************************************************************/
+void x86emuOp_inc_AX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("INC\tEAX\n");
+    } else {
+	DECODE_PRINTF("INC\tAX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = inc_long(M.x86.R_EAX);
+    } else {
+	M.x86.R_AX = inc_word(M.x86.R_AX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x41
+****************************************************************************/
+void x86emuOp_inc_CX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("INC\tECX\n");
+    } else {
+	DECODE_PRINTF("INC\tCX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ECX = inc_long(M.x86.R_ECX);
+    } else {
+	M.x86.R_CX = inc_word(M.x86.R_CX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x42
+****************************************************************************/
+void x86emuOp_inc_DX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("INC\tEDX\n");
+    } else {
+	DECODE_PRINTF("INC\tDX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EDX = inc_long(M.x86.R_EDX);
+    } else {
+	M.x86.R_DX = inc_word(M.x86.R_DX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x43
+****************************************************************************/
+void x86emuOp_inc_BX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("INC\tEBX\n");
+    } else {
+	DECODE_PRINTF("INC\tBX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EBX = inc_long(M.x86.R_EBX);
+    } else {
+	M.x86.R_BX = inc_word(M.x86.R_BX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x44
+****************************************************************************/
+void x86emuOp_inc_SP(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("INC\tESP\n");
+    } else {
+	DECODE_PRINTF("INC\tSP\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ESP = inc_long(M.x86.R_ESP);
+    } else {
+	M.x86.R_SP = inc_word(M.x86.R_SP);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x45
+****************************************************************************/
+void x86emuOp_inc_BP(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("INC\tEBP\n");
+    } else {
+	DECODE_PRINTF("INC\tBP\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EBP = inc_long(M.x86.R_EBP);
+    } else {
+	M.x86.R_BP = inc_word(M.x86.R_BP);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x46
+****************************************************************************/
+void x86emuOp_inc_SI(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("INC\tESI\n");
+    } else {
+	DECODE_PRINTF("INC\tSI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ESI = inc_long(M.x86.R_ESI);
+    } else {
+	M.x86.R_SI = inc_word(M.x86.R_SI);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x47
+****************************************************************************/
+void x86emuOp_inc_DI(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("INC\tEDI\n");
+    } else {
+	DECODE_PRINTF("INC\tDI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EDI = inc_long(M.x86.R_EDI);
+    } else {
+	M.x86.R_DI = inc_word(M.x86.R_DI);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x48
+****************************************************************************/
+void x86emuOp_dec_AX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("DEC\tEAX\n");
+    } else {
+	DECODE_PRINTF("DEC\tAX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = dec_long(M.x86.R_EAX);
+    } else {
+	M.x86.R_AX = dec_word(M.x86.R_AX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x49
+****************************************************************************/
+void x86emuOp_dec_CX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("DEC\tECX\n");
+    } else {
+	DECODE_PRINTF("DEC\tCX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ECX = dec_long(M.x86.R_ECX);
+    } else {
+	M.x86.R_CX = dec_word(M.x86.R_CX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x4a
+****************************************************************************/
+void x86emuOp_dec_DX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("DEC\tEDX\n");
+    } else {
+	DECODE_PRINTF("DEC\tDX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EDX = dec_long(M.x86.R_EDX);
+    } else {
+	M.x86.R_DX = dec_word(M.x86.R_DX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x4b
+****************************************************************************/
+void x86emuOp_dec_BX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("DEC\tEBX\n");
+    } else {
+	DECODE_PRINTF("DEC\tBX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EBX = dec_long(M.x86.R_EBX);
+    } else {
+	M.x86.R_BX = dec_word(M.x86.R_BX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x4c
+****************************************************************************/
+void x86emuOp_dec_SP(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("DEC\tESP\n");
+    } else {
+	DECODE_PRINTF("DEC\tSP\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ESP = dec_long(M.x86.R_ESP);
+    } else {
+	M.x86.R_SP = dec_word(M.x86.R_SP);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x4d
+****************************************************************************/
+void x86emuOp_dec_BP(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("DEC\tEBP\n");
+    } else {
+	DECODE_PRINTF("DEC\tBP\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EBP = dec_long(M.x86.R_EBP);
+    } else {
+	M.x86.R_BP = dec_word(M.x86.R_BP);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x4e
+****************************************************************************/
+void x86emuOp_dec_SI(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("DEC\tESI\n");
+    } else {
+	DECODE_PRINTF("DEC\tSI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ESI = dec_long(M.x86.R_ESI);
+    } else {
+	M.x86.R_SI = dec_word(M.x86.R_SI);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x4f
+****************************************************************************/
+void x86emuOp_dec_DI(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("DEC\tEDI\n");
+    } else {
+	DECODE_PRINTF("DEC\tDI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EDI = dec_long(M.x86.R_EDI);
+    } else {
+	M.x86.R_DI = dec_word(M.x86.R_DI);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x50
+****************************************************************************/
+void x86emuOp_push_AX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSH\tEAX\n");
+    } else {
+	DECODE_PRINTF("PUSH\tAX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	push_long(M.x86.R_EAX);
+    } else {
+	push_word(M.x86.R_AX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x51
+****************************************************************************/
+void x86emuOp_push_CX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSH\tECX\n");
+    } else {
+	DECODE_PRINTF("PUSH\tCX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	push_long(M.x86.R_ECX);
+    } else {
+	push_word(M.x86.R_CX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x52
+****************************************************************************/
+void x86emuOp_push_DX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSH\tEDX\n");
+    } else {
+	DECODE_PRINTF("PUSH\tDX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	push_long(M.x86.R_EDX);
+    } else {
+	push_word(M.x86.R_DX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x53
+****************************************************************************/
+void x86emuOp_push_BX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSH\tEBX\n");
+    } else {
+	DECODE_PRINTF("PUSH\tBX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	push_long(M.x86.R_EBX);
+    } else {
+	push_word(M.x86.R_BX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x54
+****************************************************************************/
+void x86emuOp_push_SP(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSH\tESP\n");
+    } else {
+	DECODE_PRINTF("PUSH\tSP\n");
+    }
+    TRACE_AND_STEP();
+	/* Always push (E)SP, since we are emulating an i386 and above
+	 * processor. This is necessary as some BIOS'es use this to check
+	 * what type of processor is in the system.
+	 */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		push_long(M.x86.R_ESP);
+	} else {
+		push_word((u16)(M.x86.R_SP));
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x55
+****************************************************************************/
+void x86emuOp_push_BP(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSH\tEBP\n");
+    } else {
+	DECODE_PRINTF("PUSH\tBP\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	push_long(M.x86.R_EBP);
+    } else {
+	push_word(M.x86.R_BP);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x56
+****************************************************************************/
+void x86emuOp_push_SI(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSH\tESI\n");
+    } else {
+	DECODE_PRINTF("PUSH\tSI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	push_long(M.x86.R_ESI);
+    } else {
+	push_word(M.x86.R_SI);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x57
+****************************************************************************/
+void x86emuOp_push_DI(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSH\tEDI\n");
+    } else {
+	DECODE_PRINTF("PUSH\tDI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	push_long(M.x86.R_EDI);
+    } else {
+	push_word(M.x86.R_DI);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x58
+****************************************************************************/
+void x86emuOp_pop_AX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POP\tEAX\n");
+    } else {
+	DECODE_PRINTF("POP\tAX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = pop_long();
+    } else {
+	M.x86.R_AX = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x59
+****************************************************************************/
+void x86emuOp_pop_CX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POP\tECX\n");
+    } else {
+	DECODE_PRINTF("POP\tCX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ECX = pop_long();
+    } else {
+	M.x86.R_CX = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x5a
+****************************************************************************/
+void x86emuOp_pop_DX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POP\tEDX\n");
+    } else {
+	DECODE_PRINTF("POP\tDX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EDX = pop_long();
+    } else {
+	M.x86.R_DX = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x5b
+****************************************************************************/
+void x86emuOp_pop_BX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POP\tEBX\n");
+    } else {
+	DECODE_PRINTF("POP\tBX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EBX = pop_long();
+    } else {
+	M.x86.R_BX = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x5c
+****************************************************************************/
+void x86emuOp_pop_SP(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POP\tESP\n");
+    } else {
+	DECODE_PRINTF("POP\tSP\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ESP = pop_long();
+    } else {
+	M.x86.R_SP = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x5d
+****************************************************************************/
+void x86emuOp_pop_BP(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POP\tEBP\n");
+    } else {
+	DECODE_PRINTF("POP\tBP\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EBP = pop_long();
+    } else {
+	M.x86.R_BP = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x5e
+****************************************************************************/
+void x86emuOp_pop_SI(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POP\tESI\n");
+    } else {
+	DECODE_PRINTF("POP\tSI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ESI = pop_long();
+    } else {
+	M.x86.R_SI = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x5f
+****************************************************************************/
+void x86emuOp_pop_DI(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POP\tEDI\n");
+    } else {
+	DECODE_PRINTF("POP\tDI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EDI = pop_long();
+    } else {
+	M.x86.R_DI = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x60
+****************************************************************************/
+void x86emuOp_push_all(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSHAD\n");
+    } else {
+	DECODE_PRINTF("PUSHA\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	u32 old_sp = M.x86.R_ESP;
+
+	push_long(M.x86.R_EAX);
+	push_long(M.x86.R_ECX);
+	push_long(M.x86.R_EDX);
+	push_long(M.x86.R_EBX);
+	push_long(old_sp);
+	push_long(M.x86.R_EBP);
+	push_long(M.x86.R_ESI);
+	push_long(M.x86.R_EDI);
+    } else {
+	u16 old_sp = M.x86.R_SP;
+
+	push_word(M.x86.R_AX);
+	push_word(M.x86.R_CX);
+	push_word(M.x86.R_DX);
+	push_word(M.x86.R_BX);
+	push_word(old_sp);
+	push_word(M.x86.R_BP);
+	push_word(M.x86.R_SI);
+	push_word(M.x86.R_DI);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x61
+****************************************************************************/
+void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POPAD\n");
+    } else {
+	DECODE_PRINTF("POPA\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EDI = pop_long();
+	M.x86.R_ESI = pop_long();
+	M.x86.R_EBP = pop_long();
+	M.x86.R_ESP += 4;              /* skip ESP */
+	M.x86.R_EBX = pop_long();
+	M.x86.R_EDX = pop_long();
+	M.x86.R_ECX = pop_long();
+	M.x86.R_EAX = pop_long();
+    } else {
+	M.x86.R_DI = pop_word();
+	M.x86.R_SI = pop_word();
+	M.x86.R_BP = pop_word();
+	M.x86.R_SP += 2;               /* skip SP */
+	M.x86.R_BX = pop_word();
+	M.x86.R_DX = pop_word();
+	M.x86.R_CX = pop_word();
+	M.x86.R_AX = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/*opcode 0x62   ILLEGAL OP, calls x86emuOp_illegal_op() */
+/*opcode 0x63   ILLEGAL OP, calls x86emuOp_illegal_op() */
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x64
+****************************************************************************/
+void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("FS:\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_SEGOVR_FS;
+    /*
+     * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4
+     * opcode subroutines we do not want to do this.
+     */
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x65
+****************************************************************************/
+void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("GS:\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_SEGOVR_GS;
+    /*
+     * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4
+     * opcode subroutines we do not want to do this.
+     */
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x66 - prefix for 32-bit register
+****************************************************************************/
+void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("DATA:\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_PREFIX_DATA;
+    /* note no DECODE_CLEAR_SEGOVR here. */
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x67 - prefix for 32-bit address
+****************************************************************************/
+void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("ADDR:\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_PREFIX_ADDR;
+    /* note no DECODE_CLEAR_SEGOVR here. */
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x68
+****************************************************************************/
+void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 imm;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	imm = fetch_long_imm();
+    } else {
+	imm = fetch_word_imm();
+    }
+    DECODE_PRINTF2("PUSH\t%x\n", imm);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	push_long(imm);
+    } else {
+	push_word((u16)imm);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x69
+****************************************************************************/
+void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("IMUL\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+	    u32 res_lo,res_hi;
+	    s32 imm;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+	    u32 res;
+	    s16 imm;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    res = (s16)srcval * (s16)imm;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+	    u32 res_lo,res_hi;
+	    s32 imm;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+	    u32 res;
+	    s16 imm;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    res = (s16)srcval * (s16)imm;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+	    u32 res_lo,res_hi;
+	    s32 imm;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+	    u32 res;
+	    s16 imm;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    res = (s16)srcval * (s16)imm;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+	    u32 res_lo,res_hi;
+	    s32 imm;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg,*srcreg;
+	    u32 res;
+	    s16 imm;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    res = (s16)*srcreg * (s16)imm;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x6a
+****************************************************************************/
+void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1))
+{
+    s16 imm;
+
+    START_OF_INSTR();
+    imm = (s8)fetch_byte_imm();
+    DECODE_PRINTF2("PUSH\t%d\n", imm);
+    TRACE_AND_STEP();
+    push_word(imm);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x6b
+****************************************************************************/
+void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+    s8  imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("IMUL\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+	    u32 res_lo,res_hi;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    imm = fetch_byte_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+	    u32 res;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    imm = fetch_byte_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    res = (s16)srcval * (s16)imm;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+	    u32 res_lo,res_hi;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    imm = fetch_byte_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+	    u32 res;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    imm = fetch_byte_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    res = (s16)srcval * (s16)imm;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+	    u32 res_lo,res_hi;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    imm = fetch_byte_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+	    u32 res;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    imm = fetch_byte_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    res = (s16)srcval * (s16)imm;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+	    u32 res_lo,res_hi;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    imm = fetch_byte_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg,*srcreg;
+	    u32 res;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    imm = fetch_byte_imm();
+	    DECODE_PRINTF2(",%d\n", (s32)imm);
+	    res = (s16)*srcreg * (s16)imm;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x6c
+****************************************************************************/
+void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("INSB\n");
+    ins(1);
+    TRACE_AND_STEP();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x6d
+****************************************************************************/
+void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("INSD\n");
+	ins(4);
+    } else {
+	DECODE_PRINTF("INSW\n");
+	ins(2);
+    }
+    TRACE_AND_STEP();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x6e
+****************************************************************************/
+void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("OUTSB\n");
+    outs(1);
+    TRACE_AND_STEP();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x6f
+****************************************************************************/
+void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("OUTSD\n");
+	outs(4);
+    } else {
+	DECODE_PRINTF("OUTSW\n");
+	outs(2);
+    }
+    TRACE_AND_STEP();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x70
+****************************************************************************/
+void x86emuOp_jump_near_O(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if overflow flag is set */
+    START_OF_INSTR();
+    DECODE_PRINTF("JO\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_OF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x71
+****************************************************************************/
+void x86emuOp_jump_near_NO(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if overflow is not set */
+    START_OF_INSTR();
+    DECODE_PRINTF("JNO\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (!ACCESS_FLAG(F_OF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x72
+****************************************************************************/
+void x86emuOp_jump_near_B(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if carry flag is set. */
+    START_OF_INSTR();
+    DECODE_PRINTF("JB\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_CF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x73
+****************************************************************************/
+void x86emuOp_jump_near_NB(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if carry flag is clear. */
+    START_OF_INSTR();
+    DECODE_PRINTF("JNB\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (!ACCESS_FLAG(F_CF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x74
+****************************************************************************/
+void x86emuOp_jump_near_Z(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if zero flag is set. */
+    START_OF_INSTR();
+    DECODE_PRINTF("JZ\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_ZF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x75
+****************************************************************************/
+void x86emuOp_jump_near_NZ(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if zero flag is clear. */
+    START_OF_INSTR();
+    DECODE_PRINTF("JNZ\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (!ACCESS_FLAG(F_ZF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x76
+****************************************************************************/
+void x86emuOp_jump_near_BE(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if carry flag is set or if the zero
+       flag is set. */
+    START_OF_INSTR();
+    DECODE_PRINTF("JBE\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x77
+****************************************************************************/
+void x86emuOp_jump_near_NBE(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if carry flag is clear and if the zero
+       flag is clear */
+    START_OF_INSTR();
+    DECODE_PRINTF("JNBE\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (!(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x78
+****************************************************************************/
+void x86emuOp_jump_near_S(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if sign flag is set */
+    START_OF_INSTR();
+    DECODE_PRINTF("JS\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_SF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x79
+****************************************************************************/
+void x86emuOp_jump_near_NS(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if sign flag is clear */
+    START_OF_INSTR();
+    DECODE_PRINTF("JNS\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (!ACCESS_FLAG(F_SF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x7a
+****************************************************************************/
+void x86emuOp_jump_near_P(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if parity flag is set (even parity) */
+    START_OF_INSTR();
+    DECODE_PRINTF("JP\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_PF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x7b
+****************************************************************************/
+void x86emuOp_jump_near_NP(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+
+    /* jump to byte offset if parity flag is clear (odd parity) */
+    START_OF_INSTR();
+    DECODE_PRINTF("JNP\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (!ACCESS_FLAG(F_PF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x7c
+****************************************************************************/
+void x86emuOp_jump_near_L(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+    int sf, of;
+
+    /* jump to byte offset if sign flag not equal to overflow flag. */
+    START_OF_INSTR();
+    DECODE_PRINTF("JL\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    sf = ACCESS_FLAG(F_SF) != 0;
+    of = ACCESS_FLAG(F_OF) != 0;
+    if (sf ^ of)
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x7d
+****************************************************************************/
+void x86emuOp_jump_near_NL(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+    int sf, of;
+
+    /* jump to byte offset if sign flag not equal to overflow flag. */
+    START_OF_INSTR();
+    DECODE_PRINTF("JNL\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    sf = ACCESS_FLAG(F_SF) != 0;
+    of = ACCESS_FLAG(F_OF) != 0;
+    /* note: inverse of above, but using == instead of xor. */
+    if (sf == of)
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x7e
+****************************************************************************/
+void x86emuOp_jump_near_LE(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+    int sf, of;
+
+    /* jump to byte offset if sign flag not equal to overflow flag
+       or the zero flag is set */
+    START_OF_INSTR();
+    DECODE_PRINTF("JLE\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    sf = ACCESS_FLAG(F_SF) != 0;
+    of = ACCESS_FLAG(F_OF) != 0;
+    if ((sf ^ of) || ACCESS_FLAG(F_ZF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x7f
+****************************************************************************/
+void x86emuOp_jump_near_NLE(u8 X86EMU_UNUSED(op1))
+{
+    s8 offset;
+    u16 target;
+    int sf, of;
+
+    /* jump to byte offset if sign flag equal to overflow flag.
+       and the zero flag is clear */
+    START_OF_INSTR();
+    DECODE_PRINTF("JNLE\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + (s16)offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    sf = ACCESS_FLAG(F_SF) != 0;
+    of = ACCESS_FLAG(F_OF) != 0;
+    if ((sf == of) && !ACCESS_FLAG(F_ZF))
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+static u8 (*opc80_byte_operation[])(u8 d, u8 s) =
+{
+    add_byte,           /* 00 */
+    or_byte,            /* 01 */
+    adc_byte,           /* 02 */
+    sbb_byte,           /* 03 */
+    and_byte,           /* 04 */
+    sub_byte,           /* 05 */
+    xor_byte,           /* 06 */
+    cmp_byte,           /* 07 */
+};
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x80
+****************************************************************************/
+void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg;
+    uint destoffset;
+    u8 imm;
+    u8 destval;
+
+    /*
+     * Weirdo special case instruction format.  Part of the opcode
+     * held below in "RH".  Doubly nested case would result, except
+     * that the decoded instruction
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ADD\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("OR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("ADC\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("SBB\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("AND\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SUB\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("XOR\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("CMP\t");
+	    break;
+	}
+    }
+#endif
+    /* know operation, decode the mod byte to find the addressing
+       mode. */
+    switch (mod) {
+    case 0:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2("%x\n", imm);
+	TRACE_AND_STEP();
+	destval = (*opc80_byte_operation[rh]) (destval, imm);
+	if (rh != 7)
+	    store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2("%x\n", imm);
+	TRACE_AND_STEP();
+	destval = (*opc80_byte_operation[rh]) (destval, imm);
+	if (rh != 7)
+	    store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2("%x\n", imm);
+	TRACE_AND_STEP();
+	destval = (*opc80_byte_operation[rh]) (destval, imm);
+	if (rh != 7)
+	    store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2("%x\n", imm);
+	TRACE_AND_STEP();
+	destval = (*opc80_byte_operation[rh]) (*destreg, imm);
+	if (rh != 7)
+	    *destreg = destval;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+static u16 (*opc81_word_operation[])(u16 d, u16 s) =
+{
+    add_word,           /*00 */
+    or_word,            /*01 */
+    adc_word,           /*02 */
+    sbb_word,           /*03 */
+    and_word,           /*04 */
+    sub_word,           /*05 */
+    xor_word,           /*06 */
+    cmp_word,           /*07 */
+};
+
+static u32 (*opc81_long_operation[])(u32 d, u32 s) =
+{
+    add_long,           /*00 */
+    or_long,            /*01 */
+    adc_long,           /*02 */
+    sbb_long,           /*03 */
+    and_long,           /*04 */
+    sub_long,           /*05 */
+    xor_long,           /*06 */
+    cmp_long,           /*07 */
+};
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x81
+****************************************************************************/
+void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    /*
+     * Weirdo special case instruction format.  Part of the opcode
+     * held below in "RH".  Doubly nested case would result, except
+     * that the decoded instruction
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ADD\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("OR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("ADC\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("SBB\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("AND\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SUB\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("XOR\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("CMP\t");
+	    break;
+	}
+    }
+#endif
+    /*
+     * Know operation, decode the mod byte to find the addressing
+     * mode.
+     */
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval,imm;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2("%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc81_long_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_long(destoffset, destval);
+	} else {
+	    u16 destval,imm;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2("%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc81_word_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval,imm;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2("%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc81_long_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_long(destoffset, destval);
+	} else {
+	    u16 destval,imm;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2("%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc81_word_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval,imm;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2("%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc81_long_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_long(destoffset, destval);
+	} else {
+	    u16 destval,imm;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2("%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc81_word_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 destval,imm;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2("%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc81_long_operation[rh]) (*destreg, imm);
+	    if (rh != 7)
+		*destreg = destval;
+	} else {
+	    u16 *destreg;
+	    u16 destval,imm;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2("%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc81_word_operation[rh]) (*destreg, imm);
+	    if (rh != 7)
+		*destreg = destval;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+static u8 (*opc82_byte_operation[])(u8 s, u8 d) =
+{
+    add_byte,           /*00 */
+    or_byte,            /*01 */ /*YYY UNUSED ???? */
+    adc_byte,           /*02 */
+    sbb_byte,           /*03 */
+    and_byte,           /*04 */ /*YYY UNUSED ???? */
+    sub_byte,           /*05 */
+    xor_byte,           /*06 */ /*YYY UNUSED ???? */
+    cmp_byte,           /*07 */
+};
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x82
+****************************************************************************/
+void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg;
+    uint destoffset;
+    u8 imm;
+    u8 destval;
+
+    /*
+     * Weirdo special case instruction format.  Part of the opcode
+     * held below in "RH".  Doubly nested case would result, except
+     * that the decoded instruction Similar to opcode 81, except that
+     * the immediate byte is sign extended to a word length.
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ADD\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("OR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("ADC\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("SBB\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("AND\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SUB\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("XOR\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("CMP\t");
+	    break;
+	}
+    }
+#endif
+    /* know operation, decode the mod byte to find the addressing
+       mode. */
+    switch (mod) {
+    case 0:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm00_address(rl);
+	destval = fetch_data_byte(destoffset);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2(",%x\n", imm);
+	TRACE_AND_STEP();
+	destval = (*opc82_byte_operation[rh]) (destval, imm);
+	if (rh != 7)
+	    store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm01_address(rl);
+	destval = fetch_data_byte(destoffset);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2(",%x\n", imm);
+	TRACE_AND_STEP();
+	destval = (*opc82_byte_operation[rh]) (destval, imm);
+	if (rh != 7)
+	    store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm10_address(rl);
+	destval = fetch_data_byte(destoffset);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2(",%x\n", imm);
+	TRACE_AND_STEP();
+	destval = (*opc82_byte_operation[rh]) (destval, imm);
+	if (rh != 7)
+	    store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2(",%x\n", imm);
+	TRACE_AND_STEP();
+	destval = (*opc82_byte_operation[rh]) (*destreg, imm);
+	if (rh != 7)
+	    *destreg = destval;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+static u16 (*opc83_word_operation[])(u16 s, u16 d) =
+{
+    add_word,           /*00 */
+    or_word,            /*01 */ /*YYY UNUSED ???? */
+    adc_word,           /*02 */
+    sbb_word,           /*03 */
+    and_word,           /*04 */ /*YYY UNUSED ???? */
+    sub_word,           /*05 */
+    xor_word,           /*06 */ /*YYY UNUSED ???? */
+    cmp_word,           /*07 */
+};
+
+static u32 (*opc83_long_operation[])(u32 s, u32 d) =
+{
+    add_long,           /*00 */
+    or_long,            /*01 */ /*YYY UNUSED ???? */
+    adc_long,           /*02 */
+    sbb_long,           /*03 */
+    and_long,           /*04 */ /*YYY UNUSED ???? */
+    sub_long,           /*05 */
+    xor_long,           /*06 */ /*YYY UNUSED ???? */
+    cmp_long,           /*07 */
+};
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x83
+****************************************************************************/
+void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    /*
+     * Weirdo special case instruction format.  Part of the opcode
+     * held below in "RH".  Doubly nested case would result, except
+     * that the decoded instruction Similar to opcode 81, except that
+     * the immediate byte is sign extended to a word length.
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+       switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ADD\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("OR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("ADC\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("SBB\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("AND\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SUB\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("XOR\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("CMP\t");
+	    break;
+	}
+    }
+#endif
+    /* know operation, decode the mod byte to find the addressing
+       mode. */
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval,imm;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    destval = fetch_data_long(destoffset);
+	    imm = (s8) fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc83_long_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_long(destoffset, destval);
+	} else {
+	    u16 destval,imm;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    destval = fetch_data_word(destoffset);
+	    imm = (s8) fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc83_word_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval,imm;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    destval = fetch_data_long(destoffset);
+	    imm = (s8) fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc83_long_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_long(destoffset, destval);
+	} else {
+	    u16 destval,imm;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    destval = fetch_data_word(destoffset);
+	    imm = (s8) fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc83_word_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval,imm;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    destval = fetch_data_long(destoffset);
+	    imm = (s8) fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc83_long_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_long(destoffset, destval);
+	} else {
+	    u16 destval,imm;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    destval = fetch_data_word(destoffset);
+	    imm = (s8) fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc83_word_operation[rh]) (destval, imm);
+	    if (rh != 7)
+		store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 destval,imm;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    imm = (s8) fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc83_long_operation[rh]) (*destreg, imm);
+	    if (rh != 7)
+		*destreg = destval;
+	} else {
+	    u16 *destreg;
+	    u16 destval,imm;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    imm = (s8) fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    destval = (*opc83_word_operation[rh]) (*destreg, imm);
+	    if (rh != 7)
+		*destreg = destval;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x84
+****************************************************************************/
+void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint destoffset;
+    u8 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("TEST\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	test_byte(destval, *srcreg);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	test_byte(destval, *srcreg);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	test_byte(destval, *srcreg);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	test_byte(*destreg, *srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x85
+****************************************************************************/
+void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("TEST\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    test_long(destval, *srcreg);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    test_word(destval, *srcreg);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    test_long(destval, *srcreg);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    test_word(destval, *srcreg);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    test_long(destval, *srcreg);
+	} else {
+	    u16 destval;
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    test_word(destval, *srcreg);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    test_long(*destreg, *srcreg);
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    test_word(*destreg, *srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x86
+****************************************************************************/
+void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint destoffset;
+    u8 destval;
+    u8 tmp;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("XCHG\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	tmp = *srcreg;
+	*srcreg = destval;
+	destval = tmp;
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	tmp = *srcreg;
+	*srcreg = destval;
+	destval = tmp;
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	destval = fetch_data_byte(destoffset);
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	tmp = *srcreg;
+	*srcreg = destval;
+	destval = tmp;
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	tmp = *srcreg;
+	*srcreg = *destreg;
+	*destreg = tmp;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x87
+****************************************************************************/
+void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("XCHG\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg;
+	    u32 destval,tmp;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    tmp = *srcreg;
+	    *srcreg = destval;
+	    destval = tmp;
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 *srcreg;
+	    u16 destval,tmp;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    tmp = *srcreg;
+	    *srcreg = destval;
+	    destval = tmp;
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg;
+	    u32 destval,tmp;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    tmp = *srcreg;
+	    *srcreg = destval;
+	    destval = tmp;
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 *srcreg;
+	    u16 destval,tmp;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    tmp = *srcreg;
+	    *srcreg = destval;
+	    destval = tmp;
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg;
+	    u32 destval,tmp;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_long(destoffset);
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    tmp = *srcreg;
+	    *srcreg = destval;
+	    destval = tmp;
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 *srcreg;
+	    u16 destval,tmp;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    destval = fetch_data_word(destoffset);
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    tmp = *srcreg;
+	    *srcreg = destval;
+	    destval = tmp;
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+	    u32 tmp;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    tmp = *srcreg;
+	    *srcreg = *destreg;
+	    *destreg = tmp;
+	} else {
+	    u16 *destreg,*srcreg;
+	    u16 tmp;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    tmp = *srcreg;
+	    *srcreg = *destreg;
+	    *destreg = tmp;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x88
+****************************************************************************/
+void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	store_data_byte(destoffset, *srcreg);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	store_data_byte(destoffset, *srcreg);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	store_data_byte(destoffset, *srcreg);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = *srcreg;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x89
+****************************************************************************/
+void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    store_data_long(destoffset, *srcreg);
+	} else {
+	    u16 *srcreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    store_data_word(destoffset, *srcreg);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    store_data_long(destoffset, *srcreg);
+	} else {
+	    u16 *srcreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    store_data_word(destoffset, *srcreg);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    store_data_long(destoffset, *srcreg);
+	} else {
+	    u16 *srcreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    store_data_word(destoffset, *srcreg);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = *srcreg;
+	} else {
+	    u16 *destreg,*srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = *srcreg;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x8a
+****************************************************************************/
+void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg, *srcreg;
+    uint srcoffset;
+    u8 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 1:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 2:
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_byte(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = *srcreg;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x8b
+****************************************************************************/
+void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg, *srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = *srcreg;
+	} else {
+	    u16 *destreg, *srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = *srcreg;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x8c
+****************************************************************************/
+void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u16 *destreg, *srcreg;
+    uint destoffset;
+    u16 destval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",");
+	srcreg = decode_rm_seg_register(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = *srcreg;
+	store_data_word(destoffset, destval);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",");
+	srcreg = decode_rm_seg_register(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = *srcreg;
+	store_data_word(destoffset, destval);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",");
+	srcreg = decode_rm_seg_register(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	destval = *srcreg;
+	store_data_word(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_WORD_REGISTER(rl);
+	DECODE_PRINTF(",");
+	srcreg = decode_rm_seg_register(rh);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = *srcreg;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x8d
+****************************************************************************/
+void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u16 *srcreg;
+    uint destoffset;
+
+/*
+ * TODO: Need to handle address size prefix!
+ *
+ * lea  eax,[eax+ebx*2] ??
+ */
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LEA\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	srcreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*srcreg = (u16)destoffset;
+	break;
+    case 1:
+	srcreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*srcreg = (u16)destoffset;
+	break;
+    case 2:
+	srcreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*srcreg = (u16)destoffset;
+	break;
+    case 3:                     /* register to register */
+	/* undefined.  Do nothing. */
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x8e
+****************************************************************************/
+void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u16 *destreg, *srcreg;
+    uint srcoffset;
+    u16 srcval;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = decode_rm_seg_register(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_word(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 1:
+	destreg = decode_rm_seg_register(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_word(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 2:
+	destreg = decode_rm_seg_register(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_word(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 3:                     /* register to register */
+	destreg = decode_rm_seg_register(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_WORD_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = *srcreg;
+	break;
+    }
+    /*
+     * Clean up, and reset all the R_xSP pointers to the correct
+     * locations.  This is about 3x too much overhead (doing all the
+     * segreg ptrs when only one is needed, but this instruction
+     * *cannot* be that common, and this isn't too much work anyway.
+     */
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x8f
+****************************************************************************/
+void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("POP\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    if (rh != 0) {
+	DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+	HALT_SYS();
+    }
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = pop_long();
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = pop_word();
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = pop_long();
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = pop_word();
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = pop_long();
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    destval = pop_word();
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = pop_long();
+	} else {
+	    u16 *destreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = pop_word();
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x90
+****************************************************************************/
+void x86emuOp_nop(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("NOP\n");
+    TRACE_AND_STEP();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x91
+****************************************************************************/
+void x86emuOp_xchg_word_AX_CX(u8 X86EMU_UNUSED(op1))
+{
+    u32 tmp;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("XCHG\tEAX,ECX\n");
+    } else {
+	DECODE_PRINTF("XCHG\tAX,CX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	tmp = M.x86.R_EAX;
+	M.x86.R_EAX = M.x86.R_ECX;
+	M.x86.R_ECX = tmp;
+    } else {
+	tmp = M.x86.R_AX;
+	M.x86.R_AX = M.x86.R_CX;
+	M.x86.R_CX = (u16)tmp;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x92
+****************************************************************************/
+void x86emuOp_xchg_word_AX_DX(u8 X86EMU_UNUSED(op1))
+{
+    u32 tmp;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("XCHG\tEAX,EDX\n");
+    } else {
+	DECODE_PRINTF("XCHG\tAX,DX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	tmp = M.x86.R_EAX;
+	M.x86.R_EAX = M.x86.R_EDX;
+	M.x86.R_EDX = tmp;
+    } else {
+	tmp = M.x86.R_AX;
+	M.x86.R_AX = M.x86.R_DX;
+	M.x86.R_DX = (u16)tmp;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x93
+****************************************************************************/
+void x86emuOp_xchg_word_AX_BX(u8 X86EMU_UNUSED(op1))
+{
+    u32 tmp;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("XCHG\tEAX,EBX\n");
+    } else {
+	DECODE_PRINTF("XCHG\tAX,BX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	tmp = M.x86.R_EAX;
+	M.x86.R_EAX = M.x86.R_EBX;
+	M.x86.R_EBX = tmp;
+    } else {
+	tmp = M.x86.R_AX;
+	M.x86.R_AX = M.x86.R_BX;
+	M.x86.R_BX = (u16)tmp;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x94
+****************************************************************************/
+void x86emuOp_xchg_word_AX_SP(u8 X86EMU_UNUSED(op1))
+{
+    u32 tmp;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("XCHG\tEAX,ESP\n");
+    } else {
+	DECODE_PRINTF("XCHG\tAX,SP\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	tmp = M.x86.R_EAX;
+	M.x86.R_EAX = M.x86.R_ESP;
+	M.x86.R_ESP = tmp;
+    } else {
+	tmp = M.x86.R_AX;
+	M.x86.R_AX = M.x86.R_SP;
+	M.x86.R_SP = (u16)tmp;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x95
+****************************************************************************/
+void x86emuOp_xchg_word_AX_BP(u8 X86EMU_UNUSED(op1))
+{
+    u32 tmp;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("XCHG\tEAX,EBP\n");
+    } else {
+	DECODE_PRINTF("XCHG\tAX,BP\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	tmp = M.x86.R_EAX;
+	M.x86.R_EAX = M.x86.R_EBP;
+	M.x86.R_EBP = tmp;
+    } else {
+	tmp = M.x86.R_AX;
+	M.x86.R_AX = M.x86.R_BP;
+	M.x86.R_BP = (u16)tmp;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x96
+****************************************************************************/
+void x86emuOp_xchg_word_AX_SI(u8 X86EMU_UNUSED(op1))
+{
+    u32 tmp;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("XCHG\tEAX,ESI\n");
+    } else {
+	DECODE_PRINTF("XCHG\tAX,SI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	tmp = M.x86.R_EAX;
+	M.x86.R_EAX = M.x86.R_ESI;
+	M.x86.R_ESI = tmp;
+    } else {
+	tmp = M.x86.R_AX;
+	M.x86.R_AX = M.x86.R_SI;
+	M.x86.R_SI = (u16)tmp;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x97
+****************************************************************************/
+void x86emuOp_xchg_word_AX_DI(u8 X86EMU_UNUSED(op1))
+{
+    u32 tmp;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("XCHG\tEAX,EDI\n");
+    } else {
+	DECODE_PRINTF("XCHG\tAX,DI\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	tmp = M.x86.R_EAX;
+	M.x86.R_EAX = M.x86.R_EDI;
+	M.x86.R_EDI = tmp;
+    } else {
+	tmp = M.x86.R_AX;
+	M.x86.R_AX = M.x86.R_DI;
+	M.x86.R_DI = (u16)tmp;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x98
+****************************************************************************/
+void x86emuOp_cbw(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("CWDE\n");
+    } else {
+	DECODE_PRINTF("CBW\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	if (M.x86.R_AX & 0x8000) {
+	    M.x86.R_EAX |= 0xffff0000;
+	} else {
+	    M.x86.R_EAX &= 0x0000ffff;
+	}
+    } else {
+	if (M.x86.R_AL & 0x80) {
+	    M.x86.R_AH = 0xff;
+	} else {
+	    M.x86.R_AH = 0x0;
+	}
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x99
+****************************************************************************/
+void x86emuOp_cwd(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("CDQ\n");
+    } else {
+	DECODE_PRINTF("CWD\n");
+    }
+    DECODE_PRINTF("CWD\n");
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	if (M.x86.R_EAX & 0x80000000) {
+	    M.x86.R_EDX = 0xffffffff;
+	} else {
+	    M.x86.R_EDX = 0x0;
+	}
+    } else {
+	if (M.x86.R_AX & 0x8000) {
+	    M.x86.R_DX = 0xffff;
+	} else {
+	    M.x86.R_DX = 0x0;
+	}
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x9a
+****************************************************************************/
+void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 farseg, faroff;
+
+    START_OF_INSTR();
+	DECODE_PRINTF("CALL\t");
+	faroff = fetch_word_imm();
+	farseg = fetch_word_imm();
+	DECODE_PRINTF2("%04x:", farseg);
+	DECODE_PRINTF2("%04x\n", faroff);
+	CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR ");
+
+    /* XXX
+     *
+     * Hooked interrupt vectors calling into our "BIOS" will cause
+     * problems unless all intersegment stuff is checked for BIOS
+     * access.  Check needed here.  For moment, let it alone.
+     */
+    TRACE_AND_STEP();
+    push_word(M.x86.R_CS);
+    M.x86.R_CS = farseg;
+    push_word(M.x86.R_IP);
+    M.x86.R_IP = faroff;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x9b
+****************************************************************************/
+void x86emuOp_wait(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("WAIT");
+    TRACE_AND_STEP();
+    /* NADA.  */
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x9c
+****************************************************************************/
+void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1))
+{
+    u32 flags;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("PUSHFD\n");
+    } else {
+	DECODE_PRINTF("PUSHF\n");
+    }
+    TRACE_AND_STEP();
+
+    /* clear out *all* bits not representing flags, and turn on real bits */
+    flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON;
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	push_long(flags);
+    } else {
+	push_word((u16)flags);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x9d
+****************************************************************************/
+void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("POPFD\n");
+    } else {
+	DECODE_PRINTF("POPF\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EFLG = pop_long();
+    } else {
+	M.x86.R_FLG = pop_word();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x9e
+****************************************************************************/
+void x86emuOp_sahf(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("SAHF\n");
+    TRACE_AND_STEP();
+    /* clear the lower bits of the flag register */
+    M.x86.R_FLG &= 0xffffff00;
+    /* or in the AH register into the flags register */
+    M.x86.R_FLG |= M.x86.R_AH;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x9f
+****************************************************************************/
+void x86emuOp_lahf(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("LAHF\n");
+    TRACE_AND_STEP();
+	M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff);
+    /*undocumented TC++ behavior??? Nope.  It's documented, but
+       you have too look real hard to notice it. */
+    M.x86.R_AH |= 0x2;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa0
+****************************************************************************/
+void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 offset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\tAL,");
+    offset = fetch_word_imm();
+    DECODE_PRINTF2("[%04x]\n", offset);
+    TRACE_AND_STEP();
+    M.x86.R_AL = fetch_data_byte(offset);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa1
+****************************************************************************/
+void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 offset;
+
+    START_OF_INSTR();
+    offset = fetch_word_imm();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset);
+    } else {
+	DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset);
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = fetch_data_long(offset);
+    } else {
+	M.x86.R_AX = fetch_data_word(offset);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa2
+****************************************************************************/
+void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 offset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\t");
+    offset = fetch_word_imm();
+    DECODE_PRINTF2("[%04x],AL\n", offset);
+    TRACE_AND_STEP();
+    store_data_byte(offset, M.x86.R_AL);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa3
+****************************************************************************/
+void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 offset;
+
+    START_OF_INSTR();
+    offset = fetch_word_imm();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset);
+    } else {
+	DECODE_PRINTF2("MOV\t[%04x],AX\n", offset);
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	store_data_long(offset, M.x86.R_EAX);
+    } else {
+	store_data_word(offset, M.x86.R_AX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa4
+****************************************************************************/
+void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1))
+{
+    u8  val;
+    u32 count;
+    int inc;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOVS\tBYTE\n");
+    if (ACCESS_FLAG(F_DF))   /* down */
+	inc = -1;
+    else
+	inc = 1;
+    TRACE_AND_STEP();
+    count = 1;
+    if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
+	/* dont care whether REPE or REPNE */
+	/* move them until CX is ZERO. */
+	count = M.x86.R_CX;
+	M.x86.R_CX = 0;
+	M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+    }
+    while (count--) {
+	val = fetch_data_byte(M.x86.R_SI);
+	store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val);
+	M.x86.R_SI += inc;
+	M.x86.R_DI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa5
+****************************************************************************/
+void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1))
+{
+    u32 val;
+    int inc;
+    u32 count;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("MOVS\tDWORD\n");
+	if (ACCESS_FLAG(F_DF))      /* down */
+	    inc = -4;
+	else
+	    inc = 4;
+    } else {
+	DECODE_PRINTF("MOVS\tWORD\n");
+	if (ACCESS_FLAG(F_DF))      /* down */
+	    inc = -2;
+	else
+	    inc = 2;
+    }
+    TRACE_AND_STEP();
+    count = 1;
+    if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
+	/* dont care whether REPE or REPNE */
+	/* move them until CX is ZERO. */
+	count = M.x86.R_CX;
+	M.x86.R_CX = 0;
+	M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+    }
+    while (count--) {
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    val = fetch_data_long(M.x86.R_SI);
+	    store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val);
+	} else {
+	    val = fetch_data_word(M.x86.R_SI);
+	    store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val);
+	}
+	M.x86.R_SI += inc;
+	M.x86.R_DI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa6
+****************************************************************************/
+void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1))
+{
+    s8 val1, val2;
+    int inc;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("CMPS\tBYTE\n");
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_DF))   /* down */
+	inc = -1;
+    else
+	inc = 1;
+
+    if (M.x86.mode & SYSMODE_PREFIX_REPE) {
+	/* REPE  */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    val1 = fetch_data_byte(M.x86.R_SI);
+	    val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+		     cmp_byte(val1, val2);
+	    M.x86.R_CX -= 1;
+	    M.x86.R_SI += inc;
+	    M.x86.R_DI += inc;
+	    if (ACCESS_FLAG(F_ZF) == 0)
+		break;
+	}
+	M.x86.mode &= ~SYSMODE_PREFIX_REPE;
+    } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) {
+	/* REPNE  */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    val1 = fetch_data_byte(M.x86.R_SI);
+	    val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+	    cmp_byte(val1, val2);
+	    M.x86.R_CX -= 1;
+	    M.x86.R_SI += inc;
+	    M.x86.R_DI += inc;
+	    if (ACCESS_FLAG(F_ZF))
+		break;          /* zero flag set means equal */
+	}
+	M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
+    } else {
+	val1 = fetch_data_byte(M.x86.R_SI);
+	val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+	cmp_byte(val1, val2);
+	M.x86.R_SI += inc;
+	M.x86.R_DI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa7
+****************************************************************************/
+void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1))
+{
+    u32 val1,val2;
+    int inc;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("CMPS\tDWORD\n");
+	if (ACCESS_FLAG(F_DF))   /* down */
+	    inc = -4;
+	else
+	    inc = 4;
+    } else {
+	DECODE_PRINTF("CMPS\tWORD\n");
+	if (ACCESS_FLAG(F_DF))   /* down */
+	    inc = -2;
+	else
+	    inc = 2;
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_REPE) {
+	/* REPE  */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		val1 = fetch_data_long(M.x86.R_SI);
+		val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+		cmp_long(val1, val2);
+	    } else {
+		val1 = fetch_data_word(M.x86.R_SI);
+		val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+		cmp_word((u16)val1, (u16)val2);
+	    }
+	    M.x86.R_CX -= 1;
+	    M.x86.R_SI += inc;
+	    M.x86.R_DI += inc;
+	    if (ACCESS_FLAG(F_ZF) == 0)
+		break;
+	}
+	M.x86.mode &= ~SYSMODE_PREFIX_REPE;
+    } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) {
+	/* REPNE  */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		val1 = fetch_data_long(M.x86.R_SI);
+		val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+		cmp_long(val1, val2);
+	    } else {
+		val1 = fetch_data_word(M.x86.R_SI);
+		val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+		cmp_word((u16)val1, (u16)val2);
+	    }
+	    M.x86.R_CX -= 1;
+	    M.x86.R_SI += inc;
+	    M.x86.R_DI += inc;
+	    if (ACCESS_FLAG(F_ZF))
+		break;          /* zero flag set means equal */
+	}
+	M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
+    } else {
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    val1 = fetch_data_long(M.x86.R_SI);
+	    val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+	    cmp_long(val1, val2);
+	} else {
+	    val1 = fetch_data_word(M.x86.R_SI);
+	    val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+	    cmp_word((u16)val1, (u16)val2);
+	}
+	M.x86.R_SI += inc;
+	M.x86.R_DI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa8
+****************************************************************************/
+void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("TEST\tAL,");
+    imm = fetch_byte_imm();
+    DECODE_PRINTF2("%04x\n", imm);
+    TRACE_AND_STEP();
+	test_byte(M.x86.R_AL, (u8)imm);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xa9
+****************************************************************************/
+void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("TEST\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("TEST\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	test_long(M.x86.R_EAX, srcval);
+    } else {
+	test_word(M.x86.R_AX, (u16)srcval);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xaa
+****************************************************************************/
+void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1))
+{
+    int inc;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("STOS\tBYTE\n");
+    if (ACCESS_FLAG(F_DF))   /* down */
+	inc = -1;
+    else
+	inc = 1;
+    TRACE_AND_STEP();
+    if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
+	/* dont care whether REPE or REPNE */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL);
+	    M.x86.R_CX -= 1;
+	    M.x86.R_DI += inc;
+	}
+	M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+    } else {
+	store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL);
+	M.x86.R_DI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xab
+****************************************************************************/
+void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1))
+{
+    int inc;
+    u32 count;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("STOS\tDWORD\n");
+	if (ACCESS_FLAG(F_DF))   /* down */
+	    inc = -4;
+	else
+	    inc = 4;
+    } else {
+	DECODE_PRINTF("STOS\tWORD\n");
+	if (ACCESS_FLAG(F_DF))   /* down */
+	    inc = -2;
+	else
+	    inc = 2;
+    }
+    TRACE_AND_STEP();
+    count = 1;
+    if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
+	/* dont care whether REPE or REPNE */
+	/* move them until CX is ZERO. */
+	count = M.x86.R_CX;
+	M.x86.R_CX = 0;
+	M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+    }
+    while (count--) {
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX);
+	} else {
+	    store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX);
+	}
+	M.x86.R_DI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xac
+****************************************************************************/
+void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1))
+{
+    int inc;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LODS\tBYTE\n");
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_DF))   /* down */
+	inc = -1;
+    else
+	inc = 1;
+    if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
+	/* dont care whether REPE or REPNE */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    M.x86.R_AL = fetch_data_byte(M.x86.R_SI);
+	    M.x86.R_CX -= 1;
+	    M.x86.R_SI += inc;
+	}
+	M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+    } else {
+	M.x86.R_AL = fetch_data_byte(M.x86.R_SI);
+	M.x86.R_SI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xad
+****************************************************************************/
+void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1))
+{
+    int inc;
+    u32 count;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("LODS\tDWORD\n");
+	if (ACCESS_FLAG(F_DF))   /* down */
+	    inc = -4;
+	else
+	    inc = 4;
+    } else {
+	DECODE_PRINTF("LODS\tWORD\n");
+	if (ACCESS_FLAG(F_DF))   /* down */
+	    inc = -2;
+	else
+	    inc = 2;
+    }
+    TRACE_AND_STEP();
+    count = 1;
+    if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
+	/* dont care whether REPE or REPNE */
+	/* move them until CX is ZERO. */
+	count = M.x86.R_CX;
+	M.x86.R_CX = 0;
+	M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+    }
+    while (count--) {
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    M.x86.R_EAX = fetch_data_long(M.x86.R_SI);
+	} else {
+	    M.x86.R_AX = fetch_data_word(M.x86.R_SI);
+	}
+	M.x86.R_SI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xae
+****************************************************************************/
+void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1))
+{
+    s8 val2;
+    int inc;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SCAS\tBYTE\n");
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_DF))   /* down */
+	inc = -1;
+    else
+	inc = 1;
+    if (M.x86.mode & SYSMODE_PREFIX_REPE) {
+	/* REPE  */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+	    cmp_byte(M.x86.R_AL, val2);
+	    M.x86.R_CX -= 1;
+	    M.x86.R_DI += inc;
+	    if (ACCESS_FLAG(F_ZF) == 0)
+		break;
+	}
+	M.x86.mode &= ~SYSMODE_PREFIX_REPE;
+    } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) {
+	/* REPNE  */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+	    cmp_byte(M.x86.R_AL, val2);
+	    M.x86.R_CX -= 1;
+	    M.x86.R_DI += inc;
+	    if (ACCESS_FLAG(F_ZF))
+		break;          /* zero flag set means equal */
+	}
+	M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
+    } else {
+	val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
+	cmp_byte(M.x86.R_AL, val2);
+	M.x86.R_DI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xaf
+****************************************************************************/
+void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1))
+{
+    int inc;
+    u32 val;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("SCAS\tDWORD\n");
+	if (ACCESS_FLAG(F_DF))   /* down */
+	    inc = -4;
+	else
+	    inc = 4;
+    } else {
+	DECODE_PRINTF("SCAS\tWORD\n");
+	if (ACCESS_FLAG(F_DF))   /* down */
+	    inc = -2;
+	else
+	    inc = 2;
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_REPE) {
+	/* REPE  */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+		cmp_long(M.x86.R_EAX, val);
+	    } else {
+		val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+		cmp_word(M.x86.R_AX, (u16)val);
+	    }
+	    M.x86.R_CX -= 1;
+	    M.x86.R_DI += inc;
+	    if (ACCESS_FLAG(F_ZF) == 0)
+		break;
+	}
+	M.x86.mode &= ~SYSMODE_PREFIX_REPE;
+    } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) {
+	/* REPNE  */
+	/* move them until CX is ZERO. */
+	while (M.x86.R_CX != 0) {
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+		cmp_long(M.x86.R_EAX, val);
+	    } else {
+		val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+		cmp_word(M.x86.R_AX, (u16)val);
+	    }
+	    M.x86.R_CX -= 1;
+	    M.x86.R_DI += inc;
+	    if (ACCESS_FLAG(F_ZF))
+		break;          /* zero flag set means equal */
+	}
+	M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
+    } else {
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
+	    cmp_long(M.x86.R_EAX, val);
+	} else {
+	    val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
+	    cmp_word(M.x86.R_AX, (u16)val);
+	}
+	M.x86.R_DI += inc;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb0
+****************************************************************************/
+void x86emuOp_mov_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\tAL,");
+    imm = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", imm);
+    TRACE_AND_STEP();
+    M.x86.R_AL = imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb1
+****************************************************************************/
+void x86emuOp_mov_byte_CL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\tCL,");
+    imm = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", imm);
+    TRACE_AND_STEP();
+    M.x86.R_CL = imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb2
+****************************************************************************/
+void x86emuOp_mov_byte_DL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\tDL,");
+    imm = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", imm);
+    TRACE_AND_STEP();
+    M.x86.R_DL = imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb3
+****************************************************************************/
+void x86emuOp_mov_byte_BL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\tBL,");
+    imm = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", imm);
+    TRACE_AND_STEP();
+    M.x86.R_BL = imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb4
+****************************************************************************/
+void x86emuOp_mov_byte_AH_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\tAH,");
+    imm = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", imm);
+    TRACE_AND_STEP();
+    M.x86.R_AH = imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb5
+****************************************************************************/
+void x86emuOp_mov_byte_CH_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\tCH,");
+    imm = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", imm);
+    TRACE_AND_STEP();
+    M.x86.R_CH = imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb6
+****************************************************************************/
+void x86emuOp_mov_byte_DH_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\tDH,");
+    imm = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", imm);
+    TRACE_AND_STEP();
+    M.x86.R_DH = imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb7
+****************************************************************************/
+void x86emuOp_mov_byte_BH_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\tBH,");
+    imm = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", imm);
+    TRACE_AND_STEP();
+    M.x86.R_BH = imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb8
+****************************************************************************/
+void x86emuOp_mov_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("MOV\tEAX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("MOV\tAX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = srcval;
+    } else {
+	M.x86.R_AX = (u16)srcval;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xb9
+****************************************************************************/
+void x86emuOp_mov_word_CX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("MOV\tECX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("MOV\tCX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ECX = srcval;
+    } else {
+	M.x86.R_CX = (u16)srcval;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xba
+****************************************************************************/
+void x86emuOp_mov_word_DX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("MOV\tEDX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("MOV\tDX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EDX = srcval;
+    } else {
+	M.x86.R_DX = (u16)srcval;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xbb
+****************************************************************************/
+void x86emuOp_mov_word_BX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("MOV\tEBX,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("MOV\tBX,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EBX = srcval;
+    } else {
+	M.x86.R_BX = (u16)srcval;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xbc
+****************************************************************************/
+void x86emuOp_mov_word_SP_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("MOV\tESP,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("MOV\tSP,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ESP = srcval;
+    } else {
+	M.x86.R_SP = (u16)srcval;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xbd
+****************************************************************************/
+void x86emuOp_mov_word_BP_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("MOV\tEBP,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("MOV\tBP,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EBP = srcval;
+    } else {
+	M.x86.R_BP = (u16)srcval;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xbe
+****************************************************************************/
+void x86emuOp_mov_word_SI_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("MOV\tESI,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("MOV\tSI,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_ESI = srcval;
+    } else {
+	M.x86.R_SI = (u16)srcval;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xbf
+****************************************************************************/
+void x86emuOp_mov_word_DI_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u32 srcval;
+
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("MOV\tEDI,");
+	srcval = fetch_long_imm();
+    } else {
+	DECODE_PRINTF("MOV\tDI,");
+	srcval = fetch_word_imm();
+    }
+    DECODE_PRINTF2("%x\n", srcval);
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EDI = srcval;
+    } else {
+	M.x86.R_DI = (u16)srcval;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/* used by opcodes c0, d0, and d2. */
+static u8(*opcD0_byte_operation[])(u8 d, u8 s) =
+{
+    rol_byte,
+    ror_byte,
+    rcl_byte,
+    rcr_byte,
+    shl_byte,
+    shr_byte,
+    shl_byte,           /* sal_byte === shl_byte  by definition */
+    sar_byte,
+};
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc0
+****************************************************************************/
+void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg;
+    uint destoffset;
+    u8 destval;
+    u8 amt;
+
+    /*
+     * Yet another weirdo special case instruction format.  Part of
+     * the opcode held below in "RH".  Doubly nested case would
+     * result, except that the decoded instruction
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ROL\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("ROR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("RCL\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("RCR\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("SHL\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SHR\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("SAL\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("SAR\t");
+	    break;
+	}
+    }
+#endif
+    /* know operation, decode the mod byte to find the addressing
+       mode. */
+    switch (mod) {
+    case 0:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm00_address(rl);
+	amt = fetch_byte_imm();
+	DECODE_PRINTF2(",%x\n", amt);
+	destval = fetch_data_byte(destoffset);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (destval, amt);
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm01_address(rl);
+	amt = fetch_byte_imm();
+	DECODE_PRINTF2(",%x\n", amt);
+	destval = fetch_data_byte(destoffset);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (destval, amt);
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm10_address(rl);
+	amt = fetch_byte_imm();
+	DECODE_PRINTF2(",%x\n", amt);
+	destval = fetch_data_byte(destoffset);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (destval, amt);
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	amt = fetch_byte_imm();
+	DECODE_PRINTF2(",%x\n", amt);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (*destreg, amt);
+	*destreg = destval;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/* used by opcodes c1, d1, and d3. */
+static u16(*opcD1_word_operation[])(u16 s, u8 d) =
+{
+    rol_word,
+    ror_word,
+    rcl_word,
+    rcr_word,
+    shl_word,
+    shr_word,
+    shl_word,           /* sal_byte === shl_byte  by definition */
+    sar_word,
+};
+
+/* used by opcodes c1, d1, and d3. */
+static u32 (*opcD1_long_operation[])(u32 s, u8 d) =
+{
+    rol_long,
+    ror_long,
+    rcl_long,
+    rcr_long,
+    shl_long,
+    shr_long,
+    shl_long,           /* sal_byte === shl_byte  by definition */
+    sar_long,
+};
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc1
+****************************************************************************/
+void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+    u8 amt;
+
+    /*
+     * Yet another weirdo special case instruction format.  Part of
+     * the opcode held below in "RH".  Doubly nested case would
+     * result, except that the decoded instruction
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ROL\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("ROR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("RCL\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("RCR\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("SHL\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SHR\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("SAL\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("SAR\t");
+	    break;
+	}
+    }
+#endif
+    /* know operation, decode the mod byte to find the addressing
+       mode. */
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    amt = fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", amt);
+	    destval = fetch_data_long(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (destval, amt);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    amt = fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", amt);
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (destval, amt);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    amt = fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", amt);
+	    destval = fetch_data_long(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (destval, amt);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    amt = fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", amt);
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (destval, amt);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    amt = fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", amt);
+	    destval = fetch_data_long(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (destval, amt);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    amt = fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", amt);
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (destval, amt);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    amt = fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", amt);
+	    TRACE_AND_STEP();
+	    *destreg = (*opcD1_long_operation[rh]) (*destreg, amt);
+	} else {
+	    u16 *destreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    amt = fetch_byte_imm();
+	    DECODE_PRINTF2(",%x\n", amt);
+	    TRACE_AND_STEP();
+	    *destreg = (*opcD1_word_operation[rh]) (*destreg, amt);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc2
+****************************************************************************/
+void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("RET\t");
+    imm = fetch_word_imm();
+    DECODE_PRINTF2("%x\n", imm);
+	RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip);
+	TRACE_AND_STEP();
+    M.x86.R_IP = pop_word();
+    M.x86.R_SP += imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc3
+****************************************************************************/
+void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("RET\n");
+	RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip);
+	TRACE_AND_STEP();
+    M.x86.R_IP = pop_word();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc4
+****************************************************************************/
+void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rh, rl;
+    u16 *dstreg;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LES\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_ES = fetch_data_word(srcoffset + 2);
+	break;
+    case 1:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_ES = fetch_data_word(srcoffset + 2);
+	break;
+    case 2:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_ES = fetch_data_word(srcoffset + 2);
+	break;
+    case 3:                     /* register to register */
+	/* UNDEFINED! */
+	TRACE_AND_STEP();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc5
+****************************************************************************/
+void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rh, rl;
+    u16 *dstreg;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LDS\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_DS = fetch_data_word(srcoffset + 2);
+	break;
+    case 1:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_DS = fetch_data_word(srcoffset + 2);
+	break;
+    case 2:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_DS = fetch_data_word(srcoffset + 2);
+	break;
+    case 3:                     /* register to register */
+	/* UNDEFINED! */
+	TRACE_AND_STEP();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc6
+****************************************************************************/
+void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg;
+    uint destoffset;
+    u8 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    if (rh != 0) {
+	DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
+	HALT_SYS();
+    }
+    switch (mod) {
+    case 0:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm00_address(rl);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2(",%2x\n", imm);
+	TRACE_AND_STEP();
+	store_data_byte(destoffset, imm);
+	break;
+    case 1:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm01_address(rl);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2(",%2x\n", imm);
+	TRACE_AND_STEP();
+	store_data_byte(destoffset, imm);
+	break;
+    case 2:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm10_address(rl);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2(",%2x\n", imm);
+	TRACE_AND_STEP();
+	store_data_byte(destoffset, imm);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	imm = fetch_byte_imm();
+	DECODE_PRINTF2(",%2x\n", imm);
+	TRACE_AND_STEP();
+	*destreg = imm;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc7
+****************************************************************************/
+void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOV\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    if (rh != 0) {
+	DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
+	HALT_SYS();
+    }
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 imm;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    store_data_long(destoffset, imm);
+	} else {
+	    u16 imm;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    store_data_word(destoffset, imm);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 imm;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    store_data_long(destoffset, imm);
+	} else {
+	    u16 imm;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    store_data_word(destoffset, imm);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 imm;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    store_data_long(destoffset, imm);
+	} else {
+	    u16 imm;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    store_data_word(destoffset, imm);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			u32 *destreg;
+			u32 imm;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    imm = fetch_long_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    *destreg = imm;
+	} else {
+			u16 *destreg;
+			u16 imm;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    imm = fetch_word_imm();
+	    DECODE_PRINTF2(",%x\n", imm);
+	    TRACE_AND_STEP();
+	    *destreg = imm;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc8
+****************************************************************************/
+void x86emuOp_enter(u8 X86EMU_UNUSED(op1))
+{
+    u16 local,frame_pointer;
+    u8  nesting;
+    int i;
+
+    START_OF_INSTR();
+    local = fetch_word_imm();
+    nesting = fetch_byte_imm();
+    DECODE_PRINTF2("ENTER %x\n", local);
+    DECODE_PRINTF2(",%x\n", nesting);
+    TRACE_AND_STEP();
+    push_word(M.x86.R_BP);
+    frame_pointer = M.x86.R_SP;
+    if (nesting > 0) {
+	for (i = 1; i < nesting; i++) {
+	    M.x86.R_BP -= 2;
+	    push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP));
+	    }
+	push_word(frame_pointer);
+	}
+    M.x86.R_BP = frame_pointer;
+    M.x86.R_SP = (u16)(M.x86.R_SP - local);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xc9
+****************************************************************************/
+void x86emuOp_leave(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("LEAVE\n");
+    TRACE_AND_STEP();
+    M.x86.R_SP = M.x86.R_BP;
+    M.x86.R_BP = pop_word();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xca
+****************************************************************************/
+void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 imm;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("RETF\t");
+    imm = fetch_word_imm();
+    DECODE_PRINTF2("%x\n", imm);
+	RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip);
+	TRACE_AND_STEP();
+    M.x86.R_IP = pop_word();
+    M.x86.R_CS = pop_word();
+    M.x86.R_SP += imm;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xcb
+****************************************************************************/
+void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("RETF\n");
+	RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip);
+	TRACE_AND_STEP();
+    M.x86.R_IP = pop_word();
+    M.x86.R_CS = pop_word();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xcc
+****************************************************************************/
+void x86emuOp_int3(u8 X86EMU_UNUSED(op1))
+{
+    u16 tmp;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("INT 3\n");
+    tmp = (u16) mem_access_word(3 * 4 + 2);
+    /* access the segment register */
+    TRACE_AND_STEP();
+	if (_X86EMU_intrTab[3]) {
+		(*_X86EMU_intrTab[3])(3);
+    } else {
+	push_word((u16)M.x86.R_FLG);
+	CLEAR_FLAG(F_IF);
+	CLEAR_FLAG(F_TF);
+	push_word(M.x86.R_CS);
+	M.x86.R_CS = mem_access_word(3 * 4 + 2);
+	push_word(M.x86.R_IP);
+	M.x86.R_IP = mem_access_word(3 * 4);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xcd
+****************************************************************************/
+void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 tmp;
+    u8 intnum;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("INT\t");
+    intnum = fetch_byte_imm();
+    DECODE_PRINTF2("%x\n", intnum);
+    tmp = mem_access_word(intnum * 4 + 2);
+    TRACE_AND_STEP();
+	if (_X86EMU_intrTab[intnum]) {
+		(*_X86EMU_intrTab[intnum])(intnum);
+    } else {
+	push_word((u16)M.x86.R_FLG);
+	CLEAR_FLAG(F_IF);
+	CLEAR_FLAG(F_TF);
+	push_word(M.x86.R_CS);
+	M.x86.R_CS = mem_access_word(intnum * 4 + 2);
+	push_word(M.x86.R_IP);
+	M.x86.R_IP = mem_access_word(intnum * 4);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xce
+****************************************************************************/
+void x86emuOp_into(u8 X86EMU_UNUSED(op1))
+{
+    u16 tmp;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("INTO\n");
+    TRACE_AND_STEP();
+    if (ACCESS_FLAG(F_OF)) {
+	tmp = mem_access_word(4 * 4 + 2);
+		if (_X86EMU_intrTab[4]) {
+			(*_X86EMU_intrTab[4])(4);
+	} else {
+	    push_word((u16)M.x86.R_FLG);
+	    CLEAR_FLAG(F_IF);
+	    CLEAR_FLAG(F_TF);
+	    push_word(M.x86.R_CS);
+	    M.x86.R_CS = mem_access_word(4 * 4 + 2);
+	    push_word(M.x86.R_IP);
+	    M.x86.R_IP = mem_access_word(4 * 4);
+	}
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xcf
+****************************************************************************/
+void x86emuOp_iret(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("IRET\n");
+
+    TRACE_AND_STEP();
+
+    M.x86.R_IP = pop_word();
+    M.x86.R_CS = pop_word();
+    M.x86.R_FLG = pop_word();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xd0
+****************************************************************************/
+void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg;
+    uint destoffset;
+    u8 destval;
+
+    /*
+     * Yet another weirdo special case instruction format.  Part of
+     * the opcode held below in "RH".  Doubly nested case would
+     * result, except that the decoded instruction
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ROL\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("ROR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("RCL\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("RCR\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("SHL\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SHR\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("SAL\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("SAR\t");
+	    break;
+	}
+    }
+#endif
+    /* know operation, decode the mod byte to find the addressing
+       mode. */
+    switch (mod) {
+    case 0:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",1\n");
+	destval = fetch_data_byte(destoffset);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (destval, 1);
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",1\n");
+	destval = fetch_data_byte(destoffset);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (destval, 1);
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",1\n");
+	destval = fetch_data_byte(destoffset);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (destval, 1);
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",1\n");
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (*destreg, 1);
+	*destreg = destval;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xd1
+****************************************************************************/
+void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    /*
+     * Yet another weirdo special case instruction format.  Part of
+     * the opcode held below in "RH".  Doubly nested case would
+     * result, except that the decoded instruction
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ROL\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("ROR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("RCL\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("RCR\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("SHL\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SHR\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("SAL\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("SAR\t");
+	    break;
+	}
+    }
+#endif
+    /* know operation, decode the mod byte to find the addressing
+       mode. */
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",1\n");
+	    destval = fetch_data_long(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (destval, 1);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",1\n");
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (destval, 1);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",1\n");
+	    destval = fetch_data_long(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (destval, 1);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",1\n");
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (destval, 1);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",1\n");
+	    destval = fetch_data_long(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (destval, 1);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    DECODE_PRINTF("BYTE PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",1\n");
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (destval, 1);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			u32 destval;
+			u32 *destreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",1\n");
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (*destreg, 1);
+	    *destreg = destval;
+	} else {
+			u16 destval;
+			u16 *destreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",1\n");
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (*destreg, 1);
+	    *destreg = destval;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xd2
+****************************************************************************/
+void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg;
+    uint destoffset;
+    u8 destval;
+    u8 amt;
+
+    /*
+     * Yet another weirdo special case instruction format.  Part of
+     * the opcode held below in "RH".  Doubly nested case would
+     * result, except that the decoded instruction
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ROL\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("ROR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("RCL\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("RCR\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("SHL\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SHR\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("SAL\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("SAR\t");
+	    break;
+	}
+    }
+#endif
+    /* know operation, decode the mod byte to find the addressing
+       mode. */
+    amt = M.x86.R_CL;
+    switch (mod) {
+    case 0:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF(",CL\n");
+	destval = fetch_data_byte(destoffset);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (destval, amt);
+	store_data_byte(destoffset, destval);
+	break;
+    case 1:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF(",CL\n");
+	destval = fetch_data_byte(destoffset);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (destval, amt);
+	store_data_byte(destoffset, destval);
+	break;
+    case 2:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF(",CL\n");
+	destval = fetch_data_byte(destoffset);
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (destval, amt);
+	store_data_byte(destoffset, destval);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF(",CL\n");
+	TRACE_AND_STEP();
+	destval = (*opcD0_byte_operation[rh]) (*destreg, amt);
+	*destreg = destval;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xd3
+****************************************************************************/
+void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+    u8 amt;
+
+    /*
+     * Yet another weirdo special case instruction format.  Part of
+     * the opcode held below in "RH".  Doubly nested case would
+     * result, except that the decoded instruction
+     */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("ROL\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("ROR\t");
+	    break;
+	case 2:
+	    DECODE_PRINTF("RCL\t");
+	    break;
+	case 3:
+	    DECODE_PRINTF("RCR\t");
+	    break;
+	case 4:
+	    DECODE_PRINTF("SHL\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("SHR\t");
+	    break;
+	case 6:
+	    DECODE_PRINTF("SAL\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("SAR\t");
+	    break;
+	}
+    }
+#endif
+    /* know operation, decode the mod byte to find the addressing
+       mode. */
+    amt = M.x86.R_CL;
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",CL\n");
+	    destval = fetch_data_long(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (destval, amt);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",CL\n");
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (destval, amt);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",CL\n");
+	    destval = fetch_data_long(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (destval, amt);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",CL\n");
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (destval, amt);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+
+	    DECODE_PRINTF("DWORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",CL\n");
+	    destval = fetch_data_long(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_long_operation[rh]) (destval, amt);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+
+	    DECODE_PRINTF("WORD PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",CL\n");
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    destval = (*opcD1_word_operation[rh]) (destval, amt);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    *destreg = (*opcD1_long_operation[rh]) (*destreg, amt);
+	} else {
+	    u16 *destreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    *destreg = (*opcD1_word_operation[rh]) (*destreg, amt);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xd4
+****************************************************************************/
+void x86emuOp_aam(u8 X86EMU_UNUSED(op1))
+{
+    u8 a;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("AAM\n");
+    a = fetch_byte_imm();      /* this is a stupid encoding. */
+    if (a != 10) {
+	DECODE_PRINTF("ERROR DECODING AAM\n");
+	TRACE_REGS();
+	HALT_SYS();
+    }
+    TRACE_AND_STEP();
+    /* note the type change here --- returning AL and AH in AX. */
+    M.x86.R_AX = aam_word(M.x86.R_AL);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xd5
+****************************************************************************/
+void x86emuOp_aad(u8 X86EMU_UNUSED(op1))
+{
+    u8 a;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("AAD\n");
+    a = fetch_byte_imm();
+    TRACE_AND_STEP();
+    M.x86.R_AX = aad_word(M.x86.R_AX);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/* opcode 0xd6 ILLEGAL OPCODE */
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xd7
+****************************************************************************/
+void x86emuOp_xlat(u8 X86EMU_UNUSED(op1))
+{
+    u16 addr;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("XLAT\n");
+    TRACE_AND_STEP();
+	addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL);
+    M.x86.R_AL = fetch_data_byte(addr);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/* instuctions  D8 .. DF are in i87_ops.c */
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe0
+****************************************************************************/
+void x86emuOp_loopne(u8 X86EMU_UNUSED(op1))
+{
+    s16 ip;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LOOPNE\t");
+    ip = (s8) fetch_byte_imm();
+    ip += (s16) M.x86.R_IP;
+    DECODE_PRINTF2("%04x\n", ip);
+    TRACE_AND_STEP();
+    M.x86.R_CX -= 1;
+    if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF))      /* CX != 0 and !ZF */
+	M.x86.R_IP = ip;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe1
+****************************************************************************/
+void x86emuOp_loope(u8 X86EMU_UNUSED(op1))
+{
+    s16 ip;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LOOPE\t");
+    ip = (s8) fetch_byte_imm();
+    ip += (s16) M.x86.R_IP;
+    DECODE_PRINTF2("%04x\n", ip);
+    TRACE_AND_STEP();
+    M.x86.R_CX -= 1;
+    if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF))       /* CX != 0 and ZF */
+	M.x86.R_IP = ip;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe2
+****************************************************************************/
+void x86emuOp_loop(u8 X86EMU_UNUSED(op1))
+{
+    s16 ip;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LOOP\t");
+    ip = (s8) fetch_byte_imm();
+    ip += (s16) M.x86.R_IP;
+    DECODE_PRINTF2("%04x\n", ip);
+    TRACE_AND_STEP();
+    M.x86.R_CX -= 1;
+    if (M.x86.R_CX != 0)
+	M.x86.R_IP = ip;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe3
+****************************************************************************/
+void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1))
+{
+    u16 target;
+    s8  offset;
+
+    /* jump to byte offset if overflow flag is set */
+    START_OF_INSTR();
+    DECODE_PRINTF("JCXZ\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    if (M.x86.R_CX == 0)
+	M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe4
+****************************************************************************/
+void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 port;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("IN\t");
+	port = (u8) fetch_byte_imm();
+    DECODE_PRINTF2("%x,AL\n", port);
+    TRACE_AND_STEP();
+    M.x86.R_AL = (*sys_inb)(port);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe5
+****************************************************************************/
+void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u8 port;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("IN\t");
+	port = (u8) fetch_byte_imm();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF2("EAX,%x\n", port);
+    } else {
+	DECODE_PRINTF2("AX,%x\n", port);
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = (*sys_inl)(port);
+    } else {
+	M.x86.R_AX = (*sys_inw)(port);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe6
+****************************************************************************/
+void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1))
+{
+    u8 port;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("OUT\t");
+	port = (u8) fetch_byte_imm();
+    DECODE_PRINTF2("%x,AL\n", port);
+    TRACE_AND_STEP();
+    (*sys_outb)(port, M.x86.R_AL);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe7
+****************************************************************************/
+void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1))
+{
+    u8 port;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("OUT\t");
+	port = (u8) fetch_byte_imm();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF2("%x,EAX\n", port);
+    } else {
+	DECODE_PRINTF2("%x,AX\n", port);
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	(*sys_outl)(port, M.x86.R_EAX);
+    } else {
+	(*sys_outw)(port, M.x86.R_AX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe8
+****************************************************************************/
+void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1))
+{
+    s16 ip;
+
+    START_OF_INSTR();
+	DECODE_PRINTF("CALL\t");
+	ip = (s16) fetch_word_imm();
+	ip += (s16) M.x86.R_IP;    /* CHECK SIGN */
+	DECODE_PRINTF2("%04x\n", ip);
+	CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, "");
+    TRACE_AND_STEP();
+    push_word(M.x86.R_IP);
+    M.x86.R_IP = ip;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xe9
+****************************************************************************/
+void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1))
+{
+    int ip;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("JMP\t");
+    ip = (s16)fetch_word_imm();
+    ip += (s16)M.x86.R_IP;
+    DECODE_PRINTF2("%04x\n", ip);
+    TRACE_AND_STEP();
+    M.x86.R_IP = (u16)ip;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xea
+****************************************************************************/
+void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 cs, ip;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("JMP\tFAR ");
+    ip = fetch_word_imm();
+    cs = fetch_word_imm();
+    DECODE_PRINTF2("%04x:", cs);
+    DECODE_PRINTF2("%04x\n", ip);
+    TRACE_AND_STEP();
+    M.x86.R_IP = ip;
+    M.x86.R_CS = cs;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xeb
+****************************************************************************/
+void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1))
+{
+    u16 target;
+    s8 offset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("JMP\t");
+    offset = (s8)fetch_byte_imm();
+    target = (u16)(M.x86.R_IP + offset);
+    DECODE_PRINTF2("%x\n", target);
+    TRACE_AND_STEP();
+    M.x86.R_IP = target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xec
+****************************************************************************/
+void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("IN\tAL,DX\n");
+    TRACE_AND_STEP();
+    M.x86.R_AL = (*sys_inb)(M.x86.R_DX);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xed
+****************************************************************************/
+void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("IN\tEAX,DX\n");
+    } else {
+	DECODE_PRINTF("IN\tAX,DX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	M.x86.R_EAX = (*sys_inl)(M.x86.R_DX);
+    } else {
+	M.x86.R_AX = (*sys_inw)(M.x86.R_DX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xee
+****************************************************************************/
+void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("OUT\tDX,AL\n");
+    TRACE_AND_STEP();
+    (*sys_outb)(M.x86.R_DX, M.x86.R_AL);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xef
+****************************************************************************/
+void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	DECODE_PRINTF("OUT\tDX,EAX\n");
+    } else {
+	DECODE_PRINTF("OUT\tDX,AX\n");
+    }
+    TRACE_AND_STEP();
+    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	(*sys_outl)(M.x86.R_DX, M.x86.R_EAX);
+    } else {
+	(*sys_outw)(M.x86.R_DX, M.x86.R_AX);
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xf0
+****************************************************************************/
+void x86emuOp_lock(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("LOCK:\n");
+    TRACE_AND_STEP();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/*opcode 0xf1 ILLEGAL OPERATION */
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xf2
+****************************************************************************/
+void x86emuOp_repne(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("REPNE\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_PREFIX_REPNE;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xf3
+****************************************************************************/
+void x86emuOp_repe(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("REPE\n");
+    TRACE_AND_STEP();
+    M.x86.mode |= SYSMODE_PREFIX_REPE;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xf4
+****************************************************************************/
+void x86emuOp_halt(u8 X86EMU_UNUSED(op1))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("HALT\n");
+    TRACE_AND_STEP();
+    HALT_SYS();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xf5
+****************************************************************************/
+void x86emuOp_cmc(u8 X86EMU_UNUSED(op1))
+{
+    /* complement the carry flag. */
+    START_OF_INSTR();
+    DECODE_PRINTF("CMC\n");
+    TRACE_AND_STEP();
+    TOGGLE_FLAG(F_CF);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xf6
+****************************************************************************/
+void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    u8 *destreg;
+    uint destoffset;
+    u8 destval, srcval;
+
+    /* long, drawn out code follows.  Double switch for a total
+       of 32 cases.  */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:                     /* mod=00 */
+	switch (rh) {
+	case 0:         /* test byte imm */
+	    DECODE_PRINTF("TEST\tBYTE PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    srcval = fetch_byte_imm();
+	    DECODE_PRINTF2("%02x\n", srcval);
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    test_byte(destval, srcval);
+	    break;
+	case 1:
+	    DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+	    HALT_SYS();
+	    break;
+	case 2:
+	    DECODE_PRINTF("NOT\tBYTE PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = not_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	case 3:
+	    DECODE_PRINTF("NEG\tBYTE PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = neg_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	case 4:
+	    DECODE_PRINTF("MUL\tBYTE PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    mul_byte(destval);
+	    break;
+	case 5:
+	    DECODE_PRINTF("IMUL\tBYTE PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    imul_byte(destval);
+	    break;
+	case 6:
+	    DECODE_PRINTF("DIV\tBYTE PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    div_byte(destval);
+	    break;
+	case 7:
+	    DECODE_PRINTF("IDIV\tBYTE PTR ");
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    idiv_byte(destval);
+	    break;
+	}
+	break;                  /* end mod==00 */
+    case 1:                     /* mod=01 */
+	switch (rh) {
+	case 0:         /* test byte imm */
+	    DECODE_PRINTF("TEST\tBYTE PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    srcval = fetch_byte_imm();
+	    DECODE_PRINTF2("%02x\n", srcval);
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    test_byte(destval, srcval);
+	    break;
+	case 1:
+	    DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n");
+	    HALT_SYS();
+	    break;
+	case 2:
+	    DECODE_PRINTF("NOT\tBYTE PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = not_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	case 3:
+	    DECODE_PRINTF("NEG\tBYTE PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = neg_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	case 4:
+	    DECODE_PRINTF("MUL\tBYTE PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    mul_byte(destval);
+	    break;
+	case 5:
+	    DECODE_PRINTF("IMUL\tBYTE PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    imul_byte(destval);
+	    break;
+	case 6:
+	    DECODE_PRINTF("DIV\tBYTE PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    div_byte(destval);
+	    break;
+	case 7:
+	    DECODE_PRINTF("IDIV\tBYTE PTR ");
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    idiv_byte(destval);
+	    break;
+	}
+	break;                  /* end mod==01 */
+    case 2:                     /* mod=10 */
+	switch (rh) {
+	case 0:         /* test byte imm */
+	    DECODE_PRINTF("TEST\tBYTE PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    srcval = fetch_byte_imm();
+	    DECODE_PRINTF2("%02x\n", srcval);
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    test_byte(destval, srcval);
+	    break;
+	case 1:
+	    DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n");
+	    HALT_SYS();
+	    break;
+	case 2:
+	    DECODE_PRINTF("NOT\tBYTE PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = not_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	case 3:
+	    DECODE_PRINTF("NEG\tBYTE PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = neg_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	case 4:
+	    DECODE_PRINTF("MUL\tBYTE PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    mul_byte(destval);
+	    break;
+	case 5:
+	    DECODE_PRINTF("IMUL\tBYTE PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    imul_byte(destval);
+	    break;
+	case 6:
+	    DECODE_PRINTF("DIV\tBYTE PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    div_byte(destval);
+	    break;
+	case 7:
+	    DECODE_PRINTF("IDIV\tBYTE PTR ");
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF("\n");
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    idiv_byte(destval);
+	    break;
+	}
+	break;                  /* end mod==10 */
+    case 3:                     /* mod=11 */
+	switch (rh) {
+	case 0:         /* test byte imm */
+	    DECODE_PRINTF("TEST\t");
+	    destreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    srcval = fetch_byte_imm();
+	    DECODE_PRINTF2("%02x\n", srcval);
+	    TRACE_AND_STEP();
+	    test_byte(*destreg, srcval);
+	    break;
+	case 1:
+	    DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+	    HALT_SYS();
+	    break;
+	case 2:
+	    DECODE_PRINTF("NOT\t");
+	    destreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = not_byte(*destreg);
+	    break;
+	case 3:
+	    DECODE_PRINTF("NEG\t");
+	    destreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = neg_byte(*destreg);
+	    break;
+	case 4:
+	    DECODE_PRINTF("MUL\t");
+	    destreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    mul_byte(*destreg);      /*!!!  */
+	    break;
+	case 5:
+	    DECODE_PRINTF("IMUL\t");
+	    destreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    imul_byte(*destreg);
+	    break;
+	case 6:
+	    DECODE_PRINTF("DIV\t");
+	    destreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    div_byte(*destreg);
+	    break;
+	case 7:
+	    DECODE_PRINTF("IDIV\t");
+	    destreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    idiv_byte(*destreg);
+	    break;
+	}
+	break;                  /* end mod==11 */
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xf7
+****************************************************************************/
+void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    /* long, drawn out code follows.  Double switch for a total
+       of 32 cases.  */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:                     /* mod=00 */
+	switch (rh) {
+	case 0:         /* test word imm */
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval,srcval;
+
+		DECODE_PRINTF("TEST\tDWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF(",");
+		srcval = fetch_long_imm();
+		DECODE_PRINTF2("%x\n", srcval);
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		test_long(destval, srcval);
+	    } else {
+		u16 destval,srcval;
+
+		DECODE_PRINTF("TEST\tWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF(",");
+		srcval = fetch_word_imm();
+		DECODE_PRINTF2("%x\n", srcval);
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		test_word(destval, srcval);
+	    }
+	    break;
+	case 1:
+	    DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
+	    HALT_SYS();
+	    break;
+	case 2:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("NOT\tDWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = not_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("NOT\tWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = not_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 3:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("NEG\tDWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = neg_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("NEG\tWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = neg_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 4:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("MUL\tDWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		mul_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("MUL\tWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		mul_word(destval);
+	    }
+	    break;
+	case 5:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("IMUL\tDWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		imul_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("IMUL\tWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		imul_word(destval);
+	    }
+	    break;
+	case 6:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("DIV\tDWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		div_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("DIV\tWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		div_word(destval);
+	    }
+	    break;
+	case 7:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("IDIV\tDWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		idiv_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("IDIV\tWORD PTR ");
+		destoffset = decode_rm00_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		idiv_word(destval);
+	    }
+	    break;
+	}
+	break;                  /* end mod==00 */
+    case 1:                     /* mod=01 */
+	switch (rh) {
+	case 0:         /* test word imm */
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval,srcval;
+
+		DECODE_PRINTF("TEST\tDWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF(",");
+		srcval = fetch_long_imm();
+		DECODE_PRINTF2("%x\n", srcval);
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		test_long(destval, srcval);
+	    } else {
+		u16 destval,srcval;
+
+		DECODE_PRINTF("TEST\tWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF(",");
+		srcval = fetch_word_imm();
+		DECODE_PRINTF2("%x\n", srcval);
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		test_word(destval, srcval);
+	    }
+	    break;
+	case 1:
+	    DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n");
+	    HALT_SYS();
+	    break;
+	case 2:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("NOT\tDWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = not_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("NOT\tWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = not_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 3:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("NEG\tDWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = neg_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("NEG\tWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = neg_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 4:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("MUL\tDWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		mul_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("MUL\tWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		mul_word(destval);
+	    }
+	    break;
+	case 5:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("IMUL\tDWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		imul_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("IMUL\tWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		imul_word(destval);
+	    }
+	    break;
+	case 6:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("DIV\tDWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		div_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("DIV\tWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		div_word(destval);
+	    }
+	    break;
+	case 7:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("IDIV\tDWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		idiv_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("IDIV\tWORD PTR ");
+		destoffset = decode_rm01_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		idiv_word(destval);
+	    }
+	    break;
+	}
+	break;                  /* end mod==01 */
+    case 2:                     /* mod=10 */
+	switch (rh) {
+	case 0:         /* test word imm */
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval,srcval;
+
+		DECODE_PRINTF("TEST\tDWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF(",");
+		srcval = fetch_long_imm();
+		DECODE_PRINTF2("%x\n", srcval);
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		test_long(destval, srcval);
+	    } else {
+		u16 destval,srcval;
+
+		DECODE_PRINTF("TEST\tWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF(",");
+		srcval = fetch_word_imm();
+		DECODE_PRINTF2("%x\n", srcval);
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		test_word(destval, srcval);
+	    }
+	    break;
+	case 1:
+	    DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n");
+	    HALT_SYS();
+	    break;
+	case 2:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("NOT\tDWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = not_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("NOT\tWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = not_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 3:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("NEG\tDWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = neg_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("NEG\tWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = neg_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 4:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("MUL\tDWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		mul_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("MUL\tWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		mul_word(destval);
+	    }
+	    break;
+	case 5:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("IMUL\tDWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		imul_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("IMUL\tWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		imul_word(destval);
+	    }
+	    break;
+	case 6:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("DIV\tDWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		div_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("DIV\tWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		div_word(destval);
+	    }
+	    break;
+	case 7:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		DECODE_PRINTF("IDIV\tDWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		idiv_long(destval);
+	    } else {
+		u16 destval;
+
+		DECODE_PRINTF("IDIV\tWORD PTR ");
+		destoffset = decode_rm10_address(rl);
+		DECODE_PRINTF("\n");
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		idiv_word(destval);
+	    }
+	    break;
+	}
+	break;                  /* end mod==10 */
+    case 3:                     /* mod=11 */
+	switch (rh) {
+	case 0:         /* test word imm */
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+		u32 srcval;
+
+		DECODE_PRINTF("TEST\t");
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF(",");
+		srcval = fetch_long_imm();
+		DECODE_PRINTF2("%x\n", srcval);
+		TRACE_AND_STEP();
+		test_long(*destreg, srcval);
+	    } else {
+		u16 *destreg;
+		u16 srcval;
+
+		DECODE_PRINTF("TEST\t");
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF(",");
+		srcval = fetch_word_imm();
+		DECODE_PRINTF2("%x\n", srcval);
+		TRACE_AND_STEP();
+		test_word(*destreg, srcval);
+	    }
+	    break;
+	case 1:
+	    DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
+	    HALT_SYS();
+	    break;
+	case 2:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+
+		DECODE_PRINTF("NOT\t");
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		*destreg = not_long(*destreg);
+	    } else {
+		u16 *destreg;
+
+		DECODE_PRINTF("NOT\t");
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		*destreg = not_word(*destreg);
+	    }
+	    break;
+	case 3:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+
+		DECODE_PRINTF("NEG\t");
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		*destreg = neg_long(*destreg);
+	    } else {
+		u16 *destreg;
+
+		DECODE_PRINTF("NEG\t");
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		*destreg = neg_word(*destreg);
+	    }
+	    break;
+	case 4:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+
+		DECODE_PRINTF("MUL\t");
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		mul_long(*destreg);      /*!!!  */
+	    } else {
+		u16 *destreg;
+
+		DECODE_PRINTF("MUL\t");
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		mul_word(*destreg);      /*!!!  */
+	    }
+	    break;
+	case 5:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+
+		DECODE_PRINTF("IMUL\t");
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		imul_long(*destreg);
+	    } else {
+		u16 *destreg;
+
+		DECODE_PRINTF("IMUL\t");
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		imul_word(*destreg);
+	    }
+	    break;
+	case 6:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+
+		DECODE_PRINTF("DIV\t");
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		div_long(*destreg);
+	    } else {
+		u16 *destreg;
+
+		DECODE_PRINTF("DIV\t");
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		div_word(*destreg);
+	    }
+	    break;
+	case 7:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+
+		DECODE_PRINTF("IDIV\t");
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		idiv_long(*destreg);
+	    } else {
+		u16 *destreg;
+
+		DECODE_PRINTF("IDIV\t");
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		idiv_word(*destreg);
+	    }
+	    break;
+	}
+	break;                  /* end mod==11 */
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xf8
+****************************************************************************/
+void x86emuOp_clc(u8 X86EMU_UNUSED(op1))
+{
+    /* clear the carry flag. */
+    START_OF_INSTR();
+    DECODE_PRINTF("CLC\n");
+    TRACE_AND_STEP();
+    CLEAR_FLAG(F_CF);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xf9
+****************************************************************************/
+void x86emuOp_stc(u8 X86EMU_UNUSED(op1))
+{
+    /* set the carry flag. */
+    START_OF_INSTR();
+    DECODE_PRINTF("STC\n");
+    TRACE_AND_STEP();
+    SET_FLAG(F_CF);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xfa
+****************************************************************************/
+void x86emuOp_cli(u8 X86EMU_UNUSED(op1))
+{
+    /* clear interrupts. */
+    START_OF_INSTR();
+    DECODE_PRINTF("CLI\n");
+    TRACE_AND_STEP();
+    CLEAR_FLAG(F_IF);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xfb
+****************************************************************************/
+void x86emuOp_sti(u8 X86EMU_UNUSED(op1))
+{
+    /* enable  interrupts. */
+    START_OF_INSTR();
+    DECODE_PRINTF("STI\n");
+    TRACE_AND_STEP();
+    SET_FLAG(F_IF);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xfc
+****************************************************************************/
+void x86emuOp_cld(u8 X86EMU_UNUSED(op1))
+{
+    /* clear interrupts. */
+    START_OF_INSTR();
+    DECODE_PRINTF("CLD\n");
+    TRACE_AND_STEP();
+    CLEAR_FLAG(F_DF);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xfd
+****************************************************************************/
+void x86emuOp_std(u8 X86EMU_UNUSED(op1))
+{
+    /* clear interrupts. */
+    START_OF_INSTR();
+    DECODE_PRINTF("STD\n");
+    TRACE_AND_STEP();
+    SET_FLAG(F_DF);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xfe
+****************************************************************************/
+void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rh, rl;
+    u8 destval;
+    uint destoffset;
+    u8 *destreg;
+
+    /* Yet another special case instruction. */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+
+	switch (rh) {
+	case 0:
+	    DECODE_PRINTF("INC\t");
+	    break;
+	case 1:
+	    DECODE_PRINTF("DEC\t");
+	    break;
+	case 2:
+	case 3:
+	case 4:
+	case 5:
+	case 6:
+	case 7:
+	    DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod);
+	    HALT_SYS();
+	    break;
+	}
+    }
+#endif
+    switch (mod) {
+    case 0:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	switch (rh) {
+	case 0:         /* inc word ptr ... */
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = inc_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	case 1:         /* dec word ptr ... */
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = dec_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	}
+	break;
+    case 1:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	switch (rh) {
+	case 0:
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = inc_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	case 1:
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = dec_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	}
+	break;
+    case 2:
+	DECODE_PRINTF("BYTE PTR ");
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	switch (rh) {
+	case 0:
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = inc_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	case 1:
+	    destval = fetch_data_byte(destoffset);
+	    TRACE_AND_STEP();
+	    destval = dec_byte(destval);
+	    store_data_byte(destoffset, destval);
+	    break;
+	}
+	break;
+    case 3:
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	switch (rh) {
+	case 0:
+	    TRACE_AND_STEP();
+	    *destreg = inc_byte(*destreg);
+	    break;
+	case 1:
+	    TRACE_AND_STEP();
+	    *destreg = dec_byte(*destreg);
+	    break;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0xff
+****************************************************************************/
+void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
+{
+    int mod, rh, rl;
+    uint destoffset = 0;
+	u16 *destreg;
+	u16 destval,destval2;
+
+    /* Yet another special case instruction. */
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+#ifdef DEBUG
+    if (DEBUG_DECODE()) {
+	/* XXX DECODE_PRINTF may be changed to something more
+	   general, so that it is important to leave the strings
+	   in the same format, even though the result is that the
+	   above test is done twice. */
+
+	switch (rh) {
+	case 0:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		DECODE_PRINTF("INC\tDWORD PTR ");
+	    } else {
+		DECODE_PRINTF("INC\tWORD PTR ");
+	    }
+	    break;
+	case 1:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		DECODE_PRINTF("DEC\tDWORD PTR ");
+	    } else {
+		DECODE_PRINTF("DEC\tWORD PTR ");
+	    }
+	    break;
+	case 2:
+	    DECODE_PRINTF("CALL\t ");
+	    break;
+	case 3:
+	    DECODE_PRINTF("CALL\tFAR ");
+	    break;
+	case 4:
+	    DECODE_PRINTF("JMP\t");
+	    break;
+	case 5:
+	    DECODE_PRINTF("JMP\tFAR ");
+	    break;
+	case 6:
+	    DECODE_PRINTF("PUSH\t");
+	    break;
+	case 7:
+	    DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
+	    HALT_SYS();
+	    break;
+	}
+    }
+#endif
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	switch (rh) {
+	case 0:         /* inc word ptr ... */
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = inc_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = inc_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 1:         /* dec word ptr ... */
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = dec_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = dec_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 2:         /* call word ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    push_word(M.x86.R_IP);
+	    M.x86.R_IP = destval;
+	    break;
+	case 3:         /* call far ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    destval2 = fetch_data_word(destoffset + 2);
+	    TRACE_AND_STEP();
+	    push_word(M.x86.R_CS);
+	    M.x86.R_CS = destval2;
+	    push_word(M.x86.R_IP);
+	    M.x86.R_IP = destval;
+	    break;
+	case 4:         /* jmp word ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    M.x86.R_IP = destval;
+	    break;
+	case 5:         /* jmp far ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    destval2 = fetch_data_word(destoffset + 2);
+	    TRACE_AND_STEP();
+	    M.x86.R_IP = destval;
+	    M.x86.R_CS = destval2;
+	    break;
+	case 6:         /*  push word ptr ... */
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		push_long(destval);
+	    } else {
+		u16 destval;
+
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		push_word(destval);
+	    }
+	    break;
+	}
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	switch (rh) {
+	case 0:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = inc_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = inc_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 1:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = dec_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = dec_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 2:         /* call word ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    push_word(M.x86.R_IP);
+	    M.x86.R_IP = destval;
+	    break;
+	case 3:         /* call far ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    destval2 = fetch_data_word(destoffset + 2);
+	    TRACE_AND_STEP();
+	    push_word(M.x86.R_CS);
+	    M.x86.R_CS = destval2;
+	    push_word(M.x86.R_IP);
+	    M.x86.R_IP = destval;
+	    break;
+	case 4:         /* jmp word ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    M.x86.R_IP = destval;
+	    break;
+	case 5:         /* jmp far ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    destval2 = fetch_data_word(destoffset + 2);
+	    TRACE_AND_STEP();
+	    M.x86.R_IP = destval;
+	    M.x86.R_CS = destval2;
+	    break;
+	case 6:         /*  push word ptr ... */
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		push_long(destval);
+	    } else {
+		u16 destval;
+
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		push_word(destval);
+	    }
+	    break;
+	}
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	switch (rh) {
+	case 0:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = inc_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = inc_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 1:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		destval = dec_long(destval);
+		store_data_long(destoffset, destval);
+	    } else {
+		u16 destval;
+
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		destval = dec_word(destval);
+		store_data_word(destoffset, destval);
+	    }
+	    break;
+	case 2:         /* call word ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    push_word(M.x86.R_IP);
+	    M.x86.R_IP = destval;
+	    break;
+	case 3:         /* call far ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    destval2 = fetch_data_word(destoffset + 2);
+	    TRACE_AND_STEP();
+	    push_word(M.x86.R_CS);
+	    M.x86.R_CS = destval2;
+	    push_word(M.x86.R_IP);
+	    M.x86.R_IP = destval;
+	    break;
+	case 4:         /* jmp word ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    TRACE_AND_STEP();
+	    M.x86.R_IP = destval;
+	    break;
+	case 5:         /* jmp far ptr ... */
+	    destval = fetch_data_word(destoffset);
+	    destval2 = fetch_data_word(destoffset + 2);
+	    TRACE_AND_STEP();
+	    M.x86.R_IP = destval;
+	    M.x86.R_CS = destval2;
+	    break;
+	case 6:         /*  push word ptr ... */
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 destval;
+
+		destval = fetch_data_long(destoffset);
+		TRACE_AND_STEP();
+		push_long(destval);
+	    } else {
+		u16 destval;
+
+		destval = fetch_data_word(destoffset);
+		TRACE_AND_STEP();
+		push_word(destval);
+	    }
+	    break;
+	}
+	break;
+    case 3:
+	switch (rh) {
+	case 0:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		*destreg = inc_long(*destreg);
+	    } else {
+		u16 *destreg;
+
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		*destreg = inc_word(*destreg);
+	    }
+	    break;
+	case 1:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		*destreg = dec_long(*destreg);
+	    } else {
+		u16 *destreg;
+
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		*destreg = dec_word(*destreg);
+	    }
+	    break;
+	case 2:         /* call word ptr ... */
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    push_word(M.x86.R_IP);
+	    M.x86.R_IP = *destreg;
+	    break;
+	case 3:         /* jmp far ptr ... */
+	    DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+	    TRACE_AND_STEP();
+	    HALT_SYS();
+	    break;
+
+	case 4:         /* jmp  ... */
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    M.x86.R_IP = (u16) (*destreg);
+	    break;
+	case 5:         /* jmp far ptr ... */
+	    DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
+	    TRACE_AND_STEP();
+	    HALT_SYS();
+	    break;
+	case 6:
+	    if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+		u32 *destreg;
+
+		destreg = DECODE_RM_LONG_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		push_long(*destreg);
+	    } else {
+		u16 *destreg;
+
+		destreg = DECODE_RM_WORD_REGISTER(rl);
+		DECODE_PRINTF("\n");
+		TRACE_AND_STEP();
+		push_word(*destreg);
+	    }
+	    break;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/***************************************************************************
+ * Single byte operation code table:
+ **************************************************************************/
+void (*x86emu_optab[256])(u8) =
+{
+/*  0x00 */ x86emuOp_add_byte_RM_R,
+/*  0x01 */ x86emuOp_add_word_RM_R,
+/*  0x02 */ x86emuOp_add_byte_R_RM,
+/*  0x03 */ x86emuOp_add_word_R_RM,
+/*  0x04 */ x86emuOp_add_byte_AL_IMM,
+/*  0x05 */ x86emuOp_add_word_AX_IMM,
+/*  0x06 */ x86emuOp_push_ES,
+/*  0x07 */ x86emuOp_pop_ES,
+
+/*  0x08 */ x86emuOp_or_byte_RM_R,
+/*  0x09 */ x86emuOp_or_word_RM_R,
+/*  0x0a */ x86emuOp_or_byte_R_RM,
+/*  0x0b */ x86emuOp_or_word_R_RM,
+/*  0x0c */ x86emuOp_or_byte_AL_IMM,
+/*  0x0d */ x86emuOp_or_word_AX_IMM,
+/*  0x0e */ x86emuOp_push_CS,
+/*  0x0f */ x86emuOp_two_byte,
+
+/*  0x10 */ x86emuOp_adc_byte_RM_R,
+/*  0x11 */ x86emuOp_adc_word_RM_R,
+/*  0x12 */ x86emuOp_adc_byte_R_RM,
+/*  0x13 */ x86emuOp_adc_word_R_RM,
+/*  0x14 */ x86emuOp_adc_byte_AL_IMM,
+/*  0x15 */ x86emuOp_adc_word_AX_IMM,
+/*  0x16 */ x86emuOp_push_SS,
+/*  0x17 */ x86emuOp_pop_SS,
+
+/*  0x18 */ x86emuOp_sbb_byte_RM_R,
+/*  0x19 */ x86emuOp_sbb_word_RM_R,
+/*  0x1a */ x86emuOp_sbb_byte_R_RM,
+/*  0x1b */ x86emuOp_sbb_word_R_RM,
+/*  0x1c */ x86emuOp_sbb_byte_AL_IMM,
+/*  0x1d */ x86emuOp_sbb_word_AX_IMM,
+/*  0x1e */ x86emuOp_push_DS,
+/*  0x1f */ x86emuOp_pop_DS,
+
+/*  0x20 */ x86emuOp_and_byte_RM_R,
+/*  0x21 */ x86emuOp_and_word_RM_R,
+/*  0x22 */ x86emuOp_and_byte_R_RM,
+/*  0x23 */ x86emuOp_and_word_R_RM,
+/*  0x24 */ x86emuOp_and_byte_AL_IMM,
+/*  0x25 */ x86emuOp_and_word_AX_IMM,
+/*  0x26 */ x86emuOp_segovr_ES,
+/*  0x27 */ x86emuOp_daa,
+
+/*  0x28 */ x86emuOp_sub_byte_RM_R,
+/*  0x29 */ x86emuOp_sub_word_RM_R,
+/*  0x2a */ x86emuOp_sub_byte_R_RM,
+/*  0x2b */ x86emuOp_sub_word_R_RM,
+/*  0x2c */ x86emuOp_sub_byte_AL_IMM,
+/*  0x2d */ x86emuOp_sub_word_AX_IMM,
+/*  0x2e */ x86emuOp_segovr_CS,
+/*  0x2f */ x86emuOp_das,
+
+/*  0x30 */ x86emuOp_xor_byte_RM_R,
+/*  0x31 */ x86emuOp_xor_word_RM_R,
+/*  0x32 */ x86emuOp_xor_byte_R_RM,
+/*  0x33 */ x86emuOp_xor_word_R_RM,
+/*  0x34 */ x86emuOp_xor_byte_AL_IMM,
+/*  0x35 */ x86emuOp_xor_word_AX_IMM,
+/*  0x36 */ x86emuOp_segovr_SS,
+/*  0x37 */ x86emuOp_aaa,
+
+/*  0x38 */ x86emuOp_cmp_byte_RM_R,
+/*  0x39 */ x86emuOp_cmp_word_RM_R,
+/*  0x3a */ x86emuOp_cmp_byte_R_RM,
+/*  0x3b */ x86emuOp_cmp_word_R_RM,
+/*  0x3c */ x86emuOp_cmp_byte_AL_IMM,
+/*  0x3d */ x86emuOp_cmp_word_AX_IMM,
+/*  0x3e */ x86emuOp_segovr_DS,
+/*  0x3f */ x86emuOp_aas,
+
+/*  0x40 */ x86emuOp_inc_AX,
+/*  0x41 */ x86emuOp_inc_CX,
+/*  0x42 */ x86emuOp_inc_DX,
+/*  0x43 */ x86emuOp_inc_BX,
+/*  0x44 */ x86emuOp_inc_SP,
+/*  0x45 */ x86emuOp_inc_BP,
+/*  0x46 */ x86emuOp_inc_SI,
+/*  0x47 */ x86emuOp_inc_DI,
+
+/*  0x48 */ x86emuOp_dec_AX,
+/*  0x49 */ x86emuOp_dec_CX,
+/*  0x4a */ x86emuOp_dec_DX,
+/*  0x4b */ x86emuOp_dec_BX,
+/*  0x4c */ x86emuOp_dec_SP,
+/*  0x4d */ x86emuOp_dec_BP,
+/*  0x4e */ x86emuOp_dec_SI,
+/*  0x4f */ x86emuOp_dec_DI,
+
+/*  0x50 */ x86emuOp_push_AX,
+/*  0x51 */ x86emuOp_push_CX,
+/*  0x52 */ x86emuOp_push_DX,
+/*  0x53 */ x86emuOp_push_BX,
+/*  0x54 */ x86emuOp_push_SP,
+/*  0x55 */ x86emuOp_push_BP,
+/*  0x56 */ x86emuOp_push_SI,
+/*  0x57 */ x86emuOp_push_DI,
+
+/*  0x58 */ x86emuOp_pop_AX,
+/*  0x59 */ x86emuOp_pop_CX,
+/*  0x5a */ x86emuOp_pop_DX,
+/*  0x5b */ x86emuOp_pop_BX,
+/*  0x5c */ x86emuOp_pop_SP,
+/*  0x5d */ x86emuOp_pop_BP,
+/*  0x5e */ x86emuOp_pop_SI,
+/*  0x5f */ x86emuOp_pop_DI,
+
+/*  0x60 */ x86emuOp_push_all,
+/*  0x61 */ x86emuOp_pop_all,
+/*  0x62 */ x86emuOp_illegal_op,   /* bound */
+/*  0x63 */ x86emuOp_illegal_op,   /* arpl */
+/*  0x64 */ x86emuOp_segovr_FS,
+/*  0x65 */ x86emuOp_segovr_GS,
+/*  0x66 */ x86emuOp_prefix_data,
+/*  0x67 */ x86emuOp_prefix_addr,
+
+/*  0x68 */ x86emuOp_push_word_IMM,
+/*  0x69 */ x86emuOp_imul_word_IMM,
+/*  0x6a */ x86emuOp_push_byte_IMM,
+/*  0x6b */ x86emuOp_imul_byte_IMM,
+/*  0x6c */ x86emuOp_ins_byte,
+/*  0x6d */ x86emuOp_ins_word,
+/*  0x6e */ x86emuOp_outs_byte,
+/*  0x6f */ x86emuOp_outs_word,
+
+/*  0x70 */ x86emuOp_jump_near_O,
+/*  0x71 */ x86emuOp_jump_near_NO,
+/*  0x72 */ x86emuOp_jump_near_B,
+/*  0x73 */ x86emuOp_jump_near_NB,
+/*  0x74 */ x86emuOp_jump_near_Z,
+/*  0x75 */ x86emuOp_jump_near_NZ,
+/*  0x76 */ x86emuOp_jump_near_BE,
+/*  0x77 */ x86emuOp_jump_near_NBE,
+
+/*  0x78 */ x86emuOp_jump_near_S,
+/*  0x79 */ x86emuOp_jump_near_NS,
+/*  0x7a */ x86emuOp_jump_near_P,
+/*  0x7b */ x86emuOp_jump_near_NP,
+/*  0x7c */ x86emuOp_jump_near_L,
+/*  0x7d */ x86emuOp_jump_near_NL,
+/*  0x7e */ x86emuOp_jump_near_LE,
+/*  0x7f */ x86emuOp_jump_near_NLE,
+
+/*  0x80 */ x86emuOp_opc80_byte_RM_IMM,
+/*  0x81 */ x86emuOp_opc81_word_RM_IMM,
+/*  0x82 */ x86emuOp_opc82_byte_RM_IMM,
+/*  0x83 */ x86emuOp_opc83_word_RM_IMM,
+/*  0x84 */ x86emuOp_test_byte_RM_R,
+/*  0x85 */ x86emuOp_test_word_RM_R,
+/*  0x86 */ x86emuOp_xchg_byte_RM_R,
+/*  0x87 */ x86emuOp_xchg_word_RM_R,
+
+/*  0x88 */ x86emuOp_mov_byte_RM_R,
+/*  0x89 */ x86emuOp_mov_word_RM_R,
+/*  0x8a */ x86emuOp_mov_byte_R_RM,
+/*  0x8b */ x86emuOp_mov_word_R_RM,
+/*  0x8c */ x86emuOp_mov_word_RM_SR,
+/*  0x8d */ x86emuOp_lea_word_R_M,
+/*  0x8e */ x86emuOp_mov_word_SR_RM,
+/*  0x8f */ x86emuOp_pop_RM,
+
+/*  0x90 */ x86emuOp_nop,
+/*  0x91 */ x86emuOp_xchg_word_AX_CX,
+/*  0x92 */ x86emuOp_xchg_word_AX_DX,
+/*  0x93 */ x86emuOp_xchg_word_AX_BX,
+/*  0x94 */ x86emuOp_xchg_word_AX_SP,
+/*  0x95 */ x86emuOp_xchg_word_AX_BP,
+/*  0x96 */ x86emuOp_xchg_word_AX_SI,
+/*  0x97 */ x86emuOp_xchg_word_AX_DI,
+
+/*  0x98 */ x86emuOp_cbw,
+/*  0x99 */ x86emuOp_cwd,
+/*  0x9a */ x86emuOp_call_far_IMM,
+/*  0x9b */ x86emuOp_wait,
+/*  0x9c */ x86emuOp_pushf_word,
+/*  0x9d */ x86emuOp_popf_word,
+/*  0x9e */ x86emuOp_sahf,
+/*  0x9f */ x86emuOp_lahf,
+
+/*  0xa0 */ x86emuOp_mov_AL_M_IMM,
+/*  0xa1 */ x86emuOp_mov_AX_M_IMM,
+/*  0xa2 */ x86emuOp_mov_M_AL_IMM,
+/*  0xa3 */ x86emuOp_mov_M_AX_IMM,
+/*  0xa4 */ x86emuOp_movs_byte,
+/*  0xa5 */ x86emuOp_movs_word,
+/*  0xa6 */ x86emuOp_cmps_byte,
+/*  0xa7 */ x86emuOp_cmps_word,
+/*  0xa8 */ x86emuOp_test_AL_IMM,
+/*  0xa9 */ x86emuOp_test_AX_IMM,
+/*  0xaa */ x86emuOp_stos_byte,
+/*  0xab */ x86emuOp_stos_word,
+/*  0xac */ x86emuOp_lods_byte,
+/*  0xad */ x86emuOp_lods_word,
+/*  0xac */ x86emuOp_scas_byte,
+/*  0xad */ x86emuOp_scas_word,
+
+
+/*  0xb0 */ x86emuOp_mov_byte_AL_IMM,
+/*  0xb1 */ x86emuOp_mov_byte_CL_IMM,
+/*  0xb2 */ x86emuOp_mov_byte_DL_IMM,
+/*  0xb3 */ x86emuOp_mov_byte_BL_IMM,
+/*  0xb4 */ x86emuOp_mov_byte_AH_IMM,
+/*  0xb5 */ x86emuOp_mov_byte_CH_IMM,
+/*  0xb6 */ x86emuOp_mov_byte_DH_IMM,
+/*  0xb7 */ x86emuOp_mov_byte_BH_IMM,
+
+/*  0xb8 */ x86emuOp_mov_word_AX_IMM,
+/*  0xb9 */ x86emuOp_mov_word_CX_IMM,
+/*  0xba */ x86emuOp_mov_word_DX_IMM,
+/*  0xbb */ x86emuOp_mov_word_BX_IMM,
+/*  0xbc */ x86emuOp_mov_word_SP_IMM,
+/*  0xbd */ x86emuOp_mov_word_BP_IMM,
+/*  0xbe */ x86emuOp_mov_word_SI_IMM,
+/*  0xbf */ x86emuOp_mov_word_DI_IMM,
+
+/*  0xc0 */ x86emuOp_opcC0_byte_RM_MEM,
+/*  0xc1 */ x86emuOp_opcC1_word_RM_MEM,
+/*  0xc2 */ x86emuOp_ret_near_IMM,
+/*  0xc3 */ x86emuOp_ret_near,
+/*  0xc4 */ x86emuOp_les_R_IMM,
+/*  0xc5 */ x86emuOp_lds_R_IMM,
+/*  0xc6 */ x86emuOp_mov_byte_RM_IMM,
+/*  0xc7 */ x86emuOp_mov_word_RM_IMM,
+/*  0xc8 */ x86emuOp_enter,
+/*  0xc9 */ x86emuOp_leave,
+/*  0xca */ x86emuOp_ret_far_IMM,
+/*  0xcb */ x86emuOp_ret_far,
+/*  0xcc */ x86emuOp_int3,
+/*  0xcd */ x86emuOp_int_IMM,
+/*  0xce */ x86emuOp_into,
+/*  0xcf */ x86emuOp_iret,
+
+/*  0xd0 */ x86emuOp_opcD0_byte_RM_1,
+/*  0xd1 */ x86emuOp_opcD1_word_RM_1,
+/*  0xd2 */ x86emuOp_opcD2_byte_RM_CL,
+/*  0xd3 */ x86emuOp_opcD3_word_RM_CL,
+/*  0xd4 */ x86emuOp_aam,
+/*  0xd5 */ x86emuOp_aad,
+/*  0xd6 */ x86emuOp_illegal_op,   /* Undocumented SETALC instruction */
+/*  0xd7 */ x86emuOp_xlat,
+/*  0xd8 */ x86emuOp_esc_coprocess_d8,
+/*  0xd9 */ x86emuOp_esc_coprocess_d9,
+/*  0xda */ x86emuOp_esc_coprocess_da,
+/*  0xdb */ x86emuOp_esc_coprocess_db,
+/*  0xdc */ x86emuOp_esc_coprocess_dc,
+/*  0xdd */ x86emuOp_esc_coprocess_dd,
+/*  0xde */ x86emuOp_esc_coprocess_de,
+/*  0xdf */ x86emuOp_esc_coprocess_df,
+
+/*  0xe0 */ x86emuOp_loopne,
+/*  0xe1 */ x86emuOp_loope,
+/*  0xe2 */ x86emuOp_loop,
+/*  0xe3 */ x86emuOp_jcxz,
+/*  0xe4 */ x86emuOp_in_byte_AL_IMM,
+/*  0xe5 */ x86emuOp_in_word_AX_IMM,
+/*  0xe6 */ x86emuOp_out_byte_IMM_AL,
+/*  0xe7 */ x86emuOp_out_word_IMM_AX,
+
+/*  0xe8 */ x86emuOp_call_near_IMM,
+/*  0xe9 */ x86emuOp_jump_near_IMM,
+/*  0xea */ x86emuOp_jump_far_IMM,
+/*  0xeb */ x86emuOp_jump_byte_IMM,
+/*  0xec */ x86emuOp_in_byte_AL_DX,
+/*  0xed */ x86emuOp_in_word_AX_DX,
+/*  0xee */ x86emuOp_out_byte_DX_AL,
+/*  0xef */ x86emuOp_out_word_DX_AX,
+
+/*  0xf0 */ x86emuOp_lock,
+/*  0xf1 */ x86emuOp_illegal_op,
+/*  0xf2 */ x86emuOp_repne,
+/*  0xf3 */ x86emuOp_repe,
+/*  0xf4 */ x86emuOp_halt,
+/*  0xf5 */ x86emuOp_cmc,
+/*  0xf6 */ x86emuOp_opcF6_byte_RM,
+/*  0xf7 */ x86emuOp_opcF7_word_RM,
+
+/*  0xf8 */ x86emuOp_clc,
+/*  0xf9 */ x86emuOp_stc,
+/*  0xfa */ x86emuOp_cli,
+/*  0xfb */ x86emuOp_sti,
+/*  0xfc */ x86emuOp_cld,
+/*  0xfd */ x86emuOp_std,
+/*  0xfe */ x86emuOp_opcFE_byte_RM,
+/*  0xff */ x86emuOp_opcFF_word_RM,
+};
+
+void tables_relocate(unsigned int offset)
+{
+    int i;
+    for (i=0; i<8; i++)
+    {
+	opc80_byte_operation[i] -= offset;
+	opc81_word_operation[i] -= offset;
+	opc81_long_operation[i] -= offset;
+
+	opc82_byte_operation[i] -= offset;
+	opc83_word_operation[i] -= offset;
+	opc83_long_operation[i] -= offset;
+
+	opcD0_byte_operation[i] -= offset;
+	opcD1_word_operation[i] -= offset;
+	opcD1_long_operation[i] -= offset;
+    }
+}
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c b/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c
new file mode 100755
index 0000000..d381307
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c
@@ -0,0 +1,2800 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  This file includes subroutines to implement the decoding
+*               and emulation of all the x86 extended two-byte processor
+*               instructions.
+*
+****************************************************************************/
+
+#include "x86emu/x86emui.h"
+
+/*----------------------------- Implementation ----------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+op1 - Instruction op code
+
+REMARKS:
+Handles illegal opcodes.
+****************************************************************************/
+void x86emuOp2_illegal_op(
+	u8 op2)
+{
+	START_OF_INSTR();
+	DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
+	TRACE_REGS();
+	printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
+		M.x86.R_CS, M.x86.R_IP-2,op2);
+    HALT_SYS();
+    END_OF_INSTR();
+}
+
+#define xorl(a,b)   ((a) && !(b)) || (!(a) && (b))
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0x80-0x8F
+****************************************************************************/
+void x86emuOp2_long_jump(u8 op2)
+{
+    s32 target;
+    char *name = 0;
+    int cond = 0;
+
+    /* conditional jump to word offset. */
+    START_OF_INSTR();
+    switch (op2) {
+      case 0x80:
+	name = "JO\t";
+	cond =  ACCESS_FLAG(F_OF);
+	break;
+      case 0x81:
+	name = "JNO\t";
+	cond = !ACCESS_FLAG(F_OF);
+	break;
+      case 0x82:
+	name = "JB\t";
+	cond = ACCESS_FLAG(F_CF);
+	break;
+      case 0x83:
+	name = "JNB\t";
+	cond = !ACCESS_FLAG(F_CF);
+	break;
+      case 0x84:
+	name = "JZ\t";
+	cond = ACCESS_FLAG(F_ZF);
+	break;
+      case 0x85:
+	name = "JNZ\t";
+	cond = !ACCESS_FLAG(F_ZF);
+	break;
+      case 0x86:
+	name = "JBE\t";
+	cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
+	break;
+      case 0x87:
+	name = "JNBE\t";
+	cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
+	break;
+      case 0x88:
+	name = "JS\t";
+	cond = ACCESS_FLAG(F_SF);
+	break;
+      case 0x89:
+	name = "JNS\t";
+	cond = !ACCESS_FLAG(F_SF);
+	break;
+      case 0x8a:
+	name = "JP\t";
+	cond = ACCESS_FLAG(F_PF);
+	break;
+      case 0x8b:
+	name = "JNP\t";
+	cond = !ACCESS_FLAG(F_PF);
+	break;
+      case 0x8c:
+	name = "JL\t";
+	cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
+	break;
+      case 0x8d:
+	name = "JNL\t";
+	cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
+	break;
+      case 0x8e:
+	name = "JLE\t";
+	cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
+		ACCESS_FLAG(F_ZF));
+	break;
+      case 0x8f:
+	name = "JNLE\t";
+	cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
+		 ACCESS_FLAG(F_ZF));
+	break;
+    }
+    DECODE_PRINTF(name);
+    target = (s16) fetch_word_imm();
+    target += (s16) M.x86.R_IP;
+    DECODE_PRINTF2("%04x\n", target);
+    TRACE_AND_STEP();
+    if (cond)
+	M.x86.R_IP = (u16)target;
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0x90-0x9F
+****************************************************************************/
+void x86emuOp2_set_byte(u8 op2)
+{
+    int mod, rl, rh;
+    uint destoffset;
+    u8  *destreg;
+    char *name = 0;
+    int cond = 0;
+
+    START_OF_INSTR();
+    switch (op2) {
+      case 0x90:
+	name = "SETO\t";
+	cond =  ACCESS_FLAG(F_OF);
+	break;
+      case 0x91:
+	name = "SETNO\t";
+	cond = !ACCESS_FLAG(F_OF);
+	break;
+      case 0x92:
+	name = "SETB\t";
+	cond = ACCESS_FLAG(F_CF);
+	break;
+      case 0x93:
+	name = "SETNB\t";
+	cond = !ACCESS_FLAG(F_CF);
+	break;
+      case 0x94:
+	name = "SETZ\t";
+	cond = ACCESS_FLAG(F_ZF);
+	break;
+      case 0x95:
+	name = "SETNZ\t";
+	cond = !ACCESS_FLAG(F_ZF);
+	break;
+      case 0x96:
+	name = "SETBE\t";
+	cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
+	break;
+      case 0x97:
+	name = "SETNBE\t";
+	cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
+	break;
+      case 0x98:
+	name = "SETS\t";
+	cond = ACCESS_FLAG(F_SF);
+	break;
+      case 0x99:
+	name = "SETNS\t";
+	cond = !ACCESS_FLAG(F_SF);
+	break;
+      case 0x9a:
+	name = "SETP\t";
+	cond = ACCESS_FLAG(F_PF);
+	break;
+      case 0x9b:
+	name = "SETNP\t";
+	cond = !ACCESS_FLAG(F_PF);
+	break;
+      case 0x9c:
+	name = "SETL\t";
+	cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
+	break;
+      case 0x9d:
+	name = "SETNL\t";
+	cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
+	break;
+      case 0x9e:
+	name = "SETLE\t";
+	cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
+		ACCESS_FLAG(F_ZF));
+	break;
+      case 0x9f:
+	name = "SETNLE\t";
+	cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
+		 ACCESS_FLAG(F_ZF));
+	break;
+    }
+    DECODE_PRINTF(name);
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destoffset = decode_rm00_address(rl);
+	TRACE_AND_STEP();
+	store_data_byte(destoffset, cond ? 0x01 : 0x00);
+	break;
+    case 1:
+	destoffset = decode_rm01_address(rl);
+	TRACE_AND_STEP();
+	store_data_byte(destoffset, cond ? 0x01 : 0x00);
+	break;
+    case 2:
+	destoffset = decode_rm10_address(rl);
+	TRACE_AND_STEP();
+	store_data_byte(destoffset, cond ? 0x01 : 0x00);
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_BYTE_REGISTER(rl);
+	TRACE_AND_STEP();
+	*destreg = cond ? 0x01 : 0x00;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xa0
+****************************************************************************/
+void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("PUSH\tFS\n");
+    TRACE_AND_STEP();
+    push_word(M.x86.R_FS);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xa1
+****************************************************************************/
+void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("POP\tFS\n");
+    TRACE_AND_STEP();
+    M.x86.R_FS = pop_word();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xa3
+****************************************************************************/
+void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+    int bit,disp;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("BT\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval;
+	    u32 *shiftreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    disp = (s16)*shiftreg >> 5;
+	    srcval = fetch_data_long(srcoffset+disp);
+	    CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
+	} else {
+	    u16 srcval;
+	    u16 *shiftreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0xF;
+	    disp = (s16)*shiftreg >> 4;
+	    srcval = fetch_data_word(srcoffset+disp);
+	    CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval;
+	    u32 *shiftreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    disp = (s16)*shiftreg >> 5;
+	    srcval = fetch_data_long(srcoffset+disp);
+	    CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
+	} else {
+	    u16 srcval;
+	    u16 *shiftreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0xF;
+	    disp = (s16)*shiftreg >> 4;
+	    srcval = fetch_data_word(srcoffset+disp);
+	    CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval;
+	    u32 *shiftreg;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    disp = (s16)*shiftreg >> 5;
+	    srcval = fetch_data_long(srcoffset+disp);
+	    CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
+	} else {
+	    u16 srcval;
+	    u16 *shiftreg;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0xF;
+	    disp = (s16)*shiftreg >> 4;
+	    srcval = fetch_data_word(srcoffset+disp);
+	    CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg,*shiftreg;
+
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
+	} else {
+	    u16 *srcreg,*shiftreg;
+
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0xF;
+	    CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xa4
+****************************************************************************/
+void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint destoffset;
+	u8 shift;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SHLD\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shld_long(destval,*shiftreg,shift);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shld_word(destval,*shiftreg,shift);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shld_long(destval,*shiftreg,shift);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shld_word(destval,*shiftreg,shift);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shld_long(destval,*shiftreg,shift);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shld_word(destval,*shiftreg,shift);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*shiftreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    *destreg = shld_long(*destreg,*shiftreg,shift);
+	} else {
+	    u16 *destreg,*shiftreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    *destreg = shld_word(*destreg,*shiftreg,shift);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xa5
+****************************************************************************/
+void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SHLD\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shld_long(destval,*shiftreg,M.x86.R_CL);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shld_word(destval,*shiftreg,M.x86.R_CL);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shld_long(destval,*shiftreg,M.x86.R_CL);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shld_word(destval,*shiftreg,M.x86.R_CL);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shld_long(destval,*shiftreg,M.x86.R_CL);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shld_word(destval,*shiftreg,M.x86.R_CL);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*shiftreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL);
+	} else {
+	    u16 *destreg,*shiftreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xa8
+****************************************************************************/
+void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("PUSH\tGS\n");
+    TRACE_AND_STEP();
+    push_word(M.x86.R_GS);
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xa9
+****************************************************************************/
+void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2))
+{
+    START_OF_INSTR();
+    DECODE_PRINTF("POP\tGS\n");
+    TRACE_AND_STEP();
+    M.x86.R_GS = pop_word();
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xaa
+****************************************************************************/
+void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+    int bit,disp;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("BTS\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval,mask;
+	    u32 *shiftreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    disp = (s16)*shiftreg >> 5;
+	    srcval = fetch_data_long(srcoffset+disp);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    store_data_long(srcoffset+disp, srcval | mask);
+	} else {
+	    u16 srcval,mask;
+	    u16 *shiftreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0xF;
+	    disp = (s16)*shiftreg >> 4;
+	    srcval = fetch_data_word(srcoffset+disp);
+			mask = (u16)(0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    store_data_word(srcoffset+disp, srcval | mask);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval,mask;
+	    u32 *shiftreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    disp = (s16)*shiftreg >> 5;
+	    srcval = fetch_data_long(srcoffset+disp);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    store_data_long(srcoffset+disp, srcval | mask);
+	} else {
+	    u16 srcval,mask;
+	    u16 *shiftreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0xF;
+	    disp = (s16)*shiftreg >> 4;
+	    srcval = fetch_data_word(srcoffset+disp);
+			mask = (u16)(0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    store_data_word(srcoffset+disp, srcval | mask);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval,mask;
+	    u32 *shiftreg;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    disp = (s16)*shiftreg >> 5;
+	    srcval = fetch_data_long(srcoffset+disp);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    store_data_long(srcoffset+disp, srcval | mask);
+	} else {
+	    u16 srcval,mask;
+	    u16 *shiftreg;
+
+			srcoffset = decode_rm10_address(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_WORD_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0xF;
+			disp = (s16)*shiftreg >> 4;
+			srcval = fetch_data_word(srcoffset+disp);
+			mask = (u16)(0x1 << bit);
+			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_word(srcoffset+disp, srcval | mask);
+		}
+		break;
+	case 3:                     /* register to register */
+		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			u32 *srcreg,*shiftreg;
+			u32 mask;
+
+			srcreg = DECODE_RM_LONG_REGISTER(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_LONG_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0x1F;
+			mask = (0x1 << bit);
+			CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+			*srcreg |= mask;
+		} else {
+			u16 *srcreg,*shiftreg;
+			u16 mask;
+
+			srcreg = DECODE_RM_WORD_REGISTER(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_WORD_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0xF;
+			mask = (u16)(0x1 << bit);
+	    CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+	    *srcreg |= mask;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xac
+****************************************************************************/
+void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint destoffset;
+	u8 shift;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SHLD\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shrd_long(destval,*shiftreg,shift);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shrd_word(destval,*shiftreg,shift);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shrd_long(destval,*shiftreg,shift);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shrd_word(destval,*shiftreg,shift);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shrd_long(destval,*shiftreg,shift);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shrd_word(destval,*shiftreg,shift);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*shiftreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    *destreg = shrd_long(*destreg,*shiftreg,shift);
+	} else {
+	    u16 *destreg,*shiftreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    DECODE_PRINTF2("%d\n", shift);
+	    TRACE_AND_STEP();
+	    *destreg = shrd_word(*destreg,*shiftreg,shift);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xad
+****************************************************************************/
+void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint destoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("SHLD\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 destval;
+	    u32 *shiftreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_long(destoffset);
+	    destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
+	    store_data_long(destoffset, destval);
+	} else {
+	    u16 destval;
+	    u16 *shiftreg;
+
+	    destoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    destval = fetch_data_word(destoffset);
+	    destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
+	    store_data_word(destoffset, destval);
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*shiftreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL);
+	} else {
+	    u16 *destreg,*shiftreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",CL\n");
+	    TRACE_AND_STEP();
+	    *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xaf
+****************************************************************************/
+void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("IMUL\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+	    u32 res_lo,res_hi;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+	    u32 res;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    TRACE_AND_STEP();
+	    res = (s16)*destreg * (s16)srcval;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+	    u32 res_lo,res_hi;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+	    u32 res;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    TRACE_AND_STEP();
+	    res = (s16)*destreg * (s16)srcval;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+	    u32 res_lo,res_hi;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_long(srcoffset);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+	    u32 res;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_word(srcoffset);
+	    TRACE_AND_STEP();
+	    res = (s16)*destreg * (s16)srcval;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg,*srcreg;
+	    u32 res_lo,res_hi;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    TRACE_AND_STEP();
+	    imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg);
+	    if (res_hi != 0) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u32)res_lo;
+	} else {
+	    u16 *destreg,*srcreg;
+	    u32 res;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    res = (s16)*destreg * (s16)*srcreg;
+	    if (res > 0xFFFF) {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	    } else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	    }
+	    *destreg = (u16)res;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xb2
+****************************************************************************/
+void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2))
+{
+	int mod, rh, rl;
+    u16 *dstreg;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LSS\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_SS = fetch_data_word(srcoffset + 2);
+	break;
+    case 1:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_SS = fetch_data_word(srcoffset + 2);
+	break;
+    case 2:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_SS = fetch_data_word(srcoffset + 2);
+	break;
+    case 3:                     /* register to register */
+	/* UNDEFINED! */
+	TRACE_AND_STEP();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xb3
+****************************************************************************/
+void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2))
+{
+	int mod, rl, rh;
+	uint srcoffset;
+	int bit,disp;
+
+	START_OF_INSTR();
+	DECODE_PRINTF("BTR\t");
+	FETCH_DECODE_MODRM(mod, rh, rl);
+	switch (mod) {
+	case 0:
+		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			u32 srcval,mask;
+			u32 *shiftreg;
+
+			srcoffset = decode_rm00_address(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_LONG_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0x1F;
+			disp = (s16)*shiftreg >> 5;
+			srcval = fetch_data_long(srcoffset+disp);
+			mask = (0x1 << bit);
+			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_long(srcoffset+disp, srcval & ~mask);
+		} else {
+			u16 srcval,mask;
+			u16 *shiftreg;
+
+			srcoffset = decode_rm00_address(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_WORD_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0xF;
+			disp = (s16)*shiftreg >> 4;
+			srcval = fetch_data_word(srcoffset+disp);
+			mask = (u16)(0x1 << bit);
+			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
+		}
+		break;
+	case 1:
+		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			u32 srcval,mask;
+			u32 *shiftreg;
+
+			srcoffset = decode_rm01_address(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_LONG_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0x1F;
+			disp = (s16)*shiftreg >> 5;
+			srcval = fetch_data_long(srcoffset+disp);
+			mask = (0x1 << bit);
+			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_long(srcoffset+disp, srcval & ~mask);
+		} else {
+			u16 srcval,mask;
+			u16 *shiftreg;
+
+			srcoffset = decode_rm01_address(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_WORD_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0xF;
+			disp = (s16)*shiftreg >> 4;
+			srcval = fetch_data_word(srcoffset+disp);
+			mask = (u16)(0x1 << bit);
+			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
+		}
+		break;
+	case 2:
+		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			u32 srcval,mask;
+			u32 *shiftreg;
+
+			srcoffset = decode_rm10_address(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_LONG_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0x1F;
+			disp = (s16)*shiftreg >> 5;
+			srcval = fetch_data_long(srcoffset+disp);
+			mask = (0x1 << bit);
+			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_long(srcoffset+disp, srcval & ~mask);
+		} else {
+			u16 srcval,mask;
+			u16 *shiftreg;
+
+			srcoffset = decode_rm10_address(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_WORD_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0xF;
+			disp = (s16)*shiftreg >> 4;
+			srcval = fetch_data_word(srcoffset+disp);
+			mask = (u16)(0x1 << bit);
+			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
+		}
+		break;
+	case 3:                     /* register to register */
+		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			u32 *srcreg,*shiftreg;
+			u32 mask;
+
+			srcreg = DECODE_RM_LONG_REGISTER(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_LONG_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0x1F;
+			mask = (0x1 << bit);
+			CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+			*srcreg &= ~mask;
+		} else {
+			u16 *srcreg,*shiftreg;
+			u16 mask;
+
+			srcreg = DECODE_RM_WORD_REGISTER(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_WORD_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0xF;
+			mask = (u16)(0x1 << bit);
+			CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+			*srcreg &= ~mask;
+		}
+		break;
+	}
+	DECODE_CLEAR_SEGOVR();
+	END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xb4
+****************************************************************************/
+void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2))
+{
+	int mod, rh, rl;
+    u16 *dstreg;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LFS\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_FS = fetch_data_word(srcoffset + 2);
+	break;
+    case 1:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_FS = fetch_data_word(srcoffset + 2);
+	break;
+    case 2:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_FS = fetch_data_word(srcoffset + 2);
+	break;
+    case 3:                     /* register to register */
+	/* UNDEFINED! */
+	TRACE_AND_STEP();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xb5
+****************************************************************************/
+void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2))
+{
+	int mod, rh, rl;
+    u16 *dstreg;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("LGS\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_GS = fetch_data_word(srcoffset + 2);
+	break;
+    case 1:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_GS = fetch_data_word(srcoffset + 2);
+	break;
+    case 2:
+	dstreg = DECODE_RM_WORD_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*dstreg = fetch_data_word(srcoffset);
+	M.x86.R_GS = fetch_data_word(srcoffset + 2);
+	break;
+    case 3:                     /* register to register */
+	/* UNDEFINED! */
+	TRACE_AND_STEP();
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xb6
+****************************************************************************/
+void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOVZX\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_byte(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = fetch_data_byte(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_byte(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = fetch_data_byte(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_byte(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = fetch_data_byte(srcoffset);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u8  *srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = *srcreg;
+	} else {
+	    u16 *destreg;
+	    u8  *srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = *srcreg;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xb7
+****************************************************************************/
+void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+    u32 *destreg;
+    u32 srcval;
+    u16 *srcreg;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOVZX\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_LONG_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = fetch_data_word(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 1:
+	destreg = DECODE_RM_LONG_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = fetch_data_word(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 2:
+	destreg = DECODE_RM_LONG_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = fetch_data_word(srcoffset);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_LONG_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_WORD_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = *srcreg;
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xba
+****************************************************************************/
+void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+    int bit;
+
+    START_OF_INSTR();
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (rh) {
+    case 3:
+	DECODE_PRINTF("BT\t");
+	break;
+    case 4:
+	DECODE_PRINTF("BTS\t");
+	break;
+    case 5:
+	DECODE_PRINTF("BTR\t");
+	break;
+    case 6:
+	DECODE_PRINTF("BTC\t");
+	break;
+    default:
+	DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
+	TRACE_REGS();
+	printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n",
+		M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl);
+	HALT_SYS();
+    }
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval, mask;
+	    u8 shift;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    TRACE_AND_STEP();
+	    bit = shift & 0x1F;
+	    srcval = fetch_data_long(srcoffset);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    switch (rh) {
+	    case 4:
+		store_data_long(srcoffset, srcval | mask);
+		break;
+	    case 5:
+		store_data_long(srcoffset, srcval & ~mask);
+		break;
+	    case 6:
+		store_data_long(srcoffset, srcval ^ mask);
+		break;
+	    default:
+		break;
+	    }
+	} else {
+	    u16 srcval, mask;
+	    u8 shift;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    TRACE_AND_STEP();
+	    bit = shift & 0xF;
+	    srcval = fetch_data_word(srcoffset);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    switch (rh) {
+	    case 4:
+		store_data_word(srcoffset, srcval | mask);
+		break;
+	    case 5:
+		store_data_word(srcoffset, srcval & ~mask);
+		break;
+	    case 6:
+		store_data_word(srcoffset, srcval ^ mask);
+		break;
+	    default:
+		break;
+	    }
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval, mask;
+	    u8 shift;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    TRACE_AND_STEP();
+	    bit = shift & 0x1F;
+	    srcval = fetch_data_long(srcoffset);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    switch (rh) {
+	    case 4:
+		store_data_long(srcoffset, srcval | mask);
+		break;
+	    case 5:
+		store_data_long(srcoffset, srcval & ~mask);
+		break;
+	    case 6:
+		store_data_long(srcoffset, srcval ^ mask);
+		break;
+	    default:
+		break;
+	    }
+	} else {
+	    u16 srcval, mask;
+	    u8 shift;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    TRACE_AND_STEP();
+	    bit = shift & 0xF;
+	    srcval = fetch_data_word(srcoffset);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    switch (rh) {
+	    case 4:
+		store_data_word(srcoffset, srcval | mask);
+		break;
+	    case 5:
+		store_data_word(srcoffset, srcval & ~mask);
+		break;
+	    case 6:
+		store_data_word(srcoffset, srcval ^ mask);
+		break;
+	    default:
+		break;
+	    }
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval, mask;
+	    u8 shift;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    TRACE_AND_STEP();
+	    bit = shift & 0x1F;
+	    srcval = fetch_data_long(srcoffset);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    switch (rh) {
+	    case 4:
+		store_data_long(srcoffset, srcval | mask);
+		break;
+	    case 5:
+		store_data_long(srcoffset, srcval & ~mask);
+		break;
+	    case 6:
+		store_data_long(srcoffset, srcval ^ mask);
+		break;
+	    default:
+		break;
+	    }
+	} else {
+	    u16 srcval, mask;
+	    u8 shift;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    TRACE_AND_STEP();
+	    bit = shift & 0xF;
+	    srcval = fetch_data_word(srcoffset);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    switch (rh) {
+	    case 4:
+		store_data_word(srcoffset, srcval | mask);
+		break;
+	    case 5:
+		store_data_word(srcoffset, srcval & ~mask);
+		break;
+	    case 6:
+		store_data_word(srcoffset, srcval ^ mask);
+		break;
+	    default:
+		break;
+	    }
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg;
+	    u32 mask;
+	    u8 shift;
+
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    TRACE_AND_STEP();
+	    bit = shift & 0x1F;
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+	    switch (rh) {
+	    case 4:
+		*srcreg |= mask;
+		break;
+	    case 5:
+		*srcreg &= ~mask;
+		break;
+	    case 6:
+		*srcreg ^= mask;
+		break;
+	    default:
+		break;
+	    }
+	} else {
+	    u16 *srcreg;
+	    u16 mask;
+	    u8 shift;
+
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shift = fetch_byte_imm();
+	    TRACE_AND_STEP();
+	    bit = shift & 0xF;
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+	    switch (rh) {
+	    case 4:
+		*srcreg |= mask;
+		break;
+	    case 5:
+		*srcreg &= ~mask;
+		break;
+	    case 6:
+		*srcreg ^= mask;
+		break;
+	    default:
+		break;
+	    }
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xbb
+****************************************************************************/
+void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+    int bit,disp;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("BTC\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval,mask;
+	    u32 *shiftreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    disp = (s16)*shiftreg >> 5;
+	    srcval = fetch_data_long(srcoffset+disp);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    store_data_long(srcoffset+disp, srcval ^ mask);
+	} else {
+	    u16 srcval,mask;
+	    u16 *shiftreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0xF;
+	    disp = (s16)*shiftreg >> 4;
+	    srcval = fetch_data_word(srcoffset+disp);
+			mask = (u16)(0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval,mask;
+	    u32 *shiftreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    disp = (s16)*shiftreg >> 5;
+	    srcval = fetch_data_long(srcoffset+disp);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    store_data_long(srcoffset+disp, srcval ^ mask);
+	} else {
+	    u16 srcval,mask;
+	    u16 *shiftreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0xF;
+	    disp = (s16)*shiftreg >> 4;
+	    srcval = fetch_data_word(srcoffset+disp);
+			mask = (u16)(0x1 << bit);
+			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval,mask;
+	    u32 *shiftreg;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    disp = (s16)*shiftreg >> 5;
+	    srcval = fetch_data_long(srcoffset+disp);
+	    mask = (0x1 << bit);
+	    CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+	    store_data_long(srcoffset+disp, srcval ^ mask);
+	} else {
+	    u16 srcval,mask;
+	    u16 *shiftreg;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0xF;
+	    disp = (s16)*shiftreg >> 4;
+	    srcval = fetch_data_word(srcoffset+disp);
+			mask = (u16)(0x1 << bit);
+			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
+			store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			u32 *srcreg,*shiftreg;
+	    u32 mask;
+
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    bit = *shiftreg & 0x1F;
+	    mask = (0x1 << bit);
+			CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+			*srcreg ^= mask;
+		} else {
+			u16 *srcreg,*shiftreg;
+			u16 mask;
+
+			srcreg = DECODE_RM_WORD_REGISTER(rl);
+			DECODE_PRINTF(",");
+			shiftreg = DECODE_RM_WORD_REGISTER(rh);
+			TRACE_AND_STEP();
+			bit = *shiftreg & 0xF;
+			mask = (u16)(0x1 << bit);
+	    CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
+	    *srcreg ^= mask;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xbc
+****************************************************************************/
+void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("BSF\n");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch(mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval, *dstreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_long(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
+		if ((srcval >> *dstreg) & 1) break;
+	} else {
+	    u16 srcval, *dstreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_word(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
+		if ((srcval >> *dstreg) & 1) break;
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval, *dstreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_long(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
+		if ((srcval >> *dstreg) & 1) break;
+	} else {
+	    u16 srcval, *dstreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_word(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
+		if ((srcval >> *dstreg) & 1) break;
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval, *dstreg;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_long(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
+		if ((srcval >> *dstreg) & 1) break;
+	} else {
+	    u16 srcval, *dstreg;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_word(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
+		if ((srcval >> *dstreg) & 1) break;
+	}
+	break;
+    case 3:				/* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg, *dstreg;
+
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+	    for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
+		if ((*srcreg >> *dstreg) & 1) break;
+	} else {
+	    u16 *srcreg, *dstreg;
+
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+	    for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
+		if ((*srcreg >> *dstreg) & 1) break;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xbd
+****************************************************************************/
+void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("BSF\n");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch(mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval, *dstreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_long(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
+		if ((srcval >> *dstreg) & 1) break;
+	} else {
+	    u16 srcval, *dstreg;
+
+	    srcoffset = decode_rm00_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_word(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
+		if ((srcval >> *dstreg) & 1) break;
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval, *dstreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_long(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
+		if ((srcval >> *dstreg) & 1) break;
+	} else {
+	    u16 srcval, *dstreg;
+
+	    srcoffset = decode_rm01_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_word(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
+		if ((srcval >> *dstreg) & 1) break;
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 srcval, *dstreg;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_long(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
+		if ((srcval >> *dstreg) & 1) break;
+	} else {
+	    u16 srcval, *dstreg;
+
+	    srcoffset = decode_rm10_address(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    srcval = fetch_data_word(srcoffset);
+	    CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
+	    for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
+		if ((srcval >> *dstreg) & 1) break;
+	}
+	break;
+    case 3:				/* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *srcreg, *dstreg;
+
+	    srcreg = DECODE_RM_LONG_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_LONG_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+	    for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
+		if ((*srcreg >> *dstreg) & 1) break;
+	} else {
+	    u16 *srcreg, *dstreg;
+
+	    srcreg = DECODE_RM_WORD_REGISTER(rl);
+	    DECODE_PRINTF(",");
+	    dstreg = DECODE_RM_WORD_REGISTER(rh);
+	    TRACE_AND_STEP();
+	    CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
+	    for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
+		if ((*srcreg >> *dstreg) & 1) break;
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xbe
+****************************************************************************/
+void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOVSX\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = (s32)((s8)fetch_data_byte(srcoffset));
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm00_address(rl);
+	    srcval = (s16)((s8)fetch_data_byte(srcoffset));
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	}
+	break;
+    case 1:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = (s32)((s8)fetch_data_byte(srcoffset));
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm01_address(rl);
+	    srcval = (s16)((s8)fetch_data_byte(srcoffset));
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	}
+	break;
+    case 2:
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u32 srcval;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = (s32)((s8)fetch_data_byte(srcoffset));
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	} else {
+	    u16 *destreg;
+	    u16 srcval;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcoffset = decode_rm10_address(rl);
+	    srcval = (s16)((s8)fetch_data_byte(srcoffset));
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = srcval;
+	}
+	break;
+    case 3:                     /* register to register */
+	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+	    u32 *destreg;
+	    u8  *srcreg;
+
+	    destreg = DECODE_RM_LONG_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = (s32)((s8)*srcreg);
+	} else {
+	    u16 *destreg;
+	    u8  *srcreg;
+
+	    destreg = DECODE_RM_WORD_REGISTER(rh);
+	    DECODE_PRINTF(",");
+	    srcreg = DECODE_RM_BYTE_REGISTER(rl);
+	    DECODE_PRINTF("\n");
+	    TRACE_AND_STEP();
+	    *destreg = (s16)((s8)*srcreg);
+	}
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/****************************************************************************
+REMARKS:
+Handles opcode 0x0f,0xbf
+****************************************************************************/
+void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2))
+{
+    int mod, rl, rh;
+    uint srcoffset;
+    u32 *destreg;
+    u32 srcval;
+    u16 *srcreg;
+
+    START_OF_INSTR();
+    DECODE_PRINTF("MOVSX\t");
+    FETCH_DECODE_MODRM(mod, rh, rl);
+    switch (mod) {
+    case 0:
+	destreg = DECODE_RM_LONG_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm00_address(rl);
+	srcval = (s32)((s16)fetch_data_word(srcoffset));
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 1:
+	destreg = DECODE_RM_LONG_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm01_address(rl);
+	srcval = (s32)((s16)fetch_data_word(srcoffset));
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 2:
+	destreg = DECODE_RM_LONG_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcoffset = decode_rm10_address(rl);
+	srcval = (s32)((s16)fetch_data_word(srcoffset));
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = srcval;
+	break;
+    case 3:                     /* register to register */
+	destreg = DECODE_RM_LONG_REGISTER(rh);
+	DECODE_PRINTF(",");
+	srcreg = DECODE_RM_WORD_REGISTER(rl);
+	DECODE_PRINTF("\n");
+	TRACE_AND_STEP();
+	*destreg = (s32)((s16)*srcreg);
+	break;
+    }
+    DECODE_CLEAR_SEGOVR();
+    END_OF_INSTR();
+}
+
+/***************************************************************************
+ * Double byte operation code table:
+ **************************************************************************/
+void (*x86emu_optab2[256])(u8) =
+{
+/*  0x00 */ x86emuOp2_illegal_op,  /* Group F (ring 0 PM)      */
+/*  0x01 */ x86emuOp2_illegal_op,  /* Group G (ring 0 PM)      */
+/*  0x02 */ x86emuOp2_illegal_op,  /* lar (ring 0 PM)          */
+/*  0x03 */ x86emuOp2_illegal_op,  /* lsl (ring 0 PM)          */
+/*  0x04 */ x86emuOp2_illegal_op,
+/*  0x05 */ x86emuOp2_illegal_op,  /* loadall (undocumented)   */
+/*  0x06 */ x86emuOp2_illegal_op,  /* clts (ring 0 PM)         */
+/*  0x07 */ x86emuOp2_illegal_op,  /* loadall (undocumented)   */
+/*  0x08 */ x86emuOp2_illegal_op,  /* invd (ring 0 PM)         */
+/*  0x09 */ x86emuOp2_illegal_op,  /* wbinvd (ring 0 PM)       */
+/*  0x0a */ x86emuOp2_illegal_op,
+/*  0x0b */ x86emuOp2_illegal_op,
+/*  0x0c */ x86emuOp2_illegal_op,
+/*  0x0d */ x86emuOp2_illegal_op,
+/*  0x0e */ x86emuOp2_illegal_op,
+/*  0x0f */ x86emuOp2_illegal_op,
+
+/*  0x10 */ x86emuOp2_illegal_op,
+/*  0x11 */ x86emuOp2_illegal_op,
+/*  0x12 */ x86emuOp2_illegal_op,
+/*  0x13 */ x86emuOp2_illegal_op,
+/*  0x14 */ x86emuOp2_illegal_op,
+/*  0x15 */ x86emuOp2_illegal_op,
+/*  0x16 */ x86emuOp2_illegal_op,
+/*  0x17 */ x86emuOp2_illegal_op,
+/*  0x18 */ x86emuOp2_illegal_op,
+/*  0x19 */ x86emuOp2_illegal_op,
+/*  0x1a */ x86emuOp2_illegal_op,
+/*  0x1b */ x86emuOp2_illegal_op,
+/*  0x1c */ x86emuOp2_illegal_op,
+/*  0x1d */ x86emuOp2_illegal_op,
+/*  0x1e */ x86emuOp2_illegal_op,
+/*  0x1f */ x86emuOp2_illegal_op,
+
+/*  0x20 */ x86emuOp2_illegal_op,  /* mov reg32,creg (ring 0 PM) */
+/*  0x21 */ x86emuOp2_illegal_op,  /* mov reg32,dreg (ring 0 PM) */
+/*  0x22 */ x86emuOp2_illegal_op,  /* mov creg,reg32 (ring 0 PM) */
+/*  0x23 */ x86emuOp2_illegal_op,  /* mov dreg,reg32 (ring 0 PM) */
+/*  0x24 */ x86emuOp2_illegal_op,  /* mov reg32,treg (ring 0 PM) */
+/*  0x25 */ x86emuOp2_illegal_op,
+/*  0x26 */ x86emuOp2_illegal_op,  /* mov treg,reg32 (ring 0 PM) */
+/*  0x27 */ x86emuOp2_illegal_op,
+/*  0x28 */ x86emuOp2_illegal_op,
+/*  0x29 */ x86emuOp2_illegal_op,
+/*  0x2a */ x86emuOp2_illegal_op,
+/*  0x2b */ x86emuOp2_illegal_op,
+/*  0x2c */ x86emuOp2_illegal_op,
+/*  0x2d */ x86emuOp2_illegal_op,
+/*  0x2e */ x86emuOp2_illegal_op,
+/*  0x2f */ x86emuOp2_illegal_op,
+
+/*  0x30 */ x86emuOp2_illegal_op,
+/*  0x31 */ x86emuOp2_illegal_op,
+/*  0x32 */ x86emuOp2_illegal_op,
+/*  0x33 */ x86emuOp2_illegal_op,
+/*  0x34 */ x86emuOp2_illegal_op,
+/*  0x35 */ x86emuOp2_illegal_op,
+/*  0x36 */ x86emuOp2_illegal_op,
+/*  0x37 */ x86emuOp2_illegal_op,
+/*  0x38 */ x86emuOp2_illegal_op,
+/*  0x39 */ x86emuOp2_illegal_op,
+/*  0x3a */ x86emuOp2_illegal_op,
+/*  0x3b */ x86emuOp2_illegal_op,
+/*  0x3c */ x86emuOp2_illegal_op,
+/*  0x3d */ x86emuOp2_illegal_op,
+/*  0x3e */ x86emuOp2_illegal_op,
+/*  0x3f */ x86emuOp2_illegal_op,
+
+/*  0x40 */ x86emuOp2_illegal_op,
+/*  0x41 */ x86emuOp2_illegal_op,
+/*  0x42 */ x86emuOp2_illegal_op,
+/*  0x43 */ x86emuOp2_illegal_op,
+/*  0x44 */ x86emuOp2_illegal_op,
+/*  0x45 */ x86emuOp2_illegal_op,
+/*  0x46 */ x86emuOp2_illegal_op,
+/*  0x47 */ x86emuOp2_illegal_op,
+/*  0x48 */ x86emuOp2_illegal_op,
+/*  0x49 */ x86emuOp2_illegal_op,
+/*  0x4a */ x86emuOp2_illegal_op,
+/*  0x4b */ x86emuOp2_illegal_op,
+/*  0x4c */ x86emuOp2_illegal_op,
+/*  0x4d */ x86emuOp2_illegal_op,
+/*  0x4e */ x86emuOp2_illegal_op,
+/*  0x4f */ x86emuOp2_illegal_op,
+
+/*  0x50 */ x86emuOp2_illegal_op,
+/*  0x51 */ x86emuOp2_illegal_op,
+/*  0x52 */ x86emuOp2_illegal_op,
+/*  0x53 */ x86emuOp2_illegal_op,
+/*  0x54 */ x86emuOp2_illegal_op,
+/*  0x55 */ x86emuOp2_illegal_op,
+/*  0x56 */ x86emuOp2_illegal_op,
+/*  0x57 */ x86emuOp2_illegal_op,
+/*  0x58 */ x86emuOp2_illegal_op,
+/*  0x59 */ x86emuOp2_illegal_op,
+/*  0x5a */ x86emuOp2_illegal_op,
+/*  0x5b */ x86emuOp2_illegal_op,
+/*  0x5c */ x86emuOp2_illegal_op,
+/*  0x5d */ x86emuOp2_illegal_op,
+/*  0x5e */ x86emuOp2_illegal_op,
+/*  0x5f */ x86emuOp2_illegal_op,
+
+/*  0x60 */ x86emuOp2_illegal_op,
+/*  0x61 */ x86emuOp2_illegal_op,
+/*  0x62 */ x86emuOp2_illegal_op,
+/*  0x63 */ x86emuOp2_illegal_op,
+/*  0x64 */ x86emuOp2_illegal_op,
+/*  0x65 */ x86emuOp2_illegal_op,
+/*  0x66 */ x86emuOp2_illegal_op,
+/*  0x67 */ x86emuOp2_illegal_op,
+/*  0x68 */ x86emuOp2_illegal_op,
+/*  0x69 */ x86emuOp2_illegal_op,
+/*  0x6a */ x86emuOp2_illegal_op,
+/*  0x6b */ x86emuOp2_illegal_op,
+/*  0x6c */ x86emuOp2_illegal_op,
+/*  0x6d */ x86emuOp2_illegal_op,
+/*  0x6e */ x86emuOp2_illegal_op,
+/*  0x6f */ x86emuOp2_illegal_op,
+
+/*  0x70 */ x86emuOp2_illegal_op,
+/*  0x71 */ x86emuOp2_illegal_op,
+/*  0x72 */ x86emuOp2_illegal_op,
+/*  0x73 */ x86emuOp2_illegal_op,
+/*  0x74 */ x86emuOp2_illegal_op,
+/*  0x75 */ x86emuOp2_illegal_op,
+/*  0x76 */ x86emuOp2_illegal_op,
+/*  0x77 */ x86emuOp2_illegal_op,
+/*  0x78 */ x86emuOp2_illegal_op,
+/*  0x79 */ x86emuOp2_illegal_op,
+/*  0x7a */ x86emuOp2_illegal_op,
+/*  0x7b */ x86emuOp2_illegal_op,
+/*  0x7c */ x86emuOp2_illegal_op,
+/*  0x7d */ x86emuOp2_illegal_op,
+/*  0x7e */ x86emuOp2_illegal_op,
+/*  0x7f */ x86emuOp2_illegal_op,
+
+/*  0x80 */ x86emuOp2_long_jump,
+/*  0x81 */ x86emuOp2_long_jump,
+/*  0x82 */ x86emuOp2_long_jump,
+/*  0x83 */ x86emuOp2_long_jump,
+/*  0x84 */ x86emuOp2_long_jump,
+/*  0x85 */ x86emuOp2_long_jump,
+/*  0x86 */ x86emuOp2_long_jump,
+/*  0x87 */ x86emuOp2_long_jump,
+/*  0x88 */ x86emuOp2_long_jump,
+/*  0x89 */ x86emuOp2_long_jump,
+/*  0x8a */ x86emuOp2_long_jump,
+/*  0x8b */ x86emuOp2_long_jump,
+/*  0x8c */ x86emuOp2_long_jump,
+/*  0x8d */ x86emuOp2_long_jump,
+/*  0x8e */ x86emuOp2_long_jump,
+/*  0x8f */ x86emuOp2_long_jump,
+
+/*  0x90 */ x86emuOp2_set_byte,
+/*  0x91 */ x86emuOp2_set_byte,
+/*  0x92 */ x86emuOp2_set_byte,
+/*  0x93 */ x86emuOp2_set_byte,
+/*  0x94 */ x86emuOp2_set_byte,
+/*  0x95 */ x86emuOp2_set_byte,
+/*  0x96 */ x86emuOp2_set_byte,
+/*  0x97 */ x86emuOp2_set_byte,
+/*  0x98 */ x86emuOp2_set_byte,
+/*  0x99 */ x86emuOp2_set_byte,
+/*  0x9a */ x86emuOp2_set_byte,
+/*  0x9b */ x86emuOp2_set_byte,
+/*  0x9c */ x86emuOp2_set_byte,
+/*  0x9d */ x86emuOp2_set_byte,
+/*  0x9e */ x86emuOp2_set_byte,
+/*  0x9f */ x86emuOp2_set_byte,
+
+/*  0xa0 */ x86emuOp2_push_FS,
+/*  0xa1 */ x86emuOp2_pop_FS,
+/*  0xa2 */ x86emuOp2_illegal_op,
+/*  0xa3 */ x86emuOp2_bt_R,
+/*  0xa4 */ x86emuOp2_shld_IMM,
+/*  0xa5 */ x86emuOp2_shld_CL,
+/*  0xa6 */ x86emuOp2_illegal_op,
+/*  0xa7 */ x86emuOp2_illegal_op,
+/*  0xa8 */ x86emuOp2_push_GS,
+/*  0xa9 */ x86emuOp2_pop_GS,
+/*  0xaa */ x86emuOp2_illegal_op,
+/*  0xab */ x86emuOp2_bt_R,
+/*  0xac */ x86emuOp2_shrd_IMM,
+/*  0xad */ x86emuOp2_shrd_CL,
+/*  0xae */ x86emuOp2_illegal_op,
+/*  0xaf */ x86emuOp2_imul_R_RM,
+
+/*  0xb0 */ x86emuOp2_illegal_op,  /* TODO: cmpxchg */
+/*  0xb1 */ x86emuOp2_illegal_op,  /* TODO: cmpxchg */
+/*  0xb2 */ x86emuOp2_lss_R_IMM,
+/*  0xb3 */ x86emuOp2_btr_R,
+/*  0xb4 */ x86emuOp2_lfs_R_IMM,
+/*  0xb5 */ x86emuOp2_lgs_R_IMM,
+/*  0xb6 */ x86emuOp2_movzx_byte_R_RM,
+/*  0xb7 */ x86emuOp2_movzx_word_R_RM,
+/*  0xb8 */ x86emuOp2_illegal_op,
+/*  0xb9 */ x86emuOp2_illegal_op,
+/*  0xba */ x86emuOp2_btX_I,
+/*  0xbb */ x86emuOp2_btc_R,
+/*  0xbc */ x86emuOp2_bsf,
+/*  0xbd */ x86emuOp2_bsr,
+/*  0xbe */ x86emuOp2_movsx_byte_R_RM,
+/*  0xbf */ x86emuOp2_movsx_word_R_RM,
+
+/*  0xc0 */ x86emuOp2_illegal_op,  /* TODO: xadd */
+/*  0xc1 */ x86emuOp2_illegal_op,  /* TODO: xadd */
+/*  0xc2 */ x86emuOp2_illegal_op,
+/*  0xc3 */ x86emuOp2_illegal_op,
+/*  0xc4 */ x86emuOp2_illegal_op,
+/*  0xc5 */ x86emuOp2_illegal_op,
+/*  0xc6 */ x86emuOp2_illegal_op,
+/*  0xc7 */ x86emuOp2_illegal_op,
+/*  0xc8 */ x86emuOp2_illegal_op,  /* TODO: bswap */
+/*  0xc9 */ x86emuOp2_illegal_op,  /* TODO: bswap */
+/*  0xca */ x86emuOp2_illegal_op,  /* TODO: bswap */
+/*  0xcb */ x86emuOp2_illegal_op,  /* TODO: bswap */
+/*  0xcc */ x86emuOp2_illegal_op,  /* TODO: bswap */
+/*  0xcd */ x86emuOp2_illegal_op,  /* TODO: bswap */
+/*  0xce */ x86emuOp2_illegal_op,  /* TODO: bswap */
+/*  0xcf */ x86emuOp2_illegal_op,  /* TODO: bswap */
+
+/*  0xd0 */ x86emuOp2_illegal_op,
+/*  0xd1 */ x86emuOp2_illegal_op,
+/*  0xd2 */ x86emuOp2_illegal_op,
+/*  0xd3 */ x86emuOp2_illegal_op,
+/*  0xd4 */ x86emuOp2_illegal_op,
+/*  0xd5 */ x86emuOp2_illegal_op,
+/*  0xd6 */ x86emuOp2_illegal_op,
+/*  0xd7 */ x86emuOp2_illegal_op,
+/*  0xd8 */ x86emuOp2_illegal_op,
+/*  0xd9 */ x86emuOp2_illegal_op,
+/*  0xda */ x86emuOp2_illegal_op,
+/*  0xdb */ x86emuOp2_illegal_op,
+/*  0xdc */ x86emuOp2_illegal_op,
+/*  0xdd */ x86emuOp2_illegal_op,
+/*  0xde */ x86emuOp2_illegal_op,
+/*  0xdf */ x86emuOp2_illegal_op,
+
+/*  0xe0 */ x86emuOp2_illegal_op,
+/*  0xe1 */ x86emuOp2_illegal_op,
+/*  0xe2 */ x86emuOp2_illegal_op,
+/*  0xe3 */ x86emuOp2_illegal_op,
+/*  0xe4 */ x86emuOp2_illegal_op,
+/*  0xe5 */ x86emuOp2_illegal_op,
+/*  0xe6 */ x86emuOp2_illegal_op,
+/*  0xe7 */ x86emuOp2_illegal_op,
+/*  0xe8 */ x86emuOp2_illegal_op,
+/*  0xe9 */ x86emuOp2_illegal_op,
+/*  0xea */ x86emuOp2_illegal_op,
+/*  0xeb */ x86emuOp2_illegal_op,
+/*  0xec */ x86emuOp2_illegal_op,
+/*  0xed */ x86emuOp2_illegal_op,
+/*  0xee */ x86emuOp2_illegal_op,
+/*  0xef */ x86emuOp2_illegal_op,
+
+/*  0xf0 */ x86emuOp2_illegal_op,
+/*  0xf1 */ x86emuOp2_illegal_op,
+/*  0xf2 */ x86emuOp2_illegal_op,
+/*  0xf3 */ x86emuOp2_illegal_op,
+/*  0xf4 */ x86emuOp2_illegal_op,
+/*  0xf5 */ x86emuOp2_illegal_op,
+/*  0xf6 */ x86emuOp2_illegal_op,
+/*  0xf7 */ x86emuOp2_illegal_op,
+/*  0xf8 */ x86emuOp2_illegal_op,
+/*  0xf9 */ x86emuOp2_illegal_op,
+/*  0xfa */ x86emuOp2_illegal_op,
+/*  0xfb */ x86emuOp2_illegal_op,
+/*  0xfc */ x86emuOp2_illegal_op,
+/*  0xfd */ x86emuOp2_illegal_op,
+/*  0xfe */ x86emuOp2_illegal_op,
+/*  0xff */ x86emuOp2_illegal_op,
+};
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c b/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c
new file mode 100755
index 0000000..72b1bf2
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c
@@ -0,0 +1,2914 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  This file contains the code to implement the primitive
+*				machine operations used by the emulation code in ops.c
+*
+* Carry Chain Calculation
+*
+* This represents a somewhat expensive calculation which is
+* apparently required to emulate the setting of the OF and AF flag.
+* The latter is not so important, but the former is.  The overflow
+* flag is the XOR of the top two bits of the carry chain for an
+* addition (similar for subtraction).  Since we do not want to
+* simulate the addition in a bitwise manner, we try to calculate the
+* carry chain given the two operands and the result.
+*
+* So, given the following table, which represents the addition of two
+* bits, we can derive a formula for the carry chain.
+*
+* a   b   cin   r     cout
+* 0   0   0     0     0
+* 0   0   1     1     0
+* 0   1   0     1     0
+* 0   1   1     0     1
+* 1   0   0     1     0
+* 1   0   1     0     1
+* 1   1   0     0     1
+* 1   1   1     1     1
+*
+* Construction of table for cout:
+*
+* ab
+* r  \  00   01   11  10
+* |------------------
+* 0  |   0    1    1   1
+* 1  |   0    0    1   0
+*
+* By inspection, one gets:  cc = ab +  r'(a + b)
+*
+* That represents alot of operations, but NO CHOICE....
+*
+* Borrow Chain Calculation.
+*
+* The following table represents the subtraction of two bits, from
+* which we can derive a formula for the borrow chain.
+*
+* a   b   bin   r     bout
+* 0   0   0     0     0
+* 0   0   1     1     1
+* 0   1   0     1     1
+* 0   1   1     0     1
+* 1   0   0     1     0
+* 1   0   1     0     0
+* 1   1   0     0     0
+* 1   1   1     1     1
+*
+* Construction of table for cout:
+*
+* ab
+* r  \  00   01   11  10
+* |------------------
+* 0  |   0    1    0   0
+* 1  |   1    1    1   0
+*
+* By inspection, one gets:  bc = a'b +  r(a' + b)
+*
+****************************************************************************/
+
+#define	PRIM_OPS_NO_REDEFINE_ASM
+#include "x86emu/x86emui.h"
+
+/*------------------------- Global Variables ------------------------------*/
+
+#ifndef	__HAVE_INLINE_ASSEMBLER__
+
+static u32 x86emu_parity_tab[8] =
+{
+	0x96696996,
+	0x69969669,
+	0x69969669,
+	0x96696996,
+	0x69969669,
+	0x96696996,
+	0x96696996,
+	0x69969669,
+};
+
+#endif
+
+#define PARITY(x)   (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0)
+#define XOR2(x) 	(((x) ^ ((x)>>1)) & 0x1)
+
+/*----------------------------- Implementation ----------------------------*/
+
+#ifndef	__HAVE_INLINE_ASSEMBLER__
+
+/****************************************************************************
+REMARKS:
+Implements the AAA instruction and side effects.
+****************************************************************************/
+u16 aaa_word(u16 d)
+{
+	u16	res;
+	if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) {
+		d += 0x6;
+		d += 0x100;
+		SET_FLAG(F_AF);
+		SET_FLAG(F_CF);
+	} else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_AF);
+	}
+	res = (u16)(d & 0xFF0F);
+	CLEAR_FLAG(F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the AAA instruction and side effects.
+****************************************************************************/
+u16 aas_word(u16 d)
+{
+	u16	res;
+	if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) {
+		d -= 0x6;
+		d -= 0x100;
+		SET_FLAG(F_AF);
+		SET_FLAG(F_CF);
+	} else {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_AF);
+	}
+	res = (u16)(d & 0xFF0F);
+	CLEAR_FLAG(F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the AAD instruction and side effects.
+****************************************************************************/
+u16 aad_word(u16 d)
+{
+	u16 l;
+	u8 hb, lb;
+
+	hb = (u8)((d >> 8) & 0xff);
+	lb = (u8)((d & 0xff));
+	l = (u16)((lb + 10 * hb) & 0xFF);
+
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CLEAR_FLAG(F_OF);
+	CONDITIONAL_SET_FLAG(l & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(l == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF);
+	return l;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the AAM instruction and side effects.
+****************************************************************************/
+u16 aam_word(u8 d)
+{
+    u16 h, l;
+
+	h = (u16)(d / 10);
+	l = (u16)(d % 10);
+	l |= (u16)(h << 8);
+
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CLEAR_FLAG(F_OF);
+	CONDITIONAL_SET_FLAG(l & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(l == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF);
+    return l;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ADC instruction and side effects.
+****************************************************************************/
+u8 adc_byte(u8 d, u8 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 cc;
+
+	if (ACCESS_FLAG(F_CF))
+		res = 1 + d + s;
+	else
+		res = d + s;
+
+	CONDITIONAL_SET_FLAG(res & 0x100, F_CF);
+	CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the carry chain  SEE NOTE AT TOP. */
+	cc = (s & d) | ((~res) & (s | d));
+	CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF);
+	CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ADC instruction and side effects.
+****************************************************************************/
+u16 adc_word(u16 d, u16 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 cc;
+
+	if (ACCESS_FLAG(F_CF))
+		res = 1 + d + s;
+	else
+		res = d + s;
+
+	CONDITIONAL_SET_FLAG(res & 0x10000, F_CF);
+	CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the carry chain  SEE NOTE AT TOP. */
+	cc = (s & d) | ((~res) & (s | d));
+	CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF);
+	CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ADC instruction and side effects.
+****************************************************************************/
+u32 adc_long(u32 d, u32 s)
+{
+	register u32 lo;	/* all operands in native machine order */
+	register u32 hi;
+	register u32 res;
+	register u32 cc;
+
+	if (ACCESS_FLAG(F_CF)) {
+		lo = 1 + (d & 0xFFFF) + (s & 0xFFFF);
+		res = 1 + d + s;
+		}
+	else {
+		lo = (d & 0xFFFF) + (s & 0xFFFF);
+		res = d + s;
+		}
+	hi = (lo >> 16) + (d >> 16) + (s >> 16);
+
+	CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF);
+	CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the carry chain  SEE NOTE AT TOP. */
+	cc = (s & d) | ((~res) & (s | d));
+	CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF);
+	CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ADD instruction and side effects.
+****************************************************************************/
+u8 add_byte(u8 d, u8 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 cc;
+
+	res = d + s;
+	CONDITIONAL_SET_FLAG(res & 0x100, F_CF);
+	CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the carry chain  SEE NOTE AT TOP. */
+	cc = (s & d) | ((~res) & (s | d));
+	CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF);
+	CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ADD instruction and side effects.
+****************************************************************************/
+u16 add_word(u16 d, u16 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 cc;
+
+	res = d + s;
+	CONDITIONAL_SET_FLAG(res & 0x10000, F_CF);
+	CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the carry chain  SEE NOTE AT TOP. */
+	cc = (s & d) | ((~res) & (s | d));
+	CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF);
+	CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ADD instruction and side effects.
+****************************************************************************/
+u32 add_long(u32 d, u32 s)
+{
+	register u32 lo;	/* all operands in native machine order */
+	register u32 hi;
+	register u32 res;
+	register u32 cc;
+
+	lo = (d & 0xFFFF) + (s & 0xFFFF);
+	res = d + s;
+	hi = (lo >> 16) + (d >> 16) + (s >> 16);
+
+	CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF);
+	CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+    /* calculate the carry chain  SEE NOTE AT TOP. */
+    cc = (s & d) | ((~res) & (s | d));
+	CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF);
+	CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+
+    return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the AND instruction and side effects.
+****************************************************************************/
+u8 and_byte(u8 d, u8 s)
+{
+	register u8 res;    /* all operands in native machine order */
+
+	res = d & s;
+
+	/* set the flags  */
+	CLEAR_FLAG(F_OF);
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res), F_PF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the AND instruction and side effects.
+****************************************************************************/
+u16 and_word(u16 d, u16 s)
+{
+    register u16 res;   /* all operands in native machine order */
+
+    res = d & s;
+
+    /* set the flags  */
+	CLEAR_FLAG(F_OF);
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+    return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the AND instruction and side effects.
+****************************************************************************/
+u32 and_long(u32 d, u32 s)
+{
+	register u32 res;   /* all operands in native machine order */
+
+	res = d & s;
+
+	/* set the flags  */
+	CLEAR_FLAG(F_OF);
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the CMP instruction and side effects.
+****************************************************************************/
+u8 cmp_byte(u8 d, u8 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 bc;
+
+	res = d - s;
+	CLEAR_FLAG(F_CF);
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+	bc = (res & (~d | s)) | (~d & s);
+	CONDITIONAL_SET_FLAG(bc & 0x80, F_CF);
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return d;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the CMP instruction and side effects.
+****************************************************************************/
+u16 cmp_word(u16 d, u16 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 bc;
+
+	res = d - s;
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+    bc = (res & (~d | s)) | (~d & s);
+	CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF);
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return d;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the CMP instruction and side effects.
+****************************************************************************/
+u32 cmp_long(u32 d, u32 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 bc;
+
+	res = d - s;
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+	bc = (res & (~d | s)) | (~d & s);
+	CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF);
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return d;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the DAA instruction and side effects.
+****************************************************************************/
+u8 daa_byte(u8 d)
+{
+	u32 res = d;
+	if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) {
+		res += 6;
+		SET_FLAG(F_AF);
+	}
+	if (res > 0x9F || ACCESS_FLAG(F_CF)) {
+		res += 0x60;
+		SET_FLAG(F_CF);
+	}
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xFF) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the DAS instruction and side effects.
+****************************************************************************/
+u8 das_byte(u8 d)
+{
+	if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) {
+		d -= 6;
+		SET_FLAG(F_AF);
+	}
+	if (d > 0x9F || ACCESS_FLAG(F_CF)) {
+		d -= 0x60;
+		SET_FLAG(F_CF);
+	}
+	CONDITIONAL_SET_FLAG(d & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(d == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(d & 0xff), F_PF);
+	return d;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the DEC instruction and side effects.
+****************************************************************************/
+u8 dec_byte(u8 d)
+{
+    register u32 res;   /* all operands in native machine order */
+    register u32 bc;
+
+    res = d - 1;
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+	/* based on sub_byte, uses s==1.  */
+	bc = (res & (~d | 1)) | (~d & 1);
+	/* carry flag unchanged */
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the DEC instruction and side effects.
+****************************************************************************/
+u16 dec_word(u16 d)
+{
+    register u32 res;   /* all operands in native machine order */
+    register u32 bc;
+
+    res = d - 1;
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+    /* calculate the borrow chain.  See note at top */
+    /* based on the sub_byte routine, with s==1 */
+    bc = (res & (~d | 1)) | (~d & 1);
+    /* carry flag unchanged */
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the DEC instruction and side effects.
+****************************************************************************/
+u32 dec_long(u32 d)
+{
+    register u32 res;   /* all operands in native machine order */
+    register u32 bc;
+
+    res = d - 1;
+
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+    /* calculate the borrow chain.  See note at top */
+	bc = (res & (~d | 1)) | (~d & 1);
+	/* carry flag unchanged */
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the INC instruction and side effects.
+****************************************************************************/
+u8 inc_byte(u8 d)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 cc;
+
+	res = d + 1;
+	CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the carry chain  SEE NOTE AT TOP. */
+	cc = ((1 & d) | (~res)) & (1 | d);
+	CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF);
+	CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the INC instruction and side effects.
+****************************************************************************/
+u16 inc_word(u16 d)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 cc;
+
+	res = d + 1;
+	CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the carry chain  SEE NOTE AT TOP. */
+	cc = (1 & d) | ((~res) & (1 | d));
+	CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF);
+	CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the INC instruction and side effects.
+****************************************************************************/
+u32 inc_long(u32 d)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 cc;
+
+	res = d + 1;
+	CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the carry chain  SEE NOTE AT TOP. */
+	cc = (1 & d) | ((~res) & (1 | d));
+	CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF);
+	CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the OR instruction and side effects.
+****************************************************************************/
+u8 or_byte(u8 d, u8 s)
+{
+	register u8 res;    /* all operands in native machine order */
+
+	res = d | s;
+	CLEAR_FLAG(F_OF);
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res), F_PF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the OR instruction and side effects.
+****************************************************************************/
+u16 or_word(u16 d, u16 s)
+{
+	register u16 res;   /* all operands in native machine order */
+
+	res = d | s;
+	/* set the carry flag to be bit 8 */
+	CLEAR_FLAG(F_OF);
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the OR instruction and side effects.
+****************************************************************************/
+u32 or_long(u32 d, u32 s)
+{
+	register u32 res;   /* all operands in native machine order */
+
+	res = d | s;
+
+	/* set the carry flag to be bit 8 */
+	CLEAR_FLAG(F_OF);
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the OR instruction and side effects.
+****************************************************************************/
+u8 neg_byte(u8 s)
+{
+    register u8 res;
+    register u8 bc;
+
+	CONDITIONAL_SET_FLAG(s != 0, F_CF);
+	res = (u8)-s;
+	CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res), F_PF);
+	/* calculate the borrow chain --- modified such that d=0.
+	   substitutiing d=0 into     bc= res&(~d|s)|(~d&s);
+	   (the one used for sub) and simplifying, since ~d=0xff...,
+	   ~d|s == 0xffff..., and res&0xfff... == res.  Similarly
+	   ~d&s == s.  So the simplified result is: */
+	bc = res | s;
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the OR instruction and side effects.
+****************************************************************************/
+u16 neg_word(u16 s)
+{
+	register u16 res;
+	register u16 bc;
+
+	CONDITIONAL_SET_FLAG(s != 0, F_CF);
+	res = (u16)-s;
+	CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain --- modified such that d=0.
+	   substitutiing d=0 into     bc= res&(~d|s)|(~d&s);
+	   (the one used for sub) and simplifying, since ~d=0xff...,
+	   ~d|s == 0xffff..., and res&0xfff... == res.  Similarly
+	   ~d&s == s.  So the simplified result is: */
+	bc = res | s;
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the OR instruction and side effects.
+****************************************************************************/
+u32 neg_long(u32 s)
+{
+	register u32 res;
+	register u32 bc;
+
+	CONDITIONAL_SET_FLAG(s != 0, F_CF);
+	res = (u32)-s;
+	CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain --- modified such that d=0.
+	   substitutiing d=0 into     bc= res&(~d|s)|(~d&s);
+	   (the one used for sub) and simplifying, since ~d=0xff...,
+	   ~d|s == 0xffff..., and res&0xfff... == res.  Similarly
+	   ~d&s == s.  So the simplified result is: */
+	bc = res | s;
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the NOT instruction and side effects.
+****************************************************************************/
+u8 not_byte(u8 s)
+{
+	return ~s;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the NOT instruction and side effects.
+****************************************************************************/
+u16 not_word(u16 s)
+{
+	return ~s;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the NOT instruction and side effects.
+****************************************************************************/
+u32 not_long(u32 s)
+{
+	return ~s;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the RCL instruction and side effects.
+****************************************************************************/
+u8 rcl_byte(u8 d, u8 s)
+{
+    register unsigned int res, cnt, mask, cf;
+
+    /* s is the rotate distance.  It varies from 0 - 8. */
+	/* have
+
+       CF  B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0
+
+       want to rotate through the carry by "s" bits.  We could
+       loop, but that's inefficient.  So the width is 9,
+       and we split into three parts:
+
+       The new carry flag   (was B_n)
+       the stuff in B_n-1 .. B_0
+       the stuff in B_7 .. B_n+1
+
+       The new rotate is done mod 9, and given this,
+       for a rotation of n bits (mod 9) the new carry flag is
+       then located n bits from the MSB.  The low part is
+       then shifted up cnt bits, and the high part is or'd
+       in.  Using CAPS for new values, and lowercase for the
+       original values, this can be expressed as:
+
+       IF n > 0
+       1) CF <-  b_(8-n)
+       2) B_(7) .. B_(n)  <-  b_(8-(n+1)) .. b_0
+       3) B_(n-1) <- cf
+       4) B_(n-2) .. B_0 <-  b_7 .. b_(8-(n-1))
+	 */
+	res = d;
+	if ((cnt = s % 9) != 0) {
+	/* extract the new CARRY FLAG. */
+	/* CF <-  b_(8-n)             */
+	cf = (d >> (8 - cnt)) & 0x1;
+
+	/* get the low stuff which rotated
+	   into the range B_7 .. B_cnt */
+	/* B_(7) .. B_(n)  <-  b_(8-(n+1)) .. b_0  */
+	/* note that the right hand side done by the mask */
+		res = (d << cnt) & 0xff;
+
+	/* now the high stuff which rotated around
+	   into the positions B_cnt-2 .. B_0 */
+	/* B_(n-2) .. B_0 <-  b_7 .. b_(8-(n-1)) */
+	/* shift it downward, 7-(n-2) = 9-n positions.
+	   and mask off the result before or'ing in.
+	 */
+	mask = (1 << (cnt - 1)) - 1;
+	res |= (d >> (9 - cnt)) & mask;
+
+	/* if the carry flag was set, or it in.  */
+		if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
+	    /*  B_(n-1) <- cf */
+	    res |= 1 << (cnt - 1);
+	}
+	/* set the new carry flag, based on the variable "cf" */
+		CONDITIONAL_SET_FLAG(cf, F_CF);
+	/* OVERFLOW is set *IFF* cnt==1, then it is the
+	   xor of CF and the most significant bit.  Blecck. */
+	/* parenthesized this expression since it appears to
+	   be causing OF to be misset */
+	CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)),
+							 F_OF);
+
+    }
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the RCL instruction and side effects.
+****************************************************************************/
+u16 rcl_word(u16 d, u8 s)
+{
+	register unsigned int res, cnt, mask, cf;
+
+	res = d;
+	if ((cnt = s % 17) != 0) {
+		cf = (d >> (16 - cnt)) & 0x1;
+		res = (d << cnt) & 0xffff;
+		mask = (1 << (cnt - 1)) - 1;
+		res |= (d >> (17 - cnt)) & mask;
+		if (ACCESS_FLAG(F_CF)) {
+			res |= 1 << (cnt - 1);
+		}
+		CONDITIONAL_SET_FLAG(cf, F_CF);
+		CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)),
+							 F_OF);
+	}
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the RCL instruction and side effects.
+****************************************************************************/
+u32 rcl_long(u32 d, u8 s)
+{
+	register u32 res, cnt, mask, cf;
+
+	res = d;
+	if ((cnt = s % 33) != 0) {
+		cf = (d >> (32 - cnt)) & 0x1;
+		res = (d << cnt) & 0xffffffff;
+		mask = (1 << (cnt - 1)) - 1;
+		res |= (d >> (33 - cnt)) & mask;
+		if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
+			res |= 1 << (cnt - 1);
+		}
+		CONDITIONAL_SET_FLAG(cf, F_CF);
+		CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)),
+							 F_OF);
+	}
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the RCR instruction and side effects.
+****************************************************************************/
+u8 rcr_byte(u8 d, u8 s)
+{
+	u32	res, cnt;
+	u32	mask, cf, ocf = 0;
+
+	/* rotate right through carry */
+    /*
+       s is the rotate distance.  It varies from 0 - 8.
+       d is the byte object rotated.
+
+       have
+
+       CF  B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0
+
+       The new rotate is done mod 9, and given this,
+       for a rotation of n bits (mod 9) the new carry flag is
+       then located n bits from the LSB.  The low part is
+       then shifted up cnt bits, and the high part is or'd
+       in.  Using CAPS for new values, and lowercase for the
+       original values, this can be expressed as:
+
+       IF n > 0
+       1) CF <-  b_(n-1)
+       2) B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_(n)
+       3) B_(8-n) <- cf
+       4) B_(7) .. B_(8-(n-1)) <-  b_(n-2) .. b_(0)
+	 */
+	res = d;
+	if ((cnt = s % 9) != 0) {
+	/* extract the new CARRY FLAG. */
+	/* CF <-  b_(n-1)              */
+	if (cnt == 1) {
+	    cf = d & 0x1;
+	    /* note hackery here.  Access_flag(..) evaluates to either
+	       0 if flag not set
+	       non-zero if flag is set.
+	       doing access_flag(..) != 0 casts that into either
+			   0..1 in any representation of the flags register
+	       (i.e. packed bit array or unpacked.)
+	     */
+			ocf = ACCESS_FLAG(F_CF) != 0;
+	} else
+	    cf = (d >> (cnt - 1)) & 0x1;
+
+	/* B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_n  */
+	/* note that the right hand side done by the mask
+	   This is effectively done by shifting the
+	   object to the right.  The result must be masked,
+	   in case the object came in and was treated
+	   as a negative number.  Needed??? */
+
+	mask = (1 << (8 - cnt)) - 1;
+	res = (d >> cnt) & mask;
+
+	/* now the high stuff which rotated around
+	   into the positions B_cnt-2 .. B_0 */
+	/* B_(7) .. B_(8-(n-1)) <-  b_(n-2) .. b_(0) */
+	/* shift it downward, 7-(n-2) = 9-n positions.
+	   and mask off the result before or'ing in.
+	 */
+	res |= (d << (9 - cnt));
+
+	/* if the carry flag was set, or it in.  */
+		if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
+	    /*  B_(8-n) <- cf */
+	    res |= 1 << (8 - cnt);
+	}
+	/* set the new carry flag, based on the variable "cf" */
+		CONDITIONAL_SET_FLAG(cf, F_CF);
+	/* OVERFLOW is set *IFF* cnt==1, then it is the
+	   xor of CF and the most significant bit.  Blecck. */
+	/* parenthesized... */
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)),
+								 F_OF);
+		}
+	}
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the RCR instruction and side effects.
+****************************************************************************/
+u16 rcr_word(u16 d, u8 s)
+{
+	u32 res, cnt;
+	u32	mask, cf, ocf = 0;
+
+	/* rotate right through carry */
+	res = d;
+	if ((cnt = s % 17) != 0) {
+		if (cnt == 1) {
+			cf = d & 0x1;
+			ocf = ACCESS_FLAG(F_CF) != 0;
+		} else
+			cf = (d >> (cnt - 1)) & 0x1;
+		mask = (1 << (16 - cnt)) - 1;
+		res = (d >> cnt) & mask;
+		res |= (d << (17 - cnt));
+		if (ACCESS_FLAG(F_CF)) {
+			res |= 1 << (16 - cnt);
+		}
+		CONDITIONAL_SET_FLAG(cf, F_CF);
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)),
+								 F_OF);
+		}
+	}
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the RCR instruction and side effects.
+****************************************************************************/
+u32 rcr_long(u32 d, u8 s)
+{
+	u32 res, cnt;
+	u32 mask, cf, ocf = 0;
+
+	/* rotate right through carry */
+	res = d;
+	if ((cnt = s % 33) != 0) {
+		if (cnt == 1) {
+			cf = d & 0x1;
+			ocf = ACCESS_FLAG(F_CF) != 0;
+		} else
+			cf = (d >> (cnt - 1)) & 0x1;
+		mask = (1 << (32 - cnt)) - 1;
+		res = (d >> cnt) & mask;
+		if (cnt != 1)
+			res |= (d << (33 - cnt));
+		if (ACCESS_FLAG(F_CF)) {     /* carry flag is set */
+			res |= 1 << (32 - cnt);
+		}
+		CONDITIONAL_SET_FLAG(cf, F_CF);
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)),
+								 F_OF);
+		}
+	}
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ROL instruction and side effects.
+****************************************************************************/
+u8 rol_byte(u8 d, u8 s)
+{
+    register unsigned int res, cnt, mask;
+
+    /* rotate left */
+    /*
+       s is the rotate distance.  It varies from 0 - 8.
+       d is the byte object rotated.
+
+       have
+
+       CF  B_7 ... B_0
+
+       The new rotate is done mod 8.
+       Much simpler than the "rcl" or "rcr" operations.
+
+       IF n > 0
+       1) B_(7) .. B_(n)  <-  b_(8-(n+1)) .. b_(0)
+       2) B_(n-1) .. B_(0) <-  b_(7) .. b_(8-n)
+	 */
+    res = d;
+	if ((cnt = s % 8) != 0) {
+		/* B_(7) .. B_(n)  <-  b_(8-(n+1)) .. b_(0) */
+		res = (d << cnt);
+
+		/* B_(n-1) .. B_(0) <-  b_(7) .. b_(8-n) */
+		mask = (1 << cnt) - 1;
+		res |= (d >> (8 - cnt)) & mask;
+
+		/* set the new carry flag, Note that it is the low order
+		   bit of the result!!!                               */
+		CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+		/* OVERFLOW is set *IFF* s==1, then it is the
+		   xor of CF and the most significant bit.  Blecck. */
+		CONDITIONAL_SET_FLAG(s == 1 &&
+							 XOR2((res & 0x1) + ((res >> 6) & 0x2)),
+							 F_OF);
+	} if (s != 0) {
+		/* set the new carry flag, Note that it is the low order
+		   bit of the result!!!                               */
+		CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+	}
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ROL instruction and side effects.
+****************************************************************************/
+u16 rol_word(u16 d, u8 s)
+{
+    register unsigned int res, cnt, mask;
+
+	res = d;
+	if ((cnt = s % 16) != 0) {
+		res = (d << cnt);
+		mask = (1 << cnt) - 1;
+		res |= (d >> (16 - cnt)) & mask;
+		CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+		CONDITIONAL_SET_FLAG(s == 1 &&
+							 XOR2((res & 0x1) + ((res >> 14) & 0x2)),
+							 F_OF);
+	} if (s != 0) {
+		/* set the new carry flag, Note that it is the low order
+		   bit of the result!!!                               */
+		CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+	}
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ROL instruction and side effects.
+****************************************************************************/
+u32 rol_long(u32 d, u8 s)
+{
+    register u32 res, cnt, mask;
+
+	res = d;
+	if ((cnt = s % 32) != 0) {
+		res = (d << cnt);
+		mask = (1 << cnt) - 1;
+		res |= (d >> (32 - cnt)) & mask;
+		CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+		CONDITIONAL_SET_FLAG(s == 1 &&
+							 XOR2((res & 0x1) + ((res >> 30) & 0x2)),
+							 F_OF);
+	} if (s != 0) {
+		/* set the new carry flag, Note that it is the low order
+		   bit of the result!!!                               */
+		CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
+	}
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ROR instruction and side effects.
+****************************************************************************/
+u8 ror_byte(u8 d, u8 s)
+{
+    register unsigned int res, cnt, mask;
+
+    /* rotate right */
+    /*
+       s is the rotate distance.  It varies from 0 - 8.
+       d is the byte object rotated.
+
+       have
+
+       B_7 ... B_0
+
+       The rotate is done mod 8.
+
+       IF n > 0
+       1) B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_(n)
+       2) B_(7) .. B_(8-n) <-  b_(n-1) .. b_(0)
+	 */
+	res = d;
+	if ((cnt = s % 8) != 0) {           /* not a typo, do nada if cnt==0 */
+	/* B_(7) .. B_(8-n) <-  b_(n-1) .. b_(0) */
+	res = (d << (8 - cnt));
+
+	/* B_(8-(n+1)) .. B_(0)  <-  b_(7) .. b_(n) */
+	mask = (1 << (8 - cnt)) - 1;
+	res |= (d >> (cnt)) & mask;
+
+	/* set the new carry flag, Note that it is the low order
+	   bit of the result!!!                               */
+		CONDITIONAL_SET_FLAG(res & 0x80, F_CF);
+		/* OVERFLOW is set *IFF* s==1, then it is the
+	   xor of the two most significant bits.  Blecck. */
+		CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF);
+	} else if (s != 0) {
+		/* set the new carry flag, Note that it is the low order
+		   bit of the result!!!                               */
+		CONDITIONAL_SET_FLAG(res & 0x80, F_CF);
+	}
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ROR instruction and side effects.
+****************************************************************************/
+u16 ror_word(u16 d, u8 s)
+{
+    register unsigned int res, cnt, mask;
+
+	res = d;
+	if ((cnt = s % 16) != 0) {
+		res = (d << (16 - cnt));
+		mask = (1 << (16 - cnt)) - 1;
+		res |= (d >> (cnt)) & mask;
+		CONDITIONAL_SET_FLAG(res & 0x8000, F_CF);
+		CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF);
+	} else if (s != 0) {
+		/* set the new carry flag, Note that it is the low order
+		   bit of the result!!!                               */
+		CONDITIONAL_SET_FLAG(res & 0x8000, F_CF);
+	}
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the ROR instruction and side effects.
+****************************************************************************/
+u32 ror_long(u32 d, u8 s)
+{
+	register u32 res, cnt, mask;
+
+	res = d;
+	if ((cnt = s % 32) != 0) {
+		res = (d << (32 - cnt));
+		mask = (1 << (32 - cnt)) - 1;
+		res |= (d >> (cnt)) & mask;
+		CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF);
+		CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF);
+	} else if (s != 0) {
+		/* set the new carry flag, Note that it is the low order
+		   bit of the result!!!                               */
+		CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF);
+	}
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHL instruction and side effects.
+****************************************************************************/
+u8 shl_byte(u8 d, u8 s)
+{
+	unsigned int cnt, res, cf;
+
+	if (s < 8) {
+		cnt = s % 8;
+
+		/* last bit shifted out goes into carry flag */
+		if (cnt > 0) {
+			res = d << cnt;
+			cf = d & (1 << (8 - cnt));
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		} else {
+			res = (u8) d;
+		}
+
+		if (cnt == 1) {
+			/* Needs simplification. */
+			CONDITIONAL_SET_FLAG(
+									(((res & 0x80) == 0x80) ^
+									 (ACCESS_FLAG(F_CF) != 0)),
+			/* was (M.x86.R_FLG&F_CF)==F_CF)), */
+									F_OF);
+		} else {
+			CLEAR_FLAG(F_OF);
+		}
+	} else {
+		res = 0;
+		CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF);
+		CLEAR_FLAG(F_OF);
+		CLEAR_FLAG(F_SF);
+		SET_FLAG(F_PF);
+		SET_FLAG(F_ZF);
+    }
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHL instruction and side effects.
+****************************************************************************/
+u16 shl_word(u16 d, u8 s)
+{
+    unsigned int cnt, res, cf;
+
+	if (s < 16) {
+		cnt = s % 16;
+		if (cnt > 0) {
+			res = d << cnt;
+			cf = d & (1 << (16 - cnt));
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		} else {
+			res = (u16) d;
+		}
+
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG(
+									(((res & 0x8000) == 0x8000) ^
+									 (ACCESS_FLAG(F_CF) != 0)),
+									F_OF);
+	} else {
+			CLEAR_FLAG(F_OF);
+	}
+    } else {
+		res = 0;
+		CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF);
+		CLEAR_FLAG(F_OF);
+		CLEAR_FLAG(F_SF);
+		SET_FLAG(F_PF);
+		SET_FLAG(F_ZF);
+	}
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHL instruction and side effects.
+****************************************************************************/
+u32 shl_long(u32 d, u8 s)
+{
+	unsigned int cnt, res, cf;
+
+	if (s < 32) {
+		cnt = s % 32;
+		if (cnt > 0) {
+			res = d << cnt;
+			cf = d & (1 << (32 - cnt));
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		} else {
+			res = d;
+		}
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^
+								  (ACCESS_FLAG(F_CF) != 0)), F_OF);
+		} else {
+			CLEAR_FLAG(F_OF);
+		}
+	} else {
+		res = 0;
+		CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF);
+		CLEAR_FLAG(F_OF);
+		CLEAR_FLAG(F_SF);
+		SET_FLAG(F_PF);
+		SET_FLAG(F_ZF);
+	}
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHR instruction and side effects.
+****************************************************************************/
+u8 shr_byte(u8 d, u8 s)
+{
+	unsigned int cnt, res, cf;
+
+	if (s < 8) {
+		cnt = s % 8;
+		if (cnt > 0) {
+			cf = d & (1 << (cnt - 1));
+			res = d >> cnt;
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		} else {
+			res = (u8) d;
+		}
+
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF);
+		} else {
+			CLEAR_FLAG(F_OF);
+		}
+	} else {
+		res = 0;
+		CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF);
+		CLEAR_FLAG(F_OF);
+		CLEAR_FLAG(F_SF);
+		SET_FLAG(F_PF);
+		SET_FLAG(F_ZF);
+	}
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHR instruction and side effects.
+****************************************************************************/
+u16 shr_word(u16 d, u8 s)
+{
+	unsigned int cnt, res, cf;
+
+	if (s < 16) {
+		cnt = s % 16;
+		if (cnt > 0) {
+			cf = d & (1 << (cnt - 1));
+			res = d >> cnt;
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		} else {
+			res = d;
+		}
+
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF);
+	} else {
+			CLEAR_FLAG(F_OF);
+	}
+	} else {
+		res = 0;
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+		SET_FLAG(F_ZF);
+		CLEAR_FLAG(F_SF);
+		CLEAR_FLAG(F_PF);
+    }
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHR instruction and side effects.
+****************************************************************************/
+u32 shr_long(u32 d, u8 s)
+{
+	unsigned int cnt, res, cf;
+
+	if (s < 32) {
+		cnt = s % 32;
+		if (cnt > 0) {
+			cf = d & (1 << (cnt - 1));
+			res = d >> cnt;
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	} else {
+	    res = d;
+	}
+	if (cnt == 1) {
+			CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF);
+	} else {
+			CLEAR_FLAG(F_OF);
+	}
+    } else {
+	res = 0;
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+		SET_FLAG(F_ZF);
+		CLEAR_FLAG(F_SF);
+		CLEAR_FLAG(F_PF);
+    }
+    return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SAR instruction and side effects.
+****************************************************************************/
+u8 sar_byte(u8 d, u8 s)
+{
+	unsigned int cnt, res, cf, mask, sf;
+
+	res = d;
+	sf = d & 0x80;
+    cnt = s % 8;
+	if (cnt > 0 && cnt < 8) {
+		mask = (1 << (8 - cnt)) - 1;
+		cf = d & (1 << (cnt - 1));
+		res = (d >> cnt) & mask;
+		CONDITIONAL_SET_FLAG(cf, F_CF);
+		if (sf) {
+			res |= ~mask;
+		}
+		CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+		CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+    } else if (cnt >= 8) {
+	if (sf) {
+	    res = 0xff;
+			SET_FLAG(F_CF);
+			CLEAR_FLAG(F_ZF);
+			SET_FLAG(F_SF);
+			SET_FLAG(F_PF);
+		} else {
+			res = 0;
+			CLEAR_FLAG(F_CF);
+			SET_FLAG(F_ZF);
+			CLEAR_FLAG(F_SF);
+			CLEAR_FLAG(F_PF);
+		}
+	}
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SAR instruction and side effects.
+****************************************************************************/
+u16 sar_word(u16 d, u8 s)
+{
+    unsigned int cnt, res, cf, mask, sf;
+
+    sf = d & 0x8000;
+    cnt = s % 16;
+	res = d;
+	if (cnt > 0 && cnt < 16) {
+	mask = (1 << (16 - cnt)) - 1;
+	cf = d & (1 << (cnt - 1));
+	res = (d >> cnt) & mask;
+		CONDITIONAL_SET_FLAG(cf, F_CF);
+	if (sf) {
+	    res |= ~mask;
+	}
+		CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+		CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+		CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+    } else if (cnt >= 16) {
+	if (sf) {
+	    res = 0xffff;
+			SET_FLAG(F_CF);
+			CLEAR_FLAG(F_ZF);
+			SET_FLAG(F_SF);
+			SET_FLAG(F_PF);
+	} else {
+	    res = 0;
+			CLEAR_FLAG(F_CF);
+			SET_FLAG(F_ZF);
+			CLEAR_FLAG(F_SF);
+			CLEAR_FLAG(F_PF);
+	}
+    }
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SAR instruction and side effects.
+****************************************************************************/
+u32 sar_long(u32 d, u8 s)
+{
+    u32 cnt, res, cf, mask, sf;
+
+    sf = d & 0x80000000;
+    cnt = s % 32;
+	res = d;
+	if (cnt > 0 && cnt < 32) {
+	mask = (1 << (32 - cnt)) - 1;
+		cf = d & (1 << (cnt - 1));
+	res = (d >> cnt) & mask;
+		CONDITIONAL_SET_FLAG(cf, F_CF);
+	if (sf) {
+	    res |= ~mask;
+	}
+		CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+		CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+		CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+    } else if (cnt >= 32) {
+	if (sf) {
+	    res = 0xffffffff;
+			SET_FLAG(F_CF);
+			CLEAR_FLAG(F_ZF);
+			SET_FLAG(F_SF);
+			SET_FLAG(F_PF);
+		} else {
+			res = 0;
+			CLEAR_FLAG(F_CF);
+			SET_FLAG(F_ZF);
+			CLEAR_FLAG(F_SF);
+			CLEAR_FLAG(F_PF);
+		}
+	}
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHLD instruction and side effects.
+****************************************************************************/
+u16 shld_word (u16 d, u16 fill, u8 s)
+{
+	unsigned int cnt, res, cf;
+
+	if (s < 16) {
+		cnt = s % 16;
+		if (cnt > 0) {
+			res = (d << cnt) | (fill >> (16-cnt));
+			cf = d & (1 << (16 - cnt));
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		} else {
+			res = d;
+		}
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^
+								  (ACCESS_FLAG(F_CF) != 0)), F_OF);
+		} else {
+			CLEAR_FLAG(F_OF);
+		}
+	} else {
+		res = 0;
+		CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF);
+		CLEAR_FLAG(F_OF);
+		CLEAR_FLAG(F_SF);
+		SET_FLAG(F_PF);
+		SET_FLAG(F_ZF);
+	}
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHLD instruction and side effects.
+****************************************************************************/
+u32 shld_long (u32 d, u32 fill, u8 s)
+{
+	unsigned int cnt, res, cf;
+
+	if (s < 32) {
+		cnt = s % 32;
+		if (cnt > 0) {
+			res = (d << cnt) | (fill >> (32-cnt));
+			cf = d & (1 << (32 - cnt));
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		} else {
+			res = d;
+		}
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^
+								  (ACCESS_FLAG(F_CF) != 0)), F_OF);
+		} else {
+			CLEAR_FLAG(F_OF);
+		}
+	} else {
+		res = 0;
+		CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF);
+		CLEAR_FLAG(F_OF);
+		CLEAR_FLAG(F_SF);
+		SET_FLAG(F_PF);
+		SET_FLAG(F_ZF);
+	}
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHRD instruction and side effects.
+****************************************************************************/
+u16 shrd_word (u16 d, u16 fill, u8 s)
+{
+	unsigned int cnt, res, cf;
+
+	if (s < 16) {
+		cnt = s % 16;
+		if (cnt > 0) {
+			cf = d & (1 << (cnt - 1));
+			res = (d >> cnt) | (fill << (16 - cnt));
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		} else {
+			res = d;
+		}
+
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF);
+	} else {
+			CLEAR_FLAG(F_OF);
+	}
+	} else {
+		res = 0;
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+		SET_FLAG(F_ZF);
+		CLEAR_FLAG(F_SF);
+		CLEAR_FLAG(F_PF);
+    }
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SHRD instruction and side effects.
+****************************************************************************/
+u32 shrd_long (u32 d, u32 fill, u8 s)
+{
+	unsigned int cnt, res, cf;
+
+	if (s < 32) {
+		cnt = s % 32;
+		if (cnt > 0) {
+			cf = d & (1 << (cnt - 1));
+			res = (d >> cnt) | (fill << (32 - cnt));
+			CONDITIONAL_SET_FLAG(cf, F_CF);
+			CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+			CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+			CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+		} else {
+			res = d;
+		}
+		if (cnt == 1) {
+			CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF);
+	} else {
+			CLEAR_FLAG(F_OF);
+	}
+	} else {
+		res = 0;
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+		SET_FLAG(F_ZF);
+		CLEAR_FLAG(F_SF);
+		CLEAR_FLAG(F_PF);
+    }
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SBB instruction and side effects.
+****************************************************************************/
+u8 sbb_byte(u8 d, u8 s)
+{
+    register u32 res;   /* all operands in native machine order */
+    register u32 bc;
+
+	if (ACCESS_FLAG(F_CF))
+		res = d - s - 1;
+	else
+		res = d - s;
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+	bc = (res & (~d | s)) | (~d & s);
+	CONDITIONAL_SET_FLAG(bc & 0x80, F_CF);
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SBB instruction and side effects.
+****************************************************************************/
+u16 sbb_word(u16 d, u16 s)
+{
+    register u32 res;   /* all operands in native machine order */
+    register u32 bc;
+
+	if (ACCESS_FLAG(F_CF))
+	res = d - s - 1;
+    else
+	res = d - s;
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+	bc = (res & (~d | s)) | (~d & s);
+	CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF);
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SBB instruction and side effects.
+****************************************************************************/
+u32 sbb_long(u32 d, u32 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 bc;
+
+	if (ACCESS_FLAG(F_CF))
+	res = d - s - 1;
+    else
+	res = d - s;
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+	bc = (res & (~d | s)) | (~d & s);
+	CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF);
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SUB instruction and side effects.
+****************************************************************************/
+u8 sub_byte(u8 d, u8 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 bc;
+
+	res = d - s;
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+	bc = (res & (~d | s)) | (~d & s);
+	CONDITIONAL_SET_FLAG(bc & 0x80, F_CF);
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return (u8)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SUB instruction and side effects.
+****************************************************************************/
+u16 sub_word(u16 d, u16 s)
+{
+    register u32 res;   /* all operands in native machine order */
+    register u32 bc;
+
+    res = d - s;
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+	bc = (res & (~d | s)) | (~d & s);
+	CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF);
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return (u16)res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the SUB instruction and side effects.
+****************************************************************************/
+u32 sub_long(u32 d, u32 s)
+{
+	register u32 res;   /* all operands in native machine order */
+	register u32 bc;
+
+	res = d - s;
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+
+	/* calculate the borrow chain.  See note at top */
+	bc = (res & (~d | s)) | (~d & s);
+	CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF);
+	CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
+	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the TEST instruction and side effects.
+****************************************************************************/
+void test_byte(u8 d, u8 s)
+{
+    register u32 res;   /* all operands in native machine order */
+
+    res = d & s;
+
+	CLEAR_FLAG(F_OF);
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+    /* AF == dont care */
+	CLEAR_FLAG(F_CF);
+}
+
+/****************************************************************************
+REMARKS:
+Implements the TEST instruction and side effects.
+****************************************************************************/
+void test_word(u16 d, u16 s)
+{
+	register u32 res;   /* all operands in native machine order */
+
+	res = d & s;
+
+	CLEAR_FLAG(F_OF);
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	/* AF == dont care */
+	CLEAR_FLAG(F_CF);
+}
+
+/****************************************************************************
+REMARKS:
+Implements the TEST instruction and side effects.
+****************************************************************************/
+void test_long(u32 d, u32 s)
+{
+	register u32 res;   /* all operands in native machine order */
+
+	res = d & s;
+
+	CLEAR_FLAG(F_OF);
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	/* AF == dont care */
+	CLEAR_FLAG(F_CF);
+}
+
+/****************************************************************************
+REMARKS:
+Implements the XOR instruction and side effects.
+****************************************************************************/
+u8 xor_byte(u8 d, u8 s)
+{
+	register u8 res;    /* all operands in native machine order */
+
+	res = d ^ s;
+	CLEAR_FLAG(F_OF);
+	CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res), F_PF);
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the XOR instruction and side effects.
+****************************************************************************/
+u16 xor_word(u16 d, u16 s)
+{
+	register u16 res;   /* all operands in native machine order */
+
+	res = d ^ s;
+	CLEAR_FLAG(F_OF);
+	CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the XOR instruction and side effects.
+****************************************************************************/
+u32 xor_long(u32 d, u32 s)
+{
+	register u32 res;   /* all operands in native machine order */
+
+	res = d ^ s;
+	CLEAR_FLAG(F_OF);
+	CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
+	CONDITIONAL_SET_FLAG(res == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF);
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the IMUL instruction and side effects.
+****************************************************************************/
+void imul_byte(u8 s)
+{
+	s16 res = (s16)((s8)M.x86.R_AL * (s8)s);
+
+	M.x86.R_AX = res;
+	if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) ||
+		((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	} else {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Implements the IMUL instruction and side effects.
+****************************************************************************/
+void imul_word(u16 s)
+{
+	s32 res = (s16)M.x86.R_AX * (s16)s;
+
+	M.x86.R_AX = (u16)res;
+	M.x86.R_DX = (u16)(res >> 16);
+	if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x00) ||
+		((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFF)) {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	} else {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Implements the IMUL instruction and side effects.
+****************************************************************************/
+void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s)
+{
+#ifdef	__HAS_LONG_LONG__
+	s64 res = (s32)d * (s32)s;
+
+	*res_lo = (u32)res;
+	*res_hi = (u32)(res >> 32);
+#else
+	u32	d_lo,d_hi,d_sign;
+	u32	s_lo,s_hi,s_sign;
+	u32	rlo_lo,rlo_hi,rhi_lo;
+
+	if ((d_sign = d & 0x80000000) != 0)
+		d = -d;
+	d_lo = d & 0xFFFF;
+	d_hi = d >> 16;
+	if ((s_sign = s & 0x80000000) != 0)
+		s = -s;
+	s_lo = s & 0xFFFF;
+	s_hi = s >> 16;
+	rlo_lo = d_lo * s_lo;
+	rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16);
+	rhi_lo = d_hi * s_hi + (rlo_hi >> 16);
+	*res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF);
+	*res_hi = rhi_lo;
+	if (d_sign != s_sign) {
+		d = ~*res_lo;
+		s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16);
+		*res_lo = ~*res_lo+1;
+		*res_hi = ~*res_hi+(s >> 16);
+		}
+#endif
+}
+
+/****************************************************************************
+REMARKS:
+Implements the IMUL instruction and side effects.
+****************************************************************************/
+void imul_long(u32 s)
+{
+	imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s);
+	if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00) ||
+		((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFF)) {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	} else {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Implements the MUL instruction and side effects.
+****************************************************************************/
+void mul_byte(u8 s)
+{
+	u16 res = (u16)(M.x86.R_AL * s);
+
+	M.x86.R_AX = res;
+	if (M.x86.R_AH == 0) {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	} else {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+	}
+}
+
+/****************************************************************************
+REMARKS:
+Implements the MUL instruction and side effects.
+****************************************************************************/
+void mul_word(u16 s)
+{
+	u32 res = M.x86.R_AX * s;
+
+	M.x86.R_AX = (u16)res;
+	M.x86.R_DX = (u16)(res >> 16);
+	if (M.x86.R_DX == 0) {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+    } else {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+    }
+}
+
+/****************************************************************************
+REMARKS:
+Implements the MUL instruction and side effects.
+****************************************************************************/
+void mul_long(u32 s)
+{
+#ifdef	__HAS_LONG_LONG__
+	u64 res = (u32)M.x86.R_EAX * (u32)s;
+
+	M.x86.R_EAX = (u32)res;
+	M.x86.R_EDX = (u32)(res >> 32);
+#else
+	u32	a,a_lo,a_hi;
+	u32	s_lo,s_hi;
+	u32	rlo_lo,rlo_hi,rhi_lo;
+
+	a = M.x86.R_EAX;
+	a_lo = a & 0xFFFF;
+	a_hi = a >> 16;
+	s_lo = s & 0xFFFF;
+	s_hi = s >> 16;
+	rlo_lo = a_lo * s_lo;
+	rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16);
+	rhi_lo = a_hi * s_hi + (rlo_hi >> 16);
+	M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF);
+	M.x86.R_EDX = rhi_lo;
+#endif
+
+	if (M.x86.R_EDX == 0) {
+		CLEAR_FLAG(F_CF);
+		CLEAR_FLAG(F_OF);
+	} else {
+		SET_FLAG(F_CF);
+		SET_FLAG(F_OF);
+    }
+}
+
+/****************************************************************************
+REMARKS:
+Implements the IDIV instruction and side effects.
+****************************************************************************/
+void idiv_byte(u8 s)
+{
+    s32 dvd, div, mod;
+
+	dvd = (s16)M.x86.R_AX;
+	if (s == 0) {
+		x86emu_intr_raise(0);
+	return;
+	}
+	div = dvd / (s8)s;
+	mod = dvd % (s8)s;
+	if (abs(div) > 0x7f) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	M.x86.R_AL = (s8) div;
+	M.x86.R_AH = (s8) mod;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the IDIV instruction and side effects.
+****************************************************************************/
+void idiv_word(u16 s)
+{
+	s32 dvd, div, mod;
+
+	dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX;
+	if (s == 0) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	div = dvd / (s16)s;
+	mod = dvd % (s16)s;
+	if (abs(div) > 0x7fff) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_SF);
+	CONDITIONAL_SET_FLAG(div == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF);
+
+	M.x86.R_AX = (u16)div;
+	M.x86.R_DX = (u16)mod;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the IDIV instruction and side effects.
+****************************************************************************/
+void idiv_long(u32 s)
+{
+#ifdef	__HAS_LONG_LONG__
+	s64 dvd, div, mod;
+
+	dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX;
+	if (s == 0) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	div = dvd / (s32)s;
+	mod = dvd % (s32)s;
+	if (abs(div) > 0x7fffffff) {
+		x86emu_intr_raise(0);
+		return;
+	}
+#else
+	s32 div = 0, mod;
+	s32 h_dvd = M.x86.R_EDX;
+	u32 l_dvd = M.x86.R_EAX;
+	u32 abs_s = s & 0x7FFFFFFF;
+	u32 abs_h_dvd = h_dvd & 0x7FFFFFFF;
+	u32 h_s = abs_s >> 1;
+	u32 l_s = abs_s << 31;
+	int counter = 31;
+	int carry;
+
+	if (s == 0) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	do {
+		div <<= 1;
+		carry = (l_dvd >= l_s) ? 0 : 1;
+
+		if (abs_h_dvd < (h_s + carry)) {
+			h_s >>= 1;
+			l_s = abs_s << (--counter);
+			continue;
+		} else {
+			abs_h_dvd -= (h_s + carry);
+			l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1)
+				: (l_dvd - l_s);
+			h_s >>= 1;
+			l_s = abs_s << (--counter);
+			div |= 1;
+			continue;
+		}
+
+	} while (counter > -1);
+	/* overflow */
+	if (abs_h_dvd || (l_dvd > abs_s)) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	/* sign */
+	div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000));
+	mod = l_dvd;
+
+#endif
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CLEAR_FLAG(F_SF);
+	SET_FLAG(F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF);
+
+	M.x86.R_EAX = (u32)div;
+	M.x86.R_EDX = (u32)mod;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the DIV instruction and side effects.
+****************************************************************************/
+void div_byte(u8 s)
+{
+	u32 dvd, div, mod;
+
+	dvd = M.x86.R_AX;
+    if (s == 0) {
+		x86emu_intr_raise(0);
+	return;
+    }
+	div = dvd / (u8)s;
+	mod = dvd % (u8)s;
+	if (abs(div) > 0xff) {
+		x86emu_intr_raise(0);
+	return;
+	}
+	M.x86.R_AL = (u8)div;
+	M.x86.R_AH = (u8)mod;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the DIV instruction and side effects.
+****************************************************************************/
+void div_word(u16 s)
+{
+	u32 dvd, div, mod;
+
+	dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX;
+	if (s == 0) {
+		x86emu_intr_raise(0);
+	return;
+    }
+	div = dvd / (u16)s;
+	mod = dvd % (u16)s;
+	if (abs(div) > 0xffff) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_SF);
+	CONDITIONAL_SET_FLAG(div == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF);
+
+	M.x86.R_AX = (u16)div;
+	M.x86.R_DX = (u16)mod;
+}
+
+/****************************************************************************
+REMARKS:
+Implements the DIV instruction and side effects.
+****************************************************************************/
+void div_long(u32 s)
+{
+#ifdef	__HAS_LONG_LONG__
+	u64 dvd, div, mod;
+
+	dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX;
+	if (s == 0) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	div = dvd / (u32)s;
+	mod = dvd % (u32)s;
+	if (abs(div) > 0xffffffff) {
+		x86emu_intr_raise(0);
+		return;
+	}
+#else
+	s32 div = 0, mod;
+	s32 h_dvd = M.x86.R_EDX;
+	u32 l_dvd = M.x86.R_EAX;
+
+	u32 h_s = s;
+	u32 l_s = 0;
+	int counter = 32;
+	int carry;
+
+	if (s == 0) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	do {
+		div <<= 1;
+		carry = (l_dvd >= l_s) ? 0 : 1;
+
+		if (h_dvd < (h_s + carry)) {
+			h_s >>= 1;
+			l_s = s << (--counter);
+			continue;
+		} else {
+			h_dvd -= (h_s + carry);
+			l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1)
+				: (l_dvd - l_s);
+			h_s >>= 1;
+			l_s = s << (--counter);
+			div |= 1;
+			continue;
+		}
+
+	} while (counter > -1);
+	/* overflow */
+	if (h_dvd || (l_dvd > s)) {
+		x86emu_intr_raise(0);
+		return;
+	}
+	mod = l_dvd;
+#endif
+	CLEAR_FLAG(F_CF);
+	CLEAR_FLAG(F_AF);
+	CLEAR_FLAG(F_SF);
+	SET_FLAG(F_ZF);
+	CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF);
+
+	M.x86.R_EAX = (u32)div;
+	M.x86.R_EDX = (u32)mod;
+}
+
+#endif	/* __HAVE_INLINE_ASSEMBLER__ */
+
+/****************************************************************************
+REMARKS:
+Implements the IN string instruction and side effects.
+****************************************************************************/
+void ins(int size)
+{
+	int inc = size;
+
+	if (ACCESS_FLAG(F_DF)) {
+		inc = -size;
+	}
+	if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
+	/* dont care whether REPE or REPNE */
+	/* in until CX is ZERO. */
+		u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ?
+					 M.x86.R_ECX : M.x86.R_CX);
+	switch (size) {
+	  case 1:
+	    while (count--) {
+				store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,
+									(*sys_inb)(M.x86.R_DX));
+				M.x86.R_DI += inc;
+	    }
+	    break;
+
+	  case 2:
+	    while (count--) {
+				store_data_word_abs(M.x86.R_ES, M.x86.R_DI,
+									(*sys_inw)(M.x86.R_DX));
+				M.x86.R_DI += inc;
+	    }
+	    break;
+	  case 4:
+	    while (count--) {
+				store_data_long_abs(M.x86.R_ES, M.x86.R_DI,
+									(*sys_inl)(M.x86.R_DX));
+				M.x86.R_DI += inc;
+		break;
+	    }
+	}
+		M.x86.R_CX = 0;
+		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			M.x86.R_ECX = 0;
+	}
+		M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+    } else {
+	switch (size) {
+	  case 1:
+			store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,
+								(*sys_inb)(M.x86.R_DX));
+	    break;
+	  case 2:
+			store_data_word_abs(M.x86.R_ES, M.x86.R_DI,
+								(*sys_inw)(M.x86.R_DX));
+	    break;
+	  case 4:
+			store_data_long_abs(M.x86.R_ES, M.x86.R_DI,
+								(*sys_inl)(M.x86.R_DX));
+	    break;
+	}
+		M.x86.R_DI += inc;
+    }
+}
+
+/****************************************************************************
+REMARKS:
+Implements the OUT string instruction and side effects.
+****************************************************************************/
+void outs(int size)
+{
+    int inc = size;
+
+	if (ACCESS_FLAG(F_DF)) {
+	inc = -size;
+    }
+	if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
+	/* dont care whether REPE or REPNE */
+	/* out until CX is ZERO. */
+		u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ?
+					 M.x86.R_ECX : M.x86.R_CX);
+	switch (size) {
+	  case 1:
+	    while (count--) {
+				(*sys_outb)(M.x86.R_DX,
+						 fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI));
+				M.x86.R_SI += inc;
+	    }
+	    break;
+
+	  case 2:
+	    while (count--) {
+				(*sys_outw)(M.x86.R_DX,
+						 fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI));
+				M.x86.R_SI += inc;
+	    }
+	    break;
+	  case 4:
+	    while (count--) {
+				(*sys_outl)(M.x86.R_DX,
+						 fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI));
+				M.x86.R_SI += inc;
+		break;
+	    }
+	}
+		M.x86.R_CX = 0;
+		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
+			M.x86.R_ECX = 0;
+	}
+		M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
+    } else {
+	switch (size) {
+	  case 1:
+			(*sys_outb)(M.x86.R_DX,
+					 fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI));
+	    break;
+	  case 2:
+			(*sys_outw)(M.x86.R_DX,
+					 fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI));
+	    break;
+	  case 4:
+			(*sys_outl)(M.x86.R_DX,
+					 fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI));
+	    break;
+	}
+		M.x86.R_SI += inc;
+    }
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- Address to fetch word from
+
+REMARKS:
+Fetches a word from emulator memory using an absolute address.
+****************************************************************************/
+u16 mem_access_word(int addr)
+{
+DB(	if (CHECK_MEM_ACCESS())
+	  x86emu_check_mem_access(addr);)
+	return (*sys_rdw)(addr);
+}
+
+/****************************************************************************
+REMARKS:
+Pushes a word onto the stack.
+
+NOTE: Do not inline this, as (*sys_wrX) is already inline!
+****************************************************************************/
+void push_word(u16 w)
+{
+DB(	if (CHECK_SP_ACCESS())
+	  x86emu_check_sp_access();)
+	M.x86.R_SP -= 2;
+	(*sys_wrw)(((u32)M.x86.R_SS << 4)  + M.x86.R_SP, w);
+}
+
+/****************************************************************************
+REMARKS:
+Pushes a long onto the stack.
+
+NOTE: Do not inline this, as (*sys_wrX) is already inline!
+****************************************************************************/
+void push_long(u32 w)
+{
+DB(	if (CHECK_SP_ACCESS())
+	  x86emu_check_sp_access();)
+	M.x86.R_SP -= 4;
+	(*sys_wrl)(((u32)M.x86.R_SS << 4)  + M.x86.R_SP, w);
+}
+
+/****************************************************************************
+REMARKS:
+Pops a word from the stack.
+
+NOTE: Do not inline this, as (*sys_rdX) is already inline!
+****************************************************************************/
+u16 pop_word(void)
+{
+	register u16 res;
+
+DB(	if (CHECK_SP_ACCESS())
+	  x86emu_check_sp_access();)
+	res = (*sys_rdw)(((u32)M.x86.R_SS << 4)  + M.x86.R_SP);
+	M.x86.R_SP += 2;
+	return res;
+}
+
+/****************************************************************************
+REMARKS:
+Pops a long from the stack.
+
+NOTE: Do not inline this, as (*sys_rdX) is already inline!
+****************************************************************************/
+u32 pop_long(void)
+{
+    register u32 res;
+
+DB(	if (CHECK_SP_ACCESS())
+	  x86emu_check_sp_access();)
+	res = (*sys_rdl)(((u32)M.x86.R_SS << 4)  + M.x86.R_SP);
+	M.x86.R_SP += 4;
+    return res;
+}
+
+#ifdef	__HAVE_INLINE_ASSEMBLER__
+
+u16 aaa_word (u16 d)
+{ return aaa_word_asm(&M.x86.R_EFLG,d); }
+
+u16 aas_word (u16 d)
+{ return aas_word_asm(&M.x86.R_EFLG,d); }
+
+u16 aad_word (u16 d)
+{ return aad_word_asm(&M.x86.R_EFLG,d); }
+
+u16 aam_word (u8 d)
+{ return aam_word_asm(&M.x86.R_EFLG,d); }
+
+u8 adc_byte (u8 d, u8 s)
+{ return adc_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 adc_word (u16 d, u16 s)
+{ return adc_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 adc_long (u32 d, u32 s)
+{ return adc_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 add_byte (u8 d, u8 s)
+{ return add_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 add_word (u16 d, u16 s)
+{ return add_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 add_long (u32 d, u32 s)
+{ return add_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 and_byte (u8 d, u8 s)
+{ return and_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 and_word (u16 d, u16 s)
+{ return and_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 and_long (u32 d, u32 s)
+{ return and_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 cmp_byte (u8 d, u8 s)
+{ return cmp_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 cmp_word (u16 d, u16 s)
+{ return cmp_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 cmp_long (u32 d, u32 s)
+{ return cmp_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 daa_byte (u8 d)
+{ return daa_byte_asm(&M.x86.R_EFLG,d); }
+
+u8 das_byte (u8 d)
+{ return das_byte_asm(&M.x86.R_EFLG,d); }
+
+u8 dec_byte (u8 d)
+{ return dec_byte_asm(&M.x86.R_EFLG,d); }
+
+u16 dec_word (u16 d)
+{ return dec_word_asm(&M.x86.R_EFLG,d); }
+
+u32 dec_long (u32 d)
+{ return dec_long_asm(&M.x86.R_EFLG,d); }
+
+u8 inc_byte (u8 d)
+{ return inc_byte_asm(&M.x86.R_EFLG,d); }
+
+u16 inc_word (u16 d)
+{ return inc_word_asm(&M.x86.R_EFLG,d); }
+
+u32 inc_long (u32 d)
+{ return inc_long_asm(&M.x86.R_EFLG,d); }
+
+u8 or_byte (u8 d, u8 s)
+{ return or_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 or_word (u16 d, u16 s)
+{ return or_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 or_long (u32 d, u32 s)
+{ return or_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 neg_byte (u8 s)
+{ return neg_byte_asm(&M.x86.R_EFLG,s); }
+
+u16 neg_word (u16 s)
+{ return neg_word_asm(&M.x86.R_EFLG,s); }
+
+u32 neg_long (u32 s)
+{ return neg_long_asm(&M.x86.R_EFLG,s); }
+
+u8 not_byte (u8 s)
+{ return not_byte_asm(&M.x86.R_EFLG,s); }
+
+u16 not_word (u16 s)
+{ return not_word_asm(&M.x86.R_EFLG,s); }
+
+u32 not_long (u32 s)
+{ return not_long_asm(&M.x86.R_EFLG,s); }
+
+u8 rcl_byte (u8 d, u8 s)
+{ return rcl_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 rcl_word (u16 d, u8 s)
+{ return rcl_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 rcl_long (u32 d, u8 s)
+{ return rcl_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 rcr_byte (u8 d, u8 s)
+{ return rcr_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 rcr_word (u16 d, u8 s)
+{ return rcr_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 rcr_long (u32 d, u8 s)
+{ return rcr_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 rol_byte (u8 d, u8 s)
+{ return rol_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 rol_word (u16 d, u8 s)
+{ return rol_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 rol_long (u32 d, u8 s)
+{ return rol_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 ror_byte (u8 d, u8 s)
+{ return ror_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 ror_word (u16 d, u8 s)
+{ return ror_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 ror_long (u32 d, u8 s)
+{ return ror_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 shl_byte (u8 d, u8 s)
+{ return shl_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 shl_word (u16 d, u8 s)
+{ return shl_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 shl_long (u32 d, u8 s)
+{ return shl_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 shr_byte (u8 d, u8 s)
+{ return shr_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 shr_word (u16 d, u8 s)
+{ return shr_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 shr_long (u32 d, u8 s)
+{ return shr_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 sar_byte (u8 d, u8 s)
+{ return sar_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 sar_word (u16 d, u8 s)
+{ return sar_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 sar_long (u32 d, u8 s)
+{ return sar_long_asm(&M.x86.R_EFLG,d,s); }
+
+u16 shld_word (u16 d, u16 fill, u8 s)
+{ return shld_word_asm(&M.x86.R_EFLG,d,fill,s); }
+
+u32 shld_long (u32 d, u32 fill, u8 s)
+{ return shld_long_asm(&M.x86.R_EFLG,d,fill,s); }
+
+u16 shrd_word (u16 d, u16 fill, u8 s)
+{ return shrd_word_asm(&M.x86.R_EFLG,d,fill,s); }
+
+u32 shrd_long (u32 d, u32 fill, u8 s)
+{ return shrd_long_asm(&M.x86.R_EFLG,d,fill,s); }
+
+u8 sbb_byte (u8 d, u8 s)
+{ return sbb_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 sbb_word (u16 d, u16 s)
+{ return sbb_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 sbb_long (u32 d, u32 s)
+{ return sbb_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 sub_byte (u8 d, u8 s)
+{ return sub_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 sub_word (u16 d, u16 s)
+{ return sub_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 sub_long (u32 d, u32 s)
+{ return sub_long_asm(&M.x86.R_EFLG,d,s); }
+
+void test_byte (u8 d, u8 s)
+{ test_byte_asm(&M.x86.R_EFLG,d,s); }
+
+void test_word (u16 d, u16 s)
+{ test_word_asm(&M.x86.R_EFLG,d,s); }
+
+void test_long (u32 d, u32 s)
+{ test_long_asm(&M.x86.R_EFLG,d,s); }
+
+u8 xor_byte (u8 d, u8 s)
+{ return xor_byte_asm(&M.x86.R_EFLG,d,s); }
+
+u16 xor_word (u16 d, u16 s)
+{ return xor_word_asm(&M.x86.R_EFLG,d,s); }
+
+u32 xor_long (u32 d, u32 s)
+{ return xor_long_asm(&M.x86.R_EFLG,d,s); }
+
+void imul_byte (u8 s)
+{ imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); }
+
+void imul_word (u16 s)
+{ imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); }
+
+void imul_long (u32 s)
+{ imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); }
+
+void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s)
+{ imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s); }
+
+void mul_byte (u8 s)
+{ mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); }
+
+void mul_word (u16 s)
+{ mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); }
+
+void mul_long (u32 s)
+{ mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); }
+
+void idiv_byte (u8 s)
+{ idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); }
+
+void idiv_word (u16 s)
+{ idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); }
+
+void idiv_long (u32 s)
+{ idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); }
+
+void div_byte (u8 s)
+{ div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); }
+
+void div_word (u16 s)
+{ div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); }
+
+void div_long (u32 s)
+{ div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); }
+
+#endif
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/sys.c b/board/MAI/bios_emulator/scitech/src/x86emu/sys.c
new file mode 100755
index 0000000..afe58f8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/sys.c
@@ -0,0 +1,658 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  This file includes subroutines which are related to
+*				programmed I/O and memory access. Included in this module
+*				are default functions with limited usefulness. For real
+*				uses these functions will most likely be overriden by the
+*				user library.
+*
+****************************************************************************/
+
+#include "x86emu.h"
+#include "x86emu/regs.h"
+#include "x86emu/debug.h"
+#include "x86emu/prim_ops.h"
+#include <string.h>
+
+/*------------------------- Global Variables ------------------------------*/
+
+X86EMU_sysEnv		_X86EMU_env;		/* Global emulator machine state */
+X86EMU_intrFuncs	_X86EMU_intrTab[256];
+
+/*----------------------------- Implementation ----------------------------*/
+#ifdef __alpha__
+/* to cope with broken egcs-1.1.2 :-(((( */
+
+/*
+ * inline functions to do unaligned accesses
+ * from linux/include/asm-alpha/unaligned.h
+ */
+
+/*
+ * EGCS 1.1 knows about arbitrary unaligned loads.  Define some
+ * packed structures to talk about such things with.
+ */
+
+#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91
+struct __una_u64 { unsigned long  x __attribute__((packed)); };
+struct __una_u32 { unsigned int   x __attribute__((packed)); };
+struct __una_u16 { unsigned short x __attribute__((packed)); };
+#endif
+
+static __inline__ unsigned long ldq_u(unsigned long * r11)
+{
+#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91
+	const struct __una_u64 *ptr = (const struct __una_u64 *) r11;
+	return ptr->x;
+#else
+	unsigned long r1,r2;
+	__asm__("ldq_u %0,%3\n\t"
+		"ldq_u %1,%4\n\t"
+		"extql %0,%2,%0\n\t"
+		"extqh %1,%2,%1"
+		:"=&r" (r1), "=&r" (r2)
+		:"r" (r11),
+		 "m" (*r11),
+		 "m" (*(const unsigned long *)(7+(char *) r11)));
+	return r1 | r2;
+#endif
+}
+
+static __inline__ unsigned long ldl_u(unsigned int * r11)
+{
+#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91
+	const struct __una_u32 *ptr = (const struct __una_u32 *) r11;
+	return ptr->x;
+#else
+	unsigned long r1,r2;
+	__asm__("ldq_u %0,%3\n\t"
+		"ldq_u %1,%4\n\t"
+		"extll %0,%2,%0\n\t"
+		"extlh %1,%2,%1"
+		:"=&r" (r1), "=&r" (r2)
+		:"r" (r11),
+		 "m" (*r11),
+		 "m" (*(const unsigned long *)(3+(char *) r11)));
+	return r1 | r2;
+#endif
+}
+
+static __inline__ unsigned long ldw_u(unsigned short * r11)
+{
+#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91
+	const struct __una_u16 *ptr = (const struct __una_u16 *) r11;
+	return ptr->x;
+#else
+	unsigned long r1,r2;
+	__asm__("ldq_u %0,%3\n\t"
+		"ldq_u %1,%4\n\t"
+		"extwl %0,%2,%0\n\t"
+		"extwh %1,%2,%1"
+		:"=&r" (r1), "=&r" (r2)
+		:"r" (r11),
+		 "m" (*r11),
+		 "m" (*(const unsigned long *)(1+(char *) r11)));
+	return r1 | r2;
+#endif
+}
+
+/*
+ * Elemental unaligned stores
+ */
+
+static __inline__ void stq_u(unsigned long r5, unsigned long * r11)
+{
+#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91
+	struct __una_u64 *ptr = (struct __una_u64 *) r11;
+	ptr->x = r5;
+#else
+	unsigned long r1,r2,r3,r4;
+
+	__asm__("ldq_u %3,%1\n\t"
+		"ldq_u %2,%0\n\t"
+		"insqh %6,%7,%5\n\t"
+		"insql %6,%7,%4\n\t"
+		"mskqh %3,%7,%3\n\t"
+		"mskql %2,%7,%2\n\t"
+		"bis %3,%5,%3\n\t"
+		"bis %2,%4,%2\n\t"
+		"stq_u %3,%1\n\t"
+		"stq_u %2,%0"
+		:"=m" (*r11),
+		 "=m" (*(unsigned long *)(7+(char *) r11)),
+		 "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4)
+		:"r" (r5), "r" (r11));
+#endif
+}
+
+static __inline__ void stl_u(unsigned long r5, unsigned int * r11)
+{
+#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91
+	struct __una_u32 *ptr = (struct __una_u32 *) r11;
+	ptr->x = r5;
+#else
+	unsigned long r1,r2,r3,r4;
+
+	__asm__("ldq_u %3,%1\n\t"
+		"ldq_u %2,%0\n\t"
+		"inslh %6,%7,%5\n\t"
+		"insll %6,%7,%4\n\t"
+		"msklh %3,%7,%3\n\t"
+		"mskll %2,%7,%2\n\t"
+		"bis %3,%5,%3\n\t"
+		"bis %2,%4,%2\n\t"
+		"stq_u %3,%1\n\t"
+		"stq_u %2,%0"
+		:"=m" (*r11),
+		 "=m" (*(unsigned long *)(3+(char *) r11)),
+		 "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4)
+		:"r" (r5), "r" (r11));
+#endif
+}
+
+static __inline__ void stw_u(unsigned long r5, unsigned short * r11)
+{
+#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91
+	struct __una_u16 *ptr = (struct __una_u16 *) r11;
+	ptr->x = r5;
+#else
+	unsigned long r1,r2,r3,r4;
+
+	__asm__("ldq_u %3,%1\n\t"
+		"ldq_u %2,%0\n\t"
+		"inswh %6,%7,%5\n\t"
+		"inswl %6,%7,%4\n\t"
+		"mskwh %3,%7,%3\n\t"
+		"mskwl %2,%7,%2\n\t"
+		"bis %3,%5,%3\n\t"
+		"bis %2,%4,%2\n\t"
+		"stq_u %3,%1\n\t"
+		"stq_u %2,%0"
+		:"=m" (*r11),
+		 "=m" (*(unsigned long *)(1+(char *) r11)),
+		 "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4)
+		:"r" (r5), "r" (r11));
+#endif
+}
+
+#elif defined (__ia64__)
+/*
+ * EGCS 1.1 knows about arbitrary unaligned loads.  Define some
+ * packed structures to talk about such things with.
+ */
+struct __una_u64 { unsigned long  x __attribute__((packed)); };
+struct __una_u32 { unsigned int   x __attribute__((packed)); };
+struct __una_u16 { unsigned short x __attribute__((packed)); };
+
+static __inline__ unsigned long
+__uldq (const unsigned long * r11)
+{
+	const struct __una_u64 *ptr = (const struct __una_u64 *) r11;
+	return ptr->x;
+}
+
+static __inline__ unsigned long
+uldl (const unsigned int * r11)
+{
+	const struct __una_u32 *ptr = (const struct __una_u32 *) r11;
+	return ptr->x;
+}
+
+static __inline__ unsigned long
+uldw (const unsigned short * r11)
+{
+	const struct __una_u16 *ptr = (const struct __una_u16 *) r11;
+	return ptr->x;
+}
+
+static __inline__ void
+ustq (unsigned long r5, unsigned long * r11)
+{
+	struct __una_u64 *ptr = (struct __una_u64 *) r11;
+	ptr->x = r5;
+}
+
+static __inline__ void
+ustl (unsigned long r5, unsigned int * r11)
+{
+	struct __una_u32 *ptr = (struct __una_u32 *) r11;
+	ptr->x = r5;
+}
+
+static __inline__ void
+ustw (unsigned long r5, unsigned short * r11)
+{
+	struct __una_u16 *ptr = (struct __una_u16 *) r11;
+	ptr->x = r5;
+}
+
+#endif
+
+/****************************************************************************
+PARAMETERS:
+addr	- Emulator memory address to read
+
+RETURNS:
+Byte value read from emulator memory.
+
+REMARKS:
+Reads a byte value from the emulator memory.
+****************************************************************************/
+u8 X86API rdb(
+    u32 addr)
+{
+	u8 val;
+
+	if (addr > M.mem_size - 1) {
+		DB(printk("mem_read: address %#lx out of range!\n", addr);)
+		HALT_SYS();
+		}
+	val = *(u8*)(M.mem_base + addr);
+DB(	if (DEBUG_MEM_TRACE())
+		printk("%#08x 1 -> %#x\n", addr, val);)
+	return val;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- Emulator memory address to read
+
+RETURNS:
+Word value read from emulator memory.
+
+REMARKS:
+Reads a word value from the emulator memory.
+****************************************************************************/
+u16 X86API rdw(
+	u32 addr)
+{
+	u16 val = 0;
+
+	if (addr > M.mem_size - 2) {
+		DB(printk("mem_read: address %#lx out of range!\n", addr);)
+		HALT_SYS();
+		}
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+		val = (*(u8*)(M.mem_base + addr) |
+			  (*(u8*)(M.mem_base + addr + 1) << 8));
+		}
+	else
+#endif
+#ifdef __alpha__
+		val = ldw_u((u16*)(M.mem_base + addr));
+#elif defined (__ia64__)
+	  val = uldw((u16*)(M.mem_base + addr));
+#else
+		val = *(u16*)(M.mem_base + addr);
+#endif
+		DB(	if (DEBUG_MEM_TRACE())
+		printk("%#08x 2 -> %#x\n", addr, val);)
+    return val;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- Emulator memory address to read
+
+RETURNS:
+Long value read from emulator memory.
+REMARKS:
+Reads a long value from the emulator memory.
+****************************************************************************/
+u32 X86API rdl(
+	u32 addr)
+{
+	u32 val = 0;
+
+	if (addr > M.mem_size - 4) {
+		DB(printk("mem_read: address %#lx out of range!\n", addr);)
+		HALT_SYS();
+		}
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x3) {
+		val = (*(u8*)(M.mem_base + addr + 0) |
+			  (*(u8*)(M.mem_base + addr + 1) << 8) |
+			  (*(u8*)(M.mem_base + addr + 2) << 16) |
+			  (*(u8*)(M.mem_base + addr + 3) << 24));
+		}
+	else
+#endif
+#ifdef __alpha__
+		val = ldl_u((u32*)(M.mem_base + addr));
+#elif defined (__ia64__)
+		val = uldl((u32*)(M.mem_base + addr));
+#else
+		val = *(u32*)(M.mem_base + addr);
+#endif
+DB(	if (DEBUG_MEM_TRACE())
+		printk("%#08x 4 -> %#x\n", addr, val);)
+	return val;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- Emulator memory address to read
+val		- Value to store
+
+REMARKS:
+Writes a byte value to emulator memory.
+****************************************************************************/
+void X86API wrb(
+	u32 addr,
+	u8 val)
+{
+DB(	if (DEBUG_MEM_TRACE())
+		printk("%#08x 1 <- %#x\n", addr, val);)
+    if (addr > M.mem_size - 1) {
+		DB(printk("mem_write: address %#lx out of range!\n", addr);)
+		HALT_SYS();
+		}
+	*(u8*)(M.mem_base + addr) = val;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- Emulator memory address to read
+val		- Value to store
+
+REMARKS:
+Writes a word value to emulator memory.
+****************************************************************************/
+void X86API wrw(
+	u32 addr,
+	u16 val)
+{
+DB(	if (DEBUG_MEM_TRACE())
+		printk("%#08x 2 <- %#x\n", addr, val);)
+	if (addr > M.mem_size - 2) {
+		DB(printk("mem_write: address %#lx out of range!\n", addr);)
+		HALT_SYS();
+		}
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+		*(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff;
+		*(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff;
+		}
+	else
+#endif
+#ifdef __alpha__
+	 stw_u(val,(u16*)(M.mem_base + addr));
+#elif defined (__ia64__)
+	 ustw(val,(u16*)(M.mem_base + addr));
+#else
+	 *(u16*)(M.mem_base + addr) = val;
+#endif
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- Emulator memory address to read
+val		- Value to store
+
+REMARKS:
+Writes a long value to emulator memory.
+****************************************************************************/
+void X86API wrl(
+	u32 addr,
+	u32 val)
+{
+DB(	if (DEBUG_MEM_TRACE())
+		printk("%#08x 4 <- %#x\n", addr, val);)
+	if (addr > M.mem_size - 4) {
+		DB(printk("mem_write: address %#lx out of range!\n", addr);)
+		HALT_SYS();
+		}
+#ifdef __BIG_ENDIAN__
+	if (addr & 0x1) {
+		*(u8*)(M.mem_base + addr + 0) = (val >>  0) & 0xff;
+		*(u8*)(M.mem_base + addr + 1) = (val >>  8) & 0xff;
+		*(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff;
+		*(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff;
+		}
+	else
+#endif
+#ifdef __alpha__
+	 stl_u(val,(u32*)(M.mem_base + addr));
+#elif defined (__ia64__)
+	 ustl(val,(u32*)(M.mem_base + addr));
+#else
+	 *(u32*)(M.mem_base + addr) = val;
+#endif
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- PIO address to read
+RETURN:
+0
+REMARKS:
+Default PIO byte read function. Doesn't perform real inb.
+****************************************************************************/
+static u8 X86API p_inb(
+	X86EMU_pioAddr addr)
+{
+DB(	if (DEBUG_IO_TRACE())
+		printk("inb %#04x \n", addr);)
+	return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- PIO address to read
+RETURN:
+0
+REMARKS:
+Default PIO word read function. Doesn't perform real inw.
+****************************************************************************/
+static u16 X86API p_inw(
+	X86EMU_pioAddr addr)
+{
+DB(	if (DEBUG_IO_TRACE())
+		printk("inw %#04x \n", addr);)
+	return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- PIO address to read
+RETURN:
+0
+REMARKS:
+Default PIO long read function. Doesn't perform real inl.
+****************************************************************************/
+static u32 X86API p_inl(
+	X86EMU_pioAddr addr)
+{
+DB(	if (DEBUG_IO_TRACE())
+		printk("inl %#04x \n", addr);)
+	return 0;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- PIO address to write
+val     - Value to store
+REMARKS:
+Default PIO byte write function. Doesn't perform real outb.
+****************************************************************************/
+static void X86API p_outb(
+	X86EMU_pioAddr addr,
+	u8 val)
+{
+DB(	if (DEBUG_IO_TRACE())
+		printk("outb %#02x -> %#04x \n", val, addr);)
+    return;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- PIO address to write
+val     - Value to store
+REMARKS:
+Default PIO word write function. Doesn't perform real outw.
+****************************************************************************/
+static void X86API p_outw(
+	X86EMU_pioAddr addr,
+	u16 val)
+{
+DB(	if (DEBUG_IO_TRACE())
+		printk("outw %#04x -> %#04x \n", val, addr);)
+	return;
+}
+
+/****************************************************************************
+PARAMETERS:
+addr	- PIO address to write
+val     - Value to store
+REMARKS:
+Default PIO ;ong write function. Doesn't perform real outl.
+****************************************************************************/
+static void X86API p_outl(
+	X86EMU_pioAddr addr,
+	u32 val)
+{
+DB(	if (DEBUG_IO_TRACE())
+		printk("outl %#08x -> %#04x \n", val, addr);)
+    return;
+}
+
+/*------------------------- Global Variables ------------------------------*/
+
+u8  	(X86APIP sys_rdb)(u32 addr) 			            = rdb;
+u16 	(X86APIP sys_rdw)(u32 addr) 			            = rdw;
+u32 	(X86APIP sys_rdl)(u32 addr) 			            = rdl;
+void 	(X86APIP sys_wrb)(u32 addr,u8 val) 		            = wrb;
+void 	(X86APIP sys_wrw)(u32 addr,u16 val) 	            = wrw;
+void 	(X86APIP sys_wrl)(u32 addr,u32 val) 	            = wrl;
+u8  	(X86APIP sys_inb)(X86EMU_pioAddr addr)	            = p_inb;
+u16 	(X86APIP sys_inw)(X86EMU_pioAddr addr)	            = p_inw;
+u32 	(X86APIP sys_inl)(X86EMU_pioAddr addr)              = p_inl;
+void 	(X86APIP sys_outb)(X86EMU_pioAddr addr, u8 val) 	= p_outb;
+void 	(X86APIP sys_outw)(X86EMU_pioAddr addr, u16 val)	= p_outw;
+void 	(X86APIP sys_outl)(X86EMU_pioAddr addr, u32 val)	= p_outl;
+
+/*----------------------------- Setup -------------------------------------*/
+
+/****************************************************************************
+PARAMETERS:
+funcs	- New memory function pointers to make active
+
+REMARKS:
+This function is used to set the pointers to functions which access
+memory space, allowing the user application to override these functions
+and hook them out as necessary for their application.
+****************************************************************************/
+void X86EMU_setupMemFuncs(
+	X86EMU_memFuncs *funcs)
+{
+	sys_rdb = funcs->rdb;
+    sys_rdw = funcs->rdw;
+    sys_rdl = funcs->rdl;
+    sys_wrb = funcs->wrb;
+    sys_wrw = funcs->wrw;
+    sys_wrl = funcs->wrl;
+}
+
+/****************************************************************************
+PARAMETERS:
+funcs	- New programmed I/O function pointers to make active
+
+REMARKS:
+This function is used to set the pointers to functions which access
+I/O space, allowing the user application to override these functions
+and hook them out as necessary for their application.
+****************************************************************************/
+void X86EMU_setupPioFuncs(
+	X86EMU_pioFuncs *funcs)
+{
+    sys_inb = funcs->inb;
+    sys_inw = funcs->inw;
+    sys_inl = funcs->inl;
+    sys_outb = funcs->outb;
+    sys_outw = funcs->outw;
+    sys_outl = funcs->outl;
+}
+
+/****************************************************************************
+PARAMETERS:
+funcs	- New interrupt vector table to make active
+
+REMARKS:
+This function is used to set the pointers to functions which handle
+interrupt processing in the emulator, allowing the user application to
+hook interrupts as necessary for their application. Any interrupts that
+are not hooked by the user application, and reflected and handled internally
+in the emulator via the interrupt vector table. This allows the application
+to get control when the code being emulated executes specific software
+interrupts.
+****************************************************************************/
+void X86EMU_setupIntrFuncs(
+	X86EMU_intrFuncs funcs[])
+{
+    int i;
+
+	for (i=0; i < 256; i++)
+		_X86EMU_intrTab[i] = NULL;
+	if (funcs) {
+		for (i = 0; i < 256; i++)
+			_X86EMU_intrTab[i] = funcs[i];
+		}
+}
+
+/****************************************************************************
+PARAMETERS:
+int	- New software interrupt to prepare for
+
+REMARKS:
+This function is used to set up the emulator state to exceute a software
+interrupt. This can be used by the user application code to allow an
+interrupt to be hooked, examined and then reflected back to the emulator
+so that the code in the emulator will continue processing the software
+interrupt as per normal. This essentially allows system code to actively
+hook and handle certain software interrupts as necessary.
+****************************************************************************/
+void X86EMU_prepareForInt(
+	int num)
+{
+    push_word((u16)M.x86.R_FLG);
+    CLEAR_FLAG(F_IF);
+    CLEAR_FLAG(F_TF);
+    push_word(M.x86.R_CS);
+    M.x86.R_CS = mem_access_word(num * 4 + 2);
+    push_word(M.x86.R_IP);
+    M.x86.R_IP = mem_access_word(num * 4);
+	M.x86.intr = 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/validate.c b/board/MAI/bios_emulator/scitech/src/x86emu/validate.c
new file mode 100755
index 0000000..c951301
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/validate.c
@@ -0,0 +1,765 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:     Watcom C 10.6 or later
+* Environment:  32-bit DOS
+* Developer:    Kendall Bennett
+*
+* Description:  Program to validate the x86 emulator library for
+*               correctness. We run the emulator primitive operations
+*               functions against the real x86 CPU, and compare the result
+*               and flags to ensure correctness.
+*
+*               We use inline assembler to compile and build this program.
+*
+****************************************************************************/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+#include "x86emu.h"
+#include "x86emu/prim_asm.h"
+
+/*-------------------------- Implementation -------------------------------*/
+
+#define true 1
+#define false 0
+
+#define ALL_FLAGS   (F_CF | F_PF | F_AF | F_ZF | F_SF | F_OF)
+
+#define VAL_START_BINARY(parm_type,res_type,dmax,smax,dincr,sincr)  \
+{                                                                   \
+    parm_type   d,s;                                                \
+    res_type    r,r_asm;                                            \
+	ulong     	flags,inflags;                                      \
+	int         f,failed = false;                                   \
+    char        buf1[80],buf2[80];                                  \
+    for (d = 0; d < dmax; d += dincr) {                             \
+	for (s = 0; s < smax; s += sincr) {                         \
+	    M.x86.R_EFLG = inflags = flags = def_flags;             \
+	    for (f = 0; f < 2; f++) {
+
+#define VAL_TEST_BINARY(name)                                           \
+		r_asm = name##_asm(&flags,d,s);                         \
+		r = name(d,s);                                  \
+		if (r != r_asm || M.x86.R_EFLG != flags)                \
+		    failed = true;                                      \
+		if (failed || trace) {
+
+#define VAL_TEST_BINARY_VOID(name)                                      \
+		name##_asm(&flags,d,s);                                 \
+		name(d,s);                                      \
+		r = r_asm = 0;                                          \
+		if (M.x86.R_EFLG != flags)                              \
+		    failed = true;                                      \
+		if (failed || trace) {
+
+#define VAL_FAIL_BYTE_BYTE_BINARY(name)                                                                 \
+		    if (failed)                                                                         \
+			printk("fail\n");                                                               \
+		    printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n",                         \
+			r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));     \
+		    printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n",                         \
+			r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags));
+
+#define VAL_FAIL_WORD_WORD_BINARY(name)                                                                 \
+		    if (failed)                                                                         \
+			printk("fail\n");                                                               \
+		    printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n",                         \
+			r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));   \
+		    printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n",                         \
+			r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags));
+
+#define VAL_FAIL_LONG_LONG_BINARY(name)                                                                 \
+		    if (failed)                                                                         \
+			printk("fail\n");                                                               \
+		    printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n",                         \
+			r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \
+		    printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n",                         \
+			r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags));
+
+#define VAL_END_BINARY()                                                    \
+		    }                                                       \
+		M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF);   \
+		if (failed)                                                 \
+		    break;                                                  \
+		}                                                           \
+	    if (failed)                                                     \
+		break;                                                      \
+	    }                                                               \
+	if (failed)                                                         \
+	    break;                                                          \
+	}                                                                   \
+    if (!failed)                                                            \
+	printk("passed\n");                                                 \
+}
+
+#define VAL_BYTE_BYTE_BINARY(name)          \
+    printk("Validating %s ... ", #name);    \
+    VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1)   \
+    VAL_TEST_BINARY(name)                   \
+    VAL_FAIL_BYTE_BYTE_BINARY(name)         \
+    VAL_END_BINARY()
+
+#define VAL_WORD_WORD_BINARY(name)                      \
+    printk("Validating %s ... ", #name);                \
+    VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \
+    VAL_TEST_BINARY(name)                               \
+    VAL_FAIL_WORD_WORD_BINARY(name)                     \
+    VAL_END_BINARY()
+
+#define VAL_LONG_LONG_BINARY(name)                                      \
+    printk("Validating %s ... ", #name);                                \
+    VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \
+    VAL_TEST_BINARY(name)                                               \
+    VAL_FAIL_LONG_LONG_BINARY(name)                                     \
+    VAL_END_BINARY()
+
+#define VAL_VOID_BYTE_BINARY(name)          \
+    printk("Validating %s ... ", #name);    \
+    VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1)   \
+    VAL_TEST_BINARY_VOID(name)              \
+    VAL_FAIL_BYTE_BYTE_BINARY(name)         \
+    VAL_END_BINARY()
+
+#define VAL_VOID_WORD_BINARY(name)                      \
+    printk("Validating %s ... ", #name);                \
+    VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \
+    VAL_TEST_BINARY_VOID(name)                          \
+    VAL_FAIL_WORD_WORD_BINARY(name)                     \
+    VAL_END_BINARY()
+
+#define VAL_VOID_LONG_BINARY(name)                                      \
+    printk("Validating %s ... ", #name);                                \
+    VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \
+    VAL_TEST_BINARY_VOID(name)                                          \
+    VAL_FAIL_LONG_LONG_BINARY(name)                                     \
+    VAL_END_BINARY()
+
+#define VAL_BYTE_ROTATE(name)               \
+    printk("Validating %s ... ", #name);    \
+    VAL_START_BINARY(u8,u8,0xFF,8,1,1)      \
+    VAL_TEST_BINARY(name)                   \
+    VAL_FAIL_BYTE_BYTE_BINARY(name)         \
+    VAL_END_BINARY()
+
+#define VAL_WORD_ROTATE(name)                           \
+    printk("Validating %s ... ", #name);                \
+    VAL_START_BINARY(u16,u16,0xFF00,16,0x100,1)         \
+    VAL_TEST_BINARY(name)                               \
+    VAL_FAIL_WORD_WORD_BINARY(name)                     \
+    VAL_END_BINARY()
+
+#define VAL_LONG_ROTATE(name)                                           \
+    printk("Validating %s ... ", #name);                                \
+    VAL_START_BINARY(u32,u32,0xFF000000,32,0x1000000,1)                 \
+    VAL_TEST_BINARY(name)                                               \
+    VAL_FAIL_LONG_LONG_BINARY(name)                                     \
+    VAL_END_BINARY()
+
+#define VAL_START_TERNARY(parm_type,res_type,dmax,smax,dincr,sincr,maxshift)\
+{                                                                   \
+    parm_type   d,s;                                                \
+    res_type    r,r_asm;                                            \
+    u8          shift;                                              \
+	u32         flags,inflags;                                      \
+    int         f,failed = false;                                   \
+    char        buf1[80],buf2[80];                                  \
+    for (d = 0; d < dmax; d += dincr) {                             \
+	for (s = 0; s < smax; s += sincr) {                         \
+	    for (shift = 0; shift < maxshift; shift += 1) {        \
+		M.x86.R_EFLG = inflags = flags = def_flags;         \
+		for (f = 0; f < 2; f++) {
+
+#define VAL_TEST_TERNARY(name)                                          \
+		    r_asm = name##_asm(&flags,d,s,shift);               \
+		    r = name(d,s,shift);                           \
+		    if (r != r_asm || M.x86.R_EFLG != flags)            \
+			failed = true;                                  \
+		    if (failed || trace) {
+
+#define VAL_FAIL_WORD_WORD_TERNARY(name)                                                                \
+			if (failed)                                                                         \
+			    printk("fail\n");                                                               \
+			printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n",                      \
+			    r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));   \
+			printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n",                      \
+			    r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags));
+
+#define VAL_FAIL_LONG_LONG_TERNARY(name)                                                                \
+			if (failed)                                                                         \
+			    printk("fail\n");                                                               \
+			printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n",                      \
+			    r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));  \
+			printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n",                      \
+			    r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags));
+
+#define VAL_END_TERNARY()                                                   \
+			}                                                       \
+		    M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF);   \
+		    if (failed)                                                 \
+			break;                                                  \
+		    }                                                           \
+		if (failed)                                                     \
+		    break;                                                      \
+		}                                                               \
+	    if (failed)                                                     \
+		break;                                                      \
+	    }                                                               \
+	if (failed)                                                         \
+	    break;                                                          \
+	}                                                                   \
+    if (!failed)                                                            \
+	printk("passed\n");                                                 \
+}
+
+#define VAL_WORD_ROTATE_DBL(name)                           \
+    printk("Validating %s ... ", #name);                    \
+    VAL_START_TERNARY(u16,u16,0xFF00,0xFF00,0x100,0x100,16) \
+    VAL_TEST_TERNARY(name)                                  \
+    VAL_FAIL_WORD_WORD_TERNARY(name)                        \
+    VAL_END_TERNARY()
+
+#define VAL_LONG_ROTATE_DBL(name)                                           \
+    printk("Validating %s ... ", #name);                                    \
+    VAL_START_TERNARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000,32) \
+    VAL_TEST_TERNARY(name)                                                  \
+    VAL_FAIL_LONG_LONG_TERNARY(name)                                        \
+    VAL_END_TERNARY()
+
+#define VAL_START_UNARY(parm_type,max,incr)                 \
+{                                                           \
+    parm_type   d,r,r_asm;                                  \
+	u32         flags,inflags;                              \
+    int         f,failed = false;                           \
+    char        buf1[80],buf2[80];                          \
+    for (d = 0; d < max; d += incr) {                       \
+	M.x86.R_EFLG = inflags = flags = def_flags;         \
+	for (f = 0; f < 2; f++) {
+
+#define VAL_TEST_UNARY(name)                                \
+	    r_asm = name##_asm(&flags,d);                   \
+	    r = name(d);                                \
+	    if (r != r_asm || M.x86.R_EFLG != flags) {      \
+		failed = true;
+
+#define VAL_FAIL_BYTE_UNARY(name)                                                               \
+		printk("fail\n");                                                               \
+		printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n",                            \
+		    r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));    \
+		printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n",                            \
+		    r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags));
+
+#define VAL_FAIL_WORD_UNARY(name)                                                               \
+		printk("fail\n");                                                               \
+		printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n",                            \
+		    r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));  \
+		printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n",                            \
+		    r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags));
+
+#define VAL_FAIL_LONG_UNARY(name)                                                               \
+		printk("fail\n");                                                               \
+		printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n",                            \
+		    r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));    \
+		printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n",                            \
+		    r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags));
+
+#define VAL_END_UNARY()                                                 \
+		}                                                       \
+	    M.x86.R_EFLG = inflags = flags = def_flags | ALL_FLAGS;     \
+	    if (failed)                                                 \
+		break;                                                  \
+	    }                                                           \
+	if (failed)                                                     \
+	    break;                                                      \
+	}                                                               \
+    if (!failed)                                                        \
+	printk("passed\n");                                             \
+}
+
+#define VAL_BYTE_UNARY(name)                \
+    printk("Validating %s ... ", #name);    \
+    VAL_START_UNARY(u8,0xFF,0x1)            \
+    VAL_TEST_UNARY(name)                    \
+    VAL_FAIL_BYTE_UNARY(name)               \
+    VAL_END_UNARY()
+
+#define VAL_WORD_UNARY(name)                \
+    printk("Validating %s ... ", #name);    \
+    VAL_START_UNARY(u16,0xFF00,0x100)       \
+    VAL_TEST_UNARY(name)                    \
+    VAL_FAIL_WORD_UNARY(name)               \
+    VAL_END_UNARY()
+
+#define VAL_WORD_BYTE_UNARY(name)           \
+    printk("Validating %s ... ", #name);    \
+    VAL_START_UNARY(u16,0xFF,0x1)           \
+    VAL_TEST_UNARY(name)                    \
+    VAL_FAIL_WORD_UNARY(name)               \
+    VAL_END_UNARY()
+
+#define VAL_LONG_UNARY(name)                \
+    printk("Validating %s ... ", #name);    \
+    VAL_START_UNARY(u32,0xFF000000,0x1000000) \
+    VAL_TEST_UNARY(name)                    \
+    VAL_FAIL_LONG_UNARY(name)               \
+    VAL_END_UNARY()
+
+#define VAL_BYTE_MUL(name)                                              \
+    printk("Validating %s ... ", #name);                                \
+{                                                                       \
+    u8          d,s;                                                    \
+    u16         r,r_asm;                                                \
+	u32         flags,inflags;                                          \
+    int         f,failed = false;                                       \
+    char        buf1[80],buf2[80];                                      \
+    for (d = 0; d < 0xFF; d += 1) {                                     \
+	for (s = 0; s < 0xFF; s += 1) {                                 \
+	    M.x86.R_EFLG = inflags = flags = def_flags;                 \
+	    for (f = 0; f < 2; f++) {                                   \
+		name##_asm(&flags,&r_asm,d,s);                          \
+		M.x86.R_AL = d;                                         \
+		name(s);                                            \
+		r = M.x86.R_AX;                                         \
+		if (r != r_asm || M.x86.R_EFLG != flags)                \
+		    failed = true;                                      \
+		if (failed || trace) {                                  \
+		    if (failed)                                         \
+			printk("fail\n");                               \
+		    printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n",                         \
+			r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));     \
+		    printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n",                         \
+			r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags));  \
+		    }                                                       \
+		M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF);   \
+		if (failed)                                                 \
+		    break;                                                  \
+		}                                                           \
+	    if (failed)                                                     \
+		break;                                                      \
+	    }                                                               \
+	if (failed)                                                         \
+	    break;                                                          \
+	}                                                                   \
+    if (!failed)                                                            \
+	printk("passed\n");                                                 \
+}
+
+#define VAL_WORD_MUL(name)                                              \
+    printk("Validating %s ... ", #name);                                \
+{                                                                       \
+    u16         d,s;                                                    \
+    u16         r_lo,r_asm_lo;                                          \
+    u16         r_hi,r_asm_hi;                                          \
+	u32         flags,inflags;                                          \
+    int         f,failed = false;                                       \
+    char        buf1[80],buf2[80];                                      \
+    for (d = 0; d < 0xFF00; d += 0x100) {                               \
+	for (s = 0; s < 0xFF00; s += 0x100) {                           \
+	    M.x86.R_EFLG = inflags = flags = def_flags;                 \
+	    for (f = 0; f < 2; f++) {                                   \
+		name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s);             \
+		M.x86.R_AX = d;                                         \
+		name(s);                                            \
+		r_lo = M.x86.R_AX;                                      \
+		r_hi = M.x86.R_DX;                                      \
+		if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\
+		    failed = true;                                      \
+		if (failed || trace) {                                  \
+		    if (failed)                                         \
+			printk("fail\n");                               \
+		    printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n",                              \
+			r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));       \
+		    printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n",                              \
+			r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags));  \
+		    }                                                                                               \
+		M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF);   \
+		if (failed)                                                 \
+		    break;                                                  \
+		}                                                           \
+	    if (failed)                                                     \
+		break;                                                      \
+	    }                                                               \
+	if (failed)                                                         \
+	    break;                                                          \
+	}                                                                   \
+    if (!failed)                                                            \
+	printk("passed\n");                                                 \
+}
+
+#define VAL_LONG_MUL(name)                                              \
+    printk("Validating %s ... ", #name);                                \
+{                                                                       \
+    u32         d,s;                                                    \
+    u32         r_lo,r_asm_lo;                                          \
+    u32         r_hi,r_asm_hi;                                          \
+	u32         flags,inflags;                                          \
+    int         f,failed = false;                                       \
+    char        buf1[80],buf2[80];                                      \
+    for (d = 0; d < 0xFF000000; d += 0x1000000) {                       \
+	for (s = 0; s < 0xFF000000; s += 0x1000000) {                   \
+	    M.x86.R_EFLG = inflags = flags = def_flags;                 \
+	    for (f = 0; f < 2; f++) {                                   \
+		name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s);             \
+		M.x86.R_EAX = d;                                        \
+		name(s);                                            \
+		r_lo = M.x86.R_EAX;                                     \
+		r_hi = M.x86.R_EDX;                                     \
+		if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\
+		    failed = true;                                      \
+		if (failed || trace) {                                  \
+		    if (failed)                                         \
+			printk("fail\n");                               \
+		    printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n",                              \
+			r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));       \
+		    printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n",                              \
+			r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags));  \
+		    }                                                                                               \
+		M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF);   \
+		if (failed)                                                 \
+		    break;                                                  \
+		}                                                           \
+	    if (failed)                                                     \
+		break;                                                      \
+	    }                                                               \
+	if (failed)                                                         \
+	    break;                                                          \
+	}                                                                   \
+    if (!failed)                                                            \
+	printk("passed\n");                                                 \
+}
+
+#define VAL_BYTE_DIV(name)                                              \
+    printk("Validating %s ... ", #name);                                \
+{                                                                       \
+    u16         d,s;                                                    \
+    u8          r_quot,r_rem,r_asm_quot,r_asm_rem;                      \
+	u32         flags,inflags;                                          \
+    int         f,failed = false;                                       \
+    char        buf1[80],buf2[80];                                      \
+    for (d = 0; d < 0xFF00; d += 0x100) {                               \
+	for (s = 1; s < 0xFF; s += 1) {                                 \
+	    M.x86.R_EFLG = inflags = flags = def_flags;                 \
+	    for (f = 0; f < 2; f++) {                                   \
+		M.x86.intr = 0;                                         \
+		M.x86.R_AX = d;                                         \
+		name(s);                                            \
+		r_quot = M.x86.R_AL;                                    \
+		r_rem = M.x86.R_AH;                                     \
+		if (M.x86.intr & INTR_SYNCH)                            \
+		    continue;                                           \
+		name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,s);          \
+		if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \
+		    failed = true;                                      \
+		if (failed || trace) {                                  \
+		    if (failed)                                         \
+			printk("fail\n");                               \
+		    printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n",                      \
+			r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));     \
+		    printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n",                      \
+			r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags));  \
+		    }                                                       \
+		M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF);   \
+		if (failed)                                                 \
+		    break;                                                  \
+		}                                                           \
+	    if (failed)                                                     \
+		break;                                                      \
+	    }                                                               \
+	if (failed)                                                         \
+	    break;                                                          \
+	}                                                                   \
+    if (!failed)                                                            \
+	printk("passed\n");                                                 \
+}
+
+#define VAL_WORD_DIV(name)                                              \
+    printk("Validating %s ... ", #name);                                \
+{                                                                       \
+    u32         d,s;                                                    \
+    u16         r_quot,r_rem,r_asm_quot,r_asm_rem;                      \
+	u32         flags,inflags;                                          \
+    int         f,failed = false;                                       \
+    char        buf1[80],buf2[80];                                      \
+    for (d = 0; d < 0xFF000000; d += 0x1000000) {                       \
+	for (s = 0x100; s < 0xFF00; s += 0x100) {                       \
+	    M.x86.R_EFLG = inflags = flags = def_flags;                 \
+	    for (f = 0; f < 2; f++) {                                   \
+		M.x86.intr = 0;                                         \
+		M.x86.R_AX = d & 0xFFFF;                                \
+		M.x86.R_DX = d >> 16;                                   \
+		name(s);                                            \
+		r_quot = M.x86.R_AX;                                    \
+		r_rem = M.x86.R_DX;                                     \
+		if (M.x86.intr & INTR_SYNCH)                            \
+		    continue;                                           \
+		name##_asm(&flags,&r_asm_quot,&r_asm_rem,d & 0xFFFF,d >> 16,s);\
+		if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \
+		    failed = true;                                      \
+		if (failed || trace) {                                  \
+		    if (failed)                                         \
+			printk("fail\n");                               \
+		    printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n",                      \
+			r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));     \
+		    printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n",                      \
+			r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags));  \
+		    }                                                       \
+		M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF);   \
+		if (failed)                                                 \
+		    break;                                                  \
+		}                                                           \
+	    if (failed)                                                     \
+		break;                                                      \
+	    }                                                               \
+	if (failed)                                                         \
+	    break;                                                          \
+	}                                                                   \
+    if (!failed)                                                            \
+	printk("passed\n");                                                 \
+}
+
+#define VAL_LONG_DIV(name)                                              \
+    printk("Validating %s ... ", #name);                                \
+{                                                                       \
+    u32         d,s;                                                    \
+    u32         r_quot,r_rem,r_asm_quot,r_asm_rem;                      \
+	u32         flags,inflags;                                          \
+    int         f,failed = false;                                       \
+    char        buf1[80],buf2[80];                                      \
+    for (d = 0; d < 0xFF000000; d += 0x1000000) {                       \
+	for (s = 0x100; s < 0xFF00; s += 0x100) {                       \
+	    M.x86.R_EFLG = inflags = flags = def_flags;                 \
+	    for (f = 0; f < 2; f++) {                                   \
+		M.x86.intr = 0;                                         \
+		M.x86.R_EAX = d;                                        \
+		M.x86.R_EDX = 0;                                        \
+		name(s);                                            \
+		r_quot = M.x86.R_EAX;                                   \
+		r_rem = M.x86.R_EDX;                                    \
+		if (M.x86.intr & INTR_SYNCH)                            \
+		    continue;                                           \
+		name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,0,s);        \
+		if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \
+		    failed = true;                                      \
+		if (failed || trace) {                                  \
+		    if (failed)                                         \
+			printk("fail\n");                               \
+		    printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n",                       \
+			r_quot, r_rem, #name, 0, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG));  \
+		    printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n",                       \
+			r_asm_quot, r_asm_rem, #name"_asm", 0, d, s, print_flags(buf1,inflags), print_flags(buf2,flags));   \
+		    }                                                       \
+		M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF);   \
+		if (failed)                                                 \
+		    break;                                                  \
+		}                                                           \
+	    if (failed)                                                     \
+		break;                                                      \
+	    }                                                               \
+	if (failed)                                                         \
+	    break;                                                          \
+	}                                                                   \
+    if (!failed)                                                            \
+	printk("passed\n");                                                 \
+}
+
+void printk(const char *fmt, ...)
+{
+    va_list argptr;
+    va_start(argptr, fmt);
+    vfprintf(stdout, fmt, argptr);
+    fflush(stdout);
+    va_end(argptr);
+}
+
+char * print_flags(char *buf,ulong flags)
+{
+    char *separator = "";
+
+    buf[0] = 0;
+    if (flags & F_CF) {
+	strcat(buf,separator);
+	strcat(buf,"CF");
+	separator = ",";
+	}
+    if (flags & F_PF) {
+	strcat(buf,separator);
+	strcat(buf,"PF");
+	separator = ",";
+	}
+    if (flags & F_AF) {
+	strcat(buf,separator);
+	strcat(buf,"AF");
+	separator = ",";
+	}
+    if (flags & F_ZF) {
+	strcat(buf,separator);
+	strcat(buf,"ZF");
+	separator = ",";
+	}
+    if (flags & F_SF) {
+	strcat(buf,separator);
+	strcat(buf,"SF");
+	separator = ",";
+	}
+    if (flags & F_OF) {
+	strcat(buf,separator);
+	strcat(buf,"OF");
+	separator = ",";
+	}
+    if (separator[0] == 0)
+	strcpy(buf,"None");
+    return buf;
+}
+
+int main(int argc)
+{
+    ulong   def_flags;
+    int trace = false;
+
+    if (argc > 1)
+	trace = true;
+    memset(&M, 0, sizeof(M));
+    def_flags = get_flags_asm() & ~ALL_FLAGS;
+
+    VAL_WORD_UNARY(aaa_word);
+    VAL_WORD_UNARY(aas_word);
+
+    VAL_WORD_UNARY(aad_word);
+    VAL_WORD_UNARY(aam_word);
+
+    VAL_BYTE_BYTE_BINARY(adc_byte);
+    VAL_WORD_WORD_BINARY(adc_word);
+    VAL_LONG_LONG_BINARY(adc_long);
+
+    VAL_BYTE_BYTE_BINARY(add_byte);
+    VAL_WORD_WORD_BINARY(add_word);
+    VAL_LONG_LONG_BINARY(add_long);
+
+    VAL_BYTE_BYTE_BINARY(and_byte);
+    VAL_WORD_WORD_BINARY(and_word);
+    VAL_LONG_LONG_BINARY(and_long);
+
+    VAL_BYTE_BYTE_BINARY(cmp_byte);
+    VAL_WORD_WORD_BINARY(cmp_word);
+    VAL_LONG_LONG_BINARY(cmp_long);
+
+    VAL_BYTE_UNARY(daa_byte);
+    VAL_BYTE_UNARY(das_byte);   /* Fails for 0x9A (out of range anyway) */
+
+    VAL_BYTE_UNARY(dec_byte);
+    VAL_WORD_UNARY(dec_word);
+    VAL_LONG_UNARY(dec_long);
+
+    VAL_BYTE_UNARY(inc_byte);
+    VAL_WORD_UNARY(inc_word);
+    VAL_LONG_UNARY(inc_long);
+
+    VAL_BYTE_BYTE_BINARY(or_byte);
+    VAL_WORD_WORD_BINARY(or_word);
+    VAL_LONG_LONG_BINARY(or_long);
+
+    VAL_BYTE_UNARY(neg_byte);
+    VAL_WORD_UNARY(neg_word);
+    VAL_LONG_UNARY(neg_long);
+
+    VAL_BYTE_UNARY(not_byte);
+    VAL_WORD_UNARY(not_word);
+    VAL_LONG_UNARY(not_long);
+
+    VAL_BYTE_ROTATE(rcl_byte);
+    VAL_WORD_ROTATE(rcl_word);
+    VAL_LONG_ROTATE(rcl_long);
+
+    VAL_BYTE_ROTATE(rcr_byte);
+    VAL_WORD_ROTATE(rcr_word);
+    VAL_LONG_ROTATE(rcr_long);
+
+    VAL_BYTE_ROTATE(rol_byte);
+    VAL_WORD_ROTATE(rol_word);
+    VAL_LONG_ROTATE(rol_long);
+
+    VAL_BYTE_ROTATE(ror_byte);
+    VAL_WORD_ROTATE(ror_word);
+    VAL_LONG_ROTATE(ror_long);
+
+    VAL_BYTE_ROTATE(shl_byte);
+    VAL_WORD_ROTATE(shl_word);
+    VAL_LONG_ROTATE(shl_long);
+
+    VAL_BYTE_ROTATE(shr_byte);
+    VAL_WORD_ROTATE(shr_word);
+    VAL_LONG_ROTATE(shr_long);
+
+    VAL_BYTE_ROTATE(sar_byte);
+    VAL_WORD_ROTATE(sar_word);
+    VAL_LONG_ROTATE(sar_long);
+
+    VAL_WORD_ROTATE_DBL(shld_word);
+    VAL_LONG_ROTATE_DBL(shld_long);
+
+    VAL_WORD_ROTATE_DBL(shrd_word);
+    VAL_LONG_ROTATE_DBL(shrd_long);
+
+    VAL_BYTE_BYTE_BINARY(sbb_byte);
+    VAL_WORD_WORD_BINARY(sbb_word);
+    VAL_LONG_LONG_BINARY(sbb_long);
+
+    VAL_BYTE_BYTE_BINARY(sub_byte);
+    VAL_WORD_WORD_BINARY(sub_word);
+    VAL_LONG_LONG_BINARY(sub_long);
+
+    VAL_BYTE_BYTE_BINARY(xor_byte);
+    VAL_WORD_WORD_BINARY(xor_word);
+    VAL_LONG_LONG_BINARY(xor_long);
+
+    VAL_VOID_BYTE_BINARY(test_byte);
+    VAL_VOID_WORD_BINARY(test_word);
+    VAL_VOID_LONG_BINARY(test_long);
+
+    VAL_BYTE_MUL(imul_byte);
+    VAL_WORD_MUL(imul_word);
+    VAL_LONG_MUL(imul_long);
+
+    VAL_BYTE_MUL(mul_byte);
+    VAL_WORD_MUL(mul_word);
+    VAL_LONG_MUL(mul_long);
+
+    VAL_BYTE_DIV(idiv_byte);
+    VAL_WORD_DIV(idiv_word);
+    VAL_LONG_DIV(idiv_long);
+
+    VAL_BYTE_DIV(div_byte);
+    VAL_WORD_DIV(div_word);
+    VAL_LONG_DIV(div_long);
+
+    return 0;
+}
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h
new file mode 100755
index 0000000..9a4a096
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h
@@ -0,0 +1,210 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for debug definitions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_DEBUG_H
+#define __X86EMU_DEBUG_H
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+/* checks to be enabled for "runtime" */
+
+#define CHECK_IP_FETCH_F                0x1
+#define CHECK_SP_ACCESS_F               0x2
+#define CHECK_MEM_ACCESS_F              0x4 /*using regular linear pointer */
+#define CHECK_DATA_ACCESS_F             0x8 /*using segment:offset*/
+
+#ifdef DEBUG
+# define CHECK_IP_FETCH()              	(M.x86.check & CHECK_IP_FETCH_F)
+# define CHECK_SP_ACCESS()             	(M.x86.check & CHECK_SP_ACCESS_F)
+# define CHECK_MEM_ACCESS()            	(M.x86.check & CHECK_MEM_ACCESS_F)
+# define CHECK_DATA_ACCESS()           	(M.x86.check & CHECK_DATA_ACCESS_F)
+#else
+# define CHECK_IP_FETCH()
+# define CHECK_SP_ACCESS()
+# define CHECK_MEM_ACCESS()
+# define CHECK_DATA_ACCESS()
+#endif
+
+#ifdef DEBUG
+# define DEBUG_INSTRUMENT()    	(M.x86.debug & DEBUG_INSTRUMENT_F)
+# define DEBUG_DECODE()        	(M.x86.debug & DEBUG_DECODE_F)
+# define DEBUG_TRACE()         	(M.x86.debug & DEBUG_TRACE_F)
+# define DEBUG_STEP()          	(M.x86.debug & DEBUG_STEP_F)
+# define DEBUG_DISASSEMBLE()   	(M.x86.debug & DEBUG_DISASSEMBLE_F)
+# define DEBUG_BREAK()         	(M.x86.debug & DEBUG_BREAK_F)
+# define DEBUG_SVC()           	(M.x86.debug & DEBUG_SVC_F)
+# define DEBUG_SAVE_IP_CS()     (M.x86.debug & DEBUG_SAVE_CS_IP)
+
+# define DEBUG_FS()            	(M.x86.debug & DEBUG_FS_F)
+# define DEBUG_PROC()          	(M.x86.debug & DEBUG_PROC_F)
+# define DEBUG_SYSINT()        	(M.x86.debug & DEBUG_SYSINT_F)
+# define DEBUG_TRACECALL()     	(M.x86.debug & DEBUG_TRACECALL_F)
+# define DEBUG_TRACECALLREGS() 	(M.x86.debug & DEBUG_TRACECALL_REGS_F)
+# define DEBUG_SYS()           	(M.x86.debug & DEBUG_SYS_F)
+# define DEBUG_MEM_TRACE()     	(M.x86.debug & DEBUG_MEM_TRACE_F)
+# define DEBUG_IO_TRACE()      	(M.x86.debug & DEBUG_IO_TRACE_F)
+# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F)
+#else
+# define DEBUG_INSTRUMENT()    	0
+# define DEBUG_DECODE()        	0
+# define DEBUG_TRACE()         	0
+# define DEBUG_STEP()          	0
+# define DEBUG_DISASSEMBLE()   	0
+# define DEBUG_BREAK()         	0
+# define DEBUG_SVC()           	0
+# define DEBUG_SAVE_IP_CS()     0
+# define DEBUG_FS()            	0
+# define DEBUG_PROC()          	0
+# define DEBUG_SYSINT()        	0
+# define DEBUG_TRACECALL()     	0
+# define DEBUG_TRACECALLREGS() 	0
+# define DEBUG_SYS()           	0
+# define DEBUG_MEM_TRACE()     	0
+# define DEBUG_IO_TRACE()      	0
+# define DEBUG_DECODE_NOPRINT() 0
+#endif
+
+#ifdef DEBUG
+
+# define DECODE_PRINTF(x)     	if (DEBUG_DECODE()) \
+									x86emu_decode_printf(x)
+# define DECODE_PRINTF2(x,y)  	if (DEBUG_DECODE()) \
+									x86emu_decode_printf2(x,y)
+
+/*
+ * The following allow us to look at the bytes of an instruction.  The
+ * first INCR_INSTRN_LEN, is called everytime bytes are consumed in
+ * the decoding process.  The SAVE_IP_CS is called initially when the
+ * major opcode of the instruction is accessed.
+ */
+#define INC_DECODED_INST_LEN(x)                    	\
+	if (DEBUG_DECODE())  	                       	\
+		x86emu_inc_decoded_inst_len(x)
+
+#define SAVE_IP_CS(x,y)                               			\
+	if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \
+	      | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
+		M.x86.saved_cs = x;                          			\
+		M.x86.saved_ip = y;                          			\
+	}
+#else
+# define INC_DECODED_INST_LEN(x)
+# define DECODE_PRINTF(x)
+# define DECODE_PRINTF2(x,y)
+# define SAVE_IP_CS(x,y)
+#endif
+
+#ifdef DEBUG
+#define TRACE_REGS()                                   		\
+	if (DEBUG_DISASSEMBLE()) {                         		\
+		x86emu_just_disassemble();                        	\
+		goto EndOfTheInstructionProcedure;             		\
+	}                                                   	\
+	if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs()
+#else
+# define TRACE_REGS()
+#endif
+
+#ifdef DEBUG
+# define SINGLE_STEP()		if (DEBUG_STEP()) x86emu_single_step()
+#else
+# define SINGLE_STEP()
+#endif
+
+#define TRACE_AND_STEP()	\
+	TRACE_REGS();			\
+	SINGLE_STEP()
+
+#ifdef DEBUG
+# define START_OF_INSTR()
+# define END_OF_INSTR()		EndOfTheInstructionProcedure: x86emu_end_instr();
+# define END_OF_INSTR_NO_TRACE()	x86emu_end_instr();
+#else
+# define START_OF_INSTR()
+# define END_OF_INSTR()
+# define END_OF_INSTR_NO_TRACE()
+#endif
+
+#ifdef DEBUG
+# define  CALL_TRACE(u,v,w,x,s)                                 \
+	if (DEBUG_TRACECALLREGS())									\
+		x86emu_dump_regs();                                     \
+	if (DEBUG_TRACECALL())                                     	\
+		printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x);
+# define RETURN_TRACE(n,u,v)                                    \
+	if (DEBUG_TRACECALLREGS())									\
+		x86emu_dump_regs();                                     \
+	if (DEBUG_TRACECALL())                                     	\
+		printk("%04x:%04x: %s\n",u,v,n);
+#else
+# define CALL_TRACE(u,v,w,x,s)
+# define RETURN_TRACE(n,u,v)
+#endif
+
+#ifdef DEBUG
+#define	DB(x)	x
+#else
+#define	DB(x)
+#endif
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {            			/* Use "C" linkage when in C++ mode */
+#endif
+
+extern void x86emu_inc_decoded_inst_len (int x);
+extern void x86emu_decode_printf (char *x);
+extern void x86emu_decode_printf2 (char *x, int y);
+extern void x86emu_just_disassemble (void);
+extern void x86emu_single_step (void);
+extern void x86emu_end_instr (void);
+extern void x86emu_dump_regs (void);
+extern void x86emu_dump_xregs (void);
+extern void x86emu_print_int_vect (u16 iv);
+extern void x86emu_instrument_instruction (void);
+extern void x86emu_check_ip_access (void);
+extern void x86emu_check_sp_access (void);
+extern void x86emu_check_mem_access (u32 p);
+extern void x86emu_check_data_access (uint s, uint o);
+
+#ifdef  __cplusplus
+}                       			/* End of "C" linkage for C++   	*/
+#endif
+
+#endif /* __X86EMU_DEBUG_H */
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h
new file mode 100755
index 0000000..321a345
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h
@@ -0,0 +1,87 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for instruction decoding logic.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_DECODE_H
+#define __X86EMU_DECODE_H
+
+/*---------------------- Macros and type definitions ----------------------*/
+
+/* Instruction Decoding Stuff */
+
+#define FETCH_DECODE_MODRM(mod,rh,rl) 	fetch_decode_modrm(&mod,&rh,&rl)
+#define DECODE_RM_BYTE_REGISTER(r)    	decode_rm_byte_register(r)
+#define DECODE_RM_WORD_REGISTER(r)    	decode_rm_word_register(r)
+#define DECODE_RM_LONG_REGISTER(r)    	decode_rm_long_register(r)
+#define DECODE_CLEAR_SEGOVR()         	M.x86.mode &= ~SYSMODE_CLRMASK
+
+/*-------------------------- Function Prototypes --------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {            			/* Use "C" linkage when in C++ mode */
+#endif
+
+void 	x86emu_intr_raise (u8 type);
+void    fetch_decode_modrm (int *mod,int *regh,int *regl);
+u8      fetch_byte_imm (void);
+u16     fetch_word_imm (void);
+u32     fetch_long_imm (void);
+u8      fetch_data_byte (uint offset);
+u8      fetch_data_byte_abs (uint segment, uint offset);
+u16     fetch_data_word (uint offset);
+u16     fetch_data_word_abs (uint segment, uint offset);
+u32     fetch_data_long (uint offset);
+u32     fetch_data_long_abs (uint segment, uint offset);
+void    store_data_byte (uint offset, u8 val);
+void    store_data_byte_abs (uint segment, uint offset, u8 val);
+void    store_data_word (uint offset, u16 val);
+void    store_data_word_abs (uint segment, uint offset, u16 val);
+void    store_data_long (uint offset, u32 val);
+void    store_data_long_abs (uint segment, uint offset, u32 val);
+u8* 	decode_rm_byte_register(int reg);
+u16* 	decode_rm_word_register(int reg);
+u32* 	decode_rm_long_register(int reg);
+u16* 	decode_rm_seg_register(int reg);
+unsigned decode_rm00_address(int rm);
+unsigned decode_rm01_address(int rm);
+unsigned decode_rm10_address(int rm);
+
+#ifdef  __cplusplus
+}                       			/* End of "C" linkage for C++   	*/
+#endif
+
+#endif /* __X86EMU_DECODE_H */
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h
new file mode 100755
index 0000000..5fb2714
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h
@@ -0,0 +1,61 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for FPU instruction decoding.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_FPU_H
+#define __X86EMU_FPU_H
+
+#ifdef  __cplusplus
+extern "C" {            			/* Use "C" linkage when in C++ mode */
+#endif
+
+/* these have to be defined, whether 8087 support compiled in or not. */
+
+extern void x86emuOp_esc_coprocess_d8 (u8 op1);
+extern void x86emuOp_esc_coprocess_d9 (u8 op1);
+extern void x86emuOp_esc_coprocess_da (u8 op1);
+extern void x86emuOp_esc_coprocess_db (u8 op1);
+extern void x86emuOp_esc_coprocess_dc (u8 op1);
+extern void x86emuOp_esc_coprocess_dd (u8 op1);
+extern void x86emuOp_esc_coprocess_de (u8 op1);
+extern void x86emuOp_esc_coprocess_df (u8 op1);
+
+#ifdef  __cplusplus
+}                       			/* End of "C" linkage for C++   	*/
+#endif
+
+#endif /* __X86EMU_FPU_H */
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h
new file mode 100755
index 0000000..65ea676
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h
@@ -0,0 +1,45 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for operand decoding functions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_OPS_H
+#define __X86EMU_OPS_H
+
+extern void (*x86emu_optab[0x100])(u8 op1);
+extern void (*x86emu_optab2[0x100])(u8 op2);
+
+#endif /* __X86EMU_OPS_H */
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h
new file mode 100755
index 0000000..e023cf8
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h
@@ -0,0 +1,970 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		Watcom C++ 10.6 or later
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  Inline assembler versions of the primitive operand
+*				functions for faster performance. At the moment this is
+*				x86 inline assembler, but these functions could be replaced
+*				with native inline assembler for each supported processor
+*				platform.
+*
+****************************************************************************/
+
+#ifndef	__X86EMU_PRIM_ASM_H
+#define	__X86EMU_PRIM_ASM_H
+
+#ifdef	__WATCOMC__
+
+#ifndef	VALIDATE
+#define	__HAVE_INLINE_ASSEMBLER__
+#endif
+
+u32		get_flags_asm(void);
+#pragma aux get_flags_asm =			\
+	"pushf"                         \
+	"pop	eax"                  	\
+	value [eax]                     \
+	modify exact [eax];
+
+u16     aaa_word_asm(u32 *flags,u16 d);
+#pragma aux aaa_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"aaa"                  			\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] 				\
+	value [ax]                      \
+	modify exact [ax];
+
+u16     aas_word_asm(u32 *flags,u16 d);
+#pragma aux aas_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"aas"                  			\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] 				\
+	value [ax]                      \
+	modify exact [ax];
+
+u16     aad_word_asm(u32 *flags,u16 d);
+#pragma aux aad_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"aad"                  			\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] 				\
+	value [ax]                      \
+	modify exact [ax];
+
+u16     aam_word_asm(u32 *flags,u8 d);
+#pragma aux aam_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"aam"                  			\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] 				\
+	value [ax]                      \
+	modify exact [ax];
+
+u8      adc_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux adc_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"adc	al,bl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [bl]            \
+	value [al]                      \
+	modify exact [al bl];
+
+u16     adc_word_asm(u32 *flags,u16 d, u16 s);
+#pragma aux adc_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"adc	ax,bx"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [bx]            \
+	value [ax]                      \
+	modify exact [ax bx];
+
+u32     adc_long_asm(u32 *flags,u32 d, u32 s);
+#pragma aux adc_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"adc	eax,ebx"                \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [ebx]          \
+	value [eax]                     \
+	modify exact [eax ebx];
+
+u8      add_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux add_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"add	al,bl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [bl]            \
+	value [al]                      \
+	modify exact [al bl];
+
+u16     add_word_asm(u32 *flags,u16 d, u16 s);
+#pragma aux add_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"add	ax,bx"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [bx]            \
+	value [ax]                      \
+	modify exact [ax bx];
+
+u32     add_long_asm(u32 *flags,u32 d, u32 s);
+#pragma aux add_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"add	eax,ebx"                \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [ebx]          \
+	value [eax]                     \
+	modify exact [eax ebx];
+
+u8      and_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux and_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"and	al,bl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [bl]            \
+	value [al]                      \
+	modify exact [al bl];
+
+u16     and_word_asm(u32 *flags,u16 d, u16 s);
+#pragma aux and_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"and	ax,bx"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [bx]            \
+	value [ax]                      \
+	modify exact [ax bx];
+
+u32     and_long_asm(u32 *flags,u32 d, u32 s);
+#pragma aux and_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"and	eax,ebx"                \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [ebx]          \
+	value [eax]                     \
+	modify exact [eax ebx];
+
+u8      cmp_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux cmp_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"cmp	al,bl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [bl]            \
+	value [al]                      \
+	modify exact [al bl];
+
+u16     cmp_word_asm(u32 *flags,u16 d, u16 s);
+#pragma aux cmp_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"cmp	ax,bx"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [bx]            \
+	value [ax]                      \
+	modify exact [ax bx];
+
+u32     cmp_long_asm(u32 *flags,u32 d, u32 s);
+#pragma aux cmp_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"cmp	eax,ebx"                \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [ebx]          \
+	value [eax]                     \
+	modify exact [eax ebx];
+
+u8      daa_byte_asm(u32 *flags,u8 d);
+#pragma aux daa_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"daa"                  			\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al]            		\
+	value [al]                      \
+	modify exact [al];
+
+u8      das_byte_asm(u32 *flags,u8 d);
+#pragma aux das_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"das"                  			\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al]            		\
+	value [al]                      \
+	modify exact [al];
+
+u8      dec_byte_asm(u32 *flags,u8 d);
+#pragma aux dec_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"dec	al"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al]            		\
+	value [al]                      \
+	modify exact [al];
+
+u16     dec_word_asm(u32 *flags,u16 d);
+#pragma aux dec_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"dec	ax"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax]            		\
+	value [ax]                      \
+	modify exact [ax];
+
+u32     dec_long_asm(u32 *flags,u32 d);
+#pragma aux dec_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"dec	eax"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax]          		\
+	value [eax]                     \
+	modify exact [eax];
+
+u8      inc_byte_asm(u32 *flags,u8 d);
+#pragma aux inc_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"inc	al"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al]            		\
+	value [al]                      \
+	modify exact [al];
+
+u16     inc_word_asm(u32 *flags,u16 d);
+#pragma aux inc_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"inc	ax"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax]            		\
+	value [ax]                      \
+	modify exact [ax];
+
+u32     inc_long_asm(u32 *flags,u32 d);
+#pragma aux inc_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"inc	eax"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax]          		\
+	value [eax]                     \
+	modify exact [eax];
+
+u8      or_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux or_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"or	al,bl"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [bl]            \
+	value [al]                      \
+	modify exact [al bl];
+
+u16     or_word_asm(u32 *flags,u16 d, u16 s);
+#pragma aux or_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"or	ax,bx"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [bx]            \
+	value [ax]                      \
+	modify exact [ax bx];
+
+u32     or_long_asm(u32 *flags,u32 d, u32 s);
+#pragma aux or_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"or	eax,ebx"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [ebx]          \
+	value [eax]                     \
+	modify exact [eax ebx];
+
+u8      neg_byte_asm(u32 *flags,u8 d);
+#pragma aux neg_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"neg	al"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al]            		\
+	value [al]                      \
+	modify exact [al];
+
+u16     neg_word_asm(u32 *flags,u16 d);
+#pragma aux neg_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"neg	ax"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax]            		\
+	value [ax]                      \
+	modify exact [ax];
+
+u32     neg_long_asm(u32 *flags,u32 d);
+#pragma aux neg_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"neg	eax"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax]          		\
+	value [eax]                     \
+	modify exact [eax];
+
+u8      not_byte_asm(u32 *flags,u8 d);
+#pragma aux not_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"not	al"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al]            		\
+	value [al]                      \
+	modify exact [al];
+
+u16     not_word_asm(u32 *flags,u16 d);
+#pragma aux not_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"not	ax"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax]            		\
+	value [ax]                      \
+	modify exact [ax];
+
+u32     not_long_asm(u32 *flags,u32 d);
+#pragma aux not_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"not	eax"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax]          		\
+	value [eax]                     \
+	modify exact [eax];
+
+u8      rcl_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux rcl_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"rcl	al,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [cl]            \
+	value [al]                      \
+	modify exact [al cl];
+
+u16     rcl_word_asm(u32 *flags,u16 d, u8 s);
+#pragma aux rcl_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"rcl	ax,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [cl]            \
+	value [ax]                      \
+	modify exact [ax cl];
+
+u32     rcl_long_asm(u32 *flags,u32 d, u8 s);
+#pragma aux rcl_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"rcl	eax,cl"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [cl]          	\
+	value [eax]                     \
+	modify exact [eax cl];
+
+u8      rcr_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux rcr_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"rcr	al,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [cl]            \
+	value [al]                      \
+	modify exact [al cl];
+
+u16     rcr_word_asm(u32 *flags,u16 d, u8 s);
+#pragma aux rcr_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"rcr	ax,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [cl]            \
+	value [ax]                      \
+	modify exact [ax cl];
+
+u32     rcr_long_asm(u32 *flags,u32 d, u8 s);
+#pragma aux rcr_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"rcr	eax,cl"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [cl]          	\
+	value [eax]                     \
+	modify exact [eax cl];
+
+u8      rol_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux rol_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"rol	al,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [cl]            \
+	value [al]                      \
+	modify exact [al cl];
+
+u16     rol_word_asm(u32 *flags,u16 d, u8 s);
+#pragma aux rol_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"rol	ax,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [cl]            \
+	value [ax]                      \
+	modify exact [ax cl];
+
+u32     rol_long_asm(u32 *flags,u32 d, u8 s);
+#pragma aux rol_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"rol	eax,cl"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [cl]          	\
+	value [eax]                     \
+	modify exact [eax cl];
+
+u8      ror_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux ror_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"ror	al,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [cl]            \
+	value [al]                      \
+	modify exact [al cl];
+
+u16     ror_word_asm(u32 *flags,u16 d, u8 s);
+#pragma aux ror_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"ror	ax,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [cl]            \
+	value [ax]                      \
+	modify exact [ax cl];
+
+u32     ror_long_asm(u32 *flags,u32 d, u8 s);
+#pragma aux ror_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"ror	eax,cl"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [cl]          	\
+	value [eax]                     \
+	modify exact [eax cl];
+
+u8      shl_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux shl_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shl	al,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [cl]            \
+	value [al]                      \
+	modify exact [al cl];
+
+u16     shl_word_asm(u32 *flags,u16 d, u8 s);
+#pragma aux shl_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shl	ax,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [cl]            \
+	value [ax]                      \
+	modify exact [ax cl];
+
+u32     shl_long_asm(u32 *flags,u32 d, u8 s);
+#pragma aux shl_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shl	eax,cl"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [cl]          	\
+	value [eax]                     \
+	modify exact [eax cl];
+
+u8      shr_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux shr_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shr	al,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [cl]            \
+	value [al]                      \
+	modify exact [al cl];
+
+u16     shr_word_asm(u32 *flags,u16 d, u8 s);
+#pragma aux shr_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shr	ax,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [cl]            \
+	value [ax]                      \
+	modify exact [ax cl];
+
+u32     shr_long_asm(u32 *flags,u32 d, u8 s);
+#pragma aux shr_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shr	eax,cl"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [cl]          	\
+	value [eax]                     \
+	modify exact [eax cl];
+
+u8      sar_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux sar_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"sar	al,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [cl]            \
+	value [al]                      \
+	modify exact [al cl];
+
+u16     sar_word_asm(u32 *flags,u16 d, u8 s);
+#pragma aux sar_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"sar	ax,cl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [cl]            \
+	value [ax]                      \
+	modify exact [ax cl];
+
+u32     sar_long_asm(u32 *flags,u32 d, u8 s);
+#pragma aux sar_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"sar	eax,cl"                	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [cl]          	\
+	value [eax]                     \
+	modify exact [eax cl];
+
+u16		shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s);
+#pragma aux shld_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shld	ax,dx,cl"               \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [dx] [cl]       \
+	value [ax]                      \
+	modify exact [ax dx cl];
+
+u32     shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s);
+#pragma aux shld_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shld	eax,edx,cl"             \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [edx] [cl]     \
+	value [eax]                     \
+	modify exact [eax edx cl];
+
+u16		shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s);
+#pragma aux shrd_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shrd	ax,dx,cl"               \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [dx] [cl]       \
+	value [ax]                      \
+	modify exact [ax dx cl];
+
+u32     shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s);
+#pragma aux shrd_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"shrd	eax,edx,cl"             \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [edx] [cl]     \
+	value [eax]                     \
+	modify exact [eax edx cl];
+
+u8      sbb_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux sbb_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"sbb	al,bl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [bl]            \
+	value [al]                      \
+	modify exact [al bl];
+
+u16     sbb_word_asm(u32 *flags,u16 d, u16 s);
+#pragma aux sbb_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"sbb	ax,bx"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [bx]            \
+	value [ax]                      \
+	modify exact [ax bx];
+
+u32     sbb_long_asm(u32 *flags,u32 d, u32 s);
+#pragma aux sbb_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"sbb	eax,ebx"                \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [ebx]          \
+	value [eax]                     \
+	modify exact [eax ebx];
+
+u8      sub_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux sub_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"sub	al,bl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [bl]            \
+	value [al]                      \
+	modify exact [al bl];
+
+u16     sub_word_asm(u32 *flags,u16 d, u16 s);
+#pragma aux sub_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"sub	ax,bx"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [bx]            \
+	value [ax]                      \
+	modify exact [ax bx];
+
+u32     sub_long_asm(u32 *flags,u32 d, u32 s);
+#pragma aux sub_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"sub	eax,ebx"                \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [ebx]          \
+	value [eax]                     \
+	modify exact [eax ebx];
+
+void	test_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux test_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"test	al,bl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [bl]            \
+	modify exact [al bl];
+
+void	test_word_asm(u32 *flags,u16 d, u16 s);
+#pragma aux test_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"test	ax,bx"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [bx]            \
+	modify exact [ax bx];
+
+void	test_long_asm(u32 *flags,u32 d, u32 s);
+#pragma aux test_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"test	eax,ebx"                \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [ebx]          \
+	modify exact [eax ebx];
+
+u8      xor_byte_asm(u32 *flags,u8 d, u8 s);
+#pragma aux xor_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"xor	al,bl"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [al] [bl]            \
+	value [al]                      \
+	modify exact [al bl];
+
+u16     xor_word_asm(u32 *flags,u16 d, u16 s);
+#pragma aux xor_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"xor	ax,bx"                  \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [ax] [bx]            \
+	value [ax]                      \
+	modify exact [ax bx];
+
+u32     xor_long_asm(u32 *flags,u32 d, u32 s);
+#pragma aux xor_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"xor	eax,ebx"                \
+	"pushf"                         \
+	"pop	[edi]"            		\
+	parm [edi] [eax] [ebx]          \
+	value [eax]                     \
+	modify exact [eax ebx];
+
+void    imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s);
+#pragma aux imul_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"imul	bl"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],ax"				\
+	parm [edi] [esi] [al] [bl]      \
+	modify exact [esi ax bl];
+
+void    imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s);
+#pragma aux imul_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"imul	bx"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],ax"				\
+	"mov	[ecx],dx"				\
+	parm [edi] [esi] [ecx] [ax] [bx]\
+	modify exact [esi edi ax bx dx];
+
+void    imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s);
+#pragma aux imul_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"imul	ebx"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],eax"				\
+	"mov	[ecx],edx"				\
+	parm [edi] [esi] [ecx] [eax] [ebx] \
+	modify exact [esi edi eax ebx edx];
+
+void    mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s);
+#pragma aux mul_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"mul	bl"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],ax"				\
+	parm [edi] [esi] [al] [bl]      \
+	modify exact [esi ax bl];
+
+void    mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s);
+#pragma aux mul_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"mul	bx"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],ax"				\
+	"mov	[ecx],dx"				\
+	parm [edi] [esi] [ecx] [ax] [bx]\
+	modify exact [esi edi ax bx dx];
+
+void    mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s);
+#pragma aux mul_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"mul	ebx"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],eax"				\
+	"mov	[ecx],edx"				\
+	parm [edi] [esi] [ecx] [eax] [ebx] \
+	modify exact [esi edi eax ebx edx];
+
+void	idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s);
+#pragma aux idiv_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"idiv	bl"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],al"				\
+	"mov	[ecx],ah"				\
+	parm [edi] [esi] [ecx] [ax] [bl]\
+	modify exact [esi edi ax bl];
+
+void	idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s);
+#pragma aux idiv_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"idiv	bx"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],ax"				\
+	"mov	[ecx],dx"				\
+	parm [edi] [esi] [ecx] [ax] [dx] [bx]\
+	modify exact [esi edi ax dx bx];
+
+void	idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s);
+#pragma aux idiv_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"idiv	ebx"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],eax"				\
+	"mov	[ecx],edx"				\
+	parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
+	modify exact [esi edi eax edx ebx];
+
+void	div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s);
+#pragma aux div_byte_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"div	bl"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],al"				\
+	"mov	[ecx],ah"				\
+	parm [edi] [esi] [ecx] [ax] [bl]\
+	modify exact [esi edi ax bl];
+
+void	div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s);
+#pragma aux div_word_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"div	bx"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],ax"				\
+	"mov	[ecx],dx"				\
+	parm [edi] [esi] [ecx] [ax] [dx] [bx]\
+	modify exact [esi edi ax dx bx];
+
+void	div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s);
+#pragma aux div_long_asm =			\
+	"push	[edi]"            		\
+	"popf"                         	\
+	"div	ebx"                  	\
+	"pushf"                         \
+	"pop	[edi]"            		\
+	"mov	[esi],eax"				\
+	"mov	[ecx],edx"				\
+	parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
+	modify exact [esi edi eax edx ebx];
+
+#endif
+
+#endif /* __X86EMU_PRIM_ASM_H */
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h
new file mode 100755
index 0000000..1633fe1
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h
@@ -0,0 +1,231 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for primitive operation functions.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_PRIM_OPS_H
+#define __X86EMU_PRIM_OPS_H
+
+#include "x86emu/prim_asm.h"
+
+#ifdef  __cplusplus
+extern "C" {            			/* Use "C" linkage when in C++ mode */
+#endif
+
+u16     aaa_word (u16 d);
+u16     aas_word (u16 d);
+u16     aad_word (u16 d);
+u16     aam_word (u8 d);
+u8      adc_byte (u8 d, u8 s);
+u16     adc_word (u16 d, u16 s);
+u32     adc_long (u32 d, u32 s);
+u8      add_byte (u8 d, u8 s);
+u16     add_word (u16 d, u16 s);
+u32     add_long (u32 d, u32 s);
+u8      and_byte (u8 d, u8 s);
+u16     and_word (u16 d, u16 s);
+u32     and_long (u32 d, u32 s);
+u8      cmp_byte (u8 d, u8 s);
+u16     cmp_word (u16 d, u16 s);
+u32     cmp_long (u32 d, u32 s);
+u8      daa_byte (u8 d);
+u8      das_byte (u8 d);
+u8      dec_byte (u8 d);
+u16     dec_word (u16 d);
+u32     dec_long (u32 d);
+u8      inc_byte (u8 d);
+u16     inc_word (u16 d);
+u32     inc_long (u32 d);
+u8      or_byte (u8 d, u8 s);
+u16     or_word (u16 d, u16 s);
+u32     or_long (u32 d, u32 s);
+u8      neg_byte (u8 s);
+u16     neg_word (u16 s);
+u32     neg_long (u32 s);
+u8      not_byte (u8 s);
+u16     not_word (u16 s);
+u32     not_long (u32 s);
+u8      rcl_byte (u8 d, u8 s);
+u16     rcl_word (u16 d, u8 s);
+u32     rcl_long (u32 d, u8 s);
+u8      rcr_byte (u8 d, u8 s);
+u16     rcr_word (u16 d, u8 s);
+u32     rcr_long (u32 d, u8 s);
+u8      rol_byte (u8 d, u8 s);
+u16     rol_word (u16 d, u8 s);
+u32     rol_long (u32 d, u8 s);
+u8      ror_byte (u8 d, u8 s);
+u16     ror_word (u16 d, u8 s);
+u32     ror_long (u32 d, u8 s);
+u8      shl_byte (u8 d, u8 s);
+u16     shl_word (u16 d, u8 s);
+u32     shl_long (u32 d, u8 s);
+u8      shr_byte (u8 d, u8 s);
+u16     shr_word (u16 d, u8 s);
+u32     shr_long (u32 d, u8 s);
+u8      sar_byte (u8 d, u8 s);
+u16     sar_word (u16 d, u8 s);
+u32     sar_long (u32 d, u8 s);
+u16     shld_word (u16 d, u16 fill, u8 s);
+u32     shld_long (u32 d, u32 fill, u8 s);
+u16     shrd_word (u16 d, u16 fill, u8 s);
+u32     shrd_long (u32 d, u32 fill, u8 s);
+u8      sbb_byte (u8 d, u8 s);
+u16     sbb_word (u16 d, u16 s);
+u32     sbb_long (u32 d, u32 s);
+u8      sub_byte (u8 d, u8 s);
+u16     sub_word (u16 d, u16 s);
+u32     sub_long (u32 d, u32 s);
+void    test_byte (u8 d, u8 s);
+void    test_word (u16 d, u16 s);
+void    test_long (u32 d, u32 s);
+u8      xor_byte (u8 d, u8 s);
+u16     xor_word (u16 d, u16 s);
+u32     xor_long (u32 d, u32 s);
+void    imul_byte (u8 s);
+void    imul_word (u16 s);
+void    imul_long (u32 s);
+void 	imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s);
+void    mul_byte (u8 s);
+void    mul_word (u16 s);
+void    mul_long (u32 s);
+void    idiv_byte (u8 s);
+void    idiv_word (u16 s);
+void    idiv_long (u32 s);
+void    div_byte (u8 s);
+void    div_word (u16 s);
+void    div_long (u32 s);
+void    ins (int size);
+void    outs (int size);
+u16     mem_access_word (int addr);
+void    push_word (u16 w);
+void    push_long (u32 w);
+u16     pop_word (void);
+u32		pop_long (void);
+
+#if  defined(__HAVE_INLINE_ASSEMBLER__) && !defined(PRIM_OPS_NO_REDEFINE_ASM)
+
+#define	aaa_word(d)		aaa_word_asm(&M.x86.R_EFLG,d)
+#define aas_word(d)		aas_word_asm(&M.x86.R_EFLG,d)
+#define aad_word(d)		aad_word_asm(&M.x86.R_EFLG,d)
+#define aam_word(d)		aam_word_asm(&M.x86.R_EFLG,d)
+#define adc_byte(d,s)	adc_byte_asm(&M.x86.R_EFLG,d,s)
+#define adc_word(d,s)	adc_word_asm(&M.x86.R_EFLG,d,s)
+#define adc_long(d,s)	adc_long_asm(&M.x86.R_EFLG,d,s)
+#define add_byte(d,s) 	add_byte_asm(&M.x86.R_EFLG,d,s)
+#define add_word(d,s)	add_word_asm(&M.x86.R_EFLG,d,s)
+#define add_long(d,s)	add_long_asm(&M.x86.R_EFLG,d,s)
+#define and_byte(d,s)	and_byte_asm(&M.x86.R_EFLG,d,s)
+#define and_word(d,s)	and_word_asm(&M.x86.R_EFLG,d,s)
+#define and_long(d,s)	and_long_asm(&M.x86.R_EFLG,d,s)
+#define cmp_byte(d,s)	cmp_byte_asm(&M.x86.R_EFLG,d,s)
+#define cmp_word(d,s)	cmp_word_asm(&M.x86.R_EFLG,d,s)
+#define cmp_long(d,s)	cmp_long_asm(&M.x86.R_EFLG,d,s)
+#define daa_byte(d)		daa_byte_asm(&M.x86.R_EFLG,d)
+#define das_byte(d)		das_byte_asm(&M.x86.R_EFLG,d)
+#define dec_byte(d)		dec_byte_asm(&M.x86.R_EFLG,d)
+#define dec_word(d)		dec_word_asm(&M.x86.R_EFLG,d)
+#define dec_long(d)		dec_long_asm(&M.x86.R_EFLG,d)
+#define inc_byte(d)		inc_byte_asm(&M.x86.R_EFLG,d)
+#define inc_word(d)		inc_word_asm(&M.x86.R_EFLG,d)
+#define inc_long(d)		inc_long_asm(&M.x86.R_EFLG,d)
+#define or_byte(d,s)	or_byte_asm(&M.x86.R_EFLG,d,s)
+#define or_word(d,s)	or_word_asm(&M.x86.R_EFLG,d,s)
+#define or_long(d,s)	or_long_asm(&M.x86.R_EFLG,d,s)
+#define neg_byte(s)		neg_byte_asm(&M.x86.R_EFLG,s)
+#define neg_word(s)		neg_word_asm(&M.x86.R_EFLG,s)
+#define neg_long(s)		neg_long_asm(&M.x86.R_EFLG,s)
+#define not_byte(s)		not_byte_asm(&M.x86.R_EFLG,s)
+#define not_word(s)		not_word_asm(&M.x86.R_EFLG,s)
+#define not_long(s)		not_long_asm(&M.x86.R_EFLG,s)
+#define rcl_byte(d,s)	rcl_byte_asm(&M.x86.R_EFLG,d,s)
+#define rcl_word(d,s)	rcl_word_asm(&M.x86.R_EFLG,d,s)
+#define rcl_long(d,s)	rcl_long_asm(&M.x86.R_EFLG,d,s)
+#define rcr_byte(d,s)	rcr_byte_asm(&M.x86.R_EFLG,d,s)
+#define rcr_word(d,s)	rcr_word_asm(&M.x86.R_EFLG,d,s)
+#define rcr_long(d,s)	rcr_long_asm(&M.x86.R_EFLG,d,s)
+#define rol_byte(d,s)	rol_byte_asm(&M.x86.R_EFLG,d,s)
+#define rol_word(d,s)	rol_word_asm(&M.x86.R_EFLG,d,s)
+#define rol_long(d,s)	rol_long_asm(&M.x86.R_EFLG,d,s)
+#define ror_byte(d,s)	ror_byte_asm(&M.x86.R_EFLG,d,s)
+#define ror_word(d,s)	ror_word_asm(&M.x86.R_EFLG,d,s)
+#define ror_long(d,s)	ror_long_asm(&M.x86.R_EFLG,d,s)
+#define shl_byte(d,s)	shl_byte_asm(&M.x86.R_EFLG,d,s)
+#define shl_word(d,s)	shl_word_asm(&M.x86.R_EFLG,d,s)
+#define shl_long(d,s)	shl_long_asm(&M.x86.R_EFLG,d,s)
+#define shr_byte(d,s)	shr_byte_asm(&M.x86.R_EFLG,d,s)
+#define shr_word(d,s)	shr_word_asm(&M.x86.R_EFLG,d,s)
+#define shr_long(d,s)	shr_long_asm(&M.x86.R_EFLG,d,s)
+#define sar_byte(d,s)	sar_byte_asm(&M.x86.R_EFLG,d,s)
+#define sar_word(d,s)	sar_word_asm(&M.x86.R_EFLG,d,s)
+#define sar_long(d,s)	sar_long_asm(&M.x86.R_EFLG,d,s)
+#define shld_word(d,fill,s)	shld_word_asm(&M.x86.R_EFLG,d,fill,s)
+#define shld_long(d,fill,s)	shld_long_asm(&M.x86.R_EFLG,d,fill,s)
+#define shrd_word(d,fill,s)	shrd_word_asm(&M.x86.R_EFLG,d,fill,s)
+#define shrd_long(d,fill,s)	shrd_long_asm(&M.x86.R_EFLG,d,fill,s)
+#define sbb_byte(d,s)	sbb_byte_asm(&M.x86.R_EFLG,d,s)
+#define sbb_word(d,s)	sbb_word_asm(&M.x86.R_EFLG,d,s)
+#define sbb_long(d,s)	sbb_long_asm(&M.x86.R_EFLG,d,s)
+#define sub_byte(d,s)	sub_byte_asm(&M.x86.R_EFLG,d,s)
+#define sub_word(d,s)	sub_word_asm(&M.x86.R_EFLG,d,s)
+#define sub_long(d,s)	sub_long_asm(&M.x86.R_EFLG,d,s)
+#define test_byte(d,s)	test_byte_asm(&M.x86.R_EFLG,d,s)
+#define test_word(d,s)	test_word_asm(&M.x86.R_EFLG,d,s)
+#define test_long(d,s)	test_long_asm(&M.x86.R_EFLG,d,s)
+#define xor_byte(d,s)	xor_byte_asm(&M.x86.R_EFLG,d,s)
+#define xor_word(d,s)	xor_word_asm(&M.x86.R_EFLG,d,s)
+#define xor_long(d,s)	xor_long_asm(&M.x86.R_EFLG,d,s)
+#define imul_byte(s)	imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s)
+#define imul_word(s)	imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s)
+#define imul_long(s)	imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s)
+#define imul_long_direct(res_lo,res_hi,d,s)	imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s)
+#define mul_byte(s)		mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s)
+#define mul_word(s)		mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s)
+#define mul_long(s)		mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s)
+#define idiv_byte(s)	idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s)
+#define idiv_word(s)	idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s)
+#define idiv_long(s)	idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s)
+#define div_byte(s)		div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s)
+#define div_word(s)		div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s)
+#define div_long(s)		div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s)
+
+#endif
+
+#ifdef  __cplusplus
+}                       			/* End of "C" linkage for C++   	*/
+#endif
+
+#endif /* __X86EMU_PRIM_OPS_H */
diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h
new file mode 100755
index 0000000..bff4903
--- /dev/null
+++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h
@@ -0,0 +1,98 @@
+/****************************************************************************
+*
+*						Realmode X86 Emulator Library
+*
+*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+* 				     Copyright (C) David Mosberger-Tang
+* 					   Copyright (C) 1999 Egbert Eich
+*
+*  ========================================================================
+*
+*  Permission to use, copy, modify, distribute, and sell this software and
+*  its documentation for any purpose is hereby granted without fee,
+*  provided that the above copyright notice appear in all copies and that
+*  both that copyright notice and this permission notice appear in
+*  supporting documentation, and that the name of the authors not be used
+*  in advertising or publicity pertaining to distribution of the software
+*  without specific, written prior permission.  The authors makes no
+*  representations about the suitability of this software for any purpose.
+*  It is provided "as is" without express or implied warranty.
+*
+*  THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+*  INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+*  EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+*  CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
+*  USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+*  OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+*  PERFORMANCE OF THIS SOFTWARE.
+*
+*  ========================================================================
+*
+* Language:		ANSI C
+* Environment:	Any
+* Developer:    Kendall Bennett
+*
+* Description:  Header file for system specific functions. These functions
+*				are always compiled and linked in the OS depedent libraries,
+*				and never in a binary portable driver.
+*
+****************************************************************************/
+
+#ifndef __X86EMU_X86EMUI_H
+#define __X86EMU_X86EMUI_H
+
+/* If we are compiling in C++ mode, we can compile some functions as
+ * inline to increase performance (however the code size increases quite
+ * dramatically in this case).
+ */
+
+#if	defined(__cplusplus) && !defined(_NO_INLINE)
+#define	_INLINE	inline
+#else
+#define	_INLINE static
+#endif
+
+/* Get rid of unused parameters in C++ compilation mode */
+
+#ifdef __cplusplus
+#define	X86EMU_UNUSED(v)
+#else
+#define	X86EMU_UNUSED(v)	v
+#endif
+
+#include "x86emu.h"
+#include "x86emu/regs.h"
+#include "x86emu/debug.h"
+#include "x86emu/decode.h"
+#include "x86emu/ops.h"
+#include "x86emu/prim_ops.h"
+#include "x86emu/fpu.h"
+#include "x86emu/fpu_regs.h"
+#include <stdio.h>
+#include <string.h>
+
+/*--------------------------- Inline Functions ----------------------------*/
+
+#ifdef  __cplusplus
+extern "C" {            			/* Use "C" linkage when in C++ mode */
+#endif
+
+extern u8  	(X86APIP sys_rdb)(u32 addr);
+extern u16 	(X86APIP sys_rdw)(u32 addr);
+extern u32 	(X86APIP sys_rdl)(u32 addr);
+extern void (X86APIP sys_wrb)(u32 addr,u8 val);
+extern void (X86APIP sys_wrw)(u32 addr,u16 val);
+extern void (X86APIP sys_wrl)(u32 addr,u32 val);
+
+extern u8  	(X86APIP sys_inb)(X86EMU_pioAddr addr);
+extern u16 	(X86APIP sys_inw)(X86EMU_pioAddr addr);
+extern u32 	(X86APIP sys_inl)(X86EMU_pioAddr addr);
+extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val);
+extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val);
+extern void	(X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val);
+
+#ifdef  __cplusplus
+}                       			/* End of "C" linkage for C++   	*/
+#endif
+
+#endif /* __X86EMU_X86EMUI_H */
diff --git a/board/MAI/bios_emulator/x86interface.c b/board/MAI/bios_emulator/x86interface.c
new file mode 100755
index 0000000..909cb3c
--- /dev/null
+++ b/board/MAI/bios_emulator/x86interface.c
@@ -0,0 +1,814 @@
+#include "x86emu.h"
+#include "glue.h"
+
+
+/*
+ * This isn't nice, but there are a lot of incompatibilities in the U-Boot and scitech include
+ * files that this is the only really workable solution.
+ * Might be cleaned out later.
+ */
+
+#ifdef DEBUG
+#undef DEBUG
+#endif
+
+#undef IO_LOGGING
+#undef MEM_LOGGING
+
+#ifdef IO_LOGGING
+#define LOGIO(port, format, args...) if (dolog(port)) _printf(format , ## args)
+#else
+#define LOGIO(port, format, args...)
+#endif
+
+#ifdef MEM_LOGGIN
+#define LOGMEM(format, args...) _printf(format , ## args)
+#else
+#define LOGMEM(format, args...)
+#endif
+
+#ifdef DEBUG
+#define PRINTF(format, args...) _printf(format , ## args)
+#else
+#define PRINTF(format, argc...)
+#endif
+
+typedef unsigned char UBYTE;
+typedef unsigned short UWORD;
+typedef unsigned long ULONG;
+
+typedef char BYTE;
+typedef short WORT;
+typedef long LONG;
+
+#define EMULATOR_MEM_SIZE       (1024*1024)
+#define EMULATOR_BIOS_OFFSET    0xC0000
+#define EMULATOR_STRAP_OFFSET   0x30000
+#define EMULATOR_STACK_OFFSET   0x20000
+#define EMULATOR_LOGO_OFFSET    0x40000 /* If you change this, change the strap code, too */
+#define VIDEO_BASE (void *)0xFD0B8000
+
+extern char *getenv(char *);
+extern int tstc(void);
+extern int getc(void);
+extern unsigned char video_get_attr(void);
+
+int atoi(char *string)
+{
+    int res = 0;
+    while (*string>='0' && *string <='9')
+    {
+	res *= 10;
+	res += *string-'0';
+	string++;
+    }
+
+    return res;
+}
+
+void cons_gets(char *buffer)
+{
+    int i = 0;
+    char c = 0;
+
+    buffer[0] = 0;
+    if (getenv("x86_runthru")) return; /*FIXME: */
+    while (c != 0x0D && c != 0x0A)
+    {
+	while (!tstc());
+	c = getc();
+	if (c>=32 && c < 127)
+	{
+	    buffer[i] = c;
+	    i++;
+	    buffer[i] = 0;
+	    putc(c);
+	}
+	else
+	{
+	    if (c == 0x08)
+	    {
+		if (i>0) i--;
+		buffer[i] = 0;
+	    }
+	}
+    }
+    buffer[i] = '\n';
+    buffer[i+1] = 0;
+}
+
+char *bios_date = "08/14/02";
+UBYTE model = 0xFC;
+UBYTE submodel = 0x00;
+
+static inline UBYTE read_byte(volatile UBYTE* from)
+{
+    int x;
+    asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from));
+    return (UBYTE)x;
+}
+
+static inline void write_byte(volatile UBYTE *to, int x)
+{
+    asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x));
+}
+
+static inline UWORD read_word_little(volatile UWORD *from)
+{
+    int x;
+    asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from));
+    return (UWORD)x;
+}
+
+static inline UWORD read_word_big(volatile UWORD *from)
+{
+    int x;
+    asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from));
+    return (UWORD)x;
+}
+
+static inline void write_word_little(volatile UWORD *to, int x)
+{
+    asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to));
+}
+
+static inline void write_word_big(volatile UWORD *to, int x)
+{
+    asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x));
+}
+
+static inline ULONG read_long_little(volatile ULONG *from)
+{
+    unsigned long x;
+    asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from));
+    return (ULONG)x;
+}
+
+static inline ULONG read_long_big(volatile ULONG *from)
+{
+    unsigned long x;
+    asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from));
+    return (ULONG)x;
+}
+
+static inline void write_long_little(volatile ULONG *to, ULONG x)
+{
+    asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to));
+}
+
+static inline void write_long_big(volatile ULONG *to, ULONG x)
+{
+    asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x));
+}
+
+static int log_init = 0;
+static int log_do = 0;
+static int log_low = 0;
+
+int dolog(int port)
+{
+    if (log_init && log_do)
+    {
+	if (log_low && port > 0x400) return 0;
+	return 1;
+    }
+
+    if (!log_init)
+    {
+	log_init = 1;
+	log_do = (getenv("x86_logio") != (char *)0);
+	log_low = (getenv("x86_loglow") != (char *)0);
+	if (log_do)
+	{
+	    if (log_low && port > 0x400) return 0;
+	    return 1;
+	}
+    }
+    return 0;
+}
+
+/* Converts an emulator address to a physical address. */
+/* Handles all special cases (bios date, model etc), and might need work */
+u32 memaddr(u32 addr)
+{
+/*    if (addr >= 0xF0000 && addr < 0xFFFFF) printf("WARNING: Segment F access (0x%x)\n", addr); */
+/*    printf("MemAddr=%p\n", addr); */
+    if (addr >= 0xA0000 && addr < 0xC0000)
+	return 0xFD000000 + addr;
+    else if (addr >= 0xFFFF5 && addr < 0xFFFFE)
+    {
+	return (u32)bios_date+addr-0xFFFF5;
+    }
+    else if (addr == 0xFFFFE)
+	return (u32)&model;
+    else if (addr == 0xFFFFF)
+	return (u32)&submodel;
+    else if (addr >= 0x80000000)
+    {
+	/*printf("Warning: High memory access at 0x%x\n", addr); */
+	return addr;
+    }
+    else
+	return (u32)M.mem_base+addr;
+}
+
+u8 A1_rdb(u32 addr)
+{
+    u8 a = read_byte((UBYTE *)memaddr(addr));
+    LOGMEM("rdb: %x -> %x\n", addr, a);
+    return a;
+}
+
+u16 A1_rdw(u32 addr)
+{
+    u16 a = read_word_little((UWORD *)memaddr(addr));
+    LOGMEM("rdw: %x -> %x\n", addr, a);
+    return a;
+}
+
+u32 A1_rdl(u32 addr)
+{
+    u32 a = read_long_little((ULONG *)memaddr(addr));
+    LOGMEM("rdl: %x -> %x\n", addr, a);
+    return a;
+}
+
+void A1_wrb(u32 addr, u8 val)
+{
+    LOGMEM("wrb: %x <- %x\n", addr, val);
+    write_byte((UBYTE *)memaddr(addr), val);
+}
+
+void A1_wrw(u32 addr, u16 val)
+{
+    LOGMEM("wrw: %x <- %x\n", addr, val);
+    write_word_little((UWORD *)memaddr(addr), val);
+}
+
+void A1_wrl(u32 addr, u32 val)
+{
+    LOGMEM("wrl: %x <- %x\n", addr, val);
+    write_long_little((ULONG *)memaddr(addr), val);
+}
+
+X86EMU_memFuncs _A1_mem =
+{
+    A1_rdb,
+    A1_rdw,
+    A1_rdl,
+    A1_wrb,
+    A1_wrw,
+    A1_wrl,
+};
+
+#define ARTICIAS_PCI_CFGADDR  0xfec00cf8
+#define ARTICIAS_PCI_CFGDATA  0xfee00cfc
+#define IOBASE                0xFE000000
+
+#define in_byte(from) read_byte( (UBYTE *)port_to_mem(from))
+#define in_word(from) read_word_little((UWORD *)port_to_mem(from))
+#define in_long(from) read_long_little((ULONG *)port_to_mem(from))
+#define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val)
+#define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val)
+#define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val)
+
+u32 port_to_mem(int port)
+{
+    if (port >= 0xCFC && port <= 0xCFF) return 0xFEE00000+port;
+    else if (port >= 0xCF8 && port <= 0xCFB) return 0xFEC00000+port;
+    else return IOBASE + port;
+}
+
+u8 A1_inb(int port)
+{
+    u8 a;
+    /*if (port == 0x3BA) return 0; */
+    a = in_byte(port);
+    LOGIO(port, "inb: %Xh -> %d (%Xh)\n", port, a, a);
+    return a;
+}
+
+u16 A1_inw(int port)
+{
+    u16 a = in_word(port);
+    LOGIO(port, "inw: %Xh -> %d (%Xh)\n", port, a, a);
+    return a;
+}
+
+u32 A1_inl(int port)
+{
+    u32 a = in_long(port);
+    LOGIO(port, "inl: %Xh -> %d (%Xh)\n", port, a, a);
+    return a;
+}
+
+void A1_outb(int port, u8 val)
+{
+    LOGIO(port, "outb: %Xh <- %d (%Xh)\n", port, val, val);
+/*    if (port == 0xCF8) port = 0xCFB;
+    else if (port == 0xCF9) port = 0xCFA;
+    else if (port == 0xCFA) port = 0xCF9;
+    else if (port == 0xCFB) port = 0xCF8;*/
+    out_byte(port, val);
+}
+
+void A1_outw(int port, u16 val)
+{
+    LOGIO(port, "outw: %Xh <- %d (%Xh)\n", port, val, val);
+    out_word(port, val);
+}
+
+void A1_outl(int port, u32 val)
+{
+    LOGIO(port, "outl: %Xh <- %d (%Xh)\n", port, val, val);
+    out_long(port, val);
+}
+
+X86EMU_pioFuncs _A1_pio =
+{
+    A1_inb,
+    A1_inw,
+    A1_inl,
+    A1_outb,
+    A1_outw,
+    A1_outl,
+};
+
+static int reloced_ops = 0;
+
+void reloc_ops(void *reloc_addr)
+{
+    extern void (*x86emu_optab[256])(u8);
+    extern void (*x86emu_optab2[256])(u8);
+    extern void tables_relocate(unsigned int offset);
+    int i;
+    unsigned long delta;
+    if (reloced_ops == 1) return;
+    reloced_ops = 1;
+
+    delta = TEXT_BASE - (unsigned long)reloc_addr;
+
+    for (i=0; i<256; i++)
+    {
+	x86emu_optab[i] -= delta;
+	x86emu_optab2[i] -= delta;
+    }
+
+    _A1_mem.rdb = A1_rdb;
+    _A1_mem.rdw = A1_rdw;
+    _A1_mem.rdl = A1_rdl;
+    _A1_mem.wrb = A1_wrb;
+    _A1_mem.wrw = A1_wrw;
+    _A1_mem.wrl = A1_wrl;
+
+    _A1_pio.inb = A1_inb;
+    _A1_pio.inw = A1_inw;
+    _A1_pio.inl = A1_inl;
+    _A1_pio.outb = A1_outb;
+    _A1_pio.outw = A1_outw;
+    _A1_pio.outl = A1_outl;
+
+    tables_relocate(delta);
+
+}
+
+
+#define ANY_KEY(text)				\
+    printf(text);				\
+    while (!tstc());
+
+
+unsigned char more_strap[] = {
+	0xb4, 0x0, 0xb0, 0x2, 0xcd, 0x10,
+};
+#define MORE_STRAP_BYTES 6 /* Additional bytes of strap code */
+
+
+unsigned char *done_msg="VGA Initialized\0";
+
+int execute_bios(pci_dev_t gr_dev, void *reloc_addr)
+{
+    extern void bios_init(void);
+    extern void remove_init_data(void);
+    extern int video_rows(void);
+    extern int video_cols(void);
+    extern int video_size(int, int);
+    u8 *strap;
+    unsigned char *logo;
+    u8 cfg;
+    int i;
+    char c;
+    char *s;
+#ifdef EASTEREGG
+    int easteregg_active = 0;
+#endif
+    char *pal_reset;
+    u8 *fb;
+    unsigned char *msg;
+    unsigned char current_attr;
+
+    PRINTF("Trying to remove init data\n");
+    remove_init_data();
+    PRINTF("Removed init data from cache, now in RAM\n");
+
+    reloc_ops(reloc_addr);
+    PRINTF("Attempting to run emulator on %02x:%02x:%02x\n",
+	   PCI_BUS(gr_dev), PCI_DEV(gr_dev), PCI_FUNC(gr_dev));
+
+    /* Enable compatibility hole for emulator access to frame buffer */
+    PRINTF("Enabling compatibility hole\n");
+    enable_compatibility_hole();
+
+    /* Allocate memory */
+    /* FIXME: We shouldn't use this much memory really. */
+    memset(&M, 0, sizeof(X86EMU_sysEnv));
+    M.mem_base = malloc(EMULATOR_MEM_SIZE);
+    M.mem_size = EMULATOR_MEM_SIZE;
+
+    if (!M.mem_base)
+    {
+	PRINTF("Unable to allocate one megabyte for emulator\n");
+	return 0;
+    }
+
+    if (attempt_map_rom(gr_dev, M.mem_base + EMULATOR_BIOS_OFFSET) == 0)
+    {
+	PRINTF("Error mapping rom. Emulation terminated\n");
+	return 0;
+    }
+
+#if 1 /*def DEBUG*/
+    s = getenv("x86_ask_start");
+    if (s)
+    {
+	printf("Press 'q' to skip initialization, 'd' for dry init\n'i' for i/o session");
+	while (!tstc());
+	c = getc();
+	if (c == 'q') return 0;
+	if (c == 'd')
+	{
+	    extern void bios_set_mode(int mode);
+	    bios_set_mode(0x03);
+	    return 0;
+	}
+	if (c == 'i') do_inout();
+    }
+
+
+#endif
+
+#ifdef EASTEREGG
+/*    if (tstc())
+    {
+	if (getc() == 'c')
+	{
+	    easteregg_active = 1;
+	}
+    }
+*/
+    if (getenv("easteregg"))
+    {
+	easteregg_active = 1;
+    }
+
+    if (easteregg_active)
+    {
+	/* Yay! */
+	setenv("x86_mode", "1");
+	setenv("vga_fg_color", "11");
+	setenv("vga_bg_color", "1");
+	easteregg_active = 1;
+    }
+#endif
+
+    strap = (u8*)M.mem_base + EMULATOR_STRAP_OFFSET;
+
+    {
+	char *m = getenv("x86_mode");
+	if (m)
+	{
+	    more_strap[3] = atoi(m);
+	    if (more_strap[3] == 1) video_size(40, 25);
+	    else                    video_size(80, 25);
+	}
+    }
+
+    /*
+     * Poke the strap routine. This might need a bit of extending
+     * if there is a mode switch involved, i.e. we want to int10
+     * afterwards to set a different graphics mode, or alternatively
+     * there might be a different start address requirement if the
+     * ROM doesn't have an x86 image in its first image.
+     */
+
+    PRINTF("Poking strap...\n");
+
+    /* FAR CALL c000:0003 */
+    *strap++ = 0x9A; *strap++ = 0x03; *strap++ = 0x00;
+    *strap++ = 0x00; *strap++ = 0xC0;
+
+#if 1
+    /* insert additional strap code */
+    for (i=0; i < MORE_STRAP_BYTES; i++)
+    {
+	*strap++ = more_strap[i];
+    }
+#endif
+    /* HALT */
+    *strap++ = 0xF4;
+
+    PRINTF("Setting up logo data\n");
+    logo = (unsigned char *)M.mem_base + EMULATOR_LOGO_OFFSET;
+    for (i=0; i<16; i++)
+    {
+	*logo++ = 0xFF;
+    }
+
+    /*
+     * Setup the init parameters.
+     * Per PCI specs, AH must contain the bus and AL
+     * must contain the devfn, encoded as (dev<<3)|fn
+     */
+
+    /* Execution starts here */
+    M.x86.R_CS = SEG(EMULATOR_STRAP_OFFSET);
+    M.x86.R_IP = OFF(EMULATOR_STRAP_OFFSET);
+
+    /* Stack at top of ram */
+    M.x86.R_SS = SEG(EMULATOR_STACK_OFFSET);
+    M.x86.R_SP = OFF(EMULATOR_STACK_OFFSET);
+
+    /* Input parameters */
+    M.x86.R_AH = PCI_BUS(gr_dev);
+    M.x86.R_AL = (PCI_DEV(gr_dev)<<3) | PCI_FUNC(gr_dev);
+
+    /* Set the I/O and memory access functions */
+    X86EMU_setupMemFuncs(&_A1_mem);
+    X86EMU_setupPioFuncs(&_A1_pio);
+
+    /* Enable timer 2 */
+    cfg = in_byte(0x61); /* Get Misc control */
+    cfg |= 0x01;         /* Enable timer 2 */
+    out_byte(0x61, cfg); /* output again */
+
+    /* Set up the timers */
+    out_byte(0x43, 0x54);
+    out_byte(0x41, 0x18);
+
+    out_byte(0x43, 0x36);
+    out_byte(0x40, 0x00);
+    out_byte(0x40, 0x00);
+
+    out_byte(0x43, 0xb6);
+    out_byte(0x42, 0x31);
+    out_byte(0x42, 0x13);
+
+    /* Init the "BIOS". */
+    bios_init();
+
+    /* Video Card Reset */
+    out_byte(0x3D8, 0);
+    out_byte(0x3B8, 1);
+    (void)in_byte(0x3BA);
+    (void)in_byte(0x3DA);
+    out_byte(0x3C0, 0);
+    out_byte(0x61, 0xFC);
+
+#ifdef DEBUG
+    s = _getenv("x86_singlestep");
+    if (s && strcmp(s, "on")==0)
+    {
+	PRINTF("Enabling single stepping for debug\n");
+	X86EMU_trace_on();
+    }
+#endif
+
+    /* Ready set go... */
+    PRINTF("Running emulator\n");
+    X86EMU_exec();
+    PRINTF("Done running emulator\n");
+
+/* FIXME: Remove me */
+    pal_reset = getenv("x86_palette_reset");
+    if (pal_reset && strcmp(pal_reset, "on") == 0)
+    {
+	PRINTF("Palette reset\n");
+	/*(void)in_byte(0x3da); */
+	/*out_byte(0x3c0, 0); */
+
+	out_byte(0x3C8, 0);
+	out_byte(0x3C9, 0);
+	out_byte(0x3C9, 0);
+	out_byte(0x3C9, 0);
+	for (i=0; i<254; i++)
+	{
+	    out_byte(0x3C9, 63);
+	    out_byte(0x3C9, 63);
+	    out_byte(0x3C9, 63);
+	}
+
+	out_byte(0x3c0, 0x20);
+    }
+/* FIXME: remove me */
+#ifdef EASTEREGG
+    if (easteregg_active)
+    {
+	extern void video_easteregg(void);
+	video_easteregg();
+    }
+#endif
+/*
+    current_attr = video_get_attr();
+    fb = (u8 *)VIDEO_BASE;
+    for (i=0; i<video_rows()*video_cols()*2; i+=2)
+    {
+	*(fb+i) = ' ';
+	*(fb+i+1) = current_attr;
+    }
+
+    fb = (u8 *)VIDEO_BASE + (video_rows())-1*(video_cols()*2);
+    for (i=0; i<video_cols(); i++)
+    {
+	*(fb + 2*i)     = 32;
+	*(fb + 2*i + 1) = 0x17;
+    }
+
+    msg = done_msg;
+    while (*msg)
+    {
+	*fb = *msg;
+	fb  += 2;
+	msg ++;
+    }
+*/
+#ifdef DEBUG
+    if (getenv("x86_do_inout")) do_inout();
+#endif
+
+/*FIXME:    dcache_disable(); */
+    return 1;
+}
+
+/* Clean up the x86 mess */
+void shutdown_bios(void)
+{
+/*    disable_compatibility_hole(); */
+    /* Free the memory associated */
+    free(M.mem_base);
+
+}
+
+int to_int(char *buffer)
+{
+    int base = 0;
+    int res  = 0;
+
+    if (*buffer == '$')
+    {
+	base = 16;
+	buffer++;
+    }
+    else base = 10;
+
+    for (;;)
+    {
+	switch(*buffer)
+	{
+	case '0' ... '9':
+	    res *= base;
+	    res += *buffer - '0';
+	    break;
+	case 'A':
+	case 'a':
+	    res *= base;
+	    res += 10;
+	    break;
+	case 'B':
+	case 'b':
+	    res *= base;
+	    res += 11;
+	    break;
+	case 'C':
+	case 'c':
+	    res *= base;
+	    res += 12;
+	    break;
+	case 'D':
+	case 'd':
+	    res *= base;
+	    res += 13;
+	    break;
+	case 'E':
+	case 'e':
+	    res *= base;
+	    res += 14;
+	    break;
+	case 'F':
+	case 'f':
+	    res *= base;
+	    res += 15;
+	    break;
+	default:
+	    return res;
+	}
+	buffer++;
+    }
+    return res;
+}
+
+void one_arg(char *buffer, int *a)
+{
+    while (*buffer && *buffer != '\n')
+    {
+	if (*buffer == ' ') buffer++;
+	else break;
+    }
+
+    *a = to_int(buffer);
+}
+
+void two_args(char *buffer, int *a, int *b)
+{
+    while (*buffer && *buffer != '\n')
+    {
+	if (*buffer == ' ') buffer++;
+	else break;
+    }
+
+    *a = to_int(buffer);
+
+    while (*buffer && *buffer != '\n')
+    {
+	if (*buffer != ' ') buffer++;
+	else break;
+    }
+
+    while (*buffer && *buffer != '\n')
+    {
+	if (*buffer == ' ') buffer++;
+	else break;
+    }
+
+    *b = to_int(buffer);
+}
+
+void do_inout(void)
+{
+    char buffer[256];
+    char *arg1, *arg2;
+    int a,b;
+
+    printf("In/Out Session\nUse 'i[bwl]' for in, 'o[bwl]' for out and 'q' to quit\n");
+
+    do
+    {
+	cons_gets(buffer);
+	printf("\n");
+
+	*arg1 = buffer;
+	while (*arg1 != ' ' ) arg1++;
+	while (*arg1 == ' ') arg1++;
+
+	if (buffer[0] == 'i')
+	{
+	    one_arg(buffer+2, &a);
+	    switch (buffer[1])
+	    {
+	    case 'b':
+		printf("in_byte(%xh) = %xh\n", a, A1_inb(a));
+		break;
+	    case 'w':
+		printf("in_word(%xh) = %xh\n", a, A1_inw(a));
+		break;
+	    case 'l':
+		printf("in_dword(%xh) = %xh\n", a, A1_inl(a));
+		break;
+	    default:
+		printf("Invalid length '%c'\n", buffer[1]);
+		break;
+	    }
+	}
+	else if (buffer[0] == 'o')
+	{
+	    two_args(buffer+2, &a, &b);
+	    switch (buffer[1])
+	    {
+	    case 'b':
+		printf("out_byte(%d, %d)\n", a, b);
+		A1_outb(a,b);
+		break;
+	    case 'w':
+		printf("out_word(%d, %d)\n", a, b);
+		A1_outw(a, b);
+		break;
+	    case 'l':
+		printf("out_long(%d, %d)\n", a, b);
+		A1_outl(a, b);
+		break;
+	    default:
+		printf("Invalid length '%c'\n", buffer[1]);
+		break;
+	    }
+	} else if (buffer[0] == 'q') return;
+    } while (1);
+}
diff --git a/board/MAI/menu/cmd_menu.c b/board/MAI/menu/cmd_menu.c
new file mode 100755
index 0000000..a515bd8
--- /dev/null
+++ b/board/MAI/menu/cmd_menu.c
@@ -0,0 +1,16 @@
+#include <common.h>
+#include <command.h>
+
+int do_menu( cmd_tbl_t *cmdtp, /*bd_t *bd,*/ int flag, int argc, char *argv[] )
+{
+/*	printf("<NOT YET IMPLEMENTED>\n"); */
+	return 0;
+}
+
+#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP)
+U_BOOT_CMD(
+	menu,   1,      1,      do_menu,
+	"menu    - display BIOS setup menu\n",
+	""
+);
+#endif
diff --git a/board/MAI/menu/menu.c b/board/MAI/menu/menu.c
new file mode 100755
index 0000000..c0c63a8
--- /dev/null
+++ b/board/MAI/menu/menu.c
@@ -0,0 +1,66 @@
+#include "menu.h"
+
+#define SINGLE_BOX 0
+#define DOUBLE_BOX 1
+
+void video_draw_box(int style, int attr, char *title, int separate, int x, int y, int w, int h);
+void video_draw_text(int x, int y, int attr, char *text);
+void video_save_rect(int x, int y, int w, int h, void *save_area, int clearchar, int clearattr);
+void video_restore_rect(int x, int y, int w, int h, void *save_area);
+int  video_rows(void);
+int  video_cols(void);
+
+#define MAX_MENU_OPTIONS 200
+
+typedef struct
+{
+    int used;                  /* flag if this entry is used */
+    int entry_x;               /* Character column of the menu entry */
+    int entry_y;               /* Character line of the entry */
+    int option_x;              /* Character colum of the option (entry is same) */
+} option_data_t;
+
+option_data_t odata[MAX_MENU_OPTIONS];
+
+int normal_attr = 0x0F;
+int select_attr = 0x2F;
+int disabled_attr = 0x07;
+
+menu_t *root_menu;
+
+int menu_init (menu_t *root)
+{
+    char *s;
+    int i;
+
+    s = getenv("menu_normal");
+    if (s) normal_attr = atoi(s);
+
+    s = getenv("menu_select");
+    if (s) select_attr = atoi(s);
+
+    s = getenv("menu_disabled");
+    if (s) disabled_attr = atoi(s);
+
+    for (i=0; i<MAX_MENU_OPTIONS; i++) odata[i].used = 0;
+
+    root_menu = root;
+}
+
+option_data_t *menu_alloc_odata(void)
+{
+    int i;
+    for (int i=0; i<MAX_MENU_OPTIONS; i++)
+    {
+	if (odata[i].used == 0) return &odata[i];
+    }
+    return NULL;
+}
+
+void menu_free_odata(option_data_t *odata)
+{
+    odata->used = 0;
+}
+
+void menu_layout (menu_t *menu)
+{
diff --git a/board/MAI/menu/menu.h b/board/MAI/menu/menu.h
new file mode 100755
index 0000000..8aebb7d
--- /dev/null
+++ b/board/MAI/menu/menu.h
@@ -0,0 +1,174 @@
+#ifndef MENU_H
+#define MENU_H
+
+/* A single menu */
+typedef void (*menu_finish_callback)(struct menu_s *menu);
+
+typedef struct menu_s
+{
+    char *name;                     /* Menu name */
+    int  num_options;               /* Number of options in this menu */
+    int  flags;                     /* Various flags - see below */
+    int  option_align;              /* Aligns options to a field width of this much characters if != 0 */
+
+    struct menu_option_s **options; /* Pointer to this menu's options */
+    menu_finish_callback callback;  /* Called when the menu closes */
+} menu_t;
+
+/*
+ * type: Type of the option (see below)
+ * name: Name to display for this option
+ * help: Optional help string
+ * id  : optional id number
+ * sys : pointer for system-specific data, init to NULL and don't touch
+ */
+
+#define OPTION_PREAMBLE				\
+    int type;                     		\
+    char *name;   				\
+    char *help;   				\
+    int id;                                     \
+    void *sys;                                  \
+
+
+/*
+ * Menu option types.
+ * There are a number of different layouts for menu options depending
+ * on their types. Currently there are the following possibilities:
+ *
+ * Submenu:
+ *   This entry links to a new menu.
+ *
+ * Boolean:
+ *   A simple on/off toggle entry. Booleans can be either yes/no, 0/1 or on/off.
+ *   Optionally, this entry can enable/disable a set of other options. An example would
+ *   be to enable/disable on-board USB, and if enabled give access to further options like
+ *   irq settings, base address etc.
+ *
+ * Text:
+ *   A single line/limited number of characters text entry box. Text can be restricted
+ *   to a certain charset (digits/hex digits/all/custom). Result is also available as an
+ *   int if numeric.
+ *
+ * Selection:
+ *   One-of-many type of selection entry. User may choose on of a set of strings, which
+ *   maps to a specific value for the variable.
+ *
+ * Routine:
+ *   Selecting this calls an entry-specific routine. This can be used for saving contents etc.
+ *
+ * Custom:
+ *   Display and behaviour of this entry is defined by a set of callbacks.
+ */
+
+#define MENU_SUBMENU_TYPE 0
+typedef struct menu_submenu_s
+{
+    OPTION_PREAMBLE
+
+    menu_t *   submenu;            /* Pointer to the submenu */
+} menu_submenu_t;
+
+#define MENU_BOOLEAN_TYPE 1
+typedef struct menu_boolean_s
+{
+    OPTION_PREAMBLE
+
+    char *variable;                /* Name of the variable to getenv()/setenv() */
+    int subtype;                   /* Subtype (on/off, 0/1, yes/no, enable/disable), see below */
+    int mutex;                     /* Bit mask of options to enable/disable. Bit 0 is the option
+				      immediately following this one, bit 1 is the next one etc.
+				      bit 7 = 0 means to disable when this option is off,
+				      bit 7 = 1 means to disable when this option is on.
+				      An option is disabled when the type field's upper bit is set */
+} menu_boolean_t;
+
+/* BOOLEAN Menu flags */
+#define MENU_BOOLEAN_ONOFF         0x01
+#define MENU_BOOLEAN_01            0x02
+#define MENU_BOOLEAN_YESNO         0x03
+#define MENU_BOOLEAN_ENDIS         0x04
+#define MENU_BOOLEAN_TYPE_MASK     0x07
+
+
+#define MENU_TEXT_TYPE 2
+typedef struct menu_text_s
+{
+    OPTION_PREAMBLE
+
+    char *variable;                /* Name of the variable to getenv()/setenv() */
+    int maxchars;                  /* Max number of characters */
+    char *charset;                 /* Optional charset to use */
+    int flags;                     /* Flags - see below */
+} menu_text_t;
+
+/* TEXT entry menu flags */
+#define MENU_TEXT_NUMERIC         0x01
+#define MENU_TEXT_HEXADECIMAL     0x02
+#define MENU_TEXT_FREE            0x03
+#define MENU_TEXT_TYPE_MASK       0x07
+
+
+#define MENU_SELECTION_TYPE 3
+typedef struct menu_select_option_s
+{
+    char *map_from;               /* Map this variable contents ... */
+    char *map_to;                 /* ... to this menu text and vice versa */
+} menu_select_option_t;
+
+typedef struct menu_select_s
+{
+    OPTION_PREAMBLE
+
+    int num_options;             /* Number of mappings */
+    menu_select_option_t **options;
+				 /* Option list array */
+} menu_select_t;
+
+
+#define MENU_ROUTINE_TYPE 4
+typedef void (*menu_routine_callback)(struct menu_routine_s *);
+
+typedef struct menu_routine_s
+{
+    OPTION_PREAMBLE
+    menu_routine_callback callback;
+				 /* routine to be called */
+    void *user_data;             /* User data, don't care for system */
+} menu_routine_t;
+
+
+#define MENU_CUSTOM_TYPE 5
+typedef void (*menu_custom_draw)(struct menu_custom_s *);
+typedef void (*menu_custom_key)(struct menu_custom_s *, int);
+
+typedef struct menu_custom_s
+{
+    OPTION_PREAMBLE
+    menu_custom_draw drawfunc;
+    menu_custom_key  keyfunc;
+    void *user_data;
+} menu_custom_t;
+
+/*
+ * The menu option superstructure
+ */
+typedef struct menu_option_s
+{
+    union
+    {
+	menu_submenu_t m_sub_menu;
+	menu_boolean_t m_boolean;
+	menu_text_t    m_text;
+	menu_select_t  m_select;
+	menu_routine_t m_routine;
+    };
+} menu_option_t;
+
+/* Init the menu system. Returns <0 on error */
+int menu_init(menu_t *root);
+
+/* Execute a single menu. Returns <0 on error */
+int menu_do(menu_t *menu);
+
+#endif
diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt
new file mode 100755
index 0000000..391d49a
--- /dev/null
+++ b/board/Marvell/common/bootseq.txt
@@ -0,0 +1,94 @@
+(cpu/mpc7xxx/start.S)
+
+start:
+    b boot_cold
+
+start_warm:
+    b boot_warm
+
+
+boot_cold:
+boot_warm:
+    clear bats
+    init l2 (if enabled)
+    init altivec (if enabled)
+    invalidate l2 (if enabled)
+    setup bats (from defines in config_EVB)
+    enable_addr_trans: (if MMU enabled)
+	enable MSR_IR and MSR_DR
+    jump to in_flash
+
+in_flash:
+    enable l1 dcache
+    gal_low_init: (board/evb64260/sdram_init.S)
+	config SDRAM (CFG, TIMING, DECODE)
+	init scratch regs (810 + 814)
+
+	detect DIMM0 (bank 0 only)
+	config SDRAM_PARA0 to 256/512Mbit
+	bl sdram_op_mode
+	detect bank0 width
+	    write scratch reg 810
+	config SDRAM_PARA0 with results
+	config SDRAM_PARA1 with results
+
+	detect DIMM1 (bank 2 only)
+	config SDRAM_PARA2 to 256/512Mbit
+	detect bank2 width
+	    write scratch reg 814
+	config SDRAM_PARA2 with results
+	config SDRAM_PARA3 with results
+
+	setup device bus timings/width
+	setup boot device timings/width
+
+	setup CPU_CONF (0x0)
+	setup cpu master control register 0x160
+	setup PCI0 TIMEOUT
+	setup PCI1 TIMEOUT
+	setup PCI0 BAR
+	setup PCI1 BAR
+
+	setup MPP control 0-3
+	setup GPP level control
+	setup Serial ports multiplex
+
+    setup stack pointer (r1)
+    setup GOT
+    call cpu_init_f
+    	debug leds
+    board_init_f: (common/board.c)
+	board_early_init_f:
+	    remap gt regs?
+	    map PCI mem/io
+	    map device space
+	    clear out interupts
+	init_timebase
+	env_init
+	serial_init
+	console_init_f
+	display_options
+	initdram: (board/evb64260/evb64260.c)
+	    detect memory
+	    for each bank:
+		dram_size()
+		setup PCI slave memory mappings
+		setup SCS
+   	setup monitor
+	alloc board info struct
+	init bd struct
+	relocate_code: (cpu/mpc7xxx/start.S)
+	    copy,got,clearbss
+	    board_init_r(bd, dest_addr) (common/board.c)
+		setup bd function pointers
+		trap_init
+		flash_init: (board/evb64260/flash.c)
+		setup bd flash info
+		cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
+		    nothing
+		mem_malloc_init
+		malloc_bin_reloc
+		spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
+		env_relocated
+		misc_init_r(bd): (board/evb64260/evb64260.c)
+		    mpsc_init2
diff --git a/board/Marvell/common/ecctest.c b/board/Marvell/common/ecctest.c
new file mode 100755
index 0000000..e22b113
--- /dev/null
+++ b/board/Marvell/common/ecctest.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2001
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef ECC_TEST
+static inline void ecc_off (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
+}
+
+static inline void ecc_on (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
+}
+
+static int putshex (const char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		printf ("%02x", buf[i]);
+	}
+	return 0;
+}
+
+static int char_memcpy (void *d, const void *s, int len)
+{
+	int i;
+	char *cd = d;
+	const char *cs = s;
+
+	for (i = 0; i < len; i++) {
+		*(cd++) = *(cs++);
+	}
+	return 0;
+}
+
+static int memory_test (char *buf)
+{
+	const char src[][16] = {
+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+		{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+		 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
+		{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+		 0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
+		{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+		 0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
+		{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+		 0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
+		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+		 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
+		{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+		 0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
+		{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+		 0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
+		{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+		 0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
+		{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+		 0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
+		{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+		 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
+		{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+	};
+	const int foo[] = { 0 };
+	int i, j, a;
+
+	printf ("\ntest @ %d %p\n", foo[0], buf);
+	for (i = 0; i < 12; i++) {
+		for (a = 0; a < 8; a++) {
+			const char *s = src[i] + a;
+			int align = (unsigned) (s) & 0x7;
+
+			/* ecc_off(); */
+			memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+			/* ecc_off(); */
+			char_memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c
new file mode 100755
index 0000000..a8add85
--- /dev/null
+++ b/board/Marvell/common/flash.c
@@ -0,0 +1,1072 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * flash.c - flash support for the 512k, 8bit boot flash
+ 	and the 8MB 32bit extra flash on the DB64360
+ *           most of this file was based on the existing U-Boot
+ *           flash drivers.
+ *
+ * written or collected and sometimes rewritten by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "../include/mv_gen_reg.h"
+#include "../include/memory.h"
+#include "intel_flash.h"
+
+#define FLASH_ROM       0xFFFD	/* unknown flash type                   */
+#define FLASH_RAM       0xFFFE	/* unknown flash type                   */
+#define FLASH_MAN_UNKNOWN 0xFFFF0000
+
+/* #define DEBUG */
+
+/* Intel flash commands */
+int flash_erase_intel (flash_info_t * info, int s_first, int s_last);
+int write_word_intel (bank_addr_t addr, bank_word_t value);
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (int portwidth, vu_long * addr,
+			     flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned int i;
+	unsigned long size_b0 = 0, size_b1 = 0;
+	unsigned long base, flash_size;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* the boot flash */
+	base = CFG_FLASH_BASE;
+	size_b0 =
+		flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base,
+				&flash_info[0]);
+
+	printf ("[%ldkB@%lx] ", size_b0 / 1024, base);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20);
+	}
+
+	base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE);
+/*	base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/
+	for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) {
+		unsigned long size =
+			flash_get_size (CFG_EXTRA_FLASH_WIDTH,
+					(vu_long *) base, &flash_info[i]);
+
+		printf ("[%ldMB@%lx] ", size >> 20, base);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			if (i == 1) {
+				printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b1, size_b1 << 20);
+			}
+			break;
+		}
+		size_b1 += size;
+		base += size;
+	}
+
+	flash_size = size_b0 + size_b1;
+	return flash_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	int sector_size;
+
+	if (!info->sector_count)
+		return;
+
+	/* set up sector start address table */
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+	case FLASH_28F128J3A:
+	case FLASH_28F640J3A:
+	case FLASH_RAM:
+		/* this chip has uniformly spaced sectors */
+		sector_size = info->size / info->sector_count;
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sector_size);
+		break;
+	default:
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type    */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x00060000;
+			}
+		} else {
+			/* set sector offsets for top boot block type               */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_STM:
+		printf ("STM ");
+		break;
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A (64 Mbit)\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A (128 Mbit)\n");
+		break;
+	case FLASH_ROM:
+		printf ("ROM\n");
+		break;
+	case FLASH_RAM:
+		printf ("RAM\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if ((info->size >> 20) > 0) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+	} else {
+		printf ("  Size: %ld kB in %d Sectors\n",
+			info->size >> 10, info->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static inline void flash_cmd (int width, volatile unsigned char *addr,
+			      int offset, unsigned char cmd)
+{
+	/* supports 1x8, 1x16, and 2x16 */
+	/* 2x8 and 4x8 are not supported */
+	if (width == 4) {
+		/* assuming chips are in 16 bit mode */
+		/* 2x16 */
+		unsigned long cmd32 = (cmd << 16) | cmd;
+
+		*(volatile unsigned long *) (addr + offset * 2) = cmd32;
+	} else {
+		/* 1x16 or 1x8 */
+		*(volatile unsigned char *) (addr + offset) = cmd;
+	}
+}
+
+static ulong
+flash_get_size (int portwidth, vu_long * addr, flash_info_t * info)
+{
+	short i;
+	volatile unsigned char *caddr = (unsigned char *) addr;
+	volatile unsigned short *saddr = (unsigned short *) addr;
+	volatile unsigned long *laddr = (unsigned long *) addr;
+	char old[2], save;
+	ulong id = 0, manu = 0, base = (ulong) addr;
+
+#ifdef DEBUG
+	printf ("%s: enter\n", __FUNCTION__);
+#endif
+	info->portwidth = portwidth;
+
+	save = *caddr;
+
+	flash_cmd (portwidth, caddr, 0, 0xf0);
+	flash_cmd (portwidth, caddr, 0, 0xf0);
+
+	udelay (10);
+
+	old[0] = caddr[0];
+	old[1] = caddr[1];
+
+
+	if (old[0] != 0xf0) {
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+
+		udelay (10);
+
+		if (*caddr == 0xf0) {
+			/* this area is ROM */
+			*caddr = save;
+			info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+			info->sector_count = 8;
+			info->size = 0x80000;
+			flash_get_offsets (base, info);
+			return info->size;
+		}
+	} else {
+		*caddr = 0;
+
+		udelay (10);
+
+		if (*caddr == 0) {
+			/* this area is RAM */
+			*caddr = save;
+			info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN;
+			info->sector_count = 8;
+			info->size = 0x80000;
+			flash_get_offsets (base, info);
+			return info->size;
+		}
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+
+		udelay (10);
+	}
+
+	/* Write auto select command: read Manufacturer ID */
+	flash_cmd (portwidth, caddr, 0x555, 0xAA);
+	flash_cmd (portwidth, caddr, 0x2AA, 0x55);
+	flash_cmd (portwidth, caddr, 0x555, 0x90);
+
+	udelay (10);
+
+	if ((caddr[0] == old[0]) && (caddr[1] == old[1])) {
+
+		/* this area is ROM */
+		info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		flash_get_offsets (base, info);
+		return info->size;
+#ifdef DEBUG
+	} else {
+		printf ("%px%d: %02x:%02x -> %02x:%02x\n",
+			caddr, portwidth, old[0], old[1], caddr[0], caddr[1]);
+#endif
+	}
+
+	switch (portwidth) {
+	case 1:
+		manu = caddr[0];
+		manu |= manu << 16;
+		id = caddr[1];
+		break;
+	case 2:
+		manu = saddr[0];
+		manu |= manu << 16;
+		id = saddr[1];
+		id |= id << 16;
+		break;
+	case 4:
+		manu = laddr[0];
+		id = laddr[1];
+		break;
+	}
+
+#ifdef DEBUG
+	flash_cmd (portwidth, caddr, 0, 0xf0);
+
+	printf ("\n%08lx:%08lx:%08lx\n", base, manu, id);
+	printf ("%08lx %08lx %08lx %08lx\n",
+		laddr[0], laddr[1], laddr[2], laddr[3]);
+#endif
+
+	switch (manu) {
+	case STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+
+		printf ("Unknown Mfr [%08lx]:%08lx\n", manu, id);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (id) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		info->chipwidth = 1;
+		break;		/* => 1 MB      */
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		info->chipwidth = 1;
+		break;		/* => 1 MB      */
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		info->chipwidth = 1;
+		break;		/* => 2 MB      */
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		info->chipwidth = 1;
+		break;		/* => 2 MB      */
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		info->chipwidth = 1;
+		break;		/* => 4 MB      */
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		info->chipwidth = 1;
+		break;		/* => 4 MB      */
+#if 0				/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB      */
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB      */
+#endif
+	case AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		info->chipwidth = 1;
+		break;		/* => 512 kB    */
+
+	case INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 128 * 1024 * 64;	/* 128kbytes x 64 blocks */
+		info->chipwidth = 2;
+		if (portwidth == 4)
+			info->size *= 2;	/* 2x16 */
+		break;
+
+	case INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 128 * 1024 * 128;	/* 128kbytes x 128 blocks */
+		info->chipwidth = 2;
+		if (portwidth == 4)
+			info->size *= 2;	/* 2x16 */
+		break;
+
+	default:
+		flash_cmd (portwidth, caddr, 0, 0xf0);
+
+		printf ("Unknown id %lx:[%lx]\n", manu, id);
+		info->flash_id = FLASH_UNKNOWN;
+		info->chipwidth = 1;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets (base, info);
+
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0)=0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *) (info->start[i]);
+		saddr = (volatile unsigned short *) (info->start[i]);
+		laddr = (volatile unsigned long *) (info->start[i]);
+		if (portwidth == 1)
+			info->protect[i] = caddr[2] & 1;
+		else if (portwidth == 2)
+			info->protect[i] = saddr[2] & 1;
+		else
+			info->protect[i] = laddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (volatile unsigned char *) info->start[0];
+
+		flash_cmd (portwidth, caddr, 0, 0xF0);	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (uchar *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+/* modified to support 2x16 Intel flash */
+/* Note that the code will not exit on a flash erasure error or timeout */
+/* but will print and error message and continue processing sectors */
+/* until they are all erased. */
+/* 10-16-2002 P. Marchese */
+	ulong mask;
+	int timeout;
+
+	if (info->portwidth == 4)
+/*		{
+		printf ("- Warning: erasing of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
+		return 1;
+		}*/
+	{
+		/* make sure it's Intel flash */
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+			/* yup! it's an Intel flash */
+			/* is it 16-bits wide? */
+			if (info->chipwidth == 2) {
+				/* yup! it's 16-bits wide */
+				/* are there any sectors to process? */
+				if ((s_first < 0) || (s_first > s_last)) {
+					printf ("Error:  There are no sectors to erase\n");
+					printf ("Either sector %d is less than zero\n", s_first);
+					printf ("or sector %d is greater than sector %d\n", s_first, s_last);
+					return 1;
+				}
+				/* check for protected sectors */
+				prot = 0;
+				for (sect = s_first; sect <= s_last; ++sect)
+					if (info->protect[sect])
+						prot++;
+				/* if variable "prot" is nonzero, there are protected sectors */
+				if (prot)
+					printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+				/* reset the flash */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				/* Disable interrupts which might cause a timeout here */
+				flag = disable_interrupts ();
+				/* Clear the status register */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_CLR_STAT);
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				/* Start erase on unprotected sectors */
+				for (sect = s_first; sect <= s_last; sect++) {
+					/* is the sector unprotected? */
+					if (info->protect[sect] == 0) {	/* not protected */
+						/* issue the single block erase command, 0x20 */
+						flash_cmd (info->portwidth,
+							   (volatile unsigned
+							    char *) info->
+							   start[sect], 0,
+							   CHIP_CMD_ERASE1);
+						/* issue the erase confirm command, 0xD0 */
+						flash_cmd (info->portwidth,
+							   (volatile unsigned
+							    char *) info->
+							   start[sect], 0,
+							   CHIP_CMD_ERASE2);
+						l_sect = sect;
+						/* re-enable interrupts if necessary */
+						if (flag)
+							enable_interrupts ();
+						/* poll for erasure completion */
+						/* put flash into read status mode by writing 0x70 to it */
+						flash_cmd (info->portwidth,
+							   addr, 0,
+							   CHIP_CMD_RD_STAT);
+						/* setup the status register mask */
+						mask = CHIP_STAT_RDY |
+							(CHIP_STAT_RDY << 16);
+						/* init. the timeout counter */
+						start = get_timer (0);
+						/* keep looping while the flash is not ready */
+						/* exit the loop by timing out or the flash */
+						/* becomes ready again */
+						timeout = 0;
+						while ((*
+							(volatile unsigned
+							 long *) info->
+							start[sect] & mask) !=
+						       mask) {
+							/* has the timeout limit been reached? */
+							if (get_timer (start)
+							    >
+							    CFG_FLASH_ERASE_TOUT)
+							{
+								/* timeout limit reached */
+								printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]);
+								printf ("Continuing with next sector\n");
+								timeout = 1;
+								goto timed_out_error;
+							}
+							/* put flash into read status mode by writing 0x70 to it */
+							flash_cmd (info->
+								   portwidth,
+								   addr, 0,
+								   CHIP_CMD_RD_STAT);
+						}
+						/* did we timeout? */
+					      timed_out_error:if (timeout == 0)
+						{
+							/* didn't timeout, so check the status register */
+							/* create the status mask to check for errors */
+							mask = CHIP_STAT_ECLBS;
+							mask = mask | (mask <<
+								       16);
+							/* put flash into read status mode by writing 0x70 to it */
+							flash_cmd (info->
+								   portwidth,
+								   addr, 0,
+								   CHIP_CMD_RD_STAT);
+							/* are there any errors? */
+							if ((*
+							     (volatile
+							      unsigned long *)
+							     info->
+							     start[sect] &
+							     mask) != 0) {
+								/* We got an erasure error */
+								printf ("Flash erasure error at address 0x%08lx\n", info->start[sect]);
+								printf ("Continuing with next sector\n");
+								/* reset the flash */
+								flash_cmd
+									(info->
+									 portwidth,
+									 addr,
+									 0,
+									 CHIP_CMD_RST);
+							}
+						}
+						/* erasure completed without errors */
+						/* reset the flash */
+						flash_cmd (info->portwidth,
+							   addr, 0,
+							   CHIP_CMD_RST);
+					}	/* end if not protected */
+				}	/* end for loop */
+				printf ("Flash erasure done\n");
+				return 0;
+			} else {
+				/* The Intel flash is not 16-bit wide */
+				/* print and error message and return */
+				/* NOTE: you can add routines here to handle other size flash */
+				printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8);
+				printf ("The erasure code only handles Intel 16-bit wide flash memory\n");
+				return 1;
+			}
+		} else {
+			/* Not Intel flash so return an error as a write timeout */
+			/* NOTE: if it's another type flash, stick its routine here */
+			printf ("Error: The flash device is not Intel type\n");
+			printf ("The erasure code only supports Intel flash in a 32-bit port width\n");
+			return 1;
+		}
+	}
+
+	/* end 32-bit wide flash code */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
+		return 1;	/* Rom can not be erased */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {	/* RAM just copy 0s to RAM */
+		for (sect = s_first; sect <= s_last; sect++) {
+			int sector_size = info->size / info->sector_count;
+
+			addr = (uchar *) (info->start[sect]);
+			memset ((void *) addr, 0, sector_size);
+		}
+		return 0;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {	/* Intel works spezial */
+		return flash_erase_intel (info,
+					  (unsigned short) s_first,
+					  (unsigned short) s_last);
+	}
+#if 0
+	if ((info->flash_id == FLASH_UNKNOWN) ||	/* Flash is unknown to PPCBoot */
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+#endif
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	flash_cmd (info->portwidth, addr, 0x555, 0xAA);	/* start erase routine */
+	flash_cmd (info->portwidth, addr, 0x2AA, 0x55);
+	flash_cmd (info->portwidth, addr, 0x555, 0x80);
+	flash_cmd (info->portwidth, addr, 0x555, 0xAA);
+	flash_cmd (info->portwidth, addr, 0x2AA, 0x55);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (uchar *) (info->start[sect]);
+			flash_cmd (info->portwidth, addr, 0, 0x30);
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (volatile unsigned char *) (info->start[l_sect]);
+	/* broken for 2x16: TODO */
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *) info->start[0];
+	flash_cmd (info->portwidth, addr, 0, 0xf0);
+	flash_cmd (info->portwidth, addr, 0, 0xf0);
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+/* broken for 2x16: TODO */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+/* Commented out since the below code should work for 32-bit(2x 16 flash) */
+/* 10-16-2002 P. Marchese */
+/*	if(info->portwidth==4) return 1; */
+/*	if(info->portwidth==4) {
+		printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
+		return 1;
+		}*/
+
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
+		return 0;
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+		memcpy ((void *) addr, src, cnt);
+		return 0;
+	}
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+/* broken for 2x16: TODO */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (uchar *) (info->start[0]);
+	ulong start;
+	int flag, i;
+	ulong mask;
+
+/* modified so that it handles 32-bit(2x16 Intel flash programming */
+/* 10-16-2002 P. Marchese */
+
+	if (info->portwidth == 4)
+/*		{
+		printf ("- Warning: writting of 32Bit (2*16Bit i.e. 2*28F640J3A) not supported yet !!!! \n");
+		return 1;
+		}*/
+	{
+		/* make sure it's Intel flash */
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+			/* yup! it's an Intel flash */
+			/* is it 16-bits wide? */
+			if (info->chipwidth == 2) {
+				/* yup! it's 16-bits wide */
+				/* so we know how to program it */
+				/* reset the flash */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				/* Disable interrupts which might cause a timeout here */
+				flag = disable_interrupts ();
+				/* Clear the status register */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_CLR_STAT);
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				/* 1st cycle of word/byte program */
+				/* write 0x40 to the location to program */
+				flash_cmd (info->portwidth, (uchar *) dest, 0,
+					   CHIP_CMD_PROG);
+				/* 2nd cycle of word/byte program */
+				/* write the data to the destination address */
+				*(ulong *) dest = data;
+				/* re-enable interrupts if necessary */
+				if (flag)
+					enable_interrupts ();
+				/* setup the status register mask */
+				mask = CHIP_STAT_RDY | (CHIP_STAT_RDY << 16);
+				/* put flash into read status mode by writing 0x70 to it */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RD_STAT);
+				/* init. the timeout counter */
+				start = get_timer (0);
+				/* keep looping while the flash is not ready */
+				/* exit the loop by timing out or the flash */
+				/* becomes ready again */
+/* 11-13-2002 Paul Marchese */
+/* modified while loop conditional statement */
+/* because we were always timing out.  */
+/* there is a type mismatch, "addr[0]" */
+/* returns a byte but "mask" is a 32-bit value */
+				while ((*(volatile unsigned long *) info->
+					start[0] & mask) != mask)
+/* original code */
+/* while (addr[0] & mask) != mask) */
+				{
+					/* has the timeout limit been reached? */
+					if (get_timer (start) >
+					    CFG_FLASH_WRITE_TOUT) {
+						/* timeout limit reached */
+						printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data);
+						/* reset the flash */
+						flash_cmd (info->portwidth,
+							   addr, 0,
+							   CHIP_CMD_RST);
+						return (1);
+					}
+					/* put flash into read status mode by writing 0x70 to it */
+					flash_cmd (info->portwidth, addr, 0,
+						   CHIP_CMD_RD_STAT);
+				}
+				/* flash is ready, so check the status */
+				/* create the status mask to check for errors */
+				mask = CHIP_STAT_DPS | CHIP_STAT_VPPS |
+					CHIP_STAT_PSLBS;
+				mask = mask | (mask << 16);
+				/* put flash into read status mode by writing 0x70 to it */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RD_STAT);
+				/* are there any errors? */
+				if ((addr[0] & mask) != 0) {
+					/* We got a one of the following errors: */
+					/* Voltage range, Device protect, or programming */
+					/* return the error as a device timeout */
+					/* put flash into read status mode by writing 0x70 to it */
+					flash_cmd (info->portwidth, addr, 0,
+						   CHIP_CMD_RD_STAT);
+					printf ("Flash programming error at address 0x%08lx\n", dest);
+					printf ("Flash status register contains 0x%08lx\n", (unsigned long) addr[0]);
+					/* reset the flash */
+					flash_cmd (info->portwidth, addr, 0,
+						   CHIP_CMD_RST);
+					return 1;
+				}
+				/* write completed without errors */
+				/* reset the flash */
+				flash_cmd (info->portwidth, addr, 0,
+					   CHIP_CMD_RST);
+				return 0;
+			} else {
+				/* it's not 16-bits wide, so return an error as a write timeout */
+				/* NOTE: you can add routines here to handle other size flash */
+				printf ("Error: Intel flash device is only %d-bits wide\n", info->chipwidth * 8);
+				printf ("The write code only handles Intel 16-bit wide flash memory\n");
+				return 1;
+			}
+		} else {
+			/* not Intel flash so return an error as a write timeout */
+			/* NOTE: if it's another type flash, stick its routine here */
+			printf ("Error: The flash device is not Intel type\n");
+			printf ("The code only supports Intel flash in a 32-bit port width\n");
+			return 1;
+		}
+	}
+
+	/* end of 32-bit flash code */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM)
+		return 1;
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+		*(unsigned long *) dest = data;
+		return 0;
+	}
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		unsigned short low = data & 0xffff;
+		unsigned short hi = (data >> 16) & 0xffff;
+		int ret = write_word_intel ((bank_addr_t) dest, hi);
+
+		if (!ret)
+			ret = write_word_intel ((bank_addr_t) (dest + 2),
+						low);
+
+		return ret;
+	}
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* first, perform an unlock bypass command to speed up flash writes */
+	addr[0x555] = 0xAA;
+	addr[0x2AA] = 0x55;
+	addr[0x555] = 0x20;
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *) &data;
+
+		addr[0] = 0xA0;
+		*(((char *) dest) + i) = data_ch[i];
+		udelay (10);	/* XXX */
+	}
+
+	/* we're done, now do an unlock bypass reset */
+	addr[0] = 0x90;
+	addr[0] = 0x00;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c
new file mode 100755
index 0000000..32b2b30
--- /dev/null
+++ b/board/Marvell/common/i2c.c
@@ -0,0 +1,532 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ * extra improvments by Brain Waite
+ */
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include "../include/mv_gen_reg.h"
+#include "../include/core.h"
+
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000	/* Should be at least the # of MHz of Tclk */
+#undef	DEBUG_I2C
+/*#define DEBUG_I2C*/
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+static void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+/* gtI2cMasterInit */
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 2 << n;	/* power = 2^(n+1) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+/* gtI2cReset */
+	GT_REG_WRITE (I2C_SOFT_RESET, 0);
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	DP (puts ("set baudrate\n"));
+
+	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+
+	udelay (I2C_DELAY * 10);
+
+	DP (puts ("read control, baudrate\n"));
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	GT_REG_READ (I2C_CONTROL, &control);
+}
+
+static uchar i2c_start (void)
+{				/* DB64360 checked -> ok */
+	unsigned int control, status;
+	int count = 0;
+
+	DP (puts ("i2c_start\n"));
+
+	/* Set the start bit */
+
+/* gtI2cGenerateStartBit() */
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
+	GT_REG_WRITE (I2C_CONTROL, control);
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+
+	count = 0;
+	while ((status & 0xff) != 0x08) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	GT_REG_WRITE (I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS (I2C_CONTROL, BIT3);
+
+	udelay (I2C_DELAY);
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	count = 0;
+	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+		udelay (I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+
+		udelay (I2C_DELAY * 5);
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x50) {
+			udelay (I2C_DELAY);
+			if (count > 2) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				return 0;
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		GT_REG_READ (I2C_DATA, &data);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+	}
+	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
+	while ((status & 0xff) != 0x58) {
+		udelay (I2C_DELAY);
+		if (count > 200) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
+
+	return (0);
+}
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		temp = (unsigned int) (*temp_ptr);
+		GT_REG_WRITE (I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+
+		udelay (I2C_DELAY);
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* 11-14-2002 Paul Marchese */
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+	/* set the interrupt bit in the control register */
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
+	udelay (I2C_DELAY * 10);
+	return (0);
+}
+
+/* 11-14-2002 Paul Marchese */
+/* created this function to get the i2c_write() */
+/* function working properly. */
+/* function to write bytes out on the i2c bus */
+/* this is identical to the function i2c_write_data() */
+/* except that it requires a buffer that is an */
+/* unsigned character array.  You can't use */
+/* i2c_write_data() to send an array of unsigned characters */
+/* since the byte of interest ends up on the wrong end of the bus */
+/* aah, the joys of big endian versus little endian! */
+/* */
+/* returns 0 = success */
+/*         anything other than zero is failure */
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count = 0;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		GT_REG_WRITE (I2C_DATA, temp);
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+
+		udelay (I2C_DELAY);
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			udelay (I2C_DELAY);
+			if (count > 20) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+/* Can't have the write issuing a stop command */
+/* it's wrong to have a stop bit in read stream or write stream */
+/* since we don't know if it's really the end of the command */
+/* or whether we have just send the device address + offset */
+/* we will push issuing the stop command off to the original */
+/* calling function */
+/*	GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); */
+	/* set the interrupt bit in the control register */
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 3));
+	udelay (I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+/* initialize the table of address offset bytes */
+/* utilized for 2 byte address offsets */
+/* NOTE: the order is high byte first! */
+	table[1] = offset & 0xff;	/* low byte */
+	table[0] = offset / 0x100;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency again */
+
+	status = i2c_start ();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);	/* send the slave address */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+/* 11-14-2002 Paul Marchese */
+/* Function to set the I2C stop bit */
+void i2c_stop (void)
+{
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
+}
+
+/* 11-14-2002 Paul Marchese */
+/* I2C write function */
+/* dev_addr = device address */
+/* offset = address offset */
+/* alen = length in bytes of the address offset */
+/* data = pointer to buffer to read data into */
+/* len = # of bytes to read */
+/* */
+/* returns 0 = succesful */
+/*         anything but zero is failure */
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+	}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+/* 11-14-2002 Paul Marchese */
+/* function to determine if an I2C device is present */
+/* chip = device address of chip to check for */
+/* */
+/* returns 0 = sucessful, the device exists */
+/*         anything other than zero is failure, no device */
+int i2c_probe (uchar chip)
+{
+
+	/* We are just looking for an <ACK> back. */
+	/* To see if the device/chip is there */
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_start ();	/* send a start bit */
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Transaction start failed: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
diff --git a/board/Marvell/common/i2c.h b/board/Marvell/common/i2c.h
new file mode 100755
index 0000000..b669ff0
--- /dev/null
+++ b/board/Marvell/common/i2c.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ */
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c
new file mode 100755
index 0000000..d26f883
--- /dev/null
+++ b/board/Marvell/common/intel_flash.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "../include/mv_gen_reg.h"
+#include "../include/memory.h"
+#include "intel_flash.h"
+
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+static void bank_reset (flash_info_t * info, int sect)
+{
+	bank_addr_t addrw, eaddrw;
+
+	addrw = (bank_addr_t) info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD (addrw);
+
+	while (addrw < eaddrw) {
+#ifdef FLASH_DEBUG
+		printf ("  writing reset cmd to addr 0x%08lx\n",
+			(unsigned long) addrw);
+#endif
+		*addrw = BANK_CMD_RST;
+		addrw++;
+	}
+}
+
+static void bank_erase_init (flash_info_t * info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int flag;
+
+#ifdef FLASH_DEBUG
+	printf ("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
+	printf ("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
+	printf ("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
+	printf ("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
+	printf ("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
+	printf ("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
+	printf ("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
+#endif
+
+	saddrw = (bank_addr_t) info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
+
+#ifdef FLASH_DEBUG
+	printf ("erasing sector %d, start addr = 0x%08lx "
+		"(bank next word addr = 0x%08lx)\n", sect,
+		(unsigned long) saddrw, (unsigned long) eaddrw);
+#endif
+
+	/* Disable intrs which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+#ifdef FLASH_DEBUG
+		printf ("  writing erase cmd to addr 0x%08lx\n",
+			(unsigned long) addrw);
+#endif
+		*addrw = BANK_CMD_ERASE1;
+		*addrw = BANK_CMD_ERASE2;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+}
+
+static int bank_erase_poll (flash_info_t * info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int sectdone, haderr;
+
+	saddrw = (bank_addr_t) info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD (saddrw);
+
+	sectdone = 1;
+	haderr = 0;
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+		bank_word_t stat = *addrw;
+
+#ifdef FLASH_DEBUG
+		printf ("  checking status at addr "
+			"0x%08x [0x%08x]\n", (unsigned long) addrw, stat);
+#endif
+		if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
+			sectdone = 0;
+		else if ((stat & BANK_STAT_ERR) != 0) {
+			printf (" failed on sector %d "
+				"(stat = 0x%08x) at "
+				"address 0x%p\n", sect, stat, addrw);
+			*addrw = BANK_CMD_CLR_STAT;
+			haderr = 1;
+		}
+	}
+
+	if (haderr)
+		return (-1);
+	else
+		return (sectdone);
+}
+
+int write_word_intel (bank_addr_t addr, bank_word_t value)
+{
+	bank_word_t stat;
+	ulong start;
+	int flag, retval;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = BANK_CMD_PROG;
+
+	*addr = value;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	retval = 0;
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	do {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			retval = 1;
+			goto done;
+		}
+		stat = *addr;
+	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
+
+	if ((stat & BANK_STAT_ERR) != 0) {
+		printf ("flash program failed (stat = 0x%08lx) "
+			"at address 0x%08lx\n", (ulong) stat, (ulong) addr);
+		*addr = BANK_CMD_CLR_STAT;
+		retval = 3;
+	}
+
+      done:
+	/* reset to read mode */
+	*addr = BANK_CMD_RST;
+
+	return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase_intel (flash_info_t * info, int s_first, int s_last)
+{
+	int prot, sect, haderr;
+	ulong start, now, last;
+
+#ifdef FLASH_DEBUG
+	printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+		(info - flash_info) + 1);
+	flash_print_info (info);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sector%s will not be erased!\n", prot, (prot > 1 ? "s" : ""));
+	}
+
+	start = get_timer (0);
+	last = 0;
+	haderr = 0;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			ulong estart;
+			int sectdone;
+
+			bank_erase_init (info, sect);
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			estart = get_timer (start);
+
+			do {
+				now = get_timer (start);
+
+				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout (sect %d)\n", sect);
+					haderr = 1;
+					break;
+				}
+#ifndef FLASH_DEBUG
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+#endif
+
+				sectdone = bank_erase_poll (info, sect);
+
+				if (sectdone < 0) {
+					haderr = 1;
+					break;
+				}
+
+			} while (!sectdone);
+
+			if (haderr)
+				break;
+		}
+	}
+
+	if (haderr > 0)
+		printf (" failed\n");
+	else
+		printf (" done\n");
+
+	/* reset to read mode */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			bank_reset (info, sect);
+		}
+	}
+	return haderr;
+}
diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h
new file mode 100755
index 0000000..666a4cd
--- /dev/null
+++ b/board/Marvell/common/intel_flash.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ */
+
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/*
+ * acceptable chips types are:
+ *
+ *	28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
+ */
+
+/* register addresses, valid only following an CHIP_CMD_RD_ID command */
+#define CHIP_ADDR_REG_MAN	0x000000	/* manufacturer's id */
+#define CHIP_ADDR_REG_DEV	0x000001	/* device id */
+#define CHIP_ADDR_REG_CFGM	0x000003	/* master lock config */
+#define CHIP_ADDR_REG_CFG(b)	(((b)<<16)|2)	/* lock config for block b */
+
+/* Commands */
+#define CHIP_CMD_RST		0xFF		/* reset flash */
+#define CHIP_CMD_RD_ID		0x90		/* read the id and lock bits */
+#define CHIP_CMD_RD_QUERY	0x98		/* read device capabilities */
+#define CHIP_CMD_RD_STAT	0x70		/* read the status register */
+#define CHIP_CMD_CLR_STAT	0x50		/* clear the staus register */
+#define CHIP_CMD_WR_BUF		0xE8		/* clear the staus register */
+#define CHIP_CMD_PROG		0x40		/* program word command */
+#define CHIP_CMD_ERASE1		0x20		/* 1st word for block erase */
+#define CHIP_CMD_ERASE2		0xD0		/* 2nd word for block erase */
+#define CHIP_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
+#define CHIP_CMD_LOCK		0x60		/* 1st word for all lock cmds */
+#define CHIP_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
+#define CHIP_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
+#define CHIP_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define CHIP_STAT_DPS		0x02		/* Device Protect Status */
+#define CHIP_STAT_VPPS		0x08		/* VPP Status */
+#define CHIP_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
+#define CHIP_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
+#define CHIP_STAT_ESS		0x40		/* Erase Suspend Status */
+#define CHIP_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
+
+#define CHIP_STAT_ERR		(CHIP_STAT_VPPS | CHIP_STAT_DPS | \
+				    CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
+#define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
+#define CHIP_RD_ID_DEV		CFG_FLASH_ID
+
+/* dimensions */
+#define CHIP_WIDTH		2		/* chips are in 16 bit mode */
+#define CHIP_WSHIFT		1		/* (log2 of CHIP_WIDTH) */
+#define CHIP_NBLOCKS		128
+#define CHIP_BLKSZ		(128 * 1024)	/* of 128Kbytes each */
+#define CHIP_SIZE		(CHIP_BLKSZ * CHIP_NBLOCKS)
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * The hymod board has 2 x 28F320J5 chips running in
+ * 16 bit mode, for a 32 bit wide bank.
+ */
+
+typedef unsigned short bank_word_t;		/* 8/16/32/64bit unsigned int */
+typedef volatile bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t;		/* want this big - >= 32 bit */
+
+#define BANK_CHIP_WIDTH		1		/* each bank is 1 chip wide */
+#define BANK_CHIP_WSHIFT	0		/* (log2 of BANK_CHIP_WIDTH) */
+
+#define BANK_WIDTH		(CHIP_WIDTH * BANK_CHIP_WIDTH)
+#define BANK_WSHIFT		(CHIP_WSHIFT + BANK_CHIP_WSHIFT)
+#define BANK_NBLOCKS		CHIP_NBLOCKS
+#define BANK_BLKSZ		(CHIP_BLKSZ * BANK_CHIP_WIDTH)
+#define BANK_SIZE		(CHIP_SIZE * BANK_CHIP_WIDTH)
+
+#define MAX_BANKS		1		/* only one bank possible */
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_WIDTH - 1)))
+#define BANK_SIZE_WORD_ALIGN(s)	((bank_size_t)BANK_ADDR_WORD_ALIGN( \
+				    (bank_size_t)(s) + (BANK_WIDTH - 1)))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_BLKSZ - 1)))
+#define BANK_SIZE_BLK_ALIGN(s)	((bank_size_t)BANK_ADDR_BLK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_BLKSZ - 1)))
+
+/* align bank addresses and sizes to bank boundaries */
+#define BANK_ADDR_BANK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_SIZE - 1)))
+#define BANK_SIZE_BANK_ALIGN(s)	((bank_size_t)BANK_ADDR_BANK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_SIZE - 1)))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o)	(bank_addr_t)((bank_size_t)(a) + \
+				    (bank_size_t)(o))
+
+/* get base address of bank b, given flash base address a */
+#define BANK_ADDR_BASE(a, b)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    (bank_size_t)(b) * BANK_SIZE)
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+				    BANK_WIDTH)
+#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+				    BANK_BLKSZ)
+#define BANK_ADDR_NEXT_BANK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    BANK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define BANK_ADDR_REG(a, r)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    ((bank_size_t)(r) << BANK_WSHIFT))
+
+/* make a bank address for each chip register address */
+
+#define BANK_ADDR_REG_MAN(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
+#define BANK_ADDR_REG_DEV(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
+#define BANK_ADDR_REG_CFGM(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
+#define BANK_ADDR_REG_CFG(b,a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the bank_word_t type, and take into account the
+ * chip width and bank layout
+ */
+
+#define BANK_FILL_WORD(o)	((bank_word_t)(o))
+
+/* make a bank word value for each chip cmd/stat/rd value */
+
+/* Commands */
+#define BANK_CMD_RST		BANK_FILL_WORD(CHIP_CMD_RST)
+#define BANK_CMD_RD_ID		BANK_FILL_WORD(CHIP_CMD_RD_ID)
+#define BANK_CMD_RD_STAT	BANK_FILL_WORD(CHIP_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1		BANK_FILL_WORD(CHIP_CMD_ERASE1)
+#define BANK_CMD_ERASE2		BANK_FILL_WORD(CHIP_CMD_ERASE2)
+#define BANK_CMD_PROG		BANK_FILL_WORD(CHIP_CMD_PROG)
+#define BANK_CMD_LOCK		BANK_FILL_WORD(CHIP_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS		BANK_FILL_WORD(CHIP_STAT_DPS)
+#define BANK_STAT_PSS		BANK_FILL_WORD(CHIP_STAT_PSS)
+#define BANK_STAT_VPPS		BANK_FILL_WORD(CHIP_STAT_VPPS)
+#define BANK_STAT_PSLBS		BANK_FILL_WORD(CHIP_STAT_PSLBS)
+#define BANK_STAT_ECLBS		BANK_FILL_WORD(CHIP_STAT_ECLBS)
+#define BANK_STAT_ESS		BANK_FILL_WORD(CHIP_STAT_ESS)
+#define BANK_STAT_RDY		BANK_FILL_WORD(CHIP_STAT_RDY)
+
+#define BANK_STAT_ERR		BANK_FILL_WORD(CHIP_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define BANK_RD_ID_LOCK		BANK_FILL_WORD(CHIP_RD_ID_LOCK)
+#define BANK_RD_ID_MAN		BANK_FILL_WORD(CHIP_RD_ID_MAN)
+#define BANK_RD_ID_DEV		BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c
new file mode 100755
index 0000000..45353af
--- /dev/null
+++ b/board/Marvell/common/memory.c
@@ -0,0 +1,1390 @@
+/*
+ * Copyright - Galileo technology.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * written or collected and sometimes rewritten by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ */
+
+
+#include <common.h>
+#include "../include/core.h"
+#include "../include/memory.h"
+
+/*******************************************************************************
+* memoryGetBankBaseAddress - Returns the base address of a memory bank.
+* DESCRIPTION:
+*       This function returns the base address of one of the SDRAM’s memory
+*       banks. There are 4 memory banks and each one represents one DIMM side.
+* INPUT:
+*       MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit Memory bank base address.
+*******************************************************************************/
+static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
+{
+	switch (bank) {
+	case BANK0:
+		return SCS_0_LOW_DECODE_ADDRESS;
+	case BANK1:
+		return SCS_1_LOW_DECODE_ADDRESS;
+	case BANK2:
+		return SCS_2_LOW_DECODE_ADDRESS;
+	case BANK3:
+		return SCS_3_LOW_DECODE_ADDRESS;
+
+	}
+	return SCS_0_LOW_DECODE_ADDRESS;	/* default value */
+}
+
+unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
+{
+	unsigned int base;
+	unsigned int regOffset = memoryGetBankRegOffset (bank);
+
+	GT_REG_READ (regOffset, &base);
+	base = base << 16;	/* MV6436x */
+	return base;
+}
+
+/*******************************************************************************
+* memoryGetDeviceBaseAddress - Returns the base address of a device.
+* DESCRIPTION:
+*       This function returns the base address of a device on the system. There
+*       are 5 possible devices (0 - 4 and one boot device) as defined in
+*       gtMemory.h. Each of the device parameters is maped to one of the CS
+*       (Devices chip selects) base address register.
+* INPUT:
+*       device - Selects one of the five devices as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit Device base address.
+*
+*******************************************************************************/
+static unsigned int memoryGetDeviceRegOffset (DEVICE device)
+{
+	switch (device) {
+	case DEVICE0:
+		return CS_0_LOW_DECODE_ADDRESS;
+	case DEVICE1:
+		return CS_1_LOW_DECODE_ADDRESS;
+	case DEVICE2:
+		return CS_2_LOW_DECODE_ADDRESS;
+	case DEVICE3:
+		return CS_3_LOW_DECODE_ADDRESS;
+	case BOOT_DEVICE:
+		return BOOTCS_LOW_DECODE_ADDRESS;
+	}
+	return CS_0_LOW_DECODE_ADDRESS;	/* default value */
+}
+
+unsigned int memoryGetDeviceBaseAddress (DEVICE device)
+{
+	unsigned int regBase;
+	unsigned int regOffset = memoryGetDeviceRegOffset (device);
+
+	GT_REG_READ (regOffset, &regBase);
+
+	regBase = regBase << 16;	/* MV6436x */
+	return regBase;
+}
+
+/*******************************************************************************
+* MemoryGetPciBaseAddr - Returns the base address of a PCI window.
+* DESCRIPTION:
+*       This function returns the base address of a PCI window. There are 5
+*       possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
+*       interface as defined in gtMemory.h, used by the CPU's address decoding
+*       mechanism.
+*	New in MV6436x
+* INPUT:
+*       pciWindow - Selects one of the PCI windows as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit PCI window base address.
+*******************************************************************************/
+unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
+{
+	unsigned int baseAddrReg, base;
+
+	switch (pciWindow) {
+	case PCI_0_IO:
+		baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS;	/*PCI_0_IO_BASE_ADDR;  */
+		break;
+	case PCI_0_MEM0:
+		baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY0_BASE_ADDR; */
+		break;
+	case PCI_0_MEM1:
+		baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY1_BASE_ADDR; */
+		break;
+	case PCI_0_MEM2:
+		baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY2_BASE_ADDR;  */
+		break;
+	case PCI_0_MEM3:
+		baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY3_BASE_ADDR;  */
+		break;
+#ifdef INCLUDE_PCI_1
+	case PCI_1_IO:
+		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_1_IO_BASE_ADDR;  */
+		break;
+	case PCI_1_MEM0:
+		baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY0_BASE_ADDR; */
+		break;
+	case PCI_1_MEM1:
+		baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY1_BASE_ADDR;  */
+		break;
+	case PCI_1_MEM2:
+		baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY2_BASE_ADDR;  */
+		break;
+	case PCI_1_MEM3:
+		baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY3_BASE_ADDR; */
+		break;
+#endif /* INCLUDE_PCI_1 */
+	default:
+		return 0xffffffff;
+	}
+	GT_REG_READ (baseAddrReg, &base);
+	return (base << 16);
+}
+
+/*******************************************************************************
+* memoryGetBankSize - Returns the size of a memory bank.
+* DESCRIPTION:
+*       This function returns the size of memory bank as described in
+*       'gtMemoryGetBankBaseAddress' function.
+* INPUT:
+*       bank - Selects one of the four banks as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit size memory bank size or 0 for a closed or non populated bank.
+*
+*******************************************************************************/
+unsigned int memoryGetBankSize (MEMORY_BANK bank)
+{
+	unsigned int sizeReg, size;
+	MEMORY_WINDOW window;
+
+	switch (bank) {
+	case BANK0:
+		sizeReg = SCS_0_HIGH_DECODE_ADDRESS;	/* CS_0_SIZE; */
+		window = CS_0_WINDOW;
+		break;
+	case BANK1:
+		sizeReg = SCS_1_HIGH_DECODE_ADDRESS;	/* CS_1_SIZE; */
+		window = CS_1_WINDOW;
+		break;
+	case BANK2:
+		sizeReg = SCS_2_HIGH_DECODE_ADDRESS;	/* CS_2_SIZE; */
+		window = CS_2_WINDOW;
+		break;
+	case BANK3:
+		sizeReg = SCS_3_HIGH_DECODE_ADDRESS;	/* CS_3_SIZE; */
+		window = CS_3_WINDOW;
+		break;
+	default:
+		return 0;
+		break;
+	}
+	/* If the window is closed, a size of 0 is returned */
+	if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
+		return 0;
+	GT_REG_READ (sizeReg, &size);
+	size = ((size << 16) | 0xffff) + 1;
+	return size;
+}
+
+/*******************************************************************************
+* memoryGetDeviceSize - Returns the size of a device memory space.
+* DESCRIPTION:
+*       This function returns the memory space size of a given device.
+* INPUT:
+*       device - Selects one of the five devices as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit size of a device memory space.
+*******************************************************************************/
+unsigned int memoryGetDeviceSize (DEVICE device)
+{
+	unsigned int sizeReg, size;
+	MEMORY_WINDOW window;
+
+	switch (device) {
+	case DEVICE0:
+		sizeReg = CS_0_HIGH_DECODE_ADDRESS;	/*DEV_CS0_SIZE; */
+		window = DEVCS_0_WINDOW;
+		break;
+	case DEVICE1:
+		sizeReg = CS_1_HIGH_DECODE_ADDRESS;	/*DEV_CS1_SIZE; */
+		window = DEVCS_1_WINDOW;
+		break;
+	case DEVICE2:
+		sizeReg = CS_2_HIGH_DECODE_ADDRESS;	/*DEV_CS2_SIZE; */
+		window = DEVCS_2_WINDOW;
+		break;
+	case DEVICE3:
+		sizeReg = CS_3_HIGH_DECODE_ADDRESS;	/*DEV_CS3_SIZE; */
+		window = DEVCS_3_WINDOW;
+		break;
+	case BOOT_DEVICE:
+		sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;	/*BOOTCS_SIZE; */
+		window = BOOT_CS_WINDOW;
+		break;
+	default:
+		return 0;
+		break;
+	}
+	/* If the window is closed, a size of 0 is returned */
+	if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
+		return 0;
+	GT_REG_READ (sizeReg, &size);
+	size = ((size << 16) | 0xffff) + 1;
+	return size;
+}
+
+/*******************************************************************************
+* MemoryGetPciWindowSize - Returns the size of a PCI memory window.
+* DESCRIPTION:
+*       This function returns the size of a PCI window.
+* INPUT:
+*       pciWindow - Selects one of the PCI memory windows as defined in
+*       Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit size of a PCI memory window.
+*******************************************************************************/
+unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
+{
+	unsigned int sizeReg, size;
+
+	switch (pciWindow) {
+	case PCI_0_IO:
+		sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS;	/*PCI_0_IO_SIZE; */
+		break;
+	case PCI_0_MEM0:
+		sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY0_SIZE; */
+		break;
+	case PCI_0_MEM1:
+		sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY1_SIZE; */
+		break;
+	case PCI_0_MEM2:
+		sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY2_SIZE; */
+		break;
+	case PCI_0_MEM3:
+		sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY3_SIZE; */
+		break;
+#ifdef INCLUDE_PCI_1
+	case PCI_1_IO:
+		sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS;	/*PCI_1_IO_SIZE; */
+		break;
+	case PCI_1_MEM0:
+		sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY0_SIZE; */
+		break;
+	case PCI_1_MEM1:
+		sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY1_SIZE;  */
+		break;
+	case PCI_1_MEM2:
+		sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY2_SIZE;  */
+		break;
+	case PCI_1_MEM3:
+		sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY3_SIZE; */
+		break;
+#endif /* INCLUDE_PCI_1 */
+	default:
+		return 0x0;
+	}
+	/* If the memory window is disabled, retrun size = 0 */
+	if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
+	    == MEM_WINDOW_DISABLED)
+		return 0;
+	GT_REG_READ (sizeReg, &size);
+	size = ((size << 16) | 0xffff) + 1;
+	return size;
+}
+
+/*******************************************************************************
+* memoryGetDeviceWidth - Returns the width of a given device.
+* DESCRIPTION:
+*       The MV's device interface supports up to 32 Bit wide devices. A device
+*       can have a  1, 2, 4 or 8 Bytes data width. This function returns the
+*       width of a device as defined by the user or the operating system.
+* INPUT:
+*       device - Selects one of the five devices as defined in Memory.h.
+* OUTPUT:
+*       None.
+* RETURN:
+*       Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
+*******************************************************************************/
+unsigned int memoryGetDeviceWidth (DEVICE device)
+{
+	unsigned int width;
+	unsigned int regValue;
+
+	GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, &regValue);
+	width = (regValue & (BIT20 | BIT21)) >> 20;
+	return (BIT0 << width);
+}
+
+/*******************************************************************************
+* memoryMapBank - Set new base address and size for one of the memory
+*                         banks.
+*
+* DESCRIPTION:
+*       The CPU interface address decoding map consists of 21 address windows
+*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
+*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
+*       space. Each address window is defined by two registers - base and size.
+*       The CPU address is compared with the values in the various CPU windows
+*       until a match is found and the address is than targeted to that window.
+*       This function sets new base and size for one the memory banks
+*       (CS0 - CS3). It is the programmer`s responsibility to make sure that
+*       there are no conflicts with other memory spaces. When two memory spaces
+*       overlap, the MV’s behavior is not defined .If a bank needs to be closed,
+*       set the ’bankLength’ parameter size to 0x0.
+*
+* INPUT:
+*       bank      - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
+*       bankBase  - The memory bank base address.
+*       bankLength  - The memory bank size. This function will decrement the
+*                   'bankLength' parameter by one and then check if the size is
+*                   valid. A valid size must be programed from LSB to MSB as
+*                   sequence of ‘1’s followed by sequence of ‘0’s.
+*                   To close a memory window simply set the size to 0.
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+* OUTPUT:
+*       None.
+* RETURN:
+*       False for invalid size, true otherwise.
+*
+* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
+*
+*******************************************************************************/
+
+bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
+		    unsigned int bankLength)
+{
+	unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
+
+/*    PCI_INTERNAL_BAR pciBAR; */
+
+	switch (bank) {
+	case BANK0:
+		baseReg = SCS_0_LOW_DECODE_ADDRESS;	/*CS_0_BASE_ADDR; */
+		sizeReg = SCS_0_HIGH_DECODE_ADDRESS;	/*CS_0_SIZE; */
+/*        pciBAR = PCI_CS0_BAR; */
+		break;
+	case BANK1:
+		baseReg = SCS_1_LOW_DECODE_ADDRESS;	/*CS_1_BASE_ADDR; */
+		sizeReg = SCS_1_HIGH_DECODE_ADDRESS;	/*CS_1_SIZE; */
+		/*        pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
+		break;
+	case BANK2:
+		baseReg = SCS_2_LOW_DECODE_ADDRESS;	/*CS_2_BASE_ADDR; */
+		sizeReg = SCS_2_HIGH_DECODE_ADDRESS;	/*CS_2_SIZE; */
+/*        pciBAR = PCI_CS2_BAR;*/
+		break;
+	case BANK3:
+		baseReg = SCS_3_LOW_DECODE_ADDRESS;	/*CS_3_BASE_ADDR; */
+		sizeReg = SCS_3_HIGH_DECODE_ADDRESS;	/*CS_3_SIZE; */
+/*        pciBAR = PCI_CS3_BAR; */
+		break;
+	default:
+		return false;
+	}
+	/* If the size is 0, the window will be disabled */
+	if (bankLength == 0) {
+		MemoryDisableWindow (CS_0_WINDOW << bank);
+		/* Disable the BAR from the PCI slave side */
+/*        gtPci0DisableInternalBAR(pciBAR); */
+/*        gtPci1DisableInternalBAR(pciBAR); */
+		return true;
+	}
+	/* The base address must be aligned to the size */
+	if ((bankBase % bankLength) != 0) {
+		return false;
+	}
+	if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
+		newBase = bankBase >> 16;
+		newSize = bankLength >> 16;
+		/* Checking that the size is a sequence of '1' followed by a
+		   sequence of '0' starting from LSB to MSB. */
+		temp = newSize - 1;
+		for (rShift = 0; rShift < 16; rShift++) {
+			temp = temp >> rShift;
+			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
+							/* or the size is not valid	 */
+				if (temp > 0x0)
+					return false;
+				else
+					break;
+			}
+		}
+#ifdef DEBUG
+		{
+			unsigned int oldBase, oldSize;
+
+			GT_REG_READ (baseReg, &oldBase);
+			GT_REG_READ (sizeReg + 8, &oldSize);
+
+			printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
+				bank, oldBase, oldSize, newBase, newSize);
+		}
+#endif
+		/* writing the new values */
+		GT_REG_WRITE (baseReg, newBase);
+		GT_REG_WRITE (sizeReg, newSize - 1);
+		/* Enable back the window */
+		MemoryEnableWindow (CS_0_WINDOW << bank);
+		/* Enable the BAR from the PCI slave side */
+/*        gtPci0EnableInternalBAR(pciBAR); */
+/*        gtPci1EnableInternalBAR(pciBAR); */
+		return true;
+	}
+	return false;
+}
+
+
+/*******************************************************************************
+* memoryMapDeviceSpace - Set new base address and size for one of the device
+*                           windows.
+*
+* DESCRIPTION:
+*       The CPU interface address decoding map consists of 21 address windows
+*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
+*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
+*       space. Each address window is defined by two registers - base and size.
+*       The CPU address is compared with the values in the various CPU windows
+*       until a match is found and the address is than targeted to that window.
+*       This function sets new base and size for one the device windows
+*       (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
+*       that there are no conflicts with other memory spaces. When two memory
+*       spaces overlap, the MV’s behavior is not defined .If a device window
+*       needs to be closed, set the 'deviceLength' parameter size to 0x0.
+*
+* INPUT:
+*       device           - One of the device windows (DEV_CS0-DEV_CS3) as
+*                          defined in gtMemory.h.
+*       deviceBase - The device window base address.
+*       deviceLength - The device window size. This function will decrement
+*                          the 'deviceLength' parameter by one and then
+*                          check if the size is valid. A valid size must be
+*                          programed from LSB to MSB as sequence of ‘1’s
+*                          followed by sequence of ‘0’s.
+*                          To close a memory window simply set the size to 0.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       False for invalid size, true otherwise.
+*
+* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
+*
+*******************************************************************************/
+
+bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
+			   unsigned int deviceLength)
+{
+	unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
+
+/*    PCI_INTERNAL_BAR pciBAR;*/
+
+	switch (device) {
+	case DEVICE0:
+		baseReg = CS_0_LOW_DECODE_ADDRESS;	/*DEV_CS0_BASE_ADDR; */
+		sizeReg = CS_0_HIGH_DECODE_ADDRESS;	/*DEV_CS0_SIZE; */
+/*        pciBAR = PCI_DEV_CS0_BAR; */
+		break;
+	case DEVICE1:
+		baseReg = CS_1_LOW_DECODE_ADDRESS;	/*DEV_CS1_BASE_ADDR; */
+		sizeReg = CS_1_HIGH_DECODE_ADDRESS;	/*DEV_CS1_SIZE; */
+/*        pciBAR = PCI_DEV_CS1_BAR; */
+		break;
+	case DEVICE2:
+		baseReg = CS_2_LOW_DECODE_ADDRESS;	/*DEV_CS2_BASE_ADDR; */
+		sizeReg = CS_2_HIGH_DECODE_ADDRESS;	/*DEV_CS2_SIZE; */
+/*        pciBAR = PCI_DEV_CS2_BAR; */
+		break;
+	case DEVICE3:
+		baseReg = CS_3_LOW_DECODE_ADDRESS;	/*DEV_CS3_BASE_ADDR; */
+		sizeReg = CS_3_HIGH_DECODE_ADDRESS;	/*DEV_CS3_SIZE; */
+/*        pciBAR = PCI_DEV_CS3_BAR; */
+		break;
+	case BOOT_DEVICE:
+		baseReg = BOOTCS_LOW_DECODE_ADDRESS;	/*BOOTCS_BASE_ADDR; */
+		sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;	/*BOOTCS_SIZE; */
+/*        pciBAR = PCI_BOOT_CS_BAR; */
+		break;
+	default:
+		return false;
+	}
+	if (deviceLength == 0) {
+		MemoryDisableWindow (DEVCS_0_WINDOW << device);
+		/* Disable the BAR from the PCI slave side */
+/*        gtPci0DisableInternalBAR(pciBAR); */
+/*        gtPci1DisableInternalBAR(pciBAR); */
+		return true;
+	}
+	/* The base address must be aligned to the size */
+	if ((deviceBase % deviceLength) != 0) {
+		return false;
+	}
+	if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
+		newBase = deviceBase >> 16;
+		newSize = deviceLength >> 16;
+		/* Checking that the size is a sequence of '1' followed by a
+		   sequence of '0' starting from LSB to MSB. */
+		temp = newSize - 1;
+		for (rShift = 0; rShift < 16; rShift++) {
+			temp = temp >> rShift;
+			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
+							/* or the size is not valid       */
+				if (temp > 0x0)
+					return false;
+				else
+					break;
+			}
+		}
+		/* writing the new values */
+		GT_REG_WRITE (baseReg, newBase);
+		GT_REG_WRITE (sizeReg, newSize - 1);
+		MemoryEnableWindow (DEVCS_0_WINDOW << device);
+		/* Enable the BAR from the PCI slave side */
+/*        gtPci0EnableInternalBAR(pciBAR); */
+/*        gtPci1EnableInternalBAR(pciBAR); */
+		return true;
+	}
+	return false;
+}
+
+/*******************************************************************************
+* MemorySetPciWindow - Set new base address and size for one of the PCI
+*                        windows.
+*
+* DESCRIPTION:
+*       The CPU interface address decoding map consists of 21 address windows
+*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
+*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
+*       space. Each address window is defined by two registers - base and size.
+*       The CPU address is compared with the values in the various CPU windows
+*       until a match is found and the address is than targeted to that window.
+*       This function sets new base and size for one the PCI windows
+*       (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
+*       that there are no conflicts with other memory spaces. When two memory
+*       spaces overlap, the MV’s behavior is not defined .If a PCI window
+*       needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
+*
+* INPUT:
+*       pciWindow     - One of the PCI windows as defined in gtMemory.h.
+*       pciWindowBase - The PCI window base address.
+*       pciWindowSize - The PCI window size. This function will decrement the
+*                       'pciWindowSize' parameter by one and then check if the
+*                       size is valid. A valid size must be programed from LSB
+*                       to MSB as sequence of ‘1’s followed by sequence of ‘0’s.
+*                       To close a memory window simply set the size to 0.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       False for invalid size, true otherwise.
+*
+*******************************************************************************/
+bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
+			 unsigned int pciWindowSize)
+{
+	unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
+
+	switch (pciWindow) {
+	case PCI_0_IO:
+		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_0_IO_BASE_ADDR; */
+		sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS;	/*PCI_0_IO_SIZE; */
+		break;
+	case PCI_0_MEM0:
+		baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY0_BASE_ADDR; */
+		sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY0_SIZE; */
+		break;
+	case PCI_0_MEM1:
+		baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY1_BASE_ADDR; */
+		sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY1_SIZE; */
+		break;
+	case PCI_0_MEM2:
+		baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY2_BASE_ADDR; */
+		sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY2_SIZE; */
+		break;
+	case PCI_0_MEM3:
+		baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY3_BASE_ADDR; */
+		sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY3_SIZE; */
+		break;
+#ifdef INCLUDE_PCI_1
+	case PCI_1_IO:
+		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_1_IO_BASE_ADDR; */
+		sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS;	/*PCI_1_IO_SIZE; */
+		break;
+	case PCI_1_MEM0:
+		baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY0_BASE_ADDR; */
+		sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY0_SIZE; */
+		break;
+	case PCI_1_MEM1:
+		baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY1_BASE_ADDR;  */
+		sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY1_SIZE; */
+		break;
+	case PCI_1_MEM2:
+		baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY2_BASE_ADDR;  */
+		sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY2_SIZE; */
+		break;
+	case PCI_1_MEM3:
+		baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY3_BASE_ADDR; */
+		sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY3_SIZE; */
+		break;
+#endif /* INCLUDE_PCI_1 */
+	default:
+		return false;
+	}
+	if (pciWindowSize == 0) {
+		MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
+		return true;
+	}
+	/* The base address must be aligned to the size */
+	if ((pciWindowBase % pciWindowSize) != 0) {
+		return false;
+	}
+	if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
+		pciWindowBase >>= 16;
+		pciWindowSize >>= 16;
+		/* Checking that the size is a sequence of '1' followed by a
+		   sequence of '0' starting from LSB to MSB. */
+		temp = pciWindowSize - 1;
+		for (rShift = 0; rShift < 16; rShift++) {
+			temp = temp >> rShift;
+			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
+							/* or the size is not valid       */
+				if (temp > 0x0)
+					return false;
+				else
+					break;
+			}
+		}
+		GT_REG_WRITE (sizeReg, pciWindowSize - 1);
+		GT_REG_READ (baseAddrReg, &currentLow);
+		pciWindowBase =
+			(pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
+		GT_REG_WRITE (baseAddrReg, pciWindowBase);
+		MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
+		return true;
+	}
+	return false;
+}
+
+/*******************************************************************************
+* memoryMapInternalRegistersSpace - Sets new base address for the internal
+*                                  registers memory space.
+*
+* DESCRIPTION:
+*       This function set new base address for the internal register’s memory
+*       space (the size is fixed and cannot be modified). The function does not
+*       handle overlapping with other memory spaces, it is the programer's
+*       responsibility to ensure that overlapping does not occur.
+*       When two memory spaces overlap, the MV’s behavior is not defined.
+*
+* INPUT:
+*       internalRegBase - new base address for the internal register’s memory
+*                         space.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*        true on success, false on failure
+*
+*******************************************************************************/
+/********************************************************************
+* memoryMapInternalRegistersSpace - Sets new base address for the internals
+*                                   registers.
+*
+* INPUTS:  unsigned int internalRegBase - The new base address.
+* RETURNS: true on success, false on failure
+*********************************************************************/
+bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
+{
+	unsigned int currentValue;
+	unsigned int internalValue = internalRegBase;
+
+	internalRegBase = (internalRegBase >> 16);
+	GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
+	internalRegBase = (currentValue & 0xff000000) | internalRegBase;
+	GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
+	/* initializing also the global variable 'internalRegBaseAddr' */
+/*    gtInternalRegBaseAddr = internalValue; */
+	INTERNAL_REG_BASE_ADDR = internalValue;
+	return true;
+}
+
+/*******************************************************************************
+* memoryGetInternalRegistersSpace - Returns the internal registers Base
+*                                     address.
+*
+* DESCRIPTION:
+*       This function returns the base address of  the internal register’s
+*       memory space .
+*
+* INPUT:
+*       None.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       32 bit base address of the internal register’s memory space.
+*
+*******************************************************************************/
+unsigned int memoryGetInternalRegistersSpace (void)
+{
+	unsigned int currentValue = 0;
+
+	GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
+	return ((currentValue & 0x000fffff) << 16);
+}
+
+/*******************************************************************************
+* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
+*
+* DESCRIPTION:
+*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
+*       funcnion return the SRAM's base address.
+* INPUT:
+*       None.
+* OUTPUT:
+*       None.
+* RETURN:
+*       32 bit SRAM's base address.
+*
+*******************************************************************************/
+unsigned int memoryGetInternalSramBaseAddr (void)
+{
+	return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
+}
+
+/*******************************************************************************
+* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
+*
+* DESCRIPTION:
+*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
+*       function sets a new base address to the SRAM .
+* INPUT:
+*       sramBaseAddress - The SRAM's base address.
+* OUTPUT:
+*       None.
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
+{
+	GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
+}
+
+/*******************************************************************************
+* memorySetProtectRegion - Set protection mode for one of the 8 regions.
+*
+* DESCRIPTION:
+*       The CPU interface supports configurable access protection. This includes
+*       up to eight address ranges defined to a different protection type :
+*       whether the address range is cacheable or not, whether it is writable or
+*       not , and whether it is accessible or not. A Low and High registers
+*       define each window while the minimum address range of each window is
+*       1Mbyte. An address driven by the CPU, in addition to the address
+*       decoding and remapping process, is compared against the eight Access
+*       Protection Low/High registers , if an address matches one of the windows
+*       , the MV device checks the transaction type against the protection bits
+*       defined in CPU Access Protection register, to determine if the access is
+*       allowed. This function set a protection mode to one of the 8 possible
+*       regions.
+*      NOTE:
+*       The CPU address windows are restricted to a size of  2 power n and the
+*       start address must be aligned to the window size. For example, if using
+*       a 16 MB window, the start address bits [23:0] must be 0.The MV's
+*       internal registers space is not protected, even if the access protection
+*       windows contain this space.
+*
+* INPUT:
+*       region - selects which region to be configured. The values defined in
+*                gtMemory.h:
+*
+*                 - MEM_REGION0
+*                 - MEM_REGION1
+*                 - etc.
+*
+*       memAccess - Allows or forbids access (read or write ) to the region. The
+*                   values defined in gtMemory.h:
+*
+*                    - MEM_ACCESS_ALLOWED
+*                    - MEM_ACCESS_FORBIDEN
+*
+*       memWrite - CPU write protection to the region. The values defined in
+*                  gtMemory.h:
+*
+*                   - MEM_WRITE_ALLOWED
+*                   - MEM_WRITE_FORBIDEN
+*
+*       cacheProtection - Defines whether caching the region is allowed or not.
+*                         The values defined in gtMemory.h:
+*
+*                          - MEM_CACHE_ALLOWED
+*                          - MEM_CACHE_FORBIDEN
+*
+*       baseAddress - the region's base Address.
+*       regionSize  - The region's size. This function will decrement the
+*                     'regionSize' parameter by one and then check if the size
+*                     is valid. A valid size must be programed from LSB to MSB
+*                     as sequence of ‘1’s followed by sequence of ‘0’s.
+*                     To close a memory window simply set the size to 0.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       False for invalid size, true otherwise.
+*
+*******************************************************************************/
+bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
+			     MEMORY_ACCESS memAccess,
+			     MEMORY_ACCESS_WRITE memWrite,
+			     MEMORY_CACHE_PROTECT cacheProtection,
+			     unsigned int baseAddress, unsigned int size)
+{
+	unsigned int dataForReg, temp, rShift;
+
+	if (size == 0) {
+		GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
+			      0x0);
+		return true;
+	}
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size >= MINIMUM_ACCESS_WIN_SIZE) {
+		baseAddress = ((baseAddress >> 16) & 0xfffff);
+		dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
+			((memWrite << 21) & BIT21) | ((cacheProtection << 22)
+						      & BIT22) | BIT31;
+		GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
+			      dataForReg);
+		size >>= 16;
+		/* Checking that the size is a sequence of '1' followed by a
+		   sequence of '0' starting from LSB to MSB. */
+		temp = size - 1;
+		for (rShift = 0; rShift < 16; rShift++) {
+			temp = temp >> rShift;
+			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
+							/* or the size is not valid       */
+				if (temp > 0x0)
+					return false;
+				else
+					break;
+			}
+		}
+		GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
+			      size - 1);
+		return true;
+	}
+	return false;
+}
+
+/*******************************************************************************
+* gtMemoryDisableProtectRegion - Disable a protected window.
+*
+* DESCRIPTION:
+*       This function disable a protected window set by
+*       'gtMemorySetProtectRegion' function.
+*
+* INPUT:
+*       window - one of the 4 windows ( defined in gtMemory.h ).
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
+{
+	RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
+			BIT31);
+}
+
+/*******************************************************************************
+* memorySetPciRemapValue - Set a remap value to a PCI memory space target.
+*
+* DESCRIPTION:
+*       In addition to the address decoding mechanism, the CPU has an address
+*       remapping mechanism to be used by every PCI decoding window. Each PCI
+*       window can be remaped to a desired address target according to the remap
+*       value within the remap register. The address remapping is useful when a
+*       CPU address range must be reallocated to a different location on the
+*       PCI bus. Also, it enables CPU access to a PCI agent located above the
+*       4Gbyte space. On system boot, each of the PCI memory spaces is maped to
+*       a defualt value (see CPU interface section in the MV spec for the
+*       default values). The remap mechanism does not always produce the desired
+*       address on the PCI bus because of the remap mechanism way of working
+*       (to fully understand why, please see the 'Address Remapping' section in
+*       the MV's spec). Therefor, this function sets a desired remap value to
+*       one of the PCI memory windows and return the effective address that
+*       should be used when exiting the PCI memory window. You should ALWAYS use
+*       the returned value by this function when remapping a PCI window and
+*       exiting it. If for example the base address of PCI0 memory 0 is
+*       0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
+*       the function will return the value of 0x91000000 that MUST
+*       be used to exit this memory window in order to achive the deisred
+*       remapping.
+*
+* INPUT:
+*       memoryWindow   - One of the PCI memory windows as defined in Memory.h
+*       remapValueLow  - The low remap value.
+*       remapValueHigh - The high remap value.
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       The effective base address to exit the PCI, or 0xffffffff if one of the
+*       parameters is erroneous or the effective base address is higher the top
+*       decode value.
+*
+*******************************************************************************/
+unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
+				     unsigned int remapValueHigh,
+				     unsigned int remapValueLow)
+{
+	unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
+	unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
+	unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
+
+	/* Initializing the base and size variables of the PCI
+	   memory windows */
+	switch (memoryWindow) {
+	case PCI_0_IO:
+		pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_IO_SIZE;
+		remapRegLow = PCI_0_IO_ADDR_REMAP;
+		remapRegHigh = PCI_0_IO_ADDR_REMAP;
+		break;
+	case PCI_0_MEM0:
+		pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
+		remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
+		break;
+	case PCI_0_MEM1:
+		pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
+		remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
+		break;
+	case PCI_0_MEM2:
+		pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
+		remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
+		break;
+	case PCI_0_MEM3:
+		pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
+		remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
+		break;
+#ifdef INCLUDE_PCI_1
+	case PCI_1_IO:
+		pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_IO_SIZE;
+		remapRegLow = PCI_1_IO_ADDR_REMAP;
+		remapRegHigh = PCI_1_IO_ADDR_REMAP;
+		break;
+	case PCI_1_MEM0:
+		pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
+		remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
+		break;
+	case PCI_1_MEM1:
+		pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
+		remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
+		break;
+	case PCI_1_MEM2:
+		pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
+		remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
+		break;
+	case PCI_1_MEM3:
+		pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
+		pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
+		remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
+		remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
+		break;
+#endif /* INCLUDE_PCI_1 */
+	default:
+		/* Retrun an invalid effective base address */
+		return 0xffffffff;
+	}
+	/* Writing the remap value to the remap regisers */
+	GT_REG_WRITE (remapRegHigh, remapValueHigh);
+	GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
+	/* Reading the values from the base address and size registers */
+	baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
+	windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
+	/* Start calculating the effective Base Address */
+	effectiveBaseAddress = baseAddrValue << 16;
+	/* The effective base address will be combined from the chopped (if any)
+	   remap value (according to the size value and remap mechanism) and the
+	   window's base address */
+	effectiveBaseAddress |=
+		(((windowSizeValue << 16) | 0xffff) & remapValueLow);
+	/* If the effectiveBaseAddress exceed the window boundaries return an
+	   invalid value. */
+	if (effectiveBaseAddress >
+	    ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
+		return 0xffffffff;
+	return effectiveBaseAddress;
+}
+
+/********************************************************************
+* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
+*                            supports Cache Coherency.
+*
+*
+* Inputs: SNOOP_REGION region - One of the four regions.
+*         SNOOP_TYPE snoopType - There is four optional Types:
+*                               1. No Snoop.
+*                               2. Snoop to WT region.
+*                               3. Snoop to WB region.
+*                               4. Snoop & Invalidate to WB region.
+*         unsigned int baseAddress - Base Address of this region.
+*         unsigned int topAddress - Top Address of this region.
+* Returns: false if one of the parameters is wrong and true else
+*********************************************************************/
+/* evb6260 code */
+#if 0
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+			      MEMORY_SNOOP_TYPE snoopType,
+			      unsigned int baseAddress,
+			      unsigned int regionLength)
+{
+    unsigned int snoopXbaseAddress;
+    unsigned int snoopXtopAddress;
+    unsigned int data;
+    unsigned int snoopHigh = baseAddress + regionLength;
+
+    if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
+	return false;
+    snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
+    snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
+				 if(regionLength == 0) /* closing the region */
+    {
+	GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
+	GT_REG_WRITE(snoopXtopAddress,0);
+	return true;
+    }
+    baseAddress = baseAddress & 0xffff0000;
+    data = (baseAddress >> 16) | snoopType << 16;
+    GT_REG_WRITE(snoopXbaseAddress,data);
+    snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+    GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
+    return true;
+}
+#endif
+
+/********************************************************************
+* memoryRemapAddress - This fubction used for address remapping.
+*
+*
+* Inputs: regOffset: remap register
+*         remapValue :
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*
+* Not needed function To_do !!!!
+*********************************************************************/
+bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
+{
+	unsigned int valueForReg;
+
+	valueForReg = (remapValue & 0xfff00000) >> 20;
+	GT_REG_WRITE (remapReg, valueForReg);
+	return true;
+}
+
+/*******************************************************************************
+* memoryGetDeviceParam - Extract the device parameters from the device bank
+*                          parameters register.
+*
+* DESCRIPTION:
+*       To allow interfacing with very slow devices and fast synchronous SRAMs,
+*       each device can be programed to different timing parameters. Each bank
+*       has its own parameters register. Bank width can be programmed to 8, 16,
+*       or 32-bits. Bank timing parameters can be programmed to support
+*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
+*       Controllers). The MV allows you to set timing parameters and width for
+*       each device through parameters register .
+*       This function extracts the parameters described from the Device Bank
+*       parameters register and fills the given 'deviceParam' (defined in
+*       gtMemory.h) structure with the read data.
+*
+* INPUT:
+*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
+*                      Memory.h).For details about each structure field please
+*                      see the device timing parameter section in the MV
+*                      datasheet.
+*       deviceNum  -   Select on of the five device banks (defined in
+*                      Memory.h) :
+*
+*                       - DEVICE0
+*                       - DEVICE1
+*                       - DEVICE2
+*                       - etc.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       false if one of the parameters is erroneous,true otherwise.
+*
+*******************************************************************************/
+/********************************************************************
+* memoryGetDeviceParam - This function used for getting device parameters from
+*                        DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs:        - deviceParam: STRUCT with paramiters for DEVICE BANK
+*                  PARAMETERS REGISTER
+*                - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+
+bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
+{
+	unsigned int valueOfReg;
+	unsigned int calcData;
+
+	if (deviceNum > 4)
+		return false;
+	GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
+	calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
+	deviceParam->turnOff = calcData;	/* Turn Off */
+
+	calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
+	deviceParam->acc2First = calcData;	/* Access To First */
+
+	calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
+	deviceParam->acc2Next = calcData;	/* Access To Next */
+
+	calcData =
+		((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
+	deviceParam->ale2Wr = calcData;	/* Ale To Write */
+
+	calcData = ((0x1c000 & valueOfReg) >> 14) +
+		((BIT26 & valueOfReg) >> 23);
+	deviceParam->wrLow = calcData;	/* Write Active */
+
+	calcData = ((0xe0000 & valueOfReg) >> 17) +
+		((BIT27 & valueOfReg) >> 24);
+	deviceParam->wrHigh = calcData;	/* Write High */
+
+	calcData = ((0x300000 & valueOfReg) >> 20);
+	deviceParam->deviceWidth = (BIT0 << calcData);	/* In bytes */
+	calcData = ((0x30000000 & valueOfReg) >> 28);
+	deviceParam->badrSkew = calcData;	/* Cycles gap between BAdr
+						   toggle to read data sample. */
+	calcData = ((0x40000000 & valueOfReg) >> 30);
+	deviceParam->DPEn = calcData;	/*  Data Parity enable  */
+	return true;
+}
+
+/*******************************************************************************
+* memorySetDeviceParam - Set new parameters for a device.
+*
+*
+* DESCRIPTION:
+*       To allow interfacing with very slow devices and fast synchronous SRAMs,
+*       each device can be programed to different timing parameters. Each bank
+*       has its own parameters register. Bank width can be programmed to 8, 16,
+*       or 32-bits. Bank timing parameters can be programmed to support
+*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
+*       Controllers). The MV allows you to set timing parameters and width for
+*       each device through parameters register. This function set new
+*       parameters to a device Bank from the delivered structure 'deviceParam'
+*       (defined in gtMemory.h). The structure must be initialized with data
+*       prior to the use of these function.
+*
+* INPUT:
+*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
+*                      Memory.h).For details about each structure field please
+*                      see the device timing parameter section in the MV
+*                      datasheet.
+*       deviceNum  -   Select on of the five device banks (defined in
+*                      Memory.h) :
+*
+*                       - DEVICE0
+*                       - DEVICE1
+*                       - DEVICE2
+*                       - etc.
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       false if one of the parameters is erroneous,true otherwise.
+*
+*******************************************************************************/
+/********************************************************************
+* memorySetDeviceParam - This function used for setting device parameters to
+*                        DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs:        - deviceParam: STRUCT for store paramiters from DEVICE BANK
+*                  PARAMETERS REGISTER
+*                - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
+{
+	unsigned int valueForReg;
+
+	if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
+	    (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
+	    (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
+	    (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
+		return false;
+	}
+	valueForReg = (((deviceParam->turnOff) & 0x7) |
+		       (((deviceParam->turnOff) & 0x8) << 19) |
+		       (((deviceParam->acc2First) & 0xf) << 3) |
+		       (((deviceParam->acc2First) & 0x10) << 19) |
+		       (((deviceParam->acc2Next) & 0xf) << 7) |
+		       (((deviceParam->acc2Next) & 0x10) << 20) |
+		       (((deviceParam->ale2Wr) & 0x7) << 11) |
+		       (((deviceParam->ale2Wr) & 0xf) << 22) |
+		       (((deviceParam->wrLow) & 0x7) << 14) |
+		       (((deviceParam->wrLow) & 0xf) << 23) |
+		       (((deviceParam->wrHigh) & 0x7) << 17) |
+		       (((deviceParam->wrHigh) & 0xf) << 24) |
+		       (((deviceParam->badrSkew) & 0x3) << 28) |
+		       (((deviceParam->DPEn) & 0x1) << 30));
+
+	/* insert the device width: */
+	switch (deviceParam->deviceWidth) {
+	case 1:
+		valueForReg = valueForReg | _8BIT;
+		break;
+	case 2:
+		valueForReg = valueForReg | _16BIT;
+		break;
+	case 4:
+		valueForReg = valueForReg | _32BIT;
+		break;
+	default:
+		valueForReg = valueForReg | _8BIT;
+		break;
+	}
+	GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
+	return true;
+}
+
+/*******************************************************************************
+* MemoryDisableWindow - Disable a memory space by the disable bit.
+* DESCRIPTION:
+*       This function disables one of the 21 availiable windows dedicated for
+*       the CPU decoding mechanism. Its possible to combine several windows with
+*       the OR command.
+* INPUT:
+*       window - One or more of the memory windows (defined in gtMemory.h).
+* OUTPUT:
+*       None.
+* RETURN:
+*       None.
+*******************************************************************************/
+void MemoryDisableWindow (MEMORY_WINDOW window)
+{
+	SET_REG_BITS (BASE_ADDR_ENABLE, window);
+}
+
+/*******************************************************************************
+* MemoryEnableWindow - Enable a memory space that was disabled by
+*                       'MemoryDisableWindow'.
+* DESCRIPTION:
+*       This function enables one of the 21 availiable windows dedicated for the
+*       CPU decoding mechanism. Its possible to combine several windows with the
+*       OR command.
+* INPUT:
+*       window - One or more of the memory windows (defined in gtMemory.h).
+* OUTPUT:
+*       None.
+* RETURN:
+*       None.
+*******************************************************************************/
+void MemoryEnableWindow (MEMORY_WINDOW window)
+{
+	RESET_REG_BITS (BASE_ADDR_ENABLE, window);
+}
+
+/*******************************************************************************
+* MemoryGetMemWindowStatus - This function check whether the memory window is
+*                              disabled or not.
+* DESCRIPTION:
+*       This function checks if the given memory window is closed .
+* INPUT:
+*       window - One or more of the memory windows (defined in gtMemory.h).
+* OUTPUT:
+*       None.
+* RETURN:
+*       True for a closed window, false otherwise .
+*******************************************************************************/
+MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
+{
+	if (GTREGREAD (BASE_ADDR_ENABLE) & window)
+		return MEM_WINDOW_DISABLED;
+	return MEM_WINDOW_ENABLED;
+}
diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S
new file mode 100755
index 0000000..41c3a95
--- /dev/null
+++ b/board/Marvell/common/misc.S
@@ -0,0 +1,235 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include "version.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "../include/mv_gen_reg.h"
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CFG_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CFG_MONITOR_LEN@h
+	ori	r8, r8, CFG_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11: gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CFG_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CFG_DFL_GT_REGS@h
+	ori	r3, r3, CFG_DFL_GT_REGS@l
+	lis	r4, CFG_GT_REGS@h
+	ori	r4, r4, CFG_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
+/*	rlwinm	r7, r4, 8, 16, 31
+	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
+	rlwinm	r7, r4, 16, 16, 31
+	/* -----------------------------------------------------*/
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0_relocated
+led_on0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC80
+	ori	r18, r18, 0x8000
+	stw	r21, 0x0(r18)
+/*	  stw	  r18, 0x0(r18) */
+	sync
+	blr
+
+	.global led_off0_relocated
+led_off0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC81
+	ori	r18, r18, 0x4000
+	stw	r21, 0x0(r18)
+/*	  stw	  r18, 0x0(r18) */
+	sync
+	blr
+
+	.global led_on0
+led_on0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0x8000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_off0
+led_off0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x4000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0xc000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_off1
+led_off1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x8000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x0000
+	stw	r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_off2
+led_off2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0xc000
+	stw	r18, 0x0(r18)
+	sync
+	blr
diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c
new file mode 100755
index 0000000..475445b
--- /dev/null
+++ b/board/Marvell/common/ns16550.c
@@ -0,0 +1,66 @@
+/*
+ * COM1 NS16550 support
+ * originally from linux source (arch/ppc/boot/ns16550.c)
+ * modified to use CFG_ISA_MEM and new defines
+ *
+ * further modified by Josh Huber <huber@mclx.com> to support
+ * the DUART on the Galileo Eval board. (db64360)
+ */
+
+#include <config.h>
+#include "ns16550.h"
+
+#ifdef ZUMA_NTL
+/* no 16550 device */
+#else
+const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0),
+	(NS16550_t) (CFG_DUART_IO + 0x20)
+};
+
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
+{
+	volatile struct NS16550 *com_port;
+
+	com_port = (struct NS16550 *) COM_PORTS[chan];
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
+
+	/* Clear & enable FIFOs */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+	return (com_port);
+}
+
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
+{
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
+
+	/* Clear & enable FIFOs */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
+}
+
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
+{
+	while ((com_port->lsr & LSR_THRE) == 0);
+	com_port->thr = c;
+}
+
+unsigned char NS16550_getc (volatile struct NS16550 *com_port)
+{
+	while ((com_port->lsr & LSR_DR) == 0);
+	return (com_port->rbr);
+}
+
+int NS16550_tstc (volatile struct NS16550 *com_port)
+{
+	return ((com_port->lsr & LSR_DR) != 0);
+}
+#endif
diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h
new file mode 100755
index 0000000..f2ed2ab
--- /dev/null
+++ b/board/Marvell/common/ns16550.h
@@ -0,0 +1,102 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/ppc/boot/ns16550.h)
+ * modified slightly to
+ * have addresses as offsets from CFG_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ *
+ * further modified to support the DUART in the Galileo eval board
+ * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ */
+
+#ifndef __NS16550_H__
+#define __NS16550_H__
+
+/* the padding is necessary because on the galileo board the UART is
+   wired in with the 3 address lines shifted over by 2 bits */
+struct NS16550
+{
+	unsigned char rbr;  /* 0 = 0-3*/
+	int pad1:24;
+
+	unsigned char ier;  /* 1 = 4-7*/
+	int pad2:24;
+
+	unsigned char fcr;  /* 2 = 8-b*/
+	int pad3:24;
+
+	unsigned char lcr;  /* 3 = c-f*/
+	int pad4:24;
+
+	unsigned char mcr;  /* 4 = 10-13*/
+	int pad5:24;
+
+	unsigned char lsr;  /* 5 = 14-17*/
+	int pad6:24;
+
+	unsigned char msr;  /* 6 =18-1b*/
+	int pad7:24;
+
+	unsigned char scr;  /* 7 =1c-1f*/
+	int pad8:24;
+} __attribute__ ((packed));
+
+/* aliases */
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+#define FCR_FIFO_EN     0x01    /*fifo enable*/
+#define FCR_RXSR        0x02    /*reciever soft reset*/
+#define FCR_TXSR        0x04    /*transmitter soft reset*/
+
+
+#define MCR_DTR         0x01
+#define MCR_RTS         0x02
+#define MCR_DMA_EN      0x04
+#define MCR_TX_DFR      0x08
+
+
+#define LCR_WLS_MSK 0x03    /* character length slect mask*/
+#define LCR_WLS_5   0x00    /* 5 bit character length */
+#define LCR_WLS_6   0x01    /* 6 bit character length */
+#define LCR_WLS_7   0x02    /* 7 bit character length */
+#define LCR_WLS_8   0x03    /* 8 bit character length */
+#define LCR_STB     0x04    /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN     0x08    /* Parity eneble*/
+#define LCR_EPS     0x10    /* Even Parity Select*/
+#define LCR_STKP    0x20    /* Stick Parity*/
+#define LCR_SBRK    0x40    /* Set Break*/
+#define LCR_BKSE    0x80    /* Bank select enable*/
+
+#define LSR_DR      0x01    /* Data ready */
+#define LSR_OE      0x02    /* Overrun */
+#define LSR_PE      0x04    /* Parity error */
+#define LSR_FE      0x08    /* Framing error */
+#define LSR_BI      0x10    /* Break */
+#define LSR_THRE    0x20    /* Xmit holding register empty */
+#define LSR_TEMT    0x40    /* Xmitter empty */
+#define LSR_ERR     0x80    /* Error */
+
+/* useful defaults for LCR*/
+#define LCR_8N1     0x03
+
+
+#define COM1 0x03F8
+#define COM2 0x02F8
+
+volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
+void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc(volatile struct NS16550 *com_port);
+int NS16550_tstc(volatile struct NS16550 *com_port);
+void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
+
+typedef struct NS16550 *NS16550_t;
+
+extern const NS16550_t COM_PORTS[];
+
+#endif
diff --git a/board/Marvell/common/ppc_error_no.h b/board/Marvell/common/ppc_error_no.h
new file mode 100755
index 0000000..53687c8
--- /dev/null
+++ b/board/Marvell/common/ppc_error_no.h
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
+ */
+#ifndef _MV_PPC_ERRNO_H
+#define _MV_PPC_ERRNO_H
+
+#define	EPERM		 1	/* Operation not permitted */
+#define	ENOENT		 2	/* No such file or directory */
+#define	ESRCH		 3	/* No such process */
+#define	EINTR		 4	/* Interrupted system call */
+#define	EIO		 5	/* I/O error */
+#define	ENXIO		 6	/* No such device or address */
+#define	E2BIG		 7	/* Arg list too long */
+#define	ENOEXEC		 8	/* Exec format error */
+#define	EBADF		 9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+#define	EDEADLOCK	58	/* File locking deadlock error */
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+/* Should never be seen by user programs */
+#define ERESTARTSYS	512
+#define ERESTARTNOINTR	513
+#define ERESTARTNOHAND	514	/* restart if no handler.. */
+#define ENOIOCTLCMD	515	/* No ioctl command */
+
+#define _LAST_ERRNO	515
+
+#endif
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
new file mode 100755
index 0000000..9d0d213
--- /dev/null
+++ b/board/Marvell/common/serial.c
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * serial.c - serial support for the gal ev board
+ */
+
+/* supports both the 16650 duart and the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include "../include/memory.h"
+#include "serial.h"
+
+#ifdef CONFIG_DB64360
+#include "../db64360/mpsc.h"
+#endif
+
+#ifdef CONFIG_DB64460
+#include "../db64460/mpsc.h"
+#endif
+
+#include "ns16550.h"
+
+#ifdef CONFIG_MPSC
+
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+	int clock_divisor = 230400 / gd->baudrate;
+#endif
+
+	mpsc_init (gd->baudrate);
+
+	/* init the DUART chans so that KGDB in the kernel can use them */
+#ifdef CFG_INIT_CHAN1
+	NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		mpsc_putchar ('\r');
+
+	mpsc_putchar (c);
+}
+
+int serial_getc (void)
+{
+	return mpsc_getchar ();
+}
+
+int serial_tstc (void)
+{
+	return mpsc_test_char ();
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+#else  /* ! CONFIG_MPSC */
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = 230400 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+	(void) NS16550_init (0, clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	(void) NS16550_init (1, clock_divisor);
+#endif
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
+
+	NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
+}
+
+int serial_getc (void)
+{
+	return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
+}
+
+int serial_tstc (void)
+{
+	return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = 230400 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+	NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+}
+
+#endif /* CONFIG_MPSC */
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif /* CFG_CMD_KGDB */
diff --git a/board/Marvell/common/serial.h b/board/Marvell/common/serial.h
new file mode 100755
index 0000000..c7fc8c1
--- /dev/null
+++ b/board/Marvell/common/serial.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* serial.h - mostly useful for DUART serial_init in serial.c */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#if 0
+
+#define B230400         1
+#define B115200         2
+#define B57600          4
+#define B38400          82
+#define B19200          163
+#define B9600           24
+#define B4800           651
+#define B2400           1302
+#define B1200           2604
+#define B600            5208
+#define B300            10417
+#define B150            20833
+#define B110            28409
+#define BDEFAULT        B115200
+
+				/* this stuff is important to initialize
+				the DUART channels */
+
+#define	Scale		0x01L		/* distance between port addresses */
+#define	COM1		0x000003f8		/* Keyboard */
+#define COM2		0x000002f8		/* Host */
+
+
+/* Port Definitions relative to base COM port addresses */
+#define DataIn	(0x00*Scale)	/* data input port */
+#define DataOut	(0x00*Scale)	/* data output port */
+#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
+#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
+#define	Ier	(0x01*Scale)	/* interrupt enable register */
+#define	Iir	(0x02*Scale)	/* interrupt identification register */
+#define	Lcr	(0x03*Scale)	/* line control register */
+#define	Mcr	(0x04*Scale)	/* modem control register */
+#define	Lsr	(0x05*Scale)	/* line status register */
+#define	Msr	(0x06*Scale)	/* modem status register */
+
+/* Bit Definitions for above ports */
+#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
+#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
+
+#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
+#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
+#define	McrDflt	(McrRts|McrDtr)
+
+#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
+			/* b6: transmitter empty */
+#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
+
+#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
+#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
+#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
+
+#define IerRda	0xf	/* b0: Enable received data available interrupt */
+
+#endif
+
+#endif /* __SERIAL_H__ */
diff --git a/board/Marvell/db64360/64360.h b/board/Marvell/db64360/64360.h
new file mode 100755
index 0000000..a65e23b
--- /dev/null
+++ b/board/Marvell/db64360/64360.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the Galileo Eval board DB64360.
+ */
+
+#ifndef __64360_H__
+#define __64360_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64360_H__ */
diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile
new file mode 100755
index 0000000..768ccdd
--- /dev/null
+++ b/board/Marvell/db64360/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+SOBJS	= ../common/misc.o
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
+	  sdram_init.o ../common/intel_flash.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/Marvell/db64360/config.mk b/board/Marvell/db64360/config.mk
new file mode 100755
index 0000000..0e42b48
--- /dev/null
+++ b/board/Marvell/db64360/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EVB64360 boards
+#
+
+TEXT_BASE = 0xfff00000
diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c
new file mode 100755
index 0000000..a2ab2d7
--- /dev/null
+++ b/board/Marvell/db64360/db64360.c
@@ -0,0 +1,936 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
+ */
+
+/*
+ * db64360.c - main board support/init for the Galileo Eval board.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+extern void flush_data_cache (void);
+extern void invalidate_l1_instruction_cache (void);
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+int display_mem_map (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CFG_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64360 P.399 */
+#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	uchar sram_boot = 0;
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6436x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6436x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 * Zuma
+	 * 0 - Flash
+	 * boot - BootCS
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+		sram_boot = 1;
+	if (!sram_boot)
+		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+
+	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+
+
+	/* configure device timing */
+#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+	if (!sram_boot)
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+#endif
+
+#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#endif
+#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#endif
+
+#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CFG_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CFG_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	/* check to see if we booted from the sram.  If so, move things
+	 * back to the way they should be. (we're running from main
+	 * memory at this point now */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+	}
+	display_mem_map ();
+	/* now, jump to the main ppcboot board init code */
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+	volatile int *addr = 0;
+	int dummy;
+
+	if (mode == 1) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x08000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x0c000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x10000);
+			break;
+		}
+	} else if (mode == 0) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x14000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x18000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x1c000);
+			break;
+		}
+	}
+
+	dummy = *addr;
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- EXT SRAM (actual - 1M)\n");
+		else if (i == 1)
+			printf ("\t- RTC\n");
+		else if (i == 2)
+			printf ("\t- UART\n");
+		else
+			printf ("\t- LARGE FLASH\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CFG_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CFG_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_DATA */
+
+#if defined (CFG_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_MEMTEST_START;
+	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_ADDRESS */
+
+#if defined (CFG_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_MEMTEST_START;
+	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata, runaddress, runwalk;
+
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+
+/*    rundata = 1; */
+/*    runaddress = 0; */
+/*    runwalk = 0; */
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+	}
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CFG_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
+/* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
+
+/* Relocate MV64360 internal regs */
+	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+
+	icache_disable ();
+	invalidate_l1_instruction_cache ();
+	flush_data_cache ();
+	dcache_disable ();
+}
diff --git a/board/Marvell/db64360/eth.h b/board/Marvell/db64360/eth.h
new file mode 100755
index 0000000..aab32d2
--- /dev/null
+++ b/board/Marvell/db64360/eth.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64360_ETH_H__
+#define __EVB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+
+int db64360_eth0_poll(void);
+int db64360_eth0_transmit(unsigned int s, volatile char *p);
+void db64360_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+
+#endif /* __EVB64360_ETH_H__ */
diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c
new file mode 100755
index 0000000..ccb3adc
--- /dev/null
+++ b/board/Marvell/db64360/mpsc.c
@@ -0,0 +1,1019 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+#include "mv_regs.h"
+
+#include "../include/memory.h"
+
+/* Define this if you wish to use the MPSC as a register based UART.
+ * This will force the serial port to not use the SDMA engine at all.
+ */
+#undef CONFIG_MPSC_DEBUG_PORT
+
+
+int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
+char (*mpsc_getchar) (void) = mpsc_getchar_debug;
+int (*mpsc_test_char) (void) = mpsc_test_char_debug;
+
+
+static volatile unsigned int *rx_desc_base = NULL;
+static unsigned int rx_desc_index = 0;
+static volatile unsigned int *tx_desc_base = NULL;
+static unsigned int tx_desc_index = 0;
+
+/* local function declarations */
+static int galmpsc_connect (int channel, int connect);
+static int galmpsc_route_rx_clock (int channel, int brg);
+static int galmpsc_route_tx_clock (int channel, int brg);
+static int galmpsc_write_config_regs (int mpsc, int mode);
+static int galmpsc_config_channel_regs (int mpsc);
+static int galmpsc_set_char_length (int mpsc, int value);
+static int galmpsc_set_stop_bit_length (int mpsc, int value);
+static int galmpsc_set_parity (int mpsc, int value);
+static int galmpsc_enter_hunt (int mpsc);
+static int galmpsc_set_brkcnt (int mpsc, int value);
+static int galmpsc_set_tcschar (int mpsc, int value);
+static int galmpsc_set_snoop (int mpsc, int value);
+static int galmpsc_shutdown (int mpsc);
+
+static int galsdma_set_RFT (int channel);
+static int galsdma_set_SFM (int channel);
+static int galsdma_set_rxle (int channel);
+static int galsdma_set_txle (int channel);
+static int galsdma_set_burstsize (int channel, unsigned int value);
+static int galsdma_set_RC (int channel, unsigned int value);
+
+static int galbrg_set_CDV (int channel, int value);
+static int galbrg_enable (int channel);
+static int galbrg_disable (int channel);
+static int galbrg_set_clksrc (int channel, int value);
+static int galbrg_set_CUV (int channel, int value);
+
+static void galsdma_enable_rx (void);
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress,
+				  unsigned int size);
+
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+static void mpsc_debug_init (void)
+{
+
+	volatile unsigned int temp;
+
+	/* Clear the CFR  (CHR4) */
+	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&".  Assuming "= &"
+
+REG_GAP));
+	temp &= 0xffffff00;
+	temp |= BIT29;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
+	temp |= (BIT12 | BIT15);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set int mask */
+	temp = GTREGREAD (GALMPSC_0_INT_MASK);
+	temp |= BIT6;
+	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
+}
+#endif
+
+char mpsc_getchar_debug (void)
+{
+	volatile int temp;
+	volatile unsigned int cause;
+
+	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	while ((cause & BIT6) == 0) {
+		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	}
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
+			  (CHANNEL * GALMPSC_REG_GAP));
+	/* By writing 1's to the set bits, the register is cleared */
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
+	return (temp >> 16) & 0xff;
+}
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int mpsc_putchar_early (char ch)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int mpsc = CHANNEL;
+	int temp =
+		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	galmpsc_set_tcschar (mpsc, ch);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
+		      temp | 0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay (MAGIC_FACTOR / gd->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int mpsc_putchar_sdma (char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset ((void *) p, 0, 8 * sizeof (unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;		/* x */
+	p[5] = (unsigned int) ch;	/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;	/* 0 */
+	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
+	p[2] = 0;		/* 8 */
+	p[3] = (unsigned int) &p[4];	/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int) &p[0];
+	p[11] = (unsigned int) &p[12];
+#endif
+
+	FLUSH_DCACHE (&p[0], &p[8]);
+
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	while (p[1] & DESC_OWNER_BIT) {
+		udelay (100);
+		INVALIDATE_DCACHE (&p[1], &p[2]);
+	}
+	return 0;
+}
+
+char mpsc_getchar_sdma (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER_BIT) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
+					  (CHANNEL * GALMPSC_REG_GAP));
+			temp |= (1 << 23);
+			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
+				      (CHANNEL * GALMPSC_REG_GAP), temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+
+int mpsc_test_char_debug (void)
+{
+	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
+		return 0;
+	else {
+		return 1;
+	}
+}
+
+
+int mpsc_test_char_sdma (void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER_BIT)
+		return 0;
+	else
+		return 1;
+}
+
+int mpsc_init (int baud)
+{
+	/* BRG CONFIG */
+	galbrg_set_baudrate (CHANNEL, baud);
+	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
+	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
+	galbrg_enable (CHANNEL);	/* Enable BRG */
+
+	/* Set up clock routing */
+	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
+
+	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
+	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
+
+	/* reset MPSC state */
+	galmpsc_shutdown (CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle (CHANNEL);
+	galsdma_set_rxle (CHANNEL);
+	galsdma_set_RC (CHANNEL, 0xf);
+	galsdma_set_SFM (CHANNEL);
+	galsdma_set_RFT (CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs (CHANNEL);
+	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
+	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
+	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+	mpsc_debug_init ();
+#endif
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
+#else
+	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
+#endif
+
+	return 0;
+}
+
+
+void mpsc_sdma_init (void)
+{
+/* Setup SDMA channel0 SDMA_CONFIG_REG*/
+	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
+
+/*  Enable MPSC-Window0 for DRAM Bank0   */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_0_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK0)) != true)
+		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window1    */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_1_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window2 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_2_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window3 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_3_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
+			__FUNCTION__);
+
+/*  Setup MPSC0 access mode Window0 full access */
+	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/*  Setup MPSC1 access mode Window1 full access */
+	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/* Setup MPSC internal address space base address 	*/
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+
+/* no high address remap*/
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
+
+/* clear interrupt cause register for MPSC (fault register)*/
+	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
+}
+
+
+void mpsc_init2 (void)
+{
+	int i;
+
+#ifndef CONFIG_MPSC_DEBUG_PORT
+	mpsc_putchar = mpsc_putchar_sdma;
+	mpsc_getchar = mpsc_getchar_sdma;
+	mpsc_test_char = mpsc_test_char_sdma;
+#endif
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset ((void *) rx_desc_base, 0,
+		(RX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
+		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
+		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
+		rx_desc_base[i * 8] = 0x00100000;
+	}
+	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
+
+	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset ((void *) tx_desc_base, 0,
+		(TX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 3] =
+			(unsigned int) &tx_desc_base[i * 8 + 4];
+		tx_desc_base[i * 8 + 2] =
+			(unsigned int) &tx_desc_base[(i + 1) * 8];
+		tx_desc_base[i * 8 + 1] =
+			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i * 8] = 0x00010001;
+	}
+	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
+
+	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
+
+	udelay (100);
+
+	galsdma_enable_rx ();
+
+	return;
+}
+
+int galbrg_set_baudrate (int channel, int rate)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int clock;
+
+	galbrg_disable (channel);	/*ok */
+
+#ifdef ZUMA_NTL
+	/* from tclk */
+	clock = (CFG_TCLK / (16 * rate)) - 1;
+#else
+	clock = (CFG_TCLK / (16 * rate)) - 1;
+#endif
+
+	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
+
+	galbrg_enable (channel);
+
+	gd->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int galbrg_set_CDV (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_enable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x00010000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_disable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_set_clksrc (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
+	temp |= (value << 18);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+	return 0;
+}
+
+static int galbrg_set_CUV (int channel, int value)
+{
+	/* set CountUpValue */
+	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int galbrg_reset (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int galsdma_set_RFT (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_SFM (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_rxle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_txle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_RC (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_burstsize (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	case 8:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x3 << 12)));
+		break;
+
+	case 4:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x2 << 12)));
+		break;
+
+	case 2:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x1 << 12)));
+		break;
+
+	case 1:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x0 << 12)));
+		break;
+
+	default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int galmpsc_connect (int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_rx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_tx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_write_config_regs (int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
+			      0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
+			      0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int galmpsc_config_channel_regs (int mpsc)
+{
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt (mpsc, 0x3);
+	galmpsc_set_tcschar (mpsc, 0xab);
+
+	return 0;
+}
+
+static int galmpsc_set_brkcnt (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_tcschar (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_char_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_stop_bit_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFBFFF;
+	temp |= (value << 14);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_parity (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_enter_hunt (int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= 0x80000000;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
+	       MPSC_ENTER_HUNT) {
+		udelay (1);
+	}
+	return 0;
+}
+
+
+static int galmpsc_shutdown (int mpsc)
+{
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
+	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
+
+	udelay (100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
+
+	udelay (100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
+
+	udelay (100);
+
+	return 0;
+}
+
+static void galsdma_enable_rx (void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt (CHANNEL);
+}
+
+static int galmpsc_set_snoop (int mpsc, int value)
+{
+	int reg =
+		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
+		MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp = GTREGREAD (reg);
+
+	if (value)
+		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
+	else
+		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
+	GT_REG_WRITE (reg, temp);
+	return 0;
+}
+
+/*******************************************************************************
+* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
+*
+* DESCRIPTION:
+*       the MV64360 SDMA has its own address decoding map that is de-coupled
+*       from the CPU interface address decoding windows. The SDMA channels
+*       share four address windows. Each region can be individually configured
+*       by this function by associating it to a target interface and setting
+*       base and size values.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*       The size must be a series of 1s followed by a series of zeros
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       True for success, false otherwise.
+*
+*******************************************************************************/
+
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress, unsigned int size)
+{
+	unsigned int temp;
+
+	if (size == 0) {
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+		return true;
+	}
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size < 0x10000) {
+		return false;
+	}
+
+	/* Align size and base to 64K */
+	baseAddress &= 0xffff0000;
+	size &= 0xffff0000;
+	temp = size >> 16;
+
+	/* Checking that the size is a sequence of '1' followed by a
+	   sequence of '0' starting from LSB to MSB. */
+	while ((temp > 0) && (temp & 0x1)) {
+		temp = temp >> 1;
+	}
+
+	if (temp != 0) {
+		GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+	} else {
+		/* An invalid size was specified */
+		return false;
+	}
+	return true;
+}
diff --git a/board/Marvell/db64360/mpsc.h b/board/Marvell/db64360/mpsc.h
new file mode 100755
index 0000000..f95f8c0
--- /dev/null
+++ b/board/Marvell/db64360/mpsc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT 		  (1 << 15)
+#define SDMA_TX_ABORT 		  (1 << 31)
+#define MPSC_TX_ABORT 		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c
new file mode 100755
index 0000000..3c5dee7
--- /dev/null
+++ b/board/Marvell/db64360/mv_eth.c
@@ -0,0 +1,3183 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.c - header file for the polled mode GT ethernet driver
+ */
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+
+#include "mv_eth.h"
+
+/* enable Debug outputs */
+
+#undef DEBUG_MV_ETH
+
+#ifdef DEBUG_MV_ETH
+#define DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#undef MV64360_CHECKSUM_OFFLOAD
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+/* Definition for configuring driver */
+/* #define UPDATE_STATS_BY_SOFTWARE */
+#undef MV64360_RX_QUEUE_FILL_ON_TASK
+
+
+/* Constants */
+#define MAGIC_ETH_RUNNING		8031971
+#define MV64360_INTERNAL_SRAM_SIZE                      _256K
+#define EXTRA_BYTES 32
+#define WRAP       ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#ifdef MV64360_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL		0x00000000
+#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Read/Write to/from MV64360 internal registers */
+#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
+#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
+#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
+#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
+
+/* Static function declarations */
+static int mv64360_eth_real_open (struct eth_device *eth);
+static int mv64360_eth_real_stop (struct eth_device *eth);
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
+						       *dev);
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
+static void mv64360_eth_update_stat (struct eth_device *dev);
+bool db64360_eth_start (struct eth_device *eth);
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset);
+int mv64360_eth_receive (struct eth_device *dev);
+
+int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+static void mv64360_eth_print_stat (struct eth_device *dev);
+#endif
+/* Processes a received packet */
+extern void NetReceive (volatile uchar *, int);
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/*************************************************
+ *Helper functions - used inside the driver only *
+ *************************************************/
+#ifdef DEBUG_MV_ETH
+void print_globals (struct eth_device *dev)
+{
+	printf ("Ethernet PRINT_Globals-Debug function\n");
+	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
+		(unsigned int) dev->priv);
+	printf ("Base Address for mv64360_eth_priv:	%08x\n",
+		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
+				 port_private));
+
+	printf ("GT Internal Base Address:	%08x\n",
+		INTERNAL_REG_BASE_ADDR);
+	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
+	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
+	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_rx_buffer_base[0],
+		(MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
+	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_tx_buffer_base[0],
+		(MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
+}
+#endif
+
+#define my_cpu_to_le32(x) my_le32_to_cpu((x))
+
+unsigned long my_le32_to_cpu (unsigned long x)
+{
+	return (((x & 0x000000ffU) << 24) |
+		((x & 0x0000ff00U) << 8) |
+		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
+}
+
+
+/**********************************************************************
+ * mv64360_eth_print_phy_status
+ *
+ * Prints gigabit ethenret phy status
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_phy_status (struct eth_device *dev)
+{
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	unsigned int port_status, phy_reg_data;
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		printf ("Ethernet port changed link status to DOWN\n");
+	} else {
+		port_status =
+			MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+		printf ("Ethernet status port %d: Link up", port_num);
+		printf (", %s",
+			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
+		if (port_status & BIT4)
+			printf (", Speed 1 Gbps");
+		else
+			printf (", %s",
+				(port_status & BIT5) ? "Speed 100 Mbps" :
+				"Speed 10 Mbps");
+		printf ("\n");
+	}
+}
+
+/**********************************************************************
+ * u-boot entry functions for mv64360_eth
+ *
+ **********************************************************************/
+int db64360_eth_probe (struct eth_device *dev)
+{
+	return ((int) db64360_eth_start (dev));
+}
+
+int db64360_eth_poll (struct eth_device *dev)
+{
+	return mv64360_eth_receive (dev);
+}
+
+int db64360_eth_transmit (struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	mv64360_eth_xmit (dev, packet, length);
+	return 0;
+}
+
+void db64360_eth_disable (struct eth_device *dev)
+{
+	mv64360_eth_stop (dev);
+}
+
+
+void mv6436x_eth_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
+		dev = calloc (sizeof (*dev), 1);
+		if (!dev) {
+			printf ("%s: mv_enet%d allocation failure, %s\n",
+				__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf (dev->name, "mv_enet%d", devnum);
+
+#ifdef DEBUG
+		printf ("Initializing %s\n", dev->name);
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_r (s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		/* ronen - set the MAC addr in the HW */
+		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
+
+		dev->init = (void *) db64360_eth_probe;
+		dev->halt = (void *) ethernet_phy_reset;
+		dev->send = (void *) db64360_eth_transmit;
+		dev->recv = (void *) db64360_eth_poll;
+
+		ethernet_private = calloc (sizeof (*ethernet_private), 1);
+		dev->priv = (void *) ethernet_private;
+
+		if (!ethernet_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Private Device Structure");
+			free (dev);
+			return;
+		}
+		/* start with an zeroed ETH_PORT_INFO */
+		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
+		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+		/* set pointer to memory for stats data structure etc... */
+		port_private = calloc (sizeof (*ethernet_private), 1);
+		ethernet_private->port_private = (void *)port_private;
+		if (!port_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Port Private Device Structure");
+
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+
+		port_private->stats =
+			calloc (sizeof (struct net_device_stats), 1);
+		if (!port_private->stats) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Net stat Structure");
+
+			free (port_private);
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+		memset (ethernet_private->port_private, 0,
+			sizeof (struct mv64360_eth_priv));
+		switch (devnum) {
+		case 0:
+			ethernet_private->port_num = ETH_0;
+			break;
+		case 1:
+			ethernet_private->port_num = ETH_1;
+			break;
+		case 2:
+			ethernet_private->port_num = ETH_2;
+			break;
+		default:
+			printf ("Invalid device number %d\n", devnum);
+			break;
+		};
+
+		port_private->port_num = devnum;
+		/*
+		 * Read MIB counter on the GT in order to reset them,
+		 * then zero all the stats fields in memory
+		 */
+		mv64360_eth_update_stat (dev);
+		memset (port_private->stats, 0,
+			sizeof (struct net_device_stats));
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_r (s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+
+		DP (printf ("Allocating descriptor and buffer rings\n"));
+
+		ethernet_private->p_rx_desc_area_base[0] =
+			(ETH_RX_DESC *) memalign (16,
+						  RX_DESC_ALIGNED_SIZE *
+						  MV64360_RX_QUEUE_SIZE + 1);
+		ethernet_private->p_tx_desc_area_base[0] =
+			(ETH_TX_DESC *) memalign (16,
+						  TX_DESC_ALIGNED_SIZE *
+						  MV64360_TX_QUEUE_SIZE + 1);
+
+		ethernet_private->p_rx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+		ethernet_private->p_tx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+
+#ifdef DEBUG_MV_ETH
+		/* DEBUG OUTPUT prints adresses of globals */
+		print_globals (dev);
+#endif
+		eth_register (dev);
+
+	}
+	DP (printf ("%s: exit\n", __FUNCTION__));
+
+}
+
+/**********************************************************************
+ * mv64360_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ * / / ronen - changed the output to match  net/eth.c needs
+ * Output : nonzero of success , zero if fails.
+ * under construction
+ **********************************************************************/
+
+int mv64360_eth_open (struct eth_device *dev)
+{
+	return (mv64360_eth_real_open (dev));
+}
+
+/* Helper function for mv64360_eth_open */
+static int mv64360_eth_real_open (struct eth_device *dev)
+{
+
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	u32 port_status, phy_reg_data;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	/* ronen - when we update the MAC env params we only update dev->enetaddr
+	   see ./net/eth.c eth_set_enetaddr() */
+	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Clear the ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+
+	/* Unmask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL);
+
+	/* Unmask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL_EXT);
+
+	/* Set phy address of the port */
+	ethernet_private->port_phy_addr = 0x8 + port_num;
+
+	/* Activate the DMA channels etc */
+	eth_port_init (ethernet_private);
+
+
+	/* "Allocate" setup TX rings */
+
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
+		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
+		ethernet_private->tx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
+			0, ethernet_private->tx_desc_area_size[queue]);
+
+		/* initialize tx desc ring with low level driver */
+		if (ether_init_tx_desc_ring
+		    (ethernet_private, ETH_Q0,
+		     port_private->tx_ring_size[queue],
+		     MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		     (unsigned int) ethernet_private->
+		     p_tx_desc_area_base[queue],
+		     (unsigned int) ethernet_private->
+		     p_tx_buffer_base[queue]) == false)
+			printf ("### Error initializing TX Ring\n");
+	}
+
+	/* "Allocate" setup RX rings */
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		/* Meantime RX Ring are fixed - but must be configurable by user */
+		port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
+		size = (port_private->rx_ring_size[queue] *
+			RX_DESC_ALIGNED_SIZE);
+		ethernet_private->rx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
+			0, ethernet_private->rx_desc_area_size[queue]);
+		if ((ether_init_rx_desc_ring
+		     (ethernet_private, ETH_Q0,
+		      port_private->rx_ring_size[queue],
+		      MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		      (unsigned int) ethernet_private->
+		      p_rx_desc_area_base[queue],
+		      (unsigned int) ethernet_private->
+		      p_rx_buffer_base[queue])) == false)
+			printf ("### Error initializing RX Ring\n");
+	}
+
+	eth_port_start (ethernet_private);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
+		      (0x5 << 17) |
+		      (MV_REG_READ
+		       (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
+		       & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
+	port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		/* Reset PHY */
+		if ((ethernet_phy_reset (port_num)) != true) {
+			printf ("$$ Warnning: No link on port %d \n",
+				port_num);
+			return 0;
+		} else {
+			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+			if (!(phy_reg_data & 0x20)) {
+				printf ("### Error: Phy is not active\n");
+				return 0;
+			}
+		}
+	} else {
+		mv64360_eth_print_phy_status (dev);
+	}
+	port_private->eth_running = MAGIC_ETH_RUNNING;
+	return 1;
+}
+
+
+static int mv64360_eth_free_tx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop Tx Queues */
+	MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free TX rings */
+	DP (printf ("Clearing previously allocated TX queues... "));
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		/* Free on TX rings */
+		for (p_tx_curr_desc =
+		     ethernet_private->p_tx_desc_area_base[queue];
+		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
+		      ethernet_private->p_tx_desc_area_base[queue] +
+		      ethernet_private->tx_desc_area_size[queue]);
+		     p_tx_curr_desc =
+		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
+				      TX_DESC_ALIGNED_SIZE)) {
+			/* this is inside for loop */
+			if (p_tx_curr_desc->return_info != 0) {
+				p_tx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+static int mv64360_eth_free_rx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free RX rings */
+	DP (printf ("Clearing previously allocated RX queues... "));
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		/* Free preallocated skb's on RX rings */
+		for (p_rx_curr_desc =
+		     ethernet_private->p_rx_desc_area_base[queue];
+		     (((unsigned int) p_rx_curr_desc <
+		       ((unsigned int) ethernet_private->
+			p_rx_desc_area_base[queue] +
+			ethernet_private->rx_desc_area_size[queue])));
+		     p_rx_curr_desc =
+		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
+				      RX_DESC_ALIGNED_SIZE)) {
+			if (p_rx_curr_desc->return_info != 0) {
+				p_rx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+/**********************************************************************
+ * mv64360_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ *********************************************************************/
+
+int mv64360_eth_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Disable all gigE address decoder */
+	MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
+	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
+	mv64360_eth_real_stop (dev);
+
+	return 0;
+};
+
+/* Helper function for mv64360_eth_stop */
+
+static int mv64360_eth_real_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	mv64360_eth_free_tx_rings (dev);
+	mv64360_eth_free_rx_rings (dev);
+
+	eth_port_reset (ethernet_private->port_num);
+	/* Disable ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+	/* Mask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
+	/* Mask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
+	MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
+			   BIT0 << port_num);
+	/* Print Network statistics */
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+	/*
+	 * Print statistics (only if ethernet is running),
+	 * then zero all the stats fields in memory
+	 */
+	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
+		port_private->eth_running = 0;
+		mv64360_eth_print_stat (dev);
+	}
+	memset (port_private->stats, 0, sizeof (struct net_device_stats));
+#endif
+	DP (printf ("\nEthernet stopped ... \n"));
+	return 0;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ *         dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ **********************************************************************/
+
+int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
+		      int dataSize)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	ETH_FUNC_RET_STATUS status;
+	struct net_device_stats *stats;
+	ETH_FUNC_RET_STATUS release_result;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	stats = port_private->stats;
+
+	/* Update packet info data structure */
+	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
+	pkt_info.byte_cnt = dataSize;
+	pkt_info.buf_ptr = (unsigned int) dataPtr;
+
+	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
+	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
+		printf ("Error on transmitting packet ..");
+		if (status == ETH_QUEUE_FULL)
+			printf ("ETH Queue is full. \n");
+		if (status == ETH_QUEUE_LAST_RESOURCE)
+			printf ("ETH Queue: using last available resource. \n");
+		goto error;
+	}
+
+	/* Update statistics and start of transmittion time */
+	stats->tx_bytes += dataSize;
+	stats->tx_packets++;
+
+	/* Check if packet(s) is(are) transmitted correctly (release everything) */
+	do {
+		release_result =
+			eth_tx_return_desc (ethernet_private, ETH_Q0,
+					    &pkt_info);
+		switch (release_result) {
+		case ETH_OK:
+			DP (printf ("descriptor released\n"));
+			if (pkt_info.cmd_sts & BIT0) {
+				printf ("Error in TX\n");
+				stats->tx_errors++;
+
+			}
+			break;
+		case ETH_RETRY:
+			DP (printf ("transmission still in process\n"));
+			break;
+
+		case ETH_ERROR:
+			printf ("routine can not access Tx desc ring\n");
+			break;
+
+		case ETH_END_OF_JOB:
+			DP (printf ("the routine has nothing to release\n"));
+			break;
+		default:	/* should not happen */
+			break;
+		}
+	} while (release_result == ETH_OK);
+
+
+	return 0;		/* success */
+      error:
+	return 1;		/* Failed - higher layers will free the skb */
+}
+
+/**********************************************************************
+ * mv64360_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ *         max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ **********************************************************************/
+
+int mv64360_eth_receive (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	struct net_device_stats *stats;
+
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
+		ETH_OK)) {
+
+#ifdef DEBUG_MV_ETH
+		if (pkt_info.byte_cnt != 0) {
+			printf ("%s: Received %d byte Packet @ 0x%x\n",
+				__FUNCTION__, pkt_info.byte_cnt,
+				pkt_info.buf_ptr);
+		}
+#endif
+		/* Update statistics. Note byte count includes 4 byte CRC count */
+		stats->rx_packets++;
+		stats->rx_bytes += pkt_info.byte_cnt;
+
+		/*
+		 * In case received a packet without first / last bits on OR the error
+		 * summary bit is on, the packets needs to be dropeed.
+		 */
+		if (((pkt_info.
+		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+			stats->rx_dropped++;
+
+			printf ("Received packet spread on multiple descriptors\n");
+
+			/* Is this caused by an error ? */
+			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
+				stats->rx_errors++;
+			}
+
+			/* free these descriptors again without forwarding them to the higher layers */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+			/* /free these descriptors again */
+		} else {
+
+/* !!! call higher layer processing */
+#ifdef DEBUG_MV_ETH
+			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
+#endif
+			/* let the upper layer handle the packet */
+			NetReceive ((uchar *) pkt_info.buf_ptr,
+				    (int) pkt_info.byte_cnt);
+
+/* **************************************************************** */
+/* free descriptor  */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+			DP (printf
+			    ("RX: pkt_info.buf_ptr =	%x\n",
+			     pkt_info.buf_ptr));
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+
+/* **************************************************************** */
+
+		}
+	}
+	mv64360_eth_get_stats (dev);	/* update statistics */
+	return 1;
+}
+
+/**********************************************************************
+ * mv64360_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ **********************************************************************/
+
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64360_eth_update_stat (dev);
+
+	return port_private->stats;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_update_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_update_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+	volatile unsigned int dummy;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	stats->rx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_RECEIVED);
+	stats->tx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_SENT);
+	stats->rx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
+	/*
+	 * Ideally this should be as follows -
+	 *
+	 *   stats->rx_bytes   += stats->rx_bytes +
+	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
+	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
+	 *
+	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
+	 * is just a dummy read for proper work of the GigE port
+	 */
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
+	stats->tx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
+	stats->rx_errors += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MAC_RECEIVE_ERROR);
+
+	/* Rx dropped is for received packet with CRC error */
+	stats->rx_dropped +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_BAD_CRC_EVENT);
+	stats->multicast += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
+	stats->collisions +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_COLLISION) +
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_LATE_COLLISION);
+	/* detailed rx errors */
+	stats->rx_length_errors +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_UNDERSIZE_RECEIVED)
+		+
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_OVERSIZE_RECEIVED);
+	/* detailed tx errors */
+}
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+/**********************************************************************
+ * mv64360_eth_print_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	printf ("\n### Network statistics: ###\n");
+	printf ("--------------------------\n");
+	printf (" Packets received:		%ld\n", stats->rx_packets);
+	printf (" Packets send:			%ld\n", stats->tx_packets);
+	printf (" Received bytes:		%ld\n", stats->rx_bytes);
+	printf (" Send bytes:			%ld\n", stats->tx_bytes);
+	if (stats->rx_errors != 0)
+		printf (" Rx Errors:			%ld\n",
+			stats->rx_errors);
+	if (stats->rx_dropped != 0)
+		printf (" Rx dropped (CRC Errors):	%ld\n",
+			stats->rx_dropped);
+	if (stats->multicast != 0)
+		printf (" Rx mulicast frames:		%ld\n",
+			stats->multicast);
+	if (stats->collisions != 0)
+		printf (" No. of collisions:		%ld\n",
+			stats->collisions);
+	if (stats->rx_length_errors != 0)
+		printf (" Rx length errors:		%ld\n",
+			stats->rx_length_errors);
+}
+#endif
+
+/**************************************************************************
+ *network_start - Network Kick Off Routine UBoot
+ *Inputs :
+ *Outputs :
+ **************************************************************************/
+
+bool db64360_eth_start (struct eth_device *dev)
+{
+	return (mv64360_eth_open (dev));	/* calls real open */
+}
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/*
+ * based on Linux code
+ * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ */
+
+/********************************************************************************
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ *       This file introduce low level API to Marvell's Gigabit Ethernet
+ *		controller. This Gigabit Ethernet Controller driver API controls
+ *		1) Operations (i.e. port init, start, reset etc').
+ *		2) Data flow (i.e. port send, receive etc').
+ *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
+ *		struct.
+ *		This struct includes user configuration information as well as
+ *		driver internal data needed for its operations.
+ *
+ *		Supported Features:
+ *		- This low level driver is OS independent. Allocating memory for
+ *		  the descriptor rings and buffers are not within the scope of
+ *		  this driver.
+ *		- The user is free from Rx/Tx queue managing.
+ *		- This low level driver introduce functionality API that enable
+ *		  the to operate Marvell's Gigabit Ethernet Controller in a
+ *		  convenient way.
+ *		- Simple Gigabit Ethernet port operation API.
+ *		- Simple Gigabit Ethernet port data flow API.
+ *		- Data flow and operation API support per queue functionality.
+ *		- Support cached descriptors for better performance.
+ *		- Enable access to all four DRAM banks and internal SRAM memory
+ *		  spaces.
+ *		- PHY access and control API.
+ *		- Port control register configuration API.
+ *		- Full control over Unicast and Multicast MAC configurations.
+ *
+ *		Operation flow:
+ *
+ *		Initialization phase
+ *		This phase complete the initialization of the ETH_PORT_INFO
+ *		struct.
+ *		User information regarding port configuration has to be set
+ *		prior to calling the port initialization routine. For example,
+ *		the user has to assign the port_phy_addr field which is board
+ *		depended parameter.
+ *		In this phase any port Tx/Rx activity is halted, MIB counters
+ *		are cleared, PHY address is set according to user parameter and
+ *		access to DRAM and internal SRAM memory spaces.
+ *
+ *		Driver ring initialization
+ *		Allocating memory for the descriptor rings and buffers is not
+ *		within the scope of this driver. Thus, the user is required to
+ *		allocate memory for the descriptors ring and buffers. Those
+ *		memory parameters are used by the Rx and Tx ring initialization
+ *		routines in order to curve the descriptor linked list in a form
+ *		of a ring.
+ *		Note: Pay special attention to alignment issues when using
+ *		cached descriptors/buffers. In this phase the driver store
+ *		information in the ETH_PORT_INFO struct regarding each queue
+ *		ring.
+ *
+ *		Driver start
+ *		This phase prepares the Ethernet port for Rx and Tx activity.
+ *		It uses the information stored in the ETH_PORT_INFO struct to
+ *		initialize the various port registers.
+ *
+ *		Data flow:
+ *		All packet references to/from the driver are done using PKT_INFO
+ *		struct.
+ *		This struct is a unified struct used with Rx and Tx operations.
+ *		This way the user is not required to be familiar with neither
+ *		Tx nor Rx descriptors structures.
+ *		The driver's descriptors rings are management by indexes.
+ *		Those indexes controls the ring resources and used to indicate
+ *		a SW resource error:
+ *		'current'
+ *		This index points to the current available resource for use. For
+ *		example in Rx process this index will point to the descriptor
+ *		that will be passed to the user upon calling the receive routine.
+ *		In Tx process, this index will point to the descriptor
+ *		that will be assigned with the user packet info and transmitted.
+ *		'used'
+ *		This index points to the descriptor that need to restore its
+ *		resources. For example in Rx process, using the Rx buffer return
+ *		API will attach the buffer returned in packet info to the
+ *		descriptor pointed by 'used'. In Tx process, using the Tx
+ *		descriptor return will merely return the user packet info with
+ *		the command status of  the transmitted buffer pointed by the
+ *		'used' index. Nevertheless, it is essential to use this routine
+ *		to update the 'used' index.
+ *		'first'
+ *		This index supports Tx Scatter-Gather. It points to the first
+ *		descriptor of a packet assembled of multiple buffers. For example
+ *		when in middle of Such packet we have a Tx resource error the
+ *		'curr' index get the value of 'first' to indicate that the ring
+ *		returned to its state before trying to transmit this packet.
+ *
+ *		Receive operation:
+ *		The eth_port_receive API set the packet information struct,
+ *		passed by the caller, with received information from the
+ *		'current' SDMA descriptor.
+ *		It is the user responsibility to return this resource back
+ *		to the Rx descriptor ring to enable the reuse of this source.
+ *		Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ *		Transmit operation:
+ *		The eth_port_send API supports Scatter-Gather which enables to
+ *		send a packet spanned over multiple buffers. This means that
+ *		for each packet info structure given by the user and put into
+ *		the Tx descriptors ring, will be transmitted only if the 'LAST'
+ *		bit will be set in the packet info command status field. This
+ *		API also consider restriction regarding buffer alignments and
+ *		sizes.
+ *		The user must return a Tx resource after ensuring the buffer
+ *		has been transmitted to enable the Tx ring indexes to update.
+ *
+ *		BOARD LAYOUT
+ *		This device is on-board.  No jumper diagram is necessary.
+ *
+ *		EXTERNAL INTERFACE
+ *
+ *       Prior to calling the initialization routine eth_port_init() the user
+ *	 must set the following fields under ETH_PORT_INFO struct:
+ *       port_num             User Ethernet port number.
+ *       port_phy_addr		    User PHY address of Ethernet port.
+ *       port_mac_addr[6]	    User defined port MAC address.
+ *       port_config          User port configuration value.
+ *       port_config_extend    User port config extend value.
+ *       port_sdma_config      User port SDMA config value.
+ *       port_serial_control   User port serial control value.
+ *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
+ *       *port_private        User scratch pad for user specific data structures.
+ *
+ *       This driver introduce a set of default values:
+ *       PORT_CONFIG_VALUE           Default port configuration value
+ *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
+ *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
+ *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
+ *
+ *		This driver data flow is done using the PKT_INFO struct which is
+ *		a unified struct for Rx and Tx operations:
+ *		byte_cnt	Tx/Rx descriptor buffer byte count.
+ *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
+ *		cmd_sts		Tx/Rx descriptor command status.
+ *		buf_ptr		Tx/Rx descriptor buffer pointer.
+ *		return_info	Tx/Rx user resource return information.
+ *
+ *
+ *		EXTERNAL SUPPORT REQUIREMENTS
+ *
+ *		This driver requires the following external support:
+ *
+ *		D_CACHE_FLUSH_LINE (address, address offset)
+ *
+ *		This macro applies assembly code to flush and invalidate cache
+ *		line.
+ *		address        - address base.
+ *		address offset - address offset
+ *
+ *
+ *		CPU_PIPE_FLUSH
+ *
+ *		This macro applies assembly code to flush the CPU pipeline.
+ *
+ *******************************************************************************/
+/* includes */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
+
+#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
+ (1 << (8 + tx_queue)))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
+
+#define CURR_RFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
+
+#define CURR_RFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_RFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
+
+#define USED_RFD_SET(p_used_desc, queue)\
+(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
+
+
+#define CURR_TFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
+
+#define CURR_TFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_TFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
+
+#define USED_TFD_SET(p_used_desc, queue) \
+ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
+
+#define FIRST_TFD_GET(p_first_desc, queue) \
+ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
+
+#define FIRST_TFD_SET(p_first_desc, queue) \
+ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
+
+
+/* Macros that save access to desc in order to find next desc pointer  */
+#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
+
+#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
+
+#define LINK_UP_TIMEOUT		100000
+#define PHY_BUSY_TIMEOUT    10000000
+
+/* locals */
+
+/* PHY routines */
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
+static int ethernet_phy_get (ETH_PORT eth_port_num);
+
+/* Ethernet Port routines */
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param);
+static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option);
+#if 0				/* FIXME */
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option);
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option);
+#endif
+
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count);
+
+void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
+
+
+typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
+u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_dram_bank_size (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_SIZE);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_SIZE);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_SIZE);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_SIZE);
+	result += 1;
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_internal_sram_base (void)
+{
+	u32 result;
+
+	result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+/*******************************************************************************
+* eth_port_init - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+*       This function prepares the ethernet port to start its activity:
+*       1) Completes the ethernet port driver struct initialization toward port
+*           start routine.
+*       2) Resets the device to a quiescent state in case of warm reboot.
+*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+*       4) Clean MAC tables. The reset status of those tables is unknown.
+*       5) Set PHY address.
+*       Note: Call this routine prior to eth_port_start routine and after setting
+*       user values in the user fields of Ethernet port control struct (i.e.
+*       port_phy_addr).
+*
+* INPUT:
+*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       See description.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	ETH_WIN_PARAM win_param;
+
+	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
+	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+	p_eth_port_ctrl->port_rx_queue_command = 0;
+	p_eth_port_ctrl->port_tx_queue_command = 0;
+
+	/* Zero out SW structs */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->rx_resource_err[queue] = false;
+	}
+
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->tx_resource_err[queue] = false;
+	}
+
+	eth_port_reset (p_eth_port_ctrl->port_num);
+
+	/* Set access parameters for DRAM bank 0 */
+	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
+	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
+	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 1 */
+	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
+	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 2 */
+	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
+	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 3 */
+	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
+	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for Internal SRAM */
+	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
+	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
+	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
+	win_param.high_addr = 0;
+	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
+	win_param.size = MV64360_INTERNAL_SRAM_SIZE;	/* Get bank size */
+	win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
+
+	ethernet_phy_set (p_eth_port_ctrl->port_num,
+			  p_eth_port_ctrl->port_phy_addr);
+
+	return;
+
+}
+
+/*******************************************************************************
+* eth_port_start - Start the Ethernet port activity.
+*
+* DESCRIPTION:
+*       This routine prepares the Ethernet port for Rx and Tx activity:
+*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
+*           for Tx and ether_init_rx_desc_ring for Rx)
+*       2. Initialize and enable the Ethernet configuration port by writing to
+*           the port's configuration and command registers.
+*       3. Initialize and enable the SDMA by writing to the SDMA's
+*    configuration and command registers.
+*       After completing these steps, the ethernet port SDMA can starts to
+*       perform Rx and Tx activities.
+*
+*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
+*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
+*       ether_init_rx_desc_ring for Rx queues).
+*
+* INPUT:
+*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       Ethernet port is ready to receive and transmit.
+*
+* RETURN:
+*       false if the port PHY is not up.
+*       true otherwise.
+*
+*******************************************************************************/
+static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	unsigned int phy_reg_data;
+	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
+
+
+	/* Assignment of Tx CTRP of given queue */
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_GET (p_tx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_tx_curr_desc));
+
+	}
+
+	/* Assignment of Rx CRDP of given queue */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_GET (p_rx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_rx_curr_desc));
+
+		if (p_rx_curr_desc != NULL)
+			/* Add the assigned Ethernet address to the port's address table */
+			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
+					      p_eth_port_ctrl->port_mac_addr,
+					      queue);
+	}
+
+	/* Assign port configuration and command. */
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config_extend);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      p_eth_port_ctrl->port_serial_control);
+
+	MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+			 ETH_SERIAL_PORT_ENABLE);
+
+	/* Assign port SDMA configuration */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_sdma_config);
+
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
+		      (eth_port_num), 0x3fffffff);
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
+		      (eth_port_num), 0x03fffcff);
+	/* Turn off the port/queue bandwidth limitation */
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
+
+	/* Enable port Rx. */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_rx_queue_command);
+
+	/* Check if link is up */
+	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+	if (!(phy_reg_data & 0x20))
+		return false;
+
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr_set - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+*		This function Set the port Ethernet MAC address.
+*
+* INPUT:
+*	ETH_PORT eth_port_num     Port number.
+*	char *        p_addr		Address to be set
+*	ETH_QUEUE 	  queue		Rx queue number for this MAC address.
+*
+* OUTPUT:
+*	Set MAC address low and high registers. also calls eth_port_uc_addr()
+*       To set the unicast table with the proper information.
+*
+* RETURN:
+*	N/A.
+*
+*******************************************************************************/
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr, ETH_QUEUE queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+		(p_addr[2] << 8) | (p_addr[3] << 0);
+
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
+
+	/* Accept frames of this address */
+	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
+
+	return;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+*	This function locates the proper entry in the Unicast table for the
+*	specified MAC nibble and sets its properties according to function
+*	parameters.
+*
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char uc_nibble		Unicast MAC Address last nibble.
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	This function add/removes MAC addresses from the port unicast address
+*	table.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_uc_addr (ETH_PORT eth_port_num,
+			      unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
+	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified unicast DA table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+#if 0				/* FIXME */
+/*******************************************************************************
+* eth_port_mc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This API controls the MV device MAC multicast support.
+*	The MV device supports multicast using two tables:
+*	1) Special Multicast Table for MAC addresses of the form
+*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	   Table entries in the DA-Filter table.
+*	   In this case, the function calls eth_port_smc_addr() routine to set the
+*	   Special Multicast Table.
+*	2) Other Multicast Table for multicast of another type. A CRC-8bit
+*	   is used as an index to the Other Multicast Table entries in the
+*	   DA-Filter table.
+*	   In this case, the function calculates the CRC-8bit value and calls
+*	   eth_port_omc_addr() routine to set the Other Multicast Table.
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char 	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if add_address_table_entry( ) failed.
+*
+*******************************************************************************/
+static void eth_port_mc_addr (ETH_PORT eth_port_num,
+			      unsigned char *p_addr,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+	unsigned char crc_result = 0;
+	int mac_array[48];
+	int crc[8];
+	int i;
+
+
+	if ((p_addr[0] == 0x01) &&
+	    (p_addr[1] == 0x00) &&
+	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
+
+		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
+	else {
+		/* Calculate CRC-8 out of the given address */
+		mac_h = (p_addr[0] << 8) | (p_addr[1]);
+		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
+			(p_addr[4] << 8) | (p_addr[5] << 0);
+
+		for (i = 0; i < 32; i++)
+			mac_array[i] = (mac_l >> i) & 0x1;
+		for (i = 32; i < 48; i++)
+			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
+
+
+		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
+			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
+			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
+			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
+			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
+			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[0];
+
+		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
+			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
+			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
+			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
+			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
+			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
+			mac_array[0];
+
+		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
+			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
+			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
+			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
+			mac_array[2] ^ mac_array[1] ^ mac_array[0];
+
+		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
+			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
+			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
+			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
+			mac_array[2] ^ mac_array[1];
+
+		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
+			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
+			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
+			mac_array[2];
+
+		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
+			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
+			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
+			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
+			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
+			mac_array[3];
+
+		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
+			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
+			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
+			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[6] ^ mac_array[5] ^ mac_array[4];
+
+		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
+			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
+			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
+			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
+			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[5];
+
+		for (i = 0; i < 8; i++)
+			crc_result = crc_result | (crc[i] << i);
+
+		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
+	}
+	return;
+}
+
+/*******************************************************************************
+* eth_port_smc_addr - Special Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device special MAC multicast support.
+*	The Special Multicast Table for MAC addresses supports MAC of the form
+*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	Table entries in the DA-Filter table.
+*	This function set the Special Multicast Table appropriate entry
+*	according to the argument given.
+*
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char 	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int smc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the SMC table entry */
+	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
+	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_omc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device Other MAC multicast support.
+*	The Other Multicast Table is used for multicast of another type.
+*	A CRC-8bit is used as an index to the Other Multicast Table entries
+*	in the DA-Filter table.
+*	The function gets the CRC-8bit value from the calling routine and
+*      set the Other Multicast Table appropriate entry according to the
+*	CRC-8 argument given.
+*
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char 	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int omc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the OMC table entry */
+	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
+	reg_offset = crc8 % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+#endif
+
+/*******************************************************************************
+* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+*
+* DESCRIPTION:
+*       Go through all the DA filter tables (Unicast, Special Multicast & Other
+*       Multicast) and set each entry to 0.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Multicast and Unicast packets are rejected.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index <= 0xC; table_index += 4)
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num) + table_index), 0);
+
+	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+	}
+}
+
+/*******************************************************************************
+* eth_clear_mib_counters - Clear all MIB counters
+*
+* DESCRIPTION:
+*       This function clears all MIB counters of a specific ethernet port.
+*       A read from the MIB counter will reset the counter.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       After reading all MIB counters, the counters resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+static void eth_clear_mib_counters (ETH_PORT eth_port_num)
+{
+	int i;
+	unsigned int dummy;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
+	     i += 4)
+		dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
+				      (eth_port_num) + i));
+
+	return;
+}
+
+/*******************************************************************************
+* eth_read_mib_counter - Read a MIB counter
+*
+* DESCRIPTION:
+*       This function reads a MIB counter of a specific ethernet port.
+*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
+*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
+*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
+*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
+*
+* OUTPUT:
+*       After reading the MIB counter, the counter resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset)
+{
+	return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
+			     + mib_offset));
+}
+
+/*******************************************************************************
+* ethernet_phy_set - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+*       This routine set the ethernet port PHY address according to given
+*       parameter.
+*
+* INPUT:
+*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Set PHY Address Register with given PHY address parameter.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	reg_data &= ~(0x1F << (5 * eth_port_num));
+	reg_data |= (phy_addr << (5 * eth_port_num));
+
+	MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
+
+	return;
+}
+
+/*******************************************************************************
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ *       This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       PHY address.
+ *
+ *******************************************************************************/
+static int ethernet_phy_get (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/*******************************************************************************
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to reset the ethernet port PHY.
+ *       The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ *       None.
+ *
+*******************************************************************************/
+static bool ethernet_phy_reset (ETH_PORT eth_port_num)
+{
+	unsigned int time_out = 50;
+	unsigned int phy_reg_data;
+
+	/* Reset the PHY */
+	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
+	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
+	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
+
+	/* Poll on the PHY LINK */
+	do {
+		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+		if (time_out-- == 0)
+			return false;
+	}
+	while (!(phy_reg_data & 0x20));
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ * 	This routine resets the chip by aborting any SDMA engine activity and
+ *      clearing the MIB counters. The Receiver and the Transmit unit are in
+ *      idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       Channel activity is halted.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_port_reset (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Tx activity to terminate. */
+		do {
+			/* Check port cause register that all Tx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Rx activity to terminate. */
+		do {
+			/* Check port cause register that all Rx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+
+	/* Clear all MIB counters */
+	eth_clear_mib_counters (eth_port_num);
+
+	/* Reset the Enable bit in the Configuration Register */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
+			     (eth_port_num));
+	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      reg_data);
+
+	return;
+}
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function sets specified bits in the given ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are set in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_set_config_reg (ETH_PORT eth_port_num,
+				     unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg =
+		MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
+	eth_config_reg |= value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* FIXME */
+/*******************************************************************************
+ * ethernet_reset_config_reg - Reset specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function resets specified bits in the given Ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are reset in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
+				       unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	eth_config_reg &= ~value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ *       This function returns the configuration register value of the given
+ *       ethernet port.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       Port configuration register value.
+ *
+ *******************************************************************************/
+static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	return eth_config_reg;
+}
+
+#endif
+
+/*******************************************************************************
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform PHY register read.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       unsigned int   phy_reg   PHY register address offset.
+ *       unsigned int   *value   Register value buffer.
+ *
+ * OUTPUT:
+ *       Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ *       false if the PHY is busy or read data is not in valid state.
+ *       true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
+				   unsigned int phy_reg, unsigned int *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+#define PHY_UPDATE_TIMEOUT	10000
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform writes to PHY registers.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int   phy_reg   PHY register address offset.
+ *      unsigned int    value   Register value.
+ *
+ * OUTPUT:
+ *      Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ *      false if the PHY is busy.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
+				    unsigned int phy_reg, unsigned int value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return true;
+}
+
+/*******************************************************************************
+ * eth_set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * DESCRIPTION:
+ *       This function configures the address decode parameters for the Gigabit
+ *       Ethernet Controller according the given parameters struct.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       ETH_WIN_PARAM  *param   Address decode parameter struct.
+ *
+ * OUTPUT:
+ *       An access window is opened using the given access parameters.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param)
+{
+	unsigned int access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
+				       (eth_port_num));
+	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
+		      access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
+		       (ETH_SIZE_REG_GAP * param->win)),
+		      (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
+		      (param->target | param->attributes | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
+			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
+			      param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				   (1 << param->win));
+	else
+		MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				 (1 << param->win));
+}
+
+/*******************************************************************************
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Rx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *      int 			rx_desc_num       Number of Rx descriptors
+ *      int 			rx_buff_size      Size of Rx buffer
+ *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
+ *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE rx_queue,
+				     int rx_desc_num,
+				     int rx_buff_size,
+				     unsigned int rx_desc_base_addr,
+				     unsigned int rx_buff_base_addr)
+{
+	ETH_RX_DESC *p_rx_desc;
+	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
+	p_rx_prev_desc = p_rx_desc;
+	buffer_addr = rx_buff_base_addr;
+
+	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (rx_buff_base_addr & 0xF)
+		return false;
+
+	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+		return false;
+
+	/* Rx buffers must be 64-bit aligned.       */
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return false;
+
+	/* initialize the Rx descriptors ring */
+	for (ix = 0; ix < rx_desc_num; ix++) {
+		p_rx_desc->buf_size = rx_buff_size;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->cmd_sts =
+			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+		p_rx_desc->next_desc_ptr =
+			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
+		p_rx_desc->buf_ptr = buffer_addr;
+		p_rx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
+		buffer_addr += rx_buff_size;
+		p_rx_prev_desc = p_rx_desc;
+		p_rx_desc = (ETH_RX_DESC *)
+			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
+	}
+
+	/* Closing Rx descriptors ring */
+	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
+	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
+
+	/* Save Rx desc pointer to driver struct. */
+	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+
+	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
+		(ETH_RX_DESC *) rx_desc_base_addr;
+	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
+		rx_desc_num * RX_DESC_ALIGNED_SIZE;
+
+	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Tx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *      int 			tx_desc_num       Number of Tx descriptors
+ *      int 			tx_buff_size      Size of Tx buffer
+ *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
+ *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE tx_queue,
+				     int tx_desc_num,
+				     int tx_buff_size,
+				     unsigned int tx_desc_base_addr,
+				     unsigned int tx_buff_base_addr)
+{
+
+	ETH_TX_DESC *p_tx_desc;
+	ETH_TX_DESC *p_tx_prev_desc;
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	/* save the first desc pointer to link with the last descriptor */
+	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
+	p_tx_prev_desc = p_tx_desc;
+	buffer_addr = tx_buff_base_addr;
+
+	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (tx_buff_base_addr & 0xF)
+		return false;
+
+	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
+	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
+		return false;
+
+	/* Initialize the Tx descriptors ring */
+	for (ix = 0; ix < tx_desc_num; ix++) {
+		p_tx_desc->byte_cnt = 0x0000;
+		p_tx_desc->l4i_chk = 0x0000;
+		p_tx_desc->cmd_sts = 0x00000000;
+		p_tx_desc->next_desc_ptr =
+			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
+
+		p_tx_desc->buf_ptr = buffer_addr;
+		p_tx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
+		buffer_addr += tx_buff_size;
+		p_tx_prev_desc = p_tx_desc;
+		p_tx_desc = (ETH_TX_DESC *)
+			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
+
+	}
+	/* Closing Tx descriptors ring */
+	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
+	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
+	/* Set Tx desc pointer in driver struct. */
+	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+
+	/* Init Tx ring base and size parameters */
+	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
+		(ETH_TX_DESC *) tx_desc_base_addr;
+	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
+		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
+
+	/* Add the queue to the list of Tx queues of this port */
+	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ *	This routine send a given packet described by p_pktinfo parameter. It
+ *      supports transmitting of a packet spaned over multiple buffers. The
+ *      routine updates 'curr' and 'first' indexes according to the packet
+ *      segment passed to the routine. In case the packet segment is first,
+ *      the 'first' index is update. In any case, the 'curr' index is updated.
+ *      If the routine get into Tx resource error it assigns 'curr' index as
+ *      'first'. This way the function can abort Tx process of multiple
+ *      descriptors per packet.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ *      ETH_QUEUE_FULL in case of Tx resource error.
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
+					  ETH_QUEUE tx_queue,
+					  PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_first;
+	volatile ETH_TX_DESC *p_tx_desc_curr;
+	volatile ETH_TX_DESC *p_tx_next_desc_curr;
+	volatile ETH_TX_DESC *p_tx_desc_used;
+	unsigned int command_status;
+
+	/* Do not process Tx ring in case of Tx ring resource error */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		return ETH_QUEUE_FULL;
+
+	/* Get the Tx Desc ring indexes */
+	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+
+	if (p_tx_desc_curr == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
+	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+	if (command_status & (ETH_TX_FIRST_DESC)) {
+		/* Update first desc */
+		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
+		p_tx_desc_first = p_tx_desc_curr;
+	} else {
+		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+		command_status |= ETH_BUFFER_OWNED_BY_DMA;
+	}
+
+	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
+	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
+	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
+	if (p_pkt_info->byte_cnt <= 8) {
+		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
+		return ETH_ERROR;
+
+		p_tx_desc_curr->buf_ptr =
+			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
+		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
+			    p_pkt_info->byte_cnt);
+	} else
+		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
+
+	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
+	p_tx_desc_curr->return_info = p_pkt_info->return_info;
+
+	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
+		/* Set last desc with DMA ownership and interrupt enable. */
+		p_tx_desc_curr->cmd_sts = command_status |
+			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+		if (p_tx_desc_curr != p_tx_desc_first)
+			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+
+		/* Flush CPU pipe */
+
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
+		CPU_PIPE_FLUSH;
+
+		/* Apply send command */
+		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
+
+		/* Finish Tx packet. Update first desc in case of Tx resource error */
+		p_tx_desc_first = p_tx_next_desc_curr;
+		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
+
+	} else {
+		p_tx_desc_curr->cmd_sts = command_status;
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+	}
+
+	/* Check for ring index overlap in the Tx desc ring */
+	if (p_tx_next_desc_curr == p_tx_desc_used) {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_desc_first, tx_queue);
+
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
+		return ETH_QUEUE_LAST_RESOURCE;
+	} else {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
+		return ETH_OK;
+	}
+}
+
+/*******************************************************************************
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ *	This routine returns the transmitted packet information to the caller.
+ *      It uses the 'first' index to support Tx desc return in case a transmit
+ *      of a packet spanned over multiple buffer still in process.
+ *      In case the Tx queue was in "resource error" condition, where there are
+ *      no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *      ETH_RETRY in case there is transmission in process.
+ *	ETH_END_OF_JOB if the routine has nothing to release.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE tx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
+	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
+	unsigned int command_status;
+
+
+	/* Get the Tx Desc ring indexes */
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+
+
+	/* Sanity check */
+	if (p_tx_desc_used == NULL)
+		return ETH_ERROR;
+
+	command_status = p_tx_desc_used->cmd_sts;
+
+	/* Still transmitting... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_RETRY;
+	}
+
+	/* Stop release. About to overlap the current available Tx descriptor */
+	if ((p_tx_desc_used == p_tx_desc_first) &&
+	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_END_OF_JOB;
+	}
+
+	/* Pass the packet information to the caller */
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->return_info = p_tx_desc_used->return_info;
+	p_tx_desc_used->return_info = 0;
+
+	/* Update the next descriptor to release. */
+	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
+
+	/* Any Tx return cancels the Tx resource error status */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+
+	return ETH_OK;
+
+}
+
+/*******************************************************************************
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ * 	This routine returns the received data to the caller. There is no
+ *	data copying during routine operation. All information is returned
+ *	using pointer to packet information struct passed from the caller.
+ *      If the routine exhausts	Rx ring resources then the resource error flag
+ *      is set.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ *	ETH_END_OF_JOB if there is no received data.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_next_curr_desc;
+	volatile ETH_RX_DESC *p_rx_used_desc;
+	unsigned int command_status;
+
+	/* Do not process Rx ring in case of Rx ring resource error */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
+		printf ("\nRx Queue is full ...\n");
+		return ETH_QUEUE_FULL;
+	}
+
+	/* Get the Rx Desc ring 'curr and 'used' indexes */
+	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
+	USED_RFD_GET (p_rx_used_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_rx_curr_desc == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
+	command_status = p_rx_curr_desc->cmd_sts;
+
+	/* Nothing to receive... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+/* 	DP(printf("Rx: command_status: %08x\n", command_status)); */
+		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
+		return ETH_END_OF_JOB;
+	}
+
+	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
+	p_pkt_info->return_info = p_rx_curr_desc->return_info;
+	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
+
+	/* Clean the return info field to indicate that the packet has been */
+	/* moved to the upper layers                                        */
+	p_rx_curr_desc->return_info = 0;
+
+	/* Update 'curr' in data structure */
+	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
+
+	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
+	if (p_rx_next_curr_desc == p_rx_used_desc)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+	CPU_PIPE_FLUSH;
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ *      next 'used' descriptor and attached the returned buffer to it.
+ *      In case the Rx ring was in "resource error" condition, where there are
+ *      no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
+ *
+ * OUTPUT:
+ *	New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE rx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
+
+	/* Get 'used' Rx descriptor */
+	USED_RFD_GET (p_used_rx_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_used_rx_desc == NULL)
+		return ETH_ERROR;
+
+	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+	p_used_rx_desc->return_info = p_pkt_info->return_info;
+	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
+	p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE;	/* Reset Buffer size */
+
+	/* Flush the write pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Return the descriptor to DMA ownership */
+	p_used_rx_desc->cmd_sts =
+		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+	/* Flush descriptor and CPU pipe */
+	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	/* Move the used descriptor pointer to the next descriptor */
+	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
+
+	/* Any Rx return cancels the Rx resource error status */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the RX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the tClk of the MV-643xx chip
+ *	, and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in usec
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set RX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      ((coal & 0x3fff) << 8) |
+		      (MV_REG_READ
+		       (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
+		       & 0xffc000ff));
+	return coal;
+}
+
+#endif
+/*******************************************************************************
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the TX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the t_cLK frequency of the
+ *	MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in uSeconds
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set TX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
+		      coal << 4);
+	return coal;
+}
+#endif
+
+/*******************************************************************************
+ * eth_b_copy - Copy bytes from source to destination
+ *
+ * DESCRIPTION:
+ *       This function supports the eight bytes limitation on Tx buffer size.
+ *       The routine will zero eight bytes starting from the destination address
+ *       followed by copying bytes from the source address to the destination.
+ *
+ * INPUT:
+ *       unsigned int src_addr    32 bit source address.
+ *       unsigned int dst_addr    32 bit destination address.
+ *       int        byte_count    Number of bytes to copy.
+ *
+ * OUTPUT:
+ *       See description.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count)
+{
+	/* Zero the dst_addr area */
+	*(unsigned int *) dst_addr = 0x0;
+
+	while (byte_count != 0) {
+		*(char *) dst_addr = *(char *) src_addr;
+		dst_addr++;
+		src_addr++;
+		byte_count--;
+	}
+}
diff --git a/board/Marvell/db64360/mv_eth.h b/board/Marvell/db64360/mv_eth.h
new file mode 100755
index 0000000..943d30b
--- /dev/null
+++ b/board/Marvell/db64360/mv_eth.h
@@ -0,0 +1,844 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64360_ETH_H__
+#define __DB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include "../common/ppc_error_no.h"
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64360_TX_QUEUE_NUM 1
+#define MV64360_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#else
+#define MV64360_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#else
+#define MV64360_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64360_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64360_TX_BUFFER_SIZE 1600
+#endif
+
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64360_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+/* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+};
+
+
+int mv64360_eth_init (struct eth_device *dev);
+int mv64360_eth_stop (struct eth_device *dev);
+int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64360_eth0_poll(); */
+
+int mv64360_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64360_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64360_ETH_ */
diff --git a/board/Marvell/db64360/mv_regs.h b/board/Marvell/db64360/mv_regs.h
new file mode 100755
index 0000000..0d6370b
--- /dev/null
+++ b/board/Marvell/db64360/mv_regs.h
@@ -0,0 +1,1124 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/********************************************************************************
+* gt64360r.h - GT-64360 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_regsh
+#define __INCmv_regsh
+
+#define MV64360
+
+/* Supported by the Atlantis */
+#define MV64360_INCLUDE_PCI_1
+#define MV64360_INCLUDE_PCI_0_ARBITER
+#define MV64360_INCLUDE_PCI_1_ARBITER
+#define MV64360_INCLUDE_SNOOP_SUPPORT
+#define MV64360_INCLUDE_P2P
+#define MV64360_INCLUDE_ETH_PORT_2
+#define MV64360_INCLUDE_CPU_MAPPING
+#define MV64360_INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64360_CS_0_BASE_ADDR					    0x008
+#define MV64360_CS_0_SIZE					    0x010
+#define MV64360_CS_1_BASE_ADDR					    0x208
+#define MV64360_CS_1_SIZE					    0x210
+#define MV64360_CS_2_BASE_ADDR					    0x018
+#define MV64360_CS_2_SIZE					    0x020
+#define MV64360_CS_3_BASE_ADDR					    0x218
+#define MV64360_CS_3_SIZE					    0x220
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64360_PCI_0_IO_BASE_ADDR				    0x048
+#define MV64360_PCI_0_IO_SIZE					    0x050
+#define MV64360_PCI_0_MEMORY0_BASE_ADDR				    0x058
+#define MV64360_PCI_0_MEMORY0_SIZE				    0x060
+#define MV64360_PCI_0_MEMORY1_BASE_ADDR				    0x080
+#define MV64360_PCI_0_MEMORY1_SIZE				    0x088
+#define MV64360_PCI_0_MEMORY2_BASE_ADDR				    0x258
+#define MV64360_PCI_0_MEMORY2_SIZE				    0x260
+#define MV64360_PCI_0_MEMORY3_BASE_ADDR				    0x280
+#define MV64360_PCI_0_MEMORY3_SIZE				    0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64360_PCI_1_IO_BASE_ADDR				    0x090
+#define MV64360_PCI_1_IO_SIZE					    0x098
+#define MV64360_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
+#define MV64360_PCI_1_MEMORY0_SIZE				    0x0a8
+#define MV64360_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
+#define MV64360_PCI_1_MEMORY1_SIZE				    0x0b8
+#define MV64360_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
+#define MV64360_PCI_1_MEMORY2_SIZE				    0x2a8
+#define MV64360_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
+#define MV64360_PCI_1_MEMORY3_SIZE				    0x2b8
+
+/* SRAM base address */
+#define MV64360_INTEGRATED_SRAM_BASE_ADDR			    0x268
+
+/* internal registers space base address */
+#define MV64360_INTERNAL_SPACE_BASE_ADDR			    0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define MV64360_BASE_ADDR_ENABLE				    0x278
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+      /* PCI 0 */
+#define MV64360_PCI_0_IO_ADDR_REMAP				    0x0f0
+#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
+#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
+#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
+#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
+#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
+#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
+#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
+#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
+      /* PCI 1 */
+#define MV64360_PCI_1_IO_ADDR_REMAP				    0x108
+#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
+#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
+#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
+#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
+#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
+#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
+#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
+#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
+
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
+#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
+#define MV64360_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+
+#define MV64360_CPU_CONFIG					    0x000
+#define MV64360_CPU_MODE					    0x120
+#define MV64360_CPU_MASTER_CONTROL				    0x160
+#define MV64360_CPU_CROSS_BAR_CONTROL_LOW			    0x150
+#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
+#define MV64360_CPU_CROSS_BAR_TIMEOUT				    0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define MV64360_SMP_WHO_AM_I					    0x200
+#define MV64360_SMP_CPU0_DOORBELL				    0x214
+#define MV64360_SMP_CPU0_DOORBELL_CLEAR				    0x21C
+#define MV64360_SMP_CPU1_DOORBELL				    0x224
+#define MV64360_SMP_CPU1_DOORBELL_CLEAR				    0x22C
+#define MV64360_SMP_CPU0_DOORBELL_MASK				    0x234
+#define MV64360_SMP_CPU1_DOORBELL_MASK				    0x23C
+#define MV64360_SMP_SEMAPHOR0					    0x244
+#define MV64360_SMP_SEMAPHOR1					    0x24c
+#define MV64360_SMP_SEMAPHOR2					    0x254
+#define MV64360_SMP_SEMAPHOR3					    0x25c
+#define MV64360_SMP_SEMAPHOR4					    0x264
+#define MV64360_SMP_SEMAPHOR5					    0x26c
+#define MV64360_SMP_SEMAPHOR6					    0x274
+#define MV64360_SMP_SEMAPHOR7					    0x27c
+
+/****************************************/
+/*  CPU Sync Barrier Register		*/
+/****************************************/
+
+#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
+#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
+#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
+#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
+#define MV64360_CPU_PROTECT_WINDOW_0_SIZE			    0x188
+#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
+#define MV64360_CPU_PROTECT_WINDOW_1_SIZE			    0x198
+#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
+#define MV64360_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
+#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
+#define MV64360_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
+
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define MV64360_CPU_ERROR_ADDR_LOW				    0x070
+#define MV64360_CPU_ERROR_ADDR_HIGH				    0x078
+#define MV64360_CPU_ERROR_DATA_LOW				    0x128
+#define MV64360_CPU_ERROR_DATA_HIGH				    0x130
+#define MV64360_CPU_ERROR_PARITY				    0x138
+#define MV64360_CPU_ERROR_CAUSE					    0x140
+#define MV64360_CPU_ERROR_MASK					    0x148
+
+/****************************************/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define MV64360_PUNIT_SLAVE_DEBUG_LOW				    0x360
+#define MV64360_PUNIT_SLAVE_DEBUG_HIGH				    0x368
+#define MV64360_PUNIT_MASTER_DEBUG_LOW				    0x370
+#define MV64360_PUNIT_MASTER_DEBUG_HIGH				    0x378
+#define MV64360_PUNIT_MMASK					    0x3e4
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define MV64360_SRAM_CONFIG					    0x380
+#define MV64360_SRAM_TEST_MODE					    0X3F4
+#define MV64360_SRAM_ERROR_CAUSE				    0x388
+#define MV64360_SRAM_ERROR_ADDR					    0x390
+#define MV64360_SRAM_ERROR_ADDR_HIGH				    0X3F8
+#define MV64360_SRAM_ERROR_DATA_LOW				    0x398
+#define MV64360_SRAM_ERROR_DATA_HIGH				    0x3a0
+#define MV64360_SRAM_ERROR_DATA_PARITY				    0x3a8
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+#define MV64360_SDRAM_CONFIG					    0x1400
+#define MV64360_D_UNIT_CONTROL_LOW				    0x1404
+#define MV64360_D_UNIT_CONTROL_HIGH				    0x1424
+#define MV64360_SDRAM_TIMING_CONTROL_LOW			    0x1408
+#define MV64360_SDRAM_TIMING_CONTROL_HIGH			    0x140c
+#define MV64360_SDRAM_ADDR_CONTROL				    0x1410
+#define MV64360_SDRAM_OPEN_PAGES_CONTROL			    0x1414
+#define MV64360_SDRAM_OPERATION					    0x1418
+#define MV64360_SDRAM_MODE					    0x141c
+#define MV64360_EXTENDED_DRAM_MODE				    0x1420
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
+#define MV64360_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
+#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
+#define MV64360_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define MV64360_SDRAM_ERROR_DATA_LOW				    0x1444
+#define MV64360_SDRAM_ERROR_DATA_HIGH				    0x1440
+#define MV64360_SDRAM_ERROR_ADDR				    0x1450
+#define MV64360_SDRAM_RECEIVED_ECC				    0x1448
+#define MV64360_SDRAM_CALCULATED_ECC				    0x144c
+#define MV64360_SDRAM_ECC_CONTROL				    0x1454
+#define MV64360_SDRAM_ECC_ERROR_COUNTER				    0x1458
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64360_DFCDL_CONFIG0					    0x1480
+#define MV64360_DFCDL_CONFIG1					    0x1484
+#define MV64360_DLL_WRITE					    0x1488
+#define MV64360_DLL_READ					    0x148c
+#define MV64360_SRAM_ADDR					    0x1490
+#define MV64360_SRAM_DATA0					    0x1494
+#define MV64360_SRAM_DATA1					    0x1498
+#define MV64360_SRAM_DATA2					    0x149c
+#define MV64360_DFCL_PROBE					    0x14a0
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define MV64360_DUNIT_DEBUG_LOW					    0x1460
+#define MV64360_DUNIT_DEBUG_HIGH				    0x1464
+#define MV64360_DUNIT_MMASK					    0X1b40
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define MV64360_DEVICE_BANK0_PARAMETERS				    0x45c
+#define MV64360_DEVICE_BANK1_PARAMETERS				    0x460
+#define MV64360_DEVICE_BANK2_PARAMETERS				    0x464
+#define MV64360_DEVICE_BANK3_PARAMETERS				    0x468
+#define MV64360_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
+#define MV64360_DEVICE_INTERFACE_CONTROL			    0x4c0
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
+
+/****************************************/
+/* Device interrupt registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_INTERRUPT_CAUSE				    0x4d0
+#define MV64360_DEVICE_INTERRUPT_MASK				    0x4d4
+#define MV64360_DEVICE_ERROR_ADDR				    0x4d8
+#define MV64360_DEVICE_ERROR_DATA				    0x4dc
+#define MV64360_DEVICE_ERROR_PARITY				    0x4e0
+
+/****************************************/
+/* Device debug registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_DEBUG_LOW				    0x4e4
+#define MV64360_DEVICE_DEBUG_HIGH				    0x4e8
+#define MV64360_RUNIT_MMASK					    0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64360_PCI_0_CS_0_BANK_SIZE				    0xc08
+#define MV64360_PCI_1_CS_0_BANK_SIZE				    0xc88
+#define MV64360_PCI_0_CS_1_BANK_SIZE				    0xd08
+#define MV64360_PCI_1_CS_1_BANK_SIZE				    0xd88
+#define MV64360_PCI_0_CS_2_BANK_SIZE				    0xc0c
+#define MV64360_PCI_1_CS_2_BANK_SIZE				    0xc8c
+#define MV64360_PCI_0_CS_3_BANK_SIZE				    0xd0c
+#define MV64360_PCI_1_CS_3_BANK_SIZE				    0xd8c
+#define MV64360_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
+#define MV64360_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
+#define MV64360_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
+#define MV64360_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
+#define MV64360_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
+#define MV64360_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
+#define MV64360_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
+#define MV64360_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
+#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
+#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
+#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
+#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
+#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
+#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
+#define MV64360_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
+#define MV64360_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
+#define MV64360_PCI_0_CPU_BAR_SIZE				    0xd28
+#define MV64360_PCI_1_CPU_BAR_SIZE				    0xda8
+#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
+#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
+#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
+#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
+#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
+#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
+#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
+#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
+#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
+#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
+#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
+#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
+#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
+#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
+#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
+#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
+#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
+#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
+#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
+#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
+#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
+#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
+#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
+#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
+#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
+#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
+#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
+#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
+#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
+#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
+#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
+#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
+#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
+#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
+#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
+#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
+#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
+#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
+#define MV64360_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
+#define MV64360_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
+#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
+#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
+#define MV64360_PCI_0_HEADERS_RETARGET_BASE			    0xF44
+#define MV64360_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
+#define MV64360_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
+#define MV64360_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
+
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
+#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
+#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
+#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
+#define MV64360_PCI_0_COMMAND					    0xc00
+#define MV64360_PCI_1_COMMAND					    0xc80
+#define MV64360_PCI_0_MODE					    0xd00
+#define MV64360_PCI_1_MODE					    0xd80
+#define MV64360_PCI_0_RETRY					    0xc04
+#define MV64360_PCI_1_RETRY					    0xc84
+#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
+#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MV64360_PCI_0_MSI_TRIGGER_TIMER				    0xc38
+#define MV64360_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
+#define MV64360_PCI_0_ARBITER_CONTROL				    0x1d00
+#define MV64360_PCI_1_ARBITER_CONTROL				    0x1d80
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
+#define MV64360_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
+#define MV64360_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
+#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
+#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
+#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
+#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
+#define MV64360_PCI_0_P2P_CONFIG				    0x1d14
+#define MV64360_PCI_1_P2P_CONFIG				    0x1d94
+
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
+
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64360_PCI_0_CONFIG_ADDR				    0xcf8
+#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
+#define MV64360_PCI_1_CONFIG_ADDR				    0xc78
+#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
+#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
+#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_SERR_MASK					    0xc28
+#define MV64360_PCI_1_SERR_MASK					    0xca8
+#define MV64360_PCI_0_ERROR_ADDR_LOW				    0x1d40
+#define MV64360_PCI_1_ERROR_ADDR_LOW				    0x1dc0
+#define MV64360_PCI_0_ERROR_ADDR_HIGH				    0x1d44
+#define MV64360_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
+#define MV64360_PCI_0_ERROR_ATTRIBUTE				    0x1d48
+#define MV64360_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
+#define MV64360_PCI_0_ERROR_COMMAND				    0x1d50
+#define MV64360_PCI_1_ERROR_COMMAND				    0x1dd0
+#define MV64360_PCI_0_ERROR_CAUSE				    0x1d58
+#define MV64360_PCI_1_ERROR_CAUSE				    0x1dd8
+#define MV64360_PCI_0_ERROR_MASK				    0x1d5c
+#define MV64360_PCI_1_ERROR_MASK				    0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_MMASK					    0X1D24
+#define MV64360_PCI_1_MMASK					    0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define MV64360_PCI_DEVICE_AND_VENDOR_ID			    0x000
+#define MV64360_PCI_STATUS_AND_COMMAND				    0x004
+#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
+#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
+
+#define MV64360_PCI_SCS_0_BASE_ADDR_LOW				    0x010
+#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
+#define MV64360_PCI_SCS_1_BASE_ADDR_LOW				    0x018
+#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
+#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
+#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
+#define MV64360_PCI_CAPABILTY_LIST_POINTER			    0x034
+#define MV64360_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
+       /* capability list */
+#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define MV64360_PCI_VPD_ADDR					    0x048
+#define MV64360_PCI_VPD_DATA					    0x04c
+#define MV64360_PCI_MSI_MESSAGE_CONTROL				    0x050
+#define MV64360_PCI_MSI_MESSAGE_ADDR				    0x054
+#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
+#define MV64360_PCI_MSI_MESSAGE_DATA				    0x05c
+#define MV64360_PCI_X_COMMAND					    0x060
+#define MV64360_PCI_X_STATUS					    0x064
+#define MV64360_PCI_COMPACT_PCI_HOT_SWAP			    0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define MV64360_PCI_SCS_2_BASE_ADDR_LOW				    0x110
+#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
+#define MV64360_PCI_SCS_3_BASE_ADDR_LOW				    0x118
+#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
+#define MV64360_PCI_CPU_BASE_ADDR_LOW				    0x220
+#define MV64360_PCI_CPU_BASE_ADDR_HIGH				    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
+#define MV64360_PCI_P2P_I_O_BASE_ADDR				    0x420
+#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define MV64360_ETH_PHY_ADDR_REG				    0x2000
+#define MV64360_ETH_SMI_REG					    0x2004
+#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
+#define MV64360_ETH_UNIT_DEFAULTID_REG				    0x200c
+#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
+#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
+#define MV64360_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
+#define MV64360_ETH_UNIT_ERROR_ADDR_REG				    0x2094
+#define MV64360_ETH_BAR_0					    0x2200
+#define MV64360_ETH_BAR_1					    0x2208
+#define MV64360_ETH_BAR_2					    0x2210
+#define MV64360_ETH_BAR_3					    0x2218
+#define MV64360_ETH_BAR_4					    0x2220
+#define MV64360_ETH_BAR_5					    0x2228
+#define MV64360_ETH_SIZE_REG_0					    0x2204
+#define MV64360_ETH_SIZE_REG_1					    0x220c
+#define MV64360_ETH_SIZE_REG_2					    0x2214
+#define MV64360_ETH_SIZE_REG_3					    0x221c
+#define MV64360_ETH_SIZE_REG_4					    0x2224
+#define MV64360_ETH_SIZE_REG_5					    0x222c
+#define MV64360_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
+#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
+#define MV64360_ETH_BASE_ADDR_ENABLE_REG			    0x2290
+#define MV64360_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
+#define MV64360_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
+#define MV64360_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
+#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
+#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
+#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
+#define MV64360_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
+#define MV64360_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
+#define MV64360_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
+#define MV64360_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
+#define MV64360_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
+#define MV64360_ETH_DSCP_3(port)				   (0x242c + (port<<10))
+#define MV64360_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
+#define MV64360_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
+#define MV64360_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
+#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
+#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
+#define MV64360_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
+#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
+#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
+#define MV64360_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
+#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
+#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
+#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
+#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
+#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
+#define MV64360_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
+#define MV64360_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
+#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
+#define MV64360_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
+#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
+#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
+#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define MV64360_CUNIT_BASE_ADDR_REG0				    0xf200
+#define MV64360_CUNIT_BASE_ADDR_REG1				    0xf208
+#define MV64360_CUNIT_BASE_ADDR_REG2				    0xf210
+#define MV64360_CUNIT_BASE_ADDR_REG3				    0xf218
+#define MV64360_CUNIT_SIZE0					    0xf204
+#define MV64360_CUNIT_SIZE1					    0xf20c
+#define MV64360_CUNIT_SIZE2					    0xf214
+#define MV64360_CUNIT_SIZE3					    0xf21c
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
+#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
+#define MV64360_MPSC0_ACCESS_PROTECTION_REG			    0xf254
+#define MV64360_MPSC1_ACCESS_PROTECTION_REG			    0xf258
+#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
+
+	/*  Error Report Registers  */
+
+#define MV64360_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
+#define MV64360_CUNIT_INTERRUPT_MASK_REG			    0xf314
+#define MV64360_CUNIT_ERROR_ADDR				    0xf318
+
+	/*  Cunit Control Registers */
+
+#define MV64360_CUNIT_ARBITER_CONTROL_REG			    0xf300
+#define MV64360_CUNIT_CONFIG_REG				    0xb40c
+#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define MV64360_CUNIT_DEBUG_LOW					    0xf340
+#define MV64360_CUNIT_DEBUG_HIGH				    0xf344
+#define MV64360_CUNIT_MMASK					    0xf380
+
+	/*  Cunit Base Address Enable Window Bits*/
+#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
+#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
+#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
+#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MV64360_MPSC_ROUTING_REG				    0xb400
+#define MV64360_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
+#define MV64360_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MV64360_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
+#define MV64360_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
+
+#define MV64360_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
+#define MV64360_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
+#define MV64360_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
+
+	/*  MPSC0 Registers	 */
+
+
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define MV64360_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
+#define MV64360_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
+#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
+#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define MV64360_SDMA_CAUSE_REG					    0xb800
+#define MV64360_SDMA_MASK_REG					    0xb880
+
+
+/****************************************/
+/* SDMA Address Space Targets		*/
+/****************************************/
+
+#define MV64360_SDMA_DRAM_CS_0_TARGET				    0x0e00
+#define MV64360_SDMA_DRAM_CS_1_TARGET				    0x0d00
+#define MV64360_SDMA_DRAM_CS_2_TARGET				    0x0b00
+#define MV64360_SDMA_DRAM_CS_3_TARGET				    0x0700
+
+#define MV64360_SDMA_DEV_CS_0_TARGET				    0x1e01
+#define MV64360_SDMA_DEV_CS_1_TARGET				    0x1d01
+#define MV64360_SDMA_DEV_CS_2_TARGET				    0x1b01
+#define MV64360_SDMA_DEV_CS_3_TARGET				    0x1701
+
+#define MV64360_SDMA_BOOT_CS_TARGET				    0x0f00
+
+#define MV64360_SDMA_SRAM_TARGET				    0x0003
+#define MV64360_SDMA_60X_BUS_TARGET				    0x4003
+
+#define MV64360_PCI_0_TARGET					    0x0003
+#define MV64360_PCI_1_TARGET					    0x0004
+
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* SDMA Window access protection */
+#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
+#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
+#define MV64360_SDMA_WIN_ACCESS_FULL 2
+
+/* BRG Interrupts */
+
+#define MV64360_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
+#define MV64360_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
+#define MV64360_BRG_CAUSE_REG					    0xb834
+#define MV64360_BRG_MASK_REG					    0xb8b4
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_CONTROL				    0x840
+#define MV64360_DMA_CHANNEL0_CONTROL_HIGH			    0x880
+#define MV64360_DMA_CHANNEL1_CONTROL				    0x844
+#define MV64360_DMA_CHANNEL1_CONTROL_HIGH			    0x884
+#define MV64360_DMA_CHANNEL2_CONTROL				    0x848
+#define MV64360_DMA_CHANNEL2_CONTROL_HIGH			    0x888
+#define MV64360_DMA_CHANNEL3_CONTROL				    0x84C
+#define MV64360_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
+
+
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_BYTE_COUNT				    0x800
+#define MV64360_DMA_CHANNEL1_BYTE_COUNT				    0x804
+#define MV64360_DMA_CHANNEL2_BYTE_COUNT				    0x808
+#define MV64360_DMA_CHANNEL3_BYTE_COUNT				    0x80C
+#define MV64360_DMA_CHANNEL0_SOURCE_ADDR			    0x810
+#define MV64360_DMA_CHANNEL1_SOURCE_ADDR			    0x814
+#define MV64360_DMA_CHANNEL2_SOURCE_ADDR			    0x818
+#define MV64360_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
+#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
+#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
+#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
+#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
+#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
+#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
+#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
+#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
+#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
+#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
+#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
+#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define MV64360_DMA_BASE_ADDR_REG0				    0xa00
+#define MV64360_DMA_BASE_ADDR_REG1				    0xa08
+#define MV64360_DMA_BASE_ADDR_REG2				    0xa10
+#define MV64360_DMA_BASE_ADDR_REG3				    0xa18
+#define MV64360_DMA_BASE_ADDR_REG4				    0xa20
+#define MV64360_DMA_BASE_ADDR_REG5				    0xa28
+#define MV64360_DMA_BASE_ADDR_REG6				    0xa30
+#define MV64360_DMA_BASE_ADDR_REG7				    0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define MV64360_DMA_SIZE_REG0					    0xa04
+#define MV64360_DMA_SIZE_REG1					    0xa0c
+#define MV64360_DMA_SIZE_REG2					    0xa14
+#define MV64360_DMA_SIZE_REG3					    0xa1c
+#define MV64360_DMA_SIZE_REG4					    0xa24
+#define MV64360_DMA_SIZE_REG5					    0xa2c
+#define MV64360_DMA_SIZE_REG6					    0xa34
+#define MV64360_DMA_SIZE_REG7					    0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
+#define MV64360_DMA_BASE_ADDR_ENABLE_REG			    0xa80
+#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
+#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
+#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
+#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
+#define MV64360_DMA_ARBITER_CONTROL				    0x860
+#define MV64360_DMA_CROSS_BAR_TIMEOUT				    0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+#define MV64360_DMA_HEADERS_RETARGET_CONTROL			    0xa84
+#define MV64360_DMA_HEADERS_RETARGET_BASE			    0xa88
+
+ /*  IDMA Interrupt Register  */
+
+#define MV64360_DMA_INTERRUPT_CAUSE_REG				    0x8c0
+#define MV64360_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
+#define MV64360_DMA_ERROR_ADDR					    0x8c8
+#define MV64360_DMA_ERROR_SELECT				    0x8cc
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define MV64360_DMA_DEBUG_LOW					    0x8e0
+#define MV64360_DMA_DEBUG_HIGH					    0x8e4
+#define MV64360_DMA_SPARE					    0xA8C
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define MV64360_TIMER_COUNTER0					    0x850
+#define MV64360_TIMER_COUNTER1					    0x854
+#define MV64360_TIMER_COUNTER2					    0x858
+#define MV64360_TIMER_COUNTER3					    0x85C
+#define MV64360_TIMER_COUNTER_0_3_CONTROL			    0x864
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
+
+/****************************************/
+/*	   Watchdog registers		*/
+/****************************************/
+
+#define MV64360_WATCHDOG_CONFIG_REG				    0xb410
+#define MV64360_WATCHDOG_VALUE_REG				    0xb414
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define MV64360_I2C_SLAVE_ADDR					    0xc000
+#define MV64360_I2C_EXTENDED_SLAVE_ADDR				    0xc010
+#define MV64360_I2C_DATA					    0xc004
+#define MV64360_I2C_CONTROL					    0xc008
+#define MV64360_I2C_STATUS_BAUDE_RATE				    0xc00C
+#define MV64360_I2C_SOFT_RESET					    0xc01c
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_GPP_IO_CONTROL					    0xf100
+#define MV64360_GPP_LEVEL_CONTROL				    0xf110
+#define MV64360_GPP_VALUE					    0xf104
+#define MV64360_GPP_INTERRUPT_CAUSE				    0xf108
+#define MV64360_GPP_INTERRUPT_MASK0				    0xf10c
+#define MV64360_GPP_INTERRUPT_MASK1				    0xf114
+#define MV64360_GPP_VALUE_SET					    0xf118
+#define MV64360_GPP_VALUE_CLEAR					    0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define MV64360_MAIN_INTERRUPT_CAUSE_LOW			    0x004
+#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
+#define MV64360_CPU_INTERRUPT0_MASK_LOW				    0x014
+#define MV64360_CPU_INTERRUPT0_MASK_HIGH			    0x01c
+#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
+#define MV64360_CPU_INTERRUPT1_MASK_LOW				    0x034
+#define MV64360_CPU_INTERRUPT1_MASK_HIGH			    0x03c
+#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
+#define MV64360_INTERRUPT0_MASK_0_LOW				    0x054
+#define MV64360_INTERRUPT0_MASK_0_HIGH				    0x05c
+#define MV64360_INTERRUPT0_SELECT_CAUSE				    0x064
+#define MV64360_INTERRUPT1_MASK_0_LOW				    0x074
+#define MV64360_INTERRUPT1_MASK_0_HIGH				    0x07c
+#define MV64360_INTERRUPT1_SELECT_CAUSE				    0x084
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_MPP_CONTROL0					    0xf000
+#define MV64360_MPP_CONTROL1					    0xf004
+#define MV64360_MPP_CONTROL2					    0xf008
+#define MV64360_MPP_CONTROL3					    0xf00c
+
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+#define MV64360_SERIAL_INIT_LAST_DATA				    0xf324
+#define MV64360_SERIAL_INIT_CONTROL				    0xf328
+#define MV64360_SERIAL_INIT_STATUS				    0xf32c
+
+
+#endif /* __INCgt64360rh */
diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c
new file mode 100755
index 0000000..5637284
--- /dev/null
+++ b/board/Marvell/db64360/pci.c
@@ -0,0 +1,940 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#include <pci.h>
+
+#include "../include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before writing
+*                      to another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before reading
+*                     from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*                               the agent is placed on another Bus. For more
+*                               information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*           GT spec (or any other PCI device spec).
+*           unsigned int pciDevNum - The device number needs to be addressed.
+*           unsigned int busNum - On which bus does the Target agent connect
+*                                 to.
+*           unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*                               the agent target locate on another PCI bus.
+*                             - Make sure the GT is configured as a master
+*                               before reading from another device on the PCI.
+*                             - The function takes care of Big/Little endian
+*                               conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec). (configuration register offset.)
+*           pciDevNum: The device number needs to be addressed.
+*           busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*           - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*                         feature bits given as an input.
+*                       - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*         unsigned int features - See file: pci.h there are defintion for those
+*                                 region features.
+*         unsigned int baseAddress - The region base Address.
+*         unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*                           to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*                      disable the park on last mechanism for each agent.
+*                      disabling this option for all agents results parking
+*                      on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*                       respond to grant assertion within a window specified in
+*                       the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*                       grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*                           Detection mechanism.
+*                           NOTE: This operation may cause a dead lock on the
+*                           pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*                 For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*                                      Boundry.
+*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*                                      Boundry.
+*          unsigned int busNum - The CPI bus number to which the PCI interface
+*                                      is connected.
+*          unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*                          supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*         snoopType - There is four optional Types:
+*                        1. No Snoop.
+*                        2. Snoop to WT region.
+*                        3. Snoop to WB region.
+*                        4. Snoop & Invalidate to WB region.
+*         baseAddress - Base Address of this region.
+*         regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+					0x0);
+		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+				       &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					bar_value);
+	}
+}
+
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CFG_PCI0_IO_SPACE_PCI,
+			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	pciArbiterEnable (PCI_HOST0);
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CFG_PCI1_IO_SPACE_PCI,
+			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}
diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c
new file mode 100755
index 0000000..d2635f8
--- /dev/null
+++ b/board/Marvell/db64360/sdram_init.c
@@ -0,0 +1,1984 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * adaption for the Marvell DB64360 Board
+ * Ingo Assmus (ingo.assmus@keymile.com)
+ ************************************************************************/
+
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "../common/i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+#define MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+int set_dfcdlInit (void);	/* setup delay line of Mv64360 */
+int mvDmaIsChannelActive (int);
+int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
+int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
+
+/* ------------------------------------------------------------------------- */
+
+int
+memory_map_bank (unsigned int bankNo,
+		 unsigned int bankBase, unsigned int bankLength)
+{
+#ifdef MAP_PCI
+	PCI_HOST host;
+#endif
+
+
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf ("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank (bankNo, bankBase, bankLength);
+
+#ifdef MAP_PCI
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 | PCI_NO_SWAP;
+
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);
+
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
+	}
+#endif
+	return 0;
+}
+
+#define GB	   (1 << 30)
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+	uchar drb_size;
+	uchar registered, ecc;
+	uchar tpar;
+	uchar tras_clocks;
+	uchar burst_len;
+	uchar banks, slot;
+} sdram_info_t;
+
+/* Typedefs for 'gtAuxilGetDIMMinfo' function */
+
+typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
+
+typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
+	SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
+} VOLTAGE_INTERFACE;
+
+typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
+		4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
+		32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
+typedef enum _max_CL_supported_SD { SD_CL_1 =
+		1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
+		SD_FAULT } MAX_CL_SUPPORTED_SD;
+
+
+/* SDRAM/DDR information struct */
+typedef struct _gtMemoryDimmInfo {
+	MEMORY_TYPE memoryType;
+	unsigned int numOfRowAddresses;
+	unsigned int numOfColAddresses;
+	unsigned int numOfModuleBanks;
+	unsigned int dataWidth;
+	VOLTAGE_INTERFACE voltageInterface;
+	unsigned int errorCheckType;	/* ECC , PARITY.. */
+	unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
+	unsigned int errorCheckDataWidth;	/* 0 - no, 1 - Yes */
+	unsigned int minClkDelay;
+	unsigned int burstLengthSupported;
+	unsigned int numOfBanksOnEachDevice;
+	unsigned int suportedCasLatencies;
+	unsigned int RefreshInterval;
+	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
+	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
+	MAX_CL_SUPPORTED_SD maxClSupported_SD;
+	unsigned int moduleBankDensity;
+	/* module attributes (true for yes) */
+	bool bufferedAddrAndControlInputs;
+	bool registeredAddrAndControlInputs;
+	bool onCardPLL;
+	bool bufferedDQMBinputs;
+	bool registeredDQMBinputs;
+	bool differentialClockInput;
+	bool redundantRowAddressing;
+
+	/* module general attributes */
+	bool suportedAutoPreCharge;
+	bool suportedPreChargeAll;
+	bool suportedEarlyRasPreCharge;
+	bool suportedWrite1ReadBurst;
+	bool suported5PercentLowVCC;
+	bool suported5PercentUpperVCC;
+	/* module timing parameters */
+	unsigned int minRasToCasDelay;
+	unsigned int minRowActiveRowActiveDelay;
+	unsigned int minRasPulseWidth;
+	unsigned int minRowPrechargeTime;	/* measured in ns */
+
+	int addrAndCommandHoldTime;	/* LoP left of point (measured in ns) */
+	int addrAndCommandSetupTime;	/* (measured in ns/100) */
+	int dataInputSetupTime; /* LoP left of point (measured in ns) */
+	int dataInputHoldTime;	/* LoP left of point (measured in ns) */
+/* tAC times for highest 2nd and 3rd highest CAS Latency values */
+	unsigned int clockToDataOut_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOut_RoP;	/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_RoP;	/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
+
+	/* Parameters calculated from
+	   the extracted DIMM information */
+	unsigned int size;
+	unsigned int deviceDensity;	/* 16,64,128,256 or 512 Mbit */
+	unsigned int numberOfDevices;
+	uchar drb_size;		/* DRAM size in n*64Mbit */
+	uchar slot;		/* Slot Number this module is inserted in */
+	uchar spd_raw_data[128];	/* Content of SPD-EEPROM copied 1:1 */
+#ifdef DEBUG
+	uchar manufactura[8];	/* Content of SPD-EEPROM Byte 64-71 */
+	uchar modul_id[18];	/* Content of SPD-EEPROM Byte 73-90 */
+	uchar vendor_data[27];	/* Content of SPD-EEPROM Byte 99-125 */
+	unsigned long modul_serial_no;	/* Content of SPD-EEPROM Byte 95-98 */
+	unsigned int manufac_date;	/* Content of SPD-EEPROM Byte 93-94 */
+	unsigned int modul_revision;	/* Content of SPD-EEPROM Byte 91-92 */
+	uchar manufac_place;	/* Content of SPD-EEPROM Byte 72 */
+
+#endif
+} AUX_MEM_DIMM_INFO;
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
+static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned long spd_checksum;
+
+#ifdef ZUMA_NTL
+	/* zero all the values */
+	memset (info, 0, sizeof (*info));
+
+/*
+	if (!slot) {
+	    info->slot = 0;
+	    info->banks = 1;
+	    info->registered = 0;
+		    info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
+/*	    info->tpar = 3;
+	    info->tras_clocks = 5;
+	    info->burst_len = 4;
+*/
+#ifdef CONFIG_MV64360_ECC
+	/* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
+	dimmInfo->errorCheckType = 2;
+/*	    info->ecc = 2;*/
+#endif
+}
+
+return 0;
+
+#else
+	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+	int ret;
+	unsigned int i, j, density = 1, devicesForErrCheck = 0;
+
+#ifdef DEBUG
+	unsigned int k;
+#endif
+	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
+	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
+	uchar supp_cal, cal_val;
+	ulong memclk, tmemclk;
+	ulong tmp;
+	uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
+	uchar data[128];
+
+	memclk = gd->bus_clk;
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+	DP (puts ("before i2c read\n"));
+
+	ret = i2c_read (addr, 0, 1, data, 128);
+
+	DP (puts ("after i2c read\n"));
+
+	/* zero all the values */
+	memset (dimmInfo, 0, sizeof (*dimmInfo));
+
+	/* copy the SPD content 1:1 into the dimmInfo structure */
+	for (i = 0; i <= 127; i++) {
+		dimmInfo->spd_raw_data[i] = data[i];
+	}
+
+	if (ret) {
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+		return 0;
+	} else
+		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
+
+#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+
+	for (i = 0; i <= 127; i++) {
+		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
+			data[i]);
+	}
+
+#endif
+#ifdef DEBUG
+/* find Manufactura of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
+		dimmInfo->manufactura[i] = data[64 + i];
+	}
+	printf ("\nThis RAM-Module is produced by:		%s\n",
+		dimmInfo->manufactura);
+
+/* find Manul-ID of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
+		dimmInfo->modul_id[i] = data[73 + i];
+	}
+	printf ("The Module-ID of this RAM-Module is:		%s\n",
+		dimmInfo->modul_id);
+
+/* find Vendor-Data of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
+		dimmInfo->vendor_data[i] = data[99 + i];
+	}
+	printf ("Vendor Data of this RAM-Module is:		%s\n",
+		dimmInfo->vendor_data);
+
+/* find modul_serial_no of Dimm Module */
+	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
+	printf ("Serial No. of this RAM-Module is:		%ld (%lx)\n",
+		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
+
+/* find Manufac-Data of Dimm Module */
+	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
+	printf ("Manufactoring Date of this RAM-Module is:	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
+
+/* find modul_revision of Dimm Module */
+	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
+	printf ("Module Revision of this RAM-Module is:			%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
+
+/* find manufac_place of Dimm Module */
+	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
+	printf ("manufac_place of this RAM-Module is:		%d\n",
+		dimmInfo->manufac_place);
+
+#endif
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+/* calculate SPD checksum */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	spd_checksum = 0;
+
+	for (i = 0; i <= 62; i++) {
+		spd_checksum += data[i];
+	}
+
+	if ((spd_checksum & 0xff) != data[63]) {
+		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
+		hang ();
+	}
+
+	else
+		printf ("SPD Checksum ok!\n");
+
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	for (i = 2; i <= 35; i++) {
+		switch (i) {
+		case 2: /* Memory type (DDR / SDRAM) */
+			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
+#ifdef DEBUG
+			if (dimmInfo->memoryType == 0)
+				DP (printf
+				    ("Dram_type in slot %d is:			SDRAM\n",
+				     dimmInfo->slot));
+			if (dimmInfo->memoryType == 1)
+				DP (printf
+				    ("Dram_type in slot %d is:			DDRAM\n",
+				     dimmInfo->slot));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 3: /* Number Of Row Addresses */
+			dimmInfo->numOfRowAddresses = data[i];
+			DP (printf
+			    ("Module Number of row addresses:		%d\n",
+			     dimmInfo->numOfRowAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 4: /* Number Of Column Addresses */
+			dimmInfo->numOfColAddresses = data[i];
+			DP (printf
+			    ("Module Number of col addresses:		%d\n",
+			     dimmInfo->numOfColAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 5: /* Number Of Module Banks */
+			dimmInfo->numOfModuleBanks = data[i];
+			DP (printf
+			    ("Number of Banks on Mod. :					%d\n",
+			     dimmInfo->numOfModuleBanks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 6: /* Data Width */
+			dimmInfo->dataWidth = data[i];
+			DP (printf
+			    ("Module Data Width:				%d\n",
+			     dimmInfo->dataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 8: /* Voltage Interface */
+			switch (data[i]) {
+			case 0x0:
+				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
+				DP (printf
+				    ("Module is						TTL_5V_TOLERANT\n"));
+				break;
+			case 0x1:
+				dimmInfo->voltageInterface = LVTTL;
+				DP (printf
+				    ("Module is						LVTTL\n"));
+				break;
+			case 0x2:
+				dimmInfo->voltageInterface = HSTL_1_5V;
+				DP (printf
+				    ("Module is						TTL_5V_TOLERANT\n"));
+				break;
+			case 0x3:
+				dimmInfo->voltageInterface = SSTL_3_3V;
+				DP (printf
+				    ("Module is						HSTL_1_5V\n"));
+				break;
+			case 0x4:
+				dimmInfo->voltageInterface = SSTL_2_5V;
+				DP (printf
+				    ("Module is						SSTL_2_5V\n"));
+				break;
+			default:
+				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
+				DP (printf
+				    ("Module is						VOLTAGE_UNKNOWN\n"));
+				break;
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 9: /* Minimum Cycle Time At Max CasLatancy */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At Max CasLatancy:		%d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 10:	/* Clock To Data Out */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOut_LoP = leftOfPoint;
+			dimmInfo->clockToDataOut_RoP = rightOfPoint;
+			DP (printf ("Clock To Data Out:					%d.%2d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->clockToDataOut */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+/*#ifdef CONFIG_ECC */
+		case 11:	/* Error Check Type */
+			dimmInfo->errorCheckType = data[i];
+			DP (printf
+			    ("Error Check Type (0=NONE):			%d\n",
+			     dimmInfo->errorCheckType));
+			break;
+/* #endif */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 12:	/* Refresh Interval */
+			dimmInfo->RefreshInterval = data[i];
+			DP (printf
+			    ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
+			     dimmInfo->RefreshInterval));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 13:	/* Sdram Width */
+			dimmInfo->sdramWidth = data[i];
+			DP (printf
+			    ("Sdram Width:					%d\n",
+			     dimmInfo->sdramWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 14:	/* Error Check Data Width */
+			dimmInfo->errorCheckDataWidth = data[i];
+			DP (printf
+			    ("Error Check Data Width:			%d\n",
+			     dimmInfo->errorCheckDataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 15:	/* Minimum Clock Delay */
+			dimmInfo->minClkDelay = data[i];
+			DP (printf
+			    ("Minimum Clock Delay:				%d\n",
+			     dimmInfo->minClkDelay));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 16:	/* Burst Length Supported */
+			   /******-******-******-*******
+			   * bit3 | bit2 | bit1 | bit0 *
+			   *******-******-******-*******
+	    burst length = *  8	  |  4	 |   2	|   1  *
+			   *****************************
+
+	    If for example bit0 and bit2 are set, the burst
+	    length supported are 1 and 4. */
+
+			dimmInfo->burstLengthSupported = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Burst Length Supported:			"));
+			if (dimmInfo->burstLengthSupported & 0x01)
+				DP (printf ("1, "));
+			if (dimmInfo->burstLengthSupported & 0x02)
+				DP (printf ("2, "));
+			if (dimmInfo->burstLengthSupported & 0x04)
+				DP (printf ("4, "));
+			if (dimmInfo->burstLengthSupported & 0x08)
+				DP (printf ("8, "));
+			DP (printf (" Bit \n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 17:	/* Number Of Banks On Each Device */
+			dimmInfo->numOfBanksOnEachDevice = data[i];
+			DP (printf
+			    ("Number Of Banks On Each Chip:			%d\n",
+			     dimmInfo->numOfBanksOnEachDevice));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 18:	/* Suported Cas Latencies */
+
+			/*     DDR:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =	 * TBD	| TBD  | 3.5  |	  3  | 2.5  |  2   | 1.5  |   1	 *
+			 *********************************************************
+			 SDRAM:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =	 * TBD	|  7   |  6   |	 5   |	4   |  3   |   2  |   1	 *
+			 ********************************************************/
+			dimmInfo->suportedCasLatencies = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Suported Cas Latencies: (CL)			"));
+			if (dimmInfo->memoryType == 0) {	/* SDRAM */
+				for (k = 0; k <= 7; k++) {
+					if (dimmInfo->
+					    suportedCasLatencies & (1 << k))
+						DP (printf
+						    ("%d,			",
+						     k + 1));
+				}
+
+			} else {	/* DDR-RAM */
+
+				if (dimmInfo->suportedCasLatencies & 1)
+					DP (printf ("1, "));
+				if (dimmInfo->suportedCasLatencies & 2)
+					DP (printf ("1.5, "));
+				if (dimmInfo->suportedCasLatencies & 4)
+					DP (printf ("2, "));
+				if (dimmInfo->suportedCasLatencies & 8)
+					DP (printf ("2.5, "));
+				if (dimmInfo->suportedCasLatencies & 16)
+					DP (printf ("3, "));
+				if (dimmInfo->suportedCasLatencies & 32)
+					DP (printf ("3.5, "));
+
+			}
+			DP (printf ("\n"));
+#endif
+			/* Calculating MAX CAS latency */
+			for (j = 7; j > 0; j--) {
+				if (((dimmInfo->
+				      suportedCasLatencies >> j) & 0x1) ==
+				    1) {
+					switch (dimmInfo->memoryType) {
+					case DDR:
+						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
+						switch (j) {
+						case 7:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 6:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 5:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				3.5 clk's\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3_5;
+							break;
+						case 4:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				3 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3;
+							break;
+						case 3:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				2.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2_5;
+							break;
+						case 2:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				2 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2;
+							break;
+						case 1:
+							DP (printf
+							    ("Max. Cas Latencies (DDR):				1.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_1_5;
+							break;
+						}
+
+						/* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
+						   lower then our SDRAM cycle count, we won't be able to support this CAL
+						   and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
+						if ((dimmInfo->
+						     minimumCycleTimeAtMaxCasLatancy_LoP
+						     <
+						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						    ||
+						    ((dimmInfo->
+						      minimumCycleTimeAtMaxCasLatancy_LoP
+						      ==
+						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     && (dimmInfo->
+							 minimumCycleTimeAtMaxCasLatancy_RoP
+							 <
+							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+						{
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								dimmInfo->
+								maxClSupported_DDR
+								>> 1;
+							DP (printf
+							    ("*** Change actual Cas Latencies cause of minimumCycleTime n"));
+						}
+						/* ronen - checkif the Dimm frequency compared to the Sysclock. */
+						if ((dimmInfo->
+						     minimumCycleTimeAtMaxCasLatancy_LoP
+						     >
+						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						    ||
+						    ((dimmInfo->
+						      minimumCycleTimeAtMaxCasLatancy_LoP
+						      ==
+						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     && (dimmInfo->
+							 minimumCycleTimeAtMaxCasLatancy_RoP
+							 >
+							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+						{
+							printf ("*********************************************************\n");
+							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
+							printf ("*********************************************************\n");
+							hang ();
+						}
+
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							=
+							1 +
+							(int) (5 * j / 10);
+						if (((5 * j) % 10) != 0)
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 5;
+						else
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation):	%d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					case SDRAM:
+						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
+						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded			*/
+						DP (printf
+						    ("Max. Cas Latencies (SD): %d\n",
+						     dimmInfo->
+						     maxClSupported_SD));
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							= j;
+						dimmInfo->
+							maxCASlatencySupported_RoP
+							= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					}
+					break;
+				}
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 21:	/* Buffered Address And Control Inputs */
+			DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
+			dimmInfo->bufferedAddrAndControlInputs =
+				data[i] & BIT0;
+			dimmInfo->registeredAddrAndControlInputs =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
+			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
+			dimmInfo->registeredDQMBinputs =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->differentialClockInput =
+				(data[i] & BIT5) >> 5;
+			dimmInfo->redundantRowAddressing =
+				(data[i] & BIT6) >> 6;
+#ifdef DEBUG
+			if (dimmInfo->bufferedAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Buffered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Buffered Address/Control Input:		No \n"));
+
+			if (dimmInfo->registeredAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Registered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Registered Address/Control Input:		No \n"));
+
+			if (dimmInfo->onCardPLL == 1)
+				DP (printf
+				    (" - On-Card PLL (clock):				Yes \n"));
+			else
+				DP (printf
+				    (" - On-Card PLL (clock):				No \n"));
+
+			if (dimmInfo->bufferedDQMBinputs == 1)
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				Yes \n"));
+			else
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				No \n"));
+
+			if (dimmInfo->registeredDQMBinputs == 1)
+				DP (printf
+				    (" - Registered DQMB Inputs:			Yes \n"));
+			else
+				DP (printf
+				    (" - Registered DQMB Inputs:			No \n"));
+
+			if (dimmInfo->differentialClockInput == 1)
+				DP (printf
+				    (" - Differential Clock Input:			Yes \n"));
+			else
+				DP (printf
+				    (" - Differential Clock Input:			No \n"));
+
+			if (dimmInfo->redundantRowAddressing == 1)
+				DP (printf
+				    (" - redundant Row Addressing:			Yes \n"));
+			else
+				DP (printf
+				    (" - redundant Row Addressing:			No \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 22:	/* Suported AutoPreCharge */
+			DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
+			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
+			dimmInfo->suportedAutoPreCharge =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->suportedPreChargeAll =
+				(data[i] & BIT2) >> 2;
+			dimmInfo->suportedWrite1ReadBurst =
+				(data[i] & BIT3) >> 3;
+			dimmInfo->suported5PercentLowVCC =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->suported5PercentUpperVCC =
+				(data[i] & BIT5) >> 5;
+#ifdef DEBUG
+			if (dimmInfo->suportedEarlyRasPreCharge == 1)
+				DP (printf
+				    (" - Early Ras Precharge:			Yes \n"));
+			else
+				DP (printf
+				    (" -  Early Ras Precharge:			No \n"));
+
+			if (dimmInfo->suportedAutoPreCharge == 1)
+				DP (printf
+				    (" - AutoPreCharge:				Yes \n"));
+			else
+				DP (printf
+				    (" -  AutoPreCharge:				No \n"));
+
+			if (dimmInfo->suportedPreChargeAll == 1)
+				DP (printf
+				    (" - Precharge All:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Precharge All:				No \n"));
+
+			if (dimmInfo->suportedWrite1ReadBurst == 1)
+				DP (printf
+				    (" - Write 1/ReadBurst:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Write 1/ReadBurst:				No \n"));
+
+			if (dimmInfo->suported5PercentLowVCC == 1)
+				DP (printf
+				    (" - lower VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    ("	- lower VCC tolerance:			10 Percent \n"));
+
+			if (dimmInfo->suported5PercentUpperVCC == 1)
+				DP (printf
+				    (" - upper VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    (" -  upper VCC tolerance:			10 Percent \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
+				rightOfPoint;
+			DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (2nd CL value):			%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
+				rightOfPoint;
+			DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (3rd CL value):			%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 27:	/* Minimum Row Precharge Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
+			trp_clocks =
+				(dimmInfo->minRowPrechargeTime +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
+			     tmemclk, tmemclk / 100, tmemclk % 100));
+			DP (printf
+			    ("Minimum Row Precharge Time [ns]:		%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 28:	/* Minimum Row Active to Row Active Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trrd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Row Active -To- Row Active Delay [ns]:	%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 29:	/* Minimum Ras-To-Cas Delay */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trcd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras-To-Cas Delay [ns]:			%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 30:	/* Minimum Ras Pulse Width */
+			dimmInfo->minRasPulseWidth = data[i];
+			tras_clocks =
+				(NSto10PS (data[i]) +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras Pulse Width [ns]:			%d = in Clk cycles %d\n",
+			     dimmInfo->minRasPulseWidth, tras_clocks));
+
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 31:	/* Module Bank Density */
+			dimmInfo->moduleBankDensity = data[i];
+			DP (printf
+			    ("Module Bank Density:				%d\n",
+			     dimmInfo->moduleBankDensity));
+#ifdef DEBUG
+			DP (printf
+			    ("*** Offered Densities (more than 1 = Multisize-Module): "));
+			{
+				if (dimmInfo->moduleBankDensity & 1)
+					DP (printf ("4MB, "));
+				if (dimmInfo->moduleBankDensity & 2)
+					DP (printf ("8MB, "));
+				if (dimmInfo->moduleBankDensity & 4)
+					DP (printf ("16MB, "));
+				if (dimmInfo->moduleBankDensity & 8)
+					DP (printf ("32MB, "));
+				if (dimmInfo->moduleBankDensity & 16)
+					DP (printf ("64MB, "));
+				if (dimmInfo->moduleBankDensity & 32)
+					DP (printf ("128MB, "));
+				if ((dimmInfo->moduleBankDensity & 64)
+				    || (dimmInfo->moduleBankDensity & 128)) {
+					DP (printf ("ERROR, "));
+					hang ();
+				}
+			}
+			DP (printf ("\n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Setup Time [ns]:		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 33:	/* Address And Command Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Hold Time [ns]:		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 34:	/* Data Input Setup Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Setup Time [ns]:			%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 35:	/* Data Input Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Hold Time [ns]:			%d.%d\n\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+		}
+	}
+	/* calculating the sdram density */
+	for (i = 0;
+	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
+	     i++) {
+		density = density * 2;
+	}
+	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
+		dimmInfo->sdramWidth;
+	dimmInfo->numberOfDevices =
+		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
+		dimmInfo->numOfModuleBanks;
+	devicesForErrCheck =
+		(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
+	if ((dimmInfo->errorCheckType == 0x1)
+	    || (dimmInfo->errorCheckType == 0x2)
+	    || (dimmInfo->errorCheckType == 0x3)) {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			(dimmInfo->numberOfDevices -
+			 /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
+			 dimmInfo->numberOfDevices / 8);
+	} else {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			dimmInfo->numberOfDevices;
+	}
+
+	/* compute the module DRB size */
+	tmp = (1 <<
+	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
+	tmp *= dimmInfo->numOfModuleBanks;
+	tmp *= dimmInfo->sdramWidth;
+	tmp = tmp >> 24;	/* div by 0x4000000 (64M)	*/
+	dimmInfo->drb_size = (uchar) tmp;
+	DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
+
+	/* try a CAS latency of 3 first... */
+
+	/* bit 1 is CL2, bit 2 is CL3 */
+	supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
+
+	cal_val = 0;
+	if (supp_cal & 3) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 3;
+	}
+
+	/* then 2... */
+	if (supp_cal & 2) {
+		if (NS10to10PS (data[23]) <= tmemclk)
+			cal_val = 2;
+	}
+
+	DP (printf ("cal_val = %d\n", cal_val));
+
+	/* bummer, did't work... */
+	if (cal_val == 0) {
+		DP (printf ("Couldn't find a good CAS latency\n"));
+		hang ();
+		return 0;
+	}
+
+	return true;
+
+#endif
+}
+
+/* sets up the GT properly with information passed in */
+int setup_sdram (AUX_MEM_DIMM_INFO * info)
+{
+	ulong tmp, check;
+	ulong tmp_sdram_mode = 0;	/* 0x141c */
+	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
+	int i;
+
+	/* added 8/21/2003 P. Marchese */
+	unsigned int sdram_config_reg;
+
+	/* added 10/10/2003 P. Marchese */
+	ulong sdram_chip_size;
+
+	/* sanity checking */
+	if (!info->numOfModuleBanks) {
+		printf ("setup_sdram called with 0 banks\n");
+		return 1;
+	}
+
+	/* delay line */
+	set_dfcdlInit ();	/* may be its not needed */
+	DP (printf ("Delay line set done\n"));
+
+	/* set SDRAM mode NOP */ /* To_do check it */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
+	}
+
+	/* SDRAM configuration */
+/* added 8/21/2003 P. Marchese */
+/* code allows usage of registered DIMMS */
+
+	/* figure out the memory refresh internal */
+	switch (info->RefreshInterval) {
+	case 0x0:
+	case 0x80:		/* refresh period is 15.625 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
+					/ (float) 1000000.0);
+		break;
+	case 0x1:
+	case 0x81:		/* refresh period is 3.9 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	case 0x2:
+	case 0x82:		/* refresh period is 7.8 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	case 0x3:
+	case 0x83:		/* refresh period is 31.3 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	case 0x4:
+	case 0x84:		/* refresh period is 62.5 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	case 0x5:
+	case 0x85:		/* refresh period is 125 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	default:		/* refresh period undefined */
+		printf ("DRAM refresh period is unknown!\n");
+		printf ("Aborting DRAM setup with an error\n");
+		hang ();
+		break;
+	}
+	DP (printf ("calculated refresh interval %0x\n", sdram_config_reg));
+
+	/* make sure the refresh value is only 14 bits */
+	if (sdram_config_reg > 0x1fff)
+		sdram_config_reg = 0x1fff;
+	DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg));
+
+	/* we want physical bank interleaving and */
+	/* virtual bank interleaving enabled so do nothing */
+	/* since these bits need to be zero to enable the interleaving */
+
+	/*  registered DRAM ? */
+	if (info->registeredAddrAndControlInputs == 1) {
+		/* it's registered DRAM, so set the reg. DRAM bit */
+		sdram_config_reg = sdram_config_reg | BIT17;
+		DP (printf ("Enabling registered DRAM bit\n"));
+	}
+	/* turn on DRAM ECC? */
+#ifdef CONFIG_MV64360_ECC
+	if (info->errorCheckType == 0x2) {
+		/* DRAM has ECC, so turn it on */
+		sdram_config_reg = sdram_config_reg | BIT18;
+		DP (printf ("Enabling ECC\n"));
+	}
+#endif
+	/* set the data DQS pin configuration */
+	switch (info->sdramWidth) {
+	case 0x4:		/* memory is x4 */
+		sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
+		DP (printf ("Data DQS pins set for 16 pins\n"));
+		break;
+	case 0x8:		/* memory is x8 or x16 */
+	case 0x10:
+		sdram_config_reg = sdram_config_reg | BIT21;
+		DP (printf ("Data DQS pins set for 8 pins\n"));
+		break;
+	case 0x20:		/* memory is x32 */
+		/* both bits are cleared for x32 so nothing to do */
+		DP (printf ("Data DQS pins set for 2 pins\n"));
+		break;
+	default:		/* memory width unsupported */
+		printf ("DRAM chip width is unknown!\n");
+		printf ("Aborting DRAM setup with an error\n");
+		hang ();
+		break;
+	}
+
+	/* perform read buffer assignments */
+	/* we are going to use the Power-up defaults */
+	/* bit 26 = CPU = buffer 1 */
+	/* bit 27 = PCI bus #0 = buffer 0 */
+	/* bit 28 = PCI bus #1 = buffer 0 */
+	/* bit 29 = MPSC = buffer 0 */
+	/* bit 30 = IDMA = buffer 0 */
+	/* bit 31 = Gigabit = buffer 0 */
+	sdram_config_reg = sdram_config_reg | BIT26;
+	/*  sdram_config_reg = sdram_config_reg | 0x58000000; */
+	/* sdram_config_reg = sdram_config_reg & 0xffffff00;  */
+
+	/* write the value into the SDRAM configuration register */
+	GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
+	DP (printf
+	    ("OOOOOOOOO sdram_conf 0x1400: %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM open pages control keep open as much as I can */
+	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
+	DP (printf
+	    ("sdram_open_pages_controll 0x1414: %08x\n",
+	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp == 0)
+		DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
+	else
+		DP (printf
+		    ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
+
+	/* SDRAM set CAS Latency according to SPD information */
+	switch (info->memoryType) {
+	case SDRAM:
+		printf ("### SD-RAM not supported !!!\n");
+		printf ("Aborting!!!\n");
+		hang ();
+		/* ToDo fill SD-RAM if needed !!!!! */
+		break;
+		/* Calculate the settings for SDRAM mode and Dunit control low registers */
+		/* Values set according to technical bulletin TB-92 rev. c */
+	case DDR:
+		DP (printf ("### SET-CL for DDR-RAM\n"));
+		switch (info->maxClSupported_DDR) {
+		case DDR_CL_3:
+			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
+			if (tmp == 1) { /* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x05110051;
+				else
+					tmp_dunit_control_low = 0x24110051;
+				DP (printf
+				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed	*/
+
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x2C1107F2;
+				else
+					tmp_dunit_control_low = 0x3C1107d2;
+				DP (printf
+				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_2_5:
+			tmp_sdram_mode = 0x62;	/* CL=2.5 Burstlength = 4 */
+			if (tmp == 1) { /* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x25110051;
+				else
+					tmp_dunit_control_low = 0x24110051;
+				DP (printf
+				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed	*/
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
+					printf ("Aborting!!!\n");
+					hang ();
+				} else
+					tmp_dunit_control_low = 0x1B1107d2;
+				DP (printf
+				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_2:
+			tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+			if (tmp == 1) { /* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x04110051;
+				else
+					tmp_dunit_control_low = 0x03110051;
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed	*/
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
+					printf ("Aborting!!!\n");
+					hang ();
+				} else
+					tmp_dunit_control_low = 0x3B1107d2;
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_1_5:
+			tmp_sdram_mode = 0x52;	/* CL=1.5 Burstlength = 4 */
+			if (tmp == 1) { /* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x24110051;
+				else
+					tmp_dunit_control_low = 0x23110051;
+				DP (printf
+				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed	*/
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");
+					printf ("Aborting!!!\n");
+					hang ();
+				} else
+					tmp_dunit_control_low = 0x1A1107d2;
+				DP (printf
+				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		default:
+			printf ("Max. CL is out of range %d\n",
+				info->maxClSupported_DDR);
+			hang ();
+			break;
+		}		/* end DDR switch */
+		break;
+	}			/* end CL switch */
+
+	/* Write results of CL detection procedure */
+	/* set SDRAM mode reg. 0x141c */
+	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+	}
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
+	}
+
+/*------------------------------------------------------------------------------ */
+
+	/* bank parameters */
+	/* SDRAM address decode register 0x1410 */
+	/* program this with the default value */
+	tmp = 0x02;		/* power-up default address select decoding value */
+
+	DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
+/* figure out the DRAM chip size */
+	sdram_chip_size =
+		(1 << (info->numOfRowAddresses + info->numOfColAddresses));
+	sdram_chip_size *= info->sdramWidth;
+	sdram_chip_size *= 4;
+	DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size));
+	/* divide sdram chip size by 64 Mbits */
+	sdram_chip_size = sdram_chip_size / 0x4000000;
+	switch (sdram_chip_size) {
+	case 1:		/* 64 Mbit */
+	case 2:		/* 128 Mbit */
+		DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
+		tmp |= (0x00 << 4);
+		break;
+	case 4:		/* 256 Mbit */
+	case 8:		/* 512 Mbit */
+		DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
+		tmp |= (0x01 << 4);
+		break;
+	case 16:		/* 1 Gbit */
+	case 32:		/* 2 Gbit */
+		DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
+		tmp |= (0x02 << 4);
+		break;
+	default:
+		printf ("Error in dram size calculation\n");
+		printf ("RAM-Device_size is unsupported\n");
+		hang ();
+	}
+
+	/* SDRAM address control */
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
+	DP (printf
+	    ("setting up sdram address control (0x1410) with: %08lx \n",
+	     tmp));
+
+/* ------------------------------------------------------------------------------ */
+/* same settings for registerd & non-registerd DDR SDRAM */
+	DP (printf
+	    ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
+	     0x11511220));
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
+
+
+/* ------------------------------------------------------------------------------ */
+
+	/* SDRAM configuration */
+	tmp = GTREGREAD (SDRAM_CONFIG);
+
+	if (info->registeredAddrAndControlInputs
+	    || info->registeredDQMBinputs) {
+		tmp |= (1 << 17);
+		DP (printf
+		    ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
+		     info->registeredAddrAndControlInputs,
+		     info->registeredDQMBinputs));
+	}
+
+	/* Use buffer 1 to return read data to the CPU
+	 * Page 426 MV64360 */
+	tmp |= (1 << 26);
+	DP (printf
+	    ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+	DP (printf
+	    ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM timing To_do: */
+/* ------------------------------------------------------------------------------ */
+
+	DP (printf
+	    ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
+	     0x9));
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9);
+
+	DP (printf
+	    ("setting up sdram address pads control (0x14c0) with: %08x \n",
+	     0x7d5014a));
+	GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
+
+	DP (printf
+	  indent: Standard input:1450: Warning:old style assignment ambiguity in "=*".	Assuming "= *"
+
+indent: Standard input:1451: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+  ("setting up sdram data pads control (0x14c4) with: %08x \n",
+	     0x7d5014a));
+	GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
+
+/* ------------------------------------------------------------------------------ */
+
+	/* set the SDRAM configuration for each bank */
+
+/*	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
+	{
+		i = info->slot;
+		DP (printf
+		    ("\n*** Running a MRS cycle for bank %d ***\n", i));
+
+		/* map the bank */
+		memory_map_bank (i, 0, GB / 4);
+
+		/* set SDRAM mode */ /* To_do check it */
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+
+
+		/* switch back to normal operation mode */
+		GT_REG_WRITE (SDRAM_OPERATION, 0);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+
+		/* unmap the bank */
+		memory_map_bank (i, 0, 0);
+	}
+
+	return 0;
+
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+long int dram_size (long int *base, long int maxsize)
+{
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
+
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
+
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
+		val = *addr;	/* read *addr */
+
+		*addr = save1;
+		*b = save2;
+
+		if (val != cnt) {
+			DP (printf
+			    ("Found %08x  at Address %08x (failure)\n",
+			     (unsigned int) val, (unsigned int) addr));
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+	return maxsize;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* ppcboot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+long int initdram (int board_type)
+{
+	int s0 = 0, s1 = 0;
+	int checkbank[4] = {[0 ... 3] = 0 };
+	ulong realsize, total, check;
+	AUX_MEM_DIMM_INFO dimmInfo1;
+	AUX_MEM_DIMM_INFO dimmInfo2;
+	int nhr, bank_no;
+	ulong dest, memSpaceAttr;
+
+	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
+
+	/* check the NHR bit and skip mem init if it's already done */
+	nhr = get_hid0 () & (1 << 16);
+
+	if (nhr) {
+		printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
+	} else {
+		/* DIMM0 */
+		s0 = check_dimm (0, &dimmInfo1);
+
+		/* DIMM1 */
+		s1 = check_dimm (1, &dimmInfo2);
+
+		memory_map_bank (0, 0, 0);
+		memory_map_bank (1, 0, 0);
+		memory_map_bank (2, 0, 0);
+		memory_map_bank (3, 0, 0);
+
+		/* ronen check correct set of DIMMS */
+		if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
+			if (dimmInfo1.errorCheckType !=
+			    dimmInfo2.errorCheckType)
+				printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
+			if (dimmInfo1.maxClSupported_DDR !=
+			    dimmInfo2.maxClSupported_DDR)
+				printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
+			if (dimmInfo1.registeredAddrAndControlInputs !=
+			    dimmInfo2.registeredAddrAndControlInputs)
+				printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
+		}
+
+		if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
+			printf ("Setup for DIMM1 failed.\n");
+		}
+
+		if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
+			printf ("Setup for DIMM2 failed.\n");
+		}
+
+		/* set the NHR bit */
+		set_hid0 (get_hid0 () | (1 << 16));
+	}
+	/* next, size the SDRAM banks */
+
+	realsize = total = 0;
+	check = GB / 4;
+	if (dimmInfo1.numOfModuleBanks > 0) {
+		checkbank[0] = 1;
+	}
+	if (dimmInfo1.numOfModuleBanks > 1) {
+		checkbank[1] = 1;
+	}
+	if (dimmInfo1.numOfModuleBanks > 2)
+		printf ("Error, SPD claims DIMM1 has >2 banks\n");
+
+	printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
+
+	if (dimmInfo2.numOfModuleBanks > 0) {
+		checkbank[2] = 1;
+	}
+	if (dimmInfo2.numOfModuleBanks > 1) {
+		checkbank[3] = 1;
+	}
+	if (dimmInfo2.numOfModuleBanks > 2)
+		printf ("Error, SPD claims DIMM2 has >2 banks\n");
+
+	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
+
+	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+		/* skip over banks that are not populated */
+		if (!checkbank[bank_no])
+			continue;
+
+		/* ronen - realsize = dram_size((long int *)total, check); */
+		if (bank_no == 0 || bank_no == 1) {
+			if (checkbank[1] == 1)
+				realsize = dimmInfo1.size / 2;
+			else
+				realsize = dimmInfo1.size;
+		}
+		if (bank_no == 2 || bank_no == 3) {
+			if (checkbank[3] == 1)
+				realsize = dimmInfo2.size / 2;
+			else
+				realsize = dimmInfo2.size;
+		}
+		memory_map_bank (bank_no, total, realsize);
+
+		/* ronen - initialize the DRAM for ECC */
+#ifdef CONFIG_MV64360_ECC
+		if ((dimmInfo1.errorCheckType != 0) &&
+		    ((dimmInfo2.errorCheckType != 0)
+		     || (dimmInfo2.numOfModuleBanks == 0))) {
+			printf ("ECC Initialization of Bank %d:", bank_no);
+			memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
+			mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
+					     realsize);
+			for (dest = total; dest < total + realsize;
+			     dest += _8M) {
+				mvDmaTransfer (0, total, dest, _8M,
+					       BIT8 /*DMA_DTL_128BYTES */  |
+					       BIT3 /*DMA_HOLD_SOURCE_ADDR */
+					       |
+					       BIT11
+					       /*DMA_BLOCK_TRANSFER_MODE */ );
+				while (mvDmaIsChannelActive (0));
+			}
+			printf (" PASS\n");
+		}
+#endif
+
+		total += realsize;
+	}
+
+	/* ronen- add DRAM conf prints */
+	switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
+	case 0x2:
+		printf ("CAS Latency = 2");
+		break;
+	case 0x3:
+		printf ("CAS Latency = 3");
+		break;
+	case 0x5:
+		printf ("CAS Latency = 1.5");
+		break;
+	case 0x6:
+		printf ("CAS Latency = 2.5");
+		break;
+	}
+	printf (" tRP = %d tRAS = %d tRCD=%d\n",
+		((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
+		((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
+		((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
+
+/*	Setup Ethernet DMA Adress window to DRAM Area */
+	if (total > _256M)
+		printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
+	else
+		printf ("Total SDRAM memory is ");
+	/* (cause all the 4 BATS are taken) */
+	return (total);
+}
+
+
+/* ronen- add Idma functions for usage of the ecc dram init. */
+/*******************************************************************************
+* mvDmaIsChannelActive - Checks if a engine is busy.
+********************************************************************************/
+int mvDmaIsChannelActive (int engine)
+{
+	ulong data;
+
+	data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
+	if (data & BIT14 /*activity status */ ) {
+		return 1;
+	}
+	return 0;
+}
+
+/*******************************************************************************
+* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
+*			map.
+*******************************************************************************/
+int mvDmaSetMemorySpace (ulong memSpace,
+			 ulong memSpaceTarget,
+			 ulong memSpaceAttr, ulong baseAddress, ulong size)
+{
+	ulong temp;
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return 0;
+	}
+	if (size >= 0x10000 /*64K */ ) {
+		size &= 0xffff0000;
+		baseAddress = (baseAddress & 0xffff0000);
+		/* Set the new attributes */
+		GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG);
+		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
+			      (temp & ~(BIT0 << memSpace)));
+		return 1;
+	}
+	return 0;
+}
+
+
+/*******************************************************************************
+* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
+*		  DMA channels.
+********************************************************************************/
+int mvDmaTransfer (int engine, ulong sourceAddr,
+		   ulong destAddr, ulong numOfBytes, ulong command)
+{
+	ulong engOffReg = 0;	/* Engine Offset Register */
+
+	if (numOfBytes > 0xffff) {
+		command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
+	}
+	command = command | ((command >> 6) & 0x7);
+	engOffReg = engine * 4;
+	GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
+		      numOfBytes);
+	GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
+		      sourceAddr);
+	GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
+		      destAddr);
+	command =
+		command | BIT12 /*DMA_CHANNEL_ENABLE */	 | BIT9
+		/*DMA_NON_CHAIN_MODE */ ;
+	/* Activate DMA engine By writting to mvDmaControlRegister */
+	GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command);
+	return 1;
+}
+
+/****************************************************************************************
+ *				SDRAM INIT						*
+ *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
+ *		  This procedure fits only the Atlantis					*
+ *											*
+ ***************************************************************************************/
+
+
+/****************************************************************************************
+ *				DFCDL initialize MV643xx Design Considerations		*
+ *											*
+ ***************************************************************************************/
+int set_dfcdlInit (void)
+{
+	int i;
+	unsigned int dfcdl_word = 0x391;	/*   0x14f;  ronen new dfcdl */
+
+	for (i = 0; i < 64; i++) {
+		GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
+/*	dfcdl_word += 0x41;  - ronen new dfcdl */
+	}
+	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
+
+	return (0);
+}
diff --git a/board/Marvell/db64360/u-boot.lds b/board/Marvell/db64360/u-boot.lds
new file mode 100755
index 0000000..d89eb6c
--- /dev/null
+++ b/board/Marvell/db64360/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/Marvell/db64460/64460.h b/board/Marvell/db64460/64460.h
new file mode 100755
index 0000000..8bb0ebf
--- /dev/null
+++ b/board/Marvell/db64460/64460.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the Galileo Eval board DB64460.
+ */
+
+#ifndef __64460_H__
+#define __64460_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64460_H__ */
diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile
new file mode 100755
index 0000000..768ccdd
--- /dev/null
+++ b/board/Marvell/db64460/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+SOBJS	= ../common/misc.o
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
+	  mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
+	  sdram_init.o ../common/intel_flash.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/Marvell/db64460/config.mk b/board/Marvell/db64460/config.mk
new file mode 100755
index 0000000..5a434d9
--- /dev/null
+++ b/board/Marvell/db64460/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EVB64460 boards
+#
+
+TEXT_BASE = 0xfff00000
diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c
new file mode 100755
index 0000000..a4abf8d
--- /dev/null
+++ b/board/Marvell/db64460/db64460.c
@@ -0,0 +1,936 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
+ */
+
+/*
+ * db64460.c - main board support/init for the Galileo Eval board.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64460.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+extern void flush_data_cache (void);
+extern void invalidate_l1_instruction_cache (void);
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+int display_mem_map (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CFG_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64460 P.399 */
+#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	uchar sram_boot = 0;
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6446x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6446x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 * Zuma
+	 * 0 - Flash
+	 * boot - BootCS
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+		sram_boot = 1;
+	if (!sram_boot)
+		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+
+	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+
+
+	/* configure device timing */
+#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+	if (!sram_boot)
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+#endif
+
+#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#endif
+#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#endif
+
+#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CFG_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CFG_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+	/* check to see if we booted from the sram.  If so, move things
+	 * back to the way they should be. (we're running from main
+	 * memory at this point now */
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+	}
+	display_mem_map ();
+	/* now, jump to the main ppcboot board init code */
+	board_init_r (gd, dest_addr);
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+	volatile int *addr = 0;
+	int dummy;
+
+	if (mode == 1) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x08000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x0c000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x10000);
+			break;
+		}
+	} else if (mode == 0) {
+		switch (led) {
+		case 0:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x14000);
+			break;
+
+		case 1:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x18000);
+			break;
+
+		case 2:
+			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+					0x1c000);
+			break;
+		}
+	}
+
+	dummy = *addr;
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- EXT SRAM (actual - 1M)\n");
+		else if (i == 1)
+			printf ("\t- RTC\n");
+		else if (i == 2)
+			printf ("\t- UART\n");
+		else
+			printf ("\t- LARGE FLASH\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CFG_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CFG_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_DATA */
+
+#if defined (CFG_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_MEMTEST_START;
+	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_ADDRESS */
+
+#if defined (CFG_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_MEMTEST_START;
+	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata, runaddress, runwalk;
+
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+
+/*    rundata = 1; */
+/*    runaddress = 0; */
+/*    runwalk = 0; */
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+	}
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CFG_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
+	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
+
+/* Relocate MV64460 internal regs */
+	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+
+	icache_disable ();
+	invalidate_l1_instruction_cache ();
+	flush_data_cache ();
+	dcache_disable ();
+}
diff --git a/board/Marvell/db64460/eth.h b/board/Marvell/db64460/eth.h
new file mode 100755
index 0000000..6c3b2e0
--- /dev/null
+++ b/board/Marvell/db64460/eth.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64460_ETH_H__
+#define __EVB64460_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+int db64460_eth0_poll(void);
+int db64460_eth0_transmit(unsigned int s, volatile char *p);
+void db64460_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+#endif /* __EVB64460_ETH_H__ */
diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c
new file mode 100755
index 0000000..33fbc49
--- /dev/null
+++ b/board/Marvell/db64460/mpsc.c
@@ -0,0 +1,1019 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+#include "mv_regs.h"
+
+#include "../include/memory.h"
+
+/* Define this if you wish to use the MPSC as a register based UART.
+ * This will force the serial port to not use the SDMA engine at all.
+ */
+#undef CONFIG_MPSC_DEBUG_PORT
+
+
+int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
+char (*mpsc_getchar) (void) = mpsc_getchar_debug;
+int (*mpsc_test_char) (void) = mpsc_test_char_debug;
+
+
+static volatile unsigned int *rx_desc_base = NULL;
+static unsigned int rx_desc_index = 0;
+static volatile unsigned int *tx_desc_base = NULL;
+static unsigned int tx_desc_index = 0;
+
+/* local function declarations */
+static int galmpsc_connect (int channel, int connect);
+static int galmpsc_route_rx_clock (int channel, int brg);
+static int galmpsc_route_tx_clock (int channel, int brg);
+static int galmpsc_write_config_regs (int mpsc, int mode);
+static int galmpsc_config_channel_regs (int mpsc);
+static int galmpsc_set_char_length (int mpsc, int value);
+static int galmpsc_set_stop_bit_length (int mpsc, int value);
+static int galmpsc_set_parity (int mpsc, int value);
+static int galmpsc_enter_hunt (int mpsc);
+static int galmpsc_set_brkcnt (int mpsc, int value);
+static int galmpsc_set_tcschar (int mpsc, int value);
+static int galmpsc_set_snoop (int mpsc, int value);
+static int galmpsc_shutdown (int mpsc);
+
+static int galsdma_set_RFT (int channel);
+static int galsdma_set_SFM (int channel);
+static int galsdma_set_rxle (int channel);
+static int galsdma_set_txle (int channel);
+static int galsdma_set_burstsize (int channel, unsigned int value);
+static int galsdma_set_RC (int channel, unsigned int value);
+
+static int galbrg_set_CDV (int channel, int value);
+static int galbrg_enable (int channel);
+static int galbrg_disable (int channel);
+static int galbrg_set_clksrc (int channel, int value);
+static int galbrg_set_CUV (int channel, int value);
+
+static void galsdma_enable_rx (void);
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress,
+				  unsigned int size);
+
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+static void mpsc_debug_init (void)
+{
+
+	volatile unsigned int temp;
+
+	/* Clear the CFR  (CHR4) */
+	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_indent: Standard input:229: Warning:old style assignment ambiguity in "=&".  Assuming "= &"
+
+REG_GAP));
+	temp &= 0xffffff00;
+	temp |= BIT29;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
+	temp |= (BIT12 | BIT15);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set int mask */
+	temp = GTREGREAD (GALMPSC_0_INT_MASK);
+	temp |= BIT6;
+	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
+}
+#endif
+
+char mpsc_getchar_debug (void)
+{
+	volatile int temp;
+	volatile unsigned int cause;
+
+	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	while ((cause & BIT6) == 0) {
+		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	}
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
+			  (CHANNEL * GALMPSC_REG_GAP));
+	/* By writing 1's to the set bits, the register is cleared */
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
+	return (temp >> 16) & 0xff;
+}
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int mpsc_putchar_early (char ch)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int mpsc = CHANNEL;
+	int temp =
+		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	galmpsc_set_tcschar (mpsc, ch);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
+		      temp | 0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay (MAGIC_FACTOR / gd->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int mpsc_putchar_sdma (char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset ((void *) p, 0, 8 * sizeof (unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;		/* x */
+	p[5] = (unsigned int) ch;	/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;	/* 0 */
+	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
+	p[2] = 0;		/* 8 */
+	p[3] = (unsigned int) &p[4];	/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int) &p[0];
+	p[11] = (unsigned int) &p[12];
+#endif
+
+	FLUSH_DCACHE (&p[0], &p[8]);
+
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	while (p[1] & DESC_OWNER_BIT) {
+		udelay (100);
+		INVALIDATE_DCACHE (&p[1], &p[2]);
+	}
+	return 0;
+}
+
+char mpsc_getchar_sdma (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER_BIT) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
+					  (CHANNEL * GALMPSC_REG_GAP));
+			temp |= (1 << 23);
+			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
+				      (CHANNEL * GALMPSC_REG_GAP), temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+
+int mpsc_test_char_debug (void)
+{
+	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
+		return 0;
+	else {
+		return 1;
+	}
+}
+
+
+int mpsc_test_char_sdma (void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER_BIT)
+		return 0;
+	else
+		return 1;
+}
+
+int mpsc_init (int baud)
+{
+	/* BRG CONFIG */
+	galbrg_set_baudrate (CHANNEL, baud);
+	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
+	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
+	galbrg_enable (CHANNEL);	/* Enable BRG */
+
+	/* Set up clock routing */
+	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
+
+	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
+	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
+
+	/* reset MPSC state */
+	galmpsc_shutdown (CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle (CHANNEL);
+	galsdma_set_rxle (CHANNEL);
+	galsdma_set_RC (CHANNEL, 0xf);
+	galsdma_set_SFM (CHANNEL);
+	galsdma_set_RFT (CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs (CHANNEL);
+	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
+	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
+	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+	mpsc_debug_init ();
+#endif
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
+#else
+	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
+#endif
+
+	return 0;
+}
+
+
+void mpsc_sdma_init (void)
+{
+/* Setup SDMA channel0 SDMA_CONFIG_REG*/
+	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
+
+/*  Enable MPSC-Window0 for DRAM Bank0   */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_0_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK0)) != true)
+		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window1    */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_1_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_1_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window2 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_2_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_2_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window3 */
+	if (galsdma_set_mem_space (MV64460_CUNIT_BASE_ADDR_WIN_3_BIT,
+				   MV64460_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_3_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
+			__FUNCTION__);
+
+/*  Setup MPSC0 access mode Window0 full access */
+	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
+			 (MV64460_SDMA_WIN_ACCESS_FULL <<
+			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/*  Setup MPSC1 access mode Window1 full access */
+	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
+			 (MV64460_SDMA_WIN_ACCESS_FULL <<
+			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/* Setup MPSC internal address space base address 	*/
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+
+/* no high address remap*/
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
+
+/* clear interrupt cause register for MPSC (fault register)*/
+	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
+}
+
+
+void mpsc_init2 (void)
+{
+	int i;
+
+#ifndef CONFIG_MPSC_DEBUG_PORT
+	mpsc_putchar = mpsc_putchar_sdma;
+	mpsc_getchar = mpsc_getchar_sdma;
+	mpsc_test_char = mpsc_test_char_sdma;
+#endif
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset ((void *) rx_desc_base, 0,
+		(RX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
+		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
+		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
+		rx_desc_base[i * 8] = 0x00100000;
+	}
+	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
+
+	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset ((void *) tx_desc_base, 0,
+		(TX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 3] =
+			(unsigned int) &tx_desc_base[i * 8 + 4];
+		tx_desc_base[i * 8 + 2] =
+			(unsigned int) &tx_desc_base[(i + 1) * 8];
+		tx_desc_base[i * 8 + 1] =
+			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i * 8] = 0x00010001;
+	}
+	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
+
+	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
+
+	udelay (100);
+
+	galsdma_enable_rx ();
+
+	return;
+}
+
+int galbrg_set_baudrate (int channel, int rate)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int clock;
+
+	galbrg_disable (channel);	/*ok */
+
+#ifdef ZUMA_NTL
+	/* from tclk */
+	clock = (CFG_TCLK / (16 * rate)) - 1;
+#else
+	clock = (CFG_TCLK / (16 * rate)) - 1;
+#endif
+
+	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
+
+	galbrg_enable (channel);
+
+	gd->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int galbrg_set_CDV (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_enable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x00010000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_disable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_set_clksrc (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
+	temp |= (value << 18);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+	return 0;
+}
+
+static int galbrg_set_CUV (int channel, int value)
+{
+	/* set CountUpValue */
+	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int galbrg_reset (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int galsdma_set_RFT (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_SFM (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_rxle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_txle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_RC (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_burstsize (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	case 8:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x3 << 12)));
+		break;
+
+	case 4:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x2 << 12)));
+		break;
+
+	case 2:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x1 << 12)));
+		break;
+
+	case 1:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x0 << 12)));
+		break;
+
+	default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int galmpsc_connect (int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_rx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_tx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_write_config_regs (int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
+			      0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
+			      0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int galmpsc_config_channel_regs (int mpsc)
+{
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt (mpsc, 0x3);
+	galmpsc_set_tcschar (mpsc, 0xab);
+
+	return 0;
+}
+
+static int galmpsc_set_brkcnt (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_tcschar (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_char_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_stop_bit_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFBFFF;
+	temp |= (value << 14);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_parity (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_enter_hunt (int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= 0x80000000;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
+	       MPSC_ENTER_HUNT) {
+		udelay (1);
+	}
+	return 0;
+}
+
+
+static int galmpsc_shutdown (int mpsc)
+{
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
+	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
+
+	udelay (100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
+
+	udelay (100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
+
+	udelay (100);
+
+	return 0;
+}
+
+static void galsdma_enable_rx (void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt (CHANNEL);
+}
+
+static int galmpsc_set_snoop (int mpsc, int value)
+{
+	int reg =
+		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
+		MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp = GTREGREAD (reg);
+
+	if (value)
+		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
+	else
+		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
+	GT_REG_WRITE (reg, temp);
+	return 0;
+}
+
+/*******************************************************************************
+* galsdma_set_mem_space - Set MV64460 IDMA memory decoding map.
+*
+* DESCRIPTION:
+*       the MV64460 SDMA has its own address decoding map that is de-coupled
+*       from the CPU interface address decoding windows. The SDMA channels
+*       share four address windows. Each region can be individually configured
+*       by this function by associating it to a target interface and setting
+*       base and size values.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*       The size must be a series of 1s followed by a series of zeros
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       True for success, false otherwise.
+*
+*******************************************************************************/
+
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress, unsigned int size)
+{
+	unsigned int temp;
+
+	if (size == 0) {
+		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+		return true;
+	}
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size < 0x10000) {
+		return false;
+	}
+
+	/* Align size and base to 64K */
+	baseAddress &= 0xffff0000;
+	size &= 0xffff0000;
+	temp = size >> 16;
+
+	/* Checking that the size is a sequence of '1' followed by a
+	   sequence of '0' starting from LSB to MSB. */
+	while ((temp > 0) && (temp & 0x1)) {
+		temp = temp >> 1;
+	}
+
+	if (temp != 0) {
+		GT_REG_WRITE (MV64460_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64460_CUNIT_SIZE0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		GT_RESET_REG_BITS (MV64460_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+	} else {
+		/* An invalid size was specified */
+		return false;
+	}
+	return true;
+}
diff --git a/board/Marvell/db64460/mpsc.h b/board/Marvell/db64460/mpsc.h
new file mode 100755
index 0000000..3cc0c0f
--- /dev/null
+++ b/board/Marvell/db64460/mpsc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64460 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT 		  (1 << 15)
+#define SDMA_TX_ABORT 		  (1 << 31)
+#define MPSC_TX_ABORT 		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c
new file mode 100755
index 0000000..ec5d581
--- /dev/null
+++ b/board/Marvell/db64460/mv_eth.c
@@ -0,0 +1,3182 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.c - header file for the polled mode GT ethernet driver
+ */
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+
+#include "mv_eth.h"
+
+/* enable Debug outputs */
+
+#undef DEBUG_MV_ETH
+
+#ifdef DEBUG_MV_ETH
+#define DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#undef MV64460_CHECKSUM_OFFLOAD
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+/* Definition for configuring driver */
+/* #define UPDATE_STATS_BY_SOFTWARE */
+#undef MV64460_RX_QUEUE_FILL_ON_TASK
+
+
+/* Constants */
+#define MAGIC_ETH_RUNNING		8031971
+#define MV64460_INTERNAL_SRAM_SIZE                      _256K
+#define EXTRA_BYTES 32
+#define WRAP       ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#ifdef MV64460_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL		0x00000000
+#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Read/Write to/from MV64460 internal registers */
+#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
+#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
+#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
+#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
+
+/* Static function declarations */
+static int mv64460_eth_real_open (struct eth_device *eth);
+static int mv64460_eth_real_stop (struct eth_device *eth);
+static struct net_device_stats *mv64460_eth_get_stats (struct eth_device
+						       *dev);
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
+static void mv64460_eth_update_stat (struct eth_device *dev);
+bool db64460_eth_start (struct eth_device *eth);
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset);
+int mv64460_eth_receive (struct eth_device *dev);
+
+int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length);
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+static void mv64460_eth_print_stat (struct eth_device *dev);
+#endif
+/* Processes a received packet */
+extern void NetReceive (volatile uchar *, int);
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/*************************************************
+ *Helper functions - used inside the driver only *
+ *************************************************/
+#ifdef DEBUG_MV_ETH
+void print_globals (struct eth_device *dev)
+{
+	printf ("Ethernet PRINT_Globals-Debug function\n");
+	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
+		(unsigned int) dev->priv);
+	printf ("Base Address for mv64460_eth_priv:	%08x\n",
+		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
+				 port_private));
+
+	printf ("GT Internal Base Address:	%08x\n",
+		INTERNAL_REG_BASE_ADDR);
+	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64460_TX_QUEUE_SIZE);
+	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64460_RX_QUEUE_SIZE);
+	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_rx_buffer_base[0],
+		(MV64460_RX_QUEUE_SIZE * MV64460_RX_BUFFER_SIZE) + 32);
+	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_tx_buffer_base[0],
+		(MV64460_TX_QUEUE_SIZE * MV64460_TX_BUFFER_SIZE) + 32);
+}
+#endif
+
+#define my_cpu_to_le32(x) my_le32_to_cpu((x))
+
+unsigned long my_le32_to_cpu (unsigned long x)
+{
+	return (((x & 0x000000ffU) << 24) |
+		((x & 0x0000ff00U) << 8) |
+		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
+}
+
+
+/**********************************************************************
+ * mv64460_eth_print_phy_status
+ *
+ * Prints gigabit ethenret phy status
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_print_phy_status (struct eth_device *dev)
+{
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	unsigned int port_status, phy_reg_data;
+
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		printf ("Ethernet port changed link status to DOWN\n");
+	} else {
+		port_status =
+			MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
+		printf ("Ethernet status port %d: Link up", port_num);
+		printf (", %s",
+			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
+		if (port_status & BIT4)
+			printf (", Speed 1 Gbps");
+		else
+			printf (", %s",
+				(port_status & BIT5) ? "Speed 100 Mbps" :
+				"Speed 10 Mbps");
+		printf ("\n");
+	}
+}
+
+/**********************************************************************
+ * u-boot entry functions for mv64460_eth
+ *
+ **********************************************************************/
+int db64460_eth_probe (struct eth_device *dev)
+{
+	return ((int) db64460_eth_start (dev));
+}
+
+int db64460_eth_poll (struct eth_device *dev)
+{
+	return mv64460_eth_receive (dev);
+}
+
+int db64460_eth_transmit (struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	mv64460_eth_xmit (dev, packet, length);
+	return 0;
+}
+
+void db64460_eth_disable (struct eth_device *dev)
+{
+	mv64460_eth_stop (dev);
+}
+
+
+void mv6446x_eth_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
+		dev = calloc (sizeof (*dev), 1);
+		if (!dev) {
+			printf ("%s: mv_enet%d allocation failure, %s\n",
+				__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf (dev->name, "mv_enet%d", devnum);
+
+#ifdef DEBUG
+		printf ("Initializing %s\n", dev->name);
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_r (s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		/* ronen - set the MAC addr in the HW */
+		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
+
+		dev->init = (void *) db64460_eth_probe;
+		dev->halt = (void *) ethernet_phy_reset;
+		dev->send = (void *) db64460_eth_transmit;
+		dev->recv = (void *) db64460_eth_poll;
+
+		ethernet_private = calloc (sizeof (*ethernet_private), 1);
+		dev->priv = (void *)ethernet_private;
+		if (!ethernet_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Private Device Structure");
+			free (dev);
+			return;
+		}
+		/* start with an zeroed ETH_PORT_INFO */
+		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
+		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+		/* set pointer to memory for stats data structure etc... */
+		port_private = calloc (sizeof (*ethernet_private), 1);
+		ethernet_private->port_private = (void *)port_private;
+		if (!port_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Port Private Device Structure");
+
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+
+		port_private->stats =
+			calloc (sizeof (struct net_device_stats), 1);
+		if (!port_private->stats) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Net stat Structure");
+
+			free (port_private);
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+		memset (ethernet_private->port_private, 0,
+			sizeof (struct mv64460_eth_priv));
+		switch (devnum) {
+		case 0:
+			ethernet_private->port_num = ETH_0;
+			break;
+		case 1:
+			ethernet_private->port_num = ETH_1;
+			break;
+		case 2:
+			ethernet_private->port_num = ETH_2;
+			break;
+		default:
+			printf ("Invalid device number %d\n", devnum);
+			break;
+		};
+
+		port_private->port_num = devnum;
+		/*
+		 * Read MIB counter on the GT in order to reset them,
+		 * then zero all the stats fields in memory
+		 */
+		mv64460_eth_update_stat (dev);
+		memset (port_private->stats, 0,
+			sizeof (struct net_device_stats));
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_r (s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+
+		DP (printf ("Allocating descriptor and buffer rings\n"));
+
+		ethernet_private->p_rx_desc_area_base[0] =
+			(ETH_RX_DESC *) memalign (16,
+						  RX_DESC_ALIGNED_SIZE *
+						  MV64460_RX_QUEUE_SIZE + 1);
+		ethernet_private->p_tx_desc_area_base[0] =
+			(ETH_TX_DESC *) memalign (16,
+						  TX_DESC_ALIGNED_SIZE *
+						  MV64460_TX_QUEUE_SIZE + 1);
+
+		ethernet_private->p_rx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64460_RX_QUEUE_SIZE *
+					   MV64460_TX_BUFFER_SIZE + 1);
+		ethernet_private->p_tx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64460_RX_QUEUE_SIZE *
+					   MV64460_TX_BUFFER_SIZE + 1);
+
+#ifdef DEBUG_MV_ETH
+		/* DEBUG OUTPUT prints adresses of globals */
+		print_globals (dev);
+#endif
+		eth_register (dev);
+
+	}
+	DP (printf ("%s: exit\n", __FUNCTION__));
+
+}
+
+/**********************************************************************
+ * mv64460_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ * / / ronen - changed the output to match  net/eth.c needs
+ * Output : nonzero of success , zero if fails.
+ * under construction
+ **********************************************************************/
+
+int mv64460_eth_open (struct eth_device *dev)
+{
+	return (mv64460_eth_real_open (dev));
+}
+
+/* Helper function for mv64460_eth_open */
+static int mv64460_eth_real_open (struct eth_device *dev)
+{
+
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	u32 port_status, phy_reg_data;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	/* ronen - when we update the MAC env params we only update dev->enetaddr
+	   see ./net/eth.c eth_set_enetaddr() */
+	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Clear the ethernet port interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+
+	/* Unmask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL);
+
+	/* Unmask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL_EXT);
+
+	/* Set phy address of the port */
+	ethernet_private->port_phy_addr = 0x8 + port_num;
+
+	/* Activate the DMA channels etc */
+	eth_port_init (ethernet_private);
+
+
+	/* "Allocate" setup TX rings */
+
+	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		port_private->tx_ring_size[queue] = MV64460_TX_QUEUE_SIZE;
+		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
+		ethernet_private->tx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
+			0, ethernet_private->tx_desc_area_size[queue]);
+
+		/* initialize tx desc ring with low level driver */
+		if (ether_init_tx_desc_ring
+		    (ethernet_private, ETH_Q0,
+		     port_private->tx_ring_size[queue],
+		     MV64460_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		     (unsigned int) ethernet_private->
+		     p_tx_desc_area_base[queue],
+		     (unsigned int) ethernet_private->
+		     p_tx_buffer_base[queue]) == false)
+			printf ("### Error initializing TX Ring\n");
+	}
+
+	/* "Allocate" setup RX rings */
+	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		/* Meantime RX Ring are fixed - but must be configurable by user */
+		port_private->rx_ring_size[queue] = MV64460_RX_QUEUE_SIZE;
+		size = (port_private->rx_ring_size[queue] *
+			RX_DESC_ALIGNED_SIZE);
+		ethernet_private->rx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
+			0, ethernet_private->rx_desc_area_size[queue]);
+		if ((ether_init_rx_desc_ring
+		     (ethernet_private, ETH_Q0,
+		      port_private->rx_ring_size[queue],
+		      MV64460_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		      (unsigned int) ethernet_private->
+		      p_rx_desc_area_base[queue],
+		      (unsigned int) ethernet_private->
+		      p_rx_buffer_base[queue])) == false)
+			printf ("### Error initializing RX Ring\n");
+	}
+
+	eth_port_start (ethernet_private);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num),
+		      (0x5 << 17) |
+		      (MV_REG_READ
+		       (MV64460_ETH_PORT_SERIAL_CONTROL_REG (port_num))
+		       & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+
+	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
+	port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num));
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		/* Reset PHY */
+		if ((ethernet_phy_reset (port_num)) != true) {
+			printf ("$$ Warnning: No link on port %d \n",
+				port_num);
+			return 0;
+		} else {
+			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+			if (!(phy_reg_data & 0x20)) {
+				printf ("### Error: Phy is not active\n");
+				return 0;
+			}
+		}
+	} else {
+		mv64460_eth_print_phy_status (dev);
+	}
+	port_private->eth_running = MAGIC_ETH_RUNNING;
+	return 1;
+}
+
+
+static int mv64460_eth_free_tx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop Tx Queues */
+	MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free TX rings */
+	DP (printf ("Clearing previously allocated TX queues... "));
+	for (queue = 0; queue < MV64460_TX_QUEUE_NUM; queue++) {
+		/* Free on TX rings */
+		for (p_tx_curr_desc =
+		     ethernet_private->p_tx_desc_area_base[queue];
+		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
+		      ethernet_private->p_tx_desc_area_base[queue] +
+		      ethernet_private->tx_desc_area_size[queue]);
+		     p_tx_curr_desc =
+		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
+				      TX_DESC_ALIGNED_SIZE)) {
+			/* this is inside for loop */
+			if (p_tx_curr_desc->return_info != 0) {
+				p_tx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+static int mv64460_eth_free_rx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free RX rings */
+	DP (printf ("Clearing previously allocated RX queues... "));
+	for (queue = 0; queue < MV64460_RX_QUEUE_NUM; queue++) {
+		/* Free preallocated skb's on RX rings */
+		for (p_rx_curr_desc =
+		     ethernet_private->p_rx_desc_area_base[queue];
+		     (((unsigned int) p_rx_curr_desc <
+		       ((unsigned int) ethernet_private->
+			p_rx_desc_area_base[queue] +
+			ethernet_private->rx_desc_area_size[queue])));
+		     p_rx_curr_desc =
+		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
+				      RX_DESC_ALIGNED_SIZE)) {
+			if (p_rx_curr_desc->return_info != 0) {
+				p_rx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+/**********************************************************************
+ * mv64460_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ *********************************************************************/
+
+int mv64460_eth_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Disable all gigE address decoder */
+	MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
+	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
+	mv64460_eth_real_stop (dev);
+
+	return 0;
+};
+
+/* Helper function for mv64460_eth_stop */
+
+static int mv64460_eth_real_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	mv64460_eth_free_tx_rings (dev);
+	mv64460_eth_free_rx_rings (dev);
+
+	eth_port_reset (ethernet_private->port_num);
+	/* Disable ethernet port interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+	/* Mask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_MASK_REG (port_num), 0);
+	/* Mask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64460_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
+	MV_RESET_REG_BITS (MV64460_CPU_INTERRUPT0_MASK_HIGH,
+			   BIT0 << port_num);
+	/* Print Network statistics */
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+	/*
+	 * Print statistics (only if ethernet is running),
+	 * then zero all the stats fields in memory
+	 */
+	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
+		port_private->eth_running = 0;
+		mv64460_eth_print_stat (dev);
+	}
+	memset (port_private->stats, 0, sizeof (struct net_device_stats));
+#endif
+	DP (printf ("\nEthernet stopped ... \n"));
+	return 0;
+}
+
+
+/**********************************************************************
+ * mv64460_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ *         dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ **********************************************************************/
+
+int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
+		      int dataSize)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	ETH_FUNC_RET_STATUS status;
+	struct net_device_stats *stats;
+	ETH_FUNC_RET_STATUS release_result;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	stats = port_private->stats;
+
+	/* Update packet info data structure */
+	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
+	pkt_info.byte_cnt = dataSize;
+	pkt_info.buf_ptr = (unsigned int) dataPtr;
+
+	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
+	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
+		printf ("Error on transmitting packet ..");
+		if (status == ETH_QUEUE_FULL)
+			printf ("ETH Queue is full. \n");
+		if (status == ETH_QUEUE_LAST_RESOURCE)
+			printf ("ETH Queue: using last available resource. \n");
+		goto error;
+	}
+
+	/* Update statistics and start of transmittion time */
+	stats->tx_bytes += dataSize;
+	stats->tx_packets++;
+
+	/* Check if packet(s) is(are) transmitted correctly (release everything) */
+	do {
+		release_result =
+			eth_tx_return_desc (ethernet_private, ETH_Q0,
+					    &pkt_info);
+		switch (release_result) {
+		case ETH_OK:
+			DP (printf ("descriptor released\n"));
+			if (pkt_info.cmd_sts & BIT0) {
+				printf ("Error in TX\n");
+				stats->tx_errors++;
+
+			}
+			break;
+		case ETH_RETRY:
+			DP (printf ("transmission still in process\n"));
+			break;
+
+		case ETH_ERROR:
+			printf ("routine can not access Tx desc ring\n");
+			break;
+
+		case ETH_END_OF_JOB:
+			DP (printf ("the routine has nothing to release\n"));
+			break;
+		default:	/* should not happen */
+			break;
+		}
+	} while (release_result == ETH_OK);
+
+
+	return 0;		/* success */
+      error:
+	return 1;		/* Failed - higher layers will free the skb */
+}
+
+/**********************************************************************
+ * mv64460_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ *         max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ **********************************************************************/
+
+int mv64460_eth_receive (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	struct net_device_stats *stats;
+
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
+		ETH_OK)) {
+
+#ifdef DEBUG_MV_ETH
+		if (pkt_info.byte_cnt != 0) {
+			printf ("%s: Received %d byte Packet @ 0x%x\n",
+				__FUNCTION__, pkt_info.byte_cnt,
+				pkt_info.buf_ptr);
+		}
+#endif
+		/* Update statistics. Note byte count includes 4 byte CRC count */
+		stats->rx_packets++;
+		stats->rx_bytes += pkt_info.byte_cnt;
+
+		/*
+		 * In case received a packet without first / last bits on OR the error
+		 * summary bit is on, the packets needs to be dropeed.
+		 */
+		if (((pkt_info.
+		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+			stats->rx_dropped++;
+
+			printf ("Received packet spread on multiple descriptors\n");
+
+			/* Is this caused by an error ? */
+			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
+				stats->rx_errors++;
+			}
+
+			/* free these descriptors again without forwarding them to the higher layers */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+			/* /free these descriptors again */
+		} else {
+
+/* !!! call higher layer processing */
+#ifdef DEBUG_MV_ETH
+			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
+#endif
+			/* let the upper layer handle the packet */
+			NetReceive ((uchar *) pkt_info.buf_ptr,
+				    (int) pkt_info.byte_cnt);
+
+/* **************************************************************** */
+/* free descriptor  */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+			DP (printf
+			    ("RX: pkt_info.buf_ptr =	%x\n",
+			     pkt_info.buf_ptr));
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+
+/* **************************************************************** */
+
+		}
+	}
+	mv64460_eth_get_stats (dev);	/* update statistics */
+	return 1;
+}
+
+/**********************************************************************
+ * mv64460_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ **********************************************************************/
+
+static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64460_eth_update_stat (dev);
+
+	return port_private->stats;
+}
+
+
+/**********************************************************************
+ * mv64460_eth_update_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_update_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+	volatile unsigned int dummy;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	stats->rx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_RECEIVED);
+	stats->tx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_SENT);
+	stats->rx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
+	/*
+	 * Ideally this should be as follows -
+	 *
+	 *   stats->rx_bytes   += stats->rx_bytes +
+	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
+	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
+	 *
+	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
+	 * is just a dummy read for proper work of the GigE port
+	 */
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
+	stats->tx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
+	stats->rx_errors += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MAC_RECEIVE_ERROR);
+
+	/* Rx dropped is for received packet with CRC error */
+	stats->rx_dropped +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_BAD_CRC_EVENT);
+	stats->multicast += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
+	stats->collisions +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_COLLISION) +
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_LATE_COLLISION);
+	/* detailed rx errors */
+	stats->rx_length_errors +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_UNDERSIZE_RECEIVED)
+		+
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_OVERSIZE_RECEIVED);
+	/* detailed tx errors */
+}
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+/**********************************************************************
+ * mv64460_eth_print_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64460_eth_print_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64460_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64460_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	printf ("\n### Network statistics: ###\n");
+	printf ("--------------------------\n");
+	printf (" Packets received:		%ld\n", stats->rx_packets);
+	printf (" Packets send:			%ld\n", stats->tx_packets);
+	printf (" Received bytes:		%ld\n", stats->rx_bytes);
+	printf (" Send bytes:			%ld\n", stats->tx_bytes);
+	if (stats->rx_errors != 0)
+		printf (" Rx Errors:			%ld\n",
+			stats->rx_errors);
+	if (stats->rx_dropped != 0)
+		printf (" Rx dropped (CRC Errors):	%ld\n",
+			stats->rx_dropped);
+	if (stats->multicast != 0)
+		printf (" Rx mulicast frames:		%ld\n",
+			stats->multicast);
+	if (stats->collisions != 0)
+		printf (" No. of collisions:		%ld\n",
+			stats->collisions);
+	if (stats->rx_length_errors != 0)
+		printf (" Rx length errors:		%ld\n",
+			stats->rx_length_errors);
+}
+#endif
+
+/**************************************************************************
+ *network_start - Network Kick Off Routine UBoot
+ *Inputs :
+ *Outputs :
+ **************************************************************************/
+
+bool db64460_eth_start (struct eth_device *dev)
+{
+	return (mv64460_eth_open (dev));	/* calls real open */
+}
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/*
+ * based on Linux code
+ * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ */
+
+/********************************************************************************
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ *       This file introduce low level API to Marvell's Gigabit Ethernet
+ *		controller. This Gigabit Ethernet Controller driver API controls
+ *		1) Operations (i.e. port init, start, reset etc').
+ *		2) Data flow (i.e. port send, receive etc').
+ *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
+ *		struct.
+ *		This struct includes user configuration information as well as
+ *		driver internal data needed for its operations.
+ *
+ *		Supported Features:
+ *		- This low level driver is OS independent. Allocating memory for
+ *		  the descriptor rings and buffers are not within the scope of
+ *		  this driver.
+ *		- The user is free from Rx/Tx queue managing.
+ *		- This low level driver introduce functionality API that enable
+ *		  the to operate Marvell's Gigabit Ethernet Controller in a
+ *		  convenient way.
+ *		- Simple Gigabit Ethernet port operation API.
+ *		- Simple Gigabit Ethernet port data flow API.
+ *		- Data flow and operation API support per queue functionality.
+ *		- Support cached descriptors for better performance.
+ *		- Enable access to all four DRAM banks and internal SRAM memory
+ *		  spaces.
+ *		- PHY access and control API.
+ *		- Port control register configuration API.
+ *		- Full control over Unicast and Multicast MAC configurations.
+ *
+ *		Operation flow:
+ *
+ *		Initialization phase
+ *		This phase complete the initialization of the ETH_PORT_INFO
+ *		struct.
+ *		User information regarding port configuration has to be set
+ *		prior to calling the port initialization routine. For example,
+ *		the user has to assign the port_phy_addr field which is board
+ *		depended parameter.
+ *		In this phase any port Tx/Rx activity is halted, MIB counters
+ *		are cleared, PHY address is set according to user parameter and
+ *		access to DRAM and internal SRAM memory spaces.
+ *
+ *		Driver ring initialization
+ *		Allocating memory for the descriptor rings and buffers is not
+ *		within the scope of this driver. Thus, the user is required to
+ *		allocate memory for the descriptors ring and buffers. Those
+ *		memory parameters are used by the Rx and Tx ring initialization
+ *		routines in order to curve the descriptor linked list in a form
+ *		of a ring.
+ *		Note: Pay special attention to alignment issues when using
+ *		cached descriptors/buffers. In this phase the driver store
+ *		information in the ETH_PORT_INFO struct regarding each queue
+ *		ring.
+ *
+ *		Driver start
+ *		This phase prepares the Ethernet port for Rx and Tx activity.
+ *		It uses the information stored in the ETH_PORT_INFO struct to
+ *		initialize the various port registers.
+ *
+ *		Data flow:
+ *		All packet references to/from the driver are done using PKT_INFO
+ *		struct.
+ *		This struct is a unified struct used with Rx and Tx operations.
+ *		This way the user is not required to be familiar with neither
+ *		Tx nor Rx descriptors structures.
+ *		The driver's descriptors rings are management by indexes.
+ *		Those indexes controls the ring resources and used to indicate
+ *		a SW resource error:
+ *		'current'
+ *		This index points to the current available resource for use. For
+ *		example in Rx process this index will point to the descriptor
+ *		that will be passed to the user upon calling the receive routine.
+ *		In Tx process, this index will point to the descriptor
+ *		that will be assigned with the user packet info and transmitted.
+ *		'used'
+ *		This index points to the descriptor that need to restore its
+ *		resources. For example in Rx process, using the Rx buffer return
+ *		API will attach the buffer returned in packet info to the
+ *		descriptor pointed by 'used'. In Tx process, using the Tx
+ *		descriptor return will merely return the user packet info with
+ *		the command status of  the transmitted buffer pointed by the
+ *		'used' index. Nevertheless, it is essential to use this routine
+ *		to update the 'used' index.
+ *		'first'
+ *		This index supports Tx Scatter-Gather. It points to the first
+ *		descriptor of a packet assembled of multiple buffers. For example
+ *		when in middle of Such packet we have a Tx resource error the
+ *		'curr' index get the value of 'first' to indicate that the ring
+ *		returned to its state before trying to transmit this packet.
+ *
+ *		Receive operation:
+ *		The eth_port_receive API set the packet information struct,
+ *		passed by the caller, with received information from the
+ *		'current' SDMA descriptor.
+ *		It is the user responsibility to return this resource back
+ *		to the Rx descriptor ring to enable the reuse of this source.
+ *		Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ *		Transmit operation:
+ *		The eth_port_send API supports Scatter-Gather which enables to
+ *		send a packet spanned over multiple buffers. This means that
+ *		for each packet info structure given by the user and put into
+ *		the Tx descriptors ring, will be transmitted only if the 'LAST'
+ *		bit will be set in the packet info command status field. This
+ *		API also consider restriction regarding buffer alignments and
+ *		sizes.
+ *		The user must return a Tx resource after ensuring the buffer
+ *		has been transmitted to enable the Tx ring indexes to update.
+ *
+ *		BOARD LAYOUT
+ *		This device is on-board.  No jumper diagram is necessary.
+ *
+ *		EXTERNAL INTERFACE
+ *
+ *       Prior to calling the initialization routine eth_port_init() the user
+ *	 must set the following fields under ETH_PORT_INFO struct:
+ *       port_num             User Ethernet port number.
+ *       port_phy_addr		    User PHY address of Ethernet port.
+ *       port_mac_addr[6]	    User defined port MAC address.
+ *       port_config          User port configuration value.
+ *       port_config_extend    User port config extend value.
+ *       port_sdma_config      User port SDMA config value.
+ *       port_serial_control   User port serial control value.
+ *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
+ *       *port_private        User scratch pad for user specific data structures.
+ *
+ *       This driver introduce a set of default values:
+ *       PORT_CONFIG_VALUE           Default port configuration value
+ *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
+ *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
+ *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
+ *
+ *		This driver data flow is done using the PKT_INFO struct which is
+ *		a unified struct for Rx and Tx operations:
+ *		byte_cnt	Tx/Rx descriptor buffer byte count.
+ *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
+ *		cmd_sts		Tx/Rx descriptor command status.
+ *		buf_ptr		Tx/Rx descriptor buffer pointer.
+ *		return_info	Tx/Rx user resource return information.
+ *
+ *
+ *		EXTERNAL SUPPORT REQUIREMENTS
+ *
+ *		This driver requires the following external support:
+ *
+ *		D_CACHE_FLUSH_LINE (address, address offset)
+ *
+ *		This macro applies assembly code to flush and invalidate cache
+ *		line.
+ *		address        - address base.
+ *		address offset - address offset
+ *
+ *
+ *		CPU_PIPE_FLUSH
+ *
+ *		This macro applies assembly code to flush the CPU pipeline.
+ *
+ *******************************************************************************/
+/* includes */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
+
+#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
+ (1 << (8 + tx_queue)))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
+
+#define CURR_RFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
+
+#define CURR_RFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_RFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
+
+#define USED_RFD_SET(p_used_desc, queue)\
+(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
+
+
+#define CURR_TFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
+
+#define CURR_TFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_TFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
+
+#define USED_TFD_SET(p_used_desc, queue) \
+ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
+
+#define FIRST_TFD_GET(p_first_desc, queue) \
+ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
+
+#define FIRST_TFD_SET(p_first_desc, queue) \
+ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
+
+
+/* Macros that save access to desc in order to find next desc pointer  */
+#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
+
+#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
+
+#define LINK_UP_TIMEOUT		100000
+#define PHY_BUSY_TIMEOUT    10000000
+
+/* locals */
+
+/* PHY routines */
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
+static int ethernet_phy_get (ETH_PORT eth_port_num);
+
+/* Ethernet Port routines */
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param);
+static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option);
+#if 0				/* FIXME */
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option);
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option);
+#endif
+
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count);
+
+void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
+
+
+typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
+u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64460_CS_0_BASE_ADDR);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64460_CS_1_BASE_ADDR);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64460_CS_2_BASE_ADDR);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64460_CS_3_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_dram_bank_size (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64460_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64460_CS_0_SIZE);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64460_CS_1_SIZE);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64460_CS_2_SIZE);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64460_CS_3_SIZE);
+	result += 1;
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_internal_sram_base (void)
+{
+	u32 result;
+
+	result = MV_REG_READ (MV64460_INTEGRATED_SRAM_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+/*******************************************************************************
+* eth_port_init - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+*       This function prepares the ethernet port to start its activity:
+*       1) Completes the ethernet port driver struct initialization toward port
+*           start routine.
+*       2) Resets the device to a quiescent state in case of warm reboot.
+*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+*       4) Clean MAC tables. The reset status of those tables is unknown.
+*       5) Set PHY address.
+*       Note: Call this routine prior to eth_port_start routine and after setting
+*       user values in the user fields of Ethernet port control struct (i.e.
+*       port_phy_addr).
+*
+* INPUT:
+*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       See description.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	ETH_WIN_PARAM win_param;
+
+	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
+	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+	p_eth_port_ctrl->port_rx_queue_command = 0;
+	p_eth_port_ctrl->port_tx_queue_command = 0;
+
+	/* Zero out SW structs */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->rx_resource_err[queue] = false;
+	}
+
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->tx_resource_err[queue] = false;
+	}
+
+	eth_port_reset (p_eth_port_ctrl->port_num);
+
+	/* Set access parameters for DRAM bank 0 */
+	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
+	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
+	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 1 */
+	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
+	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 2 */
+	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
+	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 3 */
+	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
+	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for Internal SRAM */
+	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
+	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
+	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
+	win_param.high_addr = 0;
+	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
+	win_param.size = MV64460_INTERNAL_SRAM_SIZE;	/* Get bank size */
+	win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
+
+	ethernet_phy_set (p_eth_port_ctrl->port_num,
+			  p_eth_port_ctrl->port_phy_addr);
+
+	return;
+
+}
+
+/*******************************************************************************
+* eth_port_start - Start the Ethernet port activity.
+*
+* DESCRIPTION:
+*       This routine prepares the Ethernet port for Rx and Tx activity:
+*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
+*           for Tx and ether_init_rx_desc_ring for Rx)
+*       2. Initialize and enable the Ethernet configuration port by writing to
+*           the port's configuration and command registers.
+*       3. Initialize and enable the SDMA by writing to the SDMA's
+*    configuration and command registers.
+*       After completing these steps, the ethernet port SDMA can starts to
+*       perform Rx and Tx activities.
+*
+*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
+*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
+*       ether_init_rx_desc_ring for Rx queues).
+*
+* INPUT:
+*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       Ethernet port is ready to receive and transmit.
+*
+* RETURN:
+*       false if the port PHY is not up.
+*       true otherwise.
+*
+*******************************************************************************/
+static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	unsigned int phy_reg_data;
+	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
+
+
+	/* Assignment of Tx CTRP of given queue */
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_GET (p_tx_curr_desc, queue);
+		MV_REG_WRITE ((MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_tx_curr_desc));
+
+	}
+
+	/* Assignment of Rx CRDP of given queue */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_GET (p_rx_curr_desc, queue);
+		MV_REG_WRITE ((MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_rx_curr_desc));
+
+		if (p_rx_curr_desc != NULL)
+			/* Add the assigned Ethernet address to the port's address table */
+			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
+					      p_eth_port_ctrl->port_mac_addr,
+					      queue);
+	}
+
+	/* Assign port configuration and command. */
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config);
+
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config_extend);
+
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      p_eth_port_ctrl->port_serial_control);
+
+	MV_SET_REG_BITS (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+			 ETH_SERIAL_PORT_ENABLE);
+
+	/* Assign port SDMA configuration */
+	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_sdma_config);
+
+	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
+		      (eth_port_num), 0x3fffffff);
+	MV_REG_WRITE (MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
+		      (eth_port_num), 0x03fffcff);
+	/* Turn off the port/queue bandwidth limitation */
+	MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
+
+	/* Enable port Rx. */
+	MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_rx_queue_command);
+
+	/* Check if link is up */
+	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+	if (!(phy_reg_data & 0x20))
+		return false;
+
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr_set - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+*		This function Set the port Ethernet MAC address.
+*
+* INPUT:
+*	ETH_PORT eth_port_num     Port number.
+*	char *        p_addr		Address to be set
+*	ETH_QUEUE 	  queue		Rx queue number for this MAC address.
+*
+* OUTPUT:
+*	Set MAC address low and high registers. also calls eth_port_uc_addr()
+*       To set the unicast table with the proper information.
+*
+* RETURN:
+*	N/A.
+*
+*******************************************************************************/
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr, ETH_QUEUE queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+		(p_addr[2] << 8) | (p_addr[3] << 0);
+
+	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
+	MV_REG_WRITE (MV64460_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
+
+	/* Accept frames of this address */
+	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
+
+	return;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+*	This function locates the proper entry in the Unicast table for the
+*	specified MAC nibble and sets its properties according to function
+*	parameters.
+*
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char uc_nibble		Unicast MAC Address last nibble.
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	This function add/removes MAC addresses from the port unicast address
+*	table.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_uc_addr (ETH_PORT eth_port_num,
+			      unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
+	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified unicast DA table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+#if 0				/* FIXME */
+/*******************************************************************************
+* eth_port_mc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This API controls the MV device MAC multicast support.
+*	The MV device supports multicast using two tables:
+*	1) Special Multicast Table for MAC addresses of the form
+*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	   Table entries in the DA-Filter table.
+*	   In this case, the function calls eth_port_smc_addr() routine to set the
+*	   Special Multicast Table.
+*	2) Other Multicast Table for multicast of another type. A CRC-8bit
+*	   is used as an index to the Other Multicast Table entries in the
+*	   DA-Filter table.
+*	   In this case, the function calculates the CRC-8bit value and calls
+*	   eth_port_omc_addr() routine to set the Other Multicast Table.
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char 	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if add_address_table_entry( ) failed.
+*
+*******************************************************************************/
+static void eth_port_mc_addr (ETH_PORT eth_port_num,
+			      unsigned char *p_addr,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+	unsigned char crc_result = 0;
+	int mac_array[48];
+	int crc[8];
+	int i;
+
+
+	if ((p_addr[0] == 0x01) &&
+	    (p_addr[1] == 0x00) &&
+	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
+
+		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
+	else {
+		/* Calculate CRC-8 out of the given address */
+		mac_h = (p_addr[0] << 8) | (p_addr[1]);
+		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
+			(p_addr[4] << 8) | (p_addr[5] << 0);
+
+		for (i = 0; i < 32; i++)
+			mac_array[i] = (mac_l >> i) & 0x1;
+		for (i = 32; i < 48; i++)
+			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
+
+
+		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
+			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
+			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
+			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
+			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
+			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[0];
+
+		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
+			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
+			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
+			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
+			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
+			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
+			mac_array[0];
+
+		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
+			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
+			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
+			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
+			mac_array[2] ^ mac_array[1] ^ mac_array[0];
+
+		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
+			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
+			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
+			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
+			mac_array[2] ^ mac_array[1];
+
+		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
+			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
+			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
+			mac_array[2];
+
+		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
+			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
+			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
+			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
+			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
+			mac_array[3];
+
+		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
+			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
+			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
+			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[6] ^ mac_array[5] ^ mac_array[4];
+
+		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
+			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
+			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
+			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
+			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[5];
+
+		for (i = 0; i < 8; i++)
+			crc_result = crc_result | (crc[i] << i);
+
+		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
+	}
+	return;
+}
+
+/*******************************************************************************
+* eth_port_smc_addr - Special Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device special MAC multicast support.
+*	The Special Multicast Table for MAC addresses supports MAC of the form
+*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	Table entries in the DA-Filter table.
+*	This function set the Special Multicast Table appropriate entry
+*	according to the argument given.
+*
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char 	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int smc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the SMC table entry */
+	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
+	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_omc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device Other MAC multicast support.
+*	The Other Multicast Table is used for multicast of another type.
+*	A CRC-8bit is used as an index to the Other Multicast Table entries
+*	in the DA-Filter table.
+*	The function gets the CRC-8bit value from the calling routine and
+*      set the Other Multicast Table appropriate entry according to the
+*	CRC-8 argument given.
+*
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char 	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int omc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the OMC table entry */
+	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
+	reg_offset = crc8 % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+#endif
+
+/*******************************************************************************
+* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+*
+* DESCRIPTION:
+*       Go through all the DA filter tables (Unicast, Special Multicast & Other
+*       Multicast) and set each entry to 0.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Multicast and Unicast packets are rejected.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index <= 0xC; table_index += 4)
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num) + table_index), 0);
+
+	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		MV_REG_WRITE ((MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+	}
+}
+
+/*******************************************************************************
+* eth_clear_mib_counters - Clear all MIB counters
+*
+* DESCRIPTION:
+*       This function clears all MIB counters of a specific ethernet port.
+*       A read from the MIB counter will reset the counter.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       After reading all MIB counters, the counters resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+static void eth_clear_mib_counters (ETH_PORT eth_port_num)
+{
+	int i;
+	unsigned int dummy;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
+	     i += 4)
+		dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE
+				      (eth_port_num) + i));
+
+	return;
+}
+
+/*******************************************************************************
+* eth_read_mib_counter - Read a MIB counter
+*
+* DESCRIPTION:
+*       This function reads a MIB counter of a specific ethernet port.
+*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
+*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
+*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
+*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
+*
+* OUTPUT:
+*       After reading the MIB counter, the counter resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset)
+{
+	return (MV_REG_READ (MV64460_ETH_MIB_COUNTERS_BASE (eth_port_num)
+			     + mib_offset));
+}
+
+/*******************************************************************************
+* ethernet_phy_set - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+*       This routine set the ethernet port PHY address according to given
+*       parameter.
+*
+* INPUT:
+*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Set PHY Address Register with given PHY address parameter.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
+
+	reg_data &= ~(0x1F << (5 * eth_port_num));
+	reg_data |= (phy_addr << (5 * eth_port_num));
+
+	MV_REG_WRITE (MV64460_ETH_PHY_ADDR_REG, reg_data);
+
+	return;
+}
+
+/*******************************************************************************
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ *       This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       PHY address.
+ *
+ *******************************************************************************/
+static int ethernet_phy_get (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64460_ETH_PHY_ADDR_REG);
+
+	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/*******************************************************************************
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to reset the ethernet port PHY.
+ *       The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ *       None.
+ *
+*******************************************************************************/
+static bool ethernet_phy_reset (ETH_PORT eth_port_num)
+{
+	unsigned int time_out = 50;
+	unsigned int phy_reg_data;
+
+	/* Reset the PHY */
+	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
+	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
+	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
+
+	/* Poll on the PHY LINK */
+	do {
+		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+		if (time_out-- == 0)
+			return false;
+	}
+	while (!(phy_reg_data & 0x20));
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ * 	This routine resets the chip by aborting any SDMA engine activity and
+ *      clearing the MIB counters. The Receiver and the Transmit unit are in
+ *      idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       Channel activity is halted.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_port_reset (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Tx activity to terminate. */
+		do {
+			/* Check port cause register that all Tx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Rx activity to terminate. */
+		do {
+			/* Check port cause register that all Rx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+
+	/* Clear all MIB counters */
+	eth_clear_mib_counters (eth_port_num);
+
+	/* Reset the Enable bit in the Configuration Register */
+	reg_data =
+		MV_REG_READ (MV64460_ETH_PORT_SERIAL_CONTROL_REG
+			     (eth_port_num));
+	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+	MV_REG_WRITE (MV64460_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      reg_data);
+
+	return;
+}
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function sets specified bits in the given ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are set in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_set_config_reg (ETH_PORT eth_port_num,
+				     unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg =
+		MV_REG_READ (MV64460_ETH_PORT_CONFIG_REG (eth_port_num));
+	eth_config_reg |= value;
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* FIXME */
+/*******************************************************************************
+ * ethernet_reset_config_reg - Reset specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function resets specified bits in the given Ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are reset in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
+				       unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	eth_config_reg &= ~value;
+	MV_REG_WRITE (MV64460_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ *       This function returns the configuration register value of the given
+ *       ethernet port.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       Port configuration register value.
+ *
+ *******************************************************************************/
+static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64460_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	return eth_config_reg;
+}
+
+#endif
+
+/*******************************************************************************
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform PHY register read.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       unsigned int   phy_reg   PHY register address offset.
+ *       unsigned int   *value   Register value buffer.
+ *
+ * OUTPUT:
+ *       Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ *       false if the PHY is busy or read data is not in valid state.
+ *       true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
+				   unsigned int phy_reg, unsigned int *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+#define PHY_UPDATE_TIMEOUT	10000
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform writes to PHY registers.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int   phy_reg   PHY register address offset.
+ *      unsigned int    value   Register value.
+ *
+ * OUTPUT:
+ *      Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ *      false if the PHY is busy.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
+				    unsigned int phy_reg, unsigned int value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64460_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64460_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return true;
+}
+
+/*******************************************************************************
+ * eth_set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * DESCRIPTION:
+ *       This function configures the address decode parameters for the Gigabit
+ *       Ethernet Controller according the given parameters struct.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       ETH_WIN_PARAM  *param   Address decode parameter struct.
+ *
+ * OUTPUT:
+ *       An access window is opened using the given access parameters.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param)
+{
+	unsigned int access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = MV_REG_READ (MV64460_ETH_ACCESS_PROTECTION_REG
+				       (eth_port_num));
+	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	MV_REG_WRITE (MV64460_ETH_ACCESS_PROTECTION_REG (eth_port_num),
+		      access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	MV_REG_WRITE ((MV64460_ETH_SIZE_REG_0 +
+		       (ETH_SIZE_REG_GAP * param->win)),
+		      (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	MV_REG_WRITE ((MV64460_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
+		      (param->target | param->attributes | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		MV_REG_WRITE ((MV64460_ETH_HIGH_ADDR_REMAP_REG_0 +
+			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
+			      param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		MV_RESET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
+				   (1 << param->win));
+	else
+		MV_SET_REG_BITS (MV64460_ETH_BASE_ADDR_ENABLE_REG,
+				 (1 << param->win));
+}
+
+/*******************************************************************************
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Rx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *      int 			rx_desc_num       Number of Rx descriptors
+ *      int 			rx_buff_size      Size of Rx buffer
+ *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
+ *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE rx_queue,
+				     int rx_desc_num,
+				     int rx_buff_size,
+				     unsigned int rx_desc_base_addr,
+				     unsigned int rx_buff_base_addr)
+{
+	ETH_RX_DESC *p_rx_desc;
+	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
+	p_rx_prev_desc = p_rx_desc;
+	buffer_addr = rx_buff_base_addr;
+
+	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (rx_buff_base_addr & 0xF)
+		return false;
+
+	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+		return false;
+
+	/* Rx buffers must be 64-bit aligned.       */
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return false;
+
+	/* initialize the Rx descriptors ring */
+	for (ix = 0; ix < rx_desc_num; ix++) {
+		p_rx_desc->buf_size = rx_buff_size;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->cmd_sts =
+			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+		p_rx_desc->next_desc_ptr =
+			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
+		p_rx_desc->buf_ptr = buffer_addr;
+		p_rx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
+		buffer_addr += rx_buff_size;
+		p_rx_prev_desc = p_rx_desc;
+		p_rx_desc = (ETH_RX_DESC *)
+			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
+	}
+
+	/* Closing Rx descriptors ring */
+	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
+	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
+
+	/* Save Rx desc pointer to driver struct. */
+	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+
+	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
+		(ETH_RX_DESC *) rx_desc_base_addr;
+	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
+		rx_desc_num * RX_DESC_ALIGNED_SIZE;
+
+	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Tx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *      int 			tx_desc_num       Number of Tx descriptors
+ *      int 			tx_buff_size      Size of Tx buffer
+ *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
+ *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE tx_queue,
+				     int tx_desc_num,
+				     int tx_buff_size,
+				     unsigned int tx_desc_base_addr,
+				     unsigned int tx_buff_base_addr)
+{
+
+	ETH_TX_DESC *p_tx_desc;
+	ETH_TX_DESC *p_tx_prev_desc;
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	/* save the first desc pointer to link with the last descriptor */
+	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
+	p_tx_prev_desc = p_tx_desc;
+	buffer_addr = tx_buff_base_addr;
+
+	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (tx_buff_base_addr & 0xF)
+		return false;
+
+	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
+	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
+		return false;
+
+	/* Initialize the Tx descriptors ring */
+	for (ix = 0; ix < tx_desc_num; ix++) {
+		p_tx_desc->byte_cnt = 0x0000;
+		p_tx_desc->l4i_chk = 0x0000;
+		p_tx_desc->cmd_sts = 0x00000000;
+		p_tx_desc->next_desc_ptr =
+			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
+
+		p_tx_desc->buf_ptr = buffer_addr;
+		p_tx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
+		buffer_addr += tx_buff_size;
+		p_tx_prev_desc = p_tx_desc;
+		p_tx_desc = (ETH_TX_DESC *)
+			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
+
+	}
+	/* Closing Tx descriptors ring */
+	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
+	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
+	/* Set Tx desc pointer in driver struct. */
+	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+
+	/* Init Tx ring base and size parameters */
+	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
+		(ETH_TX_DESC *) tx_desc_base_addr;
+	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
+		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
+
+	/* Add the queue to the list of Tx queues of this port */
+	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ *	This routine send a given packet described by p_pktinfo parameter. It
+ *      supports transmitting of a packet spaned over multiple buffers. The
+ *      routine updates 'curr' and 'first' indexes according to the packet
+ *      segment passed to the routine. In case the packet segment is first,
+ *      the 'first' index is update. In any case, the 'curr' index is updated.
+ *      If the routine get into Tx resource error it assigns 'curr' index as
+ *      'first'. This way the function can abort Tx process of multiple
+ *      descriptors per packet.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ *      ETH_QUEUE_FULL in case of Tx resource error.
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
+					  ETH_QUEUE tx_queue,
+					  PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_first;
+	volatile ETH_TX_DESC *p_tx_desc_curr;
+	volatile ETH_TX_DESC *p_tx_next_desc_curr;
+	volatile ETH_TX_DESC *p_tx_desc_used;
+	unsigned int command_status;
+
+	/* Do not process Tx ring in case of Tx ring resource error */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		return ETH_QUEUE_FULL;
+
+	/* Get the Tx Desc ring indexes */
+	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+
+	if (p_tx_desc_curr == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
+	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+	if (command_status & (ETH_TX_FIRST_DESC)) {
+		/* Update first desc */
+		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
+		p_tx_desc_first = p_tx_desc_curr;
+	} else {
+		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+		command_status |= ETH_BUFFER_OWNED_BY_DMA;
+	}
+
+	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
+	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
+	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
+	if (p_pkt_info->byte_cnt <= 8) {
+		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
+		return ETH_ERROR;
+
+		p_tx_desc_curr->buf_ptr =
+			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
+		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
+			    p_pkt_info->byte_cnt);
+	} else
+		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
+
+	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
+	p_tx_desc_curr->return_info = p_pkt_info->return_info;
+
+	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
+		/* Set last desc with DMA ownership and interrupt enable. */
+		p_tx_desc_curr->cmd_sts = command_status |
+			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+		if (p_tx_desc_curr != p_tx_desc_first)
+			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+
+		/* Flush CPU pipe */
+
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
+		CPU_PIPE_FLUSH;
+
+		/* Apply send command */
+		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
+
+		/* Finish Tx packet. Update first desc in case of Tx resource error */
+		p_tx_desc_first = p_tx_next_desc_curr;
+		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
+
+	} else {
+		p_tx_desc_curr->cmd_sts = command_status;
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+	}
+
+	/* Check for ring index overlap in the Tx desc ring */
+	if (p_tx_next_desc_curr == p_tx_desc_used) {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_desc_first, tx_queue);
+
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
+		return ETH_QUEUE_LAST_RESOURCE;
+	} else {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
+		return ETH_OK;
+	}
+}
+
+/*******************************************************************************
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ *	This routine returns the transmitted packet information to the caller.
+ *      It uses the 'first' index to support Tx desc return in case a transmit
+ *      of a packet spanned over multiple buffer still in process.
+ *      In case the Tx queue was in "resource error" condition, where there are
+ *      no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *      ETH_RETRY in case there is transmission in process.
+ *	ETH_END_OF_JOB if the routine has nothing to release.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE tx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
+	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
+	unsigned int command_status;
+
+
+	/* Get the Tx Desc ring indexes */
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+
+
+	/* Sanity check */
+	if (p_tx_desc_used == NULL)
+		return ETH_ERROR;
+
+	command_status = p_tx_desc_used->cmd_sts;
+
+	/* Still transmitting... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_RETRY;
+	}
+
+	/* Stop release. About to overlap the current available Tx descriptor */
+	if ((p_tx_desc_used == p_tx_desc_first) &&
+	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_END_OF_JOB;
+	}
+
+	/* Pass the packet information to the caller */
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->return_info = p_tx_desc_used->return_info;
+	p_tx_desc_used->return_info = 0;
+
+	/* Update the next descriptor to release. */
+	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
+
+	/* Any Tx return cancels the Tx resource error status */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+
+	return ETH_OK;
+
+}
+
+/*******************************************************************************
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ * 	This routine returns the received data to the caller. There is no
+ *	data copying during routine operation. All information is returned
+ *	using pointer to packet information struct passed from the caller.
+ *      If the routine exhausts	Rx ring resources then the resource error flag
+ *      is set.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ *	ETH_END_OF_JOB if there is no received data.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_next_curr_desc;
+	volatile ETH_RX_DESC *p_rx_used_desc;
+	unsigned int command_status;
+
+	/* Do not process Rx ring in case of Rx ring resource error */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
+		printf ("\nRx Queue is full ...\n");
+		return ETH_QUEUE_FULL;
+	}
+
+	/* Get the Rx Desc ring 'curr and 'used' indexes */
+	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
+	USED_RFD_GET (p_rx_used_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_rx_curr_desc == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
+	command_status = p_rx_curr_desc->cmd_sts;
+
+	/* Nothing to receive... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+/* 	DP(printf("Rx: command_status: %08x\n", command_status)); */
+		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
+		return ETH_END_OF_JOB;
+	}
+
+	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
+	p_pkt_info->return_info = p_rx_curr_desc->return_info;
+	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
+
+	/* Clean the return info field to indicate that the packet has been */
+	/* moved to the upper layers                                        */
+	p_rx_curr_desc->return_info = 0;
+
+	/* Update 'curr' in data structure */
+	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
+
+	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
+	if (p_rx_next_curr_desc == p_rx_used_desc)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+	CPU_PIPE_FLUSH;
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ *      next 'used' descriptor and attached the returned buffer to it.
+ *      In case the Rx ring was in "resource error" condition, where there are
+ *      no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
+ *
+ * OUTPUT:
+ *	New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE rx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
+
+	/* Get 'used' Rx descriptor */
+	USED_RFD_GET (p_used_rx_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_used_rx_desc == NULL)
+		return ETH_ERROR;
+
+	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+	p_used_rx_desc->return_info = p_pkt_info->return_info;
+	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
+	p_used_rx_desc->buf_size = MV64460_RX_BUFFER_SIZE;	/* Reset Buffer size */
+
+	/* Flush the write pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Return the descriptor to DMA ownership */
+	p_used_rx_desc->cmd_sts =
+		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+	/* Flush descriptor and CPU pipe */
+	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	/* Move the used descriptor pointer to the next descriptor */
+	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
+
+	/* Any Rx return cancels the Rx resource error status */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the RX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the tClk of the MV-643xx chip
+ *	, and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in usec
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set RX Coalescing mechanism */
+	MV_REG_WRITE (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      ((coal & 0x3fff) << 8) |
+		      (MV_REG_READ
+		       (MV64460_ETH_SDMA_CONFIG_REG (eth_port_num))
+		       & 0xffc000ff));
+	return coal;
+}
+
+#endif
+/*******************************************************************************
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the TX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the t_cLK frequency of the
+ *	MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in uSeconds
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set TX Coalescing mechanism */
+	MV_REG_WRITE (MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
+		      coal << 4);
+	return coal;
+}
+#endif
+
+/*******************************************************************************
+ * eth_b_copy - Copy bytes from source to destination
+ *
+ * DESCRIPTION:
+ *       This function supports the eight bytes limitation on Tx buffer size.
+ *       The routine will zero eight bytes starting from the destination address
+ *       followed by copying bytes from the source address to the destination.
+ *
+ * INPUT:
+ *       unsigned int src_addr    32 bit source address.
+ *       unsigned int dst_addr    32 bit destination address.
+ *       int        byte_count    Number of bytes to copy.
+ *
+ * OUTPUT:
+ *       See description.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count)
+{
+	/* Zero the dst_addr area */
+	*(unsigned int *) dst_addr = 0x0;
+
+	while (byte_count != 0) {
+		*(char *) dst_addr = *(char *) src_addr;
+		dst_addr++;
+		src_addr++;
+		byte_count--;
+	}
+}
diff --git a/board/Marvell/db64460/mv_eth.h b/board/Marvell/db64460/mv_eth.h
new file mode 100755
index 0000000..b4e498b
--- /dev/null
+++ b/board/Marvell/db64460/mv_eth.h
@@ -0,0 +1,840 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64460_ETH_H__
+#define __DB64460_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include "../common/ppc_error_no.h"
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64460_TX_QUEUE_NUM 1
+#define MV64460_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
+#else
+#define MV64460_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
+#else
+#define MV64460_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64460_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64460_TX_BUFFER_SIZE 1600
+#endif
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64460_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+/* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+};
+
+int mv64460_eth_init (struct eth_device *dev);
+int mv64460_eth_stop (struct eth_device *dev);
+int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64460_eth0_poll(); */
+
+int mv64460_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64460_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64460_ETH_ */
diff --git a/board/Marvell/db64460/mv_regs.h b/board/Marvell/db64460/mv_regs.h
new file mode 100755
index 0000000..fb50bb6
--- /dev/null
+++ b/board/Marvell/db64460/mv_regs.h
@@ -0,0 +1,1124 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64460X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/********************************************************************************
+* gt64460r.h - GT-64460 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_regsh
+#define __INCmv_regsh
+
+#define MV64460
+
+/* Supported by the Atlantis */
+#define MV64460_INCLUDE_PCI_1
+#define MV64460_INCLUDE_PCI_0_ARBITER
+#define MV64460_INCLUDE_PCI_1_ARBITER
+#define MV64460_INCLUDE_SNOOP_SUPPORT
+#define MV64460_INCLUDE_P2P
+#define MV64460_INCLUDE_ETH_PORT_2
+#define MV64460_INCLUDE_CPU_MAPPING
+#define MV64460_INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64460_CS_0_BASE_ADDR					    0x008
+#define MV64460_CS_0_SIZE					    0x010
+#define MV64460_CS_1_BASE_ADDR					    0x208
+#define MV64460_CS_1_SIZE					    0x210
+#define MV64460_CS_2_BASE_ADDR					    0x018
+#define MV64460_CS_2_SIZE					    0x020
+#define MV64460_CS_3_BASE_ADDR					    0x218
+#define MV64460_CS_3_SIZE					    0x220
+
+/* Devices BAR and size registers */
+
+#define MV64460_DEV_CS0_BASE_ADDR				    0x028
+#define MV64460_DEV_CS0_SIZE					    0x030
+#define MV64460_DEV_CS1_BASE_ADDR				    0x228
+#define MV64460_DEV_CS1_SIZE					    0x230
+#define MV64460_DEV_CS2_BASE_ADDR				    0x248
+#define MV64460_DEV_CS2_SIZE					    0x250
+#define MV64460_DEV_CS3_BASE_ADDR				    0x038
+#define MV64460_DEV_CS3_SIZE					    0x040
+#define MV64460_BOOTCS_BASE_ADDR				    0x238
+#define MV64460_BOOTCS_SIZE					    0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64460_PCI_0_IO_BASE_ADDR				    0x048
+#define MV64460_PCI_0_IO_SIZE					    0x050
+#define MV64460_PCI_0_MEMORY0_BASE_ADDR				    0x058
+#define MV64460_PCI_0_MEMORY0_SIZE				    0x060
+#define MV64460_PCI_0_MEMORY1_BASE_ADDR				    0x080
+#define MV64460_PCI_0_MEMORY1_SIZE				    0x088
+#define MV64460_PCI_0_MEMORY2_BASE_ADDR				    0x258
+#define MV64460_PCI_0_MEMORY2_SIZE				    0x260
+#define MV64460_PCI_0_MEMORY3_BASE_ADDR				    0x280
+#define MV64460_PCI_0_MEMORY3_SIZE				    0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64460_PCI_1_IO_BASE_ADDR				    0x090
+#define MV64460_PCI_1_IO_SIZE					    0x098
+#define MV64460_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
+#define MV64460_PCI_1_MEMORY0_SIZE				    0x0a8
+#define MV64460_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
+#define MV64460_PCI_1_MEMORY1_SIZE				    0x0b8
+#define MV64460_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
+#define MV64460_PCI_1_MEMORY2_SIZE				    0x2a8
+#define MV64460_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
+#define MV64460_PCI_1_MEMORY3_SIZE				    0x2b8
+
+/* SRAM base address */
+#define MV64460_INTEGRATED_SRAM_BASE_ADDR			    0x268
+
+/* internal registers space base address */
+#define MV64460_INTERNAL_SPACE_BASE_ADDR			    0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define MV64460_BASE_ADDR_ENABLE				    0x278
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+      /* PCI 0 */
+#define MV64460_PCI_0_IO_ADDR_REMAP				    0x0f0
+#define MV64460_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
+#define MV64460_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
+#define MV64460_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
+#define MV64460_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
+#define MV64460_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
+#define MV64460_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
+#define MV64460_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
+#define MV64460_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
+      /* PCI 1 */
+#define MV64460_PCI_1_IO_ADDR_REMAP				    0x108
+#define MV64460_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
+#define MV64460_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
+#define MV64460_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
+#define MV64460_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
+#define MV64460_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
+#define MV64460_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
+#define MV64460_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
+#define MV64460_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
+
+#define MV64460_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
+#define MV64460_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
+#define MV64460_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
+#define MV64460_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
+#define MV64460_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
+#define MV64460_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
+#define MV64460_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
+#define MV64460_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+
+#define MV64460_CPU_CONFIG					    0x000
+#define MV64460_CPU_MODE					    0x120
+#define MV64460_CPU_MASTER_CONTROL				    0x160
+#define MV64460_CPU_CROSS_BAR_CONTROL_LOW			    0x150
+#define MV64460_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
+#define MV64460_CPU_CROSS_BAR_TIMEOUT				    0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define MV64460_SMP_WHO_AM_I					    0x200
+#define MV64460_SMP_CPU0_DOORBELL				    0x214
+#define MV64460_SMP_CPU0_DOORBELL_CLEAR				    0x21C
+#define MV64460_SMP_CPU1_DOORBELL				    0x224
+#define MV64460_SMP_CPU1_DOORBELL_CLEAR				    0x22C
+#define MV64460_SMP_CPU0_DOORBELL_MASK				    0x234
+#define MV64460_SMP_CPU1_DOORBELL_MASK				    0x23C
+#define MV64460_SMP_SEMAPHOR0					    0x244
+#define MV64460_SMP_SEMAPHOR1					    0x24c
+#define MV64460_SMP_SEMAPHOR2					    0x254
+#define MV64460_SMP_SEMAPHOR3					    0x25c
+#define MV64460_SMP_SEMAPHOR4					    0x264
+#define MV64460_SMP_SEMAPHOR5					    0x26c
+#define MV64460_SMP_SEMAPHOR6					    0x274
+#define MV64460_SMP_SEMAPHOR7					    0x27c
+
+/****************************************/
+/*  CPU Sync Barrier Register		*/
+/****************************************/
+
+#define MV64460_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
+#define MV64460_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
+#define MV64460_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
+#define MV64460_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define MV64460_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
+#define MV64460_CPU_PROTECT_WINDOW_0_SIZE			    0x188
+#define MV64460_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
+#define MV64460_CPU_PROTECT_WINDOW_1_SIZE			    0x198
+#define MV64460_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
+#define MV64460_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
+#define MV64460_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
+#define MV64460_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
+
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define MV64460_CPU_ERROR_ADDR_LOW				    0x070
+#define MV64460_CPU_ERROR_ADDR_HIGH				    0x078
+#define MV64460_CPU_ERROR_DATA_LOW				    0x128
+#define MV64460_CPU_ERROR_DATA_HIGH				    0x130
+#define MV64460_CPU_ERROR_PARITY				    0x138
+#define MV64460_CPU_ERROR_CAUSE					    0x140
+#define MV64460_CPU_ERROR_MASK					    0x148
+
+/****************************************/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define MV64460_PUNIT_SLAVE_DEBUG_LOW				    0x360
+#define MV64460_PUNIT_SLAVE_DEBUG_HIGH				    0x368
+#define MV64460_PUNIT_MASTER_DEBUG_LOW				    0x370
+#define MV64460_PUNIT_MASTER_DEBUG_HIGH				    0x378
+#define MV64460_PUNIT_MMASK					    0x3e4
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define MV64460_SRAM_CONFIG					    0x380
+#define MV64460_SRAM_TEST_MODE					    0X3F4
+#define MV64460_SRAM_ERROR_CAUSE				    0x388
+#define MV64460_SRAM_ERROR_ADDR					    0x390
+#define MV64460_SRAM_ERROR_ADDR_HIGH				    0X3F8
+#define MV64460_SRAM_ERROR_DATA_LOW				    0x398
+#define MV64460_SRAM_ERROR_DATA_HIGH				    0x3a0
+#define MV64460_SRAM_ERROR_DATA_PARITY				    0x3a8
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+#define MV64460_SDRAM_CONFIG					    0x1400
+#define MV64460_D_UNIT_CONTROL_LOW				    0x1404
+#define MV64460_D_UNIT_CONTROL_HIGH				    0x1424
+#define MV64460_SDRAM_TIMING_CONTROL_LOW			    0x1408
+#define MV64460_SDRAM_TIMING_CONTROL_HIGH			    0x140c
+#define MV64460_SDRAM_ADDR_CONTROL				    0x1410
+#define MV64460_SDRAM_OPEN_PAGES_CONTROL			    0x1414
+#define MV64460_SDRAM_OPERATION					    0x1418
+#define MV64460_SDRAM_MODE					    0x141c
+#define MV64460_EXTENDED_DRAM_MODE				    0x1420
+#define MV64460_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
+#define MV64460_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
+#define MV64460_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
+#define MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
+#define MV64460_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define MV64460_SDRAM_ERROR_DATA_LOW				    0x1444
+#define MV64460_SDRAM_ERROR_DATA_HIGH				    0x1440
+#define MV64460_SDRAM_ERROR_ADDR				    0x1450
+#define MV64460_SDRAM_RECEIVED_ECC				    0x1448
+#define MV64460_SDRAM_CALCULATED_ECC				    0x144c
+#define MV64460_SDRAM_ECC_CONTROL				    0x1454
+#define MV64460_SDRAM_ECC_ERROR_COUNTER				    0x1458
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64460_DFCDL_CONFIG0					    0x1480
+#define MV64460_DFCDL_CONFIG1					    0x1484
+#define MV64460_DLL_WRITE					    0x1488
+#define MV64460_DLL_READ					    0x148c
+#define MV64460_SRAM_ADDR					    0x1490
+#define MV64460_SRAM_DATA0					    0x1494
+#define MV64460_SRAM_DATA1					    0x1498
+#define MV64460_SRAM_DATA2					    0x149c
+#define MV64460_DFCL_PROBE					    0x14a0
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define MV64460_DUNIT_DEBUG_LOW					    0x1460
+#define MV64460_DUNIT_DEBUG_HIGH				    0x1464
+#define MV64460_DUNIT_MMASK					    0X1b40
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define MV64460_DEVICE_BANK0_PARAMETERS				    0x45c
+#define MV64460_DEVICE_BANK1_PARAMETERS				    0x460
+#define MV64460_DEVICE_BANK2_PARAMETERS				    0x464
+#define MV64460_DEVICE_BANK3_PARAMETERS				    0x468
+#define MV64460_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
+#define MV64460_DEVICE_INTERFACE_CONTROL			    0x4c0
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
+#define MV64460_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
+
+/****************************************/
+/* Device interrupt registers		*/
+/****************************************/
+
+#define MV64460_DEVICE_INTERRUPT_CAUSE				    0x4d0
+#define MV64460_DEVICE_INTERRUPT_MASK				    0x4d4
+#define MV64460_DEVICE_ERROR_ADDR				    0x4d8
+#define MV64460_DEVICE_ERROR_DATA				    0x4dc
+#define MV64460_DEVICE_ERROR_PARITY				    0x4e0
+
+/****************************************/
+/* Device debug registers		*/
+/****************************************/
+
+#define MV64460_DEVICE_DEBUG_LOW				    0x4e4
+#define MV64460_DEVICE_DEBUG_HIGH				    0x4e8
+#define MV64460_RUNIT_MMASK					    0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64460_PCI_0_CS_0_BANK_SIZE				    0xc08
+#define MV64460_PCI_1_CS_0_BANK_SIZE				    0xc88
+#define MV64460_PCI_0_CS_1_BANK_SIZE				    0xd08
+#define MV64460_PCI_1_CS_1_BANK_SIZE				    0xd88
+#define MV64460_PCI_0_CS_2_BANK_SIZE				    0xc0c
+#define MV64460_PCI_1_CS_2_BANK_SIZE				    0xc8c
+#define MV64460_PCI_0_CS_3_BANK_SIZE				    0xd0c
+#define MV64460_PCI_1_CS_3_BANK_SIZE				    0xd8c
+#define MV64460_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
+#define MV64460_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
+#define MV64460_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
+#define MV64460_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
+#define MV64460_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
+#define MV64460_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
+#define MV64460_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
+#define MV64460_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
+#define MV64460_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
+#define MV64460_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
+#define MV64460_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
+#define MV64460_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
+#define MV64460_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
+#define MV64460_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
+#define MV64460_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
+#define MV64460_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
+#define MV64460_PCI_0_CPU_BAR_SIZE				    0xd28
+#define MV64460_PCI_1_CPU_BAR_SIZE				    0xda8
+#define MV64460_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
+#define MV64460_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
+#define MV64460_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
+#define MV64460_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
+#define MV64460_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
+#define MV64460_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
+#define MV64460_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
+#define MV64460_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
+#define MV64460_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
+#define MV64460_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
+#define MV64460_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
+#define MV64460_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
+#define MV64460_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
+#define MV64460_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
+#define MV64460_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
+#define MV64460_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
+#define MV64460_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
+#define MV64460_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
+#define MV64460_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
+#define MV64460_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
+#define MV64460_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
+#define MV64460_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
+#define MV64460_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
+#define MV64460_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
+#define MV64460_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
+#define MV64460_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
+#define MV64460_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
+#define MV64460_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
+#define MV64460_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
+#define MV64460_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
+#define MV64460_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
+#define MV64460_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
+#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
+#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
+#define MV64460_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
+#define MV64460_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
+#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
+#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
+#define MV64460_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
+#define MV64460_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
+#define MV64460_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
+#define MV64460_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
+#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
+#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
+#define MV64460_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
+#define MV64460_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
+#define MV64460_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
+#define MV64460_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
+#define MV64460_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
+#define MV64460_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
+#define MV64460_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
+#define MV64460_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
+#define MV64460_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
+#define MV64460_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
+#define MV64460_PCI_0_HEADERS_RETARGET_BASE			    0xF44
+#define MV64460_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
+#define MV64460_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
+#define MV64460_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
+
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define MV64460_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
+#define MV64460_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
+#define MV64460_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
+#define MV64460_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
+#define MV64460_PCI_0_COMMAND					    0xc00
+#define MV64460_PCI_1_COMMAND					    0xc80
+#define MV64460_PCI_0_MODE					    0xd00
+#define MV64460_PCI_1_MODE					    0xd80
+#define MV64460_PCI_0_RETRY					    0xc04
+#define MV64460_PCI_1_RETRY					    0xc84
+#define MV64460_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
+#define MV64460_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MV64460_PCI_0_MSI_TRIGGER_TIMER				    0xc38
+#define MV64460_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
+#define MV64460_PCI_0_ARBITER_CONTROL				    0x1d00
+#define MV64460_PCI_1_ARBITER_CONTROL				    0x1d80
+#define MV64460_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
+#define MV64460_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
+#define MV64460_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
+#define MV64460_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
+#define MV64460_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
+#define MV64460_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
+#define MV64460_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
+#define MV64460_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
+#define MV64460_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
+#define MV64460_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
+#define MV64460_PCI_0_P2P_CONFIG				    0x1d14
+#define MV64460_PCI_1_P2P_CONFIG				    0x1d94
+
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
+#define MV64460_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
+#define MV64460_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
+
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
+#define MV64460_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
+#define MV64460_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64460_PCI_0_CONFIG_ADDR				    0xcf8
+#define MV64460_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
+#define MV64460_PCI_1_CONFIG_ADDR				    0xc78
+#define MV64460_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
+#define MV64460_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
+#define MV64460_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define MV64460_PCI_0_SERR_MASK					    0xc28
+#define MV64460_PCI_1_SERR_MASK					    0xca8
+#define MV64460_PCI_0_ERROR_ADDR_LOW				    0x1d40
+#define MV64460_PCI_1_ERROR_ADDR_LOW				    0x1dc0
+#define MV64460_PCI_0_ERROR_ADDR_HIGH				    0x1d44
+#define MV64460_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
+#define MV64460_PCI_0_ERROR_ATTRIBUTE				    0x1d48
+#define MV64460_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
+#define MV64460_PCI_0_ERROR_COMMAND				    0x1d50
+#define MV64460_PCI_1_ERROR_COMMAND				    0x1dd0
+#define MV64460_PCI_0_ERROR_CAUSE				    0x1d58
+#define MV64460_PCI_1_ERROR_CAUSE				    0x1dd8
+#define MV64460_PCI_0_ERROR_MASK				    0x1d5c
+#define MV64460_PCI_1_ERROR_MASK				    0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define MV64460_PCI_0_MMASK					    0X1D24
+#define MV64460_PCI_1_MMASK					    0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define MV64460_PCI_DEVICE_AND_VENDOR_ID			    0x000
+#define MV64460_PCI_STATUS_AND_COMMAND				    0x004
+#define MV64460_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
+#define MV64460_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
+
+#define MV64460_PCI_SCS_0_BASE_ADDR_LOW				    0x010
+#define MV64460_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
+#define MV64460_PCI_SCS_1_BASE_ADDR_LOW				    0x018
+#define MV64460_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
+#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
+#define MV64460_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
+#define MV64460_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
+#define MV64460_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
+#define MV64460_PCI_CAPABILTY_LIST_POINTER			    0x034
+#define MV64460_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
+       /* capability list */
+#define MV64460_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define MV64460_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define MV64460_PCI_VPD_ADDR					    0x048
+#define MV64460_PCI_VPD_DATA					    0x04c
+#define MV64460_PCI_MSI_MESSAGE_CONTROL				    0x050
+#define MV64460_PCI_MSI_MESSAGE_ADDR				    0x054
+#define MV64460_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
+#define MV64460_PCI_MSI_MESSAGE_DATA				    0x05c
+#define MV64460_PCI_X_COMMAND					    0x060
+#define MV64460_PCI_X_STATUS					    0x064
+#define MV64460_PCI_COMPACT_PCI_HOT_SWAP			    0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define MV64460_PCI_SCS_2_BASE_ADDR_LOW				    0x110
+#define MV64460_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
+#define MV64460_PCI_SCS_3_BASE_ADDR_LOW				    0x118
+#define MV64460_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
+#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
+#define MV64460_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
+#define MV64460_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
+#define MV64460_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
+#define MV64460_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
+#define MV64460_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
+#define MV64460_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
+#define MV64460_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
+#define MV64460_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
+#define MV64460_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
+#define MV64460_PCI_CPU_BASE_ADDR_LOW				    0x220
+#define MV64460_PCI_CPU_BASE_ADDR_HIGH				    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define MV64460_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
+#define MV64460_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
+#define MV64460_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
+#define MV64460_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
+#define MV64460_PCI_P2P_I_O_BASE_ADDR				    0x420
+#define MV64460_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
+#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
+#define MV64460_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
+
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
+#define MV64460_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
+#define MV64460_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
+#define MV64460_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
+#define MV64460_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
+#define MV64460_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
+#define MV64460_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
+#define MV64460_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
+#define MV64460_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
+#define MV64460_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
+#define MV64460_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
+#define MV64460_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
+#define MV64460_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
+#define MV64460_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
+#define MV64460_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
+#define MV64460_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
+#define MV64460_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
+#define MV64460_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
+#define MV64460_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
+#define MV64460_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
+#define MV64460_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
+#define MV64460_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
+#define MV64460_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define MV64460_ETH_PHY_ADDR_REG				    0x2000
+#define MV64460_ETH_SMI_REG					    0x2004
+#define MV64460_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
+#define MV64460_ETH_UNIT_DEFAULTID_REG				    0x200c
+#define MV64460_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
+#define MV64460_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
+#define MV64460_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
+#define MV64460_ETH_UNIT_ERROR_ADDR_REG				    0x2094
+#define MV64460_ETH_BAR_0					    0x2200
+#define MV64460_ETH_BAR_1					    0x2208
+#define MV64460_ETH_BAR_2					    0x2210
+#define MV64460_ETH_BAR_3					    0x2218
+#define MV64460_ETH_BAR_4					    0x2220
+#define MV64460_ETH_BAR_5					    0x2228
+#define MV64460_ETH_SIZE_REG_0					    0x2204
+#define MV64460_ETH_SIZE_REG_1					    0x220c
+#define MV64460_ETH_SIZE_REG_2					    0x2214
+#define MV64460_ETH_SIZE_REG_3					    0x221c
+#define MV64460_ETH_SIZE_REG_4					    0x2224
+#define MV64460_ETH_SIZE_REG_5					    0x222c
+#define MV64460_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
+#define MV64460_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
+#define MV64460_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
+#define MV64460_ETH_BASE_ADDR_ENABLE_REG			    0x2290
+#define MV64460_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
+#define MV64460_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
+#define MV64460_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
+#define MV64460_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
+#define MV64460_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
+#define MV64460_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
+#define MV64460_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
+#define MV64460_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
+#define MV64460_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
+#define MV64460_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
+#define MV64460_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
+#define MV64460_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
+#define MV64460_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
+#define MV64460_ETH_DSCP_3(port)				   (0x242c + (port<<10))
+#define MV64460_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
+#define MV64460_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
+#define MV64460_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
+#define MV64460_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
+#define MV64460_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
+#define MV64460_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
+#define MV64460_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
+#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define MV64460_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
+#define MV64460_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define MV64460_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
+#define MV64460_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
+#define MV64460_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
+#define MV64460_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
+#define MV64460_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
+#define MV64460_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
+#define MV64460_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
+#define MV64460_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
+#define MV64460_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
+#define MV64460_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
+#define MV64460_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
+#define MV64460_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
+#define MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
+#define MV64460_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
+#define MV64460_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
+#define MV64460_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
+#define MV64460_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
+#define MV64460_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
+#define MV64460_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define MV64460_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define MV64460_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define MV64460_CUNIT_BASE_ADDR_REG0				    0xf200
+#define MV64460_CUNIT_BASE_ADDR_REG1				    0xf208
+#define MV64460_CUNIT_BASE_ADDR_REG2				    0xf210
+#define MV64460_CUNIT_BASE_ADDR_REG3				    0xf218
+#define MV64460_CUNIT_SIZE0					    0xf204
+#define MV64460_CUNIT_SIZE1					    0xf20c
+#define MV64460_CUNIT_SIZE2					    0xf214
+#define MV64460_CUNIT_SIZE3					    0xf21c
+#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
+#define MV64460_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
+#define MV64460_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
+#define MV64460_MPSC0_ACCESS_PROTECTION_REG			    0xf254
+#define MV64460_MPSC1_ACCESS_PROTECTION_REG			    0xf258
+#define MV64460_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
+
+	/*  Error Report Registers  */
+
+#define MV64460_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
+#define MV64460_CUNIT_INTERRUPT_MASK_REG			    0xf314
+#define MV64460_CUNIT_ERROR_ADDR				    0xf318
+
+	/*  Cunit Control Registers */
+
+#define MV64460_CUNIT_ARBITER_CONTROL_REG			    0xf300
+#define MV64460_CUNIT_CONFIG_REG				    0xb40c
+#define MV64460_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define MV64460_CUNIT_DEBUG_LOW					    0xf340
+#define MV64460_CUNIT_DEBUG_HIGH				    0xf344
+#define MV64460_CUNIT_MMASK					    0xf380
+
+	/*  Cunit Base Address Enable Window Bits*/
+#define MV64460_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
+#define MV64460_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
+#define MV64460_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
+#define MV64460_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MV64460_MPSC_ROUTING_REG				    0xb400
+#define MV64460_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
+#define MV64460_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MV64460_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
+#define MV64460_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
+
+#define MV64460_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
+#define MV64460_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
+#define MV64460_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
+#define MV64460_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
+
+	/*  MPSC0 Registers	 */
+
+
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define MV64460_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
+#define MV64460_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
+#define MV64460_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
+#define MV64460_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define MV64460_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define MV64460_SDMA_CAUSE_REG					    0xb800
+#define MV64460_SDMA_MASK_REG					    0xb880
+
+
+/****************************************/
+/* SDMA Address Space Targets		*/
+/****************************************/
+
+#define MV64460_SDMA_DRAM_CS_0_TARGET				    0x0e00
+#define MV64460_SDMA_DRAM_CS_1_TARGET				    0x0d00
+#define MV64460_SDMA_DRAM_CS_2_TARGET				    0x0b00
+#define MV64460_SDMA_DRAM_CS_3_TARGET				    0x0700
+
+#define MV64460_SDMA_DEV_CS_0_TARGET				    0x1e01
+#define MV64460_SDMA_DEV_CS_1_TARGET				    0x1d01
+#define MV64460_SDMA_DEV_CS_2_TARGET				    0x1b01
+#define MV64460_SDMA_DEV_CS_3_TARGET				    0x1701
+
+#define MV64460_SDMA_BOOT_CS_TARGET				    0x0f00
+
+#define MV64460_SDMA_SRAM_TARGET				    0x0003
+#define MV64460_SDMA_60X_BUS_TARGET				    0x4003
+
+#define MV64460_PCI_0_TARGET					    0x0003
+#define MV64460_PCI_1_TARGET					    0x0004
+
+
+/* Devices BAR and size registers */
+
+#define MV64460_DEV_CS0_BASE_ADDR				    0x028
+#define MV64460_DEV_CS0_SIZE					    0x030
+#define MV64460_DEV_CS1_BASE_ADDR				    0x228
+#define MV64460_DEV_CS1_SIZE					    0x230
+#define MV64460_DEV_CS2_BASE_ADDR				    0x248
+#define MV64460_DEV_CS2_SIZE					    0x250
+#define MV64460_DEV_CS3_BASE_ADDR				    0x038
+#define MV64460_DEV_CS3_SIZE					    0x040
+#define MV64460_BOOTCS_BASE_ADDR				    0x238
+#define MV64460_BOOTCS_SIZE					    0x240
+
+/* SDMA Window access protection */
+#define MV64460_SDMA_WIN_ACCESS_NOT_ALLOWED 0
+#define MV64460_SDMA_WIN_ACCESS_READ_ONLY 1
+#define MV64460_SDMA_WIN_ACCESS_FULL 2
+
+/* BRG Interrupts */
+
+#define MV64460_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
+#define MV64460_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
+#define MV64460_BRG_CAUSE_REG					    0xb834
+#define MV64460_BRG_MASK_REG					    0xb8b4
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define MV64460_DMA_CHANNEL0_CONTROL				    0x840
+#define MV64460_DMA_CHANNEL0_CONTROL_HIGH			    0x880
+#define MV64460_DMA_CHANNEL1_CONTROL				    0x844
+#define MV64460_DMA_CHANNEL1_CONTROL_HIGH			    0x884
+#define MV64460_DMA_CHANNEL2_CONTROL				    0x848
+#define MV64460_DMA_CHANNEL2_CONTROL_HIGH			    0x888
+#define MV64460_DMA_CHANNEL3_CONTROL				    0x84C
+#define MV64460_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
+
+
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define MV64460_DMA_CHANNEL0_BYTE_COUNT				    0x800
+#define MV64460_DMA_CHANNEL1_BYTE_COUNT				    0x804
+#define MV64460_DMA_CHANNEL2_BYTE_COUNT				    0x808
+#define MV64460_DMA_CHANNEL3_BYTE_COUNT				    0x80C
+#define MV64460_DMA_CHANNEL0_SOURCE_ADDR			    0x810
+#define MV64460_DMA_CHANNEL1_SOURCE_ADDR			    0x814
+#define MV64460_DMA_CHANNEL2_SOURCE_ADDR			    0x818
+#define MV64460_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
+#define MV64460_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
+#define MV64460_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
+#define MV64460_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
+#define MV64460_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
+#define MV64460_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
+#define MV64460_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
+#define MV64460_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
+#define MV64460_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
+#define MV64460_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
+#define MV64460_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
+#define MV64460_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
+#define MV64460_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define MV64460_DMA_BASE_ADDR_REG0				    0xa00
+#define MV64460_DMA_BASE_ADDR_REG1				    0xa08
+#define MV64460_DMA_BASE_ADDR_REG2				    0xa10
+#define MV64460_DMA_BASE_ADDR_REG3				    0xa18
+#define MV64460_DMA_BASE_ADDR_REG4				    0xa20
+#define MV64460_DMA_BASE_ADDR_REG5				    0xa28
+#define MV64460_DMA_BASE_ADDR_REG6				    0xa30
+#define MV64460_DMA_BASE_ADDR_REG7				    0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define MV64460_DMA_SIZE_REG0					    0xa04
+#define MV64460_DMA_SIZE_REG1					    0xa0c
+#define MV64460_DMA_SIZE_REG2					    0xa14
+#define MV64460_DMA_SIZE_REG3					    0xa1c
+#define MV64460_DMA_SIZE_REG4					    0xa24
+#define MV64460_DMA_SIZE_REG5					    0xa2c
+#define MV64460_DMA_SIZE_REG6					    0xa34
+#define MV64460_DMA_SIZE_REG7					    0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
+#define MV64460_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
+#define MV64460_DMA_BASE_ADDR_ENABLE_REG			    0xa80
+#define MV64460_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
+#define MV64460_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
+#define MV64460_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
+#define MV64460_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
+#define MV64460_DMA_ARBITER_CONTROL				    0x860
+#define MV64460_DMA_CROSS_BAR_TIMEOUT				    0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+#define MV64460_DMA_HEADERS_RETARGET_CONTROL			    0xa84
+#define MV64460_DMA_HEADERS_RETARGET_BASE			    0xa88
+
+ /*  IDMA Interrupt Register  */
+
+#define MV64460_DMA_INTERRUPT_CAUSE_REG				    0x8c0
+#define MV64460_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
+#define MV64460_DMA_ERROR_ADDR					    0x8c8
+#define MV64460_DMA_ERROR_SELECT				    0x8cc
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define MV64460_DMA_DEBUG_LOW					    0x8e0
+#define MV64460_DMA_DEBUG_HIGH					    0x8e4
+#define MV64460_DMA_SPARE					    0xA8C
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define MV64460_TIMER_COUNTER0					    0x850
+#define MV64460_TIMER_COUNTER1					    0x854
+#define MV64460_TIMER_COUNTER2					    0x858
+#define MV64460_TIMER_COUNTER3					    0x85C
+#define MV64460_TIMER_COUNTER_0_3_CONTROL			    0x864
+#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
+#define MV64460_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
+
+/****************************************/
+/*	   Watchdog registers		*/
+/****************************************/
+
+#define MV64460_WATCHDOG_CONFIG_REG				    0xb410
+#define MV64460_WATCHDOG_VALUE_REG				    0xb414
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define MV64460_I2C_SLAVE_ADDR					    0xc000
+#define MV64460_I2C_EXTENDED_SLAVE_ADDR				    0xc010
+#define MV64460_I2C_DATA					    0xc004
+#define MV64460_I2C_CONTROL					    0xc008
+#define MV64460_I2C_STATUS_BAUDE_RATE				    0xc00C
+#define MV64460_I2C_SOFT_RESET					    0xc01c
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define MV64460_GPP_IO_CONTROL					    0xf100
+#define MV64460_GPP_LEVEL_CONTROL				    0xf110
+#define MV64460_GPP_VALUE					    0xf104
+#define MV64460_GPP_INTERRUPT_CAUSE				    0xf108
+#define MV64460_GPP_INTERRUPT_MASK0				    0xf10c
+#define MV64460_GPP_INTERRUPT_MASK1				    0xf114
+#define MV64460_GPP_VALUE_SET					    0xf118
+#define MV64460_GPP_VALUE_CLEAR					    0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define MV64460_MAIN_INTERRUPT_CAUSE_LOW			    0x004
+#define MV64460_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
+#define MV64460_CPU_INTERRUPT0_MASK_LOW				    0x014
+#define MV64460_CPU_INTERRUPT0_MASK_HIGH			    0x01c
+#define MV64460_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
+#define MV64460_CPU_INTERRUPT1_MASK_LOW				    0x034
+#define MV64460_CPU_INTERRUPT1_MASK_HIGH			    0x03c
+#define MV64460_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
+#define MV64460_INTERRUPT0_MASK_0_LOW				    0x054
+#define MV64460_INTERRUPT0_MASK_0_HIGH				    0x05c
+#define MV64460_INTERRUPT0_SELECT_CAUSE				    0x064
+#define MV64460_INTERRUPT1_MASK_0_LOW				    0x074
+#define MV64460_INTERRUPT1_MASK_0_HIGH				    0x07c
+#define MV64460_INTERRUPT1_SELECT_CAUSE				    0x084
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+
+#define MV64460_MPP_CONTROL0					    0xf000
+#define MV64460_MPP_CONTROL1					    0xf004
+#define MV64460_MPP_CONTROL2					    0xf008
+#define MV64460_MPP_CONTROL3					    0xf00c
+
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+#define MV64460_SERIAL_INIT_LAST_DATA				    0xf324
+#define MV64460_SERIAL_INIT_CONTROL				    0xf328
+#define MV64460_SERIAL_INIT_STATUS				    0xf32c
+
+
+#endif /* __INCgt64460rh */
diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c
new file mode 100755
index 0000000..5637284
--- /dev/null
+++ b/board/Marvell/db64460/pci.c
@@ -0,0 +1,940 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#include <pci.h>
+
+#include "../include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before writing
+*                      to another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before reading
+*                     from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*                               the agent is placed on another Bus. For more
+*                               information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*           GT spec (or any other PCI device spec).
+*           unsigned int pciDevNum - The device number needs to be addressed.
+*           unsigned int busNum - On which bus does the Target agent connect
+*                                 to.
+*           unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*                               the agent target locate on another PCI bus.
+*                             - Make sure the GT is configured as a master
+*                               before reading from another device on the PCI.
+*                             - The function takes care of Big/Little endian
+*                               conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec). (configuration register offset.)
+*           pciDevNum: The device number needs to be addressed.
+*           busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*           - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*                         feature bits given as an input.
+*                       - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*         unsigned int features - See file: pci.h there are defintion for those
+*                                 region features.
+*         unsigned int baseAddress - The region base Address.
+*         unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*                           to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*                      disable the park on last mechanism for each agent.
+*                      disabling this option for all agents results parking
+*                      on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*                       respond to grant assertion within a window specified in
+*                       the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*                       grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*                           Detection mechanism.
+*                           NOTE: This operation may cause a dead lock on the
+*                           pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*                 For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*                                      Boundry.
+*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*                                      Boundry.
+*          unsigned int busNum - The CPI bus number to which the PCI interface
+*                                      is connected.
+*          unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*                          supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*         snoopType - There is four optional Types:
+*                        1. No Snoop.
+*                        2. Snoop to WT region.
+*                        3. Snoop to WB region.
+*                        4. Snoop & Invalidate to WB region.
+*         baseAddress - Base Address of this region.
+*         regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+					0x0);
+		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+				       &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					bar_value);
+	}
+}
+
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CFG_PCI0_IO_SPACE_PCI,
+			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	pciArbiterEnable (PCI_HOST0);
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CFG_PCI1_IO_SPACE_PCI,
+			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}
diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c
new file mode 100755
index 0000000..8cfe84c
--- /dev/null
+++ b/board/Marvell/db64460/sdram_init.c
@@ -0,0 +1,1985 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * adaption for the Marvell DB64460 Board
+ * Ingo Assmus (ingo.assmus@keymile.com)
+  ************************************************************************/
+
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../include/memory.h"
+#include "../include/pci.h"
+#include "../include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "../common/i2c.h"
+#include "64460.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+int set_dfcdlInit (void);	/* setup delay line of Mv64460 */
+int mvDmaIsChannelActive (int);
+int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
+int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
+
+/* ------------------------------------------------------------------------- */
+
+int
+memory_map_bank (unsigned int bankNo,
+		 unsigned int bankBase, unsigned int bankLength)
+{
+#ifdef MAP_PCI
+	PCI_HOST host;
+#endif
+
+
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf ("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank (bankNo, bankBase, bankLength);
+
+#ifdef MAP_PCI
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 | PCI_NO_SWAP;
+
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);
+
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
+	}
+#endif
+	return 0;
+}
+
+#define GB         (1 << 30)
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+	uchar drb_size;
+	uchar registered, ecc;
+	uchar tpar;
+	uchar tras_clocks;
+	uchar burst_len;
+	uchar banks, slot;
+} sdram_info_t;
+
+/* Typedefs for 'gtAuxilGetDIMMinfo' function */
+
+typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
+
+typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
+	SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
+} VOLTAGE_INTERFACE;
+
+typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
+		4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
+		32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
+typedef enum _max_CL_supported_SD { SD_CL_1 =
+		1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
+		SD_FAULT } MAX_CL_SUPPORTED_SD;
+
+
+/* SDRAM/DDR information struct */
+typedef struct _gtMemoryDimmInfo {
+	MEMORY_TYPE memoryType;
+	unsigned int numOfRowAddresses;
+	unsigned int numOfColAddresses;
+	unsigned int numOfModuleBanks;
+	unsigned int dataWidth;
+	VOLTAGE_INTERFACE voltageInterface;
+	unsigned int errorCheckType;	/* ECC , PARITY.. */
+	unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
+	unsigned int errorCheckDataWidth;	/* 0 - no, 1 - Yes */
+	unsigned int minClkDelay;
+	unsigned int burstLengthSupported;
+	unsigned int numOfBanksOnEachDevice;
+	unsigned int suportedCasLatencies;
+	unsigned int RefreshInterval;
+	unsigned int maxCASlatencySupported_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int maxCASlatencySupported_RoP;	/* RoP right of point (measured in ns) */
+	MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
+	MAX_CL_SUPPORTED_SD maxClSupported_SD;
+	unsigned int moduleBankDensity;
+	/* module attributes (true for yes) */
+	bool bufferedAddrAndControlInputs;
+	bool registeredAddrAndControlInputs;
+	bool onCardPLL;
+	bool bufferedDQMBinputs;
+	bool registeredDQMBinputs;
+	bool differentialClockInput;
+	bool redundantRowAddressing;
+
+	/* module general attributes */
+	bool suportedAutoPreCharge;
+	bool suportedPreChargeAll;
+	bool suportedEarlyRasPreCharge;
+	bool suportedWrite1ReadBurst;
+	bool suported5PercentLowVCC;
+	bool suported5PercentUpperVCC;
+	/* module timing parameters */
+	unsigned int minRasToCasDelay;
+	unsigned int minRowActiveRowActiveDelay;
+	unsigned int minRasPulseWidth;
+	unsigned int minRowPrechargeTime;	/* measured in ns */
+
+	int addrAndCommandHoldTime;	/* LoP left of point (measured in ns) */
+	int addrAndCommandSetupTime;	/* (measured in ns/100) */
+	int dataInputSetupTime;	/* LoP left of point (measured in ns) */
+	int dataInputHoldTime;	/* LoP left of point (measured in ns) */
+/* tAC times for highest 2nd and 3rd highest CAS Latency values */
+	unsigned int clockToDataOut_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOut_RoP;	/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus1_RoP;	/* RoP right of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int clockToDataOutMinus2_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP;	/* RoP right of point (measured in ns) */
+
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP;	/* LoP left of point (measured in ns) */
+	unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP;	/* RoP right of point (measured in ns) */
+
+	/* Parameters calculated from
+	   the extracted DIMM information */
+	unsigned int size;
+	unsigned int deviceDensity;	/* 16,64,128,256 or 512 Mbit */
+	unsigned int numberOfDevices;
+	uchar drb_size;		/* DRAM size in n*64Mbit */
+	uchar slot;		/* Slot Number this module is inserted in */
+	uchar spd_raw_data[128];	/* Content of SPD-EEPROM copied 1:1 */
+#ifdef DEBUG
+	uchar manufactura[8];	/* Content of SPD-EEPROM Byte 64-71 */
+	uchar modul_id[18];	/* Content of SPD-EEPROM Byte 73-90 */
+	uchar vendor_data[27];	/* Content of SPD-EEPROM Byte 99-125 */
+	unsigned long modul_serial_no;	/* Content of SPD-EEPROM Byte 95-98 */
+	unsigned int manufac_date;	/* Content of SPD-EEPROM Byte 93-94 */
+	unsigned int modul_revision;	/* Content of SPD-EEPROM Byte 91-92 */
+	uchar manufac_place;	/* Content of SPD-EEPROM Byte 72 */
+
+#endif
+} AUX_MEM_DIMM_INFO;
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
+static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned long spd_checksum;
+
+#ifdef ZUMA_NTL
+	/* zero all the values */
+	memset (info, 0, sizeof (*info));
+
+/*
+	if (!slot) {
+	    info->slot = 0;
+	    info->banks = 1;
+	    info->registered = 0;
+		    info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
+/*	    info->tpar = 3;
+	    info->tras_clocks = 5;
+	    info->burst_len = 4;
+*/
+#ifdef CONFIG_MV64460_ECC
+	/* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
+	dimmInfo->errorCheckType = 2;
+/*	    info->ecc = 2;*/
+#endif
+}
+
+return 0;
+
+#else
+	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+	int ret;
+	unsigned int i, j, density = 1, devicesForErrCheck = 0;
+
+#ifdef DEBUG
+	unsigned int k;
+#endif
+	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
+	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
+	uchar supp_cal, cal_val;
+	ulong memclk, tmemclk;
+	ulong tmp;
+	uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
+	uchar data[128];
+
+	memclk = gd->bus_clk;
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+	DP (puts ("before i2c read\n"));
+
+	ret = i2c_read (addr, 0, 1, data, 128);
+
+	DP (puts ("after i2c read\n"));
+
+	/* zero all the values */
+	memset (dimmInfo, 0, sizeof (*dimmInfo));
+
+	/* copy the SPD content 1:1 into the dimmInfo structure */
+	for (i = 0; i <= 127; i++) {
+		dimmInfo->spd_raw_data[i] = data[i];
+	}
+
+	if (ret) {
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+		return 0;
+	} else
+		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
+
+#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+
+	for (i = 0; i <= 127; i++) {
+		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
+			data[i]);
+	}
+
+#endif
+#ifdef DEBUG
+/* find Manufactura of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
+		dimmInfo->manufactura[i] = data[64 + i];
+	}
+	printf ("\nThis RAM-Module is produced by: 		%s\n",
+		dimmInfo->manufactura);
+
+/* find Manul-ID of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
+		dimmInfo->modul_id[i] = data[73 + i];
+	}
+	printf ("The Module-ID of this RAM-Module is: 		%s\n",
+		dimmInfo->modul_id);
+
+/* find Vendor-Data of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
+		dimmInfo->vendor_data[i] = data[99 + i];
+	}
+	printf ("Vendor Data of this RAM-Module is: 		%s\n",
+		dimmInfo->vendor_data);
+
+/* find modul_serial_no of Dimm Module */
+	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
+	printf ("Serial No. of this RAM-Module is: 		%ld (%lx)\n",
+		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
+
+/* find Manufac-Data of Dimm Module */
+	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
+	printf ("Manufactoring Date of this RAM-Module is: 	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
+
+/* find modul_revision of Dimm Module */
+	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
+	printf ("Module Revision of this RAM-Module is: 		%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
+
+/* find manufac_place of Dimm Module */
+	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
+	printf ("manufac_place of this RAM-Module is: 		%d\n",
+		dimmInfo->manufac_place);
+
+#endif
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+/* calculate SPD checksum */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	spd_checksum = 0;
+
+	for (i = 0; i <= 62; i++) {
+		spd_checksum += data[i];
+	}
+
+	if ((spd_checksum & 0xff) != data[63]) {
+		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
+		hang ();
+	}
+
+	else
+		printf ("SPD Checksum ok!\n");
+
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	for (i = 2; i <= 35; i++) {
+		switch (i) {
+		case 2:	/* Memory type (DDR / SDRAM) */
+			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
+#ifdef DEBUG
+			if (dimmInfo->memoryType == 0)
+				DP (printf
+				    ("Dram_type in slot %d is: 			SDRAM\n",
+				     dimmInfo->slot));
+			if (dimmInfo->memoryType == 1)
+				DP (printf
+				    ("Dram_type in slot %d is: 			DDRAM\n",
+				     dimmInfo->slot));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 3:	/* Number Of Row Addresses */
+			dimmInfo->numOfRowAddresses = data[i];
+			DP (printf
+			    ("Module Number of row addresses: 		%d\n",
+			     dimmInfo->numOfRowAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 4:	/* Number Of Column Addresses */
+			dimmInfo->numOfColAddresses = data[i];
+			DP (printf
+			    ("Module Number of col addresses: 		%d\n",
+			     dimmInfo->numOfColAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 5:	/* Number Of Module Banks */
+			dimmInfo->numOfModuleBanks = data[i];
+			DP (printf
+			    ("Number of Banks on Mod. : 				%d\n",
+			     dimmInfo->numOfModuleBanks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 6:	/* Data Width */
+			dimmInfo->dataWidth = data[i];
+			DP (printf
+			    ("Module Data Width: 				%d\n",
+			     dimmInfo->dataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 8:	/* Voltage Interface */
+			switch (data[i]) {
+			case 0x0:
+				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
+				DP (printf
+				    ("Module is 					TTL_5V_TOLERANT\n"));
+				break;
+			case 0x1:
+				dimmInfo->voltageInterface = LVTTL;
+				DP (printf
+				    ("Module is 					LVTTL\n"));
+				break;
+			case 0x2:
+				dimmInfo->voltageInterface = HSTL_1_5V;
+				DP (printf
+				    ("Module is 					TTL_5V_TOLERANT\n"));
+				break;
+			case 0x3:
+				dimmInfo->voltageInterface = SSTL_3_3V;
+				DP (printf
+				    ("Module is 					HSTL_1_5V\n"));
+				break;
+			case 0x4:
+				dimmInfo->voltageInterface = SSTL_2_5V;
+				DP (printf
+				    ("Module is 					SSTL_2_5V\n"));
+				break;
+			default:
+				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
+				DP (printf
+				    ("Module is 					VOLTAGE_UNKNOWN\n"));
+				break;
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 9:	/* Minimum Cycle Time At Max CasLatancy */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At Max CasLatancy: 		%d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 10:	/* Clock To Data Out */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOut_LoP = leftOfPoint;
+			dimmInfo->clockToDataOut_RoP = rightOfPoint;
+			DP (printf ("Clock To Data Out: 				%d.%2d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->clockToDataOut */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+/*#ifdef CONFIG_ECC */
+		case 11:	/* Error Check Type */
+			dimmInfo->errorCheckType = data[i];
+			DP (printf
+			    ("Error Check Type (0=NONE): 			%d\n",
+			     dimmInfo->errorCheckType));
+			break;
+/* #endif */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 12:	/* Refresh Interval */
+			dimmInfo->RefreshInterval = data[i];
+			DP (printf
+			    ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
+			     dimmInfo->RefreshInterval));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 13:	/* Sdram Width */
+			dimmInfo->sdramWidth = data[i];
+			DP (printf
+			    ("Sdram Width: 					%d\n",
+			     dimmInfo->sdramWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 14:	/* Error Check Data Width */
+			dimmInfo->errorCheckDataWidth = data[i];
+			DP (printf
+			    ("Error Check Data Width: 			%d\n",
+			     dimmInfo->errorCheckDataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 15:	/* Minimum Clock Delay */
+			dimmInfo->minClkDelay = data[i];
+			DP (printf
+			    ("Minimum Clock Delay: 				%d\n",
+			     dimmInfo->minClkDelay));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 16:	/* Burst Length Supported */
+			   /******-******-******-*******
+			   * bit3 | bit2 | bit1 | bit0 *
+			   *******-******-******-*******
+	    burst length = *  8   |  4   |   2  |   1  *
+			   *****************************
+
+	    If for example bit0 and bit2 are set, the burst
+	    length supported are 1 and 4. */
+
+			dimmInfo->burstLengthSupported = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Burst Length Supported: 			"));
+			if (dimmInfo->burstLengthSupported & 0x01)
+				DP (printf ("1, "));
+			if (dimmInfo->burstLengthSupported & 0x02)
+				DP (printf ("2, "));
+			if (dimmInfo->burstLengthSupported & 0x04)
+				DP (printf ("4, "));
+			if (dimmInfo->burstLengthSupported & 0x08)
+				DP (printf ("8, "));
+			DP (printf (" Bit \n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 17:	/* Number Of Banks On Each Device */
+			dimmInfo->numOfBanksOnEachDevice = data[i];
+			DP (printf
+			    ("Number Of Banks On Each Chip: 			%d\n",
+			     dimmInfo->numOfBanksOnEachDevice));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 18:	/* Suported Cas Latencies */
+
+			/*     DDR:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
+			 *********************************************************
+			 SDRAM:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
+			 ********************************************************/
+			dimmInfo->suportedCasLatencies = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Suported Cas Latencies: (CL) 			"));
+			if (dimmInfo->memoryType == 0) {	/* SDRAM */
+				for (k = 0; k <= 7; k++) {
+					if (dimmInfo->
+					    suportedCasLatencies & (1 << k))
+						DP (printf
+						    ("%d, 			",
+						     k + 1));
+				}
+
+			} else {	/* DDR-RAM */
+
+				if (dimmInfo->suportedCasLatencies & 1)
+					DP (printf ("1, "));
+				if (dimmInfo->suportedCasLatencies & 2)
+					DP (printf ("1.5, "));
+				if (dimmInfo->suportedCasLatencies & 4)
+					DP (printf ("2, "));
+				if (dimmInfo->suportedCasLatencies & 8)
+					DP (printf ("2.5, "));
+				if (dimmInfo->suportedCasLatencies & 16)
+					DP (printf ("3, "));
+				if (dimmInfo->suportedCasLatencies & 32)
+					DP (printf ("3.5, "));
+
+			}
+			DP (printf ("\n"));
+#endif
+			/* Calculating MAX CAS latency */
+			for (j = 7; j > 0; j--) {
+				if (((dimmInfo->
+				      suportedCasLatencies >> j) & 0x1) ==
+				    1) {
+					switch (dimmInfo->memoryType) {
+					case DDR:
+						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
+						switch (j) {
+						case 7:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 6:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 5:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			3.5 clk's\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3_5;
+							break;
+						case 4:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			3 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3;
+							break;
+						case 3:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			2.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2_5;
+							break;
+						case 2:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			2 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2;
+							break;
+						case 1:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			1.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_1_5;
+							break;
+						}
+
+						/* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
+						   lower then our SDRAM cycle count, we won't be able to support this CAL
+						   and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
+						if ((dimmInfo->
+						     minimumCycleTimeAtMaxCasLatancy_LoP
+						     <
+						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						    ||
+						    ((dimmInfo->
+						      minimumCycleTimeAtMaxCasLatancy_LoP
+						      ==
+						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     && (dimmInfo->
+							 minimumCycleTimeAtMaxCasLatancy_RoP
+							 <
+							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+						{
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								dimmInfo->
+								maxClSupported_DDR
+								>> 1;
+							DP (printf
+							    ("*** Change actual Cas Latencies cause of minimumCycleTime n"));
+						}
+						/* ronen - checkif the Dimm frequency compared to the Sysclock. */
+						if ((dimmInfo->
+						     minimumCycleTimeAtMaxCasLatancy_LoP
+						     >
+						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						    ||
+						    ((dimmInfo->
+						      minimumCycleTimeAtMaxCasLatancy_LoP
+						      ==
+						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     && (dimmInfo->
+							 minimumCycleTimeAtMaxCasLatancy_RoP
+							 >
+							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+						{
+							printf ("*********************************************************\n");
+							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
+							printf ("*********************************************************\n");
+							hang ();
+						}
+
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							=
+							1 +
+							(int) (5 * j / 10);
+						if (((5 * j) % 10) != 0)
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 5;
+						else
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation): 	%d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					case SDRAM:
+						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
+						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded                   */
+						DP (printf
+						    ("Max. Cas Latencies (SD): %d\n",
+						     dimmInfo->
+						     maxClSupported_SD));
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							= j;
+						dimmInfo->
+							maxCASlatencySupported_RoP
+							= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					}
+					break;
+				}
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 21:	/* Buffered Address And Control Inputs */
+			DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
+			dimmInfo->bufferedAddrAndControlInputs =
+				data[i] & BIT0;
+			dimmInfo->registeredAddrAndControlInputs =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
+			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
+			dimmInfo->registeredDQMBinputs =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->differentialClockInput =
+				(data[i] & BIT5) >> 5;
+			dimmInfo->redundantRowAddressing =
+				(data[i] & BIT6) >> 6;
+#ifdef DEBUG
+			if (dimmInfo->bufferedAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Buffered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Buffered Address/Control Input:		No \n"));
+
+			if (dimmInfo->registeredAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Registered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Registered Address/Control Input:		No \n"));
+
+			if (dimmInfo->onCardPLL == 1)
+				DP (printf
+				    (" - On-Card PLL (clock):				Yes \n"));
+			else
+				DP (printf
+				    (" - On-Card PLL (clock):				No \n"));
+
+			if (dimmInfo->bufferedDQMBinputs == 1)
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				Yes \n"));
+			else
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				No \n"));
+
+			if (dimmInfo->registeredDQMBinputs == 1)
+				DP (printf
+				    (" - Registered DQMB Inputs:			Yes \n"));
+			else
+				DP (printf
+				    (" - Registered DQMB Inputs:			No \n"));
+
+			if (dimmInfo->differentialClockInput == 1)
+				DP (printf
+				    (" - Differential Clock Input:			Yes \n"));
+			else
+				DP (printf
+				    (" - Differential Clock Input:			No \n"));
+
+			if (dimmInfo->redundantRowAddressing == 1)
+				DP (printf
+				    (" - redundant Row Addressing:			Yes \n"));
+			else
+				DP (printf
+				    (" - redundant Row Addressing:			No \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 22:	/* Suported AutoPreCharge */
+			DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
+			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
+			dimmInfo->suportedAutoPreCharge =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->suportedPreChargeAll =
+				(data[i] & BIT2) >> 2;
+			dimmInfo->suportedWrite1ReadBurst =
+				(data[i] & BIT3) >> 3;
+			dimmInfo->suported5PercentLowVCC =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->suported5PercentUpperVCC =
+				(data[i] & BIT5) >> 5;
+#ifdef DEBUG
+			if (dimmInfo->suportedEarlyRasPreCharge == 1)
+				DP (printf
+				    (" - Early Ras Precharge:			Yes \n"));
+			else
+				DP (printf
+				    (" -  Early Ras Precharge:			No \n"));
+
+			if (dimmInfo->suportedAutoPreCharge == 1)
+				DP (printf
+				    (" - AutoPreCharge:				Yes \n"));
+			else
+				DP (printf
+				    (" -  AutoPreCharge:				No \n"));
+
+			if (dimmInfo->suportedPreChargeAll == 1)
+				DP (printf
+				    (" - Precharge All:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Precharge All:				No \n"));
+
+			if (dimmInfo->suportedWrite1ReadBurst == 1)
+				DP (printf
+				    (" - Write 1/ReadBurst:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Write 1/ReadBurst:				No \n"));
+
+			if (dimmInfo->suported5PercentLowVCC == 1)
+				DP (printf
+				    (" - lower VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    ("  - lower VCC tolerance:			10 Percent \n"));
+
+			if (dimmInfo->suported5PercentUpperVCC == 1)
+				DP (printf
+				    (" - upper VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    (" -  upper VCC tolerance:			10 Percent \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
+				rightOfPoint;
+			DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (2nd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
+				rightOfPoint;
+			DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint));	/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (3rd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 27:	/* Minimum Row Precharge Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
+			trp_clocks =
+				(dimmInfo->minRowPrechargeTime +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
+			     tmemclk, tmemclk / 100, tmemclk % 100));
+			DP (printf
+			    ("Minimum Row Precharge Time [ns]: 		%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 28:	/* Minimum Row Active to Row Active Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trrd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Row Active -To- Row Active Delay [ns]: 	%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 29:	/* Minimum Ras-To-Cas Delay */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trcd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras-To-Cas Delay [ns]: 			%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 30:	/* Minimum Ras Pulse Width */
+			dimmInfo->minRasPulseWidth = data[i];
+			tras_clocks =
+				(NSto10PS (data[i]) +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras Pulse Width [ns]: 			%d = in Clk cycles %d\n",
+			     dimmInfo->minRasPulseWidth, tras_clocks));
+
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 31:	/* Module Bank Density */
+			dimmInfo->moduleBankDensity = data[i];
+			DP (printf
+			    ("Module Bank Density: 				%d\n",
+			     dimmInfo->moduleBankDensity));
+#ifdef DEBUG
+			DP (printf
+			    ("*** Offered Densities (more than 1 = Multisize-Module): "));
+			{
+				if (dimmInfo->moduleBankDensity & 1)
+					DP (printf ("4MB, "));
+				if (dimmInfo->moduleBankDensity & 2)
+					DP (printf ("8MB, "));
+				if (dimmInfo->moduleBankDensity & 4)
+					DP (printf ("16MB, "));
+				if (dimmInfo->moduleBankDensity & 8)
+					DP (printf ("32MB, "));
+				if (dimmInfo->moduleBankDensity & 16)
+					DP (printf ("64MB, "));
+				if (dimmInfo->moduleBankDensity & 32)
+					DP (printf ("128MB, "));
+				if ((dimmInfo->moduleBankDensity & 64)
+				    || (dimmInfo->moduleBankDensity & 128)) {
+					DP (printf ("ERROR, "));
+					hang ();
+				}
+			}
+			DP (printf ("\n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Setup Time [ns]: 		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 33:	/* Address And Command Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Hold Time [ns]: 		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 34:	/* Data Input Setup Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Setup Time [ns]: 			%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 35:	/* Data Input Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Hold Time [ns]: 			%d.%d\n\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+		}
+	}
+	/* calculating the sdram density */
+	for (i = 0;
+	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
+	     i++) {
+		density = density * 2;
+	}
+	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
+		dimmInfo->sdramWidth;
+	dimmInfo->numberOfDevices =
+		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
+		dimmInfo->numOfModuleBanks;
+	devicesForErrCheck =
+		(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
+	if ((dimmInfo->errorCheckType == 0x1)
+	    || (dimmInfo->errorCheckType == 0x2)
+	    || (dimmInfo->errorCheckType == 0x3)) {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			(dimmInfo->numberOfDevices -
+			 /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
+			 dimmInfo->numberOfDevices / 8);
+	} else {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			dimmInfo->numberOfDevices;
+	}
+
+	/* compute the module DRB size */
+	tmp = (1 <<
+	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
+	tmp *= dimmInfo->numOfModuleBanks;
+	tmp *= dimmInfo->sdramWidth;
+	tmp = tmp >> 24;	/* div by 0x4000000 (64M)       */
+	dimmInfo->drb_size = (uchar) tmp;
+	DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
+
+	/* try a CAS latency of 3 first... */
+
+	/* bit 1 is CL2, bit 2 is CL3 */
+	supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
+
+	cal_val = 0;
+	if (supp_cal & 3) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 3;
+	}
+
+	/* then 2... */
+	if (supp_cal & 2) {
+		if (NS10to10PS (data[23]) <= tmemclk)
+			cal_val = 2;
+	}
+
+	DP (printf ("cal_val = %d\n", cal_val));
+
+	/* bummer, did't work... */
+	if (cal_val == 0) {
+		DP (printf ("Couldn't find a good CAS latency\n"));
+		hang ();
+		return 0;
+	}
+
+	return true;
+#endif
+}
+
+/* sets up the GT properly with information passed in */
+int setup_sdram (AUX_MEM_DIMM_INFO * info)
+{
+	ulong tmp, check;
+	ulong tmp_sdram_mode = 0;	/* 0x141c */
+	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
+	int i;
+
+	/* added 8/21/2003 P. Marchese */
+	unsigned int sdram_config_reg;
+
+	/* added 10/10/2003 P. Marchese */
+	ulong sdram_chip_size;
+
+	/* sanity checking */
+	if (!info->numOfModuleBanks) {
+		printf ("setup_sdram called with 0 banks\n");
+		return 1;
+	}
+
+	/* delay line */
+	set_dfcdlInit ();	/* may be its not needed */
+	DP (printf ("Delay line set done\n"));
+
+	/* set SDRAM mode NOP */ /* To_do check it */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
+	}
+
+	/* SDRAM configuration */
+/* added 8/21/2003 P. Marchese */
+/* code allows usage of registered DIMMS */
+
+	/* figure out the memory refresh internal */
+	switch (info->RefreshInterval) {
+	case 0x0:
+	case 0x80:		/* refresh period is 15.625 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
+					/ (float) 1000000.0);
+		break;
+	case 0x1:
+	case 0x81:		/* refresh period is 3.9 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	case 0x2:
+	case 0x82:		/* refresh period is 7.8 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	case 0x3:
+	case 0x83:		/* refresh period is 31.3 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	case 0x4:
+	case 0x84:		/* refresh period is 62.5 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	case 0x5:
+	case 0x85:		/* refresh period is 125 usec */
+		sdram_config_reg =
+			(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
+					(float) 1000000.0);
+		break;
+	default:		/* refresh period undefined */
+		printf ("DRAM refresh period is unknown!\n");
+		printf ("Aborting DRAM setup with an error\n");
+		hang ();
+		break;
+	}
+	DP (printf ("calculated refresh interval %0x\n", sdram_config_reg));
+
+	/* make sure the refresh value is only 14 bits */
+	if (sdram_config_reg > 0x1fff)
+		sdram_config_reg = 0x1fff;
+	DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg));
+
+	/* we want physical bank interleaving and */
+	/* virtual bank interleaving enabled so do nothing */
+	/* since these bits need to be zero to enable the interleaving */
+
+	/*  registered DRAM ? */
+	if (info->registeredAddrAndControlInputs == 1) {
+		/* it's registered DRAM, so set the reg. DRAM bit */
+		sdram_config_reg = sdram_config_reg | BIT17;
+		DP (printf ("Enabling registered DRAM bit\n"));
+	}
+	/* turn on DRAM ECC? */
+#ifdef CONFIG_MV64460_ECC
+	if (info->errorCheckType == 0x2) {
+		/* DRAM has ECC, so turn it on */
+		sdram_config_reg = sdram_config_reg | BIT18;
+		DP (printf ("Enabling ECC\n"));
+	}
+#endif
+	/* set the data DQS pin configuration */
+	switch (info->sdramWidth) {
+	case 0x4:		/* memory is x4 */
+		sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
+		DP (printf ("Data DQS pins set for 16 pins\n"));
+		break;
+	case 0x8:		/* memory is x8 or x16 */
+	case 0x10:
+		sdram_config_reg = sdram_config_reg | BIT21;
+		DP (printf ("Data DQS pins set for 8 pins\n"));
+		break;
+	case 0x20:		/* memory is x32 */
+		/* both bits are cleared for x32 so nothing to do */
+		DP (printf ("Data DQS pins set for 2 pins\n"));
+		break;
+	default:		/* memory width unsupported */
+		printf ("DRAM chip width is unknown!\n");
+		printf ("Aborting DRAM setup with an error\n");
+		hang ();
+		break;
+	}
+
+	/*ronen db64460 */
+	/* perform read buffer assignments */
+	/* we are going to use the Power-up defaults */
+	/* bit 27 = PCI bus #0 = buffer 0 */
+	/* bit 28 = PCI bus #1 = buffer 0 */
+	/* bit 29 = MPSC = buffer 0 */
+	/* bit 30 = IDMA = buffer 0 */
+	/* bit 31 = Gigabit = buffer 0 */
+	sdram_config_reg = sdram_config_reg | 0x58000000;
+	sdram_config_reg = sdram_config_reg & 0xffffff00;
+	/* bit 14 FBSplit = FCRAM controller bsplit enable. */
+	/* bit 15 vw = FCRAM Variable write length enable.   */
+	/* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */
+	sdram_config_reg = sdram_config_reg | BIT14 | BIT15;
+
+	/* write the value into the SDRAM configuration register */
+	GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
+	DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM open pages control keep open as much as I can */
+	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
+	DP (printf
+	    ("sdram_open_pages_controll 0x1414: %08x\n",
+	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp == 0)
+		DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
+	else
+		DP (printf
+		    ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
+
+	/* SDRAM set CAS Latency according to SPD information */
+	switch (info->memoryType) {
+	case SDRAM:
+		printf ("### SD-RAM not supported !!!\n");
+		printf ("Aborting!!!\n");
+		hang ();
+		/* ToDo fill SD-RAM if needed !!!!! */
+		break;
+		/* Calculate the settings for SDRAM mode and Dunit control low registers */
+		/* Values set according to technical bulletin TB-92 rev. c */
+	case DDR:
+		DP (printf ("### SET-CL for DDR-RAM\n"));
+		/* ronen db64460 - change the tmp_dunit_control_low setting!!! */
+		switch (info->maxClSupported_DDR) {
+		case DDR_CL_3:
+			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
+			if (tmp == 1) {	/* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x05110051;
+				else
+					tmp_dunit_control_low = 0x24110051;
+				DP (printf
+				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
+			} else {	/* clk sync. bypassed   */
+
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0xC5000540;
+				else
+					tmp_dunit_control_low = 0xC4000540;
+				DP (printf
+				    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_2_5:
+			tmp_sdram_mode = 0x62;	/* CL=2.5 Burstlength = 4 */
+			if (tmp == 1) {	/* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x25110051;
+				else
+					tmp_dunit_control_low = 0x24110051;
+				DP (printf
+				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
+			} else {	/* clk sync. bypassed   */
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0xC5000540;
+					/* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
+					/* printf("Aborting!!!\n");1 */
+					/* hang();1 */
+				} else
+					tmp_dunit_control_low = 0xC4000540;
+				DP (printf
+				    ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_2:
+			tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+			if (tmp == 1) {	/* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x04110051;
+				else
+					tmp_dunit_control_low = 0x03110051;
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
+			} else {	/* clk sync. bypassed   */
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					/*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
+					/*printf("Aborting!!!\n");1 */
+					/*hang();1 */
+					tmp_dunit_control_low = 0xC4000540;
+				} else
+					tmp_dunit_control_low = 0xC3000540;;
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+		case DDR_CL_1_5:
+			tmp_sdram_mode = 0x52;	/* CL=1.5 Burstlength = 4 */
+			if (tmp == 1) {	/* clocks sync */
+				if (info->registeredAddrAndControlInputs == 1)	/* registerd DDR SDRAM? */
+					tmp_dunit_control_low = 0x24110051;
+				else
+					tmp_dunit_control_low = 0x23110051;
+				DP (printf
+				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+				printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
+			} else {	/* clk sync. bypassed   */
+
+				if (info->registeredAddrAndControlInputs == 1) {	/* registerd DDR SDRAM? */
+					/*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
+					/*printf("Aborting!!!\n");1 */
+					/*hang();1 */
+					tmp_dunit_control_low = 0xC4000540;
+				} else
+					tmp_dunit_control_low = 0xC3000540;
+				DP (printf
+				    ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		default:
+			printf ("Max. CL is out of range %d\n",
+				info->maxClSupported_DDR);
+			hang ();
+			break;
+		}		/* end DDR switch */
+		break;
+	}			/* end CL switch */
+
+	/* Write results of CL detection procedure */
+	/* set SDRAM mode reg. 0x141c */
+	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+	}
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
+	}
+
+/*------------------------------------------------------------------------------ */
+
+	/* bank parameters */
+	/* SDRAM address decode register 0x1410 */
+	/* program this with the default value */
+	tmp = 0x02;		/* power-up default address select decoding value */
+
+	DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
+/* figure out the DRAM chip size */
+	sdram_chip_size =
+		(1 << (info->numOfRowAddresses + info->numOfColAddresses));
+	sdram_chip_size *= info->sdramWidth;
+	sdram_chip_size *= 4;
+	DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size));
+	/* divide sdram chip size by 64 Mbits */
+	sdram_chip_size = sdram_chip_size / 0x4000000;
+	switch (sdram_chip_size) {
+	case 1:		/* 64 Mbit */
+	case 2:		/* 128 Mbit */
+		DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
+		tmp |= (0x00 << 4);
+		break;
+	case 4:		/* 256 Mbit */
+	case 8:		/* 512 Mbit */
+		DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
+		tmp |= (0x01 << 4);
+		break;
+	case 16:		/* 1 Gbit */
+	case 32:		/* 2 Gbit */
+		DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
+		tmp |= (0x02 << 4);
+		break;
+	default:
+		printf ("Error in dram size calculation\n");
+		printf ("RAM-Device_size is unsupported\n");
+		hang ();
+	}
+
+	/* SDRAM address control */
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
+	DP (printf
+	    ("setting up sdram address control (0x1410) with: %08lx \n",
+	     tmp));
+
+/* ------------------------------------------------------------------------------ */
+/* same settings for registerd & non-registerd DDR SDRAM */
+	DP (printf
+	    ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
+	     0x01501220));
+	/*ronen db64460 */
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220);
+
+
+/* ------------------------------------------------------------------------------ */
+
+	/* SDRAM configuration */
+	tmp = GTREGREAD (SDRAM_CONFIG);
+
+	if (info->registeredAddrAndControlInputs
+	    || info->registeredDQMBinputs) {
+		tmp |= (1 << 17);
+		DP (printf
+		    ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
+		     info->registeredAddrAndControlInputs,
+		     info->registeredDQMBinputs));
+	}
+
+	/* Use buffer 1 to return read data to the CPU
+	 * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+indent: Standard input:1465: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+4460 */
+	tmp |= (1 << 26);
+	DP (printf
+	    ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+	DP (printf
+	    ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM timing To_do: */
+/* ------------------------------------------------------------------------------ */
+	/* ronen db64460 */
+	DP (printf
+	    ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
+	     0xc));
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc);
+
+	DP (printf
+	    ("setting up sdram address pads control (0x14c0) with: %08x \n",
+	     0x7d5014a));
+	GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
+
+	DP (printf
+	    ("setting up sdram data pads control (0x14c4) with: %08x \n",
+	     0x7d5014a));
+	GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
+
+/* ------------------------------------------------------------------------------ */
+
+	/* set the SDRAM configuration for each bank */
+
+/*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
+	{
+		i = info->slot;
+		DP (printf
+		    ("\n*** Running a MRS cycle for bank %d ***\n", i));
+
+		/* map the bank */
+		memory_map_bank (i, 0, GB / 4);
+
+		/* set SDRAM mode */ /* To_do check it */
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+
+
+		/* switch back to normal operation mode */
+		GT_REG_WRITE (SDRAM_OPERATION, 0);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+
+		/* unmap the bank */
+		memory_map_bank (i, 0, 0);
+	}
+
+	return 0;
+
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+long int dram_size (long int *base, long int maxsize)
+{
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
+
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
+
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
+		val = *addr;	/* read *addr */
+
+		*addr = save1;
+		*b = save2;
+
+		if (val != cnt) {
+			DP (printf
+			    ("Found %08x  at Address %08x (failure)\n",
+			     (unsigned int) val, (unsigned int) addr));
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+	return maxsize;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* ppcboot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+long int initdram (int board_type)
+{
+	int s0 = 0, s1 = 0;
+	int checkbank[4] = {[0 ... 3] = 0 };
+	ulong realsize, total, check;
+	AUX_MEM_DIMM_INFO dimmInfo1;
+	AUX_MEM_DIMM_INFO dimmInfo2;
+	int nhr, bank_no;
+	ulong dest, memSpaceAttr;
+
+	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
+
+	/* check the NHR bit and skip mem init if it's already done */
+	nhr = get_hid0 () & (1 << 16);
+
+	if (nhr) {
+		printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
+	} else {
+		/* DIMM0 */
+		s0 = check_dimm (0, &dimmInfo1);
+
+		/* DIMM1 */
+		s1 = check_dimm (1, &dimmInfo2);
+
+		memory_map_bank (0, 0, 0);
+		memory_map_bank (1, 0, 0);
+		memory_map_bank (2, 0, 0);
+		memory_map_bank (3, 0, 0);
+
+		/* ronen check correct set of DIMMS */
+		if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
+			if (dimmInfo1.errorCheckType !=
+			    dimmInfo2.errorCheckType)
+				printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
+			if (dimmInfo1.maxClSupported_DDR !=
+			    dimmInfo2.maxClSupported_DDR)
+				printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
+			if (dimmInfo1.registeredAddrAndControlInputs !=
+			    dimmInfo2.registeredAddrAndControlInputs)
+				printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
+		}
+
+		if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
+			printf ("Setup for DIMM1 failed.\n");
+		}
+
+		if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
+			printf ("Setup for DIMM2 failed.\n");
+		}
+
+		/* set the NHR bit */
+		set_hid0 (get_hid0 () | (1 << 16));
+	}
+	/* next, size the SDRAM banks */
+
+	realsize = total = 0;
+	check = GB / 4;
+	if (dimmInfo1.numOfModuleBanks > 0) {
+		checkbank[0] = 1;
+	}
+	if (dimmInfo1.numOfModuleBanks > 1) {
+		checkbank[1] = 1;
+	}
+	if (dimmInfo1.numOfModuleBanks > 2)
+		printf ("Error, SPD claims DIMM1 has >2 banks\n");
+
+	printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
+
+	if (dimmInfo2.numOfModuleBanks > 0) {
+		checkbank[2] = 1;
+	}
+	if (dimmInfo2.numOfModuleBanks > 1) {
+		checkbank[3] = 1;
+	}
+	if (dimmInfo2.numOfModuleBanks > 2)
+		printf ("Error, SPD claims DIMM2 has >2 banks\n");
+
+	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
+
+	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+		/* skip over banks that are not populated */
+		if (!checkbank[bank_no])
+			continue;
+
+		/* ronen - realsize = dram_size((long int *)total, check); */
+		if (bank_no == 0 || bank_no == 1) {
+			if (checkbank[1] == 1)
+				realsize = dimmInfo1.size / 2;
+			else
+				realsize = dimmInfo1.size;
+		}
+		if (bank_no == 2 || bank_no == 3) {
+			if (checkbank[3] == 1)
+				realsize = dimmInfo2.size / 2;
+			else
+				realsize = dimmInfo2.size;
+		}
+		memory_map_bank (bank_no, total, realsize);
+
+		/* ronen - initialize the DRAM for ECC */
+#ifdef CONFIG_MV64460_ECC
+		if ((dimmInfo1.errorCheckType != 0) &&
+		    ((dimmInfo2.errorCheckType != 0)
+		     || (dimmInfo2.numOfModuleBanks == 0))) {
+			printf ("ECC Initialization of Bank %d:", bank_no);
+			memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
+			mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
+					     realsize);
+			for (dest = total; dest < total + realsize;
+			     dest += _8M) {
+				mvDmaTransfer (0, total, dest, _8M,
+					       BIT8 /*DMA_DTL_128BYTES */  |
+					       BIT3 /*DMA_HOLD_SOURCE_ADDR */
+					       |
+					       BIT11
+					       /*DMA_BLOCK_TRANSFER_MODE */ );
+				while (mvDmaIsChannelActive (0));
+			}
+			printf (" PASS\n");
+		}
+#endif
+
+		total += realsize;
+	}
+
+	/* ronen */
+	switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
+	case 0x2:
+		printf ("CAS Latency = 2");
+		break;
+	case 0x3:
+		printf ("CAS Latency = 3");
+		break;
+	case 0x5:
+		printf ("CAS Latency = 1.5");
+		break;
+	case 0x6:
+		printf ("CAS Latency = 2.5");
+		break;
+	}
+	printf (" tRP = %d tRAS = %d tRCD=%d\n",
+		((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
+		((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
+		((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
+
+/*	Setup Ethernet DMA Adress window to DRAM Area */
+	if (total > _256M)
+		printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
+	else
+		printf ("Total SDRAM memory is ");
+	/* (cause all the 4 BATS are taken) */
+	return (total);
+}
+
+
+/* ronen- add Idma functions for usage of the ecc dram init. */
+/*******************************************************************************
+* mvDmaIsChannelActive - Checks if a engine is busy.
+********************************************************************************/
+int mvDmaIsChannelActive (int engine)
+{
+	ulong data;
+
+	data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine);
+	if (data & BIT14 /*activity status */ ) {
+		return 1;
+	}
+	return 0;
+}
+
+/*******************************************************************************
+* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
+*                       map.
+*******************************************************************************/
+int mvDmaSetMemorySpace (ulong memSpace,
+			 ulong memSpaceTarget,
+			 ulong memSpaceAttr, ulong baseAddress, ulong size)
+{
+	ulong temp;
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return 0;
+	}
+	if (size >= 0x10000 /*64K */ ) {
+		size &= 0xffff0000;
+		baseAddress = (baseAddress & 0xffff0000);
+		/* Set the new attributes */
+		GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
+		GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
+			      (temp & ~(BIT0 << memSpace)));
+		return 1;
+	}
+	return 0;
+}
+
+
+/*******************************************************************************
+* mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
+*                 DMA channels.
+********************************************************************************/
+int mvDmaTransfer (int engine, ulong sourceAddr,
+		   ulong destAddr, ulong numOfBytes, ulong command)
+{
+	ulong engOffReg = 0;	/* Engine Offset Register */
+
+	if (numOfBytes > 0xffff) {
+		command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
+	}
+	command = command | ((command >> 6) & 0x7);
+	engOffReg = engine * 4;
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
+		      numOfBytes);
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
+		      sourceAddr);
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
+		      destAddr);
+	command =
+		command | BIT12 /*DMA_CHANNEL_ENABLE */  | BIT9
+		/*DMA_NON_CHAIN_MODE */ ;
+	/* Activate DMA engine By writting to mvDmaControlRegister */
+	GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
+	return 1;
+}
+
+/****************************************************************************************
+ *			       SDRAM INIT						*
+ *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb	*
+ *		 This procedure fits only the Atlantis					*
+ *											*
+ ***************************************************************************************/
+
+
+/****************************************************************************************
+ *			       DFCDL initialize MV643xx Design Considerations		*
+ *											*
+ ***************************************************************************************/
+int set_dfcdlInit (void)
+{
+	/*ronen the dfcdl init are done by the I2C */
+	return (0);
+}
diff --git a/board/Marvell/db64460/u-boot.lds b/board/Marvell/db64460/u-boot.lds
new file mode 100755
index 0000000..d89eb6c
--- /dev/null
+++ b/board/Marvell/db64460/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h
new file mode 100755
index 0000000..081d5fd
--- /dev/null
+++ b/board/Marvell/include/core.h
@@ -0,0 +1,238 @@
+/* Core.h - Basic core logic functions and definitions */
+
+/* Copyright Galileo Technology. */
+
+/*
+DESCRIPTION
+This header file contains simple read/write macros for addressing
+the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
+space). The macros take care of Big/Little endian conversions.
+*/
+
+#ifndef __INCcoreh
+#define __INCcoreh
+
+#include "mv_gen_reg.h"
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/****************************************/
+/*	    GENERAL Definitions			*/
+/****************************************/
+
+#define NO_BIT		0x00000000
+#define BIT0		0x00000001
+#define BIT1		0x00000002
+#define BIT2		0x00000004
+#define BIT3		0x00000008
+#define BIT4		0x00000010
+#define BIT5		0x00000020
+#define BIT6		0x00000040
+#define BIT7		0x00000080
+#define BIT8		0x00000100
+#define BIT9		0x00000200
+#define BIT10		0x00000400
+#define BIT11		0x00000800
+#define BIT12		0x00001000
+#define BIT13		0x00002000
+#define BIT14		0x00004000
+#define BIT15		0x00008000
+#define BIT16		0x00010000
+#define BIT17		0x00020000
+#define BIT18		0x00040000
+#define BIT19		0x00080000
+#define BIT20		0x00100000
+#define BIT21		0x00200000
+#define BIT22		0x00400000
+#define BIT23		0x00800000
+#define BIT24		0x01000000
+#define BIT25		0x02000000
+#define BIT26		0x04000000
+#define BIT27		0x08000000
+#define BIT28		0x10000000
+#define BIT29		0x20000000
+#define BIT30		0x40000000
+#define BIT31		0x80000000
+
+#define _1K		0x00000400
+#define _2K		0x00000800
+#define _4K		0x00001000
+#define _8K		0x00002000
+#define _16K		0x00004000
+#define _32K		0x00008000
+#define _64K		0x00010000
+#define _128K		0x00020000
+#define _256K		0x00040000
+#define _512K		0x00080000
+
+#define _1M		0x00100000
+#define _2M		0x00200000
+#define _3M		0x00300000
+#define _4M		0x00400000
+#define _5M		0x00500000
+#define _6M		0x00600000
+#define _7M		0x00700000
+#define _8M		0x00800000
+#define _9M		0x00900000
+#define _10M		0x00a00000
+#define _11M		0x00b00000
+#define _12M		0x00c00000
+#define _13M		0x00d00000
+#define _14M		0x00e00000
+#define _15M		0x00f00000
+#define _16M		0x01000000
+
+#define _32M		0x02000000
+#define _64M		0x04000000
+#define _128M		0x08000000
+#define _256M		0x10000000
+#define _512M		0x20000000
+
+#define _1G		0x40000000
+#define _2G		0x80000000
+
+typedef enum _bool{false,true} bool;
+
+/* Little to Big endian conversion macros */
+
+#ifdef LE /* Little Endian */
+#define SHORT_SWAP(X) (X)
+#define WORD_SWAP(X) (X)
+#define LONG_SWAP(X) ((l64)(X))
+
+#else	 /* Big Endian */
+#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
+
+#define WORD_SWAP(X) (((X)&0xff)<<24)+	    \
+		    (((X)&0xff00)<<8)+	    \
+		    (((X)&0xff0000)>>8)+    \
+		    (((X)&0xff000000)>>24)
+
+#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+		\
+			    (((X)&0xff00ULL)<<40)+		\
+			    (((X)&0xff0000ULL)<<24)+		\
+			    (((X)&0xff000000ULL)<<8)+		\
+			    (((X)&0xff00000000ULL)>>8)+		\
+			    (((X)&0xff0000000000ULL)>>24)+	\
+			    (((X)&0xff000000000000ULL)>>40)+	\
+			    (((X)&0xff00000000000000ULL)>>56))
+
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/* Those two definitions were defined to be compatible with MIPS */
+#define NONE_CACHEABLE		0x00000000
+#define CACHEABLE			0x00000000
+
+/* 750 cache line */
+#define CACHE_LINE_SIZE 32
+#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
+#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
+
+/* Read/Write to/from GT`s internal registers */
+#define GT_REG_READ(offset, pData)					    \
+*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |			    \
+		INTERNAL_REG_BASE_ADDR | (offset))) ) ;						     \
+*pData = WORD_SWAP(*pData)
+
+#define GTREGREAD(offset)						    \
+	 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |	     \
+		   INTERNAL_REG_BASE_ADDR | (offset))) ))
+
+#define GT_REG_WRITE(offset, data)					    \
+*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =		    \
+		    WORD_SWAP(data)
+
+/* Write 32/16/8 bit */
+#define WRITE_CHAR(address, data)					    \
+	*((unsigned char *)(address)) = data
+#define WRITE_SHORT(address, data)					    \
+	*((unsigned short *)(address)) = data
+#define WRITE_WORD(address, data)					    \
+	*((unsigned int *)(address)) = data
+
+#define GT_WRITE_CHAR(address, data)	 WRITE_CHAR(address, data)
+
+/* Write 32/16/8 bit NonCacheable */
+/*
+#define GT_WRITE_CHAR(address, data)					       \
+	(*((unsigned char *)NONE_CACHEABLE(address))) = data
+#define GT_WRITE_SHORT(address, data)					       \
+	(*((unsigned short *)NONE_CACHEABLE(address))) = data
+#define GT_WRITE_WORD(address, data)					       \
+	(*((unsigned int *)NONE_CACHEABLE(address))) = data
+*/
+ /*#define GT_WRITE_CHAR(address, data)	  ((*((volatile unsigned char *)NONE_CACHEABLE((address)))) = ((unsigned char)(data)))1 */
+
+ /*#define GT_WRITE_SHORT(address, data)   ((*((volatile unsigned short *)NONE_CACHEABLE((address)))) = ((unsigned short)(data)))1 */
+
+ /*#define GT_WRITE_WORD(address, data)	 ((*((volatile unsigned int *)NONE_CACHEABLE((address)))) = ((unsigned int)(data)))1 */
+
+
+/* Read 32/16/8 bits - returns data in variable. */
+#define READ_CHAR(address, pData)					    \
+	*pData = *((volatile unsigned char *)(address))
+
+#define READ_SHORT(address, pData)					    \
+	*pData = *((volatile unsigned short *)(address))
+
+#define READ_WORD(address, pData)					    \
+	*pData = *((volatile unsigned int *)(address))
+
+/* Read 32/16/8 bit - returns data direct. */
+#define READCHAR(address)						    \
+	*((volatile unsigned char *)((address) | NONE_CACHEABLE))
+
+#define READSHORT(address)						    \
+	*((volatile unsigned short *)((address) | NONE_CACHEABLE))
+
+#define READWORD(address)						    \
+	*((volatile unsigned int *)((address) | NONE_CACHEABLE))
+
+/* Those two Macros were defined to be compatible with MIPS */
+#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
+#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
+
+/*  SET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '1' in the
+   internal register the bits which given as an input example:
+   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '1' in register 0x840 while the other bits stays as is. */
+#define SET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
+	regOffset) |= (unsigned int)WORD_SWAP(bits)
+
+/*  RESET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '0' in the
+   internal register the bits which given as an input example:
+   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '0' in register 0x840 while the other bits stays as is. */
+#define RESET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
+	| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
+/* gets register offset and bits: a 32bit value. It set to logic '1' in the
+   internal register the bits which given as an input example:
+   GT_SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '1' in register 0x840 while the other bits stays as is. */
+ /*#define GT_SET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) | (regOffset)))) |= ((unsigned int)WORD_SWAP(bits)))1 */
+ /*#define GT_SET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)1 */
+#define GT_SET_REG_BITS(regOffset,bits) SET_REG_BITS(regOffset,bits)
+/* gets register offset and bits: a 32bit value. It set to logic '0' in the
+   internal register the bits which given as an input example:
+   GT_RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to
+   logic '0' in register 0x840 while the other bits stays as is. */
+ /*#define GT_RESET_REG_BITS(regOffset,bits)	((*((volatile unsigned int*)(NONE_CACHEABLE(INTERNAL_REG_BASE_ADDR) |  (regOffset)))) &= ~((unsigned int)WORD_SWAP(bits)))1 */
+#define GT_RESET_REG_BITS(regOffset,bits) RESET_REG_BITS(regOffset,bits)
+
+
+#define DEBUG_LED0_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x8000,0)
+#define DEBUG_LED1_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0xc000,0)
+#define DEBUG_LED2_ON()	       WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x10000,0)
+#define DEBUG_LED0_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x14000,0)
+#define DEBUG_LED1_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x18000,0)
+#define DEBUG_LED2_OFF()      WRITE_CHAR(memoryGetDeviceBaseAddress(DEVICE1) | 0x1c000,0)
+
+#endif /* __INCcoreh */
diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h
new file mode 100755
index 0000000..0947b6e
--- /dev/null
+++ b/board/Marvell/include/memory.h
@@ -0,0 +1,173 @@
+/* Memory.h - Memory mappings and remapping functions declarations */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCmemoryh
+#define __INCmemoryh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define DONT_MODIFY	0xffffffff
+#define PARITY_SUPPORT	0x40000000
+#define MINIMUM_MEM_BANK_SIZE		0x10000
+#define MINIMUM_DEVICE_WINDOW_SIZE	0x10000
+#define MINIMUM_PCI_WINDOW_SIZE		0x10000
+#define MINIMUM_ACCESS_WIN_SIZE		0x10000
+
+#define _8BIT		0x00000000
+#define _16BIT		0x00100000
+#define _32BIT		0x00200000
+#define _64BIT		0x00300000
+
+/* typedefs */
+
+ typedef struct deviceParam
+{						/* boundary values  */
+    unsigned int    turnOff;			/* 0x0 - 0xf	    */
+    unsigned int    acc2First;			/* 0x0 - 0x1f	    */
+    unsigned int    acc2Next;		/* 0x0 - 0x1f	    */
+    unsigned int    ale2Wr;			/* 0x0 - 0xf	    */
+    unsigned int    wrLow;			/* 0x0 - 0xf	    */
+    unsigned int    wrHigh;			/* 0x0 - 0xf	    */
+    unsigned int    badrSkew;		/* 0x0 - 0x2	   */
+    unsigned int    DPEn;			/* 0x0 - 0x1	   */
+    unsigned int    deviceWidth;	/* in Bytes  */
+} DEVICE_PARAM;
+
+
+typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
+typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
+
+/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2,	\
+				   MEM_REGION3,MEM_REGION4,MEM_REGION5,	      \
+				   MEM_REGION6,MEM_REGION7}		      \
+				   MEMORY_PROTECT_REGION;*/
+/* There are four possible windows that can be defined as protected */
+typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
+				  MEM_WINDOW3
+				 } MEMORY_PROTECT_WINDOW;
+/* When defining a protected window , this paramter indicates whether it
+   is accessible or not */
+typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN}	      \
+			    MEMORY_ACCESS;
+typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN}	      \
+			   MEMORY_ACCESS_WRITE;
+typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN}	      \
+				  MEMORY_CACHE_PROTECT;
+typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB}	      \
+			       MEMORY_SNOOP_TYPE;
+typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1,	      \
+				 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3}	      \
+				 MEMORY_SNOOP_REGION;
+
+/* There are 21 memory windows dedicated for the varios interfaces (PCI,
+   devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
+   address decoding mechanism. */
+typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
+			    CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
+			    DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
+			    DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
+			    BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
+			    PCI_0_MEM0_WINDOW = BIT10,
+			    PCI_0_MEM1_WINDOW = BIT11,
+			    PCI_0_MEM2_WINDOW = BIT12,
+			    PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
+			    PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
+			    PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
+			    INTEGRATED_SRAM_WINDOW = BIT19,
+			    INTERNAL_SPACE_WINDOW = BIT20,
+			    ALL_WINDOWS = 0X1FFFFF
+			   } MEMORY_WINDOW;
+
+typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
+				 } MEMORY_WINDOW_STATUS;
+
+
+typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
+#ifdef INCLUDE_PCI_1
+			  ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
+#endif /* INCLUDE_PCI_1 */
+			  } PCI_MEM_WINDOW;
+
+
+/* -------------------------------------------------------------------------------------------------*/
+
+/* functions */
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
+unsigned int memoryGetDeviceBaseAddress(DEVICE device);
+/* New at MV6436x */
+unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
+unsigned int memoryGetBankSize(MEMORY_BANK bank);
+unsigned int memoryGetDeviceSize(DEVICE device);
+unsigned int memoryGetDeviceWidth(DEVICE device);
+/* New at MV6436x */
+unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
+
+/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
+/* Set a new base and size for one of the memory banks (CS0 - CS3) */
+bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
+			   unsigned int bankSize);
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
+
+/* Change the Internal Register Base Address to a new given Address. */
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
+/* returns internal Register Space Base Address. */
+unsigned int memoryGetInternalRegistersSpace(void);
+
+/* Returns the integrated SRAM Base Address. */
+unsigned int memoryGetInternalSramBaseAddr(void);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Set new base address for the integrated SRAM. */
+void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Delete a protection feature to a given space. */
+void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Writes a new remap value to the remap register */
+unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
+				      unsigned int remapValueHigh,
+				      unsigned int remapValueLow);
+/* -------------------------------------------------------------------------------------------------*/
+
+/* Configurate the protection feature to a given space. */
+bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
+			      MEMORY_ACCESS gtMemoryAccess,
+			      MEMORY_ACCESS_WRITE gtMemoryWrite,
+			      MEMORY_CACHE_PROTECT cacheProtection,
+			      unsigned int baseAddress,
+			      unsigned int size);
+
+/* Configurate the protection feature to a given space. */
+/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+			    MEMORY_ACCESS memoryAccess,
+			    MEMORY_ACCESS_WRITE memoryWrite,
+			    MEMORY_CACHE_PROTECT cacheProtection,
+			    unsigned int baseAddress,
+			    unsigned int regionLength); */
+/* Configurate the snoop feature to a given space. */
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+			      MEMORY_SNOOP_TYPE snoopType,
+			      unsigned int baseAddress,
+			      unsigned int regionLength);
+
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+/* Set a new base and size for one of the PCI windows. */
+bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
+			  unsigned int pciWindowSize);
+
+/* Disable or enable one of the 21 windows dedicated for the CPU's
+   address decoding mechanism */
+void MemoryDisableWindow(MEMORY_WINDOW window);
+void MemoryEnableWindow (MEMORY_WINDOW window);
+MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
+#endif	/* __INCmemoryh */
diff --git a/board/Marvell/include/mv_gen_reg.h b/board/Marvell/include/mv_gen_reg.h
new file mode 100755
index 0000000..5e4f076
--- /dev/null
+++ b/board/Marvell/include/mv_gen_reg.h
@@ -0,0 +1,2288 @@
+/* mv_gen_reg.h - Internal registers definition file */
+/* Copyright - Galileo technology. */
+
+
+/*******************************************************************************
+*		    Copyright 2002, GALILEO TECHNOLOGY, LTD.		       *
+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.		       *
+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE	       *
+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
+*									       *
+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
+* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
+********************************************************************************
+* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_gen_regh
+#define __INCmv_gen_regh
+
+
+/* Supported by the Atlantis */
+#define INCLUDE_PCI_1
+#define INCLUDE_PCI_0_ARBITER
+#define INCLUDE_PCI_1_ARBITER
+#define INCLUDE_SNOOP_SUPPORT
+#define INCLUDE_P2P
+#define INCLUDE_ETH_PORT_2
+#define INCLUDE_CPU_MAPPING
+#define INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+
+/****************************************/
+/* Processor Address Space				*/
+/****************************************/
+/* DDR SDRAM BAR and size registers */
+
+/* Sdram's BAR'S */
+#define SCS_0_LOW_DECODE_ADDRESS			0x008
+#define SCS_0_HIGH_DECODE_ADDRESS			0x010
+#define SCS_1_LOW_DECODE_ADDRESS			0x208
+#define SCS_1_HIGH_DECODE_ADDRESS			0x210
+#define SCS_2_LOW_DECODE_ADDRESS			0x018
+#define SCS_2_HIGH_DECODE_ADDRESS			0x020
+#define SCS_3_LOW_DECODE_ADDRESS			0x218
+#define SCS_3_HIGH_DECODE_ADDRESS			0x220
+
+/* Make it fit the MV64360 and MV64460 Lowlevel driver */
+#define CS_0_BASE_ADDR			SCS_0_LOW_DECODE_ADDRESS
+#define CS_0_SIZE			SCS_0_HIGH_DECODE_ADDRESS
+#define CS_1_BASE_ADDR		SCS_1_LOW_DECODE_ADDRESS
+#define CS_1_SIZE			SCS_1_HIGH_DECODE_ADDRESS
+#define CS_2_BASE_ADDR		SCS_2_LOW_DECODE_ADDRESS
+#define CS_2_SIZE			SCS_2_HIGH_DECODE_ADDRESS
+#define CS_3_BASE_ADDR		SCS_3_LOW_DECODE_ADDRESS
+#define CS_3_SIZE			SCS_3_HIGH_DECODE_ADDRESS
+
+/* Devices BAR'S */
+#define CS_0_LOW_DECODE_ADDRESS			0x028
+#define CS_0_HIGH_DECODE_ADDRESS			0x030
+#define CS_1_LOW_DECODE_ADDRESS			0x228
+#define CS_1_HIGH_DECODE_ADDRESS			0x230
+#define CS_2_LOW_DECODE_ADDRESS			0x248
+#define CS_2_HIGH_DECODE_ADDRESS			0x250
+#define CS_3_LOW_DECODE_ADDRESS			0x038
+#define CS_3_HIGH_DECODE_ADDRESS			0x040
+#define BOOTCS_LOW_DECODE_ADDRESS			0x238
+#define BOOTCS_HIGH_DECODE_ADDRESS			0x240
+
+/* Make it fit the MV64360 and MV64460 Lowlevel driver */
+/* Devices BAR and size registers */
+
+#define DEV_CS0_BASE_ADDR	CS_0_LOW_DECODE_ADDRESS
+#define DEV_CS0_SIZE			CS_0_HIGH_DECODE_ADDRESS
+#define DEV_CS1_BASE_ADDR	CS_1_LOW_DECODE_ADDRESS
+#define DEV_CS1_SIZE		CS_1_HIGH_DECODE_ADDRESS
+#define DEV_CS2_BASE_ADDR	CS_2_LOW_DECODE_ADDRESS
+#define DEV_CS2_SIZE			CS_2_HIGH_DECODE_ADDRESS
+#define DEV_CS3_BASE_ADDR		CS_3_LOW_DECODE_ADDRESS
+#define DEV_CS3_SIZE		CS_3_HIGH_DECODE_ADDRESS
+#define BOOTCS_BASE_ADDR	BOOTCS_LOW_DECODE_ADDRESS
+#define BOOTCS_SIZE		BOOTCS_HIGH_DECODE_ADDRESS
+
+/* PCI 0 BAR and size registers	 old names of evb64260*/
+
+#define PCI_0I_O_LOW_DECODE_ADDRESS			0x048
+#define PCI_0I_O_HIGH_DECODE_ADDRESS			0x050
+#define PCI_0MEMORY0_LOW_DECODE_ADDRESS		0x058
+#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS		0x060
+#define PCI_0MEMORY1_LOW_DECODE_ADDRESS		0x080
+#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS		0x088
+#define PCI_0MEMORY2_LOW_DECODE_ADDRESS		0x258
+#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS		0x260
+#define PCI_0MEMORY3_LOW_DECODE_ADDRESS		0x280
+#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS		0x288
+
+/* Make it fit the MV64360 and MV64460 Lowlevel driver */
+#define PCI_0_IO_BASE_ADDR						0x048
+#define PCI_0_IO_SIZE							0x050
+#define PCI_0_MEMORY0_BASE_ADDR					0x058
+#define PCI_0_MEMORY0_SIZE						0x060
+#define PCI_0_MEMORY1_BASE_ADDR					0x080
+#define PCI_0_MEMORY1_SIZE						0x088
+#define PCI_0_MEMORY2_BASE_ADDR					0x258
+#define PCI_0_MEMORY2_SIZE						0x260
+#define PCI_0_MEMORY3_BASE_ADDR					0x280
+#define PCI_0_MEMORY3_SIZE						0x288
+
+/* PCI 1 BAR and size registers	 old names of evb64260*/
+#define PCI_1I_O_LOW_DECODE_ADDRESS			0x090
+#define PCI_1I_O_HIGH_DECODE_ADDRESS			0x098
+#define PCI_1MEMORY0_LOW_DECODE_ADDRESS		0x0a0
+#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS		0x0a8
+#define PCI_1MEMORY1_LOW_DECODE_ADDRESS		0x0b0
+#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS		0x0b8
+#define PCI_1MEMORY2_LOW_DECODE_ADDRESS		0x2a0
+#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS		0x2a8
+#define PCI_1MEMORY3_LOW_DECODE_ADDRESS		0x2b0
+#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS		0x2b8
+
+/* Make it fit the MV64360 and MV64460 Lowlevel driver */
+#define PCI_1_IO_BASE_ADDR						0x090
+#define PCI_1_IO_SIZE							0x098
+#define PCI_1_MEMORY0_BASE_ADDR					0x0a0
+#define PCI_1_MEMORY0_SIZE						0x0a8
+#define PCI_1_MEMORY1_BASE_ADDR					0x0b0
+#define PCI_1_MEMORY1_SIZE						0x0b8
+#define PCI_1_MEMORY2_BASE_ADDR					0x2a0
+#define PCI_1_MEMORY2_SIZE						0x2a8
+#define PCI_1_MEMORY3_BASE_ADDR					0x2b0
+#define PCI_1_MEMORY3_SIZE						0x2b8
+
+/* internal registers space base address */
+#define INTERNAL_SPACE_DECODE				0x068
+#define INTERNAL_SPACE_BASE_ADDR				INTERNAL_SPACE_DECODE
+
+/* SRAM base address */
+#define INTEGRATED_SRAM_BASE_ADDR				0x268
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define BASE_ADDR_ENABLE						0x278
+
+
+#define CPU_0_LOW_DECODE_ADDRESS				0x290
+#define CPU_0_HIGH_DECODE_ADDRESS				0x298
+#define CPU_1_LOW_DECODE_ADDRESS				0x2c0
+#define CPU_1_HIGH_DECODE_ADDRESS				0x2c8
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+/*****************************************************************************************/
+      /* PCI 0 */
+/* old fashion evb 64260 */
+#define PCI_0I_O_ADDRESS_REMAP				0x0f0
+#define PCI_0MEMORY0_ADDRESS_REMAP			0x0f8
+#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP		0x320
+#define PCI_0MEMORY1_ADDRESS_REMAP			0x100
+#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP		0x328
+#define PCI_0MEMORY2_ADDRESS_REMAP			0x2f8
+#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP		0x330
+#define PCI_0MEMORY3_ADDRESS_REMAP			0x300
+#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP		0x338
+
+#define PCI_0_IO_ADDR_REMAP						PCI_0I_O_ADDRESS_REMAP
+#define PCI_0_MEMORY0_LOW_ADDR_REMAP				PCI_0MEMORY0_ADDRESS_REMAP
+#define PCI_0_MEMORY0_HIGH_ADDR_REMAP				PCI_0MEMORY0_HIGH_ADDRESS_REMAP
+#define PCI_0_MEMORY1_LOW_ADDR_REMAP				PCI_0MEMORY1_ADDRESS_REMAP
+#define PCI_0_MEMORY1_HIGH_ADDR_REMAP				PCI_0MEMORY1_HIGH_ADDRESS_REMAP
+#define PCI_0_MEMORY2_LOW_ADDR_REMAP				PCI_0MEMORY2_ADDRESS_REMAP
+#define PCI_0_MEMORY2_HIGH_ADDR_REMAP				PCI_0MEMORY2_HIGH_ADDRESS_REMAP
+#define PCI_0_MEMORY3_LOW_ADDR_REMAP				PCI_0MEMORY3_ADDRESS_REMAP
+#define PCI_0_MEMORY3_HIGH_ADDR_REMAP				PCI_0MEMORY3_HIGH_ADDRESS_REMAP
+
+       /* PCI 1 */
+/* old fashion evb 64260 */
+#define PCI_1I_O_ADDRESS_REMAP				0x108
+#define PCI_1MEMORY0_ADDRESS_REMAP			0x110
+#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP		0x340
+#define PCI_1MEMORY1_ADDRESS_REMAP			0x118
+#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP		0x348
+#define PCI_1MEMORY2_ADDRESS_REMAP			0x310
+#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP		0x350
+#define PCI_1MEMORY3_ADDRESS_REMAP			0x318
+#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP		0x358
+
+#define PCI_1_IO_ADDR_REMAP						PCI_1I_O_ADDRESS_REMAP
+#define PCI_1_MEMORY0_LOW_ADDR_REMAP				PCI_1MEMORY0_ADDRESS_REMAP
+#define PCI_1_MEMORY0_HIGH_ADDR_REMAP				PCI_1MEMORY0_HIGH_ADDRESS_REMAP
+#define PCI_1_MEMORY1_LOW_ADDR_REMAP				PCI_1MEMORY1_ADDRESS_REMAP
+#define PCI_1_MEMORY1_HIGH_ADDR_REMAP				PCI_1MEMORY1_HIGH_ADDRESS_REMAP
+#define PCI_1_MEMORY2_LOW_ADDR_REMAP				PCI_1MEMORY2_ADDRESS_REMAP
+#define PCI_1_MEMORY2_HIGH_ADDR_REMAP				PCI_1MEMORY2_HIGH_ADDRESS_REMAP
+#define PCI_1_MEMORY3_LOW_ADDR_REMAP				PCI_1MEMORY3_ADDRESS_REMAP
+#define PCI_1_MEMORY3_HIGH_ADDR_REMAP				PCI_1MEMORY3_HIGH_ADDRESS_REMAP
+
+/* old fashion evb 64260 */
+#define CPU_PCI_0_HEADERS_RETARGET_CONTROL			0x3b0
+#define CPU_PCI_0_HEADERS_RETARGET_BASE				0x3b8
+#define CPU_PCI_1_HEADERS_RETARGET_CONTROL			0x3c0
+#define CPU_PCI_1_HEADERS_RETARGET_BASE				0x3c8
+#define CPU_GE_HEADERS_RETARGET_CONTROL				0x3d0
+#define CPU_GE_HEADERS_RETARGET_BASE				0x3d8
+
+/* MV64360 and MV64460 no changes needed*/
+/*****************************************************************************************/
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+/* CPU MASTER CONTROL REGISTER */
+#define CPU_CONFIGURATION				0x000
+#define CPU_MASTER_CONTROL				0x160
+
+#define CPU_CONFIG							0x000
+#define CPU_MODE							0x120
+#define CPU_MASTER_CONTROL						0x160
+/* new in MV64360 and MV64460 */
+#define CPU_CROSS_BAR_CONTROL_LOW				0x150
+#define CPU_CROSS_BAR_CONTROL_HIGH				0x158
+#define CPU_CROSS_BAR_TIMEOUT					0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define SMP_WHO_AM_I							0x200
+#define SMP_CPU0_DOORBELL						0x214
+#define SMP_CPU0_DOORBELL_CLEAR					0x21C
+#define SMP_CPU1_DOORBELL						0x224
+#define SMP_CPU1_DOORBELL_CLEAR					0x22C
+#define SMP_CPU0_DOORBELL_MASK					0x234
+#define SMP_CPU1_DOORBELL_MASK					0x23C
+#define SMP_SEMAPHOR0							0x244
+#define SMP_SEMAPHOR1							0x24c
+#define SMP_SEMAPHOR2							0x254
+#define SMP_SEMAPHOR3							0x25c
+#define SMP_SEMAPHOR4							0x264
+#define SMP_SEMAPHOR5							0x26c
+#define SMP_SEMAPHOR6							0x274
+#define SMP_SEMAPHOR7							0x27c
+
+
+/****************************************/
+/* CPU Sync Barrier				*/
+/****************************************/
+#define CPU_0_SYNC_BARRIER_TRIGGER				0x0c0
+#define CPU_0_SYNC_BARRIER_VIRTUAL				0x0c8
+#define CPU_1_SYNC_BARRIER_TRIGGER				0x0d0
+#define CPU_1_SYNC_BARRIER_VIRTUAL				0x0d8
+
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define CPU_LOW_PROTECT_ADDRESS_0			    0x180
+#define CPU_HIGH_PROTECT_ADDRESS_0			    0x188
+#define CPU_LOW_PROTECT_ADDRESS_1			    0x190
+#define CPU_HIGH_PROTECT_ADDRESS_1			    0x198
+#define CPU_LOW_PROTECT_ADDRESS_2			    0x1a0
+#define CPU_HIGH_PROTECT_ADDRESS_2			    0x1a8
+#define CPU_LOW_PROTECT_ADDRESS_3			    0x1b0
+#define CPU_HIGH_PROTECT_ADDRESS_3			    0x1b8
+/*#define CPU_LOW_PROTECT_ADDRESS_4			      0x1c0
+#define CPU_HIGH_PROTECT_ADDRESS_4			    0x1c8
+#define CPU_LOW_PROTECT_ADDRESS_5			    0x1d0
+#define CPU_HIGH_PROTECT_ADDRESS_5			    0x1d8
+#define CPU_LOW_PROTECT_ADDRESS_6			    0x1e0
+#define CPU_HIGH_PROTECT_ADDRESS_6			    0x1e8
+#define CPU_LOW_PROTECT_ADDRESS_7			    0x1f0
+#define CPU_HIGH_PROTECT_ADDRESS_7			    0x1f8
+*/
+
+#define CPU_PROTECT_WINDOW_0_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */
+#define CPU_PROTECT_WINDOW_0_SIZE			    CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */
+#define CPU_PROTECT_WINDOW_1_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_1 /* 0x190 */
+#define CPU_PROTECT_WINDOW_1_SIZE			    CPU_HIGH_PROTECT_ADDRESS_1 /* 0x198 */
+#define CPU_PROTECT_WINDOW_2_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_2 /*0x1a0 */
+#define CPU_PROTECT_WINDOW_2_SIZE			    CPU_HIGH_PROTECT_ADDRESS_2 /* 0x1a8 */
+#define CPU_PROTECT_WINDOW_3_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_3 /* 0x1b0 */
+#define CPU_PROTECT_WINDOW_3_SIZE			    CPU_HIGH_PROTECT_ADDRESS_3 /* 0x1b8 */
+
+
+/****************************************/
+/*	    Snoop Control			*/
+/****************************************/
+
+/*#define SNOOP_BASE_ADDRESS_0				      0x380
+#define SNOOP_TOP_ADDRESS_0				    0x388
+#define SNOOP_BASE_ADDRESS_1				    0x390
+#define SNOOP_TOP_ADDRESS_1				    0x398
+#define SNOOP_BASE_ADDRESS_2				    0x3a0
+#define SNOOP_TOP_ADDRESS_2				    0x3a8
+#define SNOOP_BASE_ADDRESS_3				    0x3b0
+#define SNOOP_TOP_ADDRESS_3				    0x3b8
+*/
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define SRAM_CONFIG						0x380
+#define SRAM_TEST_MODE						0x3F4
+#define SRAM_ERROR_CAUSE					0x388
+#define SRAM_ERROR_ADDR						0x390
+#define SRAM_ERROR_ADDR_HIGH					0x3F8
+#define SRAM_ERROR_DATA_LOW					0x398
+#define SRAM_ERROR_DATA_HIGH					0x3a0
+#define SRAM_ERROR_DATA_PARITY					0x3a8
+
+/****************************************/
+/*	    CPU Error Report			*/
+/****************************************/
+
+#define CPU_ERROR_ADDRESS_LOW		0x070
+#define CPU_ERROR_ADDRESS_HIGH		0x078
+#define CPU_ERROR_DATA_LOW					0x128
+#define CPU_ERROR_DATA_HIGH					0x130
+#define CPU_ERROR_PARITY					0x138
+#define CPU_ERROR_CAUSE						0x140
+#define CPU_ERROR_MASK						0x148
+
+#define CPU_ERROR_ADDR_LOW					CPU_ERROR_ADDRESS_LOW  /* 0x0701 */
+#define CPU_ERROR_ADDR_HIGH					CPU_ERROR_ADDRESS_HIGH	/* 0x0781 */
+
+/****************************************/
+/*	    Pslave Debug			*/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define X_0_ADDRESS						0x360
+#define X_0_COMMAND_ID						0x368
+#define X_1_ADDRESS						0x370
+#define X_1_COMMAND_ID						0x378
+ /*#define WRITE_DATA_LOW					0x3c01 */
+ /*#define WRITE_DATA_HIGH					0x3c81 */
+ /*#define WRITE_BYTE_ENABLE					0x3e01 */
+ /*#define READ_DATA_LOW					0x3d01 */
+ /*#define READ_DATA_HIGH					0x3d81 */
+ /*#define READ_ID						0x3e81 */
+
+#define PUNIT_SLAVE_DEBUG_LOW					X_0_ADDRESS  /* 0x3601 */
+#define PUNIT_SLAVE_DEBUG_HIGH					X_0_COMMAND_ID	/* 0x3681 */
+#define PUNIT_MASTER_DEBUG_LOW					X_1_ADDRESS  /* 0x3701 */
+#define PUNIT_MASTER_DEBUG_HIGH				   X_1_COMMAND_ID  /* 0x3781 */
+#define PUNIT_MMASK						0x3e4
+
+
+/****************************************/
+/* SDRAM and Device Address Space		*/
+/****************************************/
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+#define SDRAM_CONFIG						0x1400	/* MV64260 0x448 some changes*/
+#define D_UNIT_CONTROL_LOW					0x1404	/* NEW in MV64360 and MV64460 */
+#define D_UNIT_CONTROL_HIGH					0x1424	/* NEW in MV64360 and MV64460 */
+#define SDRAM_TIMING_CONTROL_LOW			0x1408	/* MV64260 0x4b4 new SDRAM TIMING REGISTER */
+#define SDRAM_TIMING_CONTROL_HIGH			0x140c	/* MV64260 0x4b4 new SDRAM TIMING REGISTER */
+#define SDRAM_ADDR_CONTROL				    0x1410	/* MV64260 0x47c some changes*/
+#define SDRAM_OPEN_PAGES_CONTROL			0x1414	/* NEW in MV64360 and MV64460 */
+#define SDRAM_OPERATION						0x1418	/* MV64260 0x474 some changes*/
+#define SDRAM_MODE						0x141c	/* NEW in MV64360 and MV64460 */
+#define EXTENDED_DRAM_MODE					0x1420	/* NEW in MV64360 and MV64460 */
+#define SDRAM_CROSS_BAR_CONTROL_LOW			0x1430	/* MV64260 0x4a8 NO changes*/
+#define SDRAM_CROSS_BAR_CONTROL_HIGH			0x1434	/* MV64260 0x4ac NO changes*/
+#define SDRAM_CROSS_BAR_TIMEOUT				0x1438	/* MV64260 0x4b0 NO changes*/
+#define SDRAM_ADDR_CTRL_PADS_CALIBRATION	0x14c0	/* what is this ??? */
+#define SDRAM_DATA_PADS_CALIBRATION			0x14c4	/* what is this ??? */
+/****************************************/
+/* SDRAM Configuration MV64260			*/
+/****************************************/
+ /*#define SDRAM_CONFIGURATION			0x4481 */
+ /*#define SDRAM_OPERATION_MODE			0x4741 */
+ /*#define SDRAM_ADDRESS_DECODE		0x47c1 */
+ /*#define SDRAM_UMA_CONTROL			0x4a4	eliminated in MV64360 and MV64460 */
+ /*#define SDRAM_CROSS_BAR_CONTROL_LOW	0x4a81 */
+ /*#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac1 */
+ /*#define SDRAM_CROSS_BAR_TIMEOUT		0x4b01 */
+ /*#define SDRAM_TIMING				0x4b41 */
+
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+#define SDRAM_ERROR_DATA_LOW				0x1444	/* MV64260 0x484 NO changes*/
+#define SDRAM_ERROR_DATA_HIGH					0x1440	/* MV64260 0x480 NO changes*/
+#define SDRAM_ERROR_ADDR					0x1450	/* MV64260 0x490 NO changes*/
+#define SDRAM_RECEIVED_ECC					0x1448	/* MV64260 0x488 NO changes*/
+#define SDRAM_CALCULATED_ECC					0x144c	/* MV64260 0x48c NO changes*/
+#define SDRAM_ECC_CONTROL					0x1454	/* MV64260 0x494 NO changes*/
+#define SDRAM_ECC_ERROR_COUNTER				0x1458	/* MV64260 0x498 NO changes*/
+#define SDRAM_MMASK					0x1B40	/* NEW Register in MV64360 and MV64460 DO NOT USE !!!*/
+/****************************************/
+/* SDRAM Error Report MV64260			*/
+/****************************************/
+ /*#define SDRAM_ERROR_DATA_LOW					0x4841 */
+ /*#define SDRAM_ERROR_DATA_HIGH				0x4801 */
+ /*#define SDRAM_AND_DEVICE_ERROR_ADDRESS		0x4901 */
+ /*#define SDRAM_RECEIVED_ECC				       0x4881 */
+ /*#define SDRAM_CALCULATED_ECC					0x48c1 */
+ /*#define SDRAM_ECC_CONTROL					0x4941 */
+ /*#define SDRAM_ECC_ERROR_COUNTER			0x4981 */
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+#define DFCDL_CONFIG0						0x1480
+#define DFCDL_CONFIG1						0x1484
+#define DLL_WRITE						0x1488
+#define DLL_READ						0x148c
+#define SRAM_ADDR						0x1490
+#define SRAM_DATA0						0x1494
+#define SRAM_DATA1						0x1498
+#define SRAM_DATA2						0x149c
+#define DFCL_PROBE						0x14a0
+
+
+/****************************************/
+/* SDRAM Parameters only in MV64260			*/
+/****************************************/
+
+ /*#define SDRAM_BANK0PARAMETERS				0x44C	eliminated in MV64360 and MV64460 */
+ /*#define SDRAM_BANK1PARAMETERS				0x450	eliminated in MV64360 and MV64460 */
+ /*#define SDRAM_BANK2PARAMETERS				0x454	eliminated in MV64360 and MV64460 */
+ /*#define SDRAM_BANK3PARAMETERS				0x458	eliminated in MV64360 and MV64460 */
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define DUNIT_DEBUG_LOW						0x1460
+#define DUNIT_DEBUG_HIGH					0x1464
+#define DUNIT_MMASK						0x1b40
+
+/****************************************/
+/* SDunit Debug (for internal use)	*/
+/****************************************/
+
+#define X0_ADDRESS					    0x500
+#define X0_COMMAND_AND_ID				    0x504
+#define X0_WRITE_DATA_LOW				    0x508
+#define X0_WRITE_DATA_HIGH				    0x50c
+#define X0_WRITE_BYTE_ENABLE				    0x518
+#define X0_READ_DATA_LOW				    0x510
+#define X0_READ_DATA_HIGH				    0x514
+#define X0_READ_ID					    0x51c
+#define X1_ADDRESS					    0x520
+#define X1_COMMAND_AND_ID				    0x524
+#define X1_WRITE_DATA_LOW				    0x528
+#define X1_WRITE_DATA_HIGH				    0x52c
+#define X1_WRITE_BYTE_ENABLE				    0x538
+#define X1_READ_DATA_LOW				    0x530
+#define X1_READ_DATA_HIGH				    0x534
+#define X1_READ_ID					    0x53c
+#define X0_SNOOP_ADDRESS				    0x540
+#define X0_SNOOP_COMMAND				    0x544
+#define X1_SNOOP_ADDRESS				    0x548
+#define X1_SNOOP_COMMAND				    0x54c
+
+/****************************************/
+/* Device Parameters					*/
+/****************************************/
+
+#define DEVICE_BANK0PARAMETERS				0x45c
+#define DEVICE_BANK1PARAMETERS				0x460
+#define DEVICE_BANK2PARAMETERS				0x464
+#define DEVICE_BANK3PARAMETERS				0x468
+#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
+#define DEVICE_CONTROL							0x4c0
+#define DEVICE_CROSS_BAR_CONTROL_LOW				0x4c8
+#define DEVICE_CROSS_BAR_CONTROL_HIGH				0x4cc
+#define DEVICE_CROSS_BAR_TIMEOUT				0x4c4
+
+/****************************************/
+/* Device Parameters					*/
+/****************************************/
+
+#define DEVICE_BANK0_PARAMETERS			DEVICE_BANK0PARAMETERS	/* 0x45c1 */
+#define DEVICE_BANK1_PARAMETERS			DEVICE_BANK1PARAMETERS	/* 0x4601 */
+#define DEVICE_BANK2_PARAMETERS			DEVICE_BANK2PARAMETERS	/* 0x4641 */
+#define DEVICE_BANK3_PARAMETERS			DEVICE_BANK3PARAMETERS	/* 0x4681 */
+/*#define DEVICE_BOOT_BANK_PARAMETERS			 0x46c1 */
+#define DEVICE_INTERFACE_CONTROL				DEVICE_CONTROL	/* 0x4c01 */
+#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		DEVICE_CROSS_BAR_CONTROL_LOW  /* 0x4c81 */
+#define DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		DEVICE_CROSS_BAR_CONTROL_HIGH  /* 0x4cc1 */
+#define DEVICE_INTERFACE_CROSS_BAR_TIMEOUT			DEVICE_CROSS_BAR_TIMEOUT  /* 0x4c41 */
+
+
+/****************************************/
+/* Device Interrupt					*/
+/****************************************/
+
+#define DEVICE_INTERRUPT_CAUSE						0x4d0
+#define DEVICE_INTERRUPT_MASK						0x4d4
+#define DEVICE_ERROR_ADDRESS						0x4d8
+ /*#define DEVICE_INTERRUPT_CAUSE				0x4d01 */
+ /*#define DEVICE_INTERRUPT_MASK				0x4d41 */
+#define DEVICE_ERROR_ADDR				DEVICE_ERROR_ADDRESS  /*0x4d81 */
+#define DEVICE_ERROR_DATA				0x4dc
+#define DEVICE_ERROR_PARITY					0x4e0
+
+/****************************************/
+/* Device debug registers			*/
+/****************************************/
+
+#define DEVICE_DEBUG_LOW					0x4e4
+#define DEVICE_DEBUG_HIGH				0x4e8
+#define RUNIT_MMASK							0x4f0
+
+/****************************************/
+/* DMA Record							*/
+/****************************************/
+
+ /*#define CHANNEL4_DMA_BYTE_COUNT			0x9001 */
+ /*#define CHANNEL5_DMA_BYTE_COUNT			0x9041 */
+ /*#define CHANNEL6_DMA_BYTE_COUNT			0x9081 */
+ /*#define CHANNEL7_DMA_BYTE_COUNT			0x90C1 */
+ /*#define CHANNEL4_DMA_SOURCE_ADDRESS		0x9101 */
+ /*#define CHANNEL5_DMA_SOURCE_ADDRESS		0x9141 */
+ /*#define CHANNEL6_DMA_SOURCE_ADDRESS		0x9181 */
+ /*#define CHANNEL7_DMA_SOURCE_ADDRESS		0x91C1 */
+ /*#define CHANNEL4_DMA_DESTINATION_ADDRESS		0x9201 */
+ /*#define CHANNEL5_DMA_DESTINATION_ADDRESS		0x9241 */
+ /*#define CHANNEL6_DMA_DESTINATION_ADDRESS		0x9281 */
+ /*#define CHANNEL7_DMA_DESTINATION_ADDRESS		0x92C1 */
+ /*#define CHANNEL4NEXT_RECORD_POINTER			0x9301 */
+ /*#define CHANNEL5NEXT_RECORD_POINTER			0x9341 */
+ /*#define CHANNEL6NEXT_RECORD_POINTER			0x9381 */
+ /*#define CHANNEL7NEXT_RECORD_POINTER			0x93C1 */
+ /*#define CHANNEL4CURRENT_DESCRIPTOR_POINTER		0x9701 */
+ /*#define CHANNEL5CURRENT_DESCRIPTOR_POINTER		0x9741 */
+ /*#define CHANNEL6CURRENT_DESCRIPTOR_POINTER		0x9781 */
+ /*#define CHANNEL7CURRENT_DESCRIPTOR_POINTER		0x97C1 */
+ /*#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8901 */
+ /*#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8941 */
+ /*#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x8981 */
+ /*#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x89c1 */
+ /*#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9901 */
+ /*#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9941 */
+ /*#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x9981 */
+ /*#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS		       0x99c1 */
+ /*#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a01 */
+ /*#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a41 */
+ /*#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8a81 */
+ /*#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x8ac1 */
+ /*#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a01 */
+ /*#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a41 */
+ /*#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9a81 */
+ /*#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	       0x9ac1 */
+ /*#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b01 */
+ /*#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b41 */
+ /*#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b81 */
+ /*#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8bc1 */
+ /*#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b01 */
+ /*#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b41 */
+ /*#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b81 */
+ /*#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9bc1 */
+
+/****************************************/
+/* DMA Channel Control					*/
+/****************************************/
+
+#define CHANNEL0CONTROL					0x840
+#define CHANNEL0CONTROL_HIGH				0x880
+#define CHANNEL1CONTROL					0x844
+#define CHANNEL1CONTROL_HIGH				0x884
+#define CHANNEL2CONTROL					0x848
+#define CHANNEL2CONTROL_HIGH				0x888
+#define CHANNEL3CONTROL					0x84C
+#define CHANNEL3CONTROL_HIGH				0x88C
+
+#define DMA_CHANNEL0_CONTROL				CHANNEL0CONTROL	 /*0x8401 */
+#define DMA_CHANNEL0_CONTROL_HIGH			CHANNEL0CONTROL_HIGH  /*0x8801 */
+#define DMA_CHANNEL1_CONTROL				CHANNEL1CONTROL	 /* 0x8441 */
+#define DMA_CHANNEL1_CONTROL_HIGH			CHANNEL1CONTROL_HIGH  /*0x8841 */
+#define DMA_CHANNEL2_CONTROL				CHANNEL2CONTROL	 /*0x8481 */
+#define DMA_CHANNEL2_CONTROL_HIGH			CHANNEL2CONTROL_HIGH  /*0x8881 */
+#define DMA_CHANNEL3_CONTROL				CHANNEL3CONTROL	 /*0x84C1 */
+#define DMA_CHANNEL3_CONTROL_HIGH			CHANNEL3CONTROL_HIGH  /*0x88C1 */
+
+ /*#define CHANNEL4CONTROL				0x9401 */
+ /*#define CHANNEL4CONTROL_HIGH				0x9801 */
+ /*#define CHANNEL5CONTROL				0x9441 */
+ /*#define CHANNEL5CONTROL_HIGH				0x9841 */
+ /*#define CHANNEL6CONTROL				0x9481 */
+ /*#define CHANNEL6CONTROL_HIGH				0x9881 */
+ /*#define CHANNEL7CONTROL				0x94C1 */
+ /*#define CHANNEL7CONTROL_HIGH				0x98C1 */
+
+
+/****************************************/
+/* DMA Arbiter							*/
+/****************************************/
+
+ /*#define ARBITER_CONTROL_0_3				0x8601 */
+#define ARBITER_CONTROL_4_7				0x960
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define DMA_CHANNEL0_BYTE_COUNT					CHANNEL0_DMA_BYTE_COUNT	 /*0x8001 */
+#define DMA_CHANNEL1_BYTE_COUNT					CHANNEL1_DMA_BYTE_COUNT	 /*0x8041 */
+#define DMA_CHANNEL2_BYTE_COUNT					CHANNEL2_DMA_BYTE_COUNT	 /*0x8081 */
+#define DMA_CHANNEL3_BYTE_COUNT					CHANNEL3_DMA_BYTE_COUNT	 /*0x80C1 */
+#define DMA_CHANNEL0_SOURCE_ADDR				CHANNEL0_DMA_SOURCE_ADDRESS  /*0x8101 */
+#define DMA_CHANNEL1_SOURCE_ADDR				CHANNEL1_DMA_SOURCE_ADDRESS  /*0x8141 */
+#define DMA_CHANNEL2_SOURCE_ADDR				CHANNEL2_DMA_SOURCE_ADDRESS  /*0x8181 */
+#define DMA_CHANNEL3_SOURCE_ADDR				CHANNEL3_DMA_SOURCE_ADDRESS  /*0x81c1 */
+#define DMA_CHANNEL0_DESTINATION_ADDR				CHANNEL0_DMA_DESTINATION_ADDRESS  /*0x8201 */
+#define DMA_CHANNEL1_DESTINATION_ADDR				CHANNEL1_DMA_DESTINATION_ADDRESS  /*0x8241 */
+#define DMA_CHANNEL2_DESTINATION_ADDR				CHANNEL2_DMA_DESTINATION_ADDRESS  /*0x8281 */
+#define DMA_CHANNEL3_DESTINATION_ADDR				CHANNEL3_DMA_DESTINATION_ADDRESS  /*0x82C1 */
+#define DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		CHANNEL0NEXT_RECORD_POINTER  /*0x8301 */
+#define DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		CHANNEL1NEXT_RECORD_POINTER  /*0x8341 */
+#define DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		CHANNEL2NEXT_RECORD_POINTER  /*0x8381 */
+#define DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		CHANNEL3NEXT_RECORD_POINTER  /*0x83C1 */
+#define DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		CHANNEL0CURRENT_DESCRIPTOR_POINTER  /*0x8701 */
+#define DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		CHANNEL1CURRENT_DESCRIPTOR_POINTER  /*0x8741 */
+#define DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		CHANNEL2CURRENT_DESCRIPTOR_POINTER  /*0x8781 */
+#define DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		CHANNEL3CURRENT_DESCRIPTOR_POINTER  /*0x87C1 */
+
+#define CHANNEL3CURRENT_DESCRIPTOR_POINTER		0x87C
+#define CHANNEL2CURRENT_DESCRIPTOR_POINTER		0x878
+#define CHANNEL1CURRENT_DESCRIPTOR_POINTER		0x874
+#define CHANNEL0CURRENT_DESCRIPTOR_POINTER		0x870
+#define CHANNEL0NEXT_RECORD_POINTER			0x830
+#define CHANNEL1NEXT_RECORD_POINTER			0x834
+#define CHANNEL2NEXT_RECORD_POINTER			0x838
+#define CHANNEL3NEXT_RECORD_POINTER			0x83C
+#define CHANNEL0_DMA_DESTINATION_ADDRESS		0x820
+#define CHANNEL1_DMA_DESTINATION_ADDRESS		0x824
+#define CHANNEL2_DMA_DESTINATION_ADDRESS		0x828
+#define CHANNEL3_DMA_DESTINATION_ADDRESS		0x82C
+#define CHANNEL0_DMA_SOURCE_ADDRESS			0x810
+#define CHANNEL1_DMA_SOURCE_ADDRESS			0x814
+#define CHANNEL2_DMA_SOURCE_ADDRESS			0x818
+#define CHANNEL3_DMA_SOURCE_ADDRESS			0x81C
+#define CHANNEL0_DMA_BYTE_COUNT			0x800
+#define CHANNEL1_DMA_BYTE_COUNT			0x804
+#define CHANNEL2_DMA_BYTE_COUNT			0x808
+#define CHANNEL3_DMA_BYTE_COUNT			0x80C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define DMA_BASE_ADDR_REG0						0xa00
+#define DMA_BASE_ADDR_REG1						0xa08
+#define DMA_BASE_ADDR_REG2						0xa10
+#define DMA_BASE_ADDR_REG3						0xa18
+#define DMA_BASE_ADDR_REG4						0xa20
+#define DMA_BASE_ADDR_REG5						0xa28
+#define DMA_BASE_ADDR_REG6						0xa30
+#define DMA_BASE_ADDR_REG7						0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define DMA_SIZE_REG0							0xa04
+#define DMA_SIZE_REG1							0xa0c
+#define DMA_SIZE_REG2							0xa14
+#define DMA_SIZE_REG3							0xa1c
+#define DMA_SIZE_REG4							0xa24
+#define DMA_SIZE_REG5							0xa2c
+#define DMA_SIZE_REG6							0xa34
+#define DMA_SIZE_REG7							0xa3C
+
+    /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define DMA_HIGH_ADDR_REMAP_REG0				0xa60
+#define DMA_HIGH_ADDR_REMAP_REG1				0xa64
+#define DMA_HIGH_ADDR_REMAP_REG2				0xa68
+#define DMA_HIGH_ADDR_REMAP_REG3				0xa6C
+#define DMA_BASE_ADDR_ENABLE_REG				0xa80
+#define DMA_CHANNEL0_ACCESS_PROTECTION_REG		0xa70
+#define DMA_CHANNEL1_ACCESS_PROTECTION_REG		   0xa74
+#define DMA_CHANNEL2_ACCESS_PROTECTION_REG		   0xa78
+#define DMA_CHANNEL3_ACCESS_PROTECTION_REG		   0xa7c
+#define DMA_ARBITER_CONTROL						0x860
+#define DMA_CROSS_BAR_TIMEOUT					0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+ /*#define CPU_IDMA_HEADERS_RETARGET_CONTROL			0x3e01 */
+ /*#define CPU_IDMA_HEADERS_RETARGET_BASE			 0x3e81 */
+
+#define DMA_HEADERS_RETARGET_CONTROL			0xa84
+#define DMA_HEADERS_RETARGET_BASE			0xa88
+
+/****************************************/
+/* DMA Interrupt						*/
+/****************************************/
+
+#define CHANELS0_3_INTERRUPT_CAUSE			0x8c0
+#define CHANELS0_3_INTERRUPT_MASK			0x8c4
+#define CHANELS0_3_ERROR_ADDRESS			0x8c8
+#define CHANELS0_3_ERROR_SELECT				0x8cc
+ /*#define CHANELS4_7_INTERRUPT_CAUSE			0x9c01 */
+ /*#define CHANELS4_7_INTERRUPT_MASK			0x9c41 */
+ /*#define CHANELS4_7_ERROR_ADDRESS			0x9c81 */
+ /*#define CHANELS4_7_ERROR_SELECT			0x9cc1 */
+
+#define DMA_INTERRUPT_CAUSE_REG				CHANELS0_3_INTERRUPT_CAUSE  /*0x8c01 */
+#define DMA_INTERRUPT_CAUSE_MASK			CHANELS0_3_INTERRUPT_MASK  /*0x8c41 */
+#define DMA_ERROR_ADDR						CHANELS0_3_ERROR_ADDRESS  /*0x8c81 */
+#define DMA_ERROR_SELECT					CHANELS0_3_ERROR_SELECT	 /*0x8cc1 */
+
+
+/****************************************/
+/* DMA Debug (for internal use)		*/
+/****************************************/
+
+#define DMA_X0_ADDRESS						0x8e0
+#define DMA_X0_COMMAND_AND_ID				0x8e4
+ /*#define DMA_X0_WRITE_DATA_LOW				0x8e81 */
+ /*#define DMA_X0_WRITE_DATA_HIGH				0x8ec1 */
+ /*#define DMA_X0_WRITE_BYTE_ENABLE				0x8f81 */
+ /*#define DMA_X0_READ_DATA_LOW					0x8f01 */
+ /*#define DMA_X0_READ_DATA_HIGH				0x8f41 */
+ /*#define DMA_X0_READ_ID					0x8fc1 */
+ /*#define DMA_X1_ADDRESS					0x9e01 */
+ /*#define DMA_X1_COMMAND_AND_ID			0x9e41 */
+ /*#define DMA_X1_WRITE_DATA_LOW				0x9e81 */
+ /*#define DMA_X1_WRITE_DATA_HIGH				0x9ec1 */
+ /*#define DMA_X1_WRITE_BYTE_ENABLE				0x9f81 */
+ /*#define DMA_X1_READ_DATA_LOW					0x9f01 */
+ /*#define DMA_X1_READ_DATA_HIGH				0x9f41 */
+ /*#define DMA_X1_READ_ID					0x9fc1 */
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define DMA_DEBUG_LOW						DMA_X0_ADDRESS	/* 0x8e01 */
+#define DMA_DEBUG_HIGH						DMA_X0_COMMAND_AND_ID  /*0x8e41 */
+#define DMA_SPARE						0xA8C
+
+
+/****************************************/
+/* Timer_Counter						*/
+/****************************************/
+
+#define TIMER_COUNTER0					0x850
+#define TIMER_COUNTER1					0x854
+#define TIMER_COUNTER2					0x858
+#define TIMER_COUNTER3					0x85C
+#define TIMER_COUNTER_0_3_CONTROL			0x864
+#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE		0x868
+#define TIMER_COUNTER_0_3_INTERRUPT_MASK		0x86c
+ /*#define TIMER_COUNTER4					0x9501 */
+ /*#define TIMER_COUNTER5					0x9541 */
+ /*#define TIMER_COUNTER6					0x9581 */
+ /*#define TIMER_COUNTER7					0x95C1 */
+ /*#define TIMER_COUNTER_4_7_CONTROL			0x9641 */
+ /*#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE		0x9681 */
+ /*#define TIMER_COUNTER_4_7_INTERRUPT_MASK			0x96c1 */
+
+/****************************************/
+/* PCI Slave Address Decoding		*/
+/****************************************/
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+#define PCI_0_CS_0_BANK_SIZE					PCI_0SCS_0_BANK_SIZE  /*0xc081 */
+#define PCI_1_CS_0_BANK_SIZE					PCI_1SCS_0_BANK_SIZE  /* 0xc881 */
+#define PCI_0_CS_1_BANK_SIZE					PCI_0SCS_1_BANK_SIZE  /*0xd081 */
+#define PCI_1_CS_1_BANK_SIZE					PCI_1SCS_1_BANK_SIZE  /* 0xd881 */
+#define PCI_0_CS_2_BANK_SIZE					PCI_0SCS_2_BANK_SIZE  /*0xc0c1 */
+#define PCI_1_CS_2_BANK_SIZE					PCI_1SCS_2_BANK_SIZE  /*0xc8c1 */
+#define PCI_0_CS_3_BANK_SIZE					PCI_0SCS_3_BANK_SIZE  /*0xd0c1 */
+#define PCI_1_CS_3_BANK_SIZE					PCI_1SCS_3_BANK_SIZE  /*0xd8c1 */
+#define PCI_0_DEVCS_0_BANK_SIZE					PCI_0CS_0_BANK_SIZE  /*0xc101 */
+#define PCI_1_DEVCS_0_BANK_SIZE				    PCI_1CS_0_BANK_SIZE	 /*0xc901 */
+#define PCI_0_DEVCS_1_BANK_SIZE				    PCI_0CS_1_BANK_SIZE	 /*0xd101 */
+#define PCI_1_DEVCS_1_BANK_SIZE				    PCI_1CS_1_BANK_SIZE	 /* 0xd901 */
+#define PCI_0_DEVCS_2_BANK_SIZE				    PCI_0CS_2_BANK_SIZE	 /* 0xd181 */
+#define PCI_1_DEVCS_2_BANK_SIZE				    PCI_1CS_2_BANK_SIZE	 /*0xd981 */
+#define PCI_0_DEVCS_3_BANK_SIZE				    PCI_0CS_3_BANK_SIZE	 /* 0xc141 */
+#define PCI_1_DEVCS_3_BANK_SIZE				    PCI_1CS_3_BANK_SIZE	 /*0xc941 */
+#define PCI_0_DEVCS_BOOT_BANK_SIZE			PCI_0CS_BOOT_BANK_SIZE	/*0xd141 */
+#define PCI_1_DEVCS_BOOT_BANK_SIZE			PCI_1CS_BOOT_BANK_SIZE	/* 0xd941 */
+#define PCI_0_P2P_MEM0_BAR_SIZE				    PCI_0P2P_MEM0_BAR_SIZE  /*0xd1c1 */
+#define PCI_1_P2P_MEM0_BAR_SIZE				    PCI_1P2P_MEM0_BAR_SIZE  /*0xd9c1 */
+#define PCI_0_P2P_MEM1_BAR_SIZE				    PCI_0P2P_MEM1_BAR_SIZE  /*0xd201 */
+#define PCI_1_P2P_MEM1_BAR_SIZE				    PCI_1P2P_MEM1_BAR_SIZE  /*0xda01 */
+#define PCI_0_P2P_I_O_BAR_SIZE					PCI_0P2P_I_O_BAR_SIZE  /*0xd241 */
+#define PCI_1_P2P_I_O_BAR_SIZE					PCI_1P2P_I_O_BAR_SIZE  /*0xda41 */
+#define PCI_0_CPU_BAR_SIZE					PCI_0CPU_BAR_SIZE  /*0xd281 */
+#define PCI_1_CPU_BAR_SIZE					PCI_1CPU_BAR_SIZE  /*0xda81 */
+#define PCI_0_INTERNAL_SRAM_BAR_SIZE			PCI_0DAC_SCS_0_BANK_SIZE  /*0xe001 */
+#define PCI_1_INTERNAL_SRAM_BAR_SIZE			PCI_1DAC_SCS_0_BANK_SIZE  /*0xe801 */
+#define PCI_0_EXPANSION_ROM_BAR_SIZE			PCI_0EXPANSION_ROM_BAR_SIZE  /*0xd2c1 */
+#define PCI_1_EXPANSION_ROM_BAR_SIZE		       PCI_1EXPANSION_ROM_BAR_SIZE  /*0xd9c1 */
+#define PCI_0_BASE_ADDR_REG_ENABLE			PCI_0BASE_ADDRESS_REGISTERS_ENABLE  /*0xc3c1 */
+#define PCI_1_BASE_ADDR_REG_ENABLE			PCI_1BASE_ADDRESS_REGISTERS_ENABLE  /*0xcbc1 */
+#define PCI_0_CS_0_BASE_ADDR_REMAP		PCI_0SCS_0_BASE_ADDRESS_REMAP  /*0xc481 */
+#define PCI_1_CS_0_BASE_ADDR_REMAP		PCI_1SCS_0_BASE_ADDRESS_REMAP  /*0xcc81 */
+#define PCI_0_CS_1_BASE_ADDR_REMAP		PCI_0SCS_1_BASE_ADDRESS_REMAP  /*0xd481 */
+#define PCI_1_CS_1_BASE_ADDR_REMAP		PCI_1SCS_1_BASE_ADDRESS_REMAP  /*0xdc81 */
+#define PCI_0_CS_2_BASE_ADDR_REMAP		PCI_0SCS_2_BASE_ADDRESS_REMAP  /*0xc4c1 */
+#define PCI_1_CS_2_BASE_ADDR_REMAP		PCI_1SCS_2_BASE_ADDRESS_REMAP  /*0xccc1 */
+#define PCI_0_CS_3_BASE_ADDR_REMAP		PCI_0SCS_3_BASE_ADDRESS_REMAP  /*0xd4c1 */
+#define PCI_1_CS_3_BASE_ADDR_REMAP		PCI_1SCS_3_BASE_ADDRESS_REMAP /* 0xdcc1 */
+#define PCI_0_CS_0_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP
+#define PCI_1_CS_0_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP
+#define PCI_0_CS_1_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP
+#define PCI_1_CS_1_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP
+#define PCI_0_CS_2_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP
+#define PCI_1_CS_2_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP
+#define PCI_0_CS_3_BASE_HIGH_ADDR_REMAP PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP
+#define PCI_1_CS_3_BASE_HIGH_ADDR_REMAP PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP
+#define PCI_0_DEVCS_0_BASE_ADDR_REMAP		PCI_0CS_0_BASE_ADDRESS_REMAP  /*0xc501 */
+#define PCI_1_DEVCS_0_BASE_ADDR_REMAP		PCI_1CS_0_BASE_ADDRESS_REMAP  /*0xcd01 */
+#define PCI_0_DEVCS_1_BASE_ADDR_REMAP		PCI_0CS_1_BASE_ADDRESS_REMAP  /*0xd501 */
+#define PCI_1_DEVCS_1_BASE_ADDR_REMAP		PCI_1CS_1_BASE_ADDRESS_REMAP  /*0xdd01 */
+#define PCI_0_DEVCS_2_BASE_ADDR_REMAP		PCI_0CS_2_BASE_ADDRESS_REMAP  /*0xd581 */
+#define PCI_1_DEVCS_2_BASE_ADDR_REMAP		PCI_1CS_2_BASE_ADDRESS_REMAP  /*0xdd81 */
+#define PCI_0_DEVCS_3_BASE_ADDR_REMAP			PCI_0CS_3_BASE_ADDRESS_REMAP  /*0xc541 */
+#define PCI_1_DEVCS_3_BASE_ADDR_REMAP			PCI_1CS_3_BASE_ADDRESS_REMAP  /*0xcd41 */
+#define PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP    PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP	 /*0xd541 */
+#define PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP    PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP	 /*0xdd41 */
+#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW    PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW  /*0xd5c1 */
+#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW    PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW  /*0xddc1 */
+#define PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH   PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH  /*0xd601 */
+#define PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH   PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH  /*0xde01 */
+#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW	PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW  /*0xd641 */
+#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW	PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW  /*0xde41 */
+#define PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH	PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH  /*0xd681 */
+#define PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH	PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH  /*0xde81 */
+#define PCI_0_P2P_I_O_BASE_ADDR_REMAP			PCI_0P2P_I_O_BASE_ADDRESS_REMAP	 /*0xd6c1 */
+#define PCI_1_P2P_I_O_BASE_ADDR_REMAP			PCI_1P2P_I_O_BASE_ADDRESS_REMAP	 /*0xdec 1 */
+#define PCI_0_CPU_BASE_ADDR_REMAP_LOW			PCI_0CPU_BASE_ADDRESS_REMAP  /*0xd701 */
+#define PCI_1_CPU_BASE_ADDR_REMAP_LOW			PCI_1CPU_BASE_ADDRESS_REMAP  /*0xdf01 */
+#define PCI_0_CPU_BASE_ADDR_REMAP_HIGH			0xd74
+#define PCI_1_CPU_BASE_ADDR_REMAP_HIGH			0xdf4
+#define PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		  PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP  /*0xf001 */
+#define PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		  0xf80
+#define PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		   PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP  /*0xf381 */
+#define PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		   PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP  /*0xfb81 */
+#define PCI_0_ADDR_DECODE_CONTROL				PCI_0ADDRESS_DECODE_CONTROL  /*0xd3c1 */
+#define PCI_1_ADDR_DECODE_CONTROL				PCI_1ADDRESS_DECODE_CONTROL  /*0xdbc1 */
+#define PCI_0_HEADERS_RETARGET_CONTROL			0xF40
+#define PCI_1_HEADERS_RETARGET_CONTROL				0xFc0
+#define PCI_0_HEADERS_RETARGET_BASE				0xF44
+#define PCI_1_HEADERS_RETARGET_BASE				0xFc4
+#define PCI_0_HEADERS_RETARGET_HIGH				0xF48
+#define PCI_1_HEADERS_RETARGET_HIGH				0xFc8
+
+#define PCI_0SCS_0_BANK_SIZE				0xc08
+#define PCI_1SCS_0_BANK_SIZE				0xc88
+#define PCI_0SCS_1_BANK_SIZE				0xd08
+#define PCI_1SCS_1_BANK_SIZE				0xd88
+#define PCI_0SCS_2_BANK_SIZE				0xc0c
+#define PCI_1SCS_2_BANK_SIZE				0xc8c
+#define PCI_0SCS_3_BANK_SIZE				0xd0c
+#define PCI_1SCS_3_BANK_SIZE				0xd8c
+#define PCI_0CS_0_BANK_SIZE				0xc10
+#define PCI_1CS_0_BANK_SIZE				0xc90
+#define PCI_0CS_1_BANK_SIZE				0xd10
+#define PCI_1CS_1_BANK_SIZE				0xd90
+#define PCI_0CS_2_BANK_SIZE				0xd18
+#define PCI_1CS_2_BANK_SIZE				0xd98
+#define PCI_0CS_3_BANK_SIZE				0xc14
+#define PCI_1CS_3_BANK_SIZE				0xc94
+#define PCI_0CS_BOOT_BANK_SIZE				0xd14
+#define PCI_1CS_BOOT_BANK_SIZE				0xd94
+#define PCI_0P2P_MEM0_BAR_SIZE						0xd1c
+#define PCI_1P2P_MEM0_BAR_SIZE						0xd9c
+#define PCI_0P2P_MEM1_BAR_SIZE						0xd20
+#define PCI_1P2P_MEM1_BAR_SIZE						0xda0
+#define PCI_0P2P_I_O_BAR_SIZE						0xd24
+#define PCI_1P2P_I_O_BAR_SIZE						0xda4
+#define PCI_0CPU_BAR_SIZE						0xd28
+#define PCI_1CPU_BAR_SIZE						0xda8
+#define PCI_0DAC_SCS_0_BANK_SIZE				0xe00
+#define PCI_1DAC_SCS_0_BANK_SIZE				0xe80
+#define PCI_0DAC_SCS_1_BANK_SIZE				0xe04
+#define PCI_1DAC_SCS_1_BANK_SIZE				0xe84
+#define PCI_0DAC_SCS_2_BANK_SIZE				0xe08
+#define PCI_1DAC_SCS_2_BANK_SIZE				0xe88
+#define PCI_0DAC_SCS_3_BANK_SIZE				0xe0c
+#define PCI_1DAC_SCS_3_BANK_SIZE				0xe8c
+#define PCI_0DAC_CS_0_BANK_SIZE					0xe10
+#define PCI_1DAC_CS_0_BANK_SIZE					0xe90
+#define PCI_0DAC_CS_1_BANK_SIZE					0xe14
+#define PCI_1DAC_CS_1_BANK_SIZE					0xe94
+#define PCI_0DAC_CS_2_BANK_SIZE					0xe18
+#define PCI_1DAC_CS_2_BANK_SIZE					0xe98
+#define PCI_0DAC_CS_3_BANK_SIZE					0xe1c
+#define PCI_1DAC_CS_3_BANK_SIZE					0xe9c
+#define PCI_0DAC_BOOTCS_BANK_SIZE				0xe20
+#define PCI_1DAC_BOOTCS_BANK_SIZE				0xea0
+
+#define PCI_0DAC_P2P_MEM0_BAR_SIZE				0xe24
+#define PCI_1DAC_P2P_MEM0_BAR_SIZE				0xea4
+#define PCI_0DAC_P2P_MEM1_BAR_SIZE				0xe28
+#define PCI_1DAC_P2P_MEM1_BAR_SIZE				0xea8
+#define PCI_0DAC_CPU_BAR_SIZE						0xe2c
+#define PCI_1DAC_CPU_BAR_SIZE						0xeac
+#define PCI_0EXPANSION_ROM_BAR_SIZE				0xd2c
+#define PCI_1EXPANSION_ROM_BAR_SIZE				0xdac
+#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE		0xc3c
+#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE		0xcbc
+#define PCI_0SCS_0_BASE_ADDRESS_REMAP			0xc48
+#define PCI_1SCS_0_BASE_ADDRESS_REMAP			0xcc8
+#define PCI_0SCS_1_BASE_ADDRESS_REMAP			0xd48
+#define PCI_1SCS_1_BASE_ADDRESS_REMAP			0xdc8
+#define PCI_0SCS_2_BASE_ADDRESS_REMAP			0xc4c
+#define PCI_1SCS_2_BASE_ADDRESS_REMAP			0xccc
+#define PCI_0SCS_3_BASE_ADDRESS_REMAP			0xd4c
+#define PCI_1SCS_3_BASE_ADDRESS_REMAP			0xdcc
+#define PCI_0CS_0_BASE_ADDRESS_REMAP			0xc50
+#define PCI_1CS_0_BASE_ADDRESS_REMAP			0xcd0
+#define PCI_0CS_1_BASE_ADDRESS_REMAP			0xd50
+#define PCI_1CS_1_BASE_ADDRESS_REMAP			0xdd0
+#define PCI_0CS_2_BASE_ADDRESS_REMAP			0xd58
+#define PCI_1CS_2_BASE_ADDRESS_REMAP			0xdd8
+#define PCI_0CS_3_BASE_ADDRESS_REMAP			0xc54
+#define PCI_1CS_3_BASE_ADDRESS_REMAP			0xcd4
+#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP	0xd54
+#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP	0xdd4
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW			0xd5c
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW		  0xddc
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		  0xd60
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		  0xde0
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW		 0xd64
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW		 0xde4
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		 0xd68
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		 0xde8
+#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP				0xd6c
+#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP				0xdec
+#define PCI_0CPU_BASE_ADDRESS_REMAP				0xd70
+#define PCI_1CPU_BASE_ADDRESS_REMAP				0xdf0
+#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP			0xf00
+#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP			0xff0
+#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP			0xf04
+#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP			0xf84
+#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP			0xf08
+#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP			0xf88
+#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP			0xf0c
+#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP			0xf8c
+#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP			0xf10
+#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP			0xf90
+#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP			0xf14
+#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP			0xf94
+#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP			0xf18
+#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP			0xf98
+#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP			0xf1c
+#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP			0xf9c
+#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP			0xf20
+#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP		    0xfa0
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW     0xf24
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW     0xfa4
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH    0xf28
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH    0xfa8
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	0xf2c
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW     0xfac
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH    0xf30
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH    0xfb0
+#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP				0xf34
+#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP				0xfb4
+#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP			0xf38
+#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP			0xfb8
+#define PCI_0ADDRESS_DECODE_CONTROL				0xd3c
+#define PCI_1ADDRESS_DECODE_CONTROL				0xdbc
+
+/****************************************/
+/* PCI Control				*/
+/****************************************/
+
+#define PCI_0COMMAND										0xc00
+#define PCI_1COMMAND										0xc80
+#define PCI_0MODE					    0xd00
+#define PCI_1MODE					    0xd80
+#define PCI_0TIMEOUT_RETRY									0xc04
+#define PCI_1TIMEOUT_RETRY									0xc84
+#define PCI_0READ_BUFFER_DISCARD_TIMER			    0xd04
+#define PCI_1READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MSI_0TRIGGER_TIMER				    0xc38
+#define MSI_1TRIGGER_TIMER				    0xcb8
+#define PCI_0ARBITER_CONTROL				    0x1d00
+#define PCI_1ARBITER_CONTROL				    0x1d80
+/* changing untill here */
+#define PCI_0CROSS_BAR_CONTROL_LOW			     0x1d08
+#define PCI_0CROSS_BAR_CONTROL_HIGH			     0x1d0c
+#define PCI_0CROSS_BAR_TIMEOUT				     0x1d04
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW	     0x1d18
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	     0x1d1c
+#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER		     0x1d10
+#define PCI_0P2P_CONFIGURATION				     0x1d14
+#define PCI_0ACCESS_CONTROL_BASE_0_LOW			     0x1e00
+#define PCI_0ACCESS_CONTROL_BASE_0_HIGH			     0x1e04
+#define PCI_0ACCESS_CONTROL_TOP_0			     0x1e08
+#define PCI_0ACCESS_CONTROL_BASE_1_LOW			     0x1e10
+#define PCI_0ACCESS_CONTROL_BASE_1_HIGH			     0x1e14
+#define PCI_0ACCESS_CONTROL_TOP_1			     0x1e18
+#define PCI_0ACCESS_CONTROL_BASE_2_LOW			     0x1e20
+#define PCI_0ACCESS_CONTROL_BASE_2_HIGH			     0x1e24
+#define PCI_0ACCESS_CONTROL_TOP_2			     0x1e28
+#define PCI_0ACCESS_CONTROL_BASE_3_LOW			     0x1e30
+#define PCI_0ACCESS_CONTROL_BASE_3_HIGH			     0x1e34
+#define PCI_0ACCESS_CONTROL_TOP_3			     0x1e38
+#define PCI_0ACCESS_CONTROL_BASE_4_LOW			     0x1e40
+#define PCI_0ACCESS_CONTROL_BASE_4_HIGH			     0x1e44
+#define PCI_0ACCESS_CONTROL_TOP_4			     0x1e48
+#define PCI_0ACCESS_CONTROL_BASE_5_LOW			     0x1e50
+#define PCI_0ACCESS_CONTROL_BASE_5_HIGH			     0x1e54
+#define PCI_0ACCESS_CONTROL_TOP_5			     0x1e58
+#define PCI_0ACCESS_CONTROL_BASE_6_LOW			     0x1e60
+#define PCI_0ACCESS_CONTROL_BASE_6_HIGH			     0x1e64
+#define PCI_0ACCESS_CONTROL_TOP_6			     0x1e68
+#define PCI_0ACCESS_CONTROL_BASE_7_LOW			     0x1e70
+#define PCI_0ACCESS_CONTROL_BASE_7_HIGH			     0x1e74
+#define PCI_0ACCESS_CONTROL_TOP_7			     0x1e78
+#define PCI_1CROSS_BAR_CONTROL_LOW			     0x1d88
+#define PCI_1CROSS_BAR_CONTROL_HIGH			     0x1d8c
+#define PCI_1CROSS_BAR_TIMEOUT				     0x1d84
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW	     0x1d98
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	     0x1d9c
+#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER		     0x1d90
+#define PCI_1P2P_CONFIGURATION				     0x1d94
+#define PCI_1ACCESS_CONTROL_BASE_0_LOW			     0x1e80
+#define PCI_1ACCESS_CONTROL_BASE_0_HIGH			     0x1e84
+#define PCI_1ACCESS_CONTROL_TOP_0			     0x1e88
+#define PCI_1ACCESS_CONTROL_BASE_1_LOW			     0x1e90
+#define PCI_1ACCESS_CONTROL_BASE_1_HIGH			     0x1e94
+#define PCI_1ACCESS_CONTROL_TOP_1			     0x1e98
+#define PCI_1ACCESS_CONTROL_BASE_2_LOW			     0x1ea0
+#define PCI_1ACCESS_CONTROL_BASE_2_HIGH			     0x1ea4
+#define PCI_1ACCESS_CONTROL_TOP_2			     0x1ea8
+#define PCI_1ACCESS_CONTROL_BASE_3_LOW			     0x1eb0
+#define PCI_1ACCESS_CONTROL_BASE_3_HIGH			     0x1eb4
+#define PCI_1ACCESS_CONTROL_TOP_3			     0x1eb8
+#define PCI_1ACCESS_CONTROL_BASE_4_LOW			     0x1ec0
+#define PCI_1ACCESS_CONTROL_BASE_4_HIGH			     0x1ec4
+#define PCI_1ACCESS_CONTROL_TOP_4			     0x1ec8
+#define PCI_1ACCESS_CONTROL_BASE_5_LOW			     0x1ed0
+#define PCI_1ACCESS_CONTROL_BASE_5_HIGH			     0x1ed4
+#define PCI_1ACCESS_CONTROL_TOP_5			     0x1ed8
+#define PCI_1ACCESS_CONTROL_BASE_6_LOW			     0x1ee0
+#define PCI_1ACCESS_CONTROL_BASE_6_HIGH			     0x1ee4
+#define PCI_1ACCESS_CONTROL_TOP_6			     0x1ee8
+#define PCI_1ACCESS_CONTROL_BASE_7_LOW			     0x1ef0
+#define PCI_1ACCESS_CONTROL_BASE_7_HIGH			     0x1ef4
+#define PCI_1ACCESS_CONTROL_TOP_7			     0x1ef8
+
+/****************************************/
+/* PCI Snoop Control			*/
+/****************************************/
+
+#define PCI_0SNOOP_CONTROL_BASE_0_LOW			     0x1f00
+#define PCI_0SNOOP_CONTROL_BASE_0_HIGH			     0x1f04
+#define PCI_0SNOOP_CONTROL_TOP_0			     0x1f08
+#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW			     0x1f10
+#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH		     0x1f14
+#define PCI_0SNOOP_CONTROL_TOP_1			     0x1f18
+#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW			     0x1f20
+#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH		     0x1f24
+#define PCI_0SNOOP_CONTROL_TOP_2			     0x1f28
+#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW			     0x1f30
+#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH		     0x1f34
+#define PCI_0SNOOP_CONTROL_TOP_3			     0x1f38
+#define PCI_1SNOOP_CONTROL_BASE_0_LOW			     0x1f80
+#define PCI_1SNOOP_CONTROL_BASE_0_HIGH			     0x1f84
+#define PCI_1SNOOP_CONTROL_TOP_0			     0x1f88
+#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW			     0x1f90
+#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH		     0x1f94
+#define PCI_1SNOOP_CONTROL_TOP_1			     0x1f98
+#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW			     0x1fa0
+#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH		     0x1fa4
+#define PCI_1SNOOP_CONTROL_TOP_2			     0x1fa8
+#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW			     0x1fb0
+#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH		     0x1fb4
+#define PCI_1SNOOP_CONTROL_TOP_3			     0x1fb8
+
+/****************************************/
+/* PCI Configuration Address		*/
+/****************************************/
+
+#define PCI_0CONFIGURATION_ADDRESS							0xcf8
+#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER		0xcfc
+#define PCI_1CONFIGURATION_ADDRESS							0xc78
+#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER		0xc7c
+#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xc34
+#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xcb4
+
+/****************************************/
+/* PCI Error Report			*/
+/****************************************/
+
+#define PCI_0SERR_MASK										 0xc28
+#define PCI_0ERROR_ADDRESS_LOW				     0x1d40
+#define PCI_0ERROR_ADDRESS_HIGH				     0x1d44
+#define PCI_0ERROR_DATA_LOW				     0x1d48
+#define PCI_0ERROR_DATA_HIGH				     0x1d4c
+#define PCI_0ERROR_COMMAND				     0x1d50
+#define PCI_0ERROR_CAUSE				     0x1d58
+#define PCI_0ERROR_MASK					     0x1d5c
+#define PCI_1SERR_MASK										 0xca8
+#define PCI_1ERROR_ADDRESS_LOW				     0x1dc0
+#define PCI_1ERROR_ADDRESS_HIGH				     0x1dc4
+#define PCI_1ERROR_DATA_LOW				     0x1dc8
+#define PCI_1ERROR_DATA_HIGH				     0x1dcc
+#define PCI_1ERROR_COMMAND				     0x1dd0
+#define PCI_1ERROR_CAUSE				     0x1dd8
+#define PCI_1ERROR_MASK					     0x1ddc
+
+
+/****************************************/
+/* Lslave Debug	 (for internal use)	*/
+/****************************************/
+
+#define L_SLAVE_X0_ADDRESS				    0x1d20
+#define L_SLAVE_X0_COMMAND_AND_ID			    0x1d24
+#define L_SLAVE_X1_ADDRESS				    0x1d28
+#define L_SLAVE_X1_COMMAND_AND_ID			    0x1d2c
+#define L_SLAVE_WRITE_DATA_LOW				    0x1d30
+#define L_SLAVE_WRITE_DATA_HIGH				    0x1d34
+#define L_SLAVE_WRITE_BYTE_ENABLE			    0x1d60
+#define L_SLAVE_READ_DATA_LOW				    0x1d38
+#define L_SLAVE_READ_DATA_HIGH				    0x1d3c
+#define L_SLAVE_READ_ID					    0x1d64
+
+/****************************************/
+/* PCI Configuration Function 0		*/
+/****************************************/
+
+#define PCI_DEVICE_AND_VENDOR_ID							0x000
+#define PCI_STATUS_AND_COMMAND								0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID					0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE		0x00C
+#define PCI_SCS_0_BASE_ADDRESS							0x010
+#define PCI_SCS_1_BASE_ADDRESS							    0x014
+#define PCI_SCS_2_BASE_ADDRESS							    0x018
+#define PCI_SCS_3_BASE_ADDRESS							0x01C
+#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
+#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
+#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID			0x02C
+#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER				0x030
+#define PCI_CAPABILTY_LIST_POINTER			    0x034
+#define PCI_INTERRUPT_PIN_AND_LINE						    0x03C
+#define PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define PCI_VPD_ADDRESS					    0x048
+#define PCI_VPD_DATA					    0x04c
+#define PCI_MSI_MESSAGE_CONTROL				    0x050
+#define PCI_MSI_MESSAGE_ADDRESS				    0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDRESS			    0x058
+#define PCI_MSI_MESSAGE_DATA				    0x05c
+#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY		    0x058
+
+/****************************************/
+/* PCI Configuration Function 1		*/
+/****************************************/
+
+#define PCI_CS_0_BASE_ADDRESS							0x110
+#define PCI_CS_1_BASE_ADDRESS							    0x114
+#define PCI_CS_2_BASE_ADDRESS							    0x118
+#define PCI_CS_3_BASE_ADDRESS							0x11c
+#define PCI_BOOTCS_BASE_ADDRESS				    0x120
+
+/****************************************/
+/* PCI Configuration Function 2		*/
+/****************************************/
+
+#define PCI_P2P_MEM0_BASE_ADDRESS						0x210
+ /*#define PCI_P2P_MEM1_BASE_ADDRESS							0x2141 */
+#define PCI_P2P_I_O_BASE_ADDRESS							0x218
+ /*#define PCI_CPU_BASE_ADDRESS							    0x21c1 */
+
+/****************************************/
+/* PCI Configuration Function 4		*/
+/****************************************/
+
+#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW						0x410
+#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH					    0x414
+#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW					    0x418
+#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH					    0x41c
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW		    0x420
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH		    0x424
+
+
+/****************************************/
+/* PCI Configuration Function 5		*/
+/****************************************/
+
+#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW						0x510
+#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH					    0x514
+#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW					    0x518
+#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH					    0x51c
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW		    0x520
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH		    0x524
+
+
+/****************************************/
+/* PCI Configuration Function 6		*/
+/****************************************/
+
+#define PCI_DAC_CS_0_BASE_ADDRESS_LOW						0x610
+#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH					    0x614
+#define PCI_DAC_CS_1_BASE_ADDRESS_LOW					    0x618
+#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH					    0x61c
+#define PCI_DAC_CS_2_BASE_ADDRESS_LOW				0x620
+#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH				0x624
+
+/****************************************/
+/* PCI Configuration Function 7		*/
+/****************************************/
+
+#define PCI_DAC_CS_3_BASE_ADDRESS_LOW						0x710
+#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH					    0x714
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW					    0x718
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH				    0x71c
+#define PCI_DAC_CPU_BASE_ADDRESS_LOW				0x720
+#define PCI_DAC_CPU_BASE_ADDRESS_HIGH				0x724
+
+/****************************** MV64360 and MV64460 PCI ***************************/
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define PCI_0_DLL_STATUS_AND_COMMAND				0x1d20
+#define PCI_1_DLL_STATUS_AND_COMMAND				0x1da0
+#define PCI_0_MPP_PADS_DRIVE_CONTROL				0x1d1C
+#define PCI_1_MPP_PADS_DRIVE_CONTROL				0x1d9C
+#define PCI_0_COMMAND					0xc00
+#define PCI_1_COMMAND					0xc80
+#define PCI_0_MODE							0xd00
+#define PCI_1_MODE							0xd80
+#define PCI_0_RETRY						0xc04
+#define PCI_1_RETRY						0xc84
+#define PCI_0_READ_BUFFER_DISCARD_TIMER				0xd04
+#define PCI_1_READ_BUFFER_DISCARD_TIMER				0xd84
+#define PCI_0_MSI_TRIGGER_TIMER						0xc38
+#define PCI_1_MSI_TRIGGER_TIMER						0xcb8
+#define PCI_0_ARBITER_CONTROL						0x1d00
+#define PCI_1_ARBITER_CONTROL						0x1d80
+#define PCI_0_CROSS_BAR_CONTROL_LOW				0x1d08
+#define PCI_1_CROSS_BAR_CONTROL_LOW				0x1d88
+#define PCI_0_CROSS_BAR_CONTROL_HIGH				0x1d0c
+#define PCI_1_CROSS_BAR_CONTROL_HIGH				0x1d8c
+#define PCI_0_CROSS_BAR_TIMEOUT					0x1d04
+#define PCI_1_CROSS_BAR_TIMEOUT					0x1d84
+#define PCI_0_SYNC_BARRIER_TRIGGER_REG				0x1D18
+#define PCI_1_SYNC_BARRIER_TRIGGER_REG				0x1D98
+#define PCI_0_SYNC_BARRIER_VIRTUAL_REG				0x1d10
+#define PCI_1_SYNC_BARRIER_VIRTUAL_REG				0x1d90
+#define PCI_0_P2P_CONFIG						0x1d14
+#define PCI_1_P2P_CONFIG						0x1d94
+
+#define PCI_0_ACCESS_CONTROL_BASE_0_LOW				0x1e00
+#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH			0x1e04
+#define PCI_0_ACCESS_CONTROL_SIZE_0				0x1e08
+#define PCI_0_ACCESS_CONTROL_BASE_1_LOW				0x1e10
+#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH			0x1e14
+#define PCI_0_ACCESS_CONTROL_SIZE_1				0x1e18
+#define PCI_0_ACCESS_CONTROL_BASE_2_LOW				0x1e20
+#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH			0x1e24
+#define PCI_0_ACCESS_CONTROL_SIZE_2				0x1e28
+#define PCI_0_ACCESS_CONTROL_BASE_3_LOW				0x1e30
+#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH			0x1e34
+#define PCI_0_ACCESS_CONTROL_SIZE_3				0x1e38
+#define PCI_0_ACCESS_CONTROL_BASE_4_LOW				0x1e40
+#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH			0x1e44
+#define PCI_0_ACCESS_CONTROL_SIZE_4				0x1e48
+#define PCI_0_ACCESS_CONTROL_BASE_5_LOW				0x1e50
+#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH			0x1e54
+#define PCI_0_ACCESS_CONTROL_SIZE_5				0x1e58
+
+#define PCI_1_ACCESS_CONTROL_BASE_0_LOW				0x1e80
+#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH			0x1e84
+#define PCI_1_ACCESS_CONTROL_SIZE_0				0x1e88
+#define PCI_1_ACCESS_CONTROL_BASE_1_LOW				0x1e90
+#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH			0x1e94
+#define PCI_1_ACCESS_CONTROL_SIZE_1				0x1e98
+#define PCI_1_ACCESS_CONTROL_BASE_2_LOW				0x1ea0
+#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH			0x1ea4
+#define PCI_1_ACCESS_CONTROL_SIZE_2				0x1ea8
+#define PCI_1_ACCESS_CONTROL_BASE_3_LOW				0x1eb0
+#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH			0x1eb4
+#define PCI_1_ACCESS_CONTROL_SIZE_3				0x1eb8
+#define PCI_1_ACCESS_CONTROL_BASE_4_LOW				0x1ec0
+#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH			0x1ec4
+#define PCI_1_ACCESS_CONTROL_SIZE_4				0x1ec8
+#define PCI_1_ACCESS_CONTROL_BASE_5_LOW				0x1ed0
+#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH			0x1ed4
+#define PCI_1_ACCESS_CONTROL_SIZE_5				0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define PCI_0_CONFIG_ADDR				0xcf8
+#define PCI_0_CONFIG_DATA_VIRTUAL_REG				0xcfc
+#define PCI_1_CONFIG_ADDR				0xc78
+#define PCI_1_CONFIG_DATA_VIRTUAL_REG				0xc7c
+#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
+#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define PCI_0_SERR_MASK					0xc28
+#define PCI_1_SERR_MASK					0xca8
+#define PCI_0_ERROR_ADDR_LOW						0x1d40
+#define PCI_1_ERROR_ADDR_LOW						0x1dc0
+#define PCI_0_ERROR_ADDR_HIGH						0x1d44
+#define PCI_1_ERROR_ADDR_HIGH						0x1dc4
+#define PCI_0_ERROR_ATTRIBUTE						0x1d48
+#define PCI_1_ERROR_ATTRIBUTE						0x1dc8
+#define PCI_0_ERROR_COMMAND						0x1d50
+#define PCI_1_ERROR_COMMAND						0x1dd0
+#define PCI_0_ERROR_CAUSE						0x1d58
+#define PCI_1_ERROR_CAUSE						0x1dd8
+#define PCI_0_ERROR_MASK						0x1d5c
+#define PCI_1_ERROR_MASK						0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define PCI_0_MMASK							0X1D24
+#define PCI_1_MMASK							0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define PCI_DEVICE_AND_VENDOR_ID			0x000
+#define PCI_STATUS_AND_COMMAND			0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID			0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE		0x00C
+
+#define PCI_SCS_0_BASE_ADDR_LOW				0x010
+#define PCI_SCS_0_BASE_ADDR_HIGH			0x014
+#define PCI_SCS_1_BASE_ADDR_LOW				0x018
+#define PCI_SCS_1_BASE_ADDR_HIGH			0x01C
+#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW    0x020
+#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH   0x024
+ /*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	0x02c1 */
+#define PCI_EXPANSION_ROM_BASE_ADDR_REG		0x030
+#define PCI_CAPABILTY_LIST_POINTER				0x034
+#define PCI_INTERRUPT_PIN_AND_LINE			0x03C
+       /* capability list */
+#define PCI_POWER_MANAGEMENT_CAPABILITY				0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL	     0x044
+#define PCI_VPD_ADDR							0x048
+#define PCI_VPD_DATA							0x04c
+#define PCI_MSI_MESSAGE_CONTROL					0x050
+#define PCI_MSI_MESSAGE_ADDR						0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDR				0x058
+#define PCI_MSI_MESSAGE_DATA						0x05c
+#define PCI_X_COMMAND							0x060
+#define PCI_X_STATUS							0x064
+#define PCI_COMPACT_PCI_HOT_SWAP				0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define PCI_SCS_2_BASE_ADDR_LOW				0x110
+#define PCI_SCS_2_BASE_ADDR_HIGH			0x114
+#define PCI_SCS_3_BASE_ADDR_LOW				0x118
+#define PCI_SCS_3_BASE_ADDR_HIGH			0x11c
+#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW					0x120
+#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH				0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define PCI_DEVCS_0_BASE_ADDR_LOW			0x210
+#define PCI_DEVCS_0_BASE_ADDR_HIGH			0x214
+#define PCI_DEVCS_1_BASE_ADDR_LOW			0x218
+#define PCI_DEVCS_1_BASE_ADDR_HIGH				0x21c
+#define PCI_DEVCS_2_BASE_ADDR_LOW			0x220
+#define PCI_DEVCS_2_BASE_ADDR_HIGH				0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define PCI_DEVCS_3_BASE_ADDR_LOW			0x310
+#define PCI_DEVCS_3_BASE_ADDR_HIGH			0x314
+#define PCI_BOOT_CS_BASE_ADDR_LOW			0x318
+#define PCI_BOOT_CS_BASE_ADDR_HIGH				0x31c
+#define PCI_CPU_BASE_ADDR_LOW				0x220
+#define PCI_CPU_BASE_ADDR_HIGH				0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define PCI_P2P_MEM0_BASE_ADDR_LOW			0x410
+#define PCI_P2P_MEM0_BASE_ADDR_HIGH			0x414
+#define PCI_P2P_MEM1_BASE_ADDR_LOW			0x418
+#define PCI_P2P_MEM1_BASE_ADDR_HIGH			0x41c
+#define PCI_P2P_I_O_BASE_ADDR						0x420
+#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		  0x424
+
+/****************************** MV64360 and MV64460 PCI End ***************************/
+/****************************************/
+/* I20 Support registers				*/
+/****************************************/
+
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01C
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07C
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C1C
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C2C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE		0x1C40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE		0x1C44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE				0x1C50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE			0x1C54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C6C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C7C
+
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE			0x010
+#define I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE				0x014
+#define I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE				0x018
+#define I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE				0x01C
+#define I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE				0x020
+#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE		0x024
+#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE			0x028
+#define I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE				0x02C
+#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE		0x030
+#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE		0x034
+#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE		0x040
+#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE		0x044
+#define I2O_QUEUE_CONTROL_REG_PCI_0_SIDE			0x050
+#define I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE			0x054
+#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE		0x060
+#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE		0x064
+#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE		0x068
+#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE		0x06C
+#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE		0x070
+#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE		0x074
+#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE		0x0F8
+#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE		0x0FC
+
+#define I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE			0x090
+#define I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE				0x094
+#define I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE				0x098
+#define I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE				0x09C
+#define I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE				0x0A0
+#define I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE		0x0A4
+#define I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE			0x0A8
+#define I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE				0x0AC
+#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE		0x0B0
+#define I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE		0x0B4
+#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE		0x0C0
+#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE		0x0C4
+#define I2O_QUEUE_CONTROL_REG_PCI_1_SIDE			0x0D0
+#define I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE			0x0D4
+#define I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE		0x0E0
+#define I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE		0x0E4
+#define I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE		0x0E8
+#define I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE		0x0EC
+#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE		0x0F0
+#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE		0x0F4
+#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE		0x078
+#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE		0x07C
+
+#define I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE			0x1C10
+#define I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE				0x1C14
+#define I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE				0x1C18
+#define I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE				0x1C1C
+#define I2O_INBOUND_DOORBELL_REG_CPU0_SIDE				0x1C20
+#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE			0x1C24
+#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE			0x1C28
+#define I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE				0x1C2C
+#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE		0x1C30
+#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE		0x1C34
+#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE		0x1C40
+#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE		0x1C44
+#define I2O_QUEUE_CONTROL_REG_CPU0_SIDE				0x1C50
+#define I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE				0x1C54
+#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE		0x1C60
+#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE		0x1C64
+#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE		0x1C68
+#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE		0x1C6C
+#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE		0x1C70
+#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE		0x1C74
+#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE		0x1CF8
+#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE		0x1CFC
+#define I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE			0x1C90
+#define I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE				0x1C94
+#define I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE				0x1C98
+#define I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE				0x1C9C
+#define I2O_INBOUND_DOORBELL_REG_CPU1_SIDE				0x1CA0
+#define I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE			0x1CA4
+#define I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE			0x1CA8
+#define I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE				0x1CAC
+#define I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE		0x1CB0
+#define I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE		0x1CB4
+#define I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE		0x1CC0
+#define I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE		0x1CC4
+#define I2O_QUEUE_CONTROL_REG_CPU1_SIDE				0x1CD0
+#define I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE				0x1CD4
+#define I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE		0x1CE0
+#define I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE		0x1CE4
+#define I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE		0x1CE8
+#define I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE		0x1CEC
+#define I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE		0x1CF0
+#define I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE		0x1CF4
+#define I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE		0x1C78
+#define I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE		0x1C7C
+
+
+/****************************************/
+/* Communication Unit Registers		*/
+/****************************************/
+/*
+#define ETHERNET_0_ADDRESS_CONTROL_LOW						0xf200
+#define ETHERNET_0_ADDRESS_CONTROL_HIGH			    0xf204
+#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	    0xf208
+#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	    0xf20c
+#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf210
+#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf214
+#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS		    0xf218
+#define ETHERNET_1_ADDRESS_CONTROL_LOW			    0xf220
+#define ETHERNET_1_ADDRESS_CONTROL_HIGH			    0xf224
+#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	    0xf228
+#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	    0xf22c
+#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf230
+#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf234
+#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS		    0xf238
+#define ETHERNET_2_ADDRESS_CONTROL_LOW			    0xf240
+#define ETHERNET_2_ADDRESS_CONTROL_HIGH			    0xf244
+#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	    0xf248
+#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	    0xf24c
+#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf250
+#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf254
+#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS		    0xf258
+ */
+#define MPSC_0_ADDRESS_CONTROL_LOW			    0xf280
+#define MPSC_0_ADDRESS_CONTROL_HIGH			    0xf284
+#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		    0xf288
+#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		    0xf28c
+#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf290
+#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf294
+#define MPSC_1_ADDRESS_CONTROL_LOW			    0xf2c0
+#define MPSC_1_ADDRESS_CONTROL_HIGH			    0xf2c4
+#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		    0xf2c8
+#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		    0xf2cc
+#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf2d0
+#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	    0xf2d4
+ /*#define SERIAL_INIT_PCI_HIGH_ADDRESS			       0xf3201 */
+#define COMM_UNIT_ARBITER_CONTROL			    0xf300
+#define COMM_UNIT_CROSS_BAR_TIMEOUT			    0xf304
+#define COMM_UNIT_INTERRUPT_CAUSE			    0xf310
+#define COMM_UNIT_INTERRUPT_MASK			    0xf314
+#define COMM_UNIT_ERROR_ADDRESS				    0xf314
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+ /*#define SERIAL_INIT_LAST_DATA					0xf3241 */
+ /*#define SERIAL_INIT_STATUS_AND_CONTROL			0xf3281 */
+#define SERIAL_INIT_LAST_DATA						0xf324
+#define SERIAL_INIT_CONTROL						0xf328
+#define SERIAL_INIT_STATUS						0xf32c
+
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define ETH_PHY_ADDR_REG			0x2000
+#define ETH_SMI_REG					0x2004
+#define ETH_UNIT_DEFAULT_ADDR_REG		0x2008
+#define ETH_UNIT_DEFAULTID_REG			0x200c
+#define ETH_UNIT_INTERRUPT_CAUSE_REG	0x2080
+#define ETH_UNIT_INTERRUPT_MASK_REG	0x2084
+#define ETH_UNIT_INTERNAL_USE_REG		0x24fc
+#define ETH_UNIT_ERROR_ADDR_REG			0x2094
+#define ETH_BAR_0					0x2200
+#define ETH_BAR_1					0x2208
+#define ETH_BAR_2					0x2210
+#define ETH_BAR_3					0x2218
+#define ETH_BAR_4					0x2220
+#define ETH_BAR_5					0x2228
+#define ETH_SIZE_REG_0				0x2204
+#define ETH_SIZE_REG_1				0x220c
+#define ETH_SIZE_REG_2				0x2214
+#define ETH_SIZE_REG_3				0x221c
+#define ETH_SIZE_REG_4				0x2224
+#define ETH_SIZE_REG_5					0x222c
+#define ETH_HEADERS_RETARGET_BASE_REG			0x2230
+#define ETH_HEADERS_RETARGET_CONTROL_REG	0x2234
+#define ETH_HIGH_ADDR_REMAP_REG_0		0x2280
+#define ETH_HIGH_ADDR_REMAP_REG_1		0x2284
+#define ETH_HIGH_ADDR_REMAP_REG_2		0x2288
+#define ETH_HIGH_ADDR_REMAP_REG_3			0x228c
+#define ETH_BASE_ADDR_ENABLE_REG			0x2290
+#define ETH_ACCESS_PROTECTION_REG(port)			(0x2294 + (port<<2))
+#define ETH_MIB_COUNTERS_BASE(port)			(0x3000 + (port<<7))
+#define ETH_PORT_CONFIG_REG(port)				(0x2400 + (port<<10))
+#define ETH_PORT_CONFIG_EXTEND_REG(port)		(0x2404 + (port<<10))
+#define ETH_MII_SERIAL_PARAMETRS_REG(port)		(0x2408 + (port<<10))
+#define ETH_GMII_SERIAL_PARAMETRS_REG(port)		(0x240c + (port<<10))
+#define ETH_VLAN_ETHERTYPE_REG(port)			(0x2410 + (port<<10))
+#define ETH_MAC_ADDR_LOW(port)					(0x2414 + (port<<10))
+#define ETH_MAC_ADDR_HIGH(port)					(0x2418 + (port<<10))
+#define ETH_SDMA_CONFIG_REG(port)				(0x241c + (port<<10))
+#define ETH_DSCP_0(port)					(0x2420 + (port<<10))
+#define ETH_DSCP_1(port)					(0x2424 + (port<<10))
+#define ETH_DSCP_2(port)					(0x2428 + (port<<10))
+#define ETH_DSCP_3(port)					(0x242c + (port<<10))
+#define ETH_DSCP_4(port)					(0x2430 + (port<<10))
+#define ETH_DSCP_5(port)					(0x2434 + (port<<10))
+#define ETH_DSCP_6(port)					(0x2438 + (port<<10))
+#define ETH_PORT_SERIAL_CONTROL_REG(port)		(0x243c + (port<<10))
+#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		(0x2440 + (port<<10))
+#define ETH_PORT_STATUS_REG(port)				(0x2444 + (port<<10))
+#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)	(0x2448 + (port<<10))
+#define ETH_TX_QUEUE_FIXED_PRIORITY(port)		(0x244c + (port<<10))
+#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)		(0x2450 + (port<<10))
+#define ETH_MAXIMUM_TRANSMIT_UNIT(port)				(0x2458 + (port<<10))
+#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)		(0x245c + (port<<10))
+#define ETH_INTERRUPT_CAUSE_REG(port)				(0x2460 + (port<<10))
+#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)			(0x2464 + (port<<10))
+#define ETH_INTERRUPT_MASK_REG(port)				(0x2468 + (port<<10))
+#define ETH_INTERRUPT_EXTEND_MASK_REG(port)			(0x246c + (port<<10))
+#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)			(0x2470 + (port<<10))
+#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)			(0x2474 + (port<<10))
+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)			(0x247c + (port<<10))
+#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)			(0x2484 + (port<<10)
+#define ETH_PORT_DEBUG_0_REG(port)					(0x248c + (port<<10))
+#define ETH_PORT_DEBUG_1_REG(port)					(0x2490 + (port<<10))
+#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)			(0x2494 + (port<<10))
+#define ETH_INTERNAL_USE_REG(port)					(0x24fc + (port<<10))
+#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)			(0x2680 + (port<<10))
+#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)			(0x2684 + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)			(0x260c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)			(0x261c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)			(0x262c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)			(0x263c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)			(0x264c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)			(0x265c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)			(0x266c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)			(0x267c + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)			(0x26c0 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)			(0x26c4 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)			(0x26c8 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)			(0x26cc + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)			(0x26d0 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)			(0x26d4 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)			(0x26d8 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)			(0x26dc + (port<<10))
+#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)			(0x2700 + (port<<10))
+#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)			(0x2710 + (port<<10))
+#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)			(0x2720 + (port<<10))
+#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)			(0x2730 + (port<<10))
+#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)			(0x2740 + (port<<10))
+#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)			(0x2750 + (port<<10))
+#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)			(0x2760 + (port<<10))
+#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)			(0x2770 + (port<<10))
+#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)		(0x2704 + (port<<10))
+#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)		(0x2714 + (port<<10))
+#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)		(0x2724 + (port<<10))
+#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)		(0x2734 + (port<<10))
+#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)		(0x2744 + (port<<10))
+#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)		(0x2754 + (port<<10))
+#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)		(0x2764 + (port<<10))
+#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)		(0x2774 + (port<<10))
+#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)			(0x2708 + (port<<10))
+#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)			(0x2718 + (port<<10))
+#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)			(0x2728 + (port<<10))
+#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)			(0x2738 + (port<<10))
+#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)			(0x2748 + (port<<10))
+#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)			(0x2758 + (port<<10))
+#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)			(0x2768 + (port<<10))
+#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)			(0x2778 + (port<<10))
+#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)			(0x2780 + (port<<10))
+#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)	(0x3400 + (port<<10))
+#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)		(0x3500 + (port<<10))
+#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)			(0x3600 + (port<<10))
+
+/****************************************/
+/* Cunit Debug	(for internal use)     */
+/****************************************/
+
+#define CUNIT_ADDRESS					    0xf340
+#define CUNIT_COMMAND_AND_ID				    0xf344
+#define CUNIT_WRITE_DATA_LOW				    0xf348
+#define CUNIT_WRITE_DATA_HIGH				    0xf34c
+#define CUNIT_WRITE_BYTE_ENABLE				    0xf358
+#define CUNIT_READ_DATA_LOW				    0xf350
+#define CUNIT_READ_DATA_HIGH				    0xf354
+#define CUNIT_READ_ID					    0xf35c
+
+/****************************************/
+/* Fast Ethernet Unit Registers		*/
+/****************************************/
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define ETH_PHY_ADDR_REG				0x2000
+#define ETH_SMI_REG						0x2004
+#define ETH_UNIT_DEFAULT_ADDR_REG			0x2008
+#define ETH_UNIT_DEFAULTID_REG				0x200c
+#define ETH_UNIT_INTERRUPT_CAUSE_REG			0x2080
+#define ETH_UNIT_INTERRUPT_MASK_REG		0x2084
+#define ETH_UNIT_INTERNAL_USE_REG			0x24fc
+#define ETH_UNIT_ERROR_ADDR_REG				0x2094
+#define ETH_BAR_0						0x2200
+#define ETH_BAR_1						0x2208
+#define ETH_BAR_2						0x2210
+#define ETH_BAR_3						0x2218
+#define ETH_BAR_4						0x2220
+#define ETH_BAR_5						0x2228
+#define ETH_SIZE_REG_0						0x2204
+#define ETH_SIZE_REG_1						0x220c
+#define ETH_SIZE_REG_2						0x2214
+#define ETH_SIZE_REG_3						0x221c
+#define ETH_SIZE_REG_4						0x2224
+#define ETH_SIZE_REG_5						0x222c
+#define ETH_HEADERS_RETARGET_BASE_REG			0x2230
+#define ETH_HEADERS_RETARGET_CONTROL_REG	0x2234
+#define ETH_HIGH_ADDR_REMAP_REG_0			0x2280
+#define ETH_HIGH_ADDR_REMAP_REG_1		0x2284
+#define ETH_HIGH_ADDR_REMAP_REG_2		0x2288
+#define ETH_HIGH_ADDR_REMAP_REG_3			0x228c
+#define ETH_BASE_ADDR_ENABLE_REG			0x2290
+#define ETH_ACCESS_PROTECTION_REG(port)			(0x2294 + (port<<2))
+#define ETH_MIB_COUNTERS_BASE(port)			(0x3000 + (port<<7))
+#define ETH_PORT_CONFIG_REG(port)			(0x2400 + (port<<10))
+#define ETH_PORT_CONFIG_EXTEND_REG(port)		(0x2404 + (port<<10))
+#define ETH_MII_SERIAL_PARAMETRS_REG(port)		(0x2408 + (port<<10))
+#define ETH_GMII_SERIAL_PARAMETRS_REG(port)		(0x240c + (port<<10))
+#define ETH_VLAN_ETHERTYPE_REG(port)			(0x2410 + (port<<10))
+#define ETH_MAC_ADDR_LOW(port)					(0x2414 + (port<<10))
+#define ETH_MAC_ADDR_HIGH(port)					(0x2418 + (port<<10))
+#define ETH_SDMA_CONFIG_REG(port)			(0x241c + (port<<10))
+#define ETH_DSCP_0(port)					(0x2420 + (port<<10))
+#define ETH_DSCP_1(port)					(0x2424 + (port<<10))
+#define ETH_DSCP_2(port)					(0x2428 + (port<<10))
+#define ETH_DSCP_3(port)					(0x242c + (port<<10))
+#define ETH_DSCP_4(port)					(0x2430 + (port<<10))
+#define ETH_DSCP_5(port)					(0x2434 + (port<<10))
+#define ETH_DSCP_6(port)					(0x2438 + (port<<10))
+#define ETH_PORT_SERIAL_CONTROL_REG(port)	(0x243c + (port<<10))
+#define ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		(0x2440 + (port<<10))
+#define ETH_PORT_STATUS_REG(port)				(0x2444 + (port<<10))
+#define ETH_TRANSMIT_QUEUE_COMMAND_REG(port)	(0x2448 + (port<<10))
+#define ETH_TX_QUEUE_FIXED_PRIORITY(port)		(0x244c + (port<<10))
+#define ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define ETH_MAXIMUM_TRANSMIT_UNIT(port)			(0x2458 + (port<<10))
+#define ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define ETH_INTERRUPT_CAUSE_REG(port)			(0x2460 + (port<<10))
+#define ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		(0x2464 + (port<<10))
+#define ETH_INTERRUPT_MASK_REG(port)			(0x2468 + (port<<10))
+#define ETH_INTERRUPT_EXTEND_MASK_REG(port)		(0x246c + (port<<10))
+#define ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)	(0x2470 + (port<<10))
+#define ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)	(0x2474 + (port<<10))
+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		(0x247c + (port<<10))
+#define ETH_RX_DISCARDED_FRAMES_COUNTER(port)	(0x2484 + (port<<10)
+#define ETH_PORT_DEBUG_0_REG(port)				(0x248c + (port<<10))
+#define ETH_PORT_DEBUG_1_REG(port)				(0x2490 + (port<<10))
+#define ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)	(0x2494 + (port<<10))
+#define ETH_INTERNAL_USE_REG(port)				(0x24fc + (port<<10))
+#define ETH_RECEIVE_QUEUE_COMMAND_REG(port)	(0x2680 + (port<<10))
+#define ETH_CURRENT_SERVED_TX_DESC_PTR(port)		(0x2684 + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		(0x260c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)	(0x261c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		(0x262c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		(0x263c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		(0x264c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		(0x265c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		(0x266c + (port<<10))
+#define ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		(0x267c + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)	(0x26c0 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)	(0x26c4 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)	(0x26c8 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		(0x26cc + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		(0x26d0 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		(0x26d4 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		(0x26d8 + (port<<10))
+#define ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		(0x26dc + (port<<10))
+#define ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		(0x2708 + (port<<10))
+#define ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		(0x2718 + (port<<10))
+#define ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		(0x2728 + (port<<10))
+#define ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		(0x2738 + (port<<10))
+#define ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		(0x2748 + (port<<10))
+#define ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		(0x2758 + (port<<10))
+#define ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		(0x2768 + (port<<10))
+#define ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		(0x2778 + (port<<10))
+#define ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		(0x2780 + (port<<10))
+#define ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		(0x3600 + (port<<10))
+
+
+/* Ethernet GT64260 */
+/*
+#define ETHERNET_PHY_ADDRESS_REGISTER					0x2000
+#define ETHERNET_SMI_REGISTER							0x2010
+*/
+/* Ethernet 0 */
+/*
+#define ETHERNET0_PORT_CONFIGURATION_REGISTER				0x2400
+#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER		0x2408
+#define ETHERNET0_PORT_COMMAND_REGISTER					0x2410
+#define ETHERNET0_PORT_STATUS_REGISTER					0x2418
+#define ETHERNET0_SERIAL_PARAMETRS_REGISTER				0x2420
+#define ETHERNET0_HASH_TABLE_POINTER_REGISTER				0x2428
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2430
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2438
+#define ETHERNET0_SDMA_CONFIGURATION_REGISTER			0x2440
+#define ETHERNET0_SDMA_COMMAND_REGISTER					0x2448
+#define ETHERNET0_INTERRUPT_CAUSE_REGISTER				0x2450
+#define ETHERNET0_INTERRUPT_MASK_REGISTER				0x2458
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0				0x2480
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1				0x2484
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2				0x2488
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3				0x248c
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0		0x24a0
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1		0x24a4
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2		0x24a8
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3		0x24ac
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0		0x24e0
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1		0x24e4
+#define ETHERNET0_MIB_COUNTER_BASE					0x2500
+*/
+/* Ethernet 1 */
+/*
+#define ETHERNET1_PORT_CONFIGURATION_REGISTER				0x2800
+#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER		0x2808
+#define ETHERNET1_PORT_COMMAND_REGISTER					0x2810
+#define ETHERNET1_PORT_STATUS_REGISTER					0x2818
+#define ETHERNET1_SERIAL_PARAMETRS_REGISTER				0x2820
+#define ETHERNET1_HASH_TABLE_POINTER_REGISTER				0x2828
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2830
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2838
+#define ETHERNET1_SDMA_CONFIGURATION_REGISTER			0x2840
+#define ETHERNET1_SDMA_COMMAND_REGISTER					0x2848
+#define ETHERNET1_INTERRUPT_CAUSE_REGISTER				0x2850
+#define ETHERNET1_INTERRUPT_MASK_REGISTER				0x2858
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0				0x2880
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1				0x2884
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2				0x2888
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3				0x288c
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0		0x28a0
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1		0x28a4
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2		0x28a8
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3		0x28ac
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0		0x28e0
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1		0x28e4
+#define ETHERNET1_MIB_COUNTER_BASE					0x2900
+*/
+/* Ethernet 2 */
+/*
+#define ETHERNET2_PORT_CONFIGURATION_REGISTER				0x2c00
+#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER		0x2c08
+#define ETHERNET2_PORT_COMMAND_REGISTER					0x2c10
+#define ETHERNET2_PORT_STATUS_REGISTER					0x2c18
+#define ETHERNET2_SERIAL_PARAMETRS_REGISTER				0x2c20
+#define ETHERNET2_HASH_TABLE_POINTER_REGISTER				0x2c28
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW		0x2c30
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH		0x2c38
+#define ETHERNET2_SDMA_CONFIGURATION_REGISTER			0x2c40
+#define ETHERNET2_SDMA_COMMAND_REGISTER					0x2c48
+#define ETHERNET2_INTERRUPT_CAUSE_REGISTER				0x2c50
+#define ETHERNET2_INTERRUPT_MASK_REGISTER				0x2c58
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0				0x2c80
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1				0x2c84
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2				0x2c88
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3				0x2c8c
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0		0x2ca0
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1		0x2ca4
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2		0x2ca8
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3		0x2cac
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0		0x2ce0
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1		0x2ce4
+#define ETHERNET2_MIB_COUNTER_BASE					0x2d00
+*/
+
+/****************************************/
+/* SDMA Registers			*/
+/****************************************/
+
+#define SDMA_GROUP_CONFIGURATION_REGISTER			0xb1f0
+#define CHANNEL0_CONFIGURATION_REGISTER				0x4000
+#define CHANNEL0_COMMAND_REGISTER				0x4008
+#define CHANNEL0_RX_CMD_STATUS					0x4800
+#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES		    0x4804
+#define CHANNEL0_RX_BUFFER_POINTER				0x4808
+#define CHANNEL0_RX_NEXT_POINTER				0x480c
+#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER		0x4810
+#define CHANNEL0_TX_CMD_STATUS					0x4C00
+#define CHANNEL0_TX_PACKET_SIZE					0x4C04
+#define CHANNEL0_TX_BUFFER_POINTER				0x4C08
+#define CHANNEL0_TX_NEXT_POINTER				0x4C0c
+#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER		0x4c10
+#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER			0x4c14
+/*
+#define CHANNEL1_CONFIGURATION_REGISTER				0x5000
+#define CHANNEL1_COMMAND_REGISTER				0x5008
+#define CHANNEL1_RX_CMD_STATUS					0x5800
+#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES		    0x5804
+#define CHANNEL1_RX_BUFFER_POINTER				0x5808
+#define CHANNEL1_RX_NEXT_POINTER				0x580c
+#define CHANNEL1_TX_CMD_STATUS					0x5C00
+#define CHANNEL1_TX_PACKET_SIZE					0x5C04
+#define CHANNEL1_TX_BUFFER_POINTER				0x5C08
+#define CHANNEL1_TX_NEXT_POINTER				0x5C0c
+#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER		0x5810
+#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER		0x5c10
+#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER			0x5c14
+#define CHANNEL2_CONFIGURATION_REGISTER				0x6000
+#define CHANNEL2_COMMAND_REGISTER				0x6008
+#define CHANNEL2_RX_CMD_STATUS					0x6800
+#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES		    0x6804
+#define CHANNEL2_RX_BUFFER_POINTER				0x6808
+#define CHANNEL2_RX_NEXT_POINTER				0x680c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
+#define CHANNEL2_TX_CMD_STATUS					0x6C00
+#define CHANNEL2_TX_PACKET_SIZE					0x6C04
+#define CHANNEL2_TX_BUFFER_POINTER				0x6C08
+#define CHANNEL2_TX_NEXT_POINTER				0x6C0c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
+#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER			0x6c10
+#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER			0x6c14
+*/
+/* SDMA Interrupt */
+/*
+#define SDMA_CAUSE							0xb820
+#define SDMA_MASK							0xb8a0
+*/
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define SDMA_CONFIG_REG(channel)					(0x4000 + (channel<<13))
+#define SDMA_COMMAND_REG(channel)					(0x4008 + (channel<<13))
+#define SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)		(0x4810 + (channel<<13))
+#define SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define SDMA_CAUSE_REG							0xb800
+#define SDMA_MASK_REG							0xb880
+
+/****************************************/
+/* Baude Rate Generators Registers	*/
+/****************************************/
+
+/* BRG 0 */
+#define BRG0_CONFIGURATION_REGISTER		0xb200
+#define BRG0_BAUDE_TUNING_REGISTER			 0xb204
+
+/* BRG 1 */
+#define BRG1_CONFIGURATION_REGISTER			0xb208
+#define BRG1_BAUDE_TUNING_REGISTER			 0xb20c
+
+/* BRG 2 */
+#define BRG2_CONFIGURATION_REGISTER			0xb210
+#define BRG2_BAUDE_TUNING_REGISTER			 0xb214
+
+/* BRG Interrupts */
+#define BRG_CAUSE_REGISTER					0xb834
+#define BRG_MASK_REGISTER					0xb8b4
+#define BRG_CONFIG_REG(brg)					(0xb200 + (brg<<3))
+#define BRG_BAUDE_TUNING_REG(brg)				(0xb208 + (brg<<3))
+#define BRG_CAUSE_REG						BRG_CAUSE_REGISTER  /*0xb8341 */
+#define BRG_MASK_REG						BRG_MASK_REGISTER  /*0xb8b41 */
+
+/* MISC */
+
+#define MAIN_ROUTING_REGISTER						0xb400
+#define RECEIVE_CLOCK_ROUTING_REGISTER				0xb404
+#define TRANSMIT_CLOCK_ROUTING_REGISTER				0xb408
+#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	0xb40c
+
+/****************************************/
+/*	   Watchdog registers			*/
+/****************************************/
+#define WATCHDOG_CONFIGURATION_REGISTER			0xb410
+#define WATCHDOG_VALUE_REGISTER					0xb414
+#define WATCHDOG_CONFIG_REG					WATCHDOG_CONFIGURATION_REGISTER	 /*0xb4101 */
+#define WATCHDOG_VALUE_REG						WATCHDOG_VALUE_REGISTER	 /*0xb4141 */
+
+
+/****************************************/
+/* Flex TDM Registers			*/
+/****************************************/
+
+/* FTDM Port */
+
+#define FLEXTDM_TRANSMIT_READ_POINTER			    0xa800
+#define FLEXTDM_RECEIVE_READ_POINTER			    0xa804
+#define FLEXTDM_CONFIGURATION_REGISTER			    0xa808
+#define FLEXTDM_AUX_CHANNELA_TX_REGISTER		    0xa80c
+#define FLEXTDM_AUX_CHANNELA_RX_REGISTER		    0xa810
+#define FLEXTDM_AUX_CHANNELB_TX_REGISTER		    0xa814
+#define FLEXTDM_AUX_CHANNELB_RX_REGISTER		    0xa818
+
+/* FTDM Interrupts */
+
+#define FTDM_CAUSE_REGISTER				    0xb830
+#define FTDM_MASK_REGISTER				    0xb8b0
+
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define GPP_IO_CONTROL						0xf100
+#define GPP_LEVEL_CONTROL					0xf110
+#define GPP_VALUE						0xf104
+#define GPP_INTERRUPT_CAUSE					0xf108
+#define GPP_INTERRUPT_MASK					0xf10c
+#define GPP_INTERRUPT_MASK0					GPP_INTERRUPT_MASK  /* 0xf10c1 */
+#define GPP_INTERRUPT_MASK1					0xf114
+#define GPP_VALUE_SET						0xf118
+#define GPP_VALUE_CLEAR						0xf11c
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+#define MPP_CONTROL0						0xf000
+#define MPP_CONTROL1						0xf004
+#define MPP_CONTROL2						0xf008
+#define MPP_CONTROL3						0xf00c
+#define DEBUG_PORT_MULTIPLEX					0xf014
+ /*#define SERIAL_PORT_MULTIPLEX			       0xf0101 */
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts							*/
+/****************************************/
+/****************************************/
+/* Interrupts (checked I.A. 14.10.02)				*/
+/****************************************/
+
+#define LOW_INTERRUPT_CAUSE_REGISTER			0x004  /* gt64260: 0xc181 */
+#define HIGH_INTERRUPT_CAUSE_REGISTER			0x00c  /* gt64260: 0xc681 */
+#define CPU_INTERRUPT_MASK_REGISTER_LOW		0x014  /* gt64260: 0xc1c1 */
+#define CPU_INTERRUPT_MASK_REGISTER_HIGH		0x01c  /* gt64260: 0xc6c1 */
+#define CPU_SELECT_CAUSE_REGISTER			0x024  /* gt64260: 0xc701 */
+#define CPU_INTERRUPT_1_MASK_REGISTER_LOW		0x034  /* new in the MV64360 and MV64460 */
+#define CPU_INTERRUPT_1_MASK_REGISTER_HIGH		0x03c  /* new in the MV64360 and MV64460 */
+#define CPU_SELECT_1_CAUSE_REGISTER			0x044  /* new in the MV64360 and MV64460 */
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW	0x054  /* gt64260: 0xc241 */
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x05c  /* gt64260: 0xc641 */
+#define PCI_0SELECT_CAUSE						0x064  /* gt64260: 0xc741 */
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW	0x074  /* gt64260: 0xca41 */
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0x07c  /* gt64260: 0xce41 */
+#define PCI_1SELECT_CAUSE						0x084  /* gt64260: 0xcf41 */
+/*#define CPU_INT_0_MASK						0xe60 signal is not multiplexed on MPP in the MV64360 and MV64460 */
+/*#define CPU_INT_1_MASK						0xe64 signal is not multiplexed on MPP in the MV64360 and MV64460 */
+/*#define CPU_INT_2_MASK						0xe68 signal is not multiplexed on MPP in the MV64360 and MV64460 */
+/*#define CPU_INT_3_MASK						0xe6c signal is not multiplexed on MPP in the MV64360 and MV64460 */
+
+#define MAIN_INTERRUPT_CAUSE_LOW				LOW_INTERRUPT_CAUSE_REGISTER  /* 0x0041 */
+#define MAIN_INTERRUPT_CAUSE_HIGH				HIGH_INTERRUPT_CAUSE_REGISTER  /* 0x00c1 */
+#define CPU_INTERRUPT0_MASK_LOW				CPU_INTERRUPT_MASK_REGISTER_LOW	 /* 0x0141 */
+#define CPU_INTERRUPT0_MASK_HIGH			CPU_INTERRUPT_MASK_REGISTER_HIGH  /*0x01c1 */
+#define CPU_INTERRUPT0_SELECT_CAUSE			CPU_SELECT_CAUSE_REGISTER  /* 0x0241 */
+#define CPU_INTERRUPT1_MASK_LOW				CPU_INTERRUPT_1_MASK_REGISTER_LOW  /* 0x0341 */
+#define CPU_INTERRUPT1_MASK_HIGH			CPU_INTERRUPT_1_MASK_REGISTER_HIGH  /* 0x03c1 */
+#define CPU_INTERRUPT1_SELECT_CAUSE			CPU_SELECT_1_CAUSE_REGISTER  /* 0x0441 */
+#define INTERRUPT0_MASK_0_LOW				PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW /* 0x0541 */
+#define INTERRUPT0_MASK_0_HIGH					PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH	 /* 0x05c1 */
+#define INTERRUPT0_SELECT_CAUSE				PCI_0SELECT_CAUSE  /* 0x0641 */
+#define INTERRUPT1_MASK_0_LOW					PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW	/* 0x0741 */
+#define INTERRUPT1_MASK_0_HIGH					PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH	 /* 0x07c1 */
+#define INTERRUPT1_SELECT_CAUSE				PCI_1SELECT_CAUSE  /* 0x0841 */
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define I2C_SLAVE_ADDRESS					0xc000
+#define I2C_EXTENDED_SLAVE_ADDRESS			0xc040
+#define I2C_DATA						0xc004
+#define I2C_CONTROL						0xc008
+#define I2C_STATUS_BAUDE_RATE					0xc00C
+#define I2C_SOFT_RESET						0xc01c
+#define I2C_SLAVE_ADDR						I2C_SLAVE_ADDRESS  /* 0xc0001 */
+#define I2C_EXTENDED_SLAVE_ADDR					I2C_EXTENDED_SLAVE_ADDRESS  /*0xc0101 */
+
+/****************************************/
+/* MPSC Registers			*/
+/****************************************/
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MPSC_ROUTING_REG					0xb400
+#define MPSC_RX_CLOCK_ROUTING_REG			0xb404
+#define MPSC_TX_CLOCK_ROUTING_REG			0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MPSC_CAUSE_REG(port)					(0xb804 + (port<<3))
+#define MPSC_MASK_REG(port)					(0xb884 + (port<<3))
+
+#define MPSC_MAIN_CONFIG_LOW(port)			(0x8000 + (port<<12))
+#define MPSC_MAIN_CONFIG_HIGH(port)			(0x8004 + (port<<12))
+#define MPSC_PROTOCOL_CONFIG(port)			(0x8008 + (port<<12))
+#define MPSC_CHANNEL_REG1(port)					(0x800c + (port<<12))
+#define MPSC_CHANNEL_REG2(port)					(0x8010 + (port<<12))
+#define MPSC_CHANNEL_REG3(port)					(0x8014 + (port<<12))
+#define MPSC_CHANNEL_REG4(port)					(0x8018 + (port<<12))
+#define MPSC_CHANNEL_REG5(port)					(0x801c + (port<<12))
+#define MPSC_CHANNEL_REG6(port)					(0x8020 + (port<<12))
+#define MPSC_CHANNEL_REG7(port)					(0x8024 + (port<<12))
+#define MPSC_CHANNEL_REG8(port)					(0x8028 + (port<<12))
+#define MPSC_CHANNEL_REG9(port)					(0x802c + (port<<12))
+#define MPSC_CHANNEL_REG10(port)				(0x8030 + (port<<12))
+
+
+/* MPSC0  */
+
+#define MPSC0_MAIN_CONFIGURATION_LOW			    0x8000
+#define MPSC0_MAIN_CONFIGURATION_HIGH			    0x8004
+#define MPSC0_PROTOCOL_CONFIGURATION			    0x8008
+#define CHANNEL0_REGISTER1				    0x800c
+#define CHANNEL0_REGISTER2				    0x8010
+#define CHANNEL0_REGISTER3				    0x8014
+#define CHANNEL0_REGISTER4				    0x8018
+#define CHANNEL0_REGISTER5				    0x801c
+#define CHANNEL0_REGISTER6				    0x8020
+#define CHANNEL0_REGISTER7				    0x8024
+#define CHANNEL0_REGISTER8				    0x8028
+#define CHANNEL0_REGISTER9				    0x802c
+#define CHANNEL0_REGISTER10				    0x8030
+#define CHANNEL0_REGISTER11				    0x8034
+
+/* MPSC1  */
+
+#define MPSC1_MAIN_CONFIGURATION_LOW			    0x8840
+#define MPSC1_MAIN_CONFIGURATION_HIGH			    0x8844
+#define MPSC1_PROTOCOL_CONFIGURATION			    0x8848
+#define CHANNEL1_REGISTER1				    0x884c
+#define CHANNEL1_REGISTER2				    0x8850
+#define CHANNEL1_REGISTER3				    0x8854
+#define CHANNEL1_REGISTER4				    0x8858
+#define CHANNEL1_REGISTER5				    0x885c
+#define CHANNEL1_REGISTER6				    0x8860
+#define CHANNEL1_REGISTER7				    0x8864
+#define CHANNEL1_REGISTER8				    0x8868
+#define CHANNEL1_REGISTER9				    0x886c
+#define CHANNEL1_REGISTER10				    0x8870
+#define CHANNEL1_REGISTER11				    0x8874
+
+/* MPSC2  */
+
+#define MPSC2_MAIN_CONFIGURATION_LOW			    0x9040
+#define MPSC2_MAIN_CONFIGURATION_HIGH			    0x9044
+#define MPSC2_PROTOCOL_CONFIGURATION			    0x9048
+#define CHANNEL2_REGISTER1				    0x904c
+#define CHANNEL2_REGISTER2				    0x9050
+#define CHANNEL2_REGISTER3				    0x9054
+#define CHANNEL2_REGISTER4				    0x9058
+#define CHANNEL2_REGISTER5				    0x905c
+#define CHANNEL2_REGISTER6				    0x9060
+#define CHANNEL2_REGISTER7				    0x9064
+#define CHANNEL2_REGISTER8				    0x9068
+#define CHANNEL2_REGISTER9				    0x906c
+#define CHANNEL2_REGISTER10				    0x9070
+#define CHANNEL2_REGISTER11				    0x9074
+
+/* MPSCs Interupts  */
+
+#define MPSC0_CAUSE						0xb824
+#define MPSC0_MASK						0xb8a4
+#define MPSC1_CAUSE						0xb828
+#define MPSC1_MASK						0xb8a8
+#define MPSC2_CAUSE						0xb82c
+#define MPSC2_MASK						 0xb8ac
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define CUNIT_BASE_ADDR_REG0					0xf200
+#define CUNIT_BASE_ADDR_REG1					0xf208
+#define CUNIT_BASE_ADDR_REG2					0xf210
+#define CUNIT_BASE_ADDR_REG3					0xf218
+#define CUNIT_SIZE0						0xf204
+#define CUNIT_SIZE1						0xf20c
+#define CUNIT_SIZE2						0xf214
+#define CUNIT_SIZE3						0xf21c
+#define CUNIT_HIGH_ADDR_REMAP_REG0			0xf240
+#define CUNIT_HIGH_ADDR_REMAP_REG1			0xf244
+#define CUNIT_BASE_ADDR_ENABLE_REG			0xf250
+#define MPSC0_ACCESS_PROTECTION_REG			0xf254
+#define MPSC1_ACCESS_PROTECTION_REG			0xf258
+#define CUNIT_INTERNAL_SPACE_BASE_ADDR_REG	0xf25C
+
+	/*  Error Report Registers  */
+
+#define CUNIT_INTERRUPT_CAUSE_REG			0xf310
+#define CUNIT_INTERRUPT_MASK_REG			0xf314
+#define CUNIT_ERROR_ADDR					0xf318
+
+	/*  Cunit Control Registers */
+
+#define CUNIT_ARBITER_CONTROL_REG			0xf300
+#define CUNIT_CONFIG_REG					0xb40c
+#define CUNIT_CRROSBAR_TIMEOUT_REG			0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define CUNIT_DEBUG_LOW						0xf340
+#define CUNIT_DEBUG_HIGH					0xf344
+#define CUNIT_MMASK						0xf380
+
+#endif /* __INCmv_gen_regh */
diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h
new file mode 100755
index 0000000..167248d
--- /dev/null
+++ b/board/Marvell/include/pci.h
@@ -0,0 +1,293 @@
+/* PCI.h - PCI functions header file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCpcih
+#define __INCpcih
+
+/* includes */
+
+#include"core.h"
+#include"memory.h"
+
+/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
+#define PCI_MAX_DEVICES 22
+
+
+/* Macros */
+
+/* The next Macros configurate the initiator board (SELF) or any any agent on
+   the PCI to become: MASTER, response to MEMORY transactions , response to
+   IO transactions or TWO both MEMORY_IO transactions. Those configuration
+   are for both PCI0 and PCI1. */
+
+#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |		     \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |		     \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host,		       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &		     \
+	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
+
+#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host,	       \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |		     \
+	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host,	      \
+	  PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &		     \
+	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
+
+#define		MASTER_ENABLE			BIT2
+#define		MEMORY_ENABLE			BIT1
+#define		I_O_ENABLE			BIT0
+#define	    SELF		    32
+
+/* Agent on the PCI bus may have up to 6 BARS. */
+#define	    BAR0		    0x10
+#define	    BAR1		    0x14
+#define	    BAR2		    0x18
+#define	    BAR3		    0x1c
+#define	    BAR4		    0x20
+#define	    BAR5		    0x24
+#define		BAR_SEL_MEM_IO			BIT0
+#define		BAR_MEM_TYPE_32_BIT		NO_BIT
+#define		BAR_MEM_TYPE_BELOW_1M		       BIT1
+#define		BAR_MEM_TYPE_64_BIT			      BIT2
+#define		BAR_MEM_TYPE_RESERVED		      (BIT1 | BIT2)
+#define		BAR_MEM_TYPE_MASK		      (BIT1 | BIT2)
+#define		BAR_PREFETCHABLE				      BIT3
+#define		BAR_CONFIG_MASK			(BIT0 | BIT1 | BIT2 | BIT3)
+
+/* Defines for the access regions. */
+#define	    PREFETCH_ENABLE		    BIT12
+#define	    PREFETCH_DISABLE		    NO_BIT
+#define	    DELAYED_READ_ENABLE		    BIT13
+/* #define     CACHING_ENABLE		       BIT14 */
+/* aggressive prefetch: PCI slave prefetch two burst in advance*/
+#define	    AGGRESSIVE_PREFETCH		     BIT16
+/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define	    READ_LINE_AGGRESSIVE_PREFETCH   BIT17
+/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define	    READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
+#define	    MAX_BURST_4			    NO_BIT
+#define	    MAX_BURST_8			    BIT20  /* Bits[21:20] = 01 */
+#define	    MAX_BURST_16		    BIT21  /* Bits[21:20] = 10 */
+#define	    PCI_BYTE_SWAP		    NO_BIT /* Bits[25:24] = 00 */
+#define	    PCI_NO_SWAP			    BIT24  /* Bits[25:24] = 01 */
+#define	    PCI_BYTE_AND_WORD_SWAP	    BIT25  /* Bits[25:24] = 10 */
+#define	    PCI_WORD_SWAP		   (BIT24 | BIT25) /* Bits[25:24] = 11 */
+#define	    PCI_ACCESS_PROTECT		    BIT28
+#define	    PCI_WRITE_PROTECT		    BIT29
+
+/* typedefs */
+
+typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
+				REGION6,REGION7} PCI_ACCESS_REGIONS;
+
+typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
+typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
+
+typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
+			    PCI_SNOOP_TYPE;
+typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
+			      PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
+			      PCI_SNOOP_REGION;
+
+typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
+typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
+			 PCI_REGION2,PCI_REGION3,
+			 PCI_IO}
+			 PCI_REGION;
+
+/*ronen 7/Dec/03 */
+typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
+			       PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
+			       PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
+			       PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
+			       PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
+			       PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
+			       PCI_LAST_BAR} PCI_INTERNAL_BAR;
+
+typedef struct pciBar {
+    unsigned int detectBase;
+    unsigned int base;
+    unsigned int size;
+    unsigned int type;
+} PCI_BAR;
+
+typedef struct pciDevice {
+    PCI_HOST	     host;
+    char	    type[40];
+    unsigned int    deviceNum;
+    unsigned int    venID;
+    unsigned int    deviceID;
+    PCI_BAR bar[6];
+} PCI_DEVICE;
+
+typedef struct pciSelfBars {
+    unsigned int    SCS0Base;
+    unsigned int    SCS0Size;
+    unsigned int    SCS1Base;
+    unsigned int    SCS1Size;
+    unsigned int    SCS2Base;
+    unsigned int    SCS2Size;
+    unsigned int    SCS3Base;
+    unsigned int    SCS3Size;
+    unsigned int    internalMemBase;
+    unsigned int    internalIOBase;
+    unsigned int    CS0Base;
+    unsigned int    CS0Size;
+    unsigned int    CS1Base;
+    unsigned int    CS1Size;
+    unsigned int    CS2Base;
+    unsigned int    CS2Size;
+    unsigned int    CS3Base;
+    unsigned int    CS3Size;
+    unsigned int    CSBootBase;
+    unsigned int    CSBootSize;
+    unsigned int    P2PMem0Base;
+    unsigned int    P2PMem0Size;
+    unsigned int    P2PMem1Base;
+    unsigned int    P2PMem1Size;
+    unsigned int    P2PIOBase;
+    unsigned int    P2PIOSize;
+    unsigned int    CPUBase;
+    unsigned int    CPUSize;
+} PCI_SELF_BARS;
+
+/* read/write configuration registers on local PCI bus. */
+void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
+		       unsigned int pciDevNum, unsigned int data);
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum);
+
+/* read/write configuration registers on another PCI bus. */
+void pciOverBridgeWriteConfigReg(PCI_HOST host,
+				 unsigned int regOffset,
+				 unsigned int pciDevNum,
+				 unsigned int busNum,unsigned int data);
+unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
+					unsigned int regOffset,
+					unsigned int pciDevNum,
+					unsigned int busNum);
+
+/* Performs full scane on both PCI and returns all detail possible on the
+   agents which exist on the bus. */
+void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
+		    unsigned int numberOfElment);
+
+/*	Master`s memory space	*/
+bool pciMapSpace(PCI_HOST host, PCI_REGION region,
+		unsigned int remapBase,
+		unsigned int deviceBase,
+		unsigned int deviceLength);
+unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
+unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
+
+/*	Slave`s memory space   */
+void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
+		      unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
+
+#if 0 /* GARBAGE routines - dont use till they get cleaned up */
+void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
+void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
+void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
+void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
+void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
+void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
+void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
+			       unsigned int pci0Dev0Length);
+void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
+			       unsigned int pci1Dev0Length);
+void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
+			       unsigned int pci0Dev1Length);
+void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
+			       unsigned int pci1Dev1Length);
+void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
+			       unsigned int pci0Dev2Length);
+void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
+			       unsigned int pci1Dev2Length);
+void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
+			       unsigned int pci0Dev3Length);
+void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
+			       unsigned int pci1Dev3Length);
+void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
+				  unsigned int pci0DevBootLength);
+void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
+				  unsigned int pci1DevBootLength);
+void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
+			 unsigned int pci0P2pMem0Length);
+void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
+			 unsigned int pci1P2pMem0Length);
+void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
+			 unsigned int pci0P2pMem1Length);
+void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
+			 unsigned int pci1P2pMem1Length);
+void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
+		       unsigned int pci0P2pIoLength);
+void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
+		       unsigned int pci1P2pIoLength);
+
+void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
+void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
+#endif
+
+/* PCI region options */
+
+bool  pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
+	unsigned int features, unsigned int baseAddress,
+	unsigned int regionLength);
+
+void  pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
+
+/* PCI arbiter */
+
+bool pciArbiterEnable(PCI_HOST host);
+bool pciArbiterDisable(PCI_HOST host);
+bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5);
+bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5);
+bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5);
+bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
+bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
+
+/* PCI-to-PCI (P2P) */
+
+bool pciP2PConfig(PCI_HOST host,
+		  unsigned int SecondBusLow,unsigned int SecondBusHigh,
+		  unsigned int busNum,unsigned int devNum);
+/* PCI Cache-coherency */
+
+bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength);
+
+PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
+
+#endif /* __INCpcih */
diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile
new file mode 100755
index 0000000..93907ba
--- /dev/null
+++ b/board/RPXClassic/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o eccx.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c
new file mode 100755
index 0000000..49cb8ad
--- /dev/null
+++ b/board/RPXClassic/RPXClassic.c
@@ -0,0 +1,265 @@
+/*
+ * (C)	Copyright 2001
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ * U-Boot port on RPXClassic LF (CLLF_BW31) board
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+static unsigned char aschex_to_byte (unsigned char *cp);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
+	0x3FBFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
+	0x3FBFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
+	0x3FFFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
+	0x0CFFCC00, 0x33FFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
+	0x3FFFCC27, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXClassic\n");
+	return (0);
+}
+
+/*-----------------------------------------------------------------------------
+ * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
+ *-----------------------------------------------------------------------------
+ */
+void board_get_enetaddr (uchar * enet)
+{
+	int i;
+	char buff[256], *cp;
+
+	/* Initialize I2C					*/
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/* Read 256 bytes in EEPROM				*/
+	i2c_read (0x54, 0, 1, (uchar *)buff, 128);
+	i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
+
+	/* Retrieve MAC address in buffer (key EA)		*/
+	for (cp = buff;;) {
+		if (cp[0] == 'E' && cp[1] == 'A') {
+			cp += 3;
+			/* Read MAC address			*/
+			for (i = 0; i < 6; i++, cp += 2) {
+				enet[i] = aschex_to_byte ((unsigned char *)cp);
+			}
+		}
+		/* Scan to the end of the record		*/
+		while ((*cp != '\n') && (*cp != (char)0xff)) {
+			cp++;
+		}
+		/* If the next character is a \n, 0 or ff, we are done.	*/
+		cp++;
+		if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
+			break;
+	}
+
+#ifdef CONFIG_FEC_ENET
+	/* The MAC address is the same as normal ethernet except the 3rd byte	 */
+	/* (See the E.P. Planet Core Overview manual		*/
+	enet[3] |= 0x80;
+#endif
+
+	printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
+		enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
+
+}
+
+void rpxclassic_init (void)
+{
+	/* Enable NVRAM */
+	*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
+
+#ifdef CONFIG_FEC_ENET
+
+	/* Validate the fast ethernet tranceiver                             */
+	*((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
+	*((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
+	*((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
+	*((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
+#endif
+
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size10;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000000;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - refresh twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size
+	 * try 10 column mode
+	 */
+
+	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
+						SDRAM_MAX_SIZE);
+
+	return (size10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+/*-----------------------------------------------------------------------------
+ * aschex_to_byte --
+ *-----------------------------------------------------------------------------
+ */
+static unsigned char aschex_to_byte (unsigned char *cp)
+{
+	u_char byte, c;
+
+	c = *cp++;
+
+	if ((c >= 'A') && (c <= 'F')) {
+		c -= 'A';
+		c += 10;
+	} else if ((c >= 'a') && (c <= 'f')) {
+		c -= 'a';
+		c += 10;
+	} else {
+		c -= '0';
+	}
+
+	byte = c * 16;
+
+	c = *cp;
+
+	if ((c >= 'A') && (c <= 'F')) {
+		c -= 'A';
+		c += 10;
+	} else if ((c >= 'a') && (c <= 'f')) {
+		c -= 'a';
+		c += 10;
+	} else {
+		c -= '0';
+	}
+
+	byte += c;
+
+	return (byte);
+}
diff --git a/board/RPXClassic/config.mk b/board/RPXClassic/config.mk
new file mode 100755
index 0000000..ae455e1
--- /dev/null
+++ b/board/RPXClassic/config.mk
@@ -0,0 +1,29 @@
+#
+# (C)  Copyright 2001
+# Stäubli Faverges - <www.staubli.com>
+# Pierre AUBERT  p.aubert@staubli.com
+# U-Boot port on RPXClassic LF (CLLF_BW31) board
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xff000000
diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c
new file mode 100755
index 0000000..cc76bbd
--- /dev/null
+++ b/board/RPXClassic/eccx.c
@@ -0,0 +1,351 @@
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Video support for the ECCX daughter board                                 */
+
+
+#include <common.h>
+#include <config.h>
+
+#ifdef CONFIG_VIDEO_SED13806
+#include <sed13806.h>
+
+
+/* Screen configurations: the initialization of the SD13806 depends on
+   screen and on display mode. We handle only 8bpp and 16 bpp modes          */
+
+/* ECCX board is supplied with a NEC NL6448BC20 screen                       */
+#ifdef CONFIG_NEC_NL6448BC20
+#define DISPLAY_WIDTH   640
+#define DISPLAY_HEIGHT  480
+
+#ifdef CONFIG_VIDEO_SED13806_8BPP
+static const S1D_REGS init_regs [] =
+{
+    {0x0001,0x00},   /* Miscellaneous Register */
+    {0x01FC,0x00},   /* Display Mode Register */
+    {0x0004,0x1b},   /* General IO Pins Configuration Register 0 */
+    {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+    {0x0008,0xe5},   /* General IO Pins Control Register 0 */
+    {0x0009,0x1f},   /* General IO Pins Control Register 1 */
+    {0x0010,0x02},   /* Memory Clock Configuration Register */
+    {0x0014,0x10},   /* LCD Pixel Clock Configuration Register */
+    {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+    {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+    {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+    {0x0021,0x04},   /* DRAM Refresh Rate Register */
+    {0x002A,0x00},   /* DRAM Timings Control Register 0 */
+    {0x002B,0x01},   /* DRAM Timings Control Register 1 */
+    {0x0020,0x80},   /* Memory Configuration Register */
+    {0x0030,0x25},   /* Panel Type Register */
+    {0x0031,0x00},   /* MOD Rate Register */
+    {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+    {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+    {0x0035,0x01},   /* TFT FPLINE Start Position Register */
+    {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+    {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+    {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+    {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+    {0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+    {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+    {0x0040,0x03},   /* LCD Display Mode Register */
+    {0x0041,0x02},   /* LCD Miscellaneous Register */
+    {0x0042,0x00},   /* LCD Display Start Address Register 0 */
+    {0x0043,0x00},   /* LCD Display Start Address Register 1 */
+    {0x0044,0x00},   /* LCD Display Start Address Register 2 */
+    {0x0046,0x40},   /* LCD Memory Address Offset Register 0 */
+    {0x0047,0x01},   /* LCD Memory Address Offset Register 1 */
+    {0x0048,0x00},   /* LCD Pixel Panning Register */
+    {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+    {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+    {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+    {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+    {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+    {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+    {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+    {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+    {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+    {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+    {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+    {0x005B,0x00},   /* TV Output Control Register */
+    {0x0060,0x03},   /* CRT/TV Display Mode Register */
+    {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+    {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+    {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+    {0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+    {0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+    {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+    {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+    {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+    {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+    {0x0071,0x00},   /* LCD Ink/Cursor Start Address Register */
+    {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+    {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+    {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+    {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+    {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+    {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+    {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+    {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+    {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+    {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+    {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+    {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+    {0x0081,0x00},   /* CRT/TV Ink/Cursor Start Address Register */
+    {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+    {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+    {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+    {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+    {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+    {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+    {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+    {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+    {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+    {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+    {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+    {0x0100,0x00},   /* BitBlt Control Register 0 */
+    {0x0101,0x00},   /* BitBlt Control Register 1 */
+    {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+    {0x0103,0x00},   /* BitBlt Operation Register */
+    {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+    {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+    {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+    {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+    {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+    {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+    {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+    {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+    {0x0110,0x00},   /* BitBlt Width Register 0 */
+    {0x0111,0x00},   /* BitBlt Width Register 1 */
+    {0x0112,0x00},   /* BitBlt Height Register 0 */
+    {0x0113,0x00},   /* BitBlt Height Register 1 */
+    {0x0114,0x00},   /* BitBlt Background Color Register 0 */
+    {0x0115,0x00},   /* BitBlt Background Color Register 1 */
+    {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+    {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+    {0x01E0,0x00},   /* Look-Up Table Mode Register */
+    {0x01E2,0x00},   /* Look-Up Table Address Register */
+    {0x01E4,0x00},   /* Look-Up Table Data Register */
+    {0x01F0,0x10},   /* Power Save Configuration Register */
+    {0x01F1,0x00},   /* Power Save Status Register */
+    {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+    {0x01FC,0x01},   /* Display Mode Register */
+    {0, 0}
+};
+#endif /* CONFIG_VIDEO_SED13806_8BPP */
+
+#ifdef CONFIG_VIDEO_SED13806_16BPP
+
+static const S1D_REGS init_regs [] =
+{
+    {0x0001,0x00},   /* Miscellaneous Register */
+    {0x01FC,0x00},   /* Display Mode Register */
+    {0x0004,0x1b},   /* General IO Pins Configuration Register 0 */
+    {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+    {0x0008,0xe5},   /* General IO Pins Control Register 0 */
+    {0x0009,0x1f},   /* General IO Pins Control Register 1 */
+    {0x0010,0x02},   /* Memory Clock Configuration Register */
+    {0x0014,0x10},   /* LCD Pixel Clock Configuration Register */
+    {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+    {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+    {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+    {0x0021,0x04},   /* DRAM Refresh Rate Register */
+    {0x002A,0x00},   /* DRAM Timings Control Register 0 */
+    {0x002B,0x01},   /* DRAM Timings Control Register 1 */
+    {0x0020,0x80},   /* Memory Configuration Register */
+    {0x0030,0x25},   /* Panel Type Register */
+    {0x0031,0x00},   /* MOD Rate Register */
+    {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+    {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+    {0x0035,0x01},   /* TFT FPLINE Start Position Register */
+    {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+    {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+    {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+    {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+    {0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+    {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+    {0x0040,0x05},   /* LCD Display Mode Register */
+    {0x0041,0x02},   /* LCD Miscellaneous Register */
+    {0x0042,0x00},   /* LCD Display Start Address Register 0 */
+    {0x0043,0x00},   /* LCD Display Start Address Register 1 */
+    {0x0044,0x00},   /* LCD Display Start Address Register 2 */
+    {0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+    {0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+    {0x0048,0x00},   /* LCD Pixel Panning Register */
+    {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+    {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+    {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+    {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+    {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+    {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+    {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+    {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+    {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+    {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+    {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+    {0x005B,0x00},   /* TV Output Control Register */
+    {0x0060,0x05},   /* CRT/TV Display Mode Register */
+    {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+    {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+    {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+    {0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+    {0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+    {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+    {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+    {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+    {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+    {0x0071,0x00},   /* LCD Ink/Cursor Start Address Register */
+    {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+    {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+    {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+    {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+    {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+    {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+    {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+    {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+    {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+    {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+    {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+    {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+    {0x0081,0x00},   /* CRT/TV Ink/Cursor Start Address Register */
+    {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+    {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+    {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+    {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+    {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+    {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+    {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+    {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+    {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+    {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+    {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+    {0x0100,0x00},   /* BitBlt Control Register 0 */
+    {0x0101,0x00},   /* BitBlt Control Register 1 */
+    {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+    {0x0103,0x00},   /* BitBlt Operation Register */
+    {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+    {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+    {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+    {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+    {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+    {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+    {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+    {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+    {0x0110,0x00},   /* BitBlt Width Register 0 */
+    {0x0111,0x00},   /* BitBlt Width Register 1 */
+    {0x0112,0x00},   /* BitBlt Height Register 0 */
+    {0x0113,0x00},   /* BitBlt Height Register 1 */
+    {0x0114,0x00},   /* BitBlt Background Color Register 0 */
+    {0x0115,0x00},   /* BitBlt Background Color Register 1 */
+    {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+    {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+    {0x01E0,0x01},   /* Look-Up Table Mode Register */
+    {0x01E2,0x00},   /* Look-Up Table Address Register */
+    {0x01E4,0x00},   /* Look-Up Table Data Register */
+    {0x01F0,0x10},   /* Power Save Configuration Register */
+    {0x01F1,0x00},   /* Power Save Status Register */
+    {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+    {0x01FC,0x01},   /* Display Mode Register */
+    {0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SED13806_16BPP */
+#endif /* CONFIG_NEC_NL6448BC20 */
+
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+
+/*-----------------------------------------------------------------------------
+ * video_get_info_str -- setup a board string: type, speed, etc.
+ * line_number= location to place info string beside logo
+ * info= buffer for info string
+ *-----------------------------------------------------------------------------
+ */
+void video_get_info_str (int line_number, char *info)
+{
+    if (line_number == 1) {
+	strcpy (info, " RPXClassic board");
+    }
+    else {
+	info [0] = '\0';
+    }
+
+}
+#endif
+
+/*-----------------------------------------------------------------------------
+ * board_video_init -- init de l'EPSON, config du CS
+ *-----------------------------------------------------------------------------
+ */
+unsigned int board_video_init (void)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+    /* Program ECCX registers                                                */
+    *(ECCX_CSR12) |= ECCX_860;
+    *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
+    *(ECCX_CSR8) |= ECCX_ENEPSON;
+
+    memctl->memc_or2 = SED13806_OR;
+    memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;
+
+    return (SED13806_REG_ADDR);
+}
+
+/*-----------------------------------------------------------------------------
+ * board_validate_screen --
+ *-----------------------------------------------------------------------------
+ */
+void board_validate_screen (unsigned int base)
+{
+    /* Activate the panel bias power                                         */
+    *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
+}
+/*-----------------------------------------------------------------------------
+ * board_get_regs --
+ *-----------------------------------------------------------------------------
+ */
+const S1D_REGS *board_get_regs (void)
+{
+    return (init_regs);
+}
+/*-----------------------------------------------------------------------------
+ * board_get_width --
+ *-----------------------------------------------------------------------------
+ */
+int board_get_width (void)
+{
+    return (DISPLAY_WIDTH);
+}
+
+/*-----------------------------------------------------------------------------
+ * board_get_height --
+ *-----------------------------------------------------------------------------
+ */
+int board_get_height (void)
+{
+    return (DISPLAY_HEIGHT);
+}
+
+#endif /* CONFIG_VIDEO_SED13806 */
diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c
new file mode 100755
index 0000000..2e0b8f9
--- /dev/null
+++ b/board/RPXClassic/flash.c
@@ -0,0 +1,447 @@
+/*
+ * (C)  Copyright 2001
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ * U-Boot port on RPXClassic LF (CLLF_BW31) board
+ *
+ * RPXClassic uses Am29DL323B flash memory with 2 banks
+ *
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000) ;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDL323B:
+	    printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n");
+	    break;
+	default:
+	    printf ("Unknown Chip Type\n");
+	    break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Reset flash componeny                                             */
+	addr [0] = 0xf0f0f0f0;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0xAAAAAAAA ;
+	addr[0x555] = 0x55555555 ;
+	addr[0xAAA] = 0x90909090 ;
+
+	value = addr[0] ;
+
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;		/* device ID		*/
+
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_DL323B & 0x00FF00FF):
+	    info->flash_id += FLASH_AMDL323B;
+	    info->sector_count = 71;
+	    info->size = 0x01000000;            /* 16 Mb                     */
+
+	    break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+	/* set sector offsets for bottom boot block type	*/
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00008000;
+	info->start[2] = base + 0x00010000;
+	info->start[3] = base + 0x00018000;
+	info->start[4] = base + 0x00020000;
+	info->start[5] = base + 0x00028000;
+	info->start[6] = base + 0x00030000;
+	info->start[7] = base + 0x00038000;
+	for (i = 8; i < info->sector_count; i++) {
+	    info->start[i] = base + ((i-7) * 0x00040000) ;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < 23; i++) {
+	    /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	    /* D0 = 1 if protected */
+	    addr = (volatile unsigned long *)(info->start[i]);
+	    info->protect[i] = addr[4] & 1 ;
+	}
+	/* Check for protected sectors in the 2nd bank                       */
+	addr[0x100AAA] = 0xAAAAAAAA ;
+	addr[0x100555] = 0x55555555 ;
+	addr[0x100AAA] = 0x90909090 ;
+
+	for (i = 23; i < info->sector_count; i++) {
+	    /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	    /* D0 = 1 if protected */
+	    addr = (volatile unsigned long *)(info->start[i]);
+	    info->protect[i] = addr[4] & 1 ;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank 1                      */
+		addr = (volatile unsigned long *)info->start[23];
+
+		*addr = 0xF0F0F0F0;	/* reset bank 2                      */
+
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds
new file mode 100755
index 0000000..049f990
--- /dev/null
+++ b/board/RPXClassic/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+/* XXX ?
+    . = env_offset;
+*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug
new file mode 100755
index 0000000..ddd4678
--- /dev/null
+++ b/board/RPXClassic/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/RPXlite/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c
new file mode 100755
index 0000000..f37e07b
--- /dev/null
+++ b/board/RPXlite/RPXlite.c
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * DRAM related UPMA register values are modified.
+ * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
+	0x3FBFCC27,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
+	0x3FBFCC27,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
+	0x3FFFCC27,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
+	0x0CFFCC00, 0x33FFCC27,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
+	0x3FFFCC27,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXlite\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size10;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000000;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - refresh twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size
+	 * try 10 column mode
+	 */
+
+	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
+			    SDRAM_MAX_SIZE);
+
+	return (size10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
diff --git a/board/RPXlite/config.mk b/board/RPXlite/config.mk
new file mode 100755
index 0000000..6536b77
--- /dev/null
+++ b/board/RPXlite/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RPXlite boards
+#
+
+TEXT_BASE = 0xfff00000
diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c
new file mode 100755
index 0000000..846794d
--- /dev/null
+++ b/board/RPXlite/flash.c
@@ -0,0 +1,524 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * Some of flash control words are modified. (from 2x16bit device
+ * to 4x8bit device)
+ * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
+ * are not tested.
+ *
+ * (?) Does an RPXLite board which
+ * 	does not use AM29LV800 flash memory exist ?
+ *	I don't know...
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+/*	volatile immap_t     *immap  = (immap_t *)CFG_IMMR; */
+/*	volatile memctl8xx_t *memctl = &immap->im_memctl; */
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+/*
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE_DEBUG, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+*/
+	/* Remap FLASH according to real size */
+/*%%%
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+%%%*/
+	/* Re-do sizing to get full correct info */
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00010000;
+		info->start[2] = base + 0x00018000;
+		info->start[3] = base + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0x00AA00AA ;
+	addr[0x555] = 0x00550055 ;
+	addr[0xAAA] = 0x00900090 ;
+
+	value = addr[0] ;
+
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;		/* device ID		*/
+
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_LV400T & 0x00FF00FF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & 0x00FF00FF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & 0x00FF00FF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & 0x00FF00FF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/*%%% Size doubled by yooth */
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160T & 0x00FF00FF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & 0x00FF00FF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/*%%% sector start address modified */
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00010000;
+		info->start[2] = base + 0x00018000;
+		info->start[3] = base + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[4] & 1 ;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds
new file mode 100755
index 0000000..049f990
--- /dev/null
+++ b/board/RPXlite/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+/* XXX ?
+    . = env_offset;
+*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug
new file mode 100755
index 0000000..ddd4678
--- /dev/null
+++ b/board/RPXlite/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/RPXlite_dw/Makefile b/board/RPXlite_dw/Makefile
new file mode 100755
index 0000000..d457020
--- /dev/null
+++ b/board/RPXlite_dw/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/RPXlite_dw/README b/board/RPXlite_dw/README
new file mode 100755
index 0000000..28bcb31
--- /dev/null
+++ b/board/RPXlite_dw/README
@@ -0,0 +1,161 @@
+
+After following the step of Yoo. Jonghoon and Wolfgang Denk,
+I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW.
+
+There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW.
+
+Board(in U-Boot)	version(in EmbeddedPlanet)	CPU	SDRAM	FLASH
+RPXlite				RPXlite CW		850	16MB	4MB
+RPXlite_DW		RPXlite DW(EP 823 H1 DW)	823e	64MB	16MB
+
+This fireware is specially coded for EmbeddedPlanet Co. Software Development
+Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel.
+
+It has the following three features:
+
+1. 64MHz/48MHz system frequence setting options.
+The default setting is 48MHz.To get a 64MHz u-boot,just add
+'64' in make command,like
+
+make distclean
+make RPXlite_DW_64_config
+make all
+
+2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM
+
+The default environment parameter is stored in FLASH because it is a common choice for
+environment parameter.So I make NVRAM as backup parameter storeage.The reason why I
+didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter
+home.Because of the possibility of using two firewares on this board,I didn't
+'disturb' EEPROM.To get NVRAM support,you may use the following build command:
+
+make distclean
+make RPXlite_DW_NVRAM_config
+make all
+
+3. LCD panel support
+
+To support the Platform better,I added LCD panel(NL6448BC20-08) function.
+For the convenience of debug, CONFIG_PERBOOT was supported. So you just
+perss ENTER if you want to get a serial console in boot downcounting.
+Then you can switch to LCD and serial console freely just typing
+'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled.
+
+To get a LCD support u-boot,you can do the following:
+
+make distclean
+make RPXlite_DW_LCD_config
+make all
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The basic make commands could be:
+
+make RPXlite_DW_config
+make RPXlite_DW_64_config
+make RPXlite_DW_LCD_config
+make RPXlite_DW_NVRAM_config
+
+BTW,you can combine the above features together and get a workable u-boot to meet your need.
+For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type:
+
+make RPXlite_DW_NVRAM_64_LCD_config
+make all
+
+So other combining make commands could be:
+
+make RPXlite_DW_NVRAM_64_config
+make RPXlite_DW_NVRAM_LCD_config
+make RPXlite_DW_64_LCD_config
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The boot process by "make RPXlite_DW_config" could be:
+
+U-Boot 1.1.2 (Aug 29 2004 - 15:11:27)
+
+CPU:   PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache
+Board: RPXlite_DW
+DRAM:  64 MB
+FLASH: 16 MB
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+u-boot>
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+A word on the U-Boot enviroment variable setting and usage :
+
+In the beginning, you could just need very simple defult environment variable setting,
+like[include/configs/RPXlite.h] :
+
+#define CONFIG_BOOTCOMMAND                                                      \
+	"bootp; "                                                               \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
+	"bootm"
+
+This is enough for kernel NFS test. But as debug process goes on, you would expect
+to save some time on environment variable setting and u-boot/kernel updating.
+So the default environment variable setting would become more complicated. Just like
+the one I did in include/configs/RPXlite_DW.h.
+
+Two u-boot commands, ku and uu, should be careful to use. They were designed to update
+kernel and u-boot image file respectively. You must tftp your image to default address
+'100000' and then use them correctly. Yeah, you can create your own command to do this
+job. :-) The example u-boot image updating process could be :
+
+u-boot>t 100000 RPXlite_DW_LCD.bin
+Using SCC ETHERNET device
+TFTP from server 172.16.115.6; our IP address is 172.16.115.7
+Filename 'RPXlite_DW_LCD.bin'.
+Load address: 0x100000
+Loading: #############################
+done
+Bytes transferred = 144700 (2353c hex)
+u-boot>run uu
+Un-Protect Flash Sectors 0-4 in Bank # 1
+Erase Flash Sectors 0-4 in Bank # 1
+.... done
+Copy to Flash... done
+ff000000: 27051956 552d426f 6f742031 2e312e32    '..VU-Boot 1.1.2
+ff000010: 20284175 67203239 20323030 34202d20     (Aug 29 2004 -
+ff000020: 31353a32 303a3238 29000000 00000000    15:20:28).......
+ff000030: 00000000 00000000 00000000 00000000    ................
+ff000040: 00000000 00000000 00000000 00000000    ................
+ff000050: 00000000 00000000 00000000 00000000    ................
+ff000060: 00000000 00000000 00000000 00000000    ................
+ff000070: 00000000 00000000 00000000 00000000    ................
+ff000080: 00000000 00000000 00000000 00000000    ................
+ff000090: 00000000 00000000 00000000 00000000    ................
+ff0000a0: 00000000 00000000 00000000 00000000    ................
+ff0000b0: 00000000 00000000 00000000 00000000    ................
+ff0000c0: 00000000 00000000 00000000 00000000    ................
+ff0000d0: 00000000 00000000 00000000 00000000    ................
+ff0000e0: 00000000 00000000 00000000 00000000    ................
+ff0000f0: 00000000 00000000 00000000 00000000    ................
+u-boot updating finished
+u-boot>
+
+Also for environment updating, 'run eu' could let you erase OLD default environment variable
+and then use the working u-boot environment setting.
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Finally, if you want to keep the serial port to possible debug on spot for deployment, you
+just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string
+defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot.
+
+I'd like to extend my heartfelt gratitute to kind people for helping me work it out.
+I would particually thank Wolfgang Denk for his nice help.
+
+Enjoy,
+
+Sam Song, samsongshu@yahoo.com.cn
+Institute of Electrical Machinery and Controls
+Shanghai University
+
+Oct. 11, 2004
diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c
new file mode 100755
index 0000000..237c58a
--- /dev/null
+++ b/board/RPXlite_dw/RPXlite_dw.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2004
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Sam Song
+ * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
+ * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
+ * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+static long int dram_size (long int, long int *, long int);
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
+	_NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
+	/* INIT sequence RAM WORDS
+	 * SDRAM Initialization (offset 0x36 in UPMA RAM)
+	 * The above definition uses the remaining space
+	 * to establish an initialization sequence,
+	 * which is executed by a RUN command.
+	 * The sequence is COMMAND INHIBIT(NOP),Precharge,
+	 * Load Mode Register,NOP,Auto Refresh.
+	 */
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXlite_DW\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR ;
+
+	memctl->memc_mar  = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
+	/*Disable Periodic timer A. */
+
+ 	udelay(200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr  = 0x80002236; /* SDRAM bank 0 - refresh twice */
+
+	udelay(1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	/*Enable Periodic timer A */
+
+	udelay (1000);
+
+	 /* Check Bank 0 Memory Size
+	  * try 9 column mode
+	  */
+
+	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+
+	udelay (1000);
+
+	return (size9);
+}
+
+void rpxlite_init (void)
+{
+	/* Enable NVRAM */
+	*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
diff --git a/board/RPXlite_dw/config.mk b/board/RPXlite_dw/config.mk
new file mode 100755
index 0000000..7970910
--- /dev/null
+++ b/board/RPXlite_dw/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RPXlite dw boards : lite_dw
+#
+
+TEXT_BASE = 0xff000000
diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c
new file mode 100755
index 0000000..1cbd537
--- /dev/null
+++ b/board/RPXlite_dw/flash.c
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * Some of flash control words are modified. (from 2x16bit device
+ * to 4x8bit device)
+ * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
+ * are not tested.
+ *
+ * (?) Does an RPXLite board which
+ * 	does not use AM29LV800 flash memory exist ?
+ *	I don't know...
+ */
+
+/* Yes,Yoo.They do use other FLASH for the board.
+ *
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ * U-Boot port on RPXlite DW version board
+ *
+ * By now,it uses 4 AM29DL323DB90VI devices(4x8bit).
+ * The total FLASH has 16MB(4x4MB).
+ * I just made some necessary changes on the basis of Wolfgang and Yoo's job.
+ *
+ * June 8, 2004 */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions   vu_long : volatile unsigned long IN include/common.h
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* If Monitor is in the cope of FLASH,then
+	 * protect this area by default in case for
+	 * other occupation. [SAM] */
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+	flash_info[0].size = size_b0;
+	return (size_b0);
+}
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000);
+		}
+	} else {
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDL323B:    printf ("AM29DL323B (32 Mbit, bottom boot sector)\n");
+				break;
+	/* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM]  */
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+	printf ("  Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0x00AA00AA ;
+	addr[0x555] = 0x00550055 ;
+	addr[0xAAA] = 0x00900090 ;
+
+	value = addr[0] ;
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:             		/* AMD_MANUFACT=0x00010001 in flash.h. */
+		info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;			/* device ID		*/
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_LV400T & 0x00FF00FF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV400B & 0x00FF00FF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV800T & 0x00FF00FF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (AMD_ID_LV800B & 0x00FF00FF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/* Size doubled by yooth */
+		break;				/* => 4 MB		 */
+	case (AMD_ID_LV160T & 0x00FF00FF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_LV160B & 0x00FF00FF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_DL323B & 0x00FF00FF):
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;                          /* => 16 MB(4x4MB)  */
+	/* AMD_ID_DL323B= 0x22532253  FLASH_AMDL323B= 0x0013
+	 * AMD_ID_DL323B could be found in <flash.h>.[SAM]
+	 * So we could get : flash_id = 0x00000013.
+	 * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+	/* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1,
+	 * it means bottom boot flash. GOOD IDEA! [SAM]
+	 */
+
+	/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		/* info->protect[i] = addr[4] & 1 ; */
+		/* Mask it for disorder FLASH protection **[Sam]** */
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+	return (info->size);
+}
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds
new file mode 100755
index 0000000..a9c88f6
--- /dev/null
+++ b/board/RPXlite_dw/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+/* XXX ?
+    . = env_offset;
+*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug
new file mode 100755
index 0000000..c0cf1cb
--- /dev/null
+++ b/board/RPXlite_dw/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/RRvision/Makefile b/board/RRvision/Makefile
new file mode 100755
index 0000000..fdc6fd5
--- /dev/null
+++ b/board/RRvision/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c
new file mode 100755
index 0000000..f46bb9e
--- /dev/null
+++ b/board/RRvision/RRvision.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2001-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Always return 1 (no second DRAM bank).
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	puts ("Board: RRvision ");
+
+	for (; s && *s; ++s) {
+		if (*s == ' ')
+			break;
+		putc (*s);
+	}
+
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long reg;
+	long int size8, size9;
+	long int size = 0;
+
+	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 1 the SDRAM bank 2 at physical address 0.
+	 */
+	memctl->memc_or1 = CFG_OR2_PRELIM;
+	memctl->memc_br1 = CFG_BR2_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL,
+			   SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL,
+			   SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size = size9;
+/*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {			/* back to 8 columns            */
+		size = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+/*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if (size < 0x02000000) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+	memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/*
+	 * No bank 1
+	 *
+	 * invalidate bank
+	 */
+	memctl->memc_br3 = 0;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/board/RRvision/config.mk b/board/RRvision/config.mk
new file mode 100755
index 0000000..ab1c8d6
--- /dev/null
+++ b/board/RRvision/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RedRock vision boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/RRvision/flash.c b/board/RRvision/flash.c
new file mode 100755
index 0000000..d8e07e6
--- /dev/null
+++ b/board/RRvision/flash.c
@@ -0,0 +1,522 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef	CFG_ENV_ADDR
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & OR_AM_MSK);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	puts ("AMD ");			break;
+	case FLASH_MAN_FUJ:	puts ("FUJITSU ");		break;
+	default:		puts ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	puts ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	puts ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	puts ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	puts ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	puts ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	puts ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	puts ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	puts ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		puts ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	puts ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			puts ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	puts ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	switch (value) {
+	case AMD_ID_LV400B:
+	case AMD_ID_LV800B:
+	case AMD_ID_LV160B:
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+		break;
+	case AMD_ID_LV400T:
+	case AMD_ID_LV800T:
+	case AMD_ID_LV160T:
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+		break;
+	case AMD_ID_LV320B:
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			/*
+			 * The first 8 sectors are 8 kB,
+			 * all the other ones  are 64 kB
+			 */
+			base += (i < 8)
+				?  2 * ( 8 << 10)
+				:  2 * (64 << 10);
+		}
+		break;
+	case AMD_ID_LV320T:
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			/*
+			 * The last 8 sectors are 8 kB,
+			 * all the other ones  are 64 kB
+			 */
+			base += (i < (info->sector_count - 8))
+				?  2 * (64 << 10)
+				:  2 * ( 8 << 10);
+		}
+		break;
+	default:
+		return (0);
+		break;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			puts ("- missing\n");
+		} else {
+			puts ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		puts ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			puts ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	puts (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds
new file mode 100755
index 0000000..1d6288f
--- /dev/null
+++ b/board/RRvision/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = env_offset;
+    common/environment.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/RRvision/video_ad7179.h b/board/RRvision/video_ad7179.h
new file mode 100755
index 0000000..f146738
--- /dev/null
+++ b/board/RRvision/video_ad7179.h
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define VIDEO_ENCODER_NAME	"Analog Devices AD7179"
+
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100Khz	*/
+#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
+
+#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder	*/
+#undef	VIDEO_MODE_RGB
+#define VIDEO_MODE_BPP		16
+
+#ifdef	VIDEO_MODE_PAL
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	576
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	480
+#else
+#error "NTSC mode is not supported"
+#endif
+
+static unsigned char video_encoder_data[] = {
+				0x05, /* Mode Register 0 */
+				0x11, /* Mode Register 1 */
+				0x20, /* Mode Register 2 */
+				0x0C, /* Mode Register 3 */
+				0x01, /* Mode Register 4 */
+				0x00, /* Reserved */
+				0x00, /* Reserved */
+				0x04, /* Timing Register 0 */
+				0x00, /* Timing Register 1 */
+				0xCB, /* Subcarrier Frequency Register 0 */
+				0x0A, /* Subcarrier Frequency Register 1 */
+				0x09, /* Subcarrier Frequency Register 2 */
+				0x2A, /* Subcarrier Frequency Register 3 */
+				0x00, /* Subcarrier Phase */
+				0x00, /* Closed Captioning Ext Reg 0 */
+				0x00, /* Closed Captioning Ext Reg 1 */
+				0x00, /* Closed Captioning Reg 0 */
+				0x00, /* Closed Captioning Reg 1 */
+				0x00, /* Pedestal Control Reg 0 */
+				0x00, /* Pedestal Control Reg 1 */
+				0x00, /* Pedestal Control Reg 2 */
+				0x00, /* Pedestal Control Reg 3 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00, /* CGMS_WSS Reg 0 */
+				0x00  /* Teletext Req. Control Reg */
+} ;
diff --git a/board/a3000/Makefile b/board/a3000/Makefile
new file mode 100755
index 0000000..5fde362
--- /dev/null
+++ b/board/a3000/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS 	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/a3000/README b/board/a3000/README
new file mode 100755
index 0000000..f0e92c5
--- /dev/null
+++ b/board/a3000/README
@@ -0,0 +1,17 @@
+U-Boot for Artis SBC-A3000
+---------------------------
+
+Artis SBC-A3000 has one flash socket that the user uses Intel 28F128J3A (16MB)
+or 28F064J3A (8MB) chips.
+
+In board's notation, bank 0 is the one at the address of 0xFF000000.
+bank 1 is the one at the address of 0xFF800000
+
+On power-up the processor jumps to the address of 0xFFF00100, the last
+megabyte of the bank 0 of flash.
+
+Thus, U-Boot is configured to reside in flash starting at the address of
+0xFFF00000.  The environment space is located in flash separately from
+U-Boot, at the address of 0xFFFE0000.
+
+There is a National ns83815 10/100M ethernet controller on-board.
diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c
new file mode 100755
index 0000000..ab707ae
--- /dev/null
+++ b/board/a3000/a3000.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * Modified during 2003 by
+ * Ken Chou, kchou@ieee.org
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+int checkboard (void)
+{
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq));
+	return 0;
+
+}
+
+long int initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_a3000_config_table[] = {
+	/* vendor, device, class */
+	/* bus, dev, func */
+	{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
+	  PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,	/* dp83815 eth0 divice */
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x14, PCI_ANY_ID,		/* PCI slot1 */
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x15, PCI_ANY_ID, 	/* PCI slot2 */
+	  pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
+				       PCI_ENET2_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  PCI_ANY_ID, 0x16, PCI_ANY_ID,		/* PCI slot3 */
+	  pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
+				       PCI_ENET3_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_a3000_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
diff --git a/board/a3000/config.mk b/board/a3000/config.mk
new file mode 100755
index 0000000..798e032
--- /dev/null
+++ b/board/a3000/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Artis A-3000 boards
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/a3000/flash.c b/board/a3000/flash.c
new file mode 100755
index 0000000..13a5ca5
--- /dev/null
+++ b/board/a3000/flash.c
@@ -0,0 +1,454 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc824x.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR  (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+
+/*---------------------------------------------------------------------*/
+#define DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, uchar *dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+#define BS(b)     (b)
+#define BYTEME(x) ((x) & 0xFF)
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long flash_banks[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS;
+	unsigned long size, size_b[CFG_MAX_FLASH_BANKS];
+
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+	{
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		DEBUGF("Get flash bank %d @ 0x%08lx\n", i, flash_banks[i]);
+/*
+		size_b[i] = flash_get_size((vu_char *)flash_banks[i], &flash_info[i]);
+*/
+		size_b[i] = flash_get_size((vu_char *) 0xff800000 , &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN)
+		{
+			printf ("## Unknown FLASH on Bank %d: "
+				"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+				i, flash_info[i].flash_id,
+				size_b[i], size_b[i]<<20);
+		}
+		else
+		{
+			DEBUGF("## Flash bank %d at 0x%08lx sizes: 0x%08lx \n",
+				i, flash_banks[i], size_b[i]);
+
+			flash_get_offsets (flash_banks[i], &flash_info[i]);
+			flash_info[i].size = size_b[i];
+		}
+	}
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN);
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE);
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	size = 0;
+	DEBUGF("## Final Flash bank sizes: ");
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+	{
+		DEBUGF("%08lx ", size_b[i]);
+		size += size_b[i];
+	}
+	DEBUGF("\n");
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:
+		    for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				base += 0x00020000;		/* 128k per bank */
+		    }
+		    return;
+
+		default:
+		    printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id);
+		    return;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+			printf ("28F320J3A (32Mbit = 128K x 32)\n");
+			break;
+	case FLASH_28F640J3A:
+			printf ("28F640J3A (64Mbit = 128K x 64)\n");
+			break;
+	case FLASH_28F128J3A:
+			printf ("28F128J3A (128Mbit = 128K x 128)\n");
+			break;
+	default:
+			printf ("Unknown Chip Type\n");
+			break;
+	}
+
+#if 1
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+#endif
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+	vu_char manuf, device;
+
+	addr[0] = BS(0x90);
+	manuf = BS(addr[0]);
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, manuf);
+
+	switch (manuf) {
+	case BYTEME(AMD_MANUFACT):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case BYTEME(FUJ_MANUFACT):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case BYTEME(SST_MANUFACT):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case BYTEME(STM_MANUFACT):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case BYTEME(INTEL_MANUFACT):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = BS(0xFF);		/* restore read mode, (yes, BS is a NOP) */
+		return 0;			/* no or unknown flash	*/
+	}
+
+	device = BS(addr[2]);			/* device ID		*/
+
+	DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", (ulong)(&addr[1]), device);
+
+	switch (device) {
+	case BYTEME(INTEL_ID_28F320J3A):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* =>  4 MB		*/
+
+	case BYTEME(INTEL_ID_28F640J3A):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case BYTEME(INTEL_ID_28F128J3A):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = BS(0xFF);		/* restore read mode (yes, a NOP) */
+		return 0;			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = BS(0xFF);		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_char *addr = (vu_char *)(info->start[sect]);
+			unsigned long status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = BS(0x50);	/* clear status register */
+			*addr = BS(0x20);	/* erase setup */
+			*addr = BS(0xD0);	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag) {
+				enable_interrupts();
+			}
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = BS(0xB0); /* suspend erase	  */
+					*addr = BS(0xFF); /* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = BS(0xFF);	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	1	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	uchar *wp = (uchar *)addr;
+	int rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	while (cnt > 0) {
+		if ((rc = write_data(info, wp, *src)) != 0) {
+			return rc;
+		}
+		wp++;
+		src++;
+		cnt--;
+	}
+
+	return cnt;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, uchar *dest, uchar data)
+{
+	vu_char *addr = (vu_char *)dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((BS(*addr) & data) != data) {
+		return 2;
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = BS(0x40);		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+
+	start = get_timer (0);
+
+	while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = BS(0xFF);	/* restore read mode */
+			return 1;
+		}
+	}
+
+	*addr = BS(0xFF);	/* restore read mode */
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/a3000/u-boot.lds b/board/a3000/u-boot.lds
new file mode 100755
index 0000000..acb9ffd
--- /dev/null
+++ b/board/a3000/u-boot.lds
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/adder/Makefile b/board/adder/Makefile
new file mode 100755
index 0000000..9123a80
--- /dev/null
+++ b/board/adder/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/adder/adder.c b/board/adder/adder.c
new file mode 100755
index 0000000..cab6e2f
--- /dev/null
+++ b/board/adder/adder.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM is single Samsung K4S643232F-T70 chip.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+	/* Single read	(offset 0x00 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
+	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
+
+	/* Burst read	(offset 0x08 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
+	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
+	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
+
+	/* Single write (offset 0x18 in UPM RAM) */
+	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
+	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Burst write	(offset 0x20 in UPM RAM) */
+	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Refresh	(offset 0x30 in UPM RAM) */
+	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Exception	(offset 0x3C in UPM RAM) */
+	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
+};
+
+long int initdram (int board_type)
+{
+	long int msize = CFG_SDRAM_SIZE;
+	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/* Configure SDRAM refresh */
+	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
+
+	memctl->memc_mamr = (94 << 24) | CFG_MAMR;
+	memctl->memc_mar  = 0x0;
+	udelay(200);
+
+	/* Run precharge from location 0x15 */
+	memctl->memc_mcr = 0x80002115;
+	udelay(200);
+
+	/* Run 8 refresh cycles */
+	memctl->memc_mcr = 0x80002830;
+	udelay(200);
+
+	memctl->memc_mar = 0x88;
+	udelay(200);
+
+	/* Run MRS pattern from location 0x16 */
+	memctl->memc_mcr = 0x80002116;
+	udelay(200);
+
+	return msize;
+}
+
+int checkboard( void )
+{
+	puts("Board: Adder");
+#if defined(CONFIG_MPC885_FAMILY)
+	puts("87x\n");
+#elif defined(CONFIG_MPC866_FAMILY)
+	puts("II\n");
+#endif
+
+	return 0;
+}
diff --git a/board/adder/config.mk b/board/adder/config.mk
new file mode 100755
index 0000000..4691a69
--- /dev/null
+++ b/board/adder/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Analogue&Micro Adder boards family
+#
+TEXT_BASE = 0xFE000000
diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds
new file mode 100755
index 0000000..66c3246
--- /dev/null
+++ b/board/adder/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text          :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/adsvix/Makefile b/board/adsvix/Makefile
new file mode 100755
index 0000000..24d5d06
--- /dev/null
+++ b/board/adsvix/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= adsvix.o pcmcia.o
+SOBJS	:= lowlevel_init.o pxavoltage.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/adsvix/adsvix.c b/board/adsvix/adsvix.c
new file mode 100755
index 0000000..5e770e9
--- /dev/null
+++ b/board/adsvix/adsvix.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of ADSVIX-Board */
+	gd->bd->bi_arch_number = 620;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa000003c;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
diff --git a/board/adsvix/config.mk b/board/adsvix/config.mk
new file mode 100755
index 0000000..98be4eb
--- /dev/null
+++ b/board/adsvix/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1700000
diff --git a/board/adsvix/lowlevel_init.S b/board/adsvix/lowlevel_init.S
new file mode 100755
index 0000000..8dea71c
--- /dev/null
+++ b/board/adsvix/lowlevel_init.S
@@ -0,0 +1,466 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc	p15,0,\reg,c2,c0,0
+   mov	\reg,\reg
+   sub	pc,pc,#4
+   .endm
+
+
+/*
+ *	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR3
+	ldr		r1,	=CFG_GPSR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR3
+	ldr		r1,	=CFG_GPCR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR3
+	ldr		r1,	=CFG_GPDR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_L
+	ldr		r1,	=CFG_GAFR3_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_U
+	ldr		r1,	=CFG_GAFR3_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface					    */
+	/*								    */
+	/* The sequence below is based on the recommended init steps	    */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.							    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
+	/*	   clocks to settle. Only necessary after hard reset...	    */
+	/*	   FIXME: can be optimized later			    */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller	    */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type			    */
+
+	/* MSC0: nCS(0,1)						    */
+	ldr	r2,   =CFG_MSC0_VAL
+	str	r2,   [r1, #MSC0_OFFSET]
+	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
+						/* that data latches	    */
+	/* MSC1: nCS(2,3)						    */
+	ldr	r2,  =CFG_MSC1_VAL
+	str	r2,  [r1, #MSC1_OFFSET]
+	ldr	r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)						    */
+	ldr	r2,  =CFG_MSC2_VAL
+	str	r2,  [r1, #MSC2_OFFSET]
+	ldr	r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface				    */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register				    */
+	ldr	r2,  =CFG_MECR_VAL
+	str	r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing				    */
+	ldr	r2,  =CFG_MCMEM0_VAL
+	str	r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing				    */
+	ldr	r2,  =CFG_MCMEM1_VAL
+	str	r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
+	ldr	r2,  =CFG_MCATT0_VAL
+	str	r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
+	ldr	r2,  =CFG_MCATT1_VAL
+	str	r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
+	ldr	r2,  =CFG_MCIO0_VAL
+	str	r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
+	ldr	r2,  =CFG_MCIO1_VAL
+	str	r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
+	/* ---------------------------------------------------------------- */
+	ldr	r2,  =CFG_FLYCNFG_VAL
+	str	r2,  [r1, #FLYCNFG_OFFSET]
+	str	r2,	[r1, #FLYCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
+	/* this to power on defaults + DRI field.			    */
+
+	ldr	r4,	[r1, #MDREFR_OFFSET]
+	ldr	r2,	=0xFFF
+	bic	r4,	r4, r2
+
+	ldr	r3,	=CFG_MDREFR_VAL
+	and	r3,	r3,  r2
+
+	orr	r4,	r4, r3
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+
+	orr	r4,  r4, #MDREFR_K0RUN
+	orr	r4,  r4, #MDREFR_K0DB4
+	orr	r4,  r4, #MDREFR_K0FREE
+	orr	r4,  r4, #MDREFR_K0DB2
+	orr	r4,  r4, #MDREFR_K1DB2
+	bic	r4,  r4, #MDREFR_K1FREE
+	bic	r4,  r4, #MDREFR_K2FREE
+
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	/* Note: preserve the mdrefr value in r4			    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits		    */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.						    */
+
+	ldr	r2,  =CFG_SXCNFG_VAL
+	str	r2,  [r1, #SXCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM					    */
+	/* ---------------------------------------------------------------- */
+
+	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+	orr	r4, r4, #MDREFR_K1RUN
+	bic	r4, r4, #MDREFR_K2DB2
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	bic	r4, r4, #MDREFR_SLFRSH
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	orr	r4, r4, #MDREFR_E1PIN
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	nop
+	nop
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*	    configure but not enable each SDRAM partition pair.	    */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+
+	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
+	ldr	r4,	[r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
+	/*	    100..200 µsec.					    */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	    ldr r2, [r3]
+	    cmp r4, r2
+	    bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
+	/*	    attempting non-burst read or write accesses to disabled */
+	/*	    SDRAM, as commonly specified in the power up sequence   */
+	/*	    documented in SDRAM data sheets. The address(es) used   */
+	/*	    for this purpose must not be cacheable.		    */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+
+	/* Step 4g: Write MDCNFG with enable bits asserted		    */
+	/*	    (MDCNFG:DEx set to 1).				    */
+
+	ldr	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r4, r3
+	orr	r3,	r3,	#MDCNFG_DE0
+	str	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r0, r3
+
+	/* Step 4h: Write MDMRS.					    */
+
+	ldr	r2,  =CFG_MDMRS_VAL
+	str	r2,  [r1, #MDMRS_OFFSET]
+
+	/* enable APD */
+	ldr	r3,  [r1, #MDREFR_OFFSET]
+	orr	r3,  r3,  #MDREFR_APD
+	str	r3,  [r1, #MDREFR_OFFSET]
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+setvoltage:
+
+	mov	r10,	lr
+	bl	initPXAvoltage	/* In case the board is rebooting with a    */
+	mov	lr,	r10	/* low voltage raise it up to a good one.   */
+
+wakeup:
+	/* Are we waking from sleep? */
+	ldr	r0,	=RCSR
+	ldr	r1,	[r0]
+	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+	str	r1,	[r0]
+	teq	r1,	#RCSR_SMR
+
+	bne	initirqs
+
+	ldr	r0,	=PSSR
+	mov	r1,	#PSSR_PH
+	str	r1,	[r0]
+
+	/* if so, resume at PSPR */
+	ldr	r0,	=PSPR
+	ldr	r1,	[r0]
+	mov	pc,	r1
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller	    */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr	r2,  =ICLR
+	str	r1,  [r2]
+
+	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
+	str	r1,  [r2]
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation						    */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+
+	/* Turn Off on-chip peripheral clocks (except for memory)	    */
+	/* for re-configuration.					    */
+	ldr	r1,  =CKEN
+	ldr	r2,  =CFG_CKEN
+	str	r2,  [r1]
+
+	/* ... and write the core clock config register			    */
+	ldr	r2,  =CFG_CCCR
+	ldr	r1,  =CCCR
+	str	r2,  [r1]
+
+	/* Turn on turbo mode */
+	mrc	p14, 0, r2, c6, c0, 0
+	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
+	mcr	p14, 0, r2, c6, c0, 0
+
+	/* Re-write MDREFR */
+	ldr	r1, =MEMC_BASE
+	ldr	r2, [r1, #MDREFR_OFFSET]
+	str	r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager		    */
+	ldr	r1,  =OSCC
+	mov	r2,  #OSCC_OON
+	str	r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
+	/* has settled.							    */
+60:
+	ldr	r2, [r1]
+	ands	r2, r2, #1
+	beq	60b
+#else
+#error "RTC not defined"
+#endif
+
+	/* Interrupt init: Mask all interrupts				    */
+    ldr r0, =ICMR /* enable no sources */
+	mov r1, #0
+    str r1, [r0]
+	/* FIXME */
+
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init							    */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+	mov	pc, lr
diff --git a/board/adsvix/pcmcia.c b/board/adsvix/pcmcia.c
new file mode 100755
index 0000000..ba5be01
--- /dev/null
+++ b/board/adsvix/pcmcia.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+void pcmcia_power_on(void)
+{
+#if 0
+	if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */
+		GPCR(81) = GPIO_bit(81);
+		GPSR(82) = GPIO_bit(82);
+	}
+	else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */
+		GPCR(81) = GPIO_bit(81);
+		GPCR(82) = GPIO_bit(82);
+	}
+#else
+#warning "Board will only supply 5V, wait for next HW spin for selectable power"
+	/* 5.0V */
+	GPCR(81) = GPIO_bit(81);
+	GPCR(82) = GPIO_bit(82);
+#endif
+
+	udelay(300000);
+
+	/* reset the card */
+	GPSR(52) = GPIO_bit(52);
+
+	/* enable PCMCIA */
+	GPCR(83) = GPIO_bit(83);
+
+	/* clear reset */
+	udelay(10);
+	GPCR(52) = GPIO_bit(52);
+
+	udelay(20000);
+}
+
+void pcmcia_power_off(void)
+{
+	/* 0V */
+	GPSR(81) = GPIO_bit(81);
+	GPSR(82) = GPIO_bit(82);
+	/* disable PCMCIA */
+	GPSR(83) = GPIO_bit(83);
+}
diff --git a/board/adsvix/pxavoltage.S b/board/adsvix/pxavoltage.S
new file mode 100755
index 0000000..2fe1cab
--- /dev/null
+++ b/board/adsvix/pxavoltage.S
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+
+#define LTC1663_ADDR    0x20
+
+#define LTC1663_SY	0x01	/* Sync ACK */
+#define LTC1663_SD	0x04	/* shutdown */
+#define LTC1663_BG	0x04	/* Internal Voltage Ref */
+
+#define VOLT_1_55         18    /* DAC value for 1.55V */
+
+		.global	initPXAvoltage
+
+@ Set the voltage to 1.55V early in the boot process so we can run
+@ at a high clock speed and boot quickly.  Note that this is necessary
+@ because the reset button does not reset the CPU voltage, so if the
+@ voltage was low (say 0.85V) then the CPU would crash without this
+@ routine
+
+@ This routine clobbers r0-r4
+
+initializei2c:
+
+		ldr	r2, =CKEN
+		ldr	r3, [r2]
+		orr	r3, r3, #CKEN15_PWRI2C
+		str	r3, [r2]
+
+		ldr	r2, =PCFR
+		ldr	r3, [r2]
+		orr	r3, r3, #PCFR_PI2C_EN
+		str	r3, [r2]
+
+		/* delay for about 250msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0000
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		ldr	r0, =PWRICR
+		ldr	r1, [r0]
+		bic	r1, r1, #(ICR_MA | ICR_START | ICR_STOP)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		ldr	r2, =PWRISR
+		ldr	r3, =0x7ff
+		str	r3, [r2]
+
+		bic	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		mov	r1, #(ICR_GCD | ICR_SCLE)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_IUE
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_FM
+		str	r1, [r0]
+
+		/* delay for about 1msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC00
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, lr
+
+sendbytei2c:
+		ldr	r3, =PWRIDBR
+		str	r0, [r3]
+		ldr	r3, =PWRICR
+		ldr	r0, [r3]
+		orr	r0, r0, r1
+		bic	r0, r0, r2
+		str	r0, [r3]
+		orr	r0, r0, #ICR_TB
+		str	r0, [r3]
+
+		mov	r2, #0x100000
+
+waitfortxemptyi2c:
+
+		ldr	r0, =PWRISR
+		ldr	r1, [r0]
+
+		/* take it from the top if we don't get empty after a while */
+		subs	r2, r2, #1
+		moveq	lr, r4
+		beq	initPXAvoltage
+
+		tst	r1, #ISR_ITE
+
+		beq	waitfortxemptyi2c
+
+		orr	r1, r1, #ISR_ITE
+		str	r1, [r0]
+
+		mov	pc, lr
+
+initPXAvoltage:
+
+		mov	r4, lr
+
+		bl	setleds
+
+		bl	initializei2c
+
+		bl	setleds
+
+		/* now send the real message to set the correct voltage */
+		ldr	r0, =LTC1663_ADDR
+		mov	r0, r0, LSL #1
+		mov	r1, #ICR_START
+		ldr	r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		mov	r0, #LTC1663_BG
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		and	r0, r0, #0xff
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		mov	r0, r0, ASR #8
+		and	r0, r0, #0xff
+		mov	r1, #ICR_STOP
+		mov	r2, #ICR_START
+		bl	sendbytei2c
+
+		bl	setleds
+
+		@ delay a little for the volatage to stablize
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, r4
+
+setleds:
+	mov		pc, lr
+
+	ldr		r5, =0x40e00058
+	ldr		r3, [r5]
+	bic		r3, r3, #0x3
+	str		r3, [r5]
+	ldr		r5, =0x40e0000c
+	ldr		r3, [r5]
+	orr		r3, r3, #0x00010000
+	str		r3, [r5]
+
+	@ inner loop
+	mov		r0, #0x2
+1:
+
+	ldr		r5, =0x40e00018
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+2:
+	subs		r3, r3, #1
+	bne		2b
+
+	ldr		r5, =0x40e00024
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+3:
+	subs		r3, r3, #1
+	bne		3b
+
+	subs		r0, r0, #1
+	bne		1b
+
+	mov		pc, lr
diff --git a/board/adsvix/u-boot.lds b/board/adsvix/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/adsvix/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/alaska/Makefile b/board/alaska/Makefile
new file mode 100755
index 0000000..a4c1d2e
--- /dev/null
+++ b/board/alaska/Makefile
@@ -0,0 +1,45 @@
+# (C) Copyright 2003-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c
new file mode 100755
index 0000000..93874b2
--- /dev/null
+++ b/board/alaska/alaska.c
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2004, Freescale Inc.
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8220.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+void setupBat (ulong size)
+{
+	ulong batu, batl;
+	int blocksize = 0;
+
+	/* Flash 0 */
+#if defined (CFG_AMD_BOOT)
+	batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+#else
+	batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+#endif
+	batl = CFG_FLASH0_BASE | 0x22;
+	write_bat (IBAT0, batu, batl);
+	write_bat (DBAT0, batu, batl);
+
+	/* Flash 1 */
+#if defined (CFG_AMD_BOOT)
+	batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+#else
+	batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+#endif
+	batl = CFG_FLASH1_BASE | 0x22;
+	write_bat (IBAT1, batu, batl);
+	write_bat (DBAT1, batu, batl);
+
+	/* CPLD */
+	batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batl = CFG_CPLD_BASE | 0x22;
+	write_bat (IBAT2, 0, 0);
+	write_bat (DBAT2, batu, batl);
+
+	/* FPGA */
+	batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batl = CFG_FPGA_BASE | 0x22;
+	write_bat (IBAT3, 0, 0);
+	write_bat (DBAT3, batu, batl);
+
+	/* MBAR - Data only */
+	batu = CFG_MBAR | BPP_RW | BPP_RX;
+	batl = CFG_MBAR | 0x22;
+	mtspr (IBAT4L, 0);
+	mtspr (IBAT4U, 0);
+	mtspr (DBAT4L, batl);
+	mtspr (DBAT4U, batu);
+
+	/* MBAR - SRAM */
+	batu = CFG_SRAM_BASE | BPP_RW | BPP_RX;
+	batl = CFG_SRAM_BASE | 0x42;
+	mtspr (IBAT5L, batl);
+	mtspr (IBAT5U, batu);
+	mtspr (DBAT5L, batl);
+	mtspr (DBAT5U, batu);
+
+	if (size <= 0x800000)	/* 8MB */
+		blocksize = BL_8M << 2;
+	else if (size <= 0x1000000)	/* 16MB */
+		blocksize = BL_16M << 2;
+	else if (size <= 0x2000000)	/* 32MB */
+		blocksize = BL_32M << 2;
+	else if (size <= 0x4000000)	/* 64MB */
+		blocksize = BL_64M << 2;
+	else if (size <= 0x8000000)	/* 128MB */
+		blocksize = BL_128M << 2;
+	else if (size <= 0x10000000)	/* 256MB */
+		blocksize = BL_256M << 2;
+
+	/* Memory */
+	batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
+	batl = CFG_SDRAM_BASE | 0x42;
+	mtspr (IBAT6L, batl);
+	mtspr (IBAT6U, batu);
+	mtspr (DBAT6L, batl);
+	mtspr (DBAT6U, batu);
+
+	/* memory size is less than 256MB */
+	if (size <= 0x10000000) {
+		/* Nothing */
+		batu = 0;
+		batl = 0;
+	} else {
+		size -= 0x10000000;
+		if (size <= 0x800000)	/* 8MB */
+			blocksize = BL_8M << 2;
+		else if (size <= 0x1000000)	/* 16MB */
+			blocksize = BL_16M << 2;
+		else if (size <= 0x2000000)	/* 32MB */
+			blocksize = BL_32M << 2;
+		else if (size <= 0x4000000)	/* 64MB */
+			blocksize = BL_64M << 2;
+		else if (size <= 0x8000000)	/* 128MB */
+			blocksize = BL_128M << 2;
+		else if (size <= 0x10000000)	/* 256MB */
+			blocksize = BL_256M << 2;
+
+		batu = (CFG_SDRAM_BASE +
+			0x10000000) | blocksize | BPP_RW | BPP_RX;
+		batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42;
+	}
+
+	mtspr (IBAT7L, batl);
+	mtspr (IBAT7U, batu);
+	mtspr (DBAT7L, batl);
+	mtspr (DBAT7U, batu);
+}
+
+long int initdram (int board_type)
+{
+	ulong size;
+
+	size = dramSetup ();
+
+/* if iCache ad dCache is defined */
+#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
+/*    setupBat(size);*/
+#endif
+
+	return size;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Alaska MPC8220 Evaluation Board\n");
+
+	return 0;
+}
diff --git a/board/alaska/config.mk b/board/alaska/config.mk
new file mode 100755
index 0000000..99d28a5
--- /dev/null
+++ b/board/alaska/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# alaska board
+#
+
+TEXT_BASE = 0xfff00000
+# TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/alaska/flash.c b/board/alaska/flash.c
new file mode 100755
index 0000000..383491f
--- /dev/null
+++ b/board/alaska/flash.c
@@ -0,0 +1,936 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH8
+
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+
+#define SWAP(x)         (x)
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT    0x89
+#define INTEL_ALT       0xB0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM   0x10
+#define INTEL_ERASE     0x20
+#define INTEL_CLEAR     0x50
+#define INTEL_LOCKBIT   0x60
+#define INTEL_PROTECT   0x01
+#define INTEL_STATUS    0x70
+#define INTEL_READID    0x90
+#define INTEL_CONFIRM   0xD0
+#define INTEL_RESET     0xFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED  0x80
+#define INTEL_OK        0x80
+
+#define FPW             FLASH_PORT_WIDTH
+#define FPWV            FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1    0x0555
+#define FLASH_CYCLE2    0x02aa
+
+#define WR_BLOCK        0x20
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static int write_data_block (flash_info_t * info, ulong src, ulong dest);
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+static unsigned char same_chip_banks (int bank1, int bank2);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	ulong fsize = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		memset (&flash_info[i], 0, sizeof (flash_info_t));
+
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) CFG_FLASH1_BASE,
+					&flash_info[i]);
+			flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) CFG_FLASH1_BASE,
+					&flash_info[i]);
+			fsize = CFG_FLASH1_BASE + flash_info[i - 1].size;
+			flash_get_offsets (fsize, &flash_info[i]);
+			break;
+		case 2:
+			flash_get_size ((FPW *) CFG_FLASH0_BASE,
+					&flash_info[i]);
+			flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]);
+			break;
+		case 3:
+			flash_get_size ((FPW *) CFG_FLASH0_BASE,
+					&flash_info[i]);
+			fsize = CFG_FLASH0_BASE + flash_info[i - 1].size;
+			flash_get_offsets (fsize, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+
+		/* get the h/w and s/w protection status in sync */
+		flash_sync_real_protect(&flash_info[i]);
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if defined (CFG_AMD_BOOT)
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[2]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_INTEL_BASE,
+		       CFG_INTEL_BASE + monitor_flash_len - 1,
+		       &flash_info[1]);
+#else
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[3]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_AMD_BASE,
+		       CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV1_ADDR,
+		       CFG_ENV1_ADDR + CFG_ENV1_SIZE - 1, &flash_info[1]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[3]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_AMD_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+
+	case FLASH_AM040:
+		printf ("AMD29F040B\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	FPWV value;
+	static int amd = 0;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	__asm__ ("sync");
+	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	__asm__ ("sync");
+	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD */
+	__asm__ ("sync");
+
+	udelay (100);
+
+	switch (addr[0] & 0xff) {
+
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		value = addr[1];
+		break;
+
+	case (uchar) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		value = addr[2];
+		break;
+
+	default:
+		printf ("unknown\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;	/* => 16 MB     */
+		break;
+
+	case (FPW) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		if (amd == 0) {
+			info->sector_count = 7;
+			info->size = 0x00070000;	/* => 448 KB     */
+			amd = 1;
+		} else {
+			/* for Environment settings */
+			info->sector_count = 1;
+			info->size = PHYS_AMD_SECT_SIZE;	/* => 64 KB     */
+			amd = 0;
+		}
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	if (value == (FPW) INTEL_ID_28F128J3A)
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+	else
+		addr[0] = (FPW) 0x00F000F0;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		for (i = 0; i < info->sector_count; ++i) {
+			info->protect[i] = intel_sector_protected(info, i);
+		}
+		break;
+	case FLASH_AM040:
+	default:
+		/* no h/w protect support */
+		break;
+	}
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+	FPWV *addr;
+	FPWV *lock_conf_addr;
+	ulong start;
+	unsigned char ret;
+
+	/*
+	 * first, wait for the WSM to be finished. The rationale for
+	 * waiting for the WSM to become idle for at most
+	 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * because of: (1) erase, (2) program or (3) lock bit
+	 * configuration. So we just wait for the longest timeout of
+	 * the (1)-(3), i.e. the erase timeout.
+	 */
+
+	/* wait at least 35ns (W12) before issuing Read Status Register */
+	udelay(1);
+	addr = (FPWV *) info->start[sector];
+	*addr = (FPW) INTEL_STATUS;
+
+	start = get_timer (0);
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+			*addr = (FPW) INTEL_RESET; /* restore read mode */
+			printf("WSM busy too long, can't get prot status\n");
+			return 1;
+		}
+	}
+
+	/* issue the Read Identifier Codes command */
+	*addr = (FPW) INTEL_READID;
+
+	/* wait at least 35ns (W12) before reading */
+	udelay(1);
+
+	/* Intel example code uses offset of 4 for 8-bit flash */
+	lock_conf_addr = (FPWV *) info->start[sector] + 4;
+	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+	/* put flash back in read mode */
+	*addr = (FPW) INTEL_RESET;
+
+	return ret;
+}
+
+
+/*
+ * Checks if "bank1" and "bank2" are on the same chip.  Returns 1 if they
+ * are and 0 otherwise.
+ */
+static unsigned char same_chip_banks (int bank1, int bank2)
+{
+	unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = {
+		{1, 1, 0, 0},
+		{1, 1, 0, 0},
+		{0, 0, 1, 1},
+		{0, 0, 1, 1}
+	};
+	return same_chip[bank1][bank2];
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0, intel = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		type = (info->flash_id & FLASH_VENDMASK);
+		if ((type != FLASH_MAN_AMD)) {
+			printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+			return 1;
+		}
+	}
+
+	if (type == FLASH_MAN_INTEL)
+		intel = 1;
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer (0);
+
+			if (intel) {
+				*addr = (FPW) 0x00500050;	/* clear status register */
+				*addr = (FPW) 0x00200020;	/* erase setup */
+				*addr = (FPW) 0x00D000D0;	/* erase confirm */
+			} else {
+				FPWV *base;	/* first address in bank */
+
+				base = (FPWV *) (CFG_AMD_BASE);
+				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+				base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
+				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+				*addr = (FPW) 0x00300030;	/* erase sector */
+			}
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					if (intel) {
+						*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+						*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					} else
+						*addr = (FPW) 0x00F000F0;	/* reset to read mode */
+
+					rcode = 1;
+					break;
+				}
+			}
+
+			if (intel) {
+				*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+				*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+			} else
+				*addr = (FPW) 0x00F000F0;	/* reset to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+	    {
+		FPW data = 0;	/* 16 or 32 bit word, matches flash bus width */
+		int bytes;	/* number of bytes to program in current word */
+		int left;	/* number of bytes left to program */
+		int i, res;
+
+		for (left = cnt, res = 0;
+		     left > 0 && res == 0;
+		     addr += sizeof (data), left -=
+		     sizeof (data) - bytes) {
+
+			bytes = addr & (sizeof (data) - 1);
+			addr &= ~(sizeof (data) - 1);
+
+			/* combine source and destination data so can program
+			 * an entire word of 16 or 32 bits
+			 */
+			for (i = 0; i < sizeof (data); i++) {
+				data <<= 8;
+				if (i < bytes || i - bytes >= left)
+					data += *((uchar *) addr + i);
+				else
+					data += *src++;
+			}
+
+			res = write_word_amd (info, (FPWV *) addr,
+					      data);
+		}
+		return res;
+	    }		/* case FLASH_MAN_AMD */
+
+	case FLASH_MAN_INTEL:
+	    {
+		ulong cp, wp;
+		FPW data;
+		int count, i, l, rc, port_width;
+
+		/* get lower word aligned address */
+		wp = addr;
+		port_width = 1;
+
+		/*
+		 * handle unaligned start bytes
+		 */
+		if ((l = addr - wp) != 0) {
+			data = 0;
+			for (i = 0, cp = wp; i < l; ++i, ++cp) {
+				data = (data << 8) | (*(uchar *) cp);
+			}
+
+			for (; i < port_width && cnt > 0; ++i) {
+				data = (data << 8) | *src++;
+				--cnt;
+				++cp;
+			}
+
+			for (; cnt == 0 && i < port_width; ++i, ++cp)
+				data = (data << 8) | (*(uchar *) cp);
+
+			if ((rc =
+			     write_data (info, wp, SWAP (data))) != 0)
+				return (rc);
+			wp += port_width;
+		}
+
+		if (cnt > WR_BLOCK) {
+			/*
+			 * handle word aligned part
+			 */
+			count = 0;
+			while (cnt >= WR_BLOCK) {
+
+				if ((rc =
+				     write_data_block (info,
+						       (ulong) src,
+						       wp)) != 0)
+					return (rc);
+
+				wp += WR_BLOCK;
+				src += WR_BLOCK;
+				cnt -= WR_BLOCK;
+
+				if (count++ > 0x800) {
+					spin_wheel ();
+					count = 0;
+				}
+			}
+		}
+
+		if (cnt < WR_BLOCK) {
+			/*
+			 * handle word aligned part
+			 */
+			count = 0;
+			while (cnt >= port_width) {
+				data = 0;
+				for (i = 0; i < port_width; ++i)
+					data = (data << 8) | *src++;
+
+				if ((rc =
+				     write_data (info, wp,
+						 SWAP (data))) != 0)
+					return (rc);
+
+				wp += port_width;
+				cnt -= port_width;
+				if (count++ > 0x800) {
+					spin_wheel ();
+					count = 0;
+				}
+			}
+		}
+
+		if (cnt == 0)
+			return (0);
+
+		/*
+		 * handle unaligned tail bytes
+		 */
+		data = 0;
+		for (i = 0, cp = wp; i < port_width && cnt > 0;
+		     ++i, ++cp) {
+			data = (data << 8) | *src++;
+			--cnt;
+		}
+
+		for (; i < port_width; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		return (write_data (info, wp, SWAP (data)));
+	    }		/* case FLASH_MAN_INTEL */
+
+	}			/* switch */
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer (0);
+
+	/* wait while polling the status register */
+	while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data_block (flash_info_t * info, ulong src, ulong dest)
+{
+	FPWV *srcaddr = (FPWV *) src;
+	FPWV *dstaddr = (FPWV *) dest;
+	ulong start;
+	int flag, i;
+
+	/* Check if Flash is (sufficiently) erased */
+	for (i = 0; i < WR_BLOCK; i++)
+		if ((*dstaddr++ & 0xff) != 0xff) {
+			printf ("not erased at %08lx (%lx)\n",
+				(ulong) dstaddr, *dstaddr);
+			return (2);
+		}
+
+	dstaddr = (FPWV *) dest;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*dstaddr = (FPW) 0x00e800e8;	/* write block setup */
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer (0);
+
+	/* wait while polling the status register */
+	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*dstaddr = (FPW) 0x001f001f;	/* write 32 to buffer */
+	for (i = 0; i < WR_BLOCK; i++)
+		*dstaddr++ = *srcaddr++;
+
+	dstaddr -= 1;
+	*dstaddr = (FPW) 0x00d000d0;	/* write 32 to buffer */
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer (0);
+
+	/* wait while polling the status register */
+	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success */
+	FPWV *base;		/* first address in flash bank */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (CFG_AMD_BASE);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	ulong start;
+	int i, j;
+	int curr_bank;
+	int bank;
+	int rc = 0;
+	FPWV *addr = (FPWV *) (info->start[sector]);
+	int flag = disable_interrupts ();
+
+	/*
+	 * 29F040B AMD flash does not support software protection/unprotection,
+	 * the only way to protect the AMD flash is marked it as prot bit.
+	 * This flash only support hardware protection, by supply or not supply
+	 * 12vpp to the flash
+	 */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		info->protect[sector] = prot;
+
+		return 0;
+	}
+
+	*addr = INTEL_CLEAR;	/* Clear status register    */
+	if (prot) {		/* Set sector lock bit      */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit          */
+		*addr = INTEL_PROTECT;	/* set                      */
+	} else {		/* Clear sector lock bit    */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits    */
+		*addr = INTEL_CONFIRM;	/* clear                    */
+	}
+
+	start = get_timer (0);
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
+			printf ("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
+			(uint) addr, (uint) * addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot) {
+		/*
+		 * re-locking must be done for all banks that belong on one
+		 * FLASH chip, as all the sectors on the chip were unlocked
+		 * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope
+		 * that banks never span chips, in particular chips which
+		 * support h/w protection differently).
+		 */
+
+		/* find the current bank number */
+		curr_bank = CFG_MAX_FLASH_BANKS + 1;
+		for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) {
+			if (&flash_info[j] == info) {
+				curr_bank = j;
+			}
+		}
+		if (curr_bank == CFG_MAX_FLASH_BANKS + 1) {
+			printf("Error: can't determine bank number!\n");
+		}
+
+		for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) {
+			if (!same_chip_banks(curr_bank, bank)) {
+				continue;
+			}
+			info = &flash_info[bank];
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i]) {
+					start = get_timer (0);
+					addr = (FPWV *) (info->start[i]);
+					*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
+					*addr = INTEL_PROTECT;	/* set              */
+					while ((*addr & INTEL_FINISHED) !=
+					       INTEL_FINISHED) {
+						if (get_timer (start) >
+						    CFG_FLASH_UNLOCK_TOUT) {
+							printf ("Flash lock bit operation timed out\n");
+							rc = 1;
+							break;
+						}
+					}
+				}
+			}
+		}
+
+		/*
+		 * get the s/w sector protection status in sync with the h/w,
+		 * in case something went wrong during the re-locking.
+		 */
+		flash_sync_real_protect(info); /* resets flash to read  mode */
+	}
+
+	if (flag)
+		enable_interrupts ();
+
+	*addr = INTEL_RESET;	/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/board/alaska/u-boot.lds b/board/alaska/u-boot.lds
new file mode 100755
index 0000000..889bc77
--- /dev/null
+++ b/board/alaska/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8220/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/altera/common/flash.c b/board/altera/common/flash.c
new file mode 100755
index 0000000..2638ea8
--- /dev/null
+++ b/board/altera/common/flash.c
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	unsigned long size;
+	int erased;
+	volatile unsigned char *flash;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned char *) info->start[i];
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s", info->start[i], erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int prot, sect;
+	unsigned oldpri;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	for (sect = s_first; sect <= s_last; sect++) {
+		printf("- Erase: Sect: %i @ 0x%08x\n", sect,  info->start[sect]);
+	}
+#endif
+
+	/* NOTE: disabling interrupts on Nios can be very bad since it
+	 * also disables the LO_LIMIT exception. It's better here to
+	 * set the interrupt priority to 3 & restore it when we're done.
+	 */
+	oldpri = ipri (3);
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr = 0x80;
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr2 = 0x30;
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait. Here we have to grant
+			 * timer interrupts. Otherwise get_timer() can't
+			 * work right. */
+			ipri(oldpri);
+			start = get_timer (0);
+			while (*addr2 != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+			oldpri = ipri (3); /* disallow non important irqs again */
+		}
+	}
+
+	printf ("\n");
+
+	/* Restore interrupt priority */
+	ipri (oldpri);
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
+	unsigned char b;
+	unsigned oldpri;
+	ulong start;
+
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((*dst & b) != b) {
+			printf ("%02x : %02x\n", *dst, b);
+			return (2);
+		}
+
+		/* Disable interrupts other than window underflow
+		 * (interrupt priority 2)
+		 */
+		oldpri = ipri (3);
+		*cmd = 0xaa;
+		*cmd = 0x55;
+		*cmd = 0xa0;
+		*dst = b;
+
+		/* Verify write */
+		start = get_timer (0);
+		while (*dst != b) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				ipri (oldpri);
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+		ipri (oldpri);
+	}
+
+	return (0);
+}
diff --git a/board/altera/common/sevenseg.c b/board/altera/common/sevenseg.c
new file mode 100755
index 0000000..c53cec1
--- /dev/null
+++ b/board/altera/common/sevenseg.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * common/sevenseg.c
+ *
+ * NIOS PIO based seven segment led support functions
+ */
+
+#include <common.h>
+#include <nios-io.h>
+
+#ifdef	CONFIG_SEVENSEG
+
+#define SEVENDEG_MASK_DP	((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP)
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+#if (SEVENSEG_ACTIVE == 0)
+static unsigned int sevenseg_portval = ~0;
+#else
+static unsigned int sevenseg_portval = 0;
+#endif
+#endif
+
+static int sevenseg_init_done = 0;
+
+static inline void __sevenseg_set_masked (unsigned int mask, int value)
+{
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+
+#if (SEVENSEG_ACTIVE == 0)
+	if (value)
+		sevenseg_portval &= ~mask;
+	else
+		sevenseg_portval |= mask;
+#else
+	if (value)
+		sevenseg_portval |= mask;
+	else
+		sevenseg_portval &= ~mask;
+#endif
+
+	piop->data = sevenseg_portval;
+
+#else	/* !SEVENSEG_WRONLY */
+
+#if (SEVENSEG_ACTIVE == 0)
+	if (value)
+		piop->data &= ~mask;
+	else
+		piop->data |= mask;
+#else
+	if (value)
+		piop->data |= mask;
+	else
+		piop->data &= ~mask;
+#endif
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+static inline void __sevenseg_toggle_masked (unsigned int mask)
+{
+	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+
+	sevenseg_portval ^= mask;
+	piop->data = sevenseg_portval;
+
+#else	/* !SEVENSEG_WRONLY */
+
+	piop->data ^= mask;
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+static inline void __sevenseg_set (unsigned int value)
+{
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
+
+#ifdef	SEVENSEG_WRONLY	/* emulate read access */
+
+#if (SEVENSEG_ACTIVE == 0)
+	sevenseg_portval = (sevenseg_portval &   SEVENDEG_MASK_DP)
+		         | ((~value)         & (~SEVENDEG_MASK_DP));
+#else
+	sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
+		         | (value);
+#endif
+
+	piop->data = sevenseg_portval;
+
+#else	/* !SEVENSEG_WRONLY */
+
+#if (SEVENSEG_ACTIVE == 0)
+	piop->data = (piop->data &   SEVENDEG_MASK_DP)
+		   | ((~value)   & (~SEVENDEG_MASK_DP));
+#else
+	piop->data = (piop->data & SEVENDEG_MASK_DP)
+		   | (value);
+#endif
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+static inline void __sevenseg_init (void)
+{
+	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
+
+	__sevenseg_set(0);
+
+#ifndef	SEVENSEG_WRONLY	/* setup direction */
+
+	piop->direction |= mask;
+
+#endif	/* SEVENSEG_WRONLY */
+}
+
+
+void sevenseg_set(int value)
+{
+	unsigned char	digits[] = {
+		SEVENSEG_DIGITS_0,
+		SEVENSEG_DIGITS_1,
+		SEVENSEG_DIGITS_2,
+		SEVENSEG_DIGITS_3,
+		SEVENSEG_DIGITS_4,
+		SEVENSEG_DIGITS_5,
+		SEVENSEG_DIGITS_6,
+		SEVENSEG_DIGITS_7,
+		SEVENSEG_DIGITS_8,
+		SEVENSEG_DIGITS_9,
+		SEVENSEG_DIGITS_A,
+		SEVENSEG_DIGITS_B,
+		SEVENSEG_DIGITS_C,
+		SEVENSEG_DIGITS_D,
+		SEVENSEG_DIGITS_E,
+		SEVENSEG_DIGITS_F
+	};
+
+	if (!sevenseg_init_done) {
+		__sevenseg_init();
+		sevenseg_init_done++;
+	}
+
+	switch (value & SEVENSEG_MASK_CTRL) {
+
+		case SEVENSEG_RAW:
+			__sevenseg_set( (
+				(digits[((value & SEVENSEG_MASK_VAL) >>  4)] << 8) |
+				digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) );
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_OFF:
+			__sevenseg_set(0);
+			__sevenseg_set_masked(SEVENDEG_MASK_DP, 0);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_SET_DPL:
+			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_SET_DPH:
+			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_RES_DPL:
+			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_RES_DPH:
+			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_TOG_DPL:
+			__sevenseg_toggle_masked(SEVENSEG_DIGIT_DP);
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_TOG_DPH:
+			__sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8));
+			return;
+			break;	/* paranoia */
+
+		case SEVENSEG_LO:
+		case SEVENSEG_HI:
+		case SEVENSEG_STR:
+		default:
+			break;
+	}
+}
+
+#endif	/* CONFIG_SEVENSEG */
diff --git a/board/altera/common/sevenseg.h b/board/altera/common/sevenseg.h
new file mode 100755
index 0000000..cbfd2e7
--- /dev/null
+++ b/board/altera/common/sevenseg.h
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * common/sevenseg.h
+ *
+ * NIOS PIO based seven segment led support functions
+ */
+
+#ifndef __DK1S10_SEVENSEG_H__
+#define __DK1S10_SEVENSEG_H__
+
+#ifdef	CONFIG_SEVENSEG
+
+/*
+ *  15                    8 7      0
+ * |-----------------------|--------|
+ * |   controll value      |  value |
+ * ----------------------------------
+ */
+#define	SEVENSEG_RAW		(int)(0)	/* write out byte value (hex) */
+#define	SEVENSEG_OFF		(int)( 1 << 8)	/* display switch off */
+#define	SEVENSEG_SET_DPL	(int)( 2 << 8)	/* set dp low  nibble */
+#define	SEVENSEG_SET_DPH	(int)( 3 << 8)	/* set dp high nibble */
+#define	SEVENSEG_RES_DPL	(int)( 4 << 8)	/* reset dp low  nibble */
+#define	SEVENSEG_RES_DPH	(int)( 5 << 8)	/* reset dp high nibble */
+#define	SEVENSEG_TOG_DPL	(int)( 6 << 8)	/* toggle dp low  nibble */
+#define	SEVENSEG_TOG_DPH	(int)( 7 << 8)	/* toggle dp high nibble */
+#define	SEVENSEG_LO		(int)( 8 << 8)	/* write out low nibble only */
+#define	SEVENSEG_HI		(int)( 9 << 8)	/* write out high nibble only */
+#define	SEVENSEG_STR		(int)(10 << 8)	/* write out a string */
+
+#define	SEVENSEG_MASK_VAL	(0xff)		/* only used by SEVENSEG_RAW */
+#define	SEVENSEG_MASK_CTRL	(~SEVENSEG_MASK_VAL)
+
+#ifdef	SEVENSEG_DIGIT_HI_LO_EQUAL
+
+#define	SEVENSEG_DIGITS_0	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	)
+#define	SEVENSEG_DIGITS_1	(	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	)
+#define	SEVENSEG_DIGITS_2	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_3	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_4	(	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_5	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_6	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_7	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	)
+#define	SEVENSEG_DIGITS_8	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_9	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_A	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_B	(	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_C	(	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_D	(	SEVENSEG_DIGIT_B	\
+				|	SEVENSEG_DIGIT_C	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_E	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_D	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+#define	SEVENSEG_DIGITS_F	(	SEVENSEG_DIGIT_A	\
+				|	SEVENSEG_DIGIT_E	\
+				|	SEVENSEG_DIGIT_F	\
+				|	SEVENSEG_DIGIT_G	)
+
+#else	/* !SEVENSEG_DIGIT_HI_LO_EQUAL */
+#error SEVENSEG: different pin asssignments not supported
+#endif
+
+void sevenseg_set(int value);
+
+#endif	/* CONFIG_SEVENSEG */
+
+#endif	/* __DK1S10_SEVENSEG_H__ */
diff --git a/board/altera/dk1c20/Makefile b/board/altera/dk1c20/Makefile
new file mode 100755
index 0000000..9182a4e
--- /dev/null
+++ b/board/altera/dk1c20/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o misc.o
+
+SOBJS  = vectors.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/altera/dk1c20/config.mk b/board/altera/dk1c20/config.mk
new file mode 100755
index 0000000..d200715
--- /dev/null
+++ b/board/altera/dk1c20/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2003
+# Psyent Corporation
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x018c0000
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c
new file mode 100755
index 0000000..98ee7a7
--- /dev/null
+++ b/board/altera/dk1c20/dk1c20.c
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * CompactFlash/IDE:
+ * (C) Copyright 2004, Shlomo Kut <skut@vyyo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nios-io.h>
+#if	defined(CONFIG_SEVENSEG)
+#include "../common/sevenseg.h"
+#endif
+
+void _default_hdlr (void)
+{
+	printf ("default_hdlr\n");
+}
+
+int board_early_init_f (void)
+{
+#if	defined(CONFIG_SEVENSEG)
+	/* init seven segment led display and switch off */
+	sevenseg_set(SEVENSEG_OFF);
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Altera Nios 1C20 Development Kit\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+int ide_preinit (void)
+{
+	nios_pio_t *present = (nios_pio_t *) CFG_CF_PRESENT;
+	nios_pio_t *power = (nios_pio_t *) CFG_CF_POWER;
+	nios_pio_t *atasel = (nios_pio_t *) CFG_CF_ATASEL;
+
+	/* setup data direction registers */
+	present->direction = NIOS_PIO_IN;
+	power->direction = NIOS_PIO_OUT;
+	atasel->direction = NIOS_PIO_OUT;
+
+	/* Check for presence of card */
+	if (present->data)
+		return 1;
+	printf ("Ok\n");
+
+	/* Finish setup */
+	power->data = 1;	/* Turn on power FET */
+	atasel->data = 0;	/* Put in ATA mode */
+
+	return 0;
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
diff --git a/board/altera/dk1c20/flash.c b/board/altera/dk1c20/flash.c
new file mode 100755
index 0000000..1f344dd
--- /dev/null
+++ b/board/altera/dk1c20/flash.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+/*
+ * include common flash code (for altera boards)
+ */
+#include "../common/flash.c"
+
+/*----------------------------------------------------------------------*/
+#define BANKSZ		CFG_FLASH_SIZE
+#define SECTSZ		(64 * 1024)
+#define USERFLASH	(2 * 1024 * 1024)	/* bottom 2 MB for user	*/
+
+/*----------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = BANKSZ;
+	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
+
+	addr = CFG_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+
+		/* Protect all but 2 MByte user area */
+		if (addr < (CFG_FLASH_BASE + USERFLASH))
+			fli->protect[i] = 0;
+		else
+			fli->protect[i] = 1;
+	}
+
+	return (BANKSZ);
+}
diff --git a/board/altera/dk1c20/misc.c b/board/altera/dk1c20/misc.c
new file mode 100755
index 0000000..f25cdeb
--- /dev/null
+++ b/board/altera/dk1c20/misc.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * board/altera/dk1s10/misc.c
+ *
+ * miscellaneous board interfaces / drivers
+ */
+
+#include <common.h>
+
+#if	defined(CONFIG_SEVENSEG)
+#include "../common/sevenseg.h"
+#include "../common/sevenseg.c"
+#endif
diff --git a/board/altera/dk1c20/u-boot.lds b/board/altera/dk1c20/u-boot.lds
new file mode 100755
index 0000000..8b01f45
--- /dev/null
+++ b/board/altera/dk1c20/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-nios")
+OUTPUT_ARCH(nios)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios/start.o (.text)
+	  *(.text)
+	}
+	__text_end = .;
+
+	. = ALIGN(4);
+	.rodata :
+	{
+		*(.rodata)
+	}
+	__rodata_end = .;
+
+	. = ALIGN(4);
+	.data :
+	{
+		*(.data)
+	}
+	. = ALIGN(4);
+	__data_end = .;
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	__bss_start = .;
+	. = ALIGN(4);
+	.bss :
+	{
+		*(.bss)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+}
diff --git a/board/altera/dk1c20/vectors.S b/board/altera/dk1c20/vectors.S
new file mode 100755
index 0000000..c83c0e7
--- /dev/null
+++ b/board/altera/dk1c20/vectors.S
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*************************************************************************
+ * Exception Vector Table
+ *
+ * This could have gone in the cpu soure tree, but the whole point of
+ * Nios is customization -- and polluting the cpu source tree with
+ * board-specific ifdef's really defeats the purpose, no? With this in
+ * the board-specific tree, each board has the freedom to organize
+ * vectors/traps, etc anyway it wants. The init code copies this table
+ * to the proper location.
+ *
+ * Each board can do what it likes here. But there are four "standard"
+ * handlers availble:
+ *
+ *	_cwp_lolimit	-Handles register window underflows.
+ *	_cwp_hilimit	-Handles register window overflows.
+ *	_timebase_int	-Increments the timebase.
+ *	_brkpt_hw_int	-Hardware breakpoint handler.
+ *	_brkpt_sw_int	-Software breakpoint handler.
+ *	_def_xhandler	-Default exception handler.
+ *
+ * _timebase_int handles a Nios Timer interrupt and increments the
+ * timestamp used for the get_timer(), reset_timer(), etc. routines. It
+ * expects the timer to be configured like the standard-32 low priority
+ * timer.
+ *
+ * _def_xhandler dispatches exceptions/traps via the external_interrupt()
+ * routine. This lets you use the irq_install_handler() and handle your
+ * interrupts/traps with code written in C.
+ ************************************************************************/
+
+	.data
+	.global _vectors
+	.align	4
+_vectors:
+
+	.long	_def_xhandler@h		/* Vector 0  - NMI */
+	.long	_cwp_lolimit@h		/* Vector 1  -  underflow */
+	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
+	.long	_brkpt_hw_int@h		/* Vector 3 - Breakpoint */
+	.long	_brkpt_sw_int@h		/* Vector 4 - Single step*/
+	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 6 - future reserved */
+	.long	_def_xhandler@h		/* Vector 7 - future reserved */
+	.long	_def_xhandler@h		/* Vector 8 - future reserved */
+	.long	_def_xhandler@h		/* Vector 9 - future reserved */
+	.long	_def_xhandler@h		/* Vector 10 - future reserved */
+	.long	_def_xhandler@h		/* Vector 11 - future reserved */
+	.long	_def_xhandler@h		/* Vector 12 - future reserved */
+	.long	_def_xhandler@h		/* Vector 13 - future reserved */
+	.long	_def_xhandler@h		/* Vector 14 - future reserved */
+	.long	_def_xhandler@h		/* Vector 15 - future reserved */
+	.long	_def_xhandler@h		/* Vector 16 */
+	.long	_def_xhandler@h		/* Vector 17 */
+	.long	_def_xhandler@h		/* Vector 18 */
+	.long	_def_xhandler@h		/* Vector 19 */
+	.long	_def_xhandler@h		/* Vector 20 */
+	.long	_def_xhandler@h		/* Vector 21 */
+	.long	_def_xhandler@h		/* Vector 22 */
+	.long	_def_xhandler@h		/* Vector 23 */
+	.long	_def_xhandler@h		/* Vector 24 */
+	.long	_def_xhandler@h		/* Vector 25 */
+	.long	_def_xhandler@h		/* Vector 26 */
+	.long	_def_xhandler@h		/* Vector 27 */
+	.long	_def_xhandler@h		/* Vector 28 */
+	.long	_def_xhandler@h		/* Vector 29 */
+	.long	_def_xhandler@h		/* Vector 30 */
+	.long	_def_xhandler@h		/* Vector 31 */
+	.long	_def_xhandler@h		/* Vector 32 */
+	.long	_def_xhandler@h		/* Vector 33 */
+	.long	_def_xhandler@h		/* Vector 34 */
+	.long	_def_xhandler@h		/* Vector 35 */
+	.long	_def_xhandler@h		/* Vector 36 */
+	.long	_def_xhandler@h		/* Vector 37 */
+	.long	_def_xhandler@h		/* Vector 38 */
+	.long	_def_xhandler@h		/* Vector 39 */
+	.long	_def_xhandler@h		/* Vector 40 */
+	.long	_def_xhandler@h		/* Vector 41 */
+	.long	_def_xhandler@h		/* Vector 42 */
+	.long	_def_xhandler@h		/* Vector 43 */
+	.long	_def_xhandler@h		/* Vector 44 */
+	.long	_def_xhandler@h		/* Vector 45 */
+	.long	_def_xhandler@h		/* Vector 46 */
+	.long	_def_xhandler@h		/* Vector 47 */
+	.long	_def_xhandler@h		/* Vector 48 */
+	.long	_def_xhandler@h		/* Vector 49 */
+	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
+	.long	_def_xhandler@h		/* Vector 51 */
+	.long	_def_xhandler@h		/* Vector 52 */
+	.long	_def_xhandler@h		/* Vector 53 */
+	.long	_def_xhandler@h		/* Vector 54 */
+	.long	_def_xhandler@h		/* Vector 55 */
+	.long	_def_xhandler@h		/* Vector 56 */
+	.long	_def_xhandler@h		/* Vector 57 */
+	.long	_def_xhandler@h		/* Vector 58 */
+	.long	_def_xhandler@h		/* Vector 59 */
+	.long	_def_xhandler@h		/* Vector 60 */
+	.long	_def_xhandler@h		/* Vector 61 */
+	.long	_def_xhandler@h		/* Vector 62 */
+	.long	_def_xhandler@h		/* Vector 63 */
diff --git a/board/altera/dk1s10/Makefile b/board/altera/dk1s10/Makefile
new file mode 100755
index 0000000..9182a4e
--- /dev/null
+++ b/board/altera/dk1s10/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o misc.o
+
+SOBJS  = vectors.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/altera/dk1s10/config.mk b/board/altera/dk1s10/config.mk
new file mode 100755
index 0000000..d200715
--- /dev/null
+++ b/board/altera/dk1s10/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2003
+# Psyent Corporation
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x018c0000
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/altera/dk1s10/dk1s10.c b/board/altera/dk1s10/dk1s10.c
new file mode 100755
index 0000000..c45e7f1
--- /dev/null
+++ b/board/altera/dk1s10/dk1s10.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if	defined(CONFIG_SEVENSEG)
+#include "../common/sevenseg.h"
+#endif
+
+void _default_hdlr (void)
+{
+	printf ("default_hdlr\n");
+}
+
+int board_early_init_f (void)
+{
+#if	defined(CONFIG_SEVENSEG)
+	/* init seven segment led display and switch off */
+	sevenseg_set(SEVENSEG_OFF);
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Altera Nios 1S10 Development Kit\n");
+#if     defined(CONFIG_NIOS_SAFE_32)
+	puts ("Conf.: Altera Safe 32 (safe_32)\n");
+#elif   defined(CONFIG_NIOS_STANDARD_32)
+	puts ("Conf.: Altera Standard 32 (standard_32)\n");
+#elif   defined(CONFIG_NIOS_MTX_LDK_20)
+	puts ("Conf.: Microtronix LDK 2.0 (LDK2)\n");
+#endif
+
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}
diff --git a/board/altera/dk1s10/flash.c b/board/altera/dk1s10/flash.c
new file mode 100755
index 0000000..5c70933
--- /dev/null
+++ b/board/altera/dk1s10/flash.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+/*
+ * include common flash code (for altera boards)
+ */
+#include "../common/flash.c"
+
+/*---------------------------------------------------------------------*/
+#define BANKSZ	(8 * 1024 * 1024)
+#define SECTSZ	(64 * 1024)
+#define USERFLASH (2 * 1024 * 1024)	/* bottom 2 MB for user */
+
+/*---------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = BANKSZ;
+	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
+
+	addr = CFG_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+
+		/* Protect all but 2 MByte user area */
+		if (addr < (CFG_FLASH_BASE + USERFLASH))
+			fli->protect[i] = 0;
+		else
+			fli->protect[i] = 1;
+	}
+
+	return (BANKSZ);
+}
diff --git a/board/altera/dk1s10/misc.c b/board/altera/dk1s10/misc.c
new file mode 100755
index 0000000..f25cdeb
--- /dev/null
+++ b/board/altera/dk1s10/misc.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * board/altera/dk1s10/misc.c
+ *
+ * miscellaneous board interfaces / drivers
+ */
+
+#include <common.h>
+
+#if	defined(CONFIG_SEVENSEG)
+#include "../common/sevenseg.h"
+#include "../common/sevenseg.c"
+#endif
diff --git a/board/altera/dk1s10/u-boot.lds b/board/altera/dk1s10/u-boot.lds
new file mode 100755
index 0000000..8b01f45
--- /dev/null
+++ b/board/altera/dk1s10/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-nios")
+OUTPUT_ARCH(nios)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios/start.o (.text)
+	  *(.text)
+	}
+	__text_end = .;
+
+	. = ALIGN(4);
+	.rodata :
+	{
+		*(.rodata)
+	}
+	__rodata_end = .;
+
+	. = ALIGN(4);
+	.data :
+	{
+		*(.data)
+	}
+	. = ALIGN(4);
+	__data_end = .;
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	__bss_start = .;
+	. = ALIGN(4);
+	.bss :
+	{
+		*(.bss)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+}
diff --git a/board/altera/dk1s10/vectors.S b/board/altera/dk1s10/vectors.S
new file mode 100755
index 0000000..2f44875
--- /dev/null
+++ b/board/altera/dk1s10/vectors.S
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+
+/*************************************************************************
+ * Exception Vector Table
+ *
+ * This could have gone in the cpu soure tree, but the whole point of
+ * Nios is customization -- and polluting the cpu source tree with
+ * board-specific ifdef's really defeats the purpose, no? With this in
+ * the board-specific tree, each board has the freedom to organize
+ * vectors/traps, etc anyway it wants. The init code copies this table
+ * to the proper location.
+ *
+ * Each board can do what it likes here. But there are four "standard"
+ * handlers availble:
+ *
+ *	_cwp_lolimit	-Handles register window underflows.
+ *	_cwp_hilimit	-Handles register window overflows.
+ *	_timebase_int	-Increments the timebase.
+ *	_def_xhandler	-Default exception handler.
+ *
+ * _timebase_int handles a Nios Timer interrupt and increments the
+ * timestamp used for the get_timer(), reset_timer(), etc. routines. It
+ * expects the timer to be configured like the standard-32 low priority
+ * timer.
+ *
+ * _def_xhandler dispatches exceptions/traps via the external_interrupt()
+ * routine. This lets you use the irq_install_handler() and handle your
+ * interrupts/traps with code written in C.
+ ************************************************************************/
+
+	.data
+	.global _vectors
+	.align	4
+_vectors:
+
+#if	defined(CFG_NIOS_CPU_OCI_BASE)
+	/* OCI does the reset job */
+	.long	_def_xhandler@h		/* Vector 0  - NMI / Reset */
+#else
+	/* there is no OCI, so we have to do a direct reset jump here */
+	.long	CFG_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
+#endif
+	.long	_cwp_lolimit@h		/* Vector 1  - underflow */
+	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
+
+	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 6 - future reserved */
+	.long	_def_xhandler@h		/* Vector 7 - future reserved */
+	.long	_def_xhandler@h		/* Vector 8 - future reserved */
+	.long	_def_xhandler@h		/* Vector 9 - future reserved */
+	.long	_def_xhandler@h		/* Vector 10 - future reserved */
+	.long	_def_xhandler@h		/* Vector 11 - future reserved */
+	.long	_def_xhandler@h		/* Vector 12 - future reserved */
+	.long	_def_xhandler@h		/* Vector 13 - future reserved */
+	.long	_def_xhandler@h		/* Vector 14 - future reserved */
+	.long	_def_xhandler@h		/* Vector 15 - future reserved */
+#if	(CFG_NIOS_TMRIRQ == 16)
+	.long	_timebase_int@h		/* Vector 16 - lopri timer*/
+#else
+	.long	_def_xhandler@h		/* Vector 16 */
+#endif
+	.long	_def_xhandler@h		/* Vector 17 */
+	.long	_def_xhandler@h		/* Vector 18 */
+	.long	_def_xhandler@h		/* Vector 19 */
+	.long	_def_xhandler@h		/* Vector 20 */
+	.long	_def_xhandler@h		/* Vector 21 */
+	.long	_def_xhandler@h		/* Vector 22 */
+	.long	_def_xhandler@h		/* Vector 23 */
+	.long	_def_xhandler@h		/* Vector 24 */
+	.long	_def_xhandler@h		/* Vector 25 */
+	.long	_def_xhandler@h		/* Vector 26 */
+	.long	_def_xhandler@h		/* Vector 27 */
+	.long	_def_xhandler@h		/* Vector 28 */
+	.long	_def_xhandler@h		/* Vector 29 */
+	.long	_def_xhandler@h		/* Vector 30 */
+	.long	_def_xhandler@h		/* Vector 31 */
+	.long	_def_xhandler@h		/* Vector 32 */
+	.long	_def_xhandler@h		/* Vector 33 */
+	.long	_def_xhandler@h		/* Vector 34 */
+	.long	_def_xhandler@h		/* Vector 35 */
+	.long	_def_xhandler@h		/* Vector 36 */
+	.long	_def_xhandler@h		/* Vector 37 */
+	.long	_def_xhandler@h		/* Vector 38 */
+	.long	_def_xhandler@h		/* Vector 39 */
+	.long	_def_xhandler@h		/* Vector 40 */
+	.long	_def_xhandler@h		/* Vector 41 */
+	.long	_def_xhandler@h		/* Vector 42 */
+	.long	_def_xhandler@h		/* Vector 43 */
+	.long	_def_xhandler@h		/* Vector 44 */
+	.long	_def_xhandler@h		/* Vector 45 */
+	.long	_def_xhandler@h		/* Vector 46 */
+	.long	_def_xhandler@h		/* Vector 47 */
+	.long	_def_xhandler@h		/* Vector 48 */
+	.long	_def_xhandler@h		/* Vector 49 */
+#if	(CFG_NIOS_TMRIRQ == 50)
+	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
+#else
+	.long	_def_xhandler@h		/* Vector 50 */
+#endif
+	.long	_def_xhandler@h		/* Vector 51 */
+	.long	_def_xhandler@h		/* Vector 52 */
+	.long	_def_xhandler@h		/* Vector 53 */
+	.long	_def_xhandler@h		/* Vector 54 */
+	.long	_def_xhandler@h		/* Vector 55 */
+	.long	_def_xhandler@h		/* Vector 56 */
+	.long	_def_xhandler@h		/* Vector 57 */
+	.long	_def_xhandler@h		/* Vector 58 */
+	.long	_def_xhandler@h		/* Vector 59 */
+	.long	_def_xhandler@h		/* Vector 60 */
+	.long	_def_xhandler@h		/* Vector 61 */
+	.long	_def_xhandler@h		/* Vector 62 */
+	.long	_def_xhandler@h		/* Vector 63 */
diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile
new file mode 100755
index 0000000..5654f91
--- /dev/null
+++ b/board/amcc/bamboo/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+OBJS   += flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
new file mode 100755
index 0000000..803995a
--- /dev/null
+++ b/board/amcc/bamboo/bamboo.c
@@ -0,0 +1,2089 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <ppc440.h>
+#include "bamboo.h"
+
+void ext_bus_cntlr_init(void);
+void configure_ppc440ep_pins(void);
+int is_nand_selected(void);
+
+unsigned char cfg_simulate_spd_eeprom[128];
+
+gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
+#if 0
+{	   /* GPIO   Alternate1	      Alternate2	Alternate3 */
+    {
+	/* GPIO Core 0 */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0	-> EBC_ADDR(7)	    DMA_REQ(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1	-> EBC_ADDR(6)	    DMA_ACK(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2	-> EBC_ADDR(5)	    DMA_EOT/TC(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3	-> EBC_ADDR(4)	    DMA_REQ(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4	-> EBC_ADDR(3)	    DMA_ACK(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6	-> EBC_CS_N(1) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7	-> EBC_CS_N(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8	-> EBC_CS_N(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9	 -> EBC_CS_N(4) */
+	{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->		    USB2D_RXVALID */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ	    USB2D_RXERROR */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->		    USB2D_TXVALID */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA	    USB2D_PAD_SUSPNDM */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK	    USB2D_XCVRSELECT */
+	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
+    },
+    {
+	/* GPIO Core 1 */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0	-> USB2D_OPMODE0 */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1	-> USB2D_OPMODE1 */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2	-> UART0_DCD_N	    UART1_DSR_CTS_N   UART2_SOUT */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3	-> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4	-> UART0_8PIN_CTS_N		      UART3_SIN */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5	-> UART0_RTS_N */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6	-> UART0_DTR_N	    UART1_SOUT */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7	-> UART0_RI_N	    UART1_SIN */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8	-> UIC_IRQ(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9	-> UIC_IRQ(1) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)	    DMA_ACK(1) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)	    DMA_EOT/TC(1) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)	    DMA_REQ(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)	    DMA_ACK(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)	    DMA_EOT/TC(0) */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \	   Can be unselected thru TraceSelect Bit */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /	      in PowerPC440EP Chip */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
+	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
+    }
+};
+#endif
+
+/*----------------------------------------------------------------------------+
+  | EBC Devices Characteristics
+  |   Peripheral Bank Access Parameters	      -	  EBC0_BnAP
+  |   Peripheral Bank Configuration Register  -	  EBC0_BnCR
+  +----------------------------------------------------------------------------*/
+/* Small Flash */
+#define EBC0_BNAP_SMALL_FLASH				\
+	EBC0_BNAP_BME_DISABLED			|	\
+	EBC0_BNAP_TWT_ENCODE(6)			|	\
+	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
+	EBC0_BNAP_OEN_ENCODE(1)	    		|	\
+	EBC0_BNAP_WBN_ENCODE(1)	    		|	\
+	EBC0_BNAP_WBF_ENCODE(3)	    		|	\
+	EBC0_BNAP_TH_ENCODE(1)	    		|	\
+	EBC0_BNAP_RE_ENABLED	    		|	\
+	EBC0_BNAP_SOR_DELAYED	    		|	\
+	EBC0_BNAP_BEM_WRITEONLY	    		|	\
+	EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_SMALL_FLASH_CS0			\
+	EBC0_BNCR_BAS_ENCODE(0xFFF00000)    	| 	\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BW_8BIT
+
+#define EBC0_BNCR_SMALL_FLASH_CS4			\
+	EBC0_BNCR_BAS_ENCODE(0x87F00000)    	| 	\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BW_8BIT
+
+/* Large Flash or SRAM */
+#define EBC0_BNAP_LARGE_FLASH_OR_SRAM			\
+	EBC0_BNAP_BME_DISABLED	    		|	\
+	EBC0_BNAP_TWT_ENCODE(8)	    		|	\
+	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
+	EBC0_BNAP_OEN_ENCODE(1)	    		|	\
+	EBC0_BNAP_WBN_ENCODE(1)	    		|	\
+	EBC0_BNAP_WBF_ENCODE(1)	    		|	\
+	EBC0_BNAP_TH_ENCODE(2)	    		|	\
+	EBC0_BNAP_SOR_DELAYED	    		|	\
+	EBC0_BNAP_BEM_RW	    		|	\
+	EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0   		\
+	EBC0_BNCR_BAS_ENCODE(0xFF800000)	| 	\
+	EBC0_BNCR_BS_8MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BW_16BIT
+
+
+#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4   		\
+	EBC0_BNCR_BAS_ENCODE(0x87800000)	| 	\
+	EBC0_BNCR_BS_8MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BW_16BIT
+
+/* NVRAM - FPGA */
+#define EBC0_BNAP_NVRAM_FPGA				\
+	EBC0_BNAP_BME_DISABLED	    		|	\
+	EBC0_BNAP_TWT_ENCODE(9)	    		|	\
+	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
+	EBC0_BNAP_OEN_ENCODE(1)	    		|	\
+	EBC0_BNAP_WBN_ENCODE(1)	    		|	\
+	EBC0_BNAP_WBF_ENCODE(0)	    		|	\
+	EBC0_BNAP_TH_ENCODE(2)	    		|	\
+	EBC0_BNAP_RE_ENABLED	    		|	\
+	EBC0_BNAP_SOR_DELAYED	    		|	\
+	EBC0_BNAP_BEM_WRITEONLY	    		|	\
+	EBC0_BNAP_PEN_DISABLED
+
+#define EBC0_BNCR_NVRAM_FPGA_CS5			\
+	EBC0_BNCR_BAS_ENCODE(0x80000000)    	| 	\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BW_8BIT
+
+/* Nand Flash */
+#define EBC0_BNAP_NAND_FLASH				\
+	EBC0_BNAP_BME_DISABLED	    		|	\
+	EBC0_BNAP_TWT_ENCODE(3)	    		|	\
+	EBC0_BNAP_CSN_ENCODE(0)	    		|	\
+	EBC0_BNAP_OEN_ENCODE(0)	    		|	\
+	EBC0_BNAP_WBN_ENCODE(0)	    		|	\
+	EBC0_BNAP_WBF_ENCODE(0)	    		|	\
+	EBC0_BNAP_TH_ENCODE(1)	    		|	\
+	EBC0_BNAP_RE_ENABLED	    		|	\
+	EBC0_BNAP_SOR_NOT_DELAYED   		|	\
+	EBC0_BNAP_BEM_RW	    		|	\
+	EBC0_BNAP_PEN_DISABLED
+
+
+#define EBC0_BNCR_NAND_FLASH_CS0	0xB8400000
+
+/* NAND0 */
+#define EBC0_BNCR_NAND_FLASH_CS1			\
+	EBC0_BNCR_BAS_ENCODE(0x90000000)    	| 	\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BW_32BIT
+/* NAND1 - Bank2 */
+#define EBC0_BNCR_NAND_FLASH_CS2			\
+	EBC0_BNCR_BAS_ENCODE(0x94000000)    	| 	\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BW_32BIT
+
+/* NAND1 - Bank3 */
+#define EBC0_BNCR_NAND_FLASH_CS3			\
+	EBC0_BNCR_BAS_ENCODE(0x94000000)    	| 	\
+	EBC0_BNCR_BS_1MB		    	|	\
+	EBC0_BNCR_BU_RW			    	|	\
+	EBC0_BNCR_BW_32BIT
+
+int board_early_init_f(void)
+{
+	ext_bus_cntlr_init();
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	/*--------------------------------------------------------------------
+	 * Setup the GPIO pins
+	 *-------------------------------------------------------------------*/
+	out32(GPIO0_OSRL,  0x00000400);
+	out32(GPIO0_OSRH,  0x00000000);
+	out32(GPIO0_TSRL,  0x00000400);
+	out32(GPIO0_TSRH,  0x00000000);
+	out32(GPIO0_ISR1L, 0x00000000);
+	out32(GPIO0_ISR1H, 0x00000000);
+	out32(GPIO0_ISR2L, 0x00000000);
+	out32(GPIO0_ISR2H, 0x00000000);
+	out32(GPIO0_ISR3L, 0x00000000);
+	out32(GPIO0_ISR3H, 0x00000000);
+
+	out32(GPIO1_OSRL,  0x0C380000);
+	out32(GPIO1_OSRH,  0x00000000);
+	out32(GPIO1_TSRL,  0x0C380000);
+	out32(GPIO1_TSRH,  0x00000000);
+	out32(GPIO1_ISR1L, 0x0FC30000);
+	out32(GPIO1_ISR1H, 0x00000000);
+	out32(GPIO1_ISR2L, 0x0C010000);
+	out32(GPIO1_ISR2H, 0x00000000);
+	out32(GPIO1_ISR3L, 0x01400000);
+	out32(GPIO1_ISR3H, 0x00000000);
+
+	configure_ppc440ep_pins();
+
+	return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+/*----------------------------------------------------------------------------+
+  | nand_reset.
+  |   Reset Nand flash
+  |   This routine will abort previous cmd
+  +----------------------------------------------------------------------------*/
+int nand_reset(ulong addr)
+{
+	int wait=0, stat=0;
+
+	out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
+	out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
+
+	while ((stat != 0xc0) && (wait != 0xffff)) {
+		stat = in8(addr + NAND_DATA_REG);
+		wait++;
+	}
+
+	if (stat == 0xc0) {
+		return 0;
+	} else {
+		printf("NAND Reset timeout.\n");
+		return -1;
+	}
+}
+
+void board_nand_set_device(int cs, ulong addr)
+{
+	/* Set NandFlash Core Configuration Register */
+	out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
+
+	switch (cs) {
+	case 1:
+		/* -------
+		 *  NAND0
+		 * -------
+		 * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
+		 * Set NDF1CR - Enable External CS1 in NAND FLASH controller
+		 */
+		out32(addr + NAND_CR1_REG, 0x80002222);
+		break;
+
+	case 2:
+		/* -------
+		 *  NAND1
+		 * -------
+		 * K9K2G0B : 5 addr cyc, 2 col + 3 Row
+		 * Set NDF2CR : Enable External CS2 in NAND FLASH controller
+		 */
+		out32(addr + NAND_CR2_REG, 0xC0007777);
+		break;
+	}
+
+	/* Perform Reset Command */
+	if (nand_reset(addr) != 0)
+		return;
+}
+
+void nand_init(void)
+{
+	board_nand_set_device(1, CFG_NAND_ADDR);
+
+	nand_probe(CFG_NAND_ADDR);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+
+#if 0 /* NAND1 not supported yet */
+	board_nand_set_device(2, CFG_NAND2_ADDR);
+
+	nand_probe(CFG_NAND2_ADDR);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+#endif
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+/*************************************************************************
+ *
+ * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
+ *
+ * Fixed memory is composed of :
+ *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
+ *	13 row add bits, 10 column add bits (but 12 row used only).
+ *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
+ *	12 row add bits, 10 column add bits.
+ *	Prepare a subset (only the used ones) of SPD data
+ *
+ *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
+ *	the corresponding bank is divided by 2 due to number of Row addresses
+ *	12 in the ECC module
+ *
+ *  Assumes:	64 MB, ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+static void init_spd_array(void)
+{
+	cfg_simulate_spd_eeprom[8]     = 0x04;    /* 2.5 Volt */
+	cfg_simulate_spd_eeprom[2]     = 0x07;    /* DDR ram */
+
+#ifdef CONFIG_DDR_ECC
+	cfg_simulate_spd_eeprom[11]    = 0x02;    /* ECC ON : 02 OFF : 00 */
+	cfg_simulate_spd_eeprom[31]    = 0x08;    /* bankSizeID: 32MB */
+	cfg_simulate_spd_eeprom[3]     = 0x0C;    /* num Row Addr: 12 */
+#else
+	cfg_simulate_spd_eeprom[11]    = 0x00;    /* ECC ON : 02 OFF : 00 */
+	cfg_simulate_spd_eeprom[31]    = 0x10;    /* bankSizeID: 64MB */
+	cfg_simulate_spd_eeprom[3]     = 0x0D;    /* num Row Addr: 13 */
+#endif
+
+	cfg_simulate_spd_eeprom[4]     = 0x09;    /* numColAddr: 9  */
+	cfg_simulate_spd_eeprom[5]     = 0x01;    /* numBanks: 1 */
+	cfg_simulate_spd_eeprom[0]     = 0x80;    /* number of SPD bytes used: 128 */
+	cfg_simulate_spd_eeprom[1]     = 0x08;    /*  total number bytes in SPD device = 256 */
+	cfg_simulate_spd_eeprom[21]    = 0x00;    /* not registered: 0  registered : 0x02*/
+	cfg_simulate_spd_eeprom[6]     = 0x20;    /* Module data width: 32 bits */
+	cfg_simulate_spd_eeprom[7]     = 0x00;    /* Module data width continued: +0 */
+	cfg_simulate_spd_eeprom[15]    = 0x01;    /* wcsbc = 1 */
+	cfg_simulate_spd_eeprom[27]    = 0x50;    /* tRpNs = 20 ns  */
+	cfg_simulate_spd_eeprom[29]    = 0x50;    /* tRcdNs = 20 ns */
+
+	cfg_simulate_spd_eeprom[30]    = 45;      /* tRasNs */
+
+	cfg_simulate_spd_eeprom[18]    = 0x0C;    /* casBit (2,2.5) */
+
+	cfg_simulate_spd_eeprom[9]     = 0x75;    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
+	cfg_simulate_spd_eeprom[23]    = 0xA0;    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
+	cfg_simulate_spd_eeprom[25]    = 0x00;    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
+	cfg_simulate_spd_eeprom[12]    = 0x82;    /* refresh Rate Type: Normal (15.625us) + Self refresh */
+}
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+	/*
+	 * First write simulated values in eeprom array for onboard bank 0
+	 */
+	init_spd_array();
+
+	dram_size = spd_sdram (0);
+
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_KBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long addr;
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB3 devices to 0.
+	  | Set PLB3 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp1, addr);
+	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb3_acr);
+	mtdcr(plb3_acr, addr | 0x80000000);
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB4 devices to 0.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp0, addr);
+	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(plb4_acr, addr);
+
+	/*-------------------------------------------------------------------------+
+	  | Set Nebula PLB4 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	/* Segment0 */
+	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+	mtdcr(plb0_acr, addr);
+
+	/* Segment1 */
+	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+	mtdcr(plb1_acr, addr);
+
+	return 1;
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	 * Set up Direct MMIO registers
+	 *--------------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440 EP PCI Master configuration.
+	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+
+	/*--------------------------------------------------------------------------+
+	 * Set up Configuration registers
+	 *--------------------------------------------------------------------------*/
+
+	/* Program the board's subsystem id/vendor id */
+	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+			      CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+	/* Configure command register as bus master */
+	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+	/* 240nS PCI clock */
+	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_write_config_word(0, PCI_ERREN, 0);
+
+	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	unsigned short temp_short;
+
+	/*--------------------------------------------------------------------------+
+	  | Write the PowerPC440 EP PCI Configuration regs.
+	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
+	  +--------------------------------------------------------------------------*/
+	pci_read_config_word(0, PCI_COMMAND, &temp_short);
+	pci_write_config_word(0, PCI_COMMAND,
+			      temp_short | PCI_COMMAND_MASTER |
+			      PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* Bamboo is always configured as host. */
+	return (1);
+}
+#endif				/* defined(CONFIG_PCI) */
+
+/*----------------------------------------------------------------------------+
+  | is_powerpc440ep_pass1.
+  +----------------------------------------------------------------------------*/
+int is_powerpc440ep_pass1(void)
+{
+	unsigned long pvr;
+
+	pvr = get_pvr();
+
+	if (pvr == PVR_POWERPC_440EP_PASS1)
+		return TRUE;
+	else if (pvr == PVR_POWERPC_440EP_PASS2)
+		return FALSE;
+	else {
+		printf("brdutil error 3\n");
+		for (;;)
+			;
+	}
+
+	return(FALSE);
+}
+
+/*----------------------------------------------------------------------------+
+  | is_nand_selected.
+  +----------------------------------------------------------------------------*/
+int is_nand_selected(void)
+{
+#ifdef CONFIG_BAMBOO_NAND
+	return TRUE;
+#else
+	return FALSE;
+#endif
+}
+
+/*----------------------------------------------------------------------------+
+  | config_on_ebc_cs4_is_small_flash => from EPLD
+  +----------------------------------------------------------------------------*/
+unsigned char config_on_ebc_cs4_is_small_flash(void)
+{
+	/* Not implemented yet => returns constant value */
+	return TRUE;
+}
+
+/*----------------------------------------------------------------------------+
+  | Ext_bus_cntlr_init.
+  | Initialize the external bus controller
+  +----------------------------------------------------------------------------*/
+void ext_bus_cntlr_init(void)
+{
+	unsigned long sdr0_pstrp0, sdr0_sdstp1;
+	unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
+	int	      computed_boot_device = BOOT_DEVICE_UNKNOWN;
+	unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
+	unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
+	unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
+	unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
+	unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
+
+
+	/*-------------------------------------------------------------------------+
+	  |
+	  |  PART 1 : Initialize EBC Bank 5
+	  |  ==============================
+	  | Bank5 is always associated to the NVRAM/EPLD.
+	  | It has to be initialized prior to other banks settings computation since
+	  | some board registers values may be needed
+	  |
+	  +-------------------------------------------------------------------------*/
+	/* NVRAM - FPGA */
+	mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
+	mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
+
+	/*-------------------------------------------------------------------------+
+	  |
+	  |  PART 2 : Determine which boot device was selected
+	  |  =========================================
+	  |
+	  |  Read Pin Strap Register in PPC440EP
+	  |  In case of boot from IIC, read Serial Device Strap Register1
+	  |
+	  |  Result can either be :
+	  |   - Boot from EBC 8bits    => SMALL FLASH
+	  |   - Boot from EBC 16bits   => Large Flash or SRAM
+	  |   - Boot from NAND Flash
+	  |   - Boot from PCI
+	  |
+	  +-------------------------------------------------------------------------*/
+	/* Read Pin Strap Register in PPC440EP */
+	mfsdr(sdr_pstrp0, sdr0_pstrp0);
+	bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
+
+	/*-------------------------------------------------------------------------+
+	  |  PPC440EP Pass1
+	  +-------------------------------------------------------------------------*/
+	if (is_powerpc440ep_pass1() == TRUE) {
+		switch(bootstrap_settings) {
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+			/* Boot from Small Flash */
+			computed_boot_device = BOOT_FROM_SMALL_FLASH;
+			break;
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+			/* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
+			/* Boot from PCI */
+			computed_boot_device = BOOT_FROM_PCI;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+			/* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
+			/* Boot from Nand Flash */
+			computed_boot_device = BOOT_FROM_NAND_FLASH0;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+			/* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
+			/* Boot from Small Flash */
+			computed_boot_device = BOOT_FROM_SMALL_FLASH;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+			/* Read Serial Device Strap Register1 in PPC440EP */
+			mfsdr(sdr_sdstp1, sdr0_sdstp1);
+			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+			switch(boot_selection) {
+			case SDR0_SDSTP1_BOOT_SEL_EBC:
+				switch(ebc_boot_size) {
+				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+					break;
+				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+					computed_boot_device = BOOT_FROM_SMALL_FLASH;
+					break;
+				}
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_PCI:
+				computed_boot_device = BOOT_FROM_PCI;
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_NDFC:
+				computed_boot_device = BOOT_FROM_NAND_FLASH0;
+				break;
+			}
+			break;
+		}
+	}
+
+	/*-------------------------------------------------------------------------+
+	  |  PPC440EP Pass2
+	  +-------------------------------------------------------------------------*/
+	else {
+		switch(bootstrap_settings) {
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
+			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
+			/* Boot from Small Flash */
+			computed_boot_device = BOOT_FROM_SMALL_FLASH;
+			break;
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
+			/* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
+			/* Boot from PCI */
+			computed_boot_device = BOOT_FROM_PCI;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
+			/* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
+			/* Boot from Nand Flash */
+			computed_boot_device = BOOT_FROM_NAND_FLASH0;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
+			/* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
+			/* Boot from Large Flash or SRAM */
+			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
+			/* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
+			/* Boot from Large Flash or SRAM */
+			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
+			/* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
+			/* Boot from PCI */
+			computed_boot_device = BOOT_FROM_PCI;
+			break;
+
+		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
+		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
+			/* Default Strap Settings 5-7 */
+			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
+			/* Read Serial Device Strap Register1 in PPC440EP */
+			mfsdr(sdr_sdstp1, sdr0_sdstp1);
+			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
+			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+			switch(boot_selection) {
+			case SDR0_SDSTP1_BOOT_SEL_EBC:
+				switch(ebc_boot_size) {
+				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
+					break;
+				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+					computed_boot_device = BOOT_FROM_SMALL_FLASH;
+					break;
+				}
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_PCI:
+				computed_boot_device = BOOT_FROM_PCI;
+				break;
+
+			case SDR0_SDSTP1_BOOT_SEL_NDFC:
+				computed_boot_device = BOOT_FROM_NAND_FLASH0;
+				break;
+			}
+			break;
+		}
+	}
+
+	/*-------------------------------------------------------------------------+
+	  |
+	  |  PART 3 : Compute EBC settings depending on selected boot device
+	  |  ======   ======================================================
+	  |
+	  | Resulting EBC init will be among following configurations :
+	  |
+	  |  - Boot from EBC 8bits => boot from SMALL FLASH selected
+	  |	       EBC-CS0	   = Small Flash
+	  |	       EBC-CS1,2,3 = NAND Flash or
+	  |			    Exp.Slot depending on Soft Config
+	  |	       EBC-CS4	   = SRAM/Large Flash or
+	  |			    Large Flash/SRAM depending on jumpers
+	  |	       EBC-CS5	   = NVRAM / EPLD
+	  |
+	  |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected
+	  |	       EBC-CS0	   = SRAM/Large Flash or
+	  |			     Large Flash/SRAM depending on jumpers
+	  |	       EBC-CS1,2,3 = NAND Flash or
+	  |			     Exp.Slot depending on Software Configuration
+	  |	       EBC-CS4	   = Small Flash
+	  |	       EBC-CS5	   = NVRAM / EPLD
+	  |
+	  |  - Boot from NAND Flash
+	  |	       EBC-CS0	   = NAND Flash0
+	  |	       EBC-CS1,2,3 = NAND Flash1
+	  |	       EBC-CS4	   = SRAM/Large Flash or
+	  |			     Large Flash/SRAM depending on jumpers
+	  |	       EBC-CS5	   = NVRAM / EPLD
+	  |
+	  |    - Boot from PCI
+	  |	       EBC-CS0	   = ...
+	  |	       EBC-CS1,2,3 = NAND Flash or
+	  |			     Exp.Slot depending on Software Configuration
+	  |	       EBC-CS4	   = SRAM/Large Flash or
+	  |			     Large Flash/SRAM or
+	  |			     Small Flash depending on jumpers
+	  |	       EBC-CS5	   = NVRAM / EPLD
+	  |
+	  +-------------------------------------------------------------------------*/
+
+	switch(computed_boot_device) {
+		/*------------------------------------------------------------------------- */
+	case BOOT_FROM_SMALL_FLASH:
+		/*------------------------------------------------------------------------- */
+		ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
+		ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
+		if ((is_nand_selected()) == TRUE) {
+			/* NAND Flash */
+			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+			ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
+			ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		} else {
+			/* Expansion Slot */
+			ebc0_cs1_bnap_value = 0;
+			ebc0_cs1_bncr_value = 0;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		}
+		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+		break;
+
+		/*------------------------------------------------------------------------- */
+	case BOOT_FROM_LARGE_FLASH_OR_SRAM:
+		/*------------------------------------------------------------------------- */
+		ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+		ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
+		if ((is_nand_selected()) == TRUE) {
+			/* NAND Flash */
+			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		} else {
+			/* Expansion Slot */
+			ebc0_cs1_bnap_value = 0;
+			ebc0_cs1_bncr_value = 0;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		}
+		ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+		ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+
+		break;
+
+		/*------------------------------------------------------------------------- */
+	case BOOT_FROM_NAND_FLASH0:
+		/*------------------------------------------------------------------------- */
+		ebc0_cs0_bnap_value = 0;
+		ebc0_cs0_bncr_value = 0;
+
+		ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+		ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+		ebc0_cs2_bnap_value = 0;
+		ebc0_cs2_bncr_value = 0;
+		ebc0_cs3_bnap_value = 0;
+		ebc0_cs3_bncr_value = 0;
+
+		/* Large Flash or SRAM */
+		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+
+		break;
+
+		/*------------------------------------------------------------------------- */
+	case BOOT_FROM_PCI:
+		/*------------------------------------------------------------------------- */
+		ebc0_cs0_bnap_value = 0;
+		ebc0_cs0_bncr_value = 0;
+
+		if ((is_nand_selected()) == TRUE) {
+			/* NAND Flash */
+			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
+			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		} else {
+			/* Expansion Slot */
+			ebc0_cs1_bnap_value = 0;
+			ebc0_cs1_bncr_value = 0;
+			ebc0_cs2_bnap_value = 0;
+			ebc0_cs2_bncr_value = 0;
+			ebc0_cs3_bnap_value = 0;
+			ebc0_cs3_bncr_value = 0;
+		}
+
+		if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
+			/* Small Flash */
+			ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
+			ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
+		} else {
+			/* Large Flash or SRAM */
+			ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
+			ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
+		}
+
+		break;
+
+		/*------------------------------------------------------------------------- */
+	case BOOT_DEVICE_UNKNOWN:
+		/*------------------------------------------------------------------------- */
+		/* Error */
+		break;
+
+	}
+
+
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------------*/
+	mtdcr(ebccfga, xbcfg);
+	mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN	   |
+	      EBC0_CFG_PTD_ENABLED	  |
+	      EBC0_CFG_RTC_2048PERCLK	  |
+	      EBC0_CFG_EMPL_LOW		  |
+	      EBC0_CFG_EMPH_LOW		  |
+	      EBC0_CFG_CSTC_DRIVEN	  |
+	      EBC0_CFG_BPF_ONEDW	  |
+	      EBC0_CFG_EMS_8BIT		  |
+	      EBC0_CFG_PME_DISABLED	  |
+	      EBC0_CFG_PMT_ENCODE(0)	  );
+
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC Bank 0-4
+	  +-------------------------------------------------------------------------*/
+	/* EBC Bank0 */
+	mtebc(pb0ap, ebc0_cs0_bnap_value);
+	mtebc(pb0cr, ebc0_cs0_bncr_value);
+	/* EBC Bank1 */
+	mtebc(pb1ap, ebc0_cs1_bnap_value);
+	mtebc(pb1cr, ebc0_cs1_bncr_value);
+	/* EBC Bank2 */
+	mtebc(pb2ap, ebc0_cs2_bnap_value);
+	mtebc(pb2cr, ebc0_cs2_bncr_value);
+	/* EBC Bank3 */
+	mtebc(pb3ap, ebc0_cs3_bnap_value);
+	mtebc(pb3cr, ebc0_cs3_bncr_value);
+	/* EBC Bank4 */
+	mtebc(pb4ap, ebc0_cs4_bnap_value);
+	mtebc(pb4cr, ebc0_cs4_bncr_value);
+
+	return;
+}
+
+
+/*----------------------------------------------------------------------------+
+  | get_uart_configuration.
+  +----------------------------------------------------------------------------*/
+uart_config_nb_t get_uart_configuration(void)
+{
+	return (L4);
+}
+
+/*----------------------------------------------------------------------------+
+  | set_phy_configuration_through_fpga => to EPLD
+  +----------------------------------------------------------------------------*/
+void set_phy_configuration_through_fpga(zmii_config_t config)
+{
+
+	unsigned long fpga_selection_reg;
+
+	fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
+
+	switch(config)
+	{
+	case ZMII_CONFIGURATION_IS_MII:
+		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
+		break;
+	case ZMII_CONFIGURATION_IS_RMII:
+		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
+		break;
+	case ZMII_CONFIGURATION_IS_SMII:
+		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
+		break;
+	case ZMII_CONFIGURATION_UNKNOWN:
+	default:
+		break;
+	}
+	out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
+
+}
+
+/*----------------------------------------------------------------------------+
+  | scp_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void scp_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | iic1_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void iic1_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
+	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | dma_a_b_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void dma_a_b_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | dma_a_b_unselect_in_fpga.
+  +----------------------------------------------------------------------------*/
+void dma_a_b_unselect_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | dma_c_d_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void dma_c_d_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | dma_c_d_unselect_in_fpga.
+  +----------------------------------------------------------------------------*/
+void dma_c_d_unselect_in_fpga(void)
+{
+	unsigned long fpga_selection_2_reg;
+
+	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
+	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | usb2_device_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void usb2_device_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_1_reg;
+
+	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
+	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | usb2_device_reset_through_fpga.
+  +----------------------------------------------------------------------------*/
+void usb2_device_reset_through_fpga(void)
+{
+	/* Perform soft Reset pulse */
+	unsigned long fpga_reset_reg;
+	int i;
+
+	fpga_reset_reg = in8(FPGA_RESET_REG);
+	out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
+	for (i=0; i<500; i++)
+		udelay(1000);
+	out8(FPGA_RESET_REG,fpga_reset_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | usb2_host_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void usb2_host_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_1_reg;
+
+	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
+	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | ndfc_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void ndfc_selection_in_fpga(void)
+{
+	unsigned long fpga_selection_1_reg;
+
+	fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
+	fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
+	fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
+	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
+}
+
+/*----------------------------------------------------------------------------+
+  | uart_selection_in_fpga.
+  +----------------------------------------------------------------------------*/
+void uart_selection_in_fpga(uart_config_nb_t uart_config)
+{
+	/* FPGA register */
+	unsigned char	fpga_selection_3_reg;
+
+	/* Read FPGA Reagister */
+	fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
+
+	switch (uart_config)
+	{
+	case L1:
+		/* ----------------------------------------------------------------------- */
+		/* L1 configuration:	UART0 = 8 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Configure FPGA */
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
+		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+		break;
+
+	case L2:
+		/* ----------------------------------------------------------------------- */
+		/* L2 configuration:	UART0 = 4 pins */
+		/*			UART1 = 4 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Configure FPGA */
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
+		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+		break;
+
+	case L3:
+		/* ----------------------------------------------------------------------- */
+		/* L3 configuration:	UART0 = 4 pins */
+		/*			UART1 = 2 pins */
+		/*			UART2 = 2 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Configure FPGA */
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
+		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+		break;
+
+	case L4:
+		/* Configure FPGA */
+		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
+		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
+		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
+
+		break;
+
+	default:
+		/* Unsupported UART configuration number */
+		for (;;)
+			;
+		break;
+
+	}
+}
+
+
+/*----------------------------------------------------------------------------+
+  | init_default_gpio
+  +----------------------------------------------------------------------------*/
+void init_default_gpio(void)
+{
+	int i;
+
+	/* Init GPIO0 */
+	for(i=0; i<GPIO_MAX; i++)
+	{
+		gpio_tab[GPIO0][i].add	  = GPIO0_BASE;
+		gpio_tab[GPIO0][i].in_out = GPIO_DIS;
+		gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
+	}
+
+	/* Init GPIO1 */
+	for(i=0; i<GPIO_MAX; i++)
+	{
+		gpio_tab[GPIO1][i].add	  = GPIO1_BASE;
+		gpio_tab[GPIO1][i].in_out = GPIO_DIS;
+		gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
+	}
+
+	/* EBC_CS_N(5) - GPIO0_10 */
+	gpio_tab[GPIO0][10].in_out    = GPIO_OUT;
+	gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;
+
+	/* EBC_CS_N(4) - GPIO0_9 */
+	gpio_tab[GPIO0][9].in_out    = GPIO_OUT;
+	gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_uart_ios
+  +------------------------------------------------------------------------------
+  |
+  | Set UART Configuration in PowerPC440EP
+  |
+  | +---------------------------------------------------------------------+
+  | | Configuartion   |	  Connector   | Nb of pins | Pins   | Associated  |
+  | |	 Number	      |	  Port Name   |	 available | naming |	CORE	  |
+  | +-----------------+---------------+------------+--------+-------------+
+  | |	  L1	      |	  Port_A      |	    8	   | UART   | UART core 0 |
+  | +-----------------+---------------+------------+--------+-------------+
+  | |	  L2	      |	  Port_A      |	    4	   | UART1  | UART core 0 |
+  | |	 (L2D)	      |	  Port_B      |	    4	   | UART2  | UART core 1 |
+  | +-----------------+---------------+------------+--------+-------------+
+  | |	  L3	      |	  Port_A      |	    4	   | UART1  | UART core 0 |
+  | |	 (L3D)	      |	  Port_B      |	    2	   | UART2  | UART core 1 |
+  | |		      |	  Port_C      |	    2	   | UART3  | UART core 2 |
+  | +-----------------+---------------+------------+--------+-------------+
+  | |		      |	  Port_A      |	    2	   | UART1  | UART core 0 |
+  | |	  L4	      |	  Port_B      |	    2	   | UART2  | UART core 1 |
+  | |	 (L4D)	      |	  Port_C      |	    2	   | UART3  | UART core 2 |
+  | |		      |	  Port_D      |	    2	   | UART4  | UART core 3 |
+  | +-----------------+---------------+------------+--------+-------------+
+  |
+  |  Involved GPIOs
+  |
+  | +------------------------------------------------------------------------------+
+  | |  GPIO   |	  Aternate 1	 | I/O |  Alternate 2	 | I/O | Alternate 3 | I/O |
+  | +---------+------------------+-----+-----------------+-----+-------------+-----+
+  | | GPIO1_2 | UART0_DCD_N	 |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |	O  |
+  | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |	I  |
+  | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA		 |  NA | UART3_SIN   |	I  |
+  | | GPIO1_5 | UART0_RTS_N	 |  O  | NA		 |  NA | UART3_SOUT  |	O  |
+  | | GPIO1_6 | UART0_DTR_N	 |  O  | UART1_SOUT	 |  O  | NA	     |	NA |
+  | | GPIO1_7 | UART0_RI_N	 |  I  | UART1_SIN	 |  I  | NA	     |	NA |
+  | +------------------------------------------------------------------------------+
+  |
+  |
+  +----------------------------------------------------------------------------*/
+
+void update_uart_ios(uart_config_nb_t uart_config)
+{
+	switch (uart_config)
+	{
+	case L1:
+		/* ----------------------------------------------------------------------- */
+		/* L1 configuration:	UART0 = 8 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Update GPIO Configuration Table */
+		gpio_tab[GPIO1][2].in_out = GPIO_IN;
+		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][3].in_out = GPIO_IN;
+		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][4].in_out = GPIO_IN;
+		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][7].in_out = GPIO_IN;
+		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
+
+		break;
+
+	case L2:
+		/* ----------------------------------------------------------------------- */
+		/* L2 configuration:	UART0 = 4 pins */
+		/*			UART1 = 4 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Update GPIO Configuration Table */
+		gpio_tab[GPIO1][2].in_out = GPIO_IN;
+		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][3].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][4].in_out = GPIO_IN;
+		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][7].in_out = GPIO_IN;
+		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+		break;
+
+	case L3:
+		/* ----------------------------------------------------------------------- */
+		/* L3 configuration:	UART0 = 4 pins */
+		/*			UART1 = 2 pins */
+		/*			UART2 = 2 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Update GPIO Configuration Table */
+		gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][3].in_out = GPIO_IN;
+		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][4].in_out = GPIO_IN;
+		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
+
+		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][7].in_out = GPIO_IN;
+		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+		break;
+
+	case L4:
+		/* ----------------------------------------------------------------------- */
+		/* L4 configuration:	UART0 = 2 pins */
+		/*			UART1 = 2 pins */
+		/*			UART2 = 2 pins */
+		/*			UART3 = 2 pins */
+		/* ----------------------------------------------------------------------- */
+		/* Update GPIO Configuration Table */
+		gpio_tab[GPIO1][2].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][3].in_out = GPIO_IN;
+		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][4].in_out = GPIO_IN;
+		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
+
+		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
+		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
+
+		gpio_tab[GPIO1][7].in_out = GPIO_IN;
+		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
+
+		break;
+
+	default:
+		/* Unsupported UART configuration number */
+		printf("ERROR - Unsupported UART configuration number.\n\n");
+		for (;;)
+			;
+		break;
+
+	}
+
+	/* Set input Selection Register on Alt_Receive for UART Input Core */
+	out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
+	out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
+	out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
+}
+
+/*----------------------------------------------------------------------------+
+  | update_ndfc_ios(void).
+  +----------------------------------------------------------------------------*/
+void update_ndfc_ios(void)
+{
+	/* Update GPIO Configuration Table */
+	gpio_tab[GPIO0][6].in_out = GPIO_OUT;	    /* EBC_CS_N(1) */
+	gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
+
+#if 0
+	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(2) */
+	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(3) */
+	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
+#endif
+}
+
+/*----------------------------------------------------------------------------+
+  | update_zii_ios(void).
+  +----------------------------------------------------------------------------*/
+void update_zii_ios(void)
+{
+	/* Update GPIO Configuration Table */
+	gpio_tab[GPIO0][12].in_out = GPIO_IN;	    /* ZII_p0Rxd(0) */
+	gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][13].in_out = GPIO_IN;	    /* ZII_p0Rxd(1) */
+	gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][14].in_out = GPIO_IN;	    /* ZII_p0Rxd(2) */
+	gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][15].in_out = GPIO_IN;	    /* ZII_p0Rxd(3) */
+	gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][16].in_out = GPIO_OUT;	    /* ZII_p0Txd(0) */
+	gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][17].in_out = GPIO_OUT;	    /* ZII_p0Txd(1) */
+	gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][18].in_out = GPIO_OUT;	    /* ZII_p0Txd(2) */
+	gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][19].in_out = GPIO_OUT;	    /* ZII_p0Txd(3) */
+	gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][20].in_out = GPIO_IN;	    /* ZII_p0Rx_er */
+	gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][21].in_out = GPIO_IN;	    /* ZII_p0Rx_dv */
+	gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][22].in_out = GPIO_IN;	    /* ZII_p0Crs */
+	gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][23].in_out = GPIO_OUT;	    /* ZII_p0Tx_er */
+	gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][24].in_out = GPIO_OUT;	    /* ZII_p0Tx_en */
+	gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][25].in_out = GPIO_IN;	    /* ZII_p0Col */
+	gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+  | update_uic_0_3_irq_ios().
+  +----------------------------------------------------------------------------*/
+void update_uic_0_3_irq_ios(void)
+{
+	gpio_tab[GPIO1][8].in_out = GPIO_IN;	    /* UIC_IRQ(0) */
+	gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][9].in_out = GPIO_IN;	    /* UIC_IRQ(1) */
+	gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][10].in_out = GPIO_IN;	    /* UIC_IRQ(2) */
+	gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][11].in_out = GPIO_IN;	    /* UIC_IRQ(3) */
+	gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_uic_4_9_irq_ios().
+  +----------------------------------------------------------------------------*/
+void update_uic_4_9_irq_ios(void)
+{
+	gpio_tab[GPIO1][12].in_out = GPIO_IN;	    /* UIC_IRQ(4) */
+	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][13].in_out = GPIO_IN;	    /* UIC_IRQ(6) */
+	gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][14].in_out = GPIO_IN;	    /* UIC_IRQ(7) */
+	gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][15].in_out = GPIO_IN;	    /* UIC_IRQ(8) */
+	gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][16].in_out = GPIO_IN;	    /* UIC_IRQ(9) */
+	gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_dma_a_b_ios().
+  +----------------------------------------------------------------------------*/
+void update_dma_a_b_ios(void)
+{
+	gpio_tab[GPIO1][12].in_out = GPIO_OUT;	    /* DMA_ACK(1) */
+	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][13].in_out = GPIO_BI;	    /* DMA_EOT/TC(1) */
+	gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][14].in_out = GPIO_IN;	    /* DMA_REQ(0) */
+	gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][15].in_out = GPIO_OUT;	    /* DMA_ACK(0) */
+	gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][16].in_out = GPIO_BI;	    /* DMA_EOT/TC(0) */
+	gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_dma_c_d_ios().
+  +----------------------------------------------------------------------------*/
+void update_dma_c_d_ios(void)
+{
+	gpio_tab[GPIO0][0].in_out = GPIO_IN;	    /* DMA_REQ(2) */
+	gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][1].in_out = GPIO_OUT;	    /* DMA_ACK(2) */
+	gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][2].in_out = GPIO_BI;	    /* DMA_EOT/TC(2) */
+	gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][3].in_out = GPIO_IN;	    /* DMA_REQ(3) */
+	gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][4].in_out = GPIO_OUT;	    /* DMA_ACK(3) */
+	gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][5].in_out = GPIO_BI;	    /* DMA_EOT/TC(3) */
+	gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
+
+}
+
+/*----------------------------------------------------------------------------+
+  | update_ebc_master_ios().
+  +----------------------------------------------------------------------------*/
+void update_ebc_master_ios(void)
+{
+	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* EXT_EBC_REQ */
+	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
+	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][30].in_out = GPIO_OUT;	    /* EBC_EXT_ACK */
+	gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO0][31].in_out = GPIO_OUT;	    /* EBC_EXR_BUSREQ */
+	gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  | update_usb2_device_ios().
+  +----------------------------------------------------------------------------*/
+void update_usb2_device_ios(void)
+{
+	gpio_tab[GPIO0][26].in_out = GPIO_IN;	    /* USB2D_RXVALID */
+	gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* USB2D_RXERROR */
+	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][28].in_out = GPIO_OUT;	    /* USB2D_TXVALID */
+	gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* USB2D_PAD_SUSPNDM */
+	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][30].in_out = GPIO_OUT;	    /* USB2D_XCVRSELECT */
+	gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO0][31].in_out = GPIO_OUT;	    /* USB2D_TERMSELECT */
+	gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
+
+	gpio_tab[GPIO1][0].in_out = GPIO_OUT;	    /* USB2D_OPMODE0 */
+	gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
+
+	gpio_tab[GPIO1][1].in_out = GPIO_OUT;	    /* USB2D_OPMODE1 */
+	gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
+
+}
+
+/*----------------------------------------------------------------------------+
+  | update_pci_patch_ios().
+  +----------------------------------------------------------------------------*/
+void update_pci_patch_ios(void)
+{
+	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
+	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
+}
+
+/*----------------------------------------------------------------------------+
+  |   set_chip_gpio_configuration(unsigned char gpio_core)
+  |   Put the core impacted by clock modification and sharing in reset.
+  |   Config the select registers to resolve the sharing depending of the config.
+  |   Configure the GPIO registers.
+  |
+  +----------------------------------------------------------------------------*/
+void set_chip_gpio_configuration(unsigned char gpio_core)
+{
+	unsigned char i=0, j=0, reg_offset = 0;
+	unsigned long gpio_reg, gpio_core_add;
+
+	/* GPIO config of the GPIOs 0 to 31 */
+	for (i=0; i<GPIO_MAX; i++, j++)
+	{
+		if (i == GPIO_MAX/2)
+		{
+			reg_offset = 4;
+			j = i-16;
+		}
+
+		gpio_core_add = gpio_tab[gpio_core][i].add;
+
+		if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
+		     (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+		{
+			switch (gpio_tab[gpio_core][i].alt_nb)
+			{
+			case GPIO_SEL:
+				break;
+
+			case GPIO_ALT1:
+				gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+				out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
+				break;
+
+			case GPIO_ALT2:
+				gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+				out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
+				break;
+
+			case GPIO_ALT3:
+				gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+				out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
+				break;
+			}
+		}
+		if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
+		     (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
+		{
+
+			switch (gpio_tab[gpio_core][i].alt_nb)
+			{
+			case GPIO_SEL:
+				break;
+			case GPIO_ALT1:
+				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+				break;
+			case GPIO_ALT2:
+				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+				break;
+			case GPIO_ALT3:
+				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
+				gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+				break;
+			}
+		}
+	}
+}
+
+/*----------------------------------------------------------------------------+
+  | force_bup_core_selection.
+  +----------------------------------------------------------------------------*/
+void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
+{
+	/* Pointer invalid */
+	if (core_select_P == NULL)
+	{
+		printf("Configuration invalid pointer 1\n");
+		for (;;)
+			;
+	}
+
+	/* L4 Selection */
+	*(core_select_P+UART_CORE0)	       = CORE_SELECTED;
+	*(core_select_P+UART_CORE1)	       = CORE_SELECTED;
+	*(core_select_P+UART_CORE2)	       = CORE_SELECTED;
+	*(core_select_P+UART_CORE3)	       = CORE_SELECTED;
+
+	/* RMII Selection */
+	*(core_select_P+RMII_SEL)		= CORE_SELECTED;
+
+	/* External Interrupt 0-9 selection */
+	*(core_select_P+UIC_0_3)		= CORE_SELECTED;
+	*(core_select_P+UIC_4_9)		= CORE_SELECTED;
+
+	*(core_select_P+SCP_CORE)	        = CORE_SELECTED;
+	*(core_select_P+DMA_CHANNEL_CD)		= CORE_SELECTED;
+	*(core_select_P+PACKET_REJ_FUNC_AVAIL)	= CORE_SELECTED;
+	*(core_select_P+USB1_DEVICE)		= CORE_SELECTED;
+
+	if (is_nand_selected()) {
+		*(core_select_P+NAND_FLASH)	= CORE_SELECTED;
+	}
+
+	*config_val_P = CONFIG_IS_VALID;
+
+}
+
+/*----------------------------------------------------------------------------+
+  | configure_ppc440ep_pins.
+  +----------------------------------------------------------------------------*/
+void configure_ppc440ep_pins(void)
+{
+	uart_config_nb_t uart_configuration;
+	config_validity_t config_val = CONFIG_IS_INVALID;
+
+	/* Create Core Selection Table */
+	core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
+		{
+			CORE_NOT_SELECTED,	/* IIC_CORE, */
+			CORE_NOT_SELECTED,	/* SPC_CORE, */
+			CORE_NOT_SELECTED,	/* DMA_CHANNEL_AB, */
+			CORE_NOT_SELECTED,	/* UIC_4_9, */
+			CORE_NOT_SELECTED,	/* USB2_HOST, */
+			CORE_NOT_SELECTED,	/* DMA_CHANNEL_CD, */
+			CORE_NOT_SELECTED,	/* USB2_DEVICE, */
+			CORE_NOT_SELECTED,	/* PACKET_REJ_FUNC_AVAIL, */
+			CORE_NOT_SELECTED,	/* USB1_DEVICE, */
+			CORE_NOT_SELECTED,	/* EBC_MASTER, */
+			CORE_NOT_SELECTED,	/* NAND_FLASH, */
+			CORE_NOT_SELECTED,	/* UART_CORE0, */
+			CORE_NOT_SELECTED,	/* UART_CORE1, */
+			CORE_NOT_SELECTED,	/* UART_CORE2, */
+			CORE_NOT_SELECTED,	/* UART_CORE3, */
+			CORE_NOT_SELECTED,	/* MII_SEL, */
+			CORE_NOT_SELECTED,	/* RMII_SEL, */
+			CORE_NOT_SELECTED,	/* SMII_SEL, */
+			CORE_NOT_SELECTED,	/* PACKET_REJ_FUNC_EN */
+			CORE_NOT_SELECTED,	/* UIC_0_3 */
+			CORE_NOT_SELECTED,	/* USB1_HOST */
+			CORE_NOT_SELECTED	/* PCI_PATCH */
+		};
+
+
+	/* Table Default Initialisation + FPGA Access */
+	init_default_gpio();
+	set_chip_gpio_configuration(GPIO0);
+	set_chip_gpio_configuration(GPIO1);
+
+	/* Update Table */
+	force_bup_core_selection(ppc440ep_core_selection, &config_val);
+#if 0 /* test-only */
+	/* If we are running PIBS 1, force known configuration */
+	update_core_selection_table(ppc440ep_core_selection, &config_val);
+#endif
+
+	/*----------------------------------------------------------------------------+
+	  | SDR + ios table update + fpga initialization
+	  +----------------------------------------------------------------------------*/
+	unsigned long sdr0_pfc1	    = 0;
+	unsigned long sdr0_usb0	    = 0;
+	unsigned long sdr0_mfr	    = 0;
+
+	/* PCI Always selected */
+
+	/* I2C Selection */
+	if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
+		iic1_selection_in_fpga();
+	}
+
+	/* SCP Selection */
+	if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
+		scp_selection_in_fpga();
+	}
+
+	/* UIC 0:3 Selection */
+	if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
+	{
+		update_uic_0_3_irq_ios();
+		dma_a_b_unselect_in_fpga();
+	}
+
+	/* UIC 4:9 Selection */
+	if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
+		update_uic_4_9_irq_ios();
+	}
+
+	/* DMA AB Selection */
+	if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
+		update_dma_a_b_ios();
+		dma_a_b_selection_in_fpga();
+	}
+
+	/* DMA CD Selection */
+	if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
+	{
+		update_dma_c_d_ios();
+		dma_c_d_selection_in_fpga();
+	}
+
+	/* EBC Master Selection */
+	if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+		update_ebc_master_ios();
+	}
+
+	/* PCI Patch Enable */
+	if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
+	{
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
+		update_pci_patch_ios();
+	}
+
+	/* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
+	if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
+	{
+		/* Not Implemented in PowerPC 440EP Pass1-Pass2 */
+		printf("Invalid configuration => USB2 Host selected\n");
+		for (;;)
+			;
+		/*usb2_host_selection_in_fpga(); */
+	}
+
+	/* USB2.0 Device Selection */
+	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+	{
+		update_usb2_device_ios();
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
+
+		mfsdr(sdr_usb0, sdr0_usb0);
+		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
+		mtsdr(sdr_usb0, sdr0_usb0);
+
+		usb2_device_selection_in_fpga();
+	}
+
+	/* USB1.1 Device Selection */
+	if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
+	{
+		mfsdr(sdr_usb0, sdr0_usb0);
+		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
+		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
+		mtsdr(sdr_usb0, sdr0_usb0);
+	}
+
+	/* USB1.1 Host Selection */
+	if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
+	{
+		mfsdr(sdr_usb0, sdr0_usb0);
+		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
+		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
+		mtsdr(sdr_usb0, sdr0_usb0);
+	}
+
+	/* NAND Flash Selection */
+	if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
+	{
+		update_ndfc_ios();
+
+		mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
+		      SDR0_CUST0_NDFC_ENABLE	|
+		      SDR0_CUST0_NDFC_BW_8_BIT	|
+		      SDR0_CUST0_NDFC_ARE_MASK	|
+		      SDR0_CUST0_CHIPSELGAT_EN1 |
+		      SDR0_CUST0_CHIPSELGAT_EN2);
+
+		ndfc_selection_in_fpga();
+	}
+	else
+	{
+		/* Set Mux on EMAC */
+		mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
+	}
+
+	/* MII Selection */
+	if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
+	{
+		update_zii_ios();
+		mfsdr(sdr_mfr, sdr0_mfr);
+		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
+		mtsdr(sdr_mfr, sdr0_mfr);
+
+		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
+	}
+
+	/* RMII Selection */
+	if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
+	{
+		update_zii_ios();
+		mfsdr(sdr_mfr, sdr0_mfr);
+		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
+		mtsdr(sdr_mfr, sdr0_mfr);
+
+		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
+	}
+
+	/* SMII Selection */
+	if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
+	{
+		update_zii_ios();
+		mfsdr(sdr_mfr, sdr0_mfr);
+		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
+		mtsdr(sdr_mfr, sdr0_mfr);
+
+		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
+	}
+
+	/* UART Selection */
+	uart_configuration = get_uart_configuration();
+	switch (uart_configuration)
+	{
+	case L1:	 /* L1 Selection */
+		/* UART0 8 pins Only */
+		/*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;	  /* Chip Pb */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
+		break;
+	case L2:	 /* L2 Selection */
+		/* UART0 and UART1 4 pins */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		break;
+	case L3:	 /* L3 Selection */
+		/* UART0 4 pins, UART1 and UART2 2 pins */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		break;
+	case L4:	 /* L4 Selection */
+		/* UART0, UART1, UART2 and UART3 2 pins */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
+		break;
+	}
+	update_uart_ios(uart_configuration);
+
+	/* UART Selection in all cases */
+	uart_selection_in_fpga(uart_configuration);
+
+	/* Packet Reject Function Available */
+	if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
+	{
+		/* Set UPR Bit in SDR0_PFC1 Register */
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
+	}
+
+	/* Packet Reject Function Enable */
+	if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
+	{
+		mfsdr(sdr_mfr, sdr0_mfr);
+		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
+		mtsdr(sdr_mfr, sdr0_mfr);
+	}
+
+	/* Perform effective access to hardware */
+	mtsdr(sdr_pfc1, sdr0_pfc1);
+	set_chip_gpio_configuration(GPIO0);
+	set_chip_gpio_configuration(GPIO1);
+
+	/* USB2.0 Device Reset must be done after GPIO setting */
+	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
+		usb2_device_reset_through_fpga();
+
+}
diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h
new file mode 100755
index 0000000..5f5fcde
--- /dev/null
+++ b/board/amcc/bamboo/bamboo.h
@@ -0,0 +1,401 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*----------------------------------------------------------------------------+
+  | FPGA registers and bit definitions
+  +----------------------------------------------------------------------------*/
+/*
+ * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
+ * TLB initialization makes it correspond to logical address 0x80001FF0.
+ * => Done init_chip.s in bootlib
+ */
+#define FPGA_BASE_ADDR	0x80002000
+
+/*----------------------------------------------------------------------------+
+  | Board Jumpers Setting Register
+  |   Board Settings provided by jumpers
+  +----------------------------------------------------------------------------*/
+#define FPGA_SETTING_REG	    (FPGA_BASE_ADDR+0x3)
+/* Boot from small flash */
+#define	    FPGA_SET_REG_BOOT_SMALL_FLASH	    0x80
+/* Operational Flash versus SRAM position in Memory Map */
+#define	    FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK	    0x40
+#define	     FPGA_SET_REG_OP_CODE_FLASH_ABOVE	     0x40
+#define	     FPGA_SET_REG_SRAM_ABOVE		     0x00
+/* Boot From NAND Flash */
+#define	    FPGA_SET_REG_BOOT_NAND_FLASH_MASK	    0x40
+#define	    FPGA_SET_REG_BOOT_NAND_FLASH_SELECT	     0x00
+/* On Board PCI Arbiter Select */
+#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK   0x10
+#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL	    0x00
+
+/*----------------------------------------------------------------------------+
+  | Functions Selection Register 1
+  +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_1_REG	    (FPGA_BASE_ADDR+0x4)
+#define	    FPGA_SEL_1_REG_PHY_MASK	    0xE0
+#define	    FPGA_SEL_1_REG_MII		    0x80
+#define	    FPGA_SEL_1_REG_RMII		    0x40
+#define	    FPGA_SEL_1_REG_SMII		    0x20
+#define	    FPGA_SEL_1_REG_USB2_DEV_SEL	    0x10	   /* USB2 Device Selection */
+#define	    FPGA_SEL_1_REG_USB2_HOST_SEL    0x08	   /* USB2 Host Selection */
+#define	    FPGA_SEL_1_REG_NF_SELEC_MASK    0x07	   /* NF Selection Mask */
+#define	    FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04	   /* NF0 Selected by NF_CS1 */
+#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02	   /* NF1 Selected by NF_CS2 */
+#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01	   /* NF1 Selected by NF_CS3 */
+
+/*----------------------------------------------------------------------------+
+  | Functions Selection Register 2
+  +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_2_REG	    (FPGA_BASE_ADDR+0x5)
+#define	    FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80	   /* IIC1 / SCP Selection */
+#define	    FPGA_SEL2_REG_SEL_FRAM	    0x80	   /* FRAM on IIC1 bus selected - SCP Select */
+#define	    FPGA_SEL2_REG_SEL_SCP	    0x80	   /* Identical to SCP Selection */
+#define	    FPGA_SEL2_REG_SEL_IIC1	    0x00	   /* IIC1 Selection - Default Value */
+#define	    FPGA_SEL2_REG_SEL_DMA_A_B	    0x40	   /* DMA A & B channels selected */
+#define	    FPGA_SEL2_REG_SEL_DMA_C_D	    0x20	   /* DMA C & D channels selected */
+#define	    FPGA_SEL2_REG_DMA_EOT_TC_3_SEL  0x10	   /* 0 = EOT - input to 440EP */
+							   /* 1 = TC - output from 440EP */
+#define	    FPGA_SEL2_REG_DMA_EOT_TC_2_SEL  0x08	   /* 0 = EOT (input to 440EP) */
+							   /* 1 = TC (output from 440EP) */
+#define	    FPGA_SEL2_REG_SEL_GPIO_1	    0x04	   /* EBC_GPIO & USB2_GPIO selected */
+#define	    FPGA_SEL2_REG_SEL_GPIO_2	    0x02	   /* Ether._GPIO & UART_GPIO selected */
+#define	    FPGA_SEL2_REG_SEL_GPIO_3	    0x01	   /* DMA_GPIO & Trace_GPIO selected */
+
+/*----------------------------------------------------------------------------+
+  | Functions Selection Register 3
+  +----------------------------------------------------------------------------*/
+#define FPGA_SELECTION_3_REG	    (FPGA_BASE_ADDR+0x6)
+#define	    FPGA_SEL3_REG_EXP_SLOT_EN		    0x80    /* Expansion Slot enabled */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG_MASK	    0x70
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG1	    0x40    /* one 8_pin UART */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG2	    0x20    /* two 4_pin UARTs */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG3	    0x10    /* one 4_pin & two 2_pin UARTs */
+#define	    FPGA_SEL3_REG_SEL_UART_CONFIG4	    0x08    /* four 2_pin UARTs */
+#define	    FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART   0x00    /* DTR/DSR mode for 4_pin_UART */
+#define	    FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART   0x04    /* RTS/CTS mode for 4_pin_UART */
+
+/*----------------------------------------------------------------------------+
+  | Soft Reset Register
+  +----------------------------------------------------------------------------*/
+#define FPGA_RESET_REG		    (FPGA_BASE_ADDR+0x7)
+#define	    FPGA_RESET_REG_RESET_USB20_DEV	    0x80    /* Hard Reset of the GT3200 */
+#define	    FPGA_RESET_REG_RESET_DISPLAY	    0x40    /* Hard Reset on Display Device */
+#define	    FPGA_RESET_REG_STATUS_LED_0		    0x08    /* 1 = Led On */
+#define	    FPGA_RESET_REG_STATUS_LED_1		    0x04    /* 1 = Led On */
+#define	    FPGA_RESET_REG_STATUS_LED_2		    0x02    /* 1 = Led On */
+#define	    FPGA_RESET_REG_STATUS_LED_3		    0x01    /* 1 = Led On */
+
+
+/*----------------------------------------------------------------------------+
+| SDR Configuration registers
++----------------------------------------------------------------------------*/
+/* Serial Device Strap Reg 0 */
+#define SDR0_SDSTP0		     0x0020
+/* Serial Device Strap Reg 1 */
+#define SDR0_SDSTP1		     0x0021
+/* Serial Device Strap Reg 2 */
+#define SDR0_SDSTP2		     SDR0_STRP2
+/* Serial Device Strap Reg 3 */
+#define SDR0_SDSTP3		     SDR0_STRP3
+
+#define sdr_pstrp0		     0x0040
+
+#define	  SDR0_SDSTP1_EBC_ROM_BS_MASK  0x00006000  /* EBC Boot Size Mask */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000    /* EBC 32 bits */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000    /* EBC 16 Bits */
+#define	  SDR0_SDSTP1_EBC_ROM_BS_8BIT  0x00000000    /* EBC  8 Bits */
+
+#define	  SDR0_SDSTP1_BOOT_SEL_MASK    0x00001800   /* Boot device Selection Mask */
+#define	  SDR0_SDSTP1_BOOT_SEL_EBC     0x00000000     /* EBC */
+#define	  SDR0_SDSTP1_BOOT_SEL_PCI     0x00000800     /* PCI */
+#define	  SDR0_SDSTP1_BOOT_SEL_NDFC    0x00001000     /* NDFC */
+
+/* Serial Device Enabled - Addr = 0xA8 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
+/* Serial Device Enabled - Addr = 0xA4 */
+#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
+
+/* Pin Straps Reg */
+#define SDR0_PSTRP0		     0x0040
+#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000  /* Strap Bits */
+
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000  /* Default strap settings 0 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000  /* Default strap settings 1 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000  /* Default strap settings 2 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000  /* Default strap settings 3 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000  /* Default strap settings 4 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000  /* Default strap settings 5 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000  /* Default strap settings 6 */
+#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000  /* Default strap settings 7 */
+
+/*----------------------------------------------------------------------------+
+| EBC Configuration Register - EBC0_CFG
++----------------------------------------------------------------------------*/
+/* External Bus Three-State Control */
+#define EBC0_CFG_EBTC_DRIVEN	    0x80000000
+/* Device-Paced Time-out Disable */
+#define EBC0_CFG_PTD_ENABLED	    0x00000000
+/* Ready Timeout Count */
+#define EBC0_CFG_RTC_MASK	    0x38000000
+#define EBC0_CFG_RTC_16PERCLK	    0x00000000
+#define EBC0_CFG_RTC_32PERCLK	    0x08000000
+#define EBC0_CFG_RTC_64PERCLK	    0x10000000
+#define EBC0_CFG_RTC_128PERCLK	    0x18000000
+#define EBC0_CFG_RTC_256PERCLK	    0x20000000
+#define EBC0_CFG_RTC_512PERCLK	    0x28000000
+#define EBC0_CFG_RTC_1024PERCLK	    0x30000000
+#define EBC0_CFG_RTC_2048PERCLK	    0x38000000
+/* External Master Priority Low */
+#define EBC0_CFG_EMPL_LOW	    0x00000000
+#define EBC0_CFG_EMPL_MEDIUM_LOW    0x02000000
+#define EBC0_CFG_EMPL_MEDIUM_HIGH   0x04000000
+#define EBC0_CFG_EMPL_HIGH	    0x06000000
+/* External Master Priority High */
+#define EBC0_CFG_EMPH_LOW	    0x00000000
+#define EBC0_CFG_EMPH_MEDIUM_LOW    0x00800000
+#define EBC0_CFG_EMPH_MEDIUM_HIGH   0x01000000
+#define EBC0_CFG_EMPH_HIGH	    0x01800000
+/* Chip Select Three-State Control */
+#define EBC0_CFG_CSTC_DRIVEN	    0x00400000
+/* Burst Prefetch */
+#define EBC0_CFG_BPF_ONEDW	    0x00000000
+#define EBC0_CFG_BPF_TWODW	    0x00100000
+#define EBC0_CFG_BPF_FOURDW	    0x00200000
+/* External Master Size */
+#define EBC0_CFG_EMS_8BIT	    0x00000000
+/* Power Management Enable */
+#define EBC0_CFG_PME_DISABLED	    0x00000000
+#define EBC0_CFG_PME_ENABLED	    0x00020000
+/* Power Management Timer */
+#define EBC0_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Configuration Register - EBC0_BnCR
++----------------------------------------------------------------------------*/
+/* BAS - Base Address Select */
+#define EBC0_BNCR_BAS_ENCODE(n)		((((unsigned long)(n))&0xFFF00000)<<0)
+/* BS - Bank Size */
+#define EBC0_BNCR_BS_MASK	0x000E0000
+#define EBC0_BNCR_BS_1MB	0x00000000
+#define EBC0_BNCR_BS_2MB	0x00020000
+#define EBC0_BNCR_BS_4MB	0x00040000
+#define EBC0_BNCR_BS_8MB	0x00060000
+#define EBC0_BNCR_BS_16MB	0x00080000
+#define EBC0_BNCR_BS_32MB	0x000A0000
+#define EBC0_BNCR_BS_64MB	0x000C0000
+#define EBC0_BNCR_BS_128MB	0x000E0000
+/* BU - Bank Usage */
+#define EBC0_BNCR_BU_MASK	0x00018000
+#define EBC0_BNCR_BU_RO		    0x00008000
+#define EBC0_BNCR_BU_WO		    0x00010000
+#define EBC0_BNCR_BU_RW		0x00018000
+/* BW - Bus Width */
+#define EBC0_BNCR_BW_MASK	0x00006000
+#define EBC0_BNCR_BW_8BIT	0x00000000
+#define EBC0_BNCR_BW_16BIT	0x00002000
+#define EBC0_BNCR_BW_32BIT	0x00004000
+
+/*----------------------------------------------------------------------------+
+| Peripheral Bank Access Parameters - EBC0_BnAP
++----------------------------------------------------------------------------*/
+/* Burst Mode Enable */
+#define EBC0_BNAP_BME_ENABLED	    0x80000000
+#define EBC0_BNAP_BME_DISABLED	    0x00000000
+/* Transfert Wait */
+#define EBC0_BNAP_TWT_ENCODE(n)	    ((((unsigned long)(n))&0xFF)<<23)	/* Bits 1:8 */
+/* Chip Select On Timing */
+#define EBC0_BNAP_CSN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<18)	/* Bits 12:13 */
+/* Output Enable On Timing */
+#define EBC0_BNAP_OEN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<16)	/* Bits 14:15 */
+/* Write Back Enable On Timing */
+#define EBC0_BNAP_WBN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<14)	/* Bits 16:17 */
+/* Write Back Enable Off Timing */
+#define EBC0_BNAP_WBF_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<12)	/* Bits 18:19 */
+/* Transfert Hold */
+#define EBC0_BNAP_TH_ENCODE(n)	    ((((unsigned long)(n))&0x7)<<9)	/* Bits 20:22 */
+/* PerReady Enable */
+#define EBC0_BNAP_RE_ENABLED	    0x00000100
+#define EBC0_BNAP_RE_DISABLED	    0x00000000
+/* Sample On Ready */
+#define EBC0_BNAP_SOR_DELAYED	    0x00000000
+#define EBC0_BNAP_SOR_NOT_DELAYED   0x00000080
+/* Byte Enable Mode */
+#define EBC0_BNAP_BEM_WRITEONLY	    0x00000000
+#define EBC0_BNAP_BEM_RW	    0x00000040
+/* Parity Enable */
+#define EBC0_BNAP_PEN_DISABLED	    0x00000000
+#define EBC0_BNAP_PEN_ENABLED	    0x00000020
+
+/*----------------------------------------------------------------------------+
+| Define Boot devices
++----------------------------------------------------------------------------*/
+/* */
+#define BOOT_FROM_SMALL_FLASH		0x00
+#define BOOT_FROM_LARGE_FLASH_OR_SRAM	0x01
+#define BOOT_FROM_NAND_FLASH0		0x02
+#define BOOT_FROM_PCI			0x03
+#define BOOT_DEVICE_UNKNOWN		0x04
+
+
+#define	 PVR_POWERPC_440EP_PASS1    0x42221850
+#define	 PVR_POWERPC_440EP_PASS2    0x422218D3
+
+#define TRUE 1
+#define FALSE 0
+
+#define GPIO_GROUP_MAX	    2
+#define GPIO_MAX	    32
+#define GPIO_ALT1_SEL	    0x40000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
+#define GPIO_ALT2_SEL	    0x80000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
+#define GPIO_ALT3_SEL	    0xC0000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
+#define GPIO_MASK	    0xC0000000	    /* GPIO_MASK */
+#define GPIO_IN_SEL	    0x40000000	    /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
+					    /* For the other GPIO number, you must shift */
+
+#define GPIO0		0
+#define GPIO1		1
+
+
+/*#define MAX_SELECTION_NB	CORE_NB */
+#define MAX_CORE_SELECT_NB	22
+
+/*----------------------------------------------------------------------------+
+  | PPC440EP GPIOs addresses.
+  +----------------------------------------------------------------------------*/
+#define GPIO0_BASE	 0xEF600B00
+#define GPIO0_REAL	 0xEF600B00
+
+#define GPIO1_BASE	 0xEF600C00
+#define GPIO1_REAL	 0xEF600C00
+
+/* Offsets */
+#define GPIOx_OR    0x00	/* GPIO Output Register */
+#define GPIOx_TCR   0x04	/* GPIO Three-State Control Register */
+#define GPIOx_OSL   0x08	/* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH   0x0C	/* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL   0x10	/* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH   0x14	/* GPIO Three-State Select Register  (Bits 32-63) */
+#define GPIOx_ODR   0x18	/* GPIO Open drain Register */
+#define GPIOx_IR    0x1C	/* GPIO Input Register */
+#define GPIOx_RR1   0x20	/* GPIO Receive Register 1 */
+#define GPIOx_RR2   0x24	/* GPIO Receive Register 2 */
+#define GPIOx_RR3   0x28	/* GPIO Receive Register 3 */
+#define GPIOx_IS1L  0x30	/* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H  0x34	/* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L  0x38	/* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H  0x3C	/* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L  0x40	/* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H  0x44	/* GPIO Input Select Register 3 (Bits 32-63) */
+
+/* GPIO0 */
+#define GPIO0_IS1L	(GPIO0_BASE+GPIOx_IS1L)
+#define GPIO0_IS1H	(GPIO0_BASE+GPIOx_IS1H)
+#define GPIO0_IS2L	(GPIO0_BASE+GPIOx_IS2L)
+#define GPIO0_IS2H	(GPIO0_BASE+GPIOx_IS2H)
+#define GPIO0_IS3L	(GPIO0_BASE+GPIOx_IS3L)
+#define GPIO0_IS3H	(GPIO0_BASE+GPIOx_IS3L)
+
+/* GPIO1 */
+#define GPIO1_IS1L	(GPIO1_BASE+GPIOx_IS1L)
+#define GPIO1_IS1H	(GPIO1_BASE+GPIOx_IS1H)
+#define GPIO1_IS2L	(GPIO1_BASE+GPIOx_IS2L)
+#define GPIO1_IS2H	(GPIO1_BASE+GPIOx_IS2H)
+#define GPIO1_IS3L	(GPIO1_BASE+GPIOx_IS3L)
+#define GPIO1_IS3H	(GPIO1_BASE+GPIOx_IS3L)
+
+#define GPIO_OS(x)	(x+GPIOx_OSL)	 /* GPIO Output Register High or Low */
+#define GPIO_TS(x)	(x+GPIOx_TSL)	 /* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x)	(x+GPIOx_IS1L)	 /* GPIO Input register1 High or Low */
+#define GPIO_IS2(x)	(x+GPIOx_IS2L)	 /* GPIO Input register2 High or Low */
+#define GPIO_IS3(x)	(x+GPIOx_IS3L)	 /* GPIO Input register3 High or Low */
+
+
+/*----------------------------------------------------------------------------+
+  | Declare Configuration values
+  +----------------------------------------------------------------------------*/
+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
+
+typedef struct { unsigned long	add;	/* gpio core base address */
+	gpio_driver_t  in_out; /* Driver Setting */
+	gpio_select_t  alt_nb; /* Selected Alternate */
+} gpio_param_s;
+
+/*----------------------------------------------------------------------------+
+  |			XX     XX
+  |
+  | XXXXXX   XXX XX    XXX    XXX
+  |    XX    XX X XX	XX     XX
+  |   XX     XX X XX	XX     XX
+  |  XX	     XX	  XX	XX     XX
+  | XXXXXX   XXX  XXX  XXXX   XXXX
+  +----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+  | Defines
+  +----------------------------------------------------------------------------*/
+typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
+			   ZMII_CONFIGURATION_IS_MII,
+			   ZMII_CONFIGURATION_IS_RMII,
+			   ZMII_CONFIGURATION_IS_SMII
+} zmii_config_t;
+
+/*----------------------------------------------------------------------------+
+  | Declare Configuration values
+  +----------------------------------------------------------------------------*/
+typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
+typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
+typedef enum config_list {  IIC_CORE,
+			    SCP_CORE,
+			    DMA_CHANNEL_AB,
+			    UIC_4_9,
+			    USB2_HOST,
+			    DMA_CHANNEL_CD,
+			    USB2_DEVICE,
+			    PACKET_REJ_FUNC_AVAIL,
+			    USB1_DEVICE,
+			    EBC_MASTER,
+			    NAND_FLASH,
+			    UART_CORE0,
+			    UART_CORE1,
+			    UART_CORE2,
+			    UART_CORE3,
+			    MII_SEL,
+			    RMII_SEL,
+			    SMII_SEL,
+			    PACKET_REJ_FUNC_EN,
+			    UIC_0_3,
+			    USB1_HOST,
+			    PCI_PATCH,
+			    CORE_NB
+} core_list_t;
+
+typedef enum block3_value { B3_V1,  B3_V2,  B3_V3,  B3_V4,  B3_V5,
+			    B3_V6,  B3_V7,  B3_V8,  B3_V9,  B3_V10,
+			    B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
+			    B3_V16, B3_VALUE_UNKNOWN
+} block3_value_t;
+
+typedef enum config_validity { CONFIG_IS_VALID,
+			       CONFIG_IS_INVALID
+} config_validity_t;
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
new file mode 100755
index 0000000..35cb655
--- /dev/null
+++ b/board/amcc/bamboo/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFF80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c
new file mode 100755
index 0000000..a30ab7a
--- /dev/null
+++ b/board/amcc/bamboo/flash.c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <ppc440.h>
+#include "bamboo.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*
+ * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
+ */
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+	{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
+	{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
+	{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash  */
+	{0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
+	{0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
+	{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
+	{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66      */
+	{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from             */
+	{0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+	unsigned long val;
+	unsigned long ebc_boot_size;
+	unsigned long boot_selection;
+
+	mfsdr(sdr_pstrp0, val);
+	index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
+
+	if ((index == 5) || (index == 7)) {
+		/*
+		 * Boot Settings in IIC EEprom address 0xA8 or 0xA4
+		 * Read Serial Device Strap Register1 in PPC440EP
+		 */
+		mfsdr(sdr_sdstp1, val);
+		boot_selection  = val & SDR0_SDSTP1_BOOT_SEL_MASK;
+		ebc_boot_size   = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
+
+		switch(boot_selection) {
+		case SDR0_SDSTP1_BOOT_SEL_EBC:
+			switch(ebc_boot_size) {
+			case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
+				index = 3;
+				break;
+			case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
+				index = 0;
+				break;
+			}
+			break;
+
+		case SDR0_SDSTP1_BOOT_SEL_PCI:
+			index = 1;
+			break;
+
+		case SDR0_SDSTP1_BOOT_SEL_NDFC:
+			index = 2;
+			break;
+		}
+	} else if (index == 0) {
+		if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
+			index = 8; /* sram below op code flash -> new index 8 */
+		}
+	}
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+				   &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			       i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH)
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+#endif
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
new file mode 100755
index 0000000..7820107
--- /dev/null
+++ b/board/amcc/bamboo/init.S
@@ -0,0 +1,113 @@
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_8M       0x00000060
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+
+    /*
+     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+     * speed up boot process. It is patched after relocation to enable SA_I
+     */
+    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+    tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+
+    /* PCI */
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+
+    /* USB 2.0 Device */
+    tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I )
+
+    tlbtab_end
diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds
new file mode 100755
index 0000000..176900e
--- /dev/null
+++ b/board/amcc/bamboo/u-boot.lds
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/amcc/bamboo/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile
new file mode 100755
index 0000000..f5bda55
--- /dev/null
+++ b/board/amcc/bubinga/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
new file mode 100755
index 0000000..fe6ce8a
--- /dev/null
+++ b/board/amcc/bubinga/bubinga.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+long int spd_sdram(void);
+
+#include <common.h>
+#include <asm/processor.h>
+
+int board_early_init_f(void)
+{
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicer, 0x00000000);	/* disable all ints */
+	mtdcr(uiccr, 0x00000010);
+	mtdcr(uicpr, 0xFFFF7FF0);	/* set int polarities */
+	mtdcr(uictr, 0x00000010);	/* set int trigger levels */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
+ */
+void sdram_init(void)
+{
+	return;
+}
+
+/* -------------------------------------------------------------------------
+  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  the necessary info for SDRAM controller configuration
+   ------------------------------------------------------------------------- */
+long int initdram(int board_type)
+{
+	long int ret;
+
+	ret = spd_sdram();
+	return ret;
+}
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("test: xxx MB - ok\n");
+
+	return (0);
+}
diff --git a/board/amcc/bubinga/config.mk b/board/amcc/bubinga/config.mk
new file mode 100755
index 0000000..1bdf5e4
--- /dev/null
+++ b/board/amcc/bubinga/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c
new file mode 100755
index 0000000..e4832eb
--- /dev/null
+++ b/board/amcc/bubinga/flash.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+	    flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		       size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	if (CFG_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[0]);
+#ifdef CFG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+#endif
+
+		size_b1 = 0;
+		flash_info[0].size = size_b0;
+	}
+
+	/* 2 banks */
+	else {
+		size_b1 =
+		    flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+				   &flash_info[1]);
+
+		/* Re-do sizing to get full correct info */
+
+		if (size_b1) {
+			mtdcr(ebccfga, pb0cr);
+			pbcr = mfdcr(ebccfgd);
+			mtdcr(ebccfga, pb0cr);
+			base_b1 = -size_b1;
+			pbcr = (pbcr & 0x0001ffff) | base_b1 |
+			    (((size_b1 / 1024 / 1024) - 1) << 17);
+			mtdcr(ebccfgd, pbcr);
+			/*          printf("pb1cr = %x\n", pbcr); */
+		}
+
+		if (size_b0) {
+			mtdcr(ebccfga, pb1cr);
+			pbcr = mfdcr(ebccfgd);
+			mtdcr(ebccfga, pb1cr);
+			base_b0 = base_b1 - size_b0;
+			pbcr = (pbcr & 0x0001ffff) | base_b0 |
+			    (((size_b0 / 1024 / 1024) - 1) << 17);
+			mtdcr(ebccfgd, pbcr);
+			/*            printf("pb0cr = %x\n", pbcr); */
+		}
+
+		size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+		flash_get_offsets(base_b0, &flash_info[0]);
+
+		/* monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    base_b0 + size_b0 - CFG_MONITOR_LEN,
+				    base_b0 + size_b0 - 1, &flash_info[0]);
+		/* Also protect sector containing initial power-up instruction */
+		/* (flash_protect() checks address range - other call ignored) */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
+
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 =
+			    flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+			flash_get_offsets(base_b1, &flash_info[1]);
+
+			/* monitor protection ON by default */
+			(void)flash_protect(FLAG_PROTECT_SET,
+					    base_b1 + size_b1 - CFG_MONITOR_LEN,
+					    base_b1 + size_b1 - 1,
+					    &flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void)flash_protect(FLAG_PROTECT_CLEAR,
+					    base_b0 + size_b0 - CFG_MONITOR_LEN,
+					    base_b0 + size_b0 - 1,
+					    &flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
+
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}			/* else 2 banks */
+	return (size_b0 + size_b1);
+}
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+}
diff --git a/board/amcc/bubinga/u-boot.lds b/board/amcc/bubinga/u-boot.lds
new file mode 100755
index 0000000..be03092
--- /dev/null
+++ b/board/amcc/bubinga/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
new file mode 100755
index 0000000..3a50b09
--- /dev/null
+++ b/board/amcc/common/flash.c
@@ -0,0 +1,917 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word_1(flash_info_t * info, ulong dest, ulong data);
+static int write_word_2(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AMD016:
+		printf("AM29F016D (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM033C:
+		printf("AM29LV033C (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:
+		printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:
+		printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_STMW320DT:
+		printf ("M29W320DT (32 M, top sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+	       info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s%s",
+		       info->start[i],
+		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	/* bit 0 used for big flash marking */
+	if ((ulong)addr & 0x1) {
+		return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
+	} else {
+		return flash_get_size_1(addr, info);
+	}
+}
+
+static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+		info->flash_id += FLASH_AMD016;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+		info->flash_id += FLASH_AMDLV033C;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_1(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CFG_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+		return flash_erase_2(info, s_first, s_last);
+	} else {
+		return flash_erase_1(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_1(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
+		return write_word_2(info, dest, data);
+	} else {
+		return write_word_1(info, dest, data);
+	}
+}
+
+static int write_word_1(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+#ifdef CFG_FLASH_2ND_16BIT_DEV
+
+#undef  CFG_FLASH_WORD_SIZE
+#define CFG_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	int n;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		/*  1 x 16k boot sector */
+		base -= 16 << 10;
+		--i;
+		info->start[i] = base;
+		/*  2 x 8k  boot sectors */
+		for (n=0; n<2; ++n) {
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		/*  1 x 32k boot sector */
+		base -= 32 << 10;
+		--i;
+		info->start[i] = base;
+
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of *
+		 * reading flash protection for upper 8 Mb of flash     */
+		if (i == 32) {
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+		}
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_2(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CFG_FLASH_WORD_SIZE *addr =
+	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CFG_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay(1000);	/* wait 1 ms */
+			} else {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_2(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+static int write_word_2(flash_info_t * info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+#endif /* CFG_FLASH_2ND_16BIT_DEV */
diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile
new file mode 100755
index 0000000..4a3927b
--- /dev/null
+++ b/board/amcc/ebony/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/ebony/config.mk b/board/amcc/ebony/config.mk
new file mode 100755
index 0000000..e5722dd
--- /dev/null
+++ b/board/amcc/ebony/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
new file mode 100755
index 0000000..a2595ee
--- /dev/null
+++ b/board/amcc/ebony/ebony.c
@@ -0,0 +1,289 @@
+/*
+ *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
+
+long int fixed_sdram(void);
+
+int board_early_init_f(void)
+{
+	uint reg;
+	unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+	unsigned char status;
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(ebccfga, xbcfg);
+	reg = mfdcr(ebccfgd);
+	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
+
+	mtebc(pb1ap, 0x02815480);	/* NVRAM/RTC */
+	mtebc(pb1cr, 0x48018000);	/* BA=0x480 1MB R/W 8-bit */
+	mtebc(pb7ap, 0x01015280);	/* FPGA registers */
+	mtebc(pb7cr, 0x48318000);	/* BA=0x483 1MB R/W 8-bit */
+
+	/* read FPGA_REG0  and set the bus controller */
+	status = *fpga_base;
+	if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
+		mtebc(pb0ap, 0x9b015480);	/* FLASH/SRAM */
+		mtebc(pb0cr, 0xfff18000);	/* BAS=0xfff 1MB R/W 8-bit */
+		mtebc(pb2ap, 0x9b015480);	/* 4MB FLASH */
+		mtebc(pb2cr, 0xff858000);	/* BAS=0xff8 4MB R/W 8-bit */
+	} else {
+		mtebc(pb0ap, 0x9b015480);	/* 4MB FLASH */
+		mtebc(pb0cr, 0xffc58000);	/* BAS=0xffc 4MB R/W 8-bit */
+
+		/* set CS2 if FLASH_ONBD_N == 0 */
+		if (!(status & FLASH_ONBD_N)) {
+			mtebc(pb2ap, 0x9b015480);	/* FLASH/SRAM */
+			mtebc(pb2cr, 0xff818000);	/* BAS=0xff8 4MB R/W 8-bit */
+		}
+	}
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+long int initdram(int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram(0);
+#else
+	dram_size = fixed_sdram();
+#endif
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:    128 MB, non-ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram(void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
+	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram(mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0                 */
+	mtsdram(mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram(mem_tr0, 0x410a4012);	/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3                       */
+	mtsdram(mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram(mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB     */
+	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	udelay(400);		/* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram(mem_cfg0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit           */
+	for (;;) {
+		mfsdram(mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB                           */
+}
+#endif				/* !defined(CONFIG_SPD_EEPROM) */
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+     *	The ebony board is always configured as the host & requires the
+     *	PCI arbiter to be enabled.
+	 *--------------------------------------------------------------------------*/
+	strap = mfdcr(cpc0_strp1);
+	if ((strap & 0x00100000) == 0) {
+		printf("PCI: CPC0_STRP1[PAE] not set.\n");
+		return 0;
+	}
+
+	return 1;
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r(PCIX0_PIM0SA, 0);	/* disable */
+	out32r(PCIX0_PIM1SA, 0);	/* disable */
+	out32r(PCIX0_PIM2SA, 0);	/* disable */
+	out32r(PCIX0_EROMBA, 0);	/* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+     * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+	out32r(PCIX0_PIM0LAH, 0);
+	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+
+	out32r(PCIX0_BAR0, 0);
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
+	out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+
+	out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* The ebony board is always configured as host. */
+	return (1);
+}
+#endif				/* defined(CONFIG_PCI) */
diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c
new file mode 100755
index 0000000..e8fbbc4
--- /dev/null
+++ b/board/amcc/ebony/flash.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+#define     BOOT_SMALL_FLASH        32	/* 00100000 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
+
+#define     BOOT_SMALL_FLASH_VAL    4
+#define     FLASH_ONBD_N_VAL        2
+#define     FLASH_SRAM_SEL_VAL      1
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+	{0xffc00000, 0xffe00000, 0xff880000},	/* 0:000: configuraton 3 */
+	{0xffc00000, 0xffe00000, 0xff800000},	/* 1:001: configuraton 4 */
+	{0xffc00000, 0xffe00000, 0x00000000},	/* 2:010: configuraton 7 */
+	{0xffc00000, 0xffe00000, 0x00000000},	/* 3:011: configuraton 8 */
+	{0xff800000, 0xffa00000, 0xfff80000},	/* 4:100: configuraton 1 */
+	{0xff800000, 0xffa00000, 0xfff00000},	/* 5:101: configuraton 2 */
+	{0xffc00000, 0xffe00000, 0x00000000},	/* 6:110: configuraton 5 */
+	{0xffc00000, 0xffe00000, 0x00000000}	/* 7:111: configuraton 6 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned short index = 0;
+	int i;
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	/* check the bitmap of switch status */
+	if (switch_status & BOOT_SMALL_FLASH) {
+		index += BOOT_SMALL_FLASH_VAL;
+	}
+	if (switch_status & FLASH_ONBD_N) {
+		index += FLASH_ONBD_N_VAL;
+	}
+	if (switch_status & FLASH_SRAM_SEL) {
+		index += FLASH_SRAM_SEL_VAL;
+	}
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *)
+					   flash_addr_table[index][i],
+					   &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			       i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[2]);
+#ifdef CFG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[2]);
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[2]);
+#endif
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S
new file mode 100755
index 0000000..cc8f8b4
--- /dev/null
+++ b/board/amcc/ebony/init.S
@@ -0,0 +1,96 @@
+/*
+*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+    tlbtab_end
diff --git a/board/amcc/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds
new file mode 100755
index 0000000..5a1c5b1
--- /dev/null
+++ b/board/amcc/ebony/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/amcc/ebony/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile
new file mode 100755
index 0000000..5654f91
--- /dev/null
+++ b/board/amcc/luan/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+OBJS   += flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk
new file mode 100755
index 0000000..f52c206
--- /dev/null
+++ b/board/amcc/luan/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h
new file mode 100755
index 0000000..05362e0
--- /dev/null
+++ b/board/amcc/luan/epld.h
@@ -0,0 +1,85 @@
+#define EPLD0_FSEL_FB2		0x80
+#define EPLD0_BOOT_SMALL_FLASH	0x40	/* 0 boot from large flash, 1 from small flash */
+#define EPLD0_RAW_CARD_BIT0	0x20	/* raw card EC level */
+#define EPLD0_RAW_CARD_BIT1	0x10
+#define EPLD0_RAW_CARD_BIT2	0x08
+#define EPLD0_EXT_ARB_SEL_N	0x04	/* 0 select on-board ext PCI-X, 1 internal arbiter */
+#define EPLD0_FLASH_ONBRD_N	0x02	/* 0 small flash/SRAM active, 1 block access */
+#define EPLD0_FLASH_SRAM_SEL_N	0x01	/* 0 SRAM at mem top, 1 small flash at mem top */
+
+#define EPLD1_CLK_CNTL0		0x80	/* FSEL-FB1 of MPC9772 */
+#define EPLD1_PCIX0_CNTL1	0x40	/* S*0 of 9531 */
+#define EPLD1_PCIX0_CNTL2	0x20	/* S*1 of 9531 */
+#define EPLD1_CLK_CNTL3		0x10	/* FSEL-B1 of MPC9772 */
+#define EPLD1_CLK_CNTL4		0x08	/* FSEL-B0 of MPC9772 */
+#define EPLD1_MASTER_CLOCK6	0x04	/* clock source select 6 */
+#define EPLD1_MASTER_CLOCK7	0x02	/* clock source select 7 */
+#define EPLD1_MASTER_CLOCK8	0x01	/* clock source select 8 */
+
+#define EPLD2_ETH_MODE_10	0x80	/* Ethernet mode 10   (default = 1) */
+#define EPLD2_ETH_MODE_100	0x40	/* Ethernet mode 100  (default = 1) */
+#define EPLD2_ETH_MODE_1000	0x20	/* Ethernet mode 1000 (default = 1) */
+#define EPLD2_ETH_DUPLEX_MODE	0x10	/* Ethernet force full duplex mode */
+#define EPLD2_RESET_ETH_N	0x08	/* Ethernet reset (default = 1) */
+#define EPLD2_ETH_AUTO_NEGO	0x04	/* Ethernet auto negotiation */
+#define EPLD2_DEFAULT_UART_N	0x01	/* 0 select DSR DTR for UART1 */
+
+#define EPLD3_STATUS_LED4	0x08	/* status LED 8 (1 = LED on) */
+#define EPLD3_STATUS_LED3	0x04	/* status LED 4 (1 = LED on) */
+#define EPLD3_STATUS_LED2	0x02	/* status LED 2 (1 = LED on) */
+#define EPLD3_STATUS_LED1	0x01	/* status LED 1 (1 = LED on) */
+
+#define EPLD4_PCIX0_VTH1	0x80	/* PCI-X 0 VTH1 status */
+#define EPLD4_PCIX0_VTH2	0x40	/* PCI-X 0 VTH2 status */
+#define EPLD4_PCIX0_VTH3	0x20	/* PCI-X 0 VTH3 status */
+#define EPLD4_PCIX0_VTH4	0x10	/* PCI-X 0 VTH4 status */
+#define EPLD4_PCIX1_VTH1	0x08	/* PCI-X 1 VTH1 status */
+#define EPLD4_PCIX1_VTH2	0x04	/* PCI-X 1 VTH2 status */
+#define EPLD4_PCIX1_VTH3	0x02	/* PCI-X 1 VTH3 status */
+#define EPLD4_PCIX1_VTH4	0x01	/* PCI-X 1 VTH4 status */
+
+#define EPLD5_PCIX0_INT0	0x80	/* PCIX0 INT0 status, write 0 to reset */
+#define EPLD5_PCIX0_INT1	0x40	/* PCIX0 INT1 status, write 0 to reset */
+#define EPLD5_PCIX0_INT2	0x20	/* PCIX0 INT2 status, write 0 to reset */
+#define EPLD5_PCIX0_INT3	0x10	/* PCIX0 INT3 status, write 0 to reset */
+#define EPLD5_PCIX1_INT0	0x08	/* PCIX1 INT0 status, write 0 to reset */
+#define EPLD5_PCIX1_INT1	0x04	/* PCIX1 INT1 status, write 0 to reset */
+#define EPLD5_PCIX1_INT2	0x02	/* PCIX1 INT2 status, write 0 to reset */
+#define EPLD5_PCIX1_INT3	0x01	/* PCIX1 INT3 status, write 0 to reset */
+
+#define EPLD6_PCIX0_RESET_CTL	0x80	/* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCIX1_RESET_CTL	0x40	/* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_ETH_INT_MODE	0x20	/* 0=IRQ5 recv's external eth int */
+#define EPLD6_PCIX2_RESET_CTL	0x10	/* 0=enable slot reset, 1=disable slot reset */
+#define EPLD6_PCI1_CLKCNTL1	0x80	/* PCI1 clock control S*0 of 9531 */
+#define EPLD6_PCI1_CLKCNTL2	0x40	/* PCI1 clock control S*1 of 9531 */
+#define EPLD6_PCI2_CLKCNTL1	0x20	/* PCI2 clock control S*0 of 9531 */
+#define EPLD6_PCI2_CLKCNTL2	0x10	/* PCI2 clock control S*1 of 9531 */
+
+#define EPLD7_VTH1		0x80	/* PCI2 VTH1 status */
+#define EPLD7_VTH2		0x40	/* PCI2 VTH2 status */
+#define EPLD7_VTH3		0x20	/* PCI2 VTH3 status */
+#define EPLD7_VTH4		0x10	/* PCI2 VTH4 status */
+#define EPLD7_INTA_MODE		0x80	/* see S5 on SW2 for details */
+#define EPLD7_PCI_INT_MODE_N	0x40	/* see S1 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_GPIO	0x20	/* see S2 on SW2 for details */
+#define EPLD7_WRITE_ENABLE_INT	0x10	/* see S3 on SW2 for details */
+
+
+typedef struct {
+    unsigned char  status;		/* misc status */
+    unsigned char  clock;		/* clock status, PCI-X clock control */
+    unsigned char  ethuart;		/* Ethernet, UART status */
+    unsigned char  leds;		/* LED register */
+    unsigned char  vth01;		/* PCI0, PCI1 VTH register */
+    unsigned char  pciints;		/* PCI0, PCI1 interrupts */
+    unsigned char  pci2;		/* PCI2 interrupts, clock control */
+    unsigned char  vth2;		/* PCI2 VTH register */
+    unsigned char  filler1[4096-8];
+    unsigned char  gpio00;		/* GPIO bits  0-7 */
+    unsigned char  gpio08;		/* GPIO bits  8-15 */
+    unsigned char  gpio16;		/* GPIO bits 16-23 */
+    unsigned char  gpio24;		/* GPIO bits 24-31 */
+    unsigned char  filler2[4096-4];
+    unsigned char  version;		/* EPLD version */
+} epld_t;
diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c
new file mode 100755
index 0000000..d3c3c0d
--- /dev/null
+++ b/board/amcc/luan/flash.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = {
+	{0xff900000, 0xff980000, 0xffc00000},	/* 0:000: configuraton 3 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+	/* read FPGA base register FPGA_REG0 */
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *)
+					   flash_addr_table[index][i],
+					   &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			       i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[2]);
+#ifdef CFG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[2]);
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[2]);
+#endif
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
new file mode 100755
index 0000000..7830ebd
--- /dev/null
+++ b/board/amcc/luan/init.S
@@ -0,0 +1,132 @@
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+
+#if (CFG_LARGE_FLASH == 0xffc00000)	/* if booting from large flash */
+    /* large flash */
+    tlbentry( 0xffc00000,         SZ_1M, 0xffc00000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+    tlbentry( 0xffd00000,         SZ_1M, 0xffd00000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+    tlbentry( 0xffe00000,         SZ_1M, 0xffe00000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+    tlbentry( 0xfff00000,         SZ_1M, 0xfff00000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+
+    tlbentry( 0xff800000,         SZ_1M, 0xff800000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+    tlbentry( 0xff900000,         SZ_1M, 0xff900000,          1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
+#else					/* else booting from small flash */
+    tlbentry( 0xffe00000,         SZ_1M, 0xffe00000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+    tlbentry( 0xfff00000,         SZ_1M, 0xfff00000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+
+    tlbentry( 0xff800000,         SZ_1M, 0xff800000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+    tlbentry( 0xff900000,         SZ_1M, 0xff900000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+    tlbentry( 0xffa00000,         SZ_1M, 0xffa00000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+    tlbentry( 0xffb00000,         SZ_1M, 0xffb00000,          1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+#endif
+
+    tlbentry( CFG_EPLD_BASE,    SZ_256K, 0xff000000,          1, AC_R|AC_W|SA_G|SA_I )
+
+#if (CFG_SRAM_BASE != 0)		/* if SRAM up high and SDRAM at zero */
+    tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#elif (CFG_SMALL_FLASH == 0xff900000)	/* else SRAM at 0 */
+    tlbentry( 0x00000000,   SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+#elif (CFG_SMALL_FLASH == 0xfff00000)
+    tlbentry( 0x00000000,   SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
+#else
+    #error DONT KNOW SRAM LOCATION
+#endif
+
+    /* internal ram (l2 cache) */
+    tlbentry( CFG_ISRAM_BASE,    SZ_256K, 0x80000000,      0, AC_R|AC_W|AC_X|SA_I )
+
+    /* peripherals at f0000000 */
+    tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
+
+    /* PCI */
+#if (CONFIG_COMMANDS & CFG_CMD_PCI)
+    tlbentry( CFG_PCI_BASE,    SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
+#endif
+    tlbtab_end
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
new file mode 100755
index 0000000..c6b79a9
--- /dev/null
+++ b/board/amcc/luan/luan.c
@@ -0,0 +1,458 @@
+/*
+ * (C) Copyright 2005
+ * John Otken, jotken@softadvances.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include "epld.h"
+
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+/*************************************************************************
+ *  int board_early_init_f()
+ *
+ ************************************************************************/
+int board_early_init_f(void)
+{
+	volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
+
+	mtebc( pb0ap,  0x03800000 );	/* set chip selects */
+	mtebc( pb0cr,  0xffc58000 );	/* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
+	mtebc( pb1ap,  0x03800000 );
+	mtebc( pb1cr,  0xff018000 );	/* ebc0_b1cr, 1MB at 0xff000000 CS1 */
+	mtebc( pb2ap,  0x03800000 );
+	mtebc( pb2cr,  0xff838000 );	/* ebc0_b2cr, 2MB at 0xff800000 CS2 */
+
+	mtdcr( uic1sr, 0xffffffff );	/* Clear all interrupts */
+	mtdcr( uic1er, 0x00000000 );	/* disable all interrupts */
+	mtdcr( uic1cr, 0x00000000 );	/* Set Critical / Non Critical interrupts */
+	mtdcr( uic1pr, 0x7fff83ff );	/* Set Interrupt Polarities */
+	mtdcr( uic1tr, 0x001f8000 );	/* Set Interrupt Trigger Levels */
+	mtdcr( uic1vr, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr( uic1sr, 0x00000000 );	/* clear all interrupts */
+	mtdcr( uic1sr, 0xffffffff );
+
+	mtdcr( uic0sr, 0xffffffff );	/* Clear all interrupts */
+	mtdcr( uic0er, 0x00000000 );	/* disable all interrupts excepted cascade */
+	mtdcr( uic0cr, 0x00000001 );	/* Set Critical / Non Critical interrupts */
+	mtdcr( uic0pr, 0xffffffff );	/* Set Interrupt Polarities */
+	mtdcr( uic0tr, 0x01000004 );	/* Set Interrupt Trigger Levels */
+	mtdcr( uic0vr, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
+	mtdcr( uic0sr, 0x00000000 );	/* clear all interrupts */
+	mtdcr( uic0sr, 0xffffffff );
+
+	x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
+
+	return  0;
+}
+
+
+/*************************************************************************
+ *  int misc_init_r()
+ *
+ ************************************************************************/
+int misc_init_r(void)
+{
+	volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
+	x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
+
+	return  0;
+}
+
+
+/*************************************************************************
+ *  int checkboard()
+ *
+ ************************************************************************/
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Luan - AMCC PPC440SP Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return  0;
+}
+
+
+/*************************************************************************
+ *  long int fixed_sdram()
+ *
+ ************************************************************************/
+static long int fixed_sdram(void)
+{					/* DDR2 init from BDI2000 script */
+	mtdcr( 0x10, 0x00000021 );	/* MCIF0_MCOPT2 - zero DCEN bit */
+	mtdcr( 0x11, 0x84000000 );
+	mtdcr( 0x10, 0x00000020 );	/* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
+	mtdcr( 0x11, 0x2D122000 );
+	mtdcr( 0x10, 0x00000026 );	/* MCIF0_CODT  - die termination on */
+	mtdcr( 0x11, 0x00800026 );
+	mtdcr( 0x10, 0x00000081 );	/* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
+	mtdcr( 0x11, 0x82000800 );
+	mtdcr( 0x10, 0x00000080 );	/* MCIF0_CLKTR - advance addr clock by 180 deg */
+	mtdcr( 0x11, 0x80000000 );
+	mtdcr( 0x10, 0x00000040 );	/* MCIF0_MB0CF - turn on CS0, N x 10 coll */
+	mtdcr( 0x11, 0x00000201 );
+	mtdcr( 0x10, 0x00000044 );	/* MCIF0_MB1CF - turn on CS0, N x 10 coll */
+	mtdcr( 0x11, 0x00000201 );
+	mtdcr( 0x10, 0x00000030 );	/* MCIF0_RTR   - refresh every 7.8125uS */
+	mtdcr( 0x11, 0x08200000 );
+	mtdcr( 0x10, 0x00000085 );	/* MCIF0_SDTR1 - timing register 1 */
+	mtdcr( 0x11, 0x80201000 );
+	mtdcr( 0x10, 0x00000086 );	/* MCIF0_SDTR2 - timing register 2 */
+	mtdcr( 0x11, 0x42103242 );
+	mtdcr( 0x10, 0x00000087 );	/* MCIF0_SDTR3 - timing register 3 */
+	mtdcr( 0x11, 0x0C100D14 );
+	mtdcr( 0x10, 0x00000088 );	/* MCIF0_MMODE - CAS is 4 cycles */
+	mtdcr( 0x11, 0x00000642 );
+	mtdcr( 0x10, 0x00000089 );	/* MCIF0_MEMODE - diff DQS disabled */
+	mtdcr( 0x11, 0x00000400 );	/*		  ODT term disabled */
+
+	mtdcr( 0x10, 0x00000050 );	/* MCIF0_INITPLR0 - NOP */
+	mtdcr( 0x11, 0x81b80000 );
+	mtdcr( 0x10, 0x00000051 );	/* MCIF0_INITPLR1 - PRE */
+	mtdcr( 0x11, 0x82100400 );
+	mtdcr( 0x10, 0x00000052 );	/* MCIF0_INITPLR2 - EMR2 */
+	mtdcr( 0x11, 0x80820000 );
+	mtdcr( 0x10, 0x00000053 );	/* MCIF0_INITPLR3 - EMR3 */
+	mtdcr( 0x11, 0x80830000 );
+	mtdcr( 0x10, 0x00000054 );	/* MCIF0_INITPLR4 - EMR DLL ENABLE */
+	mtdcr( 0x11, 0x80810000 );
+	mtdcr( 0x10, 0x00000055 );	/* MCIF0_INITPLR5 - MR DLL RESET */
+	mtdcr( 0x11, 0x80800542 );
+	mtdcr( 0x10, 0x00000056 );	/* MCIF0_INITPLR6 - PRE */
+	mtdcr( 0x11, 0x82100400 );
+	mtdcr( 0x10, 0x00000057 );	/* MCIF0_INITPLR7 - refresh */
+	mtdcr( 0x11, 0x99080000 );
+	mtdcr( 0x10, 0x00000058 );	/* MCIF0_INITPLR8 */
+	mtdcr( 0x11, 0x99080000 );
+	mtdcr( 0x10, 0x00000059 );	/* MCIF0_INITPLR9 */
+	mtdcr( 0x11, 0x99080000 );
+	mtdcr( 0x10, 0x0000005A );	/* MCIF0_INITPLR10 */
+	mtdcr( 0x11, 0x99080000 );
+	mtdcr( 0x10, 0x0000005B );	/* MCIF0_INITPLR11 - MR */
+	mtdcr( 0x11, 0x80800442 );
+	mtdcr( 0x10, 0x0000005C );	/* MCIF0_INITPLR12 - EMR OCD Default */
+	mtdcr( 0x11, 0x80810380 );
+	mtdcr( 0x10, 0x0000005D );	/* MCIF0_INITPLR13 - EMR OCD exit */
+	mtdcr( 0x11, 0x80810000 );
+	udelay( 10*1000 );
+
+	mtdcr( 0x10, 0x00000021 );	/* MCIF0_MCOPT2 - execute preloaded init */
+	mtdcr( 0x11, 0x28000000 );	/*		  set DC_EN */
+	udelay( 100*1000 );
+
+	mtdcr( 0x40, 0x0000F800 );	/* MQ0_B0BAS: base addr 00000000 / 256MB */
+	mtdcr( 0x41, 0x1000F800 );	/* MQ0_B1BAS: base addr 10000000 / 256MB */
+
+	mtdcr( 0x10, 0x00000078 );	/* MCIF0_RDCC - auto set read stage */
+	mtdcr( 0x11, 0x00000000 );
+	mtdcr( 0x10, 0x00000070 );	/* MCIF0_RQDC - read DQS delay control */
+	mtdcr( 0x11, 0x8000003A );	/*		enabled, frac DQS delay */
+	mtdcr( 0x10, 0x00000074 );	/* MCIF0_RFDC - two clock feedback delay */
+	mtdcr( 0x11, 0x00000200 );
+
+	return  512 << 20;
+}
+
+
+/*************************************************************************
+ *  long int initdram
+ *
+ ************************************************************************/
+long int initdram( int board_type )
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram (0);
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+	return  dram_size;
+}
+
+
+/*************************************************************************
+ *  int testdram()
+ *
+ ************************************************************************/
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *) 0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_KBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+
+	return  0;
+}
+#endif
+
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init( struct pci_controller *hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 *	The luan board is always configured as the host & requires the
+	 *	PCI arbiter to be enabled.
+	 *--------------------------------------------------------------------------*/
+	mfsdr(sdr_sdstp1, strap);
+	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
+		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+
+		return  0;
+	}
+
+	return  1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	return  1;
+}
+#endif				/* defined(CONFIG_PCI) */
+
+
+/*************************************************************************
+ *  hw_watchdog_reset
+ *
+ *	This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+}
+#endif
+
+
+/*************************************************************************
+ *  int on_off()
+ *
+ ************************************************************************/
+static int on_off( const char *s )
+{
+	if (strcmp(s, "on") == 0) {
+		return  1;
+	} else if (strcmp(s, "off") == 0) {
+		return  0;
+	}
+	return  -1;
+}
+
+
+/*************************************************************************
+ *  void l2cache_disable()
+ *
+ ************************************************************************/
+static void l2cache_disable(void)
+{
+	mtdcr( l2_cache_cfg, 0 );
+}
+
+
+/*************************************************************************
+ *  void l2cache_enable()
+ *
+ ************************************************************************/
+static void l2cache_enable(void)	/* see p258 7.4.1 Enabling L2 Cache */
+{
+	mtdcr( l2_cache_cfg, 0x80000000 );	/* enable L2_MODE L2_CFG[L2M] */
+
+	mtdcr( l2_cache_addr, 0 );		/* set L2_ADDR with all zeros */
+
+	mtdcr( l2_cache_cmd, 0x80000000 );	/* issue HCLEAR command via L2_CMD */
+
+	while (!(mfdcr( l2_cache_stat ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
+
+	mtdcr( l2_cache_cmd, 0x10000000 );	/* clear cache errors L2_CMD[CCP] */
+
+	mtdcr( l2_cache_cmd, 0x08000000 );	/* clear tag errors L2_CMD[CTE] */
+
+	mtdcr( l2_cache_snp0, 0 );		/* snoop registers */
+	mtdcr( l2_cache_snp1, 0 );
+
+	__asm__ volatile ("sync");		/* msync */
+
+	mtdcr( l2_cache_cfg, 0xe0000000 );	/* inst and data use L2 */
+
+	__asm__ volatile ("sync");
+}
+
+
+/*************************************************************************
+ *  int l2cache_status()
+ *
+ ************************************************************************/
+static int l2cache_status(void)
+{
+	return  (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
+}
+
+
+/*************************************************************************
+ *  int do_l2cache()
+ *
+ ************************************************************************/
+int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
+{
+	switch (argc) {
+	case 2:			/* on / off	*/
+		switch (on_off(argv[1])) {
+		case 0:	l2cache_disable();
+			break;
+		case 1:	l2cache_enable();
+			break;
+		}
+		/* FALL TROUGH */
+	case 1:			/* get status */
+		printf ("L2 Cache is %s\n",
+			l2cache_status() ? "ON" : "OFF");
+		return 0;
+	default:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	return  0;
+}
+
+
+U_BOOT_CMD(
+	l2cache,   2,   1,     do_l2cache,
+	"l2cache  - enable or disable L2 cache\n",
+	"[on, off]\n"
+	"    - enable or disable L2 cache\n"
+	);
diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds
new file mode 100755
index 0000000..d122f49
--- /dev/null
+++ b/board/amcc/luan/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/amcc/luan/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile
new file mode 100755
index 0000000..af223d2
--- /dev/null
+++ b/board/amcc/ocotea/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/ocotea/config.mk b/board/amcc/ocotea/config.mk
new file mode 100755
index 0000000..9e18335
--- /dev/null
+++ b/board/amcc/ocotea/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMCC 440GX Reference Platform (Ocotea) board
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c
new file mode 100755
index 0000000..5614e20
--- /dev/null
+++ b/board/amcc/ocotea/flash.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+#define     BOOT_SMALL_FLASH        0x40	/* 01000000 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
+
+#define     BOOT_SMALL_FLASH_VAL    4
+#define     FLASH_ONBD_N_VAL        2
+#define     FLASH_SRAM_SEL_VAL      1
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+	{0xFF800000, 0xFF880000, 0xFFC00000},	/* 0:000: configuraton 4 */
+	{0xFF900000, 0xFF980000, 0xFFC00000},	/* 1:001: configuraton 3 */
+	{0x00000000, 0x00000000, 0x00000000},	/* 2:010: configuraton 8 */
+	{0x00000000, 0x00000000, 0x00000000},	/* 3:011: configuraton 7 */
+	{0xFFE00000, 0xFFF00000, 0xFF800000},	/* 4:100: configuraton 2 */
+	{0xFFF00000, 0xFFF80000, 0xFF800000},	/* 5:101: configuraton 1 */
+	{0x00000000, 0x00000000, 0x00000000},	/* 6:110: configuraton 6 */
+	{0x00000000, 0x00000000, 0x00000000}	/* 7:111: configuraton 5 */
+};
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned short index = 0;
+	int i;
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	/* check the bitmap of switch status */
+	if (switch_status & BOOT_SMALL_FLASH) {
+		index += BOOT_SMALL_FLASH_VAL;
+	}
+	if (switch_status & FLASH_ONBD_N) {
+		index += FLASH_ONBD_N_VAL;
+	}
+	if (switch_status & FLASH_SRAM_SEL) {
+		index += FLASH_SRAM_SEL_VAL;
+	}
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] =
+		    flash_get_size((vu_long *) flash_addr_table[index][i],
+				   &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf
+			    ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			     i, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#ifdef CFG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S
new file mode 100755
index 0000000..e33427a
--- /dev/null
+++ b/board/amcc/ocotea/init.S
@@ -0,0 +1,97 @@
+/*
+*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)	( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+    tlbtab_end
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
new file mode 100755
index 0000000..d1a29c5
--- /dev/null
+++ b/board/amcc/ocotea/ocotea.c
@@ -0,0 +1,528 @@
+/*
+ *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include "ocotea.h"
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <ppc4xx_enet.h>
+
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
+
+long int fixed_sdram (void);
+void fpga_init (void);
+
+int board_early_init_f (void)
+{
+	unsigned long mfr;
+	unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned long cs0_base;
+	unsigned long cs0_size;
+	unsigned long cs0_twt;
+	unsigned long cs2_base;
+	unsigned long cs2_size;
+	unsigned long cs2_twt;
+
+	/*-------------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------------*/
+	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
+	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
+	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
+	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
+
+	/*-------------------------------------------------------------------------+
+	  | FPGA. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	if (switch_status & 0x40) {
+		cs0_base = 0xFFE00000;
+		cs0_size = EBC_BXCR_BS_2MB;
+		cs0_twt = 8;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_4MB;
+		cs2_twt = 10;
+	} else {
+		cs0_base = 0xFFC00000;
+		cs0_size = EBC_BXCR_BS_4MB;
+		cs0_twt = 10;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_2MB;
+		cs2_twt = 8;
+	}
+
+	/*-------------------------------------------------------------------------+
+	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
+	      cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | 4 MB FLASH. Initialize bank 2 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
+	      cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*-------------------------------------------------------------------------+
+	  | FPGA. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000); /* clear all */
+	mtdcr (uicb0er, 0x00000000); /* disable all */
+	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000); /* */
+	mtdcr (uicb0tr, 0x00000000); /* */
+	mtdcr (uicb0vr, 0x00000001); /* */
+	mfsdr (sdr_mfr, mfr);
+	mfr &= ~SDR0_MFR_ECS_MASK;
+/*	mtsdr(sdr_mfr, mfr); */
+	fpga_init();
+
+	return 0;
+}
+
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
+	if (s != NULL) {
+		puts (", serial# ");
+		puts (s);
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram (0);
+#else
+	dram_size = fixed_sdram ();
+#endif
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:    128 MB, non-ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0         */
+	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0                 */
+	mtsdram (mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram (mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (mem_tr0, 0x410a4012);	/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3                       */
+	mtsdram (mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB     */
+	mtsdram (mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_cfg0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit           */
+	for (;;) {
+		mfsdram (mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB                           */
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 *	The ocotea board is always configured as the host & requires the
+	 *	PCI arbiter to be enabled.
+	 *--------------------------------------------------------------------------*/
+	mfsdr(sdr_sdstp1, strap);
+	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
+		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+		return 0;
+	}
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+    /* The ocotea board is always configured as host. */
+    return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+
+void fpga_init(void)
+{
+	unsigned long group;
+	unsigned long sdr0_pfc0;
+	unsigned long sdr0_pfc1;
+	unsigned long sdr0_cust0;
+	unsigned long pvr;
+
+	mfsdr (sdr_pfc0, sdr0_pfc0);
+	mfsdr (sdr_pfc1, sdr0_pfc1);
+	group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
+	pvr = get_pvr ();
+
+	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
+	if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
+		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
+		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+		out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+		     FPGA_REG2_EXT_INTFACE_ENABLE);
+		mtsdr (sdr_pfc0, sdr0_pfc0);
+		mtsdr (sdr_pfc1, sdr0_pfc1);
+	} else {
+		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
+		switch (group)
+		{
+		case 0:
+		case 1:
+		case 2:
+			/* CPU trace A */
+			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+			     FPGA_REG2_EXT_INTFACE_ENABLE);
+			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
+			mtsdr (sdr_pfc0, sdr0_pfc0);
+			mtsdr (sdr_pfc1, sdr0_pfc1);
+			break;
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+			/* CPU trace B - Over EBMI */
+			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
+			mtsdr (sdr_pfc0, sdr0_pfc0);
+			mtsdr (sdr_pfc1, sdr0_pfc1);
+			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
+			     FPGA_REG2_EXT_INTFACE_DISABLE);
+			break;
+		}
+	}
+
+	/* Initialize the ethernet specific functions in the fpga */
+	mfsdr(sdr_pfc1, sdr0_pfc1);
+	mfsdr(sdr_cust0, sdr0_cust0);
+	if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
+	    ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
+	     (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
+	{
+		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+		{
+			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+			     FPGA_REG3_ENET_GROUP7);
+		}
+		else
+		{
+			if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
+			{
+				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+				     FPGA_REG3_ENET_GROUP7);
+			}
+			else
+			{
+				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+				     FPGA_REG3_ENET_GROUP8);
+			}
+		}
+	}
+	else
+	{
+		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+		{
+			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
+			     FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+		}
+		else
+		{
+			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
+			     FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
+		}
+	}
+	out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
+	     FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
+	     FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
+
+	/* reset the gigabyte phy if necessary */
+	if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
+	{
+		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
+		{
+			out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
+			udelay(10000);
+			out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
+		}
+		else
+		{
+			out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
+			udelay(10000);
+			out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
+		}
+	}
+
+	/*
+	 * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
+	 */
+	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
+		out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
+		udelay(10000);
+		out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
+	}
+
+	/* Turn off the LED's */
+	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
+	     FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
+	     FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
+
+	return;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+	return (ctrlc());
+}
+#endif
diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h
new file mode 100755
index 0000000..95ce1fd
--- /dev/null
+++ b/board/amcc/ocotea/ocotea.h
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Board specific FPGA stuff ... */
+#define FPGA_REG0                       (CFG_FPGA_BASE + 0x00)
+#define   FPGA_REG0_SSCG_MASK             0x80
+#define   FPGA_REG0_SSCG_DISABLE          0x00
+#define   FPGA_REG0_SSCG_ENABLE           0x80
+#define   FPGA_REG0_BOOT_MASK             0x40
+#define   FPGA_REG0_BOOT_LARGE_FLASH      0x00
+#define   FPGA_REG0_BOOT_SMALL_FLASH      0x40
+#define   FPGA_REG0_ECLS_MASK             0x38  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_0                0x20  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_1                0x10  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_2                0x08  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER1             0x00  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER3             0x08  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER4             0x10  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER5             0x18  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER2             0x20  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER6             0x28  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER7             0x30  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ECLS_VER8             0x38  /* New for Ocotea Rev 2 */
+#define   FPGA_REG0_ARBITER_MASK          0x04
+#define   FPGA_REG0_ARBITER_EXT           0x00
+#define   FPGA_REG0_ARBITER_INT           0x04
+#define   FPGA_REG0_ONBOARD_FLASH_MASK    0x02
+#define   FPGA_REG0_ONBOARD_FLASH_ENABLE  0x00
+#define   FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02
+#define   FPGA_REG0_FLASH                 0x01
+#define FPGA_REG1                       (CFG_FPGA_BASE + 0x01)
+#define   FPGA_REG1_9772_FSELFBX_MASK     0x80
+#define   FPGA_REG1_9772_FSELFBX_6        0x00
+#define   FPGA_REG1_9772_FSELFBX_10       0x80
+#define   FPGA_REG1_9531_SX_MASK          0x60
+#define   FPGA_REG1_9531_SX_33MHZ         0x00
+#define   FPGA_REG1_9531_SX_100MHZ        0x20
+#define   FPGA_REG1_9531_SX_66MHZ         0x40
+#define   FPGA_REG1_9531_SX_133MHZ        0x60
+#define   FPGA_REG1_9772_FSELBX_MASK      0x18
+#define   FPGA_REG1_9772_FSELBX_4         0x00
+#define   FPGA_REG1_9772_FSELBX_6         0x08
+#define   FPGA_REG1_9772_FSELBX_8         0x10
+#define   FPGA_REG1_9772_FSELBX_10        0x18
+#define   FPGA_REG1_SOURCE_MASK           0x07
+#define   FPGA_REG1_SOURCE_TC             0x00
+#define   FPGA_REG1_SOURCE_66MHZ          0x01
+#define   FPGA_REG1_SOURCE_50MHZ          0x02
+#define   FPGA_REG1_SOURCE_33MHZ          0x03
+#define   FPGA_REG1_SOURCE_25MHZ          0x04
+#define   FPGA_REG1_SOURCE_SSDIV1         0x05
+#define   FPGA_REG1_SOURCE_SSDIV2         0x06
+#define   FPGA_REG1_SOURCE_SSDIV4         0x07
+#define FPGA_REG2                       (CFG_FPGA_BASE + 0x02)
+#define   FPGA_REG2_TC0                   0x80
+#define   FPGA_REG2_TC1                   0x40
+#define   FPGA_REG2_TC2                   0x20
+#define   FPGA_REG2_TC3                   0x10
+#define   FPGA_REG2_GIGABIT_RESET_DISABLE 0x08   /*Use on Ocotea pass 2 boards*/
+#define   FPGA_REG2_EXT_INTFACE_MASK      0x04
+#define   FPGA_REG2_EXT_INTFACE_ENABLE    0x00
+#define   FPGA_REG2_EXT_INTFACE_DISABLE   0x04
+#define   FPGA_REG2_SMII_RESET_DISABLE    0x02   /*Use on Ocotea pass 3 boards*/
+#define   FPGA_REG2_DEFAULT_UART1_N       0x01
+#define FPGA_REG3                       (CFG_FPGA_BASE + 0x03)
+#define   FPGA_REG3_GIGABIT_RESET_DISABLE 0x80   /*Use on Ocotea pass 1 boards*/
+#define   FPGA_REG3_ENET_MASK1            0x70   /*Use on Ocotea pass 1 boards*/
+#define   FPGA_REG3_ENET_MASK2            0xF0   /*Use on Ocotea pass 2 boards*/
+#define   FPGA_REG3_ENET_GROUP0           0x00
+#define   FPGA_REG3_ENET_GROUP1           0x10
+#define   FPGA_REG3_ENET_GROUP2           0x20
+#define   FPGA_REG3_ENET_GROUP3           0x30
+#define   FPGA_REG3_ENET_GROUP4           0x40
+#define   FPGA_REG3_ENET_GROUP5           0x50
+#define   FPGA_REG3_ENET_GROUP6           0x60
+#define   FPGA_REG3_ENET_GROUP7           0x70
+#define   FPGA_REG3_ENET_GROUP8           0x80   /*Use on Ocotea pass 2 boards*/
+#define   FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/
+#define   FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/
+#define   FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/
+#define   FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/
+#define   FPGA_REG3_STAT_MASK             0x0F
+#define   FPGA_REG3_STAT_LED8_ENAB        0x08
+#define   FPGA_REG3_STAT_LED4_ENAB        0x04
+#define   FPGA_REG3_STAT_LED2_ENAB        0x02
+#define   FPGA_REG3_STAT_LED1_ENAB        0x01
+#define   FPGA_REG3_STAT_LED8_DISAB       0x00
+#define   FPGA_REG3_STAT_LED4_DISAB       0x00
+#define   FPGA_REG3_STAT_LED2_DISAB       0x00
+#define   FPGA_REG3_STAT_LED1_DISAB       0x00
+#define FPGA_REG4                       (CFG_FPGA_BASE + 0x04)
+#define   FPGA_REG4_GPHY_MODE10           0x80
+#define   FPGA_REG4_GPHY_MODE100          0x40
+#define   FPGA_REG4_GPHY_MODE1000         0x20
+#define   FPGA_REG4_GPHY_FRC_DPLX         0x10
+#define   FPGA_REG4_GPHY_ANEG_DIS         0x08
+#define   FPGA_REG4_CONNECT_PHYS          0x04
+
+
+#define   SDR0_CUST0_ENET3_MASK         0x00000080
+#define   SDR0_CUST0_ENET3_COPPER       0x00000000
+#define   SDR0_CUST0_ENET3_FIBER        0x00000080
+#define   SDR0_CUST0_RGMII3_MASK        0x00000070
+#define   SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
+#define   SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
+#define   SDR0_CUST0_RGMII3_DISAB       0x00000000
+#define   SDR0_CUST0_RGMII3_RTBI        0x00000040
+#define   SDR0_CUST0_RGMII3_RGMII       0x00000050
+#define   SDR0_CUST0_RGMII3_TBI         0x00000060
+#define   SDR0_CUST0_RGMII3_GMII        0x00000070
+#define   SDR0_CUST0_ENET2_MASK         0x00000008
+#define   SDR0_CUST0_ENET2_COPPER       0x00000000
+#define   SDR0_CUST0_ENET2_FIBER        0x00000008
+#define   SDR0_CUST0_RGMII2_MASK        0x00000007
+#define   SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
+#define   SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
+#define   SDR0_CUST0_RGMII2_DISAB       0x00000000
+#define   SDR0_CUST0_RGMII2_RTBI        0x00000004
+#define   SDR0_CUST0_RGMII2_RGMII       0x00000005
+#define   SDR0_CUST0_RGMII2_TBI         0x00000006
+#define   SDR0_CUST0_RGMII2_GMII        0x00000007
diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds
new file mode 100755
index 0000000..316fee8
--- /dev/null
+++ b/board/amcc/ocotea/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/amcc/ocotea/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile
new file mode 100755
index 0000000..f5bda55
--- /dev/null
+++ b/board/amcc/walnut/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/walnut/config.mk b/board/amcc/walnut/config.mk
new file mode 100755
index 0000000..1bdf5e4
--- /dev/null
+++ b/board/amcc/walnut/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c
new file mode 100755
index 0000000..056f9b9
--- /dev/null
+++ b/board/amcc/walnut/flash.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif				/* DEBUG */
+
+/*
+ * include common flash code (for amcc boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+	    flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		       size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	if (CFG_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    &flash_info[0]);
+#ifdef CFG_ENV_IS_IN_FLASH
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+				    CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
+				    CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+				    &flash_info[0]);
+#endif
+
+		size_b1 = 0;
+		flash_info[0].size = size_b0;
+	} else {
+		/* 2 banks */
+		size_b1 =
+		    flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
+				   &flash_info[1]);
+
+		/* Re-do sizing to get full correct info */
+
+		if (size_b1) {
+			mtdcr(ebccfga, pb0cr);
+			pbcr = mfdcr(ebccfgd);
+			mtdcr(ebccfga, pb0cr);
+			base_b1 = -size_b1;
+			pbcr =
+			    (pbcr & 0x0001ffff) | base_b1 |
+			    (((size_b1 / 1024 / 1024) - 1) << 17);
+			mtdcr(ebccfgd, pbcr);
+			/*          printf("pb1cr = %x\n", pbcr); */
+		}
+
+		if (size_b0) {
+			mtdcr(ebccfga, pb1cr);
+			pbcr = mfdcr(ebccfgd);
+			mtdcr(ebccfga, pb1cr);
+			base_b0 = base_b1 - size_b0;
+			pbcr =
+			    (pbcr & 0x0001ffff) | base_b0 |
+			    (((size_b0 / 1024 / 1024) - 1) << 17);
+			mtdcr(ebccfgd, pbcr);
+			/*            printf("pb0cr = %x\n", pbcr); */
+		}
+
+		size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
+
+		flash_get_offsets(base_b0, &flash_info[0]);
+
+		/* monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    base_b0 + size_b0 - monitor_flash_len,
+				    base_b0 + size_b0 - 1, &flash_info[0]);
+
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 =
+			    flash_get_size((vu_long *) base_b1, &flash_info[1]);
+
+			flash_get_offsets(base_b1, &flash_info[1]);
+
+			/* monitor protection ON by default */
+			(void)flash_protect(FLAG_PROTECT_SET,
+					    base_b1 + size_b1 -
+					    monitor_flash_len,
+					    base_b1 + size_b1 - 1,
+					    &flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void)flash_protect(FLAG_PROTECT_CLEAR,
+					    base_b0 + size_b0 -
+					    monitor_flash_len,
+					    base_b0 + size_b0 - 1,
+					    &flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
+
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}			/* else 2 banks */
+	return (size_b0 + size_b1);
+}
+
+
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+				    base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+}
diff --git a/board/amcc/walnut/u-boot.lds b/board/amcc/walnut/u-boot.lds
new file mode 100755
index 0000000..1dcbab5
--- /dev/null
+++ b/board/amcc/walnut/u-boot.lds
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
new file mode 100755
index 0000000..f1a96a6
--- /dev/null
+++ b/board/amcc/walnut/walnut.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+int board_early_init_f(void)
+{
+	/*-------------------------------------------------------------------------+
+	  | Interrupt controller setup for the Walnut/Sycamore board.
+	  | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+	  |       IRQ 16    405GP internally generated; active low; level sensitive
+	  |       IRQ 17-24 RESERVED
+	  |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+	  |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+	  |       IRQ 27 (EXT IRQ 2) Not Used
+	  |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+	  |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	  |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+	  |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+	  | Note for Walnut board:
+	  |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+	  |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+	  |       interrupt. The FPGA must be read to determine which device
+	  |       caused the interrupt. The default setting of the FPGA clears
+	  |
+	  +-------------------------------------------------------------------------*/
+
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicer, 0x00000000);	/* disable all ints */
+	mtdcr(uiccr, 0x00000020);	/* set all but FPGA SMI to be non-critical */
+	mtdcr(uicpr, 0xFFFFFFE0);	/* set int polarities */
+	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	/* set UART1 control to select CTS/RTS */
+#define FPGA_BRDC       0xF0300004
+	*(volatile char *)(FPGA_BRDC) |= 0x1;
+
+	return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+	uint pvr = get_pvr();
+
+	if (pvr == PVR_405GPR_RB) {
+		puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
+	} else {
+		puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
+	}
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
+ */
+void sdram_init(void)
+{
+	return;
+}
+
+/*
+ * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ * the necessary info for SDRAM controller configuration
+ */
+long int initdram(int board_type)
+{
+	return spd_sdram(0);
+}
+
+int testdram(void)
+{
+	/* TODO: XXX XXX XXX */
+	printf("test: xxx MB - ok\n");
+
+	return (0);
+}
diff --git a/board/amcc/yellowstone/Makefile b/board/amcc/yellowstone/Makefile
new file mode 100755
index 0000000..47116d3
--- /dev/null
+++ b/board/amcc/yellowstone/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/yellowstone/config.mk b/board/amcc/yellowstone/config.mk
new file mode 100755
index 0000000..4ab0ea0
--- /dev/null
+++ b/board/amcc/yellowstone/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/yellowstone/init.S b/board/amcc/yellowstone/init.S
new file mode 100755
index 0000000..425ad08
--- /dev/null
+++ b/board/amcc/yellowstone/init.S
@@ -0,0 +1,112 @@
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_8M       0x00000060
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+
+    /*
+     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+     * speed up boot process. It is patched after relocation to enable SA_I
+     */
+    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+
+    /* PCI */
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+
+    /* USB 2.0 Device */
+    tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+
+    tlbtab_end
diff --git a/board/amcc/yellowstone/u-boot.lds b/board/amcc/yellowstone/u-boot.lds
new file mode 100755
index 0000000..a0ba44d
--- /dev/null
+++ b/board/amcc/yellowstone/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/amcc/yellowstone/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
new file mode 100755
index 0000000..8ddf910
--- /dev/null
+++ b/board/amcc/yellowstone/yellowstone.c
@@ -0,0 +1,553 @@
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+int board_early_init_f(void)
+{
+	register uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(ebccfga, xbcfg);
+	reg = mfdcr(ebccfgd);
+	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
+
+	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
+	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */
+
+	mtebc(pb1ap, 0x00000000);
+	mtebc(pb1cr, 0x00000000);
+
+	mtebc(pb2ap, 0x04814500);
+	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */
+
+	mtebc(pb3ap, 0x00000000);
+	mtebc(pb3cr, 0x00000000);
+
+	mtebc(pb4ap, 0x00000000);
+	mtebc(pb4cr, 0x00000000);
+
+	mtebc(pb5ap, 0x00000000);
+	mtebc(pb5cr, 0x00000000);
+
+	/*--------------------------------------------------------------------
+	 * Setup the GPIO pins
+	 *-------------------------------------------------------------------*/
+	/*CPLD cs */
+	/*setup Address lines for flash size 64Meg. */
+	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
+
+	/*setup emac */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+	/*UART1 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
+	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+
+	/* external interrupts IRQ0...3 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
+	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
+#if 0 /* test-only */
+	/*setup USB 2.0 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
+	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+#endif
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	/*--------------------------------------------------------------------
+	 * Setup other serial configuration
+	 *-------------------------------------------------------------------*/
+	mfsdr(sdr_pci0, reg);
+	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
+	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
+	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */
+
+	/*clear tmrclk divisor */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+
+	/*enable ethernet */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+
+#if 0 /* test-only */
+	/*enable usb 1.1 fs device and remove usb 2.0 reset */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+#endif
+
+	/*get rid of flash write protect */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	uint pbcr;
+	int size_val = 0;
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(ebccfga, pb0cr);
+	mtdcr(ebccfgd, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+/*************************************************************************
+ *  sdram_init -- doesn't use serial presence detect.
+ *
+ *  Assumes:    256 MB, ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+void sdram_tr1_set(int ram_address, int* tr1_value)
+{
+	int i;
+	int j, k;
+	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
+	int first_good = -1, last_bad = 0x1ff;
+
+	unsigned long test[NUM_TRIES] = {
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+	/* go through all possible SDRAM0_TR1[RDCT] values */
+	for (i=0; i<=0x1ff; i++) {
+		/* set the current value for TR1 */
+		mtsdram(mem_tr1, (0x80800800 | i));
+
+		/* write values */
+		for (j=0; j<NUM_TRIES; j++) {
+			ram_pointer[j] = test[j];
+
+			/* clear any cache at ram location */
+			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+		}
+
+		/* read values back */
+		for (j=0; j<NUM_TRIES; j++) {
+			for (k=0; k<NUM_READS; k++) {
+				/* clear any cache at ram location */
+				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+				if (ram_pointer[j] != test[j])
+					break;
+			}
+
+			/* read error */
+			if (k != NUM_READS) {
+				break;
+			}
+		}
+
+		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
+		if (j == NUM_TRIES) {
+			if (first_good == -1)
+				first_good = i;		/* found beginning of window */
+		} else { /* bad read */
+			/* if we have not had a good read then don't care */
+			if(first_good != -1) {
+				/* first failure after a good read */
+				last_bad = i-1;
+				break;
+			}
+		}
+	}
+
+	/* return the current value for TR1 */
+	*tr1_value = (first_good + last_bad) / 2;
+}
+
+void sdram_init(void)
+{
+	register uint reg;
+	int tr1_bank1, tr1_bank2;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
+	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram(mem_clktr, 0x40000000);	/* ?? */
+	mtsdram(mem_wddctr, 0x40000000);	/* ?? */
+
+	/*clear this first, if the DDR is enabled by a debugger
+	  then you can not make changes. */
+	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */
+
+	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
+	mtsdram(mem_rtr, 0x04080000);	/* ?? */
+	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	mtsdram(mem_cfg0, 0x34000000);	/* Disable EEC */
+	udelay(400);		/* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram(mem_cfg0, 0x84000000);	/* Enable */
+
+	for (;;) {
+		mfsdram(mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	sdram_tr1_set(0x00000000, &tr1_bank1);
+	sdram_tr1_set(0x08000000, &tr1_bank2);
+	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
+}
+
+/*************************************************************************
+ *  long int initdram
+ *
+ ************************************************************************/
+long int initdram(int board)
+{
+	sdram_init();
+	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_KBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long addr;
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB3 devices to 0.
+	  | Set PLB3 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp1, addr);
+	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb3_acr);
+	mtdcr(plb3_acr, addr | 0x80000000);
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB4 devices to 0.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp0, addr);
+	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(plb4_acr, addr);
+
+	/*-------------------------------------------------------------------------+
+	  | Set Nebula PLB4 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	/* Segment0 */
+	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+	mtdcr(plb0_acr, addr);
+
+	/* Segment1 */
+	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+	mtdcr(plb1_acr, addr);
+
+	return 1;
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	 * Set up Direct MMIO registers
+	 *--------------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440 EP PCI Master configuration.
+	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+
+	/*--------------------------------------------------------------------------+
+	 * Set up Configuration registers
+	 *--------------------------------------------------------------------------*/
+
+	/* Program the board's subsystem id/vendor id */
+	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+			      CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+	/* Configure command register as bus master */
+	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+	/* 240nS PCI clock */
+	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_write_config_word(0, PCI_ERREN, 0);
+
+	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	unsigned short temp_short;
+
+	/*--------------------------------------------------------------------------+
+	  | Write the PowerPC440 EP PCI Configuration regs.
+	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
+	  +--------------------------------------------------------------------------*/
+	pci_read_config_word(0, PCI_COMMAND, &temp_short);
+	pci_write_config_word(0, PCI_COMMAND,
+			      temp_short | PCI_COMMAND_MASTER |
+			      PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* Bamboo is always configured as host. */
+	return (1);
+}
+#endif				/* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ *  hw_watchdog_reset
+ *
+ *	This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif
diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile
new file mode 100755
index 0000000..47116d3
--- /dev/null
+++ b/board/amcc/yosemite/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amcc/yosemite/config.mk b/board/amcc/yosemite/config.mk
new file mode 100755
index 0000000..4ab0ea0
--- /dev/null
+++ b/board/amcc/yosemite/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S
new file mode 100755
index 0000000..425ad08
--- /dev/null
+++ b/board/amcc/yosemite/init.S
@@ -0,0 +1,112 @@
+/*
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_8M       0x00000060
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+
+    /*
+     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+     * speed up boot process. It is patched after relocation to enable SA_I
+     */
+    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+
+    /* PCI */
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+
+    /* USB 2.0 Device */
+    tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+
+    tlbtab_end
diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds
new file mode 100755
index 0000000..a9a7b0a
--- /dev/null
+++ b/board/amcc/yosemite/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/amcc/yosemite/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
new file mode 100755
index 0000000..509d8e4
--- /dev/null
+++ b/board/amcc/yosemite/yosemite.c
@@ -0,0 +1,549 @@
+/*
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+int board_early_init_f(void)
+{
+	register uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(ebccfga, xbcfg);
+	reg = mfdcr(ebccfgd);
+	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
+
+	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
+	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */
+
+	mtebc(pb1ap, 0x00000000);
+	mtebc(pb1cr, 0x00000000);
+
+	mtebc(pb2ap, 0x04814500);
+	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */
+
+	mtebc(pb3ap, 0x00000000);
+	mtebc(pb3cr, 0x00000000);
+
+	mtebc(pb4ap, 0x00000000);
+	mtebc(pb4cr, 0x00000000);
+
+	mtebc(pb5ap, 0x00000000);
+	mtebc(pb5cr, 0x00000000);
+
+	/*--------------------------------------------------------------------
+	 * Setup the GPIO pins
+	 *-------------------------------------------------------------------*/
+	/*CPLD cs */
+	/*setup Address lines for flash size 64Meg. */
+	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
+
+	/*setup emac */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+	/*UART1 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
+	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+
+	/* external interrupts IRQ0...3 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
+	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
+	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
+
+	/*setup USB 2.0 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
+	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	/*--------------------------------------------------------------------
+	 * Setup other serial configuration
+	 *-------------------------------------------------------------------*/
+	mfsdr(sdr_pci0, reg);
+	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
+	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
+	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */
+
+	/*clear tmrclk divisor */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+
+	/*enable ethernet */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+
+	/*enable usb 1.1 fs device and remove usb 2.0 reset */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+
+	/*get rid of flash write protect */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	uint pbcr;
+	int size_val = 0;
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(ebccfga, pb0cr);
+	mtdcr(ebccfgd, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+/*************************************************************************
+ *  sdram_init -- doesn't use serial presence detect.
+ *
+ *  Assumes:    256 MB, ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+#define NUM_TRIES 64
+#define NUM_READS 10
+
+void sdram_tr1_set(int ram_address, int* tr1_value)
+{
+	int i;
+	int j, k;
+	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
+	int first_good = -1, last_bad = 0x1ff;
+
+	unsigned long test[NUM_TRIES] = {
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
+		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
+
+	/* go through all possible SDRAM0_TR1[RDCT] values */
+	for (i=0; i<=0x1ff; i++) {
+		/* set the current value for TR1 */
+		mtsdram(mem_tr1, (0x80800800 | i));
+
+		/* write values */
+		for (j=0; j<NUM_TRIES; j++) {
+			ram_pointer[j] = test[j];
+
+			/* clear any cache at ram location */
+			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+		}
+
+		/* read values back */
+		for (j=0; j<NUM_TRIES; j++) {
+			for (k=0; k<NUM_READS; k++) {
+				/* clear any cache at ram location */
+				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
+
+				if (ram_pointer[j] != test[j])
+					break;
+			}
+
+			/* read error */
+			if (k != NUM_READS) {
+				break;
+			}
+		}
+
+		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
+		if (j == NUM_TRIES) {
+			if (first_good == -1)
+				first_good = i;		/* found beginning of window */
+		} else { /* bad read */
+			/* if we have not had a good read then don't care */
+			if(first_good != -1) {
+				/* first failure after a good read */
+				last_bad = i-1;
+				break;
+			}
+		}
+	}
+
+	/* return the current value for TR1 */
+	*tr1_value = (first_good + last_bad) / 2;
+}
+
+void sdram_init(void)
+{
+	register uint reg;
+	int tr1_bank1, tr1_bank2;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
+	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram(mem_clktr, 0x40000000);	/* ?? */
+	mtsdram(mem_wddctr, 0x40000000);	/* ?? */
+
+	/*clear this first, if the DDR is enabled by a debugger
+	  then you can not make changes. */
+	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */
+
+	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
+	mtsdram(mem_rtr, 0x04080000);	/* ?? */
+	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	mtsdram(mem_cfg0, 0x34000000);	/* Disable EEC */
+	udelay(400);		/* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram(mem_cfg0, 0x84000000);	/* Enable */
+
+	for (;;) {
+		mfsdram(mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	sdram_tr1_set(0x00000000, &tr1_bank1);
+	sdram_tr1_set(0x08000000, &tr1_bank2);
+	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
+}
+
+/*************************************************************************
+ *  long int initdram
+ *
+ ************************************************************************/
+long int initdram(int board)
+{
+	sdram_init();
+	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_KBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long addr;
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB3 devices to 0.
+	  | Set PLB3 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp1, addr);
+	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb3_acr);
+	mtdcr(plb3_acr, addr | 0x80000000);
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB4 devices to 0.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp0, addr);
+	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(plb4_acr, addr);
+
+	/*-------------------------------------------------------------------------+
+	  | Set Nebula PLB4 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	/* Segment0 */
+	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+	mtdcr(plb0_acr, addr);
+
+	/* Segment1 */
+	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+	mtdcr(plb1_acr, addr);
+
+	return 1;
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	 * Set up Direct MMIO registers
+	 *--------------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440 EP PCI Master configuration.
+	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+
+	/*--------------------------------------------------------------------------+
+	 * Set up Configuration registers
+	 *--------------------------------------------------------------------------*/
+
+	/* Program the board's subsystem id/vendor id */
+	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+			      CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+	/* Configure command register as bus master */
+	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+	/* 240nS PCI clock */
+	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_write_config_word(0, PCI_ERREN, 0);
+
+	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	unsigned short temp_short;
+
+	/*--------------------------------------------------------------------------+
+	  | Write the PowerPC440 EP PCI Configuration regs.
+	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
+	  +--------------------------------------------------------------------------*/
+	pci_read_config_word(0, PCI_COMMAND, &temp_short);
+	pci_write_config_word(0, PCI_COMMAND,
+			      temp_short | PCI_COMMAND_MASTER |
+			      PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* Bamboo is always configured as host. */
+	return (1);
+}
+#endif				/* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ *  hw_watchdog_reset
+ *
+ *	This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif
diff --git a/board/amirix/ap1000/Makefile b/board/amirix/ap1000/Makefile
new file mode 100755
index 0000000..4e1ef21
--- /dev/null
+++ b/board/amirix/ap1000/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o serial.o pci.o powerspan.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c
new file mode 100755
index 0000000..dd836ce
--- /dev/null
+++ b/board/amirix/ap1000/ap1000.c
@@ -0,0 +1,699 @@
+/*
+ * amirix.c: ppcboot platform support for AMIRIX board
+ *
+ * Copyright 2002 Mind NV
+ * Copyright 2003 AMIRIX Systems Inc.
+ *
+ * http://www.mind.be/
+ * http://www.amirix.com/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *          Frank Smith (smith@amirix.com)
+ *
+ * Derived from : Other platform support files in this tree, ml2
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#include "powerspan.h"
+#include "ap1000.h"
+
+int board_pre_init (void)
+{
+	return 0;
+}
+
+/** serial number and platform display at startup */
+int checkboard (void)
+{
+	unsigned char *s = getenv ("serial#");
+	unsigned char *e;
+
+	/* After a loadace command, the SystemAce control register is left in a wonky state. */
+	/* this code did not work in board_pre_init */
+	unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
+
+	p[SYSACE_CTRLREG0] = 0x0;
+
+	/* add platform and device to banner */
+	switch (get_device ()) {
+	case AP1xx_AP107_TARGET:
+		puts (AP1xx_AP107_TARGET_STR);
+		break;
+	case AP1xx_AP120_TARGET:
+		puts (AP1xx_AP120_TARGET_STR);
+		break;
+	case AP1xx_AP130_TARGET:
+		puts (AP1xx_AP130_TARGET_STR);
+		break;
+	case AP1xx_AP1070_TARGET:
+		puts (AP1xx_AP1070_TARGET_STR);
+		break;
+	case AP1xx_AP1100_TARGET:
+		puts (AP1xx_AP1100_TARGET_STR);
+		break;
+	default:
+		puts (AP1xx_UNKNOWN_STR);
+		break;
+	}
+	puts (AP1xx_TARGET_STR);
+	puts (" with ");
+
+	switch (get_platform ()) {
+	case AP100_BASELINE_PLATFORM:
+	case AP1000_BASELINE_PLATFORM:
+		puts (AP1xx_BASELINE_PLATFORM_STR);
+		break;
+	case AP1xx_QUADGE_PLATFORM:
+		puts (AP1xx_QUADGE_PLATFORM_STR);
+		break;
+	case AP1xx_MGT_REF_PLATFORM:
+		puts (AP1xx_MGT_REF_PLATFORM_STR);
+		break;
+	case AP1xx_STANDARD_PLATFORM:
+		puts (AP1xx_STANDARD_PLATFORM_STR);
+		break;
+	case AP1xx_DUAL_PLATFORM:
+		puts (AP1xx_DUAL_PLATFORM_STR);
+		break;
+	case AP1xx_BASE_SRAM_PLATFORM:
+		puts (AP1xx_BASE_SRAM_PLATFORM_STR);
+		break;
+	case AP1xx_PCI_PCB_TESTPLATFORM:
+	case AP1000_PCI_PCB_TESTPLATFORM:
+		puts (AP1xx_PCI_PCB_TESTPLATFORM_STR);
+		break;
+	case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM:
+		puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR);
+		break;
+	case AP1xx_SFP_MEZZ_TESTPLATFORM:
+		puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR);
+		break;
+	default:
+		puts (AP1xx_UNKNOWN_STR);
+		break;
+	}
+
+	if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) {
+		puts (AP1xx_TESTPLATFORM_STR);
+	} else {
+		puts (AP1xx_PLATFORM_STR);
+	}
+
+	putc ('\n');
+
+	puts ("Serial#: ");
+
+	if (!s) {
+		printf ("### No HW ID - assuming AMIRIX");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		for (; s < e; ++s) {
+			putc (*s);
+		}
+	}
+
+	putc ('\n');
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	unsigned char *s = getenv ("dramsize");
+
+	if (s != NULL) {
+		if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) {
+			s += 2;
+		}
+		return simple_strtoul (s, NULL, 16);
+	} else {
+		/* give all 64 MB */
+		return 64 * 1024 * 1024;
+	}
+}
+
+unsigned int get_platform (void)
+{
+	unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
+
+	return (*revision_reg_ptr & AP1xx_PLATFORM_MASK);
+}
+
+unsigned int get_device (void)
+{
+	unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
+
+	return (*revision_reg_ptr & AP1xx_TARGET_MASK);
+}
+
+#if 0				/* loadace is not working; it appears to be a hardware issue with the system ace. */
+/*
+   This function loads FPGA configurations from the SystemACE CompactFlash
+*/
+int do_loadace (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
+	int cfg;
+
+	if ((p[SYSACE_STATREG0] & 0x10) == 0) {
+		p[SYSACE_CTRLREG0] = 0x80;
+		printf ("\nNo CompactFlash Detected\n\n");
+		p[SYSACE_CTRLREG0] = 0x00;
+		return 1;
+	}
+
+	/* reset configuration controller: |  0x80 */
+	/* select cpflash                  & ~0x40 */
+	/* cfg start                       |  0x20 */
+	/* wait for cfgstart               & ~0x10 */
+	/* force cfgmode:                  |  0x08 */
+	/* do no force cfgaddr:            & ~0x04 */
+	/* clear mpulock:                  & ~0x02 */
+	/* do not force lock request       & ~0x01 */
+
+	p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08;
+	p[SYSACE_CTRLREG1] = 0x00;
+
+	/* force config address if arg2 exists */
+	if (argc == 2) {
+		cfg = simple_strtoul (argv[1], NULL, 10);
+
+		if (cfg > 7) {
+			printf ("\nInvalid Configuration\n\n");
+			p[SYSACE_CTRLREG0] = 0x00;
+			return 1;
+		}
+		/* Set config address */
+		p[SYSACE_CTRLREG1] = (cfg << 5);
+		/* force cfgaddr */
+		p[SYSACE_CTRLREG0] |= 0x04;
+
+	} else {
+		cfg = (p[SYSACE_STATREG1] & 0xE0) >> 5;
+	}
+
+	/* release configuration controller */
+	printf ("\nLoading V2PRO with config %d...\n", cfg);
+	p[SYSACE_CTRLREG0] &= ~0x80;
+
+
+	while ((p[SYSACE_STATREG1] & 0x01) == 0) {
+
+		if (p[SYSACE_ERRREG0] & 0x80) {
+			/* attempting to load an invalid configuration makes the cpflash */
+			/* appear to be removed. Reset here to avoid that problem */
+			p[SYSACE_CTRLREG0] = 0x80;
+			printf ("\nConfiguration %d Read Error\n\n", cfg);
+			p[SYSACE_CTRLREG0] = 0x00;
+			return 1;
+		}
+	}
+
+	p[SYSACE_CTRLREG0] |= 0x20;
+
+	return 0;
+}
+#endif
+
+/** Console command to display and set the software reconfigure byte
+  * <pre>
+  * swconfig        - display the current value of the software reconfigure byte
+  * swconfig [#]    - change the software reconfigure byte to #
+  * </pre>
+  * @param  *cmdtp  [IN] as passed by run_command (ignored)
+  * @param  flag    [IN] as passed by run_command (ignored)
+  * @param  argc    [IN] as passed by run_command if 1, display, if 2 change
+  * @param  *argv[] [IN] contains the parameters to use
+  * @return
+  * <pre>
+  *      0 if passed
+  *     -1 if failed
+  * </pre>
+  */
+int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned char *sector_buffer = NULL;
+	unsigned char input_char;
+	int write_result;
+	unsigned int input_uint;
+
+	/* display value if no argument */
+	if (argc < 2) {
+		printf ("Software configuration byte is currently: 0x%02x\n",
+			*((unsigned char *) (SW_BYTE_SECTOR_ADDR +
+					     SW_BYTE_SECTOR_OFFSET)));
+		return 0;
+	} else if (argc > 3) {
+		printf ("Too many arguments\n");
+		return -1;
+	}
+
+	/* if 3 arguments, 3rd argument is the address to use */
+	if (argc == 3) {
+		input_uint = simple_strtoul (argv[1], NULL, 16);
+		sector_buffer = (unsigned char *) input_uint;
+	} else {
+		sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR;
+	}
+
+	input_char = simple_strtoul (argv[1], NULL, 0);
+	if ((input_char & ~SW_BYTE_MASK) != 0) {
+		printf ("Input of 0x%02x will be masked to 0x%02x\n",
+			input_char, (input_char & SW_BYTE_MASK));
+		input_char = input_char & SW_BYTE_MASK;
+	}
+
+	memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR,
+		SW_BYTE_SECTOR_SIZE);
+	sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char;
+
+
+	printf ("Erasing Flash...");
+	if (flash_sect_erase
+	    (SW_BYTE_SECTOR_ADDR,
+	     (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) {
+		return -1;
+	}
+
+	printf ("Writing to Flash... ");
+	write_result =
+		flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR,
+			     SW_BYTE_SECTOR_SIZE);
+	if (write_result != 0) {
+		flash_perror (write_result);
+		return -1;
+	} else {
+		printf ("done\n");
+		printf ("Software configuration byte is now: 0x%02x\n",
+			*((unsigned char *) (SW_BYTE_SECTOR_ADDR +
+					     SW_BYTE_SECTOR_OFFSET)));
+	}
+
+	return 0;
+}
+
+#define ONE_SECOND 1000000
+
+int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int pause_time;
+	unsigned int delay_time;
+	int break_loop = 0;
+
+	/* display value if no argument */
+	if (argc < 2) {
+		pause_time = 1;
+	}
+
+	else if (argc > 2) {
+		printf ("Too many arguments\n");
+		return -1;
+	} else {
+		pause_time = simple_strtoul (argv[1], NULL, 0);
+	}
+
+	printf ("Pausing with a poll time of %d, press any key to reactivate\n", pause_time);
+	delay_time = pause_time * ONE_SECOND;
+	while (break_loop == 0) {
+		udelay (delay_time);
+		if (serial_tstc () != 0) {
+			break_loop = 1;
+			/* eat user key presses */
+			while (serial_tstc () != 0) {
+				serial_getc ();
+			}
+		}
+	}
+
+	return 0;
+}
+
+int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n",
+		*((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET)));
+	udelay (1000);
+	*((unsigned char *) AP1000_CPLD_BASE) = 1;
+
+	return 0;
+}
+
+#define GET_DECIMAL(low_byte) ((low_byte >> 5) * 125)
+#define TEMP_BUSY_BIT   0x80
+#define TEMP_LHIGH_BIT  0x40
+#define TEMP_LLOW_BIT   0x20
+#define TEMP_EHIGH_BIT  0x10
+#define TEMP_ELOW_BIT   0x08
+#define TEMP_OPEN_BIT   0x04
+#define TEMP_ETHERM_BIT 0x02
+#define TEMP_LTHERM_BIT 0x01
+
+int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	char cmd;
+	int ret_val = 0;
+	unsigned char temp_byte;
+	int temp;
+	int temp_low;
+	int low;
+	int low_low;
+	int high;
+	int high_low;
+	int therm;
+	unsigned char user_data[4] = { 0 };
+	int user_data_count = 0;
+	int ii;
+
+	if (argc > 1) {
+		cmd = argv[1][0];
+	} else {
+		cmd = 's';	/* default to status */
+	}
+
+	user_data_count = argc - 2;
+	for (ii = 0; ii < user_data_count; ii++) {
+		user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0);
+	}
+	switch (cmd) {
+	case 's':
+		if (I2CAccess
+		    (0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		printf ("Status    : 0x%02x  ", temp_byte);
+		if (temp_byte & TEMP_BUSY_BIT)
+			printf ("BUSY ");
+
+		if (temp_byte & TEMP_LHIGH_BIT)
+			printf ("LHIGH ");
+
+		if (temp_byte & TEMP_LLOW_BIT)
+			printf ("LLOW ");
+
+		if (temp_byte & TEMP_EHIGH_BIT)
+			printf ("EHIGH ");
+
+		if (temp_byte & TEMP_ELOW_BIT)
+			printf ("ELOW ");
+
+		if (temp_byte & TEMP_OPEN_BIT)
+			printf ("OPEN ");
+
+		if (temp_byte & TEMP_ETHERM_BIT)
+			printf ("ETHERM ");
+
+		if (temp_byte & TEMP_LTHERM_BIT)
+			printf ("LTHERM");
+
+		printf ("\n");
+
+		if (I2CAccess
+		    (0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		printf ("Config    : 0x%02x  ", temp_byte);
+
+		if (I2CAccess
+		    (0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			printf ("\n");
+			goto fail;
+		}
+		printf ("Conversion: 0x%02x\n", temp_byte);
+		if (I2CAccess
+		    (0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		printf ("Cons Alert: 0x%02x  ", temp_byte);
+
+		if (I2CAccess
+		    (0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			printf ("\n");
+			goto fail;
+		}
+		printf ("Therm Hyst: %d\n", temp_byte);
+
+		if (I2CAccess
+		    (0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		temp = temp_byte;
+		if (I2CAccess
+		    (0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		low = temp_byte;
+		if (I2CAccess
+		    (0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		high = temp_byte;
+		if (I2CAccess
+		    (0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		therm = temp_byte;
+		printf ("Local Temp: %2d     Low: %2d     High: %2d     THERM: %2d\n", temp, low, high, therm);
+
+		if (I2CAccess
+		    (0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		temp = temp_byte;
+		if (I2CAccess
+		    (0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		temp_low = temp_byte;
+		if (I2CAccess
+		    (0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		low = temp_byte;
+		if (I2CAccess
+		    (0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		low_low = temp_byte;
+		if (I2CAccess
+		    (0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		high = temp_byte;
+		if (I2CAccess
+		    (0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		high_low = temp_byte;
+		if (I2CAccess
+		    (0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		therm = temp_byte;
+		if (I2CAccess
+		    (0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &temp_byte, I2C_READ) != 0) {
+			goto fail;
+		}
+		printf ("Ext Temp  : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte);
+		break;
+	case 'l':		/* alter local limits : low, high, therm */
+		if (argc < 3) {
+			goto usage;
+		}
+
+		/* low */
+		if (I2CAccess
+		    (0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &user_data[0], I2C_WRITE) != 0) {
+			goto fail;
+		}
+
+		if (user_data_count > 1) {
+			/* high */
+			if (I2CAccess
+			    (0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+			     &user_data[1], I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 2) {
+			/* therm */
+			if (I2CAccess
+			    (0x20, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[2],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+		break;
+	case 'e':		/* alter external limits: low, high, therm, offset */
+		if (argc < 3) {
+			goto usage;
+		}
+
+		/* low */
+		if (I2CAccess
+		    (0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &user_data[0], I2C_WRITE) != 0) {
+			goto fail;
+		}
+
+		if (user_data_count > 1) {
+			/* high */
+			if (I2CAccess
+			    (0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+			     &user_data[1], I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 2) {
+			/* therm */
+			if (I2CAccess
+			    (0x19, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[2],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 3) {
+			/* offset */
+			if (I2CAccess
+			    (0x11, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[3],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+		break;
+	case 'c':		/* alter config settings: config, conv, cons alert, therm hyst */
+		if (argc < 3) {
+			goto usage;
+		}
+
+		/* config */
+		if (I2CAccess
+		    (0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+		     &user_data[0], I2C_WRITE) != 0) {
+			goto fail;
+		}
+
+		if (user_data_count > 1) {
+			/* conversion */
+			if (I2CAccess
+			    (0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
+			     &user_data[1], I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 2) {
+			/* cons alert */
+			if (I2CAccess
+			    (0x22, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[2],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+
+		if (user_data_count > 3) {
+			/* therm hyst */
+			if (I2CAccess
+			    (0x21, I2C_SENSOR_DEV,
+			     I2C_SENSOR_CHIP_SEL, &user_data[3],
+			     I2C_WRITE) != 0) {
+				goto fail;
+			}
+		}
+		break;
+	default:
+		goto usage;
+	}
+
+	goto done;
+fail:
+	printf ("Access to sensor failed\n");
+	ret_val = -1;
+	goto done;
+usage:
+	printf ("Usage:\n%s\n", cmdtp->help);
+
+done:
+	return ret_val;
+}
+
+U_BOOT_CMD (temp, 6, 0, do_temp_sensor,
+	    "temp    - interact with the temperature sensor\n",
+	    "temp [s]\n"
+	    "        - Show status.\n"
+	    "temp l LOW [HIGH] [THERM]\n"
+	    "        - Set local limits.\n"
+	    "temp e LOW [HIGH] [THERM] [OFFSET]\n"
+	    "        - Set external limits.\n"
+	    "temp c CONFIG [CONVERSION] [CONS. ALERT] [THERM HYST]\n"
+	    "        - Set config options.\n"
+	    "\n"
+	    "All values can be decimal or hex (hex preceded with 0x).\n"
+	    "Only whole numbers are supported for external limits.\n");
+
+#if 0
+U_BOOT_CMD (loadace, 2, 0, do_loadace,
+	    "loadace - load fpga configuration from System ACE compact flash\n",
+	    "N\n"
+	    "    - Load configuration N (0-7) from System ACE compact flash\n"
+	    "loadace\n" "    - loads default configuration\n");
+#endif
+
+U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte,
+	    "swconfig- display or modify the software configuration byte\n",
+	    "N [ADDRESS]\n"
+	    "    - set software configuration byte to N, optionally use ADDRESS as\n"
+	    "      location of buffer for flash copy\n"
+	    "swconfig\n" "    - display software configuration byte\n");
+
+U_BOOT_CMD (pause, 2, 0, do_pause,
+	    "pause   - sleep processor until any key is pressed with poll time of N seconds\n",
+	    "N\n"
+	    "    - sleep processor until any key is pressed with poll time of N seconds\n"
+	    "pause\n"
+	    "    - sleep processor until any key is pressed with poll time of 1 second\n");
+
+U_BOOT_CMD (swrecon, 1, 0, do_swreconfig,
+	    "swrecon - trigger a board reconfigure to the software selected configuration\n",
+	    "\n"
+	    "    - trigger a board reconfigure to the software selected configuration\n");
diff --git a/board/amirix/ap1000/ap1000.h b/board/amirix/ap1000/ap1000.h
new file mode 100755
index 0000000..118c4d1
--- /dev/null
+++ b/board/amirix/ap1000/ap1000.h
@@ -0,0 +1,173 @@
+/*
+ * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally
+ *
+ * Author : James MacAulay
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#ifndef __AP1000_H
+#define __AP1000_H
+
+/*
+ *  Revision Register stuff
+ */
+#define AP1xx_FPGA_REV_ADDR 0x29000000
+
+#define AP1xx_PLATFORM_MASK	 0xFF000000
+#define AP100_BASELINE_PLATFORM	 0x01000000
+#define AP1xx_QUADGE_PLATFORM	 0x02000000
+#define AP1xx_MGT_REF_PLATFORM	 0x03000000
+#define AP1xx_STANDARD_PLATFORM	 0x04000000
+#define AP1xx_DUAL_PLATFORM	 0x05000000
+#define AP1xx_BASE_SRAM_PLATFORM 0x06000000
+
+#define AP1000_BASELINE_PLATFORM 0x21000000
+
+#define AP1xx_TESTPLATFORM_MASK		0xC0000000
+#define AP1xx_PCI_PCB_TESTPLATFORM	0xC0000000
+#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000
+#define AP1xx_SFP_MEZZ_TESTPLATFORM	0xC2000000
+
+#define AP1000_PCI_PCB_TESTPLATFORM	 0xC3000000
+
+#define AP1xx_TARGET_MASK  0x00FF0000
+#define AP1xx_AP107_TARGET 0x00010000
+#define AP1xx_AP120_TARGET 0x00020000
+#define AP1xx_AP130_TARGET 0x00030000
+#define AP1xx_AP1070_TARGET 0x00040000
+#define AP1xx_AP1100_TARGET 0x00050000
+
+#define AP1xx_UNKNOWN_STR "Unknown"
+
+#define AP1xx_PLATFORM_STR	     " Platform"
+#define AP1xx_BASELINE_PLATFORM_STR  "Baseline"
+#define AP1xx_QUADGE_PLATFORM_STR    "Quad GE"
+#define AP1xx_MGT_REF_PLATFORM_STR   "MGT Reference"
+#define AP1xx_STANDARD_PLATFORM_STR  "Standard"
+#define AP1xx_DUAL_PLATFORM_STR	     "Dual"
+#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM"
+
+#define AP1xx_TESTPLATFORM_STR		    " Test Platform"
+#define AP1xx_PCI_PCB_TESTPLATFORM_STR	    "Base"
+#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine"
+#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR	    "SFP Mezzanine"
+
+#define AP1xx_TARGET_STR       " Board"
+#define AP1xx_AP107_TARGET_STR "AP107"
+#define AP1xx_AP120_TARGET_STR "AP120"
+#define AP1xx_AP130_TARGET_STR "AP130"
+
+#define AP1xx_AP1070_TARGET_STR "AP1070"
+#define AP1xx_AP1100_TARGET_STR "AP1100"
+
+/*
+ *  Flash Stuff
+ */
+#define AP1xx_PROGRAM_FLASH_INDEX   0
+#define AP1xx_CONFIG_FLASH_INDEX    1
+
+/*
+ *  System Ace Stuff
+ */
+#define AP1000_SYSACE_REGBASE  0x28000000
+
+#define SYSACE_STATREG0 0x04 /* 7:0 */
+#define SYSACE_STATREG1 0x05 /* 15:8 */
+#define SYSACE_STATREG2 0x06 /* 23:16 */
+#define SYSACE_STATREG3 0x07 /* 31:24 */
+
+#define SYSACE_ERRREG0 0x08 /* 7:0 */
+#define SYSACE_ERRREG1 0x09 /* 15:8 */
+#define SYSACE_ERRREG2 0x0a /* 23:16 */
+#define SYSACE_ERRREG3 0x0b /* 31:24 */
+
+#define SYSACE_CTRLREG0 0x18 /* 7:0 */
+#define SYSACE_CTRLREG1 0x19 /* 15:8 */
+#define SYSACE_CTRLREG2 0x1A /* 23:16 */
+#define SYSACE_CTRLREG3 0x1B /* 31:24 */
+
+/*
+ *  Software reconfig thing
+ */
+#define SW_BYTE_SECTOR_ADDR	0x24FE0000
+#define SW_BYTE_SECTOR_OFFSET	0x0001FFFF
+#define SW_BYTE_SECTOR_SIZE	0x00020000
+#define SW_BYTE_MASK		0x00000003
+
+#define DEFAULT_TEMP_ADDR	0x00100000
+
+#define AP1000_CPLD_BASE	0x26000000
+
+/* PowerSpan II Stuff */
+#define PSII_SYNC() asm("eieio")
+#define PSPAN_BASEADDR 0x30000000
+#define EEPROM_DEFAULT { 0x01,	     /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */  \
+			0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
+			0x0,	     /* Byte 4 - Powerspan reserved  - start of short load */ \
+			0x0F,	     /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
+			0x0E,	     /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
+			0x00, 0x00,  /* Byte 7,8 - PCI-1 Subsystem ID - */ \
+			0x00, 0x00,  /* Byte 9,10 - PCI-1 Subsystem Vendor Id -	 */ \
+			0x00,	     /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
+			0x1F,	     /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
+			0xBA,	     /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
+			0xA0,	     /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
+			0x00,	     /* Byte 15 - Vital Product Data Disabled. */ \
+			0x88,	     /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1	*/ \
+			0x40,	     /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
+			0x00,	     /* Byte 18 - I2O disabled */ \
+			0x00,	     /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
+			0x00,0x00,   /* Bytes 20,21 - PCI 2 Subsystem Id */ \
+			0x00,0x00,   /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
+			0x0C,	     /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
+			0xBB,	     /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1  - 128 Meg (program/config flash) */ \
+			0x00,	     /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
+			0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
+			/* Long Load Information */ \
+			0x82,0x60,   /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
+			0x10,0xE3,   /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
+			0x06,	     /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
+			0x80,	     /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
+			0x00,	     /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
+			0x01,	     /* Byte 39 - Power span revision 1. */ \
+			0x6E,	     /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
+			0x40,	     /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
+			0x22,	     /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
+			0x00,0x00,   /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
+			0x0E,	     /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
+			0x2c,00,00,  /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
+			0x30,00,00,  /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
+			0x82,0x60,   /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
+			0x10,0xE3,   /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
+			0x06,	     /* Byte 56 - PCI-2 Class Base - Bridge device */ \
+			0x80,	     /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
+			0x00,	     /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
+			0x01,	     /* Byte 59 - PCI-2 class revision	1 */ \
+			0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
+
+
+#define EEPROM_LENGTH	64  /* Long Load */
+
+#define I2C_SENSOR_DEV	    0x9
+#define I2C_SENSOR_CHIP_SEL 0x4
+
+/*
+ *  Board Functions
+ */
+void set_eat_machine_checks(int a_flag);
+int get_eat_machine_checks(void);
+unsigned int get_platform(void);
+unsigned int get_device(void);
+void* memcpyb(void * dest,const void *src,size_t count);
+int process_bootflag(ulong bootflag);
+void user_led_on(void);
+void user_led_off(void);
+
+#endif	/* __COMMON_H_ */
diff --git a/board/amirix/ap1000/config.mk b/board/amirix/ap1000/config.mk
new file mode 100755
index 0000000..c09783a
--- /dev/null
+++ b/board/amirix/ap1000/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Start at bottom of RAM, but at an aliased address so that it looks
+# like it's not in RAM.  This is a bit of voodoo to allow it to be
+# run from RAM instead of Flash.
+TEXT_BASE = 0x08000000
diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c
new file mode 100755
index 0000000..1a3b252
--- /dev/null
+++ b/board/amirix/ap1000/flash.c
@@ -0,0 +1,903 @@
+/**
+ * @file flash.c
+ */
+
+/*
+ * (C) Copyright 2003
+ * AMIRIX Systems Inc.
+ *
+ * Originated from ppcboot-2.0.0/board/esd/cpci440/strataflash.c
+ *
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI           0x98
+#define FLASH_CMD_READ_ID       0x90
+#define FLASH_CMD_RESET         0xff
+#define FLASH_CMD_BLOCK_ERASE       0x20
+#define FLASH_CMD_ERASE_CONFIRM     0xD0
+#define FLASH_CMD_WRITE         0x40
+#define FLASH_CMD_PROTECT       0x60
+#define FLASH_CMD_PROTECT_SET       0x01
+#define FLASH_CMD_PROTECT_CLEAR     0xD0
+#define FLASH_CMD_CLEAR_STATUS      0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE       0x80
+#define FLASH_STATUS_ESS        0x40
+#define FLASH_STATUS_ECLBS      0x20
+#define FLASH_STATUS_PSLBS      0x10
+#define FLASH_STATUS_VPENS      0x08
+#define FLASH_STATUS_PSS        0x04
+#define FLASH_STATUS_DPS        0x02
+#define FLASH_STATUS_R          0x01
+#define FLASH_STATUS_PROTECT        0x01
+
+#define FLASH_OFFSET_CFI        0x55
+#define FLASH_OFFSET_CFI_RESP       0x10
+#define FLASH_OFFSET_WTOUT      0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT      0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT      0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT      0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE       0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS  0x2C
+#define FLASH_OFFSET_ERASE_REGIONS  0x2D
+#define FLASH_OFFSET_PROTECT        0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI           0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char *cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
+			     uchar cmd);
+static int flash_isequal (flash_info_t * info, int sect, uchar offset,
+			  uchar cmd);
+static int flash_isset (flash_info_t * info, int sect, uchar offset,
+			uchar cmd);
+static int flash_detect_cfi (flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t * info, ulong dest,
+				cfiword_t cword);
+static int flash_full_status_check (flash_info_t * info, ulong sector,
+				    ulong tout, char *prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
+				  int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+uchar *flash_make_addr (flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *) (info->start[sect] + (offset * info->chipwidth)));
+}
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+uchar flash_read_uchar (flash_info_t * info, uchar offset)
+{
+	if (info->portwidth == FLASH_CFI_8BIT) {
+		volatile uchar *cp;
+		uchar c;
+
+		cp = flash_make_addr (info, 0, offset);
+		c = *cp;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_uchar offset=%04x ptr=%08x c=%02x\n",
+			offset, (unsigned int) cp, c);
+#endif
+		return (c);
+
+	} else if (info->portwidth == FLASH_CFI_16BIT) {
+		volatile ushort *sp;
+		ushort s;
+		uchar c;
+
+		sp = (ushort *) flash_make_addr (info, 0, offset);
+		s = *sp;
+		c = (uchar) s;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c);
+#endif
+		return (c);
+
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort (flash_info_t * info, int sect, uchar offset)
+{
+	if (info->portwidth == FLASH_CFI_8BIT) {
+		volatile uchar *cp;
+		uchar c0, c1;
+		ushort s;
+
+		cp = flash_make_addr (info, 0, offset);
+		c1 = cp[2];
+		c0 = cp[0];
+		s = c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s);
+#endif
+		return (s);
+
+	} else if (info->portwidth == FLASH_CFI_16BIT) {
+		volatile ushort *sp;
+		ushort s;
+		uchar c0, c1;
+
+		sp = (ushort *) flash_make_addr (info, 0, offset);
+		s = *sp;
+		c1 = (uchar) sp[1];
+		c0 = (uchar) sp[0];
+		s = c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s);
+#endif
+		return (s);
+
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long (flash_info_t * info, int sect, uchar offset)
+{
+	if (info->portwidth == FLASH_CFI_8BIT) {
+		volatile uchar *cp;
+		uchar c0, c1, c2, c3;
+		ulong l;
+
+		cp = flash_make_addr (info, 0, offset);
+		c3 = cp[6];
+		c2 = cp[4];
+		c1 = cp[2];
+		c0 = cp[0];
+		l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l);
+#endif
+		return (l);
+
+	} else if (info->portwidth == FLASH_CFI_16BIT) {
+		volatile ushort *sp;
+		uchar c0, c1, c2, c3;
+		ulong l;
+
+		sp = (ushort *) flash_make_addr (info, 0, offset);
+		c3 = (uchar) sp[3];
+		c2 = (uchar) sp[2];
+		c1 = (uchar) sp[1];
+		c0 = (uchar) sp[0];
+		l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
+#ifdef DEBUG_FLASH
+		printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l);
+#endif
+		return (l);
+
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+
+	size = 0;
+
+	flash_info[0].flash_id = FLASH_UNKNOWN;
+	flash_info[0].portwidth = FLASH_CFI_16BIT;
+	flash_info[0].chipwidth = FLASH_CFI_16BIT;
+	size += flash_info[0].size = flash_get_size (CFG_PROGFLASH_BASE, 0);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20);
+	};
+
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].portwidth = FLASH_CFI_8BIT;
+	flash_info[1].chipwidth = FLASH_CFI_16BIT;
+	size += flash_info[1].size = flash_get_size (CFG_CONFFLASH_BASE, 1);
+	if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20);
+	};
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			flash_write_cmd (info, sect, 0,
+					 FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd (info, sect, 0,
+					 FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd (info, sect, 0,
+					 FLASH_CMD_ERASE_CONFIRM);
+
+			if (flash_full_status_check
+			    (info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf (".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf ("CFI conformant FLASH (x%d device in x%d mode)",
+		(info->chipwidth << 3), (info->portwidth << 3));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n");
+		printf (" %08lX%5s",
+			info->start[i], info->protect[i] ? " (RO)" : " ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if ((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for (i = 0; i < aln; ++i, ++cp)
+			flash_add_byte (info, &cword, (*(uchar *) cp));
+
+		for (; (i < info->portwidth) && (cnt > 0); i++) {
+			flash_add_byte (info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte (info, &cword, (*(uchar *) cp));
+		if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while (cnt >= info->portwidth) {
+		i = info->buffer_size > cnt ? cnt : info->buffer_size;
+		if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -= i;
+	}
+#else
+	/* handle the aligned part */
+	while (cnt >= info->portwidth) {
+		cword.l = 0;
+		for (i = 0; i < info->portwidth; i++) {
+			flash_add_byte (info, &cword, *src++);
+		}
+		if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+		flash_add_byte (info, &cword, *src++);
+		--cnt;
+	}
+	for (; i < info->portwidth; ++i, ++cp) {
+		flash_add_byte (info, &cword, (*(uchar *) cp));
+	}
+
+	return flash_write_cfiword (info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
+	if (prot)
+		flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if ((retcode =
+	     flash_full_status_check (info, sector, info->erase_blk_tout,
+				      prot ? "protect" : "unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if (prot == 0) {
+			int i;
+
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i])
+					flash_real_protect (info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check (flash_info_t * info, ulong sector, ulong tout,
+			       char *prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer (start) > info->erase_blk_tout) {
+			printf ("Flash %s timeout at address %lx\n", prompt,
+				info->start[sector]);
+			flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check (flash_info_t * info, ulong sector,
+				    ulong tout, char *prompt)
+{
+	int retcode;
+
+	retcode = flash_status_check (info, sector, tout, prompt);
+	if ((retcode == ERR_OK)
+	    && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf ("Flash %s error at address %lx\n", prompt,
+			info->start[sector]);
+		if (flash_isset
+		    (info, sector, 0,
+		     FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+			printf ("Command Sequence Error.\n");
+		} else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
+			printf ("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf ("Locking Error\n");
+		}
+		if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
+			printf ("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
+			printf ("Vpp Low Error.\n");
+	}
+	flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
+{
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
+{
+	/*int i; */
+	uchar *cp = (uchar *) cmdbuf;
+
+	/* for(i=0; i< info->portwidth; i++) */
+	/*  *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */
+	if (info->portwidth == FLASH_CFI_8BIT
+	    && info->chipwidth == FLASH_CFI_16BIT) {
+		cp[0] = cmd;
+	} else if (info->portwidth == FLASH_CFI_16BIT
+		   && info->chipwidth == FLASH_CFI_16BIT) {
+		cp[0] = '\0';
+		cp[1] = cmd;
+	};
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
+			     uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+
+	addr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal (flash_info_t * info, int sect, uchar offset,
+			  uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+
+	cptr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset (flash_info_t * info, int sect, uchar offset,
+			uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+
+	cptr.cp = flash_make_addr (info, sect, offset);
+	flash_make_cmd (info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi (flash_info_t * info)
+{
+
+#if 0
+	for (info->portwidth = FLASH_CFI_8BIT;
+	     info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
+		for (info->chipwidth = FLASH_CFI_BY8;
+		     info->chipwidth <= info->portwidth;
+		     info->chipwidth <<= 1) {
+			flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd (info, 0, FLASH_OFFSET_CFI,
+					 FLASH_CMD_CFI);
+			if (flash_isequal
+			    (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+			    && flash_isequal (info, 0,
+					      FLASH_OFFSET_CFI_RESP + 1, 'R')
+			    && flash_isequal (info, 0,
+					      FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+#endif
+	flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+	flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+	if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') &&
+	    flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+	    flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
+		return 1;
+	} else {
+		return 0;
+	};
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int erase_region_size;
+	int erase_region_count;
+
+	info->start[0] = base;
+
+	if (flash_detect_cfi (info)) {
+#ifdef DEBUG_FLASH
+		printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth);	/* test-only */
+#endif
+		size_ratio = 1;	/* info->portwidth / info->chipwidth; */
+		num_erase_regions =
+			flash_read_uchar (info,
+					  FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf ("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for (i = 0; i < num_erase_regions; i++) {
+			if (i > NUM_ERASE_REGIONS) {
+				printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long (info, 0,
+					       FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_count = (tmp & 0xffff) + 1;
+			tmp >>= 16;
+			erase_region_size =
+				(tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
+			for (j = 0; j < erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] =
+					flash_isset (info, sect_cnt,
+						     FLASH_OFFSET_PROTECT,
+						     FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size =
+			(1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) *
+			size_ratio;
+		info->buffer_size =
+			(1 <<
+			 flash_read_ushort (info, 0,
+					    FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout =
+			(tmp *
+			 (1 <<
+			  flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout =
+			(tmp *
+			 (1 <<
+			  flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
+		info->write_tout =
+			(tmp *
+			 (1 <<
+			  flash_read_uchar (info,
+					    FLASH_OFFSET_WMAX_TOUT))) / 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t * info, ulong dest,
+				cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr (info, 0, 0);
+	cptr.cp = (uchar *) dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if (!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	return flash_full_status_check (info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector (flash_info_t * info, ulong addr)
+{
+	int sector;
+
+	for (sector = info->sector_count - 1; sector >= 0; sector--) {
+		if (addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
+				  int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *) dest;
+	sector = find_sector (info, dest);
+	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if ((retcode =
+	     flash_status_check (info, sector, info->buffer_write_tout,
+				 "write to buffer")) == ERR_OK) {
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
+		while (cnt-- > 0) {
+			switch (info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd (info, sector, 0,
+				 FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode =
+			flash_full_status_check (info, sector,
+						 info->buffer_write_tout,
+						 "buffer write");
+	}
+	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S
new file mode 100755
index 0000000..3aaa5c2
--- /dev/null
+++ b/board/amirix/ap1000/init.S
@@ -0,0 +1,34 @@
+/*
+ * init.S: Stubs for ppcboot initialization
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	blr
+
+	.globl	sdram_init
+sdram_init:
+	blr
diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c
new file mode 100755
index 0000000..a6436ac
--- /dev/null
+++ b/board/amirix/ap1000/pci.c
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2003
+ * AMIRIX Systems Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+#define PCI_MEM_82559ER_CSR_BASE    0x30200000
+#define PCI_IO_82559ER_CSR_BASE     0x40000200
+
+/** AP1100 specific values */
+#define PSII_BASE                   0x30000000	  /**< PowerSpan II dual bridge local bus register address */
+#define PSII_CONFIG_ADDR            0x30000290	  /**< PowerSpan II Configuration Cycle Address configuration register */
+#define PSII_CONFIG_DATA            0x30000294	  /**< PowerSpan II Configuration Cycle Data register. */
+#define PSII_CONFIG_DEST_PCI2       0x01000000	  /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
+#define PSII_PCI_MEM_BASE           0x30200000	  /**< Local Bus address for start of PCI memory space on PCI2 bus. */
+#define PSII_PCI_MEM_SIZE           0x1BE00000	  /**< PCI Memory space about 510 Meg. */
+#define AP1000_SYS_MEM_START        0x00000000	  /**< System memory starts at 0. */
+#define AP1000_SYS_MEM_SIZE         0x08000000	  /**< System memory is 128 Meg. */
+
+/* static int G_verbosity_level = 1; */
+#define G_verbosity_level 1
+
+void write1 (unsigned long addr, unsigned char val)
+{
+	volatile unsigned char *p = (volatile unsigned char *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr,
+			val);
+	*p = val;
+	asm ("eieio");
+}
+
+unsigned char read1 (unsigned long addr)
+{
+	unsigned char val;
+	volatile unsigned char *p = (volatile unsigned char *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("read1: addr=%08x ", (unsigned int) addr);
+	val = *p;
+	asm ("eieio");
+	if (G_verbosity_level > 1)
+		printf ("val=%08x\n", val);
+	return val;
+}
+
+void write2 (unsigned long addr, unsigned short val)
+{
+	volatile unsigned short *p = (volatile unsigned short *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("write2: addr=%08x val=%04x -> *p=%04x\n",
+			(unsigned int) addr, val,
+			((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
+
+	*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+	asm ("eieio");
+}
+
+unsigned short read2 (unsigned long addr)
+{
+	unsigned short val;
+	volatile unsigned short *p = (volatile unsigned short *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("read2: addr=%08x ", (unsigned int) addr);
+	val = *p;
+	val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+	asm ("eieio");
+	if (G_verbosity_level > 1)
+		printf ("*p=%04x -> val=%04x\n",
+			((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
+	return val;
+}
+
+void write4 (unsigned long addr, unsigned long val)
+{
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("write4: addr=%08x val=%08x -> *p=%08x\n",
+			(unsigned int) addr, (unsigned int) val,
+			(unsigned int) (((val & 0xFF000000) >> 24) |
+					((val & 0x000000FF) << 24) |
+					((val & 0x00FF0000) >> 8) |
+					((val & 0x0000FF00) << 8)));
+
+	*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+		((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+	asm ("eieio");
+}
+
+unsigned long read4 (unsigned long addr)
+{
+	unsigned long val;
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("read4: addr=%08x", (unsigned int) addr);
+
+	val = *p;
+	val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+		((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+	asm ("eieio");
+
+	if (G_verbosity_level > 1)
+		printf ("*p=%04x -> val=%04x\n",
+			(unsigned int) (((val & 0xFF000000) >> 24) |
+					((val & 0x000000FF) << 24) |
+					((val & 0x00FF0000) >> 8) |
+					((val & 0x0000FF00) << 8)),
+			(unsigned int) val);
+	return val;
+}
+
+void write4be (unsigned long addr, unsigned long val)
+{
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+	if (G_verbosity_level > 1)
+		printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr,
+			(unsigned int) val);
+	*p = val;
+	asm ("eieio");
+}
+
+/** One byte configuration write on PSII.
+ *  Currently fixes destination PCI bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Address of location for received byte.
+ *  @return Always Zero.
+ */
+static int psII_read_config_byte (struct pci_controller *hose,
+				  pci_dev_t dev, int reg, u8 * val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	*val = read1 (PSII_CONFIG_DATA + (reg & 0x03));
+	return (0);
+}
+
+/** One byte configuration write on PSII.
+ *  Currently fixes destination bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Output byte.
+ *  @return Always Zero.
+ */
+static int psII_write_config_byte (struct pci_controller *hose,
+				   pci_dev_t dev, int reg, u8 val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val);
+
+	return (0);
+}
+
+/** One word (16 bit) configuration read on PSII.
+ *  Currently fixes destination PCI bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Address of location for received word.
+ *  @return Always Zero.
+ */
+static int psII_read_config_word (struct pci_controller *hose,
+				  pci_dev_t dev, int reg, u16 * val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	*val = read2 (PSII_CONFIG_DATA + (reg & 0x03));
+	return (0);
+}
+
+/** One word (16 bit) configuration write on PSII.
+ *  Currently fixes destination bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Output word.
+ *  @return Always Zero.
+ */
+static int psII_write_config_word (struct pci_controller *hose,
+				   pci_dev_t dev, int reg, u16 val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val);
+
+	return (0);
+}
+
+/** One DWord (32 bit) configuration read on PSII.
+ *  Currently fixes destination PCI bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Address of location for received byte.
+ *  @return Always Zero.
+ */
+static int psII_read_config_dword (struct pci_controller *hose,
+				   pci_dev_t dev, int reg, u32 * val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	*val = read4 (PSII_CONFIG_DATA);
+	return (0);
+}
+
+/** One DWord (32 bit) configuration write on PSII.
+ *  Currently fixes destination bus to PCI2, onboard
+ *  pci.
+ *  @param    hose    PCI Host controller information. Ignored.
+ *  @param    dev        Encoded PCI device/Bus and Function value.
+ *  @param    reg        PCI Configuration register number.
+ *  @param    val        Output Dword.
+ *  @return Always Zero.
+ */
+static int psII_write_config_dword (struct pci_controller *hose,
+				    pci_dev_t dev, int reg, u32 val)
+{
+	write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 |	/* Operate on PCI2 bus interface . */
+		  (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3));	/* Configuation cycle type 0 */
+
+	write4 (PSII_CONFIG_DATA, (unsigned long) val);
+
+	return (0);
+}
+
+static struct pci_config_table ap1000_config_table[] = {
+#ifdef CONFIG_AP1000
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN),
+	 PCI_FUNC (CFG_ETH_DEV_FN),
+	 pci_cfgfunc_config_device,
+	 {CFG_ETH_IOBASE, CFG_ETH_MEMBASE,
+	  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
+#endif
+	{}
+};
+
+static struct pci_controller psII_hose = {
+      config_table:ap1000_config_table,
+};
+
+void pci_init_board (void)
+{
+	struct pci_controller *hose = &psII_hose;
+
+	/*
+	 * Register the hose
+	 */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* System memory space */
+	pci_set_region (hose->regions + 0,
+			AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
+			AP1000_SYS_MEM_SIZE,
+			PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	/* PCI Memory space */
+	pci_set_region (hose->regions + 1,
+			PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE,
+			PSII_PCI_MEM_SIZE, PCI_REGION_MEM);
+
+	/* No IO Memory space  - for now */
+
+	pci_set_ops (hose,
+		     psII_read_config_byte,
+		     psII_read_config_word,
+		     psII_read_config_dword,
+		     psII_write_config_byte,
+		     psII_write_config_word, psII_write_config_dword);
+
+	hose->region_count = 2;
+
+	pci_register_hose (hose);
+
+	hose->last_busno = pci_hose_scan (hose);
+}
diff --git a/board/amirix/ap1000/powerspan.c b/board/amirix/ap1000/powerspan.c
new file mode 100755
index 0000000..f048155
--- /dev/null
+++ b/board/amirix/ap1000/powerspan.c
@@ -0,0 +1,750 @@
+/**
+ * @file powerspan.c Source file for PowerSpan II code.
+ */
+
+/*
+ * (C) Copyright 2005
+ * AMIRIX Systems Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include "powerspan.h"
+#define tolower(x) x
+#include "ap1000.h"
+
+#ifdef INCLUDE_PCI
+
+/** Write one byte with byte swapping.
+  * @param  addr [IN] the address to write to
+  * @param  val  [IN] the value to write
+  */
+void write1 (unsigned long addr, unsigned char val)
+{
+	volatile unsigned char *p = (volatile unsigned char *) addr;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("write1: addr=%08x val=%02x\n", addr, val);
+	}
+#endif
+	*p = val;
+	PSII_SYNC ();
+}
+
+/** Read one byte with byte swapping.
+  * @param  addr  [IN] the address to read from
+  * @return the value at addr
+  */
+unsigned char read1 (unsigned long addr)
+{
+	unsigned char val;
+	volatile unsigned char *p = (volatile unsigned char *) addr;
+
+	val = *p;
+	PSII_SYNC ();
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("read1: addr=%08x val=%02x\n", addr, val);
+	}
+#endif
+	return val;
+}
+
+/** Write one 2-byte word with byte swapping.
+  * @param  addr  [IN] the address to write to
+  * @param  val   [IN] the value to write
+  */
+void write2 (unsigned long addr, unsigned short val)
+{
+	volatile unsigned short *p = (volatile unsigned short *) addr;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val,
+			((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
+	}
+#endif
+	*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+	PSII_SYNC ();
+}
+
+/** Read one 2-byte word with byte swapping.
+  * @param  addr  [IN] the address to read from
+  * @return the value at addr
+  */
+unsigned short read2 (unsigned long addr)
+{
+	unsigned short val;
+	volatile unsigned short *p = (volatile unsigned short *) addr;
+
+	val = *p;
+	val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
+	PSII_SYNC ();
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p,
+			val);
+	}
+#endif
+	return val;
+}
+
+/** Write one 4-byte word with byte swapping.
+  * @param  addr  [IN] the address to write to
+  * @param  val   [IN] the value to write
+  */
+void write4 (unsigned long addr, unsigned long val)
+{
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val,
+			((val & 0xFF000000) >> 24) |
+			((val & 0x000000FF) << 24) |
+			((val & 0x00FF0000) >>  8) |
+			((val & 0x0000FF00) <<  8));
+	}
+#endif
+	*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+		((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+	PSII_SYNC ();
+}
+
+/** Read one 4-byte word with byte swapping.
+  * @param  addr  [IN] the address to read from
+  * @return the value at addr
+  */
+unsigned long read4 (unsigned long addr)
+{
+	unsigned long val;
+	volatile unsigned long *p = (volatile unsigned long *) addr;
+
+	val = *p;
+	val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
+		((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
+	PSII_SYNC ();
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p,
+			val);
+	}
+#endif
+	return val;
+}
+
+int PCIReadConfig (int bus, int dev, int fn, int reg, int width,
+		   unsigned long *val)
+{
+	unsigned int conAdrVal;
+	unsigned int conDataReg = REG_CONFIG_DATA;
+	unsigned int status;
+	int ret_val = 0;
+
+
+	/* DEST bit hardcoded to 1: local pci is PCI-2 */
+	/* TYPE bit is hardcoded to 1: all config cycles are local */
+	conAdrVal = (1 << 24)
+		| ((bus & 0xFF) << 16)
+		| ((dev & 0xFF) << 11)
+		| ((fn & 0x07) << 8)
+		| (reg & 0xFC);
+
+	/* clear any pending master aborts */
+	write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+
+	/* Load the conAdrVal value first, then read from pb_conf_data */
+	write4 (REG_CONFIG_ADDRESS, conAdrVal);
+	PSII_SYNC ();
+
+
+	/* Note: documentation does not match the pspan library code */
+	/* Note: *pData comes back as -1 if device is not present */
+	switch (width) {
+	case 4:
+		*(unsigned int *) val = read4 (conDataReg);
+		break;
+	case 2:
+		*(unsigned short *) val = read2 (conDataReg);
+		break;
+	case 1:
+		*(unsigned char *) val = read1 (conDataReg);
+		break;
+	default:
+		ret_val = ILLEGAL_REG_OFFSET;
+		break;
+	}
+	PSII_SYNC ();
+
+	/* clear any pending master aborts */
+	status = read4 (REG_P1_CSR);
+	if (status & CLEAR_MASTER_ABORT) {
+		ret_val = NO_DEVICE_FOUND;
+		write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+	}
+
+	return ret_val;
+}
+
+
+int PCIWriteConfig (int bus, int dev, int fn, int reg, int width,
+		    unsigned long val)
+{
+	unsigned int conAdrVal;
+	unsigned int conDataReg = REG_CONFIG_DATA;
+	unsigned int status;
+	int ret_val = 0;
+
+
+	/* DEST bit hardcoded to 1: local pci is PCI-2 */
+	/* TYPE bit is hardcoded to 1: all config cycles are local */
+	conAdrVal = (1 << 24)
+		| ((bus & 0xFF) << 16)
+		| ((dev & 0xFF) << 11)
+		| ((fn & 0x07) << 8)
+		| (reg & 0xFC);
+
+	/* clear any pending master aborts */
+	write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+
+	/* Load the conAdrVal value first, then read from pb_conf_data */
+	write4 (REG_CONFIG_ADDRESS, conAdrVal);
+	PSII_SYNC ();
+
+
+	/* Note: documentation does not match the pspan library code */
+	/* Note: *pData comes back as -1 if device is not present */
+	switch (width) {
+	case 4:
+		write4 (conDataReg, val);
+		break;
+	case 2:
+		write2 (conDataReg, val);
+		break;
+	case 1:
+		write1 (conDataReg, val);
+		break;
+	default:
+		ret_val = ILLEGAL_REG_OFFSET;
+		break;
+	}
+	PSII_SYNC ();
+
+	/* clear any pending master aborts */
+	status = read4 (REG_P1_CSR);
+	if (status & CLEAR_MASTER_ABORT) {
+		ret_val = NO_DEVICE_FOUND;
+		write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
+	}
+
+	return ret_val;
+}
+
+
+int pci_read_config_byte (int bus, int dev, int fn, int reg,
+			  unsigned char *val)
+{
+	unsigned long read_val;
+	int ret_val;
+
+	ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val);
+	*val = read_val & 0xFF;
+
+	return ret_val;
+}
+
+int pci_write_config_byte (int bus, int dev, int fn, int reg,
+			   unsigned char val)
+{
+	return PCIWriteConfig (bus, dev, fn, reg, 1, val);
+}
+
+int pci_read_config_word (int bus, int dev, int fn, int reg,
+			  unsigned short *val)
+{
+	unsigned long read_val;
+	int ret_val;
+
+	ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val);
+	*val = read_val & 0xFFFF;
+
+	return ret_val;
+}
+
+int pci_write_config_word (int bus, int dev, int fn, int reg,
+			   unsigned short val)
+{
+	return PCIWriteConfig (bus, dev, fn, reg, 2, val);
+}
+
+int pci_read_config_dword (int bus, int dev, int fn, int reg,
+			   unsigned long *val)
+{
+	return PCIReadConfig (bus, dev, fn, reg, 4, val);
+}
+
+int pci_write_config_dword (int bus, int dev, int fn, int reg,
+			    unsigned long val)
+{
+	return PCIWriteConfig (bus, dev, fn, reg, 4, val);
+}
+
+#endif /* INCLUDE_PCI */
+
+int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode,
+	       unsigned char theChipSel, unsigned char *theValue, int RWFlag)
+{
+	int ret_val = 0;
+	unsigned int reg_value;
+
+	reg_value = PowerSpanRead (REG_I2C_CSR);
+
+	if (reg_value & I2C_CSR_ACT) {
+		printf ("Error: I2C busy\n");
+		ret_val = I2C_BUSY;
+	} else {
+		reg_value = ((theI2CAddress & 0xFF) << 24)
+			| ((theDevCode & 0x0F) << 12)
+			| ((theChipSel & 0x07) << 9)
+			| I2C_CSR_ERR;
+		if (RWFlag == I2C_WRITE) {
+			reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16);
+		}
+
+		PowerSpanWrite (REG_I2C_CSR, reg_value);
+		udelay (1);
+
+		do {
+			reg_value = PowerSpanRead (REG_I2C_CSR);
+
+			if ((reg_value & I2C_CSR_ACT) == 0) {
+				if (reg_value & I2C_CSR_ERR) {
+					ret_val = I2C_ERR;
+				} else {
+					*theValue =
+						(reg_value & I2C_CSR_DATA) >>
+						16;
+				}
+			}
+		} while (reg_value & I2C_CSR_ACT);
+	}
+
+	return ret_val;
+}
+
+int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue)
+{
+	return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
+			  theValue, I2C_READ);
+}
+
+int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue)
+{
+	return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
+			  &theValue, I2C_WRITE);
+}
+
+int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	char cmd;
+	int ret_val = 0;
+	unsigned int address = 0;
+	unsigned char value = 1;
+	unsigned char read_value;
+	int ii;
+	int error = 0;
+	unsigned char *mem_ptr;
+	unsigned char default_eeprom[] = EEPROM_DEFAULT;
+
+	if (argc < 2) {
+		goto usage;
+	}
+
+	cmd = argv[1][0];
+	if (argc > 2) {
+		address = simple_strtoul (argv[2], NULL, 16);
+		if (argc > 3) {
+			value = simple_strtoul (argv[3], NULL, 16) & 0xFF;
+		}
+	}
+
+	switch (cmd) {
+	case 'r':
+		if (address > 256) {
+			printf ("Illegal Address\n");
+			goto usage;
+		}
+		printf ("@0x%x: ", address);
+		for (ii = 0; ii < value; ii++) {
+			if (EEPROMRead (address + ii, &read_value) !=
+			    0) {
+				printf ("Read Error\n");
+			} else {
+				printf ("0x%02x ", read_value);
+			}
+
+			if (((ii + 1) % 16) == 0) {
+				printf ("\n");
+			}
+		}
+		printf ("\n");
+		break;
+	case 'w':
+		if (address > 256) {
+			printf ("Illegal Address\n");
+			goto usage;
+		}
+		if (argc < 4) {
+			goto usage;
+		}
+		if (EEPROMWrite (address, value) != 0) {
+			printf ("Write Error\n");
+		}
+		break;
+	case 'g':
+		if (argc != 3) {
+			goto usage;
+		}
+		mem_ptr = (unsigned char *) address;
+		for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
+		     ii++) {
+			if (EEPROMRead (ii, &read_value) != 0) {
+				printf ("Read Error\n");
+				error = 1;
+			} else {
+				*mem_ptr = read_value;
+				mem_ptr++;
+			}
+		}
+		break;
+	case 'p':
+		if (argc != 3) {
+			goto usage;
+		}
+		mem_ptr = (unsigned char *) address;
+		for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
+		     ii++) {
+			if (EEPROMWrite (ii, *mem_ptr) != 0) {
+				printf ("Write Error\n");
+				error = 1;
+			}
+
+			mem_ptr++;
+		}
+		break;
+	case 'd':
+		if (argc != 2) {
+			goto usage;
+		}
+		for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
+		     ii++) {
+			if (EEPROMWrite (ii, default_eeprom[ii]) != 0) {
+				printf ("Write Error\n");
+				error = 1;
+			}
+		}
+		break;
+	default:
+		goto usage;
+	}
+
+	goto done;
+      usage:
+	printf ("Usage:\n%s\n", cmdtp->help);
+
+      done:
+	return ret_val;
+
+}
+
+U_BOOT_CMD (eeprom, 4, 0, do_eeprom,
+	    "eeprom  - read/write/copy to/from the PowerSpan II eeprom\n",
+	    "eeprom r OFF [NUM]\n"
+	    "    - read NUM words starting at OFF\n"
+	    "eeprom w OFF VAL\n"
+	    "    - write word VAL at offset OFF\n"
+	    "eeprom g ADD\n"
+	    "    - store contents of eeprom at address ADD\n"
+	    "eeprom p ADD\n"
+	    "    - put data stored at address ADD into the eeprom\n"
+	    "eeprom d\n" "    - return eeprom to default contents\n");
+
+unsigned int PowerSpanRead (unsigned int theOffset)
+{
+	volatile unsigned int *ptr =
+		(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+	unsigned int ret_val;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("PowerSpanRead: offset=%08x ", theOffset);
+	}
+#endif
+	ret_val = *ptr;
+	PSII_SYNC ();
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("value=%08x\n", ret_val);
+	}
+#endif
+
+	return ret_val;
+}
+
+void PowerSpanWrite (unsigned int theOffset, unsigned int theValue)
+{
+	volatile unsigned int *ptr =
+		(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset,
+			theValue);
+	}
+#endif
+	*ptr = theValue;
+	PSII_SYNC ();
+}
+
+/**
+ * Sets the indicated bits in the indicated register.
+ * @param theOffset [IN] the register to access.
+ * @param theMask   [IN] bits set in theMask will be set in the register.
+ */
+void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask)
+{
+	volatile unsigned int *ptr =
+		(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+	unsigned int register_value;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("PowerSpanSetBits: offset=%08x mask=%02x\n",
+			theOffset, theMask);
+	}
+#endif
+	register_value = *ptr;
+	PSII_SYNC ();
+
+	register_value |= theMask;
+	*ptr = register_value;
+	PSII_SYNC ();
+}
+
+/**
+ * Clears the indicated bits in the indicated register.
+ * @param theOffset [IN] the register to access.
+ * @param theMask   [IN] bits set in theMask will be cleared in the register.
+ */
+void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask)
+{
+	volatile unsigned int *ptr =
+		(volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
+	unsigned int register_value;
+
+#ifdef VERBOSITY
+	if (gVerbosityLevel > 1) {
+		printf ("PowerSpanClearBits: offset=%08x mask=%02x\n",
+			theOffset, theMask);
+	}
+#endif
+	register_value = *ptr;
+	PSII_SYNC ();
+
+	register_value &= ~theMask;
+	*ptr = register_value;
+	PSII_SYNC ();
+}
+
+/**
+ * Configures a slave image on the local bus, based on the parameters and some hardcoded system values.
+ * Slave Images are images that cause the PowerSpan II to be a master on the PCI bus.  Thus, they
+ *  are outgoing from the standpoint of the local bus.
+ * @param theImageIndex    [IN] the PowerSpan II image to set (assumed to be 0-7).
+ * @param theBlockSize     [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]).
+ * @param theMemIOFlag     [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
+ * @param theEndianness    [IN] the endian bits for the image (already shifted, use defines).
+ * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
+ * @param thePCIBaseAddr   [IN] the PCI address for the image (assumed to be valid with provided block size).
+ */
+int SetSlaveImage (int theImageIndex, unsigned int theBlockSize,
+		   int theMemIOFlag, int theEndianness,
+		   unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr)
+{
+	unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF;
+	unsigned int reg_value = 0;
+
+	/* Make sure that the Slave Image is disabled */
+	PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset),
+			    PB_SLAVE_CSR_IMG_EN);
+
+	/* Setup the mask required for requested PB Slave Image configuration */
+	reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24);
+	if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) {
+		reg_value |= PB_SLAVE_CSR_MEM_IO;
+	}
+
+	/* hardcoding the following:
+	   TA_EN = 1
+	   MD_EN = 0
+	   MODE  = 0
+	   PRKEEP = 0
+	   RD_AMT = 0
+	 */
+	PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value);
+
+	/* these values are not checked by software */
+	PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr);
+	PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr);
+
+	/* Enable the Slave Image */
+	PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset),
+			  PB_SLAVE_CSR_IMG_EN);
+
+	return 0;
+}
+
+/**
+ * Configures a target image on the local bus, based on the parameters and some hardcoded system values.
+ * Target Images are used when the PowerSpan II is acting as a target for an access.  Thus, they
+ *  are incoming from the standpoint of the local bus.
+ * In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI
+ *  base address will not be updated; makes sense given that the hosts own memory should be mapped to
+ *  PCI address 0x00000000.
+ * @param theImageIndex    [IN] the PowerSpan II image to set.
+ * @param theBlockSize     [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]).
+ * @param theMemIOFlag     [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
+ * @param theEndianness    [IN] the endian bits for the image (already shifted, use defines).
+ * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
+ * @param thePCIBaseAddr   [IN] the PCI address for the image (assumed to be valid with provided block size).
+ */
+int SetTargetImage (int theImageIndex, unsigned int theBlockSize,
+		    int theMemIOFlag, int theEndianness,
+		    unsigned int theLocalBaseAddr,
+		    unsigned int thePCIBaseAddr)
+{
+	unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF;
+	unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF;
+	unsigned int reg_value = 0;
+
+	/* Make sure that the Slave Image is disabled */
+	PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset),
+			    PB_SLAVE_CSR_IMG_EN);
+
+	/* Setup the mask required for requested PB Slave Image configuration */
+	reg_value =
+		PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) |
+		PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness;
+	if (theMemIOFlag == PX_TGT_USE_MEM_IO) {
+		reg_value |= PX_TGT_MEM_IO;
+	}
+
+	/* hardcoding the following:
+	   TA_EN = 1
+	   BAR_EN = 1
+	   MD_EN = 0
+	   MODE  = 0
+	   DEST  = 0
+	   RTT = 01010
+	   GBL = 0
+	   CI = 0
+	   WTT = 00010
+	   PRKEEP = 0
+	   MRA = 0
+	   RD_AMT = 0
+	 */
+	PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value);
+
+	PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset),
+			theLocalBaseAddr);
+
+	if (thePCIBaseAddr != (unsigned int) NULL) {
+		PowerSpanWrite ((REGS_P1_BST + pci_reg_offset),
+				thePCIBaseAddr);
+	}
+
+	/* Enable the Slave Image */
+	PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset),
+			  PB_SLAVE_CSR_IMG_EN);
+
+	return 0;
+}
+
+int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	char cmd;
+	int ret_val = 1;
+	unsigned int image_index;
+	unsigned int block_size;
+	unsigned int mem_io;
+	unsigned int local_addr;
+	unsigned int pci_addr;
+	int endianness;
+
+	if (argc != 8) {
+		goto usage;
+	}
+
+	cmd = argv[1][0];
+	image_index = simple_strtoul (argv[2], NULL, 16);
+	block_size = simple_strtoul (argv[3], NULL, 16);
+	mem_io = simple_strtoul (argv[4], NULL, 16);
+	endianness = argv[5][0];
+	local_addr = simple_strtoul (argv[6], NULL, 16);
+	pci_addr = simple_strtoul (argv[7], NULL, 16);
+
+
+	switch (cmd) {
+	case 'i':
+		if (tolower (endianness) == 'b') {
+			endianness = PX_TGT_CSR_BIG_END;
+		} else if (tolower (endianness) == 'l') {
+			endianness = PX_TGT_CSR_TRUE_LEND;
+		} else {
+			goto usage;
+		}
+		SetTargetImage (image_index, block_size, mem_io,
+				endianness, local_addr, pci_addr);
+		break;
+	case 'o':
+		if (tolower (endianness) == 'b') {
+			endianness = PB_SLAVE_CSR_BIG_END;
+		} else if (tolower (endianness) == 'l') {
+			endianness = PB_SLAVE_CSR_TRUE_LEND;
+		} else {
+			goto usage;
+		}
+		SetSlaveImage (image_index, block_size, mem_io,
+			       endianness, local_addr, pci_addr);
+		break;
+	default:
+		goto usage;
+	}
+
+	goto done;
+usage:
+	printf ("Usage:\n%s\n", cmdtp->help);
+
+done:
+	return ret_val;
+}
diff --git a/board/amirix/ap1000/powerspan.h b/board/amirix/ap1000/powerspan.h
new file mode 100755
index 0000000..4e9a8c1
--- /dev/null
+++ b/board/amirix/ap1000/powerspan.h
@@ -0,0 +1,170 @@
+/**
+ * @file powerspan.h Header file for PowerSpan II code.
+ */
+
+/*
+ * (C) Copyright 2005
+ * AMIRIX Systems Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef POWERSPAN_H
+#define POWERSPAN_H
+
+#define CLEAR_MASTER_ABORT 0xdeadbeef
+#define NO_DEVICE_FOUND     -1
+#define ILLEGAL_REG_OFFSET  -2
+#define I2C_BUSY            -3
+#define I2C_ERR             -4
+
+#define REG_P1_CSR          0x004
+#define REGS_P1_BST         0x018
+#define REG_P1_ERR_CSR      0x150
+#define REG_P1_MISC_CSR     0x160
+#define REGS_P1_TGT_CSR     0x100
+#define REGS_P1_TGT_TADDR   0x104
+#define REGS_PB_SLAVE_CSR   0x200
+#define REGS_PB_SLAVE_TADDR 0x204
+#define REGS_PB_SLAVE_BADDR 0x208
+#define REG_CONFIG_ADDRESS  0x290
+#define REG_CONFIG_DATA     0x294
+#define REG_PB_ERR_CSR      0x2B0
+#define REG_PB_MISC_CSR     0x2C0
+#define REG_MISC_CSR        0x400
+#define REG_I2C_CSR         0x408
+#define REG_RESET_CSR       0x40C
+#define REG_ISR0            0x410
+#define REG_ISR1            0x414
+#define REG_IER0            0x418
+#define REG_MBOX_MAP        0x420
+#define REG_HW_MAP          0x42C
+#define REG_IDR             0x444
+
+#define CSR_MEMORY_SPACE_ENABLE 0x00000002
+#define CSR_PCI_MASTER_ENABLE   0x00000004
+
+#define P1_BST_OFF  0x04
+
+#define PX_ERR_ERR_STATUS   0x01000000
+
+#define PX_MISC_CSR_MAX_RETRY_MASK  0x00000F00
+#define PX_MISC_CSR_MAX_RETRY       0x00000F00
+#define PX_MISC_REG_BAR_ENABLE      0x00008000
+#define PB_MISC_TEA_ENABLE          0x00000010
+#define PB_MISC_MAC_TEA             0x00000040
+
+#define P1_TGT_IMAGE_OFF    0x010
+#define PX_TGT_CSR_IMG_EN   0x80000000
+#define PX_TGT_CSR_TA_EN    0x40000000
+#define PX_TGT_CSR_BAR_EN   0x20000000
+#define PX_TGT_CSR_MD_EN    0x10000000
+#define PX_TGT_CSR_MODE     0x00800000
+#define PX_TGT_CSR_DEST     0x00400000
+#define PX_TGT_CSR_MEM_IO   0x00200000
+#define PX_TGT_CSR_GBL      0x00080000
+#define PX_TGT_CSR_CL       0x00040000
+#define PX_TGT_CSR_PRKEEP   0x00000080
+
+#define PX_TGT_CSR_BS_MASK      0x0F000000
+#define PX_TGT_MEM_IO           0x00200000
+#define PX_TGT_CSR_RTT_MASK     0x001F0000
+#define PX_TGT_CSR_RTT_READ     0x000A0000
+#define PX_TGT_CSR_WTT_MASK     0x00001F00
+#define PX_TGT_CSR_WTT_WFLUSH   0x00000200
+#define PX_TGT_CSR_END_MASK     0x00000060
+#define PX_TGT_CSR_BIG_END      0x00000040
+#define PX_TGT_CSR_TRUE_LEND    0x00000060
+#define PX_TGT_CSR_RDAMT_MASK   0x00000007
+
+#define PX_TGT_CSR_BS_64MB  0xa
+#define PX_TGT_CSR_BS_16MB  0x8
+
+#define PX_TGT_USE_MEM_IO   1
+#define PX_TGT_NOT_MEM_IO   0
+
+#define PB_SLAVE_IMAGE_OFF  0x010
+#define PB_SLAVE_CSR_IMG_EN 0x80000000
+#define PB_SLAVE_CSR_TA_EN  0x40000000
+#define PB_SLAVE_CSR_MD_EN  0x20000000
+#define PB_SLAVE_CSR_MODE   0x00800000
+#define PB_SLAVE_CSR_DEST   0x00400000
+#define PB_SLAVE_CSR_MEM_IO 0x00200000
+#define PB_SLAVE_CSR_PRKEEP 0x00000080
+
+#define PB_SLAVE_CSR_BS_MASK    0x1F000000
+#define PB_SLAVE_CSR_END_MASK   0x00000060
+#define PB_SLAVE_CSR_BIG_END    0x00000040
+#define PB_SLAVE_CSR_TRUE_LEND  0x00000060
+#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007
+
+#define PB_SLAVE_USE_MEM_IO 1
+#define PB_SLAVE_NOT_MEM_IO 0
+
+
+#define MISC_CSR_PCI1_LOCK  0x00000080
+
+#define I2C_CSR_ADDR      0xFF000000  /* Specifies I2C Device Address to be Accessed */
+#define I2C_CSR_DATA      0x00FF0000  /* Specifies the Required Data for a Write */
+#define I2C_CSR_DEV_CODE  0x0000F000  /* Device Select. I2C 4-bit Device Code */
+#define I2C_CSR_CS        0x00000E00  /* Chip Select */
+#define I2C_CSR_RW        0x00000100  /* Read/Write */
+#define I2C_CSR_ACT       0x00000080  /* I2C Interface Active */
+#define I2C_CSR_ERR       0x00000040  /* Error */
+
+#define I2C_EEPROM_DEV      0xa
+#define I2C_EEPROM_CHIP_SEL 0
+
+#define I2C_READ    0
+#define I2C_WRITE   1
+
+#define RESET_CSR_EEPROM_LOAD 0x00000010
+
+#define ISR_CLEAR_ALL   0xFFFFFFFF
+
+#define IER0_DMA_INTS_EN    0x0F000000
+#define IER0_PCI_1_EN       0x00400000
+#define IER0_HW_INTS_EN     0x003F0000
+#define IER0_MB_INTS_EN     0x000000FF
+#define IER0_DEFAULT        (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN)
+
+#define MBOX_MAP_TO_INT4    0xCCCCCCCC
+
+#define HW_MAP_HW4_TO_INT4  0x000C0000
+
+#define IDR_PCI_A_OUT   0x40000000
+#define IDR_MBOX_OUT    0x10000000
+
+
+int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val);
+int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val);
+int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val);
+int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val);
+int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val);
+int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val);
+
+unsigned int PowerSpanRead(unsigned int theOffset);
+void PowerSpanWrite(unsigned int theOffset, unsigned int theValue);
+
+int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag);
+
+int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val);
+int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val);
+
+int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
+int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
+
+#endif
diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c
new file mode 100755
index 0000000..39c4157
--- /dev/null
+++ b/board/amirix/ap1000/serial.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2002
+ * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+#include <common.h>
+#include <command.h>
+#include <config.h>
+
+#include <ns16550.h>
+
+#if 0
+#include "serial.h"
+#endif
+
+const NS16550_t COM_PORTS[] =
+	{ (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
+
+#undef CFG_DUART_CHAN
+#define CFG_DUART_CHAN gComPort
+static int gComPort = 0;
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+
+	(void) NS16550_init (COM_PORTS[0], clock_divisor);
+	gComPort = 0;
+
+	return 0;
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n') {
+		NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
+	}
+
+	NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
+}
+
+int serial_getc (void)
+{
+	return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
+}
+
+int serial_tstc (void)
+{
+	return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+	NS16550_reinit (COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	NS16550_reinit (COM_PORTS[1], clock_divisor);
+#endif
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif /* CFG_CMD_KGDB */
diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds
new file mode 100755
index 0000000..109e7fe
--- /dev/null
+++ b/board/amirix/ap1000/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/amirix/ap1000/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/armadillo/Makefile b/board/armadillo/Makefile
new file mode 100755
index 0000000..52ea7f2
--- /dev/null
+++ b/board/armadillo/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= armadillo.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/armadillo/armadillo.c b/board/armadillo/armadillo.c
new file mode 100755
index 0000000..de04c66
--- /dev/null
+++ b/board/armadillo/armadillo.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Activate LED flasher */
+	IO_LEDFLSH = 0x40;
+
+	/* arch number MACH_TYPE_ARMADILLO - not official*/
+	gd->bd->bi_arch_number = 83;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/board/armadillo/config.mk b/board/armadillo/config.mk
new file mode 100755
index 0000000..23c432f
--- /dev/null
+++ b/board/armadillo/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#address where u-boot will be relocated
+TEXT_BASE = 0xc0f80000
diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c
new file mode 100755
index 0000000..037a643
--- /dev/null
+++ b/board/armadillo/flash.c
@@ -0,0 +1,338 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Flash driver for armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x400000
+
+/*value used by hermit is 0x200*/
+/*document says sector size is either 64k in low mem reg and 8k in high mem reg*/
+#define MAIN_SECT_SIZE  0x10000
+
+#define UNALIGNED_MASK (3)
+#define FL_WORD(addr) (*(volatile unsigned short*)(addr))
+#define FLASH_TIMEOUT 20000000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK);
+		/*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] =
+				flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (FUJ_MANUFACT & FLASH_VENDMASK):
+		printf ("Fujitsu: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+/*
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+		printf ("28F128J3 (128Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+*/
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+/*
+Done:	;
+*/
+}
+
+/*
+ *  * Loop until both write state machines complete.
+ *   */
+static unsigned short flash_status_wait (unsigned long addr,
+					 unsigned short value)
+{
+	unsigned short status;
+	long timeout = FLASH_TIMEOUT;
+
+	while (((status = (FL_WORD (addr))) != value) && timeout > 0) {
+		timeout--;
+	}
+	return status;
+}
+
+/*
+ * Loop until the Write State machine is ready, then do a full error
+ * check.  Clear status and leave the flash in Read Array mode; return
+ * 0 for no error, -1 for error.
+ */
+static int flash_status_full_check (unsigned long addr, unsigned short value1,
+				    unsigned short value2)
+{
+	unsigned short status1, status2;
+
+	status1 = flash_status_wait (addr, value1);
+	status2 = flash_status_wait (addr + 2, value2);
+	return (status1 != value1 || status2 != value2) ? -1 : 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+	unsigned long base;
+	unsigned long addr;
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (FUJ_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	printf ("Erasing %d sectors starting at sector %2d.\n"
+		"This make take some time ... ",
+		s_last - s_first, sect);
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		/* ARM simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			addr = sect * MAIN_SECT_SIZE;
+			addr &= ~(unsigned long) UNALIGNED_MASK;	/* word align */
+			base = addr & 0xF0000000;
+
+			FL_WORD (base + (0x555 << 1)) = 0xAA;
+			FL_WORD (base + (0x2AA << 1)) = 0x55;
+			FL_WORD (base + (0x555 << 1)) = 0x80;
+			FL_WORD (base + (0x555 << 1)) = 0xAA;
+			FL_WORD (base + (0x2AA << 1)) = 0x55;
+			FL_WORD (addr) = 0x30;
+			if (flash_status_full_check (addr, 0xFFFF, 0xFFFF))
+				return ERR_PROTECTED;
+		}
+	}
+	printf ("\nDone.\n");
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ushort data)
+{
+	int flag;
+	unsigned long base;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((FL_WORD (dest) & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*if(dest & UNALIGNED_MASK) return ERR_ALIGN; */
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	base = dest & 0xF0000000;
+	FL_WORD (base + (0x555 << 1)) = 0xAA;
+	FL_WORD (base + (0x2AA << 1)) = 0x55;
+	FL_WORD (base + (0x555 << 1)) = 0xA0;
+	FL_WORD (dest) = data;
+	/*printf("writing 0x%p = 0x%x\n",dest,data); */
+	if (flash_status_wait (dest, data) != data)
+		return ERR_PROG_ERROR;
+
+	if (flag)
+		enable_interrupts ();
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+	printf ("Writing %d short data to 0x%p from 0x%p.\n ", cnt, wp, src);
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		printf ("\nDone.\n");
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/board/armadillo/lowlevel_init.S b/board/armadillo/lowlevel_init.S
new file mode 100755
index 0000000..6cf6426
--- /dev/null
+++ b/board/armadillo/lowlevel_init.S
@@ -0,0 +1,66 @@
+/*
+ * Initialization stuff - taken from hermit
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+/* setting up the memory */
+#define 	SRAM_START 	0x60000000
+#define 	SRAM_SIZE	0x0000c000
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	r0, #0x70		/* 32-bit code + data, MMU mandatory */
+	mcr	p15, 0, r0, c1, c0, 0	/* MMU init */
+
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	mov	r0, #0x80000000		/* I/O base */
+
+	mov	r1, #0x6		/* CLKCTL_73 in SYSCON3 */
+	add	r2, r0, #0x2200		/* address of SYSCON3 in r2 */
+	str	r1, [r2]		/* set clock speed to 73.728 MHz */
+
+	mov	r1, #0x81		/* 64KHz DRAM refresh period */
+	str	r1, [r0, #0x200]	/* set DRFPR */
+
+	mov	r1, #0x500		/* permanent enable, 16bits wide */
+	add	r1, r1, #0x42		/* 128Mbit, CAS lat = 2 SDRAM */
+	add	r2, r0, #0x2300		/* load address in r2 */
+	str	r1, [r2]
+
+	mov	r1, #0x100		/* SDRAM refresh rate */
+	add	r2, r0, #0x2340		/* load address in r2 */
+	str	r1, [r2]
+
+	mov	sp, #SRAM_START		/* init stack pointer */
+	add	sp, sp, #SRAM_SIZE
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/board/armadillo/u-boot.lds b/board/armadillo/u-boot.lds
new file mode 100755
index 0000000..64d946c
--- /dev/null
+++ b/board/armadillo/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm720t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/assabet/Makefile b/board/assabet/Makefile
new file mode 100755
index 0000000..c49f1b4
--- /dev/null
+++ b/board/assabet/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2004 (c) MontaVista Software, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= assabet.o
+SOBJS	:= setup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/assabet/assabet.c b/board/assabet/assabet.c
new file mode 100755
index 0000000..d3ccbb5
--- /dev/null
+++ b/board/assabet/assabet.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Board dependent initialisation
+ */
+
+#define ECOR			0x8000
+#define ECOR_RESET		0x80
+#define ECOR_LEVEL_IRQ		0x40
+#define ECOR_WR_ATTRIB		0x04
+#define ECOR_ENABLE		0x01
+
+#define ECSR			0x8002
+#define ECSR_IOIS8		0x20
+#define ECSR_PWRDWN		0x04
+#define ECSR_INT		0x02
+#define SMC_IO_SHIFT		2
+#define NCR_0           	(*((volatile u_char *)(0x100000a0)))
+#define NCR_ENET_OSC_EN		(1<<3)
+
+static inline u8
+readb(volatile u8 * p)
+{
+	return *p;
+}
+
+static inline void
+writeb(u8 v, volatile u8 * p)
+{
+	*p = v;
+}
+
+static void
+smc_init(void)
+{
+	u8 ecor;
+	u8 ecsr;
+	volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
+
+	NCR_0 |= NCR_ENET_OSC_EN;
+	udelay(100);
+
+	ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
+	writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
+	udelay(100);
+
+	/*
+	 * The device will ignore all writes to the enable bit while
+	 * reset is asserted, even if the reset bit is cleared in the
+	 * same write.  Must clear reset first, then enable the device.
+	 */
+	writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
+	writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
+
+	/*
+	 * Set the appropriate byte/word mode.
+	 */
+	ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
+	ecsr |= ECSR_IOIS8;
+	writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
+	udelay(100);
+}
+
+static void
+neponset_init(void)
+{
+	smc_init();
+}
+
+int
+board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	neponset_init();
+
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/board/assabet/config.mk b/board/assabet/config.mk
new file mode 100755
index 0000000..74cb419
--- /dev/null
+++ b/board/assabet/config.mk
@@ -0,0 +1,7 @@
+#
+# SA-1110 based Intel Assabet board
+#
+# The Intel Assabet 1 bank of 32 MiB SDRAM
+#
+
+TEXT_BASE = 0xc1f00000
diff --git a/board/assabet/setup.S b/board/assabet/setup.S
new file mode 100755
index 0000000..56ea0dd
--- /dev/null
+++ b/board/assabet/setup.S
@@ -0,0 +1,136 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*-----------------------------------------------------------------------
+ * Board defines:
+ */
+
+#define MDCNFG		0x00
+#define MDCAS00		0x04
+#define MDCAS01		0x08
+#define MDCAS02		0x0C
+#define MSC0		0x10
+#define MSC1		0x14
+#define MECR		0x18
+#define MDREFR		0x1C
+#define MDCAS20		0x20
+#define MDCAS21		0x24
+#define MDCAS22		0x28
+#define MSC2		0x2C
+#define SMCNFG		0x30
+
+#define ASSABET_BCR		(0x12000000)
+#define ASSABET_BCR_DB1110	(0x00a07490 | (0<<16) | (0<<17))
+#define ASSABET_SCR_nNEPONSET	(1 << 9)
+#define NEPONSET_LEDS		(0x10000010)
+
+
+/*-----------------------------------------------------------------------
+ * Setup parameters for the board:
+ */
+
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+mdcnfg:		.long	0x72547254
+mdcas00:	.long	0xaaaaaa7f
+mdcas01:	.long	0xaaaaaaaa
+mdcas02:	.long	0xaaaaaaaa
+msc0:		.long	0x4b384370
+msc1:		.long	0x22212419
+mecr:		.long	0x994a994a
+mdrefr:		.long	0x04340327
+mdcas20:	.long	0xaaaaaa7f
+mdcas21:	.long	0xaaaaaaaa
+mdcas22:	.long	0xaaaaaaaa
+msc2:		.long	0x42196669
+smcnfg:		.long	0x00000000
+
+BCR:		.long	ASSABET_BCR
+BCR_DB1110:	.long	ASSABET_BCR_DB1110
+LEDS:		.long	NEPONSET_LEDS
+
+
+	.globl lowlevel_init
+lowlevel_init:
+
+	/* Setting up the memory and stuff */
+
+	ldr	r0, MEM_BASE
+	ldr	r1, mdcas00
+	str	r1, [r0, #MDCAS00]
+	ldr	r1, mdcas01
+	str	r1, [r0, #MDCAS01]
+	ldr	r1, mdcas02
+	str	r1, [r0, #MDCAS02]
+	ldr	r1, mdcas20
+	str	r1, [r0, #MDCAS20]
+	ldr	r1, mdcas21
+	str	r1, [r0, #MDCAS21]
+	ldr	r1, mdcas22
+	str	r1, [r0, #MDCAS22]
+	ldr	r1, mdrefr
+	str	r1, [r0, #MDREFR]
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+	ldr	r1, msc1
+	str	r1, [r0, #MSC1]
+	ldr	r1, msc2
+	str	r1, [r0, #MSC2]
+	ldr	r1, smcnfg
+	str	r1, [r0, #SMCNFG]
+
+	ldr	r1, mdcnfg
+	str	r1, [r0, #MDCNFG]
+
+	/* Load something to activate bank */
+	ldr	r2, MEM_START
+.rept	8
+	ldr	r3, [r2]
+.endr
+
+	/* Enable SDRAM */
+	orr	r1, r1, #0x00000001
+	str	r1, [r0, #MDCNFG]
+
+	ldr	r1, BCR
+	ldr	r2, BCR_DB1110
+	str	r2, [r1]
+
+	ldr	r1, LEDS
+	mov	r0, #0x3
+	str	r0, [r1]
+
+	/* All done... */
+	mov	pc, lr
diff --git a/board/assabet/u-boot.lds b/board/assabet/u-boot.lds
new file mode 100755
index 0000000..7a3a9b8
--- /dev/null
+++ b/board/assabet/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/sa1100/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile
new file mode 100755
index 0000000..ec77da9
--- /dev/null
+++ b/board/at91rm9200dk/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= at91rm9200dk.o at45.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c
new file mode 100755
index 0000000..3c00132
--- /dev/null
+++ b/board/at91rm9200dk/at45.c
@@ -0,0 +1,621 @@
+/* Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
+the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS	(0xC << 16)
+#define DATAFLASH_TCHS	(0x1 << 24)
+
+#define AT91C_TIMEOUT_WRDY			200000
+#define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
+#define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
+
+void AT91F_SpiInit(void) {
+
+/*-------------------------------------------------------------------*/
+/*	SPI DataFlash Init								*/
+/*-------------------------------------------------------------------*/
+	/* Configure PIOs */
+	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+	/* Enable CLock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
+
+	/* Reset the SPI */
+	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
+
+	/* Configure SPI in Master Mode with No CS selected !!! */
+	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+
+	/* Configure CS0 and CS3 */
+	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+}
+
+void AT91F_SpiEnable(int cs) {
+	switch(cs) {
+	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
+		break;
+	case 3:	/* Configure SPI CS3 for Serial DataFlash Card */
+		/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
+		AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7;	/* Set in PIO mode */
+		AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7;	/* Configure in output */
+		/* Clear Output */
+		AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
+		/* Configure PCS */
+		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+		break;
+	}
+
+	/* SPI_Enable */
+	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+/*----------------------------------------------------------------------------*/
+/* \fn    AT91F_SpiWrite						      */
+/* \brief Set the PDC registers for a transfert				      */
+/*----------------------------------------------------------------------------*/
+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
+{
+	unsigned int timeout;
+
+	pDesc->state = BUSY;
+
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+
+	/* Initialize the Transmit and Receive Pointer */
+	AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
+	AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
+
+	/* Intialize the Transmit and Receive Counters */
+	AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
+	AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
+
+	if ( pDesc->tx_data_size != 0 ) {
+		/* Initialize the Next Transmit and Next Receive Pointer */
+		AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
+		AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
+
+		/* Intialize the Next Transmit and Next Receive Counters */
+		AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
+		AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
+	}
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+	timeout = 0;
+
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
+	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+	pDesc->state = IDLE;
+
+	if (timeout >= CFG_SPI_WRITE_TOUT){
+		printf("Error Timeout\n\r");
+		return DATAFLASH_ERROR;
+	}
+
+	return DATAFLASH_OK;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashSendCommand					*/
+/* \brief Generic function to send a command to the dataflash		*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char OpCode,
+	unsigned int CmdSize,
+	unsigned int DataflashAddress)
+{
+    unsigned int adr;
+
+	if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* process the address to obtain page address and byte address */
+	adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
+
+	/* fill the  command  buffer */
+	pDataFlash->pDataFlashDesc->command[0] = OpCode;
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
+		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
+		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
+		pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
+	} else {
+		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
+		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
+		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
+		pDataFlash->pDataFlashDesc->command[4] = 0;
+	}
+	pDataFlash->pDataFlashDesc->command[5] = 0;
+	pDataFlash->pDataFlashDesc->command[6] = 0;
+	pDataFlash->pDataFlashDesc->command[7] = 0;
+
+	/* Initialize the SpiData structure for the spi write fuction */
+	pDataFlash->pDataFlashDesc->tx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->tx_cmd_size =  CmdSize ;
+	pDataFlash->pDataFlashDesc->rx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->rx_cmd_size =  CmdSize ;
+
+	/* send the command and read the data */
+	return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashGetStatus					*/
+/* \brief Read the status register of the dataflash			*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
+{
+	AT91S_DataFlashStatus status;
+
+	/* if a transfert is in progress ==> return 0 */
+	if( (pDesc->state) != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* first send the read status command (D7H) */
+	pDesc->command[0] = DB_STATUS;
+	pDesc->command[1] = 0;
+
+	pDesc->DataFlash_state  = GET_STATUS;
+	pDesc->tx_data_size 	= 0 ;	/* Transmit the command and receive response */
+	pDesc->tx_cmd_pt 		= pDesc->command ;
+	pDesc->rx_cmd_pt 		= pDesc->command ;
+	pDesc->rx_cmd_size 		= 2 ;
+	pDesc->tx_cmd_size 		= 2 ;
+	status = AT91F_SpiWrite (pDesc);
+
+	pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+
+	return status;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashWaitReady					*/
+/* \brief wait for dataflash ready (bit7 of the status register == 1)	*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
+{
+	pDataFlashDesc->DataFlash_state = IDLE;
+
+	do {
+		AT91F_DataFlashGetStatus(pDataFlashDesc);
+		timeout--;
+	} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
+
+	if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+		return DATAFLASH_ERROR;
+
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashContinuousRead 				*/
+/* Object              : Continuous stream Read 				*/
+/* Input Parameters    : DataFlash Service					*/
+/*						: <src> = dataflash address	*/
+/*                     : <*dataBuffer> = data buffer pointer			*/
+/*                     : <sizeToRead> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
+	AT91PS_DataFlash pDataFlash,
+	int src,
+	unsigned char *dataBuffer,
+	int sizeToRead )
+{
+	AT91S_DataFlashStatus status;
+	/* Test the size to read in the device */
+	if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+		return DATAFLASH_MEMORY_OVERFLOW;
+
+	pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
+	pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
+
+	status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+	/* Send the command to the dataflash */
+	return(status);
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashPagePgmBuf				*/
+/* Object              : Main memory page program through buffer 1 or buffer 2	*/
+/* Input Parameters    : DataFlash Service					*/
+/*						: <*src> = Source buffer	*/
+/*                     : <dest> = dataflash destination address			*/
+/*                     : <SizeToWrite> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	unsigned int dest,
+	unsigned int SizeToWrite)
+{
+	int cmdsize;
+	pDataFlash->pDataFlashDesc->tx_data_pt = src ;
+	pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
+	pDataFlash->pDataFlashDesc->rx_data_pt = src;
+	pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+
+	cmdsize = 4;
+	/* Send the command to the dataflash */
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_MainMemoryToBufferTransfert			*/
+/* Object              : Read a page in the SRAM Buffer 1 or 2			*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned int page)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
+		return DATAFLASH_BAD_COMMAND;
+
+	/* no data to transmit or receive */
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*----------------------------------------------------------------------------- */
+/* Function Name       : AT91F_DataFlashWriteBuffer				*/
+/* Object              : Write data to the internal sram buffer 1 or 2		*/
+/* Input Parameters    : DataFlash Service					*/
+/*			: <BufferCommand> = command to write buffer1 or buffer2	*/
+/*                     : <*dataBuffer> = data buffer to write			*/
+/*                     : <bufferAddress> = address in the internal buffer	*/
+/*                     : <SizeToWrite> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned char *dataBuffer,
+	unsigned int bufferAddress,
+	int SizeToWrite )
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
+		return DATAFLASH_BAD_COMMAND;
+
+	/* buffer address must be lower than page size */
+	if (bufferAddress > pDataFlash->pDevice->pages_size)
+		return DATAFLASH_BAD_ADDRESS;
+
+	if ( (pDataFlash->pDataFlashDesc->state)  != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* Send first Write Command */
+	pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
+	pDataFlash->pDataFlashDesc->command[1] = 0;
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+	    	pDataFlash->pDataFlashDesc->command[2] = 0;
+	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
+	    	pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
+		cmdsize = 5;
+	} else {
+	    	pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
+	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
+	    	pDataFlash->pDataFlashDesc->command[4] = 0;
+		cmdsize = 4;
+	}
+
+	pDataFlash->pDataFlashDesc->tx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
+	pDataFlash->pDataFlashDesc->rx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
+
+	pDataFlash->pDataFlashDesc->rx_data_pt 	= dataBuffer ;
+	pDataFlash->pDataFlashDesc->tx_data_pt 	= dataBuffer ;
+	pDataFlash->pDataFlashDesc->rx_data_size 	= SizeToWrite ;
+	pDataFlash->pDataFlashDesc->tx_data_size 	= SizeToWrite ;
+
+	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_PageErase                                        */
+/* Object              : Erase a page 						*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PageErase(
+	AT91PS_DataFlash pDataFlash,
+	unsigned int page)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	/* no data to transmit or receive */
+    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_BlockErase                                       */
+/* Object              : Erase a Block 						*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_BlockErase(
+	AT91PS_DataFlash pDataFlash,
+	unsigned int block)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	/* no data to transmit or receive */
+    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_WriteBufferToMain				*/
+/* Object              : Write buffer to the main memory			*/
+/* Input Parameters    : DataFlash Service					*/
+/*		: <BufferCommand> = command to send to buffer1 or buffer2	*/
+/*                     : <dest> = main memory address				*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_WriteBufferToMain (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned int dest )
+{
+	int cmdsize;
+	/* Test if the buffer command is correct */
+	if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
+	    (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+	    (BufferCommand != DB_BUF2_PAGE_PGM) &&
+	    (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+		return DATAFLASH_BAD_COMMAND;
+
+	/* no data to transmit or receive */
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	/* Send the command to the dataflash */
+	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_PartialPageWrite					*/
+/* Object              : Erase partielly a page					*/
+/* Input Parameters    : <page> = page number					*/
+/*			: <AdrInpage> = adr to begin the fading			*/
+/*                     : <length> = Number of bytes to erase			*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PartialPageWrite (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	unsigned int dest,
+	unsigned int size)
+{
+	unsigned int page;
+	unsigned int AdrInPage;
+
+	page = dest / (pDataFlash->pDevice->pages_size);
+	AdrInPage = dest % (pDataFlash->pDevice->pages_size);
+
+	/* Read the contents of the page in the Sram Buffer */
+	AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
+	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	/*Update the SRAM buffer */
+	AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
+
+	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+	/* Erase page if a 128 Mbits device */
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+		AT91F_PageErase(pDataFlash, page);
+		/* Rewrite the modified Sram Buffer in the main memory */
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	}
+
+	/* Rewrite the modified Sram Buffer in the main memory */
+	return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashWrite					*/
+/* Object              :							*/
+/* Input Parameters    : <*src> = Source buffer					*/
+/*                     : <dest> = dataflash adress				*/
+/*                     : <size> = data buffer size				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWrite(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	int dest,
+	int size )
+{
+	unsigned int length;
+	unsigned int page;
+	unsigned int status;
+
+	AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+	if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+		return DATAFLASH_MEMORY_OVERFLOW;
+
+	/* If destination does not fit a page start address */
+	if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size)))  != 0 ) {
+		length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
+
+		if (size < length)
+			length = size;
+
+		if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		/* Update size, source and destination pointers */
+		size -= length;
+		dest += length;
+		src += length;
+	}
+
+	while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+		/* program dataflash page */
+		page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
+
+		status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		status = AT91F_PageErase(pDataFlash, page);
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+		if (!status)
+			return DATAFLASH_ERROR;
+
+		status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
+		if(!status)
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		/* Update size, source and destination pointers */
+		size -= pDataFlash->pDevice->pages_size ;
+		dest += pDataFlash->pDevice->pages_size ;
+		src  += pDataFlash->pDevice->pages_size ;
+	}
+
+	/* If still some bytes to read */
+	if ( size > 0 ) {
+		/* program dataflash page */
+		if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	}
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashRead 					*/
+/* Object              : Read a block in dataflash				*/
+/* Input Parameters    : 							*/
+/* Return value		: 							*/
+/*------------------------------------------------------------------------------*/
+int AT91F_DataFlashRead(
+	AT91PS_DataFlash pDataFlash,
+	unsigned long addr,
+	unsigned long size,
+	char *buffer)
+{
+	unsigned long SizeToRead;
+
+	AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+	if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+		return -1;
+
+	while (size) {
+		SizeToRead = (size < 0x8000)? size:0x8000;
+
+		if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+			return -1;
+
+		if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
+			return -1;
+
+		size -= SizeToRead;
+		addr += SizeToRead;
+		buffer += SizeToRead;
+	}
+
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataflashProbe 					*/
+/* Object              : 							*/
+/* Input Parameters    : 							*/
+/* Return value	       : Dataflash status register				*/
+/*------------------------------------------------------------------------------*/
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
+{
+	AT91F_SpiEnable(cs);
+	AT91F_DataFlashGetStatus(pDesc);
+	return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+}
+
+#endif
diff --git a/board/at91rm9200dk/at91rm9200dk.c b/board/at91rm9200dk/at91rm9200dk.c
new file mode 100755
index 0000000..77caed3
--- /dev/null
+++ b/board/at91rm9200dk/at91rm9200dk.c
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* Correct IRDA resistor problem */
+	/* Set PA23_TXD in Output */
+	(AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of AT91RM9200DK-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif	/* CONFIG_DRIVER_ETHER */
+
+/*
+ * Disk On Chip (NAND) Millenium initialization.
+ * The NAND lives in the CS2* space
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong nand_probe (ulong physadr);
+
+#define AT91_SMARTMEDIA_BASE 0x40000000	/* physical address to access memory on NCS3 */
+void nand_init (void)
+{
+	/* Setup Smart Media, fitst enable the address range of CS3 */
+	*AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
+	/* set the bus interface characteristics based on
+	   tDS Data Set up Time 30 - ns
+	   tDH Data Hold Time 20 - ns
+	   tALS ALE Set up Time 20 - ns
+	   16ns at 60 MHz ~= 3  */
+/*memory mapping structures */
+#define SM_ID_RWH	(5 << 28)
+#define SM_RWH		(1 << 28)
+#define SM_RWS		(0 << 24)
+#define SM_TDF		(1 << 8)
+#define SM_NWS		(3)
+	AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
+		AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
+		SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
+
+	/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
+	*AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
+		AT91C_PC3_BFBAA_SMWE;
+	*AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
+		AT91C_PC3_BFBAA_SMWE;
+
+	/* Configure PC2 as input (signal READY of the SmartMedia) */
+	*AT91C_PIOC_PER = AT91C_PC2_BFAVD;	/* enable direct output enable */
+	*AT91C_PIOC_ODR = AT91C_PC2_BFAVD;	/* disable output */
+
+	/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
+	*AT91C_PIOB_PER = AT91C_PIO_PB1;	/* enable direct output enable */
+	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */
+
+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
+	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
+		printf ("  No SmartMedia card inserted\n");
+#ifdef DEBUG
+	printf ("  SmartMedia card inserted\n");
+
+	printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
+#endif
+	printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
+}
+#endif
diff --git a/board/at91rm9200dk/config.mk b/board/at91rm9200dk/config.mk
new file mode 100755
index 0000000..9ce161e
--- /dev/null
+++ b/board/at91rm9200dk/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000
diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c
new file mode 100755
index 0000000..f6228ef
--- /dev/null
+++ b/board/at91rm9200dk/flash.c
@@ -0,0 +1,504 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush(void);
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef
+{
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgAT49BV16x4[] =
+{
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{  2, 32*1024 },	/*   2 * 32 kBytes sectors */
+	{ 30, 64*1024 },	/*  30 * 64 kBytes sectors */
+};
+
+OrgDef OrgAT49BV16x4A[] =
+{
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 31, 64*1024 },	/*  31 * 64 kBytes sectors */
+};
+
+OrgDef OrgAT49BV6416[] =
+{
+	{   8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 127, 64*1024 },	/* 127 * 64 kBytes sectors */
+};
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+/* AT49BV1614A Codes */
+#define FLASH_CODE1		0xAA
+#define FLASH_CODE2		0x55
+#define ID_IN_CODE		0x90
+#define ID_OUT_CODE		0xF0
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+#define CMD_SECTOR_UNLOCK	0x0070
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+void flash_identification (flash_info_t * info)
+{
+	volatile u16 manuf_code, device_code, add_device_code;
+
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_IN_CODE;
+
+	manuf_code = *(volatile u16 *) CFG_FLASH_BASE;
+	device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2);
+	add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1));
+
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_OUT_CODE;
+
+	/* Vendor type */
+	info->flash_id = ATM_MANUFACT & FLASH_VENDMASK;
+	printf ("Atmel: ");
+
+	if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) {
+
+		if ((add_device_code & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614A & FLASH_TYPEMASK)) {
+			info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK;
+			printf ("AT49BV1614A (16Mbit)\n");
+		} else {				/* AT49BV1614 Flash */
+			info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
+			printf ("AT49BV1614 (16Mbit)\n");
+		}
+
+	} else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) {
+		info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK;
+		printf ("AT49BV6416 (64Mbit)\n");
+	}
+}
+
+ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks)
+{
+	int i, nb_sectors = 0;
+
+	for (i=0; i<nb_blocks; i++){
+		nb_sectors += pOrgDef[i].sector_number;
+	}
+
+	return nb_sectors;
+}
+
+void flash_unlock_sector(flash_info_t * info, unsigned int sector)
+{
+	volatile u16 *addr = (volatile u16 *) (info->start[sector]);
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	*addr = CMD_SECTOR_UNLOCK;
+}
+
+
+ulong flash_init (void)
+{
+	int i, j, k;
+	unsigned int flash_nb_blocks, sector;
+	unsigned int start_address;
+	OrgDef *pOrgDef;
+
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_identification (&flash_info[i]);
+
+		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614 & FLASH_TYPEMASK)) {
+
+			pOrgDef = OrgAT49BV16x4;
+			flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614A & FLASH_TYPEMASK)){	/* AT49BV1614A Flash */
+
+			pOrgDef = OrgAT49BV16x4A;
+			flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			pOrgDef = OrgAT49BV6416;
+			flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef);
+		} else {
+			flash_nb_blocks = 0;
+			pOrgDef = OrgAT49BV16x4;
+		}
+
+		flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks);
+		memset (flash_info[i].protect, 0, flash_info[i].sector_count);
+
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+
+		sector = 0;
+		start_address = flashbase;
+		flash_info[i].size = 0;
+
+		for (j = 0; j < flash_nb_blocks; j++) {
+			for (k = 0; k < pOrgDef[j].sector_number; k++) {
+				flash_info[i].start[sector++] = start_address;
+				start_address += pOrgDef[j].sector_size;
+				flash_info[i].size += pOrgDef[j].sector_size;
+			}
+		}
+
+		size += flash_info[i].size;
+
+		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			/* Unlock all sectors at reset */
+			for (j=0; j<flash_info[i].sector_count; j++){
+				flash_unlock_sector(&flash_info[i], j);
+			}
+		}
+	}
+
+	/* Protect binary boot image */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + CFG_BOOT_SIZE - 1, &flash_info[0]);
+
+	/* Protect environment variables */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	/* Protect U-Boot gzipped image */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_U_BOOT_BASE,
+		       CFG_U_BOOT_BASE + CFG_U_BOOT_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (ATM_MANUFACT & FLASH_VENDMASK):
+		printf ("Atmel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (ATM_ID_BV1614 & FLASH_TYPEMASK):
+		printf ("AT49BV1614 (16Mbit)\n");
+		break;
+	case (ATM_ID_BV1614A & FLASH_TYPEMASK):
+		printf ("AT49BV1614A (16Mbit)\n");
+		break;
+	case (ATM_ID_BV6416 & FLASH_TYPEMASK):
+		printf ("AT49BV6416 (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		return;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(ATM_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr = (volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {			/* it was protected */
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t * info, ulong dest,
+								ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	};
+
+	if ((int) src & 1) {
+		printf ("unaligned source not supported\n");
+		return ERR_ALIGN;
+	};
+
+	wp = addr;
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) <<
+										   8);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	};
+
+	return ERR_OK;
+}
diff --git a/board/at91rm9200dk/u-boot.lds b/board/at91rm9200dk/u-boot.lds
new file mode 100755
index 0000000..f4fbf96
--- /dev/null
+++ b/board/at91rm9200dk/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/atc/Makefile b/board/atc/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/atc/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/atc/atc.c b/board/atc/atc.c
new file mode 100755
index 0000000..d2c6b3b
--- /dev/null
+++ b/board/atc/atc.c
@@ -0,0 +1,399 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <pci.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
+	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
+	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
+#if 1
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+#else
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+#endif
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
+	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD */
+	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
+#if 0
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+#else
+	/* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* PC15 */
+#endif
+	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+#if 0
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+#else
+	/* PD4  */ {   1,   1,   1,   0,   0,   0   }, /* PD4 */
+#endif
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
+    }
+};
+
+/*
+ * UPMB initialization table
+ */
+#define	_NOT_USED_	0xFFFFFFFF
+
+static const uint rtc_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
+	0xfaf2080, 0xfaf2080, 0xfff2400, 0x1fff6c05, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0xfffec00, 0xfffac00, 0xfff2d00, 0xfef2800,
+	0xfaf2080, 0xfaf2080, 0xfaf2400, 0x1fbf6c05, /* last */
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	printf ("Board: ATC\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+			  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+int misc_init_r(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint));
+	memctl->memc_mamr = MxMR_RLFx_6X | MxMR_WLFx_6X | MxMR_OP_NORM;
+
+	return (0);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	ulong size8, size9;
+#endif
+	long psize;
+
+	psize = 8 * 1024 * 1024;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+			  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+			  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+				  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+
+#endif	/* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/board/atc/config.mk b/board/atc/config.mk
new file mode 100755
index 0000000..eee7a60
--- /dev/null
+++ b/board/atc/config.mk
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# ATC boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_atc.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+
+TEXT_BASE := 0xFF000000
+
+# RAM version
+#TEXT_BASE := 0x100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/atc/flash.c b/board/atc/flash.c
new file mode 100755
index 0000000..2ab60e8
--- /dev/null
+++ b/board/atc/flash.c
@@ -0,0 +1,663 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+#if 0
+		ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
+#else
+		ulong flashbase = CFG_FLASH_BASE;
+#endif
+
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+			i, flash_info[i].size);
+		}
+
+		size += flash_info[i].size;
+	}
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = base + (i * sect_size);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base < info->start[0] + info->size)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
+
+	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F800C3B:
+		info->flash_id += FLASH_28F800C3B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F800B3B:
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F160C3B:
+		info->flash_id += FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F160B3B:
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F320C3B:
+		info->flash_id += FLASH_28F320C3B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F320B3B:
+		info->flash_id += FLASH_INTEL320B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F640C3B:
+		info->flash_id += FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F640B3B:
+		info->flash_id += FLASH_INTEL640B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		 left > 0 && res == 0;
+		 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+	*dest = (FPW)0x00400040;	/* program setup		*/
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00B000B0;	/* Suspend program	*/
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW)0x00100010))
+		res = 1;	/* write failed, time out error is close enough	*/
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+	return (res);
+}
diff --git a/board/atc/u-boot.lds b/board/atc/u-boot.lds
new file mode 100755
index 0000000..eee83d0
--- /dev/null
+++ b/board/atc/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/barco/Makefile b/board/barco/Makefile
new file mode 100755
index 0000000..d6bbf2f
--- /dev/null
+++ b/board/barco/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS =  $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/barco/README b/board/barco/README
new file mode 100755
index 0000000..d255a3d
--- /dev/null
+++ b/board/barco/README
@@ -0,0 +1,11 @@
+This port of U-Boot is tuned to run on a range of Barco Control Rooms
+Streaming Video Solutions, including:
+
+   - Streaming Video Card (SVC)
+   - Sample Compress Network (SCN)
+
+For more information, see http://www.barcocontrolrooms.com/
+
+Code and configuration are originally based on the Sandpoint board
+
+Marc Leeman <marc.leeman@barco.com>
diff --git a/board/barco/barco.c b/board/barco/barco.c
new file mode 100755
index 0000000..becbd0a
--- /dev/null
+++ b/board/barco/barco.c
@@ -0,0 +1,363 @@
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco.c,v $
+ * $Revision: 1.4 $
+ * $Author: mleeman $
+ * $Date: 2005/03/02 16:40:20 $
+ *
+ * Last ChangeLog Entry
+ * $Log: barco.c,v $
+ * Revision 1.4  2005/03/02 16:40:20  mleeman
+ * remove empty labels (3.4 complains)
+ *
+ * Revision 1.3  2005/02/21 12:48:58  mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.2  2005/02/21 10:10:53  mleeman
+ * - split up switch statement to a function call (Linux kernel coding guidelines)
+ *   ( feedback wd)
+ *
+ * Revision 1.1  2005/02/14 09:31:07  mleeman
+ * renaming of files
+ *
+ * Revision 1.1  2005/02/14 09:23:46  mleeman
+ * - moved 'barcohydra' directory to a more generic barco; since we will be
+ *   supporting and adding multiple boards
+ *
+ * Revision 1.3  2005/02/10 13:57:32  mleeman
+ * fixed flash corruption: I should exit from the moment I find the correct value
+ *
+ * Revision 1.2  2005/02/09 12:56:23  mleeman
+ * add generic header to track changes in sources
+ *
+ *
+ *******************************************************************/
+
+/*
+ * (C) Copyright 2004
+ * Marc Leeman <marc.leeman@barco.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <malloc.h>
+#include <command.h>
+
+#include "config.h"
+#include "barco_svc.h"
+
+#define TRY_WORKING  (3)
+#define BOOT_DEFAULT (2)
+#define BOOT_WORKING (1)
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Streaming Video Card for Hydra systems "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" Unity ##Test not implemented yet##\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size (CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg (MEAR1);
+	emear1 = mpc824x_mpc107_getreg (EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg (MEAR1, mear1);
+	mpc824x_mpc107_setreg (EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_barcohydra_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_barcohydra_config_table,
+#endif
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init (&hose);
+}
+
+int write_flash (char *addr, char value)
+{
+	char *adr = (char *)0xFF800000;
+	int cnt = 0;
+	char status,oldstatus;
+
+	*(adr+0x55) = 0xAA; udelay (1);
+	*(adr+0xAA) = 0x55; udelay (1);
+	*(adr+0x55) = 0xA0; udelay (1);
+	*addr = value;
+
+	status = *addr;
+	do {
+		oldstatus = status;
+		status = *addr;
+
+		if ((oldstatus & 0x40) == (status & 0x40)) {
+			return 4;
+		}
+		cnt++;
+		if (cnt > 10000) {
+			return 2;
+		}
+	} while ( (status & 0x20) == 0 );
+
+	oldstatus = *addr;
+	status = *addr;
+
+	if ((oldstatus & 0x40) == (status & 0x40)) {
+		return 0;
+	} else {
+		*(adr+0x55) = 0xF0;
+		return 1;
+	}
+}
+
+unsigned update_flash (unsigned char *buf)
+{
+	switch ((*buf) & 0x3) {
+	case TRY_WORKING:
+		printf ("found 3 and converted it to 2\n");
+		write_flash ((char *)buf, (*buf) & 0xFE);
+		*((unsigned char *)0xFF800000) = 0xF0;
+		udelay (100);
+		printf ("buf [%#010x] %#010x\n", buf, (*buf));
+		/* XXX - fall through??? */
+	case BOOT_WORKING :
+		return BOOT_WORKING;
+	}
+	return BOOT_DEFAULT;
+}
+
+unsigned scan_flash (void)
+{
+	char section[] =  "kernel";
+	int cfgFileLen  =  (CFG_FLASH_ERASE_SECTOR_LENGTH >> 1);
+	int sectionPtr  = 0;
+	int foundItem   = 0; /* 0: None, 1: section found, 2: "=" found */
+	int bufPtr;
+	unsigned char *buf;
+
+	buf = (unsigned char*)(CFG_FLASH_RANGE_BASE + CFG_FLASH_RANGE_SIZE \
+			- CFG_FLASH_ERASE_SECTOR_LENGTH);
+	for (bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr) {
+		if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) {
+			return BOOT_DEFAULT;
+		}
+		/* This is the scanning loop, we try to find a particular
+		 * quoted value
+		 */
+		switch (foundItem) {
+		case 0:
+			if ((section[sectionPtr] == 0)) {
+				++foundItem;
+			} else if (buf[bufPtr] == section[sectionPtr]) {
+				++sectionPtr;
+			} else {
+				sectionPtr = 0;
+			}
+			break;
+		case 1:
+			++foundItem;
+			break;
+		case 2:
+			++foundItem;
+			break;
+		case 3:
+		default:
+			return update_flash (&buf[bufPtr - 1]);
+		}
+	}
+
+	printf ("Failed to read %s\n",section);
+	return BOOT_DEFAULT;
+}
+
+TSBootInfo* find_boot_info (void)
+{
+	unsigned bootimage = scan_flash ();
+	TSBootInfo* info = (TSBootInfo*)malloc (sizeof(TSBootInfo));
+
+	switch (bootimage) {
+	case TRY_WORKING:
+		info->address = CFG_WORKING_KERNEL_ADDRESS;
+		break;
+	case BOOT_WORKING :
+		info->address = CFG_WORKING_KERNEL_ADDRESS;
+		break;
+	case BOOT_DEFAULT:
+	default:
+		info->address= CFG_DEFAULT_KERNEL_ADDRESS;
+
+	}
+	info->size = *((unsigned int *)(info->address ));
+
+	return info;
+}
+
+void barcobcd_boot (void)
+{
+	TSBootInfo* start;
+	char *bootm_args[2];
+	char *buf;
+	int cnt;
+	extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
+
+	buf = (char *)(0x00800000);
+	/* make certain there are enough chars to print the command line here!
+	 */
+	bootm_args[0] = (char *)malloc (16*sizeof(char));
+	bootm_args[1] = (char *)malloc (16*sizeof(char));
+
+	start = find_boot_info ();
+
+	printf ("Booting kernel at address %#10x with size %#10x\n",
+			start->address, start->size);
+
+	/* give length of the kernel image to bootm */
+	sprintf (bootm_args[0],"%x",start->size);
+	/* give address of the kernel image to bootm */
+	sprintf (bootm_args[1],"%x",buf);
+
+	printf ("flash address: %#10x\n",start->address+8);
+	printf ("buf address: %#10x\n",buf);
+
+	/* aha, we reserve 8 bytes here... */
+	for (cnt = 0; cnt < start->size ; cnt++) {
+		buf[cnt] = ((char *)start->address)[cnt+8];
+	}
+
+	/* initialise RAM memory */
+	*((unsigned int *)0xFEC00000) = 0x00141A98;
+	do_bootm (NULL,0,2,bootm_args);
+}
+
+int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+#if 0
+	if (argc > 1) {
+		printf ("Usage:\n (%d) %s\n", argc, cmdtp->usage);
+		return 1;
+	}
+#endif
+	barcobcd_boot ();
+
+	return 0;
+}
+
+/* Currently, boot_working and boot_default are the same command. This is
+ * left in here to see what we'll do in the future */
+
+U_BOOT_CMD (
+		try_working, 1, 1, barcobcd_boot_image,
+		" try_working - check flash value and boot the appropriate image\n",
+		"\n"
+	  );
+
+U_BOOT_CMD (
+		boot_working, 1, 1, barcobcd_boot_image,
+		" boot_working - check flash value and boot the appropriate image\n",
+		"\n"
+	  );
+
+U_BOOT_CMD (
+		boot_default, 1, 1, barcobcd_boot_image,
+		" boot_default - check flash value and boot the appropriate image\n",
+		"\n"
+	  );
+/*
+ * We are not using serial communication, so just provide empty functions
+ */
+int serial_init (void)
+{
+	return 0;
+}
+void serial_setbrg (void)
+{
+	return;
+}
+void serial_putc (const char c)
+{
+	return;
+}
+void serial_puts (const char *c)
+{
+	return;
+}
+void serial_addr (unsigned int i)
+{
+	return;
+}
+int serial_getc (void)
+{
+	return 0;
+}
+int serial_tstc (void)
+{
+	return 0;
+}
+
+unsigned long post_word_load (void)
+{
+	return 0l;
+}
+void post_word_store (unsigned long val)
+{
+	return;
+}
diff --git a/board/barco/barco_svc.h b/board/barco/barco_svc.h
new file mode 100755
index 0000000..088f61e
--- /dev/null
+++ b/board/barco/barco_svc.h
@@ -0,0 +1,68 @@
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco_svc.h,v $
+ * $Revision: 1.2 $
+ * $Author: mleeman $
+ * $Date: 2005/02/21 12:48:58 $
+ *
+ * Last ChangeLog Entry
+ * $Log: barco_svc.h,v $
+ * Revision 1.2  2005/02/21 12:48:58  mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.1  2005/02/14 09:31:07  mleeman
+ * renaming of files
+ *
+ * Revision 1.1  2005/02/14 09:23:46  mleeman
+ * - moved 'barcohydra' directory to a more generic barco; since we will be
+ *   supporting and adding multiple boards
+ *
+ * Revision 1.1  2005/02/08 15:40:19  mleeman
+ * modified and added platform files
+ *
+ * Revision 1.2  2005/01/25 08:05:04  mleeman
+ * more cleanup of the code
+ *
+ * Revision 1.1  2004/07/20 08:49:55  mleeman
+ * Working version of the default and nfs kernel booting.
+ *
+ *
+ *******************************************************************/
+
+#ifndef _LOCAL_BARCOHYDRA_H_
+#define _LOCAL_BARCOHYDRA_H_
+
+#include <flash.h>
+#include <asm/io.h>
+
+/* Defines for the barcohydra board */
+#ifndef CFG_FLASH_ERASE_SECTOR_LENGTH
+#define CFG_FLASH_ERASE_SECTOR_LENGTH (0x10000)
+#endif
+
+#ifndef CFG_DEFAULT_KERNEL_ADDRESS
+#define CFG_DEFAULT_KERNEL_ADDRESS (CFG_FLASH_BASE + 0x30000)
+#endif
+
+#ifndef CFG_WORKING_KERNEL_ADDRESS
+#define CFG_WORKING_KERNEL_ADDRESS (0xFFE00000)
+#endif
+
+
+typedef struct SBootInfo {
+	unsigned int address;
+	unsigned int size;
+	unsigned char state;
+}TSBootInfo;
+
+/* barcohydra.c */
+int checkboard(void);
+long int initdram(int board_type);
+void pci_init_board(void);
+void check_flash(void);
+int write_flash(char *addr, char value);
+TSBootInfo* find_boot_info(void);
+void final_boot(void);
+#endif
diff --git a/board/barco/config.mk b/board/barco/config.mk
new file mode 100755
index 0000000..f950c07
--- /dev/null
+++ b/board/barco/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Barco Hydra/SCN boards
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/barco/early_init.S b/board/barco/early_init.S
new file mode 100755
index 0000000..07dafb7
--- /dev/null
+++ b/board/barco/early_init.S
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2001
+ * Thomas Koeller, tkoeller@gmx.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASSEMBLY__
+#define __ASSEMBLY__	1
+#endif
+
+#include <config.h>
+#include <asm/processor.h>
+#include <mpc824x.h>
+#include <ppc_asm.tmpl>
+
+#if defined(USE_DINK32)
+  /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
+  #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+#else
+  #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
+#endif
+
+	.text
+
+	/* Values to program into memory controller registers */
+tbl:	.long	MCCR1, MCCR1VAL
+	.long	MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR3
+	.long	(((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CFG_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	MCCR4
+	.long	(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CFG_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
+		(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	MSAR1
+	.long	(((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR1
+	.long	(((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MSAR2
+	.long	(((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR2
+	.long	(((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR1
+	.long	(((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR1
+	.long	(((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR2
+	.long	(((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR2
+	.long	(((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	0
+
+
+	/*
+	 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
+	 * must be done in assembly, since we have no stack at this point.
+	 */
+	.global	early_init_f
+early_init_f:
+	mflr	r10
+
+	/* basic memory controller configuration */
+	lis	r3, CONFIG_ADDR_HIGH
+	lis	r4, CONFIG_DATA_HIGH
+	bl	lab
+lab:	mflr	r5
+	lwzu	r0, tbl - lab(r5)
+loop:	lwz	r1, 4(r5)
+	stwbrx	r0, 0, r3
+	eieio
+	stwbrx	r1, 0, r4
+	eieio
+	lwzu	r0, 8(r5)
+	cmpli	cr0, 0, r0, 0
+	bne	cr0, loop
+
+	/* set bank enable bits */
+	lis	r0, MBER@h
+	ori	r0, 0, MBER@l
+	li	r1, CFG_BANK_ENABLE
+	stwbrx	r0, 0, r3
+	eieio
+	stb	r1, 0(r4)
+	eieio
+
+	/* delay loop */
+	lis	r0, 0x0003
+	mtctr   r0
+delay:	bdnz	delay
+
+	/* enable memory controller */
+	lis	r0, MCCR1@h
+	ori	r0, 0, MCCR1@l
+	stwbrx	r0, 0, r3
+	eieio
+	lwbrx	r0, 0, r4
+	oris	r0, 0, MCCR1_MEMGO@h
+	stwbrx	r0, 0, r4
+	eieio
+
+	/* set up stack pointer */
+	lis	r1, CFG_INIT_SP_OFFSET@h
+	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+
+	mtlr	r10
+	blr
diff --git a/board/barco/flash.c b/board/barco/flash.c
new file mode 100755
index 0000000..6cb19b7
--- /dev/null
+++ b/board/barco/flash.c
@@ -0,0 +1,611 @@
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/flash.c,v $
+ * $Revision: 1.3 $
+ * $Author: mleeman $
+ * $Date: 2005/02/21 12:48:58 $
+ *
+ * Last ChangeLog Entry
+ * $Log: flash.c,v $
+ * Revision 1.3  2005/02/21 12:48:58  mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.2  2005/02/21 11:04:04  mleeman
+ * remove dead code and Coding style (feedback wd)
+ *
+ * Revision 1.1  2005/02/14 09:23:46  mleeman
+ * - moved 'barcohydra' directory to a more generic barco; since we will be
+ *   supporting and adding multiple boards
+ *
+ * Revision 1.2  2005/02/09 12:56:23  mleeman
+ * add generic header to track changes in sources
+ *
+ *
+ *******************************************************************/
+
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <flash.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR  (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0		(0xAAA)
+#define ADDR1		(0x555)
+#define ADDR3		(0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const));
+
+typedef struct{
+  FLASH_WORD_SIZE extval;
+  unsigned short intval;
+} map_entry;
+
+static unsigned long flash_id(unsigned char mfct, unsigned char chip)
+{
+	static const map_entry mfct_map[] = {
+		{(FLASH_WORD_SIZE) AMD_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+		{(FLASH_WORD_SIZE) FUJ_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+		{(FLASH_WORD_SIZE) STM_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+		{(FLASH_WORD_SIZE) MT_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+	};
+
+	static const map_entry chip_map[] = {
+		{AMD_ID_F040B,	FLASH_AM040},
+		{AMD_ID_F033C,	FLASH_AM033},
+		{AMD_ID_F065D,	FLASH_AM065},
+		{ATM_ID_LV040,	FLASH_AT040},
+		{(FLASH_WORD_SIZE) STM_ID_x800AB,	FLASH_STM800AB}
+	};
+
+	const map_entry *p;
+	unsigned long result = FLASH_UNKNOWN;
+
+	/* find chip id */
+	for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++){
+		if(p->extval == chip){
+			result = FLASH_VENDMASK | p->intval;
+			break;
+		}
+	}
+
+	/* find vendor id */
+	for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++){
+		if(p->extval == mfct){
+			result &= ~FLASH_VENDMASK;
+			result |= (unsigned long) p->intval << 16;
+			break;
+		}
+	}
+
+	return result;
+}
+
+
+unsigned long flash_init(void)
+{
+	unsigned long i;
+	unsigned char j;
+	static const ulong flash_banks[] = CFG_FLASH_BANKS;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++){
+		flash_info_t * const pflinfo = &flash_info[i];
+		pflinfo->flash_id = FLASH_UNKNOWN;
+		pflinfo->size = 0;
+		pflinfo->sector_count = 0;
+	}
+
+	/* Enable writes to Hydra/Argus flash */
+	{
+		register unsigned int temp;
+		CONFIG_READ_WORD(PICR1,temp);
+		temp |= PICR1_FLASH_WR_EN;
+		CONFIG_WRITE_WORD(PICR1,temp);
+	}
+
+	for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++){
+		flash_info_t * const pflinfo = &flash_info[i];
+		const unsigned long base_address = flash_banks[i];
+		volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address;
+
+		/* write autoselect sequence */
+		flash[0x5555] = 0xaa;
+		flash[0x2aaa] = 0x55;
+		flash[0x5555] = 0x90;
+		__asm__ __volatile__("sync");
+
+		pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]);
+
+		switch(pflinfo->flash_id & FLASH_TYPEMASK){
+			case FLASH_AM033:
+				pflinfo->size = 0x00200000;
+				pflinfo->sector_count = 64;
+				for(j = 0; j < 64; j++){
+					pflinfo->start[j] = base_address + 0x00010000 * j;
+					pflinfo->protect[j] = flash[(j << 16) | 0x2];
+				}
+				break;
+			case FLASH_AM065:
+				pflinfo->size = 0x00800000;
+				pflinfo->sector_count =128;
+				for(j = 0; j < 128; j++){
+					pflinfo->start[j] = base_address + 0x00010000 * j;
+					pflinfo->protect[j] = flash[(j << 16) | 0x2];
+				}
+				break;
+			case FLASH_AT040:
+				pflinfo->size = 0x00080000;
+				pflinfo->sector_count = 2;
+				pflinfo->start[0] = base_address ;
+				pflinfo->start[1] = base_address + 0x00004000;
+				pflinfo->protect[0] = ((flash[0x02] & 0X01)==0) ? 0X02 : 0X01;
+				pflinfo->protect[1] = 0X02;
+				break;
+			case FLASH_AM040:
+				pflinfo->size = 0x00080000;
+				pflinfo->sector_count = 8;
+				for(j = 0; j < 8; j++){
+					pflinfo->start[j] = base_address + 0x00010000 * j;
+					pflinfo->protect[j] = flash[(j << 16) | 0x2];
+				}
+				break;
+			case FLASH_STM800AB:
+				pflinfo->size = 0x00100000;
+				pflinfo->sector_count = 19;
+				pflinfo->start[0] = base_address;
+				pflinfo->start[1] = base_address + 0x4000;
+				pflinfo->start[2] = base_address + 0x6000;
+				pflinfo->start[3] = base_address + 0x8000;
+				for(j = 1; j < 16; j++){
+					pflinfo->start[j+3] = base_address + 0x00010000 * j;
+				}
+				break;
+		}
+		/* Protect monitor and environment sectors */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		flash_protect(FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+		flash_protect(FLAG_PROTECT_SET,
+				CFG_ENV_ADDR,
+				CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+				&flash_info[0]);
+#endif
+
+		/* reset device to read mode */
+		flash[0x0000] = 0xf0;
+		__asm__ __volatile__("sync");
+	}
+
+	return flash_info[0].size + flash_info[1].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	static const char unk[] = "Unknown";
+	const char *mfct = unk, *type = unk;
+	unsigned int i;
+
+	if(info->flash_id != FLASH_UNKNOWN){
+		switch(info->flash_id & FLASH_VENDMASK){
+			case FLASH_MAN_ATM:
+				mfct = "Atmel";
+				break;
+			case FLASH_MAN_AMD:
+				mfct = "AMD";
+				break;
+			case FLASH_MAN_FUJ:
+				mfct = "FUJITSU";
+				break;
+			case FLASH_MAN_STM:
+				mfct = "STM";
+				break;
+			case FLASH_MAN_SST:
+				mfct = "SST";
+				break;
+			case FLASH_MAN_BM:
+				mfct = "Bright Microelectonics";
+				break;
+			case FLASH_MAN_INTEL:
+				mfct = "Intel";
+				break;
+		}
+
+		switch(info->flash_id & FLASH_TYPEMASK){
+			case FLASH_AT040:
+				type = "AT49LV040 (512K * 8, uniform sector size)";
+				break;
+			case FLASH_AM033:
+				type = "AM29F033C (4 Mbit * 8, uniform sector size)";
+				break;
+			case FLASH_AM040:
+				type = "AM29F040B (512K * 8, uniform sector size)";
+				break;
+			case FLASH_AM065:
+				type = "AM29F0465D ( 8 MBit * 8, uniform sector size) or part of AM29F652D( 16 MB)";
+				break;
+			case FLASH_AM400B:
+				type = "AM29LV400B (4 Mbit, bottom boot sect)";
+				break;
+			case FLASH_AM400T:
+				type = "AM29LV400T (4 Mbit, top boot sector)";
+				break;
+			case FLASH_AM800B:
+				type = "AM29LV800B (8 Mbit, bottom boot sect)";
+				break;
+			case FLASH_AM800T:
+				type = "AM29LV800T (8 Mbit, top boot sector)";
+				break;
+			case FLASH_AM160T:
+				type = "AM29LV160T (16 Mbit, top boot sector)";
+				break;
+			case FLASH_AM320B:
+				type = "AM29LV320B (32 Mbit, bottom boot sect)";
+				break;
+			case FLASH_AM320T:
+				type = "AM29LV320T (32 Mbit, top boot sector)";
+				break;
+			case FLASH_STM800AB:
+				type = "M29W800AB (8 Mbit, bottom boot sect)";
+				break;
+			case FLASH_SST800A:
+				type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+				break;
+			case FLASH_SST160A:
+				type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+				break;
+		}
+	}
+
+	printf(
+			"\n  Brand: %s Type: %s\n"
+			"  Size: %lu KB in %d Sectors\n",
+			mfct,
+			type,
+			info->size >> 10,
+			info->sector_count
+	      );
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; i++){
+		unsigned long size;
+		unsigned int erased;
+		unsigned long * flash = (unsigned long *) info->start[i];
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size =
+			(i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+			(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for(
+				flash = (unsigned long *) info->start[i], erased = 1;
+				(flash != (unsigned long *) info->start[i] + size) && erased;
+				flash++
+		   ){
+			erased = *flash == ~0x0UL;
+		}
+
+		printf(
+				"%s %08lX %s %s",
+				(i % 5) ? "" : "\n   ",
+				info->start[i],
+				erased ? "E" : " ",
+				info->protect[i] ? "RO" : "  "
+		      );
+	}
+
+	puts("\n");
+	return;
+}
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned char sh8b;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+			(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
+		sh8b = 3;
+	}
+	else{
+		sh8b = 0;
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+						(info->start[sect] - info->start[0]) << sh8b));
+			if (info->flash_id & FLASH_MAN_SST){
+				addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+				addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+				udelay(30000);  /* wait 30 ms */
+			}
+			else
+				addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag){
+		enable_interrupts();
+	}
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0){
+		goto DONE;
+	}
+
+	start = get_timer (0);
+	last  = start;
+	addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+				(info->start[l_sect] - info->start[0]) << sh8b));
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;  /* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);   /* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+	unsigned char sh8b;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
+		sh8b = 3;
+	}
+	else{
+		sh8b = 0;
+	}
+
+	dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) +
+			info->start[0]);
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++){
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
+
+		dest2[i << sh8b] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag){
+			enable_interrupts();
+		}
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
+				(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*----------------------------------------------------------------------- */
diff --git a/board/barco/speed.h b/board/barco/speed.h
new file mode 100755
index 0000000..46860e8
--- /dev/null
+++ b/board/barco/speed.h
@@ -0,0 +1,78 @@
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/speed.h,v $
+ * $Revision: 1.2 $
+ * $Author: mleeman $
+ * $Date: 2005/02/21 12:48:58 $
+ *
+ * Last ChangeLog Entry
+ * $Log: speed.h,v $
+ * Revision 1.2  2005/02/21 12:48:58  mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.1  2005/02/14 09:23:46  mleeman
+ * - moved 'barcohydra' directory to a more generic barco; since we will be
+ *   supporting and adding multiple boards
+ *
+ * Revision 1.2  2005/02/09 12:56:23  mleeman
+ * add generic header to track changes in sources
+ *
+ *
+ *******************************************************************/
+
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK	      		CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */
diff --git a/board/barco/u-boot.lds b/board/barco/u-boot.lds
new file mode 100755
index 0000000..7bf8531
--- /dev/null
+++ b/board/barco/u-boot.lds
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/bmw/Makefile b/board/bmw/Makefile
new file mode 100755
index 0000000..621640b
--- /dev/null
+++ b/board/bmw/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2002
+# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ns16550.o serial.o m48t59y.o
+
+SOBJS	= early_init.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/bmw/README b/board/bmw/README
new file mode 100755
index 0000000..70bc813
--- /dev/null
+++ b/board/bmw/README
@@ -0,0 +1,331 @@
+Broadcom 95xx BMW CPCI Platform
+
+Overview
+=========
+BMW is an MPC8245 system controller featuring:
+* 3U CPCI Form Factor
+* BCM5703 Gigabit Ethernet
+* M48T59Y NVRAM
+* 16MB DOC
+* DIP Socket for Socketed DOC up to 1GB
+* 64MB SDRAM
+* LCD Display
+* Configurable Jumper options for 66,85, and 100Mhz memory bus
+
+
+BMW System Address Map
+======================
+BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual
+(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found
+onboard the processor module are listed briefly below:
+
+0x00000000 - 0x40000000 - 64MB SDRAM SIMM
+			  (Unregistered PC-100 SDRAM DIMM Module)
+
+0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000
+			  TSOP 16MB (MD2211-D16-V3)
+
+0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000
+			  DIP32 (Socketed 16MB - 1GB ) *
+			  NOTE: this is not populated on all systems.
+
+0x7c000000 - 0x7c000000 - Reset Register
+			  (Write 0 to reset)
+
+0x7c000001 - 0x7c000001 - System LED
+			  (Clear Bit 7 to turn on, set to shut off)
+
+0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3
+			  (Clear bit 7 to reset, set to assert IRQ3)
+
+0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register
+			  (Clear bit 7 to make R/W, set to make R/O)
+
+0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character
+			  5x7 Dot Matrix Alphanumeric Display
+			  (Each byte sets the appropriate character)
+
+0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC
+			  NVRAM Memory Region
+
+0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC
+			  Realtime Clock Registers
+
+0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom
+			  (AMD AM29F040, ST 29W040B)
+
+0xFFF00100 -              System Reset Vector
+
+
+IO/MMU (BAT) Configuration
+======================
+The following Block-Address-Translation (BAT) configuration
+is recommended to access all I/O devices.
+
+#define CFG_IBAT0L  (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+
+Interrupt Mappings
+======================
+BMW uses MPC8245 discrete mode interrupts. With the following
+hardwired mappings:
+
+BCM5701 10/100/1000 Ethernet 		IRQ1
+CompactPCI Interrupt A			IRQ2
+RTC/Watchdog Interrupt			IRQ3
+Internal NS16552 UART			IRQ4
+
+
+Jumper Settings
+======================
+
+BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus.
+A jumper (X) is a 0 bit.
+
+Hence 66= 10110
+      85= 11000
+     100= 10000
+
+Jumper Settings for various Speeds
+=======================
+J1 J2 J3 J4 J5
+    X        X    66Mhz
+=======================
+J1 J2 J3 J4 J5
+       X  X  X    85Mhz
+=======================
+J1 J2 J3 J4 J5
+    X  X  X  X   100Mhz
+=======================
+
+Obviously, 100Mhz memory bus is recommended for optimum performance.
+
+
+U-Boot
+===============
+Broadcom BMW board is supported under config_BWM option.
+Supported features:
+
+- NVRAM setenv/getenv (used by Linux Kernel for configuration variables)
+- BCM570x TFTP file transfer support
+- LCD Display Support
+- DOC Support - (underway)
+
+
+U-Boot 1.2.0 (Aug  6 2002 - 17:44:48)
+
+CPU:   MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
+Built: Aug  6 2002 at 17:44:37
+Local Bus at 66 MHz
+DRAM:  64 MB
+FLASH: 4095 MB
+In:    serial
+Out:   serial
+Err:   serial
+DOC:   No DiskOnChip found
+Hit any key to stop autoboot:  0
+=>printenv
+bootdelay=5
+baudrate=9600
+clocks_in_mhz=1
+hostname=switch-2
+bootcmd=tftp 100000 vmlinux.img;bootm
+gateway=10.16.64.1
+ethaddr=00:00:10:18:10:10
+nfsroot=172.16.40.111:/boot/root-fs
+filesize=5ec8c
+netmask=255.255.240.0
+ipaddr=172.16.40.114
+serverip=172.16.40.111
+root=/dev/nfs
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 315/8172 bytes
+=>boot
+
+
+DevTools
+========
+ELDK
+	DENX Embedded Linux Development Kit
+
+ROM Emulator
+	Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time)
+	Grammar Engine PL32E 32Pin PLCC Emulation cables
+	Grammar Engine 3VA8CON (3Volt adapter with Short cables)
+	Grammar Engine FPNET PromICE Ethernet Adapters
+
+ICE
+	WRS/EST VisionICE-II (PPC8240)
+
+
+=>reset
+
+
+U-Boot 1.2.0 (Aug  6 2002 - 17:44:48)
+
+CPU:   MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
+Built: Aug  6 2002 at 17:44:37
+Local Bus at 66 MHz
+DRAM:  64 MB
+FLASH: 4095 MB
+In:    serial
+Out:   serial
+Err:   serial
+DOC:   No DiskOnChip found
+Hit any key to stop autoboot:  0
+
+Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000
+BCM570x PCI Memory base address @0x80100000
+eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF
+eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010
+eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found
+eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON
+ARP broadcast 1
+TFTP from server 172.16.40.111; our IP address is 172.16.40.114
+Filename 'vmlinux.img'.
+Load address: 0x100000
+Loading: #################################################################
+	 ####################################T #############################
+	 ######################
+done
+Bytes transferred = 777199 (bdbef hex)
+
+eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline.
+## Booting image at 00100000 ...
+   Image Name:   vmlinux.bin.gz
+   Created:      2002-08-06   6:30:13 UTC
+   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
+   Data Size:    777135 Bytes = 758 kB = 0 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Verifying Checksum ... OK
+   Uncompressing Kernel Image ... OK
+Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb
+Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002
+CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000
+U-Boot Environment: 0xc01b08f0
+IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10>
+cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e
+NOTICE: mounting root file system via NFS
+IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111
+On node 0 totalpages: 16384
+zone(0): 16384 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111
+root_dev_setup:/dev/nfs or 00:ff
+time_init: decrementer frequency = 16.501145 MHz
+Calibrating delay loop... 175.71 BogoMIPS
+Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem)
+Dentry cache hash table entries: 8192 (order: 4, 65536 bytes)
+Inode cache hash table entries: 4096 (order: 3, 32768 bytes)
+Mount-cache hash table entries: 1024 (order: 1, 8192 bytes)
+Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
+POSIX conformance testing by UNIFIX
+PCI: Probing PCI hardware
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Initializing RT netlink socket
+Starting kswapd
+devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au)
+devfs: devfs_debug: 0x0
+devfs: boot_options: 0x1
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+pty: 256 Unix98 ptys configured
+Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
+Testing ttyS0 (0xf7f51500, 0xf7f51500)...
+Testing ttyS1 (0xfc004600, 0xfc004600)...
+ttyS00 at 0xf7f51500 (irq = 24) is a ST16650
+ttyS01 at 0xfc004600 (irq = 25) is a 16550A
+Real Time Clock Driver v1.10e
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
+loop: loaded (max 8 devices)
+TFFS 5.1.1 Flash disk driver for DiskOnChip
+Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd.
+DOC device(s) found: 1
+fl_init: registered device at major: 100
+fl_geninit: registered device at major: 100
+Partition check:
+ fla: p1
+partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB
+partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB
+partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
+partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
+Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02)
+eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010
+eth0: Broadcom BCM5701 Integrated Copper transceiver found
+eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON
+bond0 registered without MII link monitoring, in bonding mode.
+rtc: unable to get misc minor
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP, IGMP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 4096 bind 4096)
+bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex
+IP-Config: Gateway not on directly connected network.
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+802.1Q VLAN Support v1.7 Ben Greear <greearb@candelatech.com>
+All bugs added by David S. Miller <davem@redhat.com>
+Looking up port of RPC 100003/2 on 172.16.40.111
+Looking up port of RPC 100005/1 on 172.16.40.111
+VFS: Mounted root (nfs filesystem).
+Mounted devfs on /dev
+Freeing unused kernel memory: 100k init
+INIT: version 2.78 booting
+Mounting local filesystems...
+not mounted anything
+Setting up symlinks in /dev...done.
+Setting up extra devices in /dev...done.
+Starting devfsd...Started device management daemon for /dev
+INIT: Entering runlevel: 2
+Starting internet superserver: inetd.
+
+
+Welcome to Linux/PPC
+MPC8245/BMW
+
+
+switch-2 login: root
+Password:
+PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0)
+Last login: Thu Nov 25 11:51:14 1920 on console
+
+
+Welcome to Linux/PPC
+MPC8245/BMW
+
+
+login[49]: ROOT LOGIN on `console'
+
+root@switch-2:~# cat /proc/cpuinfo
+cpu             : 82xx
+revision        : 16.20 (pvr 8081 1014)
+bogomips        : 175.71
+vendor          : Broadcom
+machine         : BMW/MPC8245
+root@switch-2:~#
diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c
new file mode 100755
index 0000000..485e050
--- /dev/null
+++ b/board/bmw/bmw.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2002
+ * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <malloc.h>
+#include <devices.h>
+#include <net.h>
+#include <version.h>
+#include <dtt.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <linux/mtd/doc2000.h>
+
+#include "bmw.h"
+#include "m48t59y.h"
+#include <pci.h>
+
+
+int checkboard(void)
+{
+    ulong busfreq  = get_bus_freq(0);
+    char  buf[32];
+
+    puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
+    printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+    /* printf("MPLD:  Revision %d\n", SYS_REVID_GET()); */
+    printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
+    return 0;
+}
+
+long int initdram(int board_type)
+{
+    return 64*1024*1024;
+}
+
+
+void
+get_tod(void)
+{
+    int year, month, day, hour, minute, second;
+
+    m48_tod_get(&year,
+		&month,
+		&day,
+		&hour,
+		&minute,
+		&second);
+
+    printf("  Current date/time: %d/%d/%d %d:%d:%d \n",
+	   month, day, year, hour, minute, second);
+
+}
+
+/*
+ * EPIC, PCI, and I/O devices.
+ * Initialize Mousse Platform, probe for PCI devices,
+ * Query configuration parameters if not set.
+ */
+int misc_init_f (void)
+{
+#if 0
+    m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */
+    printf("RTC:   M48T589 TOD/NVRAM (%d) bytes\n",
+	   TOD_NVRAM_SIZE);
+    get_tod();
+#endif
+
+    sys_led_msg("BOOT");
+    return 0;
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+struct pci_controller hose;
+
+void pci_init_board (void)
+{
+    pci_mpc824x_init(&hose);
+    /* pci_dev_init(0); */
+}
+
+/*
+ * Write characters to LCD display.
+ * Note that the bytes for the first character is the last address.
+ */
+void
+sys_led_msg(char* msg)
+{
+    LED_REG(0) = msg[3];
+    LED_REG(1) = msg[2];
+    LED_REG(2) = msg[1];
+    LED_REG(3) = msg[0];
+}
+
+/*
+ * Map onboard TSOP-16MB DOC FLASH chip.
+ */
+void doc_init (void)
+{
+    doc_probe(DOC_BASE_ADDR);
+}
+
+#define NV_ADDR	((volatile unsigned char *) CFG_ENV_ADDR)
+
+/* Read from NVRAM */
+void*
+nvram_read(void *dest, const long src, size_t count)
+{
+    int i;
+    volatile unsigned char* d = (unsigned char*)dest;
+    volatile unsigned char* s = (unsigned char*)src;
+
+    for( i = 0; i < count;i++)
+	d[i] = s[i];
+
+    return dest;
+}
+
+/* Write to NVRAM */
+void
+nvram_write(long dest, const void *src, size_t count)
+{
+    int i;
+    volatile unsigned char* d = (unsigned char*)dest;
+    volatile unsigned char* s = (unsigned char*)src;
+
+    SYS_TOD_UNPROTECT();
+
+    for( i = 0; i < count;i++)
+	d[i] = s[i];
+
+    SYS_TOD_PROTECT();
+}
diff --git a/board/bmw/bmw.h b/board/bmw/bmw.h
new file mode 100755
index 0000000..dd97569
--- /dev/null
+++ b/board/bmw/bmw.h
@@ -0,0 +1,86 @@
+/*
+ * BMW/MPC8245 Board definitions.
+ * For more info, see http://www.vooha.com/
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * James Dougherty (jfd@broadcom.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BMW_H
+#define __BMW_H
+
+/* System addresses */
+
+#define PCI_SPECIAL_BASE	0xfe000000
+#define PCI_SPECIAL_SIZE	0x01000000
+
+#define EUMBBAR_VAL		0x80500000	/* Location of EUMB region */
+#define EUMBSIZE		0x00100000	/* Size of EUMB region */
+
+/* Extended ROM space devices */
+#define DOC_BASE_ADDR           0xff000000      /* Onboard DOC TSOP 16MB */
+#define DOC2_BASE_ADDR          0x70000000      /* DIP32 socket -> 1GB */
+#define XROM_BASE_ADDR          0x7c000000      /* RCS2 (PAL / Satellite IO) */
+#define PLD_REG_BASE		XROM_BASE_ADDR
+#define LED_REG_BASE		(XROM_BASE_ADDR | 0x2000)
+#define TOD_BASE		(XROM_BASE_ADDR | 0x4000)
+#define LED_REG(x)              (*(volatile unsigned char *) \
+				  (LED_REG_BASE + (x)))
+#define XROM_DEV_SIZE		0x00006000
+
+#define ENET_DEV_BASE		0x80000000
+
+#define PLD_REG(off)		(*(volatile unsigned char *)\
+				  (PLD_REG_BASE + (off)))
+
+#define PLD_REVID_B1		0x7f	/* Fix me */
+#define PLD_REVID_B2		0x01	/* Fix me */
+
+#define SYS_HARD_RESET()	{ for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
+#define SYS_REVID_GET()		((int) PLD_REG(0) & 0x7f)
+#define SYS_LED_OFF()		(PLD_REG(1) |= 0x80)
+#define SYS_LED_ON()		(PLD_REG(1) &= ~0x80)
+#define SYS_WATCHDOG_IRQ3()	(PLD_REG(2) |= 0x80)
+#define SYS_WATCHDOG_RESET()	(PLD_REG(2) &= ~0x80)
+#define SYS_TOD_PROTECT()	(PLD_REG(3) |= 0x80)
+#define SYS_TOD_UNPROTECT()	(PLD_REG(3) &= ~0x80)
+
+#define	TOD_REG_BASE		(TOD_BASE | 0x1ff0)
+#define	TOD_NVRAM_BASE		TOD_BASE
+#define	TOD_NVRAM_SIZE		0x1ff0
+#define	TOD_NVRAM_LIMIT		(TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
+#define RTC(r)		        (TOD_BASE + r)
+
+/* Onboard BCM570x device */
+#define	PCI_ENET_IOADDR		0x80000000
+#define	PCI_ENET_MEMADDR	0x80000000
+
+
+#ifndef __ASSEMBLY__
+/* C Function prototypes */
+void sys_led_msg(char* msg);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __BMW_H */
diff --git a/board/bmw/config.mk b/board/bmw/config.mk
new file mode 100755
index 0000000..f991549
--- /dev/null
+++ b/board/bmw/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CU824 board
+#
+
+TEXT_BASE = 0xFFF00000
+# NOTE: The flags below affect how the BCM570x driver is compiled
+PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\
+		     -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256\
+		     -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S
new file mode 100755
index 0000000..e6400c3
--- /dev/null
+++ b/board/bmw/early_init.S
@@ -0,0 +1,1170 @@
+#include <ppc_asm.tmpl>
+#include <mpc824x.h>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */
+
+
+/*
+ * Initialize the MMU using BAT entries and hardwired TLB
+ * This obviates the need for any code in cpu_init_f which
+ * configures the BAT registers.
+*/
+#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */
+	.global	iommu_setup
+	/* Initialize IO/MMU mappings via BAT method Ch. 7,
+	 * PPC Programming Reference
+	 */
+iommu_setup:
+
+/* initialize the BAT registers (SPRs 528 - 543 */
+#define	mtibat0u(x)	mtspr	528,(x)			/* SPR 528 (IBAT0U) */
+#define mtibat0l(x)	mtspr	529,(x)			/* SPR 529 (IBAT0L) */
+#define mtibat1u(x)	mtspr	530,(x)			/* SPR 530 (IBAT1U) */
+#define mtibat1l(x)	mtspr	531,(x)			/* SPR 531 (IBAT1L) */
+#define mtibat2u(x)	mtspr	532,(x)			/* SPR 532 (IBAT2U) */
+#define mtibat2l(x)	mtspr	533,(x)			/* SPR 533 (IBAT2L) */
+#define mtibat3u(x)	mtspr	534,(x)			/* SPR 534 (IBAT3U) */
+#define mtibat3l(x)	mtspr	535,(x)			/* SPR 535 (IBAT3L) */
+#define mtdbat0u(x)	mtspr	536,(x)			/* SPR 536 (DBAT0U) */
+#define mtdbat0l(x)	mtspr	537,(x)			/* SPR 537 (DBAT0L) */
+#define mtdbat1u(x)	mtspr	538,(x)			/* SPR 538 (DBAT1U) */
+#define mtdbat1l(x)	mtspr	539,(x)			/* SPR 539 (DBAT1L) */
+#define mtdbat2u(x)	mtspr	540,(x)			/* SPR 540 (DBAT2U) */
+#define mtdbat2l(x)	mtspr	541,(x)			/* SPR 541 (DBAT2L) */
+#define mtdbat3u(x)	mtspr	542,(x)			/* SPR 542 (DBAT3U) */
+#define mtdbat3l(x)	mtspr	543,(x)			/* SPR 543 (DBAT3L) */
+
+
+/* PowerPC processors do not necessarily initialize the BAT
+   registers on power-up or reset.  So they are in an unknown
+   state.  Before programming the BATs for the first time, all
+   BAT registers MUST have their Vs and Vp bits cleared in the
+   upper BAT half in order to avoid possibly having 2 BATs
+   valid and mapping the same memory region.
+
+   The reason for this is that, even with address translation
+   disabled, multiple BAT hits for an address are treated as
+   programming errors and can cause unpredictable results.
+
+   It is up to the software to make sure it never has 2 IBAT
+   mappings or 2 DBAT mappings that are valid for the same
+   addresses.  It is not necessary to perform this code
+   sequence every time the BATs are programmed, only when
+   there is a possibility that there may be overlapping BAT
+   entries.
+
+   When programming the BATs in non-reset scenarios, even if
+   you are sure that your new mapping will not temporarily
+   create overlapping regions, it is still a wise idea to
+   invalidate a BAT entry by setting its upper BAT register to
+   all 0's before programming it.  This will avoid having a
+   BAT marked valid that is in an unknown or transient state
+*/
+
+	addis   r5,0,0x0000
+	mtibat0u(r5)
+	mtibat0l(r5)
+	mtibat1u(r5)
+	mtibat1l(r5)
+	mtibat2u(r5)
+	mtibat2l(r5)
+	mtibat3u(r5)
+	mtibat3l(r5)
+	mtdbat0u(r5)
+	mtdbat0l(r5)
+	mtdbat1u(r5)
+	mtdbat1l(r5)
+	mtdbat2u(r5)
+	mtdbat2l(r5)
+	mtdbat3u(r5)
+	mtdbat3l(r5)
+	isync
+
+/*
+ *  Set up I/D BAT0
+ */
+	lis     r4, CFG_DBAT0L@h
+	ori     r4, r4, CFG_DBAT0L@l
+	lis     r3, CFG_DBAT0U@h
+	ori     r3, r3, CFG_DBAT0U@l
+
+	mtdbat0l(r4)
+	isync
+	mtdbat0u(r3)
+	isync
+	sync
+
+	lis     r4, CFG_IBAT0L@h
+	ori     r4, r4, CFG_IBAT0L@l
+	lis     r3, CFG_IBAT0U@h
+	ori     r3, r3, CFG_IBAT0U@l
+
+	isync
+	mtibat0l(r4)
+	isync
+	mtibat0u(r3)
+	isync
+
+/*
+ *  Set up I/D BAT1
+ */
+	lis     r4, CFG_IBAT1L@h
+	ori     r4, r4, CFG_IBAT1L@l
+	lis     r3, CFG_IBAT1U@h
+	ori     r3, r3, CFG_IBAT1U@l
+
+	isync
+	mtibat1l(r4)
+	isync
+	mtibat1u(r3)
+	isync
+	mtdbat1l(r4)
+	isync
+	mtdbat1u(r3)
+	isync
+	sync
+
+/*
+ *  Set up I/D BAT2
+ */
+	lis     r4, CFG_IBAT2L@h
+	ori     r4, r4, CFG_IBAT2L@l
+	lis     r3, CFG_IBAT2U@h
+	ori     r3, r3, CFG_IBAT2U@l
+
+	isync
+	mtibat2l(r4)
+	isync
+	mtibat2u(r3)
+	isync
+	mtdbat2l(r4)
+	isync
+	mtdbat2u(r3)
+	isync
+	sync
+
+/*
+ *  Setup I/D BAT3
+ */
+	lis     r4, CFG_IBAT3L@h
+	ori     r4, r4, CFG_IBAT3L@l
+	lis     r3, CFG_IBAT3U@h
+	ori     r3, r3, CFG_IBAT3U@l
+
+	isync
+	mtibat3l(r4)
+	isync
+	mtibat3u(r3)
+	isync
+	mtdbat3l(r4)
+	isync
+	mtdbat3u(r3)
+	isync
+	sync
+
+
+/*
+ *  Invalidate all 64 TLB's
+ */
+	lis     r3, 0
+	mtctr   r3
+	lis     r5, 4
+
+tlblp:
+	tlbie   r3
+	sync
+	addi    r3, r3, 0x1000
+	cmplw   r3, r5
+	blt     tlblp
+
+	sync
+
+/*
+ *  Enable Data Translation
+ */
+	lis	r4, MEMORY_MGMT_MSR_BITS@h
+	ori	r4, r4, MEMORY_MGMT_MSR_BITS@l
+	mfmsr	r3
+	or	r3, r4, r3
+	mtmsr	r3
+	isync
+	sync
+
+	blr
+
+
+#ifdef USE_V2_INIT
+/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */
+/* Macro for hiadjust and lo */
+#define HIADJ(arg)	arg@ha
+#define HI(arg)		arg@h
+#define LO(arg)		arg@l
+
+#undef LOADPTR
+#define	LOADPTR(reg,const32) \
+	  addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32)
+
+.globl  early_init_f
+
+early_init_f:
+/* MPC8245/BMW CPCI System Init
+ * Jimmy Blair, Broadcom Corp, 2002.
+ */
+	mflr    r11
+	/* Zero-out registers */
+
+	addis	r0,r0,0
+	mtspr	SPRG0,r0
+	mtspr	SPRG1,r0
+	mtspr	SPRG2,r0
+	mtspr	SPRG3,r0
+
+	/* Set MPU/MSR to a known state. Turn on FP */
+
+	LOADPTR (r3, MSR_FP)
+	sync
+	mtmsr	r3
+	isync
+
+	/* Init the floating point control/status register */
+
+	mtfsfi	7,0x0
+	mtfsfi	6,0x0
+	mtfsfi	5,0x0
+	mtfsfi	4,0x0
+	mtfsfi	3,0x0
+	mtfsfi	2,0x0
+	mtfsfi	1,0x0
+	mtfsfi	0,0x0
+	isync
+
+	/* Set MPU/MSR to a known state. Turn off FP */
+
+#if 1	/* Turn off floating point (remove to keep FP on) */
+	andi.	r3, r3, 0
+	sync
+	mtmsr 	r3
+	isync
+#endif
+
+	/* Init the Segment registers */
+
+	andi.	r3, r3, 0
+	isync
+	mtsr	0,r3
+	isync
+	mtsr	1,r3
+	isync
+	mtsr	2,r3
+	isync
+	mtsr	3,r3
+	isync
+	mtsr	4,r3
+	isync
+	mtsr	5,r3
+	isync
+	mtsr	6,r3
+	isync
+	mtsr	7,r3
+	isync
+	mtsr	8,r3
+	isync
+	mtsr	9,r3
+	isync
+	mtsr	10,r3
+	isync
+	mtsr	11,r3
+	isync
+	mtsr	12,r3
+	isync
+	mtsr	13,r3
+	isync
+	mtsr	14,r3
+	isync
+	mtsr	15,r3
+	isync
+
+	/* Turn off data and instruction cache control bits */
+
+	mfspr	r3, HID0
+	isync
+	rlwinm	r4, r3, 0, 18, 15	/* r4 has ICE and DCE bits cleared */
+	sync
+	isync
+	mtspr	HID0, r4		/* HID0 = r4 */
+	isync
+
+	/* Get cpu type */
+
+	mfspr	r28, PVR
+	rlwinm	r28, r28, 16, 16, 31
+
+	/* invalidate the MPU's data/instruction caches */
+
+	lis	r3, 0x0
+	cmpli	0, 0, r28, CPU_TYPE_603
+	beq	cpuIs603
+	cmpli	0, 0, r28, CPU_TYPE_603E
+	beq	cpuIs603
+	cmpli	0, 0, r28, CPU_TYPE_603P
+	beq	cpuIs603
+	cmpli	0, 0, r28, CPU_TYPE_604R
+	bne	cpuNot604R
+
+cpuIs604R:
+	lis	r3, 0x0
+	mtspr	HID0, r3		/* disable the caches */
+	isync
+	ori	r4, r4, 0x0002		/* disable BTAC by setting bit 30 */
+
+cpuNot604R:
+	ori	r3, r3, (HID0_ICFI |HID0_DCI)
+
+cpuIs603:
+	ori	r3, r3, (HID0_ICE | HID0_DCE)
+	or	r4, r4, r3		/* set bits */
+	sync
+	isync
+	mtspr	HID0, r4		/* HID0 = r4 */
+	andc	r4, r4, r3		/* clear bits */
+	isync
+	cmpli	0, 0, r28, CPU_TYPE_604
+	beq	cpuIs604
+	cmpli	0, 0, r28, CPU_TYPE_604E
+	beq	cpuIs604
+	cmpli	0, 0, r28, CPU_TYPE_604R
+	beq	cpuIs604
+	mtspr	HID0, r4
+	isync
+
+#ifdef USER_I_CACHE_ENABLE
+	b	instCacheOn603
+#else
+	b	cacheEnableDone
+#endif
+
+cpuIs604:
+	LOADPTR (r5, 0x1000)		/* loop count, 0x1000 */
+	mtspr	CTR, r5
+loopDelay:
+	nop
+	bdnz	loopDelay
+	isync
+	mtspr	HID0, r4
+	isync
+
+	/* turn the Instruction cache ON for faster FLASH ROM boots */
+
+#ifdef USER_I_CACHE_ENABLE
+
+	ori	r4, r4, (HID0_ICE | HID0_ICFI)
+	isync				/* Synchronize for ICE enable */
+	b	writeReg4
+instCacheOn603:
+	ori	r4, r4, (HID0_ICE | HID0_ICFI)
+	rlwinm	r3, r4, 0, 21, 19	/* clear the ICFI bit */
+
+	/*
+	 * The setting of the instruction cache enable (ICE) bit must be
+	 * preceded by an isync instruction to prevent the cache from being
+	 * enabled or disabled while an instruction access is in progress.
+	 */
+	isync
+writeReg4:
+	mtspr	HID0, r4		/* Enable Instr Cache & Inval cache */
+	cmpli	0, 0, r28, CPU_TYPE_604
+	beq	cacheEnableDone
+	cmpli	0, 0, r28, CPU_TYPE_604E
+	beq	cacheEnableDone
+
+	mtspr	HID0, r3		/* using 2 consec instructions */
+					/* PPC603 recommendation */
+#endif
+cacheEnableDone:
+
+	/* Detect map A or B */
+
+	addis	r5,r0, HI(CHRP_REG_ADDR)
+	addis	r6,r0, HI(CHRP_REG_DATA)
+	LOADPTR (r7, KAHLUA_ID)		/* Kahlua PCI controller ID */
+	LOADPTR (r8, BMC_BASE)
+
+	stwbrx	r8,0,(r5)
+	lwbrx	r3,0,(r6)		/* Store read value to r3 */
+	cmp	0,0,r3,r7
+	beq	cr0, X4_KAHLUA_START
+
+	/* It's not an 8240, is it an 8245? */
+
+	LOADPTR (r7, KAHLUA2_ID)	/* Kahlua PCI controller ID */
+	cmp	0,0,r3,r7
+	beq	cr0, X4_KAHLUA_START
+
+	/* Save the PCI controller type in r7 */
+	mr	r7, r3
+
+	LOADPTR (r5, PREP_REG_ADDR)
+	LOADPTR (r6, PREP_REG_DATA)
+
+X4_KAHLUA_START:
+	/* MPC8245 changes begin here */
+	LOADPTR (r3, MPC107_PCI_CMD)	/* PCI command reg */
+	stwbrx	r3,0,r5
+	li	r4, 6			/* Command register value */
+	sthbrx	r4, 0, r6
+
+	LOADPTR (r3, MPC107_PCI_STAT)	/* PCI status reg */
+	stwbrx	r3,0,r5
+	li	r4, -1			/* Write-to-clear all bits */
+	li	r3, 2			/* PCI_STATUS is at +2 offset */
+	sthbrx	r4, r3, r6
+
+	/*-------PROC_INT1_ADR */
+
+	LOADPTR (r3, PROC_INT1_ADR)	/* Processor I/F Config 1 reg. */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xff141b98)
+	stwbrx	r4,0,r6
+
+	/*-------PROC_INT2_ADR */
+
+	LOADPTR (r3, PROC_INT2_ADR)	/* Processor I/F Config 2 reg. */
+	stwbrx	r3,0,r5
+	lis	r4, 0x2000		/* Flush PCI config writes */
+	stwbrx	r4,0,r6
+
+	LOADPTR (r9, KAHLUA2_ID)
+	cmpl	0, 0, r7, r9
+	bne     L1not8245
+
+	/* MIOCR1 -- turn on bit for DLL delay */
+
+	LOADPTR (r3, MIOCR1_ADR_X)
+	stwbrx	r3,0,r5
+	li      r4, 0x04
+	stb	r4, MIOCR1_SHIFT(r6)
+
+	/* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
+	/* SDRAM_CLK_DEL (0x77)*/
+
+	LOADPTR (r3, MIOCR2_ADR_X)
+	stwbrx	r3,0,r5
+	li      r4, 0x10
+	stb	r4, MIOCR2_SHIFT(r6)
+
+	/* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */
+
+	LOADPTR (r3, PMCR2_ADR_X)
+	stwbrx	r3,0,r5
+	li      r4, 0x20
+	stb	r4, PMCR2_SHIFT(r6)
+
+	/* Initialize EUMBBAR early since 8245 has internal UART in EUMB */
+
+	LOADPTR (r3, EUMBBAR)
+	stwbrx	r3,0,r5
+	LOADPTR (r4, CFG_EUMB_ADDR)
+	stwbrx	r4,0,r6
+
+L1not8245:
+
+	/* Toggle the DLL reset bit in AMBOR */
+
+	LOADPTR (r3, AMBOR)
+	stwbrx	r3,0,r5
+	lbz	r4, 0(r6)
+
+	andi.   r4, r4, 0xdf
+	stb	r4, 0(r6)		/* Clear DLL_RESET */
+	sync
+
+	ori     r4, r4, 0x20		/* Set DLL_RESET */
+	stb	r4, 0(r6)
+	sync
+
+	andi.   r4, r4, 0xdf
+	stb	r4, 0(r6)		/* Clear DLL_RESET */
+
+
+	/* Enable RCS2, use supplied timings */
+	LOADPTR (r3, ERCR1)
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x80408000)
+	stwbrx	r4,0,r6
+
+	/* Disable RCS3 parameters */
+	LOADPTR (r3, ERCR2)
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x00000000)
+	stwbrx	r4,0,r6
+
+	/* RCS3 at 0x70000000, 64KBytes */
+	LOADPTR (r3, ERCR2)
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x00000004)
+	stwbrx	r4,0,r6
+
+	/*-------MCCR1 */
+
+#ifdef INCLUDE_ECC
+#define MC_ECC				1
+#else /* INCLUDE_ECC */
+#define MC_ECC				0
+#endif /* INCLUDE_ECC */
+
+#define MC1_ROMNAL			8		/* 0-15 */
+#define MC1_ROMFAL			11		/* 0-31 */
+#define MC1_DBUS_SIZE			0		/* 0-3, read only */
+#define MC1_BURST			0		/* 0-1 */
+#define MC1_MEMGO			0		/* 0-1 */
+#define MC1_SREN			1		/* 0-1 */
+#define MC1_RAM_TYPE			0		/* 0-1 */
+#define MC1_PCKEN			MC_ECC		/* 0-1 */
+#define MC1_BANKBITS			0x5555		/* 2 bits/bank 7-0 */
+
+	LOADPTR (r3, MEM_CONT1_ADR)	/* Set MCCR1 (F0) */
+	stwbrx	r3,0,r5
+	LOADPTR(r4, \
+		MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \
+		MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \
+		MC1_MEMGO << 19 | MC1_SREN << 18 | \
+		MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 )
+	li	r3, MC1_BANKBITS
+	cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
+	bne     BankBitsAdd
+	cmpli   0, 0, r3, 0x5555
+	beq     K2BankBitsHack		/* On 8245, 5555 ==> 0 */
+BankBitsAdd:
+	ori	r4, r3, 0
+K2BankBitsHack:
+	stwbrx	r4, 0, r6
+
+	/*------- MCCR2 */
+
+#define MC2_TS_WAIT_TIMER		0		/* 0-7 */
+#define MC2_ASRISE			8		/* 0-15 */
+#define MC2_ASFALL			4		/* 0-15 */
+#define MC2_INLINE_PAR_NOT_ECC		0		/* 0-1 */
+#define MC2_WRITE_PARITY_CHK_EN		MC_ECC		/* 0-1 */
+#define MC2_INLRD_PARECC_CHK_EN		MC_ECC		/* 0-1 */
+#define MC2_ECC_EN			0		/* 0-1 */
+#define MC2_EDO				0		/* 0-1 */
+/*
+*  N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM.
+*  May need to be decreased for 100 MHz
+*/
+#define MC2_REFINT			0x3a5		/* 0-0x3fff */
+#define MC2_RSV_PG			0		/* 0-1 */
+#define MC2_RMW_PAR			MC_ECC		/* 0-1 */
+
+	LOADPTR (r3, MEM_CONT2_ADR)	/* Set MCCR2 (F4) */
+	stwbrx	r3,0,r5
+	LOADPTR(r4, \
+		MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \
+		MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \
+		MC2_WRITE_PARITY_CHK_EN << 19 | \
+		MC2_INLRD_PARECC_CHK_EN << 18 | \
+		MC2_ECC_EN << 17 | MC2_EDO << 16 | \
+		MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR)
+	cmpl	0, 0, r7, r9		/* Check for Kahlua2 */
+	bne     notK2
+	/* clear Kahlua2 reserved bits */
+	LOADPTR (r3, 0xfffcffff)
+	and	r4, r4, r3
+notK2:
+	stwbrx	r4,0,r6
+
+	/*------- MCCR3 */
+
+#define MC_BSTOPRE			0x079		/* 0-0x7ff */
+
+#define MC3_BSTOPRE_U			(MC_BSTOPRE >> 4 & 0xf)
+#define MC3_REFREC			8		/* 0-15 */
+#define MC3_RDLAT			(4+MC_ECC)	/* 0-15 */
+#define MC3_CPX				0		/* 0-1 */
+#define MC3_RAS6P			0		/* 0-15 */
+#define MC3_CAS5			0		/* 0-7 */
+#define MC3_CP4				0		/* 0-7 */
+#define MC3_CAS3			0		/* 0-7 */
+#define MC3_RCD2			0		/* 0-7 */
+#define MC3_RP1				0		/* 0-7 */
+
+	LOADPTR (r3, MEM_CONT3_ADR)	/* Set MCCR3 (F8) */
+	stwbrx	r3,0,r5
+	LOADPTR(r4, \
+		MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \
+		MC3_RDLAT << 20 | MC3_CPX << 19 | \
+		MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \
+		MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1)
+	cmpl	0, 0, r7, r9              /* Check for Kahlua2 */
+	bne     notK2b
+	/* clear Kahlua2 reserved bits */
+	LOADPTR (r3, 0xff000000)
+	and	r4, r4, r3
+notK2b:
+	stwbrx	r4,0,r6
+
+	/*------- MCCR4 */
+
+#define MC4_PRETOACT			3		/* 0-15 */
+#define MC4_ACTOPRE			5		/* 0-15 */
+#define MC4_WMODE			0		/* 0-1 */
+#define MC4_INLINE			MC_ECC		/* 0-1 */
+#define MC4_REGISTERED			(1-MC_ECC)	/* 0-1 */
+#define MC4_BSTOPRE_UU			(MC_BSTOPRE >> 8 & 3)
+#define MC4_REGDIMM			0		/* 0-1 */
+#define MC4_SDMODE_CAS			2		/* 0-7 */
+#define MC4_DBUS_RCS1			1		/* 0-1, 8-bit */
+#define MC4_SDMODE_WRAP			0		/* 0-1 */
+#define MC4_SDMODE_BURST		2		/* 0-7 */
+#define MC4_ACTORW			3		/* 0-15 */
+#define MC4_BSTOPRE_L			(MC_BSTOPRE & 0xf)
+
+	LOADPTR (r3, MEM_CONT4_ADR)	/* Set MCCR4 (FC) */
+	stwbrx	r3,0,r5
+	LOADPTR(r4, \
+		MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \
+		MC4_WMODE << 23 | MC4_INLINE << 22 | \
+		MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \
+		MC4_DBUS_RCS1 << 17 | \
+		MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \
+		MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \
+		MC4_ACTORW << 4 | MC4_BSTOPRE_L)
+	cmpl	0, 0, r7, r9                /* Check for Kahlua 2 */
+	bne     notK2c
+	/* Turn on Kahlua2 extended ROM space */
+	LOADPTR (r3, 0x00200000)
+	or	r4, r4, r3
+notK2c:
+	stwbrx	r4,0,r6
+
+#ifdef INCLUDE_ECC
+	/*------- MEM_ERREN1 */
+
+	LOADPTR (r3, MEM_ERREN1_ADR)	/* Set MEM_ERREN1 (c0) */
+	stwbrx	r3,0,r5
+	lwbrx	r4,0,r6
+	ori	r4,r4,4			/* Set MEM_PERR_EN */
+	stwbrx	r4,0,r6
+#endif /* INCLUDE_ECC */
+
+	/*------- MSAR/MEAR */
+
+	LOADPTR (r3, MEM_START1_ADR)	/* Set MSAR1 (80) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xc0804000)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, MEM_START2_ADR)	/* Set MSAR2 (84) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xc0804000)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, XMEM_START1_ADR)	/* Set MESAR1 (88) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x00000000)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, XMEM_START2_ADR)	/* Set MESAR2 (8c) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x01010101)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, MEM_END1_ADR)	/* Set MEAR1 (90) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xffbf7f3f)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, MEM_END2_ADR)	/* Set MEAR2 (94) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0xffbf7f3f)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, XMEM_END1_ADR)	/* MEEAR1 (98) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x00000000)
+	stwbrx	r4,0,r6
+
+	LOADPTR (r3, XMEM_END2_ADR)	/* MEEAR2 (9c) */
+	stwbrx	r3,0,r5
+	LOADPTR (r4, 0x01010101)
+	stwbrx	r4,0,r6
+
+	/*-------ODCR */
+
+	LOADPTR (r3, ODCR_ADR_X)	/* Set ODCR */
+	stwbrx	r3,0,r5
+
+	li	r4, 0x7f
+	stb	r4, ODCR_SHIFT(r6)	/* ODCR is at +3 offset */
+
+	/*-------MBEN */
+
+	LOADPTR (r3, MEM_EN_ADR)	/* Set MBEN (a0) */
+	stwbrx	r3,0,r5
+	li	r4, 0x01		/* Enable bank 0 */
+	stb	r4, 0(r6)		/* MBEN is at +0 offset */
+
+#if 0   /* Jimmy:  I think page made is broken */
+	/*-------PGMAX */
+
+	LOADPTR (r3, MPM_ADR_X)
+	stwbrx	r3,0,r5
+	li	r4, 0x32
+	stb	r4, MPM_SHIFT(r6)		/* PAGE_MODE is at +3 offset */
+#endif
+
+	/* Wait before initializing other registers */
+
+	lis	r4,0x0001
+	mtctr	r4
+
+KahluaX4wait200us:
+	bdnz	KahluaX4wait200us
+
+	/* Set MEMGO bit */
+
+	LOADPTR (r3, MEM_CONT1_ADR)	/* MCCR1 (F0) |= PGMAX */
+	stwbrx	r3,0,r5
+	lwbrx	r4,0,r6			/* old MCCR1 */
+	oris	r4,r4,0x0008		/* MEMGO=1 */
+	stwbrx	r4, 0, r6
+
+	/* Wait again */
+
+	addis	r4,r0,0x0002
+	ori	r4,r4,0xffff
+
+	mtctr	r4
+
+KahluaX4wait8ref:
+	bdnz	KahluaX4wait8ref
+
+	sync
+	eieio
+	mtlr    r11
+	blr
+
+#else /* USE_V2_INIT */
+
+
+/* U-Boot works, but memory will not run reliably for all address ranges.
+ * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not
+ * initialized correctly. Could work if debugged.
+ */
+/* PCI Support routines */
+
+    .globl __pci_config_read_32
+__pci_config_read_32:
+    lis     r4, 0xfec0
+    stwbrx   r3, r0, r4
+    sync
+    lis     r4, 0xfee0
+    lwbrx   r3, 0, r4
+    blr
+    .globl __pci_config_read_16
+__pci_config_read_16:
+    lis     r4, 0xfec0
+    andi.    r5, r3, 2
+    stwbrx  r3, r0, r4
+    sync
+    oris     r4, r5, 0xfee0
+    lhbrx    r3, r0, r4
+    blr
+    .globl __pci_config_read_8
+__pci_config_read_8:
+    lis     r4, 0xfec0
+    andi.    r5, r3, 3
+    stwbrx  r3, r0, r4
+    sync
+    oris     r4, r5, 0xfee0
+    lbz      r3, 0(4)
+    blr
+    .globl __pci_config_write_32
+__pci_config_write_32:
+    lis     r5, 0xfec0
+    stwbrx   r3, r0, r5
+    sync
+    lis      r5, 0xfee0
+    stwbrx   r4, r0, r5
+    sync
+    blr
+    .globl __pci_config_write_16
+__pci_config_write_16:
+    lis     r5, 0xfec0
+    andi.    r6, r3, 2
+    stwbrx  r3, r0, 5
+    sync
+    oris     r5, r6, 0xfee0
+    sthbrx    r4, r0, r5
+    sync
+    blr
+    .globl __pci_config_write_8
+__pci_config_write_8:
+    lis      r5, 0xfec0
+    andi.    r6, r3, 3
+    stwbrx   r3, r0, r5
+    sync
+    oris      r5, r6, 0xfee0
+    stb       r4, 0(r5)
+    sync
+    blr
+    .globl  in_8
+in_8:
+    oris    r3, r3, 0xfe00
+    lbz     r3,0(r3)
+    blr
+    .globl  in_16
+in_16:
+    oris    r3, r3, 0xfe00
+    lhbrx   r3, 0, r3
+    blr
+    .globl in_16_ne
+in_16_ne:
+    oris    r3, r3, 0xfe00
+    lhzx    r3, 0, r3
+    blr
+    .globl  in_32
+in_32:
+    oris    r3, r3, 0xfe00
+    lwbrx   r3, 0, r3
+    blr
+    .globl  out_8
+out_8:
+    oris    r3, r3, 0xfe00
+    stb     r4, 0(r3)
+    eieio
+    blr
+    .globl  out_16
+out_16:
+    oris    r3, r3, 0xfe00
+    sthbrx  r4, 0, r3
+    eieio
+    blr
+    .globl  out_16_ne
+out_16_ne:
+    oris    r3, r3, 0xfe00
+    sth     r4, 0(r3)
+    eieio
+    blr
+    .globl  out_32
+out_32:
+    oris    r3, r3, 0xfe00
+    stwbrx  r4, 0, r3
+    eieio
+    blr
+    .globl  read_8
+read_8:
+    lbz     r3,0(r3)
+    blr
+    .globl  read_16
+read_16:
+    lhbrx   r3, 0, r3
+    blr
+    .globl  read_32
+read_32:
+    lwbrx   r3, 0, r3
+    blr
+    .globl  read_32_ne
+read_32_ne:
+    lwz     r3, 0(r3)
+    blr
+    .globl  write_8
+write_8:
+    stb     r4, 0(r3)
+    eieio
+    blr
+    .globl  write_16
+write_16:
+    sthbrx  r4, 0, r3
+    eieio
+    blr
+    .globl  write_32
+write_32:
+    stwbrx  r4, 0, r3
+    eieio
+    blr
+    .globl  write_32_ne
+write_32_ne:
+    stw     r4, 0(r3)
+    eieio
+    blr
+
+
+.globl  early_init_f
+
+early_init_f:
+	mflr    r11
+	lis     r10, 0x8000
+
+	/* PCI Latency Timer */
+	li      r4, 0x0d
+	ori     r3, r10, PLTR@l
+	bl      __pci_config_write_8
+
+	/* Cache Line Size */
+	li      r4, 0x08
+	ori     r3, r10, PCLSR@l
+	bl      __pci_config_write_8
+
+	/* PCI Cmd */
+	li      r4, 6
+	ori     r3, r10, PCICR@l
+	bl      __pci_config_write_16
+
+#if 1
+	/* PCI Stat */
+	ori     r3, r10, PCISR@l
+	bl      __pci_config_read_16
+	ori     r4, r4, 0xffff
+	ori     r3, r10, PCISR@l
+	bl      __pci_config_write_16
+#endif
+
+	/* PICR1 */
+	lis     r4, 0xff14
+	ori     r4, r4, 0x1b98
+	ori     r3, r10, PICR1@l
+	bl      __pci_config_write_32
+
+
+	/* PICR2 */
+	lis     r4, 0x0404
+	ori     r4, r4, 0x0004
+	ori     r3, r10, PICR2@l
+	bl      __pci_config_write_32
+
+	/* MIOCR1 */
+	li      r4, 0x04
+	ori     r3, r10, MIOCR1@l
+	bl      __pci_config_write_8
+
+	/* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
+	/* SDRAM_CLK_DEL (0x77)*/
+	li      r4, 0x10
+	ori     r3, r10, MIOCR2@l
+	bl      __pci_config_write_8
+
+	/* EUMBBAR */
+	lis     r4, 0xfc00
+	ori     r3, r10, EUMBBAR@l
+	bl      __pci_config_write_32
+
+	/* AMBOR */
+
+       /* Even if Address Map B is not being used (though it should),
+	* the memory DLL needs to be cleared/set/cleared before using memory.
+	*/
+
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_read_8	/* get Current bits */
+
+	andi.   r4, r4, 0xffdf
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_write_16	/* Clear DLL_RESET */
+
+	ori    r4, r4, 0x0020
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_write_16	/* Set DLL_RESET */
+
+	andi.   r4, r4, 0xffdf
+	ori     r3, r10, AMBOR@l
+	bl      __pci_config_write_16	/* Clear DLL_RESET */
+
+	/* ERCR1 */
+	lis     r4, 0x8040		/* Enable RCS2, use supplied timings */
+	ori     r4, r4, 0x8000
+	ori     r3, r10, ERCR1@l
+	bl      __pci_config_write_32
+
+	/* ERCR2 */
+	lis     r4, 0x0000		/* Disable RCS3 parms */
+	ori     r4, r4, 0x0000
+	ori     r3, r10, ERCR2@l
+	bl      __pci_config_write_32
+
+	/* ERCR3 */
+	lis     r4, 0x0000		/* RCS3 at 0x70000000, 64K bytes */
+	ori     r4, r4, 0x0004
+	ori     r3, r10, ERCR2@l
+	bl      __pci_config_write_32
+
+	/* Preserve memgo bit */
+	/* MCCR1 */
+
+/*	lis     r4, 0x75a8		/  Safe Local ROM = 11+3 clocks */
+	lis     r4, 0x75a0              /* Safe Local ROM = 11+3 clocks */
+/*      lis     r4, 0x73a0              /  Fast Local ROM = 7+3 clocks */
+/*      oris    r4, r4, 0x0010          /  Burst ROM/Flash enable */
+/*      oris    r4, r4, 0x0004          /  Self-refresh enable */
+
+/*      ori     r4,r4,0xFFFF            /  16Mbit  2bank SDRAM */
+/*      ori     r4,r4,0xAAAA            /  256Mbit 4bank SDRAM (8245 only) */
+/*      ori     r4,r4,0x5555            /  64Mbit  2bank SDRAM */
+	ori     r4,r4,0x0000            /* 64Mbit  4bank SDRAM */
+
+	ori     r3, r10, MCCR1@l
+	bl      __pci_config_write_32
+
+	/* MCCR2 */
+
+	lis     r4,0x0000
+/*      oris    r4,r4,0x4000            /  TS_WAIT_TIMER = 3 clocks */
+	oris    r4,r4,0x1000            /* ASRISE = 8 clocks */
+	oris    r4,r4,0x0080            /* ASFALL = 8 clocks */
+/*      oris    r4,r4,0x0010            /  SDRAM Parity (else ECC) */
+/*      oris    r4,r4,0x0008            /  Write parity check */
+/*      oris    r4,r4,0x0004            /  SDRAM inline reads */
+
+
+/* Select a refresh rate; it needs to match the bus speed; if too */
+/* slow, data may be lost; if too fast, performance is lost.  We */
+/* use the fastest value so we run at all speeds. */
+/* Refresh = (15600ns/busclk) - (213 (see UM)). */
+
+/*      ori     r4,r4,0x1d2c            /  133 MHz mem bus        = 1867 */
+/*      ori     r4,r4,0x150c            /  100 MHz mem bus        = 1347 */
+/*      ori     r4,r4,0x10fc            /   83 MHz mem bus        = 1087 */
+/*      ori     r4,r4,0x0cc4            /   66 MHz mem bus        =  817 */
+	ori     r4,r4,0x04cc            /*  33 MHz mem bus (SAFE) =  307 */
+/*      ori     r4,r4,0x0002            /  Reserve a page */
+/*      ori     r4,r4,0x0001            /  RWM parity */
+
+	ori     r3, r10, MCCR2@l
+	bl      __pci_config_write_32
+
+
+	/* MCCR3 */
+	lis     r4,0x0000               /* BSTOPRE_M = 7 (see A/N) */
+	oris    r4,r4,0x0500            /* REFREC    = 8 clocks */
+	ori     r3, r10, MCCR3@l
+	bl      __pci_config_write_32
+
+	/* MCCR4 */                     /* Turn on registered buffer mode */
+	lis     r4, 0x2000              /* PRETOACT = 3 clocks */
+	oris    r4,r4,0x0400            /* ACTOPRE  = 5 clocks */
+/*      oris    r4,r4,0x0080            /  Enable 8-beat burst (32-bit bus) */
+/*      oris    r4,r4,0x0040            /  Enable Inline ECC/Parity */
+	oris    r4,r4,0x0020            /* EXTROM enabled */
+	oris    r4,r4,0x0010            /* Registered buffers */
+/*      oris    r4,r4,0x0000            /  BSTOPRE_U = 0 (see A/N) */
+	oris    r4,r4,0x0002            /* DBUS_SIZ[2] (8 bit on RCS1) */
+
+/*      ori     r4,r4,0x8000            /  Registered DIMMs */
+	ori     r4,r4,0x2000            /*CAS Latency (CL=3) (see RDLAT) */
+/*      ori     r4,r4,0x2000            /  CAS Latency (CL=2) (see RDLAT) */
+/*      ori     r4,r4,0x0300            /  Sequential wrap/8-beat burst */
+	ori     r4,r4,0x0200            /* Sequential wrap/4-beat burst */
+	ori     r4,r4,0x0030            /* ACTORW  = 3 clocks */
+	ori     r4,r4,0x0009            /* BSTOPRE_L = 9 (see A/N) */
+
+	ori     r3, r10, MCCR4@l
+	bl      __pci_config_write_32
+
+	/* MSAR1 */
+	lis     r4, 0xc0804000@h
+	ori     r4, r4, 0xc0804000@l
+	ori     r3, r10, MSAR1@l
+	bl      __pci_config_write_32
+
+	/* MSAR2 */
+	lis     r4, 0xc0804000@h
+	ori     r4, r4, 0xc0804000@l
+	ori     r3, r10, MSAR2@l
+	bl      __pci_config_write_32
+
+	/* MESAR1 */
+	lis     r4, 0x00000000@h
+	ori     r4, r4, 0x00000000@l
+	ori     r3, r10, EMSAR1@l
+	bl      __pci_config_write_32
+
+	/* MESAR2 */
+	lis     r4, 0x01010101@h
+	ori     r4, r4, 0x01010101@l
+	ori     r3, r10, EMSAR2@l
+	bl      __pci_config_write_32
+
+	/* MEAR1 */
+	lis     r4, 0xffbf7f3f@h
+	ori     r4, r4, 0xffbf7f3f@l
+	ori     r3, r10, MEAR1@l
+	bl      __pci_config_write_32
+
+	/* MEAR2 */
+	lis     r4, 0xffbf7f3f@h
+	ori     r4, r4, 0xffbf7f3f@l
+	ori     r3, r10, MEAR2@l
+	bl      __pci_config_write_32
+
+	/* MEEAR1 */
+	lis     r4, 0x00000000@h
+	ori     r4, r4, 0x00000000@l
+	ori     r3, r10, EMEAR1@l
+	bl      __pci_config_write_32
+
+	/* MEEAR2 */
+	lis     r4, 0x01010101@h
+	ori     r4, r4, 0x01010101@l
+	ori     r3, r10, EMEAR2@l
+	bl      __pci_config_write_32
+
+	/* ODCR */
+	li      r4, 0x7f
+	ori     r3, r10, ODCR@l
+	bl      __pci_config_write_8
+
+	/* MBER */
+	li      r4, 0x01
+	ori     r3, r10, MBER@l
+	bl      __pci_config_write_8
+
+	/* Page CTR aka PGMAX */
+	li      r4, 0x32
+	ori     r3, r10, 0x70
+	bl      __pci_config_write_8
+
+#if 0
+	/* CLK Drive */
+	ori     r4, r10, 0xfc01 /* Top bit will be ignored */
+	ori     r3, r10, 0x74
+	bl      __pci_config_write_16
+#endif
+
+	/* delay */
+	lis     r7, 1
+	mtctr   r7
+label1: 	bdnz    label1
+
+	/* Set memgo bit */
+	/* MCCR1 */
+	ori     r3, r10, MCCR1@l
+	bl      __pci_config_read_32
+	lis	r7, 0x0008
+	or	r4, r3, r7
+	ori     r3, r10, MCCR1@l
+	bl      __pci_config_write_32
+
+	/* delay again */
+	lis     r7, 1
+	mtctr   r7
+label2: 	bdnz    label2
+#if 0
+/* DEBUG: Infinite loop, write then read */
+loop:
+	lis     r7, 0xffff
+	mtctr   r7
+	li	r3, 0x5004
+	lis	r4, 0xa0a0
+	ori	r4, r4, 0x5050
+	bl write_32_ne
+	li	r3, 0x5004
+	bl read_32_ne
+	bdnz    loop
+#endif
+	mtlr    r11
+	blr
+#endif
diff --git a/board/bmw/flash.c b/board/bmw/flash.c
new file mode 100755
index 0000000..7fba174
--- /dev/null
+++ b/board/bmw/flash.c
@@ -0,0 +1,779 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR  (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+
+#if 0
+static void flash_get_offsets (ulong base, flash_info_t * info);
+#endif /* 0 */
+
+/*flash command address offsets*/
+
+#if 0
+#define ADDR0           (0x555)
+#define ADDR1           (0x2AA)
+#define ADDR3           (0x001)
+#else
+#define ADDR0		(0xAAA)
+#define ADDR1		(0x555)
+#define ADDR3		(0x001)
+#endif
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+#if 0
+static int byte_parity_odd (unsigned char x) __attribute__ ((const));
+#endif /* 0 */
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+	__attribute__ ((const));
+
+typedef struct {
+	FLASH_WORD_SIZE extval;
+	unsigned short intval;
+} map_entry;
+
+#if 0
+static int byte_parity_odd (unsigned char x)
+{
+	x ^= x >> 4;
+	x ^= x >> 2;
+	x ^= x >> 1;
+	return (x & 0x1) != 0;
+}
+#endif /* 0 */
+
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+{
+	static const map_entry mfct_map[] = {
+		{(FLASH_WORD_SIZE) AMD_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+		{(FLASH_WORD_SIZE) FUJ_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+		{(FLASH_WORD_SIZE) STM_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+		{(FLASH_WORD_SIZE) MT_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+	};
+
+	static const map_entry chip_map[] = {
+		{AMD_ID_F040B, FLASH_AM040},
+		{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
+	};
+
+	const map_entry *p;
+	unsigned long result = FLASH_UNKNOWN;
+
+	/* find chip id */
+	for (p = &chip_map[0];
+	     p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
+		if (p->extval == chip) {
+			result = FLASH_VENDMASK | p->intval;
+			break;
+		}
+
+	/* find vendor id */
+	for (p = &mfct_map[0];
+	     p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
+		if (p->extval == mfct) {
+			result &= ~FLASH_VENDMASK;
+			result |= (unsigned long) p->intval << 16;
+			break;
+		}
+
+	return result;
+}
+
+
+unsigned long flash_init (void)
+{
+	unsigned long i;
+	unsigned char j;
+	static const ulong flash_banks[] = CFG_FLASH_BANKS;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+
+		pflinfo->flash_id = FLASH_UNKNOWN;
+		pflinfo->size = 0;
+		pflinfo->sector_count = 0;
+	}
+
+	for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+		const unsigned long base_address = flash_banks[i];
+		volatile FLASH_WORD_SIZE *const flash =
+			(FLASH_WORD_SIZE *) base_address;
+#if 0
+		volatile FLASH_WORD_SIZE *addr2;
+#endif
+#if 0
+		/* write autoselect sequence */
+		flash[0x5555] = 0xaa;
+		flash[0x2aaa] = 0x55;
+		flash[0x5555] = 0x90;
+#else
+		flash[0xAAA << (3 * i)] = 0xaa;
+		flash[0x555 << (3 * i)] = 0x55;
+		flash[0xAAA << (3 * i)] = 0x90;
+#endif
+		__asm__ __volatile__ ("sync");
+
+#if 0
+		pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]);
+#else
+		pflinfo->flash_id =
+			flash_id (flash[0x0], flash[0x2 + 14 * i]);
+#endif
+
+		switch (pflinfo->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			pflinfo->size = 0x00080000;
+			pflinfo->sector_count = 8;
+			for (j = 0; j < 8; j++) {
+				pflinfo->start[j] =
+					base_address + 0x00010000 * j;
+				pflinfo->protect[j] = flash[(j << 16) | 0x2];
+			}
+			break;
+		case FLASH_STM800AB:
+			pflinfo->size = 0x00100000;
+			pflinfo->sector_count = 19;
+			pflinfo->start[0] = base_address;
+			pflinfo->start[1] = base_address + 0x4000;
+			pflinfo->start[2] = base_address + 0x6000;
+			pflinfo->start[3] = base_address + 0x8000;
+			for (j = 1; j < 16; j++) {
+				pflinfo->start[j + 3] =
+					base_address + 0x00010000 * j;
+			}
+#if 0
+			/* check for protected sectors */
+			for (j = 0; j < pflinfo->sector_count; j++) {
+				/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+				/* D0 = 1 if protected */
+				addr2 = (volatile FLASH_WORD_SIZE
+					 *) (pflinfo->start[j]);
+				if (pflinfo->flash_id & FLASH_MAN_SST)
+					pflinfo->protect[j] = 0;
+				else
+					pflinfo->protect[j] = addr2[2] & 1;
+			}
+#endif
+			break;
+		}
+		/* Protect monitor and environment sectors
+		 */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_MONITOR_BASE,
+			       CFG_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR,
+			       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			       &flash_info[0]);
+#endif
+
+		/* reset device to read mode */
+		flash[0x0000] = 0xf0;
+		__asm__ __volatile__ ("sync");
+	}
+
+	return flash_info[0].size + flash_info[1].size;
+}
+
+#if 0
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	static const char unk[] = "Unknown";
+	const char *mfct = unk, *type = unk;
+	unsigned int i;
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			mfct = "AMD";
+			break;
+		case FLASH_MAN_FUJ:
+			mfct = "FUJITSU";
+			break;
+		case FLASH_MAN_STM:
+			mfct = "STM";
+			break;
+		case FLASH_MAN_SST:
+			mfct = "SST";
+			break;
+		case FLASH_MAN_BM:
+			mfct = "Bright Microelectonics";
+			break;
+		case FLASH_MAN_INTEL:
+			mfct = "Intel";
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			type = "AM29F040B (512K * 8, uniform sector size)";
+			break;
+		case FLASH_AM400B:
+			type = "AM29LV400B (4 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM400T:
+			type = "AM29LV400T (4 Mbit, top boot sector)";
+			break;
+		case FLASH_AM800B:
+			type = "AM29LV800B (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM800T:
+			type = "AM29LV800T (8 Mbit, top boot sector)";
+			break;
+		case FLASH_AM160T:
+			type = "AM29LV160T (16 Mbit, top boot sector)";
+			break;
+		case FLASH_AM320B:
+			type = "AM29LV320B (32 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM320T:
+			type = "AM29LV320T (32 Mbit, top boot sector)";
+			break;
+		case FLASH_STM800AB:
+			type = "M29W800AB (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_SST800A:
+			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+			break;
+		case FLASH_SST160A:
+			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+			break;
+		}
+	}
+
+	printf ("\n  Brand: %s Type: %s\n"
+		"  Size: %lu KB in %d Sectors\n",
+		mfct, type, info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; i++) {
+		unsigned long size;
+		unsigned int erased;
+		unsigned long *flash = (unsigned long *) info->start[i];
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+			(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (flash = (unsigned long *) info->start[i], erased = 1;
+		     (flash != (unsigned long *) info->start[i] + size)
+		     && erased; flash++)
+			erased = *flash == ~0x0UL;
+
+		printf ("%s %08lX %s %s",
+			(i % 5) ? "" : "\n   ",
+			info->start[i],
+			erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
+	}
+
+	puts ("\n");
+	return;
+}
+
+#if 0
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	printf ("flash_get_size: \n");
+	/* Write auto select command: read Manufacturer ID */
+	eieio ();
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90;
+	value = addr2[0];
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+	printf ("recognised manufacturer");
+
+	value = addr2[ADDR3];	/* device ID        */
+	debug ("\ndev_code=%x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB        */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB        */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB      */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB      */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB      */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB      */
+
+	case (FLASH_WORD_SIZE) SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;		/* => 1 MB      */
+
+	case (FLASH_WORD_SIZE) SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;		/* => 2 MB      */
+
+	case (FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB      */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	printf ("flash id %lx; sector count %x, size %lx\n", info->flash_id,
+		info->sector_count, info->size);
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		if (info->flash_id & FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+#endif
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned char sh8b;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->
+								       start
+								       [sect]
+								       -
+								       info->
+								       start
+								       [0]) <<
+								      sh8b));
+			if (info->flash_id & FLASH_MAN_SST) {
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				udelay (30000);	/* wait 30 ms */
+			} else
+				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
+						       info->
+						       start[0]) << sh8b));
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int flag;
+	int i;
+	unsigned char sh8b;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
+				     info->start[0]);
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i << sh8b] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c
new file mode 100755
index 0000000..d72c861
--- /dev/null
+++ b/board/bmw/m48t59y.c
@@ -0,0 +1,322 @@
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ *
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and
+ * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD)
+ * registers which are used to set/get the internal date/time functions.
+ *
+ * This module implements Y2K compliance by taking full year numbers
+ * and translating back and forth from the TOD 2-digit year.
+ *
+ * NOTE: for proper interaction with an operating system, the TOD should
+ * be used to store Universal Coordinated Time (GMT) and timezone
+ * conversions should be used.
+ *
+ * Here is a diagram of the memory layout:
+ *
+ * +---------------------------------------------+ 0xffe0a000
+ * | Non-volatile memory                         | .
+ * |                                             | .
+ * | (8176 bytes of Non-volatile memory)         | .
+ * |                                             | .
+ * +---------------------------------------------+ 0xffe0bff0
+ * | Flags                                       |
+ * +---------------------------------------------+ 0xffe0bff1
+ * | Unused                                      |
+ * +---------------------------------------------+ 0xffe0bff2
+ * | Alarm Seconds                               |
+ * +---------------------------------------------+ 0xffe0bff3
+ * | Alarm Minutes                               |
+ * +---------------------------------------------+ 0xffe0bff4
+ * | Alarm Date                                  |
+ * +---------------------------------------------+ 0xffe0bff5
+ * | Interrupts                                  |
+ * +---------------------------------------------+ 0xffe0bff6
+ * | WatchDog                                    |
+ * +---------------------------------------------+ 0xffe0bff7
+ * | Calibration                                 |
+ * +---------------------------------------------+ 0xffe0bff8
+ * | Seconds                                     |
+ * +---------------------------------------------+ 0xffe0bff9
+ * | Minutes                                     |
+ * +---------------------------------------------+ 0xffe0bffa
+ * | Hours                                       |
+ * +---------------------------------------------+ 0xffe0bffb
+ * | Day                                         |
+ * +---------------------------------------------+ 0xffe0bffc
+ * | Date                                        |
+ * +---------------------------------------------+ 0xffe0bffd
+ * | Month                                       |
+ * +---------------------------------------------+ 0xffe0bffe
+ * | Year (2 digits only)                        |
+ * +---------------------------------------------+ 0xffe0bfff
+ */
+#include <common.h>
+#include <rtc.h>
+#include "bmw.h"
+
+/*
+ * Imported from mousse.h:
+ *
+ *   TOD_REG_BASE		Base of m48t59y TOD registers
+ *   SYS_TOD_UNPROTECT()	Disable NVRAM write protect
+ *   SYS_TOD_PROTECT()		Re-enable NVRAM write protect
+ */
+
+#define YEAR		0xf
+#define MONTH		0xe
+#define DAY		0xd
+#define DAY_OF_WEEK	0xc
+#define HOUR		0xb
+#define MINUTE		0xa
+#define SECOND		0x9
+#define CONTROL		0x8
+#define WATCH		0x7
+#define INTCTL		0x6
+#define WD_DATE		0x5
+#define WD_HOUR		0x4
+#define WD_MIN		0x3
+#define WD_SEC		0x2
+#define _UNUSED		0x1
+#define FLAGS		0x0
+
+#define M48_ADDR	((volatile unsigned char *) TOD_REG_BASE)
+
+int m48_tod_init(void)
+{
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] = 0;
+    M48_ADDR[WATCH] = 0;
+    M48_ADDR[INTCTL] = 0;
+
+    /*
+     * If the oscillator is currently stopped (as on a new part shipped
+     * from the factory), start it running.
+     *
+     * Here is an example of the TOD bytes on a brand new M48T59Y part:
+     *		00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01
+     */
+
+    if (M48_ADDR[SECOND] & 0x80)
+	M48_ADDR[SECOND] = 0;
+
+    /* Is battery low */
+    if ( M48_ADDR[FLAGS] & 0x10) {
+	 printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n");
+    }
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+/*
+ * m48_tod_set
+ */
+
+static int to_bcd(int value)
+{
+    return value / 10 * 16 + value % 10;
+}
+
+static int from_bcd(int value)
+{
+    return value / 16 * 10 + value % 16;
+}
+
+static int day_of_week(int y, int m, int d)	/* 0-6 ==> Sun-Sat */
+{
+    static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4};
+    y -= m < 3;
+    return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7;
+}
+
+/*
+ * Note: the TOD should store the current GMT
+ */
+
+int m48_tod_set(int year,		/* 1980-2079 */
+		int month,		/* 01-12 */
+		int day,		/* 01-31 */
+		int hour,		/* 00-23 */
+		int minute,		/* 00-59 */
+		int second)		/* 00-59 */
+
+{
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] |= 0x80;	/* Set WRITE bit */
+
+    M48_ADDR[YEAR] = to_bcd(year % 100);
+    M48_ADDR[MONTH] = to_bcd(month);
+    M48_ADDR[DAY] = to_bcd(day);
+    M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1;
+    M48_ADDR[HOUR] = to_bcd(hour);
+    M48_ADDR[MINUTE] = to_bcd(minute);
+    M48_ADDR[SECOND] = to_bcd(second);
+
+    M48_ADDR[CONTROL] &= ~0x80;	/* Clear WRITE bit */
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+/*
+ * Note: the TOD should store the current GMT
+ */
+
+int m48_tod_get(int *year,		/* 1980-2079 */
+		int *month,		/* 01-12 */
+		int *day,		/* 01-31 */
+		int *hour,		/* 00-23 */
+		int *minute,		/* 00-59 */
+		int *second)		/* 00-59 */
+{
+    int y;
+
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] |= 0x40;	/* Set READ bit */
+
+    y = from_bcd(M48_ADDR[YEAR]);
+    *year = y < 80 ? 2000 + y : 1900 + y;
+    *month = from_bcd(M48_ADDR[MONTH]);
+    *day = from_bcd(M48_ADDR[DAY]);
+    /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */
+    *hour = from_bcd(M48_ADDR[HOUR]);
+    *minute = from_bcd(M48_ADDR[MINUTE]);
+    *second = from_bcd(M48_ADDR[SECOND] & 0x7f);
+
+    M48_ADDR[CONTROL] &= ~0x40;	/* Clear READ bit */
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+int m48_tod_get_second(void)
+{
+    return from_bcd(M48_ADDR[SECOND] & 0x7f);
+}
+
+/*
+ * Watchdog function
+ *
+ *  If usec is 0, the watchdog timer is disarmed.
+ *
+ *  If usec is non-zero, the watchdog timer is armed (or re-armed) for
+ *    approximately usec microseconds (if the exact requested usec is
+ *    not supported by the chip, the next higher available value is used).
+ *
+ *  Minimum watchdog timeout = 62500 usec
+ *  Maximum watchdog timeout = 124 sec (124000000 usec)
+ */
+
+void m48_watchdog_arm(int usec)
+{
+    int		mpy, res;
+
+    SYS_TOD_UNPROTECT();
+
+    if (usec == 0) {
+	res = 0;
+	mpy = 0;
+    } else if (usec < 2000000) {	/* Resolution: 1/16s if below 2s */
+	res = 0;
+	mpy = (usec + 62499) / 62500;
+    } else if (usec < 8000000) {	/* Resolution: 1/4s if below 8s */
+	res = 1;
+	mpy = (usec + 249999) / 250000;
+    } else if (usec < 32000000) {	/* Resolution: 1s if below 32s */
+	res = 2;
+	mpy = (usec + 999999) / 1000000;
+    } else {				/* Resolution: 4s up to 124s */
+	res = 3;
+	mpy = (usec + 3999999) / 4000000;
+	if (mpy > 31)
+	    mpy = 31;
+    }
+
+    M48_ADDR[WATCH] = (0x80 |		/* Steer to RST signal (IRQ = N/C) */
+		       mpy << 2 |
+		       res);
+
+    SYS_TOD_PROTECT();
+}
+
+/*
+ * U-Boot RTC support.
+ */
+void
+rtc_get( struct rtc_time *tmp )
+{
+	m48_tod_get(&tmp->tm_year,
+		    &tmp->tm_mon,
+		    &tmp->tm_mday,
+		    &tmp->tm_hour,
+		    &tmp->tm_min,
+		    &tmp->tm_sec);
+	tmp->tm_yday = 0;
+	tmp->tm_isdst= 0;
+
+#ifdef RTC_DEBUG
+	printf( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
+#endif
+}
+
+void
+rtc_set( struct rtc_time *tmp )
+{
+	m48_tod_set(tmp->tm_year,		/* 1980-2079 */
+		    tmp->tm_mon,		/* 01-12 */
+		    tmp->tm_mday,              /* 01-31 */
+		    tmp->tm_hour,		/* 00-23 */
+		    tmp->tm_min,		/* 00-59 */
+		    tmp->tm_sec);		/* 00-59 */
+
+#ifdef RTC_DEBUG
+	printf( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+
+}
+
+void
+rtc_reset (void)
+{
+  m48_tod_init();
+}
diff --git a/board/bmw/m48t59y.h b/board/bmw/m48t59y.h
new file mode 100755
index 0000000..717300d
--- /dev/null
+++ b/board/bmw/m48t59y.h
@@ -0,0 +1,57 @@
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ *
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M48_T59_Y_H
+#define __M48_T59_Y_H
+
+/*
+ * M48 T59Y -Timekeeping Battery backed SRAM.
+ */
+
+int m48_tod_init(void);
+
+int m48_tod_set(int year,
+		int month,
+		int day,
+		int hour,
+		int minute,
+		int second);
+
+int m48_tod_get(int *year,
+		int *month,
+		int *day,
+		int *hour,
+		int *minute,
+		int *second);
+
+int m48_tod_get_second(void);
+
+void m48_watchdog_arm(int usec);
+
+#endif /*!__M48_T59_Y_H */
diff --git a/board/bmw/ns16550.c b/board/bmw/ns16550.c
new file mode 100755
index 0000000..7064567
--- /dev/null
+++ b/board/bmw/ns16550.c
@@ -0,0 +1,57 @@
+/*
+ * COM1 NS16550 support
+ * originally from linux source (arch/ppc/boot/ns16550.c)
+ * modified to use CFG_ISA_MEM and new defines
+ */
+
+#include <config.h>
+#include "ns16550.h"
+
+typedef struct NS16550 *NS16550_t;
+
+const NS16550_t COM_PORTS[] =
+	{ (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500),
+(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) };
+
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
+{
+	volatile struct NS16550 *com_port;
+
+	com_port = (struct NS16550 *) COM_PORTS[chan];
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
+	return (com_port);
+}
+
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
+{
+	com_port->ier = 0x00;
+	com_port->lcr = LCR_BKSE;	/* Access baud rate */
+	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
+	com_port->dlm = (baud_divisor >> 8) & 0xff;
+	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
+	com_port->mcr = MCR_RTS;	/* RTS/DTR */
+	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;	/* Clear & enable FIFOs */
+}
+
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
+{
+	while ((com_port->lsr & LSR_THRE) == 0);
+	com_port->thr = c;
+}
+
+unsigned char NS16550_getc (volatile struct NS16550 *com_port)
+{
+	while ((com_port->lsr & LSR_DR) == 0);
+	return (com_port->rbr);
+}
+
+int NS16550_tstc (volatile struct NS16550 *com_port)
+{
+	return ((com_port->lsr & LSR_DR) != 0);
+}
diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h
new file mode 100755
index 0000000..104f45b
--- /dev/null
+++ b/board/bmw/ns16550.h
@@ -0,0 +1,79 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/ppc/boot/ns16550.h)
+ * modified slightly to
+ * have addresses as offsets from CFG_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ * further modified to support the 8245 duart
+ * modifications (c) Paul Jimenez, Musenki, Inc. 2001.
+ */
+
+
+struct NS16550 {
+	unsigned char rbrthrdlb;	/* 0 */
+	unsigned char ierdmb;		/* 1 */
+	unsigned char iirfcrafr;	/* 2 */
+	unsigned char lcr;		/* 3 */
+	unsigned char mcr;		/* 4 */
+	unsigned char lsr;		/* 5 */
+	unsigned char msr;		/* 6 */
+	unsigned char scr;		/* 7 */
+	unsigned char reserved[2];	/* 8 & 9 */
+	unsigned char dsr;		/* 10 */
+	unsigned char dcr;		/* 11 */
+};
+
+
+#define rbr rbrthrdlb
+#define thr rbrthrdlb
+#define dll rbrthrdlb
+#define ier ierdmb
+#define dlm ierdmb
+#define iir iirfcrafr
+#define fcr iirfcrafr
+#define afr iirfcrafr
+
+#define FCR_FIFO_EN     0x01	/*fifo enable */
+#define FCR_RXSR        0x02	/*reciever soft reset */
+#define FCR_TXSR        0x04	/*transmitter soft reset */
+#define FCR_DMS		0x08	/* DMA Mode Select */
+
+#define MCR_RTS         0x02	/* Readyu to Send */
+#define MCR_LOOP	0x10	/* Local loopback mode enable */
+/* #define MCR_DTR         0x01    noton 8245 duart */
+/* #define MCR_DMA_EN      0x04    noton 8245 duart */
+/* #define MCR_TX_DFR      0x08    noton 8245 duart */
+
+#define LCR_WLS_MSK 0x03	/* character length slect mask */
+#define LCR_WLS_5   0x00	/* 5 bit character length */
+#define LCR_WLS_6   0x01	/* 6 bit character length */
+#define LCR_WLS_7   0x02	/* 7 bit character length */
+#define LCR_WLS_8   0x03	/* 8 bit character length */
+#define LCR_STB     0x04	/* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN     0x08	/* Parity eneble */
+#define LCR_EPS     0x10	/* Even Parity Select */
+#define LCR_STKP    0x20	/* Stick Parity */
+#define LCR_SBRK    0x40	/* Set Break */
+#define LCR_BKSE    0x80	/* Bank select enable - aka DLAB on 8245 */
+
+#define LSR_DR      0x01	/* Data ready */
+#define LSR_OE      0x02	/* Overrun */
+#define LSR_PE      0x04	/* Parity error */
+#define LSR_FE      0x08	/* Framing error */
+#define LSR_BI      0x10	/* Break */
+#define LSR_THRE    0x20	/* Xmit holding register empty */
+#define LSR_TEMT    0x40	/* Xmitter empty */
+#define LSR_ERR     0x80	/* Error */
+
+/* useful defaults for LCR*/
+#define LCR_8N1     0x03
+
+
+volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
+void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
+unsigned char NS16550_getc (volatile struct NS16550 *com_port);
+int NS16550_tstc (volatile struct NS16550 *com_port);
+void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);
diff --git a/board/bmw/serial.c b/board/bmw/serial.c
new file mode 100755
index 0000000..f36a41b
--- /dev/null
+++ b/board/bmw/serial.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "ns16550.h"
+
+#if CONFIG_CONS_INDEX == 1
+static struct NS16550 *console =
+		(struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
+#elif CONFIG_CONS_INDEX == 2
+static struct NS16550 *console =
+		(struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
+#else
+#error no valid console defined
+#endif
+
+extern ulong get_bus_freq (ulong);
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
+
+	NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor);
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n') {
+		serial_putc ('\r');
+	}
+	NS16550_putc (console, c);
+}
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+
+int serial_getc (void)
+{
+	return NS16550_getc (console);
+}
+
+int serial_tstc (void)
+{
+	return NS16550_tstc (console);
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
+
+	NS16550_reinit (console, clock_divisor);
+}
diff --git a/board/bmw/u-boot.lds b/board/bmw/u-boot.lds
new file mode 100755
index 0000000..eaee3fd
--- /dev/null
+++ b/board/bmw/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/c2mon/Makefile b/board/c2mon/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/c2mon/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c
new file mode 100755
index 0000000..ca8eb0c
--- /dev/null
+++ b/board/c2mon/c2mon.c
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char *s = (unsigned char *)getenv ("serial#");
+
+	puts ("Board: TTTech C2MON ");
+
+	for (; s && *s; ++s) {
+		if (*s == ' ')
+			break;
+		putc (*s);
+	}
+
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long reg;
+	long int size8, size9;
+	long int size = 0;
+
+	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 2 the SDRAM bank 2 at physical address 0.
+	 */
+	memctl->memc_or2 = CFG_OR2_PRELIM;
+	memctl->memc_br2 = CFG_BR2_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL,
+			   SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL,
+			   SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size = size9;
+/*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {			/* back to 8 columns            */
+		size = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+/*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if (size < 0x02000000) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/*
+	 * No bank 1
+	 *
+	 * invalidate bank
+	 */
+	memctl->memc_br3 = 0;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/board/c2mon/config.mk b/board/c2mon/config.mk
new file mode 100755
index 0000000..c2d21e2
--- /dev/null
+++ b/board/c2mon/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TTTech C2MON boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/c2mon/flash.c b/board/c2mon/flash.c
new file mode 100755
index 0000000..b2be21c
--- /dev/null
+++ b/board/c2mon/flash.c
@@ -0,0 +1,570 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef	CFG_ENV_ADDR
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V;
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds
new file mode 100755
index 0000000..cdf550f
--- /dev/null
+++ b/board/c2mon/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug
new file mode 100755
index 0000000..3165d56
--- /dev/null
+++ b/board/c2mon/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/canmb/Makefile b/board/canmb/Makefile
new file mode 100755
index 0000000..607833f
--- /dev/null
+++ b/board/canmb/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+#../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
new file mode 100755
index 0000000..1782b31
--- /dev/null
+++ b/board/canmb/canmb.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m32s2-75.h"
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
+int checkboard (void)
+{
+	puts ("Board: CANMB\n");
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	return 0;
+}
diff --git a/board/canmb/config.mk b/board/canmb/config.mk
new file mode 100755
index 0000000..a163b34
--- /dev/null
+++ b/board/canmb/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2003
+# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CANMB board
+#
+# allowed and functional TEXT_BASE values:
+#
+#   0xfe000000		low boot at 0x00000100 (default board setting)
+#	0x00100000		RAM load and test
+#
+
+TEXT_BASE = 0xFE000000
+#TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h
new file mode 100755
index 0000000..ffdf039
--- /dev/null
+++ b/board/canmb/mt48lc16m32s2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/canmb/u-boot.lds b/board/canmb/u-boot.lds
new file mode 100755
index 0000000..88dc118
--- /dev/null
+++ b/board/canmb/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cds/common/cadmus.c b/board/cds/common/cadmus.c
new file mode 100755
index 0000000..5f86de5
--- /dev/null
+++ b/board/cds/common/cadmus.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+
+
+/*
+ * CADMUS Board System Registers
+ */
+#ifndef CFG_CADMUS_BASE_REG
+#define CFG_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
+#endif
+
+typedef struct cadmus_reg {
+    u_char cm_ver;		/* Board version */
+    u_char cm_csr;		/* General control/status */
+    u_char cm_rst;		/* Reset control */
+    u_char cm_hsclk;		/* High speed clock */
+    u_char cm_hsxclk;		/* High speed clock extended */
+    u_char cm_led;		/* LED data */
+    u_char cm_pci;		/* PCI control/status */
+    u_char cm_dma;		/* DMA control */
+    u_char cm_reserved[248];	/* Total 256 bytes */
+} cadmus_reg_t;
+
+
+unsigned int
+get_board_version(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	return cadmus->cm_ver;
+}
+
+
+unsigned long
+get_clock_freq(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
+
+	if (pci1_speed == 0) {
+		return 33000000;
+	} else if (pci1_speed == 1) {
+		return 66000000;
+	} else {
+		/* Really, unknown. Be safe? */
+		return 33000000;
+	}
+}
+
+
+unsigned int
+get_pci_slot(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	/*
+	 * PCI slot in USER bits CSR[6:7] by convention.
+	 */
+	return ((cadmus->cm_csr >> 6) & 0x3) + 1;
+}
+
+
+unsigned int
+get_pci_dual(void)
+{
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+	/*
+	 * PCI DUAL in CM_PCI[3]
+	 */
+	return cadmus->cm_pci & 0x10;
+}
diff --git a/board/cds/common/cadmus.h b/board/cds/common/cadmus.h
new file mode 100755
index 0000000..217ea64
--- /dev/null
+++ b/board/cds/common/cadmus.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CADMUS_H_
+#define __CADMUS_H_
+
+
+/*
+ * CADMUS Board System Register interface.
+ */
+
+/*
+ * Returns board version register.
+ */
+extern unsigned int get_board_version(void);
+
+/*
+ * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
+ */
+extern unsigned long get_clock_freq(void);
+
+
+/*
+ * Returns 1 - 4, as found in the USER CSR[6:7] bits.
+ */
+extern unsigned int get_pci_slot(void);
+
+
+/*
+ * Returns PCI DUAL as found in CM_PCI[3].
+ */
+extern unsigned int get_pci_dual(void);
+
+
+#endif	/* __CADMUS_H_ */
diff --git a/board/cds/common/eeprom.c b/board/cds/common/eeprom.c
new file mode 100755
index 0000000..5034e0c
--- /dev/null
+++ b/board/cds/common/eeprom.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <i2c.h>
+
+#include "eeprom.h"
+
+
+typedef struct {
+	char idee_pcbid[4];		/* "CCID" for CDC v1.X */
+	u8 idee_major;
+	u8 idee_minor;
+	char idee_serial[10];
+	char idee_errata[2];
+	char idee_date[8];		/* yyyymmdd */
+	/* The rest of the EEPROM space is reserved */
+} id_eeprom_t;
+
+
+unsigned int
+get_cpu_board_revision(void)
+{
+	uint major = 0;
+	uint minor = 0;
+
+	id_eeprom_t id_eeprom;
+
+	i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
+		 (uchar *) &id_eeprom, sizeof(id_eeprom));
+
+	major = id_eeprom.idee_major;
+	minor = id_eeprom.idee_minor;
+
+	if (major == 0xff && minor == 0xff) {
+		major = minor = 0;
+	}
+
+	return MPC85XX_CPU_BOARD_REV(major,minor);
+}
diff --git a/board/cds/common/eeprom.h b/board/cds/common/eeprom.h
new file mode 100755
index 0000000..12a0789
--- /dev/null
+++ b/board/cds/common/eeprom.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EEPROM_H_
+#define __EEPROM_H_
+
+
+/*
+ * EEPROM Board System Register interface.
+ */
+
+
+/*
+ * CPU Board Revision
+ */
+#define MPC85XX_CPU_BOARD_REV(maj, min)	((((maj)&0xff) << 8) | ((min) & 0xff))
+#define MPC85XX_CPU_BOARD_MAJOR(rev)	(((rev) >> 8) & 0xff)
+#define MPC85XX_CPU_BOARD_MINOR(rev)	((rev) & 0xff)
+
+#define MPC85XX_CPU_BOARD_REV_UNKNOWN	MPC85XX_CPU_BOARD_REV(0,0)
+#define MPC85XX_CPU_BOARD_REV_1_0	MPC85XX_CPU_BOARD_REV(1,0)
+#define MPC85XX_CPU_BOARD_REV_1_1	MPC85XX_CPU_BOARD_REV(1,1)
+
+/*
+ * Returns CPU board revision register as a 16-bit value with
+ * the Major in the high byte, and Minor in the low byte.
+ */
+extern unsigned int get_cpu_board_revision(void);
+
+
+#endif	/* __CADMUS_H_ */
diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile
new file mode 100755
index 0000000..0d4abbd
--- /dev/null
+++ b/board/cds/mpc8541cds/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o \
+	   ../common/cadmus.o \
+	   ../common/eeprom.o
+
+SOBJS	:= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cds/mpc8541cds/config.mk b/board/cds/mpc8541cds/config.mk
new file mode 100755
index 0000000..17cc8bc
--- /dev/null
+++ b/board/cds/mpc8541cds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8541cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1
diff --git a/board/cds/mpc8541cds/init.S b/board/cds/mpc8541cds/init.S
new file mode 100755
index 0000000..53dcd0d
--- /dev/null
+++ b/board/cds/mpc8541cds/init.S
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end
diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c
new file mode 100755
index 0000000..6b8aa68
--- /dev/null
+++ b/board/cds/mpc8541cds/mpc8541cds.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf ("    PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		/*
+		 * Work around to stabilize DDR DLL MSYNC_IN.
+		 * Errata DDR9 seems to have been fixed.
+		 * This is now the workaround for Errata DDR11:
+		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+		 */
+
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay(200);
+	}
+#endif
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	/*
+	 * SDRAM Initialization
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+	uint idx;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	asm("msync");
+
+	lbc->br2 = CFG_BR2_PRELIM;
+	asm("msync");
+
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxcds_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif
+}
diff --git a/board/cds/mpc8541cds/u-boot.lds b/board/cds/mpc8541cds/u-boot.lds
new file mode 100755
index 0000000..1bea007
--- /dev/null
+++ b/board/cds/mpc8541cds/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/cds/mpc8541cds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/cds/mpc8541cds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile
new file mode 100755
index 0000000..0d4abbd
--- /dev/null
+++ b/board/cds/mpc8548cds/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o \
+	   ../common/cadmus.o \
+	   ../common/eeprom.o
+
+SOBJS	:= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk
new file mode 100755
index 0000000..242a676
--- /dev/null
+++ b/board/cds/mpc8548cds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8548cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S
new file mode 100755
index 0000000..53dcd0d
--- /dev/null
+++ b/board/cds/mpc8548cds/init.S
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c
new file mode 100755
index 0000000..5bc0890
--- /dev/null
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf ("    PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		/*
+		 * Work around to stabilize DDR DLL MSYNC_IN.
+		 * Errata DDR9 seems to have been fixed.
+		 * This is now the workaround for Errata DDR11:
+		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+		 */
+
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay(200);
+	}
+#endif
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	/*
+	 * SDRAM Initialization
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	clkdiv = (lbc->lcrr & 0x0f) * 2;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	gur->lbiuiplldcr1 = 0x00078080;
+	if (clkdiv == 16) {
+		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+	} else if (clkdiv == 8) {
+		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+	} else if (clkdiv == 4) {
+		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+	}
+
+	lbc->lcrr |= 0x00030000;
+
+	asm("sync;isync;msync");
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+	uint idx;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	asm("msync");
+
+	lbc->br2 = CFG_BR2_PRELIM;
+	asm("msync");
+
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * MPC8548 uses "new" 15-16 style addressing.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxcds_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif
+}
diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds
new file mode 100755
index 0000000..2c8fe96
--- /dev/null
+++ b/board/cds/mpc8548cds/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/cds/mpc8548cds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/cds/mpc8548cds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile
new file mode 100755
index 0000000..0d4abbd
--- /dev/null
+++ b/board/cds/mpc8555cds/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o \
+	   ../common/cadmus.o \
+	   ../common/eeprom.o
+
+SOBJS	:= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cds/mpc8555cds/config.mk b/board/cds/mpc8555cds/config.mk
new file mode 100755
index 0000000..5dcaa77
--- /dev/null
+++ b/board/cds/mpc8555cds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8555cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1
diff --git a/board/cds/mpc8555cds/init.S b/board/cds/mpc8555cds/init.S
new file mode 100755
index 0000000..53dcd0d
--- /dev/null
+++ b/board/cds/mpc8555cds/init.S
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xa0000000	256M	PCI2 MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	PCI2 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 * 0xe300_0000	16M	PCI2 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	1M	Non-cacheable, guarded
+	 * 0xf8000000	1M	CADMUS registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xe300_0000     0xe3ff_ffff     PCI2 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
+ * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
+ * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff)
+#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+
+law_entry:
+	entry_start
+	.long 6
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+	entry_end
diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c
new file mode 100755
index 0000000..18adf5b
--- /dev/null
+++ b/board/cds/mpc8555cds/mpc8555cds.c
@@ -0,0 +1,501 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+	/* PCI slot in USER bits CSR[6:7] by convention. */
+	uint pci_slot = get_pci_slot ();
+
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
+	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+
+	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	uint cpu_board_rev = get_cpu_board_revision ();
+
+	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+		get_board_version (), pci_slot);
+
+	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+	printf ("    PCI1: %d bit, %s MHz, %s\n",
+		(pci1_32) ? 32 : 64,
+		(pci1_speed == 33000000) ? "33" :
+		(pci1_speed == 66000000) ? "66" : "unknown",
+		pci1_clk_sel ? "sync" : "async");
+
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		/*
+		 * Work around to stabilize DDR DLL MSYNC_IN.
+		 * Errata DDR9 seems to have been fixed.
+		 * This is now the workaround for Errata DDR11:
+		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
+		 */
+
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay(200);
+	}
+#endif
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	/*
+	 * SDRAM Initialization
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+	uint temp_lbcdll;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+
+	} else {
+		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+	uint idx;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint cpu_board_rev;
+	uint lsdmr_common;
+
+	puts("    SDRAM: ");
+
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	asm("msync");
+
+	lbc->br2 = CFG_BR2_PRELIM;
+	asm("msync");
+
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("msync");
+
+	/*
+	 * Determine which address lines to use baed on CPU board rev.
+	 */
+	cpu_board_rev = get_cpu_board_revision();
+	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+	} else {
+		/*
+		 * Assume something unable to identify itself is
+		 * really old, and likely has lines 16/17 mapped.
+		 */
+		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+	}
+
+	/*
+	 * Issue PRECHARGE ALL command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue 8 AUTO REFRESH commands.
+	 */
+	for (idx = 0; idx < 8; idx++) {
+		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		asm("sync;msync");
+		*sdram_addr = 0xff;
+		ppcDcbf((unsigned long) sdram_addr);
+		udelay(100);
+	}
+
+	/*
+	 * Issue 8 MODE-set command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	/*
+	 * Issue NORMAL OP command.
+	 */
+	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	asm("sync;msync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(200);    /* Overkill. Must wait > 200 bus cycles */
+
+#endif	/* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxcds_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif
+}
diff --git a/board/cds/mpc8555cds/u-boot.lds b/board/cds/mpc8555cds/u-boot.lds
new file mode 100755
index 0000000..2aa2ad7
--- /dev/null
+++ b/board/cds/mpc8555cds/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/cds/mpc8555cds/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/cds/mpc8555cds/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile
new file mode 100755
index 0000000..83e3ba4
--- /dev/null
+++ b/board/cerf250/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cerf250.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c
new file mode 100755
index 0000000..cc1bc16
--- /dev/null
+++ b/board/cerf250/cerf250.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of cerf PXA Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
diff --git a/board/cerf250/config.mk b/board/cerf250/config.mk
new file mode 100755
index 0000000..1a86cc9
--- /dev/null
+++ b/board/cerf250/config.mk
@@ -0,0 +1,5 @@
+#
+# Cerf board with PXA250 cpu
+#
+#
+TEXT_BASE = 0xa3080000
diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c
new file mode 100755
index 0000000..ba82892
--- /dev/null
+++ b/board/cerf250/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S
new file mode 100755
index 0000000..c9b68d7
--- /dev/null
+++ b/board/cerf250/lowlevel_init.S
@@ -0,0 +1,411 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc  p15,0,\reg,c2,c0,0
+   mov  \reg,\reg
+   sub  pc,pc,#4
+   .endm
+
+
+/*
+ * 	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,  [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=PSSR				/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,	[r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr		r3,	=OSCR			/* reset the OS Timer Count to zero */
+	mov 	r2,	#0
+	str 	r2,	[r3]
+	ldr 	r4,	=0x300				/* really 0x2E1 is about 200usec,   */
+							/* so 0x300 should be plenty        */
+1:
+	ldr 	r2,	[r3]
+	cmp 	r4,	r2
+	bgt 	1b
+
+mem_init:
+
+	ldr  	r1,	=MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr  	r2,	=CFG_MSC0_VAL
+	str  	r2,	[r1, #MSC0_OFFSET]
+	ldr  	r2,	[r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */
+	/* MSC1: nCS(2,3)                                                   */
+	ldr  	r2,	=CFG_MSC1_VAL
+	str  	r2,	[r1, #MSC1_OFFSET]
+	ldr  	r2,	[r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr  	r2,	=CFG_MSC2_VAL
+	str  	r2,	[r1, #MSC2_OFFSET]
+	ldr  	r2,	[r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr  	r2,	=CFG_MECR_VAL
+	str  	r2,	[r1, #MECR_OFFSET]
+	ldr	 	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr  	r2,	=CFG_MCMEM0_VAL
+	str  	r2,	[r1, #MCMEM0_OFFSET]
+	ldr	 	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr  	r2,	=CFG_MCMEM1_VAL
+	str  	r2,	[r1, #MCMEM1_OFFSET]
+	ldr	 	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr  	r2,	=CFG_MCATT0_VAL
+	str  	r2,	[r1, #MCATT0_OFFSET]
+	ldr	 	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr  	r2, =CFG_MCATT1_VAL
+	str  	r2, [r1, #MCATT1_OFFSET]
+	ldr	 	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr  	r2, =CFG_MCIO0_VAL
+	str  	r2, [r1, #MCIO0_OFFSET]
+	ldr	 	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr  	r2, =CFG_MCIO1_VAL
+	str  	r2, [r1, #MCIO1_OFFSET]
+	ldr	 	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DRI field, set SDRAM clocks free running */
+
+	ldr  	r3, =CFG_MDREFR_VAL
+	ldr  	r2, =0xFFF
+	and  	r3, r3,  r2
+
+	ldr	 	r0,	[r1, #MDREFR_OFFSET]
+	bic	 	r0, r0, r2
+	bic	 	r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
+	orr	 	r0, r0, r3
+
+	str		r0,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	/* set MDREFR according to user define with exception of a few bits */
+
+	ldr     r4, =CFG_MDREFR_VAL
+	ldr		r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
+					MDREFR_K2RUN |MDREFR_K2DB2)
+	and		r4, r4, r2
+	bic		r0,	r0,	r2
+	orr		r0, r0, r4
+
+	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r0, [r1, #MDREFR_OFFSET]
+
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
+
+	bic		r0, r0,	#(MDREFR_SLFRSH)
+	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r0, [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE  */
+
+	ldr     r4, =CFG_MDREFR_VAL
+	ldr		r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
+					MDREFR_K1FREE | MDREFR_K2FREE)
+	and		r4, r4, r2
+	orr		r0, r0, r4
+	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r0, [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
+
+	ldr		r4,	=CFG_MDCNFG_VAL
+	bic		r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic		r4, r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+	str     r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+	ldr     r4, [r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr 	r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov 	r2, #0
+	str 	r2, [r3]
+	ldr 	r4, =0x300			/* really 0x2E1 is about 200usec,   */
+						/* so 0x300 should be plenty        */
+1:
+	ldr 	r2, [r3]
+	cmp 	r4, r2
+	bgt 	1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	ldr		r3,	=CFG_DRAM_BASE
+.rept 8
+	str		r2,	[r3]
+.endr
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
+
+	ldr     r3, [r1, #MDCNFG_OFFSET]
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	str     r3, [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2, =CFG_MDMRS_VAL
+	str     r2, [r1, #MDMRS_OFFSET]
+
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2, =ICLR
+	str     r1, [r2]
+
+	ldr     r2, =ICMR	/* mask all interrupts at the controller    */
+	str     r1, [r2]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+	ldr     r1, =CKEN
+	mov     r2, #0
+	str     r2, [r1]
+
+
+	/* default value in case no valid rotary switch setting is found    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1, =CCCR
+	str     r2, [r1]
+
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+
+	ldr     r1, =OSCC
+	mov     r2, #OSCC_OON
+	str     r2, [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size */
+    ldr     r1, =DRAM_SIZE
+	str   	r8, [r1]
+
+	/* Interrupt init: Mask all interrupts                              */
+    ldr		r0,	=ICMR /* enable no sources */
+	mov 	r1,	#0
+    str 	r1,	[r0]
+
+	/* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov		r0,#0
+	mcr		p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr		p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr		p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov		r0,#0x80000000
+	mcr		p14,0,r0,c10,c0,0  /* dcsr */
+
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init                                                     */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+    mov     pc,	lr
diff --git a/board/cerf250/u-boot.lds b/board/cerf250/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/cerf250/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile
new file mode 100755
index 0000000..c66dd71
--- /dev/null
+++ b/board/cm4008/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cm4008.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c
new file mode 100755
index 0000000..4d2013b
--- /dev/null
+++ b/board/cm4008/cm4008.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of CM4008 */
+	gd->bd->bi_arch_number = 624;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/board/cm4008/config.mk b/board/cm4008/config.mk
new file mode 100755
index 0000000..74eaeb0
--- /dev/null
+++ b/board/cm4008/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x00f00000
diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c
new file mode 100755
index 0000000..86c8e2a
--- /dev/null
+++ b/board/cm4008/flash.c
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/cm4008/u-boot.lds b/board/cm4008/u-boot.lds
new file mode 100755
index 0000000..ec09fa2
--- /dev/null
+++ b/board/cm4008/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile
new file mode 100755
index 0000000..f0d3451
--- /dev/null
+++ b/board/cm41xx/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cm41xx.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c
new file mode 100755
index 0000000..65eaa94
--- /dev/null
+++ b/board/cm41xx/cm41xx.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of CM41xx */
+	gd->bd->bi_arch_number = 672;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/board/cm41xx/config.mk b/board/cm41xx/config.mk
new file mode 100755
index 0000000..74eaeb0
--- /dev/null
+++ b/board/cm41xx/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x00f00000
diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c
new file mode 100755
index 0000000..86c8e2a
--- /dev/null
+++ b/board/cm41xx/flash.c
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/cm41xx/u-boot.lds b/board/cm41xx/u-boot.lds
new file mode 100755
index 0000000..ec09fa2
--- /dev/null
+++ b/board/cm41xx/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile
new file mode 100755
index 0000000..d0def05
--- /dev/null
+++ b/board/cmc_pu2/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cmc_pu2/at45.c b/board/cmc_pu2/at45.c
new file mode 100755
index 0000000..3c00132
--- /dev/null
+++ b/board/cmc_pu2/at45.c
@@ -0,0 +1,621 @@
+/* Driver for ATMEL DataFlash support
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_HAS_DATAFLASH
+#include <dataflash.h>
+
+#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
+the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS	(0xC << 16)
+#define DATAFLASH_TCHS	(0x1 << 24)
+
+#define AT91C_TIMEOUT_WRDY			200000
+#define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
+#define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
+
+void AT91F_SpiInit(void) {
+
+/*-------------------------------------------------------------------*/
+/*	SPI DataFlash Init								*/
+/*-------------------------------------------------------------------*/
+	/* Configure PIOs */
+	AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+	AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
+				   AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
+	/* Enable CLock */
+	AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
+
+	/* Reset the SPI */
+	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
+
+	/* Configure SPI in Master Mode with No CS selected !!! */
+	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+
+	/* Configure CS0 and CS3 */
+	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+
+}
+
+void AT91F_SpiEnable(int cs) {
+	switch(cs) {
+	case 0:	/* Configure SPI CS0 for Serial DataFlash AT45DBxx */
+		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
+		break;
+	case 3:	/* Configure SPI CS3 for Serial DataFlash Card */
+		/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
+		AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7;	/* Set in PIO mode */
+		AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7;	/* Configure in output */
+		/* Clear Output */
+		AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
+		/* Configure PCS */
+		AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
+		AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+		break;
+	}
+
+	/* SPI_Enable */
+	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+/*----------------------------------------------------------------------------*/
+/* \fn    AT91F_SpiWrite						      */
+/* \brief Set the PDC registers for a transfert				      */
+/*----------------------------------------------------------------------------*/
+unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
+{
+	unsigned int timeout;
+
+	pDesc->state = BUSY;
+
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+
+	/* Initialize the Transmit and Receive Pointer */
+	AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
+	AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
+
+	/* Intialize the Transmit and Receive Counters */
+	AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
+	AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
+
+	if ( pDesc->tx_data_size != 0 ) {
+		/* Initialize the Next Transmit and Next Receive Pointer */
+		AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
+		AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
+
+		/* Intialize the Next Transmit and Next Receive Counters */
+		AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
+		AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
+	}
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+	timeout = 0;
+
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
+	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
+	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+	pDesc->state = IDLE;
+
+	if (timeout >= CFG_SPI_WRITE_TOUT){
+		printf("Error Timeout\n\r");
+		return DATAFLASH_ERROR;
+	}
+
+	return DATAFLASH_OK;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashSendCommand					*/
+/* \brief Generic function to send a command to the dataflash		*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char OpCode,
+	unsigned int CmdSize,
+	unsigned int DataflashAddress)
+{
+    unsigned int adr;
+
+	if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* process the address to obtain page address and byte address */
+	adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
+
+	/* fill the  command  buffer */
+	pDataFlash->pDataFlashDesc->command[0] = OpCode;
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
+		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
+		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
+		pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
+	} else {
+		pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
+		pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
+		pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
+		pDataFlash->pDataFlashDesc->command[4] = 0;
+	}
+	pDataFlash->pDataFlashDesc->command[5] = 0;
+	pDataFlash->pDataFlashDesc->command[6] = 0;
+	pDataFlash->pDataFlashDesc->command[7] = 0;
+
+	/* Initialize the SpiData structure for the spi write fuction */
+	pDataFlash->pDataFlashDesc->tx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->tx_cmd_size =  CmdSize ;
+	pDataFlash->pDataFlashDesc->rx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->rx_cmd_size =  CmdSize ;
+
+	/* send the command and read the data */
+	return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashGetStatus					*/
+/* \brief Read the status register of the dataflash			*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
+{
+	AT91S_DataFlashStatus status;
+
+	/* if a transfert is in progress ==> return 0 */
+	if( (pDesc->state) != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* first send the read status command (D7H) */
+	pDesc->command[0] = DB_STATUS;
+	pDesc->command[1] = 0;
+
+	pDesc->DataFlash_state  = GET_STATUS;
+	pDesc->tx_data_size 	= 0 ;	/* Transmit the command and receive response */
+	pDesc->tx_cmd_pt 		= pDesc->command ;
+	pDesc->rx_cmd_pt 		= pDesc->command ;
+	pDesc->rx_cmd_size 		= 2 ;
+	pDesc->tx_cmd_size 		= 2 ;
+	status = AT91F_SpiWrite (pDesc);
+
+	pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
+
+	return status;
+}
+
+
+/*----------------------------------------------------------------------*/
+/* \fn    AT91F_DataFlashWaitReady					*/
+/* \brief wait for dataflash ready (bit7 of the status register == 1)	*/
+/*----------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
+{
+	pDataFlashDesc->DataFlash_state = IDLE;
+
+	do {
+		AT91F_DataFlashGetStatus(pDataFlashDesc);
+		timeout--;
+	} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
+
+	if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
+		return DATAFLASH_ERROR;
+
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashContinuousRead 				*/
+/* Object              : Continuous stream Read 				*/
+/* Input Parameters    : DataFlash Service					*/
+/*						: <src> = dataflash address	*/
+/*                     : <*dataBuffer> = data buffer pointer			*/
+/*                     : <sizeToRead> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
+	AT91PS_DataFlash pDataFlash,
+	int src,
+	unsigned char *dataBuffer,
+	int sizeToRead )
+{
+	AT91S_DataFlashStatus status;
+	/* Test the size to read in the device */
+	if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+		return DATAFLASH_MEMORY_OVERFLOW;
+
+	pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
+	pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
+	pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
+
+	status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
+	/* Send the command to the dataflash */
+	return(status);
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashPagePgmBuf				*/
+/* Object              : Main memory page program through buffer 1 or buffer 2	*/
+/* Input Parameters    : DataFlash Service					*/
+/*						: <*src> = Source buffer	*/
+/*                     : <dest> = dataflash destination address			*/
+/*                     : <SizeToWrite> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	unsigned int dest,
+	unsigned int SizeToWrite)
+{
+	int cmdsize;
+	pDataFlash->pDataFlashDesc->tx_data_pt = src ;
+	pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
+	pDataFlash->pDataFlashDesc->rx_data_pt = src;
+	pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
+
+	cmdsize = 4;
+	/* Send the command to the dataflash */
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_MainMemoryToBufferTransfert			*/
+/* Object              : Read a page in the SRAM Buffer 1 or 2			*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned int page)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
+		return DATAFLASH_BAD_COMMAND;
+
+	/* no data to transmit or receive */
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*----------------------------------------------------------------------------- */
+/* Function Name       : AT91F_DataFlashWriteBuffer				*/
+/* Object              : Write data to the internal sram buffer 1 or 2		*/
+/* Input Parameters    : DataFlash Service					*/
+/*			: <BufferCommand> = command to write buffer1 or buffer2	*/
+/*                     : <*dataBuffer> = data buffer to write			*/
+/*                     : <bufferAddress> = address in the internal buffer	*/
+/*                     : <SizeToWrite> = data buffer size			*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned char *dataBuffer,
+	unsigned int bufferAddress,
+	int SizeToWrite )
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
+		return DATAFLASH_BAD_COMMAND;
+
+	/* buffer address must be lower than page size */
+	if (bufferAddress > pDataFlash->pDevice->pages_size)
+		return DATAFLASH_BAD_ADDRESS;
+
+	if ( (pDataFlash->pDataFlashDesc->state)  != IDLE)
+		return DATAFLASH_BUSY;
+
+	/* Send first Write Command */
+	pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
+	pDataFlash->pDataFlashDesc->command[1] = 0;
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+	    	pDataFlash->pDataFlashDesc->command[2] = 0;
+	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
+	    	pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
+		cmdsize = 5;
+	} else {
+	    	pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;
+	    	pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;
+	    	pDataFlash->pDataFlashDesc->command[4] = 0;
+		cmdsize = 4;
+	}
+
+	pDataFlash->pDataFlashDesc->tx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
+	pDataFlash->pDataFlashDesc->rx_cmd_pt 	 = pDataFlash->pDataFlashDesc->command ;
+	pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
+
+	pDataFlash->pDataFlashDesc->rx_data_pt 	= dataBuffer ;
+	pDataFlash->pDataFlashDesc->tx_data_pt 	= dataBuffer ;
+	pDataFlash->pDataFlashDesc->rx_data_size 	= SizeToWrite ;
+	pDataFlash->pDataFlashDesc->tx_data_size 	= SizeToWrite ;
+
+	return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_PageErase                                        */
+/* Object              : Erase a page 						*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PageErase(
+	AT91PS_DataFlash pDataFlash,
+	unsigned int page)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	/* no data to transmit or receive */
+    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_BlockErase                                       */
+/* Object              : Erase a Block 						*/
+/* Input Parameters    : DataFlash Service					*/
+/*                     : Page concerned						*/
+/*                     : 							*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_BlockErase(
+	AT91PS_DataFlash pDataFlash,
+	unsigned int block)
+{
+	int cmdsize;
+	/* Test if the buffer command is legal */
+	/* no data to transmit or receive */
+    	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
+}
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_WriteBufferToMain				*/
+/* Object              : Write buffer to the main memory			*/
+/* Input Parameters    : DataFlash Service					*/
+/*		: <BufferCommand> = command to send to buffer1 or buffer2	*/
+/*                     : <dest> = main memory address				*/
+/* Return value		: State of the dataflash				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_WriteBufferToMain (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char BufferCommand,
+	unsigned int dest )
+{
+	int cmdsize;
+	/* Test if the buffer command is correct */
+	if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
+	    (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
+	    (BufferCommand != DB_BUF2_PAGE_PGM) &&
+	    (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
+		return DATAFLASH_BAD_COMMAND;
+
+	/* no data to transmit or receive */
+	pDataFlash->pDataFlashDesc->tx_data_size = 0;
+
+	cmdsize = 4;
+	if (pDataFlash->pDevice->pages_number >= 16384)
+		cmdsize = 5;
+	/* Send the command to the dataflash */
+	return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_PartialPageWrite					*/
+/* Object              : Erase partielly a page					*/
+/* Input Parameters    : <page> = page number					*/
+/*			: <AdrInpage> = adr to begin the fading			*/
+/*                     : <length> = Number of bytes to erase			*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_PartialPageWrite (
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	unsigned int dest,
+	unsigned int size)
+{
+	unsigned int page;
+	unsigned int AdrInPage;
+
+	page = dest / (pDataFlash->pDevice->pages_size);
+	AdrInPage = dest % (pDataFlash->pDevice->pages_size);
+
+	/* Read the contents of the page in the Sram Buffer */
+	AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
+	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	/*Update the SRAM buffer */
+	AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
+
+	AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+	/* Erase page if a 128 Mbits device */
+	if (pDataFlash->pDevice->pages_number >= 16384) {
+		AT91F_PageErase(pDataFlash, page);
+		/* Rewrite the modified Sram Buffer in the main memory */
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	}
+
+	/* Rewrite the modified Sram Buffer in the main memory */
+	return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashWrite					*/
+/* Object              :							*/
+/* Input Parameters    : <*src> = Source buffer					*/
+/*                     : <dest> = dataflash adress				*/
+/*                     : <size> = data buffer size				*/
+/*------------------------------------------------------------------------------*/
+AT91S_DataFlashStatus AT91F_DataFlashWrite(
+	AT91PS_DataFlash pDataFlash,
+	unsigned char *src,
+	int dest,
+	int size )
+{
+	unsigned int length;
+	unsigned int page;
+	unsigned int status;
+
+	AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+	if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+		return DATAFLASH_MEMORY_OVERFLOW;
+
+	/* If destination does not fit a page start address */
+	if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size)))  != 0 ) {
+		length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
+
+		if (size < length)
+			length = size;
+
+		if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		/* Update size, source and destination pointers */
+		size -= length;
+		dest += length;
+		src += length;
+	}
+
+	while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+		/* program dataflash page */
+		page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
+
+		status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		status = AT91F_PageErase(pDataFlash, page);
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+		if (!status)
+			return DATAFLASH_ERROR;
+
+		status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
+		if(!status)
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+
+		/* Update size, source and destination pointers */
+		size -= pDataFlash->pDevice->pages_size ;
+		dest += pDataFlash->pDevice->pages_size ;
+		src  += pDataFlash->pDevice->pages_size ;
+	}
+
+	/* If still some bytes to read */
+	if ( size > 0 ) {
+		/* program dataflash page */
+		if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
+			return DATAFLASH_ERROR;
+
+		AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
+	}
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataFlashRead 					*/
+/* Object              : Read a block in dataflash				*/
+/* Input Parameters    : 							*/
+/* Return value		: 							*/
+/*------------------------------------------------------------------------------*/
+int AT91F_DataFlashRead(
+	AT91PS_DataFlash pDataFlash,
+	unsigned long addr,
+	unsigned long size,
+	char *buffer)
+{
+	unsigned long SizeToRead;
+
+	AT91F_SpiEnable(pDataFlash->pDevice->cs);
+
+	if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+		return -1;
+
+	while (size) {
+		SizeToRead = (size < 0x8000)? size:0x8000;
+
+		if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
+			return -1;
+
+		if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
+			return -1;
+
+		size -= SizeToRead;
+		addr += SizeToRead;
+		buffer += SizeToRead;
+	}
+
+	return DATAFLASH_OK;
+}
+
+
+/*------------------------------------------------------------------------------*/
+/* Function Name       : AT91F_DataflashProbe 					*/
+/* Object              : 							*/
+/* Input Parameters    : 							*/
+/* Return value	       : Dataflash status register				*/
+/*------------------------------------------------------------------------------*/
+int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
+{
+	AT91F_SpiEnable(cs);
+	AT91F_DataFlashGetStatus(pDesc);
+	return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+}
+
+#endif
diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c
new file mode 100755
index 0000000..14168e6
--- /dev/null
+++ b/board/cmc_pu2/cmc_pu2.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn
+ * (2004) garyj@denx.de
+ *
+ * Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mach-types.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#define CMC_HP_BASIC	1
+#define CMC_PU2		2
+#define CMC_BASIC	4
+
+int hw_detect (void);
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	AT91PS_PIO piob = AT91C_BASE_PIOB;
+	AT91PS_PIO pioc = AT91C_BASE_PIOC;
+
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* Correct IRDA resistor problem */
+	/* Set PA23_TXD in Output */
+	/* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
+	/*
+	 * configure PC0-PC3 as input without pull ups, so RS485 driver enable
+	 * (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated.
+	 */
+	pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
+	pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
+	pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+	        	AT91C_PIO_PC2 | AT91C_PIO_PC3;
+
+	/*
+	 * On CMC-PU2 board configure PB3-PB6 to input without pull ups to
+	 * clear the duo LEDs (the external pull downs assure a proper
+	 * signal). On CMC-BASIC and CMC-HP-BASIC set PB3-PB6 to output and
+	 * drive it high, to configure current measurement on AINx.
+	 */
+	if (hw_detect() & CMC_PU2) {
+		piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	}
+	else if ((hw_detect() & CMC_BASIC) || (hw_detect() & CMC_HP_BASIC)) {
+		piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+		piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	}
+	piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+			AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+			AT91C_PIO_PB5 | AT91C_PIO_PB6;
+
+	/*
+	 * arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in
+	 * the linuxarm kernel, yet.
+	 */
+	/* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */
+	gd->bd->bi_arch_number = 251;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+int checkboard (void)
+{
+	if (hw_detect() & CMC_PU2)
+		puts ("Board: CMC-PU2 (Rittal GmbH)\n");
+	else if (hw_detect() & CMC_BASIC)
+		puts ("Board: CMC-BASIC (Rittal GmbH)\n");
+	else if (hw_detect() & CMC_HP_BASIC)
+		puts ("Board: CMC-HP-BASIC (Rittal GmbH)\n");
+	else
+		puts ("Board: unknown\n");
+	return 0;
+}
+
+int hw_detect (void)
+{
+	AT91PS_PIO pio = AT91C_BASE_PIOB;
+
+	/* PIOB clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+
+	/* configure PB12 as input without pull up */
+	pio->PIO_ODR = AT91C_PIO_PB12;
+	pio->PIO_PPUDR = AT91C_PIO_PB12;
+	pio->PIO_PER = AT91C_PIO_PB12;
+
+	/* configure PB13 as input without pull up */
+	pio->PIO_ODR = AT91C_PIO_PB13;
+	pio->PIO_PPUDR = AT91C_PIO_PB13;
+	pio->PIO_PER = AT91C_PIO_PB13;
+
+	/* read board identification pin */
+	if (pio->PIO_PDSR & AT91C_PIO_PB12)
+		return ((pio->PIO_PDSR & AT91C_PIO_PB13)
+			? CMC_PU2 : 0);
+	else
+		return ((pio->PIO_PDSR & AT91C_PIO_PB13)
+			? CMC_HP_BASIC : CMC_BASIC);
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/board/cmc_pu2/config.mk b/board/cmc_pu2/config.mk
new file mode 100755
index 0000000..7116eea
--- /dev/null
+++ b/board/cmc_pu2/config.mk
@@ -0,0 +1,3 @@
+TEXT_BASE = 0x20F00000
+## For testing: load at 0x20100000 and "go" at 0x201000A4
+#TEXT_BASE = 0x20100000
diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c
new file mode 100755
index 0000000..9983c7b
--- /dev/null
+++ b/board/cmc_pu2/flash.c
@@ -0,0 +1,468 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn
+ * garyj@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifndef	CFG_ENV_ADDR
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02AA
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_short *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, vu_short *dest, ushort data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	ulong flashbase = CFG_FLASH_BASE;
+
+	/* Init: no FLASHes known */
+	memset(&flash_info[0], 0, sizeof(flash_info_t));
+
+	flash_info[0].size = flash_get_size((vu_short *)flashbase, &flash_info[0]);
+
+	size = flash_info[0].size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	vu_short *base = (vu_short *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = 0x00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = 0x00F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	info = NULL;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size && info->start[0] <= base &&
+		    base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_S29GL064M:
+		printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (vu_short *addr, flash_info_t *info)
+{
+	int i;
+	ushort value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command sequence */
+	addr[FLASH_CYCLE1] = 0x00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = 0x0055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = 0x0090;	/* selects Intel or AMD */
+
+	/* read Manufacturer ID */
+	udelay(100);
+	value = addr[0];
+	debug ("Manufacturer ID: %04X\n", value);
+
+	switch (value) {
+
+	case (AMD_MANUFACT & 0xFFFF):
+		debug ("Manufacturer: AMD (Spansion)\n");
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (INTEL_MANUFACT & 0xFFFF):
+		debug ("Manufacturer: Intel (not supported yet)\n");
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		printf ("Unknown Manufacturer ID: %04X\n", value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		goto out;
+	}
+
+	value = addr[1];
+	debug ("Device ID: %04X\n", value);
+
+	switch (addr[1]) {
+
+	case (AMD_ID_MIRROR & 0xFFFF):
+		debug ("Mirror Bit flash: addr[14] = %08X  addr[15] = %08X\n",
+			addr[14], addr[15]);
+
+		switch(addr[14]) {
+		case (AMD_ID_GL064M_2 & 0xFFFF):
+			if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) {
+				printf ("Chip: S29GLxxxM -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+				info->sector_count = 0;
+				info->size = 0;
+			} else {
+				debug ("Chip: S29GL064M-R6\n");
+				info->flash_id += FLASH_S29GL064M;
+				info->sector_count = 128;
+				info->size = 0x00800000;
+				for (i = 0; i < info->sector_count; i++) {
+					info->start[i] = base;
+					base += 0x10000;
+				}
+			}
+			break;	/* => 16 MB	*/
+		default:
+			printf ("Chip: *** unknown ***\n");
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+		}
+		break;
+
+	default:
+		printf ("Unknown Device ID: %04X\n", value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+out:
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr = (vu_short *)(info->start[0]);
+	int flag, prot, sect, ssect, l_sect;
+	ulong now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/*
+	 * Start erase on unprotected sectors.
+	 * Since the flash can erase multiple sectors with one command
+	 * we take advantage of that by doing the erase in chunks of
+	 * 3 sectors.
+	 */
+	for (sect = s_first; sect <= s_last; ) {
+		l_sect = -1;
+
+		addr[FLASH_CYCLE1] = 0x00AA;
+		addr[FLASH_CYCLE2] = 0x0055;
+		addr[FLASH_CYCLE1] = 0x0080;
+		addr[FLASH_CYCLE1] = 0x00AA;
+		addr[FLASH_CYCLE2] = 0x0055;
+
+		/* do the erase in chunks of at most 3 sectors */
+		for (ssect = 0; ssect < 3; ssect++) {
+			if ((sect + ssect) > s_last)
+				break;
+			if (info->protect[sect + ssect] == 0) {	/* not protected */
+				addr = (vu_short *)(info->start[sect + ssect]);
+				addr[0] = 0x0030;
+				l_sect = sect + ssect;
+			}
+		}
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		reset_timer_masked ();
+		last  = 0;
+		addr = (vu_short *)(info->start[l_sect]);
+		while ((addr[0] & 0x0080) != 0x0080) {
+			if ((now = get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+		addr = (vu_short *)info->start[0];
+		addr[0] = 0x00F0;	/* reset bank */
+		sect += ssect;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_short *)info->start[0];
+	addr[0] = 0x00F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	};
+
+	if ((int) src & 1) {
+		printf ("unaligned source not supported\n");
+		return ERR_ALIGN;
+	};
+
+	wp = addr;
+
+	while (cnt >= 2) {
+		data = *((vu_short *)src);
+		if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) {
+printf ("write_buff 1: write_word_amd() rc=%d\n", rc);
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (ERR_OK);
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << 8);
+		if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) {
+printf ("write_buff 1: write_word_amd() rc=%d\n", rc);
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data)
+{
+	int flag;
+	vu_short *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (vu_short *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
+	base[FLASH_CYCLE2] = 0x0055;	/* unlock */
+	base[FLASH_CYCLE1] = 0x00A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	reset_timer_masked ();
+
+	/* data polling for D7 */
+	while ((*dest & 0x0080) != (data & 0x0080)) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*dest = 0x00F0;	/* reset bank */
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c
new file mode 100755
index 0000000..94aa30d
--- /dev/null
+++ b/board/cmc_pu2/load_sernum_ethaddr.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+
+#define I2C_CHIP	0x50	/* I2C bus address of onboard EEPROM */
+#define I2C_ALEN	1	/* length of EEPROM addresses in bytes */
+#define I2C_OFFSET	0x0	/* start address of manufacturere data block
+				 * in EEPROM */
+
+/* 64 Byte manufacturer data block in EEPROM */
+struct manufacturer_data {
+	unsigned int	serial_number;	/* serial number (0...999999) */
+	unsigned short	hardware;	/* hardware version (e.g. V1.02) */
+	unsigned short	manuf_date;	/* manufacture date (e.g. 25/02) */
+	unsigned char	name[20];	/* device name (in CHIP.INI) */
+	unsigned char	macadr[6];	/* MAC address */
+	signed char	a_kal[4];	/* calibration value for U */
+	signed char	i_kal[4];	/* calibration value for I */
+	unsigned char	reserve[18];	/* reserved */
+	unsigned short	save_nr;	/* save count */
+	unsigned short	chksum;		/* checksum */
+};
+
+
+int i2c_read (unsigned char chip, unsigned int addr, int alen,
+	      unsigned char *buffer, int len);
+
+/*-----------------------------------------------------------------------
+ * Process manufacturer data block in EEPROM:
+ *
+ * If we boot on a system fresh from factory, check if the manufacturer data
+ * in the EEPROM is valid and save some information it contains.
+ *
+ * CMC manufacturer data is defined as follows:
+ *
+ * - located in the onboard EEPROM
+ * - starts at offset 0x0
+ * - size 0x00000040
+ *
+ * Internal structure: see struct definition
+ */
+
+void load_sernum_ethaddr (void)
+{
+	struct manufacturer_data data;
+	unsigned char  serial [9];
+	unsigned char  ethaddr[18];
+	unsigned short chksum;
+	unsigned char *p;
+	unsigned short i, is, id;
+
+#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C)
+#error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C)
+#endif
+	if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data,
+		     sizeof(data)) != 0) {
+		puts ("Error reading manufacturer data from EEPROM\n");
+		return;
+	}
+
+	/* check if manufacturer data block is valid  */
+	p = (unsigned char *)&data;
+	chksum = 0;
+	for (i = 0; i < (sizeof(data) - sizeof(data.chksum)); i++)
+		chksum += *p++;
+
+	debug ("checksum of manufacturer data block: %#.4x\n", chksum);
+
+	if (chksum != data.chksum) {
+		puts ("Error: manufacturer data block has invalid checksum\n");
+		return;
+	}
+
+	/* copy MAC address */
+	is = 0;
+	id = 0;
+	for (i = 0; i < 6; i++) {
+		sprintf (&ethaddr[id], "%02x", data.macadr[is++]);
+		id += 2;
+		if (is < 6)
+			ethaddr[id++] = ':';
+	}
+	ethaddr[id] = '\0';	/* just to be sure */
+
+	/* copy serial number */
+	sprintf (serial, "%d", data.serial_number);
+
+	/* set serial# and ethaddr if not yet defined */
+	if (getenv("serial#") == NULL) {
+		setenv ("serial#", serial);
+	}
+
+	if (getenv("ethaddr") == NULL) {
+		setenv ("ethaddr", ethaddr);
+	}
+}
diff --git a/board/cmc_pu2/u-boot.lds b/board/cmc_pu2/u-boot.lds
new file mode 100755
index 0000000..f4fbf96
--- /dev/null
+++ b/board/cmc_pu2/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/cmi/Makefile b/board/cmi/Makefile
new file mode 100755
index 0000000..2324d87
--- /dev/null
+++ b/board/cmi/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2001	Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= flash.o cmi.o
+SOBJS	:=
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c
new file mode 100755
index 0000000..cbf34f7
--- /dev/null
+++ b/board/cmi/cmi.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * File:		cmi.c
+ *
+ * Discription:		For generic board specific functions
+ *
+ */
+
+
+#include <common.h>
+#include <mpc5xx.h>
+
+#define SRAM_SIZE	1024000L	/* 1M RAM available*/
+
+#if defined(__APPLE__)
+/* Leading underscore on symbols */
+#  define SYM_CHAR "_"
+#else /* No leading character on symbols */
+#  define SYM_CHAR
+#endif
+
+/*
+ * Macros to generate global absolutes.
+ */
+#define GEN_SYMNAME(str) SYM_CHAR #str
+#define GEN_VALUE(str) #str
+#define GEN_ABS(name, value) \
+		asm (".globl " GEN_SYMNAME(name)); \
+		asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+
+/*
+ * Check the board
+ */
+int checkboard(void)
+{
+    puts ("Board: ### No HW ID - assuming CMI board\n");
+    return (0);
+}
+
+/*
+ * Get RAM size.
+ */
+long int initdram(int board_type)
+{
+	return (SRAM_SIZE);		/* We currently have a static size adapted for cmi board. */
+}
+
+/*
+ * Absolute environment address for linker file.
+ */
+GEN_ABS(env_start, CFG_ENV_OFFSET + CFG_FLASH_BASE);
diff --git a/board/cmi/config.mk b/board/cmi/config.mk
new file mode 100755
index 0000000..564f638
--- /dev/null
+++ b/board/cmi/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003
+# Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EPQ Board Configuration
+#
+
+# Boot from flash at location 0x00000000
+TEXT_BASE = 0x02000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/cmi/flash.c b/board/cmi/flash.c
new file mode 100755
index 0000000..f7c25f4
--- /dev/null
+++ b/board/cmi/flash.c
@@ -0,0 +1,517 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * File:		flash.c
+ *
+ * Discription:		This Driver is for 28F320J3A, 28F640J3A and
+ * 			28F128J3A Intel flashs working in 16 Bit mode.
+ *			They are single bank flashs.
+ *
+ *			Most of this code is taken from existing u-boot
+ *			source code.
+ */
+
+
+#include <common.h>
+#include <mpc5xx.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#define	FLASH_ID_MASK			0xFFFF
+#define FLASH_BLOCK_SIZE		0x00010000
+#define FLASH_CMD_READ_ID		0x0090
+#define FLASH_CMD_RESET			0x00ff
+#define FLASH_CMD_BLOCK_ERASE		0x0020
+#define FLASH_CMD_ERASE_CONFIRM		0x00D0
+#define FLASH_CMD_CLEAR_STATUS		0x0050
+#define FLASH_CMD_SUSPEND_ERASE		0x00B0
+#define FLASH_CMD_WRITE			0x0040
+#define FLASH_CMD_PROTECT		0x0060
+#define FLASH_CMD_PROTECT_SET		0x0001
+#define FLASH_CMD_PROTECT_CLEAR		0x00D0
+#define FLASH_STATUS_DONE		0x0080
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+
+/*
+ * Local function prototypes
+ */
+static ulong 	flash_get_size 		(vu_short *addr, flash_info_t *info);
+static int 	write_short 		(flash_info_t *info, ulong dest, ushort data);
+static void 	flash_get_offsets 	(ulong base, flash_info_t *info);
+
+/*
+ * Initialize flash
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+#if 1
+	debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+#endif
+	size_b0 = flash_get_size((vu_short *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	return size_b0;
+}
+
+/*
+ * Compute start adress of each sector (block)
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+	    for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base + i * FLASH_BLOCK_SIZE;
+	    }
+	    return;
+
+	default:
+	    printf ("Don't know sector offsets for flash type 0x%lx\n",
+		info->flash_id);
+	    return;
+	}
+}
+
+/*
+ * Print flash information
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320J3A (32Mbit) 16-Bit\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640J3A (64Mbit) 16-Bit\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128J3A (128Mbit) 16-Bit\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * Get size of flash in bytes.
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_short *addr, flash_info_t *info)
+{
+	vu_short value;
+
+	/* Read Manufacturer ID */
+	addr[0] = FLASH_CMD_READ_ID;
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = FLASH_CMD_RESET;	/* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case (INTEL_ID_28F320J3A  & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* =>  32 MBit		*/
+
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 64 MBit		*/
+
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 128 MBit		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = FLASH_CMD_RESET;	/* restore read mode */
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = FLASH_CMD_RESET;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*
+ * Erase unprotected sectors
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *)(info->start[sect]);
+			unsigned long status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+#ifdef DEBUG
+			printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
+#endif
+
+			*addr = FLASH_CMD_CLEAR_STATUS;
+			*addr = FLASH_CMD_BLOCK_ERASE;
+			*addr = FLASH_CMD_ERASE_CONFIRM;
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf("Flash erase timeout at address %lx\n", info->start[sect]);
+					*addr = FLASH_CMD_SUSPEND_ERASE;
+					*addr = FLASH_CMD_RESET;
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+			*addr = FLASH_CMD_RESET;
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int i, rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+
+	while (cnt >= 2) {
+		data = 0;
+		for (i=0; i<2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_short(info, wp, data));
+
+}
+
+/*
+ * Write 16 bit (short) to flash
+ */
+
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	if (!(info->flash_id & FLASH_VENDMASK)) {
+		return 4;
+	}
+	*addr = FLASH_CMD_ERASE_CONFIRM;
+	*addr = FLASH_CMD_WRITE;
+
+	*((vu_short *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	/* wait for error or finish */
+	while(!(addr[0] & FLASH_STATUS_DONE)){
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			addr[0] = FLASH_CMD_RESET;
+			return (1);
+		}
+	}
+
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*
+ * Protects a flash sector
+ */
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	vu_short *addr = (vu_short*)(info->start[sector]);
+	ulong start;
+
+	*addr = FLASH_CMD_CLEAR_STATUS;
+	*addr = FLASH_CMD_PROTECT;
+
+	if(prot) {
+		*addr = FLASH_CMD_PROTECT_SET;
+	} else {
+		*addr = FLASH_CMD_PROTECT_CLEAR;
+	}
+
+	/* wait for error or finish */
+	start = get_timer (0);
+	while(!(addr[0] & FLASH_STATUS_DONE)){
+		if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+			printf("Flash protect timeout at address %lx\n",  info->start[sector]);
+			addr[0] = FLASH_CMD_RESET;
+			return (1);
+		}
+	}
+	/* Set software protect flag */
+	info->protect[sector] = prot;
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
diff --git a/board/cmi/u-boot.lds b/board/cmi/u-boot.lds
new file mode 100755
index 0000000..5b03fef
--- /dev/null
+++ b/board/cmi/u-boot.lds
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2001	Wolfgang Denk, DENX Software Engineering, wd@denx.de
+ * (C) Copyright 2003	Martin Winistoerfer, martinwinistoerfer@gmx.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc5xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+/*   . = env_start;
+	.ppcenv	:
+	{
+		common/environment.o (.ppcenv)
+	}
+*/
+}
diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile
new file mode 100755
index 0000000..e5d8446
--- /dev/null
+++ b/board/cobra5272/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/cobra5272/bdm/cobra5272_uboot.gdb b/board/cobra5272/bdm/cobra5272_uboot.gdb
new file mode 100755
index 0000000..61e778e
--- /dev/null
+++ b/board/cobra5272/bdm/cobra5272_uboot.gdb
@@ -0,0 +1,169 @@
+#
+# GDB Init script for the Coldfire 5272 processor.
+#
+# The main purpose of this script is to configure the 
+# DRAM controller so code can be loaded.
+#
+# This file was changed to suite the senTec COBRA5272 board.
+# 
+
+define addresses
+
+set $mbar  = 0x10000001
+set $scr   = $mbar - 1 + 0x004
+set $spr   = $mbar - 1 + 0x006
+set $pmr   = $mbar - 1 + 0x008
+set $apmr  = $mbar - 1 + 0x00e
+set $dir   = $mbar - 1 + 0x010
+set $icr1  = $mbar - 1 + 0x020
+set $icr2  = $mbar - 1 + 0x024
+set $icr3  = $mbar - 1 + 0x028
+set $icr4  = $mbar - 1 + 0x02c
+set $isr   = $mbar - 1 + 0x030
+set $pitr  = $mbar - 1 + 0x034
+set $piwr  = $mbar - 1 + 0x038
+set $pivr  = $mbar - 1 + 0x03f
+set $csbr0 = $mbar - 1 + 0x040
+set $csor0 = $mbar - 1 + 0x044
+set $csbr1 = $mbar - 1 + 0x048
+set $csor1 = $mbar - 1 + 0x04c
+set $csbr2 = $mbar - 1 + 0x050
+set $csor2 = $mbar - 1 + 0x054
+set $csbr3 = $mbar - 1 + 0x058
+set $csor3 = $mbar - 1 + 0x05c
+set $csbr4 = $mbar - 1 + 0x060
+set $csor4 = $mbar - 1 + 0x064
+set $csbr5 = $mbar - 1 + 0x068
+set $csor5 = $mbar - 1 + 0x06c
+set $csbr6 = $mbar - 1 + 0x070
+set $csor6 = $mbar - 1 + 0x074
+set $csbr7 = $mbar - 1 + 0x078
+set $csor7 = $mbar - 1 + 0x07c
+set $pacnt = $mbar - 1 + 0x080
+set $paddr = $mbar - 1 + 0x084
+set $padat = $mbar - 1 + 0x086
+set $pbcnt = $mbar - 1 + 0x088
+set $pbddr = $mbar - 1 + 0x08c
+set $pbdat = $mbar - 1 + 0x08e
+set $pcddr = $mbar - 1 + 0x094
+set $pcdat = $mbar - 1 + 0x096
+set $pdcnt = $mbar - 1 + 0x098
+set $sdcr  = $mbar - 1 + 0x180
+set $sdtr  = $mbar - 1 + 0x184
+set $wrrr  = $mbar - 1 + 0x280
+set $wirr  = $mbar - 1 + 0x283
+set $wcr   = $mbar - 1 + 0x288
+set $wer   = $mbar - 1 + 0x28c
+
+end
+
+
+#
+# Setup system configuration
+#
+define setup-sys
+set *((unsigned short *) $scr) = 0x0003
+set *((unsigned short *) $spr) = 0xffff
+set *((unsigned char *) $pivr) = 0x4f
+end
+
+
+#
+# Setup Chip Selects (as per Motorola M5272C3 board)
+#
+define setup-cs
+
+# CS0 -- FLASH
+set *((unsigned long *) $csbr0) = 0xffe00201
+set *((unsigned long *) $csor0) = 0xffe00014
+
+# CS1 -- external bus test
+set *((unsigned long *) $csbr1) = 0x0
+set *((unsigned long *) $csor1) = 0x0
+
+# CS2 -- Optional FSRAM
+set *((unsigned long *) $csbr2) = 0x30000001
+set *((unsigned long *) $csor2) = 0xfff80000
+
+# CS3 -- not used
+set *((unsigned long *) $csbr3) = 0x0
+set *((unsigned long *) $csor3) = 0x0
+
+# CS4 --  not used
+set *((unsigned long *) $csbr4) = 0x0
+set *((unsigned long *) $csor4) = 0x0
+
+# CS5 -- PLI socket0
+set *((unsigned long *) $csbr5) = 0x0
+set *((unsigned long *) $csor5) = 0x0
+
+# CS6 -- PLI socket1
+set *((unsigned long *) $csbr6) = 0x0
+set *((unsigned long *) $csor6) = 0x0
+
+# CS7 -- SDRAM
+set *((unsigned long *) $csbr7) = 0x00000701
+set *((unsigned long *) $csor7) = 0xff00007c
+
+end
+
+
+#
+# Setup the DRAM controller.
+#
+
+define setup-dram
+set *((unsigned long *) $sdtr) = 0x0000f539
+set *((unsigned long *) $sdcr) = 0x00004211
+
+# Dummy write to start SDRAM
+set *((unsigned long *) 0) = 0
+end
+
+
+#
+# Setup for GPIO pins
+#
+define setup-ppio
+
+# PORT A -- the LED's
+set *((unsigned long *) $pacnt) = 0x00000000
+# lower 8 bits for output:
+set *((unsigned short *) $paddr) = 0xff
+# LED's off:
+set *((unsigned short *) $padat) = 0xff
+
+# PORT B
+set *((unsigned long *) $pbcnt) = 0x55554155
+set *((unsigned short *) $pbddr) = 0x0000
+set *((unsigned short *) $pbdat) = 0x17ea
+
+# PORT C
+#set *((unsigned short *) $pcddr) = 0x0000
+#set *((unsigned short *) $pcdat) = 0x1898
+
+# PORT D
+set *((unsigned long *) $pdcnt) = 0x00000000
+
+end
+
+
+#
+#	Added for uClinux-coldfire target...
+#
+target bdm /dev/bdm
+
+addresses
+setup-sys
+setup-cs
+setup-dram
+setup-ppio
+set print pretty
+set print asm-demangle
+display/i $pc
+
+
+#
+load u-boot
+set $pc=0x20000
+c
diff --git a/board/cobra5272/bdm/gdbinit.reset b/board/cobra5272/bdm/gdbinit.reset
new file mode 100755
index 0000000..5f1e482
--- /dev/null
+++ b/board/cobra5272/bdm/gdbinit.reset
@@ -0,0 +1,2 @@
+target bdm /dev/bdmcf0
+q
diff --git a/board/cobra5272/bdm/load-cobra_uboot b/board/cobra5272/bdm/load-cobra_uboot
new file mode 100755
index 0000000..933c7e7
--- /dev/null
+++ b/board/cobra5272/bdm/load-cobra_uboot
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot
+
diff --git a/board/cobra5272/bdm/reset b/board/cobra5272/bdm/reset
new file mode 100755
index 0000000..8bef00b
--- /dev/null
+++ b/board/cobra5272/bdm/reset
@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset
+
diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c
new file mode 100755
index 0000000..26adb4a
--- /dev/null
+++ b/board/cobra5272/cobra5272.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5272.h>
+#include <asm/immap_5272.h>
+
+
+int checkboard (void)
+{
+	puts ("Board: ");
+	puts ("senTec COBRA5272 Board\n");
+	return 0;
+};
+
+long int initdram (int board_type)
+{
+	volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR);
+
+	sdp->sdram_sdtr = 0xf539;
+	sdp->sdram_sdcr = 0x4211;
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *) 0) = 0;
+
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/board/cobra5272/config.mk b/board/cobra5272/config.mk
new file mode 100755
index 0000000..ccb2cf7
--- /dev/null
+++ b/board/cobra5272/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xffe00000
diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
new file mode 100755
index 0000000..6f5874a
--- /dev/null
+++ b/board/cobra5272/flash.c
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_PL160CB & FLASH_TYPEMASK):
+		printf ("AM29PL160CB (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+}
+
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_PL160CB & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j == 0) {
+				/* 1st is 16 KiB */
+				flash_info[i].start[j] = flashbase;
+			}
+			if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x4000 + 0x2000 * (j - 1);
+			}
+			if (j == 3) {
+				/* 4th is 224 KiB */
+				flash_info[i].start[j] = flashbase + 0x8000;
+			}
+			if ((j >= 4) && (j <= 10)) {
+				/* rest is 256 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x40000 + 0x40000 * (j -
+									 4);
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + 0x3ffff, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		set_timer (0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds
new file mode 100755
index 0000000..872f094
--- /dev/null
+++ b/board/cobra5272/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+    cpu/mcf52x2/start.o		(.text)
+    cpu/mcf52x2/cpu_init.o	(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cogent/Makefile b/board/cogent/Makefile
new file mode 100755
index 0000000..4084c7e
--- /dev/null
+++ b/board/cogent/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o
+SOBJS	:=
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cogent/README b/board/cogent/README
new file mode 100755
index 0000000..e6eef66
--- /dev/null
+++ b/board/cogent/README
@@ -0,0 +1,118 @@
+Cogent Modular Architecture configuration
+-----------------------------------------
+
+As the name suggests, the Cogent platform is a modular system where
+you have a motherboard into which plugs a cpu module and one or more
+i/o modules. This provides very nice flexibility, but makes the
+configuration task somewhat harder.
+
+The possible Cogent motherboards are:
+
+Code		Config Variable		Description
+----		---------------		-----------
+
+CMA101		CONFIG_CMA101		32MB ram, 2 ser, 1 par, rtc, dipsw,
+					2x16 lcd, eth(?)
+CMA102		CONFIG_CMA102		32MB ram, 2 ser, 1 par, rtc, dipsw,
+					2x16 lcd
+CMA111		CONFIG_CMA111		32MB ram, 1MB flash, 4 ser, 1 par,
+					rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
+					10/100TP eth
+CMA120		CONFIG_CMA120		32MB ram, 1MB flash, 4 ser, 1 par,
+					rtc, ps/2 kbd/mse, 2x16 lcd, 2xPCI,
+					10/100TP eth, 2xPCMCIA, video/lcd-panel
+CMA150		CONFIG_CMA150		8MB ram, 1MB flash, 2 ser, 1 par, rtc,
+					ps/2 kbd/mse, 2x16 lcd
+
+The possible Cogent PowerPC CPU modules are:
+
+Code		Config Variable		Description
+----		---------------		-----------
+
+CMA278-603EV	CONFIG_CMA278_603EV	PPC603ev CPU, 66MHz clock, 512K EPROM,
+					JTAG/COP
+CMA278-603ER	CONFIG_CMA278_603ER	PPC603er CPU, 66MHz clock, 512K EPROM,
+					JTAG/COP
+CMA278-740	CONFIG_CMA278_740	PPC740 CPU, 66MHz clock, 512K EPROM,
+					JTAG/COP
+CMA280-509	CONFIG_CMA280_509	MPC505/509 CPU, 50MHz clock,
+					512K EPROM, BDM
+CMA282		CONFIG_CMA282		MPC8260 CPU, 66MHz clock, 512K EPROM,
+					JTAG, 16M RAM, 1 x ser (SMC2),
+					1 x 10baseT PHY (SCC4), 1 x 10/100 TP
+					PHY (FCC1), 2 x 48pin DIN (FCC2 + TDM1)
+CMA285		CONFIG_CMA285		MPC801 CPU, 33MHz clock, 512K EPROM,
+					BDM
+CMA286-21	CONFIG_CMA286_21	MPC821 CPU, 66MHz clock, 512K EPROM,
+					BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
+					1 x 10baseT PHY (SCC2)
+CMA286-60-OLD	CONFIG_CMA286_60_OLD	MPC860 CPU, 33MHz clock, 128K EPROM,
+					BDM
+CMA286-60	CONFIG_CMA286_60	MPC860 CPU, 66MHz clock, 512K EPROM,
+					BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
+					1 x 10baseT PHY (SCC2)
+CMA286-60P	CONFIG_CMA286_60P	MPC860P CPU, 66MHz clock, 512K EPROM,
+					BDM, 16M RAM, 2 x ser (SMC1 + SMC2),
+					1 x 10baseT PHY (SCC2)
+CMA287-23	CONFIG_CMA287_23	MPC823 CPU, 33MHz clock, 512K EPROM,
+					BDM
+CMA287-50	CONFIG_CMA287_50	MPC850 CPU, 33MHz clock, 512K EPROM,
+					BDM
+
+(there are a lot of other cpu modules with ARM, MIPS and M-CORE CPUs,
+but we'll worry about those later).
+
+The possible Cogent CMA I/O Modules are:
+
+Code		Config Variable		Description
+----		---------------		-----------
+
+CMA302		CONFIG_CMA302		up to 16M flash, ps/2 keyboard/mouse
+CMA352		CONFIG_CMA352		CMAbus <=> PCI
+
+Currently supported:
+
+	Motherboards:	CMA102
+	CPU Modules:	CMA286-60-OLD
+	I/O Modules:	CMA302 I/O module
+
+To configure, perform the usual U-Boot configuration task of editing
+"include/config_cogent_mpc8xx.h" and reviewing all the options and
+settings in there. In particular, check the chip select values
+installed into the memory controller's various option and base
+registers - these are set by the defines CFG_CMA_CSn_{BASE,SIZE} and
+CFG_{B,O}Rn_PRELIM. Also be careful of the clock settings installed
+into the SCCR - via the define CFG_SCCR. Finally, decide whether you
+want the serial console on motherboard serial port A or on one of the
+8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly
+(NONE means use Cogent motherboard serial port A).
+
+Then edit the file "cogent/config.mk". Firstly, set TEXT_BASE to be
+the base address of the EPROM for the CPU module. This should be the
+same as the value selected for CFG_MONITOR_BASE in
+"include/config_cogent_*.h" (in fact, I have made this automatic via
+the -DTEXT_BASE=... option in CPPFLAGS).
+
+Finally, set the values of the make variables $(CMA_MB) and $(CMA_IOMS).
+
+$(CMA_MB) is the name of the directory that contains support for your
+motherboard. At this stage, only "cma10x" exists, which supports the
+CMA101 and CMA102 motherboards - but only selected devices, namely
+serial, lcd and dipsw.
+
+$(CMA_IOMS) is a list of zero or more directories that contain
+support for the i/o modules you have installed. At this stage, only
+"cma302" exists, which supports the CMA302 flash i/o module - but
+only the flash part, not the ps/2 keyboard and mouse interfaces.
+
+There should be a make variable for each of the above directories,
+which is the directory name with "_O" appended. This make variable is
+a list of object files to compile from that directory and include in
+the library.
+
+	e.g. cma10x_O = serial.o ...
+
+That's it. Good Luck.
+
+Murray.Jensen@cmst.csiro.au
+August 31, 2000.
diff --git a/board/cogent/README.cma286 b/board/cogent/README.cma286
new file mode 100755
index 0000000..0345fea
--- /dev/null
+++ b/board/cogent/README.cma286
@@ -0,0 +1,69 @@
+CPU module revisions
+--------------------
+
+My cpu module has the model number "CMA286-60-990526-01". My motherboard
+has the model number "CMA102-32M-990526-01". These are both fairly old,
+and may not reflect current design. In particular, I can see from the
+Cogent web site that the CMA286 has been significantly redesigned - it
+now has on board RAM (4M), ethernet 10baseT PHY (on SCC2), 2 serial ports
+(SMC1 and SMC2), and 48pin DIN for the FEC (if present i.e. MPC860T), and
+also the EPROM is 512K.
+
+My CMA286-60 has none of this, and only 128K EPROM. In addition, the CPU
+clock is listed as 66MHz, whereas mine is 33.333MHz.
+
+Clocks
+------
+
+Quote from my "CMA286 MPC860/821 User's Manual":
+
+"When setting up the Periodic Interrupt Timer (PIT), be aware that the
+CMA286 places the MPC860/821 in PLL X1 Mode. This means that we feed
+a 25MHz clock directly into the MPC860/821. This mode sets the divisor
+for the PIT to be 512. In addition, the Time Base Register (TMB)
+divisor is set to 16."
+
+I interpreted this information to mean that EXTCLK is 25MHz and that at
+power on reset, MODCK1=1 and MODCK2=0, which selects EXTCLK as the
+source for OSCCLK and PITRTCLK, sets RTDIV to 512 and sets MF (the
+multiplication factor) to 1 (I assume this is what they mean by X1
+mode above). MF=1 means the cpus internal clock runs at the same
+rate as EXTCLK i.e. 25MHz.
+
+Furthermore, since SCCR[TBS] (the Time Base Source selector bit in the
+System Clock and Reset Control register) is set in the cpu initialisation
+code, the TMBCLK source is forced to be GCLK2 and the TMBCLK prescale is
+forced to be 16. This results in TMBCLK=1562500.
+
+One problem - since PITRTCLK source is EXTCLK (25Mhz) and RTDIV is 512,
+PITRTCLK will be 48828.125 (huh?). Another quote from the MPC860 Users
+Manual:
+
+"When used by the real-time clock (RTC), the PITRTCLK source is first
+divided as determined by RTDIV, and then divided in the RTC circuits by
+either 8192 or 9600. Therefore, in order for the RTC to count in
+seconds, the clock source must satisfy:
+
+	(EXTCLK or OSCM) / [(4 or 512) x (8192 or 9600)] = 1
+
+The RTC will operate with other frequencies, but it will not count in
+units of seconds."
+
+Therefore, the internal RTC of the MPC860 is not going to count in
+seconds, so we must use the motherboard RTC (if we need a RTC).
+
+I presume this means that they do not provide a fixed oscillator for
+OSCM. The code in get_gclk_freq() assumes PITRTCLK source is OSCM,
+RTDIV is 4, and that OSCM/4 is 8192 (i.e. a ~32KHz oscillator). Since
+the CMA286-60 doesn't have this (at least mine doesn't) we can't use
+the code in get_gclk_freq().
+
+Finally, it appears that the internal clock in my CMA286-60 is actually
+33.333MHz. Which makes TMBCLK=2083312.5 (another huh?) and
+PITRTCLK=65103.515625 (bloody hell!).
+
+If anyone finds anything wrong with the stuff above, I would appreciate
+an email about it.
+
+Murray Jensen <Murray.Jensen@csiro.au>
+21-Aug-00
diff --git a/board/cogent/config.mk b/board/cogent/config.mk
new file mode 100755
index 0000000..ee77939
--- /dev/null
+++ b/board/cogent/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Cogent Modular Architecture
+#
+
+# Boot EPROM location
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/cogent/dipsw.c b/board/cogent/dipsw.c
new file mode 100755
index 0000000..d2027c9
--- /dev/null
+++ b/board/cogent/dipsw.c
@@ -0,0 +1,50 @@
+#include <common.h>
+#include <board/cogent/dipsw.h>
+
+unsigned char
+dipsw_raw(void)
+{
+    return cma_mb_reg_read(&((cma_mb_dipsw *)CMA_MB_DIPSW_BASE)->dip_val);
+}
+
+unsigned char
+dipsw_cooked(void)
+{
+    unsigned char val1, val2, mask1, mask2;
+
+    val1 = dipsw_raw();
+
+    /*
+     * we want to mirror the bits because the low bit is switch 1 and high
+     * bit is switch 8 and also invert them because 1=off and 0=on, according
+     * to manual.
+     *
+     * this makes the value more intuitive i.e.
+     * - left most, or high, or top, bit is left most switch (1);
+     * - right most, or low, or bottom, bit is right most switch (8)
+     * - a set bit means "on" and a clear bit means "off"
+     */
+
+    val2 = 0;
+    for (mask1 = 1 << 7, mask2 = 1; mask1 > 0; mask1 >>= 1, mask2 <<= 1)
+	if ((val1 & mask1) == 0)
+	    val2 |= mask2;
+
+    return (val2);
+}
+
+void
+dipsw_init(void)
+{
+    unsigned char val, mask;
+
+    val = dipsw_cooked();
+
+    printf("|");
+    for (mask = 1 << 7; mask > 0; mask >>= 1)
+	if (val & mask)
+	    printf("on |");
+	else
+	    printf("off|");
+    printf("\n");
+}
diff --git a/board/cogent/dipsw.h b/board/cogent/dipsw.h
new file mode 100755
index 0000000..4f52fd4
--- /dev/null
+++ b/board/cogent/dipsw.h
@@ -0,0 +1,3 @@
+extern unsigned char dipsw_raw(void);
+extern unsigned char dipsw_cooked(void);
+extern void dipsw_init(void);
diff --git a/board/cogent/flash.c b/board/cogent/flash.c
new file mode 100755
index 0000000..969520d
--- /dev/null
+++ b/board/cogent/flash.c
@@ -0,0 +1,648 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <board/cogent/flash.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+
+#if defined(CONFIG_CMA302)
+
+/*
+ * probe for the existence of flash at address "addr"
+ * 0 = yes, 1 = bad Manufacturer's Id, 2 = bad Device Id
+ */
+static int
+c302f_probe_word(c302f_addr_t addr)
+{
+	/* reset the flash */
+	*addr = C302F_BNK_CMD_RST;
+
+	/* check the manufacturer id */
+	*addr = C302F_BNK_CMD_RD_ID;
+	if (*C302F_BNK_ADDR_MAN(addr) != C302F_BNK_RD_ID_MAN)
+		return 1;
+
+	/* check the device id */
+	*addr = C302F_BNK_CMD_RD_ID;
+	if (*C302F_BNK_ADDR_DEV(addr) != C302F_BNK_RD_ID_DEV)
+		return 2;
+
+#ifdef FLASH_DEBUG
+	{
+		int i;
+
+		printf("\nMaster Lock Config = 0x%08lx\n",
+			*C302F_BNK_ADDR_CFGM(addr));
+		for (i = 0; i < C302F_BNK_NBLOCKS; i++)
+			printf("Block %2d Lock Config = 0x%08lx\n",
+				i, *C302F_BNK_ADDR_CFG(i, addr));
+	}
+#endif
+
+	/* reset the flash again */
+	*addr = C302F_BNK_CMD_RST;
+
+	return 0;
+}
+
+/*
+ * probe for Cogent CMA302 flash module at address "base" and store
+ * info for any found into flash_info entry "fip". Must find at least
+ * one bank.
+ */
+static void
+c302f_probe(flash_info_t *fip, c302f_addr_t base)
+{
+	c302f_addr_t addr, eaddr;
+	int nbanks;
+
+	fip->size = 0L;
+	fip->sector_count = 0;
+
+	addr = base;
+	eaddr = C302F_BNK_ADDR_BASE(addr, C302F_MAX_BANKS);
+	nbanks = 0;
+
+	while (addr < eaddr) {
+		c302f_addr_t addrw, eaddrw, addrb;
+		int i, osc, nsc;
+
+		addrw = addr;
+		eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw);
+
+		while (addrw < eaddrw)
+			if (c302f_probe_word(addrw++) != 0)
+				goto out;
+
+		/* bank exists - append info for this bank to *fip */
+		fip->flash_id = FLASH_MAN_INTEL|FLASH_28F008S5;
+		fip->size += C302F_BNK_SIZE;
+		osc = fip->sector_count;
+		fip->sector_count += C302F_BNK_NBLOCKS;
+		if ((nsc = fip->sector_count) >= CFG_MAX_FLASH_SECT)
+			panic("Too many sectors in flash at address 0x%08lx\n",
+				(unsigned long)base);
+
+		addrb = addr;
+		for (i = osc; i < nsc; i++) {
+			fip->start[i] = (ulong)addrb;
+			fip->protect[i] = 0;
+			addrb = C302F_BNK_ADDR_NEXT_BLK(addrb);
+		}
+
+		addr = C302F_BNK_ADDR_NEXT_BNK(addr);
+		nbanks++;
+	}
+
+out:
+	if (nbanks == 0)
+		panic("ERROR: no flash found at address 0x%08lx\n",
+			(unsigned long)base);
+}
+
+static void
+c302f_reset(flash_info_t *info, int sect)
+{
+	c302f_addr_t addrw, eaddrw;
+
+	addrw = (c302f_addr_t)info->start[sect];
+	eaddrw = C302F_BNK_ADDR_NEXT_WORD(addrw);
+
+	while (addrw < eaddrw) {
+#ifdef FLASH_DEBUG
+		printf("  writing reset cmd to addr 0x%08lx\n",
+			(unsigned long)addrw);
+#endif
+		*addrw = C302F_BNK_CMD_RST;
+		addrw++;
+	}
+}
+
+static void
+c302f_erase_init(flash_info_t *info, int sect)
+{
+	c302f_addr_t addrw, saddrw, eaddrw;
+	int flag;
+
+#ifdef FLASH_DEBUG
+	printf("0x%08lx C302F_BNK_CMD_PROG\n", C302F_BNK_CMD_PROG);
+	printf("0x%08lx C302F_BNK_CMD_ERASE1\n", C302F_BNK_CMD_ERASE1);
+	printf("0x%08lx C302F_BNK_CMD_ERASE2\n", C302F_BNK_CMD_ERASE2);
+	printf("0x%08lx C302F_BNK_CMD_CLR_STAT\n", C302F_BNK_CMD_CLR_STAT);
+	printf("0x%08lx C302F_BNK_CMD_RST\n", C302F_BNK_CMD_RST);
+	printf("0x%08lx C302F_BNK_STAT_RDY\n", C302F_BNK_STAT_RDY);
+	printf("0x%08lx C302F_BNK_STAT_ERR\n", C302F_BNK_STAT_ERR);
+#endif
+
+	saddrw = (c302f_addr_t)info->start[sect];
+	eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw);
+
+#ifdef FLASH_DEBUG
+	printf("erasing sector %d, start addr = 0x%08lx "
+		"(bank next word addr = 0x%08lx)\n", sect,
+		(unsigned long)saddrw, (unsigned long)eaddrw);
+#endif
+
+	/* Disable intrs which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+#ifdef FLASH_DEBUG
+		printf("  writing erase cmd to addr 0x%08lx\n",
+			(unsigned long)addrw);
+#endif
+		*addrw = C302F_BNK_CMD_ERASE1;
+		*addrw = C302F_BNK_CMD_ERASE2;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+}
+
+static int
+c302f_erase_poll(flash_info_t *info, int sect)
+{
+	c302f_addr_t addrw, saddrw, eaddrw;
+	int sectdone, haderr;
+
+	saddrw = (c302f_addr_t)info->start[sect];
+	eaddrw = C302F_BNK_ADDR_NEXT_WORD(saddrw);
+
+	sectdone = 1;
+	haderr = 0;
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+		c302f_word_t stat = *addrw;
+
+#ifdef FLASH_DEBUG
+		printf("  checking status at addr "
+			"0x%08lx [0x%08lx]\n",
+			(unsigned long)addrw, stat);
+#endif
+		if ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY)
+			sectdone = 0;
+		else if ((stat & C302F_BNK_STAT_ERR) != 0) {
+			printf(" failed on sector %d "
+				"(stat = 0x%08lx) at "
+				"address 0x%08lx\n",
+				sect, stat,
+				(unsigned long)addrw);
+			*addrw = C302F_BNK_CMD_CLR_STAT;
+			haderr = 1;
+		}
+	}
+
+	if (haderr)
+		return (-1);
+	else
+		return (sectdone);
+}
+
+static int
+c302f_write_word(c302f_addr_t addr, c302f_word_t value)
+{
+	c302f_word_t stat;
+	ulong start;
+	int flag, retval;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = C302F_BNK_CMD_PROG;
+
+	*addr = value;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	retval = 0;
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	do {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			retval = 1;
+			goto done;
+		}
+		stat = *addr;
+	} while ((stat & C302F_BNK_STAT_RDY) != C302F_BNK_STAT_RDY);
+
+	if ((stat & C302F_BNK_STAT_ERR) != 0) {
+		printf("flash program failed (stat = 0x%08lx) "
+			"at address 0x%08lx\n", (ulong)stat, (ulong)addr);
+		*addr = C302F_BNK_CMD_CLR_STAT;
+		retval = 3;
+	}
+
+done:
+	/* reset to read mode */
+	*addr = C302F_BNK_CMD_RST;
+
+	return (retval);
+}
+
+#endif	/* CONFIG_CMA302 */
+
+unsigned long
+flash_init(void)
+{
+	unsigned long total;
+	int i;
+	flash_info_t *fip;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	fip = &flash_info[0];
+	total = 0L;
+
+#if defined(CONFIG_CMA302)
+	c302f_probe(fip, (c302f_addr_t)CFG_FLASH_BASE);
+	total += fip->size;
+	fip++;
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+	/* not yet ...
+	cmbf_probe(fip, (cmbf_addr_t)CMA_MB_FLASH_BASE);
+	total += fip->size;
+	fip++;
+	*/
+#endif
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE == CFG_FLASH_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return total;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F008S5:	printf ("28F008S5\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf (" %2d - %08lX%s", i,
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int prot, sect, haderr;
+	ulong start, now, last;
+	void (*erase_init)(flash_info_t *, int);
+	int (*erase_poll)(flash_info_t *, int);
+	void (*reset)(flash_info_t *, int);
+	int rcode = 0;
+
+#ifdef FLASH_DEBUG
+	printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+		(info - flash_info) + 1);
+	flash_print_info(info);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id) {
+
+#if defined(CONFIG_CMA302)
+	case FLASH_MAN_INTEL|FLASH_28F008S5:
+		erase_init = c302f_erase_init;
+		erase_poll = c302f_erase_poll;
+		reset = c302f_reset;
+		break;
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+	case FLASH_MAN_INTEL|FLASH_28F800_B:
+	case FLASH_MAN_AMD|FLASH_AM29F800B:
+		/* not yet ...
+		erase_init = cmbf_erase_init;
+		erase_poll = cmbf_erase_poll;
+		reset = cmbf_reset;
+		break;
+		*/
+#endif
+
+	default:
+		printf ("Flash type %08lx not supported - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sector%s will not be erased!\n",
+			prot, (prot > 1 ? "s" : ""));
+	}
+
+	start = get_timer (0);
+	last = 0;
+	haderr = 0;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			ulong estart;
+			int sectdone;
+
+			(*erase_init)(info, sect);
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			estart = get_timer(start);
+
+			do {
+				now = get_timer(start);
+
+				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout (sect %d)\n", sect);
+					haderr = 1;
+					break;
+				}
+
+#ifndef FLASH_DEBUG
+				/* show that we're waiting */
+				if ((now - last) > 1000) { /* every second */
+					putc ('.');
+					last = now;
+				}
+#endif
+
+				sectdone = (*erase_poll)(info, sect);
+
+				if (sectdone < 0) {
+					haderr = 1;
+					break;
+				}
+
+			} while (!sectdone);
+
+			if (haderr)
+				break;
+		}
+	}
+
+	if (haderr > 0) {
+		printf (" failed\n");
+	        rcode = 1;
+	}
+	else
+		printf (" done\n");
+
+	/* reset to read mode */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			(*reset)(info, sect);
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - write error
+ */
+
+int
+write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	ulong start, now, last;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	start = get_timer (0);
+	last = 0;
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+
+		/* show that we're waiting */
+		now = get_timer(start);
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - write error
+ */
+static int
+write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	int retval;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*(ulong *)dest & data) != data) {
+		return (2);
+	}
+
+	switch (info->flash_id) {
+
+#if defined(CONFIG_CMA302)
+	case FLASH_MAN_INTEL|FLASH_28F008S5:
+		retval = c302f_write_word((c302f_addr_t)dest, (c302f_word_t)data);
+		break;
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+	case FLASH_MAN_INTEL|FLASH_28F800_B:
+	case FLASH_MAN_AMD|FLASH_AM29F800B:
+		/* not yet ...
+		retval = cmbf_write_word((cmbf_addr_t)dest, (cmbf_word_t)data);
+		*/
+		retval = 3;
+		break;
+#endif
+
+	default:
+		printf ("Flash type %08lx not supported - aborted\n",
+			info->flash_id);
+		retval = 3;
+		break;
+	}
+
+	return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/cogent/flash.h b/board/cogent/flash.h
new file mode 100755
index 0000000..0b8d6aa
--- /dev/null
+++ b/board/cogent/flash.h
@@ -0,0 +1,305 @@
+/**************** DEFINES for Intel 28F008S5 FLASH chip **********************/
+
+/* register addresses, valid only following a I8S5_CMD_RD_ID command */
+#define I8S5_ADDR_MAN	0x00000	/* manufacturer's id */
+#define I8S5_ADDR_DEV	0x00001	/* device id */
+#define I8S5_ADDR_CFGM	0x00003	/* master lock configuration */
+#define I8S5_ADDR_CFG(b) (((b)<<16)|2) /* block lock configuration */
+
+/* Commands */
+#define I8S5_CMD_RST	0xFF	/* reset flash */
+#define I8S5_CMD_RD_ID	0x90	/* read the id and lock bits */
+#define I8S5_CMD_RD_STAT 0x70	/* read the status register */
+#define I8S5_CMD_CLR_STAT 0x50	/* clear the staus register */
+#define I8S5_CMD_ERASE1	0x20	/* first word for block erase */
+#define I8S5_CMD_ERASE2	0xD0	/* second word for block erase */
+#define I8S5_CMD_PROG	0x40	/* program word command */
+#define I8S5_CMD_LOCK	0x60	/* first word for all lock commands */
+#define I8S5_CMD_SET_LOCK_BLK 0x01 /* 2nd word for set block lock bit */
+#define I8S5_CMD_SET_LOCK_MSTR 0xF1 /* 2nd word for set master lock bit */
+#define I8S5_CMD_CLR_LOCK_BLK 0xD0 /* 2nd word for clear block lock bit */
+
+/* status register bits */
+#define I8S5_STAT_DPS	0x02	/* Device Protect Status */
+#define I8S5_STAT_PSS	0x04	/* Program Suspend Status */
+#define I8S5_STAT_VPPS	0x08	/* VPP Status */
+#define I8S5_STAT_PSLBS	0x10	/* Program and Set Lock Bit Status */
+#define I8S5_STAT_ECLBS	0x20	/* Erase and Clear Lock Bit Status */
+#define I8S5_STAT_ESS	0x40	/* Erase Suspend Status */
+#define I8S5_STAT_RDY	0x80	/* Write State Machine Status, 1=rdy */
+
+#define I8S5_STAT_ERR	(I8S5_STAT_VPPS | I8S5_STAT_DPS | \
+			    I8S5_STAT_ECLBS | I8S5_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define I8S5_RD_ID_LOCK	0x01	/* Bit 0 of each byte */
+#define I8S5_RD_ID_MAN	0x89	/* Manufacturer code = 0x89 */
+#define I8S5_RD_ID_DEV	0xA6	/* Device code = 0xA6, 28F008S5 */
+
+/* dimensions */
+#define I8S5_NBLOCKS	16		/* a 28F008S5 consists of 16 blocks */
+#define I8S5_BLKSZ	(64*1024)	/* of 64Kbyte each */
+#define I8S5_SIZE	(I8S5_BLKSZ * I8S5_NBLOCKS)
+
+/**************** DEFINES for Intel 28F800B5 FLASH chip **********************/
+
+/* register addresses, valid only following a I8S5_CMD_RD_ID command */
+#define I8B5_ADDR_MAN	0x00000	/* manufacturer's id */
+#define I8B5_ADDR_DEV	0x00001	/* device id */
+
+/* Commands */
+#define I8B5_CMD_RST	0xFF	/* reset flash */
+#define I8B5_CMD_RD_ID	0x90	/* read the id and lock bits */
+#define I8B5_CMD_RD_STAT 0x70	/* read the status register */
+#define I8B5_CMD_CLR_STAT 0x50	/* clear the staus register */
+#define I8B5_CMD_ERASE1	0x20	/* first word for block erase */
+#define I8B5_CMD_ERASE2	0xD0	/* second word for block erase */
+#define I8B5_CMD_PROG	0x40	/* program word command */
+
+/* status register bits */
+#define I8B5_STAT_VPPS	0x08	/* VPP Status */
+#define I8B5_STAT_DWS	0x10	/* Program and Set Lock Bit Status */
+#define I8B5_STAT_ES	0x20	/* Erase and Clear Lock Bit Status */
+#define I8B5_STAT_ESS	0x40	/* Erase Suspend Status */
+#define I8B5_STAT_RDY	0x80	/* Write State Machine Status, 1=rdy */
+
+#define I8B5_STAT_ERR	(I8B5_STAT_VPPS | I8B5_STAT_DWS | I8B5_STAT_ES)
+
+/* ID Configuration */
+#define I8B5_RD_ID_MAN	0x89	/* Manufacturer code = 0x89 */
+#define I8B5_RD_ID_DEV1	0x889D	/* Device code = 0x889D, 28F800B5 */
+
+/* dimensions */
+#define I8B5_NBLOCKS	8		/* a 28F008S5 consists of 16 blocks */
+#define I8B5_BLKSZ	(128*1024)	/* of 64Kbyte each */
+#define I8B5_SIZE	(I8B5_BLKSZ * I8B5_NBLOCKS)
+
+/****************** DEFINES for Cogent CMA302 Flash **************************/
+
+/*
+ * Quoted from the CMA302 manual:
+ *
+ * Although the CMA302 supports 64-bit reads, all writes must be done with
+ * word size only. When programming the CMA302, the FLASH devices appear as 2
+ * banks of interleaved, 32-bit wide FLASH. Each 32-bit word consists of four
+ * 28F008S5 devices. The first bank is accessed when the word address is even,
+ * while the second bank is accessed when the word address is odd. This must
+ * be taken into account when programming the desired word. Also, when locking
+ * blocks, software must lock both banks. The CMA302 does not directly support
+ * byte writing.  Programming and/or erasing individual bytes is done with
+ * selective use of the Write Command.  By not placing the Write Command value
+ * on a particular byte lane, that byte will not be written with the following
+ * Write Data. Also, remember that within a byte lane (i.e. D0-7), there are
+ * two 28F008S5 devices, one for each bank or every other word.
+ *
+ * End quote.
+ *
+ * Each 28F008S5 is 8Mbit, with 8 bit wide data. i.e. each is 1Mbyte. The
+ * chips are arranged on the CMA302 in multiples of two banks, each bank having
+ * 4 chips. Each bank must be accessed as a single 32 bit wide device (i.e.
+ * aligned on a 32 bit boundary), with each byte lane within the 32 bits (0-3)
+ * going to each of the 4 chips and the word address selecting the bank, even
+ * being the low bank and odd the high bank. For 64bit reads, both banks are
+ * read simultaneously with the second bank on byte lanes 4-7. Each 28F008S5
+ * consists of 16 64Kbyte "block"s. Before programming a byte, the block that
+ * the byte resides within must be erased. So if you want to program contiguous
+ * memory locations, you must erase all 8 chips at the same time. i.e. the
+ * flash on the CMA302 can be viewed as a number of 512Kbyte blocks.
+ *
+ * Note: I am going to treat banks as 8 Mbytes (1Meg of 64bit words), whereas
+ * the example code treats them as a pair of interleaved 1 Mbyte x 32bit banks.
+ */
+
+typedef unsigned long c302f_word_t;	/* 32 or 64 bit unsigned integer */
+typedef volatile c302f_word_t *c302f_addr_t;
+typedef unsigned long c302f_size_t;	/* want this big - at least 32 bit */
+
+/* layout of banks on cma302 board */
+#define C302F_BNK_WIDTH		8	/* each bank is 8 chips wide */
+#define C302F_BNK_WSHIFT	3	/* log base 2 of C302F_BNK_WIDTH */
+#define C302F_BNK_NBLOCKS	I8S5_NBLOCKS
+#define C302F_BNK_BLKSZ		(I8S5_BLKSZ * C302F_BNK_WIDTH)
+#define C302F_BNK_SIZE		(I8S5_SIZE * C302F_BNK_WIDTH)
+
+#define C302F_MAX_BANKS		2	/* up to 2 banks (8M each) on CMA302 */
+
+/* align addresses and sizes to bank boundaries */
+#define C302F_BNK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
+				    & ~(C302F_BNK_WIDTH - 1)))
+#define C302F_BNK_SIZE_ALIGN(s)	((c302f_size_t)C302F_BNK_ADDR_ALIGN( \
+				    (c302f_size_t)(s) + (C302F_BNK_WIDTH - 1)))
+
+/* align addresses and sizes to block boundaries */
+#define C302F_BLK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
+				    & ~(C302F_BNK_BLKSZ - 1)))
+#define C302F_BLK_SIZE_ALIGN(s)	((c302f_size_t)C302F_BLK_ADDR_ALIGN( \
+				    (c302f_size_t)(s) + (C302F_BNK_BLKSZ - 1)))
+
+/* add a byte offset to a flash address */
+#define C302F_ADDR_ADD_BYTEOFF(a,o) \
+				(c302f_addr_t)((c302f_size_t)(a) + (o))
+
+/* get base address of bank b, given flash base address a */
+#define C302F_BNK_ADDR_BASE(a,b) \
+				C302F_ADDR_ADD_BYTEOFF((a), \
+				    (c302f_size_t)(b) * C302F_BNK_SIZE)
+
+/* adjust an address a (within a bank) to next word, block or bank */
+#define C302F_BNK_ADDR_NEXT_WORD(a) \
+				C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_WIDTH)
+#define C302F_BNK_ADDR_NEXT_BLK(a) \
+				C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_BLKSZ)
+#define C302F_BNK_ADDR_NEXT_BNK(a) \
+				C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define C302F_BNK_ADDR_I8S5REG(a,r) \
+				C302F_ADDR_ADD_BYTEOFF((a), \
+				    (r) << C302F_BNK_WSHIFT)
+
+/* make a bank representation for each chip address */
+
+#define C302F_BNK_ADDR_MAN(a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_MAN)
+#define C302F_BNK_ADDR_DEV(a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_DEV)
+#define C302F_BNK_ADDR_CFGM(a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFGM)
+#define C302F_BNK_ADDR_CFG(b,a)	C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the c302f_word_t type
+ */
+#define C302F_FILL_WORD(o)	(((unsigned long)(o) << 24) | \
+				    ((unsigned long)(o) << 16) | \
+				    ((unsigned long)(o) << 8) | \
+				    (unsigned long)(o))
+
+/* make a bank representation for each chip cmd/stat/rd value */
+
+/* Commands */
+#define C302F_BNK_CMD_RST	C302F_FILL_WORD(I8S5_CMD_RST)
+#define C302F_BNK_CMD_RD_ID	C302F_FILL_WORD(I8S5_CMD_RD_ID)
+#define C302F_BNK_CMD_RD_STAT	C302F_FILL_WORD(I8S5_CMD_RD_STAT)
+#define C302F_BNK_CMD_CLR_STAT	C302F_FILL_WORD(I8S5_CMD_CLR_STAT)
+#define C302F_BNK_CMD_ERASE1	C302F_FILL_WORD(I8S5_CMD_ERASE1)
+#define C302F_BNK_CMD_ERASE2	C302F_FILL_WORD(I8S5_CMD_ERASE2)
+#define C302F_BNK_CMD_PROG	C302F_FILL_WORD(I8S5_CMD_PROG)
+#define C302F_BNK_CMD_LOCK	C302F_FILL_WORD(I8S5_CMD_LOCK)
+#define C302F_BNK_CMD_SET_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_SET_LOCK_BLK)
+#define C302F_BNK_CMD_SET_LOCK_MSTR C302F_FILL_WORD(I8S5_CMD_SET_LOCK_MSTR)
+#define C302F_BNK_CMD_CLR_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define C302F_BNK_STAT_DPS	C302F_FILL_WORD(I8S5_STAT_DPS)
+#define C302F_BNK_STAT_PSS	C302F_FILL_WORD(I8S5_STAT_PSS)
+#define C302F_BNK_STAT_VPPS	C302F_FILL_WORD(I8S5_STAT_VPPS)
+#define C302F_BNK_STAT_PSLBS	C302F_FILL_WORD(I8S5_STAT_PSLBS)
+#define C302F_BNK_STAT_ECLBS	C302F_FILL_WORD(I8S5_STAT_ECLBS)
+#define C302F_BNK_STAT_ESS	C302F_FILL_WORD(I8S5_STAT_ESS)
+#define C302F_BNK_STAT_RDY	C302F_FILL_WORD(I8S5_STAT_RDY)
+
+#define C302F_BNK_STAT_ERR	C302F_FILL_WORD(I8S5_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define C302F_BNK_RD_ID_LOCK	C302F_FILL_WORD(I8S5_RD_ID_LOCK)
+#define C302F_BNK_RD_ID_MAN	C302F_FILL_WORD(I8S5_RD_ID_MAN)
+#define C302F_BNK_RD_ID_DEV	C302F_FILL_WORD(I8S5_RD_ID_DEV)
+
+/*************** DEFINES for Cogent Motherboard Flash ************************/
+
+typedef unsigned short cmbf_word_t;	/* 16 bit unsigned integer */
+typedef volatile cmbf_word_t *cmbf_addr_t;
+typedef unsigned long cmbf_size_t;	/* want this big - at least 32 bit */
+
+/* layout of banks on cogent motherboard - only 1 bank, 16 bit wide */
+#define CMBF_BNK_WIDTH		1	/* each bank is one chip wide */
+#define CMBF_BNK_WSHIFT	0	/* log base 2 of CMBF_BNK_WIDTH */
+#define CMBF_BNK_NBLOCKS	I8B5_NBLOCKS
+#define CMBF_BNK_BLKSZ		(I8B5_BLKSZ * CMBF_BNK_WIDTH)
+#define CMBF_BNK_SIZE		(I8B5_SIZE * CMBF_BNK_WIDTH)
+
+#define CMBF_MAX_BANKS		1	/* only 1 x 1Mbyte bank on cogent m/b */
+
+/* align addresses and sizes to bank boundaries */
+#define CMBF_BNK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
+				    & ~(CMBF_BNK_WIDTH - 1)))
+#define CMBF_BNK_SIZE_ALIGN(s)	((c302f_size_t)CMBF_BNK_ADDR_ALIGN( \
+				    (c302f_size_t)(s) + (CMBF_BNK_WIDTH - 1)))
+
+/* align addresses and sizes to block boundaries */
+#define CMBF_BLK_ADDR_ALIGN(a)	((c302f_addr_t)((c302f_size_t)(a) \
+				    & ~(CMBF_BNK_BLKSZ - 1)))
+#define CMBF_BLK_SIZE_ALIGN(s)	((c302f_size_t)CMBF_BLK_ADDR_ALIGN( \
+				    (c302f_size_t)(s) + (CMBF_BNK_BLKSZ - 1)))
+
+/* add a byte offset to a flash address */
+#define CMBF_ADDR_ADD_BYTEOFF(a,o) \
+				(c302f_addr_t)((c302f_size_t)(a) + (o))
+
+/* get base address of bank b, given flash base address a */
+#define CMBF_BNK_ADDR_BASE(a,b) \
+				CMBF_ADDR_ADD_BYTEOFF((a), \
+				    (c302f_size_t)(b) * CMBF_BNK_SIZE)
+
+/* adjust an address a (within a bank) to next word, block or bank */
+#define CMBF_BNK_ADDR_NEXT_WORD(a) \
+				CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_WIDTH)
+#define CMBF_BNK_ADDR_NEXT_BLK(a) \
+				CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_BLKSZ)
+#define CMBF_BNK_ADDR_NEXT_BNK(a) \
+				CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define CMBF_BNK_ADDR_I8B5REG(a,r) \
+				CMBF_ADDR_ADD_BYTEOFF((a), \
+				    (r) << CMBF_BNK_WSHIFT)
+
+/* make a bank representation for each chip address */
+
+#define CMBF_BNK_ADDR_MAN(a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_MAN)
+#define CMBF_BNK_ADDR_DEV(a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_DEV)
+#define CMBF_BNK_ADDR_CFGM(a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFGM)
+#define CMBF_BNK_ADDR_CFG(b,a)	CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the c302f_word_t type
+ */
+#define CMBF_FILL_WORD(o)	(((unsigned long)(o) << 24) | \
+				    ((unsigned long)(o) << 16) | \
+				    ((unsigned long)(o) << 8) | \
+				    (unsigned long)(o))
+
+/* make a bank representation for each chip cmd/stat/rd value */
+
+/* Commands */
+#define CMBF_BNK_CMD_RST	CMBF_FILL_WORD(I8B5_CMD_RST)
+#define CMBF_BNK_CMD_RD_ID	CMBF_FILL_WORD(I8B5_CMD_RD_ID)
+#define CMBF_BNK_CMD_RD_STAT	CMBF_FILL_WORD(I8B5_CMD_RD_STAT)
+#define CMBF_BNK_CMD_CLR_STAT	CMBF_FILL_WORD(I8B5_CMD_CLR_STAT)
+#define CMBF_BNK_CMD_ERASE1	CMBF_FILL_WORD(I8B5_CMD_ERASE1)
+#define CMBF_BNK_CMD_ERASE2	CMBF_FILL_WORD(I8B5_CMD_ERASE2)
+#define CMBF_BNK_CMD_PROG	CMBF_FILL_WORD(I8B5_CMD_PROG)
+#define CMBF_BNK_CMD_LOCK	CMBF_FILL_WORD(I8B5_CMD_LOCK)
+#define CMBF_BNK_CMD_SET_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_BLK)
+#define CMBF_BNK_CMD_SET_LOCK_MSTR CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_MSTR)
+#define CMBF_BNK_CMD_CLR_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define CMBF_BNK_STAT_DPS	CMBF_FILL_WORD(I8B5_STAT_DPS)
+#define CMBF_BNK_STAT_PSS	CMBF_FILL_WORD(I8B5_STAT_PSS)
+#define CMBF_BNK_STAT_VPPS	CMBF_FILL_WORD(I8B5_STAT_VPPS)
+#define CMBF_BNK_STAT_PSLBS	CMBF_FILL_WORD(I8B5_STAT_PSLBS)
+#define CMBF_BNK_STAT_ECLBS	CMBF_FILL_WORD(I8B5_STAT_ECLBS)
+#define CMBF_BNK_STAT_ESS	CMBF_FILL_WORD(I8B5_STAT_ESS)
+#define CMBF_BNK_STAT_RDY	CMBF_FILL_WORD(I8B5_STAT_RDY)
+
+#define CMBF_BNK_STAT_ERR	CMBF_FILL_WORD(I8B5_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define CMBF_BNK_RD_ID_LOCK	CMBF_FILL_WORD(I8B5_RD_ID_LOCK)
+#define CMBF_BNK_RD_ID_MAN	CMBF_FILL_WORD(I8B5_RD_ID_MAN)
+#define CMBF_BNK_RD_ID_DEV	CMBF_FILL_WORD(I8B5_RD_ID_DEV)
diff --git a/board/cogent/kbm.c b/board/cogent/kbm.c
new file mode 100755
index 0000000..8496402
--- /dev/null
+++ b/board/cogent/kbm.c
@@ -0,0 +1,3 @@
+/* keyboard/mouse not implemented yet */
+
+int cma_kbm_not_implemented = 1;
diff --git a/board/cogent/kbm.h b/board/cogent/kbm.h
new file mode 100755
index 0000000..7eb419c
--- /dev/null
+++ b/board/cogent/kbm.h
@@ -0,0 +1,79 @@
+/* keyboard/mouse not implemented yet */
+
+extern int cma_kbm_not_implemented;
+
+/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/
+
+/*
+ * note the auxillary port is used to control the mouse
+ */
+
+/* 8542B Commands (Sent to the Command Port) */
+#define HT8542_CMD_SET_BYTE	0x60	/* Set the command byte */
+#define HT8542_CMD_GET_BYTE	0x20	/* Get the command byte */
+#define HT8542_CMD_KBD_OBUFF	0xD2	/* Write to HT8542 Kbd Output Buffer */
+#define HT8542_CMD_AUX_OBUFF	0xD3	/* Write to HT8542 Mse Output Buffer */
+#define HT8542_CMD_AUX_WRITE	0xD4	/* Write to Mouse Port */
+#define HT8542_CMD_AUX_OFF	0xA7	/* Disable Mouse Port */
+#define HT8542_CMD_AUX_ON	0xA8	/* Re-Enable Mouse Port */
+#define HT8542_CMD_AUX_TEST	0xA9	/* Test for the presence of a Mouse */
+#define HT8542_CMD_DIAG		0xAA	/* Start Diagnostics */
+#define HT8542_CMD_KBD_TEST	0xAB	/* Test for presence of a keyboard */
+#define HT8542_CMD_KBD_OFF	0xAD	/* Disable Kbd Port (use KBD_DAT_ON) */
+#define HT8542_CMD_KBD_ON	0xAE	/* Enable Kbd Port (use KBD_DAT_OFF) */
+
+/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */
+#define HT8542_CMD_BYTE_TRANS	0x40
+#define HT8542_CMD_BYTE_AUX_OFF	0x20	/* 1 = mse port disabled, 0 = enabled */
+#define HT8542_CMD_BYTE_KBD_OFF	0x10	/* 1 = kbd port disabled, 0 = enabled */
+#define HT8542_CMD_BYTE_OVER	0x08	/* 1 = override keyboard lock */
+#define HT8542_CMD_BYTE_RES	0x04	/* reserved */
+#define HT8542_CMD_BYTE_AUX_INT	0x02	/* 1 = enable mouse interrupt */
+#define HT8542_CMD_BYTE_KBD_INT	0x01	/* 1 = enable keyboard interrupt */
+
+/* Keyboard Commands (Sent to the Data Port) */
+#define KBD_CMD_LED		0xED	/* Set Keyboard LEDS with next byte */
+#define KBD_CMD_ECHO		0xEE	/* Echo - we get 0xFA, 0xEE back */
+#define KBD_CMD_MODE		0xF0	/* set scan code mode with next byte */
+#define KBD_CMD_ID		0xF2	/* get keyboard/mouse ID */
+#define KBD_CMD_RPT		0xF3	/* Set Repeat Rate and Delay 2nd Byte */
+#define KBD_CMD_ON		0xF4	/* Enable keyboard */
+#define KBD_CMD_OFF		0xF5	/* Disables Scanning, Resets to Def */
+#define KBD_CMD_DEF		0xF6	/* Reverts kbd to default settings */
+#define KBD_CMD_RST		0xFF	/* Reset - should get 0xFA, 0xAA back */
+
+/* Set LED second bit defines */
+#define KBD_CMD_LED_SCROLL	0x01	/* Set SCROLL LOCK LED on */
+#define KBD_CMD_LED_NUM		0x02	/* Set NUM LOCK LED on */
+#define KBD_CMD_LED_CAPS	0x04	/* Set CAPS LOCK LED on */
+
+/* Set Mode second byte defines */
+#define KBD_CMD_MODE_STAT	0x00	/* get current scan code mode */
+#define KBD_CMD_MODE_SCAN1	0x01	/* set mode to scan code 1 */
+#define KBD_CMD_MODE_SCAN2	0x02	/* set mode to scan code 2 */
+#define KBD_CMD_MODE_SCAN3	0x03	/* set mode to scan code 3 */
+
+/* Keyboard/Mouse ID Codes */
+#define KBD_CMD_ID_1ST		0xAB	/* 1st byte is 0xAB, 2nd is actual ID */
+#define KBD_CMD_ID_KBD		0x83	/* Keyboard */
+#define KBD_CMD_ID_MOUSE	0x00	/* Mouse */
+
+/* Keyboard Data Return Defines */
+#define KBD_STAT_OVER		0x00	/* Buffer Overrun */
+#define KBD_STAT_DIAG_OK	0x55	/* Internal Self Test OK */
+#define KBD_STAT_RST_OK		0xAA	/* Reset Complete */
+#define KBD_STAT_ECHO		0xEE	/* Echo Command Return */
+#define KBD_STAT_BRK		0xF0	/* Prefix for Break Key Code */
+#define KBD_STAT_ACK		0xFA	/* Received after all commands */
+#define KBD_STAT_DIAG_FAIL	0xFD	/* Internal Self Test Failed */
+#define KBD_STAT_RESEND		0xFE	/* Resend Last Command */
+
+/* HT8542B Status Register Bit Defines */
+#define HT8542_STAT_OBF		0x01	/* 1 = output buffer is full */
+#define HT8542_STAT_IBF		0x02	/* 1 = input buffer is full */
+#define HT8542_STAT_SYS		0x04	/* system flag - unused */
+#define HT8542_STAT_CMD		0x08	/* 1 = cmd in input buffer, 0 = data */
+#define HT8542_STAT_INH		0x10	/* 1 = Inhibit - unused */
+#define HT8542_STAT_TX		0x20	/* 1 = Transmit Timeout has occured */
+#define HT8542_STAT_RX		0x40	/* 1 = Receive Timeout has occured */
+#define HT8542_STAT_PERR	0x80	/* 1 = Parity Error from Keyboard */
diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c
new file mode 100755
index 0000000..814b4c8
--- /dev/null
+++ b/board/cogent/lcd.c
@@ -0,0 +1,245 @@
+/* most of this is taken from the file */
+/* hal/powerpc/cogent/current/src/hal_diag.c in the */
+/* Cygnus eCos source. Here is the copyright notice: */
+/* */
+/*============================================================================= */
+/* */
+/*      hal_diag.c */
+/* */
+/*      HAL diagnostic output code */
+/* */
+/*============================================================================= */
+/*####COPYRIGHTBEGIN#### */
+/* */
+/* ------------------------------------------- */
+/* The contents of this file are subject to the Cygnus eCos Public License */
+/* Version 1.0 (the "License"); you may not use this file except in */
+/* compliance with the License.  You may obtain a copy of the License at */
+/* http://sourceware.cygnus.com/ecos */
+/* */
+/* Software distributed under the License is distributed on an "AS IS" */
+/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the */
+/* License for the specific language governing rights and limitations under */
+/* the License. */
+/* */
+/* The Original Code is eCos - Embedded Cygnus Operating System, released */
+/* September 30, 1998. */
+/* */
+/* The Initial Developer of the Original Code is Cygnus.  Portions created */
+/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved. */
+/* ------------------------------------------- */
+/* */
+/*####COPYRIGHTEND#### */
+/*============================================================================= */
+/*#####DESCRIPTIONBEGIN#### */
+/* */
+/* Author(s):    nickg, jskov */
+/* Contributors: nickg, jskov */
+/* Date:         1999-03-23 */
+/* Purpose:      HAL diagnostic output */
+/* Description:  Implementations of HAL diagnostic output support. */
+/* */
+/*####DESCRIPTIONEND#### */
+/* */
+/*============================================================================= */
+
+/*----------------------------------------------------------------------------- */
+/* Cogent board specific LCD code */
+
+#include <common.h>
+#include <stdarg.h>
+#include <board/cogent/lcd.h>
+
+static char lines[2][LCD_LINE_LENGTH+1];
+static int curline;
+static int linepos;
+static int heartbeat_active;
+/* make the next two strings exactly LCD_LINE_LENGTH (16) chars long */
+/* pad to the right with spaces if necessary */
+static char init_line0[LCD_LINE_LENGTH+1] = "U-Boot Cogent  ";
+static char init_line1[LCD_LINE_LENGTH+1] = "mjj, 11 Aug 2000";
+
+static inline unsigned char
+lcd_read_status(cma_mb_lcd *clp)
+{
+    /* read the Busy Status Register */
+    return (cma_mb_reg_read(&clp->lcd_bsr));
+}
+
+static inline void
+lcd_wait_not_busy(cma_mb_lcd *clp)
+{
+    /*
+     * wait for not busy
+     * Note: It seems that the LCD isn't quite ready to process commands
+     * when it clears the BUSY flag. Reading the status address an extra
+     * time seems to give it enough breathing room.
+     */
+
+    while (lcd_read_status(clp) & LCD_STAT_BUSY)
+	;
+
+    (void)lcd_read_status(clp);
+}
+
+static inline void
+lcd_write_command(cma_mb_lcd *clp, unsigned char cmd)
+{
+    lcd_wait_not_busy(clp);
+
+    /* write the Command Register */
+    cma_mb_reg_write(&clp->lcd_cmd, cmd);
+}
+
+static inline void
+lcd_write_data(cma_mb_lcd *clp, unsigned char data)
+{
+    lcd_wait_not_busy(clp);
+
+    /* write the Current Character Register */
+    cma_mb_reg_write(&clp->lcd_ccr, data);
+}
+
+static inline void
+lcd_dis(int addr, char *string)
+{
+    cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
+    int pos, linelen;
+
+    linelen = LCD_LINE_LENGTH;
+    if (heartbeat_active && addr == LCD_LINE0)
+	linelen--;
+
+    lcd_write_command(clp, LCD_CMD_ADD + addr);
+    for (pos = 0; *string != '\0' && pos < linelen; pos++)
+	lcd_write_data(clp, *string++);
+}
+
+void
+lcd_init(void)
+{
+    cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
+    int i;
+
+    /* configure the lcd for 8 bits/char, 2 lines and 5x7 dot matrix */
+    lcd_write_command(clp, LCD_CMD_MODE);
+
+    /* turn the LCD display on */
+    lcd_write_command(clp, LCD_CMD_DON);
+
+    curline = 0;
+    linepos = 0;
+
+    for (i = 0; i < LCD_LINE_LENGTH; i++) {
+	lines[0][i] = init_line0[i];
+	lines[1][i] = init_line1[i];
+    }
+
+    lines[0][LCD_LINE_LENGTH] = lines[1][LCD_LINE_LENGTH] = 0;
+
+    lcd_dis(LCD_LINE0, lines[0]);
+    lcd_dis(LCD_LINE1, lines[1]);
+
+    printf("HD44780 2 line x %d char display\n", LCD_LINE_LENGTH);
+}
+
+void
+lcd_write_char(const char c)
+{
+    int i, linelen;
+
+    /* ignore CR */
+    if (c == '\r')
+	return;
+
+    linelen = LCD_LINE_LENGTH;
+    if (heartbeat_active && curline == 0)
+	linelen--;
+
+    if (c == '\n') {
+	lcd_dis(LCD_LINE0, &lines[curline^1][0]);
+	lcd_dis(LCD_LINE1, &lines[curline][0]);
+
+	/* Do a line feed */
+	curline ^= 1;
+	linelen = LCD_LINE_LENGTH;
+	if (heartbeat_active && curline == 0)
+	    linelen--;
+	linepos = 0;
+
+	for (i = 0; i < linelen; i++)
+	    lines[curline][i] = ' ';
+
+	return;
+    }
+
+    /* Only allow to be output if there is room on the LCD line */
+    if (linepos < linelen)
+	lines[curline][linepos++] = c;
+}
+
+void
+lcd_flush(void)
+{
+    lcd_dis(LCD_LINE1, &lines[curline][0]);
+}
+
+void
+lcd_write_string(const char *s)
+{
+    char *p;
+
+    for (p = (char *)s; *p != '\0'; p++)
+	lcd_write_char(*p);
+}
+
+void
+lcd_printf(const char *fmt, ...)
+{
+    va_list args;
+    char buf[CFG_PBSIZE];
+
+    va_start(args, fmt);
+    (void)vsprintf(buf, fmt, args);
+    va_end(args);
+
+    lcd_write_string(buf);
+}
+
+void
+lcd_heartbeat(void)
+{
+    cma_mb_lcd *clp = (cma_mb_lcd *)CMA_MB_LCD_BASE;
+#if 0
+    static char rotchars[] = { '|', '/', '-', '\\' };
+#else
+    /* HD44780 Rom Code A00 has no backslash */
+    static char rotchars[] = { '|', '/', '-', '\315' };
+#endif
+    static int rotator_index = 0;
+
+    heartbeat_active = 1;
+
+    /* write the address */
+    lcd_write_command(clp, LCD_CMD_ADD + LCD_LINE0 + (LCD_LINE_LENGTH - 1));
+
+    /* write the next char in the sequence */
+    lcd_write_data(clp, rotchars[rotator_index]);
+
+    if (++rotator_index >= (sizeof rotchars / sizeof rotchars[0]))
+	rotator_index = 0;
+}
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void board_show_activity (ulong timestamp)
+{
+#ifdef CONFIG_STATUS_LED
+	if ((timestamp % (CFG_HZ / 2) == 0)
+		lcd_heartbeat ();
+#endif
+}
+
+void show_activity(int arg)
+{
+}
+#endif
diff --git a/board/cogent/lcd.h b/board/cogent/lcd.h
new file mode 100755
index 0000000..1056eea
--- /dev/null
+++ b/board/cogent/lcd.h
@@ -0,0 +1,84 @@
+/* most of this is taken from the file */
+/* hal/powerpc/cogent/current/src/hal_diag.c in the */
+/* Cygnus eCos source. Here is the copyright notice: */
+/* */
+/*============================================================================= */
+/* */
+/*      hal_diag.c */
+/* */
+/*      HAL diagnostic output code */
+/* */
+/*============================================================================= */
+/*####COPYRIGHTBEGIN#### */
+/* */
+/* ------------------------------------------- */
+/* The contents of this file are subject to the Cygnus eCos Public License */
+/* Version 1.0 (the "License"); you may not use this file except in */
+/* compliance with the License.  You may obtain a copy of the License at */
+/* http://sourceware.cygnus.com/ecos */
+/* */
+/* Software distributed under the License is distributed on an "AS IS" */
+/* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the */
+/* License for the specific language governing rights and limitations under */
+/* the License. */
+/* */
+/* The Original Code is eCos - Embedded Cygnus Operating System, released */
+/* September 30, 1998. */
+/* */
+/* The Initial Developer of the Original Code is Cygnus.  Portions created */
+/* by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions.  All Rights Reserved. */
+/* ------------------------------------------- */
+/* */
+/*####COPYRIGHTEND#### */
+/*============================================================================= */
+/*#####DESCRIPTIONBEGIN#### */
+/* */
+/* Author(s):    nickg, jskov */
+/* Contributors: nickg, jskov */
+/* Date:         1999-03-23 */
+/* Purpose:      HAL diagnostic output */
+/* Description:  Implementations of HAL diagnostic output support. */
+/* */
+/*####DESCRIPTIONEND#### */
+/* */
+/*============================================================================= */
+
+/* FEMA 162B 16 character x 2 line LCD */
+
+/* status register bit definitions */
+#define LCD_STAT_BUSY	0x80	/* 1 = display busy */
+#define LCD_STAT_ADD	0x7F	/* bits 0-6 return current display address */
+
+/* command register definitions */
+#define LCD_CMD_RST	0x01	/* clear entire display and reset display addr */
+#define LCD_CMD_HOME	0x02	/* reset display address and reset any shifting */
+#define LCD_CMD_ECL	0x04	/* move cursor left one pos on next data write */
+#define LCD_CMD_ESL	0x05	/* shift display left one pos on next data write */
+#define LCD_CMD_ECR	0x06	/* move cursor right one pos on next data write */
+#define LCD_CMD_ESR	0x07	/* shift disp right one pos on next data write */
+#define LCD_CMD_DOFF	0x08	/* display off, cursor off, blinking off */
+#define LCD_CMD_BL	0x09	/* blink character at current cursor position */
+#define LCD_CMD_CUR	0x0A	/* enable cursor on */
+#define LCD_CMD_DON	0x0C	/* turn display on */
+#define LCD_CMD_CL	0x10	/* move cursor left one position */
+#define LCD_CMD_SL	0x14	/* shift display left one position */
+#define LCD_CMD_CR	0x18	/* move cursor right one position */
+#define LCD_CMD_SR	0x1C	/* shift display right one position */
+#define LCD_CMD_MODE	0x38	/* sets 8 bits, 2 lines, 5x7 characters */
+#define LCD_CMD_ACG	0x40	/* bits 0-5 sets character generator address */
+#define LCD_CMD_ADD	0x80	/* bits 0-6 sets display data addr to line 1 + */
+
+/* LCD status values */
+#define LCD_OK		0x00
+#define LCD_ERR 	0x01
+
+#define LCD_LINE0	0x00
+#define LCD_LINE1	0x40
+
+#define LCD_LINE_LENGTH	16
+
+extern void lcd_init(void);
+extern void lcd_write_char(const char);
+extern void lcd_flush(void);
+extern void lcd_write_string(const char *);
+extern void lcd_printf(const char *, ...);
diff --git a/board/cogent/mb.c b/board/cogent/mb.c
new file mode 100755
index 0000000..917132b
--- /dev/null
+++ b/board/cogent/mb.c
@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <board/cogent/dipsw.h>
+#include <board/cogent/lcd.h>
+#include <board/cogent/rtc.h>
+#include <board/cogent/par.h>
+#include <board/cogent/pci.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_8260)
+
+#include <ioports.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+	/* Port A configuration */
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PA31 */ {0, 0, 0, 0, 0, 0},
+	 /* PA30 */ {0, 0, 0, 0, 0, 0},
+	 /* PA29 */ {0, 0, 0, 0, 0, 0},
+	 /* PA28 */ {0, 0, 0, 0, 0, 0},
+	 /* PA27 */ {0, 0, 0, 0, 0, 0},
+	 /* PA26 */ {0, 0, 0, 0, 0, 0},
+	 /* PA25 */ {0, 0, 0, 0, 0, 0},
+	 /* PA24 */ {0, 0, 0, 0, 0, 0},
+	 /* PA23 */ {0, 0, 0, 0, 0, 0},
+	 /* PA22 */ {0, 0, 0, 0, 0, 0},
+	 /* PA21 */ {0, 0, 0, 0, 0, 0},
+	 /* PA20 */ {0, 0, 0, 0, 0, 0},
+	 /* PA19 */ {0, 0, 0, 0, 0, 0},
+	 /* PA18 */ {0, 0, 0, 0, 0, 0},
+	 /* PA17 */ {0, 0, 0, 0, 0, 0},
+	 /* PA16 */ {0, 0, 0, 0, 0, 0},
+	 /* PA15 */ {0, 0, 0, 0, 0, 0},
+	 /* PA14 */ {0, 0, 0, 0, 0, 0},
+	 /* PA13 */ {0, 0, 0, 0, 0, 0},
+	 /* PA12 */ {0, 0, 0, 0, 0, 0},
+	 /* PA11 */ {0, 0, 0, 0, 0, 0},
+	 /* PA10 */ {0, 0, 0, 0, 0, 0},
+					/* PA9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC2 TXD */
+					/* PA8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC2 RXD */
+	 /* PA7  */ {0, 0, 0, 0, 0, 0},
+	 /* PA6  */ {0, 0, 0, 0, 0, 0},
+	 /* PA5  */ {0, 0, 0, 0, 0, 0},
+	 /* PA4  */ {0, 0, 0, 0, 0, 0},
+	 /* PA3  */ {0, 0, 0, 0, 0, 0},
+	 /* PA2  */ {0, 0, 0, 0, 0, 0},
+	 /* PA1  */ {0, 0, 0, 0, 0, 0},
+	 /* PA0  */ {0, 0, 0, 0, 0, 0}
+	 },
+
+
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PB31 */ {0, 0, 0, 0, 0, 0},
+	 /* PB30 */ {0, 0, 0, 0, 0, 0},
+	 /* PB29 */ {0, 0, 0, 0, 0, 0},
+	 /* PB28 */ {0, 0, 0, 0, 0, 0},
+	 /* PB27 */ {0, 0, 0, 0, 0, 0},
+	 /* PB26 */ {0, 0, 0, 0, 0, 0},
+	 /* PB25 */ {0, 0, 0, 0, 0, 0},
+	 /* PB24 */ {0, 0, 0, 0, 0, 0},
+	 /* PB23 */ {0, 0, 0, 0, 0, 0},
+	 /* PB22 */ {0, 0, 0, 0, 0, 0},
+	 /* PB21 */ {0, 0, 0, 0, 0, 0},
+	 /* PB20 */ {0, 0, 0, 0, 0, 0},
+	 /* PB19 */ {0, 0, 0, 0, 0, 0},
+	 /* PB18 */ {0, 0, 0, 0, 0, 0},
+	 /* PB17 */ {0, 0, 0, 0, 0, 0},
+	 /* PB16 */ {0, 0, 0, 0, 0, 0},
+	 /* PB15 */ {0, 0, 0, 0, 0, 0},
+	 /* PB14 */ {0, 0, 0, 0, 0, 0},
+	 /* PB13 */ {0, 0, 0, 0, 0, 0},
+	 /* PB12 */ {0, 0, 0, 0, 0, 0},
+	 /* PB11 */ {0, 0, 0, 0, 0, 0},
+	 /* PB10 */ {0, 0, 0, 0, 0, 0},
+	 /* PB9  */ {0, 0, 0, 0, 0, 0},
+	 /* PB8  */ {0, 0, 0, 0, 0, 0},
+	 /* PB7  */ {0, 0, 0, 0, 0, 0},
+	 /* PB6  */ {0, 0, 0, 0, 0, 0},
+	 /* PB5  */ {0, 0, 0, 0, 0, 0},
+	 /* PB4  */ {0, 0, 0, 0, 0, 0},
+					/* PB3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PB0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 },
+
+
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PC31 */ {0, 0, 0, 0, 0, 0},
+	 /* PC30 */ {0, 0, 0, 0, 0, 0},
+	 /* PC29 */ {0, 0, 0, 0, 0, 0},
+	 /* PC28 */ {0, 0, 0, 0, 0, 0},
+	 /* PC27 */ {0, 0, 0, 0, 0, 0},
+	 /* PC26 */ {0, 0, 0, 0, 0, 0},
+	 /* PC25 */ {0, 0, 0, 0, 0, 0},
+	 /* PC24 */ {0, 0, 0, 0, 0, 0},
+	 /* PC23 */ {0, 0, 0, 0, 0, 0},
+	 /* PC22 */ {0, 0, 0, 0, 0, 0},
+	 /* PC21 */ {0, 0, 0, 0, 0, 0},
+	 /* PC20 */ {0, 0, 0, 0, 0, 0},
+	 /* PC19 */ {0, 0, 0, 0, 0, 0},
+	 /* PC18 */ {0, 0, 0, 0, 0, 0},
+	 /* PC17 */ {0, 0, 0, 0, 0, 0},
+	 /* PC16 */ {0, 0, 0, 0, 0, 0},
+	 /* PC15 */ {0, 0, 0, 0, 0, 0},
+	 /* PC14 */ {0, 0, 0, 0, 0, 0},
+	 /* PC13 */ {0, 0, 0, 0, 0, 0},
+	 /* PC12 */ {0, 0, 0, 0, 0, 0},
+	 /* PC11 */ {0, 0, 0, 0, 0, 0},
+	 /* PC10 */ {0, 0, 0, 0, 0, 0},
+	 /* PC9  */ {0, 0, 0, 0, 0, 0},
+	 /* PC8  */ {0, 0, 0, 0, 0, 0},
+	 /* PC7  */ {0, 0, 0, 0, 0, 0},
+	 /* PC6  */ {0, 0, 0, 0, 0, 0},
+	 /* PC5  */ {0, 0, 0, 0, 0, 0},
+	 /* PC4  */ {0, 0, 0, 0, 0, 0},
+	 /* PC3  */ {0, 0, 0, 0, 0, 0},
+	 /* PC2  */ {0, 0, 0, 0, 0, 0},
+	 /* PC1  */ {0, 0, 0, 0, 0, 0},
+	 /* PC0  */ {0, 0, 0, 0, 0, 0}
+	 },
+
+
+	{			/*            conf ppar psor pdir podr pdat */
+	 /* PD31 */ {0, 0, 0, 0, 0, 0},
+	 /* PD30 */ {0, 0, 0, 0, 0, 0},
+	 /* PD29 */ {0, 0, 0, 0, 0, 0},
+	 /* PD28 */ {0, 0, 0, 0, 0, 0},
+	 /* PD27 */ {0, 0, 0, 0, 0, 0},
+	 /* PD26 */ {0, 0, 0, 0, 0, 0},
+	 /* PD25 */ {0, 0, 0, 0, 0, 0},
+	 /* PD24 */ {0, 0, 0, 0, 0, 0},
+	 /* PD23 */ {0, 0, 0, 0, 0, 0},
+	 /* PD22 */ {0, 0, 0, 0, 0, 0},
+	 /* PD21 */ {0, 0, 0, 0, 0, 0},
+	 /* PD20 */ {0, 0, 0, 0, 0, 0},
+	 /* PD19 */ {0, 0, 0, 0, 0, 0},
+	 /* PD18 */ {0, 0, 0, 0, 0, 0},
+	 /* PD17 */ {0, 0, 0, 0, 0, 0},
+	 /* PD16 */ {0, 0, 0, 0, 0, 0},
+					/* PD15 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SDA */
+					/* PD14 */ {1, 1, 1, 0, 0, 0},
+					/* I2C SCL */
+	 /* PD13 */ {0, 0, 0, 0, 0, 0},
+	 /* PD12 */ {0, 0, 0, 0, 0, 0},
+	 /* PD11 */ {0, 0, 0, 0, 0, 0},
+	 /* PD10 */ {0, 0, 0, 0, 0, 0},
+					/* PD9  */ {1, 1, 0, 1, 0, 0},
+					/* SMC1 TXD */
+					/* PD8  */ {1, 1, 0, 0, 0, 0},
+					/* SMC1 RXD */
+	 /* PD7  */ {0, 0, 0, 0, 0, 0},
+	 /* PD6  */ {0, 0, 0, 0, 0, 0},
+	 /* PD5  */ {0, 0, 0, 0, 0, 0},
+	 /* PD4  */ {0, 0, 0, 0, 0, 0},
+					/* PD3  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD2  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD1  */ {0, 0, 0, 0, 0, 0},
+					/* pin doesn't exist */
+					/* PD0  */ {0, 0, 0, 0, 0, 0}
+					/* pin doesn't exist */
+	 }
+};
+
+#endif /* CONFIG_8260 */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: Cogent " COGENT_MOTHERBOARD " motherboard with a "
+	      COGENT_CPU_MODULE " CPU Module\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations while still
+ * running in flash
+ */
+
+int misc_init_f (void)
+{
+	printf ("DIPSW: ");
+	dipsw_init ();
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+#ifdef CONFIG_CMA111
+	return (32L * 1024L * 1024L);
+#else
+	unsigned char dipsw_val;
+	int dual, size0, size1;
+	long int memsize;
+
+	dipsw_val = dipsw_cooked ();
+
+	dual = dipsw_val & 0x01;
+	size0 = (dipsw_val & 0x08) >> 3;
+	size1 = (dipsw_val & 0x04) >> 2;
+
+	if (size0)
+		if (size1)
+			memsize = 16L * 1024L * 1024L;
+		else
+			memsize = 1L * 1024L * 1024L;
+	else if (size1)
+		memsize = 4L * 1024L * 1024L;
+	else {
+		printf ("[Illegal dip switch settings - assuming 16Mbyte SIMMs] ");
+		memsize = 16L * 1024L * 1024L;	/* shouldn't happen - guess 16M */
+	}
+
+	if (dual)
+		memsize *= 2L;
+
+	return (memsize);
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations after monitor
+ * has been relocated into ram
+ */
+
+int misc_init_r (void)
+{
+	printf ("LCD:   ");
+	lcd_init ();
+
+#if 0
+	printf ("RTC:   ");
+	rtc_init ();
+
+	printf ("PAR:   ");
+	par_init ();
+
+	printf ("KBM:   ");
+	kbm_init ();
+
+	printf ("PCI:   ");
+	pci_init ();
+#endif
+	return (0);
+}
diff --git a/board/cogent/mb.h b/board/cogent/mb.h
new file mode 100755
index 0000000..f6eaf0a
--- /dev/null
+++ b/board/cogent/mb.h
@@ -0,0 +1,529 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * defines for Cogent Motherboards
+ */
+
+#ifndef _COGENT_MB_H
+#define _COGENT_MB_H
+
+/*
+ * Cogent Motherboard Address Map
+ *
+ * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits).
+ *
+ * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following
+ * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and
+ * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3).
+ * Most other motherboard devices have registers mapped into the area
+ * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF
+ * is free for whatever.
+ *
+ * The location of the motherboard address space in the physical address space
+ * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu
+ * module plugged into the motherboard and is configured above.
+ *
+ * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF)
+ * generally only use byte lane 0 (D0-7) for their transfers, i.e. only
+ * 8 bit, or 1 byte, transfers can take place, so all the registers are
+ * only 8 bits wide. The exceptions are the motherboard flash, which uses
+ * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space.
+ *
+ * I/O registers within the mapped motherboard devices are 64 bit aligned
+ * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
+ * will be at byte 7 (the address + 7). For little endian addressing, the
+ * register will be at byte 0 (the address + 0). To learn the endianess
+ * we must include <endian.h>
+ *
+ * Take the CMA102 and CMA111 motherboards as examples...
+ *
+ * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3
+ * CMABus slots are each mapped directly onto the three general I/O slots.
+ *
+ * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI
+ * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard
+ * PCI Bus space is mapped onto general I/O slot 2, with a small area at the
+ * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF).
+ * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area
+ * 0xA000000-0xDFFFFFF.
+ */
+
+#define CMA_MB_RAM_BASE		(CFG_CMA_MB_BASE+0x0000000)
+#define CMA_MB_RAM_SIZE		0x2000000	/* dip sws set actual size */
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
+#define CMA_MB_SLOT1_BASE	(CFG_CMA_MB_BASE+0x2000000)
+#define CMA_MB_SLOT1_SIZE	0x2000000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
+#define CMA_MB_SLOT2_BASE	(CFG_CMA_MB_BASE+0x4000000)
+#define CMA_MB_SLOT2_SIZE	0x2000000
+#endif
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
+#define CMA_MB_STDPCI_BASE	(CFG_CMA_MB_BASE+0x4000000)
+#define CMA_MB_STDPCI_SIZE	0x1ff0000
+#define CMA_MB_V360EPC_BASE	(CFG_CMA_MB_BASE+0x5ff0000)
+#define CMA_MB_V360EPC_SIZE	0x10000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
+#define CMA_MB_SLOT3_BASE	(CFG_CMA_MB_BASE+0x6000000)
+#define CMA_MB_SLOT3_SIZE	0x2000000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
+#define CMA_MB_EXTPCI_BASE	(CFG_CMA_MB_BASE+0xa000000)
+#define CMA_MB_EXTPCI_SIZE	0x4000000
+#endif
+
+#define CMA_MB_ROMLOW_BASE	(CFG_CMA_MB_BASE+0xe000000)
+#define CMA_MB_ROMLOW_SIZE	0x800000
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+#define CMA_MB_FLLOW_EXEC_BASE	(CFG_CMA_MB_BASE+0xe000000)
+#define CMA_MB_FLLOW_EXEC_SIZE	0x100000
+#define CMA_MB_FLLOW_RDWR_BASE	(CFG_CMA_MB_BASE+0xe400000)
+#define CMA_MB_FLLOW_RDWR_SIZE	0x400000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
+#define CMA_MB_RTC_BASE		(CFG_CMA_MB_BASE+0xe800000)
+#define CMA_MB_RTC_SIZE		0x4000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
+#define CMA_MB_SERPAR_BASE	(CFG_CMA_MB_BASE+0xe900000)
+#define   CMA_MB_SERIALB_BASE	  (CMA_MB_SERPAR_BASE+0x00)
+#define   CMA_MB_SERIALA_BASE	  (CMA_MB_SERPAR_BASE+0x40)
+#define   CMA_MB_PARALLEL_BASE	  (CMA_MB_SERPAR_BASE+0x80)
+#define CMA_MB_SERPAR_SIZE	0xa0
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
+#define CMA_MB_PKBM_BASE	(CFG_CMA_MB_BASE+0xe900100)
+#define CMA_MB_PKBM_SIZE	0x10
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
+#define CMA_MB_LCD_BASE		(CFG_CMA_MB_BASE+0xeb00000)
+#define CMA_MB_LCD_SIZE		0x10
+#endif
+
+#define CMA_MB_DIPSW_BASE	(CFG_CMA_MB_BASE+0xec00000)
+#define CMA_MB_DIPSW_SIZE	0x10
+
+#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
+#define CMA_MB_SLOT1CFG_BASE	(CFG_CMA_MB_BASE+0xf100000)
+#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define   CMA_MB_SER2_BASE	  (CMA_MB_SLOT1CFG_BASE+0x80)
+#define     CMA_MB_SER2B_BASE	    (CMA_MB_SER2_BASE+0x00)
+#define     CMA_MB_SER2A_BASE	    (CMA_MB_SER2_BASE+0x40)
+#endif
+#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1)
+#define   CMA_MB_S1KBM_BASE	  (CMA_MB_SLOT1CFG_BASE+0x200)
+#endif
+#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150)
+#define   CMA_MB_IREQ1STAT_BASE	  (CMA_MB_SLOT1CFG_BASE+0x100)
+#define   CMA_MB_AKBM_BASE	  (CMA_MB_SLOT1CFG_BASE+0x200)
+#define   CMA_MB_IREQ1MASK_BASE	  (CMA_MB_SLOT1CFG_BASE+0x300)
+#endif
+#define CMA_MB_SLOT1CFG_SIZE	0x400
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
+#define CMA_MB_SLOT2CFG_BASE	(CFG_CMA_MB_BASE+0xf200000)
+#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
+#define   CMA_MB_S2KBM_BASE	  (CMA_MB_SLOT2CFG_BASE+0x200)
+#endif
+#define CMA_MB_SLOT2CFG_SIZE	0x400
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
+#define CMA_MB_PCICTL_BASE	(CFG_CMA_MB_BASE+0xf200000)
+#define   CMA_MB_PCI_V3CTL_BASE	  (CMA_MB_PCICTL_BASE+0x100)
+#define   CMA_MB_PCI_IDSEL_BASE	  (CMA_MB_PCICTL_BASE+0x200)
+#define   CMA_MB_PCI_IMASK_BASE	  (CMA_MB_PCICTL_BASE+0x300)
+#define   CMA_MB_PCI_ISTAT_BASE	  (CMA_MB_PCICTL_BASE+0x400)
+#define   CMA_MB_PCI_MBID_BASE	  (CMA_MB_PCICTL_BASE+0x500)
+#define   CMA_MB_PCI_MBREV_BASE	  (CMA_MB_PCICTL_BASE+0x600)
+#define CMA_MB_PCICTL_SIZE	0x700
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
+#define CMA_MB_SLOT3CFG_BASE	(CFG_CMA_MB_BASE+0xf300000)
+#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
+#define   CMA_MB_S3KBM_BASE	  (CMA_MB_SLOT3CFG_BASE+0x200)
+#endif
+#define CMA_MB_SLOT3CFG_SIZE	0x400
+#endif
+
+#define CMA_MB_ROMHIGH_BASE	(CFG_CMA_MB_BASE+0xf800000)
+#define CMA_MB_ROMHIGH_SIZE	0x800000
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+#define CMA_MB_FLHIGH_EXEC_BASE	(CFG_CMA_MB_BASE+0xf800000)
+#define CMA_MB_FLHIGH_EXEC_SIZE	0x100000
+#define CMA_MB_FLHIGH_RDWR_BASE	(CFG_CMA_MB_BASE+0xfc00000)
+#define CMA_MB_FLHIGH_RDWR_SIZE	0x400000
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
+
+/* PCI Control Register bits */
+
+/* V360EPC Control register bits */
+#define CMA_MB_PCI_V3CTL_RESET	0x01
+#define CMA_MB_PCI_V3CTL_EXTADD	0x08
+
+/* PCI ID Select register bits */
+#define CMA_MB_PCI_IDSEL_SLOTA	0x01
+#define CMA_MB_PCI_IDSEL_SLOTB	0x02
+#define CMA_MB_PCI_IDSEL_GD82559 0x04
+#define CMA_MB_PCI_IDSEL_B69000	0x08
+#define CMA_MB_PCI_IDSEL_PD6832	0x10
+
+/* PCI Interrupt Mask/Status register bits */
+#define CMA_MB_PCI_IMS_INTA	0x01
+#define CMA_MB_PCI_IMS_INTB	0x02
+#define CMA_MB_PCI_IMS_INTC	0x04
+#define CMA_MB_PCI_IMS_INTD	0x08
+#define CMA_MB_PCI_IMS_CBINT	0x10
+#define CMA_MB_PCI_IMS_V3LINT	0x80
+
+#endif
+
+#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150)
+
+/*
+ * IREQ1 Interrupt Mask/Status register bits
+ * (Note: not available on CMA150 - must poll HT6542B interrupt register)
+ */
+
+#define IREQ1_MINT	0x01
+#define IREQ1_KINT	0x02
+#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define IREQ1_SINT2	0x04
+#define IREQ1_SINT3	0x08
+#endif
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+#ifdef USE_HOSTCC
+#include <endian.h>		/* avoid using private kernel header files */
+#else
+#include <asm/byteorder.h>	/* use U-Boot provided headers */
+#endif
+
+/* a single CMA10x motherboard i/o register */
+typedef
+    struct {
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+	unsigned char value;
+#endif
+	unsigned char filler[7];
+#if __BYTE_ORDER == __BIG_ENDIAN
+	unsigned char value;
+#endif
+    }
+cma_mb_reg;
+
+extern __inline__ unsigned char
+cma_mb_reg_read(volatile cma_mb_reg *reg)
+{
+    unsigned char data = reg->value;
+    __asm__ __volatile__ ("eieio" : : : "memory");
+    return data;
+}
+
+extern __inline__ void
+cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data)
+{
+    reg->value = data;
+    __asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
+
+/* MK48T02 RTC registers */
+typedef
+    struct {
+	cma_mb_reg sram[2040];/* Battery-Backed SRAM */
+	cma_mb_reg clk_ctl;	/* Clock Control Register */
+	cma_mb_reg clk_sec;	/* Clock Seconds Register */
+	cma_mb_reg clk_min;	/* Clock Minutes Register */
+	cma_mb_reg clk_hour;	/* Clock Hour Register */
+	cma_mb_reg clk_day;	/* Clock Day Register */
+	cma_mb_reg clk_date;	/* Clock Date Register */
+	cma_mb_reg clk_month;	/* Clock Month Register */
+	cma_mb_reg clk_year;	/* Clock Year Register */
+    }
+cma_mb_rtc;
+
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
+
+/* ST16C522 Serial I/O */
+typedef
+    struct {
+	cma_mb_reg ser_rhr;	/* Receive Holding Register (R, DLAB=0) */
+	cma_mb_reg ser_ier;	/* Interrupt Enable Register (R/W, DLAB=0) */
+	cma_mb_reg ser_isr;	/* Interrupt Status Register (R) */
+	cma_mb_reg ser_lcr;	/* Line Control Register (R/W) */
+	cma_mb_reg ser_mcr;	/* Modem Control Register (R/W) */
+	cma_mb_reg ser_lsr;	/* Line Status Register (R) */
+	cma_mb_reg ser_msr;	/* Modem Status Register (R/W) */
+	cma_mb_reg ser_spr;	/* Scratch Pad Register (R/W) */
+    }
+cma_mb_serial;
+
+#define ser_thr	ser_rhr		/* Transmit Holding Register (W, DLAB=0) */
+#define ser_brl	ser_rhr		/* Baud Rate Divisor Low Byte (R/W, DLAB=1) */
+#define ser_brh	ser_ier		/* Baud Rate Divisor High Byte (R/W, DLAB=1) */
+#define ser_fcr	ser_isr		/* FIFO Control Register (W) */
+#define ser_nop	ser_lsr		/* No Operation (W) */
+
+/* ST16C522 Parallel I/O */
+typedef
+    struct {
+	cma_mb_reg par_rdr;	/* Port Read Data Register (R) */
+	cma_mb_reg par_sr;	/* Status Register (R) */
+	cma_mb_reg par_cmd;	/* Command Register (R) */
+    }
+cma_mb_parallel;
+
+#define par_wdr	par_rdr		/* Port Write Data Register (W) */
+#define par_ios	par_sr		/* I/O Select Register (W) */
+#define par_ctl	par_cmd		/* Control Register (W) */
+
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302)
+
+/* HT6542B PS/2 Keyboard/Mouse Controller */
+typedef
+    struct {
+	cma_mb_reg kbm_rdr;	/* Read Data Register (R) */
+	cma_mb_reg kbm_sr;	/* Status Register (R) */
+    }
+cma_mb_kbm;
+
+#define kbm_wdr	kbm_rdr		/* Write Data Register (W) */
+#define kbm_cmd	kbm_sr		/* Command Register (W) */
+
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
+
+/* HD44780 LCD Display */
+typedef
+    struct {
+	cma_mb_reg lcd_ccr;	/* Current Character Register (R/W) */
+	cma_mb_reg lcd_bsr;	/* Busy Status Register (R) */
+    }
+cma_mb_lcd;
+
+#define lcd_cmd	lcd_bsr		/* Command Register (W) */
+
+#endif
+
+/* 8-Position Configuration Switch */
+typedef
+    struct {
+	cma_mb_reg dip_val;	/* Dip Switch value (R) */
+    }
+cma_mb_dipsw;
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
+
+/* V360EPC PCI Bridge */
+typedef
+    struct {
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+	unsigned short v3_pci_vendor;		/* 0x00 */
+	unsigned short v3_pci_device;
+	unsigned short v3_pci_cmd;		/* 0x04 */
+	unsigned short v3_pci_stat;
+	unsigned long  v3_pci_cc_rev;		/* 0x08 */
+	unsigned long  v3_pci_hdr_cfg;		/* 0x0c */
+	unsigned long  v3_pci_io_base;		/* 0x10 */
+	unsigned long  v3_pci_base0;		/* 0x14 */
+	unsigned long  v3_pci_base1;		/* 0x18 */
+	unsigned long  reserved1[4];		/* 0x1c */
+	unsigned short v3_pci_sub_vendor;	/* 0x2c */
+	unsigned short v3_pci_sub_id;
+	unsigned long  v3_pci_rom;		/* 0x30 */
+	unsigned long  reserved2[2];		/* 0x34 */
+	unsigned long  v3_pci_bparam;		/* 0x3c */
+	unsigned long  v3_pci_map0;		/* 0x40 */
+	unsigned long  v3_pci_map1;		/* 0x44 */
+	unsigned long  v3_pci_int_stat;		/* 0x48 */
+	unsigned long  v3_pci_int_cfg;		/* 0x4c */
+	unsigned long  reserved3[1];		/* 0x50 */
+	unsigned long  v3_lb_base0;		/* 0x54 */
+	unsigned long  v3_lb_base1;		/* 0x58 */
+	unsigned short reserved4;		/* 0x5c */
+	unsigned short v3_lb_map0;
+	unsigned short reserved5;		/* 0x60 */
+	unsigned short v3_lb_map1;
+	unsigned short v3_lb_base2;		/* 0x64 */
+	unsigned short v3_lb_map2;
+	unsigned long  v3_lb_size;		/* 0x68 */
+	unsigned short reserved6;		/* 0x6c */
+	unsigned short v3_lb_io_base;
+	unsigned short v3_fifo_cfg;		/* 0x70 */
+	unsigned short v3_fifo_priority;
+	unsigned short v3_fifo_stat;		/* 0x74 */
+	unsigned char  v3_lb_istat;
+	unsigned char  v3_lb_imask;
+	unsigned short v3_system;		/* 0x78 */
+	unsigned short v3_lb_cfg;
+	unsigned short v3_pci_cfg;		/* 0x7c */
+	unsigned short reserved7;
+	unsigned long  v3_dma_pci_addr0;	/* 0x80 */
+	unsigned long  v3_dma_local_addr0;	/* 0x84 */
+	unsigned long  v3_dma_length0:24;	/* 0x88 */
+	unsigned long  v3_dma_csr0:8;
+	unsigned long  v3_dma_ctlb_adr0;	/* 0x8c */
+	unsigned long  v3_dma_pci_addr1;	/* 0x90 */
+	unsigned long  v3_dma_local_addr1;	/* 0x94 */
+	unsigned long  v3_dma_length1:24;	/* 0x98 */
+	unsigned long  v3_dma_csr1:8;
+	unsigned long  v3_dma_ctlb_adr1;	/* 0x9c */
+	unsigned long  v3_i20_mups[8];		/* 0xa0 */
+	unsigned char  v3_mail_data0;		/* 0xc0 */
+	unsigned char  v3_mail_data1;
+	unsigned char  v3_mail_data2;
+	unsigned char  v3_mail_data3;
+	unsigned char  v3_mail_data4;		/* 0xc4 */
+	unsigned char  v3_mail_data5;
+	unsigned char  v3_mail_data6;
+	unsigned char  v3_mail_data7;
+	unsigned char  v3_mail_data8;		/* 0xc8 */
+	unsigned char  v3_mail_data9;
+	unsigned char  v3_mail_data10;
+	unsigned char  v3_mail_data11;
+	unsigned char  v3_mail_data12;		/* 0xcc */
+	unsigned char  v3_mail_data13;
+	unsigned char  v3_mail_data14;
+	unsigned char  v3_mail_data15;
+	unsigned short v3_pci_mail_iewr;	/* 0xd0 */
+	unsigned short v3_pci_mail_ierd;
+	unsigned short v3_lb_mail_iewr;		/* 0xd4 */
+	unsigned short v3_lb_mail_ierd;
+	unsigned short v3_mail_wr_stat;		/* 0xd8 */
+	unsigned short v3_mail_rd_stat;
+	unsigned long  v3_qba_map;		/* 0xdc */
+	unsigned long  v3_dma_delay:8;		/* 0xe0 */
+	unsigned long  reserved8:24;
+	unsigned long  reserved9[7];		/* 0xe4 */
+#endif
+#if __BYTE_ORDER == __BIG_ENDIAN
+	unsigned short v3_pci_device;		/* 0x00 */
+	unsigned short v3_pci_vendor;
+	unsigned short v3_pci_stat;		/* 0x04 */
+	unsigned short v3_pci_cmd;
+	unsigned long  v3_pci_cc_rev;		/* 0x08 */
+	unsigned long  v3_pci_hdr_cfg;		/* 0x0c */
+	unsigned long  v3_pci_io_base;		/* 0x10 */
+	unsigned long  v3_pci_base0;		/* 0x14 */
+	unsigned long  v3_pci_base1;		/* 0x18 */
+	unsigned long  reserved1[4];		/* 0x1c */
+	unsigned short v3_pci_sub_id;		/* 0x2c */
+	unsigned short v3_pci_sub_vendor;
+	unsigned long  v3_pci_rom;		/* 0x30 */
+	unsigned long  reserved2[2];		/* 0x34 */
+	unsigned long  v3_pci_bparam;		/* 0x3c */
+	unsigned long  v3_pci_map0;		/* 0x40 */
+	unsigned long  v3_pci_map1;		/* 0x44 */
+	unsigned long  v3_pci_int_stat;		/* 0x48 */
+	unsigned long  v3_pci_int_cfg;		/* 0x4c */
+	unsigned long  reserved3;		/* 0x50 */
+	unsigned long  v3_lb_base0;		/* 0x54 */
+	unsigned long  v3_lb_base1;		/* 0x58 */
+	unsigned short v3_lb_map0;		/* 0x5c */
+	unsigned short reserved4;
+	unsigned short v3_lb_map1;		/* 0x60 */
+	unsigned short reserved5;
+	unsigned short v3_lb_map2;		/* 0x64 */
+	unsigned short v3_lb_base2;
+	unsigned long  v3_lb_size;		/* 0x68 */
+	unsigned short v3_lb_io_base;		/* 0x6c */
+	unsigned short reserved6;
+	unsigned short v3_fifo_priority;	/* 0x70 */
+	unsigned short v3_fifo_cfg;
+	unsigned char  v3_lb_imask;		/* 0x74 */
+	unsigned char  v3_lb_istat;
+	unsigned short v3_fifo_stat;
+	unsigned short v3_lb_cfg;		/* 0x78 */
+	unsigned short v3_system;
+	unsigned short reserved7;		/* 0x7c */
+	unsigned short v3_pci_cfg;
+	unsigned long  v3_dma_pci_addr0;	/* 0x80 */
+	unsigned long  v3_dma_local_addr0;	/* 0x84 */
+	unsigned long  v3_dma_csr0:8;		/* 0x88 */
+	unsigned long  v3_dma_length0:24;
+	unsigned long  v3_dma_ctlb_adr0;	/* 0x8c */
+	unsigned long  v3_dma_pci_addr1;	/* 0x90 */
+	unsigned long  v3_dma_local_addr1;	/* 0x94 */
+	unsigned long  v3_dma_csr1:8;		/* 0x98 */
+	unsigned long  v3_dma_length1:24;
+	unsigned long  v3_dma_ctlb_adr1;	/* 0x9c */
+	unsigned long  v3_i20_mups[8];		/* 0xa0 */
+	unsigned char  v3_mail_data3;		/* 0xc0 */
+	unsigned char  v3_mail_data2;
+	unsigned char  v3_mail_data1;
+	unsigned char  v3_mail_data0;
+	unsigned char  v3_mail_data7;		/* 0xc4 */
+	unsigned char  v3_mail_data6;
+	unsigned char  v3_mail_data5;
+	unsigned char  v3_mail_data4;
+	unsigned char  v3_mail_data11;		/* 0xc8 */
+	unsigned char  v3_mail_data10;
+	unsigned char  v3_mail_data9;
+	unsigned char  v3_mail_data8;
+	unsigned char  v3_mail_data15;		/* 0xcc */
+	unsigned char  v3_mail_data14;
+	unsigned char  v3_mail_data13;
+	unsigned char  v3_mail_data12;
+	unsigned short v3_pci_mail_ierd;	/* 0xd0 */
+	unsigned short v3_pci_mail_iewr;
+	unsigned short v3_lb_mail_ierd;		/* 0xd4 */
+	unsigned short v3_lb_mail_iewr;
+	unsigned short v3_mail_rd_stat;		/* 0xd8 */
+	unsigned short v3_mail_wr_stat;
+	unsigned long  v3_qba_map;		/* 0xdc */
+	unsigned long  reserved8:24;		/* 0xe0 */
+	unsigned long  v3_dma_delay:8;
+	unsigned long  reserved9[7];		/* 0xe4 */
+#endif
+    }						/* 0x100 */
+cma_mb_v360epc;
+
+#endif
+
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* _COGENT_MB_H */
diff --git a/board/cogent/par.c b/board/cogent/par.c
new file mode 100755
index 0000000..a03c0f1
--- /dev/null
+++ b/board/cogent/par.c
@@ -0,0 +1,3 @@
+/* parallel not implemented yet */
+
+int cma_parallel_not_implemented = 1;
diff --git a/board/cogent/par.h b/board/cogent/par.h
new file mode 100755
index 0000000..664ae4a
--- /dev/null
+++ b/board/cogent/par.h
@@ -0,0 +1,3 @@
+/* parallel not implemented yet */
+
+extern int cma_parallel_not_implemented;
diff --git a/board/cogent/pci.c b/board/cogent/pci.c
new file mode 100755
index 0000000..0a57c0c
--- /dev/null
+++ b/board/cogent/pci.c
@@ -0,0 +1,3 @@
+/* pci not implemented yet */
+
+int cma_pci_not_implemented = 1;
diff --git a/board/cogent/pci.h b/board/cogent/pci.h
new file mode 100755
index 0000000..35aa354
--- /dev/null
+++ b/board/cogent/pci.h
@@ -0,0 +1,3 @@
+/* pci not implemented yet */
+
+extern int cma_pci_not_implemented;
diff --git a/board/cogent/rtc.c b/board/cogent/rtc.c
new file mode 100755
index 0000000..ace9193
--- /dev/null
+++ b/board/cogent/rtc.c
@@ -0,0 +1,3 @@
+/* rtc not implemented yet */
+
+int cma_rtc_not_implemented = 1;
diff --git a/board/cogent/rtc.h b/board/cogent/rtc.h
new file mode 100755
index 0000000..4b55bd2
--- /dev/null
+++ b/board/cogent/rtc.h
@@ -0,0 +1,3 @@
+/* rtc not implemented yet */
+
+extern int cma_rtc_not_implemented;
diff --git a/board/cogent/serial.c b/board/cogent/serial.c
new file mode 100755
index 0000000..4c20017
--- /dev/null
+++ b/board/cogent/serial.c
@@ -0,0 +1,190 @@
+/*
+ * Simple serial driver for Cogent motherboard serial ports
+ * for use during boot
+ */
+
+#include <common.h>
+#include <board/cogent/serial.h>
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
+
+#if (defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
+     (defined(CONFIG_8260) && defined(CONFIG_CONS_NONE))
+
+#if CONFIG_CONS_INDEX == 1
+#define CMA_MB_SERIAL_BASE	CMA_MB_SERIALA_BASE
+#elif CONFIG_CONS_INDEX == 2
+#define CMA_MB_SERIAL_BASE	CMA_MB_SERIALB_BASE
+#elif CONFIG_CONS_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define CMA_MB_SERIAL_BASE	CMA_MB_SER2A_BASE
+#elif CONFIG_CONS_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define CMA_MB_SERIAL_BASE	CMA_MB_SER2B_BASE
+#else
+#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial
+#endif
+
+int serial_init (void)
+{
+/*  DECLARE_GLOBAL_DATA_PTR; */
+
+    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+
+    cma_mb_reg_write(&mbsp->ser_ier, 0x00);	/* turn off interrupts */
+    serial_setbrg ();
+    cma_mb_reg_write(&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
+    cma_mb_reg_write(&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
+    cma_mb_reg_write(&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
+
+    return (0);
+}
+
+void
+serial_setbrg (void)
+{
+    DECLARE_GLOBAL_DATA_PTR;
+
+    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+    unsigned int divisor;
+    unsigned char lcr;
+
+    if ((divisor = br_to_div(gd->baudrate)) == 0)
+	divisor = DEFDIV;
+
+    lcr = cma_mb_reg_read(&mbsp->ser_lcr);
+    cma_mb_reg_write(&mbsp->ser_lcr, lcr|0x80);/* Access baud rate(set DLAB)*/
+    cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff);
+    cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff);
+    cma_mb_reg_write(&mbsp->ser_lcr, lcr);	/* unset DLAB */
+}
+
+void
+serial_putc(const char c)
+{
+    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+
+    if (c == '\n')
+	serial_putc('\r');
+
+    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0)
+	;
+
+    cma_mb_reg_write(&mbsp->ser_thr, c);
+}
+
+void
+serial_puts(const char *s)
+{
+    while (*s != '\0')
+	serial_putc(*s++);
+}
+
+int
+serial_getc(void)
+{
+    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+
+    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0)
+	;
+
+    return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f);
+}
+
+int
+serial_tstc(void)
+{
+    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_SERIAL_BASE;
+
+    return ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) != 0);
+}
+
+#endif /* CONS_NONE */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && \
+    defined(CONFIG_KGDB_NONE)
+
+#if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
+#error Console and kgdb are on the same serial port - this is not supported
+#endif
+
+#if CONFIG_KGDB_INDEX == 1
+#define CMA_MB_KGDB_SER_BASE	CMA_MB_SERIALA_BASE
+#elif CONFIG_KGDB_INDEX == 2
+#define CMA_MB_KGDB_SER_BASE	CMA_MB_SERIALB_BASE
+#elif CONFIG_KGDB_INDEX == 3 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define CMA_MB_KGDB_SER_BASE	CMA_MB_SER2A_BASE
+#elif CONFIG_KGDB_INDEX == 4 && (CMA_MB_CAPS & CMA_MB_CAP_SER2)
+#define CMA_MB_KGDB_SER_BASE	CMA_MB_SER2B_BASE
+#else
+#error CONFIG_KGDB_INDEX must be configured for Cogent motherboard serial
+#endif
+
+void
+kgdb_serial_init(void)
+{
+    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
+    unsigned int divisor;
+
+    if ((divisor = br_to_div(CONFIG_KGDB_BAUDRATE)) == 0)
+	divisor = DEFDIV;
+
+    cma_mb_reg_write(&mbsp->ser_ier, 0x00);	/* turn off interrupts */
+    cma_mb_reg_write(&mbsp->ser_lcr, 0x80);	/* Access baud rate(set DLAB)*/
+    cma_mb_reg_write(&mbsp->ser_brl, divisor & 0xff);
+    cma_mb_reg_write(&mbsp->ser_brh, (divisor >> 8) & 0xff);
+    cma_mb_reg_write(&mbsp->ser_lcr, 0x03);	/* 8 data, 1 stop, no parity */
+    cma_mb_reg_write(&mbsp->ser_mcr, 0x03);	/* RTS/DTR */
+    cma_mb_reg_write(&mbsp->ser_fcr, 0x07);	/* Clear & enable FIFOs */
+
+    printf("[on cma10x serial port B] ");
+}
+
+void
+putDebugChar(int c)
+{
+    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
+
+    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_THRE) == 0)
+	;
+
+    cma_mb_reg_write(&mbsp->ser_thr, c & 0xff);
+}
+
+void
+putDebugStr(const char *str)
+{
+    while (*str != '\0') {
+	if (*str == '\n')
+	    putDebugChar('\r');
+	putDebugChar(*str++);
+    }
+}
+
+int
+getDebugChar(void)
+{
+    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
+
+    while ((cma_mb_reg_read(&mbsp->ser_lsr) & LSR_DR) == 0)
+	;
+
+    return ((int)cma_mb_reg_read(&mbsp->ser_rhr) & 0x7f);
+}
+
+void
+kgdb_interruptible(int yes)
+{
+    cma_mb_serial *mbsp = (cma_mb_serial *)CMA_MB_KGDB_SER_BASE;
+
+    if (yes == 1) {
+	printf("kgdb: turning serial ints on\n");
+	cma_mb_reg_write(&mbsp->ser_ier, 0xf);
+    }
+    else {
+	printf("kgdb: turning serial ints off\n");
+	cma_mb_reg_write(&mbsp->ser_ier, 0x0);
+    }
+}
+
+#endif /* KGDB && KGDB_NONE */
+
+#endif /* CAPS & SERPAR */
diff --git a/board/cogent/serial.h b/board/cogent/serial.h
new file mode 100755
index 0000000..89962d8
--- /dev/null
+++ b/board/cogent/serial.h
@@ -0,0 +1,15 @@
+/* Line Status Register bits */
+#define LSR_DR		0x01	/* Data ready */
+#define LSR_OE		0x02	/* Overrun */
+#define LSR_PE		0x04	/* Parity error */
+#define LSR_FE		0x08	/* Framing error */
+#define LSR_BI		0x10	/* Break */
+#define LSR_THRE	0x20	/* Xmit holding register empty */
+#define LSR_TEMT	0x40	/* Xmitter empty */
+#define LSR_ERR		0x80	/* Error */
+
+#define CLKRATE		3686400	/* cogent motherboard serial clk = 3.6864MHz */
+#define DEFDIV		1	/* default to 230400 bps */
+
+#define br_to_div(br)	(CLKRATE / (16 * (br)))
+#define div_to_br(div)	(CLKRATE / (16 * (div)))
diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds
new file mode 100755
index 0000000..5ce2694
--- /dev/null
+++ b/board/cogent/u-boot.lds
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug
new file mode 100755
index 0000000..ddd4678
--- /dev/null
+++ b/board/cogent/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile
new file mode 100755
index 0000000..ccb811b
--- /dev/null
+++ b/board/cpc45/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o plx9030.o pd67290.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/cpc45/config.mk b/board/cpc45/config.mk
new file mode 100755
index 0000000..bf9d9de
--- /dev/null
+++ b/board/cpc45/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2001-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CPC45 board
+#
+
+
+ifeq ($(CONFIG_BOOT_ROM),y)
+	TEXT_BASE := 0xFFF00000
+	PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
+else
+	TEXT_BASE := 0xFFF00000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c
new file mode 100755
index 0000000..51b0085
--- /dev/null
+++ b/board/cpc45/cpc45.c
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <i2c.h>
+
+int sysControlDisplay(int digit, uchar ascii_code);
+extern void Plx9030Init(void);
+extern void SPD67290Init(void);
+
+	/* We have to clear the initial data area here. Couldn't have done it
+	 * earlier because DRAM had not been initialized.
+	 */
+int board_early_init_f(void)
+{
+
+	/* enable DUAL UART Mode on CPC45 */
+	*(uchar*)DUART_DCR |= 0x1;	/* set DCM bit */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+/*
+	char  revision = BOARD_REV;
+*/
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	puts ("CPC45  ");
+/*
+	printf("Revision %d ", revision);
+*/
+	printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
+
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	int m, row, col, bank, i, ref;
+	unsigned long start, end;
+	uint32_t mccr1, mccr2;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+	unsigned int tmp;
+
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	if (i2c_reg_read (0x50, 2) != 0x04)
+		return 0;	/* Memory type */
+
+	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
+	row = i2c_reg_read (0x50, 3);	/* # of rows */
+	col = i2c_reg_read (0x50, 4);	/* # of columns */
+	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
+	ref  = i2c_reg_read (0x50, 12);	/* refresh rate / type */
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	CONFIG_READ_WORD(MCCR2, mccr2);
+	mccr2 &= 0xffff0000;
+
+	start = CFG_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	switch(ref) {
+		case 0x00:
+		case 0x80:
+			tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
+			break;
+		case 0x01:
+		case 0x81:
+			tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
+			break;
+		case 0x02:
+		case 0x82:
+			tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
+			break;
+		case 0x03:
+		case 0x83:
+			tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
+			break;
+		case 0x04:
+		case 0x84:
+			tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
+			break;
+		case 0x05:
+		case 0x85:
+			tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
+			break;
+		default:
+			tmp = 0x512;
+			break;
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+static struct pci_config_table pci_cpc45_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
+				       PCI_PLX9030_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0E, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCMCIA_IO_BASE,
+				       PCMCIA_IO_BASE,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_IO }},
+#endif /*CONFIG_PCI_PNP*/
+	{ }
+};
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_cpc45_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+
+	/* init PCI_to_LOCAL Bus BRIDGE */
+	Plx9030Init();
+
+	/* Clear Display */
+	DISP_CWORD = 0x0;
+
+	sysControlDisplay(0,' ');
+	sysControlDisplay(1,'C');
+	sysControlDisplay(2,'P');
+	sysControlDisplay(3,'C');
+	sysControlDisplay(4,' ');
+	sysControlDisplay(5,'4');
+	sysControlDisplay(6,'5');
+	sysControlDisplay(7,' ');
+
+}
+
+/**************************************************************************
+*
+* sysControlDisplay - controls one of the Alphanum. Display digits.
+*
+* This routine will write an ASCII character to the display digit requested.
+*
+* SEE ALSO:
+*
+* RETURNS: NA
+*/
+
+int sysControlDisplay (int digit,	/* number of digit 0..7 */
+		       uchar ascii_code	/* ASCII code */
+		      )
+{
+	if ((digit < 0) || (digit > 7))
+		return (-1);
+
+	*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;
+
+	return (0);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+
+#ifdef CFG_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
+#endif
+
+int pcmcia_init(void)
+{
+	u_int rc;
+
+	debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
+
+	rc = i82365_init();
+
+	return rc;
+}
+
+#endif	/* CFG_CMD_PCMCIA */
+
+# ifdef CONFIG_IDE_LED
+void ide_led (uchar led, uchar status)
+{
+	u_char  val;
+	/* We have one PCMCIA slot and use LED H4 for the IDE Interface */
+	val = readb(BCSR_BASE + 0x04);
+	if (status) {				/* led on */
+		val |= B_CTRL_LED0;
+	} else {
+		val &= ~B_CTRL_LED0;
+	}
+	writeb(val, BCSR_BASE + 0x04);
+}
+# endif
diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c
new file mode 100755
index 0000000..37dd182
--- /dev/null
+++ b/board/cpc45/flash.c
@@ -0,0 +1,522 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x40000
+#define PARAM_SECT_SIZE 0x8000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+static int write_data (flash_info_t * info, ulong dest, ulong * data);
+static void write_via_fpu (vu_long * addr, ulong * data);
+static __inline__ unsigned long get_msr (void);
+static __inline__ void set_msr (unsigned long msr);
+
+/*---------------------------------------------------------------------*/
+#undef	DEBUG_FLASH
+
+/*---------------------------------------------------------------------*/
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+	uchar tempChar;
+	vu_long *tmpaddr;
+
+	/* Enable flash writes on CPC45 */
+
+	tempChar = BOARD_CTRL;
+
+	tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
+
+	tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
+
+	BOARD_CTRL = tempChar;
+
+	__asm__ volatile ("sync\n eieio");
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+		addr[0] = 0x00900090;
+
+		__asm__ volatile ("sync\n eieio");
+
+		udelay (100);
+
+		DEBUGF ("Flash bank # %d:\n"
+			"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+			"\tDevice ID @ 0x%08lX: 0x%08lX\n",
+			i,
+			(ulong) (&addr[0]), addr[0],
+			(ulong) (&addr[2]), addr[2]);
+
+
+		if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+		    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {
+
+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160F3T & FLASH_TYPEMASK);
+
+		} else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
+			 && (addr[2] == addr[3])
+			 && (addr[2] == INTEL_ID_28F160C3T)) {
+
+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160C3T & FLASH_TYPEMASK);
+
+		} else {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			addr[0] = 0xFFFFFFFF;
+			goto Done;
+		}
+
+		DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+		addr[0] = 0xFFFFFFFF;
+
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j > 30) {
+				flash_info[i].start[j] = CFG_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					(MAIN_SECT_SIZE * 31) + (j -
+								 31) *
+					PARAM_SECT_SIZE;
+			} else {
+				flash_info[i].start[j] = CFG_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					j * MAIN_SECT_SIZE;
+			}
+		}
+
+		/* unlock sectors, if 160C3T */
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			tmpaddr = (vu_long *) flash_info[i].start[j];
+
+			if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			    (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
+				tmpaddr[0] = 0x00600060;
+				tmpaddr[0] = 0x00D000D0;
+				tmpaddr[1] = 0x00600060;
+				tmpaddr[1] = 0x00D000D0;
+			}
+		}
+
+		size += flash_info[i].size;
+
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[1]);
+#else
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
+#else
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+#endif
+
+Done:
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch ((i = info->flash_id & FLASH_VENDMASK)) {
+	case (FLASH_MAN_INTEL & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor 0x%04x ", i);
+		break;
+	}
+
+	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
+	case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
+		printf ("28F160F3T (16Mbit)\n");
+		break;
+
+	case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
+		printf ("28F160C3T (16Mbit)\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type 0x%04x\n", i);
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
+		info - &flash_info[0], s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+
+			DEBUGF ("Erase sect %d @ 0x%08lX\n",
+				sect, (ulong) addr);
+
+			/* Disable interrupts which might cause a timeout
+			 * here.
+			 */
+			flag = disable_interrupts ();
+
+			addr[0] = 0x00500050;	/* clear status register */
+			addr[0] = 0x00200020;	/* erase setup */
+			addr[0] = 0x00D000D0;	/* erase confirm */
+
+			addr[1] = 0x00500050;	/* clear status register */
+			addr[1] = 0x00200020;	/* erase setup */
+			addr[1] = 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((addr[0] & 0x00800080) != 0x00800080) ||
+			       ((addr[1] & 0x00800080) != 0x00800080)) {
+				if ((now = get_timer (start)) >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					addr[0] = 0x00B000B0;	/* suspend erase */
+					addr[0] = 0x00FF00FF;	/* to read mode  */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second  */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			addr[0] = 0x00FF00FF;
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	8	/* flash bus width in bytes */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, cp, msr;
+	int l, rc, i;
+	ulong data[2];
+	ulong *datah = &data[0];
+	ulong *datal = &data[1];
+
+	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
+		addr, (ulong) src, cnt);
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	msr = get_msr ();
+	set_msr (msr | MSR_FP);
+
+	wp = (addr & ~(FLASH_WIDTH - 1));	/* get lower aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		*datah = *datal = 0;
+
+		for (i = 0, cp = wp; i < l; i++, cp++) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+					((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | (*(uchar *) cp);
+		}
+		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
+			char tmp = *src++;
+
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+					((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | tmp;
+			--cnt;
+			++cp;
+		}
+
+		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+					((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datah << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
+			return (rc);
+		}
+
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		*datah = *(ulong *) src;
+		*datal = *(ulong *) (src + 4);
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+		src += FLASH_WIDTH;
+	}
+
+	if (cnt == 0) {
+		set_msr (msr);
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	*datah = *datal = 0;
+	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
+		char tmp = *src++;
+
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
+		}
+
+		*datal = (*datal << 8) | tmp;
+		--cnt;
+	}
+
+	for (; i < FLASH_WIDTH; ++i, ++cp) {
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
+		}
+
+		*datal = (*datal << 8) | (*(uchar *) cp);
+	}
+
+	rc = write_data (info, wp, data);
+	set_msr (msr);
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, ulong * data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((addr[0] & data[0]) != data[0]) ||
+	    ((addr[1] & data[1]) != data[1])) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[0] = 0x00400040;	/* write setup */
+	write_via_fpu (addr, data);
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((addr[0] & 0x00800080) != 0x00800080) ||
+	       ((addr[1] & 0x00800080) != 0x00800080)) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			addr[0] = 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	addr[0] = 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu (vu_long * addr, ulong * data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
+}
+
+/*-----------------------------------------------------------------------
+ */
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+
+	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+}
diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c
new file mode 100755
index 0000000..c84fbae
--- /dev/null
+++ b/board/cpc45/pd67290.c
@@ -0,0 +1,68 @@
+/* pd67290.c - system configuration module for SPD67290
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * (C) 2004 DENX Software Engineering, Heiko Schocher <hs@denx.de>
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+/* imports */
+#include <mpc824x.h>
+
+static struct pci_device_id supported[] = {
+	{PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
+	{}
+};
+
+/***************************************************************************
+*
+* SPD67290Init -
+*
+* RETURNS: -1 on error, 0 if OK
+*/
+
+int SPD67290Init (void)
+{
+	pci_dev_t devno;
+	int idx = 0;		/* general index */
+	ulong membaseCsr;	/* base address of device memory space */
+
+	/* find PD67290 device */
+	if ((devno = pci_find_devices (supported, idx++)) < 0) {
+		printf ("No PD67290 device found !!\n");
+		return -1;
+	}
+	/* - 0xfe000000 see MPC 8245 Users Manual Adress Map B */
+	membaseCsr = PCMCIA_IO_BASE - 0xfe000000;
+
+	/* set base address */
+	pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, membaseCsr);
+
+	/* enable mapped memory and IO addresses */
+	pci_write_config_dword (devno,
+				PCI_COMMAND,
+				PCI_COMMAND_MEMORY |
+				PCI_COMMAND_IO | PCI_COMMAND_WAIT);
+	return 0;
+}
diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c
new file mode 100755
index 0000000..99ec39a
--- /dev/null
+++ b/board/cpc45/plx9030.c
@@ -0,0 +1,173 @@
+/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */
+/*
+ * (C) Copyright 2002-2003
+ * Josef Wagner, MicroSys GmbH, wagner@microsys.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *   Date       Modification                                      by
+ * -------      ----------------------------------------------    ---
+ * 30sep02      converted from VxWorks to LINUX                   wa
+*/
+
+
+/*
+DESCRIPTION
+
+This is the configuration module for the PLX9030 PCI to Local Bus Bridge.
+It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local
+registers (CS3) on CPC45.
+*/
+
+/* includes */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+
+/* imports */
+
+
+/* defines */
+#define	PLX9030_VENDOR_ID	0x10B5
+#define	PLX9030_DEVICE_ID	0x9030
+
+#undef PLX_DEBUG
+
+/* PLX9030 register offsets  */
+#define	P9030_LAS0RR	0x00
+#define	P9030_LAS1RR 	0x04
+#define	P9030_LAS2RR	0x08
+#define	P9030_LAS3RR	0x0c
+#define	P9030_EROMRR	0x10
+#define	P9030_LAS0BA	0x14
+#define	P9030_LAS1BA	0x18
+#define	P9030_LAS2BA	0x1c
+#define	P9030_LAS3BA	0x20
+#define	P9030_EROMBA	0x24
+#define	P9030_LAS0BRD	0x28
+#define	P9030_LAS1BRD	0x2c
+#define	P9030_LAS2BRD	0x30
+#define	P9030_LAS3BRD	0x34
+#define	P9030_EROMBRD	0x38
+#define	P9030_CS0BASE	0x3C
+#define	P9030_CS1BASE	0x40
+#define	P9030_CS2BASE	0x44
+#define	P9030_CS3BASE	0x48
+#define	P9030_INTCSR 	0x4c
+#define	P9030_CNTRL  	0x50
+#define	P9030_GPIOC	0x54
+
+/* typedefs */
+
+
+/* locals */
+
+static struct pci_device_id supported[] = {
+	{ PLX9030_VENDOR_ID, PLX9030_DEVICE_ID },
+	{ }
+};
+
+/* forward declarations */
+void sysOutLong(ulong address, ulong value);
+
+
+/***************************************************************************
+*
+* Plx9030Init - init CS0..CS3 for CPC45
+*
+*
+* RETURNS: N/A
+*/
+
+void Plx9030Init (void)
+{
+    pci_dev_t   devno;
+    ulong	membaseCsr;	  /* base address of device memory space */
+    int		idx = 0;	  /* general index */
+
+
+    /* find plx9030 device */
+
+    if ((devno = pci_find_devices(supported, idx++)) < 0)
+    {
+	printf("No PLX9030 device found !!\n");
+	return;
+    }
+
+
+#ifdef PLX_DEBUG
+	printf("PLX 9030 device found ! devno = 0x%x\n",devno);
+#endif
+
+	membaseCsr   = PCI_PLX9030_MEMADDR;
+
+	/* set base address */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr);
+
+	/* enable mapped memory and IO addresses */
+	pci_write_config_dword(devno,
+			       PCI_COMMAND,
+			       PCI_COMMAND_MEMORY |
+			       PCI_COMMAND_MASTER);
+
+
+	/* configure GBIOC */
+	sysOutLong((membaseCsr + P9030_GPIOC),   0x00000FC0);		/* CS2/CS3 enable */
+
+	/* configure CS0 (SRAM) */
+	sysOutLong((membaseCsr + P9030_LAS0BA),  0x00000001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS0RR),  0x0FE00000);		/* 2 MByte */
+	sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900);		/* 4 wait states */
+	sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001);		/* enable 2 MByte */
+	/* remap CS0 (SRAM) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE);
+
+	/* configure CS1 (ST16552 / CHAN A) */
+	sysOutLong((membaseCsr + P9030_LAS1BA),  0x00400001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS1RR),  0x0FFFFF00);		/* 256 byte */
+	sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900);		/* 4 wait states */
+	sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081);		/* enable 256 Byte */
+	/* remap CS1 (ST16552 / CHAN A) */
+	/* remap CS1 (ST16552 / CHAN A) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE);
+
+	/* configure CS2 (ST16552 / CHAN B) */
+	sysOutLong((membaseCsr + P9030_LAS2BA),  0x00800001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS2RR),  0x0FFFFF00);		/* 256 byte */
+	sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900);		/* 4 wait states */
+	sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081);		/* enable 256 Byte */
+	/* remap CS2 (ST16552 / CHAN B) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE);
+
+	/* configure CS3 (BCSR) */
+	sysOutLong((membaseCsr + P9030_LAS3BA),  0x00C00001);		/* enable space base */
+	sysOutLong((membaseCsr + P9030_LAS3RR),  0x0FFFFF00);		/* 256 byte */
+	sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80);		/* 9 wait states */
+	sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081);		/* enable 256 Byte */
+	/* remap CS3 (DISPLAY and BCSR) */
+	pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE);
+}
+
+void sysOutLong(ulong address, ulong value)
+{
+	*(ulong*)address = cpu_to_le32(value);
+}
diff --git a/board/cpc45/u-boot.lds b/board/cpc45/u-boot.lds
new file mode 100755
index 0000000..9ea26aa
--- /dev/null
+++ b/board/cpc45/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o (.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+		. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+		*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cpu86/Makefile b/board/cpu86/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/cpu86/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/cpu86/config.mk b/board/cpu86/config.mk
new file mode 100755
index 0000000..00354c4
--- /dev/null
+++ b/board/cpu86/config.mk
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CPU86 boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_CPU86.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+
+ifeq ($(CONFIG_BOOT_ROM),y)
+	TEXT_BASE := 0xFF800000
+	PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
+else
+	TEXT_BASE := 0xFF000000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c
new file mode 100755
index 0000000..3eb5b35
--- /dev/null
+++ b/board/cpu86/cpu86.c
@@ -0,0 +1,321 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "cpu86.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
+	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
+	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
+	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+			  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	ulong size8, size9;
+#endif
+	long psize;
+
+	psize = 32 * 1024 * 1024;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+			  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+			  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+				  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+
+#endif	/* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h
new file mode 100755
index 0000000..cf7852c
--- /dev/null
+++ b/board/cpu86/cpu86.h
@@ -0,0 +1,27 @@
+#ifndef __BOARD_CPU86__
+#define __BOARD_CPU86__
+
+#include <config.h>
+
+#define REG8(x)			(*(volatile unsigned char *)(x))
+
+/* CPU86 register definitions */
+#define CPU86_VME_EAC		REG8(CFG_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC		REG8(CFG_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC		REG8(CFG_BCRS_BASE + 0x02)
+#define CPU86_BCR		REG8(CFG_BCRS_BASE + 0x03)
+#define CPU86_BSR		REG8(CFG_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT	REG8(CFG_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ		REG8(CFG_BCRS_BASE + 0x04)
+#define CPU86_REV		REG8(CFG_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK	REG8(CFG_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK	REG8(CFG_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x84)
+
+/* Board Control Register bits */
+#define CPU86_BCR_FWPT		0x01
+#define CPU86_BCR_FWRE		0x02
+
+#endif /* __BOARD_CPU86__ */
diff --git a/board/cpu86/flash.c b/board/cpu86/flash.c
new file mode 100755
index 0000000..1535a6b
--- /dev/null
+++ b/board/cpu86/flash.c
@@ -0,0 +1,615 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "cpu86.h"
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_int_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write identify command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00900090;
+	baseaddr[1] = 0x00900090;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
+{
+	short i;
+	uchar vendor, devid;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x90;
+
+	udelay(1000);
+
+	vendor = addr[0];
+	devid = addr[1] & 0xff;
+
+	/* only support AMD */
+	if (vendor != 0x01) {
+		return 0;
+	}
+
+	vendor &= 0xf;
+	devid &= 0xff;
+
+	if (devid == AMD_ID_F040B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 8;
+		info->size         = info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F080B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 16;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F016D) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 32;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else {
+		printf ("## Unknown Flash Type: %02x\n", devid);
+		return 0;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* sector base address */
+		info->start[i] = base + i * (info->size / info->sector_count);
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_char *)info->start[0];
+		addr[0] = 0xF0; /* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	unsigned long size_b1 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Disable flash protection */
+	CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]);
+	size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]);
+
+	if (size_b0 > 0 || size_b1 > 0) {
+
+		printf("(");
+
+		if (size_b0 > 0) {
+			puts ("Bank#1 - ");
+			print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
+		}
+
+		if (size_b1 > 0) {
+			puts ("Bank#2 - ");
+			print_size (size_b1, ") ");
+		}
+	}
+	else {
+		printf ("## No FLASH found.\n");
+		return 0;
+	}
+	/* protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE
+	if (size_b1) {
+		/* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE
+		 * but we shouldn't protect it.
+		 */
+
+		flash_protect  (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+		);
+	}
+#else
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+#endif
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE
+	if (size_b1) {
+		flash_protect (FLAG_PROTECT_SET,
+				CFG_ENV_ADDR,
+				CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
+	}
+# else
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+# endif
+#endif
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	case 0x1:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 Mbit, bottom sector)\n");
+		break;
+	case AMD_ID_F040B:
+		printf ("AM29F040B (4 Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if (info->size < 0x100000)
+		printf ("  Size: %ld KB in %d Sectors\n",
+				info->size >> 10, info->sector_count);
+	else
+		printf ("  Size: %ld MB in %d Sectors\n",
+				info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Check the type of erased flash
+	 */
+	if (info->flash_id >> 16 == 0x1) {
+		/* Erase AMD flash
+		 */
+		l_sect = -1;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+		addr[0x0555] = 0x80;
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect<=s_last; sect++) {
+			if (info->protect[sect] == 0) { /* not protected */
+				addr = (vu_char *)(info->start[sect]);
+				addr[0] = 0x30;
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto AMD_DONE;
+
+		start = get_timer (0);
+		last  = start;
+		addr = (vu_char *)(info->start[l_sect]);
+		while ((addr[0] & 0x80) != 0x80) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {      /* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+AMD_DONE:
+		/* reset to read mode */
+		addr = (volatile unsigned char *)info->start[0];
+		addr[0] = 0xF0;     /* reset bank */
+
+	} else {
+		/* Erase Intel flash
+		 */
+
+		/* Start erase on unprotected sectors
+		 */
+		for (sect = s_first; sect <= s_last; sect++) {
+			volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+			start = get_timer (0);
+			last = start;
+			if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+				flag = disable_interrupts ();
+
+				/* Erase the block
+				 */
+				addr[0] = 0x00200020;
+				addr[1] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				addr[1] = 0x00D000D0;
+
+				/* re-enable interrupts if necessary
+				 */
+				if (flag)
+					enable_interrupts ();
+
+				/* wait at least 80us - let's wait 1 ms
+				 */
+				udelay (1000);
+
+				last = start;
+				while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+					if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+						printf ("Timeout (erase suspended!)\n");
+						/* Suspend erase
+						 */
+						addr[0] = 0x00B000B0;
+						addr[1] = 0x00B000B0;
+						goto DONE;
+					}
+					/* show that we're waiting
+					 */
+					if ((now - last) > 1000) {	/* every second */
+						serial_putc ('.');
+						last = now;
+					}
+				}
+				if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+					printf ("*** ERROR: erase failed!\n");
+					goto DONE;
+				}
+			}
+			/* Clear status register and reset to read mode
+			 */
+			addr[0] = 0x00500050;
+			addr[1] = 0x00500050;
+			addr[0] = 0x00FF00FF;
+			addr[1] = 0x00FF00FF;
+		}
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, rc, cc = cnt, res = 0;
+
+	if (info->flash_id >> 16 == 0x1) {
+
+		/* Write to AMD 8-bit flash
+		 */
+		while (cnt > 0) {
+			if ((rc = write_byte(info, addr, *src)) != 0) {
+				return (rc);
+			}
+			addr++;
+			src++;
+			cnt--;
+		}
+
+		return (0);
+	} else {
+
+		/* Write to Intel 64-bit flash
+		 */
+		for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+			l = (addr & 3);
+			addr &= ~3;
+
+			for (i = 0; i < 4; i++) {
+				v = (v << 8) + (i < l || i - l >= cc ?
+					*((unsigned char *) addr + i) : *src++);
+			}
+
+			if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+				break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/cpu86/u-boot.lds b/board/cpu86/u-boot.lds
new file mode 100755
index 0000000..05f29c6
--- /dev/null
+++ b/board/cpu86/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cpu87/Makefile b/board/cpu87/Makefile
new file mode 100755
index 0000000..26f53ed
--- /dev/null
+++ b/board/cpu87/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/cpu87/config.mk b/board/cpu87/config.mk
new file mode 100755
index 0000000..6384c78
--- /dev/null
+++ b/board/cpu87/config.mk
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CPU87 board
+#
+
+# This should be equal to the CFG_FLASH_BASE define in configs/cpu87.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+
+ifeq ($(CONFIG_BOOT_ROM),y)
+	TEXT_BASE := 0xFF800000
+	PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
+else
+	TEXT_BASE := 0xFF000000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c
new file mode 100755
index 0000000..8363d86
--- /dev/null
+++ b/board/cpu87/cpu87.c
@@ -0,0 +1,333 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "cpu87.h"
+#include <pci.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
+	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
+	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
+	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV);
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+			  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	ulong size8, size9;
+#endif
+	long psize;
+
+	psize = 32 * 1024 * 1024;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+			  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+			  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+				  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+
+#endif	/* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/board/cpu87/cpu87.h b/board/cpu87/cpu87.h
new file mode 100755
index 0000000..5dbd4ae
--- /dev/null
+++ b/board/cpu87/cpu87.h
@@ -0,0 +1,27 @@
+#ifndef __BOARD_CPU87__
+#define __BOARD_CPU87__
+
+#include <config.h>
+
+#define REG8(x)			(*(volatile unsigned char *)(x))
+
+/* CPU86 register definitions */
+#define CPU86_VME_EAC		REG8(CFG_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC		REG8(CFG_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC		REG8(CFG_BCRS_BASE + 0x02)
+#define CPU86_BCR		REG8(CFG_BCRS_BASE + 0x03)
+#define CPU86_BSR		REG8(CFG_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT	REG8(CFG_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ		REG8(CFG_BCRS_BASE + 0x04)
+#define CPU86_REV		REG8(CFG_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK	REG8(CFG_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK	REG8(CFG_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x84)
+
+/* Board Control Register bits */
+#define CPU86_BCR_FWPT		0x01
+#define CPU86_BCR_FWRE		0x02
+
+#endif /* __BOARD_CPU87__ */
diff --git a/board/cpu87/flash.c b/board/cpu87/flash.c
new file mode 100755
index 0000000..076c2f9
--- /dev/null
+++ b/board/cpu87/flash.c
@@ -0,0 +1,624 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "cpu87.h"
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_int_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write identify command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00900090;
+	baseaddr[1] = 0x00900090;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
+{
+	short i;
+	uchar vendor, devid;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x90;
+
+	udelay(1000);
+
+	vendor = addr[0];
+	devid = addr[1] & 0xff;
+
+	/* only support AMD */
+	if (vendor != 0x01) {
+		return 0;
+	}
+
+	vendor &= 0xf;
+	devid &= 0xff;
+
+	if (devid == AMD_ID_F040B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 8;
+		info->size         = info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F080B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 16;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F016D) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 32;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else {
+		printf ("## Unknown Flash Type: %02x\n", devid);
+		return 0;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* sector base address */
+		info->start[i] = base + i * (info->size / info->sector_count);
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_char *)info->start[0];
+		addr[0] = 0xF0; /* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	unsigned long size_b1 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Disable flash protection */
+	CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]);
+	size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]);
+
+	if (size_b0 > 0 || size_b1 > 0) {
+
+		printf("(");
+
+		if (size_b0 > 0) {
+			puts ("Bank#1 - ");
+			print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
+		}
+
+		if (size_b1 > 0) {
+			puts ("Bank#2 - ");
+			print_size (size_b1, ") ");
+		}
+	}
+	else {
+		printf ("## No FLASH found.\n");
+		return 0;
+	}
+	/* protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE
+	if (size_b1) {
+		/* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE
+		 * but we shouldn't protect it.
+		 */
+
+		flash_protect  (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+		);
+	}
+#else
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+#endif
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE
+	if (size_b1) {
+		flash_protect (FLAG_PROTECT_SET,
+				CFG_ENV_ADDR,
+				CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
+	}
+# else
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+# endif
+#endif
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	case 0x1:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
+	case AMD_ID_F040B:
+		printf ("AM29F040B (4 Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if (info->size < 0x100000)
+		printf ("  Size: %ld KB in %d Sectors\n",
+				info->size >> 10, info->sector_count);
+	else
+		printf ("  Size: %ld MB in %d Sectors\n",
+				info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Check the type of erased flash
+	 */
+	if (info->flash_id >> 16 == 0x1) {
+		/* Erase AMD flash
+		 */
+		l_sect = -1;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+		addr[0x0555] = 0x80;
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect<=s_last; sect++) {
+			if (info->protect[sect] == 0) { /* not protected */
+				addr = (vu_char *)(info->start[sect]);
+				addr[0] = 0x30;
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto AMD_DONE;
+
+		start = get_timer (0);
+		last  = start;
+		addr = (vu_char *)(info->start[l_sect]);
+		while ((addr[0] & 0x80) != 0x80) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {      /* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+AMD_DONE:
+		/* reset to read mode */
+		addr = (volatile unsigned char *)info->start[0];
+		addr[0] = 0xF0;     /* reset bank */
+
+	} else {
+		/* Erase Intel flash
+		 */
+
+		/* Start erase on unprotected sectors
+		 */
+		for (sect = s_first; sect <= s_last; sect++) {
+			volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+			start = get_timer (0);
+			last = start;
+			if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+				flag = disable_interrupts ();
+
+				/* Erase the block
+				 */
+				addr[0] = 0x00200020;
+				addr[1] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				addr[1] = 0x00D000D0;
+
+				/* re-enable interrupts if necessary
+				 */
+				if (flag)
+					enable_interrupts ();
+
+				/* wait at least 80us - let's wait 1 ms
+				 */
+				udelay (1000);
+
+				last = start;
+				while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+					if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+						printf ("Timeout (erase suspended!)\n");
+						/* Suspend erase
+						 */
+						addr[0] = 0x00B000B0;
+						addr[1] = 0x00B000B0;
+						goto DONE;
+					}
+					/* show that we're waiting
+					 */
+					if ((now - last) > 1000) {	/* every second */
+						serial_putc ('.');
+						last = now;
+					}
+				}
+				if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+					printf ("*** ERROR: erase failed!\n");
+					goto DONE;
+				}
+			}
+			/* Clear status register and reset to read mode
+			 */
+			addr[0] = 0x00500050;
+			addr[1] = 0x00500050;
+			addr[0] = 0x00FF00FF;
+			addr[1] = 0x00FF00FF;
+		}
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, rc, cc = cnt, res = 0;
+
+	if (info->flash_id >> 16 == 0x1) {
+
+		/* Write to AMD 8-bit flash
+		 */
+		while (cnt > 0) {
+			if ((rc = write_byte(info, addr, *src)) != 0) {
+				return (rc);
+			}
+			addr++;
+			src++;
+			cnt--;
+		}
+
+		return (0);
+	} else {
+
+		/* Write to Intel 64-bit flash
+		 */
+		for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+			l = (addr & 3);
+			addr &= ~3;
+
+			for (i = 0; i < 4; i++) {
+				v = (v << 8) + (i < l || i - l >= cc ?
+					*((unsigned char *) addr + i) : *src++);
+			}
+
+			if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+				break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/cpu87/u-boot.lds b/board/cpu87/u-boot.lds
new file mode 100755
index 0000000..fb7e665
--- /dev/null
+++ b/board/cpu87/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cradle/Makefile b/board/cradle/Makefile
new file mode 100755
index 0000000..265d500
--- /dev/null
+++ b/board/cradle/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cradle.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/cradle/config.mk b/board/cradle/config.mk
new file mode 100755
index 0000000..aa40388
--- /dev/null
+++ b/board/cradle/config.mk
@@ -0,0 +1,2 @@
+TEXT_BASE = 0xa0f80000
+#TEXT_BASE = 0
diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
new file mode 100755
index 0000000..6f65f32
--- /dev/null
+++ b/board/cradle/cradle.c
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/* local prototypes */
+void set_led (int led, int color);
+void error_code_halt (int code);
+int init_sio (int led, unsigned long base);
+inline void cradle_outb (unsigned short val, unsigned long base,
+			 unsigned long reg);
+inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
+inline void sleep (int i);
+
+inline void
+/**********************************************************/
+sleep (int i)
+/**********************************************************/
+{
+	while (i--) {
+		udelay (1000000);
+	}
+}
+
+void
+/**********************************************************/
+error_code_halt (int code)
+/**********************************************************/
+{
+	while (1) {
+		led_code (code, RED);
+		sleep (1);
+		led_code (0, OFF);
+		sleep (1);
+	}
+}
+
+void
+/**********************************************************/
+led_code (int code, int color)
+/**********************************************************/
+{
+	int i;
+
+	code &= 0xf;		/* only 4 leds */
+
+	for (i = 0; i < 4; i++) {
+		if (code & (1 << i)) {
+			set_led (i, color);
+		} else {
+			set_led (i, OFF);
+		}
+	}
+}
+
+void
+/**********************************************************/
+set_led (int led, int color)
+/**********************************************************/
+{
+	int shift = led * 2;
+	unsigned long mask = 0x3 << shift;
+
+	CRADLE_LED_CLR_REG = mask;	/* clear bits */
+	CRADLE_LED_SET_REG = (color << shift);	/* set bits */
+	udelay (5000);
+}
+
+inline void
+/**********************************************************/
+cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
+/**********************************************************/
+{
+	*(volatile unsigned short *) (base + (reg * 2)) = val;
+}
+
+inline unsigned char
+/**********************************************************/
+cradle_inb (unsigned long base, unsigned long reg)
+/**********************************************************/
+{
+	unsigned short val;
+
+	val = *(volatile unsigned short *) (base + (reg * 2));
+	return (val & 0xff);
+}
+
+int
+/**********************************************************/
+init_sio (int led, unsigned long base)
+/**********************************************************/
+{
+	unsigned char val;
+
+	set_led (led, YELLOW);
+	val = cradle_inb (base, CRADLE_SIO_INDEX);
+	val = cradle_inb (base, CRADLE_SIO_INDEX);
+	if (val != 0) {
+		set_led (led, RED);
+		return -1;
+	}
+
+	/* map SCC2 to COM1 */
+	cradle_outb (0x01, base, CRADLE_SIO_INDEX);
+	cradle_outb (0x00, base, CRADLE_SIO_DATA);
+
+	/* enable SCC2 extended regs */
+	cradle_outb (0x40, base, CRADLE_SIO_INDEX);
+	cradle_outb (0xa0, base, CRADLE_SIO_DATA);
+
+	/* enable SCC2 clock multiplier */
+	cradle_outb (0x51, base, CRADLE_SIO_INDEX);
+	cradle_outb (0x04, base, CRADLE_SIO_DATA);
+
+	/* enable SCC2 */
+	cradle_outb (0x00, base, CRADLE_SIO_INDEX);
+	cradle_outb (0x04, base, CRADLE_SIO_DATA);
+
+	/* map SCC2 DMA to channel 0 */
+	cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
+	cradle_outb (0x09, base, CRADLE_SIO_DATA);
+
+	/* read ID from SIO to check operation */
+	cradle_outb (0xe4, base, 0x3f8 + 0x3);
+	val = cradle_inb (base, 0x3f8 + 0x0);
+	if ((val & 0xf0) != 0x20) {
+		set_led (led, RED);
+		/* disable SCC2 */
+		cradle_outb (0, base, CRADLE_SIO_INDEX);
+		cradle_outb (0, base, CRADLE_SIO_DATA);
+		return -1;
+	}
+	/* set back to bank 0 */
+	cradle_outb (0, base, 0x3f8 + 0x3);
+	set_led (led, GREEN);
+	return 0;
+}
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+/**********************************************************/
+board_late_init (void)
+/**********************************************************/
+{
+	return (0);
+}
+
+int
+/**********************************************************/
+board_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	led_code (0xf, YELLOW);
+
+	/* arch number of HHP Cradle */
+	gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	/* Init SIOs to enable SCC2 */
+	udelay (100000);		/* delay makes it look neat */
+	init_sio (0, CRADLE_SIO1_PHYS);
+	udelay (100000);
+	init_sio (1, CRADLE_SIO2_PHYS);
+	udelay (100000);
+	init_sio (2, CRADLE_SIO3_PHYS);
+	udelay (100000);
+	set_led (3, GREEN);
+
+	return 1;
+}
+
+int
+/**********************************************************/
+dram_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
+
+	return (PHYS_SDRAM_1_SIZE +
+		PHYS_SDRAM_2_SIZE +
+		PHYS_SDRAM_3_SIZE +
+		PHYS_SDRAM_4_SIZE );
+}
diff --git a/board/cradle/flash.c b/board/cradle/flash.c
new file mode 100755
index 0000000..f3f9a8c
--- /dev/null
+++ b/board/cradle/flash.c
@@ -0,0 +1,359 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x400000
+#define MAIN_SECT_SIZE  0x20000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = PHYS_FLASH_1;
+			break;
+		case 1:
+			flashbase = PHYS_FLASH_2;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] =
+				flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i, j;
+
+	for (j = 0; j < CFG_MAX_FLASH_BANKS; j++) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf ("Intel: ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
+			printf ("28F320J3A (32Mbit)\n");
+			break;
+		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+			printf ("28F128J3 (128Mbit)\n");
+			break;
+		default:
+			printf ("Unknown Chip Type\n");
+			goto Done;
+			break;
+		}
+
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+		printf ("  Sector Start Addresses:");
+		for (i = 0; i < info->sector_count; i++) {
+			if ((i % 5) == 0) {
+				printf ("\n   ");
+			}
+			printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+		}
+		printf ("\n");
+		info++;
+	}
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);
+
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while ((*addr & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+
+			/* clear status register command */
+			*addr = 0x50;
+			/* reset to read mode */
+			*addr = 0xFF;
+		}
+		printf ("ok.\n");
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+outahere:
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) dest, val;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* clear status register command */
+	*addr = 0x50;
+
+	/* program set-up command */
+	*addr = 0x40;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((val = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0xB0;
+			goto outahere;
+		}
+	}
+
+	if (val & 0x1A) {	/* check for error */
+		printf ("\nFlash write error %02x at address %08lx\n",
+			(int) val, (unsigned long) dest);
+		if (val & (1 << 3)) {
+			printf ("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if (val & (1 << 1)) {
+			printf ("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if (val & (1 << 4)) {
+			printf ("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}
+
+outahere:
+	/* read array command */
+	*addr = 0xFF;
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S
new file mode 100755
index 0000000..2fd307f
--- /dev/null
+++ b/board/cradle/lowlevel_init.S
@@ -0,0 +1,515 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc  p15,0,\reg,c2,c0,0
+   mov  \reg,\reg
+   sub  pc,pc,#4
+   .endm
+
+   .macro SET_LED val
+   ldr   r6, =CRADLE_LED_CLR_REG
+   ldr   r7, =0
+   str   r7, [r6]
+   ldr   r6, =CRADLE_LED_SET_REG
+   ldr   r7, =\val
+   str   r7, [r6]
+   .endm
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+    mov      r10, lr
+
+    /* Set up GPIO pins first */
+
+   ldr      r0,   =GPSR0
+   ldr      r1,   =CFG_GPSR0_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GPSR1
+   ldr      r1,   =CFG_GPSR1_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GPSR2
+   ldr      r1,   =CFG_GPSR2_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GPCR0
+   ldr      r1,   =CFG_GPCR0_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GPCR1
+   ldr      r1,   =CFG_GPCR1_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GPCR2
+   ldr      r1,   =CFG_GPCR2_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GRER0
+   ldr      r1,   =CFG_GRER0_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GRER1
+   ldr      r1,   =CFG_GRER1_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GRER2
+   ldr      r1,   =CFG_GRER2_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GFER0
+   ldr      r1,   =CFG_GFER0_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GFER1
+   ldr      r1,   =CFG_GFER1_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GFER2
+   ldr      r1,   =CFG_GFER2_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GPDR0
+   ldr      r1,   =CFG_GPDR0_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GPDR1
+   ldr      r1,   =CFG_GPDR1_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GPDR2
+   ldr      r1,   =CFG_GPDR2_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GAFR0_L
+   ldr      r1,   =CFG_GAFR0_L_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GAFR0_U
+   ldr      r1,   =CFG_GAFR0_U_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GAFR1_L
+   ldr      r1,   =CFG_GAFR1_L_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GAFR1_U
+   ldr      r1,   =CFG_GAFR1_U_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GAFR2_L
+   ldr      r1,   =CFG_GAFR2_L_VAL
+   str      r1,   [r0]
+
+   ldr      r0,   =GAFR2_U
+   ldr      r1,   =CFG_GAFR2_U_VAL
+   str      r1,   [r0]
+
+   /* enable GPIO pins */
+   ldr      r0,   =PSSR
+   ldr      r1,   =CFG_PSSR_VAL
+   str      r1,   [r0]
+
+   SET_LED 1
+
+   ldr    r3, =MSC1             /* low - bank 2 Lubbock Registers / SRAM */
+   ldr    r2, =CFG_MSC1_VAL     /* high - bank 3 Ethernet Controller */
+   str    r2, [r3]              /* need to set MSC1 before trying to write to the HEX LEDs */
+   ldr    r2, [r3]              /* need to read it back to make sure the value latches (see MSC section of manual) */
+
+
+/*********************************************************************
+    Initlialize Memory Controller
+
+    See PXA250 Operating System Developer's Guide
+
+    pause for 200 uSecs- allow internal clocks to settle
+    *Note: only need this if hard reset... doing it anyway for now
+*/
+
+    @ Step 1
+   @ ---- Wait 200 usec
+   ldr r3, =OSCR       @ reset the OS Timer Count to zero
+   mov r2, #0
+   str r2, [r3]
+   ldr r4, =0x300         @ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+   ldr r2, [r3]
+   cmp r4, r2
+   bgt 1b
+
+   SET_LED 2
+
+mem_init:
+	@ get memory controller base address
+	ldr     r1,  =MEMC_BASE
+
+
+@****************************************************************************
+@  Step 2
+@
+
+   @ Step 2a
+   @ write msc0, read back to ensure data latches
+   @
+   ldr     r2,   =CFG_MSC0_VAL
+   str     r2,   [r1, #MSC0_OFFSET]
+   ldr     r2,   [r1, #MSC0_OFFSET]
+
+   @ write msc1
+   ldr     r2,  =CFG_MSC1_VAL
+   str     r2,  [r1, #MSC1_OFFSET]
+   ldr     r2,  [r1, #MSC1_OFFSET]
+
+   @ write msc2
+   ldr     r2,  =CFG_MSC2_VAL
+   str     r2,  [r1, #MSC2_OFFSET]
+   ldr     r2,  [r1, #MSC2_OFFSET]
+
+   @ Step 2b
+   @ write mecr
+   ldr     r2,  =CFG_MECR_VAL
+   str     r2,  [r1, #MECR_OFFSET]
+
+   @ write mcmem0
+   ldr     r2,  =CFG_MCMEM0_VAL
+   str     r2,  [r1, #MCMEM0_OFFSET]
+
+   @ write mcmem1
+   ldr     r2,  =CFG_MCMEM1_VAL
+   str     r2,  [r1, #MCMEM1_OFFSET]
+
+   @ write mcatt0
+   ldr     r2,  =CFG_MCATT0_VAL
+   str     r2,  [r1, #MCATT0_OFFSET]
+
+   @ write mcatt1
+   ldr     r2,  =CFG_MCATT1_VAL
+   str     r2,  [r1, #MCATT1_OFFSET]
+
+   @ write mcio0
+   ldr     r2,  =CFG_MCIO0_VAL
+   str     r2,  [r1, #MCIO0_OFFSET]
+
+   @ write mcio1
+   ldr     r2,  =CFG_MCIO1_VAL
+   str     r2,  [r1, #MCIO1_OFFSET]
+
+   /*SET_LED 3 */
+
+   @ Step 2c
+   @ fly-by-dma is defeatured on this part
+   @ write flycnfg
+   @ldr     r2,  =CFG_FLYCNFG_VAL
+   @str     r2,  [r1, #FLYCNFG_OFFSET]
+
+/* FIXME Does this sequence really make sense */
+#ifdef REDBOOT_WAY
+   @ Step 2d
+   @ get the mdrefr settings
+   ldr     r3,  =CFG_MDREFR_VAL
+
+   @ extract DRI field (we need a valid DRI field)
+   @
+   ldr     r2,  =0xFFF
+
+   @ valid DRI field in r3
+   @
+   and     r3,  r3,  r2
+
+   @ get the reset state of MDREFR
+   @
+   ldr     r4,  [r1, #MDREFR_OFFSET]
+
+   @ clear the DRI field
+   @
+   bic     r4,  r4,  r2
+
+   @ insert the valid DRI field loaded above
+   @
+   orr     r4,  r4,  r3
+
+   @ write back mdrefr
+   @
+   str     r4,  [r1, #MDREFR_OFFSET]
+
+   @ *Note: preserve the mdrefr value in r4 *
+
+   /*SET_LED 4 */
+
+@****************************************************************************
+@  Step 3
+@
+@ NO SRAM
+
+   mov   pc, r10
+
+
+@****************************************************************************
+@  Step 4
+@
+
+   @ Assumes previous mdrefr value in r4, if not then read current mdrefr
+
+   @ clear the free-running clock bits
+   @ (clear K0Free, K1Free, K2Free
+   @
+   bic     r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
+
+   @ set K0RUN for CPLD clock
+   @
+   orr   r4,  r4,  #0x00002000
+
+   @ set K1RUN if bank 0 installed
+   @
+   orr   r4,  r4,  #0x00010000
+
+   @ write back mdrefr
+   @
+   str     r4,  [r1, #MDREFR_OFFSET]
+   ldr     r4,  [r1, #MDREFR_OFFSET]
+
+   @ deassert SLFRSH
+   @
+   bic     r4,  r4,  #0x00400000
+
+   @ write back mdrefr
+   @
+   str     r4,  [r1, #MDREFR_OFFSET]
+
+   @ assert E1PIN
+   @
+   orr     r4,  r4,  #0x00008000
+
+   @ write back mdrefr
+   @
+   str     r4,  [r1, #MDREFR_OFFSET]
+   ldr     r4,  [r1, #MDREFR_OFFSET]
+   nop
+   nop
+#else
+   @ Step 2d
+   @ get the mdrefr settings
+   ldr     r3,  =CFG_MDREFR_VAL
+
+   @ write back mdrefr
+   @
+   str     r4,  [r1, #MDREFR_OFFSET]
+
+   @  Step 4
+
+   @ set K0RUN for CPLD clock
+   @
+   orr   r4,  r4,  #0x00002000
+
+   @ set K1RUN for bank 0
+   @
+   orr   r4,  r4,  #0x00010000
+
+   @ write back mdrefr
+   @
+   str     r4,  [r1, #MDREFR_OFFSET]
+   ldr     r4,  [r1, #MDREFR_OFFSET]
+
+   @ deassert SLFRSH
+   @
+   bic     r4,  r4,  #0x00400000
+
+   @ write back mdrefr
+   @
+   str     r4,  [r1, #MDREFR_OFFSET]
+
+   @ assert E1PIN
+   @
+   orr     r4,  r4,  #0x00008000
+
+   @ write back mdrefr
+   @
+   str     r4,  [r1, #MDREFR_OFFSET]
+   ldr     r4,  [r1, #MDREFR_OFFSET]
+   nop
+   nop
+#endif
+
+   @ Step 4d
+   @ fetch platform value of mdcnfg
+   @
+   ldr     r2,  =CFG_MDCNFG_VAL
+
+   @ disable all sdram banks
+   @
+   bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
+   bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+
+   @ program banks 0/1 for bus width
+   @
+   bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
+
+   @ write initial value of mdcnfg, w/o enabling sdram banks
+   @
+   str     r2,  [r1, #MDCNFG_OFFSET]
+
+   @ Step 4e
+   @ pause for 200 uSecs
+   @
+   ldr r3, =OSCR       @ reset the OS Timer Count to zero
+   mov r2, #0
+   str r2, [r3]
+   ldr r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+   ldr r2, [r3]
+   cmp r4, r2
+   bgt 1b
+
+   /*SET_LED 5 */
+
+   /* Why is this here??? */
+   mov    r0, #0x78                @turn everything off
+   mcr    p15, 0, r0, c1, c0, 0      @(caches off, MMU off, etc.)
+
+   @ Step 4f
+   @ Access memory *not yet enabled* for CBR refresh cycles (8)
+   @ - CBR is generated for all banks
+
+   ldr     r2, =CFG_DRAM_BASE
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+
+   @ Step 4g
+   @get memory controller base address
+   @
+   ldr     r1,  =MEMC_BASE
+
+   @fetch current mdcnfg value
+   @
+   ldr     r3,  [r1, #MDCNFG_OFFSET]
+
+   @enable sdram bank 0 if installed (must do for any populated bank)
+   @
+   orr     r3,  r3,  #MDCNFG_DE0
+
+   @write back mdcnfg, enabling the sdram bank(s)
+   @
+   str     r3,  [r1, #MDCNFG_OFFSET]
+
+   @ Step 4h
+   @ write mdmrs
+   @
+   ldr     r2,  =CFG_MDMRS_VAL
+   str     r2,  [r1, #MDMRS_OFFSET]
+
+   @ Done Memory Init
+
+   /*SET_LED 6 */
+
+   @********************************************************************
+   @ Disable (mask) all interrupts at the interrupt controller
+   @
+
+   @ clear the interrupt level register (use IRQ, not FIQ)
+   @
+   mov     r1, #0
+   ldr     r2,  =ICLR
+   str     r1,  [r2]
+
+   @ Set interrupt mask register
+   @
+   ldr     r1,  =CFG_ICMR_VAL
+   ldr     r2,  =ICMR
+   str     r1,  [r2]
+
+   @ ********************************************************************
+   @ Disable the peripheral clocks, and set the core clock
+   @
+
+	@ Turn Off ALL on-chip peripheral clocks for re-configuration
+	@
+   ldr     r1,  =CKEN
+   mov     r2,  #0
+   str     r2,  [r1]
+
+   @ set core clocks
+   @
+   ldr     r2,  =CFG_CCCR_VAL
+   ldr     r1,  =CCCR
+   str     r2,  [r1]
+
+#ifdef ENABLE32KHZ
+   @ enable the 32Khz oscillator for RTC and PowerManager
+   @
+   ldr     r1,  =OSCC
+   mov     r2,  #OSCC_OON
+   str     r2,  [r1]
+
+   @ NOTE:  spin here until OSCC.OOK get set,
+   @        meaning the PLL has settled.
+   @
+60:
+   ldr     r2, [r1]
+   ands    r2, r2, #1
+   beq     60b
+#endif
+
+	@ Turn on needed clocks
+	@
+   ldr     r1,  =CKEN
+   ldr     r2,  =CFG_CKEN_VAL
+   str     r2,  [r1]
+
+   /*SET_LED 7 */
+
+/* Is this needed???? */
+#define NODEBUG
+#ifdef NODEBUG
+   /*Disable software and data breakpoints */
+   mov   r0,#0
+   mcr   p15,0,r0,c14,c8,0  /* ibcr0 */
+   mcr   p15,0,r0,c14,c9,0  /* ibcr1 */
+   mcr   p15,0,r0,c14,c4,0  /* dbcon */
+
+   /*Enable all debug functionality */
+   mov   r0,#0x80000000
+   mcr   p14,0,r0,c10,c0,0  /* dcsr */
+
+#endif
+
+   /*SET_LED 8 */
+
+   mov   pc, r10
+
+@ End lowlevel_init
diff --git a/board/cradle/u-boot.lds b/board/cradle/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/cradle/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
new file mode 100755
index 0000000..a7114eb
--- /dev/null
+++ b/board/cray/L1/L1.c
@@ -0,0 +1,365 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <405gp_i2c.h>
+#include <command.h>
+#include <rtc.h>
+#include <post.h>
+#include <net.h>
+#include <malloc.h>
+
+#define L1_MEMSIZE (32*1024*1024)
+
+/* the std. DHCP stufff */
+#define DHCP_ROUTER       3
+#define DHCP_NETMASK      1
+#define DHCP_BOOTFILE     67
+#define DHCP_ROOTPATH     17
+#define DHCP_HOSTNAME     12
+
+/* some extras used by CRAY
+ *
+ * on the server this looks like:
+ *
+ * option L1-initrd-image code 224 = string;
+ * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image"
+ */
+#define DHCP_L1_INITRD  224
+
+/* new, [better?] way via official vendor-extensions, defining an option
+ * space.
+ * on the server this looks like:
+ *
+ * option space CRAYL1;
+ * option CRAYL1.initrd     code 3 = string;
+ * ..etc...
+ */
+#define DHCP_VENDOR_SPECX   43
+#define DHCP_VX_INITRD       3
+#define DHCP_VX_BOOTCMD      4
+#define DHCP_VX_BOOTARGS     5
+#define DHCP_VX_ROOTDEV      6
+#define DHCP_VX_FROMFLASH    7
+#define DHCP_VX_BOOTSCRIPT   8
+#define DHCP_VX_RCFILE	     9
+#define DHCP_VX_MAGIC        10
+
+/* Things DHCP server can tellme about.  If there's no flash address, then
+ * they dont participate in 'update' to flash, and we force their values
+ * back to '0' every boot to be sure to get them fresh from DHCP.  Yes, I
+ * know this is a pain...
+ *
+ * If I get no bootfile, boot from flash.  If rootpath, use that.  If no
+ * rootpath use initrd in flash.
+ */
+typedef struct dhcp_item_s {
+	u8 dhcp_option;
+	u8 dhcp_vendor_option;
+	char *dhcpvalue;
+	char *envname;
+} dhcp_item_t;
+static dhcp_item_t Things[] = {
+	{DHCP_ROUTER, 0, NULL, "gateway"},
+	{DHCP_NETMASK, 0, NULL, "netmask"},
+	{DHCP_BOOTFILE, 0, NULL, "bootfile"},
+	{DHCP_ROOTPATH, 0, NULL, "rootpath"},
+	{DHCP_HOSTNAME, 0, NULL, "hostname"},
+	{DHCP_L1_INITRD, 0, NULL, "initrd"},
+/* and the other way.. */
+	{DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_FROMFLASH, NULL, "fromflash"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTSCRIPT, NULL, "bootscript"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_RCFILE, NULL, "rcfile"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_BOOTARGS, NULL, "xbootargs"},
+	{DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL},
+	{DHCP_VENDOR_SPECX, DHCP_VX_MAGIC, NULL, NULL}
+};
+
+#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t)))
+
+extern char bootscript[];
+
+/* Here is the boot logic as HUSH script. Overridden by any TFP provided
+ * bootscript file.
+ */
+
+static void init_sdram (void);
+
+/* ------------------------------------------------------------------------- */
+int board_early_init_f (void)
+{
+	/* Running from ROM: global data is still READONLY */
+	init_sdram ();
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000020);	/* set all but FPGA SMI to be non-critical */
+	mtdcr (uicpr, 0xFFFFFFE0);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+int checkboard (void)
+{
+	return (0);
+}
+/* ------------------------------------------------------------------------- */
+
+/* ------------------------------------------------------------------------- */
+int misc_init_r (void)
+{
+	char *s, *e;
+	image_header_t *hdr;
+	time_t timestamp;
+	struct rtc_time tm;
+	char bootcmd[32];
+
+	hdr = (image_header_t *) (CFG_MONITOR_BASE - sizeof (image_header_t));
+	timestamp = (time_t) hdr->ih_time;
+	to_tm (timestamp, &tm);
+	printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d  %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
+
+#define FACTORY_SETTINGS 0xFFFC0000
+	if ((s = getenv ("ethaddr")) == NULL) {
+		e = (char *) (FACTORY_SETTINGS);
+		if (*(e + 0) != '0'
+			|| *(e + 1) != '0'
+			|| *(e + 2) != ':'
+			|| *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') {
+			printf ("No valid MAC address in flash location 0x3C0000!\n");
+		} else {
+			printf ("Factory MAC: %s\n", e);
+			setenv ("ethaddr", e);
+		}
+	}
+	sprintf (bootcmd,"autoscript %X",(unsigned)bootscript);
+	setenv ("bootcmd", bootcmd);
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+long int initdram (int board_type)
+{
+	return (L1_MEMSIZE);
+}
+
+/* ------------------------------------------------------------------------- */
+/* stubs so we can print dates w/o any nvram RTC.*/
+void rtc_get (struct rtc_time *tmp)
+{
+	return;
+}
+void rtc_set (struct rtc_time *tmp)
+{
+	return;
+}
+void rtc_reset (void)
+{
+	return;
+}
+
+/* ------------------------------------------------------------------------- */
+/*  Do sdram bank init in C so I can read it..no console to print to yet!
+ */
+static void init_sdram (void)
+{
+ unsigned long tmp;
+
+	/* write SDRAM bank 0 register */
+	mtdcr (memcfga, mem_mb0cf);
+	mtdcr (memcfgd, 0x00062001);
+
+/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.	*/
+/* To set the appropriate timings, we need to know the SDRAM speed.	*/
+/* We can use the PLB speed since the SDRAM speed is the same as	*/
+/* the PLB speed. The PLB speed is the FBK divider times the		*/
+/* 405GP reference clock, which on the L1 is 25Mhz.			*/
+/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is	*/
+/* 150Mhz; if FBK is 3, SDRAM is 150Mhz.				*/
+
+	/* divisor = ((mfdcr(strap)>> 28) & 0x3); */
+
+/* write SDRAM timing for 100Mhz. */
+	mtdcr (memcfga, mem_sdtr1);
+	mtdcr (memcfgd, 0x0086400D);
+
+/* write SDRAM refresh interval register */
+	mtdcr (memcfga, mem_rtr);
+	mtdcr (memcfgd, 0x05F00000);
+	udelay (200);
+
+/* sdram controller.*/
+	mtdcr (memcfga, mem_mcopt1);
+	mtdcr (memcfgd, 0x90800000);
+	udelay (200);
+
+/* initially, disable ECC on all banks */
+	udelay (200);
+	mtdcr (memcfga, mem_ecccf);
+	tmp = mfdcr (memcfgd);
+	tmp &= 0xff0fffff;
+	mtdcr (memcfga, mem_ecccf);
+	mtdcr (memcfgd, tmp);
+
+	return;
+}
+
+extern int memory_post_test (int flags);
+
+int testdram (void)
+{
+ unsigned long tmp;
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) L1_MEMSIZE;
+	uint *p;
+
+	if (getenv_r("booted",NULL,0) <= 0)
+	{
+		printf ("testdram..");
+	/*AA*/
+		for (p = pstart; p < pend; p++)
+			*p = 0xaaaaaaaa;
+		for (p = pstart; p < pend; p++) {
+			if (*p != 0xaaaaaaaa) {
+				printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+						(uint) p, *p, 0xaaaaaaaa);
+				return 1;
+			}
+		}
+	/*55*/
+		for (p = pstart; p < pend; p++)
+			*p = 0x55555555;
+		for (p = pstart; p < pend; p++) {
+			if (*p != 0x55555555) {
+				printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+						(uint) p, *p, 0x55555555);
+				return 1;
+			}
+		}
+	/*addr*/
+		for (p = pstart; p < pend; p++)
+			*p = (unsigned)p;
+		for (p = pstart; p < pend; p++) {
+			if (*p != (unsigned)p) {
+				printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+						(uint) p, *p, (uint)p);
+				return 1;
+			}
+		}
+		printf ("Success. ");
+	}
+	printf ("Enable ECC..");
+
+	mtdcr (memcfga, mem_mcopt1);
+	tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
+	mtdcr (memcfga, mem_mcopt1);
+	mtdcr (memcfgd, tmp);
+	udelay (600);
+	for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L)
+		;
+	udelay (400);
+	mtdcr (memcfga, mem_ecccf);
+	tmp = mfdcr (memcfgd);
+	tmp |= 0x00800000;
+	mtdcr (memcfgd, tmp);
+	udelay (400);
+	printf ("enabled.\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+static u8 *dhcp_env_update (u8 thing, u8 * pop)
+{
+	u8 i, oplen;
+
+	oplen = *(pop + 1);
+
+	if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) {
+		printf ("Whoops! failed to malloc space for DHCP thing %s\n",
+				Things[thing].envname);
+		return NULL;
+	}
+	for (i = 0; (i < oplen); i++)
+		if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ')
+			break;
+	*(Things[thing].dhcpvalue + i) = '\0';
+
+/* set env. */
+	if (Things[thing].envname)
+	{
+		setenv (Things[thing].envname, Things[thing].dhcpvalue);
+	}
+	return ((u8 *)(Things[thing].dhcpvalue));
+}
+
+/* ------------------------------------------------------------------------- */
+u8 *dhcp_vendorex_prep (u8 * e)
+{
+	u8 thing;
+
+/* ask for the things I want. */
+	*e++ = 55;					/* Parameter Request List */
+	*e++ = N_THINGS;
+	for (thing = 0; thing < N_THINGS; thing++)
+		*e++ = Things[thing].dhcp_option;
+	*e++ = 255;
+
+	return e;
+}
+
+/* ------------------------------------------------------------------------- */
+/* .. return NULL means it wasnt mine, non-null means I got it..*/
+u8 *dhcp_vendorex_proc (u8 * pop)
+{
+	u8 oplen, *sub_op, sub_oplen, *retval;
+	u8 thing = 0;
+
+	retval = NULL;
+	oplen = *(pop + 1);
+/* if pop is vender spec indicator, there are sub-options. */
+	if (*pop == DHCP_VENDOR_SPECX) {
+		for (sub_op = pop + 2;
+		     oplen && (sub_oplen = *(sub_op + 1));
+		     oplen -= sub_oplen, sub_op += (sub_oplen + 2)) {
+			for (thing = 0; thing < N_THINGS; thing++) {
+			    if (*sub_op == Things[thing].dhcp_vendor_option) {
+					if (!(retval = dhcp_env_update (thing, sub_op))) {
+						return NULL;
+					}
+			    }
+			}
+		}
+	} else {
+		for (thing = 0; thing < N_THINGS; thing++) {
+			if (*pop == Things[thing].dhcp_option)
+				if (!(retval = dhcp_env_update (thing, pop)))
+					return NULL;
+		}
+	}
+	return (pop);
+}
diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h
new file mode 100755
index 0000000..1b41824
--- /dev/null
+++ b/board/cray/L1/L1.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip
+ *
+ *                          Start Address    Length
+ * +++++++++++++++++++++++++ 0xFFC0_0000     Start of Flash -----------------
+ * | Failsafe Linux Image  | 	(1M)
+ * +=======================+ 0xFFD0_0000
+ * | (Reserved FlashFiles) |	(1M)
+ * +=======================+ 0xFFE0_0000
+ * | Failsafe RootFS       |	(1M)
+ * +=======================+ 0xFFF0_0000
+ * |                       |
+ * | U N U S E D           |
+ * |                       |
+ * +-----------------------+ 0xFFFD_0000	U-Boot image header (64 bytes)
+ * | environment settings  | 	(64k)
+ * +-----------------------+ 0xFFFE_0000	U-Boot image header (64 bytes)
+ * | U-Boot                | 0xFFFE_0040    _start of U-Boot
+ * |                       | 0xFFFE_FFFC    reset vector - branch to _start
+ * +++++++++++++++++++++++++ 0xFFFF_FFFF     End of Flash -----------------
+ *****************************************************************************/
diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile
new file mode 100755
index 0000000..bfe0922
--- /dev/null
+++ b/board/cray/L1/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not
+# built in the depend stage.  So... put bootscript.o here, not in OBJS
+$(LIB):	$(OBJS) $(SOBJS) bootscript.o
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS) bootscript.c bootscript.image bootscript.o
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+$(BOARD).o : $(BOARD).c bootscript.o
+
+bootscript.c: bootscript.image
+	od -t x1 -v -A x $^ | awk -f x2c.awk > $@
+
+bootscript.image: bootscript.hush Makefile
+	-$(TOPDIR)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d  bootscript.hush $@
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/cray/L1/bootscript.hush b/board/cray/L1/bootscript.hush
new file mode 100755
index 0000000..ec4839b
--- /dev/null
+++ b/board/cray/L1/bootscript.hush
@@ -0,0 +1,117 @@
+# $Header$
+# hush bootscript for PPCBOOT on L1
+# note: all #s are in hex, do _NOT_ prefix it with 0x
+
+flash_rfs=ffc00000
+flash_krl=fff00000
+tftp_addr=100000
+tftp2_addr=1000000
+
+if printenv booted
+then
+	echo already booted before
+else
+	echo first boot in environment, create and save settings
+	setenv booted OK
+	saveenv
+fi
+
+setenv autoload no
+# clear out stale env stuff, so we get fresh from dhcp.
+for setting in initrd fromflash kernel rootfs rootpath
+do
+setenv $setting
+done
+
+dhcp
+
+# if host provides us with a different bootscript, us it.
+if printenv bootscript
+	then
+	tftp $tftp_addr $bootcript
+	if imi $tftp_addr
+	then
+		autoscript $tftp_addr
+	fi
+fi
+
+# default base kernel arguments.
+setenv bootargs $xbootargs devfs=mount ip=$ipaddr:$serverip:$gatewayip:$netmask:L1:eth0:off wdt=120
+
+# Have a kernel in flash?
+if imi $flash_krl
+then
+	echo ok kernel to boot from $flash_krl
+	setenv kernel $flash_krl
+else
+	echo no kernel to boot from $flash_krl, need tftp
+fi
+
+# Have a rootfs in flash? 
+echo test for SQUASHfs at $flash_rfs
+
+if imi $flash_rfs
+then
+	echo appears to be a good initrd image at base of flash OK
+	setenv rootfs $flash_rfs
+else
+	echo no image at base of flash, need nfsroot or initrd
+fi
+
+# I boot from flash if told to and I can.
+if printenv fromflash && printenv kernel && printenv rootfs
+then
+	echo booting entirely from flash
+	setenv bootargs root=/dev/ram0 rw $bootargs
+	bootm $kernel $rootfs
+	echo oh no failed so I try some other stuff
+fi
+
+# TFTP down a kernel
+if printenv bootfile
+then 
+	tftp $tftp_addr $bootfile
+	setenv kernel $tftp_addr
+	echo I will boot the TFTP kernel
+else
+	if printenv kernel
+	then
+		echo no bootfile specified, will use one from flash
+	else
+		setenv bootfile /opt/crayx1/craymcu/l1/flash/linux.image
+		echo OH NO! we have no bootfile,nor flash kernel! try default: $bootfile
+		tftp $tftp_addr $bootfile
+		setenv kernel $tftp_addr
+	fi
+fi
+
+# the rootfs.
+if printenv rootpath
+then
+	echo rootpath is $rootpath
+	if printenv initrd
+	then 
+		echo initrd is also specified, so use $initrd
+		tftp $tftp2_addr $initrd
+		setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs
+		bootm $kernel $tftp2_addr
+	else
+		echo initrd is not specified, so use NFSROOT $rootpat
+		setenv bootargs root=/dev/nfs ro nfsroot=$serverip:$rootpath $bootargs
+		bootm $kernel
+	fi
+else
+	echo we have no rootpath check for one in flash
+	if printenv rootfs
+	then
+		echo I will use the one in flash
+		setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
+		bootm $kernel
+	else
+		setenv rootpath /export/crayl1
+		echo OH NO! we have no rootpath,nor flash kernel! try default: $rootpath
+		setenv bootargs root=/dev/mtdblock/0 ro rootfstype=squashfs $bootargs
+		bootm $kernel
+	fi
+fi
+reset
diff --git a/board/cray/L1/config.mk b/board/cray/L1/config.mk
new file mode 100755
index 0000000..b69fe8e
--- /dev/null
+++ b/board/cray/L1/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Note: I make an "image" from U-Boot itself, which prefixes 0x40 bytes of
+# header info, hence start address is thus shifted.
+TEXT_BASE = 0xFFFD0040
diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c
new file mode 100755
index 0000000..f313274
--- /dev/null
+++ b/board/cray/L1/flash.c
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+/*
+ * Modified July 20, 2001
+ * Strip down to support ONLY the AMD29F032B.
+ * Dave Updegraff - Cray, Inc. dave@cray.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/* The flash chip we use... */
+#define AMD_ID_F032B	0x41	/* 29F032B ID  32 Mbit,64 64Kx8 sectors */
+#define FLASH_AM320B    0x0009
+
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+#define ADDR0           0x5555
+#define ADDR1           0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Only one bank */
+	if (CFG_MAX_FLASH_BANKS == 1)
+	  {
+	    /* Setup offsets */
+	    flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+#if 0
+	    /* Monitor protection ON by default */
+	    (void)flash_protect(FLAG_PROTECT_SET,
+				FLASH_BASE0_PRELIM,
+				FLASH_BASE0_PRELIM+monitor_flash_len-1,
+				&flash_info[0]);
+#endif
+	    size_b1 = 0 ;
+	    flash_info[0].size = size_b0;
+	  }
+
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[0];
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[1];			/* device ID		*/
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_F032B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 64;
+		info->size = 0x0400000; /* => 4 MB */
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+	info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+    last  = start;
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return -1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    putc ('.');
+	    last = now;
+	}
+    }
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+		    addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+		    printf("Erasing sector %p\n", addr2);
+
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    l_sect = sect;
+		    /*
+		     * Wait for each sector to complete, it's more
+		     * reliable.  According to AMD Spec, you must
+		     * issue all erase commands within a specified
+		     * timeout.  This has been seen to fail, especially
+		     * if printf()s are included (for debug)!!
+		     */
+		    wait_for_DQ7(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *)dest) &
+	     (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S
new file mode 100755
index 0000000..72a10d3
--- /dev/null
+++ b/board/cray/L1/init.S
@@ -0,0 +1,147 @@
+/*------------------------------------------------------------------------------+ */
+/* */
+/*       This source code has been made available to you by IBM on an AS-IS */
+/*       basis.  Anyone receiving this source is licensed under IBM */
+/*       copyrights to use it in any way he or she deems fit, including */
+/*       copying it, modifying it, compiling it, and redistributing it either */
+/*       with or without modifications.  No license under IBM patents or */
+/*       patent applications is to be implied by the copyright license. */
+/* */
+/*       Any user of this software should understand that IBM cannot provide */
+/*       technical support for this software and will not be responsible for */
+/*       any consequences resulting from the use of this software. */
+/* */
+/*       Any person who transfers this source code or any derivative work */
+/*       must include the IBM copyright notice, this paragraph, and the */
+/*       preceding two paragraphs in the transferred software. */
+/* */
+/*       COPYRIGHT   I B M   CORPORATION 1995 */
+/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
+/*------------------------------------------------------------------------------- */
+
+/*----------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init */
+/* Description:  Initializes the External Bus Controller for the external */
+/*		peripherals. IMPORTANT: For pass1 this code must run from */
+/*		cache since you can not reliably change a peripheral banks */
+/*		timing register (pbxap) while running code from that bank. */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so */
+/*		we run it from cache. */
+/*	Bank 0 - Flash and SRAM */
+/*	Bank 1 - NVRAM/RTC */
+/*	Bank 2 - Keyboard/Mouse controller */
+/*	Bank 3 - IR controller */
+/*	Bank 4 - not used */
+/*	Bank 5 - not used */
+/*	Bank 6 - not used */
+/*	Bank 7 - FPGA registers */
+/*-----------------------------------------------------------------------------#include <config.h> */
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
+/*	except for #1 which we use for DMA'ing to IOCA-like things, so the */
+/*	control registers to set that up are determined by what we've */
+/*	empirically discovered work there. */
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	mflr    r4                      /* save link register */
+	bl      ..getAddr
+..getAddr:
+	mflr    r3                      /* get address of ..getAddr */
+	mtlr    r4                      /* restore link register */
+	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+	mtctr   r4                      /* 10 cache lines to fit this function */
+					/* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+	addi    r3,r3,32		/* move to next cache line */
+	bdnz    ..ebcloop               /* continue for 10 cache lines */
+
+	/*------------------------------------------------------------------- */
+	/* Delay to ensure all accesses to ROM are complete before changing */
+	    /* bank 0 timings. 200usec should be enough. */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*------------------------------------------------------------------- */
+	addis	r3,0,0x0
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
+..spinlp:
+	bdnz    ..spinlp                /* spin loop */
+
+
+	/*---------------------------------------------------------------------- */
+	/* Peripheral Bank 0 (Flash) initialization */
+	/*---------------------------------------------------------------------- */
+		/* 0x7F8FFE80 slowest boot */
+	addi    r4,0,pb0ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,0x9B01
+	ori     r4,r4,0x5480
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,0xFFC5           /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
+	ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
+	mtdcr   ebccfgd,r4
+
+	blr
+
+	/*---------------------------------------------------------------------- */
+	/* Peripheral Bank 1 (NVRAM/RTC) initialization */
+		/* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
+		/* and we do DMA on it.  The ConfigurationRegister part is threfore */
+		/* almost arbitrary, except that our linux driver needs to know the */
+		/* address, but it can query, it.. */
+		/* */
+		/* The AccessParameter is CRITICAL, */
+		/* thouch, since it needs to agree with the electrical timings on the */
+		/* IOCA parallel interface.  That value is: 0x0185,4380 */
+		/* BurstModeEnable			BME=0 */
+		/* TransferWait				TWT=3 */
+		/* ChipSelectOnTiming		CSN=1 */
+		/* OutputEnableOnTimimg		OEN=1 */
+		/* WriteByteEnableOnTiming	WBN=1 */
+		/* WriteByteEnableOffTiming	WBF=0 */
+		/* TransferHold				TH=1 */
+		/* ReadyEnable				RE=1 */
+		/* SampleOnReady			SOR=1 */
+		/* ByteEnableMode			BEM=0 */
+		/* ParityEnable				PEN=0 */
+		/* all reserved bits=0 */
+	/*---------------------------------------------------------------------- */
+	/*---------------------------------------------------------------------- */
+	addi    r4,0,pb1ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,0x0185		/* hiword */
+	ori     r4,r4,0x4380	/* loword */
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb1cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,0xF001           /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
+	ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
+	mtdcr   ebccfgd,r4
+
+	blr
+
+/*----------------------------------------------------------------------------- */
+/* Function:	sdram_init */
+/* Description:	Configures SDRAM memory banks. */
+/*				NOTE: for CrayL1 we have ECC memory, so enable it. */
+/*....now done in C in L1.c:init_sdram for readability. */
+/*----------------------------------------------------------------------------- */
+	.globl  sdram_init
+
+sdram_init:
+ blr
diff --git a/board/cray/L1/patchme b/board/cray/L1/patchme
new file mode 100755
index 0000000..e77ee7e
--- /dev/null
+++ b/board/cray/L1/patchme
@@ -0,0 +1,30 @@
+# master confi.mk
+echo "CROSS_COMPILE = powerpc-linux-"	>>include/config.mk
+
+# patch the examples/Makefile to ignore return value from OBJCOPY
+sed  -e 's/$(OBJCOPY)/-&/' < examples/Makefile > examples/makefile
+
+# add a built target for mkimage on the target architecture
+sed  -e 's/^all:.*$/all: .depend envcrc mkimage mkimage.ppc/' < tools/Makefile > tools/makefile
+
+cat <<EOF >>tools/makefile
+mkimage.ppc : mkimage.o.ppc crc32.o.ppc
+	powerpc-linux-gcc -msoft-float -Wall -Wstrict-prototypes -o \$@ \$^
+	powerpc-linux-strip $@
+
+XFLAGS="-D__KERNEL__  -I../include -DCONFIG_4xx -Wall -Wstict-prototypes"
+mkimage.o.ppc: mkimage.c
+	powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
+
+crc32.o.ppc: crc32.c
+	powerpc-linux-gcc -msoft-float -Wall -I../include -c -o \$@ \$^
+
+EOF
+
+# make an image by default out of the u-boot image
+sed  -e 's/^all:.*$/all: u-boot.image /' < Makefile > makefile
+cat <<EOF >>makefile
+u-boot.image:  u-boot.bin
+	tools/mkimage -A ppc -O linux -T firmware -C none -a 0 -e 0 -n U-Boot -d \$^ \$@
+
+EOF
diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds
new file mode 100755
index 0000000..cf4bbb9
--- /dev/null
+++ b/board/cray/L1/u-boot.lds
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/cray/L1/init.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*. = env_offset;*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug
new file mode 100755
index 0000000..1608f8c
--- /dev/null
+++ b/board/cray/L1/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/cray/L1/x2c.awk b/board/cray/L1/x2c.awk
new file mode 100755
index 0000000..9235e6c
--- /dev/null
+++ b/board/cray/L1/x2c.awk
@@ -0,0 +1,6 @@
+#!/bin/awk
+BEGIN { print "unsigned char bootscript[] = { \n"}
+{ for (i = 2; i <= NF ; i++ ) printf "0x"$i","
+  print ""
+}
+END { print "\n};\n" }
diff --git a/board/csb226/Makefile b/board/csb226/Makefile
new file mode 100755
index 0000000..5b311a9
--- /dev/null
+++ b/board/csb226/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= csb226.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/csb226/config.mk b/board/csb226/config.mk
new file mode 100755
index 0000000..2354392
--- /dev/null
+++ b/board/csb226/config.mk
@@ -0,0 +1,15 @@
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to c170'0000, the upper 1 MB of second bank
+#
+# download areas is c800'0000
+#
+
+# This is the address where U-Boot lives in flash:
+#TEXT_BASE = 0
+
+# FIXME: armboot does only work correctly when being compiled
+# for the addresses _after_ relocation to RAM!! Otherwhise the
+# .bss segment is assumed in flash...
+TEXT_BASE = 0xa1fe0000
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
new file mode 100755
index 0000000..c99a715
--- /dev/null
+++ b/board/csb226/csb226.c
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
+ * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
+ * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+/**
+ * misc_init_r: - misc initialisation routines
+ */
+
+int misc_init_r(void)
+{
+#if 0
+	uchar *str;
+
+	/* determine if the software update key is pressed during startup */
+	/* not ported yet... */
+	if (GPLR0 & 0x00000800) {
+		printf("using bootcmd_normal (sw-update button not pressed)\n");
+		str = getenv("bootcmd_normal");
+	} else {
+		printf("using bootcmd_update (sw-update button pressed)\n");
+		str = getenv("bootcmd_update");
+	}
+
+	setenv("bootcmd",str);
+#endif
+	return 0;
+}
+
+
+/**
+ * board_init: - setup some data structures
+ *
+ * @return: 0 in case of success
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of CSB226 board */
+	gd->bd->bi_arch_number = MACH_TYPE_CSB226;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+
+/**
+ * dram_init: - setup dynamic RAM
+ *
+ * @return: 0 in case of success
+ */
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+
+/**
+ * csb226_set_led: - switch LEDs on or off
+ *
+ * @param led:   LED to switch (0,1,2)
+ * @param state: switch on (1) or off (0)
+ */
+
+void csb226_set_led(int led, int state)
+{
+	switch(led) {
+
+		case 0: if (state==1) {
+				GPCR0 |= CSB226_USER_LED0;
+			} else if (state==0) {
+				GPSR0 |= CSB226_USER_LED0;
+			}
+			break;
+
+		case 1: if (state==1) {
+				GPCR0 |= CSB226_USER_LED1;
+			} else if (state==0) {
+				GPSR0 |= CSB226_USER_LED1;
+			}
+			break;
+
+		case 2: if (state==1) {
+				GPCR0 |= CSB226_USER_LED2;
+			} else if (state==0) {
+				GPSR0 |= CSB226_USER_LED2;
+			}
+			break;
+	}
+
+	return;
+}
+
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ * The CSB226 does only have 3 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
+ */
+
+void show_boot_progress (int status)
+{
+	switch(status) {
+		case  1: csb226_set_led(0,1); break;
+		case  5: csb226_set_led(1,1); break;
+		case 15: csb226_set_led(2,1); break;
+	}
+
+	return;
+}
diff --git a/board/csb226/flash.c b/board/csb226/flash.c
new file mode 100755
index 0000000..f6dfd96
--- /dev/null
+++ b/board/csb226/flash.c
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2003 (2 x 16 bit Flash bank patches)
+ * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+#define FLASH_BANK_SIZE 0x02000000
+#define MAIN_SECT_SIZE	0x40000		/* 2x16 = 256k per sector */
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/**
+ * flash_init: - initialize data structures for flash chips
+ *
+ * @return: size of the flash
+ */
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+
+		switch (i) {
+		case 0:
+			flashbase = PHYS_FLASH_1;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+	return size;
+}
+
+
+/**
+ * flash_print_info: - print information about the flash situation
+ */
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i, j;
+
+	for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {
+
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf ("Intel: ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+			printf("28F128J3 (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			return;
+		}
+
+		printf("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+		printf("  Sector Start Addresses:");
+		for (i = 0; i < info->sector_count; i++) {
+			if ((i % 5) == 0) printf ("\n	");
+
+			printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "	   ");
+		}
+		printf ("\n");
+		info++;
+	}
+}
+
+
+/**
+ * flash_erase: - erase flash sectors
+ */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
+		return ERR_UNKNOWN_FLASH_VENDOR;
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) prot++;
+	}
+
+	if (prot) return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+
+		printf("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked();
+
+		if (info->protect[sect] == 0) { /* not protected */
+			u32 * volatile addr = (u32 * volatile)(info->start[sect]);
+
+			/* erase sector:				    */
+			/* The strata flashs are aligned side by side on    */
+			/* the data bus, so we have to write the commands   */
+			/* to both chips here:				    */
+
+			*addr = 0x00200020;	/* erase setup */
+			*addr = 0x00D000D0;	/* erase confirm */
+
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+					*addr = 0x00B000B0; /* suspend erase*/
+					*addr = 0x00FF00FF; /* read mode    */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+			*addr = 0x00500050; /* clear status register cmd.   */
+			*addr = 0x00FF00FF; /* reset to read mode	    */
+		}
+		printf("ok.\n");
+	}
+	if (ctrlc()) printf("User Interrupt!\n");
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked(10000);
+
+	if (flag) enable_interrupts();
+
+	return rc;
+}
+
+/**
+ * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each
+ */
+
+static int write_long (flash_info_t *info, ulong dest, ulong data)
+{
+	u32 * volatile addr = (u32 * volatile)dest, val;
+	int rc = ERR_OK;
+	int flag;
+
+	/* read array command - just for the case... */
+	*addr = 0x00FF00FF;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts();
+
+	/* clear status register command */
+	*addr = 0x00500050;
+
+	/* program set-up command */
+	*addr = 0x00400040;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while(((val = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0x00B000B0;
+			goto outahere;
+		}
+	}
+
+	/* check for errors */
+	if(val & 0x001A001A) {
+		printf("\nFlash write error %02x at address %08lx\n",
+			(int)val, (unsigned long)dest);
+		if(val & 0x00080008) {
+			printf("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if(val & 0x00020002) {
+			printf("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if(val & 0x00100010) {
+			printf("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}
+
+outahere:
+	/* read array command */
+	*addr = 0x00FF00FF;
+	if (flag) enable_interrupts();
+
+	return rc;
+}
+
+
+/**
+ * write_buf: - Copy memory to flash.
+ *
+ * @param info:
+ * @param src:	source of copy transaction
+ * @param addr: where to copy to
+ * @param cnt:	number of bytes to copy
+ *
+ * @return	error code
+ */
+
+/* "long" version, uses 32bit words */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ulong data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+
+		if ((rc = write_long(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((ulong*)src);
+		if ((rc = write_long(info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 4;
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+
+	return write_long(info, wp, data);
+}
diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S
new file mode 100755
index 0000000..aa9dcba
--- /dev/null
+++ b/board/csb226/lowlevel_init.S
@@ -0,0 +1,437 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc  p15,0,\reg,c2,c0,0
+   mov  \reg,\reg
+   sub  pc,pc,#4
+   .endm
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+
+/*
+ * 	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+    mov      r10, lr
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr	r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
+/*	ldr	r2,	=CFG_MSC1_VAL	/  high - bank 3 Ethernet Controller */
+/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
+/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
+/* */
+/*	ldr	r1,	=LED_BLANK */
+/*	mov	r0,	#0xFF */
+/*	str	r0,	[r1]		/  turn on hex leds */
+/* */
+/*loop: */
+/* */
+/*   ldr	r0, =0xB0070001 */
+/*   ldr    	r1, =_LED */
+/*   str    	r0, [r1]		/  hex display */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr     r2,   =CFG_MSC0_VAL
+	str     r2,   [r1, #MSC0_OFFSET]
+	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */
+	/* MSC1: nCS(2,3)                                                   */
+	ldr     r2,  =CFG_MSC1_VAL
+	str     r2,  [r1, #MSC1_OFFSET]
+	ldr     r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr     r2,  =CFG_MSC2_VAL
+	str     r2,  [r1, #MSC2_OFFSET]
+	ldr     r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr     r2,  =CFG_MECR_VAL
+	str     r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr     r2,  =CFG_MCMEM0_VAL
+	str     r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr     r2,  =CFG_MCMEM1_VAL
+	str     r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr     r2,  =CFG_MCATT0_VAL
+	str     r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr     r2,  =CFG_MCATT1_VAL
+	str     r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr     r2,  =CFG_MCIO0_VAL
+	str     r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr     r2,  =CFG_MCIO1_VAL
+	str     r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
+	adr	r3, mem_init		/* r0 <- current position of code   */
+	ldr	r2, =mem_init
+	cmp	r3, r2			/* skip init if in place            */
+	beq	initirqs
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DRI field.                           */
+
+	ldr 	r3, 	=CFG_MDREFR_VAL
+	ldr	r2,	=0xFFF
+	and	r3,	r3, r2
+	ldr	r4,	=0x03ca4000
+	orr	r4,	r4,  r3
+
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr     r4,	[r1, #MDREFR_OFFSET]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	/* Step 4a: assert MDREFR:K?RUN and configure                       */
+	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
+
+	ldr	r4,	=CFG_MDREFR_VAL
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr	r4,	[r1, #MDREFR_OFFSET]
+
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
+
+	bic	r4,	r4, #(MDREFR_SLFRSH)
+
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,     [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
+
+	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
+
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,     [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+
+	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+	ldr     r4,     [r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	/*          There should 9 writes, since the first write doesn't    */
+	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
+	/*          PXA210 Processors Specification Update,                 */
+	/*          Jan 2003, Errata #116, page 30.                         */
+
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
+
+	ldr	r3, [r1, #MDCNFG_OFFSET]
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	str	r3, [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2,  =CFG_MDMRS_VAL
+	str     r2,  [r1, #MDMRS_OFFSET]
+
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2,  =ICLR
+	str     r1,  [r2]
+
+	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
+	str     r1,  [r2]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+	/* (hard-coding at 398.12MHz for now).                              */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+	ldr     r1,  =CKEN
+	mov     r2,  #0
+	str     r2,  [r1]
+
+
+	/* default value in case no valid rotary switch setting is found    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1,  =CCCR
+	str     r2,  [r1]
+
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+/*
+	ldr     r1,  =OSCC
+	mov     r2,  #OSCC_OON
+	str     r2,  [r1]
+*/
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size                                                  */
+	ldr	r1, =DRAM_SIZE
+	str	r8, [r1]
+
+	/* Interrupt init: Mask all interrupts                              */
+	ldr	r0, =ICMR			/* enable no sources        */
+	mov	r1, #0
+	str	r1, [r0]
+
+	/* FIXME */
+
+#ifndef DEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init                                                     */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+    mov     pc, lr
diff --git a/board/csb226/u-boot.lds b/board/csb226/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/csb226/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/csb272/Makefile b/board/csb272/Makefile
new file mode 100755
index 0000000..926e065
--- /dev/null
+++ b/board/csb272/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+#OBJS	= $(BOARD).o flash.o
+#OBJS	= $(BOARD).o strataflash.o
+OBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/csb272/config.mk b/board/csb272/config.mk
new file mode 100755
index 0000000..4672f08
--- /dev/null
+++ b/board/csb272/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Cogent CSB272 board
+#
+
+LDFLAGS += $(LINKER_UNDEFS)
+
+TEXT_BASE := 0xFFFC0000
+#TEXT_BASE := 0x00100000
+
+PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
new file mode 100755
index 0000000..24c6f0d
--- /dev/null
+++ b/board/csb272/csb272.c
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <ppc4xx_enet.h>
+
+/*
+ * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
+ *
+ * CLKA output => Epson LCD Controller
+ * CLKB output => Not Connected
+ * CLKC output => Ethernet
+ * CLKD output => UART external clock
+ *
+ * Note: these values are obtained from device after init by micromonitor
+*/
+uchar pll_fs6377_regs[16] = {
+	0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
+	0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
+
+/*
+ * pll_init: Initialize AMIS IC FS6377-01 PLL
+ *
+ * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
+ *
+ */
+int pll_init(void)
+{
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	return  i2c_write(CFG_I2C_PLL_ADDR, 0, 1,
+		(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
+}
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+	/* initialize PLL so UART, LCD, Ethernet clocked at correctly */
+	(void) get_clocks();
+	pll_init();
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (uicer, 0x00000000);   /* disable all ints */
+	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+
+	mtebc (epcr, 0xa8400000);   /* EBC always driven */
+
+	return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+	printf("BOARD: Cogent CSB272\n");
+
+	return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+long initdram (int board_type)
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	tot_size = 0;
+
+	mtdcr (memcfga, mem_mb0cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb1cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb2cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb3cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+	/* initialize the PHY */
+	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+	/* AUTO neg */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+	/* LEDs     */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
+
+
+	return 0; /* success */
+}
diff --git a/board/csb272/init.S b/board/csb272/init.S
new file mode 100755
index 0000000..e00ebf8
--- /dev/null
+++ b/board/csb272/init.S
@@ -0,0 +1,216 @@
+/******************************************************************************
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+	addis   reg,0,val@h;\
+	ori     reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
+
+#define WDCR_SDRAM(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   memcfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   memcfgd,r4
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * SETUP CPC0_CR0
+	 *******************************************************************/
+	LI32(r4, 0x007000c0)
+	mtdcr	cntrl0, r4
+
+	/********************************************************************
+	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, cntrl1
+	ori	r4, r4, 0x4000
+	mtdcr	cntrl1, r4
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	WDCR_EBC(epcr, 0xd84c0000)
+	/********************************************************************
+	 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb0ap, 0x02869200)*/
+	WDCR_EBC(pb0ap, 0x07869200)
+	WDCR_EBC(pb0cr, 0xfe0bc000)
+	/********************************************************************
+	 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb1ap, 0x1f869200)
+	WDCR_EBC(pb1cr, 0xf0818000)
+	/********************************************************************
+	 * Memory Bank 2 (Epson S1D13506) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb2ap, 0x05860300)
+	WDCR_EBC(pb2cr, 0xf045a000)
+	/********************************************************************
+	 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb3ap, 0x0387d200)
+	WDCR_EBC(pb3cr, 0xf021c000)
+	/********************************************************************
+	 * Memory Bank 4-7 (Unused) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb4ap, 0)
+	WDCR_EBC(pb4cr, 0)
+	WDCR_EBC(pb5ap, 0)
+	WDCR_EBC(pb5cr, 0)
+	WDCR_EBC(pb6ap, 0)
+	WDCR_EBC(pb6cr, 0)
+	WDCR_EBC(pb7ap, 0)
+	WDCR_EBC(pb7cr, 0)
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	WDCR_SDRAM(mem_mcopt1, 0x00000000)
+
+	/*
+	 * Configure Memory Banks
+	 */
+	WDCR_SDRAM(mem_mb0cf, 0x00084001)
+	WDCR_SDRAM(mem_mb1cf, 0x00000000)
+	WDCR_SDRAM(mem_mb2cf, 0x00000000)
+	WDCR_SDRAM(mem_mb3cf, 0x00000000)
+
+	/*
+	 * Set up SDTR1 (SDRAM Timing Register)
+	 */
+	WDCR_SDRAM(mem_sdtr1, 0x00854009)
+
+	/*
+	 * Set RTR (Refresh Timing Register)
+	 */
+	WDCR_SDRAM(mem_rtr,   0x10000000)
+	/* WDCR_SDRAM(mem_rtr,   0x05f00000) */
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait >200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	WDCR_SDRAM(mem_mcopt1,0x80800000)
+
+..sdri_done:
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds
new file mode 100755
index 0000000..d75d6d1
--- /dev/null
+++ b/board/csb272/u-boot.lds
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/csb272/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    lib_ppc/extable.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_generic/zlib.o	(.text)
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/csb472/Makefile b/board/csb472/Makefile
new file mode 100755
index 0000000..926e065
--- /dev/null
+++ b/board/csb472/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+#OBJS	= $(BOARD).o flash.o
+#OBJS	= $(BOARD).o strataflash.o
+OBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/csb472/config.mk b/board/csb472/config.mk
new file mode 100755
index 0000000..04aefd1
--- /dev/null
+++ b/board/csb472/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Cogent CSB472 board
+#
+
+LDFLAGS += $(LINKER_UNDEFS)
+
+TEXT_BASE := 0xFFFC0000
+#TEXT_BASE := 0x00100000
+
+PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
new file mode 100755
index 0000000..833bbce
--- /dev/null
+++ b/board/csb472/csb472.c
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <ppc4xx_enet.h>
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (uicer, 0x00000000);   /* disable all ints */
+	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+
+	mtebc (epcr, 0xa8400000);   /* EBC always driven */
+
+	return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+	printf("BOARD: Cogent CSB472\n");
+
+	return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+long initdram (int board_type)
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	tot_size = 0;
+
+	mtdcr (memcfga, mem_mb0cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb1cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb2cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb3cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+	/* initialize the PHY */
+	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
+
+	/* AUTO neg */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+
+	/* LEDs     */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
+
+	return 0; /* success */
+}
diff --git a/board/csb472/init.S b/board/csb472/init.S
new file mode 100755
index 0000000..aec42a1
--- /dev/null
+++ b/board/csb472/init.S
@@ -0,0 +1,212 @@
+/******************************************************************************
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+	addis   reg,0,val@h;\
+	ori     reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
+
+#define WDCR_SDRAM(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   memcfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   memcfgd,r4
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * SETUP CPC0_CR0
+	 *******************************************************************/
+	LI32(r4, 0x00c01030)
+	mtdcr	cntrl0, r4
+
+	/********************************************************************
+	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, cntrl1
+	ori	r4, r4, 0x4000
+	mtdcr	cntrl1, r4
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	WDCR_EBC(epcr, 0xd84c0000)
+	/********************************************************************
+	 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb0ap, 0x03055200)*/
+	/*WDCR_EBC(pb0ap, 0x04055200)*/
+	WDCR_EBC(pb0ap, 0x08055200)
+	WDCR_EBC(pb0cr, 0xff87a000)
+	/********************************************************************
+	 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb3ap, 0x07869200)*/
+	WDCR_EBC(pb3ap, 0x04055200)
+	WDCR_EBC(pb3cr, 0xf081c000)
+	/********************************************************************
+	 * Memory Bank 1,2,4-7 (Unused) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb1ap, 0)
+	WDCR_EBC(pb1cr, 0)
+	WDCR_EBC(pb2ap, 0)
+	WDCR_EBC(pb2cr, 0)
+	WDCR_EBC(pb4ap, 0)
+	WDCR_EBC(pb4cr, 0)
+	WDCR_EBC(pb5ap, 0)
+	WDCR_EBC(pb5cr, 0)
+	WDCR_EBC(pb6ap, 0)
+	WDCR_EBC(pb6cr, 0)
+	WDCR_EBC(pb7ap, 0)
+	WDCR_EBC(pb7cr, 0)
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	WDCR_SDRAM(mem_mcopt1, 0x00000000)
+
+	/*
+	 * Configure Memory Banks
+	 */
+	WDCR_SDRAM(mem_mb0cf, 0x00062001)
+	WDCR_SDRAM(mem_mb1cf, 0x00000000)
+	WDCR_SDRAM(mem_mb2cf, 0x00000000)
+	WDCR_SDRAM(mem_mb3cf, 0x00000000)
+
+	/*
+	 * Set up SDTR1 (SDRAM Timing Register)
+	 */
+	WDCR_SDRAM(mem_sdtr1, 0x00854009)
+
+	/*
+	 * Set RTR (Refresh Timing Register)
+	 */
+	WDCR_SDRAM(mem_rtr,   0x10000000)
+	/* WDCR_SDRAM(mem_rtr,   0x05f00000) */
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait >200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	WDCR_SDRAM(mem_mcopt1,0x80800000)
+
+..sdri_done:
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/board/csb472/u-boot.lds b/board/csb472/u-boot.lds
new file mode 100755
index 0000000..14ac3fb
--- /dev/null
+++ b/board/csb472/u-boot.lds
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/csb472/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    lib_ppc/extable.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_generic/zlib.o	(.text)
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/csb637/Makefile b/board/csb637/Makefile
new file mode 100755
index 0000000..61d5a35
--- /dev/null
+++ b/board/csb637/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= csb637.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/csb637/config.mk b/board/csb637/config.mk
new file mode 100755
index 0000000..4c6f631
--- /dev/null
+++ b/board/csb637/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23fc0000
diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c
new file mode 100755
index 0000000..6100a53
--- /dev/null
+++ b/board/csb637/csb637.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <bcm5221.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of CSB637-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_CSB637;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init		 = bcm5221_InitPhy;
+	p_phyops->IsPhyConnected = bcm5221_IsPhyConnected;
+	p_phyops->GetLinkSpeed	 = bcm5221_GetLinkSpeed;
+	p_phyops->AutoNegotiate	 = bcm5221_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/board/csb637/u-boot.lds b/board/csb637/u-boot.lds
new file mode 100755
index 0000000..76df6b2
--- /dev/null
+++ b/board/csb637/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/cu824/Makefile b/board/cu824/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/cu824/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/cu824/README b/board/cu824/README
new file mode 100755
index 0000000..cc0d207
--- /dev/null
+++ b/board/cu824/README
@@ -0,0 +1,453 @@
+ppcboot for a CU824 board
+---------------------------
+
+CU824 has two banks of flash 8MB each. In board's notation, bank 0 is
+the one at the address of 0xFF800000 and bank 1 is the one at the
+address of 0xFF000000. On power-up the processor jumps to the address
+of 0xFFF00100, the last megabyte of the bank 0 of flash. Thus,
+U-Boot is configured to reside in flash starting at the address of
+0xFFF00000. The environment space is not embedded in the U-Boot code
+and is located in flash separately from U-Boot, at the address of
+0xFF008000.
+
+
+U-Boot test results
+--------------------
+
+x.x Operation on all available serial consoles
+
+x.x.x CONFIG_CONS_INDEX 1
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>he
+go      - start application at address 'addr'
+run     - run commands in an environment variable
+bootm   - boot application image from memory
+bootp   - boot image via network using BootP/TFTP protocol
+tftpboot- boot image via network using TFTP protocol
+	       and env variables ipaddr and serverip
+rarpboot- boot image via network using RARP/TFTP protocol
+bootd   - boot default, i.e., run 'bootcmd'
+loads   - load S-Record file over serial line
+loadb   - load binary file over serial line (kermit mode)
+md      - memory display
+mm      - memory modify (auto-incrementing)
+nm      - memory modify (constant address)
+mw      - memory write (fill)
+cp      - memory copy
+cmp     - memory compare
+crc32   - checksum calculation
+base    - print or set address offset
+printenv- print environment variables
+setenv  - set environment variables
+saveenv - save environment variables to persistent storage
+protect - enable or disable FLASH write protection
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+bdinfo  - print Board Info structure
+iminfo  - print header information for application image
+coninfo - print console devices and informations
+loop    - infinite loop on address range
+mtest   - simple RAM test
+icache  - enable or disable instruction cache
+dcache  - enable or disable data cache
+reset   - Perform RESET of the CPU
+echo    - echo args to console
+version - print monitor version
+help    - print online help
+?       - alias for 'help'
+=>
+
+
+x.x.x CONFIG_CONS_INDEX 2
+
+**** NOT TESTED ****
+
+x.x Flash Driver Operation
+
+x.x.x Erase Operation
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>
+=>md ff000000
+ff000000: 27051956 70706362 6f6f7420 302e382e    '..Vppcboot 0.8.
+ff000010: 3320284d 61792031 31203230 3031202d    3 (May 11 2001 -
+ff000020: 2031343a 35373a30 33290000 00000000     14:57:03)......
+ff000030: 00000000 00000000 00000000 00000000    ................
+ff000040: 00000000 00000000 00000000 00000000    ................
+ff000050: 00000000 00000000 00000000 00000000    ................
+ff000060: 00000000 00000000 00000000 00000000    ................
+ff000070: 00000000 00000000 00000000 00000000    ................
+ff000080: 00000000 00000000 00000000 00000000    ................
+ff000090: 00000000 00000000 00000000 00000000    ................
+ff0000a0: 00000000 00000000 00000000 00000000    ................
+ff0000b0: 00000000 00000000 00000000 00000000    ................
+ff0000c0: 00000000 00000000 00000000 00000000    ................
+ff0000d0: 00000000 00000000 00000000 00000000    ................
+ff0000e0: 00000000 00000000 00000000 00000000    ................
+ff0000f0: 00000000 00000000 00000000 00000000    ................
+=>erase ff000000 ff007fff
+Erase Flash from 0xff000000 to 0xff007fff
+ done
+Erased 1 sectors
+=>md ff000000
+ff000000: ffffffff ffffffff ffffffff ffffffff    ................
+ff000010: ffffffff ffffffff ffffffff ffffffff    ................
+ff000020: ffffffff ffffffff ffffffff ffffffff    ................
+ff000030: ffffffff ffffffff ffffffff ffffffff    ................
+ff000040: ffffffff ffffffff ffffffff ffffffff    ................
+ff000050: ffffffff ffffffff ffffffff ffffffff    ................
+ff000060: ffffffff ffffffff ffffffff ffffffff    ................
+ff000070: ffffffff ffffffff ffffffff ffffffff    ................
+ff000080: ffffffff ffffffff ffffffff ffffffff    ................
+ff000090: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000a0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000b0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000c0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000d0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000e0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000f0: ffffffff ffffffff ffffffff ffffffff    ................
+=>
+
+x.x.x Information
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>
+=>
+=>flinfo
+
+Bank # 1: Intel: 28F160F3B (16Mbit)
+  Size: 8 MB in 39 Sectors
+  Sector Start Addresses:
+    FF000000      FF008000 (RO) FF010000      FF018000      FF020000
+    FF028000      FF030000      FF038000      FF040000      FF080000
+    FF0C0000      FF100000      FF140000      FF180000      FF1C0000
+    FF200000      FF240000      FF280000      FF2C0000      FF300000
+    FF340000      FF380000      FF3C0000      FF400000      FF440000
+    FF480000      FF4C0000      FF500000      FF540000      FF580000
+    FF5C0000      FF600000      FF640000      FF680000      FF6C0000
+    FF700000      FF740000      FF780000      FF7C0000
+
+Bank # 2: Intel: 28F160F3B (16Mbit)
+  Size: 8 MB in 39 Sectors
+  Sector Start Addresses:
+    FF800000      FF808000      FF810000      FF818000      FF820000
+    FF828000      FF830000      FF838000      FF840000      FF880000
+    FF8C0000      FF900000      FF940000      FF980000      FF9C0000
+    FFA00000      FFA40000      FFA80000      FFAC0000      FFB00000
+    FFB40000      FFB80000      FFBC0000      FFC00000      FFC40000
+    FFC80000      FFCC0000      FFD00000      FFD40000      FFD80000
+    FFDC0000      FFE00000      FFE40000      FFE80000      FFEC0000
+    FFF00000 (RO) FFF40000      FFF80000      FFFC0000
+=>
+
+x.x.x Flash Programming
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>
+=>
+=>cp 0 ff000000 20
+Copy to Flash... done
+=>md 0
+00000000: 0ec08ce0 03f9800c 00000001 040c0000    ................
+00000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00    ................
+00000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0    ...X......4...4.
+00000030: 03fcd5bc 03fcdabc 00000000 00000000    ................
+00000040: 00000000 00000000 00000000 00000000    ................
+00000050: 00000000 00000000 00000000 00000000    ................
+00000060: 00000000 00000000 00000000 00000000    ................
+00000070: 00000000 00000000 00000000 00000000    ................
+00000080: 00000000 00000000 00000000 00000000    ................
+00000090: 00000000 00000000 00000000 00000000    ................
+000000a0: 00000000 00000000 00000000 00000000    ................
+000000b0: 00000000 00000000 00000000 00000000    ................
+000000c0: 00000000 00000000 00000000 00000000    ................
+000000d0: 00000000 00000000 00000000 00000000    ................
+000000e0: 00000000 00000000 00000000 00000000    ................
+000000f0: 00000000 00000000 00000000 00000000    ................
+=>md ff000000
+ff000000: 0ec08ce0 03f9800c 00000001 040c0000    ................
+ff000010: 00000001 03fd1aa0 03fd1ae4 03fd1a00    ................
+ff000020: 03fd1a58 03fceb04 03fd34cc 03fd34d0    ...X......4...4.
+ff000030: 03fcd5bc 03fcdabc 00000000 00000000    ................
+ff000040: 00000000 00000000 00000000 00000000    ................
+ff000050: 00000000 00000000 00000000 00000000    ................
+ff000060: 00000000 00000000 00000000 00000000    ................
+ff000070: 00000000 00000000 00000000 00000000    ................
+ff000080: ffffffff ffffffff ffffffff ffffffff    ................
+ff000090: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000a0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000b0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000c0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000d0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000e0: ffffffff ffffffff ffffffff ffffffff    ................
+ff0000f0: ffffffff ffffffff ffffffff ffffffff    ................
+=>
+
+x.x.x Storage of environment variables in flash
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>printenv
+bootargs=
+bootcmd=bootm FE020000
+bootdelay=5
+baudrate=9600
+ipaddr=192.168.4.2
+serverip=192.168.4.1
+ethaddr=00:40:42:01:00:a0
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 167/32764 bytes
+=>setenv myvar 1234
+=>save_env
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Saving Environment to Flash...
+Protected 1 sectors
+=>reset
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>printenv
+bootargs=
+bootcmd=bootm FE020000
+bootdelay=5
+baudrate=9600
+ipaddr=192.168.4.2
+serverip=192.168.4.1
+ethaddr=00:40:42:01:00:a0
+myvar=1234
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 178/32764 bytes
+=>
+
+x.x Image Download and run over serial port
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>mw 40000 0 10000
+=>md 40000
+00040000: 00000000 00000000 00000000 00000000    ................
+00040010: 00000000 00000000 00000000 00000000    ................
+00040020: 00000000 00000000 00000000 00000000    ................
+00040030: 00000000 00000000 00000000 00000000    ................
+00040040: 00000000 00000000 00000000 00000000    ................
+00040050: 00000000 00000000 00000000 00000000    ................
+00040060: 00000000 00000000 00000000 00000000    ................
+00040070: 00000000 00000000 00000000 00000000    ................
+00040080: 00000000 00000000 00000000 00000000    ................
+00040090: 00000000 00000000 00000000 00000000    ................
+000400a0: 00000000 00000000 00000000 00000000    ................
+000400b0: 00000000 00000000 00000000 00000000    ................
+000400c0: 00000000 00000000 00000000 00000000    ................
+000400d0: 00000000 00000000 00000000 00000000    ................
+000400e0: 00000000 00000000 00000000 00000000    ................
+000400f0: 00000000 00000000 00000000 00000000    ................
+=>loads
+## Ready for S-Record download ...
+
+(Back at xpert.denx.de)
+[vlad@xpert vlad]$ cat hello_world.srec >/dev/ttyS0
+[vlad@xpert vlad]$ kermit -l /dev/ttyS0 -b 9600 -c
+Connecting to /dev/ttyS0, speed 9600.
+The escape character is Ctrl-\ (ASCII 28, FS)
+Type the escape character followed by C to get back,
+or followed by ? to see other options.
+md 40000
+00040000: 00018148 9421ffe0 7c0802a6 bf61000c    ...H.!..|....a..
+00040010: 90010024 48000005 7fc802a6 801effe8    ...$H...........
+00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378    ....|..x.?.8|.#x
+00040030: 807e8000 7cbd2b78 80090010 3b600000    .~..|.+x....;`..
+00040040: 7c0803a6 4e800021 813f0038 7f84e378    |...N..!.?.8...x
+00040050: 807e8004 80090010 7c0803a6 4e800021    .~......|...N..!
+00040060: 7c1be000 4181003c 80bd0000 813f0038    |...A..<.....?.8
+00040070: 3bbd0004 2c050000 40820008 80be8008    ;...,...@.......
+00040080: 80090010 7f64db78 807e800c 3b7b0001    .....d.x.~..;{..
+00040090: 7c0803a6 4e800021 7c1be000 4081ffcc    |...N..!|...@...
+000400a0: 813f0038 807e8010 80090010 7c0803a6    .?.8.~......|...
+000400b0: 4e800021 813f0038 80090004 7c0803a6    N..!.?.8....|...
+000400c0: 4e800021 2c030000 4182ffec 813f0038    N..!,...A....?.8
+000400d0: 80090000 7c0803a6 4e800021 813f0038    ....|...N..!.?.8
+000400e0: 807e8014 80090010 7c0803a6 4e800021    .~......|...N..!
+000400f0: 38600000 80010024 7c0803a6 bb61000c    8`.....$|....a..
+=>go 40004
+## Starting application at 0x00040004 ...
+Hello World
+argc = 1
+argv[0] = "40004"
+argv[1] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+=>
+
+x.x Image download and run over ethernet interface
+
+
+ppcboot 0.9.2 (May 13 2001 - 17:56:46)
+
+Initializing...
+  CPU:   MPC8240 Revsion 1.1 at 247 MHz: 16 kB I-Cache 16 kB D-Cache
+  Board: CU824 Revision 1 Local Bus at 99 MHz
+  DRAM:  64 MB
+  FLASH: 16 MB
+  In:    serial
+  Out:   serial
+  Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+=>
+=>mw 40000 0 10000
+=>md 40000
+00040000: 00000000 00000000 00000000 00000000    ................
+00040010: 00000000 00000000 00000000 00000000    ................
+00040020: 00000000 00000000 00000000 00000000    ................
+00040030: 00000000 00000000 00000000 00000000    ................
+00040040: 00000000 00000000 00000000 00000000    ................
+00040050: 00000000 00000000 00000000 00000000    ................
+00040060: 00000000 00000000 00000000 00000000    ................
+00040070: 00000000 00000000 00000000 00000000    ................
+00040080: 00000000 00000000 00000000 00000000    ................
+00040090: 00000000 00000000 00000000 00000000    ................
+000400a0: 00000000 00000000 00000000 00000000    ................
+000400b0: 00000000 00000000 00000000 00000000    ................
+000400c0: 00000000 00000000 00000000 00000000    ................
+000400d0: 00000000 00000000 00000000 00000000    ................
+000400e0: 00000000 00000000 00000000 00000000    ................
+000400f0: 00000000 00000000 00000000 00000000    ................
+=>tftpboot 40000 hello_world.bin
+ARP broadcast 1
+TFTP from server 192.168.4.1; our IP address is 192.168.4.2
+Filename 'hello_world.bin'.
+Load address: 0x40000
+Loading: #############
+done
+Bytes transferred = 65912 (10178 hex)
+=>md 40000
+00040000: 00018148 9421ffe0 7c0802a6 bf61000c    ...H.!..|....a..
+00040010: 90010024 48000005 7fc802a6 801effe8    ...$H...........
+00040020: 7fc0f214 7c7f1b78 813f0038 7c9c2378    ....|..x.?.8|.#x
+00040030: 807e8000 7cbd2b78 80090010 3b600000    .~..|.+x....;`..
+00040040: 7c0803a6 4e800021 813f0038 7f84e378    |...N..!.?.8...x
+00040050: 807e8004 80090010 7c0803a6 4e800021    .~......|...N..!
+00040060: 7c1be000 4181003c 80bd0000 813f0038    |...A..<.....?.8
+00040070: 3bbd0004 2c050000 40820008 80be8008    ;...,...@.......
+00040080: 80090010 7f64db78 807e800c 3b7b0001    .....d.x.~..;{..
+00040090: 7c0803a6 4e800021 7c1be000 4081ffcc    |...N..!|...@...
+000400a0: 813f0038 807e8010 80090010 7c0803a6    .?.8.~......|...
+000400b0: 4e800021 813f0038 80090004 7c0803a6    N..!.?.8....|...
+000400c0: 4e800021 2c030000 4182ffec 813f0038    N..!,...A....?.8
+000400d0: 80090000 7c0803a6 4e800021 813f0038    ....|...N..!.?.8
+000400e0: 807e8014 80090010 7c0803a6 4e800021    .~......|...N..!
+000400f0: 38600000 80010024 7c0803a6 bb61000c    8`.....$|....a..
+=>go 40004
+## Starting application at 0x00040004 ...
+Hello World
+argc = 1
+argv[0] = "40004"
+argv[1] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+=>
diff --git a/board/cu824/config.mk b/board/cu824/config.mk
new file mode 100755
index 0000000..18673e1
--- /dev/null
+++ b/board/cu824/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CU824 board
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c
new file mode 100755
index 0000000..5844a5c
--- /dev/null
+++ b/board/cu824/cu824.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+#define BOARD_REV_REG 0xFE80002B
+
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char  revision = *(volatile char *)(BOARD_REV_REG);
+	char  buf[32];
+
+	puts ("Board: CU824 ");
+	printf("Revision %d ", revision);
+	printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk));
+
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1,  mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_sandpoint_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_sandpoint_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
diff --git a/board/cu824/flash.c b/board/cu824/flash.c
new file mode 100755
index 0000000..7368176
--- /dev/null
+++ b/board/cu824/flash.c
@@ -0,0 +1,486 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x40000
+#define PARAM_SECT_SIZE 0x8000
+
+#define BOARD_CTRL_REG 0xFE800013
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+static int write_data (flash_info_t *info, ulong dest, ulong *data);
+static void write_via_fpu(vu_long *addr, ulong *data);
+static __inline__ unsigned long get_msr(void);
+static __inline__ void set_msr(unsigned long msr);
+
+/*---------------------------------------------------------------------*/
+#undef	DEBUG_FLASH
+
+/*---------------------------------------------------------------------*/
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+    int i, j;
+    ulong size = 0;
+    volatile unsigned char *bcr = (volatile unsigned char *)(BOARD_CTRL_REG);
+
+    DEBUGF("Write protect was: 0x%02X\n", *bcr);
+    *bcr &= 0x1;	/* FWPT must be 0  */
+    *bcr |= 0x6;	/* FWP0 = FWP1 = 1 */
+    DEBUGF("Write protect is:  0x%02X\n", *bcr);
+
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+	addr[0] = 0x00900090;
+
+	DEBUGF ("Flash bank # %d:\n"
+		"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+		"\tDevice ID @ 0x%08lX: 0x%08lX\n",
+		i,
+		(ulong)(&addr[0]), addr[0],
+		(ulong)(&addr[2]), addr[2]);
+
+	if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+	    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3B))
+	{
+	    flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				     (INTEL_ID_28F160F3B & FLASH_TYPEMASK);
+	} else {
+	    flash_info[i].flash_id = FLASH_UNKNOWN;
+	    addr[0] = 0xFFFFFFFF;
+	    goto Done;
+	}
+
+	DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+	addr[0] = 0xFFFFFFFF;
+
+	flash_info[i].size = FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	for (j = 0; j < flash_info[i].sector_count; j++) {
+		if (j <= 7) {
+			flash_info[i].start[j] = CFG_FLASH_BASE +
+						 i * FLASH_BANK_SIZE +
+						 j * PARAM_SECT_SIZE;
+		} else {
+			flash_info[i].start[j] = CFG_FLASH_BASE +
+						 i * FLASH_BANK_SIZE +
+						 (j - 7)*MAIN_SECT_SIZE;
+		}
+	}
+	size += flash_info[i].size;
+    }
+
+    /* Protect monitor and environment sectors
+     */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+    flash_protect(FLAG_PROTECT_SET,
+	      CFG_MONITOR_BASE,
+	      CFG_MONITOR_BASE + monitor_flash_len - 1,
+	      &flash_info[1]);
+#else
+    flash_protect(FLAG_PROTECT_SET,
+	      CFG_MONITOR_BASE,
+	      CFG_MONITOR_BASE + monitor_flash_len - 1,
+	      &flash_info[0]);
+#endif
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+    flash_protect(FLAG_PROTECT_SET,
+	      CFG_ENV_ADDR,
+	      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+	      &flash_info[1]);
+#else
+    flash_protect(FLAG_PROTECT_SET,
+	      CFG_ENV_ADDR,
+	      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+	      &flash_info[0]);
+#endif
+#endif
+
+Done:
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch ((i = info->flash_id & FLASH_VENDMASK)) {
+	case (FLASH_MAN_INTEL & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor 0x%04x ", i);
+		break;
+	}
+
+	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
+	case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
+		printf ("28F160F3B (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type 0x%04x\n", i);
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
+		info - &flash_info[0], s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+
+			DEBUGF ("Erase sect %d @ 0x%08lX\n",
+				sect, (ulong)addr);
+
+			/* Disable interrupts which might cause a timeout
+			 * here.
+			 */
+			flag = disable_interrupts();
+
+			addr[0] = 0x00500050;	/* clear status register */
+			addr[0] = 0x00200020;	/* erase setup */
+			addr[0] = 0x00D000D0;	/* erase confirm */
+
+			addr[1] = 0x00500050;	/* clear status register */
+			addr[1] = 0x00200020;	/* erase setup */
+			addr[1] = 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((addr[0] & 0x00800080) != 0x00800080) ||
+			       ((addr[1] & 0x00800080) != 0x00800080) ) {
+				if ((now=get_timer(start)) >
+					   CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					addr[0] = 0x00B000B0; /* suspend erase */
+					addr[0] = 0x00FF00FF; /* to read mode  */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {  /* every second  */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			addr[0] = 0x00FF00FF;
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	8	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp, cp, msr;
+	int l, rc, i;
+	ulong data[2];
+	ulong *datah = &data[0];
+	ulong *datal = &data[1];
+
+	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
+		addr, (ulong)src, cnt);
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	msr = get_msr();
+	set_msr(msr | MSR_FP);
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		*datah = *datal = 0;
+
+		for (i = 0, cp = wp; i < l; i++, cp++) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+						((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | (*(uchar *)cp);
+		}
+		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
+			char tmp;
+
+			tmp = *src;
+
+			src++;
+
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+						((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | tmp;
+
+			--cnt; ++cp;
+		}
+
+		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
+			if (i >= 4) {
+				*datah = (*datah << 8) |
+						((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datah << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			set_msr(msr);
+			return (rc);
+		}
+
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		*datah = *(ulong *)src;
+		*datal = *(ulong *)(src + 4);
+		if ((rc = write_data(info, wp, data)) != 0) {
+			set_msr(msr);
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+		src += FLASH_WIDTH;
+	}
+
+	if (cnt == 0) {
+		set_msr(msr);
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	*datah = *datal = 0;
+	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
+		char tmp;
+
+		tmp = *src;
+
+		src++;
+
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+		}
+
+		*datal = (*datal << 8) | tmp;
+
+		--cnt;
+	}
+
+	for (; i < FLASH_WIDTH; ++i, ++cp) {
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+		}
+
+		*datal = (*datal << 8) | (*(uchar *)cp);
+	}
+
+	rc = write_data(info, wp, data);
+	set_msr(msr);
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong *data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((addr[0] & data[0]) != data[0]) ||
+	    ((addr[1] & data[1]) != data[1]) ) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0] = 0x00400040;		/* write setup */
+	write_via_fpu(addr, data);
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((addr[0] & 0x00800080) != 0x00800080) ||
+	       ((addr[1] & 0x00800080) != 0x00800080) ) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			addr[0] = 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	addr[0] = 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu(vu_long *addr, ulong *data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)" : : "r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
+}
+/*-----------------------------------------------------------------------
+ */
+static __inline__ unsigned long get_msr(void)
+{
+    unsigned long msr;
+
+    __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
+    return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+    __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+}
diff --git a/board/cu824/u-boot.lds b/board/cu824/u-boot.lds
new file mode 100755
index 0000000..7be85e4
--- /dev/null
+++ b/board/cu824/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o (.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+		. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+		*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/dave/B2/B2.c b/board/dave/B2/B2.c
new file mode 100755
index 0000000..29676b8
--- /dev/null
+++ b/board/dave/B2/B2.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+/*
+ * Miscelaneous platform dependent initialization
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	u32 temp;
+
+	/* Configuration Port Control Register*/
+	/* Port A */
+	PCONA = 0x3ff;
+
+	/* Port B */
+	PCONB = 0xff;
+	PDATB = 0xFFFF;
+
+	/* Port C */
+	/*
+	PCONC = 0xff55ff15;
+	PDATC = 0x0;
+	PUPC = 0xffff;
+	*/
+
+	/* Port D */
+	/*
+	PCOND = 0xaaaa;
+	PUPD = 0xff;
+	*/
+
+	/* Port E */
+	PCONE = 0x0001aaa9;
+	PDATE = 0x0;
+	PUPE = 0xff;
+
+	/* Port F */
+	PCONF = 0x124955;
+	PDATF  = 0xff; /* B2-eth_reset tied high level */
+	/*
+	PUPF = 0x1e3;
+	*/
+
+	/* Port G */
+	PUPG = 0x1;
+	PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/
+
+	INTMSK = 0x03fffeff;
+	INTCON = 0x05;
+
+    /*
+    	Configure chip ethernet interrupt as High level
+    	Port G EINT 0-7 EINT0 -> CHIP ETHERNET
+    */
+	temp = EXTINT;
+   	temp &= ~0x7;
+    temp |= 0x1; /*LEVEL_HIGH*/
+	EXTINT = temp;
+
+    /*
+    	Reset SMSC LAN91C96 chip
+    */
+    temp= PCONF;
+    temp |= 0x00000040;
+    PCONF = temp;
+
+	/* Reset high */
+    temp = PDATF;
+    temp |= (1 << 3);
+    PDATF = temp;
+
+    /* Short delay */
+    for (temp=0;temp<10;temp++)
+    {
+		/* NOP */
+    }
+
+    /* Reset low */
+    temp = PDATF;
+    temp &= ~(1 << 3);
+    PDATF = temp;
+
+	/* arch number MACH_TYPE_MBA44B0 */
+	gd->bd->bi_arch_number = MACH_TYPE_S3C44B0;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = 0x0c000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/board/dave/B2/Makefile b/board/dave/B2/Makefile
new file mode 100755
index 0000000..548fd52
--- /dev/null
+++ b/board/dave/B2/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= B2.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/dave/B2/config.mk b/board/dave/B2/config.mk
new file mode 100755
index 0000000..5216622
--- /dev/null
+++ b/board/dave/B2/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x0C100000
+
+PLATFORM_CPPFLAGS += -Uarm
diff --git a/board/dave/B2/flash.c b/board/dave/B2/flash.c
new file mode 100755
index 0000000..ad67e86
--- /dev/null
+++ b/board/dave/B2/flash.c
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifdef __DEBUG_START_FROM_SRAM__
+	return CFG_DUMMY_FLASH_SIZE;
+#else
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (0, &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+#endif
+}
diff --git a/board/dave/B2/lowlevel_init.S b/board/dave/B2/lowlevel_init.S
new file mode 100755
index 0000000..2f3a364
--- /dev/null
+++ b/board/dave/B2/lowlevel_init.S
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures
+ * Modified By MATTO
+ *
+ * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+/*
+ * Documentation:
+ * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
+ *     Advanced Developer's manual, December 1999
+ *
+ * Intel has a very hard to find SDRAM configurator on their web site:
+ *   http://appzone.intel.com/hcd/sa1110/memory/index.asp
+ *
+ * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
+ * appears to be true, but it might be possible that somebody designs a
+ * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
+ *
+ * 04-10-2001:  SELETZ
+ * - separated memory config for multiple platform support
+ * - perform SA1110 Hardware Reset Procedure
+ *
+ */
+
+.equ    B0_Tacs,      0x0 /* 0clk */
+.equ    B0_Tcos,      0x0 /* 0clk */
+.equ    B0_Tacc,      0x4 /* 6clk */
+.equ    B0_Tcoh,      0x0 /* 0clk */
+.equ    B0_Tah,       0x0 /* 0clk */
+.equ    B0_Tacp,      0x0 /* 0clk */
+.equ    B0_PMC,       0x0 /* normal(1data) */
+/* Bank 1 parameter */
+.equ    B1_Tacs,      0x3 /* 4clk */
+.equ    B1_Tcos,      0x3 /* 4clk */
+.equ    B1_Tacc,      0x7 /* 14clkv */
+.equ    B1_Tcoh,      0x3 /* 4clk */
+.equ    B1_Tah,       0x3 /* 4clk */
+.equ    B1_Tacp,      0x3 /* 6clk */
+.equ    B1_PMC,       0x0 /* normal(1data) */
+
+/* Bank 2 parameter - LAN91C96 */
+.equ    B2_Tacs,      0x3 /* 4clk */
+.equ    B2_Tcos,      0x3 /* 4clk */
+.equ    B2_Tacc,      0x7 /* 14clk */
+.equ    B2_Tcoh,      0x3 /* 4clk */
+.equ    B2_Tah,       0x3 /* 4clk */
+.equ    B2_Tacp,      0x3 /* 6clk */
+.equ    B2_PMC,       0x0 /* normal(1data) */
+
+/* Bank 3 parameter */
+.equ    B3_Tacs,      0x3 /* 4clk */
+.equ    B3_Tcos,      0x3 /* 4clk */
+.equ    B3_Tacc,      0x7 /* 14clk */
+.equ    B3_Tcoh,      0x3 /* 4clk */
+.equ    B3_Tah,       0x3 /* 4clk */
+.equ    B3_Tacp,      0x3 /* 6clk */
+.equ    B3_PMC,       0x0 /* normal(1data) */
+
+/* Bank 4 parameter */
+.equ    B4_Tacs,      0x3 /* 4clk */
+.equ    B4_Tcos,      0x3 /* 4clk */
+.equ    B4_Tacc,      0x7 /* 14clk */
+.equ    B4_Tcoh,      0x3 /* 4clk */
+.equ    B4_Tah,       0x3 /* 4clk */
+.equ    B4_Tacp,      0x3 /* 6clk */
+.equ    B4_PMC,       0x0 /* normal(1data) */
+
+/* Bank 5 parameter */
+.equ    B5_Tacs,      0x3 /* 4clk */
+.equ    B5_Tcos,      0x3 /* 4clk */
+.equ    B5_Tacc,      0x7 /* 14clk */
+.equ    B5_Tcoh,      0x3 /* 4clk */
+.equ    B5_Tah,       0x3 /* 4clk */
+.equ    B5_Tacp,      0x3 /* 6clk */
+.equ    B5_PMC,       0x0 /* normal(1data) */
+
+/* Bank 6(if SROM) parameter */
+.equ    B6_Tacs,      0x3 /* 4clk */
+.equ    B6_Tcos,      0x3 /* 4clk */
+.equ    B6_Tacc,      0x7 /* 14clk */
+.equ    B6_Tcoh,      0x3 /* 4clk */
+.equ    B6_Tah,       0x3 /* 4clk */
+.equ    B6_Tacp,      0x3 /* 6clk */
+.equ    B6_PMC,       0x0 /* normal(1data) */
+
+/* Bank 7(if SROM) parameter */
+.equ    B7_Tacs,      0x3 /* 4clk */
+.equ    B7_Tcos,      0x3 /* 4clk */
+.equ    B7_Tacc,      0x7 /* 14clk */
+.equ    B7_Tcoh,      0x3 /* 4clk */
+.equ    B7_Tah,       0x3 /* 4clk */
+.equ    B7_Tacp,      0x3 /* 6clk */
+.equ    B7_PMC,       0x0 /* normal(1data) */
+
+/* Bank 6 parameter */
+.equ    B6_MT,        0x3 /* SDRAM */
+.equ    B6_Trcd,      0x0 /* 2clk */
+.equ    B6_SCAN,      0x0 /* 10bit */
+
+.equ    B7_MT,        0x3 /* SDRAM */
+.equ    B7_Trcd,      0x0 /* 2clk */
+.equ    B7_SCAN,      0x0 /* 10bit */
+
+
+/* REFRESH parameter */
+.equ    REFEN,        0x1 /* Refresh enable */
+.equ    TREFMD,       0x0 /* CBR(CAS before RAS)/Auto refresh */
+.equ    Trp,        0x0 /* 2clk */
+.equ    Trc,        0x3 /* 0x1=5clk 0x3=11clk*/
+.equ    Tchr,       0x0 /* 0x2=3clk 0x0=0clks  */
+.equ    REFCNT,       879
+
+MEMORY_CONFIG:
+  .long   0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/
+  .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/
+  .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/
+  .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/
+  .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/
+  .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/
+  .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/
+  .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))  /*GCS6*/
+  .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))  /*GCS7*/
+  .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)  /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/
+  .word 0x17      /*SCLK power down mode, BANKSIZE 16M/16M*/
+  .word 0x20      /*MRSR6 CL=2clk*/
+  .word 0x20      /*MRSR7*/
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*
+		the next instruction fail due memory relocation...
+		we'll find the right MEMORY_CONFIG address with the next 3 lines...
+	*/
+	/*ldr r0, =MEMORY_CONFIG*/
+	mov r0, pc
+	ldr r1, =(0x38+4)
+	sub r0, r0, r1
+
+	ldmia r0, {r1-r13}
+	ldr   r0, =0x01c80000
+	stmia r0, {r1-r13}
+	mov pc, lr
diff --git a/board/dave/B2/u-boot.lds b/board/dave/B2/u-boot.lds
new file mode 100755
index 0000000..e10ac43
--- /dev/null
+++ b/board/dave/B2/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/s3c44b0/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+	armboot_end_data = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile
new file mode 100755
index 0000000..39d2fec
--- /dev/null
+++ b/board/dave/PPChameleonEVB/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
new file mode 100755
index 0000000..5f2c705
--- /dev/null
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2003
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+int board_early_init_f (void)
+{
+	out32(GPIO0_OR, CFG_NAND0_CE);                 /* set initial outputs     */
+	out32(GPIO0_OR, CFG_NAND1_CE);                 /* set initial outputs     */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0)
+	 * IRQ 26 (EXT IRQ 1)
+	 * IRQ 27 (EXT IRQ 2)
+	 * IRQ 28 (EXT IRQ 3)
+	 * IRQ 29 (EXT IRQ 4)
+	 * IRQ 30 (EXT IRQ 5)
+	 * IRQ 31 (EXT IRQ 6)
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+#if 1 /* test-only */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+#else
+	mtebc (epcr, 0x28400000); /* ebc in high-z */
+#endif
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart = 0 - flash_info[0].size;
+	gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
+#if 0
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned char *duart0_mcr =
+		(unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr =
+		(unsigned char *)((ulong)DUART1_BA + 4);
+
+	bd_t *bd = gd->bd;
+	char *	tmp;                    /* Temporary char pointer      */
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned long cntrl0Reg;
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+#endif
+
+#if 0
+	/*
+	 * Enable power on PS/2 interface
+	 */
+	*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+#endif
+	return (0);
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming PPChameleonEVB");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0 /* test-only */
+	for (;;) {
+		NAND_DISABLE_CE(1);
+		udelay(100);
+		NAND_ENABLE_CE(1);
+		udelay(100);
+	}
+#endif
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong
+nand_probe(ulong physadr);
+
+void
+nand_init(void)
+{
+	ulong totlen = 0;
+
+/*
+	The HI model is equipped with a large block NAND chip not supported yet
+	by U-Boot
+    (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+*/
+
+#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
+	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
+	totlen += nand_probe (CFG_NAND0_BASE);
+#endif	/* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
+
+	debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
+	totlen += nand_probe (CFG_NAND1_BASE);
+
+	printf ("%3lu MB\n", totlen >>20);
+}
+#endif
+
+#ifdef CONFIG_CFB_CONSOLE
+# ifdef CONFIG_CONSOLE_EXTRA_INFO
+# include <video_fb.h>
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+	uint pvr = get_pvr ();
+
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		switch (pvr) {
+		case PVR_405EP_RB:
+			sprintf (info, " AMCC PowerPC 405EP Rev. B");
+			break;
+		default:
+			sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
+			break;
+		}
+		return;
+	case 2:
+		sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
+
+	/* no more info lines */
+	*info = 0;
+	return;
+}
+# endif	/* CONFIG_CONSOLE_EXTRA_INFO */
+#endif	/* CONFIG_CFB_CONSOLE */
diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk
new file mode 100755
index 0000000..5856aec
--- /dev/null
+++ b/board/dave/PPChameleonEVB/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Reserve 256 kB for Monitor
+TEXT_BASE = 0xFFFC0000
+
+# Reserve 320 kB for Monitor
+#TEXT_BASE = 0xFFFB0000
diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c
new file mode 100755
index 0000000..692d275
--- /dev/null
+++ b/board/dave/PPChameleonEVB/flash.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifdef __DEBUG_START_FROM_SRAM__
+	return CFG_DUMMY_FLASH_SIZE;
+#else
+	unsigned long size;
+	int i;
+	uint pbcr;
+	unsigned long base;
+	int size_val = 0;
+
+	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+	debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info);
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
+	/* Setup offsets */
+	flash_get_offsets (-size, &flash_info[0]);
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base = -size;
+	switch (size) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+	flash_info[0].size  = size;
+
+	return (size);
+#endif
+}
diff --git a/board/dave/PPChameleonEVB/fpgadata.c b/board/dave/PPChameleonEVB/fpgadata.c
new file mode 100755
index 0000000..f5e30dd
--- /dev/null
+++ b/board/dave/PPChameleonEVB/fpgadata.c
@@ -0,0 +1,1139 @@
+  0x1f,0x8b,0x08,0x08,0x80,0xb0,0xc0,0x3e,0x00,0x03,0x61,0x73,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0x94,0x9b,0x7f,0x70,0x14,0x65,
+  0x9a,0xc7,0x9f,0xe9,0xee,0x24,0x9d,0x99,0x4e,0xa6,0x0d,0x84,0x42,0xe5,0x47,0xe7,
+  0xc7,0xba,0xa3,0x37,0x0c,0x63,0x82,0x9a,0x05,0x32,0x69,0x03,0x7f,0xe4,0x84,0x2d,
+  0xd9,0xbd,0xba,0xaa,0xdb,0x5a,0x6b,0x1d,0x5d,0xbc,0xe2,0xb6,0xd0,0xca,0xea,0x55,
+  0x1d,0x67,0x6d,0xdd,0xbd,0x24,0x39,0x08,0x07,0x2b,0x01,0xb9,0x23,0xee,0x51,0x5c,
+  0xf3,0x63,0xcb,0xa8,0xa9,0xad,0x11,0x76,0x0d,0x0a,0xa5,0x4d,0x2e,0x8b,0x21,0x44,
+  0xc8,0xb1,0xd6,0x6e,0x44,0x97,0x1d,0x34,0xab,0x23,0x72,0x18,0xd1,0x92,0x44,0x20,
+  0xb9,0xf7,0xed,0xee,0xf7,0xed,0x9f,0x33,0xc9,0x8e,0x7f,0xf8,0xe4,0x9d,0xd7,0xf6,
+  0x7d,0x9e,0x79,0xfb,0x79,0x3e,0xfd,0x7d,0xde,0x86,0xd2,0xe8,0xb8,0xf9,0x0f,0x40,
+  0xe8,0x31,0x90,0x1f,0x7b,0x66,0xc3,0xb2,0xe4,0x7d,0x8f,0xde,0xfb,0x68,0x32,0x99,
+  0x78,0xea,0xc7,0xeb,0xe1,0x71,0x88,0xd4,0x3d,0x73,0x5f,0xf2,0x89,0x7f,0xfc,0xe9,
+  0xbd,0xcb,0x96,0xc1,0x8f,0xf1,0x5f,0xc9,0x64,0xfd,0xd2,0xe4,0x7d,0x4b,0xef,0xad,
+  0x87,0xf5,0x50,0x7a,0x6f,0x72,0xf9,0xb2,0x65,0xcb,0x97,0x35,0xc0,0x13,0x10,0xaa,
+  0x3f,0x3c,0x8d,0x3f,0x2f,0xbf,0xf0,0xb7,0x7f,0x9f,0x04,0x14,0x02,0x80,0x92,0x64,
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+  0x14,0xe4,0x89,0xff,0xcc,0xe3,0x77,0x15,0xd7,0xfb,0x5f,0x2b,0x92,0xad,0x46,0xf1,
+  0x33,0x01,0x00,
diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds
new file mode 100755
index 0000000..481d291
--- /dev/null
+++ b/board/dave/PPChameleonEVB/u-boot.lds
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  . = 0xFFFF8000;
+  .ppcenv :
+  {
+    common/environment.o(.ppcenv);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c
new file mode 100755
index 0000000..bf0f2bf
--- /dev/null
+++ b/board/dave/common/flash.c
@@ -0,0 +1,706 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	short n;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("ST  ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AM640U:	printf ("AM29LV640D (64 M, uniform sector)\n");
+				break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_STMW320DT:	printf ("M29W320DT (32 M, top sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+
+	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CFG_FLASH_READ0];
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CFG_FLASH_READ1];		/* device ID		*/
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;  break;	/* => 8 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		/*  1 x 16k boot sector */
+		base -= 16 << 10;
+		--i;
+		info->start[i] = base;
+		/*  2 x 8k  boot sectors */
+		for (n=0; n<2; ++n) {
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		/*  1 x 32k boot sector */
+		base -= 32 << 10;
+		--i;
+		info->start[i] = base;
+
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+		    addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			for (i=0; i<50; i++)
+			  udelay(1000);  /* wait 1 ms */
+		    } else {
+			if (sect == s_first) {
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			}
+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    }
+		    l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+#ifdef CONFIG_B2
+			data = data | ((*(uchar *)cp)<<(8*i));
+#else
+			data = (data << 8) | (*(uchar *)cp);
+#endif
+		}
+		for (; i<4 && cnt>0; ++i) {
+#ifdef CONFIG_B2
+			data = data  | ((*src++)<<(8*i));
+#else
+			data = (data << 8) | *src++;
+#endif
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+#ifdef CONFIG_B2
+			data = data | ((*(uchar *)cp)<<(8*i));
+#else
+			data = (data << 8) | (*(uchar *)cp);
+#endif
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+#ifdef CONFIG_B2
+		data = (*(ulong*)src);
+		src += 4;
+#else
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+#endif
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+#ifdef CONFIG_B2
+		data = data  | ((*src++)<<(8*i));
+#else
+		data = (data << 8) | *src++;
+#endif
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+#ifdef CONFIG_B2
+		data = data | ((*(uchar *)cp)<<(8*i));
+#else
+		data = (data << 8) | (*(uchar *)cp);
+#endif
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile ulong *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c
new file mode 100755
index 0000000..5b5b5e9
--- /dev/null
+++ b/board/dave/common/fpga.c
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2001-2003
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
+#define MAX_ONES               226
+
+#ifdef CFG_FPGA_PRG
+# define FPGA_PRG              CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
+# define FPGA_CLK              CFG_FPGA_CLK /* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CFG_FPGA_DATA /* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CFG_FPGA_DONE /* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CFG_FPGA_INIT /* FPGA init pin (ppc input)   */
+#else
+# define FPGA_PRG              0x04000000  /* FPGA program pin (ppc output) */
+# define FPGA_CLK              0x02000000  /* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             0x01000000  /* FPGA data pin (ppc output)    */
+# define FPGA_DONE             0x00800000  /* FPGA done pin (ppc input)     */
+# define FPGA_INIT             0x00400000  /* FPGA init pin (ppc input)     */
+#endif
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
+
+#define SET_FPGA(data)         out32(GPIO0_OR, data)
+
+#define FPGA_WRITE_1 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#define FPGA_WRITE_0 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+
+#if 0
+static int fpga_boot (unsigned char *fpgadata, int size)
+{
+	int i, index, len;
+	int count;
+
+#ifdef CFG_FPGA_SPARTAN2
+	int j;
+#else
+	unsigned char b;
+	int bit;
+#endif
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+#ifdef CFG_FPGA_SPARTAN2
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+		    && (fpgadata[index + 2] == 0xff)
+		    && (fpgadata[index + 3] == 0xff))
+			break;	/* preamble found */
+		else
+			index++;
+	}
+#else
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < size - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
+			break;
+	}
+	index += 2;
+#endif
+
+	DBG ("FPGA: configdata starts at position 0x%x\n", index);
+	DBG ("FPGA: length of fpga-data %d\n", size - index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+	out32 (GPIO0_ODR, 0x00000000);	/* no open drain pins */
+	out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA);	/* setup for output */
+	out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA);	/* set pins to high */
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA (FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (in32 (GPIO0_IR) & FPGA_INIT) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/* deassert PROGRAM* */
+	SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(in32 (GPIO0_IR) & FPGA_INIT)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	DBG ("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+#ifdef CFG_FPGA_SPARTAN2
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i = index; i < size; i++) {
+		for (j = 0; j < 8; j++) {
+			if ((fpgadata[i] & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			fpgadata[i] <<= 1;
+		}
+	}
+#else	/* ! CFG_FPGA_SPARTAN2 */
+	/* send 0xff 0x20 */
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+
+	/*
+	 ** Bit_DeCompression
+	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
+	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
+	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
+	 **        255                        :                   '1'
+	 */
+
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		if ((b >= 1) && (b <= MAX_ONES)) {
+			for (bit = 0; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+			FPGA_WRITE_0;
+		} else if (b == (MAX_ONES + 1)) {
+			for (bit = 1; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+				FPGA_WRITE_0;
+			}
+			FPGA_WRITE_1;
+		} else if (b == 255) {
+			FPGA_WRITE_1;
+		}
+	}
+#endif	/* CFG_FPGA_SPARTAN2 */
+
+	DBG ("%s, ",
+	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	DBG ("%s\n",
+	     ((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(in32 (GPIO0_IR) & FPGA_DONE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			DBG ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	DBG ("FPGA: Booting successful!\n");
+	return 0;
+}
+#endif	/* 0 */
diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c
new file mode 100755
index 0000000..f8f180c
--- /dev/null
+++ b/board/dave/common/pci.c
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+
+u_long pci9054_iobase;
+
+
+#define PCI_PRIMARY_CAR	(0x500000dc) /* PCI config address reg */
+#define PCI_PRIMARY_CDR	(0x80000000) /* PCI config data    reg */
+
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_read_config_dword
+|  Description: Read a PCI configuration register
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               value           Address of the configuration register value
+|  Return value:
+|               0               Successful
++-----------------------------------------------------------------------------*/
+int pci9054_read_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32* value)
+{
+  unsigned long      conAdrVal;
+  unsigned long      val;
+
+  /* generate coded value for CON_ADR register */
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  /* Note: *pResult comes back as -1 if machine check happened */
+  val = in32r(PCI_PRIMARY_CDR);
+
+  *value = (unsigned long) val;
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  if ((*(unsigned long *)0x50000304) & 0x60000000)
+    {
+      /* clear pci master/target abort bits */
+      *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+    }
+
+  return 0;
+}
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_write_config_dword
+|  Description: Write a PCI configuration register.
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               Value           Configuration register value
+|  Return value:
+|               0               Successful
+| Updated for pass2 errata #6. Need to disable interrupts and clear the
+| PCICFGADR reg after writing the PCICFGDATA reg.
++-----------------------------------------------------------------------------*/
+int pci9054_write_config_dword(struct pci_controller *hose,
+			       pci_dev_t dev, int offset, u32 value)
+{
+  unsigned long      conAdrVal;
+
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  out32r(PCI_PRIMARY_CDR, value);
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  /* clear pci master/target abort bits */
+  *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_DASA_SIM
+static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
+					struct pci_config_table *_)
+{
+  unsigned int iobase;
+  unsigned short status = 0;
+  unsigned char timer;
+
+  /*
+   * Configure PLX PCI9054
+   */
+  pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status);
+  status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+  pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status);
+
+  /* Check the latency timer for values >= 0x60.
+   */
+  pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+  if (timer < 0x60)
+    {
+      pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+    }
+
+  /* Set I/O base register.
+   */
+  pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE);
+  pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+
+  pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+  if (pci9054_iobase == 0xffffffff)
+    {
+      printf("Error: Can not set I/O base register.\n");
+      return;
+    }
+}
+#endif
+
+static struct pci_config_table pci9054_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
+    pci_cfgfunc_config_device, { CFG_ETH_IOBASE,
+				 CFG_ETH_IOBASE,
+				 PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
+#ifdef CONFIG_DASA_SIM
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN),
+    pci_dasa_sim_config_pci9054 },
+#endif
+#endif
+  { }
+};
+
+static struct pci_controller pci9054_hose = {
+  config_table: pci9054_config_table,
+};
+
+void pci_init(void)
+{
+  struct pci_controller *hose = &pci9054_hose;
+
+  /*
+   * Register the hose
+   */
+  hose->first_busno = 0;
+  hose->last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(hose->regions + 0,
+		 0x00000000, 0x00000000, 0x01000000,
+		 PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+  /* PCI Memory space */
+  pci_set_region(hose->regions + 1,
+		 0x00000000, 0xc0000000, 0x10000000,
+		 PCI_REGION_MEM);
+
+  pci_set_ops(hose,
+	      pci_hose_read_config_byte_via_dword,
+	      pci_hose_read_config_word_via_dword,
+	      pci9054_read_config_dword,
+	      pci_hose_write_config_byte_via_dword,
+	      pci_hose_write_config_word_via_dword,
+	      pci9054_write_config_dword);
+
+  hose->region_count = 2;
+
+  pci_register_hose(hose);
+
+  hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile
new file mode 100755
index 0000000..d9b0e2d
--- /dev/null
+++ b/board/dbau1x00/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= lowlevel_init.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/dbau1x00/README b/board/dbau1x00/README
new file mode 100755
index 0000000..b37ff36
--- /dev/null
+++ b/board/dbau1x00/README
@@ -0,0 +1,63 @@
+By Thomas.Lange@corelatus.se 2004-Oct-05
+----------------------------------------
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
+
+Limitations & comments
+----------------------
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which
+should be supported RSN.
+
+I only have a dbau1000, so my testing is limited
+to this board.
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped.
+Have this in mind when you compile u-boot. TEXT_BASE has
+to match the address where u-boot is located when you
+actually launch.
+
+Ethernet only supported for mac0.
+
+PCMCIA only supported for slot 0, only 3.3V.
+
+PCMCIA IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+########     NOTE!!!!!!   #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA and running cpu in big endian mode!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
diff --git a/board/dbau1x00/config.mk b/board/dbau1x00/config.mk
new file mode 100755
index 0000000..39eb60a
--- /dev/null
+++ b/board/dbau1x00/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
+#
+
+# ROM version
+TEXT_BASE = 0xbfc00000
+
+# RAM version
+#TEXT_BASE = 0x80100000
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
new file mode 100755
index 0000000..d29e8d5
--- /dev/null
+++ b/board/dbau1x00/dbau1x00.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+long int initdram(int board_type)
+{
+	/* Sdram is setup by assembler code */
+	/* If memory could be changed, we should return the true value here */
+	return MEM_SIZE*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN		0x0010
+#define BCSR_PCMCIA_PC0RST		0x0080
+
+/* In cpu/mips/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+#ifdef CONFIG_IDE_PCMCIA
+	u16 status;
+	volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
+#endif	/* CONFIG_IDE_PCMCIA */
+	volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
+	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+	u32 proc_id;
+
+	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+	proc_id = read_32bit_cp0_register(CP0_PRID);
+
+	switch (proc_id >> 24) {
+	case 0:
+		puts ("Board: Merlot (DbAu1000)\n");
+		printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 1:
+		puts ("Board: DbAu1500\n");
+		printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 2:
+		puts ("Board: DbAu1100\n");
+		printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 3:
+		puts ("Board: DbAu1550\n");
+		printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	default:
+		printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+	}
+#ifdef CONFIG_IDE_PCMCIA
+	/* Enable 3.3 V on slot 0 ( VCC )
+	   No 5V */
+	status = 4;
+	*pcmcia_bcsr = status;
+
+	status |= BCSR_PCMCIA_PC0DRVEN;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(300*1000);
+
+	status |= BCSR_PCMCIA_PC0RST;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(100*1000);
+
+	/* PCMCIA is on a 36 bit physical address.
+	   We need to map it into a 32 bit addresses */
+
+#if 0
+	/* We dont need theese unless we run whole pcmcia package */
+	write_one_tlb(20,                 /* index */
+		      0x01ffe000,         /* Pagemask, 16 MB pages */
+		      CFG_PCMCIA_IO_BASE, /* Hi */
+		      0x3C000017,         /* Lo0 */
+		      0x3C200017);        /* Lo1 */
+
+	write_one_tlb(21,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CFG_PCMCIA_ATTR_BASE, /* Hi */
+		      0x3D000017,           /* Lo0 */
+		      0x3D200017);          /* Lo1 */
+#endif	/* 0 */
+	write_one_tlb(22,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CFG_PCMCIA_MEM_ADDR,  /* Hi */
+		      0x3E000017,           /* Lo0 */
+		      0x3E200017);          /* Lo1 */
+#endif	/* CONFIG_IDE_PCMCIA */
+
+	/* Release reset of ethernet PHY chips */
+	/* Always do this, because linux does not know about it */
+	*phy = 3;
+
+	return 0;
+}
diff --git a/board/dbau1x00/flash.c b/board/dbau1x00/flash.c
new file mode 100755
index 0000000..3cf29e8
--- /dev/null
+++ b/board/dbau1x00/flash.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	printf ("Skipping flash_init\n");
+	return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	printf ("write_buff not implemented\n");
+	return (-1);
+}
diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
new file mode 100755
index 0000000..7afd584
--- /dev/null
+++ b/board/dbau1x00/lowlevel_init.S
@@ -0,0 +1,587 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR		0xB1900000
+#define sys_endian		0x0038
+#define CP0_Config0		$16
+#define CPU_SCALE		((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS			((CFG_MHZ) * 1000)
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	lowlevel_init
+lowlevel_init:
+	/*
+	 * Step 1) Establish CPU endian mode.
+	 * Db1500-specific:
+	 * Switch S1.1 Off(bit7 reads 1) is Little Endian
+	 * Switch S1.1 On (bit7 reads 0) is Big Endian
+	 */
+#ifdef CONFIG_DBAU1550
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000040
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#else
+	li	t0, MEM_STCFG1
+	li	t1, 0x00000080
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME1
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR1
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#endif
+
+	li	t0, DB1XX0_BCSR_ADDR
+	lw	t1,8(t0)
+	andi	t1,t1,0x80
+	beq	zero,t1,big_endian
+	nop
+little_endian:
+
+	/* Change Au1 core to little endian */
+	li	t0, AU1500_SYS_ADDR
+	li	t1, 1
+	sw	t1, sys_endian(t0)
+	mfc0	t2, CP0_CONFIG
+	mtc0	t2, CP0_CONFIG
+	nop
+	nop
+
+	/* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+	/*
+	 * Step 2) Establish Status Register
+	 * (set BEV, clear ERL, clear EXL, clear IE)
+	 */
+	li	t1, 0x00400000
+	mtc0	t1, CP0_STATUS
+
+	/*
+	 * Step 3) Establish CP0 Config0
+	 * (set OD, set K0=3)
+	 */
+	li	t1, 0x00080003
+	mtc0	t1, CP0_CONFIG
+
+	/*
+	 * Step 4) Disable Watchpoint facilities
+	 */
+	li t1, 0x00000000
+	mtc0	t1, CP0_WATCHLO
+	mtc0	t1, CP0_IWATCHLO
+	/*
+	 * Step 5) Disable the performance counters
+	 */
+	mtc0	zero, CP0_PERFORMANCE
+	nop
+
+	/*
+	 * Step 6) Establish EJTAG Debug register
+	 */
+	mtc0	zero, CP0_DEBUG
+	nop
+
+	/*
+	 * Step 7) Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* Establish Wired (and Random) */
+	mtc0	zero, CP0_WIRED
+	nop
+
+#ifdef CONFIG_DBAU1550
+	/* No workaround if running from ram */
+	lui	t0, 0xffc0
+	lui	t3, 0xbfc0
+	and	t1, ra, t0
+	bne	t1, t3, noCacheJump
+	nop
+
+	/*** From AMD YAMON ***/
+	/*
+	 * Step 8) Initialize the caches
+	 */
+	li		t0, (16*1024)
+	li		t1, 32
+	li		t2, 0x80000000
+	addu	t3, t0, t2
+cacheloop:
+	cache	0, 0(t2)
+	cache	1, 0(t2)
+	addu	t2, t1
+	bne		t2, t3, cacheloop
+	nop
+
+	/* Save return address */
+	move		t3, ra
+
+	/* Run from cacheable space now */
+	bal		cachehere
+	nop
+cachehere:
+	li		t1, ~0x20000000 /* convert to KSEG0 */
+	and		t0, ra, t1
+	addi	t0, 5*4			/* 5 insns beyond cachehere */
+	jr		t0
+	nop
+
+	/* Restore return address */
+	move		ra, t3
+
+	/*
+	 * Step 9) Initialize the TLB
+	 */
+	li		t0, 0			# index value
+	li		t1, 0x00000000		# entryhi value
+	li		t2, 32			# 32 entries
+
+tlbloop:
+	/* Probe TLB for matching EntryHi */
+	mtc0	t1, CP0_ENTRYHI
+	tlbp
+	nop
+
+	/* Examine Index[P], 1=no matching entry */
+	mfc0	t3, CP0_INDEX
+	li	t4, 0x80000000
+	and	t3, t4, t3
+	addiu	t1, t1, 1		# increment t1 (asid)
+	beq	zero, t3, tlbloop
+	nop
+
+	/* Initialize the TLB entry */
+	mtc0	t0, CP0_INDEX
+	mtc0	zero, CP0_ENTRYLO0
+	mtc0	zero, CP0_ENTRYLO1
+	mtc0	zero, CP0_PAGEMASK
+	tlbwi
+
+	/* Do it again */
+	addiu	t0, t0, 1
+	bne	t0, t2, tlbloop
+	nop
+
+	/* First setup pll:s to make serial work ok */
+	/* We have a 12 MHz crystal */
+	li	t0, SYS_CPUPLL
+	li	t1, CPU_SCALE  /* CPU clock */
+	sw	t1, 0(t0)
+	sync
+	nop
+	nop
+
+	/* wait 1mS for clocks to settle */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+	/* Setup AUX PLL */
+	li	t0, SYS_AUXPLL
+	li	t1, 0x20 /* 96 MHz */
+	sw	t1, 0(t0) /* aux pll */
+	sync
+
+	/*  Static memory controller */
+	/* RCE0 - can not change while fetching, do so from icache */
+	move		t2, ra /* Store return address */
+	bal		getAddr
+	nop
+
+getAddr:
+	move		t1, ra
+	move		ra, t2 /* Move return addess back */
+
+	cache	0x14,0(t1)
+	cache	0x14,32(t1)
+	/*** /From YAMON ***/
+
+noCacheJump:
+#endif /* CONFIG_DBAU1550 */
+
+#ifdef CONFIG_DBAU1550
+	li	t0, MEM_STTIME0
+	li	t1, 0x040181D7
+	sw	t1, 0(t0)
+
+	/* RCE0 AMD MirrorBit Flash (?) */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00000003
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR0
+	li	t1, 0x11803E00
+	sw	t1, 0(t0)
+#else /* CONFIG_DBAU1550 */
+	li	t0, MEM_STTIME0
+	li	t1, 0x00014C0F
+	sw	t1, 0(t0)
+
+	/* RCE0 AMD 29LV640M MirrorBit Flash */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00000013
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR0
+	li	t1, 0x11E03F80
+	sw	t1, 0(t0)
+#endif /* CONFIG_DBAU1550 */
+
+	/* RCE1 CPLD Board Logic */
+	li	t0, MEM_STCFG1
+	li	t1, 0x00000080
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME1
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR1
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+
+#ifdef CONFIG_DBAU1550
+	/* RCE2 CPLD Board Logic */
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000040
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#else
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+#endif
+
+	/* RCE3 PCMCIA 250ns */
+	li	t0, MEM_STCFG3
+	li	t1, 0x00000002
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME3
+	li	t1, 0x280E3E07
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR3
+	li	t1, 0x10000000
+	sw	t1, 0(t0)
+
+	sync
+
+	/* Set peripherals to a known state */
+	li	t0, IC0_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, IC1_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, SYS_FREQCTRL0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_FREQCTRL1
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_CLKSRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_PININPUTEN
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, 0xB1100100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, 0xB1400100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+
+	li	t0, SYS_WAKEMSK
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_WAKESRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	/* wait 1mS before setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+#ifdef CONFIG_DBAU1550
+/* SDCS 0,1,2 DDR SDRAM */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0xe21003f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0xe21043f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0xe21083f0
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9030060a /* Program refresh - disabled */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDCONFIGB
+	li	t1, 0x00028000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	li	t1, 0
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	sw	zero, 0(t0)
+	sync
+
+	/* Issue 2 autoref */
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+
+	/* Enable refresh */
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9830060a /* Program refresh - enabled */
+	sw	t1, 0(t0)
+	sync
+
+#else /* CONFIG_DBAU1550 */
+/* SDCS 0,1 SDRAM */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x005522AA
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x005522AA
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0x001003F8
+	sw	t1, 0(t0)
+
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0x001023F8
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x64000C24 /* Disable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x66000C24 /* Enable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000033
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000033
+	sw	t1, 0(t0)
+	sync
+
+#endif /* CONFIG_DBAU1550 */
+	/* wait 1mS after setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+	li	t0, SYS_PINFUNC
+	li	t1, 0x00008080
+	sw	t1, 0(t0)
+
+	li	t0, SYS_TRIOUTCLR
+	li	t1, 0x00001FFF
+	sw	t1, 0(t0)
+
+	li	t0, SYS_OUTPUTCLR
+	li	t1, 0x00008000
+	sw	t1, 0(t0)
+	sync
+
+	j	ra
+	nop
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
new file mode 100755
index 0000000..10c9917
--- /dev/null
+++ b/board/dbau1x00/u-boot.lds
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
diff --git a/board/dnp1110/Makefile b/board/dnp1110/Makefile
new file mode 100755
index 0000000..eaa38bc
--- /dev/null
+++ b/board/dnp1110/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= dnp1110.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/dnp1110/config.mk b/board/dnp1110/config.mk
new file mode 100755
index 0000000..4f6af46
--- /dev/null
+++ b/board/dnp1110/config.mk
@@ -0,0 +1,17 @@
+#
+# DNP/1110 board with SA1100 cpu
+#
+# http://www.dilnetpc.com
+#
+
+#
+# DILNETPC has 1 banks of 32 MB DRAM
+#
+# c000'0000
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to c1f8'0000, the upper 1 MB of the first (only) bank
+#
+
+TEXT_BASE = 0xc1f80000
diff --git a/board/dnp1110/dnp1110.c b/board/dnp1110/dnp1110.c
new file mode 100755
index 0000000..24c3e00
--- /dev/null
+++ b/board/dnp1110/dnp1110.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of DNP1110-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_DNP1110;
+
+    /* flash vpp on */
+    PPDR |= 0x80;	/* assumes LCD controller is off */
+    PPSR |= 0x80;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/board/dnp1110/flash.c b/board/dnp1110/flash.c
new file mode 100755
index 0000000..60874ba
--- /dev/null
+++ b/board/dnp1110/flash.c
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int   write_data (flash_info_t *info, ulong dest, FPW data);
+static void  flash_get_offsets (ulong base, flash_info_t *info);
+void inline  spin_wheel(void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+   int i;
+    ulong size = 0;
+
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    {
+	switch (i)
+	{
+	   case 0:
+	    flash_get_size((FPW *)PHYS_FLASH_1, &flash_info[i]);
+		 flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
+		break;
+	   default:
+		panic("configured too many flash banks!\n");
+		break;
+	}
+	size += flash_info[i].size;
+    }
+
+    /* Protect monitor and environment sectors
+     */
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_FLASH_BASE,
+		  CFG_FLASH_BASE + monitor_flash_len  - 1,
+		  &flash_info[0]);
+
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_ENV_ADDR,
+		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		  &flash_info[0]);
+
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+   case FLASH_28F128J3A:
+				printf ("28F128J3A\n"); break;
+	default:		printf ("Unknown Chip Type\n"); break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+		printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW)0x00AA00AA;
+	addr[0x2AAA] = (FPW)0x00550055;
+	addr[0x5555] = (FPW)0x00900090;
+
+   mb();
+	value = addr[0];
+
+   switch (value) {
+
+   case (FPW)INTEL_MANUFACT:
+      info->flash_id = FLASH_MAN_INTEL;
+      break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+   mb();
+	value = addr[1];			/* device ID		*/
+   switch (value) {
+
+   case (FPW)INTEL_ID_28F128J3A:
+      info->flash_id += FLASH_28F128J3A;
+      info->sector_count = 128;
+      info->size = 0x02000000;
+      break;            /* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+    }
+
+	addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+    }
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+   /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *)(info->start[sect]);
+			FPW status;
+
+	printf("Erasing sector %2d ... ", sect);
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+			*addr = (FPW)0x00500050;	/* clear status register */
+			*addr = (FPW)0x00200020;	/* erase setup */
+			*addr = (FPW)0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW)0x00B000B0; /* suspend erase	  */
+					*addr = (FPW)0x00FF00FF; /* reset to read mode */
+					rcode = 1;
+					break;
+	}
+    }
+
+			*addr = (FPW)0x00500050; /* clear status register cmd.   */
+			*addr = (FPW)0x00FF00FF; /* resest to read mode          */
+
+			printf (" done\n");
+	}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+	}
+		for (; i<port_width && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+		for (; cnt==0 && i<port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+	}
+
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+	    return (rc);
+	}
+		wp += port_width;
+    }
+
+    /*
+     * handle word aligned part
+     */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i=0; i<port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+	    return (rc);
+	}
+		wp  += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800)
+		{
+	 spin_wheel();
+			count = 0;
+		}
+    }
+
+    if (cnt == 0) {
+		return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+	for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+	--cnt;
+    }
+	for (; i<port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *)dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW)0x00400040;		/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW)0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+    }
+
+	*addr = (FPW)0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline
+spin_wheel(void)
+{
+   static int p=0;
+   static char w[] = "\\/-";
+
+   printf("\010%c", w[p]);
+   (++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/dnp1110/lowlevel_init.S b/board/dnp1110/lowlevel_init.S
new file mode 100755
index 0000000..7730be3
--- /dev/null
+++ b/board/dnp1110/lowlevel_init.S
@@ -0,0 +1,135 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+/* some parameters for the board */
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+#define MDCNFG		0x00
+#define MDCAS00		0x04		/* CAS waveform rotate reg 0       */
+#define MDCAS01		0x08		/* CAS waveform rotate reg 1 bank  */
+#define MDCAS02		0x0C		/* CAS waveform rotate reg 2 bank  */
+#define MDREFR		0x1C		/* DRAM refresh control reg        */
+#define MDCAS20		0x20		/* CAS waveform rotate reg 0 bank  */
+#define MDCAS21		0x24		/* CAS waveform rotate reg 1 bank  */
+#define MDCAS22		0x28		/* CAS waveform rotate reg 2 bank  */
+#define MECR		0x18		/* Expansion memory (PCMCIA) bus configuration  register */
+#define MSC0		0x10		/* static memory control reg 0     */
+#define MSC1		0x14		/* static memory control reg 1     */
+#define MSC2		0x2C		/* static memory control reg 2     */
+#define SMCNFG		0x30		/* SMROM configuration reg         */
+
+mdcas00:	.long	0x5555557F
+mdcas01:	.long	0x55555555
+mdcas02:	.long	0x55555555
+mdcas20:	.long	0x5555557F
+mdcas21:	.long	0x55555555
+mdcas22:	.long	0x55555555
+mdcnfg:		.long	0x0000B25C
+mdrefr:		.long	0x007000C1
+mecr:		.long	0x10841084
+msc0:		.long	0x00004774
+msc1:		.long	0x00000000
+msc2:		.long	0x00000000
+smcnfg:		.long	0x00000000
+
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	ldr	r0, MEM_BASE
+
+	/* Set up the DRAM */
+
+	/* MDCAS00 */
+	ldr	r1, mdcas00
+	str	r1, [r0, #MDCAS00]
+
+	/* MDCAS01 */
+	ldr	r1, mdcas01
+	str	r1, [r0, #MDCAS01]
+
+	/* MDCAS02 */
+	ldr	r1, mdcas02
+	str	r1, [r0, #MDCAS02]
+
+	/* MDCAS20 */
+	ldr	r1, mdcas20
+	str	r1, [r0, #MDCAS20]
+
+	/* MDCAS21 */
+	ldr	r1, mdcas21
+	str	r1, [r0, #MDCAS21]
+
+	/* MDCAS22 */
+	ldr	r1, mdcas22
+	str	r1, [r0, #MDCAS22]
+
+	/* MDREFR */
+	ldr	r1, mdrefr
+	str	r1, [r0, #MDREFR]
+
+	/* Set up PCMCIA space */
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+
+	/* Setup the flash memory and other */
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+
+	ldr	r1, msc1
+	str	r1, [r0, #MSC1]
+
+	ldr	r1, msc2
+	str	r1, [r0, #MSC2]
+
+	ldr	r1, smcnfg
+	str	r1, [r0, #SMCNFG]
+
+	/* MDCNFG */
+	ldr	r1, mdcnfg
+	bic	r1, r1, #0x00000001
+	str	r1, [r0, #MDCNFG]
+
+	/* Load something to activate bank */
+	ldr	r2, MEM_START
+.rept	8
+	ldr	r1, [r2]
+.endr
+
+	/* MDCNFG */
+	ldr	r1, mdcnfg
+	orr	r1, r1, #0x00000001
+	str	r1, [r0, #MDCNFG]
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/board/dnp1110/u-boot.lds b/board/dnp1110/u-boot.lds
new file mode 100755
index 0000000..258bece
--- /dev/null
+++ b/board/dnp1110/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/sa1100/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/eXalion/Makefile b/board/eXalion/Makefile
new file mode 100755
index 0000000..cfbf465
--- /dev/null
+++ b/board/eXalion/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+SOBJS	=
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/eXalion/config.mk b/board/eXalion/config.mk
new file mode 100755
index 0000000..b3f65eb
--- /dev/null
+++ b/board/eXalion/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Sandpoint boards
+#
+
+#TEXT_BASE = 0x00090000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c
new file mode 100755
index 0000000..2e3f519
--- /dev/null
+++ b/board/eXalion/eXalion.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <ide.h>
+#include "piix_pci.h"
+#include "eXalion.h"
+
+int checkboard (void)
+{
+	ulong busfreq = get_bus_freq (0);
+	char buf[32];
+
+	printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
+	printf ("Built: %s at %s\n", __DATE__, __TIME__);
+	printf ("Local Bus:  %s MHz\n", strmhz (buf, busfreq));
+
+	return 0;
+}
+
+int checkflash (void)
+{
+	printf ("checkflash\n");
+	flash_init ();
+	return (0);
+}
+
+long int initdram (int board_type)
+{
+	int i, cnt;
+	volatile uchar *base = CFG_SDRAM_BASE;
+	volatile ulong *addr;
+	ulong save[32];
+	ulong val, ret = 0;
+
+	for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
+	     cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *) base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if (*addr != 0) {
+		*addr = save[i];
+		goto Done;
+	}
+
+	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			ulong new_bank0_end = cnt * sizeof (long) - 1;
+			ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
+			ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
+
+			mear1 = (mear1 & 0xFFFFFF00) |
+				((new_bank0_end & MICR_ADDR_MASK) >>
+				 MICR_ADDR_SHIFT);
+			emear1 = (emear1 & 0xFFFFFF00) |
+				((new_bank0_end & MICR_ADDR_MASK) >>
+				 MICR_EADDR_SHIFT);
+			mpc824x_mpc107_setreg (MEAR1, mear1);
+			mpc824x_mpc107_setreg (EMEAR1, emear1);
+
+			ret = cnt * sizeof (long);
+			goto Done;
+		}
+	}
+
+	ret = CFG_MAX_RAM_SIZE;
+      Done:
+	return ret;
+}
+
+int misc_init_r (void)
+{
+	pci_dev_t bdf;
+	u32 val32;
+	u8 val8;
+
+	puts ("ISA:   ");
+	bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0);
+	if (bdf == -1) {
+		puts ("Unable to find PIIX4 ISA bridge !\n");
+		hang ();
+	}
+
+	/* set device for normal ISA instead EIO */
+	pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32);
+	val32 |= 0x00000001;
+	pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32);
+	printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf),
+		PCI_DEV (bdf), PCI_FUNC (bdf));
+
+	puts ("ISA:   ");
+	bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0);
+	if (bdf == -1) {
+		puts ("Unable to find PIIX4 IDE controller !\n");
+		hang ();
+	}
+
+	/* Init BMIBA register  */
+	/* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */
+	/* val32 |= 0x1000; */
+	/* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */
+
+	/* Enable BUS master and IO access  */
+	val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+	pci_write_config_dword (bdf, PCI_COMMAND, val32);
+
+	/* Set latency  */
+	pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8);
+	val8 = 0x40;
+	pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8);
+
+	/* Enable Primary ATA/IDE  */
+	pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32);
+	/* val32 = 0xa307a307; */
+	val32 = 0x00008000;
+	pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32);
+
+
+	printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf),
+		PCI_DEV (bdf), PCI_FUNC (bdf));
+
+	/* Try to get FAT working... */
+	/* fat_register_read(ide_read); */
+
+
+	return (0);
+}
+
+/*
+ * Show/Init PCI devices on the specified bus number.
+ */
+
+void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char line;
+
+	switch (PCI_DEV (dev)) {
+	case 16:
+		line = PCI_INT_A;
+		break;
+	case 17:
+		line = PCI_INT_B;
+		break;
+	case 18:
+		line = PCI_INT_C;
+		break;
+	case 19:
+		line = PCI_INT_D;
+		break;
+#if defined (CONFIG_MPC8245)
+	case 20:
+		line = PCI_INT_A;
+		break;
+	case 21:
+		line = PCI_INT_B;
+		break;
+	case 22:
+		line = PCI_INT_NA;
+		break;
+#endif
+	default:
+		line = PCI_INT_A;
+		break;
+	}
+	pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line);
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+#if defined (CONFIG_MPC8240)
+static struct pci_config_table pci_eXalion_config_table[] = {
+	{
+	 /* Intel 82559ER ethernet controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 PCI to ISA bridge */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 IDE controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{}
+};
+#elif defined (CONFIG_MPC8245)
+static struct pci_config_table pci_eXalion_config_table[] = {
+	{
+	 /* Intel 82559ER ethernet controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82559ER ethernet controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET1_IOADDR,
+				     PCI_ENET1_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Broadcom BCM5690 Gigabit switch */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET2_IOADDR,
+				     PCI_ENET2_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Broadcom BCM5690 Gigabit switch */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00,
+	 pci_cfgfunc_config_device, {PCI_ENET3_IOADDR,
+				     PCI_ENET3_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 PCI to ISA bridge */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{
+	 /* Intel 82371AB PIIX4 IDE controller */
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01,
+	 pci_cfgfunc_config_device, {0,
+				     0,
+				     PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
+	{}
+};
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#endif /* #ifndef CONFIG_PCI_PNP */
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_eXalion_config_table,
+	fixup_irq:pci_eXalion_fixup_irq,
+#endif
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init (&hose);
+}
diff --git a/board/eXalion/eXalion.h b/board/eXalion/eXalion.h
new file mode 100755
index 0000000..8dccabb
--- /dev/null
+++ b/board/eXalion/eXalion.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * James Dougherty (jfd@broadcom.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EXALION_H
+#define __EXALION_H
+
+/* IRQ settings */
+#define  PCI_INT_NA (0xff)   /* PCI Intr. not used */
+#define  PCI_INT_A  (0x09)   /* PCI Intr. A Interrupt Request Line Nr. */
+#define  PCI_INT_B  (0x0a)   /* PCI Intr. B Interrupt Request Line Nr. */
+#define  PCI_INT_C  (0x0b)   /* PCI Intr. C Interrupt Request Line Nr. */
+#define  PCI_INT_D  (0x0c)   /* PCI Intr. D Interrupt Request Line Nr. */
+#if defined (CPU_MPC8245)
+#define  LN_1_INT     PCI_INT_B  /* ethernet interrupt level */
+#define  LN_2_INT     PCI_INT_C  /* ethernet interrupt level */
+#define  BCM_1_INT    PCI_INT_A  /* BCM5690 interrupt level */
+#define  BCM_2_INT    PCI_INT_B  /* BCM5690 interrupt level */
+#elif defined (CPU_MPC8240)
+#define  BCM_INT      PCI_INT_B  /* BCM5600 interrupt level */
+#define  LN_INT       PCI_INT_C  /* ethernet interrupt level */
+#endif
+
+#ifndef __ASSEMBLY__
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __EXALION_H */
diff --git a/board/eXalion/piix_pci.h b/board/eXalion/piix_pci.h
new file mode 100755
index 0000000..b3c9c16
--- /dev/null
+++ b/board/eXalion/piix_pci.h
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PIIX4_PCI_H
+#define _PIIX4_PCI_H
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#define PIIX4_VENDOR_ID         0x8086
+#define PIIX4_ISA_DEV_ID        0x7110
+#define PIIX4_IDE_DEV_ID        0x7111
+
+/* Function 0 ISA Bridge */
+#define PCI_CFG_PIIX4_IORT      0x4C    /* 8 bit ISA Recovery Timer Reg (default 0x4D) */
+#define PCI_CFG_PIIX4_XBCS      0x4E    /* 16 bit XBus Chip select reg (default 0x0003) */
+#define PCI_CFG_PIIX4_PIRQC     0x60    /* PCI IRQ Route Register 4 x 8bit (default )*/
+#define PCI_CFG_PIIX4_SERIRQ    0x64
+#define PCI_CFG_PIIX4_TOM       0x69
+#define PCI_CFG_PIIX4_MSTAT     0x6A
+#define PCI_CFG_PIIX4_MBDMA     0x76
+#define PCI_CFG_PIIX4_APICBS    0x80
+#define PCI_CFG_PIIX4_DLC       0x82
+#define PCI_CFG_PIIX4_PDMACFG   0x90
+#define PCI_CFG_PIIX4_DDMABS    0x92
+#define PCI_CFG_PIIX4_GENCFG    0xB0
+#define PCI_CFG_PIIX4_RTCCFG    0xCB
+
+/* IO Addresses */
+#define PIIX4_ISA_DMA1_CH0BA    0x00
+#define PIIX4_ISA_DMA1_CH0CA    0x01
+#define PIIX4_ISA_DMA1_CH1BA    0x02
+#define PIIX4_ISA_DMA1_CH1CA    0x03
+#define PIIX4_ISA_DMA1_CH2BA    0x04
+#define PIIX4_ISA_DMA1_CH2CA    0x05
+#define PIIX4_ISA_DMA1_CH3BA    0x06
+#define PIIX4_ISA_DMA1_CH3CA    0x07
+#define PIIX4_ISA_DMA1_CMDST    0x08
+#define PIIX4_ISA_DMA1_REQ      0x09
+#define PIIX4_ISA_DMA1_WSBM     0x0A
+#define PIIX4_ISA_DMA1_CH_MOD   0x0B
+#define PIIX4_ISA_DMA1_CLR_PT   0x0C
+#define PIIX4_ISA_DMA1_M_CLR    0x0D
+#define PIIX4_ISA_DMA1_CLR_M    0x0E
+#define PIIX4_ISA_DMA1_RWAMB    0x0F
+
+#define PIIX4_ISA_DMA2_CH0BA    0xC0
+#define PIIX4_ISA_DMA2_CH0CA    0xC1
+#define PIIX4_ISA_DMA2_CH1BA    0xC2
+#define PIIX4_ISA_DMA2_CH1CA    0xC3
+#define PIIX4_ISA_DMA2_CH2BA    0xC4
+#define PIIX4_ISA_DMA2_CH2CA    0xC5
+#define PIIX4_ISA_DMA2_CH3BA    0xC6
+#define PIIX4_ISA_DMA2_CH3CA    0xC7
+#define PIIX4_ISA_DMA2_CMDST    0xD0
+#define PIIX4_ISA_DMA2_REQ      0xD2
+#define PIIX4_ISA_DMA2_WSBM     0xD4
+#define PIIX4_ISA_DMA2_CH_MOD   0xD6
+#define PIIX4_ISA_DMA2_CLR_PT   0xD8
+#define PIIX4_ISA_DMA2_M_CLR    0xDA
+#define PIIX4_ISA_DMA2_CLR_M    0xDC
+#define PIIX4_ISA_DMA2_RWAMB    0xDE
+
+#define PIIX4_ISA_INT1_ICW1     0x20
+#define PIIX4_ISA_INT1_OCW2     0x20
+#define PIIX4_ISA_INT1_OCW3     0x20
+#define PIIX4_ISA_INT1_ICW2     0x21
+#define PIIX4_ISA_INT1_ICW3     0x21
+#define PIIX4_ISA_INT1_ICW4     0x21
+#define PIIX4_ISA_INT1_OCW1     0x21
+
+#define PIIX4_ISA_INT1_ELCR     0x4D0
+
+#define PIIX4_ISA_INT2_ICW1     0xA0
+#define PIIX4_ISA_INT2_OCW2     0xA0
+#define PIIX4_ISA_INT2_OCW3     0xA0
+#define PIIX4_ISA_INT2_ICW2     0xA1
+#define PIIX4_ISA_INT2_ICW3     0xA1
+#define PIIX4_ISA_INT2_ICW4     0xA1
+#define PIIX4_ISA_INT2_OCW1     0xA1
+#define PIIX4_ISA_INT2_IMR      0xA1 /* read only */
+
+#define PIIX4_ISA_INT2_ELCR     0x4D1
+
+#define PIIX4_ISA_TMR0_CNT_ST   0x40
+#define PIIX4_ISA_TMR1_CNT_ST   0x41
+#define PIIX4_ISA_TMR2_CNT_ST   0x42
+#define PIIX4_ISA_TMR_TCW       0x43
+
+#define PIIX4_ISA_RST_XBUS      0x60
+
+#define PIIX4_ISA_NMI_CNT_ST    0x61
+#define PIIX4_ISA_NMI_ENABLE    0x70
+
+#define PIIX4_ISA_RTC_INDEX     0x70
+#define PIIX4_ISA_RTC_DATA      0x71
+#define PIIX4_ISA_RTCEXT_IND    0x70
+#define PIIX4_ISA_RTCEXT_DATA   0x71
+
+#define PIIX4_ISA_DMA1_CH2LPG   0x81
+#define PIIX4_ISA_DMA1_CH3LPG   0x82
+#define PIIX4_ISA_DMA1_CH1LPG   0x83
+#define PIIX4_ISA_DMA1_CH0LPG   0x87
+#define PIIX4_ISA_DMA2_CH2LPG   0x89
+#define PIIX4_ISA_DMA2_CH3LPG   0x8A
+#define PIIX4_ISA_DMA2_CH1LPG   0x8B
+#define PIIX4_ISA_DMA2_LPGRFR   0x8F
+
+#define PIIX4_ISA_PORT_92       0x92
+
+#define PIIX4_ISA_APM_CONTRL    0xB2
+#define PIIX4_ISA_APM_STATUS    0xB3
+
+#define PIIX4_ISA_COCPU_ERROR   0xF0
+
+/* Function 1 IDE Controller */
+#define PCI_CFG_PIIX4_BMIBA     0x20
+#define PCI_CFG_PIIX4_IDETIM    0x40
+#define PCI_CFG_PIIX4_SIDETIM   0x44
+#define PCI_CFG_PIIX4_UDMACTL   0x48
+#define PCI_CFG_PIIX4_UDMATIM   0x4A
+
+/* Function 2 USB Controller */
+#define PCI_CFG_PIIX4_SBRNUM    0x60
+#define PCI_CFG_PIIX4_LEGSUP    0xC0
+
+/* Function 3 Power Management */
+#define PCI_CFG_PIIX4_PMAB      0x40
+#define PCI_CFG_PIIX4_CNTA      0x44
+#define PCI_CFG_PIIX4_CNTB      0x48
+#define PCI_CFG_PIIX4_GPICTL    0x4C
+#define PCI_CFG_PIIX4_DEVRESD   0x50
+#define PCI_CFG_PIIX4_DEVACTA   0x54
+#define PCI_CFG_PIIX4_DEVACTB   0x58
+#define PCI_CFG_PIIX4_DEVRESA   0x5C
+#define PCI_CFG_PIIX4_DEVRESB   0x60
+#define PCI_CFG_PIIX4_DEVRESC   0x64
+#define PCI_CFG_PIIX4_DEVRESE   0x68
+#define PCI_CFG_PIIX4_DEVRESF   0x6C
+#define PCI_CFG_PIIX4_DEVRESG   0x70
+#define PCI_CFG_PIIX4_DEVRESH   0x74
+#define PCI_CFG_PIIX4_DEVRESI   0x78
+#define PCI_CFG_PIIX4_PMMISC    0x80
+#define PCI_CFG_PIIX4_SMBBA     0x90
+
+
+#endif  /* _PIIX4_PCI_H */
diff --git a/board/eXalion/u-boot.lds b/board/eXalion/u-boot.lds
new file mode 100755
index 0000000..eaee3fd
--- /dev/null
+++ b/board/eXalion/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/eltec/bab7xx/Makefile b/board/eltec/bab7xx/Makefile
new file mode 100755
index 0000000..7d8ed26
--- /dev/null
+++ b/board/eltec/bab7xx/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o
+
+SOBJS	= asm_init.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/eltec/bab7xx/asm_init.S b/board/eltec/bab7xx/asm_init.S
new file mode 100755
index 0000000..2a9b33e
--- /dev/null
+++ b/board/eltec/bab7xx/asm_init.S
@@ -0,0 +1,1476 @@
+/*
+ * (C) Copyright 2001 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * ELTEC BAB PPC RAM initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/processor.h>
+#include <74xx_7xx.h>
+#include <mpc106.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+/*
+ * This following contains the entry code for the initialization code
+ * for the MPC 106, a PCI Bridge/Memory Controller.
+ * Register usage:
+ * r0  = ramtest scratch register, toggleError loop counter
+ * r1  = 0xfec0 0cf8 CONFIG_ADDRESS
+ * r2  = 0xfee0 0cfc CONFIG_DATA
+ * r3  = scratch register, subroutine argument and return value, ramtest size
+ * r4  = scratch register, spdRead clock mask, OutHex loop count
+ * r5  = ramtest scratch register
+ * r6  = toggleError 1st value, spdRead port mask
+ * r7  = toggleError 2nd value, ramtest scratch register,
+ *       spdRead scratch register (0x00)
+ * r8  = ramtest scratch register, spdRead scratch register (0x80)
+ * r9  = ramtest scratch register, toggleError loop end, OutHex digit
+ * r10 = ramtest scratch register, spdWriteByte parameter,
+ *        spdReadByte return value, printf pointer to COM1
+ * r11 = startType
+ * r12 = ramtest scratch register, spdRead data mask
+ * r13 = pointer to message block
+ * r14 = pointer to GOT
+ * r15 = scratch register, SPD save
+ * r16 = bank0 size, total memory size
+ * r17 = bank1 size
+ * r18 = bank2 size
+ * r19 = bank3 size
+ * r20 = MCCR1, MSAR1
+ * r21 = MCCR3, MEAR1
+ * r22 = MCCR4, MBER
+ * r23 = EMSAR1
+ * r24 = EMEAR1
+ * r25 = save link register 1st level
+ * r26 = save link register 2nd level
+ * r27 = save link register 3rd level
+ * r30 = pointer to GPIO for spdRead
+ */
+
+
+.globl board_asm_init
+board_asm_init:
+/*
+ * setup pointer to message block
+ */
+    mflr    r25             /* save away link register */
+    bl      get_lnk_reg     /* r3=addr of next instruction */
+    subi    r4, r3, 8       /* r4=board_asm_init addr */
+    addi    r13, r4, (MessageBlock-board_asm_init)
+/*
+ * dcache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, HID0_DCE
+    andc    r3, r3, r4
+    mr      r2, r3
+    ori     r3, r3, HID0_DCI
+    sync
+    mtspr   HID0, r3
+    mtspr   HID0, r2
+    isync
+    sync
+/*
+ * icache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, 0
+    ori     r4, r4, HID0_ICE
+    andc    r3, r3, r4
+    sync
+    mtspr   HID0, r3
+/*
+ * invalidate caches
+ */
+    ori     r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE)
+    or      r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    andc    r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    isync
+/*
+ * icache_enable
+ */
+    mfspr   r3, HID0
+    ori     r3, r3, (HID0_ICE | HID0_ICFI)
+    sync
+    mtspr   HID0, r3
+
+    lis     r1, 0xfec0
+    ori     r1, r1, 0x0cf8
+    lis     r2, 0xfee0
+    ori     r2, r2, 0xcfc
+
+#ifdef CFG_ADDRESS_MAP_A
+/*
+ * Switch to address map A if necessary.
+ */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, PCI_PICR1
+    stwbrx  r3, 0, r1
+    sync
+    lwbrx   r4, 0, r2
+    sync
+    lis     r0, PICR1_XIO_MODE@h
+    ori     r0, r0, PICR1_XIO_MODE@l
+    andc    r4, r4, r0
+    lis     r0, PICR1_ADDRESS_MAP@h
+    ori     r0, r0, PICR1_ADDRESS_MAP@l
+    or      r4, r4, r0
+    stwbrx  r4, 0, r2
+    sync
+#endif
+
+/*
+ * Do the init for the SIO.
+ */
+    bl      .sioInit
+
+    addi    r3, r13, (MinitLogo-MessageBlock)
+    bl      Printf
+
+    addi    r3, r13, (Mspd01-MessageBlock)
+    bl      Printf
+/*
+ * Memory cofiguration using SPD information stored on the SODIMMs
+ */
+    li      r17, 0
+    li      r18, 0
+    li      r19, 0
+
+    li      r3, 0x0002          /* get RAM type from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    bne     noSpdError
+
+    addi    r3, r13, (Mfail-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x00
+    b       toggleError         /* fail - loop forever */
+
+noSpdError:
+    mr      r15, r3             /* save r3 */
+
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+
+    cmpli   0, 0, r15, 0x0001   /* FPM ? */
+    beq     configFPM
+    cmpli   0, 0, r15, 0x0002   /* EDO ? */
+    beq     configEDO
+    cmpli   0, 0, r15, 0x0004   /* SDRAM ? */
+    beq     configSDRAM
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x01
+    b       toggleError         /* fail - loop forever */
+
+configSDRAM:
+    addi    r3, r13, (MsdRam-MessageBlock)
+    bl      Printf
+/*
+ * set the Memory Configuration Reg. 1
+ */
+    li      r3, 0x001f          /* get bank size from spd bank0/1 */
+    bl      spdRead
+
+    andi.   r3, r3, 0x0038
+    beq     SD16MB2B
+
+    li      r3, 0x0011          /* get number of internal banks */
+				/* from spd for bank0/1 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x02
+    beq     SD64MB2B
+
+    cmpli   0, 0, r3, 0x04
+    beq     SD64MB4B
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x02
+    b       toggleError         /* fail - loop forever */
+
+SD64MB2B:
+    li      r20, 0x0005         /* 64-Mbit SDRAM 2 banks */
+    b       SDRow2nd
+
+SD64MB4B:
+    li      r20, 0x0000         /* 64-Mbit SDRAM 4 banks */
+    b       SDRow2nd
+
+SD16MB2B:
+    li      r20, 0x000f         /* 16-Mbit SDRAM 2 banks */
+
+SDRow2nd:
+    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x0004
+    bne     S2D64MB4B           /* bank2/3 isn't present or no SDRAM */
+
+    li      r3, 0x011f          /* get bank size from spd bank2/3 */
+    bl      spdRead
+
+    andi.   r3, r3, 0x0038
+    beq     S2D16MB2B
+/*
+ * set the Memory Configuration Reg. 2
+ */
+    li      r3, 0x0111          /* get number of internal banks */
+				/* from spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x02
+    beq     S2D64MB2B
+
+    cmpli   0, 0, r3, 0x04
+    beq     S2D64MB4B
+
+    li      r6, 0xe0            /* error codes in r6 and r7 */
+    li      r7, 0x03
+    b       toggleError         /* fail - loop forever */
+
+S2D64MB2B:
+    ori     r20, r20, 0x0050    /* 64-Mbit SDRAM 2 banks */
+    b       S2D64MB4B
+
+S2D16MB2B:
+    ori     r20, r20, 0x00f0    /* 16-Mbit SDRAM 2 banks */
+
+/*
+ * set the Memory Configuration Reg. 3
+ */
+S2D64MB4B:
+    lis     r21, 0x8630         /* BSTOPRE = 0x80, REFREC = 6, */
+				/* RDLAT = 3 */
+
+/*
+ * set the Memory Configuration Reg. 4
+ */
+    lis     r22, 0x2430         /* PRETOACT = 2, ACTOPRE = 4, */
+				/* WCBUF = 1, RCBUF = 1 */
+    ori     r22, r22, 0x2220    /* SDMODE = 0x022, ACTORW = 2 */
+
+/*
+ * get the size of bank 0-3
+ */
+    li      r3, 0x001f          /* get bank size from spd bank0/1 */
+    bl      spdRead
+
+    rlwinm  r16, r3, 2, 24, 29  /* calculate size in MByte */
+				/* (128 MB max.) */
+
+    li      r3, 0x0005          /* get number of banks from spd */
+				/* for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     SDRAMnobank1
+
+    mr      r17, r16
+
+SDRAMnobank1:
+    addi    r3, r13, (Mspd23-MessageBlock)
+    bl      Printf
+
+    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x0001    /* FPM ? */
+    bne     noFPM23             /* handle as EDO */
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MfpmRam-MessageBlock)
+    bl      Printf
+    b       configRAMcommon
+noFPM23:
+    cmpli   0, 0, r3, 0x0002    /* EDO ? */
+    bne     noEDO23
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MedoRam-MessageBlock)
+    bl      Printf
+    b       configRAMcommon
+noEDO23:
+    cmpli   0, 0, r3, 0x0004    /* SDRAM ? */
+    bne    noSDRAM23
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MsdRam-MessageBlock)
+    bl      Printf
+    b       configSDRAM23
+noSDRAM23:
+    addi    r3, r13, (Mna-MessageBlock)
+    bl      Printf
+    b       configRAMcommon     /* bank2/3 isn't present or no SDRAM */
+
+configSDRAM23:
+    li      r3, 0x011f          /* get bank size from spd bank2/3 */
+    bl      spdRead
+
+    rlwinm  r18, r3, 2, 24, 29  /* calculate size in MByte */
+				/* (128 MB max.) */
+
+    li      r3, 0x0105          /* get number of banks from */
+				/* spd bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     SDRAMnobank3
+
+    mr    r19, r18
+
+SDRAMnobank3:
+    b       configRAMcommon
+
+configFPM:
+    addi    r3, r13, (MfpmRam-MessageBlock)
+    bl      Printf
+    b       configEDO0
+/*
+ * set the Memory Configuration Reg. 1
+ */
+configEDO:
+    addi    r3, r13, (MedoRam-MessageBlock)
+    bl      Printf
+configEDO0:
+    lis     r20, MCCR1_TYPE_EDO@h
+
+getSpdRowBank01:
+    li      r3, 0x0003          /* get number of row bits from */
+				/* spd from bank0/1 */
+    bl      spdRead
+    ori     r20, r20, (MCCR1_BK0_9BITS | MCCR1_BK1_9BITS)
+    cmpli   0, 0, r3, 0x0009    /* bank0 -  9 row bits */
+    beq     getSpdRowBank23
+
+    ori     r20, r20, (MCCR1_BK0_10BITS | MCCR1_BK1_10BITS)
+    cmpli   0, 0, r3, 0x000a    /* bank0 -  10 row bits */
+    beq     getSpdRowBank23
+
+    ori     r20, r20, (MCCR1_BK0_11BITS | MCCR1_BK1_11BITS)
+    cmpli   0, 0, r3, 0x000b    /* bank0 -  11 row bits */
+    beq     getSpdRowBank23
+
+    ori     r20, r20, (MCCR1_BK0_12BITS | MCCR1_BK1_12BITS)
+    cmpli   0, 0, r3, 0x000c    /* bank0 -  12 row bits */
+    beq     getSpdRowBank23
+
+    cmpli   0, 0, r3, 0x000d    /* bank0 -  13 row bits */
+    beq     getSpdRowBank23
+
+    li      r6, 0xe0            /* error codes in r6 and r7 */
+    li      r7, 0x10
+    b       toggleError         /* fail - loop forever */
+
+getSpdRowBank23:
+    li     r3, 0x0103           /* get number of row bits from */
+				/* spd for bank2/3 */
+    bl      spdRead
+
+    ori     r20, r20, (MCCR1_BK2_9BITS | MCCR1_BK3_9BITS)
+    cmpli   0, 0, r3, 0x0009    /* bank0 -  9 row bits */
+    beq     writeRowBits
+
+    ori     r20, r20, (MCCR1_BK2_10BITS | MCCR1_BK3_10BITS)
+    cmpli   0, 0, r3, 0x000a    /* bank0 -  10 row bits */
+    beq     writeRowBits
+
+    ori     r20, r20, (MCCR1_BK2_11BITS | MCCR1_BK3_11BITS)
+    cmpli   0, 0, r3, 0x000b    /* bank0 -  11 row bits */
+    beq     writeRowBits
+
+    ori     r20, r20, (MCCR1_BK2_12BITS | MCCR1_BK3_12BITS)
+
+/*
+ * set the Memory Configuration Reg. 3
+ */
+writeRowBits:
+    lis     r21, 0x000a         /* CPX = 1, RAS6P = 4 */
+    ori     r21, r21, 0x2293    /* CAS5 = 2, CP4 = 1, */
+				/* CAS3 = 2, RCD2 = 2, RP = 3 */
+/*
+ * set the Memory Configuration Reg. 4
+ */
+    lis     r22, 0x0010         /* all SDRAM parameter 0, */
+				/* WCBUF flow through, */
+				/* RCBUF registered */
+/*
+ * get the size of bank 0-3
+ */
+    li      r3, 0x0003          /* get row bits from spd  bank0/1 */
+    bl      spdRead
+
+    li      r16, 0              /* bank size is: */
+				/* (8*2^row*2^column)/0x100000 MB */
+    ori     r16, r16, 0x8000
+    rlwnm   r16, r16, r3, 0, 31
+
+    li      r3, 0x0004          /* get column bits from spd bank0/1 */
+    bl      spdRead
+
+    rlwnm   r16, r16, r3, 0, 31
+
+    li      r3, 0x0005          /* get number of banks from */
+				/* spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     EDOnobank1
+
+    mr      r17, r16
+
+EDOnobank1:
+    addi    r3, r13, (Mspd23-MessageBlock)
+    bl      Printf
+
+    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x0001    /* FPM ? */
+    bne     noFPM231            /* handle as EDO */
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MfpmRam-MessageBlock)
+    bl      Printf
+    b       EDObank2
+noFPM231:
+    cmpli   0, 0, r3, 0x0002    /* EDO ? */
+    bne     noEDO231
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MedoRam-MessageBlock)
+    bl      Printf
+    b       EDObank2
+noEDO231:
+    cmpli   0, 0, r3, 0x0004    /* SDRAM ? */
+    bne     noSDRAM231
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+    addi    r3, r13, (MsdRam-MessageBlock)
+    bl      Printf
+    b       configRAMcommon
+noSDRAM231:
+    addi    r3, r13, (Mfail-MessageBlock)
+    bl      Printf
+    b       configRAMcommon     /* bank2/3 isn't present or no SDRAM */
+
+EDObank2:
+    li      r3, 0x0103          /* get row bits from spd for bank2/3 */
+    bl      spdRead
+
+    li      r18, 0              /* bank size is: */
+				/* (8*2^row*2^column)/0x100000 MB */
+    ori     r18, r18, 0x8000
+    rlwnm   r18, r18, r3, 0, 31
+
+    li      r3, 0x0104          /* get column bits from spd bank2/3 */
+    bl      spdRead
+
+    rlwnm   r18, r18, r3, 0, 31
+
+    li      r3, 0x0105          /* get number of banks from */
+				/* spd for bank2/3 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     configRAMcommon
+
+    mr      r19, r18
+
+configRAMcommon:
+    lis     r1, MPC106_REG_ADDR@h
+    ori     r1, r1, MPC106_REG_ADDR@l
+    lis     r2, MPC106_REG_DATA@h
+    ori     r2, r2, MPC106_REG_DATA@l
+
+    li      r0, 0
+
+/*
+ * If we are already running in RAM (debug mode), we should
+ * NOT reset the MEMGO flag. Otherwise we will stop all memory
+ * accesses.
+ */
+#ifdef IN_RAM
+    lis     r4, MCCR1_MEMGO@h
+    ori     r4, r4, MCCR1_MEMGO@l
+    or      r20, r20, r4
+#endif
+
+/*
+ * set the Memory Configuration Reg. 1
+ */
+    lis     r3, MPC106_REG@h        /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR1    /* register number 0xf0 */
+    stwbrx  r3, r0, r1              /* write this value to CONFIG_ADDR */
+    eieio                           /* make sure mem. access is complete */
+    stwbrx  r20, r0, r2             /* write data to CONFIG_DATA */
+/*
+ * set the Memory Configuration Reg. 3
+ */
+    lis     r3, MPC106_REG@h        /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR3    /* register number 0xf8 */
+    stwbrx  r3, r0, r1              /* write this value to CONFIG_ADDR */
+    eieio                           /* make sure mem. access is complete */
+    stwbrx    r21, r0, r2           /* write data to CONFIG_DATA */
+/*
+ * set the Memory Configuration Reg. 4
+ */
+    lis     r3, MPC106_REG@h        /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR4    /* register number 0xfc */
+    stwbrx  r3, r0, r1              /* write this value to CONFIG_ADDR */
+    eieio                           /* make sure mem. access is complete */
+    stwbrx  r22, r0, r2             /* write data to CONFIG_DATA */
+/*
+ * set the memory boundary registers for bank 0-3
+ */
+    li      r20, 0
+    li      r23, 0
+    li      r24, 0
+    subi    r21, r16, 1         /* calculate end address bank0 */
+    li      r22, (MBER_BANK0)
+
+    cmpi    0, 0, r17, 0        /* bank1 present ? */
+    beq     nobank1
+
+    rlwinm  r3, r16, 8, 16, 23  /* calculate start address of bank1 */
+    or      r20, r20, r3
+    add     r16, r16, r17       /* add to total memory size */
+    subi    r3, r16, 1          /* calculate end address of bank1 */
+    rlwinm  r3, r3, 8, 16, 23
+    or      r21, r21, r3
+    ori     r22, r22, (MBER_BANK1)      /* enable bank1 */
+    b       bank2
+
+nobank1:
+    ori     r23, r23, 0x0300    /* set bank1 start to unused area */
+    ori     r24, r24, 0x0300    /* set bank1 end to unused area */
+
+bank2:
+    cmpi    0, 0, r18, 0        /* bank2 present ? */
+    beq     nobank2
+
+    andi.   r3, r16, 0x00ff     /* calculate start address of bank2 */
+    andi.   r4, r16, 0x0300
+    rlwinm  r3, r3, 16, 8, 15
+    or      r20, r20, r3
+    rlwinm  r3, r4, 8, 8, 15
+    or      r23, r23, r3
+    add     r16, r16, r18       /* add to total memory size */
+    subi    r3, r16, 1          /* calculate end address of bank2 */
+    andi.   r4, r3, 0x0300
+    andi.   r3, r3, 0x00ff
+    rlwinm  r3, r3, 16, 8, 15
+    or      r21, r21, r3
+    rlwinm  r3, r4, 8, 8, 15
+    or      r24, r24, r3
+    ori     r22, r22, (MBER_BANK2)    /* enable bank2 */
+    b       bank3
+
+nobank2:
+    lis     r3, 0x0003
+    or      r23, r23, r3        /* set bank2 start to unused area */
+    or      r24, r24, r3        /* set bank2 end to unused area */
+
+bank3:
+    cmpi    0, 0, r19, 0        /* bank3 present ? */
+    beq     nobank3
+
+    andi.   r3, r16, 0x00ff     /* calculate start address of bank3 */
+    andi.   r4, r16, 0x0300
+    rlwinm  r3, r3, 24, 0, 7
+    or      r20, r20, r3
+    rlwinm  r3, r4, 16, 0, 7
+    or      r23, r23, r3
+    add     r16, r16, r19       /* add to total memory size */
+    subi    r3, r16, 1          /* calculate end address of bank3 */
+    andi.   r4, r3, 0x0300
+    andi.   r3, r3, 0x00ff
+    rlwinm  r3, r3, 24, 0, 7
+    or      r21, r21, r3
+    rlwinm  r3, r4, 16, 0, 7
+    or      r24, r24, r3
+    ori     r22, r22, (MBER_BANK3)    /* enable bank3 */
+    b       writebound
+
+nobank3:
+    lis     r3, 0x0300
+    or      r23, r23, r3        /* set bank3 start to unused area */
+    or      r24, r24, r3        /* set bank3 end to unused area */
+
+writebound:
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MSAR1    /* register number 0x80 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r20, r0, r2         /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MEAR1    /* register number 0x90 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r21, r0, r2         /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMSAR1    /* register number 0x88 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r23, r0, r2         /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMEAR1    /* register number 0x98 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r24, r0, r2         /* write data to CONFIG_DATA */
+
+/*
+ * set boundaries of unused banks to unused address space
+ */
+    lis     r4, 0x0303
+    ori     r4, r4, 0x0303      /* bank 4-7 start and end adresses */
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMSAR2    /* register number 0x8C */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r4, r0, r2          /* write data to CONFIG_DATA */
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_EMEAR2    /* register number 0x9C */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stwbrx  r4, r0, r2          /* write data to CONFIG_DATA */
+
+/*
+ * set the Memory Configuration Reg. 2
+ */
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR2    /* register number 0xf4 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+
+    li      r3, 0x000c          /* get refresh from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    bne     common1
+
+    li      r6, 0xe0            /* error codes in r6 and r7  */
+    li      r7, 0x20
+    b       toggleError         /* fail - loop forever */
+
+common1:
+    andi.   r15, r3, 0x007f     /* mask selfrefresh bit */
+    li      r3, 0x010c          /* get refresh from spd for bank2/3 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    beq     common2
+    andi.   r3, r3, 0x007f      /* mask selfrefresh bit */
+    cmp     0, 0, r3, r15       /* find the lower */
+    blt     common3
+
+common2:
+    mr      r3, r15
+
+common3:
+    li      r4, 0x1010          /* refesh cycle 1028 clocks */
+				/*  left shifted 2 */
+    cmpli   0, 0, r3, 0x0000    /* 15.6 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x0808          /* refesh cycle 514 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0002    /* 7.8 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x2020          /* refesh cycle 2056 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0003    /* 31.3 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x4040          /* refesh cycle 4112 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0004    /* 62.5 us ? */
+    beq     writeRefresh
+
+    li      r4, 0
+    ori     r4, r4, 0x8080      /* refesh cycle 8224 clocks */
+				/* left shifted 2 */
+    cmpli   0, 0, r3, 0x0005    /* 125 us ? */
+    beq     writeRefresh
+
+    li      r6, 0xe0            /* error codes in r6 and r7 */
+    li      r7, 0x21
+    b       toggleError         /* fail - loop forever */
+
+writeRefresh:
+    stwbrx  r4, r0, r2          /* write data to CONFIG_DATA */
+
+/*
+ * DRAM BANKS SHOULD BE ENABLED
+ */
+    addi    r3, r13, (Mactivate-MessageBlock)
+    bl      Printf
+    mr      r3, r16
+    bl      OutDec
+    addi    r3, r13, (Mmbyte-MessageBlock)
+    bl      Printf
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MBER /* register number 0xa0 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+    stb     r22, 0(r2)          /* write data to CONFIG_DATA */
+    li      r8, 0x63            /* PGMAX = 99 */
+    stb     r8, 3(r2)           /* write data to CONFIG_DATA */
+
+/*
+ *  DRAM SHOULD NOW BE CONFIGURED AND ENABLED
+ *  MUST WAIT 200us BEFORE ACCESSING
+ */
+    li      r0, 0x7800
+    mtctr   r0
+
+wait200us:
+    bdnz    wait200us
+
+    lis     r3, MPC106_REG@h    /* start building new reg number */
+    ori     r3, r3, MPC106_MCCR1    /* register number 0xf0 */
+    stwbrx  r3, r0, r1          /* write this value to CONFIG_ADDR */
+    eieio                       /* make sure mem. access is complete */
+
+    lwbrx   r4, r0, r2          /* load r4 from CONFIG_DATA */
+
+    lis     r0, MCCR1_MEMGO@h   /* MEMGO=1 */
+    ori     r0, r0, MCCR1_MEMGO@l
+    or      r4, r4, r0          /* set the MEMGO bit */
+    stwbrx  r4, r0, r2          /* write mdfd data to CONFIG_DATA */
+
+    li      r0, 0x7000
+    mtctr   r0
+
+wait8ref:
+    bdnz    wait8ref
+
+    addi    r3, r13, (Mok-MessageBlock)
+    bl      Printf
+
+    mtlr    r25
+    blr
+
+/*
+ * Infinite loop called in case of an error during RAM initialisation.
+ * error codes in r6 and r7.
+ */
+toggleError:
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError1:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError1
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError2:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError2
+    b       toggleError
+
+
+/******************************************************************************
+ * This function performs a basic initialisation of the superio chip
+ * to enable basic console output and SPD access during RAM initialisation.
+ *
+ * Upon completion, SIO resource registers are mapped as follows:
+ * Resource     Enabled         Address
+ * UART1        Yes             3F8-3FF COM1
+ * UART2        Yes             2F8-2FF COM2
+ * GPIO         Yes             220-227
+ */
+.set    SIO_LUNINDEX, 0x07      /* SIO LUN index register */
+.set    SIO_CNFG1, 0x21         /* SIO configuration #1 register */
+.set    SIO_PCSCI, 0x23         /* SIO PCS configuration index reg */
+.set    SIO_PCSCD, 0x24         /* SIO PCS configuration data reg */
+.set    SIO_ACTIVATE, 0x30      /* SIO activate register */
+.set    SIO_IOBASEHI, 0x60      /* SIO I/O port base address, 15:8 */
+.set    SIO_IOBASELO, 0x61      /* SIO I/O port base address, 7:0 */
+.set    SIO_LUNENABLE, 0x01     /* SIO LUN enable */
+
+.sioInit:
+    mfspr   r7, 8               /* save link register */
+
+.sioInit_87308:
+
+/*
+ * Get base addr of ISA I/O space
+ */
+    lis     r6, CFG_ISA_IO@h
+    ori     r6, r6, CFG_ISA_IO@l
+
+/*
+ * Set offset to base address for config registers.
+ */
+#if defined(CFG_NS87308_BADDR_0x)
+    addi    r4, r0, 0x0279
+#elif defined(CFG_NS87308_BADDR_10)
+    addi    r4, r0, 0x015C
+#elif defined(CFG_NS87308_BADDR_11)
+    addi    r4, r0, 0x002E
+#endif
+    add     r6, r6, r4          /* add offset to base */
+    or      r3, r6, r6          /* make a copy */
+
+/*
+ * PMC (LUN 8)
+ */
+    addi    r4, r0, SIO_LUNINDEX    /* select PMC LUN */
+    addi    r5, r0, 0x8
+    bl      .sio_bw
+    addi    r4, r0, SIO_IOBASEHI    /* initialize PMC address to 0x460 */
+    addi    r5, r0, 0x04
+    bl      .sio_bw
+    addi    r4, r0, SIO_IOBASELO
+    addi    r5, r0, 0x60
+    bl      .sio_bw
+    addi    r4, r0, SIO_ACTIVATE    /* enable PMC */
+    addi    r5, r0, SIO_LUNENABLE
+    bl      .sio_bw
+
+    lis     r8, CFG_ISA_IO@h
+    ori     r8, r8, 0x0460
+    li      r9, 0x03
+    stb     r9, 0(r8)               /* select PMC2 register */
+    eieio
+    li      r9, 0x00
+    stb     r9, 1(r8)               /* SuperI/O clock src: 24MHz via X1 */
+    eieio
+
+/*
+ * map UART1 (LUN 6) or UART2 (LUN 5) to COM1 (0x3F8)
+ */
+    addi    r4, r0, SIO_LUNINDEX    /* select COM1 LUN */
+    addi    r5, r0, 0x6
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASEHI    /* initialize COM1 address to 0x3F8 */
+    addi    r5, r0, 0x03
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASELO
+    addi    r5, r0, 0xF8
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_ACTIVATE    /* enable COM1 */
+    addi    r5, r0, SIO_LUNENABLE
+    bl      .sio_bw
+
+/*
+ * Init COM1 for polled output
+ */
+    lis     r8, CFG_ISA_IO@h
+    ori     r8, r8, 0x03f8
+    li      r9, 0x00
+    stb     r9, 1(r8)           /* int disabled */
+    eieio
+    li      r9, 0x00
+    stb     r9, 4(r8)           /* modem ctrl */
+    eieio
+    li      r9, 0x80
+    stb     r9, 3(r8)           /* link ctrl, bank select */
+    eieio
+    li      r9, 115200/CONFIG_BAUDRATE
+    stb     r9, 0(r8)           /* baud rate (LSB)*/
+    eieio
+    rotrwi  r9, r9, 8
+    stb     r9, 1(r8)           /* baud rate (MSB) */
+    eieio
+    li      r9, 0x03
+    stb     r9, 3(r8)           /* 8 data bits, 1 stop bit, */
+				/* no parity */
+    eieio
+    li      r9, 0x0b
+    stb     r9, 4(r8)           /* enable the receiver and transmitter */
+    eieio
+
+waitEmpty:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty
+    li      r9, 0x47
+    stb     r9, 3(r8)           /* send break, 8 data bits, */
+				/* 2 stop bits, no parity */
+    eieio
+
+    lis     r0, 0x0001
+    mtctr   r0
+
+waitCOM1:
+    lwz     r0, 5(r8)           /* load from port for delay */
+    bdnz    waitCOM1
+
+waitEmpty1:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty1
+    li      r9, 0x07
+    stb     r9, 3(r8)           /* 8 data bits, 2 stop bits, */
+				/* no parity */
+    eieio
+
+/*
+ * GPIO (LUN 7)
+ */
+    addi    r4, r0, SIO_LUNINDEX    /* select GPIO LUN */
+    addi    r5, r0, 0x7
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASEHI    /* initialize GPIO address to 0x220 */
+    addi    r5, r0, 0x02
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_IOBASELO
+    addi    r5, r0, 0x20
+    bl      .sio_bw
+
+    addi    r4, r0, SIO_ACTIVATE    /* enable GPIO */
+    addi    r5, r0, SIO_LUNENABLE
+    bl      .sio_bw
+
+.sioInit_done:
+
+/*
+ * Get base addr of ISA I/O space
+ */
+    lis     r3, CFG_ISA_IO@h
+    ori     r3, r3, CFG_ISA_IO@l
+
+    addi    r3, r3, 0x015C      /* adjust to superI/O 87308 base */
+    or      r6, r3, r3          /* make a copy */
+/*
+ * CS0
+ */
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x01
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x76
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x02
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x40
+    bl      .sio_bw
+/*
+ * CS1
+ */
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x05
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x05
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x70
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x06
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x1C
+    bl      .sio_bw
+/*
+ * CS2
+ */
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x08
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x00
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x09
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x71
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCI   /* select PCSCIR */
+    addi    r5, r0, 0x0A
+    bl      .sio_bw
+    addi    r4, r0, SIO_PCSCD   /* select PCSCDR */
+    addi    r5, r0, 0x1C
+    bl      .sio_bw
+
+    mtspr   8, r7               /* restore link register */
+    bclr    20, 0               /* return to caller */
+
+/*
+ * this function writes a register to the SIO chip
+ */
+.sio_bw:
+    stb     r4, 0(r3)           /* write index register with register offset */
+    eieio
+    sync
+    stb     r5, 1(r3)           /* 1st write */
+    eieio
+    sync
+    stb     r5, 1(r3)           /* 2nd write */
+    eieio
+    sync
+    bclr    20, 0               /* return to caller */
+/*
+ * this function reads a register from the SIO chip
+ */
+.sio_br:
+    stb     r4, 0(r3)           /* write index register with register offset */
+    eieio
+    sync
+    lbz     r3, 1(r3)           /* retrieve specified reg offset contents */
+    eieio
+    sync
+    bclr    20, 0               /* return to caller */
+
+/*
+ * Print a message to COM1 in polling mode
+ * r10=COM1 port, r3=(char*)string
+ */
+.globl Printf
+Printf:
+    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+
+WaitChr:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, WaitChr        /* wait till empty */
+    lbzx    r0, r0, r3          /* get char */
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addi    r3, r3, 1           /* next char */
+    lbzx    r0, r0, r3          /* get char */
+    cmpwi   cr1, r0, 0          /* end of string ? */
+    bne     cr1, WaitChr
+    blr
+
+/*
+ * Print 8/4/2 digits hex value to COM1 in polling mode
+ * r10=COM1 port, r3=val
+ */
+OutHex2:
+    li      r9, 4               /* shift reg for 2 digits */
+    b       OHstart
+OutHex4:
+    li      r9, 12              /* shift reg for 4 digits */
+    b       OHstart
+    .globl OutHex
+OutHex:
+    li      r9, 28              /* shift reg for 8 digits */
+OHstart:
+    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+OutDig:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDig
+    sraw    r0, r3, r9
+    clrlwi  r0, r0, 28
+    cmpwi   cr1, r0, 9
+    ble     cr1, digIsNum
+    addic   r0, r0, 55
+    b       nextDig
+digIsNum:
+    addic   r0, r0, 48
+nextDig:
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addic.  r9, r9, -4
+    bge     OutDig
+    blr
+/*
+ * Print 3 digits hdec value to COM1 in polling mode
+ * r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch
+ */
+.globl OutDec
+OutDec:
+    li      r6, 10
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r9 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r9, r10, r3
+
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r8 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r8, r10, r3
+
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r7 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r7, r10, r3
+
+    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+
+    or.     r7, r7, r7
+    bne     noblank1
+    li      r3, 0x20
+    b       OutDec4
+
+noblank1:
+    addi    r3, r7, 48          /* convert to ASCII */
+
+OutDec4:
+    lbz     r0, 0(r13)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec4
+    stb     r3, 0(r10)          /* x00 to transmit */
+    eieio
+
+    or.     r7, r7, r8
+    beq     OutDec5
+
+    addi    r3, r8, 48          /* convert to ASCII */
+OutDec5:
+    lbz     r0, 0(r13)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec5
+    stb     r3, 0(r10)          /* x0  to transmit */
+    eieio
+
+    addi    r3, r9, 48          /* convert to ASCII */
+OutDec6:
+    lbz     r0, 0(r13)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec6
+    stb     r3, 0(r10)          /* x   to transmit */
+    eieio
+    blr
+/*
+ * Print a char to COM1 in polling mode
+ * r10=COM1 port, r3=char
+ */
+.globl    OutChr
+OutChr:
+    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    ori     r10, r10, 0x03f8
+
+OutChr1:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutChr1        /* wait till empty */
+    stb     r3, 0(r10)          /* write to transmit reg */
+    eieio
+    blr
+/*
+ * Input:  r3 adr to read
+ * Output: r3 val or -1 for error
+ */
+spdRead:
+    mfspr   r26, 8              /* save link register */
+
+    lis     r30, CFG_ISA_IO@h
+    ori     r30, r30, 0x220     /* GPIO Port 1 */
+    li      r7, 0x00
+    li      r8, 0x100
+    and.    r5, r3, r8
+    beq     spdbank0
+    li      r12, 0x08
+    li      r4, 0x10
+    li      r6, 0x18
+    b       spdRead1
+
+spdbank0:
+    li      r12, 0x20           /* set I2C data */
+    li      r4, 0x40            /* set I2C clock */
+    li      r6, 0x60            /* set I2C clock and data */
+
+spdRead1:
+    li      r8, 0x80
+
+    bl      spdStart            /* access I2C bus as master */
+    li      r10, 0xa0           /* write to SPD */
+    bl      spdWriteByte
+    bl      spdReadAck          /* ACK returns in r10 */
+    cmpw    cr0, r10, r7
+    bne     AckErr              /* r10 must be 0, if ACK received */
+    mr      r10, r3             /* adr to read */
+    bl      spdWriteByte
+    bl      spdReadAck
+    cmpw    cr0, r10, r7
+    bne     AckErr
+    bl      spdStart
+    li      r10, 0xa1           /* read from SPD */
+    bl      spdWriteByte
+    bl      spdReadAck
+    cmpw    cr0, r10, r7
+    bne     AckErr
+    bl      spdReadByte         /* return val in r10 */
+    bl      spdWriteAck
+    bl      spdStop             /* release I2C bus */
+    mr      r3, r10
+    mtspr   8, r26              /* restore link register */
+    blr
+/*
+ * ACK error occurred
+ */
+AckErr:
+    bl      spdStop
+    orc     r3, r0, r0          /* return -1 */
+    mtspr   8, r26              /* restore link register */
+    blr
+
+/*
+ * Routines to read from RAM spd.
+ * r30 - GPIO Port1 address in all cases.
+ * r4 - clock mask for SPD
+ * r6 - port mask for SPD
+ * r12 - data mask for SPD
+ */
+waitSpd:
+    li      r0, 0x1000
+    mtctr   r0
+wSpd:
+    bdnz    wSpd
+    bclr    20, 0               /* return to caller */
+
+/*
+ * establish START condition on I2C bus
+ */
+spdStart:
+    mfspr   r27, 8              /* save link register */
+    stb     r6, 0(r30)          /* set SDA and SCL */
+    eieio
+    stb     r6, 1(r30)          /* switch GPIO to output */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* reset SDA */
+    eieio
+    bl      waitSpd
+    stb     r7, 0(r30)          /* reset SCL */
+    eieio
+    bl      waitSpd
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+/*
+ * establish STOP condition on I2C bus
+ */
+spdStop:
+    mfspr   r27, 8              /* save link register */
+    stb     r7, 0(r30)          /* reset SCL and SDA */
+    eieio
+    stb     r6, 1(r30)          /* switch GPIO to output */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* set SCL */
+    eieio
+    bl      waitSpd
+    stb     r6, 0(r30)          /* set SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r7, 1(r30)          /* switch GPIO to input */
+    eieio
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+spdReadByte:
+    mfspr   r27, 8
+    stb     r4, 1(r30)          /* set GPIO for SCL output */
+    eieio
+    li      r9, 0x08
+    li      r10, 0x00
+loopRB:
+    stb     r7, 0(r30)          /* reset SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* set SCL */
+    eieio
+    bl      waitSpd
+    lbz     r5, 0(r30)          /* read from GPIO Port1 */
+    rlwinm  r10, r10, 1, 0, 31
+    and.    r5, r5, r12
+    beq     clearBit
+    ori     r10, r10, 0x01      /* append _1_ */
+clearBit:
+    stb     r7, 0(r30)          /* reset SCL */
+    eieio
+    bl      waitSpd
+    addic.  r9, r9, -1
+    bne     loopRB
+    mtspr   8, r27
+    bclr    20, 0               /* return (r10) to caller */
+
+/*
+ * spdWriteByte writes bits 24 - 31 of r10 to I2C.
+ * r8 contains bit mask 0x80
+ */
+spdWriteByte:
+    mfspr   r27, 8              /* save link register */
+    li      r9, 0x08            /* write octet */
+    and.    r5, r10, r8
+    bne     sWB1
+    stb     r7, 0(r30)          /* set SDA to _0_ */
+    eieio
+    b       sWB2
+sWB1:
+    stb     r12, 0(r30)         /* set SDA to _1_ */
+    eieio
+sWB2:
+    stb     r6, 1(r30)          /* set GPIO to output */
+    eieio
+loopWB:
+    and.    r5, r10, r8
+    bne     sWB3
+    stb     r7, 0(r30)          /* set SDA to _0_ */
+    eieio
+    b       sWB4
+sWB3:
+    stb     r12, 0(r30)         /* set SDA to _1_ */
+    eieio
+sWB4:
+    bl      waitSpd
+    and.    r5, r10, r8
+    bne     sWB5
+    stb     r4, 0(r30)          /* set SDA to _0_ and SCL */
+    eieio
+    b       sWB6
+sWB5:
+    stb     r6, 0(r30)          /* set SDA to _1_ and SCL */
+    eieio
+sWB6:
+    bl      waitSpd
+    and.    r5, r10, r8
+    bne     sWB7
+    stb     r7, 0(r30)          /* set SDA to _0_ and reset SCL */
+    eieio
+    b       sWB8
+sWB7:
+    stb     r12, 0(r30)         /* set SDA to _1_ and reset SCL */
+    eieio
+sWB8:
+    bl      waitSpd
+    rlwinm  r10, r10, 1, 0, 31  /* next bit */
+    addic.  r9, r9, -1
+    bne     loopWB
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+/*
+ * Read ACK from SPD, return value in r10
+ */
+spdReadAck:
+    mfspr   r27, 8              /* save link register */
+    stb     r4, 1(r30)          /* set GPIO to output */
+    eieio
+    stb     r7, 0(r30)          /* reset SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r4, 0(r30)          /* set SCL */
+    eieio
+    bl      waitSpd
+    lbz     r10, 0(r30)         /* read GPIO Port 1 and mask SDA */
+    and     r10, r10, r12
+    bl      waitSpd
+    stb     r7, 0(r30)          /* reset SDA and SCL */
+    eieio
+    bl      waitSpd
+    mtspr   8, r27
+    bclr    20, 0               /* return (r10) to caller */
+
+spdWriteAck:
+    mfspr   r27, 8
+    stb     r12, 0(r30)         /* set SCL */
+    eieio
+    stb     r6, 1(r30)          /* set GPIO to output */
+    eieio
+    bl      waitSpd
+    stb     r6, 0(r30)          /* SDA and SCL */
+    eieio
+    bl      waitSpd
+    stb     r12, 0(r30)         /* reset SCL */
+    eieio
+    bl      waitSpd
+    mtspr   8, r27
+    bclr    20, 0               /* return to caller */
+
+get_lnk_reg:
+    mflr    r3                  /* return link reg */
+    blr
+
+/*
+ * Messages for console output
+ */
+.globl MessageBlock
+MessageBlock:
+Mok:
+    .ascii  "OK\015\012\000"
+Mfail:
+    .ascii  "FAILED\015\012\000"
+Mna:
+    .ascii  "NA\015\012\000"
+MinitLogo:
+    .ascii  "\015\012*** ELTEC Elektronik, Mainz ***\015\012"
+    .ascii  "\015\012Initialising RAM\015\012\000"
+Mspd01:
+    .ascii  "       Reading SPD of bank0/1 ..... \000"
+Mspd23:
+    .ascii  "       Reading SPD of bank2/3 ..... \000"
+MfpmRam:
+    .ascii  "       RAM-Type: FPM \015\012\000"
+MedoRam:
+    .ascii  "       RAM-Type: EDO \015\012\000"
+MsdRam:
+    .ascii  "       RAM-Type: SDRAM \015\012\000"
+Mactivate:
+    .ascii  "       Activating \000"
+Mmbyte:
+    .ascii  " MB .......... \000"
+    .align  4
diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c
new file mode 100755
index 0000000..fc48ed5
--- /dev/null
+++ b/board/eltec/bab7xx/bab7xx.c
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ * (C) Copyright 2001 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc106.h>
+#include <mk48t59.h>
+#include <74xx_7xx.h>
+#include <ns87308.h>
+#include <video_fb.h>
+
+/*---------------------------------------------------------------------------*/
+/*
+ * Get Bus clock frequency
+ */
+ulong bab7xx_get_bus_freq (void)
+{
+	/*
+	 * The GPIO Port 1 on BAB7xx reflects the bus speed.
+	 */
+	volatile struct GPIO *gpio =
+		(struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
+
+	unsigned char data = gpio->dta1;
+
+	if (data & 0x02)
+		return 66666666;
+
+	return 83333333;
+}
+
+/*---------------------------------------------------------------------------*/
+
+/*
+ * Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz)
+ */
+ulong bab7xx_get_gclk_freq (void)
+{
+	static const int pllratio_to_factor[] = {
+		00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
+			00,
+	};
+
+	return pllratio_to_factor[get_hid1 () >> 28] *
+		(bab7xx_get_bus_freq () / 10);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int checkcpu (void)
+{
+	uint pvr = get_pvr ();
+
+	printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
+	printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
+		bab7xx_get_bus_freq () / 1000000);
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkboard (void)
+{
+#ifdef CFG_ADDRESS_MAP_A
+	puts ("Board: ELTEC BAB7xx PReP\n");
+#else
+	puts ("Board: ELTEC BAB7xx CHRP\n");
+#endif
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("2 MB ## Test not implemented yet ##\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static unsigned int mpc106_read_cfg_dword (unsigned int reg)
+{
+	unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
+
+	out32r (MPC106_REG_ADDR, reg_addr);
+
+	return (in32r (MPC106_REG_DATA | (reg & 0x3)));
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int dram_size (int board_type)
+{
+	/* No actual initialisation to do - done when setting up
+	 * PICRs MCCRs ME/SARs etc in ram_init.S.
+	 */
+
+	register unsigned long i, msar1, mear1, memSize;
+
+#if defined(CFG_MEMTEST)
+	register unsigned long reg;
+
+	printf ("Testing DRAM\n");
+
+	/* write each mem addr with it's address */
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
+		*reg = reg;
+
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
+		if (*reg != reg)
+			return -1;
+	}
+#endif
+
+	/*
+	 * Since MPC106 memory controller chip has already been set to
+	 * control all memory, just read and interpret its memory boundery register.
+	 */
+	memSize = 0;
+	msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
+	mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
+	i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
+
+	do {
+		if (i & 0x01)	/* is bank enabled ? */
+			memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
+		msar1 >>= 8;
+		mear1 >>= 8;
+		i >>= 1;
+	} while (i);
+
+	return (memSize * 0x100000);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	return dram_size (board_type);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void after_reloc (ulong dest_addr)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*
+	 * Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *) gd, dest_addr);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * do_reset is done here because in this case it is board specific, since the
+ * 7xx CPUs can only be reset by external HW (the RTC in this case).
+ */
+void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+#if defined(CONFIG_RTC_MK48T59)
+	/* trigger watchdog immediately */
+	rtc_set_watchdog (1, RTC_WD_RB_16TH);
+#else
+#error "You must define the macro CONFIG_RTC_MK48T59."
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+/*
+ * Since the 7xx CPUs don't have an internal watchdog, this function is
+ * board specific.  We use the RTC here.
+ */
+void watchdog_reset (void)
+{
+#if defined(CONFIG_RTC_MK48T59)
+	/* we use a 32 sec watchdog timer */
+	rtc_set_watchdog (8, RTC_WD_RB_4);
+#else
+#error "You must define the macro CONFIG_RTC_MK48T59."
+#endif
+}
+#endif /* CONFIG_WATCHDOG */
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
+			 (get_pvr () >> 8) & 0xFF,
+			 get_pvr () & 0xFF,
+			 bab7xx_get_gclk_freq () / 1000000,
+			 bab7xx_get_bus_freq () / 1000000);
+		return;
+	case 2:
+		sprintf (info,
+			 " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
+			 dram_size (0) / 0x100000, flash_init () / 0x100000);
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
+
+	/* no more info lines */
+	*info = 0;
+	return;
+}
+#endif
+
+/*---------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/config.mk b/board/eltec/bab7xx/config.mk
new file mode 100755
index 0000000..aa463c5
--- /dev/null
+++ b/board/eltec/bab7xx/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/eltec/bab7xx/dc_srom.c b/board/eltec/bab7xx/dc_srom.c
new file mode 100755
index 0000000..a44af6e
--- /dev/null
+++ b/board/eltec/bab7xx/dc_srom.c
@@ -0,0 +1,291 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SRom I/O routines.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include "srom.h"
+
+#define SROM_RD         0x00004000    /* Read from Boot ROM */
+#define SROM_WR         0x00002000    /* Write to Boot ROM */
+#define SROM_SR         0x00000800    /* Select Serial ROM when set */
+
+#define DT_IN           0x00000004    /* Serial Data In */
+#define DT_CLK          0x00000002    /* Serial ROM Clock */
+#define DT_CS           0x00000001    /* Serial ROM Chip Select */
+
+static u_int         dc_srom_iobase;
+
+/*----------------------------------------------------------------------------*/
+
+static int inl(u_long addr)
+{
+    return le32_to_cpu(*(volatile u_long *)(addr));
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void outl (int command, u_long addr)
+{
+    *(volatile u_long *)(addr) = cpu_to_le32(command);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void sendto_srom(u_int command, u_long addr)
+{
+    outl(command, addr);
+    udelay(1);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int getfrom_srom(u_long addr)
+{
+    s32 tmp;
+
+    tmp = inl(addr);
+    udelay(1);
+
+    return tmp;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_latch (u_int command, u_long addr)
+{
+    sendto_srom (command, addr);
+    sendto_srom (command | DT_CLK, addr);
+    sendto_srom (command, addr);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_command_rd (u_int command, u_long addr)
+{
+    srom_latch (command, addr);
+    srom_latch (command, addr);
+    srom_latch ((command & 0x0000ff00) | DT_CS, addr);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_command_wr (u_int command, u_long addr)
+{
+    srom_latch (command, addr);
+    srom_latch ((command & 0x0000ff00) | DT_CS, addr);
+    srom_latch (command, addr);
+
+    return;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_address(u_int command, u_long addr, u_char offset)
+{
+    int i;
+    signed char a;
+
+    a = (char)(offset << 2);
+    for (i=0; i<6; i++, a <<= 1)
+    {
+	srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
+    }
+    udelay(1);
+
+    i = (getfrom_srom(addr) >> 3) & 0x01;
+
+    return;
+}
+/*----------------------------------------------------------------------------*/
+
+static short srom_data_rd (u_int command, u_long addr)
+{
+    int i;
+    short word = 0;
+    s32 tmp;
+
+    for (i=0; i<16; i++)
+    {
+	sendto_srom(command  | DT_CLK, addr);
+	tmp = getfrom_srom(addr);
+	sendto_srom(command, addr);
+
+	word = (word << 1) | ((tmp >> 3) & 0x01);
+    }
+
+    sendto_srom(command & 0x0000ff00, addr);
+
+    return word;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int srom_data_wr (u_int command, u_long addr, short val)
+{
+    int i;
+    u_long longVal;
+    s32 tmp;
+
+    longVal = (u_long)(le16_to_cpu(val));
+
+    for (i=0; i<16; i++)
+    {
+	tmp = (longVal & 0x8000)>>13;
+
+	sendto_srom (tmp | command, addr);
+	sendto_srom (tmp | command  | DT_CLK, addr);
+	sendto_srom (tmp | command, addr);
+
+	longVal = longVal<<1;
+    }
+
+    sendto_srom(command & 0x0000ff00, addr);
+    sendto_srom(command, addr);
+
+    tmp = 100;
+    do
+    {
+	if ((getfrom_srom(dc_srom_iobase) & 0x8) == 0x8)
+	    break;
+	udelay(1000);
+    } while (--tmp);
+
+    if (tmp == 0)
+    {
+	printf("Write DEC21143 SRom timed out !\n");
+	return (-1);
+    }
+
+    return 0;
+}
+
+
+/*----------------------------------------------------------------------------*/
+static short srom_rd (u_long addr, u_char offset)
+{
+    sendto_srom (SROM_RD | SROM_SR, addr);
+    srom_latch (SROM_RD | SROM_SR | DT_CS, addr);
+
+    srom_command_rd (SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
+
+    srom_address (SROM_RD | SROM_SR | DT_CS, addr, offset);
+
+    return srom_data_rd (SROM_RD | SROM_SR | DT_CS, addr);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void srom_wr_enable (u_long addr)
+{
+    int i;
+
+    sendto_srom (SROM_WR | SROM_SR, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+
+    srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+
+    for (i=0; i<6; i++)
+    {
+	srom_latch (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
+    }
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int srom_wr (u_long addr, u_char offset, short val)
+{
+    srom_wr_enable (addr);
+
+    sendto_srom (SROM_WR | SROM_SR, addr);
+    srom_latch (SROM_WR | SROM_SR | DT_CS, addr);
+
+    srom_command_wr (SROM_WR | SROM_SR | DT_IN | DT_CS, addr);
+
+    srom_address (SROM_WR | SROM_SR | DT_CS, addr, offset);
+
+    return srom_data_wr (SROM_WR | SROM_SR | DT_CS, addr, val);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * load data from the srom
+ */
+int dc_srom_load (u_short *dest)
+{
+    int offset;
+    short tmp;
+
+    /* get srom iobase from local network controller */
+    pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase);
+    dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+    dc_srom_iobase  = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase);
+    dc_srom_iobase += 0x48;            /* io offset for srom access */
+
+    memset (dest, 0, 128);
+    for (offset=0; offset<64; offset++)
+    {
+	tmp = srom_rd (dc_srom_iobase, offset);
+	*dest++ = le16_to_cpu(tmp);
+    }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
+
+/*
+ * store data into the srom
+ */
+int dc_srom_store (u_short *src)
+{
+    int offset;
+
+    /* get srom iobase from local network controller */
+    pci_read_config_dword(PCI_BDF(0,14,0), PCI_BASE_ADDRESS_1, &dc_srom_iobase);
+    dc_srom_iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+    dc_srom_iobase  = pci_mem_to_phys(PCI_BDF(0,14,0), dc_srom_iobase);
+    dc_srom_iobase += 0x48;            /* io offset for srom access */
+
+    for (offset=0; offset<64; offset++)
+    {
+	if (srom_wr (dc_srom_iobase, offset, *src) == -1)
+		return (-1);
+	src++;
+    }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/el_srom.c b/board/eltec/bab7xx/el_srom.c
new file mode 100755
index 0000000..73f8066
--- /dev/null
+++ b/board/eltec/bab7xx/el_srom.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "srom.h"
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  START sequence
+ *        _ _________
+ *  SCLK  _>         \____
+ *        _ ____
+ *  SDIO  _>    \_________
+ *         :    :    :
+ */
+static void eepStart (void)
+{
+    out8(I2C_BUS_DAT, 0x60);     /* SCLK = high  SDIO = high */
+    out8(I2C_BUS_DIR, 0x60);     /* set output direction for SCLK/SDIO */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x40);     /* SCLK = high  SDIO = low */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x00);     /* SCLK = low   SDIO = low */
+    udelay(10);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  STOP sequence
+ *              _______
+ *  SCLK  _____/
+ *        _         ___
+ *  SDIO  _>_______/
+ *         :   :   :
+ */
+static void eepStop (void)
+{
+    out8(I2C_BUS_DAT, 0x00);      /* SCLK = low   SDIO = low */
+    out8(I2C_BUS_DIR, 0x60);      /* set output direction for SCLK/SDIO */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x40);      /* SCLK = high  SDIO = low */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x60);      /* SCLK = high  SDIO = high */
+    udelay(10);
+    out8(I2C_BUS_DIR, 0x00);      /* reset to input direction */
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Read one byte from EEPROM
+ *            ___     ___     ___     ___     ___     ___     ___     ___
+ *  SCLK  ___/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \
+ *        _________________________________________________________________
+ *  SDIO  >     ^       ^       ^       ^       ^       ^       ^       ^
+ *        :  :   :   :   :   :   :   :   :   :   :   :   :   :   :   :   :
+ */
+static unsigned char eepReadByte (void)
+{
+    register unsigned char buf = 0x00;
+    register int i;
+
+    out8(I2C_BUS_DIR, 0x40);
+
+    for (i = 0; i < 8; i++)
+    {
+	out8(I2C_BUS_DAT, 0x00);    /* SCLK = low   SDIO = high */
+	udelay(10);
+	out8(I2C_BUS_DAT, 0x40);    /* SCLK = high  SDIO = high */
+	udelay(15);
+	buf <<= 1;
+	buf = (in8(I2C_BUS_DAT) & 0x20) ? (buf | 0x01) : (buf & 0xFE);
+	out8(I2C_BUS_DAT, 0x00);    /* SCLK = low   SDIO = high */
+	udelay(10);
+    }
+    return(buf);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Write one byte to EEPROM
+ *           ___     ___     ___     ___     ___     ___     ___     ___
+ *  SCLK  __/   \___/   \___/   \___/   \___/   \___/   \___/   \___/   \__
+ *         _______ _______ _______ _______ _______ _______ _______ ________
+ *  SDIO  X_______X_______X_______X_______X_______X_______X_______X________
+ *      :   7   :   6   :   5   :   4   :   3   :   2   :   1   :   0
+ */
+static void eepWriteByte (register unsigned char buf)
+{
+    register int    i;
+
+    (buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00);     /* SCLK = low   SDIO = data */
+    out8(I2C_BUS_DIR, 0x60);
+
+    for (i = 7; i >= 0; i--)
+    {
+	(buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low  SDIO=data */
+	udelay(10);
+	(buf & 0x80) ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK=high SDIO=data */
+	udelay(15);
+	(buf & 0x80) ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK=low  SDIO=data */
+	udelay(10);
+	buf <<= 1;
+    }
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Read data acknowledge of EEPROM
+ *             _______
+ *  SCLK  ____/       \___
+ *         _______________
+ *  SDIO  >
+ *        :   :   ^   :
+ */
+static int eepReadAck (void)
+{
+    int retval;
+
+    out8(I2C_BUS_DIR, 0x40);
+    out8(I2C_BUS_DAT, 0x00);            /* SCLK = low   SDIO = high */
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x40);            /* SCLK = high  SDIO = high */
+    udelay(10);
+    retval = (in8(I2C_BUS_DAT) & 0x20) ? ERROR : 0;
+    udelay(10);
+    out8(I2C_BUS_DAT, 0x00);            /* SCLK = low   SDIO = high */
+    udelay(10);
+
+    return(retval);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *  Write data acknowledge to EEPROM
+ *             _______
+ *  SCLK  ____/       \___
+ *
+ *  SDIO  >_______________
+ *        :   :       :
+ */
+static void eepWriteAck (unsigned char ack)
+{
+    ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low   SDIO = ack */
+    out8(I2C_BUS_DIR, 0x60);
+    udelay(10);
+    ack ? out8(I2C_BUS_DAT, 0x60) : out8(I2C_BUS_DAT, 0x40); /* SCLK = high  SDIO = ack */
+    udelay(15);
+    ack ? out8(I2C_BUS_DAT, 0x20) : out8(I2C_BUS_DAT, 0x00); /* SCLK = low   SDIO = ack */
+    udelay(10);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Read bytes from EEPROM
+ */
+int el_srom_load (addr, buf, cnt, device, block)
+unsigned char addr;
+unsigned char *buf;
+int cnt;
+unsigned char device;
+unsigned char block;
+{
+    register int i;
+
+    for (i=0;i<cnt;i++)
+    {
+	eepStart();
+	eepWriteByte(0xA0 | device | block);
+	if (eepReadAck() == ERROR)
+	{
+	   eepStop();
+	    return(ERROR);
+	}
+	eepWriteByte(addr++);
+	if (eepReadAck() == ERROR)
+	{
+	    eepStop();
+	    return(ERROR);
+	}
+	eepStart();
+
+	eepWriteByte(0xA1 | device | block);
+	if (eepReadAck() == ERROR)
+	{
+	    eepStop();
+	    return(ERROR);
+	}
+
+	*buf++ = eepReadByte();
+	eepWriteAck(1);
+	eepStop();
+
+	if ((addr == 0) && (i != (cnt-1)))    /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+		return(ERROR);
+	}
+    }
+    return(cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ *
+ * Write bytes to EEPROM
+ *
+ */
+int el_srom_store (addr, buf, cnt, device, block)
+unsigned char    addr, *buf, device, block;
+int        cnt;
+{
+    register int i, retVal;
+
+    for (i=0;i<cnt;i++)
+    {
+	retVal = ERROR;
+	do
+	{
+	    eepStart();
+	    eepWriteByte(0xA0 | device | block);
+	    if ((retVal = eepReadAck()) == ERROR)
+		eepStop();
+	} while (retVal == ERROR);
+
+	eepWriteByte(addr++);
+	if (eepReadAck() == ERROR)  return(ERROR);
+
+	if ((addr == 0) && (i != (cnt-1)))    /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+	    return(ERROR);
+	}
+
+	eepWriteByte(*buf++);
+	if (eepReadAck() == ERROR)
+	    return(ERROR);
+
+	eepStop();
+    }
+    return(cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * calculate checksum for ELTEC revision srom
+ */
+unsigned long el_srom_checksum (ptr, size)
+register unsigned char *ptr;
+unsigned long size;
+{
+    u_long f, accu = 0;
+    u_int  i;
+    u_char byte;
+
+    for (; size; size--)
+    {
+	byte = *ptr++;
+	for (i = 8; i; i--)
+	{
+	    f =  ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0;
+	    accu >>= 1; accu ^= f;
+	    byte >>= 1;
+	}
+    }
+    return(accu);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/flash.c b/board/eltec/bab7xx/flash.c
new file mode 100755
index 0000000..442dd00
--- /dev/null
+++ b/board/eltec/bab7xx/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC).
+ *        fixed monitor protection part
+ *
+ * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage
+ *        of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use
+ *        any other.
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0           (0x555)
+#define ADDR1           (0x2AA)
+#define ADDR3           (0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*----------------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+    unsigned long size1, size2;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+    {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* initialise 1st flash */
+    size1 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+    if (flash_info[0].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	    size1, size1<<20);
+    }
+
+    /* initialise 2nd flash */
+    size2 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+    if (flash_info[1].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+	    size2, size2<<20);
+    }
+
+    /* monitor protection ON by default */
+    if (size1 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE0_PRELIM,
+		FLASH_BASE0_PRELIM+monitor_flash_len-1,
+		&flash_info[0]);
+    }
+    if (size2 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE1_PRELIM,
+		FLASH_BASE1_PRELIM+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+    if (size2 == 4*1024*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		CFG_FLASH_BASE,
+		CFG_FLASH_BASE+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+
+    return (size1 + size2);
+}
+
+/*----------------------------------------------------------------------------*/
+
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+    int k;
+    int size;
+    int erased;
+    volatile unsigned long *flash;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	flash_init();
+    }
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+    case FLASH_MAN_AMD:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F016D:
+	printf ("AM29F016D (16 Mbit)\n");
+	break;
+    case AMD_ID_F032B:
+	printf ("AM29F032B (32 Mbit)\n");
+	break;
+   default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    if (info->size >= (1 << 20)) {
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+    } else {
+	printf ("  Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count);
+    }
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	/*
+	* Check if whole sector is erased
+	*/
+	if (i != (info->sector_count-1))
+	    size = info->start[i+1] - info->start[i];
+	else
+	    size = info->start[0] + info->size - info->start[i];
+
+	erased = 1;
+	flash = (volatile unsigned long *)info->start[i];
+	size = size >> 2;        /* divide by 4 for longword access */
+	for (k=0; k<size; k++) {
+	    if (*flash++ != 0xffffffff) {
+		erased = 0;
+		break;
+	    }
+	}
+
+	if ((i % 5) == 0)
+	    printf ("\n   ");
+
+	printf (" %08lX%s%s",
+	    info->start[i],
+	    erased ? " E" : "  ",
+	    info->protect[i] ? "RO " : "   ");
+    }
+    printf ("\n");
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    ulong vendor, devid;
+    ulong base = (ulong)addr;
+    volatile unsigned char *caddr = (unsigned char *)addr;
+
+#ifdef DEBUG
+    printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr);
+#endif
+
+    /* Write auto select command: read Manufacturer ID */
+    caddr[0] = 0xF0;   /* reset bank */
+    udelay(10);
+
+    eieio();
+    caddr[0x555] = 0xAA;
+    udelay(10);
+    caddr[0x2AA] = 0x55;
+    udelay(10);
+    caddr[0x555] = 0x90;
+
+    udelay(10);
+
+    vendor = caddr[0];
+    devid = caddr[1];
+
+#ifdef DEBUG
+    printf("Manufacturer: 0x%lx\n", vendor);
+#endif
+
+    vendor &= 0xff;
+    devid &= 0xff;
+
+    /* We accept only two AMD types */
+    switch (vendor) {
+    case (FLASH_WORD_SIZE)AMD_MANUFACT:
+	info->flash_id = FLASH_MAN_AMD;
+	break;
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	info->sector_count = 0;
+	info->size = 0;
+	return (0);         /* no or unknown flash  */
+    }
+
+    switch (devid) {
+    case (FLASH_WORD_SIZE)AMD_ID_F040B:
+	info->flash_id |= AMD_ID_F040B;
+	info->sector_count = 8;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F016D:
+	info->flash_id |= AMD_ID_F016D;
+	info->sector_count = 32;
+	info->size         = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F032B:
+	info->flash_id |= AMD_ID_F032B;
+	info->sector_count = 64;
+	info->size         = 0x00400000;
+	break;              /* => 4 MB      */
+
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	return (0);         /* => no or unknown flash */
+
+    }
+
+#ifdef DEBUG
+    printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size);
+#endif
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	caddr = (volatile unsigned char *)(info->start[i]);
+	info->protect[i] = caddr[2] & 1;
+    }
+
+    /*
+     * Prevent writes to uninitialized FLASH.
+     */
+    if (info->flash_id != FLASH_UNKNOWN) {
+	caddr = (volatile unsigned char *)info->start[0];
+	caddr[0] = 0xF0;   /* reset bank */
+    }
+
+    return (info->size);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+    int rc = 0;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    if ((info->flash_id == FLASH_UNKNOWN) ||
+	(info->flash_id > FLASH_AMD_COMP)) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+	    prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+	    if (info->flash_id & FLASH_MAN_SST) {
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+		udelay(30000);  /* wait 30 ms */
+	    }
+	    else
+		addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+	goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+DONE:
+    /* reset to read mode */
+    addr = (FLASH_WORD_SIZE *)info->start[0];
+    addr[0] = (FLASH_WORD_SIZE)0x00F000F0;  /* reset bank */
+
+    printf (" done\n");
+    return rc;
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);   /* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*----------------------------------------------------------------------------*/
+/* Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+    ulong start;
+    int flag;
+	int i;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((volatile FLASH_WORD_SIZE *)dest) &
+	     (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/l2cache.c b/board/eltec/bab7xx/l2cache.c
new file mode 100755
index 0000000..1e75377
--- /dev/null
+++ b/board/eltec/bab7xx/l2cache.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_L2_BAB7xx)
+
+#include <pci.h>
+#include <mpc106.h>
+#include <asm/processor.h>
+
+/* defines L2CR register for MPC750 */
+
+#define L2CR_E           0x80000000
+#define L2CR_256K        0x10000000
+#define L2CR_512K        0x20000000
+#define L2CR_1024K       0x30000000
+#define L2CR_I           0x00200000
+#define L2CR_SL          0x00008000
+#define L2CR_IP          0x00000001
+
+/*----------------------------------------------------------------------------*/
+
+static int dummy (int dummy)
+{
+    return (dummy+1);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int l2_cache_enable (int l2control)
+{
+    if (l2control)              /* BAB750 */
+    {
+	mtspr(SPRN_L2CR, l2control);
+	mtspr(SPRN_L2CR, (l2control | L2CR_I));
+	while (mfspr(SPRN_L2CR) & L2CR_IP)
+	    ;
+	mtspr(SPRN_L2CR, (l2control | L2CR_E));
+	return (0);
+    }
+    else /* BAB740 */
+    {
+	int picr1, picr2, mask;
+	int picr2CacheSize, cacheSize;
+	int *d;
+	int devbusfn;
+	u32 reg32;
+
+	devbusfn = pci_find_device(PCI_VENDOR_ID_MOTOROLA,
+				   PCI_DEVICE_ID_MOTOROLA_MPC106, 0);
+	if (devbusfn == -1)
+	    return (-1);
+
+	pci_read_config_dword  (devbusfn, PCI_PICR2, &reg32);
+	reg32 &= ~PICR2_L2_EN;
+	pci_write_config_dword (devbusfn, PCI_PICR2, reg32);
+
+	/* cache size */
+	if (*(volatile unsigned char *) (CFG_ISA_IO + 0x220) & 0x04)
+	{
+	    /* cache size is 512 KB */
+	    picr2CacheSize = PICR2_L2_SIZE_512K;
+	    cacheSize = 0x80000;
+	}
+	else
+	{
+	    /* cache size is 256 KB */
+	    picr2CacheSize = PICR2_L2_SIZE_256K;
+	    cacheSize = 0x40000;
+	}
+
+	/* setup PICR1 */
+	mask =
+	~(PICR1_CF_BREAD_WS(1) |
+	  PICR1_CF_BREAD_WS(2) |
+	  PICR1_CF_CBA(0xff) |
+	  PICR1_CF_CACHE_1G |
+	  PICR1_CF_DPARK |
+	  PICR1_CF_APARK |
+	  PICR1_CF_L2_CACHE_MASK);
+
+	picr1 =
+	(PICR1_CF_CBA(0x3f) |
+	 PICR1_CF_CACHE_1G |
+	 PICR1_CF_APARK |
+	 PICR1_CF_DPARK |
+	 PICR1_CF_L2_COPY_BACK); /* PICR1_CF_L2_WRITE_THROUGH */
+
+	pci_read_config_dword  (devbusfn, PCI_PICR1, &reg32);
+	reg32 &= mask;
+	reg32 |= picr1;
+	pci_write_config_dword (devbusfn, PCI_PICR1, reg32);
+
+	/*
+	 * invalidate all L2 cache
+	 */
+	picr2 =
+	(PICR2_CF_INV_MODE |
+	 PICR2_CF_HIT_HIGH |
+	 PICR2_CF_MOD_HIGH |
+	 PICR2_CF_L2_HIT_DELAY(1) |
+	 PICR2_CF_APHASE_WS(1) |
+	 picr2CacheSize);
+
+	pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
+
+	/*
+	 * dummy transactions
+	 */
+	for (d=0; d<(int *)(2*cacheSize); d++)
+	    dummy(*d);
+
+	pci_write_config_dword (devbusfn, PCI_PICR2,
+				(picr2 | PICR2_CF_FLUSH_L2));
+
+	/* setup PICR2 */
+	picr2 =
+	(PICR2_CF_FAST_CASTOUT |
+	 PICR2_CF_WDATA |
+	 PICR2_CF_ADDR_ONLY_DISABLE |
+	 PICR2_CF_HIT_HIGH |
+	 PICR2_CF_MOD_HIGH |
+	 PICR2_L2_UPDATE_EN |
+	 PICR2_L2_EN |
+	 PICR2_CF_APHASE_WS(1) |
+	 PICR2_CF_DATA_RAM_PBURST |
+	 PICR2_CF_L2_HIT_DELAY(1) |
+	 PICR2_CF_SNOOP_WS(2) |
+	 picr2CacheSize);
+
+	pci_write_config_dword (devbusfn, PCI_PICR2, picr2);
+    }
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
+
+#endif /* (CFG_L2_BAB7xx) */
diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c
new file mode 100755
index 0000000..6a24807
--- /dev/null
+++ b/board/eltec/bab7xx/misc.c
@@ -0,0 +1,547 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* includes */
+#include <common.h>
+#include <linux/ctype.h>
+#include <pci.h>
+#include <net.h>
+#include <mpc106.h>
+#include <w83c553f.h>
+#include "srom.h"
+
+/* imports  */
+extern char console_buffer[CFG_CBSIZE];
+extern int l2_cache_enable (int l2control);
+extern void *nvram_read (void *dest, const short src, size_t count);
+extern void nvram_write (short dest, const void *src, size_t count);
+
+/* globals */
+unsigned int ata_reset_time = 60;
+unsigned int scsi_reset_time = 10;
+unsigned int eltec_board;
+
+/* BAB750 uses SYM53C875(default) and BAB740 uses SYM53C860
+ * values fixed after board identification
+ */
+unsigned short scsi_dev_id = PCI_DEVICE_ID_NCR_53C875;
+unsigned int   scsi_max_scsi_id = 15;
+unsigned char  scsi_sym53c8xx_ccf = 0x13;
+
+/*----------------------------------------------------------------------------*/
+/*
+ * handle sroms on BAB740/750
+ * fix ether address
+ * L2 cache initialization
+ * ide dma control
+ */
+int misc_init_r (void)
+{
+    revinfo eerev;
+    char *ptr;
+    u_int  i, l, initSrom, copyNv;
+    char buf[256];
+    char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+	     0, 0, 0, 0, 10, 11, 12, 13, 14, 15 };
+    pci_dev_t bdf;
+
+    char sromSYM[] = {
+#ifdef TULIP_BUG
+    /* 10BaseT, 100BaseTx no full duplex modes */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
+    0x02, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
+    0x88, 0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61,
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6, 0xe8
+#endif
+    /* 10BaseT, 10BaseT-FD, 100BaseTx, 100BaseTx-FD */
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
+    0x04, 0x86, 0x02, 0x00, 0xaf, 0x08, 0xa5, 0x00,
+    0x86, 0x02, 0x04, 0xaf, 0x08, 0xa5, 0x00, 0x88,
+    0x04, 0x03, 0x27, 0x08, 0x25, 0x00, 0x61, 0x80,
+    0x88, 0x04, 0x05, 0x27, 0x08, 0x25, 0x00, 0x61,
+    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x77
+    };
+
+    char sromMII[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x5b, 0x00,
+    0x2e, 0x4d, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x08,
+    0x01, 0x95, 0x03, 0x00, 0x00, 0x04, 0x01, 0x08,
+    0x00, 0x00, 0x02, 0x08, 0x02, 0x00, 0x00, 0x78,
+    0xe0, 0x01, 0x00, 0x50, 0x00, 0x18, 0x80, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xde, 0x41
+    };
+
+    /*
+     * Check/Remake revision info
+     */
+    initSrom = 0;
+    copyNv   = 0;
+
+    /* read out current revision srom contens */
+    el_srom_load (0x0000, (u_char*)&eerev, sizeof(revinfo),
+		SECOND_DEVICE, FIRST_BLOCK);
+
+    /* read out current nvram shadow image */
+    nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
+
+    if (strcmp (eerev.magic, "ELTEC") != 0)
+    {
+	/* srom is not initialized -> create a default revision info */
+	for (i = 0, ptr = (char *)&eerev; i < sizeof(revinfo); i++)
+	    *ptr++ = 0x00;
+	strcpy(eerev.magic, "ELTEC");
+	eerev.revrev[0] = 1;
+	eerev.revrev[1] = 0;
+	eerev.size = 0x00E0;
+	eerev.category[0] = 0x01;
+
+	/* node id from dead e128 as default */
+	eerev.etheraddr[0] = 0x00;
+	eerev.etheraddr[1] = 0x00;
+	eerev.etheraddr[2] = 0x5B;
+	eerev.etheraddr[3] = 0x00;
+	eerev.etheraddr[4] = 0x2E;
+	eerev.etheraddr[5] = 0x4D;
+
+	/* cache config word for bab750 */
+	*(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
+
+	initSrom = 1;  /* force dialog */
+	copyNv   = 1;  /* copy to nvram */
+    }
+
+    if ((copyNv == 0) &&   (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) !=
+		el_srom_checksum((u_char*)buf, CFG_SROM_SIZE)))
+    {
+	printf ("Invalid revision info copy in nvram !\n");
+	printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
+	printf ("  <r> to reenter revision info.\n");
+	printf ("=> ");
+	if (0 != readline (NULL))
+	{
+	    switch ((char)toupper(console_buffer[0]))
+	    {
+	    case 'C':
+		copyNv = 1;
+		break;
+	    case 'R':
+		copyNv = 1;
+		initSrom = 1;
+		break;
+	    }
+	}
+    }
+
+    if (initSrom)
+    {
+	memcpy (buf, &eerev.revision[0][0], 14);     /* save all revision info */
+	printf ("Enter revision number (0-9): %c  ", eerev.revision[0][0]);
+	if (0 != readline (NULL))
+	{
+	    eerev.revision[0][0] = (char)toupper(console_buffer[0]);
+	    memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
+	}
+
+	printf ("Enter revision character (A-Z): %c  ", eerev.revision[0][1]);
+	if (1 == readline (NULL))
+	{
+	    eerev.revision[0][1] = (char)toupper(console_buffer[0]);
+	}
+
+	printf ("Enter board name (V-XXXX-XXXX): %s  ", (char *)&eerev.board);
+	if (11 == readline (NULL))
+	{
+	    for (i=0; i<11; i++)
+		eerev.board[i] =  (char)toupper(console_buffer[i]);
+	    eerev.board[11] = '\0';
+	}
+
+	printf ("Enter serial number: %s ", (char *)&eerev.serial );
+	if (6 == readline (NULL))
+	{
+	    for (i=0; i<6; i++)
+		eerev.serial[i] = console_buffer[i];
+	    eerev.serial[6] = '\0';
+	}
+
+	printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ",
+	    eerev.etheraddr[0], eerev.etheraddr[1],
+	    eerev.etheraddr[2], eerev.etheraddr[3],
+	    eerev.etheraddr[4], eerev.etheraddr[5]);
+	if (12 == readline (NULL))
+	{
+	    for (i=0; i<12; i+=2)
+	    eerev.etheraddr[i>>1] = (char)(16*hex[toupper(console_buffer[i])-'0'] +
+			       hex[toupper(console_buffer[i+1])-'0']);
+	}
+
+	l = strlen ((char *)&eerev.text);
+	printf("Add to text section (max 64 chr): %s ", (char *)&eerev.text );
+	if (0 != readline (NULL))
+	{
+	    for (i = l; i<63; i++)
+		eerev.text[i] = console_buffer[i-l];
+	    eerev.text[63] = '\0';
+	}
+
+	if (strstr ((char *)&eerev.board, "75") != NULL)
+	    eltec_board = 750;
+	else
+	    eltec_board = 740;
+
+	if (eltec_board == 750)
+	{
+	    if (CPU_TYPE == CPU_TYPE_750)
+		*(int*)&eerev.res[0] = CLK2P0TO1_1MB_PB_0P5DH;
+		else
+		*(int*)&eerev.res[0] = CLK2P5TO1_1MB_PB_0P5DH;
+
+	    printf("Enter L2Cache config word with leading zero (HEX): %08X  ",
+		    *(int*)&eerev.res[0] );
+	    if (0 != readline (NULL))
+	    {
+		for (i=0; i<7; i+=2)
+		{
+		    eerev.res[i>>1] =
+		    (char)(16*hex[toupper(console_buffer[i])-'0'] +
+		    hex[toupper(console_buffer[i+1])-'0']);
+		}
+	    }
+
+	    /* prepare network eeprom */
+	    sromMII[20] = eerev.etheraddr[0];
+	    sromMII[21] = eerev.etheraddr[1];
+	    sromMII[22] = eerev.etheraddr[2];
+	    sromMII[23] = eerev.etheraddr[3];
+	    sromMII[24] = eerev.etheraddr[4];
+	    sromMII[25] = eerev.etheraddr[5];
+	    printf("\nSRom:  Writing DEC21143 MII info .. ");
+
+	    if (dc_srom_store ((u_short *)sromMII) == -1)
+		printf("FAILED\n");
+	    else
+		printf("OK\n");
+	}
+
+	if (eltec_board == 740)
+	{
+	    *(int *)&eerev.res[0] = 0;
+	    sromSYM[20] = eerev.etheraddr[0];
+	    sromSYM[21] = eerev.etheraddr[1];
+	    sromSYM[22] = eerev.etheraddr[2];
+	    sromSYM[23] = eerev.etheraddr[3];
+	    sromSYM[24] = eerev.etheraddr[4];
+	    sromSYM[25] = eerev.etheraddr[5];
+	    printf("\nSRom:  Writing DEC21143 SYM info .. ");
+
+	    if (dc_srom_store ((u_short *)sromSYM) == -1)
+		printf("FAILED\n");
+	    else
+		printf("OK\n");
+	}
+
+	/* update CRC */
+	eerev.crc = el_srom_checksum((u_char *)eerev.board, eerev.size);
+
+	/* write new values */
+	printf("\nSRom:  Writing revision info ...... ");
+	if (el_srom_store((BLOCK_SIZE-sizeof(revinfo)), (u_char *)&eerev,
+			    sizeof(revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
+	    printf("FAILED\n\n");
+	else
+	    printf("OK\n\n");
+
+	/* write new values as shadow image to nvram */
+	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
+
+    } /*if (initSrom) */
+
+    /* copy current values as shadow image to nvram */
+    if (initSrom == 0 && copyNv == 1)
+	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
+
+    /* update environment */
+    sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+	    eerev.etheraddr[0], eerev.etheraddr[1],
+	    eerev.etheraddr[2], eerev.etheraddr[3],
+	    eerev.etheraddr[4], eerev.etheraddr[5]);
+    setenv ("ethaddr", buf);
+
+    /* print actual board identification */
+    printf("Ident: %s  Ser %s  Rev %c%c\n",
+	    eerev.board, (char *)&eerev.serial,
+	    eerev.revision[0][0], eerev.revision[0][1]);
+
+    /* global board ident */
+    if (strstr ((char *)&eerev.board, "75") != NULL)
+	eltec_board = 750;
+    else
+	eltec_board = 740;
+
+   /*
+    * L2 cache configuration
+    */
+#if defined(CFG_L2_BAB7xx)
+    ptr = getenv("l2cache");
+    if (*ptr == '0')
+    {
+	printf ("Cache: L2 NOT activated on BAB%d\n", eltec_board);
+    }
+    else
+    {
+	printf ("Cache: L2 activated on BAB%d\n", eltec_board);
+	l2_cache_enable(*(int*)&eerev.res[0]);
+    }
+#endif
+
+   /*
+    * Reconfig ata reset timeout from environment
+    */
+    if ((ptr = getenv ("ata_reset_time")) != NULL)
+    {
+	ata_reset_time = (int)simple_strtoul (ptr, NULL, 10);
+    }
+    else
+    {
+	sprintf (buf, "%d", ata_reset_time);
+	setenv ("ata_reset_time", buf);
+    }
+
+   /*
+    * Reconfig scsi reset timeout from environment
+    */
+    if ((ptr = getenv ("scsi_reset_time")) != NULL)
+    {
+	scsi_reset_time = (int)simple_strtoul (ptr, NULL, 10);
+    }
+    else
+    {
+	sprintf (buf, "%d", scsi_reset_time);
+	setenv ("scsi_reset_time", buf);
+    }
+
+
+    if ((bdf = pci_find_device(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, 0)) > 0)
+    {
+	if (pci_find_device(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, 0) > 0)
+	{
+	    /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 Mhz */
+	    scsi_dev_id = PCI_DEVICE_ID_NCR_53C860;
+	    scsi_max_scsi_id = 7;
+	    scsi_sym53c8xx_ccf = 0x15;
+	    pci_write_config_byte (bdf, WINBOND_IDEIRCR, 0xb0);
+	}
+
+	if ((ptr = getenv ("ide_dma_off")) != NULL)
+	{
+	    u_long dma_off = simple_strtoul (ptr, NULL, 10);
+	    /*
+	    * setup user defined registers
+	    * s.a. linux/drivers/ide/sl82c105.c
+	    */
+	    bdf |= PCI_BDF(0,0,1);            /* ide user reg at bdf function 1 */
+	    if (dma_off & 1)
+	    {
+		pci_write_config_byte (bdf, 0x46, 1);
+		printf("IDE:   DMA off flag set: Bus 0 : Dev 0\n");
+	    }
+	    if (dma_off & 2)
+	    {
+		pci_write_config_byte (bdf, 0x4a, 1);
+		printf("IDE:   DMA off flag set: Bus 0 : Dev 1\n");
+	    }
+	    if (dma_off & 4)
+	    {
+		pci_write_config_byte (bdf, 0x4e, 1);
+		printf("IDE:   DMA off flag set: Bus 1 : Dev 0\n");
+	    }
+	    if (dma_off & 8)
+	    {
+		pci_write_config_byte (bdf, 0x52, 1);
+		printf("IDE:   DMA off flag set: Bus 1 : Dev 1\n");
+	    }
+	}
+    }
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * BAB740 uses KENDIN KS8761 modem chip with not common setup values
+ */
+#ifdef CONFIG_TULIP_SELECT_MEDIA
+
+/* Register bits.
+ */
+#define BMR_SWR         0x00000001      /* Software Reset */
+#define STS_TS          0x00700000      /* Transmit Process State */
+#define STS_RS          0x000e0000      /* Receive Process State */
+#define OMR_ST          0x00002000      /* Start/Stop Transmission Command */
+#define OMR_SR          0x00000002      /* Start/Stop Receive */
+#define OMR_PS          0x00040000      /* Port Select */
+#define OMR_SDP         0x02000000      /* SD Polarity - MUST BE ASSERTED */
+#define OMR_PM          0x00000080      /* Pass All Multicast */
+#define OMR_PR          0x00000040      /* Promiscuous Mode */
+#define OMR_PCS         0x00800000      /* PCS Function */
+#define OMR_TTM         0x00400000      /* Transmit Threshold Mode */
+
+/* Ethernet chip registers.
+ */
+#define DE4X5_BMR       0x000           /* Bus Mode Register */
+#define DE4X5_TPD       0x008           /* Transmit Poll Demand Reg */
+#define DE4X5_RRBA      0x018           /* RX Ring Base Address Reg */
+#define DE4X5_TRBA      0x020           /* TX Ring Base Address Reg */
+#define DE4X5_STS       0x028           /* Status Register */
+#define DE4X5_OMR       0x030           /* Operation Mode Register */
+#define DE4X5_SISR      0x060           /* SIA Status Register */
+#define DE4X5_SICR      0x068           /* SIA Connectivity Register */
+#define DE4X5_TXRX      0x070           /* SIA Transmit and Receive Register */
+#define DE4X5_GPPR      0x078           /* General Purpose Port register */
+#define DE4X5_APROM      0x048          /* Ethernet Address PROM */
+
+/*----------------------------------------------------------------------------*/
+
+static int INL(struct eth_device* dev, u_long addr)
+{
+    return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void OUTL(struct eth_device* dev, int command, u_long addr)
+{
+    *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static void media_reg_init (
+    struct eth_device* dev,
+    u32 csr14,
+    u32 csr15_dir,
+    u32 csr15_v0,
+    u32 csr15_v1,
+    u32 csr6 )
+{
+    OUTL(dev, 0, DE4X5_OMR);            /* CSR6  */
+    udelay(10 * 1000);
+    OUTL(dev, 0, DE4X5_SICR);           /* CSR13 */
+    OUTL(dev, 1, DE4X5_SICR);           /* CSR13 */
+    udelay(10 * 1000);
+    OUTL(dev, csr14, DE4X5_TXRX);       /* CSR14 */
+    OUTL(dev, csr15_dir, DE4X5_GPPR);   /* CSR15 */
+    OUTL(dev, csr15_v0,  DE4X5_GPPR);   /* CSR15 */
+    udelay(10 * 1000);
+    OUTL(dev, csr15_v1,  DE4X5_GPPR);   /* CSR15 */
+    OUTL(dev, 0x00000301, DE4X5_SISR);  /* CSR12 */
+    OUTL(dev, csr6, DE4X5_OMR);         /* CSR6 */
+}
+
+/*----------------------------------------------------------------------------*/
+
+void dc21x4x_select_media(struct eth_device* dev)
+{
+    int i, status, ext;
+    extern unsigned int eltec_board;
+
+    if (eltec_board == 740)
+    {
+	printf("SYM media select "); /* BAB740 */
+	/* start autoneg. with 10 mbit */
+	media_reg_init (dev, 0x3ffff, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400080);
+	ext = status = 0;
+	for (i=0; i<2000+ext; i++)
+	{
+	    status = INL(dev, DE4X5_SISR);
+	    udelay(1000);
+	    if (status & 0x2000) ext = 2000;
+	    if ((status & 0x7000) == 0x5000) break;
+	}
+
+	/* autoneg. ok -> 100MB FD */
+	if ((status & 0x0100f000) == 0x0100d000)
+	{
+	    media_reg_init (dev, 0x37f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40280);
+	    printf("100baseTx-FD\n");
+	}
+	/* autoneg. ok -> 100MB HD */
+	else if ((status & 0x0080f000) == 0x0080d000)
+	{
+	    media_reg_init (dev, 0x17f7f, 0x08270008, 0x00210008, 0x00250008, 0x03c40080);
+	    printf("100baseTx\n");
+	}
+	/* autoneg. ok -> 10MB FD */
+	else if ((status & 0x0040f000) == 0x0040d000)
+	{
+	    media_reg_init (dev, 0x07f7f, 0x08af0008, 0x00a10008, 0x00a50008, 0x02400280);
+	    printf("10baseT-FD\n");
+	}
+	/* autoneg. fail -> 10MB HD */
+	else
+	{
+	    media_reg_init (dev, 0x7f7f, 0x08af0008, 0x00a10008, 0x00a50008,
+			(OMR_SDP | OMR_TTM | OMR_PM));
+	    printf("10baseT\n");
+	}
+    }
+    else
+    {
+	printf("MII media selected\n");                     /* BAB750 */
+	OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);    /* CSR6 */
+    }
+}
+#endif /* CONFIG_TULIP_SELECT_MEDIA */
+
+/*---------------------------------------------------------------------------*/
diff --git a/board/eltec/bab7xx/pci.c b/board/eltec/bab7xx/pci.c
new file mode 100755
index 0000000..edbd3dd
--- /dev/null
+++ b/board/eltec/bab7xx/pci.c
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+    struct pci_controller* hose = (struct pci_controller *)&local_hose;
+    u32 reg32;
+    u16 reg16;
+
+    hose->first_busno = 0;
+    hose->last_busno = 0xff;
+
+    pci_set_region(hose->regions + 0,
+	CFG_PCI_MEMORY_BUS,
+	CFG_PCI_MEMORY_PHYS,
+    /*
+    * Attention: pci_hose_phys_to_bus() failes in address compare,
+    * so we need (CFG_PCI_MEMORY_SIZE-1)
+    */
+	CFG_PCI_MEMORY_SIZE-1,
+	PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+    /* PCI memory space */
+    pci_set_region(hose->regions + 1,
+	CFG_PCI_MEM_BUS,
+	CFG_PCI_MEM_PHYS,
+	CFG_PCI_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* ISA/PCI memory space */
+    pci_set_region(hose->regions + 2,
+	CFG_ISA_MEM_BUS,
+	CFG_ISA_MEM_PHYS,
+	CFG_ISA_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* PCI I/O space */
+    pci_set_region(hose->regions + 3,
+	CFG_PCI_IO_BUS,
+	CFG_PCI_IO_PHYS,
+	CFG_PCI_IO_SIZE,
+	PCI_REGION_IO);
+
+    /* ISA/PCI I/O space */
+    pci_set_region(hose->regions + 4,
+	CFG_ISA_IO_BUS,
+	CFG_ISA_IO_PHYS,
+	CFG_ISA_IO_SIZE,
+	PCI_REGION_IO);
+
+    hose->region_count = 5;
+
+    pci_setup_indirect(hose,
+	MPC106_REG_ADDR,
+	MPC106_REG_DATA);
+
+    pci_register_hose(hose);
+
+    hose->last_busno = pci_hose_scan(hose);
+
+    /* Initialises the MPC10x PCI Configuration regs. */
+    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, &reg32);
+    reg32 |= PICR2_CF_SNOOP_WS(3) |
+	     PICR2_CF_FLUSH_L2 |
+	     PICR2_CF_L2_HIT_DELAY(3) |
+	     PICR2_CF_APHASE_WS(3);
+    reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN);
+    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32);
+
+    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+    /* Clear non-reserved bits in status register */
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+
+    pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, &reg32);
+    reg32 |= PICR1_CF_CBA(63) |
+	     PICR1_CF_BREAD_WS(2) |
+	     PICR1_MCP_EN |
+	     PICR1_CF_DPARK |
+	     PICR1_PROC_TYPE_604 |
+	     PICR1_CF_LOOP_SNOOP |
+	     PICR1_CF_APARK;
+    pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/board/eltec/bab7xx/srom.h b/board/eltec/bab7xx/srom.h
new file mode 100755
index 0000000..c18ab91
--- /dev/null
+++ b/board/eltec/bab7xx/srom.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* common srom defs */
+#define FIRST_DEVICE            0x00
+#define SECOND_DEVICE           0x04
+#define FIRST_BLOCK             0x00
+#define SECOND_BLOCK            0x02
+#define BLOCK_SIZE              0x100
+#define ERROR                   (-1)
+
+#define CLK2P0TO1_1MB_PB_0P5DH  0x79000100
+#define CLK2P5TO1_1MB_PB_0P5DH  0x7B000100
+
+#define CPU_TYPE_740            0x08
+#define CPU_TYPE_750            0x08
+#define CPU_TYPE                ((get_pvr()>>16)&0xffff)
+
+#define ABS(x)                  ((x<0)?-x:x)
+#define SROM_SHORT(pX)          (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
+
+/* bab7xx ELTEC srom */
+#define I2C_BUS_DAT             (CFG_ISA_IO + 0x220)
+#define I2C_BUS_DIR             (CFG_ISA_IO + 0x221)
+
+/* srom at mpc107 */
+#define MPC107_I2CADDR          (mpc107_eumb_addr + 0x3000)     /* address      */
+#define MPC107_I2CFDR           (mpc107_eumb_addr + 0x3004)     /* freq divider */
+#define MPC107_I2CCR            (mpc107_eumb_addr + 0x3008)     /* control      */
+#define MPC107_I2CSR            (mpc107_eumb_addr + 0x300c)     /* status       */
+#define MPC107_I2CDR            (mpc107_eumb_addr + 0x3010)     /* data         */
+#define MPC107_I2C_TIMEOUT      10000000
+
+/* i82559 */
+#define EE_ADDR_BITS            6
+#define EE_SIZE                 0x40                            /* 0x40 words */
+#define EE_CHECKSUM             0xBABA
+
+/* dc21143 */
+#define DEC_SROM_SIZE           128
+
+
+/*
+ * structure of revision srom
+ */
+typedef struct  {
+    char    magic[8];           /* 000 - Magic number */
+    char    revrev[2];          /* 008 - Revision of structure */
+    unsigned short size;        /* 00A - Size of CRC area */
+    unsigned long  crc;         /* 00C - CRC */
+    char    board[16];          /* 010 - Board Revision information */
+    char    option[4][16];      /* 020 - Option Revision information */
+    char    serial[8];          /* 060 - Board serial number */
+    char    etheraddr[6];       /* 068 - Ethernet node addresse */
+    char    reserved[2];        /* 06E - Reserved */
+    char    revision[7][2];     /* 070 - Revision codes */
+    char    category[2];        /* 07E - Category codes */
+    char    text[64];           /* 080 - Text field */
+    char    res[64];            /* 0C0 - Reserved */
+} revinfo;
+
+unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size);
+int el_srom_load  (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+int el_srom_store (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+
+int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider);
+int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset);
+int mpc107_i2c_write_byte (unsigned char device, unsigned char block,
+			   unsigned char offset, unsigned char val);
+int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt,
+		      unsigned char device, unsigned char block);
+int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt,
+		       unsigned char device, unsigned char block);
+
+int dc_srom_load (unsigned short *dest);
+int dc_srom_store (unsigned short *src);
+
+unsigned short eepro100_srom_checksum (unsigned short *sromdata);
+void eepro100_srom_load (unsigned short *destination);
+int  eepro100_srom_store (unsigned short *source);
diff --git a/board/eltec/bab7xx/u-boot.lds b/board/eltec/bab7xx/u-boot.lds
new file mode 100755
index 0000000..d89eb6c
--- /dev/null
+++ b/board/eltec/bab7xx/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile
new file mode 100755
index 0000000..76b2cfe
--- /dev/null
+++ b/board/eltec/elppc/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o
+
+SOBJS	= asm_init.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@  $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S
new file mode 100755
index 0000000..1b8d399
--- /dev/null
+++ b/board/eltec/elppc/asm_init.S
@@ -0,0 +1,878 @@
+/*
+ * (C) Copyright 2001 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * ELTEC ELPPC RAM initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/processor.h>
+#include <version.h>
+#include <mpc106.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+.globl board_asm_init
+board_asm_init:
+
+/*
+ * setup pointer to message block
+ */
+    mflr    r13                 /* save away link register */
+    bl      get_lnk_reg         /* r3=addr of next instruction */
+    subi    r4, r3, 8           /* r4=board_asm_init addr */
+    addi    r29, r4, (MessageBlock-board_asm_init)
+
+/*
+ * dcache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, HID0_DCE
+    andc    r3, r3, r4
+    mr      r2, r3
+    ori     r3, r3, HID0_DCI
+    sync
+    mtspr   HID0, r3
+    mtspr   HID0, r2
+    isync
+    sync
+/*
+ * icache_disable
+ */
+    mfspr   r3, HID0
+    li      r4, 0
+    ori     r4, r4, HID0_ICE
+    andc    r3, r3, r4
+    sync
+    mtspr   HID0, r3
+/*
+ * invalidate caches
+ */
+    ori     r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE)
+    or      r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    andc    r4, r4, r3
+    isync
+    mtspr   HID0, r4
+    isync
+/*
+ * icache_enable
+ */
+    mfspr   r3, HID0
+    ori     r3, r3, (HID0_ICE | HID0_ICFI)
+    sync
+    mtspr   HID0, r3
+
+
+/*
+ * setup memory controller
+ */
+    lis     r1, MPC106_REG_ADDR@h
+    ori     r1, r1, MPC106_REG_ADDR@l
+    lis     r2, MPC106_REG_DATA@h
+    ori     r2, r2, MPC106_REG_DATA@l
+
+    /* Configure PICR1 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, PCI_PICR1
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFF14
+    ori     r3, r3, 0x1CC8
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure PICR2 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, PCI_PICR2
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0000
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure EUMBAR */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, 0x0078      /* offest of EUMBAR in PCI config space */
+    stwbrx  r3, 0, r1
+    lis     r3, MPC107_EUMB_ADDR@h
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure Address Map B Option Reg */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, 0x00e0      /* offest of AMBOR in PCI config space */
+    stwbrx  r3, 0, r1
+    lis     r3, 0
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure I2C Controller */
+    lis     r14, MPC107_I2C_ADDR@h  /* base of I2C controller */
+    ori     r14, r14, MPC107_I2C_ADDR@l
+    lis     r3, 0x2b10          /* I2C clock = 100MHz/1024 */
+    stw     r3, 4(r14)
+    li      r3, 0               /* clear arbitration */
+    eieio
+    stw     r3, 12(r14)
+
+    /* Configure MCCR1 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR1
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0660      /* don't set MEMGO now ! */
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure MCCR2 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR2
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0400
+    ori     r3, r3, 0x1800
+    eieio
+    stwbrx  r3, 0, r2
+
+
+    /* Configure MCCR3 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR3
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0230
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    /* Configure MCCR4 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR4
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x2532
+    ori     r3, r3, 0x2220
+    eieio
+    stwbrx  r3, 0, r2
+
+/*
+ * configure memory interface (MICRs)
+ */
+    addis   r3, r0, 0x8000      /* ADDR_80 */
+    ori     r3, r3, 0x0080      /* SMEMADD1 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFFFF
+    ori     r3, r3, 0x4000
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_84 */
+    ori     r3, r3, 0x0084      /* SMEMADD2 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFFFF
+    ori     r3, r3, 0xFFFF
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_88 */
+    ori     r3, r3, 0x0088      /* EXTSMEM1 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0303
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_8C */
+    ori     r3, r3, 0x008c      /* EXTSMEM2 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0303
+    ori     r3, r3, 0x0303
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_90 */
+    ori     r3, r3, 0x0090      /* EMEMADD1 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFFFF
+    ori     r3, r3, 0x7F3F
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_94 */
+    ori     r3, r3, 0x0094      /* EMEMADD2 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0xFFFF
+    ori     r3, r3, 0xFFFF
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_98 */
+    ori     r3, r3, 0x0098      /* EXTEMEM1 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0303
+    ori     r3, r3, 0x0000
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_9C */
+    ori     r3, r3, 0x009c      /* EXTEMEM2 */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0303
+    ori     r3, r3, 0x0303
+    eieio
+    stwbrx  r3, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_A0 */
+    ori     r3, r3, 0x00a0      /* MEMBNKEN */
+    stwbrx  r3, 0, r1
+    addis   r3, r0, 0x0000
+    ori     r3, r3, 0x0003
+    eieio
+    stwbrx  r3, 0, r2
+
+/*
+ * must wait at least 100us after HRESET to issue a MEMGO
+ */
+    lis     r0, 1
+    mtctr   r0
+memStartWait:
+    bdnz    memStartWait
+
+/*
+ * enable RAM Operations through MCCR1 (MEMGO)
+ */
+    lis     r3, 0x8000
+    ori     r3, r3, 0x00f0
+    stwbrx  r3, r0, r1
+    sync
+    lwbrx   r3, 0, r2
+    lis     r0, 0x0008
+    or      r3, r0, r3
+    stwbrx  r3, 0, r2
+    sync
+
+/*
+ * set LEDs first time
+ */
+    li      r3, 0x1
+    lis     r30, CFG_USR_LED_BASE@h
+    stb     r3, 2(r30)
+    sync
+
+/*
+ * init COM1 for polled output
+ */
+    lis     r8, CFG_NS16550_COM1@h  /* COM1 base address*/
+    ori     r8, r8, CFG_NS16550_COM1@l
+    li      r9, 0x00
+    stb     r9, 1(r8)           /* int disabled */
+    eieio
+    li      r9, 0x00
+    stb     r9, 4(r8)           /* modem ctrl */
+    eieio
+    li      r9, 0x80
+    stb     r9, 3(r8)           /* link ctrl */
+    eieio
+    li      r9, (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE)
+    stb     r9, 0(r8)           /* baud rate (LSB)*/
+    eieio
+    li      r9, ((CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8)
+    stb     r9, 1(r8)           /* baud rate (MSB) */
+    eieio
+    li      r9, 0x07
+    stb     r9, 3(r8)           /* 8 data bits, 2 stop bit, no parity */
+    eieio
+    li      r9, 0x0b
+    stb     r9, 4(r8)           /* enable the receiver and transmitter (modem ctrl) */
+    eieio
+waitEmpty:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty
+    li      r9, 0x47
+    stb     r9, 3(r8)           /* send break, 8 data bits, 2 stop bit, no parity */
+    eieio
+
+    lis     r0, 0x0001
+    mtctr   r0
+waitCOM1:
+    lwz     r0, 5(r8)           /* load from port for delay */
+    bdnz    waitCOM1
+
+waitEmpty1:
+    lbz     r9, 5(r8)           /* transmit empty */
+    andi.   r9, r9, 0x40
+    beq     waitEmpty1
+    li      r9, 0x07
+    stb     r9, 3(r8)           /* 8 data bits, 2 stop bit, no parity */
+    eieio
+
+/*
+ * intro message from message block
+ */
+    addi    r3, r29, (MnewLine-MessageBlock)
+    bl      Printf
+    addi    r3, r29, (MinitLogo-MessageBlock)
+    bl      Printf
+
+/*
+ * memory cofiguration using SPD information stored on the SODIMMs
+ */
+    addi    r3, r29, (Mspd01-MessageBlock)
+    bl      Printf
+
+    li      r17, 0
+
+    li      r3, 0x0002          /* get RAM type from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, -1        /* error ? */
+    bne     noSpdError
+
+    addi    r3, r29, (Mfail-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xe             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+
+noSpdError:
+    mr      r15, r3             /* save r3 */
+
+    addi    r3, r29, (Mok-MessageBlock)
+    bl      Printf
+
+    cmpli   0, 0, r15, 0x0004   /* SDRAM ? */
+    beq     isSDRAM
+
+    addi    r3, r29, (MramTyp-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xd             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+
+isSDRAM:
+    li      r3, 0x0012          /* get supported CAS latencies from byte 18 */
+    bl      spdRead
+    mr      r15, r3
+    li      r3, 0x09
+    andi.   r0, r15, 0x04
+    bne     maxCLis3
+    li      r3, 0x17
+maxCLis3:
+    andi.   r0, r15, 0x02
+    bne     CL2
+
+    addi    r3, r29, (MramTyp-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xc             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+CL2:
+    bl      spdRead
+    cmpli   0, 0, r3, 0xa1      /* cycle time must be 10ns max. */
+    blt     speedOk
+
+    addi    r3, r29, (MramTyp-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xb             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+speedOk:
+    lis     r20, 0x06e8         /* preset MCR1 value */
+
+    li      r3, 0x0011          /* get number of internal banks from spd for bank0/1 */
+    bl      spdRead
+
+    cmpli   0, 0, r3, 0x02
+    beq     SD_2B
+    cmpli   0, 0, r3, 0x04
+    beq     SD_4B
+memConfErr:
+    addi    r3, r29, (MramConfErr-MessageBlock)
+    bl      Printf
+
+    li      r6, 0xa             /* error codes in r6 and r7  */
+    li      r7, 0x0
+    b       toggleError         /* fail - loop forever */
+
+SD_2B:
+    li      r3, 0x0003          /* get number of row bits from spd for bank0/1 */
+    bl      spdRead
+    cmpli   0, 0, r3, 0x0b
+    beq     row11x2
+    cmpli   0, 0, r3, 0x0c
+    beq     row12x2or13x2
+    cmpli   0, 0, r3, 0x0d
+    beq     row12x2or13x2
+    b       memConfErr
+SD_4B:
+    li      r3, 0x0003          /* get number of row bits from spd for bank0/1 */
+    bl      spdRead
+    cmpli   0, 0, r3, 0x0b
+    beq     row11x4or12x4
+    cmpli   0, 0, r3, 0x0c
+    beq     row11x4or12x4
+    cmpli   0, 0, r3, 0x0d
+    beq     row13x4
+    b       memConfErr
+row12x2or13x2:
+    ori     r20, r20, 0x05
+    b       row11x4or12x4
+row13x4:
+    ori     r20, r20, 0x0a
+    b       row11x4or12x4
+row11x2:
+    ori     r20, r20, 0x0f
+row11x4or12x4:
+    /* get the size of bank 0-1 */
+
+    li      r3, 0x001f          /* get bank size from spd for bank0/1 */
+    bl      spdRead
+
+    rlwinm  r16, r3, 2, 24, 29  /* calculate size in MByte (128 MB max.) */
+
+    li      r3, 0x0005          /* get number of banks from spd for bank0/1 */
+    bl      spdRead
+
+    cmpi    0, 0, r3, 2         /* 2 banks ? */
+    bne     SDRAMnobank1
+
+    mr      r17, r16
+
+SDRAMnobank1:
+    li      r3, 0x000c          /* get refresh from spd for bank0/1 */
+    bl      spdRead
+    andi.   r3, r3, 0x007f      /* mask selfrefresh bit */
+    li      r4, 0x1800          /* refesh cycle 1536 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0000    /* 15.6 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x0c00          /* refesh cycle 768 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0002    /* 7.8 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x3000          /* refesh cycle 3072 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0003    /* 31.3 us ? */
+    beq     writeRefresh
+
+    li      r4, 0x6000          /* refesh cycle 6144 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0004    /* 62.5 us ? */
+    beq     writeRefresh
+
+    li      r4, 0
+    ori     r4, r4, 0xc000      /* refesh cycle 8224 clocks left shifted 2 */
+    cmpli   0, 0, r3, 0x0005    /* 125 us ? */
+    beq     writeRefresh
+
+    b       memConfErr
+
+writeRefresh:
+    lis     r21, 0x0400         /* preset MCCR2 value */
+    or      r21, r21, r4
+
+    /* Overwrite MCCR1 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR1
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r20, 0, r2
+
+    /* Overwrite MCCR2 */
+    lis     r3, MPC106_REG@h
+    ori     r3, r3, MPC106_MCCR2
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r21, 0, r2
+
+    /* set the memory boundary registers for bank 0-3 */
+    li      r20, 0
+    lis     r23, 0x0303
+    lis     r24, 0x0303
+    subi    r21, r16, 1         /* calculate end address bank0 */
+    li      r22, 1
+
+    cmpi    0, 0, r17, 0        /* bank1 present ? */
+    beq     nobank1
+
+    andi.   r3, r16, 0x00ff     /* calculate start address of bank1 */
+    andi.   r4, r16, 0x0300
+    rlwinm  r3, r3, 8, 16, 23
+    or      r20, r20, r3
+    or      r23, r23, r4
+
+    add     r16, r16, r17       /* add to total memory size */
+
+    subi    r3, r16, 1          /* calculate end address of bank1 */
+    andi.   r4, r3, 0x0300
+    andi.   r3, r3, 0x00ff
+    rlwinm  r3, r3, 8, 16, 23
+    or      r21, r21, r3
+    or      r24, r24, r4
+
+    ori     r22, r22, 2         /* enable bank1 */
+    b       bankOk
+nobank1:
+    ori     r23, r23, 0x0300    /* set bank1 start to unused area */
+    ori     r24, r24, 0x0300    /* set bank1 end to unused area */
+bankOk:
+    addi    r3, r29, (Mactivate-MessageBlock)
+    bl      Printf
+    mr      r3, r16
+    bl      OutDec
+    addi    r3, r29, (Mact0123e-MessageBlock)
+    bl      Printf
+
+/*
+ * overwrite MSAR1, MEAR1, EMSAR1, and EMEAR1
+ */
+    addis   r3, r0, 0x8000      /* ADDR_80 */
+    ori     r3, r3, 0x0080      /* MSAR1 */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r20, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_88 */
+    ori     r3, r3, 0x0088      /* EMSAR1 */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r23, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_90 */
+    ori     r3, r3, 0x0090      /* MEAR1 */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r21, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_98 */
+    ori     r3, r3, 0x0098      /* EMEAR1 */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r24, 0, r2
+
+    addis   r3, r0, 0x8000      /* ADDR_A0 */
+    ori     r3, r3, 0x00a0      /* MBER */
+    stwbrx  r3, 0, r1
+    eieio
+    stwbrx  r22, 0, r2
+
+/*
+ * delay to let SDRAM go through several initialization/refresh cycles
+ */
+    lis     r3, 3
+    mtctr   r3
+memStartWait_1:
+    bdnz    memStartWait_1
+    eieio
+
+/*
+ * set LEDs end
+ */
+    li      r3, 0xf
+    lis     r30, CFG_USR_LED_BASE@h
+    stb     r3, 2(r30)
+    sync
+
+    mtlr    r13
+    blr                         /* EXIT board_asm_init ... */
+
+/*----------------------------------------------------------------------------*/
+/*
+ * print a message to COM1 in polling mode (r10=COM1 port, r3=(char*)string)
+ */
+
+Printf:
+    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CFG_NS16550_COM1@l
+WaitChr:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, WaitChr        /* wait till empty */
+    lbzx    r0, r0, r3          /* get char */
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addi    r3, r3, 1           /* next char */
+    lbzx    r0, r0, r3          /* get char */
+    cmpwi   cr1, r0, 0          /* end of string ? */
+    bne     cr1, WaitChr
+    blr
+
+/*
+ * print a char to COM1 in polling mode (r10=COM1 port, r3=char)
+ */
+OutChr:
+    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CFG_NS16550_COM1@l
+OutChr1:
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutChr1        /* wait till empty */
+    stb     r3, 0(r10)          /* write to transmit reg */
+    eieio
+    blr
+
+/*
+ * print 8/4/2 digits hex value to COM1 in polling mode (r10=COM1 port, r3=val)
+ */
+OutHex2:
+    li      r9, 4               /* shift reg for 2 digits */
+    b       OHstart
+OutHex4:
+    li      r9, 12              /* shift reg for 4 digits */
+    b       OHstart
+OutHex:
+    li      r9, 28              /* shift reg for 8 digits */
+OHstart:
+    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CFG_NS16550_COM1@l
+OutDig:
+    lbz     r0, 0(r29)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDig
+    sraw    r0, r3, r9
+    clrlwi  r0, r0, 28
+    cmpwi   cr1, r0, 9
+    ble     cr1, digIsNum
+    addic   r0, r0, 55
+    b       nextDig
+digIsNum:
+    addic   r0, r0, 48
+nextDig:
+    stb     r0, 0(r10)          /* write to transmit reg */
+    eieio
+    addic.  r9, r9, -4
+    bge     OutDig
+    blr
+
+/*
+ * print 3 digits hdec value to COM1 in polling mode
+ * (r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch)
+ */
+OutDec:
+    li      r6, 10
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r9 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r9, r10, r3
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r8 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r8, r10, r3
+    mr      r3, r0
+    divwu   r0, r3, r6          /* r0 = r3 / 10, r7 = r3 mod 10 */
+    mullw   r10, r0, r6
+    subf    r7, r10, r3
+    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CFG_NS16550_COM1@l
+    or.     r7, r7, r7
+    bne     noblank1
+    li      r3, 0x20
+    b       OutDec4
+noblank1:
+    addi    r3, r7, 48          /* convert to ASCII */
+OutDec4:
+    lbz     r0, 0(r29)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec4
+    stb     r3, 0(r10)          /* x00 to transmit */
+    eieio
+    or.     r7, r7, r8
+    beq     OutDec5
+    addi    r3, r8, 48          /* convert to ASCII */
+OutDec5:
+    lbz     r0, 0(r29)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec5
+    stb     r3, 0(r10)          /* x0  to transmit */
+    eieio
+    addi    r3, r9, 48          /* convert to ASCII */
+OutDec6:
+    lbz     r0, 0(r29)          /* slow down dummy read */
+    lbz     r0, 5(r10)          /* read link status */
+    eieio
+    andi.   r0, r0, 0x40        /* mask transmitter empty bit */
+    beq     cr0, OutDec6
+    stb     r3, 0(r10)          /* x   to transmit */
+    eieio
+    blr
+
+/*
+ * hang endless loop
+ */
+toggleError:                    /* fail type in r6, r7=0xff, toggle LEDs */
+    stb     r7, 2(r30)          /* r7 to LED */
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError1:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError1
+    stb     r6, 2(r30)          /* r6 to LED */
+    li      r0, 0
+    lis     r9, 127
+    ori     r9, r9, 65535
+toggleError2:
+    addic   r0, r0, 1
+    cmpw    cr1, r0, r9
+    ble     cr1, toggleError2
+    b       toggleError
+
+/*
+ * routines to read from ram spd
+ */
+spdWaitIdle:
+    lis     r0, 0x1             /* timeout for about 100us */
+    mtctr   r0
+iSpd:
+    lbz     r10, 12(r14)
+    andi.   r10, r10, 0x20      /* mask and test MBB */
+    beq     idle
+    bdnz    iSpd
+    orc.    r10, r0, r0         /* return -1 to caller */
+idle:
+    bclr    20, 0               /* return to caller */
+
+waitSpd:
+    lis     r0, 0x10            /* timeout for about 1.5ms */
+    mtctr   r0
+wSpd:
+    lbz     r10, 12(r14)
+    andi.   r10, r10, 0x82
+    cmpli   0, 0, r10, 0x82     /* test MCF and MIF set */
+    beq     wend
+    bdnz    wSpd
+    orc.    r10, r0, r0         /* return -1 to caller */
+    bclr    20, 0               /* return to caller */
+
+wend:
+    li      r10, 0
+    stb     r10, 12(r14)        /* clear status */
+    bclr    20, 0               /* return to caller */
+
+/*
+ * spdread
+ * in:  r3 adr to read
+ * out: r3 val or -1 for error
+ * uses r10, assumes that r14 points to I2C controller
+ */
+spdRead:
+    mfspr   r25, 8              /* save link register */
+
+    bl      spdWaitIdle
+    bne     spdErr
+
+    li      r10, 0x80           /* start with MEN */
+    stb     r10, 8(r14)
+    eieio
+
+    li      r10, 0xb0           /* start as master */
+    stb     r10, 8(r14)
+    eieio
+
+    li      r10, 0xa0           /* write device 0xA0 */
+    stb     r10, 16(r14)
+    eieio
+    bl      waitSpd
+    bne     spdErr
+
+    lbz     r10, 12(r14)        /* test ACK */
+    andi.   r10, r10, 0x01
+    bne     gotNoAck
+
+    stb     r3, 16(r14)         /* data address */
+    eieio
+    bl      waitSpd
+    bne     spdErr
+
+
+    li      r10, 0xb4           /* switch to read - restart */
+    stb     r10, 8(r14)
+    eieio
+
+    li      r10, 0xa1           /* read device 0xA0 */
+    stb     r10, 16(r14)
+    eieio
+    bl      waitSpd
+    bne     spdErr
+
+    li      r10, 0xa8           /* no ACK */
+    stb     r10, 8(r14)
+    eieio
+
+    lbz     r10, 16(r14)        /* trigger read next byte */
+    eieio
+    bl      waitSpd
+    bne     spdErr
+
+    li      r10, 0x88           /* generate STOP condition */
+    stb     r10, 8(r14)
+    eieio
+
+    lbz     r3, 16(r14)         /* return read byte */
+
+    mtspr   8, r25              /* restore link register */
+    blr
+
+gotNoAck:
+    li      r10, 0x80           /* generate STOP condition */
+    stb     r10, 8(r14)
+    eieio
+spdErr:
+    orc     r3, r0, r0          /* return -1 */
+    mtspr   8, r25              /* restore link register */
+    blr
+
+get_lnk_reg:
+    mflr    r3                  /* return link reg */
+    blr
+
+MessageBlock:
+
+MinitLogo:
+    .ascii  "\015\012*** ELTEC Elektronik, Mainz ***\015\012"
+    .ascii  "\015\012Initialising RAM\015\012\000"
+Mspd01:
+    .ascii  "       Reading SPD of SODIMM ...... \000"
+MramTyp:
+    .ascii  "\015\012\SDRAM with CL=2 at 100 MHz required!\015\012\000"
+MramConfErr:
+    .ascii  "\015\012\Unsupported SODIMM Configuration!\015\012\000"
+Mactivate:
+    .ascii  "       Activating \000"
+Mact0123e:
+    .ascii  " MByte.\015\012\000"
+Mok:
+    .ascii  "OK \015\012\000"
+Mfail:
+    .ascii  "FAILED \015\012\000"
+MnewLine:
+    .ascii  "\015\012\000"
+    .align 4
diff --git a/board/eltec/elppc/config.mk b/board/eltec/elppc/config.mk
new file mode 100755
index 0000000..aa463c5
--- /dev/null
+++ b/board/eltec/elppc/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/eltec/elppc/eepro100_srom.c b/board/eltec/elppc/eepro100_srom.c
new file mode 100755
index 0000000..f021c50
--- /dev/null
+++ b/board/eltec/elppc/eepro100_srom.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Local network srom writing for first time run
+ */
+
+/* includes */
+#include <common.h>
+#include <pci.h>
+#include <net.h>
+#include "srom.h"
+
+extern int eepro100_write_eeprom (struct eth_device* dev,
+		    int location, int addr_len, unsigned short data);
+
+/*----------------------------------------------------------------------------*/
+
+unsigned short eepro100_srom_checksum (unsigned short *sromdata)
+{
+    unsigned short sum = 0;
+    unsigned int i;
+
+    for (i = 0; i < (EE_SIZE-1); i++)
+    {
+	sum += sromdata[i];
+    }
+    return (EE_CHECKSUM - sum);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int eepro100_srom_store (unsigned short *source)
+{
+    int count;
+    struct eth_device onboard_dev;
+
+    /* get onboard network iobase */
+    pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0,
+		 (unsigned int *)&onboard_dev.iobase);
+    onboard_dev.iobase &= ~0xf;
+
+    source[63] = eepro100_srom_checksum (source);
+
+    for (count=0; count < EE_SIZE; count++)
+    {
+    if ( eepro100_write_eeprom ((struct eth_device*)&onboard_dev,
+	     count, EE_ADDR_BITS, SROM_SHORT(source)) == -1 )
+	return -1;
+    source++;
+    }
+    return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+
+#ifdef EEPRO100_SROM_CHECK
+
+extern int read_eeprom (struct eth_device* dev, int location, int addr_len);
+
+void eepro100_srom_load (unsigned short *destination)
+{
+    int count;
+    struct eth_device onboard_dev;
+#ifdef DEBUG
+    int lr = 0;
+    printf ("eepro100_srom_download:\n");
+#endif
+
+    /* get onboard network iobase */
+    pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0,
+		 &onboard_dev.iobase);
+    onboard_dev.iobase &= ~0xf;
+
+    memset (destination, 0x65, 128);
+
+    for (count=0; count < 0x40; count++)
+    {
+	*destination++ = read_eeprom (struct eth_device*)&onboard_dev,
+		 count, EE_ADDR_BITS);
+#ifdef DEBUG
+	printf ("%04x ", *(destination - 1));
+	if (lr++ == 7)
+	{
+	    printf("\n");
+	    lr = 0;
+	}
+#endif
+    }
+}
+#endif /* EEPRO100_SROM_CHECK */
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c
new file mode 100755
index 0000000..a9dbeb2
--- /dev/null
+++ b/board/eltec/elppc/elppc.c
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc106.h>
+#include <video_fb.h>
+
+/* ------------------------------------------------------------------------- */
+
+int checkboard (void)
+{
+	puts ("Board: ELTEC PowerPC\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkflash (void)
+{
+	/* TODO */
+	printf ("Test not implemented !\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static unsigned int mpc106_read_cfg_dword (unsigned int reg)
+{
+	unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
+
+	out32r (MPC106_REG_ADDR, reg_addr);
+
+	return (in32r (MPC106_REG_DATA | (reg & 0x3)));
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int dram_size (int board_type)
+{
+	/*
+	 * No actual initialisation to do - done when setting up
+	 * PICRs MCCRs ME/SARs etc in asm_init.S.
+	 */
+
+	register unsigned long i, msar1, mear1, memSize;
+
+#if defined(CFG_MEMTEST)
+	register unsigned long reg;
+
+	printf ("Testing DRAM\n");
+
+	/* write each mem addr with it's address */
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
+		*reg = reg;
+
+	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
+		if (*reg != reg)
+			return -1;
+	}
+#endif
+
+	/*
+	 * Since MPC107 memory controller chip has already been set to
+	 * control all memory, just read and interpret its memory boundery register.
+	 */
+	memSize = 0;
+	msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
+	mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
+	i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
+
+	do {
+		if (i & 0x01)			/* is bank enabled ? */
+			memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
+		msar1 >>= 8;
+		mear1 >>= 8;
+		i >>= 1;
+	} while (i);
+
+	return (memSize * 0x100000);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	return dram_size (board_type);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * The BAB 911 can be reset by writing bit 0 of the Processor Initialization
+ * Register PI in the MPC 107 (at offset 0x41090 of the Embedded Utilities
+ * Memory Block).
+ */
+int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	out8 (MPC107_EUMB_PI, 1);
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+
+/*
+ * Since the 7xx CPUs don't have an internal watchdog, this function is
+ * board specific.
+ */
+void watchdog_reset (void)
+{
+}
+#endif							/* CONFIG_WATCHDOG */
+
+/* ------------------------------------------------------------------------- */
+
+void after_reloc (ulong dest_addr)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*
+	 * Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *)gd, dest_addr);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		sprintf (info, " MPC7xx V%d.%d at %d / %d MHz",
+				 (get_pvr () >> 8) & 0xFF, get_pvr () & 0xFF, 400, 100);
+		return;
+	case 2:
+		sprintf (info, " ELTEC ELPPC with %ld MB DRAM and %ld MB FLASH",
+				 dram_size (0) / 0x100000, flash_init () / 0x100000);
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
+
+	/* no more info lines */
+	*info = 0;
+	return;
+}
+#endif
diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c
new file mode 100755
index 0000000..442dd00
--- /dev/null
+++ b/board/eltec/elppc/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 07-10-2002 Frank Gottschling: added 29F032 flash (ELPPC).
+ *        fixed monitor protection part
+ *
+ * 09-18-2001 Andreas Heppel: Reduced the code in here to the usage
+ *        of AMD's 29F040 and 29F016 flashes, since the BAB7xx does use
+ *        any other.
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0           (0x555)
+#define ADDR1           (0x2AA)
+#define ADDR3           (0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*----------------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+    unsigned long size1, size2;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+    {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* initialise 1st flash */
+    size1 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+    if (flash_info[0].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	    size1, size1<<20);
+    }
+
+    /* initialise 2nd flash */
+    size2 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+    if (flash_info[1].flash_id == FLASH_UNKNOWN)
+    {
+	printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+	    size2, size2<<20);
+    }
+
+    /* monitor protection ON by default */
+    if (size1 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE0_PRELIM,
+		FLASH_BASE0_PRELIM+monitor_flash_len-1,
+		&flash_info[0]);
+    }
+    if (size2 == 512*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		FLASH_BASE1_PRELIM,
+		FLASH_BASE1_PRELIM+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+    if (size2 == 4*1024*1024)
+    {
+	(void)flash_protect(FLAG_PROTECT_SET,
+		CFG_FLASH_BASE,
+		CFG_FLASH_BASE+monitor_flash_len-1,
+		&flash_info[1]);
+    }
+
+    return (size1 + size2);
+}
+
+/*----------------------------------------------------------------------------*/
+
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+    int k;
+    int size;
+    int erased;
+    volatile unsigned long *flash;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	flash_init();
+    }
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+    case FLASH_MAN_AMD:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F016D:
+	printf ("AM29F016D (16 Mbit)\n");
+	break;
+    case AMD_ID_F032B:
+	printf ("AM29F032B (32 Mbit)\n");
+	break;
+   default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    if (info->size >= (1 << 20)) {
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+    } else {
+	printf ("  Size: %ld kB in %d Sectors\n", info->size >> 10, info->sector_count);
+    }
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	/*
+	* Check if whole sector is erased
+	*/
+	if (i != (info->sector_count-1))
+	    size = info->start[i+1] - info->start[i];
+	else
+	    size = info->start[0] + info->size - info->start[i];
+
+	erased = 1;
+	flash = (volatile unsigned long *)info->start[i];
+	size = size >> 2;        /* divide by 4 for longword access */
+	for (k=0; k<size; k++) {
+	    if (*flash++ != 0xffffffff) {
+		erased = 0;
+		break;
+	    }
+	}
+
+	if ((i % 5) == 0)
+	    printf ("\n   ");
+
+	printf (" %08lX%s%s",
+	    info->start[i],
+	    erased ? " E" : "  ",
+	    info->protect[i] ? "RO " : "   ");
+    }
+    printf ("\n");
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    ulong vendor, devid;
+    ulong base = (ulong)addr;
+    volatile unsigned char *caddr = (unsigned char *)addr;
+
+#ifdef DEBUG
+    printf("flash_get_size for address 0x%lx: \n", (unsigned long)caddr);
+#endif
+
+    /* Write auto select command: read Manufacturer ID */
+    caddr[0] = 0xF0;   /* reset bank */
+    udelay(10);
+
+    eieio();
+    caddr[0x555] = 0xAA;
+    udelay(10);
+    caddr[0x2AA] = 0x55;
+    udelay(10);
+    caddr[0x555] = 0x90;
+
+    udelay(10);
+
+    vendor = caddr[0];
+    devid = caddr[1];
+
+#ifdef DEBUG
+    printf("Manufacturer: 0x%lx\n", vendor);
+#endif
+
+    vendor &= 0xff;
+    devid &= 0xff;
+
+    /* We accept only two AMD types */
+    switch (vendor) {
+    case (FLASH_WORD_SIZE)AMD_MANUFACT:
+	info->flash_id = FLASH_MAN_AMD;
+	break;
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	info->sector_count = 0;
+	info->size = 0;
+	return (0);         /* no or unknown flash  */
+    }
+
+    switch (devid) {
+    case (FLASH_WORD_SIZE)AMD_ID_F040B:
+	info->flash_id |= AMD_ID_F040B;
+	info->sector_count = 8;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F016D:
+	info->flash_id |= AMD_ID_F016D;
+	info->sector_count = 32;
+	info->size         = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F032B:
+	info->flash_id |= AMD_ID_F032B;
+	info->sector_count = 64;
+	info->size         = 0x00400000;
+	break;              /* => 4 MB      */
+
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	return (0);         /* => no or unknown flash */
+
+    }
+
+#ifdef DEBUG
+    printf("flash id 0x%lx; sector count 0x%x, size 0x%lx\n", info->flash_id, info->sector_count, info->size);
+#endif
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	caddr = (volatile unsigned char *)(info->start[i]);
+	info->protect[i] = caddr[2] & 1;
+    }
+
+    /*
+     * Prevent writes to uninitialized FLASH.
+     */
+    if (info->flash_id != FLASH_UNKNOWN) {
+	caddr = (volatile unsigned char *)info->start[0];
+	caddr[0] = 0xF0;   /* reset bank */
+    }
+
+    return (info->size);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+    int rc = 0;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    if ((info->flash_id == FLASH_UNKNOWN) ||
+	(info->flash_id > FLASH_AMD_COMP)) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+	    prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+    addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+	    if (info->flash_id & FLASH_MAN_SST) {
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+		addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+		udelay(30000);  /* wait 30 ms */
+	    }
+	    else
+		addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+	goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+DONE:
+    /* reset to read mode */
+    addr = (FLASH_WORD_SIZE *)info->start[0];
+    addr[0] = (FLASH_WORD_SIZE)0x00F000F0;  /* reset bank */
+
+    printf (" done\n");
+    return rc;
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);   /* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*----------------------------------------------------------------------------*/
+/* Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+    ulong start;
+    int flag;
+	int i;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((volatile FLASH_WORD_SIZE *)dest) &
+	     (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+    return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c
new file mode 100755
index 0000000..5fb20ae
--- /dev/null
+++ b/board/eltec/elppc/misc.c
@@ -0,0 +1,261 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* includes */
+#include <common.h>
+#include <linux/ctype.h>
+#include <pci.h>
+#include <net.h>
+#include "srom.h"
+
+/* imports  */
+extern char console_buffer[CFG_CBSIZE];
+extern int l2_cache_enable (int l2control);
+extern int eepro100_write_eeprom (struct eth_device *dev, int location,
+				  int addr_len, unsigned short data);
+extern int read_eeprom (struct eth_device *dev, int location, int addr_len);
+
+/*----------------------------------------------------------------------------*/
+/*
+ * read/write to nvram is only byte access
+ */
+void *nvram_read (void *dest, const long src, size_t count)
+{
+	uchar *d = (uchar *) dest;
+	uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src);
+
+	while (count--)
+		*d++ = *s++;
+
+	return dest;
+}
+
+void nvram_write (long dest, const void *src, size_t count)
+{
+	uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest);
+	uchar *s = (uchar *) src;
+
+	while (count--)
+		*d++ = *s++;
+}
+
+/*----------------------------------------------------------------------------*/
+/*
+ * handle sroms on ELPPC
+ * fix ether address
+ * set serial console as default
+ */
+int misc_init_r (void)
+{
+	revinfo eerev;
+	u_char *ptr;
+	u_int i, l, initSrom, copyNv;
+	char buf[256];
+	char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+		0, 0, 0, 0, 10, 11, 12, 13, 14, 15
+	};
+
+	/* Clock setting for MPC107 i2c */
+	mpc107_i2c_init (MPC107_EUMB_ADDR, 0x2b);
+
+	/* Reset the EPIC */
+	out32r (MPC107_EUMB_GCR, 0xa0000000);
+	while (in32r (MPC107_EUMB_GCR) & 0x80000000);	/* Wait for reset to complete */
+	out32r (MPC107_EUMB_GCR, 0x20000000);	/* Put into into mixed mode */
+	while (in32r (MPC107_EUMB_IACKR) != 0xff);	/* Clear all pending interrupts */
+
+	/*
+	 * Check/Remake revision info
+	 */
+	initSrom = 0;
+	copyNv = 0;
+
+	/* read out current revision srom contens */
+	mpc107_srom_load (0x0000, (u_char *) & eerev, sizeof (revinfo),
+			  SECOND_DEVICE, FIRST_BLOCK);
+
+	/* read out current nvram shadow image */
+	nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
+
+	if (strcmp (eerev.magic, "ELTEC") != 0) {
+		/* srom is not initialized -> create a default revision info */
+		for (i = 0, ptr = (u_char *) & eerev; i < sizeof (revinfo);
+		     i++)
+			*ptr++ = 0x00;
+		strcpy (eerev.magic, "ELTEC");
+		eerev.revrev[0] = 1;
+		eerev.revrev[1] = 0;
+		eerev.size = 0x00E0;
+		eerev.category[0] = 0x01;
+
+		/* node id from dead e128 as default */
+		eerev.etheraddr[0] = 0x00;
+		eerev.etheraddr[1] = 0x00;
+		eerev.etheraddr[2] = 0x5B;
+		eerev.etheraddr[3] = 0x00;
+		eerev.etheraddr[4] = 0x2E;
+		eerev.etheraddr[5] = 0x4D;
+
+		/* cache config word for ELPPC */
+		*(int *) &eerev.res[0] = 0;
+
+		initSrom = 1;	/* force dialog */
+		copyNv = 1;	/* copy to nvram */
+	}
+
+	if ((copyNv == 0)
+	    && (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) !=
+		el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) {
+		printf ("Invalid revision info copy in nvram !\n");
+		printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
+		printf ("  <r> to reenter revision info.\n");
+		printf ("=> ");
+		if (0 != readline (NULL)) {
+			switch ((char) toupper (console_buffer[0])) {
+			case 'C':
+				copyNv = 1;
+				break;
+			case 'R':
+				copyNv = 1;
+				initSrom = 1;
+				break;
+			}
+		}
+	}
+
+	if (initSrom) {
+		memcpy (buf, &eerev.revision[0][0], 14);	/* save all revision info */
+		printf ("Enter revision number (0-9): %c  ",
+			eerev.revision[0][0]);
+		if (0 != readline (NULL)) {
+			eerev.revision[0][0] =
+				(char) toupper (console_buffer[0]);
+			memcpy (&eerev.revision[1][0], buf, 12);	/* shift rest of rev info */
+		}
+
+		printf ("Enter revision character (A-Z): %c  ",
+			eerev.revision[0][1]);
+		if (1 == readline (NULL)) {
+			eerev.revision[0][1] =
+				(char) toupper (console_buffer[0]);
+		}
+
+		printf ("Enter board name (V-XXXX-XXXX): %s  ",
+			(char *) &eerev.board);
+		if (11 == readline (NULL)) {
+			for (i = 0; i < 11; i++)
+				eerev.board[i] =
+					(char) toupper (console_buffer[i]);
+			eerev.board[11] = '\0';
+		}
+
+		printf ("Enter serial number: %s ", (char *) &eerev.serial);
+		if (6 == readline (NULL)) {
+			for (i = 0; i < 6; i++)
+				eerev.serial[i] = console_buffer[i];
+			eerev.serial[6] = '\0';
+		}
+
+		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
+		if (12 == readline (NULL)) {
+			for (i = 0; i < 12; i += 2)
+				eerev.etheraddr[i >> 1] =
+					(char) (16 *
+						hex[toupper
+						    (console_buffer[i]) -
+						    '0'] +
+						hex[toupper
+						    (console_buffer[i + 1]) -
+						    '0']);
+		}
+
+		l = strlen ((char *) &eerev.text);
+		printf ("Add to text section (max 64 chr): %s ",
+			(char *) &eerev.text);
+		if (0 != readline (NULL)) {
+			for (i = l; i < 63; i++)
+				eerev.text[i] = console_buffer[i - l];
+			eerev.text[63] = '\0';
+		}
+
+		/* prepare network eeprom */
+		memset (buf, 0, 128);
+
+		buf[0] = eerev.etheraddr[1];
+		buf[1] = eerev.etheraddr[0];
+		buf[2] = eerev.etheraddr[3];
+		buf[3] = eerev.etheraddr[2];
+		buf[4] = eerev.etheraddr[5];
+		buf[5] = eerev.etheraddr[4];
+
+		*(unsigned short *) &buf[20] = 0x48B2;
+		*(unsigned short *) &buf[22] = 0x0004;
+		*(unsigned short *) &buf[24] = 0x1433;
+
+		printf ("\nSRom:  Writing i82559 info ........ ");
+		if (eepro100_srom_store ((unsigned short *) buf) == -1)
+			printf ("FAILED\n");
+		else
+			printf ("OK\n");
+
+		/* update CRC */
+		eerev.crc =
+			el_srom_checksum ((u_char *) eerev.board, eerev.size);
+
+		/* write new values */
+		printf ("\nSRom:  Writing revision info ...... ");
+		if (mpc107_srom_store
+		    ((BLOCK_SIZE - sizeof (revinfo)), (u_char *) & eerev,
+		     sizeof (revinfo), SECOND_DEVICE, FIRST_BLOCK) == -1)
+			printf ("FAILED\n\n");
+		else
+			printf ("OK\n\n");
+
+		/* write new values as shadow image to nvram */
+		nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CFG_SROM_SIZE);
+
+	}
+
+	/*if (initSrom) */
+	/* copy current values as shadow image to nvram */
+	if (initSrom == 0 && copyNv == 1)
+		nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CFG_SROM_SIZE);
+
+	/* update environment */
+	sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+		 eerev.etheraddr[0], eerev.etheraddr[1],
+		 eerev.etheraddr[2], eerev.etheraddr[3],
+		 eerev.etheraddr[4], eerev.etheraddr[5]);
+	setenv ("ethaddr", buf);
+
+	/* print actual board identification */
+	printf ("Ident: %s  Ser %s  Rev %c%c\n",
+		eerev.board, (char *) &eerev.serial,
+		eerev.revision[0][0], eerev.revision[0][1]);
+
+	return (0);
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/mpc107_i2c.c b/board/eltec/elppc/mpc107_i2c.c
new file mode 100755
index 0000000..ae6642e
--- /dev/null
+++ b/board/eltec/elppc/mpc107_i2c.c
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* includes */
+#include <common.h>
+#include "srom.h"
+
+/* locals */
+static unsigned long mpc107_eumb_addr = 0;
+
+/*----------------------------------------------------------------------------*/
+
+/*
+ * calculate checksum for ELTEC revision srom
+ */
+unsigned long el_srom_checksum (ptr, size)
+register unsigned char *ptr;
+unsigned long size;
+{
+    u_long f, accu = 0;
+    u_int  i;
+    u_char byte;
+
+    for (; size; size--)
+    {
+	byte = *ptr++;
+	for (i = 8; i; i--)
+	{
+	    f =  ((byte & 1) ^ (accu & 1)) ? 0x84083001 : 0;
+	    accu >>= 1; accu ^= f;
+	    byte >>= 1;
+	}
+    }
+    return(accu);
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int mpc107_i2c_wait ( unsigned long timeout )
+{
+    unsigned long x;
+
+    while (((x = in32r(MPC107_I2CSR)) & 0x82) != 0x82)
+    {
+	if (!timeout--)
+	    return -1;
+    }
+
+    if (x & 0x10)
+    {
+	return -1;
+    }
+    out32r(MPC107_I2CSR, 0);
+
+    return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+
+static int mpc107_i2c_wait_idle ( unsigned long timeout )
+{
+    while (in32r(MPC107_I2CSR) & 0x20)
+    {
+	if (!timeout--)
+	    return -1;
+    }
+    return 0;
+}
+
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_i2c_read_byte (
+    unsigned char device,
+    unsigned char block,
+    unsigned char offset )
+{
+    unsigned long timeout = MPC107_I2C_TIMEOUT;
+    int data;
+
+    if (!mpc107_eumb_addr)
+	return -6;
+
+    mpc107_i2c_wait_idle (timeout);
+
+    /* Start with MEN */
+    out32r(MPC107_I2CCR, 0x80);
+
+    /* Start as master */
+    out32r(MPC107_I2CCR, 0xB0);
+    out32r(MPC107_I2CDR, (0xA0 | device | block));
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_read Error 1\n");
+	return -2;
+    }
+
+    if (in32r(MPC107_I2CSR)&0x1)
+    {
+	/* Generate STOP condition; device busy or not existing */
+	out32r(MPC107_I2CCR, 0x80);
+	return -1;
+    }
+
+    /* Data address */
+    out32r(MPC107_I2CDR, offset);
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_read Error 2\n");
+	return -3;
+    }
+
+    /* Switch to read - restart */
+    out32r(MPC107_I2CCR, 0xB4);
+    out32r(MPC107_I2CDR, (0xA1 | device | block));
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_read Error 3\n");
+	return -4;
+    }
+
+    out32r(MPC107_I2CCR, 0xA8); /* no ACK */
+    in32r(MPC107_I2CDR);
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_read Error 4\n");
+	return -5;
+    }
+    /* Generate STOP condition */
+    out32r(MPC107_I2CCR, 0x88);
+
+    /* read */
+    data = in32r(MPC107_I2CDR);
+
+    return (data);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_i2c_write_byte (
+    unsigned char device,
+    unsigned char block,
+    unsigned char offset,
+    unsigned char val )
+{
+
+    unsigned long timeout = MPC107_I2C_TIMEOUT;
+
+    if (!mpc107_eumb_addr)
+	return -6;
+
+    mpc107_i2c_wait_idle(timeout);
+
+    /* Start with MEN */
+    out32r(MPC107_I2CCR, 0x80);
+
+    /* Start as master */
+    out32r(MPC107_I2CCR, 0xB0);
+    out32r(MPC107_I2CDR, (0xA0 | device | block));
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_write Error 1\n");
+	return -1;
+    }
+
+    /* Data address */
+    out32r(MPC107_I2CDR, offset);
+
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_write Error 2\n");
+	return -1;
+    }
+
+    /* Write */
+    out32r(MPC107_I2CDR, val);
+    if (mpc107_i2c_wait(timeout) < 0)
+    {
+	printf("mpc107_i2c_write Error 3\n");
+	return -1;
+    }
+
+    /* Generate Stop Condition */
+    out32r(MPC107_I2CCR, 0x80);
+
+    /* Return ACK or no ACK */
+    return (in32r(MPC107_I2CSR) & 0x01);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_srom_load (
+    unsigned char addr,
+    unsigned char *pBuf,
+    int          cnt,
+    unsigned char device,
+    unsigned char block )
+{
+    register int i;
+    int val;
+    int timeout;
+
+    for (i = 0; i < cnt; i++)
+    {
+	timeout=100;
+	do
+	{
+	    val = mpc107_i2c_read_byte (device, block, addr);
+	    if (val < -1)
+	    {
+	    printf("i2c_read_error %d at dev %x block %x addr %x\n",
+		   val, device, block, addr);
+	    return -1;
+	    }
+	    else if (timeout==0)
+	    {
+		printf ("i2c_read_error: timeout at dev %x block %x addr %x\n",
+			device, block, addr);
+		return -1;
+	    }
+	    timeout--;
+	} while (val == -1); /* if no ack: try again! */
+
+	*pBuf++ = (unsigned char)val;
+	addr++;
+
+	if ((addr == 0) && (i != cnt-1))    /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+	    {
+		printf ("ic2_read_error: read beyond 2. block !\n");
+		return -1;
+	    }
+	}
+    }
+    udelay(100000);
+    return (cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_srom_store (
+    unsigned char addr,
+    unsigned char *pBuf,
+    int          cnt,
+    unsigned char device,
+    unsigned char block )
+{
+    register int i;
+
+    for (i = 0; i < cnt; i++)
+    {
+	while (mpc107_i2c_write_byte (device,block,addr,*pBuf) == 1);
+	addr++;
+	pBuf++;
+
+	if ((addr == 0) && (i != cnt-1))     /* is it the same block ? */
+	{
+	    if (block == FIRST_BLOCK)
+		block = SECOND_BLOCK;
+	    else
+	    {
+		printf ("ic2_write_error: write beyond 2. block !\n");
+		return -1;
+	    }
+	}
+    }
+    udelay(100000);
+    return(cnt);
+}
+
+/*----------------------------------------------------------------------------*/
+
+int mpc107_i2c_init ( unsigned long eumb_addr, unsigned long divider )
+{
+    unsigned long x;
+
+    if (eumb_addr)
+	mpc107_eumb_addr = eumb_addr;
+    else
+	return -1;
+
+    /* Set I2C clock */
+    x = in32r(MPC107_I2CFDR) & 0xffffff00;
+    out32r(MPC107_I2CFDR, (x | divider));
+
+    /* Clear arbitration */
+    out32r(MPC107_I2CSR, 0);
+
+    return mpc107_eumb_addr;
+}
+
+/*----------------------------------------------------------------------------*/
diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c
new file mode 100755
index 0000000..5b115ea
--- /dev/null
+++ b/board/eltec/elppc/pci.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+    struct pci_controller* hose = (struct pci_controller *)&local_hose;
+    u16 reg16;
+
+    hose->first_busno = 0;
+    hose->last_busno = 0xff;
+
+    pci_set_region(hose->regions + 0,
+	CFG_PCI_MEMORY_BUS,
+	CFG_PCI_MEMORY_PHYS,
+	CFG_PCI_MEMORY_SIZE,
+	PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+    /* PCI memory space */
+    pci_set_region(hose->regions + 1,
+	CFG_PCI_MEM_BUS,
+	CFG_PCI_MEM_PHYS,
+	CFG_PCI_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* ISA/PCI memory space */
+    pci_set_region(hose->regions + 2,
+	CFG_ISA_MEM_BUS,
+	CFG_ISA_MEM_PHYS,
+	CFG_ISA_MEM_SIZE,
+	PCI_REGION_MEM);
+
+    /* PCI I/O space */
+    pci_set_region(hose->regions + 3,
+	CFG_PCI_IO_BUS,
+	CFG_PCI_IO_PHYS,
+	CFG_PCI_IO_SIZE,
+	PCI_REGION_IO);
+
+    /* ISA/PCI I/O space */
+    pci_set_region(hose->regions + 4,
+	CFG_ISA_IO_BUS,
+	CFG_ISA_IO_PHYS,
+	CFG_ISA_IO_SIZE,
+	PCI_REGION_IO);
+
+    hose->region_count = 5;
+
+    pci_setup_indirect(hose,
+	MPC106_REG_ADDR,
+	MPC106_REG_DATA);
+
+    pci_register_hose(hose);
+
+    hose->last_busno = pci_hose_scan(hose);
+
+    /* Initialises the MPC10x PCI Configuration regs. */
+    pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+    reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+    /* Clear non-reserved bits in status register */
+    pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h
new file mode 100755
index 0000000..c18ab91
--- /dev/null
+++ b/board/eltec/elppc/srom.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* common srom defs */
+#define FIRST_DEVICE            0x00
+#define SECOND_DEVICE           0x04
+#define FIRST_BLOCK             0x00
+#define SECOND_BLOCK            0x02
+#define BLOCK_SIZE              0x100
+#define ERROR                   (-1)
+
+#define CLK2P0TO1_1MB_PB_0P5DH  0x79000100
+#define CLK2P5TO1_1MB_PB_0P5DH  0x7B000100
+
+#define CPU_TYPE_740            0x08
+#define CPU_TYPE_750            0x08
+#define CPU_TYPE                ((get_pvr()>>16)&0xffff)
+
+#define ABS(x)                  ((x<0)?-x:x)
+#define SROM_SHORT(pX)          (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
+
+/* bab7xx ELTEC srom */
+#define I2C_BUS_DAT             (CFG_ISA_IO + 0x220)
+#define I2C_BUS_DIR             (CFG_ISA_IO + 0x221)
+
+/* srom at mpc107 */
+#define MPC107_I2CADDR          (mpc107_eumb_addr + 0x3000)     /* address      */
+#define MPC107_I2CFDR           (mpc107_eumb_addr + 0x3004)     /* freq divider */
+#define MPC107_I2CCR            (mpc107_eumb_addr + 0x3008)     /* control      */
+#define MPC107_I2CSR            (mpc107_eumb_addr + 0x300c)     /* status       */
+#define MPC107_I2CDR            (mpc107_eumb_addr + 0x3010)     /* data         */
+#define MPC107_I2C_TIMEOUT      10000000
+
+/* i82559 */
+#define EE_ADDR_BITS            6
+#define EE_SIZE                 0x40                            /* 0x40 words */
+#define EE_CHECKSUM             0xBABA
+
+/* dc21143 */
+#define DEC_SROM_SIZE           128
+
+
+/*
+ * structure of revision srom
+ */
+typedef struct  {
+    char    magic[8];           /* 000 - Magic number */
+    char    revrev[2];          /* 008 - Revision of structure */
+    unsigned short size;        /* 00A - Size of CRC area */
+    unsigned long  crc;         /* 00C - CRC */
+    char    board[16];          /* 010 - Board Revision information */
+    char    option[4][16];      /* 020 - Option Revision information */
+    char    serial[8];          /* 060 - Board serial number */
+    char    etheraddr[6];       /* 068 - Ethernet node addresse */
+    char    reserved[2];        /* 06E - Reserved */
+    char    revision[7][2];     /* 070 - Revision codes */
+    char    category[2];        /* 07E - Category codes */
+    char    text[64];           /* 080 - Text field */
+    char    res[64];            /* 0C0 - Reserved */
+} revinfo;
+
+unsigned long el_srom_checksum (unsigned char *ptr, unsigned long size);
+int el_srom_load  (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+int el_srom_store (unsigned char addr, unsigned char *buf, int cnt,
+		   unsigned char device, unsigned char block);
+
+int mpc107_i2c_init (unsigned long eumb_addr, unsigned long divider);
+int mpc107_i2c_read_byte (unsigned char device, unsigned char block, unsigned char offset);
+int mpc107_i2c_write_byte (unsigned char device, unsigned char block,
+			   unsigned char offset, unsigned char val);
+int mpc107_srom_load (unsigned char addr, unsigned char *pBuf, int cnt,
+		      unsigned char device, unsigned char block);
+int mpc107_srom_store (unsigned char addr, unsigned char *pBuf, int cnt,
+		       unsigned char device, unsigned char block);
+
+int dc_srom_load (unsigned short *dest);
+int dc_srom_store (unsigned short *src);
+
+unsigned short eepro100_srom_checksum (unsigned short *sromdata);
+void eepro100_srom_load (unsigned short *destination);
+int  eepro100_srom_store (unsigned short *source);
diff --git a/board/eltec/elppc/u-boot.lds b/board/eltec/elppc/u-boot.lds
new file mode 100755
index 0000000..d89eb6c
--- /dev/null
+++ b/board/eltec/elppc/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/eltec/mhpc/Makefile b/board/eltec/mhpc/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/eltec/mhpc/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/eltec/mhpc/config.mk b/board/eltec/mhpc/config.mk
new file mode 100755
index 0000000..03934de
--- /dev/null
+++ b/board/eltec/mhpc/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MHPC boards
+#
+
+TEXT_BASE = 0xfe000000
+/*TEXT_BASE  = 0x00200000 */
diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c
new file mode 100755
index 0000000..4cc66a9
--- /dev/null
+++ b/board/eltec/mhpc/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <linux/byteorder/swab.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)                         __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)                         __swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int   write_data (flash_info_t *info, ulong dest, FPW data);
+static void  flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_FLASH_BASE,
+			    CFG_FLASH_BASE+monitor_flash_len-1,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+   case FLASH_28F640J5 :
+				printf ("28F640J5 \n"); break;
+	default:		printf ("Unknown Chip Type=0x%lXh\n",
+					info->flash_id & FLASH_TYPEMASK); break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW)0xAA00AA00;
+	addr[0x2AAA] = (FPW)0x55005500;
+	addr[0x5555] = (FPW)0x90009000;
+
+	value = SWAP(addr[0]);
+
+   switch (value) {
+   case (FPW)INTEL_MANUFACT:
+      info->flash_id = FLASH_MAN_INTEL;
+      break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW)0xFF00FF00;      /* restore read mode */
+		return (0);			      /* no or unknown flash	*/
+	}
+
+   value = SWAP(addr[1]);			        /* device ID no swap !*/
+
+   switch (value) {
+   case (FPW)INTEL_ID_28F640J5 :
+	info->flash_id += FLASH_28F640J5 ;
+	info->sector_count = 64;
+	info->size = 0x00800000;
+	break;            /* => 8 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW)0xFF00FF00;      /* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rc = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *)(info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = (FPW)0x50005000;	/* clear status register */
+			*addr = (FPW)0x20002000;	/* erase setup */
+			*addr = (FPW)0xD000D000;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW)0xB000B000; /* suspend erase */
+					*addr = (FPW)0xFF00FF00; /* reset to read mode */
+					rc = 1;
+					break;
+				}
+
+				/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = (FPW)0xFF00FF00;	/* reset to read mode */
+			printf (" done\n");
+		}
+	}
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<port_width && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i=0; i<port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += port_width;
+		cnt -= port_width;
+		if ((wp & 0xfff) == 0)
+		{
+			printf("%08lX",wp);
+			printf("\x1b[8D");
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *)dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW)0x40004000;		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW)0xFF00FF00;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW)0xFF00FF00;	/* restore read mode */
+
+	return (0);
+}
diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c
new file mode 100755
index 0000000..0ffbdf0
--- /dev/null
+++ b/board/eltec/mhpc/mhpc.c
@@ -0,0 +1,483 @@
+/*
+ * (C) Copyright 2001
+ * ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * Board specific routines for the miniHiPerCam
+ *
+ * - initialisation (eeprom)
+ * - memory controller
+ * - serial io initialisation
+ * - ethernet io initialisation
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <linux/ctype.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+#include <video_fb.h>
+
+/* imports from common/main.c */
+extern char console_buffer[CFG_CBSIZE];
+
+extern void eeprom_init (void);
+extern int eeprom_read (unsigned dev_addr, unsigned offset,
+			unsigned char *buffer, unsigned cnt);
+extern int eeprom_write (unsigned dev_addr, unsigned offset,
+			 unsigned char *buffer, unsigned cnt);
+
+/* globals */
+void *video_hw_init (void);
+void video_set_lut (unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+	);
+
+GraphicDevice gdev;
+
+/* locals */
+static void video_circle (char *center, int radius, int color, int pitch);
+static void video_test_image (void);
+static void video_default_lut (unsigned int clut_type);
+
+/* revision info foer MHPC EEPROM offset 480 */
+typedef struct {
+	char board[12];		/* 000 - Board Revision information */
+	char sensor;		/* 012 - Sensor Type information */
+	char serial[8];		/* 013 - Board serial number */
+	char etheraddr[6];	/* 021 - Ethernet node addresse */
+	char revision[2];	/* 027 - Revision code */
+	char option[3];		/* 029 - resevered for options */
+} revinfo;
+
+/* ------------------------------------------------------------------------- */
+
+static const unsigned int sdram_table[] = {
+	/* read single beat cycle */
+	0xef0efc04, 0x0e2dac04, 0x01ba5c04, 0x1ff5fc00,
+	0xfffffc05, 0xeffafc34, 0x0ff0bc34, 0x1ff57c35,
+
+	/* read burst cycle */
+	0xef0efc04, 0x0e3dac04, 0x10ff5c04, 0xf0fffc00,
+	0xf0fffc00, 0xf1fffc00, 0xfffffc00, 0xfffffc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* write single beat cycle */
+	0xef0efc04, 0x0e29ac00, 0x01b25c04, 0x1ff5fc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* write burst cycle */
+	0xef0ef804, 0x0e39a000, 0x10f75000, 0xf0fff440,
+	0xf0fffc40, 0xf1fffc04, 0xfffffc05, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* periodic timer expired */
+	0xeffebc84, 0x1ffd7c04, 0xfffffc04, 0xfffffc84,
+	0xeffebc04, 0x1ffd7c04, 0xfffffc04, 0xfffffc05,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* exception */
+	0xfffffc04, 0xfffffc05, 0xfffffc04, 0xfffffc04
+};
+
+/* ------------------------------------------------------------------------- */
+
+int board_early_init_f (void)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+	volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
+
+	/* reset the port A s.a. cpm-routines */
+	ip->iop_padat = 0x0000;
+	ip->iop_papar = 0x0000;
+	ip->iop_padir = 0x0800;
+	ip->iop_paodr = 0x0000;
+
+	/* reset the port B for digital and LCD output */
+	cp->cp_pbdat = 0x0300;
+	cp->cp_pbpar = 0x5001;
+	cp->cp_pbdir = 0x5301;
+	cp->cp_pbodr = 0x0000;
+
+	/* reset the port C configured for SMC1 serial port and aqc. control */
+	ip->iop_pcdat = 0x0800;
+	ip->iop_pcpar = 0x0000;
+	ip->iop_pcdir = 0x0e30;
+	ip->iop_pcso = 0x0000;
+
+	/* Config port D for LCD output */
+	ip->iop_pdpar = 0x1fff;
+	ip->iop_pddir = 0x1fff;
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+	puts ("Board: ELTEC miniHiperCam\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r (void)
+{
+	revinfo mhpcRevInfo;
+	char nid[32];
+	char *mhpcSensorTypes[] = { "OMNIVISON OV7610/7620 color",
+		"OMNIVISON OV7110 b&w", NULL
+	};
+	char hex[23] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 0, 0,
+		0, 0, 0, 0, 10, 11, 12, 13, 14, 15
+	};
+	int i;
+
+	/* check revision data */
+	eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
+
+	if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
+		printf ("Enter revision number (0-9): %c  ",
+			mhpcRevInfo.revision[0]);
+		if (0 != readline (NULL)) {
+			mhpcRevInfo.revision[0] =
+				(char) toupper (console_buffer[0]);
+		}
+
+		printf ("Enter revision character (A-Z): %c  ",
+			mhpcRevInfo.revision[1]);
+		if (1 == readline (NULL)) {
+			mhpcRevInfo.revision[1] =
+				(char) toupper (console_buffer[0]);
+		}
+
+		printf ("Enter board name (V-XXXX-XXXX): %s  ",
+			(char *) &mhpcRevInfo.board);
+		if (11 == readline (NULL)) {
+			for (i = 0; i < 11; i++) {
+				mhpcRevInfo.board[i] =
+					(char) toupper (console_buffer[i]);
+				mhpcRevInfo.board[11] = '\0';
+			}
+		}
+
+		printf ("Supported sensor types:\n");
+		i = 0;
+		do {
+			printf ("\n    \'%d\' : %s\n", i, mhpcSensorTypes[i]);
+		} while (mhpcSensorTypes[++i] != NULL);
+
+		do {
+			printf ("\nEnter sensor number (0-255): %d  ",
+				(int) mhpcRevInfo.sensor);
+			if (0 != readline (NULL)) {
+				mhpcRevInfo.sensor =
+					(unsigned char)
+					simple_strtoul (console_buffer, NULL,
+							10);
+			}
+		} while (mhpcRevInfo.sensor >= i);
+
+		printf ("Enter serial number: %s ",
+			(char *) &mhpcRevInfo.serial);
+		if (6 == readline (NULL)) {
+			for (i = 0; i < 6; i++) {
+				mhpcRevInfo.serial[i] = console_buffer[i];
+			}
+			mhpcRevInfo.serial[6] = '\0';
+		}
+
+		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+		if (12 == readline (NULL)) {
+			for (i = 0; i < 12; i += 2) {
+				mhpcRevInfo.etheraddr[i >> 1] =
+					(char) (16 *
+						hex[toupper
+						    (console_buffer[i]) -
+						    '0'] +
+						hex[toupper
+						    (console_buffer[i + 1]) -
+						    '0']);
+			}
+		}
+
+		/* setup new revision data */
+		eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
+			      32);
+	}
+
+	/* set environment */
+	sprintf (nid, "%02x:%02x:%02x:%02x:%02x:%02x",
+		 mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1],
+		 mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3],
+		 mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
+	setenv ("ethaddr", nid);
+
+	/* print actual board identification */
+	printf ("Ident: %s %s Ser %s Rev %c%c\n",
+		mhpcRevInfo.board,
+		(mhpcRevInfo.sensor == 0 ? "color" : "b&w"),
+		(char *) &mhpcRevInfo.serial, mhpcRevInfo.revision[0],
+		mhpcRevInfo.revision[1]);
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
+	memctl->memc_mptpr = MPTPR_PTP_DIV64;
+	memctl->memc_mar = 0x00008800;
+
+	/*
+	 * Map controller SDRAM bank 0
+	 */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+	udelay (200);
+
+	/*
+	 * Map controller SDRAM bank 1
+	 */
+	memctl->memc_or2 = CFG_OR2;
+	memctl->memc_br2 = CFG_BR2;
+
+	/*
+	 * Perform SDRAM initializsation sequence
+	 */
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002730;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (10000);
+
+	/* leave place for framebuffers */
+	return (SDRAM_MAX_SIZE - SDRAM_RES_SIZE);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void video_circle (char *center, int radius, int color, int pitch)
+{
+	int x, y, d, dE, dSE;
+
+	x = 0;
+	y = radius;
+	d = 1 - radius;
+	dE = 3;
+	dSE = -2 * radius + 5;
+
+	*(center + x + y * pitch) = color;
+	*(center + y + x * pitch) = color;
+	*(center + y - x * pitch) = color;
+	*(center + x - y * pitch) = color;
+	*(center - x - y * pitch) = color;
+	*(center - y - x * pitch) = color;
+	*(center - y + x * pitch) = color;
+	*(center - x + y * pitch) = color;
+	while (y > x) {
+		if (d < 0) {
+			d += dE;
+			dE += 2;
+			dSE += 2;
+			x++;
+		} else {
+			d += dSE;
+			dE += 2;
+			dSE += 4;
+			x++;
+			y--;
+		}
+		*(center + x + y * pitch) = color;
+		*(center + y + x * pitch) = color;
+		*(center + y - x * pitch) = color;
+		*(center + x - y * pitch) = color;
+		*(center - x - y * pitch) = color;
+		*(center - y - x * pitch) = color;
+		*(center - y + x * pitch) = color;
+		*(center - x + y * pitch) = color;
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void video_test_image (void)
+{
+	char *di;
+	int i, n;
+
+	/* draw raster */
+	for (i = 0; i < LCD_VIDEO_ROWS; i += 32) {
+		memset ((char *) (LCD_VIDEO_ADDR + i * LCD_VIDEO_COLS),
+			LCD_VIDEO_FG, LCD_VIDEO_COLS);
+		for (n = i + 1; n < i + 32; n++)
+			memset ((char *) (LCD_VIDEO_ADDR +
+					  n * LCD_VIDEO_COLS), LCD_VIDEO_BG,
+				LCD_VIDEO_COLS);
+	}
+
+	for (i = 0; i < LCD_VIDEO_COLS; i += 32) {
+		for (n = 0; n < LCD_VIDEO_ROWS; n++)
+			*(char *) (LCD_VIDEO_ADDR + n * LCD_VIDEO_COLS + i) =
+				LCD_VIDEO_FG;
+	}
+
+	/* draw gray bar */
+	di = (char *) (LCD_VIDEO_ADDR + (LCD_VIDEO_COLS - 256) / 64 * 32 +
+		       97 * LCD_VIDEO_COLS);
+	for (n = 0; n < 63; n++) {
+		for (i = 0; i < 256; i++) {
+			*di++ = (char) i;
+			*(di + LCD_VIDEO_COLS * 64) = (i & 1) * 255;
+		}
+		di += LCD_VIDEO_COLS - 256;
+	}
+
+	video_circle ((char *) LCD_VIDEO_ADDR + LCD_VIDEO_COLS / 2 +
+		      LCD_VIDEO_ROWS / 2 * LCD_VIDEO_COLS, LCD_VIDEO_ROWS / 2,
+		      LCD_VIDEO_FG, LCD_VIDEO_COLS);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void video_default_lut (unsigned int clut_type)
+{
+	unsigned int i;
+	unsigned char RGB[] = {
+		0x00, 0x00, 0x00,	/* black */
+		0x80, 0x80, 0x80,	/* gray */
+		0xff, 0x00, 0x00,	/* red */
+		0x00, 0xff, 0x00,	/* green */
+		0x00, 0x00, 0xff,	/* blue */
+		0x00, 0xff, 0xff,	/* cyan */
+		0xff, 0x00, 0xff,	/* magenta */
+		0xff, 0xff, 0x00,	/* yellow */
+		0x80, 0x00, 0x00,	/* dark red */
+		0x00, 0x80, 0x00,	/* dark green */
+		0x00, 0x00, 0x80,	/* dark blue */
+		0x00, 0x80, 0x80,	/* dark cyan */
+		0x80, 0x00, 0x80,	/* dark magenta */
+		0x80, 0x80, 0x00,	/* dark yellow */
+		0xc0, 0xc0, 0xc0,	/* light gray */
+		0xff, 0xff, 0xff,	/* white */
+	};
+
+	switch (clut_type) {
+	case 1:
+		for (i = 0; i < 240; i++)
+			video_set_lut (i, i, i, i);
+		for (i = 0; i < 16; i++)
+			video_set_lut (i + 240, RGB[i * 3], RGB[i * 3 + 1],
+				       RGB[i * 3 + 2]);
+		break;
+	default:
+		for (i = 0; i < 256; i++)
+			video_set_lut (i, i, i, i);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+void *video_hw_init (void)
+{
+	unsigned int clut = 0;
+	unsigned char *penv;
+	immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/* enable video only on CLUT value */
+	if ((penv = (uchar *)getenv ("clut")) != NULL)
+		clut = (u_int) simple_strtoul ((char *)penv, NULL, 10);
+	else
+		return NULL;
+
+	/* disable graphic before write LCD regs. */
+	immr->im_lcd.lcd_lccr = 0x96000866;
+
+	/* config LCD regs. */
+	immr->im_lcd.lcd_lcfaa = LCD_VIDEO_ADDR;
+	immr->im_lcd.lcd_lchcr = 0x010a0093;
+	immr->im_lcd.lcd_lcvcr = 0x900f0024;
+
+	printf ("Video: 640x480 8Bit Index Lut %s\n",
+		(clut == 1 ? "240/16 (gray/vga)" : "256(gray)"));
+
+	video_default_lut (clut);
+
+	/* clear framebuffer */
+	memset ((char *) (LCD_VIDEO_ADDR), LCD_VIDEO_BG,
+		LCD_VIDEO_ROWS * LCD_VIDEO_COLS);
+
+	/* enable graphic */
+	immr->im_lcd.lcd_lccr = 0x96000867;
+
+	/* fill in Graphic Device */
+	gdev.frameAdrs = LCD_VIDEO_ADDR;
+	gdev.winSizeX = LCD_VIDEO_COLS;
+	gdev.winSizeY = LCD_VIDEO_ROWS;
+	gdev.gdfBytesPP = 1;
+	gdev.gdfIndex = GDF__8BIT_INDEX;
+
+	if (clut > 1)
+		/* return Graphic Device for console */
+		return (void *) &gdev;
+	else
+		/* just graphic enabled - draw something beautiful */
+		video_test_image ();
+
+	return NULL;		/* this disabels cfb - console */
+}
+
+/* ------------------------------------------------------------------------- */
+
+void video_set_lut (unsigned int index,
+		    unsigned char r, unsigned char g, unsigned char b)
+{
+	unsigned int lum;
+	unsigned short *pLut = (unsigned short *) (CFG_IMMR + 0x0e00);
+
+	/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
+	/* y = 0.299*R + 0.587*G + 0.114*B */
+	lum = (2990 * r + 5870 * g + 1140 * b) / 10000;
+	pLut[index] =
+		((b & 0xc0) << 4) | ((g & 0xc0) << 2) | (r & 0xc0) | (lum &
+								      0x3f);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds
new file mode 100755
index 0000000..7099fc4
--- /dev/null
+++ b/board/eltec/mhpc/u-boot.lds
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug
new file mode 100755
index 0000000..3165d56
--- /dev/null
+++ b/board/eltec/mhpc/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/emk/common/am79c874.c b/board/emk/common/am79c874.c
new file mode 100755
index 0000000..552813e
--- /dev/null
+++ b/board/emk/common/am79c874.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*****************************************************************************
+ * check fiber optic link present, and then copper link present. do auto switch
+ * between both
+ *****************************************************************************/
diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c
new file mode 100755
index 0000000..d6161bf
--- /dev/null
+++ b/board/emk/common/flash.c
@@ -0,0 +1,591 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined (CONFIG_TOP860)
+  typedef unsigned short FLASH_PORT_WIDTH;
+  typedef volatile unsigned short FLASH_PORT_WIDTHV;
+  #define	FLASH_ID_MASK	0xFF
+
+  #define FPW	FLASH_PORT_WIDTH
+  #define FPWV	FLASH_PORT_WIDTHV
+
+  #define FLASH_CYCLE1	0x0555
+  #define FLASH_CYCLE2	0x02aa
+  #define FLASH_ID1		0
+  #define FLASH_ID2		1
+  #define FLASH_ID3		0x0e
+  #define FLASH_ID4		0x0F
+#endif
+
+#if defined (CONFIG_TOP5200) && !defined (CONFIG_LITE5200)
+  typedef unsigned char FLASH_PORT_WIDTH;
+  typedef volatile unsigned char FLASH_PORT_WIDTHV;
+  #define	FLASH_ID_MASK	0xFF
+
+  #define FPW	FLASH_PORT_WIDTH
+  #define FPWV	FLASH_PORT_WIDTHV
+
+  #define FLASH_CYCLE1	0x0aaa
+  #define FLASH_CYCLE2	0x0555
+  #define FLASH_ID1		0
+  #define FLASH_ID2		2
+  #define FLASH_ID3		0x1c
+  #define FLASH_ID4		0x1E
+#endif
+
+#if defined (CONFIG_TOP5200) && defined (CONFIG_LITE5200)
+  typedef unsigned char FLASH_PORT_WIDTH;
+  typedef volatile unsigned char FLASH_PORT_WIDTHV;
+  #define	FLASH_ID_MASK	0xFF
+
+  #define FPW	FLASH_PORT_WIDTH
+  #define FPWV	FLASH_PORT_WIDTHV
+
+  #define FLASH_CYCLE1	0x0555
+  #define FLASH_CYCLE2	0x02aa
+  #define FLASH_ID1		0
+  #define FLASH_ID2		1
+  #define FLASH_ID3		0x0E
+  #define FLASH_ID4		0x0F
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i = 0;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(uint, ulong, ulong);
+	ulong flashbase = CFG_FLASH_BASE;
+
+	flash_preinit();
+
+	/* There is only ONE FLASH device */
+	memset(&flash_info[i], 0, sizeof(flash_info_t));
+	flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+	size += flash_info[i].size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+
+	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size &&
+			info->start[0] <= base && base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+#if 0
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+#endif
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160T:
+	case FLASH_AM160B:
+		fmt = "29LV160%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_AMLV640U:
+		fmt = "29LV640M (64 Mbit)\n";
+		break;
+	case FLASH_AMDLV065D:
+		fmt = "29LV065D (64 Mbit)\n";
+		break;
+	case FLASH_AMLV256U:
+		fmt = "29LV256M (256 Mbit)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		ulong	size;
+		int		erased;
+		ulong	*flash = (unsigned long *) info->start[i];
+
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size =
+			(i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+		(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (
+			flash = (unsigned long *) info->start[i], erased = 1;
+				(flash != (unsigned long *) info->start[i] + size) && erased;
+					flash++
+			)
+			erased = *flash == ~0x0UL;
+
+		printf (" %08lX %s %s",
+			info->start[i],
+			erased ? "E": " ",
+			info->protect[i] ? "(RO)" : "    ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int		i;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[FLASH_ID1] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+#if 0
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+#endif
+
+	default:
+		printf ("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[FLASH_ID2]) {
+
+	case (FPW)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		info->start[0] = (ulong)addr;
+		info->start[1] = (ulong)addr + 0x4000;
+		info->start[2] = (ulong)addr + 0x6000;
+		info->start[3] = (ulong)addr + 0x8000;
+		for (i = 4; i < info->sector_count; i++)
+		{
+			info->start[i] = (ulong)addr + 0x10000 * (i-3);
+		}
+		break;
+
+	case (FPW)AMD_ID_LV065D:
+		info->flash_id += FLASH_AMDLV065D;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		for (i = 0; i < info->sector_count; i++)
+		{
+			info->start[i] = (ulong)addr + 0x10000 * i;
+		}
+		break;
+
+	case (FPW)AMD_ID_MIRROR:
+		/* MIRROR BIT FLASH, read more ID bytes */
+		if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV640U_2 &&
+			(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV640U_3)
+		{
+			info->flash_id += FLASH_AMLV640U;
+			info->sector_count = 128;
+			info->size = 0x00800000;
+			for (i = 0; i < info->sector_count; i++)
+			{
+				info->start[i] = (ulong)addr + 0x10000 * i;
+			}
+			break;
+		}
+		if ((FPW)addr[FLASH_ID3] == (FPW)AMD_ID_LV256U_2 &&
+			(FPW)addr[FLASH_ID4] == (FPW)AMD_ID_LV256U_3)
+		{
+			/* attention: only the first 16 MB will be used in u-boot */
+			info->flash_id += FLASH_AMLV256U;
+			info->sector_count = 256;
+			info->size = 0x01000000;
+			for (i = 0; i < info->sector_count; i++)
+			{
+				info->start[i] = (ulong)addr + 0x10000 * i;
+			}
+			break;
+		}
+
+		/* fall thru to here ! */
+	default:
+		printf ("unknown AMD device=%x %x %x",
+			(FPW)addr[FLASH_ID2],
+			(FPW)addr[FLASH_ID3],
+			(FPW)addr[FLASH_ID4]);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0x800000;
+		break;
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160B:
+	case FLASH_AMLV640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode */
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		 left > 0 && res == 0;
+		 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
diff --git a/board/emk/common/vpd.c b/board/emk/common/vpd.c
new file mode 100755
index 0000000..8a3a12b
--- /dev/null
+++ b/board/emk/common/vpd.c
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*****************************************************************************
+ * read "factory" part of EEPROM and set some environment variables
+ *****************************************************************************/
+void read_factory_r (void)
+{
+	/* read 'factory' part of EEPROM */
+	uchar buf[81];
+	uchar *p;
+	uint length;
+	uint addr;
+	uint len;
+
+	/* get length first */
+	addr = CFG_FACT_OFFSET;
+	if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2)) {
+	  bailout:
+		printf ("cannot read factory configuration\n");
+		printf ("be sure to set ethaddr	yourself!\n");
+		return;
+	}
+	length = buf[0] + (buf[1] << 8);
+	addr += 2;
+
+	/* sanity check */
+	if (length < 20 || length > CFG_FACT_SIZE - 2)
+		goto bailout;
+
+	/* read lines */
+	while (length > 0) {
+		/* read one line */
+		len = length > 80 ? 80 : length;
+		if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len))
+			goto bailout;
+		/* mark end of buffer */
+		buf[len] = 0;
+		/* search end of line */
+		for (p = buf; *p && *p != 0x0a; p++);
+		if (!*p)
+			goto bailout;
+		*p++ = 0;
+		/* advance to next line start */
+		length -= p - buf;
+		addr += p - buf;
+		/*printf ("%s\n", buf); */
+		/* search for our specific entry */
+		if (!strncmp ((char *) buf, "[RLA/lan/Ethernet] ", 19)) {
+			setenv ("ethaddr", (char *)(buf + 19));
+		} else if (!strncmp ((char *) buf, "[BOARD/SERIAL] ", 15)) {
+			setenv ("serial#", (char *)(buf + 15));
+		} else if (!strncmp ((char *) buf, "[BOARD/TYPE] ", 13)) {
+			setenv ("board_id", (char *)(buf + 13));
+		}
+	}
+}
diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile
new file mode 100755
index 0000000..986608b
--- /dev/null
+++ b/board/emk/top5200/Makefile
@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/emk/top5200/config.mk b/board/emk/top5200/config.mk
new file mode 100755
index 0000000..84131fe
--- /dev/null
+++ b/board/emk/top5200/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2003
+# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TOP5200 board, on optional MINI5200 and EVAL5200 boards
+#
+# allowed and functional TEXT_BASE values:
+#
+#   0xff000000		low boot at 0x00000100 (default board setting)
+#   0xfff00000		high boot at 0xfff00100 (board needs modification)
+#	0x00100000		RAM load and test
+#
+
+TEXT_BASE = 0xff000000
+#TEXT_BASE = 0xfff00000
+#TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c
new file mode 100755
index 0000000..4508438
--- /dev/null
+++ b/board/emk/top5200/top5200.c
@@ -0,0 +1,210 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+/*****************************************************************************
+ * initialize SDRAM/DDRAM controller.
+ * TBD: get data from I2C EEPROM
+ *****************************************************************************/
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+#if 0
+	ulong	t;
+	ulong	tap_del;
+#endif
+
+	#define	MODE_EN		0x80000000
+	#define	SOFT_PRE	2
+	#define	SOFT_REF	4
+
+	/* configure SDRAM start/end */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+#ifdef CFG_DRAM_DDR
+	/* set extended mode register */
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
+#endif
+	/* set mode register */
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
+	/* set mode register */
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
+	/* write default TAP delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
+
+#if 0
+	for (tap_del = 0; tap_del < 32; tap_del++)
+	{
+		*(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24;
+
+		printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG);
+		for (t = 0; t < 0x04000000; t+=4)
+			*(vu_long *) t = t;
+		printf ("Checking DRAM...\n");
+		for (t = 0; t < 0x04000000; t+=4)
+		{
+			ulong	rval = *(vu_long *) t;
+			if (rval != t)
+			{
+				printf ("mismatch at %x: ", t);
+				printf (" 1.read %x", rval);
+				printf (" 2.read %x", *(vu_long *) t);
+				printf (" 3.read %x", *(vu_long *) t);
+				break;
+			}
+		}
+	}
+#endif
+#endif /* CFG_RAMBOOT */
+
+	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
+
+	/* return total ram size */
+	return dramsize;
+}
+
+/*****************************************************************************
+ * print board identification
+ *****************************************************************************/
+int checkboard (void)
+{
+#if defined (CONFIG_EVAL5200)
+	puts ("Board: EMK TOP5200 on EVAL5200\n");
+#else
+#if defined (CONFIG_LITE5200)
+	puts ("Board: LITE5200\n");
+#else
+#if defined (CONFIG_MINI5200)
+	puts ("Board: EMK TOP5200 on MINI5200\n");
+#else
+	puts ("Board: EMK TOP5200\n");
+#endif
+#endif
+#endif
+	return 0;
+}
+
+/*****************************************************************************
+ * prepare for FLASH detection
+ *****************************************************************************/
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+/*****************************************************************************
+ * finalize FLASH setup
+ *****************************************************************************/
+void flash_afterinit(uint bank, ulong start, ulong size)
+{
+	if (bank == 0) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START =
+		*(vu_long *)MPC5XXX_CS0_START =	START_REG(start);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP =
+		*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size);
+	}
+}
+
+/*****************************************************************************
+ * otherinits after RAM is there and we are relocated to RAM
+ * note: though this is an int function, nobody cares for the result!
+ *****************************************************************************/
+int misc_init_r (void)
+{
+#if !defined (CONFIG_LITE5200)
+	/* read 'factory' part of EEPROM */
+	extern void read_factory_r (void);
+	read_factory_r ();
+#endif
+	return (0);
+}
+
+/*****************************************************************************
+ * initialize the PCI system
+ *****************************************************************************/
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+/*****************************************************************************
+ * provide the IDE Reset Function
+ *****************************************************************************/
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+    	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
diff --git a/board/emk/top5200/u-boot.lds b/board/emk/top5200/u-boot.lds
new file mode 100755
index 0000000..f23432e
--- /dev/null
+++ b/board/emk/top5200/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile
new file mode 100755
index 0000000..a74dd2f
--- /dev/null
+++ b/board/emk/top860/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/emk/top860/config.mk b/board/emk/top860/config.mk
new file mode 100755
index 0000000..7b940cb
--- /dev/null
+++ b/board/emk/top860/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TOP860 board
+#
+
+TEXT_BASE = 0x80000000
diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c
new file mode 100755
index 0000000..84afaaa
--- /dev/null
+++ b/board/emk/top860/top860.c
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2003
+ * EMK Elektronik GmbH <www.emk-elektronik.de>
+ * Reinhard Meyer <r.meyer@emk-elektronik.de>
+ *
+ * Board specific routines for the TOP860
+ *
+ * - initialisation
+ * - interface to VPD data (mac address, clock speeds)
+ * - memory controller
+ * - serial io initialisation
+ * - ethernet io initialisation
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <mpc8xx.h>
+
+/*****************************************************************************
+ * UPM table for 60ns EDO RAM at 25 MHz bus/external clock
+ *****************************************************************************/
+static const uint edo_60ns_25MHz_tbl[] = {
+
+/* single read   (offset 0x00 in upm ram) */
+    0x0ff3fc04,0x08f3fc04,0x00f3fc04,0x00f3fc00,
+    0x33f7fc07,0xfffffc05,0xfffffc05,0xfffffc05,
+/* burst read    (offset 0x08 in upm ram) */
+    0x0ff3fc04,0x08f3fc04,0x00f3fc0c,0x0ff3fc40,
+    0x0cf3fc04,0x03f3fc48,0x0cf3fc04,0x03f3fc48,
+    0x0cf3fc04,0x03f3fc00,0x3ff7fc07,0xfffffc05,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+/* single write  (offset 0x18 in upm ram) */
+    0x0ffffc04,0x08fffc04,0x30fffc00,0xf1fffc07,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+/* burst write   (offset 0x20 in upm ram) */
+    0x0ffffc04,0x08fffc00,0x00fffc04,0x03fffc4c,
+    0x00fffc00,0x07fffc4c,0x00fffc00,0x0ffffc4c,
+    0x00fffc00,0x3ffffc07,0xfffffc05,0xfffffc05,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+/* refresh       (offset 0x30 in upm ram) */
+    0xc0fffc04,0x07fffc04,0x0ffffc04,0x0ffffc04,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+    0xfffffc05,0xfffffc05,0xfffffc05,0xfffffc05,
+/* exception     (offset 0x3C in upm ram) */
+    0xfffffc07,0xfffffc03,0xfffffc05,0xfffffc05,
+};
+
+/*****************************************************************************
+ * Print Board Identity
+ *****************************************************************************/
+int checkboard (void)
+{
+	puts ("Board:"CONFIG_IDENT_STRING"\n");
+	return (0);
+}
+
+/*****************************************************************************
+ * Initialize DRAM controller
+ *****************************************************************************/
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/*
+	 * Only initialize memory controller when running from FLASH.
+	 * When running from RAM, don't touch it.
+	 */
+	if ((ulong) initdram & 0xff000000) {
+		volatile uint *addr1, *addr2;
+		uint i, j;
+
+		upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl,
+			   sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
+		memctl->memc_mptpr = 0x0200;
+		memctl->memc_mamr = 0x0ca20330;
+		memctl->memc_or2 = -CFG_DRAM_MAX | OR_CSNT_SAM;
+		memctl->memc_br2 = CFG_DRAM_BASE | BR_MS_UPMA | BR_V;
+		/*
+		 * Do 8 read accesses to DRAM
+		 */
+		addr1 = (volatile uint *) 0;
+		addr2 = (volatile uint *) 0x00400000;
+		for (i = 0, j = 0; i < 8; i++)
+			j = addr1[0];
+
+		/*
+		 * Now check whether we got 4MB or 16MB populated
+		 */
+		addr1[0] = 0x12345678;
+		addr1[1] = 0x9abcdef0;
+		addr2[0] = 0xfeedc0de;
+		addr2[1] = 0x47110815;
+		if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) {
+			/* only 4MB populated */
+			memctl->memc_or2 = -(CFG_DRAM_MAX / 4) | OR_CSNT_SAM;
+		}
+	}
+
+	return -(memctl->memc_or2 & 0xffff0000);
+}
+
+/*****************************************************************************
+ * prepare for FLASH detection
+ *****************************************************************************/
+void flash_preinit(void)
+{
+}
+
+/*****************************************************************************
+ * finalize FLASH setup
+ *****************************************************************************/
+void flash_afterinit(uint bank, ulong start, ulong size)
+{
+}
+
+/*****************************************************************************
+ * otherinits after RAM is there and we are relocated to RAM
+ * note: though this is an int function, nobody cares for the result!
+ *****************************************************************************/
+int misc_init_r (void)
+{
+	/* read 'factory' part of EEPROM */
+	extern void read_factory_r (void);
+	read_factory_r ();
+
+	return (0);
+}
diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds
new file mode 100755
index 0000000..b3747e4
--- /dev/null
+++ b/board/emk/top860/u-boot.lds
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug
new file mode 100755
index 0000000..580575a
--- /dev/null
+++ b/board/emk/top860/u-boot.lds.debug
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ep7312/Makefile b/board/ep7312/Makefile
new file mode 100755
index 0000000..c53a3c7
--- /dev/null
+++ b/board/ep7312/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ep7312.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ep7312/config.mk b/board/ep7312/config.mk
new file mode 100755
index 0000000..0ae16a2
--- /dev/null
+++ b/board/ep7312/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xc0f80000
diff --git a/board/ep7312/ep7312.c b/board/ep7312/ep7312.c
new file mode 100755
index 0000000..11eab23
--- /dev/null
+++ b/board/ep7312/ep7312.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Activate LED flasher */
+	IO_LEDFLSH = 0x40;
+
+	/* arch number MACH_TYPE_EDB7312 */
+	gd->bd->bi_arch_number = MACH_TYPE_EDB7312;
+
+	/* location of boot parameters */
+	gd->bd->bi_boot_params = 0xc0020100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
diff --git a/board/ep7312/flash.c b/board/ep7312/flash.c
new file mode 100755
index 0000000..272a9e5
--- /dev/null
+++ b/board/ep7312/flash.c
@@ -0,0 +1,341 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x1000000
+#define MAIN_SECT_SIZE  0x20000
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+		printf ("28F128J3 (128Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);
+
+			*addr = 0x20;		/* erase setup */
+			*addr = 0xD0;		/* erase confirm */
+
+			while ((*addr & 0x80) != 0x80) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+
+			/* clear status register command */
+			*addr = 0x50;
+			/* reset to read mode */
+			*addr = 0xFF;
+		}
+		printf ("ok.\n");
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+  outahere:
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) dest, val;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* clear status register command */
+	*addr = 0x50;
+
+	/* program set-up command */
+	*addr = 0x40;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((val = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0xB0;
+			goto outahere;
+		}
+	}
+
+	if (val & 0x1A) {			/* check for error */
+		printf ("\nFlash write error %02x at address %08lx\n",
+				(int) val, (unsigned long) dest);
+		if (val & (1 << 3)) {
+			printf ("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if (val & (1 << 1)) {
+			printf ("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if (val & (1 << 4)) {
+			printf ("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}
+
+  outahere:
+	/* read array command */
+	*addr = 0xFF;
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);			/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/board/ep7312/lowlevel_init.S b/board/ep7312/lowlevel_init.S
new file mode 100755
index 0000000..5dadb31
--- /dev/null
+++ b/board/ep7312/lowlevel_init.S
@@ -0,0 +1,95 @@
+/*
+ * Memory Setup stuff - taken from ???
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+SYSCON1:	.long	0x80000100
+SYSCON2:	.long	0x80001100
+SYSCON3:	.long	0x80002200
+MEMCFG1:	.long	0x80000180
+MEMCFG2:	.long	0x800001C0
+SDCONF:		.long	0x80002300
+SDRFPR:		.long	0x80002340
+
+syscon1_val:	.long	0x00040100
+syscon2_val:	.long	0x00000102
+syscon3_val:	.long	0x0000020E
+memcfg1_val:	.long	0x1f101710
+memcfg2_mask:	.long	0x0000ffff @ only set lower 16 bits
+memcfg2_val:	.long	0x00001f13 @ upper 16 bits are reserved for CS7 + CS6
+sdrfpr_val:	.long	0x00000240
+sdconf_val:	.long	0x00000522
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+	/*
+	 * SYSCON1-3
+	 */
+	ldr	r0, SYSCON1
+	ldr	r1, syscon1_val
+	str	r1, [r0]
+
+	ldr	r0, SYSCON2
+	ldr	r1, syscon2_val
+	str	r1, [r0]
+
+	ldr	r0, SYSCON3
+	ldr	r1, syscon3_val
+	str	r1, [r0]
+
+	/*
+	 * MEMCFG1
+	 */
+	ldr	r0, MEMCFG1
+	ldr	r1, memcfg1_val
+	str	r1, [r0]
+
+	/*
+	 * MEMCFG2
+	 */
+	ldr	r0, MEMCFG2
+	ldr	r2, [r0]
+	ldr	r1, memcfg2_mask
+	bic	r2, r2, r1
+	ldr	r1, memcfg2_val
+	orr	r2, r2, r1
+	str	r2, [r0]
+
+	/*
+	 * SDRFPR,SDCONF
+	 */
+	ldr	r0, SDCONF
+	ldr	r1, sdconf_val
+	str	r1, [r0]
+
+	ldr	r0, SDRFPR
+	ldr	r1, sdrfpr_val
+	str	r1, [r0]
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/board/ep7312/u-boot.lds b/board/ep7312/u-boot.lds
new file mode 100755
index 0000000..1122d75
--- /dev/null
+++ b/board/ep7312/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm720t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile
new file mode 100755
index 0000000..8b10993
--- /dev/null
+++ b/board/ep8248/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ep8248/config.mk b/board/ep8248/config.mk
new file mode 100755
index 0000000..eda523b
--- /dev/null
+++ b/board/ep8248/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EP82xx series boards by Embedded Planet
+#
+
+TEXT_BASE = 0xFFF00000
diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c
new file mode 100755
index 0000000..69975ca
--- /dev/null
+++ b/board/ep8248/ep8248.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Embedded Planet EP8248 boards.
+ * Tested on EP8248E.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
+	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
+	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
+	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
+	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
+	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
+	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
+	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
+	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
+	/* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK10) */
+	/* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK11) */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
+	/* PC19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK13) */
+	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
+	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
+	/* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
+	/* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
+	/* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
+	/* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
+	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
+	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
+	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
+	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
+	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
+	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
+	/* PD15 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SDA         */
+	/* PD14 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SCL         */
+	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
+	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
+	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
+	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
+	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
+	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    }
+};
+
+int board_early_init_f (void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	bcsr[4] |= 0x30; /* Turn the LEDs off */
+
+#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
+	bcsr[6] |= 0x10;
+#endif
+#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
+	bcsr[7] |= 0x10;
+#endif
+
+#if CFG_FCC1
+	bcsr[8] |= 0xC0;
+#endif /* CFG_FCC1 */
+#if CFG_FCC2
+	bcsr[8] |= 0x30;
+#endif /* CFG_FCC2 */
+
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	long int msize = 16L << (bcsr[2] & 3);
+
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
+	uchar c = 0xFF;
+	uint psdmr = CFG_PSDMR;
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or1  = CFG_SDRAM_OR;
+	memctl->memc_br1  = CFG_SDRAM_BR;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+	*ramaddr = c;
+#endif /* !CFG_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	puts("Board: ");
+	switch (bcsr[0]) {
+	case 0x0C:
+		printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
+		break;
+	default:
+		printf("unknown: ID=%02X\n", bcsr[0]);
+	}
+
+	return 0;
+}
diff --git a/board/ep8248/u-boot.lds b/board/ep8248/u-boot.lds
new file mode 100755
index 0000000..18c4b46
--- /dev/null
+++ b/board/ep8248/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/ep8260/Makefile b/board/ep8260/Makefile
new file mode 100755
index 0000000..477e5ee
--- /dev/null
+++ b/board/ep8260/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o mii_phy.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/ep8260/config.mk b/board/ep8260/config.mk
new file mode 100755
index 0000000..eaf1560
--- /dev/null
+++ b/board/ep8260/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EP8260 boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_ep8260.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+#TEXT_BASE = 0x00100000
+#TEXT_BASE = 0xFF000000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c
new file mode 100755
index 0000000..b9e1df4
--- /dev/null
+++ b/board/ep8260/ep8260.c
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "ep8260.h"
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA30 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA29 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA28 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA27 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA26 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA21 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA20 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA19 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA18 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA17 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA16 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA15 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA14 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB30 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB29 */ {   0,   1,   1,   1,   0,   0   }, /*  */
+	/* PB28 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB27 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB26 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB25 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB24 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB23 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB22 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PB21 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB20 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB19 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB18 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /*  */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC19 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC18 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CLK15 */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CLK16 */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /*  */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /*  */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /*  */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /*  */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /*  */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /*  */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Setup CS4 to enable the Board Control/Status registers.
+ * Otherwise the smcs won't work.
+*/
+int board_early_init_f (void)
+{
+	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br4 = CFG_BR4_PRELIM;
+	memctl->memc_or4 = CFG_OR4_PRELIM;
+	regs->bcsr1 = 0x62;	/* to enable terminal on SMC1 */
+	regs->bcsr2 = 0x30;	/* enable NVRAM and writing FLASH */
+	return 0;
+}
+
+void reset_phy (void)
+{
+	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+
+	regs->bcsr4 = 0xC0;
+}
+
+/*
+ * Check Board Identity:
+ * I don' know, how the next board revisions will be coded.
+ * Thats why its a static interpretation ...
+*/
+
+int checkboard (void)
+{
+	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+	uint major = 0, minor = 0;
+
+	switch (regs->bcsr0) {
+	case 0x02:
+		major = 1;
+		break;
+	case 0x03:
+		major = 1;
+		minor = 1;
+		break;
+	case 0x06:
+		major = 1;
+		minor = 3;
+		break;
+	default:
+		break;
+	}
+	printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
+		major, minor);
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0;
+	volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110;
+
+/*
+	ulong psdmr = CFG_PSDMR;
+#ifdef CFG_LSDRAM
+	ulong lsdmr = CFG_LSDMR;
+#endif
+*/
+	long size = CFG_SDRAM0_SIZE;
+	int i;
+
+
+/*
+* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+*
+* "At system reset, initialization software must set up the
+*  programmable parameters in the memory controller banks registers
+*  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+*  system software should execute the following initialization sequence
+*  for each SDRAM device.
+*
+*  1. Issue a PRECHARGE-ALL-BANKS command
+*  2. Issue eight CBR REFRESH commands
+*  3. Issue a MODE-SET command to initialize the mode register
+*
+*  The initial commands are executed by setting P/LSDMR[OP] and
+*  accessing the SDRAM with a single-byte transaction."
+*
+* The appropriate BRx/ORx registers have already been set when we
+* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+*/
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+#ifndef CFG_RAMBOOT
+#ifdef CFG_LSDRAM
+	size += CFG_SDRAM1_SIZE;
+	ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c;
+	memctl->memc_lsrt = CFG_LSRT;
+
+	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+#endif /* CFG_LSDRAM */
+#endif /* CFG_RAMBOOT */
+	return (size * 1024 * 1024);
+}
diff --git a/board/ep8260/ep8260.h b/board/ep8260/ep8260.h
new file mode 100755
index 0000000..3032b14
--- /dev/null
+++ b/board/ep8260/ep8260.h
@@ -0,0 +1,24 @@
+#ifndef __EP8260_H__
+#define __EP8260_H__
+
+typedef struct tt_ep_regs {
+	volatile unsigned char bcsr0;
+	volatile unsigned char bcsr1;
+	volatile unsigned char bcsr2;
+	volatile unsigned char bcsr3;
+	volatile unsigned char bcsr4;
+	volatile unsigned char bcsr5;
+	volatile unsigned char bcsr6;
+	volatile unsigned char bcsr7;
+	volatile unsigned char bcsr8;
+	volatile unsigned char bcsr9;
+	volatile unsigned char bcsr10;
+	volatile unsigned char bcsr11;
+	volatile unsigned char bcsr12;
+	volatile unsigned char bcsr13;
+	volatile unsigned char bcsr14;
+	volatile unsigned char bcsr15;
+} t_ep_regs;
+typedef t_ep_regs *tp_ep_regs;
+
+#endif
diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c
new file mode 100755
index 0000000..278d606
--- /dev/null
+++ b/board/ep8260/flash.c
@@ -0,0 +1,411 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * Flash Routines for AMD device AM29DL323DB on the EP8260 board.
+ *
+ * This file is based on board/tqm8260/flash.c.
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset(void)
+{
+	if( flash_info[0].flash_id != FLASH_UNKNOWN ) {
+		V_ULONG( flash_info[0].start[0] ) = 0x00F000F0;
+		V_ULONG( flash_info[0].start[0] + 4 ) = 0x00F000F0;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size( ulong baseaddr, flash_info_t *info )
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	/* Write auto select command sequence and test FLASH answer */
+	V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG(baseaddr + ((ulong)0x02AA << 3)) = 0x00550055;
+	V_ULONG(baseaddr + ((ulong)0x0555 << 3)) = 0x00900090;
+	V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG(baseaddr + 4 + ((ulong)0x02AA << 3)) = 0x00550055;
+	V_ULONG(baseaddr + 4 + ((ulong)0x0555 << 3)) = 0x00900090;
+
+	flashtest_h = V_ULONG(baseaddr);		/* manufacturer ID	   */
+	flashtest_l = V_ULONG(baseaddr + 4);
+
+	if ((int)flashtest_h == AMD_MANUFACT) {
+		info->flash_id = FLASH_MAN_AMD;
+	} else {
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);  				/* no or unknown flash	   */
+	}
+
+	flashtest_h = V_ULONG(baseaddr + 8);	        /* device ID		   */
+	flashtest_l = V_ULONG(baseaddr + 12);
+	if (flashtest_h != flashtest_l) {
+		info->flash_id = FLASH_UNKNOWN;
+		return(0);
+	}
+
+	switch((int)flashtest_h) {
+	case AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;	 /* 4 * 4 MB = 16 MB	*/
+		break;
+	case AMD_ID_LV640U:	/* AMDLV640 and AMDLV641 have same ID */
+		info->flash_id += FLASH_AMLV640U;
+		info->sector_count = 128;
+		info->size = 0x02000000; 	/* 4 * 8 MB = 32 MB	*/
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return(0);  			 	/* no or unknown flash	   */
+	}
+
+	if(flashtest_h == AMD_ID_LV640U) {
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+	} else {
+		/* set up sector start adress table (bottom sector type) */
+		for (i = 0; i < 8; i++) {
+			info->start[i] = baseaddr + (i * 0x00008000);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
+		}
+	}
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if ((V_ULONG( info->start[i] + 16 ) & 0x00010001) ||
+		    (V_ULONG( info->start[i] + 20 ) & 0x00010001)) {
+			info->protect[i] = 1;		/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset();
+	return(info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0>>20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case FLASH_MAN_AMD:	    printf ("AMD ");		    break;
+	default:		    printf ("Unknown Vendor ");	    break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDL323B:	printf ("29DL323B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMLV640U:	printf ("29LV640U (64 M, uniform sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+			);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00800080;
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00800080;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			V_ULONG( info->start[sect] ) = 0x00300030;
+			V_ULONG( info->start[sect] + 4 ) = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 ||
+	       (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080)
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+ DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+static int write_dword (flash_info_t *, ulong, unsigned char *);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);	/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i-l) >= cc) ? V_BYTE(dp+i) : *src++;
+		if ((rc = write_dword(info, dp, bb)) != 0)
+		{
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword(info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp  += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : V_BYTE(dp+i);
+	}
+	return (write_dword(info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata)
+{
+	ulong start;
+	ulong cl = 0, ch =0;
+	int flag, i;
+
+	for (ch=0, i=0; i < 4; i++)
+		ch = (ch << 8) + *pdata++;	/* high word	*/
+	for (cl=0, i=0; i < 4; i++)
+		cl = (cl << 8) + *pdata++;	/* low word	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & ch)	!= ch
+	    ||(*((vu_long *)(dest + 4)) & cl)	!= cl)
+	{
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + (0x0555 << 3) ) = 0x00A000A0;
+	V_ULONG( dest ) = ch;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00AA00AA;
+	V_ULONG( info->start[0] + 4 + (0x02AA << 3) ) = 0x00550055;
+	V_ULONG( info->start[0] + 4 + (0x0555 << 3) ) = 0x00A000A0;
+	V_ULONG( dest + 4 ) = cl;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) ||
+	       ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/ep8260/mii_phy.c b/board/ep8260/mii_phy.c
new file mode 100755
index 0000000..813f020
--- /dev/null
+++ b/board/ep8260/mii_phy.c
@@ -0,0 +1,107 @@
+#include <common.h>
+#include <mii_phy.h>
+#include "ep8260.h"
+
+#define MII_MDIO	0x01
+#define MII_MDCK	0x02
+#define MII_MDIR	0x04
+
+void
+mii_discover_phy(void)
+{
+    int known;
+    unsigned short phy_reg;
+    unsigned long phy_id;
+
+    known = 0;
+    printf("Discovering phy @ 0: ");
+    phy_id = mii_phy_read(2) << 16;
+    phy_id |= mii_phy_read(3);
+    if ((phy_id & 0xFFFFFC00) == 0x00137800) {
+	printf("Level One ");
+	if ((phy_id & 0x000003F0) == 0xE0) {
+	    printf("LXT971A Revision %d\n", (int)(phy_id & 0xF));
+	    known = 1;
+	}
+	else printf("unknown type\n");
+    }
+    else printf("unknown OUI = 0x%08lX\n", phy_id);
+
+    phy_reg = mii_phy_read(1);
+    if (!(phy_reg & 0x0004)) printf("Link is down\n");
+    if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n");
+    if (phy_reg & 0x0002) printf("Jabber condition detected\n");
+    if (phy_reg & 0x0010) printf("Remote fault condition detected \n");
+
+    if (known) {
+	phy_reg = mii_phy_read(17);
+	if (phy_reg & 0x0400)
+	    printf("Phy operating at %d MBit/s in %s-duplex mode\n",
+		phy_reg & 0x4000 ? 100 : 10,
+		phy_reg & 0x0200 ? "full" : "half");
+	else
+	    printf("bad link!!\n");
+/*
+left  off: no link, green 100MBit, yellow 10MBit
+right off: no activity, green full-duplex, yellow half-duplex
+*/
+	mii_phy_write(20, 0x0452);
+    }
+}
+
+unsigned short
+mii_phy_read(unsigned short reg)
+{
+    int i;
+    unsigned short tmp, val = 0, adr = 0;
+    t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
+
+    tmp = 0x6002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    regs->bcsr4 |= MII_MDIR;
+    for (i = 0; i < 16; i++) {
+	val <<= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK);
+	if (regs->bcsr4 & MII_MDIO) val |= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK);
+    }
+    return val;
+}
+
+void
+mii_phy_write(unsigned short reg, unsigned short val)
+{
+    int i;
+    unsigned short tmp, adr = 0;
+    t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
+
+    tmp = 0x5002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (val & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	val <<= 1;
+    }
+}
diff --git a/board/ep8260/u-boot.lds b/board/ep8260/u-boot.lds
new file mode 100755
index 0000000..4250e83
--- /dev/null
+++ b/board/ep8260/u-boot.lds
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2001, 2002, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/opt/cross/lib); SEARCH_DIR(/opt/cross/powerpc-linux/lib);
+/* SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); */
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+/*    common/environment.o(.text) */
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/eric/Makefile b/board/eric/Makefile
new file mode 100755
index 0000000..f55e7e2
--- /dev/null
+++ b/board/eric/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/eric/config.mk b/board/eric/config.mk
new file mode 100755
index 0000000..dd0b412
--- /dev/null
+++ b/board/eric/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
diff --git a/board/eric/eric.c b/board/eric/eric.c
new file mode 100755
index 0000000..5413ae1
--- /dev/null
+++ b/board/eric/eric.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include "eric.h"
+#include <asm/processor.h>
+
+#define PPC405GP_GPIO0_OR      0xef600700	/* GPIO Output */
+#define PPC405GP_GPIO0_TCR     0xef600704	/* GPIO Three-State Control */
+#define PPC405GP_GPIO0_ODR     0xef600718	/* GPIO Open Drain */
+#define PPC405GP_GPIO0_IR      0xef60071c	/* GPIO Input */
+
+int board_early_init_f (void)
+{
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the ERIC board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive
+   |       IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive
+   |       IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive
+   |                          indicates NO Power or HOST RESET active
+   |                          check GPIO7 (HOST RESET#) and GPIO8 (NO Power#)
+   |                          for real IRQ source
+   |       IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive
+   |        -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting
+   |           PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR,
+   |           else tristate)
+   | Note for ERIC board:
+   |       An interrupt taken for the HOST (IRQ 28) indicates that
+   |       the HOST wrote a "1" to one of the following locations
+   |       - VGA CRT_GPIO0 (if R1216 is loaded)
+   |       - VGA CRT_GPIO1 (if R1217 is loaded)
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all SMI to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF88);	/* set int polarities; IRQ3 to 1 */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels, UART0 is EDGE */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	mtdcr (cntrl0, 0x00002000);	/* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
+
+	out32 (PPC405GP_GPIO0_OR, 0x60000000);	/*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
+	out32 (PPC405GP_GPIO0_TCR, 0x7E400000);
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+	char *e;
+
+	puts ("Board: ");
+
+	if (!s || strncmp (s, "ERIC", 9)) {
+		puts ("### No HW ID - assuming ERIC");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		for (; s < e; ++s) {
+			putc (*s);
+		}
+	}
+
+
+	putc ('\n');
+
+	return (0);
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+/*
+  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  the necessary info for SDRAM controller configuration
+*/
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+long int initdram (int board_type)
+{
+#ifndef CONFIG_ERIC
+	int i;
+	unsigned char datain[128];
+	int TotalSize;
+#endif
+
+
+#ifdef CONFIG_ERIC
+	/*
+	 * we have no EEPROM on ERIC
+	 * so let init.S do the init job for SDRAM
+	 * and simply return 32MByte here
+	 */
+	return (CFG_SDRAM_SIZE * 1024 * 1024);
+#else
+
+	/* Read Serial Presence Detect Information */
+	for (i = 0; i < 128; i++)
+		datain[i] = 127;
+	i2c_send (SPD_EEPROM_ADDRESS, 0, 1, datain, 128);
+	printf ("\nReading DIMM...\n");
+#if 0
+	for (i = 0; i < 128; i++) {
+		printf ("%d=0x%x ", i, datain[i]);
+		if (((i + 1) % 10) == 0)
+			printf ("\n");
+	}
+	printf ("\n");
+#endif
+
+  /*****************************/
+	/* Retrieve interesting data */
+  /*****************************/
+	/* size of a SDRAM bank */
+	/* Number of bytes per side / number of banks per side */
+	if (datain[31] == 0x08)
+		TotalSize = 32;
+	else if (datain[31] == 0x10)
+		TotalSize = 64;
+	else {
+		printf ("IIC READ ERROR!!!\n");
+		TotalSize = 32;
+	}
+
+	/* single-sided DIMM or double-sided DIMM? */
+	if (datain[5] != 1) {
+		/* double-sided DIMM => SDRAM banks 0..3 are valid */
+		printf ("double-sided DIMM\n");
+		TotalSize *= 2;
+	}
+	/* else single-sided DIMM => SDRAM bank 0 and bank 2 are valid */
+	else {
+		printf ("single-sided DIMM\n");
+	}
+
+
+	/* return size in Mb unit => *(1024*1024) */
+	return (TotalSize * 1024 * 1024);
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: xxx MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/eric/eric.h b/board/eric/eric.h
new file mode 100755
index 0000000..b50d521
--- /dev/null
+++ b/board/eric/eric.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/board/eric/flash.c b/board/eric/flash.c
new file mode 100755
index 0000000..c08a760
--- /dev/null
+++ b/board/eric/flash.c
@@ -0,0 +1,1128 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+
+#ifdef CFG_FLASH_16BIT
+#define FLASH_WORD_SIZE	unsigned short
+#define	FLASH_ID_MASK	0xFFFF
+#else
+#define FLASH_WORD_SIZE unsigned long
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+/* stolen from esteem192e/flash.c */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
+
+#ifndef CFG_FLASH_16BIT
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+#else
+static int write_short (flash_info_t *info, ulong dest, ushort data);
+#endif
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Only one bank */
+	if (CFG_MAX_FLASH_BANKS == 1)
+	  {
+	    /* Setup offsets */
+	    flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	    /* Monitor protection ON by default */
+#if 0	    /* sand: */
+	    (void)flash_protect(FLAG_PROTECT_SET,
+				FLASH_BASE0_PRELIM-monitor_flash_len+size_b0,
+				FLASH_BASE0_PRELIM-1+size_b0,
+				&flash_info[0]);
+#else
+	    (void)flash_protect(FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE+monitor_flash_len-1,
+				&flash_info[0]);
+#endif
+	    size_b1 = 0 ;
+	    flash_info[0].size = size_b0;
+	  }
+
+	/* 2 banks */
+	else
+	  {
+	    size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	    /* Re-do sizing to get full correct info */
+
+	    if (size_b1)
+	      {
+		mtdcr(ebccfga, pb0cr);
+		pbcr = mfdcr(ebccfgd);
+		mtdcr(ebccfga, pb0cr);
+		base_b1 = -size_b1;
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
+		mtdcr(ebccfgd, pbcr);
+		/*          printf("pb1cr = %x\n", pbcr); */
+	      }
+
+	    if (size_b0)
+	      {
+		mtdcr(ebccfga, pb1cr);
+		pbcr = mfdcr(ebccfgd);
+		mtdcr(ebccfga, pb1cr);
+		base_b0 = base_b1 - size_b0;
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+		mtdcr(ebccfgd, pbcr);
+		/*            printf("pb0cr = %x\n", pbcr); */
+	      }
+
+	    size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
+
+	    flash_get_offsets (base_b0, &flash_info[0]);
+
+	    /* monitor protection ON by default */
+#if 0	    /* sand: */
+	    (void)flash_protect(FLAG_PROTECT_SET,
+				FLASH_BASE0_PRELIM-monitor_flash_len+size_b0,
+				FLASH_BASE0_PRELIM-1+size_b0,
+				&flash_info[0]);
+#else
+	    (void)flash_protect(FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE+monitor_flash_len-1,
+				&flash_info[0]);
+#endif
+
+	    if (size_b1) {
+	      /* Re-do sizing to get full correct info */
+	      size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
+
+	      flash_get_offsets (base_b1, &flash_info[1]);
+
+	      /* monitor protection ON by default */
+	      (void)flash_protect(FLAG_PROTECT_SET,
+				  base_b1+size_b1-monitor_flash_len,
+				  base_b1+size_b1-1,
+				  &flash_info[1]);
+	      /* monitor protection OFF by default (one is enough) */
+	      (void)flash_protect(FLAG_PROTECT_CLEAR,
+				  base_b0+size_b0-monitor_flash_len,
+				  base_b0+size_b0-1,
+				  &flash_info[0]);
+	    } else {
+	      flash_info[1].flash_id = FLASH_UNKNOWN;
+	      flash_info[1].sector_count = -1;
+	    }
+
+	    flash_info[0].size = size_b0;
+	    flash_info[1].size = size_b1;
+	  }/* else 2 banks */
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F320J3A ||
+	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A ||
+	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) {
+	    for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base + (i * info->size/info->sector_count);
+	    }
+	} else if (info->flash_id & FLASH_BTYPE) {
+	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CFG_FLASH_16BIT
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00008000;
+		info->start[3] = base + 0x0000C000;
+		info->start[4] = base + 0x00010000;
+		info->start[5] = base + 0x00014000;
+		info->start[6] = base + 0x00018000;
+		info->start[7] = base + 0x0001C000;
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x000E0000;
+		}
+	       }
+	     else {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	       }
+#else
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00002000;
+		info->start[2] = base + 0x00004000;
+		info->start[3] = base + 0x00006000;
+		info->start[4] = base + 0x00008000;
+		info->start[5] = base + 0x0000A000;
+		info->start[6] = base + 0x0000C000;
+		info->start[7] = base + 0x0000E000;
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00070000;
+		}
+	       }
+	     else {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	       }
+#endif
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CFG_FLASH_16BIT
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00014000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x0001C000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+
+	       } else {
+
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	       }
+#else
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000A000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x0000E000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+
+	       } else {
+
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	       }
+#endif
+	}
+
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[]=", bottom boot sect)\n";
+	uchar topboot[]=", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	if (info->flash_id & 0x0001 ) {
+	boottype = botboot;
+	} else {
+	boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit%s",boottype);
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit%s",boottype);
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit%s",boottype);
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit%s",boottype);
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit%s",boottype);
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit%s",boottype);
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit%s",boottype);
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL800B:	printf ("INTEL28F800B (8 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL800T:	printf ("INTEL28F800T (8 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL160B:	printf ("INTEL28F160B (16 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL160T:	printf ("INTEL28F160T (16 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL320B:	printf ("INTEL28F320B (32 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL320T:	printf ("INTEL28F320T (32 Mbit%s",boottype);
+				break;
+
+#if 0 /* enable when devices are available */
+
+	case FLASH_INTEL640B:	printf ("INTEL28F640B (64 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL640T:	printf ("INTEL28F640T (64 Mbit%s",boottype);
+				break;
+#endif
+	case FLASH_28F320J3A:	printf ("INTEL28F320J3A (32 Mbit%s",boottype);
+				break;
+	case FLASH_28F640J3A:	printf ("INTEL28F640J3A (64 Mbit%s",boottype);
+				break;
+	case FLASH_28F128J3A:	printf ("INTEL28F128J3A (128 Mbit%s",boottype);
+				break;
+
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	short i;
+	ulong base = (ulong)addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+
+#ifndef CFG_FLASH_16BIT
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if(addr[0x0000] != 0x00890089){
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+#else
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x0089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x0090;
+
+	if(addr[0x0000] != 0x0089){
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0090;
+#endif
+	}
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+
+	case (AMD_ID_LV400T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV160T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case (AMD_ID_LV320T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_LV320B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+
+	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800T;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160T;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+#if 0 /* enable when devices are available */
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+#endif
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 32 MBit  	*/
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 64 MBit  	*/
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 128 MBit  	*/
+
+	default:
+		/* FIXME*/
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets(base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+		if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){
+		   *addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+		} else {
+		   *addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+		}
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+
+	volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
+	int flag, prot, sect, l_sect, barf;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    ((info->flash_id > FLASH_AMD_COMP) &&
+	     ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+    if(info->flash_id < FLASH_AMD_COMP) {
+#ifndef CFG_FLASH_16BIT
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+#else
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+	addr[0x0555] = 0x0080;
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+#endif
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+			addr[0] = (0x00300030 & FLASH_ID_MASK);
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
+	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
+			  (0x00800080&FLASH_ID_MASK)  )
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+    } else {
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			barf = 0;
+#ifndef CFG_FLASH_16BIT
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00200020;
+			addr[0] = 0x00D000D0;
+			while(!(addr[0] & 0x00800080));	/* wait for error or finish */
+			if( addr[0] & 0x003A003A) {	/* check for error */
+				barf = addr[0] & 0x003A0000;
+				if( barf ) {
+					barf >>=16;
+				} else {
+					barf = addr[0] & 0x0000003A;
+				}
+			}
+#else
+			addr = (vu_short*)(info->start[sect]);
+			addr[0] = 0x0020;
+			addr[0] = 0x00D0;
+			while(!(addr[0] & 0x0080));	/* wait for error or finish */
+			if( addr[0] & 0x003A)	/* check for error */
+				barf = addr[0] & 0x003A;
+#endif
+			if(barf) {
+				printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
+				if(barf & 0x0002) printf("Block locked, not erased.\n");
+				if((barf & 0x0030) == 0x0030)
+					printf("Command Sequence error.\n");
+				if((barf & 0x0030) == 0x0020)
+					printf("Block Erase error.\n");
+				if(barf & 0x0008) printf("Vpp Low error.\n");
+				rcode = 1;
+			} else printf(".");
+			l_sect = sect;
+		}
+	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+
+	}
+
+    }
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*flash_info_t *addr2info (ulong addr)
+{
+	flash_info_t *info;
+	int i;
+
+	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+		if ((addr >= info->start[0]) &&
+		    (addr < (info->start[0] + info->size)) ) {
+			return (info);
+		}
+	}
+
+	return (NULL);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+
+/*int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+	int i;
+	ulong         end        = addr + cnt - 1;
+	flash_info_t *info_first = addr2info (addr);
+	flash_info_t *info_last  = addr2info (end );
+	flash_info_t *info;
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	if (!info_first || !info_last) {
+		return (8);
+	}
+
+	for (info = info_first; info <= info_last; ++info) {
+		ulong b_end = info->start[0] + info->size;*/	/* bank end addr */
+/*		short s_end = info->sector_count - 1;
+		for (i=0; i<info->sector_count; ++i) {
+			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+			if ((end >= info->start[i]) && (addr < e_addr) &&
+			    (info->protect[i] != 0) ) {
+				return (4);
+			}
+		}
+	}
+
+*/	/* finally write data to flash */
+/*	for (info = info_first; info <= info_last && cnt>0; ++info) {
+		ulong len;
+
+		len = info->start[0] + info->size - addr;
+		if (len > cnt)
+			len = cnt;
+		if ((i = write_buff(info, src, addr, len)) != 0) {
+			return (i);
+		}
+		cnt  -= len;
+		addr += len;
+		src  += len;
+	}
+	return (0);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+#ifndef CFG_FLASH_16BIT
+	ulong cp, wp, data;
+	int l;
+#else
+	ulong cp, wp;
+	ushort data;
+#endif
+	int i, rc;
+
+#ifndef CFG_FLASH_16BIT
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+
+#else
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+/*	l = 0; used for debuging  */
+	while (cnt >= 2) {
+		data = 0;
+		for (i=0; i<2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+/*		if(!l){
+			printf("%x",data);
+			l = 1;
+		}  used for debuging */
+
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_short(info, wp, data));
+
+
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifndef CFG_FLASH_16BIT
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start,barf;
+	int flag;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+     if(info->flash_id > FLASH_AMD_COMP) {
+	/* AMD stuff */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+     } else {
+	/* intel stuff */
+	*addr = 0x00400040;
+     }
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+     if(info->flash_id > FLASH_AMD_COMP) {
+
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+     } else {
+
+	while(!(addr[0] & 0x00800080)){  	/* wait for error or finish */
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+	}
+
+	if( addr[0] & 0x003A003A) {	/* check for error */
+		barf = addr[0] & 0x003A0000;
+		if( barf ) {
+			barf >>=16;
+		} else {
+			barf = addr[0] & 0x0000003A;
+		}
+		printf("\nFlash write error at address %lx\n",(unsigned long)dest);
+		if(barf & 0x0002) printf("Block locked, not erased.\n");
+		if(barf & 0x0010) printf("Programming error.\n");
+		if(barf & 0x0008) printf("Vpp Low error.\n");
+		return(2);
+	}
+
+
+     }
+
+	return (0);
+
+}
+
+#else
+
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	ulong start,barf;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+     if(info->flash_id < FLASH_AMD_COMP) {
+	/* AMD stuff */
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+	addr[0x0555] = 0x00A0;
+     } else {
+	/* intel stuff */
+	*addr = 0x00D0;
+	*addr = 0x0040;
+     }
+	*((vu_short *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+     if(info->flash_id < FLASH_AMD_COMP) {
+	  /* AMD stuff */
+	while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+     } else {
+	/* intel stuff */
+	while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+	}
+
+	if( addr[0] & 0x003A) {	/* check for error */
+		barf = addr[0] & 0x003A;
+		printf("\nFlash write error at address %lx\n",(unsigned long)dest);
+		if(barf & 0x0002) printf("Block locked, not erased.\n");
+		if(barf & 0x0010) printf("Programming error.\n");
+		if(barf & 0x0008) printf("Vpp Low error.\n");
+		return(2);
+	}
+	*addr = 0x00B0;
+	*addr = 0x0070;
+	while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+	}
+
+	*addr = 0x00FF;
+
+     }
+
+	return (0);
+
+}
+
+
+#endif
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/eric/init.S b/board/eric/init.S
new file mode 100755
index 0000000..9d4e7ff
--- /dev/null
+++ b/board/eric/init.S
@@ -0,0 +1,355 @@
+/*------------------------------------------------------------------------------+ */
+/* */
+/*       This source code has been made available to you by IBM on an AS-IS */
+/*       basis.  Anyone receiving this source is licensed under IBM */
+/*       copyrights to use it in any way he or she deems fit, including */
+/*       copying it, modifying it, compiling it, and redistributing it either */
+/*       with or without modifications.  No license under IBM patents or */
+/*       patent applications is to be implied by the copyright license. */
+/* */
+/*       Any user of this software should understand that IBM cannot provide */
+/*       technical support for this software and will not be responsible for */
+/*       any consequences resulting from the use of this software. */
+/* */
+/*       Any person who transfers this source code or any derivative work */
+/*       must include the IBM copyright notice, this paragraph, and the */
+/*       preceding two paragraphs in the transferred software. */
+/* */
+/*       COPYRIGHT   I B M   CORPORATION 1995 */
+/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
+/*------------------------------------------------------------------------------- */
+
+/*----------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init */
+/* Description:  Initializes the External Bus Controller for the external */
+/*		peripherals. IMPORTANT: For pass1 this code must run from */
+/*		cache since you can not reliably change a peripheral banks */
+/*		timing register (pbxap) while running code from that bank. */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so */
+/*		we run it from cache. */
+/* */
+/*----------------------------------------------------------------------------- */
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	mflr    r4                      /* save link register */
+	bl      ..getAddr
+..getAddr:
+	mflr    r3                      /* get address of ..getAddr */
+	mtlr    r4                      /* restore link register */
+	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+	mtctr   r4                      /* 10 cache lines to fit this function */
+					/* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+	addi    r3,r3,32		/* move to next cache line */
+	bdnz    ..ebcloop               /* continue for 10 cache lines */
+
+	/*------------------------------------------------------------------- */
+	/* Delay to ensure all accesses to ROM are complete before changing */
+	/* bank 0 timings. 200usec should be enough. */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*------------------------------------------------------------------- */
+	addis	r3,0,0x0
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
+..spinlp:
+	bdnz    ..spinlp                /* spin loop */
+
+	/*----------------------------------------------------------------------- */
+	/* Memory Bank 0 (Flash) initialization (from openbios) */
+	/*----------------------------------------------------------------------- */
+
+	addi    r4,0,pb0ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS0_AP@h
+	ori     r4,r4,CS0_AP@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS0_CR@h
+	ori     r4,r4,CS0_CR@l
+	mtdcr   ebccfgd,r4
+
+	/*----------------------------------------------------------------------- */
+	/* Memory Bank 1 (NVRAM/RTC) initialization */
+	/*----------------------------------------------------------------------- */
+
+	addi    r4,0,pb1ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS1_AP@h
+	ori     r4,r4,CS1_AP@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb1cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS1_CR@h
+	ori     r4,r4,CS1_CR@l
+	mtdcr   ebccfgd,r4
+
+	/*----------------------------------------------------------------------- */
+	/* Memory Bank 2 (A/D converter) initialization */
+	/*----------------------------------------------------------------------- */
+
+	addi    r4,0,pb2ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS2_AP@h
+	ori     r4,r4,CS2_AP@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb2cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS2_CR@h
+	ori     r4,r4,CS2_CR@l
+	mtdcr   ebccfgd,r4
+
+	/*----------------------------------------------------------------------- */
+	/* Memory Bank 3 (Ethernet PHY Reset) initialization */
+	/*----------------------------------------------------------------------- */
+
+	addi    r4,0,pb3ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS3_AP@h
+	ori     r4,r4,CS3_AP@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb3cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS3_CR@h
+	ori     r4,r4,CS3_CR@l
+	mtdcr   ebccfgd,r4
+
+	/*----------------------------------------------------------------------- */
+	/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
+	/*----------------------------------------------------------------------- */
+
+	addi    r4,0,pb4ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS4_AP@h
+	ori     r4,r4,CS4_AP@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb4cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS4_CR@h
+	ori     r4,r4,CS4_CR@l
+	mtdcr   ebccfgd,r4
+
+	/*----------------------------------------------------------------------- */
+	/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
+	/*----------------------------------------------------------------------- */
+
+	addi    r4,0,pb5ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS5_AP@h
+	ori     r4,r4,CS5_AP@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb5cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS5_CR@h
+	ori     r4,r4,CS5_CR@l
+	mtdcr   ebccfgd,r4
+
+	/*----------------------------------------------------------------------- */
+	/* Memory Bank 6 (CPU LED0) initialization */
+	/*----------------------------------------------------------------------- */
+
+	addi    r4,0,pb6ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS6_AP@h
+	ori     r4,r4,CS6_AP@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb6cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS6_CR@h
+	ori     r4,r4,CS5_CR@l
+	mtdcr   ebccfgd,r4
+
+	/*----------------------------------------------------------------------- */
+	/* Memory Bank 7 (CPU LED1) initialization */
+	/*----------------------------------------------------------------------- */
+
+	addi    r4,0,pb7ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS7_AP@h
+	ori     r4,r4,CS7_AP@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb7cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,CS7_CR@h
+	ori     r4,r4,CS7_CR@l
+	mtdcr   ebccfgd,r4
+
+/*	addis   r4,r0,FPGA_BRDC@h */
+/*	ori     r4,r4,FPGA_BRDC@l */
+/*	lbz     r3,0(r4)                /###*get FPGA board control reg */
+/*	eieio */
+/*	ori	r3,r3,0x01              /###*set UART1 control to select CTS/RTS */
+/*	stb     r3,0(r4) */
+
+	nop				/* pass2 DCR errata #8 */
+	blr
+
+/*----------------------------------------------------------------------------- */
+/* Function:     sdram_init */
+/* Description:  Configures SDRAM memory banks on ERIC. */
+/*               We do manually init our SDRAM. */
+/*               If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */
+/*		 It is assumed that a 32MB 12x8(2) SDRAM is used. */
+/*----------------------------------------------------------------------------- */
+	.globl  sdram_init
+
+sdram_init:
+
+	mflr	r31
+
+#ifdef CFG_SDRAM_MANUALLY
+	/*------------------------------------------------------------------- */
+	/* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
+	/*------------------------------------------------------------------- */
+
+	addi    r4,0,mem_mb0cf
+	mtdcr   memcfga,r4
+	addis   r4,0,MB0CF@h
+	ori     r4,r4,MB0CF@l
+	mtdcr   memcfgd,r4
+
+	/*------------------------------------------------------------------- */
+	/* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
+	/*------------------------------------------------------------------- */
+
+	addi    r4,0,mem_mb1cf
+	mtdcr   memcfga,r4
+	addis   r4,0,MB1CF@h
+	ori     r4,r4,MB1CF@l
+	mtdcr   memcfgd,r4
+
+	/*------------------------------------------------------------------- */
+	/* Set MB2CF for bank 2. off */
+	/*------------------------------------------------------------------- */
+
+	addi    r4,0,mem_mb2cf
+	mtdcr   memcfga,r4
+	addis   r4,0,MB2CF@h
+	ori     r4,r4,MB2CF@l
+	mtdcr   memcfgd,r4
+
+	/*------------------------------------------------------------------- */
+	/* Set MB3CF for bank 3. off */
+	/*------------------------------------------------------------------- */
+
+	addi    r4,0,mem_mb3cf
+	mtdcr   memcfga,r4
+	addis   r4,0,MB3CF@h
+	ori     r4,r4,MB3CF@l
+	mtdcr   memcfgd,r4
+
+	/*------------------------------------------------------------------- */
+	/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
+	/* To set the appropriate timings, we need to know the SDRAM speed. */
+	/* We can use the PLB speed since the SDRAM speed is the same as */
+	/* the PLB speed. The PLB speed is the FBK divider times the */
+	/* 405GP reference clock, which on the Walnut board is 33Mhz. */
+	/* Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is */
+	/* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */
+	/* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */
+	/* maybe 133Mhz. */
+	/*------------------------------------------------------------------- */
+
+	mfdcr   r5,strap                 /* determine FBK divider */
+					  /* via STRAP reg to calc PLB speed. */
+					  /* SDRAM speed is the same as the PLB */
+					  /* speed. */
+	rlwinm  r4,r5,4,0x3             /* get FBK divide bits */
+
+..chk_66:
+	cmpi    %cr0,0,r4,0x1
+	bne     ..chk_100
+	addis	r6,0,SDTR_66@h		/* SDTR1 value for 66Mhz */
+	ori     r6,r6,SDTR_66@l
+	addis	r7,0,RTR_66		/* RTR value for 66Mhz */
+	b	..sdram_ok
+..chk_100:
+	cmpi    %cr0,0,r4,0x2
+	bne     ..chk_133
+	addis   r6,0,SDTR_100@h        /* SDTR1 value for 100Mhz */
+	ori     r6,r6,SDTR_100@l
+	addis   r7,0,RTR_100           /* RTR value for 100Mhz */
+	b       ..sdram_ok
+..chk_133:
+	addis   r6,0,0x0107            /* SDTR1 value for 133Mhz */
+	ori     r6,r6,0x4015
+	addis   r7,0,0x07F0            /* RTR value for 133Mhz */
+
+..sdram_ok:
+	/*------------------------------------------------------------------- */
+	/* Set SDTR1 */
+	/*------------------------------------------------------------------- */
+	addi    r4,0,mem_sdtr1
+	mtdcr   memcfga,r4
+	mtdcr   memcfgd,r6
+
+	/*------------------------------------------------------------------- */
+	/* Set RTR */
+	/*------------------------------------------------------------------- */
+	addi    r4,0,mem_rtr
+	mtdcr   memcfga,r4
+	mtdcr   memcfgd,r7
+
+	/*------------------------------------------------------------------- */
+	/* Delay to ensure 200usec have elapsed since reset. Assume worst */
+	/* case that the core is running 200Mhz: */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*------------------------------------------------------------------- */
+	addis   r3,0,0x0000
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2               /* spin loop */
+
+	/*------------------------------------------------------------------- */
+	/* Set memory controller options reg, MCOPT1. */
+	/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
+	/* read/prefetch. */
+	/*------------------------------------------------------------------- */
+	addi    r4,0,mem_mcopt1
+	mtdcr   memcfga,r4
+	addis   r4,0,0x8080             /* set DC_EN=1 */
+	ori     r4,r4,0x0000
+	mtdcr   memcfgd,r4
+
+	/*------------------------------------------------------------------- */
+	/* Delay to ensure 10msec have elapsed since reset. This is */
+	/* required for the MPC952 to stabalize. Assume worst */
+	/* case that the core is running 200Mhz: */
+	/*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
+	/* This delay should occur before accessing SDRAM. */
+	/*------------------------------------------------------------------- */
+	addis   r3,0,0x001E
+	ori     r3,r3,0x8480          /* ensure 10msec have passed since reset */
+	mtctr   r3
+..spinlp3:
+	bdnz    ..spinlp3                /* spin loop */
+
+#else
+/*fixme: do SDRAM Autoconfig from EEPROM here */
+
+#endif
+	mtlr    r31                     /* restore lr */
+	blr
diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds
new file mode 100755
index 0000000..4a0e5b4
--- /dev/null
+++ b/board/eric/u-boot.lds
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/eric/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile
new file mode 100755
index 0000000..67cf29b
--- /dev/null
+++ b/board/esd/adciop/Makefile
@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o ../common/pci.o
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c
new file mode 100755
index 0000000..7a11a12
--- /dev/null
+++ b/board/esd/adciop/adciop.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "adciop.h"
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/* ------------------------------------------------------------------------- */
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * Set port pin in escc2 to keep living, and configure user led output
+	 */
+	*(unsigned char *) 0x2000033e = 0x77;	/* ESCC2: PCR bit3=pwr on, bit7=led out */
+	*(unsigned char *) 0x2000033c = 0x88;	/* ESCC2: PVR pwr on, led off */
+
+	/*
+	 * Init pci regs
+	 */
+	*(unsigned long *) 0x50000304 = 0x02900007;	/* enable mem/io/master bits */
+	*(unsigned long *) 0x500001b4 = 0x00000000;	/* disable pci interrupt output enable */
+	*(unsigned long *) 0x50000354 = 0x00c05800;	/* disable emun interrupt output enable */
+	*(unsigned long *) 0x50000344 = 0x00000000;	/* disable pme interrupt output enable */
+	*(unsigned long *) 0x50000310 = 0x00000000;	/* pcibar0 */
+	*(unsigned long *) 0x50000314 = 0x00000000;	/* pcibar1 */
+	*(unsigned long *) 0x50000318 = 0x00000000;	/* pcibar2 */
+
+	return 0;
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (!i || strncmp (str, "ADCIOP", 6)) {
+		puts ("### No HW ID - assuming ADCIOP\n");
+		return (1);
+	}
+
+	puts (str);
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	return (16 * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/esd/adciop/adciop.h b/board/esd/adciop/adciop.h
new file mode 100755
index 0000000..5fc313a
--- /dev/null
+++ b/board/esd/adciop/adciop.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/board/esd/adciop/config.mk b/board/esd/adciop/config.mk
new file mode 100755
index 0000000..747f29f
--- /dev/null
+++ b/board/esd/adciop/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+# FLASH:
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0xFFFD0000
+
+# SDRAM:
+#TEXT_BASE = 0x00FE0000
diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c
new file mode 100755
index 0000000..d9eccba
--- /dev/null
+++ b/board/esd/adciop/flash.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
+		      FLASH_BASE0_PRELIM+size_b0-1,
+		      &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(FLASH_BASE0_PRELIM + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (FLASH_BASE0_PRELIM + size_b0, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      FLASH_BASE0_PRELIM+size_b0+size_b1-monitor_flash_len,
+			      FLASH_BASE0_PRELIM+size_b0+size_b1-1,
+			      &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect(FLAG_PROTECT_CLEAR,
+			      FLASH_BASE0_PRELIM+size_b0-monitor_flash_len,
+			      FLASH_BASE0_PRELIM+size_b0-1,
+			      &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/board/esd/adciop/u-boot.lds b/board/esd/adciop/u-boot.lds
new file mode 100755
index 0000000..ef937dd
--- /dev/null
+++ b/board/esd/adciop/u-boot.lds
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile
new file mode 100755
index 0000000..8529ec7
--- /dev/null
+++ b/board/esd/apc405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o strataflash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
new file mode 100755
index 0000000..4b2b07a
--- /dev/null
+++ b/board/esd/apc405/apc405.c
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+
+#ifdef CONFIG_LCD_USED
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp[] =
+{
+#include CFG_LCD_LOGO_NAME
+};
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include CFG_LCD_HEADER_NAME
+#endif /* CONFIG_LCD_USED */
+
+
+int board_revision(void)
+{
+	unsigned long cntrl0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of APC405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	switch (value) {
+	case 0x00180000:
+		/* CS2==1 && CS3==1 -> version <= 1.2 */
+		return 2;
+	case 0x00080000:
+		/* CS2==0 && CS3==1 -> version 1.3 */
+		return 3;
+#if 0 /* not yet manufactured ! */
+	case 0x00100000:
+		/* CS2==1 && CS3==0 -> version 1.4 */
+		return 4;
+	case 0x00000000:
+		/* CS2==0 && CS3==0 -> version 1.5 */
+		return 5;
+#endif
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
+	 */
+	out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
+	out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
+	out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
+	out32(GPIO0_OR, 0);                  /* pull prg low            */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+#if 1 /* test-only */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+#else
+	mtebc (epcr, 0x28400000); /* ebc in high-z */
+#endif
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned short *fpga_ctrl2 =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
+	volatile unsigned char *duart0_mcr =
+		(unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr =
+		(unsigned char *)((ulong)DUART1_BA + 4);
+	volatile unsigned short *fuji_lcdbl_pwm =
+		(unsigned short *)((ulong)0xf0100200 + 0xa0);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned long cntrl0Reg;
+
+	/*
+	 * Setup GPIO pins (CS6+CS7 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	/* restore gpio/cs settings */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Write board revision in FPGA
+	 */
+	*fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
+
+	/*
+	 * Enable power on PS/2 interface (with reset)
+	 */
+	*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
+	for (i=0;i<100;i++)
+		udelay(1000);
+	udelay(1000);
+	*fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET;
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+	lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+		 regs_13806_640_480_16bpp,
+		 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+		 logo_bmp, sizeof(logo_bmp));
+
+	/*
+	 * Reset microcontroller and setup backlight PWM controller
+	 */
+	*fpga_mode |= 0x0014;
+	for (i=0;i<10;i++)
+		udelay(1000);
+	*fpga_mode |= 0x001c;
+	*fuji_lcdbl_pwm = 0x00ff;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming APC405");
+	} else {
+		puts(str);
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld\n", gd->board_type);
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_IDE_RESET
+
+void ide_set_reset(int on)
+{
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+	}
+}
+
+#endif /* CONFIG_IDE_RESET */
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/esd/apc405/config.mk b/board/esd/apc405/config.mk
new file mode 100755
index 0000000..11faad2
--- /dev/null
+++ b/board/esd/apc405/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ABG405 boards
+#
+
+TEXT_BASE = 0xFFF80000
diff --git a/board/esd/apc405/fpgadata.c b/board/esd/apc405/fpgadata.c
new file mode 100755
index 0000000..c31625a
--- /dev/null
+++ b/board/esd/apc405/fpgadata.c
@@ -0,0 +1,2280 @@
+  0x1f,0x8b,0x08,0x08,0x30,0x6a,0x41,0x42,0x00,0x03,0x61,0x62,0x67,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x32,0x2e,0x62,0x69,0x74,0x00,0xed,0xbd,0x0b,0x74,0x1c,0xd5,
+  0x95,0x2e,0xbc,0xeb,0x54,0x49,0x2e,0x75,0xb7,0xd4,0xa5,0x87,0x89,0x00,0x63,0x4a,
+  0x2d,0xd9,0xb4,0x3d,0x6d,0xb9,0x2d,0x1b,0x59,0x08,0x59,0x2a,0x3d,0x20,0x1d,0xec,
+  0x60,0x41,0x98,0xc4,0x93,0x9f,0xcb,0x34,0xc4,0xc9,0x78,0xb2,0x9c,0x5c,0x43,0x72,
+  0xe7,0x3a,0x8f,0x21,0x47,0x0f,0xdb,0x6d,0xcb,0xe0,0xb6,0x71,0x12,0x67,0xe2,0x24,
+  0xed,0x07,0x60,0x88,0x27,0xd3,0x96,0x0d,0x96,0x31,0x81,0x92,0x11,0x20,0x1b,0x61,
+  0x2b,0x84,0x49,0xcc,0x23,0xd0,0x26,0x82,0x08,0x22,0x8c,0x30,0x0e,0x91,0xdf,0xff,
+  0xde,0xa7,0xba,0xaa,0xab,0x65,0x67,0xee,0xcc,0xbd,0x97,0xb5,0xfe,0xf5,0xaf,0x74,
+  0xd6,0x4c,0x76,0xaa,0x8e,0x4b,0x55,0xa7,0x4e,0xed,0xfd,0x9d,0xbd,0xbf,0xbd,0x37,
+  0xe4,0xf9,0x47,0xad,0xff,0x00,0x48,0x77,0x82,0x76,0xe7,0x5d,0xff,0x30,0x27,0x7c,
+  0xed,0xdf,0xcf,0xfa,0xfb,0x70,0x55,0xe5,0xd7,0xbf,0xb4,0x18,0xee,0x02,0x4f,0xd5,
+  0x37,0xae,0x0d,0x7f,0xe5,0x1f,0xaa,0xae,0xad,0x86,0x2f,0x81,0xb7,0x2a,0x1c,0xbe,
+  0x76,0x66,0x78,0xf6,0xcc,0xaa,0xd9,0xb0,0x18,0xf2,0x66,0xcd,0xa9,0x0d,0xd7,0xd4,
+  0x86,0x67,0xc1,0x97,0x41,0x2a,0xf4,0x5d,0xc0,0xdf,0xa3,0x3f,0xfa,0xdb,0xaf,0x84,
+  0x81,0x4b,0x00,0x30,0x21,0x2c,0x45,0xe9,0xbf,0xbd,0x61,0x49,0x97,0x80,0x37,0xcc,
+  0x08,0x83,0x49,0xff,0x1b,0xd2,0xe7,0xf3,0xc2,0xa0,0xbb,0xff,0xb7,0x14,0x06,0x03,
+  0x5a,0xa1,0x5e,0x81,0x22,0xf8,0x5f,0xff,0x24,0x50,0xb8,0x2d,0xff,0x57,0xc7,0xb3,
+  0xff,0xc4,0x78,0xfc,0xfd,0x6f,0x8f,0xff,0xcf,0xdc,0x0f,0x80,0xf2,0xbf,0x3d,0x5e,
+  0xfb,0xcf,0x8d,0xb7,0x85,0x0b,0x1a,0xfe,0x8b,0x1c,0x90,0x68,0x76,0x4b,0xfe,0x92,
+  0x60,0x34,0xf4,0xd9,0xd7,0x37,0x73,0xce,0xc3,0x05,0xde,0x90,0xf2,0x9f,0x95,0xbf,
+  0xc5,0x5f,0x08,0xef,0x1d,0x58,0x30,0xd6,0xfc,0x12,0xfb,0x00,0xe6,0xa6,0xfc,0xfd,
+  0xf2,0xbd,0xd0,0xd7,0x3e,0xfb,0xb0,0x6f,0x4c,0x1e,0x85,0x65,0xe9,0xf1,0x5c,0x3b,
+  0x0e,0xfb,0x79,0x65,0xca,0x1b,0x66,0xff,0x68,0xac,0xbb,0xa7,0x7c,0x40,0xed,0xc9,
+  0x7d,0x07,0xd6,0xf1,0x40,0xca,0x1b,0x63,0x21,0xd8,0xc1,0x03,0x83,0x6a,0x0f,0x4b,
+  0x29,0xe1,0xf4,0xf8,0x58,0xce,0x00,0xec,0x86,0x90,0xe9,0xad,0x62,0xc1,0xd8,0x36,
+  0x49,0x37,0x63,0x61,0x96,0x82,0x6d,0x9a,0x6e,0xfe,0x98,0x07,0x16,0xe0,0x34,0xea,
+  0xfd,0xd3,0xc3,0xec,0x2d,0xc9,0xbe,0xbe,0x39,0x71,0x27,0xec,0x87,0xca,0x5e,0x6f,
+  0x92,0x4d,0x97,0x7f,0x0e,0x01,0x53,0x4d,0x06,0x52,0xbc,0x0b,0x02,0xbd,0x5e,0x2e,
+  0xae,0xbf,0xd5,0xf4,0x24,0x9b,0x46,0x95,0xa8,0xfd,0xc0,0x85,0x23,0xa5,0x67,0xa0,
+  0xde,0xf4,0x27,0x65,0x43,0xff,0xa3,0x54,0x6d,0x4e,0x4a,0xb2,0x67,0xe0,0xf7,0x50,
+  0xdd,0xeb,0x5f,0x2b,0x2f,0x80,0x43,0x66,0xd8,0x2c,0x48,0xca,0xa6,0xd2,0x9a,0x1e,
+  0x9e,0x92,0x9e,0x84,0x0b,0xd0,0x60,0x8a,0xaf,0xe0,0x4d,0x14,0xbe,0x37,0x8a,0x4f,
+  0x77,0x46,0xc2,0x23,0x87,0xe4,0xb3,0xfa,0x79,0xbc,0x54,0xfe,0xa8,0x3c,0x06,0xf6,
+  0xf5,0x0d,0x6d,0x27,0xa4,0xaf,0x5f,0xa6,0x7d,0x89,0xce,0x26,0xe5,0x63,0xf0,0x82,
+  0x56,0x65,0xfa,0x3b,0xe5,0xa5,0xf0,0xaa,0x5e,0x4b,0xd7,0x6f,0x55,0xf4,0xf4,0xf8,
+  0xfe,0x9c,0x90,0x86,0xf7,0x6f,0x7a,0x93,0xde,0x28,0xac,0x53,0x66,0xe2,0x3f,0x64,
+  0x29,0x69,0x1d,0xaf,0x36,0x3f,0x03,0x72,0x08,0xda,0x53,0xe5,0x2f,0x2b,0x49,0x76,
+  0x02,0x57,0x7f,0xfa,0x7e,0x72,0x16,0x58,0xf3,0x93,0x64,0x0a,0x0a,0x95,0xbd,0xf3,
+  0xc3,0x45,0xfd,0xd0,0x91,0xd0,0x4d,0x2f,0xe4,0xfa,0x20,0xce,0x83,0xa6,0x1c,0x66,
+  0x63,0x60,0xdf,0x7f,0x54,0x9a,0x0c,0x7b,0xf9,0x8c,0x54,0xd7,0x77,0xd8,0x65,0x2d,
+  0x3f,0x4c,0xcc,0x18,0xf2,0x2e,0x6f,0x3f,0x01,0xab,0xf8,0x94,0x61,0x6f,0x7f,0xee,
+  0x53,0xbc,0x93,0x97,0xa5,0xd4,0xe5,0x97,0xf5,0x3b,0xd7,0x8f,0xa8,0x3e,0xbc,0x6c,
+  0x9d,0xe9,0xaf,0x65,0x01,0xfe,0x51,0x22,0xd4,0xe7,0xbf,0x4e,0xee,0x65,0x1d,0x4a,
+  0x78,0xe4,0x6a,0xc9,0x5b,0xa9,0x0e,0x42,0x8d,0xe9,0x0f,0xcb,0xb7,0x3a,0xab,0xde,
+  0xb8,0x2a,0x3d,0x3f,0x49,0x39,0x05,0x1f,0x68,0x0d,0x7d,0x05,0xa3,0xe5,0xa3,0xc6,
+  0x05,0x4f,0xbd,0x79,0x9f,0x81,0xcf,0x7b,0xce,0x3a,0x35,0x98,0x6b,0xcf,0xcf,0x8e,
+  0x9c,0x91,0xf4,0xfc,0x48,0x2a,0x4e,0x4b,0xfd,0x09,0x1f,0xce,0x36,0xfc,0x1a,0x6a,
+  0xcd,0x7c,0x2e,0x1f,0x87,0xa3,0x7c,0x36,0xcd,0xcf,0x7b,0xce,0xfa,0x89,0x14,0x6e,
+  0x86,0xbd,0x30,0xa3,0xd7,0xbb,0x2c,0x58,0xca,0x56,0x69,0xf3,0x8e,0x5e,0xb1,0x4c,
+  0x1e,0x84,0x87,0xb5,0x69,0xa6,0xd7,0x60,0x67,0x61,0x25,0x94,0x1d,0xf5,0x2e,0x63,
+  0x2f,0x39,0xf3,0x6f,0xc2,0x4f,0xc5,0xf3,0x7a,0xc7,0x58,0x2d,0x3e,0x66,0x08,0x9f,
+  0x2e,0x70,0x42,0x5a,0x95,0x98,0x96,0xca,0x8b,0xb0,0x37,0xe0,0x07,0xed,0xf8,0xe0,
+  0xcb,0xd9,0x28,0xd8,0xf3,0x1f,0x29,0x19,0xb0,0xe7,0x53,0xe5,0x1d,0x10,0x34,0x3d,
+  0x61,0xc6,0xd7,0x6f,0x93,0xa6,0x9b,0xde,0xeb,0xd8,0x00,0xb4,0x97,0x4e,0x35,0x71,
+  0xe9,0xbe,0xe4,0xac,0xcf,0xe1,0x89,0x3b,0xe0,0x34,0xd4,0x73,0x6f,0x42,0xbe,0x9e,
+  0x1f,0x82,0x4a,0xee,0x4b,0xb0,0xd3,0xfc,0x00,0xd4,0xf2,0xfc,0x14,0x1b,0x86,0x37,
+  0x5a,0xfe,0x89,0xdf,0x9f,0x90,0x4f,0x2b,0xce,0xfd,0x43,0x0a,0xc6,0xa0,0x1e,0xfc,
+  0x1c,0xe7,0x67,0x4c,0x49,0x0b,0xc3,0x74,0xa4,0x5d,0x3e,0xa6,0x8e,0xc1,0x13,0x1a,
+  0x1e,0x79,0xc9,0xb9,0x1f,0x55,0x1b,0x82,0x53,0x50,0x6f,0xf8,0xe3,0xf2,0x76,0x38,
+  0x08,0xb5,0xc6,0xba,0x78,0xf9,0x76,0xf5,0x15,0xe8,0x6e,0xbc,0x2f,0x2e,0xe3,0x29,
+  0xa3,0x32,0xea,0x8b,0xcb,0x07,0x9c,0xfb,0xe1,0xca,0x62,0xd8,0x07,0x95,0x86,0x37,
+  0xee,0xa9,0x50,0x57,0xc3,0x57,0x8d,0xae,0x38,0xeb,0x83,0x57,0x78,0xc0,0xf0,0xc5,
+  0xd9,0x90,0x74,0x9d,0x59,0xb9,0x3c,0x18,0xc7,0x15,0x65,0xab,0x85,0xd2,0x9c,0x8a,
+  0xf4,0x78,0x5c,0x3f,0x6d,0xec,0x2b,0x8d,0x5e,0x1a,0xf6,0x23,0x3d,0x60,0xe4,0x25,
+  0xd9,0xdb,0xf0,0x63,0xb5,0xa0,0x45,0x8d,0xb3,0xe7,0x9c,0xf5,0xa0,0x2a,0x0a,0xec,
+  0x82,0x90,0xe1,0xd5,0x8a,0x94,0xf6,0xb6,0x40,0x30,0x32,0x5f,0xcb,0x1d,0x82,0xf5,
+  0x65,0x01,0x43,0xd5,0x58,0x9f,0x8a,0xa7,0x22,0x41,0x8d,0x1d,0x90,0xec,0xf5,0xd0,
+  0x93,0x1f,0x15,0xcf,0xeb,0x5d,0x21,0x97,0x19,0xb1,0xdb,0xaa,0x4b,0x8e,0xf0,0x09,
+  0x29,0x38,0x0a,0x55,0x80,0xef,0xf7,0x98,0xd1,0x03,0xf5,0x25,0x3e,0x7c,0xd1,0x92,
+  0xbd,0x3e,0x37,0x5d,0x95,0x7e,0xde,0x56,0xf9,0xa4,0x71,0xaa,0xe8,0xeb,0x2d,0xde,
+  0x78,0xf1,0x49,0x38,0x55,0x58,0x6f,0x14,0x0c,0xe2,0xf3,0xfe,0x09,0xea,0x5b,0x70,
+  0x2a,0xde,0xc9,0xb5,0xe7,0x73,0x53,0x8e,0x3d,0x3f,0xde,0x29,0xfa,0xc1,0x68,0x7d,
+  0x8b,0x0f,0x87,0xf9,0x5e,0xf4,0x74,0xd3,0x8c,0x7d,0xd3,0x78,0x1b,0xe6,0x36,0x15,
+  0xc4,0xe5,0xe7,0x9c,0xf5,0x53,0xa3,0xa5,0xa0,0x07,0x2a,0x41,0x06,0x8f,0xd4,0x16,
+  0xbb,0xab,0xb6,0x34,0xc6,0x51,0x9f,0x8c,0x19,0x01,0x40,0xfd,0x00,0x5a,0x0f,0x04,
+  0x34,0x14,0x0e,0x3b,0xf3,0xa9,0xde,0xd0,0x67,0x3d,0x6f,0x51,0x3b,0xce,0x4f,0x4b,
+  0xa8,0x55,0xd5,0x02,0xef,0xc0,0x16,0xd0,0x69,0xc6,0xfa,0xf8,0x2e,0xa8,0x68,0xba,
+  0x52,0x2b,0x3a,0xe0,0xe8,0x9f,0xd2,0x89,0xdb,0xad,0xf9,0xd4,0xd8,0x14,0x58,0x9d,
+  0x13,0x34,0xd4,0x78,0x60,0xb1,0xb1,0x1f,0x02,0x86,0x77,0x3d,0xc3,0xa9,0xce,0x9b,
+  0x4e,0xff,0xf0,0x39,0x47,0xff,0x24,0x26,0x3a,0xef,0xb7,0x02,0x56,0xa3,0x10,0x8a,
+  0x37,0xf7,0xc1,0xbb,0xac,0xca,0xf0,0x6f,0xec,0x18,0x82,0x0f,0x3b,0xab,0x0d,0xbc,
+  0xff,0x61,0x47,0x3f,0x04,0xa5,0xed,0xf6,0xf8,0xbe,0xdc,0x53,0xb8,0x1e,0x68,0x36,
+  0xb4,0x77,0xad,0x23,0x78,0x29,0xb3,0xba,0xe9,0xea,0xb8,0x7c,0xc8,0x59,0x3f,0x41,
+  0x2d,0x21,0xe6,0xff,0x6a,0xfe,0x39,0x1d,0xfa,0xa1,0x96,0xa6,0x5d,0x67,0x63,0x93,
+  0xaa,0x00,0xf5,0x4f,0x0a,0xfa,0x55,0xf1,0x22,0x0e,0x65,0xae,0x9f,0x13,0x84,0x27,
+  0x70,0x19,0x7b,0x13,0x2c,0xa8,0xac,0x81,0x00,0x57,0x77,0xb0,0x1d,0xf0,0x79,0x5e,
+  0xcd,0xbd,0x3a,0x3b,0x65,0xdc,0xcf,0xcb,0x93,0xc1,0x44,0xd1,0x21,0xfb,0xf5,0xe2,
+  0xf8,0xb4,0xfe,0x09,0x37,0xf9,0xa0,0x03,0x74,0xf3,0xf2,0x52,0xe6,0x83,0xee,0xb6,
+  0x68,0xaf,0x37,0x9c,0x7b,0x40,0xed,0x30,0xf5,0x51,0x35,0x8c,0xe3,0xed,0xf7,0x9b,
+  0x90,0x26,0xd1,0xf7,0x6b,0x76,0x7d,0x83,0x4d,0xe2,0x1d,0x89,0xb2,0x3e,0x75,0x51,
+  0xfb,0x93,0xec,0x07,0x6c,0x8a,0xe9,0x5d,0x96,0xfb,0x6b,0x75,0x95,0x5a,0xf6,0x96,
+  0xba,0x8c,0xf5,0x6b,0xf6,0x7a,0xdb,0xa1,0x4e,0x86,0x3f,0xf3,0x79,0x29,0xfc,0x48,
+  0x27,0xc3,0xf3,0x3b,0xc2,0xa9,0xfc,0x45,0xf2,0x64,0xed,0x63,0x3e,0xeb,0x98,0x7f,
+  0xb9,0xfc,0x1b,0xf6,0x3c,0x9f,0x9d,0x08,0x2d,0x97,0x0f,0x39,0xfa,0x47,0xbd,0xca,
+  0xd2,0xb7,0xeb,0x92,0x1d,0xef,0x37,0xfd,0xf8,0x96,0x5f,0x1c,0xf0,0x6b,0xb3,0x07,
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diff --git a/board/esd/apc405/logo_640_480_24bpp.c b/board/esd/apc405/logo_640_480_24bpp.c
new file mode 100755
index 0000000..c52a430
--- /dev/null
+++ b/board/esd/apc405/logo_640_480_24bpp.c
@@ -0,0 +1,235 @@
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+  0xf8,0xfb,0x59,0xd9,0x77,0x47,0xb2,0x8d,0x0a,0x33,0x21,0xe4,0x8e,0xae,0x75,0x0f,
+  0xe7,0x6b,0x2d,0x8e,0x8c,0xd5,0xcf,0x1a,0x9b,0x2d,0xe2,0x7a,0xe1,0x7e,0x62,0xdf,
+  0xcf,0xe2,0xbe,0x3b,0x12,0x6c,0x54,0x98,0x8b,0x26,0xdc,0xcf,0x59,0xa1,0xb7,0x35,
+  0xc2,0x57,0x5f,0x30,0x36,0xdb,0xf6,0xdd,0xc2,0x5d,0xc5,0x3e,0xa1,0x95,0x6d,0x72,
+  0x24,0xd5,0xa8,0x30,0x17,0x4d,0xb8,0x9f,0xb3,0x42,0x6f,0x6b,0x84,0xaf,0x1e,0x9b,
+  0x76,0x6c,0x30,0x78,0xbc,0xc0,0x57,0xb4,0xb2,0x4d,0x8e,0xa4,0x9a,0x93,0xe4,0xba,
+  0x09,0xf7,0x73,0x56,0xe8,0x2d,0x8e,0xf0,0xd5,0x63,0xa3,0x4e,0xce,0x06,0x8f,0x17,
+  0xf5,0x90,0x56,0xb6,0xc9,0x91,0x48,0x73,0x92,0xb4,0xc7,0xdb,0x7c,0x09,0xbb,0xd6,
+  0x3d,0x9c,0xaf,0xb5,0x38,0xc2,0x57,0x0f,0x8f,0x3a,0x36,0x18,0x70,0xc1,0xbe,0x9b,
+  0x96,0x27,0xef,0xcc,0x1b,0x13,0x86,0x44,0x2d,0xd2,0xd8,0x1d,0xb1,0x4b,0x27,0x45,
+  0x1d,0x1b,0x0c,0x88,0x78,0x4e,0x8b,0x0b,0xe5,0xc8,0x1f,0xf0,0x39,0x49,0xe6,0x9f,
+  0x55,0x52,0xda,0x22,0x8d,0xc5,0x11,0xb8,0xf4,0x6d,0x72,0x9e,0xcd,0x06,0x6c,0x3f,
+  0xa7,0xd3,0x6a,0x65,0x4e,0x92,0xe1,0x07,0x95,0x17,0xb5,0x48,0x63,0x77,0x04,0x2e,
+  0x9d,0x9a,0xb3,0x2c,0xea,0x42,0x30,0xe0,0x87,0x9d,0x17,0x75,0x5a,0xad,0xcc,0x49,
+  0xd2,0x78,0x44,0x9b,0x3d,0xd8,0xb5,0xee,0xc9,0x94,0x7d,0xf5,0x11,0xb8,0x74,0x52,
+  0xc2,0xca,0xb4,0x3b,0xd9,0x80,0x8d,0x77,0x75,0x5a,0xad,0x74,0x95,0xdd,0xc0,0x2f,
+  0xf5,0xc7,0x90,0xb1,0xee,0xc9,0x94,0x7d,0x0d,0x12,0xb8,0x74,0x52,0xc2,0x9a,0xc0,
+  0x9b,0xa9,0x80,0xff,0x58,0x7b,0x5a,0xa7,0xd5,0x4a,0x7b,0xeb,0xcd,0xf9,0x52,0x7f,
+  0x09,0x19,0xeb,0x9e,0x4c,0xd9,0xd7,0x23,0x81,0x4b,0x87,0x67,0x2b,0x8b,0x1d,0x18,
+  0x0c,0x58,0x7a,0x5d,0xa7,0xd5,0x4a,0x7b,0xeb,0xcd,0xf9,0x52,0x7f,0x06,0x19,0xeb,
+  0x9e,0x4c,0xd9,0xd7,0x23,0x51,0x4b,0x87,0x07,0xab,0x49,0x9e,0x11,0x0c,0x58,0x7a,
+  0x5d,0xa7,0x35,0x4b,0x7b,0xf1,0x4d,0xf8,0x52,0x7f,0x03,0x49,0xeb,0x52,0x4a,0xe7,
+  0xc2,0x3c,0x67,0x1f,0xd8,0x69,0xe5,0xd2,0xde,0x7d,0x13,0xbe,0xa4,0xdb,0xcf,0x5b,
+  0x97,0x1e,0x9a,0x17,0xe6,0x39,0xfe,0xc0,0x4e,0x2b,0x97,0xf6,0xee,0x6b,0xff,0x32,
+  0xee,0xbd,0x60,0x69,0x00,0xfe,0xeb,0xc8,0x03,0x3b,0xad,0x5f,0xda,0xeb,0xaf,0xfd,
+  0x0b,0xbc,0xee,0xb2,0xa5,0x01,0xf8,0xc9,0x91,0x37,0x76,0x5a,0xc5,0xb4,0x37,0x60,
+  0xe3,0x17,0x7b,0xd7,0x95,0xab,0x03,0xf0,0xd1,0xd7,0x6f,0xec,0xb4,0x96,0x69,0x2f,
+  0xc1,0xae,0x2f,0xf0,0x96,0x5b,0x02,0x00,0xf0,0xd1,0x17,0x6f,0xec,0xb4,0xa2,0x69,
+  0xef,0xc1,0x96,0x2f,0xea,0x7e,0xbb,0x02,0x00,0xf0,0xca,0xab,0x67,0x76,0x5a,0xd7,
+  0xb4,0x57,0xe1,0xb4,0x03,0x39,0x78,0xb3,0x8d,0x01,0x00,0x58,0x30,0xb0,0x6e,0xda,
+  0x0b,0x71,0xd4,0x69,0x14,0x1c,0x17,0x00,0x2d,0xa6,0x95,0x4e,0x7b,0x27,0x4e,0x38,
+  0x84,0xca,0xbb,0x03,0xa0,0xc5,0xb4,0xea,0x69,0x6f,0xc6,0xc6,0xbd,0xb7,0xdc,0x1d,
+  0x00,0x2d,0xa6,0x75,0x50,0x7b,0x45,0xb6,0xec,0xba,0xeb,0xe2,0x00,0xe8,0x32,0xad,
+  0x89,0xda,0x8b,0xf2,0x12,0x8d,0x76,0xad,0xb4,0x00,0x7c,0x74,0xd7,0x86,0xba,0x31,
+  0x17,0x01,0x00,0xc5,0x94,0x2f,0x00,0x14,0x53,0xbe,0x00,0x50,0xcc,0xff,0x05,0x00,
+  0x00,0xc5,0x94,0x2f,0xc0,0xa3,0x78,0xcc,0x27,0x08,0x2c,0x5f,0x57,0x06,0x70,0x15,
+  0xde,0xf3,0x5e,0xca,0x17,0xe0,0xc9,0x3c,0xec,0x2d,0x94,0x2f,0x00,0xff,0xe2,0x79,
+  0xaf,0x11,0xdb,0xbc,0x6e,0x07,0xe0,0x1e,0xbc,0xf3,0xa9,0x94,0x2f,0x00,0x5f,0xf3,
+  0xe0,0x87,0x53,0xbe,0x00,0x1c,0xe4,0xf1,0x0f,0xa1,0x79,0x01,0x58,0xa0,0x0b,0x96,
+  0x85,0x37,0xaf,0x33,0x07,0x78,0x1a,0x8d,0x70,0x8a,0xda,0x05,0x20,0x8a,0x82,0x38,
+  0xc2,0xdf,0x79,0x01,0x48,0xa5,0x32,0x7e,0xa2,0x79,0x01,0x28,0xa3,0x3b,0xde,0xd2,
+  0x9a,0xf7,0x39,0x07,0x08,0xc0,0xb2,0xa7,0xb5,0x49,0x5e,0xe7,0xde,0xef,0xac,0x00,
+  0x28,0x70,0xfb,0x5a,0xd1,0xbc,0x00,0x8c,0x75,0xcb,0xc6,0x51,0xbb,0x00,0x5c,0xc5,
+  0x0d,0x3a,0xc8,0x5f,0x78,0x01,0xb8,0x81,0xc9,0xdd,0x94,0x5d,0xb5,0x3a,0x17,0x80,
+  0x76,0xed,0xcd,0x55,0xd6,0xb6,0x6a,0x17,0x80,0xb1,0xea,0xdb,0x50,0xf3,0x02,0xc0,
+  0x47,0xed,0xa5,0xa9,0x73,0x01,0x78,0xb2,0xf6,0x26,0x55,0xb5,0x00,0xd0,0xde,0xb6,
+  0x3a,0x17,0x00,0x3e,0xa5,0x5e,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xea,0xfc,0x03,0x26,
+  0x84,0x0a,0xd6,0x36,0x10,0x0e,0x00,
diff --git a/board/esd/apc405/strataflash.c b/board/esd/apc405/strataflash.c
new file mode 100755
index 0000000..ad7a71d
--- /dev/null
+++ b/board/esd/apc405/strataflash.c
@@ -0,0 +1,789 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI			0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+#if 0 /* test-only */
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#else
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       - CFG_MONITOR_LEN,
+		       - 1, &flash_info[1]);
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		int k;
+		int size;
+		int erased;
+		volatile unsigned long *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+		printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds
new file mode 100755
index 0000000..f7a20d1
--- /dev/null
+++ b/board/esd/apc405/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile
new file mode 100755
index 0000000..a60495a
--- /dev/null
+++ b/board/esd/ar405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c
new file mode 100755
index 0000000..3aac3c6
--- /dev/null
+++ b/board/esd/ar405/ar405.c
@@ -0,0 +1,438 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "ar405.h"
+#include <asm/processor.h>
+#include <command.h>
+
+/*cmd_boot.c*/
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+const unsigned char fpgadata_xl30[] = {
+#include "fpgadata_xl30.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int index, len, i;
+	int status;
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	/* first try 40er image */
+	gd->board_type = 40;
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* try xl30er image */
+		gd->board_type = 30;
+		status = fpga_boot ((unsigned char *) fpgadata_xl30, sizeof (fpgadata_xl30));
+		if (status != 0) {
+			/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+			/* set up serial port with default baudrate */
+			(void) get_clocks ();
+			gd->baudrate = CONFIG_BAUDRATE;
+			serial_init ();
+			console_init_f ();
+#endif
+			printf ("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf ("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}
+
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i = 0; i < 4; i++) {
+				len = fpgadata[index];
+				printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+				index += len + 3;
+			}
+			putc ('\n');
+			/* delayed reboot */
+			for (i = 20; i > 0; i--) {
+				printf ("Rebooting in %2d seconds \r", i);
+				for (index = 0; index < 1000; index++)
+					udelay (1000);
+			}
+			putc ('\n');
+			do_reset (NULL, 0, 0, NULL);
+		}
+	}
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	*(ushort *) 0xf03000ec = 0x0fff;	/* enable all interrupts in fpga */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+	const unsigned char *fpga;
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming AR405");
+	} else {
+		puts(str);
+	}
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	if (gd->board_type == 30) {
+		fpga = fpgadata_xl30;
+	} else {
+		fpga = fpgadata;
+	}
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpga[index];
+		printf ("%s ", &(fpga[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+
+#if 1 /* test-only: some internal test routines... */
+/*
+ * Some test routines
+ */
+int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile uchar *digen = (volatile uchar *)0xf03000b4;
+	volatile ushort *digout = (volatile ushort *)0xf03000b0;
+	volatile ushort *digin = (volatile ushort *)0xf03000a0;
+	int i;
+	int k;
+	int start;
+	int end;
+
+	if (argc != 3) {
+		puts("Usage: digtest n_start n_end (digtest 0 7)\n");
+		return 0;
+	}
+
+	start = simple_strtol (argv[1], NULL, 10);
+	end = simple_strtol (argv[2], NULL, 10);
+
+	/*
+	 * Enable digital outputs
+	 */
+	*digen = 0x08;
+
+	printf("\nStarting digital In-/Out Test from I/O %d to %d (Cntrl-C to abort)...\n",
+	       start, end);
+
+	/*
+	 * Set outputs one by one
+	 */
+	for (;;) {
+		for (i=start; i<=end; i++) {
+			*digout = 0x0001 << i;
+			for (k=0; k<200; k++)
+				udelay(1000);
+
+			if (*digin != (0x0001 << i)) {
+				printf("ERROR: OUT=0x%04X, IN=0x%04X\n", 0x0001 << i, *digin);
+				return 0;
+			}
+
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+		}
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	digtest,	3,	1,	do_digtest,
+	"digtest - Test digital in-/output\n",
+	NULL
+	);
+
+
+#define ERROR_DELTA     256
+
+struct io {
+	volatile short val;
+	short dummy;
+};
+
+int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile short val;
+	int i;
+	int volt;
+	struct io *out;
+	struct io *in;
+
+	out = (struct io *)0xf0300090;
+	in = (struct io *)0xf0300000;
+
+	i = simple_strtol (argv[1], NULL, 10);
+
+	volt = 0;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out[i].val = (volt * 0x7fff) / 10;
+	udelay(10000);
+	val = in[i*2].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in[i*2+1].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	volt = 5;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out[i].val = (volt * 0x7fff) / 10;
+	udelay(10000);
+	val = in[i*2].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in[i*2+1].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	volt = 10;
+	printf("Setting Channel %d to %dV...\n", i, volt);
+	out[i].val = (volt * 0x7fff) / 10;
+	udelay(10000);
+	val = in[i*2].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+	val = in[i*2+1].val;
+	printf("-> InChannel %d: 0x%04x=%dV\n", i*2+1, val, (val * 4000) / 0x7fff);
+	if ((val < ((volt * 0x7fff) / 40) - ERROR_DELTA) ||
+	    (val > ((volt * 0x7fff) / 40) + ERROR_DELTA)) {
+		printf("ERROR! (min=0x%04x max=0x%04x)\n", ((volt * 0x7fff) / 40) - ERROR_DELTA,
+		       ((volt * 0x7fff) / 40) + ERROR_DELTA);
+		return -1;
+	}
+
+	printf("Channel %d OK!\n", i);
+
+	return 0;
+}
+U_BOOT_CMD(
+	anatest,	2,	1,	do_anatest,
+	"anatest - Test analog in-/output\n",
+	NULL
+	);
+
+
+int counter = 0;
+
+void cyclicInt(void *ptr)
+{
+	*(ushort *)0xf03000e8 = 0x0800; /* ack int */
+	counter++;
+}
+
+
+int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile uchar *digout = (volatile uchar *)0xf03000b4;
+	volatile ulong *incin;
+	int i;
+
+	incin = (volatile ulong *)0xf0300040;
+
+	/*
+	 * Clear inc counter
+	 */
+	incin[0] = 0;
+	incin[1] = 0;
+	incin[2] = 0;
+	incin[3] = 0;
+
+	incin = (volatile ulong *)0xf0300050;
+
+	/*
+	 * Inc a little
+	 */
+	for (i=0; i<10000; i++) {
+		switch (i & 0x03) {
+		case 0:
+			*digout = 0x02;
+			break;
+		case 1:
+			*digout = 0x03;
+			break;
+		case 2:
+			*digout = 0x01;
+			break;
+		case 3:
+			*digout = 0x00;
+			break;
+		}
+		udelay(10);
+	}
+
+	printf("Inc 0 = %ld\n", incin[0]);
+	printf("Inc 1 = %ld\n", incin[1]);
+	printf("Inc 2 = %ld\n", incin[2]);
+	printf("Inc 3 = %ld\n", incin[3]);
+
+	*(ushort *)0xf03000e0 = 0x0c80-1; /* set counter */
+	*(ushort *)0xf03000ec |= 0x0800; /* enable int */
+	irq_install_handler (30, (interrupt_handler_t *) cyclicInt, NULL);
+	printf("counter=%d\n", counter);
+
+	return 0;
+}
+U_BOOT_CMD(
+	inctest,	3,	1,	do_inctest,
+	"inctest - Test incremental encoder inputs\n",
+	NULL
+	);
+#endif
diff --git a/board/esd/ar405/ar405.h b/board/esd/ar405/ar405.h
new file mode 100755
index 0000000..5fc313a
--- /dev/null
+++ b/board/esd/ar405/ar405.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/board/esd/ar405/config.mk b/board/esd/ar405/config.mk
new file mode 100755
index 0000000..3e8baf6
--- /dev/null
+++ b/board/esd/ar405/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd AR405 boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+#TEXT_BASE = 0xFFFD0000
+TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/ar405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/ar405/fpgadata.c b/board/esd/ar405/fpgadata.c
new file mode 100755
index 0000000..5c337e0
--- /dev/null
+++ b/board/esd/ar405/fpgadata.c
@@ -0,0 +1,2750 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+ 0x70,0x70,0x63,0x5f,0x61,0x72,0x30,0x31,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+ 0x73,0x34,0x30,0x78,0x6c,0x70,0x71,0x32,0x34,0x30,0x00,0x63,0x00,0x0b,0x32,0x30,
+ 0x30,0x31,0x2f,0x30,0x32,0x2f,0x31,0x34,0x00,0x64,0x00,0x09,0x31,0x35,0x3a,0x34,
+ 0x30,0x3a,0x30,0x34,0x00,0x65,0xe2,0x01,0x00,0x00,0xab,0x8e,0xff,0x30,0xe5,0xe5,
+ 0xe8,0xe5,0x03,0xe8,0x04,0x01,0x02,0x11,0x09,0x09,0x01,0x07,0x02,0x04,0x04,0x06,
+ 0x09,0x07,0x04,0x04,0x04,0x04,0x03,0x07,0x02,0x04,0x09,0x04,0x04,0x0b,0x09,0x09,
+ 0x03,0x07,0x02,0x09,0x04,0x04,0x04,0x04,0x0e,0x04,0x04,0x09,0x03,0x07,0x02,0x04,
+ 0x03,0x03,0x03,0x07,0xe5,0x01,0x0d,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x19,0x03,0x02,0x02,0x03,0x02,0x08,0x09,0x07,0x13,0x03,0x11,0x02,0x06,0x03,0x05,
+ 0x03,0x05,0x11,0x1d,0x1f,0x13,0x10,0x01,0x01,0xe3,0x4c,0xe5,0x01,0x0a,0x04,0x01,
+ 0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x09,0x04,0x04,0x02,0x06,0x01,0xe5,0x05,
+ 0x01,0x02,0x04,0x04,0x04,0x09,0x09,0x09,0x09,0x04,0x06,0x01,0x07,0x09,0x04,0x04,
+ 0x09,0x06,0x02,0x09,0x09,0x04,0x01,0xe7,0x03,0x04,0x07,0xe6,0x08,0x09,0x09,0x0e,
+ 0x01,0xe6,0x13,0x09,0x09,0x09,0x03,0x05,0x03,0x05,0x09,0x09,0x09,0x09,0xe5,0x07,
+ 0x03,0x05,0xe5,0x07,0xe5,0x01,0x05,0x0b,0xe5,0x07,0xe5,0x07,0x09,0x03,0x05,0xe6,
+ 0xe5,0x04,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0xe6,0x04,0x03,0x05,0xe5,0xe6,0x04,
+ 0xe5,0x07,0x03,0x05,0xe5,0x07,0x0b,0x01,0x0e,0x05,0x03,0x05,0x03,0x05,0x1d,0x03,
+ 0x05,0x03,0x44,0xe5,0xe5,0x2e,0x1c,0x01,0x13,0x32,0x01,0xe3,0x4d,0xe5,0x0f,0x09,
+ 0x09,0x27,0x09,0x42,0x04,0x4a,0x44,0x01,0x01,0x01,0x12,0x09,0x09,0x01,0x06,0x01,
+ 0x12,0x09,0x0a,0x09,0x11,0x21,0x13,0x11,0x15,0x1d,0x1b,0x0c,0x0d,0x03,0x03,0x01,
+ 0x31,0x31,0x47,0x81,0xe5,0xe5,0xe5,0x77,0x3e,0xe5,0x19,0xe5,0x1b,0x3b,0xe5,0xe5,
+ 0x5a,0x3d,0x1f,0x74,0xe6,0xe5,0x28,0x5b,0x09,0xe5,0x0a,0x08,0xe5,0x08,0x1d,0x11,
+ 0xe6,0x37,0x12,0x01,0x01,0x09,0x06,0x09,0x09,0x09,0xe5,0x07,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x01,0x03,0x03,0x03,0x05,0x05,0x05,0x09,0x09,0x09,0x09,0x09,0xe5,
+ 0x07,0x09,0x09,0x09,0x05,0x03,0x09,0x09,0x09,0x10,0xe5,0x0f,0x09,0x09,0x04,0x04,
+ 0x09,0x09,0x05,0x03,0x05,0x03,0x01,0x07,0x09,0x09,0x09,0x09,0x07,0x01,0x07,0xe5,
+ 0x01,0x07,0x01,0x06,0x02,0x09,0x05,0x03,0x06,0x02,0x09,0x05,0x01,0x01,0x01,0x07,
+ 0x05,0x03,0x09,0x09,0x09,0x04,0x04,0x0e,0x01,0xe5,0x02,0x09,0xe5,0x07,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,0x01,
+ 0x01,0x03,0xe5,0x01,0x05,0xe5,0x07,0xe5,0xe5,0x05,0x09,0x09,0x01,0x02,0x06,0x04,
+ 0x04,0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,0xe5,0x07,0x09,0xe5,0x02,0x04,0xe5,
+ 0x01,0x05,0x09,0x09,0xe5,0x07,0xe5,0x04,0x0b,0x01,0x10,0x09,0x09,0x09,0x09,0x05,
+ 0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x02,0x06,0x02,0x06,0xe6,0x01,0x06,0x02,
+ 0x06,0x02,0x09,0x09,0x03,0x02,0x02,0x09,0x06,0x02,0x09,0x09,0x06,0x02,0x06,0x02,
+ 0x09,0x09,0x0d,0x02,0xe5,0x02,0x01,0xe5,0x05,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x03,0x03,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x02,0x04,0xe5,0x03,0x03,0x05,0x03,0x0b,0x04,0xe5,0x02,0x06,0x02,0x09,0xe5,
+ 0x07,0xe5,0x01,0x05,0x05,0x03,0xe5,0x03,0x03,0x05,0x03,0xe5,0x07,0xe5,0x07,0x09,
+ 0x09,0xe5,0x07,0xe5,0x07,0x02,0x03,0xe5,0xe6,0x08,0x05,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x01,0xe5,0x05,0x06,0x09,0x07,0xe6,0x08,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,0x0a,0x09,0x08,0x01,0x03,0x06,0x08,0x09,
+ 0x09,0x0a,0x08,0x0a,0x07,0xe5,0x08,0x0a,0x09,0x08,0x09,0x11,0xe5,0xe5,0x01,0x0a,
+ 0x02,0x04,0x01,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x01,0x04,0x02,0x03,0x02,0x02,
+ 0x06,0x02,0x05,0xe5,0x01,0x05,0xe5,0x01,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,
+ 0x08,0x02,0x05,0xe5,0x01,0x06,0x02,0x05,0xe5,0x01,0x04,0x01,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x01,0x04,0x02,0x06,0x02,0x06,0x02,0x05,0xe5,0x01,0x06,0x02,0x06,
+ 0x02,0x08,0x04,0xe5,0xe6,0x02,0x11,0x04,0xe6,0x24,0x09,0xe5,0x2f,0x06,0xe5,0xe5,
+ 0x05,0x0e,0x06,0xe5,0x10,0x17,0x09,0x06,0x02,0x45,0x03,0x02,0xe5,0x15,0x0f,0x13,
+ 0x27,0x1e,0x05,0x02,0x01,0x01,0x05,0x08,0x3c,0x06,0x01,0x45,0x04,0xe8,0x11,0x01,
+ 0xe5,0x07,0x15,0x13,0x23,0x22,0xe5,0x04,0x01,0x06,0x2e,0x13,0x1d,0x2d,0xe5,0xe6,
+ 0x18,0x02,0x0c,0x17,0x09,0x31,0x0d,0xe5,0x0c,0x31,0xe7,0x58,0x04,0xe5,0xe6,0x0f,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x01,0x02,0xe5,0x02,0x09,0x09,0x05,0x03,0x05,0x03,
+ 0xe5,0x07,0x09,0x0b,0x09,0x09,0x09,0x01,0x03,0x03,0x07,0x01,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x0f,0xe6,0x13,0x1d,0x03,0x01,0x1a,0x13,0xe5,0xe5,0x0f,0x01,
+ 0xe5,0x07,0xe5,0x05,0x01,0xe5,0x06,0xe6,0xe5,0x05,0x02,0x06,0x01,0xe5,0x09,0x12,
+ 0x09,0x10,0x0a,0x01,0x08,0xe5,0x0f,0x01,0xe5,0x17,0xe5,0xe5,0x50,0x01,0x07,0x09,
+ 0x01,0x14,0x05,0x01,0x08,0x0a,0x0a,0x02,0x09,0x0d,0x0b,0x14,0x4e,0xe5,0x01,0x3c,
+ 0x0b,0x12,0x34,0x0b,0x06,0x01,0x0e,0x18,0x04,0x04,0x04,0x0f,0x27,0x19,0x02,0xe5,
+ 0x05,0x67,0x09,0x3d,0x33,0x07,0x1d,0x17,0x05,0xe5,0xe6,0x05,0x15,0x5b,0x35,0x81,
+ 0xe6,0x34,0x01,0x07,0x1d,0xe6,0x06,0x01,0x0b,0x05,0x01,0x0b,0x0b,0x2d,0x01,0x07,
+ 0x0b,0x05,0x03,0x11,0xe6,0x1a,0x01,0x03,0x17,0xe5,0x1a,0x1c,0x09,0x24,0x01,0x11,
+ 0x01,0x0e,0x07,0x15,0x1b,0x09,0x03,0x21,0x1c,0x01,0x18,0x01,0x01,0x35,0x20,0x01,
+ 0x04,0x01,0x13,0x0d,0x0b,0x12,0x10,0x02,0x0a,0x03,0x11,0x01,0x09,0x02,0x03,0x07,
+ 0x06,0x2a,0x0c,0x02,0x1a,0x0a,0x08,0x13,0x09,0x10,0xe5,0xe5,0x0b,0x03,0xe5,0x0e,
+ 0x07,0x1e,0x03,0x01,0x12,0x0f,0x02,0x01,0x02,0x17,0x02,0x01,0x02,0x11,0x0d,0x13,
+ 0xe5,0x01,0x27,0xe5,0x33,0x07,0x0d,0x3b,0x02,0x0b,0x09,0x0e,0x03,0x1c,0x35,0x01,
+ 0xe6,0x64,0x09,0x2a,0x03,0x06,0x01,0x03,0x07,0x02,0x2b,0x05,0x20,0xe6,0x24,0xe5,
+ 0xe5,0x06,0x43,0x0e,0x37,0x01,0x28,0x23,0x27,0x0c,0x15,0xe5,0xe6,0x68,0x0c,0x03,
+ 0x02,0x13,0x05,0x02,0x14,0x01,0x0b,0x03,0x07,0x08,0x06,0x16,0x06,0x36,0xe5,0xe6,
+ 0x60,0x07,0x13,0x02,0x10,0x0d,0x11,0x02,0x20,0x10,0x01,0x0c,0x01,0x02,0x34,0xe7,
+ 0x09,0x06,0x58,0x10,0x01,0x11,0x01,0x1f,0x04,0x08,0x17,0x18,0x04,0x2c,0x0b,0x03,
+ 0xe6,0x6e,0x37,0x0f,0x02,0x03,0xe5,0xe5,0x04,0xe5,0x06,0x01,0xe5,0x03,0xe5,0xe6,
+ 0x05,0x08,0xe6,0x03,0x05,0xe5,0x07,0xe5,0x05,0x1e,0xe7,0xe6,0x01,0x01,0x6c,0x13,
+ 0xe5,0x21,0xe5,0x0d,0x04,0x04,0x04,0x01,0x01,0x07,0xe5,0xe5,0x04,0xe5,0x0f,0x05,
+ 0xe6,0x03,0xe5,0x06,0xe5,0x21,0x01,0x06,0x04,0x6c,0x10,0xe5,0x16,0x06,0x01,0xe5,
+ 0xe5,0x0b,0x04,0x06,0xe5,0x10,0xe5,0x05,0xe5,0x07,0x0c,0xe5,0x18,0x1b,0x05,0x01,
+ 0xe5,0x01,0x57,0x16,0x10,0x13,0xe5,0x04,0x07,0x01,0x04,0xe5,0xe5,0x08,0x06,0x12,
+ 0xe5,0x1c,0x38,0x03,0xe5,0xe5,0x5a,0x27,0x03,0x22,0x06,0xe5,0x04,0xe5,0x06,0x01,
+ 0x0e,0x07,0x02,0x02,0x05,0x0c,0x01,0x01,0x02,0xe5,0x01,0x05,0x09,0x1f,0xe5,0xe6,
+ 0x01,0x5e,0x13,0x0f,0x03,0x04,0x10,0x01,0x02,0x04,0x08,0x02,0x01,0xe6,0x02,0x05,
+ 0x03,0x0f,0x02,0x02,0x02,0x14,0x01,0x02,0x01,0x01,0x2c,0x02,0x01,0x01,0xe5,0x5b,
+ 0x01,0x2d,0x0d,0x09,0x01,0x03,0xe5,0x03,0x04,0x01,0xe5,0x05,0x01,0x11,0x02,0x0e,
+ 0x0b,0x01,0x02,0x0b,0x09,0xe5,0xe5,0xe5,0x19,0xe5,0x02,0x5d,0x01,0x3a,0x02,0x07,
+ 0x01,0x01,0xe5,0xe5,0x01,0x02,0x06,0x17,0xe8,0xe5,0x01,0x0a,0xe5,0x0d,0x0e,0x09,
+ 0x1f,0xe5,0xe6,0x6c,0xe5,0x25,0x12,0x04,0x04,0x02,0x09,0x10,0x09,0x09,0x1d,0x09,
+ 0x21,0xe8,0x63,0x09,0x09,0x09,0x09,0x0b,0x0f,0xe5,0x0d,0x07,0xe6,0x06,0x05,0xe5,
+ 0x0b,0xe5,0x03,0xe5,0x15,0x05,0xe5,0x07,0xe5,0x1f,0x02,0xe6,0x0d,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x03,0x02,0x02,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x02,0x02,0x06,0x01,0x02,0x02,0x06,0xe5,0x04,0x02,0xe5,0x07,0x06,0x02,0x02,
+ 0xe5,0x04,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x07,0x09,0x03,0x05,0xe6,0x06,0xe6,0x06,
+ 0x09,0x06,0x06,0x02,0x01,0x02,0x59,0x08,0x0a,0x09,0x10,0x02,0x06,0x17,0x13,0x11,
+ 0x02,0x1d,0x30,0xe5,0x03,0x05,0xe5,0x58,0x13,0x0a,0x13,0x0d,0x0e,0x27,0x03,0x0f,
+ 0x0d,0x2f,0x0a,0x01,0x01,0x5f,0x07,0x01,0x04,0x02,0x1c,0x0c,0x0c,0xe6,0x06,0x06,
+ 0x01,0x09,0x0a,0xe6,0x06,0x09,0xe6,0x0a,0x04,0x0a,0xe6,0x06,0xe6,0x1e,0xe8,0x5b,
+ 0xe5,0x01,0x06,0x01,0xe5,0x07,0xe5,0x08,0x09,0x09,0x03,0x06,0xe5,0x09,0x0f,0x01,
+ 0xe5,0x02,0x02,0x02,0x0a,0x13,0x0f,0x01,0x01,0x09,0x09,0x19,0xe5,0x02,0x01,0xe8,
+ 0x66,0x12,0x1f,0xe5,0x0c,0x01,0x05,0x06,0x2b,0x03,0x0e,0x03,0x09,0x07,0x16,0x0a,
+ 0xe5,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,
+ 0x05,0xe5,0x05,0xe7,0x01,0x04,0xe6,0x07,0xe5,0x07,0xe5,0x02,0x02,0xe7,0x07,0xe5,
+ 0x05,0xe7,0x07,0xe5,0x01,0x05,0xe5,0x02,0x02,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe6,
+ 0x03,0x01,0xe8,0x5e,0x07,0x01,0x07,0x02,0x10,0x01,0x16,0x09,0x09,0xe5,0x04,0x01,
+ 0xe5,0x07,0x0a,0x08,0x0a,0x09,0xe5,0x06,0x0a,0x09,0x1b,0x08,0xe5,0x5c,0x09,0x01,
+ 0x09,0x11,0x01,0x1c,0x03,0x01,0xe5,0x01,0x07,0x01,0xe5,0xe5,0x06,0x0e,0xe5,0x01,
+ 0xe5,0xe5,0x0b,0xe5,0x01,0x0a,0x01,0x02,0x09,0xe5,0x01,0x03,0x01,0xe5,0x01,0x1c,
+ 0xe7,0x0b,0x5a,0x01,0x0a,0x06,0x13,0x0a,0x03,0x0d,0xe5,0x02,0x0a,0x13,0x03,0xe5,
+ 0x0d,0x03,0xe5,0x0c,0x0a,0x03,0xe5,0x07,0xe5,0x1b,0xe6,0xe5,0x66,0x01,0x0a,0x29,
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+ 0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x08,
+ 0x06,0xe7,0x03,0x01,0xe5,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x08,0x08,0xe5,0x07,0xe5,
+ 0x0b,0x03,0xe5,0x01,0x0b,0x01,0x05,0x01,0x01,0x02,0x05,0xe5,0x08,0x08,0xe5,0x08,
+ 0x09,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x01,0x02,0x02,0xe5,
+ 0x04,0x02,0xe5,0x04,0x01,0x03,0x08,0xe6,0x06,0xe5,0x04,0x03,0x07,0xe6,0x01,0x06,
+ 0x08,0x08,0xe6,0x06,0xe5,0x05,0x02,0xe5,0x03,0x04,0x09,0x09,0x09,0x0f,0x01,0x02,
+ 0xe5,0x03,0x06,0xe5,0x03,0x03,0xe5,0xe5,0xe5,0xe5,0x01,0xe5,0x07,0x06,0x02,0xe6,
+ 0x06,0xe5,0x02,0x04,0xe6,0xe5,0x01,0x02,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x07,0x02,
+ 0x01,0x04,0xe6,0x06,0x09,0x01,0x09,0x01,0xe5,0x05,0x02,0x04,0xe6,0x08,0x02,0x03,
+ 0x02,0x07,0x01,0x01,0x04,0x02,0x06,0xe5,0xe6,0x07,0x09,0xe5,0x06,0xe5,0x06,0x01,
+ 0x09,0x09,0x10,0xe6,0x23,0x0b,0x25,0x09,0x09,0x16,0x05,0x02,0xe5,0x07,0x0c,0x05,
+ 0x03,0x06,0x13,0x12,0x07,0x02,0x08,0x02,0x03,0x02,0x0d,0x2b,0xe5,0x0e,0x05,0x03,
+ 0x09,0x09,0x09,0xe5,0x02,0x04,0x09,0x09,0x04,0x04,0x09,0x04,0x04,0xe5,0x07,0xe5,
+ 0x07,0x01,0x01,0x05,0xe5,0x09,0x09,0x08,0xe5,0x08,0x09,0x02,0x04,0x01,0x09,0x10,
+ 0x02,0x13,0x08,0xe5,0x08,0x09,0x0e,0x01,0x01,0x0d,0xe5,0x01,0x03,0x01,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x02,
+ 0x03,0xe6,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x02,0x05,
+ 0x03,0x04,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x10,0xe6,0x0c,0x02,0x04,0x01,
+ 0x02,0x06,0x02,0x06,0x09,0x02,0x05,0xe5,0x01,0x05,0xe5,0x01,0x06,0x02,0x02,0x03,
+ 0x02,0x02,0x03,0x02,0x01,0xe5,0x02,0x09,0x02,0x06,0x06,0x02,0x08,0x01,0xe5,0x06,
+ 0x01,0x09,0x05,0x03,0x09,0x0a,0x02,0x05,0x02,0x01,0xe5,0x03,0x04,0x03,0x02,0x06,
+ 0x05,0x04,0x09,0x08,0x09,0x11,0x01,0xe5,0x0d,0xe5,0x07,0x09,0x09,0xe5,0xe5,0x05,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0xe5,0xe5,0x05,0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x07,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0x09,0x09,0x09,0xe5,0x07,0xe5,0xe5,0x05,0x02,0x06,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x0b,0xe5,0xe6,0x09,0x03,0x02,0x06,0x01,0x07,0x01,0x07,0x09,0x01,0x03,0x03,
+ 0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x04,0x04,0x01,0x07,0x04,
+ 0x04,0x04,0x06,0x05,0x03,0x05,0x03,0x09,0x09,0x13,0x13,0x04,0x04,0x03,0x11,0x07,
+ 0x03,0x05,0x0f,0x02,0xe5,0x18,0x09,0x04,0x0e,0x09,0x01,0x02,0x04,0x01,0x07,0x09,
+ 0x06,0x02,0x01,0x11,0x01,0xe5,0xe5,0x1f,0x06,0x17,0x05,0x01,0x02,0x03,0x08,0x06,
+ 0x02,0x09,0x10,0x04,0x04,0x24,0xe6,0xe5,0x0d,0x05,0x03,0x03,0x05,0x02,0x02,0x06,
+ 0x06,0x09,0x09,0x03,0x05,0x02,0x06,0x02,0x02,0xe5,0x01,0x09,0x09,0x09,0x05,0xe5,
+ 0x01,0x08,0x02,0x09,0x02,0x06,0x0d,0x05,0x0d,0x05,0x02,0x04,0x04,0xe5,0x04,0x09,
+ 0x02,0x1a,0x09,0x0f,0xe8,0x2b,0x11,0x1d,0x1d,0x18,0x04,0xe5,0x09,0x13,0x01,0x1a,
+ 0xe5,0x09,0xe5,0xe5,0x04,0x1f,0x25,0xe6,0x0f,0x03,0x05,0x09,0x09,0x09,0x09,0x01,
+ 0x07,0x09,0x09,0x09,0xe5,0x07,0x05,0x03,0x09,0x01,0x07,0x06,0xe5,0x02,0x09,0x09,
+ 0x01,0x03,0x03,0x05,0x03,0x09,0xe5,0x07,0x09,0x09,0x01,0x07,0x09,0x07,0x01,0x09,
+ 0x09,0x0d,0x01,0x01,0x04,0x27,0x39,0x25,0x09,0x0b,0x09,0x09,0x02,0xe5,0x0e,0x02,
+ 0x07,0x0b,0x1d,0x2e,0xe5,0xe6,0x50,0xe5,0x1b,0x13,0x04,0x04,0x04,0x06,0x04,0x09,
+ 0x04,0x04,0x13,0x0e,0x13,0x1d,0x27,0xe7,0x21,0xc6,0x40,0x03,0x03,0x07,0xe3,0x09,
+ 0x3a,0x03,0x07,0x29,0x1f,0x25,0x0b,0x3b,0x15,0xe5,0x2d,0x01,0x27,0xe7,0x6e,0x16,
+ 0x05,0xe5,0x01,0x05,0x02,0x02,0x05,0x03,0x05,0xe5,0x01,0x05,0x0d,0x05,0x5c,0x06,
+ 0x01,0x01,0x05,0x93,0x59,0x34,0x05,0xe5,0x01,0x04,0xe5,0xe3,0x34,0x10,0x02,0xe5,
+ 0x13,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x09,0x09,0x09,0x03,0x05,0x0a,0xe5,
+ 0xe5,0x04,0x09,0x08,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x08,0x09,0x07,0x03,0x09,0x09,0x09,0x09,0x09,
+ 0x04,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x08,0x08,0xe5,0x08,0x07,0xe6,
+ 0x11,0x16,0x09,0x09,0x0f,0x03,0x09,0x09,0x05,0x03,0x09,0x05,0x03,0x13,0x04,0x09,
+ 0x05,0x05,0x09,0x09,0x13,0x14,0x03,0x09,0x09,0x05,0x03,0x2f,0xe5,0x01,0x0d,0x03,
+ 0x03,0x05,0x03,0x05,0x03,0x01,0x0d,0x03,0x05,0x03,0x09,0x05,0x03,0x09,0x09,0x01,
+ 0x11,0x01,0x04,0x04,0x04,0x06,0x04,0x04,0x04,0x04,0x04,0x04,0x09,0x04,0x06,0x0b,
+ 0x03,0x05,0x03,0x09,0x09,0x01,0x0d,0x03,0x03,0x05,0x03,0x0e,0xe8,0x0a,0x06,0x01,
+ 0x02,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,0xe5,0x02,0x07,0xe5,0xe5,0x03,0x02,0x01,
+ 0x01,0xe5,0xe5,0x01,0x01,0x01,0xe5,0xe5,0x01,0x01,0x04,0x02,0x01,0x01,0xe5,0xe5,
+ 0x01,0x01,0x01,0x02,0x03,0x07,0xe5,0xe5,0xe6,0xe5,0x04,0x02,0x02,0x03,0x02,0x02,
+ 0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x01,0x07,0x03,0x02,0x02,0x02,0x04,
+ 0x02,0x01,0x04,0x02,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,0x05,0x04,0x03,0x07,0xe5,
+ 0xe5,0x03,0x04,0x04,0x0b,0x02,0xe5,0x01,0xe5,0x01,0xe5,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
diff --git a/board/esd/ar405/fpgadata_xl30.c b/board/esd/ar405/fpgadata_xl30.c
new file mode 100755
index 0000000..57d327a
--- /dev/null
+++ b/board/esd/ar405/fpgadata_xl30.c
@@ -0,0 +1,2436 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+ 0x70,0x70,0x63,0x5f,0x61,0x72,0x30,0x31,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+ 0x73,0x33,0x30,0x78,0x6c,0x70,0x71,0x32,0x34,0x30,0x00,0x63,0x00,0x0b,0x32,0x30,
+ 0x30,0x34,0x2f,0x31,0x32,0x2f,0x31,0x34,0x00,0x64,0x00,0x09,0x31,0x37,0x3a,0x30,
+ 0x33,0x3a,0x32,0x33,0x00,0x65,0xe2,0x01,0x00,0x00,0x97,0xf2,0xff,0x30,0xe6,0x03,
+ 0xe5,0x01,0x01,0x01,0xe5,0xe6,0x04,0x01,0x02,0x11,0x09,0x09,0x02,0x04,0x04,0x06,
+ 0x09,0x07,0x09,0x04,0x04,0x04,0x04,0x09,0x09,0x0b,0x09,0x09,0x04,0x04,0x04,0x04,
+ 0x04,0x09,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x03,0x07,0x08,0x01,0xe5,
+ 0x0c,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x13,0x03,0x02,0x02,0x03,0x02,0x08,
+ 0x09,0x11,0x03,0x11,0x02,0x06,0x03,0x05,0x03,0x21,0x33,0x11,0xe5,0xe5,0xe3,0x17,
+ 0x0b,0xe5,0x01,0x0f,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x04,0x04,0x02,
+ 0x06,0x01,0xe5,0x05,0x01,0x02,0x02,0xe6,0x03,0x04,0x09,0x09,0x07,0xe6,0x03,0x06,
+ 0x01,0x07,0x09,0x04,0x04,0x09,0x09,0x06,0x02,0x04,0x04,0x04,0x04,0x09,0x09,0x09,
+ 0x12,0x14,0x09,0x09,0x03,0x05,0x03,0x05,0x09,0x09,0x03,0x05,0x09,0xe5,0x01,0x05,
+ 0xe5,0x07,0xe5,0xe6,0x04,0x0b,0xe5,0x07,0xe5,0x07,0x03,0x05,0xe5,0x01,0x05,0xe5,
+ 0x01,0x05,0xe6,0xe5,0x04,0x03,0x05,0x03,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,
+ 0x07,0x09,0x03,0x0e,0x05,0x03,0x05,0x03,0x05,0x13,0x03,0x05,0x03,0x08,0x31,0xe5,
+ 0xe5,0x37,0x44,0x01,0x01,0x01,0x79,0x8a,0xe5,0x01,0x10,0x09,0x09,0x1d,0x09,0x38,
+ 0x04,0x36,0x45,0xe7,0xe5,0x11,0x09,0x09,0x13,0x09,0x3e,0x09,0x3b,0x1d,0x18,0x05,
+ 0x01,0x01,0x06,0x73,0x12,0x77,0xe5,0xe5,0xe5,0xa2,0xe5,0x41,0x1c,0xe8,0x84,0x1f,
+ 0x25,0x3a,0xe5,0xe6,0x3c,0x70,0x4e,0x0c,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x03,0x07,0x01,0x07,0x09,0x09,0x09,0x09,0x09,0xe5,0x07,0x09,
+ 0x09,0x09,0x01,0x07,0x0d,0xe5,0x01,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x05,0x03,0x05,0x03,0x05,0x03,0x07,0x03,0x09,0x05,0x03,0x05,0x03,0x09,0x09,0x09,
+ 0x05,0x03,0x09,0x01,0x07,0x09,0x09,0x08,0x06,0x01,0x0d,0xe5,0x05,0x01,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x04,0x01,0xe6,0x07,0xe5,0x03,0x02,0xe6,0x07,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x01,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x01,0x05,
+ 0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,
+ 0xe5,0x07,0xe5,0x01,0x0c,0xe8,0x0f,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,
+ 0x01,0x07,0x09,0xe5,0x07,0xe5,0x01,0x02,0xe5,0x02,0x09,0x09,0x09,0x09,0x01,0x01,
+ 0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x06,0x0a,0x05,0xe5,0x05,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x02,0x06,0xe5,0x03,0x03,0xe5,0x03,0x03,0xe5,0x04,0x02,
+ 0xe5,0x02,0x01,0x02,0xe5,0x01,0x05,0xe5,0x04,0x02,0xe5,0x07,0xe5,0x07,0xe5,0x03,
+ 0x03,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x07,0x02,0x03,0x03,0x0f,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x08,0x07,0x01,0x0d,0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x09,0x09,
+ 0x09,0x09,0x09,0x05,0x03,0x09,0x01,0x03,0x05,0x09,0x09,0x08,0xe5,0x06,0x01,0x09,
+ 0x08,0xe5,0x08,0x09,0x09,0x09,0x0a,0x07,0xe6,0x01,0x03,0x06,0x02,0xe5,0x04,0x02,
+ 0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,
+ 0x04,0x01,0x02,0x05,0xe5,0x01,0x08,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x04,0x01,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x06,0x02,0xe5,0x02,0x37,0xe5,0x04,0x09,0x31,0x05,0x05,0x13,0x09,0x04,0x24,0x07,
+ 0x09,0x17,0x02,0x02,0x01,0x01,0x03,0x42,0x01,0x13,0x13,0x10,0x0c,0x01,0x09,0x07,
+ 0x01,0x06,0x05,0x24,0x06,0x0a,0x0f,0x0f,0x01,0xe6,0xe5,0x1d,0x1b,0x21,0x09,0x09,
+ 0x13,0x01,0x13,0x1d,0x05,0x17,0x2b,0x05,0xe6,0x33,0x04,0x05,0xe5,0x05,0x03,0x06,
+ 0x2c,0x0b,0x04,0x1d,0x59,0xe6,0x0f,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x01,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x0d,0xe5,0x01,0x2b,0x02,0x1a,0x13,0x02,0x09,0x06,0x0c,0x08,0xe5,0xe5,0x05,
+ 0x02,0xe5,0x07,0x06,0x01,0xe5,0x09,0x0f,0x01,0xe5,0x0f,0x09,0x03,0x03,0x01,0x1b,
+ 0xe5,0xe5,0x2a,0x12,0x2f,0xe5,0x08,0x09,0x0b,0x16,0x06,0x16,0x12,0x06,0x03,0x08,
+ 0x1c,0x01,0x2b,0x1e,0x03,0x0e,0xe5,0x07,0x0a,0x03,0x04,0x0c,0x04,0x03,0xe5,0x07,
+ 0x6a,0xe5,0x01,0x59,0x06,0x03,0x1c,0x0b,0x0b,0x18,0x0d,0x13,0x2b,0x06,0xe7,0x14,
+ 0x0a,0x09,0x2c,0x15,0x64,0x34,0x01,0xe5,0x13,0x16,0x09,0x01,0x17,0x0b,0x01,0x09,
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+ 0x02,0x01,0x02,0x01,0x02,0x01,0x04,0x09,0x09,0x09,0x01,0xe5,0x05,0x05,0x03,0x02,
+ 0x05,0x02,0x09,0x02,0xe5,0x04,0x04,0x03,0xe5,0x07,0x03,0x05,0xe5,0x08,0x05,0x02,
+ 0xe5,0x02,0x03,0x01,0x04,0x04,0x09,0x09,0x09,0x06,0xe5,0xe5,0x06,0x18,0x09,0x09,
+ 0x1d,0x0f,0x13,0x03,0x0a,0x0a,0x04,0x10,0x09,0x06,0xe5,0xe5,0x4a,0xe5,0x01,0x07,
+ 0x08,0xe5,0x07,0x09,0x09,0x03,0x05,0x09,0x09,0xe5,0x07,0x09,0x09,0x09,0x05,0x03,
+ 0x06,0xe5,0x02,0x09,0x09,0x09,0xe5,0x07,0x07,0x01,0x01,0x07,0x01,0x07,0x05,0x03,
+ 0x01,0x07,0x09,0x09,0x0e,0x01,0xe5,0x03,0x61,0x11,0x01,0x07,0x0b,0x09,0x09,0x03,
+ 0x05,0x02,0xe5,0x05,0x15,0x3b,0xe5,0x14,0x13,0x13,0x09,0x14,0x09,0x0d,0x09,0x06,
+ 0x04,0x09,0x04,0xe5,0x02,0x04,0x04,0x18,0x13,0x09,0x27,0xe5,0xe5,0x09,0x17,0x06,
+ 0x02,0x4f,0x4f,0x09,0x2b,0x05,0xe6,0x0a,0x3b,0x27,0x5b,0x3c,0xe6,0x3c,0x5b,0x1e,
+ 0x26,0x27,0xe5,0xe5,0x03,0x10,0x31,0x2a,0x05,0x03,0x05,0x02,0x02,0x05,0x03,0x05,
+ 0x03,0x05,0xe5,0x01,0x05,0x14,0x13,0x29,0x06,0xe5,0xe6,0x46,0x27,0x15,0x46,0x33,
+ 0x05,0xe5,0x01,0x04,0x57,0xa9,0x03,0x14,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x09,
+ 0xe6,0x06,0x09,0xe6,0x06,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0xe6,0x06,0x09,
+ 0x09,0x09,0x09,0x0a,0x02,0x05,0x09,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x05,0x01,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x05,0x02,0x09,0x07,0x03,
+ 0x09,0x09,0x09,0x09,0x04,0x03,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x08,0x09,0x10,0xe6,0x15,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x05,0x03,0x09,0x05,0x03,0x04,0x09,0x05,0x05,0x09,0x09,0x09,0x14,0x03,0x09,
+ 0x05,0x03,0x09,0x27,0x01,0x0d,0x03,0x03,0x05,0x03,0x05,0x03,0x05,0x03,0x05,0x03,
+ 0x09,0x05,0x03,0x09,0x05,0x03,0x09,0x01,0x04,0x04,0x04,0x06,0x04,0x04,0x04,0x04,
+ 0x04,0x04,0x04,0x06,0x0b,0x03,0x09,0x09,0x09,0x09,0x03,0x05,0x03,0x0d,0x02,0x01,
+ 0x0b,0x06,0x01,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x04,0x02,
+ 0x01,0x01,0x05,0x01,0x04,0x02,0x01,0x01,0x05,0x01,0x02,0x01,0x02,0x01,0x01,0xe5,
+ 0x06,0x02,0x02,0x03,0x02,0x02,0x05,0x02,0x02,0x03,0x02,0x02,0x03,0x02,0x02,0x03,
+ 0x02,0x02,0x02,0x04,0x02,0x01,0x04,0x02,0x01,0x01,0xe5,0x03,0x01,0x01,0x02,0x04,
+ 0x02,0x01,0x02,0x01,0x01,0x02,0x04,0x04,0x04,0x06,0x02,0x02,0xe6,0xe5,0xe5,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
diff --git a/board/esd/ar405/u-boot.lds b/board/esd/ar405/u-boot.lds
new file mode 100755
index 0000000..3b9aa7c
--- /dev/null
+++ b/board/esd/ar405/u-boot.lds
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o		(.text)
+    cpu/ppc4xx/traps.o		(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o		(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o		(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    common/cmd_boot.o		(.text)
+    common/cmd_bootm.o		(.text)
+    common/cmd_flash.o		(.text)
+    common/cmd_mem.o		(.text)
+    common/cmd_nvedit.o		(.text)
+    common/console.o		(.text)
+    common/lists.o		(.text)
+    common/main.o		(.text)
+
+/*
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.ppcenv)
+*/
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile
new file mode 100755
index 0000000..a60495a
--- /dev/null
+++ b/board/esd/ash405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
new file mode 100755
index 0000000..03ae7fd
--- /dev/null
+++ b/board/esd/ash405/ash405.c
@@ -0,0 +1,252 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
+	volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+	*duart2_mcr = 0x08;
+	*duart3_mcr = 0x08;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming ASH405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif
diff --git a/board/esd/ash405/config.mk b/board/esd/ash405/config.mk
new file mode 100755
index 0000000..1d743a9
--- /dev/null
+++ b/board/esd/ash405/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ASH405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/ash405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/ash405/fpgadata.c b/board/esd/ash405/fpgadata.c
new file mode 100755
index 0000000..94e8db8
--- /dev/null
+++ b/board/esd/ash405/fpgadata.c
@@ -0,0 +1,2492 @@
+  0x1f,0x8b,0x08,0x08,0x5c,0xa1,0x5d,0x3f,0x00,0x03,0x61,0x73,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x32,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x0f,0x78,0x1c,0xe5,
+  0x91,0x2f,0x0a,0x57,0xbf,0xdd,0x92,0x5f,0x4d,0x8f,0x34,0xad,0x91,0x4c,0x14,0x30,
+  0xa6,0x35,0x92,0xcd,0x58,0x19,0xc9,0xe3,0x91,0x90,0x85,0x10,0xa3,0xb6,0x24,0x58,
+  0x45,0x36,0x58,0x71,0xd8,0x2c,0x67,0x97,0x93,0x1d,0x88,0x93,0xe3,0xdd,0x75,0x72,
+  0x1c,0x36,0x37,0xc7,0x21,0x6c,0xf2,0x6a,0x24,0xe3,0xb1,0x65,0xe3,0xc1,0x38,0xc1,
+  0x04,0x92,0x3b,0xfe,0x43,0x10,0xe0,0x24,0x63,0xd9,0x60,0x19,0x1b,0x68,0x09,0x41,
+  0xc6,0xb6,0xb0,0x15,0xc7,0x9b,0x35,0xc4,0x0b,0x63,0x50,0x88,0x30,0x82,0xc8,0xe0,
+  0x24,0xb2,0x2d,0xec,0x5b,0xd5,0x23,0xcd,0xf4,0x38,0x7b,0xf6,0xec,0xde,0xf3,0xdc,
+  0xef,0xdb,0xef,0xbb,0xab,0x73,0x9e,0x67,0x2b,0xdd,0xed,0xa6,0xfb,0x9d,0xb7,0xab,
+  0x7e,0x55,0xf5,0xab,0x2a,0xc8,0x73,0x8d,0xa7,0xfe,0x1f,0x80,0x74,0x37,0x68,0x77,
+  0xff,0xfd,0x8a,0x1a,0xff,0x0d,0x7f,0xbd,0xe0,0xaf,0xfd,0x81,0xaa,0xaf,0x7d,0x69,
+  0x39,0xdc,0x03,0x6a,0xe0,0xef,0x6f,0xf0,0x7f,0xf9,0x1b,0x5f,0x5f,0x50,0x53,0x03,
+  0x5f,0xc2,0xff,0xe5,0xf7,0x57,0xcf,0xf7,0xdf,0x88,0xff,0x1f,0x96,0x43,0xde,0x82,
+  0x05,0xf5,0x35,0xb5,0xf5,0xfe,0x1a,0xf8,0x32,0x48,0xd5,0x3b,0x2f,0xe3,0xdf,0xd3,
+  0x8f,0xfe,0xf9,0x57,0xfc,0x20,0x24,0x00,0x98,0xe1,0x97,0x42,0xf4,0x7f,0x55,0xbf,
+  0xa4,0x4b,0x20,0x1a,0x2b,0xfd,0x60,0xd2,0xff,0x86,0xa9,0xf3,0x79,0x7e,0xd0,0xed,
+  0xff,0x5b,0xf2,0x83,0x01,0xed,0x60,0x6c,0x00,0xb7,0x1f,0xfe,0xd7,0x7f,0x86,0x22,
+  0xa6,0xc5,0x7f,0xe7,0xf5,0x97,0x0f,0x8b,0xff,0xe9,0x55,0x99,0xbf,0xc6,0x8f,0x62,
+  0xd3,0x22,0xfb,0x37,0xdc,0x5f,0x32,0x20,0x7d,0xff,0x37,0xfe,0x4d,0xf7,0xff,0xc3,
+  0xf4,0xfd,0xff,0xbd,0xd7,0x83,0xfb,0xdf,0x70,0x39,0x80,0x92,0x7e,0x1e,0x37,0x38,
+  0x80,0x09,0x88,0x81,0xf7,0x5f,0x11,0x1a,0x07,0xa7,0xff,0x61,0x7f,0xce,0x09,0x71,
+  0x4c,0x34,0x24,0x67,0xac,0x92,0x67,0x19,0x93,0x7c,0x61,0xd2,0x15,0xed,0x3c,0x17,
+  0x3b,0x2a,0x1a,0x93,0xae,0x44,0xd9,0x4a,0x76,0xac,0xa3,0x5a,0x5f,0x3a,0x51,0x34,
+  0xae,0xad,0x9a,0xba,0xde,0x2c,0xf9,0x2d,0x74,0x8b,0x82,0x10,0x8f,0xb3,0xca,0x48,
+  0x1f,0x38,0x92,0x05,0x1b,0xd8,0x6f,0xf4,0xf5,0xa2,0x2a,0xa9,0xf6,0xc1,0x8b,0x7c,
+  0x9d,0xa8,0x30,0xd4,0x3e,0x96,0x54,0xf4,0xa9,0xeb,0x13,0xd0,0x65,0x74,0x82,0xcf,
+  0x7c,0xcc,0x9f,0x9b,0xaf,0x3c,0x9f,0x17,0x33,0x55,0x0d,0x06,0x79,0x58,0xf2,0xa1,
+  0x90,0xeb,0x84,0x67,0x84,0x6e,0xa8,0xfe,0xa6,0xc3,0xd2,0xf4,0xf5,0x66,0xce,0x8f,
+  0xa1,0x1b,0xaa,0x42,0x25,0xc2,0xb1,0x12,0xfa,0xc2,0x1e,0xd3,0xb1,0x81,0x7d,0x85,
+  0x45,0xb4,0xaa,0x41,0x75,0x6b,0x93,0x0f,0x9e,0xd1,0x2b,0x5a,0xd5,0x38,0x9b,0x50,
+  0xa6,0x9f,0x67,0xd1,0xcc,0x77,0xc3,0x47,0x1e,0x08,0xbe,0xe3,0xda,0x5b,0xe6,0x83,
+  0x71,0x11,0xe8,0xbf,0xee,0x71,0xf9,0x5d,0x38,0x6c,0x04,0x93,0x2e,0xbd,0xcc,0x09,
+  0xef,0xac,0x09,0xac,0x72,0xc5,0xe5,0xe1,0x96,0xe9,0xeb,0x63,0x52,0x5c,0xb9,0xbc,
+  0xa8,0x71,0x91,0xeb,0x5b,0xf2,0x41,0xf8,0x04,0x1a,0xcd,0xa5,0xa6,0x3c,0x0e,0x97,
+  0x44,0xa3,0xe9,0x1a,0x57,0x27,0xb5,0x1f,0x2a,0x2f,0xdd,0xed,0x1a,0x6f,0x1e,0x85,
+  0xd0,0xd4,0xf5,0x27,0xb4,0x2e,0xfe,0x3e,0xd4,0x0f,0x5c,0xb7,0xfb,0xf3,0x63,0xca,
+  0xaf,0xcb,0xeb,0xcd,0x25,0x8f,0x7f,0x6a,0x44,0x9a,0x80,0xa0,0xe9,0xea,0x93,0x3f,
+  0x84,0xf3,0x22,0x60,0x6c,0x88,0xcb,0xe3,0xca,0xf4,0x7a,0x26,0x72,0x74,0xd1,0x3d,
+  0xa2,0x1b,0xfc,0x59,0xd6,0x80,0x2f,0xe2,0x49,0xb4,0x46,0xd9,0xbb,0x30,0x21,0xaa,
+  0xde,0x56,0x9f,0x65,0x93,0xb0,0xbf,0xab,0xd6,0xcc,0x8f,0xb3,0x8f,0x70,0xf7,0x4f,
+  0xbd,0xaf,0xb2,0x44,0xd9,0x91,0xe0,0xe3,0x8e,0x9a,0xdc,0x8d,0x7a,0x54,0xd2,0x4f,
+  0x73,0xb7,0x7b,0x44,0xe9,0x15,0xbe,0xa4,0xaa,0xb0,0x21,0xa8,0x86,0x98,0xc1,0xfd,
+  0x6c,0x02,0xbf,0x95,0xd4,0xdf,0xb8,0xf6,0x5d,0xf8,0x94,0x28,0xfb,0x69,0xeb,0x6a,
+  0xcf,0x6c,0xe8,0xea,0xbb,0x3b,0xe9,0xbd,0x93,0xfd,0x2a,0x54,0x1e,0xa9,0x4c,0xaa,
+  0x2b,0xd8,0x9b,0xc6,0xbe,0xe1,0x39,0xa1,0xbc,0xd5,0xec,0x64,0xfa,0xfe,0xad,0x7c,
+  0x89,0xf1,0x0e,0xd4,0x8d,0x3a,0x6a,0x9b,0x37,0xc0,0x2f,0xcd,0x78,0xff,0x92,0x9b,
+  0x9a,0x86,0x8c,0x5e,0xad,0x21,0xe9,0xaa,0x29,0x3b,0x2a,0x3e,0x86,0x40,0xbb,0xd3,
+  0x2f,0x1f,0x67,0xd3,0xcf,0x6f,0xcc,0x3c,0x08,0xbf,0x85,0xe0,0xa0,0x67,0x5c,0xde,
+  0x05,0xfb,0xe0,0x06,0x13,0x57,0x6f,0xd2,0xb8,0x5f,0xc3,0xf7,0x1d,0x97,0x27,0xe1,
+  0x8f,0x4a,0x63,0x8b,0x3a,0x2e,0x0f,0xb3,0xe9,0xf5,0xe1,0x33,0x7b,0xe0,0x22,0xf8,
+  0x4d,0x67,0xbc,0x79,0x97,0x11,0x67,0x6e,0x73,0x69,0x54,0x1a,0x81,0x93,0x10,0x4c,
+  0x3a,0xe3,0xf2,0x07,0xe6,0x00,0x04,0x42,0x28,0x0c,0x40,0x7a,0x3f,0x68,0x51,0x78,
+  0x16,0x4a,0xcd,0xfc,0x55,0x15,0xb3,0xa2,0x7b,0x51,0x58,0xdc,0xce,0x06,0xa1,0x0b,
+  0x6e,0x34,0x1d,0xab,0x9a,0x86,0xf4,0x5f,0xc1,0x53,0x06,0x5f,0x85,0xeb,0x33,0x7d,
+  0xbd,0x0e,0x8f,0xc1,0x4b,0xa2,0x2c,0xf9,0xe8,0x6a,0xc7,0x8f,0xe0,0xa5,0xf0,0x9c,
+  0x64,0xdb,0x6a,0xcf,0x9b,0xd0,0x25,0xe6,0x27,0xf3,0x56,0x2f,0x7b,0x53,0xac,0x15,
+  0xd7,0xdf,0xc3,0x57,0x33,0x33,0xbd,0xdf,0x46,0x8b,0xd7,0xc3,0x6e,0xd0,0x5f,0xcf,
+  0x0b,0x38,0x36,0xf0,0x3d,0xc9,0x72,0x53,0xad,0x61,0x1f,0xe4,0x75,0xc4,0xbc,0x21,
+  0xf5,0x06,0x5c,0xcf,0x87,0x4d,0x5f,0xc8,0xeb,0x67,0xc7,0xd3,0xd7,0x8f,0xcc,0xbc,
+  0x08,0x17,0x62,0xd5,0xd1,0xfc,0x0f,0xd5,0x1e,0xb8,0xb4,0xad,0x56,0x14,0x7c,0x59,
+  0x3e,0xcf,0x1e,0x0c,0x05,0x3b,0xf3,0x56,0x7c,0x7e,0x14,0x5e,0x8d,0x2d,0x8c,0x3b,
+  0x63,0xf2,0x84,0x32,0xfd,0xbe,0xad,0x92,0xd0,0x27,0xe0,0x45,0xcd,0xd5,0x25,0xdf,
+  0x0d,0x13,0xec,0x79,0x40,0x21,0x19,0x19,0x65,0x41,0x28,0x10,0x9d,0x49,0x3e,0x01,
+  0xf7,0x31,0x97,0x90,0x8f,0xc3,0xb4,0x16,0x71,0x6a,0x3b,0x9b,0x0e,0x41,0xaf,0xe1,
+  0x8c,0xca,0xb9,0xe1,0x43,0xa2,0xb6,0xc5,0xb5,0x55,0xfe,0x4a,0xd7,0xa1,0x45,0xc1,
+  0x90,0xeb,0x71,0xf9,0x01,0x71,0x28,0x12,0x30,0x36,0x45,0xe5,0x01,0x65,0xfa,0x7a,
+  0x01,0x5f,0x81,0x0e,0x43,0xff,0x2f,0x8e,0xab,0xcb,0x7e,0x13,0xe9,0x10,0x9e,0x90,
+  0xfa,0x28,0x2b,0x87,0xd7,0xa1,0xca,0x50,0xa3,0xee,0xb9,0xf0,0x7a,0xc8,0x83,0x02,
+  0x4b,0x82,0x36,0x75,0x7d,0x5d,0x4e,0x39,0xac,0x03,0x8f,0xd1,0xba,0x19,0x2f,0x5b,
+  0x17,0xfa,0x31,0x9e,0x0d,0xaf,0xa4,0x2f,0xa8,0x55,0xdd,0xc2,0x76,0xc2,0x3a,0xdd,
+  0xba,0xfe,0xd5,0xf4,0x7e,0xf0,0x16,0x3b,0xb7,0xad,0x13,0x1e,0xa3,0xcd,0xbd,0x7e,
+  0xb0,0xa7,0xc3,0x1b,0x32,0x54,0xf7,0x80,0xb2,0xed,0x21,0x70,0x1a,0xaa,0xc6,0x94,
+  0xd8,0xa3,0x90,0x24,0x61,0x60,0x7a,0x3b,0xc0,0xea,0xfc,0x90,0x48,0x40,0x00,0x78,
+  0x58,0xd5,0x45,0x42,0xaf,0x95,0xd4,0xb0,0x4c,0x47,0x82,0xa0,0x0a,0x39,0x86,0x42,
+  0x2f,0xe0,0xfb,0xbe,0x29,0x4d,0x3f,0xcf,0xd6,0x99,0xe7,0xe0,0xf7,0xd0,0x68,0x2c,
+  0x5d,0xf6,0xf2,0xce,0xd8,0x27,0xde,0xa0,0xe1,0x1a,0x96,0xce,0x6d,0xfb,0x04,0x6e,
+  0x36,0xd4,0x61,0x79,0x04,0x2e,0xc3,0xcd,0x6d,0xae,0xa8,0xfc,0x95,0x9c,0xe9,0xef,
+  0xb1,0x24,0x67,0x2f,0xd0,0xd9,0x45,0xc7,0x17,0xef,0x15,0xff,0xc0,0xaa,0xf1,0x1f,
+  0xb2,0x1b,0xc4,0x3f,0xe4,0xdc,0x64,0xac,0x1d,0x96,0xf7,0xe2,0xad,0x7a,0x5b,0xf0,
+  0xfa,0x57,0x61,0xfa,0xfa,0xba,0x92,0xd3,0xd0,0xa7,0x54,0x09,0x1e,0x0e,0xeb,0xa2,
+  0x17,0xf0,0x79,0xba,0x1c,0xa5,0xa2,0x0f,0x3c,0xa0,0xc6,0x58,0x29,0xa0,0x20,0x54,
+  0xc1,0x8e,0xa6,0xd7,0xb3,0x55,0xe9,0x32,0x76,0x83,0xcf,0xc8,0x2b,0x72,0x6c,0x8c,
+  0xed,0x87,0x90,0xb1,0xb8,0xd8,0x93,0x03,0xfb,0xc3,0xba,0xb1,0x58,0x73,0xaf,0x51,
+  0xf6,0x33,0x9d,0xde,0xf7,0xb8,0x34,0x7d,0xff,0xad,0xca,0x2e,0xe9,0x00,0xae,0x36,
+  0x8f,0xe2,0x7a,0xee,0x87,0xb9,0xb4,0x7a,0xe5,0xfa,0x7e,0xd8,0x6e,0x74,0x3f,0x64,
+  0x1d,0xb1,0xd6,0xf3,0xdd,0xf4,0x7e,0x88,0xcd,0x7c,0xb7,0xe4,0xbc,0xd2,0xd0,0x7e,
+  0xdb,0x6c,0x75,0x27,0x9c,0x1f,0xf6,0x18,0xae,0xc7,0x3b,0xe7,0xc2,0xf9,0xa6,0xfa,
+  0xd0,0x75,0x5b,0x71,0xfd,0xcf,0xb6,0x07,0x96,0xe3,0xf3,0x8f,0xa6,0xf5,0x55,0x62,
+  0xd1,0x4e,0x71,0x9e,0xe3,0xb2,0x6c,0xc6,0xd5,0x38,0x0f,0x28,0x3c,0x2a,0xbf,0xbb,
+  0xe8,0x7c,0x6b,0x70,0x05,0x6e,0x0c,0x3c,0x22,0xf0,0x48,0x54,0xbe,0x90,0xd6,0x3f,
+  0x5c,0x8b,0xe1,0xd7,0x5c,0x0f,0xf9,0xe2,0x4b,0xba,0x38,0x19,0xaa,0x85,0x7c,0x90,
+  0x75,0xa0,0xf5,0xf7,0x09,0x59,0x37,0x4e,0x42,0x40,0xcb,0x17,0xf2,0xe1,0xf4,0x7e,
+  0xf6,0xe6,0xd4,0xc3,0x51,0xa3,0x4c,0xf0,0xa4,0xfb,0x46,0xc8,0x6d,0xa9,0x88,0x5d,
+  0x33,0xc6,0xbc,0xf0,0x40,0x17,0xae,0xd8,0x0a,0xd6,0x07,0x6f,0x0a,0x5c,0x9f,0x18,
+  0x3b,0x9c,0xd9,0x0f,0x4a,0x0b,0x74,0x1a,0xde,0x81,0x3c,0xdd,0x93,0x0f,0x0f,0x47,
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+  0x90,0x8c,0x73,0x9c,0x1d,0x2f,0xc4,0xe0,0x38,0x7f,0x3a,0xf2,0x00,0xcd,0x2b,0x3a,
+  0x7f,0x3e,0xcc,0x5a,0x62,0x63,0x8c,0x07,0x27,0xf0,0x76,0xe4,0x86,0x85,0x43,0xf8,
+  0x16,0xcd,0x33,0x61,0xc1,0x15,0x9f,0xc9,0xb8,0x05,0x8d,0x5e,0xe4,0x9a,0xf9,0xe3,
+  0x87,0x73,0x17,0x6a,0x0b,0x58,0xa1,0xc1,0xb0,0xbf,0x26,0x96,0xd0,0x38,0x27,0x78,
+  0x06,0x2e,0x41,0x1b,0x4d,0x3f,0x31,0x23,0x63,0xfe,0xbc,0x81,0x34,0x18,0xff,0xba,
+  0xd8,0x01,0x96,0x7a,0x15,0x2f,0x87,0x58,0x18,0xed,0x10,0x16,0x76,0xc4,0x81,0x06,
+  0xc5,0x8e,0x91,0x3f,0x38,0xdf,0x90,0x06,0x63,0x3e,0xfc,0xa2,0x8f,0x34,0x38,0x6c,
+  0x9d,0xe2,0xc3,0xc4,0x18,0xfd,0xf1,0xfc,0x52,0x8d,0xf2,0x59,0x1f,0x06,0x38,0x7f,
+  0x7a,0x76,0xd5,0xb7,0x1c,0x3c,0xd5,0xe3,0xdf,0xd1,0xc1,0x68,0xd0,0x46,0x80,0xb1,
+  0x7f,0xb0,0xa4,0x1c,0x95,0xbd,0x39,0x0b,0x2e,0xd1,0xaf,0x97,0x0f,0x45,0x49,0x34,
+  0x21,0xa0,0x16,0xc3,0xa8,0x6c,0x7e,0x62,0x1e,0x7a,0xc8,0x87,0x1b,0x34,0x55,0xf0,
+  0x4f,0x41,0xd0,0xb7,0xe0,0x34,0x16,0x36,0x26,0xc6,0xc8,0x37,0x1c,0x4f,0xf5,0x2c,
+  0xf2,0x61,0x88,0xf1,0x70,0x1e,0x69,0x10,0x4b,0x6c,0xc2,0xc2,0x7d,0xc2,0xc2,0xfd,
+  0xdc,0x10,0x5b,0x96,0xd1,0x18,0xe3,0x11,0x49,0xfe,0xe4,0xb1,0x2a,0xc1,0xfc,0xb1,
+  0xf4,0x69,0x58,0xa7,0xd8,0xb9,0x1e,0x7d,0x15,0x56,0xc8,0x54,0xcc,0xfd,0xa3,0x30,
+  0x6d,0x2a,0xb0,0xd2,0xec,0x0d,0xf6,0x42,0x71,0x64,0x61,0xfe,0x0c,0x44,0x77,0x0d,
+  0xf3,0x27,0x57,0xc4,0x16,0x1b,0x0d,0x18,0xd7,0x2f,0xe5,0x87,0xd1,0x1a,0xd0,0xf1,
+  0x1a,0xd1,0xf1,0xfa,0x52,0x62,0x69,0x7d,0x22,0x2f,0x58,0xd8,0xb2,0x37,0x38,0xd9,
+  0x59,0x2b,0x2e,0xe4,0x9a,0x3d,0xe3,0x7c,0x0f,0x40,0xc8,0x97,0xc2,0x85,0xcb,0xf9,
+  0xaf,0xe1,0x3b,0xfa,0x16,0x98,0x9d,0x97,0xf0,0xd3,0x43,0xc6,0x18,0x0f,0xf2,0xe4,
+  0xaa,0x9a,0xef,0xe6,0x83,0xc1,0x18,0xea,0x6a,0x5e,0xe5,0xcb,0xf0,0x8b,0xac,0x77,
+  0x4a,0x01,0x19,0x6c,0x21,0x63,0x1f,0x1b,0xe3,0x69,0xca,0xed,0x9b,0x6e,0x17,0xf3,
+  0x01,0x63,0x67,0xe4,0x7a,0xad,0x92,0xf3,0x8d,0x0c,0x6f,0x9e,0x36,0x66,0xfe,0x28,
+  0xcd,0x87,0x65,0xe4,0xd5,0x19,0xf7,0x11,0xb3,0xfd,0xd3,0xd9,0x48,0xf8,0x30,0xda,
+  0x79,0xd7,0x46,0x53,0x73,0x0e,0x65,0x82,0x85,0xa9,0x89,0xcc,0xfc,0xf1,0xe5,0xeb,
+  0xe7,0xa4,0x8f,0xb8,0xbc,0x11,0xd8,0x65,0xe9,0x0b,0x47,0x29,0x8c,0x1d,0xa9,0xf3,
+  0xc7,0x21,0x23,0x94,0x31,0x7f,0x68,0x02,0xa6,0xc9,0x67,0x63,0xc9,0x45,0x53,0x12,
+  0xec,0x3d,0xa3,0x70,0xe8,0x65,0xf9,0x03,0x44,0x83,0x3d,0xba,0x0d,0x6c,0x3f,0xe5,
+  0x10,0x16,0xc2,0xa3,0x40,0xd1,0x9c,0x3f,0x9b,0x62,0xab,0xd1,0xbf,0x53,0x7b,0xd1,
+  0xdd,0xcc,0x6d,0xa9,0x31,0x9a,0xf9,0xcd,0xfc,0x96,0x7a,0xf3,0xce,0xaa,0x36,0x63,
+  0x32,0xc6,0x78,0x84,0xb5,0xfc,0x41,0x63,0x71,0xd0,0xae,0x39,0xb7,0x3f,0xed,0xea,
+  0xab,0xff,0xcf,0x85,0x18,0x03,0x20,0x01,0x83,0x76,0xd5,0xc8,0x1f,0xbc,0x5e,0x5f,
+  0x6d,0xdd,0xbd,0xfe,0xc3,0x8d,0xf7,0x8f,0x9e,0xbd,0x7a,0x89,0xf8,0xf0,0xfb,0xf7,
+  0x34,0x1f,0xde,0xc8,0xf8,0xb0,0x68,0x74,0x87,0x8b,0x19,0x1f,0xbe,0x46,0x7c,0xf8,
+  0xe0,0xbe,0xe6,0xc3,0x3f,0x32,0x3e,0x3c,0xc5,0x63,0x8f,0xab,0xe7,0x09,0x0b,0x7f,
+  0x1f,0x3c,0xb8,0x7f,0xf1,0xaf,0x04,0x14,0x91,0x18,0x67,0xf0,0x61,0xfc,0xdf,0xff,
+  0xfc,0x0d,0xfb,0xff,0x3d,0x01,0xc5,0x8f,0x67,0xf1,0xe1,0xcb,0x13,0x3e,0x7c,0x6e,
+  0xe9,0xd5,0x5f,0x0f,0xea,0xd4,0xff,0xda,0x54,0xff,0x7b,0x4f,0x3e,0x7a,0x0f,0xa1,
+  0x81,0xbe,0xd8,0xe8,0x41,0xb3,0xf4,0xe4,0x6b,0x61,0xb1,0x58,0x2c,0x16,0x8b,0xc5,
+  0x62,0xb1,0x58,0xff,0x77,0xc5,0xb5,0x83,0xe4,0xda,0x81,0xc5,0x62,0xb1,0x58,0x2c,
+  0x16,0x8b,0xc5,0x62,0xcd,0x56,0x5c,0x3b,0x14,0xb8,0x76,0x60,0xb1,0x58,0x2c,0x16,
+  0x8b,0xc5,0x62,0xb1,0x58,0xb3,0x15,0xd7,0x0e,0x56,0x5c,0x3b,0xfc,0xd7,0x43,0x61,
+  0xb1,0x58,0x2c,0x16,0x8b,0xc5,0x62,0xb1,0x58,0xff,0xa2,0x3c,0x7a,0x81,0x1c,0x0a,
+  0xb7,0x3d,0x88,0xdf,0x89,0xc9,0x7b,0xa0,0x1e,0xfb,0x79,0x42,0xf2,0xb7,0x73,0x1e,
+  0x0c,0x45,0xb6,0xce,0x7b,0xef,0x4c,0xf7,0xfb,0x07,0x18,0x78,0xae,0x50,0xf1,0x33,
+  0x01,0x00,
diff --git a/board/esd/ash405/u-boot.lds b/board/esd/ash405/u-boot.lds
new file mode 100755
index 0000000..95854f2
--- /dev/null
+++ b/board/esd/ash405/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/canbt/Makefile b/board/esd/canbt/Makefile
new file mode 100755
index 0000000..a60495a
--- /dev/null
+++ b/board/esd/canbt/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c
new file mode 100755
index 0000000..2ced6cb
--- /dev/null
+++ b/board/esd/canbt/canbt.c
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2001
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "canbt.h"
+#include <asm/processor.h>
+#include <command.h>
+
+
+/*cmd_boot.c*/
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned long cntrl0Reg;
+	int index, len, i;
+	int status;
+
+	/*
+	 * Setup GPIO pins
+	 */
+	cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff;
+	cntrl0Reg |= 0x0070f000;
+	mtdcr (cntrl0, cntrl0Reg);
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+		/* set up serial port with default baudrate */
+		(void) get_clocks ();
+		gd->baudrate = CONFIG_BAUDRATE;
+		serial_init ();
+		console_init_f ();
+#endif
+		printf ("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf ("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf ("Rebooting in %2d seconds \r", i);
+			for (index = 0; index < 1000; index++)
+				udelay (1000);
+		}
+		putc ('\n');
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	/*
+	 * Setup port pins for normal operation
+	 */
+	out32 (GPIO0_ODR, 0x00000000);	/* no open drain pins */
+	out32 (GPIO0_TCR, 0x07038100);	/* setup for output */
+	out32 (GPIO0_OR, 0x07030100);	/* set output pins to high (default) */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (!i || strncmp (str, "CANBT", 5)) {
+		puts ("### No HW ID - assuming CANBT\n");
+		return (0);
+	}
+
+	puts (str);
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf ("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	return (16 * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/esd/canbt/canbt.h b/board/esd/canbt/canbt.h
new file mode 100755
index 0000000..5fc313a
--- /dev/null
+++ b/board/esd/canbt/canbt.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/board/esd/canbt/config.mk b/board/esd/canbt/config.mk
new file mode 100755
index 0000000..80076cd
--- /dev/null
+++ b/board/esd/canbt/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+TEXT_BASE = 0xFFFE0000
+#TEXT_BASE = 0xFFFD0000
diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c
new file mode 100755
index 0000000..de847f9
--- /dev/null
+++ b/board/esd/canbt/flash.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+	mtdcr(ebccfgd, pbcr);
+	/*          printf("pb1cr = %x\n", pbcr); */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/canbt/fpgadata.c b/board/esd/canbt/fpgadata.c
new file mode 100755
index 0000000..0de7d92
--- /dev/null
+++ b/board/esd/canbt/fpgadata.c
@@ -0,0 +1,404 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0c,
+ 0x69,0x6f,0x5f,0x63,0x68,0x69,0x70,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,0x73,
+ 0x30,0x35,0x78,0x6c,0x76,0x71,0x31,0x30,0x30,0x00,0x63,0x00,0x0b,0x32,0x30,0x30,
+ 0x31,0x2f,0x31,0x31,0x2f,0x32,0x33,0x00,0x64,0x00,0x09,0x31,0x33,0x3a,0x33,0x34,
+ 0x3a,0x34,0x33,0x00,0x65,0xe2,0x01,0x00,0x00,0x18,0xe6,0xff,0x30,0xe8,0x01,0x01,
+ 0x01,0x01,0xe7,0xe6,0x04,0x01,0x0d,0x04,0x07,0x03,0x05,0x03,0x05,0x03,0xe5,0xe5,
+ 0x05,0x09,0x04,0x06,0x01,0x07,0x09,0x01,0x07,0x0b,0x0f,0x07,0x03,0x05,0x03,0x05,
+ 0x03,0x11,0x03,0x0f,0x09,0x03,0x05,0x10,0xe5,0xe6,0x1a,0x0a,0x13,0x29,0x19,0x05,
+ 0x09,0x04,0x04,0x09,0x09,0x09,0x0b,0x04,0x04,0x09,0x09,0x09,0x0e,0xe5,0x01,0x14,
+ 0x09,0x09,0x09,0x03,0x05,0x0b,0x03,0x05,0x09,0x09,0x09,0x09,0x01,0xe6,0x7b,0x01,
+ 0x01,0x02,0x75,0xe8,0x3e,0x3b,0x02,0x34,0x0a,0x09,0x07,0x09,0x01,0x11,0x0a,0xe5,
+ 0xe6,0x5c,0x1e,0xe6,0xe5,0x0a,0xe5,0x50,0x1d,0x0d,0x31,0x09,0x14,0x13,0x07,0x01,
+ 0x01,0x2a,0x08,0x0b,0x1e,0x1c,0x01,0xe5,0x0f,0x09,0x09,0xe5,0x07,0x09,0xe6,0x08,
+ 0x05,0x03,0x01,0x07,0x09,0x09,0x0d,0xe8,0x0f,0x09,0xe5,0x07,0x09,0x04,0x05,0x0a,
+ 0x01,0x07,0x01,0x07,0x09,0x09,0x0d,0xe5,0xe6,0x0c,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x03,0x03,0xe5,0x06,0xe5,0xe6,0x03,0x03,0xe5,0x04,0x02,0xe5,0x01,0x05,0xe5,
+ 0x07,0xe5,0x01,0x07,0x05,0xe7,0x0f,0x09,0x09,0x09,0x10,0x04,0x05,0x03,0x03,0x05,
+ 0x09,0x09,0x08,0x08,0x04,0x01,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x02,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,0x02,0x03,
+ 0x02,0xe5,0x0e,0x09,0x09,0x09,0x15,0x09,0x09,0x09,0x09,0x0e,0xe6,0xe5,0x0c,0x09,
+ 0x09,0x09,0x09,0x04,0x04,0x01,0x09,0x06,0x02,0x09,0x09,0x11,0xe7,0x0c,0x02,0x06,
+ 0x02,0x04,0x01,0x02,0x01,0x01,0x02,0x02,0x06,0x02,0x03,0x02,0x01,0x02,0x06,0x02,
+ 0x01,0x04,0x02,0x06,0x02,0x03,0x02,0x02,0x11,0x03,0x17,0x03,0x05,0x12,0x15,0x02,
+ 0x23,0x08,0x16,0x06,0x0c,0x05,0x15,0x07,0x01,0x0a,0x02,0x0f,0x01,0x07,0x02,0xe5,
+ 0xe5,0x08,0x07,0x02,0x07,0x02,0x10,0x03,0x11,0x03,0x2b,0x05,0xe6,0x2b,0x0a,0x06,
+ 0x01,0x01,0x11,0x0b,0x0e,0xe5,0x08,0xe6,0xe5,0x0f,0x09,0x09,0x09,0x09,0x0b,0x09,
+ 0x09,0x01,0x07,0x09,0x0e,0x01,0xe5,0x0f,0x0d,0x22,0xe5,0xe5,0x27,0x0e,0xe6,0x47,
+ 0x11,0x17,0x02,0x04,0x01,0x01,0x0d,0x0d,0x1f,0x04,0x01,0x24,0x10,0x03,0x01,0x2a,
+ 0x12,0x0c,0x06,0xe5,0x0a,0x09,0x11,0xe5,0x01,0x1c,0x09,0x17,0x0b,0x09,0x09,0x04,
+ 0x19,0xe5,0x0c,0x01,0x0d,0x22,0x0a,0x01,0x0d,0xe5,0x04,0x18,0x01,0xe5,0x01,0x05,
+ 0x04,0x01,0x02,0xe5,0x14,0x10,0x0b,0x02,0x01,0x02,0x02,0xe5,0x19,0x0d,0xe5,0xe5,
+ 0x0e,0x09,0x09,0x02,0x06,0x09,0x02,0x03,0x04,0x03,0x05,0x09,0x15,0x0c,0x02,0xe5,
+ 0x01,0x0b,0x04,0x04,0x09,0x09,0x02,0x06,0x09,0xe5,0x01,0x06,0x05,0x03,0x06,0x1e,
+ 0x02,0x1c,0x1d,0x08,0xe5,0x05,0x02,0x06,0x02,0x03,0xe5,0x1b,0x03,0x17,0xe5,0x08,
+ 0x02,0x09,0xe5,0x09,0x0f,0xe5,0x08,0x07,0x09,0x06,0x0b,0x02,0x17,0xe5,0x09,0x01,
+ 0x1f,0x05,0xe5,0x02,0x05,0x03,0x1f,0xe5,0xe6,0x0e,0x09,0x03,0x05,0x03,0x05,0x09,
+ 0x11,0x01,0x01,0x04,0x0c,0x01,0x0a,0x0e,0x01,0xe5,0x0c,0xe6,0x06,0xe6,0x06,0xe6,
+ 0x06,0xe6,0x02,0x03,0xe6,0x03,0x03,0x02,0x09,0x06,0xe5,0xe5,0x25,0x14,0x1a,0x12,
+ 0x05,0x04,0x02,0x13,0x16,0xe7,0xe5,0x11,0xe5,0x11,0xe5,0x06,0xe5,0x14,0xe5,0x11,
+ 0xe5,0x03,0xe5,0x08,0xe5,0x06,0x01,0x02,0x02,0x02,0x01,0x2c,0xe5,0x08,0x01,0x1d,
+ 0xe5,0xe6,0x01,0x02,0x01,0x04,0x09,0x01,0x02,0xe6,0x03,0x04,0xe5,0x02,0x01,0x02,
+ 0xe5,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x02,0xe5,0x04,0x01,0x07,0x05,0xe5,
+ 0x01,0x01,0x02,0xe5,0x07,0xe5,0x01,0x01,0xe5,0x09,0xe5,0xe5,0xe7,0x01,0x0e,0x08,
+ 0x03,0xe5,0x04,0x02,0x06,0x02,0xe5,0x04,0x0d,0xe5,0x07,0xe5,0x08,0xe5,0x07,0x05,
+ 0x07,0x02,0x01,0x01,0xe8,0xe5,0x10,0x01,0x05,0x0c,0x10,0xe5,0x01,0x06,0xe5,0x08,
+ 0x08,0xe6,0x01,0x02,0x05,0xe5,0x04,0xe5,0x01,0x06,0xe5,0x01,0xe5,0x01,0x10,0x02,
+ 0x05,0xe5,0x01,0x06,0x02,0x06,0x02,0x05,0x03,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,
+ 0x04,0x03,0x03,0xe5,0x04,0x08,0xe6,0xe5,0xe6,0x01,0x0b,0x05,0x03,0x09,0x09,0x09,
+ 0x06,0x04,0x05,0x01,0x01,0x09,0x05,0x0a,0x01,0x01,0x02,0x08,0x02,0xe5,0xe6,0x01,
+ 0x11,0xe5,0x31,0x14,0x10,0x0a,0x02,0xe8,0x0c,0x03,0xe6,0x02,0x03,0x05,0x03,0x05,
+ 0x03,0x02,0x02,0x03,0x02,0x04,0x03,0x01,0x03,0x03,0x05,0x0d,0xe5,0x06,0x0b,0x01,
+ 0x01,0x11,0x0c,0x01,0x04,0x02,0x01,0x04,0x02,0x09,0x0b,0x01,0x07,0x01,0x07,0x09,
+ 0x13,0xe6,0xe6,0x0a,0x02,0x06,0x02,0x03,0x02,0x02,0x04,0xe6,0x01,0x05,0xe5,0x01,
+ 0x03,0x07,0x03,0x02,0x02,0x05,0xe5,0x01,0x03,0x02,0x02,0x03,0xe5,0xe5,0x01,0x06,
+ 0x04,0x01,0x01,0xe5,0xe5,0x01,0x08,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x08,
+ 0x0a,0xe5,0x05,0x09,0x02,0x09,0x05,0xe5,0x01,0x07,0xe5,0xe6,0x08,0x05,0x03,0x05,
+ 0x03,0x05,0x05,0x03,0x03,0x05,0x03,0x07,0x03,0x05,0x09,0x03,0x0a,0x08,0x0d,0xe5,
+ 0x5e,0x06,0x07,0x0b,0xe8,0x10,0x01,0x07,0x09,0x01,0x07,0x01,0x07,0x0b,0x09,0x09,
+ 0x08,0x03,0x06,0x0c,0xe8,0x09,0x54,0x01,0x0d,0x02,0x07,0x01,0x01,0x15,0xe5,0x05,
+ 0xe7,0x05,0xe7,0x07,0xe5,0x06,0xe6,0x08,0xe6,0x05,0xe7,0x06,0xe7,0xe5,0x02,0xe7,
+ 0x05,0xe7,0x0a,0x10,0xe5,0x07,0x09,0x33,0x06,0x0b,0x0f,0xe7,0x19,0x05,0x03,0x02,
+ 0x02,0x13,0x0b,0x09,0x03,0x05,0x06,0x02,0xe5,0x07,0x08,0x02,0xe5,0x1b,0xe6,0x07,
+ 0xe5,0x11,0xe5,0x01,0x07,0xe5,0x06,0xe6,0x07,0xe5,0xe5,0xe5,0x03,0xe5,0x02,0x03,
+ 0xe6,0x0a,0xe5,0x02,0x0e,0x09,0xe5,0xe6,0x04,0xe8,0x04,0x09,0xe5,0xe6,0x06,0xe5,
+ 0xe6,0x04,0xe5,0xe6,0x04,0xe5,0xe7,0xe6,0x01,0x01,0xe6,0x03,0xe8,0x06,0x01,0x01,
+ 0x0e,0x01,0x03,0x03,0x01,0x07,0x01,0x07,0x01,0xe5,0x05,0x01,0x09,0x01,0x07,0x01,
+ 0x07,0x01,0x01,0x08,0x08,0x01,0x0a,0xe9,0x10,0x01,0x01,0x05,0x01,0xe5,0x05,0x01,
+ 0xe6,0x04,0x01,0xe6,0x04,0x01,0x01,0x02,0x03,0xe5,0xe5,0xe5,0x03,0xe5,0xe5,0x06,
+ 0x01,0x02,0x04,0x01,0x07,0x01,0xe5,0x08,0x01,0xe6,0x0e,0xe5,0x02,0x0e,0xe5,0x07,
+ 0xe5,0x07,0xe5,0xe5,0x0d,0x09,0xe5,0x06,0x04,0xe5,0x05,0x01,0xe5,0x0c,0xe6,0xe6,
+ 0x1e,0x07,0x15,0x07,0x09,0xe5,0x0d,0xe5,0xe5,0xe5,0x01,0x01,0x09,0x04,0xe6,0xe6,
+ 0x04,0x02,0x04,0x01,0x02,0x09,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0x04,0x02,0x08,
+ 0x0b,0x06,0x0e,0x10,0xe5,0xe6,0x0b,0x01,0x07,0x01,0x03,0xe5,0x01,0x01,0x07,0x01,
+ 0x07,0x01,0x02,0x05,0x09,0x17,0x04,0x03,0x03,0x09,0xe7,0xe5,0x0d,0x01,0x07,0x01,
+ 0x07,0x01,0x04,0x02,0x01,0x07,0x01,0x04,0x01,0x0a,0x07,0x06,0x01,0x02,0x0a,0x13,
+ 0xe6,0x0d,0x03,0x05,0x09,0x03,0x05,0x09,0x03,0x03,0x03,0x02,0x05,0xe5,0x02,0x04,
+ 0xe5,0x07,0xe5,0x01,0x03,0x02,0x0d,0x01,0x02,0x0d,0x02,0x02,0x03,0x09,0x02,0x06,
+ 0x04,0x04,0x02,0xe5,0x04,0x01,0x05,0x03,0x01,0xe5,0x05,0x01,0x07,0x01,0x08,0x0c,
+ 0x06,0x06,0x02,0x05,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0xe5,0x03,0xe5,
+ 0x01,0xe5,0xe5,0xe5,0x06,0x09,0x01,0xe5,0x17,0x03,0x01,0xe6,0x09,0x02,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x01,0xe6,0x07,0x11,0xe5,0xe5,0x09,0x02,
+ 0x0e,0x0b,0x04,0x01,0x03,0x03,0x09,0x01,0x07,0x04,0x04,0x02,0xe5,0xe6,0x03,0x07,
+ 0x18,0xe5,0x13,0xe5,0xe6,0x0c,0xe5,0x03,0x03,0xe5,0x07,0xe5,0x02,0x04,0xe5,0x07,
+ 0xe5,0x0a,0x03,0xe5,0x01,0x01,0x07,0x01,0xe5,0x03,0xe5,0x09,0x01,0x0a,0x02,0x03,
+ 0xe5,0x0c,0xe6,0x06,0xe6,0x01,0x04,0xe6,0x06,0xe7,0xe5,0x03,0xe6,0x01,0x05,0x02,
+ 0x09,0x05,0x03,0x07,0x01,0x02,0x06,0x0a,0x03,0xe5,0xe6,0xe5,0x06,0x1c,0x1a,0xe5,
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+ 0x04,0x13,0x03,0x09,0x03,0x10,0x02,0x01,0xe5,0xe6,0x18,0x06,0x0b,0xe6,0x07,0x06,
+ 0x06,0x07,0x0e,0x1b,0xe9,0x0f,0x05,0x04,0x08,0x06,0xe5,0x04,0x05,0x02,0x03,0x14,
+ 0x04,0x03,0x1b,0x01,0x02,0x11,0x0a,0xe5,0x07,0x06,0x11,0xe5,0x39,0x02,0x0d,0xe5,
+ 0x0b,0x03,0x0c,0x10,0x01,0x39,0x01,0xe5,0xe5,0x0c,0x02,0x05,0x04,0x10,0x05,0xe5,
+ 0x0a,0x3a,0xe5,0xe6,0x01,0x16,0x0d,0x02,0x06,0x05,0xe5,0x06,0xe5,0xe5,0x0e,0x25,
+ 0xe5,0x01,0xe5,0x1b,0x09,0xe5,0x04,0x08,0xe5,0x07,0x02,0x19,0x11,0x0b,0x02,0x17,
+ 0x15,0x06,0x02,0x0a,0x3a,0xe7,0x11,0xe5,0x04,0x0f,0x4b,0xe5,0x02,0xe6,0x01,0x01,
+ 0x0e,0xe5,0x05,0x0f,0xe6,0x11,0x34,0x01,0x01,0x03,0xe5,0x03,0x05,0x01,0xe5,0xe5,
+ 0x03,0xe5,0xe5,0xe6,0x0f,0x01,0x04,0x01,0xe5,0x01,0x03,0xe5,0x02,0x04,0x28,0xe5,
+ 0x03,0x01,0x03,0x02,0x02,0x07,0x02,0x01,0x04,0xe5,0xe5,0xe6,0x0c,0xe5,0xe5,0xe5,
+ 0x03,0xe5,0x02,0x04,0x32,0xe5,0x05,0x02,0x01,0x01,0x0b,0x01,0x01,0x02,0x04,0x21,
+ 0xe5,0x01,0xe5,0xe5,0x05,0x02,0x2d,0xe7,0xe6,0x01,0x0a,0x01,0x02,0x04,0x13,0x01,
+ 0x01,0x01,0x02,0x05,0x02,0xe5,0x05,0x2e,0x02,0x03,0x01,0xe6,0x17,0x11,0x01,0x07,
+ 0x07,0x03,0x35,0x02,0xe8,0x11,0x06,0x11,0x01,0x09,0x03,0xe5,0x3d,0x01,0xe5,0x11,
+ 0x09,0x14,0x02,0x05,0x3e,0xe7,0xe5,0x1a,0xe5,0x1e,0x3d,0xe5,0x01,0xe5,0x0a,0x02,
+ 0x09,0x09,0x09,0x06,0x02,0x03,0x02,0x04,0x09,0x09,0x09,0x09,0x0d,0xe9,0x01,0x08,
+ 0xe5,0x04,0x09,0x14,0x02,0x05,0x02,0xe5,0x3a,0xe5,0xe6,0x0a,0x26,0x08,0x40,0xe6,
+ 0x0c,0x04,0x04,0x01,0x02,0x15,0x0b,0x04,0x36,0xe8,0x0e,0x01,0x02,0x02,0x01,0xe6,
+ 0xe5,0x0f,0x0a,0x09,0xe5,0x35,0xe8,0x08,0x02,0x09,0x01,0x10,0x07,0x08,0x07,0x2e,
+ 0x08,0xe7,0x0e,0x05,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x0c,0x09,0x01,0x14,0x14,0x36,
+ 0x02,0xe5,0x0e,0x07,0x16,0x4d,0x01,0xe5,0x0b,0x09,0x01,0x11,0x0b,0x01,0x06,0x02,
+ 0x36,0xe5,0xe6,0x02,0x0b,0x02,0x04,0x04,0x0e,0x02,0x11,0x39,0xe5,0x01,0x2b,0x15,
+ 0x01,0xe5,0x20,0x12,0xe5,0xe7,0x10,0x01,0x02,0x03,0xe5,0xe5,0x06,0x01,0x02,0x04,
+ 0x01,0x07,0x01,0x05,0x03,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0b,0xe5,
+ 0xe5,0x18,0x12,0x02,0x09,0x21,0x01,0x1c,0xe6,0xe6,0x13,0x1c,0x0b,0x01,0x13,0x24,
+ 0xe5,0x01,0xe5,0x18,0x14,0x10,0x3b,0x02,0x17,0x01,0x0e,0x02,0x01,0x07,0xe5,0x09,
+ 0x01,0x16,0x1a,0x05,0x02,0x17,0x01,0x13,0x0d,0x03,0x04,0x03,0x10,0x1c,0x02,0x02,
+ 0xe6,0x19,0x09,0x06,0x05,0x0f,0x37,0x01,0xe7,0x25,0x04,0x01,0x11,0x08,0x10,0x1f,
+ 0x02,0x01,0x26,0x08,0x0f,0x06,0x33,0x01,0x01,0x0a,0x10,0x0f,0x13,0x07,0x31,0x02,
+ 0xe6,0x11,0x16,0x01,0x03,0x0f,0x3b,0x02,0x14,0x01,0x16,0xe5,0x0c,0x28,0x13,0x04,
+ 0xe5,0x2b,0x0a,0x36,0x0a,0x01,0x01,0x2b,0xe5,0x0d,0x3e,0xe8,0xe5,0x75,0xe5,0x03,
+ 0x02,0x01,0x28,0x47,0x01,0x02,0xe6,0xe5,0x03,0x23,0x01,0x4a,0x04,0xe5,0x01,0x02,
+ 0x74,0x02,0xe6,0xe6,0x04,0x05,0x21,0x01,0x01,0x01,0x45,0x01,0xe6,0x01,0x08,0x25,
+ 0x02,0x3f,0x02,0x05,0xe6,0x72,0x04,0xe5,0xe5,0xe5,0x01,0x2c,0x4a,0x03,0xe6,0x2d,
+ 0x43,0x06,0x01,0xe5,0x7a,0xe8,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,
+ 0x0d,0x03,0xe5,0x01,0x27,0x4c,0x06,0x29,0x52,0x01,0x2d,0xe5,0x48,0x03,0x01,0x16,
+ 0x03,0x14,0x4a,0xe6,0xe5,0x2c,0x03,0x4a,0xe6,0x03,0x10,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0x02,
+ 0xe5,0x16,0x01,0x13,0x4c,0x03,0x17,0x01,0x63,0xe6,0x15,0x01,0x13,0x12,0x39,0x03,
+ 0x03,0x13,0x01,0x16,0x49,0xe5,0xe6,0x2a,0x01,0xe5,0x49,0x02,0xe6,0x10,0x01,0x01,
+ 0x05,0x01,0x02,0x03,0xe5,0xe5,0x02,0x03,0x01,0x01,0x05,0x01,0x01,0x02,0x03,0xe5,
+ 0xe5,0x06,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0a,0xe5,0x01,0x5b,0x22,0xe5,0x09,
+ 0x34,0x07,0x09,0x0b,0x1a,0x02,0x01,0x3f,0x3a,0xe6,0xe5,0x16,0x10,0x17,0x07,0x2b,
+ 0x08,0xe5,0x19,0x16,0x09,0x03,0x3b,0xe7,0x23,0x1a,0x04,0xe5,0x33,0x01,0xe6,0x1b,
+ 0x22,0x0a,0x0d,0x23,0x01,0x3f,0x3c,0xe6,0x20,0xe6,0x15,0x04,0x2a,0x09,0x06,0xe5,
+ 0xe5,0x23,0x1a,0xe5,0x28,0x0f,0x02,0xe5,0x38,0x41,0xe5,0xe6,0xe5,0x24,0x04,0x1a,
+ 0x30,0x01,0xe5,0xe5,0x2c,0x4c,0xe5,0x01,0xe6,0x75,0xe8,0xe5,0x01,0x01,0x70,0x01,
+ 0x03,0xe5,0xe5,0x03,0x70,0x04,0xe5,0x01,0x02,0x74,0x02,0x01,0xe6,0x01,0x78,0x02,
+ 0x74,0x02,0x02,0xe8,0x13,0x5f,0x04,0x03,0xe5,0x13,0xe5,0x63,0x01,0xe6,0x08,0x02,
+ 0x08,0x64,0xe5,0x01,0x0a,0xe5,0x6e,0xe5,0xe6,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,
+ 0x09,0x09,0x09,0x0d,0xe9,0x01,0x74,0x06,0x7a,0x03,0x01,0x2b,0x4d,0xe5,0xe5,0x23,
+ 0x08,0xe5,0x47,0x02,0xe8,0x2c,0x4b,0xe5,0x01,0xe5,0x12,0x01,0x07,0xe6,0x07,0xe5,
+ 0x02,0x03,0x01,0x09,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,
+ 0x01,0xe6,0x0f,0xe5,0x02,0x09,0x01,0x01,0xe5,0x03,0x03,0x03,0x01,0x38,0x0b,0x01,
+ 0x01,0x01,0x13,0x02,0x09,0xe5,0xe6,0x02,0x01,0x02,0x06,0x37,0x0d,0x01,0x01,0x15,
+ 0x07,0xe6,0xe5,0xe5,0x04,0x03,0x05,0x47,0xe5,0xe5,0x0f,0x02,0xe5,0x07,0xe5,0x01,
+ 0x01,0xe5,0x01,0xe5,0x03,0x03,0xe5,0x38,0x0e,0x01,0xe5,0x2e,0x33,0x15,0xe5,0xe5,
+ 0xe5,0x10,0x01,0x07,0x01,0x07,0x01,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x02,0xe5,0xe6,
+ 0x07,0x01,0xe5,0x05,0x01,0xe6,0x04,0xe7,0x05,0x01,0x07,0x01,0x0b,0xe7,0x3d,0x15,
+ 0x21,0x03,0x03,0xe5,0x3e,0x38,0xe5,0xe5,0xe5,0x12,0x02,0x09,0x1e,0x07,0x32,0x03,
+ 0xe5,0x19,0x05,0x01,0x0a,0x09,0x06,0x3a,0xe5,0x01,0x23,0x03,0x17,0x3a,0x03,0xe5,
+ 0x1f,0x1d,0x16,0xe5,0x24,0xe5,0x1e,0x09,0x12,0x02,0x15,0x01,0x23,0xe7,0x3e,0x23,
+ 0x17,0x01,0xe5,0x3e,0x3c,0xe6,0x24,0x19,0x3d,0xe6,0x1b,0xe5,0x04,0x02,0xe5,0x08,
+ 0x38,0x12,0x33,0x36,0xe6,0x0b,0x01,0xe5,0xe5,0x6a,0x10,0xe6,0x02,0x0b,0xe5,0xe5,
+ 0x05,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe7,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x0b,0x03,0xe5,0x0f,0x09,0x09,0x09,0x09,0x04,0x04,0x01,0x09,0x09,0x09,
+ 0x01,0x07,0x0d,0xe5,0xe6,0x0e,0x09,0x03,0x05,0x09,0x09,0x04,0x06,0x04,0x04,0x04,
+ 0x04,0x04,0x04,0x09,0x0e,0x03,0x26,0x57,0x0f,0x09,0x09,0x09,0x09,0x0b,0x01,0x07,
+ 0x09,0x09,0x02,0x06,0x0e,0xe5,0xe6,0x0c,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0e,0x03,0x03,0x09,0x09,
+ 0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x12,0xe6,0x0d,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x0b,0x03,0x0e,0x09,0x09,0x09,0x09,0x03,
+ 0x07,0x09,0x09,0x09,0x09,0x0f,0x02,0xe5,0x79,0xe5,0x01,0x0e,0x09,0x09,0x09,0x09,
+ 0x08,0x02,0x09,0x09,0x09,0x09,0x11,0xe6,0x3e,0x3b,0x02,0x10,0x09,0x09,0x09,0x09,
+ 0x0b,0x09,0x09,0x09,0x09,0x10,0xe5,0x7d,0x3f,0x3a,0xe5,0x01,0x3f,0x36,0x04,0x02,
+ 0x7a,0x01,0x01,0x13,0x3d,0x28,0x01,0x01,0x3f,0x33,0x0a,0x3f,0x34,0x08,0xe5,0x79,
+ 0x01,0x01,0x14,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0xe5,0x01,0x0f,
+ 0x09,0x09,0x09,0x09,0x07,0x03,0x09,0x09,0x09,0x08,0xe5,0x0d,0x03,0x3a,0x04,0x3a,
+ 0x02,0xe5,0x0c,0x09,0x03,0x05,0x09,0x09,0x03,0x07,0x09,0x09,0x07,0x01,0x1b,0x01,
+ 0xe5,0x0a,0x02,0x07,0x05,0x03,0x01,0x03,0x03,0x01,0x03,0x03,0x09,0x06,0xe5,0x02,
+ 0x04,0x04,0x04,0x02,0x06,0xe5,0x02,0x02,0x06,0x02,0xe5,0x02,0x03,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,
diff --git a/board/esd/canbt/u-boot.lds b/board/esd/canbt/u-boot.lds
new file mode 100755
index 0000000..ff15b3f
--- /dev/null
+++ b/board/esd/canbt/u-boot.lds
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o		(.text)
+    cpu/ppc4xx/traps.o		(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o		(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/extable.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_generic/crc32.o		(.text)
+
+    common/cmd_boot.o		(.text)
+    common/cmd_bootm.o		(.text)
+    common/cmd_flash.o		(.text)
+    common/cmd_mem.o		(.text)
+    common/cmd_nvedit.o		(.text)
+    common/console.o		(.text)
+    common/lists.o		(.text)
+    common/main.o		(.text)
+    net/net.o			(.text)
+
+/*    . = env_offset;
+    common/environment.o	(.text)
+*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
new file mode 100755
index 0000000..a11ee82
--- /dev/null
+++ b/board/esd/cms700/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
new file mode 100755
index 0000000..649619d
--- /dev/null
+++ b/board/esd/cms700/cms700.c
@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+/* fpga configuration data - not compressed, generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+int filesize = sizeof(fpgadata);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * Reset CPLD via GPIO12 (CS3) pin
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+	udelay(1000); /* wait 1ms */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+	udelay(1000); /* wait 1ms */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+ 	/*
+	 * Setup and enable EEPROM write protection
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char str[64];
+	int flashcnt;
+	int delay;
+	volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
+	volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);
+
+	puts ("Board: ");
+
+	if (getenv_r("serial#", str, sizeof(str))  == -1) {
+		puts ("### No HW ID - assuming CMS700");
+	} else {
+		puts(str);
+	}
+
+	printf(" (PLD-Version=%02d)\n", *ver_reg);
+
+	/*
+	 * Flash LEDs
+	 */
+	for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+		*led_reg = 0x00;        /* LEDs off */
+		for (delay = 0; delay < 100; delay++)
+			udelay(1000);
+		*led_reg = 0x0f;        /* LEDs on */
+		for (delay = 0; delay < 50; delay++)
+			udelay(1000);
+	}
+	*led_reg = 0x70;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	   "eepwren - Enable / disable / query EEPROM write access\n",
+	   NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk
new file mode 100755
index 0000000..5c3c01c
--- /dev/null
+++ b/board/esd/cms700/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd CMS405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/cms700/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/cms700/fpgadata.c b/board/esd/cms700/fpgadata.c
new file mode 100755
index 0000000..08be5e7
--- /dev/null
+++ b/board/esd/cms700/fpgadata.c
@@ -0,0 +1,1812 @@
+  0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,
+  0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00,
+  0xf9,0x60,0x40,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00,
+  0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08,
+  0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
+  0x08,0xea,0x08,0x00,0x00,0x00,0x32,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x04,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x00,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x00,0x24,0x00,0x1c,0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x00,0x28,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x30,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
+  0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
+  0x00,0x14,0x00,0x61,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x00,0x00,0x03,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,
+  0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x84,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x09,0x00,0x00,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x90,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
+  0xa0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa4,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xb0,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc0,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x09,0x00,0x00,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,
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+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa4,0x00,0x1c,
+  0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa8,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc0,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x14,0x00,0x61,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x35,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x35,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,
+  0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff,
+  0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00,
diff --git a/board/esd/cms700/u-boot.lds b/board/esd/cms700/u-boot.lds
new file mode 100755
index 0000000..f7a20d1
--- /dev/null
+++ b/board/esd/cms700/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
new file mode 100755
index 0000000..d48e972
--- /dev/null
+++ b/board/esd/common/auto_update.c
@@ -0,0 +1,556 @@
+/*
+ * (C) Copyright 2003-2004
+ * Gary Jennejohn, DENX Software Engineering, gj@denx.de.
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <linux/mtd/nand.h>
+#include <fat.h>
+
+#include "auto_update.h"
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#if !(CONFIG_COMMANDS & CFG_CMD_FAT)
+#error "must define CFG_CMD_FAT"
+#endif
+
+extern au_image_t au_image[];
+extern int N_AU_IMAGES;
+
+#define AU_DEBUG
+#undef AU_DEBUG
+
+#undef debug
+#ifdef	AU_DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif	/* AU_DEBUG */
+
+
+#define LOAD_ADDR ((unsigned char *)0x100000)   /* where to load files into memory */
+#define MAX_LOADSZ 0x1e00000
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols);
+#ifdef CONFIG_VFD
+extern int trab_vfd (ulong);
+extern int transfer_pic(unsigned char, unsigned char *, int, int);
+#endif
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
+/* change char* to void* to shutup the compiler */
+extern block_dev_desc_t *get_dev (char*, int);
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+/* references to names in cmd_nand.c */
+#define NANDRW_READ	0x01
+#define NANDRW_WRITE	0x00
+#define NANDRW_JFFS2	0x02
+#define NANDRW_JFFS2_SKIP	0x04
+extern struct nand_chip nand_dev_desc[];
+extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len,
+		   size_t * retlen, u_char * buf);
+extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+
+extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
+
+
+int au_check_cksum_valid(int i, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	if ((au_image[i].type == AU_FIRMWARE) && (au_image[i].size != ntohl(hdr->ih_size))) {
+		printf ("Image %s has wrong size\n", au_image[i].name);
+		return -1;
+	}
+
+	if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) {
+		printf ("Image %s bad total SIZE\n", au_image[i].name);
+		return -1;
+	}
+	/* check the data CRC */
+	checksum = ntohl(hdr->ih_dcrc);
+
+	if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
+		!= checksum) {
+		printf ("Image %s bad data checksum\n", au_image[i].name);
+		return -1;
+	}
+	return 0;
+}
+
+
+int au_check_header_valid(int i, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* check the easy ones first */
+#undef CHECK_VALID_DEBUG
+#ifdef CHECK_VALID_DEBUG
+	printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC);
+	printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_PPC);
+	printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes);
+	printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL);
+#endif
+	if (nbytes < sizeof(*hdr))
+	{
+		printf ("Image %s bad header SIZE\n", au_image[i].name);
+		return -1;
+	}
+	if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC)
+	{
+		printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name);
+		return -1;
+	}
+	/* check the hdr CRC */
+	checksum = ntohl(hdr->ih_hcrc);
+	hdr->ih_hcrc = 0;
+
+	if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) {
+		printf ("Image %s bad header checksum\n", au_image[i].name);
+		return -1;
+	}
+	hdr->ih_hcrc = htonl(checksum);
+
+	/* check the type - could do this all in one gigantic if() */
+	if ((au_image[i].type == AU_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", au_image[i].name);
+		return -1;
+	}
+	if ((au_image[i].type == AU_SCRIPT) && (hdr->ih_type != IH_TYPE_SCRIPT)) {
+		printf ("Image %s wrong type\n", au_image[i].name);
+		return -1;
+	}
+
+	/* recycle checksum */
+	checksum = ntohl(hdr->ih_size);
+
+#if 0 /* test-only */
+	/* for kernel and app the image header must also fit into flash */
+	if (idx != IDX_DISK)
+		checksum += sizeof(*hdr);
+	/* check the size does not exceed space in flash. HUSH scripts */
+	/* all have ausize[] set to 0 */
+	if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
+		printf ("Image %s is bigger than FLASH\n", au_image[i].name);
+		return -1;
+	}
+#endif
+
+	return 0;
+}
+
+
+int au_do_update(int i, long sz)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	int off, rc;
+	uint nbytes;
+	int k;
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	int total;
+#endif
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	switch (au_image[i].type) {
+	case AU_SCRIPT:
+		printf("Executing script %s\n", au_image[i].name);
+
+		/* execute a script */
+		if (hdr->ih_type == IH_TYPE_SCRIPT) {
+			addr = (char *)((char *)hdr + sizeof(*hdr));
+			/* stick a NULL at the end of the script, otherwise */
+			/* parse_string_outer() runs off the end. */
+			addr[ntohl(hdr->ih_size)] = 0;
+			addr += 8;
+
+			/*
+			 * Replace cr/lf with ;
+			 */
+			k = 0;
+			while (addr[k] != 0) {
+				if ((addr[k] == 10) || (addr[k] == 13)) {
+					addr[k] = ';';
+				}
+				k++;
+			}
+
+			run_command(addr, 0);
+			return 0;
+		}
+
+		break;
+
+	case AU_FIRMWARE:
+	case AU_NOR:
+	case AU_NAND:
+		start = au_image[i].start;
+		end = au_image[i].start + au_image[i].size - 1;
+
+		/*
+		 * do not update firmware when image is already in flash.
+		 */
+		if (au_image[i].type == AU_FIRMWARE) {
+			char *orig = (char*)start;
+			char *new  = (char *)((char *)hdr + sizeof(*hdr));
+			nbytes = ntohl(hdr->ih_size);
+
+			while(--nbytes) {
+				if (*orig++ != *new++) {
+					break;
+				}
+			}
+			if (!nbytes) {
+				printf("Skipping firmware update - images are identical\n");
+				break;
+			}
+		}
+
+		/* unprotect the address range */
+		/* this assumes that ONLY the firmware is protected! */
+		if (au_image[i].type == AU_FIRMWARE) {
+			flash_sect_protect(0, start, end);
+		}
+
+		/*
+		 * erase the address range.
+		 */
+		if (au_image[i].type != AU_NAND) {
+			printf("Updating NOR FLASH with image %s\n", au_image[i].name);
+			debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+			flash_sect_erase(start, end);
+		} else {
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+			printf("Updating NAND FLASH with image %s\n", au_image[i].name);
+			debug ("nand_erase(%lx, %lx);\n", start, end);
+			rc = nand_erase (nand_dev_desc, start, end - start + 1, 0);
+			debug ("nand_erase returned %x\n", rc);
+#endif
+		}
+
+		udelay(10000);
+
+		/* strip the header - except for the kernel and ramdisk */
+		if (au_image[i].type != AU_FIRMWARE) {
+			addr = (char *)hdr;
+			off = sizeof(*hdr);
+			nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
+		} else {
+			addr = (char *)((char *)hdr + sizeof(*hdr));
+			off = 0;
+			nbytes = ntohl(hdr->ih_size);
+		}
+
+		/*
+		 * copy the data from RAM to FLASH
+		 */
+		if (au_image[i].type != AU_NAND) {
+			debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
+			rc = flash_write((uchar *)addr, start, nbytes);
+		} else {
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+			debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes);
+			rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
+				     start, nbytes, (size_t *)&total, (uchar *)addr);
+			debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
+#endif
+		}
+		if (rc != 0) {
+			printf("Flashing failed due to error %d\n", rc);
+			return -1;
+		}
+
+		/*
+		 * check the dcrc of the copy
+		 */
+		if (au_image[i].type != AU_NAND) {
+			rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size));
+		} else {
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+			rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP,
+				     start, nbytes, (size_t *)&total, (uchar *)addr);
+			rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size));
+#endif
+		}
+		if (rc != ntohl(hdr->ih_dcrc)) {
+			printf ("Image %s Bad Data Checksum After COPY\n", au_image[i].name);
+			return -1;
+		}
+
+		/* protect the address range */
+		/* this assumes that ONLY the firmware is protected! */
+		if (au_image[i].type == AU_FIRMWARE) {
+			flash_sect_protect(1, start, end);
+		}
+
+		break;
+
+	default:
+		printf("Wrong image type selected!\n");
+	}
+
+	return 0;
+}
+
+
+static void process_macros (const char *input, char *output)
+{
+	char c, prev;
+	const char *varname_start = NULL;
+	int inputcnt  = strlen (input);
+	int outputcnt = CFG_CBSIZE;
+	int state = 0;	/* 0 = waiting for '$'	*/
+			/* 1 = waiting for '(' or '{' */
+			/* 2 = waiting for ')' or '}' */
+			/* 3 = waiting for '''  */
+#ifdef DEBUG_PARSER
+	char *output_start = output;
+
+	printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input);
+#endif
+
+	prev = '\0';			/* previous character	*/
+
+	while (inputcnt && outputcnt) {
+	    c = *input++;
+	    inputcnt--;
+
+	    if (state!=3) {
+	    /* remove one level of escape characters */
+	    if ((c == '\\') && (prev != '\\')) {
+		if (inputcnt-- == 0)
+			break;
+		prev = c;
+		c = *input++;
+	    }
+	    }
+
+	    switch (state) {
+	    case 0:			/* Waiting for (unescaped) $	*/
+		if ((c == '\'') && (prev != '\\')) {
+			state = 3;
+			break;
+		}
+		if ((c == '$') && (prev != '\\')) {
+			state++;
+		} else {
+			*(output++) = c;
+			outputcnt--;
+		}
+		break;
+	    case 1:			/* Waiting for (	*/
+		if (c == '(' || c == '{') {
+			state++;
+			varname_start = input;
+		} else {
+			state = 0;
+			*(output++) = '$';
+			outputcnt--;
+
+			if (outputcnt) {
+				*(output++) = c;
+				outputcnt--;
+			}
+		}
+		break;
+	    case 2:			/* Waiting for )	*/
+		if (c == ')' || c == '}') {
+			int i;
+			char envname[CFG_CBSIZE], *envval;
+			int envcnt = input-varname_start-1; /* Varname # of chars */
+
+			/* Get the varname */
+			for (i = 0; i < envcnt; i++) {
+				envname[i] = varname_start[i];
+			}
+			envname[i] = 0;
+
+			/* Get its value */
+			envval = getenv (envname);
+
+			/* Copy into the line if it exists */
+			if (envval != NULL)
+				while ((*envval) && outputcnt) {
+					*(output++) = *(envval++);
+					outputcnt--;
+				}
+			/* Look for another '$' */
+			state = 0;
+		}
+		break;
+	    case 3:			/* Waiting for '	*/
+		if ((c == '\'') && (prev != '\\')) {
+			state = 0;
+		} else {
+			*(output++) = c;
+			outputcnt--;
+		}
+		break;
+	    }
+	    prev = c;
+	}
+
+	if (outputcnt)
+		*output = 0;
+
+#ifdef DEBUG_PARSER
+	printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",
+		strlen(output_start), output_start);
+#endif
+}
+
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev;
+	long sz;
+	int i, res, cnt, old_ctrlc, got_ctrlc;
+	char buffer[32];
+	char str[80];
+
+	/*
+	 * Check whether a CompactFlash is inserted
+	 */
+	if (ide_dev_desc[0].type == DEV_TYPE_UNKNOWN) {
+		return -1;       /* no disk detected! */
+	}
+
+	/* check whether it has a partition table */
+	stor_dev = get_dev("ide", 0);
+	if (stor_dev == NULL) {
+		debug ("Uknown device type\n");
+		return -1;
+	}
+	if (fat_register_device(stor_dev, 1) != 0) {
+		debug ("Unable to register ide disk 0:1 for fatls\n");
+		return -1;
+	}
+
+	/*
+	 * Check if magic file is present
+	 */
+	if (do_fat_read(AU_MAGIC_FILE, buffer, sizeof(buffer), LS_NO) <= 0) {
+		return -1;
+	}
+
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+	board_auto_update_show(1);
+#endif
+	puts("\nAutoUpdate Disk detected! Trying to update system...\n");
+
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc(0);
+
+	/* just loop thru all the possible files */
+	for (i = 0; i < N_AU_IMAGES; i++) {
+		/*
+		 * Try to expand the environment var in the fname
+		 */
+		process_macros(au_image[i].name, str);
+		strcpy(au_image[i].name, str);
+
+		printf("Reading %s ...", au_image[i].name);
+		/* just read the header */
+		sz = do_fat_read(au_image[i].name, LOAD_ADDR, sizeof(image_header_t), LS_NO);
+		debug ("read %s sz %ld hdr %d\n",
+			au_image[i].name, sz, sizeof(image_header_t));
+		if (sz <= 0 || sz < sizeof(image_header_t)) {
+			puts(" not found\n");
+			continue;
+		}
+		if (au_check_header_valid(i, sz) < 0) {
+			puts(" header not valid\n");
+			continue;
+		}
+		sz = do_fat_read(au_image[i].name, LOAD_ADDR, MAX_LOADSZ, LS_NO);
+		debug ("read %s sz %ld hdr %d\n",
+			au_image[i].name, sz, sizeof(image_header_t));
+		if (sz <= 0 || sz <= sizeof(image_header_t)) {
+			puts(" not found\n");
+			continue;
+		}
+		if (au_check_cksum_valid(i, sz) < 0) {
+			puts(" checksum not valid\n");
+			continue;
+		}
+		puts(" done\n");
+
+		do {
+			res = au_do_update(i, sz);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc()) {
+				clear_ctrlc();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+		} while (res < 0);
+	}
+
+	/* restore the old state */
+	disable_ctrlc(old_ctrlc);
+
+	puts("AutoUpdate finished\n\n");
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+	board_auto_update_show(0);
+#endif
+
+	return 0;
+}
+
+
+int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	do_auto_update();
+
+	return 0;
+}
+U_BOOT_CMD(
+	autoupd,	1,	1,	auto_update,
+	"autoupd - Automatically update images\n",
+	NULL
+);
+#endif /* CONFIG_AUTO_UPDATE */
diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h
new file mode 100755
index 0000000..e2af3c7
--- /dev/null
+++ b/board/esd/common/auto_update.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _AUTO_UPDATE_H_
+#define _AUTO_UPDATE_H_
+
+#define MBR_MAGIC       0x07081967
+#define MBR_MAGIC_ADDR  0x100           /* offset 0x100 should be free space */
+
+#define AU_MAGIC_FILE   "__auto_update"
+
+#define AU_SCRIPT       1
+#define AU_FIRMWARE     2
+#define AU_NOR          3
+#define AU_NAND         4
+
+struct au_image_s {
+	char name[80];
+	ulong start;
+	ulong size;
+	int type;
+};
+
+typedef struct au_image_s au_image_t;
+
+int do_auto_update(void);
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+void board_auto_update_show(int au_active);
+#endif
+
+#endif /* #ifndef _AUTO_UPDATE_H_ */
diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c
new file mode 100755
index 0000000..dca10be
--- /dev/null
+++ b/board/esd/common/flash.c
@@ -0,0 +1,672 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	short n;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+				break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+				break;
+	case FLASH_AM640U:	printf ("AM29LV640D (64 M, uniform sector)\n");
+				break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST320:	printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST640:	printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CFG_FLASH_READ0];
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+		info->flash_id = FLASH_MAN_EXCEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CFG_FLASH_READ1];		/* device ID		*/
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;  break;	/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;  break;	/* => 8 MB	*/
+
+#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A:
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601:
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF1602:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF3201:
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF3202:
+		info->flash_id += FLASH_SST320;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF6401:
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF6402:
+		info->flash_id += FLASH_SST640;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+		    addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			for (i=0; i<50; i++)
+			  udelay(1000);  /* wait 1 ms */
+		    } else {
+			if (sect == s_first) {
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			}
+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    }
+		    l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c
new file mode 100755
index 0000000..ad56402
--- /dev/null
+++ b/board/esd/common/fpga.c
@@ -0,0 +1,282 @@
+/*
+ * (C) Copyright 2001-2004
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef FPGA_DEBUG
+#define DBG(x...) printf(x)
+#else
+#define DBG(x...)
+#endif /* DEBUG */
+
+#define MAX_ONES               226
+
+#ifdef CFG_FPGA_PRG
+# define FPGA_PRG              CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
+# define FPGA_CLK              CFG_FPGA_CLK /* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CFG_FPGA_DATA /* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CFG_FPGA_DONE /* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CFG_FPGA_INIT /* FPGA init pin (ppc input)   */
+#else
+# define FPGA_PRG              0x04000000  /* FPGA program pin (ppc output) */
+# define FPGA_CLK              0x02000000  /* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             0x01000000  /* FPGA data pin (ppc output)    */
+# define FPGA_DONE             0x00800000  /* FPGA done pin (ppc input)     */
+# define FPGA_INIT             0x00400000  /* FPGA init pin (ppc input)     */
+#endif
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
+
+#ifndef SET_FPGA
+# define SET_FPGA(data)         out32(GPIO0_OR, data)
+#endif
+
+#ifdef FPGA_PROG_ACTIVE_HIGH
+# define FPGA_PRG_LOW           FPGA_PRG
+# define FPGA_PRG_HIGH          0
+#else
+# define FPGA_PRG_LOW           0
+# define FPGA_PRG_HIGH          FPGA_PRG
+#endif
+
+#define FPGA_CLK_LOW            0
+#define FPGA_CLK_HIGH           FPGA_CLK
+
+#define FPGA_DATA_LOW           0
+#define FPGA_DATA_HIGH          FPGA_DATA
+
+#define FPGA_WRITE_1 {                                                                   \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1  */
+
+#define FPGA_WRITE_0 {                                                    \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_LOW);   /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW);   /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1  */
+
+#ifndef FPGA_DONE_STATE
+# define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE)
+#endif
+#ifndef FPGA_INIT_STATE
+# define FPGA_INIT_STATE (in32(GPIO0_IR) & FPGA_INIT)
+#endif
+
+
+static int fpga_boot(unsigned char *fpgadata, int size)
+{
+  int i,index,len;
+  int count;
+#ifdef CFG_FPGA_SPARTAN2
+  int j;
+#else
+  unsigned char b;
+  int bit;
+#endif
+
+  /* display infos on fpgaimage */
+  index = 15;
+  for (i=0; i<4; i++)
+    {
+      len = fpgadata[index];
+      DBG("FPGA: %s\n", &(fpgadata[index+1]));
+      index += len+3;
+    }
+
+#ifdef CFG_FPGA_SPARTAN2
+  /* search for preamble 0xFFFFFFFF */
+  while (1)
+    {
+      if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
+	  (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
+	break; /* preamble found */
+      else
+	index++;
+    }
+#else
+  /* search for preamble 0xFF2X */
+  for (index = 0; index < size-1 ; index++)
+    {
+      if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30))
+	break;
+    }
+  index += 2;
+#endif
+
+  DBG("FPGA: configdata starts at position 0x%x\n",index);
+  DBG("FPGA: length of fpga-data %d\n", size-index);
+
+  /*
+   * Setup port pins for fpga programming
+   */
+#ifndef CONFIG_M5249
+  out32(GPIO0_ODR, 0x00000000);                                      /* no open drain pins */
+  out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
+#endif
+  SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);            /* set pins to high */
+
+  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+  /*
+   * Init fpga by asserting and deasserting PROGRAM*
+   */
+  SET_FPGA(FPGA_PRG_LOW  | FPGA_CLK_HIGH | FPGA_DATA_HIGH);             /* set prog active */
+
+  /* Wait for FPGA init line low */
+  count = 0;
+  while (FPGA_INIT_STATE)
+    {
+      udelay(1000); /* wait 1ms */
+      /* Check for timeout - 100us max, so use 3ms */
+      if (count++ > 3)
+	{
+	  DBG("FPGA: Booting failed!\n");
+	  return ERROR_FPGA_PRG_INIT_LOW;
+	}
+    }
+
+  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+  /* deassert PROGRAM* */
+  SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);           /* set prog inactive */
+
+  /* Wait for FPGA end of init period .  */
+  count = 0;
+  while (!(FPGA_INIT_STATE))
+    {
+      udelay(1000); /* wait 1ms */
+      /* Check for timeout */
+      if (count++ > 3)
+	{
+	  DBG("FPGA: Booting failed!\n");
+	  return ERROR_FPGA_PRG_INIT_HIGH;
+	}
+    }
+
+  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+  DBG("write configuration data into fpga\n");
+  /* write configuration-data into fpga... */
+
+#ifdef CFG_FPGA_SPARTAN2
+  /*
+   * Load uncompressed image into fpga
+   */
+  for (i=index; i<size; i++)
+    {
+      for (j=0; j<8; j++)
+	{
+	  if ((fpgadata[i] & 0x80) == 0x80)
+	    {
+	      FPGA_WRITE_1;
+	    }
+	  else
+	    {
+	      FPGA_WRITE_0;
+	    }
+	  fpgadata[i] <<= 1;
+	}
+    }
+#else
+  /* send 0xff 0x20 */
+  FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
+  FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
+  FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_1; FPGA_WRITE_0;
+  FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0;
+
+  /*
+  ** Bit_DeCompression
+  **   Code 1           .. maxOnes     : n                 '1's followed by '0'
+  **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
+  **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
+  **        255                        :                   '1'
+  */
+
+  for (i=index; i<size; i++)
+    {
+      b = fpgadata[i];
+      if ((b >= 1) && (b <= MAX_ONES))
+	{
+	  for(bit=0; bit<b; bit++)
+	    {
+	      FPGA_WRITE_1;
+	    }
+	  FPGA_WRITE_0;
+	}
+      else if (b == (MAX_ONES+1))
+	{
+	  for(bit=1; bit<b; bit++)
+	    {
+	      FPGA_WRITE_1;
+	    }
+	}
+      else if ((b >= (MAX_ONES+2)) && (b <= 254))
+	{
+	  for(bit=0; bit<(b-(MAX_ONES+2)); bit++)
+	    {
+	      FPGA_WRITE_0;
+	    }
+	  FPGA_WRITE_1;
+	}
+      else if (b == 255)
+	{
+	  FPGA_WRITE_1;
+	}
+    }
+#endif
+
+  DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" );
+  DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" );
+
+  /*
+   * Check if fpga's DONE signal - correctly booted ?
+   */
+
+  /* Wait for FPGA end of programming period .  */
+  count = 0;
+  while (!(FPGA_DONE_STATE))
+    {
+      udelay(1000); /* wait 1ms */
+      /* Check for timeout */
+      if (count++ > 3)
+	{
+	  DBG("FPGA: Booting failed!\n");
+	  return ERROR_FPGA_PRG_DONE;
+	}
+    }
+
+  DBG("FPGA: Booting successful!\n");
+  return 0;
+}
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
new file mode 100755
index 0000000..0edc083
--- /dev/null
+++ b/board/esd/common/lcd.c
@@ -0,0 +1,334 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "lcd.h"
+
+
+extern int video_display_bitmap (ulong, int, int);
+
+
+int palette_index;
+int palette_value;
+int lcd_depth;
+unsigned char *glob_lcd_reg;
+unsigned char *glob_lcd_mem;
+
+#ifdef CFG_LCD_ENDIAN
+void lcd_setup(int lcd, int config)
+{
+	if (lcd == 0) {
+		/*
+		 * Set endianess and reset lcd controller 0 (small)
+		 */
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
+		udelay(10); /* wait 10us */
+		if (config == 1) {
+			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
+		} else {
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
+		}
+		udelay(10); /* wait 10us */
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
+	} else {
+		/*
+		 * Set endianess and reset lcd controller 1 (big)
+		 */
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
+		udelay(10); /* wait 10us */
+		if (config == 1) {
+			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
+		} else {
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
+		}
+		udelay(10); /* wait 10us */
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
+	}
+
+	/*
+	 * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */
+}
+#endif /* #ifdef CFG_LCD_ENDIAN */
+
+
+void lcd_bmp(uchar *logo_bmp)
+{
+	int i;
+	uchar *ptr;
+	ushort *ptr2;
+	ushort val;
+	unsigned char *dst = NULL;
+	int x, y;
+	int width, height, bpp, colors, line_size;
+	int header_size;
+	unsigned char *bmp;
+	unsigned char r, g, b;
+	BITMAPINFOHEADER *bm_info;
+	ulong len;
+
+	/*
+	 * Check for bmp mark 'BM'
+	 */
+	if (*(ushort *)logo_bmp != 0x424d) {
+
+		/*
+		 * Decompress bmp image
+		 */
+		len = CFG_VIDEO_LOGO_MAX_SIZE;
+		dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
+		if (dst == NULL) {
+			printf("Error: malloc in gunzip failed!\n");
+			return;
+		}
+		if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) {
+			return;
+		}
+		if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
+			printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
+		}
+
+		/*
+		 * Check for bmp mark 'BM'
+		 */
+		if (*(ushort *)dst != 0x424d) {
+			printf("LCD: Unknown image format!\n");
+			free(dst);
+			return;
+		}
+	} else {
+		/*
+		 * Uncompressed BMP image, just use this pointer
+		 */
+		dst = (uchar *)logo_bmp;
+	}
+
+	/*
+	 * Get image info from bmp-header
+	 */
+	bm_info = (BITMAPINFOHEADER *)(dst + 14);
+	bpp = LOAD_SHORT(bm_info->biBitCount);
+	width = LOAD_LONG(bm_info->biWidth);
+	height = LOAD_LONG(bm_info->biHeight);
+	switch (bpp) {
+	case 1:
+		colors = 1;
+		line_size = width >> 3;
+		break;
+	case 4:
+		colors = 16;
+		line_size = width >> 1;
+		break;
+	case 8:
+		colors = 256;
+		line_size = width;
+		break;
+	case 24:
+		colors = 0;
+		line_size = width * 3;
+		break;
+	default:
+		printf("LCD: Unknown bpp (%d) im image!\n", bpp);
+		if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
+			free(dst);
+		}
+		return;
+	}
+	printf(" (%d*%d, %dbpp)\n", width, height, bpp);
+
+	/*
+	 * Write color palette
+	 */
+	if ((colors <= 256) && (lcd_depth <= 8)) {
+		ptr = (unsigned char *)(dst + 14 + 40);
+		for (i=0; i<colors; i++) {
+			b = *ptr++;
+			g = *ptr++;
+			r = *ptr++;
+			ptr++;
+			S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b);
+		}
+	}
+
+	/*
+	 * Write bitmap data into framebuffer
+	 */
+	ptr = glob_lcd_mem;
+	ptr2 = (ushort *)glob_lcd_mem;
+	header_size = 14 + 40 + 4*colors;          /* skip bmp header */
+	for (y=0; y<height; y++) {
+		bmp = &dst[(height-1-y)*line_size + header_size];
+		if (lcd_depth == 16) {
+			if (bpp == 24) {
+				for (x=0; x<width; x++) {
+					/*
+					 * Generate epson 16bpp fb-format from 24bpp image
+					 */
+					b = *bmp++ >> 3;
+					g = *bmp++ >> 2;
+					r = *bmp++ >> 3;
+					val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
+					*ptr2++ = val;
+				}
+			} else if (bpp == 8) {
+				for (x=0; x<line_size; x++) {
+					/* query rgb value from palette */
+					ptr = (unsigned char *)(dst + 14 + 40) ;
+					ptr += (*bmp++) << 2;
+					b = *ptr++ >> 3;
+					g = *ptr++ >> 2;
+					r = *ptr++ >> 3;
+					val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f);
+					*ptr2++ = val;
+				}
+			}
+		} else {
+			for (x=0; x<line_size; x++) {
+				*ptr++ = *bmp++;
+			}
+		}
+	}
+
+	if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
+		free(dst);
+	}
+}
+
+
+void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
+	      uchar *logo_bmp, ulong len)
+{
+	int i;
+	ushort s1dReg;
+	uchar s1dValue;
+	int reg_byte_swap;
+
+	/*
+	 * Detect epson
+	 */
+	if (lcd_reg[0] == 0x1c) {
+		/*
+		 * Big epson detected
+		 */
+		reg_byte_swap = FALSE;
+		palette_index = 0x1e2;
+		palette_value = 0x1e4;
+		lcd_depth = 16;
+		puts("LCD:   S1D13806");
+	} else if (lcd_reg[1] == 0x1c) {
+		/*
+		 * Big epson detected (with register swap bug)
+		 */
+		reg_byte_swap = TRUE;
+		palette_index = 0x1e3;
+		palette_value = 0x1e5;
+		lcd_depth = 16;
+		puts("LCD:   S1D13806S");
+	} else if (lcd_reg[0] == 0x18) {
+		/*
+		 * Small epson detected (704)
+		 */
+		reg_byte_swap = FALSE;
+		palette_index = 0x15;
+		palette_value = 0x17;
+		lcd_depth = 8;
+		puts("LCD:   S1D13704");
+	} else if (lcd_reg[0x10000] == 0x24) {
+		/*
+		 * Small epson detected (705)
+		 */
+		reg_byte_swap = FALSE;
+		palette_index = 0x15;
+		palette_value = 0x17;
+		lcd_depth = 8;
+		lcd_reg += 0x10000; /* add offset for 705 regs */
+		puts("LCD:   S1D13705");
+	} else {
+		puts("LCD:   No controller detected!\n");
+		return;
+	}
+
+	/*
+	 * Setup lcd controller regs
+	 */
+	for (i = 0; i<reg_count; i++) {
+		s1dReg = regs[i].Index;
+		if (reg_byte_swap) {
+			if ((s1dReg & 0x0001) == 0)
+				s1dReg |= 0x0001;
+			else
+				s1dReg &= ~0x0001;
+		}
+		s1dValue = regs[i].Value;
+		lcd_reg[s1dReg] = s1dValue;
+	}
+
+	/*
+	 * Save reg & mem pointer for later usage (e.g. bmp command)
+	 */
+	glob_lcd_reg = lcd_reg;
+	glob_lcd_mem = lcd_mem;
+
+	/*
+	 * Display bmp image
+	 */
+	lcd_bmp(logo_bmp);
+}
+
+#ifdef CONFIG_VIDEO_SM501
+int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+	char *str;
+
+	if (argc != 2) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+	str = getenv("bd_type");
+	if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
+		/*
+		 * SM501 available, use standard bmp command
+		 */
+		return (video_display_bitmap(addr, 0, 0));
+	} else {
+		/*
+		 * No SM501 available, use esd epson bmp command
+		 */
+		lcd_bmp((uchar *)addr);
+		return 0;
+	}
+}
+
+U_BOOT_CMD(
+	esdbmp,	2,	1,	do_esdbmp,
+	"esdbmp   - display BMP image\n",
+	"<imageAddr> - display image\n"
+);
+#endif
diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h
new file mode 100755
index 0000000..3169e6b
--- /dev/null
+++ b/board/esd/common/lcd.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Neutralize little endians.
+ */
+#define SWAP_LONG(data) ((unsigned long)                                  \
+		         (((unsigned long)(data) >> 24)                 | \
+			  ((unsigned long)(data)  << 24)                | \
+			  (((unsigned long)(data) >> 8) & 0x0000ff00 )  | \
+			   (((unsigned long)(data) << 8) & 0x00ff0000 )))
+#define SWAP_SHORT(data) ((unsigned short)                                \
+			  (((unsigned short)(data) >> 8 )  |              \
+			   ((unsigned short)(data) << 8 )))
+#define LOAD_LONG(data)   SWAP_LONG(data)
+#define LOAD_SHORT(data)  SWAP_SHORT(data)
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE (!FALSE)
+#endif
+
+#define S1D_WRITE_PALETTE(p,i,r,g,b)  \
+  {  \
+  ((volatile uchar*)(p))[palette_index] = (uchar)(i); \
+  ((volatile uchar*)(p))[palette_value] = (uchar)(r); \
+  ((volatile uchar*)(p))[palette_value] = (uchar)(g); \
+  ((volatile uchar*)(p))[palette_value] = (uchar)(b); \
+  }
+
+typedef struct
+{
+    ushort Index;
+    uchar  Value;
+} S1D_REGS;
+
+typedef struct                       /**** BMP file info structure ****/
+{
+	unsigned int   biSize;           /* Size of info header */
+	int            biWidth;          /* Width of image */
+	int            biHeight;         /* Height of image */
+	unsigned short biPlanes;         /* Number of color planes */
+	unsigned short biBitCount;       /* Number of bits per pixel */
+	unsigned int   biCompression;    /* Type of compression to use */
+	unsigned int   biSizeImage;      /* Size of image data */
+	int            biXPelsPerMeter;  /* X pixels per meter */
+	int            biYPelsPerMeter;  /* Y pixels per meter */
+	unsigned int   biClrUsed;        /* Number of colors used */
+	unsigned int   biClrImportant;   /* Number of important colors */
+} BITMAPINFOHEADER;
diff --git a/board/esd/common/misc.c b/board/esd/common/misc.c
new file mode 100755
index 0000000..48b4b7c
--- /dev/null
+++ b/board/esd/common/misc.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+#include <miiphy.h>
+#endif
+
+
+#ifdef CONFIG_LXT971_NO_SLEEP
+void lxt971_no_sleep(void)
+{
+	unsigned short reg;
+
+	miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, &reg);
+	reg &= ~0x0040;                  /* disable sleep mode */
+	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
+}
+#endif /* CONFIG_LXT971_NO_SLEEP */
diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c
new file mode 100755
index 0000000..f711205
--- /dev/null
+++ b/board/esd/common/pci.c
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+
+u_long pci9054_iobase;
+
+
+#define PCI_PRIMARY_CAR	(0x500000dc) /* PCI config address reg */
+#define PCI_PRIMARY_CDR	(0x80000000) /* PCI config data    reg */
+
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_read_config_dword
+|  Description: Read a PCI configuration register
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               value           Address of the configuration register value
+|  Return value:
+|               0               Successful
++-----------------------------------------------------------------------------*/
+int pci9054_read_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32* value)
+{
+  unsigned long      conAdrVal;
+  unsigned long      val;
+
+  /* generate coded value for CON_ADR register */
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  /* Note: *pResult comes back as -1 if machine check happened */
+  val = in32r(PCI_PRIMARY_CDR);
+
+  *value = (unsigned long) val;
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  if ((*(unsigned long *)0x50000304) & 0x60000000)
+    {
+      /* clear pci master/target abort bits */
+      *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+    }
+
+  return 0;
+}
+
+/*-----------------------------------------------------------------------------+
+|  Subroutine:  pci9054_write_config_dword
+|  Description: Write a PCI configuration register.
+|  Inputs:
+|               hose            PCI Controller
+|               dev             PCI Bus+Device+Function number
+|               offset          Configuration register number
+|               Value           Configuration register value
+|  Return value:
+|               0               Successful
+| Updated for pass2 errata #6. Need to disable interrupts and clear the
+| PCICFGADR reg after writing the PCICFGDATA reg.
++-----------------------------------------------------------------------------*/
+int pci9054_write_config_dword(struct pci_controller *hose,
+			       pci_dev_t dev, int offset, u32 value)
+{
+  unsigned long      conAdrVal;
+
+  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
+
+  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
+
+  out32r(PCI_PRIMARY_CDR, value);
+
+  out32r(PCI_PRIMARY_CAR, 0);
+
+  /* clear pci master/target abort bits */
+  *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
+
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_DASA_SIM
+static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
+					struct pci_config_table *_)
+{
+  unsigned int iobase;
+  unsigned short status = 0;
+  unsigned char timer;
+
+  /*
+   * Configure PLX PCI9054
+   */
+  pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status);
+  status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+  pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status);
+
+  /* Check the latency timer for values >= 0x60.
+   */
+  pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+  if (timer < 0x60)
+    {
+      pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+    }
+
+  /* Set I/O base register.
+   */
+  pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE);
+  pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+
+  pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+  if (pci9054_iobase == 0xffffffff)
+    {
+      printf("Error: Can not set I/O base register.\n");
+      return;
+    }
+}
+#endif
+
+static struct pci_config_table pci9054_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
+    pci_cfgfunc_config_device, { CFG_ETH_IOBASE,
+				 CFG_ETH_IOBASE,
+				 PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
+#ifdef CONFIG_DASA_SIM
+  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+    PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN),
+    pci_dasa_sim_config_pci9054 },
+#endif
+#endif
+  { }
+};
+
+static struct pci_controller pci9054_hose = {
+  config_table: pci9054_config_table,
+};
+
+void pci_init_board(void)
+{
+  struct pci_controller *hose = &pci9054_hose;
+
+  /*
+   * Register the hose
+   */
+  hose->first_busno = 0;
+  hose->last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(hose->regions + 0,
+		 0x00000000, 0x00000000, 0x01000000,
+		 PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+  /* PCI Memory space */
+  pci_set_region(hose->regions + 1,
+		 0x00000000, 0xc0000000, 0x10000000,
+		 PCI_REGION_MEM);
+
+  pci_set_ops(hose,
+	      pci_hose_read_config_byte_via_dword,
+	      pci_hose_read_config_word_via_dword,
+	      pci9054_read_config_dword,
+	      pci_hose_write_config_byte_via_dword,
+	      pci_hose_write_config_word_via_dword,
+	      pci9054_write_config_dword);
+
+  hose->region_count = 2;
+
+  pci_register_hose(hose);
+
+  hose->last_busno = pci_hose_scan(hose);
+}
diff --git a/board/esd/common/s1d13704_320_240_4bpp.h b/board/esd/common/s1d13704_320_240_4bpp.h
new file mode 100755
index 0000000..77c8a46
--- /dev/null
+++ b/board/esd/common/s1d13704_320_240_4bpp.h
@@ -0,0 +1,53 @@
+/*
+ *
+ *  Generic Header information generated by 13704CFG.EXE (Build 10)
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
+ *
+ *  This file defines the configuration environment and registers,
+ *  which can be used by any software, such as display drivers.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY
+ *               mode.
+ *
+ */
+
+static S1D_REGS regs_13704_320_240_4bpp[] =
+{
+	{ 0x00,             0x00 },       /* Revision Code Register */
+	{ 0x01,             0x04 }, /*00*/      /* Mode Register 0 Register */
+	{ 0x02,             0xA4 }, /*a0*/      /* Mode Register 1 Register */
+	{ 0x03,             0x83 }, /*03*/      /* Mode Register 2 Register - bit7 is LUT bypass */
+	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
+	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
+	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
+	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
+	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
+	{ 0x09,             0x00 },       /* FPFRAME Start Position Register */
+	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
+	{ 0x0B,             0x00 },       /* MOD Rate Register */
+	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
+	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
+	{ 0x0E,             0x00 },       /* Not Used */
+	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
+	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
+	{ 0x11,             0x00 },       /* Not Used */
+	{ 0x12,             0x00 },       /* Memory Address Offset Register */
+	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
+	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
+	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
+	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
+	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
+	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
+	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
+	{ 0x1A,             0x00 },       /* Scratch Pad Register */
+	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
+	{ 0x1C,             0xA0 },       /* Line Byte Count Register */
+	{ 0x1D,             0x00 },       /* Not Used */
+	{ 0x1E,             0x00 },       /* Not Used */
+	{ 0x1F,             0x00 },       /* Not Used */
+};
diff --git a/board/esd/common/s1d13705_320_240_8bpp.h b/board/esd/common/s1d13705_320_240_8bpp.h
new file mode 100755
index 0000000..60843ac
--- /dev/null
+++ b/board/esd/common/s1d13705_320_240_8bpp.h
@@ -0,0 +1,53 @@
+/*
+ *
+ *  Generic Header information generated by 13704CFG.EXE (Build 10)
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
+ *
+ *  This file defines the configuration environment and registers,
+ *  which can be used by any software, such as display drivers.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY
+ *               mode.
+ *
+ */
+
+static S1D_REGS regs_13705_320_240_8bpp[] =
+{
+	{ 0x00,             0x00 },       /* Revision Code Register */
+	{ 0x01,             0x23 },       /* Mode Register 0 Register */
+	{ 0x02,             0xE0 },       /* Mode Register 1 Register */
+	{ 0x03,             0x03 },       /* Mode Register 2 Register - bit7 is LUT bypass */
+	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
+	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
+	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
+	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
+	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
+	{ 0x09,             0x01 },       /* FPFRAME Start Position Register */
+	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
+	{ 0x0B,             0x00 },       /* MOD Rate Register */
+	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
+	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
+	{ 0x0E,             0x00 },       /* Not Used */
+	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
+	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
+	{ 0x11,             0x00 },       /* Not Used */
+	{ 0x12,             0x00 },       /* Memory Address Offset Register */
+	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
+	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
+	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
+	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
+	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
+	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
+	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
+	{ 0x1A,             0x00 },       /* Scratch Pad Register */
+	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
+	{ 0x1C,             0xFF },       /* Line Byte Count Register */
+	{ 0x1D,             0x00 },       /* Not Used */
+	{ 0x1E,             0x00 },       /* Not Used */
+	{ 0x1F,             0x00 },       /* Not Used */
+};
diff --git a/board/esd/common/s1d13806_1024_768_8bpp.h b/board/esd/common/s1d13806_1024_768_8bpp.h
new file mode 100755
index 0000000..68801bf
--- /dev/null
+++ b/board/esd/common/s1d13806_1024_768_8bpp.h
@@ -0,0 +1,125 @@
+/*
+ *
+ *  File generated by S1D13806CFG.EXE
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY mode.
+ *
+ * Panel:  (active)   1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
+ *
+ */
+
+static S1D_REGS regs_13806_1024_768_8bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x00},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x00},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x01},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x55},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x7F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x12},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xFF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x02},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x03},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x00},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x03},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/board/esd/common/s1d13806_320_240_4bpp.h b/board/esd/common/s1d13806_320_240_4bpp.h
new file mode 100755
index 0000000..24d7350
--- /dev/null
+++ b/board/esd/common/s1d13806_320_240_4bpp.h
@@ -0,0 +1,125 @@
+/*
+ *
+ *  File generated by S1D13806CFG.EXE
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY mode.
+ *
+ * Panel:  (active)   320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
+ *
+ */
+
+static S1D_REGS regs_13806_320_240_4bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x08},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x08},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x08},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x32},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x00},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x27},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x03},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xEF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x00},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x02},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x50},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x00},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x03},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/board/esd/common/s1d13806_640_480_16bpp.h b/board/esd/common/s1d13806_640_480_16bpp.h
new file mode 100755
index 0000000..178f1a9
--- /dev/null
+++ b/board/esd/common/s1d13806_640_480_16bpp.h
@@ -0,0 +1,125 @@
+/*
+ *
+ *  File generated by S1D13806CFG.EXE
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY mode.
+ *
+ * Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
+ *
+ */
+
+static S1D_REGS regs_13806_640_480_16bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x18},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x18},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x25},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x00},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x24},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x05},   /* LCD Display Mode Register */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x05},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/board/esd/common/s1d13806_640_480_8bpp.h b/board/esd/common/s1d13806_640_480_8bpp.h
new file mode 100755
index 0000000..c1f5b2b
--- /dev/null
+++ b/board/esd/common/s1d13806_640_480_8bpp.h
@@ -0,0 +1,125 @@
+/*
+ *
+ *  File generated by S1D13806CFG.EXE
+ *
+ *  Copyright (c) 2000,2001 Epson Research and Development, Inc.
+ *  All rights reserved.
+ *
+ *  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
+ *               sure you transfer this file using ASCII, not BINARY mode.
+ *
+ * Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
+ * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
+ *
+ */
+
+static S1D_REGS regs_13806_640_320_16bpp[] =
+{
+	{0x0001,0x00},   /* Miscellaneous Register */
+	{0x01FC,0x00},   /* Display Mode Register */
+	{0x0004,0x18},   /* General IO Pins Configuration Register 0 */
+	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+	{0x0008,0x18},   /* General IO Pins Control Register 0 */
+	{0x0009,0x00},   /* General IO Pins Control Register 1 */
+	{0x0010,0x00},   /* Memory Clock Configuration Register */
+	{0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
+	{0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+	{0x0021,0x03},   /* DRAM Refresh Rate Register */
+	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
+	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
+	{0x0020,0x80},   /* Memory Configuration Register */
+	{0x0030,0x25},   /* Panel Type Register */
+	{0x0031,0x00},   /* MOD Rate Register */
+	{0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+	{0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+	{0x0035,0x00},   /* TFT FPLINE Start Position Register */
+	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+	{0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+	{0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+	{0x003A,0x24},   /* LCD Vertical Non-Display Period Register */
+	{0x003B,0x00},   /* TFT FPFRAME Start Position Register */
+	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+	{0x0040,0x03},   /* LCD Display Mode Register (8bpp) */
+	{0x0041,0x00},   /* LCD Miscellaneous Register */
+	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
+	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
+	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
+	{0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+	{0x0048,0x00},   /* LCD Pixel Panning Register */
+	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+	{0x005B,0x10},   /* TV Output Control Register */
+	{0x0060,0x05},   /* CRT/TV Display Mode Register */
+	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+	{0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+	{0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+	{0x0100,0x00},   /* BitBlt Control Register 0 */
+	{0x0101,0x00},   /* BitBlt Control Register 1 */
+	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+	{0x0103,0x00},   /* BitBlt Operation Register */
+	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+	{0x0110,0x00},   /* BitBlt Width Register 0 */
+	{0x0111,0x00},   /* BitBlt Width Register 1 */
+	{0x0112,0x00},   /* BitBlt Height Register 0 */
+	{0x0113,0x00},   /* BitBlt Height Register 1 */
+	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
+	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
+	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+	{0x01E0,0x00},   /* Look-Up Table Mode Register */
+	{0x01E2,0x00},   /* Look-Up Table Address Register */
+	{0x01F0,0x10},   /* Power Save Configuration Register */
+	{0x01F1,0x00},   /* Power Save Status Register */
+	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+	{0x01FC,0x01},   /* Display Mode Register */
+};
diff --git a/board/esd/common/xilinx_jtag/lenval.c b/board/esd/common/xilinx_jtag/lenval.c
new file mode 100755
index 0000000..7316266
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/lenval.c
@@ -0,0 +1,217 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: lenval.c                                      */
+/* abstract:  This file contains routines for using    */
+/*            the lenVal data structure.               */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include "lenval.h"
+#include "ports.h"
+
+
+/*****************************************************************************
+ * Function:     value
+ * Description:  Extract the long value from the lenval array.
+ * Parameters:   plvValue    - ptr to lenval.
+ * Returns:      long        - the extracted value.
+ *****************************************************************************/
+long value( lenVal*     plvValue )
+{
+	long    lValue;         /* result to hold the accumulated result */
+	short   sIndex;
+
+	lValue  = 0;
+	for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex )
+	{
+		lValue <<= 8;                       /* shift the accumulated result */
+		lValue |= plvValue->val[ sIndex];   /* get the last byte first */
+	}
+
+	return( lValue );
+}
+
+/*****************************************************************************
+ * Function:     initLenVal
+ * Description:  Initialize the lenval array with the given value.
+ *               Assumes lValue is less than 256.
+ * Parameters:   plv         - ptr to lenval.
+ *               lValue      - the value to set.
+ * Returns:      void.
+ *****************************************************************************/
+void initLenVal( lenVal*    plv,
+		 long       lValue )
+{
+	plv->len    = 1;
+	plv->val[0] = (unsigned char)lValue;
+}
+
+/*****************************************************************************
+ * Function:     EqualLenVal
+ * Description:  Compare two lenval arrays with an optional mask.
+ * Parameters:   plvTdoExpected  - ptr to lenval #1.
+ *               plvTdoCaptured  - ptr to lenval #2.
+ *               plvTdoMask      - optional ptr to mask (=0 if no mask).
+ * Returns:      short   - 0 = mismatch; 1 = equal.
+ *****************************************************************************/
+short EqualLenVal( lenVal*  plvTdoExpected,
+		   lenVal*  plvTdoCaptured,
+		   lenVal*  plvTdoMask )
+{
+	short           sEqual;
+	short           sIndex;
+	unsigned char   ucByteVal1;
+	unsigned char   ucByteVal2;
+	unsigned char   ucByteMask;
+
+	sEqual  = 1;
+	sIndex  = plvTdoExpected->len;
+
+	while ( sEqual && sIndex-- )
+	{
+		ucByteVal1  = plvTdoExpected->val[ sIndex ];
+		ucByteVal2  = plvTdoCaptured->val[ sIndex ];
+		if ( plvTdoMask )
+		{
+			ucByteMask  = plvTdoMask->val[ sIndex ];
+			ucByteVal1  &= ucByteMask;
+			ucByteVal2  &= ucByteMask;
+		}
+		if ( ucByteVal1 != ucByteVal2 )
+		{
+			sEqual  = 0;
+		}
+	}
+
+	return( sEqual );
+}
+
+
+/*****************************************************************************
+ * Function:     RetBit
+ * Description:  return the (byte, bit) of lv (reading from left to right).
+ * Parameters:   plv     - ptr to lenval.
+ *               iByte   - the byte to get the bit from.
+ *               iBit    - the bit number (0=msb)
+ * Returns:      short   - the bit value.
+ *****************************************************************************/
+short RetBit( lenVal*   plv,
+	      int       iByte,
+	      int       iBit )
+{
+	/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
+	/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
+	return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) );
+}
+
+/*****************************************************************************
+ * Function:     SetBit
+ * Description:  set the (byte, bit) of lv equal to val
+ * Example:      SetBit("00000000",byte, 1) equals "01000000".
+ * Parameters:   plv     - ptr to lenval.
+ *               iByte   - the byte to get the bit from.
+ *               iBit    - the bit number (0=msb).
+ *               sVal    - the bit value to set.
+ * Returns:      void.
+ *****************************************************************************/
+void SetBit( lenVal*    plv,
+	     int        iByte,
+	     int        iBit,
+	     short      sVal )
+{
+	unsigned char   ucByteVal;
+	unsigned char   ucBitMask;
+
+	ucBitMask   = (unsigned char)(1 << ( 7 - iBit ));
+	ucByteVal   = (unsigned char)(plv->val[ iByte ] & (~ucBitMask));
+
+	if ( sVal )
+	{
+		ucByteVal   |= ucBitMask;
+	}
+	plv->val[ iByte ]   = ucByteVal;
+}
+
+/*****************************************************************************
+ * Function:     AddVal
+ * Description:  add val1 to val2 and store in resVal;
+ *               assumes val1 and val2  are of equal length.
+ * Parameters:   plvResVal   - ptr to result.
+ *               plvVal1     - ptr of addendum.
+ *               plvVal2     - ptr of addendum.
+ * Returns:      void.
+ *****************************************************************************/
+void addVal( lenVal*    plvResVal,
+	     lenVal*    plvVal1,
+	     lenVal*    plvVal2 )
+{
+	unsigned char   ucCarry;
+	unsigned short  usSum;
+	unsigned short  usVal1;
+	unsigned short  usVal2;
+	short           sIndex;
+
+	plvResVal->len  = plvVal1->len;         /* set up length of result */
+
+	/* start at least significant bit and add bytes    */
+	ucCarry = 0;
+	sIndex  = plvVal1->len;
+	while ( sIndex-- )
+	{
+		usVal1  = plvVal1->val[ sIndex ];   /* i'th byte of val1 */
+		usVal2  = plvVal2->val[ sIndex ];   /* i'th byte of val2 */
+
+		/* add the two bytes plus carry from previous addition */
+		usSum   = (unsigned short)( usVal1 + usVal2 + ucCarry );
+
+		/* set up carry for next byte */
+		ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 );
+
+		/* set the i'th byte of the result */
+		plvResVal->val[ sIndex ]    = (unsigned char)usSum;
+	}
+}
+
+/*****************************************************************************
+ * Function:     readVal
+ * Description:  read from XSVF numBytes bytes of data into x.
+ * Parameters:   plv         - ptr to lenval in which to put the bytes read.
+ *               sNumBytes   - the number of bytes to read.
+ * Returns:      void.
+ *****************************************************************************/
+void readVal( lenVal*   plv,
+	      short     sNumBytes )
+{
+	unsigned char*  pucVal;
+
+	plv->len    = sNumBytes;        /* set the length of the lenVal        */
+	for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal )
+	{
+		/* read a byte of data into the lenVal */
+		readByte( pucVal );
+	}
+}
diff --git a/board/esd/common/xilinx_jtag/lenval.h b/board/esd/common/xilinx_jtag/lenval.h
new file mode 100755
index 0000000..6bec4ea
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/lenval.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: lenval.h                                      */
+/* abstract:  This file contains a description of the  */
+/*            data structure "lenval".                 */
+/*******************************************************/
+
+#ifndef lenval_dot_h
+#define lenval_dot_h
+
+/* the lenVal structure is a byte oriented type used to store an */
+/* arbitrary length binary value. As an example, the hex value   */
+/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes   */
+/* and val[0]=0e and val[1]=3d.  val[2-MAX_LEN] are undefined    */
+
+/* maximum length (in bytes) of value to read in        */
+/* this needs to be at least 4, and longer than the     */
+/* length of the longest SDR instruction.  If there is, */
+/* only 1 device in the chain, MAX_LEN must be at least */
+/* ceil(27/8) == 4.  For 6 devices in a chain, MAX_LEN  */
+/* must be 5, for 14 devices MAX_LEN must be 6, for 20  */
+/* devices MAX_LEN must be 7, etc..                     */
+/* You can safely set MAX_LEN to a smaller number if you*/
+/* know how many devices will be in your chain.         */
+#define MAX_LEN 7000
+
+
+typedef struct var_len_byte
+{
+	short len;   /* number of chars in this value */
+	unsigned char val[MAX_LEN+1];  /* bytes of data */
+} lenVal;
+
+
+/* return the long representation of a lenVal */
+extern long value(lenVal *x);
+
+/* set lenVal equal to value */
+extern void initLenVal(lenVal *x, long value);
+
+/* check if expected equals actual (taking the mask into account) */
+extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask);
+
+/* add val1+val2 and put the result in resVal */
+extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2);
+
+/* return the (byte, bit) of lv (reading from left to right) */
+extern short RetBit(lenVal *lv, int byte, int bit);
+
+/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1)
+   equals "01000000" */
+extern void SetBit(lenVal *lv, int byte, int bit, short val);
+
+/* read from XSVF numBytes bytes of data into x */
+extern void  readVal(lenVal *x, short numBytes);
+
+#endif
diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c
new file mode 100755
index 0000000..318f229
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/micro.c
@@ -0,0 +1,1864 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*****************************************************************************
+ * file:         micro.c
+ * abstract:     This file contains the function, xsvfExecute(),
+ *               call for interpreting the XSVF commands.
+ * Usage:        Call xsvfExecute() to process XSVF data.
+ *               The XSVF data is retrieved by readByte() in ports.c
+ *               Remove the main function if you already have one.
+ * Options:      XSVF_SUPPORT_COMPRESSION
+ *                   This define supports the XC9500/XL compression scheme.
+ *                   This define adds support for XSDRINC and XSETSDRMASKS.
+ *               XSVF_SUPPORT_ERRORCODES
+ *                   This define causes the xsvfExecute function to return
+ *                   an error code for specific errors.  See error codes below.
+ *                   If this is not defined, the return value defaults to the
+ *                   legacy values for backward compatibility:
+ *                   1 = success;  0 = failure.
+ * Debugging:    DEBUG_MODE (Legacy name)
+ *               Define DEBUG_MODE to compile with debugging features.
+ *               Both micro.c and ports.c must be compiled with the DEBUG_MODE
+ *               defined to enable the standalone main implementation in
+ *               micro.c that reads XSVF from a file.
+ * History:      v2.00   - Original XSVF implementation.
+ *               v4.04   - Added delay at end of XSIR for XC18v00 support.
+ *                         Added new commands for CoolRunner support:
+ *                         XSTATE, XENDIR, XENDDR
+ *               v4.05   - Cleanup micro.c but leave ports.c intact.
+ *               v4.06   - Fix xsvfGotoTapState for retry transition.
+ *               v4.07   - Update example waitTime implementations for
+ *                         compatibility with Virtex-II.
+ *               v4.10   - Add new XSIR2 command that supports a 2-byte
+ *                         IR-length parameter for IR shifts > 255 bits.
+ *               v4.11   - No change.  Update version to match SVF2XSVF xlator.
+ *               v4.14   - Added XCOMMENT.
+ *               v5.00   - Improve XSTATE support.
+ *                         Added XWAIT.
+ *****************************************************************************/
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#include "micro.h"
+#include "lenval.h"
+#include "ports.h"
+
+
+extern const unsigned char fpgadata[];
+extern int filesize;
+
+
+/*============================================================================
+ * XSVF #define
+ ============================================================================*/
+
+#define XSVF_VERSION    "5.00"
+
+/*****************************************************************************
+ * Define:       XSVF_SUPPORT_COMPRESSION
+ * Description:  Define this to support the XC9500/XL XSVF data compression
+ *               scheme.
+ *               Code size can be reduced by NOT supporting this feature.
+ *               However, you must use the -nc (no compress) option when
+ *               translating SVF to XSVF using the SVF2XSVF translator.
+ *               Corresponding, uncompressed XSVF may be larger.
+ *****************************************************************************/
+#ifndef XSVF_SUPPORT_COMPRESSION
+#define XSVF_SUPPORT_COMPRESSION    1
+#endif
+
+/*****************************************************************************
+ * Define:       XSVF_SUPPORT_ERRORCODES
+ * Description:  Define this to support the new XSVF error codes.
+ *               (The original XSVF player just returned 1 for success and
+ *               0 for an unspecified failure.)
+ *****************************************************************************/
+#ifndef XSVF_SUPPORT_ERRORCODES
+#define XSVF_SUPPORT_ERRORCODES     1
+#endif
+
+#ifdef  XSVF_SUPPORT_ERRORCODES
+#define XSVF_ERRORCODE(errorCode)   errorCode
+#else   /* Use legacy error code */
+#define XSVF_ERRORCODE(errorCode)   ((errorCode==XSVF_ERROR_NONE)?1:0)
+#endif  /* XSVF_SUPPORT_ERRORCODES */
+
+
+/*============================================================================
+ * DEBUG_MODE #define
+ ============================================================================*/
+#define DEBUG_MODE
+
+#ifdef  DEBUG_MODE
+#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat ); }
+#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1 ); }
+#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2 ); }
+#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2, arg3 ); }
+#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    xsvfPrintLenVal(plenVal); }
+#else   /* !DEBUG_MODE */
+#define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
+#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
+#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2)
+#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3)
+#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal)
+#endif  /* DEBUG_MODE */
+
+
+/*============================================================================
+ * XSVF Type Declarations
+ ============================================================================*/
+
+/*****************************************************************************
+ * Struct:       SXsvfInfo
+ * Description:  This structure contains all of the data used during the
+ *               execution of the XSVF.  Some data is persistent, predefined
+ *               information (e.g. lRunTestTime).  The bulk of this struct's
+ *               size is due to the lenVal structs (defined in lenval.h)
+ *               which contain buffers for the active shift data.  The MAX_LEN
+ *               #define in lenval.h defines the size of these buffers.
+ *               These buffers must be large enough to store the longest
+ *               shift data in your XSVF file.  For example:
+ *                   MAX_LEN >= ( longest_shift_data_in_bits / 8 )
+ *               Because the lenVal struct dominates the space usage of this
+ *               struct, the rough size of this struct is:
+ *                   sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals)
+ *               xsvfInitialize() contains initialization code for the data
+ *               in this struct.
+ *               xsvfCleanup() contains cleanup code for the data in this
+ *               struct.
+ *****************************************************************************/
+typedef struct tagSXsvfInfo
+{
+	/* XSVF status information */
+	unsigned char   ucComplete;         /* 0 = running; 1 = complete */
+	unsigned char   ucCommand;          /* Current XSVF command byte */
+	long            lCommandCount;      /* Number of commands processed */
+	int             iErrorCode;         /* An error code. 0 = no error. */
+
+	/* TAP state/sequencing information */
+	unsigned char   ucTapState;         /* Current TAP state */
+	unsigned char   ucEndIR;            /* ENDIR TAP state (See SVF) */
+	unsigned char   ucEndDR;            /* ENDDR TAP state (See SVF) */
+
+	/* RUNTEST information */
+	unsigned char   ucMaxRepeat;        /* Max repeat loops (for xc9500/xl) */
+	long            lRunTestTime;       /* Pre-specified RUNTEST time (usec) */
+
+	/* Shift Data Info and Buffers */
+	long            lShiftLengthBits;   /* Len. current shift data in bits */
+	short           sShiftLengthBytes;  /* Len. current shift data in bytes */
+
+	lenVal          lvTdi;              /* Current TDI shift data */
+	lenVal          lvTdoExpected;      /* Expected TDO shift data */
+	lenVal          lvTdoCaptured;      /* Captured TDO shift data */
+	lenVal          lvTdoMask;          /* TDO mask: 0=dontcare; 1=compare */
+
+#ifdef  XSVF_SUPPORT_COMPRESSION
+	/* XSDRINC Data Buffers */
+	lenVal          lvAddressMask;      /* Address mask for XSDRINC */
+	lenVal          lvDataMask;         /* Data mask for XSDRINC */
+	lenVal          lvNextData;         /* Next data for XSDRINC */
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+} SXsvfInfo;
+
+/* Declare pointer to functions that perform XSVF commands */
+typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* );
+
+/*============================================================================
+ * XSVF Command Bytes
+ ============================================================================*/
+
+/* encodings of xsvf instructions */
+#define XCOMPLETE        0
+#define XTDOMASK         1
+#define XSIR             2
+#define XSDR             3
+#define XRUNTEST         4
+/* Reserved              5 */
+/* Reserved              6 */
+#define XREPEAT          7
+#define XSDRSIZE         8
+#define XSDRTDO          9
+#define XSETSDRMASKS     10
+#define XSDRINC          11
+#define XSDRB            12
+#define XSDRC            13
+#define XSDRE            14
+#define XSDRTDOB         15
+#define XSDRTDOC         16
+#define XSDRTDOE         17
+#define XSTATE           18         /* 4.00 */
+#define XENDIR           19         /* 4.04 */
+#define XENDDR           20         /* 4.04 */
+#define XSIR2            21         /* 4.10 */
+#define XCOMMENT         22         /* 4.14 */
+#define XWAIT            23         /* 5.00 */
+/* Insert new commands here */
+/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */
+#define XLASTCMD         24         /* Last command marker */
+
+
+/*============================================================================
+ * XSVF Command Parameter Values
+ ============================================================================*/
+
+#define XSTATE_RESET     0          /* 4.00 parameter for XSTATE */
+#define XSTATE_RUNTEST   1          /* 4.00 parameter for XSTATE */
+
+#define XENDXR_RUNTEST   0          /* 4.04 parameter for XENDIR/DR */
+#define XENDXR_PAUSE     1          /* 4.04 parameter for XENDIR/DR */
+
+/* TAP states */
+#define XTAPSTATE_RESET     0x00
+#define XTAPSTATE_RUNTEST   0x01    /* a.k.a. IDLE */
+#define XTAPSTATE_SELECTDR  0x02
+#define XTAPSTATE_CAPTUREDR 0x03
+#define XTAPSTATE_SHIFTDR   0x04
+#define XTAPSTATE_EXIT1DR   0x05
+#define XTAPSTATE_PAUSEDR   0x06
+#define XTAPSTATE_EXIT2DR   0x07
+#define XTAPSTATE_UPDATEDR  0x08
+#define XTAPSTATE_IRSTATES  0x09    /* All IR states begin here */
+#define XTAPSTATE_SELECTIR  0x09
+#define XTAPSTATE_CAPTUREIR 0x0A
+#define XTAPSTATE_SHIFTIR   0x0B
+#define XTAPSTATE_EXIT1IR   0x0C
+#define XTAPSTATE_PAUSEIR   0x0D
+#define XTAPSTATE_EXIT2IR   0x0E
+#define XTAPSTATE_UPDATEIR  0x0F
+
+/*============================================================================
+ * XSVF Function Prototypes
+ ============================================================================*/
+
+int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo );   /* Illegal command function */
+int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSIR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo );
+int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo );
+int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo );
+int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo );
+int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo );
+/* Insert new command functions here */
+
+/*============================================================================
+ * XSVF Global Variables
+ ============================================================================*/
+
+/* Array of XSVF command functions.  Must follow command byte value order! */
+/* If your compiler cannot take this form, then convert to a switch statement*/
+TXsvfDoCmdFuncPtr   xsvf_pfDoCmd[]  =
+{
+	xsvfDoXCOMPLETE,        /*  0 */
+	xsvfDoXTDOMASK,         /*  1 */
+	xsvfDoXSIR,             /*  2 */
+	xsvfDoXSDR,             /*  3 */
+	xsvfDoXRUNTEST,         /*  4 */
+	xsvfDoIllegalCmd,       /*  5 */
+	xsvfDoIllegalCmd,       /*  6 */
+	xsvfDoXREPEAT,          /*  7 */
+	xsvfDoXSDRSIZE,         /*  8 */
+	xsvfDoXSDRTDO,          /*  9 */
+#ifdef  XSVF_SUPPORT_COMPRESSION
+	xsvfDoXSETSDRMASKS,     /* 10 */
+	xsvfDoXSDRINC,          /* 11 */
+#else
+	xsvfDoIllegalCmd,       /* 10 */
+	xsvfDoIllegalCmd,       /* 11 */
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+	xsvfDoXSDRBCE,          /* 12 */
+	xsvfDoXSDRBCE,          /* 13 */
+	xsvfDoXSDRBCE,          /* 14 */
+	xsvfDoXSDRTDOBCE,       /* 15 */
+	xsvfDoXSDRTDOBCE,       /* 16 */
+	xsvfDoXSDRTDOBCE,       /* 17 */
+	xsvfDoXSTATE,           /* 18 */
+	xsvfDoXENDXR,           /* 19 */
+	xsvfDoXENDXR,           /* 20 */
+	xsvfDoXSIR2,            /* 21 */
+	xsvfDoXCOMMENT,         /* 22 */
+	xsvfDoXWAIT             /* 23 */
+/* Insert new command functions here */
+};
+
+#ifdef  DEBUG_MODE
+char* xsvf_pzCommandName[]  =
+{
+	"XCOMPLETE",
+	"XTDOMASK",
+	"XSIR",
+	"XSDR",
+	"XRUNTEST",
+	"Reserved5",
+	"Reserved6",
+	"XREPEAT",
+	"XSDRSIZE",
+	"XSDRTDO",
+	"XSETSDRMASKS",
+	"XSDRINC",
+	"XSDRB",
+	"XSDRC",
+	"XSDRE",
+	"XSDRTDOB",
+	"XSDRTDOC",
+	"XSDRTDOE",
+	"XSTATE",
+	"XENDIR",
+	"XENDDR",
+	"XSIR2",
+	"XCOMMENT",
+	"XWAIT"
+};
+
+char*   xsvf_pzErrorName[]  =
+{
+	"No error",
+	"ERROR:  Unknown",
+	"ERROR:  TDO mismatch",
+	"ERROR:  TDO mismatch and exceeded max retries",
+	"ERROR:  Unsupported XSVF command",
+	"ERROR:  Illegal state specification",
+	"ERROR:  Data overflows allocated MAX_LEN buffer size"
+};
+
+char*   xsvf_pzTapState[] =
+{
+	"RESET",        /* 0x00 */
+	"RUNTEST/IDLE", /* 0x01 */
+	"DRSELECT",     /* 0x02 */
+	"DRCAPTURE",    /* 0x03 */
+	"DRSHIFT",      /* 0x04 */
+	"DREXIT1",      /* 0x05 */
+	"DRPAUSE",      /* 0x06 */
+	"DREXIT2",      /* 0x07 */
+	"DRUPDATE",     /* 0x08 */
+	"IRSELECT",     /* 0x09 */
+	"IRCAPTURE",    /* 0x0A */
+	"IRSHIFT",      /* 0x0B */
+	"IREXIT1",      /* 0x0C */
+	"IRPAUSE",      /* 0x0D */
+	"IREXIT2",      /* 0x0E */
+	"IRUPDATE"      /* 0x0F */
+};
+#endif  /* DEBUG_MODE */
+
+/*#ifdef DEBUG_MODE	*/
+/*    FILE* in;   /XXX* Legacy DEBUG_MODE file pointer */
+int xsvf_iDebugLevel;
+/*#endif /XXX* DEBUG_MODE */
+
+/*============================================================================
+ * Utility Functions
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfPrintLenVal
+ * Description:  Print the lenval value in hex.
+ * Parameters:   plv     - ptr to lenval.
+ * Returns:      void.
+ *****************************************************************************/
+#ifdef  DEBUG_MODE
+void xsvfPrintLenVal( lenVal *plv )
+{
+	int i;
+
+	if ( plv )
+	{
+		printf( "0x" );
+		for ( i = 0; i < plv->len; ++i )
+		{
+			printf( "%02x", ((unsigned int)(plv->val[ i ])) );
+		}
+	}
+}
+#endif  /* DEBUG_MODE */
+
+
+/*****************************************************************************
+ * Function:     xsvfInfoInit
+ * Description:  Initialize the xsvfInfo data.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF info structure.
+ * Returns:      int         - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfInfoInit( SXsvfInfo* pXsvfInfo )
+{
+	XSVFDBG_PRINTF1( 4, "    sizeof( SXsvfInfo ) = %d bytes\n",
+			 sizeof( SXsvfInfo ) );
+
+	pXsvfInfo->ucComplete       = 0;
+	pXsvfInfo->ucCommand        = XCOMPLETE;
+	pXsvfInfo->lCommandCount    = 0;
+	pXsvfInfo->iErrorCode       = XSVF_ERROR_NONE;
+	pXsvfInfo->ucMaxRepeat      = 0;
+	pXsvfInfo->ucTapState       = XTAPSTATE_RESET;
+	pXsvfInfo->ucEndIR          = XTAPSTATE_RUNTEST;
+	pXsvfInfo->ucEndDR          = XTAPSTATE_RUNTEST;
+	pXsvfInfo->lShiftLengthBits = 0L;
+	pXsvfInfo->sShiftLengthBytes= 0;
+	pXsvfInfo->lRunTestTime     = 0L;
+
+	return( 0 );
+}
+
+/*****************************************************************************
+ * Function:     xsvfInfoCleanup
+ * Description:  Cleanup the xsvfInfo data.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF info structure.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo )
+{
+}
+
+/*****************************************************************************
+ * Function:     xsvfGetAsNumBytes
+ * Description:  Calculate the number of bytes the given number of bits
+ *               consumes.
+ * Parameters:   lNumBits    - the number of bits.
+ * Returns:      short       - the number of bytes to store the number of bits.
+ *****************************************************************************/
+short xsvfGetAsNumBytes( long lNumBits )
+{
+	return( (short)( ( lNumBits + 7L ) / 8L ) );
+}
+
+/*****************************************************************************
+ * Function:     xsvfTmsTransition
+ * Description:  Apply TMS and transition TAP controller by applying one TCK
+ *               cycle.
+ * Parameters:   sTms    - new TMS value.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfTmsTransition( short sTms )
+{
+	setPort( TMS, sTms );
+	setPort( TCK, 0 );
+	setPort( TCK, 1 );
+}
+
+/*****************************************************************************
+ * Function:     xsvfGotoTapState
+ * Description:  From the current TAP state, go to the named TAP state.
+ *               A target state of RESET ALWAYS causes TMS reset sequence.
+ *               All SVF standard stable state paths are supported.
+ *               All state transitions are supported except for the following
+ *               which cause an XSVF_ERROR_ILLEGALSTATE:
+ *                   - Target==DREXIT2;  Start!=DRPAUSE
+ *                   - Target==IREXIT2;  Start!=IRPAUSE
+ * Parameters:   pucTapState     - Current TAP state; returns final TAP state.
+ *               ucTargetState   - New target TAP state.
+ * Returns:      int             - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfGotoTapState( unsigned char*   pucTapState,
+		      unsigned char    ucTargetState )
+{
+	int i;
+	int iErrorCode;
+
+	iErrorCode  = XSVF_ERROR_NONE;
+	if ( ucTargetState == XTAPSTATE_RESET )
+	{
+		/* If RESET, always perform TMS reset sequence to reset/sync TAPs */
+		xsvfTmsTransition( 1 );
+		for ( i = 0; i < 5; ++i )
+		{
+			setPort( TCK, 0 );
+			setPort( TCK, 1 );
+		}
+		*pucTapState    = XTAPSTATE_RESET;
+		XSVFDBG_PRINTF( 3, "   TMS Reset Sequence -> Test-Logic-Reset\n" );
+		XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+				 xsvf_pzTapState[ *pucTapState ] );
+	} else if ( ( ucTargetState != *pucTapState ) &&
+		  ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) ||
+		    ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) )
+	{
+		/* Trap illegal TAP state path specification */
+		iErrorCode      = XSVF_ERROR_ILLEGALSTATE;
+	} else {
+		if ( ucTargetState == *pucTapState )
+		{
+			/* Already in target state.  Do nothing except when in DRPAUSE
+			   or in IRPAUSE to comply with SVF standard */
+			if ( ucTargetState == XTAPSTATE_PAUSEDR )
+			{
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2DR;
+				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+						 xsvf_pzTapState[ *pucTapState ] );
+			}
+			else if ( ucTargetState == XTAPSTATE_PAUSEIR )
+			{
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2IR;
+				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+						 xsvf_pzTapState[ *pucTapState ] );
+			}
+		}
+
+		/* Perform TAP state transitions to get to the target state */
+		while ( ucTargetState != *pucTapState )
+		{
+			switch ( *pucTapState )
+			{
+			case XTAPSTATE_RESET:
+				xsvfTmsTransition( 0 );
+				*pucTapState    = XTAPSTATE_RUNTEST;
+				break;
+			case XTAPSTATE_RUNTEST:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_SELECTDR;
+				break;
+			case XTAPSTATE_SELECTDR:
+				if ( ucTargetState >= XTAPSTATE_IRSTATES )
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_SELECTIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_CAPTUREDR;
+				}
+				break;
+			case XTAPSTATE_CAPTUREDR:
+				if ( ucTargetState == XTAPSTATE_SHIFTDR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTDR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_EXIT1DR;
+				}
+				break;
+			case XTAPSTATE_SHIFTDR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT1DR;
+				break;
+			case XTAPSTATE_EXIT1DR:
+				if ( ucTargetState == XTAPSTATE_PAUSEDR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_PAUSEDR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEDR;
+				}
+				break;
+			case XTAPSTATE_PAUSEDR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2DR;
+				break;
+			case XTAPSTATE_EXIT2DR:
+				if ( ucTargetState == XTAPSTATE_SHIFTDR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTDR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEDR;
+				}
+				break;
+			case XTAPSTATE_UPDATEDR:
+				if ( ucTargetState == XTAPSTATE_RUNTEST )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_RUNTEST;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_SELECTDR;
+				}
+				break;
+			case XTAPSTATE_SELECTIR:
+				xsvfTmsTransition( 0 );
+				*pucTapState    = XTAPSTATE_CAPTUREIR;
+				break;
+			case XTAPSTATE_CAPTUREIR:
+				if ( ucTargetState == XTAPSTATE_SHIFTIR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_EXIT1IR;
+				}
+				break;
+			case XTAPSTATE_SHIFTIR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT1IR;
+				break;
+			case XTAPSTATE_EXIT1IR:
+				if ( ucTargetState == XTAPSTATE_PAUSEIR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_PAUSEIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEIR;
+				}
+				break;
+			case XTAPSTATE_PAUSEIR:
+				xsvfTmsTransition( 1 );
+				*pucTapState    = XTAPSTATE_EXIT2IR;
+				break;
+			case XTAPSTATE_EXIT2IR:
+				if ( ucTargetState == XTAPSTATE_SHIFTIR )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_SHIFTIR;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_UPDATEIR;
+				}
+				break;
+			case XTAPSTATE_UPDATEIR:
+				if ( ucTargetState == XTAPSTATE_RUNTEST )
+				{
+					xsvfTmsTransition( 0 );
+					*pucTapState    = XTAPSTATE_RUNTEST;
+				}
+				else
+				{
+					xsvfTmsTransition( 1 );
+					*pucTapState    = XTAPSTATE_SELECTDR;
+				}
+				break;
+			default:
+				iErrorCode      = XSVF_ERROR_ILLEGALSTATE;
+				*pucTapState    = ucTargetState;    /* Exit while loop */
+				break;
+			}
+			XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+					 xsvf_pzTapState[ *pucTapState ] );
+		}
+	}
+
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfShiftOnly
+ * Description:  Assumes that starting TAP state is SHIFT-DR or SHIFT-IR.
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Optionally, save the TDO data shifted out of the scan chain.
+ *               Last shift cycle is special:  capture last TDO, set last TDI,
+ *               but does not pulse TCK.  Caller must pulse TCK and optionally
+ *               set TMS=1 to exit shift state.
+ * Parameters:   lNumBits        - number of bits to shift.
+ *               plvTdi          - ptr to lenval for TDI data.
+ *               plvTdoCaptured  - ptr to lenval for storing captured TDO data.
+ *               iExitShift      - 1=exit at end of shift; 0=stay in Shift-DR.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfShiftOnly( long    lNumBits,
+		    lenVal* plvTdi,
+		    lenVal* plvTdoCaptured,
+		    int     iExitShift )
+{
+	unsigned char*  pucTdi;
+	unsigned char*  pucTdo;
+	unsigned char   ucTdiByte;
+	unsigned char   ucTdoByte;
+	unsigned char   ucTdoBit;
+	int             i;
+
+	/* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */
+
+	/* Initialize TDO storage len == TDI len */
+	pucTdo  = 0;
+	if ( plvTdoCaptured )
+	{
+		plvTdoCaptured->len = plvTdi->len;
+		pucTdo              = plvTdoCaptured->val + plvTdi->len;
+	}
+
+	/* Shift LSB first.  val[N-1] == LSB.  val[0] == MSB. */
+	pucTdi  = plvTdi->val + plvTdi->len;
+	while ( lNumBits )
+	{
+		/* Process on a byte-basis */
+		ucTdiByte   = (*(--pucTdi));
+		ucTdoByte   = 0;
+		for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i )
+		{
+			--lNumBits;
+			if ( iExitShift && !lNumBits )
+			{
+				/* Exit Shift-DR state */
+				setPort( TMS, 1 );
+			}
+
+			/* Set the new TDI value */
+			setPort( TDI, (short)(ucTdiByte & 1) );
+			ucTdiByte   >>= 1;
+
+			/* Set TCK low */
+			setPort( TCK, 0 );
+
+			if ( pucTdo )
+			{
+				/* Save the TDO value */
+				ucTdoBit    = readTDOBit();
+				ucTdoByte   |= ( ucTdoBit << i );
+			}
+
+			/* Set TCK high */
+			setPort( TCK, 1 );
+		}
+
+		/* Save the TDO byte value */
+		if ( pucTdo )
+		{
+			(*(--pucTdo))   = ucTdoByte;
+		}
+	}
+}
+
+/*****************************************************************************
+ * Function:     xsvfShift
+ * Description:  Goes to the given starting TAP state.
+ *               Calls xsvfShiftOnly to shift in the given TDI data and
+ *               optionally capture the TDO data.
+ *               Compares the TDO captured data against the TDO expected
+ *               data.
+ *               If a data mismatch occurs, then executes the exception
+ *               handling loop upto ucMaxRepeat times.
+ * Parameters:   pucTapState     - Ptr to current TAP state.
+ *               ucStartState    - Starting shift state: Shift-DR or Shift-IR.
+ *               lNumBits        - number of bits to shift.
+ *               plvTdi          - ptr to lenval for TDI data.
+ *               plvTdoCaptured  - ptr to lenval for storing TDO data.
+ *               plvTdoExpected  - ptr to expected TDO data.
+ *               plvTdoMask      - ptr to TDO mask.
+ *               ucEndState      - state in which to end the shift.
+ *               lRunTestTime    - amount of time to wait after the shift.
+ *               ucMaxRepeat     - Maximum number of retries on TDO mismatch.
+ * Returns:      int             - 0 = success; otherwise TDO mismatch.
+ * Notes:        XC9500XL-only Optimization:
+ *               Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1]
+ *               is NOT all zeros and sMatch==1.
+ *****************************************************************************/
+int xsvfShift( unsigned char*   pucTapState,
+	       unsigned char    ucStartState,
+	       long             lNumBits,
+	       lenVal*          plvTdi,
+	       lenVal*          plvTdoCaptured,
+	       lenVal*          plvTdoExpected,
+	       lenVal*          plvTdoMask,
+	       unsigned char    ucEndState,
+	       long             lRunTestTime,
+	       unsigned char    ucMaxRepeat )
+{
+	int             iErrorCode;
+	int             iMismatch;
+	unsigned char   ucRepeat;
+	int             iExitShift;
+
+	iErrorCode  = XSVF_ERROR_NONE;
+	iMismatch   = 0;
+	ucRepeat    = 0;
+	iExitShift  = ( ucStartState != ucEndState );
+
+	XSVFDBG_PRINTF1( 3, "   Shift Length = %ld\n", lNumBits );
+	XSVFDBG_PRINTF( 4, "    TDI          = ");
+	XSVFDBG_PRINTLENVAL( 4, plvTdi );
+	XSVFDBG_PRINTF( 4, "\n");
+	XSVFDBG_PRINTF( 4, "    TDO Expected = ");
+	XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
+	XSVFDBG_PRINTF( 4, "\n");
+
+	if ( !lNumBits )
+	{
+		/* Compatibility with XSVF2.00:  XSDR 0 = no shift, but wait in RTI */
+		if ( lRunTestTime )
+		{
+			/* Wait for prespecified XRUNTEST time */
+			xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
+			XSVFDBG_PRINTF1( 3, "   Wait = %ld usec\n", lRunTestTime );
+			waitTime( lRunTestTime );
+		}
+	}
+	else
+	{
+		do
+		{
+			/* Goto Shift-DR or Shift-IR */
+			xsvfGotoTapState( pucTapState, ucStartState );
+
+			/* Shift TDI and capture TDO */
+			xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift );
+
+			if ( plvTdoExpected )
+			{
+				/* Compare TDO data to expected TDO data */
+				iMismatch   = !EqualLenVal( plvTdoExpected,
+							    plvTdoCaptured,
+							    plvTdoMask );
+			}
+
+			if ( iExitShift )
+			{
+				/* Update TAP state:  Shift->Exit */
+				++(*pucTapState);
+				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
+						 xsvf_pzTapState[ *pucTapState ] );
+
+				if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) )
+				{
+					XSVFDBG_PRINTF( 4, "    TDO Expected = ");
+					XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
+					XSVFDBG_PRINTF( 4, "\n");
+					XSVFDBG_PRINTF( 4, "    TDO Captured = ");
+					XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured );
+					XSVFDBG_PRINTF( 4, "\n");
+					XSVFDBG_PRINTF( 4, "    TDO Mask     = ");
+					XSVFDBG_PRINTLENVAL( 4, plvTdoMask );
+					XSVFDBG_PRINTF( 4, "\n");
+					XSVFDBG_PRINTF1( 3, "   Retry #%d\n", ( ucRepeat + 1 ) );
+					/* Do exception handling retry - ShiftDR only */
+					xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR );
+					/* Shift 1 extra bit */
+					xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR );
+					/* Increment RUNTEST time by an additional 25% */
+					lRunTestTime    += ( lRunTestTime >> 2 );
+				}
+				else
+				{
+					/* Do normal exit from Shift-XR */
+					xsvfGotoTapState( pucTapState, ucEndState );
+				}
+
+				if ( lRunTestTime )
+				{
+					/* Wait for prespecified XRUNTEST time */
+					xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
+					XSVFDBG_PRINTF1( 3, "   Wait = %ld usec\n", lRunTestTime );
+					waitTime( lRunTestTime );
+				}
+			}
+		} while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) );
+	}
+
+	if ( iMismatch )
+	{
+		XSVFDBG_PRINTF( 1, " TDO Expected = ");
+		XSVFDBG_PRINTLENVAL( 1, plvTdoExpected );
+		XSVFDBG_PRINTF( 1, "\n");
+		XSVFDBG_PRINTF( 1, " TDO Captured = ");
+		XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured );
+		XSVFDBG_PRINTF( 1, "\n");
+		XSVFDBG_PRINTF( 1, " TDO Mask     = ");
+		XSVFDBG_PRINTLENVAL( 1, plvTdoMask );
+		XSVFDBG_PRINTF( 1, "\n");
+		if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) )
+		{
+			iErrorCode  = XSVF_ERROR_MAXRETRIES;
+		}
+		else
+		{
+			iErrorCode  = XSVF_ERROR_TDOMISMATCH;
+		}
+	}
+
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfBasicXSDRTDO
+ * Description:  Get the XSDRTDO parameters and execute the XSDRTDO command.
+ *               This is the common function for all XSDRTDO commands.
+ * Parameters:   pucTapState         - Current TAP state.
+ *               lShiftLengthBits    - number of bits to shift.
+ *               sShiftLengthBytes   - number of bytes to read.
+ *               plvTdi              - ptr to lenval for TDI data.
+ *               lvTdoCaptured       - ptr to lenval for storing TDO data.
+ *               iEndState           - state in which to end the shift.
+ *               lRunTestTime        - amount of time to wait after the shift.
+ *               ucMaxRepeat         - maximum xc9500/xl retries.
+ * Returns:      int                 - 0 = success; otherwise TDO mismatch.
+ *****************************************************************************/
+int xsvfBasicXSDRTDO( unsigned char*    pucTapState,
+		      long              lShiftLengthBits,
+		      short             sShiftLengthBytes,
+		      lenVal*           plvTdi,
+		      lenVal*           plvTdoCaptured,
+		      lenVal*           plvTdoExpected,
+		      lenVal*           plvTdoMask,
+		      unsigned char     ucEndState,
+		      long              lRunTestTime,
+		      unsigned char     ucMaxRepeat )
+{
+	readVal( plvTdi, sShiftLengthBytes );
+	if ( plvTdoExpected )
+	{
+		readVal( plvTdoExpected, sShiftLengthBytes );
+	}
+	return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits,
+			   plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask,
+			   ucEndState, lRunTestTime, ucMaxRepeat ) );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoSDRMasking
+ * Description:  Update the data value with the next XSDRINC data and address.
+ * Example:      dataVal=0x01ff, nextData=0xab, addressMask=0x0100,
+ *               dataMask=0x00ff, should set dataVal to 0x02ab
+ * Parameters:   plvTdi          - The current TDI value.
+ *               plvNextData     - the next data value.
+ *               plvAddressMask  - the address mask.
+ *               plvDataMask     - the data mask.
+ * Returns:      void.
+ *****************************************************************************/
+#ifdef  XSVF_SUPPORT_COMPRESSION
+void xsvfDoSDRMasking( lenVal*  plvTdi,
+		       lenVal*  plvNextData,
+		       lenVal*  plvAddressMask,
+		       lenVal*  plvDataMask )
+{
+	int             i;
+	unsigned char   ucTdi;
+	unsigned char   ucTdiMask;
+	unsigned char   ucDataMask;
+	unsigned char   ucNextData;
+	unsigned char   ucNextMask;
+	short           sNextData;
+
+	/* add the address Mask to dataVal and return as a new dataVal */
+	addVal( plvTdi, plvTdi, plvAddressMask );
+
+	ucNextData  = 0;
+	ucNextMask  = 0;
+	sNextData   = plvNextData->len;
+	for ( i = plvDataMask->len - 1; i >= 0; --i )
+	{
+		/* Go through data mask in reverse order looking for mask (1) bits */
+		ucDataMask  = plvDataMask->val[ i ];
+		if ( ucDataMask )
+		{
+			/* Retrieve the corresponding TDI byte value */
+			ucTdi       = plvTdi->val[ i ];
+
+			/* For each bit in the data mask byte, look for 1's */
+			ucTdiMask   = 1;
+			while ( ucDataMask )
+			{
+				if ( ucDataMask & 1 )
+				{
+					if ( !ucNextMask )
+					{
+						/* Get the next data byte */
+						ucNextData  = plvNextData->val[ --sNextData ];
+						ucNextMask  = 1;
+					}
+
+					/* Set or clear the data bit according to the next data */
+					if ( ucNextData & ucNextMask )
+					{
+						ucTdi   |= ucTdiMask;       /* Set bit */
+					}
+					else
+					{
+						ucTdi   &= ( ~ucTdiMask );  /* Clear bit */
+					}
+
+					/* Update the next data */
+					ucNextMask  <<= 1;
+				}
+				ucTdiMask   <<= 1;
+				ucDataMask  >>= 1;
+			}
+
+			/* Update the TDI value */
+			plvTdi->val[ i ]    = ucTdi;
+		}
+	}
+}
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+
+/*============================================================================
+ * XSVF Command Functions (type = TXsvfDoCmdFuncPtr)
+ * These functions update pXsvfInfo->iErrorCode only on an error.
+ * Otherwise, the error code is left alone.
+ * The function returns the error code from the function.
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfDoIllegalCmd
+ * Description:  Function place holder for illegal/unsupported commands.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo )
+{
+	XSVFDBG_PRINTF2( 0, "ERROR:  Encountered unsupported command #%d (%s)\n",
+			 ((unsigned int)(pXsvfInfo->ucCommand)),
+			 ((pXsvfInfo->ucCommand < XLASTCMD)
+			  ? (xsvf_pzCommandName[pXsvfInfo->ucCommand])
+			  : "Unknown") );
+	pXsvfInfo->iErrorCode   = XSVF_ERROR_ILLEGALCMD;
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXCOMPLETE
+ * Description:  XCOMPLETE (no parameters)
+ *               Update complete status for XSVF player.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo )
+{
+	pXsvfInfo->ucComplete   = 1;
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXTDOMASK
+ * Description:  XTDOMASK <lenVal.TdoMask[XSDRSIZE]>
+ *               Prespecify the TDO compare mask.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo )
+{
+	readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes );
+	XSVFDBG_PRINTF( 4, "    TDO Mask     = ");
+	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) );
+	XSVFDBG_PRINTF( 4, "\n");
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSIR
+ * Description:  XSIR <(byte)shiftlen> <lenVal.TDI[shiftlen]>
+ *               Get the instruction and shift the instruction into the TAP.
+ *               If prespecified XRUNTEST!=0, goto RUNTEST and wait after
+ *               the shift for XRUNTEST usec.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSIR( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucShiftIrBits;
+	short           sShiftIrBytes;
+	int             iErrorCode;
+
+	/* Get the shift length and store */
+	readByte( &ucShiftIrBits );
+	sShiftIrBytes   = xsvfGetAsNumBytes( ucShiftIrBits );
+	XSVFDBG_PRINTF1( 3, "   XSIR length = %d\n",
+			 ((unsigned int)ucShiftIrBits) );
+
+	if ( sShiftIrBytes > MAX_LEN )
+	{
+		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
+	}
+	else
+	{
+		/* Get and store instruction to shift in */
+		readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) );
+
+		/* Shift the data */
+		iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
+					 ucShiftIrBits, &(pXsvfInfo->lvTdi),
+					 /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+					 /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
+					 pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
+	}
+
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSIR2
+ * Description:  XSIR <(2-byte)shiftlen> <lenVal.TDI[shiftlen]>
+ *               Get the instruction and shift the instruction into the TAP.
+ *               If prespecified XRUNTEST!=0, goto RUNTEST and wait after
+ *               the shift for XRUNTEST usec.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo )
+{
+	long            lShiftIrBits;
+	short           sShiftIrBytes;
+	int             iErrorCode;
+
+	/* Get the shift length and store */
+	readVal( &(pXsvfInfo->lvTdi), 2 );
+	lShiftIrBits    = value( &(pXsvfInfo->lvTdi) );
+	sShiftIrBytes   = xsvfGetAsNumBytes( lShiftIrBits );
+	XSVFDBG_PRINTF1( 3, "   XSIR2 length = %d\n", (int)lShiftIrBits);
+
+	if ( sShiftIrBytes > MAX_LEN )
+	{
+		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
+	}
+	else
+	{
+		/* Get and store instruction to shift in */
+		readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) );
+
+		/* Shift the data */
+		iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
+					 lShiftIrBits, &(pXsvfInfo->lvTdi),
+					 /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+					 /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
+					 pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
+	}
+
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDR
+ * Description:  XSDR <lenVal.TDI[XSDRSIZE]>
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Compare the captured TDO with the expected TDO from the
+ *               previous XSDRTDO command using the previously specified
+ *               XTDOMASK.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDR( SXsvfInfo* pXsvfInfo )
+{
+	int iErrorCode;
+	readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
+	/* use TDOExpected from last XSDRTDO instruction */
+	iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
+				 pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi),
+				 &(pXsvfInfo->lvTdoCaptured),
+				 &(pXsvfInfo->lvTdoExpected),
+				 &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
+				 pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXRUNTEST
+ * Description:  XRUNTEST <uint32>
+ *               Prespecify the XRUNTEST wait time for shift operations.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo )
+{
+	readVal( &(pXsvfInfo->lvTdi), 4 );
+	pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) );
+	XSVFDBG_PRINTF1( 3, "   XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime );
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXREPEAT
+ * Description:  XREPEAT <byte>
+ *               Prespecify the maximum number of XC9500/XL retries.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo )
+{
+	readByte( &(pXsvfInfo->ucMaxRepeat) );
+	XSVFDBG_PRINTF1( 3, "   XREPEAT = %d\n",
+			 ((unsigned int)(pXsvfInfo->ucMaxRepeat)) );
+	return( XSVF_ERROR_NONE );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRSIZE
+ * Description:  XSDRSIZE <uint32>
+ *               Prespecify the XRUNTEST wait time for shift operations.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo )
+{
+	int iErrorCode;
+	iErrorCode  = XSVF_ERROR_NONE;
+	readVal( &(pXsvfInfo->lvTdi), 4 );
+	pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) );
+	pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits );
+	XSVFDBG_PRINTF1( 3, "   XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits );
+	if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN )
+	{
+		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRTDO
+ * Description:  XSDRTDO <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
+ *               Get the TDI and expected TDO values.  Then, shift.
+ *               Compare the expected TDO with the captured TDO using the
+ *               prespecified XTDOMASK.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo )
+{
+	int iErrorCode;
+	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+					pXsvfInfo->lShiftLengthBits,
+					pXsvfInfo->sShiftLengthBytes,
+					&(pXsvfInfo->lvTdi),
+					&(pXsvfInfo->lvTdoCaptured),
+					&(pXsvfInfo->lvTdoExpected),
+					&(pXsvfInfo->lvTdoMask),
+					pXsvfInfo->ucEndDR,
+					pXsvfInfo->lRunTestTime,
+					pXsvfInfo->ucMaxRepeat );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSETSDRMASKS
+ * Description:  XSETSDRMASKS <lenVal.AddressMask[XSDRSIZE]>
+ *                            <lenVal.DataMask[XSDRSIZE]>
+ *               Get the prespecified address and data mask for the XSDRINC
+ *               command.
+ *               Used for xc9500/xl compressed XSVF data.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+#ifdef  XSVF_SUPPORT_COMPRESSION
+int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo )
+{
+	/* read the addressMask */
+	readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes );
+	/* read the dataMask    */
+	readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes );
+
+	XSVFDBG_PRINTF( 4, "    Address Mask = " );
+	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) );
+	XSVFDBG_PRINTF( 4, "\n" );
+	XSVFDBG_PRINTF( 4, "    Data Mask    = " );
+	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) );
+	XSVFDBG_PRINTF( 4, "\n" );
+
+	return( XSVF_ERROR_NONE );
+}
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRINC
+ * Description:  XSDRINC <lenVal.firstTDI[XSDRSIZE]> <byte(numTimes)>
+ *                       <lenVal.data[XSETSDRMASKS.dataMask.len]> ...
+ *               Get the XSDRINC parameters and execute the XSDRINC command.
+ *               XSDRINC starts by loading the first TDI shift value.
+ *               Then, for numTimes, XSDRINC gets the next piece of data,
+ *               replaces the bits from the starting TDI as defined by the
+ *               XSETSDRMASKS.dataMask, adds the address mask from
+ *               XSETSDRMASKS.addressMask, shifts the new TDI value,
+ *               and compares the TDO to the expected TDO from the previous
+ *               XSDRTDO command using the XTDOMASK.
+ *               Used for xc9500/xl compressed XSVF data.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+#ifdef  XSVF_SUPPORT_COMPRESSION
+int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo )
+{
+	int             iErrorCode;
+	int             iDataMaskLen;
+	unsigned char   ucDataMask;
+	unsigned char   ucNumTimes;
+	unsigned char   i;
+
+	readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
+	iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
+				 pXsvfInfo->lShiftLengthBits,
+				 &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured),
+				 &(pXsvfInfo->lvTdoExpected),
+				 &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
+				 pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
+	if ( !iErrorCode )
+	{
+		/* Calculate number of data mask bits */
+		iDataMaskLen    = 0;
+		for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i )
+		{
+			ucDataMask  = pXsvfInfo->lvDataMask.val[ i ];
+			while ( ucDataMask )
+			{
+				iDataMaskLen    += ( ucDataMask & 1 );
+				ucDataMask      >>= 1;
+			}
+		}
+
+		/* Get the number of data pieces, i.e. number of times to shift */
+		readByte( &ucNumTimes );
+
+		/* For numTimes, get data, fix TDI, and shift */
+		for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i )
+		{
+			readVal( &(pXsvfInfo->lvNextData),
+				 xsvfGetAsNumBytes( iDataMaskLen ) );
+			xsvfDoSDRMasking( &(pXsvfInfo->lvTdi),
+					  &(pXsvfInfo->lvNextData),
+					  &(pXsvfInfo->lvAddressMask),
+					  &(pXsvfInfo->lvDataMask) );
+			iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState),
+						 XTAPSTATE_SHIFTDR,
+						 pXsvfInfo->lShiftLengthBits,
+						 &(pXsvfInfo->lvTdi),
+						 &(pXsvfInfo->lvTdoCaptured),
+						 &(pXsvfInfo->lvTdoExpected),
+						 &(pXsvfInfo->lvTdoMask),
+						 pXsvfInfo->ucEndDR,
+						 pXsvfInfo->lRunTestTime,
+						 pXsvfInfo->ucMaxRepeat );
+		}
+	}
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRBCE
+ * Description:  XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]>
+ *               If not already in SHIFTDR, goto SHIFTDR.
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Ignore TDO.
+ *               If cmd==XSDRE, then goto ENDDR.  Otherwise, stay in ShiftDR.
+ *               XSDRB, XSDRC, and XSDRE are the same implementation.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucEndDR;
+	int             iErrorCode;
+	ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ?
+				  pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
+	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+					pXsvfInfo->lShiftLengthBits,
+					pXsvfInfo->sShiftLengthBytes,
+					&(pXsvfInfo->lvTdi),
+					/*plvTdoCaptured*/0, /*plvTdoExpected*/0,
+					/*plvTdoMask*/0, ucEndDR,
+					/*lRunTestTime*/0, /*ucMaxRepeat*/0 );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSDRTDOBCE
+ * Description:  XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
+ *               If not already in SHIFTDR, goto SHIFTDR.
+ *               Shift the given TDI data into the JTAG scan chain.
+ *               Compare TDO, but do NOT use XTDOMASK.
+ *               If cmd==XSDRTDOE, then goto ENDDR.  Otherwise, stay in ShiftDR.
+ *               XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucEndDR;
+	int             iErrorCode;
+	ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ?
+				  pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
+	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
+					pXsvfInfo->lShiftLengthBits,
+					pXsvfInfo->sShiftLengthBytes,
+					&(pXsvfInfo->lvTdi),
+					&(pXsvfInfo->lvTdoCaptured),
+					&(pXsvfInfo->lvTdoExpected),
+					/*plvTdoMask*/0, ucEndDR,
+					/*lRunTestTime*/0, /*ucMaxRepeat*/0 );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXSTATE
+ * Description:  XSTATE <byte>
+ *               <byte> == XTAPSTATE;
+ *               Get the state parameter and transition the TAP to that state.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucNextState;
+	int             iErrorCode;
+	readByte( &ucNextState );
+	iErrorCode  = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState );
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXENDXR
+ * Description:  XENDIR/XENDDR <byte>
+ *               <byte>:  0 = RUNTEST;  1 = PAUSE.
+ *               Get the prespecified XENDIR or XENDDR.
+ *               Both XENDIR and XENDDR use the same implementation.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo )
+{
+	int             iErrorCode;
+	unsigned char   ucEndState;
+
+	iErrorCode  = XSVF_ERROR_NONE;
+	readByte( &ucEndState );
+	if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) )
+	{
+		iErrorCode  = XSVF_ERROR_ILLEGALSTATE;
+	}
+	else
+	{
+
+		if ( pXsvfInfo->ucCommand == XENDIR )
+		{
+			if ( ucEndState == XENDXR_RUNTEST )
+			{
+				pXsvfInfo->ucEndIR  = XTAPSTATE_RUNTEST;
+			}
+			else
+			{
+				pXsvfInfo->ucEndIR  = XTAPSTATE_PAUSEIR;
+			}
+			XSVFDBG_PRINTF1( 3, "   ENDIR State = %s\n",
+					 xsvf_pzTapState[ pXsvfInfo->ucEndIR ] );
+		}
+		else    /* XENDDR */
+		{
+			if ( ucEndState == XENDXR_RUNTEST )
+			{
+				pXsvfInfo->ucEndDR  = XTAPSTATE_RUNTEST;
+			}
+			else
+			{
+				pXsvfInfo->ucEndDR  = XTAPSTATE_PAUSEDR;
+			}
+			XSVFDBG_PRINTF1( 3, "   ENDDR State = %s\n",
+					 xsvf_pzTapState[ pXsvfInfo->ucEndDR ] );
+		}
+	}
+
+	if ( iErrorCode != XSVF_ERROR_NONE )
+	{
+		pXsvfInfo->iErrorCode   = iErrorCode;
+	}
+	return( iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXCOMMENT
+ * Description:  XCOMMENT <text string ending in \0>
+ *               <text string ending in \0> == text comment;
+ *               Arbitrary comment embedded in the XSVF.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo )
+{
+	/* Use the comment for debugging */
+	/* Otherwise, read through the comment to the end '\0' and ignore */
+	unsigned char   ucText;
+
+	if ( xsvf_iDebugLevel > 0 )
+	{
+		putc( ' ' );
+	}
+
+	do
+	{
+		readByte( &ucText );
+		if ( xsvf_iDebugLevel > 0 )
+		{
+			putc( ucText ? ucText : '\n' );
+		}
+	} while ( ucText );
+
+	pXsvfInfo->iErrorCode   = XSVF_ERROR_NONE;
+
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfDoXWAIT
+ * Description:  XWAIT <wait_state> <end_state> <wait_time>
+ *               If not already in <wait_state>, then go to <wait_state>.
+ *               Wait in <wait_state> for <wait_time> microseconds.
+ *               Finally, if not already in <end_state>, then goto <end_state>.
+ * Parameters:   pXsvfInfo   - XSVF information pointer.
+ * Returns:      int         - 0 = success;  non-zero = error.
+ *****************************************************************************/
+int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo )
+{
+	unsigned char   ucWaitState;
+	unsigned char   ucEndState;
+	long            lWaitTime;
+
+	/* Get Parameters */
+	/* <wait_state> */
+	readVal( &(pXsvfInfo->lvTdi), 1 );
+	ucWaitState = pXsvfInfo->lvTdi.val[0];
+
+	/* <end_state> */
+	readVal( &(pXsvfInfo->lvTdi), 1 );
+	ucEndState = pXsvfInfo->lvTdi.val[0];
+
+	/* <wait_time> */
+	readVal( &(pXsvfInfo->lvTdi), 4 );
+	lWaitTime = value( &(pXsvfInfo->lvTdi) );
+	XSVFDBG_PRINTF2( 3, "   XWAIT:  state = %s; time = %ld\n",
+			 xsvf_pzTapState[ ucWaitState ], lWaitTime );
+
+	/* If not already in <wait_state>, go to <wait_state> */
+	if ( pXsvfInfo->ucTapState != ucWaitState )
+	{
+		xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState );
+	}
+
+	/* Wait for <wait_time> microseconds */
+	waitTime( lWaitTime );
+
+	/* If not already in <end_state>, go to <end_state> */
+	if ( pXsvfInfo->ucTapState != ucEndState )
+	{
+		xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState );
+	}
+
+	return( XSVF_ERROR_NONE );
+}
+
+
+/*============================================================================
+ * Execution Control Functions
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfInitialize
+ * Description:  Initialize the xsvf player.
+ *               Call this before running the player to initialize the data
+ *               in the SXsvfInfo struct.
+ *               xsvfCleanup is called to clean up the data in SXsvfInfo
+ *               after the XSVF is played.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF information.
+ * Returns:      int - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfInitialize( SXsvfInfo* pXsvfInfo )
+{
+	/* Initialize values */
+	pXsvfInfo->iErrorCode   = xsvfInfoInit( pXsvfInfo );
+
+	if ( !pXsvfInfo->iErrorCode )
+	{
+		/* Initialize the TAPs */
+		pXsvfInfo->iErrorCode   = xsvfGotoTapState( &(pXsvfInfo->ucTapState),
+							    XTAPSTATE_RESET );
+	}
+
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfRun
+ * Description:  Run the xsvf player for a single command and return.
+ *               First, call xsvfInitialize.
+ *               Then, repeatedly call this function until an error is detected
+ *               or until the pXsvfInfo->ucComplete variable is non-zero.
+ *               Finally, call xsvfCleanup to cleanup any remnants.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF information.
+ * Returns:      int         - 0 = success; otherwise error.
+ *****************************************************************************/
+int xsvfRun( SXsvfInfo* pXsvfInfo )
+{
+	/* Process the XSVF commands */
+	if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) )
+	{
+		/* read 1 byte for the instruction */
+		readByte( &(pXsvfInfo->ucCommand) );
+		++(pXsvfInfo->lCommandCount);
+
+		if ( pXsvfInfo->ucCommand < XLASTCMD )
+		{
+			/* Execute the command.  Func sets error code. */
+			XSVFDBG_PRINTF1( 2, "  %s\n",
+					 xsvf_pzCommandName[pXsvfInfo->ucCommand] );
+			/* If your compiler cannot take this form,
+			   then convert to a switch statement */
+#if 0 /* test-only */
+			xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo );
+#else
+			switch (pXsvfInfo->ucCommand) {
+			case 0:
+				xsvfDoXCOMPLETE(pXsvfInfo);        /*  0 */
+				break;
+			case 1:
+				xsvfDoXTDOMASK(pXsvfInfo);         /*  1 */
+				break;
+			case 2:
+				xsvfDoXSIR(pXsvfInfo);             /*  2 */
+				break;
+			case 3:
+				xsvfDoXSDR(pXsvfInfo);             /*  3 */
+				break;
+			case 4:
+				xsvfDoXRUNTEST(pXsvfInfo);         /*  4 */
+				break;
+			case 5:
+				xsvfDoIllegalCmd(pXsvfInfo);       /*  5 */
+				break;
+			case 6:
+				xsvfDoIllegalCmd(pXsvfInfo);       /*  6 */
+				break;
+			case 7:
+				xsvfDoXREPEAT(pXsvfInfo);          /*  7 */
+				break;
+			case 8:
+				xsvfDoXSDRSIZE(pXsvfInfo);         /*  8 */
+				break;
+			case 9:
+				xsvfDoXSDRTDO(pXsvfInfo);          /*  9 */
+				break;
+#ifdef  XSVF_SUPPORT_COMPRESSION
+			case 10:
+				xsvfDoXSETSDRMASKS(pXsvfInfo);     /* 10 */
+				break;
+			case 11:
+				xsvfDoXSDRINC(pXsvfInfo);          /* 11 */
+				break;
+#else
+			case 10:
+				xsvfDoIllegalCmd(pXsvfInfo);       /* 10 */
+				break;
+			case 11:
+				xsvfDoIllegalCmd(pXsvfInfo);       /* 11 */
+				break;
+#endif  /* XSVF_SUPPORT_COMPRESSION */
+			case 12:
+				xsvfDoXSDRBCE(pXsvfInfo);          /* 12 */
+				break;
+			case 13:
+				xsvfDoXSDRBCE(pXsvfInfo);          /* 13 */
+				break;
+			case 14:
+				xsvfDoXSDRBCE(pXsvfInfo);          /* 14 */
+				break;
+			case 15:
+				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 15 */
+				break;
+			case 16:
+				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 16 */
+				break;
+			case 17:
+				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 17 */
+				break;
+			case 18:
+				xsvfDoXSTATE(pXsvfInfo);           /* 18 */
+				break;
+			case 19:
+				xsvfDoXENDXR(pXsvfInfo);           /* 19 */
+				break;
+			case 20:
+				xsvfDoXENDXR(pXsvfInfo);           /* 20 */
+				break;
+			case 21:
+				xsvfDoXSIR2(pXsvfInfo);            /* 21 */
+				break;
+			case 22:
+				xsvfDoXCOMMENT(pXsvfInfo);         /* 22 */
+				break;
+			case 23:
+				xsvfDoXWAIT(pXsvfInfo);             /* 23 */
+				break;
+			}
+#endif
+		}
+		else
+		{
+			/* Illegal command value.  Func sets error code. */
+			xsvfDoIllegalCmd( pXsvfInfo );
+		}
+	}
+
+	return( pXsvfInfo->iErrorCode );
+}
+
+/*****************************************************************************
+ * Function:     xsvfCleanup
+ * Description:  cleanup remnants of the xsvf player.
+ * Parameters:   pXsvfInfo   - ptr to the XSVF information.
+ * Returns:      void.
+ *****************************************************************************/
+void xsvfCleanup( SXsvfInfo* pXsvfInfo )
+{
+	xsvfInfoCleanup( pXsvfInfo );
+}
+
+
+/*============================================================================
+ * xsvfExecute() - The primary entry point to the XSVF player
+ ============================================================================*/
+
+/*****************************************************************************
+ * Function:     xsvfExecute
+ * Description:  Process, interpret, and apply the XSVF commands.
+ *               See port.c:readByte for source of XSVF data.
+ * Parameters:   none.
+ * Returns:      int - Legacy result values:  1 == success;  0 == failed.
+ *****************************************************************************/
+int xsvfExecute(void)
+{
+	SXsvfInfo   xsvfInfo;
+
+	xsvfInitialize( &xsvfInfo );
+
+	while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) )
+	{
+		xsvfRun( &xsvfInfo );
+	}
+
+	if ( xsvfInfo.iErrorCode )
+	{
+		XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[
+					 ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST )
+					 ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] );
+		XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld.  See line #%ld in the XSVF ASCII file.\n",
+				 xsvfInfo.lCommandCount, xsvfInfo.lCommandCount );
+	}
+	else
+	{
+		XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" );
+	}
+
+	xsvfCleanup( &xsvfInfo );
+
+	return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) );
+}
+
+
+/*****************************************************************************
+ * Function:     do_cpld
+ * Description:  main function.
+ *               Specified here for creating stand-alone debug executable.
+ *               Embedded users should call xsvfExecute() directly.
+ * Parameters:   iArgc    - number of command-line arguments.
+ *               ppzArgv  - array of ptrs to strings (command-line arguments).
+ * Returns:      int      - Legacy return value:  1 = success; 0 = error.
+ *****************************************************************************/
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int     iErrorCode;
+	char*   pzXsvfFileName;
+	unsigned long duration;
+	unsigned long long startClock, endClock;
+
+	iErrorCode          = XSVF_ERRORCODE( XSVF_ERROR_NONE );
+	pzXsvfFileName      = 0;
+	xsvf_iDebugLevel    = 0;
+
+	printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION);
+	printf("XSVF Filesize = %d bytes\n", filesize);
+
+	/* Initialize the I/O.  SetPort initializes I/O on first call */
+	setPort( TMS, 1 );
+
+	/* Execute the XSVF in the file */
+	startClock  = get_ticks();
+	iErrorCode  = xsvfExecute();
+	endClock    = get_ticks();
+	duration    = (unsigned long)(endClock - startClock);
+	printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk()));
+
+	return( iErrorCode );
+}
+U_BOOT_CMD(
+	cpld,	1,	1,	do_cpld,
+	"cpld    - Program onboard CPLD\n",
+	NULL
+	);
diff --git a/board/esd/common/xilinx_jtag/micro.h b/board/esd/common/xilinx_jtag/micro.h
new file mode 100755
index 0000000..3c463ab
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/micro.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*****************************************************************************
+ * File:         micro.h
+ * Description:  This header file contains the function prototype to the
+ *               primary interface function for the XSVF player.
+ * Usage:        FIRST - PORTS.C
+ *               Customize the ports.c function implementations to establish
+ *               the correct protocol for communicating with your JTAG ports
+ *               (setPort() and readTDOBit()) and tune the waitTime() delay
+ *               function.  Also, establish access to the XSVF data source
+ *               in the readByte() function.
+ *               FINALLY - Call xsvfExecute().
+ *****************************************************************************/
+#ifndef XSVF_MICRO_H
+#define XSVF_MICRO_H
+
+/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
+#define XSVF_LEGACY_SUCCESS 1
+#define XSVF_LEGACY_ERROR   0
+
+/* 4.04 [NEW] Error codes for xsvfExecute. */
+/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
+#define XSVF_ERROR_NONE         0
+#define XSVF_ERROR_UNKNOWN      1
+#define XSVF_ERROR_TDOMISMATCH  2
+#define XSVF_ERROR_MAXRETRIES   3   /* TDO mismatch after max retries */
+#define XSVF_ERROR_ILLEGALCMD   4
+#define XSVF_ERROR_ILLEGALSTATE 5
+#define XSVF_ERROR_DATAOVERFLOW 6   /* Data > lenVal MAX_LEN buffer size*/
+/* Insert new errors here */
+#define XSVF_ERROR_LAST         7
+
+/*****************************************************************************
+ * Function:     xsvfExecute
+ * Description:  Process, interpret, and apply the XSVF commands.
+ *               See port.c:readByte for source of XSVF data.
+ * Parameters:   none.
+ * Returns:      int - For error codes see above.
+ *****************************************************************************/
+int xsvfExecute(void);
+
+#endif  /* XSVF_MICRO_H */
diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c
new file mode 100755
index 0000000..3ad94a5
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/ports.c
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: ports.c                                       */
+/* abstract:  This file contains the routines to       */
+/*            output values on the JTAG ports, to read */
+/*            the TDO bit, and to read a byte of data  */
+/*            from the prom                            */
+/*                                                     */
+/*******************************************************/
+
+#include <common.h>
+#include <asm/processor.h>
+
+#include "ports.h"
+
+static unsigned long output = 0;
+static int filepos = 0;
+static int oldstate = 0;
+static int newstate = 0;
+static int readptr = 0;
+
+extern long filesize;
+extern const unsigned char fpgadata[];
+
+
+/* if in debugging mode, then just set the variables */
+void setPort(short p,short val)
+{
+	if (p==TMS) {
+		if (val) {
+			output |= JTAG_TMS;
+		} else {
+			output &= ~JTAG_TMS;
+		}
+	}
+	if (p==TDI) {
+		if (val) {
+			output |= JTAG_TDI;
+		} else {
+			output &= ~JTAG_TDI;
+		}
+	}
+	if (p==TCK) {
+		if (val) {
+			output |= JTAG_TCK;
+		} else {
+			output &= ~JTAG_TCK;
+		}
+		out32(GPIO0_OR, output);
+	}
+}
+
+
+/* toggle tck LH */
+void pulseClock(void)
+{
+	setPort(TCK,0);  /* set the TCK port to low  */
+	setPort(TCK,1);  /* set the TCK port to high */
+}
+
+
+/* read in a byte of data from the prom */
+void readByte(unsigned char *data)
+{
+	/* pretend reading using a file */
+	*data = fpgadata[readptr++];
+	newstate = (100 * filepos++) / filesize;
+	if (newstate != oldstate) {
+		printf("%4d\r\r\r\r", newstate);
+		oldstate = newstate;
+	}
+}
+
+/* read the TDO bit from port */
+unsigned char readTDOBit(void)
+{
+	unsigned long inputs;
+
+	inputs = in32(GPIO0_IR);
+	if (inputs & JTAG_TDO)
+		return 1;
+	else
+		return 0;
+}
+
+
+/* Wait at least the specified number of microsec.                           */
+/* Use a timer if possible; otherwise estimate the number of instructions    */
+/* necessary to be run based on the microcontroller speed.  For this example */
+/* we pulse the TCK port a number of times based on the processor speed.     */
+void waitTime(long microsec)
+{
+	udelay(microsec); /* esd */
+}
diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h
new file mode 100755
index 0000000..0e38990
--- /dev/null
+++ b/board/esd/common/xilinx_jtag/ports.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*******************************************************/
+/* file: ports.h                                       */
+/* abstract:  This file contains extern declarations   */
+/*            for providing stimulus to the JTAG ports.*/
+/*******************************************************/
+
+#ifndef ports_dot_h
+#define ports_dot_h
+
+/* these constants are used to send the appropriate ports to setPort */
+/* they should be enumerated types, but some of the microcontroller  */
+/* compilers don't like enumerated types */
+#define TCK (short) 0
+#define TMS (short) 1
+#define TDI (short) 2
+
+/*
+ * Use CFG_FPGA_xxx defines from board include file.
+ */
+#define JTAG_TMS   CFG_FPGA_PRG     /* output */
+#define JTAG_TCK   CFG_FPGA_CLK     /* output */
+#define JTAG_TDI   CFG_FPGA_DATA    /* output */
+#define JTAG_TDO   CFG_FPGA_DONE    /* input */
+
+/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
+void setPort(short p, short val);
+
+/* read the TDO bit and store it in val */
+unsigned char readTDOBit(void);
+
+/* make clock go down->up->down*/
+void pulseClock(void);
+
+/* read the next byte of data from the xsvf file */
+void readByte(unsigned char *data);
+
+void waitTime(long microsec);
+
+#endif
diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile
new file mode 100755
index 0000000..a60495a
--- /dev/null
+++ b/board/esd/cpci2dp/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/cpci2dp/config.mk b/board/esd/cpci2dp/config.mk
new file mode 100755
index 0000000..2da4c9f
--- /dev/null
+++ b/board/esd/cpci2dp/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd CPCI2DP board
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
new file mode 100755
index 0000000..df10c0e
--- /dev/null
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+int board_early_init_f (void)
+{
+	unsigned long cntrl0Reg;
+
+	/*
+	 * Setup GPIO pins (CS4+CS7 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x00900000);
+
+	/* set output pins to high */
+	out32(GPIO0_OR,	 CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
+	/* INTA# is open drain */
+	out32(GPIO0_ODR, CFG_INTA_FAKE);
+	/* setup for output */
+	out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP);
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) unused
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr(uicer, 0x00000000);	/* disable all ints */
+	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
+
+	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long cntrl0Reg;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Select cts (and not dsr) on uart1
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming CPCI2DP");
+	} else {
+		puts(str);
+	}
+
+	printf(" (Ver 1.0)");
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 64 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *	   <state>     -1: deliver current state
+ *		       0: disable write
+ *		       1: enable write
+ *  Returns:	       -1: wrong device address
+ *			0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state) {
+	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+#endif
+
+#if defined(CFG_EEPROM_WREN)
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(
+	   eepwren,	2,	0,	do_eep_wren,
+	   "eepwren - Enable / disable / query EEPROM write access\n",
+	   NULL
+	   );
+#endif /* #if defined(CFG_EEPROM_WREN) */
diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c
new file mode 100755
index 0000000..de847f9
--- /dev/null
+++ b/board/esd/cpci2dp/flash.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+	mtdcr(ebccfgd, pbcr);
+	/*          printf("pb1cr = %x\n", pbcr); */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/cpci2dp/u-boot.lds b/board/esd/cpci2dp/u-boot.lds
new file mode 100755
index 0000000..f7a20d1
--- /dev/null
+++ b/board/esd/cpci2dp/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile
new file mode 100755
index 0000000..9340a32
--- /dev/null
+++ b/board/esd/cpci405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk
new file mode 100755
index 0000000..0be45c7
--- /dev/null
+++ b/board/esd/cpci405/config.mk
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd CPCI405 boards
+#
+
+ifeq ($(BOARD_REVISION),CPCI4052)
+TEXT_BASE = 0xFFFC0000
+else
+ifeq ($(BOARD_REVISION),CPCI405DT)
+TEXT_BASE = 0xFFFC0000
+else
+ifeq ($(BOARD_REVISION),CPCI405AB)
+TEXT_BASE = 0xFFFC0000
+else
+TEXT_BASE = 0xFFFD0000
+endif
+endif
+endif
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
new file mode 100755
index 0000000..2ab9673
--- /dev/null
+++ b/board/esd/cpci405/cpci405.c
@@ -0,0 +1,799 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+#include <net.h>
+
+/* ------------------------------------------------------------------------- */
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);       /*cmd_boot.c*/
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#ifdef CONFIG_CPCI405_VER2
+# ifdef CONFIG_CPCI405AB
+#  include "fpgadata_cpci405ab.c"
+# else
+#  include "fpgadata_cpci4052.c"
+# endif
+#else
+# include "fpgadata_cpci405.c"
+#endif
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+#include "../common/auto_update.h"
+
+#ifdef CONFIG_CPCI405AB
+au_image_t au_image[] = {
+	{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+	{"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+	{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+#ifdef CONFIG_CPCI405_VER2
+au_image_t au_image[] = {
+	{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
+	{"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+	{"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
+};
+#else
+au_image_t au_image[] = {
+	{"cpci405/preinst.img", 0, -1, AU_SCRIPT},
+	{"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
+	{"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
+	{"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
+	{"cpci405/postinst.img", 0, 0, AU_SCRIPT},
+};
+#endif
+#endif
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+
+/* Prototypes */
+int cpci405_version(void);
+int gunzip(void *, int, unsigned char *, unsigned long *);
+void lxt971_no_sleep(void);
+
+
+int board_early_init_f (void)
+{
+#ifndef CONFIG_CPCI405_VER2
+	int index, len, i;
+	int status;
+#endif
+
+#ifdef FPGA_DEBUG
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f();
+#endif
+
+	/*
+	 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
+	 */
+	out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
+	out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
+	out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
+	out32(GPIO0_OR, 0);                  /* pull prg low            */
+
+	/*
+	 * Boot onboard FPGA
+	 */
+#ifndef CONFIG_CPCI405_VER2
+	if (cpci405_version() == 1) {
+		status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
+		if (status != 0) {
+			/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+			DECLARE_GLOBAL_DATA_PTR;
+
+			/* set up serial port with default baudrate */
+			(void) get_clocks ();
+			gd->baudrate = CONFIG_BAUDRATE;
+			serial_init ();
+			console_init_f();
+#endif
+			printf("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}
+
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i=0; i<4; i++) {
+				len = fpgadata[index];
+				printf("FPGA: %s\n", &(fpgadata[index+1]));
+				index += len+3;
+			}
+			putc ('\n');
+			/* delayed reboot */
+			for (i=20; i>0; i--) {
+				printf("Rebooting in %2d seconds \r",i);
+				for (index=0;index<1000;index++)
+					udelay(1000);
+			}
+			putc ('\n');
+			do_reset(NULL, 0, 0, NULL);
+		}
+	}
+#endif /* !CONFIG_CPCI405_VER2 */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	if (cpci405_version() == 3) {
+		mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
+	} else {
+		mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	}
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int ctermm2(void)
+{
+#ifdef CONFIG_CPCI405_VER2
+	return 0;                       /* no, board is cpci405 */
+#else
+	if ((*(unsigned char *)0xf0000400 == 0x00) &&
+	    (*(unsigned char *)0xf0000401 == 0x01))
+		return 0;               /* no, board is cpci405 */
+	else
+		return -1;              /* yes, board is cterm-m2 */
+#endif
+}
+
+
+int cpci405_host(void)
+{
+	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+		return -1;              /* yes, board is cpci405 host */
+	else
+		return 0;               /* no, board is cpci405 adapter */
+}
+
+
+int cpci405_version(void)
+{
+	unsigned long cntrl0Reg;
+	unsigned long value;
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	switch (value) {
+	case 0x00180000:
+		/* CS2==1 && CS3==1 -> version 1 */
+		return 1;
+	case 0x00080000:
+		/* CS2==0 && CS3==1 -> version 2 */
+		return 2;
+	case 0x00100000:
+		/* CS2==1 && CS3==0 -> version 3 */
+		return 3;
+	case 0x00000000:
+		/* CS2==0 && CS3==0 -> version 4 */
+		return 4;
+	default:
+		/* should not be reached! */
+		return 2;
+	}
+}
+
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long cntrl0Reg;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+#ifdef CONFIG_CPCI405_VER2
+	{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	/*
+	 * On CPCI-405 version 2 the environment is saved in eeprom!
+	 * FPGA can be gzip compressed (malloc) and booted this late.
+	 */
+
+	if (cpci405_version() >= 2) {
+		/*
+		 * Setup GPIO pins (CS6+CS7 as GPIO)
+		 */
+		cntrl0Reg = mfdcr(cntrl0);
+		mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+
+		dst = malloc(CFG_FPGA_MAX_SIZE);
+		if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+			printf ("GUNZIP ERROR - must RESET board to recover\n");
+			do_reset (NULL, 0, 0, NULL);
+		}
+
+		status = fpga_boot(dst, len);
+		if (status != 0) {
+			printf("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}
+
+			/* display infos on fpgaimage */
+			index = 15;
+			for (i=0; i<4; i++) {
+				len = dst[index];
+				printf("FPGA: %s\n", &(dst[index+1]));
+				index += len+3;
+			}
+			putc ('\n');
+			/* delayed reboot */
+			for (i=20; i>0; i--) {
+				printf("Rebooting in %2d seconds \r",i);
+				for (index=0;index<1000;index++)
+					udelay(1000);
+			}
+			putc ('\n');
+			do_reset(NULL, 0, 0, NULL);
+		}
+
+		/* restore gpio/cs settings */
+		mtdcr(cntrl0, cntrl0Reg);
+
+		puts("FPGA:  ");
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("%s ", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+
+		free(dst);
+
+		/*
+		 * Reset FPGA via FPGA_DATA pin
+		 */
+		SET_FPGA(FPGA_PRG | FPGA_CLK);
+		udelay(1000); /* wait 1ms */
+		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+		udelay(1000); /* wait 1ms */
+
+		if (cpci405_version() == 3) {
+			volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
+			volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
+
+			/*
+			 * Enable outputs in fpga on version 3 board
+			 */
+			*fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
+
+			/*
+			 * Set outputs to 0
+			 */
+			*leds = 0x00;
+
+			/*
+			 * Reset external DUART
+			 */
+			*fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
+			udelay(100);
+			*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
+		}
+	}
+	else {
+		puts("\n*** U-Boot Version does not match Board Version!\n");
+		puts("*** CPCI-405 Version 1.x detected!\n");
+		puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
+	}
+	}
+
+#else /* CONFIG_CPCI405_VER2 */
+
+#if 0 /* test-only: code-plug now not relavant for ip-address any more */
+	/*
+	 * Generate last byte of ip-addr from code-plug @ 0xf0000400
+	 */
+	if (ctermm2()) {
+		char str[32];
+		unsigned char ipbyte = *(unsigned char *)0xf0000400;
+
+		/*
+		 * Only overwrite ip-addr with allowed values
+		 */
+		if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
+			bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
+			sprintf(str, "%ld.%ld.%ld.%ld",
+				(bd->bi_ip_addr & 0xff000000) >> 24,
+				(bd->bi_ip_addr & 0x00ff0000) >> 16,
+				(bd->bi_ip_addr & 0x0000ff00) >> 8,
+				(bd->bi_ip_addr & 0x000000ff));
+			setenv("ipaddr", str);
+		}
+	}
+#endif
+
+	if (cpci405_version() >= 2) {
+		puts("\n*** U-Boot Version does not match Board Version!\n");
+		puts("*** CPCI-405 Board Version 2.x detected!\n");
+		puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
+	}
+
+#endif /* CONFIG_CPCI405_VER2 */
+
+	/*
+	 * Select cts (and not dsr) on uart1
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+#ifndef CONFIG_CPCI405_VER2
+	int index;
+	int len;
+#endif
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+	unsigned short ver;
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming CPCI405");
+	} else {
+		puts(str);
+	}
+
+	ver = cpci405_version();
+	printf(" (Ver %d.x, ", ver);
+
+#if 0 /* test-only */
+	if (ver >= 2) {
+		volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
+
+		if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
+			puts ("FLASH Bank B, ");
+		} else {
+			puts ("FLASH Bank A, ");
+		}
+	}
+#endif
+
+	if (ctermm2()) {
+		char str[4];
+
+		/*
+		 * Read board-id and save in env-variable
+		 */
+		sprintf(str, "%d", *(unsigned char *)0xf0000400);
+		setenv("boardid", str);
+		printf("CTERM-M2 - Id=%s)", str);
+	} else {
+		if (cpci405_host()) {
+			puts ("PCI Host Version)");
+		} else {
+			puts ("PCI Adapter Version)");
+		}
+	}
+
+#ifndef CONFIG_CPCI405_VER2
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = fpgadata[index];
+		printf("%s ", &(fpgadata[index+1]));
+		index += len+3;
+	}
+#endif
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_CPCI405_VER2
+#ifdef CONFIG_IDE_RESET
+
+void ide_set_reset(int on)
+{
+	volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		*fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
+	} else {		/* release RESET */
+		*fpga_mode |= CFG_FPGA_MODE_CF_RESET;
+	}
+}
+
+#endif /* CONFIG_IDE_RESET */
+#endif /* CONFIG_CPCI405_VER2 */
+
+
+#ifdef CONFIG_CPCI405AB
+
+#define ONE_WIRE_CLEAR   (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+			  |= CFG_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_SET     (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+			  &= ~CFG_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_GET     (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
+			  & CFG_FPGA_MODE_1WIRE)
+
+/*
+ * Generate a 1-wire reset, return 1 if no presence detect was found,
+ * return 0 otherwise.
+ * (NOTE: Does not handle alarm presence from DS2404/DS1994)
+ */
+int OWTouchReset(void)
+{
+	int result;
+
+	ONE_WIRE_CLEAR;
+	udelay(480);
+	ONE_WIRE_SET;
+	udelay(70);
+
+	result = ONE_WIRE_GET;
+
+	udelay(410);
+	return result;
+}
+
+
+/*
+ * Send 1 a 1-wire write bit.
+ * Provide 10us recovery time.
+ */
+void OWWriteBit(int bit)
+{
+	if (bit) {
+		/*
+		 * write '1' bit
+		 */
+		ONE_WIRE_CLEAR;
+		udelay(6);
+		ONE_WIRE_SET;
+		udelay(64);
+	} else {
+		/*
+		 * write '0' bit
+		 */
+		ONE_WIRE_CLEAR;
+		udelay(60);
+		ONE_WIRE_SET;
+		udelay(10);
+	}
+}
+
+
+/*
+ * Read a bit from the 1-wire bus and return it.
+ * Provide 10us recovery time.
+ */
+int OWReadBit(void)
+{
+	int result;
+
+	ONE_WIRE_CLEAR;
+	udelay(6);
+	ONE_WIRE_SET;
+	udelay(9);
+
+	result = ONE_WIRE_GET;
+
+	udelay(55);
+	return result;
+}
+
+
+void OWWriteByte(int data)
+{
+	int loop;
+
+	for (loop=0; loop<8; loop++) {
+		OWWriteBit(data & 0x01);
+		data >>= 1;
+	}
+}
+
+
+int OWReadByte(void)
+{
+	int loop, result = 0;
+
+	for (loop=0; loop<8; loop++) {
+		result >>= 1;
+		if (OWReadBit()) {
+			result |= 0x80;
+		}
+	}
+
+	return result;
+}
+
+
+int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile unsigned short val;
+	int result;
+	int i;
+	unsigned char ow_id[6];
+	char str[32];
+	unsigned char ow_crc;
+
+	/*
+	 * Clear 1-wire bit (open drain with pull-up)
+	 */
+	val = *(volatile unsigned short *)0xf0400000;
+	val &= ~0x1000; /* clear 1-wire bit */
+	*(volatile unsigned short *)0xf0400000 = val;
+
+	result = OWTouchReset();
+	if (result != 0) {
+		puts("No 1-wire device detected!\n");
+	}
+
+	OWWriteByte(0x33); /* send read rom command */
+	OWReadByte(); /* skip family code ( == 0x01) */
+	for (i=0; i<6; i++) {
+		ow_id[i] = OWReadByte();
+	}
+	ow_crc = OWReadByte(); /* read crc */
+
+	sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
+	printf("Setting environment variable 'ow_id' to %s\n", str);
+	setenv("ow_id", str);
+
+	return 0;
+}
+U_BOOT_CMD(
+	onewire,	1,	1,	do_onewire,
+	"onewire - Read 1-write ID\n",
+	NULL
+	);
+
+
+#define CFG_I2C_EEPROM_ADDR_2	0x51	/* EEPROM CAT28WC32		*/
+#define CFG_ENV_SIZE_2	0x800	/* 2048 bytes may be used for env vars*/
+
+/*
+ * Write backplane ip-address...
+ */
+int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	bd_t *bd = gd->bd;
+	char *buf;
+	ulong crc;
+	char str[32];
+	char *ptr;
+	IPaddr_t ipaddr;
+
+	buf = malloc(CFG_ENV_SIZE_2);
+	if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
+		puts("\nError reading backplane EEPROM!\n");
+	} else {
+		crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
+		if (crc != *(ulong *)buf) {
+			printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
+			return -1;
+		}
+
+		/*
+		 * Find bp_ip
+		 */
+		ptr = strstr(buf+4, "bp_ip=");
+		if (ptr == NULL) {
+			printf("ERROR: bp_ip not found!\n");
+			return -1;
+		}
+		ptr += 6;
+		ipaddr = string_to_ip(ptr);
+
+		/*
+		 * Update whole ip-addr
+		 */
+		bd->bi_ip_addr = ipaddr;
+		sprintf(str, "%ld.%ld.%ld.%ld",
+			(bd->bi_ip_addr & 0xff000000) >> 24,
+			(bd->bi_ip_addr & 0x00ff0000) >> 16,
+			(bd->bi_ip_addr & 0x0000ff00) >> 8,
+			(bd->bi_ip_addr & 0x000000ff));
+		setenv("ipaddr", str);
+		printf("Updated ip_addr from bp_eeprom to %s!\n", str);
+	}
+
+	free(buf);
+
+	return 0;
+}
+U_BOOT_CMD(
+	getbpip,	1,	1,	do_get_bpip,
+	"getbpip - Update IP-Address with Backplane IP-Address\n",
+	NULL
+	);
+
+/*
+ * Set and print backplane ip...
+ */
+int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char *buf;
+	char str[32];
+	ulong crc;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	printf("Setting bp_ip to %s\n", argv[1]);
+	buf = malloc(CFG_ENV_SIZE_2);
+	memset(buf, 0, CFG_ENV_SIZE_2);
+	sprintf(str, "bp_ip=%s", argv[1]);
+	strcpy(buf+4, str);
+	crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
+	*(ulong *)buf = crc;
+
+	if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
+		puts("\nError writing backplane EEPROM!\n");
+	}
+
+	free(buf);
+
+	return 0;
+}
+U_BOOT_CMD(
+	setbpip,	2,	1,	do_set_bpip,
+	"setbpip - Write Backplane IP-Address\n",
+	NULL
+	);
+
+#endif /* CONFIG_CPCI405AB */
diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c
new file mode 100755
index 0000000..e766895
--- /dev/null
+++ b/board/esd/cpci405/flash.c
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long calc_size(unsigned long size)
+{
+	switch (size) {
+	case 1 << 20:
+		return 0;
+	case 2 << 20:
+		return 1;
+	case 4 << 20:
+		return 2;
+	case 8 << 20:
+		return 3;
+	case 16 << 20:
+		return 4;
+	default:
+		return 0;
+	}
+}
+
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+
+	if (size_b1) {
+		if (size_b1 < (1 << 20)) {
+			/* minimum CS size on PPC405GP is 1MB !!! */
+			size_b1 = 1 << 20;
+		}
+		base_b1 = -size_b1;
+		mtdcr (ebccfga, pb0cr);
+		pbcr = mfdcr (ebccfgd);
+		mtdcr (ebccfga, pb0cr);
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
+		mtdcr (ebccfgd, pbcr);
+#if 0 /* test-only */
+		printf("size_b1=%x base_b1=%x pb1cr = %x\n",
+		       size_b1, base_b1, pbcr); /* test-only */
+#endif
+	}
+
+	if (size_b0) {
+		if (size_b0 < (1 << 20)) {
+			/* minimum CS size on PPC405GP is 1MB !!! */
+			size_b0 = 1 << 20;
+		}
+		base_b0 = base_b1 - size_b0;
+		mtdcr (ebccfga, pb1cr);
+		pbcr = mfdcr (ebccfgd);
+		mtdcr (ebccfga, pb1cr);
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
+		mtdcr (ebccfgd, pbcr);
+#if 0 /* test-only */
+		printf("size_b0=%x base_b0=%x pb0cr = %x\n",
+		       size_b0, base_b0, pbcr); /* test-only */
+#endif
+	}
+
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+				base_b1 + size_b1 - monitor_flash_len,
+				base_b1 + size_b1 - 1, &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect (FLAG_PROTECT_CLEAR,
+				base_b0 + size_b0 - monitor_flash_len,
+				base_b0 + size_b0 - 1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/board/esd/cpci405/fpgadata_cpci405.c b/board/esd/cpci405/fpgadata_cpci405.c
new file mode 100755
index 0000000..20e61c1
--- /dev/null
+++ b/board/esd/cpci405/fpgadata_cpci405.c
@@ -0,0 +1,342 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+ 0x63,0x70,0x63,0x69,0x34,0x30,0x35,0x32,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+ 0x73,0x30,0x35,0x78,0x6c,0x76,0x71,0x31,0x30,0x30,0x00,0x63,0x00,0x0b,0x32,0x30,
+ 0x30,0x31,0x2f,0x30,0x35,0x2f,0x31,0x30,0x00,0x64,0x00,0x09,0x31,0x35,0x3a,0x31,
+ 0x35,0x3a,0x32,0x33,0x00,0x65,0xe2,0x01,0x00,0x00,0x15,0x08,0xff,0x30,0xe8,0x01,
+ 0x01,0x01,0x01,0xe7,0xe6,0x04,0x01,0x02,0x11,0x05,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x04,0x04,0x0b,0x02,0x02,0x01,0x04,0x02,0x01,0x0b,0x07,0x01,0x01,0x0d,0x03,
+ 0x05,0x09,0x03,0x05,0x03,0x05,0x03,0x0b,0x13,0x01,0x06,0xe5,0xe5,0x02,0x03,0x0c,
+ 0x01,0xe6,0x11,0x08,0x13,0x16,0x08,0x1e,0x0b,0xe5,0xe6,0x0e,0x09,0x09,0x09,0x09,
+ 0x0b,0x07,0xe6,0x08,0x02,0xe5,0x04,0x01,0xe6,0x04,0x0e,0x01,0x01,0x14,0x09,0x09,
+ 0x09,0x09,0x05,0x05,0xe5,0xe6,0x04,0x03,0x05,0xe5,0x01,0x05,0xe5,0x07,0x0c,0xe5,
+ 0x5b,0x01,0x01,0x05,0x01,0x11,0x02,0xe5,0xe5,0x48,0x13,0x1a,0x01,0xe6,0x3e,0x0b,
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+ 0x0b,0x04,0xe6,0x06,0x01,0x0c,0x01,0x03,0x01,0xe6,0xe5,0x02,0x01,0x01,0x01,0x22,
+ 0xe6,0xe5,0x0c,0x06,0x05,0x06,0x02,0x02,0x06,0x03,0x0e,0x02,0x02,0xe5,0x01,0x01,
+ 0x07,0x01,0x0a,0x1a,0xe5,0x40,0xe5,0xe5,0x19,0x01,0xe5,0x05,0x01,0xe5,0x0b,0x01,
+ 0x01,0xe5,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0xe5,0x04,
+ 0xe7,0x06,0x01,0x03,0x03,0x01,0x07,0x01,0x0b,0x01,0xe5,0x22,0x0d,0x01,0xe5,0x08,
+ 0x03,0x07,0x02,0xe5,0x18,0x01,0x0a,0x05,0xe8,0x0a,0x16,0xe5,0x21,0xe5,0x01,0x26,
+ 0x06,0x01,0x01,0xe5,0x30,0x06,0x03,0x02,0x0d,0x0b,0x24,0xe5,0x03,0x2c,0x05,0x06,
+ 0x03,0x04,0x02,0xe5,0x01,0x05,0x01,0x18,0x09,0xe8,0x04,0x05,0x07,0x0b,0x1f,0xe5,
+ 0x0f,0x06,0x03,0x1b,0x01,0x03,0xe5,0xe5,0x19,0x07,0x0b,0x09,0x03,0xe6,0x07,0x04,
+ 0x03,0x01,0x24,0x03,0x01,0x03,0x1a,0x17,0x06,0x12,0x1c,0x0a,0xe6,0xe5,0x05,0x0e,
+ 0x06,0x01,0x07,0x09,0x0d,0xe5,0x10,0x16,0x12,0xe7,0x12,0x02,0x09,0x09,0x08,0xe5,
+ 0x09,0xe5,0x08,0x04,0x2c,0xe6,0x27,0x13,0xe5,0xe6,0x05,0x33,0x02,0x09,0x01,0x05,
+ 0x01,0x09,0xe5,0x07,0x1b,0x02,0x06,0x09,0x22,0xe8,0x31,0x10,0x08,0xe5,0x07,0xe5,
+ 0x05,0x0e,0x0b,0xe5,0xe7,0x07,0x15,0x10,0x0e,0x02,0xe5,0x09,0x09,0x17,0x0a,0xe5,
+ 0x01,0xe6,0x48,0x09,0x22,0xe5,0x01,0xe6,0x01,0x01,0x46,0xe6,0x01,0x04,0x1f,0x01,
+ 0x02,0x03,0x04,0x43,0x01,0x02,0x04,0x01,0x02,0x0e,0xe5,0xe5,0xe5,0x08,0x04,0x02,
+ 0xe5,0x01,0x45,0x04,0x09,0x0e,0x02,0x01,0x0b,0x02,0xe6,0xe5,0x48,0x01,0x01,0x07,
+ 0x11,0x14,0x01,0x02,0x48,0x01,0x01,0x05,0x03,0x13,0x09,0x02,0x02,0xe6,0x4b,0x09,
+ 0x04,0x0c,0x01,0x08,0x04,0xe6,0x01,0x31,0xe5,0x19,0x09,0x05,0x0b,0x01,0x10,0xe6,
+ 0x08,0x47,0x02,0x06,0x02,0x15,0x06,0xe7,0x09,0x01,0x45,0xe5,0x07,0x1d,0x03,0xe5,
+ 0x07,0x05,0x09,0x09,0x09,0x09,0x0b,0x04,0x01,0x02,0x09,0x05,0x03,0x09,0x0d,0x01,
+ 0xe7,0x01,0x47,0x09,0x22,0x04,0xe6,0x46,0x09,0x28,0xe5,0xe6,0x42,0x06,0x02,0x07,
+ 0x01,0x20,0x03,0x01,0x43,0xe5,0x08,0x08,0xe5,0x20,0x03,0xe5,0x41,0x06,0x07,0x02,
+ 0x28,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x03,0x05,0xe5,0x01,0x05,
+ 0xe5,0x01,0x05,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe6,0xe5,0x2d,0xe5,0x12,0x13,0xe6,
+ 0x1f,0x02,0xe5,0x42,0x11,0x01,0x22,0xe5,0x01,0x43,0x13,0x21,0xe7,0xe5,0x2d,0x14,
+ 0x11,0x02,0x1c,0xe5,0x03,0x02,0x4b,0x01,0xe5,0x05,0x23,0xe7,0xe5,0x10,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0xe6,0x06,0x01,0x09,0x01,0x02,0xe5,0x02,0x01,0x04,0x02,0x01,
+ 0x07,0x01,0x07,0x01,0x01,0x03,0xe5,0x06,0x2f,0x2e,0x1c,0x02,0xe5,0x1e,0x28,0x1e,
+ 0x10,0xe6,0xe6,0x1a,0x14,0x0e,0x09,0xe5,0x2a,0x03,0x02,0xe6,0x08,0x14,0x19,0x05,
+ 0x07,0x03,0xe6,0x06,0x06,0x17,0x06,0xe7,0x3e,0x0b,0x0b,0x22,0xe9,0x07,0x09,0x09,
+ 0x10,0x09,0x04,0x01,0x04,0xe6,0x27,0x0a,0x02,0xe5,0x29,0x14,0x0a,0x2a,0x04,0x02,
+ 0xe5,0x0a,0x12,0x20,0x3a,0xe5,0xe6,0x0a,0x07,0x10,0x18,0x01,0x05,0x0b,0x08,0x19,
+ 0x06,0xe5,0xe5,0x1b,0x13,0x0e,0xe5,0x0d,0x09,0x21,0x02,0x32,0x1c,0x2a,0x01,0x01,
+ 0x0a,0x2f,0x15,0x0b,0x1c,0xe5,0xe7,0x09,0x27,0x41,0x06,0xe9,0x4f,0xe5,0xe5,0x02,
+ 0xe5,0x1c,0xe5,0x01,0x01,0x02,0x01,0x4c,0xe5,0x21,0x01,0x03,0xe5,0xe5,0x03,0x0e,
+ 0xe5,0x01,0x01,0x17,0xe5,0x01,0x01,0x1d,0x03,0x1b,0x05,0x01,0xe5,0x01,0x11,0xe5,
+ 0xe5,0xe5,0x17,0xe5,0xe5,0xe5,0x3e,0x02,0xe8,0x54,0x04,0x03,0x1c,0x02,0x02,0x18,
+ 0x1d,0x20,0x01,0xe6,0x17,0x03,0x01,0xe6,0x15,0x01,0x1b,0x01,0x1d,0x23,0xe5,0x01,
+ 0xe5,0x16,0x01,0x1b,0x01,0x22,0x1f,0x03,0x09,0x02,0x4e,0x1e,0xe8,0xe5,0x59,0x01,
+ 0x1d,0xe7,0x0d,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x03,0x05,0x09,0x0d,0x01,0x01,
+ 0xe5,0x01,0x74,0x04,0xe6,0x7a,0xe5,0xe5,0x79,0xe5,0xe6,0x53,0x03,0xe5,0x1f,0xe9,
+ 0x53,0x01,0x21,0xe5,0x01,0xe5,0x08,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x09,0xe5,0x07,0xe6,0xe5,0x04,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0x02,0x55,
+ 0x01,0x26,0x55,0x01,0x22,0x03,0x40,0x14,0x01,0x23,0x02,0x04,0x50,0x01,0x02,0x22,
+ 0xe5,0x01,0x0e,0x43,0x1b,0x0b,0xe5,0x02,0xe5,0x0b,0x01,0x07,0x01,0x07,0x01,0xe5,
+ 0x05,0x01,0x07,0x01,0x04,0x04,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x04,0xe5,0xe5,
+ 0x06,0x01,0x02,0x05,0x04,0xe5,0x53,0x01,0x27,0xe5,0x72,0x04,0xe7,0xe5,0x2f,0x0e,
+ 0xe5,0x11,0x0a,0x09,0x11,0x03,0xe5,0x1b,0x1b,0x1b,0x01,0x01,0x14,0x0e,0xe5,0x1c,
+ 0x13,0x07,0x05,0xe5,0x16,0x15,0x0b,0xe5,0x01,0xe5,0x0c,0xe5,0xe5,0x17,0x02,0x0a,
+ 0x06,0xe5,0x05,0x0d,0x1a,0x0a,0x01,0xe5,0x12,0x17,0xe5,0x11,0x0f,0x17,0x12,0x01,
+ 0xe6,0x1b,0x10,0x11,0x19,0x20,0xe5,0x01,0x1e,0x20,0x3e,0x3f,0x24,0x19,0x02,0x0a,
+ 0x01,0x30,0xe5,0xe5,0x28,0x0d,0xe5,0xe5,0x0e,0x33,0x2c,0x08,0x02,0xe6,0x0e,0x17,
+ 0x1a,0x37,0xe5,0xe6,0x02,0x0b,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe7,0x07,0xe5,0x06,
+ 0xe8,0x05,0xe7,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x0b,0xe6,0xe6,0x0f,0x09,0x09,0x07,
+ 0x01,0x09,0x09,0x01,0x05,0x01,0x01,0x07,0x01,0x09,0x07,0x01,0x01,0x0b,0xe6,0xe5,
+ 0x0e,0x0a,0x03,0x04,0xe5,0x07,0x0a,0x07,0x02,0x01,0x02,0x04,0x09,0x05,0xe5,0x01,
+ 0x04,0x04,0x10,0x01,0x11,0x4b,0x1c,0xe6,0xe5,0x18,0x09,0x04,0x06,0x07,0x01,0x09,
+ 0x09,0x09,0x09,0x09,0x02,0x0b,0x02,0xe5,0x0c,0xe6,0x05,0xe6,0x01,0x05,0xe5,0x07,
+ 0xe6,0x06,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x06,0x04,
+ 0x03,0x02,0x03,0x09,0x09,0x01,0x07,0x01,0x07,0x09,0x01,0x05,0x03,0x09,0x09,0x09,
+ 0x09,0x11,0x02,0x0e,0xe5,0x07,0x09,0x09,0xe5,0x07,0x0b,0x02,0x06,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x0e,0xe5,0x0d,0x09,0x09,0x09,0x09,0x0b,
+ 0x09,0x09,0x09,0x09,0x0f,0xe5,0x01,0x12,0x06,0x09,0xe5,0x11,0x05,0x05,0xe5,0x37,
+ 0xe5,0x0d,0x06,0x02,0x09,0x09,0x09,0x08,0x02,0x09,0x09,0x09,0x09,0x0f,0xe8,0x3e,
+ 0x1d,0x20,0x10,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x0d,0x02,0xe5,0x03,
+ 0x04,0x1f,0x33,0x20,0x3f,0x3b,0xe5,0xe5,0x17,0x1d,0x08,0x02,0x33,0x05,0xe6,0x03,
+ 0x13,0x06,0x02,0x13,0x06,0x0b,0x16,0x06,0x13,0x01,0xe5,0x03,0x4c,0x0c,0x1b,0xe5,
+ 0x01,0x17,0x08,0x14,0x08,0xe5,0x1e,0x13,0x06,0x01,0xe6,0x20,0x1d,0x34,0x06,0xe5,
+ 0xe5,0x48,0x15,0x07,0x12,0xe8,0x13,0x02,0xe5,0x04,0xe8,0x04,0x09,0x02,0xe5,0x04,
+ 0xe6,0x08,0xe6,0x06,0x09,0x02,0xe5,0x04,0xe6,0x06,0x09,0xe8,0x0d,0xe5,0x06,0xe6,
+ 0x05,0xe7,0x08,0x07,0xe6,0x05,0xe5,0x01,0xe5,0x05,0x02,0x09,0x07,0xe6,0x05,0x02,
+ 0x0e,0xe8,0x25,0x18,0x3b,0x01,0xe5,0x14,0x05,0x03,0x09,0x01,0x07,0x05,0x03,0x07,
+ 0x03,0x01,0x03,0x05,0x03,0x0d,0x01,0x03,0x0c,0x01,0xe6,0x0a,0x03,0x02,0x01,0x06,
+ 0xe5,0x07,0x02,0x03,0x03,0x01,0x07,0x08,0x0b,0x04,0x05,0x03,0x0e,0x04,0xe9,0x03,
+ 0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,
diff --git a/board/esd/cpci405/fpgadata_cpci4052.c b/board/esd/cpci405/fpgadata_cpci4052.c
new file mode 100755
index 0000000..7204028
--- /dev/null
+++ b/board/esd/cpci405/fpgadata_cpci4052.c
@@ -0,0 +1,765 @@
+  0x1f,0x8b,0x08,0x08,0xe9,0xf4,0x75,0x3e,0x00,0x03,0x63,0x70,0x63,0x69,0x34,0x30,
+  0x35,0x5f,0x32,0x5f,0x30,0x34,0x2e,0x62,0x69,0x74,0x00,0xed,0x7c,0x0f,0x74,0x14,
+  0xd7,0x79,0xef,0x37,0x77,0x66,0xc5,0x68,0x77,0xa5,0x1d,0xad,0x56,0xce,0xda,0x16,
+  0xf2,0x68,0x25,0xc8,0xa2,0xae,0xc4,0xb2,0xc2,0x58,0x96,0xc5,0x6a,0xb4,0x92,0xe9,
+  0xda,0xe0,0xb0,0x26,0x6e,0xc3,0x6b,0xfd,0x92,0xc5,0x26,0xad,0xfa,0x0e,0x71,0x85,
+  0xd3,0xe6,0xa9,0x6e,0x5f,0xdf,0xd5,0x6a,0x31,0x02,0x61,0x58,0xff,0x69,0xa3,0xb8,
+  0x24,0x59,0x88,0xda,0x28,0x2e,0xc9,0x5b,0x04,0x01,0x61,0x1c,0x7b,0x50,0x65,0x2c,
+  0x40,0x06,0x85,0xfa,0xbc,0x87,0x6d,0x6a,0x2f,0x8e,0xea,0xa7,0x60,0x99,0xca,0x40,
+  0x1d,0xf1,0xcf,0x7a,0xdf,0x9d,0x7f,0xbb,0x22,0x89,0xdb,0xd3,0xd7,0x73,0xfa,0xce,
+  0x79,0x9e,0xc4,0xc7,0xd7,0xba,0xba,0x33,0xf7,0x7e,0xf3,0xdd,0xdf,0xf7,0xfb,0x7d,
+  0xdf,0x1d,0x41,0xa1,0x6b,0x5a,0xff,0x1f,0x00,0xb7,0x0e,0x4a,0x1e,0xed,0x78,0xf4,
+  0x0f,0x96,0x06,0xef,0xfc,0x4a,0xe8,0x2b,0xc1,0xa5,0x75,0x8f,0x3d,0xba,0x1e,0x1e,
+  0x01,0x7b,0xe8,0xeb,0x4b,0xee,0xfc,0xa3,0x8d,0x4b,0x96,0x2e,0x85,0x47,0xc1,0x11,
+  0x0a,0x06,0xeb,0x17,0xe3,0xff,0x97,0xdc,0x05,0xeb,0xa1,0x70,0xc9,0x5d,0x8d,0x4b,
+  0x96,0x35,0x2e,0x0d,0xc2,0x57,0x01,0xe2,0x3d,0xb3,0x78,0xbd,0xf0,0xad,0xdf,0xfa,
+  0xbd,0x20,0x50,0x0e,0x00,0xe6,0x05,0xb9,0x38,0xfb,0x77,0x41,0x90,0x93,0x39,0xa0,
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+  0xbf,0xe4,0xf3,0xca,0x1c,0x9f,0xb7,0x96,0xa5,0x39,0xff,0xd7,0xa1,0x7c,0x58,0xf8,
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+  0x9f,0xdd,0x74,0x7d,0xe6,0xf3,0xbf,0xae,0xef,0xd7,0x5f,0xec,0x6f,0x39,0x12,0xed,
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+  0x7d,0x76,0xfd,0xff,0x72,0x69,0x71,0x92,0x68,0x71,0x52,0xfd,0x8f,0x9e,0xcb,0x67,
+  0xd7,0x67,0xd7,0x67,0xd7,0x67,0xd7,0x67,0xd7,0x67,0xd7,0x7f,0xc4,0x15,0x64,0x65,
+  0x00,0xd8,0xfb,0xb2,0xf1,0xf7,0xff,0xf9,0x20,0x28,0xf3,0x3e,0xfd,0xf7,0xb5,0xdf,
+  0xb3,0x05,0x21,0xcd,0xe5,0xc6,0xf7,0xa7,0x6e,0x9e,0xeb,0xff,0x01,0x51,0x16,0x5f,
+  0xd0,0xd5,0x60,0x00,0x00,
diff --git a/board/esd/cpci405/fpgadata_cpci405ab.c b/board/esd/cpci405/fpgadata_cpci405ab.c
new file mode 100755
index 0000000..3f78473
--- /dev/null
+++ b/board/esd/cpci405/fpgadata_cpci405ab.c
@@ -0,0 +1,1285 @@
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+  0xf8,0xe4,0x4c,0x06,0x97,0x33,0xf7,0x99,0x37,0xb6,0x64,0xac,0x68,0xec,0xcc,0xe8,
+  0xc9,0x79,0x63,0x4b,0x8f,0xbe,0x71,0xfa,0x4c,0x06,0x97,0x33,0x6d,0xae,0xe1,0xb8,
+  0x3c,0x20,0x70,0xd9,0x7f,0x15,0xc7,0xe5,0x9b,0x19,0x2e,0x3f,0x70,0xd6,0x69,0x43,
+  0xda,0x61,0x1b,0x54,0x1a,0xee,0xa9,0xbd,0x96,0xa1,0xb1,0x2b,0x87,0x99,0xe1,0xb4,
+  0x41,0xbf,0xe5,0x38,0xb0,0x09,0x46,0xa6,0xd3,0xed,0xec,0x55,0xe0,0xe8,0x33,0xc9,
+  0x70,0x3e,0xdc,0xed,0x19,0x30,0xd5,0xb4,0x0c,0xbe,0xc6,0x0e,0x73,0xc3,0xf9,0x50,
+  0xf1,0x92,0x4d,0x36,0xbc,0xa6,0xd3,0xe7,0x2f,0x6f,0x65,0xf7,0x98,0x31,0x78,0xfe,
+  0xeb,0xc3,0x20,0x8e,0xa1,0xc8,0x6e,0x4a,0xec,0x36,0x17,0xfd,0x1a,0x6e,0x78,0x7b,
+  0xed,0x36,0xee,0x76,0xb2,0x0d,0x76,0x19,0xb3,0x35,0xf7,0xba,0x30,0x37,0xa6,0x1e,
+  0xb4,0xaf,0x90,0x3f,0xfd,0xf9,0xa8,0x93,0x9f,0x4f,0xe6,0x8a,0xdd,0x1f,0x0d,0x72,
+  0x43,0xf8,0x34,0xbe,0x8f,0xcf,0x87,0x1b,0xce,0xf3,0xf9,0x3e,0x30,0x99,0x85,0x75,
+  0x9f,0x75,0xa1,0x2f,0x7b,0xce,0x4e,0x7f,0xb0,0xf1,0x7f,0xf2,0x7c,0xf8,0x7c,0x7d,
+  0xc9,0x73,0x76,0x5a,0x68,0xac,0x46,0xf7,0x65,0x1f,0x91,0xd3,0xfb,0x53,0x3e,0xb5,
+  0xb5,0x7f,0xe4,0x8f,0x3e,0xdf,0x9f,0x7a,0x9b,0xff,0xc6,0x4f,0xfd,0xd8,0xd8,0x98,
+  0x79,0x71,0xe3,0xff,0xd3,0x6d,0x48,0xf6,0x12,0x1e,0x6f,0x64,0x1a,0x89,0xa5,0x37,
+  0xf1,0x5d,0x1d,0xbf,0x06,0xff,0x0b,0x6b,0x59,0xbb,0x88,0xe1,0x7c,0xbe,0x74,0x2d,
+  0xdb,0x0d,0xbe,0x7c,0x05,0x66,0x5a,0xa9,0x99,0x25,0xac,0x4e,0x58,0xd4,0x81,0x3f,
+  0x65,0x2d,0x67,0xda,0x88,0xb5,0xfc,0x7d,0x5c,0xcb,0xd6,0x12,0x9e,0xb4,0x96,0xd5,
+  0x3f,0xb6,0x96,0x9d,0x36,0x7f,0xe4,0xf9,0x8c,0x5b,0xcb,0xc0,0xd7,0xb2,0xb5,0x84,
+  0xad,0x45,0x8d,0x46,0xaf,0xf2,0x27,0xdf,0xe7,0x4f,0xf1,0x75,0x7f,0xca,0x73,0x86,
+  0x0c,0x71,0xbe,0xc8,0xe7,0xab,0xb5,0xfc,0xff,0xbe,0x36,0xff,0xf9,0x27,0x04,0xba,
+  0x44,0xf8,0xff,0x46,0xae,0xff,0x2f,0xfe,0xd3,0xaf,0x3e,0x5f,0x7d,0xbe,0xfa,0x7c,
+  0xf5,0xf9,0xea,0xf3,0xd5,0xe7,0xab,0xcf,0x57,0x9f,0xff,0x5f,0x7c,0x78,0xbc,0x44,
+  0x78,0xbc,0x64,0xfc,0x3f,0xdd,0x97,0xaf,0x3e,0x5f,0x7d,0xbe,0xfa,0x7c,0xf5,0xf9,
+  0xea,0xf3,0xd5,0xe7,0xab,0xcf,0x57,0x9f,0xff,0xbb,0x3f,0x21,0x2e,0x0c,0x7b,0xa3,
+  0x36,0x04,0xbc,0xa8,0x2b,0x87,0xc0,0xc8,0xfb,0xd3,0xfe,0x1d,0x6f,0xef,0x0a,0x41,
+  0x42,0xca,0xdc,0xa7,0xe7,0x1f,0x27,0xf6,0xf5,0xff,0x02,0xd6,0x2c,0x67,0x26,0xbd,
+  0xa4,0x00,0x00,
diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds
new file mode 100755
index 0000000..f7a20d1
--- /dev/null
+++ b/board/esd/cpci405/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/cpci440/Makefile b/board/esd/cpci440/Makefile
new file mode 100755
index 0000000..84d44fb
--- /dev/null
+++ b/board/esd/cpci440/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o strataflash.o ../common/misc.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/cpci440/config.mk b/board/esd/cpci440/config.mk
new file mode 100755
index 0000000..8e5f63f
--- /dev/null
+++ b/board/esd/cpci440/config.mk
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x01fc0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/esd/cpci440/cpci440.c b/board/esd/cpci440/cpci440.c
new file mode 100755
index 0000000..43d8a3b
--- /dev/null
+++ b/board/esd/cpci440/cpci440.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2002
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+long int fixed_sdram( void );
+
+int board_early_init_f (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr( ebccfga, xbcfg );
+	reg = mfdcr( ebccfgd );
+	mtdcr( ebccfgd, reg | 0x04000000 );	/* Set ATC */
+
+	mtebc( pb0ap, 0x92015480 );	/* FLASH/SRAM */
+	mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */
+	/* test-only: other regs still missing... */
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr( uic0sr, 0xffffffff );    /* clear all */
+	mtdcr( uic0er, 0x00000000 );    /* disable all */
+	mtdcr( uic0cr, 0x00000009 );    /* SMI & UIC1 crit are critical */
+	mtdcr( uic0pr, 0xfffffe13 );    /* per ref-board manual */
+	mtdcr( uic0tr, 0x01c00008 );    /* per ref-board manual */
+	mtdcr( uic0vr, 0x00000001 );    /* int31 highest, base=0x000 */
+	mtdcr( uic0sr, 0xffffffff );    /* clear all */
+
+	mtdcr( uic1sr, 0xffffffff );    /* clear all */
+	mtdcr( uic1er, 0x00000000 );    /* disable all */
+	mtdcr( uic1cr, 0x00000000 );    /* all non-critical */
+	mtdcr( uic1pr, 0xffffe0ff );    /* per ref-board manual */
+	mtdcr( uic1tr, 0x00ffc000 );    /* per ref-board manual */
+	mtdcr( uic1vr, 0x00000001 );    /* int31 highest, base=0x000 */
+	mtdcr( uic1sr, 0xffffffff );    /* clear all */
+
+	return 0;
+}
+
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	get_sys_info(&sysinfo);
+
+	printf("Board: esd CPCI-440\n");
+	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
+	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
+	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
+	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
+	printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000);
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long    dram_size = 0;
+
+	dram_size = fixed_sdram();
+	return dram_size;
+}
+
+
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:    64 MB, non-ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram( void )
+{
+	uint    reg;
+
+#if 1 /* test-only */
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram( mem_uabba, 0x00000000 );   /* ubba=0 (default)             */
+	mtsdram( mem_slio,  0x00000000 );   /* rdre=0 wrre=0 rarw=0         */
+	mtsdram( mem_devopt,0x00000000 );   /* dll=0 ds=0 (normal)          */
+	mtsdram( mem_wddctr,0x40000000 );   /* wrcp=0 dcd=0                 */
+	mtsdram( mem_clktr, 0x40000000 );   /* clkp=1 (90 deg wr) dcdt=0    */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/
+	mtsdram( mem_tr0,  0x410a4012 );/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3                       */
+	mtsdram( mem_tr1,  0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram( mem_rtr,  0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB     */
+	mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM    */
+	udelay( 400 );                  /* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit           */
+	for(;;)
+	{
+		mfsdram( mem_mcsts, reg );
+		if( reg & 0x80000000 )
+			break;
+	}
+
+	return( 64 * 1024 * 1024 );      /* 64 MB                           */
+#else
+	return( 32 * 1024 * 1024 );      /* 64 MB                           */
+#endif
+}
diff --git a/board/esd/cpci440/init.S b/board/esd/cpci440/init.S
new file mode 100755
index 0000000..82f37fd
--- /dev/null
+++ b/board/esd/cpci440/init.S
@@ -0,0 +1,94 @@
+/*
+*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X )
+    tlbtab_end
diff --git a/board/esd/cpci440/strataflash.c b/board/esd/cpci440/strataflash.c
new file mode 100755
index 0000000..2f055c2
--- /dev/null
+++ b/board/esd/cpci440/strataflash.c
@@ -0,0 +1,755 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+
+#define FLASH_MAN_CFI			0x01000000
+
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+#if 0 /* test-only */
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n");
+		printf (" %08lX%5s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : " "
+			);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+		        retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+ */
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+		printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/cpci440/u-boot.lds b/board/esd/cpci440/u-boot.lds
new file mode 100755
index 0000000..57220d3
--- /dev/null
+++ b/board/esd/cpci440/u-boot.lds
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+/*  .resetvec 0x01FFFFFC :*/
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+/*  .bootpg 0x01FFF000 :*/
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/esd/cpci440/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile
new file mode 100755
index 0000000..2ca73a9
--- /dev/null
+++ b/board/esd/cpci5200/Makefile
@@ -0,0 +1,53 @@
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD  = ../common/xilinx_jtag/lenval.o \
+# 	  ../common/xilinx_jtag/micro.o \
+# 	  ../common/xilinx_jtag/ports.o
+
+# OBJS	= $(BOARD).o flash.o $(CPLD)
+OBJS	= $(BOARD).o strataflash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/esd/cpci5200/config.mk b/board/esd/cpci5200/config.mk
new file mode 100755
index 0000000..07b5de1
--- /dev/null
+++ b/board/esd/cpci5200/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFF000000   boot low for 16 MiB boards
+#	0xFF800000   boot low for  8 MiB boards
+#	0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
new file mode 100755
index 0000000..6c98f13
--- /dev/null
+++ b/board/esd/cpci5200/cpci5200.c
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * cpci5200.c - main board support/init for the esd cpci5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+
+#include "mt46v16m16-75.h"
+
+void init_ata_reset(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+long int initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_ata_reset();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd CPCI5200 (cpci5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x02000000) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CFG_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CFG_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void
+    ) {
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+	}
+}
+#endif				/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_ata_reset(void)
+{
+	debug("init_ata_reset\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+}
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	int i;
+	volatile unsigned long *ptr;
+
+	addr = simple_strtol(argv[1], NULL, 16);
+	size = simple_strtol(argv[2], NULL, 16);
+
+	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+	while (1) {
+		ptr = (volatile unsigned long *)addr;
+		for (i = 0; i < (size >> 2); i++) {
+			*ptr++ = i;
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+		putc('.');
+	}
+	return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+	   "writepci- Write some data to pcibus\n",
+	   "<addr> <size>\n" "        - Write some data to pcibus.\n");
diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h
new file mode 100755
index 0000000..22d0a55
--- /dev/null
+++ b/board/esd/cpci5200/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c
new file mode 100755
index 0000000..d76af02
--- /dev/null
+++ b/board/esd/cpci5200/strataflash.c
@@ -0,0 +1,804 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI			0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char *cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+			    uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset,
+			 uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size(ulong base, int banknum);
+static int flash_write_cfiword(flash_info_t * info, ulong dest,
+			       cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+				   ulong tout, char *prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+				 int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar *flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
+}
+
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
+{
+	uchar *addr;
+
+	addr = flash_make_addr(info, sect, offset);
+	return ((addr[(2 * info->portwidth) - 1] << 8) |
+		addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
+{
+	uchar *addr;
+
+	addr = flash_make_addr(info, sect, offset);
+	return ((addr[(2 * info->portwidth) - 1] << 24) |
+		(addr[(info->portwidth) - 1] << 16) |
+		(addr[(4 * info->portwidth) - 1] << 8) |
+		addr[(3 * info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size;
+	int i;
+	unsigned long address;
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf
+			    ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+			     i, flash_info[0].size, flash_info[i].size << 20);
+		}
+	}
+
+#if 0				/* test-only */
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	for (i = 0;
+	     flash_info[0].start[i] < CFG_MONITOR_BASE + monitor_flash_len - 1;
+	     i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if (flash_full_status_check
+			    (info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf(" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth << 3), (info->chipwidth << 3));
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	printf
+	    (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	     info->erase_blk_tout, info->write_tout, info->buffer_write_tout,
+	     info->buffer_size);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n");
+		printf(" %08lX%5s",
+		       info->start[i], info->protect[i] ? " (RO)" : " ");
+	}
+	printf("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if ((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for (i = 0; i < aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+
+		for (; (i < info->portwidth) && (cnt > 0); i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *) cp));
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while (cnt >= info->portwidth) {
+		i = info->buffer_size > cnt ? cnt : info->buffer_size;
+		if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -= i;
+	}
+#else
+	/* handle the aligned part */
+	while (cnt >= info->portwidth) {
+		cword.l = 0;
+		for (i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if ((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif				/* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i < info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, &cword, (*(uchar *) cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if (prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if ((retcode =
+	     flash_full_status_check(info, sector, info->erase_blk_tout,
+				     prot ? "protect" : "unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if (prot == 0) {
+			int i;
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout,
+			      char *prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer(0);
+	while (!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt,
+			       info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector,
+				   ulong tout, char *prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if ((retcode == ERR_OK)
+	    && !flash_isequal(info, sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,
+		       info->start[sector]);
+		if (flash_isset
+		    (info, sector, 0,
+		     FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
+			printf("Command Sequence Error.\n");
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)) {
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t * info, cfiword_t * cword, uchar c)
+{
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void *cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *) cmdbuf;
+	for (i = 0; i < info->portwidth; i++)
+		*cp++ = ((i + 1) % info->chipwidth) ? '\0' : cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset,
+			    uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+ */
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for (info->portwidth = FLASH_CFI_8BIT;
+	     info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
+		for (info->chipwidth = FLASH_CFI_BY8;
+		     info->chipwidth <= info->portwidth;
+		     info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI,
+					FLASH_CMD_CFI);
+			if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
+			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1,
+					     'R')
+			    && flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2,
+					     'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size(ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio = 0;
+	uchar num_erase_regions;
+	int erase_region_size;
+	int erase_region_count;
+
+	info->start[0] = base;
+#if 0
+	invalidate_dcache_range(base, base + 0x400);
+#endif
+	if (flash_detect_cfi(info)) {
+
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions =
+		    flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+
+		sect_cnt = 0;
+		sector = base;
+		for (i = 0; i < num_erase_regions; i++) {
+			if (i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp =
+			    flash_read_long(info, 0,
+					    FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size =
+			    (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) + 1;
+			for (j = 0; j < erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] =
+				    flash_isset(info, sect_cnt,
+						FLASH_OFFSET_PROTECT,
+						FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size =
+		    (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) *
+		    size_ratio;
+		info->buffer_size =
+		    (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout =
+		    (tmp *
+		     (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT))) /
+		    1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+#ifdef DEBUG_FLASH
+	printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth);	/* test-only */
+#endif
+#ifdef DEBUG_FLASH
+	printf("found %d erase regions\n", num_erase_regions);
+#endif
+#ifdef DEBUG_FLASH
+	printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
+#endif
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *) dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if (!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch (info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t * info, ulong addr)
+{
+	int sector;
+	for (sector = info->sector_count - 1; sector >= 0; sector--) {
+		if (addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
+				 int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *) dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if ((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					  "write to buffer")) == ERR_OK) {
+		switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar) cnt - 1);
+		while (cnt-- > 0) {
+			switch (info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0,
+				FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode =
+		    flash_full_status_check(info, sector,
+					    info->buffer_write_tout,
+					    "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif				/* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/cpci5200/u-boot.lds b/board/esd/cpci5200/u-boot.lds
new file mode 100755
index 0000000..f23432e
--- /dev/null
+++ b/board/esd/cpci5200/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/cpci750/64360.h b/board/esd/cpci750/64360.h
new file mode 100755
index 0000000..262abf3
--- /dev/null
+++ b/board/esd/cpci750/64360.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ * for cpci750 Reinhard Arlt
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * main board support/init for the cpci750.
+ */
+
+#ifndef __64360_H__
+#define __64360_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_SINGLE_CPU	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64360_H__ */
diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile
new file mode 100755
index 0000000..0486729
--- /dev/null
+++ b/board/esd/cpci750/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+SOBJS	= misc.o
+
+OBJS	= $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
+	  mv_eth.o  mpsc.o i2c.o \
+	  sdram_init.o strataflash.o ide.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/cpci750/config.mk b/board/esd/cpci750/config.mk
new file mode 100755
index 0000000..7795dfa
--- /dev/null
+++ b/board/esd/cpci750/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2004
+# Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# cpci750 board
+#
+
+TEXT_BASE = 0xfff00000
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
new file mode 100755
index 0000000..e4b062b
--- /dev/null
+++ b/board/esd/cpci750/cpci750.c
@@ -0,0 +1,885 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
+ * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
+ */
+
+/*
+ * cpci750.c - main board support/init for the esd cpci750.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+#undef	DEBUG
+/*#define	DEBUG */
+
+#ifdef CONFIG_PCI
+#define	MAP_PCI
+#endif /* of CONFIG_PCI */
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+extern void flush_data_cache (void);
+extern void invalidate_l1_instruction_cache (void);
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+void board_prebootm_init (void);
+unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+int display_mem_map (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+
+/* original ppcboot 1.1.6 source
+
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+original ppcboot 1.1.6 source end */
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
+}
+
+#ifdef CONFIG_PCI
+
+static void gt_pci_config (void)
+{
+	unsigned int stat;
+	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
+
+	/* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
+	 * config registers by writing ones to the bus and device.
+	 * We then update the Virtual register with the correct value for the bus and device.
+	 */
+	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+
+		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+
+	}
+	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
+
+		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
+		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
+			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+	}
+
+	/* Enable master */
+	PCI_MASTER_ENABLE (0, SELF);
+	PCI_MASTER_ENABLE (1, SELF);
+
+	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
+	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
+	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
+									     <<
+									     18);
+	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
+	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
+
+	/* ronen- add write to pci remap registers for 64460.
+	   in 64360 when writing to pci base go and overide remap automaticaly,
+	   in 64460 it doesn't */
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+
+	/* PCI interface settings */
+	/* Timeout set to retry forever */
+	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
+	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
+
+	/* ronen - enable only CS0 and Internal reg!! */
+	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+
+/*ronen update the pci internal registers base address.*/
+#ifdef MAP_PCI
+	for (stat = 0; stat <= PCI_HOST1; stat++)
+		pciWriteConfigReg (stat,
+				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
+				   SELF, CFG_GT_REGS);
+#endif
+
+}
+#endif
+
+/* Setup CPU interface paramaters */
+static void gt_cpu_config (void)
+{
+	cpu_t cpu = get_cpu_type ();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD (CPU_CONFIGURATION);
+
+	/* set the SINGLE_CPU bit  see MV64360 P.399 */
+#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+	tmp |= CPU_CONF_SINGLE_CPU;
+#endif
+
+	tmp &= ~CPU_CONF_AACK_DELAY_2;
+
+	tmp |= CPU_CONF_DP_VALID;
+	tmp |= CPU_CONF_AP_VALID;
+
+	tmp |= CPU_CONF_PIPELINE;
+
+	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */
+
+	/* CPU master control register */
+	tmp = GTREGREAD (CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command (603e, 750)
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+
+	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+
+	/* No PCI in first release of Port To_do: enable it. */
+#ifdef CONFIG_PCI
+	gt_pci_config ();
+#endif
+	/* mask all external interrupt sources */
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	/* new in MV6436x */
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
+	/* --------------------- */
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	/* does not exist in MV6436x
+	   GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	   GT_REG_WRITE(CPU_INT_3_MASK, 0);
+	   --------------------- */
+
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM   ????
+	 * 1 - RTC      ????
+	 * 2 - UART     ????
+	 * 3 - Flash    checked 32Bit Intel Strata
+	 * boot - BootCS checked 8Bit 29LV040B
+	 *
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+
+	memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+
+
+	/* configure device timing */
+	GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+	GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR);
+
+#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
+			      CFG_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+#endif
+
+
+	gt_cpu_config ();
+
+	/* MPP setup */
+	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	DEBUG_LED0_ON ();
+	DEBUG_LED1_ON ();
+	DEBUG_LED2_ON ();
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r ()
+{
+	icache_enable ();
+#ifdef CFG_L2
+	l2cache_enable ();
+#endif
+#ifdef CONFIG_MPSC
+
+	mpsc_sdma_init ();
+	mpsc_init2 ();
+#endif
+
+#if 0
+	/* disable the dcache and MMU */
+	dcache_lock ();
+#endif
+	return 0;
+}
+
+void after_reloc (ulong dest_addr, gd_t * gd)
+{
+
+  memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
+
+  display_mem_map ();
+  /* now, jump to the main ppcboot board init code */
+  board_init_r (gd, dest_addr);
+  /* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * right now, assume borad type. (there is just one...after all)
+ */
+
+int checkboard (void)
+{
+	int l_type = 0;
+
+	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	return (l_type);
+}
+
+/* utility functions */
+void debug_led (int led, int mode)
+{
+}
+
+int display_mem_map (void)
+{
+	int i, j;
+	unsigned int base, size, width;
+
+	/* SDRAM */
+	printf ("SD (DDR) RAM\n");
+	for (i = 0; i <= BANK3; i++) {
+		base = memoryGetBankBaseAddress (i);
+		size = memoryGetBankSize (i);
+		if (size != 0) {
+			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
+				i, base, size >> 20);
+		}
+	}
+#ifdef CONFIG_PCI
+	/* CPU's PCI windows */
+	for (i = 0; i <= PCI_HOST1; i++) {
+		printf ("\nCPU's PCI %d windows\n", i);
+		base = pciGetSpaceBase (i, PCI_IO);
+		size = pciGetSpaceSize (i, PCI_IO);
+		printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
+			size >> 20);
+		for (j = 0;
+		     j <=
+		     PCI_REGION0
+		     /*ronen currently only first PCI MEM is used 3 */ ;
+		     j++) {
+			base = pciGetSpaceBase (i, j);
+			size = pciGetSpaceSize (i, j);
+			printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
+		}
+	}
+#endif /* of CONFIG_PCI */
+	/* Devices */
+	printf ("\nDEVICES\n");
+	for (i = 0; i <= DEVICE3; i++) {
+		base = memoryGetDeviceBaseAddress (i);
+		size = memoryGetDeviceSize (i);
+		width = memoryGetDeviceWidth (i) * 8;
+		printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
+		if (i == 0)
+			printf ("\t- FLASH\n");
+		else if (i == 1)
+			printf ("\t- FLASH\n");
+		else if (i == 2)
+			printf ("\t- FLASH\n");
+		else
+			printf ("\t- RTC/REGS/CAN\n");
+	}
+
+	/* Bootrom */
+	base = memoryGetDeviceBaseAddress (BOOT_DEVICE);	/* Boot */
+	size = memoryGetDeviceSize (BOOT_DEVICE);
+	width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
+	printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\t- FLASH\n",
+		base, size >> 20, width);
+	return (0);
+}
+
+/* DRAM check routines copied from gw8260 */
+
+#if defined (CFG_DRAM_TEST)
+
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CFG_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaLL,
+	0xccccccccccccccccLL,
+	0xf0f0f0f0f0f0f0f0LL,
+	0xff00ff00ff00ff00LL,
+	0xffff0000ffff0000LL,
+	0xffffffff00000000LL,
+	0x00000000ffffffffLL,
+	0x0000ffff0000ffffLL,
+	0x00ff00ff00ff00ffLL,
+	0x0f0f0f0f0f0f0f0fLL,
+	0x3333333333333333LL,
+	0x5555555555555555LL,
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_DATA */
+
+#if defined (CFG_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_MEMTEST_START;
+	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_ADDRESS */
+
+#if defined (CFG_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_MEMTEST_START;
+	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("         ");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata    = 0;
+	int runaddress = 0;
+	int runwalk    = 0;
+
+#ifdef CFG_DRAM_TEST_DATA
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+#endif
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+	}
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		printf ("Test DATA ...  ");
+		if (mem_test_data () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		printf ("Test ADDRESS ...  ");
+		if (mem_test_address () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		printf ("Test WALKING ONEs ...  ");
+		if (mem_test_walk () == 1) {
+			printf ("failed \n");
+			return 1;
+		} else
+			printf ("ok \n");
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed\n");
+	}
+	return 0;
+
+}
+#endif /* CFG_DRAM_TEST */
+
+/* ronen - the below functions are used by the bootm function           */
+/*  - we map the base register to fbe00000 (same mapping as in the LSP) */
+/*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
+/*    the kernel data areas.                                            */
+/*  - we diable and invalidate the icache and dcache.                   */
+void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 16)
+		return;
+
+	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 16);
+
+	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
+							new_loc |
+							(INTERNAL_SPACE_DECODE)))))
+	       != temp);
+
+}
+
+void board_prebootm_init ()
+{
+
+/* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
+		GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
+
+/* Stop GigE Rx DMA engines */
+	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
+/*	GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
+/*      GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
+
+/* Relocate MV64360 internal regs */
+	my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS);
+
+	icache_disable ();
+	invalidate_l1_instruction_cache ();
+	flush_data_cache ();
+	dcache_disable ();
+}
diff --git a/board/esd/cpci750/eth.h b/board/esd/cpci750/eth.h
new file mode 100755
index 0000000..aab32d2
--- /dev/null
+++ b/board/esd/cpci750/eth.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __EVB64360_ETH_H__
+#define __EVB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+
+int db64360_eth0_poll(void);
+int db64360_eth0_transmit(unsigned int s, volatile char *p);
+void db64360_eth0_disable(void);
+bool network_start(bd_t *bis);
+
+
+#endif /* __EVB64360_ETH_H__ */
diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c
new file mode 100755
index 0000000..5b1bc01
--- /dev/null
+++ b/board/esd/cpci750/i2c.c
@@ -0,0 +1,487 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ * extra improvments by Brain Waite
+ * for cpci750 by reinhard.arlt@esd-electronics.com
+ */
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include "../../Marvell/include/mv_gen_reg.h"
+#include "../../Marvell/include/core.h"
+
+#define I2C_DELAY	    100
+#undef	DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+static void i2c_init (int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualN = 0, actualM = 0;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = CFG_TCLK;
+	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
+
+	DP (puts ("i2c_init\n"));
+/* gtI2cMasterInit */
+	for (n = 0; n < 8; n++) {
+		for (m = 0; m < 16; m++) {
+			power = 2 << n;	/* power = 2^(n+1) */
+			freq = tclk / (10 * (m + 1) * power);
+			if (i2cFreq > freq)
+				margin = i2cFreq - freq;
+			else
+				margin = freq - i2cFreq;
+			if (margin < minMargin) {
+				minMargin = margin;
+				actualN = n;
+				actualM = m;
+			}
+		}
+	}
+
+	DP (puts ("setup i2c bus\n"));
+
+	/* Setup bus */
+	/* gtI2cReset */
+	GT_REG_WRITE (I2C_SOFT_RESET, 0);
+	asm(" sync");
+	GT_REG_WRITE (I2C_CONTROL, 0);
+	asm(" sync");
+
+	DP (puts ("set baudrate\n"));
+
+	GT_REG_WRITE (I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+	asm(" sync");
+
+	DP (puts ("udelay...\n"));
+
+	udelay (I2C_DELAY);
+
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+	asm(" sync");
+}
+
+
+static uchar i2c_select_device (uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	unsigned int control;
+	int count = 0;
+
+	DP (puts ("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |=  (0x1 << 2);
+	GT_REG_WRITE (I2C_CONTROL, control);
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &control);
+	control |= (0x1 << 5);	/* generate the I2C_START_BIT */
+	GT_REG_WRITE (I2C_CONTROL, control);
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, (0x01 << 3));
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+
+	count = 0;
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	while (((status & 0xff) != 0x08) && ((status & 0xff) != 0x10)){
+		if (count > 200) {
+#ifdef DEBUG_I2C
+			printf ("Failed to set startbit: 0x%02x\n", status);
+#endif
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			asm(" sync");
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	DP (puts ("i2c_select_device:write addr byte\n"));
+
+	/* assert the address */
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	GT_REG_WRITE (I2C_DATA, data);
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, BIT3);
+	asm(" sync");
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+	count = 0;
+	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+		if (count > 200) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write address: 0x%02x\n", status);
+#endif
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		asm(" sync");
+		count++;
+	}
+
+	if (bits == 10) {
+		printf ("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar i2c_get_data (uchar * return_data, int len)
+{
+
+	unsigned int data, status;
+	int count = 0;
+
+	DP (puts ("i2c_get_data\n"));
+
+	while (len) {
+
+		RESET_REG_BITS (I2C_CONTROL, BIT3);
+		asm(" sync");
+
+		/* Get and return the data */
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x50) {
+			if (count > 20) {
+#ifdef DEBUG_I2C
+				printf ("Failed to get data len status: 0x%02x\n", status);
+#endif
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return 0;
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		GT_REG_READ (I2C_DATA, &data);
+		len--;
+		*return_data = (uchar) data;
+		return_data++;
+
+	}
+	RESET_REG_BITS (I2C_CONTROL, BIT2 | BIT3);
+	asm(" sync");
+	count = 0;
+
+	GT_REG_READ (I2C_CONTROL, &status);
+	while ((status & 0x08) != 0x08) {
+		GT_REG_READ (I2C_CONTROL, &status);
+		}
+
+	while ((status & 0xff) != 0x58) {
+		if (count > 2000) {
+			GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+			return (status);
+		}
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/* stop */
+	asm(" sync");
+	RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+	asm(" sync");
+
+	return (0);
+}
+
+
+static uchar i2c_write_data (unsigned int *data, int len)
+{
+	unsigned int status;
+	int count;
+	unsigned int temp;
+	unsigned int *temp_ptr = data;
+
+	DP (puts ("i2c_write_data\n"));
+
+	while (len) {
+		count = 0;
+		temp = (unsigned int) (*temp_ptr);
+		GT_REG_WRITE (I2C_DATA, temp);
+		asm(" sync");
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+		asm(" sync");
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			if (count > 200) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+	return (0);
+}
+
+
+static uchar i2c_write_byte (unsigned char *data, int len)
+{
+	unsigned int status;
+	int count;
+	unsigned int temp;
+	unsigned char *temp_ptr = data;
+
+	DP (puts ("i2c_write_byte\n"));
+
+	while (len) {
+		count = 0;
+		/* Set and assert the data */
+		temp = *temp_ptr;
+		GT_REG_WRITE (I2C_DATA, temp);
+		asm(" sync");
+		RESET_REG_BITS (I2C_CONTROL, (0x1 << 3));
+		asm(" sync");
+
+
+		GT_REG_READ (I2C_CONTROL, &status);
+		while ((status & 0x08) != 0x08) {
+			GT_REG_READ (I2C_CONTROL, &status);
+			}
+
+		GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			if (count > 200) {
+				GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));	/*stop */
+				asm(" sync");
+				return (status);
+			}
+			GT_REG_READ (I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+		temp_ptr++;
+	}
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit,
+		    int alen)
+{
+	uchar status;
+	unsigned int table[2];
+
+	table[1] = (offset     ) & 0x0ff;	/* low byte */
+	table[0] = (offset >> 8) & 0x0ff;	/* high byte */
+
+	DP (puts ("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device (dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+22		printf ("Failed to select device setting offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+/* check the address offset length */
+	if (alen == 0)
+		/* no address offset */
+		return (0);
+	else if (alen == 1) {
+		/* 1 byte address offset */
+		status = i2c_write_data (&offset, 1);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else if (alen == 2) {
+		/* 2 bytes address offset */
+		status = i2c_write_data (table, 2);
+		if (status) {
+#ifdef DEBUG_I2C
+			printf ("Failed to write data: 0x%02x\n", status);
+#endif
+			return status;
+		}
+	} else {
+		/* address offset unknown or not supported */
+		printf ("Address length offset %d is not supported\n", alen);
+		return 1;
+	}
+	return 0;		/* sucessful completion */
+}
+
+uchar
+i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	  int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_read\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device (dev_addr, 1, 0);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to select device for data read: 0x%02x\n",
+			status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data (data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not read: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
+
+
+void i2c_stop (void)
+{
+	GT_REG_WRITE (I2C_CONTROL, (0x1 << 4));
+	asm(" sync");
+}
+
+
+uchar
+i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
+	   int len)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_write\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_set_dev_offset (dev_addr, offset, 0, alen);	/* send the slave address + offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address & offset: 0x%02x\n",
+			status);
+#endif
+		return status;
+		}
+
+
+	status = i2c_write_byte (data, len);	/* write the data */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Data not written: 0x%02x\n", status);
+#endif
+		return status;
+		}
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;
+}
+
+
+int i2c_probe (uchar chip)
+{
+
+#ifdef DEBUG_I2C
+	unsigned int i2c_status;
+#endif
+	uchar status = 0;
+	unsigned int i2cFreq = CFG_I2C_SPEED;
+
+	DP (puts ("i2c_probe\n"));
+
+	i2c_init (i2cFreq, 0);	/* set the i2c frequency */
+
+	status = i2c_set_dev_offset (chip, 0, 0, 0);	/* send the slave address + no offset */
+	if (status) {
+#ifdef DEBUG_I2C
+		printf ("Failed to set slave address: 0x%02x\n", status);
+#endif
+		return (int) status;
+	}
+#ifdef DEBUG_I2C
+	GT_REG_READ (I2C_STATUS_BAUDE_RATE, &i2c_status);
+	printf ("address %#x returned %#x\n", chip, i2c_status);
+#endif
+	/* issue a stop bit */
+	i2c_stop ();
+	return 0;		/* successful completion */
+}
diff --git a/board/esd/cpci750/i2c.h b/board/esd/cpci750/i2c.h
new file mode 100755
index 0000000..b669ff0
--- /dev/null
+++ b/board/esd/cpci750/i2c.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
+ */
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
new file mode 100755
index 0000000..bea99ce
--- /dev/null
+++ b/board/esd/cpci750/ide.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* ide.c - ide support functions */
+
+
+#include <common.h>
+#ifdef CFG_CMD_IDE
+#include <ata.h>
+#include <ide.h>
+#include <pci.h>
+
+extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
+
+int ide_preinit (void)
+{
+	int status;
+	pci_dev_t devbusfn;
+	int l;
+
+	status = 1;
+	for (l = 0; l < CFG_IDE_MAXBUS; l++) {
+		ide_bus_offset[l] = -ATA_STATUS;
+	}
+	devbusfn = pci_find_device (0x1103, 0x0004, 0);
+	if (devbusfn != -1) {
+		status = 0;
+
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
+				       (u32 *) & ide_bus_offset[0]);
+		ide_bus_offset[0] &= 0xfffffffe;
+		ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
+		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
+				       (u32 *) & ide_bus_offset[1]);
+		ide_bus_offset[1] &= 0xfffffffe;
+		ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
+	}
+	return (status);
+}
+
+void ide_set_reset (int flag) {
+	return;
+}
+
+#endif /* of CONFIG_CMDS_IDE */
diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h
new file mode 100755
index 0000000..bca0e1f
--- /dev/null
+++ b/board/esd/cpci750/local.h
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * include/local.h - local configuration options, board specific
+ */
+
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* This tells PPCBoot that the config options are compiled in */
+/* #undef ENV_IS_EMBEDDED */
+/* Don't touch this! PPCBOOT figures this out  based on other
+ * magic. */
+
+/* Uncomment and define any of the below options */
+
+/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
+#define CONFIG_750FX       /* The 750FX doesn't support as many things in L2CR like 750CX*/
+
+/* These want string arguments */
+/* #define CONFIG_BOOTARGS */
+/* #define CONFIG_BOOTCOMMAND */
+/* #define CONFIG_RAMBOOTCOMMAND */
+/* #define CONFIG_NFSBOOTCOMMAND */
+/* #define CFG_AUTOLOAD */
+/* #define CONFIG_PREBOOT */
+
+/* These don't */
+
+/* #define CONFIG_BOOTDELAY  */
+/* #define CONFIG_BAUDRATE */
+/* #define CONFIG_LOADS_ECHO */
+/* #define CONFIG_ETHADDR */
+/* #define CONFIG_ETH2ADDR */
+/* #define CONFIG_ETH3ADDR */
+/* #define CONFIG_IPADDR */
+/* #define CONFIG_SERVERIP */
+/* #define CONFIG_ROOTPATH */
+/* #define CONFIG_GATEWAYIP */
+/* #define CONFIG_NETMASK */
+/* #define CONFIG_HOSTNAME */
+/* #define CONFIG_BOOTFILE */
+/* #define CONFIG_LOADADDR */
+
+/* these hardware addresses are pretty bogus, please change them to
+   suit your needs */
+
+/* first ethernet */
+/* #define CONFIG_ETHADDR          86:06:2d:7e:c6:53 */
+#define CONFIG_ETHADDR          64:36:00:00:00:01
+
+/* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		86:06:2d:7e:c6:54
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR		86:06:2d:7e:c6:55
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S
new file mode 100755
index 0000000..160b1d3
--- /dev/null
+++ b/board/esd/cpci750/misc.S
@@ -0,0 +1,245 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include "version.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "../../Marvell/include/mv_gen_reg.h"
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CFG_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CFG_MONITOR_LEN@h
+	ori	r8, r8, CFG_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11: gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CFG_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CFG_DFL_GT_REGS@h
+	ori	r3, r3, CFG_DFL_GT_REGS@l
+	lis	r4, CFG_GT_REGS@h
+	ori	r4, r4, CFG_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
+/*	rlwinm	r7, r4, 8, 16, 31
+	rlwinm	r7, r4, 12, 16, 31	*/ /* original */
+	rlwinm	r7, r4, 16, 16, 31
+	/* -----------------------------------------------------*/
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	lis	r3, CFG_INT_SRAM_BASE@h
+	ori	r3, r3, CFG_INT_SRAM_BASE@l
+	rlwinm  r3, r3, 16, 16, 31
+	lis	r4, CFG_GT_REGS@h
+	ori	r4, r4, CFG_GT_REGS@l
+	li	r5, INTEGRATED_SRAM_BASE_ADDR
+	stwbrx  r3, r5, r4
+
+2:	lwbrx	r6, r5, r4
+	cmp	cr0, r3, r6
+	bne	2b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0_relocated
+led_on0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC80
+	ori	r18, r18, 0x8000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_off0_relocated
+led_off0_relocated:
+	xor	r21, r21, r21
+	xor	r18, r18, r18
+	lis	r18, 0xFC81
+	ori	r18, r18, 0x4000
+/*	stw	r21, 0x0(r18)   */
+	sync
+	blr
+
+	.global led_on0
+led_on0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off0
+led_off0:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x4000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c80
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off1
+led_off1:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x8000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0x0000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
+
+	.global led_off2
+led_off2:
+	xor	r18, r18, r18
+	lis	r18, 0x1c81
+	ori	r18, r18, 0xc000
+/*	stw	r18, 0x0(r18)  */
+	sync
+	blr
diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c
new file mode 100755
index 0000000..52398b2
--- /dev/null
+++ b/board/esd/cpci750/mpsc.c
@@ -0,0 +1,1018 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+#include "mv_regs.h"
+
+#include "../../Marvell/include/memory.h"
+
+/* Define this if you wish to use the MPSC as a register based UART.
+ * This will force the serial port to not use the SDMA engine at all.
+ */
+
+#undef CONFIG_MPSC_DEBUG_PORT
+
+
+int (*mpsc_putchar) (char ch) = mpsc_putchar_early;
+char (*mpsc_getchar) (void) = mpsc_getchar_debug;
+int (*mpsc_test_char) (void) = mpsc_test_char_debug;
+
+
+static volatile unsigned int *rx_desc_base = NULL;
+static unsigned int rx_desc_index = 0;
+static volatile unsigned int *tx_desc_base = NULL;
+static unsigned int tx_desc_index = 0;
+
+/* local function declarations */
+static int galmpsc_connect (int channel, int connect);
+static int galmpsc_route_rx_clock (int channel, int brg);
+static int galmpsc_route_tx_clock (int channel, int brg);
+static int galmpsc_write_config_regs (int mpsc, int mode);
+static int galmpsc_config_channel_regs (int mpsc);
+static int galmpsc_set_char_length (int mpsc, int value);
+static int galmpsc_set_stop_bit_length (int mpsc, int value);
+static int galmpsc_set_parity (int mpsc, int value);
+static int galmpsc_enter_hunt (int mpsc);
+static int galmpsc_set_brkcnt (int mpsc, int value);
+static int galmpsc_set_tcschar (int mpsc, int value);
+static int galmpsc_set_snoop (int mpsc, int value);
+static int galmpsc_shutdown (int mpsc);
+
+static int galsdma_set_RFT (int channel);
+static int galsdma_set_SFM (int channel);
+static int galsdma_set_rxle (int channel);
+static int galsdma_set_txle (int channel);
+static int galsdma_set_burstsize (int channel, unsigned int value);
+static int galsdma_set_RC (int channel, unsigned int value);
+
+static int galbrg_set_CDV (int channel, int value);
+static int galbrg_enable (int channel);
+static int galbrg_disable (int channel);
+static int galbrg_set_clksrc (int channel, int value);
+static int galbrg_set_CUV (int channel, int value);
+
+static void galsdma_enable_rx (void);
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress,
+				  unsigned int size);
+
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+static void mpsc_debug_init (void)
+{
+
+	volatile unsigned int temp;
+
+	/* Clear the CFR  (CHR4) */
+	/* Write random 'Z' bit (bit 29) of CHR4 to enable debug uart *UNDOCUMENTED FEATURE* */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP));
+	temp &= 0xffffff00;
+	temp |= BIT29;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set the Valid bit 'V' (bit 12) and int generation bit 'INT' (bit 15) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP));
+	temp |= (BIT12 | BIT15);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+
+	/* Set int mask */
+	temp = GTREGREAD (GALMPSC_0_INT_MASK);
+	temp |= BIT6;
+	GT_REG_WRITE (GALMPSC_0_INT_MASK, temp);
+}
+#endif
+
+char mpsc_getchar_debug (void)
+{
+	volatile int temp;
+	volatile unsigned int cause;
+
+	cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	while ((cause & BIT6) == 0) {
+		cause = GTREGREAD (GALMPSC_0_INT_CAUSE);
+	}
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_10 +
+			  (CHANNEL * GALMPSC_REG_GAP));
+	/* By writing 1's to the set bits, the register is cleared */
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (CHANNEL * GALMPSC_REG_GAP),
+		      temp);
+	GT_REG_WRITE (GALMPSC_0_INT_CAUSE, cause & ~BIT6);
+	return (temp >> 16) & 0xff;
+}
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int mpsc_putchar_early (char ch)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int mpsc = CHANNEL;
+	int temp =
+		GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	galmpsc_set_tcschar (mpsc, ch);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP),
+		      temp | 0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay (MAGIC_FACTOR / gd->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int mpsc_putchar_sdma (char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset ((void *) p, 0, 8 * sizeof (unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;		/* x */
+	p[5] = (unsigned int) ch;	/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;	/* 0 */
+	p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* 4 */
+	p[2] = 0;		/* 8 */
+	p[3] = (unsigned int) &p[4];	/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int) &p[0];
+	p[11] = (unsigned int) &p[12];
+#endif
+
+	FLUSH_DCACHE (&p[0], &p[8]);
+
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &p[0]);
+
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	while (p[1] & DESC_OWNER_BIT) {
+		udelay (100);
+		INVALIDATE_DCACHE (&p[1], &p[2]);
+	}
+	return 0;
+}
+
+char mpsc_getchar_sdma (void)
+{
+	static unsigned int done = 0;
+	volatile char ch;
+	unsigned int len = 0, idx = 0, temp;
+
+	volatile unsigned int *p;
+
+
+	do {
+		p = &rx_desc_base[rx_desc_index * 8];
+
+		INVALIDATE_DCACHE (&p[0], &p[1]);
+		/* Wait for character */
+		while (p[1] & DESC_OWNER_BIT) {
+			udelay (100);
+			INVALIDATE_DCACHE (&p[0], &p[1]);
+		}
+
+		/* Handle error case */
+		if (p[1] & (1 << 15)) {
+			printf ("oops, error: %08x\n", p[1]);
+
+			temp = GTREGREAD (GALMPSC_CHANNELREG_2 +
+					  (CHANNEL * GALMPSC_REG_GAP));
+			temp |= (1 << 23);
+			GT_REG_WRITE (GALMPSC_CHANNELREG_2 +
+				      (CHANNEL * GALMPSC_REG_GAP), temp);
+
+			/* Can't poll on abort bit, so we just wait. */
+			udelay (100);
+
+			galsdma_enable_rx ();
+		}
+
+		/* Number of bytes left in this descriptor */
+		len = p[0] & 0xffff;
+
+		if (len) {
+			/* Where to look */
+			idx = 5;
+			if (done > 3)
+				idx = 4;
+			if (done > 7)
+				idx = 7;
+			if (done > 11)
+				idx = 6;
+
+			INVALIDATE_DCACHE (&p[idx], &p[idx + 1]);
+			ch = p[idx] & 0xff;
+			done++;
+		}
+
+		if (done < len) {
+			/* this descriptor has more bytes still
+			 * shift down the char we just read, and leave the
+			 * buffer in place for the next time around
+			 */
+			p[idx] = p[idx] >> 8;
+			FLUSH_DCACHE (&p[idx], &p[idx + 1]);
+		}
+
+		if (done == len) {
+			/* nothing left in this descriptor.
+			 * go to next one
+			 */
+			p[1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+			p[0] = 0x00100000;
+			FLUSH_DCACHE (&p[0], &p[1]);
+			/* Next descriptor */
+			rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+			done = 0;
+		}
+	} while (len == 0);	/* galileo bug.. len might be zero */
+
+	return ch;
+}
+
+
+int mpsc_test_char_debug (void)
+{
+	if ((GTREGREAD (GALMPSC_0_INT_CAUSE) & BIT6) == 0)
+		return 0;
+	else {
+		return 1;
+	}
+}
+
+
+int mpsc_test_char_sdma (void)
+{
+	volatile unsigned int *p = &rx_desc_base[rx_desc_index * 8];
+
+	INVALIDATE_DCACHE (&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER_BIT)
+		return 0;
+	else
+		return 1;
+}
+
+int mpsc_init (int baud)
+{
+	/* BRG CONFIG */
+	galbrg_set_baudrate (CHANNEL, baud);
+	galbrg_set_clksrc (CHANNEL, 8);	/* set source=Tclk */
+	galbrg_set_CUV (CHANNEL, 0);	/* set up CountUpValue */
+	galbrg_enable (CHANNEL);	/* Enable BRG */
+
+	/* Set up clock routing */
+	galmpsc_connect (CHANNEL, GALMPSC_CONNECT);	/* connect it */
+
+	galmpsc_route_rx_clock (CHANNEL, CHANNEL);	/* chosse BRG0 for Rx */
+	galmpsc_route_tx_clock (CHANNEL, CHANNEL);	/* chose BRG0 for Tx */
+
+	/* reset MPSC state */
+	galmpsc_shutdown (CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize (CHANNEL, L1_CACHE_BYTES / 8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle (CHANNEL);
+	galsdma_set_rxle (CHANNEL);
+	galsdma_set_RC (CHANNEL, 0xf);
+	galsdma_set_SFM (CHANNEL);
+	galsdma_set_RFT (CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs (CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs (CHANNEL);
+	galmpsc_set_char_length (CHANNEL, GALMPSC_CHAR_LENGTH_8);	/* 8 */
+	galmpsc_set_parity (CHANNEL, GALMPSC_PARITY_NONE);	/* N */
+	galmpsc_set_stop_bit_length (CHANNEL, GALMPSC_STOP_BITS_1);	/* 1 */
+
+#ifdef CONFIG_MPSC_DEBUG_PORT
+	mpsc_debug_init ();
+#endif
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop (CHANNEL, 0);	/* disable snoop */
+#else
+	galmpsc_set_snoop (CHANNEL, 1);	/* enable snoop */
+#endif
+
+	return 0;
+}
+
+
+void mpsc_sdma_init (void)
+{
+/* Setup SDMA channel0 SDMA_CONFIG_REG*/
+	GT_REG_WRITE (SDMA_CONFIG_REG (0), 0x000020ff);
+
+/*  Enable MPSC-Window0 for DRAM Bank0   */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_0_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK0)) != true)
+		printf ("%s: SDMA_Window0 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window1    */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_1_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_1_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window1 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window2 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_2_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_2_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window2 memory setup failed !!! \n",
+			__FUNCTION__);
+
+
+/*  Disable MPSC-Window3 */
+	if (galsdma_set_mem_space (MV64360_CUNIT_BASE_ADDR_WIN_3_BIT,
+				   MV64360_SDMA_DRAM_CS_0_TARGET,
+				   0,
+				   memoryGetBankBaseAddress
+				   (CS_3_LOW_DECODE_ADDRESS),
+				   memoryGetBankSize (BANK3)) != true)
+		printf ("%s: SDMA_Window3 memory setup failed !!! \n",
+			__FUNCTION__);
+
+/*  Setup MPSC0 access mode Window0 full access */
+	GT_SET_REG_BITS (MPSC0_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/*  Setup MPSC1 access mode Window1 full access */
+	GT_SET_REG_BITS (MPSC1_ACCESS_PROTECTION_REG,
+			 (MV64360_SDMA_WIN_ACCESS_FULL <<
+			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
+
+/* Setup MPSC internal address space base address 	*/
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+
+/* no high address remap*/
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
+	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG1, 0x00);
+
+/* clear interrupt cause register for MPSC (fault register)*/
+	GT_REG_WRITE (CUNIT_INTERRUPT_CAUSE_REG, 0x00);
+}
+
+
+void mpsc_init2 (void)
+{
+	int i;
+
+#ifndef CONFIG_MPSC_DEBUG_PORT
+	mpsc_putchar = mpsc_putchar_sdma;
+	mpsc_getchar = mpsc_getchar_sdma;
+	mpsc_test_char = mpsc_test_char_sdma;
+#endif
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *) malloc (((RX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int) rx_desc_base + 32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset ((void *) rx_desc_base, 0,
+		(RX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i * 8 + 3] = (unsigned int) &rx_desc_base[i * 8 + 4];	/* Buffer */
+		rx_desc_base[i * 8 + 2] = (unsigned int) &rx_desc_base[(i + 1) * 8];	/* Next descriptor */
+		rx_desc_base[i * 8 + 1] = DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;	/* Command & control */
+		rx_desc_base[i * 8] = 0x00100000;
+	}
+	rx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &rx_desc_base[0];
+
+	FLUSH_DCACHE (&rx_desc_base[0], &rx_desc_base[RX_DESC * 8]);
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR + (CHANNEL * GALSDMA_REG_DIFF),
+		      (unsigned int) &rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *) malloc (((TX_DESC + 1) * 8) *
+						sizeof (unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int) tx_desc_base + 32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset ((void *) tx_desc_base, 0,
+		(TX_DESC * 8) * sizeof (unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i * 8 + 5] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 4] = (unsigned int) 0x23232323;
+		tx_desc_base[i * 8 + 3] =
+			(unsigned int) &tx_desc_base[i * 8 + 4];
+		tx_desc_base[i * 8 + 2] =
+			(unsigned int) &tx_desc_base[(i + 1) * 8];
+		tx_desc_base[i * 8 + 1] =
+			DESC_OWNER_BIT | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i * 8] = 0x00010001;
+	}
+	tx_desc_base[(i - 1) * 8 + 2] = (unsigned int) &tx_desc_base[0];
+
+	FLUSH_DCACHE (&tx_desc_base[0], &tx_desc_base[TX_DESC * 8]);
+
+	udelay (100);
+
+	galsdma_enable_rx ();
+
+	return;
+}
+
+int galbrg_set_baudrate (int channel, int rate)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int clock;
+
+	galbrg_disable (channel);	/*ok */
+
+#ifdef ZUMA_NTL
+	/* from tclk */
+	clock = (CFG_TCLK / (16 * rate)) - 1;
+#else
+	clock = (CFG_TCLK / (16 * rate)) - 1;
+#endif
+
+	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
+
+	galbrg_enable (channel);
+
+	gd->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int galbrg_set_CDV (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_enable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x00010000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_disable (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galbrg_set_clksrc (int channel, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp &= 0xFFC3FFFF;	/* Bit 18 - 21 (MV 64260 18-22) */
+	temp |= (value << 18);
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+	return 0;
+}
+
+static int galbrg_set_CUV (int channel, int value)
+{
+	/* set CountUpValue */
+	GT_REG_WRITE (GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int galbrg_reset (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE (GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int galsdma_set_RFT (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_SFM (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_rxle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_txle (int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_RC (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF),
+		      temp);
+
+	return 0;
+}
+
+static int galsdma_set_burstsize (int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALSDMA_0_CONF_REG + (channel * GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	case 8:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x3 << 12)));
+		break;
+
+	case 4:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x2 << 12)));
+		break;
+
+	case 2:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x1 << 12)));
+		break;
+
+	case 1:
+		GT_REG_WRITE (GALSDMA_0_CONF_REG +
+			      (channel * GALSDMA_REG_DIFF),
+			      (temp | (0x0 << 12)));
+		break;
+
+	default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int galmpsc_connect (int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE (GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_rx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_RxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_RxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_route_tx_clock (int channel, int brg)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_TxC_ROUTE);
+
+	if (channel == 0) {
+		temp &= ~0x0000000F;
+		temp |= brg;
+	} else {
+		temp &= ~0x00000F00;
+		temp |= (brg << 8);
+	}
+
+	GT_REG_WRITE (GALMPSC_TxC_ROUTE, temp);
+
+	return 0;
+}
+
+static int galmpsc_write_config_regs (int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE (GALMPSC_MCONF_LOW + (mpsc * GALMPSC_REG_GAP),
+			      0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE (GALMPSC_MCONF_HIGH + (mpsc * GALMPSC_REG_GAP),
+			      0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int galmpsc_config_channel_regs (int mpsc)
+{
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_3 + (mpsc * GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_4 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_5 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_6 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_7 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_8 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_9 + (mpsc * GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_10 + (mpsc * GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt (mpsc, 0x3);
+	galmpsc_set_tcschar (mpsc, 0xab);
+
+	return 0;
+}
+
+static int galmpsc_set_brkcnt (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_tcschar (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_1 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_char_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_stop_bit_length (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP));
+	temp &= 0xFFFFBFFF;
+	temp |= (value << 14);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_set_parity (int mpsc, int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	return 0;
+}
+
+static int galmpsc_enter_hunt (int mpsc)
+{
+	int temp;
+
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= 0x80000000;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	while (GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP)) &
+	       MPSC_ENTER_HUNT) {
+		udelay (1);
+	}
+	return 0;
+}
+
+
+static int galmpsc_shutdown (int mpsc)
+{
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP), temp);
+
+	GT_REG_WRITE (GALSDMA_0_COM_REG, 0);
+	GT_REG_WRITE (GALSDMA_0_COM_REG, SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE (GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE (GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE (GALMPSC_PROTOCONF_REG + (mpsc * GALMPSC_REG_GAP), 0);
+
+	udelay (100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE (GALSDMA_0_CONF_REG, 0x000000fc);
+
+	udelay (100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE (GALSDMA_0_CUR_RX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_CUR_TX_PTR, 0);
+	GT_REG_WRITE (GALSDMA_0_FIR_TX_PTR, 0);
+
+	udelay (100);
+
+	return 0;
+}
+
+static void galsdma_enable_rx (void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE (GALSDMA_0_COM_REG + (CHANNEL * GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt (CHANNEL);
+}
+
+static int galmpsc_set_snoop (int mpsc, int value)
+{
+	int reg =
+		mpsc ? MPSC_1_ADDRESS_CONTROL_LOW :
+		MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp = GTREGREAD (reg);
+
+	if (value)
+		temp |= (1 << 6) | (1 << 14) | (1 << 22) | (1 << 30);
+	else
+		temp &= ~((1 << 6) | (1 << 14) | (1 << 22) | (1 << 30));
+	GT_REG_WRITE (reg, temp);
+	return 0;
+}
+
+/*******************************************************************************
+* galsdma_set_mem_space - Set MV64360 IDMA memory decoding map.
+*
+* DESCRIPTION:
+*       the MV64360 SDMA has its own address decoding map that is de-coupled
+*       from the CPU interface address decoding windows. The SDMA channels
+*       share four address windows. Each region can be individually configured
+*       by this function by associating it to a target interface and setting
+*       base and size values.
+*
+*      NOTE!!!
+*       The size must be in 64Kbyte granularity.
+*       The base address must be aligned to the size.
+*       The size must be a series of 1s followed by a series of zeros
+*
+* OUTPUT:
+*       None.
+*
+* RETURN:
+*       True for success, false otherwise.
+*
+*******************************************************************************/
+
+static int galsdma_set_mem_space (unsigned int memSpace,
+				  unsigned int memSpaceTarget,
+				  unsigned int memSpaceAttr,
+				  unsigned int baseAddress, unsigned int size)
+{
+	unsigned int temp;
+
+	if (size == 0) {
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+		return true;
+	}
+
+	/* The base address must be aligned to the size.  */
+	if (baseAddress % size != 0) {
+		return false;
+	}
+	if (size < 0x10000) {
+		return false;
+	}
+
+	/* Align size and base to 64K */
+	baseAddress &= 0xffff0000;
+	size &= 0xffff0000;
+	temp = size >> 16;
+
+	/* Checking that the size is a sequence of '1' followed by a
+	   sequence of '0' starting from LSB to MSB. */
+	while ((temp > 0) && (temp & 0x1)) {
+		temp = temp >> 1;
+	}
+
+	if (temp != 0) {
+		GT_REG_WRITE (MV64360_CUNIT_BASE_ADDR_REG0 + memSpace * 8,
+			      (baseAddress | memSpaceTarget | memSpaceAttr));
+		GT_REG_WRITE ((MV64360_CUNIT_SIZE0 + memSpace * 8),
+			      (size - 1) & 0xffff0000);
+		GT_RESET_REG_BITS (MV64360_CUNIT_BASE_ADDR_ENABLE_REG,
+				   1 << memSpace);
+	} else {
+		/* An invalid size was specified */
+		return false;
+	}
+	return true;
+}
diff --git a/board/esd/cpci750/mpsc.h b/board/esd/cpci750/mpsc.h
new file mode 100755
index 0000000..a03d1cc
--- /dev/null
+++ b/board/esd/cpci750/mpsc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
+ *
+  ************************************************************************/
+
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include "../../Marvell/include/mv_gen_reg.h"
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_sdma_init(void);
+void mpsc_init2(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+char mpsc_getchar_debug(void);
+int mpsc_test_char_debug(void);
+
+int mpsc_test_char_sdma(void);
+
+extern int (*mpsc_putchar)(char ch);
+extern char (*mpsc_getchar)(void);
+extern int (*mpsc_test_char)(void);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER_BIT  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT 		  (1 << 15)
+#define SDMA_TX_ABORT 		  (1 << 31)
+#define MPSC_TX_ABORT 		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+#define GALMPSC_0_INT_CAUSE        0xb804
+#define GALMPSC_0_INT_MASK         0xb884
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c
new file mode 100755
index 0000000..be176dc
--- /dev/null
+++ b/board/esd/cpci750/mv_eth.c
@@ -0,0 +1,3184 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.c - header file for the polled mode GT ethernet driver
+ */
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+
+#include "mv_eth.h"
+
+/* enable Debug outputs */
+
+#undef DEBUG_MV_ETH
+
+#ifdef DEBUG_MV_ETH
+#define DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#undef MV64360_CHECKSUM_OFFLOAD
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+/* Definition for configuring driver */
+/* #define UPDATE_STATS_BY_SOFTWARE */
+#undef MV64360_RX_QUEUE_FILL_ON_TASK
+
+
+/* Constants */
+#define MAGIC_ETH_RUNNING		8031971
+#define MV64360_INTERNAL_SRAM_SIZE                      _256K
+#define EXTRA_BYTES 32
+#define WRAP       ETH_HLEN + 2 + 4 + 16
+#define BUFFER_MTU dev->mtu + WRAP
+#define INT_CAUSE_UNMASK_ALL		0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
+#ifdef MV64360_RX_FILL_ON_TASK
+#define INT_CAUSE_MASK_ALL		0x00000000
+#define INT_CAUSE_CHECK_BITS		INT_CAUSE_UNMASK_ALL
+#define INT_CAUSE_CHECK_BITS_EXT	INT_CAUSE_UNMASK_ALL_EXT
+#endif
+
+/* Read/Write to/from MV64360 internal registers */
+#define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
+#define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
+#define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
+#define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
+
+/* Static function declarations */
+static int mv64360_eth_real_open (struct eth_device *eth);
+static int mv64360_eth_real_stop (struct eth_device *eth);
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
+						       *dev);
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
+static void mv64360_eth_update_stat (struct eth_device *dev);
+bool db64360_eth_start (struct eth_device *eth);
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset);
+int mv64360_eth_receive (struct eth_device *dev);
+
+int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+static void mv64360_eth_print_stat (struct eth_device *dev);
+#endif
+/* Processes a received packet */
+extern void NetReceive (volatile uchar *, int);
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/*************************************************
+ *Helper functions - used inside the driver only *
+ *************************************************/
+#ifdef DEBUG_MV_ETH
+void print_globals (struct eth_device *dev)
+{
+	printf ("Ethernet PRINT_Globals-Debug function\n");
+	printf ("Base Address for ETH_PORT_INFO:	%08x\n",
+		(unsigned int) dev->priv);
+	printf ("Base Address for mv64360_eth_priv:	%08x\n",
+		(unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
+				 port_private));
+
+	printf ("GT Internal Base Address:	%08x\n",
+		INTERNAL_REG_BASE_ADDR);
+	printf ("Base Address for TX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
+	printf ("Base Address for RX-DESCs:	%08x	Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
+	printf ("Base Address for RX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_rx_buffer_base[0],
+		(MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
+	printf ("Base Address for TX-Buffer:	%08x	allocated Bytes %d\n",
+		(unsigned int) ((ETH_PORT_INFO *) dev->priv)->
+		p_tx_buffer_base[0],
+		(MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
+}
+#endif
+
+#define my_cpu_to_le32(x) my_le32_to_cpu((x))
+
+unsigned long my_le32_to_cpu (unsigned long x)
+{
+	return (((x & 0x000000ffU) << 24) |
+		((x & 0x0000ff00U) << 8) |
+		((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
+}
+
+
+/**********************************************************************
+ * mv64360_eth_print_phy_status
+ *
+ * Prints gigabit ethenret phy status
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_phy_status (struct eth_device *dev)
+{
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	unsigned int port_status, phy_reg_data;
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		printf ("Ethernet port changed link status to DOWN\n");
+	} else {
+		port_status =
+			MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+		printf ("Ethernet status port %d: Link up", port_num);
+		printf (", %s",
+			(port_status & BIT2) ? "Full Duplex" : "Half Duplex");
+		if (port_status & BIT4)
+			printf (", Speed 1 Gbps");
+		else
+			printf (", %s",
+				(port_status & BIT5) ? "Speed 100 Mbps" :
+				"Speed 10 Mbps");
+		printf ("\n");
+	}
+}
+
+/**********************************************************************
+ * u-boot entry functions for mv64360_eth
+ *
+ **********************************************************************/
+int db64360_eth_probe (struct eth_device *dev)
+{
+	return ((int) db64360_eth_start (dev));
+}
+
+int db64360_eth_poll (struct eth_device *dev)
+{
+	return mv64360_eth_receive (dev);
+}
+
+int db64360_eth_transmit (struct eth_device *dev, volatile void *packet,
+			  int length)
+{
+	mv64360_eth_xmit (dev, packet, length);
+	return 0;
+}
+
+void db64360_eth_disable (struct eth_device *dev)
+{
+	mv64360_eth_stop (dev);
+}
+
+
+void mv6436x_eth_initialize (bd_t * bis)
+{
+	struct eth_device *dev;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+	for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
+		dev = calloc (sizeof (*dev), 1);
+		if (!dev) {
+			printf ("%s: mv_enet%d allocation failure, %s\n",
+				__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf (dev->name, "mv_enet%d", devnum);
+
+#ifdef DEBUG
+		printf ("Initializing %s\n", dev->name);
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_r (s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		/* ronen - set the MAC addr in the HW */
+		eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
+
+		dev->init = (void *) db64360_eth_probe;
+		dev->halt = (void *) ethernet_phy_reset;
+		dev->send = (void *) db64360_eth_transmit;
+		dev->recv = (void *) db64360_eth_poll;
+
+		ethernet_private =
+			calloc (sizeof (*ethernet_private), 1);
+		dev->priv = (void *) ethernet_private;
+		if (!ethernet_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Private Device Structure");
+			free (dev);
+			return;
+		}
+		/* start with an zeroed ETH_PORT_INFO */
+		memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
+		memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+		/* set pointer to memory for stats data structure etc... */
+		port_private =
+			calloc (sizeof (*ethernet_private), 1);
+		ethernet_private->port_private = (void *)port_private;
+		if (!port_private) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Port Private Device Structure");
+
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+
+		port_private->stats =
+			calloc (sizeof (struct net_device_stats), 1);
+		if (!port_private->stats) {
+			printf ("%s: %s allocation failure, %s\n",
+				__FUNCTION__, dev->name,
+				"Net stat Structure");
+
+			free (port_private);
+			free (ethernet_private);
+			free (dev);
+			return;
+		}
+		memset (ethernet_private->port_private, 0,
+			sizeof (struct mv64360_eth_priv));
+		switch (devnum) {
+		case 0:
+			ethernet_private->port_num = ETH_0;
+			break;
+		case 1:
+			ethernet_private->port_num = ETH_1;
+			break;
+		case 2:
+			ethernet_private->port_num = ETH_2;
+			break;
+		default:
+			printf ("Invalid device number %d\n", devnum);
+			break;
+		};
+
+		port_private->port_num = devnum;
+		/*
+		 * Read MIB counter on the GT in order to reset them,
+		 * then zero all the stats fields in memory
+		 */
+		mv64360_eth_update_stat (dev);
+		memset (port_private->stats, 0,
+			sizeof (struct net_device_stats));
+		/* Extract the MAC address from the environment */
+		switch (devnum) {
+		case 0:
+			s = "ethaddr";
+			break;
+
+		case 1:
+			s = "eth1addr";
+			break;
+
+		case 2:
+			s = "eth2addr";
+			break;
+
+		default:	/* this should never happen */
+			printf ("%s: Invalid device number %d\n",
+				__FUNCTION__, devnum);
+			return;
+		}
+
+		temp = getenv_r (s, buf, sizeof (buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s);
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+
+		DP (printf ("Allocating descriptor and buffer rings\n"));
+
+		ethernet_private->p_rx_desc_area_base[0] =
+			(ETH_RX_DESC *) memalign (16,
+						  RX_DESC_ALIGNED_SIZE *
+						  MV64360_RX_QUEUE_SIZE + 1);
+		ethernet_private->p_tx_desc_area_base[0] =
+			(ETH_TX_DESC *) memalign (16,
+						  TX_DESC_ALIGNED_SIZE *
+						  MV64360_TX_QUEUE_SIZE + 1);
+
+		ethernet_private->p_rx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+		ethernet_private->p_tx_buffer_base[0] =
+			(char *) memalign (16,
+					   MV64360_RX_QUEUE_SIZE *
+					   MV64360_TX_BUFFER_SIZE + 1);
+
+#ifdef DEBUG_MV_ETH
+		/* DEBUG OUTPUT prints adresses of globals */
+		print_globals (dev);
+#endif
+		eth_register (dev);
+
+	}
+	DP (printf ("%s: exit\n", __FUNCTION__));
+
+}
+
+/**********************************************************************
+ * mv64360_eth_open
+ *
+ * This function is called when openning the network device. The function
+ * should initialize all the hardware, initialize cyclic Rx/Tx
+ * descriptors chain and buffers and allocate an IRQ to the network
+ * device.
+ *
+ * Input : a pointer to the network device structure
+ * / / ronen - changed the output to match  net/eth.c needs
+ * Output : nonzero of success , zero if fails.
+ * under construction
+ **********************************************************************/
+
+int mv64360_eth_open (struct eth_device *dev)
+{
+	return (mv64360_eth_real_open (dev));
+}
+
+/* Helper function for mv64360_eth_open */
+static int mv64360_eth_real_open (struct eth_device *dev)
+{
+
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	u32 port_status, phy_reg_data;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	/* ronen - when we update the MAC env params we only update dev->enetaddr
+	   see ./net/eth.c eth_set_enetaddr() */
+	memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
+
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Clear the ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+
+	/* Unmask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL);
+
+	/* Unmask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
+		      INT_CAUSE_UNMASK_ALL_EXT);
+
+	/* Set phy address of the port */
+	ethernet_private->port_phy_addr = 0x8 + port_num;
+
+	/* Activate the DMA channels etc */
+	eth_port_init (ethernet_private);
+
+
+	/* "Allocate" setup TX rings */
+
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
+		size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE);	/*size = no of DESCs times DESC-size */
+		ethernet_private->tx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
+			0, ethernet_private->tx_desc_area_size[queue]);
+
+		/* initialize tx desc ring with low level driver */
+		if (ether_init_tx_desc_ring
+		    (ethernet_private, ETH_Q0,
+		     port_private->tx_ring_size[queue],
+		     MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		     (unsigned int) ethernet_private->
+		     p_tx_desc_area_base[queue],
+		     (unsigned int) ethernet_private->
+		     p_tx_buffer_base[queue]) == false)
+			printf ("### Error initializing TX Ring\n");
+	}
+
+	/* "Allocate" setup RX rings */
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		unsigned int size;
+
+		/* Meantime RX Ring are fixed - but must be configurable by user */
+		port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
+		size = (port_private->rx_ring_size[queue] *
+			RX_DESC_ALIGNED_SIZE);
+		ethernet_private->rx_desc_area_size[queue] = size;
+
+		/* first clear desc area completely */
+		memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
+			0, ethernet_private->rx_desc_area_size[queue]);
+		if ((ether_init_rx_desc_ring
+		     (ethernet_private, ETH_Q0,
+		      port_private->rx_ring_size[queue],
+		      MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
+		      (unsigned int) ethernet_private->
+		      p_rx_desc_area_base[queue],
+		      (unsigned int) ethernet_private->
+		      p_rx_buffer_base[queue])) == false)
+			printf ("### Error initializing RX Ring\n");
+	}
+
+	eth_port_start (ethernet_private);
+
+	/* Set maximum receive buffer to 9700 bytes */
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
+		      (0x5 << 17) |
+		      (MV_REG_READ
+		       (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
+		       & 0xfff1ffff));
+
+	/*
+	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+	 * disable the leaky bucket mechanism .
+	 */
+
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
+	port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
+
+	/* Check Link status on phy */
+	eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+	if (!(phy_reg_data & 0x20)) {
+		/* Reset PHY */
+		if ((ethernet_phy_reset (port_num)) != true) {
+			printf ("$$ Warnning: No link on port %d \n",
+				port_num);
+			return 0;
+		} else {
+			eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
+			if (!(phy_reg_data & 0x20)) {
+				printf ("### Error: Phy is not active\n");
+				return 0;
+			}
+		}
+	} else {
+		mv64360_eth_print_phy_status (dev);
+	}
+	port_private->eth_running = MAGIC_ETH_RUNNING;
+	return 1;
+}
+
+
+static int mv64360_eth_free_tx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Stop Tx Queues */
+	MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free TX rings */
+	DP (printf ("Clearing previously allocated TX queues... "));
+	for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
+		/* Free on TX rings */
+		for (p_tx_curr_desc =
+		     ethernet_private->p_tx_desc_area_base[queue];
+		     ((unsigned int) p_tx_curr_desc <= (unsigned int)
+		      ethernet_private->p_tx_desc_area_base[queue] +
+		      ethernet_private->tx_desc_area_size[queue]);
+		     p_tx_curr_desc =
+		     (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
+				      TX_DESC_ALIGNED_SIZE)) {
+			/* this is inside for loop */
+			if (p_tx_curr_desc->return_info != 0) {
+				p_tx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+static int mv64360_eth_free_rx_rings (struct eth_device *dev)
+{
+	unsigned int queue;
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	/* Stop RX Queues */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
+		      0x0000ff00);
+
+	/* Free RX rings */
+	DP (printf ("Clearing previously allocated RX queues... "));
+	for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
+		/* Free preallocated skb's on RX rings */
+		for (p_rx_curr_desc =
+		     ethernet_private->p_rx_desc_area_base[queue];
+		     (((unsigned int) p_rx_curr_desc <
+		       ((unsigned int) ethernet_private->
+			p_rx_desc_area_base[queue] +
+			ethernet_private->rx_desc_area_size[queue])));
+		     p_rx_curr_desc =
+		     (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
+				      RX_DESC_ALIGNED_SIZE)) {
+			if (p_rx_curr_desc->return_info != 0) {
+				p_rx_curr_desc->return_info = 0;
+				DP (printf ("freed\n"));
+			}
+		}
+		DP (printf ("Done\n"));
+	}
+	return 0;
+}
+
+/**********************************************************************
+ * mv64360_eth_stop
+ *
+ * This function is used when closing the network device.
+ * It updates the hardware,
+ * release all memory that holds buffers and descriptors and release the IRQ.
+ * Input : a pointer to the device structure
+ * Output : zero if success , nonzero if fails
+ *********************************************************************/
+
+int mv64360_eth_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	/* Disable all gigE address decoder */
+	MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
+	DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
+	mv64360_eth_real_stop (dev);
+
+	return 0;
+};
+
+/* Helper function for mv64360_eth_stop */
+
+static int mv64360_eth_real_stop (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+
+	mv64360_eth_free_tx_rings (dev);
+	mv64360_eth_free_rx_rings (dev);
+
+	eth_port_reset (ethernet_private->port_num);
+	/* Disable ethernet port interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
+	/* Mask RX buffer and TX end interrupt */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
+	/* Mask phy and link status changes interrupts */
+	MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
+	MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
+			   BIT0 << port_num);
+	/* Print Network statistics */
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+	/*
+	 * Print statistics (only if ethernet is running),
+	 * then zero all the stats fields in memory
+	 */
+	if (port_private->eth_running == MAGIC_ETH_RUNNING) {
+		port_private->eth_running = 0;
+		mv64360_eth_print_stat (dev);
+	}
+	memset (port_private->stats, 0, sizeof (struct net_device_stats));
+#endif
+	DP (printf ("\nEthernet stopped ... \n"));
+	return 0;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_start_xmit
+ *
+ * This function is queues a packet in the Tx descriptor for
+ * required port.
+ *
+ * Input : skb - a pointer to socket buffer
+ *         dev - a pointer to the required port
+ *
+ * Output : zero upon success
+ **********************************************************************/
+
+int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
+		      int dataSize)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	ETH_FUNC_RET_STATUS status;
+	struct net_device_stats *stats;
+	ETH_FUNC_RET_STATUS release_result;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	stats = port_private->stats;
+
+	/* Update packet info data structure */
+	pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC;	/* DMA owned, first last */
+	pkt_info.byte_cnt = dataSize;
+	pkt_info.buf_ptr = (unsigned int) dataPtr;
+
+	status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
+	if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
+		printf ("Error on transmitting packet ..");
+		if (status == ETH_QUEUE_FULL)
+			printf ("ETH Queue is full. \n");
+		if (status == ETH_QUEUE_LAST_RESOURCE)
+			printf ("ETH Queue: using last available resource. \n");
+		goto error;
+	}
+
+	/* Update statistics and start of transmittion time */
+	stats->tx_bytes += dataSize;
+	stats->tx_packets++;
+
+	/* Check if packet(s) is(are) transmitted correctly (release everything) */
+	do {
+		release_result =
+			eth_tx_return_desc (ethernet_private, ETH_Q0,
+					    &pkt_info);
+		switch (release_result) {
+		case ETH_OK:
+			DP (printf ("descriptor released\n"));
+			if (pkt_info.cmd_sts & BIT0) {
+				printf ("Error in TX\n");
+				stats->tx_errors++;
+
+			}
+			break;
+		case ETH_RETRY:
+			DP (printf ("transmission still in process\n"));
+			break;
+
+		case ETH_ERROR:
+			printf ("routine can not access Tx desc ring\n");
+			break;
+
+		case ETH_END_OF_JOB:
+			DP (printf ("the routine has nothing to release\n"));
+			break;
+		default:	/* should not happen */
+			break;
+		}
+	} while (release_result == ETH_OK);
+
+
+	return 0;		/* success */
+      error:
+	return 1;		/* Failed - higher layers will free the skb */
+}
+
+/**********************************************************************
+ * mv64360_eth_receive
+ *
+ * This function is forward packets that are received from the port's
+ * queues toward kernel core or FastRoute them to another interface.
+ *
+ * Input : dev - a pointer to the required interface
+ *         max - maximum number to receive (0 means unlimted)
+ *
+ * Output : number of served packets
+ **********************************************************************/
+
+int mv64360_eth_receive (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+	PKT_INFO pkt_info;
+	struct net_device_stats *stats;
+
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
+		ETH_OK)) {
+
+#ifdef DEBUG_MV_ETH
+		if (pkt_info.byte_cnt != 0) {
+			printf ("%s: Received %d byte Packet @ 0x%x\n",
+				__FUNCTION__, pkt_info.byte_cnt,
+				pkt_info.buf_ptr);
+		}
+#endif
+		/* Update statistics. Note byte count includes 4 byte CRC count */
+		stats->rx_packets++;
+		stats->rx_bytes += pkt_info.byte_cnt;
+
+		/*
+		 * In case received a packet without first / last bits on OR the error
+		 * summary bit is on, the packets needs to be dropeed.
+		 */
+		if (((pkt_info.
+		      cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
+		     (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
+		    || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
+			stats->rx_dropped++;
+
+			printf ("Received packet spread on multiple descriptors\n");
+
+			/* Is this caused by an error ? */
+			if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
+				stats->rx_errors++;
+			}
+
+			/* free these descriptors again without forwarding them to the higher layers */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+			/* /free these descriptors again */
+		} else {
+
+/* !!! call higher layer processing */
+#ifdef DEBUG_MV_ETH
+			printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
+#endif
+			/* let the upper layer handle the packet */
+			NetReceive ((uchar *) pkt_info.buf_ptr,
+				    (int) pkt_info.byte_cnt);
+
+/* **************************************************************** */
+/* free descriptor  */
+			pkt_info.buf_ptr &= ~0x7;	/* realign buffer again */
+			pkt_info.byte_cnt = 0x0000;	/* Reset Byte count */
+			DP (printf
+			    ("RX: pkt_info.buf_ptr =	%x\n",
+			     pkt_info.buf_ptr));
+			if (eth_rx_return_buff
+			    (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
+				printf ("Error while returning the RX Desc to Ring\n");
+			} else {
+				DP (printf ("RX Desc returned to Ring\n"));
+			}
+
+/* **************************************************************** */
+
+		}
+	}
+	mv64360_eth_get_stats (dev);	/* update statistics */
+	return 1;
+}
+
+/**********************************************************************
+ * mv64360_eth_get_stats
+ *
+ * Returns a pointer to the interface statistics.
+ *
+ * Input : dev - a pointer to the required interface
+ *
+ * Output : a pointer to the interface's statistics
+ **********************************************************************/
+
+static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+
+	mv64360_eth_update_stat (dev);
+
+	return port_private->stats;
+}
+
+
+/**********************************************************************
+ * mv64360_eth_update_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_update_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+	volatile unsigned int dummy;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	stats->rx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_RECEIVED);
+	stats->tx_packets += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_FRAMES_SENT);
+	stats->rx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
+	/*
+	 * Ideally this should be as follows -
+	 *
+	 *   stats->rx_bytes   += stats->rx_bytes +
+	 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
+	 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
+	 *
+	 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
+	 * is just a dummy read for proper work of the GigE port
+	 */
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
+	stats->tx_bytes += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_LOW);
+	dummy = eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_GOOD_OCTETS_SENT_HIGH);
+	stats->rx_errors += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MAC_RECEIVE_ERROR);
+
+	/* Rx dropped is for received packet with CRC error */
+	stats->rx_dropped +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_BAD_CRC_EVENT);
+	stats->multicast += (unsigned long)
+		eth_read_mib_counter (ethernet_private->port_num,
+				      ETH_MIB_MULTICAST_FRAMES_RECEIVED);
+	stats->collisions +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_COLLISION) +
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_LATE_COLLISION);
+	/* detailed rx errors */
+	stats->rx_length_errors +=
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_UNDERSIZE_RECEIVED)
+		+
+		(unsigned long) eth_read_mib_counter (ethernet_private->
+						      port_num,
+						      ETH_MIB_OVERSIZE_RECEIVED);
+	/* detailed tx errors */
+}
+
+#ifndef  UPDATE_STATS_BY_SOFTWARE
+/**********************************************************************
+ * mv64360_eth_print_stat
+ *
+ * Update the statistics structure in the private data structure
+ *
+ * Input : pointer to ethernet interface network device structure
+ * Output : N/A
+ **********************************************************************/
+
+static void mv64360_eth_print_stat (struct eth_device *dev)
+{
+	ETH_PORT_INFO *ethernet_private;
+	struct mv64360_eth_priv *port_private;
+	struct net_device_stats *stats;
+	unsigned int port_num;
+
+	ethernet_private = (ETH_PORT_INFO *) dev->priv;
+	port_private =
+		(struct mv64360_eth_priv *) ethernet_private->port_private;
+	port_num = port_private->port_num;
+	stats = port_private->stats;
+
+	/* These are false updates */
+	printf ("\n### Network statistics: ###\n");
+	printf ("--------------------------\n");
+	printf (" Packets received:		%ld\n", stats->rx_packets);
+	printf (" Packets send:			%ld\n", stats->tx_packets);
+	printf (" Received bytes:		%ld\n", stats->rx_bytes);
+	printf (" Send bytes:			%ld\n", stats->tx_bytes);
+	if (stats->rx_errors != 0)
+		printf (" Rx Errors:			%ld\n",
+			stats->rx_errors);
+	if (stats->rx_dropped != 0)
+		printf (" Rx dropped (CRC Errors):	%ld\n",
+			stats->rx_dropped);
+	if (stats->multicast != 0)
+		printf (" Rx mulicast frames:		%ld\n",
+			stats->multicast);
+	if (stats->collisions != 0)
+		printf (" No. of collisions:		%ld\n",
+			stats->collisions);
+	if (stats->rx_length_errors != 0)
+		printf (" Rx length errors:		%ld\n",
+			stats->rx_length_errors);
+}
+#endif
+
+/**************************************************************************
+ *network_start - Network Kick Off Routine UBoot
+ *Inputs :
+ *Outputs :
+ **************************************************************************/
+
+bool db64360_eth_start (struct eth_device *dev)
+{
+	return (mv64360_eth_open (dev));	/* calls real open */
+}
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.   *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+/*
+ * based on Linux code
+ * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ */
+
+/********************************************************************************
+ * Marvell's Gigabit Ethernet controller low level driver
+ *
+ * DESCRIPTION:
+ *       This file introduce low level API to Marvell's Gigabit Ethernet
+ *		controller. This Gigabit Ethernet Controller driver API controls
+ *		1) Operations (i.e. port init, start, reset etc').
+ *		2) Data flow (i.e. port send, receive etc').
+ *		Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
+ *		struct.
+ *		This struct includes user configuration information as well as
+ *		driver internal data needed for its operations.
+ *
+ *		Supported Features:
+ *		- This low level driver is OS independent. Allocating memory for
+ *		  the descriptor rings and buffers are not within the scope of
+ *		  this driver.
+ *		- The user is free from Rx/Tx queue managing.
+ *		- This low level driver introduce functionality API that enable
+ *		  the to operate Marvell's Gigabit Ethernet Controller in a
+ *		  convenient way.
+ *		- Simple Gigabit Ethernet port operation API.
+ *		- Simple Gigabit Ethernet port data flow API.
+ *		- Data flow and operation API support per queue functionality.
+ *		- Support cached descriptors for better performance.
+ *		- Enable access to all four DRAM banks and internal SRAM memory
+ *		  spaces.
+ *		- PHY access and control API.
+ *		- Port control register configuration API.
+ *		- Full control over Unicast and Multicast MAC configurations.
+ *
+ *		Operation flow:
+ *
+ *		Initialization phase
+ *		This phase complete the initialization of the ETH_PORT_INFO
+ *		struct.
+ *		User information regarding port configuration has to be set
+ *		prior to calling the port initialization routine. For example,
+ *		the user has to assign the port_phy_addr field which is board
+ *		depended parameter.
+ *		In this phase any port Tx/Rx activity is halted, MIB counters
+ *		are cleared, PHY address is set according to user parameter and
+ *		access to DRAM and internal SRAM memory spaces.
+ *
+ *		Driver ring initialization
+ *		Allocating memory for the descriptor rings and buffers is not
+ *		within the scope of this driver. Thus, the user is required to
+ *		allocate memory for the descriptors ring and buffers. Those
+ *		memory parameters are used by the Rx and Tx ring initialization
+ *		routines in order to curve the descriptor linked list in a form
+ *		of a ring.
+ *		Note: Pay special attention to alignment issues when using
+ *		cached descriptors/buffers. In this phase the driver store
+ *		information in the ETH_PORT_INFO struct regarding each queue
+ *		ring.
+ *
+ *		Driver start
+ *		This phase prepares the Ethernet port for Rx and Tx activity.
+ *		It uses the information stored in the ETH_PORT_INFO struct to
+ *		initialize the various port registers.
+ *
+ *		Data flow:
+ *		All packet references to/from the driver are done using PKT_INFO
+ *		struct.
+ *		This struct is a unified struct used with Rx and Tx operations.
+ *		This way the user is not required to be familiar with neither
+ *		Tx nor Rx descriptors structures.
+ *		The driver's descriptors rings are management by indexes.
+ *		Those indexes controls the ring resources and used to indicate
+ *		a SW resource error:
+ *		'current'
+ *		This index points to the current available resource for use. For
+ *		example in Rx process this index will point to the descriptor
+ *		that will be passed to the user upon calling the receive routine.
+ *		In Tx process, this index will point to the descriptor
+ *		that will be assigned with the user packet info and transmitted.
+ *		'used'
+ *		This index points to the descriptor that need to restore its
+ *		resources. For example in Rx process, using the Rx buffer return
+ *		API will attach the buffer returned in packet info to the
+ *		descriptor pointed by 'used'. In Tx process, using the Tx
+ *		descriptor return will merely return the user packet info with
+ *		the command status of  the transmitted buffer pointed by the
+ *		'used' index. Nevertheless, it is essential to use this routine
+ *		to update the 'used' index.
+ *		'first'
+ *		This index supports Tx Scatter-Gather. It points to the first
+ *		descriptor of a packet assembled of multiple buffers. For example
+ *		when in middle of Such packet we have a Tx resource error the
+ *		'curr' index get the value of 'first' to indicate that the ring
+ *		returned to its state before trying to transmit this packet.
+ *
+ *		Receive operation:
+ *		The eth_port_receive API set the packet information struct,
+ *		passed by the caller, with received information from the
+ *		'current' SDMA descriptor.
+ *		It is the user responsibility to return this resource back
+ *		to the Rx descriptor ring to enable the reuse of this source.
+ *		Return Rx resource is done using the eth_rx_return_buff API.
+ *
+ *		Transmit operation:
+ *		The eth_port_send API supports Scatter-Gather which enables to
+ *		send a packet spanned over multiple buffers. This means that
+ *		for each packet info structure given by the user and put into
+ *		the Tx descriptors ring, will be transmitted only if the 'LAST'
+ *		bit will be set in the packet info command status field. This
+ *		API also consider restriction regarding buffer alignments and
+ *		sizes.
+ *		The user must return a Tx resource after ensuring the buffer
+ *		has been transmitted to enable the Tx ring indexes to update.
+ *
+ *		BOARD LAYOUT
+ *		This device is on-board.  No jumper diagram is necessary.
+ *
+ *		EXTERNAL INTERFACE
+ *
+ *       Prior to calling the initialization routine eth_port_init() the user
+ *	 must set the following fields under ETH_PORT_INFO struct:
+ *       port_num             User Ethernet port number.
+ *       port_phy_addr		    User PHY address of Ethernet port.
+ *       port_mac_addr[6]	    User defined port MAC address.
+ *       port_config          User port configuration value.
+ *       port_config_extend    User port config extend value.
+ *       port_sdma_config      User port SDMA config value.
+ *       port_serial_control   User port serial control value.
+ *       *port_virt_to_phys ()  User function to cast virtual addr to CPU bus addr.
+ *       *port_private        User scratch pad for user specific data structures.
+ *
+ *       This driver introduce a set of default values:
+ *       PORT_CONFIG_VALUE           Default port configuration value
+ *       PORT_CONFIG_EXTEND_VALUE    Default port extend configuration value
+ *       PORT_SDMA_CONFIG_VALUE      Default sdma control value
+ *       PORT_SERIAL_CONTROL_VALUE   Default port serial control value
+ *
+ *		This driver data flow is done using the PKT_INFO struct which is
+ *		a unified struct for Rx and Tx operations:
+ *		byte_cnt	Tx/Rx descriptor buffer byte count.
+ *		l4i_chk		CPU provided TCP Checksum. For Tx operation only.
+ *		cmd_sts		Tx/Rx descriptor command status.
+ *		buf_ptr		Tx/Rx descriptor buffer pointer.
+ *		return_info	Tx/Rx user resource return information.
+ *
+ *
+ *		EXTERNAL SUPPORT REQUIREMENTS
+ *
+ *		This driver requires the following external support:
+ *
+ *		D_CACHE_FLUSH_LINE (address, address offset)
+ *
+ *		This macro applies assembly code to flush and invalidate cache
+ *		line.
+ *		address        - address base.
+ *		address offset - address offset
+ *
+ *
+ *		CPU_PIPE_FLUSH
+ *
+ *		This macro applies assembly code to flush the CPU pipeline.
+ *
+ *******************************************************************************/
+/* includes */
+
+/* defines */
+/* SDMA command macros */
+#define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
+
+#define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
+ MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
+ (1 << (8 + tx_queue)))
+
+#define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
+
+#define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
+MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
+
+#define CURR_RFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
+
+#define CURR_RFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_RFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
+
+#define USED_RFD_SET(p_used_desc, queue)\
+(p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
+
+
+#define CURR_TFD_GET(p_curr_desc, queue) \
+ ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
+
+#define CURR_TFD_SET(p_curr_desc, queue) \
+ (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
+
+#define USED_TFD_GET(p_used_desc, queue) \
+ ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
+
+#define USED_TFD_SET(p_used_desc, queue) \
+ (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
+
+#define FIRST_TFD_GET(p_first_desc, queue) \
+ ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
+
+#define FIRST_TFD_SET(p_first_desc, queue) \
+ (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
+
+
+/* Macros that save access to desc in order to find next desc pointer  */
+#define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
+
+#define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
+
+#define LINK_UP_TIMEOUT		100000
+#define PHY_BUSY_TIMEOUT    10000000
+
+/* locals */
+
+/* PHY routines */
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
+static int ethernet_phy_get (ETH_PORT eth_port_num);
+
+/* Ethernet Port routines */
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param);
+static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option);
+#if 0				/* FIXME */
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option);
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option);
+#endif
+
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count);
+
+void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
+
+
+typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
+u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_dram_bank_size (MEMORY_BANK bank)
+{
+	u32 result = 0;
+	u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
+
+	if (enable & (1 << bank))
+		return 0;
+	if (bank == BANK0)
+		result = MV_REG_READ (MV64360_CS_0_SIZE);
+	if (bank == BANK1)
+		result = MV_REG_READ (MV64360_CS_1_SIZE);
+	if (bank == BANK2)
+		result = MV_REG_READ (MV64360_CS_2_SIZE);
+	if (bank == BANK3)
+		result = MV_REG_READ (MV64360_CS_3_SIZE);
+	result += 1;
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+u32 mv_get_internal_sram_base (void)
+{
+	u32 result;
+
+	result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
+	result &= 0x0000ffff;
+	result = result << 16;
+	return result;
+}
+
+/*******************************************************************************
+* eth_port_init - Initialize the Ethernet port driver
+*
+* DESCRIPTION:
+*       This function prepares the ethernet port to start its activity:
+*       1) Completes the ethernet port driver struct initialization toward port
+*           start routine.
+*       2) Resets the device to a quiescent state in case of warm reboot.
+*       3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
+*       4) Clean MAC tables. The reset status of those tables is unknown.
+*       5) Set PHY address.
+*       Note: Call this routine prior to eth_port_start routine and after setting
+*       user values in the user fields of Ethernet port control struct (i.e.
+*       port_phy_addr).
+*
+* INPUT:
+*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       See description.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	ETH_WIN_PARAM win_param;
+
+	p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
+	p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
+	p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
+	p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
+
+	p_eth_port_ctrl->port_rx_queue_command = 0;
+	p_eth_port_ctrl->port_tx_queue_command = 0;
+
+	/* Zero out SW structs */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->rx_resource_err[queue] = false;
+	}
+
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
+		p_eth_port_ctrl->tx_resource_err[queue] = false;
+	}
+
+	eth_port_reset (p_eth_port_ctrl->port_num);
+
+	/* Set access parameters for DRAM bank 0 */
+	win_param.win = ETH_WIN0;	/* Use Ethernet window 0 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR  */
+	win_param.attributes = EBAR_ATTR_DRAM_CS0;	/* Enable DRAM bank   */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
+	win_param.size = mv_get_dram_bank_size (BANK0);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 1 */
+	win_param.win = ETH_WIN1;	/* Use Ethernet window 1 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS1;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
+	win_param.size = mv_get_dram_bank_size (BANK1);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 2 */
+	win_param.win = ETH_WIN2;	/* Use Ethernet window 2 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS2;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
+	win_param.size = mv_get_dram_bank_size (BANK2);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for DRAM bank 3 */
+	win_param.win = ETH_WIN3;	/* Use Ethernet window 3 */
+	win_param.target = ETH_TARGET_DRAM;	/* Window target - DDR */
+	win_param.attributes = EBAR_ATTR_DRAM_CS3;	/* Enable DRAM bank */
+#ifndef CONFIG_NOT_COHERENT_CACHE
+	win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
+#endif
+	win_param.high_addr = 0;
+	/* Get bank base */
+	win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
+	win_param.size = mv_get_dram_bank_size (BANK3);	/* Get bank size */
+	if (win_param.size == 0)
+		win_param.enable = 0;
+	else
+		win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	/* Set access parameters for Internal SRAM */
+	win_param.win = ETH_WIN4;	/* Use Ethernet window 0 */
+	win_param.target = EBAR_TARGET_CBS;	/* Target - Internal SRAM */
+	win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
+	win_param.high_addr = 0;
+	win_param.base_addr = mv_get_internal_sram_base ();	/* Get base addr */
+	win_param.size = MV64360_INTERNAL_SRAM_SIZE;	/* Get bank size */
+	win_param.enable = 1;	/* Enable the access */
+	win_param.access_ctrl = EWIN_ACCESS_FULL;	/* Enable full access */
+
+	/* Set the access control for address window (EPAPR) READ & WRITE */
+	eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
+
+	eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
+
+	ethernet_phy_set (p_eth_port_ctrl->port_num,
+			  p_eth_port_ctrl->port_phy_addr);
+
+	return;
+
+}
+
+/*******************************************************************************
+* eth_port_start - Start the Ethernet port activity.
+*
+* DESCRIPTION:
+*       This routine prepares the Ethernet port for Rx and Tx activity:
+*       1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
+*           has been initialized a descriptor's ring (using ether_init_tx_desc_ring
+*           for Tx and ether_init_rx_desc_ring for Rx)
+*       2. Initialize and enable the Ethernet configuration port by writing to
+*           the port's configuration and command registers.
+*       3. Initialize and enable the SDMA by writing to the SDMA's
+*    configuration and command registers.
+*       After completing these steps, the ethernet port SDMA can starts to
+*       perform Rx and Tx activities.
+*
+*       Note: Each Rx and Tx queue descriptor's list must be initialized prior
+*       to calling this function (use ether_init_tx_desc_ring for Tx queues and
+*       ether_init_rx_desc_ring for Rx queues).
+*
+* INPUT:
+*       ETH_PORT_INFO 	*p_eth_port_ctrl       Ethernet port control struct
+*
+* OUTPUT:
+*       Ethernet port is ready to receive and transmit.
+*
+* RETURN:
+*       false if the port PHY is not up.
+*       true otherwise.
+*
+*******************************************************************************/
+static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
+{
+	int queue;
+	volatile ETH_TX_DESC *p_tx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	unsigned int phy_reg_data;
+	ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
+
+
+	/* Assignment of Tx CTRP of given queue */
+	for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
+		CURR_TFD_GET (p_tx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_tx_curr_desc));
+
+	}
+
+	/* Assignment of Rx CRDP of given queue */
+	for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
+		CURR_RFD_GET (p_rx_curr_desc, queue);
+		MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
+			       (eth_port_num)
+			       + (4 * queue)),
+			      ((unsigned int) p_rx_curr_desc));
+
+		if (p_rx_curr_desc != NULL)
+			/* Add the assigned Ethernet address to the port's address table */
+			eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
+					      p_eth_port_ctrl->port_mac_addr,
+					      queue);
+	}
+
+	/* Assign port configuration and command. */
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_config_extend);
+
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      p_eth_port_ctrl->port_serial_control);
+
+	MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+			 ETH_SERIAL_PORT_ENABLE);
+
+	/* Assign port SDMA configuration */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      p_eth_port_ctrl->port_sdma_config);
+
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
+		      (eth_port_num), 0x3fffffff);
+	MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
+		      (eth_port_num), 0x03fffcff);
+	/* Turn off the port/queue bandwidth limitation */
+	MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
+
+	/* Enable port Rx. */
+	MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
+		      p_eth_port_ctrl->port_rx_queue_command);
+
+	/* Check if link is up */
+	eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+	if (!(phy_reg_data & 0x20))
+		return false;
+
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr_set - This function Set the port Unicast address.
+*
+* DESCRIPTION:
+*		This function Set the port Ethernet MAC address.
+*
+* INPUT:
+*	ETH_PORT eth_port_num     Port number.
+*	char *        p_addr		Address to be set
+*	ETH_QUEUE 	  queue		Rx queue number for this MAC address.
+*
+* OUTPUT:
+*	Set MAC address low and high registers. also calls eth_port_uc_addr()
+*       To set the unicast table with the proper information.
+*
+* RETURN:
+*	N/A.
+*
+*******************************************************************************/
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr, ETH_QUEUE queue)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+
+	mac_l = (p_addr[4] << 8) | (p_addr[5]);
+	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
+		(p_addr[2] << 8) | (p_addr[3] << 0);
+
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
+	MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
+
+	/* Accept frames of this address */
+	eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
+
+	return;
+}
+
+/*******************************************************************************
+* eth_port_uc_addr - This function Set the port unicast address table
+*
+* DESCRIPTION:
+*	This function locates the proper entry in the Unicast table for the
+*	specified MAC nibble and sets its properties according to function
+*	parameters.
+*
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char uc_nibble		Unicast MAC Address last nibble.
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	This function add/removes MAC addresses from the port unicast address
+*	table.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_uc_addr (ETH_PORT eth_port_num,
+			      unsigned char uc_nibble,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int unicast_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the Unicast table entry */
+	uc_nibble = (0xf & uc_nibble);
+	tbl_offset = (uc_nibble / 4) * 4;	/* Register offset from unicast table base */
+	reg_offset = uc_nibble % 4;	/* Entry offset within the above register */
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified unicast DA table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at unicast DA filter table entry */
+		unicast_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+				      (eth_port_num)
+				      + tbl_offset));
+
+		unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num)
+			       + tbl_offset), unicast_reg);
+
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+#if 0				/* FIXME */
+/*******************************************************************************
+* eth_port_mc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This API controls the MV device MAC multicast support.
+*	The MV device supports multicast using two tables:
+*	1) Special Multicast Table for MAC addresses of the form
+*	   0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	   The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	   Table entries in the DA-Filter table.
+*	   In this case, the function calls eth_port_smc_addr() routine to set the
+*	   Special Multicast Table.
+*	2) Other Multicast Table for multicast of another type. A CRC-8bit
+*	   is used as an index to the Other Multicast Table entries in the
+*	   DA-Filter table.
+*	   In this case, the function calculates the CRC-8bit value and calls
+*	   eth_port_omc_addr() routine to set the Other Multicast Table.
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char 	*p_addr		Unicast MAC Address.
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if add_address_table_entry( ) failed.
+*
+*******************************************************************************/
+static void eth_port_mc_addr (ETH_PORT eth_port_num,
+			      unsigned char *p_addr,
+			      ETH_QUEUE queue, int option)
+{
+	unsigned int mac_h;
+	unsigned int mac_l;
+	unsigned char crc_result = 0;
+	int mac_array[48];
+	int crc[8];
+	int i;
+
+
+	if ((p_addr[0] == 0x01) &&
+	    (p_addr[1] == 0x00) &&
+	    (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
+
+		eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
+	else {
+		/* Calculate CRC-8 out of the given address */
+		mac_h = (p_addr[0] << 8) | (p_addr[1]);
+		mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
+			(p_addr[4] << 8) | (p_addr[5] << 0);
+
+		for (i = 0; i < 32; i++)
+			mac_array[i] = (mac_l >> i) & 0x1;
+		for (i = 32; i < 48; i++)
+			mac_array[i] = (mac_h >> (i - 32)) & 0x1;
+
+
+		crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
+			mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
+			mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
+			mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
+			mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
+			mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[0];
+
+		crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
+			mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
+			mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
+			mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
+			mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
+			mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
+			mac_array[0];
+
+		crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
+			mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
+			mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
+			mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
+			mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
+			mac_array[2] ^ mac_array[1] ^ mac_array[0];
+
+		crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
+			mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
+			mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
+			mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
+			mac_array[2] ^ mac_array[1];
+
+		crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
+			mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
+			mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
+			mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
+			mac_array[2];
+
+		crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
+			mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
+			mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
+			mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
+			mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
+			mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
+			mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
+			mac_array[3];
+
+		crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
+			mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
+			mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
+			mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
+			mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
+			mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
+			mac_array[6] ^ mac_array[5] ^ mac_array[4];
+
+		crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
+			mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
+			mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
+			mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
+			mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
+			mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
+			mac_array[6] ^ mac_array[5];
+
+		for (i = 0; i < 8; i++)
+			crc_result = crc_result | (crc[i] << i);
+
+		eth_port_omc_addr (eth_port_num, crc_result, queue, option);
+	}
+	return;
+}
+
+/*******************************************************************************
+* eth_port_smc_addr - Special Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device special MAC multicast support.
+*	The Special Multicast Table for MAC addresses supports MAC of the form
+*	0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
+*	The MAC DA[7:0] bits are used as a pointer to the Special Multicast
+*	Table entries in the DA-Filter table.
+*	This function set the Special Multicast Table appropriate entry
+*	according to the argument given.
+*
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char 	mc_byte		Multicast addr last byte (MAC DA[7:0] bits).
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_smc_addr (ETH_PORT eth_port_num,
+			       unsigned char mc_byte,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int smc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the SMC table entry */
+	tbl_offset = (mc_byte / 4) * 4;	/* Register offset from SMC table base */
+	reg_offset = mc_byte % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Special DA table entry */
+		smc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+
+/*******************************************************************************
+* eth_port_omc_addr - Multicast address settings.
+*
+* DESCRIPTION:
+*	This routine controls the MV device Other MAC multicast support.
+*	The Other Multicast Table is used for multicast of another type.
+*	A CRC-8bit is used as an index to the Other Multicast Table entries
+*	in the DA-Filter table.
+*	The function gets the CRC-8bit value from the calling routine and
+*      set the Other Multicast Table appropriate entry according to the
+*	CRC-8 argument given.
+*
+* INPUT:
+*	ETH_PORT 	eth_port_num      Port number.
+*	unsigned char 	  crc8		A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
+*	ETH_QUEUE 		 queue		Rx queue number for this MAC address.
+*	int 			option      0 = Add, 1 = remove address.
+*
+* OUTPUT:
+*	See description.
+*
+* RETURN:
+*	true is output succeeded.
+*	false if option parameter is invalid.
+*
+*******************************************************************************/
+static bool eth_port_omc_addr (ETH_PORT eth_port_num,
+			       unsigned char crc8,
+			       ETH_QUEUE queue, int option)
+{
+	unsigned int omc_table_reg;
+	unsigned int tbl_offset;
+	unsigned int reg_offset;
+
+	/* Locate the OMC table entry */
+	tbl_offset = (crc8 / 4) * 4;	/* Register offset from OMC table base */
+	reg_offset = crc8 % 4;	/* Entry offset within the above register */
+	queue &= 0x7;
+
+	switch (option) {
+	case REJECT_MAC_ADDR:
+		/* Clear accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg &= (0x0E << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	case ACCEPT_MAC_ADDR:
+		/* Set accepts frame bit at specified Other DA table entry */
+		omc_table_reg =
+			MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
+		omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
+
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
+		break;
+
+	default:
+		return false;
+	}
+	return true;
+}
+#endif
+
+/*******************************************************************************
+* eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+*
+* DESCRIPTION:
+*       Go through all the DA filter tables (Unicast, Special Multicast & Other
+*       Multicast) and set each entry to 0.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Multicast and Unicast packets are rejected.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
+{
+	int table_index;
+
+	/* Clear DA filter unicast table (Ex_dFUT) */
+	for (table_index = 0; table_index <= 0xC; table_index += 4)
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
+			       (eth_port_num) + table_index), 0);
+
+	for (table_index = 0; table_index <= 0xFC; table_index += 4) {
+		/* Clear DA filter special multicast table (Ex_dFSMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+		/* Clear DA filter other multicast table (Ex_dFOMT) */
+		MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
+	}
+}
+
+/*******************************************************************************
+* eth_clear_mib_counters - Clear all MIB counters
+*
+* DESCRIPTION:
+*       This function clears all MIB counters of a specific ethernet port.
+*       A read from the MIB counter will reset the counter.
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       After reading all MIB counters, the counters resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+static void eth_clear_mib_counters (ETH_PORT eth_port_num)
+{
+	int i;
+	unsigned int dummy;
+
+	/* Perform dummy reads from MIB counters */
+	for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
+	     i += 4)
+		dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE
+				      (eth_port_num) + i));
+
+	return;
+}
+
+/*******************************************************************************
+* eth_read_mib_counter - Read a MIB counter
+*
+* DESCRIPTION:
+*       This function reads a MIB counter of a specific ethernet port.
+*       NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
+*       following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
+*       register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
+*       ETH_MIB_GOOD_OCTETS_SENT_HIGH
+*
+* INPUT:
+*	ETH_PORT    eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*       unsigned int mib_offset   MIB counter offset (use ETH_MIB_... macros).
+*
+* OUTPUT:
+*       After reading the MIB counter, the counter resets.
+*
+* RETURN:
+*       MIB counter value.
+*
+*******************************************************************************/
+unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
+				   unsigned int mib_offset)
+{
+	return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
+			     + mib_offset));
+}
+
+/*******************************************************************************
+* ethernet_phy_set - Set the ethernet port PHY address.
+*
+* DESCRIPTION:
+*       This routine set the ethernet port PHY address according to given
+*       parameter.
+*
+* INPUT:
+*		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+*
+* OUTPUT:
+*       Set PHY Address Register with given PHY address parameter.
+*
+* RETURN:
+*       None.
+*
+*******************************************************************************/
+static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	reg_data &= ~(0x1F << (5 * eth_port_num));
+	reg_data |= (phy_addr << (5 * eth_port_num));
+
+	MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
+
+	return;
+}
+
+/*******************************************************************************
+ * ethernet_phy_get - Get the ethernet port PHY address.
+ *
+ * DESCRIPTION:
+ *       This routine returns the given ethernet port PHY address.
+ *
+ * INPUT:
+ *		ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       PHY address.
+ *
+ *******************************************************************************/
+static int ethernet_phy_get (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
+
+	return ((reg_data >> (5 * eth_port_num)) & 0x1f);
+}
+
+/*******************************************************************************
+ * ethernet_phy_reset - Reset Ethernet port PHY.
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to reset the ethernet port PHY.
+ *       The routine waits until the link is up again or link up is timeout.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       The ethernet port PHY renew its link.
+ *
+ * RETURN:
+ *       None.
+ *
+*******************************************************************************/
+static bool ethernet_phy_reset (ETH_PORT eth_port_num)
+{
+	unsigned int time_out = 50;
+	unsigned int phy_reg_data;
+
+	/* Reset the PHY */
+	eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
+	phy_reg_data |= 0x8000;	/* Set bit 15 to reset the PHY */
+	eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
+
+	/* Poll on the PHY LINK */
+	do {
+		eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
+
+		if (time_out-- == 0)
+			return false;
+	}
+	while (!(phy_reg_data & 0x20));
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_reset - Reset Ethernet port
+ *
+ * DESCRIPTION:
+ * 	This routine resets the chip by aborting any SDMA engine activity and
+ *      clearing the MIB counters. The Receiver and the Transmit unit are in
+ *      idle state after this command is performed and the port is disabled.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       Channel activity is halted.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_port_reset (ETH_PORT eth_port_num)
+{
+	unsigned int reg_data;
+
+	/* Stop Tx port activity. Check port Tx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Tx activity to terminate. */
+		do {
+			/* Check port cause register that all Tx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+	/* Stop Rx port activity. Check port Rx activity. */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			     (eth_port_num));
+
+	if (reg_data & 0xFF) {
+		/* Issue stop command for active channels only */
+		MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+			      (eth_port_num), (reg_data << 8));
+
+		/* Wait for all Rx activity to terminate. */
+		do {
+			/* Check port cause register that all Rx queues are stopped */
+			reg_data =
+				MV_REG_READ
+				(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
+				 (eth_port_num));
+		}
+		while (reg_data & 0xFF);
+	}
+
+
+	/* Clear all MIB counters */
+	eth_clear_mib_counters (eth_port_num);
+
+	/* Reset the Enable bit in the Configuration Register */
+	reg_data =
+		MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
+			     (eth_port_num));
+	reg_data &= ~ETH_SERIAL_PORT_ENABLE;
+	MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
+		      reg_data);
+
+	return;
+}
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_set_config_reg - Set specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function sets specified bits in the given ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are set in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_set_config_reg (ETH_PORT eth_port_num,
+				     unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg =
+		MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
+	eth_config_reg |= value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* FIXME */
+/*******************************************************************************
+ * ethernet_reset_config_reg - Reset specified bits in configuration register.
+ *
+ * DESCRIPTION:
+ *       This function resets specified bits in the given Ethernet
+ *       configuration register.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int    value   32 bit value.
+ *
+ * OUTPUT:
+ *      The set bits in the value parameter are reset in the configuration
+ *      register.
+ *
+ * RETURN:
+ *      None.
+ *
+ *******************************************************************************/
+static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
+				       unsigned int value)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	eth_config_reg &= ~value;
+	MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
+		      eth_config_reg);
+
+	return;
+}
+#endif
+
+#if 0				/* Not needed here */
+/*******************************************************************************
+ * ethernet_get_config_reg - Get the port configuration register
+ *
+ * DESCRIPTION:
+ *       This function returns the configuration register value of the given
+ *       ethernet port.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *
+ * OUTPUT:
+ *       None.
+ *
+ * RETURN:
+ *       Port configuration register value.
+ *
+ *******************************************************************************/
+static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
+{
+	unsigned int eth_config_reg;
+
+	eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
+				      (eth_port_num));
+	return eth_config_reg;
+}
+
+#endif
+
+/*******************************************************************************
+ * eth_port_read_smi_reg - Read PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform PHY register read.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       unsigned int   phy_reg   PHY register address offset.
+ *       unsigned int   *value   Register value buffer.
+ *
+ * OUTPUT:
+ *       Write the value of a specified PHY register into given buffer.
+ *
+ * RETURN:
+ *       false if the PHY is busy or read data is not in valid state.
+ *       true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
+				   unsigned int phy_reg, unsigned int *value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+/*    printf("     Phy-Port %d has addess %d  \n",eth_port_num, phy_addr );*/
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_READ);
+
+	time_out = PHY_BUSY_TIMEOUT;	/* initialize the time out var again */
+
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID);	/* Bit set equ operation done */
+
+	/* Wait for the data to update in the SMI register */
+#define PHY_UPDATE_TIMEOUT	10000
+	for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
+
+	reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+
+	*value = reg_value & 0xffff;
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_write_smi_reg - Write to PHY registers
+ *
+ * DESCRIPTION:
+ *       This routine utilize the SMI interface to interact with the PHY in
+ *       order to perform writes to PHY registers.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *      unsigned int   phy_reg   PHY register address offset.
+ *      unsigned int    value   Register value.
+ *
+ * OUTPUT:
+ *      Write the given value to the specified PHY register.
+ *
+ * RETURN:
+ *      false if the PHY is busy.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
+				    unsigned int phy_reg, unsigned int value)
+{
+	unsigned int reg_value;
+	unsigned int time_out = PHY_BUSY_TIMEOUT;
+	int phy_addr;
+
+	phy_addr = ethernet_phy_get (eth_port_num);
+
+	/* first check that it is not busy */
+	do {
+		reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
+		if (time_out-- == 0) {
+			return false;
+		}
+	}
+	while (reg_value & ETH_SMI_BUSY);
+
+	/* not busy */
+	MV_REG_WRITE (MV64360_ETH_SMI_REG,
+		      (phy_addr << 16) | (phy_reg << 21) |
+		      ETH_SMI_OPCODE_WRITE | (value & 0xffff));
+	return true;
+}
+
+/*******************************************************************************
+ * eth_set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * DESCRIPTION:
+ *       This function configures the address decode parameters for the Gigabit
+ *       Ethernet Controller according the given parameters struct.
+ *
+ * INPUT:
+ *	ETH_PORT   eth_port_num   Ethernet Port number. See ETH_PORT enum.
+ *       ETH_WIN_PARAM  *param   Address decode parameter struct.
+ *
+ * OUTPUT:
+ *       An access window is opened using the given access parameters.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_set_access_control (ETH_PORT eth_port_num,
+				    ETH_WIN_PARAM * param)
+{
+	unsigned int access_prot_reg;
+
+	/* Set access control register */
+	access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
+				       (eth_port_num));
+	access_prot_reg &= (~(3 << (param->win * 2)));	/* clear window permission */
+	access_prot_reg |= (param->access_ctrl << (param->win * 2));
+	MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
+		      access_prot_reg);
+
+	/* Set window Size reg (SR) */
+	MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
+		       (ETH_SIZE_REG_GAP * param->win)),
+		      (((param->size / 0x10000) - 1) << 16));
+
+	/* Set window Base address reg (BA) */
+	MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
+		      (param->target | param->attributes | param->base_addr));
+	/* High address remap reg (HARR) */
+	if (param->win < 4)
+		MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
+			       (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
+			      param->high_addr);
+
+	/* Base address enable reg (BARER) */
+	if (param->enable == 1)
+		MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				   (1 << param->win));
+	else
+		MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
+				 (1 << param->win));
+}
+
+/*******************************************************************************
+ * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Rx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *      int 			rx_desc_num       Number of Rx descriptors
+ *      int 			rx_buff_size      Size of Rx buffer
+ *      unsigned int    rx_desc_base_addr  Rx descriptors memory area base addr.
+ *      unsigned int    rx_buff_base_addr  Rx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Rx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE rx_queue,
+				     int rx_desc_num,
+				     int rx_buff_size,
+				     unsigned int rx_desc_base_addr,
+				     unsigned int rx_buff_base_addr)
+{
+	ETH_RX_DESC *p_rx_desc;
+	ETH_RX_DESC *p_rx_prev_desc;	/* pointer to link with the last descriptor */
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
+	p_rx_prev_desc = p_rx_desc;
+	buffer_addr = rx_buff_base_addr;
+
+	/* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (rx_buff_base_addr & 0xF)
+		return false;
+
+	/* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
+		return false;
+
+	/* Rx buffers must be 64-bit aligned.       */
+	if ((rx_buff_base_addr + rx_buff_size) & 0x7)
+		return false;
+
+	/* initialize the Rx descriptors ring */
+	for (ix = 0; ix < rx_desc_num; ix++) {
+		p_rx_desc->buf_size = rx_buff_size;
+		p_rx_desc->byte_cnt = 0x0000;
+		p_rx_desc->cmd_sts =
+			ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+		p_rx_desc->next_desc_ptr =
+			((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
+		p_rx_desc->buf_ptr = buffer_addr;
+		p_rx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_rx_desc, 0);
+		buffer_addr += rx_buff_size;
+		p_rx_prev_desc = p_rx_desc;
+		p_rx_desc = (ETH_RX_DESC *)
+			((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
+	}
+
+	/* Closing Rx descriptors ring */
+	p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
+	D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
+
+	/* Save Rx desc pointer to driver struct. */
+	CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+	USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
+
+	p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
+		(ETH_RX_DESC *) rx_desc_base_addr;
+	p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
+		rx_desc_num * RX_DESC_ALIGNED_SIZE;
+
+	p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
+ *
+ * DESCRIPTION:
+ *       This function prepares a Tx chained list of descriptors and packet
+ *       buffers in a form of a ring. The routine must be called after port
+ *       initialization routine and before port start routine.
+ *       The Ethernet SDMA engine uses CPU bus addresses to access the various
+ *       devices in the system (i.e. DRAM). This function uses the ethernet
+ *       struct 'virtual to physical' routine (set by the user) to set the ring
+ *       with physical addresses.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *      int 			tx_desc_num       Number of Tx descriptors
+ *      int 			tx_buff_size      Size of Tx buffer
+ *      unsigned int    tx_desc_base_addr  Tx descriptors memory area base addr.
+ *      unsigned int    tx_buff_base_addr  Tx buffer memory area base addr.
+ *
+ * OUTPUT:
+ *      The routine updates the Ethernet port control struct with information
+ *      regarding the Tx descriptors and buffers.
+ *
+ * RETURN:
+ *      false if the given descriptors memory area is not aligned according to
+ *      Ethernet SDMA specifications.
+ *      true otherwise.
+ *
+ *******************************************************************************/
+static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
+				     ETH_QUEUE tx_queue,
+				     int tx_desc_num,
+				     int tx_buff_size,
+				     unsigned int tx_desc_base_addr,
+				     unsigned int tx_buff_base_addr)
+{
+
+	ETH_TX_DESC *p_tx_desc;
+	ETH_TX_DESC *p_tx_prev_desc;
+	unsigned int buffer_addr;
+	int ix;			/* a counter */
+
+
+	/* save the first desc pointer to link with the last descriptor */
+	p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
+	p_tx_prev_desc = p_tx_desc;
+	buffer_addr = tx_buff_base_addr;
+
+	/* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
+	if (tx_buff_base_addr & 0xF)
+		return false;
+
+	/* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes  */
+	if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
+	    || (tx_buff_size < TX_BUFFER_MIN_SIZE))
+		return false;
+
+	/* Initialize the Tx descriptors ring */
+	for (ix = 0; ix < tx_desc_num; ix++) {
+		p_tx_desc->byte_cnt = 0x0000;
+		p_tx_desc->l4i_chk = 0x0000;
+		p_tx_desc->cmd_sts = 0x00000000;
+		p_tx_desc->next_desc_ptr =
+			((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
+
+		p_tx_desc->buf_ptr = buffer_addr;
+		p_tx_desc->return_info = 0x00000000;
+		D_CACHE_FLUSH_LINE (p_tx_desc, 0);
+		buffer_addr += tx_buff_size;
+		p_tx_prev_desc = p_tx_desc;
+		p_tx_desc = (ETH_TX_DESC *)
+			((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
+
+	}
+	/* Closing Tx descriptors ring */
+	p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
+	D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
+	/* Set Tx desc pointer in driver struct. */
+	CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+	USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
+
+	/* Init Tx ring base and size parameters */
+	p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
+		(ETH_TX_DESC *) tx_desc_base_addr;
+	p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
+		(tx_desc_num * TX_DESC_ALIGNED_SIZE);
+
+	/* Add the queue to the list of Tx queues of this port */
+	p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
+
+	return true;
+}
+
+/*******************************************************************************
+ * eth_port_send - Send an Ethernet packet
+ *
+ * DESCRIPTION:
+ *	This routine send a given packet described by p_pktinfo parameter. It
+ *      supports transmitting of a packet spaned over multiple buffers. The
+ *      routine updates 'curr' and 'first' indexes according to the packet
+ *      segment passed to the routine. In case the packet segment is first,
+ *      the 'first' index is update. In any case, the 'curr' index is updated.
+ *      If the routine get into Tx resource error it assigns 'curr' index as
+ *      'first'. This way the function can abort Tx process of multiple
+ *      descriptors per packet.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'curr' and 'first' indexes are updated.
+ *
+ * RETURN:
+ *      ETH_QUEUE_FULL in case of Tx resource error.
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *	ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
+					  ETH_QUEUE tx_queue,
+					  PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_first;
+	volatile ETH_TX_DESC *p_tx_desc_curr;
+	volatile ETH_TX_DESC *p_tx_next_desc_curr;
+	volatile ETH_TX_DESC *p_tx_desc_used;
+	unsigned int command_status;
+
+	/* Do not process Tx ring in case of Tx ring resource error */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		return ETH_QUEUE_FULL;
+
+	/* Get the Tx Desc ring indexes */
+	CURR_TFD_GET (p_tx_desc_curr, tx_queue);
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+
+	if (p_tx_desc_curr == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
+	command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
+
+	if (command_status & (ETH_TX_FIRST_DESC)) {
+		/* Update first desc */
+		FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
+		p_tx_desc_first = p_tx_desc_curr;
+	} else {
+		FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+		command_status |= ETH_BUFFER_OWNED_BY_DMA;
+	}
+
+	/* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
+	/* boundary. We use the memory allocated for Tx descriptor. This memory  */
+	/* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
+	if (p_pkt_info->byte_cnt <= 8) {
+		printf ("You have failed in the < 8 bytes errata - fixme\n");	/* RABEEH - TBD */
+		return ETH_ERROR;
+
+		p_tx_desc_curr->buf_ptr =
+			(unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
+		eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
+			    p_pkt_info->byte_cnt);
+	} else
+		p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
+
+	p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
+	p_tx_desc_curr->return_info = p_pkt_info->return_info;
+
+	if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
+		/* Set last desc with DMA ownership and interrupt enable. */
+		p_tx_desc_curr->cmd_sts = command_status |
+			ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
+
+		if (p_tx_desc_curr != p_tx_desc_first)
+			p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
+
+		/* Flush CPU pipe */
+
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
+		CPU_PIPE_FLUSH;
+
+		/* Apply send command */
+		ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
+
+		/* Finish Tx packet. Update first desc in case of Tx resource error */
+		p_tx_desc_first = p_tx_next_desc_curr;
+		FIRST_TFD_SET (p_tx_desc_first, tx_queue);
+
+	} else {
+		p_tx_desc_curr->cmd_sts = command_status;
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
+	}
+
+	/* Check for ring index overlap in the Tx desc ring */
+	if (p_tx_next_desc_curr == p_tx_desc_used) {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_desc_first, tx_queue);
+
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
+		return ETH_QUEUE_LAST_RESOURCE;
+	} else {
+		/* Update the current descriptor */
+		CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
+		return ETH_OK;
+	}
+}
+
+/*******************************************************************************
+ * eth_tx_return_desc - Free all used Tx descriptors
+ *
+ * DESCRIPTION:
+ *	This routine returns the transmitted packet information to the caller.
+ *      It uses the 'first' index to support Tx desc return in case a transmit
+ *      of a packet spanned over multiple buffer still in process.
+ *      In case the Tx queue was in "resource error" condition, where there are
+ *      no available Tx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	tx_queue         Number of Tx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Tx ring 'first' and 'used' indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Tx desc ring.
+ *      ETH_RETRY in case there is transmission in process.
+ *	ETH_END_OF_JOB if the routine has nothing to release.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE tx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_TX_DESC *p_tx_desc_used = NULL;
+	volatile ETH_TX_DESC *p_tx_desc_first = NULL;
+	unsigned int command_status;
+
+
+	/* Get the Tx Desc ring indexes */
+	USED_TFD_GET (p_tx_desc_used, tx_queue);
+	FIRST_TFD_GET (p_tx_desc_first, tx_queue);
+
+
+	/* Sanity check */
+	if (p_tx_desc_used == NULL)
+		return ETH_ERROR;
+
+	command_status = p_tx_desc_used->cmd_sts;
+
+	/* Still transmitting... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_RETRY;
+	}
+
+	/* Stop release. About to overlap the current available Tx descriptor */
+	if ((p_tx_desc_used == p_tx_desc_first) &&
+	    (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
+		D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+		return ETH_END_OF_JOB;
+	}
+
+	/* Pass the packet information to the caller */
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->return_info = p_tx_desc_used->return_info;
+	p_tx_desc_used->return_info = 0;
+
+	/* Update the next descriptor to release. */
+	USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
+
+	/* Any Tx return cancels the Tx resource error status */
+	if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
+		p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
+
+	return ETH_OK;
+
+}
+
+/*******************************************************************************
+ * eth_port_receive - Get received information from Rx ring.
+ *
+ * DESCRIPTION:
+ * 	This routine returns the received data to the caller. There is no
+ *	data copying during routine operation. All information is returned
+ *	using pointer to packet information struct passed from the caller.
+ *      If the routine exhausts	Rx ring resources then the resource error flag
+ *      is set.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *	PKT_INFO        *p_pkt_info       User packet buffer.
+ *
+ * OUTPUT:
+ *	Rx ring current and used indexes are updated.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *	ETH_QUEUE_FULL if Rx ring resources are exhausted.
+ *	ETH_END_OF_JOB if there is no received data.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_rx_curr_desc;
+	volatile ETH_RX_DESC *p_rx_next_curr_desc;
+	volatile ETH_RX_DESC *p_rx_used_desc;
+	unsigned int command_status;
+
+	/* Do not process Rx ring in case of Rx ring resource error */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
+		printf ("\nRx Queue is full ...\n");
+		return ETH_QUEUE_FULL;
+	}
+
+	/* Get the Rx Desc ring 'curr and 'used' indexes */
+	CURR_RFD_GET (p_rx_curr_desc, rx_queue);
+	USED_RFD_GET (p_rx_used_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_rx_curr_desc == NULL)
+		return ETH_ERROR;
+
+	/* The following parameters are used to save readings from memory */
+	p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
+	command_status = p_rx_curr_desc->cmd_sts;
+
+	/* Nothing to receive... */
+	if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
+/* 	DP(printf("Rx: command_status: %08x\n", command_status)); */
+		D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+/*	DP(printf("\nETH_END_OF_JOB ...\n"));*/
+		return ETH_END_OF_JOB;
+	}
+
+	p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
+	p_pkt_info->cmd_sts = command_status;
+	p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
+	p_pkt_info->return_info = p_rx_curr_desc->return_info;
+	p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size;	/* IP fragment indicator */
+
+	/* Clean the return info field to indicate that the packet has been */
+	/* moved to the upper layers                                        */
+	p_rx_curr_desc->return_info = 0;
+
+	/* Update 'curr' in data structure */
+	CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
+
+	/* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
+	if (p_rx_next_curr_desc == p_rx_used_desc)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
+
+	D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
+	CPU_PIPE_FLUSH;
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
+ *
+ * DESCRIPTION:
+ *	This routine returns a Rx buffer back to the Rx ring. It retrieves the
+ *      next 'used' descriptor and attached the returned buffer to it.
+ *      In case the Rx ring was in "resource error" condition, where there are
+ *      no available Rx resources, the function resets the resource error flag.
+ *
+ * INPUT:
+ *	ETH_PORT_INFO   *p_eth_port_ctrl   Ethernet Port Control srtuct.
+ *	ETH_QUEUE   	rx_queue         Number of Rx queue.
+ *      PKT_INFO        *p_pkt_info       Information on the returned buffer.
+ *
+ * OUTPUT:
+ *	New available Rx resource in Rx descriptor ring.
+ *
+ * RETURN:
+ *	ETH_ERROR in case the routine can not access Rx desc ring.
+ *      ETH_OK otherwise.
+ *
+ *******************************************************************************/
+static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
+					       p_eth_port_ctrl,
+					       ETH_QUEUE rx_queue,
+					       PKT_INFO * p_pkt_info)
+{
+	volatile ETH_RX_DESC *p_used_rx_desc;	/* Where to return Rx resource */
+
+	/* Get 'used' Rx descriptor */
+	USED_RFD_GET (p_used_rx_desc, rx_queue);
+
+	/* Sanity check */
+	if (p_used_rx_desc == NULL)
+		return ETH_ERROR;
+
+	p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
+	p_used_rx_desc->return_info = p_pkt_info->return_info;
+	p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
+	p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE;	/* Reset Buffer size */
+
+	/* Flush the write pipe */
+	CPU_PIPE_FLUSH;
+
+	/* Return the descriptor to DMA ownership */
+	p_used_rx_desc->cmd_sts =
+		ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
+
+	/* Flush descriptor and CPU pipe */
+	D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
+	CPU_PIPE_FLUSH;
+
+	/* Move the used descriptor pointer to the next descriptor */
+	USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
+
+	/* Any Rx return cancels the Rx resource error status */
+	if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
+		p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
+
+	return ETH_OK;
+}
+
+/*******************************************************************************
+ * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the RX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the tClk of the MV-643xx chip
+ *	, and the required delay of the interrupt in usec.
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in usec
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set RX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
+		      ((coal & 0x3fff) << 8) |
+		      (MV_REG_READ
+		       (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
+		       & 0xffc000ff));
+	return coal;
+}
+
+#endif
+/*******************************************************************************
+ * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
+ *
+ * DESCRIPTION:
+ *	This routine sets the TX coalescing interrupt mechanism parameter.
+ *	This parameter is a timeout counter, that counts in 64 t_clk
+ *	chunks ; that when timeout event occurs a maskable interrupt
+ *	occurs.
+ *	The parameter is calculated using the t_cLK frequency of the
+ *	MV-643xx chip and the required delay in the interrupt in uSec
+ *
+ * INPUT:
+ *	ETH_PORT eth_port_num      Ethernet port number
+ *	unsigned int t_clk        t_clk of the MV-643xx chip in HZ units
+ *	unsigned int delay       Delay in uSeconds
+ *
+ * OUTPUT:
+ *	Interrupt coalescing mechanism value is set in MV-643xx chip.
+ *
+ * RETURN:
+ *	The interrupt coalescing value set in the gigE port.
+ *
+ *******************************************************************************/
+#if 0				/* FIXME */
+static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
+					  unsigned int t_clk,
+					  unsigned int delay)
+{
+	unsigned int coal;
+
+	coal = ((t_clk / 1000000) * delay) / 64;
+	/* Set TX Coalescing mechanism */
+	MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
+		      coal << 4);
+	return coal;
+}
+#endif
+
+/*******************************************************************************
+ * eth_b_copy - Copy bytes from source to destination
+ *
+ * DESCRIPTION:
+ *       This function supports the eight bytes limitation on Tx buffer size.
+ *       The routine will zero eight bytes starting from the destination address
+ *       followed by copying bytes from the source address to the destination.
+ *
+ * INPUT:
+ *       unsigned int src_addr    32 bit source address.
+ *       unsigned int dst_addr    32 bit destination address.
+ *       int        byte_count    Number of bytes to copy.
+ *
+ * OUTPUT:
+ *       See description.
+ *
+ * RETURN:
+ *       None.
+ *
+ *******************************************************************************/
+static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
+			int byte_count)
+{
+	/* Zero the dst_addr area */
+	*(unsigned int *) dst_addr = 0x0;
+
+	while (byte_count != 0) {
+		*(char *) dst_addr = *(char *) src_addr;
+		dst_addr++;
+		src_addr++;
+		byte_count--;
+	}
+}
diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h
new file mode 100755
index 0000000..c57e679
--- /dev/null
+++ b/board/esd/cpci750/mv_eth.h
@@ -0,0 +1,844 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mv_eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __DB64360_ETH_H__
+#define __DB64360_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+#include <net.h>
+#include "mv_regs.h"
+#include "../../Marvell/common/ppc_error_no.h"
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The first part is the high level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
+#ifndef MAX_SKB_FRAGS
+#define MAX_SKB_FRAGS 0
+#endif
+
+/* Port attributes */
+/*#define MAX_RX_QUEUE_NUM	8*/
+/*#define MAX_TX_QUEUE_NUM	8*/
+#define MAX_RX_QUEUE_NUM	1
+#define MAX_TX_QUEUE_NUM	1
+
+
+/* Use one TX queue and one RX queue */
+#define MV64360_TX_QUEUE_NUM 1
+#define MV64360_RX_QUEUE_NUM 1
+
+/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+ * The TX descriptors only allocates the TX descriptors ring,
+ * with no pre allocated TX buffers (skb's are allocated by higher layers.
+ */
+
+/* Default TX ring size is 10 descriptors */
+#ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
+#else
+#define MV64360_TX_QUEUE_SIZE 4
+#endif
+
+/* Default RX ring size is 4 descriptors */
+#ifdef	CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
+#else
+#define MV64360_RX_QUEUE_SIZE 4
+#endif
+
+#ifdef CONFIG_RX_BUFFER_SIZE
+#define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
+#else
+#define MV64360_RX_BUFFER_SIZE 1600
+#endif
+
+#ifdef CONFIG_TX_BUFFER_SIZE
+#define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
+#else
+#define MV64360_TX_BUFFER_SIZE 1600
+#endif
+
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats
+{
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+
+/* Private data structure used for ethernet device */
+struct mv64360_eth_priv {
+    unsigned int port_num;
+    struct net_device_stats *stats;
+
+/* to buffer area aligned */
+    char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1];	/*pointers to alligned tx buffs in memory space */
+    char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1];	/*pointers to allinged rx buffs in memory space */
+
+    /* Size of Tx Ring per queue */
+    unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
+
+
+    /* Size of Rx Ring per queue */
+    unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
+
+    /* Magic Number for Ethernet running */
+    unsigned int eth_running;
+
+};
+
+
+int mv64360_eth_init (struct eth_device *dev);
+int mv64360_eth_stop (struct eth_device *dev);
+int mv64360_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
+/*	return db64360_eth0_poll(); */
+
+int mv64360_eth_open (struct eth_device *dev);
+
+
+/*************************************************************************
+**************************************************************************
+**************************************************************************
+*  The second part is the low level driver of the gigE ethernet ports.	 *
+**************************************************************************
+**************************************************************************
+*************************************************************************/
+
+
+/********************************************************************************
+ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+ *	 This header file contains macros typedefs and function declaration for
+ *	 the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+ *	 None.
+ *
+ *******************************************************************************/
+
+
+#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
+#ifdef CONFIG_MV64360_SRAM_CACHEABLE
+/* In case SRAM is cacheable but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case SRAM is cache coherent or non-cacheable */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif
+#else
+#ifdef CONFIG_NOT_COHERENT_CACHE
+/* In case of descriptors on DDR but not cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset)       \
+{		    \
+  __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
+}
+#else
+/* In case of descriptors on DDR and cache coherent */
+#define D_CACHE_FLUSH_LINE(addr, offset) ;
+#endif /* CONFIG_NOT_COHERENT_CACHE */
+#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
+
+
+#define CPU_PIPE_FLUSH		   \
+{		  \
+  __asm__ __volatile__ ("eieio");	  \
+}
+
+
+/* defines  */
+
+/* Default port configuration value */
+#define PORT_CONFIG_VALUE			\
+	     ETH_UNICAST_NORMAL_MODE		|   \
+	     ETH_DEFAULT_RX_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_ARP_QUEUE_0		|   \
+	     ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP	|   \
+	     ETH_RECEIVE_BC_IF_IP		|   \
+	     ETH_RECEIVE_BC_IF_ARP		|   \
+	     ETH_CAPTURE_TCP_FRAMES_DIS		|   \
+	     ETH_CAPTURE_UDP_FRAMES_DIS		|   \
+	     ETH_DEFAULT_RX_TCP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_UDP_QUEUE_0		|   \
+	     ETH_DEFAULT_RX_BPDU_QUEUE_0
+
+/* Default port extend configuration value */
+#define PORT_CONFIG_EXTEND_VALUE		\
+	     ETH_SPAN_BPDU_PACKETS_AS_NORMAL	|   \
+	     ETH_PARTITION_DISABLE
+
+
+/* Default sdma control value */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define PORT_SDMA_CONFIG_VALUE				\
+			 ETH_RX_BURST_SIZE_16_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_16_64BIT;
+#else
+#define PORT_SDMA_CONFIG_VALUE			\
+			 ETH_RX_BURST_SIZE_4_64BIT	|	\
+			 GT_ETH_IPG_INT_RX(0)			|	\
+			 ETH_TX_BURST_SIZE_4_64BIT;
+#endif
+
+#define GT_ETH_IPG_INT_RX(value)		\
+	    ((value & 0x3fff) << 8)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE			    \
+			ETH_FORCE_LINK_PASS			|	\
+			ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
+			ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
+			ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
+			ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
+			ETH_FORCE_BP_MODE_NO_JAM		|	\
+			BIT9					|	\
+			ETH_DO_NOT_FORCE_LINK_FAIL		|	\
+			ETH_RETRANSMIT_16_ETTEMPTS		|	\
+			ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
+			ETH_DTE_ADV_0				|	\
+			ETH_DISABLE_AUTO_NEG_BYPASS		|	\
+			ETH_AUTO_NEG_NO_CHANGE			|	\
+			ETH_MAX_RX_PACKET_1552BYTE		|	\
+			ETH_CLR_EXT_LOOPBACK			|	\
+			ETH_SET_FULL_DUPLEX_MODE		|	\
+			ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
+
+#define RX_BUFFER_MAX_SIZE  0xFFFF
+#define TX_BUFFER_MAX_SIZE  0xFFFF   /* Buffer are limited to 64k */
+
+#define RX_BUFFER_MIN_SIZE  0x8
+#define TX_BUFFER_MIN_SIZE  0x8
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT	    0x24    /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE  0x_fFFF  /* PMTBS register (default)      */
+#define PORT_TOKEN_RATE		    1023    /* PTTBRC register (default)     */
+
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR	    0
+#define REJECT_MAC_ADDR	    1
+
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define RX_DESC_ALIGNED_SIZE		0x20
+#define TX_DESC_ALIGNED_SIZE		0x20
+
+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
+#define TX_BUF_OFFSET_IN_DESC	    0x18
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET				0x2
+
+/* Gap define */
+#define ETH_BAR_GAP					0x8
+#define ETH_SIZE_REG_GAP				0x8
+#define ETH_HIGH_ADDR_REMAP_REG_GAP			0x4
+#define ETH_PORT_ACCESS_CTRL_GAP			0x4
+
+/* Gigabit Ethernet Unit Global Registers */
+
+/* MIB Counters register definitions */
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW   0x0
+#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH  0x4
+#define ETH_MIB_BAD_OCTETS_RECEIVED	   0x8
+#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR  0xc
+#define ETH_MIB_GOOD_FRAMES_RECEIVED	   0x10
+#define ETH_MIB_BAD_FRAMES_RECEIVED	   0x14
+#define ETH_MIB_BROADCAST_FRAMES_RECEIVED  0x18
+#define ETH_MIB_MULTICAST_FRAMES_RECEIVED  0x1c
+#define ETH_MIB_FRAMES_64_OCTETS	   0x20
+#define ETH_MIB_FRAMES_65_TO_127_OCTETS	   0x24
+#define ETH_MIB_FRAMES_128_TO_255_OCTETS   0x28
+#define ETH_MIB_FRAMES_256_TO_511_OCTETS   0x2c
+#define ETH_MIB_FRAMES_512_TO_1023_OCTETS  0x30
+#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS  0x34
+#define ETH_MIB_GOOD_OCTETS_SENT_LOW	   0x38
+#define ETH_MIB_GOOD_OCTETS_SENT_HIGH	   0x3c
+#define ETH_MIB_GOOD_FRAMES_SENT	   0x40
+#define ETH_MIB_EXCESSIVE_COLLISION	   0x44
+#define ETH_MIB_MULTICAST_FRAMES_SENT	   0x48
+#define ETH_MIB_BROADCAST_FRAMES_SENT	   0x4c
+#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+#define ETH_MIB_FC_SENT			   0x54
+#define ETH_MIB_GOOD_FC_RECEIVED	   0x58
+#define ETH_MIB_BAD_FC_RECEIVED		   0x5c
+#define ETH_MIB_UNDERSIZE_RECEIVED	   0x60
+#define ETH_MIB_FRAGMENTS_RECEIVED	   0x64
+#define ETH_MIB_OVERSIZE_RECEIVED	   0x68
+#define ETH_MIB_JABBER_RECEIVED		   0x6c
+#define ETH_MIB_MAC_RECEIVE_ERROR	   0x70
+#define ETH_MIB_BAD_CRC_EVENT		   0x74
+#define ETH_MIB_COLLISION		   0x78
+#define ETH_MIB_LATE_COLLISION		   0x7c
+
+/* Port serial status reg (PSR) */
+#define ETH_INTERFACE_GMII_MII				0
+#define ETH_INTERFACE_PCM				BIT0
+#define ETH_LINK_IS_DOWN				0
+#define ETH_LINK_IS_UP					BIT1
+#define ETH_PORT_AT_HALF_DUPLEX				0
+#define ETH_PORT_AT_FULL_DUPLEX				BIT2
+#define ETH_RX_FLOW_CTRL_DISABLED			0
+#define ETH_RX_FLOW_CTRL_ENBALED			BIT3
+#define ETH_GMII_SPEED_100_10				0
+#define ETH_GMII_SPEED_1000				BIT4
+#define ETH_MII_SPEED_10				0
+#define ETH_MII_SPEED_100				BIT5
+#define ETH_NO_TX					0
+#define ETH_TX_IN_PROGRESS				BIT7
+#define ETH_BYPASS_NO_ACTIVE				0
+#define ETH_BYPASS_ACTIVE				BIT8
+#define ETH_PORT_NOT_AT_PARTITION_STATE			0
+#define ETH_PORT_AT_PARTITION_STATE			BIT9
+#define ETH_PORT_TX_FIFO_NOT_EMPTY			0
+#define ETH_PORT_TX_FIFO_EMPTY				BIT10
+
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define ETH_UNICAST_NORMAL_MODE				0
+#define ETH_UNICAST_PROMISCUOUS_MODE			BIT0
+#define ETH_DEFAULT_RX_QUEUE_0				0
+#define ETH_DEFAULT_RX_QUEUE_1				BIT1
+#define ETH_DEFAULT_RX_QUEUE_2				BIT2
+#define ETH_DEFAULT_RX_QUEUE_3				(BIT2 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_4				BIT3
+#define ETH_DEFAULT_RX_QUEUE_5				(BIT3 | BIT1)
+#define ETH_DEFAULT_RX_QUEUE_6				(BIT3 | BIT2)
+#define ETH_DEFAULT_RX_QUEUE_7				(BIT3 | BIT2 | BIT1)
+#define ETH_DEFAULT_RX_ARP_QUEUE_0			0
+#define ETH_DEFAULT_RX_ARP_QUEUE_1			BIT4
+#define ETH_DEFAULT_RX_ARP_QUEUE_2			BIT5
+#define ETH_DEFAULT_RX_ARP_QUEUE_3			(BIT5 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_4			BIT6
+#define ETH_DEFAULT_RX_ARP_QUEUE_5			(BIT6 | BIT4)
+#define ETH_DEFAULT_RX_ARP_QUEUE_6			(BIT6 | BIT5)
+#define ETH_DEFAULT_RX_ARP_QUEUE_7			(BIT6 | BIT5 | BIT4)
+#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP			0
+#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP			BIT7
+#define ETH_RECEIVE_BC_IF_IP				0
+#define ETH_REJECT_BC_IF_IP				BIT8
+#define ETH_RECEIVE_BC_IF_ARP				0
+#define ETH_REJECT_BC_IF_ARP				BIT9
+#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY		BIT12
+#define ETH_CAPTURE_TCP_FRAMES_DIS			0
+#define ETH_CAPTURE_TCP_FRAMES_EN			BIT14
+#define ETH_CAPTURE_UDP_FRAMES_DIS			0
+#define ETH_CAPTURE_UDP_FRAMES_EN			BIT15
+#define ETH_DEFAULT_RX_TCP_QUEUE_0			0
+#define ETH_DEFAULT_RX_TCP_QUEUE_1			BIT16
+#define ETH_DEFAULT_RX_TCP_QUEUE_2			BIT17
+#define ETH_DEFAULT_RX_TCP_QUEUE_3			(BIT17 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_4			BIT18
+#define ETH_DEFAULT_RX_TCP_QUEUE_5			(BIT18 | BIT16)
+#define ETH_DEFAULT_RX_TCP_QUEUE_6			(BIT18 | BIT17)
+#define ETH_DEFAULT_RX_TCP_QUEUE_7			(BIT18 | BIT17 | BIT16)
+#define ETH_DEFAULT_RX_UDP_QUEUE_0			0
+#define ETH_DEFAULT_RX_UDP_QUEUE_1			BIT19
+#define ETH_DEFAULT_RX_UDP_QUEUE_2			BIT20
+#define ETH_DEFAULT_RX_UDP_QUEUE_3			(BIT20 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_4			(BIT21
+#define ETH_DEFAULT_RX_UDP_QUEUE_5			(BIT21 | BIT19)
+#define ETH_DEFAULT_RX_UDP_QUEUE_6			(BIT21 | BIT20)
+#define ETH_DEFAULT_RX_UDP_QUEUE_7			(BIT21 | BIT20 | BIT19)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_0			 0
+#define ETH_DEFAULT_RX_BPDU_QUEUE_1			BIT22
+#define ETH_DEFAULT_RX_BPDU_QUEUE_2			BIT23
+#define ETH_DEFAULT_RX_BPDU_QUEUE_3			(BIT23 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_4			BIT24
+#define ETH_DEFAULT_RX_BPDU_QUEUE_5			(BIT24 | BIT22)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_6			(BIT24 | BIT23)
+#define ETH_DEFAULT_RX_BPDU_QUEUE_7			(BIT24 | BIT23 | BIT22)
+
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define ETH_CLASSIFY_EN					BIT0
+#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL			0
+#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7		BIT1
+#define ETH_PARTITION_DISABLE				0
+#define ETH_PARTITION_ENABLE				BIT2
+
+
+/* Tx/Rx queue command reg (RQCR/TQCR)*/
+#define ETH_QUEUE_0_ENABLE				BIT0
+#define ETH_QUEUE_1_ENABLE				BIT1
+#define ETH_QUEUE_2_ENABLE				BIT2
+#define ETH_QUEUE_3_ENABLE				BIT3
+#define ETH_QUEUE_4_ENABLE				BIT4
+#define ETH_QUEUE_5_ENABLE				BIT5
+#define ETH_QUEUE_6_ENABLE				BIT6
+#define ETH_QUEUE_7_ENABLE				BIT7
+#define ETH_QUEUE_0_DISABLE				BIT8
+#define ETH_QUEUE_1_DISABLE				BIT9
+#define ETH_QUEUE_2_DISABLE				BIT10
+#define ETH_QUEUE_3_DISABLE				BIT11
+#define ETH_QUEUE_4_DISABLE				BIT12
+#define ETH_QUEUE_5_DISABLE				BIT13
+#define ETH_QUEUE_6_DISABLE				BIT14
+#define ETH_QUEUE_7_DISABLE				BIT15
+
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define ETH_RIFB					BIT0
+#define ETH_RX_BURST_SIZE_1_64BIT			0
+#define ETH_RX_BURST_SIZE_2_64BIT			BIT1
+#define ETH_RX_BURST_SIZE_4_64BIT			BIT2
+#define ETH_RX_BURST_SIZE_8_64BIT			(BIT2 | BIT1)
+#define ETH_RX_BURST_SIZE_16_64BIT			BIT3
+#define ETH_BLM_RX_NO_SWAP				BIT4
+#define ETH_BLM_RX_BYTE_SWAP				0
+#define ETH_BLM_TX_NO_SWAP				BIT5
+#define ETH_BLM_TX_BYTE_SWAP				0
+#define ETH_DESCRIPTORS_BYTE_SWAP			BIT6
+#define ETH_DESCRIPTORS_NO_SWAP				0
+#define ETH_TX_BURST_SIZE_1_64BIT			0
+#define ETH_TX_BURST_SIZE_2_64BIT			BIT22
+#define ETH_TX_BURST_SIZE_4_64BIT			BIT23
+#define ETH_TX_BURST_SIZE_8_64BIT			(BIT23 | BIT22)
+#define ETH_TX_BURST_SIZE_16_64BIT			BIT24
+
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define ETH_SERIAL_PORT_DISABLE				0
+#define ETH_SERIAL_PORT_ENABLE				BIT0
+#define ETH_FORCE_LINK_PASS				BIT1
+#define ETH_DO_NOT_FORCE_LINK_PASS			0
+#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX			0
+#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX			BIT2
+#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL		0
+#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL		BIT3
+#define ETH_ADV_NO_FLOW_CTRL				0
+#define ETH_ADV_SYMMETRIC_FLOW_CTRL			BIT4
+#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX		0
+#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS			BIT5
+#define ETH_FORCE_BP_MODE_NO_JAM			0
+#define ETH_FORCE_BP_MODE_JAM_TX			BIT7
+#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR		BIT8
+#define ETH_FORCE_LINK_FAIL				0
+#define ETH_DO_NOT_FORCE_LINK_FAIL			BIT10
+#define ETH_RETRANSMIT_16_ETTEMPTS			0
+#define ETH_RETRANSMIT_FOREVER				BIT11
+#define ETH_DISABLE_AUTO_NEG_SPEED_GMII			BIT13
+#define ETH_ENABLE_AUTO_NEG_SPEED_GMII			0
+#define ETH_DTE_ADV_0					0
+#define ETH_DTE_ADV_1					BIT14
+#define ETH_DISABLE_AUTO_NEG_BYPASS			0
+#define ETH_ENABLE_AUTO_NEG_BYPASS			BIT15
+#define ETH_AUTO_NEG_NO_CHANGE				0
+#define ETH_RESTART_AUTO_NEG				BIT16
+#define ETH_MAX_RX_PACKET_1518BYTE			0
+#define ETH_MAX_RX_PACKET_1522BYTE			BIT17
+#define ETH_MAX_RX_PACKET_1552BYTE			BIT18
+#define ETH_MAX_RX_PACKET_9022BYTE			(BIT18 | BIT17)
+#define ETH_MAX_RX_PACKET_9192BYTE			BIT19
+#define ETH_MAX_RX_PACKET_9700BYTE			(BIT19 | BIT17)
+#define ETH_SET_EXT_LOOPBACK				BIT20
+#define ETH_CLR_EXT_LOOPBACK				0
+#define ETH_SET_FULL_DUPLEX_MODE			BIT21
+#define ETH_SET_HALF_DUPLEX_MODE			0
+#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	BIT22
+#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	0
+#define ETH_SET_GMII_SPEED_TO_10_100			0
+#define ETH_SET_GMII_SPEED_TO_1000			BIT23
+#define ETH_SET_MII_SPEED_TO_10				0
+#define ETH_SET_MII_SPEED_TO_100			BIT24
+
+
+/* SMI reg */
+#define ETH_SMI_BUSY		BIT28	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_READ_VALID	BIT27	/* 0 - Write, 1 - Read		*/
+#define ETH_SMI_OPCODE_WRITE	0	/* Completion of Read operation */
+#define ETH_SMI_OPCODE_READ	BIT26	/* Operation is in progress		*/
+
+/* SDMA command status fields macros */
+
+/* Tx & Rx descriptors status */
+#define ETH_ERROR_SUMMARY		    (BIT0)
+
+/* Tx & Rx descriptors command */
+#define ETH_BUFFER_OWNED_BY_DMA		    (BIT31)
+
+/* Tx descriptors status */
+#define ETH_LC_ERROR			    (0	  )
+#define ETH_UR_ERROR			    (BIT1 )
+#define ETH_RL_ERROR			    (BIT2 )
+#define ETH_LLC_SNAP_FORMAT		    (BIT9 )
+
+/* Rx descriptors status */
+#define ETH_CRC_ERROR			    (0	  )
+#define ETH_OVERRUN_ERROR		    (BIT1 )
+#define ETH_MAX_FRAME_LENGTH_ERROR	    (BIT2 )
+#define ETH_RESOURCE_ERROR		    ((BIT2 | BIT1))
+#define ETH_VLAN_TAGGED			    (BIT19)
+#define ETH_BPDU_FRAME			    (BIT20)
+#define ETH_TCP_FRAME_OVER_IP_V_4	    (0	  )
+#define ETH_UDP_FRAME_OVER_IP_V_4	    (BIT21)
+#define ETH_OTHER_FRAME_TYPE		    (BIT22)
+#define ETH_LAYER_2_IS_ETH_V_2		    (BIT23)
+#define ETH_FRAME_TYPE_IP_V_4		    (BIT24)
+#define ETH_FRAME_HEADER_OK		    (BIT25)
+#define ETH_RX_LAST_DESC		    (BIT26)
+#define ETH_RX_FIRST_DESC		    (BIT27)
+#define ETH_UNKNOWN_DESTINATION_ADDR	    (BIT28)
+#define ETH_RX_ENABLE_INTERRUPT		    (BIT29)
+#define ETH_LAYER_4_CHECKSUM_OK		    (BIT30)
+
+/* Rx descriptors byte count */
+#define ETH_FRAME_FRAGMENTED		    (BIT2)
+
+/* Tx descriptors command */
+#define ETH_LAYER_4_CHECKSUM_FIRST_DESC		(BIT10)
+#define ETH_FRAME_SET_TO_VLAN		    (BIT15)
+#define ETH_TCP_FRAME			    (0	  )
+#define ETH_UDP_FRAME			    (BIT16)
+#define ETH_GEN_TCP_UDP_CHECKSUM	    (BIT17)
+#define ETH_GEN_IP_V_4_CHECKSUM		    (BIT18)
+#define ETH_ZERO_PADDING		    (BIT19)
+#define ETH_TX_LAST_DESC		    (BIT20)
+#define ETH_TX_FIRST_DESC		    (BIT21)
+#define ETH_GEN_CRC			    (BIT22)
+#define ETH_TX_ENABLE_INTERRUPT		    (BIT23)
+#define ETH_AUTO_MODE			    (BIT30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM					0x00000000
+#define EBAR_TARGET_DEVICE					0x00000001
+#define EBAR_TARGET_CBS						0x00000002
+#define EBAR_TARGET_PCI0					0x00000003
+#define EBAR_TARGET_PCI1					0x00000004
+#define EBAR_TARGET_CUNIT					0x00000005
+#define EBAR_TARGET_AUNIT					0x00000006
+#define EBAR_TARGET_GUNIT					0x00000007
+
+/* Window attributes */
+#define EBAR_ATTR_DRAM_CS0					0x00000E00
+#define EBAR_ATTR_DRAM_CS1					0x00000D00
+#define EBAR_ATTR_DRAM_CS2					0x00000B00
+#define EBAR_ATTR_DRAM_CS3					0x00000700
+
+/* DRAM Target interface */
+#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY	0x00000000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT	0x00001000
+#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB	0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_ATTR_DEVICE_DEVCS0				0x00001E00
+#define EBAR_ATTR_DEVICE_DEVCS1				0x00001D00
+#define EBAR_ATTR_DEVICE_DEVCS2				0x00001B00
+#define EBAR_ATTR_DEVICE_DEVCS3				0x00001700
+#define EBAR_ATTR_DEVICE_BOOTCS3			0x00000F00
+
+/* PCI Target interface */
+#define EBAR_ATTR_PCI_BYTE_SWAP				0x00000000
+#define EBAR_ATTR_PCI_NO_SWAP				0x00000100
+#define EBAR_ATTR_PCI_BYTE_WORD_SWAP		0x00000200
+#define EBAR_ATTR_PCI_WORD_SWAP				0x00000300
+#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT	0x00000000
+#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT		0x00000400
+#define EBAR_ATTR_PCI_IO_SPACE				0x00000000
+#define EBAR_ATTR_PCI_MEMORY_SPACE			0x00000800
+#define EBAR_ATTR_PCI_REQ64_FORCE			0x00000000
+#define EBAR_ATTR_PCI_REQ64_SIZE			0x00001000
+
+/* CPU 60x bus or internal SRAM interface */
+#define EBAR_ATTR_CBS_SRAM_BLOCK0			0x00000000
+#define EBAR_ATTR_CBS_SRAM_BLOCK1			0x00000100
+#define EBAR_ATTR_CBS_SRAM					0x00000000
+#define EBAR_ATTR_CBS_CPU_BUS				0x00000800
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY	BIT0
+#define EWIN_ACCESS_FULL	(BIT1 | BIT0)
+#define EWIN0_ACCESS_MASK		0x0003
+#define EWIN1_ACCESS_MASK		0x000C
+#define EWIN2_ACCESS_MASK		0x0030
+#define EWIN3_ACCESS_MASK		0x00C0
+
+/* typedefs */
+
+typedef enum _eth_port
+{
+    ETH_0 = 0,
+	ETH_1 = 1,
+	ETH_2 = 2
+}ETH_PORT;
+
+typedef enum _eth_func_ret_status
+{
+    ETH_OK,			/* Returned as expected.		    */
+    ETH_ERROR,			/* Fundamental error.			    */
+    ETH_RETRY,			/* Could not process request. Try later.    */
+    ETH_END_OF_JOB,		/* Ring has nothing to process.		    */
+    ETH_QUEUE_FULL,		/* Ring resource error.			    */
+    ETH_QUEUE_LAST_RESOURCE	/* Ring resources about to exhaust.	    */
+}ETH_FUNC_RET_STATUS;
+
+typedef enum _eth_queue
+{
+	ETH_Q0 = 0,
+	ETH_Q1 = 1,
+	ETH_Q2 = 2,
+	ETH_Q3 = 3,
+	ETH_Q4 = 4,
+	ETH_Q5 = 5,
+	ETH_Q6 = 6,
+    ETH_Q7 = 7
+} ETH_QUEUE;
+
+typedef enum _addr_win
+{
+	ETH_WIN0,
+	ETH_WIN1,
+	ETH_WIN2,
+	ETH_WIN3,
+	ETH_WIN4,
+    ETH_WIN5
+} ETH_ADDR_WIN;
+
+typedef enum _eth_target
+{
+	ETH_TARGET_DRAM	 ,
+	ETH_TARGET_DEVICE,
+	ETH_TARGET_CBS	 ,
+	ETH_TARGET_PCI0	 ,
+	ETH_TARGET_PCI1
+}ETH_TARGET;
+
+typedef struct _eth_rx_desc
+{
+	unsigned short	byte_cnt	   ;	/* Descriptor buffer byte count	    */
+	unsigned short	buf_size	   ;	/* Buffer size			    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	next_desc_ptr;	  /* Next descriptor pointer	      */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_RX_DESC;
+
+
+typedef struct _eth_tx_desc
+{
+    unsigned short  byte_cnt	   ;	/* Descriptor buffer byte count	    */
+    unsigned short  l4i_chk	   ;	/* CPU provided TCP Checksum	    */
+    unsigned int    cmd_sts	   ;	/* Descriptor command status	    */
+    unsigned int    next_desc_ptr;    /* Next descriptor pointer	  */
+    unsigned int    buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} ETH_TX_DESC;
+
+/* Unified struct for Rx and Tx operations. The user is not required to */
+/* be familier with neither Tx nor Rx descriptors.			 */
+typedef struct _pkt_info
+{
+	unsigned short	byte_cnt   ;	/* Descriptor buffer byte count	    */
+	unsigned short	l4i_chk	   ;	/* Tx CPU provided TCP Checksum	    */
+	unsigned int	cmd_sts	   ;	/* Descriptor command status	    */
+	unsigned int	buf_ptr	   ;	/* Descriptor buffer pointer	    */
+    unsigned int    return_info ;    /* User resource return information */
+} PKT_INFO;
+
+
+typedef struct _eth_win_param
+{
+    ETH_ADDR_WIN win;	/* Window number. See ETH_ADDR_WIN enum */
+    ETH_TARGET	target;	   /* System targets. See ETH_TARGET enum */
+    unsigned short attributes;	/* BAR attributes. See above macros. */
+    unsigned int base_addr; /* Window base address in unsigned int form */
+    unsigned int high_addr; /* Window high address in unsigned int form */
+    unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
+    bool enable; /* Enable/disable access to the window. */
+    unsigned short access_ctrl; /* Access ctrl register. see above macros */
+} ETH_WIN_PARAM;
+
+
+/* Ethernet port specific infomation */
+
+typedef struct _eth_port_ctrl
+{
+    ETH_PORT  port_num; /* User Ethernet port number */
+    int port_phy_addr;	/* User phy address of Ethrnet port */
+    unsigned char port_mac_addr[6]; /* User defined port MAC address. */
+    unsigned int  port_config; /* User port configuration value */
+    unsigned int  port_config_extend; /* User port config extend value */
+    unsigned int  port_sdma_config; /* User port SDMA config value */
+    unsigned int  port_serial_control; /* User port serial control value */
+    unsigned int  port_tx_queue_command; /* Port active Tx queues summary */
+    unsigned int  port_rx_queue_command; /* Port active Rx queues summary */
+
+    /* User function to cast virtual address to CPU bus address */
+    unsigned int  (*port_virt_to_phys)(unsigned int addr);
+    /* User scratch pad for user specific data structures */
+    void *port_private;
+
+    bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
+    bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
+
+    /* Tx/Rx rings managment indexes fields. For driver use */
+
+    /* Next available Rx resource */
+    volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
+    /* Returning Rx resource */
+    volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
+
+    /* Next available Tx resource */
+    volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
+    /* Returning Tx resource */
+    volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
+    /* An extra Tx index to support transmit of multiple buffers per packet */
+    volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
+
+    /* Tx/Rx rings size and base variables fields. For driver use */
+
+    volatile ETH_RX_DESC	*p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
+    unsigned int		 rx_desc_area_size[MAX_RX_QUEUE_NUM];
+    char			*p_rx_buffer_base[MAX_RX_QUEUE_NUM];
+
+    volatile ETH_TX_DESC	*p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
+    unsigned int		 tx_desc_area_size[MAX_TX_QUEUE_NUM];
+    char			*p_tx_buffer_base[MAX_TX_QUEUE_NUM];
+
+} ETH_PORT_INFO;
+
+
+/* ethernet.h API list */
+
+/* Port operation control routines */
+static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
+static void eth_port_reset(ETH_PORT	eth_port_num);
+static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
+
+
+/* Port MAC address routines */
+static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
+				  unsigned char *p_addr,
+				  ETH_QUEUE queue);
+#if 0	/* FIXME */
+static void eth_port_mc_addr	(ETH_PORT eth_port_num,
+				 unsigned char *p_addr,
+				 ETH_QUEUE queue,
+				 int option);
+#endif
+
+/* PHY and MIB routines */
+static bool ethernet_phy_reset(ETH_PORT eth_port_num);
+
+static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
+				   unsigned int phy_reg,
+				   unsigned int value);
+
+static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
+				  unsigned int phy_reg,
+				  unsigned int* value);
+
+static void eth_clear_mib_counters(ETH_PORT	eth_port_num);
+
+/* Port data flow control routines */
+static ETH_FUNC_RET_STATUS eth_port_send    (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE tx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE tx_queue,
+					      PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
+					     ETH_QUEUE rx_queue,
+					     PKT_INFO *p_pkt_info);
+static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
+					      ETH_QUEUE rx_queue,
+					      PKT_INFO *p_pkt_info);
+
+
+static bool ether_init_tx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	tx_queue,
+				    int				tx_desc_num,
+				    int				tx_buff_size,
+				    unsigned int	tx_desc_base_addr,
+				    unsigned int	tx_buff_base_addr);
+
+static bool ether_init_rx_desc_ring(ETH_PORT_INFO  *p_eth_port_ctrl,
+				    ETH_QUEUE	rx_queue,
+				    int				rx_desc_num,
+				    int				rx_buff_size,
+				    unsigned int	rx_desc_base_addr,
+				    unsigned int	rx_buff_base_addr);
+
+#endif /* MV64360_ETH_ */
diff --git a/board/esd/cpci750/mv_regs.h b/board/esd/cpci750/mv_regs.h
new file mode 100755
index 0000000..0d6370b
--- /dev/null
+++ b/board/esd/cpci750/mv_regs.h
@@ -0,0 +1,1124 @@
+/*
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh@galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/********************************************************************************
+* gt64360r.h - GT-64360 Internal registers definition file.
+*
+* DESCRIPTION:
+*	None.
+*
+* DEPENDENCIES:
+*	None.
+*
+*******************************************************************************/
+
+#ifndef __INCmv_regsh
+#define __INCmv_regsh
+
+#define MV64360
+
+/* Supported by the Atlantis */
+#define MV64360_INCLUDE_PCI_1
+#define MV64360_INCLUDE_PCI_0_ARBITER
+#define MV64360_INCLUDE_PCI_1_ARBITER
+#define MV64360_INCLUDE_SNOOP_SUPPORT
+#define MV64360_INCLUDE_P2P
+#define MV64360_INCLUDE_ETH_PORT_2
+#define MV64360_INCLUDE_CPU_MAPPING
+#define MV64360_INCLUDE_MPSC
+
+/* Not supported features */
+#undef	INCLUDE_CNTMR_4_7
+#undef	INCLUDE_DMA_4_7
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* DDR SDRAM BAR and size registers */
+
+#define MV64360_CS_0_BASE_ADDR					    0x008
+#define MV64360_CS_0_SIZE					    0x010
+#define MV64360_CS_1_BASE_ADDR					    0x208
+#define MV64360_CS_1_SIZE					    0x210
+#define MV64360_CS_2_BASE_ADDR					    0x018
+#define MV64360_CS_2_SIZE					    0x020
+#define MV64360_CS_3_BASE_ADDR					    0x218
+#define MV64360_CS_3_SIZE					    0x220
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* PCI 0 BAR and size registers */
+
+#define MV64360_PCI_0_IO_BASE_ADDR				    0x048
+#define MV64360_PCI_0_IO_SIZE					    0x050
+#define MV64360_PCI_0_MEMORY0_BASE_ADDR				    0x058
+#define MV64360_PCI_0_MEMORY0_SIZE				    0x060
+#define MV64360_PCI_0_MEMORY1_BASE_ADDR				    0x080
+#define MV64360_PCI_0_MEMORY1_SIZE				    0x088
+#define MV64360_PCI_0_MEMORY2_BASE_ADDR				    0x258
+#define MV64360_PCI_0_MEMORY2_SIZE				    0x260
+#define MV64360_PCI_0_MEMORY3_BASE_ADDR				    0x280
+#define MV64360_PCI_0_MEMORY3_SIZE				    0x288
+
+/* PCI 1 BAR and size registers */
+#define MV64360_PCI_1_IO_BASE_ADDR				    0x090
+#define MV64360_PCI_1_IO_SIZE					    0x098
+#define MV64360_PCI_1_MEMORY0_BASE_ADDR				    0x0a0
+#define MV64360_PCI_1_MEMORY0_SIZE				    0x0a8
+#define MV64360_PCI_1_MEMORY1_BASE_ADDR				    0x0b0
+#define MV64360_PCI_1_MEMORY1_SIZE				    0x0b8
+#define MV64360_PCI_1_MEMORY2_BASE_ADDR				    0x2a0
+#define MV64360_PCI_1_MEMORY2_SIZE				    0x2a8
+#define MV64360_PCI_1_MEMORY3_BASE_ADDR				    0x2b0
+#define MV64360_PCI_1_MEMORY3_SIZE				    0x2b8
+
+/* SRAM base address */
+#define MV64360_INTEGRATED_SRAM_BASE_ADDR			    0x268
+
+/* internal registers space base address */
+#define MV64360_INTERNAL_SPACE_BASE_ADDR			    0x068
+
+/* Enables the CS , DEV_CS , PCI 0 and PCI 1
+   windows above */
+#define MV64360_BASE_ADDR_ENABLE				    0x278
+
+/****************************************/
+/* PCI remap registers			*/
+/****************************************/
+      /* PCI 0 */
+#define MV64360_PCI_0_IO_ADDR_REMAP				    0x0f0
+#define MV64360_PCI_0_MEMORY0_LOW_ADDR_REMAP			    0x0f8
+#define MV64360_PCI_0_MEMORY0_HIGH_ADDR_REMAP			    0x320
+#define MV64360_PCI_0_MEMORY1_LOW_ADDR_REMAP			    0x100
+#define MV64360_PCI_0_MEMORY1_HIGH_ADDR_REMAP			    0x328
+#define MV64360_PCI_0_MEMORY2_LOW_ADDR_REMAP			    0x2f8
+#define MV64360_PCI_0_MEMORY2_HIGH_ADDR_REMAP			    0x330
+#define MV64360_PCI_0_MEMORY3_LOW_ADDR_REMAP			    0x300
+#define MV64360_PCI_0_MEMORY3_HIGH_ADDR_REMAP			    0x338
+      /* PCI 1 */
+#define MV64360_PCI_1_IO_ADDR_REMAP				    0x108
+#define MV64360_PCI_1_MEMORY0_LOW_ADDR_REMAP			    0x110
+#define MV64360_PCI_1_MEMORY0_HIGH_ADDR_REMAP			    0x340
+#define MV64360_PCI_1_MEMORY1_LOW_ADDR_REMAP			    0x118
+#define MV64360_PCI_1_MEMORY1_HIGH_ADDR_REMAP			    0x348
+#define MV64360_PCI_1_MEMORY2_LOW_ADDR_REMAP			    0x310
+#define MV64360_PCI_1_MEMORY2_HIGH_ADDR_REMAP			    0x350
+#define MV64360_PCI_1_MEMORY3_LOW_ADDR_REMAP			    0x318
+#define MV64360_PCI_1_MEMORY3_HIGH_ADDR_REMAP			    0x358
+
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_CONTROL		    0x3b0
+#define MV64360_CPU_PCI_0_HEADERS_RETARGET_BASE			    0x3b8
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_CONTROL		    0x3c0
+#define MV64360_CPU_PCI_1_HEADERS_RETARGET_BASE			    0x3c8
+#define MV64360_CPU_GE_HEADERS_RETARGET_CONTROL			    0x3d0
+#define MV64360_CPU_GE_HEADERS_RETARGET_BASE			    0x3d8
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_CONTROL		    0x3e0
+#define MV64360_CPU_IDMA_HEADERS_RETARGET_BASE			    0x3e8
+
+/****************************************/
+/*	   CPU Control Registers	*/
+/****************************************/
+
+#define MV64360_CPU_CONFIG					    0x000
+#define MV64360_CPU_MODE					    0x120
+#define MV64360_CPU_MASTER_CONTROL				    0x160
+#define MV64360_CPU_CROSS_BAR_CONTROL_LOW			    0x150
+#define MV64360_CPU_CROSS_BAR_CONTROL_HIGH			    0x158
+#define MV64360_CPU_CROSS_BAR_TIMEOUT				    0x168
+
+/****************************************/
+/* SMP RegisterS			*/
+/****************************************/
+
+#define MV64360_SMP_WHO_AM_I					    0x200
+#define MV64360_SMP_CPU0_DOORBELL				    0x214
+#define MV64360_SMP_CPU0_DOORBELL_CLEAR				    0x21C
+#define MV64360_SMP_CPU1_DOORBELL				    0x224
+#define MV64360_SMP_CPU1_DOORBELL_CLEAR				    0x22C
+#define MV64360_SMP_CPU0_DOORBELL_MASK				    0x234
+#define MV64360_SMP_CPU1_DOORBELL_MASK				    0x23C
+#define MV64360_SMP_SEMAPHOR0					    0x244
+#define MV64360_SMP_SEMAPHOR1					    0x24c
+#define MV64360_SMP_SEMAPHOR2					    0x254
+#define MV64360_SMP_SEMAPHOR3					    0x25c
+#define MV64360_SMP_SEMAPHOR4					    0x264
+#define MV64360_SMP_SEMAPHOR5					    0x26c
+#define MV64360_SMP_SEMAPHOR6					    0x274
+#define MV64360_SMP_SEMAPHOR7					    0x27c
+
+/****************************************/
+/*  CPU Sync Barrier Register		*/
+/****************************************/
+
+#define MV64360_CPU_0_SYNC_BARRIER_TRIGGER			    0x0c0
+#define MV64360_CPU_0_SYNC_BARRIER_VIRTUAL			    0x0c8
+#define MV64360_CPU_1_SYNC_BARRIER_TRIGGER			    0x0d0
+#define MV64360_CPU_1_SYNC_BARRIER_VIRTUAL			    0x0d8
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define MV64360_CPU_PROTECT_WINDOW_0_BASE_ADDR			    0x180
+#define MV64360_CPU_PROTECT_WINDOW_0_SIZE			    0x188
+#define MV64360_CPU_PROTECT_WINDOW_1_BASE_ADDR			    0x190
+#define MV64360_CPU_PROTECT_WINDOW_1_SIZE			    0x198
+#define MV64360_CPU_PROTECT_WINDOW_2_BASE_ADDR			    0x1a0
+#define MV64360_CPU_PROTECT_WINDOW_2_SIZE			    0x1a8
+#define MV64360_CPU_PROTECT_WINDOW_3_BASE_ADDR			    0x1b0
+#define MV64360_CPU_PROTECT_WINDOW_3_SIZE			    0x1b8
+
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define MV64360_CPU_ERROR_ADDR_LOW				    0x070
+#define MV64360_CPU_ERROR_ADDR_HIGH				    0x078
+#define MV64360_CPU_ERROR_DATA_LOW				    0x128
+#define MV64360_CPU_ERROR_DATA_HIGH				    0x130
+#define MV64360_CPU_ERROR_PARITY				    0x138
+#define MV64360_CPU_ERROR_CAUSE					    0x140
+#define MV64360_CPU_ERROR_MASK					    0x148
+
+/****************************************/
+/*	CPU Interface Debug Registers	*/
+/****************************************/
+
+#define MV64360_PUNIT_SLAVE_DEBUG_LOW				    0x360
+#define MV64360_PUNIT_SLAVE_DEBUG_HIGH				    0x368
+#define MV64360_PUNIT_MASTER_DEBUG_LOW				    0x370
+#define MV64360_PUNIT_MASTER_DEBUG_HIGH				    0x378
+#define MV64360_PUNIT_MMASK					    0x3e4
+
+/****************************************/
+/*  Integrated SRAM Registers		*/
+/****************************************/
+
+#define MV64360_SRAM_CONFIG					    0x380
+#define MV64360_SRAM_TEST_MODE					    0X3F4
+#define MV64360_SRAM_ERROR_CAUSE				    0x388
+#define MV64360_SRAM_ERROR_ADDR					    0x390
+#define MV64360_SRAM_ERROR_ADDR_HIGH				    0X3F8
+#define MV64360_SRAM_ERROR_DATA_LOW				    0x398
+#define MV64360_SRAM_ERROR_DATA_HIGH				    0x3a0
+#define MV64360_SRAM_ERROR_DATA_PARITY				    0x3a8
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+#define MV64360_SDRAM_CONFIG					    0x1400
+#define MV64360_D_UNIT_CONTROL_LOW				    0x1404
+#define MV64360_D_UNIT_CONTROL_HIGH				    0x1424
+#define MV64360_SDRAM_TIMING_CONTROL_LOW			    0x1408
+#define MV64360_SDRAM_TIMING_CONTROL_HIGH			    0x140c
+#define MV64360_SDRAM_ADDR_CONTROL				    0x1410
+#define MV64360_SDRAM_OPEN_PAGES_CONTROL			    0x1414
+#define MV64360_SDRAM_OPERATION					    0x1418
+#define MV64360_SDRAM_MODE					    0x141c
+#define MV64360_EXTENDED_DRAM_MODE				    0x1420
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_LOW			    0x1430
+#define MV64360_SDRAM_CROSS_BAR_CONTROL_HIGH			    0x1434
+#define MV64360_SDRAM_CROSS_BAR_TIMEOUT				    0x1438
+#define MV64360_SDRAM_ADDR_CTRL_PADS_CALIBRATION		    0x14c0
+#define MV64360_SDRAM_DATA_PADS_CALIBRATION			    0x14c4
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define MV64360_SDRAM_ERROR_DATA_LOW				    0x1444
+#define MV64360_SDRAM_ERROR_DATA_HIGH				    0x1440
+#define MV64360_SDRAM_ERROR_ADDR				    0x1450
+#define MV64360_SDRAM_RECEIVED_ECC				    0x1448
+#define MV64360_SDRAM_CALCULATED_ECC				    0x144c
+#define MV64360_SDRAM_ECC_CONTROL				    0x1454
+#define MV64360_SDRAM_ECC_ERROR_COUNTER				    0x1458
+
+/******************************************/
+/*  Controlled Delay Line (CDL) Registers */
+/******************************************/
+
+#define MV64360_DFCDL_CONFIG0					    0x1480
+#define MV64360_DFCDL_CONFIG1					    0x1484
+#define MV64360_DLL_WRITE					    0x1488
+#define MV64360_DLL_READ					    0x148c
+#define MV64360_SRAM_ADDR					    0x1490
+#define MV64360_SRAM_DATA0					    0x1494
+#define MV64360_SRAM_DATA1					    0x1498
+#define MV64360_SRAM_DATA2					    0x149c
+#define MV64360_DFCL_PROBE					    0x14a0
+
+/******************************************/
+/*   Debug Registers			  */
+/******************************************/
+
+#define MV64360_DUNIT_DEBUG_LOW					    0x1460
+#define MV64360_DUNIT_DEBUG_HIGH				    0x1464
+#define MV64360_DUNIT_MMASK					    0X1b40
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define MV64360_DEVICE_BANK0_PARAMETERS				    0x45c
+#define MV64360_DEVICE_BANK1_PARAMETERS				    0x460
+#define MV64360_DEVICE_BANK2_PARAMETERS				    0x464
+#define MV64360_DEVICE_BANK3_PARAMETERS				    0x468
+#define MV64360_DEVICE_BOOT_BANK_PARAMETERS			    0x46c
+#define MV64360_DEVICE_INTERFACE_CONTROL			    0x4c0
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW		    0x4c8
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH		    0x4cc
+#define MV64360_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT		    0x4c4
+
+/****************************************/
+/* Device interrupt registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_INTERRUPT_CAUSE				    0x4d0
+#define MV64360_DEVICE_INTERRUPT_MASK				    0x4d4
+#define MV64360_DEVICE_ERROR_ADDR				    0x4d8
+#define MV64360_DEVICE_ERROR_DATA				    0x4dc
+#define MV64360_DEVICE_ERROR_PARITY				    0x4e0
+
+/****************************************/
+/* Device debug registers		*/
+/****************************************/
+
+#define MV64360_DEVICE_DEBUG_LOW				    0x4e4
+#define MV64360_DEVICE_DEBUG_HIGH				    0x4e8
+#define MV64360_RUNIT_MMASK					    0x4f0
+
+/****************************************/
+/* PCI Slave Address Decoding registers */
+/****************************************/
+
+#define MV64360_PCI_0_CS_0_BANK_SIZE				    0xc08
+#define MV64360_PCI_1_CS_0_BANK_SIZE				    0xc88
+#define MV64360_PCI_0_CS_1_BANK_SIZE				    0xd08
+#define MV64360_PCI_1_CS_1_BANK_SIZE				    0xd88
+#define MV64360_PCI_0_CS_2_BANK_SIZE				    0xc0c
+#define MV64360_PCI_1_CS_2_BANK_SIZE				    0xc8c
+#define MV64360_PCI_0_CS_3_BANK_SIZE				    0xd0c
+#define MV64360_PCI_1_CS_3_BANK_SIZE				    0xd8c
+#define MV64360_PCI_0_DEVCS_0_BANK_SIZE				    0xc10
+#define MV64360_PCI_1_DEVCS_0_BANK_SIZE				    0xc90
+#define MV64360_PCI_0_DEVCS_1_BANK_SIZE				    0xd10
+#define MV64360_PCI_1_DEVCS_1_BANK_SIZE				    0xd90
+#define MV64360_PCI_0_DEVCS_2_BANK_SIZE				    0xd18
+#define MV64360_PCI_1_DEVCS_2_BANK_SIZE				    0xd98
+#define MV64360_PCI_0_DEVCS_3_BANK_SIZE				    0xc14
+#define MV64360_PCI_1_DEVCS_3_BANK_SIZE				    0xc94
+#define MV64360_PCI_0_DEVCS_BOOT_BANK_SIZE			    0xd14
+#define MV64360_PCI_1_DEVCS_BOOT_BANK_SIZE			    0xd94
+#define MV64360_PCI_0_P2P_MEM0_BAR_SIZE				    0xd1c
+#define MV64360_PCI_1_P2P_MEM0_BAR_SIZE				    0xd9c
+#define MV64360_PCI_0_P2P_MEM1_BAR_SIZE				    0xd20
+#define MV64360_PCI_1_P2P_MEM1_BAR_SIZE				    0xda0
+#define MV64360_PCI_0_P2P_I_O_BAR_SIZE				    0xd24
+#define MV64360_PCI_1_P2P_I_O_BAR_SIZE				    0xda4
+#define MV64360_PCI_0_CPU_BAR_SIZE				    0xd28
+#define MV64360_PCI_1_CPU_BAR_SIZE				    0xda8
+#define MV64360_PCI_0_INTERNAL_SRAM_BAR_SIZE			    0xe00
+#define MV64360_PCI_1_INTERNAL_SRAM_BAR_SIZE			    0xe80
+#define MV64360_PCI_0_EXPANSION_ROM_BAR_SIZE			    0xd2c
+#define MV64360_PCI_1_EXPANSION_ROM_BAR_SIZE			    0xd9c
+#define MV64360_PCI_0_BASE_ADDR_REG_ENABLE			    0xc3c
+#define MV64360_PCI_1_BASE_ADDR_REG_ENABLE			    0xcbc
+#define MV64360_PCI_0_CS_0_BASE_ADDR_REMAP			    0xc48
+#define MV64360_PCI_1_CS_0_BASE_ADDR_REMAP			    0xcc8
+#define MV64360_PCI_0_CS_1_BASE_ADDR_REMAP			    0xd48
+#define MV64360_PCI_1_CS_1_BASE_ADDR_REMAP			    0xdc8
+#define MV64360_PCI_0_CS_2_BASE_ADDR_REMAP			    0xc4c
+#define MV64360_PCI_1_CS_2_BASE_ADDR_REMAP			    0xccc
+#define MV64360_PCI_0_CS_3_BASE_ADDR_REMAP			    0xd4c
+#define MV64360_PCI_1_CS_3_BASE_ADDR_REMAP			    0xdcc
+#define MV64360_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP			    0xF04
+#define MV64360_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP			    0xF84
+#define MV64360_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP			    0xF08
+#define MV64360_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP			    0xF88
+#define MV64360_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP			    0xF0C
+#define MV64360_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP			    0xF8C
+#define MV64360_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP			    0xF10
+#define MV64360_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP			    0xF90
+#define MV64360_PCI_0_DEVCS_0_BASE_ADDR_REMAP			    0xc50
+#define MV64360_PCI_1_DEVCS_0_BASE_ADDR_REMAP			    0xcd0
+#define MV64360_PCI_0_DEVCS_1_BASE_ADDR_REMAP			    0xd50
+#define MV64360_PCI_1_DEVCS_1_BASE_ADDR_REMAP			    0xdd0
+#define MV64360_PCI_0_DEVCS_2_BASE_ADDR_REMAP			    0xd58
+#define MV64360_PCI_1_DEVCS_2_BASE_ADDR_REMAP			    0xdd8
+#define MV64360_PCI_0_DEVCS_3_BASE_ADDR_REMAP			    0xc54
+#define MV64360_PCI_1_DEVCS_3_BASE_ADDR_REMAP			    0xcd4
+#define MV64360_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xd54
+#define MV64360_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP		    0xdd4
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xd5c
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW		    0xddc
+#define MV64360_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xd60
+#define MV64360_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH		    0xde0
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xd64
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW		    0xde4
+#define MV64360_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xd68
+#define MV64360_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH		    0xde8
+#define MV64360_PCI_0_P2P_I_O_BASE_ADDR_REMAP			    0xd6c
+#define MV64360_PCI_1_P2P_I_O_BASE_ADDR_REMAP			    0xdec
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_LOW			    0xd70
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_LOW			    0xdf0
+#define MV64360_PCI_0_CPU_BASE_ADDR_REMAP_HIGH			    0xd74
+#define MV64360_PCI_1_CPU_BASE_ADDR_REMAP_HIGH			    0xdf4
+#define MV64360_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf00
+#define MV64360_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP		    0xf80
+#define MV64360_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP		    0xf38
+#define MV64360_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP		    0xfb8
+#define MV64360_PCI_0_ADDR_DECODE_CONTROL			    0xd3c
+#define MV64360_PCI_1_ADDR_DECODE_CONTROL			    0xdbc
+#define MV64360_PCI_0_HEADERS_RETARGET_CONTROL			    0xF40
+#define MV64360_PCI_1_HEADERS_RETARGET_CONTROL			    0xFc0
+#define MV64360_PCI_0_HEADERS_RETARGET_BASE			    0xF44
+#define MV64360_PCI_1_HEADERS_RETARGET_BASE			    0xFc4
+#define MV64360_PCI_0_HEADERS_RETARGET_HIGH			    0xF48
+#define MV64360_PCI_1_HEADERS_RETARGET_HIGH			    0xFc8
+
+/***********************************/
+/*   PCI Control Register Map	   */
+/***********************************/
+
+#define MV64360_PCI_0_DLL_STATUS_AND_COMMAND			    0x1d20
+#define MV64360_PCI_1_DLL_STATUS_AND_COMMAND			    0x1da0
+#define MV64360_PCI_0_MPP_PADS_DRIVE_CONTROL			    0x1d1C
+#define MV64360_PCI_1_MPP_PADS_DRIVE_CONTROL			    0x1d9C
+#define MV64360_PCI_0_COMMAND					    0xc00
+#define MV64360_PCI_1_COMMAND					    0xc80
+#define MV64360_PCI_0_MODE					    0xd00
+#define MV64360_PCI_1_MODE					    0xd80
+#define MV64360_PCI_0_RETRY					    0xc04
+#define MV64360_PCI_1_RETRY					    0xc84
+#define MV64360_PCI_0_READ_BUFFER_DISCARD_TIMER			    0xd04
+#define MV64360_PCI_1_READ_BUFFER_DISCARD_TIMER			    0xd84
+#define MV64360_PCI_0_MSI_TRIGGER_TIMER				    0xc38
+#define MV64360_PCI_1_MSI_TRIGGER_TIMER				    0xcb8
+#define MV64360_PCI_0_ARBITER_CONTROL				    0x1d00
+#define MV64360_PCI_1_ARBITER_CONTROL				    0x1d80
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_LOW			    0x1d08
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_LOW			    0x1d88
+#define MV64360_PCI_0_CROSS_BAR_CONTROL_HIGH			    0x1d0c
+#define MV64360_PCI_1_CROSS_BAR_CONTROL_HIGH			    0x1d8c
+#define MV64360_PCI_0_CROSS_BAR_TIMEOUT				    0x1d04
+#define MV64360_PCI_1_CROSS_BAR_TIMEOUT				    0x1d84
+#define MV64360_PCI_0_SYNC_BARRIER_TRIGGER_REG			    0x1D18
+#define MV64360_PCI_1_SYNC_BARRIER_TRIGGER_REG			    0x1D98
+#define MV64360_PCI_0_SYNC_BARRIER_VIRTUAL_REG			    0x1d10
+#define MV64360_PCI_1_SYNC_BARRIER_VIRTUAL_REG			    0x1d90
+#define MV64360_PCI_0_P2P_CONFIG				    0x1d14
+#define MV64360_PCI_1_P2P_CONFIG				    0x1d94
+
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_LOW			    0x1e00
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_0_HIGH		    0x1e04
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_0			    0x1e08
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_LOW			    0x1e10
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_1_HIGH		    0x1e14
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_1			    0x1e18
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_LOW			    0x1e20
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_2_HIGH		    0x1e24
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_2			    0x1e28
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_LOW			    0x1e30
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_3_HIGH		    0x1e34
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_3			    0x1e38
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_LOW			    0x1e40
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_4_HIGH		    0x1e44
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_4			    0x1e48
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_LOW			    0x1e50
+#define MV64360_PCI_0_ACCESS_CONTROL_BASE_5_HIGH		    0x1e54
+#define MV64360_PCI_0_ACCESS_CONTROL_SIZE_5			    0x1e58
+
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_LOW			    0x1e80
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_0_HIGH		    0x1e84
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_0			    0x1e88
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_LOW			    0x1e90
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_1_HIGH		    0x1e94
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_1			    0x1e98
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_LOW			    0x1ea0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_2_HIGH		    0x1ea4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_2			    0x1ea8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_LOW			    0x1eb0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_3_HIGH		    0x1eb4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_3			    0x1eb8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_LOW			    0x1ec0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_4_HIGH		    0x1ec4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_4			    0x1ec8
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_LOW			    0x1ed0
+#define MV64360_PCI_1_ACCESS_CONTROL_BASE_5_HIGH		    0x1ed4
+#define MV64360_PCI_1_ACCESS_CONTROL_SIZE_5			    0x1ed8
+
+/****************************************/
+/*   PCI Configuration Access Registers */
+/****************************************/
+
+#define MV64360_PCI_0_CONFIG_ADDR				    0xcf8
+#define MV64360_PCI_0_CONFIG_DATA_VIRTUAL_REG			    0xcfc
+#define MV64360_PCI_1_CONFIG_ADDR				    0xc78
+#define MV64360_PCI_1_CONFIG_DATA_VIRTUAL_REG			    0xc7c
+#define MV64360_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xc34
+#define MV64360_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG		    0xcb4
+
+/****************************************/
+/*   PCI Error Report Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_SERR_MASK					    0xc28
+#define MV64360_PCI_1_SERR_MASK					    0xca8
+#define MV64360_PCI_0_ERROR_ADDR_LOW				    0x1d40
+#define MV64360_PCI_1_ERROR_ADDR_LOW				    0x1dc0
+#define MV64360_PCI_0_ERROR_ADDR_HIGH				    0x1d44
+#define MV64360_PCI_1_ERROR_ADDR_HIGH				    0x1dc4
+#define MV64360_PCI_0_ERROR_ATTRIBUTE				    0x1d48
+#define MV64360_PCI_1_ERROR_ATTRIBUTE				    0x1dc8
+#define MV64360_PCI_0_ERROR_COMMAND				    0x1d50
+#define MV64360_PCI_1_ERROR_COMMAND				    0x1dd0
+#define MV64360_PCI_0_ERROR_CAUSE				    0x1d58
+#define MV64360_PCI_1_ERROR_CAUSE				    0x1dd8
+#define MV64360_PCI_0_ERROR_MASK				    0x1d5c
+#define MV64360_PCI_1_ERROR_MASK				    0x1ddc
+
+/****************************************/
+/*   PCI Debug Registers		*/
+/****************************************/
+
+#define MV64360_PCI_0_MMASK					    0X1D24
+#define MV64360_PCI_1_MMASK					    0X1DA4
+
+/*********************************************/
+/* PCI Configuration, Function 0, Registers  */
+/*********************************************/
+
+#define MV64360_PCI_DEVICE_AND_VENDOR_ID			    0x000
+#define MV64360_PCI_STATUS_AND_COMMAND				    0x004
+#define MV64360_PCI_CLASS_CODE_AND_REVISION_ID			    0x008
+#define MV64360_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	    0x00C
+
+#define MV64360_PCI_SCS_0_BASE_ADDR_LOW				    0x010
+#define MV64360_PCI_SCS_0_BASE_ADDR_HIGH			    0x014
+#define MV64360_PCI_SCS_1_BASE_ADDR_LOW				    0x018
+#define MV64360_PCI_SCS_1_BASE_ADDR_HIGH			    0x01C
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW	    0x020
+#define MV64360_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH	    0x024
+#define MV64360_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	    0x02c
+#define MV64360_PCI_EXPANSION_ROM_BASE_ADDR_REG			    0x030
+#define MV64360_PCI_CAPABILTY_LIST_POINTER			    0x034
+#define MV64360_PCI_INTERRUPT_PIN_AND_LINE			    0x03C
+       /* capability list */
+#define MV64360_PCI_POWER_MANAGEMENT_CAPABILITY			    0x040
+#define MV64360_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		    0x044
+#define MV64360_PCI_VPD_ADDR					    0x048
+#define MV64360_PCI_VPD_DATA					    0x04c
+#define MV64360_PCI_MSI_MESSAGE_CONTROL				    0x050
+#define MV64360_PCI_MSI_MESSAGE_ADDR				    0x054
+#define MV64360_PCI_MSI_MESSAGE_UPPER_ADDR			    0x058
+#define MV64360_PCI_MSI_MESSAGE_DATA				    0x05c
+#define MV64360_PCI_X_COMMAND					    0x060
+#define MV64360_PCI_X_STATUS					    0x064
+#define MV64360_PCI_COMPACT_PCI_HOT_SWAP			    0x068
+
+/***********************************************/
+/*   PCI Configuration, Function 1, Registers  */
+/***********************************************/
+
+#define MV64360_PCI_SCS_2_BASE_ADDR_LOW				    0x110
+#define MV64360_PCI_SCS_2_BASE_ADDR_HIGH			    0x114
+#define MV64360_PCI_SCS_3_BASE_ADDR_LOW				    0x118
+#define MV64360_PCI_SCS_3_BASE_ADDR_HIGH			    0x11c
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_LOW			    0x120
+#define MV64360_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH		    0x124
+
+/***********************************************/
+/*  PCI Configuration, Function 2, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_LOW			    0x210
+#define MV64360_PCI_DEVCS_0_BASE_ADDR_HIGH			    0x214
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_LOW			    0x218
+#define MV64360_PCI_DEVCS_1_BASE_ADDR_HIGH			    0x21c
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_LOW			    0x220
+#define MV64360_PCI_DEVCS_2_BASE_ADDR_HIGH			    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 3, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_LOW			    0x310
+#define MV64360_PCI_DEVCS_3_BASE_ADDR_HIGH			    0x314
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_LOW			    0x318
+#define MV64360_PCI_BOOT_CS_BASE_ADDR_HIGH			    0x31c
+#define MV64360_PCI_CPU_BASE_ADDR_LOW				    0x220
+#define MV64360_PCI_CPU_BASE_ADDR_HIGH				    0x224
+
+/***********************************************/
+/*  PCI Configuration, Function 4, Registers   */
+/***********************************************/
+
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_LOW			    0x410
+#define MV64360_PCI_P2P_MEM0_BASE_ADDR_HIGH			    0x414
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_LOW			    0x418
+#define MV64360_PCI_P2P_MEM1_BASE_ADDR_HIGH			    0x41c
+#define MV64360_PCI_P2P_I_O_BASE_ADDR				    0x420
+#define MV64360_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR		    0x424
+
+/****************************************/
+/* Messaging Unit Registers (I20)	*/
+/****************************************/
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x010
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x014
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE		    0x018
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE		    0x01C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE		    0x020
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x024
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x028
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE		    0x02C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE	    0x030
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE	    0x034
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x040
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE	    0x044
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE		    0x050
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE		    0x054
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x060
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x064
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x068
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x06C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE	    0x070
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE	    0x074
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE	    0x0F8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE	    0x0FC
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x090
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x094
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE		    0x098
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE		    0x09C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0A0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0A4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0A8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE		    0x0AC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE	    0x0B0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE	    0x0B4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE	    0x0C4
+#define MV64360_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE		    0x0D0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE		    0x0D4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0E4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x0E8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x0EC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE	    0x0F0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE	    0x0F4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE	    0x078
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE	    0x07C
+
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C10
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C14
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE		    0x1C18
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE		    0x1C1C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C20
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C24
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C28
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE		    0x1C2C
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE	    0x1C30
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE	    0x1C34
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C40
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE	    0x1C44
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU0_SIDE			    0x1C50
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE		    0x1C54
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C60
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C64
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1C68
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1C6C
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE	    0x1C70
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE	    0x1C74
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE	    0x1CF8
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE	    0x1CFC
+#define MV64360_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C90
+#define MV64360_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C94
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE		    0x1C98
+#define MV64360_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE		    0x1C9C
+#define MV64360_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CA0
+#define MV64360_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CA4
+#define MV64360_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CA8
+#define MV64360_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE		    0x1CAC
+#define MV64360_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE	    0x1CB0
+#define MV64360_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE	    0x1CB4
+#define MV64360_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC0
+#define MV64360_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE	    0x1CC4
+#define MV64360_I2O_QUEUE_CONTROL_REG_CPU1_SIDE			    0x1CD0
+#define MV64360_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE		    0x1CD4
+#define MV64360_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE0
+#define MV64360_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CE4
+#define MV64360_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1CE8
+#define MV64360_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1CEC
+#define MV64360_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE	    0x1CF0
+#define MV64360_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE	    0x1CF4
+#define MV64360_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE	    0x1C78
+#define MV64360_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE	    0x1C7C
+
+/****************************************/
+/*	  Ethernet Unit Registers		*/
+/****************************************/
+
+#define MV64360_ETH_PHY_ADDR_REG				    0x2000
+#define MV64360_ETH_SMI_REG					    0x2004
+#define MV64360_ETH_UNIT_DEFAULT_ADDR_REG			    0x2008
+#define MV64360_ETH_UNIT_DEFAULTID_REG				    0x200c
+#define MV64360_ETH_UNIT_INTERRUPT_CAUSE_REG			    0x2080
+#define MV64360_ETH_UNIT_INTERRUPT_MASK_REG			    0x2084
+#define MV64360_ETH_UNIT_INTERNAL_USE_REG			    0x24fc
+#define MV64360_ETH_UNIT_ERROR_ADDR_REG				    0x2094
+#define MV64360_ETH_BAR_0					    0x2200
+#define MV64360_ETH_BAR_1					    0x2208
+#define MV64360_ETH_BAR_2					    0x2210
+#define MV64360_ETH_BAR_3					    0x2218
+#define MV64360_ETH_BAR_4					    0x2220
+#define MV64360_ETH_BAR_5					    0x2228
+#define MV64360_ETH_SIZE_REG_0					    0x2204
+#define MV64360_ETH_SIZE_REG_1					    0x220c
+#define MV64360_ETH_SIZE_REG_2					    0x2214
+#define MV64360_ETH_SIZE_REG_3					    0x221c
+#define MV64360_ETH_SIZE_REG_4					    0x2224
+#define MV64360_ETH_SIZE_REG_5					    0x222c
+#define MV64360_ETH_HEADERS_RETARGET_BASE_REG			    0x2230
+#define MV64360_ETH_HEADERS_RETARGET_CONTROL_REG		    0x2234
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_0			    0x2280
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_1			    0x2284
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_2			    0x2288
+#define MV64360_ETH_HIGH_ADDR_REMAP_REG_3			    0x228c
+#define MV64360_ETH_BASE_ADDR_ENABLE_REG			    0x2290
+#define MV64360_ETH_ACCESS_PROTECTION_REG(port)			   (0x2294 + (port<<2))
+#define MV64360_ETH_MIB_COUNTERS_BASE(port)			   (0x3000 + (port<<7))
+#define MV64360_ETH_PORT_CONFIG_REG(port)			   (0x2400 + (port<<10))
+#define MV64360_ETH_PORT_CONFIG_EXTEND_REG(port)		   (0x2404 + (port<<10))
+#define MV64360_ETH_MII_SERIAL_PARAMETRS_REG(port)		   (0x2408 + (port<<10))
+#define MV64360_ETH_GMII_SERIAL_PARAMETRS_REG(port)		   (0x240c + (port<<10))
+#define MV64360_ETH_VLAN_ETHERTYPE_REG(port)			   (0x2410 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_LOW(port)				   (0x2414 + (port<<10))
+#define MV64360_ETH_MAC_ADDR_HIGH(port)				   (0x2418 + (port<<10))
+#define MV64360_ETH_SDMA_CONFIG_REG(port)			   (0x241c + (port<<10))
+#define MV64360_ETH_DSCP_0(port)				   (0x2420 + (port<<10))
+#define MV64360_ETH_DSCP_1(port)				   (0x2424 + (port<<10))
+#define MV64360_ETH_DSCP_2(port)				   (0x2428 + (port<<10))
+#define MV64360_ETH_DSCP_3(port)				   (0x242c + (port<<10))
+#define MV64360_ETH_DSCP_4(port)				   (0x2430 + (port<<10))
+#define MV64360_ETH_DSCP_5(port)				   (0x2434 + (port<<10))
+#define MV64360_ETH_DSCP_6(port)				   (0x2438 + (port<<10))
+#define MV64360_ETH_PORT_SERIAL_CONTROL_REG(port)		   (0x243c + (port<<10))
+#define MV64360_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)		   (0x2440 + (port<<10))
+#define MV64360_ETH_PORT_STATUS_REG(port)			   (0x2444 + (port<<10))
+#define MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(port)		   (0x2448 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_FIXED_PRIORITY(port)		   (0x244c + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port)	   (0x2450 + (port<<10))
+#define MV64360_ETH_MAXIMUM_TRANSMIT_UNIT(port)			   (0x2458 + (port<<10))
+#define MV64360_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port)	   (0x245c + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_REG(port)			   (0x2460 + (port<<10))
+#define MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG(port)		   (0x2464 + (port<<10))
+#define MV64360_ETH_INTERRUPT_MASK_REG(port)			   (0x2468 + (port<<10))
+#define MV64360_ETH_INTERRUPT_EXTEND_MASK_REG(port)		   (0x246c + (port<<10))
+#define MV64360_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2470 + (port<<10))
+#define MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port)		   (0x2474 + (port<<10))
+#define MV64360_ETH_RX_MINIMAL_FRAME_SIZE_REG(port)		   (0x247c + (port<<10))
+#define MV64360_ETH_RX_DISCARDED_FRAMES_COUNTER(port)		   (0x2484 + (port<<10)
+#define MV64360_ETH_PORT_DEBUG_0_REG(port)			   (0x248c + (port<<10))
+#define MV64360_ETH_PORT_DEBUG_1_REG(port)			   (0x2490 + (port<<10))
+#define MV64360_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port)		   (0x2494 + (port<<10))
+#define MV64360_ETH_INTERNAL_USE_REG(port)			   (0x24fc + (port<<10))
+#define MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(port)		   (0x2680 + (port<<10))
+#define MV64360_ETH_CURRENT_SERVED_TX_DESC_PTR(port)		   (0x2684 + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x260c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x261c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x262c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x263c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x264c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x265c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x266c + (port<<10))
+#define MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x267c + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)		   (0x26c0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port)		   (0x26c4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port)		   (0x26c8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port)		   (0x26cc + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port)		   (0x26d0 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port)		   (0x26d4 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port)		   (0x26d8 + (port<<10))
+#define MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port)		   (0x26dc + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port)		   (0x2700 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port)		   (0x2710 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port)		   (0x2720 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port)		   (0x2730 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port)		   (0x2740 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port)		   (0x2750 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port)		   (0x2760 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port)		   (0x2770 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port)	   (0x2704 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port)	   (0x2714 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port)	   (0x2724 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port)	   (0x2734 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port)	   (0x2744 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port)	   (0x2754 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port)	   (0x2764 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port)	   (0x2774 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_0_ARBITER_CONFIG(port)		   (0x2708 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_1_ARBITER_CONFIG(port)		   (0x2718 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_2_ARBITER_CONFIG(port)		   (0x2728 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_3_ARBITER_CONFIG(port)		   (0x2738 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_4_ARBITER_CONFIG(port)		   (0x2748 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_5_ARBITER_CONFIG(port)		   (0x2758 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_6_ARBITER_CONFIG(port)		   (0x2768 + (port<<10))
+#define MV64360_ETH_TX_QUEUE_7_ARBITER_CONFIG(port)		   (0x2778 + (port<<10))
+#define MV64360_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port)		   (0x2780 + (port<<10))
+#define MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
+#define MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)	   (0x3500 + (port<<10))
+#define MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)		   (0x3600 + (port<<10))
+
+/*******************************************/
+/*	    CUNIT  Registers		   */
+/*******************************************/
+
+	 /* Address Decoding Register Map */
+
+#define MV64360_CUNIT_BASE_ADDR_REG0				    0xf200
+#define MV64360_CUNIT_BASE_ADDR_REG1				    0xf208
+#define MV64360_CUNIT_BASE_ADDR_REG2				    0xf210
+#define MV64360_CUNIT_BASE_ADDR_REG3				    0xf218
+#define MV64360_CUNIT_SIZE0					    0xf204
+#define MV64360_CUNIT_SIZE1					    0xf20c
+#define MV64360_CUNIT_SIZE2					    0xf214
+#define MV64360_CUNIT_SIZE3					    0xf21c
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG0			    0xf240
+#define MV64360_CUNIT_HIGH_ADDR_REMAP_REG1			    0xf244
+#define MV64360_CUNIT_BASE_ADDR_ENABLE_REG			    0xf250
+#define MV64360_MPSC0_ACCESS_PROTECTION_REG			    0xf254
+#define MV64360_MPSC1_ACCESS_PROTECTION_REG			    0xf258
+#define MV64360_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG		    0xf25C
+
+	/*  Error Report Registers  */
+
+#define MV64360_CUNIT_INTERRUPT_CAUSE_REG			    0xf310
+#define MV64360_CUNIT_INTERRUPT_MASK_REG			    0xf314
+#define MV64360_CUNIT_ERROR_ADDR				    0xf318
+
+	/*  Cunit Control Registers */
+
+#define MV64360_CUNIT_ARBITER_CONTROL_REG			    0xf300
+#define MV64360_CUNIT_CONFIG_REG				    0xb40c
+#define MV64360_CUNIT_CRROSBAR_TIMEOUT_REG			    0xf304
+
+	/*  Cunit Debug Registers   */
+
+#define MV64360_CUNIT_DEBUG_LOW					    0xf340
+#define MV64360_CUNIT_DEBUG_HIGH				    0xf344
+#define MV64360_CUNIT_MMASK					    0xf380
+
+	/*  Cunit Base Address Enable Window Bits*/
+#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
+#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
+#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
+#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3
+
+	/*  MPSCs Clocks Routing Registers  */
+
+#define MV64360_MPSC_ROUTING_REG				    0xb400
+#define MV64360_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
+#define MV64360_MPSC_TX_CLOCK_ROUTING_REG			    0xb408
+
+	/*  MPSCs Interrupts Registers	  */
+
+#define MV64360_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
+#define MV64360_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))
+
+#define MV64360_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
+#define MV64360_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
+#define MV64360_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
+#define MV64360_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))
+
+	/*  MPSC0 Registers	 */
+
+
+/***************************************/
+/*	    SDMA Registers	       */
+/***************************************/
+
+#define MV64360_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
+#define MV64360_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
+#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
+#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
+#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))
+
+#define MV64360_SDMA_CAUSE_REG					    0xb800
+#define MV64360_SDMA_MASK_REG					    0xb880
+
+
+/****************************************/
+/* SDMA Address Space Targets		*/
+/****************************************/
+
+#define MV64360_SDMA_DRAM_CS_0_TARGET				    0x0e00
+#define MV64360_SDMA_DRAM_CS_1_TARGET				    0x0d00
+#define MV64360_SDMA_DRAM_CS_2_TARGET				    0x0b00
+#define MV64360_SDMA_DRAM_CS_3_TARGET				    0x0700
+
+#define MV64360_SDMA_DEV_CS_0_TARGET				    0x1e01
+#define MV64360_SDMA_DEV_CS_1_TARGET				    0x1d01
+#define MV64360_SDMA_DEV_CS_2_TARGET				    0x1b01
+#define MV64360_SDMA_DEV_CS_3_TARGET				    0x1701
+
+#define MV64360_SDMA_BOOT_CS_TARGET				    0x0f00
+
+#define MV64360_SDMA_SRAM_TARGET				    0x0003
+#define MV64360_SDMA_60X_BUS_TARGET				    0x4003
+
+#define MV64360_PCI_0_TARGET					    0x0003
+#define MV64360_PCI_1_TARGET					    0x0004
+
+
+/* Devices BAR and size registers */
+
+#define MV64360_DEV_CS0_BASE_ADDR				    0x028
+#define MV64360_DEV_CS0_SIZE					    0x030
+#define MV64360_DEV_CS1_BASE_ADDR				    0x228
+#define MV64360_DEV_CS1_SIZE					    0x230
+#define MV64360_DEV_CS2_BASE_ADDR				    0x248
+#define MV64360_DEV_CS2_SIZE					    0x250
+#define MV64360_DEV_CS3_BASE_ADDR				    0x038
+#define MV64360_DEV_CS3_SIZE					    0x040
+#define MV64360_BOOTCS_BASE_ADDR				    0x238
+#define MV64360_BOOTCS_SIZE					    0x240
+
+/* SDMA Window access protection */
+#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
+#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
+#define MV64360_SDMA_WIN_ACCESS_FULL 2
+
+/* BRG Interrupts */
+
+#define MV64360_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
+#define MV64360_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
+#define MV64360_BRG_CAUSE_REG					    0xb834
+#define MV64360_BRG_MASK_REG					    0xb8b4
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_CONTROL				    0x840
+#define MV64360_DMA_CHANNEL0_CONTROL_HIGH			    0x880
+#define MV64360_DMA_CHANNEL1_CONTROL				    0x844
+#define MV64360_DMA_CHANNEL1_CONTROL_HIGH			    0x884
+#define MV64360_DMA_CHANNEL2_CONTROL				    0x848
+#define MV64360_DMA_CHANNEL2_CONTROL_HIGH			    0x888
+#define MV64360_DMA_CHANNEL3_CONTROL				    0x84C
+#define MV64360_DMA_CHANNEL3_CONTROL_HIGH			    0x88C
+
+
+/****************************************/
+/*	     IDMA Registers		*/
+/****************************************/
+
+#define MV64360_DMA_CHANNEL0_BYTE_COUNT				    0x800
+#define MV64360_DMA_CHANNEL1_BYTE_COUNT				    0x804
+#define MV64360_DMA_CHANNEL2_BYTE_COUNT				    0x808
+#define MV64360_DMA_CHANNEL3_BYTE_COUNT				    0x80C
+#define MV64360_DMA_CHANNEL0_SOURCE_ADDR			    0x810
+#define MV64360_DMA_CHANNEL1_SOURCE_ADDR			    0x814
+#define MV64360_DMA_CHANNEL2_SOURCE_ADDR			    0x818
+#define MV64360_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
+#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
+#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
+#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
+#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
+#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
+#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
+#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
+#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
+#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
+#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
+#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
+#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C
+
+ /*  IDMA Address Decoding Base Address Registers  */
+
+#define MV64360_DMA_BASE_ADDR_REG0				    0xa00
+#define MV64360_DMA_BASE_ADDR_REG1				    0xa08
+#define MV64360_DMA_BASE_ADDR_REG2				    0xa10
+#define MV64360_DMA_BASE_ADDR_REG3				    0xa18
+#define MV64360_DMA_BASE_ADDR_REG4				    0xa20
+#define MV64360_DMA_BASE_ADDR_REG5				    0xa28
+#define MV64360_DMA_BASE_ADDR_REG6				    0xa30
+#define MV64360_DMA_BASE_ADDR_REG7				    0xa38
+
+ /*  IDMA Address Decoding Size Address Register   */
+
+#define MV64360_DMA_SIZE_REG0					    0xa04
+#define MV64360_DMA_SIZE_REG1					    0xa0c
+#define MV64360_DMA_SIZE_REG2					    0xa14
+#define MV64360_DMA_SIZE_REG3					    0xa1c
+#define MV64360_DMA_SIZE_REG4					    0xa24
+#define MV64360_DMA_SIZE_REG5					    0xa2c
+#define MV64360_DMA_SIZE_REG6					    0xa34
+#define MV64360_DMA_SIZE_REG7					    0xa3C
+
+ /* IDMA Address Decoding High Address Remap and Access
+		  Protection Registers			  */
+
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
+#define MV64360_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
+#define MV64360_DMA_BASE_ADDR_ENABLE_REG			    0xa80
+#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
+#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
+#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
+#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
+#define MV64360_DMA_ARBITER_CONTROL				    0x860
+#define MV64360_DMA_CROSS_BAR_TIMEOUT				    0x8d0
+
+ /*  IDMA Headers Retarget Registers   */
+
+#define MV64360_DMA_HEADERS_RETARGET_CONTROL			    0xa84
+#define MV64360_DMA_HEADERS_RETARGET_BASE			    0xa88
+
+ /*  IDMA Interrupt Register  */
+
+#define MV64360_DMA_INTERRUPT_CAUSE_REG				    0x8c0
+#define MV64360_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
+#define MV64360_DMA_ERROR_ADDR					    0x8c8
+#define MV64360_DMA_ERROR_SELECT				    0x8cc
+
+ /*  IDMA Debug Register ( for internal use )	 */
+
+#define MV64360_DMA_DEBUG_LOW					    0x8e0
+#define MV64360_DMA_DEBUG_HIGH					    0x8e4
+#define MV64360_DMA_SPARE					    0xA8C
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define MV64360_TIMER_COUNTER0					    0x850
+#define MV64360_TIMER_COUNTER1					    0x854
+#define MV64360_TIMER_COUNTER2					    0x858
+#define MV64360_TIMER_COUNTER3					    0x85C
+#define MV64360_TIMER_COUNTER_0_3_CONTROL			    0x864
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
+#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c
+
+/****************************************/
+/*	   Watchdog registers		*/
+/****************************************/
+
+#define MV64360_WATCHDOG_CONFIG_REG				    0xb410
+#define MV64360_WATCHDOG_VALUE_REG				    0xb414
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define MV64360_I2C_SLAVE_ADDR					    0xc000
+#define MV64360_I2C_EXTENDED_SLAVE_ADDR				    0xc010
+#define MV64360_I2C_DATA					    0xc004
+#define MV64360_I2C_CONTROL					    0xc008
+#define MV64360_I2C_STATUS_BAUDE_RATE				    0xc00C
+#define MV64360_I2C_SOFT_RESET					    0xc01c
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_GPP_IO_CONTROL					    0xf100
+#define MV64360_GPP_LEVEL_CONTROL				    0xf110
+#define MV64360_GPP_VALUE					    0xf104
+#define MV64360_GPP_INTERRUPT_CAUSE				    0xf108
+#define MV64360_GPP_INTERRUPT_MASK0				    0xf10c
+#define MV64360_GPP_INTERRUPT_MASK1				    0xf114
+#define MV64360_GPP_VALUE_SET					    0xf118
+#define MV64360_GPP_VALUE_CLEAR					    0xf11c
+
+/****************************************/
+/* Interrupt Controller Registers	*/
+/****************************************/
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define MV64360_MAIN_INTERRUPT_CAUSE_LOW			    0x004
+#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
+#define MV64360_CPU_INTERRUPT0_MASK_LOW				    0x014
+#define MV64360_CPU_INTERRUPT0_MASK_HIGH			    0x01c
+#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
+#define MV64360_CPU_INTERRUPT1_MASK_LOW				    0x034
+#define MV64360_CPU_INTERRUPT1_MASK_HIGH			    0x03c
+#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
+#define MV64360_INTERRUPT0_MASK_0_LOW				    0x054
+#define MV64360_INTERRUPT0_MASK_0_HIGH				    0x05c
+#define MV64360_INTERRUPT0_SELECT_CAUSE				    0x064
+#define MV64360_INTERRUPT1_MASK_0_LOW				    0x074
+#define MV64360_INTERRUPT1_MASK_0_HIGH				    0x07c
+#define MV64360_INTERRUPT1_SELECT_CAUSE				    0x084
+
+/****************************************/
+/*	MPP Interface Registers		*/
+/****************************************/
+
+#define MV64360_MPP_CONTROL0					    0xf000
+#define MV64360_MPP_CONTROL1					    0xf004
+#define MV64360_MPP_CONTROL2					    0xf008
+#define MV64360_MPP_CONTROL3					    0xf00c
+
+/****************************************/
+/*    Serial Initialization registers	*/
+/****************************************/
+
+#define MV64360_SERIAL_INIT_LAST_DATA				    0xf324
+#define MV64360_SERIAL_INIT_CONTROL				    0xf328
+#define MV64360_SERIAL_INIT_STATUS				    0xf32c
+
+
+#endif /* __INCgt64360rh */
diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
new file mode 100755
index 0000000..3e44fb9
--- /dev/null
+++ b/board/esd/cpci750/pci.c
@@ -0,0 +1,961 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/* PCI.c - PCI functions */
+
+
+#include <common.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+
+#ifdef CONFIG_PCI_PNP
+void pciauto_config_init(struct pci_controller *hose);
+int  pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+#endif
+
+#include "../../Marvell/include/pci.h"
+
+#undef DEBUG
+#undef IDE_SET_NATIVE_MODE
+static unsigned int local_buses[] = { 0, 0 };
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+	{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+	{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
+};
+
+
+#ifdef DEBUG
+static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
+static void gt_pci_bus_mode_display (PCI_HOST host)
+{
+	unsigned int mode;
+
+
+	mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
+	switch (mode) {
+	case 0:
+		printf ("PCI %d bus mode: Conventional PCI\n", host);
+		break;
+	case 1:
+		printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+		break;
+	case 2:
+		printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+		break;
+	case 3:
+		printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+		break;
+	default:
+		printf ("Unknown BUS %d\n", mode);
+	}
+}
+#endif
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_address_space_en[] = {
+	PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before writing
+*                      to another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before reading
+*                     from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = 0;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*                               the agent is placed on another Bus. For more
+*                               information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*           GT spec (or any other PCI device spec).
+*           unsigned int pciDevNum - The device number needs to be addressed.
+*           unsigned int busNum - On which bus does the Target agent connect
+*                                 to.
+*           unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*                               the agent target locate on another PCI bus.
+*                             - Make sure the GT is configured as a master
+*                               before reading from another device on the PCI.
+*                             - The function takes care of Big/Little endian
+*                               conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec). (configuration register offset.)
+*           pciDevNum: The device number needs to be addressed.
+*           busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+/********************************************************************
+* pciGetBaseAddress - Gets the base address of a PCI.
+*           - If the PCI size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI base address.
+*********************************************************************/
+unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int regBase;
+	unsigned int regEnd;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &regBase);
+	GT_REG_READ (regOffset + 8, &regEnd);
+
+	if (regEnd <= regBase)
+		return 0xffffffff;	/* ERROR !!! */
+
+	regBase = regBase << 16;
+	return regBase;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 16) & 0xffff;
+		high = ((bankBase + bankLength) >> 16) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 16);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xffff) << 16;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	return ((high & 0xffff) + 1) << 16;
+}
+
+
+/* ronen - 7/Dec/03*/
+/********************************************************************
+* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
+* Inputs: one of the PCI BAR
+*********************************************************************/
+void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
+{
+	SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	/*ronen different function for 3rd bank. */
+	unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
+
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + offset,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+	gtPciEnableInternalBAR (host, bank);
+}
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*                         feature bits given as an input.
+*                       - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*         unsigned int features - See file: pci.h there are defintion for those
+*                                 region features.
+*         unsigned int baseAddress - The region base Address.
+*         unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*                           to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
+*
+* Inputs:   PCI_AGENT_PRIO internalAgent - priotity for internal agent.
+*           PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
+*           PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
+*           PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
+*           PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
+*           PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
+*           PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
+				  PCI_AGENT_PRIO externalAgent0,
+				  PCI_AGENT_PRIO externalAgent1,
+				  PCI_AGENT_PRIO externalAgent2,
+				  PCI_AGENT_PRIO externalAgent3,
+				  PCI_AGENT_PRIO externalAgent4,
+				  PCI_AGENT_PRIO externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 7) + (externalAgent0 << 8) +
+		(externalAgent1 << 9) + (externalAgent2 << 10) +
+		(externalAgent3 << 11) + (externalAgent4 << 12) +
+		(externalAgent5 << 13);
+	regData = (regData & 0xffffc07f) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*                      disable the park on last mechanism for each agent.
+*                      disabling this option for all agents results parking
+*                      on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
+*                       respond to grant assertion within a window specified in
+*                       the input value: 'brokenValue'.
+*
+* Inputs: unsigned char brokenValue -  A value which limits the Master to hold the
+*                       grant without asserting frame.
+* Returns:  Error for illegal broken value otherwise true.
+*********************************************************************/
+bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
+{
+	unsigned int data;
+	unsigned int regData;
+
+	if (brokenValue > 0xf)
+		return false;	/* brokenValue must be 4 bit */
+	data = brokenValue << 3;
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = (regData & 0xffffff87) | data;
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableBrokenAgentDetection - This function disable the Broken agent
+*                           Detection mechanism.
+*                           NOTE: This operation may cause a dead lock on the
+*                           pci0 arbitration.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciDisableBrokenAgentDetection (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	regData = regData & 0xfffffffd;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciP2PConfig - This function set the PCI_n P2P configurate.
+*                 For more information on the P2P read PCI spec.
+*
+* Inputs:  unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
+*                                      Boundry.
+*          unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
+*                                      Boundry.
+*          unsigned int busNum - The CPI bus number to which the PCI interface
+*                                      is connected.
+*          unsigned int devNum - The PCI interface's device number.
+*
+* Returns:  true.
+*********************************************************************/
+bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
+		   unsigned int SecondBusHigh,
+		   unsigned int busNum, unsigned int devNum)
+{
+	unsigned int regData;
+
+	regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
+		((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
+	GT_REG_WRITE (pci_p2p_configuration[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*                          supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*         snoopType - There is four optional Types:
+*                        1. No Snoop.
+*                        2. Snoop to WT region.
+*                        3. Snoop to WB region.
+*                        4. Snoop & Invalidate to WB region.
+*         baseAddress - Base Address of this region.
+*         regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), bus,
+					     value);
+	}
+	return 0;
+}
+
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		/*ronen different function for 3rd bank. */
+		unsigned int offset =
+			(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+					0x0);
+		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
+				       &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					bar_value);
+	}
+}
+
+
+/* TODO BJW: Change this for DB64360. This was pulled from the EV64260  */
+/* and is curently not called *. */
+#if 0
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+	{}
+};
+
+struct pci_controller pci0_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+/*    fixup_irq: gt_fixup_irq, */
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+#ifdef CONFIG_PCI_PNP
+	unsigned int bar;
+#endif
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST0);
+#endif
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CFG_PCI0_IO_SPACE_PCI,
+			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+	pciArbiterEnable (PCI_HOST0);
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+	pciauto_config_init(&pci0_hose);
+	pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
+#endif
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
+
+#ifdef DEBUG
+	gt_pci_bus_mode_display (PCI_HOST1);
+#endif
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci1_hose.first_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CFG_PCI1_IO_SPACE_PCI,
+			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+#ifdef CONFIG_PCI_PNP
+	pciauto_config_init(&pci1_hose);
+	pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
+#endif
+	pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+}
+#endif /* of CONFIG_PCI */
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
new file mode 100755
index 0000000..db545ef
--- /dev/null
+++ b/board/esd/cpci750/sdram_init.c
@@ -0,0 +1,1683 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * adaption for the Marvell DB64360 Board
+ * Ingo Assmus (ingo.assmus@keymile.com)
+ *
+ * adaption for the cpci750 Board
+ * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
+ *************************************************************************/
+
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include "../../Marvell/include/memory.h"
+#include "../../Marvell/include/pci.h"
+#include "../../Marvell/include/mv_gen_reg.h"
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "../../Marvell/common/i2c.h"
+#include "64360.h"
+#include "mv_regs.h"
+
+
+#undef	DEBUG
+/* #define DEBUG */
+#ifdef CONFIG_PCI
+#define	MAP_PCI
+#endif /* of CONFIG_PCI */
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+int set_dfcdlInit(void);	/* setup delay line of Mv64360 */
+
+/* ------------------------------------------------------------------------- */
+
+int
+memory_map_bank(unsigned int bankNo,
+		unsigned int bankBase,
+		unsigned int bankLength)
+{
+#ifdef MAP_PCI
+	PCI_HOST host;
+#endif
+
+
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf("mapping bank %d at %08x - %08x\n",
+		       bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank(bankNo, bankBase, bankLength);
+
+#ifdef MAP_PCI
+	for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
+		const int features=
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 |
+			PCI_NO_SWAP;
+
+		pciMapMemoryBank(host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
+				bankLength);
+
+		pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
+	}
+#endif
+	return 0;
+}
+
+#define GB         (1 << 30)
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+	uchar drb_size;
+	uchar registered, ecc;
+	uchar tpar;
+	uchar tras_clocks;
+	uchar burst_len;
+	uchar banks, slot;
+} sdram_info_t;
+
+/* Typedefs for 'gtAuxilGetDIMMinfo' function */
+
+typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
+
+typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
+				SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
+			       } VOLTAGE_INTERFACE;
+
+typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
+typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
+
+
+/* SDRAM/DDR information struct */
+typedef struct _gtMemoryDimmInfo
+{
+    MEMORY_TYPE          memoryType;
+    unsigned int         numOfRowAddresses;
+    unsigned int         numOfColAddresses;
+    unsigned int         numOfModuleBanks;
+    unsigned int         dataWidth;
+    VOLTAGE_INTERFACE    voltageInterface;
+    unsigned int         errorCheckType;                                /* ECC , PARITY..*/
+    unsigned int         sdramWidth;                                    /* 4,8,16 or 32 */;
+    unsigned int         errorCheckDataWidth;                           /* 0 - no, 1 - Yes */
+    unsigned int         minClkDelay;
+    unsigned int         burstLengthSupported;
+    unsigned int         numOfBanksOnEachDevice;
+    unsigned int         suportedCasLatencies;
+    unsigned int     	 RefreshInterval;
+    unsigned int   	 maxCASlatencySupported_LoP;			/* LoP left of point (measured in ns) */
+    unsigned int   	 maxCASlatencySupported_RoP;			/* RoP right of point (measured in ns)*/
+    MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
+    MAX_CL_SUPPORTED_SD  maxClSupported_SD;
+    unsigned int         moduleBankDensity;
+    /* module attributes (true for yes) */
+    bool                 bufferedAddrAndControlInputs;
+    bool                 registeredAddrAndControlInputs;
+    bool                 onCardPLL;
+    bool                 bufferedDQMBinputs;
+    bool                 registeredDQMBinputs;
+    bool	         differentialClockInput;
+    bool                 redundantRowAddressing;
+
+    /* module general attributes */
+    bool                 suportedAutoPreCharge;
+    bool                 suportedPreChargeAll;
+    bool                 suportedEarlyRasPreCharge;
+    bool                 suportedWrite1ReadBurst;
+    bool                 suported5PercentLowVCC;
+    bool                 suported5PercentUpperVCC;
+    /* module timing parameters */
+    unsigned int         minRasToCasDelay;
+    unsigned int         minRowActiveRowActiveDelay;
+    unsigned int         minRasPulseWidth;
+    unsigned int         minRowPrechargeTime;   			/* measured in ns */
+
+    int   	         addrAndCommandHoldTime;			/* LoP left of point (measured in ns) */
+    int   	         addrAndCommandSetupTime;				/* (measured in ns/100) */
+    int   	         dataInputSetupTime;				/* LoP left of point (measured in ns) */
+    int   	         dataInputHoldTime;				/* LoP left of point (measured in ns) */
+/* tAC times for highest 2nd and 3rd highest CAS Latency values */
+    unsigned int   	 clockToDataOut_LoP;				/* LoP left of point (measured in ns) */
+    unsigned int   	 clockToDataOut_RoP;				/* RoP right of point (measured in ns)*/
+    unsigned int   	 clockToDataOutMinus1_LoP;				/* LoP left of point (measured in ns) */
+    unsigned int   	 clockToDataOutMinus1_RoP;			/* RoP right of point (measured in ns)*/
+    unsigned int   	 clockToDataOutMinus2_LoP;				/* LoP left of point (measured in ns) */
+    unsigned int   	 clockToDataOutMinus2_RoP;			/* RoP right of point (measured in ns)*/
+
+    unsigned int   	 minimumCycleTimeAtMaxCasLatancy_LoP;		/* LoP left of point (measured in ns) */
+    unsigned int   	 minimumCycleTimeAtMaxCasLatancy_RoP;		/* RoP right of point (measured in ns)*/
+
+    unsigned int   	 minimumCycleTimeAtMaxCasLatancyMinus1_LoP;	/* LoP left of point (measured in ns) */
+    unsigned int   	 minimumCycleTimeAtMaxCasLatancyMinus1_RoP;	/* RoP right of point (measured in ns)*/
+
+    unsigned int   	 minimumCycleTimeAtMaxCasLatancyMinus2_LoP;	/* LoP left of point (measured in ns) */
+    unsigned int   	 minimumCycleTimeAtMaxCasLatancyMinus2_RoP;	/* RoP right of point (measured in ns)*/
+
+    /* Parameters calculated from
+       the extracted DIMM information */
+    unsigned int         size;
+    unsigned int         deviceDensity;           		       	/* 16,64,128,256 or 512 Mbit */
+    unsigned int         numberOfDevices;
+    uchar 		 drb_size;				       	/* DRAM size in n*64Mbit */
+    uchar 		 slot;						/* Slot Number this module is inserted in */
+    uchar 		 spd_raw_data[128];			       	/* Content of SPD-EEPROM copied 1:1 */
+#ifdef DEBUG
+    uchar 		 manufactura[8];				/* Content of SPD-EEPROM Byte 64-71 */
+    uchar 		 modul_id[18];					/* Content of SPD-EEPROM Byte 73-90 */
+    uchar 		 vendor_data[27];			       	/* Content of SPD-EEPROM Byte 99-125 */
+    unsigned long	 modul_serial_no;			       	/* Content of SPD-EEPROM Byte 95-98 */
+    unsigned int         manufac_date;					/* Content of SPD-EEPROM Byte 93-94 */
+    unsigned int         modul_revision;				/* Content of SPD-EEPROM Byte 91-92 */
+    uchar 		 manufac_place;					/* Content of SPD-EEPROM Byte 72 */
+
+#endif
+} AUX_MEM_DIMM_INFO;
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short
+NS10to10PS(unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return(ns*100 + ns10*10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short
+NSto10PS(unsigned char spd_byte)
+{
+	return(spd_byte*100);
+}
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
+static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned long spd_checksum;
+
+	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+	int ret;
+	unsigned int i, j, density = 1, devicesForErrCheck = 0;
+
+#ifdef DEBUG
+	unsigned int k;
+#endif
+	unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
+	int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
+	uchar supp_cal, cal_val;
+	ulong memclk, tmemclk;
+	ulong tmp;
+	uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks;
+	uchar data[128];
+
+	memclk = gd->bus_clk;
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+	memset (data, 0, sizeof (data));
+
+
+	ret = 0;
+
+	DP (puts ("before i2c read\n"));
+
+	ret = i2c_read (addr, 0, 2, data, 128);
+
+	DP (puts ("after i2c read\n"));
+
+	if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
+	    || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
+	    || (data[70] != 'b') || (data[71] != 'h')) {
+		ret = -1;
+	}
+
+	if ((ret != 0) && (slot == 0)) {
+		memset (data, 0, sizeof (data));
+		data[0] = 0x80;
+		data[1] = 0x08;
+		data[2] = 0x07;
+		data[3] = 0x0c;
+		data[4] = 0x09;
+		data[5] = 0x01;
+		data[6] = 0x48;
+		data[7] = 0x00;
+		data[8] = 0x04;
+		data[9] = 0x75;
+		data[10] = 0x80;
+		data[11] = 0x02;
+		data[12] = 0x80;
+		data[13] = 0x10;
+		data[14] = 0x08;
+		data[15] = 0x01;
+		data[16] = 0x0e;
+		data[17] = 0x04;
+		data[18] = 0x0c;
+		data[19] = 0x01;
+		data[20] = 0x02;
+		data[21] = 0x20;
+		data[22] = 0x00;
+		data[23] = 0xa0;
+		data[24] = 0x80;
+		data[25] = 0x00;
+		data[26] = 0x00;
+		data[27] = 0x50;
+		data[28] = 0x3c;
+		data[29] = 0x50;
+		data[30] = 0x32;
+		data[31] = 0x10;
+		data[32] = 0xb0;
+		data[33] = 0xb0;
+		data[34] = 0x60;
+		data[35] = 0x60;
+		data[64] = 'e';
+		data[65] = 's';
+		data[66] = 'd';
+		data[67] = '-';
+		data[68] = 'g';
+		data[69] = 'm';
+		data[70] = 'b';
+		data[71] = 'h';
+		ret = 0;
+	}
+
+	/* zero all the values */
+	memset (dimmInfo, 0, sizeof (*dimmInfo));
+
+	/* copy the SPD content 1:1 into the dimmInfo structure */
+	for (i = 0; i <= 127; i++) {
+		dimmInfo->spd_raw_data[i] = data[i];
+	}
+
+	if (ret) {
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+		return 0;
+	} else
+		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
+
+#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+
+	for (i = 0; i <= 127; i++) {
+		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
+			data[i]);
+	}
+
+#endif
+#ifdef DEBUG
+	/* find Manufacturer of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
+		dimmInfo->manufactura[i] = data[64 + i];
+	}
+	printf ("\nThis RAM-Module is produced by: 		%s\n",
+		dimmInfo->manufactura);
+
+	/* find Manul-ID of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
+		dimmInfo->modul_id[i] = data[73 + i];
+	}
+	printf ("The Module-ID of this RAM-Module is: 		%s\n",
+		dimmInfo->modul_id);
+
+	/* find Vendor-Data of Dimm Module */
+	for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
+		dimmInfo->vendor_data[i] = data[99 + i];
+	}
+	printf ("Vendor Data of this RAM-Module is: 		%s\n",
+		dimmInfo->vendor_data);
+
+	/* find modul_serial_no of Dimm Module */
+	dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
+	printf ("Serial No. of this RAM-Module is: 		%ld (%lx)\n",
+		dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
+
+	/* find Manufac-Data of Dimm Module */
+	dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
+	printf ("Manufactoring Date of this RAM-Module is: 	%d.%d\n", data[93], data[94]);	/*dimmInfo->manufac_date */
+
+	/* find modul_revision of Dimm Module */
+	dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
+	printf ("Module Revision of this RAM-Module is: 		%d.%d\n", data[91], data[92]);	/* dimmInfo->modul_revision */
+
+	/* find manufac_place of Dimm Module */
+	dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
+	printf ("manufac_place of this RAM-Module is: 		%d\n",
+		dimmInfo->manufac_place);
+
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------*/
+/* calculate SPD checksum */
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	spd_checksum = 0;
+#if 0				/* test-only */
+	for (i = 0; i <= 62; i++) {
+		spd_checksum += data[i];
+	}
+
+	if ((spd_checksum & 0xff) != data[63]) {
+		printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
+		hang ();
+	}
+
+	else
+		printf ("SPD Checksum ok!\n");
+#endif /* test-only */
+
+/*------------------------------------------------------------------------------------------------------------------------------*/
+	for (i = 2; i <= 35; i++) {
+		switch (i) {
+		case 2:	/* Memory type (DDR / SDRAM) */
+			dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
+#ifdef DEBUG
+			if (dimmInfo->memoryType == 0)
+				DP (printf
+				    ("Dram_type in slot %d is: 			SDRAM\n",
+				     dimmInfo->slot));
+			if (dimmInfo->memoryType == 1)
+				DP (printf
+				    ("Dram_type in slot %d is: 			DDRAM\n",
+				     dimmInfo->slot));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 3:	/* Number Of Row Addresses */
+			dimmInfo->numOfRowAddresses = data[i];
+			DP (printf
+			    ("Module Number of row addresses: 		%d\n",
+			     dimmInfo->numOfRowAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 4:	/* Number Of Column Addresses */
+			dimmInfo->numOfColAddresses = data[i];
+			DP (printf
+			    ("Module Number of col addresses: 		%d\n",
+			     dimmInfo->numOfColAddresses));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 5:	/* Number Of Module Banks */
+			dimmInfo->numOfModuleBanks = data[i];
+			DP (printf
+			    ("Number of Banks on Mod. : 				%d\n",
+			     dimmInfo->numOfModuleBanks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 6:	/* Data Width */
+			dimmInfo->dataWidth = data[i];
+			DP (printf
+			    ("Module Data Width: 				%d\n",
+			     dimmInfo->dataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 8:	/* Voltage Interface */
+			switch (data[i]) {
+			case 0x0:
+				dimmInfo->voltageInterface = TTL_5V_TOLERANT;
+				DP (printf
+				    ("Module is 					TTL_5V_TOLERANT\n"));
+				break;
+			case 0x1:
+				dimmInfo->voltageInterface = LVTTL;
+				DP (printf
+				    ("Module is 					LVTTL\n"));
+				break;
+			case 0x2:
+				dimmInfo->voltageInterface = HSTL_1_5V;
+				DP (printf
+				    ("Module is 					TTL_5V_TOLERANT\n"));
+				break;
+			case 0x3:
+				dimmInfo->voltageInterface = SSTL_3_3V;
+				DP (printf
+				    ("Module is 					HSTL_1_5V\n"));
+				break;
+			case 0x4:
+				dimmInfo->voltageInterface = SSTL_2_5V;
+				DP (printf
+				    ("Module is 					SSTL_2_5V\n"));
+				break;
+			default:
+				dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
+				DP (printf
+				    ("Module is 					VOLTAGE_UNKNOWN\n"));
+				break;
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 9:	/* Minimum Cycle Time At Max CasLatancy */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At Max CasLatancy: 		%d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 10:	/* Clock To Data Out */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOut_LoP = leftOfPoint;
+			dimmInfo->clockToDataOut_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out: 				%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			/*dimmInfo->clockToDataOut */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+#ifdef CONFIG_ECC
+		case 11:	/* Error Check Type */
+			dimmInfo->errorCheckType = data[i];
+			DP (printf
+			    ("Error Check Type (0=NONE): 			%d\n",
+			     dimmInfo->errorCheckType));
+			break;
+#endif
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 12:	/* Refresh Interval */
+			dimmInfo->RefreshInterval = data[i];
+			DP (printf
+			    ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
+			     dimmInfo->RefreshInterval));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 13:	/* Sdram Width */
+			dimmInfo->sdramWidth = data[i];
+			DP (printf
+			    ("Sdram Width: 					%d\n",
+			     dimmInfo->sdramWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 14:	/* Error Check Data Width */
+			dimmInfo->errorCheckDataWidth = data[i];
+			DP (printf
+			    ("Error Check Data Width: 			%d\n",
+			     dimmInfo->errorCheckDataWidth));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 15:	/* Minimum Clock Delay */
+			dimmInfo->minClkDelay = data[i];
+			DP (printf
+			    ("Minimum Clock Delay: 				%d\n",
+			     dimmInfo->minClkDelay));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 16:	/* Burst Length Supported */
+			   /******-******-******-*******
+			   * bit3 | bit2 | bit1 | bit0 *
+			   *******-******-******-*******
+	    burst length = *  8   |  4   |   2  |   1  *
+			   *****************************
+
+	    If for example bit0 and bit2 are set, the burst
+	    length supported are 1 and 4. */
+
+			dimmInfo->burstLengthSupported = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Burst Length Supported: 			"));
+			if (dimmInfo->burstLengthSupported & 0x01)
+				DP (printf ("1, "));
+			if (dimmInfo->burstLengthSupported & 0x02)
+				DP (printf ("2, "));
+			if (dimmInfo->burstLengthSupported & 0x04)
+				DP (printf ("4, "));
+			if (dimmInfo->burstLengthSupported & 0x08)
+				DP (printf ("8, "));
+			DP (printf (" Bit \n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 17:	/* Number Of Banks On Each Device */
+			dimmInfo->numOfBanksOnEachDevice = data[i];
+			DP (printf
+			    ("Number Of Banks On Each Chip: 			%d\n",
+			     dimmInfo->numOfBanksOnEachDevice));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 18:	/* Suported Cas Latencies */
+
+			/*     DDR:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
+			 *********************************************************
+			 SDRAM:
+			 *******-******-******-******-******-******-******-*******
+			 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
+			 *******-******-******-******-******-******-******-*******
+			 CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
+			 ********************************************************/
+			dimmInfo->suportedCasLatencies = data[i];
+#ifdef DEBUG
+			DP (printf
+			    ("Suported Cas Latencies: (CL) 			"));
+			if (dimmInfo->memoryType == 0) {	/* SDRAM */
+				for (k = 0; k <= 7; k++) {
+					if (dimmInfo->
+					    suportedCasLatencies & (1 << k))
+						DP (printf
+						    ("%d, 			",
+						     k + 1));
+				}
+
+			} else {	/* DDR-RAM */
+
+				if (dimmInfo->suportedCasLatencies & 1)
+					DP (printf ("1, "));
+				if (dimmInfo->suportedCasLatencies & 2)
+					DP (printf ("1.5, "));
+				if (dimmInfo->suportedCasLatencies & 4)
+					DP (printf ("2, "));
+				if (dimmInfo->suportedCasLatencies & 8)
+					DP (printf ("2.5, "));
+				if (dimmInfo->suportedCasLatencies & 16)
+					DP (printf ("3, "));
+				if (dimmInfo->suportedCasLatencies & 32)
+					DP (printf ("3.5, "));
+
+			}
+			DP (printf ("\n"));
+#endif
+			/* Calculating MAX CAS latency */
+			for (j = 7; j > 0; j--) {
+				if (((dimmInfo->
+				      suportedCasLatencies >> j) & 0x1) ==
+				    1) {
+					switch (dimmInfo->memoryType) {
+					case DDR:
+						/* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
+						switch (j) {
+						case 7:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 6:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			ERROR !!!\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								=
+								DDR_CL_FAULT;
+							hang ();
+							break;
+						case 5:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			3.5 clk's\n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3_5;
+							break;
+						case 4:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			3 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_3;
+							break;
+						case 3:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			2.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2_5;
+							break;
+						case 2:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			2 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_2;
+							break;
+						case 1:
+							DP (printf
+							    ("Max. Cas Latencies (DDR): 			1.5 clk's \n"));
+							dimmInfo->
+								maxClSupported_DDR
+								= DDR_CL_1_5;
+							break;
+						}
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							=
+							1 +
+							(int) (5 * j / 10);
+						if (((5 * j) % 10) != 0)
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 5;
+						else
+							dimmInfo->
+								maxCASlatencySupported_RoP
+								= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation): 	%d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					case SDRAM:
+						/* CAS latency 1, 2, 3, 4, 5, 6, 7 */
+						dimmInfo->maxClSupported_SD = j;	/*  Cas Latency DDR-RAM Coded                   */
+						DP (printf
+						    ("Max. Cas Latencies (SD): %d\n",
+						     dimmInfo->
+						     maxClSupported_SD));
+						dimmInfo->
+							maxCASlatencySupported_LoP
+							= j;
+						dimmInfo->
+							maxCASlatencySupported_RoP
+							= 0;
+						DP (printf
+						    ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
+						     dimmInfo->
+						     maxCASlatencySupported_LoP,
+						     dimmInfo->
+						     maxCASlatencySupported_RoP));
+						break;
+					}
+					break;
+				}
+			}
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 21:	/* Buffered Address And Control Inputs */
+			DP (printf ("\nModul Attributes (SPD Byte 21): \n"));
+			dimmInfo->bufferedAddrAndControlInputs =
+				data[i] & BIT0;
+			dimmInfo->registeredAddrAndControlInputs =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
+			dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
+			dimmInfo->registeredDQMBinputs =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->differentialClockInput =
+				(data[i] & BIT5) >> 5;
+			dimmInfo->redundantRowAddressing =
+				(data[i] & BIT6) >> 6;
+#ifdef DEBUG
+			if (dimmInfo->bufferedAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Buffered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Buffered Address/Control Input:		No \n"));
+
+			if (dimmInfo->registeredAddrAndControlInputs == 1)
+				DP (printf
+				    (" - Registered Address/Control Input:		Yes \n"));
+			else
+				DP (printf
+				    (" - Registered Address/Control Input:		No \n"));
+
+			if (dimmInfo->onCardPLL == 1)
+				DP (printf
+				    (" - On-Card PLL (clock):				Yes \n"));
+			else
+				DP (printf
+				    (" - On-Card PLL (clock):				No \n"));
+
+			if (dimmInfo->bufferedDQMBinputs == 1)
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				Yes \n"));
+			else
+				DP (printf
+				    (" - Bufferd DQMB Inputs:				No \n"));
+
+			if (dimmInfo->registeredDQMBinputs == 1)
+				DP (printf
+				    (" - Registered DQMB Inputs:			Yes \n"));
+			else
+				DP (printf
+				    (" - Registered DQMB Inputs:			No \n"));
+
+			if (dimmInfo->differentialClockInput == 1)
+				DP (printf
+				    (" - Differential Clock Input:			Yes \n"));
+			else
+				DP (printf
+				    (" - Differential Clock Input:			No \n"));
+
+			if (dimmInfo->redundantRowAddressing == 1)
+				DP (printf
+				    (" - redundant Row Addressing:			Yes \n"));
+			else
+				DP (printf
+				    (" - redundant Row Addressing:			No \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 22:	/* Suported AutoPreCharge */
+			DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
+			dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
+			dimmInfo->suportedAutoPreCharge =
+				(data[i] & BIT1) >> 1;
+			dimmInfo->suportedPreChargeAll =
+				(data[i] & BIT2) >> 2;
+			dimmInfo->suportedWrite1ReadBurst =
+				(data[i] & BIT3) >> 3;
+			dimmInfo->suported5PercentLowVCC =
+				(data[i] & BIT4) >> 4;
+			dimmInfo->suported5PercentUpperVCC =
+				(data[i] & BIT5) >> 5;
+#ifdef DEBUG
+			if (dimmInfo->suportedEarlyRasPreCharge == 1)
+				DP (printf
+				    (" - Early Ras Precharge:			Yes \n"));
+			else
+				DP (printf
+				    (" -  Early Ras Precharge:			No \n"));
+
+			if (dimmInfo->suportedAutoPreCharge == 1)
+				DP (printf
+				    (" - AutoPreCharge:				Yes \n"));
+			else
+				DP (printf
+				    (" -  AutoPreCharge:				No \n"));
+
+			if (dimmInfo->suportedPreChargeAll == 1)
+				DP (printf
+				    (" - Precharge All:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Precharge All:				No \n"));
+
+			if (dimmInfo->suportedWrite1ReadBurst == 1)
+				DP (printf
+				    (" - Write 1/ReadBurst:				Yes \n"));
+			else
+				DP (printf
+				    (" -  Write 1/ReadBurst:				No \n"));
+
+			if (dimmInfo->suported5PercentLowVCC == 1)
+				DP (printf
+				    (" - lower VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    ("  - lower VCC tolerance:			10 Percent \n"));
+
+			if (dimmInfo->suported5PercentUpperVCC == 1)
+				DP (printf
+				    (" - upper VCC tolerance:			5 Percent \n"));
+			else
+				DP (printf
+				    (" -  upper VCC tolerance:			10 Percent \n"));
+
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 23:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 24:	/* Clock To Data Out 2nd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (2nd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 25:	/* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
+			shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
+			mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
+			leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
+			rightOfPoint = (data[i] & maskRightOfPoint) * mult;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
+				leftOfPoint;
+			dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
+				rightOfPoint;
+			DP (printf
+			    ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 26:	/* Clock To Data Out 3rd highest Cas Latency Value */
+			div = (dimmInfo->memoryType == DDR) ? 100 : 10;
+			time_tmp =
+				(((data[i] & 0xf0) >> 4) * 10) +
+				((data[i] & 0x0f));
+			leftOfPoint = time_tmp / div;
+			rightOfPoint = time_tmp % div;
+			dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
+			dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
+			DP (printf
+			    ("Clock To Data Out (3rd CL value): 		%d.%2d [ns]\n",
+			     leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 27:	/* Minimum Row Precharge Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);	/* measured in n times 10ps Intervals */
+			trp_clocks =
+				(dimmInfo->minRowPrechargeTime +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
+			     tmemclk, tmemclk / 100, tmemclk % 100));
+			DP (printf
+			    ("Minimum Row Precharge Time [ns]: 		%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 28:	/* Minimum Row Active to Row Active Time */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trrd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Row Active -To- Row Active Delay [ns]: 	%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 29:	/* Minimum Ras-To-Cas Delay */
+			shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
+			maskLeftOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
+			maskRightOfPoint =
+				(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
+			leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
+			rightOfPoint = (data[i] & maskRightOfPoint) * 25;
+
+			dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);	/* measured in 100ns Intervals */
+			trcd_clocks =
+				(dimmInfo->minRowActiveRowActiveDelay +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras-To-Cas Delay [ns]: 			%d.%2d = in Clk cycles %d\n",
+			     leftOfPoint, rightOfPoint, trp_clocks));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 30:	/* Minimum Ras Pulse Width */
+			dimmInfo->minRasPulseWidth = data[i];
+			tras_clocks =
+				(NSto10PS (data[i]) +
+				 (tmemclk - 1)) / tmemclk;
+			DP (printf
+			    ("Minimum Ras Pulse Width [ns]: 			%d = in Clk cycles %d\n",
+			     dimmInfo->minRasPulseWidth, tras_clocks));
+
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 31:	/* Module Bank Density */
+			dimmInfo->moduleBankDensity = data[i];
+			DP (printf
+			    ("Module Bank Density: 				%d\n",
+			     dimmInfo->moduleBankDensity));
+#ifdef DEBUG
+			DP (printf
+			    ("*** Offered Densities (more than 1 = Multisize-Module): "));
+			{
+				if (dimmInfo->moduleBankDensity & 1)
+					DP (printf ("4MB, "));
+				if (dimmInfo->moduleBankDensity & 2)
+					DP (printf ("8MB, "));
+				if (dimmInfo->moduleBankDensity & 4)
+					DP (printf ("16MB, "));
+				if (dimmInfo->moduleBankDensity & 8)
+					DP (printf ("32MB, "));
+				if (dimmInfo->moduleBankDensity & 16)
+					DP (printf ("64MB, "));
+				if (dimmInfo->moduleBankDensity & 32)
+					DP (printf ("128MB, "));
+				if ((dimmInfo->moduleBankDensity & 64)
+				    || (dimmInfo->moduleBankDensity & 128)) {
+					DP (printf ("ERROR, "));
+					hang ();
+				}
+			}
+			DP (printf ("\n"));
+#endif
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 32:	/* Address And Command Setup Time (measured in ns/1000) */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Setup Time [ns]: 		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 33:	/* Address And Command Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->addrAndCommandHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Address And Command Hold Time [ns]: 		%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 34:	/* Data Input Setup Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputSetupTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Setup Time [ns]: 			%d.%d\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+
+		case 35:	/* Data Input Hold Time */
+			sign = 1;
+			switch (dimmInfo->memoryType) {
+			case DDR:
+				time_tmp =
+					(((data[i] & 0xf0) >> 4) * 10) +
+					((data[i] & 0x0f));
+				leftOfPoint = time_tmp / 100;
+				rightOfPoint = time_tmp % 100;
+				break;
+			case SDRAM:
+				leftOfPoint = (data[i] & 0xf0) >> 4;
+				if (leftOfPoint > 7) {
+					leftOfPoint = data[i] & 0x70 >> 4;
+					sign = -1;
+				}
+				rightOfPoint = (data[i] & 0x0f);
+				break;
+			}
+			dimmInfo->dataInputHoldTime =
+				(leftOfPoint * 100 + rightOfPoint) * sign;
+			DP (printf
+			    ("Data Input Hold Time [ns]: 			%d.%d\n\n",
+			     sign * leftOfPoint, rightOfPoint));
+			break;
+/*------------------------------------------------------------------------------------------------------------------------------*/
+		}
+	}
+	/* calculating the sdram density */
+	for (i = 0;
+	     i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
+	     i++) {
+		density = density * 2;
+	}
+	dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
+		dimmInfo->sdramWidth;
+	dimmInfo->numberOfDevices =
+		(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
+		dimmInfo->numOfModuleBanks;
+	devicesForErrCheck =
+		(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
+	if ((dimmInfo->errorCheckType == 0x1)
+	    || (dimmInfo->errorCheckType == 0x2)
+	    || (dimmInfo->errorCheckType == 0x3)) {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			(dimmInfo->numberOfDevices - devicesForErrCheck);
+	} else {
+		dimmInfo->size =
+			(dimmInfo->deviceDensity / 8) *
+			dimmInfo->numberOfDevices;
+	}
+
+	/* compute the module DRB size */
+	tmp = (1 <<
+	       (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
+	tmp *= dimmInfo->numOfModuleBanks;
+	tmp *= dimmInfo->sdramWidth;
+	tmp = tmp >> 24;	/* div by 0x4000000 (64M)       */
+	dimmInfo->drb_size = (uchar) tmp;
+	DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
+
+	/* try a CAS latency of 3 first... */
+
+	/* bit 1 is CL2, bit 2 is CL3 */
+	supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
+
+	cal_val = 0;
+	if (supp_cal & 8) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 6;
+	}
+	if (supp_cal & 4) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 5;
+	}
+
+	/* then 2... */
+	if (supp_cal & 2) {
+		if (NS10to10PS (data[23]) <= tmemclk)
+			cal_val = 4;
+	}
+
+	DP (printf ("cal_val = %d\n", cal_val * 5));
+
+	/* bummer, did't work... */
+	if (cal_val == 0) {
+		DP (printf ("Couldn't find a good CAS latency\n"));
+		hang ();
+		return 0;
+	}
+
+	return true;
+}
+
+/* sets up the GT properly with information passed in */
+int setup_sdram (AUX_MEM_DIMM_INFO * info)
+{
+	ulong tmp, check;
+	ulong tmp_sdram_mode = 0;	/* 0x141c */
+	ulong tmp_dunit_control_low = 0;	/* 0x1404 */
+	int i;
+
+	/* sanity checking */
+	if (!info->numOfModuleBanks) {
+		printf ("setup_sdram called with 0 banks\n");
+		return 1;
+	}
+
+	/* delay line */
+
+	/* Program the GT with the discovered data */
+	if (info->registeredAddrAndControlInputs == true)
+		DP (printf
+		    ("Module is registered, but we do not support registered Modules !!!\n"));
+
+
+	/* delay line */
+	set_dfcdlInit ();	/* may be its not needed */
+	DP (printf ("Delay line set done\n"));
+
+	/* set SDRAM mode NOP */ /* To_do check it */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x5);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"));
+	}
+
+	/* SDRAM configuration */
+	GT_REG_WRITE (SDRAM_CONFIG, 0x58200400);
+	DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM open pages controll keep open as much as I can */
+	GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
+	DP (printf
+	    ("sdram_open_pages_controll 0x1414: %08x\n",
+	     GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)));
+
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp == 0)
+		DP (printf ("Core Signals are sync (by HW-Setting)!!!\n"));
+	else
+		DP (printf
+		    ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"));
+
+	/* SDRAM set CAS Lentency according to SPD information */
+	switch (info->memoryType) {
+	case SDRAM:
+		DP (printf ("### SD-RAM not supported yet !!!\n"));
+		hang ();
+		/* ToDo fill SD-RAM if needed !!!!! */
+		break;
+
+	case DDR:
+		DP (printf ("### SET-CL for DDR-RAM\n"));
+
+		switch (info->maxClSupported_DDR) {
+		case DDR_CL_3:
+			tmp_dunit_control_low = 0x3c000000;	/* Read-Data sampled on falling edge of Clk */
+			tmp_sdram_mode = 0x32;	/* CL=3 Burstlength = 4 */
+			DP (printf
+			    ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+			     tmp_sdram_mode, tmp_dunit_control_low));
+			break;
+
+		case DDR_CL_2_5:
+			if (tmp == 1) {	/* clocks sync */
+				tmp_dunit_control_low = 0x24000000;	/* Read-Data sampled on falling edge of Clk */
+				tmp_sdram_mode = 0x62;	/* CL=2,5 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* clk sync. bypassed     */
+
+				tmp_dunit_control_low = 0x03000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x62;	/* CL=2,5 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		case DDR_CL_2:
+			if (tmp == 1) {	/* Sync */
+				tmp_dunit_control_low = 0x03000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* Not sync.      */
+
+				tmp_dunit_control_low = 0x3b000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x22;	/* CL=2 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		case DDR_CL_1_5:
+			if (tmp == 1) {	/* Sync */
+				tmp_dunit_control_low = 0x23000000;	/* Read-Data sampled on falling edge of Clk */
+				tmp_sdram_mode = 0x52;	/* CL=1,5 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			} else {	/* not sync */
+
+				tmp_dunit_control_low = 0x1a000000;	/* Read-Data sampled on rising edge of Clk */
+				tmp_sdram_mode = 0x52;	/* CL=1,5 Burstlength = 4 */
+				DP (printf
+				    ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
+				     tmp_sdram_mode, tmp_dunit_control_low));
+			}
+			break;
+
+		default:
+			printf ("Max. CL is out of range %d\n",
+				info->maxClSupported_DDR);
+			hang ();
+			break;
+		}
+		break;
+	}
+
+	/* Write results of CL detection procedure */
+	GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
+	}
+
+
+	/* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
+	tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);	/* Clock Domain Sync from power on reset */
+	if (tmp != 1) {		/*clocks are not sync */
+		/* asyncmode */
+		GT_REG_WRITE (D_UNIT_CONTROL_LOW,
+			      (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
+			      0x18110780 | tmp_dunit_control_low);
+	} else {
+		/* syncmode */
+		GT_REG_WRITE (D_UNIT_CONTROL_LOW,
+			      (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
+			      0x00110000 | tmp_dunit_control_low);
+	}
+
+	/* set SDRAM mode SetCommand 0x1418 */
+	GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+	while (GTREGREAD (SDRAM_OPERATION) != 0) {
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"));
+	}
+
+/*------------------------------------------------------------------------------ */
+
+
+	/* bank parameters */
+	/* SDRAM address decode register */
+	/* program this with the default value */
+	tmp = 0x02;
+
+
+	DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size));
+	switch (info->drb_size) {
+	case 1:		/* 64 Mbit */
+	case 2:		/* 128 Mbit */
+		DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n"));
+		tmp |= (0x00 << 4);
+		break;
+	case 4:		/* 256 Mbit */
+	case 8:		/* 512 Mbit */
+		DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n"));
+		tmp |= (0x01 << 4);
+		break;
+	case 16:		/* 1 Gbit */
+	case 32:		/* 2 Gbit */
+		DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n"));
+		tmp |= (0x02 << 4);
+		break;
+	default:
+		printf ("Error in dram size calculation\n");
+		DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"));
+		tmp |= (0x02 << 4);
+		return 1;
+	}
+
+	/* SDRAM bank parameters */
+	/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
+	DP (printf
+	    ("setting up slot %d config with: %08lx \n", info->slot, tmp));
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
+
+/* ------------------------------------------------------------------------------ */
+
+	DP (printf
+	    ("setting up sdram_timing_control_low with: %08x \n",
+	     0x11511220));
+	GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
+
+
+/* ------------------------------------------------------------------------------ */
+
+	/* SDRAM configuration */
+	tmp = GTREGREAD (SDRAM_CONFIG);
+
+	if (info->registeredAddrAndControlInputs
+	    || info->registeredDQMBinputs) {
+		tmp |= (1 << 17);
+		DP (printf
+		    ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
+		     info->registeredAddrAndControlInputs,
+		     info->registeredDQMBinputs));
+	}
+
+	/* Use buffer 1 to return read data to the CPU
+	 * Page 426 MV64360 */
+	tmp |= (1 << 26);
+	DP (printf
+	    ("Before Buffer assignment - sdram_conf: %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+	DP (printf
+	    ("After Buffer assignment - sdram_conf: %08x\n",
+	     GTREGREAD (SDRAM_CONFIG)));
+
+	/* SDRAM timing To_do: */
+
+
+	tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
+	DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp));
+
+	/* SDRAM address decode register */
+	/* program this with the default value */
+	tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
+	DP (printf
+	    ("SDRAM address control (before: decode): %08x  ",
+	     GTREGREAD (SDRAM_ADDR_CONTROL)));
+	GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
+	DP (printf
+	    ("SDRAM address control (after: decode): %08x\n",
+	     GTREGREAD (SDRAM_ADDR_CONTROL)));
+
+	/* set the SDRAM configuration for each bank */
+
+/*	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
+	{
+		i = info->slot;
+		DP (printf
+		    ("\n*** Running a MRS cycle for bank %d ***\n", i));
+
+		/* map the bank */
+		memory_map_bank (i, 0, GB / 4);
+#if 1				/* test only */
+		/* set SDRAM mode */ /* To_do check it */
+		GT_REG_WRITE (SDRAM_OPERATION, 0x3);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+
+
+		/* switch back to normal operation mode */
+		GT_REG_WRITE (SDRAM_OPERATION, 0);
+		check = GTREGREAD (SDRAM_OPERATION);
+		DP (printf
+		    ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
+		     check));
+#endif /* test only */
+		/* unmap the bank */
+		memory_map_bank (i, 0, 0);
+	}
+
+	return 0;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+long int
+dram_size(long int *base, long int maxsize)
+{
+    volatile long int	 *addr, *b=base;
+    long int	 cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+    for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
+	    addr = base + cnt;	/* pointer arith! */
+
+	    save1=*addr;		/* save contents of addr */
+	    save2=*b;		/* save contents of base */
+
+	    *addr=cnt;		/* write cnt to addr */
+	    *b=0;			/* put null at base */
+
+	    /* check at base address */
+	    if ((*b) != 0) {
+		*addr=save1;	/* restore *addr */
+		*b=save2;	/* restore *b */
+		return (0);
+	    }
+	    val = *addr;		/* read *addr */
+	    val = *addr;		/* read *addr */
+
+	    *addr=save1;
+	    *b=save2;
+
+	    if (val != cnt) {
+		    DP(printf("Found %08x  at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr));
+		    /* fix boundary condition.. STARTVAL means zero */
+		    if(cnt==STARTVAL/sizeof(long)) cnt=0;
+		    return (cnt * sizeof(long));
+	    }
+    }
+    return maxsize;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* ppcboot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+long int
+initdram(int board_type)
+{
+	int s0 = 0, s1 = 0;
+	int checkbank[4] = { [0 ... 3] = 0 };
+		ulong bank_no, realsize, total, check;
+	AUX_MEM_DIMM_INFO dimmInfo1;
+	AUX_MEM_DIMM_INFO dimmInfo2;
+	int nhr;
+
+	/* first, use the SPD to get info about the SDRAM/ DDRRAM */
+
+	/* check the NHR bit and skip mem init if it's already done */
+	nhr = get_hid0() & (1 << 16);
+
+	if (nhr) {
+		printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
+	} else {
+		/* DIMM0 */
+		s0 = check_dimm(0, &dimmInfo1);
+
+		/* DIMM1 */
+		s1 = check_dimm(1, &dimmInfo2);
+
+		memory_map_bank(0, 0, 0);
+		memory_map_bank(1, 0, 0);
+		memory_map_bank(2, 0, 0);
+		memory_map_bank(3, 0, 0);
+
+		if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
+			printf("Setup for DIMM1 failed.\n");
+		}
+
+		if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
+			printf("Setup for DIMM2 failed.\n");
+		}
+
+		/* set the NHR bit */
+		set_hid0(get_hid0() | (1 << 16));
+	}
+	/* next, size the SDRAM banks */
+
+	realsize = total = 0;
+	check = GB/4;
+	if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
+	if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
+	if (dimmInfo1.numOfModuleBanks > 2)
+		printf("Error, SPD claims DIMM1 has >2 banks\n");
+
+	if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
+	if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
+	if (dimmInfo2.numOfModuleBanks > 2)
+		printf("Error, SPD claims DIMM2 has >2 banks\n");
+
+	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+		/* skip over banks that are not populated */
+		if (! checkbank[bank_no])
+			continue;
+
+		if ((total + check) > CFG_GT_REGS)
+			check = CFG_GT_REGS - total;
+
+		memory_map_bank(bank_no, total, check);
+		realsize = dram_size((long int *)total, check);
+		memory_map_bank(bank_no, total, realsize);
+
+		total += realsize;
+	}
+
+/*	Setup Ethernet DMA Adress window to DRAM Area */
+	return(total);
+}
+
+/* ***************************************************************************************
+! *                             SDRAM INIT                                              *
+! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb       *
+! *               This procedure fits only the Atlantis                                *
+! *                                                                                     *
+! *************************************************************************************** */
+
+
+/* ***************************************************************************************
+! *                             DFCDL initialize MV643xx Design Considerations             *
+! *                                                                                     *
+! *************************************************************************************** */
+int set_dfcdlInit (void)
+{
+	int i;
+	unsigned int dfcdl_word = 0x0000014f;
+
+	for (i = 0; i < 64; i++) {
+		GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
+	}
+	GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);	/* enable dynamic delay line updating */
+
+
+	return (0);
+}
diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c
new file mode 100755
index 0000000..44de052
--- /dev/null
+++ b/board/esd/cpci750/serial.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * modified for cpci750 board by
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * serial.c - serial support for esd cpci750 board
+ */
+
+/* supports the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include "../../Marvell/include/memory.h"
+#include "serial.h"
+
+
+#include "mpsc.h"
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	mpsc_init (gd->baudrate);
+
+	return (0);
+}
+
+void serial_putc (const char c)
+{
+	if (c == '\n')
+		mpsc_putchar ('\r');
+
+	mpsc_putchar (c);
+}
+
+int serial_getc (void)
+{
+	return mpsc_getchar ();
+}
+
+int serial_tstc (void)
+{
+	return mpsc_test_char ();
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+
+void serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+void kgdb_serial_init (void)
+{
+}
+
+void putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int getDebugChar (void)
+{
+	return serial_getc ();
+}
+
+void kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif /* CFG_CMD_KGDB */
diff --git a/board/esd/cpci750/serial.h b/board/esd/cpci750/serial.h
new file mode 100755
index 0000000..c7fc8c1
--- /dev/null
+++ b/board/esd/cpci750/serial.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * modified for marvell db64360 eval board by
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* serial.h - mostly useful for DUART serial_init in serial.c */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#if 0
+
+#define B230400         1
+#define B115200         2
+#define B57600          4
+#define B38400          82
+#define B19200          163
+#define B9600           24
+#define B4800           651
+#define B2400           1302
+#define B1200           2604
+#define B600            5208
+#define B300            10417
+#define B150            20833
+#define B110            28409
+#define BDEFAULT        B115200
+
+				/* this stuff is important to initialize
+				the DUART channels */
+
+#define	Scale		0x01L		/* distance between port addresses */
+#define	COM1		0x000003f8		/* Keyboard */
+#define COM2		0x000002f8		/* Host */
+
+
+/* Port Definitions relative to base COM port addresses */
+#define DataIn	(0x00*Scale)	/* data input port */
+#define DataOut	(0x00*Scale)	/* data output port */
+#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
+#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
+#define	Ier	(0x01*Scale)	/* interrupt enable register */
+#define	Iir	(0x02*Scale)	/* interrupt identification register */
+#define	Lcr	(0x03*Scale)	/* line control register */
+#define	Mcr	(0x04*Scale)	/* modem control register */
+#define	Lsr	(0x05*Scale)	/* line status register */
+#define	Msr	(0x06*Scale)	/* modem status register */
+
+/* Bit Definitions for above ports */
+#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
+#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
+
+#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
+#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
+#define	McrDflt	(McrRts|McrDtr)
+
+#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
+			/* b6: transmitter empty */
+#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
+
+#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
+#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
+#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
+
+#define IerRda	0xf	/* b0: Enable received data available interrupt */
+
+#endif
+
+#endif /* __SERIAL_H__ */
diff --git a/board/esd/cpci750/strataflash.c b/board/esd/cpci750/strataflash.c
new file mode 100755
index 0000000..c22fe5d
--- /dev/null
+++ b/board/esd/cpci750/strataflash.c
@@ -0,0 +1,763 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+
+#define FLASH_MAN_CFI			0x01000000
+
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+#if 0 /* test-only */
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n");
+		printf (" %08lX%5s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : " "
+			);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+		        retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+ */
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio = 0;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	invalidate_dcache_range(base, base+0x400);
+
+	if(flash_detect_cfi(info)){
+
+	        size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+#ifdef DEBUG_FLASH
+	printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+#ifdef DEBUG_FLASH
+	printf("found %d erase regions\n", num_erase_regions);
+#endif
+#ifdef DEBUG_FLASH
+	printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
+#endif
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/cpci750/u-boot.lds b/board/esd/cpci750/u-boot.lds
new file mode 100755
index 0000000..d89eb6c
--- /dev/null
+++ b/board/esd/cpci750/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile
new file mode 100755
index 0000000..a60495a
--- /dev/null
+++ b/board/esd/cpciiser4/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/cpciiser4/config.mk b/board/esd/cpciiser4/config.mk
new file mode 100755
index 0000000..58574cb
--- /dev/null
+++ b/board/esd/cpciiser4/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd CPCIISER4 boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+#TEXT_BASE = 0xFFFD0000
+TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c
new file mode 100755
index 0000000..7bf7bb5
--- /dev/null
+++ b/board/esd/cpciiser4/cpciiser4.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2000
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "cpciiser4.h"
+#include <asm/processor.h>
+#include <command.h>
+
+/*cmd_boot.c*/
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
+
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#if 0
+#define FPGA_DEBUG2
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int index, len, i;
+	volatile unsigned char dummy;
+	int status;
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+		/* set up serial port with default baudrate */
+		(void) get_clocks ();
+		gd->baudrate = CONFIG_BAUDRATE;
+		serial_init ();
+		console_init_f ();
+#endif
+		printf ("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf ("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf ("Rebooting in %2d seconds \r", i);
+			for (index = 0; index < 1000; index++)
+				udelay (1000);
+		}
+		putc ('\n');
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	/*
+	 * Init FPGA via RESET (read access on CS3)
+	 */
+	dummy = *(unsigned char *) 0xf0200000;
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
+	/*  mtdcr(uicpr, 0xFFFFFF81);   /  set int polarities */
+	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming AR405");
+	} else {
+		puts(str);
+	}
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf ("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	return (16 * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/esd/cpciiser4/cpciiser4.h b/board/esd/cpciiser4/cpciiser4.h
new file mode 100755
index 0000000..5fc313a
--- /dev/null
+++ b/board/esd/cpciiser4/cpciiser4.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c
new file mode 100755
index 0000000..de847f9
--- /dev/null
+++ b/board/esd/cpciiser4/flash.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+	mtdcr(ebccfgd, pbcr);
+	/*          printf("pb1cr = %x\n", pbcr); */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/cpciiser4/fpgadata.c b/board/esd/cpciiser4/fpgadata.c
new file mode 100755
index 0000000..5e02097
--- /dev/null
+++ b/board/esd/cpciiser4/fpgadata.c
@@ -0,0 +1,2068 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0c,
+ 0x69,0x73,0x65,0x72,0x34,0x5f,0x31,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,0x73,
+ 0x34,0x30,0x78,0x6c,0x70,0x71,0x32,0x30,0x38,0x00,0x63,0x00,0x0b,0x32,0x30,0x30,
+ 0x31,0x2f,0x30,0x33,0x2f,0x31,0x39,0x00,0x64,0x00,0x09,0x31,0x36,0x3a,0x31,0x34,
+ 0x3a,0x32,0x35,0x00,0x65,0xe2,0x01,0x00,0x00,0x80,0xf0,0xff,0x30,0xe5,0xe5,0xe8,
+ 0xe5,0x03,0xe8,0x04,0x01,0x02,0x09,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x07,0x0b,0x01,0x07,0x01,0x05,0x09,0x03,0x07,0x09,0x01,0x05,0x03,0x05,0x0b,0x0c,
+ 0x08,0x01,0x07,0x01,0x05,0x03,0x05,0x03,0x07,0x01,0x07,0x02,0x04,0x03,0x07,0x01,
+ 0x09,0x07,0x01,0x07,0x01,0x07,0x08,0xe7,0x0c,0x09,0x09,0x09,0x09,0x09,0x02,0x04,
+ 0x0b,0x09,0x06,0xe5,0xe5,0x01,0x03,0xe5,0xe5,0x08,0x02,0x06,0x07,0x01,0x06,0xe5,
+ 0x02,0x02,0x04,0x01,0x02,0xe5,0x02,0x02,0x08,0x09,0x09,0x09,0x09,0x13,0x09,0x07,
+ 0x01,0x09,0x09,0x13,0xe5,0x47,0x05,0x17,0x04,0x04,0x0e,0x0e,0x09,0x06,0x04,0x09,
+ 0x59,0x25,0x02,0xe5,0x0e,0x09,0x09,0x09,0x09,0x09,0x01,0x05,0xe6,0x08,0x09,0x09,
+ 0x01,0x07,0x09,0x01,0x07,0x09,0x0b,0x01,0x07,0x01,0x04,0x01,0x0a,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,0xe8,0x13,0x09,0x09,0x09,0x09,0x0a,0xe7,
+ 0x04,0x09,0x0a,0xe5,0x07,0xe5,0x06,0x09,0x0a,0xe5,0x07,0xe5,0x09,0xe5,0x06,0xe8,
+ 0x04,0x09,0x09,0xe5,0x07,0xe5,0x07,0x09,0x03,0x05,0xe5,0x07,0x0a,0xe5,0x06,0x09,
+ 0x09,0x09,0x03,0x40,0x08,0x1d,0xe5,0x12,0x1f,0x08,0xe5,0x07,0x01,0x55,0x26,0x01,
+ 0xe6,0xe5,0x46,0x31,0x1f,0x13,0x58,0x25,0xe6,0xe5,0x3f,0x04,0x1d,0x04,0x04,0x0e,
+ 0x0e,0x09,0x03,0x02,0x04,0x04,0x0a,0x53,0x28,0x02,0xe5,0xe5,0x10,0x09,0x09,0x02,
+ 0x06,0x09,0x1d,0x1d,0x09,0x17,0x1b,0x01,0x07,0x1d,0x09,0x02,0x10,0x13,0x09,0x09,
+ 0x0a,0x03,0x01,0x48,0x1f,0x11,0x01,0x1d,0x01,0x09,0x07,0x7e,0x01,0xe5,0xe5,0x42,
+ 0x1d,0x04,0x04,0x1d,0x09,0x0b,0x15,0x4d,0x28,0x01,0x01,0x99,0x95,0xe7,0x28,0x6f,
+ 0x0a,0x44,0x44,0xe5,0xe6,0x0f,0x09,0x09,0x04,0x04,0x09,0x09,0x09,0x09,0x03,0x05,
+ 0x05,0x03,0x09,0x09,0x09,0x09,0x0b,0x01,0x01,0x01,0x03,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x04,0x04,0x09,0x09,0x09,0x09,0x09,0x0e,0xe7,0x0f,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x07,0x03,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x03,0x0d,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x04,
+ 0x02,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x08,0xe6,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x0f,0x01,0xe5,0x0f,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,
+ 0x09,0x09,0xe5,0x07,0x09,0x09,0x06,0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x04,0x0b,0xe5,0x05,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0x02,0x06,0xe5,0x0e,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,
+ 0x04,0x09,0x04,0x04,0x09,0x0b,0x04,0x04,0x04,0x04,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x12,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x08,
+ 0xe5,0x08,0x06,0x02,0x09,0x09,0x09,0x01,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x07,0x08,0xe5,0x01,0x0d,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x09,0x06,0x02,0x04,0x01,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x06,0x02,0x06,0x04,0x04,0x01,0x02,0x06,0x02,0x06,0x02,0x06,0x02,
+ 0x05,0xe5,0x01,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x06,
+ 0x02,0x06,0x02,0x0e,0xe7,0x02,0x3b,0x11,0x25,0x1c,0x06,0x04,0x89,0x04,0x02,0x03,
+ 0x4d,0x46,0x02,0x19,0x0a,0x6f,0xe6,0x02,0x3b,0x12,0x22,0x02,0x1d,0x03,0x07,0x01,
+ 0x89,0xe5,0xe6,0x3f,0x08,0xe5,0x05,0x2a,0x17,0x11,0x18,0xe5,0x01,0xe5,0x68,0x03,
+ 0x10,0x09,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x09,0x04,0x04,0x09,0x09,0x09,0x09,
+ 0x0b,0x09,0x09,0x09,0x07,0x01,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,
+ 0x01,0x01,0x3f,0x01,0xe5,0x0d,0x0b,0x01,0xe5,0x02,0x02,0x1d,0x09,0x02,0x08,0x21,
+ 0x0f,0x02,0x1a,0x01,0xe5,0x3f,0xe5,0xe5,0x10,0x2d,0x1e,0x26,0x09,0x06,0x37,0x60,
+ 0x01,0xe5,0x67,0x26,0x0c,0x30,0x1e,0x43,0xe6,0x05,0x54,0x0f,0x2a,0x08,0xe5,0x0b,
+ 0x80,0x02,0xe5,0xd0,0x60,0x56,0x09,0x8a,0x01,0x40,0xe5,0x01,0x6e,0x1a,0x61,0x01,
+ 0x40,0xe8,0x05,0x85,0xa1,0xe5,0x01,0x61,0x38,0x14,0x09,0x01,0x0e,0x63,0xe6,0xe5,
+ 0x10,0x3f,0x5f,0x7c,0x02,0xe5,0x8e,0xe6,0x9f,0x91,0x9d,0x02,0x88,0x0c,0x98,0x03,
+ 0x63,0x3f,0x05,0x07,0x7c,0xe8,0xaa,0x05,0x40,0x3b,0x01,0x01,0xe6,0x06,0xe5,0x65,
+ 0x16,0x03,0xe5,0x04,0x1f,0xe5,0x07,0x0f,0x5e,0xe5,0x03,0x02,0x01,0x04,0xe5,0x65,
+ 0x20,0x20,0x09,0x0f,0x5b,0x01,0x06,0x04,0x6c,0x30,0xe5,0xe5,0xe5,0x08,0x04,0x01,
+ 0xe5,0x12,0x5b,0x04,0xe5,0xe6,0x01,0x6e,0x30,0x02,0x01,0x03,0xe5,0x01,0x09,0x13,
+ 0x5d,0x02,0xe8,0x70,0x22,0x0e,0x10,0x09,0x0e,0x61,0xe5,0xe5,0x01,0x6e,0x03,0x33,
+ 0x05,0x04,0x03,0x05,0x0e,0x03,0x59,0x02,0x01,0xe7,0x6f,0x1a,0x01,0x04,0x11,0x01,
+ 0x09,0x04,0xe5,0x02,0x11,0x5f,0x01,0xe5,0xe5,0x70,0x22,0x01,0x01,0x0c,0x01,0x0c,
+ 0xe7,0x02,0x02,0x0e,0x63,0xe5,0x91,0x1f,0x02,0x02,0x75,0xe5,0xe6,0x10,0x80,0xe5,
+ 0x1e,0x02,0x78,0xe5,0xe6,0x08,0x01,0x02,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x02,0x06,0x09,0x09,0xe6,0x08,0x09,0x09,0x01,0x01,0x05,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe5,0xe5,0xe5,0x01,0x09,0xa1,0x09,0x72,
+ 0x03,0x02,0x0b,0x05,0x9b,0x07,0x7a,0x01,0x92,0xe6,0x16,0x05,0xe6,0x08,0x6d,0x02,
+ 0xe7,0xe5,0x03,0x0a,0x81,0x1b,0x01,0x01,0x02,0x06,0x73,0xe5,0x92,0x01,0x1b,0x01,
+ 0x01,0x78,0xe5,0x01,0x01,0x04,0x0e,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x09,0xe5,0x07,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe8,
+ 0x08,0x05,0xa1,0x09,0x74,0x01,0x0d,0xa1,0x09,0x74,0xe5,0x01,0x0f,0x8a,0x16,0x09,
+ 0x73,0xe5,0xe5,0x0c,0x04,0x81,0x1a,0x04,0x04,0x04,0x6f,0xe5,0xe6,0x70,0x01,0xe5,
+ 0x39,0x02,0x06,0x02,0x0d,0x02,0xe5,0xe5,0x5c,0xe5,0xe6,0xe5,0x0e,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x03,0x03,0x01,0x07,0x01,0x07,0x01,0xe6,0x04,0x01,0x01,0x02,0x04,0x01,0x01,0x05,
+ 0x01,0x04,0x02,0x01,0x01,0x02,0x02,0x01,0x07,0x01,0x03,0x03,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x01,0x03,
+ 0x7a,0x08,0x2b,0x01,0xe5,0x05,0x01,0xe5,0x71,0x01,0xe6,0x88,0x0d,0x17,0xe5,0x04,
+ 0x02,0xe5,0x70,0xe6,0xe6,0x83,0x04,0x0f,0x1e,0x75,0x03,0x0f,0x5e,0x1d,0x0b,0x01,
+ 0x04,0x0f,0x01,0x05,0x77,0xe7,0x0c,0x80,0x0a,0x15,0x02,0xe5,0x7a,0x02,0x7d,0x04,
+ 0x04,0x08,0xe5,0x06,0x05,0xe5,0x0e,0xe5,0x16,0x64,0x01,0x01,0x82,0x02,0xe5,0xe5,
+ 0x05,0x09,0x15,0x09,0x04,0x08,0x04,0x62,0xe5,0xe5,0x6e,0x0e,0x08,0x09,0x07,0x15,
+ 0x0b,0x72,0xe6,0xe5,0x6e,0x1a,0x03,0x0a,0xe5,0x16,0x05,0x75,0xe5,0xe6,0x77,0x1d,
+ 0x01,0xe5,0x0f,0x83,0x02,0xe5,0x7c,0xe5,0xe5,0x09,0x05,0x1d,0x01,0x7d,0xe8,0x7a,
+ 0x07,0x02,0x0a,0x0c,0x11,0x06,0x02,0x0d,0x63,0xe6,0x01,0x11,0x5c,0x18,0x07,0x20,
+ 0x02,0x07,0x73,0xe9,0x72,0x09,0x02,0xe5,0x04,0xe5,0x03,0x0b,0x13,0x09,0x72,0xe8,
+ 0xe5,0x01,0x01,0x6d,0xe5,0xe5,0x08,0x02,0xe5,0xe5,0x02,0x05,0xe5,0x02,0x06,0x1d,
+ 0xe5,0x6d,0x01,0x02,0xe6,0xe5,0x03,0x69,0xe5,0xe5,0xe5,0x17,0xe5,0xe5,0xe5,0x03,
+ 0x01,0x02,0x01,0x0e,0xe5,0x07,0xe5,0xe5,0x6e,0x04,0xe8,0x01,0x6a,0xe5,0x01,0x01,
+ 0x0d,0xe5,0x01,0x06,0x02,0x01,0x04,0xe5,0x02,0x01,0x0e,0x09,0x02,0x71,0x02,0x03,
+ 0x73,0x02,0x04,0x0e,0x02,0x01,0x01,0xe5,0x02,0x01,0x02,0x11,0x04,0x04,0xe6,0x05,
+ 0x01,0x6c,0x02,0x02,0x70,0x02,0x04,0x09,0x03,0x05,0x01,0xe5,0x01,0x02,0x02,0x03,
+ 0x17,0x01,0x03,0x02,0x01,0x68,0x02,0xe5,0xe7,0x6f,0x01,0x07,0x09,0x01,0x02,0x04,
+ 0x01,0x09,0x01,0x1b,0x73,0x04,0x71,0x01,0x02,0x04,0x04,0x04,0x01,0x01,0xe5,0x03,
+ 0x01,0xe5,0x07,0x01,0x1b,0x75,0xe7,0x80,0x02,0x03,0x09,0x02,0x02,0x08,0x02,0x1a,
+ 0xe5,0x6e,0xe6,0x75,0x01,0x06,0x02,0xe5,0x03,0xe5,0x01,0xe5,0x07,0x0b,0x13,0x09,
+ 0x6d,0x01,0xe7,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x02,
+ 0x02,0x09,0xe5,0x04,0x02,0xe5,0x01,0x02,0x04,0x05,0x03,0x09,0x05,0x03,0x02,0xe5,
+ 0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe5,0x01,0xe5,0x01,0x6d,
+ 0x04,0x03,0xe5,0x08,0x06,0x0b,0x20,0x72,0x02,0xe8,0x6c,0x0b,0x08,0x06,0x2d,0x77,
+ 0x02,0x01,0x71,0x02,0x04,0x01,0x02,0x01,0x02,0x01,0xe7,0x03,0x01,0xe5,0x1e,0x79,
+ 0x01,0x03,0x71,0x03,0x05,0x01,0x01,0x01,0x03,0x01,0xe6,0x04,0x01,0x06,0x05,0x19,
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+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x04,0x02,0x01,0x04,0x02,0x01,0x02,0x04,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x02,0x02,0x20,0x0a,0x3d,0x06,
+ 0x03,0x02,0x05,0xe6,0x0e,0x06,0x41,0x07,0x08,0xe5,0x42,0x02,0xe6,0x23,0x31,0xe5,
+ 0x0f,0x08,0x01,0x02,0x22,0x40,0x08,0x48,0x01,0xe7,0x69,0x05,0x0a,0x01,0x1b,0x94,
+ 0x01,0x01,0x21,0xe6,0x2e,0x01,0x11,0x01,0x07,0xe6,0x04,0x01,0xe7,0x0f,0x01,0x19,
+ 0x05,0x32,0x06,0x46,0x22,0x04,0x11,0x1b,0x12,0x01,0x07,0x09,0x0e,0x03,0x01,0x07,
+ 0x15,0x0f,0x1d,0x10,0x0c,0x33,0xe5,0xe5,0x41,0x09,0x06,0x02,0x35,0x04,0x03,0x03,
+ 0x98,0x43,0x1c,0x04,0x04,0x0b,0x09,0x0e,0x09,0x4b,0x3d,0x0c,0x01,0x1c,0xe5,0x01,
+ 0x37,0x0d,0x05,0x13,0x0c,0x03,0xe5,0x05,0x95,0xe7,0x5b,0x32,0xe5,0x07,0x18,0x7d,
+ 0xe6,0x56,0x32,0x04,0x01,0x01,0x05,0xe5,0x03,0x3b,0xe5,0x1b,0x34,0x01,0x01,0x27,
+ 0x01,0x44,0x1c,0x59,0x49,0xe8,0x41,0x44,0x0a,0x19,0x7f,0x02,0xe6,0x44,0x32,0x1b,
+ 0x9a,0xe5,0xe7,0x24,0xe5,0x39,0xe5,0x05,0xe5,0x07,0x01,0xe5,0x05,0xe5,0x08,0x08,
+ 0x98,0xe5,0x02,0xe5,0x01,0x01,0x23,0x01,0x38,0xe5,0x03,0x08,0x02,0x01,0xe5,0x02,
+ 0x09,0x0a,0xe5,0x95,0x01,0x05,0xe5,0x03,0x37,0x01,0xe5,0xe5,0x28,0x02,0x09,0x06,
+ 0x02,0x09,0x01,0xe5,0x98,0x05,0xe7,0x01,0x3c,0x01,0x27,0x04,0x01,0x02,0x04,0x01,
+ 0x02,0x04,0x01,0x02,0x04,0x9e,0x03,0x01,0xe5,0x6b,0xe5,0x01,0x02,0x02,0xe5,0x01,
+ 0x02,0x02,0xe5,0x01,0x02,0x02,0xe5,0xe6,0x01,0x03,0x02,0x96,0x02,0x02,0x40,0x25,
+ 0x02,0x09,0x01,0x01,0x05,0x09,0x08,0x97,0x02,0x01,0x01,0xe5,0x3d,0x01,0x4a,0x01,
+ 0x9e,0xe5,0xe7,0x3e,0x01,0x27,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0x01,0x01,0xe5,
+ 0x9f,0xe6,0x66,0x09,0x05,0x03,0x05,0x03,0x05,0x09,0x98,0xe8,0x76,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x03,0x03,0xe5,0x98,0x01,0xe5,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x04,0x01,0xe5,0xe5,0x05,0xe5,0xe5,0x03,0x01,0xe5,0xe5,0x05,0x02,0x0b,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe5,0x01,
+ 0xe5,0x01,0x6d,0xe5,0xe5,0x04,0xe6,0xe5,0x05,0xe5,0xe5,0x04,0xe5,0x9b,0x02,0x01,
+ 0x01,0x6d,0x06,0x04,0x04,0x02,0x06,0x04,0xa0,0x03,0x01,0x74,0x01,0x07,0x01,0x07,
+ 0x09,0x97,0x01,0x02,0xe5,0x27,0x42,0x09,0x09,0x09,0x09,0x9a,0x03,0x71,0x05,0x03,
+ 0x09,0x06,0xa1,0xe6,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x01,
+ 0x05,0xe5,0x07,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x06,0xe5,0x01,0x71,0x09,0x09,0x09,0x9e,0xe8,0x72,0x09,0x09,0x09,0x9c,0x03,0x91,
+ 0x08,0x93,0x02,0xe5,0x2d,0x3d,0x09,0x09,0x09,0x04,0x04,0x9a,0xe5,0xe5,0x66,0x01,
+ 0xe5,0x05,0x09,0x01,0xe5,0x05,0x09,0x12,0x8b,0xe5,0xe6,0xe5,0x0e,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x06,0xe5,0xe5,0x06,0x01,0x04,
+ 0x02,0x01,0x04,0x02,0xe8,0x01,0x02,0x01,0xe5,0x02,0x02,0x01,0x02,0xe5,0x02,0x01,
+ 0x04,0x04,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x08,0x01,0xe6,0xe5,0x3c,0x35,0x01,0x09,0x0e,0x9f,0x01,0xe7,0x36,0xe3,0x12,0xe5,
+ 0xe7,0x46,0x13,0x17,0x25,0x8a,0x0a,0xe5,0xe5,0x1c,0x48,0x0c,0x09,0x07,0xe5,0x07,
+ 0xa0,0xe6,0x47,0x1b,0x12,0x0c,0x0d,0x06,0x3c,0x5b,0x5c,0x03,0x0f,0xe5,0x08,0x0a,
+ 0xe5,0x10,0x16,0xe5,0x05,0x6d,0x07,0xe5,0x01,0x63,0x21,0x13,0x15,0x7e,0x02,0xe5,
+ 0x61,0x13,0x01,0x0c,0x13,0x11,0x05,0x7d,0xe5,0xe5,0x91,0x06,0x94,0xe5,0x01,0x8a,
+ 0x0d,0xe5,0x93,0x02,0xe5,0x61,0x24,0x12,0x06,0x05,0x27,0x09,0x57,0xe6,0x37,0x32,
+ 0x1b,0x1d,0xe5,0x24,0x01,0x08,0x54,0xe5,0x01,0xe5,0x3a,0x49,0x21,0x25,0x60,0xe5,
+ 0xe6,0x02,0x09,0xe7,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x03,0xe5,0x01,0xe5,0x07,0xe5,0x05,0xe7,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0xe7,
+ 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x01,0x09,0xe5,0x01,
+ 0xe5,0x0d,0x01,0x09,0x09,0x09,0x09,0x02,0x06,0x02,0x06,0x07,0x01,0x09,0x07,0x01,
+ 0x05,0x03,0x09,0x09,0x07,0x01,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x02,0x0a,0x03,0x0f,0x05,0x03,0x09,0x09,0x09,0x04,0x04,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x0a,0x11,0x02,0xe5,0x11,0xe5,0x03,0x03,0x09,0x1d,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x11,0xe5,0x97,0x8b,0x09,0x01,0xe6,0x0e,0x05,0x03,0x09,
+ 0x09,0x09,0x09,0x04,0x04,0x09,0x09,0x04,0x04,0x09,0x06,0x02,0x09,0x09,0x06,0x01,
+ 0x02,0x09,0x09,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,
+ 0xe5,0x01,0x0d,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x06,0xe6,0x07,0xe5,0x09,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x10,0xe6,0x02,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x08,0xe5,0x08,0x03,0x05,0x09,0x03,0x05,0x09,0x01,
+ 0x07,0x0b,0x01,0x07,0x09,0x01,0x07,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x0b,0x05,0xe5,0xe5,0x0d,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,0x02,0x08,0xe5,0x07,0x02,
+ 0x06,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x02,0x06,0x02,0x06,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x0b,0x01,0x01,0x0e,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x0f,0xe6,0xe5,0x86,0x09,0x15,0x27,0x09,0x4e,0x05,0xe5,0x01,0x0e,0x09,0x09,0x09,
+ 0x09,0x13,0x13,0x05,0x03,0x09,0x09,0x09,0x09,0x08,0x02,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x07,0xe6,0x3f,0x13,0x10,0x33,0x1d,
+ 0x76,0x03,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x05,
+ 0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x0e,0xe7,0x03,0x37,0x03,0x05,0x0d,0x0f,0xe5,0x33,0x1c,0x72,0x03,0xe6,0xe5,0x37,
+ 0x09,0x13,0x42,0xe5,0x8e,0x04,0xe7,0x3f,0x13,0x44,0x90,0x03,0xe6,0xe5,0x8f,0x9d,
+ 0x03,0x13,0x09,0x09,0x09,0x1d,0x09,0x0c,0x06,0x09,0x09,0x36,0x06,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x15,0x01,0xe5,0x35,0x05,0x03,0x05,0x0d,0x0f,0x2a,
+ 0x97,0x06,0x02,0xe5,0x98,0x8e,0x05,0x03,0xe3,0x50,0x14,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x02,0xe5,0x04,0xe6,0x01,0xe5,0x04,0x09,0xe8,
+ 0x04,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x0f,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x03,0x05,0x09,0x09,0x08,0xe5,0x06,0xe6,
+ 0x05,0xe5,0xe7,0x07,0xe5,0x05,0xe7,0x08,0x09,0x08,0xe5,0x07,0xe5,0x08,0x07,0xe6,
+ 0x08,0x09,0x09,0x09,0x09,0x0f,0x01,0xe5,0x38,0x09,0x13,0x0a,0x36,0x95,0x02,0x0d,
+ 0x09,0x09,0x09,0x09,0x04,0x04,0x03,0xe5,0x03,0x09,0x03,0x05,0x04,0x04,0x09,0x09,
+ 0x11,0x09,0x0b,0x09,0x09,0x01,0x09,0x1d,0x0b,0x07,0x09,0x09,0x09,0x09,0x0f,0x01,
+ 0xe7,0x0a,0x02,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x03,0x02,0x02,0x03,0x01,0xe5,
+ 0x01,0x01,0x07,0x03,0x05,0x01,0x04,0x02,0x01,0x07,0x01,0x07,0x01,0x07,0x02,0x04,
+ 0x15,0x04,0x0e,0x03,0x07,0x01,0x07,0x02,0x06,0x02,0x06,0x01,0x07,0x09,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x05,0xe6,0xe5,0xe5,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
diff --git a/board/esd/cpciiser4/u-boot.lds b/board/esd/cpciiser4/u-boot.lds
new file mode 100755
index 0000000..f7a20d1
--- /dev/null
+++ b/board/esd/cpciiser4/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile
new file mode 100755
index 0000000..e3b1c87
--- /dev/null
+++ b/board/esd/dasa_sim/Makefile
@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c
new file mode 100755
index 0000000..89a4aaf
--- /dev/null
+++ b/board/esd/dasa_sim/cmd_dasa_sim.c
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+
+#define OK 0
+#define ERROR (-1)
+
+#define TRUE 1
+#define FALSE 0
+
+
+extern u_long pci9054_iobase;
+
+
+/***************************************************************************
+ *
+ * Routines for PLX PCI9054 eeprom access
+ *
+ */
+
+static unsigned int PciEepromReadLongVPD (int offs)
+{
+	unsigned int value;
+	unsigned int ret;
+	int count;
+
+	pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c,
+				(offs << 16) | 0x0003);
+	count = 0;
+
+	for (;;) {
+		udelay (10 * 1000);
+		pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret);
+		if ((ret & 0x80000000) != 0) {
+			break;
+		} else {
+			count++;
+			if (count > 10) {
+				printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
+				break;
+			}
+		}
+	}
+
+	pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x50, &value);
+
+	return value;
+}
+
+
+static int PciEepromWriteLongVPD (int offs, unsigned int value)
+{
+	unsigned int ret;
+	int count;
+
+	pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x50, value);
+	pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c,
+				(offs << 16) | 0x80000003);
+	count = 0;
+
+	for (;;) {
+		udelay (10 * 1000);
+		pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret);
+		if ((ret & 0x80000000) == 0) {
+			break;
+		} else {
+			count++;
+			if (count > 10) {
+				printf ("\nTimeout: ret=%08x - Please try again!\n", ret);
+				break;
+			}
+		}
+	}
+
+	return TRUE;
+}
+
+
+static void showPci9054 (void)
+{
+	int val;
+	int l, i;
+
+	/* read 9054-values */
+	for (l = 0; l < 6; l++) {
+		printf ("%02x: ", l * 0x10);
+		for (i = 0; i < 4; i++) {
+			pci_read_config_dword (CFG_PCI9054_DEV_FN,
+						l * 16 + i * 4,
+						(unsigned int *)&val);
+			printf ("%08x ", val);
+		}
+		printf ("\n");
+	}
+	printf ("\n");
+
+	for (l = 0; l < 7; l++) {
+		printf ("%02x: ", l * 0x10);
+		for (i = 0; i < 4; i++)
+			printf ("%08x ",
+				PciEepromReadLongVPD ((i + l * 4) * 4));
+		printf ("\n");
+	}
+	printf ("\n");
+}
+
+
+static void updatePci9054 (void)
+{
+	int val;
+
+	/*
+	 * Set EEPROM write-protect register to 0
+	 */
+	out32 (pci9054_iobase + 0x0c,
+		   in32 (pci9054_iobase + 0x0c) & 0xffff00ff);
+
+	/* Long Serial EEPROM Load Registers... */
+	val = PciEepromWriteLongVPD (0x00, 0x905410b5);
+	val = PciEepromWriteLongVPD (0x04, 0x09800001);	/* other input controller */
+	val = PciEepromWriteLongVPD (0x08, 0x28140100);
+
+	val = PciEepromWriteLongVPD (0x0c, 0x00000000);	/* MBOX0... */
+	val = PciEepromWriteLongVPD (0x10, 0x00000000);
+
+	/* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */
+	val = PciEepromWriteLongVPD (0x14, 0xfffc0000);	/* LAS0RR... */
+	val = PciEepromWriteLongVPD (0x18, 0x00000001);	/* LAS0BA */
+
+	val = PciEepromWriteLongVPD (0x1c, 0x00200000);	/* MARBR... */
+	val = PciEepromWriteLongVPD (0x20, 0x00300500);	/* LMISC/BIGEND */
+
+	val = PciEepromWriteLongVPD (0x24, 0x00000000);	/* EROMRR... */
+	val = PciEepromWriteLongVPD (0x28, 0x00000000);	/* EROMBA */
+
+	val = PciEepromWriteLongVPD (0x2c, 0x43030000);	/* LBRD0... */
+
+	val = PciEepromWriteLongVPD (0x30, 0x00000000);	/* DMRR... */
+	val = PciEepromWriteLongVPD (0x34, 0x00000000);
+	val = PciEepromWriteLongVPD (0x38, 0x00000000);
+
+	val = PciEepromWriteLongVPD (0x3c, 0x00000000);	/* DMPBAM... */
+	val = PciEepromWriteLongVPD (0x40, 0x00000000);
+
+	/* Extra Long Serial EEPROM Load Registers... */
+	val = PciEepromWriteLongVPD (0x44, 0x010212fe);	/* PCISID... */
+
+	/* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */
+	/* Offset to LAS1: Group 1: 0x00040000                 */
+	/*                 Group 2: 0x00080000                 */
+	/*                 Group 3: 0x000c0000                 */
+	val = PciEepromWriteLongVPD (0x48, 0xffe00000);	/* LAS1RR */
+	val = PciEepromWriteLongVPD (0x4c, 0x00040001);	/* LAS1BA */
+	val = PciEepromWriteLongVPD (0x50, 0x00000208);	/* LBRD1 */ /* so wars bisher */
+
+	val = PciEepromWriteLongVPD (0x54, 0x00004c06);	/* HotSwap... */
+
+	printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n");
+}
+
+
+static void clearPci9054 (void)
+{
+	int val;
+
+	/*
+	 * Set EEPROM write-protect register to 0
+	 */
+	out32 (pci9054_iobase + 0x0c,
+		in32 (pci9054_iobase + 0x0c) & 0xffff00ff);
+
+	/* Long Serial EEPROM Load Registers... */
+	val = PciEepromWriteLongVPD (0x00, 0xffffffff);
+	val = PciEepromWriteLongVPD (0x04, 0xffffffff);	/* other input controller */
+
+	printf ("Finished clearing PLX PCI9054 EEPROM!\n");
+}
+
+
+/* ------------------------------------------------------------------------- */
+int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc,
+				char *argv[])
+{
+	if (strcmp (argv[1], "info") == 0) {
+		showPci9054 ();
+		return 0;
+	}
+
+	if (strcmp (argv[1], "update") == 0) {
+		updatePci9054 ();
+		return 0;
+	}
+
+	if (strcmp (argv[1], "clear") == 0) {
+		clearPci9054 ();
+		return 0;
+	}
+
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+
+}
+
+U_BOOT_CMD(
+	pci9054, 3, 1, do_pci9054,
+	"pci9054 - PLX PCI9054 EEPROM access\n",
+	"pci9054 info - print EEPROM values\n"
+	"pci9054 update - updates EEPROM with default values\n"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/esd/dasa_sim/config.mk b/board/esd/dasa_sim/config.mk
new file mode 100755
index 0000000..747f29f
--- /dev/null
+++ b/board/esd/dasa_sim/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+# FLASH:
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0xFFFD0000
+
+# SDRAM:
+#TEXT_BASE = 0x00FE0000
diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c
new file mode 100755
index 0000000..2f8ab1a
--- /dev/null
+++ b/board/esd/dasa_sim/dasa_sim.c
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "dasa_sim.h"
+
+/* ------------------------------------------------------------------------- */
+
+#undef FPGA_DEBUG
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/* ------------------------------------------------------------------------- */
+
+/* fpga configuration data - generated by bit2inc */
+static unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+#define FPGA_PRG_SLEEP         32	/* fpga program sleep-time */
+#define LOAD_LONG(a)           a
+
+
+/******************************************************************************
+ *
+ * sysFpgaBoot - Load fpga-image into fpga
+ *
+ */
+static int fpgaBoot (void)
+{
+	int i, j, index, len;
+	unsigned char b;
+	int imageSize;
+
+	imageSize = sizeof (fpgadata);
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		index += len + 3;
+	}
+
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < imageSize - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+			&& ((fpgadata[index + 1] & 0xf0) == 0x20))
+			break;
+	}
+
+	/* enable cs1 instead of user0... */
+	*(unsigned long *) 0x50000084 &= ~0x00000002;
+
+#ifdef FPGA_DEBUG
+	printf ("%s\n",
+			((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE");
+#endif
+
+	/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
+	*(unsigned long *) 0x50000084 &= ~0x00000400;
+	udelay (FPGA_PRG_SLEEP * 1000);
+
+	*(unsigned long *) 0x50000084 |= 0x00000400;
+	udelay (FPGA_PRG_SLEEP * 1000);
+
+#ifdef FPGA_DEBUG
+	printf ("%s\n",
+			((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE");
+#endif
+
+	/* cs1: disable burst, disable ready */
+	*(unsigned long *) 0x50000114 &= ~0x00000300;
+
+	/* cs1: set write timing */
+	*(unsigned long *) 0x50000118 |= 0x00010900;
+
+	/* write configuration-data into fpga... */
+	for (i = index; i < imageSize; i++) {
+		b = fpgadata[i];
+		for (j = 0; j < 8; j++) {
+			*(unsigned long *) 0x30000000 =
+				((b & 0x80) == 0x80)
+				? LOAD_LONG (0x03030101)
+				: LOAD_LONG (0x02020000);
+			b <<= 1;
+		}
+	}
+
+#ifdef FPGA_DEBUG
+	printf ("%s\n",
+			((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE");
+#endif
+
+	/* set cs1 to 32 bit data-width, disable burst, enable ready */
+	*(unsigned long *) 0x50000114 |= 0x00000202;
+	*(unsigned long *) 0x50000114 &= ~0x00000100;
+
+	/* cs1: set iop access to little endian */
+	*(unsigned long *) 0x50000114 &= ~0x00000010;
+
+	/* cs1: set read and write timing */
+	*(unsigned long *) 0x50000118 = 0x00010000;
+	*(unsigned long *) 0x5000011c = 0x00010001;
+
+#ifdef FPGA_DEBUG
+	printf ("%s\n",
+			((in32 (0x50000084) & 0x00010000) == 0) ? "NOT DONE" : "DONE");
+#endif
+
+	/* wait for 30 ms... */
+	udelay (30 * 1000);
+	/* check if fpga's DONE signal - correctly booted ? */
+	if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0)
+		return -1;
+
+	return 0;
+}
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * Init pci regs
+	 */
+	*(unsigned long *) 0x50000304 = 0x02900007;	/* enable mem/io/master bits */
+	*(unsigned long *) 0x500001b4 = 0x00000000;	/* disable pci interrupt output enable */
+	*(unsigned long *) 0x50000354 = 0x00c05800;	/* disable emun interrupt output enable */
+	*(unsigned long *) 0x50000344 = 0x00000000;	/* disable pme interrupt output enable */
+	*(unsigned long *) 0x50000310 = 0x00000000;	/* pcibar0 */
+	*(unsigned long *) 0x50000314 = 0x00000000;	/* pcibar1 */
+	*(unsigned long *) 0x50000318 = 0x00000000;	/* pcibar2 */
+
+	return 0;
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+	int fpga;
+	unsigned short val;
+
+	puts ("Board: ");
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	fpga = fpgaBoot ();
+
+	if (!i || strncmp (str, "DASA_SIM", 8)) {
+		puts ("### No HW ID - assuming DASA_SIM");
+	}
+
+	puts (str);
+
+	if (fpga == 0) {
+		val = *(unsigned short *) 0x30000202;
+		printf (" (Id=%d Version=%d Revision=%d)",
+			(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
+
+		puts ("\nFPGA:  ");
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("%s ", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+	} else {
+		puts ("\nFPGA:  Booting failed!");
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	return (16 * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/esd/dasa_sim/dasa_sim.h b/board/esd/dasa_sim/dasa_sim.h
new file mode 100755
index 0000000..5fc313a
--- /dev/null
+++ b/board/esd/dasa_sim/dasa_sim.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/board/esd/dasa_sim/eeprom.c b/board/esd/dasa_sim/eeprom.c
new file mode 100755
index 0000000..1b4c7b3
--- /dev/null
+++ b/board/esd/dasa_sim/eeprom.c
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+
+
+#define EEPROM_CAP              0x50000358
+#define EEPROM_DATA             0x5000035c
+
+
+unsigned int eepromReadLong(int offs)
+{
+  unsigned int value;
+  volatile unsigned short ret;
+  int count;
+
+  *(unsigned short *)EEPROM_CAP = offs;
+
+  count = 0;
+
+  for (;;)
+    {
+      count++;
+      ret = *(unsigned short *)EEPROM_CAP;
+
+      if ((ret & 0x8000) != 0)
+	break;
+    }
+
+  value = *(unsigned long *)EEPROM_DATA;
+
+  return value;
+}
+
+
+unsigned char eepromReadByte(int offs)
+{
+  unsigned int valueLong;
+  unsigned char *ptr;
+
+  valueLong = eepromReadLong(offs & ~3);
+  ptr = (unsigned char *)&valueLong;
+
+  return ptr[offs & 3];
+}
+
+
+void eepromWriteLong(int offs, unsigned int value)
+{
+  volatile unsigned short ret;
+  int count;
+
+  count = 0;
+
+  *(unsigned long *)EEPROM_DATA = value;
+  *(unsigned short *)EEPROM_CAP = 0x8000 + offs;
+
+  for (;;)
+    {
+      count++;
+      ret = *(unsigned short *)EEPROM_CAP;
+
+      if ((ret & 0x8000) == 0)
+	break;
+    }
+}
+
+
+void eepromWriteByte(int offs, unsigned char valueByte)
+{
+  unsigned int valueLong;
+  unsigned char *ptr;
+
+  valueLong = eepromReadLong(offs & ~3);
+  ptr = (unsigned char *)&valueLong;
+
+  ptr[offs & 3] = valueByte;
+
+  eepromWriteLong(offs & ~3, valueLong);
+}
+
+
+void i2c_read (uchar *addr, int alen, uchar *buffer, int len)
+{
+  int i;
+  int len2, ptr;
+
+  /*  printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
+
+  ptr = *(short *)addr;
+
+  /*
+   * Read till lword boundary
+   */
+  len2 = 4 - (*(short *)addr & 0x0003);
+  for (i=0; i<len2; i++)
+    {
+      *buffer++ = eepromReadByte(ptr++);
+    }
+
+  /*
+   * Read all lwords
+   */
+  len2 = (len - len2) >> 2;
+  for (i=0; i<len2; i++)
+    {
+      *(unsigned int *)buffer = eepromReadLong(ptr);
+      buffer += 4;
+      ptr += 4;
+    }
+
+  /*
+   * Read last bytes
+   */
+  len2 = (*(short *)addr + len) & 0x0003;
+  for (i=0; i<len2; i++)
+    {
+      *buffer++ = eepromReadByte(ptr++);
+    }
+}
+
+void i2c_write (uchar *addr, int alen, uchar *buffer, int len)
+{
+  int i;
+  int len2, ptr;
+
+  /*  printf("\naddr=%x alen=%x buffer=%x len=%x", addr[0], addr[1], *(short *)addr, alen, buffer, len); /###* test-only */
+
+  ptr = *(short *)addr;
+
+  /*
+   * Write till lword boundary
+   */
+  len2 = 4 - (*(short *)addr & 0x0003);
+  for (i=0; i<len2; i++)
+    {
+      eepromWriteByte(ptr++, *buffer++);
+    }
+
+  /*
+   * Write all lwords
+   */
+  len2 = (len - len2) >> 2;
+  for (i=0; i<len2; i++)
+    {
+      eepromWriteLong(ptr, *(unsigned int *)buffer);
+      buffer += 4;
+      ptr += 4;
+    }
+
+  /*
+   * Write last bytes
+   */
+  len2 = (*(short *)addr + len) & 0x0003;
+  for (i=0; i<len2; i++)
+    {
+      eepromWriteByte(ptr++, *buffer++);
+    }
+}
diff --git a/board/esd/dasa_sim/flash.c b/board/esd/dasa_sim/flash.c
new file mode 100755
index 0000000..d2ac13f
--- /dev/null
+++ b/board/esd/dasa_sim/flash.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	unsigned long base_b0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	base_b0 = -size_b0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/dasa_sim/fpgadata.c b/board/esd/dasa_sim/fpgadata.c
new file mode 100755
index 0000000..1106d32
--- /dev/null
+++ b/board/esd/dasa_sim/fpgadata.c
@@ -0,0 +1,1952 @@
+  0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+  0x61,0x63,0x6d,0x30,0x30,0x30,0x35,0x64,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+  0x73,0x33,0x30,0x78,0x6c,0x74,0x71,0x31,0x34,0x34,0x00,0x63,0x00,0x0b,0x32,0x30,
+  0x30,0x30,0x2f,0x30,0x37,0x2f,0x31,0x30,0x00,0x64,0x00,0x09,0x31,0x39,0x3a,0x32,
+  0x37,0x3a,0x33,0x38,0x00,0x65,0x00,0x00,0x79,0xaa,0xff,0x20,0x3c,0xd4,0x9f,0x5b,
+  0xff,0x7e,0xde,0xee,0xbd,0xaa,0xfe,0xbf,0x9e,0xff,0xfb,0xfe,0x5f,0xbf,0xed,0xab,
+  0xdb,0xbe,0xe5,0xfb,0xfe,0xfb,0x9f,0xeb,0xfa,0xfe,0x5f,0xb6,0xef,0xfb,0xfe,0xfe,
+  0xaf,0xff,0xff,0xff,0xfb,0xfe,0xef,0xbf,0xef,0xff,0xba,0xff,0xbb,0xfe,0xfb,0xbe,
+  0xff,0xee,0xeb,0xff,0xef,0xbb,0xef,0xff,0xbe,0xff,0xbf,0xff,0xfb,0xfe,0xff,0xbb,
+  0xff,0xe1,0xff,0xff,0xff,0xff,0xff,0xbd,0xff,0xff,0xff,0xff,0xbc,0xff,0xbf,0xff,
+  0xfb,0xfd,0xff,0xdf,0xf7,0xff,0xff,0xbf,0xdf,0xff,0xff,0xff,0xff,0xdf,0xf7,0xfd,
+  0xff,0xff,0xfe,0x3f,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xe3,0xf6,0xff,0xbf,
+  0xef,0xfb,0xfe,0xff,0xef,0xdb,0xfe,0xff,0xbf,0xef,0xe3,0xfe,0xff,0xbf,0xef,0xfb,
+  0xfe,0xfe,0x3f,0xff,0xf7,0xff,0xef,0xbb,0xe7,0xf9,0xbe,0x7f,0xbf,0xec,0xf8,0xfe,
+  0xff,0xbb,0xef,0xfb,0xbe,0x7b,0xe3,0xfb,0xbe,0xff,0xbf,0xec,0xfb,0xfe,0xff,0xbb,
+  0xee,0xfb,0xfe,0xcf,0xbf,0xf6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,
+  0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x17,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0x93,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0x7f,0xff,0xf7,0xff,0xff,0xdf,
+  0xf7,0xf5,0xfd,0xff,0xdf,0xf7,0xff,0xfd,0xff,0xdf,0xf5,0xff,0x7f,0xff,0xdf,0xfd,
+  0xff,0xff,0x7f,0xd7,0xf7,0xfd,0x7f,0xdf,0xd7,0xf7,0xff,0x6f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xbf,0xfd,0xff,0xff,0xff,0xff,0xef,0xff,0xfe,0xdf,0xff,0xcd,0x7f,0xff,0xff,
+  0xff,0xff,0x4f,0xdf,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xdf,0xfd,0xff,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0x7f,0xff,0xff,0xfb,0x3f,0xff,
+  0xff,0xff,0xff,0xfb,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xfc,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x57,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xdf,0xff,0xfe,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,
+  0xec,0xff,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x3f,0xdf,0xf7,0xfd,0x7f,0x7f,0xcf,0xf3,
+  0xfc,0xff,0xdf,0x73,0xdd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xcf,0xf7,0xfd,0xff,
+  0x7f,0xfc,0x9f,0xff,0xef,0xbb,0xfe,0xbf,0xdf,0xef,0xbb,0xfe,0xfb,0xbf,0xef,0xfa,
+  0xee,0xff,0xff,0xfb,0xfe,0xff,0xbf,0xef,0xfa,0xee,0xff,0xbe,0xef,0xbb,0xfe,0xff,
+  0xbf,0xef,0xf7,0xeb,0xff,0xe7,0xf9,0xfe,0x7a,0x9d,0xe7,0xf9,0x7c,0x7e,0x9e,0xe7,
+  0x59,0xf6,0x7e,0x9f,0xe9,0x22,0x7f,0x9b,0xe6,0xb9,0xfe,0x4f,0x9f,0xe6,0xf9,0xfe,
+  0x7b,0x9d,0xe6,0xfe,0xfe,0x7e,0xff,0xbf,0xef,0xfb,0xee,0xff,0xbf,0xe7,0xf9,0xfe,
+  0xff,0x9f,0xef,0xfb,0xfe,0xfd,0xdf,0xfb,0xee,0xfb,0xbf,0xef,0xfb,0xee,0xf7,0xbf,
+  0xef,0xf7,0xfe,0xff,0x7f,0x5f,0x0f,0x9f,0x9b,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,
+  0xfe,0x7f,0x9f,0x66,0xf9,0xfe,0x7f,0xe7,0xf9,0xee,0x77,0x9f,0xe7,0xf9,0xde,0x7d,
+  0x9d,0xe7,0xf9,0xee,0x7f,0x9f,0xed,0xc9,0xff,0xfd,0xff,0x7f,0xdf,0xfd,0xfd,0xff,
+  0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xfd,0xff,0xdf,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,
+  0xf7,0xfd,0xff,0x7f,0xff,0xf7,0xff,0xff,0xfc,0xb7,0xfe,0xff,0xbf,0xef,0xfa,0xfe,
+  0xff,0xbf,0xef,0xfb,0xfc,0xfd,0xbd,0x6f,0xba,0xee,0xb5,0xef,0xfb,0xfe,0xff,0xbf,
+  0xef,0xfb,0xfa,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xff,0x65,0xaf,0xdb,0xd6,0xfd,0xbf,
+  0x7f,0xdb,0xf6,0xfd,0xbf,0x6f,0xfb,0xf6,0xf9,0xae,0xf7,0xd4,0x79,0xbf,0x6f,0xdb,
+  0xb6,0x7d,0xbf,0x6f,0xdb,0xf6,0xfd,0xbd,0x6f,0xdb,0xf7,0xe8,0xef,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xe7,0xfb,0xf7,0x7c,0xfd,0xff,0xf7,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0x9d,0x9e,0xff,0xff,
+  0xff,0xbf,0x7f,0xff,0xfb,0xff,0xff,0x9f,0xfe,0xff,0xff,0xff,0xfb,0xbb,0xff,0xfd,
+  0xff,0xff,0xfb,0xff,0x7f,0xdb,0xe7,0xff,0xbe,0xff,0xff,0xff,0xfb,0xfe,0xe3,0xff,
+  0xff,0xff,0xdf,0xfb,0xef,0xff,0xf7,0xfd,0xff,0xff,0xef,0xff,0xff,0xff,0xcf,0x77,
+  0xdf,0xff,0xff,0xdf,0xd7,0xff,0xff,0xff,0xff,0xdf,0xf7,0xf4,0x7f,0xff,0xff,0xfd,
+  0x7b,0xff,0xff,0xfc,0xff,0xfb,0xff,0xff,0xff,0xef,0xff,0xf7,0xff,0xbf,0xf7,0xff,
+  0x4f,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0x7f,0xff,0xfe,
+  0xfe,0xad,0xff,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,
+  0x79,0xdf,0x5d,0xff,0x7d,0xdf,0xf7,0xfc,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,
+  0xf7,0xff,0xed,0xff,0xbf,0xff,0xff,0x2f,0xd3,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xff,0xff,0xdb,0xff,0xfb,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+  0xff,0xff,0xf7,0xfd,0xbf,0xff,0xff,0xff,0xf7,0xfd,0xbf,0xfe,0xff,0xff,0xef,0xfb,
+  0xff,0xff,0xfe,0xfb,0xdb,0xfb,0xbf,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,
+  0xff,0xff,0xff,0xff,0xf7,0x97,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xef,0xff,0xef,0x7f,0xff,0xcf,0xdb,0xfd,0xff,0xef,0xff,0xfe,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xea,0xff,0xff,0xf7,0xff,0xfd,0xff,0xff,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xfd,0xfb,0x7d,0xf5,0xff,0x7f,0xdf,0xff,0xf7,0xfd,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xfd,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf7,0xdf,0xff,0x7e,0xdf,0x7f,0xfe,0xff,0xdf,0xdf,0xff,0xff,0xff,0xdf,
+  0xff,0xff,0xff,0xff,0xbf,0xef,0xff,0xff,0xff,0xb3,0xff,0xe3,0xf9,0xff,0xff,0xaf,
+  0xff,0xff,0xff,0xfd,0xfd,0xfd,0xfa,0x7f,0xfd,0xab,0xfa,0x7d,0xfe,0x9f,0x7f,0xbf,
+  0xff,0xfe,0xff,0xff,0xfa,0xfe,0xbf,0xff,0xfd,0xff,0xf7,0x7f,0xfe,0xff,0xff,0xff,
+  0xf6,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xdf,0xff,0xf6,0xfe,0xdd,0xff,0xff,0xf7,
+  0xff,0xff,0xff,0x7f,0xbf,0xff,0xee,0xfb,0xff,0xff,0xff,0xfe,0x8f,0xff,0xff,0xff,
+  0xff,0x77,0xef,0xfd,0xff,0xff,0xef,0x3f,0xfe,0xad,0x7f,0xfb,0xff,0xcf,0xf7,0xff,
+  0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xef,0x7b,0xfd,0xff,0xff,0xff,0xd1,0xff,0xff,
+  0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xfb,0xfe,0xff,0xff,0xed,0xfb,0xff,0xef,
+  0xef,0xfb,0xfe,0xff,0xdf,0xff,0xfb,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xf9,0x3f,
+  0xff,0xff,0xff,0xff,0xff,0xcf,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xfe,0xff,0xd7,
+  0x7f,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0x3f,0xff,0xff,0xff,0xff,
+  0x46,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xf8,0x7e,
+  0xbf,0xff,0xff,0xfd,0xfb,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xe2,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf7,0xfd,0xf7,0xf7,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x9f,0xf3,0xfc,0xff,0xfd,0xff,0x7f,0xff,0xff,0xff,0xbf,0xff,0xfd,
+  0xff,0xff,0xbb,0xf1,0xf3,0xbf,0xff,0xff,0xf7,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xbb,0xff,0xff,0xff,0xfe,0x3d,0xcd,0xff,0x7f,0xdf,0xff,0xfd,
+  0xff,0xff,0xef,0xef,0xff,0xfa,0xff,0xf7,0xfb,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xf5,0x7f,0xef,0xff,0xff,0xff,0xfb,0x5f,0xff,0xff,0xfc,
+  0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0x7f,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xfb,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc3,0xff,0xff,0xfc,0x7f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xf7,0xfd,0xff,0x3f,0xf9,0xfc,0xff,0xff,0xcc,0xf5,0xff,0xcf,0xe7,
+  0xff,0xff,0x3f,0xff,0x7f,0xff,0xbf,0xff,0x29,0xaf,0xff,0xff,0xdf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x2f,0xff,0x9f,0xff,0xff,0xff,0xff,0xfc,0xef,
+  0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0x5f,0x3d,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xaf,0xfb,0xca,0xff,0xfb,0x2b,0xd2,0xbf,0xff,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xef,0xa6,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0xfd,0xff,0x5f,0xff,0xe5,0x7f,0x5f,
+  0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0x74,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,0xff,0xff,0xef,0x5f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xbd,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0x5b,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x5f,0xff,0xfd,0xf7,0x7f,0xdf,0xff,
+  0xff,0x7f,0xdf,0xff,0xdd,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x77,0xfd,0x89,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,0xff,0xd2,0xc7,0xbf,0xaf,
+  0xff,0xfe,0xbf,0xaf,0xff,0xd6,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,0xef,0xff,
+  0xe0,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0xff,0xfb,0x5f,0xdf,
+  0xf5,0xff,0xff,0xd7,0xf5,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0x3f,0xfd,
+  0xff,0xf2,0x6f,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0xbf,
+  0x9f,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9f,0xff,
+  0xff,0xff,0xff,0xed,0xff,0x8f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
+  0xff,0xff,0xff,0xff,0xf8,0x1f,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,
+  0xfb,0xbf,0xef,0xfb,0xfe,0xff,0xef,0xfb,0x7e,0xff,0xbf,0xef,0xfb,0xf6,0xff,0xbf,
+  0xee,0xfb,0xfe,0xff,0xb7,0xfe,0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7c,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x57,0xff,0xff,0xff,0xfd,0xff,0x7f,
+  0xff,0xff,0xff,0xfd,0x7f,0xff,0xd7,0xe5,0xff,0xff,0xf7,0xf5,0xff,0xfb,0xff,0xd7,
+  0xff,0xef,0x7f,0xff,0xd7,0xff,0xff,0xff,0x5f,0xfe,0x9b,0xff,0xff,0xff,0xff,0x9f,
+  0xe7,0xff,0xff,0xff,0xff,0xa7,0xff,0xfa,0x7e,0x9f,0xff,0xde,0x7e,0x9d,0xff,0xff,
+  0xfa,0x77,0xff,0xb7,0xff,0xfa,0x7f,0xff,0xff,0xe9,0xff,0xff,0x7f,0xff,0xff,0xff,
+  0xb7,0xfd,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xd7,0xff,0xef,0xdf,0xff,0xff,
+  0xdf,0xff,0x5f,0xff,0xfd,0xff,0xfb,0xff,0xff,0xff,0xfd,0x7f,0xfe,0x8f,0xff,0xff,
+  0x9f,0xe6,0xe9,0xbc,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xc2,0xf9,0xfe,0x7b,0xe7,
+  0xf9,0xfe,0x7f,0x8b,0xe7,0xf8,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x2f,0x9f,0xe1,0xff,
+  0xff,0xff,0xff,0xdf,0xf7,0xaf,0xff,0xff,0xff,0xd3,0xff,0xfd,0x7a,0xff,0xfb,0xff,
+  0x3f,0x5f,0xfb,0xff,0xff,0xff,0xff,0xf7,0xff,0xfd,0x7f,0xff,0xff,0xff,0xff,0xfd,
+  0x3f,0xff,0xff,0xff,0xfb,0xee,0xff,0xff,0xff,0xff,0xfa,0xff,0xff,0xaf,0xff,0xff,
+  0x7f,0xef,0xeb,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xaf,0xff,0xff,0xff,0xff,
+  0xff,0xc7,0xff,0xff,0xff,0xff,0x77,0xdf,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,
+  0xff,0xff,0xfc,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xe4,0xff,0xff,0xff,0xff,0xee,0xfb,0xdf,0xff,0xff,0xff,0xfd,0xff,0xff,
+  0xff,0xff,0xfd,0xff,0x9f,0xff,0xfd,0xff,0x7f,0xff,0xf7,0xed,0xff,0xff,0xdf,0xff,
+  0xff,0xff,0xff,0xfe,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xbf,0xff,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0x2f,0xff,0x8b,0xff,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,0xbf,0xa7,0xe9,
+  0xfa,0xfe,0xbf,0xa7,0xc8,0xfa,0x7f,0xa3,0xe9,0xfa,0xbe,0xbf,0xab,0xea,0xfa,0xbe,
+  0xaf,0xad,0xeb,0xfa,0xfe,0xbf,0xd5,0x7b,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfc,0xff,0xff,0xff,0xff,0x7f,0xfb,0xcd,0xff,0xfc,0xcf,0xfe,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0x47,0xff,0xff,0xfb,0xf7,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x77,0xff,0xbf,0xff,0xfd,0xff,0xef,0xbf,0xba,0xbf,0xff,0xff,0xff,
+  0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb5,0xff,0xdf,0x7f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xaf,0xef,0xfb,0xff,0xf7,0xff,0xf6,0xff,0xef,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0x9f,0xff,0xff,0xfe,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xdf,0xf7,0x5d,0xff,0x7e,0x76,0xff,0xff,0xff,
+  0xff,0x8f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x3f,0xff,0x17,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfa,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,0xfd,
+  0xff,0x7f,0xf7,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xdd,0xff,0xea,0x7f,0xff,
+  0xff,0xef,0xfe,0xff,0xff,0xf7,0xff,0xff,0xfd,0xff,0xfd,0xd7,0xfd,0xff,0xf9,0xfb,
+  0xfe,0xff,0xff,0xff,0xfb,0xff,0xff,0xef,0xfd,0xff,0x7f,0xff,0xbf,0xff,0xfe,0x1f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xbe,0xff,0xff,0xef,0xff,0xbf,0xff,0xbf,
+  0x7b,0xfe,0xfd,0xaf,0xed,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xbb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xdf,0xef,0xff,
+  0x7f,0xe7,0xdf,0xff,0xbd,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xf7,0xff,0xff,0xff,
+  0xff,0xf7,0x7f,0xff,0xff,0xfd,0xff,0xfe,0xff,0xff,0xff,0xff,0xbf,0x7f,0xef,0xff,
+  0xff,0x76,0xfd,0xff,0xc7,0x3f,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xf7,0xc7,0xff,
+  0xff,0xdf,0xfe,0x4f,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
+  0xfe,0x7f,0xfe,0xff,0x9f,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xd5,0xff,0xdf,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xdf,0xfd,
+  0x3f,0x4f,0xff,0xfd,0xff,0xff,0xf7,0xf9,0xf7,0x7f,0xdf,0xdf,0xff,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xff,0x7f,0xf8,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0x9f,0x7f,0x7f,0xff,0xff,0xfe,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xa7,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,
+  0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0x3f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x6e,0x0f,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xc1,0xb3,0xff,0xff,0x3f,0xc7,0xf1,0xfc,0xff,0xfd,0x31,0x5c,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xf2,0x5b,0xff,0x7f,0xff,0xff,0xff,
+  0xff,0xfe,0x7f,0x97,0x3f,0xff,0xf7,0xfd,0xf3,0x7c,0xaf,0xff,0x97,0xe7,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x3b,0xf5,0x9b,0x7f,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xbe,0xf7,0xff,0x2b,0x4a,0xdf,0xbf,0xef,0x3a,0xfe,0xed,0x6a,
+  0x6b,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xfe,0xf4,0x2d,0xfd,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xed,0x73,0x5f,0xdf,0xf7,0xcf,0x5f,0xdf,
+  0xf7,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xf7,0x23,0xff,
+  0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xfe,0xff,0xff,0xfe,0xf5,0xbd,0x7f,
+  0xfb,0xfe,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0x5f,0xd8,
+  0xbf,0xf7,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0x77,0xff,0xff,0x7f,0xdf,0x77,0x9d,
+  0x6f,0xdf,0x77,0xdd,0xef,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0x6b,
+  0xd9,0x37,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xf6,0xb9,0xaf,0xfb,
+  0xc6,0xff,0xaf,0xef,0xfa,0xda,0xb5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xb5,0x7e,0xf3,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xfc,0x57,0xa5,
+  0xfd,0xfb,0x7e,0xb5,0xfd,0xff,0x7f,0xd7,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xdf,0x3f,0xe8,0xff,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
+  0xff,0xff,0xbf,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0x8f,0xff,0xfa,0xff,0xff,0xf9,0xff,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,
+  0xbf,0xef,0xfb,0xfe,0xfd,0xbf,0x6f,0xfe,0xd5,0xb7,0xef,0xbb,0xf6,0xff,0xbf,0xef,
+  0xfb,0xfe,0xff,0xbf,0xef,0xbb,0xff,0xee,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0xbf,0x6f,0xff,0xff,0xff,0xef,0xff,0xf6,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xf7,0xff,0xff,0xff,0xef,0xff,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xcd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xde,0xff,0xe5,0xf9,0x7f,0xdf,0xf7,0xfd,0x7b,0xdf,0xd7,0xf5,
+  0xeb,0x7f,0xff,0xff,0xff,0xfd,0x7f,0xff,0xd7,0xff,0xef,0xf9,0x3f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x79,0xf7,0x7e,0x9f,0xa7,0x6d,0xd3,0x77,0xa7,0xed,0xf2,
+  0x7e,0x9f,0xb7,0xff,0xff,0xff,0xff,0xa7,0x7f,0xfa,0x7f,0xff,0xff,0x33,0xfd,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x77,0xfe,0xd7,0x75,0xfb,0x7f,0xdd,0xf5,0xff,
+  0x7f,0xdf,0xd7,0x7d,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xc4,0xff,
+  0xff,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x6f,0x9f,0xe2,0xf8,0xbe,0x3f,0x8f,0xe6,
+  0xbe,0x3f,0x9f,0xe2,0xf8,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xff,
+  0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x9f,0xe7,0xff,0xfc,0x7f,
+  0x1f,0xfb,0xfc,0xff,0x3f,0xff,0xf3,0xff,0xff,0xff,0xff,0xd7,0xfe,0xfd,0x7f,0xff,
+  0xff,0xe3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xfe,
+  0xff,0xbf,0xff,0x7e,0xdf,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xfa,0xff,0xdf,0xaf,
+  0xff,0xff,0xfd,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,
+  0xff,0xf7,0xfd,0xff,0xff,0xf7,0xfc,0xff,0xff,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfe,0x4f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x7f,0xdf,
+  0xf7,0xff,0xfb,0x7e,0xdf,0xfd,0xfb,0x7f,0xdf,0xff,0xed,0xff,0xff,0xff,0xff,0xff,
+  0xff,0x7f,0xff,0xff,0xff,0xe5,0xdf,0xf4,0xff,0xdf,0xff,0xff,0xdf,0xff,0xff,0xef,
+  0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0x2b,0xc9,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfa,0x3f,0xfe,0xeb,0xfa,0xfe,0xaf,0xaf,0xeb,0xfa,
+  0xfe,0xaf,0x25,0xe8,0xfa,0x3e,0xaf,0x2b,0xfa,0xf6,0xaf,0xab,0xeb,0xfa,0xfe,0xaf,
+  0xaf,0xea,0xfa,0xfe,0xbf,0xaf,0xeb,0xfd,0x87,0xff,0xbf,0xef,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0x3f,0xff,0xf3,0xfd,0xdf,0xb7,0xff,0xff,0xdf,0xff,0x87,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x4f,0x7f,0xff,0xff,0x7f,0xff,
+  0xff,0xf7,0xff,0x6f,0xdf,0xbe,0xff,0xbb,0x56,0xdf,0xb7,0xe9,0xff,0xf3,0xf7,0x37,
+  0xff,0xff,0xdf,0xff,0xfd,0xff,0xff,0xff,0xff,0xfd,0xfa,0x5f,0x7f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0x76,0xfb,0xec,0x6f,0xff,0x7f,0xff,0xf5,0x7f,0xee,0xdf,0xf7,
+  0xfb,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf1,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xfd,0xdf,0xff,0xed,0xff,0xef,0xde,0xf7,0xfe,0xff,0xea,0x7f,0xde,
+  0x8f,0xab,0xff,0x3f,0xff,0x7f,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xfc,0x7f,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9f,0xbf,0xbf,0xdf,0xfd,0xdb,
+  0xff,0xa7,0xfa,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xdf,0xfe,0x47,
+  0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xef,0xef,0xff,0xfe,0xfb,0xfc,0xaf,0xbb,
+  0x8b,0xde,0x1f,0xbb,0xee,0xfd,0x7f,0xff,0xaf,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xe5,0xff,0xff,0xff,0xfe,0x2f,0xff,0xfe,0xff,0xff,0xff,0xfb,0xf6,0xfc,0xbb,0xef,
+  0xcf,0xf7,0xbf,0xff,0xcb,0xf2,0xff,0xff,0xff,0xcf,0xff,0xfd,0xf7,0xff,0xff,0xff,
+  0x7f,0xf8,0xbf,0xff,0xf7,0xff,0xfb,0xff,0xff,0xff,0xfd,0x7f,0x7f,0xd6,0xf5,0xec,
+  0xfe,0x5e,0xcc,0x75,0x7d,0xdb,0xdf,0xbf,0xff,0xff,0xfe,0xff,0xff,0xef,0x7f,0xff,
+  0xfb,0xff,0xff,0xe7,0x7f,0xff,0xff,0xdc,0xff,0xff,0xff,0xf1,0xfe,0xff,0xf7,0xaf,
+  0xf7,0xca,0xfe,0x7f,0xdb,0xf9,0xff,0xbf,0xdf,0xf1,0xfd,0x7f,0xfd,0xcf,0xff,0xff,
+  0xff,0xff,0x7f,0xff,0xe4,0xef,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xdf,0xf3,0xfe,
+  0xfd,0xfe,0xff,0xdf,0xef,0x59,0x7f,0x3b,0xf7,0xe3,0xef,0xbf,0xff,0xff,0xfe,0xff,
+  0xff,0xff,0xfe,0xff,0xff,0xfd,0x9f,0x7f,0xff,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,
+  0xeb,0xff,0xcf,0xb3,0xed,0xeb,0x7f,0xff,0xbf,0xfb,0xff,0xef,0xd7,0xff,0xff,0xfd,
+  0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xb9,0xf5,0xff,0xff,0xfe,0xaf,0xff,0xff,0xff,
+  0xff,0xff,0xf9,0xe3,0xf8,0xfe,0x3e,0x8f,0xda,0xda,0x96,0xad,0xeb,0xfe,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xea,0x7d,0xff,0xef,0xff,0xdf,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdb,0xff,0xff,0xbf,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x41,0xff,0xff,0xfc,0xff,0x3f,
+  0xff,0xff,0xfc,0xfb,0xff,0xcf,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,0xdf,0xf9,0xff,
+  0xef,0xff,0xff,0xff,0xf1,0xff,0xff,0xff,0xf9,0xf3,0xff,0x1d,0xaf,0xff,0xff,0xdf,
+  0xef,0xff,0xf3,0xfc,0xcf,0x7f,0xfd,0xff,0xe7,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,
+  0x3f,0xfd,0xff,0xff,0xff,0xfe,0xff,0xff,0x3b,0xff,0xaf,0xff,0x5f,0x35,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xbf,0xef,0xef,0xfb,0xf5,0x79,0xdf,0x37,0xcd,0xff,0xdf,0x57,
+  0xd5,0xff,0x7f,0xbf,0xff,0xff,0xff,0xff,0xff,0xfb,0xd2,0xff,0xef,0xef,0x86,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xf7,0xfd,0xf3,0x7e,0xff,0x9f,0xe7,0xf9,0xfe,0xff,
+  0xe7,0xf9,0xfe,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x5f,0xff,0xff,0x60,
+  0x3f,0xb7,0xff,0xff,0xaf,0xff,0xfe,0xff,0xbf,0xbf,0xfb,0xa7,0xed,0xf5,0x7f,0x5f,
+  0xef,0xf7,0xfd,0x5f,0x47,0xfe,0xff,0xff,0xeb,0xff,0xfe,0xbf,0xef,0x5f,0xff,0xff,
+  0xfd,0x5b,0xff,0xff,0xff,0xf5,0x7f,0xff,0x77,0xdd,0xa7,0x7d,0xda,0xff,0xbe,0xff,
+  0xff,0xff,0xfe,0xff,0xbb,0xee,0xff,0xdd,0xff,0xfd,0x5f,0xff,0xd5,0xf7,0x6b,0xdf,
+  0xff,0xfd,0x8b,0x7f,0xff,0xff,0xfe,0xbf,0xff,0xfb,0xfe,0xde,0xff,0xaf,0x77,0xed,
+  0xff,0x7d,0xdc,0x7d,0xff,0x7e,0xdf,0xb7,0xfb,0xff,0xff,0xaf,0xff,0xfa,0xff,0xbf,
+  0xaf,0xff,0x7f,0xec,0x7f,0xff,0xff,0xff,0xd7,0xff,0xfd,0xff,0x7f,0xdf,0xf7,0xc7,
+  0xff,0xff,0xff,0x1f,0xeb,0xfc,0xff,0xff,0xff,0xff,0x7f,0xff,0xf5,0xff,0xff,0x5f,
+  0xdf,0xf5,0xff,0xff,0xfe,0x87,0xfb,0x7f,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xe7,
+  0xfb,0x6f,0xfb,0xbe,0xe7,0xbf,0xfb,0xb6,0xef,0xbb,0xee,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xd1,0xff,0x9f,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,
+  0xfe,0xff,0xff,0x6f,0xfa,0xf6,0xfd,0xff,0xfb,0xfe,0xbf,0x8f,0x63,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0x1f,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xb3,
+  0xef,0xfb,0xb6,0xfd,0xbc,0x6f,0x1b,0xb6,0xfd,0xee,0xdb,0xe6,0xfd,0xbf,0xef,0xfb,
+  0xfe,0xdf,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xfe,0xa7,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0x7f,0xef,0xfb,0xf7,0xff,0x7f,0xf3,0xfc,0xfd,0xbf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x78,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf7,0xbd,0xef,0xfb,0xff,0xbb,0xee,0xfb,0xbe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x1f,0xff,0xff,0xff,
+  0xfd,0xff,0xff,0x5f,0xd7,0xf5,0xef,0x7f,0xff,0xff,0xff,0xef,0xfb,0xff,0xbf,0xff,
+  0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x8b,0xff,0xff,
+  0xff,0xff,0x9f,0xff,0xe9,0xf2,0x7e,0x9f,0xa7,0xfe,0x9f,0xbf,0xeb,0xfa,0xff,0xbf,
+  0xef,0xfb,0x7e,0xb6,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0x7f,
+  0xff,0xff,0xff,0xf7,0x7f,0xfb,0xff,0x5f,0xff,0xfd,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xff,0xbf,0xff,0xff,0xde,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xf7,0xfe,
+  0x67,0xff,0xff,0x9f,0xe6,0xf1,0xfe,0x7f,0x8b,0xe7,0xf9,0xbe,0x7f,0x9f,0xe7,0xf9,
+  0xfe,0x7f,0xe7,0xf9,0xfe,0x7f,0x9b,0xe7,0xf9,0xfe,0x7f,0x9f,0xc7,0xf9,0xfe,0x7f,
+  0x9f,0xe9,0xff,0xff,0xff,0xff,0xde,0xbf,0xf5,0xff,0xbf,0x4f,0xf1,0xfe,0xff,0xff,
+  0xe7,0xf9,0xff,0x9f,0xef,0xff,0xff,0xff,0x3f,0xef,0xff,0xff,0xff,0xfa,0xff,0xff,
+  0xff,0xff,0xff,0x3f,0xff,0xff,0xff,0xfb,0xff,0xfe,0xbf,0xf7,0xe9,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe7,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0x57,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfb,0xff,0xff,0xff,0xff,0xef,0xff,0xbf,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xc4,0xff,0xff,0xff,0xff,0xef,0x7f,0xff,0xff,0xdf,0xf7,
+  0xfd,0xff,0xdf,0xf7,0xfd,0xff,0x7f,0xf7,0xfd,0xff,0x7f,0xdf,0x9f,0xf7,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xdc,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf7,0xf5,0xef,0x7b,0xdf,0xf2,0xfc,0xbf,0xcb,0xf2,0xfd,0x2f,0x7f,0xf2,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,
+  0xbf,0xaf,0xea,0xda,0xbc,0x97,0xab,0x6a,0xda,0xb5,0xab,0x69,0xda,0x76,0xaf,0x2f,
+  0xea,0xfa,0xfe,0xb7,0xaf,0xeb,0xfa,0xfe,0xaf,0xf5,0x7f,0xff,0xff,0xcf,0xff,0xff,
+  0xff,0xff,0xcf,0xee,0xfe,0xfa,0x3f,0xbd,0xfd,0x7f,0xff,0xfd,0xf3,0x7f,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x07,0xff,0xff,0xeb,0xf7,
+  0xf7,0xff,0xff,0xab,0xff,0xfc,0xcb,0xe6,0xbd,0xf7,0xef,0xfb,0x7f,0xb5,0xe5,0xfd,
+  0xfd,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0x89,0x7f,0xff,0xff,
+  0xff,0xf7,0xbf,0xcf,0xff,0xdf,0xf7,0xbf,0xe7,0xeb,0xf6,0xfb,0xff,0xb7,0xef,0xdf,
+  0xff,0x7e,0x7b,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x1f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x8f,0xdf,0xfe,0xf6,0xbf,0xaf,0x49,0xba,0x7b,0xa7,
+  0x89,0xda,0xfd,0xb7,0xf7,0xdf,0xff,0xff,0xfb,0xff,0x7f,0xff,0xff,0xff,0xff,0xe7,
+  0xff,0x7f,0xff,0x7f,0xff,0xfb,0xff,0xfb,0xff,0xff,0x7b,0xd7,0xd5,0xfd,0x7a,0x5b,
+  0x95,0xed,0x5d,0x5f,0xef,0xff,0xff,0xfd,0xff,0x7f,0xff,0xf7,0xff,0xff,0xfe,0xff,
+  0xec,0x7f,0xff,0xff,0xff,0xfe,0xff,0xfe,0xff,0xfc,0xfe,0xf3,0xfc,0xdf,0x3b,0xce,
+  0xf3,0xfb,0x3f,0xce,0xf3,0xff,0xef,0xfb,0xfd,0xfd,0x7f,0xff,0xf7,0xff,0xff,0xbf,
+  0xff,0xfd,0x5f,0xff,0xff,0xff,0xff,0xff,0xcf,0x5b,0xfe,0xef,0xfd,0x7f,0x5f,0xd3,
+  0xf6,0xfd,0xb7,0x5b,0xd6,0xfd,0xbf,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xff,0xff,0xff,0xe2,0xff,0xff,0x7f,0xff,0xff,0xff,0xfd,0xff,0xcf,0xff,0xff,0xff,
+  0xdf,0xd6,0xed,0xef,0x46,0xd7,0xb7,0xbf,0xfe,0xff,0xdf,0xfe,0xff,0xff,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0xfe,0x7e,0xff,0xff,0xfd,0xff,0xff,0xde,0xff,0xbf,0xfc,0xff,
+  0xf9,0x7e,0x7f,0xbf,0xee,0xdd,0x3d,0xc7,0xf3,0xfb,0xf6,0x1f,0x3f,0xcf,0xdb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xae,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xfd,0xd7,
+  0xf9,0xf5,0xff,0xef,0xff,0xff,0xf7,0xbb,0xfd,0xfe,0xdf,0xff,0xfd,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,
+  0xbf,0xec,0xff,0x7f,0xcb,0xf2,0xfc,0xbf,0x3e,0xf3,0xfe,0xbe,0xa5,0xe7,0xff,0xff,
+  0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x1f,0xff,0xff,0xff,0xff,0xdf,0xf7,
+  0xfd,0xff,0xff,0xde,0xf6,0xbf,0xad,0xeb,0x6a,0xff,0x2d,0x6b,0x7a,0xff,0xb7,0xff,
+  0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x77,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xaf,0x7f,0xde,0xbf,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,
+  0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0x3f,0xff,0x1f,0xd7,
+  0xff,0xff,0xff,0x3e,0xdf,0xf7,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x7f,0x3f,0xcf,0xff,0x3c,0x7f,0x3f,0xff,0xff,0xff,0xff,0xff,0xf1,0x5a,0xff,0xf7,
+  0xff,0xff,0xfc,0xef,0xef,0xdf,0xff,0xff,0xff,0xff,0xff,0x9f,0xff,0xff,0xff,0x3f,
+  0xff,0xf9,0xff,0xcb,0xff,0xe7,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xf5,0xe3,0xdf,
+  0xff,0xff,0xf2,0xbf,0xef,0xff,0xfb,0xff,0xf1,0xd6,0x75,0xfd,0x67,0x5f,0xd6,0x7d,
+  0x67,0x5d,0x57,0xfe,0xfe,0xe6,0xbf,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf6,
+  0x6f,0xff,0xff,0xff,0xd7,0xf7,0xff,0xff,0x7f,0xff,0x3f,0x7f,0xd3,0xf4,0xfb,0x3f,
+  0x7f,0xff,0xfb,0xbf,0x7f,0xff,0x7c,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf6,0xcf,0xff,0xff,0xff,0xff,0xff,0xbb,0x2f,0xef,0xff,0xff,0xfb,0x7c,0xdf,0xff,
+  0xd5,0xfb,0x7e,0xb7,0xf1,0xff,0xff,0xfb,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xcd,0xbf,0xff,0xff,0xff,0xf7,0xdd,0xf5,0x7d,0xdf,0xf7,0xff,0xef,0xbb,
+  0xfa,0xfb,0xff,0xef,0xfe,0xfd,0xbf,0xaf,0x7d,0xdc,0xf7,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xde,0x1f,0xff,0xfd,0xfd,0x4b,0xfe,0xfe,0xb7,0xbe,0x7f,0x55,0xf1,
+  0x76,0xdd,0xf7,0xfd,0xf1,0xde,0x37,0x7d,0xff,0xff,0xed,0x0b,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfe,0x17,0xff,0xff,0x1f,0xcd,0x7f,0x7f,0xd7,0xf7,0xef,0xfb,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xf7,0xe9,0x7f,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xea,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xff,0xbb,0xfe,0xff,0xbb,0xee,0x7b,0xef,0xbb,0x6e,0xfb,0xbf,0xff,0xff,0xff,0xff,
+  0xff,0xef,0xff,0xff,0xff,0xff,0xff,0x7d,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xfd,0xaf,0xef,0xdf,0xfd,0xbf,0x6b,0xd8,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0xbf,0xff,0xff,0xff,0xff,0xfd,0xc0,0xff,0xfb,0xfe,0xff,0xbf,0xef,
+  0xfb,0x7e,0xff,0xb7,0x6f,0xdb,0xd6,0xf1,0xbb,0xef,0xde,0xed,0xbe,0x6f,0xfb,0xfe,
+  0xdf,0xbf,0x6f,0xfb,0xee,0xff,0xbf,0xef,0xfb,0xf7,0xe5,0x6f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xf7,0xfe,0xff,0xbf,0xef,0xf7,0xff,0x3f,0xcf,0xff,
+  0xff,0xff,0xff,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0xf7,0xcf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xef,0x7b,0xde,0xef,0xbf,0xfb,0xbe,0xef,
+  0xbf,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xe9,0x7f,0xbf,
+  0xff,0xff,0xff,0xff,0xf5,0xfd,0x7f,0x5f,0xff,0xbf,0xff,0xff,0xff,0xff,0xbf,0xfb,
+  0xff,0xff,0xad,0xf9,0x7f,0x5f,0xf7,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xe8,0x37,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0x9f,0xa7,0xe9,0xff,0xaf,0xef,0xfa,0xfe,0xff,0xaf,
+  0xfa,0xfe,0x9f,0xaf,0x9d,0xa7,0xe9,0xfb,0x7e,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x27,0xff,0xff,0xff,0xff,0xff,0xff,0xd7,0xf5,0xe9,0x7f,0xff,0xff,0xff,0xef,0xfb,
+  0xfd,0xff,0xdf,0xff,0xff,0xf7,0xf5,0xfd,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfe,0xff,0xff,0xf9,0xfe,0x7f,0x9f,0xe2,0xf8,0xbe,0x2f,0x9f,0xe7,0xf9,0xfe,
+  0x7f,0x9f,0xe7,0xfe,0x7f,0x9f,0xe6,0xf8,0xbe,0x2f,0x8f,0xe7,0xf9,0xfe,0x7f,0x9f,
+  0xe7,0xf9,0xfe,0x57,0xff,0xe7,0xff,0xff,0xff,0xff,0xff,0xfb,0xfe,0xff,0x9f,0xef,
+  0xfb,0xfe,0xff,0x9f,0xfb,0xfe,0xff,0xbf,0xcf,0xf9,0xff,0xff,0x7f,0x5f,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xeb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,
+  0xfd,0xff,0x7f,0xff,0xff,0xff,0x7f,0xdf,0xf7,0xfb,0xff,0xff,0xff,0xbf,0xeb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,
+  0xff,0xff,0xff,0xff,0xfb,0xff,0xfe,0xff,0xff,0xff,0xff,0x3f,0xff,0xff,0xfd,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xaf,0xff,0xf7,0xff,0xff,0xff,0xff,0xf7,0xfd,
+  0xff,0x7f,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xff,0x7f,0xdf,0xf7,0xe7,0xfd,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x7c,0x8f,0xfb,0xfa,0xf2,0xff,0xbf,0x2f,0xfa,0xfc,0xbf,0xef,0xca,0xff,0xff,0xff,
+  0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xdf,0xef,0xf3,0x2f,0xff,0xeb,0xfa,0xfe,0x9f,
+  0xa7,0xeb,0xfa,0xde,0xbf,0xae,0xca,0xfa,0x6c,0x1f,0xaf,0x38,0xbe,0xbb,0xa3,0xe8,
+  0xfa,0x3e,0x9f,0xaf,0xeb,0x7a,0xbe,0xbf,0xab,0xeb,0xff,0x56,0x7f,0xf3,0xff,0xff,
+  0xfd,0xfb,0xff,0xfb,0xff,0x3e,0x57,0xfb,0xf5,0xdf,0xaf,0x7f,0xff,0xfd,0xff,0xff,
+  0xf7,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x7f,0xff,0xff,
+  0xff,0x7f,0xbf,0xf7,0xed,0xda,0xff,0x7f,0xdb,0xdf,0xff,0x37,0x7f,0xef,0xff,0xff,
+  0xbd,0xff,0xfd,0xf7,0xf8,0xbf,0xeb,0xff,0xff,0xff,0xdf,0xff,0xdd,0xfa,0x9f,0xff,
+  0x5f,0xff,0xff,0xff,0xef,0xfa,0xff,0x35,0xba,0xff,0xff,0xef,0xff,0xfb,0xba,0x7f,
+  0x6e,0xeb,0xbf,0xdb,0xfb,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x8b,
+  0xff,0xff,0xff,0xef,0xfd,0xf7,0x69,0xfb,0xfe,0x5f,0xa7,0xcb,0xfa,0xf6,0xb5,0xa7,
+  0xfa,0xfe,0xbf,0xaf,0x3d,0xdf,0xb6,0x3f,0xfe,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,
+  0xac,0x7f,0xf7,0xff,0xff,0xff,0xff,0xff,0x79,0xee,0xff,0x95,0xad,0x7d,0x5d,0xd5,
+  0xdd,0xf5,0xde,0xf6,0xfd,0xbf,0xff,0xff,0x5f,0xdf,0xf7,0xff,0xf7,0x7f,0xff,0xff,
+  0xff,0xfe,0x8f,0xff,0xfd,0xff,0xff,0xef,0xff,0x8e,0xf3,0x6c,0xff,0xb7,0xee,0x7b,
+  0xee,0xee,0xbb,0x8b,0xbb,0xf6,0xbf,0xce,0xff,0xff,0xfd,0xf7,0xfe,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0x99,0xff,0x7f,0xff,0xff,0xff,0xff,0xf5,0xfd,0x7f,0x4f,0x9e,0xf6,
+  0xfd,0xff,0x6f,0xdb,0xf4,0x3f,0x4f,0xaf,0xfe,0xff,0xe7,0xef,0x7f,0xbf,0xff,0xff,
+  0xff,0xff,0xff,0x7f,0xfe,0x3f,0xff,0xff,0xff,0xfe,0xff,0xdf,0xfe,0xff,0xff,0x7e,
+  0x3f,0x95,0x65,0xd9,0x7e,0x3e,0xfe,0x7f,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,
+  0xff,0x7f,0xff,0xff,0xff,0xff,0x25,0xff,0xff,0xff,0xdf,0xff,0xff,0xcc,0xc3,0x38,
+  0xf7,0x38,0x4f,0x73,0xdc,0xff,0xbd,0x9e,0xf8,0x3e,0xff,0xff,0x73,0xdf,0xff,0x3d,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,
+  0xb7,0xef,0xbb,0x76,0xff,0xbf,0x9f,0xfd,0xfb,0xff,0xef,0xff,0xdf,0xfe,0xaf,0xff,
+  0xe6,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xfc,0xd5,0xff,0xff,0xff,0xff,0xff,0xfb,
+  0x9f,0xa7,0xe8,0xde,0x77,0x8c,0xe5,0x9d,0xfb,0x63,0xf7,0xfd,0x1b,0xbe,0xda,0xff,
+  0xbe,0xef,0xff,0xf7,0x7f,0xff,0xff,0xff,0xff,0xff,0x21,0xff,0xff,0xdf,0xff,0xff,
+  0xfb,0xe9,0xea,0xfe,0xb7,0xaf,0xeb,0x72,0x7e,0xbf,0xaf,0xfe,0xe7,0xbf,0xfd,0xfb,
+  0xff,0xdf,0xe7,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xf0,0x7f,0xff,0xff,0xff,
+  0xbf,0xff,0xfd,0xdf,0x77,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xff,0x5e,0xd7,0xff,
+  0xfc,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xff,
+  0xff,0xff,0x3f,0xd9,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0xff,0xfc,0x7f,
+  0xff,0xcf,0xff,0xfc,0xfb,0x3f,0xcf,0xff,0x3f,0xff,0xfe,0xff,0xff,0xff,0x31,0xaf,
+  0xff,0xff,0xff,0xf6,0xbf,0x3f,0xe7,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xbf,0x9f,
+  0xef,0x7e,0xbd,0xff,0xff,0xdf,0x77,0xcb,0xff,0xbf,0xff,0xff,0xdf,0xff,0xff,0x5a,
+  0x3d,0xff,0xff,0xff,0xff,0xff,0xc7,0x79,0xdf,0xf7,0x9d,0xf3,0x7f,0xde,0x75,0xfd,
+  0x75,0xbb,0x3f,0x1f,0xf3,0xf5,0x2f,0xef,0x7e,0xe6,0xbf,0xff,0xff,0xfb,0xff,0xff,
+  0xef,0xa6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x3f,0xe7,0xf3,0xfe,0x7f,0x3f,0xcf,
+  0xf3,0xef,0xf7,0xcd,0xff,0x7e,0x77,0xb5,0xfd,0xff,0x7e,0x57,0xff,0xff,0xff,0x7f,
+  0xff,0xff,0x6c,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xfb,0x7e,0xdf,0xff,0xf5,
+  0xfd,0x7b,0x5f,0x57,0xbf,0xff,0xf9,0xf7,0x71,0xff,0xbf,0xfb,0xff,0xff,0xff,0xff,
+  0xef,0xff,0xff,0x7f,0x9b,0xff,0xff,0xff,0xff,0xff,0xdf,0xfb,0xff,0xef,0xfb,0xff,
+  0xff,0xbf,0xef,0xdb,0xee,0xdd,0xa7,0x6b,0x38,0xef,0xbd,0xf7,0x7d,0xdf,0xf7,0xff,
+  0xff,0xfd,0xdf,0xff,0xfd,0x89,0xff,0xff,0xff,0xff,0xff,0xff,0x77,0xfd,0xfb,0x7e,
+  0xdf,0xf7,0xcd,0xfb,0x7d,0xdf,0xba,0xfe,0xbf,0xff,0xff,0xea,0xde,0xff,0xef,0xeb,
+  0xdf,0xff,0xff,0xbf,0xff,0xff,0xe2,0x7f,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xfc,0xff,0x8f,0xff,0x7e,0xd7,0xff,0xeb,0xff,0x5f,0xdf,0xf7,
+  0xfd,0x79,0xff,0xff,0xf7,0xff,0xff,0xf7,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xee,
+  0x7b,0xfe,0xff,0xbf,0xef,0xfb,0xbe,0xe7,0xbf,0xff,0xaf,0xff,0xdf,0xf7,0xff,0xff,
+  0xff,0xf9,0xff,0xbf,0xff,0xff,0xff,0xff,0xfe,0xed,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xe7,0xdf,0xf6,0xfd,0xff,0x7f,0xda,0xf6,0xff,0xff,0xfe,0xfe,0xff,0xff,0xe7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x1f,0xff,0xbf,0xef,0xfb,
+  0xfe,0xdd,0xbf,0xef,0xdb,0xee,0xfd,0xbd,0x6f,0x1b,0xbe,0xfd,0xef,0xfb,0xe6,0x5f,
+  0x9f,0xef,0xfb,0xfe,0xdf,0xbf,0xef,0xfb,0xfe,0xdf,0xbf,0xfe,0x66,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x7f,0xff,0xf7,0xff,0xfd,0xff,0xef,0xfb,0xfe,0xff,0x3f,0xfb,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x72,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xf7,0xbd,0xef,0xbb,0xdf,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x97,
+  0xff,0xff,0xff,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xf7,0xf5,0xff,0x9f,0xef,0xd7,0xfd,0xed,0x7f,0x5f,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xcb,0xff,0xff,0xff,0xfe,0x9f,0xff,0x7e,0xff,0xaf,0xeb,0xfa,0xfe,0xbf,0xaf,0xeb,
+  0xfb,0xfa,0x7e,0x9f,0xff,0xff,0xfa,0x7f,0x9f,0x27,0xe9,0xdf,0xff,0xff,0xff,0xff,
+  0xff,0xfc,0x7f,0xff,0xff,0xff,0xd7,0xff,0xdf,0xfb,0xff,0xff,0xff,0xff,0xff,0xfc,
+  0xff,0x7f,0xef,0xde,0xb7,0xbf,0xff,0x7a,0x5f,0xb7,0xff,0xfd,0x7f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x6f,0xff,0xff,0x9f,0xe2,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,
+  0x9f,0xe7,0xf9,0xfe,0x6f,0xe7,0xf9,0xde,0x6f,0x0b,0xe6,0xe9,0xfe,0x2f,0x9f,0xe7,
+  0xf9,0xfe,0x7f,0x9f,0xd5,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,
+  0xfe,0x7f,0x9f,0xef,0xfb,0xff,0x1f,0xcf,0xd9,0xf5,0xfb,0xbf,0xdf,0xd3,0xfe,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xef,0xfd,0xfe,0xfe,0xbf,0xf7,0xfb,0xaa,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x17,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0x7f,0x7f,0xff,0xbf,0xff,0x7f,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,
+  0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xf9,0xff,0xf7,0xdf,
+  0xe6,0xfd,0xff,0x7f,0xdf,0xff,0xff,0xff,0xff,0xfc,0xdf,0xff,0xff,0xff,0xff,0xbf,
+  0xef,0xab,0xeb,0xfa,0xfe,0xbf,0xaf,0xe9,0xfa,0xfe,0xaf,0xdb,0xd7,0xf5,0xff,0x2f,
+  0xff,0xfa,0xff,0xff,0xff,0xff,0xff,0xfc,0x9f,0xff,0xff,0xba,0xff,0xfe,0xbf,0xaf,
+  0xe9,0xfa,0x7e,0x0f,0xa3,0xe8,0xfa,0xfe,0xb7,0xab,0xeb,0xfa,0xf7,0xaf,0x63,0xfa,
+  0x76,0xaf,0xab,0xea,0xfa,0xbe,0xbf,0xab,0xea,0xfa,0xfe,0xbf,0x5f,0x7f,0xef,0xed,
+  0xff,0xf3,0xef,0x7f,0xff,0xfb,0xfd,0xff,0xdf,0xef,0xf5,0xff,0x6f,0x7f,0x3f,0xff,
+  0xba,0xff,0x33,0xcf,0xf3,0x7d,0xbf,0xdc,0xff,0xff,0xfb,0xff,0xff,0xde,0xa7,0xff,
+  0xff,0xdf,0xb2,0xff,0xfa,0xff,0xff,0xf7,0x7d,0xff,0x7d,0xbf,0x77,0xff,0xf7,0x7e,
+  0xdf,0xf4,0xdf,0x5e,0xcf,0xff,0xfd,0xff,0xff,0x7f,0x7f,0xfd,0xff,0xff,0x7f,0x85,
+  0x5f,0xff,0xff,0xff,0xff,0xfe,0xff,0xbb,0xff,0xff,0xfe,0xef,0xfb,0xfe,0xff,0xbb,
+  0xf3,0xaf,0xff,0xfb,0x6b,0xfa,0xfe,0x5f,0xb7,0xef,0xdb,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0x3f,0xff,0xfd,0xf7,0xf8,0xd7,0x76,0x9d,0xa6,0x4b,0xda,0x76,0x9d,0xa7,0x69,
+  0xda,0xdb,0xbf,0xad,0xfa,0xfe,0xb7,0xa7,0x7d,0xff,0x7e,0x3f,0xff,0x3f,0xff,0xff,
+  0xff,0xff,0xc7,0xff,0x7f,0xff,0xf5,0xdf,0xff,0xa7,0xd9,0xfe,0x7e,0x9f,0x67,0xd9,
+  0xf6,0x7f,0x9f,0xde,0xbf,0x7f,0xeb,0x7b,0x7e,0x57,0xfd,0xff,0x5f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfa,0xff,0xff,0xff,0xff,0xfe,0xff,0xfe,0xef,0xab,0xef,0xfa,0xfe,
+  0x3f,0xbf,0xef,0xfe,0xfb,0xb9,0xe9,0xa8,0xfa,0xfe,0xbf,0xee,0xfb,0xfe,0xff,0xfb,
+  0xef,0xff,0x7f,0xff,0xed,0x9f,0xef,0xfd,0xfb,0xde,0x7d,0x3f,0x6f,0xdb,0xe6,0xfd,
+  0xbf,0x7f,0xdb,0xd6,0xf9,0x3d,0x6b,0xfb,0xfe,0xff,0xbb,0xee,0xfa,0xfe,0xbf,0xb7,
+  0xfb,0xf5,0xff,0xff,0xff,0xff,0xbb,0xbf,0xff,0xff,0xfb,0xfb,0xfd,0xf9,0x9e,0x77,
+  0x9f,0xe3,0xf9,0xde,0x57,0x9d,0xfe,0xef,0xef,0xf6,0xff,0x5f,0xdf,0x9f,0xff,0x7f,
+  0x7f,0xff,0xf7,0xdf,0xff,0xff,0xff,0xf3,0x7f,0xff,0xff,0x7c,0xcd,0xff,0xfd,0xf7,
+  0xf8,0xd7,0xf1,0x9f,0xe7,0x1f,0xc7,0xfe,0xf5,0x3f,0xcf,0x71,0xdc,0x36,0x3d,0x8f,
+  0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x8f,0xff,0xff,0xef,0xfa,0xff,0xff,
+  0xbd,0xff,0xff,0xd7,0xbf,0xff,0xfd,0xfe,0xfb,0xff,0xbb,0x5e,0xff,0xdf,0xf7,0xfb,
+  0xfe,0xff,0xf7,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xc1,0xff,0xff,0xff,0xff,0xff,
+  0xf7,0xfd,0x7f,0x36,0xdd,0xf7,0x3c,0xcf,0x7b,0xda,0xff,0xfa,0x7e,0x9c,0xb3,0x3d,
+  0xbe,0x7d,0x9f,0xf7,0xed,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x9f,0xff,0xff,0xff,
+  0xfe,0x7a,0x5e,0xbf,0x2f,0xeb,0xaa,0xdc,0xbf,0xae,0xab,0xff,0xff,0xaf,0xab,0x7a,
+  0xdc,0xbf,0xad,0xeb,0x7a,0xfe,0xb7,0xff,0xff,0xff,0xff,0xff,0xfa,0x67,0xdf,0xff,
+  0xff,0xff,0xff,0x7f,0xdf,0xf7,0xfd,0xf7,0x77,0xdf,0xf7,0xfd,0xff,0xff,0xf7,0xf9,
+  0xdf,0x7f,0xdf,0x77,0xfd,0xff,0x7f,0xdf,0xef,0xbf,0xff,0xff,0xff,0xff,0xe8,0xbf,
+  0xff,0xff,0xff,0xfe,0x7f,0xff,0xdf,0xfc,0xfd,0xff,0xd7,0xff,0xff,0xff,0xed,0x9f,
+  0xf7,0xff,0xff,0xff,0xdf,0xff,0xfd,0xff,0x9f,0xff,0xff,0xff,0xfd,0xff,0xff,0xf1,
+  0xca,0xff,0xff,0xff,0xff,0xab,0xff,0xff,0xff,0x9f,0xff,0xf9,0xfe,0x7f,0xff,0xfd,
+  0xe3,0xff,0xff,0xcf,0xf3,0xff,0xff,0xff,0xff,0xfa,0xff,0xce,0xff,0xff,0xff,0xff,
+  0xf5,0xab,0xdf,0xff,0xff,0xff,0xfc,0xd6,0x75,0x9d,0x7f,0x59,0xd7,0x35,0xfd,0xe7,
+  0x79,0xaf,0x5d,0xf5,0x7c,0xd7,0x55,0xd5,0xff,0x7d,0x57,0xf5,0xfe,0xff,0xff,0xff,
+  0xff,0xfe,0xf0,0x6f,0xff,0xff,0xff,0xff,0x9f,0x7f,0xd3,0xfe,0xfb,0x3f,0xe7,0xf9,
+  0xfc,0xff,0x35,0xe7,0xfe,0x7f,0xbe,0xe7,0xbb,0xfe,0xff,0x3f,0x6f,0xbf,0x7f,0xff,
+  0xff,0xff,0xff,0xf7,0x47,0xff,0xff,0xff,0xff,0xff,0xf5,0x7f,0xde,0xe7,0xd5,0xe3,
+  0x7a,0xdf,0xff,0xfc,0xbf,0x7f,0xff,0xf9,0xff,0x7c,0x9f,0xef,0xcd,0xf6,0x7f,0xfb,
+  0xf2,0xff,0xff,0xff,0xff,0xd1,0xbf,0xff,0xff,0xff,0xf7,0xfe,0xff,0xe3,0xf4,0xfa,
+  0xbe,0xff,0xff,0xfe,0xfd,0x1d,0x4f,0xfa,0xfd,0x3f,0x4f,0xab,0xfa,0xfb,0xbe,0x4f,
+  0xe9,0xdc,0x57,0xff,0xff,0xff,0xd8,0x9f,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xdf,
+  0x77,0xfd,0xf7,0x7d,0xdf,0xb7,0xd2,0xf7,0xdf,0xf7,0x7d,0xff,0x7f,0xdf,0xf7,0xc5,
+  0xf7,0x77,0xef,0xab,0xff,0xf5,0xfd,0x7e,0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xe7,0xff,0xfe,0x7f,0x1f,0xff,0xf3,0x5e,0x7f,0xff,0xfa,0xff,0xff,0xff,0xeb,
+  0xfb,0xfe,0x7f,0xf7,0xfd,0x7f,0xff,0xff,0xff,0xe6,0x5f,0xff,0xff,0xff,0xff,0xfb,
+  0x9e,0xe7,0xbe,0xee,0xdb,0xee,0xff,0xbb,0xee,0x7f,0xef,0xbf,0xee,0xfb,0xbe,0xef,
+  0xb9,0xef,0xbb,0xee,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0x1b,0xff,0xff,0xff,0xff,
+  0xff,0xf9,0xf6,0x7d,0xff,0xef,0xff,0xf7,0xfd,0xaf,0x6f,0xf9,0xfd,0xff,0x6b,0xd8,
+  0xfe,0x3d,0xff,0xef,0xff,0xf6,0xff,0xff,0xff,0xff,0xff,0xff,0xb1,0xff,0xfb,0xfe,
+  0xff,0xbf,0x6f,0xdb,0xfe,0xfd,0xbb,0x6f,0xdb,0xd6,0xf1,0xbb,0x6f,0xfe,0xfd,0xbe,
+  0x6f,0xdb,0xf6,0xfd,0xbe,0x6f,0xdb,0xee,0xff,0xbf,0xef,0xfb,0xff,0xe5,0x6f,0xff,
+  0xff,0xff,0xff,0xdf,0xf7,0xff,0xff,0x7f,0x6f,0xdf,0xfe,0xff,0xbf,0x6f,0xff,0xff,
+  0x3f,0xcf,0xdb,0xfd,0xfd,0xff,0xdf,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x8f,
+  0xff,0xff,0xff,0xff,0xff,0xbf,0xef,0xfb,0xfe,0xf7,0xbf,0xef,0x7b,0xde,0xfb,0xff,
+  0xfb,0xbe,0xef,0xbb,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xff,0xf5,0xff,0xff,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
+  0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,
+  0xff,0xeb,0xbf,0xfc,0x9f,0xff,0xe9,0xff,0xbf,0xeb,0xfa,0x7e,0xff,0xbf,0xeb,0xfa,
+  0x7e,0xba,0x7f,0xfa,0xfe,0x9f,0xaf,0xed,0xfa,0xfe,0xff,0xbf,0xeb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xb3,0xff,0xd7,0xff,0xfd,0x7f,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf7,0xdd,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xf8,0xff,0xfa,0xf9,0xfe,0x2f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,
+  0xe7,0xf9,0xfe,0x7f,0x8b,0xc7,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xc7,0xf9,
+  0xfe,0x7f,0x1f,0xe7,0xf9,0xff,0x9f,0xff,0xff,0xfb,0xfe,0xff,0xff,0xef,0xfb,0xfe,
+  0xff,0xbf,0xff,0xff,0xfe,0x7d,0x7a,0xff,0xfe,0x7f,0xbf,0xef,0xf9,0xfe,0x7f,0x9e,
+  0xef,0xff,0xff,0xeb,0xff,0xe7,0xff,0x83,0xff,0xff,0xff,0x7f,0xdf,0xff,0xfd,0xff,
+  0xff,0xdf,0xf7,0xff,0xff,0xff,0xff,0xaf,0xff,0xff,0xff,0xf7,0xfd,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x7f,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xef,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xfd,0xff,0x7f,
+  0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xde,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,
+  0xff,0x7f,0xdf,0xf7,0xfd,0xff,0xff,0xff,0xff,0xf7,0xff,0xd1,0xff,0xff,0xff,0xef,
+  0xff,0xd3,0xf4,0xfd,0x1f,0x4f,0xd3,0xf4,0xfd,0x3f,0x4f,0xd8,0xfd,0x3f,0x4f,0xd1,
+  0xf4,0xfd,0x3f,0x47,0x53,0xf4,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0xaf,0xff,0xe3,
+  0xfa,0xfe,0xbb,0xa4,0xe9,0xba,0xce,0xab,0xae,0xeb,0x3a,0xce,0xb3,0x2b,0x7a,0xfe,
+  0xbf,0xa3,0xeb,0xfa,0x3e,0x9f,0x8f,0xeb,0x7a,0xbe,0xaf,0xad,0xeb,0x7b,0x07,0xff,
+  0xff,0xff,0x7f,0xfe,0xc7,0xf2,0xfd,0x5f,0xff,0xfd,0xff,0x7f,0xdf,0xf7,0x7f,0xfb,
+  0xee,0xef,0xbf,0xef,0x7b,0xae,0xfb,0x9a,0xe1,0xff,0xff,0xff,0xff,0xff,0xff,0xf2,
+  0x7f,0xff,0xff,0xff,0x79,0xf7,0xfa,0x7d,0xff,0xff,0xdf,0x9f,0xeb,0xfb,0xfe,0xff,
+  0xf7,0xfb,0x7d,0xbf,0xbf,0xdb,0xff,0x7e,0xbf,0xda,0xff,0xff,0xff,0xdf,0xff,0xff,
+  0xfa,0x5f,0xff,0xff,0xff,0xfe,0xfb,0x7f,0xf5,0xb7,0x3f,0xef,0xf7,0xff,0xff,0xaf,
+  0x7f,0xbb,0x7e,0xff,0xff,0xff,0xfe,0xfe,0xff,0xfb,0x7f,0xff,0xff,0xbf,0xff,0xff,
+  0xff,0xff,0xfb,0xff,0xeb,0xff,0xee,0x3f,0x8d,0xe3,0xf8,0xfc,0x37,0x0f,0x63,0xc8,
+  0xfe,0x1d,0xa7,0xf8,0x7c,0x3f,0x83,0x23,0xf8,0xdc,0x1f,0x87,0xe3,0xff,0xef,0xff,
+  0xff,0xff,0xfe,0x70,0x7f,0xf6,0x7f,0xff,0xdf,0xf7,0xf5,0xff,0x77,0x9f,0x37,0xf9,
+  0xff,0x7f,0xdf,0xfe,0xed,0x7f,0xdf,0x77,0xdd,0xef,0x7f,0xdf,0x97,0xf5,0xf7,0xff,
+  0xff,0xff,0xff,0xdf,0xf0,0x0f,0xff,0xfe,0xff,0xef,0xef,0xd7,0xf7,0xfb,0xff,0xff,
+  0x1f,0xee,0xf3,0xbe,0xbe,0xf2,0xbb,0xbf,0xf9,0xbf,0xfe,0xbb,0xfc,0x5f,0xff,0xff,
+  0xff,0xbf,0xff,0xff,0xff,0x7f,0x09,0xff,0x7f,0xff,0xdf,0xff,0xdf,0xff,0xff,0xbf,
+  0x7f,0xd7,0xe5,0xfd,0xbf,0x3b,0xdf,0xf4,0x3b,0x5d,0xcf,0xfe,0xfc,0x7f,0x7f,0x3b,
+  0xff,0xff,0x9f,0xff,0xfb,0xff,0xff,0xf0,0xbf,0xff,0xff,0xff,0xff,0xbe,0xdf,0xf5,
+  0x73,0xdb,0x5f,0xbf,0xdd,0xbd,0xef,0x7b,0xee,0x7f,0xff,0x7b,0xff,0xff,0xfb,0xef,
+  0xff,0xff,0xff,0xfd,0x7e,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xff,0xff,0xff,0x1f,
+  0xcf,0xf1,0xff,0xff,0xff,0xef,0xfb,0xf3,0xfe,0xfe,0xde,0xfc,0xfa,0xbf,0x3f,0x6f,
+  0xff,0xbf,0x1f,0xd7,0xff,0xfc,0x7f,0xff,0xff,0xff,0xd6,0xef,0xff,0xff,0xf7,0xff,
+  0xf7,0xfb,0x7f,0xd7,0xfe,0xff,0xfd,0xef,0xdf,0xff,0xff,0xf3,0xff,0xb7,0xfb,0xff,
+  0xf7,0xff,0xff,0xfb,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xfd,0xdf,0xff,0xff,0xff,
+  0xff,0xaf,0x7b,0xfc,0xff,0xbf,0xed,0x72,0xff,0xf3,0x7d,0xdf,0xff,0xf7,0xed,0xf9,
+  0x7e,0xdd,0x7b,0xfd,0x7f,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x11,0x7f,0xff,
+  0xff,0xff,0xef,0xec,0xfd,0x7f,0xfa,0xbf,0xef,0xf9,0xfe,0xff,0xff,0xed,0xf0,0xfb,
+  0xbf,0xed,0xf9,0xff,0xaf,0x6e,0xfb,0xfe,0xff,0xff,0xff,0xff,0xff,0xdf,0xf7,0x7f,
+  0xff,0xff,0xff,0xfc,0xf5,0xff,0xff,0xff,0xff,0xfd,0x7e,0xff,0x5f,0xdf,0xfb,0xef,
+  0xf7,0xcf,0xfb,0xf8,0xef,0xff,0xfd,0x7f,0x9f,0xf7,0xff,0xff,0xff,0xff,0xff,0xf6,
+  0xc3,0xff,0xbf,0xfc,0xff,0xf5,0xcc,0xf7,0x3c,0xff,0xfe,0xcf,0xf2,0x6c,0xcf,0xdf,
+  0xcf,0xec,0x7f,0x3f,0xff,0xbf,0xff,0xfb,0x75,0xcf,0xb3,0xff,0xff,0xe7,0xff,0xff,
+  0xff,0x35,0xaf,0xf7,0xbf,0xdf,0xff,0xff,0xa3,0xe5,0xff,0x3f,0xdd,0xfe,0xa9,0xef,
+  0x7e,0x7f,0xfc,0x5a,0x3b,0xdf,0xf7,0xff,0xff,0xfe,0xbb,0xf6,0xff,0xff,0xfe,0xbf,
+  0xff,0xff,0x58,0xbd,0xfe,0xff,0xff,0x2b,0xff,0x9f,0x9d,0x73,0x2b,0xfa,0xe7,0xbf,
+  0xab,0x5d,0xcb,0x9f,0xac,0x6a,0x9f,0x7e,0x9f,0xf7,0xef,0x7f,0xfe,0xff,0xff,0xfd,
+  0xff,0xff,0xff,0xef,0x86,0xff,0xdf,0xff,0xed,0x7f,0xff,0xcd,0x93,0x65,0x79,0x7e,
+  0xdf,0x37,0xed,0xd3,0x7f,0xf5,0xe5,0x7f,0x76,0xdd,0xff,0x7f,0xff,0xff,0xdf,0xff,
+  0xff,0xdf,0xff,0xff,0xff,0x78,0xff,0xfb,0xff,0xfe,0xff,0xeb,0xfe,0x7d,0xdd,0x2f,
+  0xcb,0xc3,0xfe,0xbe,0x7c,0xdb,0xff,0xff,0x2f,0xff,0x22,0xdf,0xf7,0xff,0xeb,0xfb,
+  0xff,0xff,0xfd,0xff,0xff,0xff,0xfc,0xdb,0xff,0x77,0xff,0xff,0x7d,0x5f,0x77,0x1d,
+  0xf7,0x51,0x5e,0x77,0x95,0x87,0x7d,0xde,0xdd,0x87,0x79,0xdf,0x7b,0xdd,0xff,0x79,
+  0x5f,0x77,0xff,0xff,0xff,0xff,0xff,0xfd,0x99,0xff,0xef,0xff,0xfe,0xbf,0xad,0xfb,
+  0xca,0xfe,0xbf,0xaf,0xab,0x42,0xfe,0xad,0x2f,0x3f,0xfe,0xbe,0xaf,0x4b,0xfe,0xdf,
+  0xfe,0xaf,0xef,0x9f,0xf7,0xed,0xff,0xff,0xff,0xe3,0x7f,0xfd,0xff,0xff,0xd7,0xf5,
+  0xfd,0xb8,0x4f,0xd7,0xf5,0xfd,0xfa,0x5f,0xd6,0xf7,0xc6,0x7f,0xd7,0xf5,0x6d,0xff,
+  0x76,0xff,0x35,0xfd,0xf3,0xfe,0x7f,0x9f,0xff,0xff,0xff,0x4f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf6,0xfd,0xbf,0xed,0xff,0xfe,0xdf,0xbf,0xcd,0xfb,0x7f,0xbf,0xed,0xd0,
+  0xfc,0xfd,0x27,0xed,0xff,0xff,0xff,0xef,0x5b,0xff,0xff,0xff,0xf1,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xe3,0xfe,0xfe,0xff,0x9f,0xe7,0xfa,0xfe,0xff,0xfb,0xfa,0xfe,
+  0xf9,0xff,0xfb,0x9b,0xfe,0x7f,0xff,0xff,0xff,0xe7,0xff,0xff,0xff,0xf9,0x1f,0xff,
+  0xbf,0xef,0xfb,0xfe,0xfd,0x9f,0x67,0xdb,0x36,0xdf,0xbf,0xee,0xdb,0xbe,0xfd,0xee,
+  0xdb,0xee,0x75,0xbf,0x67,0xbb,0xfe,0xff,0xbf,0xef,0xf8,0xfe,0xff,0xbf,0xfe,0x56,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0xbf,0x6f,0xdb,0xfc,0xff,0xff,0xef,0xf3,0xfe,0xfd,
+  0xbf,0xdb,0xff,0xfb,0xbe,0xdf,0xbf,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,
+  0x76,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xf7,0xfd,0xfe,0xff,0xff,0xf7,0xfe,0xff,
+  0xbf,0xbf,0xfb,0xff,0xfe,0xdf,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0x17,0xfe,0x5f,0xff,0xff,0xff,0x7f,0x47,0xd1,0xf5,0xfd,0x7f,0xdf,0xd7,
+  0xf5,0xef,0x7f,0xd7,0xb5,0xfb,0x1b,0x5e,0xf9,0xff,0xff,0xff,0xfe,0xff,0xfe,0x7f,
+  0xff,0xfe,0xff,0x8b,0xff,0xe9,0xff,0xff,0xff,0xe7,0xeb,0xfa,0xfe,0x9f,0xa7,0xe9,
+  0xfa,0x7e,0x8f,0xa7,0xfb,0x76,0x9f,0xe3,0xea,0xd7,0x3f,0xdf,0xff,0xff,0xff,0xff,
+  0xef,0xff,0xff,0xff,0xb0,0x7b,0xfd,0x7f,0xfd,0xff,0xfd,0xfb,0x37,0x4f,0xf7,0xe5,
+  0xef,0x7f,0x5f,0xf7,0xbd,0xef,0x7f,0xf7,0x3e,0xff,0x77,0x5c,0xf7,0xbf,0xdf,0xf7,
+  0xfe,0xfb,0xbf,0xff,0xff,0xfd,0x2f,0xff,0xaf,0x9f,0xe7,0xf9,0xbe,0x3f,0x8b,0xc2,
+  0xf8,0xbe,0x3f,0x8b,0xa7,0xf9,0xbe,0x6f,0xe2,0xf9,0xfe,0x2f,0x89,0xe6,0xf9,0xfe,
+  0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xdd,0xff,0xff,0xff,0xff,0xff,0xf3,0xf5,0xff,
+  0x7a,0x5f,0xf7,0xfc,0x7f,0x37,0xdf,0xf1,0xfd,0x1f,0x4f,0xf1,0xf5,0xff,0x1f,0xef,
+  0xff,0xfe,0x7f,0x9f,0xe7,0xff,0xff,0xff,0xeb,0x3f,0xdf,0xff,0xff,0xff,0xfe,0x7e,
+  0xbf,0xbf,0xeb,0xfa,0xff,0xbf,0xa7,0xbf,0xfb,0xff,0xbf,0xe9,0xfe,0xfe,0xbf,0xbf,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x13,0xff,0xff,0xff,0xff,0xff,
+  0xdf,0xff,0xff,0xff,0x7f,0xdf,0xff,0xfd,0xff,0x7f,0xff,0xe7,0xff,0x7f,0xff,0xff,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe6,0xdf,0xff,0xff,0xff,
+  0xff,0xf9,0xff,0x7f,0xff,0xbf,0xef,0xff,0x7e,0xdb,0xfd,0xfd,0xfe,0xdf,0xb7,0xff,
+  0x7f,0xdf,0xb7,0xf7,0xfd,0xff,0x7f,0xdf,0xfd,0xfd,0xff,0xff,0xfd,0x9f,0xf7,0x7f,
+  0xff,0xff,0xff,0xff,0xf7,0xdf,0xf7,0xfd,0xbf,0xee,0xdf,0xf6,0xfd,0xad,0xff,0xff,
+  0xfd,0xaf,0x27,0xde,0xf2,0xff,0xff,0xab,0xff,0xff,0xff,0xff,0xff,0xff,0x03,0xff,
+  0xf6,0xbf,0xa7,0xe9,0xfa,0xde,0xbb,0xaf,0xea,0xb8,0xfc,0x33,0xaf,0xe9,0xfa,0xf7,
+  0xaf,0xe3,0xba,0xf6,0xbb,0xa7,0x69,0xfa,0x7e,0xbf,0xaf,0xeb,0xfa,0xfe,0xbb,0xf3,
+  0x7f,0xdf,0xff,0xcd,0xff,0xff,0xdf,0x17,0xcd,0xae,0xf6,0xbd,0xef,0xf5,0xc3,0x73,
+  0xef,0xff,0xfe,0xe4,0x7f,0x3f,0xc7,0xff,0x6f,0xdf,0xfd,0xff,0xb3,0xff,0xff,0xff,
+  0xee,0xa7,0xff,0xff,0xdf,0xef,0xff,0xef,0xbe,0x93,0xdf,0xfd,0x7f,0x7b,0xff,0xff,
+  0xe7,0xef,0xff,0x5f,0xf7,0xfd,0xff,0xdf,0xff,0xe7,0xfb,0xff,0x7f,0xff,0xff,0xfd,
+  0xf7,0xff,0x95,0xef,0xff,0xfc,0xff,0xff,0xff,0xed,0xaf,0xcd,0xf2,0xff,0xbf,0x3f,
+  0xfe,0x3f,0xff,0xe7,0xbb,0xfb,0xcf,0xb3,0xe8,0xf6,0xff,0xfd,0x7f,0xff,0xff,0x3f,
+  0xff,0xff,0xff,0xe9,0xbf,0xfa,0xbf,0xff,0xff,0xff,0x7e,0x9a,0xb7,0xc9,0xf9,0xfd,
+  0x9f,0x6f,0x79,0xce,0xdf,0xff,0xaa,0xff,0xfe,0x9f,0x8f,0xf9,0xef,0x7b,0xdf,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xf7,0xfd,0xd5,0xff,0xff,0xff,0xff,0xe7,0xfd,0xef,0xbb,
+  0xfd,0xdf,0xbb,0xff,0xff,0xfd,0xff,0xad,0x7f,0xfc,0x57,0xbf,0xf6,0xff,0xff,0xfd,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xe8,0xff,0xfe,0xfd,0xff,0xf7,0xff,0xbf,0xff,0xff,
+  0xae,0xff,0xff,0xef,0x3d,0xab,0xee,0xdb,0xfb,0xff,0x73,0xfc,0xfe,0xff,0xcf,0xff,
+  0xf7,0xff,0xfb,0xff,0xfd,0xff,0xff,0xff,0x1f,0xff,0x37,0xfb,0xef,0xf7,0xbf,0xef,
+  0xfb,0xf4,0xed,0x7f,0xff,0x7b,0xf3,0xdf,0xff,0x59,0xff,0xff,0xfa,0xeb,0xdb,0xf5,
+  0xff,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9a,0x7f,0xef,0xff,0xff,0xff,0xff,
+  0xff,0xdf,0xff,0xd7,0xff,0x7f,0xff,0xfe,0xff,0xff,0xab,0xff,0xed,0xff,0xdf,0xfe,
+  0xff,0xfd,0xff,0xff,0xff,0xdf,0xfe,0xff,0xff,0xff,0xd0,0x7f,0xfd,0xff,0xff,0x7b,
+  0xfe,0xff,0xff,0x37,0x7d,0xf3,0xfc,0xfb,0xac,0x87,0xd1,0xd9,0xfe,0xa9,0x6f,0xbf,
+  0xf7,0xff,0x4d,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,0xff,0xbf,0xff,
+  0xdf,0xff,0xff,0xfe,0xe7,0xff,0xfe,0xbe,0xb6,0xbb,0xde,0xa9,0x7d,0xbe,0xff,0x7f,
+  0xf7,0xff,0xff,0xc1,0xbd,0xfe,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xc5,0xff,0xbf,
+  0xff,0xff,0xfb,0x7f,0xff,0xaf,0x7b,0xf7,0xd7,0x75,0xff,0xf7,0xfb,0xff,0x6f,0xfe,
+  0xfe,0xd5,0x7d,0xef,0xef,0xff,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x9d,
+  0xfb,0xf7,0xfd,0xfe,0xff,0x7b,0xef,0x4f,0xff,0xbf,0xff,0xbf,0xfb,0xfb,0xbe,0xdf,
+  0xef,0xff,0xfe,0x7f,0x75,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0x56,0xfb,0xff,0xff,0xdf,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xf7,0xff,0xfe,0xff,
+  0xdf,0xed,0xff,0xff,0xbf,0xff,0xfd,0xbe,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfa,0x1f,0xff,0x35,0xcf,0xf1,0x2f,0x7f,0x33,0xcf,0xf7,0x5c,0x53,0x5e,0xd7,
+  0xb1,0xec,0xcf,0xff,0xf3,0x5f,0xff,0x3f,0xcf,0xf1,0xef,0xff,0xe7,0xc7,0xff,0xff,
+  0xff,0xff,0xf1,0xda,0xff,0xe8,0xff,0x33,0xff,0xf9,0xf4,0xff,0xaf,0xe7,0xaa,0x7c,
+  0xdf,0x97,0xbf,0xfa,0xcf,0xaf,0x65,0xef,0xeb,0xfc,0x97,0xbd,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xf5,0xe3,0x5f,0xff,0xff,0xbf,0xad,0x77,0x4b,0xd2,0x3f,0x9f,0xf7,
+  0xed,0xd2,0x7e,0x8f,0xbb,0x5a,0x7e,0xbf,0xff,0xfb,0xfe,0xfe,0xef,0xbf,0xff,0xff,
+  0xbf,0xff,0xff,0xff,0xfe,0xfa,0x6f,0xff,0xff,0xff,0xdf,0xff,0x7d,0x7b,0x16,0x4b,
+  0xfb,0xfc,0xb9,0x37,0xcd,0xff,0xe7,0x17,0xc7,0xb7,0xe5,0xff,0x7f,0xd7,0xf7,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x83,0xfb,0x2f,0xff,0xfe,0xfc,0x97,0x7f,0xbd,
+  0xfb,0x6c,0x8f,0xb7,0xe9,0xf2,0x7c,0xfb,0x69,0xff,0x7b,0xff,0x3e,0xcf,0xb3,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd1,0xbf,0xf5,0x7f,0xff,0x77,0x1b,0x8f,
+  0x7f,0xdf,0x77,0xd5,0xf7,0x7d,0x58,0x55,0x3d,0xfd,0xd6,0xf7,0xdd,0x87,0x69,0xdf,
+  0xd7,0xdd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0x37,0xfe,0xbf,0xff,0x7b,0x8f,
+  0xfe,0xbf,0xaf,0xeb,0x52,0xf4,0xff,0xaf,0x6b,0x9b,0xff,0x2f,0xeb,0xda,0xfe,0xbf,
+  0xaf,0x4f,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xde,0x97,0xff,0xd7,0xff,0xe5,
+  0xfa,0xf7,0xd7,0xf4,0xcd,0xba,0x4e,0x9b,0xb4,0xc5,0x33,0xff,0xf4,0xfd,0x3d,0x5f,
+  0xdf,0xf7,0xcf,0x7f,0x7e,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0x7f,0xff,0xff,
+  0xfe,0xff,0xfd,0x3f,0xff,0xd9,0xf6,0xdd,0xff,0x7b,0xdb,0xf7,0xff,0xb7,0xdf,0xf7,
+  0xff,0xff,0xff,0xf9,0xfe,0xdf,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xdf,0xfb,
+  0xff,0xff,0xff,0xef,0xfa,0xff,0xff,0xbf,0xef,0xfb,0xff,0xff,0xef,0xef,0xf9,0xff,
+  0xff,0xe7,0xfb,0xfe,0xff,0xff,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x91,
+  0x7f,0xbb,0xfe,0xff,0xbe,0x66,0xfb,0xfe,0x6d,0x9e,0xe7,0x99,0xf6,0x7f,0x9b,0xed,
+  0xd6,0x7d,0x9f,0x6f,0xbb,0xb6,0xfd,0xbe,0xee,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xff,
+  0xed,0x7f,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0x3f,0xff,0xdb,0xfc,0xff,0xff,
+  0xff,0xf7,0xff,0x7f,0x6f,0xfb,0xf7,0xfd,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfe,0xf7,0x8f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xfb,0xfe,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xef,0xfd,0xff,0xff,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfe,0xff,0xd1,0xff,0xff,0xff,0xfe,0x5f,0xf1,0xff,0xed,0x1b,0x47,0xd3,0xfc,
+  0x7d,0x1b,0x46,0xdf,0xff,0x1f,0x47,0xd7,0xfd,0xfd,0x7f,0xdf,0x9f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfb,0xe9,0x3f,0xff,0xff,0xff,0x49,0xfb,0xbf,0xff,0xaf,0xeb,0xfa,
+  0xfe,0xbf,0x2f,0xcb,0xfb,0x7f,0x2f,0xeb,0xfa,0x7e,0x9f,0x27,0xe9,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x33,0xff,0xff,0x7f,0xdf,0xff,0xff,0xff,0xfc,0xdf,
+  0x3f,0xdf,0xf3,0xf4,0xfd,0x3f,0xfd,0xfd,0xff,0x7f,0xde,0xf7,0xfd,0xdf,0xf6,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0xff,0xbf,0xf9,0xfe,0x7f,0x9d,0xe7,0xf9,
+  0xbe,0x3f,0x9b,0xe2,0xf8,0xbe,0x2f,0x9f,0xe6,0x9c,0x37,0x9f,0xe3,0xf9,0xfe,0x7f,
+  0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfd,0x5f,0xff,0xff,0xf9,0xf4,0x7f,0x7f,
+  0xff,0xf1,0xf4,0xfd,0x7f,0xcf,0xf7,0xfc,0x7f,0xbf,0xf7,0xac,0x7f,0x7f,0xcf,0xf1,
+  0xfe,0xfd,0x9f,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xa3,0xfd,0xff,0xff,0xfe,0xbf,
+  0xbf,0xff,0xfe,0xfe,0xbf,0xaf,0xef,0xfb,0xff,0xbf,0xf7,0xfb,0xfe,0xff,0xff,0xfb,
+  0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0x3f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xdf,0xfb,0xff,0xff,0x3f,0xff,0xff,0xff,0xfe,0xdf,0xf7,0xfd,
+  0xff,0xbf,0xdf,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xfe,0xae,0xff,0xff,
+  0xfd,0xff,0x7f,0xf7,0xf7,0xf9,0xff,0x7f,0xdf,0xb7,0xfd,0xff,0x7f,0xdf,0xef,0xfb,
+  0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xe5,0xff,
+  0xdf,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0x7f,0xff,0xf4,0x7d,0xbb,0x7f,0xcb,0xfd,
+  0xff,0xfe,0xcb,0xfe,0xbd,0xbf,0x6f,0xd3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb2,
+  0xbf,0xff,0xeb,0xfa,0xfe,0xaf,0xad,0xe9,0xf2,0xfe,0xbf,0xa6,0xe8,0xba,0x76,0x9d,
+  0xaf,0x7a,0xbe,0xbb,0xa3,0xeb,0xda,0xce,0xbb,0xad,0xe2,0xfa,0xfe,0xb7,0xaf,0xeb,
+  0xff,0xc7,0xff,0xff,0xff,0x5f,0xfb,0xdd,0xf1,0x7c,0xda,0x37,0xcd,0xb3,0xf4,0x37,
+  0x37,0xfc,0xb8,0xdf,0x13,0xf5,0xd3,0x84,0x7d,0xd7,0xfc,0xf5,0xff,0xff,0xff,0xff,
+  0xff,0xff,0x74,0x7f,0xff,0xf7,0xfa,0xff,0x7f,0xff,0x67,0xf9,0xdf,0x77,0xdf,0xdf,
+  0xfd,0xfc,0xdf,0xbf,0xf3,0xcb,0x7f,0xbf,0xff,0x5f,0xfb,0xdf,0x7e,0xff,0xff,0xff,
+  0xff,0xef,0xff,0xf8,0x97,0xff,0xfb,0xff,0x6f,0x7e,0xfa,0x5f,0x94,0xbb,0xfe,0xff,
+  0x3f,0x97,0xe5,0xff,0xef,0x57,0xff,0xbf,0xf7,0x4b,0xef,0xef,0xfb,0xfe,0xfb,0xff,
+  0xff,0xff,0xff,0xff,0xfe,0x99,0xfd,0xfd,0xff,0xb7,0xfe,0xfd,0xfe,0xfa,0x7e,0xbd,
+  0x27,0x6b,0xb9,0xf6,0xff,0x67,0xf3,0xfe,0x1f,0x8f,0xfb,0xdb,0xff,0xbd,0xfb,0xff,
+  0xbf,0xff,0xff,0xff,0xff,0xdf,0xef,0x7f,0xff,0xee,0xff,0x7f,0xff,0xff,0xff,0x9e,
+  0xfb,0xf9,0xfe,0x7d,0xff,0xf7,0xfb,0xf5,0xee,0xfd,0xfb,0xf5,0xff,0xef,0x7f,0xff,
+  0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xa7,0xff,0xfe,0xfd,0x77,0xff,0xbf,0xee,
+  0xfd,0xeb,0xef,0x3a,0xf7,0xff,0xff,0x5f,0xff,0xb3,0xf8,0xf7,0x3b,0xef,0xfb,0xf3,
+  0xed,0x3b,0xfe,0xff,0xbf,0xff,0xff,0xff,0xff,0x89,0xff,0xff,0xff,0xff,0xfb,0xde,
+  0xf6,0xfd,0xff,0xff,0xdf,0xff,0xfd,0xcf,0x7f,0xdf,0xe5,0xff,0x7e,0xdb,0x7a,0xfe,
+  0xaf,0xef,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x3f,0xff,0xfb,0xff,0xbf,
+  0xfb,0x7e,0xd7,0xed,0xfe,0xfe,0x9f,0xff,0x3f,0xef,0xdb,0xff,0xef,0xda,0xee,0xe7,
+  0xff,0xff,0x7f,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xa7,0xfd,0xcf,0xf3,
+  0xde,0xff,0xad,0xcf,0xef,0xfb,0xfe,0xfd,0x2d,0xff,0xff,0xff,0xfb,0xbf,0xbf,0xf7,
+  0x33,0xff,0xef,0xff,0xbc,0x1f,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xfc,0xef,0xfe,
+  0xff,0x7e,0xf7,0xd7,0xdb,0x7f,0xeb,0xfb,0xfe,0xff,0x7f,0xf7,0xff,0xfe,0x79,0xeb,
+  0xff,0x9b,0x67,0xb7,0xff,0xff,0xfa,0xdf,0xff,0xff,0x7f,0xff,0xff,0xff,0xfc,0x9d,
+  0xef,0xbf,0xef,0x5f,0xdf,0x77,0x5f,0xbd,0xfd,0xdb,0xff,0x5a,0xf7,0xad,0x8b,0x3a,
+  0xf7,0xbf,0xde,0x7f,0xfd,0xb3,0xac,0xd9,0x7f,0xff,0xbf,0xdf,0xfd,0x7f,0xff,0xff,
+  0x19,0xff,0xff,0x7f,0xdf,0xf7,0xdf,0xff,0xbf,0xdf,0xb5,0xed,0x79,0xee,0xd7,0x37,
+  0xce,0xfe,0xf3,0xbf,0xef,0xbb,0x7e,0xdb,0xff,0xf7,0xff,0xff,0xff,0xff,0xaf,0xff,
+  0xff,0xff,0x77,0xff,0xff,0xff,0xff,0xbf,0xef,0xff,0xff,0xcf,0xfb,0x7f,0x7f,0x3f,
+  0xb7,0xfd,0xff,0x5f,0xf7,0xf5,0xff,0x7f,0x5f,0xdf,0xef,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0x63,0xff,0xf1,0xfc,0xcb,0x3f,0xdd,0x72,0x7d,0xcf,0x1f,0xdf,0xb3,
+  0x3f,0x7f,0xff,0xfd,0x7f,0xff,0xe7,0xf9,0xff,0xff,0x9f,0x3f,0xff,0xf3,0xff,0xcf,
+  0x3f,0xff,0xff,0xff,0x35,0xaf,0xff,0x7c,0xb9,0x6f,0xff,0x3e,0xff,0xfa,0xfb,0xff,
+  0xa7,0xff,0xff,0xff,0xff,0xaf,0xff,0xfc,0xff,0x9f,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xf3,0xff,0xff,0xff,0xff,0x5c,0xbd,0xff,0xff,0xef,0xef,0xd6,0xff,0xff,0xbf,0x4e,
+  0xcb,0xfe,0xe9,0xd6,0x75,0x9d,0x73,0xd7,0x55,0xd5,0x75,0x5d,0x57,0xfe,0xfe,0xff,
+  0xff,0xff,0xfe,0xff,0xff,0xff,0xef,0xa6,0xff,0xff,0xf7,0xfd,0xff,0xff,0xff,0x97,
+  0xed,0xf9,0x7f,0xdf,0x9f,0x4f,0xb3,0xfc,0xfe,0xff,0xf9,0xef,0xff,0x9f,0xff,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x6a,0xff,0xff,0xff,0xbf,0x3f,0xf9,0xfa,
+  0xfe,0x9e,0xee,0xdb,0xd3,0xff,0xf7,0xfc,0xde,0xb7,0xf5,0x78,0xdf,0x57,0x9d,0xe5,
+  0x7f,0xe9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x1b,0xff,0xff,0xdd,0xc7,0x7f,
+  0x3f,0x57,0xd3,0xf7,0x79,0xde,0x77,0xfe,0x6f,0xbf,0xff,0xfe,0xff,0x9b,0xef,0xfb,
+  0x7e,0xef,0xfd,0x36,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xd9,0xff,0xff,0xfe,0xda,
+  0xf7,0xed,0x6b,0x7a,0xe6,0xbe,0xae,0x2f,0xfd,0xff,0x77,0xdf,0x5d,0xdf,0x7f,0xdf,
+  0xf7,0x7d,0xfb,0xff,0xaf,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xe5,0x7f,0xff,0xff,
+  0x7f,0xdf,0xff,0xc5,0x7f,0x5e,0xdf,0xf7,0xcd,0xff,0xff,0xff,0xff,0xeb,0xfe,0xbf,
+  0xff,0xff,0xff,0xff,0xff,0xf5,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,
+  0xff,0xff,0xff,0xef,0xdb,0xff,0xfd,0xa7,0xe7,0xff,0xfe,0xdb,0xbe,0xe7,0xbb,0xfb,
+  0xbe,0xef,0xbb,0xee,0xfb,0xff,0xe7,0xde,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe9,
+  0xff,0xff,0xff,0xff,0xfe,0x3d,0xaf,0xff,0xfb,0xff,0xff,0xbf,0xff,0xfa,0xfe,0xfd,
+  0xef,0xfe,0xfe,0xbf,0x8f,0xe3,0xfb,0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xee,0x9f,0xff,0xbf,0xef,0xfb,0xfe,0x39,0xbf,0x67,0x9b,0xf6,0xf9,0xb5,0x6f,0x1b,
+  0xbe,0xfd,0xef,0xdb,0xe6,0xfd,0xbf,0x6f,0x1b,0xfe,0x7d,0xbf,0xef,0xfb,0xfe,0xff,
+  0xbf,0xfe,0x16,0xff,0xff,0xff,0xff,0xff,0xfb,0x3f,0xdf,0xdb,0xfc,0xfd,0xbf,0xef,
+  0xfb,0xfe,0xfd,0xff,0xf3,0xfc,0xfd,0xbf,0xcf,0xfb,0xfe,0xff,0x3f,0xef,0xff,0xff,
+  0xff,0xff,0xff,0x74,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xfd,0xff,0xbf,0xef,
+  0xf7,0xbd,0xee,0xfb,0xff,0xbb,0xee,0xfb,0xbe,0xfb,0xbb,0xfe,0xff,0xbf,0xfb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x17,0xff,0xff,0xff,0xf5,0xff,0x3f,0xff,0xfb,0xf5,0xff,
+  0x7f,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xf5,0xff,0x9f,0xdf,
+  0xf7,0xff,0xff,0x7f,0xff,0xff,0xbb,0xff,0xff,0xff,0xfe,0x9d,0xeb,0xfd,0xd7,0x7e,
+  0x9f,0xa7,0xe9,0xff,0xbf,0xed,0xfa,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbc,0x9f,0xf7,
+  0xed,0xfb,0x7f,0xff,0xe7,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xef,0xff,
+  0xfd,0xf7,0xad,0xff,0x7b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xf7,
+  0xff,0x7b,0x7f,0xdf,0xff,0x6d,0xff,0xff,0xfe,0xcf,0xf7,0xff,0x9f,0xe7,0xf9,0xfe,
+  0x7f,0x9f,0xe7,0xe9,0xba,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0xe7,0xf9,0xfe,0x7f,0x9f,
+  0xe7,0xf9,0xfe,0x3f,0x8f,0xe7,0xf9,0xbc,0x7f,0x9f,0x99,0xff,0xfe,0xff,0xff,0x5f,
+  0xf7,0xff,0xff,0xff,0xcd,0xf3,0x7c,0xff,0xff,0xef,0xfb,0xff,0x9f,0xef,0xfb,0xff,
+  0xff,0xbf,0xdf,0xdb,0xfd,0xff,0x7f,0xff,0xf7,0xef,0xff,0xfd,0x3f,0xdf,0xdf,0xff,
+  0xeb,0xfe,0xff,0xbf,0xff,0xff,0xeb,0xfb,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0x7e,0xff,0xbf,0xff,0xfe,0xff,0xff,0xff,0x27,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0x3f,0xef,0xf7,0xff,0xff,0xbf,0xef,0xef,0xff,
+  0xbf,0xff,0xff,0xfe,0xff,0x7f,0x7f,0xf7,0xfd,0xff,0xff,0xde,0xff,0xff,0xd2,0xff,
+  0xff,0x7f,0xff,0xf7,0xff,0x7e,0x7f,0x9f,0xf6,0xfd,0xff,0x7f,0xf7,0xfd,0xff,0x7f,
+  0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xff,0xfd,0xfb,0xfe,0xff,0xff,0xfb,0xdf,0xff,0xff,
+  0xdb,0xff,0xff,0xff,0xf7,0xfd,0xff,0xff,0xdf,0xf2,0xfd,0xff,0x6f,0xd3,0xf4,0x75,
+  0x3f,0xd1,0xf4,0xfd,0x3f,0x4f,0xd3,0xff,0xff,0xff,0xff,0xfd,0xff,0xe7,0xff,0xff,
+  0xff,0xd2,0xff,0xbe,0xaf,0xad,0xea,0xd8,0x7e,0xbd,0x8e,0xe9,0xba,0x56,0x9b,0x86,
+  0xe1,0xba,0x33,0x8e,0xc0,0xb8,0x2c,0xbb,0x0b,0xe3,0xfa,0xbe,0xbf,0xaf,0xeb,0xfa,
+  0xfe,0xbf,0xf6,0x7f,0xff,0x1f,0xfd,0xef,0x7c,0xfb,0xfa,0xff,0xf7,0xec,0xdd,0xfe,
+  0xcf,0xb1,0xed,0xdf,0xf3,0xb6,0xff,0xbf,0xd6,0xc3,0xff,0xff,0xff,0x3f,0xff,0xff,
+  0xff,0xff,0xfe,0xfe,0x25,0xff,0xcf,0xdf,0xff,0x7c,0xfd,0xff,0x7f,0xf7,0xf6,0xfb,
+  0xfa,0x77,0x54,0xff,0xff,0x7f,0x7f,0xf7,0xdf,0x7f,0xd3,0xff,0xfb,0xff,0x3f,0xfe,
+  0xff,0xff,0xef,0x7f,0xff,0xbd,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0x3b,0xff,0xbf,
+  0xec,0xff,0xfa,0xff,0xfb,0xef,0xf7,0xff,0xbb,0xbf,0xff,0xd7,0xee,0xfd,0xff,0xfd,
+  0xff,0xf7,0xff,0xff,0xff,0xfe,0xdf,0x3f,0xff,0xfb,0xff,0x7f,0xef,0x7c,0x8f,0xa7,
+  0x3b,0x5a,0x7e,0x37,0x8f,0xc3,0xf1,0x77,0x1f,0xdf,0xff,0xf3,0xff,0xbf,0xfb,0xcf,
+  0xfb,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0x15,0xff,0xff,0xdf,0xfb,0xfa,0xfd,0xf7,
+  0x9e,0xfe,0xfe,0xdd,0xef,0xdf,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xee,0xf6,
+  0xf7,0xff,0xff,0xff,0xd7,0xdf,0xff,0xff,0xef,0x64,0xff,0xbf,0xef,0xfb,0xfb,0xf3,
+  0xf3,0xfc,0xf7,0xee,0xef,0xff,0x7e,0xfe,0xb5,0xfd,0x6b,0xfd,0xff,0x7d,0xe7,0xf7,
+  0xff,0xcf,0xff,0xbf,0xdf,0xff,0xff,0xfe,0xff,0xff,0xfc,0x1f,0xff,0xff,0xff,0xbf,
+  0xed,0x7f,0xef,0xff,0xf2,0x7d,0x6b,0x7f,0xd3,0xb7,0xfd,0x7f,0x5b,0xf5,0x3d,0xff,
+  0x4b,0xdb,0xf5,0xf7,0xb7,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0x93,0x7f,0xff,0xff,
+  0xff,0xff,0xfe,0xdf,0x7f,0xcf,0xaf,0xfd,0xfb,0x2f,0xef,0xb7,0xfd,0x6e,0xd7,0xfd,
+  0xef,0xff,0xfb,0xbf,0xff,0x7f,0xff,0x7f,0xff,0xff,0xff,0xff,0x7f,0xf1,0x7f,0xdf,
+  0xff,0xfd,0xbd,0x6b,0xff,0xff,0xfe,0xaf,0xe7,0xfc,0xf6,0x3b,0x9f,0x33,0xf8,0x3f,
+  0xcf,0xf3,0xb4,0xef,0xbd,0x7f,0xff,0x77,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xaf,
+  0xff,0xff,0xff,0xff,0xff,0x7f,0xfb,0xff,0xfe,0xee,0xff,0xf7,0x4d,0x7b,0xff,0xdf,
+  0x9d,0xf7,0x7f,0xd6,0x77,0xfb,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xfe,
+  0xd1,0xff,0xfe,0xaf,0xbf,0xfd,0xb7,0xff,0xdf,0x3e,0x5e,0x97,0x79,0xff,0xfe,0xdf,
+  0xa3,0x1e,0x7b,0x9c,0xa3,0x78,0xdb,0xa7,0xd9,0xff,0x7f,0xdb,0xf7,0xff,0xff,0xff,
+  0xf7,0xbe,0x9f,0xff,0xef,0xfd,0xf8,0xff,0xf9,0xff,0xef,0xf9,0x7e,0xdd,0xd7,0xaf,
+  0x3f,0x6f,0xdf,0xfd,0xb3,0x7c,0xff,0x3f,0xf9,0xda,0x7f,0xbf,0xff,0xff,0xff,0xff,
+  0xef,0xff,0xfe,0x87,0xef,0xff,0xff,0xff,0x7f,0x7f,0xfd,0xf3,0xff,0x5f,0xbf,0x9f,
+  0xff,0xfd,0xff,0x7f,0xf7,0xff,0x5e,0xdf,0xf7,0xff,0xfc,0xff,0xf7,0xff,0xff,0xdf,
+  0xff,0xff,0xff,0xbe,0xe4,0xbf,0xff,0x35,0xc9,0xf5,0xfd,0x1f,0x35,0xcf,0xf3,0xfd,
+  0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xcf,0xff,0xff,0xff,0x1f,
+  0xdf,0xff,0xff,0xff,0xff,0xf1,0x0a,0xff,0xf7,0xff,0x3f,0xfe,0xf9,0xfe,0xac,0xfe,
+  0xfd,0xff,0xff,0xff,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xf7,0xff,0xff,
+  0xf7,0xff,0xff,0xff,0xff,0xff,0xf5,0xcb,0xdf,0x4b,0xd2,0xa6,0xbc,0xff,0x3e,0xd7,
+  0xfe,0xff,0xfe,0x77,0x9d,0x73,0x5f,0xde,0x7d,0xf5,0x7d,0x5f,0x57,0xce,0xf5,0xff,
+  0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xf9,0x6f,0xfd,0x79,0x5e,0x57,0x9f,0xcf,
+  0xf9,0xff,0xdf,0x37,0xcf,0xf3,0xfe,0x7b,0x9f,0xcf,0xfe,0x7f,0x9f,0xcf,0xfb,0x3e,
+  0x5f,0x95,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xa7,0xff,0xff,0xff,0xff,0xff,
+  0x9f,0xef,0xfd,0xfe,0xed,0xff,0xfe,0xde,0x7f,0xcd,0xfb,0x7f,0xd7,0xdf,0xfd,0x7d,
+  0xad,0xb7,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc5,0xbf,0xff,0x7f,0xdf,
+  0xf7,0xfb,0xfd,0x7f,0xba,0x77,0x9d,0xaf,0xff,0xee,0xfb,0xff,0xff,0xfe,0xfb,0xbf,
+  0xef,0xa9,0xde,0x76,0x3d,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdb,0x9f,0xfe,0xbd,
+  0xaf,0xeb,0xfb,0xf5,0xff,0xff,0x4b,0x8a,0xf7,0x7d,0xdd,0x17,0xfd,0xff,0xdf,0xb7,
+  0xed,0xe3,0x7d,0x2f,0x2b,0x9a,0xe7,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x47,0xff,
+  0xd7,0x85,0xfd,0x73,0xfe,0xbf,0xff,0xed,0xfb,0x5c,0x7f,0x9f,0xeb,0xff,0xff,0xff,
+  0xff,0xff,0xfc,0xff,0xa6,0xe5,0x7a,0x5c,0xff,0xff,0xeb,0xff,0xff,0xff,0xff,0x6c,
+  0x7f,0xff,0xff,0xff,0xff,0xfd,0xb7,0xff,0xde,0xff,0xbf,0x9e,0xeb,0xbb,0xee,0x7b,
+  0xbf,0xbb,0xee,0xfb,0xbe,0xef,0xda,0x7e,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xec,0x9f,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xf9,0xf7,0xbf,0xaf,
+  0xef,0xde,0xfd,0xef,0xeb,0xd8,0xfe,0x3f,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0xc9,0xff,0x5b,0xfe,0xdf,0xbf,0xe6,0xdb,0xf6,0x75,0xbd,0x6f,0x5b,0xd6,
+  0xf1,0xbb,0xef,0xde,0xfd,0xbe,0x6f,0xdb,0xd6,0x7f,0xbf,0xef,0xfb,0xfe,0xff,0xbf,
+  0xef,0xfb,0xff,0xea,0x6f,0xff,0xff,0xff,0xff,0xff,0xf3,0xfc,0xff,0xbf,0xef,0xfb,
+  0xfe,0xff,0xbf,0xef,0xf3,0xff,0x3f,0xcf,0xdb,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xf7,0x8f,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xef,0xfb,
+  0xfe,0xef,0x7b,0xde,0xfb,0xbb,0xfb,0xbe,0xef,0xbb,0xef,0xbf,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xc5,0xff,0xfd,0xfd,0x7f,0xdf,0xf9,0xbf,0xfd,0x9f,
+  0xdf,0xf7,0xff,0xff,0xfb,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xfd,0x1b,0xdf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0x3f,0xfe,0xdf,0xa7,0xd9,0xff,0xf6,0xdf,
+  0xef,0xe9,0xf2,0x7f,0xeb,0xfb,0xfe,0xff,0xa7,0xfa,0x7e,0xff,0xaf,0xef,0xaf,0xe9,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xf7,0xf5,0xff,0x7f,0x6f,
+  0xff,0x77,0xfb,0x7f,0xde,0xff,0x7f,0xff,0xff,0xff,0xef,0xff,0xfb,0xff,0xff,0xbd,
+  0x7f,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0xfb,0xf8,0xbe,0x6f,
+  0x8f,0xe3,0xf9,0x9e,0x3f,0x1b,0xc7,0xf9,0xfe,0x7f,0x9f,0xe7,0xfe,0x7f,0x9f,0xe7,
+  0xf8,0xfa,0x6f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xff,0xdf,0xff,0xc7,0xff,
+  0xfd,0xff,0xff,0xef,0xf1,0xfc,0x6b,0x3e,0xe7,0xfb,0xfe,0xff,0xbf,0xff,0xfe,0xfb,
+  0x9f,0xe7,0xf7,0x7c,0x7f,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xef,
+  0xef,0xff,0xbf,0xff,0xff,0xff,0xff,0xbf,0xb7,0xff,0xff,0x7f,0xdf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfb,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf2,0x7f,
+  0xff,0x7f,0xff,0xf7,0xf7,0xff,0xbf,0xdf,0xff,0xff,0xef,0xff,0xff,0xff,0xfe,0xfe,
+  0xff,0xfb,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x6f,0xff,0xb6,0xff,0xfe,0x7e,0xff,0xf7,0xfd,0xff,0x7f,0xdf,0xfd,0xff,0x7f,0xdf,
+  0xf7,0xff,0x7f,0xd7,0xf7,0xfd,0xed,0xbf,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0xff,0xff,0xff,0xff,0xfe,0xdd,0xf4,0x7d,0xff,0xcf,0xdb,0xfe,0xfc,0xbf,
+  0xcf,0xf3,0xfe,0xbf,0xaf,0xeb,0xbc,0xfd,0x3f,0x6f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0xaf,0xff,0xe9,0xfa,0xbe,0xaf,0xa7,0x6b,0xb8,0xfe,0x9b,0xa7,0xe9,
+  0xba,0xfe,0xbf,0xab,0x78,0xfe,0xaf,0xa7,0xe8,0xb8,0xae,0xbf,0xad,0xeb,0xfa,0xfe,
+  0xbf,0xaf,0xeb,0xfd,0x27,0xff,0xf3,0xff,0xf7,0xf7,0xbf,0xf3,0xed,0xfb,0xdf,0x7f,
+  0x9f,0xff,0xf7,0xff,0xe7,0xff,0xbb,0x3f,0xfd,0xff,0x7e,0xbd,0xff,0xf7,0xfb,0xff,
+  0xf7,0xff,0xff,0xff,0xff,0xf2,0x7f,0xee,0xfd,0xff,0x7e,0xfe,0xba,0xef,0xfd,0xff,
+  0x7d,0x9f,0xed,0xf1,0xfe,0xef,0x7d,0xdf,0xff,0xdf,0x57,0xfd,0x7f,0xfa,0xdf,0xfd,
+  0xff,0xff,0xfd,0xdf,0xf7,0xff,0xfb,0x57,0xff,0x7f,0xbb,0xef,0xfb,0xfe,0xfb,0xf7,
+  0xbe,0xff,0xff,0xfb,0xff,0xff,0xbf,0xba,0x7f,0x64,0xbf,0xf5,0xf7,0xfe,0xff,0xbf,
+  0xfe,0xff,0xfc,0xff,0xff,0xff,0xff,0xff,0x93,0xff,0xff,0xdb,0xd7,0xf5,0xff,0x6f,
+  0xf2,0xd2,0x9c,0xaf,0xe9,0xea,0xfe,0x9f,0xaf,0xfa,0xfe,0x9e,0xaf,0x6b,0xfe,0xb6,
+  0xbf,0xfe,0x7f,0xff,0xfb,0xff,0xff,0xff,0xdf,0xf7,0x7f,0xfb,0xff,0xef,0x7f,0xff,
+  0xff,0xbf,0xde,0xdb,0x75,0xae,0xbf,0xaf,0x6b,0x9a,0x6f,0xae,0xeb,0xfa,0xfe,0xbe,
+  0xff,0xf7,0xaf,0xff,0xff,0xf7,0x7f,0xff,0xff,0xff,0xfe,0xaf,0xff,0xfe,0xff,0x7e,
+  0xff,0xfb,0x4f,0xad,0x7c,0xff,0xfb,0xef,0xff,0x9f,0xef,0xff,0x9a,0x3f,0xf7,0x3f,
+  0xff,0xe3,0xfb,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xfb,0xff,0xc1,0xff,0xfe,0xff,
+  0xff,0x2e,0xdb,0xf6,0xfb,0xfe,0x5c,0xd3,0xf5,0xbf,0xfb,0x7f,0xff,0xf4,0xfe,0xfb,
+  0xd6,0xf7,0x7d,0x7f,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xfc,0xb7,0xff,
+  0xf7,0xf9,0xef,0x7b,0xff,0xb5,0xfe,0xdf,0xff,0xed,0xdf,0xfc,0xfb,0xcf,0xbe,0xbd,
+  0xff,0xff,0xff,0xbd,0xf9,0x7f,0xff,0xdf,0xff,0xff,0xff,0xff,0xfb,0xf7,0xff,0x57,
+  0xfd,0xcf,0xf3,0x48,0xf3,0x2d,0xcd,0xf3,0xff,0xbf,0x4f,0xcf,0xef,0xe8,0xf7,0xff,
+  0x5b,0xff,0xbf,0xaf,0xef,0x7a,0xdf,0xff,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xe6,0xef,0x7d,0xbf,0x7f,0xdf,0x97,0xe5,0xfd,0x7f,0xff,0xff,0xff,0x7f,0xff,0xdf,
+  0xff,0xdb,0xbf,0xfe,0xfb,0x8d,0xf9,0xbf,0xff,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0x5f,0xfe,0xb7,0xef,0xe1,0xd6,0xf3,0xbe,0xef,0xbd,0xbf,0x2b,0x9e,0xb7,
+  0xe8,0xcb,0x7f,0xd7,0xad,0xeb,0x6f,0xfc,0xff,0x25,0xfe,0xff,0xff,0xbf,0xff,0xff,
+  0xfd,0xff,0xfb,0xd9,0xff,0xfe,0x77,0xff,0xff,0xff,0xff,0x67,0x5b,0x7e,0xe7,0xd7,
+  0x3f,0xfe,0x37,0xde,0xff,0xdf,0xbf,0xeb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xa2,0x7f,0xff,0xd7,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xf5,
+  0xff,0xff,0x73,0xbe,0xbf,0xff,0xff,0xcf,0xf3,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xef,0x41,0xff,0xbf,0x3f,0xd7,0xff,0xfc,0xf3,0xff,0xff,
+  0x7e,0xc9,0xb3,0xfc,0xff,0xf3,0xcc,0xfc,0x4f,0x3f,0xcd,0x7f,0x3c,0xff,0x27,0xc7,
+  0xff,0x2c,0x7f,0xff,0xff,0xf1,0xff,0x65,0xaf,0x97,0xff,0xfa,0xff,0xff,0x97,0x7f,
+  0xff,0xff,0xc3,0x37,0x3e,0xcf,0xff,0xff,0xff,0xf3,0xff,0xf5,0x9f,0xe7,0xda,0x3f,
+  0xff,0xf3,0x8d,0xff,0xff,0xff,0xff,0x7f,0x59,0x35,0xfe,0xff,0xff,0x3f,0xff,0xf3,
+  0xf9,0xef,0xff,0x7a,0xd2,0xbd,0x6f,0x5f,0xcf,0x9f,0xe1,0xfe,0xff,0xf2,0xd9,0xef,
+  0xfe,0x7f,0xbf,0xbf,0xbb,0xff,0xff,0xff,0xf9,0xef,0x36,0xff,0xdf,0xff,0xcf,0xff,
+  0xfe,0xff,0x3d,0xed,0xff,0x5f,0xc7,0xbd,0xcd,0xf9,0xfe,0xf3,0xff,0xff,0xde,0xdb,
+  0xb3,0xef,0xff,0xff,0xdf,0xf7,0xff,0xff,0xff,0xff,0x9f,0x7a,0x3f,0xfb,0xdf,0xf7,
+  0xb6,0xd9,0x26,0x7d,0x9c,0x7f,0x5f,0xf2,0x71,0xfd,0x75,0xff,0xee,0xcf,0xff,0xff,
+  0xea,0x5a,0xda,0x6f,0x5f,0xfe,0xfe,0xff,0xff,0xff,0xff,0xff,0xf9,0x5b,0xfa,0x77,
+  0xff,0xf6,0xff,0xbf,0x4d,0x3b,0xff,0x7d,0xd4,0x75,0xbd,0x66,0xdb,0xdf,0xdd,0x6f,
+  0xff,0xda,0x4f,0xdd,0xf7,0x5b,0xff,0x77,0x9d,0xff,0xff,0xff,0xff,0xfd,0xa3,0x7f,
+  0xef,0xff,0xff,0xbf,0xaf,0x7f,0xfe,0xfe,0xf7,0xff,0xeb,0xd7,0xd5,0xff,0xaf,0x7a,
+  0xf7,0xfd,0x7d,0xea,0xfa,0xfe,0xf7,0xff,0xfb,0xeb,0xff,0xff,0xff,0xff,0xff,0xee,
+  0x7f,0xfd,0xdf,0xf7,0xdf,0xf7,0x77,0xff,0xff,0xdf,0x37,0xfd,0x3a,0xfe,0x99,0xf5,
+  0xf6,0x6e,0x7f,0xff,0xfd,0x7f,0x6e,0xf7,0xff,0xfd,0xff,0x7f,0xff,0xff,0xff,0xff,
+  0xff,0x07,0xfb,0x75,0xfd,0x7f,0x7f,0xd3,0xf6,0x7d,0xff,0xed,0xfb,0xf7,0xff,0xb7,
+  0x47,0xfb,0xdd,0xaf,0xe7,0xfb,0x74,0x7d,0xa7,0xff,0xf9,0xff,0xff,0xb7,0xff,0xff,
+  0xff,0xff,0x9d,0xbf,0x9e,0x7f,0x9f,0xf7,0xff,0xaf,0x7f,0xdf,0xfe,0x7f,0xef,0xff,
+  0xf9,0xfe,0x7f,0xaf,0xfa,0xfe,0x7f,0xbf,0x67,0xfb,0xfe,0xff,0x9f,0xff,0xf9,0xff,
+  0xff,0xff,0xff,0xfe,0x1f,0xff,0x9f,0xe7,0xf8,0xfe,0x6f,0x8f,0x63,0xdb,0xf6,0xfd,
+  0x9f,0x6f,0xd9,0xd6,0xe5,0xe7,0xbb,0xfe,0xef,0x9f,0xe6,0xdb,0xee,0xff,0xbf,0xef,
+  0xfb,0xfe,0xff,0xbf,0xfa,0xe7,0xff,0xfe,0xff,0xbb,0xef,0xff,0xfe,0x6f,0xb3,0xfc,
+  0xfd,0xff,0xcf,0xdb,0xfe,0xff,0xbf,0xfb,0xff,0xff,0xfe,0xff,0xdb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x6a,0xff,0xff,0xbf,0xed,0xff,0xff,0xff,0xf7,0xfd,
+  0xff,0xbf,0xff,0xfb,0xfe,0xfe,0xff,0xef,0xfb,0xff,0xff,0xff,0xbf,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x5f,0xff,0xe7,0xfb,0xb6,0x7f,0x9f,0x47,
+  0xf3,0xfd,0xfd,0x7f,0x47,0xd7,0xfc,0xff,0x7f,0xb3,0xfd,0xfd,0xfe,0xe7,0xd1,0xfd,
+  0xf9,0x7e,0x5f,0xd7,0xff,0xff,0xff,0xff,0xff,0xb3,0xfd,0xfe,0xff,0xbf,0xef,0xfb,
+  0xea,0xdb,0xbe,0x9f,0x37,0xeb,0xfb,0x7e,0xaf,0xa7,0xda,0xf6,0x9f,0xb7,0x5c,0xfa,
+  0xfe,0xdf,0xa7,0xe9,0xfa,0x7f,0xff,0xff,0xff,0xff,0xf2,0x3f,0xdf,0xff,0xff,0xdf,
+  0xff,0x6f,0xff,0xdf,0xff,0xf7,0xfd,0x7b,0x7e,0xf7,0xbd,0xfe,0xdf,0xf7,0x6f,0xff,
+  0xb7,0xd7,0xff,0xbf,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0xaf,0xff,0xf7,0x1f,
+  0xa7,0x79,0xfe,0x77,0x8f,0xe7,0xf8,0xfe,0x27,0x0f,0xe2,0xf9,0xbe,0x6f,0xe6,0xe9,
+  0xfe,0x7f,0x9b,0xc7,0xf1,0xfe,0x2f,0x9f,0xa7,0xf9,0xfe,0x7f,0x9f,0xf9,0xfe,0xfe,
+  0xfb,0xff,0x7f,0xfb,0xff,0xff,0xff,0xff,0xd3,0xfc,0x79,0x1f,0xcf,0xf1,0xff,0x3f,
+  0xc5,0xfb,0xfe,0xff,0x7a,0xde,0x93,0xff,0xfd,0x3f,0xff,0xff,0xff,0xff,0xfd,0xbf,
+  0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xbf,0xeb,0xfb,0xff,
+  0xa7,0xeb,0xef,0x7f,0xff,0xef,0xff,0xfa,0x7f,0xff,0xae,0xbf,0xff,0xff,0xff,0xff,
+  0x77,0xff,0xfb,0xbf,0xdd,0xff,0x4f,0xff,0xff,0xff,0xff,0x6f,0xf7,0xb7,0xff,0x3f,
+  0xff,0xed,0xff,0x7f,0xff,0xf3,0xfd,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,
+  0xff,0xf2,0xd7,0xff,0xdf,0xf3,0xfd,0xe9,0x7f,0xdf,0xf7,0xff,0xed,0xff,0x7e,0xdf,
+  0xb5,0xfd,0xfe,0xdf,0xe6,0xfd,0xfb,0xdf,0x9d,0xff,0x7d,0xff,0xff,0xdb,0xff,0xff,
+  0xff,0xff,0xfc,0x4a,0xff,0x4f,0xff,0xbc,0xfd,0x3f,0xef,0xd1,0xfe,0xfc,0xbf,0x7f,
+  0xd3,0xfc,0xff,0xff,0xc8,0xff,0xff,0x9f,0xcf,0xdb,0xff,0xff,0xdf,0xff,0xd1,0xff,
+  0xff,0xff,0xff,0xff,0xab,0xbf,0xde,0xbf,0xa5,0xe9,0xda,0xfe,0x8d,0xab,0xea,0xfa,
+  0xae,0x8d,0xa3,0xe3,0xfa,0xf7,0xaf,0xe8,0xfa,0xfc,0x8d,0xa7,0xea,0xfa,0xfe,0xad,
+  0xaf,0xeb,0xfa,0xde,0xbf,0xf0,0x7f,0xbe,0x3e,0xcb,0xff,0xed,0xbd,0x3f,0xce,0xdf,
+  0x78,0xcf,0x1f,0xef,0xfb,0xff,0xff,0xbf,0xff,0x74,0xdf,0x3f,0x5f,0xbf,0xdf,0xdb,
+  0xff,0xdf,0xff,0xff,0xff,0x3f,0xff,0x07,0xff,0xde,0xef,0x7f,0xc7,0xff,0x4e,0xcb,
+  0xbf,0xec,0xff,0x4e,0xd6,0xbb,0xf5,0xdf,0x7f,0xf7,0x74,0xad,0xff,0xdd,0xff,0xfd,
+  0xff,0xff,0x7f,0xef,0xff,0xff,0xff,0xff,0xa5,0xff,0xfb,0xea,0xff,0xff,0xef,0xbf,
+  0xbf,0xef,0xfb,0xef,0xff,0x3f,0xee,0xfa,0xbb,0xe7,0xef,0xfd,0xfe,0xe3,0xdb,0x77,
+  0xfd,0xbf,0x7f,0xff,0x7d,0xf7,0x7d,0xd5,0x7f,0xf8,0x9f,0xff,0xfb,0xff,0xbe,0xdb,
+  0xff,0xbf,0xaf,0xf9,0xdf,0x7e,0x9d,0xff,0xe7,0xfa,0xff,0x77,0x3f,0xde,0xde,0x37,
+  0xad,0x67,0xff,0xfc,0x7f,0xfe,0xff,0xff,0xff,0xff,0xff,0x05,0xff,0xff,0xff,0xff,
+  0xfd,0xee,0xdf,0xfe,0xdd,0xff,0xff,0xb6,0xff,0xff,0xff,0xef,0xff,0xff,0xfe,0x7e,
+  0xef,0xd5,0xff,0xf9,0xff,0xfd,0x7f,0xf7,0xef,0xff,0x7f,0xff,0xd0,0x7f,0xff,0xef,
+  0xd7,0xed,0xf3,0xff,0xfe,0xfd,0xef,0xfb,0xb0,0xdf,0x3b,0xff,0xef,0xff,0xff,0x7e,
+  0xff,0xff,0xef,0xfa,0xee,0xfd,0x7f,0xff,0xfb,0xff,0xff,0xff,0xff,0xfb,0xdf,0xff,
+  0x7f,0xff,0xf3,0xed,0x7f,0xff,0xde,0xe3,0xfc,0xbf,0xf7,0xff,0xff,0xdd,0x3f,0x56,
+  0xe5,0xfd,0xbf,0x4f,0xdb,0xf2,0xfd,0xff,0x56,0xdf,0x7f,0xff,0xff,0xfb,0xff,0x02,
+  0xff,0xfb,0xff,0xde,0xff,0xfe,0x7f,0xfb,0xf6,0xe7,0xeb,0xdf,0xdf,0xdf,0xfb,0xfb,
+  0xaf,0xff,0xff,0xed,0xfe,0x1e,0xea,0xff,0x6f,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,
+  0x74,0x7f,0x9f,0xff,0x5d,0xff,0x30,0xfe,0xfe,0xff,0x8f,0xe3,0xee,0xdd,0xff,0xce,
+  0xfa,0x75,0x3f,0x4f,0xf3,0x7c,0xff,0x3f,0xcf,0xf3,0xfc,0xff,0x3f,0xff,0xff,0xff,
+  0xf7,0xf4,0xef,0xff,0xff,0xbf,0xff,0xf9,0xbf,0x5f,0x7f,0xbd,0xbf,0x7f,0xef,0xbf,
+  0xe3,0x7f,0xdd,0xb7,0xde,0xff,0xbf,0xef,0xfb,0xfe,0xe7,0xbf,0xef,0xfa,0xff,0xff,
+  0xff,0xff,0xff,0xd5,0xff,0xed,0xbf,0xb2,0xed,0xff,0xbf,0xd3,0x7b,0x1c,0xa7,0x7f,
+  0xdd,0x77,0xdf,0xbf,0xfe,0x67,0x9f,0xa7,0xe9,0xfa,0x6a,0x8f,0xe7,0x39,0xfa,0x7f,
+  0xff,0xff,0xff,0xf7,0xb8,0x1f,0xff,0x7f,0xfd,0xff,0x7f,0xfb,0xb7,0xcf,0xfb,0xfc,
+  0xfd,0xbf,0xef,0xff,0xff,0xfb,0xef,0x73,0x3c,0x4f,0x37,0xc7,0xf3,0x7c,0xdf,0x37,
+  0xcf,0xff,0xff,0xff,0xff,0xf7,0xa7,0xff,0xfd,0xef,0x7f,0xff,0xf7,0xee,0xfd,0xff,
+  0x7f,0xd5,0xef,0xfb,0x7d,0xff,0xff,0xf3,0x7e,0xf7,0xbf,0xef,0xfb,0xfe,0xfb,0xbf,
+  0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xea,0xb7,0xff,0xff,0xcd,0x77,0x5c,0xcf,0x27,
+  0xcf,0xff,0xfc,0x7b,0x1f,0xcf,0xf3,0xfd,0xfe,0xcf,0xff,0xff,0xff,0xff,0xf7,0xff,
+  0x3f,0xff,0xdf,0xff,0xbf,0xef,0xfb,0xff,0xf1,0x1b,0xff,0xff,0xfd,0xaf,0xff,0xb3,
+  0xfe,0x7e,0xf3,0xeb,0xff,0x3f,0xfc,0xf9,0x7f,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xcf,0xff,0xff,0xff,0xf7,0xfd,0xff,0x7f,0xf5,0xd3,0xff,0xff,0x52,0xd3,0xfc,
+  0xff,0xfe,0xcf,0xbe,0xbd,0x7b,0x3e,0xce,0xe6,0xb5,0x7d,0xff,0xe7,0x79,0xdf,0x37,
+  0x9d,0xe7,0x7d,0x5f,0x57,0x9d,0xfe,0xff,0xbf,0xef,0xfe,0xfa,0x2d,0xff,0xff,0x5c,
+  0xdf,0xb7,0xff,0xfb,0xfc,0xdf,0x3f,0xef,0xfb,0x7c,0xd7,0xf7,0xcf,0xfc,0xff,0x3f,
+  0xef,0xf3,0xfc,0xff,0x3f,0xef,0xf3,0xff,0xdf,0xf7,0xfd,0xff,0xf6,0x47,0xff,0xaf,
+  0xff,0xff,0xf1,0xdf,0xff,0xbf,0xfa,0xdd,0xde,0x7f,0x8f,0xb6,0xfd,0xff,0x6d,0xff,
+  0xff,0xfc,0x7f,0x5f,0xd7,0xd5,0xf6,0xff,0xff,0x7b,0xfe,0xff,0xbf,0xff,0xc8,0xbf,
+  0xf5,0x7f,0xdf,0xf7,0xff,0xef,0xff,0xdf,0x7b,0x5b,0xdf,0x51,0xda,0x55,0x3d,0x4f,
+  0x3f,0xff,0xbf,0xef,0xfb,0xfe,0xfb,0xbe,0xef,0xfb,0xea,0x77,0xdd,0xf7,0x7f,0xd9,
+  0x1f,0xfe,0xbf,0xaf,0xef,0xff,0xfb,0xff,0xaf,0x6b,0xfb,0xff,0xff,0xaf,0x6b,0xfb,
+  0xf7,0xfd,0xf7,0x6d,0xfb,0x7e,0xdf,0x37,0xed,0xfb,0x7e,0xdf,0xef,0xfb,0xfe,0xff,
+  0xfe,0xf3,0xff,0xd7,0x35,0xfd,0xf3,0xff,0xff,0xf5,0xc5,0xff,0x6f,0xff,0xf7,0xe1,
+  0x7f,0x7f,0x7e,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,
+  0xdf,0xff,0xe4,0xff,0xb7,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xfd,0xfd,0xb7,0xff,
+  0xfb,0x7e,0x7f,0xff,0xdf,0xee,0xfb,0xbe,0xef,0xbb,0xee,0x7b,0xfe,0xe7,0xbb,0xff,
+  0xff,0xff,0xff,0xfd,0xdf,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xdb,
+  0xff,0xff,0xbf,0xff,0xfb,0xfd,0xbf,0x6b,0xd8,0xf6,0x3d,0xef,0xe7,0xff,0xf6,0x7f,
+  0xef,0xe7,0xff,0xff,0xff,0xe0,0xff,0xfb,0xfe,0xfd,0xbf,0xef,0x5b,0xfe,0xf5,0xbe,
+  0xe2,0xfb,0xd6,0xf9,0xbd,0x6f,0x1e,0x2d,0xbe,0x6f,0xdb,0xd6,0xff,0xbf,0x6f,0xdb,
+  0xf6,0xff,0xbf,0xef,0xfb,0xff,0xed,0x6f,0xff,0xff,0xff,0x3f,0xff,0xfb,0xfe,0xff,
+  0xbe,0xff,0xbb,0xfe,0xfd,0xbf,0xef,0xff,0xfb,0x3f,0xcf,0xdb,0xfe,0xff,0xbf,0xcf,
+  0xdf,0xf6,0xff,0xff,0xff,0xff,0xff,0xf7,0xcf,0xff,0xff,0xff,0xbf,0xff,0xfe,0xff,
+  0xbf,0xef,0xff,0xfe,0xff,0xbf,0xef,0xfb,0xff,0xff,0xbe,0xef,0xbb,0xee,0xfb,0xee,
+  0xef,0xbf,0xef,0x7b,0xff,0xff,0xff,0xff,0xff,0xcd,0xff,0xfd,0xff,0xfe,0x7f,0xd3,
+  0xfd,0xfd,0x7f,0x5f,0xd3,0xf5,0xed,0x7f,0xdf,0x9f,0xf9,0x3f,0xff,0xff,0xff,0xef,
+  0xff,0xff,0xff,0xff,0xff,0xfe,0x5f,0xff,0xff,0xff,0xef,0xbf,0xff,0x9f,0xff,0xf9,
+  0xfa,0xff,0xdd,0xa7,0x6a,0xfa,0xbf,0x9f,0xa7,0xe9,0xde,0x7f,0xab,0xfe,0x9f,0xaf,
+  0xeb,0xfa,0xfe,0xdf,0xb7,0xeb,0xfb,0xe9,0xff,0xff,0xff,0xff,0x07,0xfe,0xf7,0xff,
+  0xed,0xff,0xfd,0xff,0x75,0xff,0x7f,0xdf,0xd7,0xfd,0xcd,0x77,0x5f,0xed,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xf8,0xff,0xfe,
+  0xf9,0xfe,0x6f,0x9f,0xe7,0xf8,0xbe,0x2f,0x8f,0xe6,0xf9,0xfe,0x2f,0x0b,0xe6,0xfe,
+  0x7f,0x9f,0xa7,0xf9,0xfe,0x7f,0x9f,0xa7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x9f,
+  0xff,0xc7,0xfb,0xf5,0xff,0xff,0xef,0xf1,0xfd,0xfd,0x7f,0x6f,0xf1,0xfc,0xf9,0xbf,
+  0xf7,0xfe,0xff,0xbf,0xe7,0xf9,0xfe,0xff,0xff,0xef,0xfb,0xf5,0xff,0xff,0xff,0xff,
+  0xfb,0xff,0xfb,0xff,0x7e,0xbf,0xff,0xfd,0xff,0xff,0xbf,0xaf,0xf9,0xff,0xfe,0xdf,
+  0xe7,0xfa,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xbf,0xff,0xfe,0xbf,0xff,0xff,
+  0xff,0xf0,0x7f,0xfb,0x7f,0xff,0xd7,0xff,0xff,0xff,0xdf,0xf7,0xfd,0xfd,0xff,0xdf,
+  0xd7,0xb5,0xfe,0xdf,0xfb,0xfe,0xdf,0xff,0xff,0xfb,0xff,0xdf,0xbf,0xef,0xff,0xff,
+  0xff,0xff,0xff,0x4f,0xff,0xe7,0xfd,0xfa,0x7f,0xdf,0xf7,0xfd,0xfe,0xdf,0xf7,0xe7,
+  0xfd,0xfa,0x76,0x9f,0xef,0x7f,0xdf,0xf3,0xfd,0xff,0x7f,0xdf,0xf3,0xfd,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xe5,0xff,0xff,0xff,0xff,0x2f,0xdf,0xff,0xff,0xef,0x27,0xeb,
+  0xf2,0xfd,0xbf,0xa7,0xf3,0xfd,0xff,0x4f,0xd3,0xf4,0xf5,0x3d,0x4f,0xd3,0xf4,0xf5,
+  0x3d,0x6f,0xdb,0xf7,0xff,0xfb,0x37,0xf3,0xeb,0xfa,0x2e,0xb5,0xaf,0xe8,0xfa,0xfe,
+  0xbf,0x8f,0x6b,0xba,0xbe,0xbf,0xa7,0x3a,0xee,0xbb,0xae,0xeb,0xba,0xee,0x8b,0xa6,
+  0xeb,0x3a,0xbe,0xb3,0xad,0xeb,0xfd,0x27,0xff,0xff,0x7f,0xff,0xff,0xf5,0x3f,0xff,
+  0xee,0xf3,0xfb,0xfe,0xf4,0xff,0xb6,0xff,0xbc,0xdf,0x17,0xcd,0x3f,0xff,0xeb,0x15,
+  0xfd,0xff,0x7d,0xfc,0xff,0x7f,0xef,0xdf,0xee,0x6f,0xbf,0xff,0xff,0x7f,0xff,0xaf,
+  0xed,0xff,0x7f,0xdf,0x7f,0xfb,0x7b,0xbe,0xbf,0x9d,0xfd,0x2e,0x6b,0x9f,0xe7,0xff,
+  0xde,0xdf,0xbf,0xcb,0xbb,0x7f,0xff,0xff,0xff,0xf8,0x9f,0xff,0xff,0xff,0xff,0xef,
+  0xd3,0xfb,0x7e,0xff,0xbf,0xff,0xff,0xee,0xef,0xbb,0xf6,0x57,0xef,0xeb,0xfb,0xff,
+  0xff,0xfd,0xf7,0xff,0xff,0x7f,0x7f,0xdf,0xdf,0xf7,0xfe,0xe1,0xff,0xff,0xff,0x9e,
+  0x9e,0xff,0xe4,0xf8,0x7a,0x9f,0xaf,0xf9,0xde,0x7e,0x9f,0xff,0xf8,0xfe,0xbf,0xaf,
+  0xc8,0xfa,0x9e,0xa5,0xad,0xcb,0xfa,0xed,0xff,0xff,0xbf,0x6f,0xf1,0x6f,0xff,0xf9,
+  0xfd,0xfb,0xff,0xcb,0xff,0xbf,0xf7,0xd5,0xbf,0xff,0xb7,0x57,0xdf,0xff,0xbe,0xeb,
+  0xfa,0xee,0xb9,0xad,0x6b,0xfa,0xde,0xbb,0xaf,0xfd,0x7f,0xff,0xfb,0xfe,0x47,0xff,
+  0xff,0xff,0xfa,0x7f,0xff,0xef,0xff,0x98,0x77,0xab,0xbe,0xfb,0xbf,0xff,0xfb,0xbb,
+  0xbe,0xff,0xfb,0xfe,0xfb,0xff,0xef,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xc9,
+  0x7e,0xff,0xff,0xed,0x7f,0xff,0xdf,0xbf,0xfd,0x7d,0xff,0xe7,0xfc,0xff,0x6e,0xdb,
+  0xf5,0xfe,0x5f,0xff,0xfe,0xfe,0xf7,0xef,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0x6f,
+  0xf8,0xbf,0xfb,0xf7,0xfb,0xed,0xdf,0xd7,0xdd,0xff,0x6f,0x7f,0x37,0xbf,0xef,0x7b,
+  0xd6,0xee,0xe7,0xfd,0xff,0xdf,0xfd,0x7b,0x7f,0xf7,0xff,0xff,0x7d,0x7f,0xef,0xff,
+  0xff,0xf7,0x07,0xfb,0xcf,0xf3,0xd5,0x7e,0x17,0xbf,0x72,0x7c,0xff,0x3d,0xce,0xf1,
+  0xfc,0xef,0x2b,0xd3,0x9c,0xef,0x3f,0xae,0x73,0xfd,0xfd,0x3c,0xfe,0x7f,0xff,0xed,
+  0xff,0xff,0xff,0xfc,0xff,0xdd,0xbf,0x75,0xff,0xfd,0xbf,0xbb,0x7b,0xdf,0x97,0x7d,
+  0xbd,0x63,0xd9,0xeb,0xfa,0x73,0xf7,0xed,0xde,0xee,0x7b,0xbf,0xf7,0xf7,0xdf,0xff,
+  0xfe,0xff,0xff,0xff,0xfe,0x99,0xfe,0xbe,0xee,0x7f,0xfb,0x7d,0xff,0xeb,0xf1,0xde,
+  0x7a,0xae,0xd7,0xfb,0xff,0xfa,0xf5,0xe9,0xeb,0xfe,0x5e,0xff,0xae,0xbe,0xdb,0xed,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xc3,0xbf,0x6b,0x7a,0xfd,0xf6,0xce,0xff,0xff,0xff,
+  0xbf,0xe7,0xf9,0xee,0xb9,0xbf,0xef,0xda,0xf3,0x2b,0xff,0xfb,0xff,0xef,0xfb,0xff,
+  0xfa,0xff,0x9b,0xef,0xff,0xff,0xff,0xe4,0x7f,0xbf,0xff,0xf7,0xff,0xfd,0xff,0xdf,
+  0xff,0xf7,0xf3,0xff,0x7f,0xdf,0xf7,0xfb,0xff,0x76,0xef,0xef,0xff,0x5f,0xff,0xff,
+  0xff,0xff,0x6f,0xff,0xff,0xff,0xff,0xf7,0xfe,0x8f,0x8d,0xd5,0xfd,0x7f,0xff,0xff,
+  0xa7,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xdf,0xff,0xff,0xff,0xff,0xbf,0xff,0xef,
+  0xff,0xbf,0xff,0xdf,0xfb,0xfb,0xbf,0xef,0xfd,0xff,0xe9,0xfe,0xde,0xff,0xbf,0x7f,
+  0xfd,0xff,0x7e,0xff,0xef,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xf9,0xfe,
+  0xff,0xff,0xff,0xfd,0xfe,0xfd,0x9f,0xf7,0xd9,0xfe,0xdc,0xee,0x0f,0xff,0xd4,0xff,
+  0xfc,0xfb,0x3f,0xcf,0xbf,0x3f,0xff,0xff,0xfc,0xf3,0x5f,0xff,0x35,0xf1,0xfc,0xff,
+  0xfe,0xff,0xf3,0xfd,0xff,0xdf,0xdf,0xf1,0xff,0xff,0xfe,0xff,0xfc,0x96,0xbf,0xff,
+  0xaf,0xff,0x3f,0xcb,0xfd,0xf3,0xeb,0xef,0x7c,0xff,0xf9,0xcf,0xff,0xfc,0xfe,0xff,
+  0xbf,0xfe,0x9f,0xfe,0xfc,0xff,0x7f,0xfe,0xf3,0xff,0xff,0xff,0xdf,0xfd,0x78,0xf7,
+  0xff,0xe6,0xb9,0xfd,0x5f,0xcb,0xd4,0xbf,0xfe,0x6b,0x9e,0xd3,0xad,0x6f,0x2e,0xcf,
+  0x9f,0xbf,0xfd,0xfb,0xf2,0xbf,0xef,0xfb,0xd2,0xff,0xa9,0xae,0x6b,0xfb,0xff,0xbf,
+  0x9b,0xff,0xfc,0xd7,0xff,0xff,0xf3,0xde,0x57,0xb7,0xcd,0x7b,0x7e,0x57,0xf7,0xcd,
+  0xff,0xcf,0x97,0xfe,0xff,0x3c,0xd7,0xf7,0xef,0x7f,0x5f,0xdf,0xb5,0xe5,0x7f,0x7f,
+  0xfd,0xfb,0xe7,0xfd,0xff,0x5f,0xfd,0x3e,0xcf,0xd2,0xe9,0xf7,0xbf,0x0f,0x52,0xfc,
+  0xf7,0xef,0x5b,0x3f,0x9f,0x73,0xed,0xff,0xff,0xbe,0x7c,0xdf,0xfe,0xf9,0xff,0xff,
+  0xef,0xff,0xf6,0x6f,0xff,0xff,0xf7,0xfd,0xad,0x5b,0x56,0x7f,0xfd,0xe7,0xf9,0xd6,
+  0x56,0x1d,0xa7,0x6b,0x75,0x9b,0xcf,0xfd,0xdf,0xf7,0xdd,0xc7,0x6b,0xdf,0x77,0x3d,
+  0xff,0x7d,0xdf,0xf6,0xc7,0xff,0xfe,0x6b,0xff,0xff,0xf7,0xff,0xeb,0xfe,0xba,0xbe,
+  0xab,0xeb,0xfa,0xbe,0xbf,0xeb,0x5a,0xe3,0xfd,0xbf,0x7f,0xfe,0xf1,0xad,0x2f,0x5b,
+  0xea,0xfe,0xbf,0xbf,0xff,0xb1,0xff,0xfe,0xe9,0x1f,0xff,0xff,0xff,0xfd,0x7f,0x7f,
+  0xd7,0xf7,0xfd,0x7f,0x7f,0xdf,0xfd,0xb9,0x7e,0xbb,0xd6,0xc7,0xff,0x7c,0xf7,0xa5,
+  0xcd,0xff,0x5f,0xd7,0xf7,0xff,0xf9,0xbf,0xed,0xdf,0xf4,0x7f,0x9f,0xe7,0xfb,0xfc,
+  0x7f,0x3f,0xcf,0xd3,0x7e,0x7d,0x37,0xed,0xf6,0xbd,0xbf,0x6f,0xdf,0xff,0xff,0xff,
+  0x47,0xff,0xfe,0x7f,0xff,0xff,0xff,0xff,0xa5,0xfe,0x79,0xbe,0xa7,0xff,0xfe,0xff,
+  0xaf,0x7f,0xf8,0xf6,0xb9,0x9f,0xe7,0x9b,0xfe,0xff,0xe3,0xfa,0xff,0xbf,0xff,0xff,
+  0xff,0xe7,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0xee,0x7f,0xd6,0x25,0x9f,0x6f,0x5b,
+  0xee,0xef,0xbf,0xef,0x5b,0xc6,0x35,0xbf,0x62,0xfb,0x37,0x9f,0xe6,0x59,0x76,0x7f,
+  0xbf,0xef,0xd8,0x7e,0xff,0xbb,0xef,0xfb,0xfe,0xff,0xf8,0x9b,0xff,0xf3,0xbf,0xcf,
+  0xfb,0xfe,0xff,0xfc,0xef,0xbf,0xee,0xfb,0xbf,0xcf,0xbb,0xf6,0xff,0xff,0xfb,0xfd,
+  0xff,0xbf,0xff,0xdb,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xf3,0xff,0xff,0xbf,
+  0xfb,0xfe,0xff,0x7f,0xff,0xf7,0xff,0xff,0x7f,0xef,0xf7,0xfb,0xff,0x7f,0xff,0xfe,
+  0xff,0xff,0xdf,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x5f,0xed,
+  0x3f,0xc7,0xff,0xef,0xff,0xff,0x5e,0xff,0xf5,0xff,0x3e,0x5f,0xd3,0xfd,0xfe,0xc7,
+  0xd1,0xf4,0xfd,0x1f,0xff,0xd7,0xfe,0x6b,0x7e,0x5f,0xff,0xff,0xff,0xfb,0xff,0x2f,
+  0xff,0xab,0xea,0xff,0x7f,0xdf,0xf7,0xea,0x9b,0xbe,0xab,0x23,0x69,0xf2,0x3e,0x9f,
+  0xeb,0xfe,0x7e,0xbd,0xaf,0xfd,0xf2,0x7f,0x8f,0xe7,0x69,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xff,0xf5,0xed,0x7f,0xfd,0xff,0xff,0xdd,0x7f,0xff,0xf7,0xfd,0xfd,0x7f,0xde,
+  0xf7,0xfb,0x7e,0x74,0xd7,0xf5,0xff,0xff,0x5e,0xfd,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xf1,0x3d,0xff,0xbe,0x27,0x9f,0xc7,0xf9,0xfc,0x2f,0x9f,0xa2,0xf9,0xba,0x6e,
+  0x9f,0xc6,0xf1,0xb7,0x0b,0xe2,0xf8,0x9e,0x7e,0x8b,0xe6,0xf9,0xbe,0x7f,0x9f,0xe7,
+  0xf9,0xfe,0x7f,0x97,0xfb,0xd7,0xf5,0xff,0xfa,0xef,0xdf,0xe5,0xff,0x7f,0xdf,0xf7,
+  0xf4,0xff,0x7a,0xcf,0xbd,0xe9,0xbf,0xcf,0xf1,0xfc,0xff,0xbf,0x4f,0xf3,0xf4,0xff,
+  0xff,0xff,0xff,0xff,0xf0,0xff,0xfe,0xff,0xbf,0xff,0xff,0xfa,0xfe,0xbf,0xbf,0xaf,
+  0xfb,0xeb,0x9e,0xff,0xed,0xfe,0xbf,0xaf,0xed,0xff,0xfe,0xfa,0xf7,0xeb,0xfe,0xfe,
+  0xbf,0xff,0xff,0xff,0xff,0xfd,0xdf,0xff,0x5f,0xd7,0xf7,0xfd,0xbf,0xfe,0xff,0xff,
+  0xdf,0x7f,0xff,0xd7,0x7d,0xff,0xfb,0xb7,0xf4,0xff,0xff,0xdf,0xf3,0xff,0xff,0x3f,
+  0xcf,0xfb,0xff,0xff,0xff,0xff,0xff,0xc3,0xff,0xeb,0x7a,0x5f,0xbf,0xf7,0xff,0xdf,
+  0xdf,0xf3,0xbd,0xff,0x3e,0x7f,0xf7,0xf7,0xfb,0xfe,0x9f,0xf7,0xfd,0xfb,0x6f,0xdf,
+  0xbd,0xf9,0xff,0x7f,0xff,0xff,0xff,0xff,0xfe,0x7f,0xf7,0xff,0xfb,0xdb,0xff,0xf7,
+  0xff,0xcf,0xda,0xb7,0xf5,0xab,0xcf,0xfb,0xd7,0xff,0x77,0xd3,0xff,0xf5,0x3d,0xff,
+  0xfe,0xf2,0xff,0xff,0xfe,0xff,0xbf,0xfc,0xbf,0xfe,0x0e,0xfa,0xfa,0xfe,0xad,0xab,
+  0xe1,0xfa,0x7e,0xbb,0xaa,0xeb,0xba,0xfe,0x1f,0x22,0xe9,0x5e,0x3d,0xab,0xeb,0xfa,
+  0xde,0xbf,0xac,0xeb,0xf8,0xde,0xbf,0xab,0xeb,0xfa,0xdf,0x71,0xbe,0xff,0xdf,0xf7,
+  0x7c,0x71,0xfc,0xdb,0xfd,0x7f,0xff,0x64,0xff,0xdf,0x55,0xff,0xfe,0xfb,0xc5,0xff,
+  0x7b,0xff,0x7f,0xf7,0xf9,0x7c,0xff,0x3f,0xff,0xff,0xfb,0xfb,0xfb,0x9f,0xff,0xfa,
+  0x7f,0xff,0xf5,0xfd,0x77,0xf7,0xfd,0xf7,0xe6,0xff,0x7f,0xfb,0xf7,0xeb,0x73,0x97,
+  0xbf,0xed,0xee,0xff,0xff,0x6b,0xae,0xf7,0xcf,0xdf,0x6f,0xff,0xff,0x7e,0x67,0xff,
+  0xff,0xff,0xff,0xf6,0xbf,0xb7,0xfe,0xff,0xfe,0xff,0xb7,0xef,0xef,0xf7,0xfb,0xdf,
+  0xfa,0xfa,0xff,0xbf,0xfb,0xbf,0xbe,0xfb,0xb7,0xef,0xbf,0xff,0xff,0xbe,0xef,0x78,
+  0x5f,0xdf,0xd2,0x5f,0xfb,0xeb,0xdb,0xd5,0xbd,0xbf,0xf9,0xfa,0xbe,0x9e,0xeb,0xe9,
+  0xef,0xff,0xaf,0xfb,0xfe,0xd4,0x3d,0x6f,0x61,0xbf,0xdf,0xde,0xff,0xff,0xff,0xf7,
+  0xfe,0x5f,0xef,0xff,0x7f,0xff,0xff,0x7f,0xdf,0xef,0xfe,0xf7,0xdb,0xdf,0xfb,0xff,
+  0xff,0x7f,0xfe,0xde,0xc7,0xff,0xff,0xdf,0xf7,0xde,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xf5,0xfd,0xa1,0xff,0xf3,0xbc,0x17,0x9f,0xbe,0xff,0xfe,0xef,0xfb,0x8e,0xeb,0x7a,
+  0xbe,0xfb,0xbf,0xef,0x9e,0xff,0xb5,0xee,0xef,0xeb,0xbf,0xef,0xff,0xff,0xef,0xff,
+  0xff,0xff,0xff,0xfe,0x6f,0xfd,0xff,0xff,0xff,0xf6,0xff,0xef,0xed,0x5f,0xbe,0xfc,
+  0xbe,0x4f,0xd3,0xdf,0x7d,0xef,0xbf,0xff,0xff,0xef,0xfb,0x97,0xf7,0xf7,0x9f,0xfd,
+  0x93,0xdf,0xff,0xfe,0xfe,0xef,0xff,0xef,0xff,0xdf,0x56,0xed,0xff,0xfd,0x7b,0xdf,
+  0xed,0xeb,0x5d,0xff,0xdd,0xff,0x9f,0xff,0xd7,0xef,0xfd,0xff,0xff,0x7b,0x9f,0xff,
+  0xff,0xbf,0xff,0xff,0xff,0xfd,0xe1,0xff,0xdf,0xcf,0xbe,0xf7,0x8d,0xeb,0x48,0xfb,
+  0x3f,0xcf,0xf3,0x9c,0xfd,0xf7,0xcc,0x65,0xfa,0xb7,0xff,0xff,0xf4,0xd7,0x4f,0xaf,
+  0x63,0xfa,0xfe,0x3f,0xff,0xf3,0xff,0xfd,0xbf,0xef,0xff,0xff,0xfe,0xfd,0xdf,0x7f,
+  0xdf,0xb7,0xfd,0xfd,0x7e,0xf7,0xdf,0xbd,0xda,0xbf,0xfb,0xf7,0xdf,0xff,0x77,0x7f,
+  0xfd,0xff,0x77,0xef,0xf7,0x7f,0xff,0x7f,0xff,0x15,0x7f,0xb7,0x75,0x8b,0xfe,0x9f,
+  0xbf,0x78,0xfe,0xba,0x1f,0xe7,0xf1,0xbf,0x3d,0x9d,0xfd,0xfb,0x7e,0xdc,0xbf,0x6b,
+  0xdf,0x77,0xfd,0xaf,0x7f,0xf6,0x3f,0xff,0xe9,0xff,0xea,0xff,0xfd,0xdd,0xbf,0xfe,
+  0xfb,0xff,0xff,0xf3,0xef,0xf9,0xef,0xdf,0xff,0x8f,0xfb,0xff,0x7e,0xaf,0x73,0xff,
+  0xff,0xf7,0x2b,0xff,0xff,0xff,0xff,0xee,0xff,0x77,0xff,0xf8,0x1f,0xee,0xff,0xef,
+  0xff,0xdd,0x7f,0xff,0xdd,0xbd,0xbe,0xf7,0x7b,0xff,0x7f,0xec,0xff,0xfe,0xe7,0xde,
+  0xf7,0xfb,0xff,0xf7,0xfb,0xff,0xff,0xff,0xf5,0xff,0xff,0xff,0xff,0xda,0xff,0xfc,
+  0xff,0xff,0xd7,0xfc,0x7c,0xcf,0xff,0xcf,0xff,0x5f,0xd3,0x3f,0xcf,0xbf,0xff,0x3f,
+  0xcc,0xf7,0xfc,0x9f,0x3f,0xd7,0xf6,0x7f,0xff,0xfe,0xff,0xff,0xff,0xff,0xf6,0x6b,
+  0xe7,0x4f,0xff,0xf7,0xff,0xfd,0xf3,0xf8,0xff,0xff,0xe7,0xf9,0x3f,0xfc,0xff,0xff,
+  0xef,0xda,0xab,0x8e,0xff,0xfb,0xff,0xff,0x8f,0xff,0x3f,0xdf,0xff,0xff,0xff,0xdf,
+  0x4f,0x79,0xff,0x3f,0x1f,0xff,0xf7,0xfb,0x5f,0xcb,0xb5,0xb9,0xbf,0xea,0xcf,0xf5,
+  0xff,0xeb,0x7a,0xff,0xbf,0xe9,0xfe,0xcf,0xff,0xff,0xff,0xfb,0xfb,0xff,0xff,0xff,
+  0xfb,0xd1,0xbf,0xff,0xcf,0xf3,0xff,0xff,0xbf,0xe7,0xf3,0x7e,0xdf,0xb7,0xec,0xf9,
+  0xfe,0x7f,0x3d,0x7f,0x5f,0xff,0xff,0xff,0xf3,0xff,0xff,0xff,0xfd,0xff,0x7f,0xff,
+  0xff,0xcf,0xd9,0x17,0xed,0xfd,0x7f,0x5f,0xd7,0xfb,0xdb,0x6c,0xdd,0xc3,0xdb,0xb6,
+  0x26,0xdd,0xfb,0x6d,0xff,0xfd,0xd6,0xf5,0xbf,0xf7,0xff,0xfa,0xff,0xf7,0xef,0xcb,
+  0xff,0xff,0xf7,0xfe,0xc6,0xfe,0xbd,0x6d,0x7b,0xdf,0xf5,0x9f,0xe5,0x6b,0xba,0x75,
+  0x9d,0xc7,0x6b,0xdf,0xce,0xbf,0x7d,0xb6,0xf7,0xbd,0xff,0xff,0xda,0x57,0xff,0xf7,
+  0x71,0x7f,0xff,0xff,0xff,0x74,0xdf,0xff,0xdf,0xfc,0x7e,0x7f,0xff,0xdb,0xe7,0xaf,
+  0xea,0x9a,0xba,0xb7,0xef,0xff,0xfe,0xb9,0xaf,0x5b,0xce,0xdf,0xf7,0xff,0x4b,0x57,
+  0x9f,0xbe,0xaf,0xff,0xff,0xff,0xfb,0xdf,0xff,0xff,0xff,0xbf,0xfd,0xff,0xff,0xf7,
+  0xf7,0xfd,0xfa,0x7f,0xd3,0xfe,0xff,0xbf,0x97,0xb5,0xcf,0xf8,0xfc,0xfb,0xf7,0xe9,
+  0x7b,0xfc,0xdf,0xf5,0xff,0xff,0xf7,0xff,0xe9,0xfe,0xff,0xff,0xe9,0xff,0xfd,0xff,
+  0xbf,0x5f,0xdf,0xf4,0xdd,0x7f,0x67,0xdb,0x76,0x7f,0xe9,0xdb,0x7e,0xdf,0xff,0xe7,
+  0xfb,0x7f,0xbd,0x37,0xff,0xf7,0xff,0xfd,0x7f,0xe4,0x5f,0xfb,0xfb,0xfe,0x7f,0xff,
+  0x7f,0xfe,0xe6,0xfd,0xfe,0x6f,0x9b,0xff,0xfb,0xbf,0x67,0xfe,0xff,0xbf,0xef,0xff,
+  0xfe,0x7f,0xbf,0xff,0x9f,0xff,0xfc,0xff,0xff,0x8f,0xfa,0xc7,0xff,0x6f,0x1b,0xd6,
+  0xfd,0xbf,0xef,0xf8,0xb6,0x3d,0x81,0x62,0xf9,0xf6,0x71,0x8f,0xfb,0xbe,0x6f,0xbb,
+  0xef,0xdb,0xfe,0xef,0xbf,0xe3,0xfb,0x7e,0xff,0xbf,0xe7,0xff,0xb9,0xbf,0x6f,0xfb,
+  0xfe,0xfd,0xfe,0xff,0xff,0xec,0xfb,0x3e,0xef,0xbf,0xfc,0xff,0xfe,0xfb,0xff,0xff,
+  0xff,0xff,0xf3,0xfe,0xff,0xff,0xff,0xbb,0xff,0xf3,0xff,0xff,0x3f,0xf9,0xbf,0xfb,
+  0xfe,0xfe,0xff,0xff,0xff,0xff,0xff,0xbf,0xef,0xf7,0xff,0xff,0xbf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfe,0xff,0x7f,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xef,0xff,0xc7,
+  0xff,0xd7,0xb5,0xfd,0x7f,0xdf,0xbb,0xf4,0xff,0x3f,0xc7,0xf3,0xf4,0xfd,0x1f,0x4f,
+  0xef,0xff,0x9b,0xff,0xbf,0xff,0x6b,0xff,0xfe,0xd1,0xfd,0xfd,0x7f,0xff,0xfb,0xff,
+  0xe2,0xff,0xfa,0x7e,0x9f,0xa7,0x7c,0xbf,0xf6,0x8f,0x23,0xe8,0xda,0x3e,0xbd,0xaf,
+  0x6a,0xff,0xdf,0xb7,0xdd,0xff,0x77,0xdf,0xe7,0xff,0xfa,0x3e,0xdd,0xaa,0xff,0xff,
+  0xbf,0xff,0x9f,0xff,0xdf,0xd7,0xe5,0xff,0xff,0xfe,0xd7,0xfd,0xff,0x5f,0xdf,0xf7,
+  0xe5,0xff,0x7f,0xb7,0xef,0x5f,0x7b,0xff,0xbb,0xff,0xef,0xff,0xf6,0xb7,0xf5,0xff,
+  0xff,0xff,0xff,0x93,0xff,0xeb,0xe3,0xe8,0xbe,0x7f,0x9f,0xe2,0xf8,0xbe,0x3f,0x0f,
+  0xe6,0xf0,0x9e,0x2f,0x9e,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe3,0xf8,
+  0xbe,0x7f,0x9f,0xe7,0xf2,0x7f,0xfd,0x7f,0x45,0xf7,0xff,0xff,0xbf,0xdf,0xff,0xfd,
+  0xeb,0x7f,0x46,0x91,0xf5,0xff,0xe7,0xff,0xff,0xff,0x1f,0x6f,0xfb,0xfe,0xfd,0x7f,
+  0xcf,0xf7,0xff,0xff,0x9f,0xfe,0xaf,0xff,0xaf,0xeb,0xea,0xff,0xff,0xf7,0xfb,0xff,
+  0xff,0xbf,0xef,0xeb,0xfa,0xfe,0xbf,0xff,0xff,0xff,0xff,0xef,0xfb,0xff,0x7b,0xdf,
+  0xaf,0xed,0xfe,0xff,0xff,0xff,0xff,0xf1,0xfe,0xfd,0xfd,0x7f,0xdf,0xff,0xf7,0xfd,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xbf,0xff,
+  0xff,0xff,0xff,0x7f,0xdf,0xff,0xff,0xff,0xf9,0x3f,0xfe,0x9f,0xa7,0xeb,0xff,0xde,
+  0xdf,0xad,0xff,0x7f,0xdf,0xf7,0xf7,0xf9,0xff,0xdf,0xe7,0xff,0xff,0x7f,0xdf,0xf7,
+  0xfd,0xbf,0x7f,0xf7,0xb7,0xfb,0x7f,0xff,0xf7,0xff,0x93,0xff,0xdb,0xf7,0x6d,0x9f,
+  0x2f,0xd1,0xdf,0xff,0x3f,0x27,0xdb,0xfe,0x3f,0xbf,0x6f,0xff,0xbf,0xbf,0xaf,0xeb,
+  0xff,0xfe,0xbf,0xff,0xff,0xff,0xfd,0xbf,0xff,0xfd,0xff,0xe2,0xff,0xfd,0x85,0xe9,
+  0xfa,0xee,0xbf,0xad,0xe8,0xfa,0xee,0x3f,0xad,0xe8,0xfa,0xb6,0xbd,0xeb,0xfa,0xbe,
+  0x1f,0xaf,0xe9,0xf8,0xbe,0xbf,0xab,0xeb,0x5a,0xbe,0xbf,0xaf,0xf4,0x9f,0xfe,0x5f,
+  0xef,0xf3,0xbf,0xff,0xbf,0xfd,0xfc,0xff,0xef,0x0d,0xd3,0xf4,0xbd,0xf6,0xff,0xf7,
+  0xdf,0xef,0xff,0xb3,0x7f,0xbf,0xf7,0xff,0xff,0xf7,0xff,0xff,0xc7,0xff,0x99,0x7d,
+  0x7b,0xff,0x3d,0xfb,0x7a,0xdf,0xaf,0x7c,0xfe,0xf9,0xde,0xfc,0xfd,0xff,0xf7,0x7f,
+  0xf7,0xeb,0xf7,0xdf,0xbd,0xad,0xff,0x7f,0xbf,0xff,0xdf,0xff,0xff,0xef,0xff,0xe6,
+  0x67,0xff,0xff,0xff,0xff,0x5f,0x7f,0xca,0xfd,0xb2,0xff,0x6d,0x7f,0xff,0x8e,0xef,
+  0xfd,0xff,0xff,0xff,0xfb,0xfa,0xbf,0xff,0xff,0xff,0xff,0xfe,0xff,0xef,0xfa,0xff,
+  0xff,0x45,0xfc,0xff,0x2f,0xda,0xfe,0xbf,0x1f,0xeb,0xfe,0xfd,0xb7,0xaf,0xfb,0xfa,
+  0xe7,0xbf,0xfd,0xf0,0xe4,0xad,0x83,0xef,0xe8,0xff,0xff,0xfd,0xff,0xfe,0xff,0xff,
+  0xff,0x7f,0xcd,0xff,0xff,0x7b,0xbf,0xec,0x7b,0xbf,0xff,0xbf,0xbf,0xdf,0xfe,0xff,
+  0xff,0x9f,0xff,0xef,0xff,0x7f,0xe7,0xd7,0xef,0x7f,0x7f,0xff,0xdf,0xff,0xf7,0x77,
+  0xff,0xff,0xff,0xf9,0x9f,0xff,0xbb,0xce,0xe3,0xfb,0xaf,0xef,0xbe,0xff,0xef,0xfe,
+  0x3f,0x8e,0xff,0xfb,0xee,0xfe,0xff,0x7e,0xff,0xaf,0xef,0xff,0xbe,0xef,0xfb,0xff,
+  0xff,0xff,0xdf,0x3f,0xff,0x15,0xfb,0xec,0x36,0xfd,0xee,0x7f,0xdf,0xfe,0xff,0xff,
+  0xfb,0xff,0xd7,0xfd,0xef,0xef,0xff,0x7f,0xfd,0x6d,0xdb,0xf6,0xef,0xbf,0x6f,0xff,
+  0xff,0xff,0xff,0xff,0x57,0xef,0xe0,0xff,0xdf,0xbe,0xf5,0x6e,0xef,0x76,0xff,0xf7,
+  0xfb,0xff,0xff,0xdf,0xbd,0xbb,0xff,0x8b,0xff,0xfd,0x6d,0xf6,0x76,0xde,0xfd,0xed,
+  0x5f,0xf7,0xff,0xfb,0xff,0xff,0xdf,0xfc,0x5f,0xf7,0x23,0x8f,0xf3,0x3b,0xfd,0xff,
+  0xfd,0xd3,0xff,0xff,0x5f,0x8d,0xf1,0xbe,0xff,0x4e,0xe1,0xd9,0xdd,0x2f,0xcf,0xfb,
+  0xf4,0xff,0xff,0xff,0xf3,0xff,0xff,0xff,0x7f,0x93,0xb7,0xf7,0xfd,0xff,0x7f,0xff,
+  0xff,0xdf,0xff,0x77,0xfe,0xff,0xba,0xfb,0xba,0x6f,0xe9,0xbf,0x7f,0xbf,0xf7,0xfd,
+  0xff,0x7d,0xdf,0xfe,0xff,0xff,0x7f,0xff,0xff,0xff,0xfa,0x77,0xfa,0x3f,0x1e,0xe3,
+  0x25,0xd5,0x76,0xfd,0xe7,0xed,0xfb,0xbf,0xd7,0xff,0xfe,0xdf,0xdf,0xb7,0xfd,0x38,
+  0x76,0x9f,0xff,0xf9,0xfb,0xff,0xff,0x6f,0xff,0xfb,0xff,0xff,0xc6,0xff,0xf7,0xbf,
+  0xb6,0xff,0xff,0xef,0xff,0x7e,0x7e,0x33,0xae,0xfb,0xff,0xff,0xa7,0x61,0xfe,0xff,
+  0xff,0xa7,0xf3,0xfe,0xff,0xb7,0xaf,0xff,0xff,0xff,0xef,0xff,0x7f,0x89,0xff,0xf7,
+  0xff,0xf7,0x5f,0xfe,0xfd,0x7f,0xff,0x5f,0xfd,0xff,0xfd,0x5f,0xff,0xef,0xff,0xff,
+  0x3f,0xdf,0xef,0xff,0x7f,0xbf,0xce,0xff,0xff,0xff,0xff,0xff,0x7f,0xdf,0xe8,0x0f,
+  0xf2,0xff,0xbf,0x5f,0xfb,0x7e,0xdf,0xbf,0xff,0x57,0x3e,0xdf,0xbd,0xfd,0xd3,0x3f,
+  0xf5,0x5c,0xff,0x3e,0xf7,0xfd,0x5c,0xfb,0xfe,0xff,0xff,0xef,0xfb,0xfe,0xdf,0xfc,
+  0xe6,0xbe,0x97,0xf3,0xe5,0xff,0x1b,0xcf,0xf7,0xff,0xfa,0x7f,0xcf,0xf7,0xfe,0xf9,
+  0x74,0xff,0xab,0xdf,0xaf,0xce,0xf3,0xcf,0xff,0x3f,0xdf,0xff,0xfc,0xff,0x7f,0xc7,
+  0xfd,0x7c,0xf7,0xfb,0xfe,0xbc,0xaf,0x2b,0xfa,0xf2,0xdf,0xfe,0x7a,0xcf,0xc6,0x9f,
+  0xed,0xed,0xff,0xff,0xff,0xfb,0xfa,0xfe,0xbf,0xfb,0xeb,0xca,0x7f,0xff,0xaf,0xef,
+  0xca,0x7f,0xbe,0x9b,0xff,0x5c,0xd7,0x35,0xcd,0x7f,0x7e,0x55,0x9f,0xcf,0x7b,0xfe,
+  0xd5,0xff,0xfc,0xff,0xef,0xfb,0xff,0xff,0x5e,0x57,0xff,0xed,0x7b,0x57,0xff,0xf7,
+  0xfd,0xf3,0x57,0xfd,0x93,0xff,0xed,0x32,0x4c,0x93,0x27,0xcb,0xfb,0x6d,0xff,0xff,
+  0x8b,0xa2,0x5e,0xbf,0x33,0xff,0x7f,0xdf,0xf6,0xcb,0xf7,0xdf,0xde,0xa5,0x0f,0xff,
+  0xfe,0xb7,0xbf,0xeb,0xff,0xf0,0x6f,0xfd,0xfe,0x5f,0xdd,0xec,0xf5,0x5a,0x7e,0xbf,
+  0xe7,0x51,0xdf,0x4f,0xfd,0x87,0x7f,0xf7,0xff,0xfe,0x79,0x58,0x7b,0xff,0xf5,0xf9,
+  0xff,0xff,0xde,0x67,0x7d,0x76,0xf6,0x27,0xff,0xbf,0xab,0xfa,0xda,0xb7,0xae,0x6f,
+  0xd6,0xfb,0xbf,0xbf,0x6a,0xfa,0xe6,0xfd,0xff,0xff,0xf5,0xde,0xad,0xeb,0xff,0xfe,
+  0xbe,0xad,0xff,0xfa,0xde,0xff,0xef,0x5f,0xb9,0xff,0xf7,0x69,0x5f,0x46,0xd3,0x35,
+  0xfd,0x3b,0x7f,0xf7,0xfd,0xe5,0x6a,0xff,0xdb,0xdb,0xb3,0xee,0xfb,0xb5,0xfd,0x7f,
+  0xef,0xd1,0xf5,0xff,0xff,0x7f,0xdf,0xf5,0xcf,0xff,0xbf,0xff,0xd7,0xfc,0xdd,0x2f,
+  0x6d,0xfb,0x76,0x9f,0x1f,0xed,0xf8,0xfd,0xff,0xff,0x6d,0xf7,0xfd,0x8f,0x7b,0xf3,
+  0xfd,0xff,0xb7,0x4f,0xf3,0xff,0xff,0x37,0xff,0xfb,0x7f,0xf7,0xfe,0x79,0xff,0xaf,
+  0x9e,0xff,0xff,0xbe,0x6f,0xdf,0xfe,0xff,0xfe,0x7f,0xff,0xfe,0xef,0xe7,0xff,0xfe,
+  0xfc,0xaf,0xff,0xfb,0xe6,0xbd,0xaf,0xff,0xef,0xff,0xfd,0xff,0xf8,0x5f,0xfe,0x75,
+  0xbb,0x65,0xd9,0xd6,0xef,0x99,0x6f,0xdb,0xb6,0xff,0x8f,0x6f,0xf9,0xbf,0x9f,0xe7,
+  0xfb,0x16,0xe5,0xbf,0x6f,0x99,0xb6,0xef,0xbf,0xef,0xfb,0xfe,0xff,0xf8,0x5b,0xff,
+  0xfb,0xff,0x6f,0xb3,0xff,0xff,0xfe,0xef,0x9b,0xfd,0xff,0xfe,0x7f,0xff,0xff,0xff,
+  0xff,0xfb,0xff,0xf3,0xbf,0x7f,0xf7,0xed,0xfb,0xff,0xff,0x3f,0xff,0xf3,0xfd,0xab,
+  0xff,0xfe,0xff,0xfb,0xed,0xff,0xff,0xff,0xef,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfe,0x5f,0xbf,0x1f,0xcf,0xf1,0xf4,0xf9,0xff,0x47,0xd7,0xf7,0xff,0xff,0xe7,0xdf,
+  0xf4,0x7e,0x47,0xd1,0xf4,0x7d,0x7e,0x5f,0xf5,0xf4,0x7d,0x7f,0xff,0xd7,0xff,0xfb,
+  0xff,0xfa,0xaf,0xfd,0xe3,0x7a,0xfe,0xbe,0xbf,0xb7,0x6a,0xbe,0xad,0x9f,0x77,0xcc,
+  0xfe,0x76,0xbf,0xeb,0xfa,0xf4,0xbf,0xa2,0xec,0xf7,0xfe,0xa9,0xaa,0xff,0xda,0xbf,
+  0xff,0xf2,0xff,0xfd,0xff,0xfd,0xfd,0x7b,0xfd,0xd7,0xff,0xfd,0x5b,0xde,0xff,0xfd,
+  0xeb,0xfb,0x7f,0xd7,0xb9,0x7f,0x55,0xd5,0x75,0xfd,0x7f,0xcd,0xd7,0x75,0xff,0xff,
+  0x5f,0xff,0xbf,0xff,0xf8,0xbf,0xff,0x9e,0x2f,0x9d,0xe2,0xf8,0xfe,0x2f,0x9b,0xe7,
+  0xf8,0xfe,0x37,0x9b,0xe2,0x69,0xa7,0x8b,0xa2,0xf8,0xbe,0x3f,0x8f,0xe2,0x78,0xfe,
+  0x7f,0x8b,0xe7,0xf9,0xfe,0x7f,0xe7,0xff,0xf1,0xfc,0xff,0x1f,0xdf,0xf7,0xf5,0xfd,
+  0x7f,0xcf,0xd3,0xfe,0xfd,0x3f,0xcd,0xfc,0xff,0x77,0x4f,0xd7,0xf5,0xff,0xff,0x5f,
+  0xd7,0xff,0xfd,0x7f,0xff,0xff,0xff,0xe0,0xff,0xfe,0xff,0xbf,0xef,0xeb,0xfe,0xfa,
+  0xbf,0xef,0xe9,0xfa,0x7e,0xdf,0xa7,0xf9,0xef,0xbf,0xef,0xab,0xfa,0xfe,0xff,0xff,
+  0xeb,0xfa,0xff,0xff,0xaf,0xbf,0xff,0xff,0xfd,0x1f,0xff,0xdf,0xf3,0xff,0xfd,0x7f,
+  0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xff,0xf5,0xff,0xff,0xbb,0xff,0xff,0x3f,0x5f,0xd7,
+  0xff,0xff,0x7f,0xdf,0xff,0xff,0xff,0xff,0x5f,0xff,0x93,0xff,0xfb,0x7a,0x5f,0xb7,
+  0xaf,0xff,0xbb,0xdf,0xb7,0xa7,0xf9,0xff,0xde,0x9f,0xf6,0xff,0x7f,0xdb,0xa7,0xfb,
+  0x7b,0xdf,0xff,0xad,0xef,0x7f,0xff,0xf3,0xff,0xeb,0x7f,0xf8,0x3f,0xbe,0xbf,0xef,
+  0xfd,0xf7,0x7d,0xbf,0x6e,0xff,0xf2,0xfd,0x3f,0x6f,0xfb,0xfc,0xff,0xf7,0xff,0xf4,
+  0xfd,0x3f,0xef,0xff,0xf2,0xec,0xbf,0xff,0xd3,0xf4,0xfd,0x3d,0xfe,0x2f,0xff,0xfa,
+  0x7e,0xbf,0xaf,0x6b,0xfa,0x7e,0x8f,0xae,0xeb,0x5a,0xb6,0xaf,0xa7,0xeb,0x5e,0xbf,
+  0xad,0x6b,0xba,0xbe,0x3f,0xaa,0xe1,0x3a,0xde,0xbd,0xa7,0xeb,0xd2,0xff,0x61,0xff,
+  0xff,0xd9,0x7b,0xff,0xff,0x73,0xfc,0x3f,0xf7,0xff,0x7f,0x7d,0x37,0x7f,0xb3,0x7f,
+  0xfb,0xdd,0xf1,0xff,0x7d,0xff,0xfc,0xfd,0xdc,0xff,0xff,0xff,0x6f,0xbc,0xff,0xfa,
+  0x17,0xf7,0xfe,0xfe,0x7f,0xf7,0xf9,0xf1,0xf6,0xff,0xf7,0xdf,0xfa,0xfc,0xdc,0xbb,
+  0xeb,0xff,0xfb,0xbc,0xbd,0xdb,0xfc,0xff,0xf7,0xdf,0xff,0xff,0xdf,0xff,0xf7,0xed,
+  0xfe,0xb7,0xfb,0xfa,0xfd,0xff,0xfa,0xfb,0xbd,0xf3,0xff,0xef,0xfe,0xfc,0xe3,0xff,
+  0xff,0xdf,0x9e,0xbf,0xf7,0xfd,0xff,0xff,0xff,0xef,0xff,0xcf,0xff,0xff,0xff,0xff,
+  0xcf,0xff,0xe4,0x5f,0x9f,0xbe,0x3f,0xef,0xf9,0xf8,0xff,0xff,0xf7,0x63,0xfe,0xde,
+  0xaf,0xef,0x65,0xff,0x9f,0xaf,0x69,0xfb,0xff,0xf3,0xe3,0xeb,0xda,0xf7,0xff,0x8d,
+  0xff,0xfb,0x7f,0xff,0x5f,0xff,0xff,0xef,0xff,0xd6,0xde,0xff,0xbf,0xdf,0xfe,0xfd,
+  0x7f,0x57,0xf7,0xff,0xe7,0xff,0xdd,0xf7,0xbe,0xdf,0xff,0x7f,0xff,0xbf,0x6e,0xff,
+  0xeb,0x7f,0xff,0xdf,0xfe,0xb9,0xff,0xff,0xbf,0xfa,0xbf,0xff,0xed,0xbf,0xef,0xd6,
+  0xfe,0xff,0x7e,0xe7,0xba,0xff,0xeb,0xde,0xfb,0x3f,0xff,0xbf,0xf6,0x1f,0xbd,0xfb,
+  0x7f,0x7f,0xff,0xff,0xff,0xff,0xfa,0x7f,0xfb,0xff,0x6e,0xef,0xf5,0xfd,0x7f,0xfb,
+  0xff,0xbe,0x7d,0xf7,0x2f,0xdf,0xfe,0xfc,0xff,0xbb,0xfe,0xff,0xbf,0xff,0xdf,0xff,
+  0xfc,0xff,0xff,0x7b,0xff,0xdf,0xbf,0xfe,0xaf,0xfb,0xfd,0x7b,0xbf,0xff,0xf7,0xff,
+  0x5f,0xff,0x9b,0xff,0xbb,0xef,0xfb,0x5f,0xef,0xbe,0xf7,0xff,0xf7,0x7d,0x7f,0xde,
+  0xdd,0xf7,0xbf,0xbf,0xff,0xff,0xfd,0xff,0xed,0xd5,0x7f,0xfb,0x5c,0xfa,0x2e,0xbf,
+  0xef,0xdc,0x9e,0x3f,0xcf,0xa3,0xf3,0xb6,0xbe,0xcf,0x74,0xf5,0x2f,0xff,0xf1,0x58,
+  0xfe,0xff,0x7f,0xd3,0xff,0xef,0xff,0xff,0xff,0xff,0xfe,0xaf,0xfb,0x7f,0x5f,0xf7,
+  0xff,0xbf,0xff,0xdf,0xf7,0x33,0x7f,0x79,0xff,0xfb,0xeb,0x7e,0xdb,0xfd,0xff,0xff,
+  0x7f,0xdf,0xff,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0x13,0x7a,0xf7,0xba,
+  0xfe,0x67,0xde,0x7e,0xfb,0xde,0xff,0xdd,0xe7,0xef,0xcd,0x37,0xfe,0xf8,0xde,0xfe,
+  0xff,0xd3,0xeb,0xff,0xf7,0xff,0xeb,0xff,0xf7,0xff,0xfb,0xff,0xff,0xee,0xef,0xff,
+  0x7f,0xf7,0xef,0xff,0x3a,0xbf,0xfd,0xee,0xf7,0x7e,0xee,0xbf,0xfd,0xff,0x7f,0x77,
+  0x2e,0xff,0xff,0xde,0xbf,0xab,0xfe,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xfb,0x1f,
+  0xff,0x7f,0xff,0xf3,0xfd,0xff,0xff,0xff,0xfb,0xff,0xff,0x5f,0xff,0xff,0xff,0xff,
+  0xff,0xef,0x6f,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0x7f,0xff,0xfb,0xff,
+  0x80,0xff,0x5c,0xcb,0xdf,0xf7,0xb3,0xfc,0xfb,0xde,0xfd,0x33,0x2f,0xff,0xff,0xdf,
+  0xb6,0x7f,0x93,0xcc,0xf1,0xec,0xfb,0xfe,0xdf,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xcf,0x6b,0xe7,0xfa,0x1a,0x8f,0xf7,0x7f,0xdf,0x7b,0xdf,0x3f,0xbd,0xff,0xff,
+  0xdf,0xf7,0xeb,0xff,0xff,0xaf,0xbd,0xbf,0xdf,0xdf,0xf7,0xfc,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xd6,0x4f,0x7f,0xa9,0x5f,0xd2,0xf4,0xfd,0x7f,0x4f,0x9a,0xfe,0xed,0x3f,
+  0x5f,0x9b,0xde,0xff,0xfe,0x7f,0x3e,0xaf,0xbf,0xef,0x1f,0xfe,0xf9,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xfb,0xcd,0xbf,0x95,0xcd,0xff,0x5e,0xdf,0xff,0xe5,0x73,0x5f,0xff,
+  0xf5,0xef,0xff,0x7f,0xdf,0xff,0xff,0xbe,0x57,0xf7,0xff,0x79,0xff,0xdf,0x97,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdb,0x3f,0xff,0xff,0xac,0xdd,0xe3,0x7d,0xfd,0x35,0x4f,
+  0xfb,0xfe,0x92,0x2f,0xdb,0xfb,0xff,0xff,0xfc,0xff,0xfe,0xff,0xb6,0xcb,0xfb,0xfe,
+  0xb7,0xff,0xff,0xff,0xff,0xff,0xff,0x16,0xff,0xfd,0xf5,0x7f,0xfd,0x6f,0x75,0xe7,
+  0x59,0xff,0xf7,0xd5,0xfd,0x61,0xdf,0x77,0xfe,0xff,0xff,0xf7,0xdd,0xfd,0xe9,0x5f,
+  0x77,0xdc,0xaf,0xff,0xff,0xff,0xff,0xff,0x70,0x7f,0xfa,0xde,0xbf,0xfd,0xef,0xdf,
+  0xd2,0xfd,0x2f,0xef,0xfa,0xfe,0xfd,0xaf,0xef,0xff,0xdf,0xfd,0x6b,0xfb,0xfe,0xff,
+  0xaf,0xef,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0x13,0xff,0x5f,0xd5,0xfb,0xff,
+  0xb8,0xfc,0x51,0xa5,0xff,0xff,0x47,0xf7,0x15,0xcd,0xfa,0xfe,0xfe,0xe1,0x7f,0x7f,
+  0xf3,0xf5,0xfd,0xff,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0x9b,0xfe,0xdf,0xff,0x47,
+  0xd3,0x77,0xff,0xff,0x47,0xf3,0x7e,0xdd,0x7f,0x6f,0xfb,0x7f,0xff,0xdf,0xdf,0xff,
+  0xff,0xb7,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,0xef,0xff,
+  0xe7,0xf8,0xbf,0xff,0xf9,0xee,0x7d,0xbf,0xe7,0xbb,0xfe,0xbf,0xbf,0xef,0xfb,0xff,
+  0xff,0xff,0xf9,0xf7,0xff,0xff,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,0xfe,0x87,0xfb,
+  0xef,0x59,0xfe,0x39,0x9f,0x6f,0xd9,0xfe,0xf9,0xbf,0x67,0x9b,0xbe,0xfb,0xb3,0x7b,
+  0xfe,0x7f,0xbf,0xed,0xdb,0xf6,0xff,0xbf,0x6d,0xfb,0xfe,0xff,0xbf,0x6f,0xff,0xa1,
+  0xbf,0xff,0xfb,0xef,0xf1,0xbf,0xcf,0xf7,0xfe,0xf9,0xbf,0x6f,0xf3,0xfe,0xff,0xff,
+  0xcf,0xfe,0xff,0xff,0xef,0xf3,0xe6,0xff,0xff,0x6f,0xbf,0xff,0xff,0xff,0xcf,0xff,
+  0xdc,0x3f,0xff,0xfe,0xfb,0xff,0xdf,0xfb,0xff,0xff,0x7f,0xdf,0xfb,0xfe,0xfe,0xff,
+  0xff,0xfb,0xff,0x7f,0xff,0xf7,0xfe,0xff,0x7f,0xff,0xef,0xff,0xff,0xff,0xff,0xef,
+  0xff,0xff,0xe5,0xff,0xf7,0xfe,0x7f,0x9f,0xcf,0xf7,0xb4,0xed,0x7f,0xdf,0xd1,0xec,
+  0x7f,0x7f,0x5f,0xe5,0x7b,0x1f,0xff,0xd7,0xf7,0xff,0xff,0xfe,0xd7,0xff,0xfd,0x7f,
+  0xff,0xb7,0xff,0xf4,0xff,0xfe,0x77,0xcf,0xfb,0xcb,0xfe,0x7e,0xaf,0xaa,0x49,0xfa,
+  0xbf,0xbf,0xe7,0xc9,0xf6,0x8f,0xaf,0xff,0xfa,0x7d,0xcb,0x67,0xff,0xfa,0x3f,0xff,
+  0xa7,0xff,0xfb,0x7f,0xff,0x1f,0xff,0xdf,0xdf,0xbf,0xff,0x7b,0xdf,0xd7,0xb5,0xff,
+  0x77,0x5e,0xff,0xf5,0xff,0xff,0x95,0xfc,0xff,0xff,0xfe,0xdf,0xff,0xdf,0xff,0x5f,
+  0xff,0xe5,0xff,0xff,0xdf,0xff,0x0b,0xff,0xfb,0xe6,0x71,0xda,0x2f,0x9b,0xe2,0xe8,
+  0xfe,0x2f,0x89,0xe7,0x78,0xbe,0x7f,0x9a,0xe8,0xbe,0x7f,0x9f,0xe7,0xf9,0xbe,0x7f,
+  0x8b,0xe7,0xf8,0xbe,0x7f,0x8f,0xe7,0xf9,0x7f,0xff,0x3f,0xef,0xb3,0xfc,0x7f,0x1f,
+  0x47,0xd7,0xf4,0xfd,0x3f,0xc7,0xd3,0xf4,0xff,0x5d,0xf7,0xfe,0xfd,0xff,0xff,0xff,
+  0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0x7f,0xfe,0x8f,0xff,0xe7,0xff,0xfa,0xfa,0xbf,
+  0xef,0xeb,0xea,0xfe,0x9f,0xaf,0xff,0xfe,0x7e,0x9f,0xef,0xeb,0xff,0xff,0xaf,0xff,
+  0xfe,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xbf,0xff,0xd4,0xff,0xfd,0xff,0xbb,0xed,
+  0xf7,0xff,0xff,0x77,0xdf,0xf7,0xfc,0xff,0xff,0x5f,0xff,0xf9,0x7f,0xdf,0xfb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xf8,0xbf,0xff,0x9f,0xfd,
+  0xff,0x7a,0x7f,0x9f,0xa4,0xef,0x7e,0x7e,0x97,0xf7,0xe9,0xff,0x7f,0xbd,0xef,0xff,
+  0x7f,0xff,0xfd,0xfb,0xff,0xff,0xf7,0xff,0xff,0xff,0xfe,0xff,0xff,0x47,0xff,0xfe,
+  0xf6,0xbf,0xff,0xcf,0xfc,0xf6,0xfd,0xff,0x76,0xdf,0xf6,0xfd,0xbf,0x2f,0xff,0x7f,
+  0xff,0xff,0xfd,0xbf,0xfd,0xff,0x6f,0xcb,0xff,0xff,0xff,0xff,0xff,0xff,0xfa,0xff,
+  0xef,0xaf,0xea,0xfa,0xbe,0xbf,0xae,0xe9,0xda,0xae,0x8f,0xae,0xeb,0xb2,0xf6,0xbd,
+  0xeb,0xfa,0x7e,0x8f,0xa7,0xeb,0x3a,0xfe,0x9d,0xaf,0xeb,0xfa,0xfe,0xbf,0xaf,0xf6,
+  0x1f,0xef,0xf7,0xc1,0xff,0xfb,0x1f,0xcf,0xdb,0x7f,0xff,0xf7,0x8f,0xdf,0xe7,0x7f,
+  0xf6,0xff,0x6f,0xff,0x9f,0xff,0xf3,0xff,0xdc,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xc9,0xff,0xdf,0xea,0xfd,0xf2,0xdf,0xcb,0xfd,0xf7,0xff,0xff,0xd3,0xf7,0xdf,
+  0xee,0xff,0xff,0x7f,0xfd,0xbf,0xde,0xff,0xdf,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xeb,0x7d,0xff,0xf7,0xff,0x7e,0xfa,0xfb,0xea,0xfd,0xfe,0xff,0xff,0xef,
+  0xef,0xbb,0xef,0x3d,0xff,0xfb,0x6f,0xbf,0xfc,0x4f,0xfe,0xff,0xff,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xfe,0x25,0xbd,0xff,0xab,0xfe,0xbd,0xdf,0xa7,0xeb,0xaa,0xf6,0x27,
+  0xa7,0xe7,0x79,0x97,0xff,0xe3,0xd8,0xf7,0xfe,0xb7,0xeb,0xdf,0xdf,0xdd,0xaf,0x3f,
+  0xf8,0xff,0xfb,0xff,0xff,0xf5,0xff,0x5f,0xf7,0xbd,0xff,0xff,0xf5,0xf7,0x7f,0xeb,
+  0x6f,0xde,0xff,0xff,0xff,0xff,0xfd,0xfe,0xff,0xff,0xed,0xfd,0x97,0xff,0xbf,0xed,
+  0xff,0xff,0xbe,0xff,0xff,0xbf,0xfa,0x9f,0xff,0x37,0x3e,0xef,0x6c,0xef,0xaf,0x87,
+  0xef,0xb6,0x7e,0xf2,0xff,0x7f,0xfc,0xfe,0x7e,0xef,0xfe,0xff,0xfd,0xef,0xff,0xde,
+  0xfe,0x3f,0xfd,0xff,0xff,0xef,0xff,0xff,0x14,0xfb,0x9b,0x77,0xfd,0x3f,0x7f,0xcf,
+  0xa7,0xff,0xff,0x3f,0xdf,0xff,0xff,0xff,0x5f,0xde,0xfb,0xe3,0xe7,0xfb,0xf3,0xbd,
+  0xbf,0x3f,0xfb,0xff,0xff,0xff,0xff,0xfe,0xff,0xf6,0xff,0xfb,0xc7,0xb7,0xff,0xfb,
+  0x7b,0xfe,0xeb,0x7f,0xfb,0xfe,0xdf,0xff,0xff,0xff,0xd9,0xf5,0x7f,0xfd,0xff,0xfb,
+  0xaf,0xbf,0xfb,0xff,0xff,0xf7,0xfb,0xff,0xdf,0xff,0xfc,0x1f,0xff,0x3f,0xff,0x7f,
+  0xf4,0x7f,0x37,0xce,0xd6,0xf7,0xf7,0x3f,0xcf,0x73,0xff,0xf6,0x4f,0x7f,0xbf,0xff,
+  0xfd,0xcf,0xb3,0xfc,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xfd,0xd3,0xff,0xf6,0xe7,
+  0xbf,0xff,0xef,0xf7,0x3d,0xf6,0xf7,0x7f,0xf7,0xfd,0xef,0x7d,0xff,0xed,0xdf,0xfe,
+  0xff,0x7f,0x7d,0xff,0x7f,0xdd,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xf8,0x3b,0xee,
+  0xfb,0xcc,0xd7,0xf5,0xfe,0xbf,0x9f,0xfb,0xfe,0xc8,0x3c,0xbb,0xe5,0xfe,0xeb,0xbe,
+  0xd7,0xff,0xdb,0xff,0x9b,0xab,0xb9,0xef,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0xed,
+  0xff,0xff,0xff,0xff,0xff,0xb6,0x6f,0xdf,0xfa,0xee,0xaf,0xee,0xff,0xef,0xf7,0xff,
+  0xff,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xb5,0xff,0xff,0xfd,0xff,0xff,0xaf,0xfb,0xfd,0xff,0xff,0xff,0xfd,0x5f,0xff,0x7f,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xfb,0xff,0xf7,0xef,0xff,0xff,0xff,0xff,
+  0xfe,0xfe,0x8f,0xf5,0xff,0xb3,0xef,0xff,0x3f,0xef,0xbe,0x7c,0xff,0x7e,0xff,0xfd,
+  0xff,0x9b,0x27,0xbf,0xfc,0xff,0xff,0xcf,0xff,0xef,0x7b,0xc7,0xcf,0xff,0xfc,0xff,
+  0xff,0xff,0xfd,0x44,0xac,0xff,0xff,0x7c,0xf9,0xee,0x7f,0xf7,0xcf,0x3f,0x3f,0xde,
+  0x3f,0xfc,0xf9,0xde,0xb7,0xe6,0xcf,0xfe,0xbd,0xff,0xfd,0xff,0xfc,0xcf,0xff,0xff,
+  0xdf,0xff,0xff,0xfd,0x44,0xd5,0xff,0xf3,0xff,0xaf,0xff,0x1f,0xb5,0xfc,0xff,0xfb,
+  0xfb,0xff,0xff,0xef,0xee,0xfe,0xff,0xef,0xff,0xff,0xf5,0xfd,0x2f,0x2b,0x9e,0xbf,
+  0xff,0xff,0xff,0xff,0xe7,0xbc,0x5b,0xf9,0xfe,0x7f,0xf5,0xe7,0xf9,0xff,0xff,0x3f,
+  0xcd,0xf9,0x5f,0xff,0xf7,0xff,0x7f,0xdf,0x37,0xff,0xff,0xfe,0x7f,0x95,0xe5,0x7b,
+  0x7f,0xff,0xff,0xff,0xff,0xfe,0xfd,0xf1,0x7f,0xdf,0x7f,0x6c,0xbd,0x7f,0xff,0x7a,
+  0xff,0xff,0x3f,0xcb,0xb7,0xdf,0x93,0x2f,0xfb,0x5f,0xbb,0x2f,0xff,0xff,0xed,0xff,
+  0xaf,0x8f,0xb7,0xff,0xff,0xff,0xff,0xef,0xea,0x6d,0xe3,0xe6,0xff,0xd5,0xef,0x7b,
+  0xff,0x5f,0xff,0x87,0x61,0xdf,0xff,0xdd,0xe5,0x7b,0x7f,0xfd,0xe7,0x7f,0xff,0xff,
+  0xff,0xf5,0x51,0xda,0xff,0xff,0xff,0xff,0xff,0xf7,0xcd,0xff,0xfd,0xff,0xda,0xfb,
+  0xfe,0xbf,0xeb,0xff,0xf6,0xbd,0x2f,0xfe,0xfe,0xd0,0xbe,0xcf,0xff,0xda,0xbf,0xff,
+  0xfb,0xfa,0xde,0xbf,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xb5,0xbf,0xfd,0xff,0xfd,
+  0x5e,0x9f,0xf7,0x7d,0x7f,0xfc,0x57,0xa5,0xff,0xff,0x66,0xd7,0xfd,0xdf,0xff,0xdf,
+  0xff,0xfd,0xff,0x5f,0xd7,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x17,0xe7,0xf3,
+  0x7f,0xff,0xb7,0xed,0xf7,0xfc,0xdf,0x9f,0xe7,0xf1,0xf5,0xfd,0x27,0xed,0xf4,0x7f,
+  0x9f,0xed,0xf9,0xfc,0x7f,0x37,0xcd,0xfb,0xfe,0xff,0xff,0xff,0xff,0xfe,0x77,0xff,
+  0xff,0xff,0xff,0xf9,0xfe,0x7b,0x9f,0x7f,0xff,0xff,0xfd,0xfe,0x7f,0xaf,0xfe,0x7e,
+  0xa7,0xf9,0xfe,0xff,0xbf,0x7f,0xdb,0xfe,0xff,0x8f,0xfb,0xff,0xff,0xff,0xff,0xac,
+  0x7f,0xfe,0xf5,0xb5,0x6f,0xfb,0xfe,0x7d,0xbf,0x6f,0xfb,0xfe,0xff,0x8d,0x67,0xfb,
+  0x57,0x9d,0x6f,0xfb,0x66,0xe5,0xbf,0x6f,0x1b,0x46,0xd5,0xbf,0xef,0xfb,0xfe,0xff,
+  0xfb,0x9f,0xfe,0xff,0xbf,0xff,0xfb,0xff,0xf1,0xbe,0x6f,0xff,0xfe,0xfb,0xfe,0xef,
+  0xff,0xfe,0xbf,0xef,0xff,0xf6,0xff,0xbe,0x6f,0xbb,0xfe,0xff,0xbf,0xff,0xff,0xff,
+  0xff,0xfd,0x8b,0xff,0x7f,0xef,0xff,0xfd,0xff,0xff,0xdf,0xfb,0xff,0xff,0xbf,0xff,
+  0xef,0xff,0xfe,0xff,0xfb,0xff,0xff,0x7f,0xbf,0xef,0xfb,0xfe,0xff,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xf3,0x7f,0xff,0xff,0xef,0xff,0xbd,0xed,0x2f,0x7f,0xf9,0xbf,0xff,
+  0x7f,0xe7,0xd3,0xff,0xfe,0xe7,0xf7,0xff,0xff,0x7f,0xde,0xff,0xf5,0xfb,0x7f,0xdf,
+  0xff,0xff,0xff,0xff,0xff,0x4f,0xff,0xf3,0xfb,0xf7,0x7f,0xdd,0xab,0x7a,0xbf,0xff,
+  0xdd,0xa2,0x7e,0xfa,0xbf,0xdf,0xfe,0xfa,0x7d,0xdd,0x37,0x6e,0xbe,0xae,0xaf,0xa7,
+  0xcd,0xff,0xff,0xff,0xff,0xff,0xd0,0xff,0xff,0xef,0xfb,0x7f,0xff,0x3d,0xfd,0x77,
+  0xf7,0xff,0xf5,0xff,0xff,0x5f,0xd7,0xf9,0x7f,0xfe,0xff,0xf5,0xef,0x77,0xff,0xd7,
+  0xf5,0xff,0x7f,0xff,0xff,0xff,0xff,0xf7,0xbf,0xfe,0xfe,0x6f,0x9f,0xe7,0xe9,0xbe,
+  0x6f,0x9f,0xe7,0xf8,0xbe,0x77,0x8f,0xe2,0xf9,0xa7,0x9f,0xc7,0xf8,0xbe,0x2f,0x9b,
+  0xc2,0xf8,0xba,0x3f,0x9f,0xe7,0xf9,0xfe,0x7f,0x67,0xff,0xff,0xfe,0x7f,0x9f,0xfd,
+  0xd7,0xff,0xff,0xff,0xcf,0xf7,0xfe,0xfd,0x1f,0xef,0xfe,0xff,0x7e,0x6f,0xf7,0xfd,
+  0xfd,0x7e,0x5f,0xf7,0xf5,0xff,0xff,0xff,0xff,0xef,0xf8,0xff,0xbf,0xff,0xbf,0xff,
+  0xff,0xea,0xff,0xff,0xff,0xfb,0xfa,0xff,0xff,0xbf,0xff,0xff,0xff,0xaf,0x6d,0xfb,
+  0xfe,0xff,0xaf,0xeb,0xfa,0xfa,0xbf,0xff,0xff,0xff,0xff,0xfd,0x8f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0x5f,0xf7,0xf7,0xff,0xbf,0xdf,0xfb,0xf5,0xfd,0x3f,0xb3,0xff,0xfd,
+  0x7f,0x5f,0xf7,0xff,0xef,0x7f,0xdd,0xf7,0xff,0xff,0xff,0xff,0xff,0x93,0xbf,0xfd,
+  0x7e,0x7f,0xdf,0xf7,0xeb,0x7e,0xdf,0xdf,0xf7,0xfb,0x7f,0xde,0x97,0xa7,0xfb,0x5f,
+  0xdd,0xa7,0xe9,0xfa,0xdf,0xb7,0xad,0xef,0xfb,0xff,0xff,0xff,0xff,0xdf,0xf1,0x7f,
+  0xfd,0xff,0x4f,0x73,0xb6,0x7d,0xaf,0x6f,0xd9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x67,0xfd,0xf7,0xff,0xff,0xff,0x5b,0xf7,0x7c,0x9f,0xff,0xff,0xff,0xff,0xff,0xee,
+  0x2f,0xff,0xba,0xf6,0xbf,0xaf,0x6a,0xda,0xfe,0x37,0xa7,0xcb,0x72,0x7e,0xbf,0xab,
+  0xeb,0x56,0xbf,0xae,0xeb,0x7a,0xfe,0xb7,0x8e,0xeb,0xba,0xfc,0xbf,0xaf,0xeb,0xfa,
+  0xff,0x49,0xff,0xff,0xdb,0x3f,0xfb,0xdf,0x74,0xf8,0xdf,0x37,0xfb,0x3f,0xff,0x6e,
+  0xcd,0xf3,0xfd,0x16,0xdd,0xff,0xfc,0xf7,0xff,0x37,0xbf,0xff,0xef,0xff,0xcf,0xff,
+  0xff,0xff,0xfe,0x9f,0xfd,0xff,0xbf,0xfd,0xff,0xef,0x7f,0xff,0xbe,0xed,0xdf,0xff,
+  0x7f,0xef,0xb5,0x3b,0xdf,0x7f,0xff,0x7f,0xff,0x7d,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0xf7,0x7e,0x64,0xff,0xff,0xbc,0xfb,0xcf,0xf7,0x6b,0x6f,0xbb,0xdf,0xff,
+  0xfe,0xfd,0xaf,0x5f,0xc7,0x9b,0xfe,0xfe,0xfb,0x8d,0xff,0xfb,0xfa,0xff,0xfe,0x7f,
+  0xfc,0xff,0xff,0xff,0xff,0xee,0x7f,0x78,0xbf,0xf7,0x8f,0xe5,0xfa,0xfe,0xbf,0xa7,
+  0x6f,0xfe,0xff,0xff,0xad,0xdf,0xfe,0x3c,0xff,0xe3,0xff,0xf7,0xfd,0xa6,0xe9,0xfa,
+  0xfe,0xbf,0xff,0x7f,0xff,0xff,0xef,0x5f,0xfd,0x7f,0xbf,0xd7,0xdf,0xf5,0x6f,0xfb,
+  0x75,0xff,0xbf,0x7f,0xff,0xf6,0x7f,0xfb,0xdf,0xef,0xfe,0xff,0xfb,0xff,0xf5,0xd7,
+  0x7d,0xdf,0xfb,0xbf,0x7f,0xff,0xff,0xff,0xc9,0xff,0xff,0xbc,0x57,0x3f,0xef,0xfd,
+  0x5a,0xf7,0x9a,0xcf,0x7b,0xbe,0x7f,0xdf,0xcb,0xec,0xff,0xff,0xed,0xfb,0xaf,0x5f,
+  0xff,0xbf,0x6f,0x7b,0xff,0xff,0xfd,0xff,0xff,0xfb,0x7f,0xff,0x9f,0x7f,0xdf,0xff,
+  0xbf,0xfe,0xbf,0xcf,0xff,0xbc,0xff,0x7f,0xd7,0xf5,0xe9,0x77,0xfb,0xf3,0xb8,0xbf,
+  0x5f,0xdf,0xfe,0xff,0xff,0xef,0xff,0x7f,0xff,0xff,0xff,0x4e,0xbf,0xfd,0xda,0xde,
+  0xbf,0xd7,0x7f,0xff,0xf6,0xff,0xef,0x6f,0xcc,0xff,0xbf,0xff,0x9b,0xff,0xdd,0xbf,
+  0xbf,0xff,0xfe,0xff,0xef,0xfd,0xff,0xdf,0xff,0xfe,0xff,0xff,0xc1,0x76,0xff,0x7c,
+  0xfb,0x3f,0xfd,0xd3,0xd8,0xfd,0xaf,0xcc,0xf3,0x7c,0xf6,0x3b,0x9f,0xf4,0xbb,0x37,
+  0xff,0xef,0xd0,0x7f,0x3f,0xff,0xb3,0xff,0xef,0xff,0xff,0xff,0xff,0xfc,0x3e,0xff,
+  0xff,0xdc,0xe7,0xdf,0xef,0x7d,0xf7,0x77,0xed,0xf7,0x79,0xdf,0xf7,0xfb,0xff,0xdf,
+  0xf7,0xdf,0xff,0xff,0xde,0x0d,0xff,0xfd,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0x07,
+  0xff,0xbb,0xfb,0xff,0xe6,0xdf,0x46,0x6b,0xff,0xfb,0x9f,0xef,0xfb,0xce,0x73,0xcb,
+  0xb9,0xde,0xff,0xfe,0xbf,0xfd,0xf7,0x7e,0xdf,0xef,0xbf,0x7f,0xff,0xff,0xff,0xfe,
+  0xee,0x7f,0xff,0x4e,0xbb,0xef,0x73,0x96,0xfe,0xb2,0xff,0xf3,0xbf,0xd5,0xbf,0xef,
+  0xfd,0xff,0x3f,0x2e,0x7f,0xdf,0xff,0xbf,0xd7,0xf7,0xf2,0xff,0xef,0xff,0xff,0xff,
+  0xff,0xdb,0x97,0xff,0xff,0xff,0xfb,0xfe,0xff,0xd3,0xff,0xff,0xff,0x7f,0xff,0xef,
+  0xf5,0x7d,0xff,0xef,0xff,0xff,0xff,0xff,0xd7,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xa8,0xff,0xfd,0xfb,0xff,0xdd,0x73,0xff,0x1f,0x35,0xcf,0xbf,0xff,
+  0xfb,0xff,0xcc,0xf3,0xff,0xff,0xfc,0xb1,0xff,0xff,0xff,0xc7,0xf7,0xec,0xfb,0xff,
+  0xdf,0xff,0xff,0xff,0xc4,0x4b,0xfc,0xff,0xbf,0xff,0xa7,0xfd,0xff,0xff,0xe7,0xf7,
+  0xfc,0xf3,0x3f,0xf5,0x9e,0xff,0xff,0xff,0x91,0xff,0xff,0x9f,0xfb,0xff,0xff,0x39,
+  0x7f,0xff,0xff,0xff,0xff,0xd7,0x4d,0x7f,0xef,0xeb,0xd7,0xc7,0xef,0xae,0x7e,0x1e,
+  0x32,0xff,0xef,0xeb,0x4f,0xfe,0xff,0xff,0xff,0xff,0xad,0x7f,0x5f,0x7b,0xff,0xf9,
+  0xfd,0xef,0xff,0xff,0xff,0xff,0xfb,0xed,0xbf,0xf7,0xcd,0x7b,0xff,0xff,0xf5,0xff,
+  0xf3,0x96,0x5f,0xf7,0xcd,0x79,0xfe,0x5f,0x3f,0xff,0xfc,0xdf,0x9f,0xe7,0xff,0xff,
+  0xff,0xbf,0xfd,0xff,0xff,0xff,0xff,0xff,0xdf,0x9f,0xff,0xbf,0xad,0x9f,0xff,0xff,
+  0xff,0xbe,0xdd,0xfb,0xfe,0xbf,0xa7,0xfd,0xff,0x7f,0xa5,0xff,0xfa,0xff,0xff,0xff,
+  0xff,0xf7,0xfa,0xfb,0x3f,0xff,0xff,0xff,0xff,0xff,0xb6,0xff,0x9d,0xe5,0x93,0xda,
+  0xf6,0x9f,0xef,0x7f,0x1f,0x7f,0xdf,0xe4,0x7f,0xde,0xff,0xf5,0xbf,0xff,0x56,0xbd,
+  0xef,0x7f,0xf4,0xff,0xf5,0xa7,0x7f,0xff,0xff,0xff,0xff,0x7c,0x7f,0xee,0xf2,0xb7,
+  0xff,0xff,0xda,0xfb,0xff,0xf7,0xeb,0xfa,0xda,0xbd,0xff,0xbf,0xfe,0xbf,0xff,0xeb,
+  0x9f,0xe3,0xff,0xff,0xff,0x9f,0xfe,0xff,0xfd,0x5f,0xff,0xff,0xf9,0x93,0xff,0x7e,
+  0x57,0xf7,0xff,0xfd,0x5f,0xff,0xfe,0xfd,0x7f,0x7f,0xc3,0x1e,0xff,0xff,0xdb,0xaf,
+  0xfd,0x7b,0x7e,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,
+  0xff,0xef,0xdf,0xf9,0xfe,0xff,0x37,0xef,0xd9,0xfd,0xff,0x7f,0x5f,0xdb,0x7e,0xdf,
+  0x47,0xf3,0x7f,0xbf,0xa7,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf6,
+  0x7f,0xff,0xff,0xfb,0xff,0xbf,0xfb,0xdb,0xfe,0xbf,0xff,0x7f,0xc9,0xee,0xf9,0x9f,
+  0xe7,0xe6,0x7d,0xbf,0xef,0xf9,0xfe,0xbf,0xbf,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,
+  0xfe,0xe7,0xff,0xef,0xdb,0xfe,0xf9,0xbd,0x6e,0xdb,0xbe,0xf5,0xbd,0x6f,0x59,0x36,
+  0x3f,0xbf,0x78,0xfe,0xe5,0xb3,0x6d,0xfb,0x96,0xed,0xbd,0x6e,0xfb,0x7e,0xff,0xbf,
+  0xef,0xdf,0x99,0xff,0xff,0xdb,0xfe,0xfd,0xff,0xef,0x9b,0xff,0xff,0xbe,0xef,0xbb,
+  0xf6,0xf3,0xff,0x6f,0xef,0xfb,0xbf,0x7f,0xff,0xfe,0xff,0x3f,0xef,0xff,0xff,0xff,
+  0xff,0xff,0xdb,0xdd,0x3f,0xff,0xfd,0xff,0x7f,0xff,0xf7,0xfd,0xff,0xff,0xbf,0xfb,
+  0xfe,0xff,0x7f,0xff,0xf7,0xff,0xfe,0xef,0xff,0xff,0xfe,0xff,0xef,0xf7,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0x57,0xfe,0xff,0xfd,0xff,0x7f,0xff,0xdf,0xbf,0xff,0xdf,
+  0x5f,0xd7,0xfe,0x7f,0x1f,0xef,0xe4,0x6f,0x7f,0x5e,0xdf,0xf5,0xff,0xbf,0x5f,0x9f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf4,0xff,0xff,0xff,0xcf,0xf7,0xdd,0xfe,0xad,0xdf,
+  0xff,0x7a,0x9a,0xaf,0xef,0xab,0xff,0xfe,0xaf,0xeb,0xe9,0xfe,0x7c,0x9f,0x7f,0xe9,
+  0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xfd,0x4f,0xff,0xff,0xff,0xef,0xff,0xff,0xfc,
+  0xff,0x7e,0xfd,0x77,0x5f,0xff,0xb5,0x6f,0xff,0x9d,0xbd,0xfd,0x7f,0xff,0xf7,0xff,
+  0xed,0x7f,0x7e,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xfe,0xff,0xe7,0xf9,0xfe,0x7f,
+  0x1f,0xe7,0xf9,0xfe,0x6f,0x8b,0xe7,0x78,0xfe,0x7f,0x9f,0xf9,0xbe,0x2f,0x9f,0xe6,
+  0xf9,0xfe,0x2f,0x8f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xe2,0x7f,0xff,0xbf,0xff,0xfb,
+  0xfe,0x79,0x7f,0x4f,0xff,0xfd,0xff,0x7f,0xe7,0xd7,0xff,0xff,0xff,0xf3,0xf4,0x7d,
+  0x1f,0x4f,0xff,0xfc,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x0f,0xff,0xff,0xff,
+  0xff,0x7f,0xbf,0xef,0xe9,0xff,0xff,0xbf,0xaf,0xfb,0xfa,0xff,0xff,0xff,0xfe,0xfe,
+  0xbf,0xaf,0xe9,0xff,0xfe,0xbf,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xc4,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xbd,0xff,0x7f,0x7f,0xf7,0xfd,0xff,0xff,0x5f,0xdf,0xfb,0xff,
+  0xcf,0xdf,0xff,0xff,0x7f,0xff,0xf3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0xbf,
+  0xff,0xdf,0xfd,0xfd,0xff,0x77,0xb7,0xa7,0xfb,0xfe,0xde,0xf7,0xfd,0xeb,0x7b,0x7f,
+  0xfd,0xff,0x7e,0x7f,0xdf,0xe7,0xef,0xfa,0x7e,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,
+  0x77,0xff,0xff,0xf4,0xfd,0x3f,0xcf,0xda,0xf7,0xff,0x3d,0x7f,0xdb,0xf2,0x7d,0xff,
+  0xff,0x7a,0xbf,0xff,0xff,0xdf,0xf7,0xbd,0xbb,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,
+  0xff,0xe0,0xff,0xff,0xaf,0x6a,0xda,0xde,0x97,0xaf,0xe2,0xfa,0x6e,0x1f,0xae,0xe8,
+  0xba,0xfe,0xad,0xeb,0xf8,0xfe,0x9b,0xaf,0xeb,0xfa,0xde,0xbf,0x8b,0xcb,0xfa,0xfe,
+  0xbf,0xaf,0xff,0x5d,0xff,0xcd,0xff,0xbf,0xfb,0xff,0x36,0xaf,0xbe,0xbf,0xef,0x36,
+  0xfe,0xdd,0xdf,0xef,0xfd,0xfc,0x7f,0xff,0xfe,0xed,0xb2,0xff,0x3d,0xff,0xef,0xff,
+  0xff,0xff,0xff,0xfd,0xa1,0xef,0xff,0xff,0xfd,0xef,0x7e,0xbf,0xff,0x7d,0x6f,0x7f,
+  0xdf,0x77,0xff,0xba,0xfe,0xdf,0xfc,0xff,0xff,0xff,0xef,0xff,0x7b,0xae,0xbf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xea,0x5b,0xbd,0x5f,0xff,0xfe,0xff,0xfb,0xff,0xfd,0xff,
+  0xef,0xdf,0xff,0xfb,0xff,0xff,0xed,0xf7,0x37,0xff,0x7f,0xff,0xff,0xfd,0xff,0x7f,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xfe,0xef,0xff,0xff,0xef,0xfb,0x7c,0xd9,0xa7,0xcf,
+  0xf3,0xf6,0x3c,0x8f,0xe2,0xfa,0x7c,0x8f,0x7b,0xde,0xf6,0xbb,0xaf,0x5f,0xda,0xfe,
+  0xbe,0xef,0xfe,0xdf,0xff,0xff,0xff,0xff,0xbd,0xff,0xff,0xf7,0x7f,0xef,0xfb,0xfd,
+  0xff,0xbd,0xed,0x5e,0x7f,0xde,0xdf,0x5f,0xf7,0xff,0xf7,0x77,0xfb,0xfd,0xff,0xf5,
+  0x99,0x67,0x7b,0xff,0xfb,0xff,0xff,0xff,0xff,0xfa,0x3f,0xfb,0xf7,0xfe,0x3b,0xef,
+  0xfe,0xfa,0xc6,0xfb,0xff,0xfe,0xbd,0xeb,0xbf,0xea,0xee,0x3f,0xfb,0xaa,0xfa,0xff,
+  0xcf,0xfb,0xfc,0xf7,0xfb,0xfd,0xff,0xff,0xef,0xff,0xfe,0xc7,0xff,0xbf,0xff,0xfd,
+  0xff,0xff,0xdb,0xf7,0xff,0xef,0x5b,0xce,0xf7,0xdf,0xbf,0xef,0xdf,0xfd,0xff,0xfb,
+  0xf9,0xff,0xfd,0xff,0x7c,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xf6,0xff,0xff,0xff,
+  0xff,0xb1,0xfe,0xbe,0xff,0xbd,0xf5,0xff,0xfb,0xd4,0xdd,0x7d,0xbd,0xdb,0xed,0xb5,
+  0xfd,0xff,0xff,0xff,0xe7,0xfb,0xff,0x9b,0xff,0xff,0xff,0xff,0xff,0xfd,0x9b,0xed,
+  0xff,0xfd,0x41,0xf0,0xfc,0x0d,0xcb,0xf3,0xff,0xed,0x3f,0xcc,0xf1,0xf8,0xfe,0x47,
+  0xf3,0xf7,0xee,0x3f,0xcf,0xde,0xff,0xf7,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,
+  0xff,0xff,0xdf,0xff,0xdd,0xdf,0xfb,0xf9,0xef,0x7f,0xff,0xed,0xfd,0xff,0xbd,0xde,
+  0xef,0x7d,0x7b,0x7a,0x36,0xfd,0xef,0xfb,0xfb,0xb7,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf8,0x7f,0xfb,0xff,0xf7,0xbf,0x79,0xf3,0xef,0x5c,0xe1,0x2c,0xff,0x7f,0x8e,0xd7,
+  0xf8,0xfb,0xfd,0xe3,0xff,0xfe,0xf2,0x1b,0xf7,0xaf,0xfc,0x3f,0xdf,0xff,0xff,0xff,
+  0xff,0xfe,0x07,0xff,0xff,0xcb,0xfe,0x7f,0xb7,0xf7,0xfa,0xff,0xde,0x1f,0x8f,0xdb,
+  0xfe,0xbd,0xbf,0xfb,0xfc,0xfe,0x9f,0xff,0xfb,0xba,0xff,0xff,0xef,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xe5,0x7b,0x7f,0xff,0xff,0xbf,0xcd,0xff,0x7f,0x7f,0x7f,0xff,0xff,
+  0xfd,0x7f,0xbf,0xcf,0xff,0x5f,0xdf,0xff,0xef,0xff,0x7f,0x7e,0xff,0xfb,0xfd,0x7f,
+  0xff,0xff,0xff,0xfe,0xfa,0xaf,0xff,0xff,0xbf,0xfd,0xff,0xde,0xc7,0xbf,0xff,0xff,
+  0x3f,0xfc,0xbf,0xfc,0xcf,0xff,0xf7,0xff,0x9f,0xfe,0xff,0xff,0xff,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0xc2,0xbf,0xcf,0xf3,0xff,0xff,0xff,0xca,0xf3,0xff,
+  0xff,0xd7,0xfe,0xa1,0xfe,0xa3,0xdf,0xfd,0xbc,0xf3,0xff,0xf6,0xf7,0xff,0x73,0x3f,
+  0xcf,0xff,0xff,0xff,0xff,0xff,0xfd,0x44,0xf7,0xfe,0xf4,0xbd,0x7d,0xeb,0xd2,0xfe,
+  0xb9,0xaf,0x3f,0xff,0xf2,0xbf,0xff,0xff,0xcf,0xf9,0xfe,0x7f,0x7f,0xff,0xf9,0xfe,
+  0x6b,0xca,0xff,0xff,0xff,0xff,0xff,0xe7,0xbd,0x5b,0xff,0x7e,0x57,0x9f,0xcd,0x7b,
+  0x5e,0xd7,0xf5,0xe7,0xff,0xfe,0x57,0xff,0xff,0x7b,0xff,0xbf,0xcf,0xfb,0xff,0xdf,
+  0x3f,0xed,0x79,0x7f,0xff,0xff,0xff,0xff,0xfc,0xfd,0xe9,0xff,0xdb,0xfa,0x7e,0xfd,
+  0x3d,0xa9,0xa2,0x7d,0xb5,0x77,0x4b,0xfb,0xcd,0xff,0xfd,0xbf,0xfa,0xb5,0x7f,0xad,
+  0xf2,0xcd,0xdc,0x27,0xfb,0xf7,0x7f,0xff,0xff,0xff,0xff,0xe5,0x6f,0xd1,0xde,0x4d,
+  0xbd,0xe7,0xbd,0x3e,0x4e,0x1e,0x6f,0xd9,0x5f,0x76,0xbd,0xef,0x5b,0xf7,0xd6,0xef,
+  0x6b,0x54,0x5a,0xbf,0xa4,0xf9,0xf8,0xff,0xff,0xff,0xff,0xff,0xf7,0xa7,0xff,0xef,
+  0xab,0xff,0xf2,0xbf,0xaf,0xab,0xfa,0xdf,0xff,0xaf,0xeb,0xff,0xfb,0xed,0xff,0xda,
+  0xdb,0xff,0xf7,0x4b,0xff,0xfe,0xbe,0xad,0xff,0xff,0xff,0xff,0xff,0xff,0x85,0xff,
+  0xf7,0xfd,0x3f,0xfc,0x57,0xf4,0xfd,0x3f,0x5f,0xff,0xf5,0xfd,0xdf,0xff,0xff,0x9f,
+  0xf1,0x5f,0xf7,0xfa,0xe9,0x7f,0xff,0xd3,0xf7,0xff,0xbf,0xff,0xff,0xff,0xff,0xfd,
+  0x9f,0xff,0xf9,0xf6,0xdf,0xff,0xcf,0xdf,0xf6,0x7f,0x7f,0xe7,0xff,0xf4,0xdf,0xff,
+  0x49,0xfe,0xff,0x37,0xed,0xdf,0xfc,0x7f,0xbf,0x7f,0xf7,0xf6,0xdf,0xff,0xff,0xff,
+  0xfe,0xb7,0xfe,0x7f,0x9f,0xef,0xf9,0xfe,0xbf,0xff,0xff,0xfb,0xfe,0x7f,0xfe,0x67,
+  0xf9,0xe7,0xff,0xfb,0xfb,0xfe,0xf9,0xff,0xff,0xfa,0xfe,0xfd,0x9e,0xef,0xff,0xff,
+  0xff,0xff,0xe6,0x7f,0xfe,0xff,0x93,0x6f,0xdb,0x96,0x7f,0x9d,0x6f,0x9b,0xfe,0xff,
+  0x9d,0x6f,0xf8,0x77,0xbf,0x6e,0xdb,0xb6,0x35,0xbd,0x6e,0x59,0xb6,0xff,0x9b,0xef,
+  0xfb,0xfe,0xff,0xfa,0xdb,0xff,0xff,0xff,0xdf,0xf3,0xee,0xff,0xff,0xff,0x9b,0xff,
+  0xff,0xfe,0xef,0xfb,0xec,0xff,0x6f,0xb3,0xf6,0xf3,0xfc,0xef,0xfb,0xf6,0xfb,0xbf,
+  0xff,0xff,0xff,0xff,0xfd,0x83,0xff,0xff,0xff,0xff,0xfe,0xff,0xbf,0xff,0xff,0xfe,
+  0xff,0xff,0xff,0xbb,0xfd,0xff,0xbf,0xfb,0xfe,0xff,0x7f,0xff,0xef,0xfb,0xff,0x7f,
+  0xef,0xff,0xff,0xff,0xff,0xff,0xf1,0x7f,0xfd,0x7f,0x4f,0xff,0xff,0xfd,0x3f,0x4e,
+  0xdf,0xfe,0xfd,0x7f,0xe7,0xd7,0xe4,0x7a,0xff,0xf7,0xbf,0xff,0x1b,0x5f,0xfb,0xb4,
+  0xed,0xff,0x4f,0xff,0xff,0xff,0xff,0xff,0x6f,0xff,0xa7,0xeb,0xf7,0x7f,0xef,0xaf,
+  0x6b,0xfb,0xbf,0xfd,0xa7,0x7c,0xfa,0x76,0x8f,0xfd,0xff,0x3f,0xdf,0xb3,0x6a,0xff,
+  0xfe,0xbd,0xaa,0xeb,0xff,0xff,0xff,0xff,0xff,0xe0,0xff,0xef,0xfd,0x7b,0xfc,0xf7,
+  0xf5,0xfd,0x7f,0x5f,0xbf,0xfd,0xed,0xf7,0x5d,0xf7,0xfb,0xff,0xff,0xff,0xbd,0x6d,
+  0x77,0xff,0xd7,0xf7,0xfd,0x7f,0xff,0xff,0xff,0xff,0xf7,0xbf,0xff,0xfe,0x2f,0x9b,
+  0xe3,0xf8,0xbe,0x2f,0x8f,0xe7,0xf9,0xbe,0x37,0x8f,0xe2,0x79,0xff,0x9f,0xe7,0xf8,
+  0xfe,0x2f,0x9f,0xe2,0xf9,0xbe,0x2f,0x9f,0xe7,0xf9,0xfe,0x7f,0x27,0xff,0xd7,0xf5,
+  0xff,0xbf,0xdf,0xf7,0xf4,0xff,0xff,0xff,0xd3,0xfe,0xfd,0x7f,0xc7,0xfe,0xff,0xff,
+  0x7f,0xf3,0xfd,0xff,0xff,0x5f,0xdf,0xf5,0xff,0xff,0xff,0xff,0xff,0xe6,0xff,0xfa,
+  0xfe,0xbf,0xf7,0xfb,0xfb,0xfe,0x9f,0xff,0xff,0xfa,0x7f,0xff,0xaf,0xeb,0xff,0xdf,
+  0xff,0xff,0xfb,0xfe,0xbf,0xff,0xeb,0xfb,0xfe,0xbf,0xff,0xff,0xff,0xff,0xfd,0xcf,
+  0xf7,0xff,0xf7,0xff,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0xff,0xdf,0xfb,0xf5,0xff,0x7f,
+  0x9f,0xff,0xff,0xff,0xcf,0xf7,0xf7,0xff,0x7f,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,
+  0xc3,0xff,0xff,0xfa,0xff,0xdf,0xad,0xef,0xfe,0x7e,0xf7,0xef,0xf9,0xff,0xde,0xbf,
+  0xed,0xff,0x7f,0xf7,0xf7,0xef,0x7b,0xdf,0xff,0xb7,0xff,0x7a,0xff,0xff,0xff,0xff,
+  0xfe,0xfb,0x77,0xff,0xff,0x7f,0xd3,0xff,0xfd,0xff,0x67,0xff,0xf2,0xff,0xff,0x47,
+  0xff,0xf6,0xff,0x67,0xfe,0xf7,0xff,0xff,0x2e,0xdf,0xff,0xff,0xbf,0xf7,0xff,0xff,
+  0xff,0xff,0xdf,0x6f,0xff,0xfa,0xf6,0x9d,0x8f,0xeb,0xfa,0xf4,0xbf,0x2f,0x6b,0xfa,
+  0xf6,0xb7,0xab,0xe9,0xde,0xbf,0xaf,0xeb,0xf8,0xae,0x3b,0xaf,0xeb,0x7a,0xfe,0xbf,
+  0xaf,0xeb,0xfa,0xfd,0x59,0xbf,0xff,0xff,0xff,0xfb,0xff,0xfb,0xfd,0xf7,0xf4,0xf7,
+  0x7f,0xff,0x7f,0xfd,0xcd,0x6c,0xdf,0xff,0xef,0xfc,0xbf,0xfb,0xff,0xff,0xf7,0xff,
+  0x3f,0xff,0xff,0xff,0xff,0xff,0x1f,0xff,0xff,0x7f,0x7f,0xff,0xe3,0xfb,0x7f,0xfd,
+  0xf7,0xff,0xfe,0xef,0xff,0xf7,0xff,0xff,0xde,0xb7,0xf7,0x2f,0xff,0xff,0x77,0xfb,
+  0xff,0x3f,0xff,0xff,0xfd,0xff,0x7e,0x37,0xbf,0xff,0xff,0x7f,0xdf,0xff,0xfd,0xff,
+  0xff,0xef,0xbf,0xff,0xbf,0xef,0xef,0xff,0xde,0xeb,0xfb,0xe5,0xff,0xff,0xfb,0xdb,
+  0xf7,0xff,0xbd,0xff,0xff,0xff,0xff,0xff,0xe4,0x1f,0xff,0xf7,0xff,0xaf,0xeb,0xb8,
+  0xff,0xbd,0x6f,0xe7,0xdf,0xfe,0x7f,0xef,0x3b,0xde,0xff,0xb6,0xcb,0xff,0x7f,0xa7,
+  0xbf,0xeb,0xfb,0xfe,0xbc,0xff,0xff,0xff,0xff,0xfe,0x9f,0xff,0xff,0xff,0xfa,0xfd,
+  0x77,0xbf,0xdf,0xdf,0xff,0xed,0xff,0xff,0x67,0xff,0xf7,0xfb,0x7e,0xfe,0x77,0xf9,
+  0xef,0xde,0x5f,0x75,0xef,0xb7,0xff,0xff,0xff,0xff,0xbd,0x99,0xfe,0xff,0xbc,0xfb,
+  0x3e,0xef,0xbf,0xfc,0x7e,0xfb,0xff,0xff,0xbf,0xff,0x3b,0xbf,0x8f,0xff,0xfe,0xcf,
+  0xfb,0xfc,0xdf,0xbe,0x3f,0xf3,0xb2,0xdf,0xff,0xfe,0xfe,0xff,0xfd,0x7f,0xfb,0xff,
+  0x7b,0xd7,0xd3,0xff,0xbf,0x5f,0xfd,0xff,0xdf,0xff,0x7e,0xff,0xff,0xfd,0x7f,0xfe,
+  0xe7,0xfd,0xdf,0x6f,0xc7,0xfe,0xff,0xff,0x3f,0xff,0xff,0xff,0xff,0xfe,0x0d,0xff,
+  0xff,0x5a,0xdf,0xff,0xbf,0xfb,0xff,0xdf,0x9d,0xff,0xfd,0x7a,0x6f,0x97,0xff,0xaf,
+  0xff,0xff,0xbf,0xe7,0xee,0xff,0xff,0xfd,0xfd,0xbb,0xff,0xff,0xff,0xff,0xff,0xc5,
+  0xde,0xef,0xff,0xff,0xff,0xff,0xbf,0xfc,0xf7,0xff,0xcf,0xe3,0x7f,0xff,0x3f,0xcf,
+  0xf4,0xfd,0x3f,0xfd,0xff,0xbc,0xff,0xff,0xef,0x67,0xf0,0xff,0xff,0xff,0xff,0xff,
+  0xfa,0xbb,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xdf,0xff,0xfd,0xdf,0x7f,0xfb,0xf6,
+  0xbd,0xfe,0xdf,0xeb,0xef,0xdd,0xfe,0x5f,0x7f,0xfd,0xfc,0xff,0xdf,0xff,0xff,0xff,
+  0xff,0xff,0x33,0xff,0xbf,0xdd,0xff,0x7f,0x5f,0x97,0xf9,0xff,0xff,0xbd,0xeb,0xed,
+  0xdc,0x7b,0x8c,0xa9,0xdf,0x6f,0xdb,0xf7,0xfb,0xdf,0x7a,0x5f,0xd7,0xf1,0xff,0xff,
+  0xff,0xff,0xff,0xea,0xff,0xef,0xff,0x3b,0xff,0xfb,0xfe,0xbf,0xbf,0x76,0xdf,0xff,
+  0xef,0x3f,0xee,0xdf,0xbf,0xf7,0xcd,0xfb,0xbe,0xff,0xff,0x0e,0xdb,0xfe,0xbf,0xbf,
+  0xff,0xff,0xff,0xff,0xfa,0x1f,0xff,0xff,0xf7,0xf7,0xff,0x5b,0xdf,0xd7,0xff,0xff,
+  0xff,0xff,0xf7,0xfd,0xfd,0xdf,0x9f,0xfd,0x7c,0xff,0x57,0xfd,0xff,0xff,0x77,0xbf,
+  0xf7,0xff,0xff,0xff,0xff,0xbf,0xc2,0xff,0xef,0xd7,0x1f,0xff,0xff,0x3c,0xff,0xe7,
+  0xcf,0xff,0xff,0xff,0x3e,0xff,0xb7,0xfb,0xdf,0xff,0xf3,0xef,0xff,0xff,0xff,0xbf,
+  0x3f,0xfb,0xdf,0xff,0xff,0xff,0xff,0xca,0x2e,0xfd,0xf9,0xfb,0xff,0xff,0xbf,0xdf,
+  0xff,0xcd,0xff,0xff,0xff,0xf7,0xcf,0xf7,0xff,0x7f,0xff,0xf7,0x7c,0xff,0xff,0xff,
+  0xf3,0xeb,0xff,0x7f,0xff,0xff,0xff,0xff,0xd7,0x8e,0x5f,0xbf,0x5e,0xff,0xd3,0xff,
+  0xaf,0x5b,0xfe,0xdf,0xff,0xff,0x3f,0xca,0xfe,0xfc,0xff,0xff,0xff,0xbf,0xaf,0xff,
+  0x9f,0xf2,0x9c,0xf7,0xef,0xff,0xff,0xff,0xff,0xfb,0xc4,0xbf,0xf7,0xef,0xf3,0xfe,
+  0xff,0x95,0xfd,0xff,0x7f,0xff,0xff,0xcf,0xfb,0x5f,0xdf,0x3f,0xff,0xff,0xff,0x35,
+  0xe7,0xf3,0xfe,0xc7,0x3a,0xfd,0xff,0xff,0xff,0xff,0xff,0xd8,0x9f,0xfe,0xfe,0xff,
+  0xdf,0xa6,0xf5,0xdf,0xae,0xd9,0xff,0xdf,0xf7,0xf6,0x89,0x73,0x7f,0xbf,0xff,0xfb,
+  0xfe,0x9f,0x75,0xfb,0xa2,0x3e,0xdf,0xac,0xdf,0xff,0xff,0xff,0xff,0x22,0xdf,0xdd,
+  0xff,0x53,0xd6,0xf5,0xbd,0xf5,0xf9,0xdf,0xff,0xff,0xfd,0xe9,0x78,0x7f,0xf7,0xff,
+  0xff,0x77,0xd3,0xde,0x1b,0xd6,0x77,0x9d,0xf7,0xbf,0xff,0xff,0xff,0xff,0x6c,0x7f,
+  0xfb,0xff,0xff,0xff,0xff,0xfa,0xfe,0xbe,0xef,0xff,0xff,0xe7,0xff,0xaf,0xef,0xd6,
+  0xf7,0xff,0xfb,0xfa,0xff,0xff,0xff,0xeb,0xca,0xfe,0xbf,0xff,0xff,0xff,0xff,0xf9,
+  0x4f,0xff,0x7f,0xdf,0xf7,0xff,0xff,0x4f,0xd7,0xf6,0xff,0xdf,0xf7,0xff,0xf5,0x7d,
+  0xff,0xdf,0xff,0xff,0x7f,0x4f,0xdb,0xff,0xfd,0x31,0x4f,0xdf,0xff,0xff,0xff,0xff,
+  0xff,0xb3,0xff,0xff,0xff,0xe7,0xfb,0x7e,0xfd,0xb7,0xcd,0xd9,0xf5,0xfd,0x7f,0xed,
+  0xf3,0x77,0xff,0xcd,0xfb,0xff,0xfd,0xff,0x5f,0xff,0xf6,0xfd,0xb7,0xdf,0xff,0xff,
+  0xff,0xff,0xf3,0x7f,0xff,0xff,0xff,0xff,0xbf,0xeb,0xbf,0xf6,0x7b,0xfe,0x7f,0x9f,
+  0xff,0xfe,0xbe,0x6f,0xf2,0xff,0xaf,0xef,0xfb,0xf6,0x7f,0xbf,0xfb,0xfb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0x67,0xff,0xed,0xfb,0xf6,0xf9,0xbb,0x67,0xfb,0xfe,0x7f,0x9f,
+  0xe7,0xfb,0xd6,0xfb,0x8e,0xfb,0xe6,0xed,0xbe,0x67,0x18,0xf6,0xed,0x9f,0xe6,0xfb,
+  0xfe,0xff,0xbf,0xef,0xfe,0x91,0xbf,0xff,0xfb,0xfc,0xfd,0xbf,0xcf,0xfb,0xef,0xff,
+  0xfe,0xff,0xbf,0xff,0xff,0xfe,0xff,0xe6,0xfd,0xff,0x7f,0xff,0xe6,0xff,0x3f,0xef,
+  0xfb,0xef,0xff,0xff,0xff,0xff,0xdc,0xbf,0xff,0xfd,0xff,0xbf,0xdf,0xfb,0xfb,0xff,
+  0xff,0xff,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xbf,0xef,
+  0xfb,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xa7,0xff,0xff,0xed,0xff,0x7f,0xff,0xd1,
+  0xf7,0xfd,0x1f,0xee,0xf9,0xfe,0xff,0x3f,0xcf,0xe7,0xff,0x7f,0x7f,0xd3,0xb4,0xff,
+  0xff,0xc7,0xf1,0xb7,0xff,0xff,0xff,0xff,0xff,0xae,0xff,0xff,0xff,0xdf,0xf7,0xdd,
+  0xf2,0xff,0xab,0xaf,0xfe,0xff,0xbf,0xff,0xeb,0xfa,0xfe,0xe9,0xf7,0xfd,0xfa,0xfc,
+  0x8f,0xf7,0xfb,0xfe,0xfe,0xef,0xff,0xff,0xff,0xff,0xfc,0x9f,0xff,0xff,0xff,0xef,
+  0xff,0xff,0x5f,0xd7,0xf5,0xff,0xf7,0xff,0xf7,0xf5,0xff,0x7b,0xbf,0xff,0xff,0xf7,
+  0x5f,0xf7,0xef,0xff,0x3f,0xcf,0xd7,0xff,0xff,0xff,0xff,0xff,0xd1,0xff,0xff,0xe7,
+  0xf9,0xfe,0x7f,0x89,0xe6,0xf8,0x9e,0x7f,0x9d,0xe6,0xf8,0xbe,0x6f,0x9f,0xf9,0xfe,
+  0x7f,0x8b,0xe2,0xf9,0xfe,0x6f,0x9b,0xe3,0xf9,0xfe,0x7f,0x9f,0xe7,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xfd,0x7f,0xff,0xd7,0xfe,0x7f,0x9f,0xff,0xf7,0xfd,0xff,0xff,
+  0xfb,0xf7,0xfd,0x7f,0x5f,0xff,0xfd,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0xcf,
+  0xff,0xff,0xff,0xff,0xff,0xbf,0xaf,0xff,0xfa,0xff,0xff,0xff,0xff,0xfe,0xfb,0xbf,
+  0xef,0xff,0x7f,0xbf,0xaf,0xeb,0xfe,0xff,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xcd,0xff,0x7f,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xdf,0xff,0xff,0xff,0x7f,0xdf,
+  0xd7,0xfb,0xff,0xff,0xff,0xfd,0xff,0x7f,0xff,0xf7,0xfd,0xff,0x7f,0xff,0xff,0xff,
+  0xff,0xfe,0x3f,0xfd,0xff,0xff,0xff,0xff,0xfe,0xbf,0xed,0xeb,0xff,0xdf,0xf7,0xef,
+  0xeb,0x3a,0xdf,0xfd,0xfd,0xff,0xfe,0xbf,0xad,0xff,0xff,0xff,0xff,0xbd,0xff,0xff,
+  0xff,0xff,0xff,0x77,0xff,0xeb,0xb6,0xff,0xfb,0x77,0xff,0xff,0xff,0xdf,0xff,0xff,
+  0xf2,0xff,0x3f,0x67,0xf2,0xbf,0xff,0x2f,0xcb,0xf6,0xfc,0xbf,0x2f,0xfb,0xfa,0xff,
+  0xff,0xfe,0xff,0xff,0xfe,0xbf,0xff,0xaf,0x69,0xfa,0x3e,0xb7,0xa7,0xe1,0xfa,0xfe,
+  0x3f,0xa4,0xe9,0xfa,0xee,0x3d,0xea,0xfa,0xee,0xbd,0xab,0xeb,0x72,0xae,0xb7,0xa5,
+  0xeb,0xfa,0xfe,0xbf,0xaf,0xf7,0xdf,0xff,0xff,0x9f,0xff,0xfe,0xff,0xdf,0xbc,0xfd,
+  0xff,0x3f,0xff,0xfb,0x7f,0xdd,0x7f,0xed,0xff,0xef,0x3f,0xfb,0xce,0xfb,0xfb,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xd1,0x7d,0xdf,0xff,0xfd,0xff,0xff,0xbf,0xdf,
+  0xfd,0xf3,0xdf,0xff,0xfb,0xfd,0xff,0xff,0xdf,0x7f,0xf5,0xaf,0xbf,0x7f,0xfb,0xdb,
+  0xfa,0xbf,0xbf,0xff,0xff,0xff,0xff,0xff,0xef,0x5f,0xff,0xff,0xf7,0xff,0xff,0xee,
+  0xff,0xfe,0xef,0xfb,0xdf,0xff,0xff,0xfe,0xed,0xe9,0xfb,0xbf,0xef,0xfb,0xde,0xff,
+  0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xfe,0xcf,0xff,0xff,0xeb,0xf9,0xfe,
+  0xbf,0x8d,0xfd,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0xef,0xba,0xfe,0x3f,0x9f,
+  0xff,0xe8,0xff,0xbf,0xbf,0xe3,0xdf,0xff,0xff,0xff,0xff,0xdd,0xff,0xff,0xf5,0x7f,
+  0xfd,0xfb,0xfb,0xfb,0xf5,0x7f,0xfe,0xdf,0xff,0xfd,0xff,0xff,0xff,0x99,0x6f,0x6e,
+  0xff,0xdf,0xff,0xff,0xdf,0xfe,0xf6,0xff,0xff,0xff,0xff,0xff,0xf8,0xbf,0xff,0xfd,
+  0xfe,0xdb,0xfb,0x5f,0xfb,0xcf,0xfb,0xbf,0xed,0xfb,0xff,0xff,0xbc,0xee,0xce,0xf3,
+  0xbf,0xff,0x2f,0xc3,0xeb,0xbf,0xe3,0x3b,0xce,0xff,0xff,0xef,0xff,0xff,0xd7,0xff,
+  0xfe,0xfe,0xfd,0xef,0x57,0xdf,0xf5,0xbd,0xfb,0xfb,0xff,0xff,0xfd,0xb7,0x5f,0xd6,
+  0x7d,0xbf,0xfb,0xbe,0xf5,0xfc,0xef,0xef,0xdf,0xb5,0xff,0xff,0xff,0xff,0xff,0xe0,
+  0xff,0xff,0xff,0xff,0xe7,0xbf,0xde,0xff,0xf9,0xe3,0xff,0x7f,0xd7,0xfd,0xef,0xff,
+  0xdb,0xbf,0xe9,0x3e,0xdf,0xff,0xfd,0xed,0xff,0xfb,0xdf,0xef,0xff,0xff,0xff,0xff,
+  0xff,0x1f,0xef,0xff,0xbf,0x03,0x7c,0xff,0xff,0xcf,0x73,0xbc,0x7f,0xfd,0xfc,0xff,
+  0xcc,0xef,0x4e,0xff,0xfc,0xdf,0xf1,0xcf,0xf3,0xec,0x77,0xf7,0xcf,0x7f,0xff,0xff,
+  0xff,0xff,0xeb,0xfe,0xbf,0xff,0xbf,0x7f,0xdf,0xff,0xf9,0xff,0x6f,0xf7,0xff,0xff,
+  0xdf,0xf7,0xdf,0xed,0xff,0xef,0xae,0xff,0x7d,0xfb,0x7f,0xf7,0xdf,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0x7f,0xff,0xfe,0x5f,0xeb,0xf9,0xfd,0x7f,0x5f,0xa7,0xff,0xd7,
+  0xf7,0xfd,0xff,0xf9,0xfa,0x15,0xb7,0xfd,0xf7,0xfb,0x9f,0xeb,0xef,0xef,0xff,0x8f,
+  0xff,0xff,0xdf,0xff,0xee,0x27,0xff,0xff,0xfb,0xfe,0xde,0x37,0xed,0xff,0x7c,0xff,
+  0xdf,0xff,0xff,0xfe,0xff,0x8e,0xe9,0xa8,0xdf,0xbf,0xef,0xfa,0x5e,0xdf,0xf7,0xff,
+  0xd7,0xdf,0xff,0xff,0xff,0xbd,0xa1,0xff,0xff,0xfe,0xff,0xdf,0xff,0xfd,0xff,0xff,
+  0xdd,0xff,0xff,0xff,0xff,0xdf,0xcd,0xff,0xff,0xff,0xd7,0xfb,0xfc,0xff,0xdf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x8f,0xff,0xff,0xff,0xff,0xff,0xfe,0xf9,
+  0xb1,0xff,0xff,0xfe,0xff,0xff,0xff,0xd7,0xdf,0xbd,0x5c,0xcf,0x3e,0xcf,0xff,0xff,
+  0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x36,0xbf,0xff,0xf7,0xff,0xff,0x3f,
+  0xcf,0x93,0xfc,0xff,0xff,0xdf,0xff,0xff,0x69,0xbf,0xf3,0xcd,0xea,0xfb,0xcb,0xff,
+  0xff,0xff,0xfb,0xcf,0xff,0xff,0xff,0xff,0xff,0xfd,0x7c,0xf7,0xff,0xff,0xf9,0xaf,
+  0xfb,0xca,0xde,0xaf,0xef,0xff,0xfb,0xf4,0xbc,0xff,0xfb,0x56,0xb9,0xfa,0x7e,0xd2,
+  0xf3,0xf7,0xef,0xff,0xd2,0xf5,0xbf,0xff,0xff,0xff,0xff,0xbc,0x9b,0xff,0xfe,0x7f,
+  0x95,0xfd,0xf3,0x5f,0xcf,0xf7,0xff,0xff,0x7e,0xd7,0x9f,0xff,0xf9,0xd7,0xff,0xcf,
+  0xf9,0x5e,0x7f,0xb7,0xff,0xf9,0x5e,0xdf,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,0xff,
+  0xff,0xf4,0xff,0xac,0xc9,0xd2,0x6c,0xbb,0x7f,0xef,0xef,0xff,0xff,0x7d,0x5b,0xdd,
+  0xff,0xff,0xe9,0xff,0xf0,0xb3,0x77,0xe9,0xe2,0xf5,0xff,0xff,0xff,0xff,0xf7,0x6f,
+  0xff,0xff,0xf5,0x9f,0xf7,0xa9,0x3e,0x47,0x9f,0xff,0xfd,0xdf,0xf7,0xfd,0x4d,0x7f,
+  0x5a,0x3d,0x6f,0x79,0x3e,0xf7,0x96,0xaf,0xfd,0x34,0x5d,0xbf,0xff,0xff,0xff,0xf7,
+  0xe7,0xff,0xff,0xff,0xfa,0xfe,0xb7,0xaf,0xa9,0xea,0xdf,0xff,0xbf,0xeb,0xff,0xff,
+  0xff,0xeb,0xff,0xff,0xfe,0xaf,0xbf,0xea,0xff,0xfd,0x2f,0xeb,0xff,0xff,0xff,0xff,
+  0xfe,0xe9,0xbf,0xff,0xff,0xff,0x5f,0xdf,0xf4,0xfd,0x3b,0x7f,0xff,0xf7,0xfd,0x7f,
+  0xff,0xf5,0xfd,0x7f,0xff,0xdf,0xf4,0xfd,0xff,0x5f,0xfb,0xa4,0xfd,0x7f,0xff,0xff,
+  0xff,0xff,0xf9,0x2e,0xff,0xff,0xff,0xff,0x7f,0xc7,0xdf,0xf7,0xbf,0x7f,0xff,0xfb,
+  0x7f,0xff,0xbf,0x5f,0xfc,0xff,0x9f,0xef,0xdb,0x7e,0xdf,0x7f,0x6f,0xdb,0x7d,0xff,
+  0xff,0xff,0xff,0xdf,0x17,0xfe,0xff,0xff,0xef,0xdb,0xfe,0xff,0xff,0xef,0xdb,0xff,
+  0xff,0xff,0xff,0xfe,0xe7,0xff,0x2b,0xff,0xff,0xbf,0xff,0xff,0xff,0xee,0xbf,0xbf,
+  0x6f,0xff,0xff,0xff,0xff,0xe6,0x7f,0xee,0xfd,0xbc,0x6e,0xdb,0xb6,0x7f,0xb3,0x6f,
+  0xbb,0xfe,0xdf,0xb7,0xed,0xf9,0xd7,0xbb,0xef,0xdb,0xd6,0x7f,0xbf,0x6f,0xf9,0xbe,
+  0x6f,0xbe,0xef,0xfb,0xfe,0xfd,0xfa,0x9b,0xff,0xff,0x7f,0xef,0x9b,0xe6,0xff,0xff,
+  0xdf,0xbf,0xff,0xff,0xff,0xff,0xff,0xef,0xfc,0xef,0xf7,0xfe,0xff,0xff,0x6f,0xbb,
+  0xfe,0xff,0xbe,0xff,0xff,0xff,0xfd,0xbd,0x9b,0xff,0xff,0xff,0xfb,0xfd,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xf7,0xef,0xff,0xff,0xbf,0xff,0xf7,
+  0xfe,0xfe,0xff,0xdf,0xff,0xff,0xff,0xff,0xef,0xfa,0x5f,0xff,0xfb,0x7f,0xdf,0xff,
+  0xfd,0x3f,0xff,0xdf,0xff,0xfd,0x7f,0xff,0xd7,0xb4,0x6f,0xdf,0xf7,0xfd,0xfd,0x3f,
+  0xdf,0xff,0xf4,0x7d,0x3b,0xff,0xff,0xff,0xff,0xfa,0xff,0x6f,0xff,0xff,0xdd,0xfe,
+  0xae,0xef,0xaf,0x7f,0xde,0xaf,0xff,0xa7,0xff,0xfa,0x7e,0x8f,0xfc,0xb3,0x7f,0xdf,
+  0xaf,0xfd,0xfe,0xb6,0xbf,0xaf,0xfe,0xbf,0xff,0xff,0xff,0xff,0xd1,0xff,0xff,0xff,
+  0xff,0xfd,0xd7,0xf5,0xfb,0xff,0x5e,0xff,0xff,0xff,0xfe,0x5e,0xb7,0xfb,0xff,0xde,
+  0xff,0xf5,0xdb,0xfb,0x5d,0xd3,0xf5,0xef,0x7f,0xff,0xff,0xff,0xff,0xf7,0x3f,0xff,
+  0xfe,0x7f,0x9f,0xe2,0xf8,0xbe,0x7f,0x9b,0xe7,0xf9,0xfc,0x7f,0x8b,0xe6,0x79,0xff,
+  0x8b,0xe7,0xf8,0xbe,0x7f,0x8b,0xe2,0xf8,0xbe,0x6f,0x9f,0xe7,0xf9,0xfe,0x7f,0xb7,
+  0xff,0xff,0xfe,0xfd,0x7f,0xff,0xf7,0xfe,0x7f,0xff,0xef,0xd7,0xef,0xfd,0x3f,0x4f,
+  0xff,0xff,0x7f,0xef,0xd7,0xfe,0xff,0xff,0x47,0xd7,0xfd,0xff,0xff,0xff,0xff,0xff,
+  0xea,0xff,0xff,0xff,0xff,0xef,0xef,0xfa,0xff,0xff,0xff,0xfd,0xfa,0xff,0xff,0xa7,
+  0xeb,0xff,0xff,0xbf,0xfd,0xfa,0xff,0xdf,0xef,0xeb,0xfa,0xfe,0xff,0xff,0xff,0xff,
+  0xff,0xf6,0xdf,0xfe,0xff,0xfb,0xfd,0xff,0xff,0xdf,0xdf,0xfd,0xff,0xff,0xfe,0xff,
+  0xfd,0xff,0x3f,0xbf,0xfd,0xff,0xff,0xdf,0xff,0xff,0xff,0x7f,0xdf,0xf7,0xff,0xff,
+  0xff,0xff,0xff,0x9b,0xff,0xff,0xff,0x7f,0xb7,0xbd,0xeb,0xfb,0x7f,0xb7,0xf7,0xff,
+  0xdf,0xff,0x9f,0xed,0xff,0xde,0xff,0xf7,0xeb,0xff,0x7f,0xb7,0xa7,0xef,0xfa,0xdf,
+  0xff,0xff,0xff,0xff,0xfb,0x2f,0xff,0xff,0xaf,0xfb,0xff,0xfc,0xbf,0x7f,0xd9,0xff,
+  0x7d,0x1f,0xff,0xdf,0xfc,0xff,0x2f,0xd3,0xf6,0xbc,0xbf,0x6f,0xff,0xff,0xfc,0x9d,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0xef,0xfb,0xfa,0xfe,0xbf,0xaf,0xeb,0xba,0xb6,0xbf,
+  0xaf,0xeb,0xda,0xfe,0xad,0x8b,0xe3,0x4e,0xb7,0xad,0xeb,0x58,0xd6,0xbf,0xab,0xeb,
+  0xba,0xfe,0xbf,0xaf,0xeb,0xfa,0xff,0xc9,0xff,0xff,0xff,0x3f,0x7f,0xff,0xef,0xfb,
+  0x3e,0x37,0xbf,0xff,0xff,0xf7,0xf7,0xf3,0xbf,0xf7,0xbf,0xcf,0xff,0xfd,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xf9,0x1f,0xff,0xfd,0xbf,0x7f,0xff,0x7f,
+  0xff,0xaf,0xff,0x7f,0xff,0xff,0xff,0xfe,0x7a,0xfb,0xfe,0xbf,0xb7,0xaf,0xfe,0xff,
+  0x7f,0xff,0xff,0xff,0x7f,0xff,0xff,0xfd,0xff,0xde,0x85,0xfb,0xff,0xfd,0xff,0xff,
+  0xff,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xdd,0xef,0xbf,0x3f,0xff,0xf3,0xff,
+  0xff,0x2f,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xbf,0xec,0x7f,0xff,0xff,0xbf,
+  0xaf,0xeb,0xfe,0xfe,0x79,0xef,0xff,0xff,0xff,0xff,0xbf,0x7f,0xfe,0x3d,0xaf,0x68,
+  0xcb,0x3a,0x5f,0xee,0xab,0xfb,0xfa,0x7f,0xff,0xff,0xff,0xff,0xf8,0x9f,0xff,0xff,
+  0x5f,0xf5,0xdf,0x77,0xbf,0xff,0xfb,0xff,0xf7,0xff,0xff,0xfd,0xff,0xdf,0x1f,0xdd,
+  0xdf,0x76,0xed,0xff,0xef,0xfd,0x7e,0xdd,0xfe,0xff,0xff,0xff,0xff,0xff,0x91,0xff,
+  0xff,0xbf,0xff,0xdf,0xbf,0xf3,0xfe,0xef,0xbb,0xfb,0xff,0xff,0x7f,0xbf,0xcd,0xee,
+  0xfe,0x3f,0x8f,0xfb,0xfe,0xee,0xbb,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xe3,
+  0x7f,0xff,0xff,0xff,0xff,0xb6,0xfd,0xbf,0x3f,0xcf,0xff,0xff,0xff,0xff,0xdb,0xf7,
+  0xfd,0x7d,0xff,0xf5,0xfc,0xff,0x17,0xce,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0x6f,0xbf,0xff,0xff,0xbf,0xff,0xbd,0xef,0xfb,0xf6,0xff,0xf3,0xff,0xff,0x5e,
+  0x6f,0xad,0xb9,0xbf,0xff,0xff,0xef,0xff,0xbb,0xfd,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xd5,0xf7,0xff,0xfc,0xbf,0xff,0xdf,0xff,0xf8,0xfb,0xff,0xff,0xfe,0x5f,
+  0xff,0xfb,0xfb,0xf7,0xce,0x1f,0xfb,0xe2,0xdf,0xef,0xb9,0xfe,0xfe,0x7f,0xf7,0xff,
+  0xff,0xff,0xff,0xfd,0xbe,0xff,0xff,0xdf,0xff,0xfb,0xf9,0xff,0x9f,0xff,0xff,0xff,
+  0xff,0xff,0xfe,0xff,0xfa,0xff,0xfb,0xff,0xe7,0xdf,0x7f,0x77,0xff,0xfb,0xfb,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x83,0xbf,0xff,0xfb,0xff,0xf7,0xfd,0x33,0xff,0xfd,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0x7f,0xdb,0xc7,0x5d,0x7f,0x1b,0xf7,0xf3,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf6,0xbf,0xff,0xdf,0xff,0xff,0xfe,0xfa,0xff,0xf9,
+  0xeb,0xff,0xff,0xdf,0xf7,0xff,0xfb,0xff,0xf7,0xcd,0x79,0xee,0xf6,0x3f,0xf7,0xff,
+  0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x5f,0xef,0xff,0xff,0xff,0x7f,0xd7,0x7f,
+  0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0xfd,0xfd,0xfc,0xdf,0xdd,0xfd,0xf7,
+  0xff,0xff,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xd8,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x3f,0xff,0xff,0xdf,0xf3,0xfd,0xff,0xff,0xff,0xf3,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x3f,0xff,0xbf,0x3f,0xfb,0xff,0xff,0xff,0xff,0xff,0xc9,0x6b,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0x9f,0xbf,0xff,0xfe,0xff,0xff,
+  0xff,0xef,0xdf,0xf3,0xfc,0xff,0x7f,0xff,0xff,0xff,0xff,0xd7,0x6f,0x7f,0xff,0xff,
+  0xff,0xff,0xfc,0xb7,0xff,0xff,0xf4,0xbf,0xff,0xff,0xff,0xff,0xef,0xff,0x9f,0xe7,
+  0xff,0xff,0x5b,0xff,0xfe,0xbd,0x27,0xef,0xff,0xff,0xff,0xff,0xfb,0xd1,0xbf,0xff,
+  0xff,0xff,0xff,0xff,0x36,0xff,0xff,0xfe,0xd7,0xff,0xff,0xff,0xfc,0xff,0xff,0xff,
+  0xfc,0xff,0xff,0xef,0xff,0x7e,0xd7,0xb6,0xfd,0xff,0xff,0xff,0xff,0xff,0xd9,0xb7,
+  0xff,0xff,0xff,0xff,0xfa,0xfe,0xb7,0xaf,0xeb,0xef,0xff,0xff,0xff,0xeb,0xff,0x7f,
+  0xaf,0xfb,0xff,0xf5,0xfe,0x7f,0xeb,0x42,0x79,0xbb,0x3f,0xff,0xff,0xff,0xff,0xff,
+  0x46,0xff,0xff,0xff,0xff,0xff,0x57,0xd6,0xf5,0x7d,0x5f,0xf7,0xff,0xff,0xfd,0x5f,
+  0x7e,0xb5,0x7f,0xde,0xf7,0xfd,0x8f,0x69,0x6e,0x4d,0x1f,0xf7,0x7f,0xff,0xff,0xff,
+  0xff,0x7a,0xdf,0xff,0xff,0xff,0xff,0xeb,0xfa,0xfe,0xbf,0xaf,0xeb,0xff,0xf5,0xff,
+  0xaf,0xff,0xde,0xbf,0xff,0xbf,0xff,0xff,0xf7,0xad,0xab,0xfa,0xfe,0xff,0xff,0xff,
+  0xff,0xff,0xfa,0x1f,0xff,0xff,0xff,0xff,0xfd,0x7f,0x5f,0xd7,0xf5,0xe9,0x7f,0xff,
+  0xff,0xf5,0xff,0xf1,0xd7,0xff,0xfd,0xff,0x7f,0xff,0xa5,0xfd,0x3f,0x7f,0xdf,0xff,
+  0xff,0xff,0xff,0xff,0xf3,0xfe,0xdf,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfe,0xdf,0xe7,0xff,0xff,0xff,0xbf,0xef,0xf7,0xf7,0xff,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfe,0x7f,0xbf,0xff,0xfa,0xff,0xbf,0xbf,0xff,
+  0xdf,0xff,0xff,0xff,0xff,0xff,0xfe,0x87,0xff,0xef,0xfb,0xfe,0xff,0xbf,0x6f,0xfb,
+  0x7e,0xff,0xb7,0xef,0xfb,0xfe,0xff,0xbc,0x7b,0xf6,0xef,0xbf,0xee,0xdb,0xf6,0xf9,
+  0x9f,0xef,0xfb,0x7e,0xff,0xbf,0xef,0xff,0x89,0xbf,0xff,0xff,0xff,0xff,0xff,0xcf,
+  0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfc,0xff,0xbf,0xef,0xf3,0xfc,
+  0xf9,0xff,0xef,0xbf,0xff,0xff,0xff,0xff,0xff,0xda,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xbf,0xdf,0xf7,0xfe,
+  0xff,0xbf,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x25,0xff,0xff,0xbf,0xff,
+  0xff,0xfe,0xff,0xff,0xef,0x7f,0xff,0xff,0xff,0xff,0xfe,0xcf,0xef,0xff,0xfb,0xde,
+  0xb7,0xff,0xff,0xff,0x4f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbe,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdb,0xbf,0xff,0xe7,0xff,0xff,0xff,0xff,0xff,0xfb,0xf7,0xdf,0xf7,
+  0xfd,0xdf,0x7d,0xdf,0xbb,0xeb,0xdf,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,
+  0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9f,
+  0xaf,0xff,0xfe,0xff,0xff,0xbf,0xfd,0x7b,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xa3,
+  0xff,0xff,0xe7,0xf9,0xfe,0x7f,0x8f,0xe7,0xf9,0xbe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,
+  0x9e,0xf9,0xfe,0x7f,0x9f,0xe7,0xf8,0xfe,0x2f,0x1b,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,
+  0xf5,0x7f,0xff,0xff,0xef,0xff,0xfe,0xfd,0x7f,0xef,0xf3,0xff,0xff,0xff,0xff,0xfb,
+  0xfc,0x7f,0xff,0xfb,0xfe,0x7f,0xbf,0xe7,0xd7,0xfd,0xeb,0x7f,0xff,0xff,0xff,0xff,
+  0xff,0xde,0x6f,0xff,0xff,0xfd,0xff,0xff,0xdf,0xaf,0xfd,0xfe,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xbf,0xff,0xff,0x7f,0xff,0xf7,0xef,0xfa,0xfe,0xff,0xbf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xcd,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xcf,0xff,0xff,
+  0xff,0xff,0xef,0xff,0xf9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xf7,0xff,0xff,0x7e,0xf7,0xf7,0xf9,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0x7f,0xef,0xed,0xff,0x7f,0xdf,0xf7,0xef,0x7b,0xf6,0xb7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0xff,0xff,0xff,0xff,0xfd,0xff,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x6f,0xff,0xfd,0xaf,0x7f,0xdf,0xf6,0x7c,0xbf,0x73,
+  0xdb,0xf4,0xff,0xff,0xff,0xff,0xff,0xec,0xfd,0xff,0xab,0xeb,0xfa,0xbe,0xbf,0xaf,
+  0xeb,0xfa,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,0xad,0xeb,0x7a,0xde,0xbd,0xae,0xcb,0x32,
+  0xf4,0xb7,0xaf,0xeb,0xfa,0xfe,0xbf,0xaf,0xf5,0x1b,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xfd,0xff,0x3f,0xff,0xff,0xfc,0x78,0xdf,0xff,0xf3,0xfe,0xff,0xff,0x9d,
+  0xff,0xff,0xff,0x3f,0xef,0xff,0xff,0xff,0xff,0xfd,0xc9,0xfd,0xff,0xf7,0xfd,0xff,
+  0xff,0xff,0xf7,0xff,0xaf,0xff,0xff,0xff,0xfe,0xbf,0xf9,0xdf,0x7f,0xff,0xff,0xff,
+  0xff,0xef,0xf9,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe2,0x5f,0xff,0xfd,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0xff,0xff,0xef,0xff,0xff,0xdc,0xef,0xbf,0xbe,
+  0xbf,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xa7,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xa7,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xfe,
+  0xfe,0xaf,0xef,0xa7,0xf8,0xfe,0x3f,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xe1,0xff,
+  0xff,0xf7,0xff,0xff,0xff,0xf5,0xdf,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xfd,0x7b,
+  0xf5,0xbd,0xfb,0x7f,0xbf,0xff,0xbf,0xef,0x7f,0xdf,0xff,0xff,0xff,0xff,0xfb,0xfe,
+  0x1f,0xdf,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,0xff,0xff,0xff,
+  0xfa,0xff,0xff,0xfa,0xfe,0xbf,0xef,0x7a,0xff,0xbe,0xef,0xfb,0xff,0xff,0xef,0xff,
+  0xff,0x96,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfa,0xff,0xff,0xff,0xfb,
+  0xff,0xfb,0xdf,0x77,0xff,0x6f,0x9e,0xf3,0xfc,0xef,0x5f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf4,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,
+  0xff,0xff,0xff,0xab,0xf7,0xff,0xed,0xfb,0x6f,0xbf,0xeb,0xff,0xff,0xdf,0xff,0xff,
+  0xff,0xff,0xf3,0xfd,0x5f,0x7f,0xff,0xff,0xff,0xef,0xff,0x3f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xbf,0x8f,0x7f,0xbf,0xff,0xff,0xfd,0x4f,0xf3,0xfc,0xfd,0x3f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xbb,0xef,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xff,0xef,0xbf,0xff,0xfb,0xff,0xfd,0xff,0x7d,0xdd,0xf7,
+  0xff,0xff,0xff,0xff,0x7f,0xff,0xf0,0x7f,0xff,0xff,0xff,0xff,0xff,0xee,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x5d,0xff,0xaf,0xe3,0xff,0x1f,0xc7,0xf9,
+  0xfe,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0x07,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xca,0xbf,0xfb,0xbf,0xef,0xfb,0xfe,
+  0xff,0x3b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb1,0xfb,0xff,0xff,0xff,0xff,0xfd,
+  0xbf,0xff,0xdf,0xff,0xff,0xff,0xff,0xfe,0xf7,0xff,0xff,0xf7,0xff,0xef,0xfb,0xfe,
+  0xdf,0xd7,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfe,0x0b,0xff,0xff,0xbf,0xff,
+  0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe7,
+  0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xd4,0xff,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfe,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xe6,0xd7,0xff,
+  0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xbf,
+  0xff,0xff,0x9f,0xff,0xbc,0xaf,0x4b,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0xbe,0xcb,
+  0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,
+  0xd7,0xff,0xff,0xff,0xfe,0x5f,0xb5,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xfe,0x7d,
+  0xd9,0x7f,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xbf,0x4f,0xd2,0xc9,0xbd,0x3d,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xea,0x2d,0xff,0xff,0x77,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xf7,0xff,0xff,0x7b,0xdf,0x5a,0x9f,0xa7,0xbf,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf7,0x4d,0xff,0xff,0xef,0xff,0xff,0xff,0xff,0x5f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xeb,0xff,0xff,0xfe,0xff,0xeb,0xfa,0xde,0xbf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0x80,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xcf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,0xff,0xff,0xff,0xfd,0x7f,0x5f,0xd7,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xfc,0xbf,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0xff,0x3f,0xc7,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x07,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x7f,0xff,0xfb,0xde,
+  0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xe8,0x7f,0xfe,0xff,0xbf,0xef,0xfb,0xfe,
+  0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xff,0xbf,0xef,0x5b,0xf6,0xfd,0xbf,
+  0x6f,0xdb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xfb,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xfd,
+  0xfe,0xdf,0x9b,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd3,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x7f,0xff,0xff,
+  0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xf5,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,
+  0xff,0xff,0xff,0x7f,0xdf,0xff,0xef,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xaf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x9f,0xff,0xff,0xff,0xff,0xff,0xf9,
+  0xff,0xfd,0xdd,0x77,0x6a,0xfb,0xae,0xef,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xec,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd7,0xff,0xff,0xff,0xff,0xff,
+  0xef,0x7f,0xff,0xff,0xff,0xfd,0xf3,0xfd,0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xf3,0x3f,0xff,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe2,0xe9,0xfe,0x7f,0x9f,
+  0xe7,0xf9,0xef,0x9f,0xe6,0xe9,0xbe,0x6f,0x1f,0xe2,0xe9,0xfe,0x7f,0x9f,0xe7,0xf9,
+  0xfe,0x7f,0x67,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xfd,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xf7,0xf9,0x7f,0xff,0xfb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xe8,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xef,
+  0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xef,0xfe,0xfd,0xbf,0xef,0xef,0x7f,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xf7,0xff,0xff,0xfd,0xff,0xf7,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x3b,0xfe,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,
+  0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xfe,0xfd,0xff,0xd6,0xf7,0xbd,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xf4,0x3f,0xff,0xff,0x4f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xfe,0xff,0xf2,0xfd,0xff,0xff,0xff,
+  0xf2,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xee,0x8f,0xff,0xfa,0xfe,0xbf,0xab,0xeb,
+  0xfa,0xbe,0xbf,0xab,0xcb,0xfa,0xbe,0xbf,0xaf,0xeb,0xde,0xaf,0xaf,0xeb,0xda,0xde,
+  0xaf,0xae,0xea,0xfa,0xde,0xbf,0xaf,0xeb,0xfa,0xff,0xc5,0xff,0xff,0xfa,0xfd,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xef,0xef,
+  0xff,0xdd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xf8,0x9f,0xff,0xff,0xff,
+  0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7e,0x65,0xff,0xff,
+  0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xdf,0xff,
+  0xff,0xfd,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xf2,0x7f,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe3,0xff,0xff,0xfe,0xfd,0xff,0x7f,
+  0xdf,0xf7,0xe3,0xfe,0x7f,0x9f,0xae,0xed,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0x9f,0xff,0xfb,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0x7f,
+  0xff,0x7d,0xdf,0xdd,0xff,0xbf,0x7f,0xea,0xff,0xbf,0xff,0xff,0xff,0xbf,0xff,0xff,
+  0xff,0xe1,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xe7,0xef,0xff,0xff,0xff,0xff,0xfb,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xff,0xff,0xf1,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
+  0xff,0xd7,0xfb,0x7d,0xff,0xfd,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,
+  0xff,0xff,0xff,0xff,0xcf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xfb,0x9f,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,
+  0xff,0xff,0xfe,0xff,0xff,0xd5,0xff,0xbf,0xbf,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xf4,0xff,0xff,0xc7,0xdf,0xff,0xfb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xef,0xfd,0xbf,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xfe,0xf7,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb7,0xff,0xff,0xbf,0xf7,0xff,0xff,0xfe,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf3,0xeb,0xff,0xff,0xff,0xfd,0xdf,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xfe,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xef,0xf7,0xfd,0xff,0x7f,0xdf,
+  0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfb,0xff,0xff,0xf7,0xfa,0xdf,0xef,0xff,0xff,0xbf,
+  0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xdf,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xb0,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe7,0xf9,0xff,0xff,0xf5,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xc6,0x6b,0xfc,
+  0xff,0x3b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xbf,0xaf,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xd7,0xcf,
+  0x7f,0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xfb,
+  0xfd,0xbf,0xf7,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,
+  0xff,0xdb,0x37,0xff,0xbd,0x6f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xeb,0xfa,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xaf,0xef,0xff,
+  0xff,0xff,0xbf,0xa6,0xff,0xdd,0xa7,0x77,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xfd,0x5f,0x57,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0x7d,
+  0xdf,0xff,0xff,0xff,0x7a,0xdf,0xfe,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xaf,0xeb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xbf,0xbf,0xff,0xff,0xff,0xf8,0xdf,0xff,0x7f,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xf5,0xfd,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xd7,0xf7,0xff,0xff,0xff,0xff,0xd3,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x7e,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xf5,0x7f,0xef,0xf9,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x9f,0xeb,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbe,0x07,0xfe,0xed,0xfb,0xfe,0xff,
+  0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xb7,0xfb,0xfe,0xff,0xbe,0xef,
+  0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xff,0xb1,0xbf,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xde,0xbf,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd5,0xff,
+  0xd7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xed,0x7f,0x5f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x5f,0xff,0xff,0xf4,
+  0xff,0xfa,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xa7,0xe9,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe9,0xff,0xff,
+  0xff,0x1f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xef,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0x7f,
+  0xff,0xff,0xeb,0xff,0xff,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,
+  0xf9,0xfe,0x7f,0x9f,0xf9,0xfe,0x7f,0x1f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xe9,0xfe,
+  0x2f,0x9f,0xe7,0xe3,0x7f,0xfd,0x7f,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xef,0xd7,0xf4,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,
+  0xff,0xff,0xff,0xff,0xfe,0x4f,0xff,0xaf,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xfa,0xfe,0x9d,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xef,0xff,0xff,0xff,0xff,0xed,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0x3f,0xfd,0xff,0xff,0xfd,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xf7,0xfd,0xff,0x77,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x83,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf7,0xff,0xff,0xff,0xff,0xef,0xfb,0xf7,0xff,0xff,0xf9,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xf5,0xff,0xff,0xff,0xff,0xc0,0xdd,0xff,0xad,0xeb,0x7a,
+  0xfe,0xbf,0xad,0xeb,0xfa,0xfe,0xbf,0xaf,0xeb,0xfa,0xfe,0x8f,0xe9,0x7a,0xbe,0xaf,
+  0xaf,0xea,0xfa,0xfe,0xbf,0x2b,0xeb,0xda,0xfe,0xbf,0xaf,0xfd,0x5f,0xfd,0xff,0xff,
+  0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,
+  0xff,0xf7,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,0xff,0xff,0xff,0xa9,0x5f,
+  0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0x7f,0xf7,0xff,0xff,0xff,0xff,0xfd,
+  0xfb,0xff,0xff,0xdf,0xff,0xf7,0xbf,0xef,0xf3,0xff,0xff,0xff,0xff,0xff,0xf9,0xff,
+  0x47,0xfd,0xf7,0xfd,0xff,0xff,0xf7,0xfe,0xff,0xff,0xff,0xdf,0xff,0xdf,0xff,0xff,
+  0xff,0xbf,0xaf,0xbf,0xff,0xfd,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xfe,0xbf,0xff,
+  0xff,0xc1,0xff,0xff,0xe7,0xf5,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xf3,0xff,0xff,0xff,0xff,0xbf,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,
+  0xff,0xfb,0xdf,0x1f,0xfd,0xdf,0xff,0xf3,0xff,0xff,0xff,0xef,0xf3,0xfc,0xff,0xfb,
+  0xff,0xfb,0xf6,0xfe,0xef,0xff,0xff,0xff,0xfd,0x7f,0x5b,0xff,0xff,0xff,0xff,0xff,
+  0xff,0x7f,0xff,0xff,0x97,0xff,0xd7,0x75,0x7d,0xbf,0x7f,0xfb,0xfb,0xfd,0xff,0xff,
+  0xd3,0xff,0xfd,0xbf,0x2f,0xc4,0xff,0xbf,0xff,0xfb,0x7f,0xbc,0xff,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xbe,0xff,0xff,0xff,0xff,0xef,0xfb,0xff,0xff,0xff,0xef,
+  0xff,0xff,0xff,0xff,0xe7,0x6f,0xf9,0xdf,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x5f,0xf7,0xf7,0xfe,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb5,0x7f,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xdf,0xfb,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xef,0xff,0xff,0xfb,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xff,0x7d,0xff,0x5f,0x5f,0xd7,0xff,
+  0xff,0xff,0xff,0xd6,0x75,0x5f,0xf7,0xde,0xff,0xff,0xff,0xdf,0xfd,0x3f,0xdf,0xf7,
+  0x5d,0xf7,0xdd,0xff,0xff,0x5f,0xff,0xff,0x7f,0xff,0xde,0xe7,0xdf,0x8f,0xfb,0xff,
+  0x7f,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xeb,0xfe,0xdf,0xbf,0xf7,0xfe,0xff,0xbf,
+  0xff,0xff,0xfc,0xff,0xbf,0xff,0xfb,0xff,0xff,0xbf,0xff,0xff,0x95,0xf7,0xff,0xff,
+  0x7f,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xff,0xfd,0xfb,0xb3,0xf7,0x6f,0xff,0xbf,
+  0xf7,0xbf,0xff,0xff,0xdf,0xd7,0xff,0xff,0x77,0xff,0xef,0xbf,0xfb,0xfc,0xbb,0xff,
+  0x8f,0xe7,0xf9,0x7e,0x7f,0x9b,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0xe7,
+  0xf9,0xf6,0x5f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xe7,0xf9,0xfe,0x7f,0x9f,0xfc,0x16,
+  0xff,0xf3,0xfa,0xff,0xb7,0xed,0xfb,0x7e,0xff,0xbf,0xcf,0xfb,0x7a,0xfe,0xbf,0xcf,
+  0xfe,0xfe,0xbd,0xcf,0xfb,0xfe,0xff,0xbf,0xcf,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xff,
+  0xa4,0xcf,0xfe,0x7f,0x9d,0xe7,0xfb,0xfe,0xff,0xbf,0xe7,0xb9,0xfe,0xff,0xbf,0xe7,
+  0x78,0xfd,0x9f,0x67,0xfb,0xf8,0xf5,0xaf,0x67,0xdb,0xfe,0xff,0xbf,0xef,0xeb,0xac,
+  0xff,0xfe,0x9f,0xff,0xdf,0xff,0xff,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xfe,
+  0xff,0xff,0xef,0xff,0xff,0xbf,0xf7,0x7f,0xff,0xff,0xbf,0xbf,0xff,0xff,0xff,0xfd,
+  0xfd,0xff,0xfd,0xc3,0xff,0xfb,0xde,0xf7,0xbf,0xef,0xfb,0xbe,0xff,0xae,0xe7,0xfb,
+  0xfe,0xff,0xbd,0xe7,0xfe,0xbd,0xbf,0xe7,0xfb,0xfe,0xef,0xbd,0xef,0xfb,0xfe,0xff,
+  0xbf,0xef,0xfb,0xff,0xfa,0x7f,0xfc,0xff,0x37,0xcf,0xf3,0xfc,0xff,0x3f,0xcf,0xd3,
+  0x7c,0xff,0x3f,0xcf,0xf3,0xff,0x3f,0xcf,0xf3,0xfe,0xef,0x3f,0xcf,0xf3,0xfc,0xff,
+  0x3f,0xcf,0xfb,0xf6,0xef,0xfe,0x0f,0xff,0xb7,0xed,0xfb,0x7e,0xff,0xbf,0x6f,0xfb,
+  0x7e,0xdb,0xbf,0xef,0xfb,0x7a,0xdf,0xed,0xeb,0x7e,0xff,0xbe,0xef,0xdb,0x7e,0xff,
+  0xbf,0xcf,0xfb,0xfe,0xff,0xbf,0xfb,0xe5,0xff,0xfb,0xfe,0xff,0xbf,0xe5,0xf9,0x7e,
+  0x5f,0xbf,0xef,0xf9,0x7e,0x5f,0xbf,0xef,0xfa,0xff,0xbf,0xe5,0xf9,0x7e,0xdf,0xbf,
+  0xe5,0xf9,0x7e,0x5f,0x97,0xed,0xf9,0x7f,0xf9,0xbf,0xff,0x5b,0xd7,0xf5,0xfd,0xff,
+  0x7d,0xdf,0xf5,0xfd,0x7f,0x7f,0xdb,0xf5,0xfd,0x37,0xd7,0xf5,0x7d,0xf7,0x7f,0xd7,
+  0xf5,0xfd,0xef,0x7b,0xdf,0xf7,0xfd,0x7f,0x7f,0xff,0x97,0xff,0xf7,0xfd,0xff,0x7f,
+  0xff,0xff,0xbf,0xff,0x7f,0xdf,0xff,0xff,0xff,0x7f,0xdf,0xbd,0xff,0x7f,0xff,0xff,
+  0xfd,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xdf,0xff,0xfb,0xf0,0xff,0xed,0xff,0x6f,
+  0xdb,0xf6,0xfd,0xb7,0xed,0xdf,0xf7,0xfd,0xff,0x7f,0xde,0xf5,0xfb,0x6f,0xdb,0xf7,
+  0xfd,0xbf,0x7d,0xdb,0xf7,0xff,0xff,0x6f,0xfb,0xf7,0xfd,0xff,0x7e,0xdf,0xff,0xf7,
+  0xff,0xff,0xff,0xff,0xff,0xef,0xff,0xff,0xdf,0xfb,0xff,0xff,0xff,0xff,0x7f,0xff,
+  0xfb,0xff,0xff,0xbf,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xff,0xff,0xff,0xdb,0xfd,
+  0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xd7,0xf7,0xfd,0xff,0x7d,0xdf,0xf7,0xff,
+  0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0x7f,0xdf,0xf7,0xfd,0xff,0xf5,
+  0x7b,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xff,0xff,0xfe,0xff,0xff,0xdf,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xff,0xfc,0xff,0xff,0xdf,0xff,0xff,0xff,
+  0xff,0xaf,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0xff,0xff,0xf7,
+  0xfb,0xff,0xb7,0xff,0xff,0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,
+  0xff,0xff,0xfd,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbf,0xef,0xff,0xff,
+  0xff,0xff,0x7f,0xf4,0xff,0xff,0xef,0xff,0xff,0xfe,0xff,0xef,0xff,0xfe,0xff,0xff,
+  0xcf,0xfb,0xff,0xbe,0x3f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0x57,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,
+  0xff,0xff,0xff,0xdf,0xff,0xff,0xff,0xff,0xff,0xfd,0xff,0x7f,0xdf,0xff,0xfd,0xff,
+  0x7f,0xdf,0xf7,0xff,0xff,0xff,0xee,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xef,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xfe,0x9f,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7f,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xef,0x8b,0xdf,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+  0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf5,0x7f,0xff,0xfb,0xfe,0xff,
+  0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfe,0xff,0xbf,0xef,
+  0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xff,0xbf,0xef,0xfb,0xfe,0xcf,0xff,0xcf,0xf3,
+  0xfc,0xff,0xbf,0xef,0xfb,0xfc,0xff,0x3f,0xef,0xf3,0xfc,0xff,0x3f,0xb3,0xfc,0xff,
+  0x3f,0xef,0xf3,0xfc,0xff,0x3f,0xef,0xf3,0xfe,0xff,0x3f,0xef,0xff,0xfd,0xff,0xff,
+  0xbf,0xef,0xff,0xff,0xef,0xff,0xfe,0xff,0xff,0xff,0xfb,0xff,0xfb,0xff,0xf7,0xff,
+  0xfb,0xff,0xff,0xff,0xff,0xfb,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x3f,
+  0xfe,0xfe,0xbb,0xaf,0xeb,0xfa,0xff,0xbf,0xae,0xeb,0xba,0xfe,0xfb,0xee,0xeb,0xfb,
+  0xbb,0xae,0xef,0xbe,0xff,0xbb,0xee,0xef,0xbe,0xff,0xfb,0xef,0xfb,0xbe,0xef,0xff,
+  0x17,0xff,0x75,0xad,0xab,0x4a,0xba,0xef,0xeb,0xaf,0x6a,0xda,0xae,0xb5,0xfb,0x7a,
+  0xd2,0xbd,0xab,0x7a,0x5f,0xaf,0xed,0x7b,0x7a,0x5f,0xaf,0xe5,0xfa,0xfe,0xdb,0xbf,
+  0xe2,0xd4,0xff,0xff,
diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds
new file mode 100755
index 0000000..fef5b52
--- /dev/null
+++ b/board/esd/dasa_sim/u-boot.lds
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o		(.text)
+    cpu/ppc4xx/traps.o		(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o		(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/extable.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_generic/crc32.o		(.text)
+
+    common/cmd_boot.o		(.text)
+    common/cmd_bootm.o		(.text)
+    common/cmd_flash.o		(.text)
+    common/cmd_mem.o		(.text)
+    common/cmd_nvedit.o		(.text)
+    common/console.o		(.text)
+    common/lists.o		(.text)
+    common/main.o		(.text)
+
+    board/esd/dasa_sim/flash.o	(.text)
+    common/cmd_nvedit.o	(.text)
+    board/esd/dasa_sim/cmd_dasa_sim.o	(.text)
+    net/bootp.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile
new file mode 100755
index 0000000..a11ee82
--- /dev/null
+++ b/board/esd/dp405/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/dp405/config.mk b/board/esd/dp405/config.mk
new file mode 100755
index 0000000..3041b77
--- /dev/null
+++ b/board/esd/dp405/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd VOH405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x00FC0000
diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c
new file mode 100755
index 0000000..fd51f7f
--- /dev/null
+++ b/board/esd/dp405/dp405.c
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+
+/* fpga configuration data - not compressed, generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+int filesize = sizeof(fpgadata);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * Reset CPLD via GPIO13 (CS4) pin
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 13));
+	udelay(1000); /* wait 1ms */
+	out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 13));
+	udelay(1000); /* wait 1ms */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+	unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
+				   0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
+	unsigned char id1, id2;
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming DP405");
+	} else {
+		puts(str);
+	}
+
+	id1 = trans[(~(in32(GPIO0_IR) >> 5)) & 0x0000000f];
+	id2 = trans[(~(in32(GPIO0_IR) >> 9)) & 0x0000000f];
+	printf(" (ID=0x%1X%1X, PLD=0x%02X)\n", id2, id1, in8(0xf0001000));
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/dp405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/dp405/fpgadata.c b/board/esd/dp405/fpgadata.c
new file mode 100755
index 0000000..eae8457
--- /dev/null
+++ b/board/esd/dp405/fpgadata.c
@@ -0,0 +1,1812 @@
+  0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,
+  0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00,
+  0xf9,0x60,0x40,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00,
+  0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08,
+  0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
+  0x08,0xea,0x08,0x00,0x00,0x00,0x32,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x04,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x00,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x00,0x24,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x00,0x28,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x30,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
+  0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,
+  0x40,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x80,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x00,0x00,0x03,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,
+  0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x84,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x09,0x00,0x00,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x90,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
+  0xa0,0x00,0x00,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa4,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xb0,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc0,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x09,0x00,0x00,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x04,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x08,0x00,
+  0x00,0x01,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x0c,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x10,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x20,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x24,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x28,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x30,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x01,0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x01,0x44,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x01,0x48,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x01,0x4c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,
+  0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x50,
+  0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x03,0x09,0x00,0x01,0x80,0x00,0x00,0x10,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x01,0x84,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x88,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x90,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x01,0xa0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x01,0xa4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x01,0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x01,0xac,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
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+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x33,0x24,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x33,0x28,0x00,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x33,0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x33,0x30,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x33,0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x33,0x44,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,
+  0x48,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0x4c,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x33,0x50,0x00,0x00,0x00,0x03,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,
+  0x00,0x33,0x80,0x00,0x00,0x20,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x33,0x84,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x09,0x00,0x33,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x33,0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x33,0x90,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x33,0xa0,0x00,0x00,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x33,0xa4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,
+  0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xac,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xb0,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc0,0x00,0x00,
+  0x00,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc4,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc8,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xcc,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x09,0x00,0x33,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x34,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x04,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,
+  0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x0c,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x10,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x20,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x24,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x28,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x2c,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x30,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x44,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x34,0x48,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x34,0x4c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x34,0x50,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x34,0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,
+  0x00,0x09,0x00,0x34,0x84,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x88,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x8c,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x90,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x34,0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x34,0xac,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x34,0xb0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x34,0xc0,0x00,0x80,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x34,0xc4,0x00,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x34,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,
+  0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
+  0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0xd0,0x00,0x00,0x00,
+  0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,
+  0x09,0x00,0x35,0x00,0x00,0x80,0x00,0x29,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x04,
+  0x00,0x00,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x09,0x00,0x35,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x35,0x0c,0x00,0x00,0xf4,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x35,0x10,0x00,0x00,0xc4,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x35,0x20,0x00,0x1c,0x40,0x99,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x35,0x24,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x35,0x28,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
+  0x2c,0x00,0x00,0xa0,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x30,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x40,0x00,
+  0x00,0x00,0x65,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x44,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x48,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x4c,0x00,0x00,0x60,0x81,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x50,0x00,0x00,0x40,0x03,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0x80,0x20,
+  0x00,0xcc,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x84,0x20,0x00,0xc8,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x35,0x88,0x20,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
+  0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x90,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa0,0xc0,
+  0x80,0x14,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa4,0xc0,0x80,
+  0x54,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa8,0xc0,0x00,0x94,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x00,0x40,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x00,0x40,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc0,0x08,0x00,0xc4,0x09,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc4,0x08,0x00,0xc4,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x08,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x35,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x35,0xd0,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x00,0x00,0x80,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,
+  0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff,
+  0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00,
diff --git a/board/esd/dp405/u-boot.lds b/board/esd/dp405/u-boot.lds
new file mode 100755
index 0000000..43f7765
--- /dev/null
+++ b/board/esd/dp405/u-boot.lds
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile
new file mode 100755
index 0000000..5ec4a4f
--- /dev/null
+++ b/board/esd/du405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/du405/config.mk b/board/esd/du405/config.mk
new file mode 100755
index 0000000..d091d96
--- /dev/null
+++ b/board/esd/du405/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd CPCIISER4 boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0xFFFD0000
+#TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
new file mode 100755
index 0000000..26e8341
--- /dev/null
+++ b/board/esd/du405/du405.c
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "du405.h"
+#include <asm/processor.h>
+#include <ppc4xx.h>
+#include <405gp_i2c.h>
+#include <command.h>
+
+/*cmd_boot.c*/
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
+
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+#if 0
+#define FPGA_DEBUG2
+#endif
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] = {
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int board_early_init_f (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int index, len, i;
+	int status;
+
+#ifdef FPGA_DEBUG
+	/* set up serial port with default baudrate */
+	(void) get_clocks ();
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init ();
+	console_init_f ();
+#endif
+
+	/*
+	 * Boot onboard FPGA
+	 */
+	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
+	if (status != 0) {
+		/* booting FPGA failed */
+#ifndef FPGA_DEBUG
+		/* set up serial port with default baudrate */
+		(void) get_clocks ();
+		gd->baudrate = CONFIG_BAUDRATE;
+		serial_init ();
+		console_init_f ();
+#endif
+		printf ("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf ("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i = 0; i < 4; i++) {
+			len = fpgadata[index];
+			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
+			index += len + 3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i = 20; i > 0; i--) {
+			printf ("Rebooting in %2d seconds \r", i);
+			for (index = 0; index < 1000; index++)
+				udelay (1000);
+		}
+		putc ('\n');
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) DUART_A; active high; level sensitive
+	 * IRQ 27 (EXT IRQ 2) DUART_B; active high; level sensitive
+	 * IRQ 28 (EXT IRQ 3) unused; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFFB1);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 100 us
+	 */
+	mtebc (epcr, 0xb8400000);
+
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	unsigned long cntrl0Reg;
+
+	/*
+	 * Setup UART1 handshaking: use CTS instead of DSR
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	int index;
+	int len;
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming DU405");
+	} else {
+		puts (str);
+	}
+
+	puts ("\nFPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf ("%s ", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+
+	putc ('\n');
+
+	/*
+	 * Reset external DUART via FPGA
+	 */
+	*(volatile unsigned char *) FPGA_MODE_REG = 0xff;	/* reset high active */
+	*(volatile unsigned char *) FPGA_MODE_REG = 0x00;	/* low again */
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+
+long int initdram (int board_type)
+{
+	return (16 * 1024 * 1024);
+}
+
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
diff --git a/board/esd/du405/du405.h b/board/esd/du405/du405.h
new file mode 100755
index 0000000..768e843
--- /dev/null
+++ b/board/esd/du405/du405.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c
new file mode 100755
index 0000000..14549c0
--- /dev/null
+++ b/board/esd/du405/flash.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+
+	if (size_b1) {
+		mtdcr (ebccfga, pb0cr);
+		pbcr = mfdcr (ebccfgd);
+		mtdcr (ebccfga, pb0cr);
+		base_b1 = -size_b1;
+		pbcr = (pbcr & 0x0001ffff) | base_b1 |
+				(((size_b1 / 1024 / 1024) - 1) << 17);
+		mtdcr (ebccfgd, pbcr);
+		/*          printf("pb1cr = %x\n", pbcr); */
+	}
+
+	if (size_b0) {
+		mtdcr (ebccfga, pb1cr);
+		pbcr = mfdcr (ebccfgd);
+		mtdcr (ebccfga, pb1cr);
+		base_b0 = base_b1 - size_b0;
+		pbcr = (pbcr & 0x0001ffff) | base_b0 |
+				(((size_b0 / 1024 / 1024) - 1) << 17);
+		mtdcr (ebccfgd, pbcr);
+		/*            printf("pb0cr = %x\n", pbcr); */
+	}
+
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+				base_b1 + size_b1 - monitor_flash_len,
+				base_b1 + size_b1 - 1, &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect (FLAG_PROTECT_CLEAR,
+				base_b0 + size_b0 - monitor_flash_len,
+				base_b0 + size_b0 - 1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/board/esd/du405/fpgadata.c b/board/esd/du405/fpgadata.c
new file mode 100755
index 0000000..fd80d2c
--- /dev/null
+++ b/board/esd/du405/fpgadata.c
@@ -0,0 +1,703 @@
+ 0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
+ 0x64,0x75,0x72,0x61,0x67,0x34,0x30,0x35,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
+ 0x73,0x32,0x30,0x78,0x6c,0x74,0x71,0x31,0x34,0x34,0x00,0x63,0x00,0x0b,0x32,0x30,
+ 0x30,0x32,0x2f,0x30,0x32,0x2f,0x32,0x31,0x00,0x64,0x00,0x09,0x31,0x32,0x3a,0x35,
+ 0x31,0x3a,0x30,0x38,0x00,0x65,0xe2,0x01,0x00,0x00,0x2b,0x98,0xff,0x30,0xe6,0xe5,
+ 0xe5,0x02,0x04,0x01,0xe6,0x04,0x01,0x0d,0x04,0x04,0x02,0x01,0x04,0x04,0x03,0x07,
+ 0x01,0x03,0x01,0x04,0x11,0x01,0x06,0x02,0x15,0x09,0x02,0x05,0x07,0x02,0x02,0x01,
+ 0x09,0x03,0x07,0x01,0x03,0x01,0x0b,0x05,0x03,0x01,0x07,0x08,0xe5,0xe5,0x24,0x05,
+ 0x09,0x11,0x01,0x03,0x03,0x05,0x0d,0x09,0x0b,0x09,0x01,0x1d,0x09,0x13,0x03,0x05,
+ 0x12,0xe6,0x11,0x01,0x03,0x02,0x02,0x03,0x03,0x01,0x15,0x01,0x02,0x28,0x01,0x05,
+ 0x02,0xe5,0xe5,0x02,0x02,0x02,0x0d,0x02,0x02,0x03,0x02,0xe5,0xe5,0x14,0x01,0x02,
+ 0xe5,0x12,0x0b,0x03,0x0f,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x06,0x02,0x09,
+ 0x06,0xe7,0x05,0x04,0x06,0x02,0x06,0x02,0x09,0x07,0xe6,0x08,0x09,0x07,0xe6,0x08,
+ 0x09,0x0e,0xe5,0xe6,0x0d,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x07,0x09,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0x03,0x05,0xe8,0x04,0xe6,0x02,0x05,0xe6,0xe5,
+ 0x04,0xe6,0x06,0x03,0x05,0xe5,0xe6,0x04,0xe5,0x07,0x09,0xe5,0xe6,0x04,0x09,0x09,
+ 0x09,0xe8,0x46,0x09,0x14,0xe5,0x06,0x0b,0x09,0x15,0x1d,0x24,0x02,0xe5,0xe5,0x45,
+ 0x08,0x15,0x33,0x1d,0x28,0x70,0xe5,0x09,0x09,0x14,0x42,0x02,0xe5,0x30,0x27,0x01,
+ 0x15,0x1b,0x1d,0x32,0x01,0x01,0x5b,0x0c,0x51,0x24,0x01,0xe5,0xe5,0x28,0xe5,0x1c,
+ 0x25,0x53,0x19,0xe5,0x01,0x2b,0x45,0x6c,0xe5,0xe6,0x35,0x09,0x07,0x01,0x09,0x09,
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+ 0x6e,0xe6,0x70,0x6c,0x01,0xe6,0x70,0x6c,0xe6,0xe5,0x12,0x5d,0x36,0x15,0x21,0xe6,
+ 0x70,0x6c,0x02,0xe5,0x70,0x6c,0x01,0xe6,0x4c,0x23,0x6e,0xe6,0x02,0x6d,0x6c,0x03,
+ 0x4d,0x91,0x02,0xe5,0xdb,0xe9,0x01,0xdb,0xe5,0x01,0xe6,0xd9,0xe6,0x01,0xe5,0x01,
+ 0x01,0xd4,0x01,0x05,0xe5,0x03,0xd4,0x04,0xe8,0x01,0xd8,0x02,0xe6,0xe5,0xdf,0xe6,
+ 0x01,0xd8,0x05,0xe6,0xdb,0x03,0xe5,0xdd,0xe5,0x01,0xde,0x01,0xe6,0xdd,0xe6,0xe6,
+ 0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x0d,0xe6,0x01,0x02,0xd8,0x03,0x01,0xe5,0xde,0xe5,0xe5,0xe5,
+ 0xd9,0x01,0xe6,0xe5,0xdd,0x01,0xe6,0xde,0xe5,0xe5,0x14,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x08,0x01,0xdf,0x02,0xe1,0xe5,0xdd,0xe8,0xdd,0x01,0xe6,0x02,0xdb,0xe7,
+ 0xe5,0x09,0x04,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x01,0x05,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x08,0x01,0xe6,0xe5,0x51,
+ 0x13,0x79,0x01,0xe5,0x14,0x4d,0x17,0x11,0x4e,0xe6,0x01,0x71,0x6c,0x01,0xe6,0x70,
+ 0x6c,0x01,0xe6,0x70,0x6c,0xe6,0xe5,0x12,0x31,0x2b,0x4a,0x15,0x0f,0x31,0x3f,0x6d,
+ 0xe7,0x70,0x68,0x03,0xe5,0xe6,0xe5,0x6e,0x6c,0xe8,0x70,0x6e,0x01,0x02,0xdf,0xe5,
+ 0x08,0xd2,0x01,0x01,0xe5,0xdf,0x01,0xe6,0xd9,0x01,0xe6,0xe5,0x01,0x01,0xd4,0x01,
+ 0x03,0x02,0x04,0xce,0xe5,0x03,0x05,0xe7,0xd3,0x06,0x02,0x03,0xd5,0x07,0xe5,0xe7,
+ 0xda,0x03,0x01,0xe5,0xdc,0xe9,0xdd,0x02,0xe5,0x08,0xd3,0x04,0x0a,0x01,0xd1,0xe5,
+ 0xe7,0x07,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe6,0xe6,0x01,0xd3,0x04,0x02,0x03,0xd5,0x08,
+ 0x01,0x01,0xe0,0x01,0xde,0xe5,0xe6,0xdf,0x01,0xe5,0x13,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x09,0xe5,0xdd,0x03,0xe0,0x01,0xe5,0xdc,0xe8,0xdf,0x01,0xdf,0xe5,0xe5,
+ 0x10,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,
+ 0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x0c,0xe6,0xdd,0xe9,0x50,
+ 0x33,0x56,0x01,0x02,0x01,0x03,0x2c,0x3e,0x6c,0xe5,0xe7,0x6f,0x6b,0x01,0xe5,0xe5,
+ 0x12,0x5d,0x6e,0xe7,0x08,0x1f,0x09,0x3c,0x4a,0x15,0x0a,0xe9,0x70,0x6c,0x02,0xe5,
+ 0x05,0x6a,0x6c,0xe6,0xe5,0x70,0x6e,0xe6,0x70,0x6d,0xe7,0x09,0x09,0x09,0xbf,0x01,
+ 0x01,0xde,0xe5,0xe6,0x26,0xba,0xdc,0x01,0x01,0xe6,0x01,0x01,0xd4,0x01,0x03,0xe7,
+ 0x03,0xcf,0xe5,0x02,0x04,0x02,0xe5,0xe6,0xd7,0x03,0x01,0xe6,0xe5,0x06,0x01,0xd0,
+ 0x02,0xe6,0xda,0x02,0xe5,0x01,0xdd,0xe6,0xe6,0xda,0xe5,0x02,0xe7,0x07,0xd3,0x01,
+ 0xe7,0x09,0x01,0xd5,0xe5,0x07,0x05,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x06,0xe9,0xd5,0x04,
+ 0x05,0xe5,0xd2,0x0a,0x02,0xe5,0xdf,0x01,0xdf,0xe8,0xdd,0x01,0xe5,0x14,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0x01,0xe5,0xd8,0x05,0xe7,0xde,0xe5,0xe6,0xdc,0x02,
+ 0xe5,0x02,0x08,0xd3,0x01,0x32,0xab,0xe6,0xe5,0x10,0x01,0x02,0x04,0x01,0x07,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x09,0x01,
+ 0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x07,0x01,0x0a,0x02,0xe5,0xde,0x02,0xe5,0x64,0x15,0x13,0x4c,0x02,0xe6,0x70,0x6d,
+ 0xe5,0xe6,0x6f,0x6b,0x02,0x01,0x13,0x5d,0x64,0x07,0xe5,0xe7,0x43,0x2b,0x61,0x09,
+ 0xe5,0x02,0x25,0x4b,0x6e,0x01,0x06,0x20,0x49,0x6d,0xe5,0xe5,0x70,0x6c,0x03,0x03,
+ 0x6d,0x6e,0xe6,0xe1,0xdc,0x01,0xe5,0x01,0xe3,0xe7,0xd9,0x03,0xe6,0x01,0x01,0xd4,
+ 0x01,0x02,0x01,0x01,0x04,0xd4,0x06,0x01,0xd4,0xe5,0x04,0x02,0x01,0xe6,0xdc,0x01,
+ 0x02,0x02,0xd8,0x03,0x02,0x01,0xdb,0x01,0xe5,0xe5,0xdd,0xe5,0x01,0xdd,0x01,0xe7,
+ 0xdf,0xe7,0x0d,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x02,0x01,0x02,0xd8,0x04,0xe6,0xdd,0x02,0xe5,
+ 0xdd,0x01,0xe6,0xdd,0xe5,0x01,0xe5,0xde,0x01,0x15,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x09,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x06,0x01,0x01,0xde,0x01,0x01,0xe3,0xe6,0xdc,0xe5,0x01,0xdf,0xe7,0x3b,0x10,
+ 0x92,0xe6,0x10,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x07,0x01,0x01,0x05,0x01,0x07,
+ 0x01,0xe5,0x05,0x01,0x07,0x01,0x07,0x01,0x09,0x01,0x07,0x01,0x07,0x01,0x07,0x01,
+ 0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x01,0x05,0x01,0x07,0x01,0x0d,
+ 0xe5,0x50,0x34,0x58,0x02,0xe5,0x50,0x8a,0xe9,0xe5,0x02,0x5f,0x0a,0xe5,0x09,0x12,
+ 0x51,0xe5,0x03,0x49,0x22,0x14,0x13,0x42,0xe5,0x01,0xe6,0x01,0x6d,0x6f,0xe6,0x2b,
+ 0x24,0x1e,0x52,0xe5,0x0b,0x0a,0xe5,0x01,0xe6,0x23,0x05,0x01,0x3f,0x03,0x6c,0xe5,
+ 0xe6,0x26,0x06,0x42,0x6c,0x01,0xe7,0x6f,0x6d,0xe7,0x70,0x6d,0x01,0xe5,0x30,0x3d,
+ 0x5f,0x0e,0x01,0x01,0x2d,0x97,0x08,0xe5,0x0d,0xe5,0x01,0x09,0x23,0x44,0x52,0x08,
+ 0x11,0xe6,0x02,0x0b,0xe5,0x01,0x06,0x06,0xe7,0x07,0xe5,0x05,0xe7,0x05,0xe7,0x05,
+ 0xe7,0xe5,0x05,0xe5,0x08,0x08,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0b,0x02,0xe6,0x0d,0x01,
+ 0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x02,0x02,0x01,
+ 0x01,0x08,0xe5,0x0d,0x02,0x01,0x0b,0x09,0x09,0x09,0x07,0x01,0x01,0xe5,0x05,0x09,
+ 0x09,0x02,0x06,0x09,0x0d,0x02,0xe5,0x0f,0x08,0x13,0x09,0x1d,0x09,0x04,0x04,0x08,
+ 0x02,0x04,0x04,0x09,0x04,0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x02,0x14,0x41,
+ 0x87,0x01,0xe6,0x18,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x13,0x0b,0x09,0x04,0x04,
+ 0x09,0x04,0x04,0x02,0x06,0x09,0x09,0x09,0x09,0x0e,0x01,0x01,0x0d,0xe5,0x07,0xe6,
+ 0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x01,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0e,0xe8,0x02,0x05,0x03,0x09,0x01,0x04,0x02,0x01,
+ 0x07,0x09,0x09,0x01,0x07,0x01,0x07,0x09,0x07,0x01,0x0b,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x14,0x0e,0x09,0x09,0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,
+ 0x09,0xe5,0xe5,0x05,0x09,0xe5,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x0f,0x0e,0x09,0x01,0x07,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x01,0x07,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x01,0xe6,0x47,
+ 0x11,0x76,0x0c,0x01,0x01,0x0e,0x05,0x03,0x05,0x03,0x09,0x05,0x03,0x09,0x09,0x09,
+ 0x09,0x09,0x06,0x01,0x02,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,
+ 0xe8,0x0f,0x13,0x1d,0x09,0x24,0x70,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,
+ 0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,0x01,0xe5,0x46,
+ 0x96,0x02,0xe5,0x70,0x6e,0x01,0x22,0x1d,0x09,0x13,0x11,0xe5,0x67,0x06,0xe5,0x06,
+ 0x06,0x06,0x02,0x06,0x02,0x06,0x16,0x06,0x02,0x13,0x06,0x79,0xe5,0xe5,0x3a,0x1d,
+ 0x33,0x1d,0x09,0x2a,0xe6,0x06,0x05,0x08,0xe5,0x07,0xe5,0x07,0x14,0x08,0xe5,0x12,
+ 0x08,0x0a,0x65,0x06,0x03,0x71,0x66,0x05,0xe5,0xe6,0xdd,0xe5,0xe6,0x0c,0xe5,0x04,
+ 0xe8,0x04,0xe8,0x04,0xe6,0x06,0x09,0x02,0xe5,0x04,0xe8,0x04,0x09,0x02,0xe5,0x04,
+ 0xe6,0x06,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x01,0xe6,0x0c,
+ 0xe6,0x05,0xe7,0x05,0xe7,0x05,0x01,0xe5,0x08,0x07,0xe6,0x05,0xe7,0x08,0x07,0xe6,
+ 0x05,0x02,0x07,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x08,0xe5,0x07,0xe5,0x0e,
+ 0xe5,0xe5,0x33,0x2d,0x0e,0x10,0x13,0x48,0x02,0x11,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x01,0x0d,0x03,0x05,0x03,0x01,0x0d,0x03,0x01,0x03,0x07,0x09,0x09,0x09,0x09,
+ 0x03,0x05,0x09,0x09,0x11,0x13,0x01,0xe5,0x0a,0x06,0x09,0x09,0x04,0x01,0x02,0x01,
+ 0x03,0x07,0x05,0x09,0x01,0x03,0x07,0x0e,0xe5,0x02,0x06,0xe5,0x02,0x04,0x04,0x01,
+ 0x07,0x04,0x04,0x05,0x03,0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x02,0x04,0x04,0x06,
+ 0x01,0x03,0xe5,0xe5,0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,
diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds
new file mode 100755
index 0000000..1cf375f
--- /dev/null
+++ b/board/esd/du405/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile
new file mode 100755
index 0000000..9340a32
--- /dev/null
+++ b/board/esd/hh405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/hh405/config.mk b/board/esd/hh405/config.mk
new file mode 100755
index 0000000..7129ad5
--- /dev/null
+++ b/board/esd/hh405/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd VOH405 boards
+#
+
+#TEXT_BASE = 0xFFF00000
+TEXT_BASE = 0xFFF80000
+#TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x00FC0000
diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/hh405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/hh405/fpgadata.c b/board/esd/hh405/fpgadata.c
new file mode 100755
index 0000000..58ee3a8
--- /dev/null
+++ b/board/esd/hh405/fpgadata.c
@@ -0,0 +1,2520 @@
+  0x1f,0x8b,0x08,0x08,0x9c,0xc4,0xe8,0x42,0x00,0x03,0x68,0x68,0x34,0x30,0x35,0x5f,
+  0x31,0x5f,0x30,0x35,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x0f,0x78,0x14,0xd7,0x91,
+  0x2f,0x0c,0x57,0x9f,0x6e,0x89,0xa3,0xe9,0x91,0xa6,0x91,0x84,0x57,0xb6,0x31,0x6e,
+  0x8d,0x04,0x1e,0x94,0x91,0x18,0x46,0x58,0xc8,0x42,0x8c,0x5a,0x23,0xd9,0x19,0x1b,
+  0x6c,0x26,0x8e,0x93,0x65,0x77,0xfd,0xe5,0x0e,0x84,0x64,0x95,0xbc,0xc4,0x2b,0x3b,
+  0xb9,0x7b,0x49,0xd6,0xeb,0x1c,0x8d,0x04,0x8c,0x90,0x0c,0x03,0x28,0x31,0x4e,0x58,
+  0x6f,0x23,0x64,0x5b,0x38,0x24,0x3b,0x08,0x0c,0x02,0x1c,0xdc,0xc2,0xb2,0x2d,0xfe,
+  0x18,0x2b,0x0e,0xeb,0xe0,0x3f,0x71,0x06,0x47,0x26,0xb2,0x23,0xdb,0x32,0xc6,0x8e,
+  0x04,0x02,0xde,0x3a,0x3d,0x92,0xa6,0x47,0x64,0xf7,0xe6,0xbe,0xf7,0xf9,0xde,0x6f,
+  0x9f,0xe7,0xbb,0xf2,0xf3,0xec,0x9e,0xb4,0x8e,0x9a,0xee,0xd3,0xe7,0x54,0xfd,0xaa,
+  0xea,0x57,0x55,0x90,0xe1,0x18,0x4e,0xfc,0x07,0x20,0xac,0x00,0x47,0x5d,0xdd,0x02,
+  0xcf,0xad,0xff,0x6d,0xfe,0x7f,0xf3,0xdc,0x5a,0xf2,0xc0,0xd7,0x57,0xc1,0x4a,0x90,
+  0xbd,0xdf,0xbd,0xd5,0xf3,0x8d,0xef,0x3d,0x38,0x7f,0xc1,0x02,0xf8,0x3a,0xfe,0x2f,
+  0x8f,0xe7,0xd6,0x79,0x9e,0x85,0xf3,0xbc,0xe5,0xb0,0x0a,0x32,0xe6,0x97,0x56,0x2c,
+  0xf0,0x56,0x78,0x3d,0xf0,0x0d,0x10,0x4a,0x3b,0xae,0xe2,0xcf,0x33,0x8f,0x7f,0xe5,
+  0x9b,0x1e,0x60,0x02,0x00,0x4c,0xf3,0x08,0x21,0xfe,0xff,0x65,0x8f,0xa0,0x0a,0xc0,
+  0xaa,0x8a,0x3d,0x60,0xf0,0xff,0x0d,0xe3,0xbf,0xcf,0xf0,0x80,0x6a,0xfd,0xdf,0x82,
+  0x07,0x34,0x08,0x82,0xd6,0xca,0xb2,0xe1,0x2f,0xf8,0xa1,0x12,0x9b,0x18,0xfe,0x45,
+  0xf3,0x61,0x72,0xfe,0xd5,0xe3,0xec,0x3f,0x9c,0x94,0xfc,0xa9,0x3a,0xaf,0x8f,0x8f,
+  0x18,0xf1,0xfc,0xcf,0xa7,0x0b,0x01,0x98,0xb8,0xeb,0x0f,0xdf,0xfc,0x4b,0xee,0xbf,
+  0xf0,0xf3,0x89,0xfb,0xff,0xaf,0xce,0x07,0xe5,0x2f,0x98,0x8e,0xef,0x3b,0x31,0xf8,
+  0xa1,0x22,0x68,0xb0,0x1c,0xd2,0x41,0x60,0x10,0x82,0xbc,0xff,0x60,0xb0,0xb0,0x77,
+  0x62,0xfe,0xd1,0xb4,0x31,0xef,0x29,0x71,0x61,0x7e,0xd6,0xe7,0x62,0x25,0xbc,0x0a,
+  0x0b,0x8c,0xcc,0x11,0xf1,0x0a,0x8c,0x42,0x45,0x9f,0x3d,0x2e,0x8e,0xc1,0xc7,0x50,
+  0x05,0x77,0xb3,0x1c,0x0f,0xd4,0x8f,0xcf,0x37,0xf2,0x9e,0x57,0x8e,0xab,0x5e,0x95,
+  0x7e,0x4e,0x7e,0x01,0x2d,0xe0,0x8c,0xdb,0xbb,0xc9,0x47,0xd0,0xad,0x16,0xbc,0x69,
+  0xef,0xc4,0xc1,0x06,0x56,0xa2,0xd2,0x08,0x89,0x49,0x13,0xab,0xd8,0x27,0xed,0x86,
+  0x2d,0xb6,0x39,0xb0,0x61,0x01,0x91,0x60,0xab,0x50,0x62,0xe4,0x79,0xc8,0x49,0x38,
+  0x2c,0xbb,0x5e,0xa4,0x1e,0x32,0x04,0x3b,0xc1,0x0d,0x54,0x99,0xe3,0x15,0x26,0xef,
+  0x8f,0xf3,0x7f,0x02,0x4e,0x0f,0x8d,0x39,0x77,0x6b,0x3f,0x65,0x45,0xf1,0xbc,0x18,
+  0x4e,0x3b,0xbc,0x41,0x35,0x32,0x3a,0xc8,0x50,0xd8,0x46,0x4b,0x08,0xdd,0x8c,0xf7,
+  0x0f,0x8d,0xcf,0xaf,0x9e,0x3e,0x04,0xbf,0x82,0x32,0x4f,0x56,0x4c,0x74,0x85,0xdf,
+  0x3a,0xeb,0x1b,0x76,0xc7,0x6a,0x86,0x60,0x94,0x55,0xf4,0xb4,0xea,0xe2,0x71,0xe9,
+  0x8f,0xbf,0xf2,0x45,0xdd,0x11,0x41,0x91,0x26,0xee,0xaf,0x0b,0xcf,0xc1,0xc7,0xb4,
+  0x0a,0x1c,0x9e,0x1b,0xfb,0xc8,0x7b,0xb0,0xd0,0x98,0x36,0x2c,0x8e,0x09,0x97,0x33,
+  0x9e,0x37,0xb2,0x7a,0xc4,0x0f,0xe0,0xa2,0xe4,0x63,0x0e,0x2a,0x0e,0xc2,0xc4,0xfd,
+  0xfb,0x95,0xdd,0xf4,0x7d,0xcd,0x0b,0xfc,0xfe,0xd2,0x1f,0x7b,0x7c,0x41,0x7b,0xac,
+  0x60,0x08,0x2e,0x41,0x99,0x61,0x67,0xe2,0xfb,0xf0,0x47,0xcd,0x13,0xb5,0x47,0x65,
+  0x8f,0xa4,0x4e,0xbc,0x6f,0x9a,0x8f,0xb6,0xc4,0x43,0x0b,0xe4,0x61,0xb1,0x4e,0x6a,
+  0x31,0xd4,0xb7,0x6d,0x31,0x71,0x37,0xec,0x85,0x02,0x83,0x32,0x32,0xc8,0x36,0x80,
+  0x93,0xd1,0x28,0x29,0xc3,0xdd,0x3f,0xf1,0xbe,0xab,0xb5,0xf6,0x3b,0x74,0xdd,0xe6,
+  0x21,0x76,0xd8,0xa9,0xba,0xe2,0x19,0x7c,0x7d,0x76,0x42,0xa1,0xe1,0x82,0xf4,0x8d,
+  0x64,0x07,0xa8,0x1a,0x55,0xc9,0x08,0x9e,0x95,0xc4,0xcf,0x88,0xf2,0xb5,0x8c,0x8d,
+  0xb1,0xfc,0x8e,0x1b,0xbf,0x4f,0xbe,0x46,0xd7,0xeb,0x73,0x87,0xe4,0x35,0xe4,0x09,
+  0xa8,0xea,0x56,0xe3,0x74,0x0d,0x79,0x27,0xf3,0x49,0x96,0x1f,0xa2,0xdf,0x82,0x2b,
+  0x93,0xf7,0x0f,0xd0,0xa5,0xf0,0x6e,0xbb,0x1a,0xce,0xf2,0x88,0x76,0xf8,0xa3,0x5e,
+  0x39,0x96,0xe9,0x11,0x4f,0xc2,0xa7,0xd1,0x05,0x71,0x3b,0x1f,0x9c,0x85,0x98,0xe6,
+  0xae,0xa8,0x79,0x8d,0x4c,0xec,0x07,0x2d,0xad,0x55,0xfd,0x47,0xa5,0x8a,0x39,0x86,
+  0xc5,0x21,0xed,0x8a,0xb2,0xb0,0x37,0x0b,0xd7,0x07,0x3e,0x85,0xaa,0x97,0x1c,0x31,
+  0x1c,0xfc,0x7f,0x94,0xaa,0x5a,0xc7,0x48,0x8e,0x92,0x3e,0xb1,0x3e,0x54,0xfa,0x79,
+  0xb8,0x07,0x4f,0x75,0xd6,0x01,0x71,0x35,0x9c,0x80,0x32,0x96,0x19,0x13,0x87,0x70,
+  0x7e,0x59,0x9f,0x3d,0x8a,0x83,0x13,0xcc,0x1b,0xb7,0xbb,0xe4,0xa2,0xc9,0xfd,0xd3,
+  0x97,0xb7,0x5d,0x5d,0x0f,0x3b,0x80,0x7e,0x57,0x9c,0x49,0x70,0xc0,0xdc,0xf5,0xe4,
+  0x6d,0x38,0x00,0xfa,0xc9,0x40,0x30,0xfb,0x6d,0xfc,0x43,0xd5,0xa0,0x21,0x9b,0x77,
+  0xf2,0xfb,0xaa,0xb0,0x91,0xb5,0x1a,0x05,0xaa,0xad,0xdc,0xb6,0x0c,0x1e,0x63,0xea,
+  0xd9,0xeb,0xf1,0x35,0xe1,0x79,0x96,0x1f,0x2f,0x5f,0xee,0x3f,0x05,0xeb,0x71,0x80,
+  0x2f,0xae,0xc2,0xc4,0xfa,0xd7,0x49,0xad,0xb0,0x35,0xa4,0xd6,0xe3,0xee,0xca,0xc4,
+  0x8d,0xa4,0x0e,0x2f,0xe7,0xeb,0xb9,0x97,0xdf,0x36,0x37,0xdc,0xab,0xed,0x8d,0xaa,
+  0x03,0xb8,0x03,0xb3,0x27,0xf7,0xe7,0xe0,0x8c,0x41,0x38,0x65,0x94,0x36,0x67,0xe9,
+  0x05,0x7f,0x0b,0xef,0xb4,0xef,0xed,0xcc,0xd4,0xf1,0xeb,0x7f,0x0e,0x5e,0x66,0xff,
+  0x40,0xfc,0x23,0x1c,0x87,0x2e,0xe6,0xd6,0xc5,0x8a,0xc9,0xe7,0x09,0x08,0x02,0x0c,
+  0xfa,0x7d,0xd4,0x01,0x62,0x9c,0x0d,0x42,0x05,0xcd,0x62,0x62,0x1c,0x46,0x58,0x05,
+  0x38,0x98,0xf8,0x2e,0x0c,0x82,0x0f,0x1c,0x86,0xf8,0x1a,0x4c,0xdc,0x9f,0x2a,0x4f,
+  0x91,0x1e,0xf6,0x94,0x96,0x19,0x15,0x3b,0xd2,0x8f,0x41,0xf8,0x76,0x1c,0x0c,0xc0,
+  0x28,0xe9,0xd2,0xec,0x8a,0x28,0xc1,0xfb,0xe0,0xd3,0x1c,0x51,0xf1,0xe8,0xe4,0xf3,
+  0x30,0x58,0xd5,0xd3,0xdc,0xaf,0x06,0x6d,0xd1,0x9c,0x55,0xb0,0x0b,0xd4,0x3a,0x7b,
+  0x94,0x0c,0xc0,0x41,0xcd,0xa9,0x45,0xa2,0xa4,0x10,0x9a,0xa1,0x44,0x93,0xa3,0x24,
+  0x3e,0x29,0x16,0xca,0xd3,0x0a,0xd3,0x5a,0xb4,0x5f,0x04,0x68,0x34,0x7d,0x00,0x32,
+  0x94,0x6f,0x6b,0xcd,0xe6,0x7c,0x8a,0xdb,0x26,0xea,0x77,0xc3,0xcf,0x61,0x9e,0x26,
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+  0x69,0x90,0x8f,0x43,0x6b,0x2c,0x7c,0x1e,0x41,0x71,0x5c,0x6f,0x65,0xda,0x79,0xdf,
+  0x90,0x8d,0xa6,0x5e,0x93,0xf7,0x93,0x1d,0x19,0x02,0xc1,0x87,0xc5,0x23,0x2e,0x0d,
+  0x7e,0xe7,0x12,0x63,0xc0,0x31,0x29,0x3d,0x20,0xcf,0xf7,0x3b,0x58,0x18,0x65,0x87,
+  0x0a,0x2e,0x1f,0x5a,0x58,0x66,0x85,0x39,0x2a,0x0c,0xd5,0xe7,0xaa,0x1d,0xca,0xe3,
+  0x41,0x1a,0xd4,0x0b,0x2e,0xb6,0xc5,0x4b,0xd8,0x16,0x77,0x40,0xce,0x17,0xd4,0xbb,
+  0xe4,0xf9,0xa1,0xf4,0x3e,0xfa,0xa7,0x0e,0x35,0x70,0x6c,0xef,0x2a,0xad,0xbe,0xd8,
+  0x9b,0x30,0x2e,0x32,0x34,0x56,0x6f,0xb3,0x71,0x19,0x33,0x04,0x4d,0xc2,0xa8,0x5a,
+  0x3f,0xe4,0xf5,0xd0,0x51,0x5f,0x80,0x4e,0x85,0x10,0xd7,0x89,0x06,0x39,0xd2,0x53,
+  0x15,0x28,0xca,0xf1,0x23,0xac,0x89,0xbe,0xcb,0x69,0x10,0x8e,0x23,0x28,0x22,0x16,
+  0xe6,0xf5,0x31,0xf6,0x02,0x99,0x41,0x7d,0x9c,0x35,0x6b,0x61,0xab,0x9b,0x57,0xd5,
+  0x93,0x47,0x59,0x9f,0xb5,0xf8,0x54,0xe6,0x53,0x78,0x84,0xed,0x2e,0x2c,0x9c,0x48,
+  0x9f,0x32,0xd0,0x9c,0x75,0x4d,0x9f,0x33,0x22,0xad,0xde,0x8e,0xc2,0x22,0x88,0xfd,
+  0x18,0x78,0x57,0xdf,0x44,0x66,0x0a,0xda,0xb5,0x4d,0xb0,0x0d,0x98,0x1d,0x30,0xd1,
+  0xf4,0xc3,0x62,0x3b,0x00,0x1a,0xaf,0x3c,0x00,0x5b,0x55,0x3d,0x81,0x34,0xd8,0x0f,
+  0x74,0xcf,0x01,0xdb,0x36,0xea,0x54,0xd3,0xf8,0xac,0x58,0x4e,0x18,0x03,0x10,0x2b,
+  0xca,0xb7,0xaf,0x31,0xbe,0x68,0x57,0x87,0x13,0xe0,0x5c,0x29,0xd0,0x13,0x4c,0x34,
+  0x98,0x45,0x71,0x87,0x80,0x2a,0x35,0x24,0x12,0x50,0x35,0x9f,0xe5,0xb5,0x31,0x2c,
+  0x92,0x71,0xaa,0xf8,0x71,0x2c,0xfd,0xc8,0x23,0x79,0x51,0x36,0xd7,0x55,0x4c,0x79,
+  0xbe,0xae,0x81,0x8f,0x36,0xad,0xc5,0xf9,0xc4,0xe7,0x18,0x9a,0xf0,0x1d,0xa6,0x15,
+  0xe8,0x8c,0xe6,0x8a,0x13,0x1f,0x5a,0x04,0x45,0x50,0xc5,0x87,0xcc,0x31,0xab,0x08,
+  0x9c,0xda,0xac,0xca,0xf9,0x94,0x63,0x67,0x4e,0x65,0xfc,0x4e,0x3e,0x64,0x15,0x3e,
+  0xf4,0xd1,0x5d,0xee,0xd2,0x0e,0x71,0xfc,0xd1,0x14,0x90,0x06,0xe7,0x24,0x53,0xac,
+  0x1a,0xc1,0x13,0x81,0xbc,0x1e,0xc1,0x6f,0x21,0x38,0xec,0x1a,0x83,0x4e,0xbb,0x3b,
+  0x4b,0x06,0x47,0x30,0x1f,0x2a,0xeb,0xd1,0xba,0x65,0x2c,0xfc,0x07,0x53,0xc9,0x87,
+  0x1c,0xb8,0xf1,0x23,0xd5,0xf1,0x23,0x52,0xfc,0x90,0x94,0x6f,0x3c,0xc3,0xf1,0x85,
+  0x8c,0x41,0x86,0x88,0xdf,0x31,0x06,0x67,0x83,0x25,0xe3,0x8c,0x68,0xdd,0x7a,0x69,
+  0x3d,0x59,0x4e,0x58,0x58,0x9f,0x9f,0x17,0x47,0x3e,0xec,0x47,0x2c,0x64,0x55,0xa6,
+  0xcb,0x31,0x50,0xe6,0xb1,0x2c,0x11,0x37,0x65,0xbe,0xb8,0x04,0x4c,0x8d,0x3f,0xf2,
+  0x21,0x08,0x2c,0x24,0x50,0xc4,0xc6,0xcd,0xd4,0x43,0xd2,0xd5,0x10,0x9e,0x79,0x1a,
+  0x69,0x90,0xe5,0x1b,0x73,0xb0,0x18,0x41,0xf1,0xaa,0xc0,0x42,0x5f,0x19,0x14,0x87,
+  0xac,0x2b,0xbc,0x23,0x1e,0xe0,0x12,0xcf,0xf7,0xb0,0xa1,0xc3,0x3b,0x11,0xea,0x0c,
+  0xc4,0x42,0xc4,0x3c,0xc7,0x58,0xf5,0xd2,0xc8,0xce,0x75,0x76,0x25,0xbe,0xd6,0xe3,
+  0x1b,0xb2,0xc6,0xf3,0xad,0x88,0x85,0x41,0x9a,0xf6,0x62,0x3c,0x4c,0x58,0x48,0x23,
+  0x64,0xc4,0xaf,0x58,0x65,0x7e,0x2e,0xd3,0x13,0x70,0xf8,0x93,0x1f,0x9d,0x37,0x64,
+  0x3d,0x4b,0xb4,0xf9,0xbd,0xd3,0x9f,0x3a,0xa0,0x48,0xe8,0xc8,0xce,0x55,0x5e,0x2f,
+  0xa0,0x7b,0xa3,0xc8,0x87,0x69,0x36,0x8c,0xcf,0x6e,0xa3,0x53,0x7f,0x9a,0xa9,0xfe,
+  0x64,0xd9,0x88,0x53,0x9a,0xb2,0x4c,0xda,0x7f,0xcc,0xdb,0x01,0x2b,0x9e,0x0f,0x8e,
+  0x19,0x1f,0xa3,0x59,0x86,0xa0,0xa8,0x1d,0x85,0x81,0x42,0xdc,0x35,0x56,0x7c,0x40,
+  0x14,0xa2,0xb2,0x32,0x79,0xf6,0xaa,0x56,0x0b,0x29,0x0b,0x26,0xac,0xb5,0x5a,0x03,
+  0xf8,0x2d,0xfd,0x3a,0x23,0xd3,0x6b,0x19,0x65,0x23,0xe5,0xb3,0xf6,0x14,0x7d,0x45,
+  0x4e,0x9b,0x2f,0x0b,0x6f,0x58,0x09,0x6b,0xa9,0x29,0xd2,0xa6,0x99,0xb0,0x30,0xab,
+  0x8d,0x38,0xa0,0x98,0x95,0xf3,0x41,0xeb,0x66,0x89,0x93,0x22,0x3f,0x5f,0xb7,0x90,
+  0x06,0x27,0x82,0x4e,0xda,0xb8,0x7c,0x98,0x70,0xf9,0xb0,0xea,0xf8,0xe2,0x85,0xd8,
+  0xaa,0x0c,0x1e,0x8e,0x90,0x2b,0xe8,0x66,0x20,0x62,0xa4,0x58,0x0e,0x8f,0xfb,0x74,
+  0xc8,0x20,0x3e,0x14,0x06,0xa4,0xfd,0xc1,0x96,0xf2,0x62,0x0c,0xa7,0xc1,0x93,0x60,
+  0xda,0xb1,0x09,0x2d,0xa2,0xa5,0x00,0xcf,0xee,0x38,0x42,0xc6,0x16,0x86,0x57,0x8e,
+  0x17,0x2c,0x1f,0x66,0x8c,0xf8,0x10,0xbd,0x0f,0x2b,0x8e,0x56,0xbe,0x7a,0x97,0x90,
+  0x8d,0xb4,0x9e,0xa6,0x85,0xc4,0x87,0x11,0xcb,0xdf,0x84,0xc7,0x45,0x53,0x63,0x5b,
+  0x68,0xbe,0xcb,0x87,0x65,0x63,0x49,0xeb,0xd1,0x20,0x24,0x8a,0x0c,0x66,0x69,0xd1,
+  0xa9,0x36,0xe5,0xfa,0x43,0x26,0x80,0xf5,0xd9,0xb7,0x4b,0xde,0x1f,0xf0,0xed,0x85,
+  0xa5,0xd0,0xd2,0x35,0x35,0x7c,0x28,0x0f,0xef,0x40,0x0b,0xdf,0x38,0x5c,0xaa,0x3f,
+  0xc3,0x41,0x61,0x7c,0x61,0xab,0x7c,0x49,0x8c,0x67,0xf2,0xa3,0x6b,0x81,0x5e,0xaf,
+  0x63,0x13,0xc5,0xb5,0x5a,0x6d,0x38,0xe5,0xbc,0x5e,0x34,0xa2,0x5f,0x0f,0x0a,0x53,
+  0x90,0xfa,0xd3,0x1c,0x3e,0xd1,0x75,0xb9,0xda,0x41,0xff,0x5b,0xf0,0x11,0xbd,0xfb,
+  0x41,0xf7,0x33,0xb8,0x51,0x32,0x67,0x4b,0x46,0xaa,0x3f,0x8c,0x41,0x07,0x8f,0xe6,
+  0xfc,0xbb,0xad,0x2b,0xb0,0x92,0x47,0xe9,0x9f,0xd6,0x5f,0x25,0xb0,0xcc,0xf9,0x63,
+  0x64,0xb8,0x30,0x95,0xf7,0x87,0xf3,0x4c,0x8a,0x61,0x37,0x6a,0xf6,0x00,0xd5,0x07,
+  0x32,0x11,0xa3,0xda,0x60,0xe9,0x30,0xe4,0xfa,0xc3,0x21,0x89,0x55,0xda,0x2d,0xe1,
+  0x58,0xcb,0xe9,0x8a,0xb0,0x7b,0xd5,0xd0,0x31,0xa2,0x54,0x56,0xf6,0x27,0x9b,0x76,
+  0xf9,0xd0,0xda,0xbb,0x47,0x18,0x09,0x0b,0x85,0x49,0xc9,0x7c,0x88,0xf5,0x27,0xbd,
+  0xbd,0xbf,0x2e,0x98,0x49,0x41,0x6c,0x7b,0xce,0x88,0x21,0x1f,0x1a,0x3c,0x2d,0x0c,
+  0xd6,0x1f,0x20,0xd3,0x85,0x46,0xca,0x1f,0x4a,0x40,0xaa,0x7c,0x05,0xaa,0x7c,0xfa,
+  0xa1,0x40,0x42,0xcb,0x62,0x8e,0x53,0x6e,0x62,0xe3,0xe0,0x1a,0x90,0x84,0x10,0x88,
+  0x7c,0x08,0x2b,0xf4,0x12,0x16,0xd2,0x48,0xd1,0xe1,0x43,0x70,0x41,0x11,0x34,0xbd,
+  0xbc,0x9e,0xcd,0xfe,0x6d,0x5d,0xc5,0xa9,0xc6,0xd5,0xb0,0xd9,0xb7,0x88,0x5f,0x99,
+  0x6a,0x6c,0x0f,0x6d,0xf6,0x6d,0x43,0xd3,0xd1,0x1e,0x75,0x46,0x3a,0xda,0x23,0xd2,
+  0x7a,0xf0,0xf9,0xee,0xeb,0xaa,0x1f,0xee,0x6d,0x32,0x2e,0x35,0xef,0xc1,0xb3,0xff,
+  0xe1,0x84,0x71,0x29,0xe0,0x62,0xc0,0x45,0x97,0x07,0x62,0x52,0x7f,0x0a,0x02,0x0b,
+  0x89,0x0f,0x6b,0xfa,0xfa,0x64,0x3e,0xfc,0xb0,0xc4,0x87,0x7b,0xab,0xf9,0x50,0xd0,
+  0x17,0xf1,0xe1,0xfa,0x83,0x5b,0x65,0x3e,0xbc,0xfd,0x80,0xf8,0x50,0x60,0xe1,0x6f,
+  0xc3,0x73,0xb3,0x9d,0x7f,0x38,0xa0,0xb8,0xbf,0xf9,0x03,0xc2,0xc2,0xe1,0xb7,0x67,
+  0x97,0xcf,0xb9,0x46,0x9e,0x2f,0xfe,0xfa,0xef,0xd3,0x38,0xff,0x4f,0x07,0x14,0x67,
+  0xd7,0x1f,0x24,0x2c,0x9c,0xbe,0x35,0xbb,0x7e,0xce,0x35,0x55,0xf3,0x1b,0x5c,0x3e,
+  0x4c,0x36,0x6c,0xb9,0x36,0xb2,0x12,0xf9,0x30,0x79,0x60,0xcb,0x05,0x41,0x98,0x49,
+  0x81,0x9a,0xc5,0x5b,0xff,0x61,0xfd,0x26,0x24,0x34,0x7a,0x7b,0xaa,0x09,0xa9,0xc8,
+  0xfd,0x47,0x51,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0xfa,0xbf,0x4b,
+  0xf4,0x0e,0x4c,0xf5,0x0e,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,0x4a,
+  0x77,0x97,0xe8,0x1d,0x82,0xaa,0x77,0x50,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,
+  0x52,0x52,0xba,0xbb,0x44,0xef,0x10,0x12,0xbd,0x03,0xfe,0x14,0x58,0xfb,0xdc,0x2e,
+  0xde,0xb9,0xe1,0xb5,0x5d,0x1e,0xfd,0xb5,0xb6,0x0b,0xb0,0x82,0x27,0xd3,0x10,0xb3,
+  0xbd,0x89,0xcf,0xe6,0xbf,0xf4,0x8e,0x55,0x53,0xf7,0x4d,0xd6,0x9b,0xf0,0xd0,0x39,
+  0x49,0xeb,0xe7,0xd0,0x69,0x7b,0x13,0x9f,0x25,0x46,0x4f,0xda,0xcb,0xae,0x9c,0x38,
+  0xe6,0x4d,0x78,0x30,0x27,0xcd,0x9b,0x3c,0x39,0x68,0x9b,0xb6,0x37,0xf1,0xa3,0x6b,
+  0xf6,0x1f,0xb1,0xeb,0x3f,0x7b,0x7e,0xab,0x37,0xe1,0x71,0xff,0x9d,0xf5,0x7b,0xb5,
+  0xff,0x91,0xd6,0x71,0x0b,0x9e,0x58,0x32,0xe1,0xdd,0xfe,0x2f,0xc0,0xfc,0xd9,0x0a,
+  0x5e,0xed,0x7f,0x6d,0xcb,0xd7,0x33,0xf0,0xd0,0x8e,0x2f,0x37,0x7a,0x13,0x1e,0xf7,
+  0xdf,0x59,0xbf,0x67,0xf9,0xff,0x58,0xdd,0x27,0xbc,0xe6,0x95,0xd1,0x7b,0x7d,0xe6,
+  0xff,0x7e,0x65,0x4e,0x76,0x62,0xfe,0x1c,0xf4,0x2e,0xff,0x75,0x6d,0x35,0x2c,0x0f,
+  0x3f,0xec,0x5d,0xfe,0x3b,0xeb,0xf7,0x6a,0xff,0xa3,0x8d,0xe9,0x1e,0x58,0x75,0xbb,
+  0xc5,0xab,0xfc,0x31,0xe7,0x6c,0xaa,0x9f,0xe6,0x8c,0xed,0x4d,0x7c,0x16,0x1a,0x7a,
+  0xd3,0x5e,0xfd,0xc5,0xa8,0x67,0xf5,0xdf,0x5d,0xff,0xdf,0xbf,0x99,0xe0,0xc1,0x88,
+  0x25,0x47,0xcf,0xd8,0xc9,0x25,0x23,0x9e,0xd5,0x9f,0xb9,0x19,0xaa,0x9f,0x33,0x5e,
+  0xed,0xff,0x82,0x0d,0xbf,0xde,0xb2,0x3b,0x7e,0x7a,0x66,0xd2,0x9b,0xf0,0xb8,0xff,
+  0xce,0xfa,0x3d,0xdb,0xff,0x0d,0xc7,0xdf,0xb7,0x1e,0x5f,0x72,0x3a,0x7c,0xef,0xa9,
+  0xf7,0x25,0x73,0x6e,0x92,0xea,0xa7,0x67,0xf9,0x1f,0x6c,0x38,0xf3,0xb2,0xd5,0xf2,
+  0xed,0xcf,0x69,0x6f,0xc2,0xe3,0xfe,0x3b,0xeb,0xf7,0x6c,0xff,0x97,0xef,0xf8,0x0a,
+  0x12,0x75,0xef,0x79,0x57,0x7f,0xe6,0xa8,0x7e,0x7a,0x97,0xff,0xcb,0x02,0x8d,0x7c,
+  0xc3,0xe9,0xe8,0x65,0x6f,0xc2,0xd3,0x97,0x9c,0x88,0xf5,0x7b,0xb3,0xff,0xa6,0xf8,
+  0x46,0x8a,0x1b,0x3f,0x98,0x60,0xd1,0x67,0x44,0xfc,0x26,0xf0,0x7f,0x7d,0x3f,0xc1,
+  0x7d,0x6c,0xc0,0x84,0x09,0x4d,0x8a,0xb9,0xfb,0xce,0x79,0x7f,0x01,0xf4,0xb7,0xc1,
+  0xde,0xf0,0x33,0x01,0x00,
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
new file mode 100755
index 0000000..3158803
--- /dev/null
+++ b/board/esd/hh405/hh405.c
@@ -0,0 +1,877 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+#include <pci.h>
+#include <sm501.h>
+
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define SWAP32(x)	 ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
+			  (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#define BPP	16
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 1 /* test-only */
+	{0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+	{0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+	{0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+	{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+	{0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+	{0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+	{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+	{0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+
+#ifdef CONFIG_VIDEO_SM501_32BPP
+#define BPP	32
+
+/*
+ * 800x600 display B084SN03: PCLK = 40MHz
+ * => 2*PCLK = 80MHz
+ * 336/4 = 84MHz
+ * => PCLK = 84MHz
+ */
+static const SMI_REGS init_regs_800x600 [] =
+{
+#if 0 /* test-only */
+	{0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
+#else
+	{0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
+#endif
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x221a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+	{0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
+	{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x02580320)}, /* panel plane br location */
+	{0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+/*
+ * 1024x768 display G150XG02: PCLK = 65MHz
+ * => 2*PCLK = 130MHz
+ * 288/2 = 144MHz
+ * => PCLK = 72MHz
+ */
+static const SMI_REGS init_regs_1024x768 [] =
+{
+	{0x00004, SWAP32(0x00000000)},
+	/* clocks for pm1... */
+	{0x00048, SWAP32(0x00021807)},
+	{0x0004C, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000001)},
+	/* clocks for pm0... */
+	{0x00040, SWAP32(0x00021807)},
+	{0x00044, SWAP32(0x011a0a01)},
+	{0x00054, SWAP32(0x00000000)},
+	/* panel control regs... */
+	{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
+	{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
+	{0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+	{0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
+	{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
+	{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
+	{0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
+	{0x80020, SWAP32(0x03000400)}, /* panel plane br location */
+	{0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
+	{0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
+	{0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
+	{0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
+	{0x80200, SWAP32(0x00010000)}, /* crt display control */
+	{0, 0}
+};
+
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#endif /* CONFIG_VIDEO_SM501 */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp_320[] =
+{
+#include "logo_320_240_4bpp.c"
+};
+
+unsigned char logo_bmp_320_8bpp[] =
+{
+#include "logo_320_240_8bpp.c"
+};
+
+unsigned char logo_bmp_640[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+unsigned char logo_bmp_1024[] =
+{
+#include "logo_1024_768_8bpp.c"
+};
+
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/s1d13704_320_240_4bpp.h"
+#include "../common/s1d13705_320_240_8bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+#include "../common/s1d13806_1024_768_8bpp.h"
+
+
+/*
+ * include common auto-update code (for esd boards)
+ */
+#include "../common/auto_update.h"
+
+au_image_t au_image[] = {
+	{"hh405/preinst.img", 0, -1, AU_SCRIPT},
+	{"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
+	{"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
+	{"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
+	{"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
+	{"hh405/postinst.img", 0, 0, AU_SCRIPT},
+};
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+
+int board_revision(void)
+{
+	unsigned long osrh_reg;
+	unsigned long isr1h_reg;
+	unsigned long tcr_reg;
+	unsigned long value;
+
+	/*
+	 * Get version of HH405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
+	 */
+	osrh_reg = in32(GPIO0_OSRH);
+	isr1h_reg = in32(GPIO0_ISR1H);
+	tcr_reg = in32(GPIO0_TCR);
+	out32(GPIO0_OSRH, osrh_reg & ~0xC0003000);     /* output select */
+	out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000);    /* input select  */
+	out32(GPIO0_TCR, tcr_reg & ~0x80400000);       /* select input  */
+
+	udelay(1000);            /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x80400000;         /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	out32(GPIO0_OSRH, osrh_reg);                   /* output select */
+	out32(GPIO0_ISR1H, isr1h_reg);                 /* input select  */
+	out32(GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
+
+	if (value & 0x80000000) {
+		/* Revision 1.0 or 1.1 detected */
+		return 0x0101;
+	} else {
+		if (value & 0x00400000) {
+			/* unused */
+			return 0x0103;
+		} else {
+			/* Revision >= 2.0 detected */
+			/* rev. 2.x uses four SM501 GPIOs for revision coding */
+			return 0x0200;
+		}
+	}
+}
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile unsigned short *fpga_ctrl =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned short *lcd_contrast =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
+	volatile unsigned short *lcd_backlight =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	char *str;
+	unsigned long contrast0 = 0xffffffff;
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_INIT pin
+	 */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT);  /* reset low */
+	udelay(1000); /* wait 1ms */
+	out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT);   /* reset high */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Write Board revision into FPGA
+	 */
+	*fpga_ctrl |= gd->board_type & 0x0003;
+	if (gd->board_type >= 0x0200) {
+		*fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
+	}
+
+ 	/*
+	 * Setup and enable EEPROM write protection
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * Reset touch-screen controller
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
+	udelay(1000);
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST);
+
+	/*
+	 * Enable power on PS/2 interface (with reset)
+	 */
+	*fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
+	for (i=0;i<500;i++)
+		udelay(1000);
+	*fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
+
+	/*
+	 * Get contrast value from environment variable
+	 */
+	str = getenv("contrast0");
+	if (str) {
+		contrast0 = simple_strtol(str, NULL, 16);
+		if (contrast0 > 255) {
+			printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
+			contrast0 = 0;
+		}
+	}
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc230") == 0) {
+		/*
+		 * Switch backlight on
+		 */
+		*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL;
+		*lcd_backlight = 0x0000;
+
+		lcd_setup(1, 0);
+		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+			 regs_13806_1024_768_8bpp,
+			 sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
+			 logo_bmp_1024, sizeof(logo_bmp_1024));
+	} else if (strcmp(str, "ppc220") == 0) {
+		/*
+		 * Switch backlight on
+		 */
+		*fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL;
+		*lcd_backlight = 0x0000;
+
+		lcd_setup(1, 0);
+		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+			 regs_13806_640_480_16bpp,
+			 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+			 logo_bmp_640, sizeof(logo_bmp_640));
+	} else if (strcmp(str, "ppc215") == 0) {
+		/*
+		 * Set default display contrast voltage
+		 */
+		if (contrast0 == 0xffffffff) {
+			*lcd_contrast = 0x0082;
+		} else {
+			*lcd_contrast = contrast0;
+		}
+		*lcd_backlight = 0xffff;
+		/*
+		 * Switch backlight on
+		 */
+		*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
+		/*
+		 * Set lcd clock (small epson)
+		 */
+		*fpga_ctrl |= LCD_CLK_06250;
+		udelay(100);               /* wait for 100 us */
+
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+			 regs_13705_320_240_8bpp,
+			 sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
+			 logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
+	} else if (strcmp(str, "ppc210") == 0) {
+		/*
+		 * Set default display contrast voltage
+		 */
+		if (contrast0 == 0xffffffff) {
+			*lcd_contrast = 0x0060;
+		} else {
+			*lcd_contrast = contrast0;
+		}
+		*lcd_backlight = 0xffff;
+		/*
+		 * Switch backlight on
+		 */
+		*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
+		/*
+		 * Set lcd clock (small epson)
+		 */
+		*fpga_ctrl |= LCD_CLK_08330;
+
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+#ifdef CONFIG_VIDEO_SM501
+	} else {
+		pci_dev_t devbusfn;
+
+		/*
+		 * Is SM501 connected (ppc221/ppc231)?
+		 */
+		devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+		if (devbusfn != -1) {
+			puts("VGA:   SM501 with 8 MB ");
+			if (strcmp(str, "ppc221") == 0) {
+				printf("(800*600, %dbpp)\n", BPP);
+			} else if (strcmp(str, "ppc231") == 0) {
+				printf("(1024*768, %dbpp)\n", BPP);
+			} else {
+				printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+				return 0;
+			}
+		} else {
+			printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+			return 0;
+		}
+#endif /* CONFIG_VIDEO_SM501 */
+	}
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming HH405");
+	} else {
+		puts(str);
+	}
+
+	if (getenv_r("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s", str);
+	} else {
+		puts(" (Missing bd_type!");
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev %ld.%ld)\n",
+	       (gd->board_type >> 8) & 0xff,
+	       gd->board_type & 0xff);
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif
+
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access, clear bit GPIO_SINT2. */
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access, set bit GPIO_SINT2. */
+			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int query = argc == 1;
+	int state = 0;
+
+	if (query) {
+		/* Query write access state. */
+		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+		if (state < 0) {
+			puts ("Query of write access state failed.\n");
+		} else {
+			printf ("Write access for device 0x%0x is %sabled.\n",
+				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			state = 0;
+		}
+	} else {
+		if ('0' == argv[1][0]) {
+			/* Disable write access. */
+			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+		} else {
+			/* Enable write access. */
+			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+		}
+		if (state < 0) {
+			puts ("Setup of write access state failed.\n");
+		}
+	}
+
+	return state;
+}
+
+U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
+	   "eepwren - Enable / disable / query EEPROM write access\n",
+	   NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
+
+
+#ifdef CONFIG_VIDEO_SM501
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char str[64];
+	char str2[64];
+	int i = getenv_r("serial#", str2, sizeof(str));
+
+	if (line_number == 1) {
+		sprintf(str, " Board: ");
+
+		if (i == -1) {
+			strcat(str, "### No HW ID - assuming HH405");
+		} else {
+			strcat(str, str2);
+		}
+
+		if (getenv_r("bd_type", str2, sizeof(str2)) != -1) {
+			strcat(str, " (");
+			strcat(str, str2);
+		} else {
+			strcat(str, " (Missing bd_type!");
+		}
+
+		sprintf(str2, ", Rev %ld.%ld)",
+		       (gd->board_type >> 8) & 0xff, gd->board_type & 0xff);
+		strcat(str, str2);
+		strcpy(info, str);
+	} else {
+		info [0] = '\0';
+	}
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+
+/*
+ * Returns SM501 register base address. First thing called in the driver.
+ */
+unsigned int board_video_init (void)
+{
+	pci_dev_t devbusfn;
+	u32 addr;
+
+	/*
+	 * Is SM501 connected (ppc221/ppc231)?
+	 */
+	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+	if (devbusfn != -1) {
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
+		return (addr & 0xfffffffe);
+	}
+
+	return 0;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+	pci_dev_t devbusfn;
+	u32 addr;
+
+	/*
+	 * Is SM501 connected (ppc221/ppc231)?
+	 */
+	devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
+	if (devbusfn != -1) {
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
+		return (addr & 0xfffffffe);
+	}
+
+	return 0;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+	char *str;
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc221") == 0) {
+		return init_regs_800x600;
+	} else {
+		return init_regs_1024x768;
+	}
+}
+
+int board_get_width (void)
+{
+	char *str;
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc221") == 0) {
+		return 800;
+	} else {
+		return 1024;
+	}
+}
+
+int board_get_height (void)
+{
+	char *str;
+
+	str = getenv("bd_type");
+	if (strcmp(str, "ppc221") == 0) {
+		return 600;
+	} else {
+		return 768;
+	}
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
diff --git a/board/esd/hh405/logo_1024_768_8bpp.c b/board/esd/hh405/logo_1024_768_8bpp.c
new file mode 100755
index 0000000..2195547
--- /dev/null
+++ b/board/esd/hh405/logo_1024_768_8bpp.c
@@ -0,0 +1,2544 @@
+  0x1f,0x8b,0x08,0x08,0x20,0xb5,0x06,0x40,0x00,0x03,0x48,0x6f,0x6c,0x7a,0x2d,0x48,
+  0x65,0x72,0x5f,0x64,0x74,0x5f,0x33,0x43,0x5f,0x31,0x30,0x32,0x34,0x78,0x37,0x36,
+  0x38,0x5f,0x32,0x35,0x36,0x2e,0x62,0x6d,0x70,0x00,0xec,0xbd,0x0b,0x74,0x23,0xd7,
+  0x79,0xa0,0x59,0x14,0x0d,0x1d,0x71,0xb6,0xc9,0x43,0x37,0xe4,0xe4,0xa8,0xa2,0x0c,
+  0x80,0x58,0xeb,0x14,0x48,0x77,0x7a,0xe2,0xb4,0x2c,0xcb,0x56,0x4b,0xed,0xb6,0x8e,
+  0xc2,0x84,0x4e,0x6d,0x83,0x05,0x80,0x8b,0x09,0x0c,0xec,0x28,0x1c,0xc3,0x69,0x39,
+  0x41,0x4f,0xec,0xc4,0xde,0x44,0xc1,0x60,0x6d,0xb5,0xdb,0x8c,0x9b,0x09,0x99,0x75,
+  0xbc,0xd3,0xed,0xce,0x64,0xc6,0x36,0xd0,0x72,0xa4,0x90,0x9d,0x50,0x4b,0xb5,0x12,
+  0xef,0x78,0x26,0xb6,0x3c,0x93,0x2c,0x8f,0x93,0x33,0x50,0x9e,0x92,0x10,0xc2,0xe3,
+  0xcd,0x61,0x98,0xd6,0x63,0x77,0x04,0xd2,0x40,0x09,0x38,0x7b,0xef,0xad,0xd7,0x7d,
+  0x15,0x50,0x20,0xd9,0x0f,0xa9,0xff,0x0f,0x20,0x88,0x47,0xbd,0xeb,0xfe,0x8f,0xfb,
+  0xdf,0xff,0xde,0x7b,0xfc,0xa7,0xde,0xfd,0x96,0x03,0x0a,0xe6,0xdd,0x6f,0x51,0x14,
+  0x0d,0xbf,0x41,0xff,0x95,0x61,0x45,0x19,0x52,0x6e,0x53,0x1c,0xde,0xfe,0x23,0xd6,
+  0x9f,0xc3,0x5b,0x6e,0x79,0x8b,0xf2,0xe8,0xa7,0x1e,0x55,0xee,0x3c,0xfe,0x98,0xf2,
+  0xf5,0x3f,0xfe,0x9a,0xf2,0x53,0x8f,0xfd,0x89,0xf2,0xfe,0x0f,0x3c,0xa8,0xdc,0x35,
+  0xf7,0x5f,0x94,0xf2,0x97,0xd6,0x95,0xb7,0xfe,0xd0,0x43,0xca,0x0b,0xdf,0x79,0x41,
+  0x79,0xf0,0xe1,0xc7,0x94,0x7f,0xf7,0xcd,0x2d,0x25,0xfb,0xf0,0x9c,0x72,0xe1,0x4b,
+  0x17,0x94,0x3b,0x7f,0xe8,0x4e,0xe5,0xe4,0x57,0xbe,0xab,0x1c,0xf9,0xd4,0x15,0xe5,
+  0x87,0x3e,0x50,0x50,0xde,0xf6,0xae,0x82,0xf2,0x8e,0x5f,0xfc,0xae,0x72,0xd7,0xcc,
+  0x57,0x94,0x8f,0x3e,0xf6,0xb8,0xf2,0xcd,0x3f,0xfb,0x7b,0xe5,0x9f,0xcd,0x3d,0xae,
+  0xfc,0x6f,0xab,0xff,0xa0,0xdc,0xfa,0xd6,0xbb,0x94,0xff,0xfe,0xda,0x6b,0xca,0x4f,
+  0xfe,0xef,0x57,0x94,0x77,0x7f,0xec,0x4f,0x94,0xd8,0xcc,0xbc,0x72,0xd7,0x91,0x1f,
+  0x57,0xfe,0xbc,0xf6,0x9c,0xf2,0x63,0x3f,0x76,0x44,0x39,0xfb,0x9b,0x9f,0x57,0x7e,
+  0x74,0xe6,0x51,0xe5,0xc4,0xa3,0x8f,0x2b,0x3f,0xfb,0x85,0xff,0xac,0xac,0xd4,0xfe,
+  0xbb,0x72,0xe1,0xc9,0xff,0xa2,0x7c,0xf3,0x3b,0xaf,0x2b,0x2b,0xab,0x4f,0x29,0xb7,
+  0xdf,0x7e,0xbb,0x72,0xc2,0x48,0x2a,0x1f,0xfd,0x85,0x8f,0x2b,0xbf,0xfa,0xd4,0x6b,
+  0xca,0x0f,0xff,0xc2,0xf3,0xca,0xcf,0x7c,0xe5,0x35,0xe5,0x07,0x3f,0xf0,0xcb,0xca,
+  0xe3,0x7f,0xfc,0x82,0xb2,0xf4,0xc7,0x3b,0x4a,0xf8,0xed,0xef,0x51,0xee,0xfb,0xb5,
+  0x2b,0xca,0x1d,0xef,0xfb,0x59,0xe5,0xae,0x87,0xff,0x48,0x31,0xce,0x5f,0x51,0x3e,
+  0x79,0xfa,0x8b,0x4a,0xed,0x85,0x4d,0xe5,0x6d,0x93,0x3f,0xa9,0x9c,0xf9,0xc2,0x13,
+  0x4a,0xf6,0xc3,0x8f,0x29,0x5f,0xf8,0xf2,0x53,0xca,0xdb,0x67,0xce,0x2b,0xb1,0xe9,
+  0x79,0xe5,0x03,0x9f,0xfe,0x1b,0xe5,0x7f,0xfc,0xe9,0x27,0x94,0xb1,0x1f,0xd0,0xd0,
+  0xf1,0xff,0xb4,0xf2,0xc2,0xdf,0xb7,0x94,0xd0,0xc8,0xdb,0x94,0x7b,0x7e,0x3c,0xa3,
+  0xdc,0x75,0xf2,0x39,0x25,0xf9,0x2f,0x7f,0x59,0x79,0xbd,0xfb,0xba,0x72,0x71,0xed,
+  0x4f,0x94,0x5f,0xfc,0xea,0xa6,0xf2,0xc3,0xbf,0x7c,0x45,0xf9,0xd0,0xe7,0xff,0x5a,
+  0xf9,0xfc,0xa5,0x3f,0x57,0xfe,0xe6,0xf9,0x17,0x94,0x7f,0xbf,0xfe,0xba,0x72,0xe7,
+  0x7d,0x9f,0x54,0x7e,0xed,0x73,0x67,0x95,0x6f,0xfe,0xe9,0xba,0xf2,0x8f,0x57,0xae,
+  0x28,0xef,0x7c,0xe7,0x3b,0x95,0x7b,0xdf,0x77,0x9f,0xf2,0x03,0x77,0xde,0xa9,0x1c,
+  0xf9,0x95,0xbf,0x55,0xfe,0xd3,0x8b,0xaf,0x2b,0x5f,0x7d,0xe2,0x49,0xe5,0xc7,0x3e,
+  0xfd,0x9a,0x72,0xf6,0xff,0xdc,0x52,0xbe,0xf0,0xc5,0x0b,0xca,0x8f,0x4e,0xfd,0x92,
+  0x92,0xf9,0xe9,0xac,0xf2,0xf1,0x5f,0xfc,0xa4,0xf2,0xe9,0x3f,0x7a,0x4d,0x29,0x7d,
+  0xfe,0x19,0xe5,0xae,0xec,0x65,0xe5,0x77,0x9e,0xf9,0x2b,0x65,0xee,0x67,0xfe,0xa5,
+  0x72,0xef,0x47,0x9f,0x50,0xde,0xf7,0xf1,0x3f,0x54,0x9e,0xf9,0xa3,0xaf,0x29,0x3f,
+  0xf6,0xc8,0x33,0x4a,0xfa,0xc2,0x6b,0xca,0xdb,0xde,0xf9,0x3f,0x2b,0x6f,0xff,0xe0,
+  0xbf,0x51,0xa6,0x3f,0xf7,0x37,0x8a,0xfa,0xbe,0xac,0xf2,0x33,0x5f,0xfc,0x1b,0x65,
+  0x7a,0xfa,0x83,0x8a,0xf6,0xc8,0x9f,0x2a,0xef,0xf9,0xa9,0x93,0xca,0x07,0x7f,0xeb,
+  0x35,0xe5,0x81,0x5f,0xf9,0x13,0xe5,0x83,0xa9,0x39,0xe5,0xa9,0xbf,0x7d,0x5d,0x39,
+  0x92,0xfe,0xbc,0x32,0xf6,0x83,0xf7,0x28,0x87,0x4b,0xaf,0x29,0xbf,0xf0,0x95,0xe7,
+  0x95,0xcd,0xff,0xef,0x75,0xe5,0x03,0x9f,0x7b,0x4d,0x99,0xfb,0xa5,0xc7,0x94,0xfa,
+  0x95,0xd7,0x95,0x03,0xff,0xc3,0x01,0xe5,0x7f,0x2a,0x9e,0x53,0x9e,0xfb,0xcb,0x17,
+  0x94,0x1f,0xfd,0x99,0x0b,0x8a,0xfe,0xa1,0x47,0x95,0xe2,0xaf,0xfe,0x1b,0xe5,0xc7,
+  0x3f,0x74,0x46,0xf9,0xbf,0xff,0xf4,0x39,0xe5,0x17,0x3e,0xf7,0xbb,0xca,0xd1,0xfb,
+  0x1f,0x54,0x0e,0xff,0xc8,0x11,0xe5,0xa3,0x3f,0xff,0x71,0xe5,0x6b,0x7f,0xd1,0x56,
+  0x2e,0xfc,0xc1,0x5f,0x2b,0x9f,0xfa,0xdc,0x17,0x94,0x27,0x97,0x9f,0x52,0x96,0x7e,
+  0xfb,0x19,0xe5,0x27,0x1f,0xfd,0x43,0xe5,0x8b,0x17,0xbe,0xa2,0x7c,0xed,0xff,0xfa,
+  0xa6,0xf2,0x2f,0x7e,0x7e,0x5e,0x29,0x7c,0xee,0x29,0xc5,0xf8,0xb5,0x75,0xe5,0xf7,
+  0xd6,0xff,0x51,0x39,0x92,0x9d,0x57,0x1e,0xf8,0xe9,0xff,0x55,0xf9,0xf9,0x27,0x5f,
+  0x53,0xb2,0xb9,0x39,0x25,0xfc,0x8e,0xa4,0x52,0xfa,0xed,0x6f,0x29,0x1f,0xd4,0x93,
+  0xca,0x67,0x2e,0xbd,0xa0,0x5c,0xfe,0x0f,0x7f,0xad,0x9c,0xbe,0xf8,0x57,0xca,0x07,
+  0x3f,0xfc,0x79,0xe5,0x67,0x9f,0xb8,0xa2,0xdc,0xf9,0x23,0xf7,0x29,0xf1,0xec,0x17,
+  0x95,0xa5,0xaf,0x6d,0x29,0x9f,0xfc,0x95,0x47,0x95,0x47,0x1e,0xf9,0xa8,0xf2,0xb5,
+  0x3f,0x5e,0x57,0x9e,0xff,0x6f,0xe8,0x9e,0xbe,0xfd,0x9d,0x4a,0xf2,0x17,0x1e,0x55,
+  0xa2,0x0f,0x7d,0x5e,0xb9,0xf3,0xdd,0x1f,0x57,0x6e,0xfb,0xbe,0x23,0xca,0xa3,0xa5,
+  0xc7,0x94,0xc7,0x3e,0x73,0x56,0x79,0xf0,0xa1,0x0f,0x2a,0x27,0x7e,0xe6,0x33,0xca,
+  0x07,0x1f,0xfe,0xa8,0xf2,0xe5,0xca,0x93,0xca,0x3d,0xef,0xbe,0x4f,0xf9,0xfd,0xbf,
+  0x78,0x5d,0x79,0x6a,0xed,0x6b,0xca,0xdb,0xbe,0xef,0x4e,0x25,0x95,0xce,0x2a,0xff,
+  0xf4,0x9f,0xde,0xa5,0x2c,0xfe,0xee,0xba,0xf2,0xdc,0xd6,0xeb,0xca,0xd7,0xfe,0xf4,
+  0x05,0xe5,0x7f,0x39,0xf5,0x79,0xe5,0xa3,0x9f,0x79,0x0a,0x1d,0xd3,0x07,0x95,0x3f,
+  0xfe,0xcb,0x4d,0xe5,0xb1,0x3f,0xbc,0xa2,0xdc,0xf5,0xde,0x0f,0x2a,0x8f,0xff,0xc1,
+  0x37,0x95,0xd8,0x4f,0x3e,0xaa,0xbc,0x75,0xec,0x76,0xe5,0x41,0x3d,0xab,0xfc,0xca,
+  0xf2,0xa6,0xf2,0xa3,0xfa,0x27,0x94,0xc7,0xd1,0xb1,0xde,0x9b,0x3b,0xaf,0x3c,0xfa,
+  0xbb,0x2f,0x28,0xeb,0xdf,0x7e,0x4e,0x59,0xfe,0xd6,0x77,0x95,0xfb,0x3e,0x73,0x45,
+  0xf9,0xd1,0x07,0x0b,0xca,0xb1,0x0f,0x3f,0xae,0xa4,0x7e,0xeb,0x1f,0x94,0x43,0xc6,
+  0x19,0xe5,0xf3,0xbf,0x75,0x4e,0x39,0x66,0xfc,0xa2,0x92,0x7b,0xb4,0xaa,0x7c,0xfb,
+  0xff,0x79,0x5d,0xf9,0xc3,0x6f,0xfc,0xa5,0x72,0xe1,0x5b,0x6d,0xe5,0xc1,0xb3,0x57,
+  0x94,0x1f,0x3e,0xfa,0xb3,0xca,0xa1,0xb9,0xcb,0x4a,0xee,0xb7,0xb7,0x94,0xb3,0x9f,
+  0xf9,0xbc,0xf2,0x42,0xfd,0xbb,0xca,0x7b,0x72,0x5f,0x51,0x8e,0x94,0xfe,0x51,0x59,
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diff --git a/board/esd/hh405/logo_320_240_4bpp.c b/board/esd/hh405/logo_320_240_4bpp.c
new file mode 100755
index 0000000..ddf0d0b
--- /dev/null
+++ b/board/esd/hh405/logo_320_240_4bpp.c
@@ -0,0 +1,227 @@
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diff --git a/board/esd/hh405/logo_320_240_8bpp.c b/board/esd/hh405/logo_320_240_8bpp.c
new file mode 100755
index 0000000..c2c59c6
--- /dev/null
+++ b/board/esd/hh405/logo_320_240_8bpp.c
@@ -0,0 +1,521 @@
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diff --git a/board/esd/hh405/logo_640_480_24bpp.c b/board/esd/hh405/logo_640_480_24bpp.c
new file mode 100755
index 0000000..c042b6b
--- /dev/null
+++ b/board/esd/hh405/logo_640_480_24bpp.c
@@ -0,0 +1,4209 @@
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+  0x73,0xcf,0x2f,0xae,0x9b,0xaa,0x4c,0xd2,0x45,0xf7,0xf6,0x79,0x75,0x9f,0x3a,0x42,
+  0x5a,0x3b,0x49,0xc3,0x70,0xae,0xa1,0xee,0x7e,0x57,0xbb,0x53,0xe7,0x93,0xfe,0xc5,
+  0xf3,0x9e,0xac,0xbb,0xdb,0x6d,0x5a,0x77,0x3e,0xf6,0x3f,0x96,0x1b,0xda,0xc8,0x77,
+  0x63,0xd8,0x27,0x2e,0x0e,0xae,0xca,0x6f,0xee,0xc6,0xee,0x6d,0x7c,0x5e,0x1b,0xf1,
+  0x78,0xa1,0x93,0x75,0x0f,0x0a,0xbd,0xb0,0xc9,0xa7,0xee,0xe4,0xa3,0x9d,0x4f,0x7d,
+  0xe7,0x3f,0xbb,0xfc,0x63,0x9a,0x82,0xd0,0x5f,0xa1,0xfd,0xdf,0xc2,0xfe,0x45,0x0a,
+  0xe5,0x5e,0xcf,0x47,0x26,0x1f,0xab,0x7b,0x70,0xde,0xe9,0x27,0x9d,0x85,0xd0,0xf7,
+  0x50,0x85,0xf8,0xaa,0x5a,0x5c,0xc6,0xd7,0xef,0xc2,0x65,0x1d,0xdf,0x5e,0x97,0xef,
+  0xbf,0xce,0xae,0x6e,0x8b,0xe5,0x8f,0x62,0xb5,0x2e,0x9a,0x76,0x5e,0xb7,0x65,0xbd,
+  0x99,0x37,0x6d,0xfc,0xd0,0x05,0x5d,0x5c,0xb7,0x29,0xcd,0xf1,0x2c,0x8d,0xcd,0x26,
+  0xc7,0x65,0x8e,0xff,0xcd,0x34,0x9f,0xa8,0x48,0x67,0x4c,0xc1,0xa3,0xf4,0x60,0xf2,
+  0xc5,0x6a,0x7d,0xd1,0x7f,0x96,0x21,0xad,0xdb,0x62,0xd5,0x8d,0xf9,0xe1,0xf9,0x18,
+  0x9c,0xad,0xfa,0xa0,0xe9,0x82,0x59,0xdd,0x86,0x26,0x8d,0xc3,0xce,0x39,0x0d,0xcb,
+  0xf5,0x59,0x5a,0xdb,0xb4,0xe7,0xcb,0x4d,0x1a,0xfb,0x1d,0xd2,0x3e,0x9b,0xf4,0xa9,
+  0xdf,0x7c,0x6a,0xaf,0x3e,0xdf,0x7d,0xfc,0x76,0x7f,0x7d,0xb3,0xfd,0xf2,0x7d,0x7b,
+  0xfb,0xf3,0x7e,0x7d,0xb7,0x4d,0xb6,0xfe,0x73,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0xfe,0x6b,0xbf,0x00,0xff,0xcf,0xfd,0x4c,0x36,0x10,0x0e,
+  0x00,
diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds
new file mode 100755
index 0000000..f7a20d1
--- /dev/null
+++ b/board/esd/hh405/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile
new file mode 100755
index 0000000..a60495a
--- /dev/null
+++ b/board/esd/hub405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/hub405/config.mk b/board/esd/hub405/config.mk
new file mode 100755
index 0000000..a6d31aa
--- /dev/null
+++ b/board/esd/hub405/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd HUB405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/hub405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
new file mode 100755
index 0000000..e77dba8
--- /dev/null
+++ b/board/esd/hub405/hub405.c
@@ -0,0 +1,278 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+int board_revision(void)
+{
+	unsigned long osrl_reg;
+	unsigned long isr1l_reg;
+	unsigned long tcr_reg;
+	unsigned long value;
+
+	/*
+	 * Get version of HUB405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pin(s) (IRQ6/GPIO23)
+	 */
+	osrl_reg = in32(GPIO0_OSRH);
+	isr1l_reg = in32(GPIO0_ISR1H);
+	tcr_reg = in32(GPIO0_TCR);
+	out32(GPIO0_OSRH, osrl_reg & ~0x00030000);     /* output select */
+	out32(GPIO0_ISR1H, isr1l_reg | 0x00030000);    /* input select  */
+	out32(GPIO0_TCR, tcr_reg & ~0x00000100);       /* select input  */
+
+	udelay(1000);            /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00000100;         /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	out32(GPIO0_OSRH, osrl_reg);                   /* output select */
+	out32(GPIO0_ISR1H, isr1l_reg);                 /* input select  */
+	out32(GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
+
+	if (value & 0x00000100) {
+		/* Revision 1.1 or 1.2 detected */
+		return 1;
+	}
+
+	/* Revision 1.0 */
+	return 0;
+}
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
+	volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
+	volatile unsigned char *led_reg    = (unsigned char *)((ulong)DUART0_BA + 0x20);
+	unsigned long val;
+	int delay, flashcnt;
+	char *str;
+	char hw_rev[4];
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+	*duart2_mcr = 0x08;
+	*duart3_mcr = 0x08;
+
+	/*
+	 * Set RS232/RS422 control (RS232 = high on GPIO)
+	 */
+	val = in32(GPIO0_OR);
+	val &= ~(CFG_UART2_RS232 | CFG_UART3_RS232 | CFG_UART4_RS232 | CFG_UART5_RS232);
+
+	str = getenv("phys0");
+	if (!str || (str && (str[0] == '0')))
+		val |= CFG_UART2_RS232;
+
+	str = getenv("phys1");
+	if (!str || (str && (str[0] == '0')))
+		val |= CFG_UART3_RS232;
+
+	str = getenv("phys2");
+	if (!str || (str && (str[0] == '0')))
+		val |= CFG_UART4_RS232;
+
+	str = getenv("phys3");
+	if (!str || (str && (str[0] == '0')))
+		val |= CFG_UART5_RS232;
+
+	out32(GPIO0_OR, val);
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * check board type and setup AP power
+	 */
+	str = getenv("bd_type"); /* this is only set on non prototype hardware */
+	if (str != NULL) {
+		if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
+			unsigned char led_reg_default = 0;
+			str = getenv("ap_pwr");
+			if (!str || (str && (str[0] == '1')))
+				led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
+
+			/*
+			 * Flash LEDs
+			 */
+			for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+				*led_reg = led_reg_default;        /* LED_A..D off */
+				for (delay = 0; delay < 100; delay++)
+					udelay(1000);
+				*led_reg = led_reg_default | 0xf0; /* LED_A..D on */
+				for (delay = 0; delay < 50; delay++)
+					udelay(1000);
+			}
+			*led_reg = led_reg_default;
+		}
+	}
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Store hardware revision in environment for further processing
+	 */
+	sprintf(hw_rev, "1.%ld", gd->board_type);
+	setenv("hw_rev", hw_rev);
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming HUB405");
+	} else {
+		puts(str);
+	}
+
+	if (getenv_r("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s", str);
+	} else {
+		puts(" (Missing bd_type!");
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld)\n", gd->board_type);
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif
diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds
new file mode 100755
index 0000000..98338e9
--- /dev/null
+++ b/board/esd/hub405/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile
new file mode 100755
index 0000000..b3039c6
--- /dev/null
+++ b/board/esd/ocrtc/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c
new file mode 100755
index 0000000..ffbb4ad
--- /dev/null
+++ b/board/esd/ocrtc/cmd_ocrtc.c
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <pci_ids.h>
+#include <405gp_pci.h>
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+/*
+ * Set device number on pci board
+ */
+int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int idx = 1;	  /* start at 1 (skip device 0) */
+	pci_dev_t bdf = 0;
+	u32 addr;
+
+	while (bdf >= 0) {
+		if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) {
+			break;
+		}
+		printf("Found device nr %d at %x!\n", idx-1, bdf);
+		pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
+		addr &= ~0xf;
+		*(u32 *)addr = (bdf & 0x0000f800) >> 11;
+		printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	setdevice,	1,	1,	do_setdevice,
+	"setdevice - Set device number on pci adapter boards\n",
+	NULL
+);
+
+
+/*
+ * Get device number on pci board
+ */
+int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 device;
+	char str[32];
+
+	device = *(u32 *)0x0;
+	device = 0x16 - device;      /* calculate vxworks bp slot id */
+	sprintf(str, "%d", device);
+	setenv("slot", str);
+	printf("Variabel slot set to %x\n", device);
+
+	return 0;
+}
+U_BOOT_CMD(
+	getdevice,	1,	1,	do_getdevice,
+	"getdevice - Get device number and set slot env variable\n",
+	NULL
+);
+
+#endif
diff --git a/board/esd/ocrtc/config.mk b/board/esd/ocrtc/config.mk
new file mode 100755
index 0000000..f123319
--- /dev/null
+++ b/board/esd/ocrtc/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0xFFFD0000
diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c
new file mode 100755
index 0000000..c3d8bec
--- /dev/null
+++ b/board/esd/ocrtc/flash.c
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+
+	if (size_b1) {
+		mtdcr (ebccfga, pb0cr);
+		pbcr = mfdcr (ebccfgd);
+		mtdcr (ebccfga, pb0cr);
+		base_b1 = -size_b1;
+		switch (size_b1) {
+		case 1 << 20:
+			size_val = 0;
+			break;
+		case 2 << 20:
+			size_val = 1;
+			break;
+		case 4 << 20:
+			size_val = 2;
+			break;
+		case 8 << 20:
+			size_val = 3;
+			break;
+		case 16 << 20:
+			size_val = 4;
+			break;
+		}
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
+		mtdcr (ebccfgd, pbcr);
+		/*          printf("pb1cr = %x\n", pbcr); */
+	}
+
+	if (size_b0) {
+		mtdcr (ebccfga, pb1cr);
+		pbcr = mfdcr (ebccfgd);
+		mtdcr (ebccfga, pb1cr);
+		base_b0 = base_b1 - size_b0;
+		switch (size_b1) {
+		case 1 << 20:
+			size_val = 0;
+			break;
+		case 2 << 20:
+			size_val = 1;
+			break;
+		case 4 << 20:
+			size_val = 2;
+			break;
+		case 8 << 20:
+			size_val = 3;
+			break;
+		case 16 << 20:
+			size_val = 4;
+			break;
+		}
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+		mtdcr (ebccfgd, pbcr);
+		/*            printf("pb0cr = %x\n", pbcr); */
+	}
+
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+				base_b1 + size_b1 - monitor_flash_len,
+				base_b1 + size_b1 - 1, &flash_info[1]);
+		/* monitor protection OFF by default (one is enough) */
+		flash_protect (FLAG_PROTECT_CLEAR,
+				base_b0 + size_b0 - monitor_flash_len,
+				base_b0 + size_b0 - 1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c
new file mode 100755
index 0000000..261b8a5
--- /dev/null
+++ b/board/esd/ocrtc/ocrtc.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "ocrtc.h"
+#include <asm/processor.h>
+#include <i2c.h>
+#include <command.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF81);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	/*
+	 * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
+	 * transfers, set device-paced timeout to 256 cycles
+	 */
+	mtebc (epcr, 0x20400000);
+
+	return 0;
+}
+
+
+int misc_init_f (void)
+{
+	return 0;					/* dummy implementation */
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+#ifdef CONFIG_OCRTC
+		puts ("### No HW ID - assuming OCRTC");
+#endif
+#ifdef CONFIG_ORSG
+		puts ("### No HW ID - assuming ORSG");
+#endif
+	} else {
+		puts (str);
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr (memcfga, mem_mb0cf);
+	val = mfdcr (memcfgd);
+
+#if 0
+	printf ("\nmb0cf=%x\n", val);	/* test-only */
+	printf ("strap=%x\n", mfdcr (strap));	/* test-only */
+#endif
+
+	return (4 * 1024 * 1024 << ((val & 0x000e0000) >> 17));
+}
+
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
diff --git a/board/esd/ocrtc/ocrtc.h b/board/esd/ocrtc/ocrtc.h
new file mode 100755
index 0000000..b50d521
--- /dev/null
+++ b/board/esd/ocrtc/ocrtc.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * FLASH Memory Map as used by TQ Monitor:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0x4000_0000     Start of Flash -----------------
+ * | MON8xx code           | 0x4000_0100     Reset Vector
+ * +-----------------------+ 0x400?_????
+ * | (unused)              |
+ * +-----------------------+ 0x4001_FF00
+ * | Ethernet Addresses    |                 0x78
+ * +-----------------------+ 0x4001_FF78
+ * | (Reserved for MON8xx) |                 0x44
+ * +-----------------------+ 0x4001_FFBC
+ * | Lock Address          |                 0x04
+ * +-----------------------+ 0x4001_FFC0                     ^
+ * | Hardware Information  |                 0x40            | MON8xx
+ * +=======================+ 0x4002_0000 (sector border)    -----------------
+ * | Autostart Header      |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds
new file mode 100755
index 0000000..476b4a0
--- /dev/null
+++ b/board/esd/ocrtc/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile
new file mode 100755
index 0000000..6db564f
--- /dev/null
+++ b/board/esd/pci405/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o cmd_pci405.o
+SOBJS	= writeibm.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+#	$(AR) crv $@ $(OBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c
new file mode 100755
index 0000000..0315c3d
--- /dev/null
+++ b/board/esd/pci405/cmd_pci405.c
@@ -0,0 +1,985 @@
+/*
+ * (C) Copyright 2002-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <405gp_pci.h>
+#include <asm/processor.h>
+
+#include "pci405.h"
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
+extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
+unsigned long get_dcr(unsigned short);
+
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int *ptr = 0;
+	int count = 0;
+	int count2 = 0;
+	int status;
+	int i;
+	char addr[16];
+	char str[] = "\\|/-";
+	char *local_args[2];
+
+	/*
+	 * Mark sync address
+	 */
+	ptr = 0;
+	*ptr = 0xffffffff;
+	puts("\nWaiting for image from pci host -");
+
+	/*
+	 * Wait for host to write the start address
+	 */
+	while (*ptr == 0xffffffff) {
+		count++;
+		if (!(count % 100)) {
+			count2++;
+			putc(0x08); /* backspace */
+			putc(str[count2 % 4]);
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(1000);
+	}
+
+	if (*ptr == PCI_RECONFIG_MAGIC) {
+		/*
+		 * Save own pci configuration in PRAM
+		 */
+		memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
+		ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+		for (i=0; i<0x40; i+=4) {
+			pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
+		}
+		ptr = (unsigned int *)PCI_REGS_ADDR;
+		*ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+
+		printf("\nStoring PCI Configuration Regs...\n");
+	} else {
+		sprintf(addr, "%08x", *ptr);
+
+#if 0
+		/*
+		 * Boot image
+		 */
+		if (*ptr & 0x00000001) {
+			/*
+			 * Boot VxWorks image via bootvx
+			 */
+			addr[strlen(addr)-1] = '0';
+			printf("\nBooting VxWorks-Image at addr 0x%s ...\n", addr);
+			setenv("loadaddr", addr);
+
+			local_args[0] = argv[0];
+			local_args[1] = NULL;
+			status = do_bootvx (cmdtp, 0, 1, local_args);
+		} else {
+			/*
+			 * Boot image via bootm (normally Linux)
+			 */
+			printf("\nBooting Image at addr 0x%s ...\n", addr);
+			setenv("loadaddr", addr);
+
+			local_args[0] = argv[0];
+			local_args[1] = NULL;
+			status = do_bootm (cmdtp, 0, 1, local_args);
+		}
+#else
+		/*
+		 * Boot image via bootm
+		 */
+		printf("\nBooting Image at addr 0x%s ...\n", addr);
+		setenv("loadaddr", addr);
+
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		status = do_bootm (cmdtp, 0, 1, local_args);
+#endif
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	loadpci,	1,	1,	do_loadpci,
+	"loadpci - Wait for pci-image and boot it\n",
+	NULL
+);
+
+#endif
+
+#if 1 /* test-only */
+int do_getpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int val;
+	int i;
+
+	printf("\nPCI Configuration Regs for PPC405GP:");
+	for (i=0; i<0x64; i+=4) {
+		pci_read_config_dword(PCIDEVID_405GP, i, &val);
+		if (!(i % 0x10)) {
+			printf("\n%02x: ", i);
+		}
+		printf("%08x ", val);
+	}
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	getpci,	1,	1,	do_getpci,
+	"getpci  - Print own pci configuration registers\n",
+	NULL
+);
+
+int do_setpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int val;
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	val = simple_strtol (argv[2], NULL, 16);
+
+	printf("\nWriting %08x to PCI reg %08x.\n", val, addr);
+	pci_write_config_dword(PCIDEVID_405GP, addr, val);
+
+	return 0;
+}
+U_BOOT_CMD(
+	setpci,	3,	1,	do_setpci,
+	"setpci  - Set one pci configuration lword\n",
+	"<addr> <val>\n"
+	"        - Write pci configuration lword <val> to <addr>.\n"
+);
+
+int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i;
+
+	printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
+	for (i=0; i<=0x1e0; i++) {
+		if (!(i % 0x8)) {
+			printf("\n%04x ", i);
+		}
+		printf("%08lx ", get_dcr(i));
+	}
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	dumpdcr,	1,	1,	do_dumpdcr,
+	"dumpdcr - Dump all DCR registers\n",
+	NULL
+);
+
+
+int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
+	printf("\n%04x %08x ", 947, mfspr(947));
+	printf("\n%04x %08x ", 9, mfspr(9));
+	printf("\n%04x %08x ", 1014, mfspr(1014));
+	printf("\n%04x %08x ", 1015, mfspr(1015));
+	printf("\n%04x %08x ", 1010, mfspr(1010));
+	printf("\n%04x %08x ", 957, mfspr(957));
+	printf("\n%04x %08x ", 1008, mfspr(1008));
+	printf("\n%04x %08x ", 1018, mfspr(1018));
+	printf("\n%04x %08x ", 954, mfspr(954));
+	printf("\n%04x %08x ", 950, mfspr(950));
+	printf("\n%04x %08x ", 951, mfspr(951));
+	printf("\n%04x %08x ", 981, mfspr(981));
+	printf("\n%04x %08x ", 980, mfspr(980));
+	printf("\n%04x %08x ", 982, mfspr(982));
+	printf("\n%04x %08x ", 1012, mfspr(1012));
+	printf("\n%04x %08x ", 1013, mfspr(1013));
+	printf("\n%04x %08x ", 948, mfspr(948));
+	printf("\n%04x %08x ", 949, mfspr(949));
+	printf("\n%04x %08x ", 1019, mfspr(1019));
+	printf("\n%04x %08x ", 979, mfspr(979));
+	printf("\n%04x %08x ", 8, mfspr(8));
+	printf("\n%04x %08x ", 945, mfspr(945));
+	printf("\n%04x %08x ", 987, mfspr(987));
+	printf("\n%04x %08x ", 287, mfspr(287));
+	printf("\n%04x %08x ", 953, mfspr(953));
+	printf("\n%04x %08x ", 955, mfspr(955));
+	printf("\n%04x %08x ", 272, mfspr(272));
+	printf("\n%04x %08x ", 273, mfspr(273));
+	printf("\n%04x %08x ", 274, mfspr(274));
+	printf("\n%04x %08x ", 275, mfspr(275));
+	printf("\n%04x %08x ", 260, mfspr(260));
+	printf("\n%04x %08x ", 276, mfspr(276));
+	printf("\n%04x %08x ", 261, mfspr(261));
+	printf("\n%04x %08x ", 277, mfspr(277));
+	printf("\n%04x %08x ", 262, mfspr(262));
+	printf("\n%04x %08x ", 278, mfspr(278));
+	printf("\n%04x %08x ", 263, mfspr(263));
+	printf("\n%04x %08x ", 279, mfspr(279));
+	printf("\n%04x %08x ", 26, mfspr(26));
+	printf("\n%04x %08x ", 27, mfspr(27));
+	printf("\n%04x %08x ", 990, mfspr(990));
+	printf("\n%04x %08x ", 991, mfspr(991));
+	printf("\n%04x %08x ", 956, mfspr(956));
+	printf("\n%04x %08x ", 284, mfspr(284));
+	printf("\n%04x %08x ", 285, mfspr(285));
+	printf("\n%04x %08x ", 986, mfspr(986));
+	printf("\n%04x %08x ", 984, mfspr(984));
+	printf("\n%04x %08x ", 256, mfspr(256));
+	printf("\n%04x %08x ", 1, mfspr(1));
+	printf("\n%04x %08x ", 944, mfspr(944));
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	dumpspr,	1,	1,	do_dumpspr,
+	"dumpspr - Dump all SPR registers\n",
+	NULL
+);
+
+
+#define PCI0_BRDGOPT1 0x4a
+#define plb0_acr      0x87
+
+int do_getplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned short val;
+
+	printf("PLB0_ACR=%08lx\n", get_dcr(0x87));
+	pci_read_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, &val);
+	printf("PCI0_BRDGOPT1=%04x\n", val);
+	printf("CCR0=%08x\n", mfspr(ccr0));
+
+	return 0;
+}
+U_BOOT_CMD(
+	getplb,	1,	1,	do_getplb,
+	"getplb  - Dump all plb arbiter registers\n",
+	NULL
+);
+
+int do_setplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int my_acr;
+	unsigned int my_brdgopt1;
+	unsigned int my_ccr0;
+
+	my_acr = simple_strtol (argv[1], NULL, 16);
+	my_brdgopt1 = simple_strtol (argv[2], NULL, 16);
+	my_ccr0 = simple_strtol (argv[3], NULL, 16);
+
+	mtdcr(plb0_acr, my_acr);
+	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, my_brdgopt1);
+	mtspr(ccr0, my_ccr0);
+
+	return 0;
+}
+U_BOOT_CMD(
+	setplb,	4,	1,	do_setplb,
+	"setplb  - Set all plb arbiter registers\n",
+	"PLB0_ACR PCI0_BRDGOPT1 CCR0\n"
+	"        - Set all plb arbiter registers\n"
+);
+
+
+/***********************************************************************
+ *
+ * The following code is only for test purposes!!!!
+ * Please ignore this ugly stuff!!!!!!!!!!!!!!!!!!!
+ *
+ ***********************************************************************/
+
+#define PCI_ADDR 0xc0000000
+
+int do_writepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	unsigned int countmax;
+	int i;
+	int max;
+	volatile unsigned long *ptr;
+	volatile unsigned long val;
+	int loopcount = 0;
+	int test_pci_read = 0;
+	int test_pci_cfg_write = 0;
+	int test_sync = 0;
+	int test_pci_pre_read = 0;
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	size = simple_strtol (argv[2], NULL, 16);
+	countmax = simple_strtol (argv[3], NULL, 16);
+	if (countmax == 0)
+		countmax = 1000;
+
+	do_getplb(NULL, 0, 0, NULL);
+
+#if 0
+	out32r(PMM0LA, 0);
+	out32r(PMM0PCILA, 0);
+	out32r(PMM0PCIHA, 0);
+	out32r(PMM0MA, 0);
+	out32r(PMM1LA, PCI_ADDR);
+	out32r(PMM1PCILA, addr & 0xff000000);
+	out32r(PMM1PCIHA, 0x00000000);
+	out32r(PMM1MA, 0xff000001);
+#endif
+
+	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
+	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
+	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
+	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
+
+	addr = PCI_ADDR | (addr & 0x00ffffff);
+	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
+
+	max = size >> 2;
+
+	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
+
+	val = *(ulong *)0x00000000;
+	if (val & 0x00000008) {
+		test_pci_pre_read = 1;
+		printf("Running test with pre pci-memory-read access!\n");
+	}
+	if (val & 0x00000004) {
+		test_sync = 1;
+		printf("Running test with sync instruction!\n");
+	}
+	if (val & 0x00000001) {
+		test_pci_read = 1;
+		printf("Running test with pci-memory-read access!\n");
+	}
+	if (val & 0x00000002) {
+		test_pci_cfg_write = 1;
+		printf("Running test with pci-config-write access!\n");
+	}
+
+	while (1) {
+
+		if (test_pci_pre_read) {
+			/*
+			 * Read one value back
+			 */
+			ptr = (volatile unsigned long *)addr;
+			val = *ptr;
+		}
+
+		/*
+		 * Write some values to host via pci busmastering
+		 */
+		ptr = (volatile unsigned long *)addr;
+		for (i=0; i<max; i++) {
+			*ptr++ = i;
+		}
+
+		if (test_sync) {
+			/*
+			 * Sync previous writes
+			 */
+			ppcSync();
+		}
+
+		if (test_pci_read) {
+			/*
+			 * Read one value back
+			 */
+			ptr = (volatile unsigned long *)addr;
+			val = *ptr;
+		}
+
+		if (test_pci_cfg_write) {
+			/*
+			 * Generate IRQ to host via config regs
+			 */
+			pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00);
+		}
+
+		if (loopcount++ > countmax) {
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+
+			putc('.');
+
+			loopcount = 0;
+		}
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	writepci,	4,	1,	do_writepci,
+	"writepci - Write some data to pcibus\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+#define PCI_CFGADDR        0xeec00000
+#define PCI_CFGDATA        0xeec00004
+
+int ibmPciConfigWrite
+(
+	int offset,     /* offset into the configuration space */
+	int width,      /* data width                          */
+	unsigned int data       /* data to be written                  */
+	)
+{
+	/*
+	 * Write config register address to the PCI config address register
+	 * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation)
+	 */
+	out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC));
+
+#if 0 /* test-only */
+	ppcSync();
+#endif
+
+	/*
+	 * Write value to be written to the PCI config data register
+	 */
+	switch ( width ) {
+	case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF));
+		break;
+	case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF));
+		break;
+	case 4:	out32r(PCI_CFGDATA | (offset & 0x3), data);
+		break;
+	}
+
+	return (0);
+}
+
+int do_writepci2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	unsigned int countmax;
+	int max;
+	volatile unsigned long *ptr;
+	volatile unsigned long val;
+	int loopcount = 0;
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	size = simple_strtol (argv[2], NULL, 16);
+	countmax = simple_strtol (argv[3], NULL, 16);
+	if (countmax == 0)
+		countmax = 1000;
+
+	do_getplb(NULL, 0, 0, NULL);
+
+#if 0
+	out32r(PMM0LA, 0);
+	out32r(PMM0PCILA, 0);
+	out32r(PMM0PCIHA, 0);
+	out32r(PMM0MA, 0);
+	out32r(PMM1LA, PCI_ADDR);
+	out32r(PMM1PCILA, addr & 0xff000000);
+	out32r(PMM1PCIHA, 0x00000000);
+	out32r(PMM1MA, 0xff000001);
+#endif
+
+	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
+	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
+	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
+	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
+
+	addr = PCI_ADDR | (addr & 0x00ffffff);
+	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
+
+	max = size >> 2;
+
+	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
+
+	while (1) {
+
+		/*
+		 * Write one values to host via pci busmastering
+		 */
+		ptr = (volatile unsigned long *)addr;
+		*ptr = 0x01234567;
+
+		/*
+		 * Read one value back
+		 */
+		ptr = (volatile unsigned long *)addr;
+		val = *ptr;
+
+		/*
+		 * One pci config write
+		 */
+/*		pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
+/*		ibmPciConfigWrite(0x44, 1, 0x00); */
+		ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */
+
+		if (loopcount++ > countmax) {
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+
+			putc('.');
+
+			loopcount = 0;
+		}
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	writepci2,	4,	1,	do_writepci2,
+	"writepci2- Write some data to pcibus\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+int do_writepci22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	unsigned int countmax = 0;
+	volatile unsigned long *ptr;
+	volatile unsigned long val;
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	size = simple_strtol (argv[2], NULL, 16);
+
+	addr = PCI_ADDR | (addr & 0x00ffffff);
+	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
+	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
+
+	while (1) {
+
+		/*
+		 * Write one values to host via pci busmastering
+		 */
+		ptr = (volatile unsigned long *)addr;
+		*ptr = 0x01234567;
+
+		/*
+		 * Read one value back
+		 */
+		ptr = (volatile unsigned long *)addr;
+		val = *ptr;
+
+		/*
+		 * One pci config write
+		 */
+		ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	writepci22,	4,	1,	do_writepci22,
+	"writepci22- Write some data to pcibus\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+int ibmPciConfigWrite3
+(
+	int offset,     /* offset into the configuration space */
+	int width,      /* data width                          */
+	unsigned int data       /* data to be written                  */
+	)
+{
+	/*
+	 * Write config register address to the PCI config address register
+	 * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation)
+	 */
+	out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC));
+
+#if 1 /* test-only */
+	ppcSync();
+#endif
+
+	/*
+	 * Write value to be written to the PCI config data register
+	 */
+	switch ( width ) {
+	case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF));
+		break;
+	case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF));
+		break;
+	case 4:	out32r(PCI_CFGDATA | (offset & 0x3), data);
+		break;
+	}
+
+	return (0);
+}
+
+int do_writepci3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	unsigned int countmax;
+	int max;
+	volatile unsigned long *ptr;
+	volatile unsigned long val;
+	int loopcount = 0;
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	size = simple_strtol (argv[2], NULL, 16);
+	countmax = simple_strtol (argv[3], NULL, 16);
+	if (countmax == 0)
+		countmax = 1000;
+
+	do_getplb(NULL, 0, 0, NULL);
+
+#if 0
+	out32r(PMM0LA, 0);
+	out32r(PMM0PCILA, 0);
+	out32r(PMM0PCIHA, 0);
+	out32r(PMM0MA, 0);
+	out32r(PMM1LA, PCI_ADDR);
+	out32r(PMM1PCILA, addr & 0xff000000);
+	out32r(PMM1PCIHA, 0x00000000);
+	out32r(PMM1MA, 0xff000001);
+#endif
+
+	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
+	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
+	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
+	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
+
+	addr = PCI_ADDR | (addr & 0x00ffffff);
+	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
+
+	max = size >> 2;
+
+	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
+
+	while (1) {
+
+		/*
+		 * Write one values to host via pci busmastering
+		 */
+		ptr = (volatile unsigned long *)addr;
+		*ptr = 0x01234567;
+
+		/*
+		 * Read one value back
+		 */
+		ptr = (volatile unsigned long *)addr;
+		val = *ptr;
+
+		/*
+		 * One pci config write
+		 */
+/*		pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
+/*		ibmPciConfigWrite(0x44, 1, 0x00); */
+		ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */
+
+		if (loopcount++ > countmax) {
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+
+			putc('.');
+
+			loopcount = 0;
+		}
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	writepci3,	4,	1,	do_writepci3,
+	"writepci3- Write some data to pcibus\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+
+#define SECTOR_SIZE 	32		/* 32 byte cache line */
+#define SECTOR_MASK	0x1F
+
+void my_flush_dcache(ulong lcl_addr, ulong count)
+{
+  unsigned int lcl_target;
+
+  /* promote to nearest cache sector */
+  lcl_target =  (lcl_addr + count + SECTOR_SIZE - 1) & ~SECTOR_MASK;
+  lcl_addr &= ~SECTOR_MASK;
+  while (lcl_addr != lcl_target)
+    {
+      /*      ppcDcbf((void *)lcl_addr);*/
+      __asm__("dcbf 0,%0": :"r" (lcl_addr));
+      lcl_addr += SECTOR_SIZE;
+    }
+  __asm__("sync");		/* Always flush prefetch queue in any case */
+}
+
+int do_writepci_cache(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	unsigned int countmax;
+	int i;
+	volatile unsigned long *ptr;
+	volatile unsigned long val;
+	int loopcount = 0;
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	size = simple_strtol (argv[2], NULL, 16);
+	countmax = simple_strtol (argv[3], NULL, 16);
+	if (countmax == 0)
+		countmax = 1000;
+
+	do_getplb(NULL, 0, 0, NULL);
+
+#if 0
+	out32r(PMM0LA, 0);
+	out32r(PMM0PCILA, 0);
+	out32r(PMM0PCIHA, 0);
+	out32r(PMM0MA, 0);
+	out32r(PMM1LA, PCI_ADDR);
+	out32r(PMM1PCILA, addr & 0xff000000);
+	out32r(PMM1PCIHA, 0x00000000);
+	out32r(PMM1MA, 0xff000001);
+#endif
+
+	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
+	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
+	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
+	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
+
+	addr = PCI_ADDR | (addr & 0x00ffffff);
+	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
+
+	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
+
+	i = 0;
+
+	/*
+	 * Set pci region as cachable
+	 */
+	ppcSync();
+	__asm__ volatile ("	addis	4,0,0x0000 ");
+	__asm__ volatile ("	addi	4,4,0x0080 ");
+	__asm__ volatile ("	mtdccr	4 ");
+	ppcSync();
+
+	while (1) {
+
+		/*
+		 * Write one values to host via pci busmastering
+		 */
+		ptr = (volatile unsigned long *)addr;
+		printf("A\n"); /* test-only */
+		*ptr++ = i++;
+		*ptr++ = i++;
+		*ptr++ = i++;
+		*ptr++ = i++;
+		*ptr++ = i++;
+		*ptr++ = i++;
+		*ptr++ = i++;
+		*ptr++ = i++;
+		printf("B\n"); /* test-only */
+		my_flush_dcache(addr, 32);
+		printf("C\n"); /* test-only */
+
+		/*
+		 * Read one value back
+		 */
+		ptr = (volatile unsigned long *)addr;
+		val = *ptr;
+		printf("D\n"); /* test-only */
+
+		/*
+		 * One pci config write
+		 */
+/*		pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
+/*		ibmPciConfigWrite(0x44, 1, 0x00); */
+		ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */
+		printf("E\n"); /* test-only */
+
+		if (loopcount++ > countmax) {
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+
+			putc('.');
+
+			loopcount = 0;
+		}
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	writepci_cache,	4,	1,	do_writepci_cache,
+	"writepci_cache - Write some data to pcibus\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+int do_savepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int *ptr;
+	int i;
+
+	/*
+	 * Save own pci configuration in PRAM
+	 */
+	memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
+	ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+	for (i=0; i<0x40; i+=4) {
+		pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
+	}
+	ptr = (unsigned int *)PCI_REGS_ADDR;
+	*ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
+
+	printf("\nStoring PCI Configuration Regs...\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	savepci,	4,	1,	do_savepci,
+	"savepci  - Save all pci regs\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+int do_restorepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int *ptr;
+	int i;
+
+	/*
+	 * Rewrite pci config regs (only after soft-reset with magic set)
+	 */
+	ptr = (unsigned int *)PCI_REGS_ADDR;
+	if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+		puts("Restoring PCI Configurations Regs!\n");
+		ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+		for (i=0; i<0x40; i+=4) {
+			pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
+		}
+	}
+	mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+
+	return 0;
+}
+U_BOOT_CMD(
+	restorepci,	4,	1,	do_restorepci,
+	"restorepci  - Restore all pci regs\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+
+extern void write_without_sync(void);
+extern void write_with_sync(void);
+extern void write_with_less_sync(void);
+extern void write_with_more_sync(void);
+
+/*
+ * code from IBM-PPCSUPP
+ */
+int do_writeibm1(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
+
+	write_without_sync();
+
+	return 0;
+}
+U_BOOT_CMD(
+	writeibm1,	4,	1,	do_writeibm1,
+	"writeibm1- Write some data to pcibus (without sync)\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+int do_writeibm2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
+
+	write_with_sync();
+
+	return 0;
+}
+U_BOOT_CMD(
+	writeibm2,	4,	1,	do_writeibm2,
+	"writeibm2- Write some data to pcibus (with sync)\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+int do_writeibm22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
+
+	write_with_less_sync();
+
+	return 0;
+}
+U_BOOT_CMD(
+	writeibm22,	4,	1,	do_writeibm22,
+	"writeibm22- Write some data to pcibus (with less sync)\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+
+int do_writeibm3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
+
+	write_with_more_sync();
+
+	return 0;
+}
+U_BOOT_CMD(
+	writeibm3,	4,	1,	do_writeibm3,
+	"writeibm3- Write some data to pcibus (with more sync)\n",
+	"<addr> <size>\n"
+	"        - Write some data to pcibus.\n"
+);
+#endif
diff --git a/board/esd/pci405/config.mk b/board/esd/pci405/config.mk
new file mode 100755
index 0000000..83f07fe
--- /dev/null
+++ b/board/esd/pci405/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0xFFFD0000
diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c
new file mode 100755
index 0000000..3b21781
--- /dev/null
+++ b/board/esd/pci405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -monitor_flash_len,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/pci405/fpgadata.c b/board/esd/pci405/fpgadata.c
new file mode 100755
index 0000000..c64ad95
--- /dev/null
+++ b/board/esd/pci405/fpgadata.c
@@ -0,0 +1,746 @@
+  0x1f,0x8b,0x08,0x08,0xcd,0x78,0x61,0x3f,0x00,0x03,0x70,0x63,0x69,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x34,0x2e,0x62,0x69,0x74,0x00,0xed,0x9c,0x7f,0x78,0x14,0xc7,
+  0x99,0xe7,0xdf,0xae,0xee,0x11,0x2d,0xcd,0x88,0x69,0x89,0x11,0x1e,0x3b,0x32,0xdb,
+  0x1a,0x09,0x3c,0xc1,0x23,0x69,0x18,0x61,0x85,0x60,0x79,0xd4,0x8c,0x04,0x19,0x1b,
+  0xd9,0x4c,0x6c,0x27,0x61,0xf3,0xf8,0xc9,0x8e,0x1d,0x92,0x23,0x59,0x92,0x47,0x90,
+  0xdc,0x2e,0x49,0x9c,0x6c,0x8d,0x24,0xd0,0x00,0xb2,0x19,0x30,0x97,0xb0,0x59,0xce,
+  0x3b,0x60,0x12,0x0b,0x9b,0x64,0x07,0x61,0x1b,0x61,0x88,0xdd,0x92,0x85,0x23,0x40,
+  0x06,0x85,0xf5,0x79,0xb1,0xcd,0xe2,0xc1,0x91,0xbd,0xb2,0x23,0x63,0x19,0xb3,0x8e,
+  0x00,0x19,0xdd,0x5b,0xdd,0x3d,0xdd,0x2d,0xe1,0xfd,0x71,0xb7,0xf7,0xdc,0xde,0xf3,
+  0x9c,0xdb,0x7f,0xb8,0x50,0xa9,0xba,0xab,0xab,0xde,0xfa,0xd4,0xf7,0x7d,0xdf,0x6a,
+  0x41,0xbe,0x7b,0x54,0xff,0x0f,0x80,0xbb,0x1f,0xa4,0xe6,0xaf,0x7f,0x6b,0x7e,0xf0,
+  0x96,0x3f,0x9b,0xf7,0x67,0xc1,0xf9,0x55,0xdf,0xfd,0xfa,0x0a,0x78,0x00,0x0a,0x42,
+  0xdf,0x9b,0x77,0xcb,0xf7,0x57,0xcf,0x9b,0x3f,0x1f,0xbe,0x0e,0xce,0x50,0x30,0x58,
+  0x53,0x1d,0x5c,0x50,0x1d,0xba,0x05,0x56,0x40,0xfe,0xbc,0x05,0x0b,0x83,0xb7,0x2c,
+  0x9c,0x57,0x03,0xdf,0x00,0x88,0x27,0x27,0xf0,0x7a,0xe2,0xaf,0xbf,0xf4,0xcd,0x20,
+  0x50,0x0e,0x00,0xa6,0x05,0xb9,0x38,0xfb,0x7f,0x5e,0x90,0x93,0x39,0xa0,0xf5,0x95,
+  0x41,0x50,0xd9,0xbf,0xc1,0xa8,0xcf,0x0f,0x82,0x6c,0xff,0x37,0x17,0x04,0x05,0x62,
+  0xe0,0xf9,0x0e,0x14,0x4b,0x30,0xe5,0xe2,0x14,0x81,0xea,0xa5,0x7f,0xad,0x8e,0x4c,
+  0xad,0x62,0xd7,0xbf,0xa3,0xae,0xf8,0x13,0xaa,0x84,0xff,0x58,0xdd,0x84,0x04,0x71,
+  0xf0,0x42,0x1e,0x70,0xd4,0x2c,0xd4,0xf7,0xe9,0x75,0xaa,0x63,0x5c,0x7e,0xbd,0x68,
+  0x46,0x9f,0xbb,0x9f,0x8c,0xd3,0x93,0x05,0x3e,0xa5,0x70,0x8c,0x0f,0x42,0xb3,0xde,
+  0x23,0xe9,0x3d,0xba,0x59,0x29,0xff,0x47,0x67,0x92,0x5c,0x8d,0x6c,0x96,0x7d,0x59,
+  0x31,0x58,0x20,0x0b,0x41,0xad,0x2e,0xe9,0x18,0x96,0x1f,0x89,0x77,0xf6,0x3b,0x81,
+  0x74,0xc0,0x63,0xa2,0x4f,0xc9,0x0f,0x92,0x5d,0x9c,0xde,0x4e,0x2d,0xe9,0x74,0x3c,
+  0x29,0xcc,0x55,0x9d,0x69,0x18,0x11,0x9e,0x04,0xd6,0x8e,0x64,0x84,0xb8,0xde,0xa7,
+  0x92,0x63,0xf0,0xba,0xb0,0x50,0x75,0xb7,0xf1,0x7b,0xe1,0x0f,0x10,0x6a,0x2e,0xcc,
+  0xf0,0x54,0xd0,0xdb,0x65,0xb9,0x27,0x94,0xd7,0xe1,0x73,0x3d,0xee,0x97,0x1b,0x46,
+  0xe0,0x1f,0xe0,0x79,0xd5,0x3d,0xca,0xaf,0x05,0xbd,0x9d,0x22,0xed,0x26,0xc7,0x21,
+  0xa4,0xba,0x93,0xfc,0x00,0x1c,0x87,0xae,0xd8,0xf4,0x0c,0x2f,0x09,0xb2,0x56,0xd7,
+  0xef,0xa8,0xfb,0xb6,0x9b,0x94,0xab,0xce,0xa7,0xc8,0x55,0x79,0x33,0xc8,0xaa,0x98,
+  0x21,0x21,0x9c,0x3f,0xed,0x9e,0x8e,0x3b,0xc9,0x26,0xfc,0x91,0x33,0xd8,0x32,0x00,
+  0x8f,0x80,0x4c,0x0b,0x82,0x64,0x01,0xce,0x2c,0xbb,0xe2,0xdc,0xac,0xb6,0x76,0x5a,
+  0x96,0x75,0xfe,0x29,0x39,0x0b,0x3f,0xa3,0xe5,0x9d,0xe2,0x5a,0xe2,0x35,0xda,0x45,
+  0x45,0x11,0x5e,0x68,0x09,0x1e,0x75,0xcf,0xe7,0x07,0x92,0xaf,0xd3,0xe0,0xf0,0x5d,
+  0x41,0x67,0xb1,0x31,0x6f,0xca,0x8d,0xdd,0xf4,0x7d,0x8e,0x75,0xaf,0x61,0x5c,0x7e,
+  0x1f,0x6e,0xa3,0xee,0x0f,0xf8,0xc1,0x3c,0xbd,0x9f,0x9d,0xdc,0xb0,0xe0,0xfc,0x76,
+  0x78,0x60,0x73,0x95,0x33,0x90,0xbe,0x22,0x97,0x52,0x57,0x86,0x7f,0xd7,0x18,0xcf,
+  0x68,0xd1,0xc6,0x64,0xbb,0x5c,0x39,0xe0,0x8c,0xb5,0x94,0xc2,0x81,0x95,0x95,0x54,
+  0x6c,0x26,0xa7,0x8c,0x71,0xa1,0xf0,0xa8,0xf2,0xf8,0xb6,0xca,0xec,0xa6,0xe1,0xbc,
+  0x59,0x70,0x80,0x56,0xa7,0xb1,0x2f,0x59,0x30,0xde,0x4f,0x3a,0x91,0x78,0x0c,0x56,
+  0xa9,0xce,0xd0,0xcc,0x26,0xd8,0x0f,0x81,0x14,0x8e,0xe7,0x05,0x63,0x1e,0x86,0x4b,
+  0x0e,0xb5,0xbc,0x0b,0x61,0xea,0x4e,0xf3,0x7e,0xb8,0x0c,0xf5,0x89,0x1d,0x69,0xfe,
+  0xb2,0x71,0xcf,0x28,0x8e,0xe8,0x69,0x78,0x10,0x70,0xac,0xd3,0x30,0x06,0x61,0x52,
+  0xdf,0xc6,0x9f,0x02,0xbd,0x9d,0x28,0x1d,0x81,0xa3,0x10,0x52,0x2a,0xbb,0xf8,0x21,
+  0xe1,0x28,0xd4,0xad,0x3c,0x91,0x2a,0xef,0x35,0xee,0x49,0x85,0x6f,0x8a,0xac,0x4e,
+  0xdc,0xe6,0xeb,0x53,0x36,0x40,0x55,0x5c,0xfc,0x29,0xf6,0x45,0xb7,0x75,0xaf,0xa3,
+  0x02,0xb6,0x80,0x6f,0x91,0xb8,0x2d,0x6f,0x08,0x36,0xc0,0x77,0x55,0x48,0x91,0x17,
+  0x8d,0x31,0x13,0x85,0x42,0x92,0x50,0xe4,0x2f,0x8a,0x52,0xde,0x8b,0x90,0x50,0x56,
+  0x2d,0x12,0x3d,0xa4,0x97,0xd3,0xc7,0xac,0xbb,0x30,0x4e,0xfa,0xb9,0x10,0xb8,0x28,
+  0x9f,0x25,0xfd,0x10,0x86,0x2a,0xca,0x9f,0xe7,0xf5,0x79,0xd8,0x7e,0xe3,0x3f,0xc3,
+  0x3b,0xca,0xb3,0x31,0x77,0x6a,0xc6,0x5b,0x70,0x49,0xa9,0xc7,0x02,0xff,0x76,0x9e,
+  0x3e,0x66,0xdb,0x1d,0xaf,0xc0,0xab,0x10,0x56,0x02,0x29,0x7e,0x08,0x2e,0x49,0xf5,
+  0x77,0xb8,0x07,0xf9,0x39,0xc6,0x78,0x2e,0x90,0x7e,0xff,0x66,0x52,0xae,0x12,0x45,
+  0x8a,0xdd,0xeb,0xf6,0x54,0x49,0xce,0x16,0x32,0xdd,0x78,0x07,0xd1,0xd1,0xe7,0xdc,
+  0x19,0x0d,0xdc,0x1d,0x95,0x48,0x9f,0xb2,0x8f,0x0b,0x64,0x9d,0x52,0x4b,0x8b,0x61,
+  0x9f,0xde,0x92,0x5f,0x90,0x3d,0x10,0x50,0xc4,0x54,0xde,0x08,0x77,0x10,0xaa,0x14,
+  0x67,0x8a,0xac,0x37,0xc6,0x2c,0x5d,0xf4,0xb6,0xe7,0x92,0x10,0x56,0x5c,0xf8,0x3c,
+  0xe9,0x12,0x84,0xb1,0x2f,0xce,0x4e,0xc3,0xce,0xfc,0xdc,0xe3,0x70,0x3d,0x84,0x17,
+  0xb9,0xbb,0xf8,0x11,0xc0,0x3a,0x65,0x5a,0x8a,0xbf,0xc3,0x98,0x23,0xbf,0x44,0xd9,
+  0x10,0x83,0xbb,0x85,0x97,0xe5,0x31,0xe8,0x02,0x57,0x92,0x3f,0x96,0x6b,0xe7,0x58,
+  0xa8,0x6c,0xe4,0xaa,0xa8,0x73,0x37,0xff,0x2d,0xcf,0xb3,0xe0,0xa3,0xe2,0x30,0x39,
+  0x66,0x2c,0x51,0xbf,0x63,0x19,0xd7,0x0a,0x01,0xb4,0x4f,0x52,0x88,0x73,0x2b,0x2b,
+  0x62,0x37,0xd6,0xe9,0xe3,0x92,0xe6,0x4a,0xe5,0xf6,0xda,0xca,0x7e,0xe7,0x18,0xb9,
+  0x0f,0x6d,0xa2,0x3c,0xee,0x6f,0x6e,0xe9,0x37,0xc6,0xba,0x53,0x9c,0x05,0xff,0x44,
+  0x7f,0x7c,0xd9,0x3d,0x7c,0xdd,0x2c,0xf8,0x50,0x9d,0x17,0x77,0xad,0xe5,0x8f,0x19,
+  0xf6,0x29,0x16,0xee,0x26,0x7f,0xa8,0x08,0x9f,0x76,0xaf,0xff,0xc2,0x5b,0xe9,0x2b,
+  0x2b,0xeb,0x14,0x77,0x86,0xef,0x35,0xec,0x53,0x71,0x5c,0x90,0x4e,0xaa,0x37,0x0f,
+  0x09,0xe3,0x0d,0x0b,0x61,0x82,0xd6,0xc7,0x5d,0x63,0xbc,0x64,0x8c,0x67,0x67,0x51,
+  0x86,0x6c,0xce,0x94,0xab,0xe2,0xb7,0xf8,0xe5,0xd8,0x97,0xca,0x95,0xe2,0xa8,0x6f,
+  0xae,0x31,0x2e,0xc5,0x90,0x8a,0xff,0x5d,0xf1,0xfd,0x6a,0xb4,0xb9,0xc5,0x0b,0x07,
+  0xa0,0xb2,0x49,0x8c,0x13,0x81,0xea,0xef,0x17,0x97,0xfa,0x0b,0x1e,0x83,0xb4,0xda,
+  0x29,0x10,0x45,0x44,0xfb,0x8c,0x8b,0x69,0xe2,0x6d,0xd3,0xe7,0xa1,0xb3,0xe4,0xd7,
+  0xe4,0x7d,0xa8,0x51,0x5d,0xdb,0xf8,0x0a,0x98,0xe0,0xea,0xd4,0x8e,0x94,0xb3,0xaa,
+  0x4d,0xbf,0x67,0x0a,0xde,0x83,0xbf,0x87,0x9f,0xa8,0x38,0xdd,0x23,0x70,0x05,0x66,
+  0x0d,0x60,0x21,0x6b,0xd8,0x67,0x42,0x1a,0x87,0x93,0x30,0x4f,0xed,0x18,0x69,0xbd,
+  0x40,0xeb,0xd1,0x18,0x5d,0x83,0xbc,0xdc,0xa8,0xd7,0xad,0x13,0x16,0x93,0x4d,0x42,
+  0x48,0xf5,0x27,0x23,0xbf,0x87,0x43,0xe0,0x8b,0x8b,0x29,0x52,0xa1,0xe8,0xf6,0x49,
+  0x1d,0x15,0xf2,0x26,0xf0,0xa9,0xf8,0xa3,0x21,0x7c,0x07,0x5f,0xa3,0xd8,0x45,0x64,
+  0x63,0x3c,0x45,0x01,0xa0,0x35,0x88,0x78,0x20,0x64,0x00,0xeb,0x1e,0x68,0xc2,0x75,
+  0x44,0x0c,0xfb,0xa4,0x85,0x71,0xf1,0xa4,0xbf,0x46,0x15,0xbb,0x5a,0xb3,0x30,0xa1,
+  0x74,0x29,0xae,0x34,0x2f,0x13,0x63,0x1e,0x6e,0x1c,0x13,0xae,0xc8,0xb7,0xaa,0x6e,
+  0xe0,0x47,0x61,0xc2,0x1f,0x5e,0xee,0xce,0xf2,0xc3,0xd3,0x0c,0xd6,0x39,0xc6,0xc9,
+  0x49,0x39,0x2c,0xbb,0x2f,0xf0,0x21,0xe5,0x64,0x4b,0x38,0x1b,0x18,0xc3,0x5f,0xca,
+  0xf1,0x73,0x42,0xd8,0x1c,0xac,0x2a,0x70,0x7e,0x44,0xfc,0x74,0x13,0xad,0xca,0xe2,
+  0xdc,0x66,0x4d,0x7e,0xbe,0x84,0xd8,0x5c,0x45,0x9d,0xf3,0x5a,0x28,0x7d,0x0c,0x0d,
+  0x00,0xfb,0xf2,0xa6,0xc9,0xcf,0xbd,0xf0,0x24,0x54,0x25,0x9d,0x19,0x5f,0x27,0x2b,
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+  0x2e,0x02,0x45,0xb4,0x44,0x31,0xfb,0x99,0xc7,0x2d,0xa2,0xf7,0xc6,0x4b,0xbc,0x8e,
+  0x3c,0xee,0x8b,0x34,0x16,0xf7,0x78,0x1d,0x60,0xce,0x7b,0x31,0x27,0xd0,0x7c,0x59,
+  0x8a,0x0a,0xc5,0x0e,0x01,0x27,0x04,0x0b,0xd6,0xbc,0x37,0xf2,0x5f,0xa4,0x6d,0xf1,
+  0x6f,0x78,0x5d,0x4b,0xc8,0x17,0x13,0x2f,0xc7,0x6f,0xf1,0x16,0x9a,0xf7,0x3c,0xb2,
+  0x64,0xda,0xea,0xc4,0x99,0xf8,0x57,0xbc,0x25,0xeb,0x1d,0xab,0x13,0xf7,0xc5,0xff,
+  0xd2,0x5b,0x62,0xda,0xe0,0xe2,0x25,0xdc,0x6a,0xba,0x3c,0x7e,0x9d,0xb7,0xf0,0x45,
+  0x2c,0x9c,0x61,0x05,0xb5,0xc8,0xac,0xcb,0x9b,0x47,0x5d,0xf1,0x7b,0xbc,0x9e,0x17,
+  0x67,0xce,0xa3,0xa5,0xf1,0x06,0x6c,0x57,0x94,0x8b,0x6d,0x03,0x0e,0x7f,0x93,0x4c,
+  0xc4,0xc5,0x2d,0x5c,0x1c,0x27,0xf1,0x3a,0xb4,0xcf,0x5c,0x8d,0x90,0xc7,0x95,0x25,
+  0x96,0xc7,0x67,0x7a,0x1d,0xeb,0xb9,0x32,0x1a,0x8d,0x7f,0xd9,0xeb,0xa0,0xb9,0x75,
+  0xb4,0x58,0x11,0x9a,0xb9,0x26,0x98,0x01,0x92,0xea,0x68,0x86,0x26,0xf8,0x0a,0x78,
+  0xcc,0x7b,0x2e,0x26,0x10,0x4f,0x8b,0x38,0x9e,0xd0,0x02,0x71,0x1c,0x4f,0xd4,0x3a,
+  0xd4,0xec,0x4b,0x44,0x90,0x77,0x7a,0xe5,0x25,0xfe,0xa2,0x16,0x41,0x4e,0x48,0x72,
+  0xc4,0x5f,0x64,0xab,0x2b,0x53,0x54,0x4f,0xf0,0x4b,0xae,0x92,0x08,0xa7,0xf4,0xdc,
+  0x5b,0xe6,0x71,0x95,0x28,0x66,0x3f,0x09,0x17,0xeb,0xbf,0x17,0x4d,0xd6,0x11,0xe1,
+  0x62,0xf4,0xde,0x20,0x16,0x94,0x5c,0x5f,0x70,0xc5,0xc7,0x8b,0x24,0x10,0x60,0x91,
+  0x28,0x28,0xe0,0x45,0xfb,0x34,0x6b,0x60,0xf1,0xdd,0x11,0x5f,0x82,0xca,0xb2,0x28,
+  0x12,0x22,0xeb,0x05,0x30,0xfb,0xa9,0x2c,0x63,0xeb,0xef,0x2f,0xa0,0x84,0x3a,0x72,
+  0x85,0x5c,0x5f,0x8e,0x28,0x8b,0x9a,0xd9,0x09,0x18,0x5c,0x92,0x0e,0xa6,0x94,0xaf,
+  0x83,0x3b,0xcd,0x71,0x01,0x98,0x13,0xe7,0x4a,0x81,0xe0,0xbb,0xcf,0x94,0xf1,0xe1,
+  0x4b,0xa0,0x48,0x35,0xab,0x24,0x98,0x0d,0xf9,0x40,0x14,0x78,0x05,0x2a,0x58,0xc1,
+  0xfc,0x8b,0x1d,0x78,0x55,0x70,0xf3,0xee,0x6f,0x52,0x8a,0x25,0xa1,0x8f,0x2b,0x83,
+  0x68,0xec,0x1e,0x49,0xb0,0xda,0xf9,0x1c,0xdf,0x3a,0xf7,0xd5,0xe0,0xcc,0x8e,0x92,
+  0xc7,0xb9,0x95,0xea,0xdd,0xc1,0x2f,0x77,0x94,0x50,0xdb,0x3d,0x6b,0xf1,0x56,0x11,
+  0x05,0x52,0x78,0x8b,0x29,0xf7,0x14,0x85,0x60,0x91,0x57,0x58,0xc2,0x15,0x25,0x95,
+  0x78,0x91,0xb7,0x0d,0x0b,0xb6,0x7e,0xf6,0x14,0x89,0xf7,0x0a,0x5f,0xe2,0x4b,0x94,
+  0xfb,0x63,0x45,0xf7,0x0a,0x25,0xdc,0x97,0x14,0xab,0x5d,0x59,0x44,0x54,0x5a,0x3c,
+  0xf2,0xba,0x28,0x16,0xee,0x65,0x05,0xab,0xae,0x60,0x31,0xa1,0xc0,0x04,0x68,0x81,
+  0x83,0x50,0x25,0x2d,0xf9,0xad,0x3b,0x82,0x8b,0xbf,0x07,0xda,0x7a,0x56,0x07,0x45,
+  0x2c,0x70,0xdb,0xd4,0x5b,0x82,0xa2,0xed,0x9e,0x8e,0x35,0xdc,0x7d,0xf4,0x2b,0xf2,
+  0xf5,0xfd,0x5a,0xe1,0x2f,0x91,0x59,0x66,0x1d,0x8f,0x50,0x91,0x82,0x82,0x8b,0x63,
+  0x85,0xa2,0x90,0xe0,0x2a,0xb2,0xee,0x59,0x3f,0xb1,0x6c,0xe2,0xef,0x27,0x2e,0x4e,
+  0x7c,0x6c,0x16,0xe0,0xdf,0x75,0x85,0xdf,0x58,0x76,0xb5,0xf7,0xa5,0xcc,0xfe,0x1f,
+  0x87,0x5f,0x77,0xd6,0xb2,0xc2,0x2a,0xdb,0x3d,0xeb,0x97,0x4d,0xcc,0xa8,0xe9,0x1b,
+  0xf8,0xb8,0xbe,0xae,0xe9,0x24,0x2b,0x7c,0x60,0xab,0xf3,0x46,0xcf,0x16,0xcf,0x6b,
+  0xeb,0xf8,0xc1,0xad,0xde,0xe8,0x8b,0x33,0x0e,0x60,0xc1,0xaa,0x9b,0x06,0xab,0x95,
+  0x1d,0xb1,0x9b,0x3c,0xf9,0x47,0x48,0xb3,0x52,0x2a,0xdd,0x24,0xe4,0x5b,0xef,0x20,
+  0x98,0x9c,0x77,0xac,0xe6,0x74,0xce,0x9b,0x75,0x1a,0xe7,0xe3,0xc5,0x5e,0x61,0xbd,
+  0xc9,0x79,0xab,0x5d,0xfc,0x7e,0xed,0xef,0xa9,0x08,0x16,0xaf,0xad,0x31,0x13,0xd6,
+  0x24,0x4a,0xd5,0x2f,0xc8,0x45,0xfd,0xc2,0x1a,0xae,0x94,0x62,0xc1,0xba,0x27,0x00,
+  0xb6,0x93,0xf3,0x44,0xdb,0x1f,0x64,0x31,0x6b,0x24,0x61,0x0e,0x97,0x4f,0x23,0xcd,
+  0xd2,0xcf,0x85,0xd9,0x9c,0x48,0x19,0xe7,0xcd,0xba,0x32,0x58,0x9a,0x28,0x4e,0x37,
+  0x76,0x16,0x55,0x09,0x51,0xaa,0x15,0xcc,0xa7,0xa9,0x55,0xb8,0x66,0x3d,0xd4,0x11,
+  0xe4,0xee,0x82,0x7b,0x70,0xcd,0x62,0xc1,0xd8,0x52,0xd9,0x81,0x5a,0xe1,0x16,0x28,
+  0x52,0x84,0xe5,0x9c,0x07,0xbe,0x40,0xd9,0x82,0xe2,0x8c,0x6d,0x1a,0xdb,0x29,0x44,
+  0x62,0xa7,0xde,0xd8,0x01,0x32,0x30,0x0a,0x56,0x9d,0xc0,0x00,0x88,0xcb,0x80,0x62,
+  0x61,0x3b,0x5b,0x0f,0xd4,0xa8,0x93,0x38,0x05,0x55,0xc7,0x76,0x98,0x03,0xf9,0x94,
+  0x3c,0x80,0xef,0x80,0x85,0x16,0xe3,0x71,0xca,0xe2,0xbb,0xf3,0xe2,0xc8,0xf9,0x06,
+  0x51,0xea,0x15,0x82,0x7a,0x21,0xc7,0x10,0x05,0x6f,0x2f,0x1b,0x78,0xc7,0xe7,0x18,
+  0x05,0xa3,0x1d,0x38,0x21,0x48,0xd9,0xfe,0x00,0xbd,0x10,0xec,0xd1,0x0a,0x66,0xdd,
+  0xe2,0x06,0xa1,0x19,0x31,0xbd,0x44,0x44,0xbe,0xc4,0x7b,0xb4,0x02,0xcd,0xdd,0x93,
+  0x63,0x9c,0x17,0x91,0x75,0xc0,0xf6,0x29,0x17,0x2b,0xe4,0xc6,0x2c,0xc6,0x21,0x97,
+  0xcc,0x76,0xd8,0x17,0xd6,0xce,0xbc,0xa7,0x82,0xef,0xe1,0x81,0xc5,0x6c,0x6c,0x70,
+  0x0b,0x64,0x85,0x88,0x71,0xcf,0x28,0x4e,0xca,0x22,0x2a,0xc5,0x05,0xaf,0x90,0x2b,
+  0x98,0xec,0x89,0x6a,0xe7,0x6c,0x10,0xef,0xa2,0x80,0xee,0x9b,0x5e,0x00,0xf3,0x9e,
+  0x8c,0xf3,0x0c,0xef,0xf9,0x4b,0x8c,0x42,0xa1,0xc9,0x3a,0x6e,0x89,0xb0,0x3a,0x51,
+  0x1a,0xff,0x82,0xb7,0xe8,0x45,0x61,0xf5,0xba,0x1d,0xac,0x60,0xbe,0x1f,0x8e,0xf2,
+  0x6a,0xba,0x23,0x7e,0x93,0x37,0xff,0x45,0xb2,0x9a,0xde,0xc7,0x0a,0xb9,0xba,0x18,
+  0xe3,0x3c,0x6e,0x0b,0xb8,0x3f,0xbc,0xe8,0x60,0x37,0xc0,0x42,0xaf,0x39,0x9e,0xc5,
+  0x50,0x41,0x6f,0x97,0x8b,0xa3,0xc2,0x56,0xae,0x82,0x36,0xd9,0xed,0x53,0xc1,0x77,
+  0x28,0xa3,0xde,0x78,0x9e,0x97,0x5b,0x0f,0xf7,0x27,0xb4,0x82,0x69,0x4b,0x8b,0xe3,
+  0x8e,0x05,0xdc,0x2c,0x34,0x87,0xa2,0xac,0xb0,0x56,0x2f,0x98,0x73,0xc4,0xdd,0x0d,
+  0x2b,0xe8,0xf5,0x72,0x5e,0x94,0xdb,0x8a,0x05,0xc3,0x50,0x73,0xfd,0x64,0xe3,0xc9,
+  0xf6,0x00,0xa9,0x25,0x57,0xb0,0xc6,0x33,0x02,0x31,0x44,0x7f,0xa3,0x58,0x44,0x04,
+  0x85,0x6a,0x05,0x30,0xfb,0x49,0x20,0x86,0x7b,0x80,0xc3,0xc5,0x35,0xe4,0x0a,0x8a,
+  0xd9,0x4f,0x51,0x78,0x00,0x72,0xba,0x46,0x2f,0x58,0xe3,0x19,0x21,0x40,0x0d,0xce,
+  0x1b,0x05,0xf3,0x9e,0x9c,0x52,0x11,0x77,0x78,0x61,0x92,0x7d,0x9a,0xfd,0x54,0x80,
+  0xfd,0xa5,0x85,0x39,0x4a,0x7e,0x8a,0xac,0x80,0x52,0xcd,0x50,0xcd,0x7b,0xc6,0xe7,
+  0xf8,0xb9,0xe9,0xd0,0x40,0xa5,0xac,0xb0,0x80,0xbb,0x81,0x15,0x72,0xef,0x1e,0xc3,
+  0xa5,0x51,0xa6,0xb8,0x62,0xbc,0x07,0x8e,0xd0,0x79,0x8a,0x28,0xf1,0x82,0xcd,0x3e,
+  0x05,0x98,0xad,0x14,0x4a,0xfc,0xbd,0xf0,0x3b,0x98,0xbf,0x48,0xfb,0xa5,0x5e,0xab,
+  0x9f,0xc2,0xfd,0x3d,0xde,0xe0,0x92,0xd2,0xa2,0x56,0x66,0x9f,0xc1,0x25,0x2e,0x9b,
+  0x7d,0x2a,0x68,0xea,0xb6,0xf5,0x65,0xe3,0xbc,0xc2,0x45,0x1b,0x43,0x0c,0xef,0x65,
+  0x45,0x1d,0x8d,0x0f,0x5c,0xaf,0x15,0x6c,0xf6,0xa9,0x4a,0x3f,0xf0,0xcc,0x5a,0x5c,
+  0xb4,0x45,0x69,0x8c,0xc5,0x3c,0xc2,0x62,0xae,0x48,0xb1,0xd6,0x11,0x1b,0x7a,0x22,
+  0x94,0x25,0xc4,0xb8,0xa2,0x4f,0x06,0x98,0x57,0x0e,0xef,0x42,0x01,0x67,0x14,0xac,
+  0xf1,0xbc,0x93,0xbf,0x47,0x79,0x79,0xf0,0x96,0xf9,0x85,0x66,0xc1,0xbc,0x27,0x17,
+  0xad,0x58,0x53,0x58,0x4a,0xbe,0x50,0x56,0xa4,0x36,0xae,0xc9,0xdf,0x31,0x99,0x59,
+  0x33,0x6c,0x9c,0xef,0x29,0x0a,0x35,0x36,0x6d,0xb1,0x9e,0xf7,0xbf,0xcb,0xf9,0x4a,
+  0x5b,0xbb,0xab,0x53,0x38,0x5f,0x63,0xbf,0xe7,0x14,0xce,0xdf,0xea,0xbd,0xeb,0x8d,
+  0x47,0x0e,0x0c,0xbd,0x77,0xe9,0xd6,0x9f,0xdc,0x75,0x76,0x06,0x2b,0x58,0x75,0xe8,
+  0xc3,0xec,0x04,0xbf,0x52,0x50,0xda,0x6b,0x14,0x24,0xab,0x4e,0x23,0x1f,0x8e,0x9d,
+  0x64,0x15,0xac,0x4b,0x8b,0x38,0x31,0x1a,0x9a,0x85,0x6b,0xda,0x95,0xaa,0xd7,0xb6,
+  0x63,0xd9,0x67,0x48,0xea,0x21,0x1f,0xbd,0x60,0xd6,0x4c,0x99,0x71,0xa3,0x60,0xd4,
+  0x5d,0xdb,0xce,0x56,0x77,0x4d,0x4b,0xeb,0x4f,0x86,0x15,0xb4,0x87,0x76,0x42,0xa7,
+  0x32,0x57,0x2a,0x68,0x23,0x5a,0xa1,0xb4,0xd7,0x6c,0xa7,0xf5,0x73,0x12,0x99,0xac,
+  0x7b,0x5e,0xfb,0x7e,0x66,0x9d,0xc4,0xfe,0x3e,0xda,0x40,0xee,0xfd,0x06,0xe0,0x7b,
+  0x50,0xda,0x6b,0x5a,0x8c,0xfe,0x27,0x34,0x14,0x52,0xaa,0x1a,0x05,0xc9,0xea,0x0b,
+  0x11,0x58,0x0c,0x96,0x7d,0x6f,0x6d,0x14,0xec,0x93,0xab,0x3d,0x06,0x72,0xcf,0xb3,
+  0xff,0xd1,0x33,0x89,0xf2,0x41,0x18,0xc8,0xfd,0x4b,0x2f,0x18,0xbe,0xf6,0xbf,0x76,
+  0xd5,0xd5,0x5d,0xfb,0x33,0xb7,0xfb,0xdf,0x6c,0xf6,0x1f,0xb8,0xea,0x27,0x26,0x26,
+  0xd4,0x49,0x85,0xff,0x37,0xeb,0x72,0x36,0x2f,0x91,0xff,0xf3,0x36,0xff,0x49,0xed,
+  0xa6,0xda,0xae,0x35,0xb7,0xff,0x97,0x6c,0xde,0x6e,0xd7,0xd6,0x26,0xfc,0xbf,0x6c,
+  0xf3,0x80,0xa6,0xae,0xbd,0xdf,0x54,0x9b,0xff,0x17,0xdb,0xc1,0x27,0xbc,0x9f,0xed,
+  0xfa,0x17,0xde,0x1c,0x98,0xcd,0xc3,0x35,0xd7,0xa7,0x36,0xff,0x1f,0xa8,0xfb,0x97,
+  0x2f,0xf6,0xb7,0x1c,0x89,0xf6,0xff,0x45,0xbf,0xfd,0xf7,0xb6,0xf9,0xf4,0xfa,0xf4,
+  0xfa,0xf4,0xfa,0xf4,0xfa,0xf4,0xfa,0xf4,0xfa,0xff,0xe5,0xd2,0xf6,0x49,0xa2,0xed,
+  0x93,0xea,0x7f,0x76,0x5f,0x3e,0xbd,0x3e,0xbd,0x3e,0xbd,0x3e,0xbd,0x3e,0xbd,0x3e,
+  0xbd,0xfe,0x33,0xae,0x20,0xfb,0x73,0x09,0x50,0xf9,0x6b,0xe3,0xef,0xff,0xf3,0x41,
+  0x50,0xa6,0xfd,0xeb,0xbf,0xaf,0xfd,0x9e,0x23,0x08,0x69,0xce,0x6a,0xbf,0x3b,0x35,
+  0xb5,0xaf,0xff,0x13,0x87,0x7b,0xf6,0xdd,0xd4,0x60,0x00,0x00,
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
new file mode 100755
index 0000000..4be4d7e
--- /dev/null
+++ b/board/esd/pci405/pci405.c
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+#include <pci.h>
+#include <405gp_pci.h>
+
+#include "pci405.h"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
+unsigned long fpga_done_state(void);
+unsigned long fpga_init_state(void);
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* predefine these here */
+#define FPGA_DONE_STATE (fpga_done_state())
+#define FPGA_INIT_STATE (fpga_init_state())
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE)
+#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12)
+
+#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT)
+#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12)
+
+
+int board_revision(void)
+{
+	unsigned long cntrl0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of PCI405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00100200;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	switch (value) {
+	case 0x00100200:
+		/* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
+		return 1;
+	case 0x00000200:
+		/* CS2==0 && IRQ5==1 -> version 1.2 */
+		return 2;
+	case 0x00000000:
+		/* CS2==0 && IRQ5==0 -> version 1.3 */
+		return 3;
+#if 0 /* not yet manufactured ! */
+	case 0x00100000:
+		/* CS2==1 && IRQ5==0 -> version 1.4 */
+		return 4;
+#endif
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+
+unsigned long fpga_done_state(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->board_type < 2) {
+		return FPGA_DONE_STATE_V11;
+	} else {
+		return FPGA_DONE_STATE_V12;
+	}
+}
+
+
+unsigned long fpga_init_state(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->board_type < 2) {
+		return FPGA_INIT_STATE_V11;
+	} else {
+		return FPGA_INIT_STATE_V12;
+	}
+}
+
+
+int board_early_init_f (void)
+{
+	unsigned long cntrl0Reg;
+
+	/*
+	 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
+	 */
+	out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
+	out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
+	out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
+	out32(GPIO0_OR, 0);                  /* pull prg low            */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+	mtdcr(uicer, 0x00000000);        /* disable all ints */
+	mtdcr(uiccr, 0x00000000);        /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF80);        /* set int polarities */
+	mtdcr(uictr, 0x10000000);        /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);       /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+
+	/*
+	 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x00008000);
+
+	/*
+	 * Setup GPIO pins (CS6+CS7 as GPIO)
+	 */
+	mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	unsigned int *ptr;
+	unsigned int *magic;
+
+	/*
+	 * On PCI-405 the environment is saved in eeprom!
+	 * FPGA can be gzip compressed (malloc) and booted this late.
+	 */
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Check if magic for pci reconfig is written
+	 */
+	magic = (unsigned int *)0x00000004;
+	if (*magic == PCI_RECONFIG_MAGIC) {
+		/*
+		 * Rewrite pci config regs (only after soft-reset with magic set)
+		 */
+		ptr = (unsigned int *)PCI_REGS_ADDR;
+		if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
+			puts("Restoring PCI Configurations Regs!\n");
+			ptr = (unsigned int *)PCI_REGS_ADDR + 1;
+			for (i=0; i<0x40; i+=4) {
+				pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
+			}
+		}
+		mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+
+		*magic = 0;      /* clear pci reconfig magic again */
+	}
+
+#if 1 /* test-only */
+	/*
+	 * Decrease PLB latency timeout and reduce priority of the PCI bridge master
+	 */
+#define PCI0_BRDGOPT1 0x4a
+	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
+/*	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60);	*/
+
+#define plb0_acr      0x87
+	/*
+	 * Enable fairness and high bus utilization
+	 */
+	mtdcr(plb0_acr, 0x98000000);
+
+#if 0 /* test-only */
+	printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
+/*	mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000);	*/
+	mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
+#endif
+/*	printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */
+#endif
+
+	free(dst);
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming PCI405");
+	} else {
+		puts (str);
+	}
+
+	gd->board_type = board_revision();
+	printf(" (Rev 1.%ld", gd->board_type);
+
+	if (gd->board_type >= 2) {
+		unsigned long cntrl0Reg;
+		unsigned long value;
+
+		/*
+		 * Setup GPIO pins (Trace/GPIO1 to GPIO)
+		 */
+		cntrl0Reg = mfdcr(cntrl0);
+		mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
+		out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000);
+		out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000);
+		udelay(1000);                   /* wait some time before reading input */
+		value = in32(GPIO0_IR) & 0x40000000;       /* get config bits */
+		if (value) {
+			puts(", 33 MHz PCI");
+		} else {
+			puts(", 66 Mhz PCI");
+		}
+	}
+
+	puts(")\n");
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+#if 0 /* test-only: all PCI405 version must report 16mb */
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+#else
+	return (16*1024*1024);
+#endif
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+int wpeeprom(int wp)
+{
+	int wp_state = wp;
+	volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404;
+
+	if (wp == 1) {
+		*uart1_mcr &= ~0x02;
+	} else if (wp == 0) {
+		*uart1_mcr |= 0x02;
+	} else {
+		if (*uart1_mcr & 0x02) {
+			wp_state = 0;
+		} else {
+			wp_state = 1;
+		}
+	}
+	return wp_state;
+}
+
+int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int wp = -1;
+	if (argc >= 2) {
+		if (argv[1][0] == '1') {
+			wp = 1;
+		} else if (argv[1][0] == '0') {
+			wp = 0;
+		}
+	}
+
+	wp = wpeeprom(wp);
+	printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
+	return 0;
+}
+
+U_BOOT_CMD(
+	wpeeprom,	2,	1,	do_wpeeprom,
+	"wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n",
+	"wpeeprom\n"
+	"    - check I2C EEPROM write protection state\n"
+	"wpeeprom 1\n"
+	"    - enable I2C EEPROM write protection\n"
+	"wpeeprom 0\n"
+	"    - disable I2C EEPROM write protection\n"
+	);
diff --git a/board/esd/pci405/pci405.h b/board/esd/pci405/pci405.h
new file mode 100755
index 0000000..c11a20f
--- /dev/null
+++ b/board/esd/pci405/pci405.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCI405_H_
+#define _PCI405_H_
+
+#define PCI_REGS_LEN    0x100
+#define PCI_REGS_ADDR   ((unsigned long)0x01000000 - PCI_REGS_LEN)
+
+#define PCI_RECONFIG_MAGIC  0x07081967
+
+#endif /* _PCI405_H_ */
diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds
new file mode 100755
index 0000000..f7a20d1
--- /dev/null
+++ b/board/esd/pci405/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S
new file mode 100755
index 0000000..9f5c35b
--- /dev/null
+++ b/board/esd/pci405/writeibm.S
@@ -0,0 +1,223 @@
+/*------------------------------------------------------------------------------+ */
+/* */
+/*       This source code has been made available to you by IBM on an AS-IS */
+/*       basis.  Anyone receiving this source is licensed under IBM */
+/*       copyrights to use it in any way he or she deems fit, including */
+/*       copying it, modifying it, compiling it, and redistributing it either */
+/*       with or without modifications.  No license under IBM patents or */
+/*       patent applications is to be implied by the copyright license. */
+/* */
+/*       Any user of this software should understand that IBM cannot provide */
+/*       technical support for this software and will not be responsible for */
+/*       any consequences resulting from the use of this software. */
+/* */
+/*       Any person who transfers this source code or any derivative work */
+/*       must include the IBM copyright notice, this paragraph, and the */
+/*       preceding two paragraphs in the transferred software. */
+/* */
+/*       COPYRIGHT   I B M   CORPORATION 1995 */
+/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
+/*------------------------------------------------------------------------------- */
+
+/*----------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init */
+/* Description:  Initializes the External Bus Controller for the external */
+/*		peripherals. IMPORTANT: For pass1 this code must run from */
+/*		cache since you can not reliably change a peripheral banks */
+/*		timing register (pbxap) while running code from that bank. */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so */
+/*		we run it from cache. */
+/*	Bank 0 - Flash and SRAM */
+/*	Bank 1 - NVRAM/RTC */
+/*	Bank 2 - Keyboard/Mouse controller */
+/*	Bank 3 - IR controller */
+/*	Bank 4 - not used */
+/*	Bank 5 - not used */
+/*	Bank 6 - not used */
+/*	Bank 7 - FPGA registers */
+/*----------------------------------------------------------------------------- */
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+	.globl	write_without_sync
+write_without_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start1:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id */
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+
+	b       start1
+
+	blr	/* never reached !!!! */
+
+	.globl	write_with_sync
+write_with_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start2:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id */
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+	sync
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+	sync
+
+	b       start2
+
+	blr	/* never reached !!!! */
+
+	.globl	write_with_less_sync
+write_with_less_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start2b:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id */
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+	sync
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+/*        sync */
+
+	b       start2b
+
+	blr	/* never reached !!!! */
+
+	.globl	write_with_more_sync
+write_with_more_sync:
+		/*
+		 * Write one values to host via pci busmastering
+		 * ptr = 0xc0000000 -> 0x01000000 (PCI)
+		 * *ptr = 0x01234567;
+		 */
+	addi    r31,0,0
+	lis     r31,0xc000
+
+start3:
+	lis     r0,0x0123
+	ori     r0,r0,0x4567
+	stw     r0,0(r31)
+	sync
+
+		/*
+		 * Read one value back
+		 * ptr = (volatile unsigned long *)addr;
+		 * val = *ptr;
+		 */
+
+	lwz     r0,0(r31)
+	sync
+
+		/*
+		 * One pci config write
+		 * ibmPciConfigWrite(0x2e, 2, 0x1234);
+		 */
+		/* subsystem id (PCIC0_SBSYSVID)*/
+
+	li      r4,0x002C
+	oris    r4,r4,0x8000
+	lis     r3,0xEEC0
+	stwbrx  r4,0,r3
+	sync
+
+	li      r5,0x1234
+	ori     r3,r3,0x4
+	stwbrx  r5,0,r3
+	sync
+
+	b       start3
+
+	blr	/* never reached !!!! */
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
new file mode 100755
index 0000000..603bbe2
--- /dev/null
+++ b/board/esd/pf5200/Makefile
@@ -0,0 +1,53 @@
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+# CPLD  = ../common/xilinx_jtag/lenval.o \
+# 	  ../common/xilinx_jtag/micro.o \
+# 	  ../common/xilinx_jtag/ports.o
+
+# OBJS	= $(BOARD).o flash.o $(CPLD)
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/esd/pf5200/config.mk b/board/esd/pf5200/config.mk
new file mode 100755
index 0000000..07b5de1
--- /dev/null
+++ b/board/esd/pf5200/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFF000000   boot low for 16 MiB boards
+#	0xFF800000   boot low for  8 MiB boards
+#	0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c
new file mode 100755
index 0000000..53afbc0
--- /dev/null
+++ b/board/esd/pf5200/flash.c
@@ -0,0 +1,461 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FLASH_ID_MASK           0x00FF
+
+#define FPW                     FLASH_PORT_WIDTH
+#define FPWV                    FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1            0x0555
+#define FLASH_CYCLE2            0x0aaa
+#define FLASH_ID1               0x00
+#define FLASH_ID2               0x01
+#define FLASH_ID3               0x0E
+#define FLASH_ID4               0x0F
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_reset(flash_info_t * info);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	int i = 0;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(uint, ulong, ulong);
+
+	ulong flashbase = CFG_FLASH_BASE;
+
+	flash_preinit();
+
+	/* There is only ONE FLASH device */
+	memset(&flash_info[i], 0, sizeof(flash_info_t));
+	flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
+	size += flash_info[i].size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE + monitor_flash_len - 1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef  CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t * info) {
+	FPWV *base = (FPWV *) (info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base) {
+	int i;
+	flash_info_t *info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		info = &flash_info[i];
+		if ((info->size) && (info->start[0] <= base)
+		    && (base <= info->start[0] + info->size - 1)) {
+			break;
+		}
+	}
+	return (i == CFG_MAX_FLASH_BANKS ? 0 : info);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info(flash_info_t * info) {
+	int i;
+	char *fmt;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV256U:
+		fmt = "29LV256M (256 Mbit)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf(fmt);
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+	       info->sector_count);
+	printf("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		ulong size;
+		int erased;
+		ulong *flash = (unsigned long *)info->start[i];
+
+		if ((i % 5) == 0) {
+			printf("\n   ");
+		}
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size =
+		    (i !=
+		     (info->sector_count - 1)) ? (info->start[i + 1] -
+						  info->start[i]) >> 2 : (info->
+									  start
+									  [0] +
+									  info->
+									  size -
+									  info->
+									  start
+									  [i])
+		    >> 2;
+
+		for (flash = (unsigned long *)info->start[i], erased = 1;
+		     (flash != (unsigned long *)info->start[i] + size)
+		     && erased; flash++) {
+			erased = *flash == ~0x0UL;
+		}
+		printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
+		       info->protect[i] ? "(RO)" : "    ");
+	}
+
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size(FPWV * addr, flash_info_t * info) {
+	int i;
+
+	/* Write auto select command: read Manufacturer ID                     */
+	/* Write auto select command sequence and test FLASH answer            */
+	addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW) 0x00900090;	/* selects Intel or AMD        */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.         */
+	/* This works for any bus width and any FLASH device width.            */
+	udelay(100);
+	switch (addr[FLASH_ID1] & 0x00ff) {
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus.     */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch ((FPW) addr[FLASH_ID2]) {
+		case (FPW) AMD_ID_MIRROR:
+			/* MIRROR BIT FLASH, read more ID bytes */
+			if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
+			    && (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
+				/* attention: only the first 16 MB will be used in u-boot */
+				info->flash_id += FLASH_AMLV256U;
+				info->sector_count = 512;
+				info->size = 0x02000000;
+				for (i = 0; i < info->sector_count; i++) {
+					info->start[i] =
+					    (ulong) addr + 0x10000 * i;
+				}
+				break;
+			}
+			/* fall thru to here ! */
+		default:
+			printf("unknown AMD device=%x %x %x",
+			       (FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
+			       (FPW) addr[FLASH_ID4]);
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0x800000;
+			break;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+	}
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last) {
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV256U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	last = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+		if (info->protect[sect] != 0) {	/* protected, skip it */
+			continue;
+		}
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *) (info->start[sect]);
+		if (intel) {
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;	/* first address in bank */
+
+			base = (FPWV *) (info->start[0]);
+			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+			*addr = (FPW) 0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel. */
+		/* Let's wait 1 ms.                            */
+		udelay(1000);
+
+		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf("Timeout\n");
+				if (intel) {
+					/* suspend erase        */
+					*addr = (FPW) 0x00B000B0;
+				}
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;	/* failed */
+				break;
+			}
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {
+				/* every second */
+				putc('.');
+				last = get_timer(0);
+			}
+		}
+		/* show that we're waiting */
+		if ((get_timer(last)) > CFG_HZ) {
+			/* every second */
+			putc('.');
+			last = get_timer(0);
+		}
+		flash_reset(info);	/* reset to read mode */
+	}
+	printf(" done\n");
+	return (rcode);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;		/* number of bytes to program in current word         */
+	int left;		/* number of bytes left to program                    */
+	int i, res;
+
+	for (left = cnt, res = 0;
+	     left > 0 && res == 0;
+	     addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *) addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *) addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+	FPWV *base;		/* first address in flash bank  */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+	return (res);
+}
diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h
new file mode 100755
index 0000000..22d0a55
--- /dev/null
+++ b/board/esd/pf5200/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1	/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
new file mode 100755
index 0000000..2b47012
--- /dev/null
+++ b/board/esd/pf5200/pf5200.c
@@ -0,0 +1,370 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * pf5200.c - main board support/init for the esd pf5200.
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <command.h>
+
+#include "mt46v16m16-75.h"
+
+void init_power_switch(void);
+
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register: extended mode */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL =
+	    SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+long int initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* set tap delay */
+	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+	} else {
+#if 0
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0;	/* disabled */
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;	/* 2G */
+#else
+		*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
+		    0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
+		/* let SDRAM CS1 start right after CS0 */
+		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e;	/* 2G */
+#endif
+	}
+
+#if 0
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(1);
+	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	sdram_start(0);
+#endif
+	/* set SDRAM CS1 size according to the amount of RAM found */
+
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;	/* disabled */
+
+	init_power_switch();
+	return (dramsize);
+}
+
+int checkboard(void)
+{
+	puts("Board: esd ParaFinder (pf5200)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1;	/* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x02000000) {
+		/* adjust mapping */
+		*(vu_long *) MPC5XXX_BOOTCS_START =
+		    *(vu_long *) MPC5XXX_CS0_START =
+		    START_REG(CFG_BOOTCS_START | size);
+		*(vu_long *) MPC5XXX_BOOTCS_STOP =
+		    *(vu_long *) MPC5XXX_CS0_STOP =
+		    STOP_REG(CFG_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void
+    ) {
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+}
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+	}
+}
+#endif				/* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#define MPC5XXX_SIMPLEIO_GPIO_ENABLE       (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_SIMPLEIO_GPIO_DIR          (MPC5XXX_GPIO + 0x000C)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT  (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT   (MPC5XXX_GPIO + 0x0014)
+
+#define MPC5XXX_INTERRUPT_GPIO_ENABLE      (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_INTERRUPT_GPIO_DIR         (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_INTERRUPT_GPIO_STATUS      (MPC5XXX_GPIO + 0x003C)
+
+#define GPIO_WU6	0x40000000UL
+#define GPIO_USB0       0x00010000UL
+#define GPIO_USB9       0x08000000UL
+#define GPIO_USB9S      0x00080000UL
+
+void init_power_switch(void)
+{
+	debug("init_power_switch\n");
+
+	/* Configure GPIO_WU6 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
+	*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
+	__asm__ volatile ("sync");
+
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
+	__asm__ volatile ("sync");
+
+	if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
+		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
+		__asm__ volatile ("sync");
+	}
+	*(vu_char *) CFG_CS1_START = 0x02;	/* Red Power LED on */
+	__asm__ volatile ("sync");
+
+	*(vu_char *) (CFG_CS1_START + 1) = 0x02;	/* Disable driver for KB11 */
+	__asm__ volatile ("sync");
+}
+
+void power_set_reset(int power)
+{
+	debug("ide_set_reset(%d)\n", power);
+
+	if (power) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_WU6;
+		*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6;
+		if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) ==
+		    0) {
+			*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |=
+			    GPIO_USB0;
+		}
+
+	}
+}
+
+int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	power_set_reset(1);
+	return (0);
+}
+
+U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "poweroff- Switch off power\n", NULL);
+
+int phypower(int flag)
+{
+	u32 addr;
+	vu_long *reg;
+	int status;
+	pci_dev_t dev;
+
+	dev = PCI_BDF(0, 0x18, 0);
+	status = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &addr);
+	if (status == 0) {
+		reg = (vu_long *) (addr + 0x00000040);
+		*reg |= 0x40000000;
+		__asm__ volatile ("sync");
+
+		reg = (vu_long *) (addr + 0x001000c);
+		*reg |= 0x20000000;
+		__asm__ volatile ("sync");
+
+		reg = (vu_long *) (addr + 0x0010004);
+		if (flag != 0) {
+			*reg &= ~0x20000000;
+		} else {
+			*reg |= 0x20000000;
+		}
+		__asm__ volatile ("sync");
+	}
+	return (status);
+}
+
+int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int status;
+
+	if (argv[1][0] == '0') {
+		status = phypower(0);
+	} else {
+		status = phypower(1);
+	}
+	return (0);
+}
+
+U_BOOT_CMD(phypower, 2, 2, do_phypower,
+	   "phypower- Switch power of ethernet phy\n", NULL);
+
+int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int addr;
+	unsigned int size;
+	int i;
+	volatile unsigned long *ptr;
+
+	addr = simple_strtol(argv[1], NULL, 16);
+	size = simple_strtol(argv[2], NULL, 16);
+
+	printf("\nWriting at addr %08x, size %08x.\n", addr, size);
+
+	while (1) {
+		ptr = (volatile unsigned long *)addr;
+		for (i = 0; i < (size >> 2); i++) {
+			*ptr++ = i;
+		}
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+		putc('.');
+	}
+	return 0;
+}
+
+U_BOOT_CMD(writepci, 3, 1, do_writepci,
+	   "writepci- Write some data to pcibus\n",
+	   "<addr> <size>\n" "        - Write some data to pcibus.\n");
diff --git a/board/esd/pf5200/u-boot.lds b/board/esd/pf5200/u-boot.lds
new file mode 100755
index 0000000..f23432e
--- /dev/null
+++ b/board/esd/pf5200/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile
new file mode 100755
index 0000000..9340a32
--- /dev/null
+++ b/board/esd/plu405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk
new file mode 100755
index 0000000..25b2105
--- /dev/null
+++ b/board/esd/plu405/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd PLU405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x00FC0000
diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/plu405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c
new file mode 100755
index 0000000..f6656c1
--- /dev/null
+++ b/board/esd/plu405/fpgadata.c
@@ -0,0 +1,1160 @@
+  0x1f,0x8b,0x08,0x08,0x9d,0x76,0x5c,0x3f,0x00,0x03,0x70,0x6c,0x75,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0x94,0x9b,0x7f,0x6c,0x1d,0x55,
+  0x76,0xc7,0xcf,0xfc,0xb0,0x3d,0xf6,0x7b,0xf1,0x9b,0x24,0x76,0xeb,0x6e,0x82,0x33,
+  0xfe,0x41,0xf4,0x48,0x9f,0x5f,0x5e,0x9c,0x1f,0x18,0x63,0xec,0x89,0x13,0xed,0x5a,
+  0x4b,0xda,0x58,0x2a,0xad,0x56,0x15,0x62,0x0d,0x9b,0xad,0xa2,0xca,0x44,0xa6,0xdb,
+  0x56,0x51,0xba,0x0d,0xd7,0x71,0x20,0x06,0x7b,0x89,0xa1,0x48,0x04,0x9a,0xd2,0x17,
+  0x88,0x84,0x05,0xd6,0xea,0xe5,0x47,0x89,0x21,0x29,0x4c,0x8c,0x81,0x07,0x4d,0x83,
+  0x9b,0xa0,0x2a,0x1b,0x68,0x78,0x50,0x2f,0x98,0x10,0xb2,0xce,0x8f,0x06,0x93,0x38,
+  0x71,0xef,0x9d,0x99,0x7b,0xe7,0xce,0xaf,0x67,0xaf,0xf7,0x8f,0x3d,0x99,0x77,0x35,
+  0xdc,0x73,0xde,0x9d,0x73,0x3e,0xf3,0x3d,0xe7,0x41,0x71,0x6c,0xd2,0xfa,0x1f,0x80,
+  0xf0,0x20,0xa8,0x5d,0x9d,0x7f,0xb7,0x2a,0xb5,0xfa,0xa7,0x2b,0x7e,0x9a,0x4a,0x25,
+  0xb7,0xfc,0x6c,0x13,0x3c,0x04,0x91,0xfa,0x5f,0xac,0x4e,0xfd,0xfc,0x6f,0x1f,0x59,
+  0xb1,0x6a,0x15,0xfc,0x0c,0xff,0x2b,0x95,0x5a,0xb9,0x3c,0x75,0xd7,0xf2,0x54,0x03,
+  0x6c,0x82,0xe2,0x15,0xab,0x1a,0x57,0xae,0x68,0xac,0x5f,0x05,0x3f,0x07,0x61,0xe5,
+  0xfe,0x19,0xfc,0xf7,0xea,0xf3,0x7f,0xfe,0x57,0x29,0x40,0x02,0x00,0x14,0xa5,0x84,
+  0x0e,0xf2,0xff,0x91,0x94,0xa0,0x09,0x80,0x5a,0xea,0x52,0x60,0x90,0x7f,0x83,0xfd,
+  0x79,0x71,0x0a,0x34,0xfe,0xdf,0x42,0x0a,0x74,0x68,0x07,0xbd,0x1f,0x16,0xa8,0x30,
+  0xeb,0x9f,0xa0,0xcb,0x88,0xda,0xbf,0xe7,0xfa,0x99,0x0f,0x51,0xe8,0x32,0xe7,0xaf,
+  0xe5,0x72,0x9a,0x9a,0x62,0x6a,0x2e,0xf7,0x07,0x76,0xff,0xb3,0x73,0xba,0xff,0x35,
+  0x7a,0xff,0xdf,0x77,0x3d,0x2c,0x98,0xc3,0x72,0x00,0x99,0xed,0xc7,0x0a,0x8f,0x0c,
+  0x78,0x87,0x1d,0xa0,0x42,0x21,0x08,0xc4,0xa8,0x00,0xd1,0x75,0xff,0x51,0xba,0xfe,
+  0x78,0xc1,0x2d,0x98,0x41,0x2d,0xe3,0xa5,0x5b,0xa5,0x2d,0xea,0x0d,0xf4,0x07,0xb9,
+  0xd8,0x94,0x84,0xaf,0xec,0x6c,0xb1,0x8c,0xcf,0x90,0x69,0x4c,0xca,0x5d,0xf6,0xfa,
+  0x91,0x8a,0x8b,0x70,0x14,0x25,0x0d,0x65,0x8f,0x98,0x94,0xb1,0xf1,0x79,0xdf,0xb0,
+  0x68,0x5e,0xc9,0x45,0x1c,0x43,0xca,0xc8,0x34,0x8a,0x59,0xe8,0x87,0x43,0x10,0xcf,
+  0xfe,0x20,0x25,0x9e,0xc0,0x46,0xad,0xb1,0xc8,0x32,0x12,0x46,0x84,0x18,0xff,0x64,
+  0x19,0x97,0x05,0x7a,0x7f,0x03,0x86,0xe0,0x28,0xbe,0xa8,0x0c,0x8b,0xc4,0x48,0x1a,
+  0x91,0x8c,0x78,0xc1,0x6d,0xf4,0x65,0x60,0x12,0xbb,0x64,0xfd,0xad,0x2d,0xbf,0x00,
+  0x37,0xa0,0xd1,0x28,0xcd,0x48,0xc4,0x58,0x63,0xc4,0x2c,0xa3,0xd9,0x32,0x3e,0xb1,
+  0x8c,0x31,0xa0,0xf7,0x4f,0x0b,0xc7,0x60,0x06,0x5a,0x8c,0xd8,0xa4,0xf4,0x4b,0x6a,
+  0x4c,0xfb,0x8c,0x41,0x76,0x7f,0x43,0x1d,0x32,0xef,0x16,0x7d,0x53,0x4a,0x10,0xe3,
+  0x38,0x7f,0x5b,0xfa,0x1f,0x5a,0x78,0x15,0x34,0xba,0xbe,0x20,0x61,0x6e,0x52,0x59,
+  0x05,0x09,0xf8,0x46,0xb4,0xb7,0x7d,0xb7,0xc7,0x91,0xcb,0xf8,0xf4,0xdb,0xeb,0xe5,
+  0x0d,0x66,0x34,0x8a,0xcb,0xc4,0xa8,0x2f,0x2c,0x2c,0x50,0x53,0x72,0xbb,0xbd,0x7e,
+  0x4a,0x7d,0x00,0x8e,0xa0,0xba,0x5c,0xf1,0x4f,0xc4,0x4a,0x78,0x05,0xd5,0x4d,0x44,
+  0xb6,0x8a,0xe7,0x10,0xb9,0x42,0x0c,0xb0,0x8d,0x5b,0xec,0xfe,0x6d,0xca,0x06,0xb8,
+  0x82,0x37,0x39,0x4f,0x95,0x4a,0x8d,0x2b,0xdd,0x4d,0x13,0xb1,0x54,0xcd,0x49,0x38,
+  0x0d,0x4d,0x46,0x2c,0x25,0x9d,0xc0,0x1f,0x35,0x8d,0x62,0xe3,0x14,0x3b,0x1d,0x7a,
+  0xf9,0x31,0x99,0x04,0x21,0x99,0x21,0xd1,0x50,0x5b,0x46,0x63,0x97,0x2c,0xc3,0x15,
+  0x9f,0xb1,0x42,0x1a,0x1f,0x45,0xb6,0xe2,0x13,0x1b,0xa8,0x21,0xd1,0x48,0x7a,0xe2,
+  0x6f,0x1b,0xe7,0x59,0xfc,0x4f,0x54,0xec,0x85,0x23,0x50,0x67,0x44,0xba,0xc4,0x4f,
+  0x4d,0xa3,0x94,0x1a,0x11,0xce,0xb8,0x2c,0xd3,0xfb,0x6b,0xf0,0x22,0x76,0xea,0xe1,
+  0x5c,0xe4,0x27,0xe2,0x39,0x81,0x78,0xd7,0xc7,0xb9,0xc9,0x8c,0x1c,0x8b,0x7f,0xa7,
+  0xdc,0x6f,0x05,0x6d,0x58,0x3c,0x21,0x10,0xe3,0x07,0xae,0xf3,0x66,0x1b,0xa7,0xd8,
+  0xf9,0x9c,0x28,0x9f,0x80,0xeb,0xd0,0x8c,0x62,0x83,0x3d,0xb6,0x91,0x96,0x88,0xb1,
+  0x9d,0x1a,0xe6,0x95,0xeb,0x6c,0x3f,0x6d,0x42,0x1a,0xa6,0xa0,0x19,0x62,0x48,0xca,
+  0x99,0x46,0x29,0x31,0x86,0xf9,0x2b,0xd8,0x38,0x05,0xf4,0xfe,0x8a,0xba,0x1f,0xbe,
+  0x87,0x66,0x3d,0x36,0x20,0x6d,0xb2,0x8d,0x75,0xe3,0xf4,0x0a,0x33,0x46,0xd8,0x7e,
+  0x10,0x4e,0xb5,0x6f,0x40,0x52,0x8f,0xec,0x91,0x6c,0x63,0x40,0x1c,0x17,0xa8,0x61,
+  0x5e,0x29,0x1d,0xc0,0xfe,0xd2,0x2c,0xd8,0x50,0x50,0x6b,0x2d,0x7b,0x46,0xac,0x65,
+  0xeb,0x65,0xd7,0x7a,0x6c,0xbc,0xc7,0xce,0x83,0x56,0x26,0xc3,0x01,0x48,0xb4,0xf7,
+  0x0d,0x2c,0x58,0x4f,0x0c,0x3d,0xa2,0x8a,0xa3,0x6e,0xa3,0x44,0x15,0x47,0x04,0x7a,
+  0x1e,0xb6,0xce,0xeb,0xa0,0x4e,0x69,0x8e,0xe3,0x5e,0x7f,0x4f,0x4a,0xf4,0x7c,0xee,
+  0x29,0xb7,0x9d,0x1a,0xb3,0xbd,0xdb,0x8d,0xdd,0x94,0x5d,0xfe,0x96,0x0e,0x48,0x5f,
+  0x16,0xd2,0xf3,0x50,0x51,0x60,0x5d,0x5c,0x32,0x56,0x53,0xeb,0x0b,0x0b,0x33,0xde,
+  0x63,0xe7,0xa7,0x41,0xc9,0xc9,0xc3,0x90,0x54,0x22,0x48,0xd4,0xcc,0x6d,0x60,0x83,
+  0xec,0x27,0xe9,0x32,0x4e,0xb2,0x78,0xb6,0x95,0xef,0x24,0x4e,0xb5,0x46,0xd4,0xc2,
+  0x9d,0xca,0x01,0xa1,0xd3,0x76,0x53,0x20,0xfe,0x16,0x32,0xc7,0x4f,0xb1,0xfc,0xb3,
+  0x47,0xde,0x6f,0x06,0x6d,0xd1,0x40,0x09,0x31,0x96,0xb9,0xc2,0xe8,0xc4,0x93,0x9d,
+  0x87,0xb4,0xed,0x6f,0x44,0x95,0xc8,0x17,0x9d,0x0c,0xde,0xff,0x04,0xcb,0x9f,0x59,
+  0xc1,0x3a,0x0f,0xbb,0x9f,0xe9,0xc1,0xe7,0x41,0x60,0xcb,0xb6,0xbb,0xd6,0x5f,0x67,
+  0xf9,0x47,0x51,0xed,0xf3,0xd6,0x2d,0x79,0x0e,0x1e,0x6f,0x7c,0x28,0xd3,0xf3,0x1f,
+  0x2f,0x88,0xc3,0x9b,0x90,0x44,0xf7,0x8e,0x8b,0x13,0xc4,0xe8,0x8e,0xa4,0xc5,0x09,
+  0xf9,0x4d,0xd8,0x82,0xee,0x4d,0x5b,0x57,0x50,0x24,0x2d,0x3d,0xc9,0xce,0x43,0xdc,
+  0xce,0x3f,0x8b,0x34,0xb5,0x5f,0xf5,0x3e,0x26,0xcc,0xf8,0x10,0xe8,0xf7,0x8b,0xe0,
+  0x7e,0xf2,0x90,0x9e,0x88,0x74,0x04,0x3c,0xb6,0xcc,0x18,0x64,0xf7,0xef,0x45,0x0f,
+  0xa8,0xdf,0xa1,0x7b,0x72,0xb1,0xcd,0xd2,0x8b,0x60,0x1a,0x5b,0xa5,0x73,0xd8,0xa8,
+  0xa3,0x86,0x79,0xe5,0x3c,0xcb,0x3f,0x4a,0xb9,0x9d,0x4f,0xd2,0x5c,0x1a,0x91,0xbd,
+  0xf9,0x64,0x84,0xe5,0x1f,0x90,0xdf,0x22,0xf5,0xeb,0x6a,0xec,0x6b,0x69,0x3b,0x31,
+  0x72,0xa5,0x66,0xfd,0x1a,0xb0,0xeb,0xd7,0x8c,0x55,0xbf,0x0c,0x76,0x7e,0x06,0x2b,
+  0xf6,0xea,0x78,0x93,0x13,0x91,0x6d,0xe2,0x62,0xba,0xdb,0x93,0xbd,0xde,0xfd,0x9f,
+  0x67,0xdf,0x2f,0x20,0x3b,0x5f,0xe9,0xa2,0xe9,0xb8,0x51,0x82,0x97,0xa1,0x23,0xf0,
+  0xb0,0x6b,0xbd,0xc1,0xf2,0x8f,0x46,0xf3,0x8f,0xca,0xe7,0x73,0xaf,0x91,0x65,0xe7,
+  0x73,0xd0,0xf4,0x17,0x27,0xd5,0x5e,0xa9,0xd3,0xf4,0xae,0x34,0x30,0x7f,0xb2,0xfd,
+  0x20,0xc1,0xbe,0x38,0x58,0x94,0xf0,0x2d,0x63,0x46,0x8e,0xe5,0x9f,0x2a,0xf5,0x98,
+  0x62,0x26,0x6d,0x63,0xdd,0x2f,0xe1,0x77,0xb4,0xcc,0x7d,0xe6,0xa9,0x77,0x68,0x3d,
+  0x5d,0xbf,0x4f,0xee,0xb4,0x8a,0x54,0x5c,0x4c,0xd8,0xf9,0xdc,0x5b,0x7f,0xb1,0xe1,
+  0xe4,0x1f,0x24,0x58,0xf5,0x2e,0xd2,0xdb,0x9a,0x08,0xa9,0xd7,0xd8,0x48,0xb3,0xf3,
+  0xa0,0x94,0x99,0x61,0xc9,0x46,0x32,0x49,0x6c,0xa8,0x89,0xb1,0x7b,0x53,0xe2,0x7f,
+  0x22,0x6f,0x7c,0x9c,0xfc,0x03,0xbf,0x22,0xfb,0x69,0xc9,0xe2,0x43,0xfe,0x30,0x7c,
+  0xa3,0x37,0x8f,0x11,0x37,0x91,0xa7,0xfe,0x4a,0x88,0xe5,0x9f,0x74,0xf9,0x34,0x3c,
+  0x0a,0x78,0xd9,0x7c,0xe9,0x98,0x46,0xfc,0x2d,0x9d,0x94,0xbe,0x45,0xde,0xfa,0x3e,
+  0x21,0x32,0xde,0x30,0xf9,0xa7,0x39,0x17,0xfb,0xa2,0xa7,0x99,0x9e,0x96,0x21,0xf4,
+  0x11,0x72,0x9f,0x9f,0x49,0x76,0x7e,0x90,0x6a,0x43,0xce,0x90,0x98,0x2c,0x30,0x8d,
+  0xcc,0x43,0x33,0x7a,0x9f,0x9b,0x7f,0xc4,0x1c,0xfb,0x7e,0x95,0x82,0x13,0x8a,0xe9,
+  0x14,0xf0,0xe7,0xa1,0x47,0xf4,0xfa,0xcb,0xf6,0x53,0x6e,0x61,0x8f,0x94,0x16,0x69,
+  0x3c,0x5b,0x2f,0x88,0x7d,0x9e,0x78,0x4e,0x3a,0xe7,0xf3,0xd9,0x21,0x1a,0x04,0xb2,
+  0xde,0x34,0x86,0xe0,0x3f,0xdc,0xf1,0x11,0x0d,0x96,0x7f,0x3e,0x07,0x9b,0x7f,0xb4,
+  0x08,0x8b,0xc6,0xa7,0x3e,0xfe,0x99,0xe2,0xf8,0xc7,0x3e,0x66,0x03,0x52,0x82,0x7b,
+  0x1e,0x45,0x77,0xfc,0x27,0x59,0xfe,0xc9,0xca,0xf6,0xb6,0x9d,0xfd,0x8b,0xd3,0xbe,
+  0xf3,0xe0,0xf0,0x4f,0xae,0x80,0xe4,0x9f,0xb8,0x11,0xb9,0x23,0x2f,0xff,0xb0,0xfc,
+  0xd3,0x21,0x54,0x5a,0x45,0x7f,0x33,0xe6,0x9f,0x23,0x3b,0xb1,0xb1,0xad,0xda,0xcf,
+  0x03,0x67,0x38,0xfe,0x89,0xea,0x57,0xa0,0x21,0x17,0x83,0x48,0x14,0xd3,0xce,0x62,
+  0x23,0xd6,0x28,0x9d,0x84,0x2b,0x99,0xa6,0x1c,0xe5,0x1f,0xc3,0xcd,0x3f,0xb7,0x99,
+  0xf1,0x19,0x8d,0xe5,0x38,0xfe,0xd1,0xcd,0x2b,0x81,0xfc,0x33,0x58,0xe0,0x7f,0xfa,
+  0x2e,0xa0,0x6f,0x42,0xf9,0x27,0x3b,0xdf,0xce,0x27,0x7c,0xfe,0x4c,0x87,0xf3,0x8f,
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+  0xeb,0x29,0x1b,0xcc,0xeb,0xd7,0x65,0x61,0x3d,0x25,0x8a,0xbf,0x36,0x68,0xa1,0xc3,
+  0x0f,0x91,0xcd,0x0f,0xdd,0xfd,0x1d,0x75,0xe3,0xcd,0x94,0xa4,0x6d,0x48,0xc5,0x8f,
+  0x1a,0xe0,0x8e,0x20,0xc0,0xfd,0x5e,0xa8,0x3b,0xb2,0x99,0xec,0xd1,0xaf,0x4f,0x55,
+  0x1e,0x35,0xc0,0xad,0x26,0xa8,0x77,0x5b,0xae,0x4f,0x71,0xfb,0x7b,0xd6,0xe6,0x87,
+  0x29,0x8b,0x1f,0xae,0x31,0x69,0xe7,0x0e,0x7d,0x83,0x09,0xd8,0x57,0x89,0xc3,0xdc,
+  0xfa,0xa9,0x45,0x06,0x3f,0xa4,0xbb,0x27,0xb5,0x36,0x2b,0xd4,0x99,0xcc,0x10,0xcd,
+  0xa1,0x3f,0x53,0x6d,0x0f,0x2e,0x18,0xf6,0x47,0x61,0xfc,0xd0,0x5d,0x3f,0x73,0x29,
+  0x2d,0x4c,0xe9,0x15,0xbb,0xe1,0x47,0x14,0x5c,0x43,0xf9,0x21,0x62,0x44,0x51,0xb6,
+  0x41,0x8a,0x01,0xb7,0x3f,0xe5,0xf3,0x78,0x2b,0xaa,0x81,0x8e,0x41,0x18,0xce,0x2f,
+  0x41,0xb3,0xa1,0x83,0xc4,0xc7,0x69,0xcb,0x6c,0xb8,0x83,0x03,0xdc,0x7a,0x46,0xab,
+  0x41,0x67,0xfc,0x70,0x25,0xec,0x24,0x2a,0xb9,0x3a,0x1d,0x61,0xb4,0xb0,0x9f,0xd1,
+  0xc2,0x1e,0xb4,0xd3,0x26,0x8a,0xdc,0x78,0xe8,0xfa,0x51,0x73,0xa9,0x66,0xca,0x0f,
+  0xb7,0xb3,0x65,0x33,0xdc,0x2d,0xf0,0x43,0x0b,0xf0,0xeb,0x27,0x83,0xb5,0xb7,0x12,
+  0x0b,0xba,0x64,0x25,0x82,0xb3,0x39,0x25,0xdd,0x25,0xc7,0x23,0x58,0xa3,0xcf,0x7d,
+  0xa7,0x01,0x72,0x06,0x00,0x6e,0x7e,0xa8,0x7d,0x2e,0x26,0xd2,0xf4,0xcd,0xe3,0x31,
+  0x4a,0x90,0x12,0xc3,0x28,0x86,0x3a,0x20,0x4b,0x68,0x0b,0x05,0x6a,0xb6,0x68,0x00,
+  0x8d,0x9b,0x1f,0x19,0x14,0x93,0x1f,0x82,0x46,0xdf,0x46,0x01,0x19,0xfc,0x10,0x99,
+  0x44,0x51,0xb3,0xf9,0x21,0xca,0xba,0xe3,0x69,0x8c,0x30,0x7e,0x58,0x45,0xa2,0x8d,
+  0x94,0x93,0x35,0x36,0xf0,0xfc,0xd0,0x06,0xa0,0xb8,0xf3,0xa3,0xe5,0x0d,0x23,0x13,
+  0xb5,0xec,0x8f,0x60,0x76,0x1c,0xe0,0x48,0x82,0xb4,0xff,0x60,0x3f,0x3c,0x0d,0x15,
+  0x1d,0x72,0x61,0x50,0xc7,0x4f,0xc3,0x5f,0x99,0xf6,0x47,0x66,0x66,0xa7,0xe0,0x58,
+  0x24,0x6e,0x7e,0x74,0xbc,0xc4,0xf8,0xbd,0x08,0xfb,0xbd,0x6a,0xe4,0x0e,0xa2,0x8c,
+  0xc3,0x12,0xb4,0x1d,0x18,0x30,0xbf,0x22,0x9c,0xfd,0xc9,0xd2,0x1b,0xfc,0x5a,0xb6,
+  0x66,0x6d,0xf4,0x49,0xf8,0xa1,0x99,0xe6,0x15,0xc3,0x08,0x05,0x32,0x03,0x6f,0x52,
+  0x80,0x19,0xe0,0xd6,0x33,0xe5,0x6f,0x8b,0x8a,0xd5,0xd9,0x28,0xa3,0x6d,0xf3,0xb5,
+  0x6a,0x2d,0x9a,0x80,0x51,0x4a,0x2c,0xe5,0x2c,0x05,0xbf,0xa6,0x2d,0x31,0x06,0x0e,
+  0x73,0xe3,0xe9,0x60,0xd6,0x26,0xdd,0x9d,0x82,0x87,0x0d,0x50,0x11,0x8b,0x9b,0xa0,
+  0x3b,0x16,0x7f,0xca,0x06,0xbc,0xfd,0xd1,0xa0,0x89,0x5a,0xe9,0x08,0xf6,0x9a,0x70,
+  0x11,0xb8,0xeb,0xa7,0xc7,0xe6,0x87,0xf9,0x4e,0xca,0x06,0x71,0x45,0x43,0x7c,0xa8,
+  0xd3,0xa2,0x85,0xbb,0xb1,0x8f,0x1f,0x52,0xfb,0xd3,0xb9,0x36,0x9e,0xec,0xec,0x6a,
+  0x57,0x94,0xfe,0x6c,0x3c,0x81,0x25,0x14,0xd7,0x3a,0xb3,0x4a,0x02,0x9b,0x86,0x88,
+  0xb6,0x74,0xd1,0x16,0x77,0x3c,0x98,0x2d,0x40,0x47,0x77,0x50,0x06,0xbb,0xe8,0x92,
+  0x04,0x73,0x6d,0x22,0x07,0xb8,0x8f,0x0b,0x60,0x46,0x0b,0x81,0xf2,0x43,0xa8,0x02,
+  0xc6,0x06,0xa1,0x99,0xb5,0xe4,0x18,0xe8,0x74,0x18,0x23,0x35,0x7e,0xce,0x78,0xee,
+  0x8a,0xae,0xd1,0xf2,0xc7,0x1b,0x6e,0x81,0xbb,0x22,0x75,0xda,0x09,0x0a,0xaa,0xef,
+  0x42,0x6b,0x28,0x98,0x4f,0x41,0x94,0x81,0x45,0xb7,0x70,0xf6,0x87,0xde,0xaf,0xb6,
+  0xa5,0xbd,0xbe,0x70,0x47,0x63,0xfc,0xad,0x4e,0x97,0x06,0x50,0xb0,0x81,0x02,0x70,
+  0xf8,0x80,0xbb,0xa2,0x6f,0xb4,0xf9,0xe1,0xf4,0x95,0x2b,0x19,0x3f,0xfc,0xc9,0x7d,
+  0x37,0x1a,0xfc,0x70,0xaf,0xc1,0x0f,0x7f,0xc3,0xc0,0x8a,0xff,0x69,0xdf,0xfe,0x51,
+  0x10,0x86,0xa1,0x38,0x8e,0x47,0xfc,0x83,0x83,0x9b,0xbb,0x8b,0x1e,0x20,0xce,0x1d,
+  0x2a,0x38,0xb9,0xd4,0xdd,0xbb,0x68,0x3d,0x82,0x78,0x01,0x3d,0x8d,0x17,0x10,0x5c,
+  0x45,0x70,0xd0,0xbd,0x20,0x0e,0x52,0xfb,0x5e,0x5b,0x6d,0x1d,0x0a,0xed,0xa0,0x20,
+  0xdf,0xcf,0xd2,0x10,0x92,0xf0,0x96,0xc0,0xef,0x51,0x92,0xa9,0xdf,0xb8,0x69,0x3e,
+  0x74,0xfc,0xa9,0xe4,0xc3,0xf0,0xe1,0x6a,0x30,0x0b,0xe2,0x7c,0xb8,0x0f,0x83,0x30,
+  0x97,0xc7,0xca,0xd2,0x58,0x78,0x5d,0x45,0xc7,0xde,0x93,0xa0,0x38,0xd8,0x4c,0x64,
+  0xa0,0xf9,0x50,0x67,0xe6,0xd9,0xf5,0x1a,0x0b,0x6f,0x67,0x29,0x23,0x0d,0x8a,0xbe,
+  0x0e,0xe2,0x7c,0x28,0x33,0xb9,0xbc,0xea,0xa4,0xf9,0xb0,0xdf,0xf3,0x8e,0xeb,0xa1,
+  0xac,0x5f,0x78,0xbb,0xae,0x6c,0x7c,0x45,0xcd,0xea,0xd5,0xdb,0xa8,0xc5,0x8a,0xae,
+  0x75,0xf4,0x1d,0x77,0xaa,0x9f,0x02,0x00,0x00,0x00,0xe0,0xdf,0x69,0xef,0xd0,0xa0,
+  0x77,0x00,0x00,0x00,0x00,0x50,0x4c,0x7b,0x87,0x16,0xbd,0x03,0x00,0x00,0x00,0x80,
+  0x62,0xda,0x3b,0xb4,0xb5,0x77,0xf8,0x75,0x29,0x00,0x00,0x00,0x00,0xbe,0xc8,0xca,
+  0xfb,0x38,0x73,0xb8,0x58,0xb3,0x94,0x57,0x2b,0x75,0x6b,0x46,0xa5,0xff,0x27,0x24,
+  0x7b,0x9b,0xd6,0x6c,0x6b,0xef,0x33,0x4f,0xb3,0xcf,0x75,0x4f,0xaa,0x75,0xf0,0xc5,
+  0xf1,0x33,0x01,0x00,
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
new file mode 100755
index 0000000..5b9d063
--- /dev/null
+++ b/board/esd/plu405/plu405.c
@@ -0,0 +1,294 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/*
+ * include common auto-update code (for esd boards)
+ */
+#include "../common/auto_update.h"
+
+au_image_t au_image[] = {
+	{"plu405/preinst.img", 0, -1, AU_SCRIPT},
+	{"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
+	{"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
+	{"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
+	{"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
+	{"plu405/postinst.img", 0, 0, AU_SCRIPT},
+};
+
+int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming PLU405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif
+
+
+#ifdef CONFIG_AUTO_UPDATE_SHOW
+void board_auto_update_show(int au_active)
+{
+	if (au_active) {
+		printf("\n Dies ist die board-funktion: Updating!!!\n");
+	} else {
+		printf("\n Dies ist die board-funktion: Updating done!!!\n");
+	}
+}
+#endif
diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds
new file mode 100755
index 0000000..43f7765
--- /dev/null
+++ b/board/esd/plu405/u-boot.lds
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile
new file mode 100755
index 0000000..1281be7
--- /dev/null
+++ b/board/esd/pmc405/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+OBJS	= $(BOARD).o ../common/misc.o $(CPLD)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/pmc405/config.mk b/board/esd/pmc405/config.mk
new file mode 100755
index 0000000..fc2794d
--- /dev/null
+++ b/board/esd/pmc405/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd PMC405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/pmc405/fpgadata.c b/board/esd/pmc405/fpgadata.c
new file mode 100755
index 0000000..ebdf71d
--- /dev/null
+++ b/board/esd/pmc405/fpgadata.c
@@ -0,0 +1,2472 @@
+  0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,
+  0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00,
+  0xf9,0x60,0x20,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00,
+  0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08,
+  0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
+  0x08,0xea,0x08,0x00,0x00,0x00,0x22,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x00,0x04,0x38,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x24,0x38,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x00,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x2c,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
+  0x14,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,
+  0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x03,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,0x80,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x00,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x09,0x00,0x00,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x8c,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x00,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa4,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
+  0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc0,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xcc,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x00,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
+  0x09,0x00,0x01,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x04,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x08,0x01,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x01,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,
+  0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x20,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x01,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x01,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x2c,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x01,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x44,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x01,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x50,0x00,0x03,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x01,0x80,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x01,
+  0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x01,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x8c,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x01,0xa0,0x10,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xa4,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x01,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xb0,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xc0,0x00,0x21,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x01,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xc8,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xcc,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,
+  0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,
+  0x02,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x02,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x10,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x20,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x02,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x28,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x2c,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x02,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,
+  0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x44,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x02,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x02,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x02,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x84,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x88,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x8c,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x02,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,
+  0xa0,0x00,0x81,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xa4,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x02,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x02,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xb0,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x02,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xc8,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0xd0,0x00,
+  0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x03,0x00,
+  0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
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+  0x03,0x00,0x32,0xcc,0x00,0x01,0x09,0x00,0x33,0x00,0x00,0x03,0x00,0x32,0xd0,0x00,
+  0x01,0x09,0x00,0x33,0x04,0x00,0x03,0x00,0x33,0x00,0x00,0x01,0x09,0x00,0x33,0x08,
+  0x00,0x03,0x00,0x33,0x04,0x00,0x01,0x09,0x00,0x33,0x0c,0x00,0x03,0x00,0x33,0x08,
+  0x00,0x01,0x09,0x00,0x33,0x10,0x00,0x03,0x00,0x33,0x0c,0x00,0x01,0x09,0x00,0x33,
+  0x20,0x00,0x03,0x00,0x33,0x10,0x00,0x01,0x09,0x00,0x33,0x24,0x00,0x03,0x00,0x33,
+  0x20,0x00,0x01,0x09,0x00,0x33,0x28,0x00,0x03,0x00,0x33,0x24,0x00,0x01,0x09,0x00,
+  0x33,0x2c,0x00,0x03,0x00,0x33,0x28,0x00,0x01,0x09,0x00,0x33,0x30,0x00,0x03,0x00,
+  0x33,0x2c,0x00,0x01,0x09,0x00,0x33,0x40,0x00,0x03,0x00,0x33,0x30,0x00,0x01,0x09,
+  0x00,0x33,0x44,0x00,0x03,0x00,0x33,0x40,0x00,0x01,0x09,0x00,0x33,0x48,0x00,0x03,
+  0x00,0x33,0x44,0x00,0x01,0x09,0x00,0x33,0x4c,0x00,0x03,0x00,0x33,0x48,0x00,0x01,
+  0x09,0x00,0x33,0x50,0x00,0x03,0x00,0x33,0x4c,0x00,0x01,0x09,0x00,0x33,0x80,0x00,
+  0x03,0x00,0x33,0x50,0x00,0x01,0x09,0x00,0x33,0x84,0x00,0x03,0x00,0x33,0x80,0x00,
+  0x01,0x09,0x00,0x33,0x88,0x00,0x03,0x00,0x33,0x84,0x00,0x01,0x09,0x00,0x33,0x8c,
+  0x00,0x03,0x00,0x33,0x88,0x00,0x01,0x09,0x00,0x33,0x90,0x00,0x03,0x00,0x33,0x8c,
+  0x00,0x01,0x09,0x00,0x33,0xa0,0x00,0x03,0x00,0x33,0x90,0x00,0x01,0x09,0x00,0x33,
+  0xa4,0x00,0x03,0x00,0x33,0xa0,0x00,0x01,0x09,0x00,0x33,0xa8,0x00,0x03,0x00,0x33,
+  0xa4,0x00,0x01,0x09,0x00,0x33,0xac,0x00,0x03,0x00,0x33,0xa8,0x00,0x01,0x09,0x00,
+  0x33,0xb0,0x00,0x03,0x00,0x33,0xac,0x00,0x01,0x09,0x00,0x33,0xc0,0x00,0x03,0x00,
+  0x33,0xb0,0x00,0x01,0x09,0x00,0x33,0xc4,0x00,0x03,0x00,0x33,0xc0,0x00,0x01,0x09,
+  0x00,0x33,0xc8,0x00,0x03,0x00,0x33,0xc4,0x00,0x01,0x09,0x00,0x33,0xcc,0x00,0x03,
+  0x00,0x33,0xc8,0x00,0x01,0x09,0x00,0x33,0xd0,0x00,0x03,0x00,0x33,0xcc,0x00,0x01,
+  0x09,0x00,0x34,0x00,0x00,0x03,0x00,0x33,0xd0,0x00,0x01,0x09,0x00,0x34,0x04,0x00,
+  0x03,0x00,0x34,0x00,0x00,0x01,0x09,0x00,0x34,0x08,0x00,0x03,0x00,0x34,0x04,0x00,
+  0x01,0x09,0x00,0x34,0x0c,0x00,0x03,0x00,0x34,0x08,0x00,0x01,0x09,0x00,0x34,0x10,
+  0x00,0x03,0x00,0x34,0x0c,0x00,0x01,0x09,0x00,0x34,0x20,0x00,0x03,0x00,0x34,0x10,
+  0x00,0x01,0x09,0x00,0x34,0x24,0x00,0x03,0x00,0x34,0x20,0x00,0x01,0x09,0x00,0x34,
+  0x28,0x00,0x03,0x00,0x34,0x24,0x00,0x01,0x09,0x00,0x34,0x2c,0x00,0x03,0x00,0x34,
+  0x28,0x00,0x01,0x09,0x00,0x34,0x30,0x00,0x03,0x00,0x34,0x2c,0x00,0x01,0x09,0x00,
+  0x34,0x40,0x00,0x03,0x00,0x34,0x30,0x00,0x01,0x09,0x00,0x34,0x44,0x00,0x03,0x00,
+  0x34,0x40,0x00,0x01,0x09,0x00,0x34,0x48,0x00,0x03,0x00,0x34,0x44,0x00,0x01,0x09,
+  0x00,0x34,0x4c,0x00,0x03,0x00,0x34,0x48,0x00,0x01,0x09,0x00,0x34,0x50,0x00,0x03,
+  0x00,0x34,0x4c,0x00,0x01,0x09,0x00,0x34,0x80,0x00,0x03,0x00,0x34,0x50,0x00,0x01,
+  0x09,0x00,0x34,0x84,0x00,0x03,0x00,0x34,0x80,0x00,0x01,0x09,0x00,0x34,0x88,0x00,
+  0x03,0x00,0x34,0x84,0x00,0x01,0x09,0x00,0x34,0x8c,0x00,0x03,0x00,0x34,0x88,0x00,
+  0x01,0x09,0x00,0x34,0x90,0x00,0x03,0x00,0x34,0x8c,0x00,0x01,0x09,0x00,0x34,0xa0,
+  0x00,0x03,0x00,0x34,0x90,0x00,0x01,0x09,0x00,0x34,0xa4,0x00,0x03,0x00,0x34,0xa0,
+  0x00,0x01,0x09,0x00,0x34,0xa8,0x00,0x03,0x00,0x34,0xa4,0x00,0x01,0x09,0x00,0x34,
+  0xac,0x00,0x03,0x00,0x34,0xa8,0x00,0x01,0x09,0x00,0x34,0xb0,0x00,0x03,0x00,0x34,
+  0xac,0x00,0x01,0x09,0x00,0x34,0xc0,0x00,0x03,0x00,0x34,0xb0,0x00,0x01,0x09,0x00,
+  0x34,0xc4,0x00,0x03,0x00,0x34,0xc0,0x00,0x01,0x09,0x00,0x34,0xc8,0x00,0x03,0x00,
+  0x34,0xc4,0x00,0x01,0x09,0x00,0x34,0xcc,0x00,0x03,0x00,0x34,0xc8,0x00,0x01,0x09,
+  0x00,0x34,0xd0,0x00,0x03,0x00,0x34,0xcc,0x00,0x01,0x09,0x00,0x35,0x00,0x00,0x03,
+  0x00,0x34,0xd0,0x00,0x01,0x09,0x00,0x35,0x04,0x00,0x03,0x00,0x35,0x00,0x00,0x01,
+  0x09,0x00,0x35,0x08,0x00,0x03,0x00,0x35,0x04,0x00,0x01,0x09,0x00,0x35,0x0c,0x00,
+  0x03,0x00,0x35,0x08,0x00,0x01,0x09,0x00,0x35,0x10,0x00,0x03,0x00,0x35,0x0c,0x00,
+  0x01,0x09,0x00,0x35,0x20,0x00,0x03,0x00,0x35,0x10,0x00,0x01,0x09,0x00,0x35,0x24,
+  0x00,0x03,0x00,0x35,0x20,0x00,0x01,0x09,0x00,0x35,0x28,0x00,0x03,0x00,0x35,0x24,
+  0x00,0x01,0x09,0x00,0x35,0x2c,0x00,0x03,0x00,0x35,0x28,0x00,0x01,0x09,0x00,0x35,
+  0x30,0x00,0x03,0x00,0x35,0x2c,0x00,0x01,0x09,0x00,0x35,0x40,0x00,0x03,0x00,0x35,
+  0x30,0x00,0x01,0x09,0x00,0x35,0x44,0x00,0x03,0x00,0x35,0x40,0x00,0x01,0x09,0x00,
+  0x35,0x48,0x00,0x03,0x00,0x35,0x44,0x00,0x01,0x09,0x00,0x35,0x4c,0x00,0x03,0x00,
+  0x35,0x48,0x00,0x01,0x09,0x00,0x35,0x50,0x00,0x03,0x00,0x35,0x4c,0x00,0x01,0x09,
+  0x00,0x35,0x80,0x00,0x03,0x00,0x35,0x50,0x00,0x01,0x09,0x00,0x35,0x84,0x00,0x03,
+  0x00,0x35,0x80,0x00,0x01,0x09,0x00,0x35,0x88,0x00,0x03,0x00,0x35,0x84,0x00,0x01,
+  0x09,0x00,0x35,0x8c,0x00,0x03,0x00,0x35,0x88,0x00,0x01,0x09,0x00,0x35,0x90,0x00,
+  0x03,0x00,0x35,0x8c,0x00,0x01,0x09,0x00,0x35,0xa0,0x00,0x03,0x00,0x35,0x90,0x00,
+  0x01,0x09,0x00,0x35,0xa4,0x00,0x03,0x00,0x35,0xa0,0x00,0x01,0x09,0x00,0x35,0xa8,
+  0x00,0x03,0x00,0x35,0xa4,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x03,0x00,0x35,0xa8,
+  0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x03,0x00,0x35,0xac,0x00,0x01,0x09,0x00,0x35,
+  0xc0,0x00,0x03,0x00,0x35,0xb0,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x03,0x00,0x35,
+  0xc0,0x00,0x01,0x09,0x00,0x35,0xc8,0x00,0x03,0x00,0x35,0xc4,0x00,0x01,0x09,0x00,
+  0x35,0xcc,0x00,0x03,0x00,0x35,0xc8,0x00,0x01,0x09,0x00,0x35,0xd0,0x00,0x03,0x00,
+  0x35,0xcc,0x00,0x01,0x09,0x00,0x35,0xd0,0x00,0x03,0x00,0x35,0xd0,0x00,0x01,0x04,
+  0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,0x00,0x64,0x02,0x08,0xf0,0x04,
+  0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x07,0x00,0x07,0x20,0x12,0x00,0x12,0x01,0x04,
+  0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,
+  0x00,0x00,
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
new file mode 100755
index 0000000..33b5f77
--- /dev/null
+++ b/board/esd/pmc405/pmc405.c
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+/* fpga configuration data - not compressed, generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+int filesize = sizeof(fpgadata);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000);
+
+	/*
+	 * Setup GPIO pins (CS6+CS7 as GPIO)
+	 */
+	mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000);
+
+	/*
+	 * Configure GPIO pins
+	 */
+	out32(GPIO0_ODR, 0x00000000);                                /* no open drain pins */
+	out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */
+	out32(GPIO0_OR, 0);                                            /* outputs -> low   */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming PMC405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+	volatile uchar *ptr;
+	volatile uchar val;
+	int i;
+
+	addr = simple_strtol (argv[1], NULL, 16) + 0x16;
+
+	i = 0;
+	for (;;) {
+		ptr = (uchar *)addr;
+		for (i=0; i<8; i++) {
+			*ptr = i;
+			val = *ptr;
+
+			if (val != i) {
+				printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val);
+				return 0;
+			}
+
+			/* Abort if ctrl-c was pressed */
+			if (ctrlc()) {
+				puts("\nAbort\n");
+				return 0;
+			}
+
+			ptr++;
+		}
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	cantest,	3,	1,	do_cantest,
+	"cantest - Test CAN controller",
+	NULL
+	);
diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds
new file mode 100755
index 0000000..e84d69e
--- /dev/null
+++ b/board/esd/pmc405/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/tasreg/Makefile b/board/esd/tasreg/Makefile
new file mode 100755
index 0000000..e5d8446
--- /dev/null
+++ b/board/esd/tasreg/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/tasreg/config.mk b/board/esd/tasreg/config.mk
new file mode 100755
index 0000000..69fd8b6
--- /dev/null
+++ b/board/esd/tasreg/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xffc00000
diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c
new file mode 100755
index 0000000..13c07d2
--- /dev/null
+++ b/board/esd/tasreg/flash.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <ppc4xx.h>*/
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* test-only: todo: Re-do sizing to get full correct info */
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_FLASH_BASE,
+			    CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/tasreg/fpgadata.c b/board/esd/tasreg/fpgadata.c
new file mode 100755
index 0000000..611b521
--- /dev/null
+++ b/board/esd/tasreg/fpgadata.c
@@ -0,0 +1,5331 @@
+  0x1f,0x8b,0x08,0x08,0x5a,0x90,0xc1,0x41,0x00,0x03,0x72,0x61,0x73,0x72,0x65,0x67,
+  0x2e,0x62,0x69,0x74,0x00,0xac,0xfd,0x7d,0x78,0x14,0xd7,0x95,0x2e,0x8a,0xaf,0xde,
+  0xd5,0x88,0x52,0x57,0x4b,0x5d,0x96,0x48,0x0e,0xb1,0x19,0x5c,0x6a,0x09,0xd2,0xe0,
+  0x96,0xd4,0x6e,0xb0,0x90,0x65,0xd1,0x2a,0x04,0x33,0xa3,0x00,0x13,0x34,0x9e,0xdc,
+  0xf3,0x78,0xe6,0xe4,0xe6,0xd7,0xf6,0x90,0x0c,0x93,0x43,0x3c,0xc4,0xf1,0x9d,0x4b,
+  0x1c,0x1f,0x67,0xab,0x5b,0x36,0x02,0x61,0xd3,0x60,0x32,0xc1,0x89,0x27,0xd3,0x7c,
+  0x24,0x66,0x6c,0x92,0x69,0x24,0x6c,0xc4,0x47,0xec,0x92,0xac,0x38,0xe2,0xc3,0xa0,
+  0x38,0x3e,0x09,0xb6,0x19,0xa7,0xf1,0xc8,0x8e,0x6c,0xcb,0xb6,0xf8,0x48,0x2c,0x21,
+  0x01,0x77,0xad,0xbd,0xab,0xba,0xab,0x05,0x73,0x7e,0x7f,0x9c,0xe3,0x3c,0x8f,0xb3,
+  0xbc,0xab,0xba,0xd4,0xbd,0x77,0xed,0xbd,0xd7,0xbb,0xdf,0xb5,0xde,0x05,0xc5,0x81,
+  0x51,0xf9,0x3f,0x00,0xcf,0xbd,0xa0,0x3d,0x70,0xef,0xb7,0x1e,0xf8,0xea,0xdf,0xd5,
+  0xdc,0xff,0xb7,0xab,0xe1,0x3e,0xd0,0xa2,0xdf,0x8a,0x46,0x22,0x5f,0xfb,0xbb,0x85,
+  0x77,0xd4,0xc1,0xdf,0xe2,0x7f,0x45,0x22,0x0b,0x6b,0x6f,0x8f,0xd6,0xde,0x5e,0x07,
+  0xab,0xa1,0xf8,0xf6,0x85,0x0d,0x0b,0x23,0x0d,0x0b,0xa3,0xf0,0x55,0x60,0x9b,0x97,
+  0x5d,0xc3,0x7f,0x9e,0x7d,0xea,0xff,0xfa,0x5a,0x04,0xb8,0x07,0x00,0xa6,0x47,0x3c,
+  0x71,0xfa,0xff,0x9b,0x22,0x1e,0xc3,0x03,0xbc,0xa9,0x3a,0x02,0x16,0xfd,0x37,0xd8,
+  0xd7,0x8b,0x23,0x60,0xb8,0xff,0xdb,0x13,0x01,0x13,0x5a,0xe1,0xa9,0x57,0xa0,0xcc,
+  0x80,0xff,0x9d,0x7f,0x3c,0xe0,0xe5,0xc2,0xf8,0x3f,0xf5,0x1c,0xf6,0xbf,0xf5,0x18,
+  0xfa,0x27,0xf5,0x7f,0xe8,0x39,0xfc,0xff,0xe8,0x73,0xca,0xff,0xb7,0x9f,0x63,0x89,
+  0x7f,0x97,0xfd,0xef,0x3e,0xc6,0xcb,0xe9,0xdf,0xd7,0xca,0xc0,0x07,0xf7,0x71,0x3d,
+  0x5d,0x14,0xf2,0xfc,0x00,0xbe,0xc6,0x3f,0x97,0x2e,0x5a,0x63,0x1b,0xde,0x35,0xee,
+  0x96,0x22,0xfe,0xb9,0xac,0x77,0x0d,0xcc,0x86,0x3f,0xe7,0x9e,0x34,0xac,0x97,0x46,
+  0xd6,0xbb,0xbe,0xa9,0x5f,0x3c,0xc7,0x9a,0x76,0x15,0x2e,0xf3,0x5a,0xcb,0xcf,0x15,
+  0x03,0x26,0x21,0x06,0x81,0xbe,0x64,0x26,0x35,0x64,0xdc,0xa5,0x96,0x0e,0x2a,0x55,
+  0xcb,0x5e,0x6f,0x6f,0xca,0x06,0x2e,0x24,0x47,0xf9,0x30,0xc4,0xfa,0xfc,0xa3,0x4a,
+  0x38,0x7d,0xda,0x88,0x0e,0xa0,0xd1,0x08,0xbd,0x6a,0xd4,0xf2,0x72,0x25,0x02,0xeb,
+  0xe8,0x39,0x5c,0xff,0x18,0x0e,0x43,0x8d,0x05,0x19,0x08,0xf3,0xbb,0x78,0xcd,0xb9,
+  0xce,0xa3,0xbe,0x9f,0x99,0xcf,0x59,0xf3,0x47,0x97,0xef,0x63,0xe1,0xc1,0x4e,0xa8,
+  0xc9,0x6a,0x93,0xec,0x63,0xe8,0xe4,0x35,0xd0,0xd2,0xce,0x0c,0xe8,0x80,0x20,0xa8,
+  0xdc,0x67,0x98,0x9b,0xcc,0x79,0x83,0x6a,0x07,0x33,0xbc,0x11,0x7a,0x4e,0xc7,0xb4,
+  0x93,0xd0,0x05,0x61,0x53,0x8d,0x30,0x30,0xba,0xf1,0x59,0x1a,0x30,0x0e,0x69,0x33,
+  0xa4,0xfb,0xb6,0x32,0x3f,0x7f,0x12,0xc2,0xd6,0x8a,0x08,0x3b,0x69,0xee,0xd6,0xc3,
+  0xd0,0xe1,0xc5,0xc1,0xe5,0x66,0xc8,0x3b,0xdf,0x43,0x06,0x18,0xfd,0xaa,0xde,0x1c,
+  0xf4,0x88,0xef,0x63,0x7d,0x66,0x1f,0x7d,0x9f,0xde,0x0e,0x68,0x0e,0xeb,0x3d,0x50,
+  0x63,0x6a,0x99,0xe0,0x3e,0x78,0x0e,0xe6,0x5b,0x2c,0xad,0x86,0x41,0x83,0x52,0x4b,
+  0xcb,0xb0,0x8f,0xa0,0x73,0x59,0x0d,0x84,0xf0,0xe3,0xad,0x1c,0x9e,0x85,0xe5,0xf4,
+  0xb6,0x74,0xc0,0xb3,0xd6,0xde,0x1d,0x2c,0xe2,0x8d,0x8b,0xee,0xfe,0xcc,0x08,0x5c,
+  0x6e,0x89,0x59,0xf8,0x45,0x42,0xc6,0x18,0xc4,0x58,0x80,0x2b,0x69,0x18,0x86,0x06,
+  0xf8,0xa2,0xbe,0xb4,0xc6,0x7c,0x0b,0x2f,0x05,0x32,0xca,0x30,0x7c,0x00,0x31,0x33,
+  0xdc,0xa3,0xd5,0xb0,0x01,0xfa,0xb3,0x19,0xa5,0xb6,0xef,0x98,0x11,0xb5,0xfc,0x9b,
+  0x14,0xf0,0x8a,0xef,0x93,0xf5,0x1c,0x55,0xaf,0x06,0x9b,0x86,0xf0,0xe6,0x4b,0x70,
+  0x0d,0x9a,0xac,0xc0,0x3a,0x65,0x12,0x8d,0xc5,0x56,0x20,0xab,0x9c,0x85,0x6b,0x56,
+  0x93,0x75,0xeb,0xa8,0x32,0x04,0x57,0xa0,0x89,0x07,0x06,0x94,0x0b,0x78,0xa9,0xce,
+  0x2a,0xe9,0x53,0x2e,0x78,0xaf,0xd2,0xcd,0x90,0x1c,0x03,0xf1,0x7d,0x4c,0x7d,0x1f,
+  0x5c,0x4e,0xff,0xa3,0x19,0xe8,0x2a,0x0f,0x15,0x9f,0x80,0x18,0xc7,0xef,0x03,0xfa,
+  0x20,0xd4,0x41,0x49,0x4a,0x09,0xc3,0x5b,0xd0,0x45,0xdf,0x67,0x99,0xe7,0x18,0x5e,
+  0xf2,0xf3,0xce,0xb4,0x72,0x02,0x70,0xbc,0x78,0x79,0x05,0xb3,0xf4,0xe8,0x40,0x4d,
+  0x87,0xa2,0x7b,0x0d,0x7a,0xce,0xc0,0xb4,0xb0,0x7a,0xc4,0xc2,0x41,0xe1,0x89,0x2a,
+  0xfc,0xc9,0xd4,0x3f,0xca,0x5a,0xe8,0x84,0xa0,0x55,0x92,0x66,0x61,0x2f,0x19,0xda,
+  0xa8,0xaf,0x0a,0x36,0xb2,0x9a,0x94,0xca,0xa7,0xc7,0xef,0xeb,0x4c,0xed,0x3a,0x53,
+  0xb2,0x91,0x55,0x40,0x47,0xeb,0xa2,0xd7,0x4a,0xb6,0xfb,0xa2,0xb8,0x00,0xd1,0xef,
+  0x9a,0xb6,0x12,0xc7,0xab,0x26,0xdd,0xe9,0x65,0x5e,0xe0,0x2c,0x6c,0xe2,0x78,0x99,
+  0xde,0x14,0xab,0x02,0x4d,0x67,0x27,0xa1,0x1b,0xd6,0x58,0x5a,0xa4,0xc8,0x0b,0x6d,
+  0x50,0x93,0x50,0xa9,0x7b,0x93,0xd6,0x5c,0x4b,0x85,0xe5,0xcd,0x09,0xce,0x83,0xe7,
+  0x7c,0xde,0xe6,0x7a,0x5c,0xc6,0xf0,0x9f,0xb8,0x67,0xb6,0xfa,0x42,0xa2,0x3a,0xad,
+  0xad,0x63,0x37,0xf3,0x0d,0xbc,0x7a,0xaf,0x76,0xe7,0xcd,0x8f,0xc0,0x16,0x6e,0x64,
+  0xb5,0x61,0xf6,0xb6,0xe7,0xdf,0xf8,0xbc,0xac,0x56,0xcf,0xfe,0x06,0x1e,0x4b,0x57,
+  0x7f,0x6d,0xe6,0x7a,0x36,0xdb,0x6a,0xf7,0xff,0xd8,0x28,0x5e,0x5f,0xf4,0x45,0x63,
+  0x0b,0x9f,0x33,0x34,0x6f,0x39,0x9b,0x29,0xbf,0x4f,0x8b,0xea,0x87,0x0b,0x89,0xf0,
+  0x6f,0x02,0x77,0x2a,0x73,0x21,0x09,0x8d,0xc3,0x01,0x50,0x4c,0x18,0x84,0x85,0x10,
+  0xd0,0x95,0x8f,0xe1,0x22,0x84,0xac,0xc0,0xed,0x8a,0x0a,0x09,0x1e,0x7b,0x30,0x7c,
+  0x20,0x51,0xdb,0xd7,0xa1,0x1f,0x30,0xfc,0x07,0x92,0x2b,0xa1,0xb7,0x2d,0x32,0x5c,
+  0x73,0xcb,0xd2,0x32,0xb9,0x60,0x98,0x7f,0x72,0x14,0x2e,0xeb,0xd8,0xf3,0x2f,0x2b,
+  0x63,0xe6,0x51,0x88,0x79,0x03,0xa3,0xda,0x59,0x98,0x80,0x98,0x55,0xb2,0x46,0x6b,
+  0x84,0xdf,0xc1,0x22,0xec,0xe7,0xf2,0x1e,0x76,0x15,0xc7,0x3d,0x70,0x5e,0x7b,0xd8,
+  0x9c,0x84,0xbb,0x60,0x7a,0x46,0xd9,0x07,0xe3,0xbc,0x69,0xb0,0x36,0xa5,0x0c,0x16,
+  0x89,0xf1,0xda,0x3b,0x6d,0x44,0x7c,0x6a,0x3a,0xc7,0xd1,0x39,0xc3,0xa3,0x71,0x3f,
+  0x28,0x69,0x75,0x0c,0x7a,0x8c,0x40,0x4a,0x0b,0x8b,0x4b,0x81,0x17,0x14,0xbc,0xc7,
+  0x13,0xf3,0xd0,0x1c,0x64,0x67,0x20,0xea,0x09,0xd3,0x64,0x1c,0x80,0x58,0xbf,0x9f,
+  0x57,0x7e,0x20,0xe7,0x57,0xcb,0x4d,0x4f,0xc3,0x41,0x6f,0xb5,0xa5,0x44,0x7c,0x50,
+  0x96,0x84,0x34,0x0f,0xad,0x63,0xb3,0x60,0x37,0x54,0x58,0x25,0x06,0x1a,0x07,0xa1,
+  0xda,0xd2,0xfe,0x31,0x31,0x08,0x07,0xd0,0x08,0x8d,0xb2,0x59,0xfa,0x06,0xbc,0xa4,
+  0xae,0x63,0x4f,0xc3,0x06,0xa8,0x1d,0x68,0x89,0xb3,0xd7,0xe4,0xfb,0x6c,0xc1,0x8f,
+  0xe0,0xf9,0x8e,0xea,0xac,0x86,0x7d,0x08,0x1b,0x78,0x45,0xb6,0x78,0x80,0xf5,0xc1,
+  0x1e,0x7e,0x9b,0xe1,0xbb,0xc7,0xf8,0x0a,0x1c,0xb4,0xc4,0xa5,0x6d,0x91,0x03,0x78,
+  0x4f,0xf1,0xfa,0xb2,0xd9,0x7a,0x12,0xef,0x51,0xeb,0xd9,0x57,0xe0,0x51,0x5e,0x9d,
+  0x55,0xef,0x61,0xa3,0x20,0xde,0x9f,0x96,0x19,0x27,0x8b,0xf7,0x2f,0x5f,0x6b,0x69,
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+  0x37,0x24,0x28,0x42,0x23,0xba,0xec,0xa1,0x1c,0x34,0xee,0x40,0x97,0xdd,0xcb,0x9d,
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+  0xa0,0x0b,0x8f,0x79,0x61,0x57,0x9b,0xd7,0xc1,0xc6,0x08,0x0e,0x5e,0x86,0xdf,0x25,
+  0x16,0xd1,0xf6,0x64,0x99,0x52,0xca,0xb1,0x30,0x51,0x14,0x49,0xd4,0x71,0x43,0x03,
+  0x50,0x4c,0x18,0x4c,0x0e,0xd8,0x86,0x85,0x97,0x93,0xcc,0xd0,0xc1,0x28,0x73,0xf0,
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+  0x26,0x25,0x73,0xb7,0xa7,0x30,0x97,0x6d,0x64,0xf3,0xc6,0xec,0x5f,0xf6,0x7a,0x19,
+  0xe2,0x32,0xf2,0x19,0x92,0x6b,0x28,0x09,0x72,0x2f,0x79,0x94,0x4c,0x02,0x9f,0x44,
+  0xac,0x20,0xd7,0xe0,0x6e,0x95,0x60,0x1b,0x66,0xae,0x71,0x1b,0xd5,0x70,0xdb,0x16,
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+  0x18,0xf8,0x2b,0xeb,0x3e,0x6c,0x86,0x97,0xe4,0x0c,0x4d,0xd1,0x00,0x0b,0xaf,0x25,
+  0x65,0x86,0x57,0x13,0x65,0xad,0x97,0xe8,0xcc,0x20,0x7d,0x06,0x26,0x0a,0x34,0x4e,
+  0x26,0xac,0x85,0x42,0x0b,0x1a,0x0a,0xb1,0x0c,0xa4,0x45,0x73,0xf6,0x1d,0x92,0x43,
+  0x6e,0x9a,0x97,0xdf,0x2c,0xb5,0x90,0xef,0xca,0x33,0x69,0x7e,0x4b,0xa3,0x66,0x34,
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+  0xc3,0x6b,0xc0,0x3f,0xfa,0xe7,0xf2,0x4d,0x80,0x04,0x1b,0x9b,0xb5,0x2f,0xc3,0x3f,
+  0x9a,0xdf,0xdc,0x58,0x42,0x9c,0x7d,0xb9,0x51,0x5e,0xd2,0x5b,0x1a,0x9a,0x3f,0x59,
+  0x58,0x85,0x1b,0x59,0xcb,0x7c,0x2f,0xdb,0xa4,0x4a,0x43,0xb9,0x60,0x10,0x34,0x9c,
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+  0x4e,0xc0,0x44,0xb4,0xd6,0x6c,0xe0,0xdc,0x00,0x3e,0x8b,0xac,0xbb,0x3d,0x14,0x14,
+  0xba,0xb3,0x06,0xf3,0x16,0x70,0x2a,0x9c,0xdf,0x25,0x44,0x9b,0x96,0x14,0x96,0xca,
+  0xf3,0x85,0xf5,0xdc,0x97,0x60,0x78,0x39,0x56,0x58,0xfa,0x00,0x62,0x61,0x0e,0x9c,
+  0x05,0x68,0x69,0x28,0x64,0x78,0x79,0xad,0x1c,0xd3,0xf0,0xdc,0x95,0xe3,0x65,0xb9,
+  0xa1,0xcc,0xf6,0xc3,0x61,0xff,0x6a,0x6a,0xd6,0x4a,0xe4,0x5b,0x73,0x60,0xdb,0x6a,
+  0x2e,0x2c,0x91,0x73,0x84,0x42,0xc3,0x40,0xe3,0x56,0x30,0x78,0x97,0xf0,0x12,0xb4,
+  0x08,0x25,0x39,0x39,0x85,0xd8,0xa5,0xe1,0x18,0x81,0xb5,0xc8,0x82,0xa0,0x19,0xf6,
+  0xf3,0xa5,0xc0,0x0a,0x94,0xc4,0x73,0xc8,0x03,0xf0,0x40,0x13,0xed,0x41,0x3c,0x2c,
+  0x0a,0x35,0x60,0x8b,0xde,0x4a,0x62,0x77,0xf0,0xa7,0x3f,0x1a,0x6b,0x60,0xa2,0x39,
+  0xec,0x11,0x2f,0x11,0x73,0x74,0x21,0xca,0x5e,0x0c,0x38,0xc6,0xfa,0x08,0x80,0x7c,
+  0x3b,0x48,0x12,0x89,0x26,0xcb,0x6c,0x2c,0x5c,0x26,0xb6,0x62,0x0b,0x82,0xe2,0x56,
+  0x6c,0x21,0x1e,0x22,0x52,0x92,0x6c,0x06,0xa3,0xd0,0x1e,0x93,0x83,0x06,0x09,0x64,
+  0xf6,0xaf,0xcf,0x03,0xf2,0x6d,0x1f,0x28,0x9b,0xb9,0x16,0x8c,0x28,0x40,0xe0,0x99,
+  0x0f,0x7c,0x5e,0xf8,0x92,0xd2,0x6e,0x96,0xcd,0xcc,0xff,0xbc,0x28,0x18,0xe6,0xc0,
+  0x55,0x21,0xe5,0xf3,0x52,0xb1,0xd1,0x07,0x5d,0xde,0xcf,0x4b,0x5f,0x6c,0x6a,0x7f,
+  0x69,0xea,0x4c,0x25,0xbf,0xf8,0x4b,0xc6,0x09,0xf8,0x2b,0x7b,0xff,0x82,0x79,0x06,
+  0x0f,0x7f,0x33,0x3a,0xff,0xfd,0xb9,0xe8,0xf3,0xff,0xad,0x0b,0x17,0xf4,0x4f,0x6a,
+  0x01,0x50,0xfc,0x39,0x5d,0xe8,0x9f,0x74,0x0f,0xb9,0x2b,0xfe,0x39,0x80,0xc9,0x62,
+  0x8b,0xb0,0x89,0xfe,0xb3,0x6b,0x8c,0x69,0xff,0xb0,0x72,0xc5,0x30,0xb5,0x50,0x3b,
+  0x7a,0x59,0x60,0xcc,0x90,0xd7,0x0a,0x88,0x97,0x11,0x0b,0x2f,0x01,0x50,0x6c,0x02,
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+  0xcf,0xbe,0x0c,0xe0,0xe5,0xcf,0x5d,0x02,0xe4,0xfb,0x9d,0x1f,0xd6,0xff,0x61,0xd1,
+  0x85,0x7f,0xbb,0x72,0xef,0x95,0x67,0xb9,0x01,0xe0,0xf1,0xfa,0x3f,0x30,0x50,0xfc,
+  0x9d,0x4b,0xf5,0x68,0x5c,0xfe,0x7f,0x0b,0x2f,0x4f,0x7a,0xfa,0xe5,0x17,0x53,0xd6,
+  0xf7,0x79,0xf7,0xde,0x5d,0xcf,0x06,0x7f,0xb5,0xe0,0x3e,0x06,0x9c,0xa7,0xfc,0x6a,
+  0x01,0x22,0xe8,0x6f,0xad,0x80,0x96,0xfb,0x0f,0xbe,0x9a,0xba,0xb0,0x22,0x62,0x61,
+  0xea,0xff,0x1b,0x8c,0xfb,0xd9,0x18,0xe7,0x3a,0x35,0x75,0x9f,0x7b,0xf1,0xdf,0x6a,
+  0xfa,0xac,0xeb,0x7c,0x78,0xef,0xf1,0x67,0x6b,0x6e,0x5e,0x78,0x81,0x01,0xe7,0xeb,
+  0x6f,0x66,0x08,0xfa,0xdb,0x67,0xa1,0xe5,0x4a,0x71,0xa4,0xef,0xe2,0xd9,0x7a,0x0b,
+  0x53,0x5f,0x02,0xe3,0x0a,0x1b,0xe3,0x5c,0x67,0xce,0x14,0xa3,0xaf,0x68,0xc6,0xa0,
+  0x57,0x98,0xd3,0xf2,0x85,0xe7,0x1e,0xd9,0x25,0x9f,0xb9,0x65,0x8e,0x16,0x7d,0x6e,
+  0xc3,0x8c,0xf6,0x77,0x47,0x25,0xed,0x0b,0x2f,0x14,0xef,0x1a,0xcc,0x1f,0x85,0xae,
+  0xd7,0x1e,0x49,0xb5,0x9f,0xf9,0xe6,0x9c,0x95,0xd1,0x57,0x8b,0x6e,0x6e,0x5f,0xfb,
+  0xcd,0x39,0xa5,0x5f,0x78,0x0d,0xc7,0x9c,0x76,0xae,0x23,0xb6,0x93,0x2d,0x24,0xf0,
+  0x8f,0x1e,0x8d,0x1b,0x86,0xdb,0x58,0x15,0xca,0xb4,0x1c,0x75,0x77,0x79,0x0f,0xda,
+  0x63,0x9c,0xcb,0xb8,0x42,0x83,0xcc,0x11,0x23,0xee,0x50,0x86,0x65,0x64,0x87,0x0f,
+  0x49,0x56,0x97,0x73,0x42,0xd6,0x8e,0xcc,0x5b,0x06,0x7b,0x29,0x4c,0x64,0x74,0xb0,
+  0x54,0x2b,0x71,0x8c,0xe1,0x74,0x11,0x6b,0xe7,0xb1,0xbe,0xc6,0x3f,0xea,0x13,0x7c,
+  0x0d,0x65,0x52,0x38,0xd3,0x72,0xd4,0xd5,0xe5,0x0e,0x70,0x3a,0xbf,0x8b,0x8e,0x3b,
+  0xf8,0x03,0xe3,0xe8,0xb8,0x96,0x8f,0x33,0xf8,0xef,0xfa,0x4f,0x0f,0xff,0x63,0x57,
+  0x62,0xd7,0x61,0x34,0x77,0x1d,0xfc,0x7d,0xc9,0x0d,0x36,0xa2,0x03,0x46,0x58,0x2d,
+  0xe2,0x98,0x2e,0x85,0x0d,0x26,0x56,0x8b,0xfd,0x99,0xf8,0x1f,0x39,0xfa,0x9f,0xfd,
+  0x46,0xf6,0xf7,0x91,0x3d,0xed,0xe2,0x16,0xb2,0xdd,0x98,0xae,0xfd,0x69,0x86,0x28,
+  0xd8,0xbf,0x6b,0xfc,0x32,0xfd,0xef,0x18,0xce,0xfc,0x7c,0xd2,0xfd,0xf3,0x49,0x06,
+  0xb1,0xef,0x9f,0x49,0x21,0xe1,0x28,0xf9,0x47,0x32,0xd9,0xfc,0x93,0x8c,0x83,0xf2,
+  0x7f,0xe5,0xfb,0x4c,0x36,0xed,0x16,0x31,0x73,0x23,0xfe,0x09,0xb7,0x8d,0xe6,0xb4,
+  0x64,0x3e,0x7f,0xca,0xcd,0xa7,0x65,0xdf,0x85,0x38,0x3f,0xe6,0x1f,0x7b,0x59,0x7e,
+  0xdc,0xc7,0x9b,0xf9,0x2b,0x9e,0x1f,0x15,0xfa,0x53,0xae,0x92,0x75,0x45,0x83,0xfd,
+  0x2f,0xa4,0xff,0x57,0xaf,0x63,0x4d,0xd1,0x24,0xf3,0xbf,0x78,0x21,0x61,0xf8,0xbf,
+  0x78,0x81,0xff,0x43,0x9f,0xfa,0x2b,0x57,0xae,0x98,0x7f,0xba,0xf1,0xe9,0x75,0xfe,
+  0x5f,0xbe,0xce,0x04,0xdb,0xf1,0xff,0x8e,0xe1,0x5c,0xe7,0xbf,0xf8,0x5e,0xcd,0x5c,
+  0x67,0xdc,0x9e,0xfb,0x31,0x86,0x6b,0xa7,0x9e,0xe0,0xbd,0x4a,0xc8,0x7f,0xfe,0x5f,
+  0xb7,0x5c,0x08,0x32,0xd1,0xbe,0xfc,0xdf,0xb2,0x9b,0xfe,0xf7,0xee,0xcb,0xce,0x56,
+  0x3b,0x76,0x83,0xfe,0x24,0x23,0xeb,0xfb,0xfc,0x89,0x6f,0xfa,0xb1,0xfb,0x32,0xc1,
+  0x1d,0xf6,0xe8,0xf6,0x7f,0x9c,0x70,0xf3,0x5d,0x15,0x86,0x2e,0x97,0x31,0xf9,0x30,
+  0xeb,0x72,0x0f,0xce,0xfc,0xae,0xff,0xbe,0x7d,0x59,0xff,0xb8,0x5d,0x8f,0x4e,0xdc,
+  0x45,0xc6,0xdf,0x3f,0x0a,0xdb,0x97,0xc9,0xb8,0x3d,0x97,0xb7,0xb0,0x9b,0x64,0x7c,
+  0x97,0xc1,0xbb,0xfe,0x1b,0xf6,0xe5,0x8c,0xf1,0x5f,0xdb,0x97,0x33,0xc6,0x7f,0xf3,
+  0xfd,0x4c,0x32,0x01,0x91,0x3f,0xf1,0xc3,0xf3,0xe7,0xff,0xbb,0x3e,0x75,0x75,0xff,
+  0xc5,0x0b,0xf8,0x7c,0xff,0x2d,0xdf,0xe3,0xff,0xbb,0x9f,0xff,0xaf,0xed,0x3b,0x9f,
+  0x5e,0xe7,0x8f,0x5f,0xe7,0xbf,0xe7,0x13,0x22,0xba,0x20,0xb2,0xff,0x37,0x6d,0xf8,
+  0x3f,0x70,0xf9,0x4f,0x3f,0x9f,0x7e,0x3e,0xfd,0x7c,0xfa,0xf9,0xf4,0xf3,0xe9,0xe7,
+  0xd3,0xcf,0xa7,0x9f,0x4f,0x3f,0x9f,0x7e,0x3e,0xfd,0x7c,0xfa,0xf9,0xf4,0xf3,0xe9,
+  0xe7,0xd3,0xcf,0xa7,0x9f,0x4f,0x3f,0xff,0x7f,0xf8,0x61,0x67,0x4a,0x22,0x3b,0x53,
+  0xa2,0xff,0xbf,0xfe,0x2e,0x9f,0x7e,0x3e,0xfd,0x7c,0xfa,0xf9,0xf4,0xf3,0xe9,0xe7,
+  0xd3,0xcf,0xa7,0x9f,0x4f,0x3f,0x9f,0x7e,0x3e,0xfd,0x7c,0xfa,0xf9,0xf4,0xf3,0xe9,
+  0xe7,0xd3,0xcf,0xa7,0x9f,0x4f,0x3f,0x9f,0x7e,0xfe,0xcf,0x7e,0x42,0x04,0x53,0x21,
+  0x3d,0x7f,0x15,0x22,0x14,0x0b,0x2c,0xa4,0x10,0x31,0x8a,0xfe,0xfb,0xae,0xcd,0xae,
+  0x99,0x13,0x22,0x49,0x21,0xf3,0x6f,0xcd,0xbe,0x3c,0x76,0xdc,0xff,0x03,0xe6,0xeb,
+  0xaf,0xb2,0x8c,0x8c,0x02,0x00,
diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c
new file mode 100755
index 0000000..1672400
--- /dev/null
+++ b/board/esd/tasreg/tasreg.c
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/m5249.h>
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
+
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+/* predefine these here for FPGA programming (before including fpga.c) */
+#define SET_FPGA(data)  mbar2_writeLong(MCFSIM_GPIO1_OUT, data)
+#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_DONE)
+#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_INIT)
+#define FPGA_PROG_ACTIVE_HIGH          /* on this platform is PROG active high!   */
+#define out32(a,b)                     /* nothing to do (gpio already configured) */
+
+
+/* fpga configuration data - generated by bin2cc */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+int checkboard (void) {
+	ulong val;
+	uchar val8;
+
+	puts ("Board: ");
+	puts("esd TASREG");
+	val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
+	printf(" (Switch=%1X)\n", val8);
+
+	/*
+	 * Set LED on
+	 */
+	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
+	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
+
+	return 0;
+};
+
+
+long int initdram (int board_type) {
+	unsigned long	junk = 0xa5a59696;
+
+	/*
+	 *  Note:
+	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
+	 */
+
+#ifdef CFG_FAST_CLK
+	/*
+	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8239);
+#elif CFG_PLL_BYPASS
+	/*
+	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8202);
+#else
+	/*
+	 * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
+	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
+	 */
+	mbar_writeShort(MCFSIM_DCR, 0x8222);
+#endif
+
+	/*
+	 * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
+	 * PM=1 (continuous page mode)
+	 */
+
+	/* RE=0 (keep auto-refresh disabled while setting up registers) */
+	mbar_writeLong(MCFSIM_DACR0, 0x00003324);
+
+	/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
+	mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
+
+	/** Precharge sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
+	*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
+	udelay(0x10); /* Allow several Precharge cycles */
+
+	/** Refresh Sequence **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
+	udelay(0x7d0); /* Allow gobs of refresh cycles */
+
+	/** Mode Register initialization **/
+	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
+	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
+
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+
+int testdram (void) {
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
+
+
+int misc_init_r (void)
+{
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	uchar buf[8];
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 *
+	 */
+	buf[0] = 0x00;
+	buf[1] = 0x32;
+	buf[2] = 0x3f;
+	i2c_write(0x38, 0, 0, buf, 3);
+
+	return (0);
+}
+
+
+#if 1 /* test-only: board specific test commands */
+int i2c_probe(uchar addr);
+
+/*
+ */
+int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+
+	printf("iprobe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+
+	for (;;) {
+		i2c_probe(addr);
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(1000);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	iploop,	2,	1,	do_iploop,
+	"iploop - iprobe loop <addr>\n",
+	NULL
+	);
+
+/*
+ */
+int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	uchar buf[8];
+
+	*(volatile ushort *)0xe0000000 = 0x4000;
+
+	udelay(5000); /* wait for 5ms */
+
+	buf[0] = 0x10;
+	buf[1] = 0x07;
+	buf[2] = 0x03;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x01;
+	buf[2] = 0x80;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x02;
+	buf[2] = 0x03;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x03;
+	buf[2] = 0x29;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x04;
+	buf[2] = 0x00;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x05;
+	buf[2] = 0x00;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	buf[0] = 0x10;
+	buf[1] = 0x07;
+	buf[2] = 0x02;
+	i2c_write(0x10, 0, 0, buf, 3);
+
+	return 0;
+}
+U_BOOT_CMD(
+	codec,	1,	1,	do_codec,
+	"codec - Enable codec\n",
+	NULL
+	);
+
+/*
+ */
+int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+	ulong instr;
+	ulong cntrl;
+	ulong data;
+	uchar buf[8];
+
+	if (argc < 5) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	instr = simple_strtol (argv[2], NULL, 16);
+	cntrl = simple_strtol (argv[3], NULL, 16);
+	data = simple_strtol (argv[4], NULL, 16);
+
+	buf[0] = (uchar)instr;
+	buf[1] = (uchar)cntrl;
+	buf[2] = (uchar)data;
+	i2c_write(addr, 0, 0, buf, 3);
+
+	return 0;
+}
+U_BOOT_CMD(
+	saa,	5,	1,	do_saa,
+	"saa    - Write to SAA1064 <addr> <instr> <cntrl> <data>\n",
+	NULL
+	);
+
+/*
+ */
+int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+	ulong data0;
+	ulong data1;
+	ulong data2;
+	ulong data3;
+	uchar buf[8];
+	int cnt;
+
+	if (argc < 3) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	cnt = simple_strtol (argv[2], NULL, 16);
+	data0 = simple_strtol (argv[3], NULL, 16);
+	data1 = simple_strtol (argv[4], NULL, 16);
+	data2 = simple_strtol (argv[5], NULL, 16);
+	data3 = simple_strtol (argv[6], NULL, 16);
+
+	printf("Writing %d bytes to device %lx!\n", cnt, addr);
+	buf[0] = (uchar)data0;
+	buf[1] = (uchar)data1;
+	buf[2] = (uchar)data2;
+	buf[3] = (uchar)data3;
+	i2c_write(addr, 0, 0, buf, cnt);
+
+	return 0;
+}
+U_BOOT_CMD(
+	iwrite,	6,	1,	do_iwrite,
+	"iwrite - Write n bytes to I2C-device\n",
+	"addr cnt data0 ... datan\n"
+	);
+
+/*
+ */
+int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+	ulong cnt;
+	uchar buf[32];
+	int i;
+
+	if (argc < 3) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	cnt = simple_strtol (argv[2], NULL, 16);
+
+	i2c_read(addr, 0, 0, buf, cnt);
+	printf("I2C Data:");
+	for (i=0; i<cnt; i++) {
+		printf(" %02X", buf[i]);
+	}
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	iread,	3,	1,	do_iread,
+	"iread  - Read from I2C <addr> <cnt>\n",
+	NULL
+	);
+
+/*
+ */
+int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr;
+	uchar buf[32];
+	int cnt;
+
+	if (argc < 2) {
+		puts("ERROR!\n");
+		return -1;
+	}
+
+	addr = simple_strtol (argv[1], NULL, 16);
+	cnt = 1;
+
+	printf("iread looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+
+	for (;;) {
+		i2c_read(addr, 0, 0, buf, cnt);
+
+		/* Abort if ctrl-c was pressed */
+		if (ctrlc()) {
+			puts("\nAbort\n");
+			return 0;
+		}
+
+		udelay(3000);
+	}
+
+	return 0;
+}
+U_BOOT_CMD(
+	ireadl,	2,	1,	do_ireadl,
+	"ireadl - Read-loop from I2C <addr>\n",
+	NULL
+	);
+#endif
diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds
new file mode 100755
index 0000000..a803b1c
--- /dev/null
+++ b/board/esd/tasreg/u-boot.lds
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile
new file mode 100755
index 0000000..a60495a
--- /dev/null
+++ b/board/esd/voh405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/voh405/config.mk b/board/esd/voh405/config.mk
new file mode 100755
index 0000000..219a4eb
--- /dev/null
+++ b/board/esd/voh405/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd VOH405 boards
+#
+
+TEXT_BASE = 0xFFF80000
diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/voh405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/voh405/fpgadata.c b/board/esd/voh405/fpgadata.c
new file mode 100755
index 0000000..02c94a2
--- /dev/null
+++ b/board/esd/voh405/fpgadata.c
@@ -0,0 +1,2011 @@
+  0x1f,0x8b,0x08,0x08,0x38,0x6c,0x35,0x42,0x00,0x03,0x76,0x6f,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x5f,0x30,0x33,0x2e,0x62,0x69,0x74,0x00,0xed,0xfd,0x7d,0x7c,0x1c,0xd5,
+  0x91,0x2f,0x8c,0x57,0x9f,0x6e,0xc9,0xad,0xe9,0x91,0xa6,0xf5,0x62,0x22,0x40,0x98,
+  0xd6,0x48,0x98,0x41,0x19,0x49,0x63,0xc9,0x18,0x63,0xcc,0xa8,0x2d,0x09,0x22,0x6c,
+  0x07,0x4f,0x80,0xcd,0xfa,0x66,0xb9,0xd9,0x31,0xf1,0x66,0xbd,0xfb,0x73,0xb8,0x82,
+  0xe4,0xd9,0x75,0x72,0xb3,0xe4,0x68,0x24,0xdb,0x23,0xcb,0xc1,0x83,0x71,0x88,0x20,
+  0xde,0xec,0xd8,0x78,0x89,0x21,0x4e,0xee,0x58,0x36,0x20,0x63,0x16,0x5a,0x46,0x80,
+  0x6c,0x8c,0x51,0x58,0x27,0xeb,0x10,0x42,0xc6,0x44,0x21,0x82,0x18,0x22,0x8c,0x49,
+  0xe4,0xf7,0xe7,0xd4,0xe9,0x97,0xe9,0x99,0x91,0xd9,0xcd,0xbd,0xf7,0x79,0xee,0x7e,
+  0x7e,0x8f,0x27,0x7f,0xa4,0xe8,0x39,0x6e,0xf5,0xa9,0x39,0x5d,0xf5,0x3d,0x55,0xdf,
+  0xaa,0x03,0x45,0xbe,0x09,0xf3,0x7f,0x00,0xc2,0x32,0x50,0xff,0xee,0xbf,0xad,0x98,
+  0x1d,0xba,0xf6,0x2f,0x67,0xfd,0x65,0xa8,0xb9,0xe1,0xee,0x2f,0x2d,0x87,0xbb,0x40,
+  0x69,0xfa,0xea,0xb5,0xa1,0xbf,0xfa,0xda,0x3d,0xb3,0x66,0xcf,0x86,0x2f,0xb1,0xff,
+  0x0a,0x85,0xae,0x6d,0x0c,0x35,0x37,0xce,0x9a,0x0d,0xcb,0xa1,0x68,0xd6,0xac,0x79,
+  0xb3,0xaf,0x9f,0xd7,0x34,0x17,0xfe,0x0a,0x84,0xe6,0x6d,0xe7,0xd9,0xe7,0x89,0x87,
+  0xff,0xec,0xcb,0x21,0xa0,0x02,0x00,0x4c,0x0b,0x09,0x51,0xfc,0x7f,0x25,0x24,0x68,
+  0x02,0xd0,0x96,0xfa,0x10,0x18,0xf8,0xdf,0x60,0x7d,0x5f,0x14,0x02,0xcd,0xfd,0xdf,
+  0x42,0x08,0x74,0x88,0x80,0xbe,0x5e,0x2d,0x83,0x7f,0xff,0x23,0xe8,0x12,0xb5,0xe5,
+  0x3f,0x71,0xfc,0xf9,0x03,0xf4,0x82,0xc3,0x32,0x9f,0x96,0xe3,0x49,0x4b,0x52,0x49,
+  0xe8,0x3f,0x72,0x7f,0xb0,0xef,0xfa,0xfb,0x37,0xfe,0x43,0xf7,0xff,0x83,0x7d,0xff,
+  0x3f,0x75,0x3c,0xa8,0xff,0x81,0xe1,0x00,0x92,0xf3,0x3c,0xaa,0xa0,0x41,0x07,0x14,
+  0x82,0x40,0x21,0x0a,0x95,0x17,0x10,0x5a,0x86,0xed,0xf1,0x86,0x70,0x0e,0xce,0xd3,
+  0x96,0x03,0xbe,0x81,0xee,0x7b,0xe1,0x1c,0x84,0xf5,0xe2,0x09,0xf1,0x3e,0xf5,0x4d,
+  0xb5,0x45,0xf3,0xbd,0x24,0x1e,0x87,0x33,0xb4,0xb9,0xd2,0xbb,0x4f,0x0c,0x41,0xa7,
+  0x3d,0x3e,0xfe,0x63,0xd8,0x4b,0x1b,0x26,0x94,0x13,0x7d,0x7e,0x58,0x67,0x34,0xec,
+  0xf3,0x9c,0x28,0xab,0xad,0xe8,0x8d,0x34,0x68,0x4a,0x8c,0xbc,0x03,0x83,0xd4,0x2f,
+  0xcb,0xb1,0x7d,0xa1,0x5a,0x5b,0x8b,0x23,0xd2,0x7a,0xd8,0x05,0x41,0x43,0x69,0x22,
+  0x00,0x03,0x0b,0x82,0x23,0x97,0xce,0x22,0x2b,0x20,0xa1,0xad,0xd4,0x94,0x42,0x62,
+  0xc0,0x20,0x68,0x95,0x72,0x39,0x69,0x02,0xcd,0xbe,0xbf,0xb4,0x03,0xf6,0x42,0x83,
+  0xa1,0xa4,0x88,0x46,0xd7,0x91,0x86,0xb4,0x27,0x45,0x02,0x6a,0x3c,0x7e,0xab,0xae,
+  0xc4,0x49,0x5a,0xdf,0x43,0xfd,0x9a,0xdc,0x4f,0x42,0x92,0xfd,0x3c,0x37,0x4d,0x3f,
+  0x06,0xa7,0xd9,0x78,0x5f,0xaa,0xcd,0x0f,0xa7,0x92,0xe1,0x0f,0x8b,0x53,0x0b,0x16,
+  0xc3,0x11,0x63,0x86,0xe0,0x7b,0x44,0x4c,0xc3,0x84,0x36,0xb0,0xc2,0xbb,0x5e,0x54,
+  0xdb,0xed,0xf1,0x49,0xe1,0x59,0x78,0x1e,0xae,0x64,0xe3,0xd9,0x77,0x1f,0x24,0xc2,
+  0x86,0x38,0xe1,0x3f,0xc1,0xee,0xd0,0xa2,0xfa,0xa8,0x78,0x02,0x35,0x00,0xbe,0x44,
+  0xdb,0x38,0xd3,0x94,0xf9,0x19,0x55,0x77,0xb0,0x6f,0xc3,0x86,0x2f,0x24,0x26,0xd5,
+  0x53,0xd0,0x34,0x5a,0x9c,0x12,0x8f,0xc1,0x49,0x68,0xea,0xf2,0x25,0x6f,0x0f,0x56,
+  0x8f,0xab,0xe1,0x98,0x77,0x4b,0x77,0x48,0xb2,0x9f,0x7f,0xa4,0x20,0xa8,0xee,0x85,
+  0x46,0x43,0x99,0x28,0x9b,0x16,0x5f,0x07,0x73,0x0c,0x79,0x82,0x1c,0x83,0x3d,0x11,
+  0xbf,0xa1,0xac,0xf6,0x37,0xb0,0xaf,0x1a,0x64,0x39,0x41,0xe6,0xb0,0xd5,0x6f,0xcf,
+  0x77,0x31,0x3c,0x08,0xb5,0x86,0x12,0x22,0x14,0x06,0x88,0xdf,0x90,0x53,0x64,0x31,
+  0x0c,0xa8,0x01,0x43,0x09,0x10,0x05,0x1e,0x1d,0x69,0x48,0xca,0xdb,0x0b,0x57,0xb1,
+  0x77,0xc5,0xfc,0x4c,0xc0,0x17,0xe1,0x69,0x5a,0x9f,0x56,0x56,0x91,0x32,0xf8,0x76,
+  0xe2,0xaa,0xb4,0xbc,0xaa,0xf0,0x67,0xb0,0x1b,0xaf,0x2c,0x25,0x33,0x54,0xf6,0x55,
+  0x54,0x5e,0x4a,0xee,0x73,0xee,0xdf,0x01,0x8b,0xd5,0x8f,0x60,0xbe,0xe1,0x9b,0x2b,
+  0x52,0xf8,0x50,0x0d,0x4d,0x7a,0x43,0xe2,0x08,0x9d,0x60,0x8a,0xf7,0x95,0xf6,0x41,
+  0xf2,0x2e,0x98,0xaf,0x7b,0x0b,0xc5,0xdb,0x88,0xbd,0x90,0xf4,0x2b,0x9e,0x85,0xf3,
+  0xd0,0xc2,0xf4,0xd3,0x35,0xaa,0x7f,0x58,0x1a,0x8e,0x97,0xec,0x14,0x27,0xe1,0x8c,
+  0xda,0x7c,0x87,0xef,0x27,0xe2,0x04,0x7e,0xd5,0xbe,0x61,0x54,0x4c,0x14,0xda,0xfa,
+  0x91,0x81,0xeb,0x67,0xcc,0x3b,0xd0,0x0d,0xf0,0x06,0x0d,0xa5,0xbd,0xbb,0xbb,0x83,
+  0x6c,0x58,0xd3,0x88,0x6f,0x42,0x7c,0x0f,0xf6,0xb7,0x37,0x1a,0xde,0xb4,0xe8,0x71,
+  0x7e,0xdf,0x91,0xca,0xcd,0xf0,0x34,0xd4,0x8f,0x14,0xdf,0x2b,0x26,0xe0,0xa7,0x50,
+  0x6d,0x14,0xfc,0x9d,0x78,0x07,0xfb,0x45,0xaa,0x47,0x94,0x08,0x79,0xd3,0xf8,0xc1,
+  0x8a,0x46,0x5d,0x1e,0x25,0x4d,0x8e,0x3e,0x35,0xf8,0x3e,0x9b,0x6f,0x30,0x5d,0xf4,
+  0x0d,0xcf,0x57,0xe1,0x01,0x5a,0x93,0xee,0x58,0x55,0xf8,0x45,0x78,0x92,0x56,0x6f,
+  0x63,0x1a,0x38,0xb7,0xa0,0x27,0x5e,0x9f,0x8e,0xaf,0x20,0xaa,0x73,0xff,0x15,0xd6,
+  0x7a,0x2b,0x4a,0x91,0x0d,0xf0,0x80,0xa0,0x19,0x0f,0xa7,0xc8,0x57,0xe8,0x9e,0x94,
+  0x96,0x56,0xfe,0x91,0x1c,0xa4,0x8f,0x42,0xf0,0x2e,0xf9,0x32,0x4f,0x99,0x73,0xff,
+  0xf1,0xe9,0xe3,0xc2,0x29,0x08,0xd3,0xe2,0xa4,0xb8,0x0a,0xde,0x92,0x76,0xd1,0x91,
+  0xa4,0xf8,0x75,0x38,0xa7,0x0f,0xc4,0x7c,0x63,0xe2,0x7b,0xda,0x01,0x68,0x19,0x0c,
+  0xbe,0x27,0xce,0x93,0xec,0xf9,0x76,0x08,0x49,0x98,0x84,0xb0,0xe0,0xa3,0x35,0x28,
+  0xdc,0xe7,0xf5,0xd1,0xdb,0xd3,0x15,0x93,0x7a,0x58,0xf5,0xad,0xa9,0x39,0x5a,0x39,
+  0xd9,0x1a,0x86,0x0d,0x3d,0xe2,0xeb,0x60,0xaf,0x7f,0x59,0xdd,0xc6,0x56,0x4b,0x58,
+  0xf7,0x25,0xca,0x67,0x26,0x2d,0xa1,0x16,0xf6,0x43,0x53,0x74,0x43,0x7f,0x73,0xad,
+  0x7a,0x12,0xe6,0x47,0xbd,0xa5,0x22,0x91,0xec,0xf1,0x54,0x5a,0xce,0xc6,0x37,0xe8,
+  0x8b,0x12,0xa4,0xa7,0xac,0x97,0x09,0x25,0x09,0xb2,0x0d,0x7a,0x75,0xff,0x4b,0x4a,
+  0xbf,0x27,0x48,0xf7,0xea,0x0d,0x2b,0xd8,0xfa,0xd7,0x1c,0xb3,0x30,0xb7,0xa0,0x16,
+  0x1e,0x66,0xc3,0x2e,0x4f,0x90,0xab,0xc8,0xe3,0x4c,0x50,0x12,0x85,0xb5,0xd0,0x1b,
+  0xdd,0xaa,0x2b,0x0f,0x90,0xda,0xf8,0x1e,0xda,0x70,0x13,0x5b,0x6f,0x85,0xce,0x7a,
+  0xd0,0x2a,0x24,0xd8,0x02,0x41,0x5d,0xa9,0xf0,0x6c,0x83,0x2e,0x08,0x46,0x94,0x8a,
+  0xc2,0xd5,0xd0,0xb5,0x40,0xd3,0x95,0xd9,0x4d,0x12,0xec,0x64,0x57,0xe4,0xd9,0x04,
+  0x04,0x7b,0x3d,0xac,0xf2,0x46,0xa1,0x1f,0x5f,0x0a,0x50,0x34,0x18,0x27,0x61,0x58,
+  0x02,0x6d,0x1a,0x19,0x81,0x26,0xf0,0xd1,0x36,0x0d,0x98,0xea,0x20,0x48,0x95,0x19,
+  0xa2,0xbd,0x3e,0xfb,0xa7,0xf3,0xf9,0x46,0x7c,0x9b,0xca,0x4f,0xc0,0xd9,0xd6,0x96,
+  0xc8,0xfd,0x9b,0x6a,0x4e,0xc0,0x79,0x7d,0x86,0xe1,0x3b,0x2c,0x0e,0xb3,0xaf,0x5a,
+  0x22,0x1b,0x0e,0x8b,0xef,0x14,0xda,0xef,0x63,0x65,0xc1,0x98,0xa9,0x9f,0x07,0xc5,
+  0x0a,0x54,0x8b,0xee,0xdd,0x54,0xbe,0xed,0xb6,0x57,0xe5,0x26,0x9d,0x8e,0x8a,0x4c,
+  0x51,0x85,0x2d,0x1d,0xde,0xd7,0xc5,0x42,0xc7,0xfe,0xcc,0xad,0x4c,0xb3,0xb5,0xdb,
+  0x50,0xa1,0xac,0x65,0x4a,0x88,0x13,0xbf,0xbc,0x8e,0x92,0x00,0xc4,0x61,0x2b,0x78,
+  0x62,0x4d,0x9a,0x7c,0x04,0x1a,0x2a,0xe3,0x6b,0x36,0x96,0x38,0xfa,0xec,0x80,0x1e,
+  0x9c,0x94,0xae,0xa8,0x33,0x25,0xd2,0xa5,0x6b,0xb7,0x29,0x15,0xa4,0x87,0x76,0xc9,
+  0x7e,0x5d,0xae,0xd8,0x58,0x8b,0xaa,0xb8,0x59,0x2e,0xf5,0x94,0x09,0xf6,0xfd,0xfb,
+  0xa5,0x6d,0xb0,0x47,0x60,0x6a,0x54,0x49,0xad,0xdc,0xab,0x69,0x4b,0xbf,0xa7,0x12,
+  0x89,0xf6,0x82,0x5f,0x0f,0xa4,0xb6,0x5e,0x45,0xf7,0x30,0x0d,0xcb,0x0f,0x91,0x99,
+  0xce,0x7a,0x48,0x4e,0xb7,0x9e,0x3f,0xf1,0xa5,0xab,0xa3,0xfb,0xa3,0x03,0x9f,0xf3,
+  0x25,0xc4,0x6d,0xf2,0x7e,0x23,0xa4,0x57,0x3c,0xac,0x48,0xea,0xbb,0x5a,0x78,0x65,
+  0x30,0xd1,0x16,0x70,0xec,0xd5,0x88,0x60,0xaf,0x07,0x65,0x2c,0xf4,0x21,0x0d,0x47,
+  0x4b,0x12,0xe2,0x98,0xf4,0xe1,0x48,0x78,0xb9,0x4f,0x15,0xc7,0xd4,0x9f,0x4b,0xf3,
+  0xa3,0xbe,0xca,0x07,0x4f,0x39,0xf6,0x47,0x56,0xf9,0x7a,0x63,0x4a,0x16,0x35,0x38,
+  0xb2,0xa0,0x49,0x0d,0xd2,0x1a,0x0d,0x98,0xfe,0x43,0xbe,0x78,0x8d,0x16,0x60,0x0b,
+  0x4f,0xf6,0xd2,0xb6,0x03,0xce,0x7a,0x0e,0x14,0x04,0xe0,0x19,0x68,0xa0,0x72,0x92,
+  0x3c,0xa2,0x3d,0x41,0xb6,0x52,0x92,0x64,0xfa,0xf9,0xb1,0xee,0xa7,0xca,0x38,0xb9,
+  0x46,0x7a,0x06,0x1a,0x37,0x06,0xc6,0xc9,0x01,0x67,0x3d,0x04,0x98,0xfd,0xc1,0xf7,
+  0x45,0x0e,0x91,0xcf,0x30,0x43,0x14,0x30,0x6e,0x09,0x11,0x2f,0x74,0x19,0x9a,0xa1,
+  0x54,0x92,0x62,0x68,0x86,0x60,0x54,0xae,0x62,0xe3,0x9d,0xf5,0x09,0x77,0xb2,0xf7,
+  0x37,0x98,0x96,0x9b,0xc8,0x11,0xe8,0x86,0x1a,0x34,0x5c,0x55,0xb0,0x45,0xae,0x1e,
+  0x55,0xf4,0x8d,0x95,0xf8,0x6a,0x53,0xb9,0x33,0x36,0xee,0xac,0xcf,0x78,0xfc,0x8b,
+  0xf0,0x47,0x7a,0x63,0xda,0xbb,0x4a,0xbc,0x0d,0xfe,0xad,0x67,0xd6,0xb1,0xe2,0x6f,
+  0xae,0x0d,0x1b,0x2f,0xd3,0x59,0x6f,0xfb,0x26,0xc5,0x19,0xda,0x89,0x75,0x2d,0x51,
+  0xef,0xd2,0x9a,0xf7,0xfc,0xf6,0x78,0xcf,0x15,0xa6,0xbd,0xdd,0xf0,0x64,0x75,0x92,
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diff --git a/board/esd/voh405/logo_320_240_4bpp.c b/board/esd/voh405/logo_320_240_4bpp.c
new file mode 100755
index 0000000..e9f8cb4
--- /dev/null
+++ b/board/esd/voh405/logo_320_240_4bpp.c
@@ -0,0 +1,77 @@
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diff --git a/board/esd/voh405/logo_640_480_24bpp.c b/board/esd/voh405/logo_640_480_24bpp.c
new file mode 100755
index 0000000..7d3c7a3
--- /dev/null
+++ b/board/esd/voh405/logo_640_480_24bpp.c
@@ -0,0 +1,1722 @@
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+  0xc1,0x20,0x53,0xd0,0x7f,0x6b,0xc5,0x86,0x4c,0xaf,0x12,0x00,0x00,0x00,0x08,0x17,
+  0xc4,0x98,0x77,0x79,0x80,0xfe,0x3b,0xf6,0x6c,0xaa,0xdf,0x62,0x7a,0x95,0x00,0x00,
+  0x00,0x40,0xe8,0xa0,0xc3,0xab,0x82,0x4d,0x41,0x2f,0x1a,0x67,0x7a,0x89,0x00,0x00,
+  0x00,0x40,0xe8,0xa0,0x48,0x3f,0x5d,0xff,0xde,0x00,0xfd,0x77,0xfc,0x47,0x31,0x0e,
+  0x18,0x00,0x00,0x00,0x28,0x84,0xe6,0x07,0x59,0x05,0xcd,0x74,0x62,0x87,0xe9,0x25,
+  0x02,0x00,0x00,0x00,0xa1,0x83,0x8e,0x04,0x9d,0x82,0xbe,0xc9,0xf4,0x12,0x01,0x00,
+  0x00,0x80,0xd0,0x41,0x43,0xbd,0xc1,0xa6,0xa0,0xef,0xfc,0x34,0xc5,0x22,0xa6,0x57,
+  0x09,0x00,0x00,0x00,0x84,0x0c,0x22,0x9a,0xf5,0xab,0x00,0xfd,0xf7,0xe2,0xd7,0xd1,
+  0xc9,0xbd,0xa6,0x17,0x09,0x00,0x00,0x00,0x84,0x0e,0x3a,0xf0,0x22,0x5d,0x78,0x56,
+  0x80,0x16,0xfc,0xe2,0x04,0xd3,0x4b,0x04,0x00,0x00,0x00,0x42,0x07,0xc5,0x86,0xe8,
+  0xda,0x77,0x05,0xe8,0xbf,0xb7,0x7f,0xd2,0x4a,0xc4,0x4d,0xaf,0x12,0x00,0x00,0x00,
+  0x08,0x1d,0x34,0xeb,0x97,0x01,0xfa,0xef,0x98,0xb3,0xe9,0xf4,0x41,0xd3,0x4b,0x04,
+  0x00,0x00,0x00,0x42,0x07,0xed,0x5b,0x1c,0xa0,0xff,0x32,0x2d,0xbb,0xd7,0xf4,0x12,
+  0x01,0x00,0x00,0x80,0xd0,0x41,0x03,0x1d,0x74,0xd5,0xdb,0x03,0xf4,0xdf,0xfb,0xfe,
+  0x8d,0x92,0x48,0x41,0x03,0x00,0x00,0x00,0x79,0x10,0xcd,0xf8,0x59,0x80,0xfe,0x3b,
+  0xf6,0x6c,0x6a,0xa9,0x35,0xbd,0x46,0x00,0x00,0x00,0x20,0x74,0xd0,0x9e,0x45,0xc1,
+  0xa6,0xa0,0x97,0x4f,0x34,0xbd,0x44,0x00,0x00,0x00,0x20,0x74,0xd0,0x50,0x0f,0x5d,
+  0xf5,0xb6,0x40,0x53,0xd0,0x56,0x22,0x66,0x7a,0x95,0x00,0x00,0x00,0x40,0xd8,0x20,
+  0x7a,0xec,0x87,0x01,0xfa,0xef,0xa5,0x6f,0x44,0x0a,0x1a,0x00,0x00,0x00,0x28,0x84,
+  0xb6,0xcd,0x09,0x36,0x05,0xbd,0xe6,0x21,0xd3,0x4b,0x04,0x00,0x00,0x00,0x42,0x07,
+  0xf5,0xb6,0xd0,0xe5,0x6f,0x0e,0xd0,0x7f,0x1f,0xf8,0xf2,0xff,0x07,0x66,0x87,0xe4,
+  0x0f,0x36,0x10,0x0e,0x00,
diff --git a/board/esd/voh405/u-boot.lds b/board/esd/voh405/u-boot.lds
new file mode 100755
index 0000000..43f7765
--- /dev/null
+++ b/board/esd/voh405/u-boot.lds
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
new file mode 100755
index 0000000..eda3fd9
--- /dev/null
+++ b/board/esd/voh405/voh405.c
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp_320[] =
+{
+#include "logo_320_240_4bpp.c"
+};
+
+unsigned char logo_bmp_640[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/s1d13704_320_240_4bpp.h"
+#include "../common/s1d13806_320_240_4bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFFB5);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	volatile unsigned short *lcd_contrast =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
+	volatile unsigned short *lcd_backlight =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+	char *str;
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_INIT pin
+	 */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT);  /* reset low */
+	udelay(1000); /* wait 1ms */
+	out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT);   /* reset high */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+
+	/*
+	 * Init lcd interface and display logo
+	 */
+	str = getenv("bd_type");
+	if (strcmp(str, "voh405_bw") == 0) {
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+	} else if (strcmp(str, "voh405_bwbw") == 0) {
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+		lcd_setup(1, 1);
+		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+			 regs_13806_320_240_4bpp,
+			 sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+	} else if (strcmp(str, "voh405_bwc") == 0) {
+		lcd_setup(0, 1);
+		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+			 regs_13704_320_240_4bpp,
+			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+			 logo_bmp_320, sizeof(logo_bmp_320));
+		lcd_setup(1, 0);
+		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+			 regs_13806_640_480_16bpp,
+			 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+			 logo_bmp_640, sizeof(logo_bmp_640));
+	} else {
+		printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+		return 0;
+	}
+
+	/*
+	 * Set invert bit in small lcd controller
+	 */
+	*(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01;
+
+	/*
+	 * Set default contrast voltage on epson vga controller
+	 */
+	*lcd_contrast = 0x4646;
+
+	/*
+	 * Enable backlight
+	 */
+	*lcd_backlight = 0xffff;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming VOH405");
+	} else {
+		puts(str);
+	}
+
+	if (getenv_r("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s)", str);
+	} else {
+		puts(" (Missing bd_type!)");
+	}
+
+	putc ('\n');
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	volatile unsigned short *fpga_mode =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+
+	/*
+	 * Assert or deassert CompactFlash Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+	} else {		/* release RESET */
+		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif
diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile
new file mode 100755
index 0000000..a11ee82
--- /dev/null
+++ b/board/esd/vom405/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+# Objects for Xilinx JTAG programming (CPLD)
+CPLD    = ../common/xilinx_jtag/lenval.o \
+	  ../common/xilinx_jtag/micro.o \
+	  ../common/xilinx_jtag/ports.o
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/vom405/config.mk b/board/esd/vom405/config.mk
new file mode 100755
index 0000000..3041b77
--- /dev/null
+++ b/board/esd/vom405/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd VOH405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x00FC0000
diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/vom405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/vom405/fpgadata.c b/board/esd/vom405/fpgadata.c
new file mode 100755
index 0000000..1c3a963
--- /dev/null
+++ b/board/esd/vom405/fpgadata.c
@@ -0,0 +1,1812 @@
+  0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,
+  0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00,
+  0xf9,0x60,0x40,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00,
+  0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08,
+  0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
+  0x08,0xea,0x08,0x00,0x00,0x00,0x32,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x04,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x00,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x00,0x24,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x00,0x28,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x30,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
+  0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,
+  0x00,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x00,0x00,0x03,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,
+  0x80,0x00,0x00,0x10,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x84,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x09,0x00,0x00,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x90,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
+  0xa0,0x00,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa4,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xb0,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc0,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x09,0x00,0x00,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x04,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x08,0x00,
+  0x00,0x01,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x0c,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x10,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x20,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x24,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x28,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x30,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x01,0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x01,0x44,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x01,0x48,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x01,0x4c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,
+  0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x50,
+  0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x03,0x09,0x00,0x01,0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x01,0x84,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x88,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x01,0x90,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x01,0xa0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x01,0xa4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x01,0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x01,0xac,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x01,0xb0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x01,0xc0,0x00,0x00,0x40,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,
+  0xc4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xc8,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,0xcc,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0xd0,0x00,0x00,0x00,0x03,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,
+  0x02,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x02,0x04,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x09,0x00,0x02,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x02,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x02,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x02,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,
+  0x24,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x28,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x2c,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x30,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x40,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x44,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x02,0x48,0x00,0x00,0x00,0x01,0x00,
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+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x09,0x00,0x33,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x33,0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x33,0x90,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x33,0xa0,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x33,0xa4,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,
+  0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xac,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xb0,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc0,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc4,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xc8,0x00,0x20,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x33,0xcc,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x09,0x00,0x33,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x34,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x04,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,
+  0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x0c,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x10,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x20,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x24,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x28,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x2c,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x30,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x44,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x34,0x48,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x34,0x4c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x34,0x50,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x34,0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,
+  0x00,0x09,0x00,0x34,0x84,0x00,0x00,0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x88,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x8c,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x90,0x00,0x00,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x34,0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x34,0xac,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x34,0xb0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x34,0xc0,0x00,0x00,0x00,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x34,0xc4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x34,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,
+  0xcc,0x00,0x00,0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
+  0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0xd0,0x00,0x00,0x00,
+  0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,
+  0x09,0x00,0x35,0x00,0xa0,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x04,
+  0x80,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x09,0x00,0x35,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x35,0x0c,0x20,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x35,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x35,0x20,0xc0,0x00,0x14,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x35,0x24,0x00,0x00,0x00,0x15,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x35,0x28,0x00,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
+  0x2c,0xc0,0x00,0x14,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x30,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x40,0x08,
+  0x00,0x04,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x44,0x80,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x48,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x4c,0x88,0x00,0x84,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x50,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0x80,0x00,
+  0x00,0x30,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x84,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x35,0x88,0x20,0x80,0x08,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
+  0x8c,0x40,0x00,0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x90,
+  0xa0,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa0,0x00,
+  0x00,0x20,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa4,0x00,0x80,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa8,0xc0,0x1c,0x14,
+  0x85,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x00,0x48,0x01,
+  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xb0,0xc0,0x00,0x14,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc0,0x80,0x00,0x80,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x00,0x80,0x09,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x08,0x00,0x04,0x61,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x35,0xcc,0x40,0x00,0x48,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x35,0xd0,0x88,0x00,0x04,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x88,0x00,0x04,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,
+  0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff,
+  0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00,
diff --git a/board/esd/vom405/u-boot.lds b/board/esd/vom405/u-boot.lds
new file mode 100755
index 0000000..f7a20d1
--- /dev/null
+++ b/board/esd/vom405/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
new file mode 100755
index 0000000..445b8fc
--- /dev/null
+++ b/board/esd/vom405/vom405.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+
+extern void lxt971_no_sleep(void);
+
+
+/* fpga configuration data - not compressed, generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+int filesize = sizeof(fpgadata);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	/*
+	 * Reset CPLD via GPIO12 (CS3) pin
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(0x80000000 >> 12));
+	udelay(1000); /* wait 1ms */
+	out32(GPIO0_OR, in32(GPIO0_OR) | (0x80000000 >> 12));
+	udelay(1000); /* wait 1ms */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	unsigned char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+	int flashcnt;
+	int delay;
+	volatile unsigned char *led_reg = (unsigned char *)((ulong)CAN_BA + 0x1000);
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming VOM405");
+	} else {
+		puts(str);
+	}
+
+	printf(" (PLD-Version=%02d)\n", *led_reg);
+
+	/*
+	 * Flash LEDs
+	 */
+	for (flashcnt = 0; flashcnt < 3; flashcnt++) {
+		*led_reg = 0x40;        /* LED_B..D off */
+		for (delay = 0; delay < 100; delay++)
+			udelay(1000);
+		*led_reg = 0x47;        /* LED_B..D on */
+		for (delay = 0; delay < 50; delay++)
+			udelay(1000);
+	}
+	*led_reg = 0x40;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+	/*
+	 * Disable sleep mode in LXT971
+	 */
+	lxt971_no_sleep();
+#endif
+}
diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile
new file mode 100755
index 0000000..a60495a
--- /dev/null
+++ b/board/esd/wuh405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../common/misc.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esd/wuh405/config.mk b/board/esd/wuh405/config.mk
new file mode 100755
index 0000000..1d743a9
--- /dev/null
+++ b/board/esd/wuh405/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ASH405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c
new file mode 100755
index 0000000..89af119
--- /dev/null
+++ b/board/esd/wuh405/flash.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+/*
+ * include common flash code (for esd boards)
+ */
+#include "../common/flash.c"
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	uint pbcr;
+	unsigned long base_b0;
+	int size_val = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
+	switch (size_b0) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	mtdcr(ebccfgd, pbcr);
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
diff --git a/board/esd/wuh405/fpgadata.c b/board/esd/wuh405/fpgadata.c
new file mode 100755
index 0000000..fdc02e3
--- /dev/null
+++ b/board/esd/wuh405/fpgadata.c
@@ -0,0 +1,1818 @@
+  0x1f,0x8b,0x08,0x08,0xe2,0x44,0xc5,0x42,0x00,0x03,0x77,0x75,0x68,0x34,0x30,0x35,
+  0x5f,0x31,0x2e,0x62,0x69,0x74,0x00,0xec,0xbd,0x0d,0x74,0x14,0xd7,0x95,0x2e,0xba,
+  0xeb,0x54,0x49,0x94,0xba,0x5b,0xea,0x42,0x48,0x1e,0xd9,0x60,0x5c,0x6a,0x09,0xd2,
+  0x28,0x8d,0x68,0x24,0x47,0x60,0x21,0x4b,0x45,0x8b,0x78,0x14,0x20,0x41,0xe3,0x78,
+  0x12,0xee,0x7d,0x5e,0x99,0xb6,0x43,0x66,0x78,0x33,0xc4,0x97,0xc4,0xb9,0x77,0x88,
+  0x27,0xd7,0x3e,0x6a,0x09,0x23,0x2c,0x6c,0xda,0x36,0x89,0x71,0xe2,0xc9,0x34,0x98,
+  0x24,0xd8,0x61,0x32,0x0d,0xc2,0x46,0x80,0x63,0x97,0xb0,0xe2,0x34,0x58,0xc6,0x8a,
+  0xe3,0xc9,0x60,0xcc,0xe0,0x26,0x51,0x6c,0xd9,0x96,0xb1,0x8c,0x19,0x5b,0x20,0x40,
+  0xef,0xec,0x53,0x5d,0xd5,0x55,0xfd,0x23,0x27,0x77,0xd6,0xbc,0x35,0x6f,0xbd,0x61,
+  0xd6,0xba,0x77,0xa7,0xba,0x52,0xa9,0x73,0x74,0x6a,0xef,0xef,0x7c,0xfb,0xdb,0xfb,
+  0x40,0x91,0x77,0xcc,0xf8,0x3f,0x00,0xe1,0x36,0x28,0xfe,0xdb,0xff,0xb9,0xf6,0xfa,
+  0xe0,0x67,0xfe,0x62,0x61,0xed,0x1d,0x5f,0x5d,0x03,0xb7,0x83,0xbb,0xee,0xce,0xcf,
+  0x04,0xbf,0xf6,0xad,0x6f,0x2c,0xbc,0xfe,0x7a,0xf8,0x2a,0xfb,0x4f,0xc1,0xe0,0x67,
+  0x16,0x04,0x17,0x2d,0x08,0x2e,0x84,0x35,0x50,0xb4,0xf0,0x33,0x8d,0x75,0x8b,0x1b,
+  0x83,0xf5,0xf0,0x35,0x10,0xea,0x77,0x4d,0xb2,0x7f,0x4f,0x3e,0xfa,0xe7,0x7f,0x19,
+  0x04,0x2a,0x00,0xc0,0xb4,0xa0,0x10,0xc6,0xff,0xdf,0x1d,0x14,0x54,0x01,0x68,0xcb,
+  0xfc,0x20,0xe8,0xf8,0x9f,0x21,0xf5,0x7b,0x51,0x10,0x54,0xfb,0x7f,0x16,0x82,0xa0,
+  0x41,0x3b,0x68,0x5b,0x84,0x52,0xf8,0x43,0xfe,0x75,0xd1,0x94,0x21,0xfd,0x61,0xf7,
+  0x4b,0xe6,0xfd,0x93,0xc7,0x68,0xde,0x9b,0xd2,0xff,0x5a,0xce,0xc5,0x52,0x56,0x01,
+  0x09,0x7e,0xf2,0xed,0x82,0x46,0xcd,0xa7,0x5e,0x3c,0xf9,0x07,0x3d,0xff,0x7f,0x99,
+  0xcf,0xbf,0xf2,0x47,0xde,0x0f,0xca,0x1f,0x70,0x3b,0x1b,0xaf,0x69,0x5c,0x54,0x40,
+  0x06,0x02,0x40,0xc1,0x0f,0x2e,0x20,0x14,0x62,0xb9,0x8c,0x96,0x65,0xe6,0xfd,0xfa,
+  0xc6,0x2b,0x30,0xd1,0xd9,0x92,0x74,0x8f,0x88,0xdf,0xaa,0x98,0xa4,0x0d,0x27,0x8a,
+  0xc7,0xc4,0x3a,0x66,0xb4,0x0c,0x7b,0xc7,0xc5,0x31,0x78,0x83,0xd6,0x27,0xd1,0x10,
+  0xc2,0xe6,0xfd,0x15,0x3f,0x86,0xc3,0xb4,0x36,0xe9,0xde,0x4d,0xe6,0x42,0x4f,0x75,
+  0x65,0x7f,0xcf,0x37,0x9e,0xf7,0xe1,0x95,0x84,0xb7,0x8f,0xbc,0x09,0x3d,0xd4,0x97,
+  0x74,0xf7,0x91,0xa4,0x64,0xce,0x62,0x42,0xea,0x92,0x7b,0x21,0xa0,0xbb,0x63,0x85,
+  0xc3,0xd0,0x2b,0x07,0x06,0xdd,0x41,0x02,0x78,0x25,0xc1,0x8c,0x63,0xd2,0xc3,0x92,
+  0xaa,0x33,0xe3,0x88,0xa0,0x9a,0xcf,0x2f,0x18,0x86,0xc3,0x50,0xdb,0xcf,0x9e,0x1f,
+  0x9b,0xde,0x09,0x35,0xfd,0x2b,0xe2,0x35,0x7e,0x38,0x4c,0x6a,0x75,0x77,0x1c,0x9f,
+  0x0f,0x3e,0x34,0xc6,0xa4,0xf5,0xa9,0xfb,0x97,0x96,0x8f,0xc2,0x04,0x34,0xeb,0xde,
+  0x1a,0xf1,0x26,0x8a,0x46,0x71,0x7c,0x86,0x9f,0x5d,0x99,0xad,0x5f,0x17,0x17,0xcf,
+  0xc2,0xeb,0x50,0xa7,0x7b,0xe3,0xe2,0xd0,0x32,0xf3,0xfe,0xb8,0xb0,0x1f,0x26,0xa1,
+  0x45,0xf7,0x26,0x3b,0xbe,0xc6,0x8c,0x45,0xfa,0xaa,0x31,0x71,0xbf,0x3a,0x49,0x5a,
+  0xf4,0x92,0xb1,0x69,0x83,0xec,0xca,0x73,0xba,0x77,0x4c,0x1c,0x01,0x73,0xbc,0x43,
+  0xca,0x2e,0xe3,0xf9,0x31,0x71,0x97,0x3e,0x01,0x8d,0x7a,0x71,0x50,0x9c,0x27,0x4d,
+  0x48,0xcd,0xfd,0x5e,0x7c,0xfe,0xbb,0xa4,0x19,0x9f,0x3f,0x26,0x99,0xef,0x9f,0x28,
+  0xa8,0xc6,0xf7,0xd7,0xdd,0xbb,0xe9,0xa7,0xd8,0xdb,0x56,0xe9,0xf2,0x18,0x99,0x4f,
+  0x71,0x44,0x33,0xe3,0x64,0x14,0x3a,0x81,0x0f,0xe4,0x1c,0x5b,0xfd,0xa9,0xf1,0x4a,
+  0x2b,0x81,0xcf,0x8f,0x9f,0xfc,0x52,0x7a,0x5c,0xf0,0xb3,0xd9,0x28,0xfc,0x53,0xe3,
+  0x4a,0x90,0xe8,0xf0,0xb8,0x61,0x8c,0xb3,0x6f,0xc5,0xf8,0x37,0xa6,0x7c,0x49,0x3b,
+  0x10,0x9b,0x9f,0x74,0x7f,0xdb,0x75,0x15,0x6c,0xa2,0x95,0x23,0xae,0x6f,0xcf,0x7e,
+  0x05,0x0e,0xc4,0xbe,0x3e,0xe2,0xde,0x40,0xde,0x60,0x57,0xd8,0x4f,0x1b,0xc8,0x09,
+  0xeb,0xf9,0x6d,0xf2,0x32,0xf8,0x30,0xde,0xa4,0x7b,0x55,0xb1,0x8b,0x0d,0x64,0x71,
+  0xd2,0x1b,0x14,0xff,0xf4,0xc4,0x87,0xd1,0xa6,0x11,0x77,0x50,0x1c,0x84,0xdf,0x01,
+  0xfb,0x29,0x28,0xbe,0x42,0xcc,0xf5,0xa0,0x15,0xec,0x57,0x26,0xcb,0xd8,0xfc,0x28,
+  0xe2,0x7e,0x78,0x1f,0x1a,0x87,0x8a,0xe3,0xa2,0xdf,0x98,0xb1,0xb1,0xaa,0xd4,0x54,
+  0x8f,0x89,0x43,0xc4,0x9c,0x1f,0x59,0xda,0x03,0x2f,0xe2,0x45,0x75,0xda,0xb7,0x60,
+  0x82,0x36,0xbe,0xea,0x79,0xfa,0xc5,0xf9,0x2a,0xbb,0x2d,0xe9,0x89,0xb3,0x69,0xe4,
+  0xf7,0xc7,0xc5,0x63,0x60,0xcd,0x4f,0xc5,0x36,0xf8,0x17,0x98,0xaf,0xbb,0xc3,0x64,
+  0x16,0x3c,0x07,0x6a,0xa2,0xf8,0x9b,0xe2,0x2d,0xf4,0x80,0x34,0x5f,0x97,0xd7,0x93,
+  0x53,0x70,0x00,0x7f,0x5a,0x4f,0xce,0x59,0xf3,0xa9,0xc2,0xd3,0x7c,0x50,0x3d,0x23,
+  0x91,0xef,0x49,0x07,0x22,0xf3,0x46,0xe4,0x1b,0xc8,0x57,0xb4,0x03,0xec,0x4a,0xd1,
+  0x06,0x72,0x1a,0x0e,0x18,0xe3,0xd5,0xad,0xe7,0x8f,0x48,0x5d,0xf0,0x30,0x9f,0xcf,
+  0x23,0xf7,0xb2,0x69,0x54,0xf5,0xa2,0x60,0xe8,0x0b,0x6a,0xaf,0x18,0xd0,0xe5,0x20,
+  0x39,0x4e,0x53,0x13,0xfb,0x8a,0xf5,0xfc,0x64,0xf9,0x08,0x1c,0x83,0x66,0xea,0x1d,
+  0x15,0x0f,0xeb,0x17,0xa1,0x91,0x7a,0x62,0x55,0x7f,0x43,0x2f,0xb2,0x2b,0x81,0x98,
+  0x38,0xce,0x0d,0xf6,0xa7,0x1f,0x97,0xcc,0xf1,0xb6,0x09,0x31,0x18,0x87,0x66,0xf0,
+  0x52,0xb7,0xca,0x8d,0x05,0xb4,0x2a,0x09,0xe3,0x04,0xaf,0x88,0x67,0x52,0x3f,0x89,
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+  0xee,0x62,0x32,0xc5,0xb3,0x06,0xcc,0x4d,0xbf,0x0c,0x1d,0xe5,0x3d,0xe1,0xc4,0xe8,
+  0xe0,0x47,0x9b,0xa6,0xc7,0x56,0xe3,0x01,0x08,0xea,0x7c,0x88,0xd4,0xe5,0x5a,0x2a,
+  0x1f,0x2a,0x26,0x52,0x12,0xb1,0x10,0x97,0x55,0x20,0xd6,0x97,0xfc,0x5a,0xa3,0x55,
+  0xa1,0xbd,0x04,0xf9,0x30,0xb0,0x16,0xe9,0x41,0x92,0xe4,0xc3,0xc5,0x5d,0xcf,0xac,
+  0x0e,0xd1,0xb1,0xd2,0x97,0xab,0xf9,0x0f,0xec,0x3e,0x7a,0xba,0xdc,0x7a,0x93,0xfe,
+  0xd2,0xee,0x82,0xb1,0x52,0x6b,0x35,0xf7,0x81,0xfd,0x75,0x2a,0xcd,0x9c,0xf2,0x76,
+  0xdc,0xac,0xb5,0x40,0x1b,0x38,0x0f,0x8c,0x8a,0x24,0x1d,0xa7,0x06,0xbf,0x92,0xbb,
+  0x8d,0x53,0x33,0xfc,0xc8,0xb0,0xe8,0x03,0x35,0x8a,0xc9,0x17,0x2f,0x60,0x02,0xde,
+  0x01,0x59,0xec,0x31,0x1c,0xa4,0x00,0xeb,0x3c,0x6a,0x92,0xb0,0xcc,0xa5,0xc8,0x8c,
+  0x7e,0x74,0x7e,0xf1,0xf8,0x8e,0x5b,0x1e,0x16,0xeb,0x22,0x71,0x58,0xf2,0x81,0x1b,
+  0x35,0xc5,0x93,0xbb,0x39,0xab,0x8b,0x9a,0xa5,0x18,0x1e,0xda,0xd5,0xbf,0x3e,0xec,
+  0x32,0xd1,0xbb,0x98,0xf1,0x6d,0x9e,0x68,0x80,0x09,0x0d,0x4d,0x3b,0x6f,0xf6,0xb7,
+  0x08,0x8b,0x05,0xe2,0x8b,0x32,0x82,0xcc,0x84,0xc1,0xd1,0xbb,0x0f,0xd3,0xa2,0x45,
+  0xfc,0xea,0xf1,0x34,0xdc,0x80,0x83,0x1e,0x89,0x9e,0x28,0xb0,0x3a,0x1f,0x66,0x0b,
+  0xb8,0xdf,0x49,0x50,0x2c,0xe0,0xb6,0xe8,0xff,0x58,0x80,0x62,0x65,0xb5,0x47,0x1e,
+  0x32,0x2b,0xb5,0xe6,0xef,0x43,0x32,0xf8,0x77,0x3e,0xe4,0xac,0x81,0x85,0x4d,0xd3,
+  0xfc,0x7b,0x11,0x0c,0xd3,0xa3,0x2f,0x21,0xcd,0x9a,0xad,0x1b,0xf8,0x90,0xd6,0xcd,
+  0x6a,0xd8,0x92,0xb2,0x6a,0x56,0x14,0x0f,0x13,0xfc,0xe6,0x8d,0xe0,0x4d,0x17,0x06,
+  0x90,0xdf,0x7e,0x28,0x2e,0xd3,0x93,0xd7,0xcb,0xf0,0xd0,0x04,0xb5,0x79,0x14,0x0f,
+  0xf9,0x2c,0x3e,0xf4,0x9f,0x69,0xa9,0x35,0x2b,0xda,0x22,0x19,0x0e,0xcf,0x2f,0x78,
+  0x38,0x34,0xb6,0xb8,0xf0,0xba,0x11,0x2d,0xb8,0xbf,0x47,0xf3,0x53,0xc4,0x53,0x24,
+  0x0e,0xe4,0xd1,0xd7,0x8d,0x8d,0x37,0xb5,0x6e,0x1a,0x87,0x86,0x9b,0xfb,0x69,0x01,
+  0x07,0x3c,0xc3,0x9d,0xc0,0x70,0x89,0x58,0x17,0x56,0x40,0x85,0xc9,0x3c,0x63,0xa2,
+  0xe9,0x53,0x00,0x31,0xf3,0x4d,0x9c,0x05,0x8e,0x88,0x96,0xd5,0x6b,0xa5,0x72,0xc3,
+  0x84,0x2d,0xa0,0xc4,0x33,0x85,0x34,0x58,0x0e,0x3a,0x4f,0xb9,0x53,0x08,0x8a,0x7f,
+  0x0a,0xd2,0xae,0xd1,0x00,0xc5,0x54,0x93,0x18,0x15,0x5e,0x25,0x82,0xdf,0x3a,0x82,
+  0xa3,0x96,0xb3,0x26,0xcd,0x9b,0x56,0xfb,0x5a,0xe2,0xbb,0x04,0x5b,0x8a,0xce,0x3a,
+  0x96,0x96,0x1d,0xec,0xe8,0xa9,0x43,0xca,0xf5,0x92,0x84,0x73,0x81,0x77,0x04,0xbd,
+  0x2e,0x59,0x8b,0x5d,0xe0,0x4b,0x68,0x92,0x6b,0x20,0x4c,0x1b,0x9a,0xd8,0x85,0x92,
+  0x68,0x51,0xf2,0x49,0x31,0x3f,0x22,0xe9,0xf1,0x0d,0xd7,0x8c,0xf8,0x90,0x0e,0x94,
+  0xcf,0x04,0x6d,0xa7,0xd2,0x0f,0xc9,0x85,0x2b,0x02,0x1d,0xed,0xd5,0x66,0x3c,0x0c,
+  0xa1,0x57,0xa6,0x1d,0xe4,0x73,0x34,0xa3,0x21,0x16,0xce,0xf0,0xdd,0x15,0xab,0x12,
+  0x0f,0xce,0x64,0x4c,0x32,0x41,0x62,0x11,0x6e,0xa1,0xf9,0x4a,0x80,0x69,0xe7,0x1d,
+  0x2a,0x5b,0xd0,0x84,0x87,0x5c,0x75,0x3f,0xcd,0x07,0x70,0x89,0xec,0x87,0xec,0x2c,
+  0x3c,0x2a,0x1f,0x21,0x07,0x20,0xcb,0xed,0x47,0xf4,0x12,0x9a,0xa3,0x68,0x7a,0x2e,
+  0x81,0x34,0x11,0x1f,0x32,0x32,0x01,0xde,0x32,0xf2,0x21,0xc6,0xc3,0x3d,0xde,0xee,
+  0xc7,0x10,0x0b,0xf9,0xb4,0xc0,0xc2,0x02,0x99,0xe7,0x41,0x68,0xb8,0x12,0x0f,0xce,
+  0xb7,0x9b,0x72,0xfe,0xfc,0xa4,0x8c,0x34,0x58,0xc5,0x32,0x6a,0xb6,0xdc,0xe0,0xc3,
+  0xb2,0x98,0x6f,0x82,0x0f,0xd5,0xf5,0x45,0x20,0xe3,0xb4,0x86,0xf3,0xa7,0x64,0x79,
+  0x79,0x13,0x59,0x8a,0xa1,0xc9,0xa1,0xa1,0xa1,0xc9,0x44,0x3c,0xc6,0x18,0x96,0x94,
+  0xf7,0x1d,0xdf,0x30,0x61,0x2f,0xae,0x23,0xa7,0x4a,0x52,0x24,0xeb,0x15,0x6b,0xd8,
+  0x82,0x06,0xea,0x86,0x91,0x28,0x1e,0x93,0xfa,0xb6,0xe4,0x43,0xce,0xba,0x30,0xdb,
+  0xc4,0x91,0x0f,0x59,0x1d,0x0b,0x9b,0x06,0x94,0xf5,0x35,0xec,0xb5,0x96,0x78,0xd5,
+  0x33,0x17,0x63,0x5d,0x48,0x83,0x58,0x62,0x0b,0x3e,0x9c,0x43,0x12,0xdb,0x3b,0x87,
+  0x09,0xa3,0x22,0xf8,0x70,0x0e,0x94,0xf5,0xc5,0xae,0xca,0x24,0x83,0x39,0xb7,0xec,
+  0x49,0x53,0xc2,0xfc,0x63,0xbb,0xf0,0x6d,0x62,0xf3,0x3f,0x04,0x16,0xa2,0x4e,0xac,
+  0x9d,0x37,0xd7,0x17,0xf6,0xe7,0xd3,0xd0,0x0e,0x89,0x8c,0x59,0xe1,0x01,0xdc,0x88,
+  0x63,0x46,0xae,0xc0,0x4c,0x1f,0xe6,0x9f,0x18,0xa9,0xac,0x61,0x8e,0x46,0x53,0x52,
+  0xd7,0x57,0xc0,0x8e,0xc0,0x7e,0x88,0xcf,0xd6,0xaa,0xfc,0x08,0xd9,0x4f,0xb2,0xbc,
+  0xf2,0x88,0x9e,0x6f,0x11,0x77,0x90,0x3f,0x9a,0x3e,0x92,0xdc,0x1f,0xc7,0x3b,0xc8,
+  0x9b,0xe3,0x53,0xc4,0xf2,0xfb,0x9b,0xc1,0xfe,0x53,0xf1,0x05,0xf8,0x05,0xf8,0x2c,
+  0x65,0xc5,0x29,0x7c,0x88,0xb9,0x53,0x9a,0x95,0x46,0x8b,0x7a,0xbf,0x28,0x0c,0xb0,
+  0x96,0x62,0x7c,0xa2,0xb2,0xc0,0xfb,0x59,0x4b,0x26,0xee,0xc0,0x3d,0xda,0x5f,0x48,
+  0x15,0x43,0xc3,0x52,0x13,0x71,0xc7,0x5a,0x25,0x56,0x33,0x9e,0x2c,0x0d,0x56,0x5c,
+  0x7f,0xc4,0x85,0x1f,0x95,0x99,0x30,0xa6,0x7d,0x2d,0x6c,0x49,0xd9,0xd7,0x21,0x58,
+  0x29,0x08,0xc3,0x2d,0x65,0x7c,0xa0,0x1b,0xb3,0xb4,0xfa,0xf2,0xe4,0xee,0x67,0xbc,
+  0xd7,0x8a,0xd6,0x57,0xa1,0xc1,0x87,0x3c,0x77,0x4e,0x98,0x4e,0xeb,0x63,0xe4,0x43,
+  0x4b,0x60,0xe1,0x22,0x9c,0xb3,0xcd,0x90,0x0f,0x9b,0xe3,0x99,0x67,0xb9,0xd7,0xed,
+  0xb4,0x93,0xcf,0xf3,0x13,0xd3,0x45,0xdb,0x31,0xf2,0xc4,0x62,0x0c,0xd3,0x8e,0x81,
+  0xf9,0x27,0x07,0xd8,0x42,0xf3,0x40,0xa2,0xf5,0x8e,0xf3,0x21,0xac,0x8c,0xbb,0x64,
+  0xe6,0xb3,0x66,0x0d,0x39,0x37,0x41,0x14,0x31,0xc4,0xac,0xd7,0x0b,0x25,0x88,0x78,
+  0x5e,0xf0,0x21,0x87,0x2a,0x43,0x1a,0xa4,0xb1,0x32,0x43,0x50,0xa4,0x2a,0x28,0x86,
+  0x26,0xea,0xcd,0xf2,0xaf,0x91,0x49,0x46,0x1f,0x9c,0x7d,0xc5,0x6d,0x49,0xb4,0xb1,
+  0xf5,0x07,0x9d,0x87,0x53,0x2d,0xf1,0x49,0x34,0x03,0x87,0x8d,0xd7,0xea,0x46,0xc9,
+  0x3f,0x78,0xbd,0x3d,0x17,0x33,0x4b,0xc8,0x87,0xef,0xfe,0xbe,0x47,0xec,0xfe,0x7b,
+  0xbc,0x74,0x2d,0x31,0x23,0x79,0xa0,0xbd,0x01,0x06,0x4a,0xfe,0x01,0xf8,0xda,0x5b,
+  0x23,0x0f,0xdf,0xbd,0xbd,0xfc,0x9d,0x1b,0x2f,0xbe,0x35,0x26,0xf8,0xf0,0xfd,0x3a,
+  0x1f,0x2e,0x47,0x7c,0xb8,0xeb,0x19,0xf7,0x50,0xc4,0x87,0xc7,0x05,0x1f,0xee,0xd4,
+  0xf9,0xf0,0x69,0xc4,0x87,0xbb,0x78,0xec,0xf3,0xea,0xab,0x02,0x0b,0xff,0x5a,0xd9,
+  0xd9,0x1e,0xda,0xaa,0x83,0x22,0x12,0xe3,0x73,0xf8,0x50,0xfe,0xf4,0xbf,0x6f,0x62,
+  0xff,0x4f,0x1b,0xa0,0x78,0xf9,0x79,0x7c,0x38,0xd8,0xe0,0xc3,0xee,0x03,0xe3,0x1b,
+  0xf3,0xfd,0x9b,0x4f,0x1e,0x0f,0x5d,0x7a,0xa6,0xff,0xe3,0x2f,0x1e,0xbd,0x0f,0x1e,
+  0x11,0x2f,0x28,0x7c,0xc8,0xa6,0xbe,0xf8,0x59,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,
+  0xb4,0xb4,0xb4,0xb4,0xfe,0xdf,0x25,0x6b,0x07,0xaa,0x6b,0x07,0x2d,0x2d,0x2d,0x2d,
+  0x2d,0x2d,0x2d,0x2d,0x2d,0x2d,0xad,0xe7,0x4b,0xd6,0x0e,0x09,0x5d,0x3b,0x68,0x69,
+  0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x3d,0x5f,0xb2,0x76,0x30,0x65,0xed,
+  0xf0,0xbf,0x0e,0x45,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0xeb,0xbf,
+  0x28,0x5f,0xfc,0xd1,0x24,0xf8,0xe7,0x79,0x1f,0xb8,0xf8,0xce,0x53,0xdc,0x07,0xf6,
+  0xb9,0xdf,0x27,0xd4,0x3f,0x6b,0xf8,0x50,0x25,0xd1,0x39,0x1f,0x9f,0x7e,0xb6,0xdf,
+  0xbf,0x00,0x34,0x34,0xbf,0x69,0xee,0x33,0x01,0x00,
diff --git a/board/esd/wuh405/u-boot.lds b/board/esd/wuh405/u-boot.lds
new file mode 100755
index 0000000..95854f2
--- /dev/null
+++ b/board/esd/wuh405/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
new file mode 100755
index 0000000..db24122
--- /dev/null
+++ b/board/esd/wuh405/wuh405.c
@@ -0,0 +1,252 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+#define FPGA_DEBUG
+#endif
+
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* fpga configuration data - gzip compressed and generated by bin2c */
+const unsigned char fpgadata[] =
+{
+#include "fpgadata.c"
+};
+
+/*
+ * include common fpga code (for esd boards)
+ */
+#include "../common/fpga.c"
+
+
+/* Prototypes */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
+	volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
+	unsigned char *dst;
+	ulong len = sizeof(fpgadata);
+	int status;
+	int index;
+	int i;
+
+	dst = malloc(CFG_FPGA_MAX_SIZE);
+	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		printf ("GUNZIP ERROR - must RESET board to recover\n");
+		do_reset (NULL, 0, 0, NULL);
+	}
+
+	status = fpga_boot(dst, len);
+	if (status != 0) {
+		printf("\nFPGA: Booting failed ");
+		switch (status) {
+		case ERROR_FPGA_PRG_INIT_LOW:
+			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_INIT_HIGH:
+			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+			break;
+		case ERROR_FPGA_PRG_DONE:
+			printf("(Timeout: DONE not high after programming FPGA)\n ");
+			break;
+		}
+
+		/* display infos on fpgaimage */
+		index = 15;
+		for (i=0; i<4; i++) {
+			len = dst[index];
+			printf("FPGA: %s\n", &(dst[index+1]));
+			index += len+3;
+		}
+		putc ('\n');
+		/* delayed reboot */
+		for (i=20; i>0; i--) {
+			printf("Rebooting in %2d seconds \r",i);
+			for (index=0;index<1000;index++)
+				udelay(1000);
+		}
+		putc ('\n');
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	puts("FPGA:  ");
+
+	/* display infos on fpgaimage */
+	index = 15;
+	for (i=0; i<4; i++) {
+		len = dst[index];
+		printf("%s ", &(dst[index+1]));
+		index += len+3;
+	}
+	putc ('\n');
+
+	free(dst);
+
+	/*
+	 * Reset FPGA via FPGA_DATA pin
+	 */
+	SET_FPGA(FPGA_PRG | FPGA_CLK);
+	udelay(1000); /* wait 1ms */
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Reset external DUARTs
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	udelay(10); /* wait 10us */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	udelay(1000); /* wait 1ms */
+
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+
+	/*
+	 * Enable interrupts in exar duart mcr[3]
+	 */
+	*duart0_mcr = 0x08;
+	*duart1_mcr = 0x08;
+	*duart2_mcr = 0x08;
+	*duart3_mcr = 0x08;
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming WUH405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif
diff --git a/board/esteem192e/Makefile b/board/esteem192e/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/esteem192e/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/esteem192e/config.mk b/board/esteem192e/config.mk
new file mode 100755
index 0000000..9d6080b
--- /dev/null
+++ b/board/esteem192e/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8xxL boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c
new file mode 100755
index 0000000..3959eea
--- /dev/null
+++ b/board/esteem192e/esteem192e.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Modified By Conn Clark to work with Esteem 192E 7/31/00
+ *
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 *
+	 * active, NOP, read, precharge, NOP */
+	0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
+	0x11FFCC05,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 * NOP, Program
+	 */
+	0x0F0A8C34, 0x1F354C37,	/* last */
+
+	_NOT_USED_,		/* Not used */
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 * active, NOP, read, NOP, NOP, NOP, NOP, NOP */
+	0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
+	0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 * active, NOP, write, NOP, precharge, NOP */
+	0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
+	0x0FF74C04, 0x1FFFCC05,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 * active, NOP, write, NOP, NOP, NOP, NOP, NOP */
+	0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
+	0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 * precharge, NOP, auto_ref, NOP, NOP, NOP */
+	0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
+	0x0FFFCCB4, 0x1FFFCC35,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x0FFB8C00, 0x1FF74C03,	/* last */
+	_NOT_USED_, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: Esteem 192E\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0, size_b1;
+
+	/*
+	 * Explain frequency of refresh here
+	 */
+
+	memctl->memc_mptpr = 0x0200;	/* divide by 32 */
+
+	memctl->memc_mamr = 0x18003112;	/*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+
+	memctl->memc_or2 = CFG_OR2_PRELIM;	/* not defined yet */
+	memctl->memc_br2 = CFG_BR2_PRELIM;
+
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+
+	/* perform SDRAM initializsation sequence */
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 0 execute 8 refresh */
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+
+	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 1 execute 8 refresh */
+	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
+
+	memctl->memc_mamr = CFG_MAMR_8COL;	/* 0x18803112  start refresh timer TODO: explain here */
+
+/* printf ("banks 0 and 1 are programed\n"); */
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 */
+	size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+	size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+	printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
+
+/* printf ("bank 1 size %u\n",size_b1); */
+
+	if (size_b1 == 0) {
+		/*
+		 * Adjust refresh rate if bank 0 isn't stuffed
+		 */
+		memctl->memc_mptpr = 0x0400;	/* divide by 64 */
+		memctl->memc_br3 &= 0x0FFFFFFFE;
+
+		/*
+		 * Adjust OR2 for size of bank 0
+		 */
+		memctl->memc_or2 |= 7 * size_b0;
+	} else {
+		if (size_b0 < size_b1) {
+			memctl->memc_br2 &= 0x00007FFE;
+			memctl->memc_br3 &= 0x00007FFF;
+
+			/*
+			 * Adjust OR3 for size of bank 1
+			 */
+			memctl->memc_or3 |= 15 * size_b1;
+
+			/*
+			 * Adjust OR2 for size of bank 0
+			 */
+			memctl->memc_or2 |= 15 * size_b0;
+			memctl->memc_br2 += (size_b1 + 1);
+		} else {
+			memctl->memc_br3 &= 0x00007FFE;
+
+			/*
+			 * Adjust OR2 for size of bank 0
+			 */
+			memctl->memc_or2 |= 15 * size_b0;
+
+			/*
+			 * Adjust OR3 for size of bank 1
+			 */
+			memctl->memc_or3 |= 15 * size_b1;
+			memctl->memc_br3 += (size_b0 + 1);
+		}
+	}
+
+	/* before leaving set all unused i/o pins to outputs */
+
+	/*
+	 *      --*Unused Pin List*--
+	 *
+	 * group/port           bit number
+	 * IP_B                 0,1,3,4,5  Taken care of in pcmcia-cs-x.x.xx
+	 * PA                   5,7,8,9,14,15
+	 * PB                   22,23,31
+	 * PC                   4,5,6,7,10,11,12,13,14,15
+	 * PD                   5,6,7
+	 *
+	 */
+
+	/*
+	 *   --*Pin Used for I/O List*--
+	 *
+	 * port     input bit number    output bit number    either
+	 * PB                           18,26,27
+	 * PD       3,4                                      8,9,10,11,12,13,14,15
+	 *
+	 */
+
+	immap->im_ioport.iop_papar &= ~0x05C3;	/* set pins as io */
+	immap->im_ioport.iop_padir |= 0x05C3;	/* set pins as output */
+	immap->im_ioport.iop_paodr &= 0x0008;	/* config pins 9 & 14 as normal outputs */
+	immap->im_ioport.iop_padat |= 0x05C3;	/* set unused pins as high */
+
+	immap->im_cpm.cp_pbpar &= ~0x00001331;	/* set unused port b pins as io */
+	immap->im_cpm.cp_pbdir |= 0x00001331;	/* set unused port b pins as output */
+	immap->im_cpm.cp_pbodr &= ~0x00001331;	/* config bits 18,22,23,26,27 & 31 as normal outputs */
+	immap->im_cpm.cp_pbdat |= 0x00001331;	/* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
+
+	immap->im_ioport.iop_pcpar &= ~0x0F3F;	/* set unused port c pins as io */
+	immap->im_ioport.iop_pcdir |= 0x0F3F;	/* set unused port c pins as output */
+	immap->im_ioport.iop_pcso &= ~0x0F3F;	/* clear special purpose bit for unused port c pins for clarity */
+	immap->im_ioport.iop_pcdat |= 0x0F3F;	/* set unused port c pins high */
+
+	immap->im_ioport.iop_pdpar &= 0xE000;	/* set pins as io */
+	immap->im_ioport.iop_pddir &= 0xE000;	/* set bit 3 & 4 as inputs */
+	immap->im_ioport.iop_pddir |= 0x07FF;	/* set bits 5 - 15 as outputs */
+	immap->im_ioport.iop_pddat = 0x0055;	/* set alternating pattern on test port */
+
+	return (size_b0 + size_b1);
+}
diff --git a/board/esteem192e/flash.c b/board/esteem192e/flash.c
new file mode 100755
index 0000000..5465dea
--- /dev/null
+++ b/board/esteem192e/flash.c
@@ -0,0 +1,1095 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#ifdef CONFIG_FLASH_16BIT
+#define FLASH_WORD_SIZE	unsigned short
+#define	FLASH_ID_MASK	0xFFFF
+#else
+#define FLASH_WORD_SIZE unsigned long
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
+#ifndef CONFIG_FLASH_16BIT
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+#else
+static int write_short (flash_info_t *info, ulong dest, ushort data);
+#endif
+/*int flash_write (uchar *, ulong, ulong); */
+/*flash_info_t *addr2info (ulong);   */
+
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE0_PRELIM,
+				 &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM,
+				 &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801; /*  (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;*/
+
+	/* Re-do sizing to get full correct info */
+
+	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE,
+				 &flash_info[0]);
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_MONITOR_BASE,
+			    CFG_MONITOR_BASE+monitor_flash_len-1,
+			    &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 = (CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
+			      /*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V;*/
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE+monitor_flash_len-1,
+				    &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if (info->flash_id & FLASH_BTYPE) {
+	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_FLASH_16BIT
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00008000;
+		info->start[3] = base + 0x0000C000;
+		info->start[4] = base + 0x00010000;
+		info->start[5] = base + 0x00014000;
+		info->start[6] = base + 0x00018000;
+		info->start[7] = base + 0x0001C000;
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x000E0000;
+		}
+	       }
+	     else {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	       }
+#else
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00002000;
+		info->start[2] = base + 0x00004000;
+		info->start[3] = base + 0x00006000;
+		info->start[4] = base + 0x00008000;
+		info->start[5] = base + 0x0000A000;
+		info->start[6] = base + 0x0000C000;
+		info->start[7] = base + 0x0000E000;
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00070000;
+		}
+	       }
+	     else {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	       }
+#endif
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_FLASH_16BIT
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00014000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x0001C000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+
+	       } else {
+
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	       }
+#else
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000A000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x0000E000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+
+	       } else {
+
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	       }
+#endif
+	}
+
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[]=", bottom boot sect)\n";
+	uchar topboot[]=", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	if (info->flash_id & 0x0001 ) {
+	boottype = botboot;
+	} else {
+	boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit%s",boottype);
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit%s",boottype);
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit%s",boottype);
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit%s",boottype);
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit%s",boottype);
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit%s",boottype);
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit%s",boottype);
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL800B:	printf ("INTEL28F800B (8 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL800T:	printf ("INTEL28F800T (8 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL160B:	printf ("INTEL28F160B (16 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL160T:	printf ("INTEL28F160T (16 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL320B:	printf ("INTEL28F320B (32 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL320T:	printf ("INTEL28F320T (32 Mbit%s",boottype);
+				break;
+
+#if 0 /* enable when devices are available */
+
+	case FLASH_INTEL640B:	printf ("INTEL28F640B (64 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL640T:	printf ("INTEL28F640T (64 Mbit%s",boottype);
+				break;
+#endif
+
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	short i;
+	ulong base = (ulong)addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+
+#ifndef CONFIG_FLASH_16BIT
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if(addr[0x0000] != 0x00890089){
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+#else
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x0089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x0090;
+
+	if(addr[0x0000] != 0x0089){
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0090;
+#endif
+	}
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+
+	case (AMD_ID_LV400T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV160T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case (AMD_ID_LV320T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_LV320B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+
+	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800T;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160T;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+#if 0 /* enable when devices are available */
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start adress table */
+	if (info->flash_id & FLASH_BTYPE) {
+	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_FLASH_16BIT
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00008000;
+		info->start[3] = base + 0x0000C000;
+		info->start[4] = base + 0x00010000;
+		info->start[5] = base + 0x00014000;
+		info->start[6] = base + 0x00018000;
+		info->start[7] = base + 0x0001C000;
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x000E0000;
+		}
+	       }
+	     else {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	       }
+#else
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00002000;
+		info->start[2] = base + 0x00004000;
+		info->start[3] = base + 0x00006000;
+		info->start[4] = base + 0x00008000;
+		info->start[5] = base + 0x0000A000;
+		info->start[6] = base + 0x0000C000;
+		info->start[7] = base + 0x0000E000;
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00070000;
+		}
+	       }
+	     else {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	       }
+#endif
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CONFIG_FLASH_16BIT
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00014000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x0001C000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+
+	       } else {
+
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	       }
+#else
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000A000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x0000E000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+
+	       } else {
+
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	       }
+#endif
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+		if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){
+		   *addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+		} else {
+		   *addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+		}
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+
+	volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
+	int flag, prot, sect, l_sect, barf;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    ((info->flash_id > FLASH_AMD_COMP) &&
+	     ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+    if(info->flash_id < FLASH_AMD_COMP) {
+#ifndef CONFIG_FLASH_16BIT
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+#else
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+	addr[0x0555] = 0x0080;
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+#endif
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+			addr[0] = (0x00300030 & FLASH_ID_MASK);
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
+	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
+			  (0x00800080&FLASH_ID_MASK)  )
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+    } else {
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			barf = 0;
+#ifndef CONFIG_FLASH_16BIT
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00200020;
+			addr[0] = 0x00D000D0;
+			while(!(addr[0] & 0x00800080));	/* wait for error or finish */
+			if( addr[0] & 0x003A003A) {	/* check for error */
+				barf = addr[0] & 0x003A0000;
+				if( barf ) {
+					barf >>=16;
+				} else {
+					barf = addr[0] & 0x0000003A;
+				}
+			}
+#else
+			addr = (vu_short*)(info->start[sect]);
+			addr[0] = 0x0020;
+			addr[0] = 0x00D0;
+			while(!(addr[0] & 0x0080));	/* wait for error or finish */
+			if( addr[0] & 0x003A)	/* check for error */
+				barf = addr[0] & 0x003A;
+#endif
+			if(barf) {
+				printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
+				if(barf & 0x0002) printf("Block locked, not erased.\n");
+				if((barf & 0x0030) == 0x0030)
+					printf("Command Sequence error.\n");
+				if((barf & 0x0030) == 0x0020)
+					printf("Block Erase error.\n");
+				if(barf & 0x0008) printf("Vpp Low error.\n");
+				rcode = 1;
+			} else printf(".");
+			l_sect = sect;
+		}
+	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+
+	}
+
+    }
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+#ifndef CONFIG_FLASH_16BIT
+	ulong cp, wp, data;
+	int l;
+#else
+	ulong cp, wp;
+	ushort data;
+#endif
+	int i, rc;
+
+#ifndef CONFIG_FLASH_16BIT
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+
+#else
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+/*	l = 0; used for debuging  */
+	while (cnt >= 2) {
+		data = 0;
+		for (i=0; i<2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+/*		if(!l){
+			printf("%x",data);
+			l = 1;
+		}  used for debuging */
+
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_short(info, wp, data));
+
+
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifndef CONFIG_FLASH_16BIT
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start,barf;
+	int flag;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+     if(info->flash_id > FLASH_AMD_COMP) {
+	/* AMD stuff */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+     } else {
+	/* intel stuff */
+	*addr = 0x00400040;
+     }
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+     if(info->flash_id > FLASH_AMD_COMP) {
+
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+     } else {
+
+	while(!(addr[0] & 0x00800080)){  	/* wait for error or finish */
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+	}
+
+	if( addr[0] & 0x003A003A) {	/* check for error */
+		barf = addr[0] & 0x003A0000;
+		if( barf ) {
+			barf >>=16;
+		} else {
+			barf = addr[0] & 0x0000003A;
+		}
+		printf("\nFlash write error at address %lx\n",(unsigned long)dest);
+		if(barf & 0x0002) printf("Block locked, not erased.\n");
+		if(barf & 0x0010) printf("Programming error.\n");
+		if(barf & 0x0008) printf("Vpp Low error.\n");
+		return(2);
+	}
+
+
+     }
+
+	return (0);
+
+}
+
+#else
+
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	ulong start,barf;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+     if(info->flash_id < FLASH_AMD_COMP) {
+	/* AMD stuff */
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+	addr[0x0555] = 0x00A0;
+     } else {
+	/* intel stuff */
+	*addr = 0x00D0;
+	*addr = 0x0040;
+     }
+	*((vu_short *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+     if(info->flash_id < FLASH_AMD_COMP) {
+	  /* AMD stuff */
+	while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+     } else {
+	/* intel stuff */
+	while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+	}
+
+	if( addr[0] & 0x003A) {	/* check for error */
+		barf = addr[0] & 0x003A;
+		printf("\nFlash write error at address %lx\n",(unsigned long)dest);
+		if(barf & 0x0002) printf("Block locked, not erased.\n");
+		if(barf & 0x0010) printf("Programming error.\n");
+		if(barf & 0x0008) printf("Vpp Low error.\n");
+		return(2);
+	}
+	*addr = 0x00B0;
+	*addr = 0x0070;
+	while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+	}
+
+	*addr = 0x00FF;
+
+     }
+
+	return (0);
+
+}
+
+
+#endif
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds
new file mode 100755
index 0000000..4c541bf
--- /dev/null
+++ b/board/esteem192e/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/etin/debris/Makefile b/board/etin/debris/Makefile
new file mode 100755
index 0000000..305a1bf
--- /dev/null
+++ b/board/etin/debris/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS =  $(BOARD).o flash.o phantom.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/etin/debris/config.mk b/board/etin/debris/config.mk
new file mode 100755
index 0000000..64debf5
--- /dev/null
+++ b/board/etin/debris/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000, 2001
+# Sangmoon, Etin Systems, dogoil@etinsys.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Debris boards
+#
+
+#TEXT_BASE = 0x00090000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c
new file mode 100755
index 0000000..93c502c
--- /dev/null
+++ b/board/etin/debris/debris.c
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2000
+ * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <i2c.h>
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Debris "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" ##Test not implemented yet##\n");
+	return 0;
+}
+
+#if 0 	/* NOT USED */
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("## Test not implemented yet ##\n");
+
+	return (0);
+}
+#endif
+
+long int initdram (int board_type)
+{
+	int m, row, col, bank, i;
+	unsigned long start, end;
+	uint32_t mccr1;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	if (i2c_reg_read (0x50, 2) != 0x04) return 0;	/* Memory type */
+	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
+	row = i2c_reg_read (0x50, 3);	/* # of rows */
+	col = i2c_reg_read (0x50, 4);	/* # of columns */
+	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	start = CFG_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_debris_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_debris_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+void *nvram_read(void *dest, const long src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*) dest;
+	volatile uchar *s = (volatile uchar*) src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+	return dest;
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*)dest;
+	volatile uchar *s = (volatile uchar*)src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+}
+
+int misc_init_r(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Write ethernet addr in NVRAM for VxWorks */
+	nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
+			(char*)&gd->bd->bi_enetaddr[0], 6);
+	return 0;
+}
diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c
new file mode 100755
index 0000000..a4100e5
--- /dev/null
+++ b/board/etin/debris/flash.c
@@ -0,0 +1,720 @@
+/*
+ * board/eva/flash.c
+ *
+ * (C) Copyright 2002
+ * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+#include <mpc824x.h>
+
+int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
+int (*write_dword)(flash_info_t*, ulong, uint64_t);
+
+typedef uint64_t cfi_word;
+
+#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr))
+
+#define cfi_write(flash, val, addr) \
+	move64((cfi_word*)&val, \
+			(cfi_word*)(flash->start[0] + addr))
+
+#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x)))
+
+static void write32(unsigned long addr, uint32_t value)
+{
+	*(volatile uint32_t*)(addr) = value;
+	asm volatile("sync");
+}
+
+static uint32_t read32(unsigned long addr)
+{
+	uint32_t value;
+	value = *(volatile uint32_t*)addr;
+	asm volatile("sync");
+	return value;
+}
+
+static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr)
+{
+	uint32_t base = flash->start[0];
+	uint32_t val=(cmd << 16) | cmd;
+	addr <<= 3;
+	write32(base + addr, val);
+	return addr;
+}
+
+static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
+{
+	uint32_t base = flash->start[0];
+	addr <<= 3;
+	return (uint16_t)read32(base + addr);
+}
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static void move64(uint64_t *src, uint64_t *dest)
+{
+	asm volatile("lfd  0, 0(3)\n\t" /* fpr0   =  *scr       */
+	 "stfd 0, 0(4)"         /* *dest  =  fpr0       */
+	 : : : "fr0" );         /* Clobbers fr0         */
+	return;
+}
+
+static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
+{
+	unsigned long start;
+	cfi_word status = 0;
+
+	status = cfi_read(flash, dest);
+	data &= status;
+
+	cfi_cmd(flash, 0x40, 0);
+	cfi_write(flash, data, dest);
+
+	udelay(10);
+	start = get_timer (0);
+	for(;;) {
+		status = cfi_read(flash, dest);
+		status &= CMD(0x80);
+		if(status == CMD(0x80))
+			break;
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			cfi_cmd(flash, 0xff, 0);
+			return 1;
+		}
+		udelay(1);
+	}
+	cfi_cmd(flash, 0xff, 0);
+
+	return 0;
+}
+
+static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
+{
+	ulong start;
+	cfi_word status = 0;
+
+	status = cfi_read(flash, dest);
+	if(status != CMD(0xffff)) return 2;
+
+	cfi_cmd(flash, 0xaa, 0x555);
+	cfi_cmd(flash, 0x55, 0x2aa);
+	cfi_cmd(flash, 0xa0, 0x555);
+
+	cfi_write(flash, data, dest);
+
+	udelay(10);
+	start = get_timer (0);
+	status = ~data;
+	while(status != data) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+			return 1;
+		status = cfi_read(flash, dest);
+		udelay(1);
+	}
+	return 0;
+}
+
+static __inline__ unsigned long get_msr(void)
+{
+	unsigned long msr;
+	__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
+	return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+	__asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+}
+
+int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	int i, s, l, rc;
+	cfi_word data;
+	uint8_t *t = (uint8_t*)&data;
+	unsigned long base = flash->start[0];
+	uint32_t msr;
+
+	if (flash->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	if (cnt == 0)
+		return 0;
+
+	addr -= base;
+
+	msr = get_msr();
+	set_msr(msr|MSR_FP);
+
+	wp = (addr & ~7);   /* get lower word aligned address */
+
+	if((addr-wp) != 0) {
+		data = cfi_read(flash, wp);
+		s = addr & 7;
+		l = ( cnt < (8-s) ) ? cnt : (8-s);
+		for(i = 0; i < l; i++)
+			t[s+i] = *src++;
+		if ((rc = write_dword(flash, wp, data)) != 0)
+			goto DONE;
+		wp += 8;
+		cnt -= l;
+	}
+
+	while (cnt >= 8) {
+		for (i = 0; i < 8; i++)
+			t[i] = *src++;
+		if ((rc = write_dword(flash, wp, data)) != 0)
+			goto DONE;
+		wp  += 8;
+		cnt -= 8;
+	}
+
+	if (cnt == 0) {
+		rc = 0;
+		goto DONE;
+	}
+
+	data = cfi_read(flash, wp);
+	for(i = 0; i < cnt; i++)
+		t[i] = *src++;
+	rc = write_dword(flash, wp, data);
+DONE:
+	set_msr(msr);
+	return rc;
+}
+
+static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
+{
+	int sa;
+	int flag;
+	ulong start, last, now;
+	cfi_word status;
+
+	flag = disable_interrupts();
+
+	sa = (flash->start[sect] - flash->start[0]);
+	write32(flash->start[sect], 0x00200020);
+	write32(flash->start[sect], 0x00d000d0);
+
+	if (flag)
+		enable_interrupts();
+
+	udelay(1000);
+	start = get_timer (0);
+	last  = start;
+
+	for (;;) {
+		status = cfi_read(flash, sa);
+		status &= CMD(0x80);
+		if (status == CMD(0x80))
+			break;
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			cfi_cmd(flash, 0xff, 0);
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+
+		if ((now - last) > 1000) {
+			serial_putc ('.');
+			last = now;
+		}
+		udelay(10);
+	}
+	cfi_cmd(flash, 0xff, 0);
+	return ERR_OK;
+}
+
+static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
+{
+	int sect;
+	int rc = ERR_OK;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (flash->protect[sect] == 0) {
+			rc = cfi_erase_oneblock(flash, sect);
+			if (rc != ERR_OK) break;
+		}
+	}
+	printf (" done\n");
+	return rc;
+}
+
+static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
+{
+	int sect;
+	cfi_word status;
+	int sa = -1;
+	int flag;
+	ulong start, last, now;
+
+	flag = disable_interrupts();
+
+	cfi_cmd(flash, 0xaa, 0x555);
+	cfi_cmd(flash, 0x55, 0x2aa);
+	cfi_cmd(flash, 0x80, 0x555);
+	cfi_cmd(flash, 0xaa, 0x555);
+	cfi_cmd(flash, 0x55, 0x2aa);
+	for ( sect = s_first; sect <= s_last; sect++) {
+		if (flash->protect[sect] == 0) {
+			sa = flash->start[sect] - flash->start[0];
+			write32(flash->start[sect], 0x00300030);
+		}
+	}
+	if (flag)
+		enable_interrupts();
+
+	if (sa < 0)
+		goto DONE;
+
+	udelay (1000);
+	start = get_timer (0);
+	last  = start;
+	for(;;) {
+		status = cfi_read(flash, sa);
+		if (status == CMD(0xffff))
+			break;
+
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+
+		if ((now - last) > 1000) {
+			serial_putc ('.');
+			last = now;
+		}
+		udelay(10);
+	}
+DONE:
+	cfi_cmd(flash, 0xf0, 0);
+
+	printf (" done\n");
+
+	return ERR_OK;
+}
+
+int flash_erase (flash_info_t *flash, int s_first, int s_last)
+{
+	int sect;
+	int prot;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (flash->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return ERR_NOT_ERASED;
+	}
+	if (flash->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return ERR_NOT_ERASED;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++)
+		if (flash->protect[sect]) prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+					                        prot);
+	else
+		printf ("\n");
+
+	return do_flash_erase(flash, s_first, s_last);
+}
+
+struct jedec_flash_info {
+	const uint16_t mfr_id;
+	const uint16_t dev_id;
+	const char *name;
+	const int DevSize;
+	const int InterfaceDesc;
+	const int NumEraseRegions;
+	const ulong regions[4];
+};
+
+#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
+
+#define SIZE_1MiB 20
+#define SIZE_2MiB 21
+#define SIZE_4MiB 22
+
+static const struct jedec_flash_info jedec_table[] = {
+	{
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV800T,
+		name: "AMD AM29LV800T",
+		DevSize: SIZE_1MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,15),
+			  ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV800B,
+		name: "AMD AM29LV800B",
+		DevSize: SIZE_1MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,15),
+		          ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV160T,
+		name: "AMD AM29LV160T",
+		DevSize: SIZE_2MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,31),
+		          ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV160B,
+		name: "AMD AM29LV160B",
+		DevSize: SIZE_2MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x04000,1),
+		          ERASEINFO(0x02000,2),
+			  ERASEINFO(0x08000,1),
+			  ERASEINFO(0x10000,31)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV320T,
+		name: "AMD AM29LV320T",
+		DevSize: SIZE_4MiB,
+		NumEraseRegions: 2,
+		regions: {ERASEINFO(0x10000,63),
+		          ERASEINFO(0x02000,8)
+		}
+
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV320B,
+		name: "AMD AM29LV320B",
+		DevSize: SIZE_4MiB,
+		NumEraseRegions: 2,
+		regions: {ERASEINFO(0x02000,8),
+		          ERASEINFO(0x10000,63)
+		}
+	}
+};
+
+static ulong cfi_init(uint32_t base,  flash_info_t *flash)
+{
+	int sector;
+	int block;
+	int block_count;
+	int offset = 0;
+	int reverse = 0;
+	int primary;
+	int mfr_id;
+	int dev_id;
+
+	flash->start[0] = base;
+	cfi_cmd(flash, 0xF0, 0);
+	cfi_cmd(flash, 0x98, 0);
+	if ( !( cfi_read_query(flash, 0x10) == 'Q' &&
+		cfi_read_query(flash, 0x11) == 'R' &&
+		cfi_read_query(flash, 0x12) == 'Y' )) {
+		cfi_cmd(flash, 0xff, 0);
+		return 0;
+	}
+
+	flash->size = 1 << cfi_read_query(flash, 0x27);
+	flash->size *= 4;
+	block_count = cfi_read_query(flash, 0x2c);
+	primary = cfi_read_query(flash, 0x15);
+	if ( cfi_read_query(flash, primary + 4) == 0x30)
+		reverse = (cfi_read_query(flash, 0x1) & 0x01);
+	else
+		reverse = (cfi_read_query(flash, primary+15) == 3);
+
+	flash->sector_count = 0;
+
+	for ( block = reverse ? block_count - 1	: 0;
+		      reverse ? block >= 0	: block < block_count;
+		      reverse ? block--		: block ++) {
+		int sector_size =
+			(cfi_read_query(flash, 0x2d + block*4+2) |
+			(cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8;
+		int sector_count =
+			(cfi_read_query(flash, 0x2d + block*4+0) |
+			(cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1;
+		for(sector = 0; sector < sector_count; sector++) {
+			flash->start[flash->sector_count++] = base + offset;
+			offset += sector_size * 4;
+		}
+	}
+	mfr_id = cfi_read_query(flash, 0x00);
+	dev_id = cfi_read_query(flash, 0x01);
+
+	cfi_cmd(flash, 0xff, 0);
+
+	flash->flash_id = (mfr_id << 16) | dev_id;
+
+	for (sector = 0; sector < flash->sector_count; sector++) {
+		write32(flash->start[sector], 0x00600060);
+		write32(flash->start[sector], 0x00d000d0);
+	}
+	cfi_cmd(flash, 0xff, 0);
+
+	for (sector = 0; sector < flash->sector_count; sector++)
+		flash->protect[sector] = 0;
+
+	do_flash_erase = cfi_erase;
+	write_dword = cfi_write_dword;
+
+	return flash->size;
+}
+
+static ulong jedec_init(unsigned long base, flash_info_t *flash)
+{
+	int i;
+	int block, block_count;
+	int sector, offset;
+	int mfr_id, dev_id;
+	flash->start[0] = base;
+	cfi_cmd(flash, 0xF0, 0x000);
+	cfi_cmd(flash, 0xAA, 0x555);
+	cfi_cmd(flash, 0x55, 0x2AA);
+	cfi_cmd(flash, 0x90, 0x555);
+	mfr_id = cfi_read_query(flash, 0x000);
+	dev_id = cfi_read_query(flash, 0x0001);
+	cfi_cmd(flash, 0xf0, 0x000);
+
+	for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) {
+		if((jedec_table[i].mfr_id == mfr_id) &&
+			(jedec_table[i].dev_id == dev_id)) {
+
+			flash->flash_id = (mfr_id << 16) | dev_id;
+			flash->size = 1 << jedec_table[0].DevSize;
+			flash->size *= 4;
+			block_count = jedec_table[i].NumEraseRegions;
+			offset = 0;
+			flash->sector_count = 0;
+			for (block = 0; block < block_count; block++) {
+				int sector_size = jedec_table[i].regions[block];
+				int sector_count = (sector_size & 0xff) + 1;
+				sector_size >>= 8;
+				for (sector=0; sector<sector_count; sector++) {
+					flash->start[flash->sector_count++] =
+						base + offset;
+					offset += sector_size * 4;
+				}
+			}
+			break;
+		}
+	}
+
+	for (sector = 0; sector < flash->sector_count; sector++)
+		flash->protect[sector] = 0;
+
+	do_flash_erase = jedec_erase;
+	write_dword = jedec_write_dword;
+
+	return flash->size;
+}
+
+inline void mtibat1u(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   530, %0" :: "r" (x));
+}
+
+inline void mtibat1l(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   531, %0" :: "r" (x));
+}
+
+inline void mtdbat1u(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   538, %0" :: "r" (x));
+}
+
+inline void mtdbat1l(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   539, %0" :: "r" (x));
+}
+
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+	unsigned int msr;
+
+	/* BAT1 */
+	CONFIG_WRITE_WORD(ERCR3, 0x0C00000C);
+	CONFIG_WRITE_WORD(ERCR4, 0x0800000C);
+	msr = get_msr();
+	set_msr(msr & ~(MSR_IR | MSR_DR));
+	mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	set_msr(msr);
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
+	if (!size)
+		size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN)
+		printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+
+	return size;
+}
+
+void flash_print_info  (flash_info_t *flash)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *p;
+
+	if (flash->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		flash_init();
+	}
+
+	if (flash->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (((flash->flash_id) >> 16) & 0xff) {
+	case 0x01:
+		printf ("AMD ");
+		break;
+	case 0x04:
+		printf("FUJITSU ");
+		break;
+	case 0x20:
+		printf("STM ");
+		break;
+	case 0xBF:
+		printf("SST ");
+		break;
+	case 0x89:
+	case 0xB0:
+		printf("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch ((flash->flash_id) & 0xffff) {
+	case (uint16_t)AMD_ID_LV800T:
+		printf ("AM29LV800T\n");
+		break;
+	case (uint16_t)AMD_ID_LV800B:
+		printf ("AM29LV800B\n");
+		break;
+	case (uint16_t)AMD_ID_LV160T:
+		printf ("AM29LV160T\n");
+		break;
+	case (uint16_t)AMD_ID_LV160B:
+		printf ("AM29LV160B\n");
+		break;
+	case (uint16_t)AMD_ID_LV320T:
+		printf ("AM29LV320T\n");
+		break;
+	case (uint16_t)AMD_ID_LV320B:
+		printf ("AM29LV320B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F800C3T:
+		printf ("28F800C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F800C3B:
+		printf ("28F800C3B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F160C3T:
+		printf ("28F160C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F160C3B:
+		printf ("28F160C3B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F320C3T:
+		printf ("28F320C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F320C3B:
+		printf ("28F320C3B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F640C3T:
+		printf ("28F640C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F640C3B:
+		printf ("28F640C3B\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if (flash->size >= (1 << 20)) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+				flash->size >> 20, flash->sector_count);
+	} else {
+		printf ("  Size: %ld kB in %d Sectors\n",
+				flash->size >> 10, flash->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < flash->sector_count; ++i) {
+		/* Check if whole sector is erased*/
+		if (i != (flash->sector_count-1))
+			size = flash->start[i+1] - flash->start[i];
+		else
+			size = flash->start[0] + flash->size - flash->start[i];
+
+		erased = 1;
+		p = (volatile unsigned long *)flash->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*p++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s%s",
+			flash->start[i],
+			erased ? " E" : "  ",
+			flash->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c
new file mode 100755
index 0000000..0b81fc0
--- /dev/null
+++ b/board/etin/debris/phantom.c
@@ -0,0 +1,310 @@
+/*
+ * board/eva/phantom.c
+ *
+ * Phantom RTC device driver for EVA
+ *
+ * Author: Sangmoon Kim
+ *         dogoil@etinsys.com
+ *
+ * Copyright 2002 Etinsys Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+#define RTC_BASE (CFG_NVRAM_BASE_ADDR + 0x7fff8)
+
+#define RTC_YEAR                ( RTC_BASE + 7 )
+#define RTC_MONTH               ( RTC_BASE + 6 )
+#define RTC_DAY_OF_MONTH        ( RTC_BASE + 5 )
+#define RTC_DAY_OF_WEEK         ( RTC_BASE + 4 )
+#define RTC_HOURS               ( RTC_BASE + 3 )
+#define RTC_MINUTES             ( RTC_BASE + 2 )
+#define RTC_SECONDS             ( RTC_BASE + 1 )
+#define RTC_CENTURY             ( RTC_BASE + 0 )
+
+#define RTC_CONTROLA            RTC_CENTURY
+#define RTC_CONTROLB            RTC_SECONDS
+#define RTC_CONTROLC            RTC_DAY_OF_WEEK
+
+#define RTC_CA_WRITE            0x80
+#define RTC_CA_READ             0x40
+
+#define RTC_CB_OSC_DISABLE      0x80
+
+#define RTC_CC_BATTERY_FLAG     0x80
+#define RTC_CC_FREQ_TEST        0x40
+
+
+static int phantom_flag = -1;
+static int century_flag = -1;
+
+static uchar rtc_read(unsigned int addr)
+{
+	return *(volatile unsigned char *)(addr);
+}
+
+static void rtc_write(unsigned int addr, uchar val)
+{
+	*(volatile unsigned char *)(addr) = val;
+}
+
+static unsigned char phantom_rtc_sequence[] = {
+	0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
+};
+
+static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8])
+{
+	int i, j;
+	unsigned char v;
+	unsigned char save = rtc_read(addr);
+
+	for (j = 0; j < 8; j++) {
+		v = phantom_rtc_sequence[j];
+		for (i = 0; i < 8; i++) {
+			rtc_write(addr, v & 1);
+			v >>= 1;
+		}
+	}
+	for (j = 0; j < 8; j++) {
+		v = 0;
+		for (i = 0; i < 8; i++) {
+			if(rtc_read(addr) & 1)
+				v |= 1 << i;
+		}
+		rtc[j] = v;
+	}
+	rtc_write(addr, save);
+	return rtc;
+}
+
+static void phantom_rtc_write(int addr, unsigned char rtc[8])
+{
+	int i, j;
+	unsigned char v;
+	unsigned char save = rtc_read(addr);
+	for (j = 0; j < 8; j++) {
+		v = phantom_rtc_sequence[j];
+		for (i = 0; i < 8; i++) {
+			rtc_write(addr, v & 1);
+			v >>= 1;
+		}
+	}
+	for (j = 0; j < 8; j++) {
+		v = rtc[j];
+		for (i = 0; i < 8; i++) {
+			rtc_write(addr, v & 1);
+			v >>= 1;
+		}
+	}
+	rtc_write(addr, save);
+}
+
+static int get_phantom_flag(void)
+{
+	int i;
+	unsigned char rtc[8];
+
+	phantom_rtc_read(RTC_BASE, rtc);
+
+	for(i = 1; i < 8; i++) {
+		if (rtc[i] != rtc[0])
+			return 1;
+	}
+	return 0;
+}
+
+void rtc_reset(void)
+{
+	if (phantom_flag < 0)
+		phantom_flag = get_phantom_flag();
+
+	if (phantom_flag) {
+		unsigned char rtc[8];
+		phantom_rtc_read(RTC_BASE, rtc);
+		if(rtc[4] & 0x30) {
+			printf( "real-time-clock was stopped. Now starting...\n" );
+			rtc[4] &= 0x07;
+			phantom_rtc_write(RTC_BASE, rtc);
+		}
+	} else {
+		uchar reg_a, reg_b, reg_c;
+		reg_a = rtc_read( RTC_CONTROLA );
+		reg_b = rtc_read( RTC_CONTROLB );
+
+		if ( reg_b & RTC_CB_OSC_DISABLE )
+		{
+			printf( "real-time-clock was stopped. Now starting...\n" );
+			reg_a |= RTC_CA_WRITE;
+			reg_b &= ~RTC_CB_OSC_DISABLE;
+			rtc_write( RTC_CONTROLA, reg_a );
+			rtc_write( RTC_CONTROLB, reg_b );
+		}
+
+		/* make sure read/write clock register bits are cleared */
+		reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
+		rtc_write( RTC_CONTROLA, reg_a );
+
+		reg_c = rtc_read( RTC_CONTROLC );
+		if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
+			printf( "RTC battery low. Clock setting may not be reliable.\n");
+	}
+}
+
+inline unsigned bcd2bin (uchar n)
+{
+	return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+inline unsigned char bin2bcd (unsigned int n)
+{
+	return (((n / 10) << 4) | (n % 10));
+}
+
+static int get_century_flag(void)
+{
+	int flag = 0;
+	int bcd, century;
+	bcd = rtc_read( RTC_CENTURY );
+	century = bcd2bin( bcd & 0x3F );
+	rtc_write( RTC_CENTURY, bin2bcd(century+1));
+	if (bcd == rtc_read( RTC_CENTURY ))
+		flag = 1;
+	rtc_write( RTC_CENTURY, bcd);
+	return flag;
+}
+
+void rtc_get( struct rtc_time *tmp)
+{
+	if (phantom_flag < 0)
+		phantom_flag = get_phantom_flag();
+
+	if (phantom_flag)
+	{
+		unsigned char rtc[8];
+
+		phantom_rtc_read(RTC_BASE, rtc);
+
+		tmp->tm_sec	= bcd2bin(rtc[1] & 0x7f);
+		tmp->tm_min	= bcd2bin(rtc[2] & 0x7f);
+		tmp->tm_hour	= bcd2bin(rtc[3] & 0x1f);
+		tmp->tm_wday	= bcd2bin(rtc[4] & 0x7);
+		tmp->tm_mday	= bcd2bin(rtc[5] & 0x3f);
+		tmp->tm_mon	= bcd2bin(rtc[6] & 0x1f);
+		tmp->tm_year	= bcd2bin(rtc[7]) + 1900;
+		tmp->tm_yday = 0;
+		tmp->tm_isdst = 0;
+
+		if( (rtc[3] & 0x80)  && (rtc[3] & 0x40) ) tmp->tm_hour += 12;
+		if (tmp->tm_year < 1970) tmp->tm_year += 100;
+	} else {
+		uchar sec, min, hour;
+		uchar mday, wday, mon, year;
+
+		int century;
+
+		uchar reg_a;
+
+		if (century_flag < 0)
+			century_flag = get_century_flag();
+
+		reg_a = rtc_read( RTC_CONTROLA );
+		/* lock clock registers for read */
+		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
+
+		sec     = rtc_read( RTC_SECONDS );
+		min     = rtc_read( RTC_MINUTES );
+		hour    = rtc_read( RTC_HOURS );
+		mday    = rtc_read( RTC_DAY_OF_MONTH );
+		wday    = rtc_read( RTC_DAY_OF_WEEK );
+		mon     = rtc_read( RTC_MONTH );
+		year    = rtc_read( RTC_YEAR );
+		century = rtc_read( RTC_CENTURY );
+
+		/* unlock clock registers after read */
+		rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
+
+		tmp->tm_sec  = bcd2bin( sec  & 0x7F );
+		tmp->tm_min  = bcd2bin( min  & 0x7F );
+		tmp->tm_hour = bcd2bin( hour & 0x3F );
+		tmp->tm_mday = bcd2bin( mday & 0x3F );
+		tmp->tm_mon  = bcd2bin( mon & 0x1F );
+		tmp->tm_wday = bcd2bin( wday & 0x07 );
+
+		if (century_flag) {
+			tmp->tm_year = bcd2bin( year ) +
+				( bcd2bin( century & 0x3F ) * 100 );
+		} else {
+			tmp->tm_year = bcd2bin( year ) + 1900;
+			if (tmp->tm_year < 1970) tmp->tm_year += 100;
+		}
+
+		tmp->tm_yday = 0;
+		tmp->tm_isdst= 0;
+	}
+}
+
+void rtc_set( struct rtc_time *tmp )
+{
+	if (phantom_flag < 0)
+		phantom_flag = get_phantom_flag();
+
+	if (phantom_flag) {
+		uint year;
+		unsigned char rtc[8];
+
+		year = tmp->tm_year;
+		year -= (year < 2000) ? 1900 : 2000;
+
+		rtc[0] = bin2bcd(0);
+		rtc[1] = bin2bcd(tmp->tm_sec);
+		rtc[2] = bin2bcd(tmp->tm_min);
+		rtc[3] = bin2bcd(tmp->tm_hour);
+		rtc[4] = bin2bcd(tmp->tm_wday);
+		rtc[5] = bin2bcd(tmp->tm_mday);
+		rtc[6] = bin2bcd(tmp->tm_mon);
+		rtc[7] = bin2bcd(year);
+
+		phantom_rtc_write(RTC_BASE, rtc);
+	} else {
+		uchar reg_a;
+		if (century_flag < 0)
+			century_flag = get_century_flag();
+
+		/* lock clock registers for write */
+		reg_a = rtc_read( RTC_CONTROLA );
+		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
+
+		rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
+
+		rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
+		rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
+		rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
+		rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
+		rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
+
+		/* break year up into century and year in century */
+		if (century_flag) {
+			rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
+			rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
+			reg_a &= 0xc0;
+			reg_a |= bin2bcd( tmp->tm_year / 100 );
+		} else {
+			rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year -
+				((tmp->tm_year < 2000) ? 1900 : 2000)));
+		}
+
+		/* unlock clock registers after read */
+		rtc_write( RTC_CONTROLA, ( reg_a  & ~RTC_CA_WRITE ));
+	}
+}
+
+#endif
diff --git a/board/etin/debris/speed.h b/board/etin/debris/speed.h
new file mode 100755
index 0000000..b66393b
--- /dev/null
+++ b/board/etin/debris/speed.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK	      		CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */
diff --git a/board/etin/debris/u-boot.lds b/board/etin/debris/u-boot.lds
new file mode 100755
index 0000000..c742bcd
--- /dev/null
+++ b/board/etin/debris/u-boot.lds
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/etx094/Makefile b/board/etx094/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/etx094/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/etx094/config.mk b/board/etx094/config.mk
new file mode 100755
index 0000000..655c2db
--- /dev/null
+++ b/board/etx094/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# ETX_094 Boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c
new file mode 100755
index 0000000..dba3c11
--- /dev/null
+++ b/board/etx094/etx094.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+static void read_hw_vers (void);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+
+	/* single read   (offset 0x00 in upm ram) */
+
+	0xEECEFC24, 0x100DFC24, 0xE02FBC04, 0x01AA7C04,
+	0x1FB5FC00, 0xFFFFFC05, _NOT_USED_, _NOT_USED_,
+
+	/* burst read    (offset 0x08 in upm ram) */
+
+	0xEECEFC24, 0x100DFC24, 0xE0FFBC04, 0x10FF7C04,
+	0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC00, 0xFFFFFC00,
+	0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write  (offset 0x18 in upm ram) */
+
+	0xEECEFC24, 0x100DFC24, 0xE02BBC04, 0x01A27C00,
+	0xEFAAFC04, 0x1FB5FC05, _NOT_USED_, _NOT_USED_,
+
+	/* burst write   (offset 0x20 in upm ram) */
+
+	0xEECEFC24, 0x103DFC24, 0xE0FBBC00, 0x10F77C00,
+	0xF0FFFC00, 0xF0FFFC00, 0xF0FFFC04, 0xFFFFFC05,
+
+	/* init part1      (offset 0x28 in upm ram) */
+
+	0xEFFAFC3C, 0x1FF4FC34, 0xEFFCBC34, 0x1FFC3C34,
+	0xFFFC3C35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* refresh   (offset 0x30 in upm ram) */
+
+	0xEFFEBC0C, 0x1FFD7C04, 0xFFFFFC04, 0xFFFFFC05,
+
+	/* init part2     (offset 0x34 in upm ram) */
+
+	0xFFFEBC04, 0xEFFC3CB4, 0x1FFC3C34, 0xFFFC3C34,
+	0xFFFC3C34, 0xEFE83CB4, 0x1FB57C35, _NOT_USED_,
+
+	/* exception     (offset 0x3C in upm ram) */
+
+	0xFFFFFC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ETX ID string (ETX_xxx...)
+ *
+ * Return 1 always.
+ */
+
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char *s = getenv ("serial#");
+	char *e;
+
+	puts ("Board: ");
+
+#ifdef SB_ETX094
+	gd->board_type = 0; /* 0 = 2SDRAM-Device */
+#else
+	gd->board_type = 1; /* 1 = 1SDRAM-Device */
+#endif
+
+	if (!s || strncmp (s, "ETX_", 4)) {
+		puts ("### No HW ID - assuming ETX_094\n");
+		read_hw_vers ();
+		return (0);
+	}
+
+	for (e = s; *e; ++e) {
+		if (*e == ' ')
+			break;
+	}
+
+	for (; s < e; ++s) {
+		putc (*s);
+	}
+	putc ('\n');
+
+	read_hw_vers ();
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0, size_b1, size8, size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_1BK_4K;	/* MPTPR_PTP_DIV32 0x0200 */
+
+	/* A3(SDRAM)=0      => Bursttype = Sequential
+	 * A2-A0(SDRAM)=010 => Burst length = 4
+	 * A4-A6(SDRAM)=010 => CasLat=2
+	 */
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or2 = CFG_OR2_PRELIM;
+	memctl->memc_br2 = CFG_BR2_PRELIM;
+
+	if (board_type == 0) {	/* "L" type boards have only one bank SDRAM */
+		memctl->memc_or3 = CFG_OR3_PRELIM;
+		memctl->memc_br3 = CFG_BR3_PRELIM;
+	}
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004128;	/* SDRAM bank 0 (CS2) - Init Part 1 */
+	memctl->memc_mcr = 0x80004734;	/* SDRAM bank 0 (CS2) - Init Part 2 */
+	udelay (1);
+
+	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
+		memctl->memc_mcr = 0x80006128;	/* SDRAM bank 1 (CS3) - Init Part 1 */
+		memctl->memc_mcr = 0x80006734;	/* SDRAM bank 1 (CS3) - Init Part 2 */
+		udelay (1);
+	}
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {					/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
+		/*
+		 * Check Bank 1 Memory Size
+		 * use current column settings
+		 * [9 column SDRAM may also be used in 8 column mode,
+		 *  but then only half the real size will be used.]
+		 */
+		size_b1 =
+				dram_size (memctl->memc_mamr, (long *) SDRAM_BASE3_PRELIM,
+						   SDRAM_MAX_SIZE);
+/*	debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);	*/
+	} else {
+		size_b1 = 0;
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;	/*DIV16 */
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
+
+		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_br3 =
+			(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b0 > 0) {
+			/*
+			 * Position Bank 0 immediately above Bank 1
+			 */
+			memctl->memc_or2 =
+				((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+			memctl->memc_br2 =
+				((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+				+ size_b1;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 0
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br2 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+
+	} else {			/* SDRAM Bank 0 is bigger - map first   */
+
+		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_br2 =
+				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b1 > 0) {
+			/*
+			 * Position Bank 1 immediately above Bank 0
+			 */
+			memctl->memc_or3 =
+					((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+			memctl->memc_br3 =
+					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					+ size_b0;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 1
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br3 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+	}
+
+	udelay (10000);
+
+	return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* HW-ID Table (Bits: 2^9;2^7;2^5) */
+#define HW_ID_0 0x0000
+#define HW_ID_1 0x0020
+#define HW_ID_2 0x0080
+#define HW_ID_3 0x00a0
+#define HW_ID_4 0x0200
+#define HW_ID_5 0x0220
+#define HW_ID_6 0x0280
+#define HW_ID_7 0x02a0
+
+void read_hw_vers ()
+{
+	unsigned short rd_msk = 0x02A0;
+
+	/* HW-ID pin-definition */
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	immr->im_ioport.iop_pddir &= ~(rd_msk);
+	immr->im_ioport.iop_pdpar &= ~(rd_msk);
+
+	/* debug printf("State of PD: %x\n",immr->im_ioport.iop_pddat); */
+
+	/* Check the HW-ID */
+	printf ("HW-Version: ");
+	switch (immr->im_ioport.iop_pddat & rd_msk) {
+	case HW_ID_0:
+		printf ("V0.1 - V0.3 / W97238-Q3162-A1-1-2\n");
+		break;
+	case HW_ID_1:
+		printf ("V0.9 / W50037-Q1-D6-1\n");
+		break;
+	case HW_ID_2:
+		printf ("NOT USED - assuming ID#2\n");
+		break;
+	case HW_ID_3:
+		printf ("NOT USED - assuming ID#3\n");
+		break;
+	case HW_ID_4:
+		printf ("NOT USED - assuming ID#4\n");
+		break;
+	case HW_ID_5:
+		printf ("NOT USED - assuming ID#5\n");
+		break;
+	case HW_ID_6:
+		printf ("NOT USED - assuming ID#6\n");
+		break;
+	case HW_ID_7:
+		printf ("NOT USED - assuming ID#7\n");
+		break;
+	default:
+		printf ("###Error###\n");
+		break;
+	}
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/etx094/flash.c b/board/etx094/flash.c
new file mode 100755
index 0000000..98a7c0c
--- /dev/null
+++ b/board/etx094/flash.c
@@ -0,0 +1,744 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+#ifdef CONFIG_FLASH_16BIT
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */
+#else
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+#endif
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+#ifdef CONFIG_FLASH_16BIT
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V | BR_PS_16;
+#else
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V;
+#endif
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00002000);
+		}
+		return;
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+#ifdef CONFIG_FLASH_16BIT
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+#else
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+#endif
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_SST200A:	printf ("39xF200A (2M = 128K x 16)\n");
+				break;
+	case FLASH_SST400A:	printf ("39xF400A (4M = 256K x 16)\n");
+				break;
+	case FLASH_SST800A:	printf ("39xF800A (8M = 512K x 16)\n");
+				break;
+	case FLASH_STM800AB:	printf ("M29W800AB (8M = 512K x 16)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+#ifdef CONFIG_FLASH_16BIT
+	vu_short *s_addr = (vu_short*)addr;
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x0090;
+	value = s_addr[0];
+	value = value|(value<<16);
+#else
+	addr[0x5555] = 0x00AA00AA;
+	addr[0x2AAA] = 0x00550055;
+	addr[0x5555] = 0x00900090;
+	value = addr[0];
+#endif
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+#ifdef CONFIG_FLASH_16BIT
+	value = s_addr[1];
+	value = value|(value<<16);
+#else
+	value = addr[1];			/* device ID		*/
+#endif
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+#ifdef CONFIG_FLASH_16BIT
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MB */
+#else
+		info->sector_count = 19;
+		info->size = 0x00200000;	/* => 2 MB	*/
+#endif
+		break;
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+#ifdef CONFIG_FLASH_16BIT
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MB	*/
+#else
+		info->sector_count = 35;
+		info->size = 0x00400000;	/* => 4 MB	*/
+#endif
+
+		break;
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	case SST_ID_xF200A:
+		info->flash_id += FLASH_SST200A;
+		info->sector_count = 64;	/* 39xF200A ID ( 2M = 128K x 16	) */
+		info->size = 0x00080000;
+		break;
+	case SST_ID_xF400A:
+		info->flash_id += FLASH_SST400A;
+		info->sector_count = 128;	/* 39xF400A ID ( 4M = 256K x 16	) */
+		info->size = 0x00100000;
+		break;
+	case SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 256;	/* 39xF800A ID ( 8M = 512K x 16	) */
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case STM_ID_x800AB:
+		info->flash_id += FLASH_STM800AB;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00002000);
+		}
+	} else {	/* AMD and Fujitsu types */
+		/* set up sector start address table */
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+#ifdef CONFIG_FLASH_16BIT
+
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+#else
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00020000) - 0x00060000;
+#endif
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+
+		/* check for protected sectors */
+		for (i = 0; i < info->sector_count; i++) {
+			/* read sector protection at sector address:
+			 * (A7 .. A0) = 0x02
+			 * D0 = 1 if protected
+			 */
+#ifdef CONFIG_FLASH_16BIT
+			s_addr = (volatile unsigned short *)(info->start[i]);
+			info->protect[i] = s_addr[2] & 1;
+#else
+			addr = (volatile unsigned long *)(info->start[i]);
+			info->protect[i] = addr[2] & 1;
+#endif
+		}
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+#ifdef CONFIG_FLASH_16BIT
+		s_addr = (volatile unsigned short *)(info->start[0]);
+		*s_addr = 0x00F0;	/* reset bank */
+#else
+		addr = (volatile unsigned long *)info->start[0];
+		*addr = 0x00F000F0;	/* reset bank */
+#endif
+
+	}
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect;
+	ulong start, now, last;
+#ifdef CONFIG_FLASH_16BIT
+	vu_short *s_addr = (vu_short*)addr;
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+/*#ifndef CONFIG_FLASH_16BIT
+	ulong type;
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return;
+	}
+#endif*/
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+#ifdef CONFIG_FLASH_16BIT
+			vu_short *s_sect_addr = (vu_short*)(info->start[sect]);
+#else
+			vu_long	*sect_addr = (vu_long*)(info->start[sect]);
+#endif
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+#ifdef CONFIG_FLASH_16BIT
+
+			/*printf("\ns_sect_addr=%x",s_sect_addr);*/
+			s_addr[0x5555] = 0x00AA;
+			s_addr[0x2AAA] = 0x0055;
+			s_addr[0x5555] = 0x0080;
+			s_addr[0x5555] = 0x00AA;
+			s_addr[0x2AAA] = 0x0055;
+			s_sect_addr[0] = 0x0030;
+#else
+			addr[0x5555] = 0x00AA00AA;
+			addr[0x2AAA] = 0x00550055;
+			addr[0x5555] = 0x00800080;
+			addr[0x5555] = 0x00AA00AA;
+			addr[0x2AAA] = 0x00550055;
+			sect_addr[0] = 0x00300030;
+#endif
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+#ifdef CONFIG_FLASH_16BIT
+			while ((s_sect_addr[0] & 0x0080) != 0x0080) {
+#else
+			while ((sect_addr[0] & 0x00800080) != 0x00800080) {
+#endif
+				if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+		}
+	}
+
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#ifdef CONFIG_FLASH_16BIT
+	s_addr[0] = 0x00F0;	/* reset bank */
+#else
+	addr[0] = 0x00F000F0;	/* reset bank */
+#endif
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+
+#ifdef CONFIG_FLASH_16BIT
+	vu_short high_data;
+	vu_short low_data;
+	vu_short *s_addr = (vu_short*)addr;
+#endif
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+#ifdef CONFIG_FLASH_16BIT
+	/* Write the 16 higher-bits */
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	high_data = ((data>>16) & 0x0000ffff);
+
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x00A0;
+
+	*((vu_short *)dest) = high_data;
+
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+
+	/* Write the 16 lower-bits */
+#endif
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+#ifdef CONFIG_FLASH_16BIT
+	dest += 0x2;
+	low_data = (data & 0x0000ffff);
+
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x00A0;
+	*((vu_short *)dest) = low_data;
+
+#else
+	addr[0x5555] = 0x00AA00AA;
+	addr[0x2AAA] = 0x00550055;
+	addr[0x5555] = 0x00A000A0;
+	*((vu_long *)dest) = data;
+#endif
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+#ifdef CONFIG_FLASH_16BIT
+	while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
+#else
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+#endif
+
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds
new file mode 100755
index 0000000..c50db8f
--- /dev/null
+++ b/board/etx094/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    cpu/mpc8xx/traps.o	(.text)
+    cpu/mpc8xx/interrupts.o	(.text)
+    cpu/mpc8xx/serial.o	(.text)
+    cpu/mpc8xx/cpu_init.o	(.text)
+    cpu/mpc8xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/etx094/u-boot.lds.debug b/board/etx094/u-boot.lds.debug
new file mode 100755
index 0000000..e4d8b10
--- /dev/null
+++ b/board/etx094/u-boot.lds.debug
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    cpu/mpc8xx/traps.o	(.text)
+    cpu/mpc8xx/interrupts.o	(.text)
+    cpu/mpc8xx/cpu.o	(.text)
+    cpu/mpc8xx/cpu_init.o	(.text)
+    cpu/mpc8xx/speed.o	(.text)
+    cpu/mpc8xx/serial.o	(.text)
+    lib_ppc/extable.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/string.o	(.text)
+    lib_generic/crc32.o		(.text)
+    common/dlmalloc.o	(.text)
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/evb4510/Makefile b/board/evb4510/Makefile
new file mode 100755
index 0000000..10850a9
--- /dev/null
+++ b/board/evb4510/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= evb4510.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/evb4510/config.mk b/board/evb4510/config.mk
new file mode 100755
index 0000000..4d1a019
--- /dev/null
+++ b/board/evb4510/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+# Curt Brune <curt@cucy.com>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x007d0000
diff --git a/board/evb4510/evb4510.c b/board/evb4510/evb4510.c
new file mode 100755
index 0000000..0008e5a
--- /dev/null
+++ b/board/evb4510/evb4510.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <command.h>
+
+#ifdef CONFIG_EVB4510
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	icache_enable();
+
+	/* address for the kernel command line */
+	gd->bd->bi_boot_params = 0x800;
+
+	/* enable board LEDs for output */
+	PUT_REG( REG_IOPDATA, 0x0);
+	PUT_REG( REG_IOPMODE, 0xFFFF);
+	PUT_REG( REG_IOPDATA, 0xFF);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+#if CONFIG_NR_DRAM_BANKS == 2
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+#endif
+	return 0;
+}
+
+#endif
diff --git a/board/evb4510/flash.c b/board/evb4510/flash.c
new file mode 100755
index 0000000..aff92f9
--- /dev/null
+++ b/board/evb4510/flash.c
@@ -0,0 +1,539 @@
+/*
+ *
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <flash.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+typedef enum {
+	FLASH_DEV_U9_512KB = 0,
+	FLASH_DEV_U7_2MB = 1
+} FLASH_DEV;
+
+#define FLASH_DQ7		(0x80)
+#define FLASH_DQ5		(0x20)
+
+#define PROG_ADDR		(0xAAA)
+#define SETUP_ADDR		(0xAAA)
+#define ID_ADDR			(0xAAA)
+#define UNLOCK_ADDR1		(0xAAA)
+#define UNLOCK_ADDR2		(0x555)
+
+#define UNLOCK_CMD1		(0xAA)
+#define UNLOCK_CMD2		(0x55)
+#define ERASE_SUSPEND_CMD	(0xB0)
+#define ERASE_RESUME_CMD	(0x30)
+#define RESET_CMD		(0xF0)
+#define ID_CMD			(0x90)
+#define SELECT_CMD		(0x90)
+#define CHIPERASE_CMD		(0x10)
+#define BYPASS_CMD		(0x20)
+#define SECERASE_CMD		(0x30)
+#define PROG_CMD		(0xa0)
+#define SETUP_CMD		(0x80)
+
+#if 0
+#define WRITE_UNLOCK(addr) { \
+	PUT__U8( addr + UNLOCK_ADDR1, UNLOCK_CMD1); \
+	PUT__U8( addr + UNLOCK_ADDR2, UNLOCK_CMD2); \
+}
+
+/* auto select command */
+#define CMD_ID(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, ID_CMD); \
+}
+
+#define CMD_RESET(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, RESET_CMD); \
+}
+
+#define CMD_ERASE_SEC(base, addr) WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+	WRITE_UNLOCK(base); \
+	PUT__U8( addr, SECERASE_CMD);
+
+#define CMD_ERASE_CHIP(base) WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+	WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, CHIPERASE_CMD);
+
+/* prepare for bypass programming */
+#define CMD_UNLOCK_BYPASS(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, 0x20); \
+}
+
+/* terminate bypass programming */
+#define CMD_BYPASS_RESET(addr) { \
+	PUT__U8(addr, 0x90); \
+	PUT__U8(addr, 0x00); \
+}
+#endif
+
+inline static void FLASH_CMD_UNLOCK (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		PUT__U8 (base + 0xAAA, 0xAA);
+		PUT__U8 (base + 0x555, 0x55);
+		break;
+	case FLASH_DEV_U9_512KB:
+		PUT__U8 (base + 0x555, 0xAA);
+		PUT__U8 (base + 0x2AA, 0x55);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_SELECT (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SELECT_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SELECT_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_RESET (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, RESET_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, RESET_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_ERASE_SEC (FLASH_DEV dev, u32 base, u32 addr)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (addr, SECERASE_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (addr, SECERASE_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_ERASE_CHIP (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base, CHIPERASE_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base, CHIPERASE_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_UNLOCK_BYPASS (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, BYPASS_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, BYPASS_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_BYPASS_RESET (FLASH_DEV dev, u32 base)
+{
+	PUT__U8 (base, SELECT_CMD);
+	PUT__U8 (base, 0x0);
+}
+
+/* poll for flash command completion */
+static u16 _flash_poll (FLASH_DEV dev, u32 addr, u16 data, ulong timeOut)
+{
+	u32 done = 0;
+	ulong t0;
+
+	u16 error = 0;
+	volatile u16 flashData;
+
+	data = data & 0xFF;
+	t0 = get_timer (0);
+	while (get_timer (t0) < timeOut) {
+		/*	for( i = 0; i < POLL_LOOPS; i++) { */
+		/*  Read the Data */
+		flashData = GET__U8 (addr);
+
+		/*  FLASH_DQ7 = Data? */
+		if ((flashData & FLASH_DQ7) == (data & FLASH_DQ7)) {
+			done = 1;
+			break;
+		}
+
+		/*  Check Timeout (FLASH_DQ5==1) */
+		if (flashData & FLASH_DQ5) {
+			/*  Read the Data */
+			flashData = GET__U8 (addr);
+
+			/*  FLASH_DQ7 = Data? */
+			if (!((flashData & FLASH_DQ7) == (data & FLASH_DQ7))) {
+				printf ("_flash_poll(): FLASH_DQ7 & flashData not equal to write value\n");
+				error = ERR_PROG_ERROR;
+			}
+			FLASH_CMD_RESET (dev, addr);
+			done = 1;
+			break;
+		}
+		/*  spin delay */
+		udelay (10);
+	}
+
+
+	/*  error update */
+	if (!done) {
+		printf ("_flash_poll(): Timeout\n");
+		error = ERR_TIMOUT;
+	}
+
+	/*  Check the data */
+	if (!error) {
+		/*  Read the Data */
+		flashData = GET__U8 (addr);
+		if (flashData != data) {
+			error = ERR_PROG_ERROR;
+			printf ("_flash_poll(): flashData(0x%04x) not equal to data(0x%04x)\n",
+				flashData, data);
+		}
+	}
+
+	return error;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int _flash_check_protection (flash_info_t * info, int s_first, int s_last)
+{
+	int sect, prot = 0;
+
+	for (sect = s_first; sect <= s_last; sect++)
+		if (info->protect[sect]) {
+			printf ("  Flash sector %d protected.\n", sect);
+			prot++;
+		}
+	return prot;
+}
+
+static int _detectFlash (FLASH_DEV dev, u32 base, u8 venId, u8 devId)
+{
+
+	u32 baseAddr = base | CACHE_DISABLE_MASK;
+	u8 vendorId, deviceId;
+
+	/*	printf(__FUNCTION__"(): detecting flash @ 0x%08x\n", base); */
+
+	/* Send auto select command and read manufacturer info */
+	FLASH_CMD_SELECT (dev, baseAddr);
+	vendorId = GET__U8 (baseAddr);
+	FLASH_CMD_RESET (dev, baseAddr);
+
+	/* Send auto select command and read device info */
+	FLASH_CMD_SELECT (dev, baseAddr);
+
+	if (dev == FLASH_DEV_U7_2MB) {
+		deviceId = GET__U8 (baseAddr + 2);
+	} else if (dev == FLASH_DEV_U9_512KB) {
+		deviceId = GET__U8 (baseAddr + 1);
+	} else {
+		return 0;
+	}
+
+	FLASH_CMD_RESET (dev, baseAddr);
+
+	/* printf (__FUNCTION__"(): found vendorId 0x%04x, deviceId 0x%04x\n",
+		vendorId, deviceId);
+	 */
+
+	return (vendorId == venId) && (deviceId == devId);
+
+}
+
+/******************************************************************************
+ *
+ * Public u-boot interface functions below
+ *
+ *****************************************************************************/
+
+/***************************************************************************
+ *
+ * Flash initialization
+ *
+ * This board has two banks of flash, but the base addresses depend on
+ * how the board is jumpered.
+ *
+ * The two flash types are:
+ *
+ *   AMD Am29LV160DB (2MB) sectors layout 16KB, 2x8KB, 32KB, 31x64KB
+ *
+ *   AMD Am29LV040B  (512KB)  sectors: 8x64KB
+ *****************************************************************************/
+
+unsigned long flash_init (void)
+{
+	flash_info_t *info;
+	u16 i;
+	u32 flashtest;
+	s16 amd160 = -1;
+	u32 amd160base = 0;
+
+#if CFG_MAX_FLASH_BANKS == 2
+	s16 amd040 = -1;
+	u32 amd040base = 0;
+#endif
+
+	/* configure PHYS_FLASH_1 */
+	if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_1, 0x1, 0x49)) {
+		amd160 = 0;
+		amd160base = PHYS_FLASH_1;
+#if CFG_MAX_FLASH_BANKS == 1
+	}
+#else
+		if (_detectFlash
+		    (FLASH_DEV_U9_512KB, PHYS_FLASH_2, 0x1, 0x4F)) {
+			amd040 = 1;
+			amd040base = PHYS_FLASH_2;
+		} else {
+			printf (__FUNCTION__
+				"(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+				PHYS_FLASH_2);
+		}
+	} else if (_detectFlash (FLASH_DEV_U9_512KB, PHYS_FLASH_1, 0x1, 0x4F)) {
+		amd040 = 0;
+		amd040base = PHYS_FLASH_1;
+		if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_2, 0x1, 0x49)) {
+			amd160 = 1;
+			amd160base = PHYS_FLASH_2;
+		} else {
+			printf (__FUNCTION__
+				"(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+				PHYS_FLASH_2);
+		}
+	}
+#endif
+	else {
+		printf ("flash_init(): Unable to detect PHYS_FLASH_1: 0x%08x\n",
+			PHYS_FLASH_1);
+	}
+
+	/* Configure AMD Am29LV160DB (2MB) */
+	info = &flash_info[amd160];
+	info->flash_id = FLASH_DEV_U7_2MB;
+	info->sector_count = 35;
+	info->size = 2 * 1024 * 1024;	/* 2MB */
+	/* 1*16K Boot Block
+	   2*8K Parameter Block
+	   1*32K Small Main Block */
+	info->start[0] = amd160base;
+	info->start[1] = amd160base + 0x4000;
+	info->start[2] = amd160base + 0x6000;
+	info->start[3] = amd160base + 0x8000;
+	for (i = 1; i < info->sector_count; i++)
+		info->start[3 + i] = amd160base + i * (64 * 1024);
+
+	for (i = 0; i < info->sector_count; i++) {
+		/* Write auto select command sequence and query sector protection */
+		FLASH_CMD_SELECT (info->flash_id,
+				  info->start[i] | CACHE_DISABLE_MASK);
+		flashtest =
+			GET__U8 (((info->start[i] + 4) | CACHE_DISABLE_MASK));
+		FLASH_CMD_RESET (info->flash_id,
+				 amd160base | CACHE_DISABLE_MASK);
+		info->protect[i] = (flashtest & 0x0001);
+	}
+
+	/*
+	 * protect monitor and environment sectors in 2MB flash
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       amd160base, amd160base + monitor_flash_len - 1, info);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, info);
+
+#if CFG_MAX_FLASH_BANKS == 2
+	/* Configure AMD Am29LV040B (512KB) */
+	info = &flash_info[amd040];
+	info->flash_id = FLASH_DEV_U9_512KB;
+	info->sector_count = 8;
+	info->size = 512 * 1024;	/* 512KB, 8 x 64KB */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = amd040base + i * (64 * 1024);
+		/* Write auto select command sequence and query sector protection */
+		FLASH_CMD_SELECT (info->flash_id,
+				  info->start[i] | CACHE_DISABLE_MASK);
+		flashtest =
+			GET__U8 (((info->start[i] + 2) | CACHE_DISABLE_MASK));
+		FLASH_CMD_RESET (info->flash_id,
+				 amd040base | CACHE_DISABLE_MASK);
+		info->protect[i] = (flashtest & 0x0001);
+	}
+#endif
+
+	return flash_info[0].size
+#if CFG_MAX_FLASH_BANKS == 2
+		+ flash_info[1].size
+#endif
+		;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_DEV_U7_2MB) {
+		printf ("AMD Am29LV160DB (2MB) 16KB,2x8KB,32KB,31x64KB\n");
+	} else if (info->flash_id == FLASH_DEV_U9_512KB) {
+		printf ("AMD Am29LV040B	 (512KB) 8x64KB\n");
+	} else {
+		printf ("Unknown flash_id ...\n");
+		return;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf (" S%02d @ 0x%08lX%s", i,
+			info->start[i], info->protect[i] ? " !" : "  ");
+	}
+	printf ("\n");
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	u16 i, error = 0;
+
+	printf ("\n");
+
+	/* check flash protection bits */
+	if (_flash_check_protection (info, s_first, s_last)) {
+		printf ("  Flash erase aborted due to protected sectors\n");
+		return ERR_PROTECTED;
+	}
+
+	if ((s_first < info->sector_count) && (s_first <= s_last)) {
+		for (i = s_first; i <= s_last && !error; i++) {
+			printf ("  Erasing Sector %d @ 0x%08lx ... ", i,
+				info->start[i]);
+			/* bypass the cache to access the flash memory */
+			FLASH_CMD_ERASE_SEC (info->flash_id,
+					     (info->
+					      start[0] | CACHE_DISABLE_MASK),
+					     (info->
+					      start[i] | CACHE_DISABLE_MASK));
+			/* look for sector to become 0xFF after erase */
+			error = _flash_poll (info->flash_id,
+					     info->
+					     start[i] | CACHE_DISABLE_MASK,
+					     0xFF, CFG_FLASH_ERASE_TOUT);
+			FLASH_CMD_RESET (info->flash_id,
+					 (info->
+					  start[0] | CACHE_DISABLE_MASK));
+			printf ("done\n");
+			if (error) {
+				break;
+			}
+		}
+	} else
+		error = ERR_INVAL;
+
+	return error;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	u16 error = 0, i;
+	u32 n;
+	u8 *bp, *bps;
+
+	/*  Write Setup */
+	/* bypass the cache to access the flash memory */
+	FLASH_CMD_UNLOCK_BYPASS (info->flash_id,
+				 (info->start[0] | CACHE_DISABLE_MASK));
+
+	/*  Write the Data to Flash */
+
+	bp = (u8 *) (addr | CACHE_DISABLE_MASK);
+	bps = (u8 *) src;
+
+	for (n = 0; n < cnt && !error; n++, bp++, bps++) {
+
+		if (!(n % (cnt / 15))) {
+			printf (".");
+		}
+
+		/*  write the flash command for flash memory */
+		*bp = 0xA0;
+
+		/*  Write the data */
+		*bp = *bps;
+
+		/*  Check if the write is done */
+		for (i = 0; i < 0xff; i++);
+		error = _flash_poll (info->flash_id, (u32) bp, *bps,
+				     CFG_FLASH_WRITE_TOUT);
+		if (error) {
+			return error;
+		}
+	}
+
+	/*  Reset the Flash Mode to read */
+	FLASH_CMD_BYPASS_RESET (info->flash_id, info->start[0]);
+
+	printf (" ");
+
+	return error;
+}
diff --git a/board/evb4510/lowlevel_init.S b/board/evb4510/lowlevel_init.S
new file mode 100755
index 0000000..7184d72
--- /dev/null
+++ b/board/evb4510/lowlevel_init.S
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/***********************************************************************
+ * Configure Memory Map
+ *
+ * This memory map allows us to relocate from FLASH to SRAM.  After
+ * power-on reset the CPU only knows about the FLASH memory at address
+ * 0x00000000.	After lowlevel_init completes the memory map will be:
+ *
+ * Memory Addr
+ * 0x00000000
+ *     to	8MB SRAM (U5) -- 8MB Map
+ * 0x00800000
+ *
+ * 0x01000000
+ *     to	2MB Flash @ 0x00000000 (U7) -- 2MB Map
+ * 0x01200000
+ *
+ * 0x02000000
+ *     to	512KB Flash @ 0x02000000 (U9) -- 2MB Map
+ * 0x02080000
+ *
+ * Load all 12 memory registers with the STMIA instruction since
+ * memory access is disabled once these registers are written.	The
+ * last register written re-enables memory access.  For more info see
+ * the user's manual for the S3C4510B, available from Samsung's web
+ * site.  Search for part number "S3C4510B".
+ *
+ ***********************************************************************/
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* preserve the temp register (r12 AKA ip) and remap it. */
+	ldr r1, =SRAM_BASE+0xC
+	add r0, r12, #0x01000000
+	str r0, [r1]
+
+	/* remap the link register for when we return */
+	add lr, lr, #0x01000000
+
+	/* store a short program in the on chip SRAM, which is
+	 * unaffected when remapping memory.  Note the cache must be
+	 * disabled for the on chip SRAM to be available.
+	 */
+	ldr r1, =SRAM_BASE
+	ldr r0, =0xe8801ffe  /* stmia r0, {r1-r12} */
+	str r0, [r1]
+	add r1, r1, #4
+	ldr r0, =0xe59fc000  /* ldr r12, [pc, #0]  */
+	str r0, [r1]
+	add r1, r1, #4
+	ldr r0, =0xe1a0f00e  /* mov pc, lr	   */
+	str r0, [r1]
+
+	adr   r0, memory_map_data
+	ldmia r0, {r1-r12}
+	ldr   r0, =REG_EXTDBWTH
+
+	ldr pc, =SRAM_BASE
+
+.globl reset_cpu
+reset_cpu:
+	/*
+	 * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to
+	 * address 0x0.	 We accomplish this by storing a few
+	 * instructions into the on chip SRAM (8KB) and run from
+	 * there.  Note the cache must be disabled for the on chip
+	 * SRAM to be available.
+	 *
+	 * load r2 with REG_ROMCON0
+	 * load r3 with 0x12040060	   configure FLASH bank 0 @ 0x00000000
+	 * load r4 with REG_DRAMCON0
+	 * load r5 with 0x08000380	   configure   RAM bank 0 @ 0x01000000
+	 * load r6 with REG_REFEXTCON
+	 * load r7 with 0x9c218360
+	 * load r8 with 0x0
+	 * store str r3,[r2] @ SRAM_BASE
+	 * store str r5,[r4] @ SRAM_BASE + 0x4
+	 * store str r7,[r6] @ SRAM_BASE + 0x8
+	 * store mov pc,r8   @ SRAM_BASE + 0xC
+	 * mov pc, SRAM_BASE
+	 *
+	 */
+
+	/* disable cache */
+	ldr r0, =REG_SYSCFG
+	ldr r1, =0x83ffffa0	/* cache-disabled  */
+	str r1, [r0]
+
+	ldr r2, =REG_ROMCON0
+	ldr r3, =0x02000060	/* Bank0 2MB FLASH   @ 0x00000000 */
+	ldr r4, =REG_DRAMCON0
+	ldr r5, =0x18040380	/* DRAM0 8MB SRAM    @ 0x01000000 */
+	ldr r6, =REG_REFEXTCON
+	ldr r7, =0xce278360
+	ldr r8, =0x00000000
+	ldr r1, =SRAM_BASE
+	ldr r0, =0xe5823000	/* str	r3, [r2] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+4
+	ldr r0, =0xe5845000	/* str	r5, [r4] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+8
+	ldr r0, =0xe5867000	/* str	r7, [r6] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+0xC
+	ldr r0, =0xe1a0f008	/* mov	pc, r8	 */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE
+	mov pc, r1
+
+	/* never return */
+
+/************************************************************************
+ * Below are twelve 32-bit values for the twelve memory registers of
+ * the system manager, starting with register REG_EXTDBWTH.
+ ***********************************************************************/
+memory_map_data:
+	.long 0x00f03005     /* memory widths */
+	.long 0x12040060     /* Bank0 2MB FLASH	  @ 0x01000000 */
+	.long 0x22080060     /* Bank1 512KB FLASH @ 0x02000000 */
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x08000380     /* DRAM0 8MB SRAM	  @ 0x00000000 */
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x9c218360     /* enable memory */
diff --git a/board/evb4510/u-boot.lds b/board/evb4510/u-boot.lds
new file mode 100755
index 0000000..5b70a40
--- /dev/null
+++ b/board/evb4510/u-boot.lds
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  cpu/arm720t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+				  /* Stabs debugging sections.	  */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/board/evb64260/64260.h b/board/evb64260/64260.h
new file mode 100755
index 0000000..d106ced
--- /dev/null
+++ b/board/evb64260/64260.h
@@ -0,0 +1,31 @@
+#ifndef __64260_H__
+#define __64260_H__
+
+/* CPU Configuration bits */
+#define CPU_CONF_ADDR_MISS_EN	(1 << 8)
+#define	CPU_CONF_AACK_DELAY	(1 << 11)
+#define	CPU_CONF_ENDIANESS	(1 << 12)
+#define CPU_CONF_PIPELINE	(1 << 13)
+#define CPU_CONF_TA_DELAY	(1 << 15)
+#define CPU_CONF_RD_OOO		(1 << 16)
+#define CPU_CONF_STOP_RETRY	(1 << 17)
+#define CPU_CONF_MULTI_DECODE	(1 << 18)
+#define CPU_CONF_DP_VALID	(1 << 19)
+#define CPU_CONF_PERR_PROP	(1 << 22)
+#define CPU_CONF_FAST_CLK	(1 << 23)
+#define CPU_CONF_AACK_DELAY_2	(1 << 25)
+#define CPU_CONF_AP_VALID	(1 << 26)
+#define CPU_CONF_REMAP_WR_DIS	(1 << 27)
+#define CPU_CONF_CONF_SB_DIS	(1 << 28)
+#define CPU_CONF_IO_SB_DIS	(1 << 29)
+#define CPU_CONF_CLK_SYNC	(1 << 30)
+
+/* CPU Master Control bits */
+#define CPU_MAST_CTL_ARB_EN	(1 << 8)
+#define CPU_MAST_CTL_MASK_BR_1	(1 << 9)
+#define CPU_MAST_CTL_M_WR_TRIG	(1 << 10)
+#define CPU_MAST_CTL_M_RD_TRIG	(1 << 11)
+#define CPU_MAST_CTL_CLEAN_BLK	(1 << 12)
+#define CPU_MAST_CTL_FLUSH_BLK	(1 << 13)
+
+#endif /* __64260_H__ */
diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile
new file mode 100755
index 0000000..c493d6c
--- /dev/null
+++ b/board/evb64260/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+SOBJS	= misc.o
+OBJS	= $(BOARD).o flash.o serial.o memory.o pci.o \
+	  eth.o eth_addrtbl.o mpsc.o i2c.o \
+	  sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o
+
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt
new file mode 100755
index 0000000..391d49a
--- /dev/null
+++ b/board/evb64260/bootseq.txt
@@ -0,0 +1,94 @@
+(cpu/mpc7xxx/start.S)
+
+start:
+    b boot_cold
+
+start_warm:
+    b boot_warm
+
+
+boot_cold:
+boot_warm:
+    clear bats
+    init l2 (if enabled)
+    init altivec (if enabled)
+    invalidate l2 (if enabled)
+    setup bats (from defines in config_EVB)
+    enable_addr_trans: (if MMU enabled)
+	enable MSR_IR and MSR_DR
+    jump to in_flash
+
+in_flash:
+    enable l1 dcache
+    gal_low_init: (board/evb64260/sdram_init.S)
+	config SDRAM (CFG, TIMING, DECODE)
+	init scratch regs (810 + 814)
+
+	detect DIMM0 (bank 0 only)
+	config SDRAM_PARA0 to 256/512Mbit
+	bl sdram_op_mode
+	detect bank0 width
+	    write scratch reg 810
+	config SDRAM_PARA0 with results
+	config SDRAM_PARA1 with results
+
+	detect DIMM1 (bank 2 only)
+	config SDRAM_PARA2 to 256/512Mbit
+	detect bank2 width
+	    write scratch reg 814
+	config SDRAM_PARA2 with results
+	config SDRAM_PARA3 with results
+
+	setup device bus timings/width
+	setup boot device timings/width
+
+	setup CPU_CONF (0x0)
+	setup cpu master control register 0x160
+	setup PCI0 TIMEOUT
+	setup PCI1 TIMEOUT
+	setup PCI0 BAR
+	setup PCI1 BAR
+
+	setup MPP control 0-3
+	setup GPP level control
+	setup Serial ports multiplex
+
+    setup stack pointer (r1)
+    setup GOT
+    call cpu_init_f
+    	debug leds
+    board_init_f: (common/board.c)
+	board_early_init_f:
+	    remap gt regs?
+	    map PCI mem/io
+	    map device space
+	    clear out interupts
+	init_timebase
+	env_init
+	serial_init
+	console_init_f
+	display_options
+	initdram: (board/evb64260/evb64260.c)
+	    detect memory
+	    for each bank:
+		dram_size()
+		setup PCI slave memory mappings
+		setup SCS
+   	setup monitor
+	alloc board info struct
+	init bd struct
+	relocate_code: (cpu/mpc7xxx/start.S)
+	    copy,got,clearbss
+	    board_init_r(bd, dest_addr) (common/board.c)
+		setup bd function pointers
+		trap_init
+		flash_init: (board/evb64260/flash.c)
+		setup bd flash info
+		cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
+		    nothing
+		mem_malloc_init
+		malloc_bin_reloc
+		spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
+		env_relocated
+		misc_init_r(bd): (board/evb64260/evb64260.c)
+		    mpsc_init2
diff --git a/board/evb64260/config.mk b/board/evb64260/config.mk
new file mode 100755
index 0000000..0646a3e
--- /dev/null
+++ b/board/evb64260/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EVB64260 boards
+#
+
+TEXT_BASE = 0xfff00000
diff --git a/board/evb64260/ecctest.c b/board/evb64260/ecctest.c
new file mode 100755
index 0000000..5d3679a
--- /dev/null
+++ b/board/evb64260/ecctest.c
@@ -0,0 +1,111 @@
+indent: Standard input:27: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
+
+#ifdef ECC_TEST
+static inline void ecc_off (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
+}
+
+static inline void ecc_on (void)
+{
+	*(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
+}
+
+static int putshex (const char *buf, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++) {
+		printf ("%02x", buf[i]);
+	}
+	return 0;
+}
+
+static int char_memcpy (void *d, const void *s, int len)
+{
+	int i;
+	char *cd = d;
+	const char *cs = s;
+
+	for (i = 0; i < len; i++) {
+		*(cd++) = *(cs++);
+	}
+	return 0;
+}
+
+static int memory_test (char *buf)
+{
+	const char src[][16] = {
+		{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+		{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+		 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
+		{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+		 0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
+		{0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+		 0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
+		{0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+		 0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
+		{0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+		 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
+		{0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+		 0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
+		{0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+		 0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
+		{0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+		 0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
+		{0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+		 0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
+		{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+		 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
+		{0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+	};
+	const int foo[] = { 0 };
+	int i, j, a;
+
+	printf ("\ntest @ %d %p\n", foo[0], buf);
+	for (i = 0; i < 12; i++) {
+		for (a = 0; a < 8; a++) {
+			const char *s = src[i] + a;
+			int align = (unsigned) (s) & 0x7;
+
+			/* ecc_off(); */
+			memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+			/* ecc_off(); */
+			char_memcpy (buf, s, 8);
+			/* ecc_on(); */
+			putshex (s, 8);
+			if (memcmp (buf, s, 8)) {
+				putc ('\n');
+				putshex (buf, 8);
+				printf (" [FAIL] (%p) align=%d\n", s, align);
+				for (j = 0; j < 8; j++) {
+					s[j] == buf[j] ? puts ("  ") :
+						printf ("%02x",
+							(s[j]) ^ (buf[j]));
+				}
+				putc ('\n');
+			} else {
+				printf (" [PASS] (%p) align=%d\n", s, align);
+			}
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
new file mode 100755
index 0000000..eafa48b
--- /dev/null
+++ b/board/evb64260/eth.c
@@ -0,0 +1,807 @@
+/**************************************************************************
+Etherboot -  BOOTP/TFTP Bootstrap Program
+Skeleton NIC driver for Etherboot
+***************************************************************************/
+
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+/*
+ * This file is a modified version from the Galileo polled mode
+ * network driver for the ethernet contained within the GT64260
+ * chip. It has been modified to fit into the U-Boot framework, from
+ * the original (etherboot) setup.  Also, additional cleanup and features
+ * were added.
+ *
+ * - Josh Huber <huber@mclx.com>
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <galileo/gt64260R.h>
+#include <galileo/core.h>
+#include <asm/cache.h>
+#include <miiphy.h>
+#include <net.h>
+
+#include "eth.h"
+#include "eth_addrtbl.h"
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+
+#define GT6426x_ETH_BUF_SIZE	1536
+
+/* if you like verbose output, turn this on! */
+#undef DEBUG
+
+/* Restart autoneg if we detect link is up on phy init. */
+
+/*
+ * The GT doc's say that after Rst is deasserted, and the PHY
+ * reports autoneg complete, it runs through its autoneg
+ * procedures. This doesn't seem to be the case for MII
+ * PHY's. To work around this check for link up && autoneg
+ * complete when initilizing the port. If they are both set,
+ * then restart PHY autoneg. Of course, it may be something
+ * completly different.
+ */
+#ifdef CONFIG_ETHER_PORT_MII
+# define RESTART_AUTONEG
+#endif
+
+/* do this if you dont want to use snooping */
+#define USE_SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef USE_SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)           if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+/* bummer - w/o flush, nothing works, even with snooping - FIXME */
+/* #define FLUSH_DCACHE(a,b) */
+#define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+struct eth_dev_s {
+	eth0_tx_desc_single *eth_tx_desc;
+	eth0_rx_desc_single *eth_rx_desc;
+	char *eth_tx_buffer;
+	char *eth_rx_buffer[NR];
+	int tdn, rdn;
+	int dev;
+	unsigned int reg_base;
+};
+
+
+#ifdef CONFIG_INTEL_LXT97X
+/* for intel LXT972 */
+static const char ether_port_phy_addr[3]={0,1,2};
+#else
+static const char ether_port_phy_addr[3]={4,5,6};
+#endif
+
+/* MII PHY access routines are common for all i/f, use gal_ent0 */
+#define GT6426x_MII_DEVNAME	"gal_enet0"
+
+int gt6426x_miiphy_read(char *devname, unsigned char phy,
+		unsigned char reg, unsigned short *val);
+
+static inline unsigned short
+miiphy_read_ret(unsigned short phy, unsigned short reg)
+{
+    unsigned short val;
+    gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
+    return val;
+}
+
+
+/**************************************************************************
+RESET - Reset adapter
+***************************************************************************/
+void
+gt6426x_eth_reset(void *v)
+{
+	/*  we should do something here...
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *p = wp->priv;
+	*/
+
+	printf ("RESET\n");
+	/* put the card in its initial state */
+}
+
+static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
+{
+#ifdef DEBUG
+    printf("SMI interrupt: ");
+
+    if(icr&0x20000000) {
+	printf("SMI done\n");
+    }
+#endif
+
+    if(icr&0x10000000) {
+	unsigned int psr;
+	psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
+#ifdef DEBUG
+	printf("PHY state change:\n"
+	       "  GT:%s:%s:%s:%s\n",
+		psr&1?"100":" 10",
+		psr&8?" Link":"nLink",
+		psr&2?"FD":"HD",
+		psr&4?" FC":"nFC");
+
+#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
+	{
+	unsigned short mii_11;
+	mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11);
+
+	printf(" mii:%s:%s:%s:%s %s:%s %s\n",
+		mii_11&(1<<14)?"100":" 10",
+		mii_11&(1<<10)?" Link":"nLink",
+		mii_11&(1<<9)?"FD":"HD",
+		mii_11&(1<<4)?" FC":"nFC",
+
+		mii_11&(1<<7)?"ANc":"ANnc",
+		mii_11&(1<<8)?"AN":"Manual",
+		""
+		);
+	}
+#endif /* CONFIG_INTEL_LXT97X */
+#endif /* DEBUG */
+    }
+}
+
+static int
+gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
+{
+	int eth_len=0;
+	char *eth_data;
+
+	eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)];
+
+	INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
+
+	if (rx->command_status & 0x80000000) {
+		return 0; /* No packet received */
+	}
+
+	eth_len = (unsigned int)
+		(rx->buff_size_byte_count) & 0x0000ffff;
+	eth_data = (char *) p->eth_rx_buffer[p->rdn];
+
+#ifdef DEBUG
+	if (eth_len) {
+		printf ("%s: Recived %d byte Packet @ 0x%p\n",
+			__FUNCTION__, eth_len, eth_data);
+	}
+#endif
+	/*
+	 * packet is now in:
+	 * eth0_rx_buffer[RDN_ETH0];
+	 */
+
+	/* let the upper layer handle the packet */
+	NetReceive ((uchar *)eth_data, eth_len);
+
+	rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
+
+
+	/* GT96100 Owner */
+	rx->command_status = 0x80000000;
+
+	FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
+
+	p->rdn ++;
+	if (p->rdn == NR) {p->rdn = 0;}
+
+	sync();
+
+	/* Start Rx*/
+	GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
+
+#ifdef DEBUG
+	{
+	    int i;
+	    for (i=0;i<12;i++) {
+		printf(" %02x", eth_data[i]);
+	    }
+	}
+	printf(": %d bytes\n", eth_len);
+#endif
+	INVALIDATE_DCACHE((unsigned int)eth_data,
+		(unsigned int)eth_data+eth_len);
+	return eth_len;
+}
+
+/**************************************************************************
+POLL - look for an rx frame, handle other conditions
+***************************************************************************/
+int
+gt6426x_eth_poll(void *v)
+{
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *p = wp->priv;
+	unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
+
+	if(icr) {
+	    GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
+#ifdef DEBUG
+	    printf("poll got ICR %08x\n", icr);
+#endif
+	    /* SMI done or PHY state change*/
+	    if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
+	}
+	/* always process. We aren't using RX interrupts */
+	return gt6426x_eth_receive(p, icr);
+}
+
+/**************************************************************************
+TRANSMIT - Transmit a frame
+***************************************************************************/
+int
+gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
+{
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
+#ifdef DEBUG
+	unsigned int old_command_stat,old_psr;
+#endif
+	eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn];
+
+	/* wait for tx to be ready */
+	INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
+	while (tx->command_status & 0x80000000) {
+	    int i;
+	    for(i=0;i<1000;i++);
+			INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
+	}
+
+	GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
+		      (unsigned int)tx);
+
+#ifdef DEBUG
+	printf("copying to tx_buffer [%p], length %x, desc = %p\n",
+	       dev->eth_tx_buffer, s, dev->eth_tx_desc);
+#endif
+	memcpy(dev->eth_tx_buffer, (char *) p, s);
+
+	tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
+	tx->bytecount_reserved = ((__u16)s) << 16;
+
+	/*    31 - own
+	 *    22 - gencrc
+	 * 18:16 - pad, last, first */
+	tx->command_status = (1<<31) | (1<<22) | (7<<16);
+#if 0
+	/* FEr #18 */
+	tx->next_desc = NULL;
+#else
+	tx->next_desc =
+		(struct eth0_tx_desc_struct *)
+		&dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
+
+	/* cpu owned */
+	dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16);	/* pad, last, first */
+#endif
+
+#ifdef DEBUG
+	old_command_stat=tx->command_status,
+	old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
+#endif
+
+	FLUSH_DCACHE((unsigned int)tx,
+		(unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
+
+	FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
+
+	GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
+
+#ifdef DEBUG
+	{
+	    unsigned int command_stat=0;
+	    printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
+	    /* wait for tx to be ready */
+	    do {
+		unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
+		command_stat=tx->command_status;
+		if(command_stat!=old_command_stat || psr !=old_psr) {
+		    printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
+		    old_command_stat = command_stat;
+		    old_psr = psr;
+		}
+		/* gt6426x_eth0_poll(); */
+	    } while (command_stat & 0x80000000);
+
+	    printf("sent %d byte frame\n", s);
+
+	    if((command_stat & (3<<15)) == 3) {
+		printf("frame had error (stat=%08x)\n", command_stat);
+	    }
+	}
+#endif
+	return 0;
+}
+
+/**************************************************************************
+DISABLE - Turn off ethernet interface
+***************************************************************************/
+void
+gt6426x_eth_disable(void *v)
+{
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
+
+	GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
+}
+
+/**************************************************************************
+MII utilities - write: write to an MII register via SMI
+***************************************************************************/
+int
+gt6426x_miiphy_write(char *devname, unsigned char phy,
+		unsigned char reg, unsigned short data)
+{
+    unsigned int temp= (reg<<21) | (phy<<16) | data;
+
+    while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));	/* wait for !Busy */
+
+    GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
+    return 0;
+}
+
+/**************************************************************************
+MII utilities - read: read from an MII register via SMI
+***************************************************************************/
+int
+gt6426x_miiphy_read(char *devname, unsigned char phy,
+		unsigned char reg, unsigned short *val)
+{
+    unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
+
+    while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));	/* wait for !Busy */
+
+    GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
+
+    while(1) {
+	temp=GTREGREAD(ETHERNET_SMI_REGISTER);
+	if(temp & (1<<27)) break;		/* wait for ReadValid */
+    }
+    *val = temp & 0xffff;
+
+    return 0;
+}
+
+#ifdef DEBUG
+/**************************************************************************
+MII utilities - dump mii registers
+***************************************************************************/
+static void
+gt6426x_dump_mii(bd_t *bis, unsigned short phy)
+{
+	printf("mii reg 0 - 3:   %04x %04x %04x %04x\n",
+		miiphy_read_ret(phy, 0x0),
+		miiphy_read_ret(phy, 0x1),
+		miiphy_read_ret(phy, 0x2),
+		miiphy_read_ret(phy, 0x3)
+		);
+	printf("        4 - 7:   %04x %04x %04x %04x\n",
+		miiphy_read_ret(phy, 0x4),
+		miiphy_read_ret(phy, 0x5),
+		miiphy_read_ret(phy, 0x6),
+		miiphy_read_ret(phy, 0x7)
+		);
+	printf("        8:       %04x\n",
+		miiphy_read_ret(phy, 0x8)
+		);
+	printf("        16-19:   %04x %04x %04x %04x\n",
+		miiphy_read_ret(phy, 0x10),
+		miiphy_read_ret(phy, 0x11),
+		miiphy_read_ret(phy, 0x12),
+		miiphy_read_ret(phy, 0x13)
+		);
+	printf("        20,30:   %04x %04x\n",
+		miiphy_read_ret(phy, 20),
+		miiphy_read_ret(phy, 30)
+		);
+}
+#endif
+
+#ifdef RESTART_AUTONEG
+
+/* If link is up && autoneg compleate, and if
+ * GT and PHY disagree about link capabilitys,
+ * restart autoneg - something screwy with FD/HD
+ * unless we do this. */
+static void
+check_phy_state(struct eth_dev_s *p)
+{
+	int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR);
+	int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
+
+	if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) {
+		int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) &
+				miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR);
+		int want;
+
+		if (nego & PHY_ANLPAR_TXFD) {
+			want = 0x3;
+			printf("MII: 100Base-TX, Full Duplex\n");
+		} else if (nego & PHY_ANLPAR_TX) {
+			want = 0x1;
+			printf("MII: 100Base-TX, Half Duplex\n");
+		} else if (nego & PHY_ANLPAR_10FD) {
+			want = 0x2;
+			printf("MII: 10Base-T, Full Duplex\n");
+		} else if (nego & PHY_ANLPAR_10) {
+			want = 0x0;
+			printf("MII: 10Base-T, Half Duplex\n");
+		} else {
+			printf("MII: Unknown link-foo! %x\n", nego);
+			return;
+		}
+
+		if ((psr & 0x3) != want) {
+			printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
+					psr & 0x3, want);
+			miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
+					miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
+			udelay(10000);	/* the EVB's GT takes a while to notice phy
+					   went down and up */
+		}
+	}
+}
+#endif
+
+/**************************************************************************
+PROBE - Look for an adapter, this routine's visible to the outside
+***************************************************************************/
+int
+gt6426x_eth_probe(void *v, bd_t *bis)
+{
+	struct eth_device *wp = (struct eth_device *)v;
+	struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
+	int dev = p->dev;
+	unsigned int reg_base = p->reg_base;
+	unsigned long temp;
+	int i;
+
+	if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
+	{	/* This should never happen */
+		printf("%s: Invalid device %d\n", __FUNCTION__, dev );
+		return 0;
+	}
+
+#ifdef DEBUG
+	printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
+	printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
+		GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
+		GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
+#endif
+
+	/* clear MIB counters */
+	for(i=0;i<255; i++)
+	    temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
+
+#ifdef CONFIG_INTEL_LXT97X
+	/* for intel LXT972 */
+
+	/* led 1: 0x1=txact
+	   led 2: 0xc=link/rxact
+	   led 3: 0x2=rxact (N/C)
+	   strch: 0,2=30 ms, enable */
+	miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
+
+	/* 2.7ns port rise time */
+	/*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
+#else
+	/* already set up in mpsc.c */
+	/*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38);	/  b400 */
+
+	/* already set up in sdram_init.S... */
+	/* MPSC0, MPSC1, RMII */
+	/*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102);		/  f010 */
+#endif
+	GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
+	     ether_port_phy_addr[0]     |
+	    (ether_port_phy_addr[1]<<5) |
+	    (ether_port_phy_addr[2]<<10));			/* 2000 */
+
+	/* 13:12 -   10: 4x64bit burst	(cache line size = 32 bytes)
+	 *    9  -    1: RIFB - interrupt on frame boundaries only
+	 *  6:7  -   00: big endian rx and tx
+	 *  5:2  - 1111: 15 retries */
+	GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
+		(2<<12) | (1<<9) | (0xf<<2) );			/* 2440 */
+
+#ifndef USE_SOFTWARE_CACHE_MANAGEMENT
+	/* enable rx/tx desc/buffer cache snoop */
+	GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
+		&temp);						/* f200 */
+	temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
+	GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
+		temp);
+#endif
+
+	/* 31  28 27  24 23  20 19  16
+	 *  0000   0000   0000   0000 	[0004]
+	 * 15  12 11  8   7  4   3  0
+	 *  1000   1101   0000   0000	[4d00]
+	 *    20 - 0=MII 1=RMII
+	 *    19 - 0=speed autoneg
+	 * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
+	 *    11 - no force link pass
+	 *    10 - 1=disable fctl autoneg
+	 *     8 - override prio ?? */
+	temp = 0x00004d00;
+#ifndef CONFIG_ETHER_PORT_MII
+	temp |= (1<<20);	/* RMII */
+#endif
+	/* set En */
+	GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
+		     temp);				/* 2408 */
+
+	/* hardcode E1 also? */
+	/* -- according to dox, this is safer due to extra pulldowns? */
+	if (dev<2) {
+	GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
+		     temp);				/* 2408 */
+	}
+
+	/* wake up MAC */				 /* 2400 */
+	GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
+	temp |= (1<<7);		/* enable port */
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
+	temp |= (1<<12);	/* hash size 1/2k */
+#else
+	temp |= 1;		/* promisc */
+#endif
+	GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
+							/* 2400 */
+
+#ifdef RESTART_AUTONEG
+	check_phy_state(p);
+#endif
+
+	printf("%s: Waiting for link up..\n", wp->name);
+	temp = 10 * 1000;
+	/* wait for link back up */
+	while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
+			&& (--temp > 0)){
+	    udelay(1000);	/* wait 1 ms */
+	}
+	if ( temp == 0) {
+		printf("%s: Failed!\n", wp->name);
+		return (0);
+	}
+
+	printf("%s: OK!\n", wp->name);
+
+	p->tdn = 0;
+	p->rdn = 0;
+	p->eth_tx_desc[p->tdn].command_status = 0;
+
+	/* Initialize Rx Side */
+	for (temp = 0; temp < NR; temp++) {
+		p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
+		p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
+
+		/* GT96100 Owner */
+		p->eth_rx_desc[temp].command_status = 0x80000000;
+		p->eth_rx_desc[temp].next_desc =
+			(struct eth0_rx_desc_struct *)
+			&p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
+	}
+
+	FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
+		     (unsigned int)&p->eth_tx_desc[NR]);
+	FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
+		     (unsigned int)&p->eth_rx_desc[NR]);
+
+	GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
+		      (unsigned int) p->eth_tx_desc);
+	GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
+		      (unsigned int) p->eth_rx_desc);
+	GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
+		      (unsigned int) p->eth_rx_desc);
+
+#ifdef DEBUG
+	printf ("\nRx descriptor pointer is %08x %08x\n",
+		GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
+		GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
+	printf ("\n\n%08x %08x\n",
+		(unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
+
+	printf ("Descriptor dump:\n");
+	printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
+	printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
+	printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
+	printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
+	printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
+	printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
+	printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
+	printf ("%08x\n\n",
+		*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
+#endif
+
+#ifdef DEBUG
+	gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
+#endif
+
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
+	{
+		unsigned int hashtable_base;
+	    u8 *b = (u8 *)(wp->enetaddr);
+		u32 macH, macL;
+
+		/* twist the MAC up into the way the discovery wants it */
+		macH= (b[0]<<8) | b[1];
+	    macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
+
+	    /* mode 0, size 0x800 */
+	    hashtable_base =initAddressTable(dev,0,1);
+
+	    if(!hashtable_base) {
+			printf("initAddressTable failed\n");
+			return 0;
+	    }
+
+	    addAddressTableEntry(dev, macH, macL, 1, 0);
+	    GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
+		    hashtable_base);
+	}
+#endif
+
+	/* Start Rx*/
+	GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
+	printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
+	return 1;
+}
+
+/* enter all the galileo ethernet devs into MULTI-BOOT */
+void
+gt6426x_eth_initialize(bd_t *bis)
+{
+	struct eth_device *dev;
+	struct eth_dev_s *p;
+	int devnum, x, temp;
+	char *s, *e, buf[64];
+
+#ifdef DEBUG
+	printf( "\n%s\n", __FUNCTION );
+#endif
+
+	for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
+		dev = calloc(sizeof(*dev), 1);
+		if (!dev) {
+			printf( "%s: gal_enet%d allocation failure, %s\n",
+					__FUNCTION__, devnum, "eth_device structure");
+			return;
+		}
+
+		/* must be less than NAMESIZE (16) */
+		sprintf(dev->name, "gal_enet%d", devnum);
+
+#ifdef DEBUG
+		printf( "Initializing %s\n", dev->name );
+#endif
+
+		/* Extract the MAC address from the environment */
+		switch (devnum)
+		{
+			case 0: s = "ethaddr"; break;
+#if (GAL_ETH_DEVS > 1)
+			case 1: s = "eth1addr"; break;
+#endif
+#if (GAL_ETH_DEVS > 2)
+			case 2: s = "eth2addr";	break;
+#endif
+			default: /* this should never happen */
+				printf( "%s: Invalid device number %d\n",
+						__FUNCTION__, devnum );
+				return;
+		}
+
+		temp = getenv_r (s, buf, sizeof(buf));
+		s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+		printf ("Setting MAC %d to %s\n", devnum, s );
+#endif
+		for (x = 0; x < 6; ++x) {
+			dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e+1 : e;
+		}
+
+		dev->init = (void*)gt6426x_eth_probe;
+		dev->halt = (void*)gt6426x_eth_reset;
+		dev->send = (void*)gt6426x_eth_transmit;
+		dev->recv = (void*)gt6426x_eth_poll;
+
+		p = calloc( sizeof(*p), 1 );
+		dev->priv = (void*)p;
+		if (!p)
+		{
+			printf( "%s: %s allocation failure, %s\n",
+					__FUNCTION__, dev->name, "Private Device Structure");
+			free(dev);
+			return;
+		}
+
+		p->dev = devnum;
+		p->tdn=0;
+		p->rdn=0;
+		p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
+
+		p->eth_tx_desc =
+			(eth0_tx_desc_single *)
+			(((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
+						(NT+1)) & 0xfffffff0) + 0x10);
+		if (!p)
+		{
+			printf( "%s: %s allocation failure, %s\n",
+					__FUNCTION__, dev->name, "Tx Descriptor");
+			free(dev);
+			return;
+		}
+
+		p->eth_rx_desc =
+			(eth0_rx_desc_single *)
+			(((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
+						(NR+1)) & 0xfffffff0) + 0x10);
+		if (!p->eth_rx_desc)
+		{
+			printf( "%s: %s allocation failure, %s\n",
+					__FUNCTION__, dev->name, "Rx Descriptor");
+			free(dev);
+			free(p);
+			return;
+		}
+
+		p->eth_tx_buffer =
+			(char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
+		if (!p->eth_tx_buffer)
+		{
+			printf( "%s: %s allocation failure, %s\n",
+					__FUNCTION__, dev->name, "Tx Bufffer");
+			free(dev);
+			free(p);
+			free(p->eth_rx_desc);
+			return;
+		}
+
+		for (temp = 0 ; temp < NR ; temp ++) {
+			p->eth_rx_buffer[temp] =
+				(char *)
+				(((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
+			if (!p->eth_rx_buffer[temp])
+			{
+				printf( "%s: %s allocation failure, %s\n",
+						__FUNCTION__, dev->name, "Rx Buffers");
+				free(dev);
+				free(p);
+				free(p->eth_tx_buffer);
+				free(p->eth_rx_desc);
+				free(p->eth_tx_desc);
+				while (temp >= 0)
+					free(p->eth_rx_buffer[--temp]);
+				return;
+			}
+		}
+
+
+		eth_register(dev);
+#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+		miiphy_register(dev->name,
+				gt6426x_miiphy_read, gt6426x_miiphy_write);
+#endif
+	}
+
+}
+#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */
diff --git a/board/evb64260/eth.h b/board/evb64260/eth.h
new file mode 100755
index 0000000..beb6db1
--- /dev/null
+++ b/board/evb64260/eth.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * eth.h - header file for the polled mode GT ethernet driver
+ */
+
+#ifndef __GT6426x_ETH_H__
+#define __GT6426x_ETH_H__
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <common.h>
+
+typedef struct eth0_tx_desc_struct {
+	volatile __u32 bytecount_reserved;
+	volatile __u32 command_status;
+	volatile struct eth0_tx_desc_struct * next_desc;
+	/* Note - the following will not work for 64 bit addressing */
+	volatile unsigned char * buff_pointer;
+} __attribute__ ((packed)) eth0_tx_desc_single;
+
+typedef struct eth0_rx_desc_struct {
+  volatile __u32 buff_size_byte_count;
+  volatile __u32 command_status;
+  volatile struct eth0_rx_desc_struct * next_desc;
+  volatile unsigned char * buff_pointer;
+} __attribute__ ((packed)) eth0_rx_desc_single;
+
+#define NT 20 /* Number of Transmit buffers */
+#define NR 20 /* Number of Receive buffers */
+#define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) /* 1600 */
+#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
+
+unsigned long TDN_ETH0 , RDN_ETH0; /* Rx/Tx current Descriptor Number*/
+unsigned int EVB64260_ETH0_irq;
+
+#define CLOSED 0
+#define OPENED 1
+
+#define PORT_ETH0 0
+
+extern eth0_tx_desc_single *eth0_tx_desc;
+extern eth0_rx_desc_single *eth0_rx_desc;
+extern char *eth0_tx_buffer;
+extern char *eth0_rx_buffer[NR];
+extern char *eth_data;
+
+extern int gt6426x_eth_poll(void *v);
+extern int gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s);
+extern void gt6426x_eth_disable(void *v);
+extern int gt6426x_eth_probe(void *v, bd_t *bis);
+
+#endif  /* __GT64260x_ETH_H__ */
diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c
new file mode 100755
index 0000000..e8ef0e3
--- /dev/null
+++ b/board/evb64260/eth_addrtbl.c
@@ -0,0 +1,221 @@
+#include <common.h>
+#include <malloc.h>
+#include <galileo/gt64260R.h>
+#include <galileo/core.h>
+#include <asm/cache.h>
+#include "eth.h"
+#include "eth_addrtbl.h"
+
+#define TRUE 1
+#define FALSE 0
+
+#define PRINTF printf
+
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
+
+static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, };
+static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, };
+static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, };
+static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, };
+
+static const u32 hashLength[2] = {
+	(0x8000),		/* 8K * 4 entries */
+	(0x8000 / 16),		/* 512 * 4 entries */
+};
+
+/* Initialize the address table for a port, if needed */
+unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector)
+{
+	unsigned int tableBase;
+
+	if (port < 0 || port >= GAL_ETH_DEVS) {
+		printf ("%s: Invalid port number %d\n", __FUNCTION__, port);
+		return 0;
+	}
+
+	if (hashMode > 1) {
+		printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port);
+		return 0;
+	}
+
+	if (realAddrTableBase[port] &&
+	    (addressTableHashSize[port] != hashSizeSelector)) {
+		/* we have been here before,
+		 * but now we want a different sized table
+		 */
+		free (realAddrTableBase[port]);
+		realAddrTableBase[port] = 0;
+		addressTableBase[port] = 0;
+
+	}
+
+	tableBase = (unsigned int) addressTableBase[port];
+	/* we get called for every probe, so only do this once */
+	if (!tableBase) {
+		int bytes =
+			hashLength[hashSizeSelector] * sizeof (addrTblEntry);
+
+		realAddrTableBase[port] =
+			malloc (bytes + 64);
+		tableBase = (unsigned int)realAddrTableBase;
+
+		if (!tableBase) {
+			printf ("%s: alloc memory failed \n", __FUNCTION__);
+			return 0;
+		}
+
+		/* align to octal byte */
+		if (tableBase & 63)
+			tableBase = (tableBase + 63) & ~63;
+
+		addressTableHashMode[port] = hashMode;
+		addressTableHashSize[port] = hashSizeSelector;
+		addressTableBase[port] = (addrTblEntry *) tableBase;
+
+		memset ((void *) tableBase, 0, bytes);
+	}
+
+	return tableBase;
+}
+
+/*
+ * ----------------------------------------------------------------------------
+ * This function will calculate the hash function of the address.
+ * depends on the hash mode and hash size.
+ * Inputs
+ * macH             - the 2 most significant bytes of the MAC address.
+ * macL             - the 4 least significant bytes of the MAC address.
+ * hashMode         - hash mode 0 or hash mode 1.
+ * hashSizeSelector - indicates number of hash table entries (0=0x8000,1=0x800)
+ * Outputs
+ * return the calculated entry.
+ */
+u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
+{
+	u32 hashResult;
+	u32 addrH;
+	u32 addrL;
+	u32 addr0;
+	u32 addr1;
+	u32 addr2;
+	u32 addr3;
+	u32 addrHSwapped;
+	u32 addrLSwapped;
+
+
+	addrH = NIBBLE_SWAPPING_16_BIT (macH);
+	addrL = NIBBLE_SWAPPING_32_BIT (macL);
+
+	addrHSwapped = FLIP_4_BITS (addrH & 0xf)
+		+ ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4)
+		+ ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8)
+		+ ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12);
+
+	addrLSwapped = FLIP_4_BITS (addrL & 0xf)
+		+ ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4)
+		+ ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8)
+		+ ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12)
+		+ ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16)
+		+ ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20)
+		+ ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24)
+		+ ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28);
+
+	addrH = addrHSwapped;
+	addrL = addrLSwapped;
+
+	if (hash_mode == 0) {
+		addr0 = (addrL >> 2) & 0x03f;
+		addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
+		addr2 = (addrL >> 15) & 0x1ff;
+		addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
+	} else {
+		addr0 = FLIP_6_BITS (addrL & 0x03f);
+		addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff));
+		addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff);
+		addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) |
+				      ((addrH & 0x1) << 8)));
+	}
+
+	hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
+
+	if (HashSize == _8K_TABLE) {
+		hashResult = hashResult & 0xffff;
+	} else {
+		hashResult = hashResult & 0x07ff;
+	}
+
+	return (hashResult);
+}
+
+
+/*
+ * ----------------------------------------------------------------------------
+ * This function will add an entry to the address table.
+ * depends on the hash mode and hash size that was initialized.
+ * Inputs
+ * port - ETHERNET port number.
+ * macH - the 2 most significant bytes of the MAC address.
+ * macL - the 4 least significant bytes of the MAC address.
+ * skip - if 1, skip this address.
+ * rd   - the RD field in the address table.
+ * Outputs
+ * address table entry is added.
+ * TRUE if success.
+ * FALSE if table full
+ */
+int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
+{
+	addrTblEntry *entry;
+	u32 newHi;
+	u32 newLo;
+	u32 i;
+
+	newLo = (((macH >> 4) & 0xf) << 15)
+		| (((macH >> 0) & 0xf) << 11)
+		| (((macH >> 12) & 0xf) << 7)
+		| (((macH >> 8) & 0xf) << 3)
+		| (((macL >> 20) & 0x1) << 31)
+		| (((macL >> 16) & 0xf) << 27)
+		| (((macL >> 28) & 0xf) << 23)
+		| (((macL >> 24) & 0xf) << 19)
+		| (skip << SKIP_BIT) | (rd << 2) | VALID;
+
+	newHi = (((macL >> 4) & 0xf) << 15)
+		| (((macL >> 0) & 0xf) << 11)
+		| (((macL >> 12) & 0xf) << 7)
+		| (((macL >> 8) & 0xf) << 3)
+		| (((macL >> 21) & 0x7) << 0);
+
+	/*
+	 * Pick the appropriate table, start scanning for free/reusable
+	 * entries at the index obtained by hashing the specified MAC address
+	 */
+	entry = addressTableBase[port];
+	entry += hashTableFunction (macH, macL, addressTableHashSize[port],
+				    addressTableHashMode[port]);
+	for (i = 0; i < HOP_NUMBER; i++, entry++) {
+		if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) {
+			break;
+		} else {	/* if same address put in same position */
+			if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
+			    && (entry->hi == newHi)) {
+				break;
+			}
+		}
+	}
+
+	if (i == HOP_NUMBER) {
+		PRINTF ("addGT64260addressTableEntry: table section is full\n");
+		return (FALSE);
+	}
+
+	/*
+	 * Update the selected entry
+	 */
+	entry->hi = newHi;
+	entry->lo = newLo;
+	DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
+	return (TRUE);
+}
+
+#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */
diff --git a/board/evb64260/eth_addrtbl.h b/board/evb64260/eth_addrtbl.h
new file mode 100755
index 0000000..5a62c67
--- /dev/null
+++ b/board/evb64260/eth_addrtbl.h
@@ -0,0 +1,83 @@
+#ifndef _ADDRESS_TABLE_H
+#define _ADDRESS_TABLE_H 1
+
+/*
+ * ----------------------------------------------------------------------------
+ * addressTable.h - this file has all the declarations of the address table
+ */
+
+#define _8K_TABLE                           0
+#define ADDRESS_TABLE_ALIGNMENT             8
+#define HASH_DEFAULT_MODE                   14
+#define HASH_MODE                           13
+#define HASH_SIZE                           12
+#define HOP_NUMBER                          12
+#define MAC_ADDRESS_STRING_SIZE             12
+#define MAC_ENTRY_SIZE                      sizeof(addrTblEntry)
+#define MAX_NUMBER_OF_ADDRESSES_TO_STORE    1000
+#define PROMISCUOUS_MODE                    0
+#define SKIP                                1<<1
+#define SKIP_BIT                            1
+#define VALID                               1
+
+/*
+ * ----------------------------------------------------------------------------
+ * XXX_MIKE - potential sign-extension bugs lurk here...
+ */
+#define NIBBLE_SWAPPING_32_BIT(X) ( (((X) & 0xf0f0f0f0) >> 4) \
+				  | (((X) & 0x0f0f0f0f) << 4) )
+
+#define NIBBLE_SWAPPING_16_BIT(X) ( (((X) & 0x0000f0f0) >> 4) \
+				  | (((X) & 0x00000f0f) << 4) )
+
+#define FLIP_4_BITS(X)  ( (((X) & 0x01) << 3) | (((X) & 0x002) << 1) \
+			| (((X) & 0x04) >> 1) | (((X) & 0x008) >> 3) )
+
+#define FLIP_6_BITS(X)  ( (((X) & 0x01) << 5) | (((X) & 0x020) >> 5) \
+			| (((X) & 0x02) << 3) | (((X) & 0x010) >> 3) \
+			| (((X) & 0x04) << 1) | (((X) & 0x008) >> 1) )
+
+#define FLIP_9_BITS(X)  ( (((X) & 0x01) << 8) | (((X) & 0x100) >> 8) \
+			| (((X) & 0x02) << 6) | (((X) & 0x080) >> 6) \
+			| (((X) & 0x04) << 4) | (((X) & 0x040) >> 4) \
+	 | ((X) & 0x10) | (((X) & 0x08) << 2) | (((X) & 0x020) >> 2) )
+
+/*
+ * V: value we're operating on
+ * O: offset of rightmost bit in field
+ * W: width of field to shift
+ * S: distance to shift left
+ */
+#define MASK( fieldWidth )                            ((1 << (fieldWidth)) - 1)
+#define leftShiftedBitfield( V,O,W,S)        (((V) & (MASK(W) << (O)))  << (S))
+#define rightShiftedBitfield(V,O,W,S)  (((u32)((V) & (MASK(W) << (O)))) >> (S))
+
+
+/*
+ * Push to main memory all cache lines associated with
+ * the specified range of virtual memory addresses
+ *
+ * A: Address of first byte in range to flush
+ * N: Number of bytes to flush
+ * Note - flush_dcache_range() does a "sync", does NOT invalidate
+ */
+#define DCACHE_FLUSH_N_SYNC( A, N )        flush_dcache_range( (A), ((A)+(N)) )
+
+
+typedef struct addressTableEntryStruct  {
+    u32 hi;
+    u32 lo;
+} addrTblEntry;
+
+u32
+uncachedPages( u32 pages  );
+u32
+hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode );
+
+unsigned int
+initAddressTable( u32 port, u32 hashMode, u32 hashSize );
+
+int
+addAddressTableEntry( u32 port, u32 macH, u32 macL, u32 rd, u32 skip          );
+
+#endif                                           /* #ifndef _ADDRESS_TABLE_H */
diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c
new file mode 100755
index 0000000..6a9d164
--- /dev/null
+++ b/board/evb64260/evb64260.c
@@ -0,0 +1,444 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * evb64260.c - main board support/init for the Galileo Eval board.
+ */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <galileo/memory.h>
+#include <galileo/pci.h>
+#include <galileo/gt64260R.h>
+#include <net.h>
+
+#include <asm/io.h>
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64260.h"
+#ifdef CONFIG_ZUMA_V2
+extern void zuma_mbox_init(void);
+#endif
+
+#undef	DEBUG
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* this is the current GT register space location */
+/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+
+/* Unfortunately, we cant change it while we are in flash, so we initialize it
+ * to the "final" value. This means that any debug_led calls before
+ * board_early_init_f wont work right (like in cpu_init_f).
+ * See also my_remap_gt_regs below. (NTL)
+ */
+
+unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * This is a version of the GT register space remapping function that
+ * doesn't touch globals (meaning, it's ok to run from flash.)
+ *
+ * Unfortunately, this has the side effect that a writable
+ * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
+ */
+
+void
+my_remap_gt_regs(u32 cur_loc, u32 new_loc)
+{
+	u32 temp;
+
+	/* check and see if it's already moved */
+	temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
+	if ((temp & 0xffff) == new_loc >> 20)
+		return;
+
+	temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
+		0xffff0000) | (new_loc >> 20);
+
+	out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
+
+	while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
+}
+
+static void
+gt_pci_config(void)
+{
+	/* move PCI stuff out of the way - NTL */
+	/* map PCI Host 0 */
+	pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE,
+		CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE);
+
+	pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
+	pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
+	pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
+
+	pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI,
+		CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE);
+
+	/* map PCI Host 1 */
+	pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE,
+		CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE);
+
+	pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
+	pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
+	pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
+
+	pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI,
+		CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE);
+
+	/* PCI interface settings */
+	GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
+	GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
+	GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
+	GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
+
+
+}
+
+/* Setup CPU interface paramaters */
+static void
+gt_cpu_config(void)
+{
+	cpu_t cpu = get_cpu_type();
+	ulong tmp;
+
+	/* cpu configuration register */
+	tmp = GTREGREAD(CPU_CONFIGURATION);
+
+	/* set the AACK delay bit
+	 * see Res#14 */
+	tmp |= CPU_CONF_AACK_DELAY;
+	tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
+
+	/* Galileo claims this is necessary for all busses >= 100 MHz */
+	tmp |= CPU_CONF_FAST_CLK;
+
+	if (cpu == CPU_750CX) {
+		tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
+		tmp &= ~CPU_CONF_AP_VALID;
+	} else {
+		tmp |= CPU_CONF_DP_VALID;
+		tmp |= CPU_CONF_AP_VALID;
+	}
+
+	/* this only works with the MPX bus */
+	tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
+	tmp |= CPU_CONF_PIPELINE;
+	tmp |= CPU_CONF_TA_DELAY;
+
+	GT_REG_WRITE(CPU_CONFIGURATION, tmp);
+
+	/* CPU master control register */
+	tmp = GTREGREAD(CPU_MASTER_CONTROL);
+
+	tmp |= CPU_MAST_CTL_ARB_EN;
+
+	if ((cpu == CPU_7400) ||
+	    (cpu == CPU_7410) ||
+	    (cpu == CPU_7450)) {
+
+		tmp |= CPU_MAST_CTL_CLEAN_BLK;
+		tmp |= CPU_MAST_CTL_FLUSH_BLK;
+
+	} else {
+		/* cleanblock must be cleared for CPUs
+		 * that do not support this command
+		 * see Res#1 */
+		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
+		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
+	}
+	GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);
+}
+
+/*
+ * board_early_init_f.
+ *
+ * set up gal. device mappings, etc.
+ */
+int board_early_init_f (void)
+{
+	uchar sram_boot = 0;
+
+	/*
+	 * set up the GT the way the kernel wants it
+	 * the call to move the GT register space will obviously
+	 * fail if it has already been done, but we're going to assume
+	 * that if it's not at the power-on location, it's where we put
+	 * it last time. (huber)
+	 */
+	my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS);
+
+	gt_pci_config();
+
+	/* mask all external interrupt sources */
+	GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
+	GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
+	GT_REG_WRITE(CPU_INT_0_MASK, 0);
+	GT_REG_WRITE(CPU_INT_1_MASK, 0);
+	GT_REG_WRITE(CPU_INT_2_MASK, 0);
+	GT_REG_WRITE(CPU_INT_3_MASK, 0);
+
+	/* now, onto the configuration */
+	GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG);
+
+	/* ----- DEVICE BUS SETTINGS ------ */
+
+	/*
+	 * EVB
+	 * 0 - SRAM
+	 * 1 - RTC
+	 * 2 - UART
+	 * 3 - Flash
+	 * boot - BootCS
+	 *
+	 * Zuma
+	 * 0 - Flash
+	 * boot - BootCS
+	 */
+
+	/*
+	 * the dual 7450 module requires burst access to the boot
+	 * device, so the serial rom copies the boot device to the
+	 * on-board sram on the eval board, and updates the correct
+	 * registers to boot from the sram. (device0)
+	 */
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
+	/* Zuma has no SRAM */
+	sram_boot = 0;
+#else
+	if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CFG_MONITOR_BASE)
+		sram_boot = 1;
+#endif
+
+	if (!sram_boot)
+		memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+
+	memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
+	memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
+	memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+
+	/* configure device timing */
+#ifdef CFG_DEV0_PAR
+	if (!sram_boot)
+		GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+#endif
+
+#ifdef CFG_DEV1_PAR
+	GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#endif
+#ifdef CFG_DEV2_PAR
+	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#endif
+
+#ifdef CONFIG_EVB64260
+#ifdef CFG_32BIT_BOOT_PAR
+	/* detect if we are booting from the 32 bit flash */
+	if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
+		/* 32 bit boot flash */
+		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR);
+	} else {
+		/* 8 bit boot flash */
+		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+	}
+#else
+	/* 8 bit boot flash only */
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+#endif
+#else /* CONFIG_EVB64260 not defined */
+		/* We are booting from 16-bit flash.
+		 */
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_16BIT_BOOT_PAR);
+#endif
+
+	gt_cpu_config();
+
+	/* MPP setup */
+	GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0);
+	GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1);
+	GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2);
+	GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3);
+
+	GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX);
+
+	return 0;
+}
+
+/* various things to do after relocation */
+
+int misc_init_r (void)
+{
+	icache_enable();
+#ifdef CFG_L2
+	l2cache_enable();
+#endif
+
+#ifdef CONFIG_MPSC
+	mpsc_init2();
+#endif
+
+#ifdef CONFIG_ZUMA_V2
+	zuma_mbox_init();
+#endif
+	return (0);
+}
+
+void
+after_reloc(ulong dest_addr)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* check to see if we booted from the sram.  If so, move things
+	 * back to the way they should be. (we're running from main
+	 * memory at this point now */
+
+	if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) {
+		memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M);
+	}
+
+	/* now, jump to the main U-Boot board init code */
+	board_init_r ((gd_t *)gd, dest_addr);
+
+	/* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int
+checkboard (void)
+{
+	puts ("Board: " CFG_BOARD_NAME "\n");
+	return (0);
+}
+
+/* utility functions */
+void
+debug_led(int led, int mode)
+{
+#if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
+	volatile int *addr = NULL;
+	int dummy;
+
+	if (mode == 1) {
+		switch (led) {
+		case 0:
+			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000);
+			break;
+
+		case 1:
+			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000);
+			break;
+
+		case 2:
+			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000);
+			break;
+		}
+	} else if (mode == 0) {
+		switch (led) {
+		case 0:
+			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000);
+			break;
+
+		case 1:
+			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000);
+			break;
+
+		case 2:
+			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000);
+			break;
+		}
+	}
+	WRITE_CHAR(addr, 0);
+	dummy = *addr;
+#endif /* CONFIG_ZUMA_V2 */
+}
+
+void
+display_mem_map(void)
+{
+    int i,j;
+    unsigned int base,size,width;
+    /* SDRAM */
+    printf("SDRAM\n");
+    for(i=0;i<=BANK3;i++) {
+	base = memoryGetBankBaseAddress(i);
+	size = memoryGetBankSize(i);
+	if(size !=0)
+	{
+	    printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20);
+	}
+    }
+
+    /* CPU's PCI windows */
+    for(i=0;i<=PCI_HOST1;i++) {
+	printf("\nCPU's PCI %d windows\n", i);
+	base=pciGetSpaceBase(i,PCI_IO);
+	size=pciGetSpaceSize(i,PCI_IO);
+	printf("      IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20);
+	for(j=0;j<=PCI_REGION3;j++) {
+	    base = pciGetSpaceBase(i,j);
+	    size = pciGetSpaceSize(i,j);
+	    printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base,
+		    size>>20);
+	}
+    }
+
+    /* Devices */
+    printf("\nDEVICES\n");
+	for(i=0;i<=DEVICE3;i++) {
+	base = memoryGetDeviceBaseAddress(i);
+	size = memoryGetDeviceSize(i);
+	width= memoryGetDeviceWidth(i) * 8;
+	printf("DEV %d:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
+	       i, base, size>>20, width);
+    }
+
+    /* Bootrom */
+    base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
+    size = memoryGetDeviceSize(BOOT_DEVICE);
+    width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
+    printf(" BOOT:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
+	   base, size>>20, width);
+}
diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c
new file mode 100755
index 0000000..6ab23dc
--- /dev/null
+++ b/board/evb64260/flash.c
@@ -0,0 +1,854 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * flash.c - flash support for the 512k, 8bit boot flash on the GEVB
+ *           most of this file was based on the existing U-Boot
+ *           flash drivers.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <galileo/gt64260R.h>
+#include <galileo/memory.h>
+#include "intel_flash.h"
+
+#define FLASH_ROM       0xFFFD       /* unknown flash type                   */
+#define FLASH_RAM       0xFFFE       /* unknown flash type                   */
+#define FLASH_MAN_UNKNOWN 0xFFFF0000
+
+/* #define DEBUG */
+/* #define FLASH_ID_OVERRIDE */	/* Hack to set type to 040B if ROM emulator is installed.
+				 * Can be used to program a ROM in circuit if a programmer
+				 * is not available by swapping the rom out. */
+
+/* Intel flash commands */
+int flash_erase_intel(flash_info_t *info, int s_first, int s_last);
+int write_word_intel(bank_addr_t addr, bank_word_t value);
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init (void)
+{
+	unsigned int i;
+	unsigned long size_b0 = 0, size_b1 = 0;
+	unsigned long base, flash_size;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* the boot flash */
+	base = CFG_FLASH_BASE;
+#ifndef CFG_BOOT_FLASH_WIDTH
+#define CFG_BOOT_FLASH_WIDTH	1
+#endif
+	size_b0 = flash_get_size(CFG_BOOT_FLASH_WIDTH, (vu_long *)base,
+	                         &flash_info[0]);
+
+#ifndef CONFIG_P3G4
+	printf("[");
+	print_size (size_b0, "");
+	printf("@%08lX] ", base);
+#endif
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
+			base, size_b0, size_b0<<20);
+	}
+
+	base = memoryGetDeviceBaseAddress(CFG_EXTRA_FLASH_DEVICE);
+	for(i=1;i<CFG_MAX_FLASH_BANKS;i++) {
+	    unsigned long size = flash_get_size(CFG_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]);
+
+#ifndef CONFIG_P3G4
+	    printf("[");
+	    print_size (size, "");
+	    printf("@%08lX] ", base);
+#endif
+
+	    if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+		if(i==1) {
+		    printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
+			    base, size_b1, size_b1<<20);
+		}
+		break;
+	    }
+	    size_b1+=size;
+	    base+=size;
+	}
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+	              CFG_MONITOR_BASE,
+	              CFG_MONITOR_BASE + monitor_flash_len - 1,
+	              flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef  CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+	              CFG_ENV_ADDR,
+	              CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+	              flash_get_info(CFG_ENV_ADDR));
+#endif
+
+	flash_size = size_b0 + size_b1;
+	return flash_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	int sector_size;
+
+	if(!info->sector_count) return;
+
+	/* set up sector start address table */
+	switch(info->flash_id & FLASH_TYPEMASK) {
+	    case FLASH_AM040:
+	    case FLASH_28F128J3A:
+	    case FLASH_28F640J3A:
+	    case FLASH_RAM:
+		/* this chip has uniformly spaced sectors */
+		sector_size=info->size/info->sector_count;
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sector_size);
+		break;
+	    default:
+		if (info->flash_id & FLASH_BTYPE) {
+		    /* set sector offsets for bottom boot block type	*/
+		    info->start[0] = base + 0x00000000;
+		    info->start[1] = base + 0x00008000;
+		    info->start[2] = base + 0x0000C000;
+		    info->start[3] = base + 0x00010000;
+		    for (i = 4; i < info->sector_count; i++) {
+			    info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		    }
+		} else {
+		    /* set sector offsets for top boot block type		*/
+		    i = info->sector_count - 1;
+		    info->start[i--] = base + info->size - 0x00008000;
+		    info->start[i--] = base + info->size - 0x0000C000;
+		    info->start[i--] = base + info->size - 0x00010000;
+		    for (; i >= 0; i--) {
+			    info->start[i] = base + i * 0x00020000;
+		    }
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A (64 Mbit)\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A (128 Mbit)\n");
+		break;
+	case FLASH_ROM:
+		printf ("ROM\n");
+		break;
+	case FLASH_RAM:
+		printf ("RAM\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	puts ("  Size: ");
+	print_size (info->size, "");
+	printf (" in %d Sectors\n", info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static inline void flash_cmd(int width, volatile unsigned char *addr, int offset, unsigned char cmd)
+{
+	/* supports 1x8, 1x16, and 2x16 */
+	/* 2x8 and 4x8 are not supported */
+	if(width==4) {
+	    /* assuming chips are in 16 bit mode */
+	    /* 2x16 */
+	    unsigned long cmd32=(cmd<<16)|cmd;
+	    *(volatile unsigned long *)(addr+offset*2)=cmd32;
+	} else if (width == 2) {
+	    /* 1x16 */
+	    *(volatile unsigned short *)((unsigned short*)addr+offset)=cmd;
+	} else {
+	    /* 1x8 */
+	    *(volatile unsigned char *)(addr+offset)=cmd;
+	}
+}
+
+static ulong
+flash_get_size (int portwidth, vu_long *addr, flash_info_t *info)
+{
+	short i;
+	volatile unsigned char *caddr = (unsigned char *)addr;
+	volatile unsigned short *saddr = (unsigned short *)addr;
+	volatile unsigned long *laddr = (unsigned long *)addr;
+	char old[2], save;
+	ulong id, manu, base = (ulong)addr;
+
+	info->portwidth=portwidth;
+
+	save = *caddr;
+
+	flash_cmd(portwidth,caddr,0,0xf0);
+	flash_cmd(portwidth,caddr,0,0xf0);
+
+	udelay(10);
+
+	old[0] = caddr[0];
+	old[1] = caddr[1];
+
+
+	if(old[0]!=0xf0) {
+	    flash_cmd(portwidth,caddr,0,0xf0);
+	    flash_cmd(portwidth,caddr,0,0xf0);
+
+	    udelay(10);
+
+	    if(*caddr==0xf0) {
+		/* this area is ROM */
+		*caddr=save;
+#ifndef FLASH_ID_OVERRIDE
+		info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+		info->sector_count = 8;
+		info->size = 0x80000;
+#else
+		info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		info->chipwidth=1;
+#endif
+		flash_get_offsets(base, info);
+		return info->size;
+	    }
+	} else {
+	    *caddr=0;
+
+	    udelay(10);
+
+	    if(*caddr==0) {
+		/* this area is RAM */
+		*caddr=save;
+		info->flash_id = FLASH_RAM + FLASH_MAN_UNKNOWN;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		flash_get_offsets(base, info);
+		return info->size;
+	    }
+	    flash_cmd(portwidth,caddr,0,0xf0);
+
+	    udelay(10);
+	}
+
+	/* Write auto select command: read Manufacturer ID */
+	flash_cmd(portwidth,caddr,0x555,0xAA);
+	flash_cmd(portwidth,caddr,0x2AA,0x55);
+	flash_cmd(portwidth,caddr,0x555,0x90);
+
+	udelay(10);
+
+	if ((caddr[0] == old[0]) &&
+	    (caddr[1] == old[1])) {
+
+	    /* this area is ROM */
+#ifndef FLASH_ID_OVERRIDE
+	    info->flash_id = FLASH_ROM + FLASH_MAN_UNKNOWN;
+	    info->sector_count = 8;
+	    info->size = 0x80000;
+#else
+		info->flash_id = FLASH_MAN_AMD + FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x80000;
+		info->chipwidth=1;
+#endif
+	    flash_get_offsets(base, info);
+	    return info->size;
+#ifdef DEBUG
+	} else {
+	    printf("%px%d: %02x:%02x -> %02x:%02x\n",
+		    caddr, portwidth, old[0], old[1],
+		    caddr[0], caddr[1]);
+#endif
+	}
+
+	switch(portwidth) {
+	    case 1:
+		manu = caddr[0];
+		manu |= manu<<16;
+		id = caddr[1];
+		break;
+	    case 2:
+		manu = saddr[0];
+		manu |= manu<<16;
+		id = saddr[1];
+		id |= id<<16;
+		break;
+	    case 4:
+		manu = laddr[0];
+		id = laddr[1];
+		break;
+	default:
+		id = manu = -1;
+		break;
+	}
+
+#ifdef DEBUG
+	printf("\n%08lx:%08lx:%08lx\n", base, manu, id);
+	printf("%08lx %08lx %08lx %08lx\n",
+		laddr[0],laddr[1],laddr[2],laddr[3]);
+#endif
+
+	switch (manu) {
+	    case AMD_MANUFACT:
+		    info->flash_id = FLASH_MAN_AMD;
+		    break;
+	    case FUJ_MANUFACT:
+		    info->flash_id = FLASH_MAN_FUJ;
+		    break;
+	    case INTEL_MANUFACT:
+		    info->flash_id = FLASH_MAN_INTEL;
+		    break;
+	    default:
+		    printf("Unknown Mfr [%08lx]:%08lx\n", manu, id);
+		    info->flash_id = FLASH_UNKNOWN;
+		    info->sector_count = 0;
+		    info->size = 0;
+		    return (0);			/* no or unknown flash	*/
+	}
+
+	switch (id) {
+	    case AMD_ID_LV400T:
+		    info->flash_id += FLASH_AM400T;
+		    info->sector_count = 11;
+		    info->size = 0x00100000;
+		    info->chipwidth=1;
+		    break;				/* => 1 MB	*/
+
+	    case AMD_ID_LV400B:
+		    info->flash_id += FLASH_AM400B;
+		    info->sector_count = 11;
+		    info->size = 0x00100000;
+		    info->chipwidth=1;
+		    break;				/* => 1 MB	*/
+
+	    case AMD_ID_LV800T:
+		    info->flash_id += FLASH_AM800T;
+		    info->sector_count = 19;
+		    info->size = 0x00200000;
+		    info->chipwidth=1;
+		    break;				/* => 2 MB	*/
+
+	    case AMD_ID_LV800B:
+		    info->flash_id += FLASH_AM800B;
+		    info->sector_count = 19;
+		    info->size = 0x00200000;
+		    info->chipwidth=1;
+		    break;				/* => 2 MB	*/
+
+	    case AMD_ID_LV160T:
+		    info->flash_id += FLASH_AM160T;
+		    info->sector_count = 35;
+		    info->size = 0x00400000;
+		    info->chipwidth=1;
+		    break;				/* => 4 MB	*/
+
+	    case AMD_ID_LV160B:
+		    info->flash_id += FLASH_AM160B;
+		    info->sector_count = 35;
+		    info->size = 0x00400000;
+		    info->chipwidth=1;
+		    break;				/* => 4 MB	*/
+#if 0	/* enable when device IDs are available */
+	    case AMD_ID_LV320T:
+		    info->flash_id += FLASH_AM320T;
+		    info->sector_count = 67;
+		    info->size = 0x00800000;
+		    break;				/* => 8 MB	*/
+
+	    case AMD_ID_LV320B:
+		    info->flash_id += FLASH_AM320B;
+		    info->sector_count = 67;
+		    info->size = 0x00800000;
+		    break;				/* => 8 MB	*/
+#endif
+	    case AMD_ID_LV040B:
+		    info->flash_id += FLASH_AM040;
+		    info->sector_count = 8;
+		    info->size = 0x80000;
+		    info->chipwidth=1;
+		    break;
+
+	    case INTEL_ID_28F640J3A:
+		    info->flash_id += FLASH_28F640J3A;
+		    info->sector_count = 64;
+		    info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */
+		    info->chipwidth=2;
+		    if(portwidth==4) info->size*=2;	/* 2x16 */
+		    break;
+
+	    case INTEL_ID_28F128J3A:
+		    info->flash_id += FLASH_28F128J3A;
+		    info->sector_count = 128;
+		    info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */
+		    info->chipwidth=2;
+		    if(portwidth==4) info->size*=2;	/* 2x16 */
+		    break;
+
+	    default:
+		    printf("Unknown id %lx:[%lx]\n", manu, id);
+		    info->flash_id = FLASH_UNKNOWN;
+		    info->chipwidth=1;
+		    return (0);			/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets(base, info);
+
+#if 0
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_AM040) {
+		/* this chip has uniformly spaced sectors */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+#endif
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0)=0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		saddr = (volatile unsigned short *)(info->start[i]);
+		laddr = (volatile unsigned long *)(info->start[i]);
+		if(portwidth==1)
+		    info->protect[i] = caddr[2] & 1;
+		else if(portwidth==2)
+		    info->protect[i] = saddr[2] & 1;
+		else
+		    info->protect[i] = laddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (volatile unsigned char *)info->start[0];
+
+		flash_cmd(portwidth,caddr,0,0xF0);	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+/* TODO: 2x16 unsupported */
+int
+flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (uchar *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	/* TODO: 2x16 unsupported */
+	if(info->portwidth==4) return 1;
+
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+	    for (sect = s_first; sect<=s_last; sect++) {
+		int sector_size=info->size/info->sector_count;
+		addr = (uchar *)(info->start[sect]);
+		memset((void *)addr, 0, sector_size);
+	    }
+	    return 0;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL)  {
+		return flash_erase_intel(info,
+				(unsigned short)s_first,
+				(unsigned short)s_last);
+	}
+
+#if 0
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+#endif
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_cmd(info->portwidth,addr,0x555,0xAA);
+	flash_cmd(info->portwidth,addr,0x2AA,0x55);
+	flash_cmd(info->portwidth,addr,0x555,0x80);
+	flash_cmd(info->portwidth,addr,0x555,0xAA);
+	flash_cmd(info->portwidth,addr,0x2AA,0x55);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (uchar *)(info->start[sect]);
+			flash_cmd(info->portwidth,addr,0,0x30);
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile unsigned char *)(info->start[l_sect]);
+	/* broken for 2x16: TODO */
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *)info->start[0];
+	flash_cmd(info->portwidth,addr,0,0xf0);
+	flash_cmd(info->portwidth,addr,0,0xf0);
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+/* broken for 2x16: TODO */
+int
+write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if(info->portwidth==4) return 1;
+
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0;
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+	    memcpy((void *)addr, src, cnt);
+	    return 0;
+	}
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+/* broken for 2x16: TODO */
+static int
+write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (uchar *)(info->start[0]);
+	ulong start;
+	int flag, i;
+
+	if(info->portwidth==4) return 1;
+
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
+	if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
+	    *(unsigned long *)dest=data;
+	    return 0;
+	}
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)  {
+		unsigned short low = data & 0xffff;
+		unsigned short hi  = (data >> 16) & 0xffff;
+		int ret = write_word_intel((bank_addr_t)dest, hi);
+
+		if (!ret) ret = write_word_intel((bank_addr_t)(dest+2), low);
+
+		return ret;
+	}
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* first, perform an unlock bypass command to speed up flash writes */
+	addr[0x555] = 0xAA;
+	addr[0x2AA] = 0x55;
+	addr[0x555] = 0x20;
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *)&data;
+		addr[0] = 0xA0;
+		*(((char *)dest)+i) = data_ch[i];
+		udelay(10); /* XXX */
+	}
+
+	/* we're done, now do an unlock bypass reset */
+	addr[0] = 0x90;
+	addr[0] = 0x00;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c
new file mode 100755
index 0000000..c62b647
--- /dev/null
+++ b/board/evb64260/i2c.c
@@ -0,0 +1,315 @@
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include <galileo/gt64260R.h>
+#include <galileo/core.h>
+
+#define MAX_I2C_RETRYS	    10
+#define I2C_DELAY	    1000  /* Should be at least the # of MHz of Tclk */
+#undef	DEBUG_I2C
+
+#ifdef DEBUG_I2C
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+/* Assuming that there is only one master on the bus (us) */
+
+static void
+i2c_init(int speed, int slaveaddr)
+{
+	unsigned int n, m, freq, margin, power;
+	unsigned int actualFreq, actualN=0, actualM=0;
+	unsigned int control, status;
+	unsigned int minMargin = 0xffffffff;
+	unsigned int tclk = 125000000;
+
+	DP(puts("i2c_init\n"));
+
+	for(n = 0 ; n < 8 ; n++)
+	{
+		for(m = 0 ; m < 16 ; m++)
+		{
+			power = 2<<n; /* power = 2^(n+1) */
+			freq = tclk/(10*(m+1)*power);
+			if (speed > freq)
+				margin = speed - freq;
+			else
+				margin = freq - speed;
+			if(margin < minMargin)
+			{
+				minMargin   = margin;
+				actualFreq  = freq;
+				actualN	    = n;
+				actualM	    = m;
+			}
+		}
+	}
+
+	DP(puts("setup i2c bus\n"));
+
+	/* Setup bus */
+
+	GT_REG_WRITE(I2C_SOFT_RESET, 0);
+
+	DP(puts("udelay...\n"));
+
+	udelay(I2C_DELAY);
+
+	DP(puts("set baudrate\n"));
+
+	GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN);
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6));
+
+	udelay(I2C_DELAY * 10);
+
+	DP(puts("read control, baudrate\n"));
+
+	GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+	GT_REG_READ(I2C_CONTROL, &control);
+}
+
+static uchar
+i2c_start(void)
+{
+	unsigned int control, status;
+	int count = 0;
+
+	DP(puts("i2c_start\n"));
+
+	/* Set the start bit */
+
+	GT_REG_READ(I2C_CONTROL, &control);
+	control |= (0x1 << 5);
+	GT_REG_WRITE(I2C_CONTROL, control);
+
+	GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+
+	count = 0;
+	while ((status & 0xff) != 0x08) {
+		udelay(I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+			return (status);
+		}
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	return (0);
+}
+
+static uchar
+i2c_select_device(uchar dev_addr, uchar read, int ten_bit)
+{
+	unsigned int status, data, bits = 7;
+	int count = 0;
+
+	DP(puts("i2c_select_device\n"));
+
+	/* Output slave address */
+
+	if (ten_bit) {
+		bits = 10;
+	}
+
+	data = (dev_addr << 1);
+	/* set the read bit */
+	data |= read;
+	GT_REG_WRITE(I2C_DATA, data);
+	/* assert the address */
+	RESET_REG_BITS(I2C_CONTROL, BIT3);
+
+	udelay(I2C_DELAY);
+
+	GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+	count = 0;
+	while (((status & 0xff) != 0x40) && ((status & 0xff) != 0x18)) {
+		udelay(I2C_DELAY);
+		if (count > 20) {
+			GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+			return(status);
+		}
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+
+	if (bits == 10) {
+		printf("10 bit I2C addressing not yet implemented\n");
+		return (0xff);
+	}
+
+	return (0);
+}
+
+static uchar
+i2c_get_data(uchar* return_data, int len) {
+
+	unsigned int data, status = 0;
+	int count = 0;
+
+	DP(puts("i2c_get_data\n"));
+
+	while (len) {
+
+		/* Get and return the data */
+
+		RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
+
+		udelay(I2C_DELAY * 5);
+
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x50) {
+			udelay(I2C_DELAY);
+			if(count > 2) {
+				GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+				return 0;
+			}
+			GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		GT_REG_READ(I2C_DATA, &data);
+		len--;
+		*return_data = (uchar)data;
+		return_data++;
+	}
+	RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3);
+	while ((status & 0xff) != 0x58) {
+		udelay(I2C_DELAY);
+		if(count > 200) {
+			GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+			return (status);
+		}
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+	}
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */
+
+	return (0);
+}
+
+static uchar
+i2c_write_data(unsigned int data, int len)
+{
+	unsigned int status;
+	int count = 0;
+
+	DP(puts("i2c_write_data\n"));
+
+	if (len > 4)
+		return -1;
+
+	while (len) {
+		/* Set and assert the data */
+
+		GT_REG_WRITE(I2C_DATA, (unsigned int)data);
+		RESET_REG_BITS(I2C_CONTROL, (0x1 << 3));
+
+		udelay(I2C_DELAY);
+
+		GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+		count++;
+		while ((status & 0xff) != 0x28) {
+			udelay(I2C_DELAY);
+			if(count > 20) {
+				GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/
+				return (status);
+			}
+			GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status);
+			count++;
+		}
+		len--;
+	}
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 3) | (0x1 << 4));
+	GT_REG_WRITE(I2C_CONTROL, (0x1 << 4));
+
+	udelay(I2C_DELAY * 10);
+
+	return (0);
+}
+
+static uchar
+i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit)
+{
+	uchar status;
+
+	DP(puts("i2c_set_dev_offset\n"));
+
+	status = i2c_select_device(dev_addr, 0, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Failed to select device setting offset: 0x%02x\n",
+		       status);
+#endif
+		return status;
+	}
+
+	status = i2c_write_data(offset, 1);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Failed to write data: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return (0);
+}
+
+uchar
+i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data,
+	 int ten_bit)
+{
+	uchar status = 0;
+	unsigned int i2cFreq = 400000;
+
+	DP(puts("i2c_read\n"));
+
+	i2c_init(i2cFreq,0);
+
+	status = i2c_start();
+
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Transaction start failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_set_dev_offset(dev_addr, 0, 0);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Failed to set offset: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	i2c_init(i2cFreq,0);
+
+	status = i2c_start();
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Transaction restart failed: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_select_device(dev_addr, 1, ten_bit);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Address not acknowledged: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	status = i2c_get_data(data, len);
+	if (status) {
+#ifdef DEBUG_I2C
+		printf("Data not recieved: 0x%02x\n", status);
+#endif
+		return status;
+	}
+
+	return 0;
+}
diff --git a/board/evb64260/i2c.h b/board/evb64260/i2c.h
new file mode 100755
index 0000000..9c21992
--- /dev/null
+++ b/board/evb64260/i2c.h
@@ -0,0 +1,7 @@
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/* function declarations */
+uchar i2c_read(uchar, unsigned int, int, uchar*, int);
+
+#endif
diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c
new file mode 100755
index 0000000..ed6a2a0
--- /dev/null
+++ b/board/evb64260/intel_flash.c
@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the Hymod board by Murray.Jensen@cmst.csiro.au, 20-Oct-00
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <galileo/gt64260R.h>
+#include <galileo/memory.h>
+#include "intel_flash.h"
+
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+static void
+bank_reset(flash_info_t *info, int sect)
+{
+	bank_addr_t addrw, eaddrw;
+
+	addrw = (bank_addr_t)info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD(addrw);
+
+	while (addrw < eaddrw) {
+#ifdef FLASH_DEBUG
+		printf("  writing reset cmd to addr 0x%08lx\n",
+			(unsigned long)addrw);
+#endif
+		*addrw = BANK_CMD_RST;
+		addrw++;
+	}
+}
+
+static void
+bank_erase_init(flash_info_t *info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int flag;
+
+#ifdef FLASH_DEBUG
+	printf("0x%08x BANK_CMD_PROG\n", BANK_CMD_PROG);
+	printf("0x%08x BANK_CMD_ERASE1\n", BANK_CMD_ERASE1);
+	printf("0x%08x BANK_CMD_ERASE2\n", BANK_CMD_ERASE2);
+	printf("0x%08x BANK_CMD_CLR_STAT\n", BANK_CMD_CLR_STAT);
+	printf("0x%08x BANK_CMD_RST\n", BANK_CMD_RST);
+	printf("0x%08x BANK_STAT_RDY\n", BANK_STAT_RDY);
+	printf("0x%08x BANK_STAT_ERR\n", BANK_STAT_ERR);
+#endif
+
+	saddrw = (bank_addr_t)info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD(saddrw);
+
+#ifdef FLASH_DEBUG
+	printf("erasing sector %d, start addr = 0x%08lx "
+		"(bank next word addr = 0x%08lx)\n", sect,
+		(unsigned long)saddrw, (unsigned long)eaddrw);
+#endif
+
+	/* Disable intrs which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+#ifdef FLASH_DEBUG
+		printf("  writing erase cmd to addr 0x%08lx\n",
+			(unsigned long)addrw);
+#endif
+		*addrw = BANK_CMD_ERASE1;
+		*addrw = BANK_CMD_ERASE2;
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+}
+
+static int
+bank_erase_poll(flash_info_t *info, int sect)
+{
+	bank_addr_t addrw, saddrw, eaddrw;
+	int sectdone, haderr;
+
+	saddrw = (bank_addr_t)info->start[sect];
+	eaddrw = BANK_ADDR_NEXT_WORD(saddrw);
+
+	sectdone = 1;
+	haderr = 0;
+
+	for (addrw = saddrw; addrw < eaddrw; addrw++) {
+		bank_word_t stat = *addrw;
+
+#ifdef FLASH_DEBUG
+		printf("  checking status at addr "
+			"0x%08x [0x%08x]\n",
+			(unsigned long)addrw, stat);
+#endif
+		if ((stat & BANK_STAT_RDY) != BANK_STAT_RDY)
+			sectdone = 0;
+		else if ((stat & BANK_STAT_ERR) != 0) {
+			printf(" failed on sector %d "
+				"(stat = 0x%08x) at "
+				"address 0x%p\n",
+				sect, stat, addrw);
+			*addrw = BANK_CMD_CLR_STAT;
+			haderr = 1;
+		}
+	}
+
+	if (haderr)
+		return (-1);
+	else
+		return (sectdone);
+}
+
+int
+write_word_intel(bank_addr_t addr, bank_word_t value)
+{
+	bank_word_t stat;
+	ulong start;
+	int flag, retval;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = BANK_CMD_PROG;
+
+	*addr = value;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	retval = 0;
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	do {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			retval = 1;
+			goto done;
+		}
+		stat = *addr;
+	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
+
+	if ((stat & BANK_STAT_ERR) != 0) {
+		printf("flash program failed (stat = 0x%08lx) "
+			"at address 0x%08lx\n", (ulong)stat, (ulong)addr);
+		*addr = BANK_CMD_CLR_STAT;
+		retval = 3;
+	}
+
+done:
+	/* reset to read mode */
+	*addr = BANK_CMD_RST;
+
+	return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase_intel(flash_info_t *info, int s_first, int s_last)
+{
+	int prot, sect, haderr;
+	ulong start, now, last;
+
+#ifdef FLASH_DEBUG
+	printf("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+		(info - flash_info) + 1);
+	flash_print_info(info);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sector%s will not be erased!\n",
+			prot, (prot > 1 ? "s" : ""));
+	}
+
+	start = get_timer (0);
+	last = 0;
+	haderr = 0;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			ulong estart;
+			int sectdone;
+
+			bank_erase_init(info, sect);
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			estart = get_timer(start);
+
+			do {
+				now = get_timer(start);
+
+				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout (sect %d)\n", sect);
+					haderr = 1;
+					break;
+				}
+
+#ifndef FLASH_DEBUG
+				/* show that we're waiting */
+				if ((now - last) > 1000) { /* every second */
+					putc ('.');
+					last = now;
+				}
+#endif
+
+				sectdone = bank_erase_poll(info, sect);
+
+				if (sectdone < 0) {
+					haderr = 1;
+					break;
+				}
+
+			} while (!sectdone);
+
+			if (haderr)
+				break;
+		}
+	}
+
+	if (haderr > 0)
+		printf (" failed\n");
+	else
+		printf (" done\n");
+
+	/* reset to read mode */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			bank_reset(info, sect);
+		}
+	}
+	return haderr;
+}
diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h
new file mode 100755
index 0000000..dc2aa00
--- /dev/null
+++ b/board/evb64260/intel_flash.h
@@ -0,0 +1,160 @@
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/*
+ * acceptable chips types are:
+ *
+ *	28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
+ */
+
+/* register addresses, valid only following an CHIP_CMD_RD_ID command */
+#define CHIP_ADDR_REG_MAN	0x000000	/* manufacturer's id */
+#define CHIP_ADDR_REG_DEV	0x000001	/* device id */
+#define CHIP_ADDR_REG_CFGM	0x000003	/* master lock config */
+#define CHIP_ADDR_REG_CFG(b)	(((b)<<16)|2)	/* lock config for block b */
+
+/* Commands */
+#define CHIP_CMD_RST		0xFF		/* reset flash */
+#define CHIP_CMD_RD_ID		0x90		/* read the id and lock bits */
+#define CHIP_CMD_RD_QUERY	0x98		/* read device capabilities */
+#define CHIP_CMD_RD_STAT	0x70		/* read the status register */
+#define CHIP_CMD_CLR_STAT	0x50		/* clear the staus register */
+#define CHIP_CMD_WR_BUF		0xE8		/* clear the staus register */
+#define CHIP_CMD_PROG		0x40		/* program word command */
+#define CHIP_CMD_ERASE1		0x20		/* 1st word for block erase */
+#define CHIP_CMD_ERASE2		0xD0		/* 2nd word for block erase */
+#define CHIP_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
+#define CHIP_CMD_LOCK		0x60		/* 1st word for all lock cmds */
+#define CHIP_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
+#define CHIP_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
+#define CHIP_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define CHIP_STAT_DPS		0x02		/* Device Protect Status */
+#define CHIP_STAT_VPPS		0x08		/* VPP Status */
+#define CHIP_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
+#define CHIP_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
+#define CHIP_STAT_ESS		0x40		/* Erase Suspend Status */
+#define CHIP_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
+
+#define CHIP_STAT_ERR		(CHIP_STAT_VPPS | CHIP_STAT_DPS | \
+				    CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
+
+/* ID and Lock Configuration */
+#define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
+#define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
+#define CHIP_RD_ID_DEV		CFG_FLASH_ID
+
+/* dimensions */
+#define CHIP_WIDTH		2		/* chips are in 16 bit mode */
+#define CHIP_WSHIFT		1		/* (log2 of CHIP_WIDTH) */
+#define CHIP_NBLOCKS		128
+#define CHIP_BLKSZ		(128 * 1024)	/* of 128Kbytes each */
+#define CHIP_SIZE		(CHIP_BLKSZ * CHIP_NBLOCKS)
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * The hymod board has 2 x 28F320J5 chips running in
+ * 16 bit mode, for a 32 bit wide bank.
+ */
+
+typedef unsigned short bank_word_t;		/* 8/16/32/64bit unsigned int */
+typedef volatile bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t;		/* want this big - >= 32 bit */
+
+#define BANK_CHIP_WIDTH		1		/* each bank is 1 chip wide */
+#define BANK_CHIP_WSHIFT	0		/* (log2 of BANK_CHIP_WIDTH) */
+
+#define BANK_WIDTH		(CHIP_WIDTH * BANK_CHIP_WIDTH)
+#define BANK_WSHIFT		(CHIP_WSHIFT + BANK_CHIP_WSHIFT)
+#define BANK_NBLOCKS		CHIP_NBLOCKS
+#define BANK_BLKSZ		(CHIP_BLKSZ * BANK_CHIP_WIDTH)
+#define BANK_SIZE		(CHIP_SIZE * BANK_CHIP_WIDTH)
+
+#define MAX_BANKS		1		/* only one bank possible */
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_WIDTH - 1)))
+#define BANK_SIZE_WORD_ALIGN(s)	((bank_size_t)BANK_ADDR_WORD_ALIGN( \
+				    (bank_size_t)(s) + (BANK_WIDTH - 1)))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_BLKSZ - 1)))
+#define BANK_SIZE_BLK_ALIGN(s)	((bank_size_t)BANK_ADDR_BLK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_BLKSZ - 1)))
+
+/* align bank addresses and sizes to bank boundaries */
+#define BANK_ADDR_BANK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(BANK_SIZE - 1)))
+#define BANK_SIZE_BANK_ALIGN(s)	((bank_size_t)BANK_ADDR_BANK_ALIGN( \
+				    (bank_size_t)(s) + (BANK_SIZE - 1)))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o)	(bank_addr_t)((bank_size_t)(a) + \
+				    (bank_size_t)(o))
+
+/* get base address of bank b, given flash base address a */
+#define BANK_ADDR_BASE(a, b)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    (bank_size_t)(b) * BANK_SIZE)
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+				    BANK_WIDTH)
+#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+				    BANK_BLKSZ)
+#define BANK_ADDR_NEXT_BANK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    BANK_SIZE)
+
+/* get bank address of chip register r given a bank base address a */
+#define BANK_ADDR_REG(a, r)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
+				    ((bank_size_t)(r) << BANK_WSHIFT))
+
+/* make a bank address for each chip register address */
+
+#define BANK_ADDR_REG_MAN(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
+#define BANK_ADDR_REG_DEV(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
+#define BANK_ADDR_REG_CFGM(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
+#define BANK_ADDR_REG_CFG(b,a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
+
+/*
+ * replicate a chip cmd/stat/rd value into each byte position within a word
+ * so that multiple chips are accessed in a single word i/o operation
+ *
+ * this must be as wide as the bank_word_t type, and take into account the
+ * chip width and bank layout
+ */
+
+#define BANK_FILL_WORD(o)	((bank_word_t)(o))
+
+/* make a bank word value for each chip cmd/stat/rd value */
+
+/* Commands */
+#define BANK_CMD_RST		BANK_FILL_WORD(CHIP_CMD_RST)
+#define BANK_CMD_RD_ID		BANK_FILL_WORD(CHIP_CMD_RD_ID)
+#define BANK_CMD_RD_STAT	BANK_FILL_WORD(CHIP_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1		BANK_FILL_WORD(CHIP_CMD_ERASE1)
+#define BANK_CMD_ERASE2		BANK_FILL_WORD(CHIP_CMD_ERASE2)
+#define BANK_CMD_PROG		BANK_FILL_WORD(CHIP_CMD_PROG)
+#define BANK_CMD_LOCK		BANK_FILL_WORD(CHIP_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS		BANK_FILL_WORD(CHIP_STAT_DPS)
+#define BANK_STAT_PSS		BANK_FILL_WORD(CHIP_STAT_PSS)
+#define BANK_STAT_VPPS		BANK_FILL_WORD(CHIP_STAT_VPPS)
+#define BANK_STAT_PSLBS		BANK_FILL_WORD(CHIP_STAT_PSLBS)
+#define BANK_STAT_ECLBS		BANK_FILL_WORD(CHIP_STAT_ECLBS)
+#define BANK_STAT_ESS		BANK_FILL_WORD(CHIP_STAT_ESS)
+#define BANK_STAT_RDY		BANK_FILL_WORD(CHIP_STAT_RDY)
+
+#define BANK_STAT_ERR		BANK_FILL_WORD(CHIP_STAT_ERR)
+
+/* ID and Lock Configuration */
+#define BANK_RD_ID_LOCK		BANK_FILL_WORD(CHIP_RD_ID_LOCK)
+#define BANK_RD_ID_MAN		BANK_FILL_WORD(CHIP_RD_ID_MAN)
+#define BANK_RD_ID_DEV		BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/evb64260/local.h b/board/evb64260/local.h
new file mode 100755
index 0000000..3d9b443
--- /dev/null
+++ b/board/evb64260/local.h
@@ -0,0 +1,62 @@
+/*
+ * include/local.h - local configuration options, board specific
+ */
+
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* This tells U-Boot that the config options are compiled in */
+/* #undef ENV_IS_EMBEDDED */
+/* Don't touch this! U-Boot figures this out  based on other
+ * magic. */
+
+/* Uncomment and define any of the below options */
+
+/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */
+			/* Note: If you defined CONFIG_EVB64260_750CX this */
+			/* gets defined automatically. */
+
+/* These want string arguments */
+/* #define CONFIG_BOOTARGS */
+/* #define CONFIG_BOOTCOMMAND */
+/* #define CONFIG_RAMBOOTCOMMAND */
+/* #define CONFIG_NFSBOOTCOMMAND */
+/* #define CFG_AUTOLOAD */
+/* #define CONFIG_PREBOOT */
+
+/* These don't */
+
+/* #define CONFIG_BOOTDELAY  */
+/* #define CONFIG_BAUDRATE */
+/* #define CONFIG_LOADS_ECHO */
+/* #define CONFIG_ETHADDR */
+/* #define CONFIG_ETH2ADDR */
+/* #define CONFIG_ETH3ADDR */
+/* #define CONFIG_IPADDR */
+/* #define CONFIG_SERVERIP */
+/* #define CONFIG_ROOTPATH */
+/* #define CONFIG_GATEWAYIP */
+/* #define CONFIG_NETMASK */
+/* #define CONFIG_HOSTNAME */
+/* #define CONFIG_BOOTFILE */
+/* #define CONFIG_LOADADDR */
+
+/* these hardware addresses are pretty bogus, please change them to
+   suit your needs */
+
+/* first ethernet */
+#define CONFIG_ETHADDR          00:11:22:33:44:55
+
+/* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:11:22:33:44:66
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR		00:11:22:33:44:77
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
diff --git a/board/evb64260/memory.c b/board/evb64260/memory.c
new file mode 100755
index 0000000..e339854
--- /dev/null
+++ b/board/evb64260/memory.c
@@ -0,0 +1,457 @@
+/* Memory.c - Memory mappings and remapping functions */
+
+/* Copyright - Galileo technology. */
+
+/* modified by Josh Huber to clean some things up, and
+ * fit it into the U-Boot framework */
+
+#include <galileo/core.h>
+#include <galileo/memory.h>
+
+/********************************************************************
+* memoryGetBankBaseAddress - Gets the base address of a memory bank
+*      - If the memory bank size is 0 then this base address has no meaning!!!
+*
+*
+* INPUTS:   MEMORY_BANK bank - The bank we ask for its base Address.
+* OUTPUT:   N/A
+* RETURNS: Memory bank base address.
+*********************************************************************/
+static unsigned long memoryGetBankRegOffset(MEMORY_BANK bank)
+{
+    switch (bank)
+    {
+	case BANK0:
+	    return SCS_0_LOW_DECODE_ADDRESS;
+	case BANK1:
+	    return SCS_1_LOW_DECODE_ADDRESS;
+	case BANK2:
+	    return SCS_2_LOW_DECODE_ADDRESS;
+	case BANK3:
+	    return SCS_3_LOW_DECODE_ADDRESS;
+    }
+    return SCS_0_LOW_DECODE_ADDRESS; /* default value */
+}
+
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank)
+{
+    unsigned int base;
+    unsigned int regOffset=memoryGetBankRegOffset(bank);
+
+    GT_REG_READ(regOffset,&base);
+    base = base << 20;
+    return base;
+}
+
+/********************************************************************
+* memoryGetDeviceBaseAddress - Gets the base address of a device.
+*           - If the device size is 0 then this base address has no meaning!!!
+*
+*
+* INPUT:   DEVICE device - The device we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: Device base address.
+*********************************************************************/
+static unsigned int memoryGetDeviceRegOffset(DEVICE device)
+{
+    switch (device)
+    {
+	case DEVICE0:
+	    return CS_0_LOW_DECODE_ADDRESS;
+	case DEVICE1:
+	    return CS_1_LOW_DECODE_ADDRESS;
+	case DEVICE2:
+	    return CS_2_LOW_DECODE_ADDRESS;
+	case DEVICE3:
+	    return CS_3_LOW_DECODE_ADDRESS;
+	case BOOT_DEVICE:
+	    return BOOTCS_LOW_DECODE_ADDRESS;
+    }
+    return CS_0_LOW_DECODE_ADDRESS; /* default value */
+}
+
+unsigned int memoryGetDeviceBaseAddress(DEVICE device)
+{
+    unsigned int regBase;
+    unsigned int regEnd;
+    unsigned int regOffset=memoryGetDeviceRegOffset(device);
+
+    GT_REG_READ(regOffset, &regBase);
+    GT_REG_READ(regOffset+8, &regEnd);
+
+    if(regEnd<=regBase) return 0xffffffff;	/* ERROR !!! */
+
+    regBase = regBase << 20;
+    return regBase;
+}
+
+/********************************************************************
+* memoryGetBankSize - Returns the size of a memory bank.
+*
+*
+* INPUT:    MEMORY_BANK bank - The bank we ask for its size.
+* OUTPUT:   N/A
+* RETURNS: Memory bank size.
+*********************************************************************/
+unsigned int memoryGetBankSize(MEMORY_BANK bank)
+{
+    unsigned int size,base;
+    unsigned int highValue;
+    unsigned int highAddress=memoryGetBankRegOffset(bank)+8;
+
+    base = memoryGetBankBaseAddress(bank);
+    GT_REG_READ(highAddress,&highValue);
+    highValue = (highValue + 1) << 20;
+    if(base > highValue)
+	size=0;
+    else
+	size = highValue - base;
+    return size;
+}
+
+/********************************************************************
+* memoryGetDeviceSize - Returns the size of a device memory space
+*
+*
+* INPUT:    DEVICE device - The device we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS:  Size of a device memory space.
+*********************************************************************/
+unsigned int memoryGetDeviceSize(DEVICE device)
+{
+    unsigned int size,base;
+    unsigned int highValue;
+    unsigned int highAddress=memoryGetDeviceRegOffset(device)+8;
+
+    base = memoryGetDeviceBaseAddress(device);
+    GT_REG_READ(highAddress,&highValue);
+    if (highValue == 0xfff)
+    {
+	size = (~base) + 1;	/* what the heck is this? */
+	return size;
+    }
+    else
+	highValue = (highValue + 1) << 20;
+
+    if(base > highValue)
+	size=0;
+    else
+	size = highValue - base;
+    return size;
+}
+
+/********************************************************************
+* memoryGetDeviceWidth - A device can be with: 1,2,4 or 8 Bytes data width.
+*                  The width is determine in registers: 'Device Parameters'
+*                  registers (0x45c, 0x460, 0x464, 0x468, 0x46c - for each device.
+*                  at bits: [21:20].
+*
+* INPUT:    DEVICE device - Device number
+* OUTPUT:   N/A
+* RETURNS:  Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
+*********************************************************************/
+unsigned int memoryGetDeviceWidth(DEVICE device)
+{
+    unsigned int width;
+    unsigned int regValue;
+
+    GT_REG_READ(DEVICE_BANK0PARAMETERS + device*4,&regValue);
+    width =  (regValue & 0x00300000) >> 20;
+    switch (width)
+    {
+	case 0:
+	    return 1;
+	case 1:
+	    return 2;
+	case 2:
+	    return 4;
+	case 3:
+	    return 8;
+	default:
+	    return 0;
+    }
+}
+
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength)
+{
+    unsigned int low=0xfff;
+    unsigned int high=0x0;
+    unsigned int regOffset=memoryGetBankRegOffset(bank);
+
+    if(bankLength!=0) {
+	low = (bankBase >> 20) & 0xffff;
+	high=((bankBase+bankLength)>>20)-1;
+    }
+
+#ifdef DEBUG
+    {
+	unsigned int oldLow, oldHigh;
+	GT_REG_READ(regOffset,&oldLow);
+	GT_REG_READ(regOffset+8,&oldHigh);
+
+	printf("b%d %x-%x->%x-%x\n", bank, oldLow, oldHigh, low, high);
+    }
+#endif
+
+    GT_REG_WRITE(regOffset,low);
+    GT_REG_WRITE(regOffset+8,high);
+
+    return true;
+}
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength)
+{
+    /* TODO: what are appropriate "unmapped" values? */
+    unsigned int low=0xfff;
+    unsigned int high=0x0;
+    unsigned int regOffset=memoryGetDeviceRegOffset(device);
+
+    if(deviceLength != 0) {
+	low=deviceBase>>20;
+	high=((deviceBase+deviceLength)>>20)-1;
+    } else {
+	/* big problems in here... */
+	/* this will HANG */
+    }
+
+    GT_REG_WRITE(regOffset,low);
+    GT_REG_WRITE(regOffset+8,high);
+
+    return true;
+}
+
+
+/********************************************************************
+* memoryMapInternalRegistersSpace - Sets new base address for the internals
+*                                   registers.
+*
+* INPUTS:  unsigned int internalRegBase - The new base address.
+* RETURNS: true on success, false on failure
+*********************************************************************/
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase)
+{
+    unsigned int currentValue;
+    unsigned int internalValue = internalRegBase;
+
+    internalRegBase = (internalRegBase >> 20);
+    GT_REG_READ(INTERNAL_SPACE_DECODE,&currentValue);
+    internalRegBase = (currentValue & 0xffff0000) | internalRegBase;
+    GT_REG_WRITE(INTERNAL_SPACE_DECODE,internalRegBase);
+    INTERNAL_REG_BASE_ADDR = internalValue;
+    return true;
+}
+
+/********************************************************************
+* memoryGetInternalRegistersSpace - Gets internal registers Base Address.
+*
+* INPUTS:  unsigned int internalRegBase - The new base address.
+* RETURNS: true on success, false on failure
+*********************************************************************/
+unsigned int memoryGetInternalRegistersSpace(void)
+{
+    return INTERNAL_REG_BASE_ADDR;
+}
+
+/********************************************************************
+* memorySetProtectRegion - This function modifys one of the 8 regions with
+*                          one of the three protection mode.
+*                        - Be advised to check the spec before modifying them.
+*
+*
+* Inputs: CPU_PROTECT_REGION - one of the eight regions.
+*         CPU_ACCESS - general access.
+*         CPU_WRITE - read only access.
+*         CPU_CACHE_PROTECT - chache access.
+*      we defining CPU because there is another protect from the pci SIDE.
+* Returns: false if one of the parameters is wrong and true else
+*********************************************************************/
+bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+			    MEMORY_ACCESS memAccess,
+			    MEMORY_ACCESS_WRITE memWrite,
+			    MEMORY_CACHE_PROTECT cacheProtection,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+    unsigned int protectHigh = baseAddress + regionLength;
+
+    if(regionLength == 0) /* closing the region */
+    {
+	GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,0x0000ffff);
+	GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,0);
+	return true;
+    }
+    baseAddress =  (baseAddress & 0xfff00000) >> 20;
+    baseAddress = baseAddress | memAccess << 16 |  memWrite << 17
+		     | cacheProtection << 18;
+    GT_REG_WRITE(CPU_LOW_PROTECT_ADDRESS_0 + 0x10*region,baseAddress);
+    protectHigh = (protectHigh & 0xfff00000) >> 20;
+    GT_REG_WRITE(CPU_HIGH_PROTECT_ADDRESS_0 + 0x10*region,protectHigh - 1);
+    return true;
+}
+
+/********************************************************************
+* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
+*                            supports Cache Coherency.
+*
+*
+* Inputs: SNOOP_REGION region - One of the four regions.
+*         SNOOP_TYPE snoopType - There is four optional Types:
+*                               1. No Snoop.
+*                               2. Snoop to WT region.
+*                               3. Snoop to WB region.
+*                               4. Snoop & Invalidate to WB region.
+*         unsigned int baseAddress - Base Address of this region.
+*         unsigned int topAddress - Top Address of this region.
+* Returns: false if one of the parameters is wrong and true else
+*********************************************************************/
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+			      MEMORY_SNOOP_TYPE snoopType,
+			      unsigned int baseAddress,
+			      unsigned int regionLength)
+{
+    unsigned int snoopXbaseAddress;
+    unsigned int snoopXtopAddress;
+    unsigned int data;
+    unsigned int snoopHigh = baseAddress + regionLength;
+
+    if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
+	return false;
+    snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
+    snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
+    if(regionLength == 0) /* closing the region */
+    {
+	GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
+	GT_REG_WRITE(snoopXtopAddress,0);
+	return true;
+    }
+    baseAddress = baseAddress & 0xffff0000;
+    data = (baseAddress >> 16) | snoopType << 16;
+    GT_REG_WRITE(snoopXbaseAddress,data);
+    snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+    GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
+    return true;
+}
+
+/********************************************************************
+* memoryRemapAddress - This fubction used for address remapping.
+*
+*
+* Inputs: regOffset: remap register
+*         remapValue :
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue)
+{
+    unsigned int valueForReg;
+    valueForReg = (remapValue & 0xfff00000) >> 20;
+    GT_REG_WRITE(remapReg, valueForReg);
+    return true;
+}
+
+/********************************************************************
+* memoryGetDeviceParam - This function used for getting device parameters from
+*                        DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs:        - deviceParam: STRUCT with paramiters for DEVICE BANK
+*                  PARAMETERS REGISTER
+*                - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum)
+{
+    unsigned int valueOfReg;
+    unsigned int calcData;
+
+    GT_REG_READ(DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
+    calcData = (0x7 & valueOfReg) + ((0x400000 & valueOfReg) >> 19);
+    deviceParam -> turnOff = calcData;          /* Turn Off */
+
+    calcData = ((0x78 & valueOfReg) >> 3) + ((0x800000 & valueOfReg) >> 19);
+    deviceParam -> acc2First = calcData;        /* Access To First */
+
+    calcData = ((0x780 & valueOfReg) >> 7) + ((0x1000000 & valueOfReg) >> 20);
+    deviceParam -> acc2Next = calcData;         /* Access To Next */
+
+    calcData = ((0x3800 & valueOfReg) >> 11) + ((0x2000000 & valueOfReg) >> 22);
+    deviceParam -> ale2Wr = calcData;           /* Ale To Write */
+
+    calcData = ((0x1c000 & valueOfReg) >> 14) + ((0x4000000 & valueOfReg) >> 23);
+    deviceParam -> wrLow = calcData;            /* Write Active */
+
+    calcData = ((0xe0000 & valueOfReg) >> 17) + ((0x8000000 & valueOfReg) >> 24);
+    deviceParam -> wrHigh = calcData;           /* Write High */
+
+    calcData = ((0x300000 & valueOfReg) >> 20);
+    switch (calcData)
+    {
+    case 0:
+	deviceParam -> deviceWidth = 1;         /* one Byte - 8-bit */
+	break;
+    case 1:
+	deviceParam -> deviceWidth = 2;         /* two Bytes - 16-bit */
+	break;
+    case 2:
+	deviceParam -> deviceWidth = 4;         /* four Bytes - 32-bit */
+	break;
+    case 3:
+	deviceParam -> deviceWidth = 8;         /* eight Bytes - 64-bit */
+	break;
+    default:
+	deviceParam -> deviceWidth = 1;
+	break;
+    }
+    return true;
+}
+
+/********************************************************************
+* memorySetDeviceParam - This function used for setting device parameters to
+*                        DEVICE BANK PARAMETERS REGISTER
+*
+*
+* Inputs:        - deviceParam: STRUCT for store paramiters from DEVICE BANK
+*                  PARAMETERS REGISTER
+*                - deviceNum : number of device
+* Returns: false if one of the parameters is erroneous,true otherwise.
+*********************************************************************/
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum)
+{
+    unsigned int valueForReg;
+
+    if((deviceParam -> turnOff >= 0xf) || (deviceParam -> acc2First >= 0x1f) ||
+       (deviceParam -> acc2Next >= 0x1f) || (deviceParam -> ale2Wr >= 0xf) ||
+	(deviceParam -> wrLow >= 0xf) || (deviceParam -> wrHigh >= 0xf))
+	return false;
+    valueForReg = (((deviceParam -> turnOff) & 0x7) |
+		   (((deviceParam -> turnOff) & 0x8) << 19) |
+		   (((deviceParam -> acc2First) & 0xf) << 3) |
+		   (((deviceParam -> acc2First) & 0x10) << 19) |
+		   (((deviceParam -> acc2Next) & 0xf) << 7) |
+		   (((deviceParam -> acc2Next) & 0x10) << 20) |
+		   (((deviceParam -> ale2Wr) & 0x7) << 11) |
+		   (((deviceParam -> ale2Wr) & 0xf) << 22) |
+		   (((deviceParam -> wrLow) & 0x7) << 14) |
+		   (((deviceParam -> wrLow) & 0xf) << 23) |
+		   (((deviceParam -> wrHigh) & 0x7) << 17) |
+		   (((deviceParam -> wrHigh) & 0xf) << 24));
+    /* insert the device width: */
+    switch(deviceParam->deviceWidth)
+    {
+    case 1:
+	valueForReg = valueForReg | _8BIT;
+	break;
+    case 2:
+	valueForReg = valueForReg | _16BIT;
+	break;
+    case 4:
+	valueForReg = valueForReg | _32BIT;
+	break;
+    case 8:
+	valueForReg = valueForReg | _64BIT;
+	break;
+    default:
+	valueForReg = valueForReg | _8BIT;
+	break;
+    }
+    GT_REG_WRITE(DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
+    return true;
+}
diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S
new file mode 100755
index 0000000..438dea6
--- /dev/null
+++ b/board/evb64260/misc.S
@@ -0,0 +1,182 @@
+#include <config.h>
+#include <74xx_7xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include <galileo/gt64260R.h>
+
+#ifdef CONFIG_ECC
+	/* Galileo specific asm code for initializing ECC */
+	.globl board_relocate_rom
+board_relocate_rom:
+	mflr	r7
+	/* update the location of the GT registers */
+	lis	r11, CFG_GT_REGS@h
+	/* if we're using ECC, we must use the DMA engine to copy ourselves */
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+
+	mtlr	r7
+	blr
+
+	.globl board_init_ecc
+board_init_ecc:
+	mflr	r7
+	/* NOTE: r10 still contains the location we've been relocated to
+	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+
+	/* now that we're running from ram, init the rest of main memory
+	 * for ECC use */
+	lis	r8, CFG_MONITOR_LEN@h
+	ori	r8, r8, CFG_MONITOR_LEN@l
+
+	divw	r3, r10, r8
+
+	/* set up the counter, and init the starting address */
+	mtctr	r3
+	li	r12, 0
+
+	/* bytes per transfer */
+	mr	r5, r8
+about_to_init_ecc:
+1:	mr	r3, r12
+	mr	r4, r12
+	bl	start_idma_transfer_0
+	bl	wait_for_idma_0
+	bl	stop_idma_engine_0
+	add	r12, r12, r8
+	bdnz	1b
+
+	mtlr	r7
+	blr
+
+	/* r3:	dest addr
+	 * r4:	source addr
+	 * r5:	byte count
+	 * r11:	gt regbase
+	 * trashes:	 r6, r5
+	 */
+start_idma_transfer_0:
+	/* set the byte count, including the OWN bit */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_BYTE_COUNT
+	stwbrx	r5, 0, (r6)
+
+	/* set the source address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
+	stwbrx	r4, 0, (r6)
+
+	/* set the dest address */
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
+	stwbrx	r3, 0, (r6)
+
+	/* set the next record pointer */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0NEXT_RECORD_POINTER
+	stwbrx	r5, 0, (r6)
+
+	/* set the low control register */
+	/* bit 9 is NON chained mode, bit 31 is new style descriptors.
+	   bit 12 is channel enable */
+	ori	r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
+	/* 15 shifted by 16 (oris) == bit 31 */
+	oris	r5, r5, (1 << 15)
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+
+	/* this waits for the bytecount to return to zero, indicating
+	 * that the trasfer is complete */
+wait_for_idma_0:
+	mr	r5, r11
+	lis	r6, 0xff
+	ori	r6, r6, 0xffff
+	ori	r5, r5, CHANNEL0_DMA_BYTE_COUNT
+1:	lwbrx	r4, 0, (r5)
+	and.	r4, r4, r6
+	bne	1b
+
+	blr
+
+	/* this turns off channel 0 of the idma engine */
+stop_idma_engine_0:
+	/* shut off the DMA engine */
+	li	r5, 0
+	mr	r6, r11
+	ori	r6, r6, CHANNEL0CONTROL
+	stwbrx	r5, 0, (r6)
+
+	blr
+#endif
+
+#ifdef CFG_BOARD_ASM_INIT
+	/* NOTE: trashes r3-r7 */
+	.globl board_asm_init
+board_asm_init:
+	/* just move the GT registers to where they belong */
+	lis	r3, CFG_DFL_GT_REGS@h
+	ori	r3, r3, CFG_DFL_GT_REGS@l
+	lis	r4, CFG_GT_REGS@h
+	ori	r4, r4, CFG_GT_REGS@l
+	li	r5, INTERNAL_SPACE_DECODE
+
+	/* test to see if we've already moved */
+	lwbrx	r6, r5, r4
+	andi.	r6, r6, 0xffff
+	rlwinm	r7, r4, 12, 16, 31
+	cmp	cr0, r7, r6
+	beqlr
+
+	/* nope, have to move the registers */
+	lwbrx	r6, r5, r3
+	andis.	r6, r6, 0xffff
+	or	r6, r6, r7
+	stwbrx	r6, r5, r3
+
+	/* now, poll for the change */
+1:	lwbrx	r7, r5, r4
+	cmp	cr0, r7, r6
+	bne	1b
+
+	/* done! */
+	blr
+#endif
+
+/* For use of the debug LEDs */
+	.global led_on0
+led_on0:
+	xor     r18, r18, r18
+	lis     r18, 0x1c80
+	ori     r18, r18, 0x8000
+	stw     r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on1
+led_on1:
+	xor     r18, r18, r18
+	lis     r18, 0x1c80
+	ori     r18, r18, 0xc000
+	stw     r18, 0x0(r18)
+	sync
+	blr
+
+	.global led_on2
+led_on2:
+	xor     r18, r18, r18
+	lis     r18, 0x1c81
+	ori     r18, r18, 0x0000
+	stw     r18, 0x0(r18)
+	sync
+	blr
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
new file mode 100755
index 0000000..ee623ca
--- /dev/null
+++ b/board/evb64260/mpsc.c
@@ -0,0 +1,868 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpsc.c - driver for console over the MPSC.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/cache.h>
+
+#include <malloc.h>
+#include "mpsc.h"
+
+int (*mpsc_putchar)(char ch) = mpsc_putchar_early;
+
+static volatile unsigned int *rx_desc_base=NULL;
+static unsigned int rx_desc_index=0;
+static volatile unsigned int *tx_desc_base=NULL;
+static unsigned int tx_desc_index=0;
+
+/* local function declarations */
+static int galmpsc_connect(int channel, int connect);
+static int galmpsc_route_serial(int channel, int connect);
+static int galmpsc_route_rx_clock(int channel, int brg);
+static int galmpsc_route_tx_clock(int channel, int brg);
+static int galmpsc_write_config_regs(int mpsc, int mode);
+static int galmpsc_config_channel_regs(int mpsc);
+static int galmpsc_set_char_length(int mpsc, int value);
+static int galmpsc_set_stop_bit_length(int mpsc, int value);
+static int galmpsc_set_parity(int mpsc, int value);
+static int galmpsc_enter_hunt(int mpsc);
+static int galmpsc_set_brkcnt(int mpsc, int value);
+static int galmpsc_set_tcschar(int mpsc, int value);
+static int galmpsc_set_snoop(int mpsc, int value);
+static int galmpsc_shutdown(int mpsc);
+
+static int galsdma_set_RFT(int channel);
+static int galsdma_set_SFM(int channel);
+static int galsdma_set_rxle(int channel);
+static int galsdma_set_txle(int channel);
+static int galsdma_set_burstsize(int channel, unsigned int value);
+static int galsdma_set_RC(int channel, unsigned int value);
+
+static int galbrg_set_CDV(int channel, int value);
+static int galbrg_enable(int channel);
+static int galbrg_disable(int channel);
+static int galbrg_set_clksrc(int channel, int value);
+static int galbrg_set_CUV(int channel, int value);
+
+static void galsdma_enable_rx(void);
+
+/* static int galbrg_reset(int channel); */
+
+#define SOFTWARE_CACHE_MANAGEMENT
+
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+#define FLUSH_DCACHE(a,b)		 if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
+#define INVALIDATE_DCACHE(a,b)		 if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
+#else
+#define FLUSH_DCACHE(a,b)
+#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
+#define INVALIDATE_DCACHE(a,b)
+#endif
+
+
+/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
+#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack))
+
+#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
+#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
+
+#define GT_REG_WRITE_MIRROR(a,i,g,d) {MIRROR_HACK->a ## _M[i] = d; GT_REG_WRITE(a + (i*g),d);}
+#define GTREGREAD_MIRROR(a,i,g) (MIRROR_HACK->a ## _M[i])
+
+/* make sure this isn't bigger than 16 long words (u-boot.h) */
+struct _tag_mirror_hack {
+    unsigned GALMPSC_PROTOCONF_REG_M[2];	/* 8008 */
+    unsigned GALMPSC_CHANNELREG_1_M[2];		/* 800c */
+    unsigned GALMPSC_CHANNELREG_2_M[2];		/* 8010 */
+    unsigned GALBRG_0_CONFREG_M[2];		/* b200 */
+
+    unsigned GALMPSC_ROUTING_REGISTER_M;	/* b400 */
+    unsigned GALMPSC_RxC_ROUTE_M;		/* b404 */
+    unsigned GALMPSC_TxC_ROUTE_M;		/* b408 */
+
+    unsigned int baudrate;			/* current baudrate, for tsc delay calc */
+};
+
+/* static struct _tag_mirror_hack *mh = NULL;   */
+
+/* special function for running out of flash.  doesn't modify any
+ * global variables [josh] */
+int
+mpsc_putchar_early(char ch)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int mpsc=CHANNEL;
+	int temp=GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+	galmpsc_set_tcschar(mpsc,ch);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_2+(mpsc*GALMPSC_REG_GAP), temp|0x200);
+
+#define MAGIC_FACTOR	(10*1000000)
+
+	udelay(MAGIC_FACTOR / MIRROR_HACK->baudrate);
+	return 0;
+}
+
+/* This is used after relocation, see serial.c and mpsc_init2 */
+static int
+mpsc_putchar_sdma(char ch)
+{
+	volatile unsigned int *p;
+	unsigned int temp;
+
+
+	/* align the descriptor */
+	p = tx_desc_base;
+	memset((void *)p, 0, 8 * sizeof(unsigned int));
+
+	/* fill one 64 bit buffer */
+	/* word swap, pad with 0 */
+	p[4] = 0;						/* x */
+	p[5] = (unsigned int)ch;				/* x */
+
+	/* CHANGED completely according to GT64260A dox - NTL */
+	p[0] = 0x00010001;					/* 0 */
+	p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;		/* 4 */
+	p[2] = 0;						/* 8 */
+	p[3] = (unsigned int)&p[4];				/* c */
+
+#if 0
+	p[9] = DESC_FIRST | DESC_LAST;
+	p[10] = (unsigned int)&p[0];
+	p[11] = (unsigned int)&p[12];
+#endif
+
+	FLUSH_DCACHE(&p[0], &p[8]);
+
+	GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
+		     (unsigned int)&p[0]);
+	GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
+		     (unsigned int)&p[0]);
+
+	temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF));
+	temp |= (TX_DEMAND | TX_STOP);
+	GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp);
+
+	INVALIDATE_DCACHE(&p[1], &p[2]);
+
+	while(p[1] & DESC_OWNER) {
+	    udelay(100);
+	    INVALIDATE_DCACHE(&p[1], &p[2]);
+	}
+
+	return 0;
+}
+
+char
+mpsc_getchar(void)
+{
+    DECLARE_GLOBAL_DATA_PTR;
+    static unsigned int done = 0;
+    volatile char ch;
+    unsigned int len=0, idx=0, temp;
+
+    volatile unsigned int *p;
+
+
+    do {
+	p=&rx_desc_base[rx_desc_index*8];
+
+	INVALIDATE_DCACHE(&p[0], &p[1]);
+	/* Wait for character */
+	while (p[1] & DESC_OWNER){
+	    udelay(100);
+	    INVALIDATE_DCACHE(&p[0], &p[1]);
+	}
+
+	/* Handle error case */
+	if (p[1] & (1<<15)) {
+		printf("oops, error: %08x\n", p[1]);
+
+		temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,CHANNEL,GALMPSC_REG_GAP);
+		temp |= (1 << 23);
+		GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2, CHANNEL,GALMPSC_REG_GAP, temp);
+
+		/* Can't poll on abort bit, so we just wait. */
+		udelay(100);
+
+		galsdma_enable_rx();
+	}
+
+	/* Number of bytes left in this descriptor */
+	len = p[0] & 0xffff;
+
+	if (len) {
+	    /* Where to look */
+	    idx = 5;
+	    if (done > 3) idx = 4;
+	    if (done > 7) idx = 7;
+	    if (done > 11) idx = 6;
+
+	    INVALIDATE_DCACHE(&p[idx], &p[idx+1]);
+	    ch = p[idx] & 0xff;
+	    done++;
+	}
+
+	if (done < len) {
+		/* this descriptor has more bytes still
+		 * shift down the char we just read, and leave the
+		 * buffer in place for the next time around
+		 */
+		p[idx] =  p[idx] >> 8;
+		FLUSH_DCACHE(&p[idx], &p[idx+1]);
+	}
+
+	if (done == len) {
+		/* nothing left in this descriptor.
+		 * go to next one
+		 */
+		p[1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
+		p[0] = 0x00100000;
+		FLUSH_DCACHE(&p[0], &p[1]);
+		/* Next descriptor */
+		rx_desc_index = (rx_desc_index + 1) % RX_DESC;
+		done = 0;
+	}
+    } while (len==0);	/* galileo bug.. len might be zero */
+
+    return ch;
+}
+
+int
+mpsc_test_char(void)
+{
+	volatile unsigned int *p=&rx_desc_base[rx_desc_index*8];
+
+	INVALIDATE_DCACHE(&p[1], &p[2]);
+
+	if (p[1] & DESC_OWNER) return 0;
+	else return 1;
+}
+
+int
+mpsc_init(int baud)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	memset(MIRROR_HACK, 0, sizeof(struct _tag_mirror_hack));
+	MIRROR_HACK->GALMPSC_ROUTING_REGISTER_M=0x3fffffff;
+
+	/* BRG CONFIG */
+	galbrg_set_baudrate(CHANNEL, baud);
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
+	galbrg_set_clksrc(CHANNEL,0x8);	/* connect TCLK -> BRG */
+#else
+	galbrg_set_clksrc(CHANNEL,0);
+#endif
+	galbrg_set_CUV(CHANNEL, 0);
+	galbrg_enable(CHANNEL);
+
+	/* Set up clock routing */
+	galmpsc_connect(CHANNEL, GALMPSC_CONNECT);
+	galmpsc_route_serial(CHANNEL, GALMPSC_CONNECT);
+	galmpsc_route_rx_clock(CHANNEL, CHANNEL);
+	galmpsc_route_tx_clock(CHANNEL, CHANNEL);
+
+	/* reset MPSC state */
+	galmpsc_shutdown(CHANNEL);
+
+	/* SDMA CONFIG */
+	galsdma_set_burstsize(CHANNEL, L1_CACHE_BYTES/8);	/* in 64 bit words (8 bytes) */
+	galsdma_set_txle(CHANNEL);
+	galsdma_set_rxle(CHANNEL);
+	galsdma_set_RC(CHANNEL, 0xf);
+	galsdma_set_SFM(CHANNEL);
+	galsdma_set_RFT(CHANNEL);
+
+	/* MPSC CONFIG */
+	galmpsc_write_config_regs(CHANNEL, GALMPSC_UART);
+	galmpsc_config_channel_regs(CHANNEL);
+	galmpsc_set_char_length(CHANNEL, GALMPSC_CHAR_LENGTH_8);       /* 8 */
+	galmpsc_set_parity(CHANNEL, GALMPSC_PARITY_NONE);              /* N */
+	galmpsc_set_stop_bit_length(CHANNEL, GALMPSC_STOP_BITS_1);     /* 1 */
+
+	/* COMM_MPSC CONFIG */
+#ifdef SOFTWARE_CACHE_MANAGEMENT
+	galmpsc_set_snoop(CHANNEL, 0);     				/* disable snoop */
+#else
+	galmpsc_set_snoop(CHANNEL, 1);     				/* enable snoop */
+#endif
+
+	return 0;
+}
+
+void
+mpsc_init2(void)
+{
+	int i;
+
+	mpsc_putchar = mpsc_putchar_sdma;
+
+	/* RX descriptors */
+	rx_desc_base = (unsigned int *)malloc(((RX_DESC+1)*8) *
+		sizeof(unsigned int));
+
+	/* align descriptors */
+	rx_desc_base = (unsigned int *)
+		(((unsigned int)rx_desc_base+32) & 0xFFFFFFF0);
+
+	rx_desc_index = 0;
+
+	memset((void *)rx_desc_base, 0, (RX_DESC*8)*sizeof(unsigned int));
+
+	for (i = 0; i < RX_DESC; i++) {
+		rx_desc_base[i*8 + 3] = (unsigned int)&rx_desc_base[i*8 + 4]; /* Buffer */
+		rx_desc_base[i*8 + 2] = (unsigned int)&rx_desc_base[(i+1)*8]; /* Next descriptor */
+		rx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST;  /* Command & control */
+		rx_desc_base[i*8] = 0x00100000;
+	}
+	rx_desc_base[(i-1)*8 + 2] = (unsigned int)&rx_desc_base[0];
+
+	FLUSH_DCACHE(&rx_desc_base[0], &rx_desc_base[RX_DESC*8]);
+	GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR+(CHANNEL*GALSDMA_REG_DIFF),
+		     (unsigned int)&rx_desc_base[0]);
+
+	/* TX descriptors */
+	tx_desc_base = (unsigned int *)malloc(((TX_DESC+1)*8) *
+		sizeof(unsigned int));
+
+	/* align descriptors */
+	tx_desc_base = (unsigned int *)
+		(((unsigned int)tx_desc_base+32) & 0xFFFFFFF0);
+
+	tx_desc_index = -1;
+
+	memset((void *)tx_desc_base, 0, (TX_DESC*8)*sizeof(unsigned int));
+
+	for (i = 0; i < TX_DESC; i++) {
+		tx_desc_base[i*8 + 5] = (unsigned int)0x23232323;
+		tx_desc_base[i*8 + 4] = (unsigned int)0x23232323;
+		tx_desc_base[i*8 + 3] = (unsigned int)&tx_desc_base[i*8 + 4];
+		tx_desc_base[i*8 + 2] = (unsigned int)&tx_desc_base[(i+1)*8];
+		tx_desc_base[i*8 + 1] = DESC_OWNER | DESC_FIRST | DESC_LAST;
+
+		/* set sbytecnt and shadow byte cnt to 1 */
+		tx_desc_base[i*8] = 0x00010001;
+	}
+	tx_desc_base[(i-1)*8 + 2] = (unsigned int)&tx_desc_base[0];
+
+	FLUSH_DCACHE(&tx_desc_base[0], &tx_desc_base[TX_DESC*8]);
+
+	udelay(100);
+
+	galsdma_enable_rx();
+
+	return;
+}
+
+int
+galbrg_set_baudrate(int channel, int rate)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int clock;
+
+	galbrg_disable(channel);
+
+#if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
+	/* from tclk */
+	clock = (CFG_BUS_HZ/(16*rate)) - 1;
+#else
+	clock = (3686400/(16*rate)) - 1;
+#endif
+
+	galbrg_set_CDV(channel, clock);
+
+	galbrg_enable(channel);
+
+	MIRROR_HACK->baudrate = rate;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------ */
+
+/* Below are all the private functions that no one else needs */
+
+static int
+galbrg_set_CDV(int channel, int value)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
+	temp &= 0xFFFF0000;
+	temp |= (value & 0x0000FFFF);
+	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel,GALBRG_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galbrg_enable(int channel)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
+	temp |= 0x00010000;
+	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp);
+
+	return 0;
+}
+
+static int
+galbrg_disable(int channel)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
+	temp &= 0xFFFEFFFF;
+	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp);
+
+	return 0;
+}
+
+static int
+galbrg_set_clksrc(int channel, int value)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP);
+	temp &= 0xFF83FFFF;
+	temp |= (value << 18);
+	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp);
+
+	return 0;
+}
+
+static int
+galbrg_set_CUV(int channel, int value)
+{
+	GT_REG_WRITE(GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);
+
+	return 0;
+}
+
+#if 0
+static int
+galbrg_reset(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
+	temp |= 0x20000;
+	GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);
+
+	return 0;
+}
+#endif
+
+static int
+galsdma_set_RFT(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp |= 0x00000001;
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_SFM(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp |= 0x00000002;
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_rxle(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp |= 0x00000040;
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_txle(int channel)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp |= 0x00000080;
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_RC(int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp &= ~0x0000003c;
+	temp |= (value << 2);
+	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);
+
+	return 0;
+}
+
+static int
+galsdma_set_burstsize(int channel, unsigned int value)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
+	temp &= 0xFFFFCFFF;
+	switch (value) {
+	 case 8:
+		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+			     (temp | (0x3 << 12)));
+		break;
+
+	 case 4:
+		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+			     (temp | (0x2 << 12)));
+		break;
+
+	 case 2:
+		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+			     (temp | (0x1 << 12)));
+		break;
+
+	 case 1:
+		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
+			     (temp | (0x0 << 12)));
+		break;
+
+	 default:
+		return -1;
+		break;
+	}
+
+	return 0;
+}
+
+static int
+galmpsc_connect(int channel, int connect)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER);
+
+	if ((channel == 0) && connect)
+		temp &= ~0x00000007;
+	else if ((channel == 1) && connect)
+		temp &= ~(0x00000007 << 6);
+	else if ((channel == 0) && !connect)
+		temp |= 0x00000007;
+	else
+		temp |= (0x00000007 << 6);
+
+	/* Just in case... */
+	temp &= 0x3fffffff;
+
+	GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_route_serial(int channel, int connect)
+{
+	unsigned int temp;
+
+	temp = GTREGREAD(GALMPSC_SERIAL_MULTIPLEX);
+
+	if ((channel == 0) && connect)
+		temp |= 0x00000100;
+	else if ((channel == 1) && connect)
+		temp |= 0x00001000;
+	else if ((channel == 0) && !connect)
+		temp &= ~0x00000100;
+	else
+		temp &= ~0x00001000;
+
+	GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX,temp);
+
+	return 0;
+}
+
+static int
+galmpsc_route_rx_clock(int channel, int brg)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE);
+
+	if (channel == 0)
+		temp |= brg;
+	else
+		temp |= (brg << 8);
+
+	GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp);
+
+	return 0;
+}
+
+static int
+galmpsc_route_tx_clock(int channel, int brg)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE);
+
+	if (channel == 0)
+		temp |= brg;
+	else
+		temp |= (brg << 8);
+
+	GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp);
+
+	return 0;
+}
+
+static int
+galmpsc_write_config_regs(int mpsc, int mode)
+{
+	if (mode == GALMPSC_UART) {
+		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
+		GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP),
+			     0x000004c4);
+
+		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
+		GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP),
+			     0x024003f8);
+		/*        22 2222 1111 */
+		/*        54 3210 9876 */
+		/* 0000 0010 0000 0000 */
+		/*       1 */
+		/*       098 7654 3210 */
+		/* 0000 0011 1111 1000 */
+	} else
+		return -1;
+
+	return 0;
+}
+
+static int
+galmpsc_config_channel_regs(int mpsc)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0);
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_7+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_8+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_9+(mpsc*GALMPSC_REG_GAP), 0);
+	GT_REG_WRITE(GALMPSC_CHANNELREG_10+(mpsc*GALMPSC_REG_GAP), 0);
+
+	galmpsc_set_brkcnt(mpsc, 0x3);
+	galmpsc_set_tcschar(mpsc, 0xab);
+
+	return 0;
+}
+
+static int
+galmpsc_set_brkcnt(int mpsc, int value)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
+	temp &= 0x0000FFFF;
+	temp |= (value << 16);
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_set_tcschar(int mpsc, int value)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
+	temp &= 0xFFFF0000;
+	temp |= value;
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_set_char_length(int mpsc, int value)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
+	temp &= 0xFFFFCFFF;
+	temp |= (value << 12);
+	GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_set_stop_bit_length(int mpsc, int value)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
+	temp |= (value << 14);
+	GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp);
+
+	return 0;
+}
+
+static int
+galmpsc_set_parity(int mpsc, int value)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+	if (value != -1) {
+		temp &= 0xFFF3FFF3;
+		temp |= ((value << 18) | (value << 2));
+		temp |= ((value << 17) | (value << 1));
+	} else {
+		temp &= 0xFFF1FFF1;
+	}
+
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);
+
+	return 0;
+}
+
+static int
+galmpsc_enter_hunt(int mpsc)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	int temp;
+
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+	temp |= 0x80000000;
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);
+
+	/* Should Poll on Enter Hunt bit, but the register is write-only */
+	/* errata suggests pausing 100 system cycles */
+	udelay(100);
+
+	return 0;
+}
+
+
+static int
+galmpsc_shutdown(int mpsc)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+#if 0
+	unsigned int temp;
+
+	/* cause RX abort (clears RX) */
+	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
+	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
+	temp &= ~MPSC_ENTER_HUNT;
+	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp);
+#endif
+
+	GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0);
+	GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF,
+	             SDMA_TX_ABORT | SDMA_RX_ABORT);
+
+	/* shut down the MPSC */
+	GT_REG_WRITE(GALMPSC_MCONF_LOW, 0);
+	GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0);
+	GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0);
+
+	udelay(100);
+
+	/* shut down the sdma engines. */
+	/* reset config to default */
+	GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF,
+	             0x000000fc);
+
+	udelay(100);
+
+	/* clear the SDMA current and first TX and RX pointers */
+	GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+	GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+	GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
+
+	udelay(100);
+
+	return 0;
+}
+
+static void
+galsdma_enable_rx(void)
+{
+	int temp;
+
+	/* Enable RX processing */
+	temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF));
+	temp |= RX_ENABLE;
+	GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp);
+
+	galmpsc_enter_hunt(CHANNEL);
+}
+
+static int
+galmpsc_set_snoop(int mpsc, int value)
+{
+	int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW;
+	int temp=GTREGREAD(reg);
+	if(value)
+	    temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30);
+	else
+	    temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30));
+	GT_REG_WRITE(reg, temp);
+	return 0;
+}
diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h
new file mode 100755
index 0000000..54b642a
--- /dev/null
+++ b/board/evb64260/mpsc.h
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2001
+ * John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpsc.h - header file for MPSC in uart mode (console driver)
+ */
+
+#ifndef __MPSC_H__
+#define __MPSC_H__
+
+/* include actual Galileo defines */
+#include <galileo/gt64260R.h>
+
+/* driver related defines */
+
+int mpsc_init(int baud);
+void mpsc_init2(void);
+char mpsc_getchar(void);
+int mpsc_test_char(void);
+int galbrg_set_baudrate(int channel, int rate);
+
+int mpsc_putchar_early(char ch);
+extern int (*mpsc_putchar)(char ch);
+
+#define CHANNEL CONFIG_MPSC_PORT
+
+#define TX_DESC     5
+#define RX_DESC     20
+
+#define DESC_FIRST  0x00010000
+#define DESC_LAST   0x00020000
+#define DESC_OWNER  0x80000000
+
+#define TX_DEMAND   0x00800000
+#define TX_STOP     0x00010000
+#define RX_ENABLE   0x00000080
+
+#define SDMA_RX_ABORT 		  (1 << 15)
+#define SDMA_TX_ABORT 		  (1 << 31)
+#define MPSC_TX_ABORT 		  (1 << 7)
+#define MPSC_RX_ABORT             (1 << 23)
+#define MPSC_ENTER_HUNT           (1 << 31)
+
+/* MPSC defines */
+
+#define GALMPSC_CONNECT            0x1
+#define GALMPSC_DISCONNECT         0x0
+
+#define GALMPSC_UART               0x1
+
+#define GALMPSC_STOP_BITS_1        0x0
+#define GALMPSC_STOP_BITS_2        0x1
+#define GALMPSC_CHAR_LENGTH_8      0x3
+#define GALMPSC_CHAR_LENGTH_7      0x2
+
+#define GALMPSC_PARITY_ODD         0x0
+#define GALMPSC_PARITY_EVEN        0x2
+#define GALMPSC_PARITY_MARK        0x3
+#define GALMPSC_PARITY_SPACE       0x1
+#define GALMPSC_PARITY_NONE        -1
+
+#define GALMPSC_SERIAL_MULTIPLEX   SERIAL_PORT_MULTIPLEX           /* 0xf010 */
+#define GALMPSC_ROUTING_REGISTER   MAIN_ROUTING_REGISTER           /* 0xb400 */
+#define GALMPSC_RxC_ROUTE          RECEIVE_CLOCK_ROUTING_REGISTER  /* 0xb404 */
+#define GALMPSC_TxC_ROUTE          TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
+#define GALMPSC_MCONF_LOW          MPSC0_MAIN_CONFIGURATION_LOW    /* 0x8000 */
+#define GALMPSC_MCONF_HIGH         MPSC0_MAIN_CONFIGURATION_HIGH   /* 0x8004 */
+#define GALMPSC_PROTOCONF_REG      MPSC0_PROTOCOL_CONFIGURATION    /* 0x8008 */
+
+#define GALMPSC_REG_GAP            0x1000
+
+#define GALMPSC_MCONF_CHREG_BASE   CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_1       CHANNEL0_REGISTER1  /* 0x800c */
+#define GALMPSC_CHANNELREG_2       CHANNEL0_REGISTER2  /* 0x8010 */
+#define GALMPSC_CHANNELREG_3       CHANNEL0_REGISTER3  /* 0x8014 */
+#define GALMPSC_CHANNELREG_4       CHANNEL0_REGISTER4  /* 0x8018 */
+#define GALMPSC_CHANNELREG_5       CHANNEL0_REGISTER5  /* 0x801c */
+#define GALMPSC_CHANNELREG_6       CHANNEL0_REGISTER6  /* 0x8020 */
+#define GALMPSC_CHANNELREG_7       CHANNEL0_REGISTER7  /* 0x8024 */
+#define GALMPSC_CHANNELREG_8       CHANNEL0_REGISTER8  /* 0x8028 */
+#define GALMPSC_CHANNELREG_9       CHANNEL0_REGISTER9  /* 0x802c */
+#define GALMPSC_CHANNELREG_10      CHANNEL0_REGISTER10 /* 0x8030 */
+#define GALMPSC_CHANNELREG_11      CHANNEL0_REGISTER11 /* 0x8034 */
+
+#define GALSDMA_COMMAND_FIRST     (1 << 16)
+#define GALSDMA_COMMAND_LAST      (1 << 17)
+#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
+#define GALSDMA_COMMAND_AUTO      (1 << 30)
+#define GALSDMA_COMMAND_OWNER     (1 << 31)
+
+#define GALSDMA_RX                 0
+#define GALSDMA_TX                 1
+
+/* CHANNEL2 should be CHANNEL1, according to documentation,
+ * but to work with the current GTREGS file...
+ */
+#define GALSDMA_0_CONF_REG         CHANNEL0_CONFIGURATION_REGISTER   /* 0x4000 */
+#define GALSDMA_1_CONF_REG         CHANNEL2_CONFIGURATION_REGISTER   /* 0x6000 */
+#define GALSDMA_0_COM_REG          CHANNEL0_COMMAND_REGISTER         /* 0x4008 */
+#define GALSDMA_1_COM_REG          CHANNEL2_COMMAND_REGISTER         /* 0x6008 */
+#define GALSDMA_0_CUR_RX_PTR       CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x4810 */
+#define GALSDMA_0_CUR_TX_PTR       CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x4c10 */
+#define GALSDMA_0_FIR_TX_PTR       CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER    /* 0x4c14 */
+#define GALSDMA_1_CUR_RX_PTR       CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER  /* 0x6810 */
+#define GALSDMA_1_CUR_TX_PTR       CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER  /* 0x6c10 */
+#define GALSDMA_1_FIR_TX_PTR       CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER    /* 0x6c14 */
+#define GALSDMA_REG_DIFF           0x2000
+
+/* WRONG in gt64260R.h */
+#define GALSDMA_INT_CAUSE          0xb800   /* SDMA_CAUSE */
+#define GALSDMA_INT_MASK           0xb880   /* SDMA_MASK  */
+
+#define GALSDMA_MODE_UART          0
+#define GALSDMA_MODE_BISYNC        1
+#define GALSDMA_MODE_HDLC          2
+#define GALSDMA_MODE_TRANSPARENT   3
+
+#define GALBRG_0_CONFREG           BRG0_CONFIGURATION_REGISTER  /*  0xb200  */
+#define GALBRG_REG_GAP             0x0008
+#define GALBRG_0_BTREG             BRG0_BAUDE_TUNING_REGISTER   /*  0xb204  */
+
+#endif /* __MPSC_H__ */
diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c
new file mode 100755
index 0000000..59b9acb
--- /dev/null
+++ b/board/evb64260/pci.c
@@ -0,0 +1,760 @@
+/* PCI.c - PCI functions */
+
+/* Copyright - Galileo technology. */
+
+#include <common.h>
+#include <pci.h>
+
+#include <galileo/pci.h>
+
+static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
+#ifdef CONFIG_ZUMA_V2
+	{0, 0, 0, 0, 0, 0, 0, 29,[8 ... PCI_MAX_DEVICES - 1] = 0},
+	{0, 0, 0, 0, 0, 0, 0, 28,[8 ... PCI_MAX_DEVICES - 1] = 0}
+#else				/* EVB??? This is a guess */
+	{0, 0, 0, 0, 0, 0, 0, 27, 27,[9 ... PCI_MAX_DEVICES - 1] = 0},
+	{0, 0, 0, 0, 0, 0, 0, 29, 29,[9 ... PCI_MAX_DEVICES - 1] = 0}
+#endif
+};
+
+static const unsigned int pci_p2p_configuration_reg[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static const unsigned int pci_configuration_address[] = {
+	PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
+
+static const unsigned int pci_configuration_data[] = {
+	PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+	PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
+
+static const unsigned int pci_error_cause_reg[] = {
+	PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
+
+static const unsigned int pci_arbiter_control[] = {
+	PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
+
+static const unsigned int pci_snoop_control_base_0_low[] = {
+	PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+	PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
+
+static const unsigned int pci_access_control_base_0_low[] = {
+	PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+	PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
+
+static const unsigned int pci_scs_bank_size[2][4] = {
+	{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+	 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+	{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+	 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
+
+static const unsigned int pci_p2p_configuration[] = {
+	PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
+
+static unsigned int local_buses[] = { 0, 0 };
+
+/********************************************************************
+* pciWriteConfigReg - Write to a PCI configuration register
+*                    - Make sure the GT is configured as a master before writing
+*                      to another device on the PCI.
+*                    - The function takes care of Big/Little endian conversion.
+*
+*
+* Inputs:   unsigned int regOffset: The register offset as it apears in the GT spec
+*                   (or any other PCI device spec)
+*           pciDevNum: The device number needs to be addressed.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+			unsigned int pciDevNum, unsigned int data)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int functionNum;
+	unsigned int busNum = PCI_BUS (pciDevNum);
+	unsigned int addr;
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &addr);
+	if (addr != DataForAddrReg)
+		return;
+	GT_REG_WRITE (pci_configuration_data[host], data);
+}
+
+/********************************************************************
+* pciReadConfigReg  - Read from a PCI0 configuration register
+*                    - Make sure the GT is configured as a master before reading
+*                     from another device on the PCI.
+*                   - The function takes care of Big/Little endian conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec)
+*           pciDevNum: The device number needs to be addressed.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|00|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum)
+{
+	volatile unsigned int DataForAddrReg;
+	unsigned int data;
+	unsigned int functionNum;
+	unsigned int busNum = PCI_BUS (pciDevNum);
+
+	if (pciDevNum > 32)	/* illegal device Number */
+		return 0xffffffff;
+	if (pciDevNum == SELF) {	/* configure our configuration space. */
+		pciDevNum =
+			(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+			0x1f;
+		busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+			0xff0000;
+	}
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xfc;
+	DataForAddrReg =
+		(regOffset | pciDevNum | functionNum | busNum) | BIT31;
+	GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+	GT_REG_READ (pci_configuration_address[host], &data);
+	if (data != DataForAddrReg)
+		return 0xffffffff;
+	GT_REG_READ (pci_configuration_data[host], &data);
+	return data;
+}
+
+/********************************************************************
+* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
+*                               the agent is placed on another Bus. For more
+*                               information read P2P in the PCI spec.
+*
+* Inputs:   unsigned int regOffset - The register offset as it apears in the
+*           GT spec (or any other PCI device spec).
+*           unsigned int pciDevNum - The device number needs to be addressed.
+*           unsigned int busNum - On which bus does the Target agent connect
+*                                 to.
+*           unsigned int data - data to be written.
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*  The configuration Address is configure as type-I (bits[1:0] = '01') due to
+*   PCI spec referring to P2P.
+*
+*********************************************************************/
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+				  unsigned int regOffset,
+				  unsigned int pciDevNum,
+				  unsigned int busNum, unsigned int data)
+{
+	unsigned int DataForReg;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+	} else {
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT31 | BIT0;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	if (pciDevNum == SELF) {	/* This board */
+		GT_REG_WRITE (pci_configuration_data[host], data);
+	} else {		/* configuration Transaction over the pci. */
+
+		/* The PCI is working in LE Mode So it swap the Data. */
+		GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data));
+	}
+}
+
+
+/********************************************************************
+* pciOverBridgeReadConfigReg  - Read from a PCIn configuration register where
+*                               the agent target locate on another PCI bus.
+*                             - Make sure the GT is configured as a master
+*                               before reading from another device on the PCI.
+*                             - The function takes care of Big/Little endian
+*                               conversion.
+* INPUTS:   regOffset: The register offset as it apears in the GT spec (or PCI
+*                        spec). (configuration register offset.)
+*           pciDevNum: The device number needs to be addressed.
+*           busNum: the Bus number where the agent is place.
+* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
+*                 cause register to make sure the data is valid
+*
+*  Configuration Address 0xCF8:
+*
+*       31 30    24 23  16 15  11 10     8 7      2  0     <=bit Number
+*  |congif|Reserved|  Bus |Device|Function|Register|01|
+*  |Enable|        |Number|Number| Number | Number |  |    <=field Name
+*
+*********************************************************************/
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+					 unsigned int regOffset,
+					 unsigned int pciDevNum,
+					 unsigned int busNum)
+{
+	unsigned int DataForReg;
+	unsigned int data;
+	unsigned int functionNum;
+
+	functionNum = regOffset & 0x00000700;
+	pciDevNum = pciDevNum << 11;
+	regOffset = regOffset & 0xff;
+	busNum = busNum << 16;
+	if (pciDevNum == SELF) {	/* This board */
+		DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+	} else {		/* agent on another bus */
+
+		DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+			BIT0 | BIT31;
+	}
+	GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+	if (pciDevNum == SELF) {	/* This board */
+		GT_REG_READ (pci_configuration_data[host], &data);
+		return data;
+	} else {		/* The PCI is working in LE Mode So it swap the Data. */
+
+		GT_REG_READ (pci_configuration_data[host], &data);
+		return WORD_SWAP (data);
+	}
+}
+
+/********************************************************************
+* pciGetRegOffset - Gets the register offset for this region config.
+*
+* INPUT:   Bus, Region - The bus and region we ask for its base address.
+* OUTPUT:   N/A
+* RETURNS: PCI register base address
+*********************************************************************/
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_LOW_DECODE_ADDRESS;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+		}
+	}
+	return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+}
+
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
+{
+	switch (host) {
+	case PCI_HOST0:
+		switch (region) {
+		case PCI_IO:
+			return PCI_0I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_0MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_0MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_0MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_0MEMORY3_ADDRESS_REMAP;
+		}
+	case PCI_HOST1:
+		switch (region) {
+		case PCI_IO:
+			return PCI_1I_O_ADDRESS_REMAP;
+		case PCI_REGION0:
+			return PCI_1MEMORY0_ADDRESS_REMAP;
+		case PCI_REGION1:
+			return PCI_1MEMORY1_ADDRESS_REMAP;
+		case PCI_REGION2:
+			return PCI_1MEMORY2_ADDRESS_REMAP;
+		case PCI_REGION3:
+			return PCI_1MEMORY3_ADDRESS_REMAP;
+		}
+	}
+	return PCI_0MEMORY0_ADDRESS_REMAP;
+}
+
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+		  unsigned int bankBase, unsigned int bankLength)
+{
+	unsigned int low = 0xfff;
+	unsigned int high = 0x0;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+	unsigned int remapOffset = pciGetRemapOffset (host, region);
+
+	if (bankLength != 0) {
+		low = (bankBase >> 20) & 0xfff;
+		high = ((bankBase + bankLength) >> 20) - 1;
+	}
+
+	GT_REG_WRITE (regOffset, low | (1 << 24));	/* no swapping */
+	GT_REG_WRITE (regOffset + 8, high);
+
+	if (bankLength != 0) {	/* must do AFTER writing maps */
+		GT_REG_WRITE (remapOffset, remapBase >> 20);	/* sorry, 32 bits only.
+								   dont support upper 32
+								   in this driver */
+	}
+	return true;
+}
+
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	return (low & 0xfff) << 20;
+}
+
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
+{
+	unsigned int low, high;
+	unsigned int regOffset = pciGetRegOffset (host, region);
+
+	GT_REG_READ (regOffset, &low);
+	GT_REG_READ (regOffset + 8, &high);
+	high &= 0xfff;
+	low &= 0xfff;
+	if (high <= low)
+		return 0;
+	return (high + 1 - low) << 20;
+}
+
+/********************************************************************
+* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
+*
+* Inputs: base and size of PCI SCS
+*********************************************************************/
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+		       unsigned int pciDramBase, unsigned int pciDramSize)
+{
+	pciDramBase = pciDramBase & 0xfffff000;
+	pciDramBase = pciDramBase | (pciReadConfigReg (host,
+						       PCI_SCS_0_BASE_ADDRESS
+						       + 4 * bank,
+						       SELF) & 0x00000fff);
+	pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF,
+			   pciDramBase);
+	if (pciDramSize == 0)
+		pciDramSize++;
+	GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
+}
+
+
+/********************************************************************
+* pciSetRegionFeatures - This function modifys one of the 8 regions with
+*                         feature bits given as an input.
+*                       - Be advised to check the spec before modifying them.
+* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
+*         unsigned int features - See file: pci.h there are defintion for those
+*                                 region features.
+*         unsigned int baseAddress - The region base Address.
+*         unsigned int topAddress - The region top Address.
+* Returns: false if one of the parameters is erroneous true otherwise.
+*********************************************************************/
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+			   unsigned int features, unsigned int baseAddress,
+			   unsigned int regionLength)
+{
+	unsigned int accessLow;
+	unsigned int accessHigh;
+	unsigned int accessTop = baseAddress + regionLength;
+
+	if (regionLength == 0) {	/* close the region. */
+		pciDisableAccessRegion (host, region);
+		return true;
+	}
+	/* base Address is store is bits [11:0] */
+	accessLow = (baseAddress & 0xfff00000) >> 20;
+	/* All the features are update according to the defines in pci.h (to be on
+	   the safe side we disable bits: [11:0] */
+	accessLow = accessLow | (features & 0xfffff000);
+	/* write to the Low Access Region register */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      accessLow);
+
+	accessHigh = (accessTop & 0xfff00000) >> 20;
+
+	/* write to the High Access Region register */
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+		      accessHigh - 1);
+	return true;
+}
+
+/********************************************************************
+* pciDisableAccessRegion - Disable The given Region by writing MAX size
+*                           to its low Address and MIN size to its high Address.
+*
+* Inputs:   PCI_ACCESS_REGIONS region - The region we to be Disabled.
+* Returns:  N/A.
+*********************************************************************/
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
+{
+	/* writing back the registers default values. */
+	GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+		      0x01001fff);
+	GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
+}
+
+/********************************************************************
+* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true.
+*********************************************************************/
+bool pciArbiterEnable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+	return true;
+}
+
+/********************************************************************
+* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
+*
+* Inputs:   N/A
+* Returns:  true
+*********************************************************************/
+bool pciArbiterDisable (PCI_HOST host)
+{
+	unsigned int regData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+	return true;
+}
+
+/********************************************************************
+* pciParkingDisable - Park on last option disable, with this function you can
+*                      disable the park on last mechanism for each agent.
+*                      disabling this option for all agents results parking
+*                      on the internal master.
+*
+* Inputs: PCI_AGENT_PARK internalAgent -  parking Disable for internal agent.
+*         PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
+*         PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
+*         PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
+*         PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
+*         PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
+*         PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
+* Returns:  true
+*********************************************************************/
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5)
+{
+	unsigned int regData;
+	unsigned int writeData;
+
+	GT_REG_READ (pci_arbiter_control[host], &regData);
+	writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+		(externalAgent1 << 16) + (externalAgent2 << 17) +
+		(externalAgent3 << 18) + (externalAgent4 << 19) +
+		(externalAgent5 << 20);
+	regData = (regData & ~(0x7f << 14)) | writeData;
+	GT_REG_WRITE (pci_arbiter_control[host], regData);
+	return true;
+}
+
+/********************************************************************
+* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
+*                          supports Cache Coherency in the PCI_n interface.
+* Inputs: region - One of the four regions.
+*         snoopType - There is four optional Types:
+*                        1. No Snoop.
+*                        2. Snoop to WT region.
+*                        3. Snoop to WB region.
+*                        4. Snoop & Invalidate to WB region.
+*         baseAddress - Base Address of this region.
+*         regionLength - Region length.
+* Returns: false if one of the parameters is wrong otherwise return true.
+*********************************************************************/
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength)
+{
+	unsigned int snoopXbaseAddress;
+	unsigned int snoopXtopAddress;
+	unsigned int data;
+	unsigned int snoopHigh = baseAddress + regionLength;
+
+	if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+		return false;
+	snoopXbaseAddress =
+		pci_snoop_control_base_0_low[host] + 0x10 * region;
+	snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+	if (regionLength == 0) {	/* closing the region */
+		GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+		GT_REG_WRITE (snoopXtopAddress, 0);
+		return true;
+	}
+	baseAddress = baseAddress & 0xfff00000;	/* Granularity of 1MByte */
+	data = (baseAddress >> 20) | snoopType << 12;
+	GT_REG_WRITE (snoopXbaseAddress, data);
+	snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+	GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
+	return true;
+}
+
+/*
+ *
+ */
+
+static int gt_read_config_dword (struct pci_controller *hose,
+				 pci_dev_t dev, int offset, u32 * value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+					   PCI_DEV (dev));
+	} else {
+		*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+						     cfg_addr, offset,
+						     PCI_DEV (dev), bus);
+	}
+	return 0;
+}
+
+static int gt_write_config_dword (struct pci_controller *hose,
+				  pci_dev_t dev, int offset, u32 value)
+{
+	int bus = PCI_BUS (dev);
+
+	if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+		pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+				   PCI_DEV (dev), value);
+	} else {
+		pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+					     offset, PCI_DEV (dev), value,
+					     bus);
+	}
+	return 0;
+}
+
+/*
+ *
+ */
+
+static void gt_setup_ide (struct pci_controller *hose,
+			  pci_dev_t dev, struct pci_config_table *entry)
+{
+	static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+	u32 bar_response, bar_value;
+	int bar;
+
+	for (bar = 0; bar < 6; bar++) {
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					0x0);
+		pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+				       &bar_response);
+
+		pciauto_region_allocate (bar_response &
+					 PCI_BASE_ADDRESS_SPACE_IO ? hose->
+					 pci_io : hose->pci_mem, ide_bar[bar],
+					 &bar_value);
+
+		pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+					bar_value);
+	}
+}
+
+#ifndef CONFIG_P3G4
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char pin, irq;
+
+	pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
+
+	if (pin == 1) {		/* only allow INT A */
+		irq = pci_irq_swizzle[(PCI_HOST) hose->
+				      cfg_addr][PCI_DEV (dev)];
+		if (irq)
+			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+	}
+}
+#endif
+
+struct pci_config_table gt_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+
+	{}
+};
+
+struct pci_controller pci0_hose = {
+#ifndef CONFIG_P3G4
+	fixup_irq:gt_fixup_irq,
+#endif
+	config_table:gt_config_table,
+};
+
+struct pci_controller pci1_hose = {
+#ifndef CONFIG_P3G4
+	fixup_irq:gt_fixup_irq,
+#endif
+	config_table:gt_config_table,
+};
+
+void pci_init_board (void)
+{
+	unsigned int command;
+
+	pci0_hose.first_busno = 0;
+	pci0_hose.last_busno = 0xff;
+	local_buses[0] = pci0_hose.first_busno;
+	/* PCI memory space */
+	pci_set_region (pci0_hose.regions + 0,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_0_MEM_SPACE,
+			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci0_hose.regions + 1,
+			CFG_PCI0_IO_SPACE_PCI,
+			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci0_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci0_hose.region_count = 2;
+
+	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
+
+	pci_register_hose (&pci0_hose);
+
+#ifndef CONFIG_P3G4
+	pciArbiterEnable (PCI_HOST0);
+	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+#endif
+
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
+
+	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+
+	pci1_hose.first_busno = pci0_hose.last_busno + 1;
+	pci1_hose.last_busno = 0xff;
+	pci1_hose.current_busno = pci0_hose.current_busno;
+	local_buses[1] = pci1_hose.first_busno;
+
+	/* PCI memory space */
+	pci_set_region (pci1_hose.regions + 0,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_0_MEM_SPACE,
+			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (pci1_hose.regions + 1,
+			CFG_PCI1_IO_SPACE_PCI,
+			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+
+	pci_set_ops (&pci1_hose,
+		     pci_hose_read_config_byte_via_dword,
+		     pci_hose_read_config_word_via_dword,
+		     gt_read_config_dword,
+		     pci_hose_write_config_byte_via_dword,
+		     pci_hose_write_config_word_via_dword,
+		     gt_write_config_dword);
+
+	pci1_hose.region_count = 2;
+
+	pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
+
+	pci_register_hose (&pci1_hose);
+
+#ifndef CONFIG_P3G4
+	pciArbiterEnable (PCI_HOST1);
+	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+#endif
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MASTER;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+
+	pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
+
+	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+	command |= PCI_COMMAND_MEMORY;
+	pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
+}
diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c
new file mode 100755
index 0000000..8d63c6f
--- /dev/null
+++ b/board/evb64260/sdram_init.c
@@ -0,0 +1,662 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* sdram_init.c - automatic memory sizing */
+
+#include <common.h>
+#include <74xx_7xx.h>
+#include <galileo/memory.h>
+#include <galileo/pci.h>
+#include <galileo/gt64260R.h>
+#include <net.h>
+
+#include "eth.h"
+#include "mpsc.h"
+#include "i2c.h"
+#include "64260.h"
+
+/* #define	DEBUG */
+#define	MAP_PCI
+
+#ifdef DEBUG
+#define DP(x) x
+#else
+#define DP(x)
+#endif
+
+#define GB         (1 << 30)
+
+/* structure to store the relevant information about an sdram bank */
+typedef struct sdram_info {
+	uchar drb_size;
+	uchar registered, ecc;
+	uchar tpar;
+	uchar tras_clocks;
+	uchar burst_len;
+	uchar banks, slot;
+	int size;		/* detected size, not from I2C but from dram_size() */
+} sdram_info_t;
+
+#ifdef DEBUG
+void dump_dimm_info (struct sdram_info *d)
+{
+	static const char *ecc_legend[] = { "", " Parity", " ECC" };
+
+	printf ("dimm%s %sDRAM: %dMibytes:\n",
+		ecc_legend[d->ecc],
+		d->registered ? "R" : "", (d->size >> 20));
+	printf ("  drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
+		d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
+		d->banks, d->slot);
+}
+#endif
+
+static int
+memory_map_bank (unsigned int bankNo,
+		 unsigned int bankBase, unsigned int bankLength)
+{
+#ifdef DEBUG
+	if (bankLength > 0) {
+		printf ("mapping bank %d at %08x - %08x\n",
+			bankNo, bankBase, bankBase + bankLength - 1);
+	} else {
+		printf ("unmapping bank %d\n", bankNo);
+	}
+#endif
+
+	memoryMapBank (bankNo, bankBase, bankLength);
+
+	return 0;
+}
+
+#ifdef MAP_PCI
+static int
+memory_map_bank_pci (unsigned int bankNo,
+		     unsigned int bankBase, unsigned int bankLength)
+{
+	PCI_HOST host;
+
+	for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+		const int features =
+			PREFETCH_ENABLE |
+			DELAYED_READ_ENABLE |
+			AGGRESSIVE_PREFETCH |
+			READ_LINE_AGGRESSIVE_PREFETCH |
+			READ_MULTI_AGGRESSIVE_PREFETCH |
+			MAX_BURST_4 | PCI_NO_SWAP;
+
+		pciMapMemoryBank (host, bankNo, bankBase, bankLength);
+
+		pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+				       bankLength);
+
+		pciSetRegionFeatures (host, bankNo, features, bankBase,
+				      bankLength);
+	}
+	return 0;
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* much of this code is based on (or is) the code in the pip405 port */
+/* thanks go to the authors of said port - Josh */
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+static inline unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+#ifdef CONFIG_ZUMA_V2
+static int check_dimm (uchar slot, sdram_info_t * info)
+{
+	/* assume 2 dimms, 2 banks each 256M - we dont have an
+	 * dimm i2c so rely on the detection routines later */
+
+	memset (info, 0, sizeof (*info));
+
+	info->slot = slot;
+	info->banks = 2;	/* Detect later */
+	info->registered = 0;
+	info->drb_size = 32;	/* 16 - 256MBit, 32 - 512MBit
+				   but doesn't matter, both do same
+				   thing in setup_sdram() */
+	info->tpar = 3;
+	info->tras_clocks = 5;
+	info->burst_len = 4;
+#ifdef CONFIG_ECC
+	info->ecc = 0;		/* Detect later */
+#endif /* CONFIG_ECC */
+	return 0;
+}
+
+#elif defined(CONFIG_P3G4)
+
+static int check_dimm (uchar slot, sdram_info_t * info)
+{
+	memset (info, 0, sizeof (*info));
+
+	if (slot)
+		return 0;
+
+	info->slot = slot;
+	info->banks = 1;
+	info->registered = 0;
+	info->drb_size = 4;
+	info->tpar = 3;
+	info->tras_clocks = 6;
+	info->burst_len = 4;
+#ifdef CONFIG_ECC
+	info->ecc = 2;
+#endif
+	return 0;
+}
+
+#else  /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
+
+/* This code reads the SPD chip on the sdram and populates
+ * the array which is passed in with the relevant information */
+static int check_dimm (uchar slot, sdram_info_t * info)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
+	int ret;
+	uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
+	ulong tmemclk;
+	uchar trp_clocks, trcd_clocks;
+	uchar data[128];
+
+	get_clocks ();
+
+	tmemclk = 1000000000 / (gd->bus_clk / 100);	/* in 10 ps units */
+
+#ifdef CONFIG_EVB64260_750CX
+	if (0 != slot) {
+		printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
+		printf ("            called with slot=%d insetad!\n", slot);
+		return 0;
+	}
+#endif
+	DP (puts ("before i2c read\n"));
+
+	ret = i2c_read (addr, 0, 128, data, 0);
+
+	DP (puts ("after i2c read\n"));
+
+	/* zero all the values */
+	memset (info, 0, sizeof (*info));
+
+	if (ret) {
+		DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
+		return 0;
+	}
+
+	/* first, do some sanity checks */
+	if (data[2] != 0x4) {
+		printf ("Not SDRAM in slot %d\n", slot);
+		return 0;
+	}
+
+	/* get various information */
+	rows = data[3];
+	cols = data[4];
+	info->banks = data[5];
+	sdram_banks = data[17];
+	width = data[13] & 0x7f;
+
+	DP (printf
+	    ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
+
+	/* check if the memory is registered */
+	if (data[21] & (BIT1 | BIT4))
+		info->registered = 1;
+
+#ifdef CONFIG_ECC
+	/* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
+	info->ecc = (data[11] & 2) >> 1;
+#endif
+
+	/* bit 1 is CL2, bit 2 is CL3 */
+	supp_cal = (data[18] & 0x6) >> 1;
+
+	/* compute the relevant clock values */
+	trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
+	trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
+	info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
+
+	DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
+		    trp_clocks, trcd_clocks, info->tras_clocks));
+
+	/* try a CAS latency of 3 first... */
+	cal_val = 0;
+	if (supp_cal & 3) {
+		if (NS10to10PS (data[9]) <= tmemclk)
+			cal_val = 3;
+	}
+
+	/* then 2... */
+	if (supp_cal & 2) {
+		if (NS10to10PS (data[23]) <= tmemclk)
+			cal_val = 2;
+	}
+
+	DP (printf ("cal_val = %d\n", cal_val));
+
+	/* bummer, did't work... */
+	if (cal_val == 0) {
+		DP (printf ("Couldn't find a good CAS latency\n"));
+		return 0;
+	}
+
+	/* get the largest delay -- these values need to all be the same
+	 * see Res#6 */
+	info->tpar = cal_val;
+	if (trp_clocks > info->tpar)
+		info->tpar = trp_clocks;
+	if (trcd_clocks > info->tpar)
+		info->tpar = trcd_clocks;
+
+	DP (printf ("tpar set to: %d\n", info->tpar));
+
+#ifdef CFG_BROKEN_CL2
+	if (info->tpar == 2) {
+		info->tpar = 3;
+		DP (printf ("tpar fixed-up to: %d\n", info->tpar));
+	}
+#endif
+	/* compute the module DRB size */
+	info->drb_size =
+		(((1 << (rows + cols)) * sdram_banks) * width) / _16M;
+
+	DP (printf ("drb_size set to: %d\n", info->drb_size));
+
+	/* find the burst len */
+	info->burst_len = data[16] & 0xf;
+	if ((info->burst_len & 8) == 8) {
+		info->burst_len = 1;
+	} else if ((info->burst_len & 4) == 4) {
+		info->burst_len = 0;
+	} else {
+		return 0;
+	}
+
+	info->slot = slot;
+	return 0;
+}
+#endif /* ! CONFIG_ZUMA_V2 */
+
+static int setup_sdram_common (sdram_info_t info[2])
+{
+	ulong tmp;
+	int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
+
+	if (!info[0].banks && !info[1].banks)
+		return 0;
+
+	if (info[0].banks) {
+		if (info[0].tpar > tpar)
+			tpar = info[0].tpar;
+		if (info[0].tras_clocks > tras_clocks)
+			tras_clocks = info[0].tras_clocks;
+		if (!info[0].registered)
+			registered = 0;
+		if (info[0].ecc != 2)
+			ecc = 0;
+	}
+
+	if (info[1].banks) {
+		if (info[1].tpar > tpar)
+			tpar = info[1].tpar;
+		if (info[1].tras_clocks > tras_clocks)
+			tras_clocks = info[1].tras_clocks;
+		if (!info[1].registered)
+			registered = 0;
+		if (info[1].ecc != 2)
+			ecc = 0;
+	}
+
+	/* SDRAM configuration */
+	tmp = GTREGREAD (SDRAM_CONFIGURATION);
+
+	/* Turn on physical interleave if both DIMMs
+	 * have even numbers of banks. */
+	if ((info[0].banks == 0 || info[0].banks == 2) &&
+	    (info[1].banks == 0 || info[1].banks == 2)) {
+		/* physical interleave on */
+		tmp &= ~(1 << 15);
+	} else {
+		/* physical interleave off */
+		tmp |= (1 << 15);
+	}
+
+	tmp |= (registered << 17);
+
+	/* Use buffer 1 to return read data to the CPU
+	 * See Res #12 */
+	tmp |= (1 << 26);
+
+	GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
+	DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
+
+	/* SDRAM timing */
+	tmp = (((tpar == 3) ? 2 : 1) |
+	       (((tpar == 3) ? 2 : 1) << 2) |
+	       (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
+
+#ifdef CONFIG_ECC
+	/* Setup ECC */
+	if (ecc == 2)
+		tmp |= 1 << 13;
+#endif /* CONFIG_ECC */
+
+	GT_REG_WRITE (SDRAM_TIMING, tmp);
+	DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
+		    GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
+
+	/* SDRAM address decode register */
+	/* program this with the default value */
+	GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
+	DP (printf ("SDRAM decode: %08x\n",
+		    GTREGREAD (SDRAM_ADDRESS_DECODE)));
+
+	return 0;
+}
+
+/* sets up the GT properly with information passed in */
+static int setup_sdram (sdram_info_t * info)
+{
+	ulong tmp, check;
+	ulong *addr = 0;
+	int i;
+
+	/* sanity checking */
+	if (!info->banks)
+		return 0;
+
+	/* ---------------------------- */
+	/* Program the GT with the discovered data */
+
+	/* bank parameters */
+	tmp = (0xf << 16);	/* leave all virt bank pages open */
+
+	DP (printf ("drb_size: %d\n", info->drb_size));
+	switch (info->drb_size) {
+	case 1:
+		tmp |= (1 << 14);
+		break;
+	case 4:
+	case 8:
+		tmp |= (2 << 14);
+		break;
+	case 16:
+	case 32:
+		tmp |= (3 << 14);
+		break;
+	default:
+		printf ("Error in dram size calculation\n");
+		return 1;
+	}
+
+	/* SDRAM bank parameters */
+	/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
+	GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
+	GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
+	DP (printf
+	    ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
+	     info->slot * 2, (info->slot * 2) + 1, tmp));
+
+	/* set the SDRAM configuration for each bank */
+	for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
+		DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
+
+		/* map the bank */
+		memory_map_bank (i, 0, GB / 4);
+
+		/* set SDRAM mode */
+		GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
+		check = GTREGREAD (SDRAM_OPERATION_MODE);
+
+		/* dummy write */
+		*addr = 0;
+
+		/* wait for the command to complete */
+		while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
+
+		/* switch back to normal operation mode */
+		GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
+		check = GTREGREAD (SDRAM_OPERATION_MODE);
+
+		/* unmap the bank */
+		memory_map_bank (i, 0, 0);
+		DP (printf ("*** MRS cycle for bank %d done ***\n", i));
+	}
+
+	return 0;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int *base, long int maxsize)
+{
+	volatile long int *addr, *b = base;
+	long int cnt, val, save1, save2;
+
+#define STARTVAL (1<<20)	/* start test at 1M */
+	for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+	     cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save1 = *addr;	/* save contents of addr */
+		save2 = *b;	/* save contents of base */
+
+		*addr = cnt;	/* write cnt to addr */
+		*b = 0;		/* put null at base */
+
+		/* check at base address */
+		if ((*b) != 0) {
+			*addr = save1;	/* restore *addr */
+			*b = save2;	/* restore *b */
+			return (0);
+		}
+		val = *addr;	/* read *addr */
+
+		*addr = save1;
+		*b = save2;
+
+		if (val != cnt) {
+			/* fix boundary condition.. STARTVAL means zero */
+			if (cnt == STARTVAL / sizeof (long))
+				cnt = 0;
+			return (cnt * sizeof (long));
+		}
+	}
+	return maxsize;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* U-Boot interface function to SDRAM init - this is where all the
+ * controlling logic happens */
+long int initdram (int board_type)
+{
+	ulong checkbank[4] = {[0 ... 3] = 0 };
+	int bank_no;
+	ulong total;
+	int nhr;
+	sdram_info_t dimm_info[2];
+
+
+	/* first, use the SPD to get info about the SDRAM */
+
+	/* check the NHR bit and skip mem init if it's already done */
+	nhr = get_hid0 () & (1 << 16);
+
+	if (nhr) {
+		printf ("Skipping SDRAM setup due to NHR bit being set\n");
+	} else {
+		/* DIMM0 */
+		check_dimm (0, &dimm_info[0]);
+
+		/* DIMM1 */
+#ifndef CONFIG_EVB64260_750CX	/* EVB64260_750CX has only 1 DIMM */
+		check_dimm (1, &dimm_info[1]);
+#else  /* CONFIG_EVB64260_750CX */
+		memset (&dimm_info[1], 0, sizeof (sdram_info_t));
+#endif
+
+		/* unmap all banks */
+		memory_map_bank (0, 0, 0);
+		memory_map_bank (1, 0, 0);
+		memory_map_bank (2, 0, 0);
+		memory_map_bank (3, 0, 0);
+
+		/* Now, program the GT with the correct values */
+		if (setup_sdram_common (dimm_info)) {
+			printf ("Setup common failed.\n");
+		}
+
+		if (setup_sdram (&dimm_info[0])) {
+			printf ("Setup for DIMM1 failed.\n");
+		}
+
+		if (setup_sdram (&dimm_info[1])) {
+			printf ("Setup for DIMM2 failed.\n");
+		}
+
+		/* set the NHR bit */
+		set_hid0 (get_hid0 () | (1 << 16));
+	}
+	/* next, size the SDRAM banks */
+
+	total = 0;
+	if (dimm_info[0].banks > 0)
+		checkbank[0] = 1;
+	if (dimm_info[0].banks > 1)
+		checkbank[1] = 1;
+	if (dimm_info[0].banks > 2)
+		printf ("Error, SPD claims DIMM1 has >2 banks\n");
+
+	if (dimm_info[1].banks > 0)
+		checkbank[2] = 1;
+	if (dimm_info[1].banks > 1)
+		checkbank[3] = 1;
+	if (dimm_info[1].banks > 2)
+		printf ("Error, SPD claims DIMM2 has >2 banks\n");
+
+	/* Generic dram sizer: works even if we don't have i2c DIMMs,
+	 * as long as the timing settings are more or less correct */
+
+	/*
+	 * pass 1: size all the banks, using first bat (0-256M)
+	 *         limitation: we only support 256M per bank due to
+	 *         us only having 1 BAT for all DRAM
+	 */
+	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+		/* skip over banks that are not populated */
+		if (!checkbank[bank_no])
+			continue;
+
+		DP (printf ("checking bank %d\n", bank_no));
+
+		memory_map_bank (bank_no, 0, GB / 4);
+		checkbank[bank_no] = dram_size (NULL, GB / 4);
+		memory_map_bank (bank_no, 0, 0);
+
+		DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
+	}
+
+	/*
+	 * pass 2: contiguously map each bank into physical address
+	 *         space.
+	 */
+	dimm_info[0].banks = dimm_info[1].banks = 0;
+	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+		if (!checkbank[bank_no])
+			continue;
+
+		dimm_info[bank_no / 2].banks++;
+		dimm_info[bank_no / 2].size += checkbank[bank_no];
+
+		memory_map_bank (bank_no, total, checkbank[bank_no]);
+#ifdef MAP_PCI
+		memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
+#endif
+		total += checkbank[bank_no];
+	}
+
+#ifdef CONFIG_ECC
+#ifdef CONFIG_ZUMA_V2
+	/*
+	 * We always enable ECC when bank 2 and 3 are unpopulated
+	 * If we 2 or 3 are populated, we CAN'T support ECC.
+	 * (Zuma boards only support ECC in banks 0 and 1; assume that
+	 * in that configuration, ECC chips are mounted, even for stacked
+	 * chips)
+	 */
+	if (checkbank[2] == 0 && checkbank[3] == 0) {
+		dimm_info[0].ecc = 2;
+		GT_REG_WRITE (SDRAM_TIMING,
+			      GTREGREAD (SDRAM_TIMING) | (1 << 13));
+		/* TODO: do we have to run MRS cycles again? */
+	}
+#endif /* CONFIG_ZUMA_V2 */
+
+	if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
+		puts ("[ECC] ");
+	}
+#endif /* CONFIG_ECC */
+
+#ifdef DEBUG
+	dump_dimm_info (&dimm_info[0]);
+	dump_dimm_info (&dimm_info[1]);
+#endif
+	/* TODO: return at MOST 256M? */
+	/* return total > GB/4 ? GB/4 : total; */
+	return total;
+}
diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c
new file mode 100755
index 0000000..d9c7a15
--- /dev/null
+++ b/board/evb64260/serial.c
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * serial.c - serial support for the gal ev board
+ */
+
+/* supports both the 16650 duart and the MPSC */
+
+#include <common.h>
+#include <command.h>
+#include <galileo/memory.h>
+
+#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+#include <ns16550.h>
+#endif
+
+#include "serial.h"
+
+#include "mpsc.h"
+
+#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1,
+				(NS16550_t) CFG_NS16550_COM2 };
+#endif
+
+#ifdef CONFIG_MPSC
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+#endif
+
+	mpsc_init(gd->baudrate);
+
+	/* init the DUART chans so that KGDB in the kernel can use them */
+#ifdef CFG_INIT_CHAN1
+	NS16550_reinit(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	NS16550_reinit(COM_PORTS[1], clock_divisor);
+#endif
+	return (0);
+}
+
+void
+serial_putc(const char c)
+{
+	if (c == '\n')
+		mpsc_putchar('\r');
+
+	mpsc_putchar(c);
+}
+
+int
+serial_getc(void)
+{
+	return mpsc_getchar();
+}
+
+int
+serial_tstc(void)
+{
+	return mpsc_test_char();
+}
+
+void
+serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate);
+}
+
+#else /* ! CONFIG_MPSC */
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+	(void)NS16550_init(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	(void)NS16550_init(COM_PORTS[1], clock_divisor);
+#endif
+
+	return (0);
+}
+
+void
+serial_putc(const char c)
+{
+	if (c == '\n')
+		NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r');
+
+	NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c);
+}
+
+int
+serial_getc(void)
+{
+	return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]);
+}
+
+int
+serial_tstc(void)
+{
+	return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]);
+}
+
+void
+serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+	NS16550_reinit(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	NS16550_reinit(COM_PORTS[1], clock_divisor);
+#endif
+}
+
+#endif /* CONFIG_MPSC */
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+void
+kgdb_serial_init(void)
+{
+}
+
+void
+putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void
+putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int
+getDebugChar (void)
+{
+	return serial_getc();
+}
+
+void
+kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif	/* CFG_CMD_KGDB	*/
diff --git a/board/evb64260/serial.h b/board/evb64260/serial.h
new file mode 100755
index 0000000..bac9253
--- /dev/null
+++ b/board/evb64260/serial.h
@@ -0,0 +1,63 @@
+/* serial.h - mostly useful for DUART serial_init in serial.c */
+
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#if 0
+
+#define B230400         1
+#define B115200         2
+#define B57600          4
+#define B38400          82
+#define B19200          163
+#define B9600           24
+#define B4800           651
+#define B2400           1302
+#define B1200           2604
+#define B600            5208
+#define B300            10417
+#define B150            20833
+#define B110            28409
+#define BDEFAULT        B115200
+
+				/* this stuff is important to initialize
+				the DUART channels */
+
+#define	Scale		0x01L		/* distance between port addresses */
+#define	COM1		0x000003f8		/* Keyboard */
+#define COM2		0x000002f8		/* Host */
+
+
+/* Port Definitions relative to base COM port addresses */
+#define DataIn	(0x00*Scale)	/* data input port */
+#define DataOut	(0x00*Scale)	/* data output port */
+#define BaudLsb	(0x00*Scale)	/* baud rate divisor least significant byte */
+#define BaudMsb	(0x01*Scale)	/* baud rate divisor most significant byte */
+#define	Ier	(0x01*Scale)	/* interrupt enable register */
+#define	Iir	(0x02*Scale)	/* interrupt identification register */
+#define	Lcr	(0x03*Scale)	/* line control register */
+#define	Mcr	(0x04*Scale)	/* modem control register */
+#define	Lsr	(0x05*Scale)	/* line status register */
+#define	Msr	(0x06*Scale)	/* modem status register */
+
+/* Bit Definitions for above ports */
+#define LcrDlab	0x80	/* b7:	 enable baud rate divisor registers */
+#define	LcrDflt	0x03	/* b6-0: no parity, 1 stop, 8 data */
+
+#define	McrRts	0x02	/* b1:	request to send (I am ready to xmit) */
+#define	McrDtr	0x01	/* b0:	data terminal ready (I am alive ready to rcv) */
+#define	McrDflt	(McrRts|McrDtr)
+
+#define LsrTxD	0x6000	/* b5: transmit holding register empty (i.e. xmit OK!)*/
+			/* b6: transmitter empty */
+#define LsrRxD	0x0100	/* b0: received data ready (i.e. got a byte!) */
+
+#define	MsrRi	0x0040	/* b6: ring indicator (other guy is ready to rcv) */
+#define	MsrDsr	0x0020	/* b5: data set ready (other guy is alive ready to rcv */
+#define	MsrCts	0x0010	/* b4: clear to send (other guy is ready to rcv) */
+
+#define IerRda	0xf	/* b0: Enable received data available interrupt */
+
+#endif
+
+#endif /* __SERIAL_H__ */
diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds
new file mode 100755
index 0000000..d89eb6c
--- /dev/null
+++ b/board/evb64260/u-boot.lds
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c
new file mode 100755
index 0000000..d64025a
--- /dev/null
+++ b/board/evb64260/zuma_pbb.c
@@ -0,0 +1,220 @@
+#include <common.h>
+#include <malloc.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+#include <command.h>
+#endif
+
+#include <pci.h>
+#include <galileo/pci.h>
+#include "zuma_pbb.h"
+
+#undef DEBUG
+
+#define PAT_LO 0x00010203
+#define PAT_HI 0x04050607
+
+static PBB_DMA_REG_MAP *zuma_pbb_reg = NULL;
+static char test_buf1[2048];
+static char test_buf2[2048];
+void zuma_init_pbb(void);
+int zuma_mbox_init(void);
+int zuma_test_dma(int cmd, int size);
+
+int zuma_test_dma (int cmd, int size)
+{
+	static const char *const test_legend[] = {
+		"write", "verify",
+		"copy", "compare",
+		"write inc", "verify inc"
+	};
+	register int i, j;
+	unsigned int p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff);
+	unsigned int p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff);
+	volatile unsigned int *ps = (unsigned int *) p1;
+	volatile unsigned int *pd = (unsigned int *) p2;
+	unsigned int funct, pat_lo = PAT_LO, pat_hi = PAT_HI;
+	DMA_INT_STATUS stat;
+	int ret = 0;
+
+	if (!zuma_pbb_reg) {
+		printf ("not initted\n");
+		return -1;
+	}
+
+	if (cmd < 0 || cmd > 5) {
+		printf ("inv cmd %d\n", cmd);
+		return -1;
+	}
+
+	if (cmd == 2 || cmd == 3) {
+		/* not implemented */
+		return 0;
+	}
+
+	if (size <= 0 || size > 1024)
+		size = 1024;
+
+	size &= (~7);				/* throw away bottom 3 bits */
+
+	p1 = ((unsigned int) test_buf1 + 0xff) & (~0xff);
+	p2 = ((unsigned int) test_buf2 + 0xff) & (~0xff);
+
+	memset ((void *) p1, 0, size);
+	memset ((void *) p2, 0, size);
+
+	for (i = 0; i < size / 4; i += 2) {
+		ps[i] = pat_lo;
+		ps[i + 1] = pat_hi;
+		if (cmd == 4 || cmd == 5) {
+			unsigned char *pl = (unsigned char *) &pat_lo;
+			unsigned char *ph = (unsigned char *) &pat_hi;
+
+			for (j = 0; j < 4; j++) {
+				pl[j] += 8;
+				ph[j] += 8;
+			}
+		}
+	}
+
+	funct = (1 << 31) | (cmd << 24) | (size);
+
+	zuma_pbb_reg->int_mask.pci_bits.chan0 =
+			EOF_RX_FLAG | EOF_TX_FLAG | EOB_TX_FLAG;
+
+	zuma_pbb_reg->debug_57 = PAT_LO;	/* patl */
+	zuma_pbb_reg->debug_58 = PAT_HI;	/* path */
+
+	zuma_pbb_reg->debug_54 = cpu_to_le32 (p1);	/* src 0x01b0 */
+	zuma_pbb_reg->debug_55 = cpu_to_le32 (p2);	/* dst 0x01b8 */
+	zuma_pbb_reg->debug_56 = cpu_to_le32 (funct);	/* func, 0x01c0 */
+
+	/* give DMA time to chew on things.. dont use DRAM or PCI */
+	/* if you can avoid it. */
+	do {
+		for (i = 0; i < 1000 * 10; i++);
+	} while (le32_to_cpu (zuma_pbb_reg->debug_56) & (1 << 31));
+
+	stat.word = zuma_pbb_reg->status.word;
+	zuma_pbb_reg->int_mask.word = 0;
+
+	printf ("stat: %08x (%x)\n", stat.word, stat.pci_bits.chan0);
+
+	printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56));
+	printf ("src @%08x: %08x %08x %08x %08x\n", p1, ps[0], ps[1], ps[2],
+			ps[3]);
+	printf ("dst @%08x: %08x %08x %08x %08x\n", p2, pd[0], pd[1], pd[2],
+			pd[3]);
+	printf ("func: %08x\n", le32_to_cpu (zuma_pbb_reg->debug_56));
+
+
+	if (cmd == 0 || cmd == 4) {
+		/* this is a write */
+		if (!(stat.pci_bits.chan0 & EOF_RX_FLAG) ||	/* not done */
+			(memcmp ((void *) ps, (void *) pd, size) != 0)) {	/* cmp error */
+			for (i = 0; i < size / 4; i += 2) {
+				if ((ps[i] != pd[i]) || (ps[i + 1] != pd[i + 1])) {
+					printf ("s @%p:%08x %08x\n", &ps[i], ps[i], ps[i + 1]);
+					printf ("d @%p:%08x %08x\n", &pd[i], pd[i], pd[i + 1]);
+				}
+			}
+			ret = -1;
+		}
+	} else {
+		/* this is a verify */
+		if (!(stat.pci_bits.chan0 & EOF_TX_FLAG) ||	/* not done */
+			(stat.pci_bits.chan0 & EOB_TX_FLAG)) {	/* cmp error */
+			printf ("%08x: %08x %08x\n",
+					le32_to_cpu (zuma_pbb_reg->debug_63),
+					zuma_pbb_reg->debug_61, zuma_pbb_reg->debug_62);
+			ret = -1;
+		}
+	}
+
+	printf ("%s cmd %d, %d bytes: %s!\n", test_legend[cmd], cmd, size,
+			(ret == 0) ? "PASSED" : "FAILED");
+	return 0;
+}
+
+void zuma_init_pbb (void)
+{
+	unsigned int iobase;
+	pci_dev_t dev =
+			pci_find_device (VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
+
+	if (dev == -1) {
+		printf ("no zuma pbb\n");
+		return;
+	}
+
+	pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase);
+
+	zuma_pbb_reg =
+			(PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+	if (!zuma_pbb_reg) {
+		printf ("zuma pbb bar none! (hah hah, get it?)\n");
+		return;
+	}
+
+	zuma_pbb_reg->int_mask.word = 0;
+
+	printf ("pbb @ %p v%d.%d, timestamp %08x\n", zuma_pbb_reg,
+			zuma_pbb_reg->version.pci_bits.rev_major,
+			zuma_pbb_reg->version.pci_bits.rev_minor,
+			zuma_pbb_reg->timestamp);
+
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+static int last_cmd = 4;		/* write increment */
+static int last_size = 64;
+
+int
+do_zuma_init_pbb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	zuma_init_pbb ();
+	return 0;
+}
+
+int
+do_zuma_test_dma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc > 1) {
+		last_cmd = simple_strtoul (argv[1], NULL, 10);
+	}
+	if (argc > 2) {
+		last_size = simple_strtoul (argv[2], NULL, 10);
+	}
+	zuma_test_dma (last_cmd, last_size);
+	return 0;
+}
+
+int
+do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	zuma_mbox_init ();
+	return 0;
+}
+
+U_BOOT_CMD(
+	zinit,	 1,	 0,	 do_zuma_init_pbb,
+	"zinit   - init zuma pbb\n",
+	"\n"
+	"    - init zuma pbb\n"
+);
+U_BOOT_CMD(
+	zdtest,	  3,	  1,	  do_zuma_test_dma,
+	"zdtest  - run dma test\n",
+	"[cmd [count]]\n"
+	"    - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n"
+);
+U_BOOT_CMD(
+	zminit,	  1,	  0,	  do_zuma_init_mbox,
+	"zminit  - init zuma mbox\n",
+	"\n"
+	"    - init zuma mbox\n"
+);
+
+#endif /* CFG_CMD_BSP */
diff --git a/board/evb64260/zuma_pbb.h b/board/evb64260/zuma_pbb.h
new file mode 100755
index 0000000..300b2fe
--- /dev/null
+++ b/board/evb64260/zuma_pbb.h
@@ -0,0 +1,346 @@
+#ifndef ZUMA_PBB_H
+#define ZUMA_PBB_H
+
+#define MAX_NUM_BUFFER_PER_RING	32
+
+#ifdef __BIG_ENDIAN
+#define cpu_bits _be_s_bits	/* use with le32_to_cpu only */
+#define pci_bits _be_bits	/* may contain swapped bytes,
+				   but dont need le32_to_cpu */
+#endif
+
+#ifdef __LITTLE_ENDIAN
+#define cpu_bits _le_bits
+#define pci_bits _le_bits
+#endif
+
+#define VENDOR_ID_ZUMA		0x1172
+#define DEVICE_ID_ZUMA_PBB	0x0004
+
+#define RXDBP(chan)		(&sip->rx_desc[chan].base)	/* ch*8      */
+#define RXDP(chan)		(&sip->rx_desc[chan].current)	/* ch*8 +  4 */
+#define TXDBP(chan)		(&sip->tx_desc[chan].base)	/* ch*8 + 64 */
+#define TXDP(chan)		(&sip->tx_desc[chan].current)	/* ch*8 + 68 */
+
+#define PBB_DMA_OWN_BIT		0x80000000
+#define PBB_DMA_LAST_BIT	0x40000000
+
+#define EOF_RX_FLAG		1	/* bit 0 */
+#define EOB_RX_FLAG		2	/* bit 1 */
+#define EOF_TX_FLAG		4	/* bit 2 */
+#define EOB_TX_FLAG		8	/* bit 3 */
+
+#define TX_MODE(m)		(((m)&7) << 16)
+
+#define RX_DESC(i)		(cs->rx_desc[i])
+#define TX_DESC(i)		(cs->tx_desc[i])
+
+#define RX_CONTROL(i)		(RX_DESC(i).control.word)
+#define RX_CONTROL_SIZE(i)	(RX_DESC(i).control.rx.size)
+#define TX_CONTROL(i)		(TX_DESC(i).control.word)
+
+#define RX_DATA_P(i)		(&RX_DESC(i).ptr)
+#define TX_DATA_P(i)		(&TX_DESC(i).ptr)
+
+typedef volatile unsigned char V8;
+typedef volatile unsigned short V16;
+typedef volatile unsigned int V32;
+
+/* RAM descriptor layout */
+typedef struct _tag_dma_descriptor {
+    V32 ptr;
+    union {
+	struct {
+	    V32 owner:1;
+	    V32 last:1;
+	    V32 reserved0: 10;
+	    V32 tx_mode: 4;
+
+	    V32 reserved1: 5;
+	    V32 size: 11;
+	} tx;
+	struct {
+	    V32 owner:1;
+	    V32 last:1;
+	    V32 reserved0: 14;
+
+	    V32 reserved1: 5;
+	    V32 size: 11;
+	} rx;
+	V32 word;
+    } control;
+} DMA_DESCRIPTOR;
+
+/*
+ * NOTE: DO NOT USE structure to write non-word values... all registers
+ * MUST be written 4 bytes at a time in SI version 0.
+ * Non-word writes will result in "unaccessed" bytes written as zero.
+ *
+ * Byte reads are allowed.
+ *
+ * V32 pads are because the registers are spaced every 8 bytes (64 bits)
+ *
+ */
+
+/* NOTE!!! 4 dwords */
+typedef struct _tag_dma_descriptor_ring {
+    DMA_DESCRIPTOR *base;
+    V32 pad1;	/* skip high dword */
+    volatile DMA_DESCRIPTOR *current;
+    V32 pad3;	/* skip high dword */
+} DMA_DESCRIPTOR_RING;
+
+/* 1 dword */
+typedef union _tag_dma_generic {
+    struct {	/* byte 3 2 1 0 */
+	V32 chan7:4;	/* bits 31-28 */
+	V32 chan6:4;	/* bits 27-24 */
+	V32 chan5:4;	/* bits 23-20 */
+	V32 chan4:4;	/* bits 19-16 */
+	V32 chan3:4;	/* bits 15-12 */
+	V32 chan2:4;	/* bits 11-8 */
+	V32 chan1:4;	/* bits 7-4 */
+	V32 chan0:4;	/* bits 3-0 */
+    } _be_s_bits;
+    struct {	/* byte 0 1 2 3 */
+	V32 chan1:4;	/* bits 7-4 */
+	V32 chan0:4;	/* bits 3-0 */
+	V32 chan3:4;	/* bits 15-12 */
+	V32 chan2:4;	/* bits 11-8 */
+	V32 chan5:4;	/* bits 23-20 */
+	V32 chan4:4;	/* bits 19-16 */
+	V32 chan7:4;	/* bits 31-28 */
+	V32 chan6:4;	/* bits 27-24 */
+    } _be_bits;
+    struct {	/* byte 0 1 2 3 */
+	V32 chan0:4;	/* bits 0-3 */
+	V32 chan1:4;	/* bits 4-7 */
+	V32 chan2:4;	/* bits 8-11 */
+	V32 chan3:4;	/* bits 12-15 */
+	V32 chan4:4;	/* bits 16-19 */
+	V32 chan5:4;	/* bits 20-23 */
+	V32 chan6:4;	/* bits 24-27 */
+	V32 chan7:4;	/* bits 28-31 */
+    } _le_bits;
+    V8 byte[4];
+    V32 word;
+} DMA_RXTX_ENABLE, DMA_RX_DELETE,
+  DMA_INT_STATUS, DMA_INT_MASK,
+  DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK;
+
+/* 1 dword */
+typedef union _tag_dma_rx_timer{
+    struct {
+	V32 res0:8;	/* bits 32-24 */
+	V32 res1:7;	/* bits 23-17 */
+	V32 enable:1;	/* bit 16 */
+	V32 value:16;	/* bits 15-0 */
+    } _be_s_bits;
+    struct {
+	/* crosses byte boundary. must use swap. */
+	V32 s_value:16;	/* bits 7-0,15-8 */
+	V32 enable:1;	/* bit 16 */
+	V32 res1:7;	/* bits 23-17 */
+	V32 res0:8;	/* bits 32-24 */
+    } _be_bits;
+    struct {
+	V32 value:16;	/* bits 0-15 */
+	V32 enable:1;	/* bit 16 */
+	V32 res1:7;	/* bits 17-23 */
+	V32 res0:8;	/* bits 24-32 */
+    } _le_bits;
+    V8 byte[4];
+    V32 word;
+} DMA_RX_TIMER;
+
+/* NOTE!!!: 2 dwords */
+typedef struct _tag_dma_desc_level{
+    union {
+	struct {
+	    V32 res1:8;	/* bits 31-24 */
+	    V32 res0:7;	/* bits 23-17 */
+	    V32 write:1;	/* bit 16 */
+	    V32 thresh:8;	/* bits 15-8 */
+	    V32 level:8;	/* bits 7-0 */
+	} _be_s_bits;
+	struct {
+	    V32 level:8;	/* bits 7-0 */
+	    V32 thresh:8;	/* bits 15-8 */
+	    V32 res0:7;	/* bits 30-17 */
+	    V32 write:1;	/* bit 16 */
+	    V32 res1:8;	/* bits 31-24 */
+	} _be_bits;
+	struct {
+	    V32 level:8;	/* bits 0-7 */
+	    V32 thresh:8;	/* bits 8-15 */
+	    V32 write:1;	/* bit 16 */
+	    V32 res0:7;	/* bit 17-30 */
+	    V32 res1:8;	/* bits 24-31 */
+	} _le_bits;
+	V8 byte[4];
+	V32 word;
+    } desc;
+    V32 pad1;
+} DMA_DESC_LEVEL;
+
+typedef struct _tag_pbb_dma_reg_map {
+    /* 0-15 (0x000-0x078) */
+    DMA_DESCRIPTOR_RING rx_desc[8];	/* 4 dwords each, 128 bytes tot. */
+
+    /* 16-31 (0x080-0x0f8) */
+    DMA_DESCRIPTOR_RING tx_desc[8];	/* 4 dwords each, 128 bytes tot. */
+
+    /* 32/33 (0x100/0x108) */
+    V32 reserved_32;
+    V32 pad_32;
+    V32 reserved_33;
+    V32 pad_33;
+
+    /* 34 (0x110) */
+    DMA_RXTX_ENABLE rxtx_enable;
+    V32 pad_34;
+
+    /* 35 (0x118) */
+    DMA_RX_DELETE rx_delete;
+    V32 pad_35;
+
+    /* 36-38 (0x120-0x130) */
+    DMA_INT_STATUS status;
+    V32 pad_36;
+    DMA_INT_STATUS last_status;
+    V32 pad_37;
+    DMA_INT_MASK int_mask;
+    V32 pad_38;
+
+    /* 39/40 (0x138/0x140) */
+    union {
+	/* NOTE!! 4 dwords */
+	struct {
+	    V32 channel_3:8;
+	    V32 channel_2:8;
+	    V32 channel_1:8;
+	    V32 channel_0:8;
+	    V32 pad1;
+	    V32 channel_7:8;
+	    V32 channel_6:8;
+	    V32 channel_5:8;
+	    V32 channel_4:8;
+	    V32 pad3;
+	} _be_s_bits;
+	struct {
+	    V32 channel_0:8;
+	    V32 channel_1:8;
+	    V32 channel_2:8;
+	    V32 channel_3:8;
+	    V32 pad1;
+	    V32 channel_4:8;
+	    V32 channel_5:8;
+	    V32 channel_6:8;
+	    V32 channel_7:8;
+	    V32 pad3;
+	} _be_bits, _le_bits;
+	V8 byte[16];
+	V32 word[4];
+    } rx_size;
+
+    /* 41/42 (0x148/0x150) */
+    V32 reserved_41;
+    V32 pad_41;
+    V32 reserved_42;
+    V32 pad_42;
+
+    /* 43/44 (0x158/0x160) */
+    DMA_RX_LEVEL_STATUS rx_level_status;
+    V32 pad_43;
+    DMA_RX_LEVEL_INT_MASK rx_level_int_mask;
+    V32 pad_44;
+
+    /* 45 (0x168) */
+    DMA_RX_TIMER rx_timer;
+    V32 pad_45;
+
+    /* 46 (0x170) */
+    V32 reserved_46;
+    V32 pad_46;
+
+    /* 47 (0x178) */
+    V32 mbox_status;
+    V32 pad_47;
+
+    /* 48/49 (0x180/0x188) */
+    V32 mbox_out;
+    V32 pad_48;
+    V32 mbox_in;
+    V32 pad_49;
+
+    /* 50 (0x190) */
+    V32 config;
+    V32 pad_50;
+
+    /* 51/52 (0x198/0x1a0) */
+    V32 c2a_ctr;
+    V32 pad_51;
+    V32 a2c_ctr;
+    V32 pad_52;
+
+    /* 53 (0x1a8) */
+    union {
+	struct {
+	    V32 rev_major:8;	/* bits 31-24 */
+	    V32 rev_minor:8;	/* bits 23-16 */
+	    V32 reserved:16;	/* bits 15-0 */
+	} _be_s_bits;
+	struct {
+	    V32 s_reserved:16;	/* bits 7-0, 15-8 */
+	    V32 rev_minor:8;	/* bits 23-16 */
+	    V32 rev_major:8;	/* bits 31-24 */
+	} _be_bits;
+	struct {
+	    V32 reserved:16;	/* bits 0-15 */
+	    V32 rev_minor:8;	/* bits 16-23 */
+	    V32 rev_major:8;	/* bits 24-31 */
+	} _le_bits;
+	V8 byte[4];
+	V32 word;
+    } version;
+    V32 pad_53;
+
+    /* 54-59 (0x1b0-0x1d8) */
+    V32 debug_54;
+    V32 pad_54;
+    V32 debug_55;
+    V32 pad_55;
+    V32 debug_56;
+    V32 pad_56;
+    V32 debug_57;
+    V32 pad_57;
+    V32 debug_58;
+    V32 pad_58;
+    V32 debug_59;
+    V32 pad_59;
+
+    /* 60 (0x1e0) */
+    V32 timestamp;
+    V32 pad_60;
+
+    /* 61-63 (0x1e8-0x1f8) */
+    V32 debug_61;
+    V32 pad_61;
+    V32 debug_62;
+    V32 pad_62;
+    V32 debug_63;
+    V32 pad_63;
+
+    /* 64-71 (0x200 - 0x238) */
+    DMA_DESC_LEVEL rx_desc_level[8];	/* 2 dwords each, 32 bytes tot. */
+
+    /* 72-98 (0x240 - 0x2f8) */
+    /* reserved */
+
+    /* 96-127 (0x300 - 0x3f8) */
+    /* mirrors (0x100 - 0x1f8) */
+
+} PBB_DMA_REG_MAP;
+
+
+#endif /* ZUMA_PBB_H */
diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c
new file mode 100755
index 0000000..2b9a469
--- /dev/null
+++ b/board/evb64260/zuma_pbb_mbox.c
@@ -0,0 +1,187 @@
+#include <common.h>
+#include <galileo/pci.h>
+#include <net.h>
+#include <pci.h>
+
+#include "zuma_pbb.h"
+#include "zuma_pbb_mbox.h"
+
+
+struct _zuma_mbox_dev zuma_mbox_dev;
+
+
+static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data)
+{
+  unsigned int status, count = 0, i;
+
+  status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+
+  while((status & OUT_PENDING) && count < 1000) {
+    count++;
+    for(i=0;i<1000;i++);
+    status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+  }
+  if(count < 1000) {
+    /* if SET it means msg pending */
+    /* printf("mbox real write %08x\n",data); */
+    dev->sip->mbox_out = cpu_to_le32(data);
+    return 4;
+  }
+
+  printf("mbox tx timeout\n");
+  return 0;
+}
+
+static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data)
+{
+  unsigned int status, count = 0, i;
+
+  status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+
+  while(!(status & IN_VALID) && count < 1000) {
+    count++;
+    for(i=0;i<1000;i++);
+    status = (volatile int)le32_to_cpu(dev->sip->mbox_status);
+  }
+  if(count < 1000) {
+    /* if SET it means msg pending */
+    *data=le32_to_cpu(dev->sip->mbox_in);
+    /*printf("mbox real read %08x\n", *data); */
+    return 4;
+  }
+  printf("mbox rx timeout\n");
+  return 0;
+}
+
+static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in)
+{
+  int ret;
+  ret=zuma_mbox_write(&zuma_mbox_dev,out);
+  /*printf("write 0x%08x (%d bytes)\n", out, ret); */
+  if(ret!=4) return -1;
+  ret=zuma_mbox_read(&zuma_mbox_dev,in);
+  /*printf("read 0x%08x (%d bytes)\n", *in, ret); */
+  if(ret!=4) return -1;
+  return 0;
+}
+
+
+#define RET_IF_FAILED(x)	if ((x) == -1) return -1
+
+static int zuma_mbox_do_all_mailbox(void)
+{
+  unsigned int data_in;
+  unsigned short sdata_in;
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in));
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in));
+  memcpy(zuma_acc_mac+2,&data_in,4);
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in));
+  sdata_in=data_in&0xffff;
+  memcpy(zuma_acc_mac,&sdata_in,2);
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in));
+  zuma_ip=data_in;
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in));
+  zuma_slot_bac=data_in>>3;
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in));
+  zuma_console_baud = data_in & 0xffff;
+  zuma_debug_baud   = data_in >> 16;
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in));
+  memcpy(zuma_prv_mac+2,&data_in,4);
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in));
+  sdata_in=data_in&0xffff;
+  memcpy(zuma_prv_mac,&sdata_in,2);
+
+  RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in));
+
+  return 0;
+}
+
+
+static void
+zuma_mbox_dump(void)
+{
+  printf("ACC MAC=%04x%08x\n",*(unsigned short *)(&zuma_acc_mac),*(unsigned int *)((char *)&zuma_acc_mac+2));
+  printf("PRV MAC=%04x%08x\n",*(unsigned short *)(&zuma_prv_mac),*(unsigned int *)((char *)&zuma_prv_mac+2));
+  printf("slot:bac=%d:%d\n",(zuma_slot_bac>>2)&0xf, zuma_slot_bac & 0x3);
+  printf("BAUD1=%d BAUD2=%d\n",zuma_console_baud,zuma_debug_baud);
+}
+
+
+static void
+zuma_mbox_setenv(void)
+{
+  char *data, buf[32];
+  unsigned char save = 0;
+
+  data = getenv("baudrate");
+
+  if(!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) {
+    sprintf(buf, "%6d", zuma_console_baud);
+    setenv("baudrate", buf);
+    save=1;
+    printf("baudrate doesn't match from mbox\n");
+  }
+
+  ip_to_string(zuma_ip, buf);
+  setenv("ipaddr", buf);
+
+  sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
+	  zuma_prv_mac[0],
+	  zuma_prv_mac[1],
+	  zuma_prv_mac[2],
+	  zuma_prv_mac[3],
+	  zuma_prv_mac[4],
+	  zuma_prv_mac[5]);
+  setenv("ethaddr", buf);
+
+  sprintf(buf,"%02x",zuma_slot_bac);
+  setenv("bacslot", buf);
+
+  if(save)
+    saveenv();
+}
+
+/**
+ * 	zuma_mbox_init:
+ */
+
+int zuma_mbox_init(void)
+{
+  unsigned int iobase;
+  memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev));
+
+  zuma_mbox_dev.dev = pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0);
+
+  if(zuma_mbox_dev.dev == -1) {
+    printf("no zuma pbb\n");
+    return -1;
+  }
+
+  pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase);
+
+  zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+  zuma_mbox_dev.sip->int_mask.word=0;
+
+  printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip,
+	 zuma_mbox_dev.sip->version.pci_bits.rev_major,
+	 zuma_mbox_dev.sip->version.pci_bits.rev_minor,
+	 zuma_mbox_dev.sip->timestamp);
+
+  if (zuma_mbox_do_all_mailbox() == -1) {
+	  printf("mailbox failed.. no ACC?\n");
+	  return -1;
+  }
+
+  zuma_mbox_dump();
+
+  zuma_mbox_setenv();
+
+  return 0;
+}
diff --git a/board/evb64260/zuma_pbb_mbox.h b/board/evb64260/zuma_pbb_mbox.h
new file mode 100755
index 0000000..b4a4c0c
--- /dev/null
+++ b/board/evb64260/zuma_pbb_mbox.h
@@ -0,0 +1,43 @@
+#define IN_VALID 1
+#define OUT_PENDING 2
+
+enum {
+	ZUMA_MBOXMSG_DONE,
+	ZUMA_MBOXMSG_MACL,
+	ZUMA_MBOXMSG_MACH,
+	ZUMA_MBOXMSG_IP,
+	ZUMA_MBOXMSG_SLOT,
+	ZUMA_MBOXMSG_RESET,
+	ZUMA_MBOXMSG_BAUD,
+	ZUMA_MBOXMSG_START,
+	ZUMA_MBOXMSG_ENG_PRV_MACL,
+	ZUMA_MBOXMSG_ENG_PRV_MACH,
+
+	MBOXMSG_LAST
+};
+
+struct zuma_mailbox_info {
+	unsigned char acc_mac[6];
+	unsigned char prv_mac[6];
+	unsigned int ip;
+	unsigned int slot_bac;
+	unsigned int console_baud;
+	unsigned int debug_baud;
+};
+
+struct _zuma_mbox_dev {
+	pci_dev_t dev;
+	PBB_DMA_REG_MAP *sip;
+	struct zuma_mailbox_info mailbox;
+};
+
+#define zuma_prv_mac		zuma_mbox_dev.mailbox.prv_mac
+#define zuma_acc_mac		zuma_mbox_dev.mailbox.acc_mac
+#define zuma_ip                 zuma_mbox_dev.mailbox.ip
+#define zuma_slot_bac		zuma_mbox_dev.mailbox.slot_bac
+#define zuma_console_baud	zuma_mbox_dev.mailbox.console_baud
+#define zuma_debug_baud		zuma_mbox_dev.mailbox.debug_baud
+
+
+extern struct _zuma_mbox_dev zuma_mbox_dev;
+extern int zuma_mbox_init (void);
diff --git a/board/exbitgen/Makefile b/board/exbitgen/Makefile
new file mode 100755
index 0000000..34bd4b2
--- /dev/null
+++ b/board/exbitgen/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/exbitgen/config.mk b/board/exbitgen/config.mk
new file mode 100755
index 0000000..42ea0c6
--- /dev/null
+++ b/board/exbitgen/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# ExbitGen board
+#
+
+LDFLAGS += $(LINKER_UNDEFS)
+
+TEXT_BASE := 0xFFF80000
+#TEXT_BASE := 0x00100000
+
+PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c
new file mode 100755
index 0000000..39a9722
--- /dev/null
+++ b/board/exbitgen/exbitgen.c
@@ -0,0 +1,117 @@
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+#include <common.h>
+#include "exbitgen.h"
+
+/* ************************************************************************ */
+int board_early_init_f (void)
+/* ------------------------------------------------------------------------ --
+ * Purpose     :
+ * Remarks     :
+ * Restrictions:
+ * See also    :
+ * Example     :
+ * ************************************************************************ */
+{
+	unsigned long i;
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000020);	/* set all but FPGA SMI to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF90);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	/* Perform reset of PHY connected to PPC via register in CPLD */
+	out8 (PHY_CTRL_ADDR, 0x2e);	/* activate nRESET,FDX,F100,ANEN, enable output */
+	for (i = 0; i < 10000000; i++) {
+		;
+	}
+	out8 (PHY_CTRL_ADDR, 0x2f);	/* deactivate nRESET */
+
+	return 0;
+}
+
+
+/* ************************************************************************ */
+int checkboard (void)
+/* ------------------------------------------------------------------------ --
+ * Purpose     :
+ * Remarks     :
+ * Restrictions:
+ * See also    :
+ * Example     :
+ * ************************************************************************ */
+{
+	printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR));
+	return (0);
+}
+
+/* ************************************************************************ */
+long int initdram (int board_type)
+/* ------------------------------------------------------------------------ --
+ * Purpose     : Determines size of mounted DRAM.
+ * Remarks     : Size is determined by reading SDRAM configuration registers as
+ *               set up by sdram_init.
+ * Restrictions:
+ * See also    :
+ * Example     :
+ * ************************************************************************ */
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	tot_size = 0;
+
+	mtdcr (memcfga, mem_mb0cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb1cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb2cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb3cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
diff --git a/board/exbitgen/exbitgen.h b/board/exbitgen/exbitgen.h
new file mode 100755
index 0000000..058ad48
--- /dev/null
+++ b/board/exbitgen/exbitgen.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define GPIO_CPU_LED		GPIO_3
+
+
+#define CPLD_BASE		0x10000000		/* t.b.m. */
+#define DEBUG_LEDS_ADDR 	CPLD_BASE + 0x01
+#define HW_ID_ADDR      	CPLD_BASE + 0x02
+#define DIP_SWITCH_ADDR 	CPLD_BASE + 0x04
+#define PHY_CTRL_ADDR   	CPLD_BASE + 0x05
+#define SPI_OUT_ADDR    	CPLD_BASE + 0x07
+#define SPI_IN_ADDR     	CPLD_BASE + 0x08
+#define MDIO_OUT_ADDR   	CPLD_BASE + 0x09
+#define MDIO_IN_ADDR    	CPLD_BASE + 0x0A
+#define MISC_OUT_ADDR   	CPLD_BASE + 0x0B
+
+/* Addresses used on I2C bus */
+#define LM75_CHIP_ADDR		0x9C
+#define LM75_CPU_ADDR		0x9E
+#define SDRAM_SPD_ADDR		0xA0
+
+#define SDRAM_SPD_WRITE_ADDRESS	(SDRAM_SPD_ADDR)
+#define SDRAM_SPD_READ_ADDRESS	(SDRAM_SPD_ADDR+1)
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c
new file mode 100755
index 0000000..ae88994
--- /dev/null
+++ b/board/exbitgen/flash.c
@@ -0,0 +1,597 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+#include <ppc4xx.h>
+#include <common.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+#ifdef MEIGSBOARD_ONBOARD_FLASH /* onboard = 2MB */
+#  ifdef CONFIG_EXBITGEN
+#     define FLASH_WORD_SIZE unsigned long
+#  endif
+#else /* Meigsboard socket flash = 512KB */
+#  ifdef CONFIG_EXBITGEN
+#    define FLASH_WORD_SIZE unsigned char
+#  endif
+#endif
+
+#ifdef CONFIG_EXBITGEN
+#define ADDR0           0x5555
+#define ADDR1           0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long bank_size;
+	unsigned long tot_size;
+	unsigned long bank_addr;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].size = 0;
+	}
+
+	tot_size = 0;
+
+	/* Detect Boot Flash */
+	bank_addr = CFG_FLASH0_BASE;
+	bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[0]);
+	if (bank_size > 0) {
+		(void)flash_protect(FLAG_PROTECT_CLEAR,
+			bank_addr,
+			bank_addr + bank_size - 1,
+			&flash_info[0]);
+	}
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Boot Flash Bank\n");
+	}
+	flash_info[0].size = bank_size;
+	tot_size += bank_size;
+
+	/* Detect Application Flash */
+	bank_addr = CFG_FLASH1_BASE;
+	for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) {
+		bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[i]);
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			break;
+		}
+		if (bank_size > 0) {
+			(void)flash_protect(FLAG_PROTECT_CLEAR,
+				bank_addr,
+				bank_addr + bank_size - 1,
+				&flash_info[i]);
+		}
+		flash_info[i].size = bank_size;
+		tot_size += bank_size;
+		bank_addr += bank_size;
+	}
+	if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Application Flash Bank\n");
+	}
+
+	/* Protect monitor and environment sectors */
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		CFG_MONITOR_BASE,
+		CFG_MONITOR_BASE + monitor_flash_len - 1,
+		&flash_info[0]);
+#if 0xfffffffc >= CFG_FLASH0_BASE
+#if 0xfffffffc <= CFG_FLASH0_BASE + CFG_FLASH0_SIZE - 1
+	flash_protect(FLAG_PROTECT_SET,
+		0xfffffffc, 0xffffffff,
+		&flash_info[0]);
+#endif
+#endif
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+	flash_protect(FLAG_PROTECT_SET,
+		CFG_ENV_ADDR,
+		CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		&flash_info[0]);
+#endif
+
+	return tot_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+				break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDLV033C:	printf ("AM29LV033C (32 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMDLV065D:	printf ("AM29LV065D (64 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST040:	printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[0];
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[1];			/* device ID		*/
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000; /* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV033C:
+		info->flash_id += FLASH_AMDLV033C;
+		info->sector_count = 64;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV065D:
+		info->flash_id += FLASH_AMDLV065D;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (FLASH_WORD_SIZE)SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (FLASH_WORD_SIZE)SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (FLASH_WORD_SIZE)SST_ID_xF040:
+		info->flash_id += FLASH_SST040;
+		info->sector_count = 128;
+		info->size = 0x00080000;
+		break;				/* => 512KB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+		(info->flash_id  == FLASH_AM040) ||
+		(info->flash_id == FLASH_AMDLV033C) ||
+		(info->flash_id == FLASH_AMDLV065D)) {
+		ulong sectsize = info->size / info->sector_count;
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sectsize);
+	} else {
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	    }
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* switch to the read mode */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+			addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (FLASH_WORD_SIZE)0x00300030;
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while ((addr2[0] & 0x00800080) !=
+				(FLASH_WORD_SIZE) 0x00800080) {
+				if ((now=get_timer(start)) >
+					   CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {  /* every second  */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
+		}
+	}
+
+	printf (" done\n");
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile ulong *)dest) & data) != data) {
+		printf("dest = %08lx, *dest = %08lx, data = %08lx\n",
+			dest, *(volatile ulong *)dest, data);
+		return 2;
+	}
+
+	for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & 0x00800080) != (data2[i] & 0x00800080)) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				addr2[0] = (FLASH_WORD_SIZE)0x00F000F0;
+				return (1);
+			}
+		}
+	}
+
+	addr2[0] = (FLASH_WORD_SIZE)0x00F000F0;
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S
new file mode 100755
index 0000000..0e6cd04
--- /dev/null
+++ b/board/exbitgen/init.S
@@ -0,0 +1,1009 @@
+/*----------------------------------------------------------------------+
+ *
+ *       This source code has been made available to you by IBM on an AS-IS
+ *       basis.  Anyone receiving this source is licensed under IBM
+ *       copyrights to use it in any way he or she deems fit, including
+ *       copying it, modifying it, compiling it, and redistributing it either
+ *       with or without modifications.  No license under IBM patents or
+ *       patent applications is to be implied by the copyright license.
+ *
+ *       Any user of this software should understand that IBM cannot provide
+ *       technical support for this software and will not be responsible for
+ *       any consequences resulting from the use of this software.
+ *
+ *       Any person who transfers this source code or any derivative work
+ *       must include the IBM copyright notice, this paragraph, and the
+ *       preceding two paragraphs in the transferred software.
+ *
+ *       COPYRIGHT   I B M   CORPORATION 1995
+ *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-----------------------------------------------------------------------
+ */
+
+#include <config.h>
+#include <ppc4xx.h>
+#include "config.h"
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+#define FPGA_BRDC       0xF0300004
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include "exbitgen.h"
+
+/* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */
+/* c-code declarations and consequently can't be included here). */
+/* (Possibly to be solved somehow else). */
+/*--------------------------------------------------------------------- */
+#define	   I2C_REGISTERS_BASE_ADDRESS 0xEF600500
+#define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
+#define    IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
+#define    IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
+#define    IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
+#define    IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
+#define    IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
+#define    IIC_STS	(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
+#define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
+#define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
+#define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
+#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
+#define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
+#define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
+#define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
+
+/* MDCNTL Register Bit definition */
+#define    IIC_MDCNTL_HSCL 0x01
+#define    IIC_MDCNTL_EUBS 0x02
+#define    IIC_MDCNTL_FMDB 0x40
+#define    IIC_MDCNTL_FSDB 0x80
+
+/* CNTL Register Bit definition */
+#define    IIC_CNTL_PT     0x01
+#define    IIC_CNTL_READ   0x02
+#define    IIC_CNTL_CHT    0x04
+
+/* STS Register Bit definition */
+#define    IIC_STS_PT	   0X01
+#define    IIC_STS_ERR	   0X04
+#define    IIC_STS_MDBS    0X20
+
+/* EXTSTS Register Bit definition */
+#define    IIC_EXTSTS_XFRA 0X01
+#define    IIC_EXTSTS_ICT  0X02
+#define    IIC_EXTSTS_LA   0X04
+
+/* LED codes used for inditing progress and errors during read of DIMM SPD.  */
+/*--------------------------------------------------------------------- */
+#define LED_SDRAM_CODE_1  0xef
+#define LED_SDRAM_CODE_2  0xee
+#define LED_SDRAM_CODE_3  0xed
+#define LED_SDRAM_CODE_4  0xec
+#define LED_SDRAM_CODE_5  0xeb
+#define LED_SDRAM_CODE_6  0xea
+#define LED_SDRAM_CODE_7  0xe9
+#define LED_SDRAM_CODE_8  0xe8
+#define LED_SDRAM_CODE_9  0xe7
+#define LED_SDRAM_CODE_10 0xe6
+#define LED_SDRAM_CODE_11 0xe5
+#define LED_SDRAM_CODE_12 0xe4
+#define LED_SDRAM_CODE_13 0xe3
+#define LED_SDRAM_CODE_14 0xe2
+#define LED_SDRAM_CODE_15 0xe1
+#define LED_SDRAM_CODE_16 0xe0
+
+
+#define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100
+
+#define FLASH_8bit_AP   0x9B015480
+#define FLASH_8bit_CR   0xFFF18000 /* 1MB(min), 8bit, R/W */
+
+#define FLASH_32bit_AP  0x9B015480
+#define FLASH_32bit_CR  0xFFE3C000 /* 2MB, 32bit, R/W */
+
+
+#define WDCR_EBC(reg,val) addi    r4,0,reg;\
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
+
+/*---------------------------------------------------------------------
+ * Function:     ext_bus_cntlr_init
+ * Description:  Initializes the External Bus Controller for the external
+ *		peripherals. IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *	Bank 0 - Boot flash
+ *	Bank 1-4 - application flash
+ *	Bank 5 - CPLD
+ *	Bank 6 - not used
+ *	Bank 7 - Heathrow chip
+ *---------------------------------------------------------------------
+ */
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	mflr    r4                      /* save link register */
+	bl      ..getAddr
+..getAddr:
+	mflr    r3                      /* get address of ..getAddr */
+	mtlr    r4                      /* restore link register */
+	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+	mtctr   r4                      /* 10 cache lines to fit this function */
+					/* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+	addi    r3,r3,32		/* move to next cache line */
+	bdnz    ..ebcloop               /* continue for 10 cache lines */
+
+	mflr	r31			/* save link register */
+
+	/*-----------------------------------------------------------
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *-----------------------------------------------------------
+	 */
+
+	addis	r3,0,0x0
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
+..spinlp:
+	bdnz    ..spinlp                /* spin loop */
+
+	/*---------------------------------------------------------------
+	 * Memory Bank 0 (Boot Flash) initialization
+	 *---------------------------------------------------------------
+	 */
+	WDCR_EBC(pb0ap, FLASH_32bit_AP)
+	WDCR_EBC(pb0cr, 0xffe38000)
+/*pnc	WDCR_EBC(pb0cr, FLASH_32bit_CR) */
+
+	/*---------------------------------------------------------------
+	 * Memory Bank 5 (CPLD) initialization
+	 *---------------------------------------------------------------
+	 */
+	WDCR_EBC(pb5ap, 0x01010040)
+/*jsa recommendation:		WDCR_EBC(pb5ap, 0x00010040) */
+	WDCR_EBC(pb5cr, 0x10038000)
+
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 6 (not used) initialization */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb6cr, 0x00000000)
+
+	/* Read HW ID to determine whether old H2 board or new generic CPU board */
+	addis	r3, 0,  HW_ID_ADDR@h
+	ori	r3, r3, HW_ID_ADDR@l
+	lbz     r3,0x0000(r3)
+	cmpi	0, r3, 1          /* if (HW_ID==1) */
+	beq 	setup_h2evalboard /* then jump */
+	cmpi	0, r3, 2          /* if (HW_ID==2) */
+	beq 	setup_genieboard  /* then jump */
+	cmpi	0, r3, 3          /* if (HW_ID==3) */
+	beq 	setup_genieboard  /* then jump */
+
+setup_genieboard:
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 1 (Application Flash) initialization for generic CPU board */
+	/*--------------------------------------------------------------- */
+/*	WDCR_EBC(pb1ap, 0x7b015480)	/###* T.B.M. */
+/*	WDCR_EBC(pb1ap, 0x7F8FFE80)	/###* T.B.M. */
+	WDCR_EBC(pb1ap, 0x9b015480)	/* hlb-20020207: burst 8 bit 6 cycles  */
+
+/*	WDCR_EBC(pb1cr, 0x20098000)	/###* 16 MB */
+	WDCR_EBC(pb1cr, 0x200B8000)	/* 32 MB */
+
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb4ap, 0x01010000)	/*  */
+	WDCR_EBC(pb4cr, 0x1021c000)	/*  */
+
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 7 (Heathrow chip on Reference board) initialization */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb7ap, 0x200ffe80)	/* No Ready, many wait states (let reflections die out) */
+	WDCR_EBC(pb7cr, 0X4001A000)
+
+	bl	setup_continue
+
+
+setup_h2evalboard:
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 1 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb1ap, 0x7b015480)	/* T.B.M. */
+/*3010	WDCR_EBC(pb1ap, 0x7F8FFE80)	/###* T.B.M. */
+	WDCR_EBC(pb1cr, 0x20058000)
+
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 2 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb2ap, 0x7b015480)	/* T.B.M. */
+/*3010	WDCR_EBC(pb2ap, 0x7F8FFE80)	/###* T.B.M. */
+	WDCR_EBC(pb2cr, 0x20458000)
+
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 3 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb3ap, 0x7b015480)	/* T.B.M. */
+/*3010	WDCR_EBC(pb3ap, 0x7F8FFE80)	/###* T.B.M. */
+	WDCR_EBC(pb3cr, 0x20858000)
+
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 4 (Application Flash) initialization */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb4ap, 0x7b015480)	/* T.B.M. */
+/*3010	WDCR_EBC(pb4ap, 0x7F8FFE80)	/###* T.B.M. */
+	WDCR_EBC(pb4cr, 0x20C58000)
+
+	/*--------------------------------------------------------------- */
+	/* Memory Bank 7 (Heathrow chip) initialization */
+	/*--------------------------------------------------------------- */
+	WDCR_EBC(pb7ap, 0x02000280)	/* No Ready, 4 wait states */
+	WDCR_EBC(pb7cr, 0X4001A000)
+
+setup_continue:
+
+
+	mtlr    r31                     /* restore lr	 */
+	nop				/* pass2 DCR errata #8 */
+	blr
+
+/*--------------------------------------------------------------------- */
+/* Function:     sdram_init */
+/* Description:  Configures SDRAM memory banks. */
+/*--------------------------------------------------------------------- */
+	.globl  sdram_init
+
+sdram_init:
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+	blr
+#else
+	mflr	r31
+
+	/* output SDRAM code  on LEDs */
+	addi	r4, 0, LED_SDRAM_CODE_1
+	addis	r5, 0, 0x1000
+	ori	r5, r5, 0x0001
+	stb	r4,0(r5)
+	eieio
+
+	/* Read contents of spd */
+	/*--------------------- */
+	bl	read_spd
+
+	/*----------------------------------------------------------- */
+	/* */
+	/* */
+	/* Update SDRAM timing register */
+	/* */
+	/* */
+	/*----------------------------------------------------------- */
+
+	/* Read  PLL feedback divider and calculate clock period of local bus in */
+	/* granularity of 10 ps. Save clock period in r30 */
+	/*-------------------------------------------------------------- */
+	mfdcr	r4, pllmd
+	addi	r9, 0, 25
+	srw	r4, r4, r9
+	andi.	r4, r4, 0x07
+	addis	r5, 0,  TIMEBASE_10PS@h
+	ori	r5, r5, TIMEBASE_10PS@l
+	divwu	r30, r5, r4
+
+	/* Determine CASL */
+	/*--------------- */
+	bl	find_casl	/* Returns CASL in r3 */
+
+	/* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */
+	/* (trp read from byte 27 in granularity of 1 ns) */
+	/*------------------------------------------------ */
+	mulli	r16, r16, 100
+	add	r16, r16, r30
+	addi	r6, 0, 1
+	subf	r16, r6, r16
+	divwu	r16, r16, r30
+
+	/* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */
+	/* (trcd read from byte 29 in granularity of 1 ns) */
+	/*--------------------------------------------------- */
+	mulli	r17, r17, 100
+	add	r17, r17, r30
+	addi	r6, 0, 1
+	subf	r17, r6, r17
+	divwu	r17, r17, r30
+
+	/* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */
+	/* (tras read from byte 30 in granularity of 1 ns) */
+	/*--------------------------------------------------- */
+	mulli	r18, r18, 100
+	add	r18, r18, r30
+	addi	r6, 0, 1
+	subf	r18, r6, r18
+	divwu	r18, r18, r30
+
+	/* Calc trc_clocks = trp_clocks + tras_clocks */
+	/*------------------------------------------- */
+	add	r18, r18, r16
+
+	/* CASL value */
+	/*----------- */
+	addi	r9, 0, 23
+	slw	r4, r3, r9
+
+	/* PTA = trp_clocks - 1 */
+	/*--------------------- */
+	addi	r6, 0, 1
+	subf	r5, r6, r16
+	addi	r9, 0, 18
+	slw	r5, r5, r9
+	or	r4, r4, r5
+
+	/* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */
+	/*------------------------------------------------ */
+	addi	r5, r18, 0
+	subf	r5, r16, r5
+	subf	r5, r17, r5
+	addi	r6, 0, 1
+	subf	r5, r6, r5
+	addi	r9, 0, 16
+	slw	r5, r5, r9
+	or	r4, r4, r5
+
+	/* LDF = 1 */
+	/*-------- */
+	ori	r4, r4, 0x4000
+
+	/* RFTA = trc_clocks - 4 */
+	/*---------------------- */
+	addi	r6, 0, 4
+	subf	r5, r6, r18
+	addi	r9, 0, 2
+	slw	r5, r5, r9
+	or	r4, r4, r5
+
+	/* RCD = trcd_clocks - 1 */
+	/*---------------------- */
+	addi	r6, 0, 1
+	subf	r5, r6, r17
+	or	r4, r4, r5
+
+	/*----------------------------------------------------------- */
+	/* Set SDTR1  */
+	/*----------------------------------------------------------- */
+	addi    r5,0,mem_sdtr1
+	mtdcr   memcfga,r5
+	mtdcr   memcfgd,r4
+
+	/*----------------------------------------------------------- */
+	/* */
+	/* */
+	/* Update memory bank 0-3 configuration registers */
+	/* */
+	/* */
+	/*----------------------------------------------------------- */
+
+	/* Build contents of configuration register for bank 0 into r6 */
+	/*------------------------------------------------------------ */
+	bl	find_mode	/* returns addressing mode in r3 */
+	addi	r29, r3, 0	/* save mode temporarily in r29 */
+	bl	find_size_code	/* returns size code in r3 */
+	addi	r9, 0, 17	/* bit offset of size code in configuration register */
+	slw	r3, r3, r9	/* */
+	addi	r9, 0, 13	/* bit offset of addressing mode in configuration register  */
+	slw	r29, r29, r9	/*  */
+	or	r3, r29, r3	/* merge size code and addressing mode */
+	ori	r6, r3, CFG_SDRAM_BASE + 1 /* insert base address and enable bank */
+
+	/* Calculate banksize r15 = (density << 22) / 2 */
+	/*--------------------------------------------- */
+	addi	r9, 0, 21
+	slw	r15, r15, r9
+
+	/* Set SDRAM bank 0 register and adjust r6 for next bank */
+	/*------------------------------------------------------ */
+	addi    r7,0,mem_mb0cf
+	mtdcr   memcfga,r7
+	mtdcr   memcfgd,r6
+
+	add	r6, r6, r15	/* add bank size to base address for next bank */
+
+	/* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */
+	/*---------------------------------------------------------------------------- */
+	cmpi	0, r12, 2
+	bne	b1skip
+
+	addi    r7,0,mem_mb1cf
+	mtdcr   memcfga,r7
+	mtdcr   memcfgd,r6
+
+	add	r6, r6, r15	/* add bank size to base address for next bank */
+
+	/* Set SDRAM bank 2 register and adjust r6 for next bank */
+	/*------------------------------------------------------ */
+b1skip:	addi    r7,0,mem_mb2cf
+	mtdcr   memcfga,r7
+	mtdcr   memcfgd,r6
+
+	add	r6, r6, r15	/* add bank size to base address for next bank */
+
+	/* If two rows/banks then set SDRAM bank 3 register */
+	/*------------------------------------------------ */
+	cmpi	0, r12, 2
+	bne	b3skip
+
+	addi    r7,0,mem_mb3cf
+	mtdcr   memcfga,r7
+	mtdcr   memcfgd,r6
+b3skip:
+
+	/*----------------------------------------------------------- */
+	/* Set RTR */
+	/*----------------------------------------------------------- */
+	cmpi	0, r30, 1600
+	bge	rtr_1
+	addis   r7, 0, 0x05F0	/* RTR value for 100Mhz */
+	bl	rtr_2
+rtr_1:	addis	r7, 0, 0x03F8
+rtr_2:	addi    r4,0,mem_rtr
+	mtdcr   memcfga,r4
+	mtdcr   memcfgd,r7
+
+	/*----------------------------------------------------------- */
+	/* Delay to ensure 200usec have elapsed since reset. Assume worst */
+	/* case that the core is running 200Mhz: */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*----------------------------------------------------------- */
+	addis   r3,0,0x0000
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2               /* spin loop */
+
+	/*----------------------------------------------------------- */
+	/* Set memory controller options reg, MCOPT1. */
+	/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst  */
+	/* read/prefetch. */
+	/*----------------------------------------------------------- */
+	addi    r4,0,mem_mcopt1
+	mtdcr   memcfga,r4
+	addis   r4,0,0x80C0             /* set DC_EN=1 */
+	ori     r4,r4,0x0000
+	mtdcr   memcfgd,r4
+
+
+	/*----------------------------------------------------------- */
+	/* Delay to ensure 10msec have elapsed since reset. This is */
+	/* required for the MPC952 to stabalize. Assume worst */
+	/* case that the core is running 200Mhz: */
+	/*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
+	/* This delay should occur before accessing SDRAM. */
+	/*----------------------------------------------------------- */
+	addis   r3,0,0x001E
+	ori     r3,r3,0x8480          /* ensure 10msec have passed since reset */
+	mtctr   r3
+..spinlp3:
+	bdnz    ..spinlp3                /* spin loop */
+
+	/* output SDRAM code  on LEDs */
+	addi	r4, 0, LED_SDRAM_CODE_16
+	addis	r5, 0, 0x1000
+	ori	r5, r5, 0x0001
+	stb	r4,0(r5)
+	eieio
+
+	mtlr    r31                     /* restore lr */
+	blr
+
+/*--------------------------------------------------------------------- */
+/* Function:    read_spd */
+/* Description: Reads contents of SPD and saves parameters to be used for */
+/*		configuration in dedicated registers (see code below). */
+/*---------------------------------------------------------------------	 */
+
+#define WRITE_I2C(reg,val) \
+	addi    r3,0,val;\
+	addis   r4, 0, 0xef60;\
+	ori     r4, r4, 0x0500 + reg;\
+	stb     r3, 0(r4);\
+	eieio
+
+#define READ_I2C(reg) \
+	addis   r3, 0, 0xef60;\
+	ori     r3, r3, 0x0500 + reg;\
+	lbz     r3, 0x0000(r3);\
+	eieio
+
+read_spd:
+
+	mflr	r5
+
+	/* Initialize i2c */
+	/*--------------- */
+	WRITE_I2C(IICLMADR, 0x00)	/* clear lo master address */
+	WRITE_I2C(IICHMADR, 0x00)	/* clear hi master address */
+	WRITE_I2C(IICLSADR, 0x00)	/* clear lo slave address */
+	WRITE_I2C(IICHSADR, 0x00)	/* clear hi slave address */
+	WRITE_I2C(IICSTS, 0x08)		/* update status register */
+	WRITE_I2C(IICEXTSTS, 0x8f)
+	WRITE_I2C(IICCLKDIV, 0x05)
+	WRITE_I2C(IICINTRMSK, 0x00)	/* no interrupts */
+	WRITE_I2C(IICXFRCNT, 0x00)	/* clear transfer count */
+	WRITE_I2C(IICXTCNTLSS, 0xf0)	/* clear extended control & stat */
+	WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB)	/* mode control */
+	READ_I2C(IICMDCNTL)
+	ori	r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL
+	WRITE_I2C(IICMDCNTL, r3)	/* mode control */
+	WRITE_I2C(IICCNTL, 0x00)	/* clear control reg */
+
+	/* Wait until initialization completed */
+	/*------------------------------------ */
+	bl	wait_i2c_transfer_done
+
+	WRITE_I2C(IICHMADR, 0x00)	/* 7-bit addressing */
+	WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS)
+
+	/* Write 0 into buffer(start address) */
+	/*----------------------------------- */
+	WRITE_I2C(IICMDBUF, 0x00);
+
+	/* Wait a little */
+	/*-------------- */
+	addis   r3,0,0x0000
+	ori     r3,r3,0xA000
+	mtctr   r3
+in02:	bdnz    in02
+
+	/* Issue write command */
+	/*-------------------- */
+	WRITE_I2C(IICCNTL, IIC_CNTL_PT)
+	bl	wait_i2c_transfer_done
+
+	/* Read 128 bytes */
+	/*--------------- */
+	addi	r7, 0, 0	/* byte counter in r7 */
+	addi	r8, 0, 0	/* checksum in r8 */
+rdlp:
+	/* issue read command */
+	/*------------------- */
+	cmpi	0, r7, 127
+	blt	rd01
+	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT)
+	bl	rd02
+rd01:	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT)
+rd02:	bl	wait_i2c_transfer_done
+
+	/* Fetch byte from buffer */
+	/*----------------------- */
+	READ_I2C(IICMDBUF)
+
+	/* Retrieve parameters that are going to be used during configuration. */
+	/* Save them in dedicated registers. */
+	/*------------------------------------------------------------ */
+	cmpi	0, r7, 3	/* Save byte 3 in r10 */
+	bne	rd10
+	addi	r10, r3, 0
+rd10:	cmpi	0, r7, 4	/* Save byte 4 in r11 */
+	bne	rd11
+	addi	r11, r3, 0
+rd11:	cmpi	0, r7, 5	/* Save byte 5 in r12 */
+	bne	rd12
+	addi	r12, r3, 0
+rd12:	cmpi	0, r7, 17	/* Save byte 17 in r13 */
+	bne	rd13
+	addi	r13, r3, 0
+rd13:	cmpi	0, r7, 18	/* Save byte 18 in r14 */
+	bne	rd14
+	addi	r14, r3, 0
+rd14:	cmpi	0, r7, 31	/* Save byte 31 in r15 */
+	bne	rd15
+	addi	r15, r3, 0
+rd15:	cmpi	0, r7, 27	/* Save byte 27 in r16 */
+	bne	rd16
+	addi	r16, r3, 0
+rd16:	cmpi	0, r7, 29	/* Save byte 29 in r17 */
+	bne	rd17
+	addi	r17, r3, 0
+rd17:	cmpi	0, r7, 30	/* Save byte 30 in r18 */
+	bne	rd18
+	addi	r18, r3, 0
+rd18:	cmpi	0, r7, 9	/* Save byte 9 in r19 */
+	bne	rd19
+	addi	r19, r3, 0
+rd19:	cmpi	0, r7, 23	/* Save byte 23 in r20 */
+	bne	rd20
+	addi	r20, r3, 0
+rd20:	cmpi	0, r7, 25	/* Save byte 25 in r21 */
+	bne	rd21
+	addi	r21, r3, 0
+rd21:
+
+	/* Calculate checksum of the first 63 bytes */
+	/*----------------------------------------- */
+	cmpi	0, r7, 63
+	bgt	rd31
+	beq	rd30
+	add	r8, r8, r3
+	bl	rd31
+
+	/* Verify checksum at byte 63 */
+	/*--------------------------- */
+rd30:	andi.	r8, r8, 0xff		/* use only 8 bits */
+	cmp	0, r8, r3
+	beq	rd31
+	addi	r4, 0, LED_SDRAM_CODE_8
+	addis	r5, 0, 0x1000
+	ori	r5, r5, 0x0001
+	stb	r4,0(r5)
+	eieio
+rderr:	bl	rderr
+
+rd31:
+
+	/* Increment byte counter and check whether all bytes have been read. */
+	/*------------------------------------------------------------------- */
+	addi	r7, r7, 1
+	cmpi	0, r7, 127
+	bgt	rd05
+	bl	rdlp
+rd05:
+	mtlr    r5                     /* restore lr */
+	blr
+
+wait_i2c_transfer_done:
+	mflr	r6
+wt01:	READ_I2C(IICSTS)
+	andi.	r4, r3, IIC_STS_PT
+	cmpi	0, r4, IIC_STS_PT
+	beq	wt01
+	mtlr    r6                     /* restore lr */
+	blr
+
+/*--------------------------------------------------------------------- */
+/* Function:    find_mode */
+/* Description: Determines addressing mode to be used dependent on   */
+/*		number of rows (r10 = byte 3 from SPD), number of columns (r11 = */
+/*		byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */
+/*		mode is returned in r3. */
+/* (It would be nicer having a table, pnc). */
+/*---------------------------------------------------------------------	 */
+find_mode:
+
+	mflr	r5
+
+	cmpi	0, r10, 11
+	bne	fm01
+	cmpi	0, r11, 9
+	bne	fm01
+	cmpi	0, r13, 2
+	bne	fm01
+	addi	r3, 0, 1
+	bl	fmfound
+
+fm01:	cmpi	0, r10, 11
+	bne	fm02
+	cmpi	0, r11, 10
+	bne	fm02
+	cmpi	0, r13, 2
+	bne	fm02
+	addi	r3, 0, 1
+	bl	fmfound
+
+fm02:	cmpi	0, r10, 12
+	bne	fm03
+	cmpi	0, r11, 9
+	bne	fm03
+	cmpi	0, r13, 4
+	bne	fm03
+	addi	r3, 0, 2
+	bl	fmfound
+
+fm03:	cmpi	0, r10, 12
+	bne	fm04
+	cmpi	0, r11, 10
+	bne	fm04
+	cmpi	0, r13, 4
+	bne	fm04
+	addi	r3, 0, 2
+	bl	fmfound
+
+fm04:	cmpi	0, r10, 13
+	bne	fm05
+	cmpi	0, r11, 9
+	bne	fm05
+	cmpi	0, r13, 4
+	bne	fm05
+	addi	r3, 0, 3
+	bl	fmfound
+
+fm05:	cmpi	0, r10, 13
+	bne	fm06
+	cmpi	0, r11, 10
+	bne	fm06
+	cmpi	0, r13, 4
+	bne	fm06
+	addi	r3, 0, 3
+	bl	fmfound
+
+fm06:	cmpi	0, r10, 13
+	bne	fm07
+	cmpi	0, r11, 11
+	bne	fm07
+	cmpi	0, r13, 4
+	bne	fm07
+	addi	r3, 0, 3
+	bl	fmfound
+
+fm07:	cmpi	0, r10, 12
+	bne	fm08
+	cmpi	0, r11, 8
+	bne	fm08
+	cmpi	0, r13, 2
+	bne	fm08
+	addi	r3, 0, 4
+	bl	fmfound
+
+fm08:	cmpi	0, r10, 12
+	bne	fm09
+	cmpi	0, r11, 8
+	bne	fm09
+	cmpi	0, r13, 4
+	bne	fm09
+	addi	r3, 0, 4
+	bl	fmfound
+
+fm09:	cmpi	0, r10, 11
+	bne	fm10
+	cmpi	0, r11, 8
+	bne	fm10
+	cmpi	0, r13, 2
+	bne	fm10
+	addi	r3, 0, 5
+	bl	fmfound
+
+fm10:	cmpi	0, r10, 11
+	bne	fm11
+	cmpi	0, r11, 8
+	bne	fm11
+	cmpi	0, r13, 4
+	bne	fm11
+	addi	r3, 0, 5
+	bl	fmfound
+
+fm11:	cmpi	0, r10, 13
+	bne	fm12
+	cmpi	0, r11, 8
+	bne	fm12
+	cmpi	0, r13, 2
+	bne	fm12
+	addi	r3, 0, 6
+	bl	fmfound
+
+fm12:	cmpi	0, r10, 13
+	bne	fm13
+	cmpi	0, r11, 8
+	bne	fm13
+	cmpi	0, r13, 4
+	bne	fm13
+	addi	r3, 0, 6
+	bl	fmfound
+
+fm13:	cmpi	0, r10, 13
+	bne	fm14
+	cmpi	0, r11, 9
+	bne	fm14
+	cmpi	0, r13, 2
+	bne	fm14
+	addi	r3, 0, 7
+	bl	fmfound
+
+fm14:	cmpi	0, r10, 13
+	bne	fm15
+	cmpi	0, r11, 10
+	bne	fm15
+	cmpi	0, r13, 2
+	bne	fm15
+	addi	r3, 0, 7
+	bl	fmfound
+
+fm15:
+	/* not found, error code to be issued on LEDs */
+	addi	r7, 0, LED_SDRAM_CODE_2
+	addis	r6, 0, 0x1000
+	ori	r6, r6, 0x0001
+	stb	r7,0(r6)
+	eieio
+fmerr:	bl	fmerr
+
+fmfound:addi	r6, 0, 1
+	subf	r3, r6, r3
+
+	mtlr    r5                     /* restore lr */
+	blr
+
+/*--------------------------------------------------------------------- */
+/* Function:    find_size_code */
+/* Description: Determines size code to be used in configuring SDRAM controller */
+/*		dependent on density (r15 = byte 31 from SPD) */
+/*--------------------------------------------------------------------- */
+find_size_code:
+
+	mflr	r5
+
+	addi	r3, r15, 0	/* density */
+	addi	r7, 0, 0
+fs01:	andi.	r6, r3, 0x01
+	cmpi	0, r6, 1
+	beq	fs04
+
+	addi	r7, r7, 1
+	cmpi	0, r7, 7
+	bge	fs02
+	addi	r9, 0, 1
+	srw	r3, r3, r9
+	bl	fs01
+
+	/* not found, error code to be issued on LEDs */
+fs02:	addi	r4, 0, LED_SDRAM_CODE_3
+	addis	r8, 0, 0x1000
+	ori	r8, r8, 0x0001
+	stb	r4,0(r8)
+	eieio
+fs03:	bl	fs03
+
+fs04:	addi	r3, r7, 0
+	cmpi	0, r3, 0
+	beq	fs05
+	addi	r6, 0, 1
+	subf	r3, r6, r3
+fs05:
+	mtlr    r5                     /* restore lr */
+	blr
+
+/*--------------------------------------------------------------------- */
+/* Function:    find_casl */
+/* Description: Determines CAS latency */
+/*--------------------------------------------------------------------- */
+find_casl:
+
+	mflr	r5
+
+	andi.	r14, r14, 0x7f	/* r14 holds supported CAS latencies */
+	addi	r3, 0, 0xff	/* preset determined CASL */
+	addi	r4, 0, 6	/* Start at bit 6 of supported CAS latencies */
+	addi	r2, 0, 0	/* Start finding highest CAS latency */
+
+fc01:	srw	r6, r14, r4	/*  */
+	andi.	r6, r6, 0x01	/*  */
+	cmpi	0, r6, 1	/* Check bit for current latency */
+	bne	fc06		/* If not supported, go to next */
+
+	cmpi	0, r2, 2	/* Check if third-highest latency */
+	bge	fc04		/* If so, go calculate with another format */
+
+	cmpi	0, r2, 0	/* Check if highest latency */
+	bgt	fc02		/* */
+	addi	r7, r19, 0	/* SDRAM cycle time for highest CAS latenty */
+
+	bl	fc03
+fc02:
+	addi	r7, r20, 0	/* SDRAM cycle time for next-highest CAS latenty */
+fc03:
+	addi	r8, r7, 0
+	addi	r9, 0, 4
+	srw	r7, r7, r9
+	andi.	r7, r7, 0x0f
+	mulli	r7, r7, 100
+	andi.	r8, r8, 0x0f
+	mulli	r8, r8, 10
+	add	r7, r7, r8
+	cmp	0, r7, r30
+	bgt	fc05
+	addi	r3, r2, 0
+	bl	fc05
+fc04:
+	addi	r7, r21, 0	/* SDRAM cycle time for third-highest CAS latenty */
+	addi	r8, r7, 0
+	addi	r9, 0, 2
+	srw	r7, r7, r9
+	andi.	r7, r7, 0x3f
+	mulli	r7, r7, 100
+	andi.	r8, r8, 0x03
+	mulli	r8, r8, 25
+	add	r7, r7, r8
+
+	cmp	0, r7, r30
+	bgt	fc05
+	addi	r3, r2, 0
+
+fc05:	addi	r2, r2, 1	/* next latency */
+	cmpi	0, r2, 3
+	bge	fc07
+fc06:	addi	r6, 0, 1
+	subf	r4, r6, r4
+	cmpi	0, r4, 0
+	bne	fc01
+
+fc07:
+
+	mtlr    r5		/* restore lr */
+	blr
+#endif
+
+
+/*  Peripheral Bank 1 Access Parameters */
+/*     0	BME = 1	; burstmode enabled */
+/*    " 1:8"	TWT=00110110	;Transfer wait (details below) */
+/*     1:5	FWT=00110	; first wait = 6 cycles */
+/*     6:8	BWT=110	; burst wait = 6 cycles */
+/*     9:11	000	; reserved */
+/*     12:13	CSN=00	; chip select on timing = 0 */
+/*     14:15	OEN=01	; output enable  */
+/*     16:17	WBN=01	; write byte enable on timing 1 cycle */
+/*     18:19	WBF=01	; write byte enable off timing 1 cycle */
+/*     20:22	TH=010	; transfer hold = 2 cycles */
+/*     23	RE=0	; ready enable = disabled */
+/*     24	SOR=1	; sample on ready = same PerClk */
+/*     25	BEM=0	; byte enable mode = only for write cycles */
+/*     26	PEN=0	; parity enable = disable */
+/*     27:31	00000	;reserved */
+/* */
+/* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */
+/* */
+/* */
+/*	Code for BDI probe: */
+/* */
+/* WDCR    18      0x00000011      ;Select PB1AP */
+/* WDCR    19      0x1b015480      ;PB1AP: Flash */
+/* */
+/* Peripheral Bank 0 Access Parameters */
+/* 0:11	BAS=0x200	; base address select = 0x200 * 0x100000 (1MB) =  */
+/* 12:14	BS=100	; bank size =  16MB (100) / 32MB (101) */
+/* 15:16	BU=11	; bank usage = read/write */
+/* 17:18	BW=00	; bus width = 8-bit */
+/* 19:31		; reserved */
+/* */
+/* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */
+/* WDCR    18      0x00000001      ;Select PB1CR */
+/* WDCR    19      0x20098000      ;PB1CR: 1MB at 0x00100000, r/w, 8bit */
+
+/* For CPLD */
+/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */
+/*	WDCR_EBC(pb5ap, 0x01010040) */
+/*jsa recommendation:		WDCR_EBC(pb5ap, 0x00010040) */
+/*	WDCR_EBC(pb5cr, 0X10018000) */
+/* Access parms */
+/*   100   3      8          0    0    0 */
+/* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */
+/* Address :	0x10000000 */
+/* Size:	2 MB */
+/* Usage:	read/write */
+/* Width:	32 bit */
+
+/* For Genie onboard fpga 32 bit interface */
+/* 0      1      0         1         0         0         0            0 */
+/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */
+/* 0x01010000 */
+/* Access parms */
+/*   102   1      c          0    0    0 */
+/* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */
+/* Address :	0x10200000 */
+/* Size:	2 MB */
+/* Usage:	read/write */
+/* Width:	32 bit */
+
+/* Walnut fpga pb7ap */
+/* 0      1      8         1         5         2         8            0 */
+/* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */
+/* Walnut fpga pb7cr */
+/* 0xF0318000 */
+/*  */
diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds
new file mode 100755
index 0000000..d5dea82
--- /dev/null
+++ b/board/exbitgen/u-boot.lds
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/exbitgen/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+  . = ALIGN(4);
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/fads/Makefile b/board/fads/Makefile
new file mode 100755
index 0000000..baa6c2e
--- /dev/null
+++ b/board/fads/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o lamp.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/fads/config.mk b/board/fads/config.mk
new file mode 100755
index 0000000..621b9a2
--- /dev/null
+++ b/board/fads/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
+# MPC885ADS boards
+#
+
+TEXT_BASE = 0xFE000000
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/fads
+HOST_CFLAGS += -I$(TOPDIR)/board/fads
+HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/fads
diff --git a/board/fads/fads.c b/board/fads/fads.c
new file mode 100755
index 0000000..013b3cb
--- /dev/null
+++ b/board/fads/fads.c
@@ -0,0 +1,953 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <mpc8xx.h>
+#include <pcmcia.h>
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/* ========================================================================= */
+
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
+
+#if defined(CONFIG_DRAM_50MHZ)
+/* 50MHz tables */
+static const uint dram_60ns[] =
+{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
+  0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_,
+  0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
+  0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
+  0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
+  0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint dram_70ns[] =
+{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
+  0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
+  0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
+  0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
+  0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
+  0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint edo_60ns[] =
+{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
+  0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
+  0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
+  0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
+  0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint edo_70ns[] =
+{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
+  0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
+  0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
+  0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
+  0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
+  0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+#elif defined(CONFIG_DRAM_25MHZ)
+
+/* 25MHz tables */
+
+static const uint dram_60ns[] =
+{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint dram_70ns[] =
+{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
+  0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
+  0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint edo_60ns[] =
+{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
+  0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
+  0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+static const uint edo_70ns[] =
+{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
+  0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
+  0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
+  0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
+  0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+#else
+#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
+#endif
+
+/* ------------------------------------------------------------------------- */
+static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* init upm */
+
+	switch (delay) {
+	case 70:
+		if (edo) {
+			upmconfig (UPMA, (uint *) edo_70ns,
+				   sizeof (edo_70ns) / sizeof (uint));
+		} else {
+			upmconfig (UPMA, (uint *) dram_70ns,
+				   sizeof (dram_70ns) / sizeof (uint));
+		}
+
+		break;
+
+	case 60:
+		if (edo) {
+			upmconfig (UPMA, (uint *) edo_60ns,
+				   sizeof (edo_60ns) / sizeof (uint));
+		} else {
+			upmconfig (UPMA, (uint *) dram_60ns,
+				   sizeof (dram_60ns) / sizeof (uint));
+		}
+
+		break;
+
+	default:
+		return -1;
+	}
+
+	memctl->memc_mptpr = 0x0400;	/* divide by 16 */
+
+	switch (noMbytes) {
+	case 4:				/* 4 Mbyte uses only CS2 */
+#ifdef CONFIG_ADS
+		memctl->memc_mamr = 0xc0a21114;
+#else
+		memctl->memc_mamr = 0x13a01114;	/* PTA 0x13 AMA 010 */
+#endif
+		memctl->memc_or2 = 0xffc00800;	/* 4M */
+		break;
+
+	case 8:				/* 8 Mbyte uses both CS3 and CS2 */
+		memctl->memc_mamr = 0x13a01114;	/* PTA 0x13 AMA 010 */
+		memctl->memc_or3 = 0xffc00800;	/* 4M */
+		memctl->memc_br3 = 0x00400081 + base;
+		memctl->memc_or2 = 0xffc00800;	/* 4M */
+		break;
+
+	case 16:			/* 16 Mbyte uses only CS2 */
+#ifdef CONFIG_ADS	/* XXX: why PTA=0x60 only in 16M case? - NTL */
+		memctl->memc_mamr = 0x60b21114;	/* PTA 0x60 AMA 011 */
+#else
+		memctl->memc_mamr = 0x13b01114;	/* PTA 0x13 AMA 011 */
+#endif
+		memctl->memc_or2 = 0xff000800;	/* 16M */
+		break;
+
+	case 32:			/* 32 Mbyte uses both CS3 and CS2 */
+		memctl->memc_mamr = 0x13b01114;	/* PTA 0x13 AMA 011 */
+		memctl->memc_or3 = 0xff000800;	/* 16M */
+		memctl->memc_br3 = 0x01000081 + base;
+		memctl->memc_or2 = 0xff000800;	/* 16M */
+		break;
+
+	default:
+		return -1;
+	}
+
+	memctl->memc_br2 = 0x81 + base;	/* use upma */
+
+	*((uint *) BCSR1) &= ~BCSR1_DRAM_EN;	/* enable dram */
+
+	/* if no dimm is inserted, noMbytes is still detected as 8m, so
+	 * sanity check top and bottom of memory */
+
+	/* check bytes / 2 because get_ram_size tests at base+bytes, which
+	 * is not mapped */
+	if (noMbytes == 8)
+		if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
+			*((uint *) BCSR1) |= BCSR1_DRAM_EN;	/* disable dram */
+			return -1;
+		}
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void _dramdisable(void)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br2 = 0x00000000;
+	memctl->memc_br3 = 0x00000000;
+
+	/* maybe we should turn off upma here or something */
+}
+#endif /* !CONFIG_MPC885ADS */
+
+/* ========================================================================= */
+
+#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */
+
+#if defined(CONFIG_SDRAM_100MHZ)
+
+/* ------------------------------------------------------------------------- */
+/* sdram table by Dan Malek                                                  */
+
+/* This has the stretched early timing so the 50 MHz
+ * processor can make the 100 MHz timing.  This will
+ * work at all processor speeds.
+ */
+
+#ifdef SDRAM_ALT_INIT_SEQENCE
+# define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
+#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
+# define SDRAM_MCRVALUE0  0x80808111   /* run upmb cs4 loop 1 addr 0x11 MRS */
+# define SDRAM_MCRVALUE1  SDRAM_MCRVALUE0  /* ??? why not 0x80808130? */
+#else
+# define SDRAM_MxMR_PTx         195
+# define UPM_MRS_ADDR           0x11
+# define UPM_REFRESH_ADDR       0x30    /* or 0x11 if we want to be like above? */
+#endif /* !SDRAM_ALT_INIT_SEQUENCE */
+
+static const uint sdram_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
+	0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
+	0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
+	0x1ff77c45,
+
+	/* precharge + MRS. (offset 11 in upm RAM) */
+	0xeffbbc04, 0x1ff77c34, 0xefeabc34,
+	0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
+	0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
+	0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ };
+
+#elif defined(CONFIG_SDRAM_50MHZ)
+
+/* ------------------------------------------------------------------------- */
+/* sdram table stolen from the fads manual                                   */
+/* for chip MB811171622A-100                                                 */
+
+/* this table is for 32-50MHz operation */
+#ifdef SDRAM_ALT_INIT_SEQENCE
+# define SDRAM_MBMRVALUE0 0x80802114   /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
+# define SDRAM_MBMRVALUE1 0x80802118   /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */
+# define SDRAM_MCRVALUE0  0x80808105   /* run upmb cs4 loop 1 addr 0x5 MRS */
+# define SDRAM_MCRVALUE1  0x80808130   /* run upmb cs4 loop 1 addr 0x30 REFRESH */
+# define SDRAM_MPTRVALUE  0x400
+#define SDRAM_MARVALUE   0x88
+#else
+# define SDRAM_MxMR_PTx         128
+# define UPM_MRS_ADDR           0x5
+# define UPM_REFRESH_ADDR       0x30
+#endif  /* !SDRAM_ALT_INIT_SEQUENCE */
+
+static const uint sdram_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* precharge + MRS. (offset 5 in upm RAM) */
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+/* ------------------------------------------------------------------------- */
+#else
+#error SDRAM not correctly configured
+#endif
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+#define SDRAM_OR4VALUE   0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */
+#define SDRAM_BR4VALUE   0x000000c1 /* UPMB,base addr or'ed on later */
+
+/* ------------------------------------------------------------------------- */
+#ifdef SDRAM_ALT_INIT_SEQENCE
+/* ------------------------------------------------------------------------- */
+
+static int _initsdram(uint base, uint noMbytes)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = SDRAM_MPTPRVALUE;
+
+	/* Configure the refresh (mostly).  This needs to be
+	* based upon processor clock speed and optimized to provide
+	* the highest level of performance.  For multiple banks,
+	* this time has to be divided by the number of banks.
+	* Although it is not clear anywhere, it appears the
+	* refresh steps through the chip selects for this UPM
+	* on each refresh cycle.
+	* We have to be careful changing
+	* UPM registers after we ask it to run these commands.
+	*/
+
+	memctl->memc_mbmr = SDRAM_MBMRVALUE0;   /* TLF 4 */
+	memctl->memc_mar = SDRAM_MARVALUE;  /* MRS code */
+
+	udelay(200);
+
+	/* Now run the precharge/nop/mrs commands.
+	*/
+
+	memctl->memc_mcr = 0x80808111;   /* run umpb cs4 1 count 1, addr 0x11 ??? (50Mhz) */
+	                                 /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100Mhz) */
+	udelay(200);
+
+	/* Run 8 refresh cycles */
+
+	memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 Mhz)*/
+					    /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */
+
+	udelay(200);
+
+	memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 Mhz) or TLF 8 (50MHz) */
+	memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 Mhz) */
+					    /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */
+
+	udelay(200);
+
+	memctl->memc_mbmr = SDRAM_MBMRVALUE0;   /* TLF 4 */
+
+	memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
+	memctl->memc_br4 = SDRAM_BR4VALUE | base;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+#else  /* !SDRAM_ALT_INIT_SEQUENCE */
+/* ------------------------------------------------------------------------- */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
+# define MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
+# define MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
+# define MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
+# define MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
+
+/*
+ * MxMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTBE  |   \
+			MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
+			MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
+/* 9 column SDRAM */
+# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTAE  |   \
+			MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
+			MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
+
+static int _initsdram(uint base, uint noMbytes)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = MPTPR_2BK_4K;
+	memctl->memc_mbmr  = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */
+
+	/* map CS 4 */
+	memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
+	memctl->memc_br4 = SDRAM_BR4VALUE | base;
+
+	/* Perform SDRAM initilization */
+# ifdef UPM_NOP_ADDR    /* not currently in UPM table */
+	/* step 1: nop */
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(0) | UPM_NOP_ADDR;
+# endif
+
+	/* step 2: delay */
+	udelay(200);
+
+# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */
+	/* step 3: precharge */
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(4) | UPM_PRECHARGE_ADDR;
+# endif
+
+	/* step 4: refresh */
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(2) | UPM_REFRESH_ADDR;
+
+	/*
+	 * note: for some reason, the UPM values we are using include
+	 * precharge with MRS
+	 */
+
+	/* step 5: mrs */
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(1) | UPM_MRS_ADDR;
+
+# ifdef UPM_NOP_ADDR
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
+			   MCR_MLCF(0) | UPM_NOP_ADDR;
+# endif
+	/*
+	 * Enable refresh
+	 */
+
+	memctl->memc_mbmr |= MBMR_PTBE;
+	return 0;
+}
+#endif  /* !SDRAM_ALT_INIT_SEQUENCE */
+
+/* ------------------------------------------------------------------------- */
+
+static void _sdramdisable(void)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br4 = 0x00000000;
+
+	/* maybe we should turn off upmb here or something */
+}
+
+/* ------------------------------------------------------------------------- */
+
+static int initsdram(uint base, uint *noMbytes)
+{
+	uint m = CFG_SDRAM_SIZE>>20;
+
+	/* _initsdram needs access to sdram */
+	*((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
+
+	if(!_initsdram(base, m))
+	{
+	        *noMbytes += m;
+		return 0;
+	}
+	else
+	{
+		*((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
+
+		_sdramdisable();
+
+		return -1;
+	}
+}
+
+#endif /* CONFIG_FADS */
+
+/* ========================================================================= */
+
+long int initdram (int board_type)
+{
+	uint sdramsz = 0;	/* size of sdram in Mbytes */
+	uint base = 0;		/* base of dram in bytes */
+	uint m = 0;		/* size of dram in Mbytes */
+#ifndef CONFIG_MPC885ADS
+	uint k, s;
+#endif
+
+#ifdef CONFIG_FADS
+	if (!initsdram (0x00000000, &sdramsz)) {
+		base = sdramsz << 20;
+		printf ("(%u MB SDRAM) ", sdramsz);
+	}
+#endif
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
+	k = (*((uint *) BCSR2) >> 23) & 0x0f;
+
+	switch (k & 0x3) {
+		/* "MCM36100 / MT8D132X" */
+	case 0x00:
+		m = 4;
+		break;
+
+		/* "MCM36800 / MT16D832X" */
+	case 0x01:
+		m = 32;
+		break;
+		/* "MCM36400 / MT8D432X" */
+	case 0x02:
+		m = 16;
+		break;
+		/* "MCM36200 / MT16D832X ?" */
+	case 0x03:
+		m = 8;
+		break;
+
+	}
+
+	switch (k >> 2) {
+	case 0x02:
+		k = 70;
+		break;
+
+	case 0x03:
+		k = 60;
+		break;
+
+	default:
+		printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
+		k = 70;
+	}
+
+#ifdef CONFIG_FADS
+	/* the FADS is missing this bit, all rams treated as non-edo */
+	s = 0;
+#else
+	s = (*((uint *) BCSR2) >> 27) & 0x01;
+#endif
+
+	if (!_draminit (base, m, s, k)) {
+		printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : "");
+	} else {
+		_dramdisable ();
+		m = 0;
+	}
+#endif /* !CONFIG_MPC885ADS */
+	m += sdramsz;				/* add sdram size to total */
+
+	return (m << 20);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+    /* TODO: XXX XXX XXX */
+    printf ("test: 16 MB - ok\n");
+
+    return (0);
+}
+
+/* ========================================================================= */
+
+/*
+ * Check Board Identity:
+ */
+
+#if defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD)
+static void checkdboard(void)
+{
+	/* get db type from BCSR 3 */
+	uint k = (*((uint *)BCSR3) >> 24) & 0x3f;
+
+	puts (" with db ");
+
+	switch(k) {
+	case 0x03 :
+		puts ("MPC823");
+		break;
+	case 0x20 :
+		puts ("MPC801");
+		break;
+	case 0x21 :
+		puts ("MPC850");
+		break;
+	case 0x22 :
+		puts ("MPC821, MPC860 / MPC860SAR / MPC860T");
+		break;
+	case 0x23 :
+		puts ("MPC860SAR");
+		break;
+	case 0x24 :
+	case 0x2A :
+		puts ("MPC860T");
+		break;
+	case 0x3F :
+		puts ("MPC850SAR");
+		break;
+	default : printf("0x%x", k);
+	}
+}
+#endif	/* defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) */
+
+int checkboard (void)
+{
+	/* get revision from BCSR 3 */
+	uint r =  (((*((uint *) BCSR3) >> 23) & 1) << 3)
+		| (((*((uint *) BCSR3) >> 19) & 1) << 2)
+		| (((*((uint *) BCSR3) >> 16) & 3));
+
+	puts ("Board: ");
+
+#if defined(CONFIG_MPC86xADS)
+	puts ("MPC86xADS");
+#elif defined(CONFIG_MPC885ADS)
+	puts ("MPC885ADS");
+	r = 0; /* I've got NR (No Revision) board */
+#elif defined(CONFIG_FADS)
+	puts ("FADS");
+	checkdboard ();
+#else
+	puts ("ADS");
+#endif
+	puts (" rev ");
+
+	switch (r) {
+#if defined(CONFIG_ADS)
+	case 0x00:
+		puts ("ENG - this board sucks, check the errata, not supported\n");
+		return -1;
+	case 0x01:
+		puts ("PILOT - warning, read errata \n");
+		break;
+	case 0x02:
+		puts ("A - warning, read errata \n");
+		break;
+	case 0x03:
+		puts ("B \n");
+		break;
+#elif defined(CONFIG_MPC885ADS)
+	case 0x00:
+		puts ("NR\n");
+		break;
+#else  /* FADS and newer */
+	case 0x00:
+		puts ("ENG\n");
+		break;
+	case 0x01:
+		puts ("PILOT\n");
+		break;
+#endif /* CONFIG_ADS */
+	default:
+		printf ("unknown (0x%x)\n", r);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* ========================================================================= */
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+
+#ifdef CFG_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
+#endif
+
+int pcmcia_init(void)
+{
+	volatile pcmconf8xx_t	*pcmp;
+	uint v, slota = 0, slotb = 0;
+
+	/*
+	** Enable the PCMCIA for a Flash card.
+	*/
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+#if 0
+	pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
+	pcmp->pcmc_por0 = 0xc00ff05d;
+#endif
+
+	/* Set all slots to zero by default. */
+	pcmp->pcmc_pgcra = 0;
+	pcmp->pcmc_pgcrb = 0;
+#ifdef CONFIG_PCMCIA_SLOT_A
+	pcmp->pcmc_pgcra = 0x40;
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
+	pcmp->pcmc_pgcrb = 0x40;
+#endif
+
+	/* enable PCMCIA buffers */
+	*((uint *)BCSR1) &= ~BCSR1_PCCEN;
+
+	/* Check if any PCMCIA card is plugged in. */
+
+#ifdef CONFIG_PCMCIA_SLOT_A
+	slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
+	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
+#endif
+
+	if (!(slota || slotb)) {
+		printf("No card present\n");
+		pcmp->pcmc_pgcra = 0;
+		pcmp->pcmc_pgcrb = 0;
+		return -1;
+	}
+	else
+		printf("Card present (");
+
+	v = 0;
+
+	/* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
+	**
+	** Paolo - Yes, but i have to insert some 3.3V card in that slot on
+	**	   my FADS... :-)
+	*/
+
+#if defined(CONFIG_MPC86x)
+	switch ((pcmp->pcmc_pipr >> 30) & 3)
+#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
+	switch ((pcmp->pcmc_pipr >> 14) & 3)
+#endif
+	{
+	case 0x00 :
+		printf("5V");
+		v = 5;
+		break;
+	case 0x01 :
+		printf("5V and 3V");
+#ifdef CONFIG_FADS
+		v = 3; /* User lower voltage if supported! */
+#else
+		v = 5;
+#endif
+		break;
+	case 0x03 :
+		printf("5V, 3V and x.xV");
+#ifdef CONFIG_FADS
+		v = 3; /* User lower voltage if supported! */
+#else
+		v = 5;
+#endif
+		break;
+	}
+
+	switch (v) {
+#ifdef CONFIG_FADS
+	case 3:
+		printf("; using 3V");
+		/*
+		** Enable 3 volt Vcc.
+		*/
+		*((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
+		*((uint *)BCSR1) |= BCSR1_PCCVCC0;
+		break;
+#endif
+	case 5:
+		printf("; using 5V");
+#ifdef CONFIG_ADS
+		/*
+		** Enable 5 volt Vcc.
+		*/
+		*((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
+#endif
+#ifdef CONFIG_FADS
+		/*
+		** Enable 5 volt Vcc.
+		*/
+		*((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
+		*((uint *)BCSR1) |= BCSR1_PCCVCC1;
+#endif
+		break;
+
+	default:
+		*((uint *)BCSR1) |= BCSR1_PCCEN;  /* disable pcmcia */
+
+		printf("; unknown voltage");
+		return -1;
+	}
+	printf(")\n");
+	/* disable pcmcia reset after a while */
+
+	udelay(20);
+
+#ifdef CONFIG_PCMCIA_SLOT_A
+	pcmp->pcmc_pgcra = 0;
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
+	pcmp->pcmc_pgcrb = 0;
+#endif
+
+	/* If you using a real hd you should give a short
+	* spin-up time. */
+#ifdef CONFIG_DISK_SPINUP_TIME
+	udelay(CONFIG_DISK_SPINUP_TIME);
+#endif
+
+	return 0;
+}
+
+#endif	/* CFG_CMD_PCMCIA */
+
+/* ========================================================================= */
+
+#ifdef CFG_PC_IDE_RESET
+
+void ide_set_reset(int on)
+{
+	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+	/*
+	 * Configure PC for IDE Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+	} else {		/* release RESET */
+		immr->im_ioport.iop_pcdat |=   CFG_PC_IDE_RESET;
+	}
+
+	/* program port pin as GPIO output */
+	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
+	immr->im_ioport.iop_pcso  &= ~(CFG_PC_IDE_RESET);
+	immr->im_ioport.iop_pcdir |=   CFG_PC_IDE_RESET;
+}
+
+#endif	/* CFG_PC_IDE_RESET */
diff --git a/board/fads/fads.h b/board/fads/fads.h
new file mode 100755
index 0000000..1127c7f
--- /dev/null
+++ b/board/fads/fads.h
@@ -0,0 +1,514 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
+ * and Dan Malek
+ *
+ * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+ *
+ * This header file contains values common to all FADS family boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************
+ * Flash Memory Map as used by U-Boot:
+ *
+ *                          Start Address    Length
+ * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
+ * |                       | 0xFE00_0100     Reset Vector
+ * +                       + 0xFE0?_????
+ * | U-Boot code           |
+ * |                       |
+ * +-----------------------+ 0xFE04_0000 (sector border)
+ * |                       |
+ * |                       |
+ * | U-Boot environment    |
+ * |                       |                                 ^
+ * |                       |                                 | U-Boot
+ * +=======================+ 0xFE08_0000 (sector border)    -----------------
+ * | Available             |                                 | Applications
+ * | ...                   |                                 v
+ *
+ *****************************************************************************/
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+    "dhcp;"									\
+    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "		\
+    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+    "bootm"
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */
+
+/*
+ * New MPC86xADS and Duet provide two Ethernet connectivity options:
+ * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
+ * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
+ * got FEC so FEC is the default.
+ */
+#ifndef CONFIG_ADS
+#undef	CONFIG_SCC1_ENET		/* Disable SCC1 ethernet */
+#define	CONFIG_FEC_ENET			/* Use FEC ethernet  */
+#else					/* Old ADS has not got FEC option */
+#define	CONFIG_SCC1_ENET		/* Use SCC1 ethernet */
+#undef	CONFIG_FEC_ENET			/* No FEC ethernet  */
+#endif /* !CONFIG_ADS */
+
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#ifdef CONFIG_FEC_ENET
+#define CFG_DISCOVER_PHY
+#endif
+
+#ifndef CONFIG_COMMANDS
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
+			 | CFG_CMD_DHCP   \
+			 | CFG_CMD_IMMAP  \
+			 | CFG_CMD_JFFS2  \
+			 | CFG_CMD_MII    \
+			 | CFG_CMD_PCMCIA \
+			 | CFG_CMD_PING   \
+			)
+#endif /* !CONFIG_COMMANDS */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_LOAD_ADDR	 	0x00100000
+
+#define	CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
+#define	CFG_SDRAM_SIZE		0x00800000      	/* 8 Mbyte */
+#elif defined(CONFIG_FADS)				/* Old/new FADS */
+#define	CFG_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
+#else							/* Old ADS */
+#define	CFG_SDRAM_SIZE		0x00000000		/* No SDRAM */
+#endif
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#if (CFG_SDRAM_SIZE)
+#define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
+#else
+#define CFG_MEMTEST_END		0x0400000     	/* 1 ... 4 MB in DRAM	*/
+#endif /* CFG_SDRAM_SIZE */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
+
+#ifdef CONFIG_BZIP2
+#define	CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
+#else
+#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#endif /* CONFIG_BZIP2 */
+
+/*-----------------------------------------------------------------------
+ * Flash organization
+ */
+#define CFG_FLASH_BASE		CFG_MONITOR_BASE
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte	*/
+
+#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
+#define CFG_ENV_OFFSET		CFG_ENV_SECT_SIZE
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment		*/
+
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
+#define MTDPARTS_DEFAULT	"mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
+*/
+
+#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C configuration
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
+#define CFG_I2C_SLAVE		0x7F
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		14-22
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control
+ */
+#ifndef CFG_PLPRCR
+#define CFG_PLPRCR	PLPRCR_TEXPS
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		 0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/OR0 (Flash)
+ * BR1/OR1 (BCSR)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+#define BCSR_ADDR		((uint) 0xFF080000)
+
+#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
+#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
+
+/* BCSRx - Board Control and Status Registers */
+#define CFG_OR1_PRELIM	0xFFFF8110		/* 64Kbyte address space */
+#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/* values according to the manual */
+
+#define PCMCIA_MEM_ADDR		((uint)0xFF020000)
+#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
+
+#define	BCSR0			((uint) (BCSR_ADDR + 0x00))
+#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
+#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
+#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
+#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
+
+/*
+ * (F)ADS bitvalues by Helmut Buchsbaum
+ *
+ * See User's Manual for a proper
+ * description of the following structures
+ */
+
+#define BCSR0_ERB       ((uint)0x80000000)
+#define BCSR0_IP        ((uint)0x40000000)
+#define BCSR0_BDIS      ((uint)0x10000000)
+#define BCSR0_BPS_MASK  ((uint)0x0C000000)
+#define BCSR0_ISB_MASK  ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+
+#define BCSR1_FLASH_EN           ((uint)0x80000000)
+#define BCSR1_DRAM_EN            ((uint)0x40000000)
+#define BCSR1_ETHEN              ((uint)0x20000000)
+#define BCSR1_IRDEN              ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN            ((uint)0x02000000)
+#define BCSR1_RS232EN_1          ((uint)0x01000000)
+#define BCSR1_PCCEN              ((uint)0x00800000)
+#define BCSR1_PCCVCC0            ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
+#define BCSR1_RS232EN_2          ((uint)0x00040000)
+#define BCSR1_SDRAM_EN           ((uint)0x00020000)
+#define BCSR1_PCCVCC1            ((uint)0x00010000)
+
+#define BCSR1_PCCVCCON		 BCSR1_PCCVCC0
+
+#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_FLASH_PD_SHIFT     28
+#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT      23
+#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
+
+#define BCSR3_DBID_MASK          ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0            ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
+#define BCSR3_BREVN1             ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
+
+#define BCSR4_ETHLOOP            ((uint)0x80000000)
+#define BCSR4_TFPLDL             ((uint)0x40000000)
+#define BCSR4_TPSQEL             ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#define BCSR4_FETHRST            ((uint)0x00200000)
+
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_EN             ((uint)0x08000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860SAR
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#endif /* CONFIG_MPC860SAR */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_SPEED          ((uint)0x04000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VCCO               ((uint)0x02000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_ON           ((uint)0x00800000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_RST          ((uint)0x00200000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHRST            ((uint)0x00200000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_MODEM_EN           ((uint)0x00100000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC850
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#endif /* CONFIG_MPC850 */
+
+/* BSCR5 exists on MPC86xADS and Duet ADS only */
+
+#define CFG_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)
+
+#define BCSR5			(CFG_PHYDEV_ADDR + 0x300)
+
+#define BCSR5_MII2_EN		0x40
+#define BCSR5_MII2_RST		0x20
+#define BCSR5_T1_RST		0x10
+#define BCSR5_ATM155_RST	0x08
+#define BCSR5_ATM25_RST		0x04
+#define BCSR5_MII1_EN		0x02
+#define BCSR5_MII1_RST		0x01
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_MAC_PARTITION    1
+#define CONFIG_DOS_PARTITION    1
+#define CONFIG_ISO_PARTITION	1
+
+#undef	CONFIG_ATAPI
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0000
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+#undef CONFIG_DISK_SPINUP_TIME	/* usin´ Compact Flash */
diff --git a/board/fads/flash.c b/board/fads/flash.c
new file mode 100755
index 0000000..f0fb621
--- /dev/null
+++ b/board/fads/flash.c
@@ -0,0 +1,560 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#define QUAD_ID(id)	((((ulong)(id) & 0xFF) << 24) | \
+			 (((ulong)(id) & 0xFF) << 16) | \
+			 (((ulong)(id) & 0xFF) << 8)  | \
+			 (((ulong)(id) & 0xFF) << 0)    \
+			)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	vu_long *bcsr = (vu_long *)BCSR_ADDR;
+	unsigned long pd_size, total_size, bsize, or_am;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].size = 0;
+		flash_info[i].sector_count = 0;
+		flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */
+	}
+
+	switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) {
+	case 2:
+	case 4:
+	case 6:
+		pd_size = 0x800000;
+		or_am = 0xFF800000;
+		break;
+
+	case 5:
+	case 7:
+		pd_size = 0x400000;
+		or_am = 0xFFC00000;
+		break;
+
+	case 8:
+		pd_size = 0x200000;
+		or_am = 0xFFE00000;
+		break;
+
+	default:
+		pd_size = 0;
+		or_am = 0xFFE00000;
+		printf("## Unsupported flash detected by BCSR: 0x%08X\n", bcsr[2]);
+	}
+
+	total_size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS && total_size < pd_size; ++i) {
+		bsize = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size),
+				       &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, bsize, bsize >> 20);
+		}
+
+		total_size += bsize;
+	}
+
+	if (total_size != pd_size) {
+		printf("## Detected flash size %lu conflicts with PD data %lu\n",
+		       total_size, pd_size);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = or_am | CFG_OR_TIMING_FLASH;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		if (CFG_MONITOR_BASE >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CFG_MONITOR_BASE,
+				       CFG_MONITOR_BASE + monitor_flash_len - 1,
+				       &flash_info[i]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		if (CFG_ENV_ADDR >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CFG_ENV_ADDR,
+				       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+				       &flash_info[i]);
+#endif
+	}
+
+	return total_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_BM:
+		printf ("BRIGHT MICRO ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+		break;
+	case FLASH_AM080:
+		printf ("29F080 or 29LV080 (8 Mbit, uniform sectors)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ * The following code can not run from flash!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x90909090;
+
+	switch (addr[0]) {
+	case QUAD_ID(AMD_MANUFACT):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case QUAD_ID(FUJ_MANUFACT):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	switch (addr[1]) {	/* device ID            */
+	case QUAD_ID(AMD_ID_F040B):
+	case QUAD_ID(AMD_ID_LV040B):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case QUAD_ID(AMD_ID_F080B):
+		info->flash_id += FLASH_AM080;
+		info->sector_count = 16;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#if 0
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+#endif /* 0 */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+#if 0
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+#else
+	/* set sector offsets for uniform sector type */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = (ulong)addr + (i * 0x00040000);
+#endif
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *) (info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *) info->start[0];
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x80808080;
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *) (info->start[sect]);
+			addr[0] = 0x30303030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (vu_long *) (info->start[l_sect]);
+	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
+	{
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *) info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & data) != data) {
+		return ERR_NOT_ERASED;
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0xA0A0A0A0;
+
+	*((vu_long *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080))
+	{
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			return ERR_TIMOUT;
+		}
+	}
+	return (0);
+}
diff --git a/board/fads/lamp.c b/board/fads/lamp.c
new file mode 100755
index 0000000..4e58291
--- /dev/null
+++ b/board/fads/lamp.c
@@ -0,0 +1,47 @@
+#include <config.h>
+
+#ifndef CONFIG_ADS /* Old ADS has not got any user-controllable LED */
+
+#include <common.h>
+
+void
+signal_delay(unsigned int n)
+{
+  while (n--);
+}
+
+void
+signal_on(void)
+{
+  *((volatile uint *)BCSR4) &= ~(1<<(31-3)); /* led on */
+}
+
+void
+signal_off(void)
+{
+  *((volatile uint *)BCSR4) |= (1<<(31-3)); /* led off */
+}
+
+void
+slow_blink(unsigned int n)
+{
+  while (n--) {
+    signal_on();
+    signal_delay(0x00400000);
+    signal_off();
+    signal_delay(0x00400000);
+  }
+}
+
+void
+fast_blink(unsigned int n)
+{
+  while (n--) {
+    signal_on();
+    signal_delay(0x00100000);
+    signal_off();
+    signal_delay(0x00100000);
+  }
+}
+
+#endif /* !CONFIG_ADS */
diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds
new file mode 100755
index 0000000..21a2d9e
--- /dev/null
+++ b/board/fads/u-boot.lds
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o		(.text)
+
+    /*. = DEFINED(env_offset) ? env_offset : .;*/
+    common/environment.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/fads/u-boot.lds.debug b/board/fads/u-boot.lds.debug
new file mode 100755
index 0000000..650572d
--- /dev/null
+++ b/board/fads/u-boot.lds.debug
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/flagadm/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/flagadm/config.mk b/board/flagadm/config.mk
new file mode 100755
index 0000000..9c72c79
--- /dev/null
+++ b/board/flagadm/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8xxL boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c
new file mode 100755
index 0000000..9c55367
--- /dev/null
+++ b/board/flagadm/flagadm.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/*Orginal table, GPL4 disabled*/
+const uint sdram_table[] =
+{
+	/* single read   (offset 0x00 in upm ram) */
+	0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00,
+	0x1ff74c47,
+	/* Precharge */
+	0x1FF74C05,
+	_NOT_USED_,
+	_NOT_USED_,
+	/* burst read    (offset 0x08 in upm ram) */
+	0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00,
+	0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* single write  (offset 0x18 in upm ram) */
+	0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47,
+	/* Load moderegister */
+	0x1FF74C34, /*Precharge*/
+	0xEFEA8C34, /*NOP*/
+	0x1FB54C35, /*Load moderegister*/
+	_NOT_USED_,
+
+	/* burst write   (offset 0x20 in upm ram) */
+	0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00,
+	0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* refresh       (offset 0x30 in upm ram) */
+	0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04,
+	0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* exception     (offset 0x3C in upm ram) */
+	0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* GPL5 driven every cycle */
+/* the display and the DSP */
+const uint dsp_disp_table[] =
+{
+	/* single read   (offset 0x00 in upm ram) */
+	0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004,
+	0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05,
+	/* burst read    (offset 0x08 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* single write  (offset 0x18 in upm ram) */
+	0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004,
+	0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05,
+	/* burst write   (offset 0x20 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* refresh       (offset 0x30 in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* exception     (offset 0x3C in upm ram) */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+int checkboard (void)
+{
+	puts ("Board: FlagaDM V3.0\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0;
+
+	memctl->memc_or2 = CFG_OR2;
+	memctl->memc_br2 = CFG_BR2;
+
+	udelay(100);
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = MPTPR_PTP_DIV16;
+	memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_1X;
+
+	/*Do the initialization of the SDRAM*/
+	/*Start with the precharge cycle*/
+	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
+				MCR_MLCF(1) | MCR_MAD(0x5));
+
+	/*Then we need two refresh cycles*/
+	memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_2X;
+	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
+				MCR_MLCF(2) | MCR_MAD(0x30));
+
+	/*Mode register programming*/
+	memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/
+	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
+				MCR_MLCF(1) | MCR_MAD(0x1C));
+
+	/* That should do it, just enable the periodic refresh in burst of 4*/
+	memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X;
+	memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
+
+	size_b0 = 16*1024*1024;
+
+	/*
+	 * No bank 1 or 3
+	 * invalidate bank
+	 */
+	memctl->memc_br1 = 0;
+	memctl->memc_br3 = 0;
+
+	upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
+
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;
+
+	memctl->memc_or4 = CFG_OR4;
+	memctl->memc_br4 = CFG_BR4;
+
+	return (size_b0);
+}
diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c
new file mode 100755
index 0000000..fd0082c
--- /dev/null
+++ b/board/flagadm/flash.c
@@ -0,0 +1,697 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <flash.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+ulong flash_recognize (vu_long *base);
+int write_word (flash_info_t *info, ulong dest, ulong data);
+void flash_get_geometry (vu_long *base, flash_info_t *info);
+void flash_unprotect(flash_info_t *info);
+int _flash_real_protect(flash_info_t *info, long idx, int on);
+
+
+unsigned long flash_init (void)
+{
+	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t	*memctl = &immap->im_memctl;
+	int i;
+	int rec;
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	*((vu_short*)CFG_FLASH_BASE) = 0xffff;
+
+	flash_get_geometry ((vu_long*)CFG_FLASH_BASE, &flash_info[0]);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) |
+		(memctl->memc_br0 & ~(BR_BA_MSK));
+
+	rec = flash_recognize((vu_long*)CFG_FLASH_BASE);
+
+	if (rec == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				flash_info[0].size, flash_info[0].size<<20);
+	}
+
+#if CFG_FLASH_PROTECTION
+	/*Unprotect all the flash memory*/
+	flash_unprotect(&flash_info[0]);
+#endif
+
+	*((vu_short*)CFG_FLASH_BASE) = 0xffff;
+
+	return (flash_info[0].size);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_OFFSET,
+		      CFG_ENV_OFFSET+CFG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (flash_info[0].size);
+}
+
+
+int flash_get_protect_status(flash_info_t * info, long idx)
+{
+	vu_short * base;
+	ushort res;
+
+#ifdef DEBUG
+	printf("\n Attempting to set protection info with %d sectors\n", info->sector_count);
+#endif
+
+
+	base = (vu_short*)info->start[idx];
+
+	*(base) = 0xffff;
+
+	*(base + 0x55) = 0x0098;
+	res = base[0x2];
+
+	*(base) = 0xffff;
+
+	if(res != 0)
+		res = 1;
+	else
+		res = 0;
+
+	return res;
+}
+
+void flash_get_geometry (vu_long *base, flash_info_t *info)
+{
+	int i,j;
+	ulong ner = 0;
+	vu_short * sb  = (vu_short*)base;
+	ulong offset = (ulong)base;
+
+	/* Read Device geometry */
+
+	*sb = 0xffff;
+
+	*sb = 0x0090;
+
+	info->flash_id = ((ulong)base[0x0]);
+#ifdef DEBUG
+	printf("Id is %x\n", (uint)(ulong)info->flash_id);
+#endif
+
+	*sb = 0xffff;
+
+	*(sb+0x55) = 0x0098;
+
+	info->size = 1 << (sb[0x27]); /* Read flash size */
+
+#ifdef DEBUG
+	printf("Size is %x\n", (uint)(ulong)info->size);
+#endif
+
+	*sb = 0xffff;
+
+	*(sb + 0x55) = 0x0098;
+	ner = sb[0x2c] ; /*Number of erase regions*/
+
+#ifdef DEBUG
+	printf("Number of erase regions %x\n", (uint)ner);
+#endif
+
+	info->sector_count = 0;
+
+	for(i = 0; i < ner; i++)
+	{
+		uint s;
+		uint count;
+		uint t1,t2,t3,t4;
+
+		*sb = 0xffff;
+
+		*(sb + 0x55) = 0x0098;
+
+		t1 = sb[0x2d + i*4];
+		t2 = sb[0x2e + i*4];
+		t3 = sb[0x2f + i*4];
+		t4 = sb[0x30 + i*4];
+
+		count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/
+		s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/
+
+#ifdef DEBUG
+		printf("count and size %x, %x\n", count, s);
+		printf("sector count for erase region %d is %d\n", i, count);
+#endif
+		for(j = 0; j < count; j++)
+		{
+#ifdef DEBUG
+			printf("%x, ", (uint)offset);
+#endif
+			info->start[ info->sector_count + j] = offset;
+			offset += s;
+		}
+		info->sector_count += count;
+	}
+
+	if ((offset - (ulong)base) != info->size)
+		printf("WARNING reported size %x does not match to calculted size %x.\n"
+				, (uint)info->size, (uint)(offset - (ulong)base) );
+
+	/* Next check if there are any sectors protected.*/
+
+	for(i = 0; i < info->sector_count; i++)
+		info->protect[i] = flash_get_protect_status(info, i);
+
+	*sb = 0xffff;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return ;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case INTEL_MANUFACT & FLASH_VENDMASK:
+		printf ("Intel ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case INTEL_ID_28F320C3B & FLASH_TYPEMASK:
+		printf ("28F320RC3(4 MB)\n");
+		break;
+	case INTEL_ID_28F320J3A:
+		printf("28F320J3A (4 MB)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+			break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf ("  %02d %08lX%s",
+			i, info->start[i],
+			info->protect[i]!=0 ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return ;
+}
+
+ulong flash_recognize (vu_long *base)
+{
+	ulong id;
+	ulong res = FLASH_UNKNOWN;
+	vu_short * sb = (vu_short*)base;
+
+	*sb = 0xffff;
+
+	*sb = 0x0090;
+	id = base[0];
+
+	switch (id & 0x00FF0000)
+	{
+		case (MT_MANUFACT & 0x00FF0000):	/* MT or => Intel */
+		case (INTEL_ALT_MANU & 0x00FF0000):
+		res = FLASH_MAN_INTEL;
+		break;
+	default:
+		res = FLASH_UNKNOWN;
+	}
+
+	*sb = 0xffff;
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------*/
+#define INTEL_FLASH_STATUS_BLS	0x02
+#define INTEL_FLASH_STATUS_PSS	0x04
+#define INTEL_FLASH_STATUS_VPPS	0x08
+#define INTEL_FLASH_STATUS_PS	0x10
+#define INTEL_FLASH_STATUS_ES	0x20
+#define INTEL_FLASH_STATUS_ESS	0x40
+#define INTEL_FLASH_STATUS_WSMS	0x80
+
+int	flash_decode_status_bits(char status)
+{
+	int err = 0;
+
+	if(!(status & INTEL_FLASH_STATUS_WSMS)) {
+		printf("Busy\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_ESS) {
+		printf("Erase suspended\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_ES) {
+		printf("Error in block erase\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_PS) {
+		printf("Error in programming\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_VPPS) {
+		printf("Vpp low, operation aborted\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_PSS) {
+		printf("Program is suspended\n");
+		err = -1;
+	}
+
+	if(status & INTEL_FLASH_STATUS_BLS) {
+		printf("Attempting to program/erase a locked sector\n");
+		err = -1;
+	}
+
+	if((status & INTEL_FLASH_STATUS_PS) &&
+	   (status & INTEL_FLASH_STATUS_ES) &&
+	   (status & INTEL_FLASH_STATUS_ESS)) {
+		printf("A command sequence error\n");
+		return -1;
+	}
+
+	return err;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr;
+	int flag, prot, sect;
+	ulong start, now;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		char tmp;
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_short *)(info->start[sect]);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Single Block Erase Command */
+			*addr = 0x0020;
+			/* Confirm */
+			*addr = 0x00D0;
+			/* Resume Command, as per errata update */
+			*addr = 0x00D0;
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			*addr = 0x70; /*Read status register command*/
+			tmp = (short)*addr & 0x00FF; /* Read the status */
+			while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					*addr = 0x0050; /* Reset the status register */
+					*addr = 0xffff;
+					printf ("Timeout\n");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - start) > 1000) {	/* every second */
+					putc ('.');
+				}
+				udelay(100000); /* 100 ms */
+				*addr = 0x0070; /*Read status register command*/
+				tmp = (short)*addr & 0x00FF; /* Read status */
+				start = get_timer(0);
+			}
+			if( tmp & INTEL_FLASH_STATUS_ES )
+				flash_decode_status_bits(tmp);
+
+			*addr = 0x0050; /* Reset the status register */
+			*addr = 0xffff; /* Reset to read mode */
+		}
+	}
+
+
+	printf (" done\n");
+	return rcode;
+}
+
+void flash_unprotect (flash_info_t *info)
+{
+	/*We can only unprotect the whole flash at once*/
+	/*Therefore we must prevent the _flash_real_protect()*/
+	/*from re-protecting sectors, that ware protected before */
+	/*we called flash_real_protect();*/
+
+	int i;
+
+	for(i = 0; i < info->sector_count; i++)
+		info->protect[i] = 0;
+
+#ifdef CFG_FLASH_PROTECTION
+		_flash_real_protect(info, 0, 0);
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_word (flash_info_t *info, ulong dest, ulong da)
+{
+	vu_short *addr = (vu_short *)dest;
+	ulong start;
+	char csr;
+	int flag;
+	ushort * d = (ushort*)&da;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((*addr & d[0]) != d[0]) || ((*(addr+1) & d[1]) != d[1])) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for(i = 0; i < 2; i++)
+	{
+		/* Write Command */
+		*addr = 0x0010;
+
+		/* Write Data */
+		*addr = d[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		flag  = 0;
+		*addr = 0x0070; /*Read statusregister command */
+		while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				flag = 1;
+				break;
+			}
+			*addr = 0x0070; /*Read statusregister command */
+		}
+		if (csr & INTEL_FLASH_STATUS_PSS) {
+			printf ("CSR indicates write error (%0x) at %08lx\n",
+					csr, (ulong)addr);
+			flag = 1;
+		}
+
+		/* Clear Status Registers Command */
+		*addr = 0x0050;
+		/* Reset to read array mode */
+		*addr = 0xffff;
+		addr++;
+	}
+
+	return (flag);
+}
+
+int flash_real_protect(flash_info_t *info, long offset, int prot)
+{
+	int i, idx;
+
+	for(idx = 0; idx < info->sector_count; idx++)
+		if(info->start[idx] == offset)
+			break;
+
+	if(idx==info->sector_count)
+		return -1;
+
+	if(prot == 0) {
+		/* Unprotect one sector, which means unprotect all flash
+		 * and reprotect the other protected sectors.
+		 */
+		_flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/
+		info->protect[idx] = 0;
+
+		for(i = 0; i < info->sector_count; i++)
+			if(info->protect[i])
+				_flash_real_protect(info, i, 1);
+		}
+	else {
+		/* We can protect individual sectors */
+		_flash_real_protect(info, idx, 1);
+	}
+
+	for( i = 0; i < info->sector_count; i++)
+		info->protect[i] = flash_get_protect_status(info, i);
+
+	return 0;
+}
+
+int _flash_real_protect(flash_info_t *info, long idx, int prot)
+{
+	vu_short *addr;
+	int flag;
+	ushort cmd;
+	ushort tmp;
+	ulong now, start;
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		printf ("Can't change protection for unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return -1;
+	}
+
+	if(prot == 0) {
+		/*Unlock the sector*/
+		cmd = 0x00D0;
+	}
+	else {
+		/*Lock the sector*/
+		cmd = 0x0001;
+	}
+
+	addr = (vu_short *)(info->start[idx]);
+
+	/* If chip is busy, wait for it */
+	start = get_timer(0);
+	*addr = 0x0070; /*Read status register command*/
+	tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
+	while(!(tmp & INTEL_FLASH_STATUS_WSMS)) {
+		/*Write State Machine Busy*/
+		/*Wait untill done or timeout.*/
+		if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0x0050; /* Reset the status register */
+			*addr = 0xffff; /* Reset the chip */
+			printf ("TTimeout\n");
+			return 1;
+		}
+		*addr = 0x0070;
+		tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
+		start = get_timer(0);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Unlock block*/
+	*addr = 0x0060;
+
+	*addr = cmd;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+	*addr = 0x0070; /*Read status register command*/
+	tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */
+	while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
+		/* Write State Machine Busy */
+		if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0x0050; /* Reset the status register */
+			*addr = 0xffff;
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - start) > 1000) {	/* every second */
+			putc ('.');
+		}
+		udelay(100000); /* 100 ms */
+		*addr = 0x70; /*Read status register command*/
+		tmp = (short)*addr & 0x00FF; /* Read status */
+		start = get_timer(0);
+	}
+	if( tmp & INTEL_FLASH_STATUS_PS )
+		flash_decode_status_bits(tmp);
+
+	*addr =0x0050; /*Clear status register*/
+
+	/* reset to read mode */
+	*addr = 0xffff;
+
+	return 0;
+}
diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds
new file mode 100755
index 0000000..04995ea
--- /dev/null
+++ b/board/flagadm/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug
new file mode 100755
index 0000000..3165d56
--- /dev/null
+++ b/board/flagadm/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/funkwerk/vovpn-gw/Makefile b/board/funkwerk/vovpn-gw/Makefile
new file mode 100755
index 0000000..f77cc60
--- /dev/null
+++ b/board/funkwerk/vovpn-gw/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o m88e6060.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/funkwerk/vovpn-gw/config.mk b/board/funkwerk/vovpn-gw/config.mk
new file mode 100755
index 0000000..e59b483
--- /dev/null
+++ b/board/funkwerk/vovpn-gw/config.mk
@@ -0,0 +1,21 @@
+# (C) Copyright 2004
+# Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+#
+# Support for the Elmeg VoVPN Gateway Module
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+TEXT_BASE = 0xfff00000
diff --git a/board/funkwerk/vovpn-gw/flash.c b/board/funkwerk/vovpn-gw/flash.c
new file mode 100755
index 0000000..7dd0d3f
--- /dev/null
+++ b/board/funkwerk/vovpn-gw/flash.c
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3
+ * and 28F128J3A flashs working in 8 Bit mode.
+ *
+ * Most of this code is taken from existing u-boot source code.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t				flash_info[CFG_MAX_FLASH_BANKS];
+
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_READ_STATUS		0x70
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xd0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_SUSPEND_ERASE		0xb0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_WRITE_BUFF		0xe8
+#define FLASH_CMD_PROG_RESUME		0xd0
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xd0
+#define FLASH_STATUS_DONE		0x80
+
+#define FLASH_WRITE_BUFFER_SIZE		32
+
+#ifdef CFG_FLASH_16BIT
+#define FLASH_WORD_SIZE			unsigned short
+#define FLASH_ID_MASK			0xffff
+#define FLASH_CMD_ADDR_SHIFT		0
+#else
+#define FLASH_WORD_SIZE			unsigned char
+#define FLASH_ID_MASK			0xff
+/* A0 is not used in either 8x or 16x for READ ID */
+#define FLASH_CMD_ADDR_SHIFT		1
+#endif
+
+
+static unsigned long
+flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	volatile FLASH_WORD_SIZE *p;
+	FLASH_WORD_SIZE value;
+	int i;
+
+	addr[0] = FLASH_CMD_READ_ID;
+
+	/* manufactor */
+	value = addr[0 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+
+	}
+
+	/* device */
+	value = addr[1 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+	}
+
+	/* setup sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count);
+	}
+
+	/* check protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		p = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1;
+	}
+
+	/* reset bank */
+	*addr = FLASH_CMD_RESET;
+	return (info->size);
+}
+
+unsigned long
+flash_init(void)
+{
+	unsigned long	size;
+	int		i;
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+	size = flash_get((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH Size=0x%08lx\n", size);
+		return (0);
+	}
+
+	/* always protect 1 sector containing the HRCW */
+	flash_protect(FLAG_PROTECT_SET,
+		      flash_info[0].start[0],
+		      flash_info[0].start[1] - 1,
+		      &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_FLASH,
+		      CFG_MONITOR_FLASH+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+#ifdef	CFG_ENV_IS_IN_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+void
+flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320JA3 (32 Mbit)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640JA3 (64 Mbit)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128JA3 (128 Mbit)\n");
+				break;
+	default:		printf ("Unknown Chip Type");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long start, now, last;
+	int flag, prot, sect;
+	volatile FLASH_WORD_SIZE *addr;
+	FLASH_WORD_SIZE status;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return (1);
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Cannot erase unknown flash - aborted\n");
+		return (1);
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect]) {
+			continue;
+		}
+
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+#ifdef DEBUG
+		printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
+#endif
+
+		*addr = FLASH_CMD_CLEAR_STATUS;
+		*addr = FLASH_CMD_BLOCK_ERASE;
+		*addr = FLASH_CMD_ERASE_CONFIRM;
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
+			if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf("Flash erase timeout at address %lx\n", info->start[sect]);
+				*addr = FLASH_CMD_SUSPEND_ERASE;
+				*addr = FLASH_CMD_RESET;
+				return (1);
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+		*addr = FLASH_CMD_RESET;
+	}
+	printf (" done\n");
+	return (0);
+}
+
+static int
+write_buff2( volatile FLASH_WORD_SIZE *dst,
+	     volatile FLASH_WORD_SIZE *src,
+	     unsigned long cnt )
+{
+	unsigned long start;
+	FLASH_WORD_SIZE status;
+	int flag, i;
+
+	start = get_timer (0);
+	while (1) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		dst[0] = FLASH_CMD_WRITE_BUFF;
+		if ((status = *dst) & FLASH_STATUS_DONE) {
+			break;
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (-1);
+		}
+	}
+	dst[0] = (FLASH_WORD_SIZE)(cnt - 1);
+	for (i=0; i<cnt; i++) {
+		dst[i] = src[i];
+	}
+	dst[0] = FLASH_CMD_PROG_RESUME;
+
+	if (flag) {
+		enable_interrupts();
+	}
+
+	return( 0 );
+}
+
+static int
+poll_status( volatile FLASH_WORD_SIZE *addr )
+{
+	unsigned long start;
+
+	start = get_timer (0);
+	/* wait for error or finish */
+	while (1) {
+		if (*addr == FLASH_STATUS_DONE) {
+			if (*addr == FLASH_STATUS_DONE) {
+				break;
+			}
+		}
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = FLASH_CMD_RESET;
+			return (-1);
+		}
+	}
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*
+ * write_buff return values:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+int
+write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt)
+{
+	volatile FLASH_WORD_SIZE *addr, *dst;
+	unsigned long bcnt;
+	int flag, i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return (4);
+	}
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[0]);
+	dst = (volatile FLASH_WORD_SIZE *) udst;
+
+#ifdef CFG_FLASH_16BIT
+#error NYI
+#else
+	while (cnt > 0) {
+		/* Check if buffer write is possible */
+		if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) {
+			bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt;
+			/* Check if Flash is (sufficiently) erased */
+			for (i=0; i<bcnt; i++) {
+				if ((dst[i] & src[i]) != src[i]) {
+					return (2);
+				}
+			}
+			if (write_buff2( dst,src,bcnt ) != 0) {
+				addr[0] = FLASH_CMD_READ_STATUS;
+			}
+			if (poll_status( dst ) != 0) {
+				return (1);
+			}
+			cnt -= bcnt;
+			dst += bcnt;
+			src += bcnt;
+			continue;
+		}
+
+		/* Check if Flash is (sufficiently) erased */
+		if ((*dst & *src) != *src) {
+			return (2);
+		}
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		addr[0] = FLASH_CMD_ERASE_CONFIRM;
+		addr[0] = FLASH_CMD_WRITE;
+		*dst++ = *src++;
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (poll_status( dst ) != 0) {
+			return (1);
+		}
+		cnt --;
+	}
+#endif
+	return (0);
+}
+
+int
+flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	volatile FLASH_WORD_SIZE *addr;
+	unsigned long start;
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[sector]);
+	*addr = FLASH_CMD_CLEAR_STATUS;
+	*addr = FLASH_CMD_PROTECT;
+
+	if(prot) {
+		*addr = FLASH_CMD_PROTECT_SET;
+	} else {
+		*addr = FLASH_CMD_PROTECT_CLEAR;
+	}
+
+	/* wait for error or finish */
+	start = get_timer (0);
+	while(!(addr[0] & FLASH_STATUS_DONE)){
+		if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+			printf("Flash protect timeout at address %lx\n",  info->start[sector]);
+			addr[0] = FLASH_CMD_RESET;
+			return (1);
+		}
+	}
+
+	/* Set software protect flag */
+	info->protect[sector] = prot;
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
diff --git a/board/funkwerk/vovpn-gw/m88e6060.c b/board/funkwerk/vovpn-gw/m88e6060.c
new file mode 100755
index 0000000..03a03d0
--- /dev/null
+++ b/board/funkwerk/vovpn-gw/m88e6060.c
@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <net.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+static int		prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 };
+static int		phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 };
+
+static m88x_regCfg_t	prtCfg0[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001e },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg1[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001d },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg2[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001b },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg3[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x0017 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg4[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x000f },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*prtCfg[M88X_PRT_CNT] = {
+	prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL
+};
+
+static m88x_regCfg_t	phyCfgX[] = {
+	{  4, 0xfa1f, 0x01e0 },
+	{  0, 0x213f, 0x1200 },
+	{ 24, 0x81ff, 0x1200 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*phyCfg[M88X_PHY_CNT] = {
+	phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL
+};
+
+#if 0
+static void
+m88e6060_dump( int devAddr )
+{
+	int		i, j;
+	unsigned short	val[6];
+
+	printf( "M88E6060 Register Dump\n" );
+	printf( "====================================\n" );
+	printf( "PortNo    0    1    2    3    4    5\n" );
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] );
+	printf( "STAT   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] );
+	printf( "ID     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] );
+	printf( "CNTL   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] );
+	printf( "VLAN   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] );
+	printf( "PAV    %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] );
+	printf( "RX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] );
+	printf( "TX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	printf( "------------------------------------\n" );
+	printf( "PhyNo     0    1    2    3    4\n" );
+	for (i=0; i<9; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+	for (i=0x10; i<0x1d; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+}
+#endif
+
+int
+m88e6060_initialize( int devAddr )
+{
+	static char	*_f = "m88e6060_initialize:";
+	m88x_regCfg_t	*p;
+	int		err;
+	int		i;
+	unsigned short	val;
+
+	/*** reset all phys into powerdown ************************************/
+	for (i=0, err=0; i<M88X_PHY_CNT; i++) {
+		err += bb_miiphy_read(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,&val );
+		/* keep SpeedLSB, Duplex */
+		val &= 0x2100;
+		/* set SWReset, AnegEn, PwrDwn, RestartAneg */
+		val |= 0x9a00;
+		err += bb_miiphy_write(NULL, devAddr+phyTab[i],M88X_PHY_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] reset phys\n",_f );
+		return( -1 );
+	}
+
+	/*** disable all ports ************************************************/
+	for (i=0, err=0; i<M88X_PRT_CNT; i++) {
+		err += bb_miiphy_read(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,&val );
+		val &= 0xfffc;
+		err += bb_miiphy_write(NULL, devAddr+prtTab[i],M88X_PRT_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] disable ports\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize switch ************************************************/
+	/* set switch mac addr */
+#define ea eth_get_dev()->enetaddr
+	val = (ea[4] <<  8) | ea[5];
+	err = bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC45,val );
+	val = (ea[2] <<  8) | ea[3];
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC23,val );
+	val = (ea[0] <<  8) | ea[1];
+#undef ea
+	val &= 0xfeff;		/* clear DiffAddr */
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_MAC01,val );
+	if (err) {
+		printf( "%s [ERR] switch mac address register\n",_f );
+		return( -1 );
+	}
+
+	/* !DiscardExcessive, MaxFrameSize, CtrMode */
+	err = bb_miiphy_read(NULL, devAddr+15,M88X_GLB_CNTL,&val );
+	val &= 0xd870;
+	val |= 0x0500;
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_GLB_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] switch global control register\n",_f );
+		return( -1 );
+	}
+
+	/* LernDis off, ATUSize 1024, AgeTime 5min */
+	err = bb_miiphy_read(NULL, devAddr+15,M88X_ATU_CNTL,&val );
+	val &= 0x000f;
+	val |= 0x2130;
+	err += bb_miiphy_write(NULL, devAddr+15,M88X_ATU_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] atu control register\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize ports *************************************************/
+	for (i=0; i<M88X_PRT_CNT; i++) {
+		if ((p = prtCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += bb_miiphy_read(NULL, devAddr+prtTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += bb_miiphy_write(NULL, devAddr+prtTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+
+	/*** initialize phys **************************************************/
+	for (i=0; i<M88X_PHY_CNT; i++) {
+		if ((p = phyCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += bb_miiphy_read(NULL, devAddr+phyTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += bb_miiphy_write(NULL, devAddr+phyTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+	udelay(100000);
+	return( 0 );
+}
+#endif
diff --git a/board/funkwerk/vovpn-gw/m88e6060.h b/board/funkwerk/vovpn-gw/m88e6060.h
new file mode 100755
index 0000000..15d4583
--- /dev/null
+++ b/board/funkwerk/vovpn-gw/m88e6060.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _INC_m88e6060_h_
+#define _INC_m88e6060_h_
+
+/* ************************************************************************** */
+/* *** DEFINES ************************************************************** */
+
+/* switch hw */
+#define M88X_PRT_CNT			6
+#define M88X_PHY_CNT			5
+
+/* phy register offsets */
+#define M88X_PHY_CNTL			0x00
+#define M88X_PHY_STAT			0x00
+#define M88X_PHY_ID0			0x02
+#define M88X_PHY_ID1			0x03
+#define M88X_PHY_ANEG_ADV		0x04
+#define M88X_PHY_LPA			0x05
+#define M88X_PHY_ANEG_EXP		0x06
+#define M88X_PHY_NPT			0x07
+#define M88X_PHY_LPNP			0x08
+
+/* port register offsets */
+#define M88X_PRT_STAT			0x00
+#define M88X_PRT_ID			0x03
+#define M88X_PRT_CNTL			0x04
+#define M88X_PRT_VLAN			0x06
+#define M88X_PRT_PAV			0x0b
+#define M88X_PRT_RX			0x10
+#define M88X_PRT_TX			0x11
+
+/* global/atu register offsets */
+#define M88X_GLB_STAT			0x00
+#define M88X_GLB_MAC01			0x01
+#define M88X_GLB_MAC23			0x02
+#define M88X_GLB_MAC45			0x03
+#define M88X_GLB_CNTL			0x04
+#define M88X_ATU_CNTL			0x0a
+#define M88X_ATU_OP			0x0b
+
+/* id0 register - 0x02 */
+#define M88X_PHY_ID0_VALUE		0x0141
+
+/* id1 register - 0x03 */
+#define M88X_PHY_ID1_VALUE		0x0c80		/* without revision ! */
+
+
+/* misc */
+#define M88E6060_ID		((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE)
+
+/* ************************************************************************** */
+/* *** TYPEDEFS ************************************************************* */
+
+typedef struct {
+	int		reg;
+	unsigned short	msk;
+	unsigned short	val;
+} m88x_regCfg_t;
+
+/* ************************************************************************** */
+/* *** PROTOTYPES *********************************************************** */
+
+extern int		m88e6060_initialize( int );
+
+#endif	/* _INC_m88e6060_h_ */
diff --git a/board/funkwerk/vovpn-gw/u-boot.lds b/board/funkwerk/vovpn-gw/u-boot.lds
new file mode 100755
index 0000000..bf8048d
--- /dev/null
+++ b/board/funkwerk/vovpn-gw/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c
new file mode 100755
index 0000000..97f81ee
--- /dev/null
+++ b/board/funkwerk/vovpn-gw/vovpn-gw.c
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+    /* Port A configuration */
+    {	/*	     conf ppar psor pdir podr pdat */
+	/* PA31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1252           */
+	/* PA30 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    BP_RES           */
+	/* PA29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1253           */
+	/* PA28 */ { 1,   1,   1,   1,   0,   0 }, /* FCC1   RMII TX_EN       */
+	/* PA27 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII CRS_DV      */
+	/* PA26 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII RX_ERR      */
+	/* PA25 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA24 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA23 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA22 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA21 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA20 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    LED STATUS       */
+	/* PA19 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[1]      */
+	/* PA18 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[0]      */
+	/* PA17 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[0]      */
+	/* PA16 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[1]      */
+	/* PA15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1255           */
+	/* PA14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP????           */
+	/* PA13 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    EN_BCTL1 XXX jse */
+	/* PA12 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    SWITCH RESET     */
+	/* PA11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL1 RESET    */
+	/* PA10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL2 RESET    */
+	/* PA9  */ { 1,   1,   0,   1,   0,   0 }, /* SMC2   TXD              */
+	/* PA8  */ { 1,   1,   0,   0,   0,   0 }, /* SMC2   RXD              */
+	/* PA7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exit       */
+    },
+
+    /* Port B configuration */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PB31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1257           */
+	/* PB30 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII CRS_DV      */
+	/* PB29 */ { 1,   1,   1,   1,   0,   0 }, /* FCC2   RMII TX_EN       */
+	/* PB28 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RX_ERR      */
+	/* PB27 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1TXD XXX val=0  */
+	/* PB26 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1RXD XXX val,dr */
+	/* PB25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1259           */
+	/* PB24 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_B2 L1RSYNC          */
+	/* PB23 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[1]      */
+	/* PB22 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[0]      */
+	/* PB21 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[0]      */
+	/* PB20 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[1]      */
+	/* PB19 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    PHY MDC          */
+	/* PB18 */ { 1,   0,   0,   0,   0,   0 }, /* GPIO   PHY MDIO         */
+	/* PB17 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB16 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB15 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB14 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    },
+
+    /* Port C */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PC31 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC30 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1183           */
+	/* PC28 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1184           */
+	/* PC27 */ { 1,   1,   0,   0,   0,   0 }, /* CLK5   TDM_A1 RX        */
+	/* PC26 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1185           */
+	/* PC25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1178           */
+	/* PC24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1186           */
+	/* PC23 */ { 1,   1,   0,   0,   0,   0 }, /* CLK9   TDM_B2 RX        */
+	/* PC22 */ { 1,   1,   0,   0,   0,   0 }, /* CLK10  FCC1 RMII REFCLK */
+	/* PC21 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1187           */
+	/* PC20 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1182           */
+	/* PC19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1188           */
+	/* PC18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    HW RESET         */
+	/* PC17 */ { 1,   1,   0,   1,   0,   0 }, /* BRG8   SWITCH CLKIN     */
+	/* PC16 */ { 1,   1,   0,   0,   0,   0 }, /* CLK16  FCC2 RMII REFCLK */
+	/* PC15 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_3      */
+	/* PC14 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_2      */
+	/* PC13 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_1      */
+	/* PC12 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_0      */
+	/* PC11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1176           */
+	/* PC10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1177           */
+	/* PC9  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_3      */
+	/* PC8  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_2      */
+	/* PC7  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_1      */
+	/* PC6  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_0      */
+	/* PC5  */ { 1,   1,   0,   1,   0,   0 }, /* SMC1   TXD              */
+	/* PC4  */ { 1,   1,   0,   0,   0,   0 }, /* SMC1   RXD              */
+	/* PC3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC1  */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1192           */
+	/* PC0  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    RACK             */
+    },
+
+    /* Port D */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PD31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1193           */
+	/* PD30 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1194           */
+	/* PD29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1195           */
+	/* PD28 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD27 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD26 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1179           */
+	/* PD24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1180           */
+	/* PD23 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1181           */
+	/* PD22 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1TXD            */
+	/* PD21 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1RXD            */
+	/* PD20 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_A2 L1RSYNC          */
+	/* PD19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1196           */
+	/* PD18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1197           */
+	/* PD17 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1198           */
+	/* PD16 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1199           */
+	/* PD15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1250           */
+	/* PD14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1251           */
+	/* PD13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD7  */ { 0,   0,   0,   1,   0,   0 }, /* GPO    FL_BYTE          */
+	/* PD6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    }
+};
+
+void reset_phy (void)
+{
+	volatile ioport_t *iop;
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	int i;
+	unsigned short val;
+#endif
+
+	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+
+	/* Reset the PHY */
+	iop->pdat &= 0xfff7ffff;	/* PA12 = |SWITCH_RESET */
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	udelay(20000);
+	iop->pdat |= 0x00080000;
+	for (i=0; i<100; i++) {
+		udelay(20000);
+		if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) {
+			break;
+		}
+	}
+	/* initialize switch */
+	m88e6060_initialize( CFG_PHY_ADDR );
+#endif
+}
+
+static unsigned long UPMATable[] = {
+	0x8fffec00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, /* Words 0 to 3	*/
+	0x0ffcfc04,  0x3ffdfc00,  0xfffffc01,  0xfffffc01, /* Words 4 to 7	*/
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, /* Words 8 to 11	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 12 to 15	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 16 to 19	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 20 to 23	*/
+	0x8fffec00,  0x00fffc00,  0x00fffc00,  0x00fffc00, /* Words 24 to 27	*/
+	0x0ffffc04,  0xfffffc01,  0xfffffc01,  0xfffffc01, /* Words 28 to 31	*/
+	0xfffffc00,  0xfffffc01,  0xfffffc01,  0xfffffc00, /* Words 32 to 35	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 36 to 39	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 40 to 43	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 44 to 47	*/
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, /* Words 48 to 51	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, /* Words 52 to 55	*/
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, /* Words 56 to 59	*/
+	0xffffec00,  0xffffec04,  0xffffec00,  0xfffffc01  /* Words 60 to 63	*/
+};
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	int i;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+
+#if 0
+	/* CS2-5 - DSP via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#else
+	/* CS7 - DPRAM via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	volatile ioport_t *iop;
+	unsigned char temp;
+#if 0
+	/* DUMP UPMA RAM */
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	unsigned char c;
+	int i;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+
+
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_RARR;
+	for (i = 0; i < 64; i++) {
+		c = *dummy;
+		printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
+		        memctl->memc_mamr,
+		        memctl->memc_mar,
+		        memctl->memc_mdr );
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	/* enable buffers (DSP, DPRAM) */
+	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+	iop->pdat &= 0xfffbffff;	/* PA13 = |EN_M_BCTL1 */
+
+	/* destroy DPRAM magic */
+	*(volatile unsigned char *)0xf0500000 = 0x00;
+
+	/* clear any pending DPRAM irq */
+	temp = *(volatile unsigned char *)0xf05003ff;
+
+	/* write module-id into DPRAM */
+	*(volatile unsigned char *)0xf0500201 = 0x50;
+
+	return 0;
+}
+
+#if defined(CONFIG_HAVE_OWN_RESET)
+int
+do_reset (void *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile ioport_t *iop;
+
+	iop = ioport_addr((immap_t *)CFG_IMMR, 2);
+	iop->pdat |= 0x00002000;	/* PC18 = HW_RESET */
+	return 1;
+}
+#endif	/* CONFIG_HAVE_OWN_RESET */
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile uchar *ramaddr;
+	int i;
+	uchar c;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+	ramaddr = (uchar *) CFG_SDRAM_BASE;
+	c = 0xff;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
+	immap->im_siu_conf.sc_tescr1   = 0x00000000;
+	immap->im_siu_conf.sc_tescr2   = 0x00000000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM;
+
+	/* Precharge all banks */
+	memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
+	*ramaddr = c;
+
+	/* CBR refresh */
+	memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	/* Mode Register write */
+	memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
+	*ramaddr = c;
+
+	/* Refresh enable */
+	memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
+	*ramaddr = c;
+#endif /* CFG_RAMBOOT */
+
+	return (CFG_SDRAM_SIZE);
+}
+
+int checkboard (void)
+{
+#ifdef CONFIG_CLKIN_66MHz
+	puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
+#else
+	puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
+#endif
+	return 0;
+}
diff --git a/board/g2000/Makefile b/board/g2000/Makefile
new file mode 100755
index 0000000..5471d13
--- /dev/null
+++ b/board/g2000/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o strataflash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/g2000/config.mk b/board/g2000/config.mk
new file mode 100755
index 0000000..25b2105
--- /dev/null
+++ b/board/g2000/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd PLU405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
+#TEXT_BASE = 0x00FC0000
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
new file mode 100755
index 0000000..3f78753
--- /dev/null
+++ b/board/g2000/g2000.c
@@ -0,0 +1,312 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+#define MEM_MCOPT1_INIT_VAL     0x00800000
+#define MEM_RTR_INIT_VAL        0x04070000
+#define MEM_PMIT_INIT_VAL       0x07c00000
+#define MEM_MB0CF_INIT_VAL      0x00082001
+#define MEM_MB1CF_INIT_VAL      0x04082000
+#define MEM_SDTR1_INIT_VAL      0x00854005
+#define SDRAM0_CFG_ENABLE       0x80000000
+
+#define CFG_SDRAM_SIZE          0x04000000      /* 64 MB */
+
+int board_early_init_f (void)
+{
+#if 0 /* test-only */
+	mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+	mtdcr (uicer, 0x00000000);      /* disable all ints */
+	mtdcr (uiccr, 0x00000010);
+	mtdcr (uicpr, 0xFFFF7FF0);      /* set int polarities */
+	mtdcr (uictr, 0x00000010);      /* set int trigger levels */
+	mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+#else
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFFF0);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+#endif
+
+#if 1 /* test-only */
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000); /* ebc always driven */
+#endif
+
+	return 0;
+}
+
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+	/*
+	 * Set NAND-FLASH GPIO signals to default
+	 */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+#endif
+
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming G2000");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+
+/* -------------------------------------------------------------------------
+  G2000 rev B is an embeded design. we don't read for spd of this version.
+  Doing static SDRAM controller configuration in the following section.
+   ------------------------------------------------------------------------- */
+
+long int init_sdram_static_settings(void)
+{
+#define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+	/* disable memcontroller so updates work */
+	mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
+	mtsdram0( mem_rtr   , MEM_RTR_INIT_VAL   );
+	mtsdram0( mem_pmit  , MEM_PMIT_INIT_VAL  );
+	mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL );
+	mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL );
+	mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL );
+
+	/* SDRAM have a power on delay,  500 micro should do */
+	udelay(500);
+	mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
+
+	return (CFG_SDRAM_SIZE); /* CFG_SDRAM_SIZE is in G2000.h */
+ }
+
+
+long int initdram (int board_type)
+{
+	long int ret;
+
+/* flzt, we can still turn this on in the future */
+/* #ifdef CONFIG_SPD_EEPROM
+	ret = spd_sdram ();
+#else
+	ret = init_sdram_static_settings();
+#endif
+*/
+
+	ret = init_sdram_static_settings();
+
+	return ret;
+}
+
+
+#if 1 /* test-only */
+void sdram_init(void)
+{
+	init_sdram_static_settings();
+}
+#endif
+
+
+#if 0 /* test-only */
+long int initdram (int board_type)
+{
+	unsigned long val;
+
+	mtdcr(memcfga, mem_mb0cf);
+	val = mfdcr(memcfgd);
+
+#if 0
+	printf("\nmb0cf=%x\n", val); /* test-only */
+	printf("strap=%x\n", mfdcr(strap)); /* test-only */
+#endif
+
+	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
+}
+#endif
+
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 16 MB - ok\n");
+
+	return (0);
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	nand_probe(CFG_NAND_BASE);
+	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+	}
+}
+#endif
+
+
+#if 0 /* test-only !!! */
+int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong ap, cr;
+
+	printf("\nEBC registers for PPC405GP:\n");
+	mfebc(pb0ap, ap); mfebc(pb0cr, cr);
+	printf("0: AP=%08lx CP=%08lx\n", ap, cr);
+	mfebc(pb1ap, ap); mfebc(pb1cr, cr);
+	printf("1: AP=%08lx CP=%08lx\n", ap, cr);
+	mfebc(pb2ap, ap); mfebc(pb2cr, cr);
+	printf("2: AP=%08lx CP=%08lx\n", ap, cr);
+	mfebc(pb3ap, ap); mfebc(pb3cr, cr);
+	printf("3: AP=%08lx CP=%08lx\n", ap, cr);
+	mfebc(pb4ap, ap); mfebc(pb4cr, cr);
+	printf("4: AP=%08lx CP=%08lx\n", ap, cr);
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	dumpebc,	1,	1,	do_dumpebc,
+	"dumpebc - Dump all EBC registers\n",
+	NULL
+);
+
+
+int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i;
+
+	printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
+	for (i=0; i<=0x1e0; i++) {
+		if (!(i % 0x8)) {
+			printf("\n%04x ", i);
+		}
+		printf("%08lx ", get_dcr(i));
+	}
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	dumpdcr,	1,	1,	do_dumpdcr,
+	"dumpdcr - Dump all DCR registers\n",
+	NULL
+);
+
+
+int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
+	printf("\n%04x %08x ", 947, mfspr(947));
+	printf("\n%04x %08x ", 9, mfspr(9));
+	printf("\n%04x %08x ", 1014, mfspr(1014));
+	printf("\n%04x %08x ", 1015, mfspr(1015));
+	printf("\n%04x %08x ", 1010, mfspr(1010));
+	printf("\n%04x %08x ", 957, mfspr(957));
+	printf("\n%04x %08x ", 1008, mfspr(1008));
+	printf("\n%04x %08x ", 1018, mfspr(1018));
+	printf("\n%04x %08x ", 954, mfspr(954));
+	printf("\n%04x %08x ", 950, mfspr(950));
+	printf("\n%04x %08x ", 951, mfspr(951));
+	printf("\n%04x %08x ", 981, mfspr(981));
+	printf("\n%04x %08x ", 980, mfspr(980));
+	printf("\n%04x %08x ", 982, mfspr(982));
+	printf("\n%04x %08x ", 1012, mfspr(1012));
+	printf("\n%04x %08x ", 1013, mfspr(1013));
+	printf("\n%04x %08x ", 948, mfspr(948));
+	printf("\n%04x %08x ", 949, mfspr(949));
+	printf("\n%04x %08x ", 1019, mfspr(1019));
+	printf("\n%04x %08x ", 979, mfspr(979));
+	printf("\n%04x %08x ", 8, mfspr(8));
+	printf("\n%04x %08x ", 945, mfspr(945));
+	printf("\n%04x %08x ", 987, mfspr(987));
+	printf("\n%04x %08x ", 287, mfspr(287));
+	printf("\n%04x %08x ", 953, mfspr(953));
+	printf("\n%04x %08x ", 955, mfspr(955));
+	printf("\n%04x %08x ", 272, mfspr(272));
+	printf("\n%04x %08x ", 273, mfspr(273));
+	printf("\n%04x %08x ", 274, mfspr(274));
+	printf("\n%04x %08x ", 275, mfspr(275));
+	printf("\n%04x %08x ", 260, mfspr(260));
+	printf("\n%04x %08x ", 276, mfspr(276));
+	printf("\n%04x %08x ", 261, mfspr(261));
+	printf("\n%04x %08x ", 277, mfspr(277));
+	printf("\n%04x %08x ", 262, mfspr(262));
+	printf("\n%04x %08x ", 278, mfspr(278));
+	printf("\n%04x %08x ", 263, mfspr(263));
+	printf("\n%04x %08x ", 279, mfspr(279));
+	printf("\n%04x %08x ", 26, mfspr(26));
+	printf("\n%04x %08x ", 27, mfspr(27));
+	printf("\n%04x %08x ", 990, mfspr(990));
+	printf("\n%04x %08x ", 991, mfspr(991));
+	printf("\n%04x %08x ", 956, mfspr(956));
+	printf("\n%04x %08x ", 284, mfspr(284));
+	printf("\n%04x %08x ", 285, mfspr(285));
+	printf("\n%04x %08x ", 986, mfspr(986));
+	printf("\n%04x %08x ", 984, mfspr(984));
+	printf("\n%04x %08x ", 256, mfspr(256));
+	printf("\n%04x %08x ", 1, mfspr(1));
+	printf("\n%04x %08x ", 944, mfspr(944));
+	printf("\n");
+
+	return 0;
+}
+U_BOOT_CMD(
+	dumpspr,	1,	1,	do_dumpspr,
+	"dumpspr - Dump all SPR registers\n",
+	NULL
+);
+#endif
diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c
new file mode 100755
index 0000000..8446e02
--- /dev/null
+++ b/board/g2000/strataflash.c
@@ -0,0 +1,793 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+#define FLASH_MAN_CFI			0x01000000
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+#if 0 /* test-only */
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#else
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       - CFG_MONITOR_LEN,
+		       - 1, &flash_info[1]);
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		int k;
+		int size;
+		int erased;
+		volatile unsigned long *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+		printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			if (len & 0x1) { /* test-only: unaligned size */
+				puts("\nUnalgined size!!!\n"); /* test-only */
+				cnt++;
+			}
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/g2000/u-boot.lds b/board/g2000/u-boot.lds
new file mode 100755
index 0000000..43f7765
--- /dev/null
+++ b/board/g2000/u-boot.lds
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/gcplus/Makefile b/board/gcplus/Makefile
new file mode 100755
index 0000000..1954d66
--- /dev/null
+++ b/board/gcplus/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# 2003 (c) MontaVista Software, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= gcplus.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/gcplus/config.mk b/board/gcplus/config.mk
new file mode 100755
index 0000000..57326b8
--- /dev/null
+++ b/board/gcplus/config.mk
@@ -0,0 +1,13 @@
+#
+# ADS GCPlus board with SA1110 cpu
+#
+# The ADS GCPlus has 2 banks of 16 MiB SDRAM
+#
+# We use the ADS GCPlus Linux boot ROM to load U-Boot into SDRAM
+# at c020'0000 and then move ourself to c8f0'0000. Basically, just
+# install the U-Boot binary as you would the Linux zImage and then
+# reap the benfits of more convenient Linux development cycles, i.e.
+# bootp;tftp;bootm, repeat, etc.,.
+#
+
+TEXT_BASE = 0xc8f00000
diff --git a/board/gcplus/flash.c b/board/gcplus/flash.c
new file mode 100755
index 0000000..36d7363
--- /dev/null
+++ b/board/gcplus/flash.c
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * 2003 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)				__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)				__swab32(x)
+#endif
+
+#define FPW				FLASH_PORT_WIDTH
+#define FPWV				FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPW * addr, flash_info_t * info);
+static int write_data(flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+void inline spin_wheel(void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init(void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets(PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_FLASH_BASE,
+		      CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf("28F128J3A\n");
+		break;
+	case FLASH_28F640J5:
+		printf("28F640J5\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong
+flash_get_size(FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb();
+	value = addr[1];	/* device ID            */
+	switch (value) {
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;		/* => 16 MB     */
+	case (FPW) INTEL_ID_28F640J5:
+		info->flash_id += FLASH_28F640J5;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf("** ERROR: sector count %d > max (%d) **\n",
+		       info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	start = get_timer(0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+					printf("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf(" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int
+write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_data(flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lX (%lX)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline
+spin_wheel(void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/gcplus/gcplus.c b/board/gcplus/gcplus.c
new file mode 100755
index 0000000..261e894
--- /dev/null
+++ b/board/gcplus/gcplus.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_arch_number = MACH_TYPE_GRAPHICSCLIENT;
+
+	gd->bd->bi_boot_params = 0xc000003c; /* Weird address? */
+
+	/* Most of the ADS GCPlus I/O is connected to Static nCS2.
+	 * So I'm brute forcing nCS2 timiming here for worst case.
+	 */
+	MSC1 &= ~0xFFFF;
+	MSC1 |= 0x8649;
+
+	/* Nothing is connected to Static nCS4 or nCS5. But I'm using
+	 * nCS4 as a paranoia safe guard to force nCS2, nOE; nWE high
+	 * after accessing I/O via (non-VLIO) nCS2. What can I say, I'm
+	 * paranoid and lack decent tools to alleviate my fear. I sure
+	 * do wish I had a logic analyzer. : (
+	 */
+
+	MSC2 =  0xfff9fff9;
+
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return (0);
+}
diff --git a/board/gcplus/lowlevel_init.S b/board/gcplus/lowlevel_init.S
new file mode 100755
index 0000000..f292c4d
--- /dev/null
+++ b/board/gcplus/lowlevel_init.S
@@ -0,0 +1,77 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include "config.h"
+#include "version.h"
+
+
+	.globl	lowlevel_init
+lowlevel_init:
+	/* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
+	 * However the darn thing leaves the MMU enabled before handing control
+	 * over to us. So we need to disable the MMU and we use lowlevel_init
+	 * to do it.
+	 */
+
+@ The following code segment was borrowed with gratitude from:
+@	linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S
+
+	@ Data cache might be active.
+	@ Be sure to flush kernel binary out of the cache,
+	@ whatever state it is, before it is turned off.
+	@ This is done by fetching through currently executed
+	@ memory to be sure we hit the same cache.
+	bic	r2, pc, #0x1f
+	add	r3, r2, #0x4000		@ 16 kb is quite enough...
+1:	ldr	r0, [r2], #32
+	teq	r2, r3
+	bne	1b
+	mcr	p15, 0, r0, c7, c10, 4	@ drain WB
+	mcr	p15, 0, r0, c7, c7, 0	@ flush I & D caches
+
+	@ disabling MMU and caches
+	mrc	p15, 0, r0, c1, c0, 0	@ read control reg
+	bic	r0, r0, #0x0d		@ clear WB, DC, MMU
+	bic	r0, r0, #0x1000		@ clear Icache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	b	2f
+2:
+	nop
+	nop
+	nop
+	nop
+	nop
+
+
+	mov	pc, lr
diff --git a/board/gcplus/u-boot.lds b/board/gcplus/u-boot.lds
new file mode 100755
index 0000000..9900a57
--- /dev/null
+++ b/board/gcplus/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * 2003 (c) MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/sa1100/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile
new file mode 100755
index 0000000..dd7ecf1
--- /dev/null
+++ b/board/gen860t/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o beeper.o fpga.o ioport.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/gen860t/README b/board/gen860t/README
new file mode 100755
index 0000000..7205afb
--- /dev/null
+++ b/board/gen860t/README
@@ -0,0 +1,146 @@
+This directory contains board specific code for a generic MPC860T based
+embedded computer, called 'GEN860T'.  The design is generic in the sense that
+common, readily available components are used and that the architecture of the
+system is relatively straightforward:
+
+	One eight bit wide boot (FLASH) memory
+	32 bit main memory using SDRAM
+	DOC 2000+
+	Ethernet PHY
+	Some I2C peripheral devices: Atmel AT24C256 EEPROM, Maxim DS1337 RTC.
+	Some other miscellaneous peripherals
+
+NOTE: There are references to a XIlinx FPGA and Mil-Std 1553 databus in this
+port.  I guess the computer is not as generic as I first said 8)  However,
+these extras can be safely ignored.
+
+Given the GEN860T files, it should be pretty easy to reverse engineer the
+hardware configuration, if that's useful to you.  Hopefully, this code will
+be useful to someone as a basis for a port to a new system or as a head start
+on a custom design.  If you end up using any of this, I would appreciate
+hearing from you, especially if you discover bugs or find ways to improve the
+quality of this U-Boot port.
+
+Here are the salient features of the system:
+Clock						:	33.3 Mhz oscillator
+Processor core frequency	:	66.6 Mhz  if in 1:2:1 mode; can also run 1:1
+Bus frequency				:	33.3 Mhz
+
+Main memory:
+	Type	: SDRAM
+	Width	: 32 bits
+	Size	: 64 mibibytes
+	Chip	: Two Micron MT48LC16M16A2TG-7E
+	CS		: MPC860T CS1*/UPMA
+	UPMA CONNECTIONS:
+		SDRAM A10	: GPLA0*
+		SDRAM CAS*	: GPLA2*
+		SDRAM WE*	: GPLA3*
+		SDRAM RAS*	: GPLA4*
+
+Boot memory:
+	Type	: FLASH
+	Width	: 8 bits
+	Size	: 16 mibibytes
+	Chip	: One Intel 28F128J3A (StrataFlash)
+	CS		: MPC860T CS0*/GPCM (this is the "boot" chip select)
+
+EEPROM memory:
+	Type	: Serial I2C EEPROM
+	Width	: 8 bits
+	Size	: 32 kibibytes
+	Chip	: One Atmel AT25C256
+	CS		: 0x50 (external I2C address pins on device are tied to GND)
+
+Filesystem memory:
+	Type	: NAND FLASH (Toshiba)
+	Width	: 8 bits (i.e. interface to DOC is 8 bits)
+	Size	: 32 mibibytes
+	Chip	: One DiskOnCHip Millenium Plus (DOC 2000+)
+	CS		: MPC860T CS2*/GPCM
+
+Network support:
+	MAC		: MPC86OT FEC (Fast Ethernet Controller)
+	PHY		: Intel LXT971A
+	MII Addr: 0x0 (hardwired on the board)
+	MII IRQ	:
+
+Console:
+	RS-232 on SMC1 (Maxim MAX3232 LVCMOS-RS232 level shifter)
+
+Real Time Clock:
+	Type	: Low power, I2C interface
+	Chip	: Maxim DS1337
+	CS		: Address 0x68 on I2C bus
+
+	The MPC860T's internal RTC has a defect in Mask rev D that increases
+	the current drain on the KAPWR line to 10 mA.  Since this is an
+	unreasonable amount of current draw for a RTC, and Motorola does not
+	plan to fix this in future mask revisions, a serial (I2C) RTC that
+	works has been included instead.  NOTE that the DS1337 can be
+	configured to output a 32768 Hz clock while the main power is on.
+	This clock output has been routed to the MPC860T's EXTAL pin to allow
+	the internal RTC to be used.  NOTE also that due to yet another
+	defect in the rev D mask, the RTC does not operate reliably when the
+	internal RTC divisor is set to use a 32768 Hz reference.  So just use
+	the I2C RTC.
+
+Miscellaneous:
+	Xilinx Virtex FPGA on CS3*/GPCM.
+	Virtex FPGA slave SelectMap interface on cs4*/UPMB.
+	Mil-Std 1553 databus interface on CS5*/GPCM.
+	Audio sounder (beeper) with digital volume control connected to SPKROUT.
+
+SC variant:
+	A reduced-feature version of the GEN860T port is also supported: GEN860T_SC.
+	The 'SC' variant only provides support for the Virtex FPGA, SDRAM main
+	memory, EEPROM and flash memory.  The system clock frequency is reduced
+	to 24 MHz.
+
+Issues:
+	The DOC 2000+ returns 0x40 as its device ID when probed using the method
+	desxribed in the DOC datasheet.  Unfortunately, the U-Boot DOC driver
+	does not recognize this device.  As of this writing, it seems that MTD
+	does not support the DOC 2000+ either.
+
+Status:
+	Everything appears to work except DOC support. As of this writing,
+	David Woodhouse has stated on the MTD mailing list that he has no
+	knowledge of the DOC Millineum Plus and therfore there is no support
+	in MTD for this device.  I wish I had known this sooner :(
+
+The GEN860T board specific files and configuration is based on the work
+of others who have contributed to U-Boot. The copyright and license notices
+of these authors have been retained wherever their code has been reused.
+All new code to support the GEN860T board is:
+
+	(C) Copyright 2001-2003
+	Keith Outwater (keith_outwater@mvis.com)
+
+and the following license applies:
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License as
+published by the Free Software Foundation; either version 2 of
+the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+MA 02111-1307 USA
+
+Thanks to Wolfgang Denk for a great software package and to everyone
+who contributed to its development.
+
+Keith Outwater
+Sr. Staff Engineer
+Microvision, Inc.
+<keith_outwater@mvis.com>
+<outwater@eskimo.com>
+
+vim: set ts=4 sw=4 tw=78:
diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c
new file mode 100755
index 0000000..46fe66b
--- /dev/null
+++ b/board/gen860t/beeper.c
@@ -0,0 +1,213 @@
+/*
+ * (C) Copyright 2002
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include <linux/ctype.h>
+
+/*
+ * Basic beeper support for the GEN860T board.  The GEN860T includes
+ * an audio sounder driven by a Phillips TDA8551 amplifier.  The
+ * TDA8551 features a digital volume control which uses a "trinary"
+ * input (high/high-Z/low) to set volume.  The 860's SPKROUT pin
+ * drives the amplifier input.
+ */
+
+
+/*
+ * Initialize beeper-related hardware. Initialize timer 1 for use with
+ * the beeper. Use 66 Mhz internal clock with prescale of 33 to get
+ * 1 uS period per count.
+ * FIXME: we should really compute the prescale based on the reported
+ * core clock frequency.
+ */
+void
+init_beeper(void)
+{
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+
+	immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1;
+	immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK)
+								 | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN;
+	immap->im_cpmtimer.cpmt_tcn1 = 0;
+	immap->im_cpmtimer.cpmt_ter1 = 0xffff;
+	immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1;
+}
+
+
+/*
+ * Set beeper frequency.  Max allowed frequency is 2.5 KHz.  This limit
+ * is mostly arbitrary, but the beeper isn't really much good beyond this
+ * frequency.
+ */
+void
+set_beeper_frequency(uint frequency)
+{
+#define FREQ_LIMIT	2500
+
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+
+	/*
+	 * Compute timer ticks given desired frequency.  The timer is set up
+	 * to count 0.5 uS per tick and it takes two ticks per cycle (Hz).
+	 */
+	if (frequency > FREQ_LIMIT) frequency = FREQ_LIMIT;
+	frequency = 1000000/frequency;
+	immap->im_cpmtimer.cpmt_trr1 = (ushort)frequency;
+}
+
+
+/*
+ * Turn the beeper on
+ */
+void
+beeper_on(void)
+{
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+
+	immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1;
+}
+
+
+/*
+ * Turn the beeper off
+ */
+void
+beeper_off(void)
+{
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+
+	immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1;
+}
+
+
+/*
+ * Increase or decrease the beeper volume.  Volume can be set
+ * from off to full in 64 steps.  To increase volume, the output
+ * pin is actively driven high, then returned to tristate.
+ * To decrease volume, output a low on the port pin (no need to
+ * change pin mode to tristate) then output a high to go back to
+ * tristate.
+ */
+void
+set_beeper_volume(int steps)
+{
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	int i;
+
+	if (steps >= 0) {
+		for (i = 0; i < (steps >= 64 ? 64 : steps); i++) {
+			immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19);
+			udelay(1);
+			immap->im_cpm.cp_pbodr |= (0x80000000 >> 19);
+			udelay(1);
+		}
+	}
+	else {
+		for (i = 0; i > (steps <= -64 ? -64 : steps); i--) {
+			immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19);
+			udelay(1);
+			immap->im_cpm.cp_pbdat |= (0x80000000 >> 19);
+			udelay(1);
+		}
+	}
+}
+
+
+/*
+ * Check the environment to see if the beeper needs beeping.
+ * Controlled by a sequence of the form:
+ * freq/delta volume/on time/off time;... where:
+ * freq 		= frequency in Hz (0 - 2500)
+ * delta volume = volume steps up or down (-64 <= vol <= 64)
+ * on time		= time in mS
+ * off time		= time in mS
+ *
+ * Return 1 on success, 0 on failure
+ */
+int
+do_beeper(char *sequence)
+{
+#define DELIMITER	';'
+
+int args[4];
+int i;
+int val;
+char *p = sequence;
+char *tp;
+
+	/*
+	 * Parse the control sequence.  This is a really simple parser
+	 * without any real error checking.  You can probably blow it
+	 * up really easily.
+	 */
+	if (*p == '\0' || !isdigit(*p)) {
+		printf("%s:%d: null or invalid string (%s)\n",
+				__FILE__, __LINE__, p);
+		return 0;
+	}
+
+	i = 0;
+	while (*p != '\0') {
+		while (*p != DELIMITER) {
+			if (i > 3) i = 0;
+			val = (int) simple_strtol(p, &tp, 0);
+			if (tp == p) {
+				printf("%s:%d: no digits or bad format\n",
+								__FILE__,__LINE__);
+				return 0;
+			}
+			else {
+				args[i] = val;
+			}
+
+			i++;
+			if (*tp == DELIMITER)
+				p = tp;
+			else
+				p = ++tp;
+		}
+		p++;
+
+		/*
+		 * Well, we got something that has a chance of being correct
+		 */
+#if 0
+		for (i = 0; i < 4; i++) {
+			printf("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, args[i]);
+		}
+		printf("\n");
+#endif
+
+		set_beeper_frequency(args[0]);
+		set_beeper_volume(args[1]);
+		beeper_on();
+		udelay(1000 * args[2]);
+		beeper_off();
+		udelay(1000 * args[3]);
+	}
+	return 1;
+}
+
+/* vim: set ts=4 sw=4 tw=78: */
diff --git a/board/gen860t/beeper.h b/board/gen860t/beeper.h
new file mode 100755
index 0000000..535ee6c
--- /dev/null
+++ b/board/gen860t/beeper.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2002
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+void init_beeper(void);
+void set_beeper_frequency(uint frequency);
+void beeper_on(void);
+void beeper_off(void);
+void set_beeper_volume(int steps);
+int do_beeper(char *sequence);
+
+/* vim: set ts=4 tw=78 sw=4: */
diff --git a/board/gen860t/config.mk b/board/gen860t/config.mk
new file mode 100755
index 0000000..7acd904
--- /dev/null
+++ b/board/gen860t/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# FLASH base address for GEN860T board
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c
new file mode 100755
index 0000000..ec32d07
--- /dev/null
+++ b/board/gen860t/flash.c
@@ -0,0 +1,644 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvsi.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*
+ * Use buffered writes to flash by default - they are about 32x faster than
+ * single byte writes.
+ */
+#ifndef  CFG_GEN860T_FLASH_USE_WRITE_BUFFER
+#define CFG_GEN860T_FLASH_USE_WRITE_BUFFER
+#endif
+
+/*
+ * Max time to wait (in mS) for flash device to allocate a write buffer.
+ */
+#ifndef CFG_FLASH_ALLOC_BUFFER_TOUT
+#define CFG_FLASH_ALLOC_BUFFER_TOUT		100
+#endif
+
+/*
+ * These functions support a single Intel StrataFlash device (28F128J3A)
+ * in byte mode only!.  The flash routines are very basic and simple
+ * since there isn't really any remapping necessary.
+ */
+
+/*
+ * Intel SCS (Scalable Command Set) command definitions
+ * (taken from 28F128J3A datasheet)
+ */
+#define SCS_READ_CMD				0xff
+#define SCS_READ_ID_CMD				0x90
+#define SCS_QUERY_CMD				0x98
+#define SCS_READ_STATUS_CMD			0x70
+#define SCS_CLEAR_STATUS_CMD		0x50
+#define SCS_WRITE_BUF_CMD			0xe8
+#define SCS_PROGRAM_CMD				0x40
+#define SCS_BLOCK_ERASE_CMD			0x20
+#define SCS_BLOCK_ERASE_RESUME_CMD	0xd0
+#define SCS_PROGRAM_RESUME_CMD		0xd0
+#define SCS_BLOCK_ERASE_SUSPEND_CMD	0xb0
+#define SCS_SET_BLOCK_LOCK_CMD		0x60
+#define SCS_CLR_BLOCK_LOCK_CMD		0x60
+
+/*
+ * SCS status/extended status register bit definitions
+ */
+#define  SCS_SR7					0x80
+#define  SCS_XSR7					0x80
+
+/*---------------------------------------------------------------------*/
+#if 0
+#define DEBUG_FLASH
+#endif
+
+#ifdef DEBUG_FLASH
+#define PRINTF(fmt,args...) printf(fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_data8 (flash_info_t *info, ulong dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ * Initialize the flash memory.
+ */
+unsigned long
+flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	for (i= 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/*
+	 * The gen860t board only has one FLASH memory device, so the
+	 * FLASH Bank configuration is done statically.
+	 */
+	PRINTF("\n## Get flash bank 1 size @ 0x%08x\n", FLASH_BASE0_PRELIM);
+	size_b0 = flash_get_size((vu_char *)FLASH_BASE0_PRELIM, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+				"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+				flash_info[0].flash_id,size_b0, size_b0 << 20);
+	}
+
+	PRINTF("## Before remap:\n"
+		   "  BR0: 0x%08x    OR0: 0x%08x\n  BR1: 0x%08x    OR1: 0x%08x\n",
+		   memctl->memc_br0, memctl->memc_or0,
+		   memctl->memc_br1, memctl->memc_or1);
+
+	/*
+	 * Remap FLASH according to real size
+	 */
+	memctl->memc_or0 |= (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 |= (CFG_FLASH_BASE & BR_BA_MSK);
+
+	PRINTF("## After remap:\n"
+		   "  BR0: 0x%08x    OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0);
+
+	/*
+	 * Re-do sizing to get full correct info
+	 */
+	size_b0 = flash_get_size ((vu_char *)CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/*
+	 * Monitor protection is ON by default
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      	  CFG_MONITOR_BASE,
+		      	  CFG_MONITOR_BASE + monitor_flash_len - 1,
+		      	  &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/*
+	 * Environment protection ON by default
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      	  CFG_ENV_ADDR,
+		      	  CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+		      	  &flash_info[0]);
+#endif
+
+	PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0);
+	return (size_b0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Fill in the FLASH offset table
+ */
+static void
+flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:
+	    	for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				base += 1024 * 128;
+	    	}
+	    	return;
+
+		default:
+	   		printf ("Don't know sector offsets for FLASH"
+			        " type 0x%lx\n", info->flash_id);
+	    return;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * Display FLASH device info
+ */
+void
+flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+			printf ("Intel ");
+			break;
+	default:
+			printf ("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+			printf ("28F128J3A (128Mbit = 128K x 128)\n");
+			break;
+	default:
+			printf ("Unknown Chip Type\n");
+			break;
+	}
+
+	if (info->size >= (1024 * 1024)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+			info->size >> i,
+			(i == 20) ? 'M' : 'k',
+			info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+			printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Get size and other information for a FLASH device.
+ * NOTE: The following code cannot be run from FLASH!
+ */
+static
+ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+#define NO_FLASH	0
+
+	vu_char value[2];
+
+	/*
+	 * Try to read the manufacturer ID
+	 */
+	addr[0] = SCS_READ_CMD;
+	addr[0] = SCS_READ_ID_CMD;
+	value[0] = addr[0];
+	value[1] = addr[2];
+	addr[0] = SCS_READ_CMD;
+
+	PRINTF("Manuf. ID @ 0x%08lx: 0x%02x\n", (ulong)addr, value[0]);
+	switch (value[0]) {
+		case (INTEL_MANUFACT & 0xff):
+			info->flash_id = FLASH_MAN_INTEL;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (NO_FLASH);
+	}
+
+	/*
+	 * Read the device ID
+	 */
+	PRINTF("Device ID @ 0x%08lx: 0x%02x\n", (ulong)(&addr[2]), value[1]);
+	switch (value[1]) {
+		case (INTEL_ID_28F128J3A & 0xff):
+			info->flash_id += FLASH_28F128J3A;
+			info->sector_count = 128;
+			info->size = 16 * 1024 * 1024;
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (NO_FLASH);
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+				info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Erase the specified sectors in the specified FLASH device
+ */
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	/*
+	 * Start erase on unprotected sectors
+	 */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_char *addr = (uchar *)(info->start[sect]);
+			vu_char status;
+
+			/*
+			 * Disable interrupts which might cause a timeout
+			 */
+			flag = disable_interrupts();
+
+			*addr = SCS_CLEAR_STATUS_CMD;
+			*addr = SCS_BLOCK_ERASE_CMD;
+			*addr = SCS_BLOCK_ERASE_RESUME_CMD;
+
+			/*
+			 * Re-enable interrupts if necessary
+			 */
+			if (flag)
+				enable_interrupts();
+
+			/*
+			 * Wait at least 80us - let's wait 1 ms
+			 */
+			udelay (1000);
+
+			while (((status = *addr) & SCS_SR7) != SCS_SR7) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = SCS_BLOCK_ERASE_SUSPEND_CMD;
+					*addr = SCS_READ_CMD;
+					return 1;
+				}
+
+				/*
+				 * Show that we're waiting
+				 */
+				if ((now - last) > 1000) {	/* 1 second */
+					putc ('.');
+					last = now;
+				}
+			}
+			*addr = SCS_READ_CMD;
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+
+#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER
+/*
+ * Allocate a flash buffer, fill it with data and write it to the flash.
+ * 0 - OK
+ * 1 - Timeout on buffer request
+ *
+ * NOTE: After the last call to this function, WSM status needs to be checked!
+ */
+static int
+write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p,
+				    uint count)
+{
+	vu_char *block_addr_p = NULL;
+	vu_char *start_addr_p = NULL;
+	ulong blocksize = info_p->size / (ulong)info_p->sector_count;
+
+	int i;
+	uint time = get_timer(0);
+
+	PRINTF("%s:%d: src: 0x%p dest: 0x%p  count: %d\n",
+		   __FUNCTION__, __LINE__, src_p, dest_p, count);
+
+	/*
+	 * What block are we in? We already know that the source address is
+	 * in the flash address range, but we also can't cross a block boundary.
+	 * We assume that the block does not cross a boundary (we'll check before
+	 * calling this function).
+	 */
+ 	for (i = 0; i < info_p->sector_count; ++i) {
+		if ( ((ulong)dest_p >= info_p->start[i]) &&
+		    ((ulong)dest_p < (info_p->start[i] + blocksize)) ) {
+			PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n",
+				   __FUNCTION__, __LINE__, dest_p, i, info_p->start[i]);
+			block_addr_p = (vu_char *)info_p->start[i];
+			break;
+		}
+	}
+
+	/*
+	 * Request a buffer
+	 */
+	*block_addr_p = SCS_WRITE_BUF_CMD;
+	while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) {
+		if (get_timer(time) >  CFG_FLASH_ALLOC_BUFFER_TOUT) {
+			PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n",
+				   __FUNCTION__, __LINE__, block_addr_p,
+				   CFG_FLASH_ALLOC_BUFFER_TOUT);
+			return 1;
+		}
+		*block_addr_p = SCS_WRITE_BUF_CMD;
+	}
+
+	/*
+	 * Fill the buffer with data
+	 */
+	start_addr_p = dest_p;
+	*block_addr_p = count - 1; /* flash device wants count - 1 */
+	PRINTF("%s:%d: Fill buffer at block addr 0x%p\n",
+		   __FUNCTION__, __LINE__, block_addr_p);
+	for (i = 0; i < count; i++) {
+		*start_addr_p++ = *src_p++;
+	}
+
+	/*
+	 * Flush buffer to flash
+	 */
+	*block_addr_p = SCS_PROGRAM_RESUME_CMD;
+#if 1
+	time = get_timer(0);
+	while ((*block_addr_p & SCS_SR7) != SCS_SR7) {
+		if (get_timer(time) >  CFG_FLASH_WRITE_TOUT) {
+			PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n",
+				   __FUNCTION__, __LINE__, block_addr_p, CFG_FLASH_WRITE_TOUT);
+			return 1;
+		}
+	}
+
+#endif
+	return 0;
+}
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+int
+write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count)
+{
+	int rc = 0;
+#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER
+#define FLASH_WRITE_BUF_SIZE	0x00000020	/* 32 bytes */
+	int i;
+	uint bufs;
+	ulong buf_count;
+	vu_char *sp;
+	vu_char *dp;
+#else
+	ulong wp;
+#endif
+
+	PRINTF("\n%s:%d: src: 0x%.8lx dest: 0x%.8lx size: %d (0x%.8lx)\n",
+		   __FUNCTION__, __LINE__, (ulong)src_p, addr, (uint)count, count);
+
+	if (info_p->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER
+	sp = src_p;
+	dp = (uchar *)addr;
+
+	/*
+	 * For maximum performance, we want to align the start address to
+	 * the beginning of a write buffer boundary (i.e. A4-A0 of the
+	 * start address = 0). See how many bytes are required to get to a
+	 * write-buffer-aligned address.  If that number is non-zero, do
+	 * non buffered writes of the non-aligned data.  By doing non-buffered
+	 * writes, we avoid the problem of crossing a block (sector) boundary
+	 * with buffered writes.
+	 */
+	buf_count = FLASH_WRITE_BUF_SIZE - (addr & (FLASH_WRITE_BUF_SIZE - 1));
+	if (buf_count == FLASH_WRITE_BUF_SIZE) { /* already on a boundary */
+		buf_count = 0;
+	}
+	if (buf_count > count) { /* not a full buffers worth of data to write */
+		buf_count = count;
+	}
+	count -= buf_count;
+
+	PRINTF("%s:%d: Write buffer alignment count = %ld\n",
+		   __FUNCTION__, __LINE__, buf_count);
+	while (buf_count-- >= 1) {
+		if ((rc = write_data8(info_p, (ulong)dp++, *sp++)) != 0)  {
+			return (rc);
+		}
+	}
+
+	PRINTF("%s:%d: count = %ld\n", __FUNCTION__, __LINE__, count);
+	if (count == 0) { /* all done */
+		PRINTF("%s:%d: Less than 1 buffer (%d) worth of bytes\n",
+			   __FUNCTION__, __LINE__, FLASH_WRITE_BUF_SIZE);
+		return (rc);
+	}
+
+	/*
+	 * Now that we are write buffer aligned, write full or partial buffers.
+	 * The fact that we are write buffer aligned automatically avoids
+	 * crossing a block address during a write buffer operation.
+	 */
+	bufs = count / FLASH_WRITE_BUF_SIZE;
+	PRINTF("%s:%d: %d (0x%x) buffers to write\n", __FUNCTION__, __LINE__,
+		   bufs, bufs);
+	while (bufs >= 1) {
+		rc = write_flash_buffer8(info_p, sp, dp, FLASH_WRITE_BUF_SIZE);
+		if (rc != 0) {
+			PRINTF("%s:%d: ** Error writing buf %d\n",
+				   __FUNCTION__, __LINE__, bufs);
+			return (rc);
+		}
+		bufs--;
+		sp += FLASH_WRITE_BUF_SIZE;
+		dp += FLASH_WRITE_BUF_SIZE;
+	}
+
+	/*
+	 * Do the leftovers
+	 */
+	i = count % FLASH_WRITE_BUF_SIZE;
+	PRINTF("%s:%d: %d (0x%x) leftover bytes\n", __FUNCTION__, __LINE__, i, i);
+	if (i > 0) {
+		rc = write_flash_buffer8(info_p, sp, dp, i);
+	}
+
+	sp = (vu_char*)info_p->start[0];
+	*sp = SCS_READ_CMD;
+	return (rc);
+
+#else
+	wp = addr;
+	while (count-- >= 1) {
+		if((rc = write_data8(info_p, wp++, *src_p++)) != 0)
+			return (rc);
+	}
+	return 0;
+#endif
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_data8 (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)dest;
+	vu_char status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = SCS_PROGRAM_CMD;
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & SCS_SR7) != SCS_SR7) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = SCS_READ_CMD;
+			return (1);
+		}
+	}
+	*addr = SCS_READ_CMD;
+	return (0);
+}
+
+/* vim: set ts=4 sw=4 tw=78: */
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
new file mode 100755
index 0000000..37788d5
--- /dev/null
+++ b/board/gen860t/fpga.c
@@ -0,0 +1,380 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Virtex2 FPGA configuration support for the GEN860T computer
+ */
+
+#include <common.h>
+#include <virtex2.h>
+#include <command.h>
+#include "fpga.h"
+
+#if (CONFIG_FPGA)
+
+#if 0
+#define GEN860T_FPGA_DEBUG
+#endif
+
+#ifdef GEN860T_FPGA_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define	PRINTF(fmt,args...)
+#endif
+
+/*
+ * Port bit numbers for the Selectmap controls
+ */
+#define FPGA_INIT_BIT_NUM		22	/* PB22 */
+#define FPGA_RESET_BIT_NUM		11	/* PC11 */
+#define FPGA_DONE_BIT_NUM		16	/* PB16 */
+#define FPGA_PROGRAM_BIT_NUM	7	/* PA7  */
+
+/* Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ */
+Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_init_fn,
+	fpga_err_fn,
+	fpga_done_fn,
+	fpga_clk_fn,
+	fpga_cs_fn,
+	fpga_wr_fn,
+	fpga_read_data_fn,
+	fpga_write_data_fn,
+	fpga_busy_fn,
+	fpga_abort_fn,
+	fpga_post_config_fn
+};
+
+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+	{Xilinx_Virtex2,
+	 slave_selectmap,
+	 XILINX_XC2V3000_SIZE,
+	 (void *) &fpga_fns,
+	 0}
+};
+
+/*
+ * Display FPGA revision information
+ */
+void print_fpga_revision (void)
+{
+	vu_long *rev_p = (vu_long *) 0x60000008;
+
+	printf ("FPGA Revision 0x%.8lx"
+		" (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
+		*rev_p,
+		((*rev_p >> 28) & 0xf),
+		((*rev_p >> 20) & 0xff),
+		((*rev_p >> 12) & 0xff),
+		((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
+}
+
+
+/*
+ * Perform a simple test of the FPGA to processor interface using the FPGA's
+ * inverting bus test register.  The great thing about doing a read/write
+ * test on a register that inverts it's contents is that you avoid any
+ * problems with bus charging.
+ * Return 0 on failure, 1 on success.
+ */
+int test_fpga_ibtr (void)
+{
+	vu_long *ibtr_p = (vu_long *) 0x60000010;
+	vu_long readback;
+	vu_long compare;
+	int i;
+	int j;
+	int k;
+	int pass = 1;
+
+	static const ulong bitpattern[] = {
+		0xdeadbeef,	/* magic ID pattern for debug   */
+		0x00000001,	/* single bit                                   */
+		0x00000003,	/* two adjacent bits                    */
+		0x00000007,	/* three adjacent bits                  */
+		0x0000000F,	/* four adjacent bits                   */
+		0x00000005,	/* two non-adjacent bits                */
+		0x00000015,	/* three non-adjacent bits              */
+		0x00000055,	/* four non-adjacent bits               */
+		0xaaaaaaaa,	/* alternating 1/0                              */
+	};
+
+	for (i = 0; i < 1024; i++) {
+		for (j = 0; j < 31; j++) {
+			for (k = 0;
+			     k < sizeof (bitpattern) / sizeof (bitpattern[0]);
+			     k++) {
+				*ibtr_p = compare = (bitpattern[k] << j);
+				readback = *ibtr_p;
+				if (readback != ~compare) {
+					printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
+					pass = 0;
+					break;
+				}
+			}
+			if (!pass)
+				break;
+		}
+		if (!pass)
+			break;
+	}
+	if (pass) {
+		printf ("FPGA inverting bus test passed\n");
+		print_fpga_revision ();
+	} else {
+		printf ("** FPGA inverting bus test failed\n");
+	}
+	return pass;
+}
+
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+void fpga_reset (int assert)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
+	if (assert) {
+		immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
+		PRINTF ("asserted\n");
+	} else {
+		immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
+		PRINTF ("deasserted\n");
+	}
+}
+
+
+/*
+ * Initialize the SelectMap interface.  We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+void fpga_selectmap_init (void)
+{
+	PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
+		__LINE__);
+	fpga_pgm_fn (FALSE, FALSE, 0);	/* make sure program pin is inactive */
+}
+
+
+/*
+ * Initialize the fpga.  Return 1 on success, 0 on failure.
+ */
+int gen860t_init_fpga (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int i;
+
+	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
+	fpga_init (gd->reloc_off);
+	fpga_selectmap_init ();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
+		fpga_add (fpga_xilinx, &fpga[i]);
+	}
+	return 1;
+}
+
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+int fpga_pgm_fn (int assert, int flush, int cookie)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
+
+	if (assert) {
+		immap->im_ioport.iop_padat &=
+			~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("asserted\n");
+	} else {
+		immap->im_ioport.iop_padat |=
+			(0x8000 >> FPGA_PROGRAM_BIT_NUM);
+		PRINTF ("deasserted\n");
+	}
+	return assert;
+}
+
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn (int cookie)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
+	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
+		PRINTF ("high\n");
+		return 0;
+	} else {
+		PRINTF ("low\n");
+		return 1;
+	}
+}
+
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn (int cookie)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
+	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
+		PRINTF ("high\n");
+		return FPGA_SUCCESS;
+	} else {
+		PRINTF ("low\n");
+		return FPGA_FAIL;
+	}
+}
+
+
+/*
+ * Read FPGA SelectMap data.
+ */
+int fpga_read_data_fn (unsigned char *data, int cookie)
+{
+	vu_char *p = (vu_char *) SELECTMAP_BASE;
+
+	*data = *p;
+#if 0
+	PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
+#endif
+	return (int) data;
+}
+
+
+/*
+ * Write data to the FPGA SelectMap port
+ */
+int fpga_write_data_fn (unsigned char data, int flush, int cookie)
+{
+	vu_char *p = (vu_char *) SELECTMAP_BASE;
+
+#if 0
+	PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
+#endif
+	*p = data;
+	return (int) data;
+}
+
+
+/*
+ * Abort and FPGA operation
+ */
+int fpga_abort_fn (int cookie)
+{
+	PRINTF ("%s:%d: FPGA program sequence aborted\n",
+		__FUNCTION__, __LINE__);
+	return FPGA_FAIL;
+}
+
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+int fpga_pre_config_fn (int cookie)
+{
+	PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
+	return 0;
+}
+
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+int fpga_post_config_fn (int cookie)
+{
+	int rc;
+
+	PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
+	fpga_reset (TRUE);
+	udelay (1000);
+	fpga_reset (FALSE);
+	udelay (1000);
+
+	/*
+	 * Use the FPGA,s inverting bus test register to do a simple test of the
+	 * processor interface.
+	 */
+	rc = test_fpga_ibtr ();
+	return rc;
+}
+
+
+/*
+ * Clock, chip select and write signal assert functions and error check
+ * and busy functions.  These are only stubs because the GEN860T selectmap
+ * interface handles sequencing of control signals automatically (it uses
+ * a memory-mapped interface to the FPGA SelectMap port).  The design of
+ * the interface guarantees that the SelectMap port cannot be overrun so
+ * no busy check is needed.  A configuration error is signalled by INIT
+ * going low during configuration, so there is no need for a separate error
+ * function.
+ */
+int fpga_clk_fn (int assert_clk, int flush, int cookie)
+{
+	return assert_clk;
+}
+
+int fpga_cs_fn (int assert_cs, int flush, int cookie)
+{
+	return assert_cs;
+}
+
+int fpga_wr_fn (int assert_write, int flush, int cookie)
+{
+	return assert_write;
+}
+
+int fpga_err_fn (int cookie)
+{
+	return 0;
+}
+
+int fpga_busy_fn (int cookie)
+{
+	return 0;
+}
+#endif
+
+/* vim: set ts=4 tw=78 sw=4: */
diff --git a/board/gen860t/fpga.h b/board/gen860t/fpga.h
new file mode 100755
index 0000000..01967a4
--- /dev/null
+++ b/board/gen860t/fpga.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Virtex2 FPGA configuration support for the GEN860T computer
+ */
+
+extern int gen860t_init_fpga(void);
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_err_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_read_data_fn(unsigned char *data, int cookie);
+extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
+extern int fpga_busy_fn(int cookie);
+extern int fpga_abort_fn(int cookie );
+extern int fpga_pre_config_fn(int cookie );
+extern int fpga_post_config_fn(int cookie );
+
+/* vim: set ts=4 sw=4 tw=78: */
diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c
new file mode 100755
index 0000000..b7a1b56
--- /dev/null
+++ b/board/gen860t/gen860t.c
@@ -0,0 +1,309 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <virtex2.h>
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include "beeper.h"
+#include "fpga.h"
+#include "ioport.h"
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+
+#if defined(CFG_CMD_MII) && defined(CONFIG_MII)
+#include <net.h>
+#endif
+
+#if 0
+#define GEN860T_DEBUG
+#endif
+
+#ifdef GEN860T_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define	PRINTF(fmt,args...)
+#endif
+
+/*
+ * The following UPM init tables were generated automatically by
+ * Motorola's MCUINIT program. See the README file for UPM to
+ * SDRAM pin assignments if you want to type this data into
+ * MCUINIT in order to reverse engineer the waveforms.
+ */
+
+/*
+ * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
+ * (UPMA) and Virtex FPGA SelectMap interface (UPMB).
+ * NOTE that unused areas of the table are used to hold NOP, precharge
+ * and mode register set sequences.
+ *
+ */
+#define	UPMA_NOP_ADDR			0x5
+#define	UPMA_PRECHARGE_ADDR		0x6
+#define UPMA_MRS_ADDR			0x12
+
+#define UPM_SINGLE_READ_ADDR	0x00
+#define UPM_BURST_READ_ADDR		0x08
+#define UPM_SINGLE_WRITE_ADDR	0x18
+#define UPM_BURST_WRITE_ADDR	0x20
+#define	UPM_REFRESH_ADDR		0x30
+
+const uint sdram_upm_table[] = {
+	/* single read   (offset 0x00 in upm ram) */
+	0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
+	0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
+	/* burst read    (offset 0x08 in upm ram) */
+	0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
+	0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
+	0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
+	0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
+	/* single write  (offset 0x18 in upm ram) */
+	0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* burst write   (offset 0x20 in upm ram) */
+	0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
+	0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* refresh       (offset 0x30 in upm ram) */
+	0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
+	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* exception     (offset 0x3C in upm ram) */
+};
+
+const uint selectmap_upm_table[] = {
+	/* single read   (offset 0x00 in upm ram) */
+	0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
+	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* burst read    (offset 0x08 in upm ram) */
+	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* single write  (offset 0x18 in upm ram) */
+	0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* burst write   (offset 0x20 in upm ram) */
+	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* refresh       (offset 0x30 in upm ram) */
+	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+	/* exception     (offset 0x3C in upm ram) */
+	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
+};
+
+/*
+ * Check board identity.  Always successful (gives information only)
+ */
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char *s;
+	char buf[64];
+	int i;
+
+	i = getenv_r ("board_id", buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;
+
+	if (s) {
+		printf ("%s ", s);
+	} else {
+		printf ("<unknown> ");
+	}
+
+	i = getenv_r ("serial#", buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;
+
+	if (s) {
+		printf ("S/N %s\n", s);
+	} else {
+		printf ("S/N <unknown>\n");
+	}
+
+	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
+	printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
+	return (0);
+}
+
+/*
+ * Initialize SDRAM
+ */
+long int initdram (int board_type)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	upmconfig (UPMA,
+		   (uint *) sdram_upm_table,
+		   sizeof (sdram_upm_table) / sizeof (uint)
+		);
+
+	/*
+	 * Setup MAMR register
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	/*
+	 * Map CS1* to SDRAM bank
+	 */
+	memctl->memc_or1 = CFG_OR1;
+	memctl->memc_br1 = CFG_BR1;
+
+	/*
+	 * Perform SDRAM initialization sequence:
+	 * 1. Apply at least one NOP command
+	 * 2. 100 uS delay (JEDEC standard says 200 uS)
+	 * 3. Issue 4 precharge commands
+	 * 4. Perform two refresh cycles
+	 * 5. Program mode register
+	 *
+	 * Program SDRAM for standard operation, sequential burst, burst length
+	 * of 4, CAS latency of 2.
+	 */
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (0) | UPMA_NOP_ADDR;
+	udelay (200);
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;
+
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (2) | UPM_REFRESH_ADDR;
+
+	memctl->memc_mar = 0x00000088;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (1) | UPMA_MRS_ADDR;
+
+	memctl->memc_mar = 0x00000000;
+	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
+		MCR_MLCF (0) | UPMA_NOP_ADDR;
+	/*
+	 * Enable refresh
+	 */
+	memctl->memc_mamr |= MAMR_PTAE;
+
+	return (SDRAM_SIZE);
+}
+
+/*
+ * Disk On Chip (DOC) Millenium initialization.
+ * The DOC lives in the CS2* space
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+
+void doc_init (void)
+{
+	printf ("Probing at 0x%.8x: ", DOC_BASE);
+	doc_probe (DOC_BASE);
+}
+#endif
+
+/*
+ * Miscellaneous intialization
+ */
+int misc_init_r (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	/*
+	 * Set up UPMB to handle the Virtex FPGA SelectMap interface
+	 */
+	upmconfig (UPMB, (uint *) selectmap_upm_table,
+		   sizeof (selectmap_upm_table) / sizeof (uint));
+
+	memctl->memc_mbmr = 0x0;
+
+	config_mpc8xx_ioports (immr);
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+	mii_init ();
+#endif
+
+#if (CONFIG_FPGA)
+	gen860t_init_fpga ();
+#endif
+	return 0;
+}
+
+/*
+ * Final init hook before entering command loop.
+ */
+int last_stage_init (void)
+{
+#if !defined(CONFIG_SC)
+	char buf[256];
+	int i;
+
+	/*
+	 * Turn the beeper volume all the way down in case this is a warm boot.
+	 */
+	set_beeper_volume (-64);
+	init_beeper ();
+
+	/*
+	 * Read the environment to see what to do with the beeper
+	 */
+	i = getenv_r ("beeper", buf, sizeof (buf));
+	if (i > 0) {
+		do_beeper (buf);
+	}
+#endif
+	return 0;
+}
+
+/*
+ * Stub to make POST code happy.  Can't self-poweroff, so just hang.
+ */
+void board_poweroff (void)
+{
+	puts ("### Please power off the board ###\n");
+	while (1);
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed (void)
+{
+	return 0;		/* No hotkeys supported */
+}
+#endif
+
+/* vim: set ts=4 sw=4 tw=78 : */
diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c
new file mode 100755
index 0000000..1fc9545
--- /dev/null
+++ b/board/gen860t/ioport.c
@@ -0,0 +1,347 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include "ioport.h"
+
+#if 0
+#define IOPORT_DEBUG
+#endif
+
+#ifdef  IOPORT_DEBUG
+#define PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+/*
+ * The ioport configuration table.
+ */
+const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
+    /*
+	 * Port A configuration
+	 * Pin	Signal					Type	Active	Initial state
+	 * PA7 	fpgaProgramLowOut		Out		Low			High
+	 * PA1 	fpgaCoreVoltageFailLow	In		Low			N/A
+	 */
+    {	/*	    conf ppar psor pdir podr pdat pint	   function 		*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /* No pin			*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /* No pin			*/
+	/* PA15 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA12 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA11 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA10 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA9  */ { 1,   0,   0,   1,   0,   0,   0 }, /* grn bicolor LED 1*/
+	/* PA8  */ { 1,   0,   0,   1,   0,   0,   0 }, /* red bicolor LED 1*/
+	/* PA7  */ { 1,   0,   0,   1,   0,   1,   0 }, /* fpgaProgramLow	*/
+	/* PA6  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA5  */ { 1,   0,   0,   1,   0,   0,   0 }, /* grn bicolor LED 0*/
+	/* PA4  */ { 1,   0,   0,   1,   0,   0,   0 }, /* red bicolor LED 0*/
+	/* PA3  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PA2  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PA1  */ { 1,   0,   0,   0,   0,   0,   0 }, /*	fpgaCoreVoltageFail*/
+#else
+	/* PA1  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#endif
+	/* PA0  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
+    },
+
+	/*
+	 * Port B configuration
+	 * Pin		Signal			Type		Active		Initial state
+	 * PB14		docBusyLowIn	In			Low			X
+	 * PB15		gpio1Sig		Out			High		Low
+	 * PB16		fpgaDoneBi		In			High		X
+	 * PB17		swBitOkLowOut	Out			Low			High
+	 * PB19		speakerVolSig	Out/Hi-Z	High/Low	High (Hi-Z)
+	 * PB22		fpgaInitLowBi	In			Low			X
+	 * PB23		batteryOkSig	In			High		X
+	 * PB31		pulseCatcherClr	Out			High		0
+	 */
+	{	/*	    conf ppar psor pdir podr pdat pint 	  function			*/
+#if !defined(CONFIG_SC)
+	/* PB31 */ { 0,	  0,   0,   0,   0,   0,   0 }, /*	*/
+#else
+	/* PB31 */ { 1,   0,   0,   1,   0,   0,   0 }, /* pulseCatcherClr	*/
+#endif
+	/* PB30 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB29 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB28 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB27 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB26 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB25 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB24 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PB23 */ { 1,   0,   0,   0,   0,   0,   0 }, /* batteryOk		*/
+#else
+	/* PB23 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#endif
+	/* PB22 */ { 1,   0,   0,   0,   0,   0,   0 }, /* fpgaInitLowBi	*/
+	/* PB21 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB20 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PB19 */ { 1,   0,   0,   1,   1,   1,   0 }, /* speakerVol		*/
+#else
+	/* PB19 */ { 0,   0,   0,   1,   1,   1,   0 }, /*	*/
+#endif
+	/* PB18 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PB17 */ { 1,   0,   0,   1,   0,   1,   0 }, /* swBitOkLow		*/
+	/* PB16 */ { 1,   0,   0,   0,   0,   0,   0 }, /* fpgaDone			*/
+	/* PB15 */ { 1,   0,   0,   1,   0,   0,   0 }, /* gpio1			*/
+#if !defined(CONFIG_SC)
+	/* PB14 */ { 1,   0,   0,   0,   0,   0,   0 }  /* docBusyLow		*/
+#else
+	/* PB14 */ { 0,   0,   0,   0,   0,   0,   0 }  /* 	*/
+#endif
+	},
+
+	/*
+	 * Port C configuration
+	 * Pin		Signal				Type	Active		Initial state
+	 * PC4		i2cBus1EnSig		Out		High		High
+	 * PC5		i2cBus2EnSig		Out		High		High
+	 * PC6		gpio0Sig			Out		High		Low
+	 * PC8		i2cBus3EnSig		Out		High		High
+	 * PC10		i2cBus4EnSig		Out		High		High
+	 * PC11		fpgaResetLowOut		Out		Low			High
+	 * PC12		systemBitOkIn		In		High		X
+	 * PC15		selfDreqLow			In		Low			X
+	 */
+	{	/*	    conf ppar psor pdir podr pdat pint 	  function			*/
+	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A	*/ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PC15 */ { 1,   0,   0,   0,   0,   0,   0 }, /* selfDreqLowIn	*/
+	/* PC14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PC13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PC12 */ { 1,   0,   0,   0,   0,   0,   0 }, /* systemBitOkIn	*/
+#else
+	/* PC12 */ { 0,   0,   0,   0,   0,   0,   0 }, /* 	*/
+#endif
+	/* PC11 */ { 1,   0,   0,   1,   0,   1,   0 }, /* fpgaResetLowOut	*/
+#if !defined(CONFIG_SC)
+	/* PC10 */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus4EnSig		*/
+#else
+	/* PC10 */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+#endif
+	/* PC9  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+#if !defined(CONFIG_SC)
+	/* PC8  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus3EnSig		*/
+#else
+	/* PC8  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+#endif
+	/* PC7  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PC6  */ { 1,   0,   0,   1,   0,   1,   0 }, /* gpio0			*/
+#if !defined(CONFIG_SC)
+	/* PC5  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus2EnSig		*/
+	/* PC4  */ { 1,   0,   0,   1,   0,   1,   0 }, /* i2cBus1EnSig		*/
+#else
+	/* PC5  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+	/* PC4  */ { 0,   0,   0,   1,   0,   1,   0 }, /*	*/
+#endif
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
+	},
+
+	/*
+	 * Port D configuration
+	 */
+	{	/*	    conf ppar psor pdir podr pdat pint 	   function			*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD15 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD14 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD13 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD12 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD11 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD10 */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD9  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD8  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD7  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD6  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD5  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD4  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* PD3  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }, /*	*/
+	/* N/A  */ { 0,   0,   0,   0,   0,   0,   0 }  /*	*/
+	}
+};
+
+/*
+ * Configure the MPC8XX I/O ports per the ioport configuration table
+ * (taken from ./cpu/mpc8260/cpu_init.c)
+ */
+void config_mpc8xx_ioports (volatile immap_t * immr)
+{
+	int portnum;
+
+	for (portnum = 0; portnum < NUM_PORTS; portnum++) {
+		uint pmsk = 0, ppar = 0, psor = 0, pdir = 0;
+		uint podr = 0, pdat = 0, pint = 0;
+		uint msk = 1;
+		mpc8xx_iop_conf_t *iopc =
+			(mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0];
+		mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS;
+
+		/*
+		 * For all ports except port B, ignore the two don't care entries
+		 * in the configuration tables.
+		 */
+		if (portnum != 1) {
+			iopc = (mpc8xx_iop_conf_t *) &
+				iop_conf_tab[portnum][2];
+		}
+
+		/*
+		 * NOTE: index 0 refers to pin 17, index 17 refers to pin 0
+		 */
+		while (iopc < eiopc) {
+			if (iopc->conf) {
+				pmsk |= msk;
+				if (iopc->ppar)
+					ppar |= msk;
+				if (iopc->psor)
+					psor |= msk;
+				if (iopc->pdir)
+					pdir |= msk;
+				if (iopc->podr)
+					podr |= msk;
+				if (iopc->pdat)
+					pdat |= msk;
+				if (iopc->pint)
+					pint |= msk;
+			}
+			msk <<= 1;
+			iopc++;
+		}
+
+		PRINTF ("%s:%d:\n  portnum=%d ", __FUNCTION__, __LINE__,
+			portnum);
+#ifdef IOPORT_DEBUG
+		switch (portnum) {
+		case 0:
+			printf ("(A)\n");
+			break;
+		case 1:
+			printf ("(B)\n");
+			break;
+		case 2:
+			printf ("(C)\n");
+			break;
+		case 3:
+			printf ("(D)\n");
+			break;
+		default:
+			printf ("(?)\n");
+			break;
+		}
+#endif
+		PRINTF ("  ppar=0x%.8x  pdir=0x%.8x  podr=0x%.8x\n"
+			"  pdat=0x%.8x  psor=0x%.8x  pint=0x%.8x  pmsk=0x%.8x\n",
+			ppar, pdir, podr, pdat, psor, pint, pmsk);
+
+		/*
+		 * Have to handle the ioports on a port-by-port basis since there
+		 * are three different flavors.
+		 */
+		if (pmsk != 0) {
+			uint tpmsk = ~pmsk;
+
+			if (0 == portnum) {	/* port A */
+				immr->im_ioport.iop_papar &= tpmsk;
+				immr->im_ioport.iop_padat =
+					(immr->im_ioport.
+					 iop_padat & tpmsk) | pdat;
+				immr->im_ioport.iop_padir =
+					(immr->im_ioport.
+					 iop_padir & tpmsk) | pdir;
+				immr->im_ioport.iop_paodr =
+					(immr->im_ioport.
+					 iop_paodr & tpmsk) | podr;
+				immr->im_ioport.iop_papar |= ppar;
+			} else if (1 == portnum) {	/* port B */
+				immr->im_cpm.cp_pbpar &= tpmsk;
+				immr->im_cpm.cp_pbdat =
+					(immr->im_cpm.
+					 cp_pbdat & tpmsk) | pdat;
+				immr->im_cpm.cp_pbdir =
+					(immr->im_cpm.
+					 cp_pbdir & tpmsk) | pdir;
+				immr->im_cpm.cp_pbodr =
+					(immr->im_cpm.
+					 cp_pbodr & tpmsk) | podr;
+				immr->im_cpm.cp_pbpar |= ppar;
+			} else if (2 == portnum) {	/* port C */
+				immr->im_ioport.iop_pcpar &= tpmsk;
+				immr->im_ioport.iop_pcdat =
+					(immr->im_ioport.
+					 iop_pcdat & tpmsk) | pdat;
+				immr->im_ioport.iop_pcdir =
+					(immr->im_ioport.
+					 iop_pcdir & tpmsk) | pdir;
+				immr->im_ioport.iop_pcint =
+					(immr->im_ioport.
+					 iop_pcint & tpmsk) | pint;
+				immr->im_ioport.iop_pcso =
+					(immr->im_ioport.
+					 iop_pcso & tpmsk) | psor;
+				immr->im_ioport.iop_pcpar |= ppar;
+			} else if (3 == portnum) {	/* port D */
+				immr->im_ioport.iop_pdpar &= tpmsk;
+				immr->im_ioport.iop_pddat =
+					(immr->im_ioport.
+					 iop_pddat & tpmsk) | pdat;
+				immr->im_ioport.iop_pddir =
+					(immr->im_ioport.
+					 iop_pddir & tpmsk) | pdir;
+				immr->im_ioport.iop_pdpar |= ppar;
+			}
+		}
+	}
+
+	PRINTF ("%s:%d: Port A:\n  papar=0x%.4x  padir=0x%.4x"
+		"  paodr=0x%.4x\n  padat=0x%.4x\n", __FUNCTION__, __LINE__,
+		immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
+		immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
+	PRINTF ("%s:%d: Port B:\n  pbpar=0x%.8x  pbdir=0x%.8x"
+		"  pbodr=0x%.8x\n  pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
+		immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
+		immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
+	PRINTF ("%s:%d: Port C:\n  pcpar=0x%.4x  pcdir=0x%.4x"
+		"  pcdat=0x%.4x\n  pcso=0x%.4x  pcint=0x%.4x\n  ",
+		__FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
+		immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
+		immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
+	PRINTF ("%s:%d: Port D:\n  pdpar=0x%.4x  pddir=0x%.4x"
+		"  pddat=0x%.4x\n", __FUNCTION__, __LINE__,
+		immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
+		immr->im_ioport.iop_pddat);
+}
diff --git a/board/gen860t/ioport.h b/board/gen860t/ioport.h
new file mode 100755
index 0000000..34a2d7b
--- /dev/null
+++ b/board/gen860t/ioport.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define NUM_PORTS	4
+#define PORT_BITS	18
+
+/*
+ * This structure provides configuration information for one port pin.
+ * We include all fields needed to initialize any of the ioports.
+ */
+typedef struct {
+    unsigned char conf:1;	/* If 1, configure this port		*/
+    unsigned char ppar:1;	/* Port Pin Assignment Register		*/
+    unsigned char psor:1;	/* Port Special Options Register	*/
+    unsigned char pdir:1;	/* Port Data Direction Register		*/
+    unsigned char podr:1;	/* Port Open Drain Register			*/
+    unsigned char pdat:1;	/* Port Data Register				*/
+    unsigned char pint:1;	/* Port Interrupt Register			*/
+} mpc8xx_iop_conf_t;
+
+extern void config_mpc8xx_ioports(volatile immap_t *immr);
+
+/* vim: set ts=4 tw=78 sw=4: */
diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds
new file mode 100755
index 0000000..7926a2e
--- /dev/null
+++ b/board/gen860t/u-boot-flashenv.lds
@@ -0,0 +1,139 @@
+/*
+ * Linker command file for the GEN860T board when the environment is
+ * stored in flash memory.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+  /*
+   * Read-only sections, merged into text segment:
+   */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /*
+   * Read-write section, merged into data segment:
+   */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data:
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+
+  .ppcenv:
+  {
+    . = env_offset;
+    common/environment.o
+  }
+}
diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds
new file mode 100755
index 0000000..1df4817
--- /dev/null
+++ b/board/gen860t/u-boot.lds
@@ -0,0 +1,133 @@
+/*
+ * Linker command file for the GEN860T board.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+  /*
+   * Read-only sections, merged into text segment:
+   */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text :
+  {
+    cpu/mpc8xx/start.o		(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /*
+   * Read-write section, merged into data segment:
+   */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/genietv/Makefile b/board/genietv/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/genietv/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/genietv/config.mk b/board/genietv/config.mk
new file mode 100755
index 0000000..69ab21f
--- /dev/null
+++ b/board/genietv/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x00000000
+OBJCFLAGS = --set-section-flags=.ppcenv=contents,alloc,load,data
diff --git a/board/genietv/flash.c b/board/genietv/flash.c
new file mode 100755
index 0000000..1c1728b
--- /dev/null
+++ b/board/genietv/flash.c
@@ -0,0 +1,469 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+	    flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	/* Detect size */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	/* Setup offsets */
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	size_b1 = 0 ;
+
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].sector_count = -1;
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ * Fix this to support variable sector sizes
+*/
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+	{
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case FLASH_MAN_AMD:	printf ("AMD ");		break;
+		case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+		case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK)
+	{
+		case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+			break;
+		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+					break;
+		default:		printf ("Unknown Chip Type\n");
+					break;
+	}
+
+	if (info->size >> 20) {
+	    printf ("  Size: %ld MB in %d Sectors\n",
+	    	info->size >> 20,
+		info->sector_count);
+	} else {
+	    printf ("  Size: %ld KB in %d Sectors\n",
+	    	info->size >> 10,
+		info->sector_count);
+	}
+
+	puts ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i)
+	{
+		if ((i % 5) == 0)
+		{
+			puts ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	putc ('\n');
+	return;
+}
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	volatile unsigned char *caddr;
+	char value;
+
+	caddr = (volatile unsigned char *)addr ;
+
+	/* Write auto select command: read Manufacturer ID */
+
+#if 0
+	printf("Base address is: %08x\n", caddr);
+#endif
+
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	value = caddr[0];
+
+#if 0
+	printf("Manufact ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case 0x1: /* AMD_MANUFACT */
+			info->flash_id = FLASH_MAN_AMD;
+		break;
+
+		case 0x4: /* FUJ_MANUFACT */
+			info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	value = caddr[1];			/* device ID		*/
+#if 0
+	printf("Device ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case AMD_ID_LV040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;				/* => 512Kb 		*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);			/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets ((ulong)addr, &flash_info[0]);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++)
+	{
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN)
+	{
+		caddr = (volatile unsigned char *)info->start[0];
+		*caddr = 0xF0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (volatile unsigned char *)(info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile unsigned char *)(info->start[l_sect]);
+
+	while ((addr[0] & 0xFF) != 0xFF)
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *)info->start[0];
+
+	addr[0] = 0xF0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]),
+				*cdest,*cdata;
+	ulong start;
+	int flag, count = 4 ;
+
+	cdest = (volatile unsigned char *)dest ;
+	cdata = (volatile unsigned char *)&data ;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	while(count--)
+	{
+	    /* Disable interrupts which might cause a timeout here */
+	    flag = disable_interrupts();
+
+	    addr[0x0555] = 0xAA;
+	    addr[0x02AA] = 0x55;
+	    addr[0x0555] = 0xA0;
+
+	    *cdest = *cdata;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	    	enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((*cdest ^ *cdata) & 0x80)
+	    {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	    }
+
+	    cdata++ ;
+	    cdest++ ;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c
new file mode 100755
index 0000000..5f8c899
--- /dev/null
+++ b/board/genietv/genietv.c
@@ -0,0 +1,360 @@
+/*
+ * genietv/genietv.c
+ *
+ * The GENIETV is using the following physical memorymap (copied from
+ * the FADS configuration):
+ *
+ * ff020000 -> ff02ffff : pcmcia
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxROM
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * 02800000 -> 0287ffff : flash      connected to CS0
+ * 00000000 -> nnnnnnnn : sdram      setup by U-Boot
+ *
+ * CS pins are connected as follows:
+ *
+ * CS0 -512Kb boot flash
+ * CS1 - SDRAM #1
+ * CS2 - SDRAM #2
+ * CS3 - Flash #1
+ * CS4 - Flash #2
+ * CS5 - LON (if present)
+ * CS6 - PCMCIA #1
+ * CS7 - PCMCIA #2
+ *
+ * Ports are configured as follows:
+ *
+ * PA7 - SDRAM banks enable
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define CFG_PA7		0x0100
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMB RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00,
+	0x1FFDDC47,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMB RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMB RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMB RAM)
+	 */
+	0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMB RAM)
+	 */
+	0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMB RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMB RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity
+ */
+
+int checkboard (void)
+{
+	puts ("Board: GenieTV\n");
+	return 0;
+}
+
+#if 0
+static void PrintState (void)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &im->im_memctl;
+
+	printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0,
+		memctl->memc_or0);
+	printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1,
+		memctl->memc_or1);
+	printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2,
+		memctl->memc_or2);
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &im->im_memctl;
+	long int size_b0, size_b1, size8;
+
+	/* Enable SDRAM */
+
+	/* Configuring PA7 for general purpouse output pin */
+	im->im_ioport.iop_papar &= ~CFG_PA7;	/* 0 = general purpouse */
+	im->im_ioport.iop_padir |= CFG_PA7;	/* 1 = output */
+
+	/* Enable SDRAM - PA7 = 1 */
+	im->im_ioport.iop_padat |= CFG_PA7;	/* value of PA7 */
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+
+	memctl->memc_mbmr = CFG_MBMR_8COL;
+
+	upmconfig (UPMB, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+
+	memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br1 =
+		((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
+
+	memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br2 =
+		((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
+
+	/* perform SDRAM initialization sequence */
+	memctl->memc_mar = 0x00000088;
+
+	memctl->memc_mcr = 0x80802105;	/* SDRAM bank 0 */
+
+	memctl->memc_mcr = 0x80804105;	/* SDRAM bank 1 */
+
+	/* Execute refresh 8 times */
+	memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X;
+
+	memctl->memc_mcr = 0x80802130;	/* SDRAM bank 0 - execute twice */
+
+	memctl->memc_mcr = 0x80804130;	/* SDRAM bank 1 - execute twice */
+
+	/* Execute refresh 4 times */
+	memctl->memc_mbmr = CFG_MBMR_8COL;
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+
+#if 0
+	PrintState ();
+#endif
+/*    printf ("\nChecking bank1..."); */
+	size8 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	size_b0 = size8;
+
+/*    printf ("\nChecking bank2..."); */
+	size_b1 =
+		dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
+
+	if (size_b1 > 0) {
+		/*
+		 * Position Bank 1 immediately above Bank 0
+		 */
+		memctl->memc_or2 =
+			((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_br2 =
+			((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
+			(size_b0 & BR_BA_MSK);
+	} else {
+		/*
+		 * No bank 1
+		 *
+		 * invalidate bank
+		 */
+		memctl->memc_br2 = 0;
+		/* adjust refresh rate depending on SDRAM type, one bank */
+		memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+	}
+
+	/* If no memory detected, disable SDRAM */
+	if ((size_b0 + size_b1) == 0) {
+		printf ("disabling SDRAM!\n");
+		/* Disable SDRAM - PA7 = 1 */
+		im->im_ioport.iop_padat &= ~CFG_PA7;	/* value of PA7 */
+	}
+/*	else */
+/*    printf("done! (%08lx)\n", size_b0 + size_b1); */
+
+#if 0
+	PrintState ();
+#endif
+	return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mbmr_value, long int *base,
+			   long int maxsize)
+{
+	long size;
+
+	/*memctl->memc_mbmr = mbmr_value; */
+
+	size = get_ram_size (base, maxsize);
+
+	if (size) {
+/*      printf("(%08lx)", size); */
+	} else {
+		printf ("(0)");
+	}
+
+	return (size);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+
+#ifdef	CFG_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char *) CFG_PCMCIA_MEM_ADDR;
+#endif
+
+int pcmcia_init (void)
+{
+	volatile pcmconf8xx_t *pcmp;
+	uint v, slota, slotb;
+
+	/*
+	 ** Enable the PCMCIA for a Flash card.
+	 */
+	pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
+
+#if 0
+	pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
+	pcmp->pcmc_por0 = 0xc00ff05d;
+#endif
+
+	/* Set all slots to zero by default. */
+	pcmp->pcmc_pgcra = 0;
+	pcmp->pcmc_pgcrb = 0;
+#ifdef PCMCIA_SLOT_A
+	pcmp->pcmc_pgcra = 0x40;
+#endif
+#ifdef PCMCIA_SLOT_B
+	pcmp->pcmc_pgcrb = 0x40;
+#endif
+
+	/* Check if any PCMCIA card is luged in. */
+	slota = (pcmp->pcmc_pipr & 0x18000000) == 0;
+	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0;
+
+	if (!(slota || slotb)) {
+		printf ("No card present\n");
+#ifdef PCMCIA_SLOT_A
+		pcmp->pcmc_pgcra = 0;
+#endif
+#ifdef PCMCIA_SLOT_B
+		pcmp->pcmc_pgcrb = 0;
+#endif
+		return -1;
+	} else
+		printf ("Unknown card (");
+
+	v = 0;
+
+	switch ((pcmp->pcmc_pipr >> 14) & 3) {
+	case 0x00:
+		printf ("5V");
+		v = 5;
+		break;
+	case 0x01:
+		printf ("5V and 3V");
+		v = 3;
+		break;
+	case 0x03:
+		printf ("5V, 3V and x.xV");
+		v = 3;
+		break;
+	}
+
+	switch (v) {
+	case 3:
+		printf ("; using 3V");
+		/* Enable 3 volt Vcc. */
+
+		break;
+
+	default:
+		printf ("; unknown voltage");
+		return -1;
+	}
+	printf (")\n");
+	/* disable pcmcia reset after a while */
+
+	udelay (20);
+
+	pcmp->pcmc_pgcrb = 0;
+
+	/* If you using a real hd you should give a short
+	 * spin-up time. */
+#ifdef CONFIG_DISK_SPINUP_TIME
+	udelay (CONFIG_DISK_SPINUP_TIME);
+#endif
+
+	return 0;
+}
+#endif /* CFG_CMD_PCMCIA */
diff --git a/board/genietv/genietv.h b/board/genietv/genietv.h
new file mode 100755
index 0000000..7c95b56
--- /dev/null
+++ b/board/genietv/genietv.h
@@ -0,0 +1,25 @@
+/*
+ * The GENIETV is using the following physical memorymap (copied from
+ * the FADS configuration):
+ *
+ * ff020000 -> ff02ffff : pcmcia
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxROM
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * 02800000 -> 0287ffff : flash      connected to CS0
+ * 00000000 -> nnnnnnnn : sdram      setup by U-Boot
+ *
+ * CS pins are connected as follows:
+ *
+ * CS0 -512Kb boot flash
+ * CS1 - SDRAM #1
+ * CS2 - SDRAM #2
+ * CS3 - Flash #1
+ * CS4 - Flash #2
+ * CS5 - LON (if present)
+ * CS6 - PCMCIA #1
+ * CS7 - PCMCIA #2
+ *
+ * Ports are configured as follows:
+ *
+ * PA7 - SDRAM banks enable
+ */
diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds
new file mode 100755
index 0000000..f48b9ad
--- /dev/null
+++ b/board/genietv/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  . = ALIGN(256 * 1024);
+  .ppcenv	:
+  {
+    common/environment.o (.ppcenv)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug
new file mode 100755
index 0000000..e843df6
--- /dev/null
+++ b/board/genietv/u-boot.lds.debug
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  . = ALIGN(256 * 1024);
+  .ppcenv	:
+  {
+    common/environment.o (.ppcenv)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/gth/Makefile b/board/gth/Makefile
new file mode 100755
index 0000000..e14c12e
--- /dev/null
+++ b/board/gth/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ee_access.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/gth/README b/board/gth/README
new file mode 100755
index 0000000..241c70b
--- /dev/null
+++ b/board/gth/README
@@ -0,0 +1,18 @@
+Written by Thomas.Lange@corelatus.com 010805
+
+To make a system for gth that actually works ;-)
+the variable TBASE needs to be set to 0,1 or 2
+depending on location where image is supposed to
+be started from.
+E.g. make TBASE=1
+
+0: Start from RAM, base 0
+
+1: Start from flash_base + 0x10070
+
+2: Start from flash_base + 0x30070
+
+When using 1 or 2, the image is supposed to be launched
+from miniboot that boots the first U-Boot image found in
+flash.
+For miniboot code, description, see www.opensource.se
diff --git a/board/gth/config.mk b/board/gth/config.mk
new file mode 100755
index 0000000..3c80156
--- /dev/null
+++ b/board/gth/config.mk
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+ifeq ($(TBASE),0)
+TEXT_BASE = 0
+else
+ifeq ($(TBASE),1)
+TEXT_BASE = 0x80010070
+else
+ifeq ($(TBASE),2)
+TEXT_BASE = 0x80030070
+else
+## Only to make ordinary make work
+TEXT_BASE = 0x90000000
+endif
+endif
+endif
+
+OBJCFLAGS =	--set-section-flags=.ppcenv=contents,alloc,load,data
diff --git a/board/gth/ee_access.c b/board/gth/ee_access.c
new file mode 100755
index 0000000..716c90e
--- /dev/null
+++ b/board/gth/ee_access.c
@@ -0,0 +1,335 @@
+/* Module for handling DALLAS DS2438, smart battery monitor
+   Chip can store up to 40 bytes of user data in EEPROM,
+   perform temp, voltage and current measurements.
+   Chip also contains a unique serial number.
+
+   Always read/write LSb first
+
+   For documentaion, see data sheet for DS2438, 2438.pdf
+
+   By Thomas.Lange@corelatus.com 001025 */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+#include <../board/gth/ee_dev.h>
+
+/* We dont have kernel functions */
+#define printk printf
+#define KERN_DEBUG
+#define KERN_ERR
+#define EIO 1
+
+static int Debug = 0;
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/*
+ * lookup table ripped from DS app note 17, understanding and using
+ * cyclic redundancy checks...
+ */
+
+static u8 crc_lookup[256] = {
+	0,	94,	188,	226,	97,	63,	221,	131,
+	194,	156,	126,	32,	163,	253,	31,	65,
+	157,	195,	33,	127,	252,	162,	64,	30,
+	95,	1,	227,	189,	62,	96,	130,	220,
+	35,	125,	159,	193,	66,	28,	254,	160,
+	225,	191,	93,	3,	128,	222,	60,	98,
+	190,	224,	2,	92,	223,	129,	99,	61,
+	124,	34,	192,	158,	29,	67,	161,	255,
+	70,	24,	250,	164,	39,	121,	155,	197,
+	132,	218,	56,	102,	229,	187,	89,	7,
+	219,	133,	103,	57,	186,	228,	6,	88,
+	25,	71,	165,	251,	120,	38,	196,	154,
+	101,	59,	217,	135,	4,	90,	184,	230,
+	167,	249,	27,	69,	198,	152,	122,	36,
+	248,	166,	68,	26,	153,	199,	37,	123,
+	58,	100,	134,	216,	91,	5,	231,	185,
+	140,	210,	48,	110,	237,	179,	81,	15,
+	78,	16,	242,	172,	47,	113,	147,	205,
+	17,	79,	173,	243,	112,	46,	204,	146,
+	211,	141,	111,	49,	178,	236,	14,	80,
+	175,	241,	19,	77,	206,	144,	114,	44,
+	109,	51,	209,	143,	12,	82,	176,	238,
+	50,	108,	142,	208,	83,	13,	239,	177,
+	240,	174,	76,	18,	145,	207,	45,	115,
+	202,	148,	118,	40,	171,	245,	23,	73,
+	8,	86,	180,	234,	105,	55,	213,	139,
+	87,	9,	235,	181,	54,	104,	138,	212,
+	149,	203,	41,	119,	244,	170,	72,	22,
+	233,	183,	85,	11,	136,	214,	52,	106,
+	43,	117,	151,	201,	74,	20,	246,	168,
+	116,	42,	200,	150,	21,	75,	169,	247,
+	182,	232,	10,	84,	215,	137,	107,	53
+};
+
+static u8 make_new_crc( u8 Old_crc, u8 New_value ){
+  /* Compute a new checksum with new byte, using previous checksum as input
+     See DS app note 17, understanding and using cyclic redundancy checks...
+     Also see DS2438, page 11 */
+  return( crc_lookup[Old_crc ^ New_value ]);
+}
+
+int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
+  /* Check if the checksum for this buffer is correct */
+  u8 Curr_crc=0;
+  int i;
+  u8 *Curr_byte = Buffer;
+
+  for(i=0;i<Len;i++){
+    Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
+    Curr_byte++;
+  }
+  E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
+
+  if(Curr_crc == Crc){
+    /* Good */
+    return(TRUE);
+  }
+  printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n",
+	Curr_crc, Crc);
+  return(FALSE);
+}
+
+static void
+set_idle(void){
+  /* Send idle and keep start time
+     Continous 1 is idle */
+  WRITE_PORT(1);
+}
+
+static int
+do_reset(void){
+  /* Release reset and verify that chip responds with presence pulse */
+  int Retries = 0;
+  while(Retries<5){
+    udelay(RESET_LOW_TIME);
+
+    /* Send reset */
+    WRITE_PORT(0);
+    udelay(RESET_LOW_TIME);
+
+    /* Release reset */
+    WRITE_PORT(1);
+
+    /* Wait for EEPROM to drive output */
+    udelay(PRESENCE_TIMEOUT);
+    if(!READ_PORT){
+      /* Ok, EEPROM is driving a 0 */
+      E_DEBUG("Presence detected\n");
+      if(Retries){
+	E_DEBUG("Retries %d\n",Retries);
+      }
+      /* Make sure chip releases pin */
+      udelay(PRESENCE_LOW_TIME);
+      return 0;
+    }
+    Retries++;
+  }
+
+  printk(KERN_ERR"EEPROM did not respond when releasing reset\n");
+
+    /* Make sure chip releases pin */
+  udelay(PRESENCE_LOW_TIME);
+
+  /* Set to idle again */
+  set_idle();
+
+  return(-EIO);
+}
+
+static u8
+read_byte(void){
+  /* Read a single byte from EEPROM
+     Read LSb first */
+  int i;
+  int Value;
+  u8 Result=0;
+#ifndef CFG_IMMR
+  u32 Flags;
+#endif
+
+  E_DEBUG("Reading byte\n");
+
+  for(i=0;i<8;i++){
+    /* Small delay between pulses */
+    udelay(1);
+
+#ifndef CFG_IMMR
+    /* Disable irq */
+    save_flags(Flags);
+    cli();
+#endif
+
+    /* Pull down pin short time to start read
+       See page 26 in data sheet */
+
+    WRITE_PORT(0);
+    udelay(READ_LOW);
+    WRITE_PORT(1);
+
+    /* Wait for chip to drive pin */
+    udelay(READ_TIMEOUT);
+
+    Value = READ_PORT;
+    if(Value)
+      Value=1;
+
+#ifndef CFG_IMMR
+    /* Enable irq */
+    restore_flags(Flags);
+#endif
+
+    /* Wait for chip to release pin */
+    udelay(TOTAL_READ_LOW-READ_TIMEOUT);
+
+    /* LSb first */
+    Result|=Value<<i;
+  }
+
+  E_DEBUG("Read byte 0x%x\n",Result);
+
+  return(Result);
+}
+
+static void
+write_byte(u8 Byte){
+  /* Write a single byte to EEPROM
+     Write LSb first */
+  int i;
+  int Value;
+#ifndef CFG_IMMR
+  u32 Flags;
+#endif
+
+  E_DEBUG("Writing byte 0x%x\n",Byte);
+
+  for(i=0;i<8;i++){
+    /* Small delay between pulses */
+    udelay(1);
+    Value = Byte&1;
+
+#ifndef CFG_IMMR
+    /* Disable irq */
+    save_flags(Flags);
+    cli();
+#endif
+
+    /* Pull down pin short time for a 1, long time for a 0
+       See page 26 in data sheet */
+
+    WRITE_PORT(0);
+    if(Value){
+      /* Write a 1 */
+      udelay(WRITE_1_LOW);
+    }
+    else{
+      /* Write a 0 */
+      udelay(WRITE_0_LOW);
+    }
+
+    WRITE_PORT(1);
+
+#ifndef CFG_IMMR
+    /* Enable irq */
+    restore_flags(Flags);
+#endif
+
+    if(Value)
+      /* Wait for chip to read the 1 */
+      udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
+    Byte>>=1;
+  }
+}
+
+int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
+  /* Execute this command string, including
+     giving reset and setting to idle after command
+     if Rx_len is set, we read out data from EEPROM */
+  int i;
+
+  E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
+
+  if(do_reset()){
+    /* Failed! */
+    return(-EIO);
+  }
+
+  if(Send_skip)
+    /* Always send SKIP_ROM first to tell chip we are sending a command,
+       except when we read out rom data for chip */
+    write_byte(SKIP_ROM);
+
+  /* Always have Tx data */
+  for(i=0;i<Tx_len;i++){
+    write_byte(Tx[i]);
+  }
+
+  if(Rx_len){
+    for(i=0;i<Rx_len;i++){
+      Rx[i]=read_byte();
+    }
+  }
+
+  set_idle();
+
+  E_DEBUG("Command done\n");
+
+  return(0);
+}
+
+int ee_init_data(void){
+  int i;
+  u8 Tx[10];
+  int tmp;
+  volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+  while(0){
+    tmp = 1-tmp;
+    if(tmp)
+      immap->im_ioport.iop_padat &= ~PA_FRONT_LED;
+    else
+      immap->im_ioport.iop_padat |= PA_FRONT_LED;
+    udelay(1);
+  }
+
+  /* Set port to open drain to be able to read data from
+     port without setting it to input */
+  PORT_B_PAR &= ~PB_EEPROM;
+  PORT_B_ODR |= PB_EEPROM;
+  SET_PORT_B_OUTPUT(PB_EEPROM);
+
+  /* Set idle mode */
+  set_idle();
+
+  /* Copy all User EEPROM data to scratchpad */
+  for(i=0;i<USER_PAGES;i++){
+    Tx[0]=RECALL_MEMORY;
+    Tx[1]=EE_USER_PAGE_0+i;
+    if(ee_do_command(Tx,2,NULL,0,TRUE)) return(-EIO);
+  }
+
+  /* Make sure chip doesnt store measurements in NVRAM */
+  Tx[0]=WRITE_SCRATCHPAD;
+  Tx[1]=0; /* Page */
+  Tx[2]=9;
+  if(ee_do_command(Tx,3,NULL,0,TRUE)) return(-EIO);
+
+  Tx[0]=COPY_SCRATCHPAD;
+  if(ee_do_command(Tx,2,NULL,0,TRUE)) return(-EIO);
+
+  /* FIXME check status bit instead
+     Could take 10 ms to store in EEPROM */
+  for(i=0;i<10;i++){
+    udelay(1000);
+  }
+
+  return(0);
+}
diff --git a/board/gth/ee_access.h b/board/gth/ee_access.h
new file mode 100755
index 0000000..e847f2c
--- /dev/null
+++ b/board/gth/ee_access.h
@@ -0,0 +1,16 @@
+/* By Thomas.Lange@Corelatus.com 001025
+
+   Definitions for EEPROM/VOLT METER  DS2438 */
+
+#ifndef INCeeaccessh
+#define INCeeaccessh
+
+int ee_do_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
+int ee_init_data(void);
+int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#endif /* INCeeaccessh */
diff --git a/board/gth/ee_dev.h b/board/gth/ee_dev.h
new file mode 100755
index 0000000..417c7b6
--- /dev/null
+++ b/board/gth/ee_dev.h
@@ -0,0 +1,85 @@
+/* By Thomas.Lange@Corelatus.com 001025
+   $Revision: 1.6 $
+
+   Definitions for EEPROM/VOLT METER  DS2438
+   Copyright (C) 2000-2001 Corelatus AB */
+
+#ifndef INCeedevh
+#define INCeedevh
+
+#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
+
+#define PORT_B_PAR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbpar
+#define PORT_B_ODR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbodr
+#define PORT_B_DIR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdir
+#define PORT_B_DAT ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat
+
+#define SET_PORT_B_INPUT(Mask)  PORT_B_DIR &= ~(Mask)
+#define SET_PORT_B_OUTPUT(Mask) PORT_B_DIR |= Mask
+
+#define WRITE_PORT_B(Mask,Value) { \
+			if (Value) PORT_B_DAT |= Mask; \
+			else PORT_B_DAT &= ~(Mask); \
+		}
+#define WRITE_PORT(Value) WRITE_PORT_B(PB_EEPROM,Value)
+
+#define READ_PORT (PORT_B_DAT&PB_EEPROM)
+
+/* 64 bytes chip */
+#define EE_CHIP_SIZE 64
+
+/* We use this resistor for measuring the current drain on 3.3V */
+#define CURRENT_RESISTOR 0.022
+
+/* microsecs
+   Pull line down at least this long for reset pulse */
+#define RESET_LOW_TIME    490
+
+/* Read presence pulse after we release reset pulse */
+#define PRESENCE_TIMEOUT  100
+#define PRESENCE_LOW_TIME 200
+
+#define WRITE_0_LOW 80
+#define WRITE_1_LOW 2
+#define TOTAL_WRITE_LOW 80
+
+#define READ_LOW        2
+#define READ_TIMEOUT   10
+#define TOTAL_READ_LOW 80
+
+/*** Rom function commands ***/
+#define READ_ROM   0x33
+#define MATCH_ROM  0x55
+#define SKIP_ROM   0xCC
+#define SEARCH_ROM 0xF0
+
+
+/*** Memory_command_function ***/
+#define WRITE_SCRATCHPAD 0x4E
+#define READ_SCRATCHPAD  0xBE
+#define COPY_SCRATCHPAD  0x48
+#define RECALL_MEMORY    0xB8
+#define CONVERT_TEMP     0x44
+#define CONVERT_VOLTAGE  0xB4
+
+/* Chip is divided in 8 pages, 8 bytes each */
+
+#define EE_PAGE_SIZE 8
+
+/* All chip data we want are in page 0 */
+
+/* Bytes in page 0 */
+#define EE_P0_STATUS   0
+#define EE_P0_TEMP_LSB 1
+#define EE_P0_TEMP_MSB 2
+#define EE_P0_VOLT_LSB 3
+#define EE_P0_VOLT_MSB 4
+#define EE_P0_CURRENT_LSB 5
+#define EE_P0_CURRENT_MSB 6
+
+
+/* 40 byte user data is located at page 3-7 */
+#define EE_USER_PAGE_0 3
+#define USER_PAGES 5
+
+#endif /* INCeedevh */
diff --git a/board/gth/flash.c b/board/gth/flash.c
new file mode 100755
index 0000000..41a5c50
--- /dev/null
+++ b/board/gth/flash.c
@@ -0,0 +1,649 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/*printf("faking");*/
+
+	return(0x1fffff);
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+	{
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN)
+	{
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+#if 0
+	if (FLASH_BASE1_PRELIM != 0x0) {
+	  size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	  if (size_b1 > size_b0) {
+	    printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+	    	size_b1, size_b1<<20,size_b0, size_b0<<20);
+
+	    flash_info[0].flash_id	= FLASH_UNKNOWN;
+	    flash_info[1].flash_id	= FLASH_UNKNOWN;
+	    flash_info[0].sector_count	= -1;
+	    flash_info[1].sector_count	= -1;
+	    flash_info[0].size		= 0;
+	    flash_info[1].size		= 0;
+	    return (0);
+	  }
+	} else {
+#endif
+	  size_b1 = 0;
+
+	  /* Remap FLASH according to real size */
+	  memctl->memc_or0 = CFG_OR0_PRELIM;
+	  memctl->memc_br0 = CFG_BR0_PRELIM;
+
+	  /* Re-do sizing to get full correct info */
+	  size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	  flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	  /* monitor protection ON by default */
+	  (void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_MONITOR_BASE,
+			    CFG_MONITOR_BASE+monitor_flash_len-1,
+			    &flash_info[0]);
+#endif
+
+	if (size_b1)
+	{
+	  /* memctl->memc_or1 = CFG_OR1_PRELIM;
+	     memctl->memc_br1 = CFG_BR1_PRELIM; */
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					 &flash_info[1]);
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET,
+				    CFG_MONITOR_BASE,
+				    CFG_MONITOR_BASE+monitor_flash_len-1,
+				    &flash_info[1]);
+#endif
+	}
+	else
+	{
+/*	    memctl->memc_or1 = CFG_OR1_PRELIM;
+ FIXME	    memctl->memc_br1 = CFG_BR1_PRELIM;  */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if (info->flash_id & FLASH_BTYPE)
+	{
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++)
+		{
+			info->start[i] = base + (i * 0x00040000);
+		}
+	}
+	else
+	{
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		for (; i >= 0; i--)
+		{
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+
+#if 0
+	case FLASH_AM040B:
+		printf ("AM29F040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM040T:
+		printf ("AM29F040T (4 Mbit, top boot sect)\n");
+		break;
+#endif
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i)
+	{
+		if ((i % 5) == 0)
+		{
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+#if 0
+	ulong base = (ulong)addr;
+#endif
+	ulong value;
+
+	/* Write auto select command: read Manufacturer ID */
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x90909090;
+#endif
+
+	value = addr[0];
+
+	switch (value)
+	{
+		case AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+		break;
+
+		case FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value)
+	{
+#if 0
+		case AMD_ID_F040B:
+			info->flash_id += FLASH_AM040B;
+			info->sector_count = 8;
+			info->size = 0x00200000;
+			break;				/* => 2 MB		*/
+#endif
+		case AMD_ID_LV400T:
+			info->flash_id += FLASH_AM400T;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;				/* => 1 MB		*/
+
+		case AMD_ID_LV400B:
+			info->flash_id += FLASH_AM400B;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;				/* => 1 MB		*/
+
+		case AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;				/* => 2 MB		*/
+
+		case AMD_ID_LV800B:
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;				/* => 2 MB		*/
+
+		case AMD_ID_LV160T:
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;				/* => 4 MB		*/
+
+		case AMD_ID_LV160B:
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+		case AMD_ID_LV320T:
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;				/* => 8 MB		*/
+
+		case AMD_ID_LV320B:
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;				/* => 8 MB		*/
+#endif
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);			/* => no or unknown flash */
+
+	}
+
+#if 0
+	/* set up sector start adress table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+#else
+	flash_get_offsets ((ulong)addr, &flash_info[0]);
+#endif
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++)
+	{
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN)
+	{
+		addr = (volatile unsigned long *)info->start[0];
+#if 0
+		*addr = 0x00F000F0;	/* reset bank */
+#else
+		*addr = 0xF0F0F0F0;	/* reset bank */
+#endif
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x80808080;
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+#endif
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+#if 0
+			addr[0] = 0x00300030;
+#else
+			addr[0] = 0x30303030;
+#endif
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+#if 0
+	while ((addr[0] & 0x00800080) != 0x00800080)
+#else
+	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
+#endif
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#if 0
+	addr[0] = 0x00F000F0;	/* reset bank */
+#else
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+#endif
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0xA0A0A0A0;
+#endif
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+#if 0
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
+#else
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
+#endif
+	{
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/gth/gth.c b/board/gth/gth.c
new file mode 100755
index 0000000..b1fcbf5
--- /dev/null
+++ b/board/gth/gth.c
@@ -0,0 +1,595 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Adapted from FADS and other board config files to GTH by thomas@corelatus.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <watchdog.h>
+#include <mpc8xx.h>
+#include "ee_access.h"
+#include "ee_dev.h"
+
+#ifdef CONFIG_BDM
+#undef printf
+#define printf(a,...)			/* nothing */
+#endif
+
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	int Id = 0;
+	int Rev = 0;
+	u32 Pbdat;
+
+	puts ("Board: ");
+
+	/* Turn on leds and setup for reading rev and id */
+
+#define PB_OUTS (PB_BLUE_LED|PB_ID_GND)
+#define PB_INS  (PB_ID_0|PB_ID_1|PB_ID_2|PB_ID_3|PB_REV_1|PB_REV_0)
+
+	immap->im_cpm.cp_pbpar &= ~(PB_OUTS | PB_INS);
+
+	immap->im_cpm.cp_pbdir &= ~PB_INS;
+
+	immap->im_cpm.cp_pbdir |= PB_OUTS;
+	immap->im_cpm.cp_pbodr |= PB_OUTS;
+	immap->im_cpm.cp_pbdat &= ~PB_OUTS;
+
+	/* Hold 100 Mbit in reset until fpga is loaded */
+	immap->im_ioport.iop_pcpar &= ~PC_ENET100_RESET;
+	immap->im_ioport.iop_pcdir |= PC_ENET100_RESET;
+	immap->im_ioport.iop_pcso &= ~PC_ENET100_RESET;
+	immap->im_ioport.iop_pcdat &= ~PC_ENET100_RESET;
+
+	/* Turn on front led to show that we are alive */
+	immap->im_ioport.iop_papar &= ~PA_FRONT_LED;
+	immap->im_ioport.iop_padir |= PA_FRONT_LED;
+	immap->im_ioport.iop_paodr |= PA_FRONT_LED;
+	immap->im_ioport.iop_padat &= ~PA_FRONT_LED;
+
+	Pbdat = immap->im_cpm.cp_pbdat;
+
+	if (!(Pbdat & PB_ID_0))
+		Id += 1;
+	if (!(Pbdat & PB_ID_1))
+		Id += 2;
+	if (!(Pbdat & PB_ID_2))
+		Id += 4;
+	if (!(Pbdat & PB_ID_3))
+		Id += 8;
+
+	if (Pbdat & PB_REV_0)
+		Rev += 1;
+	if (Pbdat & PB_REV_1)
+		Rev += 2;
+
+	/* Turn ID off since we dont need it anymore */
+	immap->im_cpm.cp_pbdat |= PB_ID_GND;
+
+	printf ("GTH board, rev %d, id=0x%01x\n", Rev, Id);
+	return 0;
+}
+
+#define _NOT_USED_ 0xffffffff
+const uint sdram_table[] = {
+	/* Single read, offset 0 */
+	0x0f3dfc04, 0x0eefbc04, 0x01bf7c04, 0x0feafc00,
+	0x1fb5fc45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* Burst read, Offset 0x8, 4 reads */
+	0x0f3dfc04, 0x0eefbc04, 0x00bf7c04, 0x00ffec00,
+	0x00fffc00, 0x01eafc00, 0x1fb5fc00, 0xfffffc45,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* Not used part of burst read is used for MRS, Offset 0x14 */
+	0xefeabc34, 0x1fb57c34, 0xfffffc05, _NOT_USED_,
+	/* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
+
+	/* Single write, Offset 0x18 */
+	0x0f3dfc04, 0x0eebbc00, 0x01a27c04, 0x1fb5fc45,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* Burst write, Offset 0x20. 4 writes */
+	0x0f3dfc04, 0x0eebbc00, 0x00b77c00, 0x00fffc00,
+	0x00fffc00, 0x01eafc04, 0x1fb5fc45, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* Not used part of burst write is used for precharge, Offset 0x2C */
+	0x0ff5fc04, 0xfffffc05, _NOT_USED_, _NOT_USED_,
+	/* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */
+
+	/* Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command */
+	0x1ffd7c04, 0xfffffc04, 0xfffffc04, 0xfffffc05,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* Exception, Offset 0x3C */
+	0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_
+};
+
+const uint fpga_table[] = {
+	/* Single read, offset 0 */
+	0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
+	0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
+
+	/* Burst read, Offset 0x8 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* Single write, Offset 0x18 */
+	0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04,
+	0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05,
+
+	/* Burst write, Offset 0x20. */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* Period timer service. Offset 0x30. */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* Exception, Offset 0x3C */
+	0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_
+};
+
+int _initsdram (uint base, uint * noMbytes)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *mc = &immap->im_memctl;
+	volatile u32 *memptr;
+
+	mc->memc_mptpr = MPTPR_PTP_DIV16;	/* (16-17) */
+
+	/*  SDRAM in UPMA
+
+	   GPL_0 is connected instead of A19 to SDRAM.
+	   According to table 16-17, AMx should be 001, i.e. type 1
+	   and GPL_0 should hold address A10 when multiplexing */
+
+	mc->memc_mamr = (0x2E << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_AMA_TYPE_1 | MAMR_G0CLA_A10 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X;	/* (16-13) */
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/* Perform init of sdram ( Datasheet Page 9 )
+	   Precharge */
+	mc->memc_mcr = 0x8000212C;	/* run upm a at 0x2C (16-15) */
+
+	/* Run 2 refresh cycles */
+	mc->memc_mcr = 0x80002130;	/* run upm a at 0x30 (16-15) */
+	mc->memc_mcr = 0x80002130;	/* run upm a at 0x30 (16-15) */
+
+	/* Set Mode register */
+	mc->memc_mar = 0x00000088;	/* set mode register (address) to 0x022 (16-17) */
+	/* Lower 2 bits are not connected to chip */
+	mc->memc_mcr = 0x80002114;	/* run upm a at 0x14 (16-15) */
+
+	/* CS1, base 0x0000000 - 64 Mbyte, use UPM A */
+	mc->memc_or1 = 0xfc000000 | OR_CSNT_SAM;
+	mc->memc_br1 = BR_MS_UPMA | BR_V;	/* SDRAM base always 0 */
+
+	/* Test if we really have 64 MB SDRAM */
+	memptr = (u32 *) 0;
+	*memptr = 0;
+
+	memptr = (u32 *) 0x2000000;	/* First u32 in upper 32 MB */
+	*memptr = 0x12345678;
+
+	memptr = (u32 *) 0;
+	if (*memptr == 0x12345678) {
+		/* Wrapped, only have 32 MB */
+		mc->memc_or1 = 0xfe000000 | OR_CSNT_SAM;
+		*noMbytes = 32;
+	} else {
+		/* 64 MB */
+		*noMbytes = 64;
+	}
+
+	/* Setup FPGA in UPMB */
+	upmconfig (UPMB, (uint *) fpga_table,
+			   sizeof (fpga_table) / sizeof (uint));
+
+	/* Enable UPWAITB */
+	mc->memc_mbmr = MBMR_GPL_B4DIS;	/* (16-13) */
+
+	/* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */
+	mc->memc_or2 = 0xffc00000 | OR_BI;
+	mc->memc_br2 = FPGA_2_BASE | BR_MS_UPMB | BR_V;
+
+	/* CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit */
+	mc->memc_or3 = 0xffc00000 | OR_BI;
+	mc->memc_br3 = FPGA_3_BASE | BR_MS_UPMB | BR_V | BR_PS_16;
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void _sdramdisable (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_br1 = 0x00000000;
+
+	/* maybe we should turn off upmb here or something */
+}
+
+/* ------------------------------------------------------------------------- */
+
+int initsdram (uint base, uint * noMbytes)
+{
+	*noMbytes = 32;
+
+#ifdef CONFIG_START_IN_RAM
+	/* SDRAM is already setup. Dont touch it */
+	return 0;
+#else
+
+	if (!_initsdram (base, noMbytes)) {
+
+		return 0;
+	} else {
+		_sdramdisable ();
+
+		return -1;
+	}
+#endif
+}
+
+long int initdram (int board_type)
+{
+	u32 *i;
+	u32 j;
+	u32 k;
+
+	/* GTH only have SDRAM */
+	uint sdramsz;
+
+	if (!initsdram (0x00000000, &sdramsz)) {
+		printf ("(%u MB SDRAM) ", sdramsz);
+	} else {
+	/********************************
+     *SDRAM ERROR, HALT PROCESSOR
+     *********************************/
+		printf ("SDRAM ERROR\n");
+		while (1);
+	}
+
+#ifndef CONFIG_START_IN_RAM
+
+#define U32_S ((sdramsz<<18)-1)
+
+#if 1
+	/* Do a simple memory test */
+	for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) {
+		*i = j + (j << 17);
+		*(i + 1) = ~(j + (j << 18));
+	}
+
+	WATCHDOG_RESET ();
+
+	printf (".");
+
+	for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) {
+		k = *i;
+		if (k != (j + (j << 17))) {
+			printf ("Mem test error, i=0x%x, 0x%x\n, 0x%x", (u32) i, j, k);
+			while (1);
+		}
+		k = *(i + 1);
+		if (k != ~(j + (j << 18))) {
+			printf ("Mem test error(+1), i=0x%x, 0x%x\n, 0x%x",
+					(u32) i + 1, j, k);
+			while (1);
+		}
+	}
+#endif
+
+	WATCHDOG_RESET ();
+
+	/* Clear memory */
+	for (i = (u32 *) 0; (u32) i < U32_S; i++) {
+		*i = 0;
+	}
+#endif /* !start in ram */
+
+	WATCHDOG_RESET ();
+
+	return (sdramsz << 20);
+}
+
+#define POWER_OFFSET    0xF0000
+#define SW_WATCHDOG_REASON 13
+
+#define BOOTDATA_OFFSET 0xF8000
+#define MAX_ATTEMPTS 5
+
+#define FAILSAFE_BOOT 1
+#define SYSTEM_BOOT   2
+
+#define WRITE_FLASH16(a, d)      \
+do                              \
+{                               \
+  *((volatile u16 *) (a)) = (d);\
+ } while(0)
+
+static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
+{
+	u16 data;
+	volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
+
+	if ((System != FAILSAFE_BOOT) & (System != SYSTEM_BOOT)) {
+		printf ("Invalid system data %u, setting failsafe\n", System);
+		System = FAILSAFE_BOOT;
+	}
+
+	if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
+		printf ("Invalid boot count %u, setting 1\n", Count);
+		Count = 1;
+	}
+
+	if (System == FAILSAFE_BOOT) {
+		printf ("Setting failsafe boot in flash\n");
+	} else {
+		printf ("Setting system boot in flash\n");
+	}
+	printf ("Boot attempt %d\n", Count);
+
+	data = (System << 8) | Count;
+	/* AMD 16 bit */
+	WRITE_FLASH16 (&flash[0x555], 0xAAAA);
+	WRITE_FLASH16 (&flash[0x2AA], 0x5555);
+	WRITE_FLASH16 (&flash[0x555], 0xA0A0);
+
+	WRITE_FLASH16 (addr, data);
+}
+
+static void maybe_update_restart_reason (volatile u32 * addr32)
+{
+	/* Update addr if sw wd restart */
+	volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
+	volatile u16 *addr_16 = (u16 *) addr32;
+	u32 rsr;
+
+	/* Dont reset register now */
+	rsr = ((volatile immap_t *) CFG_IMMR)->im_clkrst.car_rsr;
+
+	rsr >>= 24;
+
+	if (rsr & 0x10) {
+		/* Was really a sw wd restart, update reason */
+
+		printf ("Last restart by software watchdog\n");
+
+		/* AMD 16 bit */
+		WRITE_FLASH16 (&flash[0x555], 0xAAAA);
+		WRITE_FLASH16 (&flash[0x2AA], 0x5555);
+		WRITE_FLASH16 (&flash[0x555], 0xA0A0);
+
+		WRITE_FLASH16 (addr_16, 0);
+
+		udelay (1000);
+
+		WATCHDOG_RESET ();
+
+		/* AMD 16 bit */
+		WRITE_FLASH16 (&flash[0x555], 0xAAAA);
+		WRITE_FLASH16 (&flash[0x2AA], 0x5555);
+		WRITE_FLASH16 (&flash[0x555], 0xA0A0);
+
+		WRITE_FLASH16 (addr_16 + 1, SW_WATCHDOG_REASON);
+
+	}
+}
+
+static void check_restart_reason (void)
+{
+	/* Update restart reason if sw watchdog was
+	   triggered */
+
+	int i;
+	volatile u32 *raddr;
+
+	raddr = (u32 *) (CFG_FLASH_BASE + POWER_OFFSET);
+
+	if (*raddr == 0xFFFFFFFF) {
+		/* Nothing written */
+		maybe_update_restart_reason (raddr);
+	} else {
+		/* Search for latest written reason */
+		i = 0;
+		while ((*(raddr + 2) != 0xFFFFFFFF) & (i < 2000)) {
+			raddr += 2;
+			i++;
+		}
+		if (i >= 2000) {
+			/* Whoa, dont write any more */
+			printf ("*** No free restart reason found ***\n");
+		} else {
+			/* Check if written */
+			if (*raddr == 0) {
+				/* Erased by kernel, no new reason written */
+				maybe_update_restart_reason (raddr + 2);
+			}
+		}
+	}
+}
+
+static void check_boot_tries (void)
+{
+	/* Count the number of boot attemps
+	   switch system if too many */
+
+	int i;
+	volatile u16 *addr;
+	volatile u16 data;
+	int failsafe = 1;
+	u8 system;
+	u8 count;
+
+	addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET);
+
+	if (*addr == 0xFFFF) {
+		printf ("*** No bootdata exists. ***\n");
+		write_bootdata (addr, FAILSAFE_BOOT, 1);
+	} else {
+		/* Search for latest written bootdata */
+		i = 0;
+		while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
+			addr++;
+			i++;
+		}
+		if (i >= 8000) {
+			/* Whoa, dont write any more */
+			printf ("*** No bootdata found. Not updating flash***\n");
+		} else {
+			/* See how many times we have tried to boot real system */
+			data = *addr;
+			system = data >> 8;
+			count = data & 0xFF;
+			if ((system != SYSTEM_BOOT) & (system != FAILSAFE_BOOT)) {
+				printf ("*** Wrong system %d\n", system);
+				system = FAILSAFE_BOOT;
+				count = 1;
+			} else {
+				switch (count) {
+				case 0:
+				case 1:
+				case 2:
+				case 3:
+				case 4:
+					/* Try same system again if needed */
+					count++;
+					break;
+
+				case 5:
+					/* Switch system and reset tries */
+					count = 1;
+					system = 3 - system;
+					printf ("***Too many boot attempts, switching system***\n");
+					break;
+				default:
+					/* Switch system, start over and hope it works */
+					printf ("***Unexpected data on addr 0x%x, %u***\n",
+							(u32) addr, data);
+					count = 1;
+					system = 3 - system;
+				}
+			}
+			write_bootdata (addr + 1, system, count);
+			if (system == SYSTEM_BOOT) {
+				failsafe = 0;
+			}
+		}
+	}
+	if (failsafe) {
+		printf ("Booting failsafe system\n");
+		setenv ("bootargs", "panic=1 root=/dev/hda7");
+		setenv ("bootcmd", "disk 100000 0:5;bootm 100000");
+	} else {
+		printf ("Using normal system\n");
+		setenv ("bootargs", "panic=1 root=/dev/hda4");
+		setenv ("bootcmd", "disk 100000 0:2;bootm 100000");
+	}
+}
+
+int misc_init_r (void)
+{
+	u8 Rx[80];
+	u8 Tx[5];
+	int page;
+	int read = 0;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	/* Kill fpga */
+	immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG | PA_FL_CE);
+	immap->im_ioport.iop_padir |= (PA_FL_CONFIG | PA_FL_CE);
+	immap->im_ioport.iop_paodr &= ~(PA_FL_CONFIG | PA_FL_CE);
+
+	/* Enable fpga, active low */
+	immap->im_ioport.iop_padat &= ~PA_FL_CE;
+
+	/* Start configuration */
+	immap->im_ioport.iop_padat &= ~PA_FL_CONFIG;
+	udelay (2);
+
+	immap->im_ioport.iop_padat |= (PA_FL_CONFIG | PA_FL_CE);
+
+	/* Check if we need to boot failsafe system */
+	check_boot_tries ();
+
+	/* Check if we need to update restart reason */
+	check_restart_reason ();
+
+	if (ee_init_data ()) {
+		printf ("EEPROM init failed\n");
+		return (0);
+	}
+
+	/* Read the pages where ethernet address is stored */
+
+	for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
+		/* Copy from nvram to scratchpad */
+		Tx[0] = RECALL_MEMORY;
+		Tx[1] = page;
+		if (ee_do_command (Tx, 2, NULL, 0, TRUE)) {
+			printf ("EE user page %d recall failed\n", page);
+			return (0);
+		}
+
+		Tx[0] = READ_SCRATCHPAD;
+		if (ee_do_command (Tx, 2, Rx + read, 9, TRUE)) {
+			printf ("EE user page %d read failed\n", page);
+			return (0);
+		}
+		/* Crc in 9:th byte */
+		if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
+			printf ("EE read failed, page %d. CRC error\n", page);
+			return (0);
+		}
+		read += 8;
+	}
+
+	/* Add eos after eth addr */
+	Rx[17] = 0;
+
+	printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
+
+	if ((Rx[2] != ':') |
+		(Rx[5] != ':') |
+		(Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
+		printf ("*** ethernet addr invalid, using default ***\n");
+	} else {
+		setenv ("ethaddr", (char *)Rx);
+	}
+	return (0);
+}
diff --git a/board/gth/u-boot.lds b/board/gth/u-boot.lds
new file mode 100755
index 0000000..8ac4bda
--- /dev/null
+++ b/board/gth/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/gw8260/Makefile b/board/gw8260/Makefile
new file mode 100755
index 0000000..827a6ac
--- /dev/null
+++ b/board/gw8260/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= gw8260.o flash.o
+SOBJS   :=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/gw8260/config.mk b/board/gw8260/config.mk
new file mode 100755
index 0000000..ca0540d
--- /dev/null
+++ b/board/gw8260/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MBX8xx boards
+#
+
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c
new file mode 100755
index 0000000..5620a1d
--- /dev/null
+++ b/board/gw8260/flash.c
@@ -0,0 +1,523 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Oliver Brown <oliverb@alumni.utexas.net>
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*********************************************************************/
+/* DESCRIPTION:
+ *   This file contains the flash routines for the GW8260 board.
+ *
+ *
+ *
+ * MODULE DEPENDENCY:
+ *   None
+ *
+ *
+ * RESTRICTIONS/LIMITATIONS:
+ *
+ *   Only supports the following flash devices:
+ *     AMD 29F080B
+ *     AMD 29F016D
+ *
+ * Copyright (c) 2001, Advent Networks, Inc.
+ *
+ */
+/*********************************************************************/
+
+#include <common.h>
+#include <mpc8260.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*********************************************************************/
+/*		      functions					     */
+/*********************************************************************/
+
+/*********************************************************************/
+/* NAME: flash_init() -	 initializes flash banks		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function initializes the flash bank(s).		     */
+/*								     */
+/* RETURNS:							     */
+/*   The size in bytes of the flash				     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+unsigned long flash_init (void)
+{
+    unsigned long size;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* for now, only support the 4 MB Flash SIMM */
+    size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]);
+
+    /*
+     * protect monitor and environment sectors
+     */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_MONITOR_BASE,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_ENV_ADDR,
+		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+
+    return (CFG_FLASH0_SIZE * 1024 * 1024);  /*size*/
+}
+
+/*********************************************************************/
+/* NAME: flash_print_info() - prints flash imformation		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function prints the flash information.		     */
+/*								     */
+/* INPUTS:							     */
+/*   flash_info_t *info - flash information structure		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays flash information to console			     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch ((info->flash_id >> 16) & 0xff) {
+    case 0x1:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F080B:
+	printf ("AM29F080B (8 Mbit)\n");
+	break;
+    case AMD_ID_F016D:
+	printf ("AM29F016D (16 Mbit)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+	    info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	if ((i % 5) == 0)
+	    printf ("\n	  ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "	   "
+	    );
+    }
+    printf ("\n");
+    return;
+}
+
+/*********************************************************************/
+/*   The following code cannot be run from FLASH!		     */
+/*********************************************************************/
+
+/*********************************************************************/
+/* NAME: flash_get_size() - detects the flash size		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   1) Reads vendor ID and devices ID from the flash devices.	     */
+/*   2) Initializes flash info struct.				     */
+/*   3) Return the flash size					     */
+/*								     */
+/* INPUTS:							     */
+/*   vu_long *addr	- pointer to start of flash		     */
+/*   flash_info_t *info - flash information structure		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   Size of the flash in bytes, or 0 if device id is unknown.	     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   Only supports the following devices:			     */
+/*     AM29F080D						     */
+/*     AM29F016D						     */
+/*								     */
+/*********************************************************************/
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    vu_long vendor, devid;
+    ulong base = (ulong)addr;
+
+    /*printf("addr   = %08lx\n", (unsigned long)addr); */
+
+    /* Reset and Write auto select command: read Manufacturer ID */
+    addr[0x0000] = 0xf0f0f0f0;
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x90909090;
+    udelay (1000);
+
+    vendor = addr[0];
+    /*printf("vendor = %08lx\n", vendor); */
+    if (vendor != 0x01010101) {
+	info->size = 0;
+	goto out;
+    }
+
+    devid = addr[1];
+    /*printf("devid  = %08lx\n", devid); */
+
+    if ((devid & 0xff) == AMD_ID_F080B) {
+	info->flash_id	   = (vendor & 0xff) << 16 | AMD_ID_F080B;
+	/* we have 16 sectors with 64KB each x 4 */
+	info->sector_count = 16;
+	info->size	   = 4 * info->sector_count * 64*1024;
+    } else if ((devid & 0xff) == AMD_ID_F016D){
+	info->flash_id	   = (vendor & 0xff) << 16 | AMD_ID_F016D;
+	/* we have 32 sectors with 64KB each x 4 */
+	info->sector_count = 32;
+	info->size	   = 4 * info->sector_count * 64*1024;
+    } else {
+	info->size = 0;
+	goto out;
+    }
+    /*printf("sector count = %08x\n", info->sector_count); */
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	addr = (volatile unsigned long *)(info->start[i]);
+	info->protect[i] = addr[2] & 1;
+    }
+
+    /* reset command */
+    addr = (vu_long *)info->start[0];
+
+  out:
+    addr[0] = 0xf0f0f0f0;
+
+    /*printf("size = %08x\n", info->size); */
+    return info->size;
+}
+
+/*********************************************************************/
+/* NAME: flash_erase() - erases flash by sector			     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function erases flash sectors starting for s_first to	     */
+/*   s_last.							     */
+/*								     */
+/* INPUTS:							     */
+/*   flash_info_t *info - flash information structure		     */
+/*   int s_first - first sector to erase			     */
+/*   int s_last	 - last sector to erase				     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   Returns 0 for success, 1 for failure.			     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*********************************************************************/
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x80808080;
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    udelay (100);
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (vu_long*)(info->start[sect]);
+	    addr[0] = 0x30303030;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+	goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_long*)(info->start[l_sect]);
+    while ((addr[0] & 0x80808080) != 0x80808080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+  DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned long *)info->start[0];
+    addr[0] = 0xF0F0F0F0;   /* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*********************************************************************/
+/* NAME: write_buff() - writes a buffer to flash		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function copies a buffer, *src, to flash.		     */
+/*								     */
+/* INPUTS:							     */
+/*  flash_info_t *info - flash information structure		     */
+/*  uchar *src - pointer to buffer to write to flash		     */
+/*  ulong addr - address to start write at			     */
+/*  ulong cnt - number of bytes to write to flash		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 - OK							     */
+/*   1 - write timeout						     */
+/*   2 - Flash not erased					     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*********************************************************************/
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i = 0, cp = wp; i < l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; (i < 4) && (cnt > 0); ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; (cnt == 0) && (i < 4); ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i = 0; i < 4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i = 0, cp = wp; (i < 4) && (cnt > 0); ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; (i < 4); ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*********************************************************************/
+/* NAME: write_word() - writes a word to flash			     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This writes a single word to flash.			     */
+/*								     */
+/* INPUTS:							     */
+/*  flash_info_t *info - flash information structure		     */
+/*  ulong dest - address to write				     */
+/*  ulong data - data to write					     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 - OK							     */
+/*   1 - write timeout						     */
+/*   2 - Flash not erased					     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*********************************************************************/
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_long *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0xA0A0A0A0;
+
+    *((vu_long *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+/*********************************************************************/
+/*			   End of flash.c			     */
+/*********************************************************************/
diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c
new file mode 100755
index 0000000..2719a95
--- /dev/null
+++ b/board/gw8260/gw8260.c
@@ -0,0 +1,659 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Oliver Brown <oliverb@alumni.utexas.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*********************************************************************/
+/* DESCRIPTION:
+ *   This file contains the board routines for the GW8260 board.
+ *
+ * MODULE DEPENDENCY:
+ *   None
+ *
+ * RESTRICTIONS/LIMITATIONS:
+ *   None
+ *
+ * Copyright (c) 2001, Advent Networks, Inc.
+ */
+/*********************************************************************/
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ */
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	       conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   0,	 0,   1,   0,	0   }, /* TP14		*/
+	/* PA30 */ {   1,   1,	 1,   1,   0,	0   }, /* US_RTS	*/
+	/* PA29 */ {   1,   0,	 0,   1,   0,	1   }, /* LSSI_DATA	*/
+	/* PA28 */ {   1,   0,	 0,   1,   0,	1   }, /* LSSI_CLK	*/
+	/* PA27 */ {   1,   0,	 0,   1,   0,	0   }, /* TP12		*/
+	/* PA26 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_STATUS	*/
+	/* PA25 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_CLOCK	*/
+	/* PA24 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_CONFIG	*/
+	/* PA23 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_DONE	*/
+	/* PA22 */ {   1,   0,	 0,   0,   0,	0   }, /* IO_DATA	*/
+	/* PA21 */ {   1,   1,	 0,   1,   0,	0   }, /* US_TXD3	*/
+	/* PA20 */ {   1,   1,	 0,   1,   0,	0   }, /* US_TXD2	*/
+	/* PA19 */ {   1,   1,	 0,   1,   0,	0   }, /* US_TXD1	*/
+	/* PA18 */ {   1,   1,	 0,   1,   0,	0   }, /* US_TXD0	*/
+	/* PA17 */ {   1,   1,	 0,   0,   0,	0   }, /* DS_RXD0	*/
+	/* PA16 */ {   1,   1,	 0,   0,   0,	0   }, /* DS_RXD1	*/
+	/* PA15 */ {   1,   1,	 0,   0,   0,	0   }, /* DS_RXD2	*/
+	/* PA14 */ {   1,   1,	 0,   0,   0,	0   }, /* DS_RXD3	*/
+	/* PA13 */ {   1,   0,	 0,   1,   0,	0   }, /* SPARE7	*/
+	/* PA12 */ {   1,   0,	 0,   1,   0,	0   }, /* SPARE6	*/
+	/* PA11 */ {   1,   0,	 0,   1,   0,	0   }, /* SPARE5	*/
+	/* PA10 */ {   1,   0,	 0,   1,   0,	0   }, /* SPARE4	*/
+	/* PA9	*/ {   1,   0,	 0,   1,   0,	0   }, /* SPARE3	*/
+	/* PA8	*/ {   1,   0,	 0,   1,   0,	0   }, /* SPARE2	*/
+	/* PA7	*/ {   1,   0,	 0,   0,   0,	0   }, /* LSSI_IN	*/
+	/* PA6	*/ {   1,   0,	 0,   1,   0,	0   }, /* SPARE0	*/
+	/* PA5	*/ {   1,   0,	 0,   1,   0,	0   }, /* DEMOD_RESET_	*/
+	/* PA4	*/ {   1,   0,	 0,   1,   0,	0   }, /* MOD_RESET_	*/
+	/* PA3	*/ {   1,   0,	 0,   1,   0,	0   }, /* IO_RESET	*/
+	/* PA2	*/ {   1,   0,	 0,   1,   0,	0   }, /* TX_ENABLE	*/
+	/* PA1	*/ {   1,   0,	 0,   0,   0,	0   }, /* RX_LOCK	*/
+	/* PA0	*/ {   1,   0,	 0,   1,   0,	1   }  /* MPC_RESET_	*/
+    },
+
+    /* Port B configuration */
+    {	/*	       conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FETH0_TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_COL   */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_CRS   */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TXD3  */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TXD2  */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TXD1  */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH0_TXD0  */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RXD0  */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RXD1  */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RXD2  */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RXD3  */
+	/* PB17 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RX_DV */
+	/* PB16 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RX_ER */
+	/* PB15 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TX_ER */
+	/* PB14 */ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TX_EN */
+	/* PB13 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_COL   */
+	/* PB12 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_CRS   */
+	/* PB11 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RXD3  */
+	/* PB10 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RXD2  */
+	/* PB9	*/ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RXD1  */
+	/* PB8	*/ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RXD0  */
+	/* PB7	*/ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TXD0  */
+	/* PB6	*/ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TXD1  */
+	/* PB5	*/ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TXD2  */
+	/* PB4	*/ {   1,   1,	 0,   1,   0,	0   }, /* FETH1_TXD3  */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	       conf ppar psor pdir podr pdat */
+	/* PC31 */ {   1,   0,	 0,   1,   0,	1   }, /* FAST_RESET_	*/
+	/* PC30 */ {   1,   0,	 0,   1,   0,	1   }, /* FAST_PAUSE_	*/
+	/* PC29 */ {   1,   0,	 0,   1,   0,	0   }, /* FAST_SLEW1	*/
+	/* PC28 */ {   1,   0,	 0,   1,   0,	0   }, /* FAST_SLEW0	*/
+	/* PC27 */ {   1,   0,	 0,   1,   0,	0   }, /* TP13		*/
+	/* PC26 */ {   1,   0,	 0,   0,   0,	0   }, /* RXDECDFLG	*/
+	/* PC25 */ {   1,   0,	 0,   0,   0,	0   }, /* RXACQFAIL	*/
+	/* PC24 */ {   1,   0,	 0,   0,   0,	0   }, /* RXACQFLG	*/
+	/* PC23 */ {   1,   0,	 0,   1,   0,	0   }, /* WD_TCL	*/
+	/* PC22 */ {   1,   0,	 0,   1,   0,	0   }, /* WD_EN		*/
+	/* PC21 */ {   1,   0,	 0,   1,   0,	0   }, /* US_TXCLK	*/
+	/* PC20 */ {   1,   0,	 0,   0,   0,	0   }, /* DS_RXCLK	*/
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_RX_CLK	*/
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH0_TX_CLK	*/
+	/* PC17 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_RX_CLK	*/
+	/* PC16 */ {   1,   1,	 0,   0,   0,	0   }, /* FETH1_TX_CLK	*/
+	/* PC15 */ {   1,   0,	 0,   1,   0,	0   }, /* TX_SHUTDOWN_	*/
+	/* PC14 */ {   1,   0,	 0,   0,   0,	0   }, /* RS_232_DTR_	*/
+	/* PC13 */ {   1,   0,	 0,   0,   0,	0   }, /* TXERR		*/
+	/* PC12 */ {   1,   0,	 0,   1,   0,	1   }, /* FETH1_MDDIS	*/
+	/* PC11 */ {   1,   0,	 0,   1,   0,	1   }, /* FETH0_MDDIS	*/
+	/* PC10 */ {   1,   0,	 0,   1,   0,	0   }, /* MDC		*/
+	/* PC9	*/ {   1,   0,	 0,   1,   1,	1   }, /* MDIO		*/
+	/* PC8	*/ {   1,   0,	 0,   1,   1,	1   }, /* SER_NUM	*/
+	/* PC7	*/ {   1,   1,	 0,   0,   0,	0   }, /* US_CTS	*/
+	/* PC6	*/ {   1,   1,	 0,   0,   0,	0   }, /* DS_CD_	*/
+	/* PC5	*/ {   1,   0,	 0,   1,   0,	0   }, /* FETH1_PWRDWN	*/
+	/* PC4	*/ {   1,   0,	 0,   1,   0,	0   }, /* FETH0_PWRDWN	*/
+	/* PC3	*/ {   1,   0,	 0,   1,   0,	0   }, /* MPULED3	*/
+	/* PC2	*/ {   1,   0,	 0,   1,   0,	0   }, /* MPULED2	*/
+	/* PC1	*/ {   1,   0,	 0,   1,   0,	0   }, /* MPULED1	*/
+	/* PC0	*/ {   1,   0,	 0,   1,   0,	1   }, /* MPULED0	*/
+    },
+
+    /* Port D */
+    {	/*	       conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD30 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD29 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD28 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD27 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD26 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD25 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD24 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD23 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD22 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD21 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD20 */ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD19 */ {   1,   1,	 1,   0,   0,	0   }, /*  not used	*/
+	/* PD18 */ {   1,   1,	 1,   0,   0,	0   }, /*  not used	*/
+	/* PD17 */ {   1,   1,	 1,   0,   0,	0   }, /*  not used	*/
+	/* PD16 */ {   1,   1,	 1,   0,   0,	0   }, /*  not used	*/
+	/* PD15 */ {   1,   1,	 1,   0,   1,	1   }, /*  SDRAM_SDA	*/
+	/* PD14 */ {   1,   1,	 1,   0,   1,	1   }, /*  SDRAM_SCL	*/
+	/* PD13 */ {   1,   0,	 0,   1,   0,	0   }, /*  MPULED7	*/
+	/* PD12 */ {   1,   0,	 0,   1,   0,	0   }, /*  MPULED6	*/
+	/* PD11 */ {   1,   0,	 0,   1,   0,	0   }, /*  MPULED5	*/
+	/* PD10 */ {   1,   0,	 0,   1,   0,	0   }, /*  MPULED4	*/
+	/* PD9	*/ {   1,   1,	 0,   1,   0,	0   }, /*  RS232_TXD	*/
+	/* PD8	*/ {   1,   1,	 0,   0,   0,	0   }, /*  RD232_RXD	*/
+	/* PD7	*/ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD6	*/ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD5	*/ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD4	*/ {   1,   0,	 0,   0,   0,	0   }, /*  not used	*/
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+/*********************************************************************/
+/* NAME: checkboard() -	 Displays the board type and serial number   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays the board type and serial number			     */
+/*								     */
+/* RETURNS:							     */
+/*   Always returns 1						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int checkboard (void)
+{
+	char *str;
+
+	puts ("Board: Advent Networks gw8260\n");
+
+	str = getenv ("serial#");
+	if (str != NULL) {
+		printf ("SN:    %s\n", str);
+	}
+	return 0;
+}
+
+
+#if defined (CFG_DRAM_TEST)
+/*********************************************************************/
+/* NAME:  move64() -  moves a double word (64-bit)		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   this function performs a double word move from the data at	     */
+/*   the source pointer to the location at the destination pointer.  */
+/*								     */
+/* INPUTS:							     */
+/*   unsigned long long *src  - pointer to data to move		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   unsigned long long *dest - pointer to locate to move data	     */
+/*								     */
+/* RETURNS:							     */
+/*   None							     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*   May cloober fr0.						     */
+/*								     */
+/*********************************************************************/
+static void move64 (unsigned long long *src, unsigned long long *dest)
+{
+	asm ("lfd  0, 0(3)\n\t"	/* fpr0   =  *scr       */
+	     "stfd 0, 0(4)"	/* *dest  =  fpr0       */
+      : : : "fr0");		/* Clobbers fr0         */
+	return;
+}
+
+
+#if defined (CFG_DRAM_TEST_DATA)
+
+unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
+};
+
+/*********************************************************************/
+/* NAME:  mem_test_data() -  test data lines for shorts and opens    */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Tests data lines for shorts and opens by forcing adjacent data  */
+/*   to opposite states. Because the data lines could be routed in   */
+/*   an arbitrary manner the must ensure test patterns ensure that   */
+/*   every case is tested. By using the following series of binary   */
+/*   patterns every combination of adjacent bits is test regardless  */
+/*   of routing.						     */
+/*								     */
+/*     ...101010101010101010101010				     */
+/*     ...110011001100110011001100				     */
+/*     ...111100001111000011110000				     */
+/*     ...111111110000000011111111				     */
+/*								     */
+/*   Carrying this out, gives us six hex patterns as follows:	     */
+/*								     */
+/*     0xaaaaaaaaaaaaaaaa					     */
+/*     0xcccccccccccccccc					     */
+/*     0xf0f0f0f0f0f0f0f0					     */
+/*     0xff00ff00ff00ff00					     */
+/*     0xffff0000ffff0000					     */
+/*     0xffffffff00000000					     */
+/*								     */
+/*   The number test patterns will always be given by:		     */
+/*								     */
+/*   log(base 2)(number data bits) = log2 (64) = 6		     */
+/*								     */
+/*   To test for short and opens to other signals on our boards. we  */
+/*   simply							     */
+/*   test with the 1's complemnt of the paterns as well.	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern				     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*  Assumes only one one SDRAM bank				     */
+/*								     */
+/*********************************************************************/
+int mem_test_data (void)
+{
+	unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE;
+	unsigned long long temp64 = 0;
+	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
+	int i;
+	unsigned int hi, lo;
+
+	for (i = 0; i < num_patterns; i++) {
+		move64 (&(pattern[i]), pmem);
+		move64 (pmem, &temp64);
+
+		/* hi = (temp64>>32) & 0xffffffff;          */
+		/* lo = temp64 & 0xffffffff;                */
+		/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+
+		hi = (pattern[i] >> 32) & 0xffffffff;
+		lo = pattern[i] & 0xffffffff;
+		/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
+
+		if (temp64 != pattern[i]) {
+			printf ("\n   Data Test Failed, pattern 0x%08x%08x",
+				hi, lo);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_DATA */
+
+#if defined (CFG_DRAM_TEST_ADDRESS)
+/*********************************************************************/
+/* NAME:  mem_test_address() -	test address lines		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   This function performs a test to verify that each word im	     */
+/*   memory is uniquly addressable. The test sequence is as follows: */
+/*								     */
+/*   1) write the address of each word to each word.		     */
+/*   2) verify that each location equals its address		     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_address (void)
+{
+	volatile unsigned int *pmem =
+		(volatile unsigned int *) CFG_SDRAM_BASE;
+	const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024) / 4;
+	unsigned int i;
+
+	/* write address to each location */
+	for (i = 0; i < size; i++) {
+		pmem[i] = i;
+	}
+
+	/* verify each loaction */
+	for (i = 0; i < size; i++) {
+		if (pmem[i] != i) {
+			printf ("\n   Address Test Failed at 0x%x", i);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_ADDRESS */
+
+#if defined (CFG_DRAM_TEST_WALK)
+/*********************************************************************/
+/* NAME:   mem_march() -  memory march				     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Marches up through memory. At each location verifies rmask if   */
+/*   read = 1. At each location write wmask if	write = 1. Displays  */
+/*   failing address and pattern.				     */
+/*								     */
+/* INPUTS:							     */
+/*   volatile unsigned long long * base - start address of test	     */
+/*   unsigned int size - number of dwords(64-bit) to test	     */
+/*   unsigned long long rmask - read verify mask		     */
+/*   unsigned long long wmask - wrtie verify mask		     */
+/*   short read - verifies rmask if read = 1			     */
+/*   short write  - writes wmask if write = 1			     */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays failing test pattern and address			     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_march (volatile unsigned long long *base,
+	       unsigned int size,
+	       unsigned long long rmask,
+	       unsigned long long wmask, short read, short write)
+{
+	unsigned int i;
+	unsigned long long temp = 0;
+	unsigned int hitemp, lotemp, himask, lomask;
+
+	for (i = 0; i < size; i++) {
+		if (read != 0) {
+			/* temp = base[i]; */
+			move64 ((unsigned long long *) &(base[i]), &temp);
+			if (rmask != temp) {
+				hitemp = (temp >> 32) & 0xffffffff;
+				lotemp = temp & 0xffffffff;
+				himask = (rmask >> 32) & 0xffffffff;
+				lomask = rmask & 0xffffffff;
+
+				printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
+				return 1;
+			}
+		}
+		if (write != 0) {
+			/*  base[i] = wmask; */
+			move64 (&wmask, (unsigned long long *) &(base[i]));
+		}
+	}
+	return 0;
+}
+#endif /* CFG_DRAM_TEST_WALK */
+
+/*********************************************************************/
+/* NAME:   mem_test_walk() -  a simple walking ones test	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Performs a walking ones through entire physical memory. The     */
+/*   test uses as series of memory marches, mem_march(), to verify   */
+/*   and write the test patterns to memory. The test sequence is as  */
+/*   follows:							     */
+/*     1) march writing 0000...0001				     */
+/*     2) march verifying 0000...0001  , writing  0000...0010	     */
+/*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
+/*	   the write mask equals 1000...0000			     */
+/*     4) march verifying 1000...0000				     */
+/*   The test fails if any of the memory marches return a failure.   */
+/*								     */
+/* OUTPUTS:							     */
+/*   Displays which pass on the memory test is executing	     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int mem_test_walk (void)
+{
+	unsigned long long mask;
+	volatile unsigned long long *pmem =
+		(volatile unsigned long long *) CFG_SDRAM_BASE;
+	const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024) / 8;
+
+	unsigned int i;
+
+	mask = 0x01;
+
+	printf ("Initial Pass");
+	mem_march (pmem, size, 0x0, 0x1, 0, 1);
+
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+	printf ("		");
+	printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
+
+	for (i = 0; i < 63; i++) {
+		printf ("Pass %2d", i + 2);
+		if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
+			/*printf("mask: 0x%x, pass: %d, ", mask, i); */
+			return 1;
+		}
+		mask = mask << 1;
+		printf ("\b\b\b\b\b\b\b");
+	}
+
+	printf ("Last Pass");
+	if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
+		/* printf("mask: 0x%x", mask); */
+		return 1;
+	}
+	printf ("\b\b\b\b\b\b\b\b\b");
+	printf ("	     ");
+	printf ("\b\b\b\b\b\b\b\b\b");
+
+	return 0;
+}
+
+/*********************************************************************/
+/* NAME:    testdram() -  calls any enabled memory tests	     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Runs memory tests if the environment test variables are set to  */
+/*   'y'.							     */
+/*								     */
+/* INPUTS:							     */
+/*   testdramdata    - If set to 'y', data test is run.		     */
+/*   testdramaddress - If set to 'y', address test is run.	     */
+/*   testdramwalk    - If set to 'y', walking ones test is run	     */
+/*								     */
+/* OUTPUTS:							     */
+/*   None							     */
+/*								     */
+/* RETURNS:							     */
+/*   0 -  Passed test						     */
+/*   1 -  Failed test						     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+int testdram (void)
+{
+	char *s;
+	int rundata, runaddress, runwalk;
+
+	s = getenv ("testdramdata");
+	rundata = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramaddress");
+	runaddress = (s && (*s == 'y')) ? 1 : 0;
+	s = getenv ("testdramwalk");
+	runwalk = (s && (*s == 'y')) ? 1 : 0;
+
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("Testing RAM ... ");
+	}
+#ifdef CFG_DRAM_TEST_DATA
+	if (rundata == 1) {
+		if (mem_test_data () == 1) {
+			return 1;
+		}
+	}
+#endif
+#ifdef CFG_DRAM_TEST_ADDRESS
+	if (runaddress == 1) {
+		if (mem_test_address () == 1) {
+			return 1;
+		}
+	}
+#endif
+#ifdef CFG_DRAM_TEST_WALK
+	if (runwalk == 1) {
+		if (mem_test_walk () == 1) {
+			return 1;
+		}
+	}
+#endif
+	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
+		printf ("passed");
+	}
+	return 0;
+
+}
+#endif /* CFG_DRAM_TEST */
+
+/*********************************************************************/
+/* NAME: initdram() -  initializes SDRAM controller		     */
+/*								     */
+/* DESCRIPTION:							     */
+/*   Initializes the MPC8260's SDRAM controller.		     */
+/*								     */
+/* INPUTS:							     */
+/*   CFG_IMMR	    -  MPC8260 Internal memory map		     */
+/*   CFG_SDRAM_BASE -  Physical start address of SDRAM		     */
+/*   CFG_PSDMR -       SDRAM mode register			     */
+/*   CFG_MPTPR -       Memory refresh timer prescaler register	     */
+/*   CFG_SDRAM0_SIZE - SDRAM size				     */
+/*								     */
+/* RETURNS:							     */
+/*   SDRAM size in bytes					     */
+/*								     */
+/* RESTRICTIONS/LIMITATIONS:					     */
+/*								     */
+/*								     */
+/*********************************************************************/
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
+	ulong psdmr = CFG_PSDMR;
+	int i;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++) {
+		*ramaddr = c;
+	}
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+	/* return total ram size */
+	return (CFG_SDRAM0_SIZE * 1024 * 1024);
+}
+
+/*********************************************************************/
+/*			   End of gw8260.c			     */
+/*********************************************************************/
diff --git a/board/gw8260/u-boot.lds b/board/gw8260/u-boot.lds
new file mode 100755
index 0000000..ab65cb1
--- /dev/null
+++ b/board/gw8260/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/hermes/Makefile b/board/hermes/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/hermes/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/hermes/config.mk b/board/hermes/config.mk
new file mode 100755
index 0000000..008165f
--- /dev/null
+++ b/board/hermes/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Multidata HERMES-PRO ISDN Routers
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/hermes/flash.c b/board/hermes/flash.c
new file mode 100755
index 0000000..799fe83
--- /dev/null
+++ b/board/hermes/flash.c
@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) |
+				(memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	uchar value;
+	vu_char *caddr = (vu_char *)addr;
+	ulong base = (ulong)addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0AAA] = 0xAA;
+	caddr[0x0555] = 0x55;
+	caddr[0x0AAA] = 0x90;
+
+	value = caddr[0];
+	switch (value) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = caddr[2];			/* device ID		*/
+
+	switch (value) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+#if 0	/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[4] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *)info->start[0];
+
+		*caddr = 0xF0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0AAA] = 0xAA;
+	addr[0x0555] = 0x55;
+	addr[0x0AAA] = 0x80;
+	addr[0x0AAA] = 0xAA;
+	addr[0x0555] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char*)(info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_char*)(info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_char *)info->start[0];
+	addr[0] = 0xF0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0AAA] = 0xAA;
+	addr[0x0555] = 0x55;
+	addr[0x0AAA] = 0xA0;
+
+	*((vu_char *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c
new file mode 100755
index 0000000..e95d9ee
--- /dev/null
+++ b/board/hermes/hermes.c
@@ -0,0 +1,605 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <mpc8xx.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+static ulong board_init (void);
+static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
+							uchar * msg);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,					/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1fe77c35, 0xffaffc34, 0x1fa57c35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00,
+	0xf0afcc00, 0xe1bb8c06, 0x1ff77c47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07,		/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7ffffc07,					/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (HERMES...)
+ *
+ * Return code for board revision and network speed
+ */
+
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char *s = getenv ("serial#");
+	char *e;
+
+	puts ("Board: ");
+
+	if (!s || strncmp (s, "HERMES", 6)) {
+		puts ("### No HW ID - assuming HERMES-PRO");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		for (; s < e; ++s) {
+			putc (*s);
+		}
+	}
+
+	gd->board_type = board_init ();
+
+	printf ("  Rev. %ld.x\n", (gd->board_type >> 16));
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size, size8, size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = 0x0400;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 1 to the SDRAM banks at preliminary address
+	 */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	/* HERMES-PRO boards have only one bank SDRAM */
+
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mamr = 0xD0802114;
+	memctl->memc_mcr = 0x80002105;
+	udelay (1);
+	memctl->memc_mamr = 0xD0802118;
+	memctl->memc_mcr = 0x80002130;
+	udelay (1);
+	memctl->memc_mamr = 0xD0802114;
+	memctl->memc_mcr = 0x80002106;
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {					/* back to 8 columns            */
+		size = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
+	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	udelay (10000);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define	PB_LED_3	0x00020000	/* Status LED's */
+#define PB_LED_2	0x00010000
+#define PB_LED_1	0x00008000
+#define PB_LED_0	0x00004000
+
+#define PB_LED_ALL	(PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3)
+
+#define	PC_REP_SPD1	0x00000800
+#define PC_REP_SPD0	0x00000400
+
+#define PB_RESET_2081	0x00000020	/* Reset PEB2081 */
+
+#define PB_MAI_4	0x00000010	/* Configuration */
+#define PB_MAI_3	0x00000008
+#define PB_MAI_2	0x00000004
+#define PB_MAI_1	0x00000002
+#define PB_MAI_0	0x00000001
+
+#define PB_MAI_ALL	(PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4)
+
+
+#define	PC_REP_MGRPRS	0x0200
+#define PC_REP_SPD	0x0040		/* Select 100 Mbps */
+#define PC_REP_RES	0x0004
+#define PC_BIT14	0x0002		/* ??? */
+#define PC_BIT15	0x0001		/* ??? ENDSL ?? */
+
+/* ------------------------------------------------------------------------- */
+
+static ulong board_init (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	ulong reg, revision, speed = 100;
+	int ethspeed;
+	char *s;
+
+	if ((s = getenv ("ethspeed")) != NULL) {
+		if (strcmp (s, "100") == 0) {
+			ethspeed = 100;
+		} else if (strcmp (s, "10") == 0) {
+			ethspeed = 10;
+		} else {
+			ethspeed = 0;
+		}
+	} else {
+		ethspeed = 0;
+	}
+
+	/* Configure Port B Output Pins => 0x0003cc3F */
+	reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 |
+			PB_MAI_ALL;
+	immr->im_cpm.cp_pbpar &= ~reg;
+	immr->im_cpm.cp_pbodr &= ~reg;
+	immr->im_cpm.cp_pbdat &= ~reg;	/* all 0 */
+	immr->im_cpm.cp_pbdir |= reg;
+
+	/* Check hardware revision */
+	if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
+		/*
+		 * Revision 3.x hardware
+		 */
+		revision = 3;
+
+		immr->im_ioport.iop_pcdat = 0x0240;
+		immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14);	/* = 0x0246 */
+		immr->im_ioport.iop_pcdat |= PC_REP_RES;
+	} else {
+		immr->im_ioport.iop_pcdat = 0x0002;
+		immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15);	/* = 0x0207 */
+
+		if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
+			/*
+			 * Revision 2.x hardware: PC9 connected to PB21
+			 */
+			revision = 2;
+
+			if (ethspeed == 0) {
+				/* both 10 and 100 Mbps allowed:
+				 * select 10 Mbps and autonegotiation
+				 */
+				puts ("  [10+100]");
+				immr->im_cpm.cp_pbdat = 0;	/* SPD1:SPD0 = 0:0 - autonegot. */
+				speed = 10;
+			} else if (ethspeed == 10) {
+				/* we are asked for 10 Mbps,
+				 * so select 10 Mbps
+				 */
+				puts ("  [10]");
+				immr->im_cpm.cp_pbdat = 0;	/* ??? */
+				speed = 10;
+			} else {
+				/* anything else:
+				 * select 100 Mbps
+				 */
+				puts ("  [100]");
+				immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
+				/* SPD1:SPD0 = 1:1 - 100 Mbps */
+				speed = 100;
+			}
+			immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);
+
+			/* must be run from RAM  */
+			/* start_lxt980 (speed); */
+		/*************************/
+		} else {
+			/*
+			 * Revision 1.x hardware
+			 */
+			revision = 1;
+
+			immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14;	/* = 0x0202 */
+			immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15);	/* = 0x0247 */
+
+			if (ethspeed == 0) {
+				/* both 10 and 100 Mbps allowed:
+				 * select 100 Mbps and autonegotiation
+				 */
+				puts ("  [10+100]");
+				immr->im_cpm.cp_pbdat = 0;	/* SPD1:SPD0 = 0:0 - autonegot. */
+				immr->im_ioport.iop_pcdat |= PC_REP_SPD;
+			} else if (ethspeed == 10) {
+				/* we are asked for 10 Mbps,
+				   * so select 10 Mbps
+				 */
+				puts ("  [10]");
+				immr->im_cpm.cp_pbdat = PC_REP_SPD0;	/* SPD1:SPD0 = 0:1 - 10 Mbps */
+			} else {
+				/* anything else:
+				   * select 100 Mbps
+				 */
+				puts ("  [100]");
+				immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
+				/* SPD1:SPD0 = 1:1 - 100 Mbps */
+				immr->im_ioport.iop_pcdat |= PC_REP_SPD;
+			}
+
+			immr->im_ioport.iop_pcdat |= PC_REP_RES;
+		}
+	}
+	SHOW_BOOT_PROGRESS (0x00);
+
+	return ((revision << 16) | (speed & 0xFFFF));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define SCC_SM		1			/* Index => SCC2 */
+#define	PROFF		PROFF_SCC2
+
+#define SMI_MSGLEN	8			/* Length of SMI Messages        */
+
+#define PHYGPCR_ADDR	0x109	/* Port Enable               */
+#define PHYPCR_ADDR	0x132		/* PHY Port Control Reg. (port 1)    */
+#define LEDPCR_ADDR	0x141		/* LED Port Control Reg.         */
+#define RPRESET_ADDR	0x144	/* Repeater Reset            */
+
+#define PHYPCR_SPEED	0x2000	/* on for 100 Mbps, off for 10 Mbps  */
+#define PHYPCR_AN	0x1000		/* on to enable  Auto-Negotiation    */
+#define PHYPCR_REST_AN	0x0200	/* on to restart Auto-Negotiation    */
+#define PHYPCR_FDX	0x0100		/* on for Full Duplex, off for HDX   */
+#define PHYPCR_COLT	0x0080		/* on to enable COL signal test      */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Must run from RAM:
+ * uses parameter RAM area which is used for stack while running from ROM
+ */
+void hermes_start_lxt980 (int speed)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
+	volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
+	volatile cbd_t *bd;
+	volatile hdlc_pram_t *hp;
+	uchar smimsg[SMI_MSGLEN];
+	ushort phypcrval;
+	uint bd_off;
+	int pnr;
+
+	printf ("LXT9880: %3d Mbps\n", speed);
+
+	immr->im_ioport.iop_paodr |= 0x0008;	/* init PAODR: PA12 (TXD2) open drain */
+	immr->im_ioport.iop_papar |= 0x400c;	/* init PAPAR: TXD2, RXD2, BRGO4 */
+	immr->im_ioport.iop_padir &= 0xbff3;	/* init PADIR: BRGO4 */
+	immr->im_ioport.iop_padir |= 0x4000;
+
+	/* get temporary BD; no need for permanent alloc */
+	bd_off = dpram_base_align (8);
+
+	bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off);
+
+	bd->cbd_bufaddr = 0;
+	bd->cbd_datlen = 0;
+	bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC;
+
+	/* init. baudrate generator BRG4 */
+	cp->cp_brgc4 = (0x00010000 | (50 << 1));	/* output 1 MHz */
+
+	cp->cp_sicr &= 0xFFFF00FF;	/* SICR: mask SCC2 */
+	cp->cp_sicr |= 0x00001B00;	/* SICR: SCC2 clk BRG4 */
+
+	/* init SCC_SM register */
+	sp->scc_psmr = 0x0000;		/* init PSMR: no additional flags */
+	sp->scc_todr = 0x0000;
+	sp->scc_dsr = 0x7e7e;
+
+	/* init. SCC_SM parameter area */
+	hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF];
+
+	hp->tbase = bd_off;			/* offset from beginning of DPRAM */
+
+	hp->rfcr = 0x18;
+	hp->tfcr = 0x18;
+	hp->mrblr = 10;
+
+	hp->c_mask = 0x0000f0b8;
+	hp->c_pres = 0x0000ffff;
+
+	hp->disfc = 0;
+	hp->crcec = 0;
+	hp->abtsc = 0;
+	hp->nmarc = 0;
+	hp->retrc = 0;
+
+	hp->mflr = 10;
+
+	hp->rfthr = 1;
+
+	hp->hmask = 0;
+	hp->haddr1 = 0;
+	hp->haddr2 = 0;
+	hp->haddr3 = 0;
+	hp->haddr4 = 0;
+
+	cp->cp_cpcr = SCC_SM << 6 | 0x0001;	/* SCC_SM: init TX/RX params */
+	while (cp->cp_cpcr & CPM_CR_FLG);
+
+	/* clear all outstanding SCC events */
+	sp->scc_scce = ~0;
+
+	/* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
+	sp->scc_gsmrh = 0;
+	sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
+			SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC;
+
+#if 0
+	smimsg[0] = 0x00;			/* CHIP/HUB ID */
+	smimsg[1] = 0x38;			/* WRITE CMD */
+	smimsg[2] = (RPRESET_ADDR << 4) & 0xf0;
+	smimsg[3] = RPRESET_ADDR >> 4;
+	smimsg[4] = 0x01;
+	smimsg[5] = 0x00;
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+#endif
+
+	smimsg[0] = 0x7f;			/* BROADCAST */
+	smimsg[1] = 0x34;			/* ASSIGN HUB ID */
+	smimsg[2] = 0x00;
+	smimsg[3] = 0x00;
+	smimsg[4] = 0x00;			/* HUB ID = 0 */
+	smimsg[5] = 0x00;
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+
+	smimsg[0] = 0x7f;			/* BROADCAST */
+	smimsg[1] = 0x3c;			/* SET ARBOUT TO 0 */
+	smimsg[2] = 0x00;			/* ADDRESS = 0 */
+	smimsg[3] = 0x00;
+	smimsg[4] = 0x00;			/* DATA = 0 */
+	smimsg[5] = 0x00;
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+
+	if (speed == 100) {
+		phypcrval = PHYPCR_SPEED;	/* 100 MBIT, disable autoneg. */
+	} else {
+		phypcrval = 0;			/* 10 MBIT, disable autoneg. */
+	}
+
+	/* send MSGs */
+	for (pnr = 0; pnr < 8; pnr++) {
+		smimsg[0] = 0x00;		/* CHIP/HUB ID */
+		smimsg[1] = 0x38;		/* WRITE CMD */
+		smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0;
+		smimsg[3] = (PHYPCR_ADDR + pnr) >> 4;
+		smimsg[4] = (unsigned char) (phypcrval & 0xff);
+		smimsg[5] = (unsigned char) (phypcrval >> 8);
+		smimsg[6] = 0x00;
+		smimsg[7] = 0x00;
+
+		send_smi_frame (sp, bd, smimsg);
+	}
+
+	smimsg[0] = 0x00;			/* CHIP/HUB ID */
+	smimsg[1] = 0x38;			/* WRITE CMD */
+	smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0;
+	smimsg[3] = PHYGPCR_ADDR >> 4;
+	smimsg[4] = 0xff;			/* enable port 1-8 */
+	smimsg[5] = 0x01;			/* enable MII1 (0x01) */
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+
+	smimsg[0] = 0x00;			/* CHIP/HUB ID */
+	smimsg[1] = 0x38;			/* WRITE CMD */
+	smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0;
+	smimsg[3] = LEDPCR_ADDR >> 4;
+	smimsg[4] = 0xaa;			/* Port 1-8 Conf.bits = 10 (Hardware control) */
+	smimsg[5] = 0xaa;
+	smimsg[6] = 0x00;
+	smimsg[7] = 0x00;
+
+	send_smi_frame (sp, bd, smimsg);
+
+	/*
+	 * Disable Transmitter (so that we can free the BD, too)
+	 */
+	sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
+							uchar * msg)
+{
+#ifdef DEBUG
+	unsigned hub, chip, cmd, length, addr;
+
+	hub = msg[0] & 0x1F;
+	chip = msg[0] >> 5;
+	cmd = msg[1] & 0x1F;
+	length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
+	addr = (msg[2] >> 4) | (msg[3] << 4);
+
+	printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
+			"%02x %02x %02x %02x\n",
+			hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]);
+#endif /* DEBUG */
+
+	bd->cbd_bufaddr = (uint) msg;
+	bd->cbd_datlen = SMI_MSGLEN;
+	bd->cbd_sc |= BD_SC_READY;
+
+	/* wait for msg transmitted */
+	while ((sp->scc_scce & 0x0002) == 0);
+	/* clear all events */
+	sp->scc_scce = ~0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void show_boot_progress (int status)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	status ^= 0x0F;
+	status = (status & 0x0F) << 14;
+	immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds
new file mode 100755
index 0000000..ef53ab7
--- /dev/null
+++ b/board/hermes/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    cpu/mpc8xx/interrupts.o	(.text)
+    lib_ppc/time.o		(.text)
+    lib_ppc/ticks.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_generic/crc32.o		(.text)
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug
new file mode 100755
index 0000000..a961fa4
--- /dev/null
+++ b/board/hermes/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    cpu/mpc8xx/interrupts.o (.text)
+    lib_ppc/time.o		(.text)
+    lib_ppc/ticks.o		(.text)
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/hidden_dragon/Makefile b/board/hidden_dragon/Makefile
new file mode 100755
index 0000000..b9f1df6
--- /dev/null
+++ b/board/hidden_dragon/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS =  $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/hidden_dragon/README b/board/hidden_dragon/README
new file mode 100755
index 0000000..529fe2b
--- /dev/null
+++ b/board/hidden_dragon/README
@@ -0,0 +1,60 @@
+U-Boot for Hidden Dragon board
+------------------------------
+
+Hidden Dragon is a MPC824x-based board by Motorola. For the most
+part it is similar to Sandpoint8245 board. So unless otherwise
+mentioned, the codes in this directory are adapted from ../sandpoint
+directory.
+
+Apparently there are very few of this board out there. Even Motorola
+website does not have any info on it.
+
+RAM:
+  start = 0x0000 0000
+  size	= 0x0200 0000 (32 MB)
+
+Flash:
+  BANK ONE:
+    start = 0xFFE0 0000
+    size  = 0x0020 0000 (2 MB)
+    flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
+    flash sectors = 16K, 2x8K, 32K, 31x64K
+
+  BANK TWO:
+    NONE
+
+The processor interrupt vectors reside on the first 256 bytes
+starting from address 0xFFF00000. The "reset vector" (first
+instruction executed after reset) is located on 0xFFF0 0100.
+
+U-Boot is configured to reside in flash starting at the address of
+0xFFF00000. The environment space is located in flash separately from
+U-Boot, at the second sector of the first flash bank, starting from
+0xFFE04000 until 0xFFE06000 (8KB).
+
+Network:
+  - RTL8139 chip on the base board	  (SUPPORTED)
+  - RTL8129 chip on the processor board	  (NOT SUPPORTED)
+
+Serial:
+  - Two NS16550 compatible UART on the processor board	(SUPPORTED)
+  - One NS16550 compatible UART on the base board	(UNTESTED)
+
+Misc:
+  VIA686A PCI SuperIO peripheral controller
+  - 2 USB ports		    (UNTESTED)
+  - 2 PS2 ports		    (UNTESTED)
+  - Parallel port	    (UNTESTED)
+  - IDE & floppy interface  (UNTESTED)
+
+  S3 Savage4 video card	    (UNTESTED)
+
+TODO:
+-----
+- Support for the VIA686A based peripherals
+- The RTL8139 driver frequently gives rx error.
+- Support for RTL8129 network controller. (Why is the support removed from
+  rtl8139.c driver?)
+
+(C) Copyright 2004
+Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
diff --git a/board/hidden_dragon/config.mk b/board/hidden_dragon/config.mk
new file mode 100755
index 0000000..5c36d05
--- /dev/null
+++ b/board/hidden_dragon/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Hidden Dragon boards
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/hidden_dragon/early_init.S b/board/hidden_dragon/early_init.S
new file mode 100755
index 0000000..07dafb7
--- /dev/null
+++ b/board/hidden_dragon/early_init.S
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2001
+ * Thomas Koeller, tkoeller@gmx.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASSEMBLY__
+#define __ASSEMBLY__	1
+#endif
+
+#include <config.h>
+#include <asm/processor.h>
+#include <mpc824x.h>
+#include <ppc_asm.tmpl>
+
+#if defined(USE_DINK32)
+  /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
+  #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+#else
+  #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
+#endif
+
+	.text
+
+	/* Values to program into memory controller registers */
+tbl:	.long	MCCR1, MCCR1VAL
+	.long	MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR3
+	.long	(((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CFG_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	MCCR4
+	.long	(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CFG_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
+		(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	MSAR1
+	.long	(((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR1
+	.long	(((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MSAR2
+	.long	(((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR2
+	.long	(((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR1
+	.long	(((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR1
+	.long	(((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR2
+	.long	(((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR2
+	.long	(((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	0
+
+
+	/*
+	 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
+	 * must be done in assembly, since we have no stack at this point.
+	 */
+	.global	early_init_f
+early_init_f:
+	mflr	r10
+
+	/* basic memory controller configuration */
+	lis	r3, CONFIG_ADDR_HIGH
+	lis	r4, CONFIG_DATA_HIGH
+	bl	lab
+lab:	mflr	r5
+	lwzu	r0, tbl - lab(r5)
+loop:	lwz	r1, 4(r5)
+	stwbrx	r0, 0, r3
+	eieio
+	stwbrx	r1, 0, r4
+	eieio
+	lwzu	r0, 8(r5)
+	cmpli	cr0, 0, r0, 0
+	bne	cr0, loop
+
+	/* set bank enable bits */
+	lis	r0, MBER@h
+	ori	r0, 0, MBER@l
+	li	r1, CFG_BANK_ENABLE
+	stwbrx	r0, 0, r3
+	eieio
+	stb	r1, 0(r4)
+	eieio
+
+	/* delay loop */
+	lis	r0, 0x0003
+	mtctr   r0
+delay:	bdnz	delay
+
+	/* enable memory controller */
+	lis	r0, MCCR1@h
+	ori	r0, 0, MCCR1@l
+	stwbrx	r0, 0, r3
+	eieio
+	lwbrx	r0, 0, r4
+	oris	r0, 0, MCCR1_MEMGO@h
+	stwbrx	r0, 0, r4
+	eieio
+
+	/* set up stack pointer */
+	lis	r1, CFG_INIT_SP_OFFSET@h
+	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+
+	mtlr	r10
+	blr
diff --git a/board/hidden_dragon/flash.c b/board/hidden_dragon/flash.c
new file mode 100755
index 0000000..21c5a01
--- /dev/null
+++ b/board/hidden_dragon/flash.c
@@ -0,0 +1,575 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+#include <w83c553f.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR  (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*flash command address offsets*/
+
+#define ADDR0		(0xAAA)
+#define ADDR1		(0x555)
+#define ADDR3		(0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+	__attribute__ ((const));
+
+typedef struct {
+	FLASH_WORD_SIZE extval;
+	unsigned short intval;
+} map_entry;
+
+static unsigned long flash_id (unsigned char mfct, unsigned char chip)
+{
+	static const map_entry mfct_map[] = {
+		{(FLASH_WORD_SIZE) AMD_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+		{(FLASH_WORD_SIZE) FUJ_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+		{(FLASH_WORD_SIZE) STM_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+		{(FLASH_WORD_SIZE) MT_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_MANUFACT,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+		{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
+		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+	};
+
+	static const map_entry chip_map[] = {
+		{AMD_ID_F040B, FLASH_AM040},
+		{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
+	};
+
+	const map_entry *p;
+	unsigned long result = FLASH_UNKNOWN;
+
+	/* find chip id */
+	for (p = &chip_map[0];
+	     p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
+		if (p->extval == chip) {
+			result = FLASH_VENDMASK | p->intval;
+			break;
+		}
+
+	/* find vendor id */
+	for (p = &mfct_map[0];
+	     p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
+		if (p->extval == mfct) {
+			result &= ~FLASH_VENDMASK;
+			result |= (unsigned long) p->intval << 16;
+			break;
+		}
+
+	return result;
+}
+
+unsigned long flash_init (void)
+{
+	unsigned long i;
+	unsigned char j;
+	static const ulong flash_banks[] = CFG_FLASH_BANKS;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+
+		pflinfo->flash_id = FLASH_UNKNOWN;
+		pflinfo->size = 0;
+		pflinfo->sector_count = 0;
+	}
+
+	/* Enable writes to Hidden Dragon flash */
+	{
+		register unsigned char temp;
+
+		CONFIG_READ_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+				  temp);
+		temp &= ~0x20;	/* clear BIOSWP bit */
+		CONFIG_WRITE_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+				   temp);
+	}
+
+	for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
+		flash_info_t *const pflinfo = &flash_info[i];
+		const unsigned long base_address = flash_banks[i];
+		volatile FLASH_WORD_SIZE *const flash =
+			(FLASH_WORD_SIZE *) base_address;
+
+		flash[0xAAA << (3 * i)] = 0xaa;
+		flash[0x555 << (3 * i)] = 0x55;
+		flash[0xAAA << (3 * i)] = 0x90;
+		__asm__ __volatile__ ("sync");
+
+		pflinfo->flash_id =
+			flash_id (flash[0x0], flash[0x2 + 14 * i]);
+
+		switch (pflinfo->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			pflinfo->size = 0x00080000;
+			pflinfo->sector_count = 8;
+			for (j = 0; j < 8; j++) {
+				pflinfo->start[j] =
+					base_address + 0x00010000 * j;
+				pflinfo->protect[j] = flash[(j << 16) | 0x2];
+			}
+			break;
+		case FLASH_STM800AB:
+			pflinfo->size = 0x00100000;
+			pflinfo->sector_count = 19;
+			pflinfo->start[0] = base_address;
+			pflinfo->start[1] = base_address + 0x4000;
+			pflinfo->start[2] = base_address + 0x6000;
+			pflinfo->start[3] = base_address + 0x8000;
+			for (j = 1; j < 16; j++) {
+				pflinfo->start[j + 3] =
+					base_address + 0x00010000 * j;
+			}
+			break;
+		default:
+			/* The chip used is not listed in flash_id
+			   TODO: Change this to explicitly detect the flash type
+			 */
+			{
+				int sector_addr = base_address;
+
+				pflinfo->size = 0x00200000;
+				pflinfo->sector_count = 35;
+				pflinfo->start[0] = sector_addr;
+				sector_addr += 0x4000;	/* 16K */
+				pflinfo->start[1] = sector_addr;
+				sector_addr += 0x2000;	/* 8K */
+				pflinfo->start[2] = sector_addr;
+				sector_addr += 0x2000;	/* 8K */
+				pflinfo->start[3] = sector_addr;
+				sector_addr += 0x8000;	/* 32K */
+
+				for (j = 4; j < 35; j++) {
+					pflinfo->start[j] = sector_addr;
+					sector_addr += 0x10000;	/* 64K */
+				}
+			}
+			break;
+		}
+		/* Protect monitor and environment sectors
+		 */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_MONITOR_BASE,
+			       CFG_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR,
+			       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			       &flash_info[0]);
+#endif
+
+		/* reset device to read mode */
+		flash[0x0000] = 0xf0;
+		__asm__ __volatile__ ("sync");
+	}
+
+	/* only have 1 bank */
+	return flash_info[0].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	static const char unk[] = "Unknown";
+	const char *mfct = unk, *type = unk;
+	unsigned int i;
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			mfct = "AMD";
+			break;
+		case FLASH_MAN_FUJ:
+			mfct = "FUJITSU";
+			break;
+		case FLASH_MAN_STM:
+			mfct = "STM";
+			break;
+		case FLASH_MAN_SST:
+			mfct = "SST";
+			break;
+		case FLASH_MAN_BM:
+			mfct = "Bright Microelectonics";
+			break;
+		case FLASH_MAN_INTEL:
+			mfct = "Intel";
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			type = "AM29F040B (512K * 8, uniform sector size)";
+			break;
+		case FLASH_AM400B:
+			type = "AM29LV400B (4 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM400T:
+			type = "AM29LV400T (4 Mbit, top boot sector)";
+			break;
+		case FLASH_AM800B:
+			type = "AM29LV800B (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM800T:
+			type = "AM29LV800T (8 Mbit, top boot sector)";
+			break;
+		case FLASH_AM160T:
+			type = "AM29LV160T (16 Mbit, top boot sector)";
+			break;
+		case FLASH_AM320B:
+			type = "AM29LV320B (32 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM320T:
+			type = "AM29LV320T (32 Mbit, top boot sector)";
+			break;
+		case FLASH_STM800AB:
+			type = "M29W800AB (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_SST800A:
+			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+			break;
+		case FLASH_SST160A:
+			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+			break;
+		}
+	}
+
+	printf ("\n  Brand: %s Type: %s\n"
+		"  Size: %lu KB in %d Sectors\n",
+		mfct, type, info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; i++) {
+		unsigned long size;
+		unsigned int erased;
+		unsigned long *flash = (unsigned long *) info->start[i];
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (i != (info->sector_count - 1)) ?
+			(info->start[i + 1] - info->start[i]) >> 2 :
+			(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (flash = (unsigned long *) info->start[i], erased = 1;
+		     (flash != (unsigned long *) info->start[i] + size)
+		     && erased; flash++)
+			erased = *flash == ~0x0UL;
+
+		printf ("%s %08lX %s %s",
+			(i % 5) ? "" : "\n   ",
+			info->start[i],
+			erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
+	}
+
+	puts ("\n");
+	return;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned char sh8b;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (FLASH_WORD_SIZE *) (info->start[0] +
+						    ((info->start[sect] -
+						      info->start[0]) << sh8b));
+			if (info->flash_id & FLASH_MAN_SST) {
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] =
+					(FLASH_WORD_SIZE) 0x00550055;
+				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				udelay (30000);	/* wait 30 ms */
+			} else
+				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
+						       info->
+						       start[0]) << sh8b));
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+      DONE:
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int flag;
+	int i;
+	unsigned char sh8b;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+	    && (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
+				     info->start[0]);
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i << sh8b] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c
new file mode 100755
index 0000000..daab833
--- /dev/null
+++ b/board/hidden_dragon/hidden_dragon.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Hidden Dragon "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" ##Test not implemented yet##\n");
+	/* TODO: Implement board test */
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_hidden_dragon_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_hidden_dragon_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
diff --git a/board/hidden_dragon/speed.h b/board/hidden_dragon/speed.h
new file mode 100755
index 0000000..b66393b
--- /dev/null
+++ b/board/hidden_dragon/speed.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK	      		CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */
diff --git a/board/hidden_dragon/u-boot.lds b/board/hidden_dragon/u-boot.lds
new file mode 100755
index 0000000..2a5cd2e
--- /dev/null
+++ b/board/hidden_dragon/u-boot.lds
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/hmi1001/Makefile b/board/hmi1001/Makefile
new file mode 100755
index 0000000..ed36ea7
--- /dev/null
+++ b/board/hmi1001/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/hmi1001/config.mk b/board/hmi1001/config.mk
new file mode 100755
index 0000000..51e8e84c
--- /dev/null
+++ b/board/hmi1001/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# INKA 4X0 board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFE00000   boot high
+#
+#	0x00100000   boot from RAM (for testing only)
+#
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+#TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c
new file mode 100755
index 0000000..237e863
--- /dev/null
+++ b/board/hmi1001/hmi1001.c
@@ -0,0 +1,297 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <malloc.h>
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+/*	return dramsize + dramsize2; */
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: HMI1001\n");
+	return 0;
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[]		= "key_magic";
+static uchar kbd_command_prefix[]	= "key_cmd";
+
+#define S1_ROT	0xf0
+#define S2_Q	0x40
+#define S2_M	0x20
+
+struct kbd_data_t {
+	char s1;
+	char s2;
+};
+
+struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+{
+	kbd_data->s1 = *((volatile uchar*)(CFG_STATUS1_BASE));
+	kbd_data->s2 = *((volatile uchar*)(CFG_STATUS2_BASE));
+
+	return kbd_data;
+}
+
+static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str)
+{
+	char s1 = str[0];
+	char s2;
+
+	if (s1 >= '0' && s1 <= '9')
+		s1 -= '0';
+	else if (s1 >= 'a' && s1 <= 'f')
+		s1 = s1 - 'a' + 10;
+	else if (s1 >= 'A' && s1 <= 'F')
+		s1 = s1 - 'A' + 10;
+	else
+		return -1;
+
+	if (((S1_ROT & kbd_data->s1) >> 4) != s1)
+		return -1;
+
+	s2 = (S2_Q | S2_M) & kbd_data->s2;
+
+	switch (str[1]) {
+	case 'q':
+	case 'Q':
+		if (s2 == S2_Q)
+			return -1;
+		break;
+	case 'm':
+	case 'M':
+		if (s2 == S2_M)
+			return -1;
+		break;
+	case '\0':
+		if (s2 == (S2_Q | S2_M))
+			return 0;
+	default:
+		return -1;
+	}
+
+	if (str[2])
+		return -1;
+
+	return 0;
+}
+
+static uchar *key_match (const struct kbd_data_t *kbd_data)
+{
+	uchar magic[sizeof (kbd_magic_prefix) + 1];
+	uchar *suffix;
+	uchar *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can be appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix = kbd_magic_keys; *suffix ||
+		     suffix == kbd_magic_keys; ++suffix) {
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+
+		if (compare_magic(kbd_data, getenv(magic)) == 0) {
+			uchar cmd_name[sizeof (kbd_command_prefix) + 1];
+			char *cmd;
+
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			cmd = getenv (cmd_name);
+
+			return (cmd);
+		}
+	}
+
+	return (NULL);
+}
+
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PREBOOT
+	struct kbd_data_t kbd_data;
+	/* Decode keys */
+	uchar *str = strdup (key_match (get_keys (&kbd_data)));
+	/* Set or delete definition */
+	setenv ("preboot", str);
+	free (str);
+#endif /* CONFIG_PREBOOT */
+
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	return 0;
+}
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
diff --git a/board/hmi1001/u-boot.lds b/board/hmi1001/u-boot.lds
new file mode 100755
index 0000000..123a14c
--- /dev/null
+++ b/board/hmi1001/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the sector layout of our flash chips!    XXX FIXME XXX   */
+
+    cpu/mpc5xxx/start.o          (.text)
+    cpu/mpc5xxx/traps.o          (.text)
+    lib_generic/crc32.o         (.text)
+    lib_ppc/cache.o             (.text)
+    lib_ppc/time.o              (.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o        (.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/hymod/Makefile b/board/hymod/Makefile
new file mode 100755
index 0000000..b52af9a
--- /dev/null
+++ b/board/hymod/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c
new file mode 100755
index 0000000..0596fa4
--- /dev/null
+++ b/board/hymod/bsp.c
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <asm/iopin_8260.h>
+
+/*-----------------------------------------------------------------------
+ * Board Special Commands: FPGA load/store, EEPROM erase
+ */
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#define LOAD_SUCCESS		0
+#define LOAD_FAIL_NOCONF	1
+#define LOAD_FAIL_NOINIT	2
+#define LOAD_FAIL_NODONE	3
+
+#define STORE_SUCCESS		0
+
+/*
+ * Programming the Hymod FPGAs
+ *
+ * The 8260 io port config table is set up so that the INIT pin is
+ * held Low (Open Drain output 0) - this will delay the automatic
+ * Power-On config until INIT is released (by making it an input).
+ *
+ * If the FPGA has been programmed before, then the assertion of PROGRAM
+ * will initiate configuration (i.e. it begins clearing the RAM).
+ *
+ * When the FPGA is ready to receive configuration data (either after
+ * releasing INIT after Power-On, or after asserting PROGRAM), it will
+ * pull INIT high.
+ *
+ * Notes from Paul Dunn:
+ *
+ *  1. program pin should be forced low for >= 300ns
+ *     (about 20 bus clock cycles minimum).
+ *
+ *  2. then wait for init to go high, which signals
+ *     that the FPGA has cleared its internal memory
+ *     and is ready to load
+ *
+ *  3. perform load writes of entire config file
+ *
+ *  4. wait for done to go high, which should be
+ *     within a few bus clock cycles. If done has not
+ *     gone high after reasonable period, then load
+ *     has not worked (wait several ms?)
+ */
+
+int
+fpga_load (int mezz, uchar *addr, ulong size)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
+	xlx_info_t *fp;
+	xlx_iopins_t *fpgaio;
+	volatile uchar *fpgabase;
+	volatile uint cnt;
+	uchar *eaddr = addr + size;
+	int result;
+
+	if (mezz)
+		fp = &cp->mezz.xlx[0];
+	else
+		fp = &cp->main.xlx[0];
+
+	if (!fp->mmap.prog.exists)
+		return (LOAD_FAIL_NOCONF);
+
+	fpgabase = (uchar *)fp->mmap.prog.base;
+	fpgaio = &fp->iopins;
+
+	/* set enable HIGH if required */
+	if (fpgaio->enable_pin.flag)
+		iopin_set_high (&fpgaio->enable_pin);
+
+	/* ensure INIT is released (set it to be an input) */
+	iopin_set_in (&fpgaio->init_pin);
+
+	/* toggle PROG Low then High (will already be Low after Power-On) */
+	iopin_set_low (&fpgaio->prog_pin);
+	udelay (1);	/* minimum 300ns - 1usec should do it */
+	iopin_set_high (&fpgaio->prog_pin);
+
+	/* wait for INIT High */
+	cnt = 0;
+	while (!iopin_is_high (&fpgaio->init_pin))
+		if (++cnt == 10000000) {
+			result = LOAD_FAIL_NOINIT;
+			goto done;
+		}
+
+	/* write configuration data */
+	while (addr < eaddr)
+		*fpgabase = *addr++;
+
+	/* wait for DONE High */
+	cnt = 0;
+	while (!iopin_is_high (&fpgaio->done_pin))
+		if (++cnt == 100000000) {
+			result = LOAD_FAIL_NODONE;
+			goto done;
+		}
+
+	/* success */
+	result = LOAD_SUCCESS;
+
+  done:
+
+	if (fpgaio->enable_pin.flag)
+		iopin_set_low (&fpgaio->enable_pin);
+
+	return (result);
+}
+
+/* ------------------------------------------------------------------------- */
+int
+do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	uchar *addr, *save_addr;
+	ulong size;
+	int mezz, arg, result;
+
+	switch (argc) {
+
+	case 0:
+	case 1:
+		break;
+
+	case 2:
+		if (strcmp (argv[1], "info") == 0) {
+			printf ("\nHymod FPGA Info...\n");
+			printf ("\t\t\t\tAddress\t\tSize\n");
+			printf ("\tMain Configuration:\t0x%08x\t%d\n",
+				FPGA_MAIN_CFG_BASE, FPGA_MAIN_CFG_SIZE);
+			printf ("\tMain Register:\t\t0x%08x\t%d\n",
+				FPGA_MAIN_REG_BASE, FPGA_MAIN_REG_SIZE);
+			printf ("\tMain Port:\t\t0x%08x\t%d\n",
+				FPGA_MAIN_PORT_BASE, FPGA_MAIN_PORT_SIZE);
+			printf ("\tMezz Configuration:\t0x%08x\t%d\n",
+				FPGA_MEZZ_CFG_BASE, FPGA_MEZZ_CFG_SIZE);
+			return 0;
+		}
+		break;
+
+	case 3:
+		if (strcmp (argv[1], "store") == 0) {
+			addr = (uchar *) simple_strtoul (argv[2], NULL, 16);
+
+			save_addr = addr;
+#if 0
+			/* fpga readback unimplemented */
+			while (more readback data)
+				*addr++ = *fpga;
+			result = error ? STORE_FAIL_XXX : STORE_SUCCESS;
+#else
+			result = STORE_SUCCESS;
+#endif
+
+			if (result == STORE_SUCCESS) {
+				printf ("SUCCEEDED (%d bytes)\n",
+					addr - save_addr);
+				return 0;
+			} else
+				printf ("FAILED (%d bytes)\n",
+					addr - save_addr);
+			return 1;
+		}
+		break;
+
+	case 4:
+		if (strcmp (argv[1], "tftp") == 0) {
+			copy_filename (BootFile, argv[2], sizeof (BootFile));
+			load_addr = simple_strtoul (argv[3], NULL, 16);
+			NetBootFileXferSize = 0;
+
+			if (NetLoop (TFTP) <= 0) {
+				printf ("tftp transfer failed - aborting "
+					"fgpa load\n");
+				return 1;
+			}
+
+			if (NetBootFileXferSize == 0) {
+				printf ("can't determine file size - "
+					"aborting fpga load\n");
+				return 1;
+			}
+
+			printf ("File transfer succeeded - "
+				"beginning fpga load...");
+
+			result = fpga_load (0, (uchar *) load_addr,
+				NetBootFileXferSize);
+
+			if (result == LOAD_SUCCESS) {
+				printf ("SUCCEEDED\n");
+				return 0;
+			} else if (result == LOAD_FAIL_NOCONF)
+				printf ("FAILED (no CONF)\n");
+			else if (result == LOAD_FAIL_NOINIT)
+				printf ("FAILED (no INIT)\n");
+			else
+				printf ("FAILED (no DONE)\n");
+			return 1;
+
+		}
+		/* fall through ... */
+
+	case 5:
+		if (strcmp (argv[1], "load") == 0) {
+			if (argc == 5) {
+				if (strcmp (argv[2], "main") == 0)
+					mezz = 0;
+				else if (strcmp (argv[2], "mezz") == 0)
+					mezz = 1;
+				else {
+					printf ("FPGA type must be either "
+						"`main' or `mezz'\n");
+					return 1;
+				}
+				arg = 3;
+			} else {
+				mezz = 0;
+				arg = 2;
+			}
+
+			addr = (uchar *) simple_strtoul (argv[arg++], NULL, 16);
+			size = (ulong) simple_strtoul (argv[arg], NULL, 16);
+
+			result = fpga_load (mezz, addr, size);
+
+			if (result == LOAD_SUCCESS) {
+				printf ("SUCCEEDED\n");
+				return 0;
+			} else if (result == LOAD_FAIL_NOCONF)
+				printf ("FAILED (no CONF)\n");
+			else if (result == LOAD_FAIL_NOINIT)
+				printf ("FAILED (no INIT)\n");
+			else
+				printf ("FAILED (no DONE)\n");
+			return 1;
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+U_BOOT_CMD(
+	fpga,	6,	1,	do_fpga,
+	"fpga    - FPGA sub-system\n",
+	"load [type] addr size\n"
+	"  - write the configuration data at memory address `addr',\n"
+	"    size `size' bytes, into the FPGA of type `type' (either\n"
+	"    `main' or `mezz', default `main'). e.g.\n"
+	"        `fpga load 100000 7d8f'\n"
+	"    loads the main FPGA with config data at address 100000\n"
+	"    HEX, size 7d8f HEX (32143 DEC) bytes\n"
+	"fpga tftp file addr\n"
+	"  - transfers `file' from the tftp server into memory at\n"
+	"    address `addr', then writes the entire file contents\n"
+	"    into the main FPGA\n"
+	"fpga store addr\n"
+	"  - read configuration data from the main FPGA (the mezz\n"
+	"    FPGA is write-only), into address `addr'. There must be\n"
+	"    enough memory available at `addr' to hold all the config\n"
+	"    data - the size of which is determined by VC:???\n"
+	"fpga info\n"
+	"  - print information about the Hymod FPGA, namely the\n"
+	"    memory addresses at which the four FPGA local bus\n"
+	"    address spaces appear in the physical address space\n"
+);
+/* ------------------------------------------------------------------------- */
+int
+do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	uchar data[HYMOD_EEPROM_SIZE];
+	uint addr = CFG_I2C_EEPROM_ADDR;
+
+	switch (argc) {
+
+	case 1:
+		addr |= HYMOD_EEOFF_MAIN;
+		break;
+
+	case 2:
+		if (strcmp (argv[1], "main") == 0) {
+			addr |= HYMOD_EEOFF_MAIN;
+			break;
+		}
+		if (strcmp (argv[1], "mezz") == 0) {
+			addr |= HYMOD_EEOFF_MEZZ;
+			break;
+		}
+		/* fall through ... */
+
+	default:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	memset (data, 0, HYMOD_EEPROM_SIZE);
+
+	eeprom_write (addr, 0, data, HYMOD_EEPROM_SIZE);
+
+	return 0;
+}
+U_BOOT_CMD(
+	eeclear,	1,	0,	do_eecl,
+	"eeclear - Clear the eeprom on a Hymod board \n",
+	"[type]\n"
+	"  - write zeroes into the EEPROM on the board of type `type'\n"
+	"    (`type' is either `main' or `mezz' - default `main')\n"
+	"    Note: the EEPROM write enable jumper must be installed\n"
+);
+
+/* ------------------------------------------------------------------------- */
+
+int
+do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+#if 0
+	int rc;
+#endif
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+	extern void eth_loopback_test (void);
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+	printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
+
+#if 0
+	/* Load FPGA with test program */
+
+	printf ("Loading test FPGA program ...");
+
+	rc = fpga_load (0, test_bitfile, sizeof (test_bitfile));
+
+	switch (rc) {
+
+	case LOAD_SUCCESS:
+		printf (" SUCCEEDED\n");
+		break;
+
+	case LOAD_FAIL_NOCONF:
+		printf (" FAILED (no configuration space defined)\n");
+		return 1;
+
+	case LOAD_FAIL_NOINIT:
+		printf (" FAILED (timeout - no INIT signal seen)\n");
+		return 1;
+
+	case LOAD_FAIL_NODONE:
+		printf (" FAILED (timeout - no DONE signal seen)\n");
+		return 1;
+
+	default:
+		printf (" FAILED (unknown return code from fpga_load\n");
+		return 1;
+	}
+
+	/* run Local Bus <=> Xilinx tests */
+
+	/* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
+
+	/* run SDRAM test */
+#endif
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+	/* run Ethernet test */
+	eth_loopback_test ();
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+	return 0;
+}
+
+#endif	/* CFG_CMD_BSP */
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/hymod/config.mk b/board/hymod/config.mk
new file mode 100755
index 0000000..0a9985f
--- /dev/null
+++ b/board/hymod/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# HYMOD boards
+#
+
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -I$(TOPDIR)
+
+OBJCFLAGS = --remove-section=.ppcenv
diff --git a/board/hymod/eeprom.c b/board/hymod/eeprom.c
new file mode 100755
index 0000000..c9b9b18
--- /dev/null
+++ b/board/hymod/eeprom.c
@@ -0,0 +1,694 @@
+/*
+ * (C) Copyright 2001
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+
+/* imports from fetch.c */
+extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
+
+/* imports from input.c */
+extern int hymod_get_serno (const char *);
+
+/* this is relative to the root of the server's tftp directory */
+static char *def_bddb_cfgdir = "/hymod/bddb";
+
+static int
+hymod_eeprom_load (int which, hymod_eeprom_t *ep)
+{
+	unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \
+		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
+	unsigned offset = 0;
+	uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp;
+	hymod_eehdr_t hdr;
+	ulong len, crc;
+
+	memset (ep, 0, sizeof *ep);
+
+	eeprom_read (dev_addr, offset, (uchar *)&hdr, sizeof (hdr));
+	offset += sizeof (hdr);
+
+	if (hdr.id != HYMOD_EEPROM_ID || hdr.ver > HYMOD_EEPROM_VER ||
+	  (len = hdr.len) > HYMOD_EEPROM_MAXLEN)
+	    return (0);
+
+	eeprom_read (dev_addr, offset, data, len);
+	offset += len;
+
+	eeprom_read (dev_addr, offset, (uchar *)&crc, sizeof (ulong));
+	offset += sizeof (ulong);
+
+	if (crc32 (crc32 (0, (uchar *)&hdr, sizeof hdr), data, len) != crc)
+		return (0);
+
+	ep->ver = hdr.ver;
+	dp = data; edp = dp + len;
+
+	for (;;) {
+		ulong rtyp;
+		uchar rlen, *rdat;
+
+		rtyp = *dp++;
+		if ((rtyp & 0x80) == 0)
+			rlen = *dp++;
+		else {
+			uchar islarge = rtyp & 0x40;
+
+			rtyp = ((rtyp & 0x3f) << 8) | *dp++;
+			if (islarge) {
+				rtyp = (rtyp << 8) | *dp++;
+				rtyp = (rtyp << 8) | *dp++;
+			}
+
+			rlen = *dp++;
+			rlen = (rlen << 8) | *dp++;
+			if (islarge) {
+				rlen = (rlen << 8) | *dp++;
+				rlen = (rlen << 8) | *dp++;
+			}
+		}
+
+		if (rtyp == 0)
+			break;
+
+		rdat = dp;
+		dp += rlen;
+
+		if (dp > edp)	/* error? */
+			break;
+
+		switch (rtyp) {
+
+		case HYMOD_EEREC_SERNO:		/* serial number */
+			if (rlen == sizeof (ulong))
+				ep->serno = \
+					((ulong)rdat[0] << 24) | \
+					((ulong)rdat[1] << 16) | \
+					((ulong)rdat[2] << 8) | \
+					(ulong)rdat[3];
+			break;
+
+		case HYMOD_EEREC_DATE:		/* date */
+			if (rlen == sizeof (hymod_date_t)) {
+				ep->date.year = ((ushort)rdat[0] << 8) | \
+					(ushort)rdat[1];
+				ep->date.month = rdat[2];
+				ep->date.day = rdat[3];
+			}
+			break;
+
+		case HYMOD_EEREC_BATCH:		/* batch */
+			if (rlen <= HYMOD_MAX_BATCH)
+				memcpy (ep->batch, rdat, ep->batchlen = rlen);
+			break;
+
+		case HYMOD_EEREC_TYPE:		/* board type */
+			if (rlen == 1)
+				ep->bdtype = *rdat;
+			break;
+
+		case HYMOD_EEREC_REV:		/* board revision */
+			if (rlen == 1)
+				ep->bdrev = *rdat;
+			break;
+
+		case HYMOD_EEREC_SDRAM:		/* sdram size(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_SDRAM) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->sdramsz[i] = rdat[i];
+				ep->nsdram = rlen;
+			}
+			break;
+
+		case HYMOD_EEREC_FLASH:		/* flash size(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_FLASH) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->flashsz[i] = rdat[i];
+				ep->nflash = rlen;
+			}
+			break;
+
+		case HYMOD_EEREC_ZBT:		/* zbt ram size(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_ZBT) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->zbtsz[i] = rdat[i];
+				ep->nzbt = rlen;
+			}
+			break;
+
+		case HYMOD_EEREC_XLXTYP:	/* xilinx fpga type(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->xlx[i].type = rdat[i];
+				ep->nxlx = rlen;
+			}
+			break;
+
+		case HYMOD_EEREC_XLXSPD:	/* xilinx fpga speed(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->xlx[i].speed = rdat[i];
+			}
+			break;
+
+		case HYMOD_EEREC_XLXTMP:	/* xilinx fpga temperature(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->xlx[i].temp = rdat[i];
+			}
+			break;
+
+		case HYMOD_EEREC_XLXGRD:	/* xilinx fpga grade(s) */
+			if (rlen > 0 && rlen <= HYMOD_MAX_XLX) {
+				int i;
+
+				for (i = 0; i < rlen; i++)
+					ep->xlx[i].grade = rdat[i];
+			}
+			break;
+
+		case HYMOD_EEREC_CPUTYP:	/* CPU type */
+			if (rlen == 1)
+				ep->mpc.type = *rdat;
+			break;
+
+		case HYMOD_EEREC_CPUSPD:	/* CPU speed */
+			if (rlen == 1)
+				ep->mpc.cpuspd = *rdat;
+			break;
+
+		case HYMOD_EEREC_CPMSPD:	/* CPM speed */
+			if (rlen == 1)
+				ep->mpc.cpmspd = *rdat;
+			break;
+
+		case HYMOD_EEREC_BUSSPD:	/* bus speed */
+			if (rlen == 1)
+				ep->mpc.busspd = *rdat;
+			break;
+
+		case HYMOD_EEREC_HSTYPE:	/* hs-serial chip type */
+			if (rlen == 1)
+				ep->hss.type = *rdat;
+			break;
+
+		case HYMOD_EEREC_HSCHIN:	/* num hs-serial input chans */
+			if (rlen == 1)
+				ep->hss.nchin = *rdat;
+			break;
+
+		case HYMOD_EEREC_HSCHOUT:	/* num hs-serial output chans */
+			if (rlen == 1)
+				ep->hss.nchout = *rdat;
+			break;
+
+		default:	/* ignore */
+			break;
+		}
+	}
+
+	return (1);
+}
+
+/* maps an ascii "name=value" into a binary eeprom data record */
+typedef
+	struct _eerec_map {
+		char *name;
+		uint type;
+		uchar *(*handler) \
+			(struct _eerec_map *, uchar *, uchar *, uchar *);
+		uint length;
+		uint maxlen;
+	}
+eerec_map_t;
+
+static uchar *
+uint_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
+{
+	char *eval;
+	ulong lval;
+
+	lval = simple_strtol ((char *)val, &eval, 10);
+
+	if ((uchar *)eval == val || *eval != '\0') {
+		printf ("%s rec (%s) is not a valid uint\n", rp->name, val);
+		return (NULL);
+	}
+
+	if (dp + 2 + rp->length > edp) {
+		printf ("can't fit %s rec into eeprom\n", rp->name);
+		return (NULL);
+	}
+
+	*dp++ = rp->type;
+	*dp++ = rp->length;
+
+	switch (rp->length) {
+
+	case 1:
+		if (lval >= 256) {
+			printf ("%s rec value (%lu) out of range (0-255)\n",
+				rp->name, lval);
+			return (NULL);
+		}
+		*dp++ = lval;
+		break;
+
+	case 2:
+		if (lval >= 65536) {
+			printf ("%s rec value (%lu) out of range (0-65535)\n",
+				rp->name, lval);
+			return (NULL);
+		}
+		*dp++ = lval >> 8;
+		*dp++ = lval;
+		break;
+
+	case 4:
+		*dp++ = lval >> 24;
+		*dp++ = lval >> 16;
+		*dp++ = lval >> 8;
+		*dp++ = lval;
+		break;
+
+	default:
+		printf ("huh? rp->length not 1, 2 or 4! (%d)\n", rp->length);
+		return (NULL);
+	}
+
+	return (dp);
+}
+
+static uchar *
+date_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
+{
+	hymod_date_t date;
+	char *p = (char *)val;
+	char *ep;
+	ulong lval;
+
+	lval = simple_strtol (p, &ep, 10);
+	if (ep == p || *ep++ != '-') {
+bad_date:
+		printf ("%s rec (%s) is not a valid date\n", rp->name, val);
+		return (NULL);
+	}
+	if (lval >= 65536)
+		goto bad_date;
+	date.year = lval;
+
+	lval = simple_strtol (p = ep, &ep, 10);
+	if (ep == p || *ep++ != '-' || lval == 0 || lval > 12)
+		goto bad_date;
+	date.month = lval;
+
+	lval = simple_strtol (p = ep, &ep, 10);
+	if (ep == p || *ep != '\0' || lval == 0 || lval > 31)
+		goto bad_date;
+	date.day = lval;
+
+	if (dp + 2 + rp->length > edp) {
+		printf ("can't fit %s rec into eeprom\n", rp->name);
+		return (NULL);
+	}
+
+	*dp++ = rp->type;
+	*dp++ = rp->length;
+	*dp++ = date.year >> 8;
+	*dp++ = date.year;
+	*dp++ = date.month;
+	*dp++ = date.day;
+
+	return (dp);
+}
+
+static uchar *
+string_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
+{
+	uint len;
+
+	if ((len = strlen ((char *)val)) > rp->maxlen) {
+		printf ("%s rec (%s) string is too long (%d>%d)\n",
+			rp->name, val, len, rp->maxlen);
+		return (NULL);
+	}
+
+	if (dp + 2 + len > edp) {
+		printf ("can't fit %s rec into eeprom\n", rp->name);
+		return (NULL);
+	}
+
+	*dp++ = rp->type;
+	*dp++ = len;
+	memcpy (dp, val, len);
+	dp += len;
+
+	return (dp);
+}
+
+static uchar *
+bytes_handler (eerec_map_t *rp, uchar *val, uchar *dp, uchar *edp)
+{
+	uchar bytes[HYMOD_MAX_BYTES], nbytes, *p;
+	char *ep;
+
+	for (nbytes = 0, p = val; *p != '\0'; p = (uchar *)ep) {
+		ulong lval;
+
+		lval = simple_strtol ((char *)p, &ep, 10);
+		if ((uchar *)ep == p || (*ep != '\0' && *ep != ',') || \
+		    lval >= 256) {
+			printf ("%s rec (%s) byte array has invalid uint\n",
+				rp->name, val);
+			return (NULL);
+		}
+		if (nbytes >= HYMOD_MAX_BYTES) {
+			printf ("%s rec (%s) byte array too long\n",
+				rp->name, val);
+			return (NULL);
+		}
+		bytes[nbytes++] = lval;
+
+		if (*ep != '\0')
+			ep++;
+	}
+
+	if (dp + 2 + nbytes > edp) {
+		printf ("can't fit %s rec into eeprom\n", rp->name);
+		return (NULL);
+	}
+
+	*dp++ = rp->type;
+	*dp++ = nbytes;
+	memcpy (dp, bytes, nbytes);
+	dp += nbytes;
+
+	return (dp);
+}
+
+static eerec_map_t eerec_map[] = {
+	/* name      type                 handler         len max             */
+	{ "serno",   HYMOD_EEREC_SERNO,   uint_handler,   4,  0               },
+	{ "date",    HYMOD_EEREC_DATE,    date_handler,   4,  0               },
+	{ "batch",   HYMOD_EEREC_BATCH,   string_handler, 0,  HYMOD_MAX_BATCH },
+	{ "type",    HYMOD_EEREC_TYPE,    uint_handler,   1,  0               },
+	{ "rev",     HYMOD_EEREC_REV,     uint_handler,   1,  0               },
+	{ "sdram",   HYMOD_EEREC_SDRAM,   bytes_handler,  0,  HYMOD_MAX_SDRAM },
+	{ "flash",   HYMOD_EEREC_FLASH,   bytes_handler,  0,  HYMOD_MAX_FLASH },
+	{ "zbt",     HYMOD_EEREC_ZBT,     bytes_handler,  0,  HYMOD_MAX_ZBT   },
+	{ "xlxtyp",  HYMOD_EEREC_XLXTYP,  bytes_handler,  0,  HYMOD_MAX_XLX   },
+	{ "xlxspd",  HYMOD_EEREC_XLXSPD,  bytes_handler,  0,  HYMOD_MAX_XLX   },
+	{ "xlxtmp",  HYMOD_EEREC_XLXTMP,  bytes_handler,  0,  HYMOD_MAX_XLX   },
+	{ "xlxgrd",  HYMOD_EEREC_XLXGRD,  bytes_handler,  0,  HYMOD_MAX_XLX   },
+	{ "cputyp",  HYMOD_EEREC_CPUTYP,  uint_handler,   1,  0               },
+	{ "cpuspd",  HYMOD_EEREC_CPUSPD,  uint_handler,   1,  0               },
+	{ "cpmspd",  HYMOD_EEREC_CPMSPD,  uint_handler,   1,  0               },
+	{ "busspd",  HYMOD_EEREC_BUSSPD,  uint_handler,   1,  0               },
+	{ "hstype",  HYMOD_EEREC_HSTYPE,  uint_handler,   1,  0               },
+	{ "hschin",  HYMOD_EEREC_HSCHIN,  uint_handler,   1,  0               },
+	{ "hschout", HYMOD_EEREC_HSCHOUT, uint_handler,   1,  0               },
+};
+
+static int neerecs = sizeof eerec_map / sizeof eerec_map[0];
+
+static uchar data[HYMOD_EEPROM_SIZE], *sdp, *dp, *edp;
+
+static int
+eerec_callback (uchar *name, uchar *val)
+{
+	eerec_map_t *rp;
+
+	for (rp = eerec_map; rp < &eerec_map[neerecs]; rp++)
+		if (strcmp ((char *)name, rp->name) == 0)
+			break;
+
+	if (rp >= &eerec_map[neerecs])
+		return (0);
+
+	if ((dp = (*rp->handler) (rp, val, dp, edp)) == NULL)
+		return (0);
+
+	return (1);
+}
+
+static int
+hymod_eeprom_fetch(int which, char *filename, ulong addr)
+{
+	unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \
+		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
+	hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0];
+	ulong crc;
+
+	memset (hp, 0, sizeof *hp);
+	hp->id = HYMOD_EEPROM_ID;
+	hp->ver = HYMOD_EEPROM_VER;
+
+	dp = sdp = (uchar *)(hp + 1);
+	edp = dp + HYMOD_EEPROM_MAXLEN;
+
+	if (fetch_and_parse (filename, addr, eerec_callback) == 0)
+		return (0);
+
+	hp->len = dp - sdp;
+
+	crc = crc32 (0, data, dp - data);
+	memcpy (dp, &crc, sizeof (ulong));
+	dp += sizeof (ulong);
+
+	eeprom_write (dev_addr, 0, data, dp - data);
+
+	return (1);
+}
+
+static char *type_vals[] = {
+	"NONE", "IO", "CLP", "DSP", "INPUT", "ALT-INPUT", "DISPLAY"
+};
+
+static char *xlxtyp_vals[] = {
+	"NONE", "XCV300E", "XCV400E", "XCV600E"
+};
+
+static char *xlxspd_vals[] = {
+	"NONE", "6", "7", "8"
+};
+
+static char *xlxtmp_vals[] = {
+	"NONE", "COM", "IND"
+};
+
+static char *xlxgrd_vals[] = {
+	"NONE", "NORMAL", "ENGSAMP"
+};
+
+static char *cputyp_vals[] = {
+	"NONE", "MPC8260"
+};
+
+static char *clk_vals[] = {
+	"NONE", "33", "66", "100", "133", "166", "200"
+};
+
+static char *hstype_vals[] = {
+	"NONE", "AMCC-S2064A"
+};
+
+static void
+print_mem (char *l, char *s, uchar n, uchar a[])
+{
+	if (n > 0) {
+		if (n == 1)
+			printf ("%s%dMB %s", s, 1 << (a[0] - 20), l);
+		else {
+			ulong t = 0;
+			int i;
+
+			for (i = 0; i < n; i++)
+				t += 1 << (a[i] - 20);
+
+			printf ("%s%luMB %s (%d banks:", s, t, l, n);
+
+			for (i = 0; i < n; i++)
+				printf ("%dMB%s",
+					1 << (a[i] - 20),
+					(i == n - 1) ? ")" : ",");
+		}
+	}
+	else
+		printf ("%sNO %s", s, l);
+}
+
+void
+hymod_eeprom_print (hymod_eeprom_t *ep)
+{
+	int i;
+
+	printf ("         Hymod %s board, rev %03d\n",
+		type_vals[ep->bdtype], ep->bdrev);
+
+	printf ("         serial #: %010lu, date %04d-%02d-%02d",
+		ep->serno, ep->date.year, ep->date.month, ep->date.day);
+	if (ep->batchlen > 0)
+		printf (", batch \"%.*s\"", ep->batchlen, ep->batch);
+	puts ("\n");
+
+	switch (ep->bdtype) {
+
+	case HYMOD_BDTYPE_IO:
+	case HYMOD_BDTYPE_CLP:
+	case HYMOD_BDTYPE_DSP:
+		printf ("         Motorola %s CPU, speeds: %s/%s/%s",
+		    cputyp_vals[ep->mpc.type], clk_vals[ep->mpc.cpuspd],
+		    clk_vals[ep->mpc.cpmspd], clk_vals[ep->mpc.busspd]);
+
+		print_mem ("SDRAM", ", ", ep->nsdram, ep->sdramsz);
+
+		print_mem ("FLASH", ", ", ep->nflash, ep->flashsz);
+
+		puts ("\n");
+
+		print_mem ("ZBT", "         ", ep->nzbt, ep->zbtsz);
+
+		if (ep->nxlx > 0) {
+			hymod_xlx_t *xp;
+
+			if (ep->nxlx == 1) {
+				xp = &ep->xlx[0];
+				printf (", Xilinx %s FPGA (%s/%s/%s)",
+					xlxtyp_vals[xp->type],
+					xlxspd_vals[xp->speed],
+					xlxtmp_vals[xp->temp],
+					xlxgrd_vals[xp->grade]);
+			}
+			else {
+				printf (", %d Xilinx FPGAs (", ep->nxlx);
+				for (i = 0; i < ep->nxlx; i++) {
+					xp = &ep->xlx[i];
+					printf ("%s[%s/%s/%s]%s",
+					    xlxtyp_vals[xp->type],
+					    xlxspd_vals[xp->speed],
+					    xlxtmp_vals[xp->temp],
+					    xlxgrd_vals[xp->grade],
+					    (i == ep->nxlx - 1) ? ")" : ", ");
+				}
+			}
+		}
+		else
+			puts(", NO FPGAs");
+
+		puts ("\n");
+
+		if (ep->hss.type > 0)
+			printf ("         High Speed Serial: "
+				"%s, %d input%s, %d output%s\n",
+				hstype_vals[ep->hss.type],
+				ep->hss.nchin,
+				(ep->hss.nchin == 1 ? "" : "s"),
+				ep->hss.nchout,
+				(ep->hss.nchout == 1 ? "" : "s"));
+		break;
+
+	case HYMOD_BDTYPE_INPUT:
+	case HYMOD_BDTYPE_ALTINPUT:
+	case HYMOD_BDTYPE_DISPLAY:
+		break;
+
+	default:
+		/* crap! */
+		printf ("         UNKNOWN BOARD TYPE: %d\n", ep->bdtype);
+		break;
+	}
+}
+
+int
+hymod_eeprom_read (int which, hymod_eeprom_t *ep)
+{
+	char *label = which ? "mezzanine" : "main";
+	unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \
+		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
+	char filename[50], prompt[50], *dir;
+	int serno, count = 0, rc;
+
+	rc = eeprom_probe (dev_addr, 0);
+
+	if (rc > 0) {
+		printf ("*** probe for eeprom failed with code %d\n", rc);
+		return (0);
+	}
+
+	if (rc < 0)
+		return (rc);
+
+	sprintf (prompt, "Enter %s board serial number: ", label);
+
+	if ((dir = getenv ("bddb_cfgdir")) == NULL)
+		dir = def_bddb_cfgdir;
+
+	for (;;) {
+		int rc;
+
+		if (hymod_eeprom_load (which, ep))
+			return (1);
+
+		printf ("*** %s board EEPROM contents are %sinvalid\n",
+			label, count == 0 ? "" : "STILL ");
+
+		puts ("*** will fetch from server (Ctrl-C to abort)\n");
+
+		serno = hymod_get_serno (prompt);
+
+		if (serno < 0) {
+			if (serno == -1)
+				puts ("\n*** interrupted!");
+			else
+				puts ("\n*** timeout!");
+			puts (" - ignoring eeprom contents\n");
+			return (0);
+		}
+
+		sprintf (filename, "%s/%010d.cfg", dir, serno);
+
+		printf ("*** fetching %s board EEPROM contents from server\n",
+			label);
+
+		rc = hymod_eeprom_fetch (which, filename, CFG_LOAD_ADDR);
+
+		if (rc == 0) {
+			puts ("*** fetch failed - ignoring eeprom contents\n");
+			return (0);
+		}
+
+		count++;
+	}
+}
diff --git a/board/hymod/env.c b/board/hymod/env.c
new file mode 100755
index 0000000..f9e1421
--- /dev/null
+++ b/board/hymod/env.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2003
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* imports from fetch.c */
+extern int fetch_and_parse (char *, ulong, int (*)(uchar *, uchar *));
+
+/* this is relative to the root of the server's tftp directory */
+static char *def_global_env_path = "/hymod/global_env";
+
+static int
+env_callback (uchar *name, uchar *value)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
+	char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver;
+	int override = 1, append = 0, remove = 0, nnl, ovl, nvl;
+
+	nn = (char *)name;
+
+	if (*nn == '-') {
+		override = 0;
+		nn++;
+	}
+
+	while (*nn == ' ' || *nn == '\t')
+		nn++;
+
+	if ((nnl = strlen (nn)) == 0) {
+		printf ("Empty name in global env file\n");
+		return (0);
+	}
+
+	if ((c = nn[nnl - 1]) == '+' || c == '-') {
+		if (c == '+')
+			append = 1;
+		else
+			remove = 1;
+		nn[--nnl] = '\0';
+	}
+
+	while (nnl > 0 && ((c = nn[nnl - 1]) == ' ' || c == '\t'))
+		nn[--nnl] = '\0';
+	if (nnl == 0) {
+		printf ("Empty name in global env file\n");
+		return (0);
+	}
+
+	p = (char *)value;
+	q = nv;
+
+	while ((c = *p) == ' ' || c == '\t')
+		p++;
+
+	nvl = strlen (p);
+	while (nvl > 0 && ((c = p[nvl - 1]) == ' ' || c == '\t'))
+		p[--nvl] = '\0';
+
+	while ((*q = *p++) != '\0') {
+		if (*q == '%') {
+			switch (*p++) {
+
+			case '\0':	/* whoops - back up */
+				p--;
+				break;
+
+			case '%':	/* a single percent character */
+				q++;
+				break;
+
+			case 's':	/* main board serial number as string */
+				q += sprintf (q, "%010lu",
+					cp->main.eeprom.serno);
+				break;
+
+			case 'S':	/* main board serial number as number */
+				q += sprintf (q, "%lu", cp->main.eeprom.serno);
+				break;
+
+			default:	/* ignore any others */
+				break;
+			}
+		}
+		else
+			q++;
+	}
+
+	if ((nvl = q - nv) == 0) {
+		setenv (nn, NULL);
+		return (1);
+	}
+
+	if ((curver = getenv ("global_env_version")) == NULL)
+		curver = "unknown";
+
+	if ((newver = getenv ("new_genv_version")) == NULL || \
+	    strcmp (curver, newver) == 0) {
+		if (strcmp (nn, "version") == 0)
+			setenv ("new_genv_version", nv);
+		return (1);
+	}
+
+	if ((p = getenv (nn)) != NULL) {
+
+		strcpy (ov, p);
+		ovl = strlen (ov);
+
+		if (append) {
+
+			if (strstr (ov, nv) == NULL) {
+
+				printf ("Appending '%s' to env var '%s'\n",
+					nv, nn);
+
+				while (nvl >= 0) {
+					nv[ovl + 1 + nvl] = nv[nvl];
+					nvl--;
+				}
+
+				nv[ovl] = ' ';
+
+				while (--ovl >= 0)
+					nv[ovl] = ov[ovl];
+
+				setenv (nn, nv);
+			}
+
+			return (1);
+		}
+
+		if (remove) {
+
+			if (strstr (ov, nv) != NULL) {
+
+				printf ("Removing '%s' from env var '%s'\n",
+					nv, nn);
+
+				while ((p = strstr (ov, nv)) != NULL) {
+					q = p + nvl;
+					if (*q == ' ')
+						q++;
+					strcpy(p, q);
+				}
+
+				setenv (nn, ov);
+			}
+
+			return (1);
+		}
+
+		if (!override || strcmp (ov, nv) == 0)
+			return (1);
+
+		printf ("Re-setting env cmd '%s' from '%s' to '%s'\n",
+			nn, ov, nv);
+	}
+	else
+		printf ("Setting env cmd '%s' to '%s'\n", nn, nv);
+
+	setenv (nn, nv);
+	return (1);
+}
+
+void
+hymod_check_env (void)
+{
+	char *p, *path, *curver, *newver;
+	int firsttime = 0, needsave = 0;
+
+	if (getenv ("global_env_loaded") == NULL) {
+		puts ("*** global environment has never been loaded\n");
+		puts ("*** fetching from server");
+		firsttime = 1;
+	}
+	else if ((p = getenv ("always_check_env")) != NULL &&
+	    strcmp (p, "yes") == 0)
+		puts ("*** checking for updated global environment");
+	else
+		return;
+
+	puts (" (Control-C to Abort)\n");
+
+	if ((path = getenv ("global_env_path")) == NULL || *path == '\0')
+		path = def_global_env_path;
+
+	if (fetch_and_parse (path, CFG_LOAD_ADDR, env_callback) == 0) {
+		puts ("*** Fetch of global environment failed!\n");
+		return;
+	}
+
+	if ((newver = getenv ("new_genv_version")) == NULL) {
+		puts ("*** Version number not set - contents ignored!\n");
+		return;
+	}
+
+	if ((curver = getenv ("global_env_version")) == NULL || \
+	    strcmp (curver, newver) != 0) {
+		setenv ("global_env_version", newver);
+		needsave = 1;
+	}
+	else
+		printf ("*** Global environment up-to-date (ver %s)\n", curver);
+
+	setenv ("new_genv_version", NULL);
+
+	if (firsttime) {
+		setenv ("global_env_loaded", "yes");
+		needsave = 1;
+	}
+
+	if (needsave)
+		puts ("\n*** Remember to run the 'saveenv' "
+			"command to save the changes\n\n");
+}
diff --git a/board/hymod/fetch.c b/board/hymod/fetch.c
new file mode 100755
index 0000000..e121d55
--- /dev/null
+++ b/board/hymod/fetch.c
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2001
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+
+/* imports from input.c */
+extern int hymod_get_ethaddr (void);
+
+int
+fetch_and_parse (char *fn, ulong addr, int (*cback)(uchar *, uchar *))
+{
+	char *ethaddr;
+	uchar *fp, *efp;
+	int rc, count = 0;
+
+	while ((ethaddr = getenv ("ethaddr")) == NULL || *ethaddr == '\0') {
+
+		printf ("*** Ethernet address is%s not set\n",
+			count == 0 ? "" : " STILL");
+
+		if ((rc = hymod_get_ethaddr ()) < 0) {
+			if (rc == -1)
+				puts ("\n*** interrupted!");
+			else
+				puts ("\n*** timeout!");
+			printf (" - fetch of '%s' aborted\n", fn);
+			return (0);
+		}
+
+		count++;
+	}
+
+	copy_filename (BootFile, fn, sizeof (BootFile));
+	load_addr = addr;
+	NetBootFileXferSize = 0;
+
+	if (NetLoop (TFTP) == 0) {
+		printf ("tftp transfer of file '%s' failed\n", fn);
+		return (0);
+	}
+
+	if (NetBootFileXferSize == 0) {
+		printf ("can't determine size of file '%s'\n", fn);
+		return (0);
+	}
+
+	fp = (uchar *)load_addr;
+	efp = fp + NetBootFileXferSize;
+
+	do {
+		uchar *name, *value;
+
+		if (*fp == '#' || *fp == '\n') {
+			/* skip this line */
+			while (fp < efp && *fp++ != '\n')
+				;
+			continue;
+		}
+
+		name = fp;
+
+		while (fp < efp && *fp != '=' && *fp != '\n')
+			fp++;
+		if (fp >= efp)
+			break;
+		if (*fp == '\n') {
+			fp++;
+			continue;
+		}
+		*fp++ = '\0';
+
+		value = fp;
+
+		while (fp < efp && *fp != '\n')
+			fp++;
+		if (fp[-1] == '\r')
+			fp[-1] = '\0';
+		*fp++ = '\0';	/* ok if we go off the end here */
+
+		if ((*cback)(name, value) == 0)
+			return (0);
+
+	} while (fp < efp);
+
+	return (1);
+}
diff --git a/board/hymod/flash.c b/board/hymod/flash.c
new file mode 100755
index 0000000..ad0a229
--- /dev/null
+++ b/board/hymod/flash.c
@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <board/hymod/flash.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * probe for flash bank at address "base" and store info about it
+ * in the flash_info entry "fip". Fatal error if nothing there.
+ */
+static void
+bank_probe (flash_info_t *fip, volatile bank_addr_t base)
+{
+	volatile bank_addr_t addr;
+	bank_word_t word;
+	int i;
+
+	/* reset the flash */
+	*base = BANK_CMD_RST;
+
+	/* put flash into read id mode */
+	*base = BANK_CMD_RD_ID;
+
+	/* check the manufacturer id - must be intel */
+	word = *BANK_REG_MAN_CODE (base);
+	if (word != BANK_FILL_WORD (INTEL_MANUFACT&0xff))
+		panic ("\nbad manufacturer's code (0x%08lx) at addr 0x%08lx",
+			(unsigned long)word, (unsigned long)base);
+
+	/* check the device id */
+	word = *BANK_REG_DEV_CODE (base);
+	switch (word) {
+
+	case BANK_FILL_WORD (INTEL_ID_28F320J5&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J5;
+		fip->sector_count = 32;
+		break;
+
+	case BANK_FILL_WORD (INTEL_ID_28F640J5&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J5;
+		fip->sector_count = 64;
+		break;
+
+	case BANK_FILL_WORD (INTEL_ID_28F320J3A&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F320J3A;
+		fip->sector_count = 32;
+		break;
+
+	case BANK_FILL_WORD (INTEL_ID_28F640J3A&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F640J3A;
+		fip->sector_count = 64;
+		break;
+
+	case BANK_FILL_WORD (INTEL_ID_28F128J3A&0xff):
+		fip->flash_id = FLASH_MAN_INTEL | FLASH_28F128J3A;
+		fip->sector_count = 128;
+		break;
+
+	default:
+		panic ("\nbad device code (0x%08lx) at addr 0x%08lx",
+			(unsigned long)word, (unsigned long)base);
+	}
+
+	if (fip->sector_count >= CFG_MAX_FLASH_SECT)
+		panic ("\ntoo many sectors (%d) in flash at address 0x%08lx",
+			fip->sector_count, (unsigned long)base);
+
+	addr = base;
+	for (i = 0; i < fip->sector_count; i++) {
+		fip->start[i] = (unsigned long)addr;
+		fip->protect[i] = 0;
+		addr = BANK_ADDR_NEXT_BLK (addr);
+	}
+
+	fip->size = (bank_size_t)addr - (bank_size_t)base;
+
+	/* reset the flash */
+	*base = BANK_CMD_RST;
+}
+
+static void
+bank_reset (flash_info_t *info, int sect)
+{
+	volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
+
+#ifdef FLASH_DEBUG
+	printf ("writing reset cmd to addr 0x%08lx\n", (unsigned long)addr);
+#endif
+
+	*addr = BANK_CMD_RST;
+}
+
+static void
+bank_erase_init (flash_info_t *info, int sect)
+{
+	volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
+	int flag;
+
+#ifdef FLASH_DEBUG
+	printf ("erasing sector %d, addr = 0x%08lx\n",
+		sect, (unsigned long)addr);
+#endif
+
+	/* Disable intrs which might cause a timeout here */
+	flag = disable_interrupts ();
+
+#ifdef FLASH_DEBUG
+	printf ("writing erase cmd to addr 0x%08lx\n", (unsigned long)addr);
+#endif
+	*addr = BANK_CMD_ERASE1;
+	*addr = BANK_CMD_ERASE2;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+}
+
+static int
+bank_erase_poll (flash_info_t *info, int sect)
+{
+	volatile bank_addr_t addr = (bank_addr_t)info->start[sect];
+	bank_word_t stat = *addr;
+
+#ifdef FLASH_DEBUG
+	printf ("checking status at addr 0x%08lx [0x%08lx]\n",
+		(unsigned long)addr, (unsigned long)stat);
+#endif
+
+	if ((stat & BANK_STAT_RDY) == BANK_STAT_RDY) {
+		if ((stat & BANK_STAT_ERR) != 0) {
+			printf ("failed on sector %d [0x%08lx] at "
+				"address 0x%08lx\n", sect,
+				(unsigned long)stat, (unsigned long)addr);
+			*addr = BANK_CMD_CLR_STAT;
+			return (-1);
+		}
+		else
+			return (1);
+	}
+	else
+		return (0);
+}
+
+static int
+bank_write_word (volatile bank_addr_t addr, bank_word_t value)
+{
+	bank_word_t stat;
+	ulong start;
+	int flag, retval;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = BANK_CMD_PROG;
+
+	*addr = value;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	retval = 0;
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	do {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			retval = 1;
+			goto done;
+		}
+		stat = *addr;
+	} while ((stat & BANK_STAT_RDY) != BANK_STAT_RDY);
+
+	if ((stat & BANK_STAT_ERR) != 0) {
+		printf ("flash program failed [0x%08lx] at address 0x%08lx\n",
+			(unsigned long)stat, (unsigned long)addr);
+		*addr = BANK_CMD_CLR_STAT;
+		retval = 3;
+	}
+
+done:
+	/* reset to read mode */
+	*addr = BANK_CMD_RST;
+
+	return (retval);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long
+flash_init (void)
+{
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	bank_probe (&flash_info[0], (bank_addr_t)CFG_FLASH_BASE);
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE == CFG_FLASH_BASE
+	(void)flash_protect (FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#if defined(CFG_FLASH_ENV_ADDR)
+	(void)flash_protect (FLAG_PROTECT_SET,
+		      CFG_FLASH_ENV_ADDR,
+#if defined(CFG_FLASH_ENV_BUF)
+		      CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_BUF - 1,
+#else
+		      CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_SIZE - 1,
+#endif
+		      &flash_info[0]);
+#endif
+
+	return flash_info[0].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J5:	printf ("28F320J5 (32 Mbit, 2 x 16bit)\n");
+				break;
+	case FLASH_28F640J5:	printf ("28F640J5 (64 Mbit, 2 x 16bit)\n");
+				break;
+	case FLASH_28F320J3A:	printf ("28F320J3A (32 Mbit, 2 x 16bit)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640J3A (64 Mbit, 2 x 16bit)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F320J3A (128 Mbit, 2 x 16bit)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int prot, sect, haderr;
+	ulong start, now, last;
+	int rcode = 0;
+
+#ifdef FLASH_DEBUG
+	printf ("\nflash_erase: erase %d sectors (%d to %d incl.) from\n"
+		"  Bank # %d: ", s_last - s_first + 1, s_first, s_last,
+		(info - flash_info) + 1);
+	flash_print_info (info);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sector%s will not be erased\n",
+			prot, (prot > 1 ? "s" : ""));
+	}
+
+	start = get_timer (0);
+	last = 0;
+	haderr = 0;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			ulong estart;
+			int sectdone;
+
+			bank_erase_init (info, sect);
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			estart = get_timer (start);
+
+			do {
+				now = get_timer (start);
+
+				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout (sect %d)\n", sect);
+					haderr = 1;
+					rcode = 1;
+					break;
+				}
+
+#ifndef FLASH_DEBUG
+				/* show that we're waiting */
+				if ((now - last) > 1000) { /* every second */
+					putc ('.');
+					last = now;
+				}
+#endif
+
+				sectdone = bank_erase_poll (info, sect);
+
+				if (sectdone < 0) {
+					haderr = 1;
+					rcode = 1;
+					break;
+				}
+
+			} while (!sectdone);
+
+			if (haderr)
+				break;
+		}
+	}
+
+	if (haderr > 0)
+		printf (" failed\n");
+	else
+		printf (" done\n");
+
+	/* reset to read mode */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			bank_reset (info, sect);
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - Program failed
+ */
+static int
+write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	/* Check if Flash is (sufficiently) erased */
+	if ((*(ulong *)dest & data) != data)
+		return (2);
+
+	return (bank_write_word ((bank_addr_t)dest, (bank_word_t)data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - Program failed
+ */
+
+int
+write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/hymod/flash.h b/board/hymod/flash.h
new file mode 100755
index 0000000..ee047fe
--- /dev/null
+++ b/board/hymod/flash.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
+
+/* Commands */
+#define ISF_CMD_RST		0xFF		/* reset flash */
+#define ISF_CMD_RD_ID		0x90		/* read the id and lock bits */
+#define ISF_CMD_RD_QUERY	0x98		/* read device capabilities */
+#define ISF_CMD_RD_STAT		0x70		/* read the status register */
+#define ISF_CMD_CLR_STAT	0x50		/* clear the staus register */
+#define ISF_CMD_WR_BUF		0xE8		/* clear the staus register */
+#define ISF_CMD_PROG		0x40		/* program word command */
+#define ISF_CMD_ERASE1		0x20		/* 1st word for block erase */
+#define ISF_CMD_ERASE2		0xD0		/* 2nd word for block erase */
+#define ISF_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
+#define ISF_CMD_LOCK		0x60		/* 1st word for all lock cmds */
+#define ISF_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
+#define ISF_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
+#define ISF_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
+
+/* status register bits */
+#define ISF_STAT_DPS		0x02		/* Device Protect Status */
+#define ISF_STAT_VPPS		0x08		/* VPP Status */
+#define ISF_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
+#define ISF_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
+#define ISF_STAT_ESS		0x40		/* Erase Suspend Status */
+#define ISF_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
+
+#define ISF_STAT_ERR		(ISF_STAT_VPPS | ISF_STAT_DPS | \
+				    ISF_STAT_ECLBS | ISF_STAT_PSLBS)
+
+/* register addresses, valid only following an ISF_CMD_RD_ID command */
+#define ISF_REG_MAN_CODE	0x00		/* manufacturer code */
+#define ISF_REG_DEV_CODE	0x01		/* device code */
+#define ISF_REG_BLK_LCK		0x02		/* block lock configuration */
+#define ISF_REG_MST_LCK		0x03		/* master lock configuration */
+
+/********************** DEFINES for Hymod Flash ******************************/
+
+/*
+ * this code requires that the flash on any Hymod board appear as a bank
+ * of two (identical) 16bit Intel StrataFlash chips with 64Kword erase
+ * sectors (or blocks), running in x16 bit mode and connected side-by-side
+ * to make a 32-bit wide bus.
+ */
+
+typedef unsigned long bank_word_t;
+typedef bank_word_t bank_blk_t[64 * 1024];
+
+#define BANK_FILL_WORD(b)	(((bank_word_t)(b) << 16) | (bank_word_t)(b))
+
+#ifdef EXAMPLE
+
+/* theoretically the following examples should also work */
+
+/* one flash chip in x8 mode with 128Kword sectors and 8bit bus */
+typedef unsigned char bank_word_t;
+typedef bank_word_t bank_blk_t[128 * 1024];
+#define BANK_FILL_WORD(b)	((bank_word_t)(b))
+
+/* four flash chips in x16 mode with 32Kword sectors and 64bit bus */
+typedef unsigned long long bank_word_t;
+typedef bank_word_t bank_blk_t[32 * 1024];
+#define BANK_FILL_WORD(b)	( \
+				    ((bank_word_t)(b) << 48) \
+				    ((bank_word_t)(b) << 32) \
+				    ((bank_word_t)(b) << 16) \
+				    ((bank_word_t)(b) <<  0) \
+				)
+
+#endif /* EXAMPLE */
+
+/* the sizes of these two types should probably be the same */
+typedef bank_word_t *bank_addr_t;
+typedef unsigned long bank_size_t;
+
+/* align bank addresses and sizes to bank word boundaries */
+#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(sizeof (bank_word_t) - 1)))
+#define BANK_SIZE_WORD_ALIGN(s)	(((bank_size_t)(s) + sizeof (bank_word_t) - 1) \
+				    & ~(sizeof (bank_word_t) - 1))
+
+/* align bank addresses and sizes to bank block boundaries */
+#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
+				    & ~(sizeof (bank_blk_t) - 1)))
+#define BANK_SIZE_BLK_ALIGN(s)	(((bank_size_t)(s) + sizeof (bank_blk_t) - 1) \
+				    & ~(sizeof (bank_blk_t) - 1))
+
+/* add an offset to a bank address */
+#define BANK_ADDR_OFFSET(a, o)	((bank_addr_t)((bank_size_t)(a) + \
+				    (bank_size_t)(o)))
+
+/* adjust a bank address to start of next word, block or bank */
+#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
+				    sizeof (bank_word_t))
+#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
+				    sizeof (bank_blk_t))
+
+/* get bank address of register r given a bank base address a and block num b */
+#define BANK_ADDR_REG(a, b, r)	BANK_ADDR_OFFSET(BANK_ADDR_OFFSET((a), \
+				    (bank_size_t)(b) * sizeof (bank_blk_t)), \
+					(bank_size_t)(r) * sizeof (bank_word_t))
+
+/* make a bank word value for each StrataFlash value */
+
+/* Commands */
+#define BANK_CMD_RST		BANK_FILL_WORD(ISF_CMD_RST)
+#define BANK_CMD_RD_ID		BANK_FILL_WORD(ISF_CMD_RD_ID)
+#define BANK_CMD_RD_STAT	BANK_FILL_WORD(ISF_CMD_RD_STAT)
+#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(ISF_CMD_CLR_STAT)
+#define BANK_CMD_ERASE1		BANK_FILL_WORD(ISF_CMD_ERASE1)
+#define BANK_CMD_ERASE2		BANK_FILL_WORD(ISF_CMD_ERASE2)
+#define BANK_CMD_PROG		BANK_FILL_WORD(ISF_CMD_PROG)
+#define BANK_CMD_LOCK		BANK_FILL_WORD(ISF_CMD_LOCK)
+#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(ISF_CMD_SET_LOCK_BLK)
+#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(ISF_CMD_SET_LOCK_MSTR)
+#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(ISF_CMD_CLR_LOCK_BLK)
+
+/* status register bits */
+#define BANK_STAT_DPS		BANK_FILL_WORD(ISF_STAT_DPS)
+#define BANK_STAT_PSS		BANK_FILL_WORD(ISF_STAT_PSS)
+#define BANK_STAT_VPPS		BANK_FILL_WORD(ISF_STAT_VPPS)
+#define BANK_STAT_PSLBS		BANK_FILL_WORD(ISF_STAT_PSLBS)
+#define BANK_STAT_ECLBS		BANK_FILL_WORD(ISF_STAT_ECLBS)
+#define BANK_STAT_ESS		BANK_FILL_WORD(ISF_STAT_ESS)
+#define BANK_STAT_RDY		BANK_FILL_WORD(ISF_STAT_RDY)
+
+#define BANK_STAT_ERR		BANK_FILL_WORD(ISF_STAT_ERR)
+
+/* make a bank register address for each StrataFlash register address */
+
+#define BANK_REG_MAN_CODE(a)	BANK_ADDR_REG((a), 0, ISF_REG_MAN_CODE)
+#define BANK_REG_DEV_CODE(a)	BANK_ADDR_REG((a), 0, ISF_REG_DEV_CODE)
+#define BANK_REG_BLK_LCK(a, b)	BANK_ADDR_REG((a), (b), ISF_REG_BLK_LCK)
+#define BANK_REG_MST_LCK(a)	BANK_ADDR_REG((a), 0, ISF_REG_MST_LCK)
diff --git a/board/hymod/global_env b/board/hymod/global_env
new file mode 100755
index 0000000..f61d080
--- /dev/null
+++ b/board/hymod/global_env
@@ -0,0 +1,161 @@
+# DONT FORGET TO CHANGE THE "version" VAR BELOW IF YOU MAKE CHANGES TO THIS FILE
+
+# (C) Copyright 2001
+# Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+#
+# global_env
+#
+# file used by Hymod boards to initialise the u-boot non-volatile
+# environment when u-boot is first run (it determines this by the
+# absence of the environment variable "global_env_loaded")
+#
+# format of this file is:
+#
+#	1. blank lines and lines beginning with '#' are ignored
+#	2. all other lines must have the form <name>=<value>
+#	3. if a percent appears anywhere, it is replaced like so:
+#
+#		%s	serial number of the main board (10 digit zero filled)
+#		%S	serial number of the main board (plain number)
+#		%%	a percentage character
+#		... otherwise the %x is discarded
+#
+# if first character in <name> is a dash ('-'), then an existing env var
+# will not be overwritten (the dash is removed). i.e. it is only set if
+# it does not exist
+#
+# if last character in <name> is a plus ('+'), then <value> will be appended
+# to any existing env var (the plus is ignored). Duplicates of <value> are
+# removed.
+#
+# similarly, if the last character in <name> is a minus ('-'), then any
+# occurences of <value> in the current value of <name> will removed (the
+# minus is ignored).
+#
+# leading and trailing whitespace is removed in both <name> and <value>
+# (after processing any initial or final plus/minus in <name>).
+#
+
+# MISCELLANEOUS PARAMETERS
+
+# version must always come first
+version=4
+
+# set the ip address based on the main board serial number
+ipaddr=192.168.1.%S
+serverip=192.168.1.254
+
+# stop auto execute after tftp (not a very good name really)
+autostart=no
+
+# setting this to "yes" forces the global_env file to be loaded and processed
+# if the current version is different to the version in the file
+always_check_env=no
+
+# BOOTING COMMANDS AND PARAMETERS
+
+# command to run when "auto-booting"
+bootcmd=bootm 40080000
+
+# how long the "countdown" to automatically running "bootcmd" is
+bootdelay=2
+
+# how long before it "times out" console input and attempts to run "bootcmd"
+bootretry=5
+
+# arguments passed to the boot program (i.e. linux kernel) via register 6
+# the linux kernel (v2.4) uses the following registers:
+#	r3 - address of board information structure
+#	r4 - address of initial ramdisk image (0 means no initrd)
+#	r5 - size of initial ramdisk image
+#	r6 - address of command line string
+-bootargs=root=/dev/mtdblock5 rootfstype=squashfs ro
+
+# these four are for hymod linux integrated into our Sun network
+bootargs+=serialno=%S
+bootargs+=nisclient nisdomain=mlb.dmt.csiro.au nissrvadr=138.194.112.4
+bootargs+=nfsclient
+bootargs+=automount
+
+# start a web server by default
+bootargs+=webserver
+
+# give negotiation time to finish
+bootargs+=netsleep=5
+
+# then our ciscos don't pass packets for 25-30 secs after that, so
+# pinging the server until it responds prevents network connections
+# from failing...
+bootargs+=netping
+
+# these are old bootargs - we don't need them anymore
+bootargs-=preload=unix,i2c-cpm,i2c-dev
+bootargs-=ramdisk_size=32768
+bootargs-=ramdisk_size=24576
+
+# FLASH MANIPULATION COMMANDS
+
+#
+# 16M flash, 64 x 256K sectors, mapped at address 0x40000000
+#
+# Sector(s)	Address		Size	Description
+#
+#  0 -  0	0x40000000	256K	boot code
+#  1 -  1	0x40040000	256K	non volatile environment
+#  2 -  4	0x40080000	768K	linux kernel image
+#  5 -  7	0x40140000	768K	alternate linux kernel image
+#  8 - 47	0x40200000	 10M	linux initial ramdisk image
+# 48 - 63	0x40c00000	  4M	ramdisk image for applications
+#
+
+fetchboot=tftp 100000 /hymod/u-boot.bin
+eraseboot=protect off 1:0 ; erase 1:0 ; protect on 1:0
+copyboot=protect off 1:0 ; cp.b 100000 40000000 40000 ; protect on 1:0
+cmpboot=cmp.b 100000 40000000 40000
+newboot=run fetchboot eraseboot copyboot cmpboot
+
+fetchlinux=tftp 100000 /hymod/linux.bin
+eraselinux=erase 1:2-4
+copylinux=cp.b 100000 40080000 ${filesize}
+cmplinux=cmp.b 100000 40080000 ${filesize}
+newlinux=run fetchlinux eraselinux copylinux cmplinux
+
+fetchaltlinux=tftp 100000 /hymod/altlinux.bin
+erasealtlinux=erase 1:5-7
+copyaltlinux=cp.b 100000 40140000 ${filesize}
+cmpaltlinux=cmp.b 100000 40140000 ${filesize}
+newaltlinux=run fetchaltlinux erasealtlinux copyaltlinux cmpaltlinux
+
+fetchroot=tftp 100000 /hymod/root.bin
+eraseroot=erase 1:8-47
+copyroot=cp.b 100000 40200000 ${filesize}
+cmproot=cmp.b 100000 40200000 ${filesize}
+newroot=run fetchroot eraseroot copyroot cmproot
+
+fetchard=tftp 100000 /hymod/apprd.bin
+eraseard=erase 1:48-63
+copyard=cp.b 100000 40c00000 ${filesize}
+cmpard=cmp.b 100000 40c00000 ${filesize}
+newapprd=run fetchard eraseard copyard cmpard
+
+# pass above map to linux mtd driver
+bootargs+=mtdparts=phys:256k(u-boot),256k(u-boot-env),768k(linux),768k(altlinux),10m(root),4m(hymod)
diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c
new file mode 100755
index 0000000..dea0a70
--- /dev/null
+++ b/board/hymod/hymod.c
@@ -0,0 +1,537 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for the Hymod board by Murray.Jensen@csiro.au, 20-Oct-00
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <mpc8260_irq.h>
+#include <ioports.h>
+#include <i2c.h>
+#include <asm/iopin_8260.h>
+
+/* ------------------------------------------------------------------------- */
+
+/* imports from eeprom.c */
+extern int hymod_eeprom_read (int, hymod_eeprom_t *);
+extern void hymod_eeprom_print (hymod_eeprom_t *);
+
+/* imports from env.c */
+extern void hymod_check_env (void);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+	/* Port A configuration */
+	{
+		/* cnf par sor dir odr dat */
+		{   1,  1,  1,  0,  0,  0   },	/* PA31: FCC1 MII COL */
+		{   1,  1,  1,  0,  0,  0   },	/* PA30: FCC1 MII CRS */
+		{   1,  1,  1,  1,  0,  0   },	/* PA29: FCC1 MII TX_ER */
+		{   1,  1,  1,  1,  0,  0   },	/* PA28: FCC1 MII TX_EN */
+		{   1,  1,  1,  0,  0,  0   },	/* PA27: FCC1 MII RX_DV */
+		{   1,  1,  1,  0,  0,  0   },	/* PA26: FCC1 MII RX_ER */
+		{   1,  0,  0,  1,  0,  0   },	/* PA25: FCC2 MII MDIO */
+		{   1,  0,  0,  1,  0,  0   },	/* PA24: FCC2 MII MDC */
+		{   1,  0,  0,  1,  0,  0   },	/* PA23: FCC3 MII MDIO */
+		{   1,  0,  0,  1,  0,  0   },	/* PA22: FCC3 MII MDC */
+		{   1,  1,  0,  1,  0,  0   },	/* PA21: FCC1 MII TxD[3] */
+		{   1,  1,  0,  1,  0,  0   },	/* PA20: FCC1 MII TxD[2] */
+		{   1,  1,  0,  1,  0,  0   },	/* PA19: FCC1 MII TxD[1] */
+		{   1,  1,  0,  1,  0,  0   },	/* PA18: FCC1 MII TxD[0] */
+		{   1,  1,  0,  0,  0,  0   },	/* PA17: FCC1 MII RxD[3] */
+		{   1,  1,  0,  0,  0,  0   },	/* PA16: FCC1 MII RxD[2] */
+		{   1,  1,  0,  0,  0,  0   },	/* PA15: FCC1 MII RxD[1] */
+		{   1,  1,  0,  0,  0,  0   },	/* PA14: FCC1 MII RxD[0] */
+		{   1,  0,  0,  1,  0,  0   },	/* PA13: FCC1 MII MDIO */
+		{   1,  0,  0,  1,  0,  0   },	/* PA12: FCC1 MII MDC */
+		{   1,  0,  0,  1,  0,  0   },	/* PA11: SEL_CD */
+		{   1,  0,  0,  0,  0,  0   },	/* PA10: FLASH STS1 */
+		{   1,  0,  0,  0,  0,  0   },	/* PA09: FLASH STS0 */
+		{   1,  0,  0,  0,  0,  0   },	/* PA08: FLASH ~PE */
+		{   1,  0,  0,  0,  0,  0   },	/* PA07: WATCH ~HRESET */
+		{   1,  0,  0,  0,  1,  0   },	/* PA06: VC DONE */
+		{   1,  0,  0,  1,  1,  0   },	/* PA05: VC INIT */
+		{   1,  0,  0,  1,  0,  0   },	/* PA04: VC ~PROG */
+		{   1,  0,  0,  1,  0,  0   },	/* PA03: VM ENABLE */
+		{   1,  0,  0,  0,  1,  0   },	/* PA02: VM DONE */
+		{   1,  0,  0,  1,  1,  0   },	/* PA01: VM INIT */
+		{   1,  0,  0,  1,  0,  0   } 	/* PA00: VM ~PROG */
+	},
+
+	/* Port B configuration */
+	{
+		/* cnf par sor dir odr dat */
+		{   1,  1,  0,  1,  0,  0   },	/* PB31: FCC2 MII TX_ER */
+		{   1,  1,  0,  0,  0,  0   },	/* PB30: FCC2 MII RX_DV */
+		{   1,  1,  1,  1,  0,  0   },	/* PB29: FCC2 MII TX_EN */
+		{   1,  1,  0,  0,  0,  0   },	/* PB28: FCC2 MII RX_ER */
+		{   1,  1,  0,  0,  0,  0   },	/* PB27: FCC2 MII COL */
+		{   1,  1,  0,  0,  0,  0   },	/* PB26: FCC2 MII CRS */
+		{   1,  1,  0,  1,  0,  0   },	/* PB25: FCC2 MII TxD[3] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB24: FCC2 MII TxD[2] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB23: FCC2 MII TxD[1] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB22: FCC2 MII TxD[0] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB21: FCC2 MII RxD[0] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB20: FCC2 MII RxD[1] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB19: FCC2 MII RxD[2] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB18: FCC2 MII RxD[3] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB17: FCC3 MII RX_DV */
+		{   1,  1,  0,  0,  0,  0   },	/* PB16: FCC3 MII RX_ER */
+		{   1,  1,  0,  1,  0,  0   },	/* PB15: FCC3 MII TX_ER */
+		{   1,  1,  0,  1,  0,  0   },	/* PB14: FCC3 MII TX_EN */
+		{   1,  1,  0,  0,  0,  0   },	/* PB13: FCC3 MII COL */
+		{   1,  1,  0,  0,  0,  0   },	/* PB12: FCC3 MII CRS */
+		{   1,  1,  0,  0,  0,  0   },	/* PB11: FCC3 MII RxD[3] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB10: FCC3 MII RxD[2] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB09: FCC3 MII RxD[1] */
+		{   1,  1,  0,  0,  0,  0   },	/* PB08: FCC3 MII RxD[0] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB07: FCC3 MII TxD[3] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB06: FCC3 MII TxD[2] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB05: FCC3 MII TxD[1] */
+		{   1,  1,  0,  1,  0,  0   },	/* PB04: FCC3 MII TxD[0] */
+		{   0,  0,  0,  0,  0,  0   },	/* PB03: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   },	/* PB02: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   },	/* PB01: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   }	/* PB00: pin doesn't exist */
+	},
+
+	/* Port C configuration */
+	{
+		/* cnf par sor dir odr dat */
+		{   1,  0,  0,  0,  0,  0   },	/* PC31: MEZ ~IACK */
+		{   0,  0,  0,  0,  0,  0   },	/* PC30: ? */
+		{   1,  1,  0,  0,  0,  0   },	/* PC29: CLK SCCx */
+		{   1,  1,  0,  0,  0,  0   },	/* PC28: CLK4 */
+		{   1,  1,  0,  0,  0,  0   },	/* PC27: CLK SCCF */
+		{   1,  1,  0,  0,  0,  0   },	/* PC26: CLK 32K */
+		{   1,  1,  0,  0,  0,  0   },	/* PC25: BRG4/CLK7 */
+		{   0,  0,  0,  0,  0,  0   },	/* PC24: ? */
+		{   1,  1,  0,  0,  0,  0   },	/* PC23: CLK SCCx */
+		{   1,  1,  0,  0,  0,  0   },	/* PC22: FCC1 MII RX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC21: FCC1 MII TX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC20: CLK SCCF */
+		{   1,  1,  0,  0,  0,  0   },	/* PC19: FCC2 MII RX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC18: FCC2 MII TX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC17: FCC3 MII RX_CLK */
+		{   1,  1,  0,  0,  0,  0   },	/* PC16: FCC3 MII TX_CLK */
+		{   1,  0,  0,  0,  0,  0   },	/* PC15: SCC1 UART ~CTS */
+		{   1,  0,  0,  0,  0,  0   },	/* PC14: SCC1 UART ~CD */
+		{   1,  0,  0,  0,  0,  0   },	/* PC13: SCC2 UART ~CTS */
+		{   1,  0,  0,  0,  0,  0   },	/* PC12: SCC2 UART ~CD */
+		{   1,  0,  0,  1,  0,  0   },	/* PC11: SCC1 UART ~DTR */
+		{   1,  0,  0,  1,  0,  0   },	/* PC10: SCC1 UART ~DSR */
+		{   1,  0,  0,  1,  0,  0   },	/* PC09: SCC2 UART ~DTR */
+		{   1,  0,  0,  1,  0,  0   },	/* PC08: SCC2 UART ~DSR */
+		{   1,  0,  0,  0,  0,  0   },	/* PC07: TEMP ~ALERT */
+		{   1,  0,  0,  0,  0,  0   },	/* PC06: FCC3 INT */
+		{   1,  0,  0,  0,  0,  0   },	/* PC05: FCC2 INT */
+		{   1,  0,  0,  0,  0,  0   },	/* PC04: FCC1 INT */
+		{   0,  1,  1,  1,  0,  0   },	/* PC03: SDMA IDMA2 ~DACK */
+		{   0,  1,  1,  0,  0,  0   },	/* PC02: SDMA IDMA2 ~DONE */
+		{   0,  1,  0,  0,  0,  0   },	/* PC01: SDMA IDMA2 ~DREQ */
+		{   1,  1,  0,  1,  0,  0   }	/* PC00: BRG7 */
+	},
+
+	/* Port D configuration */
+	{
+		/* cnf par sor dir odr dat */
+		{   1,  1,  0,  0,  0,  0   },	/* PD31: SCC1 UART RxD */
+		{   1,  1,  1,  1,  0,  0   },	/* PD30: SCC1 UART TxD */
+		{   1,  0,  0,  1,  0,  0   },	/* PD29: SCC1 UART ~RTS */
+		{   1,  1,  0,  0,  0,  0   },	/* PD28: SCC2 UART RxD */
+		{   1,  1,  0,  1,  0,  0   },	/* PD27: SCC2 UART TxD */
+		{   1,  0,  0,  1,  0,  0   },	/* PD26: SCC2 UART ~RTS */
+		{   1,  0,  0,  0,  0,  0   },	/* PD25: SCC1 UART ~RI */
+		{   1,  0,  0,  0,  0,  0   },	/* PD24: SCC2 UART ~RI */
+		{   1,  0,  0,  1,  0,  0   },	/* PD23: CLKGEN PD */
+		{   1,  0,  0,  0,  0,  0   },	/* PD22: USER3 */
+		{   1,  0,  0,  0,  0,  0   },	/* PD21: USER2 */
+		{   1,  0,  0,  0,  0,  0   },	/* PD20: USER1 */
+		{   1,  1,  1,  0,  0,  0   },	/* PD19: SPI ~SEL */
+		{   1,  1,  1,  0,  0,  0   },	/* PD18: SPI CLK */
+		{   1,  1,  1,  0,  0,  0   },	/* PD17: SPI MOSI */
+		{   1,  1,  1,  0,  0,  0   },	/* PD16: SPI MISO */
+		{   1,  1,  1,  0,  1,  0   },	/* PD15: I2C SDA */
+		{   1,  1,  1,  0,  1,  0   },	/* PD14: I2C SCL */
+		{   1,  0,  0,  1,  0,  1   },	/* PD13: TEMP ~STDBY */
+		{   1,  0,  0,  1,  0,  1   },	/* PD12: FCC3 ~RESET */
+		{   1,  0,  0,  1,  0,  1   },	/* PD11: FCC2 ~RESET */
+		{   1,  0,  0,  1,  0,  1   },	/* PD10: FCC1 ~RESET */
+		{   1,  0,  0,  0,  0,  0   },	/* PD09: PD9 */
+		{   1,  0,  0,  0,  0,  0   },	/* PD08: PD8 */
+		{   1,  0,  0,  1,  0,  1   },	/* PD07: PD7 */
+		{   1,  0,  0,  1,  0,  1   },	/* PD06: PD6 */
+		{   1,  0,  0,  1,  0,  1   },	/* PD05: PD5 */
+		{   1,  0,  0,  1,  0,  1   },	/* PD04: PD4 */
+		{   0,  0,  0,  0,  0,  0   },	/* PD03: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   },	/* PD02: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   },	/* PD01: pin doesn't exist */
+		{   0,  0,  0,  0,  0,  0   }	/* PD00: pin doesn't exist */
+	}
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * AMI FS6377 Clock Generator configuration table
+ *
+ * the "fs6377_regs[]" table entries correspond to FS6377 registers
+ * 0 - 15 (total of 16 bytes).
+ *
+ * the data is written to the FS6377 via the i2c bus using address in
+ * "fs6377_addr" (address is 7 bits - R/W bit not included).
+ *
+ * The fs6377 has four clock outputs: A, B, C and D.
+ *
+ * Outputs C and D can each provide two different clock outputs C1/D1 or
+ * C2/D2 depending on the state of the SEL_CD input which is connected to
+ * the MPC8260 I/O port pin PA11. PA11 output (SEL_CD input) low (or 0)
+ * selects C1/D1 and PA11 output (SEL_CD input) high (or 1) selects C2/D2.
+ *
+ * PA11 defaults to output low (or 0) in the i/o port config table above.
+ *
+ * Output A provides a 100MHz for the High Speed Serial chips. Output B
+ * provides a 3.6864MHz clock for more accurate asynchronous serial bit
+ * rates. Output C is routed to the mezzanine connector but is currently
+ * unused - both C1 and C2 are set to 16MHz. Output D is used by both the
+ * alt-input and display mezzanine boards for their video chips. The
+ * alt-input board requires a clock of 24.576MHz and this is available on
+ * D1 (PA11=SEL_CD=0). The display board requires a clock of 27MHz and this
+ * is available on D2 (PA11=SEL_CD=1).
+ *
+ * So the default is a clock suitable for the alt-input board. PA11 is toggled
+ * later in misc_init_r(), if a display board is detected.
+ */
+
+uchar fs6377_addr = 0x5c;
+
+uchar fs6377_regs[16] = {
+	 12,  75,  64,  25, 144, 128,  25, 192,
+	  0,  16, 135, 192, 224,  64,  64, 192
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * special board initialisation, after clocks and timebase have been
+ * set up but before environment and serial are initialised.
+ *
+ * added so that very early initialisations can be done using the i2c
+ * driver (which requires the clocks, to calculate the dividers, and
+ * the timebase, for udelay())
+ */
+
+int
+board_postclk_init (void)
+{
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/*
+	 * Initialise the FS6377 clock chip
+	 *
+	 * the secondary address is the register number from where to
+	 * start the write - I want to write all the registers
+	 *
+	 * don't bother checking return status - we have no console yet
+	 * to print it on, nor any RAM to store it in - it will be obvious
+	 * if this doesn't work
+	 */
+	(void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
+					sizeof (fs6377_regs));
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity: Hardwired to HYMOD
+ */
+
+int
+checkboard (void)
+{
+	puts ("Board: HYMOD\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * miscellaneous (early - while running in flash) initialisations.
+ */
+
+#define _NOT_USED_	0xFFFFFFFF
+
+uint upmb_table[] = {
+	/* Read Single Beat (RSS) - offset 0x00 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Read Burst (RBS) - offset 0x08 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Write Single Beat (WSS) - offset 0x18 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Write Burst (WSS) - offset 0x20 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Refresh Timer (PTS) - offset 0x30 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Exception Condition (EXS) - offset 0x3c */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+uint upmc_table[] = {
+	/* Read Single Beat (RSS) - offset 0x00 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Read Burst (RBS) - offset 0x08 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Write Single Beat (WSS) - offset 0x18 */
+	0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
+	0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Write Burst (WSS) - offset 0x20 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Refresh Timer (PTS) - offset 0x30 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/* Exception Condition (EXS) - offset 0x3c */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
+};
+
+int
+misc_init_f (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	printf ("UPMs:  ");
+
+	upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
+	memctl->memc_mbmr = CFG_MBMR;
+
+	upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
+	memctl->memc_mcmr = CFG_MCMR;
+
+	printf ("configured\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long
+initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
+	ulong psdmr = CFG_PSDMR;
+	int i;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are conÞgured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+	return (CFG_SDRAM_SIZE << 20);
+}
+
+/* ------------------------------------------------------------------------- */
+/* miscellaneous initialisations after relocation into ram (misc_init_r)     */
+/* 									     */
+/* loads the data in the main board and mezzanine board eeproms into	     */
+/* the hymod configuration struct stored in the board information area.	     */
+/* 									     */
+/* if the contents of either eeprom is invalid, prompts for a serial	     */
+/* number (and an ethernet address if required) then fetches a file	     */
+/* containing information to be stored in the eeprom from the tftp server    */
+/* (the file name is based on the serial number and a built-in path)	     */
+
+int
+last_stage_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
+	int rc;
+
+#ifdef CONFIG_BOOT_RETRY_TIME
+	/*
+	 * we use the readline () function, but we also want
+	 * command timeout enabled
+	 */
+	init_cmd_timeout ();
+#endif
+
+	memset ((void *) cp, 0, sizeof (*cp));
+
+	/* set up main board config info */
+
+	rc = hymod_eeprom_read (0, &cp->main.eeprom);
+
+	puts ("EEPROM:main...");
+	if (rc < 0)
+		puts ("NOT PRESENT\n");
+	else if (rc == 0)
+		puts ("INVALID\n");
+	else {
+		cp->main.eeprom.valid = 1;
+
+		printf ("OK (ver %u)\n", cp->main.eeprom.ver);
+		hymod_eeprom_print (&cp->main.eeprom);
+
+		/*
+		 * hard-wired assumption here: all hymod main boards will have
+		 * one xilinx fpga, with the interrupt line connected to IRQ2
+		 *
+		 * One day, this might be based on the board type
+		 */
+
+		cp->main.xlx[0].mmap.prog.exists = 1;
+		cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
+		cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;
+
+		cp->main.xlx[0].mmap.reg.exists = 1;
+		cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
+		cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;
+
+		cp->main.xlx[0].mmap.port.exists = 1;
+		cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
+		cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;
+
+		cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
+		cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
+		cp->main.xlx[0].iopins.prog_pin.flag = 1;
+		cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
+		cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
+		cp->main.xlx[0].iopins.init_pin.flag = 1;
+		cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
+		cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
+		cp->main.xlx[0].iopins.done_pin.flag = 1;
+#ifdef FPGA_MAIN_ENABLE_PORT
+		cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
+		cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
+		cp->main.xlx[0].iopins.enable_pin.flag = 1;
+#endif
+
+		cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
+	}
+
+	/* set up mezzanine board config info */
+
+	rc = hymod_eeprom_read (1, &cp->mezz.eeprom);
+
+	puts ("EEPROM:mezz...");
+	if (rc < 0)
+		puts ("NOT PRESENT\n");
+	else if (rc == 0)
+		puts ("INVALID\n");
+	else {
+		cp->main.eeprom.valid = 1;
+
+		printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
+		hymod_eeprom_print (&cp->mezz.eeprom);
+	}
+
+	cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));
+
+	hymod_check_env ();
+
+	return (0);
+}
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void board_show_activity (ulong timebase)
+{
+#ifdef CFG_HYMOD_DBLEDS
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile iop8260_t *iop = &immr->im_ioport;
+	static int shift = 0;
+
+	if ((timestamp % CFG_HZ) == 0) {
+		if (++shift > 3)
+			shift = 0;
+		iop->iop_pdatd =
+				(iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
+	}
+#endif /* CFG_HYMOD_DBLEDS */
+}
+
+void show_activity(int arg)
+{
+}
+#endif /* CONFIG_SHOW_ACTIVITY */
diff --git a/board/hymod/hymod.h b/board/hymod/hymod.h
new file mode 100755
index 0000000..9d8d662
--- /dev/null
+++ b/board/hymod/hymod.h
@@ -0,0 +1,322 @@
+/*
+ * (C) Copyright 2001
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _HYMOD_H_
+#define _HYMOD_H_
+
+#include <linux/config.h>
+#ifdef CONFIG_8260
+#include <asm/iopin_8260.h>
+#endif
+
+/*
+ * hymod configuration data - passed by boot code via the board information
+ * structure (only U-Boot has support for this at the moment)
+ *
+ * there are three types of data passed up from the boot monitor. the first
+ * (type hymod_eeprom_t) is the eeprom data that was read off both the main
+ * (or mother) board and the mezzanine board (if any). this data defines how
+ * many Xilinx fpgas are on each board, and their types (among other things).
+ * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where
+ * in the physical address space the various Xilinx fpga access regions have
+ * been mapped by the boot rom. the third type of data (type xlx_iopins_t,
+ * one per Xilinx fpga) defines which io port pins are connected to the various
+ * signals required to program a Xilinx fpga.
+ *
+ * A ram/flash "bank" refers to memory controlled by the same chip select.
+ *
+ * the eeprom contents are defined as in technical note #2 - basically,
+ * a header, zero or more records in no particular order, and a 32 bit crc
+ * a record is 1 or more type bytes, a length byte and "length" bytes.
+ */
+
+#define HYMOD_EEPROM_ID		0xAA	/* eeprom id byte */
+#define HYMOD_EEPROM_VER	1	/* eeprom contents version (0-127) */
+#define HYMOD_EEPROM_SIZE	256	/* number of bytes in the eeprom */
+
+/* eeprom header */
+typedef
+    struct {
+	unsigned char id;		/* eeprom id byte */
+	unsigned char :1;
+	unsigned char ver:7;		/* eeprom contents version number */
+	unsigned long len;		/* total # of bytes btw hdr and crc */
+    }
+hymod_eehdr_t;
+
+/* maximum number of bytes available for eeprom data records */
+#define HYMOD_EEPROM_MAXLEN	(HYMOD_EEPROM_SIZE \
+					- sizeof (hymod_eehdr_t) \
+					- sizeof (unsigned long))
+
+/* eeprom data record */
+typedef
+    union {
+	struct {
+	    unsigned char topbit:1;
+	    unsigned char type:7;
+	    unsigned char len;
+	    unsigned char data[1];	/* variable length */
+	} small;
+	struct {
+	    unsigned short topbit:1;
+	    unsigned short nxtbit:1;
+	    unsigned short type:14;
+	    unsigned short len;
+	    unsigned char data[1];	/* variable length */
+	} medium;
+	struct {
+	    unsigned long topbit:1;
+	    unsigned long nxtbit:1;
+	    unsigned long type:30;
+	    unsigned long len;
+	    unsigned char data[1];	/* variable length */
+	} large;
+    }
+hymod_eerec_t;
+
+#define HYMOD_EEOFF_MAIN	0x00	/* i2c addr offset for main eeprom */
+#define HYMOD_EEOFF_MEZZ	0x04	/* i2c addr offset for mezz eepomr */
+
+/* eeprom record types */
+#define HYMOD_EEREC_SERNO	1	/* serial number */
+#define HYMOD_EEREC_DATE	2	/* date */
+#define HYMOD_EEREC_BATCH	3	/* batch id */
+#define HYMOD_EEREC_TYPE	4	/* board type */
+#define HYMOD_EEREC_REV		5	/* revision number */
+#define HYMOD_EEREC_SDRAM	6	/* sdram sizes */
+#define HYMOD_EEREC_FLASH	7	/* flash sizes */
+#define HYMOD_EEREC_ZBT		8	/* zbt ram sizes */
+#define HYMOD_EEREC_XLXTYP	9	/* Xilinx fpga types */
+#define HYMOD_EEREC_XLXSPD	10	/* Xilinx fpga speeds */
+#define HYMOD_EEREC_XLXTMP	11	/* Xilinx fpga temperatures */
+#define HYMOD_EEREC_XLXGRD	12	/* Xilinx fpga grades */
+#define HYMOD_EEREC_CPUTYP	13	/* Motorola CPU type */
+#define HYMOD_EEREC_CPUSPD	14	/* CPU speed */
+#define HYMOD_EEREC_BUSSPD	15	/* bus speed */
+#define HYMOD_EEREC_CPMSPD	16	/* CPM speed */
+#define HYMOD_EEREC_HSTYPE	17	/* high-speed serial chip type */
+#define HYMOD_EEREC_HSCHIN	18	/* high-speed serial input channels */
+#define HYMOD_EEREC_HSCHOUT	19	/* high-speed serial output channels */
+
+/* some dimensions */
+#define HYMOD_MAX_BATCH		32	/* max no. of bytes in batch id */
+#define HYMOD_MAX_SDRAM		4	/* max sdram "banks" on any board */
+#define HYMOD_MAX_FLASH		4	/* max flash "banks" on any board */
+#define HYMOD_MAX_ZBT		16	/* max ZBT rams on any board */
+#define HYMOD_MAX_XLX		4	/* max Xilinx fpgas on any board */
+
+#define HYMOD_MAX_BYTES		16	/* enough to store any bytes array */
+
+/* board types */
+#define HYMOD_BDTYPE_NONE	0	/* information not present */
+#define HYMOD_BDTYPE_IO		1	/* I/O main board */
+#define HYMOD_BDTYPE_CLP	2	/* CLP main board */
+#define HYMOD_BDTYPE_DSP	3	/* DSP main board */
+#define HYMOD_BDTYPE_INPUT	4	/* video input mezzanine board */
+#define HYMOD_BDTYPE_ALTINPUT	5	/* video input mezzanine board */
+#define HYMOD_BDTYPE_DISPLAY	6	/* video display mezzanine board */
+#define HYMOD_BDTYPE_MAX	7	/* first invalid value */
+
+/* Xilinx fpga types */
+#define HYMOD_XTYP_NONE		0	/* information not present */
+#define HYMOD_XTYP_XCV300E	1	/* Xilinx Virtex 300 */
+#define HYMOD_XTYP_XCV400E	2	/* Xilinx Virtex 400 */
+#define HYMOD_XTYP_XCV600E	3	/* Xilinx Virtex 600 */
+#define HYMOD_XTYP_MAX		4	/* first invalid value */
+
+/* Xilinx fpga speeds */
+#define HYMOD_XSPD_NONE		0	/* information not present */
+#define HYMOD_XSPD_SIX		1
+#define HYMOD_XSPD_SEVEN	2
+#define HYMOD_XSPD_EIGHT	3
+#define HYMOD_XSPD_MAX		4	/* first invalid value */
+
+/* Xilinx fpga temperatures */
+#define HYMOD_XTMP_NONE		0	/* information not present */
+#define HYMOD_XTMP_COM		1
+#define HYMOD_XTMP_IND		2
+#define HYMOD_XTMP_MAX		3	/* first invalid value */
+
+/* Xilinx fpga grades */
+#define HYMOD_XTMP_NONE		0	/* information not present */
+#define HYMOD_XTMP_NORMAL	1
+#define HYMOD_XTMP_ENGSAMP	2
+#define HYMOD_XTMP_MAX		3	/* first invalid value */
+
+/* CPU types */
+#define HYMOD_CPUTYPE_NONE	0	/* information not present */
+#define HYMOD_CPUTYPE_MPC8260	1	/* Motorola MPC8260 embedded powerpc */
+#define HYMOD_CPUTYPE_MAX	2	/* first invalid value */
+
+/* CPU/BUS/CPM clock speeds */
+#define HYMOD_CLKSPD_NONE	0	/* information not present */
+#define HYMOD_CLKSPD_33MHZ	1
+#define HYMOD_CLKSPD_66MHZ	2
+#define HYMOD_CLKSPD_100MHZ	3
+#define HYMOD_CLKSPD_133MHZ	4
+#define HYMOD_CLKSPD_166MHZ	5
+#define HYMOD_CLKSPD_200MHZ	6
+#define HYMOD_CLKSPD_MAX	7	/* first invalid value */
+
+/* high speed serial chip types */
+#define HYMOD_HSSTYPE_NONE	0	/* information not present */
+#define HYMOD_HSSTYPE_AMCC52064	1
+#define HYMOD_HSSTYPE_MAX	2	/* first invalid value */
+
+/* a date (yyyy-mm-dd) */
+typedef
+    struct {
+	unsigned short year;
+	unsigned char month;
+	unsigned char day;
+    }
+hymod_date_t;
+
+/* describes a Xilinx fpga */
+typedef
+    struct {
+	unsigned char type;		/* chip type */
+	unsigned char speed;		/* chip speed rating */
+	unsigned char temp;		/* chip temperature rating */
+	unsigned char grade;		/* chip grade */
+    }
+hymod_xlx_t;
+
+/* describes a Motorola embedded processor */
+typedef
+    struct {
+	unsigned char type;		/* CPU type */
+	unsigned char cpuspd;		/* speed of the PowerPC core */
+	unsigned char busspd;		/* speed of the system and 60x bus */
+	unsigned char cpmspd;		/* speed of the CPM co-processor */
+    }
+hymod_mpc_t;
+
+/* info about high-speed (1Gbit) serial interface */
+typedef
+    struct {
+	unsigned char type;		/* high-speed serial chip type */
+	unsigned char nchin;		/* number of input channels mounted */
+	unsigned char nchout;		/* number of output channels mounted */
+    }
+hymod_hss_t;
+
+/*
+ * this defines the contents of the serial eeprom that exists on every
+ * hymod board, including mezzanine boards (the serial eeprom will be
+ * faked for early development boards that don't have one)
+ */
+
+typedef
+    struct {
+	unsigned char valid:1;		/* contents of this struct is valid */
+	unsigned char ver:7;		/* eeprom contents version */
+	unsigned char bdtype;		/* board type */
+	unsigned char bdrev;		/* board revision */
+	unsigned char batchlen;		/* length of batch string below */
+	unsigned long serno;		/* serial number */
+	hymod_date_t date;		/* manufacture date */
+	unsigned char batch[32];	/* manufacturer specific batch id */
+	unsigned char nsdram;		/* # of ram "banks" */
+	unsigned char nflash;		/* # of flash "banks" */
+	unsigned char nzbt;		/* # of ZBT rams */
+	unsigned char nxlx;		/* # of Xilinx fpgas */
+	unsigned char sdramsz[HYMOD_MAX_SDRAM];	/* log2 of sdram size */
+	unsigned char flashsz[HYMOD_MAX_FLASH];	/* log2 of flash size */
+	unsigned char zbtsz[HYMOD_MAX_ZBT];	/* log2 of ZBT ram size */
+	hymod_xlx_t xlx[HYMOD_MAX_XLX];	/* Xilinx fpga info */
+	hymod_mpc_t mpc;		/* Motorola MPC CPU info */
+	hymod_hss_t hss;		/* high-speed serial info */
+    }
+hymod_eeprom_t;
+
+/*
+ * this defines a region in the processor's physical address space
+ */
+typedef
+    struct {
+	unsigned long exists:1;		/* 1 if the region exists, 0 if not */
+	unsigned long size:31;		/* size in bytes */
+	unsigned long base;		/* base address */
+    }
+xlx_prgn_t;
+
+/*
+ * this defines where the various Xilinx fpga access regions are mapped
+ * into the physical address space of the processor
+ */
+typedef
+    struct {
+	xlx_prgn_t prog;		/* program access region */
+	xlx_prgn_t reg;			/* register access region */
+	xlx_prgn_t port;		/* port access region */
+    }
+xlx_mmap_t;
+
+/*
+ * this defines which 8260 i/o port pins are connected to the various
+ * signals required for programming a Xilinx fpga
+ */
+typedef
+    struct {
+	iopin_t prog_pin;		/* assert for >= 300ns to program */
+	iopin_t init_pin;		/* goes high when fpga is cleared */
+	iopin_t done_pin;		/* goes high when program is done */
+	iopin_t enable_pin;		/* some fpgas need enabling */
+    }
+xlx_iopins_t;
+
+/* all info about one Xilinx chip */
+typedef
+    struct {
+	xlx_mmap_t mmap;
+	xlx_iopins_t iopins;
+	unsigned long irq:8;		/* h/w intr req number for this fpga */
+    }
+xlx_info_t;
+
+/* all info about one hymod board */
+typedef
+    struct {
+	hymod_eeprom_t eeprom;
+	xlx_info_t xlx[HYMOD_MAX_XLX];
+    }
+hymod_board_t;
+
+/*
+ * this defines the configuration information of a hymod board-set
+ * (main board + possible mezzanine board). In future, there may be
+ * more than one mezzanine board (stackable?) - if so, add a "mezz2"
+ * field, and so on... or make mezz an array?
+ */
+typedef
+    struct {
+	unsigned long ver:8;		/* version control */
+	hymod_board_t main;		/* main board info */
+	hymod_board_t mezz;		/* mezzanine board info */
+	unsigned long crc;		/* ensures kernel and boot prom agree */
+    }
+hymod_conf_t;
+
+#endif /* _HYMOD_H_ */
diff --git a/board/hymod/input.c b/board/hymod/input.c
new file mode 100755
index 0000000..63aa13c
--- /dev/null
+++ b/board/hymod/input.c
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2003
+ * Murray Jensen, CSIRO-MIT, <Murray.Jensen@csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* imports from common/main.c */
+extern char console_buffer[CFG_CBSIZE];
+
+int
+hymod_get_serno (const char *prompt)
+{
+	for (;;) {
+		int n, serno;
+		char *p;
+
+#ifdef CONFIG_BOOT_RETRY_TIME
+		reset_cmd_timeout ();
+#endif
+
+		n = readline (prompt);
+
+		if (n < 0)
+			return (n);
+
+		if (n == 0)
+			continue;
+
+		serno = (int) simple_strtol (console_buffer, &p, 10);
+
+		if (p > console_buffer && *p == '\0' && serno > 0)
+			return (serno);
+
+		printf ("Invalid number (%s) - please re-enter\n",
+			console_buffer);
+	}
+}
+
+int
+hymod_get_ethaddr (void)
+{
+	for (;;) {
+		int n;
+
+#ifdef CONFIG_BOOT_RETRY_TIME
+		reset_cmd_timeout ();
+#endif
+
+		n = readline ("Enter board ethernet address: ");
+
+		if (n < 0)
+			return (n);
+
+		if (n == 0)
+			continue;
+
+		if (n == 17) {
+			int i;
+			char *p, *q;
+			uchar ea[6];
+
+			/* see if it looks like an ethernet address */
+
+			p = console_buffer;
+
+			for (i = 0; i < 6; i++) {
+				char term = (i == 5 ? '\0' : ':');
+
+				ea[i] = simple_strtol (p, &q, 16);
+
+				if ((q - p) != 2 || *q++ != term)
+					break;
+
+				p = q;
+			}
+
+			if (i == 6) {
+				/* it looks ok - set it */
+				printf ("Setting ethernet addr to %s\n",
+					console_buffer);
+
+				setenv ("ethaddr", console_buffer);
+
+				puts ("Remember to do a 'saveenv' to "
+					"make it permanent\n");
+
+				return (0);
+			}
+		}
+
+		printf ("Invalid ethernet addr (%s) - please re-enter\n",
+			console_buffer);
+	}
+}
diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds
new file mode 100755
index 0000000..337a395
--- /dev/null
+++ b/board/hymod/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8260/start.o	(.text)
+/*
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  . = ALIGN(256 * 1024);
+  .ppcenv	:
+  {
+    common/environment.o (.ppcenv)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug
new file mode 100755
index 0000000..ddd4678
--- /dev/null
+++ b/board/hymod/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/icecube/Makefile b/board/icecube/Makefile
new file mode 100755
index 0000000..eb5ed59
--- /dev/null
+++ b/board/icecube/Makefile
@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/icecube/config.mk b/board/icecube/config.mk
new file mode 100755
index 0000000..07b5de1
--- /dev/null
+++ b/board/icecube/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IceCube board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFF000000   boot low for 16 MiB boards
+#	0xFF800000   boot low for  8 MiB boards
+#	0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
new file mode 100755
index 0000000..713011c
--- /dev/null
+++ b/board/icecube/flash.c
@@ -0,0 +1,491 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(ulong);
+	ulong flashbase = CFG_FLASH_BASE;
+
+	flash_preinit();
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		size += flash_info[i].size;
+		flashbase += 0x800000;
+	}
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+
+	flash_afterinit(size);
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size &&
+			info->start[0] <= base && base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDLV065D:
+		fmt = "29LV065 (64 Mbit, uniform sectors)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int i;
+	FPWV* addr2;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
+
+	case (FPW)AMD_ID_LV065D:
+		info->flash_id += FLASH_AMDLV065D;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = (ulong)addr + (i * 0x10000);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* test for real flash at bank 1 */
+	addr2 = (FPW *)((ulong)addr | 0x800000);
+	if (addr2 != addr &&
+		((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
+		/* Seems 2 banks are the same space (8Mb chip is installed,
+		 * J24 in default position (CS0)). Disable this (first) bank.
+		 */
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+	}
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDLV065D:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		 left > 0 && res == 0;
+		 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
new file mode 100755
index 0000000..1f1a74c
--- /dev/null
+++ b/board/icecube/icecube.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
+int checkboard (void)
+{
+#if defined(CONFIG_MPC5200)
+	puts ("Board: Motorola MPC5200 (IceCube)\n");
+#elif defined(CONFIG_MGT5100)
+	puts ("Board: Motorola MGT5100 (IceCube)\n");
+#endif
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+#if defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+#endif
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x800000) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(CFG_BOOTCS_START | size);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(CFG_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+    	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h
new file mode 100755
index 0000000..4c0f9a7
--- /dev/null
+++ b/board/icecube/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x705f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h
new file mode 100755
index 0000000..ffdf039
--- /dev/null
+++ b/board/icecube/mt48lc16m16a2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/icecube/u-boot.lds b/board/icecube/u-boot.lds
new file mode 100755
index 0000000..f23432e
--- /dev/null
+++ b/board/icecube/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/icu862/Makefile b/board/icu862/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/icu862/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/icu862/config.mk b/board/icu862/config.mk
new file mode 100755
index 0000000..315e70d
--- /dev/null
+++ b/board/icu862/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# ICU862 boards
+#
+
+TEXT_BASE = 0x40F00000
+OBJCFLAGS =	--set-section-flags=.ppcenv=contents,alloc,load,data
diff --git a/board/icu862/flash.c b/board/icu862/flash.c
new file mode 100755
index 0000000..ca5bcf3
--- /dev/null
+++ b/board/icu862/flash.c
@@ -0,0 +1,617 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0,
+			size_b0 >> 20);
+	}
+
+	if (FLASH_BASE1_PRELIM != 0x0) {
+		size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+		if (size_b1 > size_b0) {
+			printf ("## ERROR: Bank 1 (0x%08lx = %ld MB)"
+				" > Bank 0 (0x%08lx = %ld MB)\n",
+				size_b1, size_b1 >> 20,
+				size_b0, size_b0 >> 20);
+
+			flash_info[0].flash_id	= FLASH_UNKNOWN;
+			flash_info[1].flash_id	= FLASH_UNKNOWN;
+			flash_info[0].sector_count	= -1;
+			flash_info[1].sector_count	= -1;
+			flash_info[0].size		= 0;
+			flash_info[1].size		= 0;
+			return (0);
+		}
+	} else {
+		size_b1 = 0;
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	/* ICU862 Board has only one Flash Bank */
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].sector_count = -1;
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+		((info->flash_id & FLASH_TYPEMASK) == FLASH_AM033C)) {
+		/* set sector offsets for uniform sector type	*/
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00040000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	puts ("AMD ");		break;
+	case FLASH_MAN_FUJ:	puts ("FUJITSU ");	break;
+	case FLASH_MAN_BM:	puts ("BRIGHT MICRO ");	break;
+	default:		puts ("Unknown Vendor "); break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	puts ("29F040/29LV040 (4 Mbit, uniform sectors)\n");
+				break;
+	case FLASH_AM400B:	puts ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	puts ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	puts ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	puts ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	puts ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	puts ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	puts ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	puts ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM033C:	puts ("AM29LV033C (32 Mbit)\n");
+				break;
+	default:		puts ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	puts ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			puts ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+
+	puts ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+#if 0
+	ulong base = (ulong)addr;
+#endif
+	uchar value;
+
+	/* Write auto select command: read Manufacturer ID */
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x90909090;
+#endif
+
+	value = addr[0];
+
+	switch (value + (value << 16)) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch ((unsigned long)value) {
+	case AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	case AMD_ID_LV033C:
+		info->flash_id += FLASH_AM033C;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;				/* => 16Mb		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+#if 0
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+#else
+	flash_get_offsets ((ulong)addr, &flash_info[0]);
+#endif
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+#if 1
+		/* We don't know why it happens, but on ICU Board	*
+		 * for AMD29033C flash we need to resend the command of	*
+		 * reading flash protection for upper 8 Mb of flash	*/
+		if ( i == 32 ) {
+			addr[0x0555] = 0xAAAAAAAA;
+			addr[0x02AA] = 0x55555555;
+			addr[0x0555] = 0x90909090;
+		}
+#endif
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+#if 0
+		*addr = 0x00F000F0;	/* reset bank */
+#else
+		*addr = 0xF0F0F0F0;	/* reset bank */
+#endif
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			puts ("- missing\n");
+		} else {
+			puts ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		puts ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		puts ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0x80808080;
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+#endif
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+#if 0
+			addr[0] = 0x00300030;
+#else
+			addr[0] = 0x30303030;
+#endif
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+#if 0
+	while ((addr[0] & 0x00800080) != 0x00800080)
+#else
+	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
+#endif
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			puts ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#if 0
+	addr[0] = 0x00F000F0;	/* reset bank */
+#else
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+#endif
+
+	puts (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+#if 0
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+#else
+	addr[0x0555] = 0xAAAAAAAA;
+	addr[0x02AA] = 0x55555555;
+	addr[0x0555] = 0xA0A0A0A0;
+#endif
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+#if 0
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080))
+#else
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
+#endif
+	{
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c
new file mode 100755
index 0000000..8da9d1c
--- /dev/null
+++ b/board/icu862/icu862.c
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/*
+ *  Memory Controller Using
+ *
+ *  CS0 - Flash memory            (0x40000000)
+ *  CS1 - SDRAM                   (0x00000000}
+ *  CS2 - S/UNI Ultra ATM155
+ *  CS3 - IDT 77106 ATM25
+ *  CS4 - DSP HPI
+ *  CS5 - E1/T1 Interface device
+ *  CS6 - PCMCIA device
+ *  CS7 - PCMCIA device
+ */
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_	0xffffffff
+
+const uint sdram_table[] = {
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* MRS initialization (offset 5) */
+
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: ICU862 Board\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
+	unsigned long reg;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 1 to the SDRAM bank at
+	 * preliminary address - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (200);
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - execute twice */
+	udelay (200);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE1_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE1_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {					/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;					/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds
new file mode 100755
index 0000000..4bc50c5
--- /dev/null
+++ b/board/icu862/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+/*
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug
new file mode 100755
index 0000000..87f228b
--- /dev/null
+++ b/board/icu862/u-boot.lds.debug
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ids8247/Makefile b/board/ids8247/Makefile
new file mode 100755
index 0000000..cfef750
--- /dev/null
+++ b/board/ids8247/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/ids8247/config.mk b/board/ids8247/config.mk
new file mode 100755
index 0000000..136cdb8
--- /dev/null
+++ b/board/ids8247/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IDS 8247 Board
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_IDS8247.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/ids8247/flash.c b/board/ids8247/flash.c
new file mode 100755
index 0000000..4eba4b9
--- /dev/null
+++ b/board/ids8247/flash.c
@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH8
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#elif FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#else /* FLASH_PORT_WIDTH8 */
+#define FLASH_PORT_WIDTH	uchar
+#define FLASH_PORT_WIDTHV	vu_char
+#endif
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPWV * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size ((FPW *) CFG_FLASH0_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	memctl->memc_or0 = 0xff800060;
+	memctl->memc_br0 = 0xff800801;
+
+	flash_get_offsets (0xff800000, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPWV * addr, flash_info_t * info)
+{
+	FPW value;
+
+	addr[0] = (FPW) 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+#ifdef FLASH_PORT_WIDTH8
+	value = addr[2];			/* device ID        */
+#else
+	value = addr[1];			/* device ID        */
+#endif
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 4 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+				rcode = 1;
+				break;
+			    }
+
+			    /* show that we're waiting */
+			    if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			    }
+			}
+
+			*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+
+	int i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#elif defined(FLASH_PORT_WIDTH32)
+	wp = (addr & ~3);
+	port_width = 4;
+#else
+	wp = addr;
+	port_width = 1;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c
new file mode 100755
index 0000000..081ef65
--- /dev/null
+++ b/board/ids8247/ids8247.c
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 COL */
+	/* PA30 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 CRS */
+	/* PA29 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXER */
+	/* PA28 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXEN */
+	/* PA27 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXDV */
+	/* PA26 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,	 0,   0,   1,	0   }, /* 8247_P0 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PA24 */ {   1,   0,	 0,   0,   1,	1   }, /* I2C_SDA2 */
+	/* PA23 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C_SCL2 */
+#else /* normal I/O port pins */
+	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* PA24 */
+	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* PA23 */
+#endif
+	/* PA22 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DCD */
+	/* PA21 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD1 */
+	/* PA15 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_RTS */
+	/* PA12 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_CTS */
+	/* PA11 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_DTR */
+	/* PA10 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DSR */
+	/* PA9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
+	/* PA8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
+	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
+	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
+	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
+	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
+	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
+	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
+	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
+	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
+	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
+	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
+	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
+	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
+	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
+	/* PC29 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_OUT */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_IN */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
+	/* PC16 */ {   0,   0,	 0,   1,   0,	0   }, /* PC16 */
+	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
+	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDC */
+	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDIO */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
+	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
+	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC3_RX */
+	/* PD24 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_TX */
+	/* PD23 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_RTS */
+	/* PD22 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC4_RXD */
+	/* PD21 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_TXD */
+	/* PD20 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_RTS */
+	/* PD19 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_SEL */
+	/* PD18 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_CLK */
+	/* PD17 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MOSI */
+	/* PD16 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MISO */
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA1 */
+	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL1 */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* PD15 */
+	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* PD14 */
+#endif
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD9 */
+	/* PD8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD8 */
+	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* MII_MDIO */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: IDS 8247\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	psize = try_init (memctl, CFG_PSDMR, CFG_OR2,
+						  (uchar *) CFG_SDRAM_BASE);
+#endif /* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_flashstart = 0xff800000;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong
+nand_probe (ulong physadr);
+
+void
+nand_init (void)
+{
+	ulong totlen = 0;
+
+	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
+	totlen += nand_probe (CFG_NAND0_BASE);
+
+	printf ("%4lu MB\n", totlen >>20);
+}
+
+#endif	/* CFG_CMD_NAND */
diff --git a/board/ids8247/u-boot.lds b/board/ids8247/u-boot.lds
new file mode 100755
index 0000000..788aed3
--- /dev/null
+++ b/board/ids8247/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/impa7/Makefile b/board/impa7/Makefile
new file mode 100755
index 0000000..08543f9
--- /dev/null
+++ b/board/impa7/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= impa7.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/impa7/config.mk b/board/impa7/config.mk
new file mode 100755
index 0000000..417d6a8
--- /dev/null
+++ b/board/impa7/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xc1780000
diff --git a/board/impa7/flash.c b/board/impa7/flash.c
new file mode 100755
index 0000000..ca76fe8
--- /dev/null
+++ b/board/impa7/flash.c
@@ -0,0 +1,357 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x20000
+#define PARAM_SECT_SIZE 0x4000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT & FLASH_VENDMASK) |
+			(INTEL_ID_28F320B3T & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else if (i == 1)
+			flashbase = PHYS_FLASH_2;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j <= 7) {
+				flash_info[i].start[j] =
+					flashbase + j * PARAM_SECT_SIZE;
+			} else {
+				flash_info[i].start[j] =
+					flashbase + (j - 7) * MAIN_SECT_SIZE;
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F320B3T & FLASH_TYPEMASK):
+		printf ("28F320F3B (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+
+			*addr = 0x00200020;	/* erase setup */
+			*addr = 0x00D000D0;	/* erase confirm */
+
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					*addr = 0x00B000B0;	/* suspend erase */
+					*addr = 0x00FF00FF;	/* reset to read mode */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+
+			*addr = 0x00FF00FF;	/* reset to read mode */
+		}
+		printf ("ok.\n");
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong barf;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* clear status register command */
+	*addr = 0x00500050;
+
+	/* program set-up command */
+	*addr = 0x00400040;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* read status register command */
+	*addr = 0x00700070;
+
+	/* wait while polling the status register */
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			/* suspend program command */
+			*addr = 0x00B000B0;
+			goto outahere;
+		}
+
+		if (*addr & 0x003A003A) {	/* check for error */
+			barf = *addr;
+			if (barf & 0x003A0000) {
+				barf >>= 16;
+			} else {
+				barf &= 0x0000003A;
+			}
+			printf ("\nFlash write error %02lx at address %08lx\n", barf, (unsigned long) dest);
+			if (barf & 0x0002) {
+				printf ("Block locked, not erased.\n");
+				rc = ERR_NOT_ERASED;
+				goto outahere;
+			}
+			if (barf & 0x0010) {
+				printf ("Programming error.\n");
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (barf & 0x0008) {
+				printf ("Vpp Low error.\n");
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+	}
+
+
+      outahere:
+	/* read array command */
+	*addr = 0x00FF00FF;
+
+	if (flag)
+		enable_interrupts ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 4;
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 24);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/board/impa7/impa7.c b/board/impa7/impa7.c
new file mode 100755
index 0000000..e496923
--- /dev/null
+++ b/board/impa7/impa7.c
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Activate LED flasher */
+	IO_LEDFLSH = 0x40;
+
+	/* arch number of EP7111 */
+	gd->bd->bi_arch_number = MACH_TYPE_EDB7211;
+
+	/* location of boot parameters for EP7111 */
+	gd->bd->bi_boot_params = 0xc0020100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return (0);
+}
diff --git a/board/impa7/lowlevel_init.S b/board/impa7/lowlevel_init.S
new file mode 100755
index 0000000..7ce10a2
--- /dev/null
+++ b/board/impa7/lowlevel_init.S
@@ -0,0 +1,85 @@
+/*
+ * Memory Setup stuff - taken from ???
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+SYSCON2:	.long	0x80001100
+MEMCFG1:	.long	0x80000180
+MEMCFG2:	.long	0x800001C0
+DRFPR:		.long	0x80000200
+
+syscon2_mask:	.long	0x00000004
+memcfg1_val:	.long	0x160c1414
+memcfg2_mask:	.long	0x0000ffff @ only set lower 16 bits
+memcfg2_val:	.long	0x00000000 @ upper 16 bits are reserved for CS7 + CS6
+drfpr_val:	.long	0x00000081
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+	/*
+	 * DRFPR
+	 * 64kHz DRAM refresh
+	 */
+	ldr	r0, DRFPR
+	ldr	r1, drfpr_val
+	str	r1, [r0]
+
+	/*
+	 * SYSCON2: clear bit 2, DRAM is 32 bits wide
+	 */
+	ldr	r0, SYSCON2
+	ldr	r2, [r0]
+	ldr	r1, syscon2_mask
+	bic	r2, r2, r1
+	str	r2, [r0]
+
+	/*
+	 * MEMCFG1
+	 * Setting up Keyboard at CS3, 8 Bit, 3 Waitstates
+	 * Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates
+	 * Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates
+	 */
+	ldr	r0, MEMCFG1
+	ldr	r1, memcfg1_val
+	str	r1, [r0]
+
+	/*
+	 * MEMCFG2
+	 * Setting up ? with 0
+	 *
+	 */
+	ldr	r0, MEMCFG2
+	ldr	r2, [r0]
+	ldr	r1, memcfg2_mask
+	bic	r2, r2, r1
+	ldr	r1, memcfg2_val
+	orr	r2, r2, r1
+	str	r2, [r0]
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/board/impa7/u-boot.lds b/board/impa7/u-boot.lds
new file mode 100755
index 0000000..1122d75
--- /dev/null
+++ b/board/impa7/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm720t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/incaip/Makefile b/board/incaip/Makefile
new file mode 100755
index 0000000..d9b0e2d
--- /dev/null
+++ b/board/incaip/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= lowlevel_init.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/incaip/config.mk b/board/incaip/config.mk
new file mode 100755
index 0000000..0cecc01
--- /dev/null
+++ b/board/incaip/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# INCA-IP board with MIPS 4Kc CPU core
+#
+
+# ROM version
+TEXT_BASE = 0xB0000000
+
+# RAM version
+#TEXT_BASE = 0x80100000
diff --git a/board/incaip/flash.c b/board/incaip/flash.c
new file mode 100755
index 0000000..520514d
--- /dev/null
+++ b/board/incaip/flash.c
@@ -0,0 +1,671 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/inca-ip.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#if 0
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+#else
+#define FLASH_CYCLE1	0x0554
+#define FLASH_CYCLE2	0x02ab
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
+		ulong * buscon = (ulong *)
+			((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2);
+
+		/* Disable write protection */
+		*buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
+
+#if 1
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+#endif
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+			i, flash_info[i].size);
+		}
+
+		size += flash_info[i].size;
+	}
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = base + (i * sect_size);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base < info->start[0] + info->size)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[1] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) {
+
+	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F800C3B:
+		info->flash_id += FLASH_28F800C3B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F800B3B:
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F160C3B:
+		info->flash_id += FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F160B3B:
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F320C3B:
+		info->flash_id += FLASH_28F320C3B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F320B3B:
+		info->flash_id += FLASH_INTEL320B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F640C3B:
+		info->flash_id += FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F640B3B:
+		info->flash_id += FLASH_INTEL640B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			base[FLASH_CYCLE1] = (FPW)0x00800080;	/* erase mode */
+			base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+			base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		/* show that we're waiting */
+		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+			putc ('.');
+			last = get_timer(0);
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+    int bytes;	  /* number of bytes to program in current word		*/
+    int left;	  /* number of bytes left to program			*/
+    int i, res;
+
+    for (left = cnt, res = 0;
+	 left > 0 && res == 0;
+	 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+	bytes = addr & (sizeof(data) - 1);
+	addr &= ~(sizeof(data) - 1);
+
+	/* combine source and destination data so can program
+	 * an entire word of 16 or 32 bits
+	 */
+	for (i = 0; i < sizeof(data); i++) {
+	    data <<= 8;
+	    if (i < bytes || i - bytes >= left )
+		data += *((uchar *)addr + i);
+	    else
+		data += *src++;
+	}
+
+	/* write one word to the flash */
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		res = write_word_amd(info, (FPWV *)addr, data);
+		break;
+	case FLASH_MAN_INTEL:
+		res = write_word_intel(info, (FPWV *)addr, data);
+		break;
+	default:
+		/* unknown flash type, error! */
+		printf ("missing or unknown FLASH type\n");
+		res = 1;	/* not really a timeout, but gives error */
+		break;
+	}
+    }
+
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+    FPWV *base;		/* first address in flash bank	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+
+    base = (FPWV *)(info->start[0]);
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+    base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+    base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    /* data polling for D7 */
+    while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00F000F0;	/* reset bank */
+	    res = 1;
+	}
+    }
+
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+    *dest = (FPW)0x00400040;	/* program setup		*/
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00B000B0;	/* Suspend program	*/
+	    res = 1;
+	}
+    }
+
+    if (res == 0 && (*dest & (FPW)0x00100010))
+	res = 1;	/* write failed, time out error is close enough	*/
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+    return (res);
+}
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
new file mode 100755
index 0000000..b5d9e00
--- /dev/null
+++ b/board/incaip/incaip.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/addrspace.h>
+#include <asm/inca-ip.h>
+
+
+extern uint incaip_get_cpuclk(void);
+
+static ulong max_sdram_size(void)
+{
+	/* The only supported SDRAM data width is 16bit.
+	 */
+#define CFG_DW	2
+
+	/* The only supported number of SDRAM banks is 4.
+	 */
+#define CFG_NB	4
+
+	ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
+	int   cols   = cfgpb0 & 0xF;
+	int   rows   = (cfgpb0 & 0xF0) >> 4;
+	ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
+
+	return size;
+}
+
+long int initdram(int board_type)
+{
+	int   rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
+	ulong size, max_size       = 0;
+	ulong our_address;
+
+	asm volatile ("move %0, $25" : "=r" (our_address) :);
+
+		/* Can't probe for RAM size unless we are running from Flash.
+		 */
+	if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1))
+	{
+		return max_sdram_size();
+	}
+
+	for (cols = 0x8; cols <= 0xC; cols++)
+	{
+		for (rows = 0xB; rows <= 0xD; rows++)
+		{
+			*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
+			                           (rows << 4) | cols;
+			size = get_ram_size((long *)CFG_SDRAM_BASE,
+			                                     max_sdram_size());
+
+			if (size > max_size)
+			{
+				best_val = *INCA_IP_SDRAM_MC_CFGPB0;
+				max_size = size;
+			}
+		}
+	}
+
+	*INCA_IP_SDRAM_MC_CFGPB0 = best_val;
+	return max_size;
+}
+
+int checkboard (void)
+{
+
+	unsigned long chipid = *INCA_IP_WDT_CHIPID;
+	int part_num;
+
+	puts ("Board: INCA-IP ");
+	part_num = (chipid >> 12) & 0xffff;
+	switch (part_num) {
+	case 0xc0:
+		printf ("Standard Version, ");
+		break;
+	case 0xc1:
+		printf ("Basic Version, ");
+		break;
+	default:
+		printf ("Unknown Part Number 0x%x ", part_num);
+		break;
+	}
+
+	printf ("Chip V1.%ld, ", (chipid >> 28));
+
+	printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
+
+	return 0;
+}
diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S
new file mode 100755
index 0000000..14d738a
--- /dev/null
+++ b/board/incaip/lowlevel_init.S
@@ -0,0 +1,298 @@
+/*
+ *  Memory sub-system initialization code for INCA-IP development board.
+ *
+ *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+
+#define EBU_MODUL_BASE		0xB8000200
+#define EBU_CLC(value)		0x0000(value)
+#define EBU_CON(value)		0x0010(value)
+#define EBU_ADDSEL0(value)	0x0020(value)
+#define EBU_ADDSEL1(value)	0x0024(value)
+#define EBU_ADDSEL2(value)	0x0028(value)
+#define EBU_BUSCON0(value)	0x0060(value)
+#define EBU_BUSCON1(value)	0x0064(value)
+#define EBU_BUSCON2(value)	0x0068(value)
+
+#define MC_MODUL_BASE		0xBF800000
+#define MC_ERRCAUSE(value)	0x0100(value)
+#define MC_ERRADDR(value)	0x0108(value)
+#define MC_IOGP(value)		0x0800(value)
+#define MC_SELFRFSH(value)	0x0A00(value)
+#define MC_CTRLENA(value)	0x1000(value)
+#define MC_MRSCODE(value)	0x1008(value)
+#define MC_CFGDW(value)		0x1010(value)
+#define MC_CFGPB0(value)	0x1018(value)
+#define MC_LATENCY(value)	0x1038(value)
+#define MC_TREFRESH(value)	0x1040(value)
+
+#define CGU_MODUL_BASE		0xBF107000
+#define CGU_PLL1CR(value)	0x0008(value)
+#define CGU_DIVCR(value)	0x0010(value)
+#define CGU_MUXCR(value)	0x0014(value)
+#define CGU_PLL1SR(value)	0x000C(value)
+
+	.set	noreorder
+
+
+/*
+ * void ebu_init(long)
+ *
+ * a0 has the clock value we are going to run at
+ */
+	.globl	ebu_init
+	.ent	ebu_init
+ebu_init:
+__ebu_init:
+
+	li	t1, EBU_MODUL_BASE
+	li	t2, 0xA0000041
+	sw	t2, EBU_ADDSEL0(t1)
+	li	t2, 0xA0800041
+	sw	t2, EBU_ADDSEL2(t1)
+	li	t2, 0xBE0000F1
+	sw	t2, EBU_ADDSEL1(t1)
+
+	li	t3, 100000000
+	beq	a0, t3, 1f
+	nop
+	li	t3, 133000000
+	beq	a0, t3, 2f
+	nop
+	li	t3, 150000000
+	beq	a0, t3, 2f
+	nop
+	b	3f
+	nop
+
+	/* 100 MHz */
+1:
+	li	t2, 0x8841417D
+	sw	t2, EBU_BUSCON0(t1)
+	sw	t2, EBU_BUSCON2(t1)
+	li	t2, 0x684142BD
+	b	3f
+	sw	t2, EBU_BUSCON1(t1)	/* delay slot */
+
+	/* 133 or 150 MHz */
+2:
+	li	t2, 0x8841417E
+	sw	t2, EBU_BUSCON0(t1)
+	sw	t2, EBU_BUSCON2(t1)
+	li	t2, 0x684143FD
+	sw	t2, EBU_BUSCON1(t1)
+3:
+	j	ra
+	nop
+
+	.end	ebu_init
+
+
+/*
+ * void cgu_init(long)
+ *
+ * a0 has the clock value
+ */
+	.globl	cgu_init
+	.ent	cgu_init
+cgu_init:
+__cgu_init:
+
+	li	t1, CGU_MODUL_BASE
+
+	li	t3, 100000000
+	beq	a0, t3, 1f
+	nop
+	li	t3, 133000000
+	beq	a0, t3, 2f
+	nop
+	li	t3, 150000000
+	beq	a0, t3, 3f
+	nop
+	b	5f
+	nop
+
+	/* 100 MHz clock */
+1:
+	li	t2, 0x80000014
+	sw	t2, CGU_DIVCR(t1)
+	li	t2, 0x80000000
+	sw	t2, CGU_MUXCR(t1)
+	li	t2, 0x800B0001
+	b	5f
+	sw	t2, CGU_PLL1CR(t1)	/* delay slot */
+
+	/* 133 MHz clock */
+2:
+	li	t2, 0x80000054
+	sw	t2, CGU_DIVCR(t1)
+	li	t2, 0x80000000
+	sw	t2, CGU_MUXCR(t1)
+	li	t2, 0x800B0001
+	b	5f
+	sw	t2, CGU_PLL1CR(t1)	/* delay slot */
+
+	/* 150 MHz clock */
+3:
+	li	t2, 0x80000017
+	sw	t2, CGU_DIVCR(t1)
+	li	t2, 0xC00B0001
+	sw	t2, CGU_PLL1CR(t1)
+	li	t3, 0x80000000
+4:
+	lw	t2, CGU_PLL1SR(t1)
+	and	t2, t2, t3
+	beq	t2, zero, 4b
+	nop
+	li	t2, 0x80000001
+	sw	t2, CGU_MUXCR(t1)
+5:
+	j	ra
+	nop
+
+	.end	cgu_init
+
+
+/*
+ * void sdram_init(long)
+ *
+ * a0 has the clock value
+ */
+	.globl	sdram_init
+	.ent	sdram_init
+sdram_init:
+__sdram_init:
+
+	li	t1, MC_MODUL_BASE
+
+#if 0
+	/* Disable memory controller before changing any of its registers */
+	sw	zero, MC_CTRLENA(t1)
+#endif
+
+	li	t2, 100000000
+	beq	a0, t2, 1f
+	nop
+	li	t2, 133000000
+	beq	a0, t2, 2f
+	nop
+	li	t2, 150000000
+	beq	a0, t2, 3f
+	nop
+	b	5f
+	nop
+
+	/* 100 MHz clock */
+1:
+	/* Set clock ratio (clkrat=1:1, rddel=3) */
+	li	t2, 0x00000003
+	sw	t2, MC_IOGP(t1)
+
+	/* Set sdram refresh rate (4K/64ms @ 100MHz) */
+	li	t2, 0x0000061A
+	b	4f
+	sw	t2, MC_TREFRESH(t1)
+
+	/* 133 MHz clock */
+2:
+	/* Set clock ratio (clkrat=1:1, rddel=3) */
+	li	t2, 0x00000003
+	sw	t2, MC_IOGP(t1)
+
+	/* Set sdram refresh rate (4K/64ms @ 133MHz) */
+	li	t2, 0x00000822
+	b	4f
+	sw	t2, MC_TREFRESH(t1)
+
+	/* 150 MHz clock */
+3:
+	/* Set clock ratio (clkrat=3:2, rddel=4) */
+	li	t2, 0x00000014
+	sw	t2, MC_IOGP(t1)
+
+	/* Set sdram refresh rate (4K/64ms @ 150MHz) */
+	li	t2, 0x00000927
+	sw	t2, MC_TREFRESH(t1)
+
+4:
+	/* Clear Error log registers */
+	sw	zero, MC_ERRCAUSE(t1)
+	sw	zero, MC_ERRADDR(t1)
+
+	/* Clear Power-down registers */
+	sw	zero, MC_SELFRFSH(t1)
+
+	/* Set CAS Latency */
+	li	t2, 0x00000020		/* CL = 2 */
+	sw	t2, MC_MRSCODE(t1)
+
+	/* Set word width to 16 bit */
+	li	t2, 0x2
+	sw	t2, MC_CFGDW(t1)
+
+	/* Set CS0 to SDRAM parameters */
+	li	t2, 0x000014C9
+	sw	t2, MC_CFGPB0(t1)
+
+	/* Set SDRAM latency parameters */
+	li	t2, 0x00026325		/* BC PC100 */
+	sw	t2, MC_LATENCY(t1)
+
+5:
+	/* Finally enable the controller */
+	li	t2, 0x00000001
+	sw	t2, MC_CTRLENA(t1)
+
+	j	ra
+	nop
+
+	.end	sdram_init
+
+
+	.globl	lowlevel_init
+	.ent	lowlevel_init
+lowlevel_init:
+
+	/* EBU, CGU and SDRAM Initialization.
+	 */
+	li	a0, CPU_CLOCK_RATE
+	move	t0, ra
+
+	/* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
+	 * modify t0 and a0.
+	 */
+	bal	__cgu_init
+	nop
+	bal	__ebu_init
+	nop
+	bal	__sdram_init
+	nop
+	move	ra, t0
+
+	j	ra
+	nop
+
+	.end	lowlevel_init
diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds
new file mode 100755
index 0000000..10c9917
--- /dev/null
+++ b/board/incaip/u-boot.lds
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile
new file mode 100755
index 0000000..bf83292
--- /dev/null
+++ b/board/inka4x0/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/inka4x0/config.mk b/board/inka4x0/config.mk
new file mode 100755
index 0000000..cb19a7d
--- /dev/null
+++ b/board/inka4x0/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# INKA 4X0 board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFE00000   boot low
+#
+#	0x00100000   boot from RAM (for testing only)
+#
+
+ifndef TEXT_BASE
+## Standard: boot low
+TEXT_BASE = 0xFFE00000
+## For testing: boot from RAM
+#TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/inka4x0/flash.c b/board/inka4x0/flash.c
new file mode 100755
index 0000000..b138655
--- /dev/null
+++ b/board/inka4x0/flash.c
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * CPU to flash interface is 8-bit, so make declaration accordingly
+ */
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	extern void flash_preinit(void);
+	ulong flashbase = CFG_FLASH_BASE;
+
+	flash_preinit();
+
+	/* Init: no FLASHes known */
+	memset(&flash_info[0], 0, sizeof(flash_info_t));
+
+	flash_info[0].size =
+		flash_get_size((FPW *)flashbase, &flash_info[0]);
+
+	size = flash_info[0].size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size && info->start[0] <= base &&
+		    base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM116DB:
+		printf ("AM29LV116DB (16Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AMLV128U:
+		printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int i;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		debug ("Manufacturer: AMD (Spansion)\n");
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		debug ("Manufacturer: Intel (not supported yet)\n");
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
+
+	case (uchar)AMD_ID_LV116DB:
+		debug ("Chip: AM29LV116DB\n");
+		info->flash_id += FLASH_AM116DB;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		/*
+		 * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
+		 * the other ones are 64 kB
+		 */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for( i = 4; i < info->sector_count; i++ )
+			info->start[i] =
+				base + (i * (64 << 10)) - 0x00030000;
+		break;          /* => 2 MB */
+
+	case (FPW)AMD_ID_LV160B:
+		debug ("Chip: AM29LV160MB\n");
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		/*
+		 * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
+		 * the other ones are 64 kB
+		 */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for( i = 4; i < info->sector_count; i++ )
+			info->start[i] =
+				base + (i * 2 * (64 << 10)) - 0x00060000;
+		break;		/* => 4 MB */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr = (FPWV*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = (FPW)0x00AA00AA;
+	addr[0x02AA] = (FPW)0x00550055;
+	addr[0x0555] = (FPW)0x00800080;
+	addr[0x0555] = (FPW)0x00AA00AA;
+	addr[0x02AA] = (FPW)0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (FPWV*)(info->start[sect]);
+			addr[0] = (FPW)0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (FPWV*)(info->start[l_sect]);
+	while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (FPWV*)info->start[0];
+	addr[0] = (FPW)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	int i, rc = 0;
+
+	for (i = 0; i < cnt; i++)
+		if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) {
+			return (rc);
+		}
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
new file mode 100755
index 0000000..29878f9
--- /dev/null
+++ b/board/inka4x0/inka4x0.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+/*	return dramsize + dramsize2; */
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: INKA 4X0\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+#define GPIO_WKUP_7	0x80000000UL
+#define GPIO_PSC3_9	0x04000000UL
+
+int misc_init_f (void)
+{
+	uchar tmp[10];
+	int i, br;
+
+	i = getenv_r("brightness", tmp, sizeof(tmp));
+	br = (i > 0)
+		? (int) simple_strtoul (tmp, NULL, 10)
+		: CFG_BRIGHTNESS;
+	if (br > 255)
+		br = 255;
+
+	/* Initialize GPIO output pins.
+	 */
+	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
+	*(vu_long *)MPC5XXX_GPT0_ENABLE =
+	*(vu_long *)MPC5XXX_GPT1_ENABLE =
+	*(vu_long *)MPC5XXX_GPT2_ENABLE =
+	*(vu_long *)MPC5XXX_GPT3_ENABLE =
+	*(vu_long *)MPC5XXX_GPT4_ENABLE =
+	*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
+
+	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
+	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
+	*(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
+	*(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
+	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
+
+	/* Configure PSC3_6,7 as GPIO output */
+	*(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
+	*(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
+
+	/* Configure PSC3_8 as GPIO output, no interrupt */
+	*(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
+	*(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
+	*(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
+
+	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
+	*(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
+	*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
+
+	/* Set LR mirror bit because it is low-active */
+	*(vu_long *)MPC5XXX_WU_GPIO_DATA    |= GPIO_WKUP_7;
+	/*
+	 * Reset Coral-P graphics controller
+	 */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC3_9;
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC3_9;
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h
new file mode 100755
index 0000000..f650faa
--- /dev/null
+++ b/board/inka4x0/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h
new file mode 100755
index 0000000..13a97ac
--- /dev/null
+++ b/board/inka4x0/mt48lc16m16a2-75.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2	0x8AD70000
+/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/inka4x0/u-boot.lds b/board/inka4x0/u-boot.lds
new file mode 100755
index 0000000..123a14c
--- /dev/null
+++ b/board/inka4x0/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the sector layout of our flash chips!    XXX FIXME XXX   */
+
+    cpu/mpc5xxx/start.o          (.text)
+    cpu/mpc5xxx/traps.o          (.text)
+    lib_generic/crc32.o         (.text)
+    lib_ppc/cache.o             (.text)
+    lib_ppc/time.o              (.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o        (.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/innokom/Makefile b/board/innokom/Makefile
new file mode 100755
index 0000000..73f6a74
--- /dev/null
+++ b/board/innokom/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= innokom.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/innokom/config.mk b/board/innokom/config.mk
new file mode 100755
index 0000000..2354392
--- /dev/null
+++ b/board/innokom/config.mk
@@ -0,0 +1,15 @@
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to c170'0000, the upper 1 MB of second bank
+#
+# download areas is c800'0000
+#
+
+# This is the address where U-Boot lives in flash:
+#TEXT_BASE = 0
+
+# FIXME: armboot does only work correctly when being compiled
+# for the addresses _after_ relocation to RAM!! Otherwhise the
+# .bss segment is assumed in flash...
+TEXT_BASE = 0xa1fe0000
diff --git a/board/innokom/flash.c b/board/innokom/flash.c
new file mode 100755
index 0000000..298acc8
--- /dev/null
+++ b/board/innokom/flash.c
@@ -0,0 +1,419 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2002
+ * Auerswald GmbH & Co KG, Germany
+ * Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+/* Debugging macros ------------------------------------------------------  */
+
+#undef FLASH_DEBUG
+
+/* Some debug macros */
+#if (FLASH_DEBUG > 2 )
+#define PRINTK3(args...) printf(args)
+#else
+#define PRINTK3(args...)
+#endif
+
+#if FLASH_DEBUG > 1
+#define PRINTK2(args...) printf(args)
+#else
+#define PRINTK2(args...)
+#endif
+
+#ifdef FLASH_DEBUG
+#define PRINTK(args...) printf(args)
+#else
+#define PRINTK(args...)
+#endif
+
+/* ------------------------------------------------------------------------ */
+
+/* Development system: we have only 16 MB Flash                             */
+#ifdef CONFIG_MTD_INNOKOM_16MB
+#define FLASH_BANK_SIZE 0x01000000	/* 16 MB (during development)       */
+#define MAIN_SECT_SIZE  0x00020000	/* 128k per sector                  */
+#endif
+
+/* Production system: we have 64 MB Flash                                   */
+#ifdef CONFIG_MTD_INNOKOM_64MB
+#define FLASH_BANK_SIZE 0x04000000	/* 64 MB                            */
+#define MAIN_SECT_SIZE  0x00020000	/* 128k per sector                  */
+#endif
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+/**
+ * flash_init: - initialize data structures for flash chips
+ *
+ * @return: size of the flash
+ */
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		flash_info[i].flash_id =
+	  		(INTEL_MANUFACT & FLASH_VENDMASK) |
+	  		(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+
+		switch (i) {
+			case 0:
+				flashbase = PHYS_FLASH_1;
+				break;
+			default:
+				panic("configured too many flash banks!\n");
+				break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect u-boot sectors */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + (256*1024) - 1,
+			&flash_info[0]);
+
+#ifdef CFG_ENV_IS_IN_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	return size;
+}
+
+
+/**
+ * flash_print_info: - print information about the flash situation
+ *
+ * @param info:
+ */
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i, j;
+
+	for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {
+
+		switch (info->flash_id & FLASH_VENDMASK) {
+
+			case (INTEL_MANUFACT & FLASH_VENDMASK):
+				printf("Intel: ");
+				break;
+			default:
+				printf("Unknown Vendor ");
+				break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+
+			case (INTEL_ID_28F128J3 & FLASH_TYPEMASK):
+				printf("28F128J3 (128Mbit)\n");
+				break;
+			default:
+				printf("Unknown Chip Type\n");
+				return;
+		}
+
+		printf("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+		printf("  Sector Start Addresses:");
+		for (i = 0; i < info->sector_count; i++) {
+			if ((i % 5) == 0) printf ("\n   ");
+
+			printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+		}
+		printf ("\n");
+		info++;
+	}
+}
+
+
+/**
+ * flash_erase: - erase flash sectors
+ *
+ */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
+		return ERR_UNKNOWN_FLASH_VENDOR;
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) prot++;
+	}
+
+	if (prot) return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+
+		printf("Erasing sector %2d ... ", sect);
+
+		PRINTK("\n");
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			u16 * volatile addr = (u16 * volatile)(info->start[sect]);
+
+			PRINTK("unlocking sector\n");
+			*addr = 0x0060;
+			*addr = 0x00d0;
+			*addr = 0x00ff;
+
+			PRINTK("erasing sector\n");
+			*addr = 0x0020;
+			PRINTK("confirming erase\n");
+			*addr = 0x00D0;
+
+			while ((*addr & 0x0080) != 0x0080) {
+				PRINTK(".");
+				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+					*addr = 0x00B0; /* suspend erase*/
+					*addr = 0x00FF; /* read mode    */
+					rc = ERR_TIMOUT;
+					goto outahere;
+				}
+			}
+
+			PRINTK("clearing status register\n");
+			*addr = 0x0050;
+			PRINTK("resetting to read mode");
+			*addr = 0x00FF;
+		}
+
+		printf("ok.\n");
+	}
+
+	if (ctrlc()) printf("User Interrupt!\n");
+
+	outahere:
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked(10000);
+
+	if (flag) enable_interrupts();
+
+	return rc;
+}
+
+
+/**
+ * write_word: - copy memory to flash
+ *
+ * @param info:
+ * @param dest:
+ * @param data:
+ * @return:
+ */
+
+static int write_word (flash_info_t *info, ulong dest, ushort data)
+{
+	volatile u16 *addr = (u16 *)dest, val;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts();
+
+	/* clear status register command */
+	*addr = 0x50;
+
+	/* program set-up command */
+	*addr = 0x40;
+
+	/* latch address/data */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	/* wait while polling the status register */
+	while(((val = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+			rc = ERR_TIMOUT;
+			*addr = 0xB0; /* suspend program command */
+			goto outahere;
+		}
+	}
+
+	if(val & 0x1A) {	/* check for error */
+		printf("\nFlash write error %02x at address %08lx\n",
+			(int)val, (unsigned long)dest);
+		if(val & (1<<3)) {
+			printf("Voltage range error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		if(val & (1<<1)) {
+			printf("Device protect error.\n");
+			rc = ERR_PROTECTED;
+			goto outahere;
+		}
+		if(val & (1<<4)) {
+			printf("Programming error.\n");
+			rc = ERR_PROG_ERROR;
+			goto outahere;
+		}
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	}
+
+	outahere:
+
+	*addr = 0xFF; /* read array command */
+	if (flag) enable_interrupts();
+
+	return rc;
+}
+
+
+/**
+ * write_buf: - Copy memory to flash.
+ *
+ * @param info:
+ * @param src:	source of copy transaction
+ * @param addr:	where to copy to
+ * @param cnt: 	number of bytes to copy
+ *
+ * @return	error code
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 8);
+		}
+		for (; i<2 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 8);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		/* data = *((vushort*)src); */
+		data = *((ushort*)src);
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp  += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 8);
+	}
+
+	return write_word(info, wp, data);
+}
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
new file mode 100755
index 0000000..ae5402e
--- /dev/null
+++ b/board/innokom/innokom.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de
+ * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net
+ * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/mach-types.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+/**
+ * i2c_init_board - reset i2c bus. When the board is powercycled during a
+ * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
+ * The Innokom board has GPIO70 connected to SCLK which can be toggled
+ * until all chips think that their current cycles are finished.
+ */
+int i2c_init_board(void)
+{
+	int i, icr;
+
+	/* disable I2C controller first, otherwhise it thinks we want to    */
+	/* talk to the slave port...                                        */
+	icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE);
+
+	/* set gpio pin low _before_ we change direction to output          */
+	GPCR(70) = GPIO_bit(70);
+
+	/* now toggle between output=low and high-impedance                 */
+	for (i = 0; i < 20; i++) {
+		GPDR(70) |= GPIO_bit(70);  /* output */
+		udelay(10);
+		GPDR(70) &= ~GPIO_bit(70); /* input  */
+		udelay(10);
+	}
+
+	ICR = icr;
+
+	return 0;
+}
+
+
+/**
+ * misc_init_r: - misc initialisation routines
+ */
+
+int misc_init_r(void)
+{
+	uchar *str;
+
+	/* determine if the software update key is pressed during startup   */
+	if (GPLR0 & 0x00000800) {
+		printf("using bootcmd_normal (sw-update button not pressed)\n");
+		str = getenv("bootcmd_normal");
+	} else {
+		printf("using bootcmd_update (sw-update button pressed)\n");
+		str = getenv("bootcmd_update");
+	}
+
+	setenv("bootcmd",str);
+
+	return 0;
+}
+
+
+/**
+ * board_init: - setup some data structures
+ *
+ * @return: 0 in case of success
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	gd->bd->bi_arch_number = MACH_TYPE_INNOKOM;
+	gd->bd->bi_boot_params = 0xa0000100;
+	gd->bd->bi_baudrate = CONFIG_BAUDRATE;
+
+	return 0;
+}
+
+
+/**
+ * dram_init: - setup dynamic RAM
+ *
+ * @return: 0 in case of success
+ */
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+
+/**
+ * innokom_set_led: - switch LEDs on or off
+ *
+ * @param led:   LED to switch (0,1,2)
+ * @param state: switch on (1) or off (0)
+ */
+
+void innokom_set_led(int led, int state)
+{
+	switch(led) {
+/*
+		case 0: if (state==1) {
+				GPCR0 |= CSB226_USER_LED0;
+			} else if (state==0) {
+				GPSR0 |= CSB226_USER_LED0;
+			}
+			break;
+
+		case 1: if (state==1) {
+				GPCR0 |= CSB226_USER_LED1;
+			} else if (state==0) {
+				GPSR0 |= CSB226_USER_LED1;
+			}
+			break;
+
+		case 2: if (state==1) {
+				GPCR0 |= CSB226_USER_LED2;
+			} else if (state==0) {
+				GPSR0 |= CSB226_USER_LED2;
+			}
+			break;
+*/
+	}
+
+	return;
+}
+
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ * The CSB226 does only have 3 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
+ */
+
+void show_boot_progress (int status)
+{
+	switch(status) {
+/*
+		case  1: csb226_set_led(0,1); break;
+		case  5: csb226_set_led(1,1); break;
+		case 15: csb226_set_led(2,1); break;
+*/
+	}
+
+	return;
+}
diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S
new file mode 100755
index 0000000..aa9dcba
--- /dev/null
+++ b/board/innokom/lowlevel_init.S
@@ -0,0 +1,437 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc  p15,0,\reg,c2,c0,0
+   mov  \reg,\reg
+   sub  pc,pc,#4
+   .endm
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+
+/*
+ * 	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+    mov      r10, lr
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr	r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
+/*	ldr	r2,	=CFG_MSC1_VAL	/  high - bank 3 Ethernet Controller */
+/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
+/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
+/* */
+/*	ldr	r1,	=LED_BLANK */
+/*	mov	r0,	#0xFF */
+/*	str	r0,	[r1]		/  turn on hex leds */
+/* */
+/*loop: */
+/* */
+/*   ldr	r0, =0xB0070001 */
+/*   ldr    	r1, =_LED */
+/*   str    	r0, [r1]		/  hex display */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr     r2,   =CFG_MSC0_VAL
+	str     r2,   [r1, #MSC0_OFFSET]
+	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */
+	/* MSC1: nCS(2,3)                                                   */
+	ldr     r2,  =CFG_MSC1_VAL
+	str     r2,  [r1, #MSC1_OFFSET]
+	ldr     r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr     r2,  =CFG_MSC2_VAL
+	str     r2,  [r1, #MSC2_OFFSET]
+	ldr     r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr     r2,  =CFG_MECR_VAL
+	str     r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr     r2,  =CFG_MCMEM0_VAL
+	str     r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr     r2,  =CFG_MCMEM1_VAL
+	str     r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr     r2,  =CFG_MCATT0_VAL
+	str     r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr     r2,  =CFG_MCATT1_VAL
+	str     r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr     r2,  =CFG_MCIO0_VAL
+	str     r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr     r2,  =CFG_MCIO1_VAL
+	str     r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
+	adr	r3, mem_init		/* r0 <- current position of code   */
+	ldr	r2, =mem_init
+	cmp	r3, r2			/* skip init if in place            */
+	beq	initirqs
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DRI field.                           */
+
+	ldr 	r3, 	=CFG_MDREFR_VAL
+	ldr	r2,	=0xFFF
+	and	r3,	r3, r2
+	ldr	r4,	=0x03ca4000
+	orr	r4,	r4,  r3
+
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr     r4,	[r1, #MDREFR_OFFSET]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	/* Step 4a: assert MDREFR:K?RUN and configure                       */
+	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
+
+	ldr	r4,	=CFG_MDREFR_VAL
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr	r4,	[r1, #MDREFR_OFFSET]
+
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
+
+	bic	r4,	r4, #(MDREFR_SLFRSH)
+
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,     [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
+
+	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
+
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,     [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+
+	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+	ldr     r4,     [r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	/*          There should 9 writes, since the first write doesn't    */
+	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
+	/*          PXA210 Processors Specification Update,                 */
+	/*          Jan 2003, Errata #116, page 30.                         */
+
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
+
+	ldr	r3, [r1, #MDCNFG_OFFSET]
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	str	r3, [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2,  =CFG_MDMRS_VAL
+	str     r2,  [r1, #MDMRS_OFFSET]
+
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2,  =ICLR
+	str     r1,  [r2]
+
+	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
+	str     r1,  [r2]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+	/* (hard-coding at 398.12MHz for now).                              */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+	ldr     r1,  =CKEN
+	mov     r2,  #0
+	str     r2,  [r1]
+
+
+	/* default value in case no valid rotary switch setting is found    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1,  =CCCR
+	str     r2,  [r1]
+
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+/*
+	ldr     r1,  =OSCC
+	mov     r2,  #OSCC_OON
+	str     r2,  [r1]
+*/
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size                                                  */
+	ldr	r1, =DRAM_SIZE
+	str	r8, [r1]
+
+	/* Interrupt init: Mask all interrupts                              */
+	ldr	r0, =ICMR			/* enable no sources        */
+	mov	r1, #0
+	str	r1, [r0]
+
+	/* FIXME */
+
+#ifndef DEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init                                                     */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+    mov     pc, lr
diff --git a/board/innokom/u-boot.lds b/board/innokom/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/innokom/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/integratorap/Makefile b/board/integratorap/Makefile
new file mode 100755
index 0000000..358df62
--- /dev/null
+++ b/board/integratorap/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# ARM Ltd.
+# Philippe Robin, <philippe.robin@arm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= integratorap.o flash.o
+SOBJS	:= lowlevel_init.o memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/integratorap/config.mk b/board/integratorap/config.mk
new file mode 100755
index 0000000..25b79b3
--- /dev/null
+++ b/board/integratorap/config.mk
@@ -0,0 +1,5 @@
+#
+# image should be loaded at 0x01000000
+#
+
+TEXT_BASE = 0x01000000
diff --git a/board/integratorap/flash.c b/board/integratorap/flash.c
new file mode 100755
index 0000000..b120d63
--- /dev/null
+++ b/board/integratorap/flash.c
@@ -0,0 +1,473 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c
new file mode 100755
index 0000000..d4f61d6
--- /dev/null
+++ b/board/integratorap/integratorap.c
@@ -0,0 +1,651 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of Integrator Board */
+	gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	gd->flags = 0;
+
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+	cm_remap();	/* remaps writeable memory to 0x00000000 */
+#endif
+
+	icache_enable ();
+
+	flash__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PCI
+	pci_init();
+#endif
+	setenv("verify", "n");
+	return (0);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifdef CONFIG_PCI
+
+#ifndef CONFIG_PCI_PNP
+
+static struct pci_config_table pci_integrator_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+/* V3 access routines */
+#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
+#define _V3Read16(o)	(*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
+
+#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
+#define _V3Read32(o)	(*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
+
+/* Compute address necessary to access PCI config space for the given */
+/* bus and device. */
+#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({				\
+	unsigned int __address, __devicebit;						\
+	unsigned short __mapaddress;							\
+	unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */		\
+											\
+	if (__bus == 0) {								\
+		/* local bus segment so need a type 0 config cycle */			\
+		/* build the PCI configuration "address" with one-hot in A31-A11 */	\
+		__address = PCI_CONFIG_BASE;						\
+		__address |= ((__devfn & 0x07) << 8);					\
+		__address |= __offset & 0xFF;						\
+		__mapaddress = 0x000A;	/* 101=>config cycle, 0=>A1=A0=0 */		\
+		__devicebit = (1 << (__dev + 11));					\
+											\
+		if ((__devicebit & 0xFF000000) != 0) {					\
+			/* high order bits are handled by the MAP register */		\
+			__mapaddress |= (__devicebit >> 16);				\
+		} else {								\
+			/* low order bits handled directly in the address */		\
+			__address |= __devicebit;					\
+		}									\
+	} else {		/* bus !=0 */						\
+		/* not the local bus segment so need a type 1 config cycle */		\
+		/* A31-A24 are don't care (so clear to 0) */				\
+		__mapaddress = 0x000B;	/* 101=>config cycle, 1=>A1&A0 from PCI_CFG */	\
+		__address = PCI_CONFIG_BASE;						\
+		__address |= ((__bus & 0xFF) << 16);	/* bits 23..16 = bus number	*/  \
+		__address |= ((__dev & 0x1F) << 11);	/* bits 15..11 = device number	*/  \
+		__address |= ((__devfn & 0x07) << 8);	/* bits 10..8  = function number */ \
+		__address |= __offset & 0xFF;	/* bits	 7..0  = register number */	\
+	}										\
+	_V3Write16 (V3_LB_MAP1, __mapaddress);						\
+	__address;									\
+})
+
+/* _V3OpenConfigWindow - open V3 configuration window */
+#define _V3OpenConfigWindow() {								\
+	/* Set up base0 to see all 512Mbytes of memory space (not	     */		\
+	/* prefetchable), this frees up base1 for re-use by configuration*/		\
+	/* memory */									\
+											\
+	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
+				     0x90 | V3_LB_BASE_M_ENABLE));			\
+	/* Set up base1 to point into configuration space, note that MAP1 */		\
+	/* register is set up by pciMakeConfigAddress(). */				\
+											\
+	_V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) |			\
+				     0x40 | V3_LB_BASE_M_ENABLE));			\
+}
+
+/* _V3CloseConfigWindow - close V3 configuration window */
+#define _V3CloseConfigWindow() {							\
+    /* Reassign base1 for use by prefetchable PCI memory */				\
+	_V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000)	\
+					| 0x84 | V3_LB_BASE_M_ENABLE));			\
+	_V3Write16 (V3_LB_MAP1,								\
+	    (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006);	\
+											\
+	/* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */	\
+											\
+	_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) |			\
+			     0x80 | V3_LB_BASE_M_ENABLE));				\
+}
+
+static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev,
+				     int offset, unsigned char *val)
+{
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							       PCI_FUNC (dev),
+							       offset);
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_read__word (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned short *val)
+{
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+								PCI_FUNC (dev),
+								offset);
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_read_dword (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned int *val)
+{
+	_V3OpenConfigWindow ();
+	*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+								PCI_FUNC (dev),
+								offset);
+	*val |= (*(volatile unsigned int *)
+		 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev),
+				     (offset + 2))) << 16;
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_write_byte (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned char val)
+{
+	_V3OpenConfigWindow ();
+	*(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							PCI_FUNC (dev),
+							offset) = val;
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_write_word (struct pci_controller *hose,
+				      pci_dev_t dev, int offset,
+				      unsigned short val)
+{
+	_V3OpenConfigWindow ();
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 offset) = val;
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+
+static int pci_integrator_write_dword (struct pci_controller *hose,
+				       pci_dev_t dev, int offset,
+				       unsigned int val)
+{
+	_V3OpenConfigWindow ();
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 offset) = (val & 0xFFFF);
+	*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
+							 PCI_FUNC (dev),
+							 (offset + 2)) = ((val >> 16) & 0xFFFF);
+	_V3CloseConfigWindow ();
+
+	return 0;
+}
+/******************************
+ * PCI initialisation
+ ******************************/
+
+struct pci_controller integrator_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_integrator_config_table,
+#endif
+};
+
+void pci_init_board (void)
+{
+	volatile int i, j;
+	struct pci_controller *hose = &integrator_hose;
+
+	/* setting this register will take the V3 out of reset */
+
+	*(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1;
+
+	/* wait a few usecs to settle the device and the PCI bus */
+
+	for (i = 0; i < 100; i++)
+		j = i + 1;
+
+	/* Now write the Base I/O Address Word to V3_BASE + 0x6C */
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) =
+		(unsigned short) (V3_BASE >> 16);
+
+	do {
+		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA;
+		*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) =
+			0x55;
+	} while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA
+		 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA +
+						 4) != 0x55);
+
+	/* Make sure that V3 register access is not locked, if it is, unlock it */
+
+	if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &
+	     V3_SYSTEM_M_LOCK)
+	    == V3_SYSTEM_M_LOCK)
+		*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F;
+
+	/* Ensure that the slave accesses from PCI are disabled while we */
+	/* setup windows */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &=
+		~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
+
+	/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
+
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &=
+		~V3_SYSTEM_M_RST_OUT;
+
+	/* Make all accesses from PCI space retry until we're ready for them */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |=
+		V3_PCI_CFG_M_RETRY_EN;
+
+	/* Set up any V3 PCI Configuration Registers that we absolutely have to */
+	/* LB_CFG controls Local Bus protocol. */
+	/* Enable LocalBus byte strobes for READ accesses too. */
+	/* set bit 7 BE_IMODE and bit 6 BE_OMODE */
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0;
+
+	/* PCI_CMD controls overall PCI operation. */
+	/* Enable PCI bus master. */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04;
+
+	/* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */
+
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) =
+		(INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M |
+					      V3_PCI_MAP_M_REG_EN |
+					      V3_PCI_MAP_M_ENABLE);
+
+	/* PCI_BASE0 is the PCI address of the start of the window */
+
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) =
+		INTEGRATOR_BOOT_ROM_BASE;
+
+	/* PCI_MAP1 is LOCAL address of the start of the window */
+
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) =
+		(INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M |
+						V3_PCI_MAP_M_REG_EN |
+						V3_PCI_MAP_M_ENABLE);
+
+	/* PCI_BASE1 is the PCI address of the start of the window */
+
+	*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) =
+		INTEGRATOR_HDR0_SDRAM_BASE;
+
+	/* Set up the windows from local bus memory into PCI configuration, */
+	/* I/O and Memory. */
+	/* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) =
+		((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0;
+
+	/* PCI Configuration, use LB_BASE1/LB_MAP1. */
+
+	/* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
+	/* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
+	/* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
+
+	*(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) =
+		INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) =
+		((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
+
+	/* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
+
+	*(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) =
+		INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
+
+	*(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) =
+		(((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
+
+	/* Allow accesses to PCI Configuration space */
+	/* and set up A1, A0 for type 1 config cycles */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) =
+		((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) &
+		 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) |
+		V3_PCI_CFG_M_AD_LOW0;
+
+	/* now we can allow in PCI MEMORY accesses */
+
+	*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) =
+		(*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) |
+		V3_COMMAND_M_MEM_EN;
+
+	/* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
+	/* initialise and lock the V3 system register so that no one else */
+	/* can play with it */
+
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
+		V3_SYSTEM_M_RST_OUT;
+
+	*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
+		(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
+		V3_SYSTEM_M_LOCK;
+
+	/*
+	 * Register the hose
+	 */
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* System memory space */
+	pci_set_region (hose->regions + 0,
+			0x00000000, 0x40000000, 0x01000000,
+			PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	/* PCI Memory - config space */
+	pci_set_region (hose->regions + 1,
+			0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM);
+
+	/* PCI V3 regs */
+	pci_set_region (hose->regions + 2,
+			0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM);
+
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 3,
+			0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO);
+
+	pci_set_ops (hose,
+		     pci_integrator_read_byte,
+		     pci_integrator_read__word,
+		     pci_integrator_read_dword,
+		     pci_integrator_write_byte,
+		     pci_integrator_write_word, pci_integrator_write_dword);
+
+	hose->region_count = 4;
+
+	pci_register_hose (hose);
+
+	pciauto_config_init (hose);
+	pciauto_config_device (hose, 0);
+
+	hose->last_busno = pci_hose_scan (hose);
+}
+#endif
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size	 = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_CM_SPD_DETECT
+	{
+extern void dram_query(void);
+	unsigned long cm_reg_sdram;
+	unsigned long sdram_shift;
+
+	dram_query();	/* Assembler accesses to CM registers */
+			/* Queries the SPD values	      */
+
+	/* Obtain the SDRAM size from the CM SDRAM register */
+
+	cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+	/*   Register	      SDRAM size
+	 *
+	 *   0xXXXXXXbbb000bb	 16 MB
+	 *   0xXXXXXXbbb001bb	 32 MB
+	 *   0xXXXXXXbbb010bb	 64 MB
+	 *   0xXXXXXXbbb011bb	128 MB
+	 *   0xXXXXXXbbb100bb	256 MB
+	 *
+	 */
+	sdram_shift		 = ((cm_reg_sdram & 0x0000001C)/4)%4;
+	gd->bd->bi_dram[0].size	 = 0x01000000 << sdram_shift;
+
+	}
+#endif /* CM_SPD_DETECT */
+
+	return 0;
+}
+
+/* The Integrator/AP timer1 is clocked at 24MHz
+ * can be divided by 16 or 256
+ * and is a 16-bit counter
+ */
+/* U-Boot expects a 32 bit timer running at CFG_HZ*/
+static ulong timestamp;		/* U-Boot ticks since startup	      */
+static ulong total_count = 0;	/* Total timer count		      */
+static ulong lastdec;		/* Timer reading at last call	      */
+static ulong div_clock	 = 256; /* Divisor applied to the timer clock */
+static ulong div_timer	 = 1;	/* Divisor to convert timer reading
+				 * change to U-Boot ticks
+				 */
+/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
+
+#define TIMER_LOAD_VAL 0x0000FFFFL
+#define READ_TIMER ((*(volatile ulong *)(CFG_TIMERBASE+4)) & 0x0000FFFFL)
+
+/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec
+ *  - unless otherwise stated
+ */
+
+/* starts a counter
+ * - the Integrator/AP timer issues an interrupt
+ *   each time it reaches zero
+ */
+int interrupt_init (void)
+{
+	/* Load timer with initial value */
+	*(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
+	/* Set timer to be
+	 *	enabled		  1
+	 *	free-running	  0
+	 *	XX		 00
+	 *	divider 256	 10
+	 *	XX		 00
+	 */
+	*(volatile ulong *)(CFG_TIMERBASE + 8) = 0x00000088;
+	total_count = 0;
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	div_timer  = CFG_HZ_CLOCK / CFG_HZ;
+	div_timer /= div_clock;
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base_ticks)
+{
+	return get_timer_masked () - base_ticks;
+}
+
+void set_timer (ulong ticks)
+{
+	timestamp = ticks;
+	total_count = ticks * div_timer;
+	reset_timer_masked();
+}
+
+/* delay x useconds */
+void udelay (unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	/* Convert to U-Boot ticks */
+	tmo  = usec * CFG_HZ;
+	tmo /= (1000000L);
+
+	tmp  = get_timer_masked();	/* get current timestamp */
+	tmo += tmp;			/* wake up timestamp	 */
+
+	while (get_timer_masked () < tmo) { /* loop till event */
+		/*NOP*/;
+	}
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec	  = READ_TIMER; /* capture current decrementer value   */
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+}
+
+/* converts the timer reading to U-Boot ticks	       */
+/* the timestamp is the number of ticks since reset    */
+/* This routine does not detect wraps unless called regularly
+   ASSUMES a call at least every 16 seconds to detect every reload */
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;		/* current count */
+
+	if (now > lastdec) {
+		/* Must have wrapped */
+		total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
+	} else {
+		total_count += lastdec - now;
+	}
+	lastdec	  = now;
+	timestamp = total_count/div_timer;
+
+	return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+	udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * Return the timebase clock frequency
+ * i.e. how often the timer decrements
+ */
+ulong get_tbclk (void)
+{
+	return CFG_HZ_CLOCK/div_clock;
+}
diff --git a/board/integratorap/lowlevel_init.S b/board/integratorap/lowlevel_init.S
new file mode 100755
index 0000000..ab9589c
--- /dev/null
+++ b/board/integratorap/lowlevel_init.S
@@ -0,0 +1,213 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+	/* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+	mov	r0, #CM_BASE
+	ldr	r1,[r0,#OS_CTRL]
+	orr	r1,r1,#CMMASK_RESET
+	str	r1,[r0,#OS_CTRL]
+
+reset_failed:
+	b	reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+	/* If U-Boot has been run after the ARM boot monitor
+	 * then all the necessary actions have been done
+	 * otherwise we are running from user flash mapped to 0x00000000
+	 * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+	 * Changes to the (possibly soft) reset defaults of the processor
+	 * itself should be performed in cpu/arm<>/start.S
+	 * This function affects only the core module or board settings
+	 */
+
+#ifdef CONFIG_CM_INIT
+	/* CM has an initialization register
+	 * - bits in it are wired into test-chip pins to force
+	 *   reset defaults
+	 * - may need to change its contents for U-Boot
+	 */
+
+	/* set the desired CM specific value */
+	mov	r2,#CMMASK_LOWVEC	/* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+	orr	r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+     !defined (CONFIG_CM940T)
+
+#ifdef	CONFIG_CM_MULTIPLE_SSRAM
+	/* set simple mapping			*/
+	and	r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM	*/
+
+#ifdef	CONFIG_CM_TCRAM
+	/* disable TCRAM			*/
+	and	r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM		*/
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+     defined (CONFIG_CM1136JF_S)
+
+	and	r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+	orr	r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+	/* read CM_INIT		 */
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_INIT]
+	/* check against desired bit setting */
+	and	r3,r1,r2
+	cmp	r3,r2
+	beq	init_reg_OK
+
+	/* lock for change */
+	mov	r3, #CMVAL_LOCK1
+	add	r3,r3,#CMVAL_LOCK2
+	str	r3, [r0, #OS_LOCK]
+	/* set desired value */
+	orr	r1,r1,r2
+	/* write & relock CM_INIT */
+	str	r1, [r0, #OS_INIT]
+	mov	r1, #CMVAL_UNLOCK
+	str	r1, [r0, #OS_LOCK]
+
+	/* soft reset so new values used */
+	b	reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+	mov	pc, lr
+
+#ifdef	CONFIG_CM_SPD_DETECT
+	/* Fast memory is available for the DRAM data
+	 * - ensure it has been transferred, then summarize the data
+	 *   into a CM register
+	 */
+.globl dram_query
+dram_query:
+	stmfd	r13!,{r4-r6,lr}
+	/* set up SDRAM info					*/
+	/* - based on example code from the CM User Guide */
+	mov	r0, #CM_BASE
+
+readspdbit:
+	ldr	r1, [r0, #OS_SDRAM]	/* read the SDRAM register	*/
+	and	r1, r1, #0x20		/* mask SPD bit (5)		*/
+	cmp	r1, #0x20		/* test if set			*/
+	bne	readspdbit
+
+setupsdram:
+	add	r0, r0, #OS_SPD		/* address the copy of the SDP data	*/
+	ldrb	r1, [r0, #3]		/* number of row address lines		*/
+	ldrb	r2, [r0, #4]		/* number of column address lines	*/
+	ldrb	r3, [r0, #5]		/* number of banks			*/
+	ldrb	r4, [r0, #31]		/* module bank density			*/
+	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)	*/
+	mov	r5, r5, ASL#2		/* size in MB				*/
+	mov	r0, #CM_BASE		/* reload for later code		*/
+	cmp	r5, #0x10		/* is it 16MB?				*/
+	bne	not16
+	mov	r6, #0x2		/* store size and CAS latency of 2	*/
+	b	writesize
+
+not16:
+	cmp	r5, #0x20		/* is it  32MB? */
+	bne	not32
+	mov	r6, #0x6
+	b	writesize
+
+not32:
+	cmp	r5, #0x40		/* is it  64MB? */
+	bne	not64
+	mov	r6, #0xa
+	b	writesize
+
+not64:
+	cmp	r5, #0x80		/* is it 128MB? */
+	bne	not128
+	mov	r6, #0xe
+	b	writesize
+
+not128:
+	/* if it is none of these sizes then it is either 256MB, or
+	 * there is no SDRAM fitted so default to 256MB
+	 */
+	mov	r6, #0x12
+
+writesize:
+	mov	r1, r1, ASL#8		/* row addr lines from SDRAM reg */
+	orr	r2, r1, r2, ASL#12	/* OR in column address lines	 */
+	orr	r3, r2, r3, ASL#16	/* OR in number of banks	 */
+	orr	r6, r6, r3		/* OR in size and CAS latency	 */
+	str	r6, [r0, #OS_SDRAM]	/* store SDRAM parameters	 */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+	ldmfd	r13!,{r4-r6,pc}			/* back to caller */
+
+#ifdef	CONFIG_CM_REMAP
+	/* CM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 */
+.globl cm_remap
+cm_remap:
+	stmfd	r13!,{r4-r10,lr}
+
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_CTRL]
+	orr	r1, r1, #CMMASK_REMAP	/* set remap and led bits */
+	str	r1, [r0, #OS_CTRL]
+
+	/* Now 0x00000000 is writeable, replace the vectors	*/
+	ldr	r0, =_start	/* r0 <- start of vectors	*/
+	ldr	r2, =_armboot_start	/* r2 <- past vectors	*/
+	sub	r1,r1,r1		/* destination 0x00000000	*/
+
+copy_vec:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]	*/
+	stmia	r1!, {r3-r10}		/* copy to	 target address [r1]	*/
+	cmp	r0, r2			/* until source end address [r2]	*/
+	ble	copy_vec
+
+	ldmfd	r13!,{r4-r10,pc}	/* back to caller			*/
+
+#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/board/integratorap/memsetup.S b/board/integratorap/memsetup.S
new file mode 100755
index 0000000..dfdc784
--- /dev/null
+++ b/board/integratorap/memsetup.S
@@ -0,0 +1,29 @@
+/*
+ * Memory setup for integratorAP
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * 	Memory setup
+ *      - the reset defaults are assumed sufficient
+ */
+
+.globl memsetup
+memsetup:
+	mov	pc,lr
diff --git a/board/integratorap/split_by_variant.sh b/board/integratorap/split_by_variant.sh
new file mode 100755
index 0000000..9f71bab
--- /dev/null
+++ b/board/integratorap/split_by_variant.sh
@@ -0,0 +1,116 @@
+#!/bin/sh
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n	"/* Integrator configuration implied "	 > tmp.fil
+echo	" by Makefile target */"	 	>> tmp.fil
+echo -n	"#define CONFIG_INTEGRATOR"		>> tmp.fil
+echo	" /* Integrator board */"		>> tmp.fil
+echo -n	"#define CONFIG_ARCH_INTEGRATOR"	>> tmp.fil
+echo	" 1 /* Integrator/AP	 */"		>> tmp.fil
+# ---------------------------------------------------------
+#	Set the core module defines according to Core Module
+# ---------------------------------------------------------
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$1" == "" ]
+then
+	echo "$0:: No parameters - using arm_intcm"
+else
+	case "$1" in
+	ap7_config)
+	cpu="arm_intcm"
+	variant="unported core module CM7TDMI"
+	;;
+
+	ap966)
+	cpu="arm_intcm"
+	variant="unported core module CM966E-S"
+	;;
+
+	ap922_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T"
+	;;
+
+	integratorap_config	|	\
+	ap_config)
+	cpu="arm_intcm"
+	variant="unspecified core module"
+	;;
+
+	ap720t_config)
+	cpu="arm720t"
+	echo -n	"#define CONFIG_CM720T"		>> tmp.fil
+	echo	" 1 /* CPU core is ARM720T */ "	>> tmp.fil
+	variant="Core module CM720T"
+	;;
+
+	ap922_XA10_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T_XA10"
+	echo -n	"#define CONFIG_CM922T_XA10" 		>> tmp.fil
+	echo	" 1 /* CPU core is ARM922T_XA10 */" 	>> tmp.fil
+	;;
+
+	ap920t_config)
+	cpu="arm920t"
+	variant="Core module CM920T"
+	echo -n	"#define CONFIG_CM920T" 		>> tmp.fil
+	echo	" 1 /* CPU core is ARM920T */"		>> tmp.fil
+	;;
+
+	ap926ejs_config)
+	cpu="arm926ejs"
+	variant="Core module CM926EJ-S"
+	echo -n	"#define CONFIG_CM926EJ_S"		>> tmp.fil
+	echo	" 1 /* CPU core is ARM926EJ-S */ "	>> tmp.fil
+	;;
+
+	ap946es_config)
+	cpu="arm946es"
+	variant="Core module CM946E-S"
+	echo -n	"#define CONFIG_CM946E_S"		>> tmp.fil
+	echo	" 1 /* CPU core is ARM946E-S */ "	>> tmp.fil
+	;;
+
+	*)
+	echo "$0:: Unknown core module"
+	variant="unknown core module"
+	cpu="arm_intcm"
+	;;
+
+	esac
+fi
+
+if [ "$cpu" == "arm_intcm" ]
+then
+	echo "/* Core module undefined/not ported */"	>> tmp.fil
+	echo "#define CONFIG_ARM_INTCM 1"		>> tmp.fil
+	echo -n	"#undef CONFIG_CM_MULTIPLE_SSRAM"	>> tmp.fil
+	echo -n	"	/* CM may not have " 		>> tmp.fil
+	echo	"multiple SSRAM mapping */"		>> tmp.fil
+	echo -n	"#undef CONFIG_CM_SPD_DETECT " 		>> tmp.fil
+	echo -n	" /* CM may not support SPD " 		>> tmp.fil
+	echo	"query */"				>> tmp.fil
+	echo -n	"#undef CONFIG_CM_REMAP	" 		>> tmp.fil
+	echo -n	" /* CM may not support "		>> tmp.fil
+	echo	"remapping */"	 			>> tmp.fil
+	echo -n	"#undef CONFIG_CM_INIT	" 		>> tmp.fil
+	echo -n	" /* CM may not have	"		>> tmp.fil
+	echo	"initialization reg */"			>> tmp.fil
+	echo -n	"#undef CONFIG_CM_TCRAM	" 		>> tmp.fil
+	echo	" /* CM may not have TCRAM */" 		>> tmp.fil
+fi
+mv tmp.fil ./include/config.h
+# ---------------------------------------------------------
+#	Ensure correct core object loaded first in U-Boot image
+# ---------------------------------------------------------
+sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorap/u-boot.lds.template > board/integratorap/u-boot.lds
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+./mkconfig -a integratorap arm $cpu integratorap;
+echo "Variant:: $variant with core $cpu"
+
diff --git a/board/integratorap/u-boot.lds.template b/board/integratorap/u-boot.lds.template
new file mode 100755
index 0000000..0ec8087
--- /dev/null
+++ b/board/integratorap/u-boot.lds.template
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+# Template used during configuration to emsure the core module processor code,
+# from CPU_FILE, is placed at the start of the image */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+		CPU_FILE (.text)
+		*(.text)
+	}
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/integratorcp/Makefile b/board/integratorcp/Makefile
new file mode 100755
index 0000000..3d589fc
--- /dev/null
+++ b/board/integratorcp/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= integratorcp.o flash.o
+SOBJS	:= lowlevel_init.o memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/integratorcp/config.mk b/board/integratorcp/config.mk
new file mode 100755
index 0000000..25b79b3
--- /dev/null
+++ b/board/integratorcp/config.mk
@@ -0,0 +1,5 @@
+#
+# image should be loaded at 0x01000000
+#
+
+TEXT_BASE = 0x01000000
diff --git a/board/integratorcp/flash.c b/board/integratorcp/flash.c
new file mode 100755
index 0000000..4d6eff0
--- /dev/null
+++ b/board/integratorcp/flash.c
@@ -0,0 +1,564 @@
+/*
+ * (C) Copyright 2004
+ * Xiaogeng (Shawn) Jin, Agilent Technologies, xiaogeng_jin@agilent.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define DEBUG
+
+#define PHYS_FLASH_SECT_SIZE	0x00040000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+/* CP control register base address */
+#define CPCR_BASE      		0xCB000000
+#define CPCR_EXTRABANK		0x8
+#define CPCR_FLASHSIZE		0x4
+#define CPCR_FLWREN		0x2
+#define CPCR_FLVPPEN		0x1
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	int i, nbanks;
+	ulong size = 0;
+	vu_long *cpcr = (vu_long *)CPCR_BASE;
+
+	/* Check if there is an extra bank of flash */
+	if (cpcr[1] & CPCR_EXTRABANK)
+		nbanks = 2;
+	else
+		nbanks = 1;
+
+	if (nbanks > CFG_MAX_FLASH_BANKS)
+		nbanks = CFG_MAX_FLASH_BANKS;
+
+	/* Enable flash write */
+	cpcr[1] |= 3;
+
+	for (i = 0; i < nbanks; i++) {
+		flash_get_size ((FPW *)(CFG_FLASH_BASE + size), &flash_info[i]);
+		flash_get_offsets (CFG_FLASH_BASE + size, &flash_info[i]);
+		size += flash_info[i].size;
+	}
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+		      &flash_info[0]);
+#endif
+
+	/* Protect SIB (0x24800000) and bootMonitor (0x24c00000) */
+	flash_protect (FLAG_PROTECT_SET,
+		       flash_info[0].start[62],
+		       flash_info[0].start[63] + PHYS_FLASH_SECT_SIZE - 1,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base +	(i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	/* Integrator CP board uses 28F640J3C or 28F128J3C parts,
+	 * which have the same device id numbers as 28F640J3A or
+	 * 28F128J3A
+	 */
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("FLASH 28F640J3C\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("FLASH 28F128J3C\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+	vu_long *cpcr = (vu_long *)CPCR_BASE;
+	int nsects;
+
+	/* Check the flash size */
+	if (cpcr[1] & CPCR_FLASHSIZE)
+		nsects = 128;
+	else
+		nsects = 64;
+
+	if (nsects > CFG_MAX_FLASH_SECT)
+		nsects = CFG_MAX_FLASH_SECT;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+		return (0); /* no or unknown flash */
+	}
+
+	mb ();
+	value = addr[1]; /* device ID */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB */
+
+	case (FPW) (INTEL_ID_28F640J3A):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = nsects;
+		info->size = nsects * PHYS_FLASH_SECT_SIZE;
+		break;
+
+	case (FPW) (INTEL_ID_28F128J3A):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = nsects;
+		info->size = nsects * PHYS_FLASH_SECT_SIZE;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+	FPW status;
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+
+	reset_timer_masked();
+	while (((status = *addr) & (FPW)0x00800080) != 0x00800080) {
+		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout");
+			break;
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			/* flash_unprotect_sectors (addr); */
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050; /* clear status register */
+			*addr = (FPW) 0x00200020; /* erase setup */
+			*addr = (FPW) 0x00D000D0; /* erase confirm */
+			mb();
+
+			udelay(1000); /* Let's wait 1 ms */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					*addr = (FPW)0x00700070;
+					status = *addr;
+					if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) {
+						/* erase suspended? Resume it */
+						reset_timer_masked();
+						*addr = (FPW) 0x00D000D0;
+					} else {
+#ifdef DEBUG
+						printf ("Timeout,0x%08x\n", status);
+#else
+						printf("Timeout\n");
+#endif
+
+						*addr = (FPW) 0x00500050;
+						*addr = (FPW) 0x00FF00FF; /* reset to read mode */
+						rcode = 1;
+						break;
+					}
+				}
+			}
+
+			*addr = (FPW) 0x00FF00FF; /* resest to read mode */
+			printf (" done\n");
+		}
+	}
+
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* flash_unprotect_sectors (addr); */
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	mb();
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+#ifdef DEBUG
+			*addr = (FPW) 0x00700070;
+			status = *addr;
+			printf("## status=0x%08x, addr=0x%08x\n", status, addr);
+#endif
+			*addr = (FPW) 0x00500050; /* clear status register cmd */
+			*addr = (FPW) 0x00FF00FF; /* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF; /* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/integratorcp/integratorcp.c b/board/integratorcp/integratorcp.c
new file mode 100755
index 0000000..216876b
--- /dev/null
+++ b/board/integratorcp/integratorcp.c
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void flash__init (void);
+void ether__init (void);
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of Integrator Board */
+	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	gd->flags = 0;
+
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+	cm_remap();	/* remaps writeable memory to 0x00000000 */
+#endif
+
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	setenv("verify", "n");
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	      for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size	 = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_CM_SPD_DETECT
+    {
+extern void dram_query(void);
+	unsigned long cm_reg_sdram;
+	unsigned long sdram_shift;
+
+	dram_query();	/* Assembler accesses to CM registers */
+			/* Queries the SPD values	      */
+
+	/* Obtain the SDRAM size from the CM SDRAM register */
+
+	cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+	/*   Register	      SDRAM size
+	 *
+	 *   0xXXXXXXbbb000bb	 16 MB
+	 *   0xXXXXXXbbb001bb	 32 MB
+	 *   0xXXXXXXbbb010bb	 64 MB
+	 *   0xXXXXXXbbb011bb	128 MB
+	 *   0xXXXXXXbbb100bb	256 MB
+	 *
+	 */
+	sdram_shift		 = ((cm_reg_sdram & 0x0000001C)/4)%4;
+	gd->bd->bi_dram[0].size	 = 0x01000000 << sdram_shift;
+
+    }
+#endif /* CM_SPD_DETECT */
+
+	return 0;
+}
+
+/* The Integrator/CP timer1 is clocked at 1MHz
+ * can be divided by 16 or 256
+ * and can be set up as a 32-bit timer
+ */
+/* U-Boot expects a 32 bit timer, running at CFG_HZ */
+/* Keep total timer count to avoid losing decrements < div_timer */
+static unsigned long long total_count = 0;
+static unsigned long long lastdec;	 /* Timer reading at last call	   */
+static unsigned long long div_clock = 1; /* Divisor applied to timer clock */
+static unsigned long long div_timer = 1; /* Divisor to convert timer reading
+					  * change to U-Boot ticks
+					  */
+/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
+static ulong timestamp;		/* U-Boot ticks since startup	      */
+
+#define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF)
+#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
+
+/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec
+ *  - unless otherwise stated
+ */
+
+/* starts up a counter
+ * - the Integrator/CP timer can be set up to issue an interrupt */
+int interrupt_init (void)
+{
+	/* Load timer with initial value */
+	*(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
+	/* Set timer to be
+	 *	enabled		  1
+	 *	periodic	  1
+	 *	no interrupts	  0
+	 *	X		  0
+	 *	divider 1	 00 == less rounding error
+	 *	32 bit		  1
+	 *	wrapping	  0
+	 */
+	*(volatile ulong *)(CFG_TIMERBASE + 8) = 0x000000C2;
+	/* init the timestamp */
+	total_count = 0ULL;
+	reset_timer_masked();
+
+	div_timer  = (unsigned long long)(CFG_HZ_CLOCK / CFG_HZ);
+	div_timer /= div_clock;
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base_ticks)
+{
+	return get_timer_masked () - base_ticks;
+}
+
+void set_timer (ulong ticks)
+{
+	timestamp   = ticks;
+	total_count = (unsigned long long)ticks * div_timer;
+}
+
+/* delay usec useconds */
+void udelay (unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	/* Convert to U-Boot ticks */
+	tmo  = usec * CFG_HZ;
+	tmo /= (1000000L);
+
+	tmp  = get_timer_masked();	/* get current timestamp */
+	tmo += tmp;			/* form target timestamp */
+
+	while (get_timer_masked () < tmo) {/* loop till event */
+		/*NOP*/;
+	}
+}
+
+void reset_timer_masked (void)
+{
+	/* capure current decrementer value    */
+	lastdec	  = (unsigned long long)READ_TIMER;
+	/* start "advancing" time stamp from 0 */
+	timestamp = 0L;
+}
+
+/* converts the timer reading to U-Boot ticks	       */
+/* the timestamp is the number of ticks since reset    */
+ulong get_timer_masked (void)
+{
+	/* get current count */
+	unsigned long long now = (unsigned long long)READ_TIMER;
+
+	if(now > lastdec) {
+		/* Must have wrapped */
+		total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
+	} else {
+		total_count += lastdec - now;
+	}
+	lastdec	  = now;
+	timestamp = (ulong)(total_count/div_timer);
+
+	return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+	udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return (unsigned long long)get_timer(0);
+}
+
+/*
+ * Return the timebase clock frequency
+ * i.e. how often the timer decrements
+ */
+ulong get_tbclk (void)
+{
+	return (ulong)(((unsigned long long)CFG_HZ_CLOCK)/div_clock);
+}
diff --git a/board/integratorcp/lowlevel_init.S b/board/integratorcp/lowlevel_init.S
new file mode 100755
index 0000000..18f7d2e
--- /dev/null
+++ b/board/integratorcp/lowlevel_init.S
@@ -0,0 +1,214 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Reset using CM control register */
+.global reset_cpu
+reset_cpu:
+	mov	r0, #CM_BASE
+	ldr	r1,[r0,#OS_CTRL]
+	orr	r1,r1,#CMMASK_RESET
+	str	r1,[r0,#OS_CTRL]
+
+reset_failed:
+	b	reset_failed
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+	/* If U-Boot has been run after the ARM boot monitor
+	 * then all the necessary actions have been done
+	 * otherwise we are running from user flash mapped to 0x00000000
+	 * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+	 * Changes to the (possibly soft) reset defaults of the processor
+	 * itself should be performed in cpu/arm<>/start.S
+	 * This function affects only the core module or board settings
+	 */
+
+#ifdef CONFIG_CM_INIT
+	/* CM has an initialization register
+	 * - bits in it are wired into test-chip pins to force
+	 *   reset defaults
+	 * - may need to change its contents for U-Boot
+	 */
+
+	/* set the desired CM specific value */
+	mov	r2,#CMMASK_LOWVEC	/* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+	orr	r2,r2,#CMMASK_INIT_102
+#else
+
+#if	!defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+	!defined (CONFIG_CM940T)
+	/* CMxx6 code	*/
+
+#ifdef	CONFIG_CM_MULTIPLE_SSRAM
+	/* set simple mapping			*/
+	and	r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM	*/
+
+#ifdef	CONFIG_CM_TCRAM
+	/* disable TCRAM			*/
+	and	r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM		*/
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+			defined (CONFIG_CM1136JF_S)
+
+	and	r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+	orr	r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+	/* read CM_INIT		 */
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_INIT]
+	/* check against desired bit setting */
+	and	r3,r1,r2
+	cmp	r3,r2
+	beq	init_reg_OK
+
+	/* lock for change */
+	mov	r3, #CMVAL_LOCK1
+	and	r3, r3, #CMVAL_LOCK2
+	str	r3, [r0, #OS_LOCK]
+	/* set desired value */
+	orr	r1,r1,r2
+	/* write & relock CM_INIT */
+	str	r1, [r0, #OS_INIT]
+	mov	r1, #CMVAL_UNLOCK
+	str	r1, [r0, #OS_LOCK]
+
+	/* soft reset so new values used */
+	b	reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+	mov	pc, lr
+
+#ifdef	CONFIG_CM_SPD_DETECT
+	/* Fast memory is available for the DRAM data
+	 * - ensure it has been transferred, then summarize the data
+	 *	 into a CM register
+	 */
+.globl dram_query
+dram_query:
+	stmfd	r13!,{r4-r6,lr}
+	/* set up SDRAM info					*/
+	/* - based on example code from the CM User Guide */
+	mov	r0, #CM_BASE
+
+readspdbit:
+	ldr	r1, [r0, #OS_SDRAM]	/* read the SDRAM register */
+	and	r1, r1, #0x20		/* mask SPD bit (5)		 */
+	cmp	r1, #0x20		/* test if set			 */
+	bne	readspdbit
+
+setupsdram:
+	add	r0, r0, #OS_SPD		/* address the copy of the SDP data	*/
+	ldrb	r1, [r0, #3]		/* number of row address lines		*/
+	ldrb	r2, [r0, #4]		/* number of column address lines	*/
+	ldrb	r3, [r0, #5]		/* number of banks			*/
+	ldrb	r4, [r0, #31]		/* module bank density			*/
+	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)	*/
+	mov	r5, r5, ASL#2		/* size in MB				*/
+	mov	r0, #CM_BASE		/* reload for later code		*/
+	cmp	r5, #0x10		/* is it 16MB?				*/
+	bne	not16
+	mov	r6, #0x2		/* store size and CAS latency of 2	*/
+	b	writesize
+
+not16:
+	cmp	r5, #0x20		/* is it  32MB? */
+	bne	not32
+	mov	r6, #0x6
+	b	writesize
+
+not32:
+	cmp	r5, #0x40		/* is it  64MB? */
+	bne	not64
+	mov	r6, #0xa
+	b	writesize
+
+not64:
+	cmp	r5, #0x80		/* is it 128MB? */
+	bne	not128
+	mov	r6, #0xe
+	b	writesize
+
+not128:
+	/* if it is none of these sizes then it is either 256MB, or
+	 * there is no SDRAM fitted so default to 256MB
+	 */
+	mov	r6, #0x12
+
+writesize:
+	mov	r1, r1, ASL#8		/* row addr lines from SDRAM reg */
+	orr	r2, r1, r2, ASL#12	/* OR in column address lines	 */
+	orr	r3, r2, r3, ASL#16	/* OR in number of banks	 */
+	orr	r6, r6, r3		/* OR in size and CAS latency	 */
+	str	r6, [r0, #OS_SDRAM]	/* store SDRAM parameters	 */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+	ldmfd	r13!,{r4-r6,pc}			/* back to caller */
+
+#ifdef	CONFIG_CM_REMAP
+	/* CM remap bit is operational
+	 * - use it to map writeable memory at 0x00000000, in place of flash
+	 */
+.globl cm_remap
+cm_remap:
+	stmfd	r13!,{r4-r10,lr}
+
+	mov	r0, #CM_BASE
+	ldr	r1, [r0, #OS_CTRL]
+	orr	r1, r1, #CMMASK_REMAP	/* set remap and led bits */
+	str	r1, [r0, #OS_CTRL]
+
+	/* Now 0x00000000 is writeable, replace the vectors	*/
+	ldr	r0, =_start	/* r0 <- start of vectors	*/
+	ldr	r2, =_armboot_start	/* r2 <- past vectors	*/
+	sub	r1,r1,r1		/* destination 0x00000000	*/
+
+copy_vec:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]	*/
+	stmia	r1!, {r3-r10}		/* copy to	 target address [r1]	*/
+	cmp	r0, r2			/* until source end address [r2]	*/
+	ble	copy_vec
+
+	ldmfd	r13!,{r4-r10,pc}	/* back to caller			*/
+
+#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/board/integratorcp/memsetup.S b/board/integratorcp/memsetup.S
new file mode 100755
index 0000000..dfdc784
--- /dev/null
+++ b/board/integratorcp/memsetup.S
@@ -0,0 +1,29 @@
+/*
+ * Memory setup for integratorAP
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * 	Memory setup
+ *      - the reset defaults are assumed sufficient
+ */
+
+.globl memsetup
+memsetup:
+	mov	pc,lr
diff --git a/board/integratorcp/split_by_variant.sh b/board/integratorcp/split_by_variant.sh
new file mode 100755
index 0000000..3a35433
--- /dev/null
+++ b/board/integratorcp/split_by_variant.sh
@@ -0,0 +1,111 @@
+#!/bin/sh
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n "/* Integrator configuration implied "   > tmp.fil
+echo    " by Makefile target */"   		>> tmp.fil
+echo -n "#define CONFIG_INTEGRATOR"  		>> tmp.fil
+echo	 " /* Integrator board */"  		>> tmp.fil
+echo -n "#define CONFIG_ARCH_CINTEGRATOR"	>> tmp.fil
+echo     " 1 /* Integrator/CP   */"  		>> tmp.fil
+
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$1" == "" ]
+then
+	echo "$0:: No parameters - using arm_intcm"
+else
+	case "$1" in
+	ap966)
+	cpu="arm_intcm"
+	variant="unported core module CM966E-S"
+	;;
+
+	ap922_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T"
+	;;
+
+	integratorcp_config	|	\
+	cp_config)
+	cpu="arm_intcm"
+	variant="unspecified core module"
+	;;
+
+	cp922_XA10_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T_XA10"
+	echo -n "#define CONFIG_CM922T_XA10" 		>> tmp.fil
+	echo    " 1 /* CPU core is ARM922T_XA10 */" 	>> tmp.fil
+	;;
+
+	cp920t_config)
+	cpu="arm920t"
+	variant="Core module CM920T"
+	echo -n "#define CONFIG_CM920T" 		>> tmp.fil
+	echo    " 1 /* CPU core is ARM920T */"		>> tmp.fil
+	;;
+
+	cp926ejs_config)
+	cpu="arm926ejs"
+	variant="Core module CM926EJ-S"
+	echo -n "#define CONFIG_CM926EJ_S"		>> tmp.fil
+	echo    " 1 /* CPU core is ARM926EJ-S */ "	>> tmp.fil
+	;;
+
+
+	cp946es_config)
+	cpu="arm946es"
+	variant="Core module CM946E-S"
+	echo -n "#define CONFIG_CM946E_S"		>> tmp.fil
+	echo    " 1 /* CPU core is ARM946E-S */ "	>> tmp.fil
+	;;
+
+	cp1136_config)
+	cpu="arm1136"
+	variant="Core module CM1136EJF-S"
+	echo -n "#define CONFIG_CM1136EJF_S"		>> tmp.fil
+	echo    " 1 /* CPU core is ARM1136JF-S */ "	>> tmp.fil
+	;;
+
+	*)
+	echo "$0:: Unknown core module"
+	variant="unknown core module"
+	cpu="arm_intcm"
+	;;
+
+	esac
+
+fi
+
+if [ "$cpu" == "arm_intcm" ]
+then
+	echo "/* Core module undefined/not ported */"	>> tmp.fil
+	echo "#define CONFIG_ARM_INTCM 1"  		>> tmp.fil
+	echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM"	>> tmp.fil
+	echo -n "  /* CM may not have " 		>> tmp.fil
+	echo    "multiple SSRAM mapping */"  		>> tmp.fil
+	echo -n "#undef CONFIG_CM_SPD_DETECT " 		>> tmp.fil
+	echo -n " /* CM may not support SPD " 		>> tmp.fil
+	echo    "query */"    				>> tmp.fil
+	echo -n "#undef CONFIG_CM_REMAP  " 		>> tmp.fil
+	echo -n " /* CM may not support "  		>> tmp.fil
+	echo    "remapping */"   			>> tmp.fil
+	echo -n "#undef CONFIG_CM_INIT  " 		>> tmp.fil
+	echo -n " /* CM may not have  "  		>> tmp.fil
+	echo    "initialization reg */"  		>> tmp.fil
+	echo -n "#undef CONFIG_CM_TCRAM  " 		>> tmp.fil
+	echo    " /* CM may not have TCRAM */" 		>> tmp.fil
+fi
+mv tmp.fil ./include/config.h
+# ---------------------------------------------------------
+#  Ensure correct core object loaded first in U-Boot image
+# ---------------------------------------------------------
+sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorcp/u-boot.lds.template > board/integratorcp/u-boot.lds
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+./mkconfig -a integratorcp arm $cpu integratorcp;
+echo "Variant:: $variant with core $cpu"
+
diff --git a/board/integratorcp/u-boot.lds.template b/board/integratorcp/u-boot.lds.template
new file mode 100755
index 0000000..0ec8087
--- /dev/null
+++ b/board/integratorcp/u-boot.lds.template
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+# Template used during configuration to emsure the core module processor code,
+# from CPU_FILE, is placed at the start of the image */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+		CPU_FILE (.text)
+		*(.text)
+	}
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/ip860/Makefile b/board/ip860/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/ip860/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/ip860/config.mk b/board/ip860/config.mk
new file mode 100755
index 0000000..ea3b873
--- /dev/null
+++ b/board/ip860/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MicroSys IP860 VMEBus Systems
+#
+
+TEXT_BASE = 0x10000000
diff --git a/board/ip860/flash.c b/board/ip860/flash.c
new file mode 100755
index 0000000..2cf23b3
--- /dev/null
+++ b/board/ip860/flash.c
@@ -0,0 +1,456 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t	*memctl = &immap->im_memctl;
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	bcsr->bd_ctrl |= BD_CTRL_FLWE;
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
+				(memctl->memc_br1 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* all possible flash types
+	 * (28F016SV, 28F160S3, 28F320S3)
+	 * have the same erase block size: 64 kB per chip,
+	 * of 128 kB per bank
+	 */
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += 0x00020000;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+
+	value = addr[0];
+	switch (value) {
+	case (MT_MANUFACT & 0x00FF00FF):	/* MT or => Intel */
+	case (INTEL_ALT_MANU & 0x00FF00FF):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case (INTEL_ID_28F016S):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F160S3):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F320S3):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 2x4 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base + (i * 0x00020000);
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+			/* Resume Command, as per errata update */
+			*addr = 0xD0D0D0D0;
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+		}
+	}
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+	while (((csr = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x00400040) {
+printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c
new file mode 100755
index 0000000..9dd809b
--- /dev/null
+++ b/board/ip860/ip860.c
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+unsigned long ip860_get_dram_size(void);
+unsigned long ip860_get_clk_freq (void);
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,					/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07,		/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7ffffc07,					/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+/* ------------------------------------------------------------------------- */
+int board_early_init_f(void)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */
+    memctl->memc_or4 = CFG_OR4;
+    memctl->memc_br4 = CFG_BR4;
+
+    return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (IP860...)
+ */
+
+int checkboard (void)
+{
+	unsigned char *s, *e;
+	unsigned char buf[64];
+	int i;
+
+	puts ("Board: ");
+
+	i = getenv_r ("serial#", (char *)buf, sizeof (buf));
+	s = (i > 0) ? buf : NULL;
+
+	if (!s || strncmp ((char *)s, "IP860", 5)) {
+		puts ("### No HW ID - assuming IP860");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		for (; s < e; ++s) {
+			putc (*s);
+		}
+	}
+
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+	ulong refresh_val;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	if (ip860_get_clk_freq() == 50000000)
+	{
+		memctl->memc_mptpr = 0x0400;
+		refresh_val = 0xC3000000;
+	}
+	else
+	{
+		memctl->memc_mptpr = 0x0200;
+		refresh_val = 0x9C000000;
+	}
+
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 to the SDRAM address
+	 */
+	memctl->memc_or2 = CFG_OR2;
+	memctl->memc_br2 = CFG_BR2;
+
+	/* IP860 boards have only one bank SDRAM */
+
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mamr = 0x00804114 | refresh_val;
+	memctl->memc_mcr  = 0x80004105;	/* run precharge pattern from loc 5 */
+	udelay(1);
+	memctl->memc_mamr = 0x00804118 | refresh_val;
+	memctl->memc_mcr  = 0x80004130;	/* run refresh pattern 8 times */
+
+
+	udelay (1000);
+
+	/*
+	 * Check SDRAM Memory Size
+	 */
+	if (ip860_get_dram_size() == 16)
+		size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE);
+	else
+		size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
+	memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	udelay (10000);
+
+	/*
+	 * Also, map other memory to correct position
+	 */
+
+#if (defined(CFG_OR1) && defined(CFG_BR1_PRELIM))
+	memctl->memc_or1 = CFG_OR1;
+	memctl->memc_br1 = CFG_BR1;
+#endif
+
+#if defined(CFG_OR3) && defined(CFG_BR3)
+	memctl->memc_or3 = CFG_OR3;
+	memctl->memc_br3 = CFG_BR3;
+#endif
+
+#if defined(CFG_OR4) && defined(CFG_BR4)
+	memctl->memc_or4 = CFG_OR4;
+	memctl->memc_br4 = CFG_BR4;
+#endif
+
+#if defined(CFG_OR5) && defined(CFG_BR5)
+	memctl->memc_or5 = CFG_OR5;
+	memctl->memc_br5 = CFG_BR5;
+#endif
+
+#if defined(CFG_OR6) && defined(CFG_BR6)
+	memctl->memc_or6 = CFG_OR6;
+	memctl->memc_br6 = CFG_BR6;
+#endif
+
+#if defined(CFG_OR7) && defined(CFG_BR7)
+	memctl->memc_or7 = CFG_OR7;
+	memctl->memc_br7 = CFG_BR7;
+#endif
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	ulong mask = PB_ENET_RESET | PB_ENET_JABD;
+	ulong reg;
+
+	/* Make sure PHY is not in low-power mode */
+	immr->im_cpm.cp_pbpar &= ~(mask);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(mask);	/* active output */
+
+	/* Set  JABD low  (no JABber Disable),
+	 * and RESET high (Reset PHY)
+	 */
+	reg = immr->im_cpm.cp_pbdat;
+	reg = (reg & ~PB_ENET_JABD) | PB_ENET_RESET;
+	immr->im_cpm.cp_pbdat = reg;
+
+	/* now drive outputs */
+	immr->im_cpm.cp_pbdir |= mask;	/* output */
+	udelay (1000);
+	/*
+	   * Release RESET signal
+	 */
+	immr->im_cpm.cp_pbdat &= ~(PB_ENET_RESET);
+	udelay (1000);
+}
+
+/* ------------------------------------------------------------------------- */
+
+unsigned long ip860_get_clk_freq(void)
+{
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+	ulong temp;
+	uchar sysclk;
+
+	if ((bcsr->bd_status & 0x80) == 0x80)	/* bd_rev valid ? */
+		sysclk = (bcsr->bd_rev & 0x18) >> 3;
+	else
+		sysclk = 0x00;
+
+	switch (sysclk)
+	{
+		case 0x00:
+			temp = 50000000;
+			break;
+
+		case 0x01:
+			temp = 80000000;
+			break;
+
+		default:
+			temp = 50000000;
+			break;
+	}
+
+	return (temp);
+
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+unsigned long ip860_get_dram_size(void)
+{
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+	ulong temp;
+	uchar dram_size;
+
+	if ((bcsr->bd_status & 0x80) == 0x80)	/* bd_rev valid ? */
+		dram_size = (bcsr->bd_rev & 0xE0) >> 5;
+	else
+		dram_size = 0x00;	/* default is 16 MB */
+
+	switch (dram_size)
+	{
+		case 0x00:
+			temp = 16;
+			break;
+
+		case 0x01:
+			temp = 32;
+			break;
+
+		default:
+			temp = 16;
+			break;
+	}
+
+	return (temp);
+
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds
new file mode 100755
index 0000000..8cb2504
--- /dev/null
+++ b/board/ip860/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    cpu/mpc8xx/interrupts.o (.text)
+    lib_ppc/time.o		(.text)
+    lib_ppc/ticks.o		(.text)
+/**
+    . = env_offset;
+    common/environment.o(.text)
+**/
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug
new file mode 100755
index 0000000..43d2b3b
--- /dev/null
+++ b/board/ip860/u-boot.lds.debug
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    cpu/mpc8xx/interrupts.o (.text)
+    lib_ppc/time.o		(.text)
+    lib_ppc/ticks.o		(.text)
+/**
+    . = env_offset;
+    common/environment.o(.text)
+**/
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/iphase4539/Makefile b/board/iphase4539/Makefile
new file mode 100755
index 0000000..19da5d0
--- /dev/null
+++ b/board/iphase4539/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/iphase4539/config.mk b/board/iphase4539/config.mk
new file mode 100755
index 0000000..632c1d2
--- /dev/null
+++ b/board/iphase4539/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# iphase4539 board
+#
+
+TEXT_BASE = 0xffb00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/iphase4539/flash.c b/board/iphase4539/flash.c
new file mode 100755
index 0000000..4eca467
--- /dev/null
+++ b/board/iphase4539/flash.c
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Adapted for Interphase 4539 by Wolfgang Grandegger <wg@denx.de>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <flash.h>
+#include <asm/io.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+
+extern int hwc_flash_size(void);
+static ulong flash_get_size (u32 addr, flash_info_t *info);
+static int flash_get_offsets (u32 base, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_reset (u32 addr);
+
+#define out8(a,v) *(volatile unsigned char*)(a) = v
+#define in8(a)	  *(volatile unsigned char*)(a)
+#define in32(a)	  *(volatile unsigned long*)(a)
+#define iobarrier_rw() eieio()
+
+unsigned long flash_init (void)
+{
+	unsigned int i;
+	unsigned long flash_size = 0;
+	unsigned long bank_size;
+	unsigned int bank = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = 0;
+		flash_info[i].size = 0;
+	}
+
+	/* Initialise the BOOT Flash */
+	if (bank == CFG_MAX_FLASH_BANKS) {
+		puts ("Warning: not all Flashes are initialised !");
+		return flash_size;
+	}
+
+	bank_size = flash_get_size (CFG_FLASH_BASE, flash_info + bank);
+	if (bank_size) {
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
+    CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_MAX_FLASH_SIZE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      flash_info + bank);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			      flash_info + bank);
+#endif
+
+		/* HWC protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_FLASH_BASE,
+			      CFG_FLASH_BASE + 0x10000 - 1,
+			      flash_info + bank);
+
+		flash_size += bank_size;
+		bank++;
+	} else {
+		puts ("Warning: the BOOT Flash is not initialised !");
+	}
+
+	return flash_size;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (u32 addr, flash_info_t *info)
+{
+	volatile uchar value;
+#if 0
+	int i;
+#endif
+
+	/* Write auto select command: read Manufacturer ID */
+	out8(addr + 0x0555, 0xAA);
+	iobarrier_rw();
+	udelay(10);
+	out8(addr + 0x02AA, 0x55);
+	iobarrier_rw();
+	udelay(10);
+	out8(addr + 0x0555, 0x90);
+	iobarrier_rw();
+	udelay(10);
+
+	value = in8(addr);
+	iobarrier_rw();
+	udelay(10);
+	switch (value | (value << 16)) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		flash_reset (addr);
+		return 0;
+	}
+
+	value = in8(addr + 1);			/* device ID		*/
+	iobarrier_rw();
+
+	switch (value) {
+	case AMD_ID_LV033C:
+		info->flash_id += FLASH_AM033C;
+		info->size = hwc_flash_size();
+		if (info->size > CFG_MAX_FLASH_SIZE) {
+			printf("U-Boot supports only %d MB\n",
+			       CFG_MAX_FLASH_SIZE);
+			info->size = CFG_MAX_FLASH_SIZE;
+		}
+		info->sector_count = info->size / 0x10000;
+		break;				/* => 4 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		flash_reset (addr);
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (!flash_get_offsets (addr, info)) {
+		flash_reset (addr);
+		return 0;
+	}
+
+#if 0
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		value = in8(info->start[i] + 2);
+		iobarrier_rw();
+		info->protect[i] = (value & 1) != 0;
+	}
+#endif
+
+	/*
+	 * Reset bank to read mode
+	 */
+	flash_reset (addr);
+
+	return (info->size);
+}
+
+static int flash_get_offsets (u32 base, flash_info_t *info)
+{
+	unsigned int i, size;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM033C:
+		/* set sector offsets for uniform sector type	*/
+		size = info->size / info->sector_count;
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + i * size;
+		}
+		break;
+	default:
+		return 0;
+	}
+
+	return 1;
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile u32 addr = info->start[0];
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if (s_first < 0 || s_first > s_last) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN ||
+	    info->flash_id > FLASH_AMD_COMP) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x555, 0x80);
+	iobarrier_rw();
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = info->start[sect];
+			out8(addr, 0x30);
+			iobarrier_rw();
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = info->start[l_sect];
+	while ((in8(addr) & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+		iobarrier_rw();
+	}
+
+DONE:
+	/* reset to read mode */
+	flash_reset (info->start[0]);
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile u32 addr = info->start[0];
+	ulong start;
+	int flag, i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((in32(dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* first, perform an unlock bypass command to speed up flash writes */
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x555, 0x20);
+	iobarrier_rw();
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *)&data;
+		out8(addr, 0xA0);
+		iobarrier_rw();
+		out8(dest+i, data_ch[i]);
+		iobarrier_rw();
+		udelay(10); /* XXX */
+	}
+
+	/* we're done, now do an unlock bypass reset */
+	out8(addr, 0x90);
+	iobarrier_rw();
+	out8(addr, 0x00);
+	iobarrier_rw();
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((in32(dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+		iobarrier_rw();
+	}
+
+	flash_reset (addr);
+
+	return (0);
+}
+
+/*
+ * Reset bank to read mode
+ */
+static void flash_reset (u32 addr)
+{
+	out8(addr, 0xF0);	/* reset bank */
+	iobarrier_rw();
+}
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM033C:	printf ("AM29LV033C (32 Mbit, uniform sectors)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size % 0x100000 == 0) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size / 0x100000, info->sector_count);
+	}
+	else if (info->size % 0x400 == 0) {
+		printf ("  Size: %ld KB in %d Sectors\n",
+			info->size / 0x400, info->sector_count);
+	}
+	else {
+		printf ("  Size: %ld B in %d Sectors\n",
+			info->size, info->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
diff --git a/board/iphase4539/iphase4539.c b/board/iphase4539/iphase4539.c
new file mode 100755
index 0000000..0ca9cf5
--- /dev/null
+++ b/board/iphase4539/iphase4539.c
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/io.h>
+#include <asm/immap_8260.h>
+
+int hwc_flash_size (void);
+int hwc_local_sdram_size (void);
+int hwc_main_sdram_size (void);
+int hwc_serial_number (void);
+int hwc_mac_address (char *str);
+int hwc_manufact_date (char *str);
+int seeprom_read (int addr, uchar * data, int size);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ *
+ * The port definitions are taken from the old firmware (see
+ * also SYS/H/4539.H):
+ *
+ *        ppar      psor        pdir       podr       pdat
+ * PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0
+ * PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290
+ * PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d
+ * PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9
+ */
+const iop_conf_t iop_conf_tab[4][32] = {
+
+	/* Port A configuration */
+	{							/* conf ppar psor pdir podr pdat */
+	 {0, 1, 0, 0, 0, 0},		/* PA31 FCC1_TXENB  SLAVE */
+	 {0, 1, 0, 1, 0, 0},		/* PA30 FCC1_TXCLAV SLAVE */
+	 {0, 1, 0, 1, 0, 0},		/* PA29 FCC1_TXSOC */
+	 {0, 1, 0, 0, 0, 0},		/* PA28 FCC1_RXENB  SLAVE */
+	 {0, 1, 0, 0, 0, 0},		/* PA27 FCC1_RXSOC */
+	 {0, 1, 0, 1, 0, 0},		/* PA26 FCC1_RXCLAV SLAVE */
+	 {0, 1, 0, 1, 0, 1},		/* PA25 FCC1_TXD0 */
+	 {0, 1, 0, 1, 0, 1},		/* PA24 FCC1_TXD1 */
+	 {0, 1, 0, 1, 0, 1},		/* PA23 FCC1_TXD2 */
+	 {0, 1, 0, 1, 0, 1},		/* PA22 FCC1_TXD3 */
+	 {0, 1, 0, 1, 0, 1},		/* PA21 FCC1_TXD4 */
+	 {0, 1, 0, 1, 0, 1},		/* PA20 FCC1_TXD5 */
+	 {0, 1, 0, 1, 0, 1},		/* PA19 FCC1_TXD6 */
+	 {0, 1, 0, 1, 0, 1},		/* PA18 FCC1_TXD7 */
+	 {0, 1, 0, 0, 0, 0},		/* PA17 FCC1_RXD7 */
+	 {0, 1, 0, 0, 0, 0},		/* PA16 FCC1_RXD6 */
+	 {0, 1, 0, 0, 0, 0},		/* PA15 FCC1_RXD5 */
+	 {0, 1, 0, 0, 0, 0},		/* PA14 FCC1_RXD4 */
+	 {0, 1, 0, 0, 0, 0},		/* PA13 FCC1_RXD3 */
+	 {0, 1, 0, 0, 0, 0},		/* PA12 FCC1_RXD2 */
+	 {0, 1, 0, 0, 0, 0},		/* PA11 FCC1_RXD1 */
+	 {0, 1, 0, 0, 0, 0},		/* PA10 FCC1_RXD0 */
+	 {0, 1, 1, 1, 0, 1},		/* PA9  TDMA1_L1TXD */
+	 {0, 1, 1, 0, 0, 0},		/* PA8  TDMA1_L1RXD */
+	 {0, 0, 0, 0, 0, 0},		/* PA7  CONFIG0 */
+	 {0, 1, 1, 0, 0, 1},		/* PA6  TDMA1_L1RSYNC */
+	 {0, 0, 0, 1, 0, 0},		/* PA5  FCC2:RxAddr[2] */
+	 {0, 0, 0, 1, 0, 0},		/* PA4  FCC2:RxAddr[1] */
+	 {0, 0, 0, 1, 0, 0},		/* PA3  FCC2:RxAddr[0] */
+	 {0, 0, 0, 1, 0, 0},		/* PA2  FCC2:TxAddr[0] */
+	 {0, 0, 0, 1, 0, 0},		/* PA1  FCC2:TxAddr[1] */
+	 {0, 0, 0, 1, 0, 0}			/* PA0  FCC2:TxAddr[2] */
+	 },
+	/* Port B configuration */
+	{							/* conf ppar psor pdir podr pdat */
+	 {0, 0, 0, 1, 0, 0},		/* PB31 FCC2_RXSOC */
+	 {0, 0, 0, 1, 0, 0},		/* PB30 FCC2_TXSOC */
+	 {0, 0, 0, 1, 0, 0},		/* PB29 FCC2_RXCLAV */
+	 {0, 0, 0, 0, 0, 0},		/* PB28 CONFIG2 */
+	 {0, 1, 1, 0, 0, 1},		/* PB27 FCC2_TXD0 */
+	 {0, 1, 1, 0, 0, 0},		/* PB26 FCC2_TXD1 */
+	 {0, 0, 0, 1, 0, 0},		/* PB25 FCC2_TXD4 */
+	 {0, 1, 1, 0, 0, 1},		/* PB24 FCC2_TXD5 */
+	 {0, 0, 0, 1, 0, 0},		/* PB23 FCC2_TXD6 */
+	 {0, 1, 0, 1, 0, 1},		/* PB22 FCC2_TXD7 */
+	 {0, 1, 0, 0, 0, 0},		/* PB21 FCC2_RXD7 */
+	 {0, 1, 0, 0, 0, 0},		/* PB20 FCC2_RXD6 */
+	 {0, 1, 0, 0, 0, 0},		/* PB19 FCC2_RXD5 */
+	 {0, 0, 0, 1, 0, 0},		/* PB18 FCC2_RXD4 */
+	 {1, 1, 0, 0, 0, 0},		/* PB17 FCC3_RX_DV */
+	 {1, 1, 0, 0, 0, 0},		/* PB16 FCC3_RX_ER */
+	 {1, 1, 0, 1, 0, 0},		/* PB15 FCC3_TX_ER */
+	 {1, 1, 0, 1, 0, 0},		/* PB14 FCC3_TX_EN */
+	 {1, 1, 0, 0, 0, 0},		/* PB13 FCC3_COL */
+	 {1, 1, 0, 0, 0, 0},		/* PB12 FCC3_CRS */
+	 {1, 1, 0, 0, 0, 0},		/* PB11 FCC3_RXD3 */
+	 {1, 1, 0, 0, 0, 0},		/* PB10 FCC3_RXD2 */
+	 {1, 1, 0, 0, 0, 0},		/* PB9  FCC3_RXD1 */
+	 {1, 1, 0, 0, 0, 0},		/* PB8  FCC3_RXD0 */
+	 {1, 1, 0, 1, 0, 1},		/* PB7  FCC3_TXD0 */
+	 {1, 1, 0, 1, 0, 1},		/* PB6  FCC3_TXD1 */
+	 {1, 1, 0, 1, 0, 1},		/* PB5  FCC3_TXD2 */
+	 {1, 1, 0, 1, 0, 1},		/* PB4  FCC3_TXD3 */
+	 {0, 0, 0, 0, 0, 0},		/* PB3  */
+	 {0, 0, 0, 0, 0, 0},		/* PB2  */
+	 {0, 0, 0, 0, 0, 0},		/* PB1  */
+	 {0, 0, 0, 0, 0, 0},		/* PB0  */
+	 },
+	/* Port C configuration */
+	{							/* conf ppar psor pdir podr pdat */
+	 {0, 1, 0, 0, 0, 1},		/* PC31 CLK1 */
+	 {0, 0, 0, 1, 0, 0},		/* PC30 U1MASTER_N */
+	 {0, 1, 0, 0, 0, 1},		/* PC29 CLK3 */
+	 {0, 0, 0, 1, 0, 1},		/* PC28 -MT90220_RST */
+	 {0, 1, 0, 0, 0, 1},		/* PC27 CLK5 */
+	 {0, 0, 0, 1, 0, 1},		/* PC26 -QUADFALC_RST */
+	 {0, 1, 1, 1, 0, 1},		/* PC25 BRG4 */
+	 {1, 0, 0, 1, 0, 0},		/* PC24 MDIO */
+	 {1, 0, 0, 1, 0, 0},		/* PC23 MDC */
+	 {0, 1, 0, 0, 0, 1},		/* PC22 CLK10 */
+	 {0, 0, 0, 1, 0, 0},		/* PC21  */
+	 {0, 1, 0, 0, 0, 1},		/* PC20 CLK12 */
+	 {0, 1, 0, 0, 0, 1},		/* PC19 CLK13 */
+	 {1, 1, 0, 0, 0, 1},		/* PC18 CLK14 */
+	 {0, 1, 0, 0, 0, 0},		/* PC17 CLK15 */
+	 {1, 1, 0, 0, 0, 1},		/* PC16 CLK16 */
+	 {0, 1, 1, 0, 0, 0},		/* PC15 FCC1_TXADDR0 SLAVE */
+	 {0, 1, 1, 0, 0, 0},		/* PC14 FCC1_RXADDR0 SLAVE */
+	 {0, 1, 1, 0, 0, 0},		/* PC13 FCC1_TXADDR1 SLAVE */
+	 {0, 1, 1, 0, 0, 0},		/* PC12 FCC1_RXADDR1 SLAVE */
+	 {0, 0, 0, 1, 0, 0},		/* PC11 FCC2_RXD2 */
+	 {0, 0, 0, 1, 0, 0},		/* PC10 FCC2_RXD3 */
+	 {0, 0, 0, 1, 0, 1},		/* PC9  LTMODE */
+	 {0, 0, 0, 1, 0, 1},		/* PC8  SELSYNC */
+	 {0, 1, 1, 0, 0, 0},		/* PC7  FCC1_TXADDR2 SLAVE  */
+	 {0, 1, 1, 0, 0, 0},		/* PC6  FCC1_RXADDR2 SLAVE */
+	 {0, 0, 0, 1, 0, 0},		/* PC5  FCC2_TXCLAV MASTER */
+	 {0, 0, 0, 1, 0, 0},		/* PC4  FCC2_RXENB MASTER */
+	 {0, 0, 0, 1, 0, 0},		/* PC3  FCC2_TXD2 */
+	 {0, 0, 0, 1, 0, 0},		/* PC2  FCC2_TXD3 */
+	 {0, 0, 0, 0, 0, 1},		/* PC1  PTMC -PTEENB */
+	 {0, 0, 0, 1, 0, 1},		/* PC0  COMCLK_N */
+	 },
+	/* Port D configuration */
+	{							/* conf ppar psor pdir podr pdat */
+	 {0, 0, 0, 1, 0, 1},		/* PD31 -CAM_RST */
+	 {0, 0, 0, 1, 0, 0},		/* PD30 FCC2_TXENB */
+	 {0, 1, 1, 0, 0, 0},		/* PD29 FCC1_RXADDR3 SLAVE */
+	 {0, 1, 1, 0, 0, 1},		/* PD28 TDMC1_L1TXD */
+	 {0, 1, 1, 0, 0, 0},		/* PD27 TDMC1_L1RXD */
+	 {0, 1, 1, 0, 0, 1},		/* PD26 TDMC1_L1RSYNC */
+	 {0, 0, 0, 1, 0, 1},		/* PD25 LED0 -OFF */
+	 {0, 0, 0, 1, 0, 1},		/* PD24 LED5 -OFF */
+	 {1, 0, 0, 1, 0, 1},		/* PD23 -LXT971_RST */
+	 {0, 1, 1, 0, 0, 1},		/* PD22 TDMA2_L1TXD */
+	 {0, 1, 1, 0, 0, 0},		/* PD21 TDMA2_L1RXD */
+	 {0, 1, 1, 0, 0, 1},		/* PD20 TDMA2_L1RSYNC */
+	 {0, 0, 0, 1, 0, 0},		/* PD19 FCC2_TXADDR3 */
+	 {0, 0, 0, 1, 0, 0},		/* PD18 FCC2_RXADDR3 */
+	 {0, 1, 0, 1, 0, 0},		/* PD17 BRG2 */
+	 {0, 0, 0, 1, 0, 0},		/* PD16  */
+	 {0, 0, 0, 1, 0, 0},		/* PD15 PT2TO1 */
+	 {0, 0, 0, 1, 0, 1},		/* PD14 PT4TO3 */
+	 {0, 0, 0, 1, 0, 1},		/* PD13 -SWMODE */
+	 {0, 0, 0, 1, 0, 1},		/* PD12 -PTMODE */
+	 {0, 0, 0, 1, 0, 0},		/* PD11 FCC2_RXD0 */
+	 {0, 0, 0, 1, 0, 0},		/* PD10 FCC2_RXD1 */
+	 {1, 1, 0, 1, 0, 1},		/* PD9  SMC1_SMTXD */
+	 {1, 1, 0, 0, 0, 1},		/* PD8  SMC1_SMRXD */
+	 {0, 1, 1, 0, 0, 0},		/* PD7  FCC1_TXADDR3 SLAVE */
+	 {0, 0, 0, 1, 0, 0},		/* PD6  IMAMODE */
+	 {0, 0, 0, 0, 0, 0},		/* PD5  CONFIG2 */
+	 {0, 1, 0, 1, 0, 0},		/* PD4  BRG8 */
+	 {0, 0, 0, 0, 0, 0},		/* PD3  */
+	 {0, 0, 0, 0, 0, 0},		/* PD2  */
+	 {0, 0, 0, 0, 0, 0},		/* PD1  */
+	 {0, 0, 0, 0, 0, 0},		/* PD0  */
+	 }
+};
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar *base;
+	ulong maxsize;
+	int i;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	immap->im_siu_conf.sc_ppc_acr = 0x00000026;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_lcl_acr = 0x00000000;
+	immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
+	immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_tescr1 = 0x00004000;
+	immap->im_siu_conf.sc_ltescr1 = 0x00004000;
+
+	/* Init Main SDRAM */
+#define OP_VALUE   0x404A241A
+#define OP_VALUE_M (OP_VALUE & 0x87FFFFFF);
+	base = (uchar *) CFG_SDRAM_BASE;
+	memctl->memc_psdmr = 0x28000000 | OP_VALUE_M;
+	*base = 0xFF;
+	memctl->memc_psdmr = 0x08000000 | OP_VALUE_M;
+	for (i = 0; i < 8; i++)
+		*base = 0xFF;
+	memctl->memc_psdmr = 0x18000000 | OP_VALUE_M;
+	*(base + 0x110) = 0xFF;
+	memctl->memc_psdmr = OP_VALUE;
+	memctl->memc_lsdmr = 0x4086A522;
+	*base = 0xFF;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
+
+	maxsize = get_ram_size((long *)base, maxsize);
+
+	memctl->memc_or1 |= ~(maxsize - 1);
+
+	if (maxsize != hwc_main_sdram_size ())
+		printf ("Oops: memory test has not found all memory!\n");
+#endif
+
+	icache_enable ();
+	/* return total ram size of SDRAM */
+	return (maxsize);
+}
+
+int checkboard (void)
+{
+	char string[32];
+
+	hwc_manufact_date (string);
+
+	printf ("Board: Interphase 4539 (#%d %s)\n",
+		hwc_serial_number (),
+		string);
+
+#ifdef DEBUG
+	printf ("Manufacturing date: %s\n", string);
+	printf ("Serial number     : %d\n", hwc_serial_number ());
+	printf ("FLASH size        : %d MB\n", hwc_flash_size () >> 20);
+	printf ("Main SDRAM size   : %d MB\n", hwc_main_sdram_size () >> 20);
+	printf ("Local SDRAM size  : %d MB\n", hwc_local_sdram_size () >> 20);
+	hwc_mac_address (string);
+	printf ("MAC address       : %s\n", string);
+#endif
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	char *s, str[32];
+	int num;
+
+	if ((s = getenv ("serial#")) == NULL &&
+		(num = hwc_serial_number ()) != -1) {
+		sprintf (str, "%06d", num);
+		setenv ("serial#", str);
+	}
+	if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) {
+		setenv ("ethaddr", str);
+	}
+	return (0);
+}
+
+/***************************************************************
+ * We take some basic Hardware Configuration Parameter from the
+ * Serial EEPROM conected to the PSpan bridge. We keep it as
+ * simple as possible.
+ */
+int hwc_flash_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte >> 2) & 0x3) {
+		case 0x1:
+			return 0x0400000;
+			break;
+		case 0x2:
+			return 0x0800000;
+			break;
+		case 0x3:
+			return 0x1000000;
+		default:
+			return 0x0100000;
+		}
+	}
+	return -1;
+}
+int hwc_local_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte & 0x03)) {
+		case 0x1:
+			return 0x0800000;
+		case 0x2:
+			return 0x1000000;
+		default:
+			return 0;			/* not present */
+		}
+	}
+	return -1;
+}
+int hwc_main_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x41, &byte, sizeof (byte))) {
+		return 0x1000000 << ((byte >> 5) & 0x7);
+	}
+	return -1;
+}
+int hwc_serial_number (void)
+{
+	int sn = -1;
+
+	if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
+		sn = cpu_to_le32 (sn);
+	}
+	return sn;
+}
+int hwc_mac_address (char *str)
+{
+	char mac[6];
+
+	if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
+		sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n",
+				 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+	} else {
+		strcpy (str, "ERROR");
+		return -1;
+	}
+	return 0;
+}
+int hwc_manufact_date (char *str)
+{
+	uchar byte;
+	int value;
+
+	if (seeprom_read (0x92, &byte, sizeof (byte)))
+		goto out;
+	value = byte;
+	if (seeprom_read (0x93, &byte, sizeof (byte)))
+		goto out;
+	value += byte << 8;
+	sprintf (str, "%02d/%02d/%04d",
+			 value & 0x1F, (value >> 5) & 0xF,
+			 1980 + ((value >> 9) & 0x1FF));
+	return 0;
+
+  out:
+	strcpy (str, "ERROR");
+	return -1;
+}
+
+#define PSPAN_ADDR      0xF0020000
+#define EEPROM_REG      0x408
+#define EEPROM_READ_CMD 0xA000
+#define PSPAN_WRITE(a,v) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
+#define PSPAN_READ(a) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a)))
+
+int seeprom_read (int addr, uchar * data, int size)
+{
+	ulong val, cmd;
+	int i;
+
+	for (i = 0; i < size; i++) {
+
+		cmd = EEPROM_READ_CMD;
+		cmd |= ((addr + i) << 24) & 0xff000000;
+
+		/* Wait for ACT to authorize write */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Write command */
+		PSPAN_WRITE (EEPROM_REG, cmd);
+
+		/* Wait for data to be valid */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+		/* Do it twice, first read might be erratic */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Read error */
+		if (val & 0x00000040) {
+			return -1;
+		} else {
+			data[i] = (val >> 16) & 0xff;
+		}
+	}
+	return 0;
+}
diff --git a/board/iphase4539/u-boot.lds b/board/iphase4539/u-boot.lds
new file mode 100755
index 0000000..4ea01ea
--- /dev/null
+++ b/board/iphase4539/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ispan/Makefile b/board/ispan/Makefile
new file mode 100755
index 0000000..9123a80
--- /dev/null
+++ b/board/ispan/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ispan/config.mk b/board/ispan/config.mk
new file mode 100755
index 0000000..4600dbb
--- /dev/null
+++ b/board/ispan/config.mk
@@ -0,0 +1,29 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Interphase iSPAN Communications Controllers
+#
+#TEXT_BASE = 0xFF800000
+#TEXT_BASE = 0xFFBA0000
+TEXT_BASE = 0xFE7A0000
diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c
new file mode 100755
index 0000000..d39b8cd
--- /dev/null
+++ b/board/ispan/ispan.c
@@ -0,0 +1,464 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Interphase iSPAN Communications Controllers
+ * (453x and others). Tested on 4532.
+ *
+ * Derived from iSPAN 4539 port (iphase4539) by
+ * Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/io.h>
+
+/*
+ * I/O Ports configuration table
+ *
+ * If conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
+	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
+	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
+	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
+	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
+	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
+	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
+	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 SMTXD */
+	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 SMRXD */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7 */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5 */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4 */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3 */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2 */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0 */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_DV  */
+	/* PB16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_ER  */
+	/* PB15 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_ER  */
+	/* PB14 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_EN  */
+	/* PB13 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII COL    */
+	/* PB12 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII CRS    */
+	/* PB11 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[3] */
+	/* PB10 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[2] */
+	/* PB9  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[1] */
+	/* PB8  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[0] */
+	/* PB7  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[0] */
+	/* PB6  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[1] */
+	/* PB5  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[2] */
+	/* PB4  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[3] */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
+	/* PC22 */ { 0,          0,   0,   0,   0,   0 }, /* PC22 */
+	/* PC21 */ { 0,          0,   0,   0,   0,   0 }, /* PC21 */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
+	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19 */
+	/* PC18 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Rx Clock (CLK14) */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
+	/* PC16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Tx Clock (CLK16) */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
+	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
+	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8  */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7  */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6  */
+	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5  */
+	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4  */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3  */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2  */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1  */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }  /* PC0  */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 0,          0,   0,   0,   0,   0 }, /* PD31 */
+	/* PD30 */ { 0,          0,   0,   0,   0,   0 }, /* PD30 */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29 */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28 */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27 */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26 */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25 */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24 */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23 */
+	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22 */
+	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21 */
+	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20 */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19 */
+	/* PD18 */ { 0,          1,   1,   0,   0,   0 }, /* SPICLK  */
+	/* PD17 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMOSI */
+	/* PD16 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMISO */
+	/* PD15 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SDA */
+	/* PD14 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SCL */
+	/* PD13 */ { 1,          0,   0,   0,   0,   0 }, /* MII MDIO */
+	/* PD12 */ { 1,          0,   0,   1,   0,   0 }, /* MII MDC  */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11 */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10 */
+	/* PD9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 SMTXD */
+	/* PD8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 SMRXD */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7 */
+	/* PD6  */ { CFG_FCC3,   0,   0,   1,   0,   1 }, /* MII PHY Reset  */
+	/* PD5  */ { CFG_FCC3,   0,   0,   1,   0,   0 }, /* MII PHY Enable */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4 */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
+    }
+};
+
+#define PSPAN_ADDR      0xF0020000
+#define EEPROM_REG      0x408
+#define EEPROM_READ_CMD 0xA000
+#define PSPAN_WRITE(a,v) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
+#define PSPAN_READ(a) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a)))
+
+static int seeprom_read (int addr, uchar * data, int size)
+{
+	ulong val, cmd;
+	int i;
+
+	for (i = 0; i < size; i++) {
+
+		cmd = EEPROM_READ_CMD;
+		cmd |= ((addr + i) << 24) & 0xff000000;
+
+		/* Wait for ACT to authorize write */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Write command */
+		PSPAN_WRITE (EEPROM_REG, cmd);
+
+		/* Wait for data to be valid */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+		/* Do it twice, first read might be erratic */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Read error */
+		if (val & 0x00000040) {
+			return -1;
+		} else {
+			data[i] = (val >> 16) & 0xff;
+		}
+	}
+	return 0;
+}
+
+/***************************************************************
+ * We take some basic Hardware Configuration Parameter from the
+ * Serial EEPROM conected to the PSpan bridge. We keep it as
+ * simple as possible.
+ */
+#ifdef DEBUG
+static int hwc_flash_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte >> 2) & 0x3) {
+		case 0x1:
+			return 0x0400000;
+			break;
+		case 0x2:
+			return 0x0800000;
+			break;
+		case 0x3:
+			return 0x1000000;
+		default:
+			return 0x0100000;
+		}
+	}
+	return -1;
+}
+
+static int hwc_local_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte & 0x03)) {
+		case 0x1:
+			return 0x0800000;
+		case 0x2:
+			return 0x1000000;
+		default:
+			return 0;			/* not present */
+		}
+	}
+	return -1;
+}
+#endif	/* DEBUG */
+
+static int hwc_main_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x41, &byte, sizeof (byte))) {
+		return 0x1000000 << ((byte >> 5) & 0x7);
+	}
+	return -1;
+}
+
+static int hwc_serial_number (void)
+{
+	int sn = -1;
+
+	if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
+		sn = cpu_to_le32 (sn);
+	}
+	return sn;
+}
+
+static int hwc_mac_address (char *str)
+{
+	char mac[6];
+
+	if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
+		sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
+				 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+	} else {
+		strcpy (str, "ERROR");
+		return -1;
+	}
+	return 0;
+}
+
+static int hwc_manufact_date (char *str)
+{
+	uchar byte;
+	int value;
+
+	if (seeprom_read (0x92, &byte, sizeof (byte)))
+		goto out;
+	value = byte;
+	if (seeprom_read (0x93, &byte, sizeof (byte)))
+		goto out;
+	value += byte << 8;
+	sprintf (str, "%02d/%02d/%04d",
+			 value & 0x1F, (value >> 5) & 0xF,
+			 1980 + ((value >> 9) & 0x1FF));
+	return 0;
+
+out:
+	strcpy (str, "ERROR");
+	return -1;
+}
+
+static int hwc_board_type (char **str)
+{
+	ushort id = 0;
+
+	if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
+		switch (id) {
+		case 0x9080:
+			*str = "4532-002";
+			break;
+		case 0x9081:
+			*str = "4532-001";
+			break;
+		case 0x9082:
+			*str = "4532-000";
+			break;
+		default:
+			*str = "Unknown";
+		}
+	} else {
+		*str = "Unknown";
+	}
+
+	return id;
+}
+
+long int initdram (int board_type)
+{
+	long maxsize = hwc_main_sdram_size();
+
+#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE)
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar *base;
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x00000026;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_lcl_acr  = 0x00000000;
+	immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
+	immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+	immap->im_siu_conf.sc_ltescr1  = 0x00004000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	/* Initialise 60x bus SDRAM */
+	base = (uchar *)(CFG_SDRAM_BASE | 0x110);
+	memctl->memc_psrt  = CFG_PSRT;
+	memctl->memc_or1   = CFG_60x_OR;
+	memctl->memc_br1   = CFG_SDRAM_BASE | CFG_60x_BR;
+
+	memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
+	*base = 0xFF;
+	memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*base = 0xFF;
+	memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
+	*base = 0xFF;
+	memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
+
+	/* Initialise local bus SDRAM */
+	base = (uchar *)CFG_LSDRAM_BASE;
+	memctl->memc_lsrt  = CFG_LSRT;
+	memctl->memc_or2   = CFG_LOC_OR;
+	memctl->memc_br2   = CFG_LSDRAM_BASE | CFG_LOC_BR;
+
+	memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
+	*base = 0xFF;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*base = 0xFF;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
+	*base = 0xFF;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
+
+	maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
+
+	memctl->memc_or1 |= ~(maxsize - 1);
+
+	if (maxsize != hwc_main_sdram_size())
+		puts("Oops: memory test has not found all memory!\n");
+#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */
+
+	/* Return total RAM size (size of 60x SDRAM) */
+	return maxsize;
+}
+
+int checkboard(void)
+{
+	char string[32], *id;
+
+	hwc_manufact_date(string);
+	hwc_board_type(&id);
+	printf("Board: Interphase iSPAN %s (#%d %s)\n",
+	       id, hwc_serial_number(), string);
+#ifdef DEBUG
+	printf("Manufacturing date: %s\n", string);
+	printf("Serial number     : %d\n", hwc_serial_number());
+	printf("FLASH size        : %d MB\n", hwc_flash_size() >> 20);
+	printf("Main SDRAM size   : %d MB\n", hwc_main_sdram_size() >> 20);
+	printf("Local SDRAM size  : %d MB\n", hwc_local_sdram_size() >> 20);
+	hwc_mac_address(string);
+	printf("MAC address       : %s\n", string);
+#endif
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	char *s, str[32];
+	int num;
+
+	if ((s = getenv("serial#")) == NULL &&
+	    (num = hwc_serial_number()) != -1) {
+		sprintf(str, "%06d", num);
+		setenv("serial#", str);
+	}
+	if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
+		setenv("ethaddr", str);
+	}
+
+	return 0;
+}
diff --git a/board/ispan/u-boot.lds b/board/ispan/u-boot.lds
new file mode 100755
index 0000000..bf8048d
--- /dev/null
+++ b/board/ispan/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/ivm/Makefile b/board/ivm/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/ivm/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/ivm/config.mk b/board/ivm/config.mk
new file mode 100755
index 0000000..37e7185
--- /dev/null
+++ b/board/ivm/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IVM boards
+#
+
+TEXT_BASE = 0xFF000000
diff --git a/board/ivm/flash.c b/board/ivm/flash.c
new file mode 100755
index 0000000..140ba2d
--- /dev/null
+++ b/board/ivm/flash.c
@@ -0,0 +1,598 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \
+				BR_MS_GPCM | BR_PS_16 | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_MT:
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00020000);
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	    }
+	    return;
+
+	case FLASH_MAN_SST:
+	    for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base + (i * 0x00002000);
+	    }
+	    return;
+
+	case FLASH_MAN_AMD:
+	case FLASH_MAN_FUJ:
+
+	    /* set up sector start address table */
+	    if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	    } else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	    }
+	    return;
+	default:
+	    printf ("Don't know sector ofsets for flash type 0x%lx\n",
+		info->flash_id);
+	    return;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_SST200A:	printf ("39xF200A (2M = 128K x 16)\n");
+				break;
+	case FLASH_SST400A:	printf ("39xF400A (4M = 256K x 16)\n");
+				break;
+	case FLASH_SST800A:	printf ("39xF800A (8M = 512K x 16)\n");
+				break;
+	case FLASH_STM800AB:	printf ("M29W800AB (8M = 512K x 16)\n");
+				break;
+	case FLASH_28F008S5:	printf ("28F008S5 (1M = 64K x 16)\n");
+				break;
+	case FLASH_28F400_T:	printf ("28F400B3 (4Mbit, top boot sector)\n");
+				break;
+	case FLASH_28F400_B:	printf ("28F400B3 (4Mbit, bottom boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	ushort value;
+	vu_short *saddr = (vu_short *)addr;
+
+	/* Read Manufacturer ID */
+	saddr[0] = 0x0090;
+	value = saddr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (SST_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (STM_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (MT_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_MT;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		saddr[0] = 0x00FF;		/* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = saddr[1];			/* device ID		*/
+
+	switch (value) {
+	case (AMD_ID_LV400T & 0xFFFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & 0xFFFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & 0xFFFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & 0xFFFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV160T & 0xFFFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & 0xFFFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFFFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_LV320B & 0xFFFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	case (SST_ID_xF200A & 0xFFFF):
+		info->flash_id += FLASH_SST200A;
+		info->sector_count = 64;	/* 39xF200A ID ( 2M = 128K x 16	) */
+		info->size = 0x00080000;
+		break;
+	case (SST_ID_xF400A & 0xFFFF):
+		info->flash_id += FLASH_SST400A;
+		info->sector_count = 128;	/* 39xF400A ID ( 4M = 256K x 16	) */
+		info->size = 0x00100000;
+		break;
+	case (SST_ID_xF800A & 0xFFFF):
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 256;	/* 39xF800A ID ( 8M = 512K x 16	) */
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (STM_ID_x800AB & 0xFFFF):
+		info->flash_id += FLASH_STM800AB;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (MT_ID_28F400_T & 0xFFFF):
+		info->flash_id += FLASH_28F400_T;
+		info->sector_count = 7;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+	case (MT_ID_28F400_B & 0xFFFF):
+		info->flash_id += FLASH_28F400_B;
+		info->sector_count = 7;
+		info->size = 0x00080000;
+		break;				/* => 512 kB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		saddr[0] = 0x00FF;		/* restore read mode */
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	saddr[0] = 0x00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MT) {
+		printf ("Can erase only MT flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *)(info->start[sect]);
+			unsigned short status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = 0x0050;	/* clear status register */
+			*addr = 0x0020;	/* erase setup */
+			*addr = 0x00D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & 0x0080) != 0x0080) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0x00FF;	/* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = 0x00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	2	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower FLASH_WIDTH aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<FLASH_WIDTH && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		data = 0;
+		for (i=0; i<FLASH_WIDTH; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<FLASH_WIDTH; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_short *addr = (vu_short *)dest;
+	ushort sdata = (ushort)data;
+	ushort status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & sdata) != sdata) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = 0x0040;		/* write setup */
+	*addr = sdata;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & 0x0080) != 0x0080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0x00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0x00FF;		/* restore read mode */
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c
new file mode 100755
index 0000000..7927ea9
--- /dev/null
+++ b/board/ivm/ivm.c
@@ -0,0 +1,352 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+
+#ifdef CONFIG_STATUS_LED
+# include <status_led.h>
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/*
+ * 50 MHz SHARC access using UPM A
+ */
+const uint sharc_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
+	0xFFFFEC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
+	0xFFFFEC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+/*
+ * 50 MHz SDRAM access using UPM B
+ */
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45,	/* last */
+	_NOT_USED_,
+	/*
+	 * SDRAM Initialization (offset 5 in UPM RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
+	0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
+	0xE1BBBC04, 0x1FF77C45,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
+	0xFFFFFC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+#ifdef CONFIG_IVMS8
+	puts ("Board: IVMS8\n");
+#endif
+#ifdef CONFIG_IVML24
+	puts ("Board: IVM-L8/24\n");
+#endif
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	long int size_b0;
+
+	/* enable SDRAM clock ("switch on" SDRAM) */
+	immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE);	/* active output */
+	immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE;	/* output */
+	immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE;	/* assert SDRAM CLKE */
+	udelay (1);
+
+	/*
+	 * Map controller bank 1 for ELIC SACCO
+	 */
+	memctl->memc_or1 = CFG_OR1;
+	memctl->memc_br1 = CFG_BR1;
+
+	/*
+	 * Map controller bank 2 for ELIC EPIC
+	 */
+	memctl->memc_or2 = CFG_OR2;
+	memctl->memc_br2 = CFG_BR2;
+
+	/*
+	 * Configure UPMA for SHARC
+	 */
+	upmconfig (UPMA, (uint *) sharc_table,
+		   sizeof (sharc_table) / sizeof (uint));
+
+#if defined(CONFIG_IVML24)
+	/*
+	 * Map controller bank 4 for HDLC Address space
+	 */
+	memctl->memc_or4 = CFG_OR4;
+	memctl->memc_br4 = CFG_BR4;
+#endif
+
+	/*
+	 * Map controller bank 5 for SHARC
+	 */
+	memctl->memc_or5 = CFG_OR5;
+	memctl->memc_br5 = CFG_BR5;
+
+	memctl->memc_mamr = 0x00001000;
+
+	/*
+	 * Configure UPMB for SDRAM
+	 */
+	upmconfig (UPMB, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mbmr = CFG_MBMR_8COL;	/* refresh not enabled yet */
+
+	udelay (200);
+	memctl->memc_mcr = 0x80806105;	/* precharge */
+	udelay (1);
+	memctl->memc_mcr = 0x80806106;	/* load mode register */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;	/* autorefresh */
+
+	memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 */
+	size_b0 =
+		dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	memctl->memc_mbmr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy (void)
+{
+	immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/* De-assert Ethernet Powerdown */
+	immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN);	/* active output */
+	immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN;	/* output */
+	immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN);	/* Enable PHY power */
+	udelay (1000);
+
+	/*
+	 * RESET is implemented by a positive pulse of at least 1 us
+	 * at the reset pin.
+	 *
+	 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
+	 *
+	 * Note: The RESET pin is high active, but there is an
+	 *       inverter on the SPD823TS board...
+	 */
+	immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET);
+	immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET;
+	/* assert RESET signal of PHY */
+	immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET);
+	udelay (10);
+	/* de-assert RESET signal of PHY */
+	immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET;
+	udelay (10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void show_boot_progress (int status)
+{
+#if defined(CONFIG_STATUS_LED)
+# if defined(STATUS_LED_YELLOW)
+	status_led_set (STATUS_LED_YELLOW,
+			(status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
+# endif	/* STATUS_LED_YELLOW */
+# if defined(STATUS_LED_BOOT)
+	if (status == 6)
+		status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
+# endif	/* STATUS_LED_BOOT */
+#endif /* CONFIG_STATUS_LED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+void ide_set_reset (int on)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/*
+	 * Configure PC for IDE Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+	} else {		/* release RESET */
+		immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+	}
+
+	/* program port pin as GPIO output */
+	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
+	immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
+	immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds
new file mode 100755
index 0000000..fdeabc5
--- /dev/null
+++ b/board/ivm/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    common/environment.o(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug
new file mode 100755
index 0000000..3214f3f
--- /dev/null
+++ b/board/ivm/u-boot.lds.debug
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ixdp425/Makefile b/board/ixdp425/Makefile
new file mode 100755
index 0000000..e4282c4
--- /dev/null
+++ b/board/ixdp425/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ixdp425.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ixdp425/config.mk b/board/ixdp425/config.mk
new file mode 100755
index 0000000..9f616f3
--- /dev/null
+++ b/board/ixdp425/config.mk
@@ -0,0 +1,2 @@
+#TEXT_BASE = 0x00100000
+TEXT_BASE = 0x00f80000
diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c
new file mode 100755
index 0000000..1d958c8
--- /dev/null
+++ b/board/ixdp425/flash.c
@@ -0,0 +1,427 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               		x
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               		__swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID            */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c
new file mode 100755
index 0000000..c04626a
--- /dev/null
+++ b/board/ixdp425/ixdp425.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/ixp425.h>
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/* local prototypes */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+/**********************************************************/
+
+int board_post_init (void)
+{
+	return (0);
+}
+
+/**********************************************************/
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of IXDP */
+	gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	return 0;
+}
+
+/**********************************************************/
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+/**********************************************************/
+
+extern struct pci_controller hose;
+extern void pci_ixp_init(struct pci_controller * hose);
+
+void pci_init_board(void)
+{
+	extern void pci_ixp_init (struct pci_controller *hose);
+
+	pci_ixp_init(&hose);
+}
diff --git a/board/ixdp425/u-boot.lds b/board/ixdp425/u-boot.lds
new file mode 100755
index 0000000..e2ceac7
--- /dev/null
+++ b/board/ixdp425/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/ixp/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/jse/Makefile b/board/jse/Makefile
new file mode 100755
index 0000000..0da27b6
--- /dev/null
+++ b/board/jse/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright 2004 Picture Elements, Inc.
+# Stephen Williams <steve@icarus.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o sdram.o flash.o host_bridge.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/jse/README.txt b/board/jse/README.txt
new file mode 100755
index 0000000..84497db
--- /dev/null
+++ b/board/jse/README.txt
@@ -0,0 +1,48 @@
+JSE Configuration Details
+
+Memory Bank 0 -- Flash chip
+---------------------------
+
+0xfff00000 - 0xffffffff
+
+The flash chip is really only 512Kbytes, but the high address bit of
+the 1Meg region is ignored, so the flash is replicated through the
+region. Thus, this is consistent with a flash base address 0xfff80000.
+
+The placement at the end is to be consistent with reset behavior,
+where the processor itself initially uses this bus to load the branch
+vector and start running.
+
+On-Chip Memory
+--------------
+
+0xf4000000 - 0xf4000fff
+
+The 405GPr includes a 4K on-chip memory that can be placed however
+software chooses. I choose to place the memory at this address, to
+keep it out of the cachable areas.
+
+
+Memory Bank 1 -- SystemACE Controller
+-------------------------------------
+
+0xf0000000 - 0xf00fffff
+
+The SystemACE chip is along on peripheral bank CS#1. We don't need
+much space, but 1Meg is the smallest we can configure the chip to
+allocate. We need it far away from the flash region, because this
+region is set to be non-cached.
+
+
+Internal Peripherals
+--------------------
+
+0xef600300 - 0xef6008ff
+
+These are scattered various peripherals internal to the PPC405GPr
+chip.
+
+SDRAM
+-----
+
+0x00000000 - 0x07ffffff  (128 MBytes)
diff --git a/board/jse/config.mk b/board/jse/config.mk
new file mode 100755
index 0000000..03ec085
--- /dev/null
+++ b/board/jse/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2003 Picture Elements, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Picture Elements, Inc. JSE boards
+#
+
+TEXT_BASE = 0xFFF80000
diff --git a/board/jse/flash.c b/board/jse/flash.c
new file mode 100755
index 0000000..c462fe0
--- /dev/null
+++ b/board/jse/flash.c
@@ -0,0 +1,520 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#if CFG_MAX_FLASH_BANKS != 1
+#error "CFG_MAX_FLASH_BANKS must be 1"
+#endif
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#define ADDR0		0x5555
+#define ADDR1		0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+
+	/* Init: no FLASHes known */
+	flash_info[0].flash_id = FLASH_UNKNOWN;
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	/* Setup offsets */
+	flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+			      FLASH_BASE0_PRELIM,
+			      FLASH_BASE0_PRELIM + monitor_flash_len - 1,
+			      &flash_info[0]);
+	flash_info[0].size = size_b0;
+
+	return size_b0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+/*
+ * This implementation assumes that the flash chips are uniform sector
+ * devices. This is true for all likely JSE devices.
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	unsigned idx;
+	unsigned long sector_size = info->size / info->sector_count;
+
+	for (idx = 0; idx < info->sector_count; idx += 1) {
+		info->start[idx] = base + (idx * sector_size);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf ("ST Micro ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	  /* (Reduced table of only parts expected in JSE boards.) */
+	switch (info->flash_id) {
+	case FLASH_MAN_AMD | FLASH_AM040:
+		printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_MAN_STM | FLASH_AM040:
+		printf ("MM29W040W (512 Kbit, uniform sector size)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *) info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ", info->protect[i] ? "RO " : "   "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+
+	value = addr2[0];
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		printf("Unknown flash manufacturer code: 0x%x\n", value);
+		return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID		*/
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000; /* => 512 ko */
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	  /* Calculate the sector offsets (Use JSE Optimized code). */
+	flash_get_offsets(base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr =
+		(FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+			printf ("Erasing sector %p\n", addr2);	/* CLH */
+
+			if ((info->flash_id & FLASH_VENDMASK) ==
+			    FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay (1000);	/* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7 (info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7 (info, l_sect);
+
+DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 =
+		(FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	    (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/board/jse/host_bridge.c b/board/jse/host_bridge.c
new file mode 100755
index 0000000..363be97
--- /dev/null
+++ b/board/jse/host_bridge.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ident "$Id:$"
+
+# include  <common.h>
+# include  <pci.h>
+# include  "jse_priv.h"
+
+/*
+ * The JSE board has an Intel 21555 non-transparent bridge for
+ * communication with the host. We need to render it harmless on the
+ * JSE side, but leave it alone on the host (primary) side. Normally,
+ * this will all be done before the host BIOS can gain access to the
+ * board, due to the Primary Access Lockout bit.
+ *
+ * The host_bridge_init function is called as a late initialization
+ * function, after most of the board is set up, including a PCI scan.
+ */
+
+void host_bridge_init (void)
+{
+	/* The bridge chip is at a fixed location. */
+	pci_dev_t dev = PCI_BDF (0, 10, 0);
+
+	/* Set PCI Class code --
+	   The primary side sees this class code at 0x08 in the
+	   primary config space. This must be something other then a
+	   bridge, or MS Windows starts doing weird stuff to me. */
+	pci_write_config_dword (dev, 0x48, 0x04800000);
+
+	/* Set subsystem ID --
+	   The primary side sees this value at 0x2c. We set it here so
+	   that the host can tell what sort of device this is:
+	   We are a Picture Elements [0x12c5] JSE [0x008a]. */
+	pci_write_config_dword (dev, 0x6c, 0x008a12c5);
+
+	/* Downstream (Primary-to-Secondary) BARs are set up mostly
+	   off. We need only the Memory-0 Bar so that the host can get
+	   at the CSR region to set up tables and the lot. */
+
+	/* Downstream Memory 0 setup (4K for CSR) */
+	pci_write_config_dword (dev, 0xac, 0xfffff000);
+	/* Downstream Memory 1 setup (off) */
+	pci_write_config_dword (dev, 0xb0, 0x00000000);
+	/* Downstream Memory 2 setup (off) */
+	pci_write_config_dword (dev, 0xb4, 0x00000000);
+	/* Downstream Memory 3 setup (off) */
+	pci_write_config_dword (dev, 0xb8, 0x00000000);
+
+	/* Upstream (Secondary-to-Primary) BARs are used to get at
+	   host memory from the JSE card. Create two regions: a small
+	   one to manage individual word reads/writes, and a larger
+	   one for doing bulk frame moves. */
+
+	/* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
+	pci_write_config_dword (dev, 0xc4, 0xfffff000);
+	/* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
+	pci_write_config_dword (dev, 0xc8, 0xfffff000);
+
+	/* Upstream Memory 2 (BAR4) uses page translation, and is set
+	   up in CCR1. Configure for 4K pages. */
+
+	/* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
+	   bit as well, so we are done configuring after this
+	   point. Therefore, this must be the last step.
+
+	   CC1[15:12]= 0  (disable I2O message unit)
+	   CC1[11:8] = 0x5 (4K page size)
+	   CC0[11]   = 1  (Secondary Clock Disable: disable clock)
+	   CC0[10]   = 0  (Primary Access Lockout: allow primary access)
+	 */
+	pci_write_config_dword (dev, 0xcc, 0x05000800);
+}
diff --git a/board/jse/init.S b/board/jse/init.S
new file mode 100755
index 0000000..231cd1c
--- /dev/null
+++ b/board/jse/init.S
@@ -0,0 +1,105 @@
+/*------------------------------------------------------------------------+ */
+/* */
+/*       This source code has been made available to you by IBM on an AS-IS */
+/*       basis.  Anyone receiving this source is licensed under IBM */
+/*       copyrights to use it in any way he or she deems fit, including */
+/*       copying it, modifying it, compiling it, and redistributing it either */
+/*       with or without modifications.  No license under IBM patents or */
+/*       patent applications is to be implied by the copyright license. */
+/* */
+/*       Any user of this software should understand that IBM cannot provide */
+/*       technical support for this software and will not be responsible for */
+/*       any consequences resulting from the use of this software. */
+/* */
+/*       Any person who transfers this source code or any derivative work */
+/*       must include the IBM copyright notice, this paragraph, and the */
+/*       preceding two paragraphs in the transferred software. */
+/* */
+/*       COPYRIGHT   I B M   CORPORATION 1995 */
+/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
+/*------------------------------------------------------------------------- */
+
+/*------------------------------------------------------------------------- */
+/* Function:     ext_bus_cntlr_init */
+/* Description:  Initializes the External Bus Controller for the external */
+/*		peripherals. IMPORTANT: For pass1 this code must run from */
+/*		cache since you can not reliably change a peripheral banks */
+/*		timing register (pbxap) while running code from that bank. */
+/*		For ex., since we are running from ROM on bank 0, we can NOT */
+/*		execute the code that modifies bank 0 timings from ROM, so */
+/*		we run it from cache. */
+/*                                    */
+/*                                    */
+/* The layout for the PEI JSE board:  */
+/*	Bank 0 - Flash and SRAM       */
+/*	Bank 1 - SystemACE            */
+/*	Bank 2 - not used             */
+/*	Bank 3 - not used             */
+/*	Bank 4 - not used             */
+/*	Bank 5 - not used             */
+/*	Bank 6 - not used             */
+/*	Bank 7 - not used             */
+/*------------------------------------------------------------------------- */
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define cpc0_cr0 0xB1
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	mflr    r4                      /* save link register */
+	bl      ..getAddr
+..getAddr:
+	mflr    r3                      /* get address of ..getAddr */
+	mtlr    r4                      /* restore link register */
+	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
+	mtctr   r4                      /* 10 cache lines to fit this function */
+					/* in cache (gives us 8x10=80 instrctns) */
+..ebcloop:
+	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+	addi    r3,r3,32		/* move to next cache line */
+	bdnz    ..ebcloop               /* continue for 10 cache lines */
+
+	/*----------------------------------------------------------------- */
+	/* Delay to ensure all accesses to ROM are complete before changing */
+	/* bank 0 timings. 200usec should be enough. */
+	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+	/*----------------------------------------------------------------- */
+	addis	r3,0,0x0
+	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
+	mtctr   r3
+..spinlp:
+	bdnz    ..spinlp                /* spin loop */
+
+	/*----------------------------------------------------------------- */
+	/* Memory Bank 0 (Flash) initialization */
+	/*----------------------------------------------------------------- */
+
+	addi    r4,0,pb0ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,0x9B01
+	ori     r4,r4,0x5480
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	addis   r4,0,0xFFF1           /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
+	ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
+	mtdcr   ebccfgd,r4
+
+	blr
+
+
+/*----------------------------------------------------------------------- */
+/* Function:     sdram_init                                               */
+/* Description:  This function is called by cpu/ppc4xx/start.S code       */
+/*               to get the SDRAM initialized.                            */
+/*----------------------------------------------------------------------- */
+	.globl  sdram_init
+sdram_init:
+	blr
diff --git a/board/jse/jse.c b/board/jse/jse.c
new file mode 100755
index 0000000..9290814
--- /dev/null
+++ b/board/jse/jse.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+# include  <common.h>
+# include  <ppc4xx.h>
+# include  <asm/processor.h>
+# include  <asm/io.h>
+# include  "jse_priv.h"
+
+/*
+ * This function is run very early, out of flash, and before devices are
+ * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
+ * of being in the init_sequence array.
+ *
+ * The SDRAM has been initialized already -- start.S:start called
+ * init.S:init_sdram early on -- but it is not yet being used for
+ * anything, not even stack. So be careful.
+ */
+int board_early_init_f (void)
+{
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the JSE board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED/UNUSED
+   |       IRQ 25 (EXT IRQ 0) PCI SLOT 0; active low; level sensitive
+   |       IRQ 26 (EXT IRQ 1) PCI SLOT 1; active low; level sensitive
+   |       IRQ 27 (EXT IRQ 2) JP2C CHIP ; active low; level sensitive
+   |       IRQ 28 (EXT IRQ 3) PCI bridge; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) SystemACE IRQ; active high
+   |       IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
+   |       IRQ 31 (EXT IRQ 6) (unused)
+   +-------------------------------------------------------------------------*/
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF87);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	/* Configure the interface to the SystemACE MCU port.
+	   The SystemACE is fast, but there is no reason to have
+	   excessivly tight timings. So the settings are slightly
+	   generous. */
+
+	/* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1,
+	   WBN=0, WBF=1, TH=0,  RE=0,  SOR=0, BEM=0, PEN=0 */
+	mtdcr (ebccfga, pb1ap);
+	mtdcr (ebccfgd, 0x01011000);
+
+	/* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
+	mtdcr (ebccfga, pb1cr);
+	mtdcr (ebccfgd, CFG_SYSTEMACE_BASE | 0x00018000);
+
+	/* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
+	/* CPC0_CR1 |= PCIPW */
+	mtdcr (0xb2, mfdcr (0xb2) | 0x00004000);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_PRE_INIT
+int board_pre_init (void)
+{
+	return board_early_init_f ();
+}
+
+#endif
+
+/*
+ * This function is also called by lib_ppc/board.c:board_init_f (it is
+ * also in the init_sequence array) but later. Many more things are
+ * configured, but we are still running from flash.
+ */
+int checkboard (void)
+{
+	unsigned vers, status;
+
+	/* check that the SystemACE chip is alive. */
+	printf ("ACE:   ");
+	vers = readw (CFG_SYSTEMACE_BASE + 0x16);
+	printf ("SystemACE %u.%u (build %u)",
+		(vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
+
+	status = readl (CFG_SYSTEMACE_BASE + 0x04);
+#ifdef DEBUG
+	printf (" STATUS=0x%08x", status);
+#endif
+	/* If the flash card is present and there is an initial error,
+	   then force a restart of the program. */
+	if (status & 0x00000010) {
+		printf (" CFDETECT");
+
+		if (status & 0x04) {
+			/* CONTROLREG = CFGPROG */
+			writew (0x1000, CFG_SYSTEMACE_BASE + 0x18);
+			udelay (500);
+			/* CONTROLREG = CFGRESET */
+			writew (0x0080, CFG_SYSTEMACE_BASE + 0x18);
+			udelay (500);
+			writew (0x0000, CFG_SYSTEMACE_BASE + 0x18);
+			/* CONTROLREG = CFGSTART */
+			writew (0x0020, CFG_SYSTEMACE_BASE + 0x18);
+
+			status = readl (CFG_SYSTEMACE_BASE + 0x04);
+		}
+	}
+
+	/* Wait for the SystemACE to program its chain of devices. */
+	while ((status & 0x84) == 0x00) {
+		udelay (500);
+		status = readl (CFG_SYSTEMACE_BASE + 0x04);
+	}
+
+	if (status & 0x04)
+		printf (" CFG-ERROR");
+	if (status & 0x80)
+		printf (" CFGDONE");
+
+	printf ("\n");
+
+	/* Force /RTS to active. The board it not wired quite
+	   correctly to use cts/rtc flow control, so just force the
+	   /RST active and forget about it. */
+	writeb (readb (0xef600404) | 0x03, 0xef600404);
+
+	printf ("JSE:   ready\n");
+
+	return 0;
+}
+
+/* **** No more functions called by board_init_f. **** */
+
+/*
+ * This function is called by lib_ppc/board.c:board_init_r. At this
+ * point, basic setup is done, U-Boot has been moved into SDRAM and
+ * PCI has been set up. From here we done late setup.
+ */
+int misc_init_r (void)
+{
+	host_bridge_init ();
+	return 0;
+}
diff --git a/board/jse/jse_priv.h b/board/jse/jse_priv.h
new file mode 100755
index 0000000..ed4894b
--- /dev/null
+++ b/board/jse/jse_priv.h
@@ -0,0 +1,25 @@
+#ifndef __jse_priv_H
+#define __jse_prov_H
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+extern void host_bridge_init(void);
+
+#endif
diff --git a/board/jse/sdram.c b/board/jse/sdram.c
new file mode 100755
index 0000000..9060d97
--- /dev/null
+++ b/board/jse/sdram.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+# define SDRAM_LEN 0x08000000
+
+/*
+ * this is even after checkboard. It returns the size of the SDRAM
+ * that we have installed. This function is called by board_init_f
+ * in lib_ppc/board.c to initialize the memory and return what I
+ * found.
+ */
+long int initdram (int board_type)
+{
+	/* Configure the SDRAMS */
+
+	/* disable memory controller */
+	mtdcr (memcfga, mem_mcopt1);
+	mtdcr (memcfgd, 0x00000000);
+
+	udelay (500);
+
+	/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
+	mtdcr (memcfga, mem_besra);
+	mtdcr (memcfgd, 0xffffffff);
+
+	/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
+	mtdcr (memcfga, mem_besrb);
+	mtdcr (memcfgd, 0xffffffff);
+
+	/* Clear SDRAM0_ECCCFG (disable ECC) */
+	mtdcr (memcfga, mem_ecccf);
+	mtdcr (memcfgd, 0x00000000);
+
+	/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
+	mtdcr (memcfga, mem_eccerr);
+	mtdcr (memcfgd, 0xffffffff);
+
+	/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
+	mtdcr (memcfga, mem_sdtr1);
+	mtdcr (memcfgd, 0x010a4016);
+
+	/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
+	mtdcr (memcfga, mem_mb0cf);
+	mtdcr (memcfgd, 0x00084001);
+
+	/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
+	mtdcr (memcfga, mem_mb1cf);
+	mtdcr (memcfgd, 0x04084001);
+
+	/* Memory Bank 2 Config ==  BE=0 */
+	mtdcr (memcfga, mem_mb2cf);
+	mtdcr (memcfgd, 0x00000000);
+
+	/* Memory Bank 3 Config ==  BE=0 */
+	mtdcr (memcfga, mem_mb3cf);
+	mtdcr (memcfgd, 0x00000000);
+
+	/* refresh timer = 0x400  */
+	mtdcr (memcfga, mem_rtr);
+	mtdcr (memcfgd, 0x04000000);
+
+	/* Power management idle timer set to the default. */
+	mtdcr (memcfga, mem_pmit);
+	mtdcr (memcfgd, 0x07c00000);
+
+	udelay (500);
+
+	/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
+	mtdcr (memcfga, mem_mcopt1);
+	mtdcr (memcfgd, 0x80e00000);
+
+	return SDRAM_LEN;
+}
+
+/*
+ * The U-Boot core, as part of the initialization to prepare for
+ * loading the monitor into SDRAM, requests of this function that the
+ * memory be tested. Return 0 if the memory tests OK.
+ */
+int testdram (void)
+{
+	unsigned long idx;
+	unsigned val;
+	unsigned errors;
+	volatile unsigned long *sdram;
+
+#ifdef DEBUG
+	printf ("SDRAM Controller Registers --\n");
+
+	mtdcr (memcfga, mem_mcopt1);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_CFG   : 0x%08x\n", val);
+
+	mtdcr (memcfga, 0x24);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_STATUS: 0x%08x\n", val);
+
+	mtdcr (memcfga, mem_mb0cf);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_B0CR  : 0x%08x\n", val);
+
+	mtdcr (memcfga, mem_mb1cf);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_B1CR  : 0x%08x\n", val);
+
+	mtdcr (memcfga, mem_sdtr1);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_TR    : 0x%08x\n", val);
+
+	mtdcr (memcfga, mem_rtr);
+	val = mfdcr (memcfgd);
+	printf ("    SDRAM0_RTR   : 0x%08x\n", val);
+#endif
+
+	/* Wait for memory to be ready by testing MRSCMPbit
+	   bit. Really, there should already have been plenty of time,
+	   given it was started long ago. But, best to check. */
+	for (idx = 0; idx < 1000000; idx += 1) {
+		mtdcr (memcfga, 0x24);
+		val = mfdcr (memcfgd);
+		if (val & 0x80000000)
+			break;
+	}
+
+	if (!(val & 0x80000000)) {
+		printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
+		return 1;
+	}
+
+	/* Start memory test. */
+	printf ("test: %u MB - ", SDRAM_LEN / 1048576);
+
+	sdram = (unsigned long *) CFG_SDRAM_BASE;
+
+	printf ("write - ");
+	for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
+		sdram[idx + 0] = idx;
+		sdram[idx + 1] = ~idx;
+	}
+
+	printf ("read - ");
+	errors = 0;
+	for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
+		if (sdram[idx + 0] != idx)
+			errors += 1;
+		if (sdram[idx + 1] != ~idx)
+			errors += 1;
+		if (errors > 0)
+			break;
+	}
+
+	if (errors > 0) {
+		printf ("NOT OK\n");
+		printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
+			sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);
+		return 1;
+	}
+
+	printf ("ok\n");
+	return 0;
+}
diff --git a/board/jse/u-boot.lds b/board/jse/u-boot.lds
new file mode 100755
index 0000000..60c1115
--- /dev/null
+++ b/board/jse/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text          : {
+    /* The start.o file includes the initial jump vector that
+       must be located in the beginning. It is the basic run-
+       time function that calls all other functions. */
+    cpu/ppc4xx/start.o	(.text)
+
+    board/jse/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/kb9202/Makefile b/board/kb9202/Makefile
new file mode 100755
index 0000000..f36d88d
--- /dev/null
+++ b/board/kb9202/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Adapted for KwikByte KB920x boards - APR2005
+#
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= kb9202.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/kb9202/config.mk b/board/kb9202/config.mk
new file mode 100755
index 0000000..9ce161e
--- /dev/null
+++ b/board/kb9202/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000
diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c
new file mode 100755
index 0000000..4a7cf77
--- /dev/null
+++ b/board/kb9202/kb9202.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Adapted for KwikByte KB920x board from at91rm9200dk.c: 22APR2005
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <lxt971a.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void lowlevel_init(void) {
+	/* Required by assembly functions - do nothing	*/
+}
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	gd->bd->bi_arch_number = MACH_TYPE_KB9200;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac);
+UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac);
+UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac);
+UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status);
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = lxt972_InitPhy;
+	p_phyops->IsPhyConnected = lxt972_IsPhyConnected;
+	p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed;
+	p_phyops->AutoNegotiate = lxt972_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/board/kb9202/u-boot.lds b/board/kb9202/u-boot.lds
new file mode 100755
index 0000000..76df6b2
--- /dev/null
+++ b/board/kb9202/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/kup/Makefile b/board/kup/Makefile
new file mode 100755
index 0000000..071f0d2
--- /dev/null
+++ b/board/kup/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o kup.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/kup/common/flash.c b/board/kup/common/flash.c
new file mode 100755
index 0000000..903c88f
--- /dev/null
+++ b/board/kup/common/flash.c
@@ -0,0 +1,515 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef	CFG_ENV_ADDR
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+#define CONFIG_FLASH_16BIT
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	vu_short *s_addr=(vu_short*)addr;
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x0090;
+
+	value = s_addr[0];
+	value = value|(value<<16);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = s_addr[1];
+	value = value|(value<<16);
+
+		switch (value) {
+	case FUJI_ID_29F800BA:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	/* set sector offsets for bottom boot block type	*/
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00004000;
+	info->start[2] = base + 0x00006000;
+	info->start[3] = base + 0x00008000;
+	for (i = 4; i < info->sector_count; i++) {
+		info->start[i] = base + (i * 0x00010000) - 0x00030000;
+	}
+
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		s_addr = (volatile unsigned short *)(info->start[i]);
+		info->protect[i] = s_addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		s_addr = (volatile unsigned short *)info->start[0];
+		*s_addr = 0x00F0;	/* reset bank */
+	}
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect;
+	ulong start, now, last;
+#ifdef CONFIG_FLASH_16BIT
+	vu_short *s_addr = (vu_short*)addr;
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+/*#ifndef CONFIG_FLASH_16BIT
+	ulong type;
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_SST) && (type != FLASH_MAN_STM)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return;
+	}
+#endif*/
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+#ifdef CONFIG_FLASH_16BIT
+			vu_short *s_sect_addr = (vu_short*)(info->start[sect]);
+#else
+			vu_long	*sect_addr = (vu_long*)(info->start[sect]);
+#endif
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+#ifdef CONFIG_FLASH_16BIT
+
+			/*printf("\ns_sect_addr=%x",s_sect_addr);*/
+			s_addr[0x5555] = 0x00AA;
+			s_addr[0x2AAA] = 0x0055;
+			s_addr[0x5555] = 0x0080;
+			s_addr[0x5555] = 0x00AA;
+			s_addr[0x2AAA] = 0x0055;
+			s_sect_addr[0] = 0x0030;
+#else
+			addr[0x5555] = 0x00AA00AA;
+			addr[0x2AAA] = 0x00550055;
+			addr[0x5555] = 0x00800080;
+			addr[0x5555] = 0x00AA00AA;
+			addr[0x2AAA] = 0x00550055;
+			sect_addr[0] = 0x00300030;
+#endif
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+#ifdef CONFIG_FLASH_16BIT
+			while ((s_sect_addr[0] & 0x0080) != 0x0080) {
+#else
+			while ((sect_addr[0] & 0x00800080) != 0x00800080) {
+#endif
+				if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+		}
+	}
+
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#ifdef CONFIG_FLASH_16BIT
+	s_addr[0] = 0x00F0;	/* reset bank */
+#else
+	addr[0] = 0x00F000F0;	/* reset bank */
+#endif
+
+	printf (" done\n");
+	return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+
+#ifdef CONFIG_FLASH_16BIT
+	vu_short high_data;
+	vu_short low_data;
+	vu_short *s_addr = (vu_short*)addr;
+#endif
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+#ifdef CONFIG_FLASH_16BIT
+	/* Write the 16 higher-bits */
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	high_data = ((data>>16) & 0x0000ffff);
+
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x00A0;
+
+	*((vu_short *)dest) = high_data;
+
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+
+	/* Write the 16 lower-bits */
+#endif
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+#ifdef CONFIG_FLASH_16BIT
+	dest += 0x2;
+	low_data = (data & 0x0000ffff);
+
+	s_addr[0x5555] = 0x00AA;
+	s_addr[0x2AAA] = 0x0055;
+	s_addr[0x5555] = 0x00A0;
+	*((vu_short *)dest) = low_data;
+
+#else
+	addr[0x5555] = 0x00AA00AA;
+	addr[0x2AAA] = 0x00550055;
+	addr[0x5555] = 0x00A000A0;
+	*((vu_long *)dest) = data;
+#endif
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+#ifdef CONFIG_FLASH_16BIT
+	while ((*((vu_short *)dest) & 0x0080) != (low_data & 0x0080)) {
+#else
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+#endif
+
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c
new file mode 100755
index 0000000..d018e3c
--- /dev/null
+++ b/board/kup/common/kup.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2004
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "kup.h"
+
+int misc_init_f (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile sysconf8xx_t *siu = &immap->im_siu_conf;
+
+	while (siu->sc_sipend & 0x20000000) {
+		/* printf("waiting for 5V VCC\n"); */
+		;
+	}
+
+	/* RS232 / RS485 default is RS232 */
+	immap->im_ioport.iop_padat &= ~(PA_RS485);
+	immap->im_ioport.iop_papar &= ~(PA_RS485);
+	immap->im_ioport.iop_paodr &= ~(PA_RS485);
+	immap->im_ioport.iop_padir |= (PA_RS485);
+	return (0);
+}
+
+
+#ifdef CONFIG_IDE_LED
+void ide_led (uchar led, uchar status)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	/* We have one led for both pcmcia slots */
+	if (status) {		/* led on */
+		immap->im_ioport.iop_padat &= ~(PA_LED_YELLOW);
+	} else {
+		immap->im_ioport.iop_padat |= (PA_LED_YELLOW);
+	}
+}
+#endif
+
+void poweron_key (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1);
+	immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1);
+
+	if (immap->im_ioport.iop_pcdat & (PC_SWITCH1))
+		setenv ("key1", "off");
+	else
+		setenv ("key1", "on");
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed (void)
+{
+	return (0);
+}
+#endif
diff --git a/board/kup/common/kup.h b/board/kup/common/kup.h
new file mode 100755
index 0000000..70d7f01
--- /dev/null
+++ b/board/kup/common/kup.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2004
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __KUP_H
+#define __KUP_H
+
+#define PA_8       0x0080
+#define PA_11      0x0010
+#define PA_12      0x0008
+
+#define PB_14      0x00020000
+#define PB_17      0x00004000
+
+#define PC_9       0x0040
+
+#define PA_RS485                 PA_11   /* SCC1: 0=RS232 1=RS485 */
+#define PA_LED_YELLOW            PA_8
+#define BP_USB_VCC               PB_14   /* VCC for USB devices 0=vcc on, 1=vcc off*/
+#define PB_LCD_PWM	         PB_17	 /* PB 17 */
+#define PC_SWITCH1               PC_9    /* Reboot switch */
+
+extern void poweron_key (void);
+
+#endif	/* __KUP_H */
diff --git a/board/kup/common/load_sernum_ethaddr.c b/board/kup/common/load_sernum_ethaddr.c
new file mode 100755
index 0000000..b7b7499
--- /dev/null
+++ b/board/kup/common/load_sernum_ethaddr.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*-----------------------------------------------------------------------
+ * Process Hardware Information Block:
+ *
+ * If we boot on a system fresh from factory, check if the Hardware
+ * Information Block exists and save the information it contains.
+ *
+ * The KUP Hardware Information Block is defined as
+ * follows:
+ * - located in first flash bank
+ * - starts at offset CFG_HWINFO_OFFSET
+ * - size CFG_HWINFO_SIZE
+ *
+ * Internal structure:
+ * - sequence of ASCII character lines
+ * - fields separated by <CR><LF>
+ * - last field terminated by NUL character (0x00)
+ *
+ * Fields in Hardware Information Block:
+ * 1) Module Type
+ * 2) MAC Address
+ * 3) ....
+ */
+
+
+#define ETHADDR_TOKEN "ethaddr="
+#define LCD_TOKEN "lcd="
+
+void load_sernum_ethaddr (void)
+{
+	unsigned char *hwi;
+	char *var;
+	unsigned char hwi_stack[CFG_HWINFO_SIZE];
+	char *p;
+
+	hwi = (unsigned char *) (CFG_FLASH_BASE + CFG_HWINFO_OFFSET);
+	if (*((unsigned long *) hwi) != (unsigned long) CFG_HWINFO_MAGIC) {
+		printf ("HardwareInfo not found!\n");
+		return;
+	}
+	memcpy (hwi_stack, hwi, CFG_HWINFO_SIZE);
+
+	/*
+	 ** ethaddr
+	 */
+	var = strstr ((char *)hwi_stack, ETHADDR_TOKEN);
+	if (var) {
+		var += sizeof (ETHADDR_TOKEN) - 1;
+		p = strchr (var, '\r');
+		if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) {
+			*p = '\0';
+			setenv ("ethaddr", var);
+			*p = '\r';
+		}
+	}
+	/*
+	 ** lcd
+	 */
+	var = strstr ((char *)hwi_stack, LCD_TOKEN);
+	if (var) {
+		var += sizeof (LCD_TOKEN) - 1;
+		p = strchr (var, '\r');
+		if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) {
+			*p = '\0';
+			setenv ("lcd", var);
+			*p = '\r';
+		}
+	}
+}
diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile
new file mode 100755
index 0000000..62d289b
--- /dev/null
+++ b/board/kup/kup4k/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/kup/kup4k/config.mk b/board/kup/kup4k/config.mk
new file mode 100755
index 0000000..22e30b2
--- /dev/null
+++ b/board/kup/kup4k/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# KUP4K board
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c
new file mode 100755
index 0000000..e621c43
--- /dev/null
+++ b/board/kup/kup4k/kup4k.c
@@ -0,0 +1,459 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "../common/kup.h"
+#ifdef CONFIG_KUP4K_LOGO
+   #include "s1d13706.h"
+#endif
+
+#undef DEBUG
+#ifdef  DEBUG
+# define debugk(fmt,args...)    printf(fmt ,##args)
+#else
+# define debugk(fmt,args...)
+#endif
+
+typedef struct {
+	volatile unsigned char *VmemAddr;
+	volatile unsigned char *RegAddr;
+} FB_INFO_S1D13xxx;
+
+
+/* ------------------------------------------------------------------------- */
+
+#if 0
+static long int dram_size (long int, long int *, long int);
+#endif
+
+#ifdef CONFIG_KUP4K_LOGO
+void lcd_logo(bd_t *bd);
+#endif
+
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	uchar *latch,rev,mod;
+
+	/*
+	 * Init ChipSelect #4 (CAN + HW-Latch)
+	 */
+	immap->im_memctl.memc_or4 = 0xFFFF8926;
+	immap->im_memctl.memc_br4 = 0x90000401;
+	__asm__ ("eieio");
+	latch=(uchar *)0x90000200;
+	rev = (*latch & 0xF8) >> 3;
+	mod=(*latch & 0x03);
+	printf ("Board: KUP4K Rev %d.%d\n",rev,mod);
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0 = 0;
+	long int size_b1 = 0;
+	long int size_b2 = 0;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			 sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+/*	memctl->memc_or1 = CFG_OR1_PRELIM;	*/
+/*	memctl->memc_br1 = CFG_BR1_PRELIM;	*/
+
+/*	memctl->memc_or2 = CFG_OR2_PRELIM;	*/
+/*	memctl->memc_br2 = CFG_BR2_PRELIM;	*/
+
+
+	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002830;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 1 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 2 */
+	udelay (1);
+	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 2 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	udelay (1000);
+
+#if 0							/* 3 x 8MB */
+	size_b0 = 0x00800000;
+	size_b1 = 0x00800000;
+	size_b2 = 0x00800000;
+	memctl->memc_mptpr = CFG_MPTPR;
+	udelay (1000);
+	memctl->memc_or1 = 0xFF800A00;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_or2 = 0xFF000A00;
+	memctl->memc_br2 = 0x00800081;
+	memctl->memc_or3 = 0xFE000A00;
+	memctl->memc_br3 = 0x01000081;
+#else							/* 3 x 16 MB */
+	size_b0 = 0x01000000;
+	size_b1 = 0x01000000;
+	size_b2 = 0x01000000;
+	memctl->memc_mptpr = CFG_MPTPR;
+	udelay (1000);
+	memctl->memc_or1 = 0xFF000A00;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_or2 = 0xFE000A00;
+	memctl->memc_br2 = 0x01000081;
+	memctl->memc_or3 = 0xFC000A00;
+	memctl->memc_br3 = 0x02000081;
+#endif
+
+	udelay (10000);
+
+	return (size_b0 + size_b1 + size_b2);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+#if 0
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];				/* to make test non-destructive */
+	unsigned char i = 0;
+
+	memctl->memc_mamr = mamr_value;
+
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;		/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+#endif
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_STATUS_LED
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+#endif
+#ifdef CONFIG_KUP4K_LOGO
+	bd_t *bd = gd->bd;
+
+	lcd_logo (bd);
+#endif							/* CONFIG_KUP4K_LOGO */
+#ifdef CONFIG_IDE_LED
+	/* Configure PA8 as output port */
+	immap->im_ioport.iop_padir |= 0x80;
+	immap->im_ioport.iop_paodr |= 0x80;
+	immap->im_ioport.iop_papar &= ~0x80;
+	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
+#endif
+	setenv("hw","4k");
+	poweron_key();
+	return (0);
+}
+
+#ifdef CONFIG_KUP4K_LOGO
+
+
+void lcd_logo (bd_t * bd)
+{
+	FB_INFO_S1D13xxx fb_info;
+	S1D_INDEX s1dReg;
+	S1D_VALUE s1dValue;
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl;
+	ushort i;
+	uchar *fb;
+	int rs, gs, bs;
+	int r = 8, g = 8, b = 4;
+	int r1, g1, b1;
+	int n;
+	char tmp[64];		/* long enough for environment variables */
+	int tft = 0;
+
+	immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM);
+	immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM);
+	immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM);	/* set to 0 = enabled */
+	immr->im_cpm.cp_pbdir |= (PB_LCD_PWM);
+
+/*----------------------------------------------------------------------------- */
+/* Initialize the chip and the frame buffer driver. */
+/*----------------------------------------------------------------------------- */
+	memctl = &immr->im_memctl;
+
+
+	/*
+	 * Init ChipSelect #5 (S1D13768)
+	 */
+	memctl->memc_or5 = 0xFFC007F0;	/* 4 MB  17 WS or externel TA */
+	memctl->memc_br5 = 0x80080801;	/* Start at 0x80080000 */
+	__asm__ ("eieio");
+
+	fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
+	fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
+
+	if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
+	    || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
+		printf ("Warning:LCD Controller S1D13706 not found\n");
+		setenv ("lcd", "none");
+		return;
+	}
+
+
+	for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) {
+		s1dReg = aS1DRegs_prelimn[i].Index;
+		s1dValue = aS1DRegs_prelimn[i].Value;
+		debugk ("s13768 reg: %02x value: %02x\n",
+			aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value);
+		((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
+			s1dValue;
+	}
+
+
+	n = getenv_r ("lcd", tmp, sizeof (tmp));
+	if (n > 0) {
+		if (!strcmp ("tft", tmp))
+			tft = 1;
+		else
+			tft = 0;
+	}
+#if 0
+	if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04)
+		tft = 0;
+	else
+		tft = 1;
+#endif
+
+	debugk ("Port=0x%02x -> TFT=%d\n", tft,
+		((S1D_VALUE *) fb_info.RegAddr)[0xAC]);
+
+	/* init controller */
+	if (!tft) {
+		for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) {
+			s1dReg = aS1DRegs_stn[i].Index;
+			s1dValue = aS1DRegs_stn[i].Value;
+			debugk ("s13768 reg: %02x value: %02x\n",
+				aS1DRegs_stn[i].Index,
+				aS1DRegs_stn[i].Value);
+			((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] =
+				s1dValue;
+		}
+		n = getenv_r ("contrast", tmp, sizeof (tmp));
+		((S1D_VALUE *) fb_info.RegAddr)[0xB3] =
+			(n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0;
+		switch (bd->bi_busfreq) {
+		case 40000000:
+			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
+			break;
+		case 48000000:
+			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
+			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
+			break;
+		default:
+			printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
+		case 64000000:
+			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
+			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
+			break;
+		}
+		/*   setenv("lcd","stn"); */
+	} else {
+		for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) {
+			s1dReg = aS1DRegs_tft[i].Index;
+			s1dValue = aS1DRegs_tft[i].Value;
+			debugk ("s13768 reg: %02x value: %02x\n",
+				aS1DRegs_tft[i].Index,
+				aS1DRegs_tft[i].Value);
+			((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
+				s1dValue;
+		}
+
+		switch (bd->bi_busfreq) {
+		default:
+			printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq);
+		case 40000000:
+			((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42;
+			((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30;
+			break;
+		}
+		/* setenv("lcd","tft"); */
+	}
+
+	/* create and set colormap */
+	rs = 256 / (r - 1);
+	gs = 256 / (g - 1);
+	bs = 256 / (b - 1);
+	for (i = 0; i < 256; i++) {
+		r1 = (rs * ((i / (g * b)) % r)) * 255;
+		g1 = (gs * ((i / b) % g)) * 255;
+		b1 = (bs * ((i) % b)) * 255;
+		debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4);
+		S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
+				   (b1 >> 4));
+	}
+
+	/* copy bitmap */
+	fb = (uchar *) (fb_info.VmemAddr);
+	memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
+}
+#endif	/* CONFIG_KUP4K_LOGO */
diff --git a/board/kup/kup4k/s1d13706.h b/board/kup/kup4k/s1d13706.h
new file mode 100755
index 0000000..cd5eccc
--- /dev/null
+++ b/board/kup/kup4k/s1d13706.h
@@ -0,0 +1,174 @@
+/*---------------------------------------------------------------------------- */
+/* */
+/*  File generated by S1D13706CFG.EXE */
+/* */
+/*  Copyright (c) 2000,2001 Epson Research and Development, Inc. */
+/*  All rights reserved. */
+/* */
+/*---------------------------------------------------------------------------- */
+
+/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */
+
+#define S1D_DISPLAY_WIDTH           320
+#define S1D_DISPLAY_HEIGHT          240
+#define S1D_DISPLAY_BPP             8
+#define S1D_DISPLAY_SCANLINE_BYTES  320
+#define S1D_PHYSICAL_VMEM_ADDR      0x800A0000L
+#define S1D_PHYSICAL_VMEM_SIZE      0x14000L
+#define S1D_PHYSICAL_REG_ADDR       0x80080000L
+#define S1D_PHYSICAL_REG_SIZE       0x100
+#define S1D_DISPLAY_PCLK            6250
+#define S1D_PALETTE_SIZE            256
+#define S1D_REGDELAYOFF             0xFFFE
+#define S1D_REGDELAYON              0xFFFF
+
+#define S1D_WRITE_PALETTE(p,i,r,g,b)  \
+{  \
+    ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4);  \
+    ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4);  \
+    ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4);  \
+    ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
+}
+
+#define S1D_READ_PALETTE(p,i,r,g,b)  \
+{  \
+    ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
+    r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)];  \
+    g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)];  \
+    b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)];  \
+}
+
+typedef unsigned short S1D_INDEX;
+typedef unsigned char  S1D_VALUE;
+
+
+typedef struct
+{
+    S1D_INDEX Index;
+    S1D_VALUE Value;
+} S1D_REGS;
+
+
+static S1D_REGS aS1DRegs_prelimn[] =
+{
+    {0x10,0x00},   /* PANEL Type Register */
+    {0xA8,0x00},   /* GPIO Config Register 0 */
+    {0xA9,0x80},   /* GPIO Config Register 1 */
+
+};
+
+static S1D_REGS aS1DRegs_stn[] =
+{
+    {0x04,0x10},   /* BUSCLK MEMCLK Config Register */
+    {0x10,0xD0},   /* PANEL Type Register */
+    {0x11,0x00},   /* MOD Rate Register */
+    {0x14,0x27},   /* Horizontal Display Period Register */
+    {0x16,0x00},   /* Horizontal Display Period Start Pos Register 0 */
+    {0x17,0x00},   /* Horizontal Display Period Start Pos Register 1 */
+    {0x18,0xF0},   /* Vertical Total Register 0 */
+    {0x19,0x00},   /* Vertical Total Register 1 */
+    {0x1C,0xEF},   /* Vertical Display Period Register 0 */
+    {0x1D,0x00},   /* Vertical Display Period Register 1 */
+    {0x1E,0x00},   /* Vertical Display Period Start Pos Register 0 */
+    {0x1F,0x00},   /* Vertical Display Period Start Pos Register 1 */
+    {0x20,0x87},   /* Horizontal Sync Pulse Width Register */
+    {0x22,0x00},   /* Horizontal Sync Pulse Start Pos Register 0 */
+    {0x23,0x00},   /* Horizontal Sync Pulse Start Pos Register 1 */
+    {0x24,0x80},   /* Vertical Sync Pulse Width Register */
+    {0x26,0x01},   /* Vertical Sync Pulse Start Pos Register 0 */
+    {0x27,0x00},   /* Vertical Sync Pulse Start Pos Register 1 */
+    {0x70,0x83},   /* Display Mode Register */
+    {0x71,0x00},   /* Special Effects Register */
+    {0x74,0x00},   /* Main Window Display Start Address Register 0 */
+    {0x75,0x00},   /* Main Window Display Start Address Register 1 */
+    {0x76,0x00},   /* Main Window Display Start Address Register 2 */
+    {0x78,0x50},   /* Main Window Address Offset Register 0 */
+    {0x79,0x00},   /* Main Window Address Offset Register 1 */
+    {0x7C,0x00},   /* Sub Window Display Start Address Register 0 */
+    {0x7D,0x00},   /* Sub Window Display Start Address Register 1 */
+    {0x7E,0x00},   /* Sub Window Display Start Address Register 2 */
+    {0x80,0x50},   /* Sub Window Address Offset Register 0 */
+    {0x81,0x00},   /* Sub Window Address Offset Register 1 */
+    {0x84,0x00},   /* Sub Window X Start Pos Register 0 */
+    {0x85,0x00},   /* Sub Window X Start Pos Register 1 */
+    {0x88,0x00},   /* Sub Window Y Start Pos Register 0 */
+    {0x89,0x00},   /* Sub Window Y Start Pos Register 1 */
+    {0x8C,0x4F},   /* Sub Window X End Pos Register 0 */
+    {0x8D,0x00},   /* Sub Window X End Pos Register 1 */
+    {0x90,0xEF},   /* Sub Window Y End Pos Register 0 */
+    {0x91,0x00},   /* Sub Window Y End Pos Register 1 */
+    {0xA0,0x00},   /* Power Save Config Register */
+    {0xA1,0x00},   /* CPU Access Control Register */
+    {0xA2,0x00},   /* Software Reset Register */
+    {0xA3,0x00},   /* BIG Endian Support Register */
+    {0xA4,0x00},   /* Scratch Pad Register 0 */
+    {0xA5,0x00},   /* Scratch Pad Register 1 */
+    {0xA8,0x01},   /* GPIO Config Register 0 */
+    {0xA9,0x80},   /* GPIO Config Register 1 */
+    {0xAC,0x01},   /* GPIO Status Control Register 0 */
+    {0xAD,0x00},   /* GPIO Status Control Register 1 */
+    {0xB0,0x10},   /* PWM CV Clock Control Register */
+    {0xB1,0x80},   /* PWM CV Clock Config Register */
+    {0xB2,0x00},   /* CV Clock Burst Length Register */
+    {0xAD,0x80},   /* reset seq */
+    {0x70,0x03},
+};
+
+static S1D_REGS aS1DRegs_tft[] =
+{
+    {0x04,0x10},   /* BUSCLK MEMCLK Config Register */
+    {0x05,0x42},   /* PCLK Config  Register */
+    {0x10,0x61},   /* PANEL Type Register */
+    {0x11,0x00},   /* MOD Rate Register */
+    {0x12,0x30},   /* Horizontal Total Register */
+    {0x14,0x27},   /* Horizontal Display Period Register */
+    {0x16,0x11},   /* Horizontal Display Period Start Pos Register 0 */
+    {0x17,0x00},   /* Horizontal Display Period Start Pos Register 1 */
+    {0x18,0xFA},   /* Vertical Total Register 0 */
+    {0x19,0x00},   /* Vertical Total Register 1 */
+    {0x1C,0xEF},   /* Vertical Display Period Register 0 */
+    {0x1D,0x00},   /* Vertical Display Period Register 1 */
+    {0x1E,0x00},   /* Vertical Display Period Start Pos Register 0 */
+    {0x1F,0x00},   /* Vertical Display Period Start Pos Register 1 */
+    {0x20,0x07},   /* Horizontal Sync Pulse Width Register */
+    {0x22,0x00},   /* Horizontal Sync Pulse Start Pos Register 0 */
+    {0x23,0x00},   /* Horizontal Sync Pulse Start Pos Register 1 */
+    {0x24,0x00},   /* Vertical Sync Pulse Width Register */
+    {0x26,0x00},   /* Vertical Sync Pulse Start Pos Register 0 */
+    {0x27,0x00},   /* Vertical Sync Pulse Start Pos Register 1 */
+    {0x70,0x03},   /* Display Mode Register */
+    {0x71,0x00},   /* Special Effects Register */
+    {0x74,0x00},   /* Main Window Display Start Address Register 0 */
+    {0x75,0x00},   /* Main Window Display Start Address Register 1 */
+    {0x76,0x00},   /* Main Window Display Start Address Register 2 */
+    {0x78,0x50},   /* Main Window Address Offset Register 0 */
+    {0x79,0x00},   /* Main Window Address Offset Register 1 */
+    {0x7C,0x00},   /* Sub Window Display Start Address Register 0 */
+    {0x7D,0x00},   /* Sub Window Display Start Address Register 1 */
+    {0x7E,0x00},   /* Sub Window Display Start Address Register 2 */
+    {0x80,0x50},   /* Sub Window Address Offset Register 0 */
+    {0x81,0x00},   /* Sub Window Address Offset Register 1 */
+    {0x84,0x00},   /* Sub Window X Start Pos Register 0 */
+    {0x85,0x00},   /* Sub Window X Start Pos Register 1 */
+    {0x88,0x00},   /* Sub Window Y Start Pos Register 0 */
+    {0x89,0x00},   /* Sub Window Y Start Pos Register 1 */
+    {0x8C,0x4F},   /* Sub Window X End Pos Register 0 */
+    {0x8D,0x00},   /* Sub Window X End Pos Register 1 */
+    {0x90,0xEF},   /* Sub Window Y End Pos Register 0 */
+    {0x91,0x00},   /* Sub Window Y End Pos Register 1 */
+    {0xA0,0x00},   /* Power Save Config Register */
+    {0xA1,0x00},   /* CPU Access Control Register */
+    {0xA2,0x00},   /* Software Reset Register */
+    {0xA3,0x00},   /* BIG Endian Support Register */
+    {0xA4,0x00},   /* Scratch Pad Register 0 */
+    {0xA5,0x00},   /* Scratch Pad Register 1 */
+    {0xA8,0x01},   /* GPIO Config Register 0 */
+    {0xA9,0x80},   /* GPIO Config Register 1 */
+    {0xAC,0x01},   /* GPIO Status Control Register 0 */
+    {0xAD,0x00},   /* GPIO Status Control Register 1 */
+    {0xB0,0x10},   /* PWM CV Clock Control Register */
+    {0xB1,0x80},   /* PWM CV Clock Config Register */
+    {0xB2,0x00},   /* CV Clock Burst Length Register */
+    {0xAD,0x80},   /* reset seq */
+    {0x70,0x03},
+};
diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds
new file mode 100755
index 0000000..8625999
--- /dev/null
+++ b/board/kup/kup4k/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+/*
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug
new file mode 100755
index 0000000..c0cf1cb
--- /dev/null
+++ b/board/kup/kup4k/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile
new file mode 100755
index 0000000..62d289b
--- /dev/null
+++ b/board/kup/kup4x/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/kup/kup4x/config.mk b/board/kup/kup4x/config.mk
new file mode 100755
index 0000000..61d4e09
--- /dev/null
+++ b/board/kup/kup4x/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# KUP4X board
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c
new file mode 100755
index 0000000..cd9ed13
--- /dev/null
+++ b/board/kup/kup4x/kup4x.c
@@ -0,0 +1,312 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <post.h>
+#include "../common/kup.h"
+#ifdef CONFIG_KUP4K_LOGO
+/* #include "s1d13706.h" */
+#endif
+
+#define KUP4X_USB
+
+
+typedef struct {
+	volatile unsigned char *VmemAddr;
+	volatile unsigned char *RegAddr;
+} FB_INFO_S1D13xxx;
+
+/* ------------------------------------------------------------------------- */
+
+int usb_init_kup4x (void);
+
+
+#ifdef CONFIG_KUP4K_LOGO
+void lcd_logo (bd_t * bd);
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47,		/* last */
+
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile uchar *latch;
+	uchar rev, mod;
+
+	/*
+	 * Init ChipSelect #4 (CAN + HW-Latch)
+	 */
+	memctl->memc_or4 = 0xFFFF8926;
+	memctl->memc_br4 = 0x90000401;
+	__asm__ ("eieio");
+	latch = (volatile uchar *) 0x90000200;
+	rev = (*latch & 0xF8) >> 3;
+	mod = (*latch & 0x03);
+	printf ("Board: KUP4X Rev %d.%d\n",rev,mod);
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0 = 0;
+	long int size_b1 = 0;
+	long int size_b2 = 0;
+	long int size_b3 = 0;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+/*	memctl->memc_or1 = CFG_OR1_PRELIM;	*/
+/*	memctl->memc_br1 = CFG_BR1_PRELIM;	*/
+
+/*	memctl->memc_or2 = CFG_OR2_PRELIM;	*/
+/*	memctl->memc_br2 = CFG_BR2_PRELIM;	*/
+
+	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002830;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80002106;	/* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004830;	/* SDRAM bank 1 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80004106;	/* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 2 */
+	udelay (1);
+	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 2 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x80006106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mcr = 0x8000C105;	/* SDRAM bank 2 */
+	udelay (1);
+	memctl->memc_mcr = 0x8000C830;	/* SDRAM bank 2 - execute twice */
+	udelay (1);
+	memctl->memc_mcr = 0x8000C106;	/* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	udelay (1000);
+#if 0				/* 4 x 8MB */
+	size_b0 = 0x00800000;
+	size_b1 = 0x00800000;
+	size_b2 = 0x00800000;
+	size_b3 = 0x00800000;
+	memctl->memc_mptpr = CFG_MPTPR;
+	udelay (1000);
+	memctl->memc_or1 = 0xFF800A00;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_or2 = 0xFF000A00;
+	memctl->memc_br2 = 0x00800081;
+	memctl->memc_or3 = 0xFE000A00;
+	memctl->memc_br3 = 0x01000081;
+	memctl->memc_or6 = 0xFE000A00;
+	memctl->memc_br6 = 0x01800081;
+#else  /* 4 x 16 MB */
+	size_b0 = 0x01000000;
+	size_b1 = 0x01000000;
+	size_b2 = 0x01000000;
+	size_b3 = 0x01000000;
+	memctl->memc_mptpr = CFG_MPTPR;
+	udelay (1000);
+	memctl->memc_or1 = 0xFF000A00;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_or2 = 0xFE000A00;
+	memctl->memc_br2 = 0x01000081;
+	memctl->memc_or3 = 0xFD000A00;
+	memctl->memc_br3 = 0x02000081;
+	memctl->memc_or6 = 0xFC000A00;
+	memctl->memc_br6 = 0x03000081;
+#endif
+	udelay (10000);
+
+	return (size_b0 + size_b1 + size_b2 + size_b3);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+#if 0
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile long int *addr;
+	ulong cnt, val;
+	ulong save[32];		/* to make test non-destructive */
+	unsigned char i = 0;
+
+	memctl->memc_mamr = mamr_value;
+
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+#endif
+
+int misc_init_r (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+#ifdef CONFIG_IDE_LED
+	/* Configure PA8 as output port */
+	immap->im_ioport.iop_padir |= 0x80;
+	immap->im_ioport.iop_paodr |= 0x80;
+	immap->im_ioport.iop_papar &= ~0x80;
+	immap->im_ioport.iop_padat |= 0x80;	/* turn it off */
+#endif
+#ifdef KUP4X_USB
+	usb_init_kup4x ();
+#endif
+	setenv ("hw", "4x");
+	poweron_key ();
+	return (0);
+}
diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds
new file mode 100755
index 0000000..8625999
--- /dev/null
+++ b/board/kup/kup4x/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+/*
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug
new file mode 100755
index 0000000..c0cf1cb
--- /dev/null
+++ b/board/kup/kup4x/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/lantec/Makefile b/board/lantec/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/lantec/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/lantec/config.mk b/board/lantec/config.mk
new file mode 100755
index 0000000..05ea3b9
--- /dev/null
+++ b/board/lantec/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Lantec board (based on TQM8xxL config).
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/lantec/flash.c b/board/lantec/flash.c
new file mode 100755
index 0000000..0faa82c
--- /dev/null
+++ b/board/lantec/flash.c
@@ -0,0 +1,625 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Derived from ../tqm8xx/flash.c
+ * [Torsten Stevens, FHG IMS; Bruno Achauer, Exet AG]
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE5_PRELIM);
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE5_PRELIM, &flash_info[1]);
+
+	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	DEBUGF ("## Before remap: "
+		"BR0: 0x%08x    OR0: 0x%08x    "
+		"BR1: 0x%08x    OR1: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0,
+		memctl->memc_br1, memctl->memc_or1);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \
+				BR_MS_GPCM | BR_PS_32 | BR_V;
+
+	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or5 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br5 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_PS_32 | BR_V;
+
+		DEBUGF("## BR5: 0x%08x    OR5: 0x%08x\n",
+			memctl->memc_br5, memctl->memc_or5);
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_info[1].size = size_b1;
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br5 = 0;		/* invalidate bank */
+		memctl->memc_or5 = 0;		/* invalidate bank */
+
+		DEBUGF("## DISABLE BR5: 0x%08x    OR5: 0x%08x\n",
+			memctl->memc_br5, memctl->memc_or5);
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+		flash_info[1].size = 0;
+	}
+
+	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c
new file mode 100755
index 0000000..417dbbb
--- /dev/null
+++ b/board/lantec/lantec.c
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2001
+ * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
+ * Bruno Achauer, Exet AG, bruno@exet-ag.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Derived from ../tqm8xx/tqm8xx.c
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1ff77c35, 0xefeabc34, 0x1fb57c35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, 0xfffffc07,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7ffffc07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Return 1 for "L" type, 0 else.
+ */
+
+int checkboard (void)
+{
+	printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0;
+	int i;
+
+	/*
+	 * Configure UPMA for SDRAM
+	 */
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ;
+
+	/* burst length=4, burst type=sequential, CAS latency=2 */
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	/* initialize memory address register */
+	memctl->memc_mamr = CFG_MAMR_8COL;	/* refresh not enabled yet */
+
+	/* mode initialization (offset 5) */
+	udelay (200);		/* 0x80006105 */
+	memctl->memc_mcr =
+		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
+
+	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+	udelay (1);		/* 0x80006130 */
+	memctl->memc_mcr =
+		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+	udelay (1);		/* 0x80006130 */
+	memctl->memc_mcr =
+		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+
+	udelay (1);		/* 0x80006106 */
+	memctl->memc_mcr =
+		MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
+
+	udelay (200);
+
+	/* Need at least 10 DRAM accesses to stabilize */
+	for (i = 0; i < 10; ++i) {
+		volatile unsigned long *addr =
+			(volatile unsigned long *) SDRAM_BASE3_PRELIM;
+		unsigned long val;
+
+		val = *(addr + i);
+		*(addr + i) = val;
+	}
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 */
+	size_b0 = dram_size (CFG_MAMR_8COL,
+			     (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+	memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	udelay (1000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds
new file mode 100755
index 0000000..29ecabd
--- /dev/null
+++ b/board/lantec/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug
new file mode 100755
index 0000000..65b25b9
--- /dev/null
+++ b/board/lantec/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/lart/Makefile b/board/lart/Makefile
new file mode 100755
index 0000000..550aa1d
--- /dev/null
+++ b/board/lart/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= lart.o flash.o
+SOBJS	:= flashasm.o lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/lart/config.mk b/board/lart/config.mk
new file mode 100755
index 0000000..3033c4f
--- /dev/null
+++ b/board/lart/config.mk
@@ -0,0 +1,23 @@
+#
+# LART board with SA1100 cpu
+#
+# see http://www.lart.tudelft.nl/ for more information on LART
+#
+
+#
+# LART has 4 banks of 8 MB DRAM
+#
+# c000'0000
+# c100'0000
+# c800'0000
+# c900'0000
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to c178'0000, the upper 1 MB of second bank
+#
+# download areas is c800'0000
+#
+
+
+TEXT_BASE = 0xc1780000
diff --git a/board/lart/flash.c b/board/lart/flash.c
new file mode 100755
index 0000000..5232ed2
--- /dev/null
+++ b/board/lart/flash.c
@@ -0,0 +1,474 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush(void);
+
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x20000
+#define PARAM_SECT_SIZE 0x4000
+
+/* puzzle magic for lart
+ * data_*_flash are def'd in flashasm.S
+ */
+
+extern u32 data_from_flash(u32);
+extern u32 data_to_flash(u32);
+
+#define PUZZLE_FROM_FLASH(x)	data_from_flash((x))
+#define PUZZLE_TO_FLASH(x)	data_to_flash((x))
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00FF00FF
+#define CMD_IDENTIFY		0x00900090
+#define CMD_ERASE_SETUP		0x00200020
+#define CMD_ERASE_CONFIRM	0x00D000D0
+#define CMD_PROGRAM		0x00400040
+#define CMD_RESUME		0x00D000D0
+#define CMD_SUSPEND		0x00B000B0
+#define CMD_STATUS_READ		0x00700070
+#define CMD_STATUS_RESET	0x00500050
+
+#define BIT_BUSY		0x00800080
+#define BIT_ERASE_SUSPEND	0x00400040
+#define BIT_ERASE_ERROR		0x00200020
+#define BIT_PROGRAM_ERROR	0x00100010
+#define BIT_VPP_RANGE_ERROR	0x00080008
+#define BIT_PROGRAM_SUSPEND	0x00040004
+#define BIT_PROTECT_ERROR	0x00020002
+#define BIT_UNDEFINED		0x00010001
+
+#define BIT_SEQUENCE_ERROR	0x00300030
+#define BIT_TIMEOUT		0x80000000
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(void)
+{
+    int i, j;
+    ulong size = 0;
+
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    {
+	ulong flashbase = 0;
+	flash_info[i].flash_id =
+	  (INTEL_MANUFACT & FLASH_VENDMASK) |
+	  (INTEL_ID_28F160F3B & FLASH_TYPEMASK);
+	flash_info[i].size = FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	if (i == 0)
+	  flashbase = PHYS_FLASH_1;
+	else
+	  panic("configured too many flash banks!\n");
+	for (j = 0; j < flash_info[i].sector_count; j++)
+	{
+	    if (j <= 7)
+	    {
+		flash_info[i].start[j] = flashbase + j * PARAM_SECT_SIZE;
+	    }
+	    else
+	    {
+		flash_info[i].start[j] = flashbase + (j - 7)*MAIN_SECT_SIZE;
+	    }
+	}
+	size += flash_info[i].size;
+    }
+
+    /* Protect monitor and environment sectors
+     */
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_FLASH_BASE,
+		  CFG_FLASH_BASE + monitor_flash_len - 1,
+		  &flash_info[0]);
+
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_ENV_ADDR,
+		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		  &flash_info[0]);
+
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    switch (info->flash_id & FLASH_VENDMASK)
+    {
+    case (INTEL_MANUFACT & FLASH_VENDMASK):
+	printf("Intel: ");
+	break;
+    default:
+	printf("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK)
+    {
+    case (INTEL_ID_28F160F3B & FLASH_TYPEMASK):
+	printf("2x 28F160F3B (16Mbit)\n");
+	break;
+    default:
+	printf("Unknown Chip Type\n");
+	goto Done;
+	break;
+    }
+
+    printf("  Size: %ld MB in %d Sectors\n",
+	   info->size >> 20, info->sector_count);
+
+    printf("  Sector Start Addresses:");
+    for (i = 0; i < info->sector_count; i++)
+    {
+	if ((i % 5) == 0)
+	{
+	    printf ("\n   ");
+	}
+	printf (" %08lX%s", info->start[i],
+		info->protect[i] ? " (RO)" : "     ");
+    }
+    printf ("\n");
+
+Done:
+    ;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_error (ulong code)
+{
+	/* Check bit patterns */
+	/* SR.7=0 is busy, SR.7=1 is ready */
+	/* all other flags indicate error on 1 */
+	/* SR.0 is undefined */
+	/* Timeout is our faked flag */
+
+	/* sequence is described in Intel 290644-005 document */
+
+	/* check Timeout */
+	if (code & BIT_TIMEOUT)
+	{
+		printf ("Timeout\n");
+		return ERR_TIMOUT;
+	}
+
+	/* check Busy, SR.7 */
+	if (~code & BIT_BUSY)
+	{
+		printf ("Busy\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Vpp low, SR.3 */
+	if (code & BIT_VPP_RANGE_ERROR)
+	{
+		printf ("Vpp range error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Device Protect Error, SR.1 */
+	if (code & BIT_PROTECT_ERROR)
+	{
+		printf ("Device protect error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Command Seq Error, SR.4 & SR.5 */
+	if (code & BIT_SEQUENCE_ERROR)
+	{
+		printf ("Command seqence error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Error, SR.5 */
+	if (code & BIT_ERASE_ERROR)
+	{
+		printf ("Block erase error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Error, SR.4 */
+	if (code & BIT_PROGRAM_ERROR)
+	{
+		printf ("Program error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Suspended, SR.6 */
+	if (code & BIT_ERASE_SUSPEND)
+	{
+		printf ("Block erase suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Suspended, SR.2 */
+	if (code & BIT_PROGRAM_SUSPEND)
+	{
+		printf ("Program suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* OK, no error */
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    ulong result;
+    int iflag, cflag, prot, sect;
+    int rc = ERR_OK;
+
+    /* first look for protection bits */
+
+    if (info->flash_id == FLASH_UNKNOWN)
+	return ERR_UNKNOWN_FLASH_TYPE;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	return ERR_INVAL;
+    }
+
+    if ((info->flash_id & FLASH_VENDMASK) !=
+	(INTEL_MANUFACT & FLASH_VENDMASK)) {
+	return ERR_UNKNOWN_FLASH_VENDOR;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+    if (prot)
+	return ERR_PROTECTED;
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
+    {
+	printf("Erasing sector %2d ... ", sect);
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	if (info->protect[sect] == 0)
+	{	/* not protected */
+	    vu_long *addr = (vu_long *)(info->start[sect]);
+
+	    *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET);
+	    *addr = PUZZLE_TO_FLASH(CMD_ERASE_SETUP);
+	    *addr = PUZZLE_TO_FLASH(CMD_ERASE_CONFIRM);
+
+	    /* wait until flash is ready */
+	    do
+	    {
+		/* check timeout */
+		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+		{
+		    *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
+		    result = BIT_TIMEOUT;
+		    break;
+		}
+
+		result = PUZZLE_FROM_FLASH(*addr);
+	    }  while (~result & BIT_BUSY);
+
+	    *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+
+	    if ((rc = flash_error(result)) != ERR_OK)
+		goto outahere;
+
+	    printf("ok.\n");
+	}
+	else /* it was protected */
+	{
+	    printf("protected!\n");
+	}
+    }
+
+    if (ctrlc())
+      printf("User Interrupt!\n");
+
+outahere:
+    /* allow flash to settle - wait 10 ms */
+    udelay_masked(10000);
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long *)dest;
+    ulong result;
+    int rc = ERR_OK;
+    int cflag, iflag;
+
+    /* Check if Flash is (sufficiently) erased
+     */
+    result = PUZZLE_FROM_FLASH(*addr);
+    if ((result & data) != data)
+	return ERR_NOT_ERASED;
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    *addr = PUZZLE_TO_FLASH(CMD_STATUS_RESET);
+    *addr = PUZZLE_TO_FLASH(CMD_PROGRAM);
+    *addr = data;
+
+    /* arm simple, non interrupt dependent timer */
+    reset_timer_masked();
+
+    /* wait until flash is ready */
+    do
+    {
+	/* check timeout */
+	if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+	{
+	    *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
+	    result = BIT_TIMEOUT;
+	    break;
+	}
+
+	result = PUZZLE_FROM_FLASH(*addr);
+    }  while (~result & BIT_BUSY);
+
+    *addr = PUZZLE_TO_FLASH(CMD_READ_ARRAY);
+
+    rc = flash_error(result);
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int l;
+    int i, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data >> 8) | (*src++ << 24);
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = *((vu_long*)src);
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	src += 4;
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return ERR_OK;
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data >> 8) | (*src++ << 24);
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data >> 8) | (*(uchar *)cp << 24);
+    }
+
+    return write_word(info, wp, data);
+}
diff --git a/board/lart/flashasm.S b/board/lart/flashasm.S
new file mode 100755
index 0000000..9021972
--- /dev/null
+++ b/board/lart/flashasm.S
@@ -0,0 +1,177 @@
+/*
+ * flashasm.S: flash magic for LART
+ *
+ * Copyright (C) 1999 2000 2001 Jan-Derk bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+.text
+
+
+.globl	data_to_flash
+.globl	data_from_flash
+	/* Subroutine that takes data in r0 and formats it so it will be in */
+	/* the correct order for the internal flash */
+	/* used for LART only */
+data_to_flash:
+	mov	r1, #0x0
+
+	tst	r0, #0x00000001
+	orrne	r1, r1, #0x00001000
+	tst	r0, #0x00000002
+	orrne	r1, r1, #0x00004000
+	tst	r0, #0x00000004
+	orrne	r1, r1, #0x00000800
+	tst	r0, #0x00000008
+	orrne	r1, r1, #0x00000200
+	tst	r0, #0x00000010
+	orrne	r1, r1, #0x00000001
+	tst	r0, #0x00000020
+	orrne	r1, r1, #0x00000004
+	tst	r0, #0x00000040
+	orrne	r1, r1, #0x00000080
+	tst	r0, #0x00000080
+	orrne	r1, r1, #0x00000020
+
+	tst	r0, #0x00000100
+	orrne	r1, r1, #0x00002000
+	tst	r0, #0x00000200
+	orrne	r1, r1, #0x00008000
+	tst	r0, #0x00000400
+	orrne	r1, r1, #0x00000400
+	tst	r0, #0x00000800
+	orrne	r1, r1, #0x00000100
+	tst	r0, #0x00001000
+	orrne	r1, r1, #0x00000002
+	tst	r0, #0x00002000
+	orrne	r1, r1, #0x00000008
+	tst	r0, #0x00004000
+	orrne	r1, r1, #0x00000040
+	tst	r0, #0x00008000
+	orrne	r1, r1, #0x00000010
+
+	tst	r0, #0x00010000
+	orrne	r1, r1, #0x00100000
+	tst	r0, #0x00020000
+	orrne	r1, r1, #0x00400000
+	tst	r0, #0x00040000
+	orrne	r1, r1, #0x00080000
+	tst	r0, #0x00080000
+	orrne	r1, r1, #0x00020000
+	tst	r0, #0x00100000
+	orrne	r1, r1, #0x01000000
+	tst	r0, #0x00200000
+	orrne	r1, r1, #0x04000000
+	tst	r0, #0x00400000
+	orrne	r1, r1, #0x80000000
+	tst	r0, #0x00800000
+	orrne	r1, r1, #0x20000000
+
+	tst	r0, #0x01000000
+	orrne	r1, r1, #0x00200000
+	tst	r0, #0x02000000
+	orrne	r1, r1, #0x00800000
+	tst	r0, #0x04000000
+	orrne	r1, r1, #0x00040000
+	tst	r0, #0x08000000
+	orrne	r1, r1, #0x00010000
+	tst	r0, #0x10000000
+	orrne	r1, r1, #0x02000000
+	tst	r0, #0x20000000
+	orrne	r1, r1, #0x08000000
+	tst	r0, #0x40000000
+	orrne	r1, r1, #0x40000000
+	tst	r0, #0x80000000
+	orrne	r1, r1, #0x10000000
+
+	mov	r0, r1
+	mov	pc, lr
+
+	/* Takes data received from the flash, and unshuffles it. */
+data_from_flash:
+	mov	r1, #0x00
+
+	tst	r0, #0x00000001
+	orrne	r1, r1, #0x00000010
+	tst	r0, #0x00000002
+	orrne	r1, r1, #0x00001000
+	tst	r0, #0x00000004
+	orrne	r1, r1, #0x00000020
+	tst	r0, #0x00000008
+	orrne	r1, r1, #0x00002000
+	tst	r0, #0x00000010
+	orrne	r1, r1, #0x00008000
+	tst	r0, #0x00000020
+	orrne	r1, r1, #0x00000080
+	tst	r0, #0x00000040
+	orrne	r1, r1, #0x00004000
+	tst	r0, #0x00000080
+	orrne	r1, r1, #0x00000040
+
+	tst	r0, #0x00000100
+	orrne	r1, r1, #0x00000800
+	tst	r0, #0x00000200
+	orrne	r1, r1, #0x00000008
+	tst	r0, #0x00000400
+	orrne	r1, r1, #0x00000400
+	tst	r0, #0x00000800
+	orrne	r1, r1, #0x00000004
+	tst	r0, #0x00001000
+	orrne	r1, r1, #0x00000001
+	tst	r0, #0x00002000
+	orrne	r1, r1, #0x00000100
+	tst	r0, #0x00004000
+	orrne	r1, r1, #0x00000002
+	tst	r0, #0x00008000
+	orrne	r1, r1, #0x00000200
+
+	tst	r0, #0x00010000
+	orrne	r1, r1, #0x08000000
+	tst	r0, #0x00020000
+	orrne	r1, r1, #0x00080000
+	tst	r0, #0x00040000
+	orrne	r1, r1, #0x04000000
+	tst	r0, #0x00080000
+	orrne	r1, r1, #0x00040000
+	tst	r0, #0x00100000
+	orrne	r1, r1, #0x00010000
+	tst	r0, #0x00200000
+	orrne	r1, r1, #0x01000000
+	tst	r0, #0x00400000
+	orrne	r1, r1, #0x00020000
+	tst	r0, #0x00800000
+	orrne	r1, r1, #0x02000000
+
+	tst	r0, #0x01000000
+	orrne	r1, r1, #0x00100000
+	tst	r0, #0x02000000
+	orrne	r1, r1, #0x10000000
+	tst	r0, #0x04000000
+	orrne	r1, r1, #0x00200000
+	tst	r0, #0x08000000
+	orrne	r1, r1, #0x20000000
+	tst	r0, #0x10000000
+	orrne	r1, r1, #0x80000000
+	tst	r0, #0x20000000
+	orrne	r1, r1, #0x00800000
+	tst	r0, #0x40000000
+	orrne	r1, r1, #0x40000000
+	tst	r0, #0x80000000
+	orrne	r1, r1, #0x00400000
+
+	mov	r0, r1
+	mov	pc, lr
diff --git a/board/lart/lart.c b/board/lart/lart.c
new file mode 100755
index 0000000..66b730d
--- /dev/null
+++ b/board/lart/lart.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of LART-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_LART;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	bd_t *bd = gd->bd;
+
+	bd->bi_dram[0].start = PHYS_SDRAM_1;
+	bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	bd->bi_dram[1].start = PHYS_SDRAM_2;
+	bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	bd->bi_dram[2].start = PHYS_SDRAM_3;
+	bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	bd->bi_dram[3].start = PHYS_SDRAM_4;
+	bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return (0);
+}
diff --git a/board/lart/lowlevel_init.S b/board/lart/lowlevel_init.S
new file mode 100755
index 0000000..db9fd63
--- /dev/null
+++ b/board/lart/lowlevel_init.S
@@ -0,0 +1,94 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+#define	MDCNFG	0x00
+#define MDCAS0	0x04
+#define MDCAS1	0x08
+#define MDCAS2	0x0c
+#define MSC0	0x10
+#define MSC1	0x14
+#define MECR	0x18
+
+mdcas0:		.long	0xc71c703f
+mdcas1:		.long	0xffc71c71
+mdcas2:		.long	0xffffffff
+/* mdcnfg:		.long   0x0bb2bcbf */
+mdcnfg:		.long	0x0334b22f	@ alt
+/* mcs0:		.long   0xfff8fff8 */
+msc0:		.long	0xad8c4888	@ alt
+mecr:		.long	0x00060006
+/* mecr:		.long	0x994a994a	@ alt */
+
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	r0, MEM_BASE
+
+	/* Setup the flash memory */
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+
+	/* Set up the DRAM */
+
+	/* MDCAS0 */
+	ldr	r1, mdcas0
+	str	r1, [r0, #MDCAS0]
+
+	/* MDCAS1 */
+	ldr	r1, mdcas1
+	str	r1, [r0, #MDCAS1]
+
+	/* MDCAS2 */
+	ldr	r1, mdcas2
+	str	r1, [r0, #MDCAS2]
+
+	/* MDCNFG */
+	ldr	r1, mdcnfg
+	str	r1, [r0, #MDCNFG]
+
+	/* Set up PCMCIA space */
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+
+	/* Load something to activate bank */
+	ldr	r1, MEM_START
+
+.rept	8
+	ldr	r0, [r1]
+.endr
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/board/lart/u-boot.lds b/board/lart/u-boot.lds
new file mode 100755
index 0000000..258bece
--- /dev/null
+++ b/board/lart/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/sa1100/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/logodl/Makefile b/board/logodl/Makefile
new file mode 100755
index 0000000..c7cde7d
--- /dev/null
+++ b/board/logodl/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= logodl.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/logodl/config.mk b/board/logodl/config.mk
new file mode 100755
index 0000000..76c382d
--- /dev/null
+++ b/board/logodl/config.mk
@@ -0,0 +1,15 @@
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to c170'0000, the upper 1 MB of second bank
+#
+# download areas is c800'0000
+#
+
+#TEXT_BASE = 0
+
+# FIXME: armboot does only work correctly when being compiled
+# # for the addresses _after_ relocation to RAM!! Otherwhise the
+# # .bss segment is assumed in flash...
+#
+TEXT_BASE = 0x083E0000
diff --git a/board/logodl/flash.c b/board/logodl/flash.c
new file mode 100755
index 0000000..a947731
--- /dev/null
+++ b/board/logodl/flash.c
@@ -0,0 +1,829 @@
+/*
+ * (C) 2000 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) 2003 August Hoeraendl, Logotronic GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef CONFIG_FLASH_16BIT
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE 0x1000000
+#define MAIN_SECT_SIZE  0x20000		/* 2x64k = 128k per sector */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+#define write_word(in, de, da)   write_word_amd(in, de, da)
+static void flash_get_offsets(ulong base, flash_info_t *info);
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t *info);
+#endif
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+ulong flash_init(void)
+{
+    int i, j;
+    ulong size = 0;
+
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    {
+	ulong flashbase = 0;
+	flash_info[i].flash_id =
+	  (FLASH_MAN_AMD & FLASH_VENDMASK) |
+	  (FLASH_AM640U & FLASH_TYPEMASK);
+	flash_info[i].size = FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	switch (i)
+	{
+	   case 0:
+		flashbase = PHYS_FLASH_1;
+		break;
+	   case 1:
+		flashbase = PHYS_FLASH_2;
+		break;
+	   default:
+		panic("configured too many flash banks!\n");
+		break;
+	}
+	for (j = 0; j < flash_info[i].sector_count; j++)
+	{
+	    flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
+	}
+	size += flash_info[i].size;
+    }
+
+    /* Protect monitor and environment sectors
+     */
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_FLASH_BASE,
+		  CFG_FLASH_BASE + _bss_start - _armboot_start,
+		  &flash_info[0]);
+
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_ENV_ADDR,
+		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		  &flash_info[0]);
+
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = base + (i * sect_size);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	uchar *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[0x0555] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[0x02AA] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[0x0555] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
+
+	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F800C3B:
+		info->flash_id += FLASH_28F800C3B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F800B3B:
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F160C3B:
+		info->flash_id += FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F160B3B:
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F320C3B:
+		info->flash_id += FLASH_28F320C3B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F320B3B:
+		info->flash_id += FLASH_INTEL320B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F640C3B:
+		info->flash_id += FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F640B3B:
+		info->flash_id += FLASH_INTEL640B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_sync_real_protect(flash_info_t *info)
+{
+    FPWV *addr = (FPWV *)(info->start[0]);
+    FPWV *sect;
+    int i;
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case FLASH_28F800C3B:
+    case FLASH_28F800C3T:
+    case FLASH_28F160C3B:
+    case FLASH_28F160C3T:
+    case FLASH_28F320C3B:
+    case FLASH_28F320C3T:
+    case FLASH_28F640C3B:
+    case FLASH_28F640C3T:
+	/* check for protected sectors */
+	*addr = (FPW)0x00900090;
+	for (i = 0; i < info->sector_count; i++) {
+	    /* read sector protection at sector address, (A7 .. A0) = 0x02.
+	     * D0 = 1 for each device if protected.
+	     * If at least one device is protected the sector is marked
+	     * protected, but mixed protected and  unprotected devices
+	     * within a sector should never happen.
+	     */
+	    sect = (FPWV *)(info->start[i]);
+	    info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+	break;
+
+    case FLASH_AM640U:
+    default:
+	/* no hardware protect that we support */
+	break;
+    }
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer(0);
+	last  = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW)0x00550055;	/* unlock */
+			base[0x0555] = (FPW)0x00800080;	/* erase mode */
+			base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+    int bytes;	  /* number of bytes to program in current word		*/
+    int left;	  /* number of bytes left to program			*/
+    int i, res;
+
+    for (left = cnt, res = 0;
+	 left > 0 && res == 0;
+	 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+	bytes = addr & (sizeof(data) - 1);
+	addr &= ~(sizeof(data) - 1);
+
+	/* combine source and destination data so can program
+	 * an entire word of 16 or 32 bits
+	 */
+	for (i = 0; i < sizeof(data); i++) {
+	    data <<= 8;
+	    if (i < bytes || i - bytes >= left )
+		data += *((uchar *)addr + i);
+	    else
+		data += *src++;
+	}
+
+	/* write one word to the flash */
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		res = write_word_amd(info, (FPWV *)addr, data);
+		break;
+	case FLASH_MAN_INTEL:
+		res = write_word_intel(info, (FPWV *)addr, data);
+		break;
+	default:
+		/* unknown flash type, error! */
+		printf ("missing or unknown FLASH type\n");
+		res = 1;	/* not really a timeout, but gives error */
+		break;
+	}
+    }
+
+    return (res);
+}
+
+/**
+ * write_buf: - Copy memory to flash.
+ *
+ * @param info:
+ * @param src:	source of copy transaction
+ * @param addr:	where to copy to
+ * @param cnt: 	number of bytes to copy
+ *
+ * @return	error code
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 8);
+		}
+		for (; i<2 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 8);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		/* data = *((vushort*)src); */
+		data = *((FPW*)src);
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += sizeof(FPW);
+		wp  += sizeof(FPW);
+		cnt -= sizeof(FPW);
+	}
+
+	if (cnt == 0) return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 8);
+	}
+
+	return write_word(info, wp, data);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+    FPWV *base;		/* first address in flash bank	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+
+    base = (FPWV *)(info->start[0]);
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+    base[0x02AA] = (FPW)0x00550055;	/* unlock */
+    base[0x0555] = (FPW)0x00A000A0;	/* selects program mode */
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    /* data polling for D7 */
+    while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00F000F0;	/* reset bank */
+	    res = 1;
+	}
+    }
+
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+    *dest = (FPW)0x00400040;	/* program setup		*/
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00B000B0;	/* Suspend program	*/
+	    res = 1;
+	}
+    }
+
+    if (res == 0 && (*dest & (FPW)0x00100010))
+	res = 1;	/* write failed, time out error is close enough	*/
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+    return (res);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset (info);		/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset (info);		/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect (info);
+		break;
+
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c
new file mode 100755
index 0000000..95634ac
--- /dev/null
+++ b/board/logodl/logodl.c
@@ -0,0 +1,123 @@
+/*
+ * (C) 2002 Kyle Harris <kharris@nexus-tech.net>, Nexus Technologies, Inc.
+ * (C) 2002 Marius Groeger <mgroeger@sysgo.de>, Sysgo GmbH
+ * (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+/**
+ * board_init: - setup some data structures
+ *
+ * @return: 0 in case of success
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	gd->bd->bi_arch_number = MACH_TYPE_LOGODL;
+	gd->bd->bi_boot_params = 0x08000100;
+	gd->bd->bi_baudrate = CONFIG_BAUDRATE;
+
+	(*((volatile short*)0x14800000)) = 0xff; /* power on eth0 */
+	(*((volatile short*)0x14000000)) = 0xff; /* power on uart */
+
+	return 0;
+}
+
+
+/**
+ * dram_init: - setup dynamic RAM
+ *
+ * @return: 0 in case of success
+ */
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+
+/**
+ * logodl_set_led: - switch LEDs on or off
+ *
+ * @param led:   LED to switch (0,1)
+ * @param state: switch on (1) or off (0)
+ */
+
+void logodl_set_led(int led, int state)
+{
+	switch(led) {
+
+	case 0:
+		if (state==1) {
+			CFG_LED_A_CR = CFG_LED_A_BIT;
+		} else if (state==0) {
+			CFG_LED_A_SR = CFG_LED_A_BIT;
+		}
+		break;
+
+	case 1:
+		if (state==1) {
+			CFG_LED_B_CR = CFG_LED_B_BIT;
+		} else if (state==0) {
+			CFG_LED_B_SR = CFG_LED_B_BIT;
+		}
+		break;
+	}
+
+	return;
+}
+
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ * The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
+ */
+
+void show_boot_progress (int status)
+{
+	/*
+	  switch(status) {
+	  case  1: logodl_set_led(0,1); break;
+	  case  5: logodl_set_led(1,1); break;
+	  case 15: logodl_set_led(2,1); break;
+	  }
+	*/
+	logodl_set_led(0, (status & 1)==1);
+	logodl_set_led(1, (status & 2)==2);
+
+	return;
+}
diff --git a/board/logodl/lowlevel_init.S b/board/logodl/lowlevel_init.S
new file mode 100755
index 0000000..aa9dcba
--- /dev/null
+++ b/board/logodl/lowlevel_init.S
@@ -0,0 +1,437 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc  p15,0,\reg,c2,c0,0
+   mov  \reg,\reg
+   sub  pc,pc,#4
+   .endm
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+
+/*
+ * 	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+    mov      r10, lr
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr	r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+/*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
+/*	ldr	r2,	=CFG_MSC1_VAL	/  high - bank 3 Ethernet Controller */
+/*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
+/*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
+/* */
+/*	ldr	r1,	=LED_BLANK */
+/*	mov	r0,	#0xFF */
+/*	str	r0,	[r1]		/  turn on hex leds */
+/* */
+/*loop: */
+/* */
+/*   ldr	r0, =0xB0070001 */
+/*   ldr    	r1, =_LED */
+/*   str    	r0, [r1]		/  hex display */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr     r2,   =CFG_MSC0_VAL
+	str     r2,   [r1, #MSC0_OFFSET]
+	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */
+	/* MSC1: nCS(2,3)                                                   */
+	ldr     r2,  =CFG_MSC1_VAL
+	str     r2,  [r1, #MSC1_OFFSET]
+	ldr     r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr     r2,  =CFG_MSC2_VAL
+	str     r2,  [r1, #MSC2_OFFSET]
+	ldr     r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr     r2,  =CFG_MECR_VAL
+	str     r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr     r2,  =CFG_MCMEM0_VAL
+	str     r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr     r2,  =CFG_MCMEM1_VAL
+	str     r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr     r2,  =CFG_MCATT0_VAL
+	str     r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr     r2,  =CFG_MCATT1_VAL
+	str     r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr     r2,  =CFG_MCIO0_VAL
+	str     r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr     r2,  =CFG_MCIO1_VAL
+	str     r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+	/* test if we run from flash or RAM - RAM/BDI: don't setup RAM      */
+	adr	r3, mem_init		/* r0 <- current position of code   */
+	ldr	r2, =mem_init
+	cmp	r3, r2			/* skip init if in place            */
+	beq	initirqs
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DRI field.                           */
+
+	ldr 	r3, 	=CFG_MDREFR_VAL
+	ldr	r2,	=0xFFF
+	and	r3,	r3, r2
+	ldr	r4,	=0x03ca4000
+	orr	r4,	r4,  r3
+
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr     r4,	[r1, #MDREFR_OFFSET]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	/* Step 4a: assert MDREFR:K?RUN and configure                       */
+	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
+
+	ldr	r4,	=CFG_MDREFR_VAL
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr	r4,	[r1, #MDREFR_OFFSET]
+
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
+
+	bic	r4,	r4, #(MDREFR_SLFRSH)
+
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,     [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO                           */
+
+	orr	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
+
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,     [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+
+	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+	ldr     r4,     [r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	/*          There should 9 writes, since the first write doesn't    */
+	/*          trigger a refresh cycle on PXA250. See Intel PXA250 and */
+	/*          PXA210 Processors Specification Update,                 */
+	/*          Jan 2003, Errata #116, page 30.                         */
+
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+	str	r2, [r3]
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
+
+	ldr	r3, [r1, #MDCNFG_OFFSET]
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	str	r3, [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2,  =CFG_MDMRS_VAL
+	str     r2,  [r1, #MDMRS_OFFSET]
+
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2,  =ICLR
+	str     r1,  [r2]
+
+	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
+	str     r1,  [r2]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+	/* (hard-coding at 398.12MHz for now).                              */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+	ldr     r1,  =CKEN
+	mov     r2,  #0
+	str     r2,  [r1]
+
+
+	/* default value in case no valid rotary switch setting is found    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1,  =CCCR
+	str     r2,  [r1]
+
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+/*
+	ldr     r1,  =OSCC
+	mov     r2,  #OSCC_OON
+	str     r2,  [r1]
+*/
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size                                                  */
+	ldr	r1, =DRAM_SIZE
+	str	r8, [r1]
+
+	/* Interrupt init: Mask all interrupts                              */
+	ldr	r0, =ICMR			/* enable no sources        */
+	mov	r1, #0
+	str	r1, [r0]
+
+	/* FIXME */
+
+#ifndef DEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init                                                     */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+    mov     pc, lr
diff --git a/board/logodl/u-boot.lds b/board/logodl/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/logodl/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/lpd7a40x/Makefile b/board/lpd7a40x/Makefile
new file mode 100755
index 0000000..ebe14df
--- /dev/null
+++ b/board/lpd7a40x/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= lpd7a40x.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/lpd7a40x/config.mk b/board/lpd7a40x/config.mk
new file mode 100755
index 0000000..bc03874
--- /dev/null
+++ b/board/lpd7a40x/config.mk
@@ -0,0 +1,38 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Logic ZOOM LH7A400 SDK board w/Logic LH7A400-10 card engine
+# w/Sharp LH7A400 SoC (ARM920T) cpu
+#
+
+#
+# 32 or 64 MB SDRAM on SDCSC0 @ 0xc0000000
+#
+# Linux-Kernel is @ 0xC0008000, entry 0xc0008000
+# params @ 0xc0000100
+# optionally with a ramdisk at 0xc0300000
+#
+# we load ourself to 0xc1fc0000 (32M - 256K)
+#
+# download area is 0xc0f00000
+#
+
+TEXT_BASE = 0xc1fc0000
+#TEXT_BASE = 0x00000000
diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c
new file mode 100755
index 0000000..2dfe376
--- /dev/null
+++ b/board/lpd7a40x/flash.c
@@ -0,0 +1,489 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <environment.h>
+
+#define FLASH_BANK_SIZE 0x1000000	/* 16MB (2 x 8 MB) */
+#define MAIN_SECT_SIZE  0x40000		/* 256KB (2 x 128kB) */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00FF00FF
+#define CMD_IDENTIFY		0x00900090
+#define CMD_ERASE_SETUP		0x00200020
+#define CMD_ERASE_CONFIRM	0x00D000D0
+#define CMD_PROGRAM		0x00400040
+#define CMD_RESUME		0x00D000D0
+#define CMD_SUSPEND		0x00B000B0
+#define CMD_STATUS_READ		0x00700070
+#define CMD_STATUS_RESET	0x00500050
+
+#define BIT_BUSY		0x00800080
+#define BIT_ERASE_SUSPEND	0x00400040
+#define BIT_ERASE_ERROR		0x00200020
+#define BIT_PROGRAM_ERROR	0x00100010
+#define BIT_VPP_RANGE_ERROR	0x00080008
+#define BIT_PROGRAM_SUSPEND	0x00040004
+#define BIT_PROTECT_ERROR	0x00020002
+#define BIT_UNDEFINED		0x00010001
+
+#define BIT_SEQUENCE_ERROR	0x00300030
+#define BIT_TIMEOUT		0x80000000
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT     & FLASH_VENDMASK) |
+			(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = CFG_FLASH_BASE;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase;
+
+			/* uniform sector size */
+			flashbase += MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F640J3A & FLASH_TYPEMASK):
+		printf ("2x 28F640J3A (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		return;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_error (ulong code)
+{
+	/* Check bit patterns */
+	/* SR.7=0 is busy, SR.7=1 is ready */
+	/* all other flags indicate error on 1 */
+	/* SR.0 is undefined */
+	/* Timeout is our faked flag */
+
+	/* sequence is described in Intel 290644-005 document */
+
+	/* check Timeout */
+	if (code & BIT_TIMEOUT) {
+		puts ("Timeout\n");
+		return ERR_TIMOUT;
+	}
+
+	/* check Busy, SR.7 */
+	if (~code & BIT_BUSY) {
+		puts ("Busy\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Vpp low, SR.3 */
+	if (code & BIT_VPP_RANGE_ERROR) {
+		puts ("Vpp range error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Device Protect Error, SR.1 */
+	if (code & BIT_PROTECT_ERROR) {
+		puts ("Device protect error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Command Seq Error, SR.4 & SR.5 */
+	if (code & BIT_SEQUENCE_ERROR) {
+		puts ("Command seqence error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Error, SR.5 */
+	if (code & BIT_ERASE_ERROR) {
+		puts ("Block erase error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Error, SR.4 */
+	if (code & BIT_PROGRAM_ERROR) {
+		puts ("Program error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Suspended, SR.6 */
+	if (code & BIT_ERASE_SUSPEND) {
+		puts ("Block erase suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Suspended, SR.2 */
+	if (code & BIT_PROGRAM_SUSPEND) {
+		puts ("Program suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* OK, no error */
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result, result1;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	debug ("flash_erase: s_first %d  s_last %d\n", s_first, s_last);
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		debug ("Erasing sector %2d @ %08lX... ",
+			sect, info->start[sect]);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+			ulong bsR7, bsR7_2, bsR5, bsR5_2;
+
+			/* *addr = CMD_STATUS_RESET; */
+			*addr = CMD_ERASE_SETUP;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			do {
+				/* check timeout */
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					*addr = CMD_STATUS_RESET;
+					result = BIT_TIMEOUT;
+					break;
+				}
+
+				*addr = CMD_STATUS_READ;
+				result = *addr;
+				bsR7 = result & (1 << 7);
+				bsR7_2 = result & (1 << 23);
+			} while (!bsR7 | !bsR7_2);
+
+			*addr = CMD_STATUS_READ;
+			result1 = *addr;
+			bsR5 = result1 & (1 << 5);
+			bsR5_2 = result1 & (1 << 21);
+#ifdef SAMSUNG_FLASH_DEBUG
+			printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+			if (bsR5 != 0 && bsR5_2 != 0)
+				printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+#endif
+
+			*addr = CMD_READ_ARRAY;
+			*addr = CMD_RESUME;
+
+			if ((rc = flash_error (result)) != ERR_OK)
+				goto outahere;
+#if 0
+			printf ("ok.\n");
+		} else {		/* it was protected */
+
+			printf ("protected!\n");
+#endif
+		}
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t * info, ulong dest,
+								ulong data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* *addr = CMD_STATUS_RESET; */
+	*addr = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	do {
+		/* check timeout */
+		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+			*addr = CMD_SUSPEND;
+			result = BIT_TIMEOUT;
+			break;
+		}
+
+		*addr = CMD_STATUS_READ;
+		result = *addr;
+	} while (~result & BIT_BUSY);
+
+	/* *addr = CMD_READ_ARRAY; */
+	*addr = CMD_STATUS_READ;
+	result = *addr;
+
+	rc = flash_error (result);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	*addr = CMD_READ_ARRAY;
+	*addr = CMD_RESUME;
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);			/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 4;
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 24);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/board/lpd7a40x/lowlevel_init.S b/board/lpd7a40x/lowlevel_init.S
new file mode 100755
index 0000000..b3ed55c
--- /dev/null
+++ b/board/lpd7a40x/lowlevel_init.S
@@ -0,0 +1,212 @@
+/*
+ * Memory Setup - initialize memory controller(s) for devices required
+ *                to boot and relocate
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* memory controller */
+#define BCRX_DEFAULT	(0x0000fbe0)
+#define BCRX_MW_8	(0x00000000)
+#define BCRX_MW_16	(0x10000000)
+#define BCRX_MW_32	(0x20000000)
+#define BCRX_PME	(0x08000000)
+#define BCRX_WP		(0x04000000)
+#define BCRX_WST2_SHIFT	(11)
+#define BCRX_WST1_SHIFT	(5)
+#define BCRX_IDCY_SHIFT	(0)
+
+/* Bank0 Async Flash */
+#define BCR0	   	(0x80002000)
+#define BCR0_FLASH	(BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT))
+
+/* Bank1 Open */
+#define BCR1	(0x80002004)
+
+/* Bank2 Not used (EEPROM?) */
+#define BCR2	(0x80002008)
+
+/* Bank3 Not used */
+#define BCR3	(0x8000200C)
+
+/* Bank4 PC Card1 */
+
+/* Bank5 PC Card2 */
+
+/* Bank6 CPLD IO Controller Peripherals (slow) */
+#define BCR6	 	(0x80002018)
+#define BCR6_CPLD_SLOW	(BCRX_DEFAULT | BCRX_MW_16)
+
+/* Bank7 CPLD IO Controller Peripherals (fast) */
+#define BCR7		(0x8000201C)
+#define BCR7_CPLD_FAST	(BCRX_MW_16 | (0x16<<BCRX_WST2_SHIFT) | (0x16<<BCRX_WST1_SHIFT) | (0x2<<BCRX_IDCY_SHIFT))
+
+/* SDRAM */
+#define GBLCNFG		(0x80002404)
+#define GC_CKE		(0x80000000)
+#define GC_CKSD		(0x40000000)
+#define GC_LCR		(0x00000040)
+#define GC_SMEMBURST	(0x00000020)
+#define GC_MRS		(0x00000002)
+#define GC_INIT		(0x00000001)
+
+#define GC_CMD_NORMAL		(GC_CKE)
+#define GC_CMD_MODE		(GC_CKE | GC_MRS)
+#define GC_CMD_SYNCFLASH_LOAD	(GC_CKE | GC_MRS | GC_LCR)
+#define GC_CMD_PRECHARGEALL	(GC_CKE | GC_INIT)
+#define GC_CMD_NOP		(GC_CKE | GC_INIT | GC_MRS)
+
+#define RFSHTMR		(0x80002408)
+#define RFSHTMR_INIT	(10)	/* period=100 ns, HCLK=100Mhz, (2048+1-15.6*66) */
+#define RFSHTMR_NORMAL	(1500)	/* period=15.6 us, HCLK=100Mhz, (2048+1-15.6*66) */
+
+#define SDCSCX_BASE		(0x80002410)
+#define SDCSCX_DEFAULT		(0x01220008)
+#define SDCSCX_AUTOPC		(0x01000000)
+#define SDCSCX_RAS2CAS_2	(0x00200000)
+#define SDCSCX_RAS2CAS_3	(0x00300000)
+#define SDCSCX_WBL		(0x00080000)
+#define SDCSCX_CASLAT_8		(0x00070000)
+#define SDCSCX_CASLAT_7		(0x00060000)
+#define SDCSCX_CASLAT_6		(0x00050000)
+#define SDCSCX_CASLAT_5		(0x00040000)
+#define SDCSCX_CASLAT_4		(0x00030000)
+#define SDCSCX_CASLAT_3		(0x00020000)
+#define SDCSCX_CASLAT_2		(0x00010000)
+#define SDCSCX_2KPAGE		(0x00000040)
+#define SDCSCX_SROMLL		(0x00000020)
+#define SDCSCX_SROM512		(0x00000010)
+#define SDCSCX_4BNK		(0x00000008)
+#define SDCSCX_2BNK		(0x00000000)
+#define SDCSCX_EBW_16		(0x00000004)
+#define SDCSCX_EBW_32		(0x00000000)
+
+#define SDRAM_BASE		(0xC0000000)
+#define SDCSC_BANK_OFFSET	(0x10000000)
+
+/*
+ * The SDRAM DEVICE MODE PROGRAMMING VALUE
+ */
+#define BURST_LENGTH_4		(2 << 10)
+#define BURST_LENGTH_8		(3 << 10)
+#define WBURST_LENGTH_BL	(0 << 19)
+#define WBURST_LENGTH_SINGLE	(1 << 19)
+#define CAS_2			(2 << 14)
+#define CAS_3			(3 << 14)
+#define BAT_SEQUENTIAL		(0 << 13)
+#define BAT_INTERLEAVED		(1 << 13)
+#define OPM_NORMAL		(0 << 17)
+#define SDRAM_DEVICE_MODE	(WBURST_LENGTH_BL|OPM_NORMAL|CAS_3|BAT_SEQUENTIAL|BURST_LENGTH_4)
+
+
+#define TIMER1_BASE	(0x80000C00)
+
+/*
+ * special lookup flags
+ */
+#define DO_MEM_DELAY	1
+#define DO_MEM_READ	2
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	r9, lr	@ save return address
+
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads INITMEM_DATA out of FLASH rather than memory ! */
+	/*   r0 = current word pointer */
+	/*   r1 = end word location, one word past last actual word */
+	/*   r3 = address for writes, special lookup flags */
+	/*   r4 = value for writes, delay constants, or read addresses */
+	/*   r2 = location for mem reads */
+
+	ldr	r0, =INITMEM_DATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	add	r1, r0, #112
+
+mem_loop:
+	cmp	r1, r0
+	moveq	pc, r9		@ Done
+
+	ldr	r3, [r0], #4	@ Fetch Destination Register Address, or 1 for delay
+	ldr	r4, [r0], #4	@ value
+
+	cmp	r3, #DO_MEM_DELAY
+	bleq	mem_delay
+	beq	mem_loop
+	cmp	r3, #DO_MEM_READ
+	ldreq	r2, [r4]
+	beq	mem_loop
+	str	r4, [r3]	@ normal register/ram store
+	b	mem_loop
+
+mem_delay:
+	ldr	r5, =TIMER1_BASE
+	mov	r6, r4, LSR #1	@ timer resolution is ~2us
+	str	r6, [r5]
+	mov	r6, #0x88	@ using 508.469KHz clock, enable
+	str	r6, [r5, #8]
+0:	ldr	r6, [r5, #4]	@ timer value
+	cmp	r6, #0
+	bne	0b
+	mov	r6, #0		@ disable timer
+	str	r6, [r5, #8]
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+INITMEM_DATA:
+	.word	BCR0
+	.word	BCR0_FLASH
+	.word	BCR6
+	.word	BCR6_CPLD_SLOW
+	.word	BCR7
+	.word	BCR7_CPLD_FAST
+	.word	SDCSCX_BASE
+	.word	(SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
+	.word	GBLCNFG
+	.word	GC_CMD_NOP
+	.word	DO_MEM_DELAY
+	.word	200
+	.word	GBLCNFG
+	.word	GC_CMD_PRECHARGEALL
+	.word	RFSHTMR
+	.word	RFSHTMR_INIT
+	.word	DO_MEM_DELAY
+	.word	8
+	.word	RFSHTMR
+	.word	RFSHTMR_NORMAL
+	.word	GBLCNFG
+	.word	GC_CMD_MODE
+	.word	DO_MEM_READ
+	.word	(SDRAM_BASE | SDRAM_DEVICE_MODE)
+	.word	GBLCNFG
+	.word	GC_CMD_NORMAL
+	.word	SDCSCX_BASE
+	.word	(SDCSCX_AUTOPC | SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
diff --git a/board/lpd7a40x/lpd7a40x.c b/board/lpd7a40x/lpd7a40x.c
new file mode 100755
index 0000000..4c373ee
--- /dev/null
+++ b/board/lpd7a40x/lpd7a40x.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_LH7A400)
+#include <lh7a400.h>
+#elif defined(CONFIG_LH7A404)
+#include <lh7a404.h>
+#else
+#error "No CPU defined!"
+#endif
+#include <asm/mach-types.h>
+
+#include <lpd7a400_cpld.h>
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* set up the I/O ports */
+
+	/* enable flash programming */
+	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_FLASH_REG)) |= FLASH_FPEN;
+
+	/* Auto wakeup, LCD disable, WLAN enable */
+	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_CECTL_REG)) &=
+		~(CECTL_AWKP|CECTL_LCDV|CECTL_WLPE);
+
+	/* Status LED 2 on (leds are active low) */
+	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_EXTGPIO_REG)) =
+		(EXTGPIO_STATUS1|EXTGPIO_GPIO1) & ~(EXTGPIO_STATUS2);
+
+#if defined(CONFIG_LH7A400)
+	/* arch number of Logic-Board - MACH_TYPE_LPD7A400 */
+	gd->bd->bi_arch_number = MACH_TYPE_LPD7A400;
+#elif defined(CONFIG_LH7A404)
+	/* arch number of Logic-Board - MACH_TYPE_LPD7A400 */
+	gd->bd->bi_arch_number = MACH_TYPE_LPD7A404;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff --git a/board/lpd7a40x/u-boot.lds b/board/lpd7a40x/u-boot.lds
new file mode 100755
index 0000000..156b871
--- /dev/null
+++ b/board/lpd7a40x/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/lh7a40x/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/lubbock/Makefile b/board/lubbock/Makefile
new file mode 100755
index 0000000..106622c
--- /dev/null
+++ b/board/lubbock/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= lubbock.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/lubbock/config.mk b/board/lubbock/config.mk
new file mode 100755
index 0000000..55c8b27
--- /dev/null
+++ b/board/lubbock/config.mk
@@ -0,0 +1,3 @@
+#TEXT_BASE = 0xa1700000
+TEXT_BASE = 0xa3080000
+#TEXT_BASE = 0
diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c
new file mode 100755
index 0000000..ba82892
--- /dev/null
+++ b/board/lubbock/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S
new file mode 100755
index 0000000..15276e8
--- /dev/null
+++ b/board/lubbock/lowlevel_init.S
@@ -0,0 +1,411 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc  p15,0,\reg,c2,c0,0
+   mov  \reg,\reg
+   sub  pc,pc,#4
+   .endm
+
+
+/*
+ * 	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+    mov      r10, lr
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr	r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr     r2,   =CFG_MSC0_VAL
+	str     r2,   [r1, #MSC0_OFFSET]
+	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */
+	/* MSC1: nCS(2,3)                                                   */
+	ldr     r2,  =CFG_MSC1_VAL
+	str     r2,  [r1, #MSC1_OFFSET]
+	ldr     r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr     r2,  =CFG_MSC2_VAL
+	str     r2,  [r1, #MSC2_OFFSET]
+	ldr     r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr     r2,  =CFG_MECR_VAL
+	str     r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr     r2,  =CFG_MCMEM0_VAL
+	str     r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr     r2,  =CFG_MCMEM1_VAL
+	str     r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr     r2,  =CFG_MCATT0_VAL
+	str     r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr     r2,  =CFG_MCATT1_VAL
+	str     r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr     r2,  =CFG_MCIO0_VAL
+	str     r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr     r2,  =CFG_MCIO1_VAL
+	str     r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DRI field.                           */
+
+	ldr     r3,     =CFG_MDREFR_VAL
+	ldr     r2,     =0xFFF
+	and     r3,     r3,  r2
+	ldr	r4,	=0x03ca4000
+	orr     r4,     r4,  r3
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+	/* Note: preserve the mdrefr value in r4                            */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	/* set MDREFR according to user define with exception of a few bits */
+
+	ldr     r4,     =CFG_MDREFR_VAL
+	orr	r4,	r4,	#(MDREFR_SLFRSH)
+	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
+
+	bic	r4,	r4,	#(MDREFR_SLFRSH)
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
+
+	ldr     r4,     =CFG_MDREFR_VAL
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,     [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+
+	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+	ldr     r4,     [r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	    str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	    ldr r2, [r3]
+	    cmp r4, r2
+	    bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
+
+	ldr     r3,  [r1, #MDCNFG_OFFSET]
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	str     r3,  [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2,  =CFG_MDMRS_VAL
+	str     r2,  [r1, #MDMRS_OFFSET]
+
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2,  =ICLR
+	str     r1,  [r2]
+
+	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
+	str     r1,  [r2]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+	/* (hard-coding at 398.12MHz for now).                              */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+	ldr     r1,  =CKEN
+	mov     r2,  #0
+	str     r2,  [r1]
+
+
+	/* default value in case no valid rotary switch setting is found    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1,  =CCCR
+	str     r2,  [r1]
+
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+
+	ldr     r1,  =OSCC
+	mov     r2,  #OSCC_OON
+	str     r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size */
+    ldr     r1, =DRAM_SIZE
+	 str	   r8, [r1]
+
+	/* Interrupt init: Mask all interrupts                              */
+    ldr	r0, =ICMR /* enable no sources */
+	mov r1, #0
+    str r1, [r0]
+
+	/* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init                                                     */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+    mov     pc, lr
diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c
new file mode 100755
index 0000000..e618ab9
--- /dev/null
+++ b/board/lubbock/lubbock.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of Lubbock-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
diff --git a/board/lubbock/u-boot.lds b/board/lubbock/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/lubbock/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/lwmon/Makefile b/board/lwmon/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/lwmon/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/lwmon/README.keybd b/board/lwmon/README.keybd
new file mode 100755
index 0000000..54f0aeb
--- /dev/null
+++ b/board/lwmon/README.keybd
@@ -0,0 +1,126 @@
+
+Tastaturabfrage:
+
+Die Implementierung / Decodierung beruht auf den Angaben aus dem  Do-
+kument  "PIC LWE-Tastatur" in der Fassung vom 9. 3. 2001, insbesonde-
+re Tabelle 3 im Kapitel 4.3 Tastencodes. In  U-Boot  werden  die  vom
+Keyboard-Controller  gelesenen Daten hexadezimal codiert in der auto-
+matisch angelegten Environment-Variablen "keybd" übergeben. Ist  kei-
+ne Taste gedrückt worden, steht dort:
+
+	keybd=000000000000000000
+
+Der decodierte Tastencode ("keybd") kann mit den  "bootargs"  an  den
+Linux-Kernel  übergeben  und  dort z. B. in einem Device-Treiber oder
+einer Applikation ausgewertet werden.
+
+
+Sonderfunktionen beim Booten:
+
+Es lassen sich eine oder mehrere (beliebig viele) Tasten oder Tasten-
+kombinationen definieren, die Sonderfunktionen auslösen,  wenn  diese
+Tasten beim Booten (Reset) gedrückt sind.
+
+Wird eine eingestellte Taste bzw. Tastenkombination erkannt, so  wird
+in  U-Boot noch vor dem Start des "Countdown" und somit vor jedem an-
+deren Kommando der Inhalt einer dieser Taste  bzw.  Tastenkombination
+zugeordneten Environment-Variablen ausführen.
+
+
+Die Environment-Variable "magic_keys" wird als Liste von Zeichen ver-
+standen, die als Suffix an den Namen "key_magic" angefügt werden  und
+so  die  Namen  der  Environment-Variablen  definieren, mit denen die
+Tasten (-kombinationen) festgelegt werden:
+
+Ist "magic_keys" NICHT definiert, so wird nur die in der Environment-
+Variablen "key_magic" codierte  Tasten  (-kombination)  geprüft,  und
+ggf.  der  Inhalt der Environment-Variablen "key_cmd" ausgeführt (ge-
+nauer: der Inhalt von "key_cmd" wird der Variablen "preboot" zugewie-
+sen, die ausgeführt wird, unmittelbar bevor die interaktive Kommando-
+interpretation beginnt).
+
+Enthält "magic_keys" z. B.  die  Zeichenkette  "0123CB*",  so  werden
+nacheinander folgende Aktionen ausgeführt:
+
+	prüfe Tastencode	ggf. führe aus Kommando
+	in Variable		in Variable
+	-----------------------------------
+	key_magic0	==>	key_cmd0
+	key_magic1	==>	key_cmd1
+	key_magic2	==>	key_cmd2
+	key_magic3	==>	key_cmd3
+	key_magicC	==>	key_cmdC
+	key_magicB	==>	key_cmdB
+	key_magicA	==>	key_cmdA
+	key_magic*	==>	key_cmd*
+
+Hinweis: sobald ein aktivierter Tastencode erkannt  wurde,  wird  die
+Bearbeitung  abgebrochen; es wird daher höchstens eines der definier-
+ten Kommandos ausgeführt, wobei die Priorität durch  die  Suchreihen-
+folge  festgelegt wird, also durch die Reihenfolge der Zeichen in der
+Varuiablen "magic_keys".
+
+
+Die Codierung der Tasten, die beim Booten gedrückt werden müssen, um
+eine Funktion auszulösen, erfolgt nach der Tastaturtabelle.
+
+Die Definitionen
+
+	=> setenv key_magic0 3a+3b
+	=> setenv key_cmd0 setenv bootdelay 30
+
+bedeuten dementsprechend, daß die Tasten mit den  Codes  0x3A  (Taste
+"F1")  und 0x3B (Taste "F2") gleichzeitig gedrückt werden müssen. Sie
+können dort eine beliebige  Tastenkombination  eintragen  (jeweils  2
+Zeichen für die Hex-Codes der Tasten, und '+' als Trennzeichen).
+
+Wird die eingestellte Tastenkombination erkannt, so  wird  in  U-Boot
+noch  vor  dem Start des "Countdown" und somit vor jedem anderen Kom-
+mando das angebene Kommando ausgeführt und  somit  ein  langes  Boot-
+Delay eingetragen.
+
+Praktisch könnten Sie also in U-Boot "bootdelay"  auf  0  setzen  und
+somit  stets  ohne  jede  User-Interaktion automatisch booten, außer,
+wenn die beiden Tasten "F1" und "F2"  beim  Booten  gedrückt  werden:
+dann würde ein Boot-Delay von 30 Sekunden eingefügt.
+
+
+Hinweis: dem Zeichen '#' kommt innerhalb von "magic_keys" eine beson-
+dere Bedeutung zu: die dadurch definierte  Key-Sequenz  schaltet  den
+Monitor in den "Debug-Modus" - das bedeutet zunächst, daß alle weite-
+ren  Meldungen  von  U-Boot  über  das LCD-Display ausgegeben werden;
+außerdem kann man durch das mit dieser  Tastenkombination  verknüpfte
+Kommando  z. B. die Linux-Bootmeldungen ebenfalls auf das LCD-Display
+legen, so daß der Boot-Vorgang direkt und  ohne  weitere  Hilfsmittel
+analysiert werden kann.
+
+Beispiel:
+
+In U-Boot werden folgende Environment-Variablen gesetzt und abgespei-
+chert:
+
+(1)	=> setenv magic_keys 01234#X
+(2)	=> setenv key_cmd# setenv addfb setenv bootargs \\${bootargs} console=tty0 console=ttyS1,\\${baudrate}
+(3)	=> setenv nfsargs setenv bootargs root=/dev/nfs rw nfsroot=\${serverip}:\${rootpath}
+(4)	=> setenv addip setenv bootargs \${bootargs} ip=\${ipaddr}:\${serverip}:\${gatewayip}:\${netmask}:\${hostname}::off panic=1
+(5)	=> setenv addfb setenv bootargs \${bootargs} console=ttyS1,\${baudrate}
+(6)	=> setenv bootcmd bootp\;run nfsargs\;run addip\;run addfb\;bootm
+
+Hierbei wird die Linux Commandline (in der Variablen  "bootargs")  im
+Boot-Kommando  "bootcmd"  (6)  schrittweise zusammengesetzt: zunächst
+werden die für Root-Filesystem über NFS erforderlichen  Optionen  ge-
+setzt  ("run  nfsargs", vgl. (3)), dann die Netzwerkkonfiguration an-
+gefügt ("run addip", vgl. (4)),  und  schließlich  die  Systemconsole
+definiert ("run addfb").
+
+Dabei wird im Normalfall die Definition (5)  verwendt;  wurde  aller-
+dings  beim  Reset die entsprechende Taste gedrückt gehalten, so wird
+diese Definition bei der Ausführung des in (2) definierten  Kommandos
+überschrieben,  so  daß  Linux die Bootmeldungen auch über das Frame-
+buffer-Device (=LCD-Display) ausgibt.
+
+Beachten Sie die Verdoppelung der '\'-Escapes in der  Definition  von
+"key_cmd#" - diese ist erforderlich, weil der String _zweimal_ inter-
+pretiert  wird:  das  erste  Mal  bei der Eingabe von "key_cmd#", das
+zweite Mal, wenn der String (als  Inhalt  von  "preboot")  ausgeführt
+wird.
diff --git a/board/lwmon/config.mk b/board/lwmon/config.mk
new file mode 100755
index 0000000..dfa952a
--- /dev/null
+++ b/board/lwmon/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# LWE Monitorcontroller Litronic LCD IV boards
+#
+
+TEXT_BASE = 0x40000000
+#TEXT_BASE = 0x41000000
diff --git a/board/lwmon/flash.c b/board/lwmon/flash.c
new file mode 100755
index 0000000..b894887
--- /dev/null
+++ b/board/lwmon/flash.c
@@ -0,0 +1,648 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, ulong data);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	debug  ("## Before remap: "
+		"BR0: 0x%08x    OR0: 0x%08x    "
+		"BR1: 0x%08x    OR1: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0,
+		memctl->memc_br1, memctl->memc_or1);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
+				OR_CSNT_SAM | OR_ACS_DIV1;
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V;
+
+	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
+					OR_CSNT_SAM | OR_ACS_DIV1;
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+					BR_PS_32 | BR_V;
+
+		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_info[1].size = size_b1;
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+		memctl->memc_or1 = 0;		/* invalidate bank */
+
+		debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+		flash_info[1].size = 0;
+	}
+
+	debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+	    for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += 0x00020000 * 2;		/* 128k * 2 chips per bank */
+	    }
+	    return;
+
+	default:
+	    printf ("Don't know sector ofsets for flash type 0x%lx\n",
+		info->flash_id);
+	    return;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320J3A (32Mbit = 128K x 32)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640J3A (64Mbit = 128K x 64)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128J3A (128Mbit = 128K x 128)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	ulong value;
+
+	/* Read Manufacturer ID */
+	addr[0] = 0x00900090;
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0x00FF00FF;		/* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000 * 2;
+		break;				/* =>  8 MB		*/
+
+	case INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000 * 2;
+		break;				/* => 16 MB		*/
+
+	case INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000 * 2;
+		break;				/* => 32 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = 0x00FF00FF;		/* restore read mode */
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+			unsigned long status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = 0x00600060;	/* clear lock bit setup */
+			*addr = 0x00D000D0;	/* clear lock bit confirm */
+
+			udelay (1000);
+			/* This takes awfully long - up to 50 ms and more */
+			while (((status = *addr) & 0x00800080) != 0x00800080) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0x00FF00FF; /* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+				udelay (1000);	/* to trigger the watchdog */
+			}
+
+			*addr = 0x00500050;	/* clear status register */
+			*addr = 0x00200020;	/* erase setup */
+			*addr = 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & 0x00800080) != 0x00800080) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0x00B000B0; /* suspend erase	  */
+					*addr = 0x00FF00FF; /* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+				udelay (1000);	/* to trigger the watchdog */
+			}
+
+			*addr = 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	4	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower FLASH_WIDTH aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<FLASH_WIDTH && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= FLASH_WIDTH) {
+		i = CFG_FLASH_BUFFER_SIZE > cnt ?
+		    (cnt & ~(FLASH_WIDTH - 1)) : CFG_FLASH_BUFFER_SIZE;
+		if((rc = write_data_buf(info, wp, src,i)) != 0)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	while (cnt >= FLASH_WIDTH) {
+		data = 0;
+		for (i=0; i<FLASH_WIDTH; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<FLASH_WIDTH; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Check flash status, returns:
+ * 0 - OK
+ * 1 - timeout
+ */
+static int flash_status_check(vu_long *addr, ulong tout, char * prompt)
+{
+	ulong status;
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(((status = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > tout) {
+			printf("Flash %s timeout at address %p\n", prompt, addr);
+			*addr = 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = 0x00400040;		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	if (flash_status_check(addr, CFG_FLASH_WRITE_TOUT, "write") != 0) {
+		return (1);
+	}
+
+	*addr = 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+/*-----------------------------------------------------------------------
+ * Write a buffer to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ */
+static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+	vu_long *addr = (vu_long *)dest;
+	int sector;
+	int cnt;
+	int retcode;
+	vu_long * src = (vu_long *)cp;
+	vu_long * dst = (vu_long *)dest;
+
+	/* find sector */
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(dest >= info->start[sector])
+			break;
+	}
+
+	*addr = 0x00500050;		/* clear status */
+	*addr = 0x00e800e8;		/* write buffer */
+
+	if((retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT,
+					 "write to buffer")) == 0) {
+		cnt = len / FLASH_WIDTH;
+		*addr = (cnt-1) | ((cnt-1) << 16);
+		while(cnt-- > 0) {
+			*dst++ = *src++;
+		}
+		*addr = 0x00d000d0;		/* write buffer confirm */
+		retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT,
+						 "buffer write");
+	}
+	*addr = 0x00FF00FF;	/* restore read mode */
+	*addr = 0x00500050;	/* clear status */
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
new file mode 100755
index 0000000..a174b57
--- /dev/null
+++ b/board/lwmon/lwmon.c
@@ -0,0 +1,1068 @@
+/***********************************************************************
+ *
+M* Modul:         lwmon.c
+M*
+M* Content:       LWMON specific U-Boot commands.
+ *
+ * (C) Copyright 2001, 2002
+ * DENX Software Engineering
+ * Wolfgang Denk, wd@denx.de
+ * All rights reserved.
+ *
+D* Design:        wd@denx.de
+C* Coding:        wd@denx.de
+V* Verification:  dzu@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ ***********************************************************************/
+
+/*---------------------------- Headerfiles ----------------------------*/
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+#include <i2c.h>
+#include <command.h>
+#include <malloc.h>
+#include <post.h>
+#include <serial.h>
+
+#include <linux/types.h>
+#include <linux/string.h>	/* for strdup */
+
+/*------------------------ Local prototypes ---------------------------*/
+static long int dram_size (long int, long int *, long int);
+static void kbd_init (void);
+static int compare_magic (uchar *kbd_data, uchar *str);
+
+
+/*--------------------- Local macros and constants --------------------*/
+#define	_NOT_USED_	0xFFFFFFFF
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void);
+extern void disable_putc(void);
+#endif /* CONFIG_MODEM_SUPPORT */
+
+/*
+ * 66 MHz SDRAM access using UPM A
+ */
+const uint sdram_table[] =
+{
+#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E)
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
+	0x1FF5FC47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPM RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
+#endif
+#ifdef CFG_MEMORY_7E
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
+	_NOT_USED_,
+	/*
+	 * SDRAM Initialization (offset 5 in UPM RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
+	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
+	0xE1BAFC04, 0x1FF5FC47, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
+#endif
+};
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+/***********************************************************************
+F* Function:     int checkboard (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int - 0 is always returned
+ *
+Z* Intention:    This function is the checkboard() method implementation
+Z*               for the lwmon board.  Only a standard message is printed.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int checkboard (void)
+{
+	puts ("Board: LICCON Konsole LCD3\n");
+	return (0);
+}
+
+/***********************************************************************
+F* Function:     long int initdram (int board_type) P*A*Z*
+ *
+P* Parameters:   int board_type
+P*                - Usually type of the board - ignored here.
+P*
+P* Returnvalue:  long int
+P*                - Size of initialized memory
+ *
+Z* Intention:    This function is the initdram() method implementation
+Z*               for the lwmon board.
+Z*               The memory controller is initialized to access the
+Z*               DRAM.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+long int initdram (int board_type)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	long int size_b0;
+	long int size8, size9;
+	int i;
+
+	/*
+	 * Configure UPMA for SDRAM
+	 */
+	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	/* burst length=4, burst type=sequential, CAS latency=2 */
+	memctl->memc_mar = CFG_MAR;
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	/* initialize memory address register */
+	memctl->memc_mamr = CFG_MAMR_8COL;	/* refresh not enabled yet */
+
+	/* mode initialization (offset 5) */
+	udelay (200);				/* 0x80006105 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
+
+	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+	udelay (1);				/* 0x80006130 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+	udelay (1);				/* 0x80006130 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
+
+	udelay (1);				/* 0x80006106 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */
+
+	udelay (200);
+
+	/* Need at least 10 DRAM accesses to stabilize */
+	for (i = 0; i < 10; ++i) {
+		volatile unsigned long *addr =
+			(volatile unsigned long *) SDRAM_BASE3_PRELIM;
+		unsigned long val;
+
+		val = *(addr + i);
+		*(addr + i) = val;
+	}
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE;
+		udelay (500);
+	} else {			/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
+		udelay (500);
+	}
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |
+			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
+	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	udelay (1000);
+
+	return (size_b0);
+}
+
+/***********************************************************************
+F* Function:     static long int dram_size (long int mamr_value,
+F*                                          long int *base,
+F*                                          long int maxsize) P*A*Z*
+ *
+P* Parameters:   long int mamr_value
+P*                - Value for MAMR for the test
+P*               long int *base
+P*                - Base address for the test
+P*               long int maxsize
+P*                - Maximum size to test for
+P*
+P* Returnvalue:  long int
+P*                - Size of probed memory
+ *
+Z* Intention:    Check memory range for valid RAM. A simple memory test
+Z*               determines the actually available RAM size between
+Z*               addresses `base' and `base + maxsize'. Some (not all)
+Z*               hardware errors are detected:
+Z*                - short between address lines
+Z*                - short between data lines
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifndef	PB_ENET_TENA
+# define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+#endif
+
+/***********************************************************************
+F* Function:     int board_early_init_f (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned.
+ *
+Z* Intention:    This function is the board_early_init_f() method implementation
+Z*               for the lwmon board.
+Z*               Disable Ethernet TENA on Port B.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int board_early_init_f (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/* Disable Ethernet TENA on Port B
+	 * Necessary because of pull up in COM3 port.
+	 *
+	 * This is just a preliminary fix, intended to turn off TENA
+	 * as soon as possible to avoid noise on the network. Once
+	 * I²C is running we will make sure the interface is
+	 * correctly initialized.
+	 */
+	immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA;
+	immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA;
+	immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA;	/* set to 0 = disabled */
+	immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/***********************************************************************
+F* Function:     void reset_phy (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  none
+ *
+Z* Intention:    Reset the PHY.  In the lwmon case we do this by the
+Z*               signaling the PIC I/O expander.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+void reset_phy (void)
+{
+	uchar c;
+
+#ifdef DEBUG
+	printf ("### Switch on Ethernet for SCC2 ###\n");
+#endif
+	c = pic_read (0x61);
+#ifdef DEBUG
+	printf ("Old PIC read: reg_61 = 0x%02x\n", c);
+#endif
+	c |= 0x40;					/* disable COM3 */
+	c &= ~0x80;					/* enable Ethernet */
+	pic_write (0x61, c);
+#ifdef DEBUG
+	c = pic_read (0x61);
+	printf ("New PIC read: reg_61 = 0x%02x\n", c);
+#endif
+	udelay (1000);
+}
+
+
+/*------------------------- Keyboard controller -----------------------*/
+/* command codes */
+#define	KEYBD_CMD_READ_KEYS	0x01
+#define KEYBD_CMD_READ_VERSION	0x02
+#define KEYBD_CMD_READ_STATUS	0x03
+#define KEYBD_CMD_RESET_ERRORS	0x10
+
+/* status codes */
+#define KEYBD_STATUS_MASK	0x3F
+#define	KEYBD_STATUS_H_RESET	0x20
+#define KEYBD_STATUS_BROWNOUT	0x10
+#define KEYBD_STATUS_WD_RESET	0x08
+#define KEYBD_STATUS_OVERLOAD	0x04
+#define KEYBD_STATUS_ILLEGAL_WR	0x02
+#define KEYBD_STATUS_ILLEGAL_RD	0x01
+
+/* Number of bytes returned from Keyboard Controller */
+#define KEYBD_VERSIONLEN	2	/* version information */
+#define	KEYBD_DATALEN		9	/* normal key scan data */
+
+/* maximum number of "magic" key codes that can be assigned */
+
+static uchar kbd_addr = CFG_I2C_KEYBD_ADDR;
+
+static uchar *key_match (uchar *);
+
+#define	KEYBD_SET_DEBUGMODE	'#'	/* Magic key to enable debug output */
+
+/***********************************************************************
+F* Function:     int board_postclk_init (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned.
+ *
+Z* Intention:    This function is the board_postclk_init() method implementation
+Z*               for the lwmon board.
+ *
+ ***********************************************************************/
+int board_postclk_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	kbd_init();
+
+#ifdef CONFIG_MODEM_SUPPORT
+	if (key_pressed()) {
+		disable_putc();	/* modem doesn't understand banner etc */
+		gd->do_mdm_init = 1;
+	}
+#endif
+
+	return (0);
+}
+
+struct serial_device * default_serial_console (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device;
+}
+
+static void kbd_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar tmp_data[KEYBD_DATALEN];
+	uchar val, errcd;
+	int i;
+
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	gd->kbd_status = 0;
+
+	/* Forced by PIC. Delays <= 175us loose */
+	udelay(1000);
+
+	/* Read initial keyboard error code */
+	val = KEYBD_CMD_READ_STATUS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, &errcd, 1);
+	/* clear unused bits */
+	errcd &= KEYBD_STATUS_MASK;
+	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
+	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
+	if (errcd) {
+		gd->kbd_status |= errcd << 8;
+	}
+	/* Reset error code and verify */
+	val = KEYBD_CMD_RESET_ERRORS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	udelay(1000);	/* delay NEEDED by keyboard PIC !!! */
+
+	val = KEYBD_CMD_READ_STATUS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, &val, 1);
+
+	val &= KEYBD_STATUS_MASK;	/* clear unused bits */
+	if (val) {			/* permanent error, report it */
+		gd->kbd_status |= val;
+		return;
+	}
+
+	/*
+	 * Read current keyboard state.
+	 *
+	 * After the error reset it may take some time before the
+	 * keyboard PIC picks up a valid keyboard scan - the total
+	 * scan time is approx. 1.6 ms (information by Martin Rajek,
+	 * 28 Sep 2002). We read a couple of times for the keyboard
+	 * to stabilize, using a big enough delay.
+	 * 10 times should be enough. If the data is still changing,
+	 * we use what we get :-(
+	 */
+
+	memset (tmp_data, 0xFF, KEYBD_DATALEN);	/* impossible value */
+	for (i=0; i<10; ++i) {
+		val = KEYBD_CMD_READ_KEYS;
+		i2c_write (kbd_addr, 0, 0, &val, 1);
+		i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+		if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
+			/* consistent state, done */
+			break;
+		}
+		/* remeber last state, delay, and retry */
+		memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
+		udelay (5000);
+	}
+}
+
+/***********************************************************************
+F* Function:     int misc_init_r (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned, even in the case of a keyboard
+P*                    error.
+ *
+Z* Intention:    This function is the misc_init_r() method implementation
+Z*               for the lwmon board.
+Z*               The keyboard controller is initialized and the result
+Z*               of a read copied to the environment variable "keybd".
+Z*               If KEYBD_SET_DEBUGMODE is defined, a check is made for
+Z*               this key, and if found display to the LCD will be enabled.
+Z*               The keys in "keybd" are checked against the magic
+Z*               keycommands defined in the environment.
+Z*               See also key_match().
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	uchar kbd_data[KEYBD_DATALEN];
+	char keybd_env[2 * KEYBD_DATALEN + 1];
+	uchar kbd_init_status = gd->kbd_status >> 8;
+	uchar kbd_status = gd->kbd_status;
+	uchar val;
+	char *str;
+	int i;
+
+	if (kbd_init_status) {
+		printf ("KEYBD: Error %02X\n", kbd_init_status);
+	}
+	if (kbd_status) {		/* permanent error, report it */
+		printf ("*** Keyboard error code %02X ***\n", kbd_status);
+		sprintf (keybd_env, "%02X", kbd_status);
+		setenv ("keybd", keybd_env);
+		return 0;
+	}
+
+	/*
+	 * Now we know that we have a working  keyboard,  so  disable
+	 * all output to the LCD except when a key press is detected.
+	 */
+
+	if ((console_assign (stdout, "serial") < 0) ||
+		(console_assign (stderr, "serial") < 0)) {
+		printf ("Can't assign serial port as output device\n");
+	}
+
+	/* Read Version */
+	val = KEYBD_CMD_READ_VERSION;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
+	printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
+
+	/* Read current keyboard state */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+	}
+	setenv ("keybd", keybd_env);
+
+	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
+#ifdef KEYBD_SET_DEBUGMODE
+	if (kbd_data[0] == KEYBD_SET_DEBUGMODE) {	/* set debug mode */
+		if ((console_assign (stdout, "lcd") < 0) ||
+			(console_assign (stderr, "lcd") < 0)) {
+			printf ("Can't assign LCD display as output device\n");
+		}
+	}
+#endif /* KEYBD_SET_DEBUGMODE */
+#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
+	setenv ("preboot", str);	/* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+	if (str != NULL) {
+		free (str);
+	}
+	return (0);
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static int compare_magic (uchar *kbd_data, uchar *str)
+{
+	uchar compare[KEYBD_DATALEN-1];
+	char *nxt;
+	int i;
+
+	/* Don't include modifier byte */
+	memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
+
+	for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
+		uchar c;
+		int k;
+
+		c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
+
+		if (str == (uchar *)nxt) {	/* invalid character */
+			break;
+		}
+
+		/*
+		 * Check if this key matches the input.
+		 * Set matches to zero, so they match only once
+		 * and we can find duplicates or extra keys
+		 */
+		for (k = 0; k < sizeof(compare); ++k) {
+			if (compare[k] == '\0')	/* only non-zero entries */
+				continue;
+			if (c == compare[k]) {	/* found matching key */
+				compare[k] = '\0';
+				break;
+			}
+		}
+		if (k == sizeof(compare)) {
+			return -1;		/* unmatched key */
+		}
+	}
+
+	/*
+	 * A full match leaves no keys in the `compare' array,
+	 */
+	for (i = 0; i < sizeof(compare); ++i) {
+		if (compare[i])
+		{
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/***********************************************************************
+F* Function:     static uchar *key_match (uchar *kbd_data) P*A*Z*
+ *
+P* Parameters:   uchar *kbd_data
+P*                - The keys to match against our magic definitions
+P*
+P* Returnvalue:  uchar *
+P*                - != NULL: Pointer to the corresponding command(s)
+P*                     NULL: No magic is about to happen
+ *
+Z* Intention:    Check if pressed key(s) match magic sequence,
+Z*               and return the command string associated with that key(s).
+Z*
+Z*               If no key press was decoded, NULL is returned.
+Z*
+Z*               Note: the first character of the argument will be
+Z*                     overwritten with the "magic charcter code" of the
+Z*                     decoded key(s), or '\0'.
+Z*
+Z*               Note: the string points to static environment data
+Z*                     and must be saved before you call any function that
+Z*                     modifies the environment.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+static uchar *key_match (uchar *kbd_data)
+{
+	char magic[sizeof (kbd_magic_prefix) + 1];
+	uchar *suffix;
+	char *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can pe appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+#if 0
+		printf ("### Check magic \"%s\"\n", magic);
+#endif
+		if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+			char cmd_name[sizeof (kbd_command_prefix) + 1];
+			char *cmd;
+
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+
+			cmd = getenv (cmd_name);
+#if 0
+			printf ("### Set PREBOOT to $(%s): \"%s\"\n",
+					cmd_name, cmd ? cmd : "<<NULL>>");
+#endif
+			*kbd_data = *suffix;
+			return ((uchar *)cmd);
+		}
+	}
+#if 0
+	printf ("### Delete PREBOOT\n");
+#endif
+	*kbd_data = '\0';
+	return (NULL);
+}
+#endif /* CONFIG_PREBOOT */
+
+/*---------------Board Special Commands: PIC read/write ---------------*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+/***********************************************************************
+F* Function:     int do_pic (cmd_tbl_t *cmdtp, int flag,
+F*                           int argc, char *argv[]) P*A*Z*
+ *
+P* Parameters:   cmd_tbl_t *cmdtp
+P*                - Pointer to our command table entry
+P*               int flag
+P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
+P*                  a repetition
+P*               int argc
+P*                - Argument count
+P*               char *argv[]
+P*                - Array of the actual arguments
+P*
+P* Returnvalue:  int
+P*                - 0  The command was handled successfully
+P*                  1  An error occurred
+ *
+Z* Intention:    Implement the "pic [read|write]" commands.
+Z*               The read subcommand takes one argument, the register,
+Z*               whereas the write command takes two, the register and
+Z*               the new value.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	uchar reg, val;
+
+	switch (argc) {
+	case 3:					/* PIC read reg */
+		if (strcmp (argv[1], "read") != 0)
+			break;
+
+		reg = simple_strtoul (argv[2], NULL, 16);
+
+		printf ("PIC read: reg %02x: %02x\n\n", reg, pic_read (reg));
+
+		return 0;
+	case 4:					/* PIC write reg val */
+		if (strcmp (argv[1], "write") != 0)
+			break;
+
+		reg = simple_strtoul (argv[2], NULL, 16);
+		val = simple_strtoul (argv[3], NULL, 16);
+
+		printf ("PIC write: reg %02x val 0x%02x: %02x => ",
+				reg, val, pic_read (reg));
+		pic_write (reg, val);
+		printf ("%02x\n\n", pic_read (reg));
+		return 0;
+	default:
+		break;
+	}
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+U_BOOT_CMD(
+	pic,	4,	1,	do_pic,
+	"pic     - read and write PIC registers\n",
+	"read  reg      - read PIC register `reg'\n"
+	"pic write reg val  - write value `val' to PIC register `reg'\n"
+);
+
+/***********************************************************************
+F* Function:     int do_kbd (cmd_tbl_t *cmdtp, int flag,
+F*                           int argc, char *argv[]) P*A*Z*
+ *
+P* Parameters:   cmd_tbl_t *cmdtp
+P*                - Pointer to our command table entry
+P*               int flag
+P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
+P*                  a repetition
+P*               int argc
+P*                - Argument count
+P*               char *argv[]
+P*                - Array of the actual arguments
+P*
+P* Returnvalue:  int
+P*                - 0 is always returned.
+ *
+Z* Intention:    Implement the "kbd" command.
+Z*               The keyboard status is read.  The result is printed on
+Z*               the console and written into the "keybd" environment
+Z*               variable.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	char keybd_env[2 * KEYBD_DATALEN + 1];
+	uchar val;
+	int i;
+
+#if 0 /* Done in kbd_init */
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	puts ("Keys:");
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+		printf (" %02x", kbd_data[i]);
+	}
+	putc ('\n');
+	setenv ("keybd", keybd_env);
+	return 0;
+}
+
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
+	"kbd     - read keyboard status\n",
+	NULL
+);
+
+/* Read and set LSB switch */
+#define CFG_PC_TXD1_ENA		0x0008		/* PC.12 */
+
+/***********************************************************************
+F* Function:     int do_lsb (cmd_tbl_t *cmdtp, int flag,
+F*                           int argc, char *argv[]) P*A*Z*
+ *
+P* Parameters:   cmd_tbl_t *cmdtp
+P*                - Pointer to our command table entry
+P*               int flag
+P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
+P*                  a repetition
+P*               int argc
+P*                - Argument count
+P*               char *argv[]
+P*                - Array of the actual arguments
+P*
+P* Returnvalue:  int
+P*                - 0  The command was handled successfully
+P*                  1  An error occurred
+ *
+Z* Intention:    Implement the "lsb [on|off]" commands.
+Z*               The lsb is switched according to the first parameter by
+Z*               by signaling the PIC I/O expander.
+Z*               Called with no arguments, the current setting is
+Z*               printed.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	uchar val;
+	immap_t *immr = (immap_t *) CFG_IMMR;
+
+	switch (argc) {
+	case 1:					/* lsb - print setting */
+		val = pic_read (0x60);
+		printf ("LSB is o%s\n", (val & 0x20) ? "n" : "ff");
+		return 0;
+	case 2:					/* lsb on or lsb off - set switch */
+		val = pic_read (0x60);
+
+		if (strcmp (argv[1], "on") == 0) {
+			val |= 0x20;
+			immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdat |= CFG_PC_TXD1_ENA;
+			immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
+		} else if (strcmp (argv[1], "off") == 0) {
+			val &= ~0x20;
+			immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdat &= ~(CFG_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
+		} else {
+			break;
+		}
+		pic_write (0x60, val);
+		return 0;
+	default:
+		break;
+	}
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	lsb,	2,	1,	do_lsb,
+	"lsb     - check and set LSB switch\n",
+	"on  - switch LSB on\n"
+	"lsb off - switch LSB off\n"
+	"lsb     - print current setting\n"
+);
+
+#endif /* CFG_CMD_BSP */
+
+/*----------------------------- Utilities -----------------------------*/
+/***********************************************************************
+F* Function:     uchar pic_read (uchar reg) P*A*Z*
+ *
+P* Parameters:   uchar reg
+P*                - Register to read
+P*
+P* Returnvalue:  uchar
+P*                - Value read from register
+ *
+Z* Intention:    Read a register from the PIC I/O expander.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+uchar pic_read (uchar reg)
+{
+	return (i2c_reg_read (CFG_I2C_PICIO_ADDR, reg));
+}
+
+/***********************************************************************
+F* Function:     void pic_write (uchar reg, uchar val) P*A*Z*
+ *
+P* Parameters:   uchar reg
+P*                - Register to read
+P*               uchar val
+P*                - Value to write
+P*
+P* Returnvalue:  none
+ *
+Z* Intention:    Write to a register on the PIC I/O expander.
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+void pic_write (uchar reg, uchar val)
+{
+	i2c_reg_write (CFG_I2C_PICIO_ADDR, reg, val);
+}
+
+/*---------------------- Board Control Functions ----------------------*/
+/***********************************************************************
+F* Function:     void board_poweroff (void) P*A*Z*
+ *
+P* Parameters:   none
+P*
+P* Returnvalue:  none
+ *
+Z* Intention:    Turn off the battery power and loop endless, so this
+Z*               should better be the last function you call...
+ *
+D* Design:       wd@denx.de
+C* Coding:       wd@denx.de
+V* Verification: dzu@denx.de
+ ***********************************************************************/
+void board_poweroff (void)
+{
+    /* Turn battery off */
+    ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13));
+
+    while (1);
+}
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar val;
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	return (compare_magic(kbd_data, (uchar *)CONFIG_MODEM_KEY_MAGIC) == 0);
+}
+#endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar val;
+
+	/* Read keys */
+	val = KEYBD_CMD_READ_KEYS;
+	i2c_write (kbd_addr, 0, 0, &val, 1);
+	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
+}
+#endif
diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds
new file mode 100755
index 0000000..6505d45
--- /dev/null
+++ b/board/lwmon/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    common/environment.o(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug
new file mode 100755
index 0000000..828afbb
--- /dev/null
+++ b/board/lwmon/u-boot.lds.debug
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/m5272c3/Makefile b/board/m5272c3/Makefile
new file mode 100755
index 0000000..e5d8446
--- /dev/null
+++ b/board/m5272c3/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/m5272c3/config.mk b/board/m5272c3/config.mk
new file mode 100755
index 0000000..ccb2cf7
--- /dev/null
+++ b/board/m5272c3/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xffe00000
diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c
new file mode 100755
index 0000000..fb91843
--- /dev/null
+++ b/board/m5272c3/flash.c
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_PL160CB & FLASH_TYPEMASK):
+		printf ("AM29PL160CB (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:
+}
+
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_PL160CB & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j == 0) {
+				/* 1st is 16 KiB */
+				flash_info[i].start[j] = flashbase;
+			}
+			if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x4000 + 0x2000 * (j - 1);
+			}
+			if (j == 3) {
+				/* 4th is 224 KiB */
+				flash_info[i].start[j] = flashbase + 0x8000;
+			}
+			if ((j >= 4) && (j <= 10)) {
+				/* rest is 256 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x40000 + 0x40000 * (j -
+									 4);
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + 0x3ffff, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		set_timer (0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
diff --git a/board/m5272c3/m5272c3.c b/board/m5272c3/m5272c3.c
new file mode 100755
index 0000000..0dfeaf2
--- /dev/null
+++ b/board/m5272c3/m5272c3.c
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5272.h>
+#include <asm/immap_5272.h>
+
+
+int checkboard (void) {
+	puts ("Board: ");
+	puts("MOTOROLA MCF5272C3 EVB\n");
+	return 0;
+	};
+
+long int initdram (int board_type) {
+	volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR);
+
+	sdp->sdram_sdtr = 0xf539;
+	sdp->sdram_sdcr = 0x4211;
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *)0) = 0;
+
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+	};
+
+int testdram (void) {
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}
diff --git a/board/m5272c3/u-boot.lds b/board/m5272c3/u-boot.lds
new file mode 100755
index 0000000..f7dc070
--- /dev/null
+++ b/board/m5272c3/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o		(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/m5282evb/Makefile b/board/m5282evb/Makefile
new file mode 100755
index 0000000..e5d8446
--- /dev/null
+++ b/board/m5282evb/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/m5282evb/config.mk b/board/m5282evb/config.mk
new file mode 100755
index 0000000..8484307
--- /dev/null
+++ b/board/m5282evb/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x20000
diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c
new file mode 100755
index 0000000..ff70783
--- /dev/null
+++ b/board/m5282evb/flash.c
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_PL160CB & FLASH_TYPEMASK):
+		printf ("AM29PL160CB (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:
+}
+
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_PL160CB & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j == 0) {
+				/* 1st is 16 KiB */
+				flash_info[i].start[j] = flashbase;
+			}
+			if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x4000 + 0x2000 * (j - 1);
+			}
+			if (j == 3) {
+				/* 4th is 32 KiB */
+				flash_info[i].start[j] = flashbase + 0x8000;
+			}
+			if ((j >= 4) && (j <= 34)) {
+				/* rest is 256 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x10000 + 0x10000 * (j -
+									 4);
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + 0xffff, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		set_timer (0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}
diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c
new file mode 100755
index 0000000..a08af68
--- /dev/null
+++ b/board/m5282evb/m5282evb.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int checkboard (void)
+{
+	puts ("MOTOROLA M5272EVB Evaluation Board\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return 0x1000000;
+}
diff --git a/board/m5282evb/u-boot.lds b/board/m5282evb/u-boot.lds
new file mode 100755
index 0000000..c461d20
--- /dev/null
+++ b/board/m5282evb/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/string.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o	(.text)
+    lib_generic/zlib.o	(.text)
+
+/*    . = env_offset; */
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+    .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile
new file mode 100755
index 0000000..3e8376c
--- /dev/null
+++ b/board/mbx8xx/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o vpd.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mbx8xx/config.mk b/board/mbx8xx/config.mk
new file mode 100755
index 0000000..d5e8ed2
--- /dev/null
+++ b/board/mbx8xx/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MBX8xx boards
+#
+
+TEXT_BASE = 0xfe000000
+/*TEXT_BASE  = 0x00200000 */
diff --git a/board/mbx8xx/csr.h b/board/mbx8xx/csr.h
new file mode 100755
index 0000000..832e924
--- /dev/null
+++ b/board/mbx8xx/csr.h
@@ -0,0 +1,60 @@
+#ifndef __csr_h
+#define __csr_h
+
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Control and Status Register definitions for the MBX
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* bits for control register #1 / status register #1 */
+#define CSR1_ETEN       0x80    /* Ethernet Transceiver Enabled             */
+#define CSR1_ELEN       0x40    /* Ethernet XCVR in Internal Loopback       */
+#define CSR1_EAEN       0x20    /* Auto selection TP/AUI Enabled            */
+#define CSR1_TPEN       0x10    /* TP manually selected                     */
+#define CSR1_FDDIS      0x08    /* Full Duplex Mode disabled                */
+#define CSR1_FCTEN      0x04    /* Collision Testing of XCVR disabled       */
+#define CSR1_COM1EN     0x02    /* COM1 signals routed to RS232 Transceiver */
+#define CSR1_XCVRDIS    0x01    /* Onboard RS232 Transceiver Disabled       */
+
+/* bits for control register #2 */
+#define CR2_VDDSEL      0xC0    /* PCMCIA Supply Voltage                    */
+#define CR2_VPPSEL      0x30    /* PCMCIA Programming Voltage               */
+#define CR2_BRDFAIL     0x08    /* Board fail                               */
+#define CR2_SWS1        0x04    /* Software Status #2 LED                   */
+#define CR2_SWS2        0x02    /* Software Status #2 LED                   */
+#define CR2_QSPANRST    0x01    /* Reset QSPAN                              */
+
+/* bits for status register #2 */
+#define SR2_VDDSEL      0xC0    /* PCMCIA Supply Voltage                    */
+#define SR2_VPPSEL      0x30    /* PCMCIA Programming Voltage               */
+#define SR2_BATGD       0x08    /* Low Voltage indication for onboard bat   */
+#define SR2_NVBATGD     0x04    /* Low Voltage indication for NVRAM         */
+#define SR2_RDY         0x02    /* Flash programming status bit             */
+#define SR2_FT          0x01    /* Reserved for Factory test purposes       */
+
+#define MBX_CSR1 (*((uchar *)CFG_CSR_BASE))
+#define MBX_CSR2 (*((uchar *)CFG_CSR_BASE + 1))
+
+#endif /* __csr_h */
diff --git a/board/mbx8xx/dimm.h b/board/mbx8xx/dimm.h
new file mode 100755
index 0000000..b40f112
--- /dev/null
+++ b/board/mbx8xx/dimm.h
@@ -0,0 +1,98 @@
+#ifndef __dimm_h
+#define __dimm_h
+
+/*
+ * Module name: %M%
+ * Description:
+ * Serial Presence Detect Definitions Module
+ * SCCS identification: %I%
+ * Branch: %B%
+ * Sequence: %S%
+ * Date newest applied delta was created (MM/DD/YY): %G%
+ * Time newest applied delta was created (HH:MM:SS): %U%
+ * SCCS file name %F%
+ * Fully qualified SCCS file name:
+ * %P%
+ * Copyright:
+ * (C) COPYRIGHT MOTOROLA, INC. 1996
+ * ALL RIGHTS RESERVED
+ * Notes:
+ * 1. All data was taken from an IBM application note titled
+ * "Serial Presence Detect Definitions".
+ * History:
+ * Date Who
+ *
+ * 10/24/96 Rob Baxter
+ * Initial release.
+ *
+ */
+
+/*
+ * serial PD byte assignment address map (256 byte EEPROM)
+ */
+typedef struct dimm
+{
+	uchar n_bytes; /* 00 number of bytes written/used */
+	uchar t_bytes; /* 01 total number of bytes in serial PD device */
+	uchar fmt; /* 02 fundamental memory type (FPM/EDO/SDRAM) */
+	uchar n_row; /* 03 number of rows */
+	uchar n_col; /* 04 number of columns */
+	uchar n_banks; /* 05 number of banks */
+	uchar data_w_lo; /* 06 data width */
+	uchar data_w_hi; /* 07 data width */
+	uchar ifl; /* 08 interface levels */
+	uchar a_ras; /* 09 RAS access */
+	uchar a_cas; /* 0A CAS access */
+	uchar ct; /* 0B configuration type (non-parity/parity/ECC) */
+	uchar refresh_rt; /* 0C refresh rate/type */
+	uchar p_dram_o; /* 0D primary DRAM organization */
+	uchar s_dram_o; /* 0E secondary DRAM organization (parity/ECC-checkbits) */
+	uchar reserved[17]; /* 0F reserved fields for future offerings */
+	uchar ss_info[32]; /* 20 superset information (may be used in the future) */
+	uchar m_info[64]; /* 40 manufacturer information (optional) */
+	uchar unused[128]; /* 80 unused storage locations */
+} dimm_t;
+
+/*
+ * memory type definitions
+ */
+#define DIMM_MT_FPM 1 /* standard FPM (fast page mode) DRAM */
+#define DIMM_MT_EDO 2 /* EDO (extended data out) */
+#define DIMM_MT_PN 3 /* pipelined nibble */
+#define DIMM_MT_SDRAM 4 /* SDRAM (synchronous DRAM) */
+
+/*
+ * row addresses definitions
+ */
+#define DIMM_RA_RDNDNT (1<<7) /* redundant addressing */
+#define DIMM_RA_MASK 0x7f /* number of row addresses mask */
+
+/*
+ * module interface levels definitions
+ */
+#define DIMM_IFL_TTL 0 /* TTL/5V tolerant */
+#define DIMM_IFL_LVTTL 1 /* LVTTL (not 5V tolerant) */
+#define DIMM_IFL_HSTL15 2 /* HSTL 1.5 */
+#define DIMM_IFL_SSTL33 3 /* SSTL 3.3 */
+#define DIMM_IFL_SSTL25 4 /* SSTL 2.5 */
+
+/*
+ * DIMM configuration type definitions
+ */
+#define DIMM_CT_NONE 0 /* none */
+#define DIMM_CT_PARITY 1 /* parity */
+#define DIMM_CT_ECC 2 /* ECC */
+
+/*
+ * row addresses definitions
+ */
+#define DIMM_RRT_SR (1<<7) /* self refresh flag */
+#define DIMM_RRT_MASK 0x7f /* refresh rate mask */
+#define DIMM_RRT_NRML 0x00 /* normal (15.625us) */
+#define DIMM_RRT_R_3_9 0x01 /* reduced .25x (3.9us) */
+#define DIMM_RRT_R_7_8 0x02 /* reduced .5x (7.8us) */
+#define DIMM_RRT_E_31_3 0x03 /* extended 2x (31.3us) */
+#define DIMM_RRT_E_62_5 0x04 /* extended 4x (62.5us) */
+#define DIMM_RRT_E_125 0x05 /* extended 8x (125us) */
+
+#endif /* __dimm_h */
diff --git a/board/mbx8xx/flash.c b/board/mbx8xx/flash.c
new file mode 100755
index 0000000..a491f7b
--- /dev/null
+++ b/board/mbx8xx/flash.c
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AM290[48]0B devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "vpd.h"
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    unsigned long size, totsize;
+    int i;
+    ulong addr;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    totsize = 0;
+    addr = 0xfc000000;
+    for(i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	size = flash_get_size((vu_long *)addr, &flash_info[i]);
+	if (flash_info[i].flash_id == FLASH_UNKNOWN)
+	  break;
+	totsize += size;
+	addr += size;
+    }
+
+    addr = 0xfe000000;
+    for(i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+
+	size = flash_get_size((vu_long *)addr, &flash_info[i]);
+	if (flash_info[i].flash_id == FLASH_UNKNOWN)
+	  break;
+	totsize += size;
+	addr += size;
+    }
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+    /* monitor protection ON by default */
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_MONITOR_BASE,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+    return (totsize);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id >> 16) {
+    case 0x1:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F080B:
+	printf ("AM29F080B (8 Mbit)\n");
+	break;
+    case AMD_ID_F016D:
+	printf ("AM29F016D (16 Mbit)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+	    info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	if ((i % 5) == 0)
+	  printf ("\n   ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "     "
+		);
+    }
+    printf ("\n");
+    return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    ulong vendor, devid;
+    ulong base = (ulong)addr;
+
+    /* Write auto select command: read Manufacturer ID */
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x90909090;
+
+    vendor = addr[0];
+    devid = addr[1] & 0xff;
+
+    /* only support AMD */
+    if (vendor != 0x01010101) {
+	return 0;
+    }
+
+    vendor &= 0xf;
+    devid &= 0xff;
+
+    if (devid == AMD_ID_F040B) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 8;
+	info->size         = info->sector_count * 0x10000;
+    }
+    else if (devid == AMD_ID_F080B) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 16;
+	info->size         = 4 * info->sector_count * 0x10000;
+    }
+    else if (devid == AMD_ID_F016D) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 32;
+	info->size         = 4 * info->sector_count * 0x10000;
+    }
+    else {
+	printf ("## Unknown Flash Type: %08lx\n", devid);
+	return 0;
+    }
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	addr = (volatile unsigned long *)(info->start[i]);
+	info->protect[i] = addr[2] & 1;
+    }
+
+    /*
+     * Prevent writes to uninitialized FLASH.
+     */
+    if (info->flash_id != FLASH_UNKNOWN) {
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0;	/* reset bank */
+    }
+
+    return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0XAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x80808080;
+    addr[0x0555] = 0XAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) {	/* not protected */
+	    addr = (vu_long*)(info->start[sect]);
+	    addr[0] = 0x30303030;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+      goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_long*)(info->start[l_sect]);
+    while ((addr[0] & 0x80808080) != 0x80808080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {	/* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+    DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned long *)info->start[0];
+    addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_long *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0xA0A0A0A0;
+
+    *((vu_long *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c
new file mode 100755
index 0000000..9a9bf80
--- /dev/null
+++ b/board/mbx8xx/mbx8xx.c
@@ -0,0 +1,379 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Board specific routines for the MBX
+ *
+ * - initialisation
+ * - interface to VPD data (mac address, clock speeds)
+ * - memory controller
+ * - serial io initialisation
+ * - ethernet io initialisation
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <commproc.h>
+#include <mpc8xx.h>
+#include "dimm.h"
+#include "vpd.h"
+#include "csr.h"
+
+/* ------------------------------------------------------------------------- */
+
+static const uint sdram_table_40[] = {
+	/* DRAM - single read. (offset 0 in upm RAM)
+	 */
+	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
+	0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - burst read. (offset 8 in upm RAM)
+	 */
+	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
+	0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
+	0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - single write. (offset 18 in upm RAM)
+	 */
+	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x33FF4804,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - burst write. (offset 20 in upm RAM)
+	 */
+	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
+	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
+	0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* refresh  (offset 30 in upm RAM)
+	 */
+	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
+	0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* exception. (offset 3c in upm RAM)
+	 */
+	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
+};
+
+static const uint sdram_table_50[] = {
+	/* DRAM - single read. (offset 0 in upm RAM)
+	 */
+	0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
+	0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - burst read. (offset 8 in upm RAM)
+	 */
+	0xCFAFC004, 0X0FAFC404, 0X0CAF8C04, 0X00AF0C04,
+  /*	0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C04,	*/
+	0X07AF0C08, 0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08,
+	0X0CAF0C04, 0X01AF0C04, 0X0FAF0C08, 0X0CAF0C04,
+  /*	0X10AF0C04, 0XF0AFC000, 0XF3FF4805, 0XFFFFC005,	*/
+	0X10AF0C04, 0XF0AFC000, 0XF3BF4805, 0XFFFFC005,
+
+	/* DRAM - single write. (offset 18 in upm RAM)
+	 */
+	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
+	0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* DRAM - burst write. (offset 20 in upm RAM)
+	 */
+	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
+	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
+	0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* refresh  (offset 30 in upm RAM)
+	 */
+	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
+	0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
+	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
+
+	/* exception. (offset 3c in upm RAM)
+	 */
+	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
+};
+
+/* ------------------------------------------------------------------------- */
+
+static unsigned int get_reffreq(void);
+static unsigned int board_get_cpufreq(void);
+
+void mbx_init (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	ulong speed, refclock, plprcr, sccr;
+	ulong br0_32 = memctl->memc_br0 & 0x400;
+
+	/* real-time clock status and control register */
+	immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
+	immr->im_sit.sit_rtcsc = 0x00C3;
+
+	/* SIEL and SIMASK Registers (see MBX PRG 2-3) */
+	immr->im_siu_conf.sc_simask = 0x00000000;
+	immr->im_siu_conf.sc_siel = 0xAAAA0000;
+	immr->im_siu_conf.sc_tesr = 0xFFFFFFFF;
+
+	/*
+	 * Prepare access to i2c bus. The MBX offers 3 devices on the i2c bus:
+	 * 1. Vital Product Data (contains clock speeds, MAC address etc, see vpd.h)
+	 * 2. RAM  Specs (see dimm.h)
+	 * 2. DIMM Specs (see dimm.h)
+	 */
+	vpd_init ();
+
+	/* system clock and reset control register */
+	immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
+	sccr = immr->im_clkrst.car_sccr;
+	sccr &= SCCR_MASK;
+	sccr |= CFG_SCCR;
+	immr->im_clkrst.car_sccr = sccr;
+
+	speed = board_get_cpufreq ();
+	refclock = get_reffreq ();
+
+#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
+	plprcr = CFG_PLPRCR;
+#else
+	plprcr = immr->im_clkrst.car_plprcr;
+	plprcr &= PLPRCR_MF_MSK;	/* isolate MF field */
+	plprcr |= CFG_PLPRCR;		/* reset control bits   */
+#endif
+
+#ifdef CFG_USE_OSCCLK			/* See doc/README.MBX ! */
+	plprcr |= ((speed + refclock / 2) / refclock - 1) << 20;
+#endif
+
+	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+	immr->im_clkrst.car_plprcr = plprcr;
+
+	/*
+	 * preliminary setup of memory controller:
+	 * - map Flash, otherwise configuration/status
+	 *    registers won't be accessible when read
+	 *    by board_init_f.
+	 * - map NVRAM and configuation/status registers.
+	 * - map pci registers.
+	 * - DON'T map ram yet, this is done in initdram().
+	 */
+	switch (speed / 1000000) {
+	case 40:
+		memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
+		memctl->memc_or0 = 0xFF800930;
+		memctl->memc_or4 = CFG_NVRAM_OR | 0x920;
+		memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
+		break;
+	case 50:
+		memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
+		memctl->memc_or0 = 0xFF800940;
+		memctl->memc_or4 = CFG_NVRAM_OR | 0x930;
+		memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
+		break;
+	default:
+		hang ();
+		break;
+	}
+#ifdef CONFIG_USE_PCI
+	memctl->memc_or5 = CFG_PCIMEM_OR;
+	memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001;
+	memctl->memc_or6 = CFG_PCIBRIDGE_OR;
+	memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001;
+#endif
+	/*
+	 * FIXME: I do not understand why I have to call this to
+	 * initialise the control register here before booting from
+	 * the PCMCIA card but if I do not the Linux kernel falls
+	 * over in a big heap. If you can answer this question I
+	 * would like to know about it.
+	 */
+	board_ether_init();
+}
+
+void board_serial_init (void)
+{
+	MBX_CSR1 &= ~(CSR1_COM1EN | CSR1_XCVRDIS);
+}
+
+void board_ether_init (void)
+{
+	MBX_CSR1 &= ~(CSR1_EAEN | CSR1_ELEN);
+	MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS;
+}
+
+static unsigned int board_get_cpufreq (void)
+{
+#ifndef CONFIG_8xx_GCLK_FREQ
+	vpd_packet_t *packet;
+
+	packet = vpd_find_packet (VPD_PID_ICS);
+	return *((ulong *) packet->data);
+#else
+	return((unsigned int)CONFIG_8xx_GCLK_FREQ );
+#endif /* CONFIG_8xx_GCLK_FREQ */
+}
+
+static unsigned int get_reffreq (void)
+{
+	vpd_packet_t *packet;
+
+	packet = vpd_find_packet (VPD_PID_RCS);
+	return *((ulong *) packet->data);
+}
+
+void board_get_enetaddr (uchar * addr)
+{
+	int i;
+	vpd_packet_t *packet;
+
+	packet = vpd_find_packet (VPD_PID_EA);
+	for (i = 0; i < 6; i++)
+		addr[i] = packet->data[i];
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	vpd_packet_t *packet;
+	int i;
+	const char *const fmt =
+		"\n	 *** Warning: Low Battery Status - %s Battery ***";
+
+	puts ("Board: ");
+
+	packet = vpd_find_packet (VPD_PID_PID);
+	for (i = 0; i < packet->size; i++) {
+		serial_putc (packet->data[i]);
+	}
+	packet = vpd_find_packet (VPD_PID_MT);
+	for (i = 0; i < packet->size; i++) {
+		serial_putc (packet->data[i]);
+	}
+	serial_putc ('(');
+	packet = vpd_find_packet (VPD_PID_FAN);
+	for (i = 0; i < packet->size; i++) {
+		serial_putc (packet->data[i]);
+	}
+	serial_putc (')');
+
+	if (!(MBX_CSR2 & SR2_BATGD))
+		printf (fmt, "On-Board");
+	if (!(MBX_CSR2 & SR2_NVBATGD))
+		printf (fmt, "NVRAM");
+
+	serial_putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static ulong get_ramsize (dimm_t * dimm)
+{
+	ulong size = 0;
+
+	if (dimm->fmt == 1 || dimm->fmt == 2 || dimm->fmt == 3
+		|| dimm->fmt == 4) {
+		size = (1 << (dimm->n_row + dimm->n_col)) * dimm->n_banks *
+			((dimm->data_w_hi << 8 | dimm->data_w_lo) / 8);
+	}
+
+	return size;
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long ram_sz = 0;
+	unsigned long dimm_sz = 0;
+	dimm_t vpd_dimm, vpd_dram;
+	unsigned int speed = board_get_cpufreq () / 1000000;
+
+	if (vpd_read (0xa2, (uchar *) & vpd_dimm, sizeof (vpd_dimm), 0) > 0) {
+		dimm_sz = get_ramsize (&vpd_dimm);
+	}
+	if (vpd_read (0xa6, (uchar *) & vpd_dram, sizeof (vpd_dram), 0) > 0) {
+		ram_sz = get_ramsize (&vpd_dram);
+	}
+
+	/*
+	 * Only initialize memory controller when running from FLASH.
+	 * When running from RAM, don't touch it.
+	 */
+	if ((ulong) initdram & 0xff000000) {
+		ulong dimm_bank;
+		ulong br0_32 = memctl->memc_br0 & 0x400;
+
+		switch (speed) {
+		case 40:
+			upmconfig (UPMA, (uint *) sdram_table_40,
+					   sizeof (sdram_table_40) / sizeof (uint));
+			memctl->memc_mptpr = 0x0200;
+			memctl->memc_mamr = dimm_sz ? 0x06801000 : 0x13801000;
+			memctl->memc_or7 = 0xff800930;
+			memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
+			break;
+		case 50:
+			upmconfig (UPMA, (uint *) sdram_table_50,
+					   sizeof (sdram_table_50) / sizeof (uint));
+			memctl->memc_mptpr = 0x0200;
+			memctl->memc_mamr = dimm_sz ? 0x08801000 : 0x1880100;
+			memctl->memc_or7 = 0xff800940;
+			memctl->memc_br7 = 0xfc000000 | (br0_32 ^ br0_32) | 1;
+			break;
+		default:
+			hang ();
+			break;
+		}
+
+		/* now map ram and dimm, largest one first */
+		dimm_bank = dimm_sz / 2;
+		if (!dimm_sz) {
+			memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
+			memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
+			memctl->memc_br2 = 0;
+			memctl->memc_br3 = 0;
+		} else if (ram_sz > dimm_bank) {
+			memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
+			memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
+			memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
+			memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81;
+			memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
+			memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) \
+								     | 0x81;
+		} else {
+			memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
+			memctl->memc_br2 = CFG_SDRAM_BASE | 0x81;
+			memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
+			memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81;
+			memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
+			memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81;
+		}
+	}
+
+	return ram_sz + dimm_sz;
+}
diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds
new file mode 100755
index 0000000..1400cea
--- /dev/null
+++ b/board/mbx8xx/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug
new file mode 100755
index 0000000..650572d
--- /dev/null
+++ b/board/mbx8xx/u-boot.lds.debug
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mbx8xx/vpd.c b/board/mbx8xx/vpd.c
new file mode 100755
index 0000000..6f88352
--- /dev/null
+++ b/board/mbx8xx/vpd.c
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Code in faintly related to linux/arch/ppc/8xx_io:
+ * MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
+ *
+ * This file implements functions to read the MBX's Vital Product Data
+ * (VPD). I can't use the more general i2c code in mpc8xx/... since I need
+ * the VPD at a time where there is no RAM available yet. Hence the VPD is
+ * read into a special area in the DPRAM (see config_MBX.h::CFG_DPRAMVPD).
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#ifdef CONFIG_8xx
+#include <commproc.h>
+#endif
+#include "vpd.h"
+
+/* Location of receive/transmit buffer descriptors
+ * Allocate one transmit bd and one receive bd.
+ * IIC_BD_FREE points to free bd space which we'll use as tx buffer.
+ */
+#define IIC_BD_TX1     (BD_IIC_START + 0*sizeof(cbd_t))
+#define IIC_BD_TX2     (BD_IIC_START + 1*sizeof(cbd_t))
+#define IIC_BD_RX      (BD_IIC_START + 2*sizeof(cbd_t))
+#define IIC_BD_FREE    (BD_IIC_START + 3*sizeof(cbd_t))
+
+/* FIXME -- replace 0x2000 with offsetof */
+#define VPD_P ((vpd_t *)(CFG_IMMR + 0x2000 + CFG_DPRAMVPD))
+
+/* transmit/receive buffers */
+#define IIC_RX_LENGTH 128
+
+#define WITH_MICROCODE_PATCH
+
+vpd_packet_t * vpd_find_packet(u_char ident)
+{
+    vpd_packet_t *packet;
+    vpd_t *vpd = VPD_P;
+
+    packet = (vpd_packet_t *)&vpd->packets;
+    while ((packet->identifier != ident) && packet->identifier != 0xFF)
+    {
+	packet = (vpd_packet_t *)((char *)packet + packet->size + 2);
+    }
+    return packet;
+}
+
+void vpd_init(void)
+{
+    volatile immap_t  *im = (immap_t *)CFG_IMMR;
+    volatile cpm8xx_t *cp = &(im->im_cpm);
+    volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
+    volatile iic_t *iip;
+#ifdef WITH_MICROCODE_PATCH
+    ulong reloc = 0;
+#endif
+
+    iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
+
+    /*
+     * kludge: when running from flash, no microcode patch can be
+     * installed. However, the DPMEM usually contains non-zero
+     * garbage at the relocatable patch base location, so lets clear
+     * it now. This way the rest of the code can support the microcode
+     * patch dynamically.
+     */
+    if ((ulong)vpd_init & 0xff000000)
+      iip->iic_rpbase = 0;
+
+#ifdef WITH_MICROCODE_PATCH
+    /* Check for and use a microcode relocation patch. */
+    if ((reloc = iip->iic_rpbase))
+      iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
+#endif
+    /* Initialize Port B IIC pins */
+    cp->cp_pbpar |= 0x00000030;
+    cp->cp_pbdir |= 0x00000030;
+    cp->cp_pbodr |= 0x00000030;
+
+    i2c->i2c_i2mod = 0x04;  /* filter clock */
+    i2c->i2c_i2add = 0x34;	/* select an arbitrary (unique) address */
+    i2c->i2c_i2brg = 0x07;  /* make clock run maximum slow	*/
+    i2c->i2c_i2cmr = 0x00;  /* disable interrupts */
+    i2c->i2c_i2cer = 0x1f;  /* clear events */
+    i2c->i2c_i2com = 0x01;  /* configure i2c to work as master */
+
+    if (vpd_read(0xa4, (uchar*)VPD_P, VPD_EEPROM_SIZE, 0) != VPD_EEPROM_SIZE)
+    {
+	hang();
+    }
+}
+
+
+/* Read from I2C.
+ * This is a two step process.  First, we send the "dummy" write
+ * to set the device offset for the read.  Second, we perform
+ * the read operation.
+ */
+int vpd_read(uint iic_device, uchar *buf, int count, int offset)
+{
+    volatile immap_t  *im = (immap_t *)CFG_IMMR;
+    volatile cpm8xx_t *cp = &(im->im_cpm);
+    volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
+    volatile iic_t *iip;
+    volatile cbd_t *tbdf1, *tbdf2, *rbdf;
+    uchar *tb;
+    uchar event;
+#ifdef WITH_MICROCODE_PATCH
+    ulong reloc = 0;
+#endif
+
+    iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
+#ifdef WITH_MICROCODE_PATCH
+    /* Check for and use a microcode relocation patch. */
+    if ((reloc = iip->iic_rpbase))
+      iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
+#endif
+    tbdf1 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX1];
+    tbdf2 = (cbd_t *)&cp->cp_dpmem[IIC_BD_TX2];
+    rbdf  = (cbd_t *)&cp->cp_dpmem[IIC_BD_RX];
+
+    /* Send a "dummy write" operation.  This is a write request with
+     * only the offset sent, followed by another start condition.
+     * This will ensure we start reading from the first location
+     * of the EEPROM.
+     */
+    tb = (uchar*)&cp->cp_dpmem[IIC_BD_FREE];
+    tb[0] = iic_device & 0xfe;	/* device address */
+    tb[1] = offset;	        /* offset */
+    tbdf1->cbd_bufaddr = (uint)tb;
+    tbdf1->cbd_datlen = 2;
+    tbdf1->cbd_sc = 0x8400;
+
+    tb += 2;
+    tb[0] = iic_device | 1;	/* device address */
+    tbdf2->cbd_bufaddr = (uint)tb;
+    tbdf2->cbd_datlen = count+1;
+    tbdf2->cbd_sc = 0xbc00;
+
+    rbdf->cbd_bufaddr = (uint)buf;
+    rbdf->cbd_datlen = 0;
+    rbdf->cbd_sc = 0xb000;
+
+    iip->iic_tbase = IIC_BD_TX1;
+    iip->iic_tbptr = IIC_BD_TX1;
+    iip->iic_rbase = IIC_BD_RX;
+    iip->iic_rbptr = IIC_BD_RX;
+    iip->iic_rfcr = 0x15;
+    iip->iic_tfcr = 0x15;
+    iip->iic_mrblr = count;
+    iip->iic_rstate = 0;
+    iip->iic_tstate = 0;
+
+    i2c->i2c_i2cer = 0x1f;  /* clear event mask */
+    i2c->i2c_i2mod |= 1;    /* enable iic operation */
+    i2c->i2c_i2com |= 0x80;	/* start master */
+
+    /* wait for IIC transfer */
+    do {
+	__asm__ volatile ("eieio");
+	event = i2c->i2c_i2cer;
+    } while (event == 0);
+
+    if ((event & 0x10) || (event & 0x04)) {
+	count = -1;
+	goto bailout;
+    }
+
+bailout:
+    i2c->i2c_i2mod &= ~1;   /* turn off iic operation */
+    i2c->i2c_i2cer = 0x1f;  /* clear event mask */
+
+    return count;
+}
diff --git a/board/mbx8xx/vpd.h b/board/mbx8xx/vpd.h
new file mode 100755
index 0000000..1d9eb7f
--- /dev/null
+++ b/board/mbx8xx/vpd.h
@@ -0,0 +1,119 @@
+#ifndef __vpd_h
+#define __vpd_h
+
+/*
+ * Module name: %M%
+ * Description:
+ * Vital Product Data (VPD) Header Module
+ * SCCS identification: %I%
+ * Branch: %B%
+ * Sequence: %S%
+ * Date newest applied delta was created (MM/DD/YY): %G%
+ * Time newest applied delta was created (HH:MM:SS): %U%
+ * SCCS file name %F%
+ * Fully qualified SCCS file name:
+ * %P%
+ * Copyright:
+ * (C) COPYRIGHT MOTOROLA, INC. 1996
+ * ALL RIGHTS RESERVED
+ * Notes:
+ * History:
+ * Date Who
+ *
+ * 10/24/96 Rob Baxter
+ * Initial release.
+ *
+ */
+
+#define VPD_EEPROM_SIZE 256 /* EEPROM size in bytes */
+
+/*
+ * packet tuple identifiers
+ *
+ * 0x0D - 0xBF reserved
+ * 0xC0 - 0xFE user defined
+ */
+#define VPD_PID_GI   0x00 /* guaranteed illegal */
+#define VPD_PID_PID  0x01 /* product identifier (ASCII) */
+#define VPD_PID_FAN  0x02 /* factory assembly-number (ASCII) */
+#define VPD_PID_SN   0x03 /* serial-number (ASCII) */
+#define VPD_PID_PCO  0x04 /* product configuration options(binary) */
+#define VPD_PID_ICS  0x05 /* internal clock speed in HZ (integer) */
+#define VPD_PID_ECS  0x06 /* external clock speed in HZ (integer) */
+#define VPD_PID_RCS  0x07 /* reference clock speed in HZ(integer) */
+#define VPD_PID_EA   0x08 /* ethernet address (binary) */
+#define VPD_PID_MT   0x09 /* microprocessor type (ASCII) */
+#define VPD_PID_CRC  0x0A /* EEPROM CRC (integer) */
+#define VPD_PID_FMC  0x0B /* FLASH memory configuration (binary) */
+#define VPD_PID_VLSI 0x0C /* VLSI revisions/versions (binary) */
+#define VPD_PID_TERM 0xFF /* termination */
+
+/*
+ * VPD structure (format)
+ */
+#define VPD_EYE_SIZE 8 /* eyecatcher size */
+typedef struct vpd_header
+{
+	uchar eyecatcher[VPD_EYE_SIZE]; /* eyecatcher - "MOTOROLA" */
+	ushort size; /* size of EEPROM */
+} vpd_header_t;
+
+#define VPD_DATA_SIZE (VPD_EEPROM_SIZE-sizeof(vpd_header_t))
+typedef struct vpd
+{
+	vpd_header_t header; /* header */
+	uchar packets[VPD_DATA_SIZE]; /* data */
+} vpd_t;
+
+/*
+ * packet tuple structure (format)
+ */
+typedef struct vpd_packet
+{
+    uchar identifier; /* identifier (PIDs above) */
+    uchar size;       /* size of the following data area */
+    uchar data[1];    /* data (size is dependent upon PID) */
+} vpd_packet_t;
+
+/*
+ * MBX product configuration options bit definitions
+ *
+ * Notes:
+ * 1. The bit numbering is reversed in perspective with the C compiler.
+ */
+#define PCO_BBRAM    (1<<0)  /* battery-backed RAM (BBRAM) and socket */
+#define PCO_BOOTROM  (1<<1)  /* boot ROM and socket (i.e., socketed FLASH) */
+#define PCO_KAPWR    (1<<2)  /* keep alive power source (lithium battey) and control circuit */
+#define PCO_ENET_TP  (1<<3)  /* ethernet twisted pair (TP) connector (RJ45) */
+#define PCO_ENET_AUI (1<<4)  /* ethernet attachment unit interface (AUI) header */
+#define PCO_PCMCIA   (1<<5)  /* PCMCIA socket */
+#define PCO_DIMM     (1<<6)  /* DIMM module socket */
+#define PCO_DTT      (1<<7)  /* digital thermometer and thermostat (DTT) device */
+#define PCO_LCD      (1<<8)  /* liquid crystal display (LCD) device */
+#define PCO_PCI      (1<<9)  /* PCI-Bus bridge device (QSpan) and ISA-Bus bridge device (Winbond) */
+#define PCO_PCIO     (1<<10) /* PC I/O (COM1, COM2, FDC, LPT, Keyboard/Mouse) */
+#define PCO_EIDE     (1<<11) /* enhanced IDE (EIDE) header */
+#define PCO_FDC      (1<<12) /* floppy disk controller (FDC) header */
+#define PCO_LPT_8XX  (1<<13) /* parallel port header via MPC8xx */
+#define PCO_LPT_PCIO (1<<14) /* parallel port header via PC I/O */
+
+/*
+ * FLASH memory configuration packet data
+ */
+typedef struct vpd_fmc
+{
+    ushort mid; /* manufacturer's idenitfier */
+    ushort did; /* manufacturer's device idenitfier */
+    uchar ddw;  /* device data width (e.g., 8-bits, 16-bits) */
+    uchar nod;  /* number of devices present */
+    uchar noc;  /* number of columns */
+    uchar cw;   /* column width in bits */
+    uchar wedw; /* write/erase data width */
+} vpd_fmc_t;
+
+/* function prototypes */
+extern void vpd_init(void);
+extern int  vpd_read(uint iic_device, uchar *buf, int count, int offset);
+extern      vpd_packet_t *vpd_find_packet(u_char ident);
+
+#endif /* __vpd_h */
diff --git a/board/ml2/Makefile b/board/ml2/Makefile
new file mode 100755
index 0000000..40c60b1
--- /dev/null
+++ b/board/ml2/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o serial.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/ml2/config.mk b/board/ml2/config.mk
new file mode 100755
index 0000000..41118d5
--- /dev/null
+++ b/board/ml2/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0x18000000
diff --git a/board/ml2/flash.c b/board/ml2/flash.c
new file mode 100755
index 0000000..87cb1ff
--- /dev/null
+++ b/board/ml2/flash.c
@@ -0,0 +1,300 @@
+/*
+ * flash.c: Support code for the flash chips on the Xilinx ML2 board
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire program
+ * is licensed under the GPL.
+ *
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <configs/ML2.h>
+
+#define FLASH_BANK_SIZE (64*1024*1024)
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+#define SECT_SIZE		(512*1024)
+
+#define CMD_READ_ARRAY	0x00FF00FF00FF00FULL
+#define CMD_IDENTIFY        0x0090009000900090ULL
+#define CMD_ERASE_SETUP     0x0020002000200020ULL
+#define CMD_ERASE_CONFIRM   0x00D000D000D000D0ULL
+#define CMD_PROGRAM     0x0040004000400040ULL
+#define CMD_RESUME      0x00D000D000D000D0ULL
+#define CMD_SUSPEND     0x00B000B000B000B0ULL
+#define CMD_STATUS_READ     0x0070007000700070ULL
+#define CMD_STATUS_RESET    0x0050005000500050ULL
+
+#define BIT_BUSY        0x0080008000800080ULL
+#define BIT_ERASE_SUSPEND   0x004000400400040ULL
+#define BIT_ERASE_ERROR     0x0020002000200020ULL
+#define BIT_PROGRAM_ERROR   0x0010001000100010ULL
+#define BIT_VPP_RANGE_ERROR 0x0008000800080008ULL
+#define BIT_PROGRAM_SUSPEND 0x0004000400040004ULL
+#define BIT_PROTECT_ERROR   0x0002000200020002ULL
+#define BIT_UNDEFINED       0x0001000100010001ULL
+
+#define BIT_SEQUENCE_ERROR  0x0030003000300030ULL
+
+#define BIT_TIMEOUT     0x80000000
+
+
+inline void eieio(void) {
+
+	__asm__ __volatile__ ("eieio" : : : "memory");
+
+}
+
+ulong flash_init(void) {
+
+	int i, j;
+	ulong size = 0;
+
+	for(i=0;i<CFG_MAX_FLASH_BANKS;i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) |
+								 (INTEL_ID_28F128J3A & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i==0)
+			flashbase = CFG_FLASH_BASE;
+		else
+			panic("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++)
+				flash_info[i].start[j]=flashbase + j * SECT_SIZE;
+
+		size += flash_info[i].size;
+	}
+
+	return size;
+}
+
+void flash_print_info  (flash_info_t *info) {
+
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case (INTEL_MANUFACT & FLASH_VENDMASK):
+			printf("Intel: ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F128J3A & FLASH_TYPEMASK):
+			printf("4x 28F128J3A (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf (" %08lX%s", info->start[i],
+				 info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+int flash_error (unsigned long long code) {
+
+	if (code & BIT_TIMEOUT) {
+		printf ("Timeout\n");
+		return ERR_TIMOUT;
+	}
+
+	if (~code & BIT_BUSY) {
+		printf ("Busy\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_VPP_RANGE_ERROR) {
+		printf ("Vpp range error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_PROTECT_ERROR) {
+		printf ("Device protect error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_SEQUENCE_ERROR) {
+		printf ("Command seqence error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_ERASE_ERROR) {
+		printf ("Block erase error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_PROGRAM_ERROR) {
+		printf ("Program error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_ERASE_SUSPEND) {
+		printf ("Block erase suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & BIT_PROGRAM_SUSPEND) {
+		printf ("Program suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	return ERR_OK;
+
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last) {
+
+	int rc = ERR_OK;
+	int sect;
+	unsigned long long result;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last))
+		return ERR_INVAL;
+
+	if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
+		return ERR_UNKNOWN_FLASH_VENDOR;
+
+	for (sect=s_first; sect<=s_last; ++sect)
+		if (info->protect[sect])
+			return ERR_PROTECTED;
+
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+		volatile unsigned long long *addr=
+									(unsigned long long *)(info->start[sect]);
+
+		printf("Erasing sector %2d ... ", sect);
+
+		*addr=CMD_STATUS_RESET;
+		eieio();
+		*addr=CMD_ERASE_SETUP;
+		eieio();
+		*addr=CMD_ERASE_CONFIRM;
+		eieio();
+
+		do {
+			result = *addr;
+		} while(~result & BIT_BUSY);
+
+		*addr=CMD_READ_ARRAY;
+
+		if ((rc = flash_error(result)) == ERR_OK)
+			printf("ok.\n");
+		else
+			break;
+	}
+
+	if (ctrlc())
+		printf("User Interrupt!\n");
+
+	return rc;
+}
+
+static int write_word (flash_info_t *info, ulong dest, unsigned long long data) {
+
+	volatile unsigned long long *addr=(unsigned long long *)dest;
+	unsigned long long result;
+	int rc = ERR_OK;
+
+	result=*addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	*addr=CMD_STATUS_RESET;
+	eieio();
+	*addr=CMD_PROGRAM;
+	eieio();
+	*addr=data;
+	eieio();
+
+	do {
+		result=*addr;
+	} while(~result & BIT_BUSY);
+
+	*addr=CMD_READ_ARRAY;
+
+	rc = flash_error(result);
+
+	return rc;
+
+}
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
+
+	ulong cp, wp;
+	unsigned long long data;
+	int l;
+	int i,rc;
+
+	wp=(addr & ~7);
+
+	if((l=addr-wp) != 0) {
+		data=0;
+		for(i=0,cp=wp;i<l;++i,++cp)
+			data = (data >> 8) | (*(uchar *)cp << 24);
+
+		for (; i<8 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+
+		for (; i<8; ++i, ++cp)
+			data = (data >> 8) | (*(uchar *)cp << 24);
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return rc;
+
+		wp+=8;
+	}
+
+	while(cnt>=8) {
+		data=*((unsigned long long *)src);
+		if ((rc = write_word(info, wp, data)) != 0)
+			return rc;
+		src+=8;
+		wp+=8;
+		cnt-=8;
+	}
+
+	if(cnt == 0)
+		return ERR_OK;
+
+	data = 0;
+	for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i<8; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+
+	return write_word(info, wp, data);
+
+}
diff --git a/board/ml2/init.S b/board/ml2/init.S
new file mode 100755
index 0000000..80f98c5
--- /dev/null
+++ b/board/ml2/init.S
@@ -0,0 +1,34 @@
+/*
+ * init.S: Stubs for U-Boot initialization
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+
+	.globl	ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	blr
+
+	.globl  sdram_init
+sdram_init:
+	blr
diff --git a/board/ml2/ml2.c b/board/ml2/ml2.c
new file mode 100755
index 0000000..f32e512
--- /dev/null
+++ b/board/ml2/ml2.c
@@ -0,0 +1,66 @@
+/*
+ * ml2.c: U-Boot platform support for Xilinx ML2 board
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * Derived from : Other platform support files in this tree
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+	char *e;
+
+	if (!s || strncmp (s, "ML2", 9)) {
+		printf ("### No HW ID - assuming ML2");
+	} else {
+		for (e = s; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		for (; s < e; ++s) {
+			putc (*s);
+		}
+	}
+
+
+	putc ('\n');
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	return 32 * 1024 * 1024;
+}
+
+int testdram (void)
+{
+	printf ("test: xxx MB - ok\n");
+
+	return (0);
+}
diff --git a/board/ml2/serial.c b/board/ml2/serial.c
new file mode 100755
index 0000000..92baba9
--- /dev/null
+++ b/board/ml2/serial.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+#include <common.h>
+#include <command.h>
+#include <configs/ML2.h>
+
+#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+#include <ns16550.h>
+#endif
+
+#if 0
+#include "serial.h"
+#endif
+
+#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1,
+				(NS16550_t) CFG_NS16550_COM2 };
+#endif
+
+int
+serial_init (void)
+{
+		DECLARE_GLOBAL_DATA_PTR;
+
+	    int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+	    (void)NS16550_init(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+	    (void)NS16550_init(COM_PORTS[1], clock_divisor);
+#endif
+		return 0;
+
+}
+
+void
+serial_putc(const char c)
+{
+    if (c == '\n')
+	NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r');
+
+    NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c);
+}
+
+int
+serial_getc(void)
+{
+    return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]);
+}
+
+int
+serial_tstc(void)
+{
+    return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]);
+}
+
+void
+serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+    int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+
+#ifdef CFG_INIT_CHAN1
+    NS16550_reinit(COM_PORTS[0], clock_divisor);
+#endif
+#ifdef CFG_INIT_CHAN2
+    NS16550_reinit(COM_PORTS[1], clock_divisor);
+#endif
+}
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+void
+kgdb_serial_init(void)
+{
+}
+
+void
+putDebugChar (int c)
+{
+	serial_putc (c);
+}
+
+void
+putDebugStr (const char *str)
+{
+	serial_puts (str);
+}
+
+int
+getDebugChar (void)
+{
+	return serial_getc();
+}
+
+void
+kgdb_interruptible (int yes)
+{
+	return;
+}
+#endif	/* CFG_CMD_KGDB	*/
diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds
new file mode 100755
index 0000000..f8e9e33
--- /dev/null
+++ b/board/ml2/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/ml2/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ml2/u-boot.lds.debug b/board/ml2/u-boot.lds.debug
new file mode 100755
index 0000000..1608f8c
--- /dev/null
+++ b/board/ml2/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/modnet50/Makefile b/board/modnet50/Makefile
new file mode 100755
index 0000000..ab2c376
--- /dev/null
+++ b/board/modnet50/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= modnet50.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/modnet50/config.mk b/board/modnet50/config.mk
new file mode 100755
index 0000000..49d4836
--- /dev/null
+++ b/board/modnet50/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x00f00000
+#CROSS_COMPILE = arm-elf-
diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c
new file mode 100755
index 0000000..a50639e
--- /dev/null
+++ b/board/modnet50/flash.c
@@ -0,0 +1,536 @@
+/*
+ * (C) Copyright 2002
+ * MAZeT GmbH <www.mazet.de>
+ * Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
+ *
+ * The most stuff comes from PPCBoot and Linux.
+ *
+ * IMMS gGmbH <www.imms.de>
+ * Thomas Elste <info@elste.org>
+ *
+ * Modifications for ModNET50 Board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/netarm_registers.h>
+
+#define SCR   (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_SYSTEM_CONTROL))
+
+#define ALIGN_ABORT_OFF		SCR = SCR & ~NETARM_GEN_SYS_CFG_ALIGN_ABORT
+#define ALIGN_ABORT_ON		SCR = SCR |  NETARM_GEN_SYS_CFG_ALIGN_ABORT
+
+#define PROG_ADDR		(0x555*2)
+#define SETUP_ADDR		(0x555*2)
+#define ID_ADDR			(0x555*2)
+#define UNLOCK_ADDR1		(0x555*2)
+#define UNLOCK_ADDR2		(0x2AA*2)
+
+#define UNLOCK_CMD1		(0xAA)
+#define UNLOCK_CMD2		(0x55)
+#define ERASE_SUSPEND_CMD	(0xB0)
+#define ERASE_RESUME_CMD	(0x30)
+#define RESET_CMD		(0xF0)
+#define ID_CMD			(0x90)
+#define SECERASE_CMD		(0x30)
+#define CHIPERASE_CMD		(0x10)
+#define PROG_CMD		(0xa0)
+#define SETUP_CMD		(0x80)
+
+#define DQ2			(0x04)
+#define DQ3			(DQ2*2)
+#define DQ5			(DQ3*4)
+#define DQ6			(DQ5*2)
+
+#define WRITE_UNLOCK(addr) { \
+  *(volatile __u16*)(addr + UNLOCK_ADDR1) = (__u16)UNLOCK_CMD1; \
+  *(volatile __u16*)(addr + UNLOCK_ADDR2) = (__u16)UNLOCK_CMD2; \
+}
+
+#define CONFIG_AM29_RESERVED	(0)
+#define K			(1024)
+#define MB			(4)
+
+#define CELL_SIZE		(64*K)
+#define DEVICE_SIZE		(MB*K*K)
+#define CELLS_PER_DEVICE	(DEVICE_SIZE/CELL_SIZE)
+#define RESERVED_CELLS		(CONFIG_AM29_RESERVED*K)/CELL_SIZE
+#define MAX_FLASH_DEVICES	(1)
+#define AVAIL_SIZE		(DEVICE_SIZE*MAX_FLASH_DEVICES - RESERVED_CELLS*CELL_SIZE)
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+static __u16 toggling_bits;
+
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+	short i;
+	__u16 flashtest;
+
+	/* Write auto select command sequence and test FLASH answer */
+	WRITE_UNLOCK (baseaddr);
+	*(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD;
+	flashtest /* manufacturer ID */  = *(volatile __u16 *) (baseaddr);
+	*(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD;
+
+	switch ((__u32) ((flashtest << 16) + flashtest)) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD & FLASH_VENDMASK;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ & FLASH_VENDMASK;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash */
+	}
+
+	/* Write auto select command sequence and test FLASH answer */
+	WRITE_UNLOCK (baseaddr);
+	*(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) ID_CMD;
+	flashtest /* device ID */  = *(volatile __u16 *) (baseaddr + 2);
+	*(volatile __u16 *) (baseaddr + ID_ADDR) = (__u16) RESET_CMD;
+
+	/* toggling_bits = (flashtest == TOSHIBA)?(DQ6):(DQ2|DQ6); */
+	toggling_bits = (DQ2 | DQ6);
+
+	switch ((__u32) ((flashtest << 16) + flashtest)) {
+	case AMD_ID_LV160B:
+		info->flash_id +=
+			(FLASH_AM160LV | FLASH_AM160B) & FLASH_TYPEMASK;
+		info->sector_count = CFG_MAX_FLASH_SECT;
+		info->size = CFG_FLASH_SIZE;
+		/* 1*16K Boot Block
+		   2*8K Parameter Block
+		   1*32K Small Main Block */
+		info->start[0] = baseaddr;
+		info->start[1] = baseaddr + 0x4000;
+		info->start[2] = baseaddr + 0x6000;
+		info->start[3] = baseaddr + 0x8000;
+		for (i = 1; i < info->sector_count; i++)
+			info->start[3 + i] = baseaddr + i * CFG_MAIN_SECT_SIZE;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* no or unknown flash */
+	}
+
+	for (i = 0; i < info->sector_count; i++) {
+		/* Write auto select command sequence and test FLASH answer */
+		WRITE_UNLOCK (info->start[i]);
+		*(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) ID_CMD;
+		flashtest /* protected verify */  = *(volatile __u16 *) (info->start[i] + 4);
+		*(volatile __u16 *) (info->start[i] + ID_ADDR) = (__u16) RESET_CMD;
+		if (flashtest & 0x0001) {
+			info->protect[i] = 1;	/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_init (void)
+{
+	ulong size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+	size = flash_get_size (CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size >> 20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("Fujitsu ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDL323B:
+		printf ("29DL323B (32 M, bottom sector)\n");
+		break;
+	case (FLASH_AM160LV | FLASH_AM160B):
+		printf ("29LV160BE (1M x 16, bottom sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf (" S%02d @ 0x%08lX%s", i,
+			info->start[i], info->protect[i] ? " !" : "  ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_check_protection (flash_info_t * info, int s_first, int s_last)
+{
+	int sect, prot = 0;
+
+	for (sect = s_first; sect <= s_last; sect++)
+		if (info->protect[sect])
+			prot++;
+	if (prot)
+		printf ("- can't erase %d protected sectors\n", prot);
+	return prot;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_check_erase_amd (ulong start)
+{
+	__u16 v1, v2;
+
+	v1 = *(volatile __u16 *) (start);
+	v2 = *(volatile __u16 *) (start);
+
+	if (((v1 ^ v2) & toggling_bits) == toggling_bits) {
+		if (((v1 | v2) & DQ5) == DQ5) {
+			printf ("[DQ5] ");
+			/* OOPS: exceeded timing limits */
+
+			v1 = *(volatile __u16 *) (start);
+			v2 = *(volatile __u16 *) (start);
+
+			if (((v1 ^ v2) & toggling_bits) == toggling_bits) {
+
+				printf ("[%s] ",
+					((toggling_bits & (DQ2 | DQ6)) ==
+					 (DQ2 | DQ6)) ? "DQ2,DQ6" : "DQ6");
+
+				/* OOPS: there is an erasure in progress,
+				 *       try to reset chip */
+				*(volatile __u16 *) (start) =
+					(__u16) RESET_CMD;
+
+				return 1;	/* still busy */
+			}
+		}
+		return 1;	/* still busy */
+	}
+	return 0;		/* be free */
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, sect, setup_offset = 0;
+	int rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("- missing\n");
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return ERR_INVAL;
+	}
+
+	if (flash_check_protection (info, s_first, s_last))
+		return ERR_PROTECTED;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_FUJ:
+	case FLASH_MAN_AMD:
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (FLASH_AM160LV | FLASH_AM160B):
+			setup_offset = UNLOCK_ADDR1;	/* just the adress for setup_cmd differs */
+		case FLASH_AMDL323B:
+			/*
+			 * Disable interrupts which might cause a timeout
+			 * here. Remember that our exception vectors are
+			 * at address 0 in the flash, and we don't want a
+			 * (ticker) exception to happen while the flash
+			 * chip is in programming mode.
+			 */
+			flag = disable_interrupts ();
+			/* Start erase on unprotected sectors */
+			for (sect = s_first; sect <= s_last && !ctrlc ();
+			     sect++) {
+				printf ("Erasing sector %2d ... ", sect);
+
+				if (info->protect[sect] == 0) {
+					/* not protected */
+					/* Write sector erase command sequence */
+					WRITE_UNLOCK (info->start[0]);
+					*(volatile __u16 *) (info->start[0] +
+							     setup_offset) =
+						(__u16) SETUP_CMD;
+					WRITE_UNLOCK (info->start[0]);
+					*(volatile __u16 *) (info->
+							     start[sect]) =
+						(__u16) SECERASE_CMD;
+
+					/* wait some time */
+					reset_timer_masked ();
+					while (get_timer_masked () < 1000) {
+					}
+
+					/* arm simple, non interrupt dependent timer */
+					reset_timer_masked ();
+					while (flash_check_erase_amd (info->start[sect])) {
+						if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+							printf ("timeout!\n");
+							/* OOPS: reach timeout,
+							 * try to reset chip
+							 */
+							*(volatile __u16 *) (info-> start[sect]) = (__u16) RESET_CMD;
+							rc = ERR_TIMOUT;
+							goto outahere_323B;
+						}
+					}
+					printf ("ok.\n");
+				} else {
+					printf ("protected!\n");
+				}
+			}
+			if (ctrlc ())
+				printf ("User Interrupt!\n");
+outahere_323B:
+			/* allow flash to settle - wait 10 ms */
+			udelay_masked (10000);
+			if (flag)
+				enable_interrupts ();
+			return rc;
+		default:
+			printf ("- unknown chip type\n");
+			return ERR_UNKNOWN_FLASH_TYPE;
+		}
+		break;
+	default:
+		printf ("- unknown vendor ");
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_check_write_amd (ulong dest)
+{
+	__u16 v1, v2;
+
+	v1 = *(volatile __u16 *) (dest);
+	v2 = *(volatile __u16 *) (dest);
+
+	/* DQ6 toggles during write */
+	if (((v1 ^ v2) & DQ6) == DQ6) {
+		if (((v1 | v2) & DQ5) == DQ5) {
+			printf ("[DQ5] @ %08lX\n", dest);
+
+			/* OOPS: exceeded timing limits,
+			 *       try to reset chip */
+			*(volatile __u16 *) (dest) = (__u16) RESET_CMD;
+			return 0;	/* be free */
+		}
+		return 1;	/* still busy */
+	}
+
+	return 0;		/* be free */
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+static int write_word (flash_info_t * info, ulong dest, ushort data)
+{
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*(__u16 *) (dest) & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+	/* Write program command sequence */
+	WRITE_UNLOCK (info->start[0]);
+
+	/* Flash dependend program seqence */
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_FUJ:
+	case FLASH_MAN_AMD:
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (FLASH_AM160LV | FLASH_AM160B):
+			*(volatile __u16 *) (info->start[0] + UNLOCK_ADDR1) =
+				(__u16) PROG_CMD;
+			*(volatile __u16 *) (dest) = (__u16) data;
+			break;
+		case FLASH_AMDL323B:
+			*(volatile __u16 *) (dest) = (__u16) PROG_CMD;
+			*(volatile __u16 *) (dest) = (__u16) data;
+			break;
+		}
+	}
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	while (flash_check_write_amd (dest)) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			printf ("timeout! @ %08lX\n", dest);
+			/* OOPS: reach timeout,
+			 *       try to reset chip */
+			*(volatile __u16 *) (dest) = (__u16) RESET_CMD;
+
+			rc = ERR_TIMOUT;
+			goto outahere_323B;
+		}
+	}
+
+	/* Check if Flash was (accurately) written */
+	if (*(__u16 *) (dest) != data)
+		rc = ERR_PROG_ERROR;
+
+outahere_323B:
+	if (flag)
+		enable_interrupts ();
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	ushort data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((ushort *) src);
+		if ((rc = write_word (info, wp, data)) != 0)
+			return (rc);
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0)
+		return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/board/modnet50/lowlevel_init.S b/board/modnet50/lowlevel_init.S
new file mode 100755
index 0000000..c98c155
--- /dev/null
+++ b/board/modnet50/lowlevel_init.S
@@ -0,0 +1,204 @@
+/*
+ * Memory Setup stuff - taken from Linux
+ *
+ * Copyright (c) 2002	Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
+ * (c) 2004 IMMS gGmbH <www.imms.de>, Thomas Elste <info@elste.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/netarm_registers.h>
+
+
+/* some parameters for the board */
+#define FLASH_90ns_WAIT_STATES	((NETARM_PLL_COUNT_VAL + 2) / 3)
+#define FLASH_70ns_WAIT_STATES	4
+
+#define NETARM_MMAP_CS0_BASE	(PHYS_FLASH_1)
+#if 1
+#define NETARM_MMAP_CS0_MASK	(~(PHYS_FLASH_1_SIZE - 1))
+#else
+#define NETARM_MMAP_CS0_MASK	(~(1000000 - 1))
+#endif
+#define NETARM_MMAP_CS1_BASE	(PHYS_SDRAM_1)
+#define NETARM_MMAP_CS1_MASK	(~(PHYS_SDRAM_1_SIZE - 1))
+#define NETARM_MMAP_CS2_BASE	(PHYS_SDRAM_2)
+#define NETARM_MMAP_CS2_MASK	(~(PHYS_SDRAM_2_SIZE - 1))
+#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
+#define NETARM_MMAP_CS3_BASE	(PHYS_NVRAM_1)
+#define NETARM_MMAP_CS3_MASK	(~(PHYS_NVRAM_SIZE - 1))
+#endif
+#define NETARM_MMAP_CS4_BASE	(PHYS_EXT_1)
+#define NETARM_MMAP_CS4_MASK	(~(PHYS_EXT_SIZE - 1))
+
+/* setting up the memory */
+.globl lowlevel_init
+lowlevel_init:
+
+#if defined(CONFIG_MODNET50)
+	ldr	pc, =(_jump_to_high + NETARM_MMAP_CS0_BASE - TEXT_BASE)
+
+_jump_to_high:
+	/*
+	 * MEM Config Reg
+	 * ---------------------------------------------------
+	 */
+	ldr	r0, =NETARM_MEM_MODULE_BASE
+	ldr	r1, =(	NETARM_MEM_REFR_PERIOD_USEC(16) | \
+			NETARM_MEM_CFG_REFRESH_EN | \
+			NETARM_MEM_CFG_REFR_CYCLE_5CLKS )
+	str	r1, [r0, #+NETARM_MEM_MODULE_CONFIG]
+
+
+memsetup_cs0:
+	/*
+	 * Base Addr / Option Reg 0 (Flash)
+	 * ---------------------------------------------------
+	 */
+	ldr	r1, =(	NETARM_MEM_BAR_BASE(NETARM_MMAP_CS0_BASE) | \
+			NETARM_MEM_BAR_DRAM_FP | \
+			NETARM_MEM_BAR_DRAM_MUX_INT | \
+			NETARM_MEM_BAR_DRAM_MUX_BAL | \
+			NETARM_MEM_BAR_VALID )
+	str	r1, [r0, #+NETARM_MEM_CS0_BASE_ADDR]
+
+	/* trust that the bus size for flash was strapped correctly */
+	/* this saves the bus width in r2 and then ORs it back in */
+	/* it's pretty safe assumption, otherwise it wouldn't boot */
+	ldr	r2, [r0, #+NETARM_MEM_CS0_OPTIONS]
+	and	r2, r2, #NETARM_MEM_OPT_BUS_SIZE_MASK
+
+/*	just a test: assume 32 bit flash mem */
+/*	mov	r2, #NETARM_MEM_OPT_32BIT */
+
+	ldr	r1, =(	NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS0_MASK) | \
+			NETARM_MEM_OPT_WAIT_STATES(FLASH_70ns_WAIT_STATES) | \
+			NETARM_MEM_OPT_BCYC_4 | \
+			NETARM_MEM_OPT_BSIZE_16 | \
+			NETARM_MEM_OPT_16BIT | \
+			NETARM_MEM_OPT_READ_ASYNC | \
+			NETARM_MEM_OPT_WRITE_ASYNC )
+
+	orr	r1, r1, r2
+	str	r1, [r0, #+NETARM_MEM_CS0_OPTIONS]
+
+
+memsetup_cs1:
+	/*
+	 * Base Addr / Option Reg 1 (DRAM #1)
+	 * ---------------------------------------------------
+	 */
+#ifdef CONFIG_NETARM_NET40_REV2
+	/* we have to config SDRAM in burst mode */
+	ldr	r1, =(	NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
+			NETARM_MEM_OPT_BCYC_2 | \
+			NETARM_MEM_OPT_BSIZE_16 | \
+			NETARM_MEM_OPT_WAIT_STATES(0) | \
+			NETARM_MEM_OPT_32BIT | \
+			NETARM_MEM_OPT_READ_ASYNC | \
+			NETARM_MEM_OPT_WRITE_ASYNC )
+	str	r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
+
+	ldr	r1, =(	NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
+			NETARM_MEM_BAR_DRAM_SYNC | \
+			NETARM_MEM_BAR_DRAM_MUX_INT | \
+			NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
+			NETARM_MEM_BAR_DRAM_SEL | \
+			NETARM_MEM_BAR_BURST_EN | \
+			NETARM_MEM_BAR_VALID )
+	str	r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
+#else
+	/* we have to config FPDRAM in burst mode with smaller burst access size */
+	ldr	r1, =(	NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS1_MASK) | \
+			NETARM_MEM_OPT_BCYC_2 | \
+			NETARM_MEM_OPT_BSIZE_16 | \
+			NETARM_MEM_OPT_WAIT_STATES(0) | \
+			NETARM_MEM_OPT_32BIT | \
+			NETARM_MEM_OPT_READ_ASYNC | \
+			NETARM_MEM_OPT_WRITE_ASYNC )
+	str	r1, [r0, #+NETARM_MEM_CS1_OPTIONS]
+
+	ldr	r1, =(	NETARM_MEM_BAR_BASE(NETARM_MMAP_CS1_BASE) | \
+			NETARM_MEM_BAR_DRAM_SYNC | \
+			NETARM_MEM_BAR_DRAM_MUX_INT | \
+			NETARM_MEM_BAR_DRAM_MUX_UNBAL | \
+			NETARM_MEM_BAR_DRAM_SEL | \
+			NETARM_MEM_BAR_BURST_EN | \
+			NETARM_MEM_BAR_VALID )
+	str	r1, [r0, #+NETARM_MEM_CS1_BASE_ADDR]
+
+#endif /* CONFIG_NETARM_NET40_REV2 */
+
+
+memsetup_cs3:
+	/*
+	 * Base Addr / Option Reg 3 (EEPROM, NVRAM)
+	 * ---------------------------------------------------
+	 */
+#if defined(CONFIG_NETARM_EEPROM) && defined(PHYS_NVRAM_1) && defined(PHYS_NVRAM_SIZE)
+	ldr	r1, =(	NETARM_MEM_OPT_BASE_USE(NETARM_MMAP_CS3_MASK) | \
+			NETARM_MEM_OPT_BCYC_3 | \
+			NETARM_MEM_OPT_BSIZE_2 | \
+			NETARM_MEM_OPT_WAIT_STATES(10) | \
+			NETARM_MEM_OPT_8BIT | \
+			NETARM_MEM_OPT_READ_ASYNC | \
+			NETARM_MEM_OPT_WRITE_ASYNC )
+	str	r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
+
+	ldr	r1, =(	NETARM_MEM_BAR_BASE(NETARM_MMAP_CS3_BASE) | \
+			NETARM_MEM_BAR_DRAM_FP | \
+			NETARM_MEM_BAR_DRAM_MUX_INT | \
+			NETARM_MEM_BAR_DRAM_MUX_BAL | \
+			NETARM_MEM_BAR_VALID )
+	str	r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
+#else
+	/* we don't need EEPROM --> no config */
+	ldr	r1, =( 0 )
+	str	r1, [r0, #+NETARM_MEM_CS3_OPTIONS]
+
+	ldr	r1, =( 0 )
+	str	r1, [r0, #+NETARM_MEM_CS3_BASE_ADDR]
+#endif
+
+
+#else
+/*
+#error "missing CONFIG_MODNET50 (see your config.h)"
+*/
+#endif /* CONFIG_MODNET50 */
+
+
+lowlevel_init_end:
+	/*
+	 * manipulate address in lr and ip to match new
+	 * address space
+	 */
+	ldr	r3, =(NETARM_MMAP_CS0_BASE)
+	mov	r0, lr
+	add	r0, r3, r0
+	mov	lr, r0
+	mov	r0, ip
+	add	r0, r3, r0
+	mov	ip, r0
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/board/modnet50/modnet50.c b/board/modnet50/modnet50.c
new file mode 100755
index 0000000..448c623
--- /dev/null
+++ b/board/modnet50/modnet50.c
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	/* address for the kernel command line */
+	gd->bd->bi_boot_params = 0x800;
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	if (CONFIG_NR_DRAM_BANKS == 2) {
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+		gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	}
+	return (0);
+}
diff --git a/board/modnet50/u-boot.lds b/board/modnet50/u-boot.lds
new file mode 100755
index 0000000..5b70a40
--- /dev/null
+++ b/board/modnet50/u-boot.lds
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  cpu/arm720t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+				  /* Stabs debugging sections.	  */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/board/mousse/Makefile b/board/mousse/Makefile
new file mode 100755
index 0000000..ddc5546
--- /dev/null
+++ b/board/mousse/Makefile
@@ -0,0 +1,41 @@
+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o m48t59y.o pci.o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mousse/README b/board/mousse/README
new file mode 100755
index 0000000..d5dda7a
--- /dev/null
+++ b/board/mousse/README
@@ -0,0 +1,346 @@
+
+U-Boot for MOUSSE/MPC8240 (KAHLUA)
+----------------------------------
+James Dougherty (jfd@broadcom.com), 09/10/01
+
+The Broadcom/Vooha Mousse board is a 3U Compact PCI system board
+which uses the MPC8240, a 64MB SDRAM SIMM, and has onboard
+DEC 21143, NS16550 UART, an SGS M48T59Y TOD, and 4MB FLASH.
+See also: http://www.vooha.com/
+
+* NVRAM setenv/printenv/savenv supported.
+* Date Command
+* Serial Console support
+* Network support
+* FLASH of kernel images is supported.
+* FLASH of U-Boot to onboard and PLCC boot region.
+* Kernel command line options from NVRAM is supported.
+* IP PNP options supported.
+
+U-Boot Loading...
+
+
+U-Boot 1.0.5 (Sep 10 2001 - 00:22:25)
+
+CPU:   MPC8240 Revision 1.1 at 198 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)
+Built: Sep 10 2001 at 01:01:50
+MPLD:  Revision 127
+Local Bus:  33 MHz
+RTC:   M48T589 TOD/NVRAM (8176) bytes
+  Current date/time: 9/10/2001 0:18:52
+DRAM:  64 MB
+FLASH:  1.960 MB
+PCI:    scanning bus0 ...
+  bus dev fn venID devID class  rev MBAR0    MBAR1    IPIN ILINE
+  00  00  00 1057  0003  060000 11  00000008 00000000 01   00
+  00  0d  00 1011  0019  020000 41  80000001 80000000 01   01
+  00  0e  00 105a  4d38  018000 01  a0000001 a0001001 01   03
+In:    serial
+Out:   serial
+Err:   serial
+
+Hit any key to stop autoboot:  0
+=>
+
+I. Root FileSystem/IP Configuration
+
+bootcmd=tftp 100000 vmlinux.img;bootm
+bootdelay=3
+baudrate=9600
+ipaddr=<IP ADDRESS>
+netmask=<NETMASK>
+hostname=<NAME>
+serverip=<NFS SERVER IP ADDRESS>
+ethaddr=00:00:10:20:30:44
+nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs
+gateway=<IP ADDRESS>
+root=/dev/nfs
+stdin=serial
+stdout=serial
+stderr=serial
+
+NVRAM environment variables.
+
+use the command:
+
+setenv <attribute> <value>
+
+type "saveenv" to write to NVRAM.
+
+
+II. To boot from a hard drive:
+
+setenv root /dev/hda1
+
+
+III. IP options which configure the network:
+
+ipaddr=<IP ADDRESS OF MACHINE>
+netmask=<NETMASK>
+hostname=mousse
+ethaddr=00:00:10:20:30:44
+gateway=<IP ADDRESS OF GATEWAY/ROUTER>
+
+
+IV. IP Options which configure NFS Root/Boot Support
+
+root=/dev/nfs
+serverip=<NFS SERVER IP ADDRESS>
+nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs
+
+V. U-Boot Image Support
+
+The U-Boot boot loader assumes that after you build
+your kernel (vmlinux), you will create a U-Boot image
+using the following commands or script:
+
+#!/bin/csh
+/bin/touch vmlinux.img
+/bin/rm vmlinux.img
+set path=($TOOLBASE/bin $path)
+set path=($U_BOOT/tools $path)
+powerpc-linux-objcopy -S -O binary vmlinux vmlinux.bin
+gzip -vf vmlinux.bin
+mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 -n vmlinux.bin.gz -d vmlinux.bin.gz vmlinux.img
+ls -l vmlinux.img
+
+
+VI. ONBOARD FLASH Support
+
+FLASH support is provided for the onboard FLASH chip Bootrom area.
+U-Boot is loaded into either the ROM boot region of the FLASH chip,
+after first being boot-strapped from a pre-progammed AMD29F040 PLCC
+bootrom. The PLCC needs to be programmed with a ROM burner using
+AMD 29F040 ROM parts and the u-boot.bin or u-boot.hex (S-Record)
+images.
+
+The PLCC overlays this same region of flash as the onboard FLASH,
+the jumper J100 is a chip-select for which flash chip you want to
+progam. When jumper J100 is connected to pins 2-3, you boot from
+PLCC FLASH.
+
+To bringup a system, simply flash a flash an AMD29F040 PLCC
+bootrom, and put this in the PLCC socket. Move jumper J100 to
+pins 2-3 and boot from the PLCC.
+
+
+Now, while the system is running, move Jumper J100 to
+pins 1-2 and follow the procedure below to FLASH a bootrom
+(u-boot.bin) image into the onboard bootrom region (AMD29LV160DB):
+
+tftp 100000 u-boot.bin
+protect off FFF00000 FFF7FFFF
+erase FFF00000 FFF7FFFF
+cp.b 100000 FFF00000 \${filesize}\
+
+
+Here is an example:
+
+=>tftp 100000 u-boot.bin
+eth_halt
+eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0)
+DEC Ethernet iobase=0x80000000
+ARP broadcast 1
+Filename 'u-boot.bin'.
+Load address: 0x100000
+Loading: #########################
+done
+Bytes transferred = 123220 (1e154 hex)
+eth_halt
+=>protect off FFF00000 FFF7FFFF
+Un-Protected 8 sectors
+=>erase FFF00000 FFF7FFFF
+Erase Flash from 0xfff00000 to 0xfff7ffff
+Erase FLASH[PLCC_BOOT] -8 sectors:........ done
+Erased 8 sectors
+=>cp.b 100000 FFF00000 1e154
+Copy to Flash... FLASH[PLCC_BOOT]:..done
+=>
+
+
+B. FLASH RAMDISK REGION
+
+FLASH support is provided for an Onboard 512K RAMDISK region.
+
+TThe following commands will FLASH a bootrom (u-boot.bin) image
+into the onboard FLASH region (AMD29LV160DB 2MB FLASH):
+
+tftp 100000 u-boot.bin
+protect off FFF80000 FFFFFFFF
+erase FFF80000 FFFFFFFF
+cp.b 100000 FFF80000 \${filesize}\
+
+
+C. FLASH KERNEL REGION (960KB)
+
+FLASH support is provided for the 960KB onboard FLASH1 segment.
+This allows flashing of kernel images which U-Boot can load
+and run (standalone) from the onboard FLASH chip. It also assumes
+
+The following commands will FLASH a kernel image to 0xffe10000
+
+tftp 100000 vmlinux.img
+protect off FFE10000 FFEFFFFF
+erase FFE10000 FFEFFFFF
+cp.b 100000 FFE10000 \${filesize}\
+reset
+
+Here is an example:
+
+
+=>tftp 100000 vmlinux.img
+eth_halt
+eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0)
+DEC Ethernet iobase=0x80000000
+ARP broadcast 1
+TFTP from server 209.128.93.133; our IP address is 209.128.93.138
+Filename 'vmlinux.img'.
+Load address: 0x100000
+Loading: #####################################################################################################################################################
+done
+Bytes transferred = 760231 (b99a7 hex)
+eth_halt
+=>protect off FFE10000 FFEFFFFF
+Un-Protected 15 sectors
+=>erase FFE10000 FFEFFFFF
+Erase Flash from 0xffe10000 to 0xffefffff
+Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done
+Erased 15 sectors
+=>cp.b 100000 FFE10000 b99a7
+Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done
+=>
+
+
+When finished, use the command:
+
+bootm ffe10000
+
+to start the kernel.
+
+Finally, to make this the default boot command, use
+the following commands:
+
+setenv bootcmd bootm ffe10000
+savenv
+
+to make it automatically boot the kernel from FLASH.
+
+
+To go back to development mode (NFS boot)
+
+setenv bootcmd tftp 100000 vmlinux.img\;bootm
+savenv
+
+
+=>tftp 100000 vmlinux.img
+eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0)
+DEC Ethernet iobase=0x80000000
+ARP broadcast 1
+Filename 'vmlinux.img'.
+Load address: 0x100000
+Loading: ####################################################################################################################################################
+done
+Bytes transferred = 752717 (b7c4d hex)
+eth_halt
+=>protect off FFE10000 FFEFFFFF
+Un-Protected 15 sectors
+=>erase FFE10000 FFEFFFFF
+Erase Flash from 0xffe10000 to 0xffefffff
+Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done
+Erased 15 sectors
+=>cp.b 100000 FFE10000 b7c4d
+Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done
+=>bootm ffe10000
+## Booting image at ffe10000 ...
+   Image Name:   vmlinux.bin.gz
+   Image Type:   PowerPC Linux Kernel Image (gzip compressed)
+   Data Size:    752653 Bytes = 735 kB = 0 MB
+   Load Address: 00000000
+   Entry Point:  00000000
+   Verifying Checksum ... OK
+   Uncompressing Kernel Image ... OK
+Total memory = 64MB; using 0kB for hash table (at 00000000)
+Linux version 2.4.2_hhl20 (jfd@atlantis) (gcc version 2.95.2 19991024 (release)) #597 Wed Sep 5 23:23:23 PDT 2001
+cpu0: MPC8240/KAHLUA : MOUSSE Platform : 64MB RAM: MPLD Rev. 7f
+Sandpoint port (C) 2000, 2001 MontaVista Software, Inc. (source@mvista.com)
+IP PNP: 802.3 Ethernet Address=<0:0:10:20:30:44>
+NOTICE: mounting root file system via NFS
+On node 0 totalpages: 16384
+zone(0): 16384 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+time_init: decrementer frequency = 16.665914 MHz
+time_init: MPC8240 PCI Bus frequency = 33.331828 MHz
+Calibrating delay loop... 133.12 BogoMIPS
+Memory: 62436k available (1336k kernel code, 500k data, 88k init, 0k highmem)
+Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes)
+Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
+Inode-cache hash table entries: 4096 (order: 3, 32768 bytes)
+POSIX conformance testing by UNIFIX
+PCI: Probing PCI hardware
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Initializing RT netlink socket
+Starting kswapd v1.8
+pty: 256 Unix98 ptys configured
+block: queued sectors max/low 41394kB/13798kB, 128 slots per queue
+Uniform Multi-Platform E-IDE driver Revision: 6.31
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+PDC20262: IDE controller on PCI bus 00 dev 70
+PDC20262: chipset revision 1
+PDC20262: not 100% native mode: will probe irqs later
+PDC20262: ROM enabled at 0x000d0000
+PDC20262: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.
+PDC20262: FORCING BURST BIT 0x00 -> 0x01 ACTIVE
+PDC20262: irq=3 dev->irq=3
+    ide0: BM-DMA at 0xbfff00-0xbfff07, BIOS settings: hda:DMA, hdb:DMA
+    ide1: BM-DMA at 0xbfff08-0xbfff0f, BIOS settings: hdc:pio, hdd:pio
+hda: WDC WD300AB-00BVA0, ATA DISK drive
+hdc: SONY CD-RW CRX160E, ATAPI CD/DVD-ROM drive
+ide0 at 0xbfff78-0xbfff7f,0xbfff76 on irq 3
+ide1 at 0xbfff68-0xbfff6f,0xbfff66 on irq 3
+hda: 58633344 sectors (30020 MB) w/2048KiB Cache, CHS=58168/16/63, UDMA(66)
+hdc: ATAPI 32X CD-ROM CD-R/RW drive, 4096kB Cache
+Uniform CD-ROM driver Revision: 3.12
+Partition check:
+ /dev/ide/host0/bus0/target0/lun0: p1 p2
+hd: unable to get major 3 for hard disk
+udf: registering filesystem
+loop: loaded (max 8 devices)
+Serial driver version 5.02 (2000-08-09) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
+ttyS00 at 0xffe08080 (irq = 4) is a ST16650
+Linux Tulip driver version 0.9.13a (January 20, 2001)
+eth0: Digital DS21143 Tulip rev 65 at 0xbfff80, EEPROM not present, 00:00:10:20:30:44, IRQ 1.
+eth0:  MII transceiver #0 config 3000 status 7829 advertising 01e1.
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 4096 bind 4096)
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+devfs: v0.102 (20000622) Richard Gooch (rgooch@atnf.csiro.au)
+devfs: boot_options: 0x0
+VFS: Mounted root (nfs filesystem).
+Mounted devfs on /dev
+Freeing unused kernel memory: 88k init 4k openfirmware
+eth0: Setting full-duplex based on MII#0 link partner capability of 45e1.
+INIT: version 2.78 booting
+INIT: Entering runlevel: 2
+
+
+Welcome to Linux/PPC
+MPC8240/MOUSSE
+
+
+mousse login: root
+Password:
+PAM_unix[13]: (login) session opened for user root by LOGIN(uid=0)
+Last login: Thu Sep  6 00:16:51 2001 on console
+
+
+Welcome to Linux/PPC
+MPC8240/MOUSSE
+
+
+mousse#
diff --git a/board/mousse/config.mk b/board/mousse/config.mk
new file mode 100755
index 0000000..64cffa4
--- /dev/null
+++ b/board/mousse/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MOUSSE boards
+#
+TEXT_BASE = 0xFFF00000
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/mousse/flash.c b/board/mousse/flash.c
new file mode 100755
index 0000000..2c32b8f
--- /dev/null
+++ b/board/mousse/flash.c
@@ -0,0 +1,939 @@
+/*
+ * MOUSSE/MPC8240 Board definitions.
+ * Flash Routines for MOUSSE onboard AMD29LV106DB devices
+ *
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <malloc.h>
+#include "mousse.h"
+#include "flash.h"
+
+int flashLibDebug = 0;
+int flashLibInited = 0;
+
+#define OK  0
+#define ERROR -1
+#define STATUS int
+#define PRINTF			if (flashLibDebug) printf
+#if 0
+#define PRIVATE			static
+#else
+#define PRIVATE
+#endif
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#define SLEEP_DELAY    166
+#define FLASH_SECTOR_SIZE   (64*1024)
+/***********************************************************************
+ *
+ * Virtual Flash Devices on Mousse board
+ *
+ * These must be kept in sync with the definitions in flashLib.h.
+ *
+ ***********************************************************************/
+
+PRIVATE flash_dev_t flashDev[] = {
+    /* Bank 0 sector SA0 (16 kB) */
+    {	"SA0",FLASH0_BANK, FLASH0_SEG0_START, 1, 14,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sector SA1 (8 kB) */
+    {	"SA1", FLASH0_BANK, FLASH0_SEG0_START + 0x4000, 1, 13,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sector SA2 (8 kB) */
+    {	"SA2", FLASH0_BANK, FLASH0_SEG0_START + 0x6000, 1, 13,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sector SA3 is occluded by Mousse I/O devices */
+    /* Bank 0 sectors SA4-SA18, after Mousse devices up to PLCC (960 kB)  */
+    {	"KERNEL", FLASH0_BANK, FLASH0_SEG1_START, 15, 16,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sectors SA19-SA26, jumper can occlude this by PLCC (512 kB) */
+    /* This is where the Kahlua boot vector and boot ROM code resides. */
+    {	"BOOT",FLASH0_BANK, FLASH0_SEG2_START, 8, 16,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+    /* Bank 0 sectors SA27-SA34 (512 kB) */
+    {	"RAMDISK",FLASH0_BANK, FLASH0_SEG3_START, 8, 16,
+	FLASH0_VENDOR_ID, FLASH0_DEVICE_ID
+    },
+};
+
+int flashDevCount = (sizeof (flashDev) / sizeof (flashDev[0]));
+
+#define DEV(no)			(&flashDev[no])
+#define DEV_NO(dev)		((dev) - flashDev)
+
+/***********************************************************************
+ *
+ * Private Flash Routines
+ *
+ ***********************************************************************/
+
+/*
+ * The convention is:
+ *
+ * "addr" is always the PROM raw address, which is the address of an
+ * 8-bit quantity for flash 0 and 16-bit quantity for flash 1.
+ *
+ * "pos" is always a logical byte position from the PROM beginning.
+ */
+
+#define FLASH0_ADDR(dev, addr) \
+	((unsigned char *) ((dev)->base + (addr)))
+
+#define FLASH0_WRITE(dev, addr, value) \
+	(*FLASH0_ADDR(dev, addr) = (value))
+
+#define FLASH0_READ(dev, addr) \
+	(*FLASH0_ADDR(dev, addr))
+
+PRIVATE int flashCheck (flash_dev_t * dev)
+{
+	if (!flashLibInited) {
+		printf ("flashCheck: flashLib not initialized\n");
+		return ERROR;
+	}
+
+	if (dev < &flashDev[0] || dev >= &flashDev[flashDevCount]) {
+		printf ("flashCheck: Bad dev parameter\n");
+		return ERROR;
+	}
+
+	if (!dev->found) {
+		printf ("flashCheck: Device %d not available\n", DEV_NO (dev));
+		return ERROR;
+	}
+
+	return OK;
+}
+
+PRIVATE void flashReset (flash_dev_t * dev)
+{
+	PRINTF ("flashReset: dev=%d\n", DEV_NO (dev));
+
+	if (dev->bank == FLASH0_BANK) {
+		FLASH0_WRITE (dev, 0x555, 0xaa);
+		FLASH0_WRITE (dev, 0xaaa, 0x55);
+		FLASH0_WRITE (dev, 0x555, 0xf0);
+	}
+
+	udelay (SLEEP_DELAY);
+
+	PRINTF ("flashReset: done\n");
+}
+
+PRIVATE int flashProbe (flash_dev_t * dev)
+{
+	int rv, deviceID, vendorID;
+
+	PRINTF ("flashProbe: dev=%d\n", DEV_NO (dev));
+
+	if (dev->bank != FLASH0_BANK) {
+		rv = ERROR;
+		goto DONE;
+	}
+
+	FLASH0_WRITE (dev, 0xaaa, 0xaa);
+	FLASH0_WRITE (dev, 0x555, 0x55);
+	FLASH0_WRITE (dev, 0xaaa, 0x90);
+
+	udelay (SLEEP_DELAY);
+
+	vendorID = FLASH0_READ (dev, 0);
+	deviceID = FLASH0_READ (dev, 2);
+
+	FLASH0_WRITE (dev, 0, 0xf0);
+
+	PRINTF ("flashProbe: vendor=0x%x device=0x%x\n", vendorID, deviceID);
+
+	if (vendorID == dev->vendorID && deviceID == dev->deviceID)
+		rv = OK;
+	else
+		rv = ERROR;
+
+  DONE:
+	PRINTF ("flashProbe: rv=%d\n", rv);
+
+	return rv;
+}
+
+PRIVATE int flashWait (flash_dev_t * dev, int addr, int expect, int erase)
+{
+	int rv = ERROR;
+	int i, data;
+	int polls;
+
+#if 0
+	PRINTF ("flashWait: dev=%d addr=0x%x expect=0x%x erase=%d\n",
+		DEV_NO (dev), addr, expect, erase);
+#endif
+
+	if (dev->bank != FLASH0_BANK) {
+		rv = ERROR;
+		goto done;
+	}
+
+	if (erase)
+		polls = FLASH_ERASE_SECTOR_TIMEOUT;	/* Ticks */
+	else
+		polls = FLASH_PROGRAM_POLLS;	/* Loops */
+
+	for (i = 0; i < polls; i++) {
+		if (erase)
+			udelay (SLEEP_DELAY);
+
+		data = FLASH0_READ (dev, addr);
+
+		if (((data ^ expect) & 0x80) == 0) {
+			rv = OK;
+			goto done;
+		}
+
+		if (data & 0x20) {
+			/*
+			 * If the 0x20 bit has come on, it could actually be because
+			 * the operation succeeded, so check the done bit again.
+			 */
+
+			data = FLASH0_READ (dev, addr);
+
+			if (((data ^ expect) & 0x80) == 0) {
+				rv = OK;
+				goto done;
+			}
+
+			printf ("flashWait: Program error (dev: %d, addr: 0x%x)\n",
+					DEV_NO (dev), addr);
+
+			flashReset (dev);
+			rv = ERROR;
+			goto done;
+		}
+	}
+
+	printf ("flashWait: Timeout %s (dev: %d, addr: 0x%x)\n",
+		erase ? "erasing sector" : "programming byte",
+		DEV_NO (dev), addr);
+
+  done:
+
+#if 0
+	PRINTF ("flashWait: rv=%d\n", rv);
+#endif
+
+	return rv;
+}
+
+/***********************************************************************
+ *
+ * Public Flash Routines
+ *
+ ***********************************************************************/
+
+STATUS flashLibInit (void)
+{
+	int i;
+
+	PRINTF ("flashLibInit: devices=%d\n", flashDevCount);
+
+	for (i = 0; i < flashDevCount; i++) {
+		flash_dev_t *dev = &flashDev[i];
+
+		/*
+		 * For bank 1, probe both without and with byte swappage,
+		 * so that this module works on both old and new Mousse boards.
+		 */
+
+		flashReset (dev);
+
+		if (flashProbe (dev) != ERROR)
+			dev->found = 1;
+
+		flashReset (dev);
+
+		if (flashProbe (dev) != ERROR)
+			dev->found = 1;
+
+		dev->swap = 0;
+
+		if (dev->found) {
+			PRINTF ("\n  FLASH %s[%d]: iobase=0x%x - %d sectors %d KB",
+				flashDev[i].name, i, flashDev[i].base,
+				flashDev[i].sectors,
+				(flashDev[i].sectors * FLASH_SECTOR_SIZE) / 1024);
+
+		}
+	}
+
+	flashLibInited = 1;
+
+	PRINTF ("flashLibInit: done\n");
+
+	return OK;
+}
+
+STATUS flashEraseSector (flash_dev_t * dev, int sector)
+{
+	int pos, addr;
+
+	PRINTF ("flashErasesector: dev=%d sector=%d\n", DEV_NO (dev), sector);
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	if (sector < 0 || sector >= dev->sectors) {
+		printf ("flashEraseSector: Sector out of range (dev: %d, sector: %d)\n", DEV_NO (dev), sector);
+		return ERROR;
+	}
+
+	pos = FLASH_SECTOR_POS (dev, sector);
+
+	if (dev->bank != FLASH0_BANK) {
+		return ERROR;
+	}
+
+	addr = pos;
+
+	FLASH0_WRITE (dev, 0xaaa, 0xaa);
+	FLASH0_WRITE (dev, 0x555, 0x55);
+	FLASH0_WRITE (dev, 0xaaa, 0x80);
+	FLASH0_WRITE (dev, 0xaaa, 0xaa);
+	FLASH0_WRITE (dev, 0x555, 0x55);
+	FLASH0_WRITE (dev, addr, 0x30);
+
+	return flashWait (dev, addr, 0xff, 1);
+}
+
+/*
+ * Note: it takes about as long to flash all sectors together with Chip
+ * Erase as it does to flash them one at a time (about 30 seconds for 2
+ * MB).  Also since we want to be able to treat subsets of sectors as if
+ * they were complete devices, we don't use Chip Erase.
+ */
+
+STATUS flashErase (flash_dev_t * dev)
+{
+	int sector;
+
+	PRINTF ("flashErase: dev=%d sectors=%d\n", DEV_NO (dev), dev->sectors);
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	for (sector = 0; sector < dev->sectors; sector++) {
+		if (flashEraseSector (dev, sector) == ERROR)
+			return ERROR;
+	}
+	return OK;
+}
+
+/*
+ * Read and write bytes
+ */
+
+STATUS flashRead (flash_dev_t * dev, int pos, char *buf, int len)
+{
+	int addr, words;
+
+	PRINTF ("flashRead: dev=%d pos=0x%x buf=0x%x len=0x%x\n",
+		DEV_NO (dev), pos, (int) buf, len);
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) {
+		printf ("flashRead: Position out of range "
+			"(dev: %d, pos: 0x%x, len: 0x%x)\n",
+			DEV_NO (dev), pos, len);
+		return ERROR;
+	}
+
+	if (len == 0)
+		return OK;
+
+	if (dev->bank == FLASH0_BANK) {
+		addr = pos;
+		words = len;
+
+		PRINTF ("flashRead: memcpy(0x%x, 0x%x, 0x%x)\n",
+			(int) buf, (int) FLASH0_ADDR (dev, pos), len);
+
+		memcpy (buf, FLASH0_ADDR (dev, addr), words);
+
+	}
+	PRINTF ("flashRead: rv=OK\n");
+
+	return OK;
+}
+
+STATUS flashWrite (flash_dev_t * dev, int pos, char *buf, int len)
+{
+	int addr, words;
+
+	PRINTF ("flashWrite: dev=%d pos=0x%x buf=0x%x len=0x%x\n",
+		DEV_NO (dev), pos, (int) buf, len);
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) {
+		printf ("flashWrite: Position out of range "
+			"(dev: %d, pos: 0x%x, len: 0x%x)\n",
+			DEV_NO (dev), pos, len);
+		return ERROR;
+	}
+
+	if (len == 0)
+		return OK;
+
+	if (dev->bank == FLASH0_BANK) {
+		unsigned char tmp;
+
+		addr = pos;
+		words = len;
+
+		while (words--) {
+			tmp = *buf;
+			if (~FLASH0_READ (dev, addr) & tmp) {
+				printf ("flashWrite: Attempt to program 0 to 1 "
+					"(dev: %d, addr: 0x%x, data: 0x%x)\n",
+					DEV_NO (dev), addr, tmp);
+				return ERROR;
+			}
+			FLASH0_WRITE (dev, 0xaaa, 0xaa);
+			FLASH0_WRITE (dev, 0x555, 0x55);
+			FLASH0_WRITE (dev, 0xaaa, 0xa0);
+			FLASH0_WRITE (dev, addr, tmp);
+			if (flashWait (dev, addr, tmp, 0) < 0)
+				return ERROR;
+			buf++;
+			addr++;
+		}
+	}
+
+	PRINTF ("flashWrite: rv=OK\n");
+
+	return OK;
+}
+
+/*
+ * flashWritable returns TRUE if a range contains all F's.
+ */
+
+STATUS flashWritable (flash_dev_t * dev, int pos, int len)
+{
+	int addr, words;
+	int rv = ERROR;
+
+	PRINTF ("flashWritable: dev=%d pos=0x%x len=0x%x\n",
+			DEV_NO (dev), pos, len);
+
+	if (flashCheck (dev) == ERROR)
+		goto done;
+
+	if (pos < 0 || len < 0 || pos + len > FLASH_MAX_POS (dev)) {
+		printf ("flashWritable: Position out of range "
+			"(dev: %d, pos: 0x%x, len: 0x%x)\n",
+			DEV_NO (dev), pos, len);
+		goto done;
+	}
+
+	if (len == 0) {
+		rv = 1;
+		goto done;
+	}
+
+	if (dev->bank == FLASH0_BANK) {
+		addr = pos;
+		words = len;
+
+		while (words--) {
+			if (FLASH0_READ (dev, addr) != 0xff) {
+				rv = 0;
+				goto done;
+			}
+			addr++;
+		}
+	}
+
+	rv = 1;
+
+  done:
+	PRINTF ("flashWrite: rv=%d\n", rv);
+	return rv;
+}
+
+
+/*
+ * NOTE: the below code cannot run from FLASH!!!
+ */
+/***********************************************************************
+ *
+ * Flash Diagnostics
+ *
+ ***********************************************************************/
+
+STATUS flashDiag (flash_dev_t * dev)
+{
+	unsigned int *buf = 0;
+	int i, len, sector;
+	int rv = ERROR;
+
+	if (flashCheck (dev) == ERROR)
+		return ERROR;
+
+	printf ("flashDiag: Testing device %d, "
+		"base: 0x%x, %d sectors @ %d kB = %d kB\n",
+		DEV_NO (dev), dev->base,
+		dev->sectors,
+		1 << (dev->lgSectorSize - 10),
+		dev->sectors << (dev->lgSectorSize - 10));
+
+	len = 1 << dev->lgSectorSize;
+
+	printf ("flashDiag: Erasing\n");
+
+	if (flashErase (dev) == ERROR) {
+		printf ("flashDiag: Erase failed\n");
+		goto done;
+	}
+	printf ("%d bytes requested ...\n", len);
+	buf = malloc (len);
+	printf ("allocated %d bytes ...\n", len);
+	if (buf == 0) {
+		printf ("flashDiag: Out of memory\n");
+		goto done;
+	}
+
+	/*
+	 * Write unique counting pattern to each sector
+	 */
+
+	for (sector = 0; sector < dev->sectors; sector++) {
+		printf ("flashDiag: Write sector %d\n", sector);
+
+		for (i = 0; i < len / 4; i++)
+			buf[i] = sector << 24 | i;
+
+		if (flashWrite (dev,
+				sector << dev->lgSectorSize,
+				(char *) buf, len) == ERROR) {
+			printf ("flashDiag: Write failed (dev: %d, sector: %d)\n",
+				DEV_NO (dev), sector);
+			goto done;
+		}
+	}
+
+	/*
+	 * Verify
+	 */
+
+	for (sector = 0; sector < dev->sectors; sector++) {
+		printf ("flashDiag: Verify sector %d\n", sector);
+
+		if (flashRead (dev,
+				   sector << dev->lgSectorSize,
+				   (char *) buf, len) == ERROR) {
+			printf ("flashDiag: Read failed (dev: %d, sector: %d)\n",
+				DEV_NO (dev), sector);
+			goto done;
+		}
+
+		for (i = 0; i < len / 4; i++) {
+			if (buf[i] != (sector << 24 | i)) {
+				printf ("flashDiag: Verify error "
+					"(dev: %d, sector: %d, offset: 0x%x)\n",
+					DEV_NO (dev), sector, i);
+				printf ("flashDiag: Expected 0x%08x, got 0x%08x\n",
+					sector << 24 | i, buf[i]);
+
+				goto done;
+			}
+		}
+	}
+
+	printf ("flashDiag: Erasing\n");
+
+	if (flashErase (dev) == ERROR) {
+		printf ("flashDiag: Final erase failed\n");
+		goto done;
+	}
+
+	rv = OK;
+
+  done:
+	if (buf)
+		free (buf);
+
+	if (rv == OK)
+		printf ("flashDiag: Device %d passed\n", DEV_NO (dev));
+	else
+		printf ("flashDiag: Device %d failed\n", DEV_NO (dev));
+
+	return rv;
+}
+
+STATUS flashDiagAll (void)
+{
+	int i;
+	int rv = OK;
+
+	PRINTF ("flashDiagAll: devices=%d\n", flashDevCount);
+
+	for (i = 0; i < flashDevCount; i++) {
+		flash_dev_t *dev = &flashDev[i];
+
+		if (dev->found && flashDiag (dev) == ERROR)
+			rv = ERROR;
+	}
+
+	if (rv == OK)
+		printf ("flashDiagAll: Passed\n");
+	else
+		printf ("flashDiagAll: Failed because of earlier errors\n");
+
+	return OK;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	flash_dev_t *dev = NULL;
+
+	flashLibInit ();
+
+	/*
+	 * Provide info for FLASH (up to 960K) of Kernel Image data.
+	 */
+	dev = FLASH_DEV_BANK0_LOW;
+	flash_info[FLASH_BANK_KERNEL].flash_id =
+			(dev->vendorID << 16) | dev->deviceID;
+	flash_info[FLASH_BANK_KERNEL].sector_count = dev->sectors;
+	flash_info[FLASH_BANK_KERNEL].size =
+			flash_info[FLASH_BANK_KERNEL].sector_count * FLASH_SECTOR_SIZE;
+	flash_info[FLASH_BANK_KERNEL].start[FIRST_SECTOR] = dev->base;
+	size += flash_info[FLASH_BANK_KERNEL].size;
+
+	/*
+	 * Provide info for 512K PLCC FLASH ROM (U-Boot)
+	 */
+	dev = FLASH_DEV_BANK0_BOOT;
+	flash_info[FLASH_BANK_BOOT].flash_id =
+			(dev->vendorID << 16) | dev->deviceID;
+	flash_info[FLASH_BANK_BOOT].sector_count = dev->sectors;
+	flash_info[FLASH_BANK_BOOT].size =
+			flash_info[FLASH_BANK_BOOT].sector_count * FLASH_SECTOR_SIZE;
+	flash_info[FLASH_BANK_BOOT].start[FIRST_SECTOR] = dev->base;
+	size += flash_info[FLASH_BANK_BOOT].size;
+
+
+	/*
+	 * Provide info for 512K FLASH0 segment (U-Boot)
+	 */
+	dev = FLASH_DEV_BANK0_HIGH;
+	flash_info[FLASH_BANK_AUX].flash_id =
+			(dev->vendorID << 16) | dev->deviceID;
+	flash_info[FLASH_BANK_AUX].sector_count = dev->sectors;
+	flash_info[FLASH_BANK_AUX].size =
+			flash_info[FLASH_BANK_AUX].sector_count * FLASH_SECTOR_SIZE;
+	flash_info[FLASH_BANK_AUX].start[FIRST_SECTOR] = dev->base;
+	size += flash_info[FLASH_BANK_AUX].size;
+
+
+	return size;
+}
+
+/*
+ * Get flash device from U-Boot flash info.
+ */
+flash_dev_t *getFlashDevFromInfo (flash_info_t * info)
+{
+	int i;
+
+	if (!info)
+		return NULL;
+
+	for (i = 0; i < flashDevCount; i++) {
+		flash_dev_t *dev = &flashDev[i];
+
+		if (dev->found && (dev->base == info->start[0]))
+			return dev;
+	}
+	printf ("ERROR: notice, no FLASH mapped at address 0x%x\n",
+			(unsigned int) info->start[0]);
+	return NULL;
+}
+
+ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	int i;
+
+	for (i = 0; i < flashDevCount; i++) {
+		flash_dev_t *dev = &flashDev[i];
+
+		if (dev->found) {
+			if (dev->base == (unsigned int) addr) {
+				info->flash_id = (dev->vendorID << 16) | dev->deviceID;
+				info->sector_count = dev->sectors;
+				info->size = info->sector_count * FLASH_SECTOR_SIZE;
+				return dev->sectors * FLASH_SECTOR_SIZE;
+			}
+		}
+	}
+	return 0;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	unsigned int chip;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x1:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+	chip = (unsigned int) info->flash_id & 0x000000ff;
+
+	switch (chip) {
+
+	case AMD_ID_F040B:
+		printf ("AM29F040B (4 Mbit)\n");
+		break;
+
+	case AMD_ID_LV160B:
+	case FLASH_AM160LV:
+	case 0x49:
+		printf ("AM29LV160B (16 Mbit / 2M x 8bit)\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type:0x%x\n", chip);
+		break;
+	}
+
+	printf ("  Size: %ld bytes in %d Sectors\n",
+		info->size, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[FIRST_SECTOR] + i * FLASH_SECTOR_SIZE,
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+
+/*
+ * Erase a range of flash sectors.
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	int prot, sect, l_sect;
+	flash_dev_t *dev = NULL;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Start erase on unprotected sectors */
+	dev = getFlashDevFromInfo (info);
+	if (dev) {
+		printf ("Erase FLASH[%s] -%d sectors:", dev->name, dev->sectors);
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				addr = (vu_long *) (dev->base);
+				/*   printf("erase_sector: sector=%d, addr=0x%x\n",
+				   sect, addr); */
+				printf (".");
+				if (ERROR == flashEraseSector (dev, sect)) {
+					printf ("ERROR: could not erase sector %d on FLASH[%s]\n", sect, dev->name);
+					return 1;
+				}
+			}
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+
+	flash_dev_t *dev = getFlashDevFromInfo (info);
+	int addr = dest - info->start[0];
+
+	if (!dev)
+		return 1;
+
+	if (OK != flashWrite (dev, addr, (char *) &data, sizeof (ulong))) {
+		printf ("ERROR: could not write to addr=0x%x, data=0x%x\n",
+			(unsigned int) addr, (unsigned) data);
+		return 1;
+	}
+
+	if ((addr % FLASH_SECTOR_SIZE) == 0)
+		printf (".");
+
+
+	PRINTF ("write_word:0x%x, base=0x%x, addr=0x%x, data=0x%x\n",
+		(unsigned) info->start[0],
+		(unsigned) dest,
+		(unsigned) (dest - info->start[0]), (unsigned) data);
+
+	return (0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	flash_dev_t *dev = getFlashDevFromInfo (info);
+
+	if (dev) {
+		printf ("FLASH[%s]:", dev->name);
+		wp = (addr & ~3);	/* get lower word aligned address */
+
+		/*
+		 * handle unaligned start bytes
+		 */
+		if ((l = addr - wp) != 0) {
+			data = 0;
+			for (i = 0, cp = wp; i < l; ++i, ++cp) {
+				data = (data << 8) | (*(uchar *) cp);
+			}
+			for (; i < 4 && cnt > 0; ++i) {
+				data = (data << 8) | *src++;
+				--cnt;
+				++cp;
+			}
+			for (; cnt == 0 && i < 4; ++i, ++cp) {
+				data = (data << 8) | (*(uchar *) cp);
+			}
+			if ((rc = write_word (info, wp, data)) != 0) {
+				return (rc);
+			}
+			wp += 4;
+		}
+
+		/*
+		 * handle word aligned part
+		 */
+		while (cnt >= 4) {
+			data = 0;
+			for (i = 0; i < 4; ++i) {
+				data = (data << 8) | *src++;
+			}
+			if ((rc = write_word (info, wp, data)) != 0) {
+				return (rc);
+			}
+			wp += 4;
+			cnt -= 4;
+		}
+
+		if (cnt == 0) {
+			return (0);
+		}
+
+		/*
+		 * handle unaligned tail bytes
+		 */
+		data = 0;
+		for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+			data = (data << 8) | *src++;
+			--cnt;
+		}
+		for (; i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		return (write_word (info, wp, data));
+	}
+	return 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/mousse/flash.h b/board/mousse/flash.h
new file mode 100755
index 0000000..b7e4619
--- /dev/null
+++ b/board/mousse/flash.h
@@ -0,0 +1,78 @@
+#ifndef	FLASH_LIB_H
+#define	FLASH_LIB_H
+
+#include <common.h>
+
+/* PIO operations max */
+#define	FLASH_PROGRAM_POLLS		100000
+
+/* 10 Seconds default */
+#define	FLASH_ERASE_SECTOR_TIMEOUT	(10*1000 /*SEC*/ )
+
+/* Flash device info structure */
+typedef struct flash_dev_s {
+    char        name[24];               /* Bank Name */
+    int		bank;			/* Bank 0 or 1 */
+    unsigned int base;			/* Base address */
+    int		sectors;		/* Sector count */
+    int		lgSectorSize;		/* Log2(usable bytes/sector) */
+    int		vendorID;		/* Expected vendor ID */
+    int		deviceID;		/* Expected device ID */
+    int		found;			/* Set if found by flashLibInit */
+    int		swap;			/* Set for bank 1 if byte swap req'd */
+} flash_dev_t;
+
+#define FLASH_MAX_POS(dev) \
+	((dev)->sectors << (dev)->lgSectorSize)
+
+#define FLASH_SECTOR_POS(dev, sector) \
+	((sector) << (dev)->lgSectorSize)
+
+/* AMD 29F040 */
+#define FLASH0_BANK			0
+#define FLASH0_VENDOR_ID		0x01
+#define FLASH0_DEVICE_ID		0x49
+
+/* AMD29LV160DB */
+#define FLASH1_BANK			1
+#define FLASH1_VENDOR_ID		0x0001
+#define FLASH1_DEVICE_ID		0x2249
+
+extern	flash_dev_t			flashDev[];
+extern	int				flashDevCount;
+
+/*
+ * Device pointers
+ *
+ * These must be kept in sync with the table in flashLib.c.
+ */
+#define FLASH_DEV_BANK0_SA0		(&flashDev[0])
+#define FLASH_DEV_BANK0_SA1		(&flashDev[1])
+#define FLASH_DEV_BANK0_SA2		(&flashDev[2])
+#define FLASH_DEV_BANK0_LOW		(&flashDev[3]) /* 960K */
+#define FLASH_DEV_BANK0_BOOT		(&flashDev[4]) /* PLCC */
+#define FLASH_DEV_BANK0_HIGH		(&flashDev[5]) /* 512K PLCC shadow */
+
+unsigned long flash_init(void);
+int flashEraseSector(flash_dev_t *dev, int sector);
+int flashErase(flash_dev_t *dev);
+int flashRead(flash_dev_t *dev, int pos, char *buf, int len);
+int flashWrite(flash_dev_t *dev, int pos, char *buf, int len);
+int flashWritable(flash_dev_t *dev, int pos, int len);
+int flashDiag(flash_dev_t *dev);
+int flashDiagAll(void);
+
+ulong flash_get_size (vu_long *addr, flash_info_t *info);
+void flash_print_info  (flash_info_t *info);
+int  flash_erase (flash_info_t *info, int s_first, int s_last);
+int  write_buff  (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+
+/*
+ * Flash info indices.
+ */
+#define FLASH_BANK_KERNEL 0
+#define FLASH_BANK_BOOT   1
+#define FLASH_BANK_AUX    2
+#define FIRST_SECTOR      0
+
+#endif	/* !FLASH_LIB_H */
diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c
new file mode 100755
index 0000000..37a6244
--- /dev/null
+++ b/board/mousse/m48t59y.c
@@ -0,0 +1,322 @@
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ *
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and
+ * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD)
+ * registers which are used to set/get the internal date/time functions.
+ *
+ * This module implements Y2K compliance by taking full year numbers
+ * and translating back and forth from the TOD 2-digit year.
+ *
+ * NOTE: for proper interaction with an operating system, the TOD should
+ * be used to store Universal Coordinated Time (GMT) and timezone
+ * conversions should be used.
+ *
+ * Here is a diagram of the memory layout:
+ *
+ * +---------------------------------------------+ 0xffe0a000
+ * | Non-volatile memory                         | .
+ * |                                             | .
+ * | (8176 bytes of Non-volatile memory)         | .
+ * |                                             | .
+ * +---------------------------------------------+ 0xffe0bff0
+ * | Flags                                       |
+ * +---------------------------------------------+ 0xffe0bff1
+ * | Unused                                      |
+ * +---------------------------------------------+ 0xffe0bff2
+ * | Alarm Seconds                               |
+ * +---------------------------------------------+ 0xffe0bff3
+ * | Alarm Minutes                               |
+ * +---------------------------------------------+ 0xffe0bff4
+ * | Alarm Date                                  |
+ * +---------------------------------------------+ 0xffe0bff5
+ * | Interrupts                                  |
+ * +---------------------------------------------+ 0xffe0bff6
+ * | WatchDog                                    |
+ * +---------------------------------------------+ 0xffe0bff7
+ * | Calibration                                 |
+ * +---------------------------------------------+ 0xffe0bff8
+ * | Seconds                                     |
+ * +---------------------------------------------+ 0xffe0bff9
+ * | Minutes                                     |
+ * +---------------------------------------------+ 0xffe0bffa
+ * | Hours                                       |
+ * +---------------------------------------------+ 0xffe0bffb
+ * | Day                                         |
+ * +---------------------------------------------+ 0xffe0bffc
+ * | Date                                        |
+ * +---------------------------------------------+ 0xffe0bffd
+ * | Month                                       |
+ * +---------------------------------------------+ 0xffe0bffe
+ * | Year (2 digits only)                        |
+ * +---------------------------------------------+ 0xffe0bfff
+ */
+#include <common.h>
+#include <rtc.h>
+#include "mousse.h"
+
+/*
+ * Imported from mousse.h:
+ *
+ *   TOD_REG_BASE		Base of m48t59y TOD registers
+ *   SYS_TOD_UNPROTECT()	Disable NVRAM write protect
+ *   SYS_TOD_PROTECT()		Re-enable NVRAM write protect
+ */
+
+#define YEAR		0xf
+#define MONTH		0xe
+#define DAY		0xd
+#define DAY_OF_WEEK	0xc
+#define HOUR		0xb
+#define MINUTE		0xa
+#define SECOND		0x9
+#define CONTROL		0x8
+#define WATCH		0x7
+#define INTCTL		0x6
+#define WD_DATE		0x5
+#define WD_HOUR		0x4
+#define WD_MIN		0x3
+#define WD_SEC		0x2
+#define _UNUSED		0x1
+#define FLAGS		0x0
+
+#define M48_ADDR	((volatile unsigned char *) TOD_REG_BASE)
+
+int m48_tod_init(void)
+{
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] = 0;
+    M48_ADDR[WATCH] = 0;
+    M48_ADDR[INTCTL] = 0;
+
+    /*
+     * If the oscillator is currently stopped (as on a new part shipped
+     * from the factory), start it running.
+     *
+     * Here is an example of the TOD bytes on a brand new M48T59Y part:
+     *		00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01
+     */
+
+    if (M48_ADDR[SECOND] & 0x80)
+	M48_ADDR[SECOND] = 0;
+
+    /* Is battery low */
+    if ( M48_ADDR[FLAGS] & 0x10) {
+	 printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n");
+    }
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+/*
+ * m48_tod_set
+ */
+
+static int to_bcd(int value)
+{
+    return value / 10 * 16 + value % 10;
+}
+
+static int from_bcd(int value)
+{
+    return value / 16 * 10 + value % 16;
+}
+
+static int day_of_week(int y, int m, int d)	/* 0-6 ==> Sun-Sat */
+{
+    static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4};
+    y -= m < 3;
+    return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7;
+}
+
+/*
+ * Note: the TOD should store the current GMT
+ */
+
+int m48_tod_set(int year,		/* 1980-2079 */
+		int month,		/* 01-12 */
+		int day,		/* 01-31 */
+		int hour,		/* 00-23 */
+		int minute,		/* 00-59 */
+		int second)		/* 00-59 */
+
+{
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] |= 0x80;	/* Set WRITE bit */
+
+    M48_ADDR[YEAR] = to_bcd(year % 100);
+    M48_ADDR[MONTH] = to_bcd(month);
+    M48_ADDR[DAY] = to_bcd(day);
+    M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1;
+    M48_ADDR[HOUR] = to_bcd(hour);
+    M48_ADDR[MINUTE] = to_bcd(minute);
+    M48_ADDR[SECOND] = to_bcd(second);
+
+    M48_ADDR[CONTROL] &= ~0x80;	/* Clear WRITE bit */
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+/*
+ * Note: the TOD should store the current GMT
+ */
+
+int m48_tod_get(int *year,		/* 1980-2079 */
+		int *month,		/* 01-12 */
+		int *day,		/* 01-31 */
+		int *hour,		/* 00-23 */
+		int *minute,		/* 00-59 */
+		int *second)		/* 00-59 */
+{
+    int y;
+
+    SYS_TOD_UNPROTECT();
+
+    M48_ADDR[CONTROL] |= 0x40;	/* Set READ bit */
+
+    y = from_bcd(M48_ADDR[YEAR]);
+    *year = y < 80 ? 2000 + y : 1900 + y;
+    *month = from_bcd(M48_ADDR[MONTH]);
+    *day = from_bcd(M48_ADDR[DAY]);
+    /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */
+    *hour = from_bcd(M48_ADDR[HOUR]);
+    *minute = from_bcd(M48_ADDR[MINUTE]);
+    *second = from_bcd(M48_ADDR[SECOND] & 0x7f);
+
+    M48_ADDR[CONTROL] &= ~0x40;	/* Clear READ bit */
+
+    SYS_TOD_PROTECT();
+
+    return 0;
+}
+
+int m48_tod_get_second(void)
+{
+    return from_bcd(M48_ADDR[SECOND] & 0x7f);
+}
+
+/*
+ * Watchdog function
+ *
+ *  If usec is 0, the watchdog timer is disarmed.
+ *
+ *  If usec is non-zero, the watchdog timer is armed (or re-armed) for
+ *    approximately usec microseconds (if the exact requested usec is
+ *    not supported by the chip, the next higher available value is used).
+ *
+ *  Minimum watchdog timeout = 62500 usec
+ *  Maximum watchdog timeout = 124 sec (124000000 usec)
+ */
+
+void m48_watchdog_arm(int usec)
+{
+    int		mpy, res;
+
+    SYS_TOD_UNPROTECT();
+
+    if (usec == 0) {
+	res = 0;
+	mpy = 0;
+    } else if (usec < 2000000) {	/* Resolution: 1/16s if below 2s */
+	res = 0;
+	mpy = (usec + 62499) / 62500;
+    } else if (usec < 8000000) {	/* Resolution: 1/4s if below 8s */
+	res = 1;
+	mpy = (usec + 249999) / 250000;
+    } else if (usec < 32000000) {	/* Resolution: 1s if below 32s */
+	res = 2;
+	mpy = (usec + 999999) / 1000000;
+    } else {				/* Resolution: 4s up to 124s */
+	res = 3;
+	mpy = (usec + 3999999) / 4000000;
+	if (mpy > 31)
+	    mpy = 31;
+    }
+
+    M48_ADDR[WATCH] = (0x80 |		/* Steer to RST signal (IRQ = N/C) */
+		       mpy << 2 |
+		       res);
+
+    SYS_TOD_PROTECT();
+}
+
+/*
+ * U-Boot RTC support.
+ */
+void
+rtc_get( struct rtc_time *tmp )
+{
+	m48_tod_get(&tmp->tm_year,
+		    &tmp->tm_mon,
+		    &tmp->tm_mday,
+		    &tmp->tm_hour,
+		    &tmp->tm_min,
+		    &tmp->tm_sec);
+	tmp->tm_yday = 0;
+	tmp->tm_isdst= 0;
+
+#ifdef RTC_DEBUG
+	printf( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
+#endif
+}
+
+void
+rtc_set( struct rtc_time *tmp )
+{
+	m48_tod_set(tmp->tm_year,		/* 1980-2079 */
+		    tmp->tm_mon,		/* 01-12 */
+		    tmp->tm_mday,              /* 01-31 */
+		    tmp->tm_hour,		/* 00-23 */
+		    tmp->tm_min,		/* 00-59 */
+		    tmp->tm_sec);		/* 00-59 */
+
+#ifdef RTC_DEBUG
+	printf( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+#endif
+
+}
+
+void
+rtc_reset (void)
+{
+  m48_tod_init();
+}
diff --git a/board/mousse/m48t59y.h b/board/mousse/m48t59y.h
new file mode 100755
index 0000000..717300d
--- /dev/null
+++ b/board/mousse/m48t59y.h
@@ -0,0 +1,57 @@
+/*
+ * SGS M48-T59Y TOD/NVRAM Driver
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
+ *
+ * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __M48_T59_Y_H
+#define __M48_T59_Y_H
+
+/*
+ * M48 T59Y -Timekeeping Battery backed SRAM.
+ */
+
+int m48_tod_init(void);
+
+int m48_tod_set(int year,
+		int month,
+		int day,
+		int hour,
+		int minute,
+		int second);
+
+int m48_tod_get(int *year,
+		int *month,
+		int *day,
+		int *hour,
+		int *minute,
+		int *second);
+
+int m48_tod_get_second(void);
+
+void m48_watchdog_arm(int usec);
+
+#endif /*!__M48_T59_Y_H */
diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c
new file mode 100755
index 0000000..7208a17
--- /dev/null
+++ b/board/mousse/mousse.c
@@ -0,0 +1,86 @@
+/*
+ * MOUSSE Board Support
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James Dougherty, jfd@cs.stanford.edu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#include "mousse.h"
+#include "m48t59y.h"
+#include <pci.h>
+
+
+int checkboard (void)
+{
+	ulong busfreq = get_bus_freq (0);
+	char buf[32];
+
+	puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n");
+	printf ("Built: %s at %s\n", __DATE__, __TIME__);
+	printf ("MPLD:  Revision %d\n", SYS_REVID_GET ());
+	printf ("Local Bus:  %s MHz\n", strmhz (buf, busfreq));
+
+	return 0;
+}
+
+int checkflash (void)
+{
+	printf ("checkflash\n");
+	flash_init ();
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return CFG_RAM_SIZE;
+}
+
+
+void get_tod (void)
+{
+	int year, month, day, hour, minute, second;
+
+	m48_tod_get (&year, &month, &day, &hour, &minute, &second);
+
+	printf ("  Current date/time: %d/%d/%d %d:%d:%d \n",
+		month, day, year, hour, minute, second);
+
+}
+
+/*
+ * EPIC, PCI, and I/O devices.
+ * Initialize Mousse Platform, probe for PCI devices,
+ * Query configuration parameters if not set.
+ */
+int misc_init_f (void)
+{
+	m48_tod_init ();	/* Init SGS M48T59Y TOD/NVRAM */
+	printf ("RTC:   M48T589 TOD/NVRAM (%d) bytes\n", TOD_NVRAM_SIZE);
+	get_tod ();
+	return 0;
+}
diff --git a/board/mousse/mousse.h b/board/mousse/mousse.h
new file mode 100755
index 0000000..5468314
--- /dev/null
+++ b/board/mousse/mousse.h
@@ -0,0 +1,259 @@
+/*
+ * MOUSSE/MPC8240 Board definitions.
+ * For more info, see http://www.vooha.com/
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James Dougherty (jfd@cs.stanford.edu)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MOUSSE_H
+#define __MOUSSE_H
+
+/* System addresses */
+
+#define PCI_SPECIAL_BASE	0xfe000000
+#define PCI_SPECIAL_SIZE	0x01000000
+
+/* PORTX Device Addresses for Mousse */
+
+#define PORTX_DEV_BASE		0xff000000
+#define PORTX_DEV_SIZE		0x01000000
+
+#define ENET_DEV_BASE		0x80000000
+
+#define PLD_REG_BASE		(PORTX_DEV_BASE | 0xe09000)
+#define PLD_REG(off)		(*(volatile unsigned char *) \
+				 (PLD_REG_BASE + (off)))
+
+#define PLD_REVID_B1		0x7f
+#define PLD_REVID_B2		0x01
+
+/* MPLD */
+#define SYS_HARD_RESET()	{ for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
+#define SYS_REVID_GET()		((int) PLD_REG(0) & 0x7f)
+#define SYS_LED_OFF()		(PLD_REG(1) |= 0x80)
+#define SYS_LED_ON()		(PLD_REG(1) &= ~0x80)
+#define SYS_WATCHDOG_IRQ3()	(PLD_REG(2) |= 0x80)
+#define SYS_WATCHDOG_RESET()	(PLD_REG(2) &= ~0x80)
+#define SYS_TOD_PROTECT()	(PLD_REG(3) |= 0x80)
+#define SYS_TOD_UNPROTECT()	(PLD_REG(3) &= ~0x80)
+
+/* SGS M48T59Y */
+#define TOD_BASE		(PORTX_DEV_BASE | 0xe0a000)
+#define TOD_REG_BASE		(TOD_BASE | 0x1ff0)
+#define TOD_NVRAM_BASE		TOD_BASE
+#define TOD_NVRAM_SIZE		0x1ff0
+#define TOD_NVRAM_LIMIT		(TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
+
+/* NS16552 SIO */
+#define SERIAL_BASE(_x)		(PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80))
+#define N_SIO_CHANNELS		2
+#define N_COM_PORTS		N_SIO_CHANNELS
+
+/*
+ * On-board Dec21143 PCI Ethernet
+ * Note: The PCI MBAR chosen here was used from MPC8240UM which states
+ * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS]
+ * is set, then PCI memory maps 1-1 with this address range in the
+ * correct byte order.
+ */
+#define PCI_ENET_IOADDR		0x80000000
+#define PCI_ENET_MEMADDR	0x80000000
+
+/*
+ * Flash Memory Layout
+ *
+ *    2 MB Flash Bank 0 runs in 8-bit mode.  In Flash Bank 0, the 32 kB
+ *    sector SA3 is obscured by the 32 kB serial/TOD access space, and
+ *    the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC
+ *    containing the fixed boot ROM.  (If the 512 kB PLCC is
+ *    deconfigured by jumper, this window to Flash Bank 0 becomes
+ *    visible, but it still contains the fixed boot code and should be
+ *    considered read-only).  Flash Bank 0 sectors SA0 (16 kB), SA1 (8
+ *    kB), and SA2 (8 kB) are currently unused.
+ *
+ *    2 MB Flash Bank 1 runs in 16-bit mode.  Flash Bank 1 is fully
+ *    usable, but it's a 16-bit wide device on a 64-bit bus.  Therefore
+ *    16-bit words only exist at addresses that are multiples of 8.  All
+ *    PROM data and control addresses must be multiplied by 8.
+ *
+ *    See flashMap.c for description of flash filesystem layout.
+ */
+
+/*
+ * FLASH memory address space: 8-bit wide FLASH memory spaces.
+ */
+#define FLASH0_SEG0_START	0xffe00000	 /* Baby 32Kb segment */
+#define FLASH0_SEG0_END		0xffe07fff	 /* 16 kB + 8 kB + 8 kB */
+#define FLASH0_SEG0_SIZE	0x00008000	 /*   (sectors SA0-SA2) */
+
+#define FLASH0_SEG1_START	0xffe10000	 /* 1MB - 64Kb FLASH0 seg */
+#define FLASH0_SEG1_END		0xffefffff	 /* 960 kB */
+#define FLASH0_SEG1_SIZE	0x000f0000
+
+#define FLASH0_SEG2_START	0xfff00000	 /* Boot Loader stored here */
+#define FLASH0_SEG2_END		0xfff7ffff	 /* 512 kB FLASH0/PLCC seg */
+#define FLASH0_SEG2_SIZE	0x00080000
+
+#define FLASH0_SEG3_START	0xfff80000	 /* 512 kB FLASH0 seg */
+#define FLASH0_SEG3_END		0xffffffff
+#define FLASH0_SEG3_SIZE	0x00080000
+
+/* Where Kahlua starts */
+#define FLASH_RESET_VECT	0xfff00100
+
+/*
+ * CHRP / PREP (MAP A/B) definitions.
+ */
+
+#define PREP_REG_ADDR		0x80000cf8	/* MPC107 Config, Map A */
+#define PREP_REG_DATA		0x80000cfc	/* MPC107 Config, Map A */
+/* MPC107 (MPC8240 internal EUMBBAR mapped) */
+#define CHRP_REG_ADDR		0xfec00000	/* MPC106 Config, Map B */
+#define CHRP_REG_DATA		0xfee00000	/* MPC106 Config, Map B */
+
+/*
+ * Mousse PCI IDSEL Assignments (Device Number)
+ */
+#define MOUSSE_IDSEL_ENET	13		/* On-board 21143 Ethernet */
+#define MOUSSE_IDSEL_LPCI	14		/* On-board PCI slot */
+#define MOUSSE_IDSEL_82371	15		/* That other thing */
+#define MOUSSE_IDSEL_CPCI2	31		/* CPCI slot 2 */
+#define MOUSSE_IDSEL_CPCI3	30		/* CPCI slot 3 */
+#define MOUSSE_IDSEL_CPCI4	29		/* CPCI slot 4 */
+#define MOUSSE_IDSEL_CPCI5	28		/* CPCI slot 5 */
+#define MOUSSE_IDSEL_CPCI6	27		/* CPCI slot 6 */
+
+/*
+ * Mousse Interrupt Mapping:
+ *
+ *	IRQ1	Enet (intA|intB|intC|intD)
+ *	IRQ2	CPCI intA (See below)
+ *	IRQ3	Local PCI slot intA|intB|intC|intD
+ *	IRQ4	COM1 Serial port (Actually higher addressed port on duart)
+ *
+ * PCI Interrupt Mapping in CPCI chassis:
+ *
+ *		   |	       CPCI Slot
+ *		   | 1 (CPU)	2	3	4	5	6
+ *	-----------+--------+-------+-------+-------+-------+-------+
+ *	  intA	   |	X		X		X
+ *	  intB	   |		X		X		X
+ *	  intC	   |	X		X		X
+ *	  intD	   |		X		X		X
+ */
+
+
+#define EPIC_VECTOR_EXT0	0
+#define EPIC_VECTOR_EXT1	1
+#define EPIC_VECTOR_EXT2	2
+#define EPIC_VECTOR_EXT3	3
+#define EPIC_VECTOR_EXT4	4
+#define EPIC_VECTOR_TM0		16
+#define EPIC_VECTOR_TM1		17
+#define EPIC_VECTOR_TM2		18
+#define EPIC_VECTOR_TM3		19
+#define EPIC_VECTOR_I2C		20
+#define EPIC_VECTOR_DMA0	21
+#define EPIC_VECTOR_DMA1	22
+#define EPIC_VECTOR_I2O		23
+
+
+#define INT_VEC_IRQ0		0
+#define INT_NUM_IRQ0		INT_VEC_IRQ0
+#define MOUSSE_IRQ_ENET		EPIC_VECTOR_EXT1	/* Hardwired */
+#define MOUSSE_IRQ_CPCI		EPIC_VECTOR_EXT2	/* Hardwired */
+#define MOUSSE_IRQ_LPCI		EPIC_VECTOR_EXT3	/* Hardwired */
+#define MOUSSE_IRQ_DUART	EPIC_VECTOR_EXT4	/* Hardwired */
+
+/* Onboard DEC 21143 Ethernet */
+#define PCI_ENET_MEMADDR	0x80000000
+#define PCI_ENET_IOADDR		0x80000000
+
+/* Some other PCI device */
+#define PCI_SLOT_MEMADDR	0x81000000
+#define PCI_SLOT_IOADDR		0x81000000
+
+/* Promise ATA66 PCI Device (ATA controller) */
+#define PROMISE_MBAR0  0xa0000000
+#define PROMISE_MBAR1  (PROMISE_MBAR0 + 0x1000)
+#define PROMISE_MBAR2  (PROMISE_MBAR0 + 0x2000)
+#define PROMISE_MBAR3  (PROMISE_MBAR0 + 0x3000)
+#define PROMISE_MBAR4  (PROMISE_MBAR0 + 0x4000)
+#define PROMISE_MBAR5  (PROMISE_MBAR0 + 0x5000)
+
+/* ATA/66 Controller offsets */
+#define CFG_ATA_BASE_ADDR     PROMISE_MBAR0
+#define CFG_IDE_MAXBUS	       2 /* ide0/ide1 */
+#define CFG_IDE_MAXDEVICE      2 /* 2 drives per controller */
+#define CFG_ATA_IDE0_OFFSET    0
+#define CFG_ATA_IDE1_OFFSET    0x3000
+/*
+ * Definitions for accessing IDE controller registers
+ */
+#define CFG_ATA_DATA_OFFSET    0
+#define CFG_ATA_REG_OFFSET     0
+#define CFG_ATA_ALT_OFFSET    (0x1000)
+
+/*
+ * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
+ * are defined in config.h and Makefile.
+ * All definitions for these constants must be identical.
+ */
+#define ROM_BASE_ADRS		0xfff00000	/* base address of ROM */
+#define ROM_TEXT_ADRS		(ROM_BASE_ADRS+0x0100) /* with PC & SP */
+#define ROM_WARM_ADRS		(ROM_TEXT_ADRS+0x0004) /* warm reboot entry */
+#define ROM_SIZE		0x00080000	/* 512KB ROM space */
+#define RAM_LOW_ADRS		0x00010000   /* RAM address for vxWorks */
+#define RAM_HIGH_ADRS		0x00c00000   /* RAM address for bootrom */
+
+/*
+ *  NVRAM configuration
+ *  NVRAM is implemented via the SGS Thomson M48T59Y
+ *  64Kbit (8Kbx8) Timekeeper SRAM.
+ *  This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information.
+ */
+
+#define NV_RAM_ADRS		TOD_NVRAM_BASE
+#define NV_RAM_INTRVL		1
+#define NV_RAM_WR_ENBL		SYS_TOD_UNPROTECT()
+#define NV_RAM_WR_DSBL		SYS_TOD_PROTECT()
+
+#define NV_OFF_BOOT0		0x0000	/* Boot string 0 (256b) */
+#define NV_OFF_BOOT1		0x0100	/* Boot string 1 (256b) */
+#define NV_OFF_BOOT2		0x0200	/* Boot string 2 (256b)*/
+#define NV_OFF_MACADDR		0x0400	/* 21143 MAC address (6b) */
+#define NV_OFF_ACTIVEBOOT	0x0406	/* Active boot string, 0 to 2 (1b) */
+#define NV_OFF_UNUSED1		0x0407	/* Unused (1b) */
+#define NV_OFF_BINDFIX		0x0408	/* See sysLib.c:sysBindFix() (1b) */
+#define NV_OFF_UNUSED2		0x0409	/* Unused (7b) */
+#define NV_OFF_TIMEZONE		0x0410	/* TIMEZONE env var (64b) */
+#define NV_OFF_VXWORKS_END	0x07FF	/* 2047 VxWorks Total */
+#define NV_OFF_U_BOOT		0x0800	/* 2048 U-Boot boot-loader */
+#define NV_OFF_U_BOOT_ADDR	(TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/
+#define NV_U_BOOT_ENV_SIZE	2048	/* 2K - U-Boot Total */
+#define NV_OFF__next_free	(NV_U_BOOT_ENVSIZE +1)
+#define NV_RAM_SIZE		8176	/* NVRAM End */
+
+#endif /* __MOUSSE_H */
diff --git a/board/mousse/pci.c b/board/mousse/pci.c
new file mode 100755
index 0000000..4f39398
--- /dev/null
+++ b/board/mousse/pci.c
@@ -0,0 +1,283 @@
+/*
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James Dougherty (jfd@cs.stanford.edu)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI Configuration space access support for MPC824x/MPC107 PCI Bridge
+ */
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+#include "mousse.h"
+
+/*
+ * Promise ATA/66 support.
+ */
+#define XFER_PIO_4	0x0C	/* 0000|1100 */
+#define XFER_PIO_3	0x0B	/* 0000|1011 */
+#define XFER_PIO_2	0x0A	/* 0000|1010 */
+#define XFER_PIO_1	0x09	/* 0000|1001 */
+#define XFER_PIO_0	0x08	/* 0000|1000 */
+#define XFER_PIO_SLOW	0x00	/* 0000|0000 */
+
+/* Promise Regs */
+#define REG_A		0x01
+#define REG_B		0x02
+#define REG_C		0x04
+#define REG_D		0x08
+
+void
+pdc202xx_decode_registers (unsigned char registers, unsigned char value)
+{
+	unsigned char	bit = 0, bit1 = 0, bit2 = 0;
+	switch(registers) {
+		case REG_A:
+			bit2 = 0;
+			printf("  A Register ");
+			if (value & 0x80) printf("SYNC_IN ");
+			if (value & 0x40) printf("ERRDY_EN ");
+			if (value & 0x20) printf("IORDY_EN ");
+			if (value & 0x10) printf("PREFETCH_EN ");
+			if (value & 0x08) { printf("PA3 ");bit2 |= 0x08; }
+			if (value & 0x04) { printf("PA2 ");bit2 |= 0x04; }
+			if (value & 0x02) { printf("PA1 ");bit2 |= 0x02; }
+			if (value & 0x01) { printf("PA0 ");bit2 |= 0x01; }
+			printf("PIO(A) = %d ", bit2);
+			break;
+		case REG_B:
+			bit1 = 0;bit2 = 0;
+			printf("  B Register ");
+			if (value & 0x80) { printf("MB2 ");bit1 |= 0x80; }
+			if (value & 0x40) { printf("MB1 ");bit1 |= 0x40; }
+			if (value & 0x20) { printf("MB0 ");bit1 |= 0x20; }
+			printf("DMA(B) = %d ", bit1 >> 5);
+			if (value & 0x10) printf("PIO_FORCED/PB4 ");
+			if (value & 0x08) { printf("PB3 ");bit2 |= 0x08; }
+			if (value & 0x04) { printf("PB2 ");bit2 |= 0x04; }
+			if (value & 0x02) { printf("PB1 ");bit2 |= 0x02; }
+			if (value & 0x01) { printf("PB0 ");bit2 |= 0x01; }
+			printf("PIO(B) = %d ", bit2);
+			break;
+		case REG_C:
+			bit2 = 0;
+			printf("  C Register ");
+			if (value & 0x80) printf("DMARQp ");
+			if (value & 0x40) printf("IORDYp ");
+			if (value & 0x20) printf("DMAR_EN ");
+			if (value & 0x10) printf("DMAW_EN ");
+
+			if (value & 0x08) { printf("MC3 ");bit2 |= 0x08; }
+			if (value & 0x04) { printf("MC2 ");bit2 |= 0x04; }
+			if (value & 0x02) { printf("MC1 ");bit2 |= 0x02; }
+			if (value & 0x01) { printf("MC0 ");bit2 |= 0x01; }
+			printf("DMA(C) = %d ", bit2);
+			break;
+		case REG_D:
+			printf("  D Register ");
+			break;
+		default:
+			return;
+	}
+	printf("\n        %s ", (registers & REG_D) ? "DP" :
+				(registers & REG_C) ? "CP" :
+				(registers & REG_B) ? "BP" :
+				(registers & REG_A) ? "AP" : "ERROR");
+	for (bit=128;bit>0;bit/=2)
+		printf("%s", (value & bit) ? "1" : "0");
+	printf("\n");
+}
+
+/*
+ * Promise ATA/66 Support: configure Promise ATA66 card in specified mode.
+ */
+int
+pdc202xx_tune_chipset (pci_dev_t dev, int drive, unsigned char speed)
+{
+	unsigned short		drive_conf;
+	int			err = 0;
+	unsigned char			drive_pci, AP, BP, CP, DP;
+	unsigned char			TA = 0, TB = 0;
+
+	switch (drive) {
+		case 0: drive_pci = 0x60; break;
+		case 1: drive_pci = 0x64; break;
+		case 2: drive_pci = 0x68; break;
+		case 3: drive_pci = 0x6c; break;
+		default: return -1;
+	}
+
+	pci_read_config_word(dev, drive_pci, &drive_conf);
+	pci_read_config_byte(dev, (drive_pci), &AP);
+	pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+	pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
+	pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
+
+	if ((AP & 0x0F) || (BP & 0x07)) {
+	  /* clear PIO modes of lower 8421 bits of A Register */
+	  pci_write_config_byte(dev, (drive_pci), AP & ~0x0F);
+	  pci_read_config_byte(dev, (drive_pci), &AP);
+
+	  /* clear PIO modes of lower 421 bits of B Register */
+	  pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07);
+	  pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+
+	  pci_read_config_byte(dev, (drive_pci), &AP);
+	  pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+	}
+
+	pci_read_config_byte(dev, (drive_pci), &AP);
+	pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+	pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
+
+	switch(speed) {
+		case XFER_PIO_4:	TA = 0x01; TB = 0x04; break;
+		case XFER_PIO_3:	TA = 0x02; TB = 0x06; break;
+		case XFER_PIO_2:	TA = 0x03; TB = 0x08; break;
+		case XFER_PIO_1:	TA = 0x05; TB = 0x0C; break;
+		case XFER_PIO_0:
+		default:		TA = 0x09; TB = 0x13; break;
+	}
+
+	pci_write_config_byte(dev, (drive_pci), AP|TA);
+	pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
+
+	pci_read_config_byte(dev, (drive_pci), &AP);
+	pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
+	pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
+	pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
+
+
+#ifdef PDC202XX_DEBUG
+	pdc202xx_decode_registers(REG_A, AP);
+	pdc202xx_decode_registers(REG_B, BP);
+	pdc202xx_decode_registers(REG_C, CP);
+	pdc202xx_decode_registers(REG_D, DP);
+#endif
+	return err;
+}
+/*
+ * Show/Init PCI devices on the specified bus number.
+ */
+
+void pci_mousse_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned int line;
+
+	switch(PCI_DEV(dev)) {
+	case 0x0d:
+		line = 0x00000101;
+		break;
+
+	case 0x0e:
+	default:
+		line = 0x00000303;
+		break;
+	}
+
+	pci_write_config_dword(dev, PCI_INTERRUPT_LINE, line);
+}
+
+void pci_mousse_setup_pdc202xx(struct pci_controller *hose, pci_dev_t dev,
+			       struct pci_config_table *_)
+{
+	unsigned short vendorId;
+	unsigned int mbar0, cmd;
+	int bar, a;
+
+	pci_read_config_word(dev, PCI_VENDOR_ID, &vendorId);
+
+	if(vendorId == PCI_VENDOR_ID_PROMISE || vendorId == PCI_VENDOR_ID_CMD){
+		/* PDC 202xx card is handled differently, it is a bootable
+		 * device and needs all 5 MBAR's configured
+		 */
+		for(bar = 0; bar < 5; bar++){
+			pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
+			pci_write_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, ~0);
+			pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
+#ifdef DEBUG
+			printf("  ATA_bar[%d] = %dbytes\n", bar,
+			       ~(mbar0 & PCI_BASE_ADDRESS_MEM_MASK) + 1);
+#endif
+		}
+
+		/* Program all BAR's */
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PROMISE_MBAR0);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, PROMISE_MBAR1);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_2,	PROMISE_MBAR2);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_3,	PROMISE_MBAR3);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_4,	PROMISE_MBAR4);
+		pci_write_config_dword(dev, PCI_BASE_ADDRESS_5,	PROMISE_MBAR5);
+
+		for(bar = 0; bar < 5; bar++){
+			pci_read_config_dword(dev, PCI_BASE_ADDRESS_0+bar*4, &mbar0);
+#ifdef DEBUG
+			printf("  ATA_bar[%d]@0x%x\n", bar, mbar0);
+#endif
+		}
+
+		/* Enable ROM Expansion base */
+		pci_write_config_dword(dev, PCI_ROM_ADDRESS, PROMISE_MBAR5|1);
+
+		/* Io enable, Memory enable, master enable */
+		pci_read_config_dword(dev, PCI_COMMAND, &cmd);
+		cmd &= ~0xffff0000;
+		cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+		pci_write_config_dword(dev, PCI_COMMAND, cmd);
+
+		/* Breath some life into the controller */
+		for( a = 0; a < 4; a++)
+			pdc202xx_tune_chipset(dev, a, XFER_PIO_0);
+	}
+}
+
+static struct pci_config_table pci_sandpoint_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0e, 0x00,
+	  pci_mousse_setup_pdc202xx },
+#ifndef CONFIG_PCI_PNP
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 0x0d, 0x00,
+	  pci_cfgfunc_config_device, {PCI_ENET_IOADDR,
+				      PCI_ENET_MEMADDR,
+				      PCI_COMMAND_MEMORY |
+				      PCI_COMMAND_MASTER}},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, {PCI_SLOT_IOADDR,
+				      PCI_SLOT_MEMADDR,
+				      PCI_COMMAND_MEMORY |
+				      PCI_COMMAND_MASTER}},
+#endif
+	{ }
+};
+
+struct pci_controller hose = {
+	config_table: pci_sandpoint_config_table,
+	fixup_irq: pci_mousse_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds
new file mode 100755
index 0000000..57358b8
--- /dev/null
+++ b/board/mousse/u-boot.lds
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram
new file mode 100755
index 0000000..eb47ae6
--- /dev/null
+++ b/board/mousse/u-boot.lds.ram
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems Ltd. robt@flyingpig.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+
+MEMORY {
+ 	ram  (!rx) : org = 0x00000000 , LENGTH = 8M
+ 	code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000)
+ 	rom   (rx) : org = 0xfff00000 , LENGTH = 512K
+}
+
+SECTIONS
+{
+  _f_init = .;
+  PROVIDE(_f_init = .);
+  _f_init_rom = .;
+  PROVIDE(_f_init_rom = .);
+
+  .init : {
+      cpu/mpc824x/start.o	(.text)
+      *(.init)
+  } > ram
+  _init_size = SIZEOF(.init);
+  PROVIDE(_init_size = SIZEOF(.init));
+
+  ENTRY(_start)
+
+/*  _ftext = .;
+  _ftext_rom = .;
+  _text_size = SIZEOF(.text);
+ */
+  .text : {
+      *(.text)
+      *(.got1)
+      } > ram
+  .rodata : { *(.rodata) } > ram
+  .dtors : { *(.dtors) } > ram
+  .data : { *(.data) } > ram
+  .sdata : { *(.sdata) } > ram
+  .sdata2 : { *(.sdata2)
+      *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+    } > ram
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .sbss : { *(.sbss) } > ram
+  .sbss2 : { *(.sbss2) } > ram
+  .bss : { *(.bss) } > ram
+  .debug : { *(.debug) } > ram
+  .line : { *(.line) } > ram
+  .symtab : { *(.symtab) } > ram
+  .shrstrtab : { *(.shstrtab) } > ram
+  .strtab : { *(.strtab) } > ram
+ /* .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  } > ram
+  */
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+   __start___ex_table = .;
+    __ex_table : { *(__ex_table) } > ram
+    __stop___ex_table = .;
+
+
+  .ppcenv	:
+  {
+    common/environment.o (.ppcenv)
+  } > ram
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom
new file mode 100755
index 0000000..5a5722e
--- /dev/null
+++ b/board/mousse/u-boot.lds.rom
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+	 common/board.o (.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+		. = env_offset;
+    common/environment.o (.text)
+
+		*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mp2usb/Makefile b/board/mp2usb/Makefile
new file mode 100755
index 0000000..b6ea3cf
--- /dev/null
+++ b/board/mp2usb/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= mp2usb.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mp2usb/config.mk b/board/mp2usb/config.mk
new file mode 100755
index 0000000..e299bfd
--- /dev/null
+++ b/board/mp2usb/config.mk
@@ -0,0 +1,3 @@
+TEXT_BASE = 0x27F00000
+## For testing: load at 0x20100000 and "go" at 0x201000A4
+#TEXT_BASE = 0x20100000
diff --git a/board/mp2usb/flash.c b/board/mp2usb/flash.c
new file mode 100755
index 0000000..89ced16
--- /dev/null
+++ b/board/mp2usb/flash.c
@@ -0,0 +1,552 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define CFG_MAX_FLASH_BANKS	1
+#define PHYS_FLASH_SECT_SIZE	0x00020000 /* 128 KB sectors (x1) */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#define SWAP(x)			__swab16(x)
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM	0x00100010
+#define INTEL_ERASE	0x00200020
+#define INTEL_PROG	0x00400040
+#define INTEL_CLEAR	0x00500050
+#define INTEL_LOCKBIT	0x00600060
+#define INTEL_PROTECT	0x00010001
+#define INTEL_STATUS	0x00700070
+#define INTEL_READID	0x00900090
+#define INTEL_SUSPEND	0x00B000B0
+#define INTEL_CONFIRM	0x00D000D0
+#define INTEL_RESET	0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED	0x00800080
+#define INTEL_OK	0x00800080
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) INTEL_RESET;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) INTEL_RESET;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+	int cflag, iflag;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	/* Disable interrupts which might cause a timeout here */
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) INTEL_CLEAR;	/* clear status register */
+			*addr = (FPW) INTEL_ERASE;	/* erase setup */
+			*addr = (FPW) INTEL_CONFIRM;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) INTEL_SUSPEND;	/* suspend erase     */
+					*addr = (FPW) INTEL_RESET;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPWV)INTEL_CLEAR;	/* clear status register cmd.   */
+			*addr = (FPWV)INTEL_RESET;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	/* get lower word aligned address */
+	wp = (addr & ~1);
+	port_width = 2;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int cflag, iflag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	/* Disable interrupts which might cause a timeout here */
+	iflag = disable_interrupts ();
+
+	*addr = (FPW) INTEL_PROG;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) INTEL_RESET;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) INTEL_RESET;	/* restore read mode */
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int i;
+	int rc = 0;
+	FPWV *addr = (FPWV *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = (FPW) INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = (FPW) INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = (FPW) INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = (FPW) INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = (FPW) INTEL_CONFIRM;	/* clear */
+	}
+
+	reset_timer_masked ();
+
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != (FPW) INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+	{
+		for (i = 0; i < info->sector_count; i++)
+		{
+			if (info->protect[i])
+			{
+				reset_timer_masked ();
+				addr = (FPWV *) (info->start[i]);
+				*addr = (FPW) INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = (FPW) INTEL_PROTECT;	/* set */
+				while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED)
+				{
+					if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT)
+					{
+						printf("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = (FPW) INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/board/mp2usb/mp2usb.c b/board/mp2usb/mp2usb.c
new file mode 100755
index 0000000..e75be1e
--- /dev/null
+++ b/board/mp2usb/mp2usb.c
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+#include <dm9161.h>
+#include <asm/mach-types.h>
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Enable Ctrlc */
+	console_init_f ();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of MP2USB-Board. */
+	gd->bd->bi_arch_number = MACH_TYPE_MP2USB;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	at91rm9200_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif	/* CONFIG_DRIVER_ETHER */
diff --git a/board/mp2usb/u-boot.lds b/board/mp2usb/u-boot.lds
new file mode 100755
index 0000000..76df6b2
--- /dev/null
+++ b/board/mp2usb/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mpc8260ads/Makefile b/board/mpc8260ads/Makefile
new file mode 100755
index 0000000..cc519d1
--- /dev/null
+++ b/board/mpc8260ads/Makefile
@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8260ads/config.mk b/board/mpc8260ads/config.mk
new file mode 100755
index 0000000..eb6f7c9
--- /dev/null
+++ b/board/mpc8260ads/config.mk
@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2001-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+endif
diff --git a/board/mpc8260ads/flash.c b/board/mpc8260ads/flash.c
new file mode 100755
index 0000000..59997aa
--- /dev/null
+++ b/board/mpc8260ads/flash.c
@@ -0,0 +1,492 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * (C) Copyright 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Re-written to support multi-bank flash SIMMs.
+ * Added support for real protection and JFFS2.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT  0x89898989
+#define INTEL_ALT     0xB0B0B0B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x10101010
+#define INTEL_ERASE   0x20202020
+#define INTEL_CLEAR   0x50505050
+#define INTEL_LOCKBIT 0x60606060
+#define INTEL_PROTECT 0x01010101
+#define INTEL_STATUS  0x70707070
+#define INTEL_READID  0x90909090
+#define INTEL_CONFIRM 0xD0D0D0D0
+#define INTEL_RESET   0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x80808080
+#define INTEL_OK       0x80808080
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
+ * Up to 32MB of flash supported (up to 4 banks.)
+ * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
+ *
+ * The following code can not run from flash!
+ */
+unsigned long flash_init (void)
+{
+	ulong size = 0, sect_start, sect_size = 0, bank_size;
+	ushort sect_count = 0;
+	int i, j, nbanks;
+	vu_long *addr = (vu_long *)CFG_FLASH_BASE;
+	vu_long *bcsr = (vu_long *)CFG_BCSR;
+
+	switch (bcsr[2] & 0xF) {
+	case 0:
+		nbanks = 4;
+		break;
+	case 1:
+		nbanks = 2;
+		break;
+	case 2:
+		nbanks = 1;
+		break;
+	default:		/* Unsupported configurations */
+		nbanks = CFG_MAX_FLASH_BANKS;
+	}
+
+	if (nbanks > CFG_MAX_FLASH_BANKS)
+		nbanks = CFG_MAX_FLASH_BANKS;
+
+	for (i = 0; i < nbanks; i++) {
+		*addr = INTEL_READID;	/* Read Intelligent Identifier */
+		if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
+			switch (addr[1]) {
+			case SHARP_ID_28F016SCL:
+			case SHARP_ID_28F016SCZ:
+				flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+				sect_count = 32;
+				sect_size = 0x40000;
+				break;
+			default:
+				flash_info[i].flash_id = FLASH_UNKNOWN;
+				sect_count = CFG_MAX_FLASH_SECT;
+				sect_size =
+				   CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
+			}
+		}
+		else
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
+			       addr[0], addr[1], (ulong)addr);
+			size = 0;
+			*addr = INTEL_RESET; /* Reset bank to Read Array mode */
+			break;
+		}
+		flash_info[i].sector_count = sect_count;
+		flash_info[i].size = bank_size = sect_size * sect_count;
+		size += bank_size;
+		sect_start = (ulong)addr;
+		for (j = 0; j < sect_count; j++) {
+			addr = (vu_long *)sect_start;
+			flash_info[i].start[j]   = sect_start;
+			flash_info[i].protect[j] = (addr[2] == 0x01010101);
+			sect_start += sect_size;
+		}
+		*addr = INTEL_RESET; /* Reset bank to Read Array mode */
+		addr = (vu_long *)sect_start;
+	}
+
+	if (size == 0) {	/* Unknown flash, fill with hard-coded values */
+		sect_start = CFG_FLASH_BASE;
+		for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
+			flash_info[i].sector_count = sect_count;
+			for (j = 0; j < sect_count; j++) {
+				flash_info[i].start[j]   = sect_start;
+				flash_info[i].protect[j] = 0;
+				sect_start += sect_size;
+			}
+		}
+		size = CFG_FLASH_SIZE;
+	}
+	else
+		for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			flash_info[i].size = 0;
+			flash_info[i].sector_count = 0;
+		}
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Clear Status Register */
+			*addr = INTEL_CLEAR;
+			/* Single Block Erase Command */
+			*addr = INTEL_ERASE;
+			/* Confirm */
+			*addr = INTEL_CONFIRM;
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = INTEL_CONFIRM;
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = INTEL_RESET;	/* reset bank */
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			if (*addr != INTEL_OK) {
+				printf("Block erase failed at %08X, CSR=%08X\n",
+				       (uint)addr, (uint)*addr);
+				*addr = INTEL_RESET;	/* reset bank */
+				return 1;
+			}
+
+			/* reset to read mode */
+			*addr = INTEL_RESET;
+		}
+	}
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	ulong start;
+	int rc = 0;
+	int flag;
+	vu_long *addr = (vu_long *)dest;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+
+	*addr = INTEL_CLEAR; /* Clear status register */
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = INTEL_PROGRAM;
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			printf("Write timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+	if (*addr != INTEL_OK) {
+		printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	*addr = INTEL_RESET; /* Reset to read array mode */
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	*(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	rc = write_word(info, wp, data);
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	ulong start;
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
+	}
+
+	start = get_timer(0);
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+		for (i = 0; i < info->sector_count; i++)
+			if (info->protect[i]) {
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				udelay(CFG_FLASH_LOCK_TOUT * 1000);
+			}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c
new file mode 100755
index 0000000..93550e2
--- /dev/null
+++ b/board/mpc8260ads/mpc8260ads.c
@@ -0,0 +1,546 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified during 2001 by
+ * Advanced Communications Technologies (Australia) Pty. Ltd.
+ * Howard Walker, Tuong Vu-Dinh
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Added support for the 16M dram simm on the 8260ads boards
+ *
+ * (C) Copyright 2003-2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
+	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
+	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
+	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
+	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
+	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
+	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
+	/* PA9  */ { 0,          0,   0,   0,   0,   0 }, /* PA9 */
+	/* PA8  */ { 0,          0,   0,   0,   0,   0 }, /* PA8 */
+	/* PA7  */ { 0,          0,   0,   1,   0,   0 }, /* PA7 */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
+	/* PA5  */ { 0,          0,   0,   1,   0,   0 }, /* PA5 */
+	/* PA4  */ { 0,          0,   0,   1,   0,   0 }, /* PA4 */
+	/* PA3  */ { 0,          0,   0,   1,   0,   0 }, /* PA3 */
+	/* PA2  */ { 0,          0,   0,   1,   0,   0 }, /* PA2 */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
+	/* PA0  */ { 0,          0,   0,   1,   0,   0 }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER */
+	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV */
+	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN */
+	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER */
+	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL */
+	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS */
+	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV */
+	/* PB16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR */
+	/* PB15 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR */
+	/* PB14 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN */
+	/* PB13 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL */
+	/* PB12 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS */
+	/* PB11 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB10 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB9  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB8  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB7  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB6  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB5  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB4  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
+	/* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Tx Clock (CLK10) */
+	/* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Rx Clock (CLK11) */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
+#if CONFIG_ADSTYPE == CFG_8272ADS
+	/* PC19 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
+	/* PC18 */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
+	/* PC17 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK15) */
+	/* PC16 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK16) */
+#else
+	/* PC19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK13) */
+	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK14) */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16 */
+#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
+#if CONFIG_ADSTYPE == CFG_8272ADS
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
+	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
+#else
+	/* PC10 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
+	/* PC9  */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
+#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8 */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7 */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6 */
+	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5 */
+	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4 */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3 */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2 */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1 */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
+	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* PD29 */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+void reset_phy (void)
+{
+	vu_long *bcsr = (vu_long *)CFG_BCSR;
+
+	/* Reset the PHY */
+#if CFG_PHY_ADDR == 0
+	bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
+	udelay(2);
+	bcsr[1] |=  FETH1_RST;
+#else
+	bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
+	udelay(2);
+	bcsr[3] |=  FETH2_RST;
+#endif /* CFG_PHY_ADDR == 0 */
+	udelay(1000);
+#ifdef CONFIG_MII
+#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+	/*
+	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
+	 * Enable autonegotiation.
+	 */
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#else
+	/*
+	 * Ethernet PHY is configured (by means of configuration pins)
+	 * to work at 10Mb/s only. We reconfigure it using MII
+	 * to advertise all capabilities, including 100Mb/s, and
+	 * restart autonegotiation.
+	 */
+
+	/* Advertise all capabilities */
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
+
+	/* Do not bypass Rx/Tx (de)scrambler */
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR,  0x0000);
+
+	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+#endif /* CONFIG_MII */
+}
+
+#ifdef CONFIG_PCI
+typedef struct pci_ic_s {
+	unsigned long pci_int_stat;
+	unsigned long pci_int_mask;
+}pci_ic_t;
+#endif
+
+int board_early_init_f (void)
+{
+	vu_long *bcsr = (vu_long *)CFG_BCSR;
+
+#ifdef CONFIG_PCI
+	volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
+
+	/* mask alll the PCI interrupts */
+	pci_ic->pci_int_mask |= 0xfff00000;
+#endif
+#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
+	bcsr[1] &= ~RS232EN_1;
+#endif
+#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
+	bcsr[1] &= ~RS232EN_2;
+#endif
+
+#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+	if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+	{
+		volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+		immap->im_siu_conf.sc_siumcr =
+			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
+			| SIUMCR_LBPC01;
+	}
+#endif /* CONFIG_ADSTYPE != CFG_8260ADS */
+
+	return 0;
+}
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+#if   CONFIG_ADSTYPE == CFG_PQ2FADS
+	long int msize = 32;
+#elif CONFIG_ADSTYPE == CFG_8272ADS
+	long int msize = 64;
+#else
+	long int msize = 16;
+#endif
+
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar *ramaddr, c = 0xff;
+	uint or;
+	uint psdmr;
+	uint psrt;
+
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x00000002;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+#ifdef CFG_LSDRAM_BASE
+	/*
+	  Initialise local bus SDRAM only if the pins
+	  are configured as local bus pins and not as PCI.
+	  The configuration is determined by the HRCW.
+	*/
+	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
+		memctl->memc_lsrt  = CFG_LSRT;
+#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
+		memctl->memc_or3   = 0xFF803280;
+		memctl->memc_br3   = CFG_LSDRAM_BASE | 0x00001861;
+#else  				  /* CS4 */
+		memctl->memc_or4   = 0xFFC01480;
+		memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+		memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
+		ramaddr = (uchar *) CFG_LSDRAM_BASE;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
+		for (i = 0; i < 8; i++)
+			*ramaddr = c;
+		memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
+	}
+#endif /* CFG_LSDRAM_BASE */
+
+	/* Init 60x bus SDRAM */
+#ifdef CONFIG_SPD_EEPROM
+	{
+		spd_eeprom_t spd;
+		uint pbi, bsel, rowst, lsb, tmp;
+
+		i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
+
+		/* Bank-based interleaving is not supported for physical bank
+		   sizes greater than 128MB which is encoded as 0x20 in SPD
+		 */
+		pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
+		msize = spd.nrows * (4 * spd.row_dens);	/* Mixed size not supported */
+		or = ~(msize - 1) << 20;	/* SDAM */
+		switch (spd.nbanks) {	/* BPD */
+		case 2:
+			bsel = 1;
+			break;
+		case 4:
+			bsel = 2;
+			or |= 0x00002000;
+			break;
+		case 8:
+			bsel = 3;
+			or |= 0x00004000;
+			break;
+		}
+		lsb = 3;	/* For 64-bit port, lsb is 3 bits */
+
+		if (pbi) {	/* Bus partition depends on interleaving */
+			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
+			or |= (rowst << 9);	/* ROWST */
+		} else {
+			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
+			or |= ((rowst * 2 - 12) << 9);	/* ROWST */
+		}
+		or |= ((spd.nrow_addr - 9) << 6);	/* NUMR */
+
+		psdmr = (pbi << 31);	/* PBI */
+		/* Bus multiplexing parameters */
+		tmp = 32 - (lsb + spd.nrow_addr);	/* Tables 10-19 and 10-20 */
+		psdmr |= ((tmp - (rowst - 5) - 13) << 24);	/* SDAM */
+		psdmr |= ((tmp - 3 - 12) << 21);	/* BSMA */
+
+		tmp = (31 - lsb - 10) - tmp;
+		/* Pin connected to SDA10 is (31 - lsb - 10).
+		   rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
+		   so (rowst + tmp) alternates with AP.
+		 */
+		if (pbi)				/* Table 10-7 */
+			psdmr |= ((10 - (rowst + tmp)) << 18);	/* SDA10 */
+		else
+			psdmr |= ((12 - (rowst + tmp)) << 18);	/* SDA10 */
+
+		/* SDRAM device-specific parameters */
+		tmp = ns2clk (70);	/* Refresh recovery is not in SPD, so assume 70ns */
+		switch (tmp) {		/* RFRC */
+		case 1:
+		case 2:
+			psdmr |= (1 << 15);
+			break;
+		case 3:
+		case 4:
+		case 5:
+		case 6:
+		case 7:
+		case 8:
+			psdmr |= ((tmp - 2) << 15);
+			break;
+		default:
+			psdmr |= (7 << 15);
+		}
+		psdmr |= (ns2clk (spd.trp) % 8 << 12);	/* PRETOACT */
+		psdmr |= (ns2clk (spd.trcd) % 8 << 9);	/* ACTTORW */
+		/* BL=0 because for 64-bit SDRAM burst length must be 4 */
+		/* LDOTOPRE ??? */
+		for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
+			tmp >>= 1;
+		switch (i) {			/* WRC */
+		case 0:
+		case 1:
+			psdmr |= (1 << 4);
+			break;
+		case 2:
+		case 3:
+			psdmr |= (i << 4);
+			break;
+		}
+		/* EAMUX=0 - no external address multiplexing */
+		/* BUFCMD=0 - no external buffers */
+		for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
+			tmp >>= 1;
+		psdmr |= i;				/* CL */
+
+		switch (spd.refresh & 0x7F) {
+		case 1:
+			tmp = 3900;
+			break;
+		case 2:
+			tmp = 7800;
+			break;
+		case 3:
+			tmp = 31300;
+			break;
+		case 4:
+			tmp = 62500;
+			break;
+		case 5:
+			tmp = 125000;
+			break;
+		default:
+			tmp = 15625;
+		}
+		psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
+				  ((memctl->memc_mptpr >> 8) + 1)) - 1;
+#ifdef SPD_DEBUG
+		printf ("\nDIMM type:       %-18.18s\n", spd.mpart);
+		printf ("SPD size:        %d\n", spd.info_size);
+		printf ("EEPROM size:     %d\n", 1 << spd.chip_size);
+		printf ("Memory type:     %d\n", spd.mem_type);
+		printf ("Row addr:        %d\n", spd.nrow_addr);
+		printf ("Column addr:     %d\n", spd.ncol_addr);
+		printf ("# of rows:       %d\n", spd.nrows);
+		printf ("Row density:     %d\n", spd.row_dens);
+		printf ("# of banks:      %d\n", spd.nbanks);
+		printf ("Data width:      %d\n",
+				256 * spd.dataw_msb + spd.dataw_lsb);
+		printf ("Chip width:      %d\n", spd.primw);
+		printf ("Refresh rate:    %02X\n", spd.refresh);
+		printf ("CAS latencies:   %02X\n", spd.cas_lat);
+		printf ("Write latencies: %02X\n", spd.write_lat);
+		printf ("tRP:             %d\n", spd.trp);
+		printf ("tRCD:            %d\n", spd.trcd);
+
+		printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
+#endif /* SPD_DEBUG */
+	}
+#else  /* !CONFIG_SPD_EEPROM */
+	or    = CFG_OR2;
+	psdmr = CFG_PSDMR;
+	psrt  = CFG_PSRT;
+#endif /* CONFIG_SPD_EEPROM */
+	memctl->memc_psrt = psrt;
+	memctl->memc_or2 = or;
+	memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
+	ramaddr = (uchar *) CFG_SDRAM_BASE;
+	memctl->memc_psdmr = psdmr | 0x28000000;	/* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | 0x08000000;	/* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | 0x18000000;	/* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | 0x40000000;	/* Refresh enable */
+	*ramaddr = c;
+#endif /* CFG_RAMBOOT */
+
+	/* return total 60x bus SDRAM size */
+	return (msize * 1024 * 1024);
+}
+
+int checkboard (void)
+{
+#if   CONFIG_ADSTYPE == CFG_8260ADS
+	puts ("Board: Motorola MPC8260ADS\n");
+#elif CONFIG_ADSTYPE == CFG_8266ADS
+	puts ("Board: Motorola MPC8266ADS\n");
+#elif CONFIG_ADSTYPE == CFG_PQ2FADS
+	puts ("Board: Motorola PQ2FADS-ZU\n");
+#elif CONFIG_ADSTYPE == CFG_8272ADS
+	puts ("Board: Motorola MPC8272ADS\n");
+#else
+	puts ("Board: unknown\n");
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/board/mpc8260ads/u-boot.lds b/board/mpc8260ads/u-boot.lds
new file mode 100755
index 0000000..bf8048d
--- /dev/null
+++ b/board/mpc8260ads/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/mpc8266ads/Makefile b/board/mpc8266ads/Makefile
new file mode 100755
index 0000000..cd0f40b
--- /dev/null
+++ b/board/mpc8266ads/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8266ads/config.mk b/board/mpc8266ads/config.mk
new file mode 100755
index 0000000..ecc2a7d
--- /dev/null
+++ b/board/mpc8266ads/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8260ads board
+#
+
+TEXT_BASE = 0xfe000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/mpc8266ads/flash.c b/board/mpc8266ads/flash.c
new file mode 100755
index 0000000..9512c72
--- /dev/null
+++ b/board/mpc8266ads/flash.c
@@ -0,0 +1,509 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#ifndef CONFIG_MPC8266ADS
+	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t	*memctl = &immap->im_memctl;
+	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
+#endif
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+#ifndef CONFIG_MPC8266ADS
+	bcsr->bd_ctrl |= BD_CTRL_FLWE;
+#endif
+
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+#ifndef CONFIG_MPC8266ADS
+	/* Remap FLASH according to real size */
+	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
+				(memctl->memc_br1 & ~(BR_BA_MSK));
+#endif
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+
+	value = addr[0] & 0x00FF00FF;
+	switch (value) {
+	case MT_MANUFACT:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case (INTEL_ID_28F016S):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F160S3):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F320S3):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		sector_offset = 0x20000;
+		break;				/* => 2x4 MB		*/
+
+	case SHARP_ID_28F016SCL:
+	case SHARP_ID_28F016SCZ:
+		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+		info->sector_count  = 32;
+		info->size          = 0x00800000;
+		sector_offset = 0x40000;
+		break;				/* => 4x2 MB		*/
+
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Reset Array */
+			*addr = 0xffffffff;
+			/* Clear Status Register */
+			*addr = 0x50505050;
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = 0xD0D0D0D0;
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+			while ((*addr & 0x80808080) != 0x80808080) {
+				if(*addr & 0x20202020){
+					printf("Error in Block Erase - Lock Bit may be set!\n");
+					printf("Status Register = 0x%X\n", (uint)*addr);
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					return 1;
+				}
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+		}
+	}
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+	while (((csr = *addr) & 0x80808080) != 0x80808080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x40404040) {
+		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long  * addr)
+{
+	ulong start, now;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	/* Clear Status Register */
+	*addr = 0x50505050;
+
+	*addr = 0x60606060;
+	*addr = 0xd0d0d0d0;
+
+	start = get_timer (0);
+	while(*addr != 0x80808080){
+		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			return 1;
+		}
+	}
+	return 0;
+}
diff --git a/board/mpc8266ads/mpc8266ads.c b/board/mpc8266ads/mpc8266ads.c
new file mode 100755
index 0000000..8f7273c
--- /dev/null
+++ b/board/mpc8266ads/mpc8266ads.c
@@ -0,0 +1,586 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified during 2001 by
+ * Advanced Communications Technologies (Australia) Pty. Ltd.
+ * Howard Walker, Tuong Vu-Dinh
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Added support for the 16M dram simm on the 8260ads boards
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <i2c.h>
+#include <mpc8260.h>
+#include <pci.h>
+
+/*
+ * PBI Page Based Interleaving
+ *   PSDMR_PBI page based interleaving
+ *   0         bank based interleaving
+ * External Address Multiplexing (EAMUX) adds a clock to address cycles
+ *   (this can help with marginal board layouts)
+ *   PSDMR_EAMUX  adds a clock
+ *   0            no extra clock
+ * Buffer Command (BUFCMD) adds a clock to command cycles.
+ *   PSDMR_BUFCMD adds a clock
+ *   0            no extra clock
+ */
+#define CONFIG_PBI		0
+#define PESSIMISTIC_SDRAM	0
+#define EAMUX			0	/* EST requires EAMUX */
+#define BUFCMD			0
+
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* LXT970 FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* LXT970 FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+typedef struct bscr_ {
+	unsigned long bcsr0;
+	unsigned long bcsr1;
+	unsigned long bcsr2;
+	unsigned long bcsr3;
+	unsigned long bcsr4;
+	unsigned long bcsr5;
+	unsigned long bcsr6;
+	unsigned long bcsr7;
+} bcsr_t;
+
+typedef struct pci_ic_s {
+	unsigned long pci_int_stat;
+	unsigned long pci_int_mask;
+} pci_ic_t;
+
+void reset_phy(void)
+{
+    volatile bcsr_t  *bcsr           = (bcsr_t *)CFG_BCSR;
+
+    /* reset the FEC port */
+    bcsr->bcsr1                    &= ~FETH_RST;
+    bcsr->bcsr1                    |= FETH_RST;
+}
+
+
+int board_early_init_f (void)
+{
+    volatile bcsr_t  *bcsr         = (bcsr_t *)CFG_BCSR;
+    volatile pci_ic_t *pci_ic      = (pci_ic_t *) CFG_PCI_INT;
+
+    bcsr->bcsr1                    = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
+
+    /* mask all PCI interrupts */
+    pci_ic->pci_int_mask |= 0xfff00000;
+
+    return 0;
+}
+
+int checkboard(void)
+{
+    puts ("Board: Motorola MPC8266ADS\n");
+    return 0;
+}
+
+long int initdram(int board_type)
+{
+	/* Autoinit part stolen from board/sacsng/sacsng.c */
+    volatile immap_t *immap         = (immap_t *)CFG_IMMR;
+    volatile memctl8260_t *memctl   = &immap->im_memctl;
+    volatile uchar c = 0xff;
+    volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
+    uint  psdmr = CFG_PSDMR;
+    int i;
+
+    uint   psrt = 0x21;					/* for no SPD */
+    uint   chipselects = 1;				/* for no SPD */
+    uint   sdram_size = CFG_SDRAM_SIZE * 1024 * 1024;	/* for no SPD */
+    uint   or = CFG_OR2_PRELIM;				/* for no SPD */
+    uint   data_width;
+    uint   rows;
+    uint   banks;
+    uint   cols;
+    uint   caslatency;
+    uint   width;
+    uint   rowst;
+    uint   sdam;
+    uint   bsma;
+    uint   sda10;
+    u_char spd_size;
+    u_char data;
+    u_char cksum;
+    int    j;
+
+    /* Keep the compiler from complaining about potentially uninitialized vars */
+    data_width = rows = banks = cols = caslatency = 0;
+
+    /*
+     * Read the SDRAM SPD EEPROM via I2C.
+     */
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+    i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
+    spd_size = data;
+    cksum    = data;
+    for(j = 1; j < 64; j++)
+	{	/* read only the checksummed bytes */
+	/* note: the I2C address autoincrements when alen == 0 */
+		i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
+		/*printf("addr %d = 0x%02x\n", j, data);*/
+		if(j ==  5) chipselects = data & 0x0F;
+		else if(j ==  6) data_width  = data;
+		else if(j ==  7) data_width |= data << 8;
+		else if(j ==  3) rows        = data & 0x0F;
+		else if(j ==  4) cols        = data & 0x0F;
+		else if(j == 12)
+		{
+			/*
+				 * Refresh rate: this assumes the prescaler is set to
+			 * approximately 0.39uSec per tick and the target refresh period
+			 * is about 85% of maximum.
+			 */
+			switch(data & 0x7F)
+			{
+					default:
+					case 0:  psrt = 0x21; /*  15.625uS */  break;
+					case 1:  psrt = 0x07; /*   3.9uS   */  break;
+					case 2:  psrt = 0x0F; /*   7.8uS   */  break;
+					case 3:  psrt = 0x43; /*  31.3uS   */  break;
+					case 4:  psrt = 0x87; /*  62.5uS   */  break;
+					case 5:  psrt = 0xFF; /* 125uS     */  break;
+			}
+		}
+		else if(j == 17) banks       = data;
+		else if(j == 18)
+		{
+			caslatency = 3; /* default CL */
+#		    if(PESSIMISTIC_SDRAM)
+				if((data & 0x04) != 0) caslatency = 3;
+				else if((data & 0x02) != 0) caslatency = 2;
+				else if((data & 0x01) != 0) caslatency = 1;
+#			else
+				if((data & 0x01) != 0) caslatency = 1;
+				else if((data & 0x02) != 0) caslatency = 2;
+				else if((data & 0x04) != 0) caslatency = 3;
+#			endif
+			else
+			{
+			printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
+					data);
+			}
+		}
+		else if(j == 63)
+		{
+			if(data != cksum)
+			{
+				printf ("WARNING: Configuration data checksum failure:"
+					" is 0x%02x, calculated 0x%02x\n",
+				data, cksum);
+			}
+		}
+		cksum += data;
+    }
+
+    /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
+    if(caslatency < 2) {
+		printf("CL was %d, forcing to 2\n", caslatency);
+		caslatency = 2;
+    }
+    if(rows > 14) {
+		printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
+		rows = 14;
+    }
+    if(cols > 11) {
+		printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
+		cols = 11;
+    }
+
+    if((data_width != 64) && (data_width != 72))
+    {
+		printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
+			data_width);
+    }
+    width = 3;		/* 2^3 = 8 bytes = 64 bits wide */
+    /*
+     * Convert banks into log2(banks)
+     */
+    if     (banks == 2)	banks = 1;
+    else if(banks == 4)	banks = 2;
+    else if(banks == 8)	banks = 3;
+
+
+    sdram_size = 1 << (rows + cols + banks + width);
+    /* hack for high density memory (512MB per CS) */
+    /* !!!!! Will ONLY work with Page Based Interleave !!!!!
+	     ( PSDMR[PBI] = 1 )
+    */
+    /* mamory actually has 11 column addresses, but the memory controller
+       doesn't really care.
+       the calculations that follow will however move the rows so that
+       they are muxed one bit off if you use 11 bit columns.
+       The solution is to tell the memory controller the correct size of the memory
+       but change the number of columns to 10 afterwards.
+       The 11th column addre will still be mucxed correctly onto the bus.
+
+       Also be aware that the MPC8266ADS board Rev B has not connected
+       Row addres 13 to anything.
+
+       The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
+    */
+    if (cols > 10)
+	    cols = 10;
+
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    rowst = ((32 - 6) - (rows + cols + width)) * 2;
+#else
+    rowst = 32 - (rows + banks + cols + width);
+#endif
+
+   or = ~(sdram_size - 1)    |	/* SDAM address mask	*/
+	  ((banks-1) << 13)   |	/* banks per device	*/
+	  (rowst << 9)        |	/* rowst		*/
+	  ((rows - 9) << 6);	/* numr			*/
+
+
+    /*printf("memctl->memc_or2 = 0x%08x\n", or);*/
+
+    /*
+     * SDAM specifies the number of columns that are multiplexed
+     * (reference AN2165/D), defined to be (columns - 6) for page
+     * interleave, (columns - 8) for bank interleave.
+     *
+     * BSMA is 14 - max(rows, cols).  The bank select lines come
+     * into play above the highest "address" line going into the
+     * the SDRAM.
+     */
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    sdam = cols - 8;
+    bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+    sda10 = sdam + 2;
+#else
+    sdam = cols + banks - 8;
+    bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+    sda10 = sdam;
+#endif
+#if(PESSIMISTIC_SDRAM)
+    psdmr = (CONFIG_PBI              |\
+	     PSDMR_RFEN              |\
+	     PSDMR_RFRC_16_CLK       |\
+	     PSDMR_PRETOACT_8W       |\
+	     PSDMR_ACTTORW_8W        |\
+	     PSDMR_WRC_4C            |\
+	     PSDMR_EAMUX             |\
+	     PSDMR_BUFCMD)           |\
+	     caslatency              |\
+	     ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */ \
+	     (sdam << 24)            |\
+	     (bsma << 21)            |\
+	     (sda10 << 18);
+#else
+    psdmr = (CONFIG_PBI              |\
+	     PSDMR_RFEN              |\
+	     PSDMR_RFRC_7_CLK        |\
+	     PSDMR_PRETOACT_3W       |	/* 1 for 7E parts (fast PC-133) */ \
+	     PSDMR_ACTTORW_2W        |	/* 1 for 7E parts (fast PC-133) */ \
+	     PSDMR_WRC_1C            |	/* 1 clock + 7nSec */
+	     EAMUX                   |\
+	     BUFCMD)                 |\
+	     caslatency              |\
+	     ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */ \
+	     (sdam << 24)            |\
+	     (bsma << 21)            |\
+	     (sda10 << 18);
+#endif
+	/*printf("psdmr = 0x%08x\n", psdmr);*/
+
+    /*
+     * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+     *
+     * "At system reset, initialization software must set up the
+     *  programmable parameters in the memory controller banks registers
+     *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+     *  system software should execute the following initialization sequence
+     *  for each SDRAM device.
+     *
+     *  1. Issue a PRECHARGE-ALL-BANKS command
+     *  2. Issue eight CBR REFRESH commands
+     *  3. Issue a MODE-SET command to initialize the mode register
+     *
+     * Quote from Micron MT48LC8M16A2 data sheet:
+     *
+     *  "...the SDRAM requires a 100uS delay prior to issuing any
+     *  command other than a COMMAND INHIBIT or NOP.  Starting at some
+     *  point during this 100uS period and continuing at least through
+     *  the end of this period, COMMAND INHIBIT or NOP commands should
+     *  be applied."
+     *
+     *  "Once the 100uS delay has been satisfied with at least one COMMAND
+     *  INHIBIT or NOP command having been applied, a /PRECHARGE command/
+     *  should be applied.  All banks must then be precharged, thereby
+     *  placing the device in the all banks idle state."
+     *
+     *  "Once in the idle state, /two/ AUTO REFRESH cycles must be
+     *  performed.  After the AUTO REFRESH cycles are complete, the
+     *  SDRAM is ready for mode register programming."
+     *
+     *  (/emphasis/ mine, gvb)
+     *
+     *  The way I interpret this, Micron start up sequence is:
+     *  1. Issue a PRECHARGE-BANK command (initial precharge)
+     *  2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
+     *  3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
+     *  4. Issue a MODE-SET command to initialize the mode register
+     *
+     *  --------
+     *
+     *  The initial commands are executed by setting P/LSDMR[OP] and
+     *  accessing the SDRAM with a single-byte transaction."
+     *
+     * The appropriate BRx/ORx registers have already been set when we
+     * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+     */
+
+    memctl->memc_mptpr = CFG_MPTPR;
+    memctl->memc_psrt  = psrt;
+
+    memctl->memc_br2 = CFG_BR2_PRELIM;
+    memctl->memc_or2 = or;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+    for (i = 0; i < 8; i++)
+	*ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+    *ramaddr = c;
+
+    /*
+     * Do it a second time for the second set of chips if the DIMM has
+     * two chip selects (double sided).
+     */
+    if(chipselects > 1)
+	{
+	ramaddr += sdram_size;
+
+		memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
+		memctl->memc_or3 = or;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+		*ramaddr = c;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+		for (i = 0; i < 8; i++)
+			*ramaddr = c;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+		*ramaddr = c;
+
+		memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+		*ramaddr = c;
+    }
+
+	/* print info */
+	printf("SDRAM configuration read from SPD\n");
+	printf("\tSize per side = %dMB\n", sdram_size >> 20);
+	printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
+	printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    printf(", Using Bank Based Interleave\n");
+#else
+    printf(", Using Page Based Interleave\n");
+#endif
+	printf("\tTotal size: ");
+
+    /* this delay only needed for original 16MB DIMM...
+     * Not needed for any other memory configuration */
+    if ((sdram_size * chipselects) == (16 *1024 *1024))
+	udelay (250000);
+    return (sdram_size * chipselects);
+	/*return (16 * 1024 * 1024);*/
+}
+
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/board/mpc8266ads/u-boot.lds b/board/mpc8266ads/u-boot.lds
new file mode 100755
index 0000000..2220758
--- /dev/null
+++ b/board/mpc8266ads/u-boot.lds
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mpc8349ads/Makefile b/board/mpc8349ads/Makefile
new file mode 100755
index 0000000..4327b0d
--- /dev/null
+++ b/board/mpc8349ads/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8349ads/config.mk b/board/mpc8349ads/config.mk
new file mode 100755
index 0000000..4602169
--- /dev/null
+++ b/board/mpc8349ads/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC83xxADS
+#
+
+TEXT_BASE  =   0xFE700000
diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c
new file mode 100755
index 0000000..da8d3d7
--- /dev/null
+++ b/board/mpc8349ads/mpc8349ads.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Change log:
+ * 20050101: Eran Liberty (liberty@freescale.com)
+ *           Initial file creating (porting from 85XX & 8260)
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#endif
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#endif
+int fixed_sdram(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	volatile u8* bcsr = (volatile u8*)CFG_BCSR;
+
+	/* Enable flash write */
+	bcsr[1] &= ~0x01;
+
+	return 0;
+}
+
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	u32 msize = 0;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+#if defined(CONFIG_SPD_EEPROM)
+	msize = spd_sdram(NULL);
+#else
+	msize = fixed_sdram();
+#endif
+	/*
+	 * Initialize SDRAM if it is on local bus.
+	 */
+	sdram_init();
+	puts("   DDR RAM: ");
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return (msize * 1024 * 1024);
+}
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+	u32 msize = 0;
+	u32 ddr_size;
+	u32 ddr_size_log2;
+
+	msize = CFG_DDR_SIZE;
+	for (ddr_size = msize << 20, ddr_size_log2 = 0;
+	     (ddr_size > 1);
+	     ddr_size = ddr_size>>1, ddr_size_log2++) {
+		if (ddr_size & 1) {
+			return -1;
+		}
+	}
+	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+#if (CFG_DDR_SIZE != 256)
+#warning Currenly any ddr size other than 256 is not supported
+#endif
+
+	im->ddr.csbnds[0].csbnds = 0x00100017;
+	im->ddr.csbnds[1].csbnds = 0x0018001f;
+	im->ddr.csbnds[2].csbnds = 0x00000007;
+	im->ddr.csbnds[3].csbnds = 0x0008000f;
+	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[1] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[3] = CFG_DDR_CONFIG;
+	im->ddr.timing_cfg_1 =
+		3 << TIMING_CFG1_PRETOACT_SHIFT |
+		7 << TIMING_CFG1_ACTTOPRE_SHIFT |
+		3 << TIMING_CFG1_ACTTORW_SHIFT  |
+		4 << TIMING_CFG1_CASLAT_SHIFT   |
+		3 << TIMING_CFG1_REFREC_SHIFT   |
+		3 << TIMING_CFG1_WRREC_SHIFT    |
+		2 << TIMING_CFG1_ACTTOACT_SHIFT |
+		1 << TIMING_CFG1_WRTORD_SHIFT;
+	im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN
+#if defined(CONFIG_DDR_2T_TIMING)
+		| SDRAM_CFG_2T_EN
+#endif
+		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+	im->ddr.sdram_mode =
+		0x2000 << SDRAM_MODE_ESD_SHIFT |
+		0x0162 << SDRAM_MODE_SD_SHIFT;
+
+	im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
+		0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
+	udelay(200);
+
+	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+
+	return msize;
+}
+#endif/*!CFG_SPD_EEPROM*/
+
+
+int checkboard (void)
+{
+	puts("Board: Freescale MPC8349ADS\n");
+	return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc83xxads_config_table[] = {
+	{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
+	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				    PCI_ENET0_MEMADDR,
+				    PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
+	} },
+	{}
+}
+#endif
+
+
+volatile static struct pci_controller hose[] = {
+	{
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_mpc83xxads_config_table,
+#endif
+	},
+	{
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_mpc83xxads_config_table,
+#endif
+	}
+};
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
+
+	pci_mpc83xx_init(hose);
+#endif /* CONFIG_PCI */
+}
+
+/*
+ * if MPC8349ADS is soldered with SDRAM
+ */
+#if defined(CFG_BR2_PRELIM)  \
+	&& defined(CFG_OR2_PRELIM) \
+	&& defined(CFG_LBLAWBAR2_PRELIM) \
+	&& defined(CFG_LBLAWAR2_PRELIM)
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
+	volatile lbus8349_t *lbc= &immap->lbus;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+	puts("\n   SDRAM on Local Bus: ");
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
+	 */
+
+	/*setup mtrpt, lsrt and lbcr for LB bus*/
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller Machine Mode Register.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/
+
+	lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
+	asm("sync");
+	/*1 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*2 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*3 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*4 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*5 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*6 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*7 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+	/*8 times*/
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	/* 0x58636733;mode register write operation */
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/
+	asm("sync");
+	*sdram_addr = 0xff;
+	udelay(100);
+}
+#else
+void
+sdram_init(void)
+{
+	put("SDRAM on Local Bus is NOT available!\n");
+}
+#endif
diff --git a/board/mpc8349ads/u-boot.lds b/board/mpc8349ads/u-boot.lds
new file mode 100755
index 0000000..020cfa6
--- /dev/null
+++ b/board/mpc8349ads/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/mpc8540ads/Makefile b/board/mpc8540ads/Makefile
new file mode 100755
index 0000000..5d8ea34
--- /dev/null
+++ b/board/mpc8540ads/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8540ads/config.mk b/board/mpc8540ads/config.mk
new file mode 100755
index 0000000..92f8931
--- /dev/null
+++ b/board/mpc8540ads/config.mk
@@ -0,0 +1,33 @@
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8540ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/mpc8540ads/init.S b/board/mpc8540ads/init.S
new file mode 100755
index 0000000..242cb9f
--- /dev/null
+++ b/board/mpc8540ads/init.S
@@ -0,0 +1,280 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xf8000000	16K	BCSR registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 8, 9:	128M	DDR
+	 * 0x00000000	64M	DDR System memory
+	 * 0x04000000	64M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+#error("Update the number of table entries in tlb1_entry")
+	.long TLB1_MAS0(1, 8, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1, 9, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,1,0,1,0,1)
+#endif
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x05
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4
+	entry_end
diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c
new file mode 100755
index 0000000..d0eb690
--- /dev/null
+++ b/board/mpc8540ads/mpc8540ads.c
@@ -0,0 +1,344 @@
+ /*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+int board_early_init_f (void)
+{
+    return 0;
+}
+
+int checkboard (void)
+{
+	puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+	printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+	       CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf("    PCI1: disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    uint temp_ddrdll = 0;
+
+	    /*
+	     * Work around to stabilize DDR DLL
+	     */
+	    temp_ddrdll = gur->ddrdllcr;
+	    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	    asm("sync;isync;msync");
+	}
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+
+	/*
+	 * Initialize SDRAM.
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+	puts("    SDRAM: ");
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
diff --git a/board/mpc8540ads/u-boot.lds b/board/mpc8540ads/u-boot.lds
new file mode 100755
index 0000000..e7a88cf
--- /dev/null
+++ b/board/mpc8540ads/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/mpc8540ads/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/mpc8540ads/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile
new file mode 100755
index 0000000..6f1995e
--- /dev/null
+++ b/board/mpc8540eval/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+#OBJS	:= $(BOARD).o flash.o $(BOARD)_slave.o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8540eval/config.mk b/board/mpc8540eval/config.mk
new file mode 100755
index 0000000..68271bd
--- /dev/null
+++ b/board/mpc8540eval/config.mk
@@ -0,0 +1,34 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# gda8540 board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+#TEXT_BASE = 0x1000000
+TEXT_BASE = 0xfff80000
+
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c
new file mode 100755
index 0000000..7300a04
--- /dev/null
+++ b/board/mpc8540eval/flash.c
@@ -0,0 +1,892 @@
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ *  Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*
+ * The variable should be in the flash info structure. Since it
+ * is only used in this board specific file it is declared here.
+ * In the future I think an endian flag should be part of the
+ * flash_info_t structure. (Ron Alder)
+ */
+static ulong big_endian = 0;
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_block (flash_info_t *info, uchar * src, ulong dest, ulong cnt);
+static int write_short (flash_info_t *info, ulong dest, ushort data);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(flash_info_t *info, vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	case FLASH_28F640J3A:   printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+ /* only deal with 16 bit and 32 bit port width, 16bit chip */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value,va,vb,vc,vd;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+#ifdef DEBUG
+	printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+	udelay(20);
+	asm("sync");
+
+#ifndef CFG_FLASH_CFI
+	printf("Not define CFG_FLASH_CFI\n");
+	return (0);
+#else
+	value = addr[0];
+	va=(value & 0xFF000000)>>24;
+	vb=(value & 0x00FF0000)>>16;
+	vc=(value & 0x0000FF00)>>8;
+	vd=(value & 0x000000FF);
+	if ((va==0) && (vb==0)) {
+		printf("cannot identify Flash\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+	else if ((va==0) && (vb!=0)) {
+		big_endian = 1;
+		info->chipwidth = FLASH_CFI_BY16;
+		if(vb == vd) info->portwidth = FLASH_CFI_32BIT;
+		else info->portwidth = FLASH_CFI_16BIT;
+	}
+	else if ((va!=0) && (vb==0)) {
+		big_endian = 0;
+		info->chipwidth = FLASH_CFI_BY16;
+		if(va == vc) info->portwidth = FLASH_CFI_32BIT;
+		else info->portwidth = FLASH_CFI_16BIT;
+	}
+	else if ((va!=0) && (vb!=0)) {
+		big_endian = 1;		/* no meaning for 8bit chip */
+		info->chipwidth = FLASH_CFI_BY8;
+		if(va == vb) info->portwidth = FLASH_CFI_16BIT;
+		else info->portwidth = FLASH_CFI_8BIT;
+	}
+#ifdef DEBUG
+	switch (info->portwidth) {
+		case FLASH_CFI_8BIT:
+			printf("port width is 8 bit.\n");
+			break;
+		case FLASH_CFI_16BIT:
+			printf("port width is 16 bit, ");
+			break;
+		case FLASH_CFI_32BIT:
+			printf("port width is 32 bit, ");
+			break;
+	}
+	switch (info->chipwidth) {
+		case FLASH_CFI_BY16:
+			printf("chip width is 16 bit, ");
+			switch (big_endian) {
+				case 0:
+					printf("Little Endian.\n");
+					break;
+				case 1:
+					printf("Big Endian.\n");
+					break;
+			}
+			break;
+	}
+#endif
+#endif		/*#ifdef CFG_FLASH_CFI*/
+
+	if (big_endian==0) value = (addr[0] & 0xFF000000) >>8;
+	else value = (addr[0] & 0x00FF0000);
+#ifdef DEBUG
+	printf("manufacturer=0x%x\n",(uint)(value>>16));
+#endif
+	switch (value) {
+	case MT_MANUFACT & 0xFFFF0000:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU & 0xFFFF0000:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	if (info->portwidth==FLASH_CFI_16BIT) {
+		switch (big_endian) {
+			case 0:
+				value = (addr[0] & 0x0000FF00)>>8;
+				break;
+			case 1:
+				value = (addr[0] & 0x000000FF);
+				break;
+		}
+	}
+	else if (info->portwidth == FLASH_CFI_32BIT) {
+		switch (big_endian) {
+			case 0:
+				value = (addr[1] & 0x0000FF00)>>8;
+				break;
+			case 1:
+				value = (addr[1] & 0x000000FF);
+				break;
+		}
+	}
+
+#ifdef DEBUG
+	printf("deviceID=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case (INTEL_ID_28F016S & 0x0000FFFF):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		sector_offset = 0x10000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F160S3 & 0x0000FFFF):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		sector_offset = 0x10000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F320S3 & 0x0000FFFF):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		sector_offset = 0x10000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F640J3A & 0x0000FFFF):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		sector_offset = 0x20000;
+		break;                          /* => 8 MB             */
+
+	case SHARP_ID_28F016SCL & 0x0000FFFF:
+	case SHARP_ID_28F016SCZ & 0x0000FFFF:
+		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+		info->sector_count  = 32;
+		sector_offset = 0x10000;
+		break;				/* => 2 MB		*/
+
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	sector_offset = sector_offset * (info->portwidth / info->chipwidth);
+	info->size = info->sector_count * sector_offset;
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+		asm("sync");
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last, ready, erase_err_status;
+
+	if (big_endian == 1) {
+		ready = 0x0080;
+		erase_err_status = 0x00a0;
+	}
+	else {
+		ready = 0x8000;
+		erase_err_status = 0xa000;
+	}
+	if ((info->portwidth / info->chipwidth)==2) {
+		ready += (ready <<16);
+		erase_err_status += (erase_err_status <<16);
+	}
+
+#ifdef DEBUG
+	printf ("\nReady flag is 0x%lx\nErase error flag is 0x%lx", ready, erase_err_status);
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	printf("\nFlash Erase:\n");
+#endif
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit(info, (vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+	/* Start erase on unprotected sectors */
+#if defined(DEBUG)
+	printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr16 = (vu_short *)(info->start[sect]);
+			vu_long *addr   = (vu_long *)(info->start[sect]);
+			printf(".");
+			switch (info->portwidth) {
+				case FLASH_CFI_16BIT:
+					asm("sync");
+					last = start = get_timer (0);
+					/* Disable interrupts which might cause a timeout here */
+					flag = disable_interrupts();
+					/* Reset Array */
+					*addr16 = 0xffff;
+					asm("sync");
+					/* Clear Status Register */
+					*addr16 = 0x5050;
+					asm("sync");
+					/* Single Block Erase Command */
+					*addr16 = 0x2020;
+					asm("sync");
+					/* Confirm */
+					*addr16 = 0xD0D0;
+					asm("sync");
+					if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+					    /* Resume Command, as per errata update */
+					    *addr16 = 0xD0D0;
+					    asm("sync");
+					}
+					/* re-enable interrupts if necessary */
+					if (flag)
+						enable_interrupts();
+					/* wait at least 80us - let's wait 1 ms */
+					*addr16 = 0x7070;
+					udelay (1000);
+					while ((*addr16 & ready) != ready) {
+						if((*addr16 & erase_err_status)== erase_err_status){
+							printf("Error in Block Erase - Lock Bit may be set!\n");
+							printf("Status Register = 0x%X\n", (uint)*addr16);
+							*addr16 = 0xFFFF;	/* reset bank */
+							asm("sync");
+							return 1;
+						}
+						if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+							printf ("Timeout\n");
+							*addr16 = 0xFFFF;	/* reset bank */
+							asm("sync");
+							return 1;
+						}
+						/* show that we're waiting */
+						if ((now - last) > 1000) {	/* every second */
+							putc ('.');
+							last = now;
+						}
+					}
+					/* reset to read mode */
+					*addr16 = 0xFFFF;
+					asm("sync");
+					break;
+				case FLASH_CFI_32BIT:
+					asm("sync");
+					last = start = get_timer (0);
+					/* Disable interrupts which might cause a timeout here */
+					flag = disable_interrupts();
+					/* Reset Array */
+					*addr = 0xffffffff;
+					asm("sync");
+					/* Clear Status Register */
+					*addr = 0x50505050;
+					asm("sync");
+					/* Single Block Erase Command */
+					*addr = 0x20202020;
+					asm("sync");
+					/* Confirm */
+					*addr = 0xD0D0D0D0;
+					asm("sync");
+					if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+					    /* Resume Command, as per errata update */
+					    *addr = 0xD0D0D0D0;
+					    asm("sync");
+					}
+					/* re-enable interrupts if necessary */
+					if (flag)
+						enable_interrupts();
+					/* wait at least 80us - let's wait 1 ms */
+					*addr = 0x70707070;
+					udelay (1000);
+					while ((*addr & ready) != ready) {
+						if((*addr & erase_err_status)==erase_err_status){
+							printf("Error in Block Erase - Lock Bit may be set!\n");
+							printf("Status Register = 0x%X\n", (uint)*addr);
+							*addr = 0xFFFFFFFF;	/* reset bank */
+							asm("sync");
+							return 1;
+						}
+						if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+							printf ("Timeout\n");
+							*addr = 0xFFFFFFFF;	/* reset bank */
+							asm("sync");
+							return 1;
+						}
+						/* show that we're waiting */
+						if ((now - last) > 1000) {	/* every second */
+							putc ('.');
+							last = now;
+						}
+					}
+					/* reset to read mode */
+					*addr = 0xFFFFFFFF;
+					asm("sync");
+					break;
+			}	/* end switch */
+		}		/* end if */
+	}			/* end for */
+
+	printf ("flash erase done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+#define FLASH_BLOCK_SIZE 32
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data, count, temp;
+/*	ulong temp[FLASH_BLOCK_SIZE/4];*/
+	int i, l, rc;
+
+	count = cnt;
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	cp = wp;
+	/* handle unaligned block bytes , flash block size = 16bytes */
+	wp = (cp+FLASH_BLOCK_SIZE-1) & ~(FLASH_BLOCK_SIZE-1);
+	if ((wp-cp)>=cnt) {
+		if ((rc = write_block(info,src,cp,wp-cp)) !=0)
+			return (rc);
+		src += wp-cp;
+		cnt -= wp-cp;
+	}
+	/* handle aligned block bytes */
+	temp = 0;
+	printf("\n");
+	while ( cnt >= FLASH_BLOCK_SIZE) {
+		if ((rc = write_block(info,src,cp,FLASH_BLOCK_SIZE)) !=0) {
+			return (rc);
+		}
+		src += FLASH_BLOCK_SIZE;
+		cp += FLASH_BLOCK_SIZE;
+		cnt -= FLASH_BLOCK_SIZE;
+		if (((count-cnt)>>10)>temp) {
+			temp=(count-cnt)>>10;
+			printf("\r%d KB",temp);
+		}
+	}
+	printf("\n");
+	wp = cp;
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+#undef FLASH_BLOCK_SIZE
+
+/*-----------------------------------------------------------------------
+ * Write block to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * -1  Error
+ */
+static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt)
+{
+	vu_short *baddr, *addr = (vu_short *)dest;
+	ushort data;
+	ulong start, now, xsr,csr, ready;
+	int flag;
+
+	if (cnt==0) return 0;
+	else if(cnt != (cnt& ~1)) return -1;
+
+	/* Check if Flash is (sufficiently) erased */
+	data = * src;
+	data = (data<<8) | *(src+1);
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	if (big_endian == 1) {
+		ready = 0x0080;
+	}
+	else {
+		ready = 0x8000;
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+		do {
+			/* Write Command */
+			*addr = 0xe8e8;
+			asm("sync");
+			xsr = *addr;
+			asm("sync");
+		} while (!(xsr & ready));	/*wait until read */
+		/*write count=BLOCK SIZE -1 */
+		data=(cnt>>1)-1;
+		data=(data<<8)|data;
+		*addr = data;		/* word mode, cnt/2 */
+		asm("sync");
+		baddr = addr;
+		while(cnt) {
+			data = * src++;
+			data = (data<<8) | *src++;
+			asm("sync");
+			*baddr = data;
+			asm("sync");
+			++baddr;
+			cnt = cnt -2;
+		}
+		*addr = 0xd0d0;			/* confirm write */
+		start = get_timer(0);
+		asm("sync");
+		if (flag)
+			enable_interrupts();
+		/* data polling for D7 */
+		flag  = 0;
+		while (((csr = *addr) & ready) != ready) {
+			if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+				flag = 1;
+				break;
+			}
+		}
+		if (csr & 0x4040) {
+			printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr);
+			flag = 1;
+		}
+		/* Clear Status Registers Command */
+		*addr = 0x5050;
+		asm("sync");
+		/* Reset to read array mode */
+		*addr = 0xFFFF;
+		asm("sync");
+	return (flag);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a short word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *)dest;
+	ulong start, now, csr, ready;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+		/* Write Command */
+		*addr = 0x1010;
+		start = get_timer (0);
+		asm("sync");
+		/* Write Data */
+		*addr = data;
+		asm("sync");
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+		if (big_endian == 1) {
+			ready = 0x0080;
+		}
+		else {
+			ready = 0x8000;
+		}
+		/* data polling for D7 */
+		flag  = 0;
+		while (((csr = *addr) & ready) != ready) {
+			if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+				flag = 1;
+				break;
+			}
+		}
+		if (csr & 0x4040) {
+			printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr);
+			flag = 1;
+		}
+		/* Clear Status Registers Command */
+		*addr = 0x5050;
+		asm("sync");
+		/* Reset to read array mode */
+		*addr = 0xFFFF;
+		asm("sync");
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr, ready;
+	int flag=0;
+
+	switch (info->portwidth) {
+	case FLASH_CFI_32BIT:
+		/* Check if Flash is (sufficiently) erased */
+		if ((*addr & data) != data) {
+			return (2);
+		}
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		if (big_endian == 1) {
+			ready = 0x0080;
+		}
+		else {
+			ready = 0x8000;
+		}
+		if ((info->portwidth / info->chipwidth)==2) {
+			ready += (ready <<16);
+		}
+		else {
+			ready = ready << 16;
+		}
+		/* Write Command */
+		*addr = 0x10101010;
+		asm("sync");
+		/* Write Data */
+		*addr = data;
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+		/* data polling for D7 */
+		start = get_timer (0);
+		flag  = 0;
+		while (((csr = *addr) & ready) != ready) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				flag = 1;
+				break;
+			}
+		}
+		if (csr & 0x40404040) {
+			printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+			flag = 1;
+		}
+		/* Clear Status Registers Command */
+		*addr = 0x50505050;
+		asm("sync");
+		/* Reset to read array mode */
+		*addr = 0xFFFFFFFF;
+		asm("sync");
+		break;
+	case FLASH_CFI_16BIT:
+		flag = write_short (info, dest,  (unsigned short) (data>>16));
+		if (flag == 0)
+			flag = write_short (info, dest+2,  (unsigned short) (data));
+		break;
+	}
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(flash_info_t * info, vu_long  * addr)
+{
+	ulong start, now, ready;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	asm("sync");
+	/* Clear Status Register */
+	*addr = 0x50505050;
+	asm("sync");
+
+	*addr = 0x60606060;
+	asm("sync");
+	*addr = 0xd0d0d0d0;
+	asm("sync");
+
+
+	if (big_endian == 1) {
+		ready = 0x0080;
+	}
+	else {
+		ready = 0x8000;
+	}
+	if ((info->portwidth / info->chipwidth)==2) {
+		ready += (ready <<16);
+	}
+	else {
+		ready = ready << 16;
+	}
+#ifdef DEBUG
+	printf ("%s: Ready flag is 0x%8lx\n", __FUNCTION__, ready);
+#endif
+	*addr = 0x70707070;	/* read status */
+	start = get_timer (0);
+	while((*addr & ready) != ready){
+		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			asm("sync");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S
new file mode 100755
index 0000000..8c2ca65
--- /dev/null
+++ b/board/mpc8540eval/init.S
@@ -0,0 +1,178 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+/* TLB1 entries configuration: */
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	.long 0x0a	/* the following data table uses a few of 16 TLB entries */
+
+	.long TLB1_MAS0(1,1,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if defined(CFG_FLASH_PORT_WIDTH_16)
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+  #if !defined(CONFIG_SPD_EEPROM)
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+	.long TLB1_MAS0(1,6,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+  #if defined(CONFIG_RAM_AS_FLASH)
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+  #else
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,7,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+  #ifdef CONFIG_L2_INIT_RAM
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+  #else
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,8,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,9,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+	entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ *   f800_0000-fbff_ffff: LBC SDRAM(64M)
+ *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ *   fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x03
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	entry_end
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
new file mode 100755
index 0000000..3b3c8ed
--- /dev/null
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+extern long int spd_sdram (void);
+
+long int fixed_sdram (void);
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+	pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info (&sysinfo);
+
+	printf ("Board: Freescale MPC8540EVAL Board\n");
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+		|| (CFG_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %lu MHz\n",
+			sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
+	} else {
+		printf("\tLBC: unknown\n");
+	}
+	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+	return (0);
+}
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	sys_info_t sysinfo;
+	uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+	volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+
+#if defined(CONFIG_DDR_DLL)
+	uint temp_ddrdll = 0;
+
+	/* Work around to stabilize DDR DLL */
+	temp_ddrdll = gur->ddrdllcr;
+	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if defined(CFG_RAMBOOT)
+	return dram_size;
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
+	get_sys_info(&sysinfo);
+	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	} else {
+		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		udelay(200);
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	* (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	* (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	* (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	* (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	{
+		/* Initialize all of memory for ECC, then
+		 * enable errors */
+		uint *p = 0;
+		uint i = 0;
+		volatile immap_t *immap = (immap_t *)CFG_IMMR;
+		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		dma_init();
+		for (*p = 0; p < (uint *)(8 * 1024); p++) {
+			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+			*p = (unsigned int)0xdeadbeef;
+			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+		}
+
+		/* 8K */
+		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+		/* 16K */
+		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+		/* 32K */
+		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+		/* 64K */
+		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+		/* 128k */
+		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+		/* 256k */
+		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+		/* 512k */
+		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+		/* 1M */
+		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+		/* 2M */
+		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+		/* 4M */
+		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+		for (i = 1; i < dram_size / 0x800000; i++) {
+			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+		}
+
+		/* Enable errors for ECC */
+		ddr->err_disable = 0x00000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+#if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+#endif
+	asm("sync;isync;msync");
+	udelay(500);
+#if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+#else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+#endif
+	asm("sync; isync; msync");
+	udelay(500);
+#endif
+	return (CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds
new file mode 100755
index 0000000..0755d01
--- /dev/null
+++ b/board/mpc8540eval/u-boot.lds
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Assumes that the size of u-boot is less than 512K and the
+ * start address is aligned on a 512K block.
+ * Boot page and reset vector is put at that end of the 512K block. */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/mpc8540eval/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+
+  . = (. & 0xFFF80000) + 0x0007F000;
+  .bootpg   :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/mpc8540eval/init.o (.bootpg)
+  } = 0xffff
+
+  . = (. & 0xFFF80000) + 0x0007FFFC;
+  .resetvec  :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+}
diff --git a/board/mpc8560ads/Makefile b/board/mpc8560ads/Makefile
new file mode 100755
index 0000000..5d8ea34
--- /dev/null
+++ b/board/mpc8560ads/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpc8560ads/config.mk b/board/mpc8560ads/config.mk
new file mode 100755
index 0000000..9aef2bb
--- /dev/null
+++ b/board/mpc8560ads/config.mk
@@ -0,0 +1,32 @@
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8560ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/mpc8560ads/init.S b/board/mpc8560ads/init.S
new file mode 100755
index 0000000..242cb9f
--- /dev/null
+++ b/board/mpc8560ads/init.S
@@ -0,0 +1,280 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xf8000000	16K	BCSR registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 8, 9:	128M	DDR
+	 * 0x00000000	64M	DDR System memory
+	 * 0x04000000	64M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+#error("Update the number of table entries in tlb1_entry")
+	.long TLB1_MAS0(1, 8, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1, 9, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,1,0,1,0,1)
+#endif
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x05
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4
+	entry_end
diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c
new file mode 100755
index 0000000..25f69a0
--- /dev/null
+++ b/board/mpc8560ads/mpc8560ads.c
@@ -0,0 +1,546 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+
+/*
+ * MPC8560ADS Board Status & Control Registers
+ */
+typedef struct bcsr_ {
+	volatile unsigned char bcsr0;
+	volatile unsigned char bcsr1;
+	volatile unsigned char bcsr2;
+	volatile unsigned char bcsr3;
+	volatile unsigned char bcsr4;
+	volatile unsigned char bcsr5;
+} bcsr_t;
+
+
+int board_early_init_f (void)
+{
+    return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+	volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
+#endif
+	/* reset Giga bit Ethernet port if needed here */
+
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr->bcsr2 &= ~FETH2_RST;
+	udelay(2);
+	bcsr->bcsr2 |=  FETH2_RST;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr->bcsr3 &= ~FETH3_RST;
+	udelay(2);
+	bcsr->bcsr3 |=  FETH3_RST;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	/* reset PHY */
+	miiphy_reset("FCC1 ETHERNET", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+}
+
+
+int checkboard (void)
+{
+	puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+	printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+	       CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf("    PCI1: disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    uint temp_ddrdll = 0;
+
+	    /*
+	     * Work around to stabilize DDR DLL
+	     */
+	    temp_ddrdll = gur->ddrdllcr;
+	    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	    asm("sync;isync;msync");
+	}
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+
+	/*
+	 * Initialize SDRAM.
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+	puts("    SDRAM: ");
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	asm("msync");
+
+	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+
+	/*
+	 * Configure the SDRAM controller.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
diff --git a/board/mpc8560ads/u-boot.lds b/board/mpc8560ads/u-boot.lds
new file mode 100755
index 0000000..8dcee1f
--- /dev/null
+++ b/board/mpc8560ads/u-boot.lds
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/mpc8560ads/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/mpc8560ads/init.o (.text)
+    cpu/mpc85xx/commproc.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/serial_scc.o (.text)
+    cpu/mpc85xx/ether_fcc.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/i2c.o (.text)
+    cpu/mpc85xx/spd_sdram.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
new file mode 100755
index 0000000..b331d6e
--- /dev/null
+++ b/board/mpl/common/common_util.c
@@ -0,0 +1,674 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <video_fb.h>
+#include "common_util.h"
+#include <asm/processor.h>
+#include <asm/byteorder.h>
+#include <i2c.h>
+#include <devices.h>
+#include <pci.h>
+#include <malloc.h>
+#include <bzlib.h>
+
+#ifdef CONFIG_PIP405
+#include "../pip405/pip405.h"
+#include <405gp_pci.h>
+#endif
+#ifdef CONFIG_MIP405
+#include "../mip405/mip405.h"
+#include <405gp_pci.h>
+#endif
+#if defined(CONFIG_PATI)
+#define FIRM_START 0xFFF00000
+#endif
+
+extern int gunzip(void *, int, uchar *, unsigned long *);
+extern int mem_test(ulong start, ulong ramsize, int quiet);
+
+#define I2C_BACKUP_ADDR 0x7C00		/* 0x200 bytes for backup */
+#define IMAGE_SIZE CFG_MONITOR_LEN	/* ugly, but it works for now */
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+static image_header_t header;
+
+
+static int
+mpl_prg(uchar *src, ulong size)
+{
+	ulong start;
+	flash_info_t *info;
+	int i, rc;
+#if defined(CONFIG_PATI)
+	int start_sect;
+#endif
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
+	char *copystr = (char *)src;
+	ulong *magic = (ulong *)src;
+#endif
+
+	info = &flash_info[0];
+
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
+	if (ntohl(magic[0]) != IH_MAGIC) {
+		puts("Bad Magic number\n");
+		return -1;
+	}
+	/* some more checks before we delete the Flash... */
+	/* Checking the ISO_STRING prevents to program a
+	 * wrong Firmware Image into the flash.
+	 */
+	i = 4; /* skip Magic number */
+	while (1) {
+		if (strncmp(&copystr[i], "MEV-", 4) == 0)
+			break;
+		if (i++ >= 0x100) {
+			puts("Firmware Image for unknown Target\n");
+			return -1;
+		}
+	}
+	/* we have the ISO STRING, check */
+	if (strncmp(&copystr[i], CONFIG_ISO_STRING, sizeof(CONFIG_ISO_STRING)-1) != 0) {
+		printf("Wrong Firmware Image: %s\n", &copystr[i]);
+		return -1;
+	}
+#if !defined(CONFIG_PATI)
+	start = 0 - size;
+	for (i = info->sector_count-1; i > 0; i--) {
+		info->protect[i] = 0; /* unprotect this sector */
+		if (start >= info->start[i])
+			break;
+	}
+	/* set-up flash location */
+	/* now erase flash */
+	printf("Erasing at %lx (sector %d) (start %lx)\n",
+				start,i,info->start[i]);
+	if ((rc = flash_erase (info, i, info->sector_count-1)) != 0) {
+		puts("ERROR ");
+		flash_perror(rc);
+		return (1);
+	}
+
+#else /* #if !defined(CONFIG_PATI */
+	start = FIRM_START;
+	start_sect = -1;
+	for (i = 0; i < info->sector_count; i++) {
+		if (start < info->start[i]) {
+			start_sect = i - 1;
+			break;
+		}
+	}
+
+	info->protect[i - 1] = 0;	/* unprotect this sector */
+	for (; i < info->sector_count; i++) {
+		if ((start + size) < info->start[i])
+			break;
+		info->protect[i] = 0;	/* unprotect this sector */
+	}
+
+	i--;
+	/* set-up flash location */
+	/* now erase flash */
+	printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n",
+		start, start + size, start_sect, i,
+		info->start[start_sect], info->start[i]);
+	if ((rc = flash_erase (info, start_sect, i)) != 0) {
+		puts ("ERROR ");
+		flash_perror (rc);
+		return (1);
+	}
+#endif /* defined(CONFIG_PATI) */
+
+#elif defined(CONFIG_VCMA9)
+	start = 0;
+	for (i = 0; i <info->sector_count; i++) {
+		info->protect[i] = 0; /* unprotect this sector */
+		if (size < info->start[i])
+		    break;
+	}
+	/* set-up flash location */
+	/* now erase flash */
+	printf("Erasing at %lx (sector %d) (start %lx)\n",
+				start,0,info->start[0]);
+	if ((rc = flash_erase (info, 0, i)) != 0) {
+		puts("ERROR ");
+		flash_perror(rc);
+		return (1);
+	}
+
+#endif
+	printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
+		(ulong)src, size);
+	if ((rc = flash_write ((char *)src, start, size)) != 0) {
+		puts("ERROR ");
+		flash_perror(rc);
+		return (1);
+	}
+	puts("OK programming done\n");
+	return 0;
+}
+
+
+static int
+mpl_prg_image(uchar *ld_addr)
+{
+	unsigned long len, checksum;
+	uchar *data;
+	image_header_t *hdr = &header;
+	int rc;
+
+	/* Copy header so we can blank CRC field for re-calculation */
+	memcpy (&header, (char *)ld_addr, sizeof(image_header_t));
+	if (ntohl(hdr->ih_magic)  != IH_MAGIC) {
+		puts("Bad Magic Number\n");
+		return 1;
+	}
+	print_image_hdr(hdr);
+	if (hdr->ih_os  != IH_OS_U_BOOT) {
+		puts("No U-Boot Image\n");
+		return 1;
+	}
+	if (hdr->ih_type  != IH_TYPE_FIRMWARE) {
+		puts("No Firmware Image\n");
+		return 1;
+	}
+	data = (uchar *)&header;
+	len  = sizeof(image_header_t);
+	checksum = ntohl(hdr->ih_hcrc);
+	hdr->ih_hcrc = 0;
+	if (crc32 (0, (uchar *)data, len) != checksum) {
+		puts("Bad Header Checksum\n");
+		return 1;
+	}
+	data = ld_addr + sizeof(image_header_t);
+	len  = ntohl(hdr->ih_size);
+	puts("Verifying Checksum ... ");
+	if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) {
+		puts("Bad Data CRC\n");
+		return 1;
+	}
+	puts("OK\n");
+
+	if (hdr->ih_comp != IH_COMP_NONE) {
+		uchar *buf;
+		/* reserve space for uncompressed image */
+		if ((buf = malloc(IMAGE_SIZE)) == NULL) {
+		    	puts("Insufficient space for decompression\n");
+			return 1;
+		}
+
+		switch (hdr->ih_comp) {
+		case IH_COMP_GZIP:
+			puts("Uncompressing (GZIP) ... ");
+			rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len);
+			if (rc != 0) {
+				puts("GUNZIP ERROR\n");
+				free(buf);
+				return 1;
+			}
+			puts("OK\n");
+			break;
+#ifdef CONFIG_BZIP2
+		case IH_COMP_BZIP2:
+			puts("Uncompressing (BZIP2) ... ");
+			{
+			uint retlen = IMAGE_SIZE;
+			rc = BZ2_bzBuffToBuffDecompress ((char *)(buf), &retlen,
+				(char *)data, len, 0, 0);
+			len = retlen;
+			}
+			if (rc != BZ_OK) {
+				printf ("BUNZIP2 ERROR: %d\n", rc);
+				free(buf);
+				return 1;
+			}
+			puts("OK\n");
+			break;
+#endif
+		default:
+			printf ("Unimplemented compression type %d\n", hdr->ih_comp);
+			free(buf);
+			return 1;
+		}
+
+		rc = mpl_prg(buf, len);
+		free(buf);
+	} else {
+		rc = mpl_prg(data, len);
+	}
+
+	return(rc);
+}
+
+#if !defined(CONFIG_PATI)
+void get_backup_values(backup_t *buf)
+{
+	i2c_read(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
+}
+
+void set_backup_values(int overwrite)
+{
+	backup_t back;
+	int i;
+
+	get_backup_values(&back);
+	if(!overwrite) {
+		if(strncmp(back.signature,"MPL\0",4)==0) {
+			puts("Not possible to write Backup\n");
+			return;
+		}
+	}
+	memcpy(back.signature,"MPL\0",4);
+	i = getenv_r("serial#",back.serial_name,16);
+	if(i < 0) {
+		puts("Not possible to write Backup\n");
+		return;
+	}
+	back.serial_name[16]=0;
+	i = getenv_r("ethaddr",back.eth_addr,20);
+	if(i < 0) {
+		puts("Not possible to write Backup\n");
+		return;
+	}
+	back.eth_addr[20]=0;
+	i2c_write(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
+}
+
+void clear_env_values(void)
+{
+	backup_t back;
+	unsigned char env_crc[4];
+
+	memset(&back,0xff,sizeof(backup_t));
+	memset(env_crc,0x00,4);
+	i2c_write(CFG_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
+	i2c_write(CFG_DEF_EEPROM_ADDR,CFG_ENV_OFFSET,2,(void *)env_crc,4);
+}
+
+/*
+ * check crc of "older" environment
+ */
+int check_env_old_size(ulong oldsize)
+{
+	ulong crc, len, new;
+	unsigned off;
+	uchar buf[64];
+
+	/* read old CRC */
+	eeprom_read (CFG_DEF_EEPROM_ADDR,
+		     CFG_ENV_OFFSET,
+		     (uchar *)&crc, sizeof(ulong));
+
+	new = 0;
+	len = oldsize;
+	off = sizeof(long);
+	len = oldsize-off;
+	while (len > 0) {
+		int n = (len > sizeof(buf)) ? sizeof(buf) : len;
+
+		eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, buf, n);
+		new = crc32 (new, buf, n);
+		len -= n;
+		off += n;
+	}
+
+	return (crc == new);
+}
+
+static ulong oldsizes[] = {
+	0x200,
+	0x800,
+	0
+};
+
+void copy_old_env(ulong size)
+{
+	uchar name_buf[64];
+	uchar value_buf[0x800];
+	uchar c;
+	ulong len;
+	unsigned off;
+	uchar *name, *value;
+
+	name=&name_buf[0];
+	value=&value_buf[0];
+	len=size;
+	off = sizeof(long);
+	while (len > off) {
+		eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, &c, 1);
+		if(c != '=') {
+			*name++=c;
+			off++;
+		}
+		else {
+			*name++='\0';
+			off++;
+			do {
+				eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, &c, 1);
+				*value++=c;
+				off++;
+				if(c == '\0')
+					break;
+			} while(len > off);
+			name=&name_buf[0];
+			value=&value_buf[0];
+			if(strncmp((char *)name,"baudrate",8)!=0) {
+				setenv((char *)name,(char *)value);
+			}
+
+		}
+	}
+}
+
+
+void check_env(void)
+{
+	char *s;
+	int i=0;
+	char buf[32];
+	backup_t back;
+
+	s=getenv("serial#");
+	if(!s) {
+		while(oldsizes[i]) {
+			if(check_env_old_size(oldsizes[i]))
+				break;
+			i++;
+		}
+		if(!oldsizes[i]) {
+			/* no old environment has been found */
+			get_backup_values (&back);
+			if (strncmp (back.signature, "MPL\0", 4) == 0) {
+				sprintf (buf, "%s", back.serial_name);
+				setenv ("serial#", buf);
+				sprintf (buf, "%s", back.eth_addr);
+				setenv ("ethaddr", buf);
+				printf ("INFO:  serial# and ethaddr recovered, use saveenv\n");
+				return;
+			}
+		}
+		else {
+			copy_old_env(oldsizes[i]);
+			puts("INFO:  old environment ajusted, use saveenv\n");
+		}
+	}
+	else {
+		/* check if back up is set */
+		get_backup_values(&back);
+		if(strncmp(back.signature,"MPL\0",4)!=0) {
+			set_backup_values(0);
+		}
+	}
+}
+
+
+extern device_t *stdio_devices[];
+extern char *stdio_names[];
+
+void show_stdio_dev(void)
+{
+	/* Print information */
+	puts("In:    ");
+	if (stdio_devices[stdin] == NULL) {
+		puts("No input devices available!\n");
+	} else {
+		printf ("%s\n", stdio_devices[stdin]->name);
+	}
+
+	puts("Out:   ");
+	if (stdio_devices[stdout] == NULL) {
+		puts("No output devices available!\n");
+	} else {
+		printf ("%s\n", stdio_devices[stdout]->name);
+	}
+
+	puts("Err:   ");
+	if (stdio_devices[stderr] == NULL) {
+		puts("No error devices available!\n");
+	} else {
+		printf ("%s\n", stdio_devices[stderr]->name);
+	}
+}
+
+#endif /* #if !defined(CONFIG_PATI) */
+
+int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ 	ulong size,src,ld_addr;
+	int result;
+#if !defined(CONFIG_PATI)
+	backup_t back;
+	src = MULTI_PURPOSE_SOCKET_ADDR;
+	size = IMAGE_SIZE;
+#endif
+
+	if (strcmp(argv[1], "flash") == 0)
+	{
+#if (CONFIG_COMMANDS & CFG_CMD_FDC)
+		if (strcmp(argv[2], "floppy") == 0) {
+ 			char *local_args[3];
+			extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]);
+			puts("\nupdating bootloader image from floppy\n");
+			local_args[0] = argv[0];
+	    		if(argc==4) {
+				local_args[1] = argv[3];
+				local_args[2] = NULL;
+				ld_addr=simple_strtoul(argv[3], NULL, 16);
+				result=do_fdcboot(cmdtp, 0, 2, local_args);
+			}
+			else {
+				local_args[1] = NULL;
+				ld_addr=CFG_LOAD_ADDR;
+				result=do_fdcboot(cmdtp, 0, 1, local_args);
+			}
+			result=mpl_prg_image((uchar *)ld_addr);
+			return result;
+		}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_FDC) */
+		if (strcmp(argv[2], "mem") == 0) {
+	    		if(argc==4) {
+				ld_addr=simple_strtoul(argv[3], NULL, 16);
+			}
+			else {
+				ld_addr=load_addr;
+			}
+			printf ("\nupdating bootloader image from memory at %lX\n",ld_addr);
+			result=mpl_prg_image((uchar *)ld_addr);
+			return result;
+		}
+#if !defined(CONFIG_PATI)
+		if (strcmp(argv[2], "mps") == 0) {
+			puts("\nupdating bootloader image from MPS\n");
+			result=mpl_prg((uchar *)src,size);
+			return result;
+		}
+#endif /* #if !defined(CONFIG_PATI)	*/
+	}
+	if (strcmp(argv[1], "mem") == 0)
+	{
+		result=0;
+		if(argc==3)
+		{
+			result = (int)simple_strtol(argv[2], NULL, 16);
+	    }
+	    src=(unsigned long)&result;
+	    src-=CFG_MEMTEST_START;
+	    src-=(100*1024); /* - 100k */
+	    src&=0xfff00000;
+	    size=0;
+	    do {
+	    	size++;
+			printf("\n\nPass %ld\n",size);
+			mem_test(CFG_MEMTEST_START,src,1);
+			if(ctrlc())
+				break;
+			if(result>0)
+				result--;
+
+		}while(result);
+		return 0;
+	}
+#if !defined(CONFIG_PATI)
+	if (strcmp(argv[1], "clearenvvalues") == 0)
+	{
+ 		if (strcmp(argv[2], "yes") == 0)
+		{
+			clear_env_values();
+			return 0;
+		}
+	}
+	if (strcmp(argv[1], "getback") == 0) {
+		get_backup_values(&back);
+		back.signature[3]=0;
+		back.serial_name[16]=0;
+		back.eth_addr[20]=0;
+		printf("GetBackUp: signature: %s\n",back.signature);
+		printf("           serial#:   %s\n",back.serial_name);
+		printf("           ethaddr:   %s\n",back.eth_addr);
+		return 0;
+	}
+	if (strcmp(argv[1], "setback") == 0) {
+		set_backup_values(1);
+		return 0;
+	}
+#endif
+	printf("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe(ulong physadr);
+void doc_init (void)
+{
+  doc_probe(MULTI_PURPOSE_SOCKET_ADDR);
+}
+#endif
+
+
+#ifdef CONFIG_VIDEO
+/******************************************************
+ * Routines to display the Board information
+ * to the screen (since the VGA will be initialized as last,
+ * we must resend the infos)
+ */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+extern GraphicDevice ctfb;
+extern int get_boot_mode(void);
+
+void video_get_info_str (int line_number, char *info)
+{
+	/* init video info strings for graphic console */
+	DECLARE_GLOBAL_DATA_PTR;
+	PPC405_SYS_INFO sys_info;
+	char rev;
+	int i,boot;
+	unsigned long pvr;
+	char buf[64];
+	char tmp[16];
+	char cpustr[16];
+	char *s, *e, bc;
+	switch (line_number)
+	{
+	case 2:
+		/* CPU and board infos */
+		pvr=get_pvr();
+		get_sys_info (&sys_info);
+		switch (pvr) {
+			case PVR_405GP_RB: rev='B'; break;
+			case PVR_405GP_RC: rev='C'; break;
+			case PVR_405GP_RD: rev='D'; break;
+			case PVR_405GP_RE: rev='E'; break;
+			case PVR_405GPR_RB: rev='B'; break;
+			default:           rev='?'; break;
+		}
+		if(pvr==PVR_405GPR_RB)
+			sprintf(cpustr,"PPC405GPr %c",rev);
+		else
+			sprintf(cpustr,"PPC405GP %c",rev);
+		/* Board info */
+		i=0;
+		s=getenv ("serial#");
+#ifdef CONFIG_PIP405
+		if (!s || strncmp (s, "PIP405", 6)) {
+			sprintf(buf,"### No HW ID - assuming PIP405");
+		}
+#endif
+#ifdef CONFIG_MIP405
+		if (!s || strncmp (s, "MIP405", 6)) {
+			sprintf(buf,"### No HW ID - assuming MIP405");
+		}
+#endif
+		else {
+			for (e = s; *e; ++e) {
+				if (*e == ' ')
+					break;
+			}
+			for (; s < e; ++s) {
+				if (*s == '_') {
+					++s;
+					break;
+				}
+				buf[i++]=*s;
+			}
+			sprintf(&buf[i]," SN ");
+			i+=4;
+			for (; s < e; ++s) {
+				buf[i++]=*s;
+			}
+			buf[i++]=0;
+		}
+		sprintf (info," %s %s %s MHz (%lu/%lu/%lu MHz)",
+			buf, cpustr,
+			strmhz (tmp, gd->cpu_clk), sys_info.freqPLB / 1000000,
+			sys_info.freqPLB / sys_info.pllOpbDiv / 1000000,
+			sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000);
+		return;
+	case 3:
+		/* Memory Info */
+		boot = get_boot_mode();
+		bc = in8 (CONFIG_PORT_ADDR);
+		sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s",
+			gd->bd->bi_memsize / 0x100000,
+			gd->bd->bi_flashsize / 0x100000,
+			bc,
+			(boot & BOOT_MPS) ? "MPS boot" : "Flash boot",
+			ctfb.modeIdent);
+		return;
+	case 1:
+		sprintf	(buf, "%s",CONFIG_IDENT_STRING);
+		sprintf (info, " %s", &buf[1]);
+		return;
+    }
+    /* no more info lines */
+    *info = 0;
+    return;
+}
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
+
+#endif /* CONFIG_VIDEO */
diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h
new file mode 100755
index 0000000..8f2ec03
--- /dev/null
+++ b/board/mpl/common/common_util.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _COMMON_UTIL_H_
+#define _COMMON_UTIL_H_
+
+typedef struct {
+	char signature[4];
+	char serial_name[17]; 	/* "MIP405_1000xxxxx" */
+	char eth_addr[21];	/* "00:60:C2:0a:00:00" */
+} backup_t;
+
+void get_backup_values(backup_t *buf);
+
+#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
+#define BOOT_MPS	0x01
+#define BOOT_PCI	0x02
+#endif
+
+void show_stdio_dev(void);
+void check_env(void);
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+void doc_init (void);
+#endif
+
+#endif /* _COMMON_UTIL_H_ */
diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c
new file mode 100755
index 0000000..fd43008
--- /dev/null
+++ b/board/mpl/common/flash.c
@@ -0,0 +1,882 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+/*
+ * Modified 3/7/2001
+ * - adapted for pip405, Denis Peter, MPL AG Switzerland
+ * TODO:
+ * clean-up
+ */
+
+#include <common.h>
+
+#if !defined(CONFIG_PATI)
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include "common_util.h"
+#if defined(CONFIG_MIP405)
+#include "../mip405/mip405.h"
+#endif
+#if defined(CONFIG_PIP405)
+#include "../pip405/pip405.h"
+#endif
+#include <405gp_pci.h>
+#else /* defined(CONFIG_PATI) */
+#include <mpc5xx.h>
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt);
+
+#define ADDR0           0x5555
+#define ADDR1           0x2aaa
+#define FLASH_WORD_SIZE unsigned short
+
+#define FALSE           0
+#define TRUE            1
+
+#if !defined(CONFIG_PATI)
+
+/*-----------------------------------------------------------------------
+ * Some CS switching routines:
+ *
+ * On PIP/MIP405 we have 3 (4) possible boot mode
+ *
+ * - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from MPS   (Flash CS = CS1, MPS CS = CS0)
+ * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
+ * - Boot from PCI with MPS map   (Flash CS = CS1, MPS CS = CS0)
+ * The flash init is the first board specific routine which is called
+ * after code relocation (running from SDRAM)
+ * The first thing we do is to map the Flash CS to the Flash area and
+ * the MPS CS to the MPS area. Since the flash size is unknown at this
+ * point, we use the max flash size and the lowest flash address as base.
+ *
+ * After flash detection we adjust the size of the CS area accordingly.
+ * The board_init_r will fill in wrong values in the board init structure,
+ * but this will be fixed in the misc_init_r routine:
+ * bd->bi_flashstart=0-flash_info[0].size
+ * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
+ * bd->bi_flashoffset=0
+ *
+ */
+int get_boot_mode(void)
+{
+	unsigned long pbcr;
+	int res = 0;
+	pbcr = mfdcr (strap);
+	if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
+		/* boot via MPS or MPS mapping */
+		res = BOOT_MPS;
+	if(pbcr & PSR_ROM_LOC)
+		/* boot via PCI.. */
+		res |= BOOT_PCI;
+	 return res;
+}
+
+/* Map the flash high (in boot area)
+   This code can only be executed from SDRAM (after relocation).
+*/
+void setup_cs_reloc(void)
+{
+	int mode;
+	/* Since we are relocated, we can set-up the CS finaly
+	 * but first of all, switch off PCI mapping (in case it was a PCI boot) */
+	out32r(PMM0MA,0L);
+	icache_enable (); /* we are relocated */
+	/* get boot mode */
+	mode=get_boot_mode();
+	/* we map the flash high in every case */
+	/* first findout on which cs the flash is */
+	if(mode & BOOT_MPS) {
+		/* map flash high on CS1 and MPS on CS0 */
+		mtdcr (ebccfga, pb0ap);
+		mtdcr (ebccfgd, MPS_AP);
+		mtdcr (ebccfga, pb0cr);
+		mtdcr (ebccfgd, MPS_CR);
+		/* we use the default values (max values) for the flash
+		 * because its real size is not yet known */
+		mtdcr (ebccfga, pb1ap);
+		mtdcr (ebccfgd, FLASH_AP);
+		mtdcr (ebccfga, pb1cr);
+		mtdcr (ebccfgd, FLASH_CR_B);
+	}
+	else {
+		/* map flash high on CS0 and MPS on CS1 */
+		mtdcr (ebccfga, pb1ap);
+		mtdcr (ebccfgd, MPS_AP);
+		mtdcr (ebccfga, pb1cr);
+		mtdcr (ebccfgd, MPS_CR);
+		/* we use the default values (max values) for the flash
+		 * because its real size is not yet known */
+		mtdcr (ebccfga, pb0ap);
+		mtdcr (ebccfgd, FLASH_AP);
+		mtdcr (ebccfga, pb0cr);
+		mtdcr (ebccfgd, FLASH_CR_B);
+	}
+}
+
+#endif /* #if !defined(CONFIG_PATI) */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+
+#if !defined(CONFIG_PATI)
+	unsigned long size_b1,flashcr,size_reg;
+	int mode;
+	extern char version_string;
+	char *p=&version_string;
+
+	/* Since we are relocated, we can set-up the CS finally */
+	setup_cs_reloc();
+	/* get and display boot mode */
+	mode=get_boot_mode();
+	if(mode & BOOT_PCI)
+		printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ?
+			"MPS" : "Flash");
+	else
+		printf("(%s Boot) ",(mode & BOOT_MPS) ?
+			"MPS" : "Flash");
+#endif /* #if !defined(CONFIG_PATI) */
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)CFG_MONITOR_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+	/* protect the bootloader */
+	/* Monitor protection ON by default */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_MONITOR_BASE,
+			CFG_MONITOR_BASE+monitor_flash_len-1,
+			&flash_info[0]);
+#endif
+#if !defined(CONFIG_PATI)
+	/* protect reset vector */
+	flash_info[0].protect[flash_info[0].sector_count-1] = 1;
+	size_b1 = 0 ;
+	flash_info[0].size = size_b0;
+	/* set up flash cs according to the size */
+	size_reg=(flash_info[0].size >>20);
+	switch (size_reg) {
+		case 0:
+		case 1: i=0; break; /* <= 1MB */
+		case 2: i=1; break; /* = 2MB */
+		case 4: i=2; break; /* = 4MB */
+		case 8: i=3; break; /* = 8MB */
+		case 16: i=4; break; /* = 16MB */
+		case 32: i=5; break; /* = 32MB */
+		case 64: i=6; break; /* = 64MB */
+		case 128: i=7; break; /*= 128MB */
+		default:
+			printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg);
+			while(1);
+	}
+	if(mode & BOOT_MPS) {
+		/* flash is on CS1 */
+		mtdcr(ebccfga, pb1cr);
+		flashcr = mfdcr (ebccfgd);
+		/* we map the flash high in every case */
+		flashcr&=0x0001FFFF; /* mask out address bits */
+		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+		flashcr|= (i << 17); /* size addr */
+		mtdcr(ebccfga, pb1cr);
+		mtdcr(ebccfgd, flashcr);
+	}
+	else {
+		/* flash is on CS0 */
+		mtdcr(ebccfga, pb0cr);
+		flashcr = mfdcr (ebccfgd);
+		/* we map the flash high in every case */
+		flashcr&=0x0001FFFF; /* mask out address bits */
+		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
+		flashcr|= (i << 17); /* size addr */
+		mtdcr(ebccfga, pb0cr);
+		mtdcr(ebccfgd, flashcr);
+	}
+#if 0
+	/* enable this (PIP405/MIP405 only) if you want to test if
+	   the relocation has be done ok.
+	   This will disable both Chipselects */
+	mtdcr (ebccfga, pb0cr);
+	mtdcr (ebccfgd, 0L);
+	mtdcr (ebccfga, pb1cr);
+	mtdcr (ebccfgd, 0L);
+	printf("CS0 & CS1 switched off for test\n");
+#endif
+	/* patch version_string */
+	for(i=0;i<0x100;i++) {
+		if(*p=='\n') {
+			*p=0;
+			break;
+		}
+		p++;
+	}
+#else /* #if !defined(CONFIG_PATI) */
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif /* #if !defined(CONFIG_PATI) */
+	return (size_b0);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+				break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+				break;
+	case FLASH_INTEL320T:	printf ("TE28F320C3 (32 Mbit, top sector size)\n");
+				break;
+	case FLASH_AM640U:	printf ("AM29LV640U (64 Mbit, uniform sector size)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		*/
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+
+*/
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[0];
+	/*	printf("flash_get_size value: %x\n",value); */
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	case (FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+	value = addr2[1];			/* device ID		*/
+	/*	printf("Device value %x\n",value); 		    */
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000; /* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (FLASH_WORD_SIZE)AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#if 0	/* enable when device IDs are available */
+
+	case (FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#endif
+	case (FLASH_WORD_SIZE)SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (FLASH_WORD_SIZE)INTEL_ID_28F320C3T:
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+
+	case (FLASH_WORD_SIZE)SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* base address calculation */
+	base=0-info->size;
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	     (info->flash_id  == FLASH_AM040) ||
+	     (info->flash_id  == FLASH_AM640U)){
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+	else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++)
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+		else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			if(info->sector_count==71) {
+
+				info->start[i--] = base + info->size - 0x00002000;
+				info->start[i--] = base + info->size - 0x00004000;
+				info->start[i--] = base + info->size - 0x00006000;
+				info->start[i--] = base + info->size - 0x00008000;
+				info->start[i--] = base + info->size - 0x0000A000;
+				info->start[i--] = base + info->size - 0x0000C000;
+				info->start[i--] = base + info->size - 0x0000E000;
+				for (; i >= 0; i--)
+					info->start[i] = base + i * 0x000010000;
+			}
+			else {
+				info->start[i--] = base + info->size - 0x00004000;
+				info->start[i--] = base + info->size - 0x00006000;
+				info->start[i--] = base + info->size - 0x00008000;
+				for (; i >= 0; i--)
+					info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+	return (info->size);
+}
+
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return ERR_OK;
+}
+
+int intel_wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last, status;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	status = addr[0] & (FLASH_WORD_SIZE)0x00280028;
+	/* clear status register */
+	addr[0] = (FLASH_WORD_SIZE)0x00500050;
+	/* check status for block erase fail and VPP low */
+	return (status == 0 ? ERR_OK : ERR_NOT_ERASED);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i, rcode = 0;
+
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+			/*  printf("Erasing sector %p\n", addr2); */ /* CLH */
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+				for (i=0; i<50; i++)
+					udelay(1000);  /* wait 1 ms */
+				rcode |= wait_for_DQ7(info, sect);
+			}
+			else {
+				if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){
+					addr2[0] = (FLASH_WORD_SIZE)0x00600060;  /* unlock sector */
+					addr2[0] = (FLASH_WORD_SIZE)0x00D000D0;  /* sector erase */
+					intel_wait_for_DQ7(info, sect);
+					addr2[0] = (FLASH_WORD_SIZE)0x00200020;  /* sector erase */
+					addr2[0] = (FLASH_WORD_SIZE)0x00D000D0;  /* sector erase */
+					rcode |= intel_wait_for_DQ7(info, sect);
+				}
+				else {
+					addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+					addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+					addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+					addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+					addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+					addr2[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+					rcode |= wait_for_DQ7(info, sect);
+				}
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			/*   wait_for_DQ7(info, sect); */
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7(info, l_sect);
+
+DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	if (!rcode)
+	    printf (" done\n");
+
+	return rcode;
+}
+
+
+void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt)
+{
+	int i;
+	volatile FLASH_WORD_SIZE *addr2;
+	long c;
+	c= (long)cnt;
+	for(i=info->sector_count-1;i>0;i--)
+	{
+		if(addr>=info->start[i])
+			break;
+	}
+	do {
+		addr2 = (FLASH_WORD_SIZE *)(info->start[i]);
+		addr2[0] = (FLASH_WORD_SIZE)0x00600060;  /* unlock sector setup */
+		addr2[0] = (FLASH_WORD_SIZE)0x00D000D0;  /* unlock sector */
+		intel_wait_for_DQ7(info, i);
+		i++;
+		c-=(info->start[i]-info->start[i-1]);
+	}while(c>0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){
+		unlock_intel_sectors(info,addr,cnt);
+	}
+	wp = (addr & ~3);	/* get lower word aligned address */
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		if((wp % 0x10000)==0)
+			printf("."); /* show Progress */
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+	rc=write_word(info, wp, data);
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static FLASH_WORD_SIZE *read_val = (FLASH_WORD_SIZE *)0x200000;
+
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *)dest) &
+		(FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	{
+		if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){
+			/* intel style writting */
+			dest2[i] = (FLASH_WORD_SIZE)0x00500050;
+			dest2[i] = (FLASH_WORD_SIZE)0x00400040;
+			*read_val++ = data2[i];
+			dest2[i] = data2[i];
+			if (flag)
+				enable_interrupts();
+			/* data polling for D7 */
+			start = get_timer (0);
+			udelay(10);
+			while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080)
+			{
+				if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+					return (1);
+			}
+			dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */
+			udelay(10);
+			dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */
+			if(dest2[i]!=data2[i])
+				printf("Error at %p 0x%04X != 0x%04X\n",&dest2[i],dest2[i],data2[i]);
+		}
+		else {
+			addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+			addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+			addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+			dest2[i] = data2[i];
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+			/* data polling for D7 */
+			start = get_timer (0);
+			while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+				(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+				if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+					return (1);
+				}
+			}
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c
new file mode 100755
index 0000000..51b2773
--- /dev/null
+++ b/board/mpl/common/isa.c
@@ -0,0 +1,494 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * TODO: clean-up
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <devices.h>
+#include "isa.h"
+#include "piix4_pci.h"
+#include "kbd.h"
+#include "video.h"
+
+
+#undef	ISA_DEBUG
+
+#ifdef	ISA_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#ifndef	TRUE
+#define TRUE            1
+#endif
+#ifndef FALSE
+#define FALSE           0
+#endif
+
+#if defined(CONFIG_PIP405)
+
+extern int drv_isa_kbd_init (void);
+
+/* fdc (logical device 0) */
+const SIO_LOGDEV_TABLE sio_fdc[] = {
+	{0x60, 3},			/* set IO to FDPort (3F0) */
+	{0x61, 0xF0},		/* set IO to FDPort (3F0) */
+	{0x70, 06},			/* set IRQ 6 for FDPort */
+	{0x74, 02},			/* set DMA 2 for FDPort */
+	{0xF0, 0x05},		/* set to PS2 type */
+	{0xF1, 0x00},	  /* default value */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+/* paralell port (logical device 3) */
+const SIO_LOGDEV_TABLE sio_pport[] = {
+	{0x60, 3},			/* set IO to PPort (378) */
+	{0x61, 0x78},		/* set IO to PPort (378) */
+	{0x70, 07},			/* set IRQ 7 for PPort */
+	{0xF1, 00},			/* set PPort to normal */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+/* paralell port (logical device 3) Floppy assigned to lpt */
+const SIO_LOGDEV_TABLE sio_pport_fdc[] = {
+	{0x60, 3},			/* set IO to PPort (378) */
+	{0x61, 0x78},		/* set IO to PPort (378) */
+	{0x70, 07},			/* set IRQ 7 for PPort */
+	{0xF1, 02},			/* set PPort to Floppy */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+/* uart 1 (logical device 4) */
+const SIO_LOGDEV_TABLE sio_com1[] = {
+	{0x60, 3},			/* set IO to COM1 (3F8) */
+	{0x61, 0xF8},		/* set IO to COM1 (3F8) */
+	{0x70, 04},			/* set IRQ 4 for COM1 */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+/* uart 2 (logical device 5) */
+const SIO_LOGDEV_TABLE sio_com2[] = {
+	{0x60, 2},			/* set IO to COM2 (2F8) */
+	{0x61, 0xF8},		/* set IO to COM2 (2F8) */
+	{0x70, 03},			/* set IRQ 3 for COM2 */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+
+/* keyboard controller (logical device 7) */
+const SIO_LOGDEV_TABLE sio_keyboard[] = {
+	{0x70, 1},			/* set IRQ 1 for keyboard */
+	{0x72, 12},			/* set IRQ 12 for mouse */
+	{0xF0, 0},			/* disable Port92 (this is a PowerPC!!) */
+	{0x30, 1},			/* and activate the device */
+	{0xFF, 0}				/* end of device table */
+};
+
+
+/*******************************************************************************
+* Config SuperIO FDC37C672
+********************************************************************************/
+unsigned char open_cfg_super_IO(int address)
+{
+	out8(CFG_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
+	out8(CFG_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
+	if(in8(CFG_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
+		return TRUE;
+	else
+		return FALSE;
+}
+
+void close_cfg_super_IO(int address)
+{
+	out8(CFG_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */
+}
+
+
+unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr)
+{
+	/* assuming config reg is open */
+	out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
+	out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
+	out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
+	return in8(CFG_ISA_IO_BASE_ADDRESS | address | 1);
+}
+
+void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data)
+{
+	/* assuming config reg is open */
+	out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
+	out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
+	out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
+	out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */
+}
+
+void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev)
+{
+	while (ldt->index != 0xFF) {
+		write_cfg_super_IO(SIO_CFG_PORT, ldev, ldt->index, ldt->val);
+		ldt++;
+	} /* endwhile */
+}
+
+void isa_sio_loadtable(void)
+{
+	char *s = getenv("floppy");
+	/* setup Floppy device 0*/
+	isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0);
+	/* setup parallel port device 3 */
+	if(s && !strncmp(s, "lpt", 3)) {
+		printf("SIO:   Floppy assigned to LPT\n");
+		/* floppy is assigned to the LPT */
+		isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport_fdc,3);
+	}
+	else {
+		/*printf("Floppy assigned to internal port\n");*/
+		isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport,3);
+	}
+	/* setup Com1 port device 4 */
+	isa_write_table((SIO_LOGDEV_TABLE *)&sio_com1,4);
+	/* setup Com2 port device 5 */
+	isa_write_table((SIO_LOGDEV_TABLE *)&sio_com2,5);
+	/* setup keyboards device 7 */
+	isa_write_table((SIO_LOGDEV_TABLE *)&sio_keyboard,7);
+}
+
+
+void isa_sio_setup(void)
+{
+	if(open_cfg_super_IO(SIO_CFG_PORT)==TRUE)
+	{
+		isa_sio_loadtable();
+		close_cfg_super_IO(0x3F0);
+	}
+}
+#endif
+
+/******************************************************************************
+ * IRQ Controller
+ * we use the Vector mode
+ */
+
+struct	isa_irq_action {
+	 interrupt_handler_t *handler;
+	 void *arg;
+	 int count;
+};
+
+static struct isa_irq_action isa_irqs[16];
+
+
+/*
+ * This contains the irq mask for both 8259A irq controllers,
+ */
+static unsigned int cached_irq_mask = 0xfff9;
+
+#define cached_imr1	(unsigned char)cached_irq_mask
+#define cached_imr2	(unsigned char)(cached_irq_mask>>8)
+#define IMR_1		CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1
+#define IMR_2		CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1
+#define ICW1_1	CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1
+#define ICW1_2	CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1
+#define ICW2_1	CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2
+#define ICW2_2	CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2
+#define ICW3_1	ICW2_1
+#define ICW3_2	ICW2_2
+#define ICW4_1	ICW2_1
+#define ICW4_2	ICW2_2
+#define ISR_1		ICW1_1
+#define ISR_2		ICW1_2
+
+
+void disable_8259A_irq(unsigned int irq)
+{
+	unsigned int mask = 1 << irq;
+
+	cached_irq_mask |= mask;
+	if (irq & 8)
+		out8(IMR_2,cached_imr2);
+	else
+		out8(IMR_1,cached_imr1);
+}
+
+void enable_8259A_irq(unsigned int irq)
+{
+	unsigned int mask = ~(1 << irq);
+
+	cached_irq_mask &= mask;
+	if (irq & 8)
+		out8(IMR_2,cached_imr2);
+	else
+		out8(IMR_1,cached_imr1);
+}
+/*
+int i8259A_irq_pending(unsigned int irq)
+{
+	unsigned int mask = 1<<irq;
+	int ret;
+
+	if (irq < 8)
+		ret = inb(0x20) & mask;
+	else
+		ret = inb(0xA0) & (mask >> 8);
+	spin_unlock_irqrestore(&i8259A_lock, flags);
+
+	return ret;
+}
+*/
+
+/*
+ * This function assumes to be called rarely. Switching between
+ * 8259A registers is slow.
+ */
+int i8259A_irq_real(unsigned int irq)
+{
+	int value;
+	int irqmask = 1<<irq;
+
+	if (irq < 8) {
+		out8(ISR_1,0x0B);		/* ISR register */
+		value = in8(ISR_1) & irqmask;
+		out8(ISR_1,0x0A);		/* back to the IRR register */
+		return value;
+	}
+	out8(ISR_2,0x0B);		/* ISR register */
+	value = in8(ISR_2) & (irqmask >> 8);
+	out8(ISR_2,0x0A);		/* back to the IRR register */
+	return value;
+}
+
+/*
+ * Careful! The 8259A is a fragile beast, it pretty
+ * much _has_ to be done exactly like this (mask it
+ * first, _then_ send the EOI, and the order of EOI
+ * to the two 8259s is important!
+ */
+void mask_and_ack_8259A(unsigned int irq)
+{
+	unsigned int irqmask = 1 << irq;
+	unsigned int temp_irqmask = cached_irq_mask;
+	/*
+	 * Lightweight spurious IRQ detection. We do not want
+	 * to overdo spurious IRQ handling - it's usually a sign
+	 * of hardware problems, so we only do the checks we can
+	 * do without slowing down good hardware unnecesserily.
+	 *
+	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
+	 * usually resulting from the 8259A-1|2 PICs) occur
+	 * even if the IRQ is masked in the 8259A. Thus we
+	 * can check spurious 8259A IRQs without doing the
+	 * quite slow i8259A_irq_real() call for every IRQ.
+	 * This does not cover 100% of spurious interrupts,
+	 * but should be enough to warn the user that there
+	 * is something bad going on ...
+	 */
+	if (temp_irqmask & irqmask)
+		goto spurious_8259A_irq;
+	temp_irqmask |= irqmask;
+
+handle_real_irq:
+	if (irq & 8) {
+		in8(IMR_2);		/* DUMMY - (do we need this?) */
+		out8(IMR_2,(unsigned char)(temp_irqmask>>8));
+		out8(ISR_2,0x60+(irq&7));/* 'Specific EOI' to slave */
+		out8(ISR_1,0x62);	/* 'Specific EOI' to master-IRQ2 */
+		out8(IMR_2,cached_imr2); /* turn it on again */
+	} else {
+		in8(IMR_1);		/* DUMMY - (do we need this?) */
+		out8(IMR_1,(unsigned char)temp_irqmask);
+		out8(ISR_1,0x60+irq);	/* 'Specific EOI' to master */
+		out8(IMR_1,cached_imr1); /* turn it on again */
+	}
+
+	return;
+
+spurious_8259A_irq:
+	/*
+	 * this is the slow path - should happen rarely.
+	 */
+	if (i8259A_irq_real(irq))
+		/*
+		 * oops, the IRQ _is_ in service according to the
+		 * 8259A - not spurious, go handle it.
+		 */
+		goto handle_real_irq;
+
+	{
+		static int spurious_irq_mask;
+		/*
+		 * At this point we can be sure the IRQ is spurious,
+		 * lets ACK and report it. [once per IRQ]
+		 */
+		if (!(spurious_irq_mask & irqmask)) {
+			PRINTF("spurious 8259A interrupt: IRQ%d.\n", irq);
+			spurious_irq_mask |= irqmask;
+		}
+		/* irq_err_count++; */
+		/*
+		 * Theoretically we do not have to handle this IRQ,
+		 * but in Linux this does not cause problems and is
+		 * simpler for us.
+		 */
+		goto handle_real_irq;
+	}
+}
+
+void init_8259A(void)
+{
+	out8(IMR_1,0xff);	/* mask all of 8259A-1 */
+	out8(IMR_2,0xff);	/* mask all of 8259A-2 */
+
+	out8(ICW1_1,0x11);	/* ICW1: select 8259A-1 init */
+	out8(ICW2_1,0x20 + 0);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
+	out8(ICW3_1,0x04);	/* 8259A-1 (the master) has a slave on IR2 */
+	out8(ICW4_1,0x01);	/* master expects normal EOI */
+	out8(ICW1_2,0x11);	/* ICW2: select 8259A-2 init */
+	out8(ICW2_2,0x20 + 8);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
+	out8(ICW3_2,0x02);	/* 8259A-2 is a slave on master's IR2 */
+	out8(ICW4_2,0x01);	/* (slave's support for AEOI in flat mode
+				    is to be investigated) */
+	udelay(10000);		/* wait for 8259A to initialize */
+	out8(IMR_1,cached_imr1);	/* restore master IRQ mask */
+	udelay(10000);		/* wait for 8259A to initialize */
+	out8(IMR_2,cached_imr2);	/* restore slave IRQ mask */
+}
+
+
+#define PCI_INT_ACK_ADDR 0xEED00000
+
+int handle_isa_int(void)
+{
+	unsigned long irqack;
+	unsigned char isr1,isr2,irq;
+	/* first we acknokledge the int via the PCI bus */
+	irqack=in32(PCI_INT_ACK_ADDR);
+	/* now we get the ISRs */
+	isr2=in8(ISR_2);
+	isr1=in8(ISR_1);
+	irq=(unsigned char)irqack;
+	irq-=32;
+/*	if((irq==7)&&((isr1&0x80)==0)) {
+		PRINTF("IRQ7 detected but not in ISR\n");
+	}
+	else {
+*/		/* we should handle cascaded interrupts here also */
+	{
+/*		printf("ISA Irq %d\n",irq); */
+		isa_irqs[irq].count++;
+		if(irq!=2) { /* just swallow the cascade irq 2 */
+			if (isa_irqs[irq].handler != NULL)
+				(*isa_irqs[irq].handler)(isa_irqs[irq].arg);      /* call isr */
+			else {
+				PRINTF ("bogus interrupt vector 0x%x\n", irq);
+			}
+		}
+	}
+	/* issue EOI instruction to clear the IRQ */
+	mask_and_ack_8259A(irq);
+	return 0;
+}
+
+
+/******************************************************************
+ * Install and free an ISA interrupt handler.
+ */
+
+void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+{
+	if (isa_irqs[vec].handler != NULL) {
+		printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
+			vec, (uint)handler, (uint)isa_irqs[vec].handler);
+	}
+	isa_irqs[vec].handler = handler;
+	isa_irqs[vec].arg     = arg;
+	enable_8259A_irq(vec);
+	PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
+
+}
+
+void isa_irq_free_handler(int vec)
+{
+	disable_8259A_irq(vec);
+	isa_irqs[vec].handler = NULL;
+	isa_irqs[vec].arg     = NULL;
+	PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
+
+}
+
+/****************************************************************************/
+void isa_init_irq_contr(void)
+{
+	int i;
+	/* disable all Interrupts */
+	/* first write icws controller 1 */
+	for(i=0;i<16;i++)
+	{
+		isa_irqs[i].handler=NULL;
+		isa_irqs[i].arg=NULL;
+		isa_irqs[i].count=0;
+	}
+	init_8259A();
+	out8(IMR_2,0xFF);
+}
+/*************************************************************************/
+
+void isa_show_irq(void)
+{
+	int vec;
+
+	printf ("\nISA Interrupt-Information:\n");
+	printf ("Nr  Routine   Arg       Count\n");
+
+	for (vec=0; vec<16; vec++) {
+		if (isa_irqs[vec].handler != NULL) {
+			printf ("%02d  %08lx  %08lx  %d\n",
+				vec,
+				(ulong)isa_irqs[vec].handler,
+				(ulong)isa_irqs[vec].arg,
+				isa_irqs[vec].count);
+		}
+	}
+}
+
+int isa_irq_get_count(int vec)
+{
+	return(isa_irqs[vec].count);
+}
+
+/******************************************************************
+ * Init the ISA bus and devices.
+ */
+
+#if defined(CONFIG_PIP405)
+
+int isa_init(void)
+{
+	isa_sio_setup();
+	isa_init_irq_contr();
+	drv_isa_kbd_init();
+	return 0;
+}
+#endif
diff --git a/board/mpl/common/isa.h b/board/mpl/common/isa.h
new file mode 100755
index 0000000..28ed219
--- /dev/null
+++ b/board/mpl/common/isa.h
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ISA_H_
+#define _ISA_H_
+/* Super IO */
+#define SIO_CFG_PORT	0x3F0	/* Config Port Address */
+
+#if defined(CONFIG_PIP405)
+/* table fore SIO initialization */
+typedef struct {
+	const uchar index;
+	const uchar val;
+} SIO_LOGDEV_TABLE;
+
+typedef struct {
+	const uchar ldev;
+	const SIO_LOGDEV_TABLE *ldev_table;
+} SIO_TABLE;
+
+
+unsigned char open_cfg_super_IO(int address);
+unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr);
+void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
+void close_cfg_super_IO(int address);
+void isa_sio_setup(void);
+#endif
+
+void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
+void isa_irq_free_handler(int vec);
+int handle_isa_int(void);
+void isa_init_irq_contr(void);
+void isa_show_irq(void);
+int isa_irq_get_count(int vec);
+
+
+#endif
diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c
new file mode 100755
index 0000000..7724e24
--- /dev/null
+++ b/board/mpl/common/kbd.c
@@ -0,0 +1,647 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Source partly derived from:
+ * linux/drivers/char/pc_keyb.c
+ *
+ *
+ */
+#include <common.h>
+#include <asm/processor.h>
+#include <devices.h>
+#include "isa.h"
+#include "kbd.h"
+
+
+unsigned char kbd_read_status(void);
+unsigned char kbd_read_input(void);
+void kbd_send_data(unsigned char data);
+void disable_8259A_irq(unsigned int irq);
+void enable_8259A_irq(unsigned int irq);
+
+/* used only by send_data - set by keyboard_interrupt */
+
+
+#undef KBG_DEBUG
+
+#ifdef KBG_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#define KBD_STAT_KOBF		0x01
+#define KBD_STAT_IBF		0x02
+#define KBD_STAT_SYS		0x04
+#define KBD_STAT_CD			0x08
+#define KBD_STAT_LOCK		0x10
+#define KBD_STAT_MOBF		0x20
+#define KBD_STAT_TI_OUT	0x40
+#define KBD_STAT_PARERR	0x80
+
+#define KBD_INIT_TIMEOUT 1000		/* Timeout in ms for initializing the keyboard */
+#define KBC_TIMEOUT 250			/* Timeout in ms for sending to keyboard controller */
+#define KBD_TIMEOUT 2000		/* Timeout in ms for keyboard command acknowledge */
+/*
+ *	Keyboard Controller Commands
+ */
+
+#define KBD_CCMD_READ_MODE			0x20	/* Read mode bits */
+#define KBD_CCMD_WRITE_MODE			0x60	/* Write mode bits */
+#define KBD_CCMD_GET_VERSION		0xA1	/* Get controller version */
+#define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
+#define KBD_CCMD_MOUSE_ENABLE		0xA8	/* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE			0xA9	/* Mouse interface test */
+#define KBD_CCMD_SELF_TEST			0xAA	/* Controller self test */
+#define KBD_CCMD_KBD_TEST				0xAB	/* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE		0xAD	/* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE			0xAE	/* Keyboard interface enable */
+#define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
+					   initiated by the auxiliary device */
+#define KBD_CCMD_WRITE_MOUSE		0xD4	/* Write the following byte to the mouse */
+
+/*
+ *	Keyboard Commands
+ */
+
+#define KBD_CMD_SET_LEDS				0xED	/* Set keyboard leds */
+#define KBD_CMD_SET_RATE				0xF3	/* Set typematic rate */
+#define KBD_CMD_ENABLE					0xF4	/* Enable scanning */
+#define KBD_CMD_DISABLE					0xF5	/* Disable scanning */
+#define KBD_CMD_RESET						0xFF	/* Reset */
+
+/*
+ *	Keyboard Replies
+ */
+
+#define KBD_REPLY_POR						0xAA	/* Power on reset */
+#define KBD_REPLY_ACK						0xFA	/* Command ACK */
+#define KBD_REPLY_RESEND				0xFE	/* Command NACK, send the cmd again */
+
+/*
+ *	Status Register Bits
+ */
+
+#define KBD_STAT_OBF 						0x01	/* Keyboard output buffer full */
+#define KBD_STAT_IBF 						0x02	/* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST				0x04	/* Self test successful */
+#define KBD_STAT_CMD						0x08	/* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED				0x10	/* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF			0x20	/* Mouse output buffer full */
+#define KBD_STAT_GTO 						0x40	/* General receive/xmit timeout */
+#define KBD_STAT_PERR 					0x80	/* Parity error */
+
+#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
+
+/*
+ *	Controller Mode Register Bits
+ */
+
+#define KBD_MODE_KBD_INT				0x01	/* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT			0x02	/* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS 						0x04	/* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK			0x08	/* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD		0x10	/* Disable keyboard interface */
+#define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
+#define KBD_MODE_KCC 						0x40	/* Scan code conversion to PC format */
+#define KBD_MODE_RFU						0x80
+
+
+#define KDB_DATA_PORT			0x60
+#define KDB_COMMAND_PORT	0x64
+
+#define 	LED_SCR		0x01	/* scroll lock led */
+#define 	LED_CAP		0x04	/* caps lock led */
+#define 	LED_NUM		0x02	/* num lock led */
+
+#define 	KBD_BUFFER_LEN 0x20  /* size of the keyboardbuffer */
+
+
+static volatile char kbd_buffer[KBD_BUFFER_LEN];
+static volatile int in_pointer = 0;
+static volatile int out_pointer = 0;
+
+
+static unsigned char num_lock = 0;
+static unsigned char caps_lock = 0;
+static unsigned char scroll_lock = 0;
+static unsigned char shift = 0;
+static unsigned char ctrl = 0;
+static unsigned char alt = 0;
+static unsigned char e0 = 0;
+static unsigned char leds = 0;
+
+#define DEVNAME "kbd"
+
+/* Simple translation table for the keys */
+
+static unsigned char kbd_plain_xlate[] = {
+	0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t',	/* 0x00 - 0x0f */
+	 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's',	/* 0x10 - 0x1f */
+	 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v',	/* 0x20 - 0x2f */
+	 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
+	'\r',0xff,0xff
+	};
+
+static unsigned char kbd_shift_xlate[] = {
+	0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t',	/* 0x00 - 0x0f */
+	 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S',	/* 0x10 - 0x1f */
+	 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V',	/* 0x20 - 0x2f */
+	 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
+	'\r',0xff,0xff
+	};
+
+static unsigned char kbd_ctrl_xlate[] = {
+	0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t',	/* 0x00 - 0x0f */
+	0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13,	/* 0x10 - 0x1f */
+	0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16,	/* 0x20 - 0x2f */
+	0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
+	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
+	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
+	'\r',0xff,0xff
+	};
+
+/******************************************************************
+ * Init
+ ******************************************************************/
+int isa_kbd_init(void)
+{
+	char* result;
+	result=kbd_initialize();
+	if(result==NULL) {
+		PRINTF("AT Keyboard initialized\n");
+		irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
+		isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
+		return (1);
+	}
+	else {
+		printf("%s\n",result);
+		return (-1);
+	}
+}
+
+#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console (void);
+#else
+int overwrite_console (void)
+{
+	return (0);
+}
+#endif
+
+int drv_isa_kbd_init (void)
+{
+	int error;
+  	device_t kbddev ;
+	char *stdinname  = getenv ("stdin");
+
+	if(isa_kbd_init()==-1)
+		return -1;
+  	memset (&kbddev, 0, sizeof(kbddev));
+  	strcpy(kbddev.name, DEVNAME);
+  	kbddev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+  	kbddev.putc = NULL ;
+	kbddev.puts = NULL ;
+	kbddev.getc = kbd_getc ;
+	kbddev.tstc = kbd_testc ;
+
+ 	error = device_register (&kbddev);
+	if(error==0) {
+		/* check if this is the standard input device */
+		if(strcmp(stdinname,DEVNAME)==0) {
+			/* reassign the console */
+			if(overwrite_console()) {
+				return 1;
+			}
+			error=console_assign(stdin,DEVNAME);
+			if(error==0)
+				return 1;
+			else
+				return error;
+		}
+		return 1;
+	}
+	return error;
+}
+
+/******************************************************************
+ * Queue handling
+ ******************************************************************/
+/* puts character in the queue and sets up the in and out pointer */
+void kbd_put_queue(char data)
+{
+	if((in_pointer+1)==KBD_BUFFER_LEN) {
+		if(out_pointer==0) {
+			return; /* buffer full */
+		} else{
+			in_pointer=0;
+		}
+	} else {
+		if((in_pointer+1)==out_pointer)
+			return; /* buffer full */
+		in_pointer++;
+	}
+	kbd_buffer[in_pointer]=data;
+	return;
+}
+
+/* test if a character is in the queue */
+int kbd_testc(void)
+{
+	if(in_pointer==out_pointer)
+		return(0); /* no data */
+	else
+		return(1);
+}
+/* gets the character from the queue */
+int kbd_getc(void)
+{
+	char c;
+	while(in_pointer==out_pointer);
+	if((out_pointer+1)==KBD_BUFFER_LEN)
+		out_pointer=0;
+	else
+		out_pointer++;
+	c=kbd_buffer[out_pointer];
+	return (int)c;
+
+}
+
+
+/* set LEDs */
+
+void kbd_set_leds(void)
+{
+	if(caps_lock==0)
+		leds&=~LED_CAP; /* switch caps_lock off */
+	else
+		leds|=LED_CAP; /* switch on LED */
+	if(num_lock==0)
+		leds&=~LED_NUM; /* switch LED off */
+	else
+		leds|=LED_NUM;  /* switch on LED */
+	if(scroll_lock==0)
+		leds&=~LED_SCR; /* switch LED off */
+	else
+		leds|=LED_SCR; /* switch on LED */
+	kbd_send_data(KBD_CMD_SET_LEDS);
+	kbd_send_data(leds);
+}
+
+
+void handle_keyboard_event(unsigned char scancode)
+{
+	unsigned char keycode;
+
+	/*  Convert scancode to keycode */
+	PRINTF("scancode %x\n",scancode);
+	if(scancode==0xe0) {
+		e0=1; /* special charakters */
+		return;
+	}
+	if(e0==1) {
+		e0=0; /* delete flag */
+		if(!(	((scancode&0x7F)==0x38)|| /* the right ctrl key */
+					((scancode&0x7F)==0x1D)|| /* the right alt key */
+					((scancode&0x7F)==0x35)||	/* the right '/' key */
+					((scancode&0x7F)==0x1C) ))  /* the right enter key */
+			/* we swallow unknown e0 codes */
+			return;
+	}
+	/* special cntrl keys */
+	switch(scancode)
+	{
+		case 0x2A:
+		case 0x36: /* shift pressed */
+			shift=1;
+			return; /* do nothing else */
+		case 0xAA:
+		case 0xB6: /* shift released */
+			shift=0;
+			return; /* do nothing else */
+		case 0x38: /* alt pressed */
+			alt=1;
+			return; /* do nothing else */
+		case 0xB8: /* alt released */
+			alt=0;
+			return; /* do nothing else */
+		case 0x1d: /* ctrl pressed */
+			ctrl=1;
+			return; /* do nothing else */
+		case 0x9d: /* ctrl released */
+			ctrl=0;
+			return; /* do nothing else */
+		case 0x46: /* scrollock pressed */
+			scroll_lock=~scroll_lock;
+			kbd_set_leds();
+			return; /* do nothing else */
+		case 0x3A: /* capslock pressed */
+			caps_lock=~caps_lock;
+			kbd_set_leds();
+			return;
+		case 0x45: /* numlock pressed */
+			num_lock=~num_lock;
+			kbd_set_leds();
+			return;
+		case 0xC6: /* scroll lock released */
+		case 0xC5: /* num lock released */
+		case 0xBA: /* caps lock released */
+			return; /* just swallow */
+	}
+	if((scancode&0x80)==0x80) /* key released */
+		return;
+	/* now, decide which table we need */
+	if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
+		PRINTF("unkown scancode %X\n",scancode);
+		return; /* swallow it */
+	}
+	/* setup plain code first */
+	keycode=kbd_plain_xlate[scancode];
+	if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
+		if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
+			PRINTF("unkown caps-locked scancode %X\n",scancode);
+			return; /* swallow it */
+		}
+		keycode=kbd_shift_xlate[scancode];
+		if(keycode<'A') { /* we only want the alphas capital */
+			keycode=kbd_plain_xlate[scancode];
+		}
+	}
+	if(shift==1) { /* shift overwrites caps_lock */
+		if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
+			PRINTF("unkown shifted scancode %X\n",scancode);
+			return; /* swallow it */
+		}
+		keycode=kbd_shift_xlate[scancode];
+	}
+	if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
+		if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
+			PRINTF("unkown ctrl scancode %X\n",scancode);
+			return; /* swallow it */
+		}
+		keycode=kbd_ctrl_xlate[scancode];
+	}
+	/* check if valid keycode */
+	if(keycode==0xff) {
+		PRINTF("unkown scancode %X\n",scancode);
+		return; /* swallow unknown codes */
+	}
+
+	kbd_put_queue(keycode);
+	PRINTF("%x\n",keycode);
+}
+
+/*
+ * This reads the keyboard status port, and does the
+ * appropriate action.
+ *
+ */
+unsigned char handle_kbd_event(void)
+{
+	unsigned char status = kbd_read_status();
+	unsigned int work = 10000;
+
+	while ((--work > 0) && (status & KBD_STAT_OBF)) {
+		unsigned char scancode;
+
+		scancode = kbd_read_input();
+
+		/* Error bytes must be ignored to make the
+		   Synaptics touchpads compaq use work */
+		/* Ignore error bytes */
+		if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
+		{
+			if (status & KBD_STAT_MOUSE_OBF)
+				; /* not supported: handle_mouse_event(scancode); */
+			else
+				handle_keyboard_event(scancode);
+		}
+		status = kbd_read_status();
+	}
+	if (!work)
+		PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
+	return status;
+}
+
+
+/******************************************************************************
+ * Lowlevel Part of keyboard section
+ */
+unsigned char kbd_read_status(void)
+{
+	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
+}
+
+unsigned char kbd_read_input(void)
+{
+	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
+}
+
+void kbd_write_command(unsigned char cmd)
+{
+	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
+}
+
+void kbd_write_output(unsigned char data)
+{
+	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
+}
+
+int kbd_read_data(void)
+{
+	int val;
+	unsigned char status;
+
+	val=-1;
+	status = kbd_read_status();
+	if (status & KBD_STAT_OBF) {
+		val = kbd_read_input();
+		if (status & (KBD_STAT_GTO | KBD_STAT_PERR))
+			val = -2;
+	}
+	return val;
+}
+
+int kbd_wait_for_input(void)
+{
+	unsigned long timeout;
+	int val;
+
+	timeout = KBD_TIMEOUT;
+	val=kbd_read_data();
+	while(val < 0)
+	{
+		if(timeout--==0)
+			return -1;
+		udelay(1000);
+		val=kbd_read_data();
+	}
+	return val;
+}
+
+
+int kb_wait(void)
+{
+	unsigned long timeout = KBC_TIMEOUT * 10;
+
+	do {
+		unsigned char status = handle_kbd_event();
+		if (!(status & KBD_STAT_IBF))
+			return 0; /* ok */
+		udelay(1000);
+		timeout--;
+	} while (timeout);
+	return 1;
+}
+
+void kbd_write_command_w(int data)
+{
+	if(kb_wait())
+		PRINTF("timeout in kbd_write_command_w\n");
+	kbd_write_command(data);
+}
+
+void kbd_write_output_w(int data)
+{
+	if(kb_wait())
+		PRINTF("timeout in kbd_write_output_w\n");
+	kbd_write_output(data);
+}
+
+void kbd_send_data(unsigned char data)
+{
+	unsigned char status;
+	disable_8259A_irq(1); /* disable interrupt */
+	kbd_write_output_w(data);
+	status = kbd_wait_for_input();
+	if (status == KBD_REPLY_ACK)
+		enable_8259A_irq(1); /* enable interrupt */
+}
+
+
+char * kbd_initialize(void)
+{
+	int status;
+
+	in_pointer = 0; /* delete in Buffer */
+	out_pointer = 0;
+	/*
+	 * Test the keyboard interface.
+	 * This seems to be the only way to get it going.
+	 * If the test is successful a x55 is placed in the input buffer.
+	 */
+	kbd_write_command_w(KBD_CCMD_SELF_TEST);
+	if (kbd_wait_for_input() != 0x55)
+		return "Kbd:   failed self test";
+	/*
+	 * Perform a keyboard interface test.  This causes the controller
+	 * to test the keyboard clock and data lines.  The results of the
+	 * test are placed in the input buffer.
+	 */
+	kbd_write_command_w(KBD_CCMD_KBD_TEST);
+	if (kbd_wait_for_input() != 0x00)
+		return "Kbd:   interface failed self test";
+	/*
+	 * Enable the keyboard by allowing the keyboard clock to run.
+	 */
+	kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
+	status = kbd_wait_for_input();
+	/*
+	 * Reset keyboard. If the read times out
+	 * then the assumption is that no keyboard is
+	 * plugged into the machine.
+	 * This defaults the keyboard to scan-code set 2.
+	 *
+	 * Set up to try again if the keyboard asks for RESEND.
+	 */
+	do {
+		kbd_write_output_w(KBD_CMD_RESET);
+		status = kbd_wait_for_input();
+		if (status == KBD_REPLY_ACK)
+			break;
+		if (status != KBD_REPLY_RESEND)
+		{
+			PRINTF("status: %X\n",status);
+			return "Kbd:   reset failed, no ACK";
+		}
+	} while (1);
+	if (kbd_wait_for_input() != KBD_REPLY_POR)
+		return "Kbd:   reset failed, no POR";
+
+	/*
+	 * Set keyboard controller mode. During this, the keyboard should be
+	 * in the disabled state.
+	 *
+	 * Set up to try again if the keyboard asks for RESEND.
+	 */
+	do {
+		kbd_write_output_w(KBD_CMD_DISABLE);
+		status = kbd_wait_for_input();
+		if (status == KBD_REPLY_ACK)
+			break;
+		if (status != KBD_REPLY_RESEND)
+			return "Kbd:   disable keyboard: no ACK";
+	} while (1);
+
+	kbd_write_command_w(KBD_CCMD_WRITE_MODE);
+	kbd_write_output_w(KBD_MODE_KBD_INT
+			      | KBD_MODE_SYS
+			      | KBD_MODE_DISABLE_MOUSE
+			      | KBD_MODE_KCC);
+
+	/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
+	kbd_write_command_w(KBD_CCMD_READ_MODE);
+	if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
+		/*
+		 * If the controller does not support conversion,
+		 * Set the keyboard to scan-code set 1.
+		 */
+		kbd_write_output_w(0xF0);
+		kbd_wait_for_input();
+		kbd_write_output_w(0x01);
+		kbd_wait_for_input();
+	}
+	kbd_write_output_w(KBD_CMD_ENABLE);
+	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+		return "Kbd:   enable keyboard: no ACK";
+
+	/*
+	 * Finally, set the typematic rate to maximum.
+	 */
+	kbd_write_output_w(KBD_CMD_SET_RATE);
+	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+		return "Kbd:   Set rate: no ACK";
+	kbd_write_output_w(0x00);
+	if (kbd_wait_for_input() != KBD_REPLY_ACK)
+		return "Kbd:   Set rate: no ACK";
+	return NULL;
+}
+
+void kbd_interrupt(void)
+{
+	handle_kbd_event();
+}
diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h
new file mode 100755
index 0000000..229ba61
--- /dev/null
+++ b/board/mpl/common/kbd.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _KBD_H_
+#define _KBD_H_
+
+extern int kbd_testc(void);
+extern int kbd_getc(void);
+extern void kbd_interrupt(void);
+extern char *kbd_initialize(void);
+
+unsigned char kbd_is_init(void);
+#define KBD_INTERRUPT 1
+#endif
diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c
new file mode 100755
index 0000000..2c77d37
--- /dev/null
+++ b/board/mpl/common/memtst.c
@@ -0,0 +1,590 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* NOT Used yet...
+  add following code to PIP405.c :
+int testdram (void)
+{
+	unsigned char s[32];
+	int i;
+
+	i = getenv_r ("testmem", s, 32);
+	if (i != 0) {
+		i = (int) simple_strtoul (s, NULL, 10);
+		if ((i > 0) && (i < 0xf)) {
+			printf ("testing ");
+			i = mem_test (0, ramsize, i);
+			if (i > 0)
+				printf ("ERROR ");
+			else
+				printf ("Ok ");
+		}
+	}
+	return (1);
+}
+*/
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <405gp_i2c.h>
+
+#define FALSE           0
+#define TRUE            1
+
+#define TEST_QUIET 			8
+#define TEST_SHOW_PROG 	4
+#define TEST_SHOW_ERR 	2
+#define TEST_SHOW_ALL		1
+
+#define TESTPAT1 0xAA55AA55
+#define TESTPAT2 0x55AA55AA
+#define TEST_PASSED 0
+#define TEST_FAILED 1
+#define MEGABYTE (1024*1024)
+
+
+typedef struct {
+	volatile unsigned long pat1;
+	volatile unsigned long pat2;
+} RAM_MEMTEST_PATTERN2;
+
+typedef struct {
+	volatile unsigned long addr;
+} RAM_MEMTEST_ADDRLINE;
+
+static __inline unsigned long Swap_32 (unsigned long val)
+{
+	return (((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF));
+}
+
+void testm_puts (int quiet, char *buf)
+{
+	if ((quiet & TEST_SHOW_ALL) == TEST_SHOW_ALL)
+		puts (buf);
+}
+
+
+void Write_Error (int mode, unsigned long addr, unsigned long expected,
+				  unsigned long actual)
+{
+
+	char dispbuf[64];
+
+	sprintf (dispbuf, "\n ERROR @ 0x%08lX: (exp: 0x%08lX act: 0x%08lX) ",
+			 addr, expected, actual);
+	testm_puts (((mode & TEST_SHOW_ERR) ==
+				 TEST_SHOW_ERR) ? TEST_SHOW_ALL : mode, dispbuf);
+}
+
+
+/*
+ * fills the memblock of <size> bytes from <startaddr> with pat1 and pat2
+ */
+
+
+void RAM_MemTest_WritePattern2 (unsigned long startaddr,
+								unsigned long size, unsigned long pat1,
+								unsigned long pat2)
+{
+	RAM_MEMTEST_PATTERN2 *p, *pe;
+
+	p = (RAM_MEMTEST_PATTERN2 *) startaddr;
+	pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size);
+
+	while (p < pe) {
+		p->pat1 = pat1;
+		p->pat2 = pat2;
+		p++;
+	}							/* endwhile */
+}
+
+/*
+ * checks the memblock of <size> bytes from <startaddr> with pat1 and pat2
+ * returns the address of the first error or NULL if all is well
+ */
+
+void *RAM_MemTest_CheckPattern2 (int mode, unsigned long startaddr,
+								 unsigned long size, unsigned long pat1,
+								 unsigned long pat2)
+{
+	RAM_MEMTEST_PATTERN2 *p, *pe;
+	unsigned long actual1, actual2;
+
+	p = (RAM_MEMTEST_PATTERN2 *) startaddr;
+	pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size);
+
+	while (p < pe) {
+		actual1 = p->pat1;
+		actual2 = p->pat2;
+
+		if (actual1 != pat1) {
+			Write_Error (mode, (unsigned long) &(p->pat1), pat1, actual1);
+			return ((void *) &(p->pat1));
+		}
+		/* endif */
+		if (actual2 != pat2) {
+			Write_Error (mode, (unsigned long) &(p->pat2), pat2, actual2);
+			return ((void *) &(p->pat2));
+		}
+		/* endif */
+		p++;
+	}							/* endwhile */
+
+	return (NULL);
+}
+
+/*
+ * fills the memblock of <size> bytes from <startaddr> with the address
+ */
+
+void RAM_MemTest_WriteAddrLine (unsigned long startaddr,
+								unsigned long size, int swapped)
+{
+	RAM_MEMTEST_ADDRLINE *p, *pe;
+
+	p = (RAM_MEMTEST_ADDRLINE *) startaddr;
+	pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size);
+
+	if (!swapped) {
+		while (p < pe) {
+			p->addr = (unsigned long) p;
+			p++;
+		}						/* endwhile */
+	} else {
+		while (p < pe) {
+			p->addr = Swap_32 ((unsigned long) p);
+			p++;
+		}						/* endwhile */
+	}							/* endif */
+}
+
+/*
+ * checks the memblock of <size> bytes from <startaddr>
+ * returns the address of the error or NULL if all is well
+ */
+
+void *RAM_MemTest_CheckAddrLine (int mode, unsigned long startaddr,
+								 unsigned long size, int swapped)
+{
+	RAM_MEMTEST_ADDRLINE *p, *pe;
+	unsigned long actual, expected;
+
+	p = (RAM_MEMTEST_ADDRLINE *) startaddr;
+	pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size);
+
+	if (!swapped) {
+		while (p < pe) {
+			actual = p->addr;
+			expected = (unsigned long) p;
+			if (actual != expected) {
+				Write_Error (mode, (unsigned long) &(p->addr), expected,
+							 actual);
+				return ((void *) &(p->addr));
+			}					/* endif */
+			p++;
+		}						/* endwhile */
+	} else {
+		while (p < pe) {
+			actual = p->addr;
+			expected = Swap_32 ((unsigned long) p);
+			if (actual != expected) {
+				Write_Error (mode, (unsigned long) &(p->addr), expected,
+							 actual);
+				return ((void *) &(p->addr));
+			}					/* endif */
+			p++;
+		}						/* endwhile */
+	}							/* endif */
+
+	return (NULL);
+}
+
+/*
+ * checks the memblock of <size> bytes from <startaddr+size>
+ * returns the address of the error or NULL if all is well
+ */
+
+void *RAM_MemTest_CheckAddrLineReverse (int mode, unsigned long startaddr,
+										unsigned long size, int swapped)
+{
+	RAM_MEMTEST_ADDRLINE *p, *pe;
+	unsigned long actual, expected;
+
+	p = (RAM_MEMTEST_ADDRLINE *) (startaddr + size - sizeof (p->addr));
+	pe = (RAM_MEMTEST_ADDRLINE *) startaddr;
+
+	if (!swapped) {
+		while (p > pe) {
+			actual = p->addr;
+			expected = (unsigned long) p;
+			if (actual != expected) {
+				Write_Error (mode, (unsigned long) &(p->addr), expected,
+							 actual);
+				return ((void *) &(p->addr));
+			}					/* endif */
+			p--;
+		}						/* endwhile */
+	} else {
+		while (p > pe) {
+			actual = p->addr;
+			expected = Swap_32 ((unsigned long) p);
+			if (actual != expected) {
+				Write_Error (mode, (unsigned long) &(p->addr), expected,
+							 actual);
+				return ((void *) &(p->addr));
+			}					/* endif */
+			p--;
+		}						/* endwhile */
+	}							/* endif */
+
+	return (NULL);
+}
+
+/*
+ * fills the memblock of <size> bytes from <startaddr> with walking bit pattern
+ */
+
+void RAM_MemTest_WriteWalkBit (unsigned long startaddr, unsigned long size)
+{
+	volatile unsigned long *p, *pe;
+	unsigned long i;
+
+	p = (unsigned long *) startaddr;
+	pe = (unsigned long *) (startaddr + size);
+	i = 0;
+
+	while (p < pe) {
+		*p = 1UL << i;
+		i = (i + 1 + (((unsigned long) p) >> 7)) % 32;
+		p++;
+	}							/* endwhile */
+}
+
+/*
+ * checks the memblock of <size> bytes from <startaddr>
+ * returns the address of the error or NULL if all is well
+ */
+
+void *RAM_MemTest_CheckWalkBit (int mode, unsigned long startaddr,
+								unsigned long size)
+{
+	volatile unsigned long *p, *pe;
+	unsigned long actual, expected;
+	unsigned long i;
+
+	p = (unsigned long *) startaddr;
+	pe = (unsigned long *) (startaddr + size);
+	i = 0;
+
+	while (p < pe) {
+		actual = *p;
+		expected = (1UL << i);
+		if (actual != expected) {
+			Write_Error (mode, (unsigned long) p, expected, actual);
+			return ((void *) p);
+		}						/* endif */
+		i = (i + 1 + (((unsigned long) p) >> 7)) % 32;
+		p++;
+	}							/* endwhile */
+
+	return (NULL);
+}
+
+/*
+ * fills the memblock of <size> bytes from <startaddr> with "random" pattern
+ */
+
+void RAM_MemTest_WriteRandomPattern (unsigned long startaddr,
+									 unsigned long size,
+									 unsigned long *pat)
+{
+	unsigned long i, p;
+
+	p = *pat;
+
+	for (i = 0; i < (size / 4); i++) {
+		*(unsigned long *) (startaddr + i * 4) = p;
+		if ((p % 2) > 0) {
+			p ^= i;
+			p >>= 1;
+			p |= 0x80000000;
+		} else {
+			p ^= ~i;
+			p >>= 1;
+		}						/* endif */
+	}							/* endfor */
+	*pat = p;
+}
+
+/*
+ * checks the memblock of <size> bytes from <startaddr>
+ * returns the address of the error or NULL if all is well
+ */
+
+void *RAM_MemTest_CheckRandomPattern (int mode, unsigned long startaddr,
+									  unsigned long size,
+									  unsigned long *pat)
+{
+	void *perr = NULL;
+	unsigned long i, p, p1;
+
+	p = *pat;
+
+	for (i = 0; i < (size / 4); i++) {
+		p1 = *(unsigned long *) (startaddr + i * 4);
+		if (p1 != p) {
+			if (perr == NULL) {
+				Write_Error (mode, startaddr + i * 4, p, p1);
+				perr = (void *) (startaddr + i * 4);
+			}					/* endif */
+		}
+		/* endif */
+		if ((p % 2) > 0) {
+			p ^= i;
+			p >>= 1;
+			p |= 0x80000000;
+		} else {
+			p ^= ~i;
+			p >>= 1;
+		}						/* endif */
+	}							/* endfor */
+
+	*pat = p;
+	return (perr);
+}
+
+
+void RAM_MemTest_WriteData1 (unsigned long startaddr, unsigned long size,
+							 unsigned long *pat)
+{
+	RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT1, TESTPAT2);
+}
+
+void *RAM_MemTest_CheckData1 (int mode, unsigned long startaddr,
+							  unsigned long size, unsigned long *pat)
+{
+	return (RAM_MemTest_CheckPattern2
+			(mode, startaddr, size, TESTPAT1, TESTPAT2));
+}
+
+void RAM_MemTest_WriteData2 (unsigned long startaddr, unsigned long size,
+							 unsigned long *pat)
+{
+	RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT2, TESTPAT1);
+}
+
+void *RAM_MemTest_CheckData2 (int mode, unsigned long startaddr,
+							  unsigned long size, unsigned long *pat)
+{
+	return (RAM_MemTest_CheckPattern2
+			(mode, startaddr, size, TESTPAT2, TESTPAT1));
+}
+
+void RAM_MemTest_WriteAddr1 (unsigned long startaddr, unsigned long size,
+							 unsigned long *pat)
+{
+	RAM_MemTest_WriteAddrLine (startaddr, size, FALSE);
+}
+
+void *RAM_MemTest_Check1Addr1 (int mode, unsigned long startaddr,
+							   unsigned long size, unsigned long *pat)
+{
+	return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, FALSE));
+}
+
+void *RAM_MemTest_Check2Addr1 (int mode, unsigned long startaddr,
+							   unsigned long size, unsigned long *pat)
+{
+	return (RAM_MemTest_CheckAddrLineReverse
+			(mode, startaddr, size, FALSE));
+}
+
+void RAM_MemTest_WriteAddr2 (unsigned long startaddr, unsigned long size,
+							 unsigned long *pat)
+{
+	RAM_MemTest_WriteAddrLine (startaddr, size, TRUE);
+}
+
+void *RAM_MemTest_Check1Addr2 (int mode, unsigned long startaddr,
+							   unsigned long size, unsigned long *pat)
+{
+	return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, TRUE));
+}
+
+void *RAM_MemTest_Check2Addr2 (int mode, unsigned long startaddr,
+							   unsigned long size, unsigned long *pat)
+{
+	return (RAM_MemTest_CheckAddrLineReverse
+			(mode, startaddr, size, TRUE));
+}
+
+
+typedef struct {
+	void (*test_write) (unsigned long startaddr, unsigned long size,
+						unsigned long *pat);
+	char *test_write_desc;
+	void *(*test_check1) (int mode, unsigned long startaddr,
+						  unsigned long size, unsigned long *pat);
+	void *(*test_check2) (int mode, unsigned long startaddr,
+						  unsigned long size, unsigned long *pat);
+} RAM_MEMTEST_FUNC;
+
+
+#define TEST_STAGES 5
+static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = {
+	{RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1,
+	 NULL},
+	{RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2,
+	 NULL},
+	{RAM_MemTest_WriteAddr1, "address line test...\n",
+	 RAM_MemTest_Check1Addr1, RAM_MemTest_Check2Addr1},
+	{RAM_MemTest_WriteAddr2, "address line test (swapped)...\n",
+	 RAM_MemTest_Check1Addr2, RAM_MemTest_Check2Addr2},
+	{RAM_MemTest_WriteRandomPattern, "random data test...\n",
+	 RAM_MemTest_CheckRandomPattern, NULL}
+};
+
+void mem_test_reloc(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long addr;
+	int i;
+	for (i=0; i< TEST_STAGES; i++) {
+ 		addr = (ulong) (test_stage[i].test_write) + gd->reloc_off;
+		test_stage[i].test_write=
+			(void (*) (unsigned long startaddr, unsigned long size,
+						unsigned long *pat))addr;
+ 		addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off;
+		test_stage[i].test_write_desc=(char *)addr;
+ 		if(test_stage[i].test_check1) {
+			addr = (ulong) (test_stage[i].test_check1) + gd->reloc_off;
+			test_stage[i].test_check1=
+				(void *(*) (int mode, unsigned long startaddr,
+				 unsigned long size, unsigned long *pat))addr;
+		}
+ 		if(test_stage[i].test_check2) {
+			addr = (ulong) (test_stage[i].test_check2) + gd->reloc_off;
+			test_stage[i].test_check2=
+				(void *(*) (int mode, unsigned long startaddr,
+				 unsigned long size, unsigned long *pat))addr;
+		}
+	}
+}
+
+
+int mem_test (unsigned long start, unsigned long ramsize, int quiet)
+{
+	unsigned long errors, stage;
+	unsigned long startaddr, size, i;
+	const unsigned long blocksize = 0x80000;	/* check in 512KB blocks */
+	unsigned long *perr;
+	unsigned long rdatapat;
+	char dispbuf[80];
+	int status = TEST_PASSED;
+	int prog = 0;
+
+	errors = 0;
+	startaddr = start;
+	size = ramsize;
+	if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
+		prog++;
+		printf (".");
+	}
+	sprintf (dispbuf, "\nMemory Test: addr = 0x%lx size = 0x%lx\n",
+			 startaddr, size);
+	testm_puts (quiet, dispbuf);
+	for (stage = 0; stage < TEST_STAGES; stage++) {
+		sprintf (dispbuf, test_stage[stage].test_write_desc);
+		testm_puts (quiet, dispbuf);
+		/* fill SDRAM */
+		rdatapat = 0x12345678;
+		sprintf (dispbuf, "writing block:     ");
+		testm_puts (quiet, dispbuf);
+		for (i = 0; i < size; i += blocksize) {
+			sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
+			testm_puts (quiet, dispbuf);
+			test_stage[stage].test_write (startaddr + i, blocksize,
+										  &rdatapat);
+		}						/* endfor */
+		sprintf (dispbuf, "\n");
+		testm_puts (quiet, dispbuf);
+		if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
+			prog++;
+			printf (".");
+		}
+		/* check SDRAM */
+		rdatapat = 0x12345678;
+		sprintf (dispbuf, "checking block:     ");
+		testm_puts (quiet, dispbuf);
+		for (i = 0; i < size; i += blocksize) {
+			sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
+			testm_puts (quiet, dispbuf);
+			if ((perr =
+				 test_stage[stage].test_check1 (quiet, startaddr + i,
+												blocksize,
+												&rdatapat)) != NULL) {
+				status = TEST_FAILED;
+			}					/* endif */
+		}						/* endfor */
+		sprintf (dispbuf, "\n");
+		testm_puts (quiet, dispbuf);
+		if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
+			prog++;
+			printf (".");
+		}
+		if (test_stage[stage].test_check2 != NULL) {
+			/* check2 SDRAM */
+			sprintf (dispbuf, "2nd checking block:     ");
+			rdatapat = 0x12345678;
+			testm_puts (quiet, dispbuf);
+			for (i = 0; i < size; i += blocksize) {
+				sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize);
+				testm_puts (quiet, dispbuf);
+				if ((perr =
+					 test_stage[stage].test_check2 (quiet, startaddr + i,
+													blocksize,
+													&rdatapat)) != NULL) {
+					status = TEST_FAILED;
+				}				/* endif */
+			}					/* endfor */
+			sprintf (dispbuf, "\n");
+			testm_puts (quiet, dispbuf);
+			if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
+				prog++;
+				printf (".");
+			}
+		}
+
+	}							/* next stage */
+	if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) {
+		while (prog-- > 0)
+			printf ("\b \b");
+	}
+
+	if (status == TEST_FAILED)
+		errors++;
+
+	return (errors);
+}
diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
new file mode 100755
index 0000000..692930b
--- /dev/null
+++ b/board/mpl/common/pci.c
@@ -0,0 +1,126 @@
+/*-----------------------------------------------------------------------------+
+|
+|       This source code has been made available to you by IBM on an AS-IS
+|       basis.  Anyone receiving this source is licensed under IBM
+|       copyrights to use it in any way he or she deems fit, including
+|       copying it, modifying it, compiling it, and redistributing it either
+|       with or without modifications.  No license under IBM patents or
+|       patent applications is to be implied by the copyright license.
+|
+|       Any user of this software should understand that IBM cannot provide
+|       technical support for this software and will not be responsible for
+|       any consequences resulting from the use of this software.
+|
+|       Any person who transfers this source code or any derivative work
+|       must include the IBM copyright notice, this paragraph, and the
+|       preceding two paragraphs in the transferred software.
+|
+|       COPYRIGHT   I B M   CORPORATION 1995
+|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++-----------------------------------------------------------------------------*/
+/*
+ * Adapted for PIP405 03.07.01
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * TODO: Clean-up
+ */
+
+#include <common.h>
+#include <pci.h>
+#include "isa.h"
+
+#ifdef CONFIG_405GP
+#ifdef CONFIG_PCI
+
+#undef DEBUG
+
+#include "piix4_pci.h"
+#include "pci_parts.h"
+
+void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
+			   struct pci_config_table *entry)
+{
+	struct pci_pip405_config_entry *table;
+	int i;
+
+	table = (struct pci_pip405_config_entry*) entry->priv[0];
+
+	for (i=0; table[i].width; i++)
+	{
+#ifdef DEBUG
+		printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
+		       table[i].index, table[i].val, table[i].width);
+#endif
+
+		switch(table[i].width)
+		{
+		case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break;
+		case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break;
+		case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break;
+		}
+	}
+}
+
+
+static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char int_line = 0xff;
+	unsigned char pin;
+	/*
+	 * Write pci interrupt line register
+	 */
+	if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */
+		return;
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
+	if ((pin == 0) || (pin > 4))
+	    return;
+
+	int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+#ifdef DEBUG
+	printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
+	       PCI_DEV(dev),dev,int_line,int_line);
+#endif
+}
+
+extern void pci_405gp_init(struct pci_controller *hose);
+
+
+static struct pci_controller hose = {
+  config_table: pci_pip405_config_table,
+  fixup_irq: pci_pip405_fixup_irq,
+};
+
+
+static void reloc_pci_cfg_table(struct pci_config_table *table)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long addr;
+
+	for (; table && table->vendor; table++) {
+ 		addr = (ulong) (table->config_device) + gd->reloc_off;
+#ifdef DEBUG
+		printf ("device \"%d\": 0x%08lx => 0x%08lx\n",
+				table->device, (ulong) (table->config_device), addr);
+#endif
+		table->config_device =
+			(void (*)(struct pci_controller* hose, pci_dev_t dev,
+			      struct pci_config_table *))addr;
+		table->priv[0]+=gd->reloc_off;
+	}
+}
+
+void pci_init_board(void)
+{
+	/*we want the ptrs to RAM not flash (ie don't use init list)*/
+	hose.fixup_irq    = pci_pip405_fixup_irq;
+	hose.config_table = pci_pip405_config_table;
+	reloc_pci_cfg_table(hose.config_table);
+#ifdef DEBUG
+	printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose);
+#endif
+	pci_405gp_init(&hose);
+}
+
+#endif /* CONFIG_PCI */
+#endif /* CONFIG_405GP */
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
new file mode 100755
index 0000000..60008e2
--- /dev/null
+++ b/board/mpl/common/pci_parts.h
@@ -0,0 +1,193 @@
+ /*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _PCI_PARTS_H_
+#define _PCI_PARTS_H_
+
+
+/* Board specific file containing:
+ * - PCI Memory Mapping
+ * - PCI IO Mapping
+ * - PCI Interrupt Mapping
+ */
+
+/* PIP405 PCI INT Routing:
+ *                      IRQ0  VECTOR
+ * PIXX4 IDSEL  = AD16  INTA#  28 (Function 2 USB is INTD# = 31)
+ * VGA   IDSEL  = AD17  INTB#  29
+ * SCSI  IDSEL  = AD18  INTC#  30
+ * PC104 IDSEL0 = AD20  INTA#  28
+ * PC104 IDSEL1 = AD21  INTB#  29
+ * PC104 IDSEL2 = AD22  INTC#  30
+ * PC104 IDSEL3 = AD23  INTD#  31
+ *
+ * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00
+ *              ^         ^         ^     ^   ^
+ *             31        23        15    10   7
+ * E = Enabled
+ * B = Bussnumber
+ * D = Devicenumber (Device0 = AD10)
+ * F = Functionnumber
+ * R = Registernumber
+ *
+ * Device = (busdevfunc>>11) + 10
+ * Vector = devicenumber % 4 + 28
+ *
+ */
+#define PCI_HIGHEST_ON_BOARD_ID	19
+/*#define PCI_DEV_NUMBER(x)	(((x>>11) & 0x1f) + 10) */
+#define PCI_IRQ_VECTOR(x)	((PCI_DEV(x) + 10) % 4) + 28
+
+
+/* PCI Device List for PIP405 */
+
+/* Mapping:
+ * +-------------+------------+------------+--------------------------------+
+ * ¦ PCI MemAddr | PCI IOAddr | Local Addr | Device / Function              |
+ * +-------------+------------+------------+--------------------------------+
+ * |  0x00000000 |            | 0xA0000000 | ISA Memory (hard wired)        |
+ * |  0x00FFFFFF |            | 0xA0FFFFFF |                                |
+ * +-------------+------------+------------+--------------------------------+
+ * |             | 0x00000000 | 0xE8000000 | ISA IO (hard wired)            |
+ * |             | 0x0000FFFF | 0xE800FFFF |                                |
+ * +-------------+------------+------------+--------------------------------+
+ * |  0x80000000 |            | 0x80000000 | VGA Controller Memory          |
+ * |  0x80FFFFFF |            | 0x80FFFFFF |                                |
+ * +-------------+------------+------------+--------------------------------+
+ * |  0x81000000 |            | 0x81000000 | SCSI Controller Memory         |
+ * |  0x81FFFFFF |            | 0x81FFFFFF |                                |
+ * +-------------+------------+------------+--------------------------------+
+ */
+
+struct pci_pip405_config_entry {
+	int 		index; 	/* address */
+	unsigned long 	val;	/* value */
+	int 		width;	/* data size */
+};
+
+extern void pci_pip405_write_regs(struct pci_controller *,
+				  pci_dev_t,
+				  struct pci_config_table *);
+
+/* PIIX4 ISA Bridge Function 0 */
+static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
+	{PCI_CFG_PIIX4_SERIRQ,	0xD0,		1}, /* enable Continous SERIRQ Pin */
+	{PCI_CFG_PIIX4_GENCFG,	0x00018041,	4}, /* enable SERIRQs, ISA, PNP, GPI11 */
+	{PCI_CFG_PIIX4_TOM,	0xFE,		1}, /* Top of Memory		*/
+	{PCI_CFG_PIIX4_XBCS,	0x02C4,		2}, /* disable all peri CS	*/
+	{PCI_CFG_PIIX4_RTCCFG,	0x21,		1}, /* enable RTC	   	*/
+#if defined(CONFIG_PIP405)
+	{PCI_CFG_PIIX4_MBDMA,	0x82,		1}, /* set MBDMA0 to DMA 2   	*/
+	{PCI_CFG_PIIX4_MBDMA+1,	0x83,		1}, /* set MBDMA1 to DMA 3   	*/
+#endif
+	{PCI_CFG_PIIX4_DLC,	0x0,		1}, /* disable passive release feature */
+	{ }				    	    /* end of device table	*/
+};
+
+/* PIIX4 IDE Controller Function 1 */
+static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
+	{PCI_CFG_PIIX4_BMIBA,	0x0001000,	4}, /* set BMI to a valid address */
+	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
+#if !defined(CONFIG_MIP405T)
+	{PCI_CFG_PIIX4_IDETIM,	0x80008000,	4}, /* enable Both IDE channels	*/
+#else
+	{PCI_CFG_PIIX4_IDETIM,	0x00008000,	4}, /* enable IDE channel0	*/
+#endif
+	{ }					    /* end of device table 	*/
+};
+
+/* PIIX4 USB Controller Function 2 */
+static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
+#if !defined(CONFIG_MIP405T)
+	{PCI_INTERRUPT_LINE,	31,		1}, /* Int vector = 31 		*/
+	{PCI_BASE_ADDRESS_4,	0x0000E001,	4}, /* Set IO Address to 0xe000 to 0xe01F */
+	{PCI_LATENCY_TIMER,	0x80,		1}, /* Latency Timer 0x80 	*/
+	{0xC0,			0x2000,		2}, /* Legacy support 		*/
+	{PCI_COMMAND,		0x0005,		2}, /* enable IO access and Master */
+#endif
+	{ }					    /* end of device table 	*/
+};
+
+/* PIIX4 Power Management Function 3 */
+static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
+	{PCI_CFG_PIIX4_PMBA,	0x00004000,	4}, /* set PMBA to "valid" value */
+	{PCI_CFG_PIIX4_SMBBA,	0x00005000,	4}, /* set SMBBA to "valid" value */
+	{PCI_CFG_PIIX4_PMMISC,	0x01,		1}, /* enable PMBA IO access	*/
+	{PCI_COMMAND,		0x0001,		2}, /* enable IO access 	*/
+	{ }					    /* end of device table 	*/
+};
+/* PPC405 Dummy only used to prevent autosetup on this host bridge */
+static struct pci_pip405_config_entry ppc405_dummy[] = {
+	{ }				    	    /* end of device table 	*/
+};
+
+void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
+			 struct pci_config_table *entry);
+
+
+static struct pci_config_table pci_pip405_config_table[]={
+	{PCI_VENDOR_ID_IBM, 			/* 405 dummy */
+	 PCI_DEVICE_ID_IBM_405GP,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 0,
+	 pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
+
+	{PCI_VENDOR_ID_INTEL, 			/* PIIX4 ISA Bridge Function 0 */
+	 PCI_DEVICE_ID_INTEL_82371AB_0,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 0,
+	 pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}},
+
+	{PCI_VENDOR_ID_INTEL,			/* PIIX4 IDE Controller Function 1 */
+	 PCI_DEVICE_ID_INTEL_82371AB,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 1,
+	 pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}},
+
+	{PCI_VENDOR_ID_INTEL,			/* PIIX4 USB Controller Function 2 */
+	 PCI_DEVICE_ID_INTEL_82371AB_2,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 2,
+	 pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}},
+
+	{PCI_VENDOR_ID_INTEL,			/* PIIX4 USB Controller Function 3 */
+	 PCI_DEVICE_ID_INTEL_82371AB_3,
+	 PCI_ANY_ID,
+	 PCI_ANY_ID, PCI_ANY_ID, 3,
+	 pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}},
+
+	{PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_CLASS_DISPLAY_VGA,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 pci_405gp_setup_vga},
+
+	{PCI_ANY_ID,
+	 PCI_ANY_ID,
+	 PCI_CLASS_NOT_DEFINED_VGA,
+	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 pci_405gp_setup_vga},
+
+	{ }
+};
+#endif /* _PCI_PARTS_H_ */
diff --git a/board/mpl/common/piix4_pci.h b/board/mpl/common/piix4_pci.h
new file mode 100755
index 0000000..0ff802e
--- /dev/null
+++ b/board/mpl/common/piix4_pci.h
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _PIIX4_PCI_H
+#define _PIIX4_PCI_H
+
+/***************************************************************************
+* Defines PIIX4 Config Registers
+****************************************************************************/
+
+/* Function 0 ISA Bridge */
+#define	PCI_CFG_PIIX4_IORT		0x4C	/* 8 bit ISA Recovery Timer Reg (default 0x4D) */
+#define	PCI_CFG_PIIX4_XBCS		0x4E	/* 16 bit XBus Chip select reg (default 0x0003) */
+#define	PCI_CFG_PIIX4_PIRQC		0x60  /* PCI IRQ Route Register 4 x 8bit (default )*/
+#define	PCI_CFG_PIIX4_SERIRQ	0x64
+#define	PCI_CFG_PIIX4_TOM			0x69
+#define	PCI_CFG_PIIX4_MSTAT		0x6A
+#define	PCI_CFG_PIIX4_MBDMA		0x76
+#define	PCI_CFG_PIIX4_APICBS	0x80
+#define	PCI_CFG_PIIX4_DLC			0x82
+#define	PCI_CFG_PIIX4_PDMACFG	0x90
+#define	PCI_CFG_PIIX4_DDMABS	0x92
+#define	PCI_CFG_PIIX4_GENCFG	0xB0
+#define	PCI_CFG_PIIX4_RTCCFG	0xCB
+
+/* IO Addresses */
+#define PIIX4_ISA_DMA1_CH0BA	0x00
+#define PIIX4_ISA_DMA1_CH0CA	0x01
+#define PIIX4_ISA_DMA1_CH1BA	0x02
+#define PIIX4_ISA_DMA1_CH1CA	0x03
+#define PIIX4_ISA_DMA1_CH2BA	0x04
+#define PIIX4_ISA_DMA1_CH2CA	0x05
+#define PIIX4_ISA_DMA1_CH3BA	0x06
+#define PIIX4_ISA_DMA1_CH3CA	0x07
+#define PIIX4_ISA_DMA1_CMDST	0x08
+#define PIIX4_ISA_DMA1_REQ		0x09
+#define PIIX4_ISA_DMA1_WSBM		0x0A
+#define PIIX4_ISA_DMA1_CH_MOD	0x0B
+#define PIIX4_ISA_DMA1_CLR_PT	0x0C
+#define PIIX4_ISA_DMA1_M_CLR	0x0D
+#define PIIX4_ISA_DMA1_CLR_M	0x0E
+#define PIIX4_ISA_DMA1_RWAMB	0x0F
+
+#define PIIX4_ISA_DMA2_CH0BA	0xC0
+#define PIIX4_ISA_DMA2_CH0CA	0xC1
+#define PIIX4_ISA_DMA2_CH1BA	0xC2
+#define PIIX4_ISA_DMA2_CH1CA	0xC3
+#define PIIX4_ISA_DMA2_CH2BA	0xC4
+#define PIIX4_ISA_DMA2_CH2CA	0xC5
+#define PIIX4_ISA_DMA2_CH3BA	0xC6
+#define PIIX4_ISA_DMA2_CH3CA	0xC7
+#define PIIX4_ISA_DMA2_CMDST	0xD0
+#define PIIX4_ISA_DMA2_REQ		0xD2
+#define PIIX4_ISA_DMA2_WSBM		0xD4
+#define PIIX4_ISA_DMA2_CH_MOD	0xD6
+#define PIIX4_ISA_DMA2_CLR_PT	0xD8
+#define PIIX4_ISA_DMA2_M_CLR	0xDA
+#define PIIX4_ISA_DMA2_CLR_M	0xDC
+#define PIIX4_ISA_DMA2_RWAMB	0xDE
+
+#define PIIX4_ISA_INT1_ICW1		0x20
+#define PIIX4_ISA_INT1_OCW2		0x20
+#define PIIX4_ISA_INT1_OCW3		0x20
+#define PIIX4_ISA_INT1_ICW2		0x21
+#define PIIX4_ISA_INT1_ICW3		0x21
+#define PIIX4_ISA_INT1_ICW4		0x21
+#define PIIX4_ISA_INT1_OCW1		0x21
+
+#define PIIX4_ISA_INT1_ELCR		0x4D0
+
+#define PIIX4_ISA_INT2_ICW1		0xA0
+#define PIIX4_ISA_INT2_OCW2		0xA0
+#define PIIX4_ISA_INT2_OCW3		0xA0
+#define PIIX4_ISA_INT2_ICW2		0xA1
+#define PIIX4_ISA_INT2_ICW3		0xA1
+#define PIIX4_ISA_INT2_ICW4		0xA1
+#define PIIX4_ISA_INT2_OCW1		0xA1
+#define PIIX4_ISA_INT2_IMR		0xA1 /* read only */
+
+#define PIIX4_ISA_INT2_ELCR		0x4D1
+
+#define PIIX4_ISA_TMR0_CNT_ST	0x40
+#define PIIX4_ISA_TMR1_CNT_ST	0x41
+#define PIIX4_ISA_TMR2_CNT_ST	0x42
+#define PIIX4_ISA_TMR_TCW			0x43
+
+#define PIIX4_ISA_RST_XBUS		0x60
+
+#define PIIX4_ISA_NMI_CNT_ST	0x61
+#define PIIX4_ISA_NMI_ENABLE	0x70
+
+#define PIIX4_ISA_RTC_INDEX		0x70
+#define PIIX4_ISA_RTC_DATA		0x71
+#define PIIX4_ISA_RTCEXT_IND	0x70
+#define PIIX4_ISA_RTCEXT_DATA	0x71
+
+#define PIIX4_ISA_DMA1_CH2LPG	0x81
+#define PIIX4_ISA_DMA1_CH3LPG	0x82
+#define PIIX4_ISA_DMA1_CH1LPG	0x83
+#define PIIX4_ISA_DMA1_CH0LPG	0x87
+#define PIIX4_ISA_DMA2_CH2LPG	0x89
+#define PIIX4_ISA_DMA2_CH3LPG	0x8A
+#define PIIX4_ISA_DMA2_CH1LPG	0x8B
+#define PIIX4_ISA_DMA2_LPGRFR	0x8F
+
+#define PIIX4_ISA_PORT_92			0x92
+
+#define PIIX4_ISA_APM_CONTRL	0xB2
+#define PIIX4_ISA_APM_STATUS	0xB3
+
+#define PIIX4_ISA_COCPU_ERROR	0xF0
+
+/* Function 1 IDE Controller */
+#define	PCI_CFG_PIIX4_BMIBA		0x20
+#define	PCI_CFG_PIIX4_IDETIM	0x40
+#define	PCI_CFG_PIIX4_SIDETIM	0x44
+#define	PCI_CFG_PIIX4_UDMACTL	0x48
+#define	PCI_CFG_PIIX4_UDMATIM 0x4A
+
+/* Function 2 USB Controller */
+#define	PCI_CFG_PIIX4_SBRNUM	0x60
+#define	PCI_CFG_PIIX4_LEGSUP	0xC0
+
+/* Function 3 Power Management */
+#define	PCI_CFG_PIIX4_PMBA		0x40
+#define	PCI_CFG_PIIX4_CNTA		0x44
+#define	PCI_CFG_PIIX4_CNTB		0x48
+#define	PCI_CFG_PIIX4_GPICTL	0x4C
+#define	PCI_CFG_PIIX4_DEVRESD	0x50
+#define	PCI_CFG_PIIX4_DEVACTA	0x54
+#define	PCI_CFG_PIIX4_DEVACTB	0x58
+#define	PCI_CFG_PIIX4_DEVRESA	0x5C
+#define	PCI_CFG_PIIX4_DEVRESB	0x60
+#define	PCI_CFG_PIIX4_DEVRESC	0x64
+#define	PCI_CFG_PIIX4_DEVRESE	0x68
+#define	PCI_CFG_PIIX4_DEVRESF	0x6C
+#define	PCI_CFG_PIIX4_DEVRESG	0x70
+#define	PCI_CFG_PIIX4_DEVRESH	0x74
+#define	PCI_CFG_PIIX4_DEVRESI	0x78
+#define	PCI_CFG_PIIX4_PMMISC	0x80
+#define	PCI_CFG_PIIX4_SMBBA	0x90
+
+
+#endif
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
new file mode 100755
index 0000000..84c91c4
--- /dev/null
+++ b/board/mpl/common/usb_uhci.c
@@ -0,0 +1,1169 @@
+/*
+ * Part of this code has been derived from linux:
+ * Universal Host Controller Interface driver for USB (take II).
+ *
+ * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar)
+ *               Deti Fliegl, deti@fliegl.de (executive slave) (lead voice)
+ *               Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader)
+ *               Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter)
+ * (c) 2000      Yggdrasil Computing, Inc. (port of new PCI interface support
+ *               from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
+ * (C) 2000      David Brownell, david-b@pacbell.net (usb-ohci.c)
+ *
+ * HW-initalization based on material of
+ *
+ * (C) Copyright 1999 Linus Torvalds
+ * (C) Copyright 1999 Johannes Erdfelt
+ * (C) Copyright 1999 Randy Dunlap
+ * (C) Copyright 1999 Gregory P. Smith
+ *
+ *
+ * Adapted for U-Boot:
+ * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ */
+
+/**********************************************************************
+ * How it works:
+ * -------------
+ * The framelist / Transfer descriptor / Queue Heads are similar like
+ * in the linux usb_uhci.c.
+ *
+ * During initialization, the following skeleton is allocated in init_skel:
+ *
+ *         framespecific           |           common chain
+ *
+ * framelist[]
+ * [  0 ]-----> TD ---------\
+ * [  1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
+ *   ...        TD ---------/
+ * [1023]-----> TD --------/
+ *
+ *              ^^             ^^         ^^          ^^          ^^
+ *              7 TDs for      1 TD for   Start of    Start of    End Chain
+ *              INT (2-128ms)  1ms-INT    CTRL Chain  BULK Chain
+ *
+ *
+ * Since this is a bootloader, the isochronous transfer descriptor have been removed.
+ *
+ * Interrupt Transfers.
+ * --------------------
+ * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * will be inserted after the appropriate (depending the interval setting) skeleton TD.
+ * If an interrupt has been detected the dev->irqhandler is called. The status and number
+ * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
+ * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
+ * the interrupt TD will be reactivated.
+ *
+ * Control Transfers
+ * -----------------
+ * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ * Bulk Transfers
+ * --------------
+ * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ *
+ */
+
+#include <common.h>
+#include <pci.h>
+
+#ifdef CONFIG_USB_UHCI
+
+#include <usb.h>
+#include "usb_uhci.h"
+
+#define USB_MAX_TEMP_TD      128  /* number of temporary TDs for bulk and control transfers */
+#define USB_MAX_TEMP_INT_TD  32   /* number of temporary TDs for Interrupt transfers */
+
+
+#undef USB_UHCI_DEBUG
+
+#ifdef	USB_UHCI_DEBUG
+#define	USB_UHCI_PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define USB_UHCI_PRINTF(fmt,args...)
+#endif
+
+
+static int irqvec = -1;            /* irq vector, if -1 uhci is stopped / reseted */
+unsigned int usb_base_addr;       /* base address */
+
+static uhci_td_t td_int[8];        /* Interrupt Transfer descriptors */
+static uhci_qh_t qh_cntrl;         /* control Queue Head */
+static uhci_qh_t qh_bulk;          /*  bulk Queue Head */
+static uhci_qh_t qh_end;           /* end Queue Head */
+static uhci_td_t td_last;          /* last TD (linked with end chain) */
+
+/* temporary tds */
+static uhci_td_t tmp_td[USB_MAX_TEMP_TD];          /* temporary bulk/control td's  */
+static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD];  /* temporary interrupt td's  */
+
+static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */
+
+static struct virt_root_hub rh;   /* struct for root hub */
+
+/**********************************************************************
+ * some forward decleration
+ */
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+						void *buffer, int transfer_len,struct devrequest *setup);
+
+/* fill a td with the approproiate data. Link, status, info and buffer
+ * are used by the USB controller itselfes, dev is used to identify the
+ * "connected" device
+ */
+void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status,
+					unsigned long info, unsigned long buffer, unsigned long dev)
+{
+	td->link=swap_32(link);
+	td->status=swap_32(status);
+	td->info=swap_32(info);
+	td->buffer=swap_32(buffer);
+	td->dev_ptr=dev;
+}
+
+/* fill a qh with the approproiate data. Head and element are used by the USB controller
+ * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
+ * Please note, that after completion of the td chain, the entry element is removed /
+ * marked invalid by the USB controller.
+ */
+void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element)
+{
+	qh->head=swap_32(head);
+	qh->element=swap_32(element);
+	qh->dev_ptr=0L;
+}
+
+/* get the status of a td->status
+ */
+unsigned long usb_uhci_td_stat(unsigned long status)
+{
+	unsigned long result=0;
+	result |= (status & TD_CTRL_NAK)      ? USB_ST_NAK_REC : 0;
+	result |= (status & TD_CTRL_STALLED)  ? USB_ST_STALLED : 0;
+	result |= (status & TD_CTRL_DBUFERR)  ? USB_ST_BUF_ERR : 0;
+	result |= (status & TD_CTRL_BABBLE)   ? USB_ST_BABBLE_DET : 0;
+	result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
+	result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
+	result |= (status & TD_CTRL_ACTIVE)   ? USB_ST_NOT_PROC : 0;
+	return result;
+}
+
+/* get the status and the transfered len of a td chain.
+ * called from the completion handler
+ */
+int usb_get_td_status(uhci_td_t *td,struct usb_device *dev)
+{
+	unsigned long temp,info;
+	unsigned long stat;
+	uhci_td_t *mytd=td;
+
+	if(dev->devnum==rh.devnum)
+		return 0;
+	dev->act_len=0;
+	stat=0;
+	do {
+		temp=swap_32((unsigned long)mytd->status);
+		stat=usb_uhci_td_stat(temp);
+		info=swap_32((unsigned long)mytd->info);
+		if(((info & 0xff)!= USB_PID_SETUP) &&
+				(((info >> 21) & 0x7ff)!= 0x7ff) &&
+				(temp & 0x7FF)!=0x7ff)
+		{  /* if not setup and not null data pack */
+			dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */
+		}
+		if(stat) {           /* status no ok */
+			dev->status=stat;
+			return -1;
+		}
+		temp=swap_32((unsigned long)mytd->link);
+		mytd=(uhci_td_t *)(temp & 0xfffffff0);
+	}while((temp & 0x1)==0); /* process all TDs */
+	dev->status=stat;
+	return 0; /* Ok */
+}
+
+
+/*-------------------------------------------------------------------
+ *                         LOW LEVEL STUFF
+ *          assembles QHs und TDs for control, bulk and iso
+ *-------------------------------------------------------------------*/
+
+/* Submits a control message. That is a Setup, Data and Status transfer.
+ * Routine does not wait for completion.
+ */
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+										int transfer_len,struct devrequest *setup)
+{
+	unsigned long destination, status;
+	int maxsze = usb_maxpacket(dev, pipe);
+	unsigned long dataptr;
+	int len;
+	int pktsze;
+	int i=0;
+
+	if (!maxsze) {
+		USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe);
+		return -1;
+	}
+	if(((pipe>>8)&0x7f)==rh.devnum) {
+		/* this is the root hub -> redirect it */
+		return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup);
+	}
+	USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze);
+	/* The "pipe" thing contains the destination in bits 8--18 */
+	destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */
+	/* 3 errors */
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+	/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
+	/*  Build the TD for the control request, try forever, 8 bytes of data */
+	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev);
+#if 0
+	{
+		char *sp=(char *)setup;
+		printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
+		    sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]);
+	}
+#endif
+	dataptr = (unsigned long)buffer;
+	len=transfer_len;
+
+	/* If direction is "send", change the frame from SETUP (0x2D)
+	   to OUT (0xE1). Else change it from SETUP to IN (0x69). */
+	destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN);
+	while (len > 0) {
+		/* data stage */
+		pktsze = len;
+		i++;
+		if (pktsze > maxsze)
+			pktsze = maxsze;
+		destination ^= 1 << TD_TOKEN_TOGGLE;	/* toggle DATA0/1 */
+		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
+		tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
+
+		dataptr += pktsze;
+		len -= pktsze;
+	}
+
+	/*  Build the final TD for control status */
+	/* It's only IN if the pipe is out AND we aren't expecting data */
+
+	destination &= ~UHCI_PID;
+	if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0))
+		destination |= USB_PID_IN;
+	else
+		destination |= USB_PID_OUT;
+	destination |= 1 << TD_TOKEN_TOGGLE;	/* End in Data1 */
+	i++;
+	status &=~TD_CTRL_SPD;
+	/* no limit on errors on final packet , 0 bytes of data */
+	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev);
+	tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);	/* queue status td */
+	/*	usb_show_td(i+1);*/
+	USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i);
+	/* first mark the control QH element terminated */
+	qh_cntrl.element=0xffffffffL;
+	/* set qh active */
+	qh_cntrl.dev_ptr=(unsigned long)dev;
+	/* fill in tmp_td_chain */
+	qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]);
+	return 0;
+}
+
+/*-------------------------------------------------------------------
+ * Prepare TDs for bulk transfers.
+ */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len)
+{
+	unsigned long destination, status,info;
+	unsigned long dataptr;
+	int maxsze = usb_maxpacket(dev, pipe);
+	int len;
+	int i=0;
+
+	if(transfer_len < 0) {
+		printf("Negative transfer length in submit_bulk\n");
+		return -1;
+	}
+	if (!maxsze)
+		return -1;
+	/* The "pipe" thing contains the destination in bits 8--18. */
+	destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe);
+	/* 3 errors */
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+	/*	((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
+	/* Build the TDs for the bulk request */
+	len = transfer_len;
+	dataptr = (unsigned long)buffer;
+	do {
+		int pktsze = len;
+		if (pktsze > maxsze)
+			pktsze = maxsze;
+		/* pktsze bytes of data  */
+		info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) |
+			(usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE);
+
+		if((len-pktsze)==0)
+			status |= TD_CTRL_IOC;	/* last one generates INT */
+
+		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
+		if(i>0)
+			tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
+		i++;
+		dataptr += pktsze;
+		len -= pktsze;
+		usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+	} while (len > 0);
+	/* first mark the bulk QH element terminated */
+	qh_bulk.element=0xffffffffL;
+	/* set qh active */
+	qh_bulk.dev_ptr=(unsigned long)dev;
+	/* fill in tmp_td_chain */
+	qh_bulk.element=swap_32((unsigned long)&tmp_td[0]);
+	return 0;
+}
+
+
+/* search a free interrupt td
+ */
+uhci_td_t *uhci_alloc_int_td(void)
+{
+	int i;
+	for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
+		if(tmp_int_td[i].dev_ptr==0) /* no device assigned -> free TD */
+			return &tmp_int_td[i];
+	}
+	return NULL;
+}
+
+#if 0
+void uhci_show_temp_int_td(void)
+{
+	int i;
+	for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
+		if((tmp_int_td[i].dev_ptr&0x01)!=0x1L) /* no device assigned -> free TD */
+			printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr);
+	}
+	printf("all others temp_tds are free\n");
+}
+#endif
+/*-------------------------------------------------------------------
+ * submits USB interrupt (ie. polling ;-)
+ */
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval)
+{
+	int nint, n;
+	unsigned long status, destination;
+	unsigned long info,tmp;
+	uhci_td_t *mytd;
+	if (interval < 0 || interval >= 256)
+		return -1;
+
+	if (interval == 0)
+		nint = 0;
+	else {
+		for (nint = 0, n = 1; nint <= 8; nint++, n += n)	/* round interval down to 2^n */
+		 {
+			if(interval < n) {
+				interval = n / 2;
+				break;
+			}
+		}
+		nint--;
+	}
+
+	USB_UHCI_PRINTF("Rounded interval to %i, chain  %i\n", interval, nint);
+	mytd=uhci_alloc_int_td();
+	if(mytd==NULL) {
+		printf("No free INT TDs found\n");
+		return -1;
+	}
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
+/*		(urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
+*/
+
+	destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21);
+
+	info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
+	tmp = swap_32(td_int[nint].link);
+	usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev);
+	/* Link it */
+	tmp = swap_32((unsigned long)mytd);
+	td_int[nint].link=tmp;
+
+	usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+
+	return 0;
+}
+
+/**********************************************************************
+ * Low Level functions
+ */
+
+
+void reset_hc(void)
+{
+
+	/* Global reset for 100ms */
+	out16r( usb_base_addr + USBPORTSC1,0x0204);
+	out16r( usb_base_addr + USBPORTSC2,0x0204);
+	out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS);
+	/* Turn off all interrupts */
+	out16r(usb_base_addr + USBINTR,0);
+	wait_ms(50);
+	out16r( usb_base_addr + USBCMD,0);
+	wait_ms(10);
+}
+
+void start_hc(void)
+{
+	int timeout = 1000;
+
+	while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) {
+		if (!--timeout) {
+			printf("USBCMD_HCRESET timed out!\n");
+			break;
+		}
+	}
+	/* Turn on all interrupts */
+	out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP);
+	/* Start at frame 0 */
+	out16r(usb_base_addr + USBFRNUM,0);
+	/* set Framebuffer base address */
+	out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist);
+	/* Run and mark it configured with a 64-byte max packet */
+	out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
+}
+
+/* Initialize the skeleton
+ */
+void usb_init_skel(void)
+{
+	unsigned long temp;
+	int n;
+
+	for(n=0;n<USB_MAX_TEMP_INT_TD;n++)
+		tmp_int_td[n].dev_ptr=0L; /* no devices connected */
+	/* last td */
+	usb_fill_td(&td_last,UHCI_PTR_TERM,TD_CTRL_IOC ,0,0,0L);
+  /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */
+	/* End Queue Header */
+	usb_fill_qh(&qh_end,UHCI_PTR_TERM,(unsigned long)&td_last);
+	/* Bulk Queue Header */
+	temp=(unsigned long)&qh_end;
+	usb_fill_qh(&qh_bulk,temp | UHCI_PTR_QH,UHCI_PTR_TERM);
+	/* Control Queue Header */
+	temp=(unsigned long)&qh_bulk;
+	usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH,UHCI_PTR_TERM);
+	/* 1ms Interrupt td */
+	temp=(unsigned long)&qh_cntrl;
+	usb_fill_td(&td_int[0],temp | UHCI_PTR_QH,0,0,0,0L);
+	temp=(unsigned long)&td_int[0];
+	for(n=1; n<8; n++)
+		usb_fill_td(&td_int[n],temp,0,0,0,0L);
+	for (n = 0; n < 1024; n++) {
+	/* link all framelist pointers to one of the interrupts */
+		int m, o;
+		if ((n&127)==127)
+			framelist[n]= swap_32((unsigned long)&td_int[0]);
+		else
+			for (o = 1, m = 2; m <= 128; o++, m += m)
+				if ((n & (m - 1)) == ((m - 1) / 2))
+						framelist[n]= swap_32((unsigned long)&td_int[o]);
+	}
+}
+
+/* check the common skeleton for completed transfers, and update the status
+ * of the "connected" device. Called from the IRQ routine.
+ */
+void usb_check_skel(void)
+{
+	struct usb_device *dev;
+	/* start with the control qh */
+	if(qh_cntrl.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
+	{
+		dev=(struct usb_device *)qh_cntrl.dev_ptr;
+		usb_get_td_status(&tmp_td[0],dev); /* update status */
+		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+			qh_cntrl.dev_ptr=0;
+		}
+	}
+	/* now process the bulk */
+	if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
+	{
+		dev=(struct usb_device *)qh_bulk.dev_ptr;
+		usb_get_td_status(&tmp_td[0],dev); /* update status */
+		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+			qh_bulk.dev_ptr=0;
+		}
+	}
+}
+
+/* check the interrupt chain, ubdate the status of the appropriate device,
+ * call the appropriate irqhandler and reactivate the TD if the irqhandler
+ * returns with 1
+ */
+void usb_check_int_chain(void)
+{
+	int i,res;
+	unsigned long link,status;
+	struct usb_device *dev;
+	uhci_td_t *td,*prevtd;
+
+	for(i=0;i<8;i++) {
+		prevtd=&td_int[i]; /* the first previous td is the skeleton td */
+		link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
+		td=(uhci_td_t *)link; /* assign it */
+		/* all interrupt TDs are finally linked to the td_int[0].
+ 		 * so we process all until we find the td_int[0].
+		 * if int0 chain points to a QH, we're also done
+	   */
+		while(((i>0) && (link != (unsigned long)&td_int[0])) ||
+					((i==0) && !(swap_32(td->link) &  UHCI_PTR_QH)))
+		{
+			/* check if a device is assigned with this td */
+			status=swap_32(td->status);
+			if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) {
+				/* td is not active and a device is assigned -> call irqhandler */
+				dev=(struct usb_device *)td->dev_ptr;
+				dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */
+				dev->irq_status=usb_uhci_td_stat(status); /* get status */
+				res=dev->irq_handle(dev); /* call irqhandler */
+				if(res==1) {
+					/* reactivate */
+					status|=TD_CTRL_ACTIVE;
+					td->status=swap_32(status);
+					prevtd=td; /* previous td = this td */
+				}
+				else {
+					prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */
+					/* remove device pointer */
+					td->dev_ptr=0L;
+				}
+			} /* if we call the irq handler */
+			link=swap_32(td->link) & 0xfffffff0; /* next in chain */
+			td=(uhci_td_t *)link; /* assign it */
+		} /* process all td in this int chain */
+	} /* next interrupt chain */
+}
+
+
+/* usb interrupt service routine.
+ */
+void handle_usb_interrupt(void)
+{
+	unsigned short status;
+
+	/*
+	 * Read the interrupt status, and write it back to clear the
+	 * interrupt cause
+	 */
+
+	status = in16r(usb_base_addr + USBSTS);
+
+	if (!status)		/* shared interrupt, not mine */
+		return;
+	if (status != 1) {
+		/* remove host controller halted state */
+		if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) {
+			out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD));
+		}
+	}
+	usb_check_int_chain(); /* call interrupt handlers for int tds */
+	usb_check_skel(); /* call completion handler for common transfer routines */
+	out16r(usb_base_addr+USBSTS,status);
+}
+
+
+/* init uhci
+ */
+int usb_lowlevel_init(void)
+{
+	unsigned char temp;
+	int	busdevfunc;
+
+	busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */
+	if(busdevfunc==-1) {
+		printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID);
+		return -1;
+	}
+	pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp);
+	irqvec = temp;
+	irq_free_handler(irqvec);
+	USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec);
+	pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp);
+	USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp);
+	pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
+	USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
+	usb_base_addr&=0xFFFFFFF0;
+	usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS;
+	rh.devnum = 0;
+	usb_init_skel();
+	reset_hc();
+	start_hc();
+	irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL);
+	return 0;
+}
+
+/* stop uhci
+ */
+int usb_lowlevel_stop(void)
+{
+	if(irqvec==-1)
+		return 1;
+	irq_free_handler(irqvec);
+	reset_hc();
+	irqvec=-1;
+	return 0;
+}
+
+/*******************************************************************************************
+ * Virtual Root Hub
+ * Since the uhci does not have a real HUB, we simulate one ;-)
+ */
+#undef	USB_RH_DEBUG
+
+#ifdef	USB_RH_DEBUG
+#define	USB_RH_PRINTF(fmt,args...)	printf (fmt ,##args)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex);
+static void usb_display_Req(unsigned short req);
+#else
+#define USB_RH_PRINTF(fmt,args...)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {}
+static void usb_display_Req(unsigned short req) {}
+#endif
+
+static unsigned char root_hub_dev_des[] =
+{
+	0x12,			/*  __u8  bLength; */
+	0x01,			/*  __u8  bDescriptorType; Device */
+	0x00,			/*  __u16 bcdUSB; v1.0 */
+	0x01,
+	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  bDeviceSubClass; */
+	0x00,			/*  __u8  bDeviceProtocol; */
+	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,			/*  __u16 idVendor; */
+	0x00,
+	0x00,			/*  __u16 idProduct; */
+	0x00,
+	0x00,			/*  __u16 bcdDevice; */
+	0x00,
+	0x01,			/*  __u8  iManufacturer; */
+	0x00,			/*  __u8  iProduct; */
+	0x00,			/*  __u8  iSerialNumber; */
+	0x01			/*  __u8  bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static unsigned char root_hub_config_des[] =
+{
+	0x09,			/*  __u8  bLength; */
+	0x02,			/*  __u8  bDescriptorType; Configuration */
+	0x19,			/*  __u16 wTotalLength; */
+	0x00,
+	0x01,			/*  __u8  bNumInterfaces; */
+	0x01,			/*  __u8  bConfigurationValue; */
+	0x00,			/*  __u8  iConfiguration; */
+	0x40,			/*  __u8  bmAttributes;
+				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,			/*  __u8  MaxPower; */
+
+     /* interface */
+	0x09,			/*  __u8  if_bLength; */
+	0x04,			/*  __u8  if_bDescriptorType; Interface */
+	0x00,			/*  __u8  if_bInterfaceNumber; */
+	0x00,			/*  __u8  if_bAlternateSetting; */
+	0x01,			/*  __u8  if_bNumEndpoints; */
+	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  if_bInterfaceSubClass; */
+	0x00,			/*  __u8  if_bInterfaceProtocol; */
+	0x00,			/*  __u8  if_iInterface; */
+
+     /* endpoint */
+	0x07,			/*  __u8  ep_bLength; */
+	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
+	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
+	0x08,			/*  __u16 ep_wMaxPacketSize; 8 Bytes */
+	0x00,
+	0xff			/*  __u8  ep_bInterval; 255 ms */
+};
+
+
+static unsigned char root_hub_hub_des[] =
+{
+	0x09,			/*  __u8  bLength; */
+	0x29,			/*  __u8  bDescriptorType; Hub-descriptor */
+	0x02,			/*  __u8  bNbrPorts; */
+	0x00,			/* __u16  wHubCharacteristics; */
+	0x00,
+	0x01,			/*  __u8  bPwrOn2pwrGood; 2ms */
+	0x00,			/*  __u8  bHubContrCurrent; 0 mA */
+	0x00,			/*  __u8  DeviceRemovable; *** 7 Ports max *** */
+	0xff			/*  __u8  PortPwrCtrlMask; *** 7 ports max *** */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+	28,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'U',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'C',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'I',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+};
+
+
+/*
+ * Root Hub Control Pipe (interrupt Pipes are not supported)
+ */
+
+
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd)
+{
+	void *data = buffer;
+	int leni = transfer_len;
+	int len = 0;
+	int status = 0;
+	int stat = 0;
+	int i;
+
+	unsigned short cstatus;
+
+	unsigned short bmRType_bReq;
+	unsigned short wValue;
+	unsigned short wIndex;
+	unsigned short wLength;
+
+	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+		printf("Root-Hub submit IRQ: NOT implemented\n");
+#if 0
+		uhci->rh.urb = urb;
+		uhci->rh.send = 1;
+		uhci->rh.interval = urb->interval;
+		rh_init_int_timer (urb);
+#endif
+		return 0;
+	}
+	bmRType_bReq = cmd->requesttype | cmd->request << 8;
+	wValue = swap_16(cmd->value);
+	wIndex = swap_16(cmd->index);
+	wLength = swap_16(cmd->length);
+	usb_display_Req(bmRType_bReq);
+	for (i = 0; i < 8; i++)
+		rh.c_p_r[i] = 0;
+	USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n",
+	     dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength);
+
+	switch (bmRType_bReq) {
+		/* Request Destination:
+		   without flags: Device,
+		   RH_INTERFACE: interface,
+		   RH_ENDPOINT: endpoint,
+		   RH_CLASS means HUB here,
+		   RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
+		 */
+
+	case RH_GET_STATUS:
+		*(unsigned short *) data = swap_16(1);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_INTERFACE:
+		*(unsigned short *) data = swap_16(0);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_ENDPOINT:
+		*(unsigned short *) data = swap_16(0);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_CLASS:
+		*(unsigned long *) data = swap_32(0);
+		len=4;
+		break;	/* hub power ** */
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+
+		status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
+		cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
+			((status & USBPORTSC_PEC) >> (3 - 1)) |
+			(rh.c_p_r[wIndex - 1] << (0 + 4));
+		status = (status & USBPORTSC_CCS) |
+			((status & USBPORTSC_PE) >> (2 - 1)) |
+			((status & USBPORTSC_SUSP) >> (12 - 2)) |
+			((status & USBPORTSC_PR) >> (9 - 4)) |
+			(1 << 8) |	/* power on ** */
+			((status & USBPORTSC_LSDA) << (-8 + 9));
+
+		*(unsigned short *) data = swap_16(status);
+		*(unsigned short *) (data + 2) = swap_16(cstatus);
+		len=4;
+		break;
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		switch (wValue) {
+		case (RH_ENDPOINT_STALL):
+			len=0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		switch (wValue) {
+		case (RH_C_HUB_OVER_CURRENT):
+			len=0;	/* hub power over current ** */
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		usb_display_wValue(wValue,wIndex);
+		switch (wValue) {
+		case (RH_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) & ~USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_SUSPEND):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) & ~USBPORTSC_SUSP;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_POWER):
+			len=0;	/* port power ** */
+			break;
+		case (RH_C_PORT_CONNECTION):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_CSC;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_C_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PEC;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_C_PORT_SUSPEND):
+/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
+			len=0;
+			break;
+		case (RH_C_PORT_OVER_CURRENT):
+			len=0;
+			break;
+		case (RH_C_PORT_RESET):
+			rh.c_p_r[wIndex - 1] = 0;
+			len=0;
+			break;
+		}
+		break;
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		usb_display_wValue(wValue,wIndex);
+		switch (wValue) {
+		case (RH_PORT_SUSPEND):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_SUSP;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_RESET):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PR;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			wait_ms(10);
+			status = (status & 0xfff5) & ~USBPORTSC_PR;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			udelay(10);
+			status = (status & 0xfff5) | USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			wait_ms(10);
+			status = (status & 0xfff5) | 0xa;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_POWER):
+			len=0;	/* port power ** */
+			break;
+		case (RH_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		}
+		break;
+
+	case RH_SET_ADDRESS:
+		rh.devnum = wValue;
+		len=0;
+		break;
+	case RH_GET_DESCRIPTOR:
+		switch ((wValue & 0xff00) >> 8) {
+		case (0x01):	/* device descriptor */
+			i=sizeof(root_hub_config_des);
+			status=i > wLength ? wLength : i;
+			len = leni > status ? status : leni;
+			memcpy (data, root_hub_dev_des, len);
+			break;
+		case (0x02):	/* configuration descriptor */
+			i=sizeof(root_hub_config_des);
+			status=i > wLength ? wLength : i;
+			len = leni > status ? status : leni;
+			memcpy (data, root_hub_config_des, len);
+			break;
+		case (0x03):	/*string descriptors */
+			if(wValue==0x0300) {
+				i=sizeof(root_hub_str_index0);
+				status = i > wLength ? wLength : i;
+				len = leni > status ? status : leni;
+				memcpy (data, root_hub_str_index0, len);
+				break;
+			}
+			if(wValue==0x0301) {
+				i=sizeof(root_hub_str_index1);
+				status = i > wLength ? wLength : i;
+				len = leni > status ? status : leni;
+				memcpy (data, root_hub_str_index1, len);
+				break;
+			}
+			stat = USB_ST_STALLED;
+		}
+		break;
+
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		root_hub_hub_des[2] = 2;
+		i=sizeof(root_hub_hub_des);
+		status= i > wLength ? wLength : i;
+		len = leni > status ? status : leni;
+		memcpy (data, root_hub_hub_des, len);
+		break;
+	case RH_GET_CONFIGURATION:
+		*(unsigned char *) data = 0x01;
+		len = 1;
+		break;
+	case RH_SET_CONFIGURATION:
+		len=0;
+		break;
+	default:
+		stat = USB_ST_STALLED;
+	}
+	USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat,
+	     in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2));
+	dev->act_len=len;
+	dev->status=stat;
+	return stat;
+
+}
+
+/********************************************************************************
+ * Some Debug Routines
+ */
+
+#ifdef	USB_RH_DEBUG
+
+static void usb_display_Req(unsigned short req)
+{
+	USB_RH_PRINTF("- Root-Hub Request: ");
+	switch (req) {
+	case RH_GET_STATUS:
+		USB_RH_PRINTF("Get Status ");
+		break;
+	case RH_GET_STATUS | RH_INTERFACE:
+		USB_RH_PRINTF("Get Status Interface ");
+		break;
+	case RH_GET_STATUS | RH_ENDPOINT:
+		USB_RH_PRINTF("Get Status Endpoint ");
+		break;
+	case RH_GET_STATUS | RH_CLASS:
+		USB_RH_PRINTF("Get Status Class");
+		break;	/* hub power ** */
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Get Status Class Others");
+		break;
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		USB_RH_PRINTF("Clear Feature Endpoint ");
+		break;
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		USB_RH_PRINTF("Clear Feature Class ");
+		break;
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Clear Feature Other Class ");
+		break;
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Set Feature Other Class ");
+		break;
+	case RH_SET_ADDRESS:
+		USB_RH_PRINTF("Set Address ");
+		break;
+	case RH_GET_DESCRIPTOR:
+		USB_RH_PRINTF("Get Descriptor ");
+		break;
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		USB_RH_PRINTF("Get Descriptor Class ");
+		break;
+	case RH_GET_CONFIGURATION:
+		USB_RH_PRINTF("Get Configuration ");
+		break;
+	case RH_SET_CONFIGURATION:
+		USB_RH_PRINTF("Get Configuration ");
+		break;
+	default:
+		USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req);
+	}
+	USB_RH_PRINTF("\n");
+
+}
+
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex)
+{
+	switch (wValue) {
+		case (RH_PORT_ENABLE):
+			USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex);
+			break;
+		case (RH_PORT_SUSPEND):
+			USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex);
+			break;
+		case (RH_PORT_POWER):
+			USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex);
+			break;
+		case (RH_C_PORT_CONNECTION):
+			USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_ENABLE):
+			USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_SUSPEND):
+			USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_OVER_CURRENT):
+			USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_RESET):
+			USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex);
+			break;
+		default:
+			USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex);
+			break;
+	}
+}
+
+#endif
+
+
+#ifdef	USB_UHCI_DEBUG
+
+static int usb_display_td(uhci_td_t *td)
+{
+	unsigned long tmp;
+	int valid;
+
+	printf("TD at %p:\n",td);
+
+	tmp=swap_32(td->link);
+	printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0,
+		((tmp & 0x4)==0x4) ? "Depth" : "Breath",
+		((tmp & 0x2)==0x2) ? "QH" : "TD",
+		((tmp & 0x1)==0x1) ? "invalid" : "valid");
+	valid=((tmp & 0x1)==0x0);
+	tmp=swap_32(td->status);
+	printf("     %s %ld Errors %s %s %s \n     %s %s %s %s %s %s\n     Len 0x%lX\n",
+		(((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable",
+		((tmp>>28)&0x3),
+		(((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed",
+		(((tmp>>25)&0x1)==0x1) ? "ISO " : "",
+		(((tmp>>24)&0x1)==0x1) ? "IOC " : "",
+		(((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ",
+		(((tmp>>22)&0x1)==0x1) ? "Stalled" : "",
+		(((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "",
+		(((tmp>>20)&0x1)==0x1) ? "Babble" : "",
+		(((tmp>>19)&0x1)==0x1) ? "NAK" : "",
+		(((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "",
+		(tmp&0x7ff));
+	tmp=swap_32(td->info);
+	printf("     MaxLen 0x%lX\n",((tmp>>21)&0x7FF));
+	printf("     %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "",
+		((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF);
+	tmp=swap_32(td->buffer);
+	printf("     Buffer 0x%08lX\n",tmp);
+	printf("     DEV %08lX\n",td->dev_ptr);
+	return valid;
+}
+
+
+void usb_show_td(int max)
+{
+	int i;
+	if(max>0) {
+		for(i=0;i<max;i++) {
+			usb_display_td(&tmp_td[i]);
+		}
+	}
+	else {
+		i=0;
+		do {
+			printf("tmp_td[%d]\n",i);
+		}while(usb_display_td(&tmp_td[i++]));
+	}
+}
+
+
+#endif
+#endif /* CONFIG_USB_UHCI */
+
+/* EOF */
diff --git a/board/mpl/common/usb_uhci.h b/board/mpl/common/usb_uhci.h
new file mode 100755
index 0000000..af80837
--- /dev/null
+++ b/board/mpl/common/usb_uhci.h
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_UHCI_H_
+#define _USB_UHCI_H_
+
+
+/* Command register */
+#define USBCMD		0
+#define   USBCMD_RS       0x0001	/* Run/Stop */
+#define   USBCMD_HCRESET  0x0002	/* Host reset */
+#define   USBCMD_GRESET   0x0004	/* Global reset */
+#define   USBCMD_EGSM     0x0008	/* Global Suspend Mode */
+#define   USBCMD_FGR      0x0010	/* Force Global Resume */
+#define   USBCMD_SWDBG    0x0020	/* SW Debug mode */
+#define   USBCMD_CF       0x0040	/* Config Flag (sw only) */
+#define   USBCMD_MAXP     0x0080	/* Max Packet (0 = 32, 1 = 64) */
+
+/* Status register */
+#define USBSTS		2
+#define   USBSTS_USBINT   0x0001	/* Interrupt due to IOC */
+#define   USBSTS_ERROR    0x0002	/* Interrupt due to error */
+#define   USBSTS_RD       0x0004	/* Resume Detect */
+#define   USBSTS_HSE      0x0008	/* Host System Error - basically PCI problems */
+#define   USBSTS_HCPE     0x0010	/* Host Controller Process Error - the scripts were buggy */
+#define   USBSTS_HCH      0x0020	/* HC Halted */
+
+/* Interrupt enable register */
+#define USBINTR		4
+#define   USBINTR_TIMEOUT 0x0001	/* Timeout/CRC error enable */
+#define   USBINTR_RESUME  0x0002	/* Resume interrupt enable */
+#define   USBINTR_IOC     0x0004	/* Interrupt On Complete enable */
+#define   USBINTR_SP      0x0008	/* Short packet interrupt enable */
+
+#define USBFRNUM      6
+#define USBFLBASEADD  8
+#define USBSOF        12
+
+/* USB port status and control registers */
+#define USBPORTSC1	16
+#define USBPORTSC2	18
+#define   USBPORTSC_CCS   0x0001	/* Current Connect Status ("device present") */
+#define   USBPORTSC_CSC   0x0002	/* Connect Status Change */
+#define   USBPORTSC_PE    0x0004	/* Port Enable */
+#define   USBPORTSC_PEC   0x0008	/* Port Enable Change */
+#define   USBPORTSC_LS    0x0030	/* Line Status */
+#define   USBPORTSC_RD    0x0040	/* Resume Detect */
+#define   USBPORTSC_LSDA  0x0100	/* Low Speed Device Attached */
+#define   USBPORTSC_PR    0x0200	/* Port Reset */
+#define   USBPORTSC_SUSP  0x1000	/* Suspend */
+
+/* Legacy support register */
+#define USBLEGSUP 0xc0
+#define USBLEGSUP_DEFAULT 0x2000	/* only PIRQ enable set */
+
+#define UHCI_NULL_DATA_SIZE 0x7ff	/* for UHCI controller TD */
+#define UHCI_PID            0xff	/* PID MASK */
+
+#define UHCI_PTR_BITS       0x000F
+#define UHCI_PTR_TERM       0x0001
+#define UHCI_PTR_QH         0x0002
+#define UHCI_PTR_DEPTH      0x0004
+
+/* for TD <status>: */
+#define TD_CTRL_SPD         (1 << 29)	/* Short Packet Detect */
+#define TD_CTRL_C_ERR_MASK  (3 << 27)	/* Error Counter bits */
+#define TD_CTRL_LS          (1 << 26)	/* Low Speed Device */
+#define TD_CTRL_IOS         (1 << 25)	/* Isochronous Select */
+#define TD_CTRL_IOC         (1 << 24)	/* Interrupt on Complete */
+#define TD_CTRL_ACTIVE      (1 << 23)	/* TD Active */
+#define TD_CTRL_STALLED     (1 << 22)	/* TD Stalled */
+#define TD_CTRL_DBUFERR     (1 << 21)	/* Data Buffer Error */
+#define TD_CTRL_BABBLE      (1 << 20)	/* Babble Detected */
+#define TD_CTRL_NAK         (1 << 19)	/* NAK Received */
+#define TD_CTRL_CRCTIMEO    (1 << 18)	/* CRC/Time Out Error */
+#define TD_CTRL_BITSTUFF    (1 << 17)	/* Bit Stuff Error */
+#define TD_CTRL_ACTLEN_MASK 0x7ff	/* actual length, encoded as n - 1 */
+
+#define TD_CTRL_ANY_ERROR	(TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
+				 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
+
+#define TD_TOKEN_TOGGLE		19
+
+/* ------------------------------------------------------------------------------------
+   Virtual Root HUB
+   ------------------------------------------------------------------------------------ */
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+/* Our Vendor Specific feature */
+#define RH_REMOVE_EP               0x00
+
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+
+/* Transfer descriptor structure */
+typedef struct {
+	unsigned long link;     /* next td/qh (LE)*/
+	unsigned long status;   /* status of the td */
+	unsigned long info;     /* Max Lenght / Endpoint / device address and PID */
+	unsigned long buffer;   /* pointer to data buffer (LE) */
+	unsigned long dev_ptr;  /* pointer to the assigned device (BE) */
+	unsigned long res[3];   /* reserved (TDs must be 8Byte aligned) */
+} uhci_td_t, *puhci_td_t;
+
+/* Queue Header structure */
+typedef struct {
+	unsigned long head;       /* Next QH (LE)*/
+	unsigned long element;		/* Queue element pointer (LE) */
+	unsigned long res[5];     /* reserved */
+	unsigned long dev_ptr;    /* if 0 no tds have been assigned to this qh */
+} uhci_qh_t, *puhci_qh_t;
+
+struct virt_root_hub {
+	int devnum;		            /* Address of Root Hub endpoint */
+	int numports;             /* number of ports */
+	int c_p_r[8];             /* C_PORT_RESET */
+};
+
+
+#endif /* _USB_UHCI_H_ */
diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile
new file mode 100755
index 0000000..9276f64
--- /dev/null
+++ b/board/mpl/mip405/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \
+			../common/usb_uhci.o ../common/memtst.o ../common/common_util.o
+
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c
new file mode 100755
index 0000000..6fbc585
--- /dev/null
+++ b/board/mpl/mip405/cmd_mip405.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for MIP405
+ */
+
+#include <common.h>
+#include <command.h>
+#include "mip405.h"
+#include "../common/common_util.h"
+
+
+extern void print_mip405_info(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+
+/* ------------------------------------------------------------------------- */
+
+int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+
+ 	ulong led_on;
+
+	if (strcmp(argv[1], "info") == 0)
+	{
+		print_mip405_info();
+	 	return 0;
+   	}
+ 	if (strcmp(argv[1], "led") == 0)
+	{
+		led_on = (ulong)simple_strtoul(argv[2], NULL, 10);
+		user_led0(led_on);
+		return 0;
+   	}
+	return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+U_BOOT_CMD(
+	mip405,	8,	1,	do_mip405,
+	"mip405  - MIP405 specific Cmds\n",
+	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
+	"mip405 flash mps - updates U-Boot with image from MPS\n"
+	"mip405 info      - displays board information\n"
+	"mip405 led <on>  - switches LED on (on=1) or off (on=0)\n"
+	"mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever\n"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/mip405/config.mk b/board/mpl/mip405/config.mk
new file mode 100755
index 0000000..0f8d153
--- /dev/null
+++ b/board/mpl/mip405/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0xFFF80000
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
new file mode 100755
index 0000000..3351b5b
--- /dev/null
+++ b/board/mpl/mip405/init.S
@@ -0,0 +1,233 @@
+/*------------------------------------------------------------------------------+
+ *
+ *      This source code has been made available to you by IBM on an AS-IS
+ *      basis.  Anyone receiving this source is licensed under IBM
+ *      copyrights to use it in any way he or she deems fit, including
+ *      copying it, modifying it, compiling it, and redistributing it either
+ *      with or without modifications.  No license under IBM patents or
+ *      patent applications is to be implied by the copyright license.
+ *
+ *      Any user of this software should understand that IBM cannot provide
+ *      technical support for this software and will not be responsible for
+ *      any consequences resulting from the use of this software.
+ *
+ *      Any person who transfers this source code or any derivative work
+ *      must include the IBM copyright notice, this paragraph, and the
+ *      preceding two paragraphs in the transferred software.
+ *
+ *      COPYRIGHT   I B M   CORPORATION 1995
+ *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-------------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Function:     ext_bus_cntlr_init
+ * Description:  Initializes the External Bus Controller for the external
+ *		peripherals. IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *	Bank 0 - Flash or Multi Purpose Socket
+ *	Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
+ *	Bank 2 - UART 1 (set in C-Code)
+ *	Bank 3 - UART 2 (set in C-Code)
+ *	Bank 4 - not used
+ *	Bank 5 - not used
+ *	Bank 6 - not used
+ *	Bank 7 - PLD Register
+ *-----------------------------------------------------------------------------*/
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <configs/MIP405.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include "mip405.h"
+
+
+  .globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+  mflr   r4                      /* save link register */
+  mfdcr  r3,strap                /* get strapping reg */
+  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
+  bnelr                          /* jump back if PCI boot */
+
+  bl      ..getAddr
+..getAddr:
+  mflr    r3                      /* get address of ..getAddr */
+  mtlr    r4                      /* restore link register */
+  addi    r4,0,14                 /* set ctr to 14; used to prefetch */
+  mtctr   r4                      /* 14 cache lines to fit this function */
+				   /* in cache (gives us 8x14=112 instrctns) */
+..ebcloop:
+  icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+  addi    r3,r3,32								/* move to next cache line */
+  bdnz    ..ebcloop               /* continue for 14 cache lines */
+
+   /*-------------------------------------------------------------------
+    * Delay to ensure all accesses to ROM are complete before changing
+    * bank 0 timings.
+    *------------------------------------------------------------------- */
+	addis	r3,0,0x0
+  ori     r3,r3,0xA000
+  mtctr   r3
+..spinlp:
+  bdnz    ..spinlp                /* spin loop */
+
+	/*-----------------------------------------------------------------------
+	 * decide boot up mode
+	 *----------------------------------------------------------------------- */
+	addi		r4,0,pb0cr
+	mtdcr		ebccfga,r4
+	mfdcr		r4,ebccfgd
+
+	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
+	beq		0f				/* jump if 8 bit bus width */
+
+	/* setup 16 bit things
+   *-----------------------------------------------------------------------
+   * Memory Bank 0 (16 Bit Flash) initialization
+   *---------------------------------------------------------------------- */
+
+	addi    r4,0,pb0ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,(FLASH_AP_B)@h
+	ori     r4,r4,(FLASH_AP_B)@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(FLASH_CR_B)@h
+	ori     r4,r4,(FLASH_CR_B)@l
+	mtdcr   ebccfgd,r4
+	b				1f
+
+0:
+
+	/* 8Bit boot mode: */
+	/*-----------------------------------------------------------------------
+	* Memory Bank 0 Multi Purpose Socket initialization
+	*----------------------------------------------------------------------- */
+	/* 0x7F8FFE80 slowest boot */
+	addi    r4,0,pb0ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,(MPS_AP_B)@h
+	ori     r4,r4,(MPS_AP_B)@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(MPS_CR_B)@h
+	ori     r4,r4,(MPS_CR_B)@l
+
+	mtdcr   ebccfgd,r4
+
+
+1:
+  /*-----------------------------------------------------------------------
+   * Memory Bank 2-3-4-5-6 (not used) initialization
+   *-----------------------------------------------------------------------*/
+  addi    r4,0,pb1cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb2cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb3cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb4cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb5cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb6cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb7cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+  nop				/* pass2 DCR errata #8 */
+  blr
+
+/*-----------------------------------------------------------------------------
+ * Function:     sdram_init
+ * Description:  Configures the internal SRAM memory. and setup the
+ *               Stackpointer in it.
+ *----------------------------------------------------------------------------- */
+	.globl  sdram_init
+
+sdram_init:
+
+
+  blr
+
+
+#if defined(CONFIG_BOOT_PCI)
+    .section .bootpg,"ax"
+    .globl _start_pci
+/*******************************************
+ */
+
+_start_pci:
+  /* first handle errata #68 / PCI_18 */
+  iccci   r0, r0          /* invalidate I-cache */
+  lis     r31, 0
+  mticcr  r31             /* ICCR = 0 (all uncachable) */
+  isync
+
+  mfccr0  r28             /* set CCR0[24] = 1 */
+  ori     r28, r28, 0x0080
+  mtccr0  r28
+
+  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
+  lis     r28, 0xEF40
+  addi    r28, r28, 0x0004
+  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
+  lis     r29, 0xFFF8     /* open 512 kByte */
+  addi    r29, r29, 0x0001/* and enable this region */
+  stwbrx  r29, r0, r28    /* write PMM0MA */
+
+  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
+  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
+
+  lis     r31, 0x8000     /* set en bit bus 0 */
+  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
+  stwbrx  r31, r0, r28    /* write it */
+
+  lwbrx   r31, r0, r29    /* load XBCS register */
+  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
+  stwbrx  r31, r0, r29    /* write back XBCS register */
+
+  nop
+  nop
+  b	_start		/* normal start */
+#endif
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
new file mode 100755
index 0000000..9c469b0
--- /dev/null
+++ b/board/mpl/mip405/mip405.c
@@ -0,0 +1,820 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * TODO: clean-up
+ */
+
+/*
+ * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
+ *
+ * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
+ * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
+ * parameters from the datasheet are:
+ * Tclk = 7.5ns (CL = 2)
+ * Trp = 15ns
+ * Trc = 60ns
+ * Trcd = 15ns
+ * Trfc = 66ns
+ *
+ * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
+ * period is 10ns and the parameters needed for the Timing Register are:
+ * CASL = CL = 2 clock cycles
+ * PTA = Trp = 15ns / 10ns = 2 clock cycles
+ * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
+ * LDF = 2 clock cycles (but can be extended to meet board-level timing)
+ * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
+ * RCD = Trcd = 15ns / 10ns= 2 clock cycles
+ *
+ * The actual bit settings in the register would be:
+ *
+ * CASL = 0b01
+ * PTA = 0b01
+ * CTP = 0b10
+ * LDF = 0b01
+ * RFTA = 0b011
+ * RCD = 0b01
+ *
+ * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
+ * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
+ * defined as Trc rather than Trfc.
+ * When using DIMM modules, most but not all of the required timing parameters can be read
+ * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
+ * are not available from the EEPROM
+ */
+
+#include <common.h>
+#include "mip405.h"
+#include <asm/processor.h>
+#include <405gp_i2c.h>
+#include <miiphy.h>
+#include "../common/common_util.h"
+#include <i2c.h>
+#include <rtc.h>
+extern block_dev_desc_t * scsi_get_dev(int dev);
+extern block_dev_desc_t * ide_get_dev(int dev);
+
+#undef SDRAM_DEBUG
+#define ENABLE_ECC /* for ecc boards */
+#define FALSE           0
+#define TRUE            1
+
+/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
+#ifndef __ldiv_t_defined
+typedef struct {
+	long int quot;		/* Quotient	*/
+	long int rem;		/* Remainder	*/
+} ldiv_t;
+extern ldiv_t ldiv (long int __numer, long int __denom);
+# define __ldiv_t_defined	1
+#endif
+
+
+#define PLD_PART_REG 		PER_PLD_ADDR + 0
+#define PLD_VERS_REG 		PER_PLD_ADDR + 1
+#define PLD_BOARD_CFG_REG 	PER_PLD_ADDR + 2
+#define PLD_IRQ_REG 		PER_PLD_ADDR + 3
+#define PLD_COM_MODE_REG 	PER_PLD_ADDR + 4
+#define PLD_EXT_CONF_REG 	PER_PLD_ADDR + 5
+
+#define MEGA_BYTE (1024*1024)
+
+typedef struct {
+	unsigned char boardtype; /* Board revision and Population Options */
+	unsigned char cal;		/* cas Latency (will be programmend as cal-1) */
+	unsigned char trp;		/* datain27 in clocks */
+	unsigned char trcd;		/* datain29 in clocks */
+	unsigned char tras;		/* datain30 in clocks */
+	unsigned char tctp;		/* tras - trcd in clocks */
+	unsigned char am;		/* Address Mod (will be programmed as am-1) */
+	unsigned char sz;		/* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
+	unsigned char ecc;		/* if true, ecc is enabled */
+} sdram_t;
+#if defined(CONFIG_MIP405T)
+const sdram_t sdram_table[] = {
+	{ 0x0F,	/* MIP405T Rev A, 64MByte -1 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		2,	/* Address Mode = 2 (12x9x4) */
+		3,	/* size value (32MByte) */
+		0},	/* ECC disabled */
+	{ 0xff, /* terminator */
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff }
+};
+#else
+const sdram_t sdram_table[] = {
+	{ 0x0f,	/* Rev A, 128MByte -1 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		3,	/* Address Mode = 3 */
+		5,	/* size value */
+		1},	/* ECC enabled */
+	{ 0x07,	/* Rev A, 64MByte -2 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		2,	/* Address Mode = 2 */
+		4,	/* size value */
+		1},	/* ECC enabled */
+	{ 0x03,	/* Rev A, 128MByte -4 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		3,	/* Address Mode = 3 */
+		5,	/* size value */
+		1},	/* ECC enabled */
+	{ 0x1f,	/* Rev B, 128MByte -3 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		3,	/* Address Mode = 3 */
+		5,	/* size value */
+		1},	/* ECC enabled */
+	{ 0x2f,	/* Rev C, 128MByte -3 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		3,	/* Address Mode = 3 */
+		5,	/* size value */
+		1},	/* ECC enabled */
+	{ 0xff, /* terminator */
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff }
+};
+#endif /*CONFIG_MIP405T */
+void SDRAM_err (const char *s)
+{
+#ifndef SDRAM_DEBUG
+	DECLARE_GLOBAL_DATA_PTR;
+
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+#endif
+	serial_puts ("\n");
+	serial_puts (s);
+	serial_puts ("\n enable SDRAM_DEBUG for more info\n");
+	for (;;);
+}
+
+
+unsigned char get_board_revcfg (void)
+{
+	out8 (PER_BOARD_ADDR, 0);
+	return (in8 (PER_BOARD_ADDR));
+}
+
+
+#ifdef SDRAM_DEBUG
+
+void write_hex (unsigned char i)
+{
+	char cc;
+
+	cc = i >> 4;
+	cc &= 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+	cc = i & 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+}
+
+void write_4hex (unsigned long val)
+{
+	write_hex ((unsigned char) (val >> 24));
+	write_hex ((unsigned char) (val >> 16));
+	write_hex ((unsigned char) (val >> 8));
+	write_hex ((unsigned char) val);
+}
+
+#endif
+
+
+int init_sdram (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned long	tmp, baseaddr;
+	unsigned short	i;
+	unsigned char	trp_clocks,
+			trcd_clocks,
+			tras_clocks,
+			trc_clocks,
+			tctp_clocks;
+	unsigned char	cal_val;
+	unsigned char	bc;
+	unsigned long	sdram_tim, sdram_bank;
+
+	/*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+	/* set up the pld */
+	mtdcr (ebccfga, pb7ap);
+	mtdcr (ebccfgd, PLD_AP);
+	mtdcr (ebccfga, pb7cr);
+	mtdcr (ebccfgd, PLD_CR);
+	/* THIS IS OBSOLETE */
+	/* set up the board rev reg*/
+	mtdcr (ebccfga, pb5ap);
+	mtdcr (ebccfgd, BOARD_AP);
+	mtdcr (ebccfga, pb5cr);
+	mtdcr (ebccfgd, BOARD_CR);
+#ifdef SDRAM_DEBUG
+	/* get all informations from PLD */
+	serial_puts ("\nPLD Part  0x");
+	bc = in8 (PLD_PART_REG);
+	write_hex (bc);
+	serial_puts ("\nPLD Vers  0x");
+	bc = in8 (PLD_VERS_REG);
+	write_hex (bc);
+	serial_puts ("\nBoard Rev 0x");
+	bc = in8 (PLD_BOARD_CFG_REG);
+	write_hex (bc);
+	serial_puts ("\n");
+#endif
+	/* check board */
+	bc = in8 (PLD_PART_REG);
+#if defined(CONFIG_MIP405T)
+	if((bc & 0x80)==0)
+		SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
+#else
+	if((bc & 0x80)==0x80)
+		SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
+#endif
+	/* set-up the chipselect machine */
+	mtdcr (ebccfga, pb0cr);		/* get cs0 config reg */
+	tmp = mfdcr (ebccfgd);
+	if ((tmp & 0x00002000) == 0) {
+		/* MPS Boot, set up the flash */
+		mtdcr (ebccfga, pb1ap);
+		mtdcr (ebccfgd, FLASH_AP);
+		mtdcr (ebccfga, pb1cr);
+		mtdcr (ebccfgd, FLASH_CR);
+	} else {
+		/* Flash boot, set up the MPS */
+		mtdcr (ebccfga, pb1ap);
+		mtdcr (ebccfgd, MPS_AP);
+		mtdcr (ebccfga, pb1cr);
+		mtdcr (ebccfgd, MPS_CR);
+	}
+	/* set up UART0 (CS2) and UART1 (CS3) */
+	mtdcr (ebccfga, pb2ap);
+	mtdcr (ebccfgd, UART0_AP);
+	mtdcr (ebccfga, pb2cr);
+	mtdcr (ebccfgd, UART0_CR);
+	mtdcr (ebccfga, pb3ap);
+	mtdcr (ebccfgd, UART1_AP);
+	mtdcr (ebccfga, pb3cr);
+	mtdcr (ebccfgd, UART1_CR);
+	bc = in8 (PLD_BOARD_CFG_REG);
+#ifdef SDRAM_DEBUG
+	serial_puts ("\nstart SDRAM Setup\n");
+	serial_puts ("\nBoard Rev: ");
+	write_hex (bc);
+	serial_puts ("\n");
+#endif
+	i = 0;
+	baseaddr = CFG_SDRAM_BASE;
+	while (sdram_table[i].sz != 0xff) {
+		if (sdram_table[i].boardtype == bc)
+			break;
+		i++;
+	}
+	if (sdram_table[i].boardtype != bc)
+		SDRAM_err ("No SDRAM table found for this board!!!\n");
+#ifdef SDRAM_DEBUG
+	serial_puts (" found table ");
+	write_hex (i);
+	serial_puts (" \n");
+#endif
+	/* since the ECC initialisation needs some time,
+	 * we show that we're alive
+	 */
+	if (sdram_table[i].ecc)
+		serial_puts ("\nInitializing SDRAM, Please stand by");
+	cal_val = sdram_table[i].cal - 1;	/* Cas Latency */
+	trp_clocks = sdram_table[i].trp;	/* 20ns / 7.5 ns datain[27] */
+	trcd_clocks = sdram_table[i].trcd;	/* 20ns /7.5 ns (datain[29]) */
+	tras_clocks = sdram_table[i].tras;	/* 44ns /7.5 ns  (datain[30]) */
+	/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
+	tctp_clocks = sdram_table[i].tctp;	/* 44 - 20ns = 24ns */
+	/* trc_clocks is sum of trp_clocks + tras_clocks */
+	trc_clocks = trp_clocks + tras_clocks;
+	/* get SDRAM timing register */
+	mtdcr (memcfga, mem_sdtr1);
+	sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
+	/* insert CASL value */
+	sdram_tim |= ((unsigned long) (cal_val)) << 23;
+	/* insert PTA value */
+	sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
+	/* insert CTP value */
+	sdram_tim |=
+			((unsigned long) (trc_clocks - trp_clocks -
+							  trcd_clocks)) << 16;
+	/* insert LDF (always 01) */
+	sdram_tim |= ((unsigned long) 0x01) << 14;
+	/* insert RFTA value */
+	sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
+	/* insert RCD value */
+	sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
+
+	tmp = ((unsigned long) (sdram_table[i].am - 1) << 13);	/* AM = 3 */
+	/* insert SZ value; */
+	tmp |= ((unsigned long) sdram_table[i].sz << 17);
+	/* get SDRAM bank 0 register */
+	mtdcr (memcfga, mem_mb0cf);
+	sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
+	sdram_bank |= (baseaddr | tmp | 0x01);
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("sdtr: ");
+	write_4hex (sdram_tim);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM timing register */
+	mtdcr (memcfga, mem_sdtr1);
+	mtdcr (memcfgd, sdram_tim);
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("mb0cf: ");
+	write_4hex (sdram_bank);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM bank 0 register */
+	mtdcr (memcfga, mem_mb0cf);
+	mtdcr (memcfgd, sdram_bank);
+
+	if (get_bus_freq (tmp) > 110000000) {	/* > 110MHz */
+		/* get SDRAM refresh interval register */
+		mtdcr (memcfga, mem_rtr);
+		tmp = mfdcr (memcfgd) & ~0x3FF80000;
+		tmp |= 0x07F00000;
+	} else {
+		/* get SDRAM refresh interval register */
+		mtdcr (memcfga, mem_rtr);
+		tmp = mfdcr (memcfgd) & ~0x3FF80000;
+		tmp |= 0x05F00000;
+	}
+	/* write SDRAM refresh interval register */
+	mtdcr (memcfga, mem_rtr);
+	mtdcr (memcfgd, tmp);
+	/* enable ECC if used */
+#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
+	if (sdram_table[i].ecc) {
+		/* disable checking for all banks */
+		unsigned long	*p;
+#ifdef SDRAM_DEBUG
+		serial_puts ("disable ECC.. ");
+#endif
+		mtdcr (memcfga, mem_ecccf);
+		tmp = mfdcr (memcfgd);
+		tmp &= 0xff0fffff;		/* disable all banks */
+		mtdcr (memcfga, mem_ecccf);
+		/* set up SDRAM Controller with ECC enabled */
+#ifdef SDRAM_DEBUG
+		serial_puts ("setup SDRAM Controller.. ");
+#endif
+		mtdcr (memcfgd, tmp);
+		mtdcr (memcfga, mem_mcopt1);
+		tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
+		mtdcr (memcfga, mem_mcopt1);
+		mtdcr (memcfgd, tmp);
+		udelay (600);
+#ifdef SDRAM_DEBUG
+		serial_puts ("fill the memory..\n");
+#endif
+		serial_puts (".");
+		/* now, fill all the memory */
+		tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
+		p = (unsigned long) 0;
+		while ((unsigned long) p < tmp) {
+			*p++ = 0L;
+			if (!((unsigned long) p % 0x00800000))	/* every 8MByte */
+				serial_puts (".");
+		}
+		/* enable bank 0 */
+		serial_puts (".");
+#ifdef SDRAM_DEBUG
+		serial_puts ("enable ECC\n");
+#endif
+		udelay (400);
+		mtdcr (memcfga, mem_ecccf);
+		tmp = mfdcr (memcfgd);
+		tmp |= 0x00800000;		/* enable bank 0 */
+		mtdcr (memcfgd, tmp);
+		udelay (400);
+	} else
+#endif
+	{
+		/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
+		mtdcr (memcfga, mem_mcopt1);
+		tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
+		mtdcr (memcfga, mem_mcopt1);
+		mtdcr (memcfgd, tmp);
+		udelay (400);
+	}
+	serial_puts ("\n");
+	return (0);
+}
+
+int board_early_init_f (void)
+{
+	init_sdram ();
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the PIP405 board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
+   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
+   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for MIP405 board:
+   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that
+   |       the Interrupt Controller in the South Bridge has caused the
+   |       interrupt. The IC must be read to determine which device
+   |       caused the interrupt.
+   |
+   +-------------------------------------------------------------------------*/
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical (for now) */
+	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	return 0;
+}
+
+
+/*
+ * Get some PLD Registers
+ */
+
+unsigned short get_pld_parvers (void)
+{
+	unsigned short result;
+	unsigned char rc;
+
+	rc = in8 (PLD_PART_REG);
+	result = (unsigned short) rc << 8;
+	rc = in8 (PLD_VERS_REG);
+	result |= rc;
+	return result;
+}
+
+
+void user_led0 (unsigned char on)
+{
+	if (on)
+		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
+	else
+		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
+}
+
+
+void ide_set_reset (int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	if (idereset)
+		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
+	else {
+		udelay (10000);
+		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
+	}
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
+{
+#if !defined(CONFIG_MIP405T)
+	unsigned char bc,rc,tmp;
+	int i;
+
+	bc = in8 (PLD_BOARD_CFG_REG);
+	tmp = ~bc;
+	tmp &= 0xf;
+	rc = 0;
+	for (i = 0; i < 4; i++) {
+		rc <<= 1;
+		rc += (tmp & 0x1);
+		tmp >>= 1;
+	}
+	rc++;
+	if((  (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
+	   || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
+		&& (rc==0x1))     /* Population Option 1 is a -3 */
+		rc=3;
+	*pcbrev=(bc >> 4) & 0xf;
+	*var=rc;
+#else
+	unsigned char bc;
+	bc = in8 (PLD_BOARD_CFG_REG);
+	*pcbrev=(bc >> 4) & 0xf;
+	*var=16-(bc & 0xf);
+#endif
+}
+
+/*
+ * Check Board Identity:
+ */
+/* serial String: "MIP405_1000" OR "MIP405T_1000" */
+#if !defined(CONFIG_MIP405T)
+#define BOARD_NAME	"MIP405"
+#else
+#define BOARD_NAME	"MIP405T"
+#endif
+
+int checkboard (void)
+{
+	char s[50];
+	unsigned char bc, var;
+	int i;
+	backup_t *b = (backup_t *) s;
+
+	puts ("Board: ");
+	get_pcbrev_var(&bc,&var);
+	i = getenv_r ("serial#", (char *)s, 32);
+	if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
+		get_backup_values (b);
+		if (strncmp (b->signature, "MPL\0", 4) != 0) {
+			puts ("### No HW ID - assuming " BOARD_NAME);
+			printf ("-%d Rev %c", var, 'A' + bc);
+		} else {
+			b->serial_name[sizeof(BOARD_NAME)-1] = 0;
+			printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
+					'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
+		}
+	} else {
+		s[sizeof(BOARD_NAME)-1] = 0;
+		printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
+				&s[sizeof(BOARD_NAME)]);
+	}
+	bc = in8 (PLD_EXT_CONF_REG);
+	printf (" Boot Config: 0x%x\n", bc);
+	return (0);
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+/*
+  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  the necessary info for SDRAM controller configuration
+*/
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+static int test_dram (unsigned long ramsize);
+
+long int initdram (int board_type)
+{
+
+	unsigned long bank_reg[4], tmp, bank_size;
+	int i, ds;
+	unsigned long TotalSize;
+
+	ds = 0;
+	/* since the DRAM controller is allready set up, calculate the size with the
+	   bank registers    */
+	mtdcr (memcfga, mem_mb0cf);
+	bank_reg[0] = mfdcr (memcfgd);
+	mtdcr (memcfga, mem_mb1cf);
+	bank_reg[1] = mfdcr (memcfgd);
+	mtdcr (memcfga, mem_mb2cf);
+	bank_reg[2] = mfdcr (memcfgd);
+	mtdcr (memcfga, mem_mb3cf);
+	bank_reg[3] = mfdcr (memcfgd);
+	TotalSize = 0;
+	for (i = 0; i < 4; i++) {
+		if ((bank_reg[i] & 0x1) == 0x1) {
+			tmp = (bank_reg[i] >> 17) & 0x7;
+			bank_size = 4 << tmp;
+			TotalSize += bank_size;
+		} else
+			ds = 1;
+	}
+	mtdcr (memcfga, mem_ecccf);
+	tmp = mfdcr (memcfgd);
+
+	if (!tmp)
+		printf ("No ");
+	printf ("ECC ");
+
+	test_dram (TotalSize * MEGA_BYTE);
+	return (TotalSize * MEGA_BYTE);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static int test_dram (unsigned long ramsize)
+{
+#ifdef SDRAM_DEBUG
+	mem_test (0L, ramsize, 1);
+#endif
+	/* not yet implemented */
+	return (1);
+}
+
+/* used to check if the time in RTC is valid */
+static unsigned long start;
+static struct rtc_time tm;
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart=0-flash_info[0].size;
+	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+	gd->bd->bi_flashoffset=0;
+
+	/* check, if RTC is running */
+	rtc_get (&tm);
+	start=get_timer(0);
+	/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
+	if (mfdcr(strap) & PSR_ROM_LOC)
+	       mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+
+	return (0);
+}
+
+
+void print_mip405_rev (void)
+{
+	unsigned char part, vers, pcbrev, var;
+
+	get_pcbrev_var(&pcbrev,&var);
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	printf ("Rev:   " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
+			var, pcbrev + 'A', part & 0x7F, vers);
+}
+
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+#endif
+
+extern void mem_test_reloc(void);
+extern int mk_date (char *, struct rtc_time *);
+
+int last_stage_init (void)
+{
+	unsigned long stop;
+	struct rtc_time newtm;
+	char *s;
+	mem_test_reloc();
+	/* write correct LED configuration */
+	if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
+		printf ("Error writing to the PHY\n");
+	}
+	/* since LED/CFG2 is not connected on the -2,
+	 * write to correct capability information */
+	if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
+		printf ("Error writing to the PHY\n");
+	}
+	print_mip405_rev ();
+	show_stdio_dev ();
+	check_env ();
+	/* check if RTC time is valid */
+	stop=get_timer(start);
+	while(stop<1200) {   /* we wait 1.2 sec to check if the RTC is running */
+		udelay(1000);
+		stop=get_timer(start);
+	}
+	rtc_get (&newtm);
+	if(tm.tm_sec==newtm.tm_sec) {
+		s=getenv("defaultdate");
+		if(!s)
+			mk_date ("010112001970", &newtm);
+		else
+			if(mk_date (s, &newtm)!=0) {
+				printf("RTC: Bad date format in defaultdate\n");
+				return 0;
+			}
+		rtc_reset ();
+		rtc_set(&newtm);
+	}
+	return 0;
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+
+int overwrite_console (void)
+{
+	return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0);	/* return TRUE if console should be overwritten */
+}
+
+
+/************************************************************************
+* Print MIP405 Info
+************************************************************************/
+void print_mip405_info (void)
+{
+	unsigned char part, vers, cfg, irq_reg, com_mode, ext;
+
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	cfg = in8 (PLD_BOARD_CFG_REG);
+	irq_reg = in8 (PLD_IRQ_REG);
+	com_mode = in8 (PLD_COM_MODE_REG);
+	ext = in8 (PLD_EXT_CONF_REG);
+
+	printf ("PLD Part %d version %d\n", part & 0x7F, vers);
+	printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
+	printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
+			(cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
+	printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
+	printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
+#if !defined(CONFIG_MIP405T)
+	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
+			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
+			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
+			(ext >> 6) & 0x1, (ext >> 7) & 0x1);
+	printf ("SER1 uses handshakes %s\n",
+			(ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
+#else
+	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
+			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
+			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
+			(ext >> 6) & 0x1,(ext >> 7) & 0x1);
+#endif
+	printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
+	printf ("IRQs:\n");
+	printf ("  PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
+#if !defined(CONFIG_MIP405T)
+	printf ("  UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
+	printf ("  UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
+#endif
+	printf ("  PIIX SMI:  %s\n", (irq_reg & 0x10) ? "inactive" : "active");
+	printf ("  PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
+	printf ("  PIIX NMI:  %s\n", (irq_reg & 0x4) ? "inactive" : "active");
+}
diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h
new file mode 100755
index 0000000..b1d91de
--- /dev/null
+++ b/board/mpl/mip405/mip405.h
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ /****************************************************************************
+ * Global routines used for MIP405
+ *****************************************************************************/
+#ifndef __ASSEMBLY__
+/*int switch_cs(unsigned char boot);*/
+
+extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
+
+void user_led0(unsigned char on);
+
+
+#endif
+/* timings */
+/* PLD (CS7) */
+#define PLD_BME	0 	/* Burst disable */
+#define PLD_TWE	5	/* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define PLD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define PLD_OEN	1	/* Cycles from CS low to OE low   */
+#define PLD_WBN	1	/* Cycles from CS low to WE low   */
+#define PLD_WBF	1	/* Cycles from WE high to CS high */
+#define PLD_TH	2	/* Number of hold cycles after transfer */
+#define PLD_RE	0	/* Ready disabled */
+#define PLD_SOR	1	/* Sample on Ready disabled */
+#define PLD_BEM	0	/* Byte Write only active on Write cycles */
+#define PLD_PEN	0	/* Parity disable */
+#define PLD_AP 	((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
+					(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define PLD_BS	0	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define PLD_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define PLD_BW	0	/* 16Bit */
+#define PLD_CR	((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
+
+
+/* timings */
+
+#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
+/* Dummy CS to get the board revision */
+#define BOARD_BME	0 	/* Burst disable */
+#define BOARD_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define BOARD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define BOARD_OEN	1	/* Cycles from CS low to OE low   */
+#define BOARD_WBN	1	/* Cycles from CS low to WE low   */
+#define BOARD_WBF	1	/* Cycles from WE high to CS high */
+#define BOARD_TH	2	/* Number of hold cycles after transfer */
+#define BOARD_RE	0	/* Ready disabled */
+#define BOARD_SOR	1	/* Sample on Ready disabled */
+#define BOARD_BEM	0	/* Byte Write only active on Write cycles */
+#define BOARD_PEN	0	/* Parity disable */
+#define BOARD_AP 	((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
+					(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define BOARD_BS	0	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define BOARD_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define BOARD_BW	0	/* 16Bit */
+#define BOARD_CR	((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
+
+
+/* UART0 CS2 */
+#define UART0_BME	0 	/* Burst disable */
+#define UART0_TWE	7	/* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
+#define UART0_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define UART0_OEN	1	/* Cycles from CS low to OE low   */
+#define UART0_WBN	1	/* Cycles from CS low to WE low   */
+#define UART0_WBF	1	/* Cycles from WE high to CS high */
+#define UART0_TH	2	/* Number of hold cycles after transfer */
+#define UART0_RE	0	/* Ready disabled */
+#define UART0_SOR	1	/* Sample on Ready disabled */
+#define UART0_BEM	0	/* Byte Write only active on Write cycles */
+#define UART0_PEN	0	/* Parity disable */
+#define UART0_AP 	((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
+					(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define UART0_BS	0	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define UART0_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define UART0_BW	0	/* 8Bit */
+#define UART0_CR	((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
+
+/* UART1 CS3 */
+#define UART1_AP UART0_AP /* same timing as UART0 */
+#define UART1_CR	((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
+
+
+/* Flash CS0 or CS 1 */
+/* 0x7F8FFE80 slowest timing at all... */
+#define FLASH_BME_B	1 	/* Burst enable */
+#define FLASH_FWT_B	0x6	/* 6 * 30ns 210ns First Wait Access */
+#define FLASH_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
+#define FLASH_BME	0 	/* Burst disable */
+#define FLASH_TWE	0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define FLASH_CSN	0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define FLASH_OEN	1	/* Cycles from CS low to OE low   */
+#define FLASH_WBN	1	/* Cycles from CS low to WE low   */
+#define FLASH_WBF	1	/* Cycles from WE high to CS high */
+#define FLASH_TH	2	/* Number of hold cycles after transfer */
+#define FLASH_RE	0	/* Ready disabled */
+#define FLASH_SOR	1	/* Sample on Ready disabled */
+#define FLASH_BEM	0	/* Byte Write only active on Write cycles */
+#define FLASH_PEN	0	/* Parity disable */
+/* Access Parameter Register for non Boot */
+#define FLASH_AP 	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+/* Access Parameter Register for Boot */
+#define FLASH_AP_B 	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define FLASH_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define FLASH_BW	1	/* 16Bit */
+/* CR register for Boot */
+#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+/* CR register for non Boot */
+#define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+
+/* MPS CS1 or CS0 */
+/* Boot CS: */
+#define MPS_BME_B	1 	/* Burst enable */
+#define MPS_FWT_B	0x6/* 6 * 30ns 210ns First Wait Access */
+#define MPS_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
+#define MPS_BME		0 	/* Burst disable */
+#define MPS_TWE		0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define MPS_CSN		0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define MPS_OEN		1	/* Cycles from CS low to OE low   */
+#define MPS_WBN		1	/* Cycles from CS low to WE low   */
+#define MPS_WBF		1	/* Cycles from WE high to CS high */
+#define MPS_TH		2	/* Number of hold cycles after transfer */
+#define MPS_RE		0	/* Ready disabled */
+#define MPS_SOR		1	/* Sample on Ready disabled */
+#define MPS_BEM		0	/* Byte Write only active on Write cycles */
+#define MPS_PEN		0	/* Parity disable */
+/* Access Parameter Register for non Boot */
+#define MPS_AP 		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+/* Access Parameter Register for Boot */
+#define MPS_AP_B 		((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define MPS_BS		2	/* 4 MByte */
+#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define MPS_BU		3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define MPS_BW		0	/* 8Bit */
+/* CR register for Boot */
+#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+/* CR register for non Boot */
+#define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds
new file mode 100755
index 0000000..ad5f273
--- /dev/null
+++ b/board/mpl/mip405/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+  .bootpg 0xFFFFF000 :
+  {
+    board/mpl/mip405/init.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/mpl/mip405/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile
new file mode 100755
index 0000000..1a9ce12
--- /dev/null
+++ b/board/mpl/pati/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001	Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:=  pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o
+#### cmd_pati.o
+SOBJS	:=
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
new file mode 100755
index 0000000..98429c0
--- /dev/null
+++ b/board/mpl/pati/cmd_pati.c
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Adapted for PATI
+ */
+
+#include <common.h>
+#include <command.h>
+#define PLX9056_LOC
+#include "plx9056.h"
+#include "pati.h"
+#include "pci_eeprom.h"
+
+extern void show_pld_regs(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+extern void user_led0(int led_on);
+extern void user_led1(int led_on);
+
+/* ------------------------------------------------------------------------- */
+#if defined(CFG_PCI_CON_DEVICE)
+extern void pci_con_disc(void);
+extern void pci_con_connect(void);
+#endif
+
+/******************************************************************************
+ * Eeprom Support
+ ******************************************************************************/
+unsigned long get32(unsigned long addr)
+{
+	unsigned long *p=(unsigned long *)addr;
+	return *p;
+}
+
+void set32(unsigned long addr,unsigned long data)
+{
+	unsigned long *p=(unsigned long *)addr;
+	*p=data;
+}
+
+#define PCICFG_GET_REG(x)	(get32((x) + PCI_CONFIG_BASE))
+#define PCICFG_SET_REG(x,y)	(set32((x) + PCI_CONFIG_BASE,(y)))
+
+
+/******************************************************************************
+ * reload_pci_eeprom
+ ******************************************************************************/
+
+static void reload_pci_eeprom(void)
+{
+	unsigned long reg;
+	/* Set Bit 29 and clear it again */
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	udelay(1);
+	/* set it*/
+	reg|=(1<<29);
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	/* EECLK @ 33MHz = 125kHz
+	 * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec
+	 * use 20msec
+	 */
+	udelay(20000); /* wait 20ms */
+	reg &= ~(1<<29); /* set it low */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	udelay(1); /* wait some time */
+}
+
+/******************************************************************************
+ * clock_pci_eeprom
+ ******************************************************************************/
+
+static void clock_pci_eeprom(void)
+{
+	unsigned long reg;
+	/* clock is low, data is valid */
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	udelay(1);
+	/* set clck high */
+	reg|=(1<<24);
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	udelay(1); /* wait some time */
+	reg &= ~(1<<24); /* set clock low */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	udelay(1); /* wait some time */
+}
+
+/******************************************************************************
+ * send_pci_eeprom_cmd
+ ******************************************************************************/
+static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len)
+{
+	unsigned long reg;
+	int i;
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	/* Clear all EEPROM bits */
+	reg &= ~(0xF << 24);
+	/* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	udelay(1); /* wait some time */
+	/* Enable EEPROM Chip Select */
+	reg |= (1 << 25);
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+	/* Send EEPROM command - one bit at a time */
+	for (i = (int)(len-1); i >= 0; i--) {
+		/* Check if current bit is 0 or 1 */
+		if (cmd & (1 << i))
+			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
+		else
+			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
+		clock_pci_eeprom();
+	}
+}
+
+/******************************************************************************
+ * write_pci_eeprom_offs
+ ******************************************************************************/
+static void write_pci_eeprom_offs(unsigned short offset, unsigned short value)
+{
+	unsigned long reg;
+	int bitpos, cmdshft, cmdlen, timeout;
+	/* we're using the Eeprom 93CS66 */
+	cmdshft  = 2;
+	cmdlen = EE66_CMD_LEN;
+	/* Send Write_Enable command to EEPROM */
+	send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen);
+	/* Send EEPROM Write command and offset to EEPROM */
+	send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen);
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	/* Clear all EEPROM bits */
+	reg &= ~(0xF << 24);
+	/* Make sure EEDO Input is disabled for some PLX chips */
+	reg &= ~(1 << 31);
+	/* Enable EEPROM Chip Select */
+	reg |= (1 << 25);
+	/* Write 16-bit value to EEPROM - one bit at a time */
+	for (bitpos = 15; bitpos >= 0; bitpos--) {
+		/* Get bit value and shift into result */
+		if (value & (1 << bitpos))
+			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
+		else
+			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg );
+		clock_pci_eeprom();
+	} /* for */
+	/* Deselect Chip */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25));
+	/* Re-select Chip */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25));
+	/* A small delay is needed to let EEPROM complete */
+	timeout = 0;
+	do {
+		udelay(10);
+		reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+		timeout++;
+	} while (((reg & (1 << 27)) == 0) && timeout < 20000);
+	/* Send Write_Disable command to EEPROM */
+	send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen);
+	/* Clear Chip Select and all other EEPROM bits */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
+}
+
+
+/******************************************************************************
+ * read_pci_eeprom_offs
+ ******************************************************************************/
+static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue)
+{
+	unsigned long reg;
+	int bitpos, cmdshft, cmdlen;
+	/* we're using the Eeprom 93CS66 */
+	cmdshft  = 2;
+	cmdlen = EE66_CMD_LEN;
+	/* Send EEPROM read command and offset to EEPROM */
+	send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen);
+	/* Set EEPROM write output bit */
+	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+	/* Set EEDO Input enable */
+	reg |= (1 << 31);
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26));
+	/* Get 16-bit value from EEPROM - one bit at a time */
+	for (bitpos = 0; bitpos < 16; bitpos++) {
+		clock_pci_eeprom();
+		udelay(10);
+		reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
+		/* Get bit value and shift into result */
+		if (reg & (1 << 27))
+			*pvalue = (unsigned short)((*pvalue << 1) | 1);
+		else
+			*pvalue = (unsigned short)(*pvalue << 1);
+	}
+	/* Clear EEDO Input enable */
+	reg &= ~(1 << 31);
+	/* Clear Chip Select and all other EEPROM bits */
+	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
+}
+
+
+/******************************************************************************
+ * EEPROM read/writes
+******************************************************************************/
+
+#undef EEPROM_DBG
+static int pati_pci_eeprom_erase(void)
+{
+	int i;
+	printf("Erasing EEPROM ");
+	for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) {
+		write_pci_eeprom_offs(i,0xffff);
+		if((i%0x10))
+			printf(".");
+	}
+	printf("\nDone\n");
+	return 0;
+}
+
+static int pati_pci_eeprom_prg(void)
+{
+	int i;
+	i=0;
+	printf("Programming EEPROM ");
+	while(pati_eeprom[i].offset<0xffff) {
+		write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value);
+		#ifdef EEPROM_DBG
+		printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value);
+		#else
+		if((i%0x10))
+			printf(".");
+		#endif
+		i++;
+	}
+	printf("\nDone\n");
+	return 0;
+}
+
+static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size)
+{
+	int i;
+	unsigned short value;
+	unsigned short *buffer =(unsigned short *)addr;
+	if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
+		size = PATI_EEPROM_LAST_OFFSET - offset;
+	}
+	printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2);
+	for( i = offset; i< (offset + size); i+=2) {
+		value = *buffer++;
+		write_pci_eeprom_offs(i,value);
+		#ifdef EEPROM_DBG
+		printf("0x%04X: 0x%04X\n",i, value);
+		#else
+		if((i%0x10))
+			printf(".");
+		#endif
+	}
+	printf("\nDone\n");
+	return 0;
+}
+
+static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size)
+{
+	int i;
+	unsigned short value;
+	unsigned short *buffer =(unsigned short *)addr;
+	if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
+		size = PATI_EEPROM_LAST_OFFSET - offset;
+	}
+	printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2);
+	for( i = offset; i< (offset + size); i+=2) {
+		read_pci_eeprom_offs(i,&value);
+		*buffer++=value;
+		#ifdef EEPROM_DBG
+		printf("0x%04X: 0x%04X\n",i, value);
+		#else
+		if((i%0x10))
+			printf(".");
+		#endif
+	}
+	printf("\nDone\n");
+	return 0;
+}
+
+/******************************************************************************
+ * PCI Bridge Registers Dump
+*******************************************************************************/
+static void display_pci_regs(void)
+{
+	printf(" PCI9056_SPACE0_RANGE     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE));
+	printf(" PCI9056_SPACE0_REMAP     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP));
+	printf(" PCI9056_LOCAL_DMA_ARBIT  %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT));
+	printf(" PCI9056_ENDIAN_DESC      %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC));
+	printf(" PCI9056_EXP_ROM_RANGE    %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE));
+	printf(" PCI9056_EXP_ROM_REMAP    %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP));
+	printf(" PCI9056_SPACE0_ROM_DESC  %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC));
+	printf(" PCI9056_DM_RANGE         %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE));
+	printf(" PCI9056_DM_MEM_BASE      %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE));
+	printf(" PCI9056_DM_IO_BASE       %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE));
+	printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP));
+	printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG));
+	printf(" PCI9056_SPACE1_RANGE     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE));
+	printf(" PCI9056_SPACE1_REMAP     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP));
+	printf(" PCI9056_SPACE1_DESC      %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC));
+	printf(" PCI9056_DM_DAC           %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC));
+	printf(" PCI9056_MAILBOX0         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0));
+	printf(" PCI9056_MAILBOX1         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1));
+	printf(" PCI9056_MAILBOX2         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2));
+	printf(" PCI9056_MAILBOX3         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3));
+	printf(" PCI9056_MAILBOX4         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4));
+	printf(" PCI9056_MAILBOX5         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5));
+	printf(" PCI9056_MAILBOX6         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6));
+	printf(" PCI9056_MAILBOX7         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7));
+	printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL));
+	printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL));
+	printf(" PCI9056_INT_CTRL_STAT    %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT));
+	printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT));
+	printf(" PCI9056_PERM_VENDOR_ID   %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID));
+	printf(" PCI9056_REVISION_ID      %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID));
+	printf(" \n");
+	printf(" PCI9056_VENDOR_ID        %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID));
+	printf(" PCI9056_COMMAND          %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND));
+	printf(" PCI9056_REVISION         %08lX\n",PCICFG_GET_REG(PCI9056_REVISION));
+	printf(" PCI9056_CACHE_SIZE       %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE));
+	printf(" PCI9056_RTR_BASE         %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE));
+	printf(" PCI9056_RTR_IO_BASE      %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE));
+	printf(" PCI9056_LOCAL_BASE0      %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0));
+	printf(" PCI9056_LOCAL_BASE1      %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1));
+	printf(" PCI9056_UNUSED_BASE1     %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1));
+	printf(" PCI9056_UNUSED_BASE2     %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2));
+	printf(" PCI9056_CIS_PTR          %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR));
+	printf(" PCI9056_SUB_ID           %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID));
+	printf(" PCI9056_EXP_ROM_BASE     %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE));
+	printf(" PCI9056_CAP_PTR          %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR));
+	printf(" PCI9056_INT_LINE         %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE));
+	printf(" PCI9056_PM_CAP_ID        %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID));
+	printf(" PCI9056_PM_CSR           %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR));
+	printf(" PCI9056_HS_CAP_ID        %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID));
+	printf(" PCI9056_VPD_CAP_ID       %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID));
+	printf(" PCI9056_VPD_DATA         %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA));
+}
+
+
+int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	if (strcmp(argv[1], "info") == 0)
+	{
+		show_pld_regs();
+	 	return 0;
+	}
+	if (strcmp(argv[1], "pci") == 0)
+	{
+		display_pci_regs();
+	 	return 0;
+	}
+	if (strcmp(argv[1], "led") == 0)
+	{
+		int led_nr,led_on;
+		led_nr = (int)simple_strtoul(argv[2], NULL, 10);
+		led_on = (int)simple_strtoul(argv[3], NULL, 10);
+		if(!led_nr)
+			user_led0(led_on);
+		else
+			user_led1(led_on);
+		return 0;
+   	}
+#if defined(CFG_PCI_CON_DEVICE)
+	if (strcmp(argv[1], "con") == 0) {
+		pci_con_connect();
+		return 0;
+	}
+	if (strcmp(argv[1], "disc") == 0) {
+		pci_con_disc();
+		return 0;
+	}
+#endif
+	if (strcmp(argv[1], "eeprom") == 0) {
+		unsigned long addr;
+		int size, offset;
+		offset = 0;
+		size = PATI_EEPROM_LAST_OFFSET;
+		if(argc>2) {
+			if(argc>3) {
+				addr = simple_strtoul(argv[3], NULL, 16);
+				if(argc>4)
+					offset = (int) simple_strtoul(argv[4], NULL, 16);
+				if(argc>5)
+					size = (int) simple_strtoul(argv[5], NULL, 16);
+				if (strcmp(argv[2], "read") == 0) {
+					return (pati_pci_eeprom_read(offset, addr, size));
+				}
+				if (strcmp(argv[2], "write") == 0) {
+					return (pati_pci_eeprom_write(offset, addr, size));
+				}
+			}
+			if (strcmp(argv[2], "prg") == 0) {
+				return (pati_pci_eeprom_prg());
+			}
+			if (strcmp(argv[2], "era") == 0) {
+				return (pati_pci_eeprom_erase());
+			}
+			if (strcmp(argv[2], "reload") == 0) {
+				reload_pci_eeprom();
+				return 0;
+			}
+
+
+		}
+	}
+
+	return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+
+U_BOOT_CMD(
+	pati,	8,	1,	do_pati,
+	"pati    - PATI specific Cmds\n",
+	"info - displays board information\n"
+	"pati pci  - displays PCI registers\n"
+	"pati led <nr> <on> \n"
+	"          - switch LED <nr> <on>\n"
+	"pati flash mem [SrcAddr]\n"
+	"          - updates U-Boot with image in memory\n"
+	"pati eeprom <cmd> - PCI EEPROM sub-system\n"
+	"    read <addr> <offset> <size>\n"
+	"          - read PCI EEPROM to <addr> from <offset> <size> words\n"
+	"    write <addr> <offset> <size>\n"
+	"          - write PCI EEPROM from <addr> to <offset> <size> words\n"
+	"    prg   - programm PCI EEPROM with default values\n"
+	"    era   - erase PCI EEPROM (write all word to 0xffff)\n"
+	"    reload- Reload PCI Bridge with EEPROM Values\n"
+	"    NOTE: <addr> must start on word boundary\n"
+	"          <offset> and <size> must be even byte values\n"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pati/config.mk b/board/mpl/pati/config.mk
new file mode 100755
index 0000000..b8a0985
--- /dev/null
+++ b/board/mpl/pati/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003
+# Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# EPQ Board Configuration
+#
+
+# Boot from flash at location 0x00000000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
new file mode 100755
index 0000000..0355b65
--- /dev/null
+++ b/board/mpl/pati/pati.c
@@ -0,0 +1,618 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ * Atapted for PATI
+ * Denis Peter, d.peter@mpl.ch
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/***********************************************************************************
+ * Bits for the SDRAM controller
+ * -----------------------------
+ *
+ * CAL:	CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on
+ *	the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM
+ *	controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3).
+ * RCD:	RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default)
+ *	tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns.
+ * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns.
+ *	If set to 1 tWR must be equal or less 50ns.
+ * RP:	Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less
+ *	25ns. If set to 1 tRP must be equal or less 50ns.
+ * RC:	Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal
+ *	or less 75ns. If set to 1 tRC must be equal or less 100ns.
+ * LMR:	Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM
+ *	is the Load Mode Register Command.
+ * IIP:	Init in progress. Set to 1 for starting the init sequence
+ *	(Precharge All). As long this bit is set, the Precharge All is still in progress.
+ *	After command has completed, wait at least for 8 refresh (200usec) before proceed.
+ **********************************************************************************/
+
+#include <common.h>
+#include <mpc5xx.h>
+#include <devices.h>
+#include <pci_ids.h>
+#define PLX9056_LOC
+#include "plx9056.h"
+#include "pati.h"
+
+#if defined(__APPLE__)
+/* Leading underscore on symbols */
+#  define SYM_CHAR "_"
+#else /* No leading character on symbols */
+#  define SYM_CHAR
+#endif
+
+#undef SDRAM_DEBUG
+/*
+ * Macros to generate global absolutes.
+ */
+#define GEN_SYMNAME(str) SYM_CHAR #str
+#define GEN_VALUE(str) #str
+#define GEN_ABS(name, value) \
+		asm (".globl " GEN_SYMNAME(name)); \
+		asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
+
+
+/************************************************************************
+ * Early debug routines
+ */
+void write_hex (unsigned char i)
+{
+	char cc;
+
+	cc = i >> 4;
+	cc &= 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+	cc = i & 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+}
+
+#if defined(SDRAM_DEBUG)
+
+void write_4hex (unsigned long val)
+{
+	write_hex ((unsigned char) (val >> 24));
+	write_hex ((unsigned char) (val >> 16));
+	write_hex ((unsigned char) (val >> 8));
+	write_hex ((unsigned char) val);
+}
+
+#endif
+
+unsigned long in32(unsigned long addr)
+{
+	unsigned long *p=(unsigned long *)addr;
+	return *p;
+}
+
+void out32(unsigned long addr,unsigned long data)
+{
+	unsigned long *p=(unsigned long *)addr;
+	*p=data;
+}
+
+typedef struct {
+	unsigned short boardtype; /* Board revision and Population Options */
+	unsigned char cal;		/* cas Latency  0:CAL=2 1:CAL=3 */
+	unsigned char rcd;		/* ras to cas delay  0:<25ns 1:<50ns*/
+	unsigned char wrec;		/* write recovery 0:<25ns 1:<50ns */
+	unsigned char pr;		/* Precharge Command Time 0:<25ns 1:<50ns */
+	unsigned char rc;		/* Auto Refresh to Active Time 0:<75ns 1:<100ns */
+	unsigned char sz;		/* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
+} sdram_t;
+
+const sdram_t sdram_table[] = {
+	{ 0x0000,	/* PATI Rev A, 16MByte -1 Board */
+		1,	/* Case Latenty = 3 */
+		0,	/* ras to cas delay  0 (20ns) */
+		0,	/* write recovery 0:<25ns 1:<50ns*/
+		0,	/* Precharge Command Time 0 (20ns) */
+		0,	/* Auto Refresh to Active Time 0 (68) */
+		2	/* log binary => Size 2 = 16MByte, 1=8 */
+	},
+	{ 0xffff, /* terminator */
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff,
+	  0xff }
+};
+
+
+extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
+extern void mem_test_reloc(void);
+
+/*
+ * Get RAM size.
+ */
+long int initdram(int board_type)
+{
+	unsigned char board_rev;
+	unsigned long reg;
+	unsigned long lmr;
+	int i,timeout;
+
+#if defined(SDRAM_DEBUG)
+	reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
+	puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg));
+	puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg));
+	puts("\nSDRAM  part  0x"); write_4hex(SDRAM_PART(reg));
+	puts(" Vers 0x"); write_4hex(SDRAM_ID(reg));
+	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+	puts("\nBoard rev.   0x"); write_4hex(SYSCNTR_BREV(reg));
+   putc('\n');
+#endif
+	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+	board_rev=(unsigned char)(SYSCNTR_BREV(reg));
+	i=0;
+	while(1) {
+		if(sdram_table[i].boardtype==0xffff) {
+			puts("ERROR, found no table for Board 0x");
+			write_hex(board_rev);
+			while(1);
+		}
+		if(sdram_table[i].boardtype==(unsigned char)board_rev)
+			break;
+		i++;
+	}
+	/* Set CAL, RCD, WREQ, PR and RC Bits */
+#if defined(SDRAM_DEBUG)
+	puts("Set CAL, RCD, WREQ, PR and RC Bits\n");
+#endif
+	/* mask bits */
+	reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) |
+				SET_REG_BIT(1,SDRAM_PR)  |  SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR)  |
+				SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0));
+	/* set bits */
+	reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) |
+			  SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) |
+			  SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) |
+			  SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) |
+			  SET_REG_BIT(sdram_table[i].rc,SDRAM_RC));
+
+	out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
+	/* step 2 set IIP */
+#if defined(SDRAM_DEBUG)
+	puts("step 2 set IIP\n");
+#endif
+	/* step 2 set IIP */
+	reg |= SET_REG_BIT(1,SDRAM_IIP);
+	timeout=0;
+	while (timeout!=0xffff) {
+		__asm__ volatile("eieio");
+		reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+		if((reg & SET_REG_BIT(1,SDRAM_IIP))==0)
+			break;
+		timeout++;
+		udelay(1);
+	}
+	/* wait for at least 8 refresh */
+	udelay(1000);
+	/* set LMR */
+	reg |= SET_REG_BIT(1,SDRAM_LMR);
+	out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
+	__asm__ volatile("eieio");
+	lmr=0x00000002; /* sequential burst 4 data */
+	if(sdram_table[i].cal==1)
+		lmr|=0x00000030; /* cal = 3 */
+	else
+		lmr|=0000000020; /* cal = 2 */
+	/* rest standard operation programmed write burst length */
+	/* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
+	lmr<<=2;
+	in32(CFG_SDRAM_BASE + lmr);
+	/* ok, we're done, return SDRAM size */
+	return ((0x400000 << sdram_table[i].sz));		/* log2 value of 4MByte  */
+}
+
+
+void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp)
+{
+	unsigned long reg;
+	reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE);
+	reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) |
+			   SET_REG_BIT(1,SYSCNTR_FL_VPP) |
+				SET_REG_BIT(1,SYSCNTR_FL_WP));
+
+	reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) |
+			   SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) |
+				SET_REG_BIT(ext_wp,SYSCNTR_FL_WP));
+	out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg);
+	udelay(100);
+}
+
+
+void show_pld_regs(void)
+{
+	unsigned long reg,reg1;
+	reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
+	printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg));
+	printf("SDRAM  part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg));
+	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+	printf("Board rev.  %c\n",(char) (SYSCNTR_BREV(reg)+'A'));
+	printf("Waitstates  %ld\n",GET_SYSCNTR_FLWAIT(reg));
+	printf("SDRAM:      CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n            RC=%ld  LMR=%ld IIP=%ld\n",
+		GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD),
+		GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR),
+		GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR),
+		GET_REG_BIT(reg,SDRAM_IIP));
+	reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1);
+	reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2);
+	printf("HW Config:  FLAG=%ld IP=%ld  index=%ld PRPM=%ld\n            ICW=%ld  ISB=%ld BDIS=%ld  PCIM=%ld\n",
+		GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP),
+		GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM),
+		GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg),
+		GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM));
+	printf("Switches:   MUX=%ld PCI_DIS=%ld Boot_EN=%ld  Config=%ld\n",GET_SDRAM_MUX(reg),
+		GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN),
+		GET_SYSCNTR_CFG(reg1));
+	printf("Misc:       RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n",
+		GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP),
+		GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP));
+}
+
+
+/****************************************************************
+ * Setting IOs
+ * -----------
+ * GPIO6 is User LED1
+ * GPIO7 is Interrupt PLX (Output)
+ * GPIO5 is User LED0
+ * GPIO2 is PLX USERi (Output)
+ * GPIO1 is PLX Interrupt (Input)
+ ****************************************************************/
+ void init_ios(void)
+ {
+	volatile immap_t * immr = (immap_t *) CFG_IMMR;
+	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+	unsigned long reg;
+	reg=sysconf->sc_sgpiocr; /* Data direction register */
+	reg &= ~0x67000000;
+	reg |= 0x27000000; /* set outpupts */
+	sysconf->sc_sgpiocr=reg; /* Data direction register */
+	reg=sysconf->sc_sgpiodt2; /* Data register */
+	/* set output to 0 */
+	reg &= ~0x27000000;
+	/* set IRQ and USERi to 1 */
+	reg |= 0x28000000;
+	sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+void user_led0(int led_on)
+{
+	volatile immap_t * immr = (immap_t *) CFG_IMMR;
+	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+	unsigned long reg;
+	reg=sysconf->sc_sgpiodt2; /* Data register */
+	if(led_on)	/* set output to 1 */
+		reg |= 0x04000000;
+	else
+		reg &= ~0x04000000;
+	sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+void user_led1(int led_on)
+{
+	volatile immap_t * immr = (immap_t *) CFG_IMMR;
+	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
+	unsigned long reg;
+	reg=sysconf->sc_sgpiodt2; /* Data register */
+	if(led_on)	/* set output to 1 */
+		reg |= 0x02000000;
+	else
+		reg &= ~0x02000000;
+	sysconf->sc_sgpiodt2=reg; /* Data register */
+}
+
+
+/****************************************************************
+ * Last Stage Init
+ ****************************************************************/
+int last_stage_init (void)
+{
+	mem_test_reloc();
+	init_ios();
+	return 0;
+}
+
+/****************************************************************
+ * Check the board
+ ****************************************************************/
+
+#define BOARD_NAME	"PATI"
+
+int checkboard (void)
+{
+	unsigned char s[50];
+	unsigned long reg;
+	char rev;
+	int i;
+
+	puts ("\nBoard: ");
+	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
+	rev=(char)(SYSCNTR_BREV(reg)+'A');
+	i = getenv_r ("serial#", s, 32);
+	if ((i == -1)) {
+		puts ("### No HW ID - assuming " BOARD_NAME);
+		printf(" Rev. %c\n",rev);
+	}
+	else {
+		s[sizeof(BOARD_NAME)-1] = 0;
+		printf ("%s-1 Rev %c SN: %s\n", s,rev,
+				&s[sizeof(BOARD_NAME)]);
+	}
+	set_flash_vpp(1,0,0); /* set Flash VPP */
+	return 0;
+}
+
+
+#ifdef CFG_PCI_CON_DEVICE
+/************************************************************************
+ * PCI Communication
+ *
+ * Alive (Pinging):
+ * ----------------
+ * PCI Host sends message ALIVE, Local acknowledges with ALIVE
+ *
+ * PCI_CON console over PCI:
+ * -------------------------
+ * Local side:
+ *     - uses PCI9056_LOC_TO_PCI_DBELL register to signal that
+ *       data is avaible (PCIMSG_CONN)
+ *     - uses PCI9056_MAILBOX1 to send data
+ *     - uses PCI9056_MAILBOX0 to receive data
+ * PCI side:
+ *     - uses PCI9056_PCI_TO_LOC_DBELL register to signal that
+ *       data is avaible (PCIMSG_CONN)
+ *     - uses PCI9056_MAILBOX0 to send data
+ *     - uses PCI9056_MAILBOX1 to receive data
+ *
+ * How it works:
+ *     Send:
+ *     - check if PCICON_TRANSMIT_REG is empty
+ *     - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG
+ *     - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data
+ *       is waiting
+ *     Receive:
+ *     - get an interrupt via the PCICON_ACK_REG register message
+ *       PCIMSG_CONN
+ *     - write the data from the PCICON_RECEIVE_REG into the receive
+ *       buffer and if the receive buffer is not full, clear the
+ *       PCICON_RECEIVE_REG (this allows the counterpart to write more data)
+ *     - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG
+ *
+ *     The PCICON_RECEIVE_REG must be cleared by the routine which reads
+ *     the receive buffer if the buffer is not full any more
+ *
+ */
+
+#undef PCI_CON_DEBUG
+
+#ifdef	PCI_CON_DEBUG
+#define	PCI_CON_PRINTF(fmt,args...)	serial_printf (fmt ,##args)
+#else
+#define PCI_CON_PRINTF(fmt,args...)
+#endif
+
+
+/*********************************************************
+ * we work only with a receive buffer on eiter side.
+ * Transmit buffer is free, if mailbox is cleared.
+ * Transmit character is or'ed with 0x80000000
+ * PATI receive register MAILBOX0
+ * PATI transmit register MAILBOX1
+ *********************************************************/
+#define PCICON_RECEIVE_REG	PCI9056_MAILBOX0
+#define PCICON_TRANSMIT_REG	PCI9056_MAILBOX1
+#define PCICON_DBELL_REG	PCI9056_LOC_TO_PCI_DBELL
+#define PCICON_ACK_REG		PCI9056_PCI_TO_LOC_DBELL
+
+
+#define PCIMSG_ALIVE		0x1
+#define PCIMSG_CONN		0x2
+#define PCIMSG_DISC		0x3
+#define PCIMSG_CON_DATA	0x5
+
+
+#define PCICON_GET_REG(x)	(in32(x + PCI_CONFIG_BASE))
+#define PCICON_SET_REG(x,y)	(out32(x + PCI_CONFIG_BASE,y))
+#define PCICON_TX_FLAG		0x80000000
+
+
+#define REC_BUFFER_SIZE	0x100
+int recbuf[REC_BUFFER_SIZE];
+static int r_ptr = 0;
+int w_ptr;
+device_t pci_con_dev;
+int conn=0;
+int buff_full=0;
+
+void pci_con_put_it(const char c)
+{
+	/* Test for completition */
+	unsigned long reg;
+	do {
+		reg=PCICON_GET_REG(PCICON_TRANSMIT_REG);
+	}while(reg);
+	reg=PCICON_TX_FLAG + c;
+	PCICON_SET_REG(PCICON_TRANSMIT_REG,reg);
+	PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
+}
+
+void pci_con_putc(const char c)
+{
+	pci_con_put_it(c);
+	if(c == '\n')
+		pci_con_put_it('\r');
+}
+
+
+int pci_con_getc(void)
+{
+	int res;
+	int diff;
+	while(r_ptr==(volatile int)w_ptr);
+	res=recbuf[r_ptr++];
+	if(r_ptr==REC_BUFFER_SIZE)
+		r_ptr=0;
+	if(w_ptr<r_ptr)
+		diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
+	else
+		diff=r_ptr-w_ptr;
+	if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
+   		/* clear Mail box */
+			buff_full=0;
+			PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+	}
+	return res;
+}
+
+int pci_con_tstc(void)
+{
+	if(r_ptr==(volatile int)w_ptr)
+		return 0;
+	return 1;
+}
+
+void pci_con_puts (const char *s)
+{
+	while (*s) {
+		pci_con_putc(*s);
+		++s;
+	}
+}
+
+void pci_con_init (void)
+{
+	w_ptr = 0;
+	r_ptr = 0;
+	PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+	conn=1;
+}
+
+/*******************************************
+ * IRQ routine
+ ******************************************/
+int pci_dorbell_irq(void)
+{
+	unsigned long reg,data;
+	int diff;
+	reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
+	PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg);
+	if(reg & (1<<20) ) {
+		/* read doorbell */
+		reg=PCICON_GET_REG(PCICON_ACK_REG);
+		switch(reg) {
+			case PCIMSG_ALIVE:
+				PCI_CON_PRINTF(" Alive\n");
+				PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE);
+				break;
+			case PCIMSG_CONN:
+				PCI_CON_PRINTF(" Conn %d",conn);
+				w_ptr = 0;
+				r_ptr = 0;
+				buff_full=0;
+				PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+				conn=1;
+				PCI_CON_PRINTF(" ... %d\n",conn);
+				break;
+			case PCIMSG_CON_DATA:
+				data=PCICON_GET_REG(PCICON_RECEIVE_REG);
+				recbuf[w_ptr++]=(int)(data&0xff);
+				PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)),
+					r_ptr,w_ptr,recbuf[w_ptr-1]);
+				if(w_ptr==REC_BUFFER_SIZE)
+					w_ptr=0;
+				if(w_ptr<r_ptr)
+					diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
+				else
+					diff=r_ptr-w_ptr;
+				if(diff>(REC_BUFFER_SIZE-4))
+					buff_full=1;
+				else
+					/* clear Mail box */
+					PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
+				break;
+			default:
+				serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg);
+		}
+		/* clear IRQ */
+		PCICON_SET_REG(PCICON_ACK_REG,~0L);
+	}
+	return 0;
+}
+
+void pci_con_connect(void)
+{
+	unsigned long reg;
+	conn=0;
+	reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
+	/* default 0x0f010180 */
+	reg &= 0xff000000;
+	reg |= 0x00030000; /* enable local dorbell */
+	reg |= 0x00000300; /* enable PCI dorbell */
+	PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg);
+	irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL);
+	memset (&pci_con_dev, 0, sizeof (pci_con_dev));
+	strcpy (pci_con_dev.name, "pci_con");
+	pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	pci_con_dev.putc = pci_con_putc;
+	pci_con_dev.puts = pci_con_puts;
+	pci_con_dev.getc = pci_con_getc;
+	pci_con_dev.tstc = pci_con_tstc;
+	device_register (&pci_con_dev);
+	printf("PATI ready for PCI connection, type ctrl-c for exit\n");
+	do {
+		udelay(10);
+		if((volatile int)conn)
+			break;
+		if(ctrlc()) {
+			irq_free_handler(0x2);
+			return;
+		}
+	}while(1);
+	console_assign(stdin,"pci_con");
+	console_assign(stderr,"pci_con");
+	console_assign(stdout,"pci_con");
+}
+
+void pci_con_disc(void)
+{
+	console_assign(stdin,"serial");
+	console_assign(stderr,"serial");
+	console_assign(stdout,"serial");
+	PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC);
+	/* reconnection */
+	irq_free_handler(0x02);
+	pci_con_connect();
+}
+#endif /* #ifdef CFG_PCI_CON_DEVICE */
+
+/*
+ * Absolute environment address for linker file.
+ */
+GEN_ABS(env_start, CFG_ENV_OFFSET + CFG_FLASH_BASE);
diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h
new file mode 100755
index 0000000..d521772
--- /dev/null
+++ b/board/mpl/pati/pati.h
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter, d.peter@mpl.ch
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/************************************************************************
+ * MACROS and register definitions for PATI Registers
+ ************************************************************************/
+#ifndef __PATI_H_
+#define __PATI_H_	1
+
+#define PLD_PART_ID		0x0
+#define PLD_BOARD_TIMING	0x4
+#define PLD_CONF_REG1		0x8
+#define PLD_CONF_REG2		0xC
+#define PLD_CONF_RES		0x10
+
+#define SET_REG_BIT(y,x) (y<<(31-x))
+#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L)
+
+/* SDRAM Controller PLD_PART_ID */
+/* 9  10 11 12 13 14 19 31 */
+#define SDRAM_PART3	9
+#define SDRAM_PART2	10
+#define SDRAM_PART1	11
+#define SDRAM_PART0	12
+#define SDRAM_ID3	13
+#define SDRAM_ID2	14
+#define SDRAM_ID1	19
+#define SDRAM_ID0	31
+
+#define SDRAM_PART(x)	(	\
+	(GET_REG_BIT(x,SDRAM_PART3)<<3) |\
+	(GET_REG_BIT(x,SDRAM_PART2)<<2) |\
+	(GET_REG_BIT(x,SDRAM_PART1)<<1) |\
+	(GET_REG_BIT(x,SDRAM_PART0)))
+
+#define SDRAM_ID(x)	(	\
+	(GET_REG_BIT(x,SDRAM_ID3)<<3) |\
+	(GET_REG_BIT(x,SDRAM_ID2)<<2) |\
+	(GET_REG_BIT(x,SDRAM_ID1)<<1) |\
+	(GET_REG_BIT(x,SDRAM_ID0)))
+
+/* System Controller */
+/* 0  1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_PART4	0
+#define SYSCNTR_PART3	1
+#define SYSCNTR_PART2	3
+#define SYSCNTR_PART1	4
+#define SYSCNTR_PART0	5
+#define SYSCNTR_ID4	16
+#define SYSCNTR_ID3	20
+#define SYSCNTR_ID2	28
+#define SYSCNTR_ID1	29
+#define SYSCNTR_ID0	30
+
+#define SYSCNTR_PART(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\
+	(GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\
+	(GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_PART0)))
+
+#define SYSCNTR_ID(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\
+	(GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\
+	(GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_ID0)))
+
+/* SDRAM Controller PLD_BOARD_TIMING */
+/* 9  10 11 12 13 14 19 31 */
+#define SDRAM_CAL	9
+#define SDRAM_RCD	10
+#define SDRAM_WREQ	11
+#define SDRAM_PR 	12
+#define SDRAM_RC	13
+#define SDRAM_LMR	14
+#define SDRAM_IIP	19
+#define SDRAM_RES0	31
+/* System Controller */
+/* 0  1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_BREV0	0
+#define SYSCNTR_BREV1	1
+#define SYSCNTR_BREV2	3
+#define SYSCNTR_BREV3	4
+#define SYSCNTR_RES0	5
+#define SYSCNTR_RES1	16
+#define SYSCNTR_RES2	20
+#define SYSCNTR_FLWAIT2	28
+#define SYSCNTR_FLWAIT1	29
+#define SYSCNTR_FLWAIT0	30
+
+#define SYSCNTR_BREV(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\
+	(GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_BREV0)))
+
+#define GET_SYSCNTR_FLWAIT(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_FLWAIT0)))
+
+#define SET_SYSCNTR_FLWAIT(x)	(	\
+	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\
+	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\
+	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0)))
+
+/* SDRAM Controller REG 2*/
+/* 9  10 11 12 13 14 19 31 */
+#define SDRAM_MUX0	9
+#define SDRAM_MUX1	10
+#define SDRAM_PDIS	11
+#define SDRAM_RES1 	12
+#define SDRAM_RES2	13
+#define SDRAM_RES3	14
+#define SDRAM_RES4	19
+#define SDRAM_RIP	31
+
+#define GET_SDRAM_MUX(x)	(	\
+	(GET_REG_BIT(x,SDRAM_MUX1)<<1)| \
+	(GET_REG_BIT(x,SDRAM_MUX0)))
+
+
+/* System Controller */
+/* 0  1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_FLAG	0
+#define SYSCNTR_IP	1
+#define SYSCNTR_BIND2	3
+#define SYSCNTR_BIND1	4
+#define SYSCNTR_BIND0	5
+#define SYSCNTR_PRM	16
+#define SYSCNTR_ICW	20
+#define SYSCNTR_ISB2	28
+#define SYSCNTR_ISB1	29
+#define SYSCNTR_ISB0	30
+
+#define GET_SYSCNTR_BOOTIND(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\
+	(GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\
+	(GET_REG_BIT(x,SYSCNTR_BIND0)))
+
+#define SET_SYSCNTR_BOOTIND(x)	(	\
+	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\
+	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \
+	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0)))
+
+#define GET_SYSCNTR_ISB(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \
+	(GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \
+	(GET_REG_BIT(x,SYSCNTR_ISB0)))
+
+#define SET_SYSCNTR_ISB(x)	(	\
+	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \
+	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \
+	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0)))
+
+/* SDRAM Controller REG 3*/
+/* 9  10 11 12 13 14 19 31 */
+#define SDRAM_RES5	9
+#define SDRAM_CFG1	10
+#define SDRAM_CFG2	11
+#define SDRAM_CFG3 	12
+#define SDRAM_RES6	13
+#define SDRAM_CFG5	14
+#define SDRAM_CFG6	19
+#define SDRAM_RES7	31
+
+#define GET_SDRAM_CFG(x)	(	\
+	(GET_REG_BIT(x,SDRAM_CFG6)<<4) |\
+	(GET_REG_BIT(x,SDRAM_CFG5)<<3) |\
+	(GET_REG_BIT(x,SDRAM_CFG3)<<2) |\
+	(GET_REG_BIT(x,SDRAM_CFG2)<<1) |\
+	(GET_REG_BIT(x,SDRAM_CFG1)))
+
+/* System Controller */
+/* 0  1 3 4 5 16 20 28 29 30 */
+#define SYSCNTR_BDIS	0
+#define SYSCNTR_PCIM	1
+#define SYSCNTR_CFG0	3
+#define SYSCNTR_CFG1	4
+#define SYSCNTR_CFG2	5
+#define SYSCNTR_CFG3	16
+#define SYSCNTR_BOOTEN	20
+#define SYSCNTR_CPU_VPP	28
+#define SYSCNTR_FL_VPP	29
+#define SYSCNTR_FL_WP	30
+
+#define GET_SYSCNTR_CFG(x)	(	\
+	(GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \
+	(GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \
+	(GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \
+	(GET_REG_BIT(x,SYSCNTR_CFG0)))
+
+
+/***************************************************************
+ * MISC Defines
+ ***************************************************************/
+
+#define PCI_VENDOR_ID_MPL 	0x18E6
+#define PCI_DEVICE_ID_PATI	0x00DA
+
+#if defined(CONFIG_MIP405)
+#define PATI_FIRMWARE_START_OFFSET	0x00300000
+#define PATI_ISO_STRING  "MEV-10084-001"
+#endif
+
+#define PATI_ENDIAN_MODE	0x3E
+
+/*******************************************
+ * PATI Mapping:
+ * -------------
+ * PCI Map:
+ * -------
+ * All addreses are mapped into the memory area
+ * (IO Area on some areas may also be possible)
+ * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
+ * - pci_space0_addr:  configurable
+ * - pci_space1_addr	  configurable
+ *
+ * Local Map:
+ * ----------
+ * Local addresses (Remap)
+ * - SDRAM      0x06000000 Size 16MByte mask 0xff000000
+ * - EPLD CFG   0x07000000 Size 512Bytes
+ * - FLASH      0x03000000 Size up to 8MByte
+ * - CPU        0x01000000 Size 4MByte (only accessable if special configured)
+ *
+ * Implemention:
+ * -------------
+ * To prevent using large resources reservation on the host following
+ * PCI mapping is choosed:
+ * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
+ * - pci_space0_addr:  configured to the EPLD Config Area size 256Bytes
+ * - pci_space1_addr:  configured to the SDRAM Area size 1MBytes, this
+ *                     space is used to switch between SDRAM, Flash and CPU
+ *
+ */
+
+/* Attribute definitions */
+#define PATI_BUS_SIZE_8		0
+#define PATI_BUS_SIZE_16	1
+#define PATI_BUS_SIZE_32	3
+
+#define PATI_SPACE0_MASK	(0xFEFFFE00)  /* Mask Attributes */
+#define PATI_SPACE1_MASK	(0x00000000)  /* Mask Attributes */
+
+#define PATI_EXTRA_LONG_EEPROM	1
+
+#define SPACE0_TA_ENABLE (1<<6)
+#define SPACE1_TA_ENABLE (1<<6)
+
+/* Config Area */
+#define PATI_LOC_CFG_ADDR		0x07000000		/* Local Address */
+#define PATI_LOC_CFG_MASK		0xFFFFFF00  		/* 256 Bytes */
+/* Attributes */
+#define PATI_LOC_CFG_BUS_SIZE		PATI_BUS_SIZE_32  	/* 32 Bit */
+#define PATI_LOC_CFG_BURST		0  			/* No Burst */
+#define PATI_LOC_CFG_NO_PREFETCH	1  			/* No Prefetch */
+#define PATI_LOC_CFG_TA_ENABLE		1 			/* Enable TA */
+
+#define PATI_LOC_CFG_SPACE0_ATTR  ( \
+		PATI_LOC_CFG_BUS_SIZE | \
+		(PATI_LOC_CFG_TA_ENABLE << 6) | \
+		(PATI_LOC_CFG_NO_PREFETCH << 8) | \
+		(PATI_LOC_CFG_BURST << 24) | \
+		(PATI_EXTRA_LONG_EEPROM << 25))
+
+/* should never be used */
+#define PATI_LOC_CFG_SPACE1_ATTR  ( \
+		PATI_LOC_CFG_BUS_SIZE | \
+		(PATI_LOC_CFG_TA_ENABLE << 6) | \
+		(PATI_LOC_CFG_NO_PREFETCH << 9) | \
+		(PATI_LOC_CFG_BURST << 8))
+
+
+/* SDRAM Area */
+#define PATI_LOC_SDRAM_ADDR		0x06000000		/* Local Address */
+#define PATI_LOC_SDRAM_MASK		0xFFF00000		/* 1MByte */
+/* Attributes */
+#define PATI_LOC_SDRAM_BUS_SIZE		PATI_BUS_SIZE_32  	/* 32 Bit */
+#define PATI_LOC_SDRAM_BURST		0  			/* No Burst */
+#define PATI_LOC_SDRAM_NO_PREFETCH	0  			/* Prefetch */
+#define PATI_LOC_SDRAM_TA_ENABLE	1  			/* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_SDRAM_SPACE0_ATTR  ( \
+		PATI_LOC_SDRAM_BUS_SIZE | \
+		(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
+		(PATI_LOC_SDRAM_NO_PREFETCH << 8) | \
+		(PATI_LOC_SDRAM_BURST << 24) | \
+		(PATI_EXTRA_LONG_EEPROM << 25))
+
+#define PATI_LOC_SDRAM_SPACE1_ATTR  ( \
+		PATI_LOC_SDRAM_BUS_SIZE | \
+		(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
+		(PATI_LOC_SDRAM_NO_PREFETCH << 9) | \
+		(PATI_LOC_SDRAM_BURST << 8))
+
+
+/* Flash Area */
+#define PATI_LOC_FLASH_ADDR		0x03000000		/* Local Address */
+#define PATI_LOC_FLASH_MASK		0xFFF00000		/* 1MByte */
+/* Attributes */
+#define PATI_LOC_FLASH_BUS_SIZE		PATI_BUS_SIZE_16  	/* 16 Bit */
+#define PATI_LOC_FLASH_BURST		0  			/* No Burst */
+#define PATI_LOC_FLASH_NO_PREFETCH	1  			/* No Prefetch */
+#define PATI_LOC_FLASH_TA_ENABLE	1  			/* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_FLASH_SPACE0_ATTR  ( \
+		PATI_LOC_FLASH_BUS_SIZE | \
+		(PATI_LOC_FLASH_TA_ENABLE << 6) | \
+		(PATI_LOC_FLASH_NO_PREFETCH << 8) | \
+		(PATI_LOC_FLASH_BURST << 24) | \
+		(PATI_EXTRA_LONG_EEPROM << 25))
+
+#define PATI_LOC_FLASH_SPACE1_ATTR  ( \
+		PATI_LOC_FLASH_BUS_SIZE | \
+		(PATI_LOC_FLASH_TA_ENABLE << 6) | \
+		(PATI_LOC_FLASH_NO_PREFETCH << 9) | \
+		(PATI_LOC_FLASH_BURST << 8))
+
+
+/* CPU Area */
+#define PATI_LOC_CPU_ADDR		0x01000000		/* Local Address */
+#define PATI_LOC_CPU_MASK		0xFFF00000		/* 1Mbyte */
+/* Attributes */
+#define PATI_LOC_CPU_BUS_SIZE		PATI_BUS_SIZE_32  	/* 32 Bit */
+#define PATI_LOC_CPU_BURST		0			/* No Burst */
+#define PATI_LOC_CPU_NO_PREFETCH	1			/* No Prefetch */
+#define PATI_LOC_CPU_TA_ENABLE		1			/* Enable TA */
+
+/* should never be used */
+#define PATI_LOC_CPU_SPACE0_ATTR  ( \
+		PATI_LOC_CPU_BUS_SIZE | \
+		(PATI_LOC_CPU_TA_ENABLE << 6) | \
+		(PATI_LOC_CPU_NO_PREFETCH << 8) | \
+		(PATI_LOC_CPU_BURST << 24) | \
+		(PATI_EXTRA_CPU_EEPROM << 25))
+
+#define PATI_LOC_CPU_SPACE1_ATTR  ( \
+		PATI_LOC_CPU_BUS_SIZE | \
+		(PATI_LOC_CPU_TA_ENABLE << 6) | \
+		(PATI_LOC_CPU_NO_PREFETCH << 9) | \
+		(PATI_LOC_CPU_BURST << 8))
+
+/***************************************************
+ * Hardware Config word definition
+ ***************************************************/
+#define BOOT_EXT_FLASH		0x00000000
+#define BOOT_INT_FLASH		0x00000004
+#define BOOT_FROM_PCI		0x00000006
+#define BOOT_FROM_SDRAM		0x00000005
+
+#define ENABLE_INT_ARB		0x00000008
+
+#define INITIAL_IRQ_PREF	0x00000010
+
+#define INITIAL_MEM_0M		0x00000000
+#define INITIAL_MEM_4M		0x00000080
+#define INITIAL_MEM_8M		0x00000040
+#define INITIAL_MEM_12M		0x000000C0
+#define INITIAL_MEM_16M		0x00000020
+#define INITIAL_MEM_20M		0x000000A0
+#define INITIAL_MEM_24M		0x00000060
+#define INITIAL_MEM_28M		0x000000E0
+/* CONF */
+#define INTERNAL_HWCONF		0x00000100
+/* PRPM */
+#define LOCAL_CPU_SLAVE		0x00000200
+/* BDIS */
+#define DISABLE_MEM_CNTR	0x00000400
+/* PCIM */
+#define PCI_MASTER_ONLY		0x00000800
+
+
+#define PATI_HW_START		((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
+#define PATI_HW_PCI_ONLY 	((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_CPU_ACC		((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
+#define PATI_HW_CPU_SLAVE 	((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
+
+/***************************************************
+ * Direct Master Config
+ ***************************************************/
+#define PATI_DMASTER_PCI_ADDR		0x01000000
+#define PATI_BUS_MASTER 1
+
+
+#define PATI_DMASTER_MASK 		0xFFF00000  /* 1MByte */
+#define PATI_DMASTER_ADDR 		0x01000000  /* Local Address */
+
+#define PATI_DMASTER_MEMORY_EN 		0x00000001 /* 0x00000001 */
+#define PATI_DMASTER_READ_AHEAD 	0x00000004 /* 0x00000004 */
+#define PATI_DMASTER_READ_NOT_AHEAD 	0x00000000 /* 0x00000004 */
+#define PATI_DMASTER_PRE_SIZE_CNTRL_0	0x00000000
+#define PATI_DMASTER_PRE_SIZE_CNTRL_4	0x00000008
+#define PATI_DMASTER_PRE_SIZE_CNTRL_8	0x00001000
+#define PATI_DMASTER_PRE_SIZE_CNTRL_16	0x00001008
+#define PATI_DMASTER_REL_PCI		0x00000000
+#define PATI_DMASTER_NOT_REL_PCI	0x00000010
+#define PATI_DMASTER_WR_INVAL		0x00000200
+#define PATI_DMASTER_NOT_WR_INVAL	0x00000000
+#define PATI_DMASTER_PRE_LIMIT		0x00000800
+#define PATI_DMASTER_PRE_CONT		0x00000000
+#define PATI_DMASTER_DELAY_WR_0		0x00000000
+#define PATI_DMASTER_DELAY_WR_4		0x00004000
+#define PATI_DMASTER_DELAY_WR_8		0x00008000
+#define PATI_DMASTER_DELAY_WR_16	0x0000C000
+
+#define PATI_DMASTER_PCI_ADDR_MASK	0xFFFF0000
+
+#define PATI_DMASTER_ATTR	\
+	PATI_DMASTER_MEMORY_EN | \
+	PATI_DMASTER_READ_AHEAD | \
+	PATI_DMASTER_PRE_SIZE_CNTRL_4 | \
+	PATI_DMASTER_REL_PCI | \
+	PATI_DMASTER_NOT_WR_INVAL | \
+	PATI_DMASTER_PRE_LIMIT | \
+	PATI_DMASTER_DELAY_WR_0
+
+
+#endif /* #ifndef __PATI_H_ */
diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h
new file mode 100755
index 0000000..9658808
--- /dev/null
+++ b/board/mpl/pati/pci_eeprom.h
@@ -0,0 +1,91 @@
+
+#ifndef __PCI_EEPROM_H_
+#define __PCI_EEPROM_H_	1
+
+#include "pati.h"
+/******************************************************************************
+ * Eeprom Support
+ ******************************************************************************/
+/**********************************************
+*               Definitions
+**********************************************/
+#define EE46_CMD_LEN    9       /* Bits in instructions */
+#define EE56_CMD_LEN    11      /* Bits in instructions */
+#define EE66_CMD_LEN    11      /* Bits in instructions */
+#define EE_READ         0x0180  /* 01 1000 0000 read instruction */
+#define EE_WRITE        0x0140  /* 01 0100 0000 write instruction */
+#define EE_WREN         0x0130  /* 01 0011 0000 write enable instruction */
+#define EE_WRALL        0x0110  /* 01 0001 0000 write all registers */
+#define EE_PRREAD       0x0180  /* 01 1000 0000 read address stored in Protect Register */
+#define EE_PRWRITE      0x0140  /* 01 0100 0000 write the address into PR */
+#define EE_WDS          0x0100  /* 01 0000 0000 write disable instruction */
+#define EE_PREN         0x0130  /* 01 0011 0000 protect enable instruction */
+#define EE_PRCLEAR      0x01FF  /* 01 1111 1111 clear protect register instr */
+#define EE_PRDS         0x0100  /* 01 0000 0000 ONE TIME ONLY, permenant */
+
+/***************************************************
+ * EEPROM
+ ***************************************************/
+#define LOW_WORD(x)	(((x) & 0xFFFF))
+#define HIGH_WORD(x)	(((x) >> 16) & 0xFFFF)
+
+typedef struct pci_eeprom_t {
+	unsigned short offset;
+	unsigned short value;
+} pci_eeprom;
+
+static pci_eeprom pati_eeprom[] = {
+	{ 0x00,PCI_DEVICE_ID_PATI }, 	/* PCI Device ID PCIIDR[31:16] */
+	{ 0x02,PCI_VENDOR_ID_MPL }, 	/* PCI Vendor ID PCIIDR[15:0] */
+	{ 0x04,PCI_CLASS_PROCESSOR_POWERPC }, 	/* PCI Class Code PCICCR[23:8] */
+	{ 0x06,0x00BA }, 	/* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
+	{ 0x08,0x0007 }, 	/* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
+	{ 0x0A,0x0100 }, 	/* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
+	{ 0x0C,0x0000 }, 	/* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
+	{ 0x0E,0x0000 }, 	/* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
+	{ 0x10,0x0000 }, 	/* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
+	{ 0x12,0x0000 }, 	/* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
+	{ 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, 	/* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
+	{ 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, 	/* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
+	{ 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, 	/* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
+	{ 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, 	/* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
+	{ 0x1C,0x0000 }, 	/* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
+	{ 0x1E,0x0000 }, 	/* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
+	{ 0x20,0x0030 }, 	/* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
+	{ 0x22,0x0510 }, 	/* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
+	{ 0x24,0x0000 }, 	/* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
+	{ 0x26,0x0000 }, 	/* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1]  */
+	{ 0x28,0x0000 }, 	/* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
+	{ 0x2A,0x0000 }, 	/* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
+	{ 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, 	/* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
+	{ 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, 	/* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
+	{ 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, 	/* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
+	{ 0x32,LOW_WORD(PATI_DMASTER_MASK) }, 	/* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
+	{ 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, 	/* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
+	{ 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, 	/* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
+	{ 0x38,0x0000 }, 	/* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
+	{ 0x3A,0x0000 }, 	/* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
+	{ 0x3C,0x0000 }, 	/* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
+	{ 0x3E,0x0000 }, 	/* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
+	{ 0x40,0x0000 }, 	/* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
+	{ 0x42,0x0000 }, 	/* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
+	{ 0x44,0x0000 }, 	/* PCI Subsystem ID PCISID[15:0] */
+	{ 0x46,0x0000 }, 	/* PCI Subsystem Vendor ID PCISVID[15:0] */
+	{ 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, 	/* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
+	{ 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, 	/* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
+	{ 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, 	/* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
+	{ 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, 	/* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
+	{ 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, 	/* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
+	{ 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, 	/* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
+	{ 0x54,0x0000 }, 	/* Hot Swap Control/Status (Reserved) Reserved */
+	{ 0x56,0x0000 }, 	/* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
+	{ 0x58,0x0000 }, 	/* Reserved Reserved */
+	{ 0x5A,0x0000 }, 	/* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
+	{ 0x5C,0x0000 }, 	/* Power Management Capabilities PMC[15:9, 2:0] */
+	{ 0x5E,0x0000 }, 	/* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
+	{ 0x60,0x0000 }, 	/* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
+	{ 0x62,0x0000 }, 	/* Power Management Control/Status PMCSR[14:8] */
+	{ 0xFFFF,0xFFFF} 	/* terminaror */
+};
+#define PATI_EEPROM_LAST_OFFSET	0x64
+#endif /* #ifndef __PCI_EEPROM_H_ */
diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h
new file mode 100755
index 0000000..cd4df18
--- /dev/null
+++ b/board/mpl/pati/plx9056.h
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter, d.peter@mpl.ch
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* PLX9096 register definitions
+*/
+#ifndef __PLX9056_H_
+#define __PLX9056_H_	1
+
+#include <pci.h>
+
+#ifdef PLX9056_LOC
+#define LOCAL_OFFSET					0x080
+/* PCI Config regs */
+#else
+#define LOCAL_OFFSET					0x000
+#endif
+
+#define PCI9056_VENDOR_ID            PCI_VENDOR_ID
+/*#define PCI9656_DEVICE_ID            PCI_DEVICE_ID */
+#define PCI9056_COMMAND              PCI_COMMAND
+/*#define PCI9656_STATUS               PCI_STATUS */
+#define PCI9056_REVISION             PCI_REVISION_ID
+
+#define PCI9056_CACHE_SIZE           PCI_CACHE_LINE_SIZE
+#define PCI9056_RTR_BASE             PCI_BASE_ADDRESS_0
+#define PCI9056_RTR_IO_BASE          PCI_BASE_ADDRESS_1
+#define PCI9056_LOCAL_BASE0          PCI_BASE_ADDRESS_2
+#define PCI9056_LOCAL_BASE1          PCI_BASE_ADDRESS_3
+#define PCI9056_UNUSED_BASE1         PCI_BASE_ADDRESS_4
+#define PCI9056_UNUSED_BASE2         PCI_BASE_ADDRESS_5
+#define PCI9056_CIS_PTR              PCI_CARDBUS_CIS
+#define PCI9056_SUB_ID               PCI_SUBSYSTEM_VENDOR_ID
+#define PCI9056_EXP_ROM_BASE         PCI_ROM_ADDRESS
+#define PCI9056_CAP_PTR              PCI_CAPABILITY_LIST
+#define PCI9056_INT_LINE             PCI_INTERRUPT_LINE
+
+#if defined(PLX9056_LOC)
+    #define PCI9056_PM_CAP_ID            0x180
+    #define PCI9056_PM_CSR               0x184
+    #define PCI9056_HS_CAP_ID            0x188
+    #define PCI9056_VPD_CAP_ID           0x18C
+    #define PCI9056_VPD_DATA             0x190
+#endif
+
+
+#define PCI_DEVICE_ID_PLX9056		0x9056
+
+/* Local Configuration Registers Accessible via the PCI Base address + Variable */
+#define PCI9056_SPACE0_RANGE         (0x000 + LOCAL_OFFSET)
+#define PCI9056_SPACE0_REMAP         (0x004 + LOCAL_OFFSET)
+#define PCI9056_LOCAL_DMA_ARBIT      (0x008 + LOCAL_OFFSET)
+#define PCI9056_ENDIAN_DESC          (0x00c + LOCAL_OFFSET)
+#define PCI9056_EXP_ROM_RANGE        (0x010 + LOCAL_OFFSET)
+#define PCI9056_EXP_ROM_REMAP        (0x014 + LOCAL_OFFSET)
+#define PCI9056_SPACE0_ROM_DESC      (0x018 + LOCAL_OFFSET)
+#define PCI9056_DM_RANGE             (0x01c + LOCAL_OFFSET)
+#define PCI9056_DM_MEM_BASE          (0x020 + LOCAL_OFFSET)
+#define PCI9056_DM_IO_BASE           (0x024 + LOCAL_OFFSET)
+#define PCI9056_DM_PCI_MEM_REMAP     (0x028 + LOCAL_OFFSET)
+#define PCI9056_DM_PCI_IO_CONFIG     (0x02c + LOCAL_OFFSET)
+#define PCI9056_SPACE1_RANGE         (0x0f0 + LOCAL_OFFSET)
+#define PCI9056_SPACE1_REMAP         (0x0f4 + LOCAL_OFFSET)
+#define PCI9056_SPACE1_DESC          (0x0f8 + LOCAL_OFFSET)
+#define PCI9056_DM_DAC               (0x0fc + LOCAL_OFFSET)
+
+#ifdef PLX9056_LOC
+#define PCI9056_ARBITER_CTRL         0x1A0
+#define PCI9056_ABORT_ADDRESS        0x1A4
+#endif
+
+/* Runtime registers  PCI Address + LOCAL_OFFSET */
+#ifdef PLX9056_LOC
+#define PCI9056_MAILBOX0				0x0C0
+#define PCI9056_MAILBOX1				0x0C4
+#else
+#define PCI9056_MAILBOX0				0x078
+#define PCI9056_MAILBOX1				0x07c
+#endif
+
+#define PCI9056_MAILBOX2				(0x048 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX3				(0x04c + LOCAL_OFFSET)
+#define PCI9056_MAILBOX4				(0x050 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX5				(0x054 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX6				(0x058 + LOCAL_OFFSET)
+#define PCI9056_MAILBOX7				(0x05c + LOCAL_OFFSET)
+#define PCI9056_PCI_TO_LOC_DBELL		(0x060 + LOCAL_OFFSET)
+#define PCI9056_LOC_TO_PCI_DBELL		(0x064 + LOCAL_OFFSET)
+#define PCI9056_INT_CTRL_STAT			(0x068 + LOCAL_OFFSET)
+#define PCI9056_EEPROM_CTRL_STAT		(0x06c + LOCAL_OFFSET)
+#define PCI9056_PERM_VENDOR_ID		(0x070 + LOCAL_OFFSET)
+#define PCI9056_REVISION_ID			(0x074 + LOCAL_OFFSET)
+
+#endif /* #ifndef __PLX9056_H_ */
diff --git a/board/mpl/pati/u-boot.lds b/board/mpl/pati/u-boot.lds
new file mode 100755
index 0000000..5b03fef
--- /dev/null
+++ b/board/mpl/pati/u-boot.lds
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2001	Wolfgang Denk, DENX Software Engineering, wd@denx.de
+ * (C) Copyright 2003	Martin Winistoerfer, martinwinistoerfer@gmx.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc5xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+/*   . = env_start;
+	.ppcenv	:
+	{
+		common/environment.o (.ppcenv)
+	}
+*/
+}
diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile
new file mode 100755
index 0000000..a818d08
--- /dev/null
+++ b/board/mpl/pip405/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o \
+	  ../common/flash.o cmd_pip405.o ../common/pci.o \
+	  ../common/isa.o ../common/kbd.o \
+	  ../common/usb_uhci.o \
+	  ../common/memtst.o ../common/common_util.o
+
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c
new file mode 100755
index 0000000..1bf4d7b
--- /dev/null
+++ b/board/mpl/pip405/cmd_pip405.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * hacked for PIP405
+ */
+
+#include <common.h>
+#include <command.h>
+#include "pip405.h"
+#include "../common/common_util.h"
+
+
+extern void print_pip405_info(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+
+/* ------------------------------------------------------------------------- */
+
+int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+
+ 	ulong led_on,led_nr;
+
+	if (strcmp(argv[1], "info") == 0)
+	{
+		print_pip405_info();
+	 	return 0;
+   	}
+ 	if (strcmp(argv[1], "led") == 0)
+	{
+		led_nr = (ulong)simple_strtoul(argv[2], NULL, 10);
+		led_on = (ulong)simple_strtoul(argv[3], NULL, 10);
+		if(!led_nr)
+			user_led0(led_on);
+		else
+			user_led1(led_on);
+		return 0;
+   	}
+
+	return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+U_BOOT_CMD(
+	pip405,	6,	1,	do_pip405,
+	"pip405  - PIP405 specific Cmds\n",
+	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
+	"pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n"
+	"pip405 flash mps - updates U-Boot with image from MPS\n"
+);
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pip405/config.mk b/board/mpl/pip405/config.mk
new file mode 100755
index 0000000..0f8d153
--- /dev/null
+++ b/board/mpl/pip405/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0xFFF80000
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
new file mode 100755
index 0000000..39f2ea5
--- /dev/null
+++ b/board/mpl/pip405/init.S
@@ -0,0 +1,230 @@
+/*------------------------------------------------------------------------------+
+ *
+ *      This source code has been made available to you by IBM on an AS-IS
+ *      basis.  Anyone receiving this source is licensed under IBM
+ *      copyrights to use it in any way he or she deems fit, including
+ *      copying it, modifying it, compiling it, and redistributing it either
+ *      with or without modifications.  No license under IBM patents or
+ *      patent applications is to be implied by the copyright license.
+ *
+ *      Any user of this software should understand that IBM cannot provide
+ *      technical support for this software and will not be responsible for
+ *      any consequences resulting from the use of this software.
+ *
+ *      Any person who transfers this source code or any derivative work
+ *      must include the IBM copyright notice, this paragraph, and the
+ *      preceding two paragraphs in the transferred software.
+ *
+ *      COPYRIGHT   I B M   CORPORATION 1995
+ *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *-------------------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------------
+ * Function:     ext_bus_cntlr_init
+ * Description:  Initializes the External Bus Controller for the external
+ *		peripherals. IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *	Bank 0 - Flash or Multi Purpose Socket
+ *	Bank 1 - Multi Purpose Socket or Flash
+ *	Bank 2 - not used
+ *	Bank 3 - not used
+ *	Bank 4 - not used
+ *	Bank 5 - not used
+ *	Bank 6 - used to switch on the 12V for the Multipurpose socket
+ *	Bank 7 - Config Register
+ *-----------------------------------------------------------------------------*/
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <configs/PIP405.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include "pip405.h"
+
+  .globl ext_bus_cntlr_init
+ ext_bus_cntlr_init:
+  mflr   r4                      /* save link register */
+  mfdcr  r3,strap                /* get strapping reg */
+  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
+  bnelr                          /* jump back if PCI boot */
+
+  bl      ..getAddr
+..getAddr:
+  mflr    r3                      /* get address of ..getAddr */
+  mtlr    r4                      /* restore link register */
+  addi    r4,0,14                 /* set ctr to 14; used to prefetch */
+  mtctr   r4                      /* 14 cache lines to fit this function */
+				   /* in cache (gives us 8x14=112 instrctns) */
+..ebcloop:
+  icbt    r0,r3                   /* prefetch cache line for addr in r3 */
+  addi    r3,r3,32								/* move to next cache line */
+  bdnz    ..ebcloop               /* continue for 14 cache lines */
+
+   /*-------------------------------------------------------------------
+    * Delay to ensure all accesses to ROM are complete before changing
+    * bank 0 timings.
+    *------------------------------------------------------------------- */
+	addis	r3,0,0x0
+  ori     r3,r3,0xA000
+  mtctr   r3
+..spinlp:
+  bdnz    ..spinlp                /* spin loop */
+
+	/*-----------------------------------------------------------------------
+	 * decide boot up mode
+	 *----------------------------------------------------------------------- */
+	addi		r4,0,pb0cr
+	mtdcr		ebccfga,r4
+	mfdcr		r4,ebccfgd
+
+	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
+	beq		0f				/* jump if 8 bit bus width */
+
+	/* setup 16 bit things
+   *-----------------------------------------------------------------------
+   * Memory Bank 0 (16 Bit Flash) initialization
+   *---------------------------------------------------------------------- */
+
+	addi    r4,0,pb0ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,(FLASH_AP_B)@h
+	ori     r4,r4,(FLASH_AP_B)@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(FLASH_CR_B)@h
+	ori     r4,r4,(FLASH_CR_B)@l
+	mtdcr   ebccfgd,r4
+	b				1f
+
+0:
+	/* 8Bit boot mode: */
+	/*-----------------------------------------------------------------------
+	* Memory Bank 0 Multi Purpose Socket initialization
+	*----------------------------------------------------------------------- */
+	/* 0x7F8FFE80 slowest boot */
+	addi    r4,0,pb0ap
+	mtdcr   ebccfga,r4
+	addis   r4,0,(MPS_AP_B)@h
+	ori     r4,r4,(MPS_AP_B)@l
+	mtdcr   ebccfgd,r4
+
+	addi    r4,0,pb0cr
+	mtdcr   ebccfga,r4
+	/* BS=0x010(4MB),BU=0x3(R/W), */
+	addis   r4,0,(MPS_CR_B)@h
+	ori     r4,r4,(MPS_CR_B)@l
+	mtdcr   ebccfgd,r4
+
+
+1:
+  /*-----------------------------------------------------------------------
+   * Memory Bank 2-3-4-5-6 (not used) initialization
+   *-----------------------------------------------------------------------*/
+  addi    r4,0,pb1cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb2cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb3cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb4cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb5cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb6cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+
+  addi    r4,0,pb7cr
+  mtdcr   ebccfga,r4
+  addis   r4,0,0x0000
+  ori     r4,r4,0x0000
+  mtdcr   ebccfgd,r4
+  nop				/* pass2 DCR errata #8 */
+  blr
+
+/*-----------------------------------------------------------------------------
+ * Function:     sdram_init
+ * Description:  Configures the internal SRAM memory. and setup the
+ *               Stackpointer in it.
+ *----------------------------------------------------------------------------- */
+	.globl  sdram_init
+
+sdram_init:
+
+
+  blr
+
+
+#if defined(CONFIG_BOOT_PCI)
+    .section .bootpg,"ax"
+    .globl _start_pci
+/*******************************************
+ */
+
+_start_pci:
+  /* first handle errata #68 / PCI_18 */
+  iccci   r0, r0          /* invalidate I-cache */
+  lis     r31, 0
+  mticcr  r31             /* ICCR = 0 (all uncachable) */
+  isync
+
+  mfccr0  r28             /* set CCR0[24] = 1 */
+  ori     r28, r28, 0x0080
+  mtccr0  r28
+
+  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
+  lis     r28, 0xEF40
+  addi    r28, r28, 0x0004
+  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
+  lis     r29, 0xFFF8     /* open 512 kByte */
+  addi    r29, r29, 0x0001/* and enable this region */
+  stwbrx  r29, r0, r28    /* write PMM0MA */
+
+  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
+  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
+
+  lis     r31, 0x8000     /* set en bit bus 0 */
+  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
+  stwbrx  r31, r0, r28    /* write it */
+
+  lwbrx   r31, r0, r29    /* load XBCS register */
+  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
+  stwbrx  r31, r0, r29    /* write back XBCS register */
+
+  nop
+  nop
+  b	_start		/* normal start */
+#endif
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
new file mode 100755
index 0000000..a398362
--- /dev/null
+++ b/board/mpl/pip405/pip405.c
@@ -0,0 +1,960 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * TODO: clean-up
+ */
+
+#include <common.h>
+#include "pip405.h"
+#include <asm/processor.h>
+#include <i2c.h>
+#include "../common/isa.h"
+#include "../common/common_util.h"
+
+#undef SDRAM_DEBUG
+
+#define FALSE           0
+#define TRUE            1
+
+/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
+#ifndef __ldiv_t_defined
+typedef struct {
+	long int quot;		/* Quotient */
+	long int rem;		/* Remainder    */
+} ldiv_t;
+extern ldiv_t ldiv (long int __numer, long int __denom);
+
+# define __ldiv_t_defined	1
+#endif
+
+
+typedef enum {
+	SDRAM_NO_ERR,
+	SDRAM_SPD_COMM_ERR,
+	SDRAM_SPD_CHKSUM_ERR,
+	SDRAM_UNSUPPORTED_ERR,
+	SDRAM_UNKNOWN_ERR
+} SDRAM_ERR;
+
+typedef struct {
+	const unsigned char mode;
+	const unsigned char row;
+	const unsigned char col;
+	const unsigned char bank;
+} SDRAM_SETUP;
+
+static const SDRAM_SETUP sdram_setup_table[] = {
+	{1, 11, 9, 2},
+	{1, 11, 10, 2},
+	{2, 12, 9, 4},
+	{2, 12, 10, 4},
+	{3, 13, 9, 4},
+	{3, 13, 10, 4},
+	{3, 13, 11, 4},
+	{4, 12, 8, 2},
+	{4, 12, 8, 4},
+	{5, 11, 8, 2},
+	{5, 11, 8, 4},
+	{6, 13, 8, 2},
+	{6, 13, 8, 4},
+	{7, 13, 9, 2},
+	{7, 13, 10, 2},
+	{0, 0, 0, 0}
+};
+
+static const unsigned char cal_indextable[] = {
+	9, 23, 25
+};
+
+
+/*
+ * translate ns.ns/10 coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
+{
+	unsigned short ns, ns10;
+
+	/* isolate upper nibble */
+	ns = (spd_byte >> 4) & 0x0F;
+	/* isolate lower nibble */
+	ns10 = (spd_byte & 0x0F);
+
+	return (ns * 100 + ns10 * 10);
+}
+
+/*
+ * translate ns.ns/4 coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
+{
+	unsigned short ns, ns4;
+
+	/* isolate upper 6 bits */
+	ns = (spd_byte >> 2) & 0x3F;
+	/* isloate lower 2 bits */
+	ns4 = (spd_byte & 0x03);
+
+	return (ns * 100 + ns4 * 25);
+}
+
+/*
+ * translate ns coding of SPD timing values
+ * into 10 ps unit values
+ */
+
+unsigned short NSto10PS (unsigned char spd_byte)
+{
+	return (spd_byte * 100);
+}
+
+void SDRAM_err (const char *s)
+{
+#ifndef SDRAM_DEBUG
+	DECLARE_GLOBAL_DATA_PTR;
+
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+#endif
+	serial_puts ("\n");
+	serial_puts (s);
+	serial_puts ("\n enable SDRAM_DEBUG for more info\n");
+	for (;;);
+}
+
+
+#ifdef SDRAM_DEBUG
+
+void write_hex (unsigned char i)
+{
+	char cc;
+
+	cc = i >> 4;
+	cc &= 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+	cc = i & 0xf;
+	if (cc > 9)
+		serial_putc (cc + 55);
+	else
+		serial_putc (cc + 48);
+}
+
+void write_4hex (unsigned long val)
+{
+	write_hex ((unsigned char) (val >> 24));
+	write_hex ((unsigned char) (val >> 16));
+	write_hex ((unsigned char) (val >> 8));
+	write_hex ((unsigned char) val);
+}
+
+#endif
+
+int board_early_init_f (void)
+{
+	unsigned char dataout[1];
+	unsigned char datain[128];
+	unsigned long sdram_size = 0;
+	SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
+	unsigned long memclk;
+	unsigned long tmemclk = 0;
+	unsigned long tmp, bank, baseaddr, bank_size;
+	unsigned short i;
+	unsigned char rows, cols, banks, sdram_banks, density;
+	unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
+			trc_clocks, tctp_clocks;
+	unsigned char cal_index, cal_val, spd_version, spd_chksum;
+	unsigned char buf[8];
+#ifdef SDRAM_DEBUG
+	DECLARE_GLOBAL_DATA_PTR;
+#endif
+	/* set up the config port */
+	mtdcr (ebccfga, pb7ap);
+	mtdcr (ebccfgd, CONFIG_PORT_AP);
+	mtdcr (ebccfga, pb7cr);
+	mtdcr (ebccfgd, CONFIG_PORT_CR);
+
+	memclk = get_bus_freq (tmemclk);
+	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
+
+#ifdef SDRAM_DEBUG
+	(void) get_clocks ();
+	gd->baudrate = 9600;
+	serial_init ();
+	serial_puts ("\nstart SDRAM Setup\n");
+#endif
+
+	/* Read Serial Presence Detect Information */
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	dataout[0] = 0;
+	for (i = 0; i < 128; i++)
+		datain[i] = 127;
+	i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
+#ifdef SDRAM_DEBUG
+	serial_puts ("\ni2c_read returns ");
+	write_hex (i);
+	serial_puts ("\n");
+#endif
+
+#ifdef SDRAM_DEBUG
+	for (i = 0; i < 128; i++) {
+		write_hex (datain[i]);
+		serial_puts (" ");
+		if (((i + 1) % 16) == 0)
+			serial_puts ("\n");
+	}
+	serial_puts ("\n");
+#endif
+	spd_chksum = 0;
+	for (i = 0; i < 63; i++) {
+		spd_chksum += datain[i];
+	}							/* endfor */
+	if (datain[63] != spd_chksum) {
+#ifdef SDRAM_DEBUG
+		serial_puts ("SPD chksum: 0x");
+		write_hex (datain[63]);
+		serial_puts (" != calc. chksum: 0x");
+		write_hex (spd_chksum);
+		serial_puts ("\n");
+#endif
+		SDRAM_err ("SPD checksum Error");
+	}
+	/* SPD seems to be ok, use it */
+
+	/* get SPD version */
+	spd_version = datain[62];
+
+	/* do some sanity checks on the kind of RAM */
+	if ((datain[0] < 0x80) ||	/* less than 128 valid bytes in SPD */
+		(datain[2] != 0x04) ||	/* if not SDRAM */
+		(!((datain[6] == 0x40) || (datain[6] == 0x48))) ||	/* or not (64 Bit or 72 Bit)  */
+		(datain[7] != 0x00) || (datain[8] != 0x01) ||	/* or not LVTTL signal levels */
+		(datain[126] == 0x66))	/* or a 66Mhz modules */
+		SDRAM_err ("unsupported SDRAM");
+#ifdef SDRAM_DEBUG
+	serial_puts ("SDRAM sanity ok\n");
+#endif
+
+	/* get number of rows/cols/banks out of byte 3+4+5 */
+	rows = datain[3];
+	cols = datain[4];
+	banks = datain[5];
+
+	/* get number of SDRAM banks out of byte 17 and
+	   supported CAS latencies out of byte 18 */
+	sdram_banks = datain[17];
+	supported_cal = datain[18] & ~0x81;
+
+	while (t->mode != 0) {
+		if ((t->row == rows) && (t->col == cols)
+			&& (t->bank == sdram_banks))
+			break;
+		t++;
+	}							/* endwhile */
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("rows: ");
+	write_hex (rows);
+	serial_puts (" cols: ");
+	write_hex (cols);
+	serial_puts (" banks: ");
+	write_hex (banks);
+	serial_puts (" mode: ");
+	write_hex (t->mode);
+	serial_puts ("\n");
+#endif
+	if (t->mode == 0)
+		SDRAM_err ("unsupported SDRAM");
+	/* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
+#ifdef SDRAM_DEBUG
+	serial_puts ("tRP: ");
+	write_hex (datain[27]);
+	serial_puts ("\ntRCD: ");
+	write_hex (datain[29]);
+	serial_puts ("\ntRAS: ");
+	write_hex (datain[30]);
+	serial_puts ("\n");
+#endif
+
+	trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
+	trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
+	tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
+	density = datain[31];
+
+	/* trc_clocks is sum of trp_clocks + tras_clocks */
+	trc_clocks = trp_clocks + tras_clocks;
+	/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
+	tctp_clocks =
+			((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
+			 (tmemclk - 1)) / tmemclk;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("c_RP: ");
+	write_hex (trp_clocks);
+	serial_puts ("\nc_RCD: ");
+	write_hex (trcd_clocks);
+	serial_puts ("\nc_RAS: ");
+	write_hex (tras_clocks);
+	serial_puts ("\nc_RC: (RP+RAS): ");
+	write_hex (trc_clocks);
+	serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
+	write_hex (tctp_clocks);
+	serial_puts ("\nt_CTP: RAS - RCD: ");
+	write_hex ((unsigned
+				char) ((NSto10PS (datain[30]) -
+						NSto10PS (datain[29])) >> 8));
+	write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
+	serial_puts ("\ntmemclk: ");
+	write_hex ((unsigned char) (tmemclk >> 8));
+	write_hex ((unsigned char) (tmemclk));
+	serial_puts ("\n");
+#endif
+
+
+	cal_val = 255;
+	for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
+		/* is this CAS latency supported ? */
+		if ((supported_cal >> i) & 0x01) {
+			buf[0] = datain[cal_indextable[cal_index]];
+			if (cal_index < 2) {
+				if (NS10to10PS (buf[0], spd_version) <= tmemclk)
+					cal_val = i;
+			} else {
+				/* SPD bytes 25+26 have another format */
+				if (NS4to10PS (buf[0], spd_version) <= tmemclk)
+					cal_val = i;
+			}	/* endif */
+			cal_index++;
+		}	/* endif */
+	}	/* endfor */
+#ifdef SDRAM_DEBUG
+	serial_puts ("CAL: ");
+	write_hex (cal_val + 1);
+	serial_puts ("\n");
+#endif
+
+	if (cal_val == 255)
+		SDRAM_err ("unsupported SDRAM");
+
+	/* get SDRAM timing register */
+	mtdcr (memcfga, mem_sdtr1);
+	tmp = mfdcr (memcfgd) & ~0x018FC01F;
+	/* insert CASL value */
+/*  tmp |= ((unsigned long)cal_val) << 23; */
+	tmp |= ((unsigned long) cal_val) << 23;
+	/* insert PTA value */
+	tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
+	/* insert CTP value */
+/*  tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
+	tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
+	/* insert LDF (always 01) */
+	tmp |= ((unsigned long) 0x01) << 14;
+	/* insert RFTA value */
+	tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
+	/* insert RCD value */
+	tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("sdtr: ");
+	write_4hex (tmp);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM timing register */
+	mtdcr (memcfga, mem_sdtr1);
+	mtdcr (memcfgd, tmp);
+	baseaddr = CFG_SDRAM_BASE;
+	bank_size = (((unsigned long) density) << 22) / 2;
+	/* insert AM value */
+	tmp = ((unsigned long) t->mode - 1) << 13;
+	/* insert SZ value; */
+	switch (bank_size) {
+	case 0x00400000:
+		tmp |= ((unsigned long) 0x00) << 17;
+		break;
+	case 0x00800000:
+		tmp |= ((unsigned long) 0x01) << 17;
+		break;
+	case 0x01000000:
+		tmp |= ((unsigned long) 0x02) << 17;
+		break;
+	case 0x02000000:
+		tmp |= ((unsigned long) 0x03) << 17;
+		break;
+	case 0x04000000:
+		tmp |= ((unsigned long) 0x04) << 17;
+		break;
+	case 0x08000000:
+		tmp |= ((unsigned long) 0x05) << 17;
+		break;
+	case 0x10000000:
+		tmp |= ((unsigned long) 0x06) << 17;
+		break;
+	default:
+		SDRAM_err ("unsupported SDRAM");
+	}	/* endswitch */
+	/* get SDRAM bank 0 register */
+	mtdcr (memcfga, mem_mb0cf);
+	bank = mfdcr (memcfgd) & ~0xFFCEE001;
+	bank |= (baseaddr | tmp | 0x01);
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank0: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+	serial_puts (" mb0cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+	baseaddr += bank_size;
+	sdram_size += bank_size;
+
+	/* write SDRAM bank 0 register */
+	mtdcr (memcfga, mem_mb0cf);
+	mtdcr (memcfgd, bank);
+
+	/* get SDRAM bank 1 register */
+	mtdcr (memcfga, mem_mb1cf);
+	bank = mfdcr (memcfgd) & ~0xFFCEE001;
+	sdram_size = 0;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank1: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+#endif
+	if (banks == 2) {
+		bank |= (baseaddr | tmp | 0x01);
+		baseaddr += bank_size;
+		sdram_size += bank_size;
+	}	/* endif */
+#ifdef SDRAM_DEBUG
+	serial_puts (" mb1cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+	/* write SDRAM bank 1 register */
+	mtdcr (memcfga, mem_mb1cf);
+	mtdcr (memcfgd, bank);
+
+	/* get SDRAM bank 2 register */
+	mtdcr (memcfga, mem_mb2cf);
+	bank = mfdcr (memcfgd) & ~0xFFCEE001;
+
+	bank |= (baseaddr | tmp | 0x01);
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank2: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+	serial_puts (" mb2cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+
+	baseaddr += bank_size;
+	sdram_size += bank_size;
+
+	/* write SDRAM bank 2 register */
+	mtdcr (memcfga, mem_mb2cf);
+	mtdcr (memcfgd, bank);
+
+	/* get SDRAM bank 3 register */
+	mtdcr (memcfga, mem_mb3cf);
+	bank = mfdcr (memcfgd) & ~0xFFCEE001;
+
+#ifdef SDRAM_DEBUG
+	serial_puts ("bank3: baseaddr: ");
+	write_4hex (baseaddr);
+	serial_puts (" banksize: ");
+	write_4hex (bank_size);
+#endif
+
+	if (banks == 2) {
+		bank |= (baseaddr | tmp | 0x01);
+		baseaddr += bank_size;
+		sdram_size += bank_size;
+	}
+	/* endif */
+#ifdef SDRAM_DEBUG
+	serial_puts (" mb3cf: ");
+	write_4hex (bank);
+	serial_puts ("\n");
+#endif
+
+	/* write SDRAM bank 3 register */
+	mtdcr (memcfga, mem_mb3cf);
+	mtdcr (memcfgd, bank);
+
+
+	/* get SDRAM refresh interval register */
+	mtdcr (memcfga, mem_rtr);
+	tmp = mfdcr (memcfgd) & ~0x3FF80000;
+
+	if (tmemclk < NSto10PS (16))
+		tmp |= 0x05F00000;
+	else
+		tmp |= 0x03F80000;
+
+	/* write SDRAM refresh interval register */
+	mtdcr (memcfga, mem_rtr);
+	mtdcr (memcfgd, tmp);
+
+	/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
+	mtdcr (memcfga, mem_mcopt1);
+	tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000;
+	mtdcr (memcfga, mem_mcopt1);
+	mtdcr (memcfgd, tmp);
+
+
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the PIP405 board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
+   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
+   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for PIP405 board:
+   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that
+   |       the Interrupt Controller in the South Bridge has caused the
+   |       interrupt. The IC must be read to determine which device
+   |       caused the interrupt.
+   |
+   +-------------------------------------------------------------------------*/
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical (for now) */
+	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char s[50];
+	unsigned char bc;
+	int i;
+	backup_t *b = (backup_t *) s;
+
+	puts ("Board: ");
+
+	i = getenv_r ("serial#", (char *)s, 32);
+	if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
+		get_backup_values (b);
+		if (strncmp (b->signature, "MPL\0", 4) != 0) {
+			puts ("### No HW ID - assuming PIP405");
+		} else {
+			b->serial_name[6] = 0;
+			printf ("%s SN: %s", b->serial_name,
+				&b->serial_name[7]);
+		}
+	} else {
+		s[6] = 0;
+		printf ("%s SN: %s", s, &s[7]);
+	}
+	bc = in8 (CONFIG_PORT_ADDR);
+	printf (" Boot Config: 0x%x\n", bc);
+	return (0);
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+/*
+  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  the necessary info for SDRAM controller configuration
+*/
+/* ------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------- */
+static int test_dram (unsigned long ramsize);
+
+long int initdram (int board_type)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	unsigned long bank_reg[4], tmp, bank_size;
+	int i, ds;
+	unsigned long TotalSize;
+
+	ds = 0;
+	/* since the DRAM controller is allready set up,
+	 * calculate the size with the bank registers
+	 */
+	mtdcr (memcfga, mem_mb0cf);
+	bank_reg[0] = mfdcr (memcfgd);
+	mtdcr (memcfga, mem_mb1cf);
+	bank_reg[1] = mfdcr (memcfgd);
+	mtdcr (memcfga, mem_mb2cf);
+	bank_reg[2] = mfdcr (memcfgd);
+	mtdcr (memcfga, mem_mb3cf);
+	bank_reg[3] = mfdcr (memcfgd);
+	TotalSize = 0;
+	for (i = 0; i < 4; i++) {
+		if ((bank_reg[i] & 0x1) == 0x1) {
+			tmp = (bank_reg[i] >> 17) & 0x7;
+			bank_size = 4 << tmp;
+			TotalSize += bank_size;
+		} else
+			ds = 1;
+	}
+	if (ds == 1)
+		printf ("single-sided DIMM ");
+	else
+		printf ("double-sided DIMM ");
+	test_dram (TotalSize * 1024 * 1024);
+	/* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
+	(void) get_clocks();
+	if (gd->cpu_clk > 220000000)
+		TotalSize /= 2;
+	return (TotalSize * 1024 * 1024);
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+static int test_dram (unsigned long ramsize)
+{
+	/* not yet implemented */
+	return (1);
+}
+
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart=0-flash_info[0].size;
+	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+	gd->bd->bi_flashoffset=0;
+
+	/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
+	if (mfdcr(strap) & PSR_ROM_LOC)
+	       mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+
+	return (0);
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+
+int overwrite_console (void)
+{
+	return (in8 (CONFIG_PORT_ADDR) & 0x1);	/* return TRUE if console should be overwritten */
+}
+
+
+extern int isa_init (void);
+
+
+void print_pip405_rev (void)
+{
+	unsigned char part, vers, cfg;
+
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	cfg = in8 (PLD_BOARD_CFG_REG);
+	printf ("Rev:   PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
+			16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
+			vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
+}
+
+extern void check_env(void);
+
+
+int last_stage_init (void)
+{
+	print_pip405_rev ();
+	isa_init ();
+	show_stdio_dev ();
+	check_env();
+	return 0;
+}
+
+/************************************************************************
+* Print PIP405 Info
+************************************************************************/
+void print_pip405_info (void)
+{
+	unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
+			compwr, nicvga, scsirst;
+
+	part = in8 (PLD_PART_REG);
+	vers = in8 (PLD_VERS_REG);
+	cfg = in8 (PLD_BOARD_CFG_REG);
+	ledu = in8 (PLD_LED_USER_REG);
+	sysman = in8 (PLD_SYS_MAN_REG);
+	flashcom = in8 (PLD_FLASH_COM_REG);
+	can = in8 (PLD_CAN_REG);
+	serpwr = in8 (PLD_SER_PWR_REG);
+	compwr = in8 (PLD_COM_PWR_REG);
+	nicvga = in8 (PLD_NIC_VGA_REG);
+	scsirst = in8 (PLD_SCSI_RST_REG);
+	printf ("PLD Part %d version %d\n",
+		part & 0xf, vers & 0xf);
+	printf ("PLD Part %d version %d\n",
+		(part >> 4) & 0xf, (vers >> 4) & 0xf);
+	printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
+	printf ("Population Options %d %d %d %d\n",
+		(cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
+		(cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
+	printf ("User LED0 %s User LED1 %s\n",
+		((ledu & 0x1) == 0x1) ? "on" : "off",
+		((ledu & 0x2) == 0x2) ? "on" : "off");
+	printf ("Additionally Options %d %d\n",
+		(ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
+	printf ("User Config Switch %d %d %d %d\n",
+		(ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
+		(ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
+	switch (sysman & 0x3) {
+	case 0:
+		printf ("PCI Clocks are running\n");
+		break;
+	case 1:
+		printf ("PCI Clocks are stopped in POS State\n");
+		break;
+	case 2:
+		printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
+		break;
+	case 3:
+		printf ("PCI Clocks are stopped\n");
+		break;
+	}
+	switch ((sysman >> 2) & 0x3) {
+	case 0:
+		printf ("Main Clocks are running\n");
+		break;
+	case 1:
+		printf ("Main Clocks are stopped in POS State\n");
+		break;
+	case 2:
+	case 3:
+		printf ("PCI Clocks are stopped\n");
+		break;
+	}
+	printf ("INIT asserts %sINT2# (SMI)\n",
+			((sysman & 0x10) == 0x10) ? "" : "not ");
+	printf ("INIT asserts %sINT1# (NMI)\n",
+			((sysman & 0x20) == 0x20) ? "" : "not ");
+	printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
+	printf ("SER1 is routed to %s\n",
+			((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
+	printf ("COM2 is routed to %s\n",
+			((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
+	printf ("RS485 is configured as %s duplex\n",
+			((flashcom & 0x4) == 0x4) ? "full" : "half");
+	printf ("RS485 is connected to %s\n",
+			((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
+	printf ("SER1 uses handshakes %s\n",
+			((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
+	printf ("Bootflash is %swriteprotected\n",
+			((flashcom & 0x20) == 0x20) ? "not " : "");
+	printf ("Bootflash VPP is %s\n",
+			((flashcom & 0x40) == 0x40) ? "on" : "off");
+	printf ("Bootsector is %swriteprotected\n",
+			((flashcom & 0x80) == 0x80) ? "not " : "");
+	switch ((can) & 0x3) {
+	case 0:
+		printf ("CAN Controller is on address 0x1000..0x10FF\n");
+		break;
+	case 1:
+		printf ("CAN Controller is on address 0x8000..0x80FF\n");
+		break;
+	case 2:
+		printf ("CAN Controller is on address 0xE000..0xE0FF\n");
+		break;
+	case 3:
+		printf ("CAN Controller is disabled\n");
+		break;
+	}
+	switch ((can >> 2) & 0x3) {
+	case 0:
+		printf ("CAN Controller Reset is ISA Reset\n");
+		break;
+	case 1:
+		printf ("CAN Controller Reset is ISA Reset and POS State\n");
+		break;
+	case 2:
+	case 3:
+		printf ("CAN Controller is in reset\n");
+		break;
+	}
+	if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
+		printf ("CAN Interrupt is disabled\n");
+	else
+		printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
+	switch (serpwr & 0x3) {
+	case 0:
+		printf ("SER0 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("SER0 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("SER0 Drivers are disabled\n");
+		break;
+	}
+	switch ((serpwr >> 2) & 0x3) {
+	case 0:
+		printf ("SER1 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("SER1 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("SER1 Drivers are disabled\n");
+		break;
+	}
+	switch (compwr & 0x3) {
+	case 0:
+		printf ("COM1 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("COM1 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("COM1 Drivers are disabled\n");
+		break;
+	}
+	switch ((compwr >> 2) & 0x3) {
+	case 0:
+		printf ("COM2 Drivers are enabled\n");
+		break;
+	case 1:
+		printf ("COM2 Drivers are disabled in the POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("COM2 Drivers are disabled\n");
+		break;
+	}
+	switch ((nicvga) & 0x3) {
+	case 0:
+		printf ("PHY is running\n");
+		break;
+	case 1:
+		printf ("PHY is in Power save mode in POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("PHY is in Power save mode\n");
+		break;
+	}
+	switch ((nicvga >> 2) & 0x3) {
+	case 0:
+		printf ("VGA is running\n");
+		break;
+	case 1:
+		printf ("VGA is in Power save mode in POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("VGA is in Power save mode\n");
+		break;
+	}
+	printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
+	printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
+	printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
+			(nicvga >> 7) & 0x1);
+	switch ((scsirst) & 0x3) {
+	case 0:
+		printf ("SCSI Controller is running\n");
+		break;
+	case 1:
+		printf ("SCSI Controller is in Power save mode in POS state\n");
+		break;
+	case 2:
+	case 3:
+		printf ("SCSI Controller is in Power save mode\n");
+		break;
+	}
+	printf ("SCSI termination is %s\n",
+			((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
+	printf ("SCSI Controller is %sreseted\n",
+			((scsirst & 0x10) == 0x10) ? "" : "not ");
+	printf ("IDE disks are %sreseted\n",
+			((scsirst & 0x20) == 0x20) ? "" : "not ");
+	printf ("ISA Bus is %sreseted\n",
+			((scsirst & 0x40) == 0x40) ? "" : "not ");
+	printf ("Super IO is %sreseted\n",
+			((scsirst & 0x80) == 0x80) ? "" : "not ");
+}
+
+void user_led0 (unsigned char on)
+{
+	if (on == TRUE)
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
+	else
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
+}
+
+void user_led1 (unsigned char on)
+{
+	if (on == TRUE)
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
+	else
+		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
+}
+
+void ide_set_reset (int idereset)
+{
+	/* if reset = 1 IDE reset will be asserted */
+	unsigned char resreg;
+
+	resreg = in8 (PLD_SCSI_RST_REG);
+	if (idereset == 1)
+		resreg |= 0x20;
+	else {
+		udelay(10000);
+		resreg &= 0xdf;
+	}
+	out8 (PLD_SCSI_RST_REG, resreg);
+}
diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
new file mode 100755
index 0000000..b41c5bb
--- /dev/null
+++ b/board/mpl/pip405/pip405.h
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ /****************************************************************************
+ * Global routines used for PIP405
+ *****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
+
+void print_pip405_info(void);
+
+void user_led0(unsigned char on);
+void user_led1(unsigned char on);
+
+
+#define PLD_BASE_ADDRESS		CFG_ISA_IO_BASE_ADDRESS + 0x800
+#define PLD_PART_REG			PLD_BASE_ADDRESS + 0
+#define PLD_VERS_REG			PLD_BASE_ADDRESS + 1
+#define PLD_BOARD_CFG_REG		PLD_BASE_ADDRESS + 2
+#define PLD_LED_USER_REG		PLD_BASE_ADDRESS + 3
+#define PLD_SYS_MAN_REG			PLD_BASE_ADDRESS + 4
+#define PLD_FLASH_COM_REG		PLD_BASE_ADDRESS + 5
+#define PLD_CAN_REG			PLD_BASE_ADDRESS + 6
+#define PLD_SER_PWR_REG			PLD_BASE_ADDRESS + 7
+#define PLD_COM_PWR_REG			PLD_BASE_ADDRESS + 8
+#define PLD_NIC_VGA_REG			PLD_BASE_ADDRESS + 9
+#define PLD_SCSI_RST_REG		PLD_BASE_ADDRESS + 0xA
+
+#define PIIX4_VENDOR_ID			0x8086
+#define PIIX4_IDE_DEV_ID		0x7111
+
+#endif
+
+/* timings */
+
+/* CS Config register (CS7) */
+#define CONFIG_PORT_BME	0 	/* Burst disable */
+#define CONFIG_PORT_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
+#define CONFIG_PORT_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define CONFIG_PORT_OEN	1	/* Cycles from CS low to OE low   */
+#define CONFIG_PORT_WBN	1	/* Cycles from CS low to WE low   */
+#define CONFIG_PORT_WBF	1	/* Cycles from WE high to CS high */
+#define CONFIG_PORT_TH	2	/* Number of hold cycles after transfer */
+#define CONFIG_PORT_RE	0	/* Ready disabled */
+#define CONFIG_PORT_SOR	1	/* Sample on Ready disabled */
+#define CONFIG_PORT_BEM	0	/* Byte Write only active on Write cycles */
+#define CONFIG_PORT_PEN	0	/* Parity disable */
+#define CONFIG_PORT_AP 	((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
+				(CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define CONFIG_PORT_BS	0	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define CONFIG_PORT_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define CONFIG_PORT_BW	0	/* 16Bit */
+#define CONFIG_PORT_CR	((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
+
+/* Flash CS0 or CS 1 */
+/* 0x7F8FFE80 slowest timing at all... */
+#define FLASH_BME_B	1 	/* Burst enable */
+#define FLASH_FWT_B	0x6	/* 6 * 30ns 210ns First Wait Access */
+#define FLASH_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
+#define FLASH_BME	0 	/* Burst disable */
+#define FLASH_TWE	0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define FLASH_CSN	0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define FLASH_OEN	1	/* Cycles from CS low to OE low   */
+#define FLASH_WBN	1	/* Cycles from CS low to WE low   */
+#define FLASH_WBF	1	/* Cycles from WE high to CS high */
+#define FLASH_TH	2	/* Number of hold cycles after transfer */
+#define FLASH_RE	0	/* Ready disabled */
+#define FLASH_SOR	1	/* Sample on Ready disabled */
+#define FLASH_BEM	0	/* Byte Write only active on Write cycles */
+#define FLASH_PEN	0	/* Parity disable */
+/* Access Parameter Register for non Boot */
+#define FLASH_AP 	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+/* Access Parameter Register for Boot */
+#define FLASH_AP_B 	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define FLASH_BU	3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define FLASH_BW	1	/* 16Bit */
+/* CR register for Boot */
+#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+/* CR register for non Boot */
+#define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
+
+/* MPS CS1 or CS0 */
+/* Boot CS: */
+#define MPS_BME_B	1 	/* Burst enable */
+#define MPS_FWT_B	0x6/* 6 * 30ns 210ns First Wait Access */
+#define MPS_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
+#define MPS_BME		0 	/* Burst disable */
+#define MPS_TWE		0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
+#define MPS_CSN		0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
+#define MPS_OEN		1	/* Cycles from CS low to OE low   */
+#define MPS_WBN		1	/* Cycles from CS low to WE low   */
+#define MPS_WBF		1	/* Cycles from WE high to CS high */
+#define MPS_TH		2	/* Number of hold cycles after transfer */
+#define MPS_RE		0	/* Ready disabled */
+#define MPS_SOR		1	/* Sample on Ready disabled */
+#define MPS_BEM		0	/* Byte Write only active on Write cycles */
+#define MPS_PEN		0	/* Parity disable */
+/* Access Parameter Register for non Boot */
+#define MPS_AP 		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+/* Access Parameter Register for Boot */
+#define MPS_AP_B 	((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
+
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define MPS_BS		2	/* 4 MByte */
+#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
+/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
+#define MPS_BU		3	/* R/W */
+/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
+#define MPS_BW		0	/* 8Bit */
+/* CR register for Boot */
+#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
+/* CR register for non Boot */
+#define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds
new file mode 100755
index 0000000..11819a4
--- /dev/null
+++ b/board/mpl/pip405/u-boot.lds
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/mpl/pip405/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug
new file mode 100755
index 0000000..1608f8c
--- /dev/null
+++ b/board/mpl/pip405/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
new file mode 100755
index 0000000..304c965
--- /dev/null
+++ b/board/mpl/vcma9/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= vcma9.o flash.o cmd_vcma9.o
+OBJS	+= ../common/common_util.o ../common/memtst.o
+
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
new file mode 100755
index 0000000..44b4112
--- /dev/null
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2002
+ * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
+ *
+ * adapted for VCMA9
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include "vcma9.h"
+#include "../common/common_util.h"
+
+#if defined(CONFIG_DRIVER_CS8900)
+#include <../drivers/cs8900.h>
+
+static uchar cs8900_chksum(ushort data)
+{
+	return((data >> 8) & 0x00FF) + (data & 0x00FF);
+}
+
+#endif
+
+extern void print_vcma9_info(void);
+extern int vcma9_cantest(int);
+extern int vcma9_nandtest(void);
+extern int vcma9_nanderase(void);
+extern int vcma9_nandread(ulong);
+extern int vcma9_nandwrite(ulong);
+extern int vcma9_dactest(int);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* ------------------------------------------------------------------------- */
+
+int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (strcmp(argv[1], "info") == 0)
+	{
+		print_vcma9_info();
+	 	return 0;
+   	}
+#if defined(CONFIG_DRIVER_CS8900)
+	if (strcmp(argv[1], "cs8900") == 0) {
+		if (strcmp(argv[2], "read") == 0) {
+			uchar addr; ushort data;
+
+			addr = simple_strtoul(argv[3], NULL, 16);
+			cs8900_e2prom_read(addr, &data);
+			printf("0x%2.2X: 0x%4.4X\n", addr, data);
+		} else if (strcmp(argv[2], "write") == 0) {
+			uchar addr; ushort data;
+
+			addr = simple_strtoul(argv[3], NULL, 16);
+			data = simple_strtoul(argv[4], NULL, 16);
+			cs8900_e2prom_write(addr, data);
+		} else if (strcmp(argv[2], "setaddr") == 0) {
+			uchar addr, i, csum; ushort data;
+
+			/* check for valid ethaddr */
+			for (i = 0; i < 6; i++)
+				if (gd->bd->bi_enetaddr[i] != 0)
+					break;
+
+			if (i < 6) {
+				addr = 1;
+				data = 0x2158;
+				cs8900_e2prom_write(addr, data);
+				csum = cs8900_chksum(data);
+				addr++;
+				for (i = 0; i < 6; i+=2) {
+					data = gd->bd->bi_enetaddr[i+1] << 8 |
+					       gd->bd->bi_enetaddr[i];
+					cs8900_e2prom_write(addr, data);
+					csum += cs8900_chksum(data);
+					addr++;
+				}
+				/* calculate header link byte */
+				data = 0xA100 | (addr * 2);
+				cs8900_e2prom_write(0, data);
+				csum += cs8900_chksum(data);
+				/* write checksum word */
+				cs8900_e2prom_write(addr, (0 - csum) << 8);
+			} else {
+				puts("\nplease defined 'ethaddr'\n");
+			}
+		} else if (strcmp(argv[2], "dump") == 0) {
+			uchar addr = 0, endaddr, csum; ushort data;
+
+			puts("Dump of CS8900 config device: ");
+			cs8900_e2prom_read(addr, &data);
+			if ((data & 0xE000) == 0xA000) {
+				endaddr = (data & 0x00FF) / 2;
+				csum = cs8900_chksum(data);
+				for (addr = 1; addr <= endaddr; addr++) {
+					cs8900_e2prom_read(addr, &data);
+					printf("\n0x%2.2X: 0x%4.4X", addr, data);
+					csum += cs8900_chksum(data);
+				}
+				printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong");
+			} else {
+				puts("no valid config found");
+			}
+			puts("\n");
+		}
+
+		return 0;
+	}
+#endif
+#if 0
+	if (strcmp(argv[1], "cantest") == 0) {
+		if (argc >= 3)
+			vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+			vcma9_cantest(0);
+		return 0;
+	}
+	if (strcmp(argv[1], "nandtest") == 0) {
+		vcma9_nandtest();
+		return 0;
+	}
+	if (strcmp(argv[1], "nanderase") == 0) {
+		vcma9_nanderase();
+		return 0;
+	}
+	if (strcmp(argv[1], "nandread") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandread(offset);
+		return 0;
+	}
+	if (strcmp(argv[1], "nandwrite") == 0) {
+		ulong offset = 0;
+
+		if (argc >= 3)
+			offset = simple_strtoul(argv[2], NULL, 16);
+
+		vcma9_nandwrite(offset);
+		return 0;
+	}
+	if (strcmp(argv[1], "dactest") == 0) {
+		if (argc >= 3)
+			vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1);
+		else
+		vcma9_dactest(0);
+		return 0;
+	}
+#endif
+
+	return (do_mplcommon(cmdtp, flag, argc, argv));
+}
+
+U_BOOT_CMD(
+	vcma9, 6, 1, do_vcma9,
+	"vcma9   - VCMA9 specific commands\n",
+	"flash mem [SrcAddr]\n    - updates U-Boot with image in memory\n"
+);
diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk
new file mode 100755
index 0000000..1fa09c9
--- /dev/null
+++ b/board/mpl/vcma9/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2002, 2003
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# MPL VCMA9 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.mpl.ch/ for more information about the MPL VCMA9
+#
+
+#
+# MPL VCMA9 has 1 bank of minimal 16 MB DRAM
+# from 0x30000000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3040'0000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3080'0000
+#
+
+
+#TEXT_BASE = 0x30F80000
+TEXT_BASE = 0x33F80000
diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c
new file mode 100755
index 0000000..ccfe176
--- /dev/null
+++ b/board/mpl/vcma9/flash.c
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush (void);
+
+
+#define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
+#define MAIN_SECT_SIZE  0x10000	/* 64 KB */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x000000F0
+#define CMD_UNLOCK1		0x000000AA
+#define CMD_UNLOCK2		0x00000055
+#define CMD_ERASE_SETUP		0x00000080
+#define CMD_ERASE_CONFIRM	0x00000030
+#define CMD_PROGRAM		0x000000A0
+#define CMD_UNLOCK_BYPASS	0x00000020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+
+#define BIT_ERASE_DONE		0x00000080
+#define BIT_RDY_MASK		0x00000080
+#define BIT_PROGRAM_ERROR	0x00000020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+#if defined(CONFIG_AMD_LV400)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV400B & FLASH_TYPEMASK);
+#elif defined(CONFIG_AMD_LV800)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV800B & FLASH_TYPEMASK);
+#else
+#error "Unknown flash configured"
+#endif
+			flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j <= 3) {
+				/* 1st one is 16 KB */
+				if (j == 0) {
+					flash_info[i].start[j] =
+						flashbase + 0;
+				}
+
+				/* 2nd and 3rd are both 8 KB */
+				if ((j == 1) || (j == 2)) {
+					flash_info[i].start[j] =
+						flashbase + 0x4000 + (j -
+								      1) *
+						0x2000;
+				}
+
+				/* 4th 32 KB */
+				if (j == 3) {
+					flash_info[i].start[j] =
+						flashbase + 0x8000;
+				}
+			} else {
+				flash_info[i].start[j] =
+					flashbase + (j - 3) * MAIN_SECT_SIZE;
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		puts ("AMD: ");
+		break;
+	default:
+		puts ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_LV400B & FLASH_TYPEMASK):
+		puts ("1x Amd29LV400BB (4Mbit)\n");
+		break;
+	case (AMD_ID_LV800B & FLASH_TYPEMASK):
+		puts ("1x Amd29LV800BB (8Mbit)\n");
+		break;
+	default:
+		puts ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	puts ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			puts ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	puts ("\n");
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ushort result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip = TMO;
+					break;
+				}
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip = READY;
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+					chip = ERR;
+
+			} while (!chip);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			puts ("ok.\n");
+		} else {	/* it was protected */
+
+			puts ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		puts ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) dest;
+	ushort result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+			chip = ERR | TMO;
+			break;
+		}
+		if (!chip && ((result & 0x80) == (data & 0x80)))
+			chip = READY;
+
+		if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = *addr;
+
+			if ((result & 0x80) == (data & 0x80))
+				chip = READY;
+			else
+				chip = ERR;
+		}
+
+	} while (!chip);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	int l;
+	int i, rc;
+	ushort data;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_hword (info, wp, data);
+}
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
new file mode 100755
index 0000000..a023353
--- /dev/null
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -0,0 +1,212 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+#define BWSCON		0x48000000
+#define PLD_BASE	0x2C000000
+#define SDRAM_REG	0x2C000106
+
+/* BWSCON */
+#define DW8		 	(0x0)
+#define DW16		 	(0x1)
+#define DW32		 	(0x2)
+#define WAIT		 	(0x1<<2)
+#define UBLB		 	(0x1<<3)
+
+/* BANKSIZE */
+#define BURST_EN		(0x1<<7)
+
+#define B1_BWSCON	  	(DW16)
+#define B2_BWSCON	  	(DW32)
+#define B3_BWSCON	  	(DW32)
+#define B4_BWSCON	  	(DW16 + WAIT + UBLB)
+#define B5_BWSCON	  	(DW8 + UBLB)
+#define B6_BWSCON	  	(DW32)
+#define B7_BWSCON	  	(DW32)
+
+/* BANK0CON */
+#define B0_Tacs		 	0x0	/*  0clk */
+#define B0_Tcos		 	0x1	/*  1clk */
+/*#define B0_Tcos		0x0	  0clk */
+#define B0_Tacc		 	0x7	/*  14clk */
+/*#define B0_Tacc		0x5	  8clk */
+#define B0_Tcoh		 	0x0	/*  0clk */
+#define B0_Tah		 	0x0	/*  0clk */
+#define B0_Tacp		 	0x0     /* page mode is not used */
+#define B0_PMC		 	0x0	/* page mode disabled */
+
+/* BANK1CON */
+#define B1_Tacs		 	0x0	/*  0clk */
+#define B1_Tcos		 	0x1	/*  1clk */
+/*#define B1_Tcos		0x0	  0clk */
+#define B1_Tacc			0x7	/*  14clk */
+/*#define B1_Tacc		0x5	  8clk */
+#define B1_Tcoh		 	0x0	/*  0clk */
+#define B1_Tah		 	0x0	/*  0clk */
+#define B1_Tacp		 	0x0     /* page mode is not used */
+#define B1_PMC		 	0x0	/* page mode disabled */
+
+#define B2_Tacs		 	0x3	/*  4clk */
+#define B2_Tcos		 	0x3	/*  4clk */
+#define B2_Tacc		 	0x7     /* 14clk */
+#define B2_Tcoh		 	0x3	/*  4clk */
+#define B2_Tah		 	0x3	/*  4clk */
+#define B2_Tacp		 	0x0	/* page mode is not used */
+#define B2_PMC		 	0x0     /* page mode disabled */
+
+#define B3_Tacs		 	0x3	/*  4clk */
+#define B3_Tcos		 	0x3	/*  4clk */
+#define B3_Tacc		 	0x7     /* 14clk */
+#define B3_Tcoh		 	0x3	/*  4clk */
+#define B3_Tah		 	0x3	/*  4clk */
+#define B3_Tacp		 	0x0	/* page mode is not used */
+#define B3_PMC		 	0x0     /* page mode disabled */
+
+#define B4_Tacs		 	0x3	/*  4clk */
+#define B4_Tcos		 	0x1	/*  1clk */
+#define B4_Tacc		 	0x7	/* 14clk */
+#define B4_Tcoh		 	0x1	/*  1clk */
+#define B4_Tah		 	0x0	/*  0clk */
+#define B4_Tacp		 	0x0     /* page mode is not used */
+#define B4_PMC		 	0x0	/* page mode disabled */
+
+#define B5_Tacs		 	0x0	/*  0clk */
+#define B5_Tcos		 	0x3	/*  4clk */
+#define B5_Tacc		 	0x5	/*  8clk */
+#define B5_Tcoh		 	0x2	/*  2clk */
+#define B5_Tah		 	0x1	/*  1clk */
+#define B5_Tacp		 	0x0     /* page mode is not used */
+#define B5_PMC		 	0x0	/* page mode disabled */
+
+#define B6_MT		 	0x3	/* SDRAM */
+#define B6_Trcd	 	 	0x1	/* 3clk */
+#define B6_SCAN		 	0x2	/* 10bit */
+
+#define B7_MT		 	0x3	/* SDRAM */
+#define B7_Trcd		 	0x1	/* 3clk */
+#define B7_SCAN		 	0x2	/* 10bit */
+
+/* REFRESH parameter */
+#define REFEN		 	0x1	/* Refresh enable */
+#define TREFMD		 	0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp		 	0x0	/* 2clk */
+#define Trc		 	0x3	/* 7clk */
+#define Tchr		 	0x2	/* 3clk */
+#define REFCNT		 	1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =CSDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #CSDATA_END-CSDATA
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* PLD access is now possible */
+	/* r0 == SDRAMDATA */
+	/* r1 == SDRAM controller regs */
+	ldr	r2, =PLD_BASE
+	ldrb	r3, [r2, #SDRAM_REG-PLD_BASE]
+	mov	r4, #SDRAMDATA1_END-SDRAMDATA
+	/* calculate start and end point */
+	mla	r0, r3, r4, r0
+	add     r2, r0, r4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+CSDATA:
+    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+CSDATA_END:
+
+SDRAMDATA:
+/* 4Mx8x4 */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+SDRAMDATA1_END:
+
+/* 8Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+
+/* 2Mx8x4 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
+
+/* 4Mx8x2 (not implemented yet) */
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32 + BURST_EN
+    .word 0x30
+    .word 0x30
diff --git a/board/mpl/vcma9/u-boot.lds b/board/mpl/vcma9/u-boot.lds
new file mode 100755
index 0000000..f4fbf96
--- /dev/null
+++ b/board/mpl/vcma9/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
new file mode 100755
index 0000000..ffdba5d
--- /dev/null
+++ b/board/mpl/vcma9/vcma9.c
@@ -0,0 +1,353 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2410.h>
+#include <i2c.h>
+
+#include "vcma9.h"
+#include "../common/common_util.h"
+
+/* ------------------------------------------------------------------------- */
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV	0xC3
+#define M_PDIV	0x4
+#define M_SDIV	0x1
+#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#define M_MDIV	0xA1
+#define M_PDIV	0x3
+#define M_SDIV	0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV	0xA1
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV	0x48
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x2
+#endif
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+	  "subs %0, %1, #1\n"
+	  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* to reduce PLL lock time, adjust the LOCKTIME register */
+	clk_power->LOCKTIME = 0xFFFFFF;
+
+	/* configure MPLL */
+	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (4000);
+
+	/* configure UPLL */
+	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (8000);
+
+	/* set up the I/O ports */
+	gpio->GPACON = 0x007FFFFF;
+	gpio->GPBCON = 0x002AAAAA;
+	gpio->GPBUP = 0x000002BF;
+	gpio->GPCCON = 0xAAAAAAAA;
+	gpio->GPCUP = 0x0000FFFF;
+	gpio->GPDCON = 0xAAAAAAAA;
+	gpio->GPDUP = 0x0000FFFF;
+	gpio->GPECON = 0xAAAAAAAA;
+	gpio->GPEUP = 0x000037F7;
+	gpio->GPFCON = 0x00000000;
+	gpio->GPFUP = 0x00000000;
+	gpio->GPGCON = 0xFFEAFF5A;
+	gpio->GPGUP = 0x0000F0DC;
+	gpio->GPHCON = 0x0028AAAA;
+	gpio->GPHUP = 0x00000656;
+
+	/* setup correct IRQ modes for NIC */
+	gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
+
+	/* select USB port 2 to be host or device (fix to host for now) */
+	gpio->MISCCR |= 0x08;
+
+	/* init serial */
+	gd->baudrate = CONFIG_BAUDRATE;
+	gd->have_console = 1;
+	serial_init();
+
+	/* arch number of VCMA9-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x30000100;
+
+	icache_enable();
+	dcache_enable();
+
+	return 0;
+}
+
+/*
+ * NAND flash initialization.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong
+nand_probe(ulong physadr);
+
+
+static inline void NF_Reset(void)
+{
+    int i;
+
+    NF_SetCE(NFCE_LOW);
+    NF_Cmd(0xFF);		/* reset command */
+    for(i = 0; i < 10; i++);	/* tWB = 100ns. */
+    NF_WaitRB();		/* wait 200~500us; */
+    NF_SetCE(NFCE_HIGH);
+}
+
+
+static inline void NF_Init(void)
+{
+#if 0 /* a little bit too optimistic */
+#define TACLS   0
+#define TWRPH0  3
+#define TWRPH1  0
+#else
+#define TACLS   0
+#define TWRPH0  4
+#define TWRPH1  2
+#endif
+
+    NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
+    /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
+    /* 1  1    1     1,   1      xxx,  r xxx,   r xxx */
+    /* En 512B 4step ECCR nFCE=H tACLS   tWRPH0   tWRPH1 */
+
+    NF_Reset();
+}
+
+void
+nand_init(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	NF_Init();
+#ifdef DEBUG
+	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
+#endif
+	printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
+}
+#endif
+
+/*
+ * Get some Board/PLD Info
+ */
+
+static u8 Get_PLD_ID(void)
+{
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+
+	return(pld->ID);
+}
+
+static u8 Get_PLD_BOARD(void)
+{
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+
+	return(pld->BOARD);
+}
+
+static u8 Get_PLD_SDRAM(void)
+{
+	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+
+	return(pld->SDRAM);
+}
+
+static u8 Get_PLD_Version(void)
+{
+	return((Get_PLD_ID() >> 4) & 0x0F);
+}
+
+static u8 Get_PLD_Revision(void)
+{
+	return(Get_PLD_ID() & 0x0F);
+}
+
+#if 0	/* not used */
+static int Get_Board_Config(void)
+{
+	u8 config = Get_PLD_BOARD() & 0x03;
+
+	if (config == 3)
+	    return 1;
+	else
+	    return 0;
+}
+#endif
+
+static uchar Get_Board_PCB(void)
+{
+	return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
+}
+
+static u8 Get_SDRAM_ChipNr(void)
+{
+	switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
+		case 0: return 4;
+		case 1: return 1;
+		case 2: return 2;
+		default: return 0;
+	}
+}
+
+static ulong Get_SDRAM_ChipSize(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return 16 * (1024*1024);
+		case 1: return 32 * (1024*1024);
+		case 2: return  8 * (1024*1024);
+		case 3: return  8 * (1024*1024);
+		default: return 0;
+	}
+}
+static const char * Get_SDRAM_ChipGeom(void)
+{
+	switch (Get_PLD_SDRAM() & 0x0F) {
+		case 0: return "4Mx8x4";
+		case 1: return "8Mx8x4";
+		case 2: return "2Mx8x4";
+		case 3: return "4Mx8x2";
+		default: return "unknown";
+	}
+}
+
+static void Show_VCMA9_Info(char *board_name, char *serial)
+{
+	printf("Board: %s SN: %s  PCB Rev: %c PLD(%d,%d)\n",
+		board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
+	printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+	unsigned char s[50];
+	int i;
+	backup_t *b = (backup_t *) s;
+
+	i = getenv_r("serial#", s, 32);
+	if ((i < 0) || strncmp (s, "VCMA9", 5)) {
+		get_backup_values (b);
+		if (strncmp (b->signature, "MPL\0", 4) != 0) {
+			puts ("### No HW ID - assuming VCMA9");
+		} else {
+			b->serial_name[5] = 0;
+			Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
+		}
+	} else {
+		s[5] = 0;
+		Show_VCMA9_Info(s, &s[6]);
+	}
+	/*printf("\n");*/
+	return(0);
+}
+
+
+extern void mem_test_reloc(void);
+
+int last_stage_init(void)
+{
+	mem_test_reloc();
+	checkboard();
+	show_stdio_dev();
+	check_env();
+	return 0;
+}
+
+/***************************************************************************
+ * some helping routines
+ */
+#if !CONFIG_USB_KEYBOARD
+int overwrite_console(void)
+{
+	/* return TRUE if console should be overwritten */
+	return 0;
+}
+#endif
+
+/************************************************************************
+* Print VCMA9 Info
+************************************************************************/
+void print_vcma9_info(void)
+{
+	unsigned char s[50];
+	int i;
+
+	if ((i = getenv_r("serial#", s, 32)) < 0) {
+		puts ("### No HW ID - assuming VCMA9");
+		printf("i %d", i*24);
+	} else {
+		s[5] = 0;
+		Show_VCMA9_Info(s, &s[6]);
+	}
+}
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h
new file mode 100755
index 0000000..c0167d5
--- /dev/null
+++ b/board/mpl/vcma9/vcma9.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2002, 2003
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ /****************************************************************************
+ * Global routines used for VCMA9
+ *****************************************************************************/
+
+#include <s3c2410.h>
+
+extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
+
+void print_vcma9_info(void);
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+typedef enum {
+	NFCE_LOW,
+	NFCE_HIGH
+} NFCE_STATE;
+
+static inline void NF_Conf(u16 conf)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFCONF = conf;
+}
+
+static inline void NF_Cmd(u8 cmd)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFCMD = cmd;
+}
+
+static inline void NF_CmdW(u8 cmd)
+{
+	NF_Cmd(cmd);
+	udelay(1);
+}
+
+static inline void NF_Addr(u8 addr)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFADDR = addr;
+}
+
+static inline void NF_SetCE(NFCE_STATE s)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	switch (s) {
+		case NFCE_LOW:
+			nand->NFCONF &= ~(1<<11);
+			break;
+
+		case NFCE_HIGH:
+			nand->NFCONF |= (1<<11);
+			break;
+	}
+}
+
+static inline void NF_WaitRB(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	while (!(nand->NFSTAT & (1<<0)));
+}
+
+static inline void NF_Write(u8 data)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFDATA = data;
+}
+
+static inline u8 NF_Read(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	return(nand->NFDATA);
+}
+
+static inline void NF_Init_ECC(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	nand->NFCONF |= (1<<12);
+}
+
+static inline u32 NF_Read_ECC(void)
+{
+	S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+
+	return(nand->NFECC);
+}
+
+#endif
+
+/* VCMA9 PLD regsiters */
+typedef struct {
+	S3C24X0_REG8	ID;
+	S3C24X0_REG8	NIC;
+	S3C24X0_REG8	CAN;
+	S3C24X0_REG8	MISC;
+	S3C24X0_REG8	GPCD;
+	S3C24X0_REG8	BOARD;
+	S3C24X0_REG8	SDRAM;
+} /*__attribute__((__packed__))*/ VCMA9_PLD;
+
+#define VCMA9_PLD_BASE	0x2C000100
+static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void)
+{
+	return (VCMA9_PLD * const)VCMA9_PLD_BASE;
+}
diff --git a/board/musenki/Makefile b/board/musenki/Makefile
new file mode 100755
index 0000000..24dc026
--- /dev/null
+++ b/board/musenki/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	=
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/musenki/README b/board/musenki/README
new file mode 100755
index 0000000..135a01a
--- /dev/null
+++ b/board/musenki/README
@@ -0,0 +1,298 @@
+U-Boot for a Musenki M-3/M-1 board
+---------------------------
+
+Musenki M-1 and M-3 have two banks of flash of 4MB or 8MB each.
+
+In board's notation, bank 0 is the one at the address of 0xFF800000
+and bank 1 is the one at the address of 0xFF000000.
+
+On power-up the processor jumps to the address of 0xFFF00100, the last
+megabyte of the bank 0 of flash.
+
+Thus, U-Boot is configured to reside in flash starting at the address of
+0xFFF00000.  The environment space is located in flash separately from
+U-Boot, at the address of 0xFF800000.
+
+There is a Davicom 9102A on-board, but I don't have it working yet.
+
+U-Boot test results
+--------------------
+
+x.x Operation on all available serial consoles
+
+x.x.x CONFIG_CONS_INDEX 1
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> help
+autoscr - run script from memory
+base    - print or set address offset
+bdinfo  - print Board Info structure
+bootm   - boot application image from memory
+bootp   - boot image via network using BootP/TFTP protocol
+bootd   - boot default, i.e., run 'bootcmd'
+cmp     - memory compare
+coninfo - print console devices and informations
+cp      - memory copy
+crc32   - checksum calculation
+dcache  - enable or disable data cache
+echo    - echo args to console
+erase   - erase FLASH memory
+flinfo  - print FLASH memory information
+go      - start application at address 'addr'
+help    - print online help
+icache  - enable or disable instruction cache
+iminfo  - print header information for application image
+loadb   - load binary file over serial line (kermit mode)
+loads   - load S-Record file over serial line
+loop    - infinite loop on address range
+md      - memory display
+mm      - memory modify (auto-incrementing)
+mtest   - simple RAM test
+mw      - memory write (fill)
+nm      - memory modify (constant address)
+printenv- print environment variables
+protect - enable or disable FLASH write protection
+rarpboot- boot image via network using RARP/TFTP protocol
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+tftpboot- boot image via network using TFTP protocol
+	       and env variables ipaddr and serverip
+version - print monitor version
+?       - alias for 'help'
+
+
+x.x.x CONFIG_CONS_INDEX 2
+
+**** NOT TESTED ****
+
+x.x Flash Driver Operation
+
+
+Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=>
+=> md ff800000
+ff800000: 46989bf8 626f6f74 636d643d 626f6f74    F...bootcmd=boot
+ff800010: 6d204646 38323030 30300062 6f6f7464    m FF820000.bootd
+ff800020: 656c6179 3d350062 61756472 6174653d    elay=5.baudrate=
+ff800030: 39363030 00636c6f 636b735f 696e5f6d    9600.clocks_in_m
+ff800040: 687a3d31 00737464 696e3d73 65726961    hz=1.stdin=seria
+ff800050: 6c007374 646f7574 3d736572 69616c00    l.stdout=serial.
+ff800060: 73746465 72723d73 65726961 6c006970    stderr=serial.ip
+ff800070: 61646472 3d313932 2e313638 2e302e34    addr=192.168.0.4
+ff800080: 32007365 72766572 69703d31 39322e31    2.serverip=192.1
+ff800090: 36382e30 2e380000 00000000 00000000    68.0.8..........
+ff8000a0: 00000000 00000000 00000000 00000000    ................
+ff8000b0: 00000000 00000000 00000000 00000000    ................
+ff8000c0: 00000000 00000000 00000000 00000000    ................
+ff8000d0: 00000000 00000000 00000000 00000000    ................
+ff8000e0: 00000000 00000000 00000000 00000000    ................
+ff8000f0: 00000000 00000000 00000000 00000000    ................
+=> protect off ff800000 ff81ffff
+Un-Protected 1 sectors
+=> erase ff800000 ff81ffff
+Erase Flash from 0xff800000 to 0xff81ffff
+ done
+Erased 1 sectors
+=> md ff800000
+ff800000: ffffffff ffffffff ffffffff ffffffff    ................
+ff800010: ffffffff ffffffff ffffffff ffffffff    ................
+ff800020: ffffffff ffffffff ffffffff ffffffff    ................
+ff800030: ffffffff ffffffff ffffffff ffffffff    ................
+ff800040: ffffffff ffffffff ffffffff ffffffff    ................
+ff800050: ffffffff ffffffff ffffffff ffffffff    ................
+ff800060: ffffffff ffffffff ffffffff ffffffff    ................
+ff800070: ffffffff ffffffff ffffffff ffffffff    ................
+ff800080: ffffffff ffffffff ffffffff ffffffff    ................
+ff800090: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000a0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000b0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000c0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000d0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000e0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000f0: ffffffff ffffffff ffffffff ffffffff    ................
+
+x.x.x Information
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> flinfo
+
+Bank # 1: Intel 28F320J3A (32Mbit = 128K x 32)
+  Size: 4 MB in 32 Sectors
+  Sector Start Addresses:
+    FF800000 (RO) FF820000      FF840000      FF860000      FF880000
+    FF8A0000      FF8C0000      FF8E0000      FF900000      FF920000
+    FF940000      FF960000      FF980000      FF9A0000      FF9C0000
+    FF9E0000      FFA00000      FFA20000      FFA40000      FFA60000
+    FFA80000      FFAA0000      FFAC0000      FFAE0000      FFB00000
+    FFB20000      FFB40000      FFB60000      FFB80000      FFBA0000
+    FFBC0000      FFBE0000
+
+Bank # 2: missing or unknown FLASH type
+=>
+
+
+x.x.x Flash Programming
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=>
+=>
+=>
+=> protect off ff800000 ff81ffff
+Un-Protected 1 sectors
+=> cp 0 ff800000 20
+Copy to Flash... done
+=> md ff800000
+ff800000: 37ce33ec 33cc334c 33c031cc 33cc35cc    7.3.3.3L3.1.3.5.
+ff800010: 33ec13ce 30ccb3ec b3c833c4 31c836cc    3...0.....3.1.6.
+ff800020: 33cc3b9d 31ec33ee 13ecf3cc 338833ec    3.;.1.3.....3.3.
+ff800030: 234c33ec 32cc22cc 33883bdc 534433cc    #L3.2.".3.;.SD3.
+ff800040: 33cc30c8 31cc32ec 338c33cc 330c33dc    3.0.1.2.3.3.3.3.
+ff800050: 33cc13dc 334c534c b1c433d8 128c13cc    3...3LSL..3.....
+ff800060: 37ec36cd 33dc33cc bbc9f7e8 bbcc77cc    7.6.3.3.......w.
+ff800070: 314c0adc 139c30ed 33cc334c 33c833ec    1L....0.3.3L3.3.
+ff800080: ffffffff ffffffff ffffffff ffffffff    ................
+ff800090: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000a0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000b0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000c0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000d0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000e0: ffffffff ffffffff ffffffff ffffffff    ................
+ff8000f0: ffffffff ffffffff ffffffff ffffffff    ................
+
+
+x.x.x Storage of environment variables in flash
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> printenv
+bootcmd=bootm FF820000
+bootdelay=5
+baudrate=9600
+clocks_in_mhz=1
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 106/16380 bytes
+=> setenv myvar 1234
+=> saveenv
+Un-Protected 1 sectors
+Erasing Flash...
+ done
+Erased 1 sectors
+Saving Environment to Flash...
+Protected 1 sectors
+=> reset
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> printenv
+bootcmd=bootm FF820000
+bootdelay=5
+baudrate=9600
+clocks_in_mhz=1
+myvar=1234
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 117/16380 bytes
+
+x.x Image Download and run over serial port
+
+
+U-Boot 1.1.1 (Nov 20 2001 - 15:55:32)
+
+CPU:   MPC8245 Revision 16.20 at 250 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MUSENKI Local Bus at 100 MHz
+DRAM:  32 MB
+FLASH:  4 MB
+In:    serial
+Out:   serial
+Err:   serial
+Hit any key to stop autoboot:  0
+=> loads
+## Ready for S-Record download ...
+
+## First Load Addr = 0x00040000
+## Last  Load Addr = 0x00050177
+## Total Size      = 0x00010178 = 65912 Bytes
+## Start Addr      = 0x00040004
+=> go 40004
+## Starting application at 0x00040004 ...
+Hello World
+argc = 1
+argv[0] = "40004"
+argv[1] = "<NULL>"
+Hit any key to exit ...
+
+## Application terminated, rc = 0x0
+
+
+x.x Image download and run over ethernet interface
+
+untested (not working yet, actually)
diff --git a/board/musenki/config.mk b/board/musenki/config.mk
new file mode 100755
index 0000000..18673e1
--- /dev/null
+++ b/board/musenki/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CU824 board
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/musenki/flash.c b/board/musenki/flash.c
new file mode 100755
index 0000000..cd33d8e
--- /dev/null
+++ b/board/musenki/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, uchar *dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+/*
+ * don't ask.  its stupid, but more than one soul has had to live with this mistake
+ * "swaptab[i]" is the value of "i" with the bits reversed.
+ */
+
+#define  MUSENKI_BROKEN_FLASH 1
+
+#ifdef MUSENKI_BROKEN_FLASH
+unsigned char swaptab[256] = {
+  0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
+  0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
+  0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
+  0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
+  0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
+  0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
+  0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
+  0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
+  0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
+  0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
+  0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
+  0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
+  0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
+  0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
+  0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
+  0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
+  0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
+  0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
+  0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
+  0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
+  0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
+  0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
+  0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
+  0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
+  0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
+  0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
+  0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
+  0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
+  0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
+  0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
+  0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
+  0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
+};
+
+#define BS(b)     (swaptab[b])
+
+#else
+
+#define BS(b)     (b)
+
+#endif
+
+#define BYTEME(x) ((x) & 0xFF)
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CFG_FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_char *)CFG_FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0: "
+			"ID 0x%lx, Size = 0x%08lx = %ld MB\n",
+			flash_info[0].flash_id,
+			size_b0, size_b0<<20);
+	}
+
+	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CFG_FLASH_BASE1_PRELIM);
+	size_b1 = flash_get_size((vu_char *)CFG_FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, monitor_flash_len);
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE);
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		flash_info[1].size = size_b1;
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+		flash_info[1].size = 0;
+	}
+
+	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+	    for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += 0x00020000;		/* 128k per bank */
+	    }
+	    return;
+
+	default:
+	    printf ("Don't know sector ofsets for flash type 0x%lx\n", info->flash_id);
+	    return;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("Fujitsu ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_MT:	printf ("MT ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320J3A (32Mbit = 128K x 32)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640J3A (64Mbit = 128K x 64)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128J3A (128Mbit = 128K x 128)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size >= (1 << 20)) {
+		i = 20;
+	} else {
+		i = 10;
+	}
+	printf ("  Size: %ld %cB in %d Sectors\n",
+		info->size >> i,
+		(i == 20) ? 'M' : 'k',
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+	vu_char manuf, device;
+
+	addr[0] = BS(0x90);
+	manuf = BS(addr[0]);
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (vu_char *)addr, manuf);
+
+	switch (manuf) {
+	case BYTEME(AMD_MANUFACT):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case BYTEME(FUJ_MANUFACT):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case BYTEME(SST_MANUFACT):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case BYTEME(STM_MANUFACT):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case BYTEME(INTEL_MANUFACT):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = BS(0xFF);		/* restore read mode, (yes, BS is a NOP) */
+		return 0;			/* no or unknown flash	*/
+	}
+
+	device = BS(addr[2]);			/* device ID		*/
+
+	DEBUGF("Device ID @ 0x%08x: 0x%08x\n", (&addr[1]), device);
+
+	switch (device) {
+	case BYTEME(INTEL_ID_28F320J3A):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* =>  4 MB		*/
+
+	case BYTEME(INTEL_ID_28F640J3A):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case BYTEME(INTEL_ID_28F128J3A):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = BS(0xFF);		/* restore read mode (yes, a NOP) */
+		return 0;			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = BS(0xFF);		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+		printf ("Can erase only Intel flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_char *addr = (vu_char *)(info->start[sect]);
+			unsigned long status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = BS(0x50);	/* clear status register */
+			*addr = BS(0x20);	/* erase setup */
+			*addr = BS(0xD0);	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag) {
+				enable_interrupts();
+			}
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = BS(0xB0); /* suspend erase	  */
+					*addr = BS(0xFF); /* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = BS(0xFF);	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	1	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	uchar *wp = (uchar *)addr;
+	int rc;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	while (cnt > 0) {
+		if ((rc = write_data(info, wp, *src)) != 0) {
+			return rc;
+		}
+		wp++;
+		src++;
+		cnt--;
+	}
+
+	return cnt;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, uchar *dest, uchar data)
+{
+	vu_char *addr = (vu_char *)dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((BS(*addr) & data) != data) {
+		return 2;
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = BS(0x40);		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+
+	start = get_timer (0);
+
+	while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = BS(0xFF);	/* restore read mode */
+			return 1;
+		}
+	}
+
+	*addr = BS(0xFF);	/* restore read mode */
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c
new file mode 100755
index 0000000..88ef83a
--- /dev/null
+++ b/board/musenki/musenki.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+int checkboard (void)
+{
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	printf("Board: MUSENKI Local Bus at %s MHz\n", strmhz(buf, busfreq));
+	return 0;
+
+}
+
+#if 0 	/* NOT USED */
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("## Test not implemented yet ##\n");
+
+	return (0);
+}
+#endif
+
+long int initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_sandpoint_config_table[] = {
+#if 0
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  0x0, 0x0, 0x0, /* unknown eth0 divice */
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	  0x0, 0x0, 0x0, /* unknown eth1 device */
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_IO |
+				       PCI_COMMAND_MEMORY |
+				       PCI_COMMAND_MASTER }},
+#endif
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_sandpoint_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
diff --git a/board/musenki/u-boot.lds b/board/musenki/u-boot.lds
new file mode 100755
index 0000000..7c05109
--- /dev/null
+++ b/board/musenki/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mvblue/Makefile b/board/mvblue/Makefile
new file mode 100755
index 0000000..24dc026
--- /dev/null
+++ b/board/mvblue/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	=
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mvblue/config.mk b/board/mvblue/config.mk
new file mode 100755
index 0000000..6e0ce4e
--- /dev/null
+++ b/board/mvblue/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2001-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c
new file mode 100755
index 0000000..8df573a
--- /dev/null
+++ b/board/mvblue/flash.c
@@ -0,0 +1,583 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2001-2003
+ *
+ * Changes for MATRIX Vision mvBLUE devices
+ * MATRIX Vision GmbH / hg,as info@matrix-vision.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+
+#if 0
+	#define mvdebug(p) printf ##p
+#else
+	#define mvdebug(p)
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+
+#define FLASH_BUS_WIDTH		8
+
+#if (FLASH_BUS_WIDTH==32)
+	#define FLASH_DATA_MASK 0xffffffff
+	#define FLASH_SHIFT 1
+	#define FDT	vu_long
+#elif (FLASH_BUS_WIDTH==16)
+	#define FLASH_DATA_MASK 0xff
+	#define FLASH_SHIFT 0
+	#define FDT	vu_short
+#elif (FLASH_BUS_WIDTH==8)
+	#define FLASH_DATA_MASK 0xff
+	#define FLASH_SHIFT 0
+	#define FDT	vu_char
+#else
+	#error FLASH_BUS_WIDTH undefined
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *address, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)0xffc00000, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH : Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	flash_get_offsets (0xffc00000, &flash_info[0]);
+	flash_info[0].size = size_b0;
+
+	/* monitor protection OFF by default */
+	flash_protect ( FLAG_PROTECT_CLEAR, 0xffc00000, 0x2000, flash_info );
+
+	return size_b0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE)
+	{	/* bottom boot sector types - these are the useful ones! */
+		/* set sector offsets for bottom boot block type */
+		if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B)
+		{	/* AMDLV320B has 8 x 8k bottom boot sectors */
+			for (i = 0; i < 8; i++)												/* +8k		*/
+				info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
+			for (; i < info->sector_count; i++)									/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT);
+		}
+		else
+		{	/* other types have 4 bottom boot sectors (16,8,8,32) */
+			i = 0;
+			info->start[i++] = base +  0x00000000;								/* -		*/
+			info->start[i++] = base + (0x00004000 << FLASH_SHIFT);				/* +16k		*/
+			info->start[i++] = base + (0x00006000 << FLASH_SHIFT);				/* +8k		*/
+			info->start[i++] = base + (0x00008000 << FLASH_SHIFT);				/* +8k		*/
+			info->start[i++] = base + (0x00010000 << FLASH_SHIFT);				/* +32k		*/
+			for (; i < info->sector_count; i++)									/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT);
+		}
+	}
+	else
+	{	/* top boot sector types - not so useful */
+		/* set sector offsets for top boot block type */
+		if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T)
+		{	/* AMDLV320T has 8 x 8k top boot sectors */
+			for (i = 0; i < info->sector_count - 8; i++)						/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
+			for (; i < info->sector_count; i++)									/* +8k		*/
+				info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
+		}
+		else
+		{	/* other types have 4 top boot sectors (32,8,8,16) */
+			for (i = 0; i < info->sector_count - 4; i++)						/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
+
+			info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT);	/* -32k		*/
+			info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT);	/* -8k		*/
+			info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT);	/* -8k		*/
+			info->start[i]   = base + info->size - (0x00004000 << FLASH_SHIFT);	/* -16k		*/
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");	break;
+	case FLASH_MAN_STM:	printf ("ST ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_STMW320DB:	printf ("M29W320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_STMW320DT:	printf ("M29W320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+#define	AMD_ID_LV160T_MVS	(AMD_ID_LV160T & FLASH_DATA_MASK)
+#define AMD_ID_LV160B_MVS	(AMD_ID_LV160B & FLASH_DATA_MASK)
+#define AMD_ID_LV320T_MVS	(AMD_ID_LV320T & FLASH_DATA_MASK)
+#define AMD_ID_LV320B_MVS	(AMD_ID_LV320B & FLASH_DATA_MASK)
+#define STM_ID_W320DT_MVS	(STM_ID_29W320DT & FLASH_DATA_MASK)
+#define STM_ID_W320DB_MVS	(STM_ID_29W320DB & FLASH_DATA_MASK)
+#define AMD_MANUFACT_MVS	(AMD_MANUFACT  & FLASH_DATA_MASK)
+#define FUJ_MANUFACT_MVS	(FUJ_MANUFACT  & FLASH_DATA_MASK)
+#define STM_MANUFACT_MVS	(STM_MANUFACT  & FLASH_DATA_MASK)
+
+#if (FLASH_BUS_WIDTH >= 16)
+	#define AUTOSELECT_ADDR1	0x0555
+	#define AUTOSELECT_ADDR2	0x02AA
+	#define AUTOSELECT_ADDR3	AUTOSELECT_ADDR1
+#else
+	#define AUTOSELECT_ADDR1	0x0AAA
+	#define AUTOSELECT_ADDR2	0x0555
+	#define AUTOSELECT_ADDR3	AUTOSELECT_ADDR1
+#endif
+
+#define AUTOSELECT_DATA1	(0x00AA00AA & FLASH_DATA_MASK)
+#define AUTOSELECT_DATA2	(0x00550055 & FLASH_DATA_MASK)
+#define AUTOSELECT_DATA3	(0x00900090 & FLASH_DATA_MASK)
+
+#define RESET_BANK_DATA		(0x00F000F0 & FLASH_DATA_MASK)
+
+
+static ulong flash_get_size (vu_long *address, flash_info_t *info)
+{
+	short i;
+	FDT value;
+	FDT *addr = (FDT *)address;
+
+	ulong base = (ulong)address;
+	addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1;
+	addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2;
+	addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3;
+	__asm__ __volatile__("sync");
+
+	udelay(180);
+
+	value = addr[0];			/* manufacturer ID	*/
+	switch (value) {
+	case AMD_MANUFACT_MVS:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT_MVS:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case STM_MANUFACT_MVS:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+#if (FLASH_BUS_WIDTH >= 16)
+	value = addr[1];			/* device ID		*/
+#else
+	value = addr[2];			/* device ID		*/
+#endif
+
+	switch (value) {
+	case AMD_ID_LV160T_MVS:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 37;
+		info->size = (0x00200000 << FLASH_SHIFT);
+		break;				/* => 2 or 4 MB		*/
+
+	case AMD_ID_LV160B_MVS:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 37;
+		info->size = (0x00200000 << FLASH_SHIFT);
+		break;				/* => 2 or 4 MB		*/
+
+	case AMD_ID_LV320T_MVS:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8 MB		*/
+
+	case AMD_ID_LV320B_MVS:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8MB		*/
+
+	case STM_ID_W320DT_MVS:
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8 MB		*/
+
+	case STM_ID_W320DB_MVS:
+		info->flash_id += FLASH_STMW320DB;
+		info->sector_count = 67;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	flash_get_offsets (base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (FDT *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (FDT *)info->start[0];
+		*addr = RESET_BANK_DATA;	/* reset bank */
+	}
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+#if (FLASH_BUS_WIDTH >= 16)
+	#define ERASE_ADDR1 0x0555
+	#define ERASE_ADDR2 0x02AA
+#else
+	#define ERASE_ADDR1 0x0AAA
+	#define ERASE_ADDR2 0x0555
+#endif
+
+#define ERASE_ADDR3 ERASE_ADDR1
+#define ERASE_ADDR4 ERASE_ADDR1
+#define ERASE_ADDR5 ERASE_ADDR2
+
+#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
+#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK)
+#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK)
+#define ERASE_DATA4 ERASE_DATA1
+#define ERASE_DATA5 ERASE_DATA2
+
+#define ERASE_SECTOR_DATA 	(0x00300030 & FLASH_DATA_MASK)
+#define ERASE_CHIP_DATA 	(0x00100010 & FLASH_DATA_MASK)
+#define ERASE_CONFIRM_DATA 	(0x00800080 & FLASH_DATA_MASK)
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FDT *addr = (FDT *)(info->start[0]);
+
+	int prot, sect, l_sect, flag;
+	ulong start, now, last;
+
+	__asm__ __volatile__ ("sync");
+	addr[0] = 0xf0;
+	udelay(1000);
+
+	printf("\nflash_erase: first = %d @ 0x%08lx\n", s_first, info->start[s_first] );
+	printf("             last  = %d @ 0x%08lx\n", s_last , info->start[s_last ] );
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) || (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[ERASE_ADDR1] = ERASE_DATA1;
+	addr[ERASE_ADDR2] = ERASE_DATA2;
+	addr[ERASE_ADDR3] = ERASE_DATA3;
+	addr[ERASE_ADDR4] = ERASE_DATA4;
+	addr[ERASE_ADDR5] = ERASE_DATA5;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {
+			addr = (FDT *)(info->start[sect]);
+			addr[0] = ERASE_SECTOR_DATA;
+			l_sect = sect;
+		}
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (FDT *)(info->start[l_sect]);
+
+	while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+#define BUFF_INC 4
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt));
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		mvdebug ((" handle unaligned start bytes (cnt = 0x%08lx)\n", cnt));
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<BUFF_INC && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<BUFF_INC; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += BUFF_INC;
+	}
+
+	/*
+	 * handle (half)word aligned part
+	 */
+	mvdebug ((" handle word aligned part (cnt = 0x%08lx)\n", cnt));
+	while (cnt >= BUFF_INC) {
+		data = 0;
+		for (i=0; i<BUFF_INC; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += BUFF_INC;
+		cnt -= BUFF_INC;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	mvdebug ((" handle unaligned tail bytes (cnt = 0x%08lx)\n", cnt));
+	data = 0;
+	for (i=0, cp=wp; i<BUFF_INC && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<BUFF_INC; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+#if (FLASH_BUS_WIDTH >= 16)
+	#define WRITE_ADDR1 0x0555
+	#define WRITE_ADDR2 0x02AA
+#else
+	#define WRITE_ADDR1 0x0AAA
+	#define WRITE_ADDR2 0x0555
+	#define WRITE_ADDR3 WRITE_ADDR1
+#endif
+
+#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
+#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK)
+#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK)
+
+#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_char (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		printf(" *** ERROR: Flash not erased !\n");
+		return (2);
+	}
+	flag = disable_interrupts();
+
+	addr[WRITE_ADDR1] = WRITE_DATA1;
+	addr[WRITE_ADDR2] = WRITE_DATA2;
+	addr[WRITE_ADDR3] = WRITE_DATA3;
+	*((vu_char *)dest) = data;
+
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	addr = (vu_char *)dest;
+	while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			printf(" *** ERROR: Flash write timeout !");
+			return (1);
+		}
+	}
+ 	mvdebug (("-write_byte\n"));
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	int i,
+		result = 0;
+
+	mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest));
+	for ( i=0; (i < 4) && (result == 0); i++, dest+=1 )
+		result = write_char (info, dest, (data >> (8*(3-i))) & 0xff );
+ 	mvdebug (("-write_word\n"));
+	return result;
+}
+/*---------------------------------------------------------------- */
diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c
new file mode 100755
index 0000000..20a551d
--- /dev/null
+++ b/board/mvblue/mvblue.c
@@ -0,0 +1,247 @@
+/*
+ * GNU General Public License for more details.
+ *
+ * MATRIX Vision GmbH / June 2002-Nov 2003
+ * Andre Schwarz
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/io.h>
+#include <ns16550.h>
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+#endif
+
+u32 get_BoardType (void);
+
+#define PCI_CONFIG(b,d,f,r)    cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
+						      | ((d&0x1f)<<11) \
+						      | ((f&0x7)<<7)   \
+						      | (r&0xfc) )
+
+int mv_pci_read (int bus, int dev, int func, int reg)
+{
+	*(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
+	asm ("sync");
+	return cpu_to_le32 (*(u32 *) (0xfee00cfc));
+}
+
+u32 get_BoardType ()
+{
+	return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
+}
+
+void init_2nd_DUART (void)
+{
+	NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
+	int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
+
+	*(u8 *) (0xfc004511) = 0x1;
+	NS16550_init (console, clock_divisor);
+}
+void hw_watchdog_reset (void)
+{
+	if (get_BoardType () == 0) {
+		*(u32 *) (0xff000005) = 0;
+		asm ("sync");
+	}
+}
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	ulong busfreq = get_bus_freq (0);
+	char buf[32];
+	u32 BoardType = get_BoardType ();
+	char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
+	char *p;
+	bd_t *bd = gd->bd;
+
+	hw_watchdog_reset ();
+
+	printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
+	printf ("       Found %s running at %s MHz memory clock.\n",
+		BoardName[BoardType], strmhz (buf, busfreq));
+
+	init_2nd_DUART ();
+
+	if ((p = getenv ("console_nr")) != NULL) {
+		unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
+
+		bd->bi_baudrate &= ~3;
+		bd->bi_baudrate |= con_nr & 3;
+	}
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1,  mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+u8 *dhcp_vendorex_prep (u8 * e)
+{
+	char *ptr;
+
+	/* DHCP vendor-class-identifier = 60 */
+	if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
+		*e++ = 60;
+		*e++ = strlen (ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	/* my DHCP_CLIENT_IDENTIFIER = 61 */
+	if ((ptr = getenv ("dhcp_client_id"))) {
+		*e++ = 61;
+		*e++ = strlen (ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	return e;
+}
+
+u8 *dhcp_vendorex_proc (u8 * popt)
+{
+	return NULL;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Initialize PCI Devices
+ */
+#ifdef CONFIG_PCI
+void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
+{
+	u32 cnt;
+
+	printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
+		PCI_FUNC (dev));
+	for (cnt = 0; cnt < 6; cnt++)
+		pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
+					     0x0);
+	printf ("done\n");
+}
+
+void duart_setup (u32 base, u16 divisor)
+{
+	printf ("duart setup ...");
+	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
+	printf ("done\n");
+}
+
+void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
+					 pci_dev_t bridge, unsigned char irq)
+{
+	pci_dev_t d;
+	unsigned char bus;
+	unsigned short vendor, class;
+
+	pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
+	for (d = PCI_BDF (bus, 0, 0);
+	     d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
+			  PCI_MAX_PCI_FUNCTIONS - 1);
+	     d += PCI_BDF (0, 0, 1)) {
+		pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
+		if (vendor != 0xffff && vendor != 0x0000) {
+			pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
+						   &class);
+			if (class == PCI_CLASS_BRIDGE_PCI)
+				pci_mvblue_fixup_irq_behind_bridge (hose, d,
+								    irq);
+			else
+				pci_hose_write_config_byte (hose, d,
+							    PCI_INTERRUPT_LINE,
+							    irq);
+		}
+	}
+}
+
+#define MV_MAX_PCI_BUSSES	3
+#define SLOT0_IRQ	3
+#define SLOT1_IRQ	4
+void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
+{
+	unsigned char line = 0xff;
+	unsigned short class;
+
+	if (PCI_BUS (dev) == 0) {
+		switch (PCI_DEV (dev)) {
+		case 0xd:
+			if (get_BoardType () == 0) {
+				line = 1;
+			} else
+				/* mvBL */
+				line = 2;
+			break;
+		case 0xe:
+			/* mvBB: IDE */
+			line = 2;
+			pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
+			break;
+		case 0xf:
+			/* mvBB: Slot0 (Grabber) */
+			pci_hose_read_config_word (hose, dev,
+						   PCI_CLASS_DEVICE, &class);
+			if (class == PCI_CLASS_BRIDGE_PCI) {
+				pci_mvblue_fixup_irq_behind_bridge (hose, dev,
+								    SLOT0_IRQ);
+				line = 0xff;
+			} else
+				line = SLOT0_IRQ;
+			break;
+		case 0x10:
+			/* mvBB: Slot1 */
+			pci_hose_read_config_word (hose, dev,
+						   PCI_CLASS_DEVICE, &class);
+			if (class == PCI_CLASS_BRIDGE_PCI) {
+				pci_mvblue_fixup_irq_behind_bridge (hose, dev,
+								    SLOT1_IRQ);
+				line = 0xff;
+			} else
+				line = SLOT1_IRQ;
+			break;
+		default:
+			printf ("***pci_scan: illegal dev = 0x%08x\n",
+				PCI_DEV (dev));
+			line = 0xff;
+			break;
+		}
+		pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
+					    line);
+	}
+}
+
+struct pci_controller hose = {
+	fixup_irq:pci_mvblue_fixup_irq
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init (&hose);
+}
+#endif
diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds
new file mode 100755
index 0000000..7c05109
--- /dev/null
+++ b/board/mvblue/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mvs1/Makefile b/board/mvs1/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/mvs1/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/mvs1/README b/board/mvs1/README
new file mode 100755
index 0000000..69520bd
--- /dev/null
+++ b/board/mvs1/README
@@ -0,0 +1,14 @@
+This port is for the MATRIX Vision mvSensor.
+It is an mpc823-based universal image processing board
+with CMOS or CCD sensor, 4MB FLASH and 16-64MB RAM.
+
+See http://www.matrix-vision.de for more details or mail...
+
+mvsensor@matrix-vision.de
+
+Howard Gray
+MATRIX Vision GmbH
+Talstr. 16
+D-71570
+Oppenweiler
+Germany
diff --git a/board/mvs1/config.mk b/board/mvs1/config.mk
new file mode 100755
index 0000000..9d6080b
--- /dev/null
+++ b/board/mvs1/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8xxL boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/mvs1/flash.c b/board/mvs1/flash.c
new file mode 100755
index 0000000..0845943
--- /dev/null
+++ b/board/mvs1/flash.c
@@ -0,0 +1,719 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Changes for MATRIX Vision MVsensor (C) Copyright 2001
+ * MATRIX Vision GmbH / hg, info@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#undef MVDEBUG
+#ifdef MVDEBUG
+#define mvdebug debug
+#else
+#define mvdebug(p) do {} while (0)
+#endif
+
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+
+#ifdef CONFIG_MVS_16BIT_FLASH
+	#define FLASH_DATA_MASK 0xffff
+	#define FLASH_SHIFT 0
+#else
+	#define FLASH_DATA_MASK 0xffffffff
+	#define FLASH_SHIFT 1
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *address, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+#if defined (FLASH_BASE1_PRELIM)
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+#else
+	size_b1 = 0;
+#endif
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+#ifdef CONFIG_MVS_16BIT_FLASH
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+#else
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_GPCM | BR_V;
+#endif
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_FLASH_BASE,
+		      CFG_FLASH_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+
+	if (size_b1) {
+		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+#ifdef CONFIG_MVS_16BIT_FLASH
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_PS_16 | BR_MS_GPCM | BR_V;
+#else
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_PS_32 | BR_MS_GPCM | BR_V;
+#endif
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_FLASH_BASE,
+			      CFG_FLASH_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE)
+	{	/* bottom boot sector types - these are the useful ones! */
+		/* set sector offsets for bottom boot block type */
+		if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B)
+		{	/* AMDLV320B has 8 x 8k bottom boot sectors */
+			for (i = 0; i < 8; i++)												/* +8k		*/
+				info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
+			for (; i < info->sector_count; i++)									/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00070000 << FLASH_SHIFT);
+		}
+		else
+		{	/* other types have 4 bottom boot sectors (16,8,8,32) */
+			i = 0;
+			info->start[i++] = base +  0x00000000;								/* -		*/
+			info->start[i++] = base + (0x00004000 << FLASH_SHIFT);				/* +16k		*/
+			info->start[i++] = base + (0x00006000 << FLASH_SHIFT);				/* +8k		*/
+			info->start[i++] = base + (0x00008000 << FLASH_SHIFT);				/* +8k		*/
+			info->start[i++] = base + (0x00010000 << FLASH_SHIFT);				/* +32k		*/
+			for (; i < info->sector_count; i++)									/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT)) - (0x00030000 << FLASH_SHIFT);
+		}
+	}
+	else
+	{	/* top boot sector types - not so useful */
+		/* set sector offsets for top boot block type */
+		if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T)
+		{	/* AMDLV320T has 8 x 8k top boot sectors */
+			for (i = 0; i < info->sector_count - 8; i++)						/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
+			for (; i < info->sector_count; i++)									/* +8k		*/
+				info->start[i] = base + (i * (0x00002000 << FLASH_SHIFT));
+		}
+		else
+		{	/* other types have 4 top boot sectors (32,8,8,16) */
+			for (i = 0; i < info->sector_count - 4; i++)						/* +64k		*/
+				info->start[i] = base + (i * (0x00010000 << FLASH_SHIFT));
+
+			info->start[i++] = base + info->size - (0x00010000 << FLASH_SHIFT);	/* -32k		*/
+			info->start[i++] = base + info->size - (0x00008000 << FLASH_SHIFT);	/* -8k		*/
+			info->start[i++] = base + info->size - (0x00006000 << FLASH_SHIFT);	/* -8k		*/
+			info->start[i]   = base + info->size - (0x00004000 << FLASH_SHIFT);	/* -16k		*/
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");	break;
+	case FLASH_MAN_STM:	printf ("ST ");			break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_STMW320DB:	printf ("M29W320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_STMW320DT:	printf ("M29W320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+#define	AMD_ID_LV160T_MVS	(AMD_ID_LV160T & FLASH_DATA_MASK)
+#define AMD_ID_LV160B_MVS	(AMD_ID_LV160B & FLASH_DATA_MASK)
+#define AMD_ID_LV320T_MVS	(AMD_ID_LV320T & FLASH_DATA_MASK)
+#define AMD_ID_LV320B_MVS	(AMD_ID_LV320B & FLASH_DATA_MASK)
+#define STM_ID_W320DT_MVS	(STM_ID_29W320DT & FLASH_DATA_MASK)
+#define STM_ID_W320DB_MVS	(STM_ID_29W320DB & FLASH_DATA_MASK)
+#define AMD_MANUFACT_MVS	(AMD_MANUFACT  & FLASH_DATA_MASK)
+#define FUJ_MANUFACT_MVS	(FUJ_MANUFACT  & FLASH_DATA_MASK)
+#define STM_MANUFACT_MVS	(STM_MANUFACT  & FLASH_DATA_MASK)
+
+#define AUTOSELECT_ADDR1	0x0555
+#define AUTOSELECT_ADDR2	0x02AA
+#define AUTOSELECT_ADDR3	AUTOSELECT_ADDR1
+
+#define AUTOSELECT_DATA1	(0x00AA00AA & FLASH_DATA_MASK)
+#define AUTOSELECT_DATA2	(0x00550055 & FLASH_DATA_MASK)
+#define AUTOSELECT_DATA3	(0x00900090 & FLASH_DATA_MASK)
+
+#define RESET_BANK_DATA		(0x00F000F0 & FLASH_DATA_MASK)
+
+static ulong flash_get_size (vu_long *address, flash_info_t *info)
+{
+	short i;
+#ifdef CONFIG_MVS_16BIT_FLASH
+	ushort value;
+	vu_short *addr = (vu_short *)address;
+#else
+	ulong value;
+	vu_long *addr = (vu_long *)address;
+#endif
+	ulong base = (ulong)address;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[AUTOSELECT_ADDR1] = AUTOSELECT_DATA1;
+	addr[AUTOSELECT_ADDR2] = AUTOSELECT_DATA2;
+	addr[AUTOSELECT_ADDR3] = AUTOSELECT_DATA3;
+
+	value = addr[0];			/* manufacturer ID	*/
+	switch (value) {
+	case AMD_MANUFACT_MVS:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT_MVS:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case STM_MANUFACT_MVS:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+	switch (value) {
+	case AMD_ID_LV160T_MVS:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 37;
+		info->size = (0x00200000 << FLASH_SHIFT);
+		break;				/* => 2 or 4 MB		*/
+
+	case AMD_ID_LV160B_MVS:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 37;
+		info->size = (0x00200000 << FLASH_SHIFT);
+		break;				/* => 2 or 4 MB		*/
+
+	case AMD_ID_LV320T_MVS:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8 MB		*/
+
+	case AMD_ID_LV320B_MVS:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8MB		*/
+
+	case STM_ID_W320DT_MVS:
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8 MB		*/
+
+	case STM_ID_W320DB_MVS:
+		info->flash_id += FLASH_STMW320DB;
+		info->sector_count = 67;
+		info->size = (0x00400000 << FLASH_SHIFT);
+		break;				/* => 4 or 8MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	flash_get_offsets (base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+#ifdef CONFIG_MVS_16BIT_FLASH
+		addr = (vu_short *)(info->start[i]);
+#else
+		addr = (vu_long *)(info->start[i]);
+#endif
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+#ifdef CONFIG_MVS_16BIT_FLASH
+		addr = (vu_short *)info->start[0];
+#else
+		addr = (vu_long *)info->start[0];
+#endif
+		*addr = RESET_BANK_DATA;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+#define ERASE_ADDR1 0x0555
+#define ERASE_ADDR2 0x02AA
+#define ERASE_ADDR3 ERASE_ADDR1
+#define ERASE_ADDR4 ERASE_ADDR1
+#define ERASE_ADDR5 ERASE_ADDR2
+
+#define ERASE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
+#define ERASE_DATA2 (0x00550055 & FLASH_DATA_MASK)
+#define ERASE_DATA3 (0x00800080 & FLASH_DATA_MASK)
+#define ERASE_DATA4 ERASE_DATA1
+#define ERASE_DATA5 ERASE_DATA2
+
+#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK)
+#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK)
+#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK)
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+#ifdef CONFIG_MVS_16BIT_FLASH
+	vu_short *addr = (vu_short *)(info->start[0]);
+#else
+	vu_long *addr = (vu_long *)(info->start[0]);
+#endif
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[ERASE_ADDR1] = ERASE_DATA1;
+	addr[ERASE_ADDR2] = ERASE_DATA2;
+	addr[ERASE_ADDR3] = ERASE_DATA3;
+	addr[ERASE_ADDR4] = ERASE_DATA4;
+	addr[ERASE_ADDR5] = ERASE_DATA5;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+#ifdef CONFIG_MVS_16BIT_FLASH
+			addr = (vu_short *)(info->start[sect]);
+#else
+			addr = (vu_long *)(info->start[sect]);
+#endif
+			addr[0] = ERASE_SECTOR_DATA;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+#ifdef CONFIG_MVS_16BIT_FLASH
+	addr = (vu_short *)(info->start[l_sect]);
+#else
+	addr = (vu_long *)(info->start[l_sect]);
+#endif
+	while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+#ifdef CONFIG_MVS_16BIT_FLASH
+	addr = (vu_short *)info->start[0];
+#else
+	addr = (vu_long *)info->start[0];
+#endif
+	addr[0] = RESET_BANK_DATA;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+#define BUFF_INC 4
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	mvdebug (("+write_buff %p ==> 0x%08lx, count = 0x%08lx\n", src, addr, cnt));
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		mvdebug ((" handle unaligned start bytes (cnt = 0x%08%lx)\n", cnt));
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<BUFF_INC && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<BUFF_INC; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += BUFF_INC;
+	}
+
+	/*
+	 * handle (half)word aligned part
+	 */
+	mvdebug ((" handle word aligned part (cnt = 0x%08%lx)\n", cnt));
+	while (cnt >= BUFF_INC) {
+		data = 0;
+		for (i=0; i<BUFF_INC; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += BUFF_INC;
+		cnt -= BUFF_INC;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	mvdebug ((" handle unaligned tail bytes (cnt = 0x%08%lx)\n", cnt));
+	data = 0;
+	for (i=0, cp=wp; i<BUFF_INC && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<BUFF_INC; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+#define WRITE_ADDR1 0x0555
+#define WRITE_ADDR2 0x02AA
+#define WRITE_ADDR3 WRITE_ADDR1
+
+#define WRITE_DATA1 (0x00AA00AA & FLASH_DATA_MASK)
+#define WRITE_DATA2 (0x00550055 & FLASH_DATA_MASK)
+#define WRITE_DATA3 (0x00A000A0 & FLASH_DATA_MASK)
+
+#define WRITE_CONFIRM_DATA ERASE_CONFIRM_DATA
+
+#ifndef CONFIG_MVS_16BIT_FLASH
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	mvdebug (("+write_word (to 0x%08lx)\n", dest));
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[WRITE_ADDR1] = WRITE_DATA1;
+	addr[WRITE_ADDR2] = WRITE_DATA2;
+	addr[WRITE_ADDR3] = WRITE_DATA3;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	addr = (vu_long *)dest;
+	while ((*addr & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+ 	mvdebug (("-write_word\n"));
+	return (0);
+}
+#else /* CONFIG_MVS_16BIT_FLASH */
+/*-----------------------------------------------------------------------
+ * Write a halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_halfword (flash_info_t *info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	mvdebug (("+write_halfword (to 0x%08lx)\n", dest));
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[WRITE_ADDR1] = WRITE_DATA1;
+	addr[WRITE_ADDR2] = WRITE_DATA2;
+	addr[WRITE_ADDR3] = WRITE_DATA3;
+
+	*((vu_short *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	addr = (vu_short *)dest;
+	while ((*addr & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+ 	mvdebug (("-write_halfword\n"));
+	return (0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	int result = 0;
+
+	if (write_halfword (info, dest, (data & ~FLASH_DATA_MASK) >> 16) == 0)
+	{
+		dest += 2;
+		data = data & FLASH_DATA_MASK;
+		result = write_halfword (info, dest, data);
+	}
+	return result;
+}
+#endif
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/mvs1/mvs1.c b/board/mvs1/mvs1.c
new file mode 100755
index 0000000..f8a8cb7
--- /dev/null
+++ b/board/mvs1/mvs1.c
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Changes for MATRIX Vision MVsensor (C) Copyright 2001
+ * MATRIX Vision GmbH / hg, info@matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
+	0x1FF5FC47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F0DFC04 /*0x1F2DFC04??*/, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: MATRIX Vision MVsensor\n");
+	return 0;
+}
+
+
+#ifdef DO_RAM_TEST
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Test SDRAM by writing its address to itself and reading several times
+*/
+#define READ_RUNS 4
+static void test_dram (unsigned long *start, unsigned long *end)
+{
+	unsigned long *addr;
+	unsigned long value;
+	int read_runs, errors, addr_errors;
+
+	printf ("\nChecking SDRAM from %p to %p\n", start, end);
+	udelay (1000000);
+	for (addr = start; addr < end; addr++)
+		*addr = (unsigned long) addr;
+
+	for (addr = start, addr_errors = 0; addr < end; addr++) {
+		for (read_runs = READ_RUNS, errors = 0; read_runs > 0; read_runs--) {
+			if ((value = *addr) != (unsigned long) addr)
+				errors++;
+		}
+		if (errors > 0) {
+			addr_errors++;
+			printf ("SDRAM errors (%d) at %p, last read  = %ld\n",
+					errors, addr, value);
+			udelay (10000);
+		}
+	}
+	printf ("SDRAM check finished, total errors = %d\n", addr_errors);
+}
+#endif							/*  DO_RAM_TEST */
+
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0, size_b1, size8, size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or2 = CFG_OR2_PRELIM;
+	memctl->memc_br2 = CFG_BR2_PRELIM;
+
+#if defined (CFG_OR3_PRELIM) && defined (CFG_BR3_PRELIM)
+	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
+		memctl->memc_or3 = CFG_OR3_PRELIM;
+		memctl->memc_br3 = CFG_BR3_PRELIM;
+	}
+#endif
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
+		memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
+		udelay (1);
+		memctl->memc_mcr = 0x80006230;	/* SDRAM bank 1 - execute twice */
+		udelay (1);
+	}
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+	} else {					/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+	}
+
+	if (board_type == 0) {		/* "L" type boards have only one bank SDRAM */
+		/*
+		 * Check Bank 1 Memory Size
+		 * use current column settings
+		 * [9 column SDRAM may also be used in 8 column mode,
+		 *  but then only half the real size will be used.]
+		 */
+#if defined (SDRAM_BASE3_PRELIM)
+		size_b1 =
+				dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
+						   SDRAM_MAX_SIZE);
+#else
+		size_b1 = 0;
+#endif
+	} else {
+		size_b1 = 0;
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
+
+		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_br3 =
+				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b0 > 0) {
+			/*
+			 * Position Bank 0 immediately above Bank 1
+			 */
+			memctl->memc_or2 =
+					((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+			memctl->memc_br2 =
+					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					+ size_b1;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 0
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br2 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+
+	} else {					/* SDRAM Bank 0 is bigger - map first   */
+
+		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_br2 =
+				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b1 > 0) {
+			/*
+			 * Position Bank 1 immediately above Bank 0
+			 */
+			memctl->memc_or3 =
+					((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+			memctl->memc_br3 =
+					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					+ size_b0;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 1
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br3 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+	}
+
+	udelay (10000);
+
+#ifdef DO_RAM_TEST
+	if (size_b0 > 0)
+		test_dram ((unsigned long *) CFG_SDRAM_BASE,
+				   (unsigned long *) (CFG_SDRAM_BASE + size_b0));
+#endif
+
+	return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+u8 *dhcp_vendorex_prep (u8 * e)
+{
+	char *ptr;
+
+/* DHCP vendor-class-identifier = 60 */
+	if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
+		*e++ = 60;
+		*e++ = strlen (ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+/* my DHCP_CLIENT_IDENTIFIER = 61 */
+	if ((ptr = getenv ("dhcp_client_id"))) {
+		*e++ = 61;
+		*e++ = strlen (ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+
+	return e;
+}
+
+
+/* ------------------------------------------------------------------------- */
+u8 *dhcp_vendorex_proc (u8 * popt)
+{
+	return NULL;
+}
diff --git a/board/mvs1/u-boot.lds b/board/mvs1/u-boot.lds
new file mode 100755
index 0000000..a04de3d
--- /dev/null
+++ b/board/mvs1/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_generic/ctype.o		(.text)
+    lib_generic/string.o	(.text)
+    lib_ppc/extable.o		(.text)
+    lib_ppc/kgdb.o		(.text)
+
+  . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mvs1/u-boot.lds.debug b/board/mvs1/u-boot.lds.debug
new file mode 100755
index 0000000..ddd4678
--- /dev/null
+++ b/board/mvs1/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile
new file mode 100755
index 0000000..3e805fe
--- /dev/null
+++ b/board/mx1ads/Makefile
@@ -0,0 +1,48 @@
+#
+# board/mx1ads/Makefile
+#
+# (c) Copyright 2004
+# Techware Information Technology, Inc.
+# http://www.techware.com.tw/
+#
+# Ming-Len Wu <minglen_wu@techware.com.tw>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= mx1ads.o syncflash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mx1ads/config.mk b/board/mx1ads/config.mk
new file mode 100755
index 0000000..f6ac40d
--- /dev/null
+++ b/board/mx1ads/config.mk
@@ -0,0 +1,25 @@
+#
+# board/mx1ads/config.mk
+#
+# (c) Copyright 2004
+# Techware Information Technology, Inc.
+# http://www.techware.com.tw/
+#
+# Ming-Len Wu <minglen_wu@techware.com.tw>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+TEXT_BASE = 0x08400000
diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S
new file mode 100755
index 0000000..09c260d
--- /dev/null
+++ b/board/mx1ads/lowlevel_init.S
@@ -0,0 +1,81 @@
+/*
+ * board/mx1ads/lowlevel_init.S
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#define SDCTL0			0x221000
+#define SDCTL1			0x221004
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+/* memory controller init	 	*/
+
+	ldr  r1, =SDCTL0
+
+/*  Set Precharge Command		*/
+
+	ldr  r3, =0x92120200
+/*	ldr  r3, =0x92120251
+*/
+	str  r3, [r1]
+
+/* Issue Precharge All Commad		*/
+	ldr  r3, =0x8200000
+	ldr  r2, [r3]
+
+/* Set AutoRefresh Command 		*/
+	ldr  r3, =0xA2120200
+	str  r3, [r1]
+
+/* Issue AutoRefresh Command		*/
+	ldr  r3, =0x8000000
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+
+/* Set Mode Register 			*/
+	ldr  r3, =0xB2120200
+	str  r3, [r1]
+
+/* Issue Mode Register Command		*/
+	ldr  r3, =0x08111800 	/* Mode Register Value 		*/
+	ldr  r2, [r3]
+
+/* Set Normal Mode			*/
+	ldr  r3, =0x82124200
+	str  r3, [r1]
+
+/* everything is fine now 		*/
+	mov	pc, lr
diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
new file mode 100755
index 0000000..5c33ba3
--- /dev/null
+++ b/board/mx1ads/mx1ads.c
@@ -0,0 +1,168 @@
+/*
+ * board/mx1ads/mx1ads.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <mc9328.h>*/
+#include <asm/arch/imx-regs.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV	0xC3
+#define M_PDIV	0x4
+#define M_SDIV	0x1
+#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#define M_MDIV	0xA1
+#define M_PDIV	0x3
+#define M_SDIV	0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV	0xA1
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV	0x48
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x2
+#endif
+
+#if 0
+
+static inline void delay (unsigned long loops) {
+	__asm__ volatile ("1:\n"
+	  "subs %0, %1, #1\n"
+	  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+#endif
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+void SetAsynchMode(void) {
+	__asm__ (
+		"mrc p15,0,r0,c1,c0,0 \n"
+		"mov r2, #0xC0000000 \n"
+		"orr r0,r2,r0 \n"
+		"mcr p15,0,r0,c1,c0,0 \n"
+	);
+}
+
+static u32 mc9328sid;
+
+int board_init (void) {
+
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile unsigned int  tmp;
+
+	mc9328sid	= SIDR;
+
+	GPCR 		= 0x000003AB;		/* I/O pad driving strength 	*/
+
+/*	MX1_CS1U 	= 0x00000A00;	*/	/* SRAM initialization 		*/
+/*	MX1_CS1L 	= 0x11110601; 	*/
+
+	MPCTL0 		= 0x04632410;	/* setting for 150 MHz MCU PLL CLK	*/
+
+/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
+ * BCLK divider to 2 (i.e. BCLK to 48 MHz)
+ */
+	CSCR 	= 0xAF000403;
+
+	CSCR 	|= 0x00200000;   	/* Trigger the restart bit(bit 21)	*/
+	CSCR 	&= 0xFFFF7FFF;		/* Program PRESC bit(bit 15) to 0 to divide-by-1 */
+
+/* setup cs4 for cs8900 ethernet */
+
+	CS4U	= 0x00000F00;	/* Initialize CS4 for CS8900 ethernet 	*/
+	CS4L	= 0x00001501;
+
+	GIUS(0)	&= 0xFF3FFFFF;
+	GPR(0)	&= 0xFF3FFFFF;
+
+	tmp = *(unsigned int *)(0x1500000C);
+	tmp = *(unsigned int *)(0x1500000C);
+
+	SetAsynchMode();
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
+
+	gd->bd->bi_boot_params = 0x08000100;	/* adress of boot parameters	*/
+
+	icache_enable();
+	dcache_enable();
+
+/* set PERCLKs				*/
+	PCDR = 0x00000055;     	/* set PERCLKS				*/
+
+/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
+ * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
+ * all sources selected as normal interrupt
+ */
+
+/*	MX1_INTTYPEH = 0;
+	MX1_INTTYPEL = 0;
+*/
+	return 0;
+}
+
+int board_late_init(void) {
+
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+
+	switch	(mc9328sid) {
+		case 0x0005901d :
+			printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
+			break;
+		case 0x04d4c01d :
+			printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+			break;
+		case 0x00d4c01d :
+			printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+			break;
+
+		default :
+			printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
+			break;
+	}
+	return 0;
+}
+
+int dram_init (void) {
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c
new file mode 100755
index 0000000..eb7fde5
--- /dev/null
+++ b/board/mx1ads/syncflash.c
@@ -0,0 +1,322 @@
+/*
+ * board/mx1ads/syncflash.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <mc9328.h>*/
+#include <asm/arch/imx-regs.h>
+
+typedef unsigned long * p_u32;
+
+/* 4Mx16x2 IAM=0 CSD1 */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*  Following Setting is for CSD1	*/
+#define SFCTL			0x00221004
+#define reg_SFCTL		__REG(SFCTL)
+
+#define SYNCFLASH_A10		(0x00100000)
+
+#define CMD_NORMAL		(0x81020300)			/* Normal Mode			*/
+#define CMD_PREC		(CMD_NORMAL + 0x10000000) 	/* Precharge Command		*/
+#define CMD_AUTO		(CMD_NORMAL + 0x20000000) 	/* Auto Refresh Command		*/
+#define CMD_LMR			(CMD_NORMAL + 0x30000000) 	/* Load Mode Register Command 	*/
+#define CMD_LCR			(CMD_NORMAL + 0x60000000) 	/* LCR Command			*/
+#define CMD_PROGRAM		(CMD_NORMAL + 0x70000000)
+
+#define MODE_REG_VAL		(CFG_FLASH_BASE+0x0008CC00) 	/* Cas Latency 3		*/
+
+/* LCR Command */
+#define LCR_READSTATUS		(0x0001C000)			/* 0x70				*/
+#define LCR_ERASE_CONFIRM	(0x00008000)			/* 0x20				*/
+#define LCR_ERASE_NVMODE	(0x0000C000)			/* 0x30				*/
+#define LCR_PROG_NVMODE		(0x00028000)			/* 0xA0				*/
+#define LCR_SR_CLEAR		(0x00014000)			/* 0x50				*/
+
+/* Get Status register 			*/
+u32 SF_SR(void) {
+	u32 tmp,tmp1;
+
+	reg_SFCTL	= CMD_PROGRAM;
+	tmp 		= __REG(CFG_FLASH_BASE);
+
+	reg_SFCTL	= CMD_NORMAL;
+
+	reg_SFCTL	= CMD_LCR;			/* Activate LCR Mode 		*/
+	tmp1 		= __REG(CFG_FLASH_BASE + LCR_SR_CLEAR);
+
+	return tmp;
+}
+
+/* check if SyncFlash is ready 		*/
+u8 SF_Ready(void) {
+	u32 tmp;
+
+	tmp	= SF_SR();
+
+	if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
+		printf ("SyncFlash Error code %08x\n",tmp);
+	};
+
+	if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
+		printf ("SyncFlash Error code %08x\n",tmp);
+	};
+
+	if (tmp == 0x00800080) 		/* Test Bit 7 of SR	*/
+		return 1;
+	else
+		return 0;
+}
+
+/* Issue the precharge all command 		*/
+void SF_PrechargeAll(void) {
+
+	u32 tmp;
+
+	reg_SFCTL	= CMD_PREC;			/* Set Precharge Command 	*/
+	tmp 		= __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
+}
+
+/* set SyncFlash to normal mode			*/
+void SF_Normal(void) {
+
+	SF_PrechargeAll();
+
+	reg_SFCTL	= CMD_NORMAL;
+}
+
+/* Erase SyncFlash 				*/
+void SF_Erase(u32 RowAddress) {
+	u32 tmp;
+
+	reg_SFCTL	= CMD_NORMAL;
+	tmp 		= __REG(RowAddress);
+
+	reg_SFCTL	= CMD_PREC;
+	tmp 		= __REG(RowAddress);
+
+	reg_SFCTL 	= CMD_LCR;			/* Set LCR mode 		*/
+	__REG(RowAddress + LCR_ERASE_CONFIRM)	= 0;	/* Issue Erase Setup Command 	*/
+
+	reg_SFCTL	= CMD_NORMAL;			/* return to Normal mode 	*/
+	__REG(RowAddress)	= 0xD0D0D0D0; 		/* Confirm			*/
+
+	while(!SF_Ready());
+}
+
+void SF_NvmodeErase(void) {
+	SF_PrechargeAll();
+
+	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
+	__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE)  = 0;	/* Issue Erase Nvmode Reg Command */
+
+	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode 	*/
+	__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0;	/* Confirm 		*/
+
+	while(!SF_Ready());
+}
+
+void SF_NvmodeWrite(void) {
+	SF_PrechargeAll();
+
+	reg_SFCTL 	= CMD_LCR;			/* Set to LCR mode 		*/
+	__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0;	/* Issue Program Nvmode reg command */
+
+	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode 	*/
+	__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; 	/* Confirm not needed 	*/
+}
+
+/****************************************************************************************/
+
+ulong flash_init(void) {
+	int i, j;
+	u32 tmp;
+
+/* Turn on CSD1 for negating RESETSF of SyncFLash */
+
+	reg_SFCTL 	|= 0x80000000;		/* enable CSD1 for SyncFlash 		*/
+	udelay(200);
+
+	reg_SFCTL 	= CMD_LMR;		/* Set Load Mode Register Command 	*/
+	tmp 		= __REG(MODE_REG_VAL);	/* Issue Load Mode Register Command 	*/
+
+	SF_Normal();
+
+	i = 0;
+
+	flash_info[i].flash_id 	=  FLASH_MAN_MT | FLASH_MT28S4M16LC;
+
+	flash_info[i].size 	= FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+
+	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+
+	for (j = 0; j < flash_info[i].sector_count; j++) {
+		flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
+	}
+
+	flash_protect(FLAG_PROTECT_SET,
+		CFG_FLASH_BASE,
+		CFG_FLASH_BASE + monitor_flash_len - 1,
+		&flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		CFG_ENV_ADDR,
+		CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		&flash_info[0]);
+
+	return FLASH_BANK_SIZE;
+}
+
+void flash_print_info (flash_info_t *info) {
+
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case (FLASH_MAN_MT & FLASH_VENDMASK):
+			printf("Micron: ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
+			printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			return;
+			break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses: ");
+
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last) {
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+
+/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last))
+		return ERR_INVAL;
+
+	if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
+		return ERR_UNKNOWN_FLASH_VENDOR;
+
+	prot = 0;
+
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf("protected!\n");
+		return ERR_PROTECTED;
+	}
+/*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+
+	cflag = icache_status();
+	icache_disable();
+	iflag = disable_interrupts();
+
+/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
+
+		printf("Erasing sector %2d ... ", sect);
+
+/* arm simple, non interrupt dependent timer */
+
+		reset_timer_masked();
+
+		SF_NvmodeErase();
+		SF_NvmodeWrite();
+
+		SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect));
+		SF_Normal();
+
+		printf("ok.\n");
+	}
+
+	if (ctrlc())
+		printf("User Interrupt!\n");
+
+	if (iflag)
+		enable_interrupts();
+
+	if (cflag)
+		icache_enable();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
+	int i;
+
+	for(i = 0; i < cnt; i += 4) {
+
+		SF_PrechargeAll();
+
+		reg_SFCTL	= CMD_PROGRAM;		/* Enter SyncFlash Program mode */
+		__REG(addr + i) = __REG((u32)src  + i);
+
+		while(!SF_Ready());
+	}
+
+	SF_Normal();
+
+	return ERR_OK;
+}
diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds
new file mode 100755
index 0000000..8438f99
--- /dev/null
+++ b/board/mx1ads/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * board/mx1ads/u-boot.lds
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/mx1fs2/Makefile b/board/mx1fs2/Makefile
new file mode 100755
index 0000000..9e3bca1
--- /dev/null
+++ b/board/mx1fs2/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= mx1fs2.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mx1fs2/config.mk b/board/mx1fs2/config.mk
new file mode 100755
index 0000000..59ab542
--- /dev/null
+++ b/board/mx1fs2/config.mk
@@ -0,0 +1,10 @@
+#
+# This config file is used for compilation of IMX sources
+#
+# You might change location of U-Boot in memory by setting right TEXT_BASE.
+# This allows for example having one copy located at the end of ram and stored
+# in flash device and later on while developing use other location to test
+# the code in RAM device only.
+#
+
+TEXT_BASE = 0x08f00000
diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c
new file mode 100755
index 0000000..3806310
--- /dev/null
+++ b/board/mx1fs2/flash.c
@@ -0,0 +1,849 @@
+/*
+ * (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) 2003 August Hoeraendl, Logotronic GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef CONFIG_FLASH_16BIT
+
+#include <common.h>
+
+#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE
+#define MAIN_SECT_SIZE  MX1FS2_FLASH_SECT_SIZE
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips   */
+
+/*
+ * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+#if 0
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+#endif
+static void flash_reset(flash_info_t * info);
+static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+#define write_word(in, de, da)   write_word_amd(in, de, da)
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t * info);
+#endif
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+ulong
+flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		flash_info[i].flash_id =
+		    (FLASH_MAN_AMD & FLASH_VENDMASK) |
+		    (FLASH_AM640U & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = MX1FS2_FLASH_BASE;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_FLASH_BASE,
+		      CFG_FLASH_BASE + _bss_start - _armboot_start,
+		      &flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_reset(flash_info_t * info)
+{
+	FPWV *base = (FPWV *) (info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+#if 0
+static void
+flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector  */
+		int sect_size;	/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set sector offsets for bottom boot block type        */
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		   && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;	/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sect_size);
+	}
+}
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------
+ */
+
+void
+flash_print_info(flash_info_t * info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	uchar *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_BM:
+		printf("BRIGHT MICRO ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	} else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf(fmt, bootletter, boottype);
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf("\n   ");
+		}
+
+		printf(" %08lX%s", info->start[i],
+		       info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+#if 0
+ulong
+flash_get_size(FPWV * addr, flash_info_t * info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[0x0555] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[0x02AA] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	addr[0x0555] = (FPW) 0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[0] & 0xff) {
+
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN)
+		switch (addr[1]) {
+
+		case (FPW) AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F800C3B:
+			info->flash_id += FLASH_28F800C3B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F800B3B:
+			info->flash_id += FLASH_INTEL800B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F160C3B:
+			info->flash_id += FLASH_28F160C3B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F160B3B:
+			info->flash_id += FLASH_INTEL160B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F320C3B:
+			info->flash_id += FLASH_28F320C3B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F320B3B:
+			info->flash_id += FLASH_INTEL320B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F640C3B:
+			info->flash_id += FLASH_28F640C3B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F640B3B:
+			info->flash_id += FLASH_INTEL640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* => no or unknown flash */
+		}
+
+	flash_get_offsets((ulong) addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+#endif /* 0 */
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void
+flash_sync_real_protect(flash_info_t * info)
+{
+	FPWV *addr = (FPWV *) (info->start[0]);
+	FPWV *sect;
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		/* check for protected sectors */
+		*addr = (FPW) 0x00900090;
+		for (i = 0; i < info->sector_count; i++) {
+			/* read sector protection at sector address, (A7 .. A0) = 0x02.
+			 * D0 = 1 for each device if protected.
+			 * If at least one device is protected the sector is marked
+			 * protected, but mixed protected and  unprotected devices
+			 * within a sector should never happen.
+			 */
+			sect = (FPWV *) (info->start[i]);
+			info->protect[i] =
+			    (sect[2] & (FPW) (0x00010001)) ? 1 : 0;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+		break;
+
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		break;
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	start = get_timer(0);
+	last = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *) (info->start[sect]);
+		if (intel) {
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;	/* first address in bank */
+
+			base = (FPWV *) (info->start[0]);
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			base[0x0555] = (FPW) 0x00800080;	/* erase mode */
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			*addr = (FPW) 0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay(1000);
+
+		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			if ((now = get_timer(0)) - start > CFG_FLASH_ERASE_TOUT) {
+				printf("Timeout\n");
+
+				if (intel) {
+					/* suspend erase        */
+					*addr = (FPW) 0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;	/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc('.');
+				last = now;
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode   */
+	}
+
+	printf(" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int
+bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;		/* number of bytes to program in current word         */
+	int left;		/* number of bytes left to program                    */
+	int i, res;
+
+	for (left = cnt, res = 0;
+	     left > 0 && res == 0;
+	     addr += sizeof (data), left -= sizeof (data) - bytes) {
+
+		bytes = addr & (sizeof (data) - 1);
+		addr &= ~(sizeof (data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof (data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *) addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *) addr, data);
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel(info, (FPWV *) addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/**
+ * write_buf: - Copy memory to flash.
+ *
+ * @param info:
+ * @param src:	source of copy transaction
+ * @param addr:	where to copy to
+ * @param cnt: 	number of bytes to copy
+ *
+ * @return	error code
+ */
+
+int
+write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/* handle unaligned start bytes */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/* handle word aligned part */
+	while (cnt >= 2) {
+		/* data = *((vushort*)src); */
+		data = *((FPW *) src);
+		if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
+			return (rc);
+		}
+		src += sizeof (FPW);
+		wp += sizeof (FPW);
+		cnt -= sizeof (FPW);
+	}
+
+	if (cnt == 0)
+		return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word(info, (FPWV *)wp, data);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word_amd(flash_info_t * info, FPWV * dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+	FPWV *base;		/* first address in flash bank  */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (info->start[0]);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+	base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+	base[0x0555] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer(0) - start > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			printf("SHA timeout\n");
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word_intel(flash_info_t * info, FPWV * dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+	*dest = (FPW) 0x00400040;	/* program setup                */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00B000B0;	/* Suspend program      */
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW) 0x00100010))
+		res = 1;	/* write failed, time out error is close enough */
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+
+	return (res);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int
+flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset(info);	/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset(info);	/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect(info);
+		break;
+
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
diff --git a/board/mx1fs2/intel.h b/board/mx1fs2/intel.h
new file mode 100755
index 0000000..8db5dd4
--- /dev/null
+++ b/board/mx1fs2/intel.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef	FLASH_INTEL_H
+#define	FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define	CFI_CHIP_INTEL_28F320J3A		0x0016
+#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
+#define	CFI_CHIP_INTEL_28F640J3A		0x0017
+#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
+#define	CFI_CHIP_INTEL_28F128J3A		0x0018
+#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define	CFI_CHIP_INTEL_28F640K3			0x8801
+#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
+#define	CFI_CHIP_INTEL_28F128K3			0x8802
+#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
+#define	CFI_CHIP_INTEL_28F256K3			0x8803
+#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
+#define	CFI_CHIP_INTEL_28F640K18		0x8805
+#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
+#define	CFI_CHIP_INTEL_28F128K18		0x8806
+#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
+#define	CFI_CHIP_INTEL_28F256K18		0x8807
+#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
+
+#endif				/* FLASH_INTEL_H */
diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S
new file mode 100755
index 0000000..8211beb
--- /dev/null
+++ b/board/mx1fs2/lowlevel_init.S
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+	ldr		r0,	=PCDR
+	ldr		r1,	=CFG_PCDR_VAL
+	str		r1,   [r0]
+
+/* set MCU PLL Control Register 0 */
+
+	ldr		r0,	=MPCTL0
+	ldr		r1,	=CFG_MPCTL0_VAL
+	str		r1,   [r0]
+
+/* set MCU PLL Control Register 1 */
+
+	ldr		r0,	=MPCTL1
+	ldr		r1,	=CFG_MPCTL1_VAL
+	str		r1,   [r0]
+
+/* set mpll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<21)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+/* set System PLL Control Register 0 */
+
+	ldr		r0,	=SPCTL0
+	ldr		r1,	=CFG_SPCTL0_VAL
+	str		r1,   [r0]
+
+/* set System PLL Control Register 1 */
+
+	ldr		r0,	=SPCTL1
+	ldr		r1,	=CFG_SPCTL1_VAL
+	str		r1,   [r0]
+
+/* set spll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<22)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+	ldr		r0,   =CSCR
+	ldr		r1,   =CFG_CSCR_VAL
+	str		r1,   [r0]
+
+	ldr		r0,   =GPCR
+	ldr		r1,   =CFG_GPCR_VAL
+	str		r1,   [r0]
+
+/*
+ * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ * this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too!  Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+ *
+ * Slapping this into my bootloader does the trick...
+ *
+ * MRC p15,0,r0,c1,c0,0    ; read core configuration register
+ * ORR r0,r0,#0xC0000000   ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0    ; write modified value to core configuration
+ * register
+ *
+ */
+	MRC p15,0,r0,c1,c0,0
+/*	ORR r0,r0,#0xC0000000 async mode */
+/*	ORR r0,r0,#0x40000000 sync mode */
+	ORR r0,r0,#0xC0000000
+	MCR p15,0,r0,c1,c0,0
+
+	ldr		r0,	=GIUS(0)
+	ldr		r1,	=CFG_GIUS_A_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=FMCR
+	ldr		r1,	=CFG_FMCR_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0U
+	ldr		r1,	=CFG_CS0U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0L
+	ldr		r1,	=CFG_CS0L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1U
+	ldr		r1,	=CFG_CS1U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1L
+	ldr		r1,	=CFG_CS1L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4U
+	ldr		r1,	=CFG_CS4U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4L
+	ldr		r1,	=CFG_CS4L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5U
+	ldr		r1,	=CFG_CS5U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5L
+	ldr		r1,	=CFG_CS5L_VAL
+	str		r1,   [r0]
+
+/* SDRAM Setup */
+
+	ldr  r1,=0x00221000   /* adr of SDCTRL0			*/
+	ldr  r0,=0x92120200
+	str  r0,[r1,#0]       /* put in precharge command mode    */
+	ldr  r2,=0x08200000   /* adr for precharge cmd 	   */
+	ldr  r0,[r2,#0]       /* precharge			   */
+	ldr  r0,=0xA2120200
+	ldr  r2,=0x08000000   /* start of SDRAM		   */
+	str  r0,[r1,#0]       /* put in auto-refresh mode	   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,=0xB2120200
+	ldr  r2,=0x08111800
+	str  r0,[r1,#0]       /* setup for mode register of SDRAM */
+	ldr  r0,[r2,#0]       /* program mode register 	   */
+	ldr  r0,=0x82124267
+	str  r0,[r1,#0]       /* back to normal operation	   */
+
+	mov	pc,r10
diff --git a/board/mx1fs2/mx1fs2.c b/board/mx1fs2/mx1fs2.c
new file mode 100755
index 0000000..9e7a06c
--- /dev/null
+++ b/board/mx1fs2/mx1fs2.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#include <asm/arch/imx-regs.h>
+
+#define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+
+extern void imx_gpio_mode(int gpio_mode);
+
+static void logo_init(void)
+{
+	imx_gpio_mode(PD15_PF_LD0);
+	imx_gpio_mode(PD16_PF_LD1);
+	imx_gpio_mode(PD17_PF_LD2);
+	imx_gpio_mode(PD18_PF_LD3);
+	imx_gpio_mode(PD19_PF_LD4);
+	imx_gpio_mode(PD20_PF_LD5);
+	imx_gpio_mode(PD21_PF_LD6);
+	imx_gpio_mode(PD22_PF_LD7);
+	imx_gpio_mode(PD23_PF_LD8);
+	imx_gpio_mode(PD24_PF_LD9);
+	imx_gpio_mode(PD25_PF_LD10);
+	imx_gpio_mode(PD26_PF_LD11);
+	imx_gpio_mode(PD27_PF_LD12);
+	imx_gpio_mode(PD28_PF_LD13);
+	imx_gpio_mode(PD29_PF_LD14);
+	imx_gpio_mode(PD30_PF_LD15);
+	imx_gpio_mode(PD14_PF_FLM_VSYNC);
+	imx_gpio_mode(PD13_PF_LP_HSYNC);
+	imx_gpio_mode(PD6_PF_LSCLK);
+	imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO);
+	imx_gpio_mode(PD11_PF_CONTRAST);
+	imx_gpio_mode(PD10_PF_SPL_SPR);
+
+	LCDC_RMCR = 0x00000000;
+	LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5);
+	LCDC_HCR = HCR_H_WIDTH(2);
+	LCDC_VCR = VCR_V_WIDTH(2);
+
+	LCDC_PWMR = 0x00000380;   /* contrast to 0x80 middle (is best !!!) */
+	LCDC_SSA  = 0x10040000;   /* image in flash */
+
+	LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240);   /* screen size */
+
+	LCDC_VPW  = 0x000000A0;   /* Virtual Page Width Register */
+	LCDC_POS  = 0x00000000;   /* panning offset 0 (0 pixel offset) */
+
+	/* disable Cursor */
+	LCDC_CPOS  = 0x00000000;
+
+	/* fixed burst length */
+	LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2);
+
+	/* enable LCD */
+	DR(3)   |= 0x00001000;
+	LCDC_RMCR = RMCR_LCDC_EN;
+
+}
+
+int
+board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX1FS2;
+	gd->bd->bi_boot_params = 0x08000100;
+serial_init();
+	logo_init();
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+	gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1;
+	gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE;
+#endif
+	return 0;
+}
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ */
+
+void
+show_boot_progress(int status)
+{
+	/* We use this as a hook to disable serial ports just before booting
+	 * This way we suppress the "uncompressing linux..." message
+	 */
+#ifdef CONFIG_SILENT_CONSOLE
+	if( status == 8) {
+		if( getenv("silent") != NULL ) {
+			*(volatile unsigned long *)0x206080 &= ~1;
+			*(volatile unsigned long *)0x207080 &= ~1;
+		}
+	}
+#endif
+	return;
+}
diff --git a/board/mx1fs2/u-boot.lds b/board/mx1fs2/u-boot.lds
new file mode 100755
index 0000000..1d1669c
--- /dev/null
+++ b/board/mx1fs2/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/arm920t/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/nc650/Makefile b/board/nc650/Makefile
new file mode 100755
index 0000000..a4dd85f
--- /dev/null
+++ b/board/nc650/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/nc650/config.mk b/board/nc650/config.mk
new file mode 100755
index 0000000..fa8ba31
--- /dev/null
+++ b/board/nc650/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# NC650 board
+#
+
+TEXT_BASE = 0x40700000
diff --git a/board/nc650/flash.c b/board/nc650/flash.c
new file mode 100755
index 0000000..ce2f83b
--- /dev/null
+++ b/board/nc650/flash.c
@@ -0,0 +1,542 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
+#define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				      OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH8
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#elif FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#else /* FLASH_PORT_WIDTH8 */
+#define FLASH_PORT_WIDTH	uchar
+#define FLASH_PORT_WIDTHV	vu_char
+#endif
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPWV * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
+	int scy, trlx, flash_or_timing, clk_diff;
+
+	DECLARE_GLOBAL_DATA_PTR;
+
+	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+		trlx = OR_TRLX;
+		scy *= 2;
+	} else
+		trlx = 0;
+
+		/* We assume that each 10MHz of bus clock require 1-clk SCY
+		 * adjustment.
+		 */
+	clk_diff = (gd->bus_clk / 1000000) - 50;
+
+		/* We need proper rounding here. This is what the "+5" and "-5"
+		 * are here for.
+		 */
+	if (clk_diff >= 0)
+		scy += (clk_diff + 5) / 10;
+	else
+		scy += (clk_diff - 5) / 10;
+
+		/* For bus frequencies above 50MHz, we want to use relaxed
+		 * timing (OR_TRLX).
+		 */
+	if (gd->bus_clk >= 50000000)
+		trlx = OR_TRLX;
+	else
+		trlx = 0;
+
+	if (trlx)
+		scy /= 2;
+
+	if (scy > 0xf)
+		scy = 0xf;
+	if (scy < 1)
+		scy = 1;
+
+	flash_or_timing = (scy << 4) | trlx |
+			  (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+#endif
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	/* Remap FLASH according to real size */
+#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+#else
+	memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
+#endif
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPWV * addr, flash_info_t * info)
+{
+	FPW value;
+
+	addr[0] = (FPW) 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+#ifdef FLASH_PORT_WIDTH8
+	value = addr[2];			/* device ID        */
+#else
+	value = addr[1];			/* device ID        */
+#endif
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 4 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+				rcode = 1;
+				break;
+			    }
+
+			    /* show that we're waiting */
+			    if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			    }
+			}
+
+			*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+
+	int i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#elif defined(FLASH_PORT_WIDTH32)
+	wp = (addr & ~3);
+	port_width = 4;
+#else
+	wp = addr;
+	port_width = 1;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
new file mode 100755
index 0000000..fe96b93
--- /dev/null
+++ b/board/nc650/nc650.c
@@ -0,0 +1,253 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/*
+ *  Memory Controller Using
+ *
+ *  CS0 - Flash memory            (0x40000000)
+ *  CS3 - SDRAM                   (0x00000000}
+ */
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_	0xffffffff
+
+const uint sdram_table[] = {
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* MRS initialization (offset 5) */
+
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_
+};
+
+const uint nand_flash_table[] = {
+	/* single read. (offset 0 in upm RAM) */
+	0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
+	0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
+	0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+
+	/* exception. (offset 3c in upm RAM) */
+	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: NC650\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
+	unsigned long reg;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 1 to the SDRAM bank at
+	 * preliminary address - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 0 */
+	udelay (200);
+	memctl->memc_mcr = 0x80006230;	/* SDRAM bank 0 - execute twice */
+	udelay (200);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
+					  SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	if (size8 < size9) {
+		size_b0 = size9;
+	} else {
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+	}
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks.
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+
+	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;					/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+	/* Configure UPMB for NAND flash access */
+	upmconfig (UPMB, (uint *) nand_flash_table,
+			   sizeof (nand_flash_table) / sizeof (uint));
+
+	memctl->memc_mbmr = CFG_MBMR_NAND;
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_init(void)
+{
+	extern unsigned long nand_probe(unsigned long physadr);
+
+	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds
new file mode 100755
index 0000000..ca44918
--- /dev/null
+++ b/board/nc650/u-boot.lds
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/nc650/u-boot.lds.debug b/board/nc650/u-boot.lds.debug
new file mode 100755
index 0000000..2228a20
--- /dev/null
+++ b/board/nc650/u-boot.lds.debug
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/netphone/Makefile b/board/netphone/Makefile
new file mode 100755
index 0000000..b3c1797
--- /dev/null
+++ b/board/netphone/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o phone_console.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/netphone/config.mk b/board/netphone/config.mk
new file mode 100755
index 0000000..8497ebc
--- /dev/null
+++ b/board/netphone/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# netVia Boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/netphone/flash.c b/board/netphone/flash.c
new file mode 100755
index 0000000..0c81140
--- /dev/null
+++ b/board/netphone/flash.c
@@ -0,0 +1,529 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+#if CONFIG_NETPHONE_VERSION == 2
+	unsigned long size1;
+#endif
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size;
+
+#if CONFIG_NETPHONE_VERSION == 2
+	size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]);
+	if (size1 > 0) {
+		if (flash_info[1].flash_id == FLASH_UNKNOWN)
+			printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
+
+		/* Remap FLASH according to real size */
+		memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
+		memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
+
+		/* Re-do sizing to get full correct info */
+		size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]);
+
+		flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]);
+
+		size += size1;
+	} else
+		memctl->memc_br4 &= ~BR_V;
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c
new file mode 100755
index 0000000..dd03e4b
--- /dev/null
+++ b/board/netphone/netphone.c
@@ -0,0 +1,722 @@
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <sed156x.h>
+#include <status_led.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define GPL0_AAAA	0x00000000
+#define GPL0_AAA0	0x00200000
+#define GPL0_AAA1	0x00300000
+#define GPL0_000A	0x00800000
+#define GPL0_0000	0x00A00000
+#define GPL0_0001	0x00B00000
+#define GPL0_111A	0x00C00000
+#define GPL0_1110	0x00E00000
+#define GPL0_1111	0x00F00000
+
+#define GPL1_0000	0x00000000
+#define GPL1_0001	0x00040000
+#define GPL1_1110	0x00080000
+#define GPL1_1111	0x000C0000
+
+#define GPL2_0000	0x00000000
+#define GPL2_0001	0x00010000
+#define GPL2_1110	0x00020000
+#define GPL2_1111	0x00030000
+
+#define GPL3_0000	0x00000000
+#define GPL3_0001	0x00004000
+#define GPL3_1110	0x00008000
+#define GPL3_1111	0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+#define A10_AAAA	GPL0_AAAA
+#define A10_AAA0	GPL0_AAA0
+#define A10_AAA1	GPL0_AAA1
+#define A10_000A	GPL0_000A
+#define A10_0000	GPL0_0000
+#define A10_0001	GPL0_0001
+#define A10_111A	GPL0_111A
+#define A10_1110	GPL0_1110
+#define A10_1111	GPL0_1111
+
+#define RAS_0000	GPL1_0000
+#define RAS_0001	GPL1_0001
+#define RAS_1110	GPL1_1110
+#define RAS_1111	GPL1_1111
+
+#define CAS_0000	GPL2_0000
+#define CAS_0001	GPL2_0001
+#define CAS_1110	GPL2_1110
+#define CAS_1111	GPL2_1111
+
+#define WE_0000		GPL3_0000
+#define WE_0001		GPL3_0001
+#define WE_1110		GPL3_1110
+#define WE_1111		GPL3_1111
+
+/* #define CAS_LATENCY	3  */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+#if CONFIG_NETPHONE_VERSION == 2
+static const uint nandcs_table[0x40] = {
+	/* RSS */
+	CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111,
+	CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,	/* NOP   */
+
+	/* RBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+	/* WBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 ,
+	CS_0001 | LAST,
+};
+#endif
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 8 */
+#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+long int initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+	{
+		u32 d1, d2;
+
+		d1 = 0xAA55AA55;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+
+		d1 = 0x55AA55AA;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+	if (size == 0) {
+		printf("SIZE is zero: LOOP on 0\n");
+		for (;;) {
+			*(volatile u32 *)0 = 0;
+			(void)*(volatile u32 *)0;
+		}
+	}
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	udelay(10000);
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
+		if (v == 0xFFFF)
+			continue;
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
+		udelay(10000);
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+				PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		udelay(10000);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	0
+#define PA_GP_OUTMASK	(_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
+#define PA_SP_MASK	0
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(3) | _BW(14) | _BW(15))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	_B(28)
+#define PB_GP_OUTMASK	(_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_MASK	(_BR(22, 25))
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_DIRVAL	0
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define PC_GP_INMASK	_BW(12)
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(13) | _BW(15))
+#elif CONFIG_NETPHONE_VERSION == 2
+#define PC_GP_INMASK	(_BW(13) | _BW(15))
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(12))
+#endif
+#define PC_SP_MASK	0
+#define PC_SOVAL	0
+#define PC_INTVAL	0
+#define PC_GP_OUTVAL	(_BW(10) | _BW(11))
+#define PC_SP_DIRVAL	0
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define PE_GP_INMASK	_B(31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27) | _B(28))
+#elif CONFIG_NETPHONE_VERSION == 2
+#define PE_GP_INMASK	_BR(28, 31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27))
+#endif
+#define PE_SP_MASK	0
+#define PE_ODR_VAL	0
+#define PE_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* NAND chip select */
+#if CONFIG_NETPHONE_VERSION == 1
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#elif CONFIG_NETPHONE_VERSION == 2
+	upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
+	memctl->memc_mamr = 0;	/* all clear */
+#endif
+
+	/* DSP chip select */
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
+	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+#if CONFIG_NETPHONE_VERSION == 1
+	memctl->memc_br4 &= ~BR_V;
+#endif
+	memctl->memc_br5 &= ~BR_V;
+	memctl->memc_br6 &= ~BR_V;
+	memctl->memc_br7 &= ~BR_V;
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	cpm->cp_pedat		= PE_GP_OUTVAL;
+	cpm->cp_peodr		= PE_ODR_VAL;
+	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;
+	cpm->cp_pepar		= PE_SP_MASK;
+
+	return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <linux/mtd/nand.h>
+
+extern ulong nand_probe(ulong physadr);
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	unsigned long totlen;
+
+	totlen = nand_probe(CFG_NAND_BASE);
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
+
+#ifdef CONFIG_SHOW_ACTIVITY
+
+static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ;	/* poll */
+
+/* called from timer interrupt every 1/CFG_HZ sec */
+void board_show_activity(ulong timestamp)
+{
+	if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
+		--left_to_poll;
+}
+
+extern void phone_console_do_poll(void);
+
+static void do_poll(void)
+{
+	unsigned int base;
+
+	while (left_to_poll <= 0) {
+		phone_console_do_poll();
+		base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
+		do {
+			left_to_poll = base;
+		} while (base != left_to_poll);
+	}
+}
+
+/* called when looping */
+void show_activity(int arg)
+{
+	do_poll();
+}
+
+#endif
+
+#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	/* printf("overwrite_console called\n"); */
+	return 0;
+}
+#endif
+
+extern int drv_phone_init(void);
+extern int drv_phone_use_me(void);
+extern int drv_phone_is_idle(void);
+
+int misc_init_r(void)
+{
+	return drv_phone_init();
+}
+
+int last_stage_init(void)
+{
+	int i;
+
+#if CONFIG_NETPHONE_VERSION == 2
+	/* assert peripheral reset */
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+	for (i = 0; i < 10; i++)
+		udelay(1000);
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
+#endif
+	reset_phys();
+
+	/* check in order to enable the local console */
+	left_to_poll = PHONE_CONSOLE_POLL_HZ;
+	i = CFG_HZ * 2;
+	while (i > 0) {
+
+	       	if (tstc()) {
+			getc();
+			break;
+		}
+
+		do_poll();
+
+		if (drv_phone_use_me()) {
+			status_led_set(0, STATUS_LED_ON);
+			while (!drv_phone_is_idle()) {
+				do_poll();
+				udelay(1000000 / CFG_HZ);
+			}
+
+			console_assign(stdin, "phone");
+			console_assign(stdout, "phone");
+			console_assign(stderr, "phone");
+			setenv("bootdelay", "-1");
+			break;
+		}
+
+		udelay(1000000 / CFG_HZ);
+		i--;
+		left_to_poll--;
+	}
+	left_to_poll = PHONE_CONSOLE_POLL_HZ;
+
+	return 0;
+}
diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c
new file mode 100755
index 0000000..408ada0
--- /dev/null
+++ b/board/netphone/phone_console.c
@@ -0,0 +1,1144 @@
+/*
+ * (C) Copyright 2004 Intracom S.A.
+ * Pantelis Antoniou <panto@intracom.gr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * phone_console.c
+ *
+ * A phone based console
+ *
+ * Virtual display of 80x24 characters.
+ * The actual display is much smaller and panned to show the virtual one.
+ * Input is made by a numeric keypad utilizing the input method of
+ * mobile phones. Sorry no T9 lexicons...
+ *
+ */
+
+#include <common.h>
+
+#include <version.h>
+#include <linux/types.h>
+#include <devices.h>
+
+#include <sed156x.h>
+
+/*************************************************************************************************/
+
+#define ROWS	24
+#define COLS	80
+
+#define REFRESH_HZ		(CFG_HZ/50)	/* refresh every 20ms */
+#define BLINK_HZ		(CFG_HZ/2)	/* cursor blink every 500ms */
+
+/*************************************************************************************************/
+
+#define DISPLAY_BACKLIT_PORT	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat
+#define DISPLAY_BACKLIT_MASK	0x0010
+
+/*************************************************************************************************/
+
+#define KP_STABLE_HZ		(CFG_HZ/100)	/* stable for 10ms */
+#define KP_REPEAT_DELAY_HZ	(CFG_HZ/4)	/* delay before repeat 250ms */
+#define KP_REPEAT_HZ		(CFG_HZ/20)	/* repeat every 50ms */
+#define KP_FORCE_DELAY_HZ	(CFG_HZ/2)	/* key was force pressed */
+#define KP_IDLE_DELAY_HZ	(CFG_HZ/2)	/* key was released and idle */
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_RXD_MASK 0x0008
+
+#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_TXD_MASK 0x0004
+
+#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_CLK_MASK 0x0001
+#elif CONFIG_NETPHONE_VERSION == 2
+#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_RXD_MASK 0x00000008
+
+#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_TXD_MASK 0x00000004
+
+#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_CLK_MASK 0x00000002
+#endif
+
+#define KP_CS_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat)
+#define KP_CS_MASK	0x00000010
+
+#define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK)
+
+#define KP_SPI_TXD(x) \
+	do { \
+		if (x) \
+			KP_SPI_TXD_PORT |=  KP_SPI_TXD_MASK; \
+		else \
+			KP_SPI_TXD_PORT &= ~KP_SPI_TXD_MASK; \
+	} while(0)
+
+#define KP_SPI_CLK(x) \
+	do { \
+		if (x) \
+			KP_SPI_CLK_PORT |=  KP_SPI_CLK_MASK; \
+		else \
+			KP_SPI_CLK_PORT &= ~KP_SPI_CLK_MASK; \
+	} while(0)
+
+#define KP_SPI_CLK_TOGGLE() (KP_SPI_CLK_PORT ^= KP_SPI_CLK_MASK)
+
+#define KP_SPI_BIT_DELAY()	/* no delay */
+
+#define KP_CS(x) \
+	do { \
+		if (x) \
+			KP_CS_PORT |=  KP_CS_MASK; \
+		else \
+			KP_CS_PORT &= ~KP_CS_MASK; \
+	} while(0)
+
+#define KP_ROWS 7
+#define KP_COLS 4
+
+#define KP_ROWS_MASK	((1 << KP_ROWS) - 1)
+#define KP_COLS_MASK	((1 << KP_COLS) - 1)
+
+#define SCAN		0
+#define SCAN_FILTER	1
+#define SCAN_COL	2
+#define SCAN_COL_FILTER 3
+#define PRESSED		4
+
+#define KP_F1	0	/* leftmost dot (tab)	*/
+#define KP_F2	1	/* middle left dot	*/
+#define KP_F3	2	/* up			*/
+#define KP_F4	3	/* middle right dot	*/
+#define KP_F5	4	/* rightmost dot	*/
+#define KP_F6	5	/* C			*/
+#define KP_F7	6	/* left			*/
+#define KP_F8	7	/* down			*/
+#define KP_F9	8	/* right		*/
+#define KP_F10	9	/* enter		*/
+#define KP_F11	10	/* R			*/
+#define KP_F12	11	/* save			*/
+#define KP_F13	12	/* redial		*/
+#define KP_F14	13	/* speaker		*/
+#define KP_F15	14	/* unused		*/
+#define KP_F16	15	/* unused		*/
+
+#define KP_RELEASE		-1	/* key depressed				*/
+#define KP_FORCE		-2	/* key was pressed for more than force hz	*/
+#define KP_IDLE			-3	/* key was released and idle			*/
+
+#define KP_1	'1'
+#define KP_2	'2'
+#define KP_3	'3'
+#define KP_4	'4'
+#define KP_5	'5'
+#define KP_6	'6'
+#define KP_7	'7'
+#define KP_8	'8'
+#define KP_9	'9'
+#define KP_0	'0'
+#define KP_STAR '*'
+#define KP_HASH '#'
+
+/*************************************************************************************************/
+
+static int curs_disabled;
+static int curs_col, curs_row;
+static int disp_col, disp_row;
+
+static int width, height;
+
+/* the simulated vty buffer */
+static char vty_buf[ROWS * COLS];
+static char last_visible_buf[ROWS * COLS];	/* worst case */
+static char *last_visible_curs_ptr;
+static int last_visible_curs_rev;
+static int blinked_state;
+static int last_input_mode;
+static int refresh_time;
+static int blink_time;
+static char last_fast_punct;
+
+/*************************************************************************************************/
+
+#define IM_SMALL	0
+#define IM_CAPITAL	1
+#define IM_NUMBER	2
+
+static int input_mode;
+static char fast_punct;
+static int tab_indicator;
+static const char *fast_punct_list = ",.:;*";
+
+static const char *input_mode_txt[] = { "abc", "ABC", "123" };
+
+static const char *punct = ".,!;?'\"-()@/:_+&%*=<>$[]{}\\~^#|";
+static const char *whspace = " 0\n";
+/* per mode character select (for 2-9) */
+static const char *digits_sel[2][8] = {
+	{	/* small */
+		"abc2",					/* 2 */
+		"def3",					/* 3 */
+		"ghi4",					/* 4 */
+		"jkl5",					/* 5 */
+		"mno6",					/* 6 */
+		"pqrs7",				/* 7 */
+		"tuv8",					/* 8 */
+		"wxyz9",				/* 9 */
+	}, {	/* capital */
+		"ABC2",					/* 2 */
+		"DEF3",					/* 3 */
+		"GHI4",					/* 4 */
+		"JKL5",					/* 5 */
+		"MNO6",					/* 6 */
+		"PQRS7",				/* 7 */
+		"TUV8",					/* 8 */
+		"WXYZ9",				/* 9 */
+	}
+};
+
+/*****************************************************************************/
+
+static void update(void);
+static void ensure_visible(int col, int row, int dx, int dy);
+
+static void console_init(void)
+{
+	curs_disabled = 0;
+	curs_col = 0;
+	curs_row = 0;
+
+	disp_col = 0;
+	disp_row = 0;
+
+	input_mode = IM_SMALL;
+	fast_punct = ',';
+	last_fast_punct = '\0';
+	refresh_time = REFRESH_HZ;
+	blink_time = BLINK_HZ;
+
+	memset(vty_buf, ' ', sizeof(vty_buf));
+
+	memset(last_visible_buf, ' ', sizeof(last_visible_buf));
+	last_visible_curs_ptr = NULL;
+	last_input_mode = -1;
+	last_visible_curs_rev = 0;
+
+	blinked_state = 0;
+
+	sed156x_init();
+	width = sed156x_text_width;
+	height = sed156x_text_height - 1;
+
+	tab_indicator = 0;
+}
+
+/*****************************************************************************/
+
+void phone_putc(const char c);
+
+/*****************************************************************************/
+
+static int  queued_char = -1;
+static int  enabled = 0;
+
+/*****************************************************************************/
+
+/* flush buffers */
+int phone_start(void)
+{
+	console_init();
+
+	update();
+	sed156x_sync();
+
+	enabled = 1;
+	queued_char = 'U' - '@';
+
+	/* backlit on */
+	DISPLAY_BACKLIT_PORT &= ~DISPLAY_BACKLIT_MASK;
+
+	return 0;
+}
+
+int phone_stop(void)
+{
+	enabled = 0;
+
+	sed156x_clear();
+	sed156x_sync();
+
+	/* backlit off */
+	DISPLAY_BACKLIT_PORT |= DISPLAY_BACKLIT_MASK;
+
+	return 0;
+}
+
+void phone_puts(const char *s)
+{
+	int count = strlen(s);
+
+	while (count--)
+		phone_putc(*s++);
+}
+
+int phone_tstc(void)
+{
+	return queued_char >= 0 ? 1 : 0;
+}
+
+int phone_getc(void)
+{
+	int r;
+
+	if (queued_char < 0)
+		return -1;
+
+	r = queued_char;
+	queued_char = -1;
+
+	return r;
+}
+
+/*****************************************************************************/
+
+int drv_phone_init(void)
+{
+	device_t console_dev;
+
+	console_init();
+
+	memset(&console_dev, 0, sizeof(console_dev));
+	strcpy(console_dev.name, "phone");
+	console_dev.ext = DEV_EXT_VIDEO;	/* Video extensions */
+	console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	console_dev.start = phone_start;
+	console_dev.stop = phone_stop;
+	console_dev.putc = phone_putc;	/* 'putc' function */
+	console_dev.puts = phone_puts;	/* 'puts' function */
+	console_dev.tstc = phone_tstc;	/* 'tstc' function */
+	console_dev.getc = phone_getc;	/* 'getc' function */
+
+	if (device_register(&console_dev) == 0)
+		return 1;
+
+	return 0;
+}
+
+static int use_me;
+
+int drv_phone_use_me(void)
+{
+	return use_me;
+}
+
+static void kp_do_poll(void);
+
+void phone_console_do_poll(void)
+{
+	int i, x, y;
+
+	kp_do_poll();
+
+	if (enabled) {
+		/* do the blink */
+		blink_time -= PHONE_CONSOLE_POLL_HZ;
+		if (blink_time <= 0) {
+			blink_time += BLINK_HZ;
+			if (last_visible_curs_ptr) {
+				i = last_visible_curs_ptr - last_visible_buf;
+				x = i % width; y = i / width;
+				sed156x_reverse_at(x, y, 1);
+				last_visible_curs_rev ^= 1;
+			}
+		}
+
+		/* do the refresh */
+		refresh_time -= PHONE_CONSOLE_POLL_HZ;
+		if (refresh_time <= 0) {
+			refresh_time += REFRESH_HZ;
+			sed156x_sync();
+		}
+	}
+
+}
+
+static int last_scancode = -1;
+static int forced_scancode = 0;
+static int input_state = -1;
+static int input_scancode = -1;
+static int input_selected_char = -1;
+static char input_covered_char;
+
+static void putchar_at_cursor(char c)
+{
+	vty_buf[curs_row * COLS + curs_col] = c;
+	ensure_visible(curs_col, curs_row, 1, 1);
+}
+
+static char getchar_at_cursor(void)
+{
+	return vty_buf[curs_row * COLS + curs_col];
+}
+
+static void queue_input_char(char c)
+{
+	if (c <= 0)
+		return;
+
+	queued_char = c;
+}
+
+static void terminate_input(void)
+{
+	if (input_state < 0)
+		return;
+
+	if (input_selected_char >= 0)
+		queue_input_char(input_selected_char);
+
+	input_state = -1;
+	input_selected_char = -1;
+	putchar_at_cursor(input_covered_char);
+
+	curs_disabled = 0;
+	blink_time = BLINK_HZ;
+	update();
+}
+
+static void handle_enabled_scancode(int scancode)
+{
+	char c;
+	int new_disp_col, new_disp_row;
+	const char *sel;
+
+
+	switch (scancode) {
+
+			/* key was released */
+		case KP_RELEASE:
+			forced_scancode = 0;
+			break;
+
+			/* key was forced */
+		case KP_FORCE:
+
+			switch (last_scancode) {
+				case '#':
+					if (input_mode == IM_NUMBER) {
+						input_mode = IM_CAPITAL;
+						/* queue backspace to erase # */
+						queue_input_char('\b');
+					} else {
+						input_mode = IM_NUMBER;
+						fast_punct = '*';
+					}
+					update();
+					break;
+
+				case '0': case '1':
+				case '2': case '3': case '4': case '5':
+				case '6': case '7': case '8': case '9':
+
+					if (input_state < 0)
+						break;
+
+					input_selected_char = last_scancode;
+					putchar_at_cursor((char)input_selected_char);
+					terminate_input();
+
+					break;
+
+				default:
+					break;
+			}
+
+			break;
+
+			/* release and idle */
+		case KP_IDLE:
+			input_scancode = -1;
+			if (input_state < 0)
+				break;
+			terminate_input();
+			break;
+
+			/* change input mode */
+		case '#':
+			if (last_scancode == '#')	/* no repeat */
+				break;
+
+			if (input_mode == IM_NUMBER) {
+				input_scancode = scancode;
+				input_state = 0;
+				input_selected_char = scancode;
+				input_covered_char = getchar_at_cursor();
+				putchar_at_cursor((char)input_selected_char);
+				terminate_input();
+				break;
+			}
+
+			if (input_mode == IM_SMALL)
+				input_mode = IM_CAPITAL;
+			else
+				input_mode = IM_SMALL;
+
+			update();
+			break;
+
+		case '*':
+			/* no repeat */
+			if (last_scancode == scancode)
+				break;
+
+			if (input_state >= 0)
+				terminate_input();
+
+			input_scancode = fast_punct;
+			input_state = 0;
+			input_selected_char = input_scancode;
+			input_covered_char = getchar_at_cursor();
+			putchar_at_cursor((char)input_selected_char);
+			terminate_input();
+
+			break;
+
+		case '0': case '1':
+		case '2': case '3': case '4': case '5':
+		case '6': case '7': case '8': case '9':
+
+			/* no repeat */
+			if (last_scancode == scancode)
+				break;
+
+			if (input_mode == IM_NUMBER) {
+				input_scancode = scancode;
+				input_state = 0;
+				input_selected_char = scancode;
+				input_covered_char = getchar_at_cursor();
+				putchar_at_cursor((char)input_selected_char);
+				terminate_input();
+				break;
+			}
+
+			if (input_state >= 0 && input_scancode != scancode)
+				terminate_input();
+
+			if (input_state < 0) {
+				curs_disabled = 1;
+				input_scancode = scancode;
+				input_state = 0;
+				input_covered_char = getchar_at_cursor();
+			} else
+				input_state++;
+
+			if (scancode == '0')
+				sel = whspace;
+			else if (scancode == '1')
+				sel = punct;
+			else
+				sel = digits_sel[input_mode][scancode - '2'];
+			c = *(sel + input_state);
+			if (c == '\0') {
+				input_state = 0;
+				c = *sel;
+			}
+
+			input_selected_char = (int)c;
+			putchar_at_cursor((char)input_selected_char);
+			update();
+
+			break;
+
+			/* move visible display */
+		case KP_F3: case KP_F8: case KP_F7: case KP_F9:
+
+			new_disp_col = disp_col;
+			new_disp_row = disp_row;
+
+			switch (scancode) {
+					/* up */
+				case KP_F3:
+					if (new_disp_row <= 0)
+						break;
+					new_disp_row--;
+					break;
+
+					/* down */
+				case KP_F8:
+					if (new_disp_row >= ROWS - height)
+						break;
+					new_disp_row++;
+					break;
+
+					/* left */
+				case KP_F7:
+					if (new_disp_col <= 0)
+						break;
+					new_disp_col--;
+					break;
+
+					/* right */
+				case KP_F9:
+					if (new_disp_col >= COLS - width)
+						break;
+					new_disp_col++;
+					break;
+			}
+
+			/* no change? */
+			if (disp_col == new_disp_col && disp_row == new_disp_row)
+				break;
+
+			disp_col = new_disp_col;
+			disp_row = new_disp_row;
+			update();
+
+			break;
+
+		case KP_F6:	/* backspace */
+			/* inputing something; no backspace sent, just cancel input */
+			if (input_state >= 0) {
+				input_selected_char = -1;	/* cancel */
+				terminate_input();
+				break;
+			}
+			queue_input_char('\b');
+			break;
+
+		case KP_F10:	/* enter */
+			/* inputing something; first cancel input */
+			if (input_state >= 0)
+				terminate_input();
+			queue_input_char('\r');
+			break;
+
+		case KP_F11:	/* R -> Ctrl-C (abort) */
+			if (input_state >= 0)
+				terminate_input();
+			queue_input_char('C' - 'Q');	/* ctrl-c */
+			break;
+
+		case KP_F5:	/* F% -> Ctrl-U (clear line) */
+			if (input_state >= 0)
+				terminate_input();
+			queue_input_char('U' - 'Q');	/* ctrl-c */
+			break;
+
+
+		case KP_F1:	/* tab */
+			/* inputing something; first cancel input */
+			if (input_state >= 0)
+				terminate_input();
+			queue_input_char('\t');
+			break;
+
+		case KP_F2:	/* change fast punct */
+			sel = strchr(fast_punct_list, fast_punct);
+			if (sel == NULL)
+				sel = &fast_punct_list[0];
+			sel++;
+			if (*sel == '\0')
+				sel = &fast_punct_list[0];
+			fast_punct = *sel;
+			update();
+			break;
+
+
+	}
+
+	if (scancode != KP_FORCE && scancode != KP_IDLE)	/* don't record forced or idle scancode */
+		last_scancode = scancode;
+}
+
+static void scancode_action(int scancode)
+{
+#if 0
+	if (scancode == KP_RELEASE)
+		printf(" RELEASE\n");
+	else if (scancode == KP_FORCE)
+		printf(" FORCE\n");
+	else if (scancode == KP_IDLE)
+		printf(" IDLE\n");
+	else if (scancode < 32)
+		printf(" F%d", scancode + 1);
+	else
+		printf(" %c", (char)scancode);
+	printf("\n");
+#endif
+
+	if (enabled) {
+		handle_enabled_scancode(scancode);
+		return;
+	}
+
+	if (scancode == KP_FORCE && last_scancode == '*')
+		use_me = 1;
+
+	last_scancode = scancode;
+}
+
+/**************************************************************************************/
+
+/* update the display; make sure to update only the differences */
+static void update(void)
+{
+	int i;
+	char *s, *e, *t, *r, *b, *cp;
+
+	if (input_mode != last_input_mode)
+		sed156x_output_at(sed156x_text_width - 3, sed156x_text_height - 1, input_mode_txt[input_mode], 3);
+
+	if (tab_indicator == 0) {
+		sed156x_output_at(0, sed156x_text_height - 1, "\\t", 2);
+		tab_indicator = 1;
+	}
+
+	if (fast_punct != last_fast_punct)
+		sed156x_output_at(4, sed156x_text_height - 1, &fast_punct, 1);
+
+	if (curs_disabled ||
+		curs_col < disp_col || curs_col >= (disp_col + width) ||
+		curs_row < disp_row || curs_row >= (disp_row + height)) {
+		cp = NULL;
+	} else
+		cp = last_visible_buf + (curs_row - disp_row) * width + (curs_col - disp_col);
+
+
+	/* printf("(%d,%d) (%d,%d) %s\n", curs_col, curs_row, disp_col, disp_row, cp ? "YES" : "no"); */
+
+	/* clear previous cursor */
+	if (last_visible_curs_ptr && last_visible_curs_rev == 0) {
+		i = last_visible_curs_ptr - last_visible_buf;
+		sed156x_reverse_at(i % width, i / width, 1);
+	}
+
+	b = vty_buf + disp_row * COLS + disp_col;
+	t = last_visible_buf;
+	for (i = 0; i < height; i++) {
+		s = b;
+		e = b + width;
+		/* update only the differences */
+		do {
+			while (s < e && *s == *t) {
+				s++;
+				t++;
+			}
+			if (s == e)	/* no more */
+				break;
+
+			/* find run */
+			r = s;
+			while (s < e && *s != *t)
+				*t++ = *s++;
+
+			/* and update */
+			sed156x_output_at(r - b, i, r, s - r);
+
+		} while (s < e);
+
+		b += COLS;
+	}
+
+	/* set cursor */
+	if (cp) {
+		last_visible_curs_ptr = cp;
+		i = last_visible_curs_ptr - last_visible_buf;
+		sed156x_reverse_at(i % width, i / width, 1);
+		last_visible_curs_rev = 0;
+	} else {
+		last_visible_curs_ptr = NULL;
+	}
+
+	last_input_mode = input_mode;
+	last_fast_punct = fast_punct;
+}
+
+/* ensure visibility; the trick is to minimize the screen movement */
+static void ensure_visible(int col, int row, int dx, int dy)
+{
+	int x1, y1, x2, y2, a1, b1, a2, b2;
+
+	/* clamp visible region */
+	if (col < 0) {
+		dx -= col;
+		col = 0;
+		if (dx <= 0)
+			dx = 1;
+	}
+
+	if (row < 0) {
+		dy -= row;
+		row = 0;
+		if (dy <= 0)
+			dy = 1;
+	}
+
+	if (col + dx > COLS)
+		dx = COLS - col;
+
+	if (row + dy > ROWS)
+		dy = ROWS - row;
+
+
+	/* move to easier to use vars */
+	x1 = disp_col;	 y1 = disp_row;
+	x2 = x1 + width; y2 = y1 + height;
+	a1 = col;	 b1 = row;
+	a2 = a1 + dx;	 b2 = b1 + dy;
+
+	/* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */
+
+	if (a2 > x2) {
+		/* move to the right */
+		x2 = a2;
+		x1 = x2 - width;
+		if (x1 < 0) {
+			x1 = 0;
+			x2 = width;
+		}
+	} else if (a1 < x1) {
+		/* move to the left */
+		x1 = a1;
+		x2 = x1 + width;
+		if (x2 > COLS) {
+			x2 = COLS;
+			x1 = x2 - width;
+		}
+	}
+
+	if (b2 > y2) {
+		/* move down */
+		y2 = b2;
+		y1 = y2 - height;
+		if (y1 < 0) {
+			y1 = 0;
+			y2 = height;
+		}
+	} else if (b1 < y1) {
+		/* move up */
+		y1 = b1;
+		y2 = y1 + width;
+		if (y2 > ROWS) {
+			y2 = ROWS;
+			y1 = y2 - height;
+		}
+	}
+
+	/* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */
+
+	/* no movement? */
+	if (disp_col == x1 && disp_row == y1)
+		return;
+
+	disp_col = x1;
+	disp_row = y1;
+}
+
+/**************************************************************************************/
+
+static void newline(void)
+{
+	curs_col = 0;
+	if (curs_row + 1 < ROWS)
+		curs_row++;
+	else {
+		memmove(vty_buf, vty_buf + COLS, COLS * (ROWS - 1));
+		memset(vty_buf + (ROWS - 1) * COLS, ' ', COLS);
+	}
+}
+
+void phone_putc(const char c)
+{
+	int i;
+
+	if (input_mode != -1) {
+		input_selected_char = -1;
+		terminate_input();
+	}
+
+	curs_disabled = 1;
+	update();
+
+	blink_time = BLINK_HZ;
+
+	switch (c) {
+		case '\a':		/* ignore bell		  */
+		case '\r':		/* ignore carriage return */
+			break;
+
+		case '\n':		/* next line */
+			newline();
+			ensure_visible(curs_col, curs_row, 1, 1);
+			break;
+
+		case 9: /* tab 8 */
+			/* move to tab */
+			i = curs_col;
+			i |=  0x0008;
+			i &= ~0x0007;
+
+			if (i < COLS)
+				curs_col = i;
+			else
+				newline();
+
+			ensure_visible(curs_col, curs_row, 1, 1);
+			break;
+
+		case 8:		/* backspace */
+			if (curs_col <= 0)
+				break;
+			curs_col--;
+
+			/* make sure that we see a couple of characters before */
+			if (curs_col > 4)
+				ensure_visible(curs_col - 4, curs_row, 4, 1);
+			else
+				ensure_visible(curs_col, curs_row, 1, 1);
+
+			break;
+
+		default:		/* draw the char */
+			putchar_at_cursor(c);
+
+			/*
+			 * check for newline
+			 */
+			if (curs_col + 1 < COLS)
+				curs_col++;
+			else
+				newline();
+
+			ensure_visible(curs_col, curs_row, 1, 1);
+
+			break;
+	}
+
+	curs_disabled = 0;
+	blink_time = BLINK_HZ;
+	update();
+}
+
+/**************************************************************************************/
+
+static inline unsigned int kp_transfer(unsigned int val)
+{
+	unsigned int rx;
+	int b;
+
+	rx = 0; b = 8;
+	while (--b >= 0) {
+		KP_SPI_TXD(val & 0x80);
+		val <<= 1;
+		KP_SPI_CLK_TOGGLE();
+		KP_SPI_BIT_DELAY();
+		rx <<= 1;
+		if (KP_SPI_RXD())
+			rx |= 1;
+		KP_SPI_CLK_TOGGLE();
+		KP_SPI_BIT_DELAY();
+	}
+
+	return rx;
+}
+
+unsigned int kp_data_transfer(unsigned int val)
+{
+	KP_SPI_CLK(1);
+	KP_CS(0);
+	val = kp_transfer(val);
+	KP_CS(1);
+
+	return val;
+}
+
+unsigned int kp_get_col_mask(unsigned int row_mask)
+{
+	unsigned int val, col_mask;
+
+	val = 0x80 | (row_mask & 0x7F);
+	(void)kp_data_transfer(val);
+#if CONFIG_NETPHONE_VERSION == 1
+	col_mask = kp_data_transfer(val) & 0x0F;
+#elif CONFIG_NETPHONE_VERSION == 2
+	col_mask = ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & 0x0f;
+	/* XXX FUCK FUCK FUCK FUCK FUCK!!!! */
+	col_mask = ((col_mask & 0x08) >> 3) |	/* BKBR1 */
+		   ((col_mask & 0x04) << 1) |	/* BKBR2 */
+		    (col_mask & 0x02) |		/* BKBR3 */
+		   ((col_mask & 0x01) << 2);	/* BKBR4 */
+
+#endif
+	/* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */
+
+	return col_mask;
+}
+
+/**************************************************************************************/
+
+static const int kp_scancodes[KP_ROWS * KP_COLS] = {
+	KP_F1,	 KP_F3,	  KP_F4,  KP_F2,
+	KP_F6,	 KP_F8,	  KP_F9,  KP_F7,
+	KP_1,	 KP_3,	  KP_F11, KP_2,
+	KP_4,	 KP_6,	  KP_F12, KP_5,
+	KP_7,	 KP_9,	  KP_F13, KP_8,
+	KP_STAR, KP_HASH, KP_F14, KP_0,
+	KP_F5,	 KP_F15,  KP_F16, KP_F10,
+};
+
+static const int kp_repeats[KP_ROWS * KP_COLS] = {
+	0, 1, 0, 0,
+	0, 1, 1, 1,
+	1, 1, 0, 1,
+	1, 1, 0, 1,
+	1, 1, 0, 1,
+	1, 1, 0, 1,
+	0, 0, 0, 1,
+};
+
+static int kp_state = SCAN;
+static int kp_last_col_mask;
+static int kp_cur_row, kp_cur_col;
+static int kp_scancode;
+static int kp_stable;
+static int kp_repeat;
+static int kp_repeat_time;
+static int kp_force_time;
+static int kp_idle_time;
+
+static void kp_do_poll(void)
+{
+	unsigned int col_mask;
+	int col;
+
+	switch (kp_state) {
+		case SCAN:
+			if (kp_idle_time > 0) {
+				kp_idle_time -= PHONE_CONSOLE_POLL_HZ;
+				if (kp_idle_time <= 0)
+					scancode_action(KP_IDLE);
+			}
+
+			col_mask = kp_get_col_mask(KP_ROWS_MASK);
+			if (col_mask == KP_COLS_MASK)
+				break;	/* nothing */
+			kp_last_col_mask = col_mask;
+			kp_stable = 0;
+			kp_state = SCAN_FILTER;
+			break;
+
+		case SCAN_FILTER:
+			col_mask = kp_get_col_mask(KP_ROWS_MASK);
+			if (col_mask != kp_last_col_mask) {
+				kp_state = SCAN;
+				break;
+			}
+
+			kp_stable += PHONE_CONSOLE_POLL_HZ;
+			if (kp_stable < KP_STABLE_HZ)
+				break;
+
+			kp_cur_row = 0;
+			kp_stable = 0;
+			kp_state = SCAN_COL;
+
+			(void)kp_get_col_mask(1 << kp_cur_row);
+			break;
+
+		case SCAN_COL:
+			col_mask = kp_get_col_mask(1 << kp_cur_row);
+			if (col_mask == KP_COLS_MASK) {
+				if (++kp_cur_row >= KP_ROWS) {
+					kp_state = SCAN;
+					break;
+				}
+				kp_get_col_mask(1 << kp_cur_row);
+				break;
+			}
+			kp_last_col_mask = col_mask;
+			kp_stable = 0;
+			kp_state = SCAN_COL_FILTER;
+			break;
+
+		case SCAN_COL_FILTER:
+			col_mask = kp_get_col_mask(1 << kp_cur_row);
+			if (col_mask != kp_last_col_mask || col_mask == KP_COLS_MASK) {
+				kp_state = SCAN;
+				break;
+			}
+
+			kp_stable += PHONE_CONSOLE_POLL_HZ;
+			if (kp_stable < KP_STABLE_HZ)
+				break;
+
+			for (col = 0; col < KP_COLS; col++)
+				if ((col_mask & (1 << col)) == 0)
+					break;
+			kp_cur_col = col;
+			kp_state = PRESSED;
+			kp_scancode = kp_scancodes[kp_cur_row * KP_COLS + kp_cur_col];
+			kp_repeat = kp_repeats[kp_cur_row * KP_COLS + kp_cur_col];
+
+			if (kp_repeat)
+				kp_repeat_time = KP_REPEAT_DELAY_HZ;
+			kp_force_time = KP_FORCE_DELAY_HZ;
+
+			scancode_action(kp_scancode);
+
+			break;
+
+		case PRESSED:
+			col_mask = kp_get_col_mask(1 << kp_cur_row);
+			if (col_mask != kp_last_col_mask) {
+				kp_state = SCAN;
+				scancode_action(KP_RELEASE);
+				kp_idle_time = KP_IDLE_DELAY_HZ;
+				break;
+			}
+
+			if (kp_repeat) {
+				kp_repeat_time -= PHONE_CONSOLE_POLL_HZ;
+				if (kp_repeat_time <= 0) {
+					kp_repeat_time += KP_REPEAT_HZ;
+					scancode_action(kp_scancode);
+				}
+			}
+
+			if (kp_force_time > 0) {
+				kp_force_time -= PHONE_CONSOLE_POLL_HZ;
+				if (kp_force_time <= 0)
+					scancode_action(KP_FORCE);
+			}
+
+			break;
+	}
+}
+
+/**************************************************************************************/
+
+int drv_phone_is_idle(void)
+{
+	return kp_state == SCAN;
+}
diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds
new file mode 100755
index 0000000..9f2901c
--- /dev/null
+++ b/board/netphone/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp		: { *(.interp)		}
+  .hash         : { *(.hash)		}
+  .dynsym       : { *(.dynsym)		}
+  .dynstr       : { *(.dynstr)		}
+  .rel.text     : { *(.rel.text)	}
+  .rela.text    : { *(.rela.text) 	}
+  .rel.data     : { *(.rel.data)	}
+  .rela.data    : { *(.rela.data) 	}
+  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.rodata  : { *(.rela.rodata)	}
+  .rel.got      : { *(.rel.got)		}
+  .rela.got     : { *(.rela.got)	}
+  .rel.ctors    : { *(.rel.ctors)	}
+  .rela.ctors   : { *(.rela.ctors)	}
+  .rel.dtors    : { *(.rel.dtors)	}
+  .rela.dtors   : { *(.rela.dtors)	}
+  .rel.bss      : { *(.rel.bss)		}
+  .rela.bss     : { *(.rela.bss)	}
+  .rel.plt      : { *(.rel.plt)		}
+  .rela.plt     : { *(.rela.plt)	}
+  .init         : { *(.init)		}
+  .plt			: { *(.plt) 		}
+  .text      	:
+  {
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug
new file mode 100755
index 0000000..004e7fd
--- /dev/null
+++ b/board/netphone/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/netta/Makefile b/board/netta/Makefile
new file mode 100755
index 0000000..68e2402
--- /dev/null
+++ b/board/netta/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o dsp.o codec.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/netta/codec.c b/board/netta/codec.c
new file mode 100755
index 0000000..01ab14b
--- /dev/null
+++ b/board/netta/codec.c
@@ -0,0 +1,1484 @@
+/*
+ * CODEC
+ */
+
+#include <common.h>
+#include <post.h>
+
+#include "mpc8xx.h"
+
+/***********************************************/
+
+#define MAX_DUSLIC	4
+
+#define NUM_CHANNELS	2
+#define MAX_SLICS	(MAX_DUSLIC * NUM_CHANNELS)
+
+/***********************************************/
+
+#define SOP_READ_CH_0		0xC4  /* Read SOP Register for Channel A  */
+#define SOP_READ_CH_1		0xCC  /* Read SOP Register for Channel B  */
+#define SOP_WRITE_CH_0		0x44  /* Write SOP Register for Channel A */
+#define SOP_WRITE_CH_1		0x4C  /* Write SOP Register for Channel B */
+
+#define COP_READ_CH_0		0xC5
+#define COP_READ_CH_1		0xCD
+#define COP_WRITE_CH_0		0x45
+#define COP_WRITE_CH_1		0x4D
+
+#define POP_READ_CH_0		0xC6
+#define POP_READ_CH_1		0xCE
+#define POP_WRITE_CH_0		0x46
+#define POP_WRITE_CH_1		0x4E
+
+#define RST_CMD_DUSLIC_CHIP	0x40  /* OR 0x48 */
+#define RST_CMD_DUSLIC_CH_A	0x41
+#define RST_CMD_DUSLIC_CH_B	0x49
+
+#define PCM_RESYNC_CMD_CH_A	0x42
+#define PCM_RESYNC_CMD_CH_B	0x4A
+
+#define ACTIVE_HOOK_LEV_4	0
+#define ACTIVE_HOOK_LEV_12	1
+
+#define SLIC_P_NORMAL		0x01
+
+/************************************************/
+
+#define CODSP_WR	0x00
+#define CODSP_RD	0x80
+#define CODSP_OP	0x40
+#define CODSP_ADR(x)	(((unsigned char)(x) & 7) << 3)
+#define CODSP_M(x)	((unsigned char)(x) & 7)
+#define CODSP_CMD(x)	((unsigned char)(x) & 7)
+
+/************************************************/
+
+/* command indication ops */
+#define CODSP_M_SLEEP_PWRDN	7
+#define CODSP_M_PWRDN_HIZ	0
+#define CODSP_M_ANY_ACT		2
+#define CODSP_M_RING		5
+#define CODSP_M_ACT_MET		6
+#define CODSP_M_GND_START	4
+#define CODSP_M_RING_PAUSE	1
+
+/* single byte commands */
+#define CODSP_CMD_SOFT_RESET	CODSP_CMD(0)
+#define CODSP_CMD_RESET_CH	CODSP_CMD(1)
+#define CODSP_CMD_RESYNC	CODSP_CMD(2)
+
+/* two byte commands */
+#define CODSP_CMD_SOP		CODSP_CMD(4)
+#define CODSP_CMD_COP		CODSP_CMD(5)
+#define CODSP_CMD_POP		CODSP_CMD(6)
+
+/************************************************/
+
+/* read as 4-bytes */
+#define CODSP_INTREG_INT_CH	0x80000000
+#define CODSP_INTREG_HOOK	0x40000000
+#define CODSP_INTREG_GNDK	0x20000000
+#define CODSP_INTREG_GNDP	0x10000000
+#define CODSP_INTREG_ICON	0x08000000
+#define CODSP_INTREG_VRTLIM	0x04000000
+#define CODSP_INTREG_OTEMP	0x02000000
+#define CODSP_INTREG_SYNC_FAIL	0x01000000
+#define CODSP_INTREG_LM_THRES	0x00800000
+#define CODSP_INTREG_READY	0x00400000
+#define CODSP_INTREG_RSTAT	0x00200000
+#define CODSP_INTREG_LM_OK	0x00100000
+#define CODSP_INTREG_IO4_DU	0x00080000
+#define CODSP_INTREG_IO3_DU	0x00040000
+#define CODSP_INTREG_IO2_DU	0x00020000
+#define CODSP_INTREG_IO1_DU	0x00010000
+#define CODSP_INTREG_DTMF_OK	0x00008000
+#define CODSP_INTREG_DTMF_KEY4	0x00004000
+#define CODSP_INTREG_DTMF_KEY3	0x00002000
+#define CODSP_INTREG_DTMF_KEY2	0x00001000
+#define CODSP_INTREG_DTMF_KEY1	0x00000800
+#define CODSP_INTREG_DTMF_KEY0	0x00000400
+#define CODSP_INTREG_UTDR_OK	0x00000200
+#define CODSP_INTREG_UTDX_OK	0x00000100
+#define CODSP_INTREG_EDSP_FAIL	0x00000080
+#define CODSP_INTREG_CIS_BOF	0x00000008
+#define CODSP_INTREG_CIS_BUF	0x00000004
+#define CODSP_INTREG_CIS_REQ	0x00000002
+#define CODSP_INTREG_CIS_ACT	0x00000001
+
+/************************************************/
+
+/* ======== SOP REG ADDRESSES =======*/
+
+#define REVISION_ADDR		0x00
+#define PCMC1_ADDR		0x05
+#define XCR_ADDR		0x06
+#define INTREG1_ADDR		0x07
+#define INTREG2_ADDR		0x08
+#define INTREG3_ADDR		0x09
+#define INTREG4_ADDR		0x0A
+#define LMRES1_ADDR		0x0D
+#define MASK_ADDR		0x11
+#define IOCTL3_ADDR		0x14
+#define BCR1_ADDR		0x15
+#define BCR2_ADDR		0x16
+#define BCR3_ADDR		0x17
+#define BCR4_ADDR		0x18
+#define BCR5_ADDR		0x19
+#define DSCR_ADDR		0x1A
+#define LMCR1_ADDR		0x1C
+#define LMCR2_ADDR		0x1D
+#define LMCR3_ADDR		0x1E
+#define OFR1_ADDR		0x1F
+#define PCMR1_ADDR		0x21
+#define PCMX1_ADDR		0x25
+#define TSTR3_ADDR		0x2B
+#define TSTR4_ADDR		0x2C
+#define TSTR5_ADDR		0x2D
+
+/* ========= POP REG ADDRESSES ========*/
+
+#define CIS_DAT_ADDR		0x00
+
+#define LEC_LEN_ADDR		0x3A
+#define LEC_POWR_ADDR		0x3B
+#define LEC_DELP_ADDR		0x3C
+#define LEC_DELQ_ADDR		0x3D
+#define LEC_GAIN_XI_ADDR	0x3E
+#define LEC_GAIN_RI_ADDR	0x3F
+#define LEC_GAIN_XO_ADDR	0x40
+#define LEC_RES_1_ADDR		0x41
+#define LEC_RES_2_ADDR		0x42
+
+#define NLP_POW_LPF_ADDR	0x30
+#define NLP_POW_LPS_ADDR	0x31
+#define NLP_BN_LEV_X_ADDR	0x32
+#define NLP_BN_LEV_R_ADDR	0x33
+#define NLP_BN_INC_ADDR		0x34
+#define NLP_BN_DEC_ADDR		0x35
+#define NLP_BN_MAX_ADDR		0x36
+#define NLP_BN_ADJ_ADDR		0x37
+#define NLP_RE_MIN_ERLL_ADDR	0x38
+#define NLP_RE_EST_ERLL_ADDR	0x39
+#define NLP_SD_LEV_X_ADDR	0x3A
+#define NLP_SD_LEV_R_ADDR	0x3B
+#define NLP_SD_LEV_BN_ADDR	0x3C
+#define NLP_SD_LEV_RE_ADDR	0x3D
+#define NLP_SD_OT_DT_ADDR	0x3E
+#define NLP_ERL_LIN_LP_ADDR	0x3F
+#define NLP_ERL_LEC_LP_ADDR	0x40
+#define NLP_CT_LEV_RE_ADDR	0x41
+#define NLP_CTRL_ADDR		0x42
+
+#define UTD_CF_H_ADDR		0x4B
+#define UTD_CF_L_ADDR		0x4C
+#define UTD_BW_H_ADDR		0x4D
+#define UTD_BW_L_ADDR		0x4E
+#define UTD_NLEV_ADDR		0x4F
+#define UTD_SLEV_H_ADDR		0x50
+#define UTD_SLEV_L_ADDR		0x51
+#define UTD_DELT_ADDR		0x52
+#define UTD_RBRK_ADDR		0x53
+#define UTD_RTIME_ADDR		0x54
+#define UTD_EBRK_ADDR		0x55
+#define UTD_ETIME_ADDR		0x56
+
+#define DTMF_LEV_ADDR		0x30
+#define DTMF_TWI_ADDR		0x31
+#define DTMF_NCF_H_ADDR		0x32
+#define DTMF_NCF_L_ADDR		0x33
+#define DTMF_NBW_H_ADDR		0x34
+#define DTMF_NBW_L_ADDR		0x35
+#define DTMF_GAIN_ADDR		0x36
+#define DTMF_RES1_ADDR		0x37
+#define DTMF_RES2_ADDR		0x38
+#define DTMF_RES3_ADDR		0x39
+
+#define CIS_LEV_H_ADDR		0x43
+#define CIS_LEV_L_ADDR		0x44
+#define CIS_BRS_ADDR		0x45
+#define CIS_SEIZ_H_ADDR		0x46
+#define CIS_SEIZ_L_ADDR		0x47
+#define CIS_MARK_H_ADDR		0x48
+#define CIS_MARK_L_ADDR		0x49
+#define CIS_LEC_MODE_ADDR	0x4A
+
+/*=====================================*/
+
+#define HOOK_LEV_ACT_START_ADDR 0x89
+#define RO1_START_ADDR		0x70
+#define RO2_START_ADDR		0x95
+#define RO3_START_ADDR		0x96
+
+#define TG1_FREQ_START_ADDR	0x38
+#define TG1_GAIN_START_ADDR	0x39
+#define TG1_BANDPASS_START_ADDR 0x3B
+#define TG1_BANDPASS_END_ADDR	0x3D
+
+#define TG2_FREQ_START_ADDR	0x40
+#define TG2_GAIN_START_ADDR	0x41
+#define TG2_BANDPASS_START_ADDR 0x43
+#define TG2_BANDPASS_END_ADDR	0x45
+
+/*====================================*/
+
+#define PCM_HW_B		0x80
+#define PCM_HW_A		0x00
+#define PCM_TIME_SLOT_0		0x00   /*  Byte 0 of PCM Frame (by default is assigned to channel A ) */
+#define PCM_TIME_SLOT_1		0x01   /*  Byte 1 of PCM Frame (by default is assigned to channel B ) */
+#define PCM_TIME_SLOT_4		0x04   /*  Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
+
+#define	 RX_LEV_ADDR	0x28
+#define	 TX_LEV_ADDR	0x30
+#define	 Ik1_ADDR	0x83
+
+#define	 AR_ROW		3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
+#define	 AX_ROW		6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct	*/
+#define	 DCF_ROW	0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
+
+/* Mark the start byte of Duslic parameters that we use with configurator */
+#define	 Ik1_START_BYTE		3
+#define	 RX_LEV_START_BYTE	0
+#define	 TX_LEV_START_BYTE	0
+
+/************************************************/
+
+#define INTREG4_CIS_ACT		(1 << 0)
+
+#define BCR1_SLEEP		0x20
+#define BCR1_REVPOL		0x10
+#define BCR1_ACTR		0x08
+#define BCR1_ACTL		0x04
+#define BCR1_SLIC_MASK		0x03
+
+#define BCR2_HARD_POL_REV	0x40
+#define BCR2_TTX		0x20
+#define BCR2_TTX_12K		0x10
+#define BCR2_HIMAN		0x08
+#define BCR2_PDOT		0x01
+
+#define BCR3_PCMX_EN		(1 << 4)
+
+#define BCR5_DTMF_EN		(1 << 0)
+#define BCR5_DTMF_SRC		(1 << 1)
+#define BCR5_LEC_EN		(1 << 2)
+#define BCR5_LEC_OUT		(1 << 3)
+#define BCR5_CIS_EN		(1 << 4)
+#define BCR5_CIS_AUTO		(1 << 5)
+#define BCR5_UTDX_EN		(1 << 6)
+#define BCR5_UTDR_EN		(1 << 7)
+
+#define DSCR_TG1_EN		(1 << 0)
+#define DSCR_TG2_EN		(1 << 1)
+#define DSCR_PTG		(1 << 2)
+#define DSCR_COR8		(1 << 3)
+#define DSCR_DG_KEY(x)		(((x) & 0x0F) << 4)
+
+#define CIS_LEC_MODE_CIS_V23	(1 << 0)
+#define CIS_LEC_MODE_CIS_FRM	(1 << 1)
+#define CIS_LEC_MODE_NLP_EN	(1 << 2)
+#define CIS_LEC_MODE_UTDR_SUM	(1 << 4)
+#define CIS_LEC_MODE_UTDX_SUM	(1 << 5)
+#define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
+#define CIS_LEC_MODE_LEC_ADAPT	(1 << 7)
+
+#define TSTR4_COR_64		(1 << 5)
+
+#define TSTR3_AC_DLB_8K		(1 << 2)
+#define TSTR3_AC_DLB_32K	(1 << 3)
+#define TSTR3_AC_DLB_4M		(1 << 5)
+
+
+#define LMCR1_TEST_EN		(1 << 7)
+#define LMCR1_LM_EN		(1 << 6)
+#define LMCR1_LM_THM		(1 << 5)
+#define LMCR1_LM_ONCE		(1 << 2)
+#define LMCR1_LM_MASK		(1 << 1)
+
+#define LMCR2_LM_RECT			(1 << 5)
+#define LMCR2_LM_SEL_VDD		0x0D
+#define LMCR2_LM_SEL_IO3		0x0A
+#define LMCR2_LM_SEL_IO4		0x0B
+#define LMCR2_LM_SEL_IO4_MINUS_IO3	0x0F
+
+#define LMCR3_RTR_SEL		(1 << 6)
+
+#define LMCR3_RNG_OFFSET_NONE	0x00
+#define LMCR3_RNG_OFFSET_1	0x01
+#define LMCR3_RNG_OFFSET_2	0x02
+#define LMCR3_RNG_OFFSET_3	0x03
+
+#define TSTR5_DC_HOLD		(1 << 3)
+
+/************************************************/
+
+#define TARGET_ONHOOK_BATH_x100		4600	/* 46.0 Volt */
+#define TARGET_ONHOOK_BATL_x100		2500	/* 25.0 Volt */
+#define TARGET_V_DIVIDER_RATIO_x100	21376L	/* (R1+R2)/R2 = 213.76 */
+#define DIVIDER_RATIO_ACCURx100		(22 * 100)
+#define V_AD_x10000			10834L	/* VAD = 1.0834 */
+#define TARGET_VDDx100			330	/* VDD = 3.3 * 10 */
+#define VDD_MAX_DIFFx100		20	/* VDD Accur = 0.2*100 */
+
+#define RMS_MULTIPLIERx100		111	/* pi/(2xsqrt(2)) = 1.11*/
+#define K_INTDC_RECT_ON			4	/* When Rectifier is ON this value is necessary(2^4) */
+#define K_INTDC_RECT_OFF		2	/* 2^2 */
+#define RNG_FREQ			25
+#define SAMPLING_FREQ			(2000L)
+#define N_SAMPLES			(SAMPLING_FREQ/RNG_FREQ)     /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
+#define HOOK_THRESH_RING_START_ADDR	0x8B
+#define RING_PARAMS_START_ADDR		0x70
+
+#define V_OUT_BATH_MAX_DIFFx100		300	/* 3.0 x100 */
+#define V_OUT_BATL_MAX_DIFFx100		400	/* 4.0 x100 */
+#define MAX_V_RING_MEANx100		50
+#define TARGET_V_RING_RMSx100		2720
+#define V_RMS_RING_MAX_DIFFx100		250
+
+#define LM_OK_SRC_IRG_2			(1 << 4)
+
+/************************************************/
+
+#define PORTB		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define PORTC		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define PORTD		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
+
+#define _PORTD_SET(mask, state) \
+	do { \
+		if (state) \
+			PORTD |= mask; \
+		else \
+			PORTD &= ~mask; \
+	} while (0)
+
+#define _PORTB_SET(mask, state) \
+	do { \
+		if (state) \
+			PORTB |= mask; \
+		else \
+			PORTB &= ~mask; \
+	} while (0)
+
+#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)
+#define _PORTB_GET(mask) (!!(PORTB & mask))
+
+#define _PORTC_GET(mask) (!!(PORTC & mask))
+
+/* port B */
+#define SPI_RXD		(1 << (31 - 28))
+#define SPI_TXD		(1 << (31 - 29))
+#define SPI_CLK		(1 << (31 - 30))
+
+/* port C */
+#define COM_HOOK1	(1 << (15 - 9))
+#define COM_HOOK2	(1 << (15 - 10))
+
+#ifndef CONFIG_NETTA_SWAPHOOK
+
+#define COM_HOOK3	(1 << (15 - 11))
+#define COM_HOOK4	(1 << (15 - 12))
+
+#else
+
+#define COM_HOOK3	(1 << (15 - 12))
+#define COM_HOOK4	(1 << (15 - 11))
+
+#endif
+
+/* port D */
+#define SPIENC1		(1 << (15 - 9))
+#define SPIENC2		(1 << (15 - 10))
+#define SPIENC3		(1 << (15 - 11))
+#define SPIENC4		(1 << (15 - 14))
+
+#define SPI_DELAY() udelay(1)
+
+static inline unsigned int __SPI_Transfer(unsigned int tx)
+{
+	unsigned int rx;
+	int b;
+
+	rx = 0; b = 8;
+	while (--b >= 0) {
+		_PORTB_SET(SPI_TXD, tx & 0x80);
+		tx <<= 1;
+		_PORTB_TGL(SPI_CLK);
+		SPI_DELAY();
+		rx <<= 1;
+		rx |= _PORTB_GET(SPI_RXD);
+		_PORTB_TGL(SPI_CLK);
+		SPI_DELAY();
+	}
+
+	return rx;
+}
+
+static const char *codsp_dtmf_map = "D1234567890*#ABC";
+
+static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };
+static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };
+
+static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen)
+{
+	unsigned int rx;
+	int i;
+
+	/* just some sanity checks */
+	if (cmd == 0 || cmdlen < 0)
+		return -1;
+
+	_PORTD_SET(spienc_mask_tab[duslic_id], 0);
+
+	/* first 2 bytes are without response */
+	i = 2;
+	while (i-- > 0 && cmdlen-- > 0)
+		__SPI_Transfer(*cmd++);
+
+	while (cmdlen-- > 0) {
+		rx = __SPI_Transfer(*cmd++);
+		if (res != 0 && reslen-- > 0)
+			*res++ = (unsigned char)rx;
+	}
+	if (res != 0) {
+		while (reslen-- > 0)
+			*res++ = __SPI_Transfer(0xFF);
+	}
+
+	_PORTD_SET(spienc_mask_tab[duslic_id], 1);
+
+	return 0;
+}
+
+/****************************************************************************/
+
+void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)
+{
+	unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m);
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+void codsp_reset_chip(int duslic_id)
+{
+	static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET;
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+void codsp_reset_channel(int duslic_id, int channel)
+{
+	unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH;
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+void codsp_resync_channel(int duslic_id, int channel)
+{
+	unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC;
+	codsp_send(duslic_id, &cmd, 1, 0, 0);
+}
+
+/****************************************************************************/
+
+void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+	cmd[2] = val;
+
+	codsp_send(duslic_id, cmd, 3, 0, 0);
+}
+
+void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
+{
+	unsigned char cmd[4];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char)(val >> 8);
+	cmd[3] = (unsigned char)val;
+
+	codsp_send(duslic_id, cmd, 4, 0, 0);
+}
+
+void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
+{
+	unsigned char cmd[5];
+
+	cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char)(val >> 24);
+	cmd[3] = (unsigned char)(val >> 16);
+	cmd[4] = (unsigned char)(val >> 8);
+	cmd[5] = (unsigned char)val;
+
+	codsp_send(duslic_id, cmd, 6, 0, 0);
+}
+
+unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno)
+{
+	unsigned char cmd[3];
+	unsigned char res[2];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+
+	codsp_send(duslic_id, cmd, 2, res, 2);
+
+	return res[1];
+}
+
+unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[3];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+
+	codsp_send(duslic_id, cmd, 2, res, 3);
+
+	return ((unsigned short)res[1] << 8) | res[2];
+}
+
+unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[5];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
+	cmd[1] = regno;
+
+	codsp_send(duslic_id, cmd, 2, res, 5);
+
+	return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4];
+}
+
+/****************************************************************************/
+
+void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block)
+{
+	unsigned char cmd[10];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	memcpy(cmd + 2, block, 8);
+	codsp_send(duslic_id, cmd, 10, 0, 0);
+}
+
+void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	cmd[2] = val;
+	codsp_send(duslic_id, cmd, 3, 0, 0);
+}
+
+void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	cmd[2] = (unsigned char)(val >> 8);
+	cmd[3] = (unsigned char)val;
+
+	codsp_send(duslic_id, cmd, 4, 0, 0);
+}
+
+void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block)
+{
+	unsigned char cmd[2];
+	unsigned char res[9];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	codsp_send(duslic_id, cmd, 2, res, 9);
+	memcpy(block, res + 1, 8);
+}
+
+unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr)
+{
+	unsigned char cmd[2];
+	unsigned char res[2];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+	codsp_send(duslic_id, cmd, 2, res, 2);
+	return res[1];
+}
+
+unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr)
+{
+	unsigned char cmd[2];
+	unsigned char res[3];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
+	cmd[1] = addr;
+
+	codsp_send(duslic_id, cmd, 2, res, 3);
+
+	return ((unsigned short)res[1] << 8) | res[2];
+}
+
+/****************************************************************************/
+
+#define MAX_POP_BLOCK	50
+
+void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr,
+			    const unsigned char *block, int len)
+{
+	unsigned char cmd[2 + MAX_POP_BLOCK];
+
+	if (len > MAX_POP_BLOCK)	/* truncate */
+		len = MAX_POP_BLOCK;
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = addr;
+	memcpy (cmd + 2, block, len);
+	codsp_send (duslic_id, cmd, 2 + len, 0, 0);
+}
+
+void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno,
+			   unsigned char val)
+{
+	unsigned char cmd[3];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+	cmd[2] = val;
+
+	codsp_send (duslic_id, cmd, 3, 0, 0);
+}
+
+void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno,
+			    unsigned short val)
+{
+	unsigned char cmd[4];
+
+	cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char) (val >> 8);
+	cmd[3] = (unsigned char) val;
+
+	codsp_send (duslic_id, cmd, 4, 0, 0);
+}
+
+void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno,
+			  unsigned int val)
+{
+	unsigned char cmd[5];
+
+	cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+	cmd[2] = (unsigned char) (val >> 24);
+	cmd[3] = (unsigned char) (val >> 16);
+	cmd[4] = (unsigned char) (val >> 8);
+	cmd[5] = (unsigned char) val;
+
+	codsp_send (duslic_id, cmd, 6, 0, 0);
+}
+
+unsigned char codsp_read_pop_char (int duslic_id, int channel,
+				   unsigned char regno)
+{
+	unsigned char cmd[3];
+	unsigned char res[2];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+
+	codsp_send (duslic_id, cmd, 2, res, 2);
+
+	return res[1];
+}
+
+unsigned short codsp_read_pop_short (int duslic_id, int channel,
+				     unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[3];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+
+	codsp_send (duslic_id, cmd, 2, res, 3);
+
+	return ((unsigned short) res[1] << 8) | res[2];
+}
+
+unsigned int codsp_read_pop_int (int duslic_id, int channel,
+				 unsigned char regno)
+{
+	unsigned char cmd[2];
+	unsigned char res[5];
+
+	cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
+	cmd[1] = regno;
+
+	codsp_send (duslic_id, cmd, 2, res, 5);
+
+	return (((unsigned int) res[1] << 24) |
+		((unsigned int) res[2] << 16) |
+		((unsigned int) res[3] <<  8) |
+		res[4] );
+}
+/****************************************************************************/
+
+struct _coeffs {
+	unsigned char addr;
+	unsigned char values[8];
+};
+
+struct _coeffs ac_coeffs[11] = {
+	{ 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
+	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
+	{ 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter	      */
+	{ 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter	      */
+	{ 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter	      */
+	{ 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter	      */
+	{ 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter	      */
+	{ 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter	      */
+	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
+	{ 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
+	{ 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} }  /* 0x10 TH-Filter part 3 */
+};
+
+struct _coeffs ac_coeffs_0dB[11] = {
+	{ 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} },
+	{ 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} },
+	{ 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} },
+	{ 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} },
+	{ 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} },
+	{ 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} },
+	{ 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} },
+	{ 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} },
+	{ 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} },
+	{ 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} },
+	{ 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} }
+};
+
+struct _coeffs dc_coeffs[9] = {
+	{ 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter     */
+	{ 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing	      */
+	{ 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters	      */
+	{ 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels      */
+	{ 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator   */
+	{ 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX	      */
+	{ 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1	      */
+	{ 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2	      */
+	{ 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} }  /* 0x98 Reserved	      */
+};
+
+void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)
+{
+	int i;
+
+	for (i = 0; i < tab_size; i++)
+	codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
+}
+
+#define SS_OPEN_CIRCUIT			0
+#define SS_RING_PAUSE			1
+#define SS_ACTIVE			2
+#define SS_ACTIVE_HIGH			3
+#define SS_ACTIVE_RING			4
+#define SS_RINGING			5
+#define SS_ACTIVE_WITH_METERING		6
+#define SS_ONHOOKTRNSM			7
+#define SS_STANDBY			8
+#define SS_MAX				8
+
+static void codsp_set_slic(int duslic_id, int channel, int state)
+{
+	unsigned char v;
+
+	v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR);
+
+	switch (state) {
+
+		case SS_ACTIVE:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL);
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
+			break;
+
+		case SS_ACTIVE_HIGH:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL));
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
+			break;
+
+		case SS_ACTIVE_RING:
+		case SS_ONHOOKTRNSM:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
+			break;
+
+		case SS_STANDBY:
+			codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR));
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN);
+			break;
+
+		case SS_OPEN_CIRCUIT:
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ);
+			break;
+
+		case SS_RINGING:
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING);
+			break;
+
+		case SS_RING_PAUSE:
+			codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE);
+			break;
+	}
+}
+
+const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 };
+const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 };
+
+void retrieve_slic_state(int slic_id)
+{
+	int duslic_id = slic_id >> 1;
+	int channel = slic_id & 1;
+
+	/* Retrieve the state of the SLICs */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
+
+	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
+	udelay(10000);
+
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
+	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);
+
+	/* Program Default Hook Ring thresholds */
+	codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values);
+
+	/* Now program Hook Threshold while Ring and ac RingTrip to max values */
+	codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values);
+
+	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
+
+	udelay(40000);
+}
+
+int wait_level_metering_finish(int duslic_id, int channel)
+{
+	int cnt;
+
+	for (cnt = 0; cnt < 1000 &&
+		(codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { }
+
+	return cnt != 1000;
+}
+
+int measure_on_hook_voltages(int slic_id, long *vdd,
+		long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v)
+{
+	short LM_Result, Offset_Compensation;	/* Signed 16 bit */
+	long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
+	unsigned char err_mask = 0;
+	int duslic_id = slic_id >> 1;
+	int channel = slic_id & 1;
+	int i;
+
+	/* measure VDD */
+	/* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */
+	codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD);
+
+	/* Activate Test Mode ==> To Enable DC Hold !!! */
+	/* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */
+	/* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	udelay(40000);
+
+	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD);
+
+	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
+	udelay(10000);
+
+	/* Now Read the LM Result Registers */
+	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+	VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ;	/* VDDx100 */
+
+	*vdd = VDD;
+
+	VDD_diff = VDD - TARGET_VDDx100;
+
+	if (VDD_diff < 0)
+		VDD_diff = -VDD_diff;
+
+	if (VDD_diff > VDD_MAX_DIFFx100)
+		err_mask |= 1;
+
+	Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100;
+
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */
+
+	udelay(40000);
+
+	codsp_write_sop_char(duslic_id, channel,
+		LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	udelay(40000);
+
+	/* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
+
+	/* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
+	udelay(10000);
+
+	/* Now Read the LM Result Registers */
+	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ;  /* Vin x 10000*/
+
+	V_out = (V_in * Divider_Ratio) / 10000L ;	/* Vout x100 */
+
+	*v_oh_H = V_out;
+
+	Vout_diff = V_out - TARGET_ONHOOK_BATH_x100;
+
+	if (Vout_diff < 0)
+		Vout_diff = -Vout_diff;
+
+	if (Vout_diff > V_OUT_BATH_MAX_DIFFx100)
+		err_mask |= 2;
+
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */
+
+	udelay(40000);
+
+	/* Now Read the LM Result Registers */
+	LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+
+	V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ;  /* Vin x 10000*/
+
+	V_out = (V_in * Divider_Ratio) / 10000L ;	/* Vout x100 */
+
+	*v_oh_L = V_out;
+
+	Vout_diff = V_out - TARGET_ONHOOK_BATL_x100;
+
+	if (Vout_diff < 0)
+		Vout_diff = -Vout_diff;
+
+	if (Vout_diff > V_OUT_BATL_MAX_DIFFx100)
+		err_mask |= 4;
+
+	/* perform ring tests */
+
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	udelay(40000);
+
+	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE);
+
+	/* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/
+	codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz);
+
+	/* By Default RO1 is selected when ringing RNG-OFFSET = 00 */
+
+	/* Now program Hook Threshold while Ring and ac RingTrip to max values */
+	for(i = 0; i < sizeof(Max_HookRingTh); i++)
+		codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]);
+
+	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
+
+	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
+
+	/* select source for the levelmeter to be IO4-IO3 */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
+
+	udelay(40000);
+
+	/* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */
+	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF);
+
+	udelay(10000);
+
+	/* Enable LevelMeter to Integrate only once (Rectifier Disabled) */
+	codsp_write_sop_char(duslic_id, channel,
+			LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+	udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
+
+	if (wait_level_metering_finish(duslic_id, channel)) {
+
+		udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */
+
+		/* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */
+		Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+		Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES);
+
+		/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+		codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
+
+		/* Now programm Integrator Offset Registers !!! */
+		codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
+
+		codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */
+
+		udelay(40000);
+
+		/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
+		codsp_write_sop_char(duslic_id, channel,
+				LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+		udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
+
+		/* Poll the LM_OK bit to see when Integration Result is Ready */
+		if (wait_level_metering_finish(duslic_id, channel)) {
+
+			udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */
+
+			/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
+			/*				    ==>After that Result Regs will be updated every 500us !!!) */
+			LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+			V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ;  /* Vin x 10000*/
+
+			V_out = (V_in * Divider_Ratio) / 10000L ;	/* Vout x100 */
+
+			if (V_out < 0)
+				V_out= -V_out;
+
+			if (V_out > MAX_V_RING_MEANx100)
+				err_mask |= 8;
+
+			*ring_mean_v = V_out;
+		} else {
+			err_mask |= 8;
+			*ring_mean_v = 0;
+		}
+	} else {
+		err_mask |= 8;
+		*ring_mean_v = 0;
+	}
+
+	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
+		LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
+	codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
+
+	codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
+
+	/* Now Enable Rectifier */
+	/* select source for the levelmeter to be IO4-IO3 */
+	codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR,
+		LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT);
+
+	/* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */
+	codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON);
+
+	udelay(40000);
+
+	/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
+			LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+	udelay(40000);
+
+	/* Poll the LM_OK bit to see when Integration Result is Ready */
+	if (wait_level_metering_finish(duslic_id, channel)) {
+
+		udelay(10000);
+
+		/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
+		/*				    ==>After that Result Regs will be updated every 500us !!!) */
+		Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+		Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);
+
+		/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+		codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
+
+		/* Now programm Integrator Offset Registers !!! */
+		codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
+
+		/* Be sure that a Ring is generated !!!! */
+		codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */
+
+		udelay(40000);
+
+		/* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
+		codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
+				LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
+
+		udelay(40000);
+
+		/* Poll the LM_OK bit to see when Integration Result is Ready */
+		if (wait_level_metering_finish(duslic_id, channel)) {
+
+			udelay(10000);
+
+			/* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
+			/*				    ==>After that Result Regs will be updated every 500us !!!) */
+			LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
+			V_in = (-1) *  ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ;  /* Vin x 10000*/
+
+			V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ;	/* Vout_RMS x100 */
+			if (V_out < 0)
+				V_out = -V_out;
+
+			Vout_diff = (V_out - TARGET_V_RING_RMSx100);
+
+			if (Vout_diff < 0)
+				Vout_diff = -Vout_diff;
+
+			if (Vout_diff > V_RMS_RING_MAX_DIFFx100)
+				err_mask |= 16;
+
+			*ring_rms_v = V_out;
+		} else {
+			err_mask |= 16;
+			*ring_rms_v = 0;
+		}
+	} else {
+		err_mask |= 16;
+		*ring_rms_v = 0;
+	}
+	/* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
+	codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
+
+	retrieve_slic_state(slic_id);
+
+	return(err_mask);
+}
+
+int test_dtmf(int slic_id)
+{
+	unsigned char code;
+	unsigned char b;
+	unsigned int intreg;
+	int duslic_id = slic_id >> 1;
+	int channel = slic_id & 1;
+
+	for (code = 0; code < 16; code++) {
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+			(b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
+		udelay(80000);
+
+		intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);
+		if ((intreg & CODSP_INTREG_INT_CH) == 0)
+			break;
+
+		if ((intreg & CODSP_INTREG_DTMF_OK) == 0 ||
+				codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])
+			break;
+
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+				b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+
+		udelay(80000);
+
+		intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */
+	}
+
+	if (code != 16) {
+		b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
+		codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
+				b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
+		return(1);
+	}
+
+	return(0);
+}
+
+void data_up_persist_time(int duslic_id, int channel, int time_ms)
+{
+	unsigned char b;
+
+	b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR);
+	b = (b & 0x0F) | ((time_ms & 0x0F) << 4);
+	codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b);
+}
+
+static void program_dtmf_params(int duslic_id, int channel)
+{
+	unsigned char b;
+
+	codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10);
+	codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02);
+	codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB);
+	codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91);
+	codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00);
+	codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00);
+	codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00);
+
+	b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR);
+	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN);
+}
+
+static void codsp_channel_full_reset(int duslic_id, int channel)
+{
+
+	program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs));
+	program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs));
+
+	/* program basic configuration registers */
+	codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01);
+	codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41);
+	codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43);
+	codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00);
+	codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00);
+
+	codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04);		/* PG */
+
+	program_dtmf_params(duslic_id, channel);
+
+	codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);	/* RingTRip_SEL */
+
+	data_up_persist_time(duslic_id, channel, 4);
+
+	codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF);     /* All interrupts masked */
+
+	codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
+}
+
+static int codsp_chip_full_reset(int duslic_id)
+{
+	int i, cnt;
+	int intreg[NUM_CHANNELS];
+	unsigned char pcm_resync;
+	unsigned char revision;
+
+	codsp_reset_chip(duslic_id);
+
+	udelay(2000);
+
+	for (i = 0; i < NUM_CHANNELS; i++)
+		intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR);
+
+	udelay(1500);
+
+	if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) {
+		printf("_HOOK(%d) stayed low\n", duslic_id);
+		return -1;
+	}
+
+	for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) {
+		if (intreg[i] & CODSP_INTREG_SYNC_FAIL)
+			pcm_resync |= 1 << i;
+	}
+
+	for (cnt = 0; cnt < 5 && pcm_resync; cnt++) {
+		for (i = 0; i < NUM_CHANNELS; i++)
+			codsp_resync_channel(duslic_id, i);
+
+		udelay(2000);
+
+		pcm_resync = 0;
+
+		for (i = 0; i < NUM_CHANNELS; i++) {
+			if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL)
+				pcm_resync |= 1 << i;
+		}
+	}
+
+	if (cnt == 5) {
+		printf("PCM_Resync(%u) not completed\n", duslic_id);
+		return -2;
+	}
+
+	revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR);
+	printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F);
+
+	codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80);	/* EDSP_EN */
+
+	for (i = 0; i < NUM_CHANNELS; i++) {
+		codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01);
+		codsp_channel_full_reset(duslic_id, i);
+	}
+
+	return 0;
+}
+
+int slic_self_test(int duslic_mask)
+{
+	int slic;
+	int i;
+	int r;
+	long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v;
+	const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" };
+	int error = 0;
+
+	for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */
+		if (duslic_mask & (1 << (slic >> 1))) {
+			r = measure_on_hook_voltages(slic, &vdd,
+				&v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
+
+			printf("SLIC %u measured voltages (x100):\n\t"
+				    "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
+				    slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
+
+			if (r != 0)
+				error |= 1 << slic;
+
+			for (i = 0; i < 5; i++)
+				if (r & (1 << i))
+					printf("\t%s out of range\n", err_txt[i]);
+		}
+	}
+
+	for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */
+		if (duslic_mask & (1 << (slic >> 1))) {
+			printf("SLIC %u VOICE PATH...CHECKING", slic);
+			printf("\rSLIC %u VOICE PATH...%s\n", slic,
+				(r = test_dtmf(slic)) != 0 ? "FAILED  " : "PASSED  ");
+
+			if (r != 0)
+				error |= 1 << slic;
+		}
+	}
+
+	return(error);
+}
+
+#if defined(CONFIG_NETTA_ISDN)
+
+#define SPIENS1		(1 << (31 - 15))
+#define SPIENS2		(1 << (31 - 19))
+
+static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 };
+int s_initialized = 0;
+
+static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value)
+{
+	unsigned int rx, v;
+
+	_PORTB_SET(spiens_mask_tab[s_id], 0);
+
+	rx = __SPI_Transfer(address);
+
+	switch (address & 0xF0) {
+	case 0x60:	/* write byte register */
+	case 0x70:
+		rx = __SPI_Transfer(value);
+		break;
+
+	case 0xE0:	/* read R6 register */
+		v = __SPI_Transfer(0);
+
+		rx = (rx << 8) | v;
+
+		break;
+
+	case 0xF0:	/* read byte register */
+		rx = __SPI_Transfer(0);
+
+		break;
+	}
+
+	_PORTB_SET(spiens_mask_tab[s_id], 1);
+
+	return rx;
+}
+
+static void s_write_BR(int s_id, unsigned int regno, unsigned int val)
+{
+	unsigned int address;
+	unsigned int v;
+
+	address = 0x70 | (regno & 15);
+	val &= 0xff;
+
+	v = s_transfer_internal(s_id, address, val);
+}
+
+static void s_write_OR(int s_id, unsigned int regno, unsigned int val)
+{
+	unsigned int address;
+	unsigned int v;
+
+	address = 0x70 | (regno & 15);
+	val &= 0xff;
+
+	v = s_transfer_internal(s_id, address, val);
+}
+
+static void s_write_NR(int s_id, unsigned int regno, unsigned int val)
+{
+	unsigned int address;
+	unsigned int v;
+
+	address = (regno & 7) << 4;
+	val &= 0xf;
+
+	v = s_transfer_internal(s_id, address | val, 0x00);
+}
+
+#define BR7_IFR			0x08	/* IDL2 free run */
+#define BR7_ICSLSB		0x04	/* IDL2 clock speed LSB */
+
+#define BR15_OVRL_REG_EN	0x80
+#define OR7_D3VR		0x80	/* disable 3V regulator */
+
+#define OR8_TEME		0x10	/* TE mode enable */
+#define OR8_MME			0x08	/* master mode enable */
+
+void s_initialize(void)
+{
+	int s_id;
+
+	for (s_id = 0; s_id < 2; s_id++) {
+		s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB);
+		s_write_BR(s_id, 15, BR15_OVRL_REG_EN);
+		s_write_OR(s_id, 8, OR8_TEME | OR8_MME);
+		s_write_OR(s_id, 7, OR7_D3VR);
+		s_write_OR(s_id, 6, 0);
+		s_write_BR(s_id, 15, 0);
+		s_write_NR(s_id, 3, 0);
+	}
+}
+
+#endif
+
+int board_post_codec(int flags)
+{
+	int j;
+	int r;
+	int duslic_mask;
+
+	printf("board_post_dsp\n");
+
+#if defined(CONFIG_NETTA_ISDN)
+	if (s_initialized == 0) {
+		s_initialize();
+		s_initialized = 1;
+
+		printf("s_initialized\n");
+
+		udelay(20000);
+	}
+#endif
+	duslic_mask = 0;
+
+	for (j = 0; j < MAX_DUSLIC; j++) {
+		if (codsp_chip_full_reset(j) < 0)
+			printf("Error initializing DuSLIC#%d\n", j);
+		else
+			duslic_mask |= 1 << j;
+	}
+
+	if (duslic_mask != 0) {
+		printf("Testing SLICs...\n");
+
+		r = slic_self_test(duslic_mask);
+		for (j = 0; j < MAX_SLICS; j++) {
+			if (duslic_mask & (1 << (j >> 1)))
+				printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK");
+		}
+	}
+	printf("DuSLIC self test finished\n");
+
+	return 0;	/* return -1 on error */
+}
diff --git a/board/netta/config.mk b/board/netta/config.mk
new file mode 100755
index 0000000..8497ebc
--- /dev/null
+++ b/board/netta/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# netVia Boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/netta/dsp.c b/board/netta/dsp.c
new file mode 100755
index 0000000..66e0b85
--- /dev/null
+++ b/board/netta/dsp.c
@@ -0,0 +1,1208 @@
+/*
+ * Intracom TI6711/TI6412 DSP
+ */
+
+#include <common.h>
+#include <post.h>
+
+#include "mpc8xx.h"
+
+struct ram_range {
+	u32 start;
+	u32 size;
+};
+
+#if defined(CONFIG_NETTA_6412)
+
+static const struct ram_range int_ram[] = {
+	{ 0x00000000U, 0x00040000U },
+};
+
+static const struct ram_range ext_ram[] = {
+	{ 0x80000000U, 0x00100000U },
+};
+
+static const struct ram_range ranges[] = {
+	{ 0x00000000U, 0x00040000U },
+	{ 0x80000000U, 0x00100000U },
+};
+
+static inline u16 bit_invert(u16 d)
+{
+	register u8 i;
+	register u16 r;
+	register u16 bit;
+
+	r = 0;
+	for (i = 0; i < 16; i++) {
+		bit = d & (1 << i);
+		if (bit != 0)
+			r |= 1 << (15 - i);
+	}
+	return r;
+}
+
+#else
+
+static const struct ram_range int_ram[] = {
+	{ 0x00000000U, 0x00010000U },
+};
+
+static const struct ram_range ext_ram[] = {
+	{ 0x80000000U, 0x00100000U },
+};
+
+static const struct ram_range ranges[] = {
+	{ 0x00000000U, 0x00010000U },
+	{ 0x80000000U, 0x00100000U },
+};
+
+#endif
+
+/*******************************************************************************************************/
+
+static inline int addr_in_int_ram(u32 addr)
+{
+	int i;
+
+	for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++)
+		if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size)
+			return 1;
+
+	return 0;
+}
+
+static inline int addr_in_ext_ram(u32 addr)
+{
+	int i;
+
+	for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++)
+		if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size)
+			return 1;
+
+	return 0;
+}
+
+/*******************************************************************************************************/
+
+#define DSP_HPIC	0x0
+#define DSP_HPIA	0x4
+#define DSP_HPID1	0x8
+#define DSP_HPID2	0xC
+
+static u32 dummy_delay;
+static volatile u32 *ti6711_delay = &dummy_delay;
+
+static inline void dsp_go_slow(void)
+{
+	volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
+#if defined(CONFIG_NETTA_6412)
+	memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;
+#else
+	memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;
+#endif
+	memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;
+
+	ti6711_delay = (u32 *)DUMMY_BASE;
+}
+
+static inline void dsp_go_fast(void)
+{
+	volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
+#if defined(CONFIG_NETTA_6412)
+	memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
+#else
+	memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;
+#endif
+	memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
+
+	ti6711_delay = &dummy_delay;
+}
+
+/*******************************************************************************************************/
+
+static inline void dsp_delay(void)
+{
+	/* perform ti6711_delay chip select read to have a small delay */
+	(void) *(volatile u32 *)ti6711_delay;
+}
+
+static inline u16 dsp_read_hpic(void)
+{
+#if defined(CONFIG_NETTA_6412)
+	return bit_invert(*((volatile u16 *)DSP_BASE));
+#else
+	return *((volatile u16 *)DSP_BASE);
+#endif
+}
+
+static inline void dsp_write_hpic(u16 val)
+{
+#if defined(CONFIG_NETTA_6412)
+	*((volatile u16 *)DSP_BASE) = bit_invert(val);
+#else
+	*((volatile u16 *)DSP_BASE) = val;
+#endif
+}
+
+static inline void dsp_reset(void)
+{
+#if defined(CONFIG_NETTA_6412)
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
+	udelay(500);
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 15));
+	udelay(500);
+#else
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
+	udelay(250);
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));
+	udelay(250);
+#endif
+}
+
+static inline u32 dsp_read_hpic_word(u32 addr)
+{
+	u32 val;
+	volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+
+	val = ((u32) bit_invert(p[0]) << 16);
+	/* dsp_delay(); */
+
+	val |= bit_invert(p[1]);
+	/* dsp_delay(); */
+#else
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+
+	val = ((u32) p[0] << 16);
+	dsp_delay();
+
+	val |= p[1];
+	dsp_delay();
+#endif
+	return val;
+}
+
+static inline u16 dsp_read_hpic_hi_hword(u32 addr)
+{
+#if defined(CONFIG_NETTA_6412)
+	return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr));
+#else
+	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+#endif
+}
+
+static inline u16 dsp_read_hpic_lo_hword(u32 addr)
+{
+#if defined(CONFIG_NETTA_6412)
+	return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2));
+#else
+	return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);
+#endif
+}
+
+static inline void dsp_wait_hrdy(void)
+{
+	int i;
+
+	i = 0;
+#if defined(CONFIG_NETTA_6412)
+	while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
+#else
+	while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
+#endif
+		dsp_delay();
+		i++;
+	}
+}
+
+static inline void dsp_write_hpic_word(u32 addr, u32 val)
+{
+	volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+	p[0] = bit_invert((u16)(val >> 16));
+	/* dsp_delay(); */
+
+	p[1] = bit_invert((u16)val);
+	/* dsp_delay(); */
+#else
+	p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
+	p[0] = (u16)(val >> 16);
+	dsp_delay();
+
+	p[1] = (u16)val;
+	dsp_delay();
+#endif
+}
+
+static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h)
+{
+#if defined(CONFIG_NETTA_6412)
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h);
+#else
+
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;
+#endif
+}
+
+static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
+{
+#if defined(CONFIG_NETTA_6412)
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l);
+#else
+	*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;
+#endif
+}
+
+/********************************************************************/
+
+static inline void c62_write_word(u32 addr, u32 val)
+{
+	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+
+	dsp_wait_hrdy();
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+
+	/* dsp_wait_hrdy();
+	dsp_delay(); */
+#endif
+	dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+}
+
+static u32 c62_read_word(u32 addr)
+{
+	u32 val;
+
+	dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+
+	/* FETCH */
+#if defined(CONFIG_NETTA_6412)
+	dsp_write_hpic_word(DSP_HPIC, 0x00100010);
+#else
+	dsp_write_hpic(0x10);
+	dsp_delay();
+#endif
+	dsp_wait_hrdy();
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16;
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+
+	/* dsp_wait_hrdy();
+	dsp_delay(); */
+#endif
+	val |= dsp_read_hpic_lo_hword(DSP_HPID2);
+#if !defined(CONFIG_NETTA_6412)
+	dsp_delay();
+#endif
+	return val;
+}
+
+static inline void c62_read(u32 addr, u32 *buffer, int numdata)
+{
+	int i;
+
+	if (numdata <= 0)
+		return;
+
+	for (i = 0; i < numdata; i++) {
+		*buffer++ = c62_read_word(addr);
+		addr += 4;
+	}
+}
+
+static inline u32 c62_checksum(u32 addr, int numdata)
+{
+	int i;
+	u32 chksum;
+
+	chksum = 0;
+	for (i = 0; i < numdata; i++) {
+		chksum += c62_read_word(addr);
+		addr += 4;
+	}
+
+	return chksum;
+}
+
+static inline void c62_write(u32 addr, const u32 *buffer, int numdata)
+{
+	int i;
+
+	if (numdata <= 0)
+		return;
+
+	for (i = 0; i < numdata; i++) {
+		c62_write_word(addr, *buffer++);
+		addr += 4;
+	}
+}
+
+static inline int c62_write_word_validated(u32 addr, u32 val)
+{
+	c62_write_word(addr, val);
+	return c62_read_word(addr) == val ? 0 : -1;
+}
+
+static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata)
+{
+	int i, r;
+
+	if (numdata <= 0)
+		return 0;
+
+	for (i = 0; i < numdata; i++) {
+		r = c62_write_word_validated(addr, *buffer++);
+		if (r < 0)
+			return r;
+		addr += 4;
+	}
+	return 0;
+}
+
+#if defined(CONFIG_NETTA_6412)
+
+#define DRAM_REGS_BASE	0x1800000
+
+#define GBLCTL	DRAM_REGS_BASE
+#define CECTL1	(DRAM_REGS_BASE + 0x4)
+#define CECTL0	(DRAM_REGS_BASE + 0x8)
+#define CECTL2	(DRAM_REGS_BASE + 0x10)
+#define CECTL3	(DRAM_REGS_BASE + 0x14)
+#define SDCTL	(DRAM_REGS_BASE + 0x18)
+#define SDTIM	(DRAM_REGS_BASE + 0x1C)
+#define SDEXT	(DRAM_REGS_BASE + 0x20)
+#define SESEC1	(DRAM_REGS_BASE + 0x44)
+#define SESEC0	(DRAM_REGS_BASE + 0x48)
+#define SESEC2	(DRAM_REGS_BASE + 0x50)
+#define SESEC3	(DRAM_REGS_BASE + 0x54)
+
+#define MAR128	0x1848200
+#define MAR129	0x1848204
+
+void dsp_dram_initialize(void)
+{
+	c62_write_word(GBLCTL, 0x120E4);
+	c62_write_word(CECTL1, 0x18);
+	c62_write_word(CECTL0, 0xD0);
+	c62_write_word(CECTL2, 0x18);
+	c62_write_word(CECTL3, 0x18);
+	c62_write_word(SDCTL, 0x47115000);
+	c62_write_word(SDTIM, 1536);
+	c62_write_word(SDEXT, 0x534A9);
+#if 0
+	c62_write_word(SESEC1, 0);
+	c62_write_word(SESEC0, 0);
+	c62_write_word(SESEC2, 0);
+	c62_write_word(SESEC3, 0);
+#endif
+	c62_write_word(MAR128, 1);
+	c62_write_word(MAR129, 0);
+}
+
+#endif
+
+static inline void dsp_init_hpic(void)
+{
+	int i;
+	volatile u16 *p;
+#if defined(CONFIG_NETTA_6412)
+	dsp_go_fast();
+#else
+	dsp_go_slow();
+#endif
+	i = 0;
+#if defined(CONFIG_NETTA_6412)
+	while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
+#else
+	while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
+#endif
+		dsp_delay();
+		i++;
+	}
+
+	if (i == 1000)
+		printf("HRDY stuck\n");
+
+	dsp_delay();
+
+	/* write control register */
+	p = (volatile u16 *)DSP_BASE;
+	p[0] = 0x0000;
+	dsp_delay();
+	p[1] = 0x0000;
+	dsp_delay();
+
+#if !defined(CONFIG_NETTA_6412)
+	dsp_go_fast();
+#endif
+}
+
+/***********************************************************************************************************/
+
+#if !defined(CONFIG_NETTA_6412)
+
+static const u8 bootstrap_rbin[5084] = {
+	0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00,
+	0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a,
+	0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x03, 0x62,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x10, 0x5a,
+	0x00, 0x19, 0x2e, 0x28, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64,
+	0x02, 0x00, 0x00, 0xaa, 0x02, 0x10, 0xac, 0xe2, 0x00, 0x00, 0x20, 0x00,
+	0x00, 0x00, 0x02, 0x64, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x9f, 0x7a,
+	0x30, 0x00, 0x08, 0x10, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
+	0x00, 0x10, 0x02, 0xe4, 0x00, 0x00, 0x60, 0x00, 0x00, 0x02, 0xd6, 0xc8,
+	0x00, 0x10, 0x02, 0xf4, 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x03, 0x1a, 0xf7, 0xca, 0x03, 0x10, 0x02, 0xf6, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
+	0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x02, 0x97, 0xcf, 0x5a,
+	0x02, 0x90, 0x02, 0xf6, 0x02, 0x90, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x02, 0x96, 0x10, 0xca, 0x02, 0x90, 0x02, 0xf6, 0x00, 0x0c, 0x03, 0x62,
+	0x00, 0x00, 0x80, 0x00, 0x02, 0x90, 0x10, 0x5a, 0x00, 0x00, 0x04, 0x28,
+	0x00, 0x00, 0xc6, 0x69, 0x02, 0x16, 0x4c, 0xa2, 0x02, 0x00, 0x90, 0x7a,
+	0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00, 0x03, 0x18, 0x2f, 0xda,
+	0x03, 0x10, 0x02, 0xf6, 0x03, 0x10, 0x02, 0xe6, 0x00, 0x00, 0x60, 0x00,
+	0x03, 0x1a, 0x10, 0x8a, 0x03, 0x10, 0x02, 0xf6, 0x00, 0x19, 0x2e, 0x28,
+	0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x02, 0x64, 0x03, 0x00, 0x00, 0xaa,
+	0x02, 0x98, 0xac, 0xe2, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x02, 0x64,
+	0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0xbf, 0x7a, 0x22, 0x90, 0x02, 0xe6,
+	0x00, 0x00, 0x60, 0x00, 0x22, 0x96, 0xd6, 0x8a, 0x22, 0x90, 0x02, 0xf6,
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+	0x00, 0x14, 0x02, 0x74, 0x00, 0x19, 0x2a, 0x28, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x18, 0xe0, 0x29, 0x00, 0x00, 0x02, 0x66, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x00, 0x40, 0x00, 0x31, 0x80, 0x80, 0x59, 0x32, 0x19, 0x2e, 0x2a,
+	0x32, 0x00, 0x00, 0x6a, 0x31, 0x90, 0x02, 0xf4, 0x30, 0x02, 0x9d, 0x41,
+	0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4,
+	0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa,
+	0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a,
+	0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6,
+	0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64,
+	0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74,
+	0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62,
+	0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+static int load_bootstrap(void)
+{
+	const u8 *s = bootstrap_rbin;
+	u32 l = sizeof(bootstrap_rbin);
+	const u8 *data, *hdr, *h;
+	u32 chksum, chksum2;
+	int i, j, rangenr;
+	u32 start, length;
+
+	if (l < 12) {
+		printf("bootstrap image corrupted. (too short header)\n");
+		return -1;
+	}
+
+	chksum  = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] <<  8) |  (u32)s[ 7];
+	rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] <<  8) |  (u32)s[11];
+	s += 12; l -= 12;
+
+	hdr = s;
+	s += 8 * rangenr; l -= 8 * rangenr;
+	data = s;
+
+	/* validate bootstrap image */
+	h = hdr; s = data; chksum2 = 0;
+	for (i = 0; i < rangenr; i++) {
+		start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
+		length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
+		h += 8;
+
+		/* too short */
+		if (l < length) {
+			printf("bootstrap image corrupted. (too short data)\n");
+			return -1;
+		}
+		l -= length;
+
+		j = (int)length / 4;
+		while (j-- > 0) {
+			chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] <<  8) |  (u32)s[3];
+			s += 4;
+		}
+	}
+
+	/* checksum must match */
+	if (chksum != chksum2) {
+		printf("bootstrap image corrupted. (checksum error)\n");
+		return -1;
+	}
+
+	/* nothing must be left */
+	if (l != 0) {
+		printf("bootstrap image corrupted. (garbage at the end)\n");
+		return -1;
+	}
+
+	/* write the image */
+	h = hdr;
+	s = data;
+	for (i = 0; i < rangenr; i++) {
+		start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
+		length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
+		h += 8;
+		c62_write(start, (u32 *)s, length / 4);
+		s += length;
+	}
+
+	/* and now validate checksum */
+	h = hdr;
+	s = data;
+	chksum2 = 0;
+	for (i = 0; i < rangenr; i++) {
+		start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
+		length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
+		h += 8;
+		chksum2 += c62_checksum(start, length / 4);
+		s += length;
+	}
+
+	/* checksum must match */
+	if (chksum != chksum2) {
+		printf("bootstrap in DSP memory is corrupted\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+struct host_init {
+	u32 master_mode;
+	struct {
+		u8 port_id;
+		u8 slot_id;
+	} ch_serial_map[32];
+	u32 clk_divider[2];
+	/* pll */
+	u32 initmode;
+	u32 pllm;
+	u32 div[4];
+	u32 oscdiv1;
+	u32 unused[10];
+};
+
+const struct host_init hi_default = {
+	.master_mode	=
+#if !defined(CONFIG_NETTA_ISDN)
+		-1,
+#else
+		0,
+#endif
+
+	.ch_serial_map	= {
+		[ 0]	= { .port_id = 2, .slot_id = 16 },
+		[ 1]	= { .port_id = 2, .slot_id = 17 },
+		[ 2]	= { .port_id = 2, .slot_id = 18 },
+		[ 3]	= { .port_id = 2, .slot_id = 19 },
+		[ 4]	= { .port_id = 2, .slot_id = 20 },
+		[ 5]	= { .port_id = 2, .slot_id = 21 },
+		[ 6]	= { .port_id = 2, .slot_id = 22 },
+		[ 7]	= { .port_id = 2, .slot_id = 23 },
+		[ 8]	= { .port_id = 2, .slot_id = 24 },
+		[ 9]	= { .port_id = 2, .slot_id = 25 },
+		[10]	= { .port_id = 2, .slot_id = 26 },
+		[11]	= { .port_id = 2, .slot_id = 27 },
+		[12]	= { .port_id = 2, .slot_id = 28 },
+		[13]	= { .port_id = 2, .slot_id = 29 },
+		[14]	= { .port_id = 2, .slot_id = 30 },
+		[15]	= { .port_id = 2, .slot_id = 31 },
+	},
+
+	/*
+	   dsp_clk(xin, pllm)         = xin * pllm
+	   serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1)
+	 */
+
+	.clk_divider	= {
+		[0]	= 47,		/* must be 2048Hz */
+		[1] 	= 47,
+	},
+
+	.initmode	= 1,
+	.pllm		=
+#if !defined(CONFIG_NETTA_ISDN)
+	8,		/* for =~ 25MHz 8 */
+#else
+	4,
+#endif
+	.div		= {
+		[0]	= 0x8000,
+		[1]	= 0x8000,	/* for =~ 25MHz 0x8000 */
+		[2]	= 0x8001,	/* for =~ 25MHz 0x8001 */
+		[3]	= 0x8001,	/* for =~ 25MHz 0x8001 */
+	},
+
+	.oscdiv1	= 0,
+};
+
+static void hi_write(const struct host_init *hi)
+{
+	u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)];
+	u32 *s;
+	u32 chksum;
+	int i;
+
+	memset(hi_buf, 0, sizeof(hi_buf));
+
+	s = hi_buf;
+	s++;
+	*s++ = hi->master_mode;
+	for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++)
+		*s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) |
+				((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id;
+
+	for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++)
+		*s++ = hi->clk_divider[i];
+
+	*s++ = hi->initmode;
+	*s++ = hi->pllm;
+	for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++)
+		*s++ = hi->div[i];
+	*s++ = hi->oscdiv1;
+
+	chksum = 0;
+	for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++)
+		chksum += hi_buf[i];
+	hi_buf[0] = -chksum;
+
+	c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0]));
+}
+
+static void run_bootstrap(void)
+{
+	dsp_go_slow();
+
+	hi_write(&hi_default);
+
+	/* signal interrupt */
+	dsp_write_hpic(0x0002);
+	dsp_delay();
+
+	dsp_go_fast();
+}
+
+#endif
+
+/***********************************************************************************************************/
+
+int board_post_dsp(int flags)
+{
+	u32 ramS, ramE;
+	u32 data, data2;
+	int i, j, k;
+#if !defined(CONFIG_NETTA_6412)
+	int r;
+#endif
+	dsp_reset();
+	dsp_init_hpic();
+#if !defined(CONFIG_NETTA_6412)
+	dsp_go_slow();
+#endif
+	data = 0x11223344;
+	dsp_write_hpic_word(DSP_HPIA, data);
+	data2 = dsp_read_hpic_word(DSP_HPIA);
+	if (data2 !=   0x11223344) {
+		printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
+		goto err;
+	}
+
+	data = 0xFFEEDDCC;
+	dsp_write_hpic_word(DSP_HPIA, data);
+	data2 = dsp_read_hpic_word(DSP_HPIA);
+	if (data2 != 0xFFEEDDCC) {
+		printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
+		goto err;
+	}
+#if defined(CONFIG_NETTA_6412)
+	dsp_dram_initialize();
+#else
+	r = load_bootstrap();
+	if (r < 0) {
+		printf("BOOTSTRAP: ** ERROR ** failed to load\n");
+		goto err;
+	}
+
+	run_bootstrap();
+
+	dsp_go_fast();
+#endif
+	printf("    ");
+
+	/* test RAMs */
+	for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) {
+
+		ramS = ranges[k].start;
+		ramE = ranges[k].start + ranges[k].size;
+
+		for (j = 0; j < 3; j++) {
+
+			printf("\b\b\b\bR%d.%d", k, j);
+
+			for (i = ramS; i < ramE; i += 4) {
+
+				data = 0;
+				switch (j) {
+					case 0: data = 0xAA55AA55; break;
+					case 1: data = 0x55AA55AA; break;
+					case 2: data = (u32)i;     break;
+				}
+
+				c62_write_word(i, data);
+				data2 = c62_read_word(i);
+				if (data != data2) {
+					printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2);
+					goto err;
+				}
+			}
+		}
+	}
+
+	printf("\b\b\b\b    \b\b\b\bOK\n");
+#if !defined(CONFIG_NETTA_6412)
+	/* XXX assume that this works */
+	load_bootstrap();
+	run_bootstrap();
+	dsp_go_fast();
+#endif
+	return 0;
+
+err:
+	return -1;
+}
+
+int board_dsp_reset(void)
+{
+#if !defined(CONFIG_NETTA_6412)
+	int r;
+#endif
+	dsp_reset();
+	dsp_init_hpic();
+#if defined(CONFIG_NETTA_6412)
+	dsp_dram_initialize();
+#else
+	dsp_go_slow();
+	r = load_bootstrap();
+	if (r < 0)
+		return r;
+
+	run_bootstrap();
+	dsp_go_fast();
+#endif
+	return 0;
+}
diff --git a/board/netta/flash.c b/board/netta/flash.c
new file mode 100755
index 0000000..ca3e061
--- /dev/null
+++ b/board/netta/flash.c
@@ -0,0 +1,508 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/netta/netta.c b/board/netta/netta.c
new file mode 100755
index 0000000..9194bfb
--- /dev/null
+++ b/board/netta/netta.c
@@ -0,0 +1,600 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Intracom NETTA"
+#if defined(CONFIG_NETTA_ISDN)
+			" with ISDN support"
+#endif
+#if defined(CONFIG_NETTA_6412)
+			" (DSP:TI6412)"
+#else
+			" (DSP:TI6711)"
+#endif
+			"\n"
+			);
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define A10_AAAA	0x00000000
+#define A10_AAA0	0x00200000
+#define A10_AAA1	0x00300000
+#define A10_000A	0x00800000
+#define A10_0000	0x00A00000
+#define A10_0001	0x00B00000
+#define A10_111A	0x00C00000
+#define A10_1110	0x00E00000
+#define A10_1111	0x00F00000
+
+#define RAS_0000	0x00000000
+#define RAS_0001	0x00040000
+#define RAS_1110	0x00080000
+#define RAS_1111	0x000C0000
+
+#define CAS_0000	0x00000000
+#define CAS_0001	0x00010000
+#define CAS_1110	0x00020000
+#define CAS_1111	0x00030000
+
+#define WE_0000		0x00000000
+#define WE_0001		0x00004000
+#define WE_1110		0x00008000
+#define WE_1111		0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+/* #define CAS_LATENCY	3 */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 8 */
+#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+long int initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+	{
+		u32 d1, d2;
+
+		d1 = 0xAA55AA55;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+
+		d1 = 0x55AA55AA;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+#if 0
+	printf("check 0\n");
+	check_ram(( 0 << 20), (2 << 20));
+	printf("check 16\n");
+	check_ram((16 << 20), (2 << 20));
+	printf("check 32\n");
+	check_ram((32 << 20), (2 << 20));
+	printf("check 48\n");
+	check_ram((48 << 20), (2 << 20));
+#endif
+
+	if (size == 0) {
+		printf("SIZE is zero: LOOP on 0\n");
+		for (;;) {
+			*(volatile u32 *)0 = 0;
+			(void)*(volatile u32 *)0;
+		}
+	}
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r(void)
+{
+	return(0);
+}
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
+		if (v == 0xFFFF)
+			continue;
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
+		udelay(10000);
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+				PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		udelay(10000);
+	}
+}
+
+extern int board_dsp_reset(void);
+
+int last_stage_init(void)
+{
+	int r;
+
+	reset_phys();
+	r = board_dsp_reset();
+	if (r < 0)
+		printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	(_BWR(3) | _BWR(7, 9) | _BW(11))
+#define PA_GP_OUTMASK	(_BW(6) | _BW(10) | _BWR(12, 15))
+#define PA_SP_MASK	(_BWR(0, 2) | _BWR(4, 5))
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(13) | _BWR(14, 15))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	(_B(28) | _B(31))
+#define PB_GP_OUTMASK	(_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
+#define PB_SP_MASK	(_BR(22, 25))
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_SP_DIRVAL	0
+
+#define PC_GP_INMASK	(_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
+#define PC_GP_OUTMASK	(_BW(6) | _BW(12))
+#define PC_SP_MASK	(_BW(4) | _BW(8))
+#define PC_SOVAL	0
+#define PC_INTVAL	_BW(7)
+#define PC_GP_OUTVAL	(_BW(6) | _BW(12))
+#define PC_SP_DIRVAL	0
+
+#define PD_GP_INMASK	0
+#define PD_GP_OUTMASK	_BWR(3, 15)
+#define PD_SP_MASK	0
+
+#if defined(CONFIG_NETTA_6412)
+
+#define PD_GP_OUTVAL	(_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
+
+#else
+
+#define PD_GP_OUTVAL	(_BWR(5, 7) | _BW(9) | _BW(11))
+
+#endif
+
+#define PD_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* CS1: NAND chip select */
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#if !defined(CONFIG_NETTA_6412)
+	/* CS2: DSP */
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
+	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+#else
+	/* CS6: DSP */
+	memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
+	memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+#endif
+	/* CS4: External register chip select */
+	memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
+	memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+
+	/* CS5: dummy for accurate delay */
+	memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
+	memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	ioport->iop_pddat	= PD_GP_OUTVAL;
+	ioport->iop_pddir	= PD_GP_OUTMASK | PD_SP_DIRVAL;
+	ioport->iop_pdpar	= PD_SP_MASK;
+
+	/* ioport->iop_pddat |=  (1 << (15 - 6)) | (1 << (15 - 7)); */
+
+	return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <linux/mtd/nand.h>
+
+extern ulong nand_probe(ulong physadr);
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+
+int pcmcia_init(void)
+{
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds
new file mode 100755
index 0000000..9f2901c
--- /dev/null
+++ b/board/netta/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp		: { *(.interp)		}
+  .hash         : { *(.hash)		}
+  .dynsym       : { *(.dynsym)		}
+  .dynstr       : { *(.dynstr)		}
+  .rel.text     : { *(.rel.text)	}
+  .rela.text    : { *(.rela.text) 	}
+  .rel.data     : { *(.rel.data)	}
+  .rela.data    : { *(.rela.data) 	}
+  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.rodata  : { *(.rela.rodata)	}
+  .rel.got      : { *(.rel.got)		}
+  .rela.got     : { *(.rela.got)	}
+  .rel.ctors    : { *(.rel.ctors)	}
+  .rela.ctors   : { *(.rela.ctors)	}
+  .rel.dtors    : { *(.rel.dtors)	}
+  .rela.dtors   : { *(.rela.dtors)	}
+  .rel.bss      : { *(.rel.bss)		}
+  .rela.bss     : { *(.rela.bss)	}
+  .rel.plt      : { *(.rel.plt)		}
+  .rela.plt     : { *(.rela.plt)	}
+  .init         : { *(.init)		}
+  .plt			: { *(.plt) 		}
+  .text      	:
+  {
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug
new file mode 100755
index 0000000..004e7fd
--- /dev/null
+++ b/board/netta/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/netta2/Makefile b/board/netta2/Makefile
new file mode 100755
index 0000000..d457020
--- /dev/null
+++ b/board/netta2/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/netta2/config.mk b/board/netta2/config.mk
new file mode 100755
index 0000000..8497ebc
--- /dev/null
+++ b/board/netta2/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# netVia Boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/netta2/flash.c b/board/netta2/flash.c
new file mode 100755
index 0000000..a1c87f5
--- /dev/null
+++ b/board/netta2/flash.c
@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c
new file mode 100755
index 0000000..c9b4051
--- /dev/null
+++ b/board/netta2/netta2.c
@@ -0,0 +1,670 @@
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+int fec8xx_miiphy_read(char *devname, unsigned char addr,
+		unsigned char  reg, unsigned short *value);
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION);
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define GPL0_AAAA	0x00000000
+#define GPL0_AAA0	0x00200000
+#define GPL0_AAA1	0x00300000
+#define GPL0_000A	0x00800000
+#define GPL0_0000	0x00A00000
+#define GPL0_0001	0x00B00000
+#define GPL0_111A	0x00C00000
+#define GPL0_1110	0x00E00000
+#define GPL0_1111	0x00F00000
+
+#define GPL1_0000	0x00000000
+#define GPL1_0001	0x00040000
+#define GPL1_1110	0x00080000
+#define GPL1_1111	0x000C0000
+
+#define GPL2_0000	0x00000000
+#define GPL2_0001	0x00010000
+#define GPL2_1110	0x00020000
+#define GPL2_1111	0x00030000
+
+#define GPL3_0000	0x00000000
+#define GPL3_0001	0x00004000
+#define GPL3_1110	0x00008000
+#define GPL3_1111	0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+#define A10_AAAA	GPL0_AAAA
+#define A10_AAA0	GPL0_AAA0
+#define A10_AAA1	GPL0_AAA1
+#define A10_000A	GPL0_000A
+#define A10_0000	GPL0_0000
+#define A10_0001	GPL0_0001
+#define A10_111A	GPL0_111A
+#define A10_1110	GPL0_1110
+#define A10_1111	GPL0_1111
+
+#define RAS_0000	GPL1_0000
+#define RAS_0001	GPL1_0001
+#define RAS_1110	GPL1_1110
+#define RAS_1111	GPL1_1111
+
+#define CAS_0000	GPL2_0000
+#define CAS_0001	GPL2_0001
+#define CAS_1110	GPL2_1110
+#define CAS_1111	GPL2_1111
+
+#define WE_0000		GPL3_0000
+#define WE_0001		GPL3_0001
+#define WE_1110		GPL3_1110
+#define WE_1111		GPL3_1111
+
+/* #define CAS_LATENCY	3  */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+#if CONFIG_NETTA2_VERSION == 2
+static const uint nandcs_table[0x40] = {
+	/* RSS */
+	CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111,
+	CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,	/* NOP   */
+
+	/* RBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+	/* WBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 ,
+	CS_0001 | LAST,
+};
+#endif
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 8 */
+#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+long int initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mbmr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+	{
+		u32 d1, d2;
+
+		d1 = 0xAA55AA55;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+
+		d1 = 0x55AA55AA;
+		*(volatile u32 *)0 = d1;
+		d2 = *(volatile u32 *)0;
+		if (d1 != d2) {
+			printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+			hang();
+		}
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+	if (size == 0) {
+		printf("SIZE is zero: LOOP on 0\n");
+		for (;;) {
+			*(volatile u32 *)0 = 0;
+			(void)*(volatile u32 *)0;
+		}
+	}
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	udelay(10000);
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		fec8xx_miiphy_read(NULL, phyno, PHY_PHYIDR1, &v);
+		if (v == 0xFFFF)
+			continue;
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR, PHY_BMCR_POWD);
+		udelay(10000);
+		fec8xx_miiphy_write(NULL, phyno, PHY_BMCR,
+				PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		udelay(10000);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	0
+#define PA_GP_OUTMASK	(_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
+#define PA_SP_MASK	0
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(3) | _BW(14) | _BW(15))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	_B(28)
+#define PB_GP_OUTMASK	(_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_MASK	(_BR(22, 25))
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_B(26) | _B(27) | _B(29) | _B(30))
+#define PB_SP_DIRVAL	0
+
+#if CONFIG_NETTA2_VERSION == 1
+#define PC_GP_INMASK	_BW(12)
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(13) | _BW(15))
+#elif CONFIG_NETTA2_VERSION == 2
+#define PC_GP_INMASK	(_BW(13) | _BW(15))
+#define PC_GP_OUTMASK	(_BW(10) | _BW(11) | _BW(12))
+#endif
+#define PC_SP_MASK	0
+#define PC_SOVAL	0
+#define PC_INTVAL	0
+#define PC_GP_OUTVAL	(_BW(10) | _BW(11))
+#define PC_SP_DIRVAL	0
+
+#if CONFIG_NETTA2_VERSION == 1
+#define PE_GP_INMASK	_B(31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27) | _B(28))
+#elif CONFIG_NETTA2_VERSION == 2
+#define PE_GP_INMASK	_BR(28, 31)
+#define PE_GP_OUTMASK	(_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
+#define PE_GP_OUTVAL	(_B(20) | _B(24) | _B(27))
+#endif
+#define PE_SP_MASK	0
+#define PE_ODR_VAL	0
+#define PE_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* NAND chip select */
+#if CONFIG_NETTA2_VERSION == 1
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#elif CONFIG_NETTA2_VERSION == 2
+	upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
+	memctl->memc_mamr = 0;	/* all clear */
+#endif
+
+	/* DSP chip select */
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
+	memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+#if CONFIG_NETTA2_VERSION == 1
+	memctl->memc_br4 &= ~BR_V;
+#endif
+	memctl->memc_br5 &= ~BR_V;
+	memctl->memc_br6 &= ~BR_V;
+	memctl->memc_br7 &= ~BR_V;
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	cpm->cp_pedat		= PE_GP_OUTVAL;
+	cpm->cp_peodr		= PE_ODR_VAL;
+	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;
+	cpm->cp_pepar		= PE_SP_MASK;
+
+	return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <linux/mtd/nand.h>
+
+extern ulong nand_probe(ulong physadr);
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	unsigned long totlen;
+
+	totlen = nand_probe(CFG_NAND_BASE);
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
+
+#ifdef CONFIG_SHOW_ACTIVITY
+
+/* called from timer interrupt every 1/CFG_HZ sec */
+void board_show_activity(ulong timestamp)
+{
+}
+
+/* called when looping */
+void show_activity(int arg)
+{
+}
+
+#endif
+
+#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	/* printf("overwrite_console called\n"); */
+	return 0;
+}
+#endif
+
+extern int drv_phone_init(void);
+extern int drv_phone_use_me(void);
+extern int drv_phone_is_idle(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int last_stage_init(void)
+{
+#if CONFIG_NETTA2_VERSION == 2
+	int i;
+#endif
+
+#if CONFIG_NETTA2_VERSION == 2
+	/* assert peripheral reset */
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+	for (i = 0; i < 10; i++)
+		udelay(1000);
+	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
+#endif
+	reset_phys();
+
+	return 0;
+}
diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds
new file mode 100755
index 0000000..9f2901c
--- /dev/null
+++ b/board/netta2/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp		: { *(.interp)		}
+  .hash         : { *(.hash)		}
+  .dynsym       : { *(.dynsym)		}
+  .dynstr       : { *(.dynstr)		}
+  .rel.text     : { *(.rel.text)	}
+  .rela.text    : { *(.rela.text) 	}
+  .rel.data     : { *(.rel.data)	}
+  .rela.data    : { *(.rela.data) 	}
+  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.rodata  : { *(.rela.rodata)	}
+  .rel.got      : { *(.rel.got)		}
+  .rela.got     : { *(.rela.got)	}
+  .rel.ctors    : { *(.rel.ctors)	}
+  .rela.ctors   : { *(.rela.ctors)	}
+  .rel.dtors    : { *(.rel.dtors)	}
+  .rela.dtors   : { *(.rela.dtors)	}
+  .rel.bss      : { *(.rel.bss)		}
+  .rela.bss     : { *(.rela.bss)	}
+  .rel.plt      : { *(.rel.plt)		}
+  .rela.plt     : { *(.rela.plt)	}
+  .init         : { *(.init)		}
+  .plt			: { *(.plt) 		}
+  .text      	:
+  {
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug
new file mode 100755
index 0000000..004e7fd
--- /dev/null
+++ b/board/netta2/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/netvia/Makefile b/board/netvia/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/netvia/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/netvia/config.mk b/board/netvia/config.mk
new file mode 100755
index 0000000..9dddaad
--- /dev/null
+++ b/board/netvia/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# netVia Boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/netvia/flash.c b/board/netvia/flash.c
new file mode 100755
index 0000000..d31f770
--- /dev/null
+++ b/board/netvia/flash.c
@@ -0,0 +1,511 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c
new file mode 100755
index 0000000..fb7f770
--- /dev/null
+++ b/board/netvia/netvia.c
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetVia board
+ */
+
+#include <common.h>
+#include "mpc8xx.h"
+
+/****************************************************************/
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+/* last value written to the external register; we cannot read back */
+unsigned int last_er_val;
+#endif
+
+/****************************************************************/
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define A10_AAAA	0x00000000
+#define A10_AAA0	0x00200000
+#define A10_AAA1	0x00300000
+#define A10_000A	0x00800000
+#define A10_0000	0x00A00000
+#define A10_0001	0x00B00000
+#define A10_111A	0x00C00000
+#define A10_1110	0x00E00000
+#define A10_1111	0x00F00000
+
+#define RAS_0000	0x00000000
+#define RAS_0001	0x00040000
+#define RAS_1110	0x00080000
+#define RAS_1111	0x000C0000
+
+#define CAS_0000	0x00000000
+#define CAS_0001	0x00010000
+#define CAS_1110	0x00020000
+#define CAS_1111	0x00030000
+
+#define WE_0000		0x00000000
+#define WE_0001		0x00004000
+#define WE_1110		0x00008000
+#define WE_1111		0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+const uint sdram_table[0x40] = {
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,
+
+	/* REG */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ETX ID string (ETX_xxx...)
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+	printf ("NETVIA v1\n");
+#else
+	printf ("NETVIA v2+\n");
+#endif
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+#define MAR_SDRAM_INIT		0x000000C8LU
+
+#define MCR_OP(x)		((unsigned long)((x) & 3) << (31-1))
+#define MCR_OP_MASK		MCR_OP(3)
+
+#define MCR_UM(x)		((unsigned long)((x) & 1) << (31 - 8))
+#define MCR_UM_MASK		MCR_UM(1)
+#define MCR_UM_UPMA		MCR_UM(0)
+#define MCR_UM_UPMB		MCR_UM(1)
+
+#define MCR_MB(x)		((unsigned long)((x) & 7) << (31 - 18))
+#define MCR_MB_MASK		MCR_MB(7)
+#define MCR_MB_CS(x)		MCR_MB(x)
+
+#define MCR_MCLF(x)		((unsigned long)((x) & 15) << (31 - 23))
+#define MCR_MCLF_MASK		MCR_MCLF(15)
+
+long int initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+    /*
+     * Map controller bank 3 to the SDRAM bank at preliminary address.
+     */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_9COL & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C);	/* precharge all			*/
+	udelay(1);
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0)		*/
+	udelay(1);
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E);	/* exception program (write mar) */
+	udelay(1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(1000);
+
+	memctl->memc_mamr = CFG_MAMR_9COL;
+
+	size = SDRAM_MAX_SIZE;
+
+	udelay(10000);
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r(void)
+{
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+	last_er_val = 0xffffffff;
+#endif
+	return(0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	0
+#define PA_GP_OUTMASK	(_BW(5) | _BWR(14, 15))
+#define PA_SP_MASK	(_BW(4) | _BWR(6, 13))
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	_BW(5)
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	_B(28)
+#define PB_GP_OUTMASK	(_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_SP_MASK	_BR(22, 25)
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
+#define PB_SP_DIRVAL	0
+
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+
+#define PC_GP_INMASK	(_BWR(5, 7) | _BWR(9, 10) | _BW(13))
+#define PC_GP_OUTMASK	_BW(12)
+#define PC_SP_MASK	(_BW(4) | _BW(8))
+#define PC_SOVAL	0
+#define PC_INTVAL	0
+#define PC_GP_OUTVAL	0
+#define PC_SP_DIRVAL	0
+
+#define PD_GP_INMASK	0
+#define PD_GP_OUTMASK	_BWR(3, 15)
+#define PD_SP_MASK	0
+#define PD_GP_OUTVAL	(_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15))
+#define PD_SP_DIRVAL	0
+
+#elif CONFIG_NETVIA_VERSION >= 2
+
+#define PC_GP_INMASK	(_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15))
+#define PC_GP_OUTMASK	(_BW(6) | _BW(12))
+#define PC_SP_MASK	(_BW(4) | _BW(8))
+#define PC_SOVAL	0
+#define PC_INTVAL	_BW(7)
+#define PC_GP_OUTVAL	(_BW(6) | _BW(12))
+#define PC_SP_DIRVAL	0
+
+#define PD_GP_INMASK	0
+#define PD_GP_OUTMASK	_BWR(3, 15)
+#define PD_SP_MASK	0
+#define PD_GP_OUTVAL	(_BW(3) | _BW(5) | _BW(9) | _BW(11))
+#define PD_SP_DIRVAL	0
+
+#else
+#error Unknown NETVIA board version.
+#endif
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* DSP0 chip select */
+	memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
+	memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+	/* DSP1 chip select */
+	memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
+	memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
+
+	/* FPGA chip select */
+	memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK);
+	memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+	/* NAND chip select */
+	memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
+	memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+
+	/* kill this chip select */
+	memctl->memc_br2 &= ~BR_V;	/* invalid */
+
+	/* external reg chip select */
+	memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
+	memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
+#endif
+
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	ioport->iop_pddat	= PD_GP_OUTVAL;
+	ioport->iop_pddir	= PD_GP_OUTMASK | PD_SP_DIRVAL;
+	ioport->iop_pdpar	= PD_SP_MASK;
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+	/* external register init */
+	*(volatile uint *)ER_BASE = 0xFFFFFFFF;
+#endif
+
+	return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <linux/mtd/nand.h>
+
+extern ulong nand_probe(ulong physadr);
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds
new file mode 100755
index 0000000..dc69db6
--- /dev/null
+++ b/board/netvia/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp		: { *(.interp)		}
+  .hash         : { *(.hash)		}
+  .dynsym       : { *(.dynsym)		}
+  .dynstr       : { *(.dynstr)		}
+  .rel.text     : { *(.rel.text)	}
+  .rela.text    : { *(.rela.text) 	}
+  .rel.data     : { *(.rel.data)	}
+  .rela.data    : { *(.rela.data) 	}
+  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.rodata  : { *(.rela.rodata)	}
+  .rel.got      : { *(.rel.got)		}
+  .rela.got     : { *(.rela.got)	}
+  .rel.ctors    : { *(.rel.ctors)	}
+  .rela.ctors   : { *(.rela.ctors)	}
+  .rel.dtors    : { *(.rel.dtors)	}
+  .rela.dtors   : { *(.rela.dtors)	}
+  .rel.bss      : { *(.rel.bss)		}
+  .rela.bss     : { *(.rela.bss)	}
+  .rel.plt      : { *(.rel.plt)		}
+  .rela.plt     : { *(.rela.plt)	}
+  .init         : { *(.init)		}
+  .plt			: { *(.plt) 		}
+  .text      	:
+  {
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug
new file mode 100755
index 0000000..96569bf
--- /dev/null
+++ b/board/netvia/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile
new file mode 100755
index 0000000..fb4333c
--- /dev/null
+++ b/board/ns9750dev/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ns9750dev.o flash.o led.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ns9750dev/config.mk b/board/ns9750dev/config.mk
new file mode 100755
index 0000000..6a22cee
--- /dev/null
+++ b/board/ns9750dev/config.mk
@@ -0,0 +1,16 @@
+#######################################################################
+#
+# Copyright (C) 2004 by FS Forth-Systeme GmbH.
+# Markus Pietrek <mpietrek@fsforth.de>
+#
+# @TODO
+# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000
+# optionally with a ramdisk at 0080'0000
+#
+# we load ourself to 0078'0000
+#
+# download area is 0060'0000
+#
+
+
+TEXT_BASE = 0x00780000
diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c
new file mode 100755
index 0000000..e7d6515
--- /dev/null
+++ b/board/ns9750dev/flash.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/ns9750dev/led.c b/board/ns9750dev/led.c
new file mode 100755
index 0000000..b85c869
--- /dev/null
+++ b/board/ns9750dev/led.c
@@ -0,0 +1,46 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @Descr: Defines helper functions for toggeling LEDs
+ * @Usage:
+ * @References: [1]
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifdef CONFIG_STATUS_LED
+
+#include <ns9750_bbus.h>
+
+static inline void __led_init( led_id_t mask, int state )
+{
+	XXXX;
+}
+
+static inline void __led_toggle( led_id_t mask )
+{
+}
+
+static inline void __led_set( led_id_t mask, int state )
+{
+}
+
+#endif /* CONFIG_STATUS_LED */
diff --git a/board/ns9750dev/lowlevel_init.S b/board/ns9750dev/lowlevel_init.S
new file mode 100755
index 0000000..3a09786
--- /dev/null
+++ b/board/ns9750dev/lowlevel_init.S
@@ -0,0 +1,298 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for the NS9750 DevBoard by
+ * (C) Copyright 2004 by FS Forth-Systeme GmbH.
+ * Markus Pietrek <mpietrek@fsforth.de>
+ * @References: [1] NS9750 Hardware Reference/December 2003
+ *	        [2] ns9750_a.cmd from MAJIC configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_NS9750DEV)
+# ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#  include <./ns9750_sys.h>
+#  include <./ns9750_mem.h>
+# endif
+#endif
+
+/***********************************************************************
+ * @Function: write_register_block
+ * @Return: nothing
+ * @Descr: Copies the register block of register_offset:register value to
+ *         the registers at base r0. The block is assumed to start in RAM at r1
+ *         and end at r2. The linked RAM base address of U-Boot is assumed to be
+ *	   in r5 while the ROM base address we are running from is r6
+ *         Uses r3 and r4 as tempory registers
+ ***********************************************************************/
+
+.macro	write_register_block
+	@@ map the addresses to high memory
+	sub	r1, r1, r5
+	add	r1, r1, r6
+	sub	r2, r2, r5
+	add	r2, r2, r6
+
+	@@ copy all
+1:
+	@@ Write register/value pair starting at [r1] to register base r0
+	ldr	r3, [r1], #4
+	ldr	r4, [r1], #4
+	str	r4, [r0,r3]
+	cmp	r1, r2
+	blt	1b
+.endm
+
+_TEXT_BASE:
+	.word	TEXT_BASE	@ sdram load addr from config.mk
+_PHYS_FLASH:
+	.word	PHYS_FLASH_1    @ real flash address (without mirroring)
+_CAS_LATENCY:
+	.word	0x00022000	@ for CAS2 latency
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+
+	/* U-Boot may be linked to RAM at 0x780000. But this code will run in
+	   flash from 0x0. But in order to enable RAM we have to disable the
+	   mirror bit, therefore we have to jump to our real flash address
+	   beginning at PHYS_FLASH_1 (CS4 Base). Therefore,
+	   _run_at_real_flash_address may be 0x500003b0 while be linked to
+	   0x7803b0. So we must modify our linked addresses */
+
+	@@ branch to high memory address, away from 0x0
+	ldr	r5, _TEXT_BASE
+	ldr	r6, _PHYS_FLASH
+	ldr	r0, =_run_at_real_flash_address
+	sub	r0, r0, r5
+	add	r0, r0, r6
+	mov	pc, r0
+	nop			@ for pipelining
+
+_run_at_real_flash_address:
+	@@ now we are running > PHYS_FLASH_1, safe to enable memory controller
+
+	@@ Write Memory Configuration Registers
+
+	ldr	r0, _NS9750_MEM_MODULE_BASE
+	ldr	r1, =_MEM_CONFIG_START
+	ldr	r2, =_MEM_CONFIG_END
+
+	write_register_block
+
+	@@ Give SDRAM some time to settle
+	@@ @TODO. According to [2] it should be 2 AHB cycles. Check
+
+	ldr	r1, =0x50
+_sdram_settle:
+	subs	r1, r1, #1
+	bne	_sdram_settle
+
+_enable_mappings:
+	@@ Enable SDRAM Mode
+
+	ldr	r1, =_MEM_MODE_START
+	ldr	r2, =_MEM_MODE_END
+
+	write_register_block
+
+	ldr	r3, _CAS_LATENCY @ perform one read from SDRAM
+	ldr	r3, [r3]
+
+	@@ Enable SDRAM and memory mappings
+
+	ldr	r1, =_MEM_ENABLE_START
+	ldr	r2, =_MEM_ENABLE_END
+
+	write_register_block
+
+	@@ Activate AHB monitor
+
+	ldr	r0, =NS9750_SYS_MODULE_BASE
+	ldr	r1, =_AHB_MONITOR_START
+	ldr	r2, =_AHB_MONITOR_END
+
+	write_register_block
+_relocate_lr:
+	/* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to
+	   PHYS_FLASH. */
+	mov	r1, ip
+	add	r1, r1, r6
+	mov	ip, r1
+
+	mov	r1, lr
+	add	r1, r1, r6
+	mov	lr, r1
+
+	@@ back to arch calling code
+	mov	pc,	lr
+
+	.ltorg
+
+_NS9750_MEM_MODULE_BASE:
+	.word	NS9750_MEM_MODULE_BASE
+
+_MEM_CONFIG_START:
+	/* Table of 2 32bit entries. First word is register address offset
+	   relative to NS9750_MEM_MODULE_BASE, second one is value. They are
+	   written in order of appearance */
+
+	@@ Register values taken from [2]
+	.word	NS9750_MEM_CTRL
+	.word	NS9750_MEM_CTRL_E
+
+	.word	NS9750_MEM_DYN_REFRESH
+	.word	(0x6 & NS9750_MEM_DYN_REFRESH_MA)
+
+	.word	NS9750_MEM_DYN_READ_CFG
+	.word	(0x1 & NS9750_MEM_DYN_READ_CFG_MA)
+
+	.word	NS9750_MEM_DYN_TRP
+	.word	(0x1 & NS9750_MEM_DYN_TRP_MA)
+
+	.word	NS9750_MEM_DYN_TRAS
+	.word	(0x4 & NS9750_MEM_DYN_TRAS_MA)
+
+	.word	NS9750_MEM_DYN_TAPR
+	.word	(0x1 & NS9750_MEM_DYN_TRAS_MA)
+
+	.word	NS9750_MEM_DYN_TDAL
+	.word	(0x5 & NS9750_MEM_DYN_TDAL_MA)
+
+	.word	NS9750_MEM_DYN_TWR
+	.word	(0x1 & NS9750_MEM_DYN_TWR_MA)
+
+	.word	NS9750_MEM_DYN_TRC
+	.word	(0x6 & NS9750_MEM_DYN_TRC_MA)
+
+	.word	NS9750_MEM_DYN_TRFC
+	.word	(0x6 & NS9750_MEM_DYN_TRFC_MA)
+
+	.word	NS9750_MEM_DYN_TRRD
+	.word	(0x1 & NS9750_MEM_DYN_TRRD_MA)
+
+	.word	NS9750_MEM_DYN_TMRD
+	.word	(0x1 & NS9750_MEM_DYN_TMRD_MA)
+
+	@@ CS 4
+	.word	NS9750_MEM_DYN_CFG(0)
+	.word	(NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	.word	NS9750_MEM_DYN_RAS_CAS(0)
+	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+	@@ CS 5
+	.word	NS9750_MEM_DYN_CFG(1)
+	.word	(NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	.word	NS9750_MEM_DYN_RAS_CAS(1)
+	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+	@@ CS 6
+	.word	NS9750_MEM_DYN_CFG(2)
+	.word	(NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	.word	NS9750_MEM_DYN_RAS_CAS(2)
+	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+	@@ CS 7
+	.word	NS9750_MEM_DYN_CFG(3)
+	.word	(NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	.word	NS9750_MEM_DYN_RAS_CAS(3)
+	.word	((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+		 (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+	.word	NS9750_MEM_DYN_CTRL
+	.word	(NS9750_MEM_DYN_CTRL_I_PALL | \
+		 NS9750_MEM_DYN_CTRL_SR | \
+		 NS9750_MEM_DYN_CTRL_CE )
+
+	.word	NS9750_MEM_DYN_REFRESH
+	.word	(0x1 & NS9750_MEM_DYN_REFRESH_MA)
+	@@ No further register settings after refresh
+_MEM_CONFIG_END:
+
+_MEM_MODE_START:
+	.word	NS9750_MEM_DYN_REFRESH
+	.word	(0x30 & NS9750_MEM_DYN_REFRESH_MA)
+
+	.word	NS9750_MEM_DYN_CTRL
+	.word	(NS9750_MEM_DYN_CTRL_I_MODE | \
+		 NS9750_MEM_DYN_CTRL_SR | \
+		 NS9750_MEM_DYN_CTRL_CE )
+_MEM_MODE_END:
+
+_MEM_ENABLE_START:
+	.word	NS9750_MEM_DYN_CTRL
+	.word	(NS9750_MEM_DYN_CTRL_I_NORMAL | \
+		 NS9750_MEM_DYN_CTRL_SR | \
+		 NS9750_MEM_DYN_CTRL_CE )
+
+	@@ CS 4
+	.word	NS9750_MEM_DYN_CFG(0)
+	.word	(NS9750_MEM_DYN_CFG_BDMC | \
+		 NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	@@ CS 5
+	.word	NS9750_MEM_DYN_CFG(1)
+	.word	(NS9750_MEM_DYN_CFG_BDMC | \
+		 NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	@@ CS 6
+	.word	NS9750_MEM_DYN_CFG(2)
+	.word	(NS9750_MEM_DYN_CFG_BDMC | \
+		 NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+	@@ CS 7
+	.word	NS9750_MEM_DYN_CFG(3)
+	.word	(NS9750_MEM_DYN_CFG_BDMC | \
+		 NS9750_MEM_DYN_CFG_AM | \
+		 (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+_MEM_ENABLE_END:
+
+_AHB_MONITOR_START:
+	.word	NS9750_SYS_AHB_TIMEOUT
+	.word	0x01000100	@ @TODO not calculated yet
+
+	.word	NS9750_SYS_AHB_MON
+	.word	(NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \
+		 NS9750_SYS_AHB_MON_BATC_GEN_IRQ)
+_AHB_MONITOR_END:
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c
new file mode 100755
index 0000000..ea00d5a
--- /dev/null
+++ b/board/ns9750dev/ns9750dev.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ * Markus Pietrek <mpietrek@fsforth.de>
+ * derived from omap1610innovator.c
+ * @References: [1] NS9750 Hardware Reference/December 2003
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_NS9750DEV)
+# include <./configs/ns9750dev.h>
+# include <./ns9750_bbus.h>
+#endif
+
+void flash__init( void );
+void ether__init( void );
+
+static inline void delay( unsigned long loops )
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+
+/***********************************************************************
+ * @Function: board_init
+ * @Return: 0
+ * @Descr: Enables BBUS modules and other devices
+ ***********************************************************************/
+
+int board_init( void )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Active BBUS modules */
+	*get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0;
+
+#warning Please register your machine at http://www.arm.linux.org.uk/developer/machines/?action=new
+	/* arch number of OMAP 1510-Board */
+	/* to be changed for OMAP 1610 Board */
+	gd->bd->bi_arch_number = 234;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable();
+
+	flash__init();
+	ether__init();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	  		   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#if CONFIG_NR_DRAM_BANKS > 1
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+	return 0;
+}
diff --git a/board/ns9750dev/u-boot.lds b/board/ns9750dev/u-boot.lds
new file mode 100755
index 0000000..8ebb651
--- /dev/null
+++ b/board/ns9750dev/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = . ;
+
+}
diff --git a/board/nx823/Makefile b/board/nx823/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/nx823/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/nx823/config.mk b/board/nx823/config.mk
new file mode 100755
index 0000000..3b3ea1e
--- /dev/null
+++ b/board/nx823/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Nexus boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/nx823/flash.c b/board/nx823/flash.c
new file mode 100755
index 0000000..581925e
--- /dev/null
+++ b/board/nx823/flash.c
@@ -0,0 +1,464 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern u_long  *my_sernum;		/* from nx823.c */
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#endif
+
+#define FPW		FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int   write_data (flash_info_t *info, ulong dest, FPW data);
+static void  flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_FLASH_BASE,
+			    CFG_FLASH_BASE+monitor_flash_len-1,
+			    &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+   case FLASH_28F320J3A:
+				printf ("28F320J3A\n"); break;
+   case FLASH_28F640J3A:
+				printf ("28F640J3A\n"); break;
+   case FLASH_28F128J3A:
+				printf ("28F128J3A\n"); break;
+	default:		printf ("Unknown Chip Type\n"); break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW)0x00AA00AA;
+	addr[0x2AAA] = (FPW)0x00550055;
+	addr[0x5555] = (FPW)0x00900090;
+
+	value = addr[0];
+
+   switch (value) {
+   case (FPW)INTEL_MANUFACT:
+      info->flash_id = FLASH_MAN_INTEL;
+      break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+   switch (value) {
+   case (FPW)INTEL_ID_28F320J3A:
+      info->flash_id += FLASH_28F320J3A;
+      info->sector_count = 32;
+      info->size = 0x00400000;
+      break;            /* => 4 MB     */
+
+   case (FPW)INTEL_ID_28F640J3A:
+      info->flash_id += FLASH_28F640J3A;
+      info->sector_count = 64;
+      info->size = 0x00800000;
+      break;            /* => 8 MB     */
+
+   case (FPW)INTEL_ID_28F128J3A:
+      info->flash_id += FLASH_28F128J3A;
+      info->sector_count = 128;
+      info->size = 0x01000000;
+      break;            /* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *)(info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			*addr = (FPW)0x00500050;	/* clear status register */
+			*addr = (FPW)0x00200020;	/* erase setup */
+			*addr = (FPW)0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW)0x00B000B0; /* suspend erase	  */
+					*addr = (FPW)0x00FF00FF; /* reset to read mode */
+					rcode = 1;
+					break;
+				}
+
+				/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			*addr = (FPW)0x00FF00FF;	/* reset to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/* save sernum if needed */
+	if (addr >= CFG_FLASH_SN_SECTOR && addr < CFG_FLASH_SN_BASE)
+	{
+		u_long dest = CFG_FLASH_SN_BASE;
+		u_short *sn = (u_short *)my_sernum;
+
+		printf("(saving sernum)");
+		for (i=0; i<4; i++)
+		{
+			if ((rc = write_data(info, dest, sn[i])) != 0) {
+				return (rc);
+			}
+			dest += port_width;
+		}
+	}
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<port_width && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i=0; i<port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800)
+		{
+			putc('.');
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *)dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf("not erased at %08lx (%x)\n",(ulong)addr,*addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*addr = (FPW)0x00400040;		/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW)0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW)0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c
new file mode 100755
index 0000000..65d45c1
--- /dev/null
+++ b/board/nx823/nx823.c
@@ -0,0 +1,404 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+#if (MPC8XX_SPEED <= 50000000L)
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
+	0xFFFFFFFF,
+
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FE7F434, 0xEFABE834, 0x1FA7D435,
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
+	0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
+	0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
+#else
+
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
+	0x1FF7F447,
+
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
+
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+	printf ("Board: Nexus NX823");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0, size_b1, size8, size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Up to 2 Banks of 64Mbit x 2 devices
+	 * Initial builds only have 1
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller SDRAM bank 0
+	 */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	udelay (200);
+
+	/*
+	 * Map controller SDRAM bank 1
+	 */
+	memctl->memc_or2 = CFG_OR2_PRELIM;
+	memctl->memc_br2 = CFG_BR2_PRELIM;
+
+	/*
+	 * Perform SDRAM initializsation sequence
+	 */
+	memctl->memc_mcr = 0x80002105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80002230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 1 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 1 - execute twice */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	udelay (1000);
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {	/* leave configuration at 9 columns     */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {		/* back to 8 columns                    */
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	/*
+	 * Check Bank 1 Memory Size
+	 * use current column settings
+	 * [9 column SDRAM may also be used in 8 column mode,
+	 *  but then only half the real size will be used.]
+	 */
+	size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
+			     SDRAM_MAX_SIZE);
+/*	debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);	*/
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
+
+		memctl->memc_or2 =
+			((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_br2 =
+			(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b0 > 0) {
+			/*
+			 * Position Bank 0 immediately above Bank 1
+			 */
+			memctl->memc_or1 =
+				((-size_b0) & 0xFFFF0000) |
+				CFG_OR_TIMING_SDRAM;
+			memctl->memc_br1 =
+				((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
+				 BR_V)
+				+ size_b1;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 0
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br1 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+
+	} else {		/* SDRAM Bank 0 is bigger - map first   */
+
+		memctl->memc_or1 =
+			((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_br1 =
+			(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b1 > 0) {
+			/*
+			 * Position Bank 1 immediately above Bank 0
+			 */
+			memctl->memc_or2 =
+				((-size_b1) & 0xFFFF0000) |
+				CFG_OR_TIMING_SDRAM;
+			memctl->memc_br2 =
+				((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
+				 BR_V)
+				+ size_b0;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 1
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br2 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+	}
+
+	udelay (10000);
+
+	return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+u_long *my_sernum;
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char tmp[50];
+	u_char *e = gd->bd->bi_enetaddr;
+
+	/* save serial numbre from flash (uniquely programmed) */
+	my_sernum = malloc (8);
+	memcpy (my_sernum, gd->bd->bi_sernum, 8);
+
+	/* save env variables according to sernum */
+	sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
+	setenv ("serial#", tmp);
+
+	sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3],
+		 e[4], e[5]);
+	setenv ("ethaddr", tmp);
+	return (0);
+}
+
+void load_sernum_ethaddr (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int i;
+	bd_t *bd = gd->bd;
+
+	for (i = 0; i < 8; i++) {
+		bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i);
+	}
+	bd->bi_enetaddr[0] = 0x10;
+	bd->bi_enetaddr[1] = 0x20;
+	bd->bi_enetaddr[2] = 0x30;
+	bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
+	bd->bi_enetaddr[4] = bd->bi_sernum[5];
+	bd->bi_enetaddr[5] = bd->bi_sernum[6];
+}
diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds
new file mode 100755
index 0000000..7099fc4
--- /dev/null
+++ b/board/nx823/u-boot.lds
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug
new file mode 100755
index 0000000..3165d56
--- /dev/null
+++ b/board/nx823/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/o2dnt/Makefile b/board/o2dnt/Makefile
new file mode 100755
index 0000000..2eb4366
--- /dev/null
+++ b/board/o2dnt/Makefile
@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/o2dnt/config.mk b/board/o2dnt/config.mk
new file mode 100755
index 0000000..b873376
--- /dev/null
+++ b/board/o2dnt/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# boot low for 16 MiB boards
+TEXT_BASE = 0xFF000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/o2dnt/flash.c b/board/o2dnt/flash.c
new file mode 100755
index 0000000..037d287
--- /dev/null
+++ b/board/o2dnt/flash.c
@@ -0,0 +1,587 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * flash_real_protect() routine based on boards/alaska/flash.c
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Intel-compatible flash commands */
+#define INTEL_ERASE	0x20
+#define INTEL_PROGRAM	0x40
+#define INTEL_CLEAR	0x50
+#define INTEL_LOCKBIT	0x60
+#define INTEL_PROTECT	0x01
+#define INTEL_STATUS	0x70
+#define INTEL_READID	0x90
+#define INTEL_READID	0x90
+#define INTEL_SUSPEND	0xB0
+#define INTEL_CONFIRM	0xD0
+#define INTEL_RESET	0xFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED	0x80
+#define INTEL_OK	0x80
+
+typedef unsigned char FLASH_PORT_WIDTH;
+typedef volatile unsigned char FLASH_PORT_WIDTHV;
+#define FPW		FLASH_PORT_WIDTH
+#define FPWV		FLASH_PORT_WIDTHV
+#define	FLASH_ID_MASK	0xFF
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+static int write_data (flash_info_t *info, FPWV *dest, FPW data); /* O2D */
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(ulong);
+
+	flash_preinit();
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Query flash chip */
+	flash_info[0].size =
+		flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+	size += flash_info[0].size;
+
+	/* get the h/w and s/w protection status in sync */
+	flash_sync_real_protect(&flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_MONITOR_BASE,
+			CFG_MONITOR_BASE+monitor_flash_len-1,
+			flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+			flash_get_info(CFG_ENV_ADDR));
+#endif
+
+
+	flash_afterinit(size);
+	return (size ? size : 1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW) INTEL_RESET;	/* Intel Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size &&
+				info->start[0] <= base &&
+				base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return (i == CFG_MAX_FLASH_BANKS ? 0 : info);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_INTEL:
+			printf ("INTEL ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	} else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_28F128J3A:
+			fmt = "28F128J3 (128 Mbit, uniform sectors)\n";
+			break;
+		default:
+			fmt = "Unknown Chip Type\n";
+			break;
+	}
+
+	printf (fmt, bootletter, boottype);
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20,
+			info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int i;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW) INTEL_READID;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+		case (uchar)INTEL_MANUFACT:
+			info->flash_id = FLASH_MAN_INTEL;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	/* Strataflash is configurable to 8/16bit Bus,
+	 * but the Query-Structure is Word-orientated */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch ((FPW)addr[2]) {
+			case (FPW)INTEL_ID_28F128J3:
+				info->flash_id += FLASH_28F128J3A;
+				info->sector_count = 128;
+				info->size = 0x01000000;
+				for( i = 0; i < info->sector_count; i++ )
+					info->start[i] = (ulong)addr + (i * 0x20000);
+				break;				/* => Intel Strataflash 16MB */
+			default:
+				printf("Flash_id != %xd\n", (FPW)addr[2]);
+				info->flash_id = FLASH_UNKNOWN;
+				info->sector_count = 0;
+				info->size = 0;
+				return (0);			/* => no or unknown flash */
+		}
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_28F128J3A:
+			break;
+		case FLASH_UNKNOWN:
+		default:
+			printf ("Can't erase unknown flash type %08lx - aborted\n",
+					info->flash_id);
+			return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect)
+		if (info->protect[sect])
+			prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!",
+				prot);
+
+	printf ("\n");
+	last = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		*addr = (FPW) INTEL_CLEAR; /* clear status register */
+		*addr = (FPW) INTEL_ERASE; /* erase setup */
+		*addr = (FPW) INTEL_CONFIRM; /* erase confirm */
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		/* wait at least 80us for Intel - let's wait 1 ms */
+		udelay (1000);
+
+		while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) INTEL_SUSPEND;/* suspend erase */
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) { /* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode */
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0;	/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	/* number of bytes to program in current word		*/
+	int left;	/* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+			left > 0 && res == 0;
+			addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits  */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left )
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+			case FLASH_MAN_INTEL:
+				res = write_data(info, (FPWV *)addr, data);
+				break;
+			default:
+				/* unknown flash type, error! */
+				printf ("missing or unknown FLASH type\n");
+				res = 1;	/* not really a timeout, but gives error */
+				break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, FPWV *dest, FPW data)
+{
+	FPWV *addr = dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) INTEL_PROGRAM;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer(0);
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) INTEL_RESET;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) INTEL_RESET;	/* restore read mode */
+	if (flag)
+		enable_interrupts();
+
+	return (0);
+}
+
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	ulong start;
+	int i;
+	int rc = 0;
+	FPWV *addr = (FPWV *) (info->start[sector]);
+	int flag = disable_interrupts ();
+
+	*addr = INTEL_CLEAR;	/* Clear status register    */
+	if (prot) {		/* Set sector lock bit      */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit          */
+		*addr = INTEL_PROTECT;	/* set                      */
+	} else {		/* Clear sector lock bit    */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits    */
+		*addr = INTEL_CONFIRM;	/* clear                    */
+	}
+
+	start = get_timer (0);
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
+			printf ("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
+			(uint) addr, (uint) * addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (info->protect[i]) {
+				start = get_timer (0);
+				addr = (FPWV *) (info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
+				*addr = INTEL_PROTECT;	/* set              */
+				while ((*addr & INTEL_FINISHED) !=
+				       INTEL_FINISHED) {
+					if (get_timer (start) >
+					    CFG_FLASH_UNLOCK_TOUT) {
+						printf ("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	if (flag)
+		enable_interrupts ();
+
+	*addr = INTEL_RESET;	/* Reset to read array mode */
+
+	return rc;
+}
+
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+	int i;
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		for (i = 0; i < info->sector_count; ++i) {
+			info->protect[i] = intel_sector_protected(info, i);
+		}
+		break;
+	default:
+		/* no h/w protect support */
+		break;
+	}
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+	FPWV *addr;
+	FPWV *lock_conf_addr;
+	ulong start;
+	unsigned char ret;
+
+	/*
+	 * first, wait for the WSM to be finished. The rationale for
+	 * waiting for the WSM to become idle for at most
+	 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * because of: (1) erase, (2) program or (3) lock bit
+	 * configuration. So we just wait for the longest timeout of
+	 * the (1)-(3), i.e. the erase timeout.
+	 */
+
+	/* wait at least 35ns (W12) before issuing Read Status Register */
+	udelay(1);
+	addr = (FPWV *) info->start[sector];
+	*addr = (FPW) INTEL_STATUS;
+
+	start = get_timer (0);
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+			*addr = (FPW) INTEL_RESET; /* restore read mode */
+			printf("WSM busy too long, can't get prot status\n");
+			return 1;
+		}
+	}
+
+	/* issue the Read Identifier Codes command */
+	*addr = (FPW) INTEL_READID;
+
+	/* wait at least 35ns (W12) before reading */
+	udelay(1);
+
+	/* Intel example code uses offset of 4 for 8-bit flash */
+	lock_conf_addr = (FPWV *) info->start[sector] + 4;
+	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+	/* put flash back in read mode */
+	*addr = (FPW) INTEL_RESET;
+
+	return ret;
+}
diff --git a/board/o2dnt/o2dnt.c b/board/o2dnt/o2dnt.c
new file mode 100755
index 0000000..81a2700
--- /dev/null
+++ b/board/o2dnt/o2dnt.c
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#define SDRAM_MODE      0x00CD0000
+#define SDRAM_CONTROL   0x504F0000
+#define SDRAM_CONFIG1   0xD2322800
+#define SDRAM_CONFIG2   0x8AD70000
+
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0)
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	else
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+
+	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20))
+		dramsize2 = 0;
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: O2DNT\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x800000) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(CFG_BOOTCS_START | size);
+
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(CFG_BOOTCS_START | size, size);
+	}
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
diff --git a/board/o2dnt/u-boot.lds b/board/o2dnt/u-boot.lds
new file mode 100755
index 0000000..88dc118
--- /dev/null
+++ b/board/o2dnt/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/omap1510inn/Makefile b/board/omap1510inn/Makefile
new file mode 100755
index 0000000..902b24e
--- /dev/null
+++ b/board/omap1510inn/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap1510innovator.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/omap1510inn/config.mk b/board/omap1510inn/config.mk
new file mode 100755
index 0000000..7b24780
--- /dev/null
+++ b/board/omap1510inn/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1510 (ARM925T) cpu
+# see http://www.ti.com/ for more information on Texas Insturments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+TEXT_BASE = 0x11080000
diff --git a/board/omap1510inn/lowlevel_init.S b/board/omap1510inn/lowlevel_init.S
new file mode 100755
index 0000000..1c68e5b
--- /dev/null
+++ b/board/omap1510inn/lowlevel_init.S
@@ -0,0 +1,396 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * -- Some bits of code used from rrload's head_OMAP1510.s --
+ * Copyright (C) 2002 RidgeRun, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE        /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*
+	 * Configure 1510 pins functions to match our board.
+	 */
+	ldr     r0, REG_PULL_DWN_CTRL_0
+	ldr     r1, VAL_PULL_DWN_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_1
+	ldr     r1, VAL_PULL_DWN_CTRL_1
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_2
+	ldr     r1, VAL_PULL_DWN_CTRL_2
+	str     r1, [r0]
+	ldr     r0, REG_PULL_DWN_CTRL_3
+	ldr     r1, VAL_PULL_DWN_CTRL_3
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_4
+	ldr     r1, VAL_FUNC_MUX_CTRL_4
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_5
+	ldr     r1, VAL_FUNC_MUX_CTRL_5
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_6
+	ldr     r1, VAL_FUNC_MUX_CTRL_6
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_7
+	ldr     r1, VAL_FUNC_MUX_CTRL_7
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_8
+	ldr     r1, VAL_FUNC_MUX_CTRL_8
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_9
+	ldr     r1, VAL_FUNC_MUX_CTRL_9
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_A
+	ldr     r1, VAL_FUNC_MUX_CTRL_A
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_B
+	ldr     r1, VAL_FUNC_MUX_CTRL_B
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_C
+	ldr     r1, VAL_FUNC_MUX_CTRL_C
+	str     r1, [r0]
+	ldr     r0, REG_FUNC_MUX_CTRL_D
+	ldr     r1, VAL_FUNC_MUX_CTRL_D
+	str     r1, [r0]
+	ldr     r0, REG_VOLTAGE_CTRL_0
+	ldr     r1, VAL_VOLTAGE_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_TEST_DBG_CTRL_0
+	ldr     r1, VAL_TEST_DBG_CTRL_0
+	str     r1, [r0]
+	ldr     r0, REG_MOD_CONF_CTRL_0
+	ldr     r1, VAL_MOD_CONF_CTRL_0
+	str     r1, [r0]
+
+	/* Move to 1510 mode */
+	ldr     r0, REG_COMP_MODE_CTRL_0
+	ldr     r1, VAL_COMP_MODE_CTRL_0
+	str     r1, [r0]
+
+	/* Set up Traffic Ctlr*/
+	ldr r0, REG_TC_IMIF_PRIO
+	mov r1, #0x0
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFS_PRIO
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFF_PRIO
+	str r1, [r0]
+
+	ldr r0, REG_TC_EMIFS_CONFIG
+	ldr r1, [r0]
+	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
+	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
+	str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
+
+	/* Setup some clock domains */
+	ldr r1, =OMAP1510_CLKS
+	ldr r0, REG_ARM_IDLECT2
+	strh r1, [r0]  /* CLKM, Clock domain control. */
+
+	mov r1, #0x01  /* PER_EN bit */
+	ldr r0, REG_ARM_RSTCT2
+	strh r1, [r0]  /* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable  */
+	/* I supposidly need to enable the dsp clock before switching */
+	mov r1, #0x1000
+	ldr r0, REG_ARM_SYSST
+	strh r1, [r0]
+	mov r0, #0x400
+1:
+	subs r0, r0, #0x1   /* wait for any bubbles to finish */
+	bne 1b
+
+	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
+	ldr r0, REG_ARM_CKCTL
+	strh r1, [r0]
+
+	/* setup DPLL 1 */
+	ldr r1, VAL_DPLL1_CTL
+	ldr r0, REG_DPLL1_CTL
+	strh r1, [r0]
+	ands r1, r1, #0x10  /* Check if PLL is enabled. */
+	beq lock_end        /* Do not look for lock if BYPASS selected */
+2:
+	ldrh r1, [r0]
+	ands r1, r1, #0x01  /* Check the LOCK bit. */
+	beq 2b              /* ...loop until bit goes hi. */
+lock_end:
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	mov r0, #0x10000000                 /* Load physical SDRAM base. */
+	mov r1, pc                          /* Get current execution location. */
+	/* Zero all but top 6 bits of PC, as they alone detect whether an
+	 * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
+	 * valid range for SDRAM on the OMAP 1510/5910.
+	 */
+	and r1, r1, #0xfc000000
+	cmp r1, r0			/* Compare. */
+	beq skip_sdram			/* Skip over EMIF-fast initialization
+					 * if running from SDRAM.
+					 */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800                        /* value should be checked */
+3:
+	subs r3, r3, #0x1                     /* Decrement count */
+	bne 3b
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
+	bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
+	orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
+	orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r3, [r2]                        /* Store the passed value with AR disabled. */
+
+	ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
+	ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
+	str r1, [r2]                        /* Store the passed value.*/
+
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r0, [r2]                        /* Store the passed value. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800
+4:
+	subs r3, r3, #1                     /* Decrement count. */
+	bne 4b
+
+skip_sdram:
+
+	/* slow interface */
+	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+	ldr r0, REG_TC_EMIFS_CS0_CONFIG
+	str r1, [r0] /* Chip Select 0 */
+	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+	ldr r0, REG_TC_EMIFS_CS1_CONFIG
+	str r1, [r0] /* Chip Select 1 */
+	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+	ldr r0, REG_TC_EMIFS_CS2_CONFIG
+	str r1, [r0] /* Chip Select 2 */
+	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+	ldr r0, REG_TC_EMIFS_CS3_CONFIG
+	str r1, [r0] /* Chip Select 3 */
+
+ /* Next, Enable the RS232 Line Drivers in the FPGA. */
+ /* Also, power on the audio CODEC's amplifier here, */
+ /* which will make a noise on the audio output. */
+ /* This is done here instead of in the kernel so there */
+ /* isn't a loud popping noise at the start of each */
+ /* song. */
+ /* Also, disable the CODEC's clocks. */
+ /* omap1510-HelenP1 [specific] */
+
+	ldr r0, REG_FPGA_POWER
+	mov r1, #0
+	ldr r2, REG_FPGA_DIP_SWITCH
+	ldrb r3, [r2]
+	cmp r3, #0x8
+	movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
+	strb r1, [r0]
+	ldr r0, REG_FPGA_AUDIO
+	mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
+	strb r1, [r0]
+
+	/* back to arch calling code */
+	mov	pc, lr
+
+/* the literal pools origin */
+	.ltorg
+
+/* OMAP configuration registers */
+REG_FUNC_MUX_CTRL_0:		/* 32 bits */
+	.word 0xfffe1000
+REG_FUNC_MUX_CTRL_1:		/* 32 bits */
+	.word 0xfffe1004
+REG_FUNC_MUX_CTRL_2:		/* 32 bits */
+	.word 0xfffe1008
+REG_COMP_MODE_CTRL_0:		/* 32 bits */
+	.word 0xfffe100c
+REG_FUNC_MUX_CTRL_3:		/* 32 bits */
+	.word 0xfffe1010
+REG_FUNC_MUX_CTRL_4:		/* 32 bits */
+	.word 0xfffe1014
+REG_FUNC_MUX_CTRL_5:		/* 32 bits */
+	.word 0xfffe1018
+REG_FUNC_MUX_CTRL_6:		/* 32 bits */
+	.word 0xfffe101c
+REG_FUNC_MUX_CTRL_7:		/* 32 bits */
+	.word 0xfffe1020
+REG_FUNC_MUX_CTRL_8:		/* 32 bits */
+	.word 0xfffe1024
+REG_FUNC_MUX_CTRL_9:		/* 32 bits */
+	.word 0xfffe1028
+REG_FUNC_MUX_CTRL_A:		/* 32 bits */
+	.word 0xfffe102C
+REG_FUNC_MUX_CTRL_B:		/* 32 bits */
+	.word 0xfffe1030
+REG_FUNC_MUX_CTRL_C:		/* 32 bits */
+	.word 0xfffe1034
+REG_FUNC_MUX_CTRL_D:		/* 32 bits */
+	.word 0xfffe1038
+REG_PULL_DWN_CTRL_0:		/* 32 bits */
+	.word 0xfffe1040
+REG_PULL_DWN_CTRL_1:		/* 32 bits */
+	.word 0xfffe1044
+REG_PULL_DWN_CTRL_2:		/* 32 bits */
+	.word 0xfffe1048
+REG_PULL_DWN_CTRL_3:		/* 32 bits */
+	.word 0xfffe104c
+REG_VOLTAGE_CTRL_0:		/* 32 bits */
+	.word 0xfffe1060
+REG_TEST_DBG_CTRL_0:		/* 32 bits */
+	.word 0xfffe1070
+REG_MOD_CONF_CTRL_0:		/* 32 bits */
+	.word 0xfffe1080
+REG_TC_IMIF_PRIO:		/* 32 bits */
+	.word 0xfffecc00
+REG_TC_EMIFS_PRIO:		/* 32 bits */
+	.word 0xfffecc04
+REG_TC_EMIFF_PRIO:		/* 32 bits */
+	.word 0xfffecc08
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
+	.word 0xfffecc20
+REG_TC_EMIFF_MRS:		/* 32 bits */
+	.word 0xfffecc24
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+/* identification code register */
+REG_IDCODE:			/* 32 bits */
+	.word 0xfffed404
+
+/* Innovator specific */
+REG_FPGA_LED_DIGIT:		/* 8 bits (not used on Innovator) */
+	.word 0x08000003
+REG_FPGA_POWER:			/* 8 bits */
+	.word 0x08000005
+REG_FPGA_AUDIO:			/* 8 bits (not used on Innovator) */
+	.word 0x0800000c
+REG_FPGA_DIP_SWITCH:		/* 8 bits (not used on Innovator) */
+	.word 0x0800000e
+
+VAL_COMP_MODE_CTRL_0:
+	.word 0x0000eaef
+VAL_FUNC_MUX_CTRL_4:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_5:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_6:
+	.word 0x00000001
+VAL_FUNC_MUX_CTRL_7:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_8:
+	.word 0x10001200
+VAL_FUNC_MUX_CTRL_9:
+	.word 0x01201012
+VAL_FUNC_MUX_CTRL_A:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_B:
+	.word 0x00000248
+VAL_FUNC_MUX_CTRL_C:
+	.word 0x09000000
+VAL_FUNC_MUX_CTRL_D:
+	.word 0x00000000
+VAL_PULL_DWN_CTRL_0:
+	.word 0x11a10000
+VAL_PULL_DWN_CTRL_1:
+	.word 0x2e047fff
+VAL_PULL_DWN_CTRL_2:
+	.word 0xffd603a6
+VAL_PULL_DWN_CTRL_3:
+	.word 0x00003e03
+VAL_VOLTAGE_CTRL_0:
+	.word 0x00000007
+VAL_TEST_DBG_CTRL_0:
+	/*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
+	 *   This slows down internal SRAM accesses.
+	 */
+	.word 0x00000007
+VAL_MOD_CONF_CTRL_0:
+	.word 0x0b000008
+VAL_ARM_CKCTL:
+	.word 0x010f
+VAL_DPLL1_CTL:
+	.word 0x2710
+VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
+	.word 0x00001149
+VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
+	.word 0x00004158
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x0000f559
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00003331
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
diff --git a/board/omap1510inn/omap1510innovator.c b/board/omap1510inn/omap1510innovator.c
new file mode 100755
index 0000000..f037f42
--- /dev/null
+++ b/board/omap1510inn/omap1510innovator.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+static void flash__init (void);
+static void ether__init (void);
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of OMAP 1510-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+/* kk - this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
+	/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
+
+	/* setup gpio direction to match board (no floats!) */
+	/**gdir = 0xCFF9; */
+	/**mdir = 0x103F; */
+
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void flash__init (void)
+{
+#define CS0_CHIP_SELECT_REG 0xfffecc10
+#define CS3_CHIP_SELECT_REG 0xfffecc1c
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+
+	{
+		unsigned int regval;
+
+		regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+		regval = regval | 0x0001;	/* Turn off write protection for flash devices. */
+		if (regval & 0x0002) {
+			regval = regval & 0xfffd;	/* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
+			/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
+			/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
+			/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
+		}
+		*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+	}
+}
+
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0800000b
+	/* take the Ethernet controller out of reset and wait
+	 * for the EEPROM load to complete.
+	 */
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff --git a/board/omap1510inn/u-boot.lds b/board/omap1510inn/u-boot.lds
new file mode 100755
index 0000000..b6d1619
--- /dev/null
+++ b/board/omap1510inn/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm925t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/omap1610inn/Makefile b/board/omap1610inn/Makefile
new file mode 100755
index 0000000..4560102
--- /dev/null
+++ b/board/omap1610inn/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap1610innovator.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/omap1610inn/config.mk b/board/omap1610inn/config.mk
new file mode 100755
index 0000000..80976ef
--- /dev/null
+++ b/board/omap1610inn/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Innovator board with OMAP1610 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+TEXT_BASE = 0x11080000
diff --git a/board/omap1610inn/flash.c b/board/omap1610inn/flash.c
new file mode 100755
index 0000000..c8e4c9e
--- /dev/null
+++ b/board/omap1610inn/flash.c
@@ -0,0 +1,493 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	   */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+void flash_unlock(flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]);
+			flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]);
+			/* to reset the lock bit */
+			flash_unlock(&flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_unlock(flash_info_t * info)
+{
+	int j;
+	for (j=2;j<CFG_MAX_FLASH_SECT;j++){
+	FPWV *addr = (FPWV *) (info->start[j]);
+	flash_unprotect_sectors (addr);
+	*addr = (FPW) 0x00500050;/* clear status register */
+	*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "	   ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash	*/
+	}
+
+	mb ();
+	value = addr[1];	/* device ID	    */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.	*/
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/omap1610inn/lowlevel_init.S b/board/omap1610inn/lowlevel_init.S
new file mode 100755
index 0000000..eaf1742
--- /dev/null
+++ b/board/omap1610inn/lowlevel_init.S
@@ -0,0 +1,452 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1, #0xffffffff
+	ldr	r0, =REG_IHL1_MIR
+	str	r1, [r0]
+	ldr	r0, =REG_IHL2_MIR
+	str	r1, [r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)  		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+#ifdef CONFIG_CS_AUTOBOOT		/* do the setup depending on boot mode */
+	ldr	r0, CONF_STATUS
+	ldr	r1, [r0]
+	tst	r1, #0x02
+	beq	disable_wd		/* booting from RAM, skip setup */
+#endif
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x0000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+ 	 *------------------------------------------------------*/
+disable_wd:
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Load physical SDRAM base. */
+	mov 	r0, 	#0x10000000
+	/* Get current execution location. */
+	mov 	r1, 	pc
+	/* Compare. */
+	cmp 	r1, 	r0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bge 	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne 	3b
+
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+
+	/* mobile ddr operation */
+	ldr	r0,	REG_SDRAM_OPERATION
+	mov	r2,	#07
+	str	r2,	[r0]
+
+	/* config register */
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	/* manual command register */
+	ldr	r0,	REG_SDRAM_MANUAL_CMD
+	/* issue set cke high */
+	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
+	str	r1,	[r0]
+	/* issue nop */
+	mov	r1,	#CMD_SDRAM_NOP
+	str	r1,	[r0]
+
+	mov	r2,	#0x0100
+waitMDDR1:
+	subs	r2,	r2,	 #1
+	bne	waitMDDR1	/* delay loop */
+
+	/* issue precharge */
+	mov	r1,	#CMD_SDRAM_PRECHARGE
+	str	r1,	[r0]
+
+	/* issue autorefresh x 2 */
+	mov	r1,	#CMD_SDRAM_AUTOREFRESH
+	str	r1,	[r0]
+	str	r1,	[r0]
+
+	/* mrs register ddr mobile */
+	ldr	r0,	REG_SDRAM_MRS
+	mov	r1,	#0x33
+	str	r1,	[r0]
+
+	/* emrs1 low-power register */
+	ldr	r0,	REG_SDRAM_EMRS1
+	/* self refresh on all banks */
+	mov	r1,	#0
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_URD_CONTROL
+	ldr	r1,	DLL_URD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_LRD_CONTROL
+	ldr	r1,	DLL_LRD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_WRT_CONTROL
+	ldr	r1,	DLL_WRT_CONTROL_VAL
+	str	r1,	[r0]
+
+	/* delay loop */
+	mov	r2,	#0x0100
+waitMDDR2:
+	subs	r2,	r2,	#1
+	bne	waitMDDR2
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov	r3,	#0x1800
+4:
+	subs	r3,	r3,	#1	/* Decrement count. */
+	bne	4b
+	b	common_tc
+
+skip_sdram:
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+#ifdef CONFIG_H2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+#ifdef CONFIG_CS_AUTOBOOT
+CONF_STATUS:
+	.word 0xfffe1130	/* 32 bits */
+#endif
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+	.word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+	.word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+	.word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+	.word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+	.word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+	.word 0x03f00002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+	.word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+	.word 0x00800002
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+	.word 0xfffecccc
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec600
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+	.word 0x001200f4
+
+DLL_LRD_CONTROL_VAL:
+	.word 0x00800002
+
+VAL_ARM_CKCTL:
+	.word 0x3000
+VAL_DPLL1_CTL:
+	.word 0x2830
+
+#ifdef CONFIG_INNOVATOROMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00001131
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+/* command values */
+.equ CMD_SDRAM_NOP,		0x00000000
+.equ CMD_SDRAM_PRECHARGE,	0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007
diff --git a/board/omap1610inn/omap1610innovator.c b/board/omap1610inn/omap1610innovator.c
new file mode 100755
index 0000000..7842518
--- /dev/null
+++ b/board/omap1610inn/omap1610innovator.c
@@ -0,0 +1,306 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+#ifdef CONFIG_CS_AUTOBOOT
+unsigned long omap_flash_base;
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (machine_is_omap_h2())
+		gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2;
+	else if (machine_is_omap_innovator())
+		gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
+	else
+		gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+	peripheral_power_enable ();
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+	unsigned int regval;
+
+#ifdef CONFIG_CS_AUTOBOOT
+	 /* Check swapping of CS0 and CS3, set flash base accordingly */
+	omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
+					PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
+#endif
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	  		   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0400030b
+
+#ifdef CONFIG_H2_OMAP1610
+	#define LAN_RESET_REGISTER 0x0400001c
+
+	/* The debug board on which the lan chip resides may not be powered
+	 * ON at the same time as the OMAP chip. So wait in a loop until the
+	 * lan reset register (on the debug board) is available (powered on)
+	 * and reset the lan chip.
+	 */
+
+	*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
+		udelay (3);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
+
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+		udelay (3);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
+#endif
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+ 			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* setup for UART1 */
+	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
+	/* setup for UART2 */
+	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x08000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
+	/*setup mux for UART3 */
+	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
+	*MuxConfReg &= ~0x0000003e;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
+	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
+	/*  hardware will actually use TX and RTS based on bit 25 in  */
+	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!  */
+	*MuxConfReg |= 0x00201000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
+	/* setup for UART2 */
+	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
+	/*  hardware will actually use TX and RTS based on bit 24 in  */
+	/*  FUNC_MUX_CTRL_0. */
+	*MuxConfReg |= 0x09000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
+	*MuxConfReg = 0x00000000;
+	/* mux setup for SD/MMC driver */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
+	*MuxConfReg &= 0xFFFE0FFF;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 13 for MMC2 XOR_CLK */
+	*MuxConfReg &= ~(0x00002000);
+	/* bit 29 for UART 1 */
+	*MuxConfReg &= ~(0x00002000);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
+	*MuxConfReg |= 0x000C0000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
+	*MuxConfReg &= ~(0x00000070);
+	*MuxConfReg &= ~(0x00000008);
+	*MuxConfReg |= 0x00000003;
+	*MuxConfReg |= 0x00000180;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 17, software controls VBUS */
+	*MuxConfReg &= ~(0x00020000);
+	/* Enable USB 48 and 12M clocks */
+	*MuxConfReg |= 0x00000200;
+	*MuxConfReg &= ~(0x00000180);
+	/*2.75V for MMCSDIO1 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
+	*MuxConfReg = 0x00001FE7;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	/* Turn on UART2 48 MHZ clock */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	*MuxConfReg |= 0x40000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
+	/* setup for USB VBus detection OMAP161x */
+	*MuxConfReg |= 0x00040000;	/* bit 18 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	/* PullUps for SD/MMC driver */
+	*MuxConfReg |= ~(0xFFFE0FFF);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
+	*MuxConfReg = COMP_MODE_ENABLE;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)
+
+	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
+}
diff --git a/board/omap1610inn/u-boot.lds b/board/omap1610inn/u-boot.lds
new file mode 100755
index 0000000..710b2a2
--- /dev/null
+++ b/board/omap1610inn/u-boot.lds
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile
new file mode 100755
index 0000000..ed47868
--- /dev/null
+++ b/board/omap2420h4/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap2420h4.o mem.o sys_info.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/omap2420h4/config.mk b/board/omap2420h4/config.mk
new file mode 100755
index 0000000..3edcde0
--- /dev/null
+++ b/board/omap2420h4/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+#
+# TI H4 board with OMAP2420 (ARM1136) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
+# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1) ES2 will be configurable
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
+
+# Used with full SRAM boot.
+# This is either with a GP system or a signed boot image.
+# easiest, and safest way to go if you can.
+#TEXT_BASE = 0x40270000
+
+
+# Handy to get symbols to debug ROM version.
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0x08000000
+#TEXT_BASE = 0x04000000
diff --git a/board/omap2420h4/flash.c b/board/omap2420h4/flash.c
new file mode 100755
index 0000000..d5e106a
--- /dev/null
+++ b/board/omap2420h4/flash.c
@@ -0,0 +1,537 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sizes.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	SZ_128K
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+# define FLASH_PORT_WIDTH		ushort
+# define FLASH_PORT_WIDTHV		vu_short
+# define SWAP(x)			__swab16(x)
+#else
+# define FLASH_PORT_WIDTH		ulong
+# define FLASH_PORT_WIDTHV		vu_long
+# define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, SZ_32K},		/* 4 * 32kBytes sectors */
+	{255, SZ_128K},		/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+void flash_unlock(flash_info_t * info, int bank);
+int flash_probe(void);
+
+/*-----------------------------------------------------------------------
+ */
+
+/* see if flash is ok */
+int flash_probe(void)
+{
+	return(flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[0]));
+}
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			/* to reset the lock bit */
+			flash_unlock(&flash_info[i],i);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			/* to reset the lock bit */
+			flash_unlock(&flash_info[i],i);
+			break;
+
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+#ifdef CFG_ENV_IS_IN_FLASH
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+				   CFG_FLASH_BASE,
+				   CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+				   CFG_ENV_ADDR,
+				   CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_unlock(flash_info_t * info, int bank)
+{
+	int j;
+	if (!bank)
+		j=2;	/* leave 0,1 locked for boot bank */
+	else
+		j=0;	/* get the whole bank for #2 */
+
+	for (;j<CFG_MAX_FLASH_SECT;j++) {
+		FPWV *addr = (FPWV *) (info->start[j]);
+		if (addr == NULL) {
+			printf("Warning Flash probe failed\n");
+			break;
+		}
+		flash_unprotect_sectors (addr);
+		*addr = (FPW) 0x00500050;/* clear status register */
+		*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	volatile int r;	 /* gcc 3.4.0-1 strangeness, need to follow up.*/
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 254) { /* 255,256,257,258 */
+				r=i;
+				info->start[i] = base + (((r-(int)255) * SZ_32K) + (255*PHYS_FLASH_SECT_SIZE));
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+				info->start[i], info->protect[i] ? " (RO)" : "	   ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+	/* mb();  this one makes ARM11 err go away, but I want it :) as a guide to problems */
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0] & 0xFF;	/* just looking for 89 (8989 is hw pat)*/
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return(0);		   /* no or unknown flash	*/
+	}
+
+	mb ();
+	value = addr[1];	/* device ID */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):	 /* 880D */
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;	/*0-258*/
+		info->size = SZ_32M;
+		break;			/* => 32 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return(info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+#ifdef CONFIG_USE_IRQ
+	int iflag;
+#endif
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+#ifdef CONFIG_USE_IRQ
+	/* Disable interrupts which might cause a timeout here */
+	iflag = disable_interrupts ();
+#endif
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+					 *addr) & (FPW) 0x00800080) !=
+				   (FPW) 0x00800080) {
+				if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.	*/
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+#ifdef CONFIG_USE_IRQ
+	if (iflag)
+		enable_interrupts();
+#endif
+
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return(rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return(rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return(0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return(write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+#ifdef CONFIG_USE_IRQ
+	int iflag;
+#endif
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return(2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+#ifdef CONFIG_USE_IRQ
+	iflag = disable_interrupts ();
+#endif
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return(1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+#ifdef CONFIG_USE_IRQ
+	if (iflag)
+		enable_interrupts();
+#endif
+
+	return(0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/omap2420h4/lowlevel_init.S b/board/omap2420h4/lowlevel_init.S
new file mode 100755
index 0000000..9752fc4
--- /dev/null
+++ b/board/omap2420h4/lowlevel_init.S
@@ -0,0 +1,185 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+	/* Copy DPLL code into SRAM */
+	adr	r0, go_to_speed		/* get addr of clock setting code */
+	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
+	mov	r1, r1			/* r1 <- dest address (passed in) */
+	add	r2, r2, r0		/* r2 <- source end address */
+next2:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	bne	next2
+	mov	pc, lr			/* back to caller */
+
+/* ****************************************************************************
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *		 -executed from SRAM.
+ *  R0 = PRCM_CLKCFG_CTRL - addr of valid reg
+ *  R1 = CM_CLKEN_PLL - addr dpll ctlr reg
+ *  R2 = dpll value
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+	sub	sp, sp, #0x4 /* get some stack space */
+	str	r4, [sp]     /* save r4's value */
+
+	/* move into fast relock bypass */
+	ldr	r8, pll_ctl_add
+	mov	r4, #0x2
+	str	r4, [r8]
+	ldr	r4, pll_stat
+block:
+	ldr	r8, [r4]	/* wait for bypass to take effect */
+	and	r8, r8, #0x3
+	cmp	r8, #0x1
+	bne	block
+
+	/* set new dpll dividers _after_ in bypass */
+	ldr	r4, pll_div_add
+	ldr	r8, pll_div_val
+	str	r8, [r4]
+
+	/* now prepare GPMC (flash) for new dpll speed */
+	/* flash needs to be stable when we jump back to it */
+	ldr	r4, cfg3_0_addr
+	ldr	r8, cfg3_0_val
+	str	r8, [r4]
+	ldr	r4, cfg4_0_addr
+	ldr	r8, cfg4_0_val
+	str	r8, [r4]
+	ldr	r4, cfg1_0_addr
+	ldr	r8, [r4]
+	orr	r8, r8, #0x3	 /* up gpmc divider */
+	str	r8, [r4]
+
+	/* setup to 2x loop though code.  The first loop pre-loads the
+	 * icache, the 2nd commits the prcm config, and locks the dpll
+	 */
+	mov	r4, #0x1000	 /* spin spin spin */
+	mov	r8, #0x4	 /* first pass condition & set registers */
+	cmp	r8, #0x4
+2:
+	ldrne	r8, [r3]	 /* DPLL lock check */
+	and	r8, r8, #0x7
+	cmp	r8, #0x2
+	beq	4f
+3:
+	subeq	r8, r8, #0x1
+	streq	r8, [r0]	 /* commit dividers (2nd time) */
+	nop
+lloop1:
+	sub	r4, r4, #0x1	/* Loop currently necessary else bad jumps */
+	nop
+	cmp	r4, #0x0
+	bne	lloop1
+	mov	r4, #0x40000
+	cmp	r8, #0x1
+	nop
+	streq	r2, [r1]	/* lock dpll (2nd time) */
+	nop
+lloop2:
+	sub	r4, r4, #0x1	/* loop currently necessary else bad jumps */
+	nop
+	cmp	r4, #0x0
+	bne	lloop2
+	mov	r4, #0x40000
+	cmp	r8, #0x1
+	nop
+	ldreq	r8, [r3]	 /* get lock condition for dpll */
+	cmp	r8, #0x4	 /* first time though? */
+	bne	2b
+	moveq	r8, #0x2	 /* set to dpll check condition. */
+	beq	3b		 /* if condition not true branch */
+4:
+	ldr	r4, [sp]
+	add	sp, sp, #0x4	 /* return stack space */
+	mov	pc, lr		 /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+cfg3_0_addr:
+    .word  GPMC_CONFIG3_0
+cfg3_0_val:
+    .word  H4_24XX_GPMC_CONFIG3_0
+cfg4_0_addr:
+    .word  GPMC_CONFIG4_0
+cfg4_0_val:
+    .word  H4_24XX_GPMC_CONFIG4_0
+cfg1_0_addr:
+    .word  GPMC_CONFIG1_0
+pll_ctl_add:
+    .word CM_CLKEN_PLL
+pll_stat:
+    .word CM_IDLEST_CKGEN
+pll_div_add:
+    .word CM_CLKSEL1_PLL
+pll_div_val:
+    .word DPLL_VAL	/* DPLL setting (300MHz default) */
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp,	SRAM_STACK
+	str	ip,	[sp]	/* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+	bl	s_init		/* go setup pll,mux,memory */
+	ldr	ip,	[sp]	/* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* map interrupt controller */
+	ldr	r0,	VAL_INTH_SETUP
+	mcr	p15, 0, r0, c15, c2, 4
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_CONTROL_STATUS:
+	.word CONTROL_STATUS
+VAL_INTH_SETUP:
+	.word PERIFERAL_PORT_BASE
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c
new file mode 100755
index 0000000..62eb6e3
--- /dev/null
+++ b/board/omap2420h4/mem.c
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+
+/************************************************************
+ * sdelay() - simple spin loop.  Will be constant time as
+ *  its generally used in 12MHz bypass conditions only.  This
+ *  is necessary until timers are accessible.
+ *
+ *  not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*********************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
+ *   -- called from SRAM, or Flash (using temp SRAM stack).
+ *********************************************************************************/
+void prcm_init(void)
+{
+	u32 div;
+	void (*f_lock_pll) (u32, u32, u32, u32);
+	extern void *_end_vect, *_start;
+
+	f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE);
+
+	__raw_writel(0, CM_FCLKEN1_CORE);	   /* stop all clocks to reduce ringing */
+	__raw_writel(0, CM_FCLKEN2_CORE);	   /* may not be necessary */
+	__raw_writel(0, CM_ICLKEN1_CORE);
+	__raw_writel(0, CM_ICLKEN2_CORE);
+
+	__raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);	/* set DPLL out */
+	__raw_writel(MPU_DIV, CM_CLKSEL_MPU);	/* set MPU divider */
+	__raw_writel(DSP_DIV, CM_CLKSEL_DSP);	/* set dsp and iva dividers */
+	__raw_writel(GFX_DIV, CM_CLKSEL_GFX);	/* set gfx dividers */
+
+	div = BUS_DIV;
+	__raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/Vlnc/SSi dividers */
+	sdelay(1000);
+
+	if(running_in_sram()){
+		/* If running fully from SRAM this is OK.  The Flash bus drops out for just a little.
+		* but then comes back.  If running from Flash this sequence kills you, thus you need
+		* to run it using CONFIG_PARTIAL_SRAM.
+		*/
+		__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
+		wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
+		sdelay(1000);
+		/* set clock selection and dpll dividers. */
+		__raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);	 /* set pll for target rate */
+		__raw_writel(COMMIT_DIVIDERS, PRCM_CLKCFG_CTRL); /* commit dividers */
+		sdelay(10000);
+		__raw_writel(DPLL_LOCK, CM_CLKEN_PLL); /* enable dpll */
+		sdelay(10000);
+		wait_on_value(BIT0|BIT1, BIT1, CM_IDLEST_CKGEN, LDELAY);  /*wait for dpll lock */
+	}else if(running_in_flash()){
+		/* if running from flash, need to jump to small relocated code area in SRAM.
+		 * This is the only safe spot to do configurations from.
+		 */
+		(*f_lock_pll)(PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, CM_IDLEST_CKGEN);
+	}
+
+	__raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL);   /* enable apll */
+	wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);	/* wait for apll lock */
+	sdelay(1000);
+}
+
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ *  command line mem=xyz use all memory with out discontigious support
+ *  compiled in.  Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(SDRC_CS0_OSET);
+	size /= SZ_32M;  /* find size to offset CS1 */
+	a_add_high = (size & 3) << 8;   /* set up low field */
+	a_add_low = (size & 0x3C) >> 2; /* set up high field */
+	__raw_writel((a_add_high|a_add_low),SDRC_CS_CFG);
+
+}
+
+/********************************************************
+ *  mem_ok() - test used to see if timings are correct
+ *             for a part. Helps in gussing which part
+ *             we are currently using.
+ *******************************************************/
+u32 mem_ok(void)
+{
+	u32 val1, val2;
+	u32 pattern = 0x12345678;
+
+	__raw_writel(0x0,OMAP2420_SDRC_CS0+0x400);   /* clear pos A */
+	__raw_writel(pattern, OMAP2420_SDRC_CS0);    /* pattern to pos B */
+	__raw_writel(0x0,OMAP2420_SDRC_CS0+4);       /* remove pattern off the bus */
+	val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */
+	val2 = __raw_readl(OMAP2420_SDRC_CS0);       /* get val2 */
+
+	if ((val1 != 0) || (val2 != pattern))        /* see if pos A value changed*/
+		return(0);
+	else
+		return(1);
+}
+
+
+/********************************************************
+ *  sdrc_init() - init the sdrc chip selects CS0 and CS1
+ *  - early init routines, called from flash or
+ *  SRAM.
+ *******************************************************/
+void sdrc_init(void)
+{
+	#define EARLY_INIT 1
+	do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);  /* only init up first bank here */
+}
+
+/*************************************************************************
+ * do_sdrc_init(): initialize the SDRAM for use.
+ *  -called from low level code with stack only.
+ *  -code sets up SDRAM timing and muxing for 2422 or 2420.
+ *  -optimal settings can be placed here, or redone after i2c
+ *      inspection of board info
+ *
+ *  This is a bit ugly, but should handle all memory moduels
+ *   used with the H4. The first time though this code from s_init()
+ *   we configure the first chip select.  Later on we come back and
+ *   will configure the 2nd chip select if it exists.
+ *
+ **************************************************************************/
+void do_sdrc_init(u32 offset, u32 early)
+{
+	u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype;
+	sdrc_data_t *sdata;	 /* do not change type */
+	u32 a, b, r;
+
+	static const sdrc_data_t sdrc_2422 =
+	{
+		H4_2422_SDRC_SHARING, H4_2422_SDRC_MDCFG_0_DDR, 0 , H4_2422_SDRC_ACTIM_CTRLA_0,
+		H4_2422_SDRC_ACTIM_CTRLB_0, H4_2422_SDRC_RFR_CTRL, H4_2422_SDRC_MR_0_DDR,
+		0, H4_2422_SDRC_DLLAB_CTRL
+	};
+	static const sdrc_data_t sdrc_2420 =
+	{
+		H4_2420_SDRC_SHARING, H4_2420_SDRC_MDCFG_0_DDR, H4_2420_SDRC_MDCFG_0_SDR,
+		H4_2420_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0,
+		H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, H4_2420_SDRC_MR_0_SDR,
+		H4_2420_SDRC_DLLAB_CTRL
+	};
+
+	if (offset == SDRC_CS0_OSET)
+		cs0 = common = 1;  /* int regs shared between both chip select */
+
+	cpu = get_cpu_type();
+	rev = get_cpu_rev();
+
+	/* warning generated, though code generation is correct. this may bite later,
+	 * but is ok for now. there is only so much C code you can do on stack only
+	 * operation.
+	 */
+	if (cpu == CPU_2422){
+		sdata = (sdrc_data_t *)&sdrc_2422;
+		pass_type = STACKED;
+	} else{
+		sdata = (sdrc_data_t *)&sdrc_2420;
+		pass_type = IP_DDR;
+	}
+
+	__asm__ __volatile__("": : :"memory");  /* limit compiler scope */
+
+	/* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx.
+	 * If we are running in flash prior to relocation and we use data
+	 * here which is not pc relative we need to get the address correct.
+	 * We need to find the current flash mapping to dress up the initial
+	 * pointer load.  As long as this is const data we should be ok.
+	 */
+	if((early) && running_in_flash()){
+		sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
+		/* NOR internal boot offset is 0x4000 from xloader signature */
+		if(running_from_internal_boot())
+			sdata = (sdrc_data_t *)((u32)sdata + 0x4000);
+	}
+
+	if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) {
+		if(mtype == DDR_COMBO){
+			pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */
+			pass_type = COMBO_DDR; /* CS1 config */
+			__raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER);
+		}
+		if(rev != CPU_2420_2422_ES1)	/* for es2 and above smooth things out */
+			make_cs1_contiguous();
+	}
+
+next_mem_type:
+	if (common) {	/* do a SDRC reset between types to clear regs*/
+		__raw_writel(SOFTRESET, SDRC_SYSCONFIG);	/* reset sdrc */
+		wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */
+		__raw_writel(0, SDRC_SYSCONFIG);		/* clear soft reset */
+		__raw_writel(sdata->sdrc_sharing, SDRC_SHARING);
+#ifdef POWER_SAVE
+		__raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG);
+		__raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING);
+		__raw_writel((__raw_readl(SDRC_POWER)|BIT6), SDRC_POWER);
+#endif
+	}
+
+	if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */
+		__raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset);
+	else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */
+		__raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset);
+	} else if (pass_type == IP_SDR){ /* ip sdr-CS0 */
+		__raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset);
+	}
+
+	a = sdata->sdrc_actim_ctrla_0;
+	b = sdata->sdrc_actim_ctrlb_0;
+	r = sdata->sdrc_dllab_ctrl;
+
+	/* work around ES1 DDR issues */
+	if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){
+		a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1;
+		b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1;
+		r = H4_242x_SDRC_RFR_CTRL_ES1;
+ 	}
+
+	if (cs0) {
+		__raw_writel(a, SDRC_ACTIM_CTRLA_0);
+		__raw_writel(b, SDRC_ACTIM_CTRLB_0);
+	} else {
+		__raw_writel(a, SDRC_ACTIM_CTRLA_1);
+		__raw_writel(b, SDRC_ACTIM_CTRLB_1);
+	}
+	__raw_writel(r, SDRC_RFR_CTRL+offset);
+
+	/* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */
+	__raw_writel(CMD_NOP, SDRC_MANUAL_0+offset);
+	sdelay(5000);  /* susposed to be 100us per design spec for mddr/msdr */
+	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0+offset);
+	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
+	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0+offset);
+
+	/*
+	 * CSx SDRC Mode Register
+	 * Burst length = (4 - DDR) (2-SDR)
+	 * Serial mode
+	 * CAS latency = x
+	 */
+	if(pass_type == IP_SDR)
+		__raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0+offset);
+	else
+		__raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset);
+
+	/* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/
+	if (rev == CPU_2420_2422_ES1){
+		dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */
+		__raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7)
+			,SMS_CLASS_ARB0);/* enable bust complete for lcd */
+	}
+	else
+		dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */
+
+	/* enable & load up DLL with good value for 75MHz, and set phase to 90
+	 * ES1 recommends 90 phase, ES2 recommends 72 phase.
+	 */
+	if (common && (pass_type != IP_SDR)) {
+		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL);
+		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL);
+		__raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL);
+		__raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL);
+	}
+	sdelay(90000);
+
+	if(mem_ok())
+		return; /* STACKED, other configued type */
+	++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */
+	goto next_mem_type;
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+	u32 mux=0, mtype, mwidth, rev, tval;
+
+	rev  = get_cpu_rev();
+	if (rev == CPU_2420_2422_ES1)
+		tval = 1;
+	else
+		tval = 0;  /* disable bit switched meaning */
+
+	/* global settings */
+	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
+	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
+	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */
+#ifdef CFG_NAND_BOOT
+	__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */
+#else
+	__raw_writel(0x111, GPMC_CONFIG);	/* set nWP, disable limited addr */
+#endif
+
+	/* discover bus connection from sysboot */
+	if (is_gpmc_muxed() == GPMC_MUXED)
+		mux = BIT9;
+	mtype = get_gpmc0_type();
+	mwidth = get_gpmc0_width();
+
+	/* setup cs0 */
+	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
+	sdelay(1000);
+
+#ifdef CFG_NAND_BOOT
+	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0);
+#else
+	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
+#endif
+
+#ifdef PRCM_CONFIG_III
+	__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+#endif
+	__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
+	__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
+#ifdef PRCM_CONFIG_III
+	__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+	__raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
+#endif
+	__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
+	sdelay(2000);
+
+	/* setup cs1 */
+	__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
+	sdelay(1000);
+	__raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
+	__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
+	sdelay(2000);
+}
diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c
new file mode 100755
index 0000000..6ae1a49
--- /dev/null
+++ b/board/omap2420h4/omap2420h4.c
@@ -0,0 +1,868 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/mem.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+#endif
+
+ void wait_for_command_complete(unsigned int wd_base);
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRM, finish GPMC */
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;		/* board id for linux */
+	gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);	/* adress of boot parameters */
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ *  general use.
+ ***********************************************************/
+void try_unlock_sram(void)
+{
+	/* if GP device unlock device SRAM for general use */
+	if (get_device_type() == GP_DEVICE) {
+		__raw_writel(0xFF, A_REQINFOPERM0);
+		__raw_writel(0xCFDE, A_READPERM0);
+		__raw_writel(0xCFDE, A_WRITEPERM0);
+	}
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with sram stack.
+ **********************************************************/
+void s_init(void)
+{
+	int in_sdram = running_in_sdram();
+
+	watchdog_init();
+	set_muxconf_regs();
+	delay(100);
+	try_unlock_sram();
+
+	if(!in_sdram)
+		prcm_init();
+
+	peripheral_enable();
+	icache_enable();
+	if (!in_sdram)
+		sdrc_init();
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r (void)
+{
+	ether_init(); /* better done here so timers are init'ed */
+	return(0);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+	/* There are 4 watch dogs.  1 secure, and 3 general purpose.
+	* The ROM takes care of the secure one. Of the 3 GP ones,
+	* 1 can reset us directly, the other 2 only generate MPU interrupts.
+	*/
+	__raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
+	wait_for_command_complete(WD2_BASE);
+	__raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
+
+#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
+	__raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
+	wait_for_command_complete(WD3_BASE);
+	__raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
+
+	__raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
+	wait_for_command_complete(WD4_BASE);
+	__raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
+#endif
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+	int pending = 1;
+	do {
+		pending = __raw_readl(wd_base+WWPS);
+	} while (pending);
+}
+
+/*******************************************************************
+ * Routine:ether_init
+ * Description: take the Ethernet controller out of reset and wait
+ *  		   for the EEPROM load to complete.
+ ******************************************************************/
+void ether_init (void)
+{
+#ifdef CONFIG_DRIVER_LAN91C96
+	int cnt = 20;
+
+	__raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
+
+	__raw_writew(0x0, LAN_RESET_REGISTER);
+	do {
+		__raw_writew(0x1, LAN_RESET_REGISTER);
+		udelay (100);
+		if (cnt == 0)
+			goto h4reset_err_out;
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
+
+	cnt = 20;
+
+	do {
+		__raw_writew(0x0, LAN_RESET_REGISTER);
+		udelay (100);
+		if (cnt == 0)
+			goto h4reset_err_out;
+		--cnt;
+	} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
+	udelay (1000);
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (1000);
+
+	h4reset_err_out:
+	return;
+#endif
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0=0,size1=0;
+	u32 mtype, btype, rev, cpu;
+	u8 chg_on = 0x5; /* enable charge of back up battery */
+	u8 vmode_on = 0x8C;
+	#define NOT_EARLY 0
+
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
+
+	btype = get_board_type();
+	mtype = get_mem_type();
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+
+	display_board_info(btype);
+	if (btype == BOARD_H4_MENELAUS){
+		update_mux(btype,mtype); /* combo part on menelaus */
+		i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
+		i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
+	}
+
+	if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
+		do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);	/* init other chip select */
+	}
+	size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+	size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	else /* ES2 and above can remap at 32MB granularity */
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ *              specific to the hardware
+ *********************************************************/
+void set_muxconf_regs (void)
+{
+	muxSetupSDRC();
+	muxSetupGPMC();
+	muxSetupUsb0();
+	muxSetupUart3();
+	muxSetupI2C1();
+	muxSetupUART1();
+	muxSetupLCD();
+	muxSetupCamera();
+	muxSetupMMCSD();
+	muxSetupTouchScreen();
+	muxSetupHDQ();
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+void peripheral_enable(void)
+{
+	unsigned int v, if_clks=0, func_clks=0;
+
+	/* Enable GP2 timer.*/
+	if_clks |= BIT4;
+	func_clks |= BIT4;
+	v = __raw_readl(CM_CLKSEL2_CORE) | 0x4;	/* Sys_clk input OMAP2420_GPT2 */
+	__raw_writel(v, CM_CLKSEL2_CORE);
+	__raw_writel(0x1, CM_CLKSEL_WKUP);
+
+#ifdef CFG_NS16550
+	/* Enable UART1 clock */
+	func_clks |= BIT21;
+	if_clks |= BIT21;
+#endif
+	v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;	/* Interface clocks on */
+	__raw_writel(v,CM_ICLKEN1_CORE );
+	v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
+	__raw_writel(v, CM_FCLKEN1_CORE);
+	delay(1000);
+
+#ifndef KERNEL_UPDATED
+	{
+#define V1 0xffffffff
+#define V2 0x00000007
+
+		__raw_writel(V1, CM_FCLKEN1_CORE);
+		__raw_writel(V2, CM_FCLKEN2_CORE);
+		__raw_writel(V1, CM_ICLKEN1_CORE);
+		__raw_writel(V1, CM_ICLKEN2_CORE);
+	}
+#endif
+}
+
+/****************************************
+ * Routine: muxSetupUsb0   (ostboot)
+ * Description: Setup usb muxing
+ *****************************************/
+void muxSetupUsb0(void)
+{
+	volatile uint8   *MuxConfigReg;
+	volatile uint32  *otgCtrlReg;
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	/* setup for USB VBus detection */
+	otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
+	*otgCtrlReg |= 0x00040000; /* bit 18 */
+}
+
+/****************************************
+ * Routine: muxSetupUart3   (ostboot)
+ * Description: Setup uart3 muxing
+ *****************************************/
+void muxSetupUart3(void)
+{
+	volatile uint8 *MuxConfigReg;
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
+	*MuxConfigReg &= (uint8)(~0x1F);
+
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
+	*MuxConfigReg &= (uint8)(~0x1F);
+}
+
+/****************************************
+ * Routine: muxSetupI2C1   (ostboot)
+ * Description: Setup i2c muxing
+ *****************************************/
+void muxSetupI2C1(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* I2C1 Clock pin configuration, PIN = M19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* I2C1 Data pin configuration, PIN = L15 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* Pull-up required on data line */
+	/* external pull-up already present. */
+	/* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
+}
+
+/****************************************
+ * Routine: muxSetupUART1  (ostboot)
+ * Description: Set up uart1 muxing
+ *****************************************/
+void muxSetupUART1(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* UART1_CTS pin configuration, PIN = D21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* UART1_RTS pin configuration, PIN = H21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* UART1_TX pin configuration, PIN = L20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* UART1_RX pin configuration, PIN = T21 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupLCD   (ostboot)
+ * Description: Setup lcd muxing
+ *****************************************/
+void muxSetupLCD(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* LCD_D0 pin configuration, PIN = Y7  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D1 pin configuration, PIN = P10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D2 pin configuration, PIN = V8  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D3 pin configuration, PIN = Y8  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D4 pin configuration, PIN = W8  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D5 pin configuration, PIN = R10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D6 pin configuration, PIN = Y9  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D7 pin configuration, PIN = V9  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D8 pin configuration, PIN = W9  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D9 pin configuration, PIN = P11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D10 pin configuration, PIN = V10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D11 pin configuration, PIN = Y10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D12 pin configuration, PIN = W10 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D13 pin configuration, PIN = R11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D14 pin configuration, PIN = V11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D15 pin configuration, PIN = W11 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D16 pin configuration, PIN = P12 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_D17 pin configuration, PIN = R12 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_PCLK pin configuration,   PIN = W6   */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_VSYNC pin configuration,  PIN = V7  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_HSYNC pin configuration,  PIN = Y6  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* LCD_ACBIAS pin configuration, PIN = W7 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupCamera  (ostboot)
+ * Description: Setup camera muxing
+ *****************************************/
+void muxSetupCamera(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* CAMERA_RSTZ  pin configuration, PIN = Y16 */
+	/* CAM_RST is connected through the I2C IO expander.*/
+	/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
+	/* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled   */
+
+	/* CAMERA_XCLK  pin configuration, PIN = U3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_LCLK  pin configuration, PIN = V5 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
+	*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_VSYNC pin configuration, PIN = U2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_HSYNC pin configuration, PIN = T3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT0 pin configuration, PIN = T4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT1 pin configuration, PIN = V2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT2 pin configuration, PIN = V3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT3 pin configuration, PIN = U4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT4 pin configuration, PIN = W2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT5 pin configuration, PIN = V4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT6 pin configuration, PIN = W3 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT7 pin configuration, PIN = Y2 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT8 pin configuration, PIN = Y4 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* CAMERA_DAT9 pin configuration, PIN = V6 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupMMCSD (ostboot)
+ * Description: set up MMC muxing
+ *****************************************/
+void muxSetupMMCSD(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* SDMMC_CLKI pin configuration,  PIN = H15 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CLKO pin configuration,  PIN = G19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CMD pin configuration,   PIN = H18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT0 pin configuration,  PIN = F20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT1 pin configuration,  PIN = H14 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT2 pin configuration,  PIN = E19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DAT3 pin configuration,  PIN = D19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+	/* External pull-ups are present. */
+	/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
+
+	/* SDMMC_DDIR0 pin configuration, PIN = F19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR1 pin configuration, PIN = E20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR2 pin configuration, PIN = F18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_DDIR3 pin configuration, PIN = E18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SDMMC_CDIR pin configuration,  PIN = G18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
+	/* MMC_CD for 2422IP=K1 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
+
+	/* MMC_WP pin configuration,      PIN = B4  */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
+}
+
+/******************************************
+ * Routine: muxSetupTouchScreen (ostboot)
+ * Description:  Set up touch screen muxing
+ *******************************************/
+void muxSetupTouchScreen(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* SPI1_CLK pin configuration,  PIN = U18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_MOSI pin configuration, PIN = V20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_MISO pin configuration, PIN = T18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* SPI1_nCS0 pin configuration, PIN = U19 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+	/* PEN_IRQ pin configuration,   PIN = P20 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
+				   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
+}
+
+/****************************************
+ * Routine: muxSetupHDQ (ostboot)
+ * Description: setup 1wire mux
+ *****************************************/
+void muxSetupHDQ(void)
+{
+	volatile unsigned char  *MuxConfigReg;
+
+	/* HDQ_SIO pin configuration,  PIN = N18 */
+	MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
+				   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+/***************************************************************
+ * Routine: muxSetupGPMC (ostboot)
+ * Description: Configures balls which cam up in protected mode
+ ***************************************************************/
+void muxSetupGPMC(void)
+{
+	volatile uint8 *MuxConfigReg;
+	volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
+
+	/* gpmc_io_dir */
+	*MCR = 0x19000000;
+
+	/* NOR FLASH CS0 */
+	/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
+				   *MuxConfigReg = 0x01 ;
+
+	/* MPDB(Multi Port Debug Port) CS1 */
+	/* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
+				   *MuxConfigReg = 0x00 ;
+}
+
+/****************************************************************
+ * Routine: muxSetupSDRC  (ostboot)
+ * Description: Configures balls which come up in protected mode
+ ****************************************************************/
+void muxSetupSDRC(void)
+{
+	volatile uint8 *MuxConfigReg;
+
+	/* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
+				   *MuxConfigReg = 0x00 ;
+
+	/* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3	Pull/up - N/A */
+	MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
+				   *MuxConfigReg = 0x00;
+
+	if (get_cpu_type() == CPU_2422) {
+		MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
+					   *MuxConfigReg = 0x1b;
+	}
+}
+
+/*****************************************************************************
+ * Routine: update_mux()
+ * Description: Update balls which are different beween boards.  All should be
+ *              updated to match functionaly.  However, I'm only updating ones
+ *              which I'll be using for now.  When power comes into play they
+ *              all need updating.
+ *****************************************************************************/
+void update_mux(u32 btype,u32 mtype)
+{
+	u32 cpu, base = OMAP2420_CTRL_BASE;
+	cpu = get_cpu_type();
+
+	if (btype == BOARD_H4_MENELAUS) {
+		if (cpu == CPU_2420) {
+			/* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
+			__raw_writeb(0x3, base+0x30);
+			/* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
+			__raw_writeb(0x3, base+0xa3);
+			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
+			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
+			/* PIN = M1 (HSUSBOTG) */
+			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
+			__raw_writeb(0x3, base+0x9d);
+			/* PIN = U32, (WLAN_CLKREQ) */
+			/* PIN = Y11, WLAN */
+			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
+			__raw_writeb(0x3, base+0xe7);
+			/* PIN = AA8, mDOC */
+			/* PIN = AA10, BT */
+			/* PIN = AA13, WLAN */
+			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 HHUSB */
+			/* PIN = H19 HSUSB */
+			/* PIN = W13, P13, R13, W16 ... */
+			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
+			__raw_writeb(0x3, base+0xde);
+			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
+			__raw_writeb(0x0, base+0x12c);
+			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
+			__raw_writeb(0x0, base+0x136);
+		} else if (cpu == CPU_2422) {
+			/* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
+			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
+			/* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
+			/* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
+			__raw_writeb(0x0, base+0x92);
+			/* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
+			/* PIN = M1 (HSUSBOTG) */
+			/* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
+			__raw_writeb(0x3, base+0x10c);
+			/* PIN = U32, (WLAN_CLKREQ) */
+			/* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
+			__raw_writeb(0x3, base+0x30);
+			/* PIN = AA8, mDOC */
+			/* PIN = AA10, BT */
+			/* PIN = AA12, WLAN */
+			/* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 HHUSB */
+			/* PIN = H19 HSUSB */
+			/* PIN = W13, P13, R13, W16 ... */
+			/* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
+			__raw_writeb(0x3, base+0xde);
+			/* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
+			__raw_writeb(0x0, base+0x12c);
+			/* PIN = AA17->sys_clkreq        mode 0   -DO- */
+			__raw_writeb(0x0, base+0x136);
+		}
+
+	} else if (btype == BOARD_H4_SDP) {
+		if (cpu == CPU_2420) {
+			/* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
+			/* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
+			/* Pin = Y11 VLNQ */
+			/* Pin = AA4 VLNQ */
+			/* Pin = AA6 VLNQ */
+			/* Pin = AA8 VLNQ */
+			/* Pin = AA10 VLNQ */
+			/* Pin = AA12 VLNQ */
+			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 MDOC_nDMAREQ */
+			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
+			__raw_writeb(0x3, base+0x114);
+			/* PIN = W13, V12, P13, R13, W19, W16 ... */
+			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
+		} else if (cpu == CPU_2422) {
+			/* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
+			/* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
+			/* Pin = Y11 VLNQ */
+			/* Pin = AA4 VLNQ */
+			/* Pin = AA6 VLNQ */
+			/* Pin = AA8 VLNQ */
+			/* Pin = AA10 VLNQ */
+			/* Pin = AA12 VLNQ */
+			/* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x10e);
+			/* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
+			__raw_writeb(0x3, base+0x110);
+			/* PIN = J15 MDOC_nDMAREQ */
+			/* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
+			__raw_writeb(0x3, base+0x114);
+			/* PIN = W13, V12, P13, R13, W19, W16 ... */
+			/* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
+		}
+	}
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_init(void)
+{
+    extern flash_info_t flash_info[];
+
+    nand_probe(CFG_NAND_ADDR);
+    if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+		print_size(nand_dev_desc[0].totlen, "\n");
+    }
+
+#ifdef CFG_JFFS2_MEM_NAND
+    flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
+    flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2;      /* only read kernel single meg partition */
+	flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024;   /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
+    flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
+#endif
+}
+#endif
diff --git a/board/omap2420h4/sys_info.c b/board/omap2420h4/sys_info.c
new file mode 100755
index 0000000..a9f7241
--- /dev/null
+++ b/board/omap2420h4/sys_info.c
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>  /* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <i2c.h>
+
+/**************************************************************************
+ * get_prod_id() - get id info from chips
+ ***************************************************************************/
+static u32 get_prod_id(void)
+{
+	u32 p;
+	p = __raw_readl(PRODUCTION_ID); /* get production ID */
+	return((p & CPU_242X_PID_MASK) >> 16);
+}
+
+/**************************************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ * - just looking to say if this is a 2422 or 2420 or ...
+ * - to start with we will look at switch settings..
+ * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics
+ *   (mux for 2420, non-mux for 2422).
+ ***************************************************************************/
+u32 get_cpu_type(void)
+{
+	u32 v;
+
+	switch(get_prod_id()){
+		case 1:;/* 2420 */
+		case 2: return(CPU_2420); break; /* 2420 pop */
+		case 4: return(CPU_2422); break;
+		case 8: return(CPU_2423); break;
+		default: break;  /* early 2420/2422's unmarked */
+	}
+
+	v = __raw_readl(TAP_IDCODE_REG);
+	v &= CPU_24XX_ID_MASK;
+	if (v == CPU_2420_CHIPID) {	  /* currently 2420 and 2422 have same id */
+		if (is_gpmc_muxed() == GPMC_MUXED)	  /* if mux'ed */
+			return(CPU_2420);
+		else
+			return(CPU_2422);
+	} else
+		return(CPU_2420); /* don't know, say 2420 */
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+	u32 v;
+	v = __raw_readl(TAP_IDCODE_REG);
+	v = v >> 28;
+	return(v+1);  /* currently 2422 and 2420 match up */
+}
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+	volatile u32 *burst = (volatile u32 *)(SDRC_MR_0+SDRC_CS0_OSET);
+	if(*burst == H4_2420_SDRC_MR_0_SDR)
+		return(1);
+	return(0);
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ * 2422 uses stacked DDR, 2 parts CS0/CS1.
+ * 2420 may have 1 or 2, no good way to know...only init 1...
+ * when eeprom data is up we can select 1 more.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+	u32 cpu, sdr = is_mem_sdr();
+
+	cpu = get_cpu_type();
+	if (cpu == CPU_2422 || cpu == CPU_2423)
+		return(DDR_STACKED);
+
+	if(get_prod_id() == 0x2)
+		return(XDR_POP);
+
+	if (get_board_type() == BOARD_H4_MENELAUS)
+		if(sdr)
+			return(SDR_DISCRETE);
+		else
+			return(DDR_COMBO);
+	else
+		if(sdr) /* SDP + SDR kit */
+			return(SDR_DISCRETE);
+		else
+			return(DDR_DISCRETE); /* origional SDP */
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+	u32 size;
+	size = __raw_readl(SDRC_MCFG_0+offset) >> 8; /* get ram size field */
+	size &= 0x2FF;   /* remove unwanted bits */
+	size *= SZ_2M;   /* find size in MB */
+	return(size);
+}
+
+/***********************************************************************
+ * get_board_type() - get board type based on current production stats.
+ *  --- NOTE: 2 I2C EEPROMs will someday be populated with proper info.
+ *      when they are available we can get info from there.  This should
+ *      be correct of all known boards up until today.
+ ************************************************************************/
+u32 get_board_type(void)
+{
+	if (i2c_probe(I2C_MENELAUS) == 0)
+		return(BOARD_H4_MENELAUS);
+	else
+		return(BOARD_H4_SDP);
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings (dip switch on h4)
+ ******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+	return(0x00000FFF & __raw_readl(CONTROL_STATUS));
+}
+
+/***************************************************************************
+ *  get_gpmc0_base() - Return current address hardware will be
+ *     fetching from. The below effectively gives what is correct, its a bit
+ *   mis-leading compared to the TRM.  For the most general case the mask
+ *   needs to be also taken into account this does work in practice.
+ *   - for u-boot we currently map:
+ *       -- 0 to nothing,
+ *       -- 4 to flash
+ *       -- 8 to enent
+ *       -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+	u32 b;
+
+	b = __raw_readl(GPMC_CONFIG7_0);
+	b &= 0x1F;	 /* keep base [5:0] */
+	b = b << 24; /* ret 0x0b000000 */
+	return(b);
+}
+
+/*****************************************************************
+ *  is_gpmc_muxed() - tells if address/data lines are multiplexed
+ *****************************************************************/
+u32 is_gpmc_muxed(void)
+{
+	u32 mux;
+	mux = get_sysboot_value();
+	if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3))
+		return(GPMC_MUXED); /* NAND Boot mode */
+	if (mux & BIT1)	   /* if mux'ed */
+		return(GPMC_MUXED);
+	else
+		return(GPMC_NONMUXED);
+}
+
+/************************************************************************
+ *  get_gpmc0_type() - read sysboot lines to see type of memory attached
+ ************************************************************************/
+u32 get_gpmc0_type(void)
+{
+	u32 type;
+	type = get_sysboot_value();
+	if ((type & (BIT3|BIT2)) == (BIT3|BIT2))
+		return(TYPE_NAND);
+	else
+		return(TYPE_NOR);
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+	u32 width;
+	width = get_sysboot_value();
+	if ((width & 0xF) == (BIT3|BIT2))
+		return(WIDTH_8BIT);
+	else
+		return(WIDTH_16BIT);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ *   volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+	u32 i = 0, val;
+	do {
+		++i;
+		val = __raw_readl(read_addr) & read_bit_mask;
+		if (val == match_value)
+			return(1);
+		if (i==bound)
+			return(0);
+	} while (1);
+}
+
+/*********************************************************************
+ *  display_board_info() - print banner with board info.
+ *********************************************************************/
+void display_board_info(u32 btype)
+{
+	char cpu_2420[] = "2420";   /* cpu type */
+	char cpu_2422[] = "2422";
+	char cpu_2423[] = "2423";
+	char db_men[] = "Menelaus"; /* board type */
+	char db_ip[] = "IP";
+	char mem_sdr[] = "mSDR";    /* memory type */
+	char mem_ddr[] = "mDDR";
+	char t_tst[] = "TST";	    /* security level */
+	char t_emu[] = "EMU";
+	char t_hs[] = "HS";
+	char t_gp[] = "GP";
+	char unk[] = "?";
+
+	char *cpu_s, *db_s, *mem_s, *sec_s;
+	u32 cpu, rev, sec;
+
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+	sec = get_device_type();
+
+	if(is_mem_sdr())
+		mem_s = mem_sdr;
+	else
+		mem_s = mem_ddr;
+
+	if(cpu == CPU_2423)
+		cpu_s = cpu_2423;
+	else if (cpu == CPU_2422)
+		cpu_s = cpu_2422;
+	else
+		cpu_s = cpu_2420;
+
+	if(btype ==  BOARD_H4_MENELAUS)
+		db_s = db_men;
+	else
+		db_s = db_ip;
+
+	switch(sec){
+		case TST_DEVICE: sec_s = t_tst; break;
+		case EMU_DEVICE: sec_s = t_emu; break;
+		case HS_DEVICE:  sec_s = t_hs; break;
+		case GP_DEVICE:  sec_s = t_gp; break;
+		default: sec_s = unk;
+	}
+
+	printf("OMAP%s-%s revision %d\n", cpu_s, sec_s, rev-1);
+	printf("TI H4 SDP Base Board + %s Daughter Board + %s \n", db_s, mem_s);
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ *          0 = 242x IP platform (first 2xx boards)
+ *          1 = 242x Menelaus platfrom.
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+	u32 rev = 0;
+	u32 btype = get_board_type();
+
+	if (btype == BOARD_H4_MENELAUS){
+		rev = 1;
+	}
+	return(rev);
+}
+
+/********************************************************
+ *  get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+	u32  val;
+	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
+	val &= 0xF0000000;
+	val >>= 28;
+	return(val);
+}
+
+/********************************************************
+ *  get_base2(); get 2upper addr of current execution
+ *******************************************************/
+u32 get_base2(void)
+{
+	u32  val;
+	__asm__ __volatile__("mov %0, pc \n" : "=r" (val) : : "memory");
+	val &= 0xFF000000;
+	val >>= 24;
+	return(val);
+}
+
+/********************************************************
+ *  running_in_flash() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_flash(void)
+{
+	if (get_base() < 4)
+		return(1);  /* in flash */
+	return(0); /* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ *  running_in_sram() - tell if currently running in
+ *   sram.
+ *******************************************************/
+u32 running_in_sram(void)
+{
+	if (get_base() == 4)
+		return(1);  /* in SRAM */
+	return(0); /* running in FLASH or SDRAM */
+}
+/********************************************************
+ *  running_in_sdram() - tell if currently running in
+ *   flash.
+ *******************************************************/
+u32 running_in_sdram(void)
+{
+	if (get_base() > 4)
+		return(1);  /* in sdram */
+	return(0); /* running in SRAM or FLASH */
+}
+
+/*************************************************************
+ *  running_from_internal_boot() - am I a signed NOR image.
+ *************************************************************/
+u32 running_from_internal_boot(void)
+{
+	u32 v, base;
+
+	v = get_sysboot_value() & BIT3;
+	base = get_base2();
+	/* if running at mask rom flash address and
+	 * sysboot3 says this was an internal boot
+	 */
+	if ((base == 0x08) && v)
+		return(1);
+	else
+		return(0);
+}
+
+/*************************************************************
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+	int mode;
+	mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
+	return(mode >>= 8);
+}
diff --git a/board/omap2420h4/u-boot.lds b/board/omap2420h4/u-boot.lds
new file mode 100755
index 0000000..1460adc
--- /dev/null
+++ b/board/omap2420h4/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  cpu/arm1136/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/omap5912osk/Makefile b/board/omap5912osk/Makefile
new file mode 100755
index 0000000..4b56421
--- /dev/null
+++ b/board/omap5912osk/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap5912osk.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/omap5912osk/config.mk b/board/omap5912osk/config.mk
new file mode 100755
index 0000000..0375796
--- /dev/null
+++ b/board/omap5912osk/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2002-2004
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+# Rishi Bhattacharya <rishi@ti.com>
+#
+# TI OSK board with OMAP5912 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# OSK has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+
+TEXT_BASE = 0x11080000
diff --git a/board/omap5912osk/lowlevel_init.S b/board/omap5912osk/lowlevel_init.S
new file mode 100755
index 0000000..3b9633a
--- /dev/null
+++ b/board/omap5912osk/lowlevel_init.S
@@ -0,0 +1,442 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1, #0xffffffff
+	ldr	r0, =REG_IHL1_MIR
+	str	r1, [r0]
+	ldr	r0, =REG_IHL2_MIR
+	str	r1, [r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)  		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x0000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+ 	 *------------------------------------------------------*/
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Load physical SDRAM base. */
+	mov 	r0, 	#0x10000000
+	/* Get current execution location. */
+	mov 	r1, 	pc
+	/* Compare. */
+	cmp 	r1, 	r0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bge 	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne 	3b
+
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+
+	/* mobile ddr operation */
+	ldr	r0,	REG_SDRAM_OPERATION
+	mov	r2,	#07
+	str	r2,	[r0]
+
+	/* config register */
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	/* manual command register */
+	ldr	r0,	REG_SDRAM_MANUAL_CMD
+	/* issue set cke high */
+	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
+	str	r1,	[r0]
+	/* issue nop */
+	mov	r1,	#CMD_SDRAM_NOP
+	str	r1,	[r0]
+
+	mov	r2,	#0x0100
+waitMDDR1:
+	subs	r2,	r2,	 #1
+	bne	waitMDDR1	/* delay loop */
+
+	/* issue precharge */
+	mov	r1,	#CMD_SDRAM_PRECHARGE
+	str	r1,	[r0]
+
+	/* issue autorefresh x 2 */
+	mov	r1,	#CMD_SDRAM_AUTOREFRESH
+	str	r1,	[r0]
+	str	r1,	[r0]
+
+	/* mrs register ddr mobile */
+	ldr	r0,	REG_SDRAM_MRS
+	mov	r1,	#0x33
+	str	r1,	[r0]
+
+	/* emrs1 low-power register */
+	ldr	r0,	REG_SDRAM_EMRS1
+	/* self refresh on all banks */
+	mov	r1,	#0
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_URD_CONTROL
+	ldr	r1,	DLL_URD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_LRD_CONTROL
+	ldr	r1,	DLL_LRD_CONTROL_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_DLL_WRT_CONTROL
+	ldr	r1,	DLL_WRT_CONTROL_VAL
+	str	r1,	[r0]
+
+	/* delay loop */
+	mov	r2,	#0x0100
+waitMDDR2:
+	subs	r2,	r2,	#1
+	bne	waitMDDR2
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov	r3,	#0x1800
+4:
+	subs	r3,	r3,	#1	/* Decrement count. */
+	bne	4b
+	b	common_tc
+
+skip_sdram:
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+#ifdef CONFIG_H2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+	.word 0xfffecc80
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+	.word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+	.word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+	.word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+	.word 0xfffecc68
+DLL_WRT_CONTROL_VAL:
+	.word 0x03f00002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+	.word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+	.word 0x00800002
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+	.word 0xfffecccc
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec600
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+	.word 0x001200f4
+
+DLL_LRD_CONTROL_VAL:
+	.word 0x00800002
+
+VAL_ARM_CKCTL:
+	.word 0x3000
+VAL_DPLL1_CTL:
+	.word 0x2830
+
+#ifdef CONFIG_OSK_OMAP5912
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x002130b0
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00001131
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x000055f0
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x88011131
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x010290fc
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+/* command values */
+.equ CMD_SDRAM_NOP,		0x00000000
+.equ CMD_SDRAM_PRECHARGE,	0x00000001
+.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007
diff --git a/board/omap5912osk/omap5912osk.c b/board/omap5912osk/omap5912osk.c
new file mode 100755
index 0000000..1faa084
--- /dev/null
+++ b/board/omap5912osk/omap5912osk.c
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Rishi Bhattacharya <rishi@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP1610)
+#include <./configs/omap1510.h>
+#endif
+
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+	peripheral_power_enable ();
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+	unsigned int regval;
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0480000b
+	int i;
+
+	*((volatile unsigned short *) 0xfffece08) = 0x03FF;
+	*((volatile unsigned short *) 0xfffb3824) = 0x8000;
+	*((volatile unsigned short *) 0xfffb3830) = 0x0000;
+	*((volatile unsigned short *) 0xfffb3834) = 0x0009;
+	*((volatile unsigned short *) 0xfffb3838) = 0x0009;
+	*((volatile unsigned short *) 0xfffb3818) = 0x0002;
+	*((volatile unsigned short *) 0xfffb382C) = 0x0048;
+	*((volatile unsigned short *) 0xfffb3824) = 0x8603;
+	udelay (3);
+	for (i=0;i<2000;i++);
+	*((volatile unsigned short *) 0xfffb381C) = 0x6610;
+	udelay (30);
+	for (i=0;i<10000;i++);
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+
+
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* setup for UART1 */
+	*MuxConfReg &= ~(0x02000000);	/* bit 25 */
+	/* setup for UART2 */
+	*MuxConfReg &= ~(0x01000000);	/* bit 24 */
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x08000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
+	/*setup mux for UART3 */
+	*MuxConfReg |= 0x00000001;	/* bit3, 1, 0 (mux0 5,5,26) */
+	*MuxConfReg &= ~0x0000003e;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
+	/* Disable Uwire CS Hi-Z */
+	*MuxConfReg |= 0x00001200;	/*bit 9 for CS0 12 for CS3 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
+	/*  Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the  */
+	/*  hardware will actually use TX and RTS based on bit 25 in  */
+	/*  FUNC_MUX_CTRL_0.  I told you this thing was screwy!	 */
+	*MuxConfReg |= 0x00201000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
+	/* setup for UART2 */
+	/*  Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the  */
+	/*  hardware will actually use TX and RTS based on bit 24 in  */
+	/*  FUNC_MUX_CTRL_0. */
+	*MuxConfReg |= 0x09000000;
+	MuxConfReg =
+	(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D);
+	*MuxConfReg |= 0x00000020;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
+	*MuxConfReg = 0x00000000;
+	/* mux setup for SD/MMC driver */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
+	*MuxConfReg &= 0xFFFE0FFF;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 13 for MMC2 XOR_CLK */
+	*MuxConfReg &= ~(0x00002000);
+	/* bit 29 for UART 1 */
+	*MuxConfReg &= ~(0x00002000);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
+	/* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
+	*MuxConfReg |= 0x000C0000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
+	*MuxConfReg &= ~(0x00000070);
+	*MuxConfReg &= ~(0x00000008);
+	*MuxConfReg |= 0x00000003;
+	*MuxConfReg |= 0x00000180;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	/* bit 17, software controls VBUS */
+	*MuxConfReg &= ~(0x00020000);
+	/* Enable USB 48 and 12M clocks */
+	*MuxConfReg |= 0x00000200;
+	*MuxConfReg &= ~(0x00000180);
+	/*2.75V for MMCSDIO1 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
+	*MuxConfReg = 0x00001FE7;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
+	*MuxConfReg = 0x00000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
+	*MuxConfReg = 0x00000000;
+	/* Turn on UART2 48 MHZ clock */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
+	*MuxConfReg |= 0x40000000;
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
+	/* setup for USB VBus detection OMAP161x */
+	*MuxConfReg |= 0x00040000;	/* bit 18 */
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
+	/* PullUps for SD/MMC driver */
+	*MuxConfReg |= ~(0xFFFE0FFF);
+	MuxConfReg =
+		(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
+	*MuxConfReg = COMP_MODE_ENABLE;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+#define UART1_48MHZ_ENABLE	((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST	((volatile unsigned short *)0xFFFE0834)
+
+	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
+}
diff --git a/board/omap5912osk/u-boot.lds b/board/omap5912osk/u-boot.lds
new file mode 100755
index 0000000..142450c
--- /dev/null
+++ b/board/omap5912osk/u-boot.lds
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/omap730p2/Makefile b/board/omap730p2/Makefile
new file mode 100755
index 0000000..29467ac
--- /dev/null
+++ b/board/omap730p2/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= omap730p2.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/omap730p2/config.mk b/board/omap730p2/config.mk
new file mode 100755
index 0000000..16bff6f
--- /dev/null
+++ b/board/omap730p2/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+TEXT_BASE = 0x11080000
diff --git a/board/omap730p2/flash.c b/board/omap730p2/flash.c
new file mode 100755
index 0000000..e7d6515
--- /dev/null
+++ b/board/omap730p2/flash.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
+	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256L18T;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/omap730p2/lowlevel_init.S b/board/omap730p2/lowlevel_init.S
new file mode 100755
index 0000000..6c6f482
--- /dev/null
+++ b/board/omap730p2/lowlevel_init.S
@@ -0,0 +1,395 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003-2004
+ *
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
+ * (http://www.mpc-data.co.uk)
+ *
+ * TODO : Tidy up and change to use system register defines
+ *        from omap730.h where possible.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Save callers address in r11 - r11 must never be modified */
+	mov r11, lr
+
+	/*------------------------------------------------------*
+	 *mask all IRQs by setting all bits in the INTMR default*
+	 *------------------------------------------------------*/
+	mov	r1,	#0xffffffff
+	ldr	r0,	=REG_IHL1_MIR
+	str	r1,	[r0]
+	ldr	r0,	=REG_IHL2_MIR
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT1)                   *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT1
+	ldr	r1,	VAL_ARM_IDLECT1
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT2)  		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT2
+	ldr	r1,	VAL_ARM_IDLECT2
+	str	r1,	[r0]
+
+	/*------------------------------------------------------*
+	 * Set up ARM CLM registers (IDLECT3)		        *
+	 *------------------------------------------------------*/
+	ldr	r0,	REG_ARM_IDLECT3
+	ldr	r1,	VAL_ARM_IDLECT3
+	str	r1,	[r0]
+
+
+	mov	r1,	#0x01		/* PER_EN bit */
+	ldr	r0,	REG_ARM_RSTCT2
+	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable	*/
+	/* I supposedly need to enable the dsp clock before switching */
+	mov	r1,	#0x1000
+	ldr	r0,	REG_ARM_SYSST
+	strh	r1,	[r0]
+	mov	r0,	#0x400
+1:
+	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
+	bne	1b
+	ldr	r1,	VAL_ARM_CKCTL
+	ldr	r0,	REG_ARM_CKCTL
+	strh	r1,	[r0]
+
+	/* a few nops to let settle */
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* setup DPLL 1 */
+	/* Ramp up the clock to 96Mhz */
+	ldr	r1,	VAL_DPLL1_CTL
+	ldr	r0,	REG_DPLL1_CTL
+	strh	r1,	[r0]
+	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
+	beq	lock_end	/* Do not look for lock if BYPASS selected */
+2:
+	ldrh	r1,	[r0]
+	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
+	beq 2b			/*	loop until bit goes hi. */
+lock_end:
+
+	/*------------------------------------------------------*
+	 * Turn off the watchdog during init...			*
+ 	 *------------------------------------------------------*/
+	ldr	r0,	REG_WATCHDOG
+	ldr	r1,	WATCHDOG_VAL1
+	str	r1,	[r0]
+	ldr	r1,	WATCHDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL1
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+
+watch1Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch1Wait
+
+	ldr	r0,	REG_WSPRDOG
+	ldr	r1,	WSPRDOG_VAL2
+	str	r1,	[r0]
+	ldr	r0,	REG_WWPSDOG
+watch2Wait:
+	ldr	r1,	[r0]
+	tst	r1,	#0x10
+	bne	watch2Wait
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	/* Compare physical SDRAM base & current execution location. */
+	and     r0, pc, #0xF0000000
+	/* Compare. */
+	cmp     r0, #0
+	/* Skip over EMIF-fast initialization if running from SDRAM. */
+	bne 	skip_sdram
+
+	/*
+	* Delay for SDRAM initialization.
+	*/
+	mov	r3,	#0x1800		/* value should be checked */
+3:
+	subs	r3,	r3,	#0x1	/* Decrement count */
+	bne 	3b
+
+	ldr	r0,	REG_SDRAM_CONFIG
+	ldr	r1,	SDRAM_CONFIG_VAL
+	str	r1,	[r0]
+
+	ldr	r0,	REG_SDRAM_MRS_LEGACY
+	ldr	r1,	SDRAM_MRS_VAL
+	str	r1,	[r0]
+
+skip_sdram:
+
+common_tc:
+	/* slow interface */
+	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
+	str	r1,	[r0] /* Chip Select 0 */
+
+	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
+	str	r1,	[r0] /* Chip Select 1 */
+	ldr	r1,	VAL_TC_EMIFS_CS2_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS2_CONFIG
+	str	r1,	[r0] /* Chip Select 2 */
+	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
+	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
+	str	r1,	[r0] /* Chip Select 3 */
+
+	/* 48MHz clock request for UART1 */
+	ldr	r1,	PERSEUS2_CONFIG_BASE
+	ldrh	r0,	[r1, #CONFIG_PCC_CONF]
+	orr	r0,	r0, #CONF_MOD_UART1_CLK_MODE_R
+	strh	r0,	[r1, #CONFIG_PCC_CONF]
+
+	/* Initialize public and private rheas
+	 *  - set access factor 2 on both rhea / strobe
+	 *  - disable write buffer on strb0, enable write buffer on strb1
+	 */
+
+	ldr	R0,	REG_RHEA_PUB_CTL
+	ldr	R1,	REG_RHEA_PRIV_CTL
+	ldr	R2,	VAL_RHEA_CTL
+	strh	R2,	[R0]
+	strh	R2,	[R1]
+	mov	R3,	#2          /* disable write buffer on strb0, enable write buffer on strb1 */
+	strh	R3,	[R0, #0x08]	/* arm rhea control reg */
+	strh	R3,	[R1, #0x08]
+
+	/* enable IRQ and FIQ */
+
+	mrs	r4,	CPSR
+	bic	r4,	r4, #IRQ_MASK
+	bic	r4,	r4, #FIQ_MASK
+	msr	CPSR,	r4
+
+	/* set TAP CONF to TRI EMULATION */
+
+	ldr	r1,	[r0, #CONFIG_MODE2]
+	bic	r1,	r1, #0x18
+	orr	r1,	r1, #0x10
+	str	r1,	[r0, #CONFIG_MODE2]
+
+	/* set tdbgen to 1 */
+
+	ldr	r0,	PERSEUS2_CONFIG_BASE
+	ldr	r1,	[r0, #CONFIG_MODE1]
+	mov	r2,	#0x10000
+	orr	r1,	r1, r2
+	str	r1,	[r0, #CONFIG_MODE1]
+
+#ifdef CONFIG_P2_OMAP1610
+	/* inserting additional 2 clock cycle hold time for LAN */
+	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
+	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
+	str     r1,     [r0]
+#endif
+	/* Start MPU Timer 1 */
+	ldr	r0,	REG_MPU_LOAD_TIMER
+	ldr	r1,	VAL_MPU_LOAD_TIMER
+	str	r1,	[r0]
+
+	ldr	r0,	REG_MPU_CNTL_TIMER
+	ldr	r1,	VAL_MPU_CNTL_TIMER
+	str	r1,	[r0]
+
+	/* back to arch calling code */
+	mov	pc,	r11
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+
+#ifdef CONFIG_P2_OMAP730
+REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
+	.word 0xfffecc54
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+
+REG_ARM_IDLECT3:		/* 16 bits */
+	.word 0xfffece24
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_IDLECT1:		/* 16 bits */
+	.word 0xfffece04
+
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+	.word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+	.word 0xfffeb034
+
+WSPRDOG_VAL1:
+	.word 0x0000aaaa
+WSPRDOG_VAL2:
+	.word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+	.word 0xfffecc20
+
+REG_SDRAM_MRS_LEGACY:
+	.word 0xfffecc24
+
+REG_WATCHDOG:
+	.word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+	.word 0xfffec600
+REG_MPU_CNTL_TIMER:
+	.word 0xfffec500
+
+/* Public and private rhea bridge registers definition */
+
+REG_RHEA_PUB_CTL:
+	.word 0xFFFECA00
+
+REG_RHEA_PRIV_CTL:
+	.word 0xFFFED300
+
+/* EMIFF SDRAM Configuration register
+   - self refresh disable
+   - auto refresh enabled
+   - SDRAM type 64 Mb, 16 bits bus 4 banks
+   - power down enabled
+   - SDRAM clock disabled
+ */
+SDRAM_CONFIG_VAL:
+	.word 0x0C017DF4
+
+/* Burst full page length ; cas latency = 3 */
+SDRAM_MRS_VAL:
+	.word 0x00000037
+
+VAL_ARM_CKCTL:
+	.word 0x6505
+VAL_DPLL1_CTL:
+	.word 0x3412
+
+#ifdef CONFIG_P2_OMAP730
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x0000FFF3
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00004278
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x00004278
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00004278
+VAL_TC_EMIFS_CS1_ADVANCED:
+	.word 0x00000022
+#endif
+
+VAL_ARM_IDLECT1:
+	.word 0x00000400
+VAL_ARM_IDLECT2:
+	.word 0x00000886
+VAL_ARM_IDLECT3:
+	.word 0x00000015
+
+WATCHDOG_VAL1:
+	.word 0x000000f5
+WATCHDOG_VAL2:
+	.word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+	.word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+	.word 0xffffffa1
+
+VAL_RHEA_CTL:
+	.word			0xFF22
+
+/* Config Register vals */
+PERSEUS2_CONFIG_BASE:
+	.word			0xFFFE1000
+
+.equ	CONFIG_PCC_CONF,	0xB4
+.equ	CONFIG_MODE1,		0x10
+.equ	CONFIG_MODE2,		0x14
+.equ	CONF_MOD_UART1_CLK_MODE_R,	0x0A
+
+/* misc values */
+.equ	IRQ_MASK,		0x80           /* IRQ mask value */
+.equ	FIQ_MASK,		0x40           /* FIQ mask value */
diff --git a/board/omap730p2/omap730p2.c b/board/omap730p2/omap730p2.c
new file mode 100755
index 0000000..256c6a6
--- /dev/null
+++ b/board/omap730p2/omap730p2.c
@@ -0,0 +1,267 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP730)
+#include <./configs/omap730.h>
+#endif
+
+int test_boot_mode(void);
+void spin_up_leds(void);
+void flash__init (void);
+void ether__init (void);
+void set_muxconf_regs (void);
+void peripheral_power_enable (void);
+
+#define FLASH_ON_CS0	1
+#define FLASH_ON_CS3	0
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+int test_boot_mode(void)
+{
+	/* Check for CS0 and CS3 address decode swapping */
+	if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
+		return(FLASH_ON_CS3);
+	else
+		return(FLASH_ON_CS0);
+}
+
+/* Toggle backup LED indication */
+void toggle_backup_led(void)
+{
+	static int  backupLEDState = 0;	 /* Init variable so that the LED will be ON the first time */
+	volatile unsigned int *IOConfReg;
+
+
+	IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
+
+	if (backupLEDState != 0) {
+		*IOConfReg &= (0xFFFFEFFF);
+		backupLEDState = 0;
+	} else {
+		*IOConfReg |= (0x00001000);
+		backupLEDState = 1;
+	}
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of OMAP 730 P2 Board - Same as the Innovator! */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	/* Configure MUX settings */
+	set_muxconf_regs ();
+
+	peripheral_power_enable ();
+
+	/* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
+	toggle_backup_led();
+
+	/* Hold GSM in reset until needed */
+	*((volatile unsigned short *)M_CTL) &= ~1;
+
+	/*
+	 *  CSx timings, GPIO Mux ... setup
+	 */
+
+	/* Flash: CS0 timings setup */
+	*((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
+	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
+
+	/* Ethernet support trough the debug board */
+	/* CS1 timings setup */
+	*((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
+	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
+
+	/* this speeds up your boot a quite a bit.  However to make it
+	 *  work, you need make sure your kernel startup flush bug is fixed.
+	 *  ... rkw ...
+	 */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	/* currently empty */
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+	unsigned int regval;
+
+	regval = *((volatile unsigned int *) EMIFS_CONFIG);
+	/* Turn off write protection for flash devices. */
+	regval = regval | 0x0001;
+	*((volatile unsigned int *) EMIFS_CONFIG) = regval;
+}
+
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+			   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+#define LAN_RESET_REGISTER 0x0400001c
+
+	*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
+		udelay (100);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
+
+	do {
+		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
+		udelay (100);
+	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
+
+#define ETH_CONTROL_REG 0x0400030b
+
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (100);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/******************************************************
+ Routine: set_muxconf_regs
+ Description: Setting up the configuration Mux registers
+			  specific to the hardware
+*******************************************************/
+void set_muxconf_regs (void)
+{
+	volatile unsigned int *MuxConfReg;
+	/* set each registers to its reset value; */
+
+	/*
+	 *  Backup LED Indication
+	 */
+
+	/* Configure MUXed pin. Mode 6: GPIO_140 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
+	*MuxConfReg &= (0xFFFFFF1F);	     /* Clear D_MPU_LPG1 */
+	*MuxConfReg |= 0x000000C0;	     /* Set D_MPU_LPG1 to 0x6 */
+
+	/* Configure GPIO_140 as output */
+	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
+	*MuxConfReg &= (0xFFFFEFFF);	     /* Clear direction (output) for GPIO 140 */
+
+	/*
+	 * Configure GPIOs for battery charge & feedback
+	 */
+
+	/* Configure MUXed pin. Mode 6: GPIO_35 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
+	*MuxConfReg &= 0xFFFFFFF1;	     /* Clear M_CLK_OUT */
+	*MuxConfReg |= 0x0000000C;	     /* Set M_CLK_OUT = 0x6 (GPIOs) */
+
+	/* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
+	*MuxConfReg &= 0xFFFF1FFF;	     /* Clear D_DDR */
+	*MuxConfReg |= 0x0000C000;	     /* Set D_DDR = 0x6 (GPIOs) */
+
+	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
+	*MuxConfReg |= 0x00000100;	     /* Configure GPIO_72 as input */
+	*MuxConfReg &= 0xFFFFFDFF;	     /* Configure GPIO_73 as output	*/
+
+	/*
+	 * Allow battery charge
+	 */
+
+	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
+	*MuxConfReg &= (0xFFFFFDFF);	     /* Clear GPIO_73 pin */
+
+	/*
+	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
+	 * It is used as the Ethernet controller interrupt
+	 */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
+	*MuxConfReg &= 0x1FFFFFFF;
+}
+
+/******************************************************
+ Routine: peripheral_power_enable
+ Description: Enable the power for UART1
+*******************************************************/
+void peripheral_power_enable (void)
+{
+	volatile unsigned int *MuxConfReg;
+
+
+	/* Set up pins used by UART */
+
+	/* Start UART clock (48MHz) */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
+	*MuxConfReg &= (0xFFFFFFF7);
+	*MuxConfReg |= (0x00000008);
+
+	/* Get the UART pin in mode0  */
+	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
+	*MuxConfReg &= (0xFF1FFFFF);
+	*MuxConfReg &= (0xF1FFFFFF);
+}
diff --git a/board/omap730p2/u-boot.lds b/board/omap730p2/u-boot.lds
new file mode 100755
index 0000000..710b2a2
--- /dev/null
+++ b/board/omap730p2/u-boot.lds
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/oxc/Makefile b/board/oxc/Makefile
new file mode 100755
index 0000000..ae7a932
--- /dev/null
+++ b/board/oxc/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/oxc/config.mk b/board/oxc/config.mk
new file mode 100755
index 0000000..7a5bcfc
--- /dev/null
+++ b/board/oxc/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# OXC boards
+#
+
+#TEXT_BASE = 0x00090000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/oxc/flash.c b/board/oxc/flash.c
new file mode 100755
index 0000000..795b7cc
--- /dev/null
+++ b/board/oxc/flash.c
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for STM29W320DB/STM29W800D flash chips
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static ulong flash_get_size (vu_char *addr, flash_info_t *info);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    unsigned long size;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /*
+     * We use the following trick here: since flash is cyclically
+     * mapped in the 0xFF800000-0xFFFFFFFF area, we detect the type
+     * and the size of flash using 0xFF800000 as the base address,
+     * and then call flash_get_size() again to fill flash_info.
+     */
+    size = flash_get_size((vu_char *)CFG_FLASH_PRELIMBASE, &flash_info[0]);
+    if (size)
+    {
+	flash_get_size((vu_char *)(-size), &flash_info[0]);
+    }
+
+#if (CFG_MONITOR_BASE >= CFG_FLASH_PRELIMBASE)
+    /* monitor protection ON by default */
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_MONITOR_BASE,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_ENV_ADDR,
+		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+
+    return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+    case FLASH_MAN_STM:
+	printf ("ST ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case FLASH_STM320DB:
+	printf ("M29W320DB (32 Mbit)\n");
+	break;
+    case FLASH_STM800DB:
+	printf ("M29W800DB (8 Mbit, bottom boot block)\n");
+	break;
+    case FLASH_STM800DT:
+	printf ("M29W800DT (8 Mbit, top boot block)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld KB in %d Sectors\n",
+	    info->size >> 10, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	if ((i % 5) == 0)
+	    printf ("\n   ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "     "
+		);
+    }
+    printf ("\n");
+    return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_char *addr, flash_info_t *info)
+{
+    short i;
+    uchar vendor, devid;
+    ulong base = (ulong)addr;
+
+    /* Write auto select command: read Manufacturer ID */
+    addr[0x0AAA] = 0xAA;
+    addr[0x0555] = 0x55;
+    addr[0x0AAA] = 0x90;
+
+    udelay(1000);
+
+    vendor = addr[0];
+    devid = addr[2];
+
+    /* only support STM */
+    if ((vendor << 16) != FLASH_MAN_STM) {
+	return 0;
+    }
+
+    if (devid == FLASH_STM320DB) {
+    	/* MPC8240 can address maximum 2Mb of flash, that is why the MSB
+	 * lead is grounded and we can access only 2 first Mb */
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 32;
+	info->size         = info->sector_count * 0x10000;
+	for (i = 0; i < info->sector_count; i++) {
+	    info->start[i] = base + i * 0x10000;
+	}
+    }
+    else if (devid == FLASH_STM800DB) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 19;
+	info->size         = 0x100000;
+	info->start[0]     = 0x0000;
+	info->start[1]     = 0x4000;
+	info->start[2]     = 0x6000;
+	info->start[3]     = 0x8000;
+	for (i = 4; i < info->sector_count; i++) {
+	    info->start[i] = base + (i-3) * 0x10000;
+	}
+    }
+    else if (devid == FLASH_STM800DT) {
+	info->flash_id     = vendor << 16 | devid;
+	info->sector_count = 19;
+	info->size         = 0x100000;
+	for (i = 0; i < info->sector_count-4; i++) {
+	    info->start[i] = base + i * 0x10000;
+	}
+	info->start[i]     = base + i * 0x10000;
+	info->start[i+1]   = base + i * 0x10000 + 0x8000;
+	info->start[i+2]   = base + i * 0x10000 + 0xa000;
+	info->start[i+3]   = base + i * 0x10000 + 0xc000;
+    }
+    else {
+	return 0;
+    }
+
+    /* mark all sectors as unprotected */
+    for (i = 0; i < info->sector_count; i++) {
+	info->protect[i] = 0;
+    }
+
+    /* Issue the reset command */
+    if (info->flash_id != FLASH_UNKNOWN) {
+	addr[0] = 0xF0;	/* reset bank */
+    }
+
+    return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_char *addr = (vu_char *)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0AAA] = 0xAA;
+    addr[0x0555] = 0x55;
+    addr[0x0AAA] = 0x80;
+    addr[0x0AAA] = 0xAA;
+    addr[0x0555] = 0x55;
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) {	/* not protected */
+	    addr = (vu_char *)(info->start[sect]);
+	    addr[0] = 0x30;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+      goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_char *)(info->start[l_sect]);
+    while ((addr[0] & 0x80) != 0x80) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {	/* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+    DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned char *)info->start[0];
+    addr[0] = 0xF0;	/* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    int rc;
+
+    while (cnt > 0) {
+	if ((rc = write_byte(info, addr, *src)) != 0) {
+	    return (rc);
+	}
+	addr++;
+	src++;
+	cnt--;
+    }
+
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+    vu_char *addr = (vu_char *)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_char *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0AAA] = 0xAA;
+    addr[0x0555] = 0x55;
+    addr[0x0AAA] = 0xA0;
+
+    *((vu_char *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c
new file mode 100755
index 0000000..fa7ff02
--- /dev/null
+++ b/board/oxc/oxc.c
@@ -0,0 +1,217 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+#include <i2c.h>
+
+int checkboard (void)
+{
+	puts (	"Board: OXC8240\n" );
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+#ifndef CFG_RAMBOOT
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+#else
+	/* if U-Boot starts from RAM, then suppose we have 16Mb of RAM */
+	return (16 << 20);
+#endif
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_oxc_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x14, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x15, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_oxc_config_table,
+#endif
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+int board_early_init_f (void)
+{
+	*(volatile unsigned char *)(CFG_CPLD_RESET) = 0x89;
+	return 0;
+}
+
+#ifdef CONFIG_WATCHDOG
+void oxc_wdt_reset(void)
+{
+	*(volatile unsigned char *)(CFG_CPLD_WATCHDOG) = 0xff;
+}
+
+void watchdog_reset(void)
+{
+	int re_enable = disable_interrupts();
+
+	oxc_wdt_reset();
+	if (re_enable)
+		enable_interrupts();
+}
+#endif
+
+static int oxc_get_expander(unsigned char addr, unsigned char * val)
+{
+	return i2c_read(addr, 0, 0, val, 1);
+}
+
+static int oxc_set_expander(unsigned char addr, unsigned char val)
+{
+	return i2c_write(addr, 0, 0, &val, 1);
+}
+
+static int expander0alive = 0;
+
+#ifdef CONFIG_SHOW_ACTIVITY
+static int ledtoggle = 0;
+static int ledstatus = 1;
+
+void oxc_toggle_activeled(void)
+{
+	ledtoggle++;
+}
+
+void board_show_activity (ulong timestamp)
+{
+	if ((timestamp % (CFG_HZ / 10)) == 0)
+		oxc_toggle_activeled ();
+}
+
+void show_activity(int arg)
+{
+	static unsigned char led = 0;
+	unsigned char val;
+
+	if (!expander0alive) return;
+
+	if ((ledtoggle > (2 * arg)) && ledstatus) {
+		led ^= 0x80;
+		oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val);
+		udelay(200);
+		oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, (val & 0x7F) | led);
+		ledtoggle = 0;
+	}
+}
+#endif
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress(int arg)
+{
+	unsigned char val;
+
+	if (!expander0alive) return;
+
+	if (arg > 0 && ledstatus) {
+		ledstatus = 0;
+		oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val);
+		udelay(200);
+		oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val | 0x80);
+	} else if (arg < 0) {
+		oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val);
+		udelay(200);
+		oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val & 0x7F);
+		ledstatus = 1;
+	}
+}
+#endif
+
+int misc_init_r (void)
+{
+	/* check whether the i2c expander #0 is accessible */
+	if (!oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, 0x7F)) {
+		udelay(200);
+		expander0alive = 1;
+	}
+
+#ifdef CFG_OXC_GENERATE_IP
+	{
+		DECLARE_GLOBAL_DATA_PTR;
+
+		char str[32];
+		unsigned long ip = CFG_OXC_IPMASK;
+		bd_t *bd = gd->bd;
+
+		if (expander0alive) {
+			unsigned char val;
+
+			if (!oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val)) {
+				ip = (ip & 0xffffff00) | ((val & 0x7c) >> 2);
+			}
+		}
+
+		if ((ip & 0xff) < 3) {
+			/* if fail, set x.x.x.254 */
+			ip = (ip & 0xffffff00) | 0xfe;
+		}
+
+		bd->bi_ip_addr = ip;
+		sprintf(str, "%ld.%ld.%ld.%ld",
+			(bd->bi_ip_addr & 0xff000000) >> 24,
+			(bd->bi_ip_addr & 0x00ff0000) >> 16,
+			(bd->bi_ip_addr & 0x0000ff00) >> 8,
+			(bd->bi_ip_addr & 0x000000ff));
+		setenv("ipaddr", str);
+		printf("ip:    %s\n", str);
+	}
+#endif
+	return (0);
+}
diff --git a/board/oxc/u-boot.lds b/board/oxc/u-boot.lds
new file mode 100755
index 0000000..2a5cd2e
--- /dev/null
+++ b/board/oxc/u-boot.lds
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile
new file mode 100755
index 0000000..d1cdc6b
--- /dev/null
+++ b/board/pb1x00/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= memsetup.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/pb1x00/README b/board/pb1x00/README
new file mode 100755
index 0000000..b37ff36
--- /dev/null
+++ b/board/pb1x00/README
@@ -0,0 +1,63 @@
+By Thomas.Lange@corelatus.se 2004-Oct-05
+----------------------------------------
+DbAu1xx0 are development boards from AMD containing
+an Alchemy AU1xx0 series cpu with mips32 core.
+Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
+
+Limitations & comments
+----------------------
+Support was originally big endian only.
+I have not tested, but several u-boot users report working
+configurations in little endian mode.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+( dbau1000, dbau1100 and dbau1500 ).
+Now there is a new board called dbau1550 also, which
+should be supported RSN.
+
+I only have a dbau1000, so my testing is limited
+to this board.
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader delivered with board.
+
+NOTE! When you switch between the two boot flashes, the
+base addresses will be swapped.
+Have this in mind when you compile u-boot. TEXT_BASE has
+to match the address where u-boot is located when you
+actually launch.
+
+Ethernet only supported for mac0.
+
+PCMCIA only supported for slot 0, only 3.3V.
+
+PCMCIA IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+########     NOTE!!!!!!   #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA and running cpu in big endian mode!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
diff --git a/board/pb1x00/config.mk b/board/pb1x00/config.mk
new file mode 100755
index 0000000..396a045
--- /dev/null
+++ b/board/pb1x00/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMD development board AMD Alchemy Pb1x00, MIPS32 core
+#
+
+# ROM version
+#TEXT_BASE = 0xbfc00000
+
+# SDRAM version
+TEXT_BASE = 0x83800000
diff --git a/board/pb1x00/flash.c b/board/pb1x00/flash.c
new file mode 100755
index 0000000..3cf29e8
--- /dev/null
+++ b/board/pb1x00/flash.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	printf ("Skipping flash_init\n");
+	return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	printf ("write_buff not implemented\n");
+	return (-1);
+}
diff --git a/board/pb1x00/memsetup.S b/board/pb1x00/memsetup.S
new file mode 100755
index 0000000..44f02b9
--- /dev/null
+++ b/board/pb1x00/memsetup.S
@@ -0,0 +1,392 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR		0xB1900000
+#define sys_endian		0x0038
+#define CP0_Config0		$16
+#define MEM_1MS			((396000000/1000000) * 1000)
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	memsetup
+memsetup:
+	/*
+	 * Step 1) Establish CPU endian mode.
+	 * NOTE: A fair amount of code is necessary on the Pb1000 to
+	 * obtain the value of Switch S8.1 which is used to determine
+	 * endian at run-time.
+	 */
+
+	/* RCE1 */
+	li		t0, MEM_STCFG1
+	li		t1, 0x00000083
+	sw		t1, 0(t0)
+
+	li		t0, MEM_STTIME1
+	li		t1, 0x33030A10
+	sw		t1, 0(t0)
+
+	li		t0, MEM_STADDR1
+	li		t1, 0x11803E40
+	sw		t1, 0(t0)
+
+	/* Set DSTRB bits so switch will read correctly */
+	li		t1, 0xBE00000C
+	lw		t2, 0(t1)
+	or		t2, t2, 0x00000300
+	sw		t2, 0(t1)
+
+	/* Check switch setting */
+	li		t1, 0xBE000014
+	lw		t2, 0(t1)
+	and		t2, t2, 0x00000100
+	bne		t2, zero, big_endian
+	nop
+
+little_endian:
+
+	/* Change Au1 core to little endian */
+	li	t0, AU1500_SYS_ADDR
+	li	t1, 1
+	sw	t1, sys_endian(t0)
+	mfc0	t2, CP0_CONFIG
+	mtc0	t2, CP0_CONFIG
+	nop
+	nop
+
+	/* Big Endian is default so nothing to do but fall through */
+
+big_endian:
+
+	/*
+	 * Step 2) Establish Status Register
+	 * (set BEV, clear ERL, clear EXL, clear IE)
+	 */
+	li	t1, 0x00400000
+	mtc0	t1, CP0_STATUS
+
+	/*
+	 * Step 3) Establish CP0 Config0
+	 * (set OD, set K0=3)
+	 */
+	li	t1, 0x00080003
+	mtc0	t1, CP0_CONFIG
+
+	/*
+	 * Step 4) Disable Watchpoint facilities
+	 */
+	li t1, 0x00000000
+	mtc0	t1, CP0_WATCHLO
+	mtc0	t1, CP0_IWATCHLO
+	/*
+	 * Step 5) Disable the performance counters
+	 */
+	mtc0	zero, CP0_PERFORMANCE
+	nop
+
+	/*
+	 * Step 6) Establish EJTAG Debug register
+	 */
+	mtc0	zero, CP0_DEBUG
+	nop
+
+	/*
+	 * Step 7) Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* Establish Wired (and Random) */
+	mtc0	zero, CP0_WIRED
+	nop
+
+	/* First setup pll:s to make serial work ok */
+	/* We have a 12 MHz crystal */
+	li	t0, SYS_CPUPLL
+	li	t1, 0x21  /* 396 MHz */
+	sw	t1, 0(t0)
+	sync
+	nop
+	nop
+
+	/* wait 1mS for clocks to settle */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+	/* Setup AUX PLL */
+	li	t0, SYS_AUXPLL
+	li	t1, 8 /* 96 MHz */
+	sw	t1, 0(t0) /* aux pll */
+	sync
+
+	/*  Static memory controller */
+
+	/* RCE0 8MB AMD29D323 Flash */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00001403
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME0
+	li	t1, 0xFFFFFFDD
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR0
+	li	t1, 0x11F83FE0
+	sw	t1, 0(t0)
+
+	/* RCE1 CPLD Board Logic */
+	li	t0, MEM_STCFG1
+	li	t1, 0x00000083
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME1
+	li	t1, 0x33030A10
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR1
+	li	t1, 0x11803E40
+	sw	t1, 0(t0)
+
+	/* RCE2 CPLD Board Logic */
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000004
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x08061908
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x12A03FC0
+	sw	t1, 0(t0)
+
+	/* RCE3 PCMCIA 250ns */
+	li	t0, MEM_STCFG3
+	li	t1, 0x00000002
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME3
+	li	t1, 0x280E3E07
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR3
+	li	t1, 0x10000000
+	sw	t1, 0(t0)
+
+	sync
+
+	/* Set peripherals to a known state */
+	li	t0, IC0_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, IC1_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, SYS_FREQCTRL0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_FREQCTRL1
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_CLKSRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_PININPUTEN
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, 0xB1100100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, 0xB1400100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+
+	li	t0, SYS_WAKEMSK
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_WAKESRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	/* wait 1mS before setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+	/*
+	 * Skip memory setup if we are running from memory
+	 */
+	li		t0, 0x90000000
+	sub		t0, ra, t0
+	bltz		t0, skip_memsetup
+	nop
+
+	/*
+	 * SDCS0 - Not used, for SMROM
+	 * SDCS1 - 32MB Micron 48LCBM16A2
+	 * SDCS2 - 32MB Micron 48LCBM16A2
+	 */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x00552229
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0x00552229
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0x001003F8
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0x001023F8
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x74000c30 /* Disable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDREFCFG
+	li	t1, 0x76000c30 /* Enable */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000023
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000023
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x00000023
+	sw	t1, 0(t0)
+	sync
+
+	/* wait 1mS after setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+skip_memsetup:
+
+	li	t0, SYS_PINFUNC
+	li	t1, 0/*0x00008080*/
+	sw	t1, 0(t0)
+
+	/*
+	li	t0, SYS_TRIOUTCLR
+	li	t1, 0x00001FFF
+	sw	t1, 0(t0)
+
+	li	t0, SYS_OUTPUTCLR
+	li	t1, 0x00008000
+	sw	t1, 0(t0)
+	*/
+	sync
+
+	j	ra
+	nop
diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
new file mode 100755
index 0000000..40ac2a4
--- /dev/null
+++ b/board/pb1x00/pb1x00.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+long int initdram(int board_type)
+{
+	/* Sdram is setup by assembler code */
+	/* If memory could be changed, we should return the true value here */
+	return 64*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN		0x0010
+#define BCSR_PCMCIA_PC0RST		0x0080
+
+/* In cpu/mips/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+	u16 status;
+	/* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
+	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+	u32 proc_id;
+
+	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+	proc_id = read_32bit_cp0_register(CP0_PRID);
+
+	switch (proc_id >> 24) {
+	case 0:
+		puts ("Board: Pb1000\n");
+		printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 1:
+		puts ("Board: Pb1500\n");
+		printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	case 2:
+		puts ("Board: Pb1100\n");
+		printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
+	default:
+		printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+	}
+#if defined(CONFIG_IDE_PCMCIA) && 0
+	/* Enable 3.3 V on slot 0 ( VCC )
+	   No 5V */
+	status = 4;
+	*pcmcia_bcsr = status;
+
+	status |= BCSR_PCMCIA_PC0DRVEN;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(300*1000);
+
+	status |= BCSR_PCMCIA_PC0RST;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(100*1000);
+
+	/* PCMCIA is on a 36 bit physical address.
+	   We need to map it into a 32 bit addresses */
+
+#if 0
+	/* We dont need theese unless we run whole pcmcia package */
+	write_one_tlb(20,                 /* index */
+		      0x01ffe000,         /* Pagemask, 16 MB pages */
+		      CFG_PCMCIA_IO_BASE, /* Hi */
+		      0x3C000017,         /* Lo0 */
+		      0x3C200017);        /* Lo1 */
+
+	write_one_tlb(21,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CFG_PCMCIA_ATTR_BASE, /* Hi */
+		      0x3D000017,           /* Lo0 */
+		      0x3D200017);          /* Lo1 */
+#endif	/* 0 */
+	write_one_tlb(22,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CFG_PCMCIA_MEM_ADDR,  /* Hi */
+		      0x3E000017,           /* Lo0 */
+		      0x3E200017);          /* Lo1 */
+#endif	/* CONFIG_IDE_PCMCIA */
+
+	return 0;
+}
diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds
new file mode 100755
index 0000000..a2d19a8
--- /dev/null
+++ b/board/pb1x00/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
diff --git a/board/pcippc2/Makefile b/board/pcippc2/Makefile
new file mode 100755
index 0000000..2998f23
--- /dev/null
+++ b/board/pcippc2/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COBJS	= $(BOARD).o cpc710_pci.o flash.o sconsole.o \
+	  fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o
+
+AOBJS	=
+
+OBJS	= $(COBJS) $(AOBJS)
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
+	$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/pcippc2/config.mk b/board/pcippc2/config.mk
new file mode 100755
index 0000000..92d37c9
--- /dev/null
+++ b/board/pcippc2/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# PCIPPC-2 boards
+#
+
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/pcippc2/cpc710.h b/board/pcippc2/cpc710.h
new file mode 100755
index 0000000..8167270
--- /dev/null
+++ b/board/pcippc2/cpc710.h
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPC710_H_
+#define _CPC710_H_
+
+/* Revision */
+#define CPC710_TYPE_100	0x80
+#define CPC710_TYPE_100P	0x90
+
+/* System control area */
+#define HW_PHYS_SCA		0xff000000
+
+#define HW_SCA_CPC0		0x000000
+#define HW_SCA_SDRAM0		0x000000
+#define HW_SCA_DMA0		0x1C0000
+
+#define HW_PHYS_CPC0		(HW_PHYS_SCA + HW_SCA_CPC0)
+#define HW_PHYS_SDRAM0		(HW_PHYS_SCA + HW_SCA_SDRAM0)
+
+#define HW_CPC0_PCICNFR		0x000c
+#define HW_CPC0_RSTR		0x0010
+#define HW_CPC0_SPOR		0x00e8
+#define HW_CPC0_UCTL		0x1000
+#define HW_CPC0_SIOC0		0x1020
+#define HW_CPC0_ABCNTL		0x1030
+#define HW_CPC0_SESR		0x1060
+#define HW_CPC0_SEAR		0x1070
+#define HW_CPC0_PGCHP		0x1100
+#define HW_CPC0_RGBAN0		0x1110
+#define HW_CPC0_RGBAN1		0x1120
+
+#define HW_CPC0_GPDIR		0x1130
+#define HW_CPC0_GPIN		0x1140
+#define HW_CPC0_GPOUT		0x1150
+
+#define HW_CPC0_ATAS		0x1160
+
+#define HW_CPC0_PCIBAR		0x200018
+#define HW_CPC0_PCIENB		0x201000
+
+#define HW_SDRAM0_MCCR		0x1200
+#define HW_SDRAM0_MESR		0x1220
+#define HW_SDRAM0_MEAR		0x1230
+
+#define HW_SDRAM0_MCER0		0x1300
+#define HW_SDRAM0_MCER1		0x1310
+#define HW_SDRAM0_MCER2		0x1320
+#define HW_SDRAM0_MCER3		0x1330
+#define HW_SDRAM0_MCER4		0x1340
+#define HW_SDRAM0_MCER5		0x1350
+#define HW_SDRAM0_MCER6		0x1360
+#define HW_SDRAM0_MCER7		0x1370
+
+#define HW_BRIDGE_PCIDG		0xf6120
+#define HW_BRIDGE_INTACK	0xf7700
+#define HW_BRIDGE_PIBAR		0xf7800
+#define HW_BRIDGE_PMBAR		0xf7810
+#define HW_BRIDGE_CRR		0xf7ef0
+#define HW_BRIDGE_PR		0xf7f20
+#define HW_BRIDGE_ACR		0xf7f30
+#define HW_BRIDGE_MSIZE		0xf7f40
+#define HW_BRIDGE_IOSIZE	0xf7f60
+#define HW_BRIDGE_SMBAR		0xf7f80
+#define HW_BRIDGE_SIBAR		0xf7fc0
+#define HW_BRIDGE_CFGADDR	0xf8000
+#define HW_BRIDGE_CFGDATA	0xf8010
+#define HW_BRIDGE_PSSIZE	0xf8100
+#define HW_BRIDGE_BARPS		0xf8120
+#define HW_BRIDGE_PSBAR		0xf8140
+
+/* Configuration space registers */
+#define CPC710_BUS_NUMBER	0x40
+#define CPC710_SUB_BUS_NUMBER	0x41
+
+#endif
diff --git a/board/pcippc2/cpc710_init_ram.c b/board/pcippc2/cpc710_init_ram.c
new file mode 100755
index 0000000..57ed8f0
--- /dev/null
+++ b/board/pcippc2/cpc710_init_ram.c
@@ -0,0 +1,254 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include "pcippc2.h"
+#include "i2c.h"
+
+typedef struct cpc710_mem_org_s
+{
+  u8		rows;
+  u8		cols;
+  u8		banks2;
+  u8		org;
+} cpc710_mem_org_t;
+
+static int		cpc710_compute_mcer	(u32 *		mcer,
+						 unsigned long *
+								size,
+						 unsigned int	sdram);
+static int		cpc710_eeprom_checksum	(unsigned int	sdram);
+static u8		cpc710_eeprom_read	(unsigned int	sdram,
+						 unsigned int	offset);
+
+static u32		cpc710_mcer_mem [] =
+{
+  0x000003f3,	/* 18 lines,    4 Mb */
+  0x000003e3,	/* 19 lines,    8 Mb */
+  0x000003c3,	/* 20 lines,   16 Mb */
+  0x00000383,	/* 21 lines,   32 Mb */
+  0x00000303,	/* 22 lines,   64 Mb */
+  0x00000203,	/* 23 lines,  128 Mb */
+  0x00000003,	/* 24 lines,  256 Mb */
+  0x00000002,	/* 25 lines,  512 Mb */
+  0x00000001	/* 26 lines, 1024 Mb */
+};
+static cpc710_mem_org_t	cpc710_mem_org [] =
+{
+  { 0x0c, 0x09, 0x02, 0x00 },	/* 0000: 12/ 9/2 */
+  { 0x0d, 0x09, 0x02, 0x00 },	/* 0000: 13/ 9/2 */
+  { 0x0d, 0x0a, 0x02, 0x00 },	/* 0000: 13/10/2 */
+  { 0x0d, 0x0b, 0x02, 0x00 },	/* 0000: 13/11/2 */
+  { 0x0d, 0x0c, 0x02, 0x00 },	/* 0000: 13/12/2 */
+  { 0x0e, 0x0c, 0x02, 0x00 },	/* 0000: 14/12/2 */
+  { 0x0b, 0x08, 0x02, 0x01 },	/* 0001: 11/ 8/2 */
+  { 0x0b, 0x09, 0x01, 0x02 },	/* 0010: 11/ 9/1 */
+  { 0x0b, 0x0a, 0x01, 0x03 },	/* 0011: 11/10/1 */
+  { 0x0c, 0x08, 0x02, 0x04 },	/* 0100: 12/ 8/2 */
+  { 0x0c, 0x0a, 0x02, 0x05 },	/* 0101: 12/10/2 */
+  { 0x0d, 0x08, 0x01, 0x06 },	/* 0110: 13/ 8/1 */
+  { 0x0d, 0x08, 0x02, 0x07 },	/* 0111: 13/ 8/2 */
+  { 0x0d, 0x09, 0x01, 0x08 },	/* 1000: 13/ 9/1 */
+  { 0x0d, 0x0a, 0x01, 0x09 },	/* 1001: 13/10/1 */
+  { 0x0b, 0x08, 0x01, 0x0a },	/* 1010: 11/ 8/1 */
+  { 0x0c, 0x08, 0x01, 0x0b },	/* 1011: 12/ 8/1 */
+  { 0x0c, 0x09, 0x01, 0x0c },	/* 1100: 12/ 9/1 */
+  { 0x0e, 0x09, 0x02, 0x0d },	/* 1101: 14/ 9/2 */
+  { 0x0e, 0x0a, 0x02, 0x0e },	/* 1110: 14/10/2 */
+  { 0x0e, 0x0b, 0x02, 0x0f } 	/* 1111: 14/11/2 */
+};
+
+unsigned long cpc710_ram_init (void)
+{
+  unsigned long 	memsize = 0;
+  unsigned long		bank_size;
+  u32			mcer;
+
+#ifndef CFG_RAMBOOT
+    /* Clear memory banks
+     */
+  out32(REG(SDRAM0, MCER0), 0);
+  out32(REG(SDRAM0, MCER1), 0);
+  out32(REG(SDRAM0, MCER2), 0);
+  out32(REG(SDRAM0, MCER3), 0);
+  out32(REG(SDRAM0, MCER4), 0);
+  out32(REG(SDRAM0, MCER5), 0);
+  out32(REG(SDRAM0, MCER6), 0);
+  out32(REG(SDRAM0, MCER7), 0);
+  iobarrier_rw();
+
+    /* Disable memory
+     */
+  out32(REG(SDRAM0,MCCR), 0x13b06000);
+  iobarrier_rw();
+#endif
+
+    /* Only the first memory bank is initialised now
+     */
+  if (! cpc710_compute_mcer(& mcer, & bank_size, 0))
+  {
+    puts("Unsupported SDRAM type !\n");
+    hang();
+  }
+  memsize += bank_size;
+#ifndef CFG_RAMBOOT
+    /* Enable bank, zero start
+     */
+  out32(REG(SDRAM0, MCER0), mcer | 0x80000000);
+  iobarrier_rw();
+#endif
+
+#ifndef CFG_RAMBOOT
+    /* Enable memory
+     */
+  out32(REG(SDRAM0, MCCR), in32(REG(SDRAM0, MCCR)) | 0x80000000);
+
+    /* Wait until initialisation finished
+     */
+  while (! (in32 (REG(SDRAM0, MCCR)) & 0x20000000))
+  {
+    iobarrier_rw();
+  }
+
+    /* Clear Memory Error Status and Address registers
+     */
+  out32(REG(SDRAM0, MESR), 0);
+  out32(REG(SDRAM0, MEAR), 0);
+  iobarrier_rw();
+
+    /* ECC is not configured now
+     */
+#endif
+
+    /* Memory size counter
+     */
+  out32(REG(CPC0, RGBAN1), memsize);
+
+  return memsize;
+}
+
+static int cpc710_compute_mcer (
+  u32 *			mcer,
+  unsigned long	*	size,
+  unsigned int		sdram)
+{
+  u8			rows;
+  u8			cols;
+  u8			banks2;
+  unsigned int		lines;
+  u32			mc = 0;
+  unsigned int		i;
+  cpc710_mem_org_t *	org = 0;
+
+
+  if (! i2c_reset())
+  {
+    puts("Can't reset I2C!\n");
+    hang();
+  }
+
+  if (! cpc710_eeprom_checksum(sdram))
+  {
+    puts("Invalid EEPROM checksum !\n");
+    hang();
+  }
+
+  rows   = cpc710_eeprom_read(sdram, 3);
+  cols   = cpc710_eeprom_read(sdram, 4);
+    /* Can be 2 or 4 banks; divide by 2
+     */
+  banks2 = cpc710_eeprom_read(sdram, 17) / 2;
+
+  lines = rows + cols + banks2;
+
+  if (lines < 18 || lines > 26)
+  {
+      /* Unsupported configuration
+       */
+    return 0;
+  }
+
+
+  mc |= cpc710_mcer_mem [lines - 18] << 6;
+
+  for (i = 0; i < sizeof(cpc710_mem_org) / sizeof(cpc710_mem_org_t); i++)
+  {
+    cpc710_mem_org_t *	corg = cpc710_mem_org + i;
+
+    if (corg->rows == rows && corg->cols == cols && corg->banks2 == banks2)
+    {
+      org = corg;
+
+      break;
+    }
+  }
+
+  if (! org)
+  {
+      /* Unsupported configuration
+       */
+    return 0;
+  }
+
+  mc |= (u32) org->org << 2;
+
+    /* Supported configuration
+     */
+  *mcer = mc;
+  *size = 1l << (lines + 4);
+
+  return 1;
+}
+
+static int cpc710_eeprom_checksum (
+  unsigned int		sdram)
+{
+  u8			sum = 0;
+  unsigned int		i;
+
+  for (i = 0; i < 63; i++)
+  {
+    sum += cpc710_eeprom_read(sdram, i);
+  }
+
+  return sum == cpc710_eeprom_read(sdram, 63);
+}
+
+static u8 cpc710_eeprom_read (
+  unsigned int		sdram,
+  unsigned int		offset)
+{
+  u8			dev = (sdram << 1) | 0xa0;
+  u8			data;
+
+  if (! i2c_read_byte(& data, dev,offset))
+  {
+    puts("I2C error !\n");
+    hang();
+  }
+
+  return data;
+}
diff --git a/board/pcippc2/cpc710_pci.c b/board/pcippc2/cpc710_pci.c
new file mode 100755
index 0000000..bed8aea
--- /dev/null
+++ b/board/pcippc2/cpc710_pci.c
@@ -0,0 +1,309 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include "hardware.h"
+#include "pcippc2.h"
+
+struct pci_controller local_hose, cpci_hose;
+
+static u32	cpc710_mapped_ram;
+
+  /* Enable PCI retry timeouts
+   */
+void cpc710_pci_enable_timeout (void)
+{
+  out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, CFGDATA), 0x32000000);
+  iobarrier_rw();
+
+  out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
+  iobarrier_rw();
+}
+
+void cpc710_pci_init (void)
+{
+  u32			sdram_size = pcippc2_sdram_size();
+
+  cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ?
+		      sdram_size : PCI_MEMORY_MAXSIZE;
+
+    /* Select the local PCI
+     */
+  out32(REG(CPC0, PCICNFR), 0x80000002);
+  iobarrier_rw();
+
+  out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS);
+  iobarrier_rw();
+
+    /* Enable PCI bridge address decoding
+     */
+  out32(REG(CPC0, PCIENB), 0x80000000);
+  iobarrier_rw();
+
+    /* Select the CPCI bridge
+     */
+  out32(REG(CPC0, PCICNFR), 0x80000003);
+  iobarrier_rw();
+
+  out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS);
+  iobarrier_rw();
+
+    /* Enable PCI bridge address decoding
+     */
+  out32(REG(CPC0, PCIENB), 0x80000000);
+  iobarrier_rw();
+
+    /* Disable configuration accesses
+     */
+  out32(REG(CPC0, PCICNFR), 0x80000000);
+  iobarrier_rw();
+
+    /* Initialise the local PCI
+     */
+  out32(BRIDGE(LOCAL, CRR), 0x7c000000);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PCIDG), 0x40000000);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS);
+  out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS);
+  out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS);
+  out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS);
+  out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PR), 0x00ffe000);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, ACR), 0xfe000000);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24);
+  out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24);
+  out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
+  iobarrier_rw();
+
+    /* Initialise the CPCI bridge
+     */
+  out32(BRIDGE(CPCI, CRR), 0x7c000000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PCIDG), 0xC0000000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS);
+  out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS);
+  out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS);
+  out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS);
+  out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PR), 0x80ffe000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, ACR), 0xdf000000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24);
+  out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24);
+  out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24));
+  iobarrier_rw();
+
+    /* Local PCI
+     */
+
+  out32(BRIDGE(LOCAL, CFGADDR), 0x04000080);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, CFGDATA), 0x56010000);
+  iobarrier_rw();
+
+  out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
+  iobarrier_rw();
+
+    /* Set bus and subbus numbers
+     */
+  out32(BRIDGE(LOCAL, CFGADDR), 0x40000080);
+  iobarrier_rw();
+  out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
+  iobarrier_rw();
+
+  out32(BRIDGE(LOCAL, CFGADDR), 0x50000080);
+  iobarrier_rw();
+    /* PCI retry timeouts will be enabled later
+     */
+  out32(BRIDGE(LOCAL, CFGDATA), 0x00000000);
+  iobarrier_rw();
+
+    /* CPCI
+     */
+
+    /* Set bus and subbus numbers
+     */
+  out32(BRIDGE(CPCI, CFGADDR), 0x40000080);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x01010000);
+  iobarrier_rw();
+
+  out32(BRIDGE(CPCI, CFGADDR), 0x04000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x56010000);
+  iobarrier_rw();
+
+  out32(BRIDGE(CPCI, CFGADDR), 0x0c000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16);
+  iobarrier_rw();
+
+    /* Write to the PSBAR */
+  out32(BRIDGE(CPCI, CFGADDR), 0x10000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS));
+  iobarrier_rw();
+
+    /* Set bus and subbus numbers
+     */
+  out32(BRIDGE(CPCI, CFGADDR), 0x40000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000);
+  iobarrier_rw();
+
+  out32(BRIDGE(CPCI, CFGADDR), 0x50000180);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CFGDATA), 0x32000000);
+    /* PCI retry timeouts will be enabled later
+     */
+  out32(BRIDGE(CPCI, CFGDATA), 0x00000000);
+  iobarrier_rw();
+
+    /* Remove reset on the PCI buses
+     */
+  out32(BRIDGE(LOCAL, CRR), 0xfc000000);
+  iobarrier_rw();
+  out32(BRIDGE(CPCI, CRR), 0xfc000000);
+  iobarrier_rw();
+
+  local_hose.first_busno = 0;
+  local_hose.last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(local_hose.regions + 0,
+		 PCI_MEMORY_BUS,
+		 PCI_MEMORY_PHYS,
+		 PCI_MEMORY_MAXSIZE,
+		 PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+  /* PCI memory space */
+  pci_set_region(local_hose.regions + 1,
+		 BRIDGE_LOCAL_MEM_BUS,
+		 BRIDGE_LOCAL_MEM_PHYS,
+		 BRIDGE_LOCAL_MEM_SIZE,
+		 PCI_REGION_MEM);
+
+  /* PCI I/O space */
+  pci_set_region(local_hose.regions + 2,
+		 BRIDGE_LOCAL_IO_BUS,
+		 BRIDGE_LOCAL_IO_PHYS,
+		 BRIDGE_LOCAL_IO_SIZE,
+		 PCI_REGION_IO);
+
+  local_hose.region_count = 3;
+
+  pci_setup_indirect(&local_hose,
+		     BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR,
+		     BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA);
+
+  pci_register_hose(&local_hose);
+
+  /* Initialize PCI32 bus registers */
+  pci_hose_write_config_byte(&local_hose,
+			  PCI_BDF(local_hose.first_busno,0,0),
+			  CPC710_BUS_NUMBER,
+			  local_hose.first_busno);
+  pci_hose_write_config_byte(&local_hose,
+			  PCI_BDF(local_hose.first_busno,0,0),
+			  CPC710_SUB_BUS_NUMBER,
+			  local_hose.last_busno);
+
+  local_hose.last_busno = pci_hose_scan(&local_hose);
+
+  /* Write out correct max subordinate bus number for local hose */
+  pci_hose_write_config_byte(&local_hose,
+			  PCI_BDF(local_hose.first_busno,0,0),
+			  CPC710_SUB_BUS_NUMBER,
+			  local_hose.last_busno);
+
+  cpci_hose.first_busno = local_hose.last_busno + 1;
+  cpci_hose.last_busno = 0xff;
+
+  /* System memory space */
+  pci_set_region(cpci_hose.regions + 0,
+		 PCI_MEMORY_BUS,
+		 PCI_MEMORY_PHYS,
+		 PCI_MEMORY_MAXSIZE,
+		 PCI_REGION_MEMORY);
+
+  /* PCI memory space */
+  pci_set_region(cpci_hose.regions + 1,
+		 BRIDGE_CPCI_MEM_BUS,
+		 BRIDGE_CPCI_MEM_PHYS,
+		 BRIDGE_CPCI_MEM_SIZE,
+		 PCI_REGION_MEM);
+
+  /* PCI I/O space */
+  pci_set_region(cpci_hose.regions + 2,
+		 BRIDGE_CPCI_IO_BUS,
+		 BRIDGE_CPCI_IO_PHYS,
+		 BRIDGE_CPCI_IO_SIZE,
+		 PCI_REGION_IO);
+
+  cpci_hose.region_count = 3;
+
+  pci_setup_indirect(&cpci_hose,
+		     BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR,
+		     BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA);
+
+  pci_register_hose(&cpci_hose);
+
+  /* Initialize PCI64 bus registers */
+  pci_hose_write_config_byte(&cpci_hose,
+			  PCI_BDF(cpci_hose.first_busno,0,0),
+			  CPC710_BUS_NUMBER,
+			  cpci_hose.first_busno);
+  pci_hose_write_config_byte(&cpci_hose,
+			  PCI_BDF(cpci_hose.first_busno,0,0),
+			  CPC710_SUB_BUS_NUMBER,
+			  cpci_hose.last_busno);
+
+  cpci_hose.last_busno = pci_hose_scan(&cpci_hose);
+
+  /* Write out correct max subordinate bus number for cpci hose */
+  pci_hose_write_config_byte(&cpci_hose,
+			  PCI_BDF(cpci_hose.first_busno,0,0),
+			  CPC710_SUB_BUS_NUMBER,
+			  cpci_hose.last_busno);
+}
diff --git a/board/pcippc2/cpc710_pci.h b/board/pcippc2/cpc710_pci.h
new file mode 100755
index 0000000..24d0db6
--- /dev/null
+++ b/board/pcippc2/cpc710_pci.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CPC710_PCI_H_
+#define _CPC710_PCI_H_
+
+#define PCI_MEMORY_PHYS		0x00000000
+#define PCI_MEMORY_BUS		0x80000000
+#define PCI_MEMORY_MAXSIZE      0x20000000
+
+#define BRIDGE_CPCI_PHYS	0xff500000
+#define BRIDGE_CPCI_MEM_SIZE	0x08000000
+#define BRIDGE_CPCI_MEM_PHYS    0xf0000000
+#define BRIDGE_CPCI_MEM_BUS     0x00000000
+#define BRIDGE_CPCI_IO_SIZE	0x02000000
+#define BRIDGE_CPCI_IO_PHYS     0xfc000000
+#define BRIDGE_CPCI_IO_BUS      0x00000000
+
+#define BRIDGE_LOCAL_PHYS	0xff400000
+#define BRIDGE_LOCAL_MEM_SIZE	0x04000000
+#define BRIDGE_LOCAL_MEM_PHYS   0xf8000000
+#define BRIDGE_LOCAL_MEM_BUS    0x40000000
+#define BRIDGE_LOCAL_IO_SIZE	0x01000000
+#define BRIDGE_LOCAL_IO_PHYS    0xfe000000
+#define BRIDGE_LOCAL_IO_BUS     0x04000000
+
+#define BRIDGE(r, x)		(BRIDGE_##r##_PHYS + HW_BRIDGE_##x)
+
+#define PCI_LATENCY_TIMER_VAL	0xff
+
+#endif
diff --git a/board/pcippc2/flash.c b/board/pcippc2/flash.c
new file mode 100755
index 0000000..8c01415
--- /dev/null
+++ b/board/pcippc2/flash.c
@@ -0,0 +1,573 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <flash.h>
+#include <asm/io.h>
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+
+static ulong flash_get_size (ulong addr, flash_info_t *info);
+static int flash_get_offsets (ulong base, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_reset (ulong addr);
+
+unsigned long flash_init (void)
+{
+	unsigned int i;
+	unsigned long flash_size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = 0;
+		flash_info[i].size = 0;
+	}
+
+	DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE);
+
+	flash_size = flash_get_size (CFG_FLASH_BASE, flash_info);
+
+	DEBUGF("## Flash bank size: %08lx\n", flash_size);
+
+	if (flash_size) {
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
+    CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			      &flash_info[0]);
+#endif
+
+	} else {
+		puts ("Warning: the BOOT Flash is not initialised !");
+	}
+
+	return flash_size;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (ulong addr, flash_info_t *info)
+{
+	short i;
+	uchar value;
+
+	/* Write auto select command: read Manufacturer ID */
+	out8(addr + 0x0555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x02AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x0555, 0x90);
+	iobarrier_rw();
+
+	value = in8(addr);
+	iobarrier_rw();
+
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
+
+	switch (value | (value << 16)) {
+		case AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+
+		case FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+
+		case STM_MANUFACT:
+			info->flash_id = FLASH_MAN_STM;
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			flash_reset (addr);
+			return 0;
+	}
+
+	value = in8(addr + 1);			/* device ID		*/
+	iobarrier_rw();
+
+	DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value);
+
+	switch ((ulong)value) {
+		case AMD_ID_F040B:
+			DEBUGF("Am29F040B\n");
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;			/* => 512 kB		*/
+
+		case AMD_ID_LV040B:
+			DEBUGF("Am29LV040B\n");
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;			/* => 512 kB		*/
+
+		case AMD_ID_LV400T:
+			DEBUGF("Am29LV400T\n");
+			info->flash_id += FLASH_AM400T;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;			/* => 1 MB		*/
+
+		case AMD_ID_LV400B:
+			DEBUGF("Am29LV400B\n");
+			info->flash_id += FLASH_AM400B;
+			info->sector_count = 11;
+			info->size = 0x00100000;
+			break;			/* => 1 MB		*/
+
+		case AMD_ID_LV800T:
+			DEBUGF("Am29LV800T\n");
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;			/* => 2 MB		*/
+
+		case AMD_ID_LV800B:
+			DEBUGF("Am29LV400B\n");
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00200000;
+			break;			/* => 2 MB		*/
+
+		case AMD_ID_LV160T:
+			DEBUGF("Am29LV160T\n");
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;			/* => 4 MB		*/
+
+		case AMD_ID_LV160B:
+			DEBUGF("Am29LV160B\n");
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break;			/* => 4 MB		*/
+
+		case AMD_ID_LV320T:
+			DEBUGF("Am29LV320T\n");
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;			/* => 8 MB		*/
+
+#if 0
+		/* Has the same ID as AMD_ID_LV320T, to be fixed */
+		case AMD_ID_LV320B:
+			DEBUGF("Am29LV320B\n");
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 67;
+			info->size = 0x00800000;
+			break;			/* => 8 MB		*/
+#endif
+
+		case AMD_ID_LV033C:
+			DEBUGF("Am29LV033C\n");
+			info->flash_id += FLASH_AM033C;
+			info->sector_count = 64;
+			info->size = 0x01000000;
+			break;			/* => 16Mb		*/
+
+		case STM_ID_F040B:
+			DEBUGF("M29F040B\n");
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;			/* => 512 kB		*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			flash_reset (addr);
+			return (0);		/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	if (! flash_get_offsets (addr, info)) {
+		flash_reset (addr);
+		return 0;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		value = in8(info->start[i] + 2);
+		iobarrier_rw();
+		info->protect[i] = (value & 1) != 0;
+	}
+
+	/*
+	 * Reset bank to read mode
+	 */
+	flash_reset (addr);
+
+	return (info->size);
+}
+
+static int flash_get_offsets (ulong base, flash_info_t *info)
+{
+	unsigned int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM040:
+			/* set sector offsets for uniform sector type	*/
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base + i * info->size /
+				                            info->sector_count;
+			}
+			break;
+		default:
+			return 0;
+	}
+
+	return 1;
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile ulong addr = info->start[0];
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if (s_first < 0 || s_first > s_last) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+	out8(addr + 0x555, 0x80);
+	iobarrier_rw();
+	out8(addr + 0x555, 0xAA);
+	iobarrier_rw();
+	out8(addr + 0x2AA, 0x55);
+	iobarrier_rw();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = info->start[sect];
+			out8(addr, 0x30);
+			iobarrier_rw();
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = info->start[l_sect];
+
+	DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT);
+
+	while ((in8(addr) & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			flash_reset (info->start[0]);
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+		iobarrier_rw();
+	}
+
+DONE:
+	/* reset to read mode */
+	flash_reset (info->start[0]);
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile ulong addr = info->start[0];
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((in32(dest) & data) != data) {
+		return (2);
+	}
+
+	/* write each byte out */
+	for (i = 0; i < 4; i++) {
+		char *data_ch = (char *)&data;
+		int flag = disable_interrupts();
+
+		out8(addr + 0x555, 0xAA);
+		iobarrier_rw();
+		out8(addr + 0x2AA, 0x55);
+		iobarrier_rw();
+		out8(addr + 0x555, 0xA0);
+		iobarrier_rw();
+		out8(dest+i, data_ch[i]);
+		iobarrier_rw();
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				flash_reset (addr);
+				return (1);
+			}
+			iobarrier_rw();
+		}
+	}
+
+	flash_reset (addr);
+	return (0);
+}
+
+/*
+ * Reset bank to read mode
+ */
+static void flash_reset (ulong addr)
+{
+	out8(addr, 0xF0);	/* reset bank */
+	iobarrier_rw();
+}
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_STM:	printf ("SGS THOMSON ");	break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+				break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	if (info->size % 0x100000 == 0) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+			info->size / 0x100000, info->sector_count);
+	} else if (info->size % 0x400 == 0) {
+		printf ("  Size: %ld KB in %d Sectors\n",
+		        info->size / 0x400, info->sector_count);
+	} else {
+		printf ("  Size: %ld B in %d Sectors\n",
+		        info->size, info->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
diff --git a/board/pcippc2/fpga_serial.c b/board/pcippc2/fpga_serial.c
new file mode 100755
index 0000000..579bfc7
--- /dev/null
+++ b/board/pcippc2/fpga_serial.c
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include "fpga_serial.h"
+#include "hardware.h"
+#include "pcippc2.h"
+
+  /* 8 data, 1 stop, no parity
+   */
+#define LCRVAL		0x03
+  /* RTS/DTR
+   */
+#define MCRVAL		0x03
+  /* Clear & enable FIFOs
+   */
+#define FCRVAL		0x07
+
+static void fpga_serial_wait (void);
+static void fpga_serial_print (char c);
+
+void fpga_serial_init (int baudrate)
+{
+	int clock_divisor = 115200 / baudrate;
+
+	out8 (FPGA (INT, SERIAL_CONFIG), 0x24);
+	iobarrier_rw ();
+
+	fpga_serial_wait ();
+
+	out8 (UART (IER), 0);
+	out8 (UART (LCR), LCRVAL | 0x80);
+	iobarrier_rw ();
+	out8 (UART (DLL), clock_divisor & 0xff);
+	out8 (UART (DLM), clock_divisor >> 8);
+	iobarrier_rw ();
+	out8 (UART (LCR), LCRVAL);
+	iobarrier_rw ();
+	out8 (UART (MCR), MCRVAL);
+	out8 (UART (FCR), FCRVAL);
+	iobarrier_rw ();
+}
+
+void fpga_serial_putc (char c)
+{
+	if (c) {
+		fpga_serial_print (c);
+	}
+}
+
+void fpga_serial_puts (const char *s)
+{
+	while (*s) {
+		fpga_serial_print (*s++);
+	}
+}
+
+int fpga_serial_getc (void)
+{
+	while ((in8 (UART (LSR)) & 0x01) == 0);
+
+	return in8 (UART (RBR));
+}
+
+int fpga_serial_tstc (void)
+{
+	return (in8 (UART (LSR)) & 0x01) != 0;
+}
+
+void fpga_serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int clock_divisor = 115200 / gd->baudrate;
+
+	fpga_serial_wait ();
+
+	out8 (UART (LCR), LCRVAL | 0x80);
+	iobarrier_rw ();
+	out8 (UART (DLL), clock_divisor & 0xff);
+	out8 (UART (DLM), clock_divisor >> 8);
+	iobarrier_rw ();
+	out8 (UART (LCR), LCRVAL);
+	iobarrier_rw ();
+}
+
+static void fpga_serial_wait (void)
+{
+	while ((in8 (UART (LSR)) & 0x40) == 0);
+}
+
+static void fpga_serial_print (char c)
+{
+	if (c == '\n') {
+		while ((in8 (UART (LSR)) & 0x20) == 0);
+
+		out8 (UART (THR), '\r');
+		iobarrier_rw ();
+	}
+
+	while ((in8 (UART (LSR)) & 0x20) == 0);
+
+	out8 (UART (THR), c);
+	iobarrier_rw ();
+
+	if (c == '\n') {
+		fpga_serial_wait ();
+	}
+}
diff --git a/board/pcippc2/fpga_serial.h b/board/pcippc2/fpga_serial.h
new file mode 100755
index 0000000..92c9cdd
--- /dev/null
+++ b/board/pcippc2/fpga_serial.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FPGA_SERIAL_H_
+#define _FPGA_SERIAL_H_
+
+extern void	fpga_serial_init	(int);
+extern void	fpga_serial_putc 	(char);
+extern void	fpga_serial_puts 	(const char *);
+extern int	fpga_serial_getc 	(void);
+extern int	fpga_serial_tstc 	(void);
+extern void	fpga_serial_setbrg 	(void);
+
+#endif
diff --git a/board/pcippc2/hardware.h b/board/pcippc2/hardware.h
new file mode 100755
index 0000000..489929d
--- /dev/null
+++ b/board/pcippc2/hardware.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _HARDWARE_H_
+#define _HARDWARE_H_
+
+#include "cpc710.h"
+#include "cpc710_pci.h"
+#include "pcippc2_fpga.h"
+#include "ns16550.h"
+
+#define REG(r, x)	(HW_PHYS_##r + HW_##r##_##x)
+
+  /* Address map:
+   *
+   * 0x00000000-0x20000000	SDRAM
+   * 0x40000000-0x00008000	Init RAM in the CPU DCache
+   * 0xf0000000-0xf8000000	CPCI MEM
+   * 0xf8000000-0xfc000000	Local PCI MEM
+   * 0xfc000000-0xfe000000	CPCI I/O
+   * 0xfe000000-0xff000000	Local PCI I/O
+   * 0xff000000-0xff201000	System configuration space
+   * 0xff400000-0xff500000	Local PCI bridge space
+   * 0xff500000-0xff600000	CPCI bridge space
+   * 0xfff00000-0xfff80000	Boot Flash
+   */
+
+#endif
diff --git a/board/pcippc2/i2c.c b/board/pcippc2/i2c.c
new file mode 100755
index 0000000..36b1d0f
--- /dev/null
+++ b/board/pcippc2/i2c.c
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include "hardware.h"
+#include "i2c.h"
+
+static void		i2c_start	(void);
+static void		i2c_stop	(void);
+static int		i2c_write	(u8		data);
+static void		i2c_read	(u8 *		data);
+
+static inline void	i2c_port_start  (void);
+static inline void	i2c_clock	(unsigned int	val);
+static inline void	i2c_data	(unsigned int	val);
+static inline unsigned int
+			i2c_in		(void);
+static inline void	i2c_write_bit	(unsigned int	val);
+static inline unsigned int
+			i2c_read_bit	(void);
+
+static inline void	i2c_udelay	(unsigned int	time);
+
+int i2c_read_byte (
+  u8 *			data,
+  u8			dev,
+  u8			offset)
+{
+  int			err = 0;
+
+  i2c_start();
+
+  err = ! i2c_write(dev);
+
+  if (! err)
+  {
+    err = ! i2c_write(offset);
+  }
+
+  if (! err)
+  {
+    i2c_start();
+  }
+
+  if (! err)
+  {
+    err = ! i2c_write(dev | 0x01);
+  }
+
+  if (! err)
+  {
+    i2c_read(data);
+  }
+
+  i2c_stop();
+
+  return ! err;
+}
+
+static inline void i2c_udelay (
+  unsigned int		time)
+{
+  int			v;
+
+  asm volatile("mtdec %0" : : "r" (time * ((CFG_BUS_CLK / 4) / 1000000)));
+
+  do
+  {
+    asm volatile("isync; mfdec %0" : "=r" (v));
+  } while (v >= 0);
+}
+
+  /* Low-level hardware access
+   */
+
+#define BIT_GPDATA		0x80000000
+#define BIT_GPCLK		0x40000000
+
+static inline void i2c_port_start (void)
+{
+  out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~(BIT_GPCLK | BIT_GPDATA));
+  out32(REG(CPC0, GPOUT), in32(REG(CPC0, GPOUT)) & ~(BIT_GPCLK | BIT_GPDATA));
+  iobarrier_rw();
+
+  i2c_udelay(1);
+}
+
+static inline void i2c_clock (
+  unsigned int		val)
+{
+  if (val)
+  {
+    out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPCLK);
+  }
+  else
+  {
+    out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPCLK);
+  }
+
+  iobarrier_rw();
+
+  i2c_udelay(1);
+}
+
+static inline void i2c_data (
+  unsigned int		val)
+{
+  if (val)
+  {
+    out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPDATA);
+  }
+  else
+  {
+    out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPDATA);
+  }
+
+  iobarrier_rw();
+
+  i2c_udelay(1);
+}
+
+static inline unsigned int i2c_in (void)
+{
+  unsigned int		val = ((in32(REG(CPC0, GPIN)) & BIT_GPDATA) != 0)?1:0;
+
+  iobarrier_rw();
+
+  return val;
+}
+
+
+  /* Protocol implementation
+   */
+
+static inline void i2c_write_bit (
+  unsigned int		val)
+{
+  i2c_data(val);
+  i2c_udelay(10);
+  i2c_clock(1);
+  i2c_udelay(10);
+  i2c_clock(0);
+  i2c_udelay(10);
+}
+
+static inline unsigned int i2c_read_bit (void)
+{
+  unsigned int		val;
+
+  i2c_data(1);
+  i2c_udelay(10);
+
+  i2c_clock(1);
+  i2c_udelay(10);
+
+  val = i2c_in();
+
+  i2c_clock(0);
+  i2c_udelay(10);
+
+  return val;
+}
+
+unsigned int i2c_reset (void)
+{
+  unsigned int		val;
+  int i;
+
+  i2c_port_start();
+
+  i=0;
+  do {
+    i2c_udelay(10);
+    i2c_clock(0);
+    i2c_udelay(10);
+    i2c_clock(1);
+    i2c_udelay(10);
+    val = i2c_in();
+    i++;
+  }  while ((i<9)&&(val==0));
+  return (val);
+}
+
+
+static void i2c_start (void)
+{
+  i2c_data(1);
+  i2c_clock(1);
+  i2c_udelay(10);
+  i2c_data(0);
+  i2c_udelay(10);
+  i2c_clock(0);
+  i2c_udelay(10);
+}
+
+static void i2c_stop (void)
+{
+  i2c_data(0);
+  i2c_udelay(10);
+  i2c_clock(1);
+  i2c_udelay(10);
+  i2c_data(1);
+  i2c_udelay(10);
+}
+
+static int i2c_write (
+  u8			data)
+{
+  unsigned int		i;
+
+  for (i = 0; i < 8; i++)
+  {
+    i2c_write_bit(data >> 7);
+    data <<= 1;
+  }
+
+  return i2c_read_bit() == 0;
+}
+
+static void i2c_read (
+  u8 *			data)
+{
+  unsigned int		i;
+  u8			val = 0;
+
+  for (i = 0; i < 8; i++)
+  {
+    val <<= 1;
+    val |= i2c_read_bit();
+  }
+
+  *data = val;
+  i2c_write_bit(1); /* NoAck */
+}
diff --git a/board/pcippc2/i2c.h b/board/pcippc2/i2c.h
new file mode 100755
index 0000000..1224b42
--- /dev/null
+++ b/board/pcippc2/i2c.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+#include <common.h>
+
+extern int	i2c_read_byte	(u8 *		data,
+				 u8		dev,
+				 u8 offset);
+
+extern unsigned int i2c_reset (void);
+
+
+#endif
diff --git a/board/pcippc2/ns16550.h b/board/pcippc2/ns16550.h
new file mode 100755
index 0000000..7023f13
--- /dev/null
+++ b/board/pcippc2/ns16550.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _NS16550_H_
+#define _NS16550_H_
+
+#define NS16550_RBR	0x00
+#define NS16550_IER	0x01
+#define NS16550_FCR	0x02
+#define NS16550_LCR	0x03
+#define NS16550_MCR	0x04
+#define NS16550_LSR	0x05
+#define NS16550_MSR	0x06
+#define NS16550_SCR	0x07
+
+#define NS16550_THR	NS16550_RBR
+#define NS16550_IIR	NS16550_FCR
+#define NS16550_DLL	NS16550_RBR
+#define NS16550_DLM	NS16550_IER
+
+#endif
diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c
new file mode 100755
index 0000000..231b505
--- /dev/null
+++ b/board/pcippc2/pcippc2.c
@@ -0,0 +1,245 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <linux/mtd/doc2000.h>
+#include <watchdog.h>
+#include <pci.h>
+
+#include "hardware.h"
+#include "pcippc2.h"
+#include "sconsole.h"
+#include "fpga_serial.h"
+
+#if defined(CONFIG_WATCHDOG)
+
+static int pcippc2_wdt_init_done = 0;
+
+void pcippc2_wdt_init (void);
+
+#endif
+
+  /* Check board identity
+   */
+int checkboard (void)
+{
+#ifdef CONFIG_PCIPPC2
+	puts ("Board: Gespac PCIPPC-2\n");
+#else
+	puts ("Board: Gespac PCIPPC-6\n");
+#endif
+	return 0;
+}
+
+  /* RAM size is stored in CPC0_RGBAN1
+   */
+u32 pcippc2_sdram_size (void)
+{
+	return in32 (REG (CPC0, RGBAN1));
+}
+
+long initdram (int board_type)
+{
+	return cpc710_ram_init ();
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	out32 (REG (CPC0, SPOR), 0);
+	iobarrier_rw ();
+	while (1);
+	/* notreached */
+	return (-1);
+}
+
+int board_early_init_f (void)
+{
+	out32 (REG (CPC0, RSTR), 0xC0000000);
+	iobarrier_rw ();
+
+	out32 (REG (CPC0, RSTR), 0xF0000000);
+	iobarrier_rw ();
+
+	out32 (REG (CPC0, UCTL), 0x00F80000);
+
+	out32 (REG (CPC0, SIOC0), 0x30000000);
+
+	out32 (REG (CPC0, ABCNTL), 0x00000000);
+
+	out32 (REG (CPC0, SESR), 0x00000000);
+	out32 (REG (CPC0, SEAR), 0x00000000);
+
+	/* Detect IBM Avignon CPC710 Revision */
+	if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P)
+		out32 (REG (CPC0, PGCHP), 0xA0000040);
+	else
+		out32 (REG (CPC0, PGCHP), 0x80800040);
+
+
+	out32 (REG (CPC0, ATAS), 0x709C2508);
+
+	iobarrier_rw ();
+
+	return 0;
+}
+
+void after_reloc (ulong dest_addr)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Jump to the main U-Boot board init code
+	 */
+	board_init_r ((gd_t *)gd, dest_addr);
+}
+
+int misc_init_r (void)
+{
+	pcippc2_fpga_init ();
+
+	pcippc2_cpci3264_init ();
+
+#if defined(CONFIG_WATCHDOG)
+	pcippc2_wdt_init ();
+#endif
+
+	fpga_serial_init (sconsole_get_baudrate ());
+
+	sconsole_putc   = fpga_serial_putc;
+	sconsole_puts   = fpga_serial_puts;
+	sconsole_getc   = fpga_serial_getc;
+	sconsole_tstc   = fpga_serial_tstc;
+	sconsole_setbrg = fpga_serial_setbrg;
+
+	sconsole_flush ();
+	return (0);
+}
+
+void pci_init_board (void)
+{
+	cpc710_pci_init ();
+
+	/* FPGA requires no retry timeouts to be enabled
+	 */
+	cpc710_pci_enable_timeout ();
+}
+
+void doc_init (void)
+{
+	doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC);
+}
+
+void pcippc2_cpci3264_init (void)
+{
+  pci_dev_t		bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
+
+  if (bdf == -1)
+  {
+    puts("Unable to find FPGA !\n");
+    hang();
+  }
+
+	if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000)
+	/* 32-bits Compact PCI bus - LSB bit */
+	{
+		iobarrier_rw();
+		out32(BRIDGE(CPCI, PCIDG), 0x40000000);	/* 32-bits bridge, Pipeline */
+		iobarrier_rw();
+	}
+}
+
+#if defined(CONFIG_WATCHDOG)
+
+void pcippc2_wdt_init (void)
+{
+	out16r (FPGA (WDT, PROG), 0xffff);
+	out8 (FPGA (WDT, CTRL), 0x1);
+
+	pcippc2_wdt_init_done = 1;
+}
+
+void pcippc2_wdt_done (void)
+{
+	out8 (FPGA (WDT, CTRL), 0x0);
+
+	pcippc2_wdt_init_done = 0;
+}
+
+void pcippc2_wdt_reset (void)
+{
+	if (pcippc2_wdt_init_done == 1)
+		out8 (FPGA (WDT, REFRESH), 0x56);
+}
+
+void watchdog_reset (void)
+{
+	int re_enable = disable_interrupts ();
+
+	pcippc2_wdt_reset ();
+	if (re_enable)
+		enable_interrupts ();
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	switch (argc) {
+	case 1:
+		printf ("Watchdog timer status is %s\n",
+			pcippc2_wdt_init_done == 1 ? "on" : "off");
+
+		return 0;
+	case 2:
+		if (!strcmp(argv[1],"on")) {
+			pcippc2_wdt_init();
+			printf("Watchdog timer now is on\n");
+
+			return 0;
+
+		} else if (!strcmp(argv[1],"off")) {
+			pcippc2_wdt_done();
+			printf("Watchdog timer now is off\n");
+
+			return 0;
+
+		} else
+			break;
+	default:
+		break;
+	}
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	wd,	2,	1,	do_wd,
+	"wd      - check and set watchdog\n",
+	"on   - switch watchDog on\n"
+	"wd off  - switch watchdog off\n"
+	"wd      - print current status\n"
+);
+
+#endif	/* CFG_CMD_BSP */
+#endif	/* CONFIG_WATCHDOG */
diff --git a/board/pcippc2/pcippc2.h b/board/pcippc2/pcippc2.h
new file mode 100755
index 0000000..3820bbe
--- /dev/null
+++ b/board/pcippc2/pcippc2.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCIPPC2_H_
+#define _PCIPPC2_H_
+
+#include <config.h>
+#include <common.h>
+
+#include "hardware.h"
+
+#define FPGA(r, p)	(pcippc2_fpga0_phys + HW_FPGA0_##r##_##p)
+#define UART(r)		(pcippc2_fpga0_phys + HW_FPGA0_UART1 + NS16550_##r * 4)
+#define RTC(r)		(pcippc2_fpga1_phys + HW_FPGA1_RTC + r)
+
+extern u32		pcippc2_fpga0_phys;
+extern u32		pcippc2_fpga1_phys;
+
+extern u32	pcippc2_sdram_size		(void);
+
+extern void 	pcippc2_fpga_init		(void);
+
+extern void 	pcippc2_cpci3264_init	(void);
+
+extern void 	cpc710_pci_init			(void);
+extern void	cpc710_pci_enable_timeout	(void);
+
+extern unsigned long
+		cpc710_ram_init			(void);
+
+#endif
diff --git a/board/pcippc2/pcippc2_fpga.c b/board/pcippc2/pcippc2_fpga.c
new file mode 100755
index 0000000..7f6739d
--- /dev/null
+++ b/board/pcippc2/pcippc2_fpga.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include "pci.h"
+
+#include "hardware.h"
+#include "pcippc2.h"
+
+u32		pcippc2_fpga0_phys;
+u32		pcippc2_fpga1_phys;
+
+void pcippc2_fpga_init (void)
+{
+  pci_dev_t		bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
+  unsigned int		addr;
+  u16			cmd;
+
+  if (bdf == -1)
+  {
+    puts("Unable to find FPGA !\n");
+    hang();
+  }
+
+  pci_read_config_word(bdf, PCI_COMMAND, &cmd);
+  if ((cmd & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) != (PCI_COMMAND_MEMORY | PCI_COMMAND_IO))
+  {
+    puts("FPGA is not configured !\n");
+    hang();
+  }
+
+  pci_read_config_dword(bdf, PCI_BASE_ADDRESS_0, &addr);
+  if (addr & 0x1)
+  {
+      /* IO space
+       */
+    pcippc2_fpga0_phys = pci_io_to_phys(bdf, addr & 0xfffffffc);
+  }
+  else
+  {
+      /* Memory space
+       */
+    pcippc2_fpga0_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0);
+  }
+
+  pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
+  if (addr & 0x1)
+  {
+      /* IO space
+       */
+    pcippc2_fpga1_phys = pci_io_to_phys(bdf, addr & 0xfffffffc);
+  }
+  else
+  {
+      /* Memory space
+       */
+    pcippc2_fpga1_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0);
+  }
+
+    /* Interrupts are not used
+     */
+  out32(FPGA(INT, INTR_MASK), 0xffffffff);
+  iobarrier_rw();
+}
diff --git a/board/pcippc2/pcippc2_fpga.h b/board/pcippc2/pcippc2_fpga.h
new file mode 100755
index 0000000..850c331
--- /dev/null
+++ b/board/pcippc2/pcippc2_fpga.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCIPPC2_FPGA_H_
+#define _PCIPPC2_FPGA_H_
+
+#define FPGA_VENDOR_ID			0x1310
+#define FPGA_DEVICE_ID			0x000d
+
+#define HW_FPGA0_INT			0x0000
+#define HW_FPGA0_BOARD		0x0060
+#define HW_FPGA0_UART1			0x0080
+#define HW_FPGA0_UART2			0x0100
+#define HW_FPGA0_RTC			0x2000
+#define HW_FPGA0_DOC			0x4000
+#define HW_FPGA1_RTC			0x0000
+#define HW_FPGA1_DOC			0x4000
+
+#define HW_FPGA0_INT_INTR_MASK		0x30
+#define HW_FPGA0_INT_INTR_STATUS	0x34
+#define HW_FPGA0_INT_INTR_EOI		0x40
+#define HW_FPGA0_INT_SERIAL_CONFIG	0x5c
+
+#define HW_FPGA0_WDT_CTRL		0x44
+#define HW_FPGA0_WDT_PROG		0x48
+#define HW_FPGA0_WDT_VAL		0x4c
+#define HW_FPGA0_WDT_REFRESH		0x50
+
+#endif
diff --git a/board/pcippc2/sconsole.c b/board/pcippc2/sconsole.c
new file mode 100755
index 0000000..a9f2b29
--- /dev/null
+++ b/board/pcippc2/sconsole.c
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+
+#include "sconsole.h"
+
+void	(*sconsole_putc) (char) = 0;
+void	(*sconsole_puts) (const char *) = 0;
+int	(*sconsole_getc) (void) = 0;
+int	(*sconsole_tstc) (void) = 0;
+void	(*sconsole_setbrg) (void) = 0;
+
+int serial_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+	sb->pos  = 0;
+	sb->size = 0;
+	sb->baud = gd->baudrate;
+	sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
+
+	return (0);
+}
+
+void serial_putc (char c)
+{
+	if (sconsole_putc) {
+		(*sconsole_putc) (c);
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		if (c) {
+			sb->data[sb->pos++] = c;
+			if (sb->pos == sb->max_size) {
+				sb->pos = 0;
+			}
+			if (sb->size < sb->max_size) {
+				sb->size++;
+			}
+		}
+	}
+}
+
+void serial_puts (const char *s)
+{
+	if (sconsole_puts) {
+		(*sconsole_puts) (s);
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		while (*s) {
+			sb->data[sb->pos++] = *s++;
+			if (sb->pos == sb->max_size) {
+				sb->pos = 0;
+			}
+			if (sb->size < sb->max_size) {
+				sb->size++;
+			}
+		}
+	}
+}
+
+int serial_getc (void)
+{
+	if (sconsole_getc) {
+		return (*sconsole_getc) ();
+	} else {
+		return 0;
+	}
+}
+
+int serial_tstc (void)
+{
+	if (sconsole_tstc) {
+		return (*sconsole_tstc) ();
+	} else {
+		return 0;
+	}
+}
+
+void serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (sconsole_setbrg) {
+		(*sconsole_setbrg) ();
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		sb->baud = gd->baudrate;
+	}
+}
+
+int sconsole_get_baudrate (void)
+{
+	sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+	return sb->baud;
+}
+
+void sconsole_flush (void)
+{
+	if (sconsole_putc) {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+		unsigned int end = sb->pos < sb->size
+				? sb->pos + sb->max_size - sb->size
+				: sb->pos - sb->size;
+
+		while (sb->size) {
+			(*sconsole_putc) (sb->data[end++]);
+			if (end == sb->max_size) {
+				end = 0;
+			}
+			sb->size--;
+		}
+	}
+}
diff --git a/board/pcippc2/sconsole.h b/board/pcippc2/sconsole.h
new file mode 100755
index 0000000..40fd75b
--- /dev/null
+++ b/board/pcippc2/sconsole.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SCONSOLE_H_
+#define _SCONSOLE_H_
+
+#include <config.h>
+
+typedef struct sconsole_buffer_s
+{
+  unsigned long		size;
+  unsigned long		max_size;
+  unsigned long 	pos;
+  unsigned long 	baud;
+  char			data [1];
+} sconsole_buffer_t;
+
+#define SCONSOLE_BUFFER		((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)
+
+extern void	(* sconsole_putc) 	(char);
+extern void	(* sconsole_puts) 	(const char *);
+extern int	(* sconsole_getc) 	(void);
+extern int	(* sconsole_tstc) 	(void);
+extern void	(* sconsole_setbrg) 	(void);
+
+extern void	sconsole_flush		(void);
+extern int 	sconsole_get_baudrate 	(void);
+
+#endif
diff --git a/board/pcippc2/u-boot.lds b/board/pcippc2/u-boot.lds
new file mode 100755
index 0000000..5c8cd5a
--- /dev/null
+++ b/board/pcippc2/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/74xx_7xx/start.o	(.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/*    . = env_offset; */
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/pleb2/Makefile b/board/pleb2/Makefile
new file mode 100755
index 0000000..95d9170
--- /dev/null
+++ b/board/pleb2/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= pleb2.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/pleb2/config.mk b/board/pleb2/config.mk
new file mode 100755
index 0000000..6958a63
--- /dev/null
+++ b/board/pleb2/config.mk
@@ -0,0 +1,3 @@
+TEXT_BASE =  0xa1F80000
+#TEXT_BASE = 0xa3080000
+#TEXT_BASE = 0
diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c
new file mode 100755
index 0000000..97271d9
--- /dev/null
+++ b/board/pleb2/flash.c
@@ -0,0 +1,814 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+/* environment.h defines the various CFG_ENV_... values in terms
+ * of whichever ones are given in the configuration file.
+ */
+#include <environment.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPWV * addr, flash_info_t * info);
+static void flash_reset (flash_info_t * info);
+static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data);
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect (flash_info_t * info);
+#endif
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b;
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",
+			size_b);
+	}
+
+	/* Do this again (was done already in flast_get_size), just
+	 * in case we move it when remap the FLASH.
+	 */
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#ifdef CFG_FLASH_PROTECTION
+	/* read the hardware protection status (if any) into the
+	 * protection array in flash_info.
+	 */
+	flash_sync_real_protect (&flash_info[0]);
+#endif
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_ADDR
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR_REDUND,
+		       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+		       &flash_info[0]);
+#endif
+
+	return (size_b);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset (flash_info_t * info)
+{
+	FPWV *base = (FPWV *) (info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector  */
+		int sect_size;	/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set sector offsets for bottom boot block type        */
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		   && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;	/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sect_size);
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		   && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
+
+		int sect_size;	/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set up sector start address table (top boot sector type) */
+		for (i = 0; i < info->sector_count - 3; i++)
+			info->start[i] = base + (i * sect_size);
+		i = info->sector_count - 1;
+		info->start[i--] =
+			base + (info->size - 0x00004000) * (sizeof (FPW) / 2);
+		info->start[i--] =
+			base + (info->size - 0x00006000) * (sizeof (FPW) / 2);
+		info->start[i--] =
+			base + (info->size - 0x00008000) * (sizeof (FPW) / 2);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	uchar *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_BM:
+		printf ("BRIGHT MICRO ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf ("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	} else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		fmt = "29LV800B%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV * addr, flash_info_t * info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[0x0555] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[0x02AA] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	addr[0x0555] = (FPW) 0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[0] & 0xff) {
+
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN)
+		switch (addr[1]) {
+
+		case (FPW) AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MiB        */
+
+		case (FPW) AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F800C3B:
+			info->flash_id += FLASH_28F800C3B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F800B3B:
+			info->flash_id += FLASH_INTEL800B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F160C3B:
+			info->flash_id += FLASH_28F160C3B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F160B3B:
+			info->flash_id += FLASH_INTEL160B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F320C3B:
+			info->flash_id += FLASH_28F320C3B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F320B3B:
+			info->flash_id += FLASH_INTEL320B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F640C3B:
+			info->flash_id += FLASH_28F640C3B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F640B3B:
+			info->flash_id += FLASH_INTEL640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* => no or unknown flash */
+		}
+
+	flash_get_offsets ((ulong) addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset (info);
+
+	return (info->size);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_sync_real_protect (flash_info_t * info)
+{
+	FPWV *addr = (FPWV *) (info->start[0]);
+	FPWV *sect;
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		/* check for protected sectors */
+		*addr = (FPW) 0x00900090;
+		for (i = 0; i < info->sector_count; i++) {
+			/* read sector protection at sector address, (A7 .. A0) = 0x02.
+			 * D0 = 1 for each device if protected.
+			 * If at least one device is protected the sector is marked
+			 * protected, but mixed protected and  unprotected devices
+			 * within a sector should never happen.
+			 */
+			sect = (FPWV *) (info->start[i]);
+			info->protect[i] =
+				(sect[2] & (FPW) (0x00010001)) ? 1 : 0;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset (info);
+		break;
+
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+	default:
+		/* no hardware protect that we support */
+		break;
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	reset_timer_masked ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		reset_timer_masked ();
+		last = 0;
+
+		addr = (FPWV *) (info->start[sect]);
+		if (intel) {
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;	/* first address in bank */
+
+			base = (FPWV *) (info->start[0]);
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			base[0x0555] = (FPW) 0x00800080;	/* erase mode */
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			*addr = (FPW) 0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			if ((now =
+			     get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase        */
+					*addr = (FPW) 0x00B000B0;
+				}
+
+				flash_reset (info);	/* reset to read mode */
+				rcode = 1;	/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1 * CFG_HZ) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+
+		flash_reset (info);	/* reset to read mode   */
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;		/* number of bytes to program in current word         */
+	int left;		/* number of bytes left to program                    */
+	int i, res;
+
+	for (left = cnt, res = 0;
+	     left > 0 && res == 0;
+	     addr += sizeof (data), left -= sizeof (data) - bytes) {
+
+		bytes = addr & (sizeof (data) - 1);
+		addr &= ~(sizeof (data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+#ifdef CFG_LITTLE_ENDIAN
+		for (i = 0; i < sizeof (data); i++) {
+			data >>= 8;
+			if (i < bytes || i - bytes >= left)
+				data += (*((uchar *) addr + i)) << 24;
+			else
+				data += (*src++) << 24;
+		}
+#else
+		for (i = 0; i < sizeof (data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *) addr + i);
+			else
+				data += *src++;
+		}
+#endif
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd (info, (FPWV *) addr, data);
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel (info, (FPWV *) addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf ("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
+{
+	int flag;
+	int res = 0;		/* result, assume success       */
+	FPWV *base;		/* first address in flash bank  */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+
+	base = (FPWV *) (info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+	base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+	base[0x0555] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	reset_timer_masked ();
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data)
+{
+	int flag;
+	int res = 0;		/* result, assume success       */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+	*dest = (FPW) 0x00400040;	/* program setup                */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	reset_timer_masked ();
+
+	while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00B000B0;	/* Suspend program      */
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW) 0x00100010))
+		res = 1;	/* write failed, time out error is close enough */
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+
+	return (res);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset (info);	/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset (info);	/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect (info);
+		break;
+
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
diff --git a/board/pleb2/lowlevel_init.S b/board/pleb2/lowlevel_init.S
new file mode 100755
index 0000000..add2c53
--- /dev/null
+++ b/board/pleb2/lowlevel_init.S
@@ -0,0 +1,488 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+	.macro CPWAIT reg
+	mrc	p15,0,\reg,c2,c0,0
+	mov	\reg,\reg
+	sub	pc,pc,#4
+	.endm
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	r10, lr
+
+	/* Set up GPIO pins first */
+
+	ldr	r0,   =GPSR0
+	ldr	r1,   =CFG_GPSR0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPSR1
+	ldr	r1,   =CFG_GPSR1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPSR2
+	ldr	r1,   =CFG_GPSR2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPCR0
+	ldr	r1,   =CFG_GPCR0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPCR1
+	ldr	r1,   =CFG_GPCR1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPCR2
+	ldr	r1,   =CFG_GPCR2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GRER0
+	ldr	r1,   =CFG_GRER0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GRER1
+	ldr	r1,   =CFG_GRER1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GRER2
+	ldr	r1,   =CFG_GRER2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GFER0
+	ldr	r1,   =CFG_GFER0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GFER1
+	ldr	r1,   =CFG_GFER1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GFER2
+	ldr	r1,   =CFG_GFER2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPDR0
+	ldr	r1,   =CFG_GPDR0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPDR1
+	ldr	r1,   =CFG_GPDR1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPDR2
+	ldr	r1,   =CFG_GPDR2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR0_L
+	ldr	r1,   =CFG_GAFR0_L_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR0_U
+	ldr	r1,   =CFG_GAFR0_U_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR1_L
+	ldr	r1,   =CFG_GAFR1_L_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR1_U
+	ldr	r1,   =CFG_GAFR1_U_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR2_L
+	ldr	r1,   =CFG_GAFR2_L_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR2_U
+	ldr	r1,   =CFG_GAFR2_U_VAL
+	str	r1,   [r0]
+
+	/* enable GPIO pins */
+	ldr	r0,   =PSSR
+	ldr	r1,   =CFG_PSSR_VAL
+	str	r1,   [r0]
+
+
+/*********************************************************************
+    Initlialize Memory Controller
+
+    See PXA250 Operating System Developer's Guide
+
+    pause for 200 uSecs- allow internal clocks to settle
+    *Note: only need this if hard reset... doing it anyway for now
+*/
+
+	@ Step 1
+	@ ---- Wait 200 usec
+	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+mem_init:
+	@ get memory controller base address
+	ldr	r1,  =MEMC_BASE
+
+@****************************************************************************
+@  Step 2
+@
+
+	@ Step 2a
+	@ write msc0, read back to ensure data latches
+	@
+	ldr	r2,   =CFG_MSC0_VAL
+	str	r2,   [r1, #MSC0_OFFSET]
+	ldr	r2,   [r1, #MSC0_OFFSET]
+
+	@ write msc1
+	ldr	r2,  =CFG_MSC1_VAL
+	str	r2,  [r1, #MSC1_OFFSET]
+	ldr	r2,  [r1, #MSC1_OFFSET]
+
+	@ write msc2
+	ldr	r2,  =CFG_MSC2_VAL
+	str	r2,  [r1, #MSC2_OFFSET]
+	ldr	r2,  [r1, #MSC2_OFFSET]
+
+
+@ Step 2b
+	@ write mecr
+	ldr	r2,  =CFG_MECR_VAL
+	str	r2,  [r1, #MECR_OFFSET]
+
+	@ write mcmem0
+	ldr	r2,  =CFG_MCMEM0_VAL
+	str	r2,  [r1, #MCMEM0_OFFSET]
+
+	@ write mcmem1
+	ldr	r2,  =CFG_MCMEM1_VAL
+	str	r2,  [r1, #MCMEM1_OFFSET]
+
+	@ write mcatt0
+	ldr	r2,  =CFG_MCATT0_VAL
+	str	r2,  [r1, #MCATT0_OFFSET]
+
+	@ write mcatt1
+	ldr	r2,  =CFG_MCATT1_VAL
+	str	r2,  [r1, #MCATT1_OFFSET]
+
+	@ write mcio0
+	ldr	r2,  =CFG_MCIO0_VAL
+	str	r2,  [r1, #MCIO0_OFFSET]
+
+	@ write mcio1
+	ldr	r2,  =CFG_MCIO1_VAL
+	str	r2,  [r1, #MCIO1_OFFSET]
+
+@ Step 2c
+	@ fly-by-dma is defeatured on this part
+	@ write flycnfg
+	@ldr	r2,  =CFG_FLYCNFG_VAL
+	@str	r2,  [r1, #FLYCNFG_OFFSET]
+
+/* FIXME Does this sequence really make sense */
+#ifdef REDBOOT_WAY
+	@ Step 2d
+	@ get the mdrefr settings
+	ldr	r3,  =CFG_MDREFR_VAL
+
+	@ extract DRI field (we need a valid DRI field)
+	@
+	ldr	r2,  =0xFFF
+
+	@ valid DRI field in r3
+	@
+	and	r3,  r3,  r2
+
+	@ get the reset state of MDREFR
+	@
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	@ clear the DRI field
+	@
+	bic	r4,  r4,  r2
+
+	@ insert the valid DRI field loaded above
+	@
+	orr	r4,  r4,  r3
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@ *Note: preserve the mdrefr value in r4 *
+
+@****************************************************************************
+@  Step 3
+@
+@ NO SRAM
+
+	mov	pc, r10
+
+
+@****************************************************************************
+@  Step 4
+@
+
+	@ Assumes previous mdrefr value in r4, if not then read current mdrefr
+
+	@ clear the free-running clock bits
+	@ (clear K0Free, K1Free, K2Free
+	@
+	bic	r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
+
+	@ set K0RUN for CPLD clock
+	@
+	orr	r4,  r4,  #0x00002000
+
+	@ set K1RUN if bank 0 installed
+	@
+	orr	r4,  r4,  #0x00010000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	@ deassert SLFRSH
+	@
+	bic	r4,  r4,  #0x00400000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@ assert E1PIN
+	@
+	orr	r4,  r4,  #0x00008000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+	nop
+	nop
+#else
+	@ Step 2d
+	@ get the mdrefr settings
+	ldr	r3,  =CFG_MDREFR_VAL
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@  Step 4
+
+	@ set K0RUN for CPLD clock
+	@
+	orr	r4,  r4,  #0x00002000
+
+	@ set K1RUN for bank 0
+	@
+	orr	r4,  r4,  #0x00010000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	@ deassert SLFRSH
+	@
+	bic	r4,  r4,  #0x00400000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@ assert E1PIN
+	@
+	orr	r4,  r4,  #0x00008000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+	nop
+	nop
+#endif
+
+	@ Step 4d
+	@ fetch platform value of mdcnfg
+	@
+	ldr	r2,  =CFG_MDCNFG_VAL
+
+	@ disable all sdram banks
+	@
+	bic	r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
+	bic	r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+
+	@ program banks 0/1 for bus width
+	@
+	bic	r2,  r2,  #MDCNFG_DWID0	     @0=32-bit
+
+	@ write initial value of mdcnfg, w/o enabling sdram banks
+	@
+	str	r2,  [r1, #MDCNFG_OFFSET]
+
+	@ Step 4e
+	@ pause for 200 uSecs
+	@
+	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
+	1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+	/* Why is this here??? */
+	mov	r0, #0x78		 @turn everything off
+	mcr	p15, 0, r0, c1, c0, 0	   @(caches off, MMU off, etc.)
+
+	@ Step 4f
+	@ Access memory *not yet enabled* for CBR refresh cycles (8)
+	@ - CBR is generated for all banks
+
+	ldr	r2, =CFG_DRAM_BASE
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+
+	@ Step 4g
+	@get memory controller base address
+	@
+	ldr	r1,  =MEMC_BASE
+
+	@fetch current mdcnfg value
+	@
+	ldr	r3,  [r1, #MDCNFG_OFFSET]
+
+	@enable sdram bank 0 if installed (must do for any populated bank)
+	@
+	orr	r3,  r3,  #MDCNFG_DE0
+
+	@write back mdcnfg, enabling the sdram bank(s)
+	@
+	str	r3,  [r1, #MDCNFG_OFFSET]
+
+	@ Step 4h
+	@ write mdmrs
+	@
+	ldr	r2,  =CFG_MDMRS_VAL
+	str	r2,  [r1, #MDMRS_OFFSET]
+
+	@ Done Memory Init
+
+	/*SET_LED 6 */
+
+	@********************************************************************
+	@ Disable (mask) all interrupts at the interrupt controller
+	@
+
+	@ clear the interrupt level register (use IRQ, not FIQ)
+	@
+	mov	r1, #0
+	ldr	r2,  =ICLR
+	str	r1,  [r2]
+
+	@ Set interrupt mask register
+	@
+	ldr	r1,  =CFG_ICMR_VAL
+	ldr	r2,  =ICMR
+	str	r1,  [r2]
+
+	@ ********************************************************************
+	@ Disable the peripheral clocks, and set the core clock
+	@
+
+	@ Turn Off ALL on-chip peripheral clocks for re-configuration
+	@
+	ldr	r1,  =CKEN
+	mov	r2,  #0
+	str	r2,  [r1]
+
+	@ set core clocks
+	@
+	ldr	r2,  =CFG_CCCR_VAL
+	ldr	r1,  =CCCR
+	str	r2,  [r1]
+
+	#ifdef ENABLE32KHZ
+	@ enable the 32Khz oscillator for RTC and PowerManager
+	@
+	ldr	r1,  =OSCC
+	mov	r2,  #OSCC_OON
+	str	r2,  [r1]
+
+	@ NOTE:	 spin here until OSCC.OOK get set,
+	@	 meaning the PLL has settled.
+	@
+60:
+	ldr	r2, [r1]
+	ands	r2, r2, #1
+	beq	60b
+#endif
+
+	@ Turn on needed clocks
+	@
+	ldr	r1,  =CKEN
+	ldr	r2,  =CFG_CKEN_VAL
+	str	r2,  [r1]
+
+	/*SET_LED 7 */
+
+/* Is this needed???? */
+#define NODEBUG
+#ifdef NODEBUG
+   /*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+
+#endif
+
+	mov	pc, r10
+
+@ End lowlevel_init
diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c
new file mode 100755
index 0000000..ce9245c
--- /dev/null
+++ b/board/pleb2/pleb2.c
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm-arm/mach-types.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of Lubbock-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PLEB2;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
diff --git a/board/pleb2/u-boot.lds b/board/pleb2/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/pleb2/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/pm520/Makefile b/board/pm520/Makefile
new file mode 100755
index 0000000..8cf0d7d
--- /dev/null
+++ b/board/pm520/Makefile
@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/pm520/config.mk b/board/pm520/config.mk
new file mode 100755
index 0000000..ad689f3
--- /dev/null
+++ b/board/pm520/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# PM520 board
+#
+
+TEXT_BASE = 0xfff00000
+# TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/pm520/flash.c b/board/pm520/flash.c
new file mode 100755
index 0000000..3868221
--- /dev/null
+++ b/board/pm520/flash.c
@@ -0,0 +1,655 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               		(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               		(x)
+#endif
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT  0x00890089
+#define INTEL_ALT     0x00B000B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x00100010
+#define INTEL_ERASE   0x00200020
+#define INTEL_CLEAR   0x00500050
+#define INTEL_LOCKBIT 0x00600060
+#define INTEL_PROTECT 0x00010001
+#define INTEL_STATUS  0x00700070
+#define INTEL_READID  0x00900090
+#define INTEL_CONFIRM 0x00D000D0
+#define INTEL_RESET   0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x00800080
+#define INTEL_OK       0x00800080
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	extern void flash_preinit(void);
+	extern void flash_afterinit(ulong, ulong);
+	ulong flashbase = CFG_FLASH_BASE;
+
+	flash_preinit();
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			memset(&flash_info[i], 0, sizeof(flash_info_t));
+			flash_get_size ((FPW *) flashbase, &flash_info[i]);
+			flash_get_offsets (flash_info[i].start[0], &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+
+		/* get the h/w and s/w protection status in sync */
+		flash_sync_real_protect(&flash_info[i]);
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#ifndef CONFIG_BOOT_ROM
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_MONITOR_BASE,
+			CFG_MONITOR_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+#endif
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+#endif
+
+	flash_afterinit(flash_info[0].start[0], flash_info[0].size);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	udelay(100);
+
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		info->start[0] = CFG_FLASH_BASE;
+		break;				/* => 32 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		info->start[0] = CFG_FLASH_BASE + 0x01000000;
+		break;				/* => 16 MB     */
+
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x800000;
+		info->start[0] = CFG_FLASH_BASE + 0x01800000;
+		break;				/* => 8 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+
+	case FLASH_28F128J3A:
+	case FLASH_28F640J3A:
+	case FLASH_28F320J3A:
+		for (i = 0; i < info->sector_count; ++i) {
+			info->protect[i] = intel_sector_protected(info, i);
+		}
+		break;
+	default:
+		/* no h/w protect support */
+		break;
+	}
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+	FPWV *addr;
+	FPWV *lock_conf_addr;
+	ulong start;
+	unsigned char ret;
+
+	/*
+	 * first, wait for the WSM to be finished. The rationale for
+	 * waiting for the WSM to become idle for at most
+	 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * because of: (1) erase, (2) program or (3) lock bit
+	 * configuration. So we just wait for the longest timeout of
+	 * the (1)-(3), i.e. the erase timeout.
+	 */
+
+	/* wait at least 35ns (W12) before issuing Read Status Register */
+	udelay(1);
+	addr = (FPWV *) info->start[sector];
+	*addr = (FPW) INTEL_STATUS;
+
+	start = get_timer (0);
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+			*addr = (FPW) INTEL_RESET; /* restore read mode */
+			printf("WSM busy too long, can't get prot status\n");
+			return 1;
+		}
+	}
+
+	/* issue the Read Identifier Codes command */
+	*addr = (FPW) INTEL_READID;
+
+	/* wait at least 35ns (W12) before reading */
+	udelay(1);
+
+	/* Intel example code uses offset of 2 for 16 bit flash */
+	lock_conf_addr = (FPWV *) info->start[sector] + 2;
+	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+	/* put flash back in read mode */
+	*addr = (FPW) INTEL_RESET;
+
+	return ret;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			start = get_timer(0);
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	start = get_timer(0);
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect (flash_info_t *info, long sector, int prot)
+{
+	ulong start;
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
+	}
+
+	start = get_timer(0);
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 * WARNING: code below re-locks sectors only for one bank (info).
+	 * This causes problems on boards where several banks share
+	 * the same chip, as sectors in othere banks will be unlocked
+	 * but not re-locked. It works fine on pm520 though, as there
+	 * is only one chip and one bank.
+	 */
+	if (!prot)
+	{
+		for (i = 0; i < info->sector_count; i++)
+		{
+			if (info->protect[i])
+			{
+				start = get_timer(0);
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
+				{
+					if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT)
+					{
+						printf("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+		/*
+		 * get the s/w sector protection status in sync with the h/w,
+		 * in case something went wrong during the re-locking.
+		 */
+		flash_sync_real_protect(info); /* resets flash to read  mode */
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h
new file mode 100755
index 0000000..f650faa
--- /dev/null
+++ b/board/pm520/mt46v16m16-75.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h
new file mode 100755
index 0000000..ffdf039
--- /dev/null
+++ b/board/pm520/mt48lc16m16a2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c
new file mode 100755
index 0000000..d4cc5cb
--- /dev/null
+++ b/board/pm520/pm520.c
@@ -0,0 +1,322 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
+int checkboard (void)
+{
+#if defined(CONFIG_MPC5200)
+	puts ("Board: MicroSys PM520 \n");
+#elif defined(CONFIG_MGT5100)
+	puts ("Board: MicroSys PM510 \n");
+#endif
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+#if defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+#endif
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+void flash_afterinit(ulong start, ulong size)
+{
+#if defined(CONFIG_BOOT_ROM)
+	/* adjust mapping */
+	*(vu_long *)MPC5XXX_CS1_START =
+			START_REG(start);
+	*(vu_long *)MPC5XXX_CS1_STOP =
+			STOP_REG(start, size);
+#else
+	/* adjust mapping */
+	*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(start);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(start, size);
+#endif
+}
+
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	/* adjust flash start */
+	gd->bd->bi_flashstart = flash_info[0].start[0];
+	return (0);
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
diff --git a/board/pm520/u-boot.lds b/board/pm520/u-boot.lds
new file mode 100755
index 0000000..3cc2968
--- /dev/null
+++ b/board/pm520/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/pm826/Makefile b/board/pm826/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/pm826/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/pm826/config.mk b/board/pm826/config.mk
new file mode 100755
index 0000000..c93bad9
--- /dev/null
+++ b/board/pm826/config.mk
@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MicroSys PM826 board:
+#
+
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot 64-bit flash
+TEXT_BASE = 0xFF000000
+
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/pm826/flash.c b/board/pm826/flash.c
new file mode 100755
index 0000000..fee07cf
--- /dev/null
+++ b/board/pm826/flash.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write query command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00980098;
+	baseaddr[1] = 0x00980098;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3 or 640C3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/* protect monitor and environment sectors
+	 */
+
+#ifndef CONFIG_BOOT_ROM
+	/* If U-Boot is  booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE
+	 * but we shouldn't protect it.
+	 */
+
+# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+# endif
+#endif	/* CONFIG_BOOT_ROM */
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Start erase on unprotected sectors
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+		start = get_timer (0);
+		last = start;
+		if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+			flag = disable_interrupts ();
+
+			/* Erase the block
+			 */
+			addr[0] = 0x00200020;
+			addr[1] = 0x00200020;
+			addr[0] = 0x00D000D0;
+			addr[1] = 0x00D000D0;
+
+			/* re-enable interrupts if necessary
+			 */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms
+			 */
+			udelay (1000);
+
+			last = start;
+			while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+				if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout (erase suspended!)\n");
+					/* Suspend erase
+					 */
+					addr[0] = 0x00B000B0;
+					addr[1] = 0x00B000B0;
+					goto DONE;
+				}
+				/* show that we're waiting
+				 */
+				if ((now - last) > 1000) {	/* every second */
+					serial_putc ('.');
+					last = now;
+				}
+			}
+			if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+				printf ("*** ERROR: erase failed!\n");
+				goto DONE;
+			}
+		}
+		/* Clear status register and reset to read mode
+		 */
+		addr[0] = 0x00500050;
+		addr[1] = 0x00500050;
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, cc = cnt, res = 0;
+
+
+	for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+		l = (addr & 3);
+		addr &= ~3;
+
+		for (i = 0; i < 4; i++) {
+			v = (v << 8) + (i < l || i - l >= cc ?
+				*((unsigned char *) addr + i) : *src++);
+		}
+
+		if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+			break;
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c
new file mode 100755
index 0000000..7514cd7
--- /dev/null
+++ b/board/pm826/pm826.c
@@ -0,0 +1,330 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <pci.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXEN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXDV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* PA25 */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* PA24 */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* PA23 */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* PA22 */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD1*/
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* PA13 */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* PA12 */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* PA11 */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* PA10 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* PA9 */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* PA8 */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_DV  */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 TX_EN  */
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+#ifdef CONFIG_ETHER_ON_FCC2
+#error "SCC1 conflicts with FCC2"
+#endif
+	/* PB28 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+#else
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_ER */
+#endif
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PB14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC3 RXD */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   1,   1,   1,   1,   0,   0   }, /* SCC3 TXD */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* PC23 */
+	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXCK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK(2) */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RXCK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 TXCK */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 DCD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 DCD */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 CTS */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 DCD */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 CTS */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 DCD */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* PD30 */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 RTS */
+	/* PD22 */ {   1,   1,   0,   0,   0,   0   }, /* SCC4 RXD */
+	/* PD21 */ {   1,   1,   0,   1,   0,   0   }, /* SCC4 TXD */
+	/* PD20 */ {   0,   0,   1,   1,   0,   0   }, /* SCC4 RTS */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* PD9 */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* PD8 */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   1,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: PM826\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	ulong size8, size9;
+#endif
+	ulong psize = 32 * 1024 * 1024;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+					  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+					  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+						  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+#endif
+	return (psize);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/board/pm826/u-boot.lds b/board/pm826/u-boot.lds
new file mode 100755
index 0000000..05f29c6
--- /dev/null
+++ b/board/pm826/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/pm828/Makefile b/board/pm828/Makefile
new file mode 100755
index 0000000..b9ef0c0
--- /dev/null
+++ b/board/pm828/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/pm828/config.mk b/board/pm828/config.mk
new file mode 100755
index 0000000..e894af7
--- /dev/null
+++ b/board/pm828/config.mk
@@ -0,0 +1,37 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MicroSys PM828 board:
+#
+
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot 64-bit flash
+TEXT_BASE = 0x40000000
+
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/pm828/flash.c b/board/pm828/flash.c
new file mode 100755
index 0000000..1f21b3e
--- /dev/null
+++ b/board/pm828/flash.c
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write query command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00980098;
+	baseaddr[1] = 0x00980098;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3 or 640c3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/* protect monitor and environment sectors
+	 */
+
+#ifndef CONFIG_BOOT_ROM
+	/* If U-Boot is  booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE
+	 * but we shouldn't protect it.
+	 */
+
+# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+# endif
+#endif	/* CONFIG_BOOT_ROM */
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 M, bottom sector)\n");
+		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Start erase on unprotected sectors
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+		start = get_timer (0);
+		last = start;
+		if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+			flag = disable_interrupts ();
+
+			/* Erase the block
+			 */
+			addr[0] = 0x00200020;
+			addr[1] = 0x00200020;
+			addr[0] = 0x00D000D0;
+			addr[1] = 0x00D000D0;
+
+			/* re-enable interrupts if necessary
+			 */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms
+			 */
+			udelay (1000);
+
+			last = start;
+			while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+				if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout (erase suspended!)\n");
+					/* Suspend erase
+					 */
+					addr[0] = 0x00B000B0;
+					addr[1] = 0x00B000B0;
+					goto DONE;
+				}
+				/* show that we're waiting
+				 */
+				if ((now - last) > 1000) {	/* every second */
+					serial_putc ('.');
+					last = now;
+				}
+			}
+			if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+				printf ("*** ERROR: erase failed!\n");
+				goto DONE;
+			}
+		}
+		/* Clear status register and reset to read mode
+		 */
+		addr[0] = 0x00500050;
+		addr[1] = 0x00500050;
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, cc = cnt, res = 0;
+
+
+	for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+		l = (addr & 3);
+		addr &= ~3;
+
+		for (i = 0; i < 4; i++) {
+			v = (v << 8) + (i < l || i - l >= cc ?
+				*((unsigned char *) addr + i) : *src++);
+		}
+
+		if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+			break;
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c
new file mode 100755
index 0000000..3193274
--- /dev/null
+++ b/board/pm828/pm828.c
@@ -0,0 +1,363 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <pci.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 TXEN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXDV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* PA25 */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* PA24 */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* PA23 */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* PA22 */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD1*/
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* PA13 */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* PA12 */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* PA11 */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* PA10 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* PA9 */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* PA8 */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_DV  */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 TX_EN  */
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+#ifdef CONFIG_ETHER_ON_FCC2
+#error "SCC1 conflicts with FCC2"
+#endif
+	/* PB28 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+#else
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RX_ER */
+#endif
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PB14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC3 RXD */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   1,   1,   1,   1,   0,   0   }, /* SCC3 TXD */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* PC23 */
+	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 RXCK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 TXCK(2) */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 RXCK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 TXCK */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 DCD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* SCC2 DCD */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 CTS */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 DCD */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 CTS */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* SCC4 DCD */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* PD30 */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* SCC3 RTS */
+	/* PD22 */ {   1,   1,   0,   0,   0,   0   }, /* SCC4 RXD */
+	/* PD21 */ {   1,   1,   0,   1,   0,   0   }, /* SCC4 TXD */
+	/* PD20 */ {   0,   0,   1,   1,   0,   0   }, /* SCC4 RTS */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* PD9 */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* PD8 */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   1,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: PM828\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile ulong cnt, val;
+	volatile ulong *addr;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	int i;
+	ulong save[32];				/* to make test non-destructive */
+	ulong maxsize;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	/*
+	 * Check memory range for valid RAM. A simple memory test determines
+	 * the actually available RAM size between addresses `base' and
+	 * `base + maxsize'. Some (not all) hardware errors are detected:
+	 * - short between address lines
+	 * - short between data lines
+	 */
+	i = 0;
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *) base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if ((val = *addr) != 0) {
+		*addr = save[i];
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;	/* pointer arith! */
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+			/* Write the actual size to ORx
+			 */
+			*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
+			return (cnt * sizeof (long));
+		}
+	}
+	return (maxsize);
+}
+
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	ulong size8, size9;
+#endif
+	ulong psize = 32 * 1024 * 1024;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+					  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+					  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+						  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+#endif
+	return (psize);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif
diff --git a/board/pm828/u-boot.lds b/board/pm828/u-boot.lds
new file mode 100755
index 0000000..928c1cf
--- /dev/null
+++ b/board/pm828/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/pm854/Makefile b/board/pm854/Makefile
new file mode 100755
index 0000000..7828166
--- /dev/null
+++ b/board/pm854/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/pm854/config.mk b/board/pm854/config.mk
new file mode 100755
index 0000000..7d58d6e
--- /dev/null
+++ b/board/pm854/config.mk
@@ -0,0 +1,33 @@
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# pm854 board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/pm854/init.S b/board/pm854/init.S
new file mode 100755
index 0000000..ade5d6e
--- /dev/null
+++ b/board/pm854/init.S
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	64M	FLASH (8,16,32 or 64 MB)
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 7:	256M	DDR
+	 * 0x00000000	256M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+#endif
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xfc00_0000     0xffff_ffff     FLASH (boot bank)       64M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x05
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4
+	entry_end
diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c
new file mode 100755
index 0000000..94c492f
--- /dev/null
+++ b/board/pm854/pm854.c
@@ -0,0 +1,296 @@
+ /*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+int board_early_init_f (void)
+{
+#if defined(CONFIG_PCI)
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+    pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+
+    return 0;
+}
+
+int checkboard (void)
+{
+	puts("Board: MicroSys PM854\n");
+
+#ifdef CONFIG_PCI
+	printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+	       CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf("    PCI1: disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    int i,x;
+
+	    x = 10;
+
+	    /*
+	     * Work around to stabilize DDR DLL
+	     */
+	    gur->ddrdllcr = 0x81000000;
+	    asm("sync;isync;msync");
+	    udelay (200);
+	    while (gur->ddrdllcr != 0x81000100)
+	    {
+	    	gur->devdisr = gur->devdisr | 0x00010000;
+		asm("sync;isync;msync");
+		for (i=0; i<x; i++)
+		    ;
+		gur->devdisr = gur->devdisr & 0xfff7ffff;
+		asm("sync;isync;msync");
+		x++;
+	    }
+	}
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	puts("    DDR: ");
+	return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_pm854_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_pm854_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds
new file mode 100755
index 0000000..fbfc65a
--- /dev/null
+++ b/board/pm854/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/pm854/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/pm854/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/pm856/Makefile b/board/pm856/Makefile
new file mode 100755
index 0000000..5d8ea34
--- /dev/null
+++ b/board/pm856/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/pm856/config.mk b/board/pm856/config.mk
new file mode 100755
index 0000000..1f98b33
--- /dev/null
+++ b/board/pm856/config.mk
@@ -0,0 +1,33 @@
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# PM856 board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/pm856/init.S b/board/pm856/init.S
new file mode 100755
index 0000000..ade5d6e
--- /dev/null
+++ b/board/pm856/init.S
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	64M	Non-cacheable, guarded
+	 * 0xfc000000	64M	FLASH (8,16,32 or 64 MB)
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 7:	256M	DDR
+	 * 0x00000000	256M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+#endif
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xfc00_0000     0xffff_ffff     FLASH (boot bank)       64M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x05
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4
+	entry_end
diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c
new file mode 100755
index 0000000..5044708
--- /dev/null
+++ b/board/pm856/pm856.c
@@ -0,0 +1,449 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+long int fixed_sdram(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   0,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   1,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+
+int board_early_init_f (void)
+{
+    return 0;
+}
+
+void reset_phy (void)
+{
+}
+
+
+int checkboard (void)
+{
+	puts("Board: MicroSys PM856\n");
+
+#ifdef CONFIG_PCI
+	printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+	       CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf("    PCI1: disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    int i,x;
+
+	    x = 10;
+
+	    /*
+	     * Work around to stabilize DDR DLL
+	     */
+	    gur->ddrdllcr = 0x81000000;
+	    asm("sync;isync;msync");
+	    udelay (200);
+	    while (gur->ddrdllcr != 0x81000100)
+	    {
+	    	gur->devdisr = gur->devdisr | 0x00010000;
+		asm("sync;isync;msync");
+		for (i=0; i<x; i++)
+		    ;
+		gur->devdisr = gur->devdisr & 0xfff7ffff;
+		asm("sync;isync;msync");
+		x++;
+	    }
+	}
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm("sync;isync;msync");
+	}
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
diff --git a/board/pm856/u-boot.lds b/board/pm856/u-boot.lds
new file mode 100755
index 0000000..e946a8e
--- /dev/null
+++ b/board/pm856/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2005 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/pm856/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/pm856/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/pn62/Makefile b/board/pn62/Makefile
new file mode 100755
index 0000000..e85d4fd
--- /dev/null
+++ b/board/pn62/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS =  $(BOARD).o cmd_pn62.o misc.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c
new file mode 100755
index 0000000..3ea068d
--- /dev/null
+++ b/board/pn62/cmd_pn62.c
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <command.h>
+#include "pn62.h"
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
+
+/*
+ * Command led: controls the various LEDs 0..11 on the PN62 card.
+ */
+int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    unsigned int number, function;
+
+    if (argc != 3) {
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+    }
+    number = simple_strtoul(argv[1], NULL, 10);
+    if (number > PN62_LED_MAX)
+	return 1;
+    function = simple_strtoul(argv[2], NULL, 16);
+    set_led (number, function);
+    return 0;
+}
+U_BOOT_CMD(
+	led    ,	3,	1,	do_led,
+	"led     - set LED 0..11 on the PN62 board\n",
+	"i fun\n"
+	"    - set 'i'th LED to function 'fun'\n"
+);
+
+/*
+ * Command loadpci: loads a image over PCI.
+ */
+#define CMD_MOVE_WINDOW 0x1
+#define CMD_BOOT_IMAGE  0x2
+
+int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    char *s;
+    ulong addr = 0, count = 0;
+    u32 off;
+    int cmd, rcode = 0;
+
+    /* pre-set load_addr */
+    if ((s = getenv("loadaddr")) != NULL) {
+	addr = simple_strtoul(s, NULL, 16);
+    }
+
+    switch (argc) {
+    case 1:
+	break;
+    case 2:
+	addr = simple_strtoul(argv[1], NULL, 16);
+	break;
+    default:
+       printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+    }
+
+    printf ("## Ready for image download ...\n");
+
+    show_startup_phase(12);
+
+    while (1) {
+	/* Alive indicator */
+	i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY);
+
+	/* Toggle status LEDs */
+	cmd = (count / 200) % 4; /* downscale */
+	set_led(4, cmd == 0 ? LED_1 : LED_0);
+	set_led(5, cmd == 1 ? LED_1 : LED_0);
+	set_led(6, cmd == 2 ? LED_1 : LED_0);
+	set_led(7, cmd == 3 ? LED_1 : LED_0);
+	udelay(1000);
+	count++;
+
+	cmd = i2155x_read_scrapad(BOOT_CMD);
+
+	if (cmd == BOOT_CMD_MOVE) {
+	    off = i2155x_read_scrapad(BOOT_DATA);
+	    off += addr;
+	    i2155x_set_bar_base(3, off);
+	    printf ("## BAR3 Addr moved = 0x%08x\n", off);
+	    i2155x_write_scrapad(BOOT_CMD, ~cmd);
+	    show_startup_phase(13);
+	}
+	else if (cmd == BOOT_CMD_BOOT) {
+	    set_led(4, LED_1);
+	    set_led(5, LED_1);
+	    set_led(6, LED_1);
+	    set_led(7, LED_1);
+
+	    i2155x_write_scrapad(BOOT_CMD, ~cmd);
+	    show_startup_phase(14);
+	    break;
+	}
+
+	/* Abort if ctrl-c was pressed */
+	if (ctrlc()) {
+	    printf("\nAbort\n");
+	    return 0;
+	}
+
+    }
+
+    /* Repoint to the default shared memory */
+    i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
+
+    load_addr = addr;
+    printf ("## Start Addr      = 0x%08lx\n", addr);
+
+    show_startup_phase(15);
+
+    /* Loading ok, check if we should attempt an auto-start */
+    if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
+	char *local_args[2];
+	local_args[0] = argv[0];
+	local_args[1] = NULL;
+
+	printf ("Automatic boot of image at addr 0x%08lX ...\n",
+		load_addr);
+	rcode = do_bootm (cmdtp, 0, 1, local_args);
+    }
+
+#ifdef CONFIG_AUTOSCRIPT
+    if (load_addr) {
+	char *s;
+
+	if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) {
+	    printf("Running autoscript at addr 0x%08lX ...\n", load_addr);
+	    rcode = autoscript (bd, load_addr);
+	}
+    }
+#endif
+    return rcode;
+}
+
+U_BOOT_CMD(
+	loadpci,	2,	1,	do_loadpci,
+	"loadpci - load binary file over PCI\n",
+	"[addr]\n"
+	"    - load binary file over PCI to address 'addr'\n"
+);
+
+#endif
diff --git a/board/pn62/config.mk b/board/pn62/config.mk
new file mode 100755
index 0000000..a2b6f05
--- /dev/null
+++ b/board/pn62/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# PN62 boards
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/pn62/misc.c b/board/pn62/misc.c
new file mode 100755
index 0000000..dcb2db5
--- /dev/null
+++ b/board/pn62/misc.c
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include "pn62.h"
+
+typedef struct {
+    pci_dev_t    devno;
+    volatile u32 *csr;
+
+} i2155x_t;
+
+static i2155x_t i2155x = { 0, NULL };
+
+static struct pci_device_id i2155x_ids[] = {
+    { 0x1011, 0x0046 },		/* i21554 */
+    { 0x8086, 0xb555 }		/* i21555 */
+};
+
+int i2155x_init(void)
+{
+    pci_dev_t devno;
+    u32 val;
+    int i;
+
+    /*
+     * Find the Intel bridge.
+     */
+    if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) {
+	printf("Error: Intel bridge 2155x not found!\n");
+	return -1;
+    }
+    i2155x.devno = devno;
+
+    /*
+     * Get auto-configured base address for CSR access.
+     */
+    pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val);
+    if (val & PCI_BASE_ADDRESS_SPACE_IO) {
+	val &= PCI_BASE_ADDRESS_IO_MASK;
+	i2155x.csr = (volatile u32 *)(_IO_BASE + val);
+    } else {
+	val &= PCI_BASE_ADDRESS_MEM_MASK;
+	i2155x.csr =  (volatile u32 *)val;
+    }
+
+    /*
+     * Translate downstream memory 2 (bar3) to base of shared memory.
+     */
+    i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
+
+    /*
+     * Enable memory space, I/O space and bus master bits
+     * in both Primary and Secondary command registers.
+     */
+    val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO;
+    pci_write_config_word(devno, 0x44, val);
+    pci_write_config_word(devno, 0x04, val);
+
+    /*
+     * Clear scratchpad registers.
+     */
+    for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) {
+	i2155x_write_scrapad(i, 0x0);
+    }
+
+    /*
+     * Set interrupt line for Linux.
+     */
+    pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3);
+
+    return 0;
+}
+
+/*
+ * Access the Scratchpad registers 0..7 of the Intel bridge.
+ */
+void i2155x_write_scrapad(int idx, u32 val)
+{
+    if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
+	out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val);
+    else
+	printf("i2155x_write_scrapad: invalid index\n");
+}
+
+u32 i2155x_read_scrapad(int idx)
+{
+    if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
+	return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx);
+    else
+	printf("i2155x_read_scrapad: invalid index\n");
+    return -1;
+}
+
+void i2155x_set_bar_base(int bar, u32 base)
+{
+    if (bar >= 2 && bar <= 4) {
+	pci_write_config_dword(i2155x.devno,
+			       I2155X_BAR2_BASE + (bar - 2) * 4,
+			       base);
+    }
+}
+
+/*
+ * Read Vital Product Data (VPD) from the Serial EPROM attached
+ * to the Intel bridge.
+ */
+int i2155x_read_vpd(int offset, int size, unsigned char *data)
+{
+    int i, n;
+    u16 val16;
+
+    for (i = 0; i < size; i++) {
+	pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR,
+			      offset + i - I2155X_VPD_START);
+	for (n = 10000; n > 0; n--) {
+	    pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16);
+	    if ((val16 & 0x8000) != 0) /* wait for completion */
+		break;
+	    udelay(100);
+	}
+	if (n == 0) {
+	    printf("i2155x_read_vpd: TIMEOUT\n");
+	    return -1;
+	}
+
+	pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]);
+    }
+
+    return i;
+}
+
+static struct pci_device_id am79c95x_ids [] = {
+	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
+	{ }
+};
+
+
+/*
+ * Initialize the AMD ethernet controllers.
+ */
+int am79c95x_init(void)
+{
+    pci_dev_t devno;
+    int i;
+
+    /*
+     * Set interrupt line for Linux.
+     */
+    for (i = 0; i < 2; i++) {
+	if ((devno = pci_find_devices(am79c95x_ids, i)) < 0)
+	    break;
+	pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i);
+    }
+    if (i < 2)
+	printf("Error: Only %d AMD Ethernet Controller found!\n", i);
+
+    return 0;
+}
+
+
+void set_led(unsigned int number, unsigned int function)
+{
+    volatile u8 *addr;
+
+    if ((number >= 0) && (number < PN62_LED_MAX) &&
+	(function >= 0) && (function <= LED_LAST_FUNCTION)) {
+	addr = (volatile u8 *)(PN62_LED_BASE + number * 8);
+	out_8(addr, function&0xff);
+    }
+}
+
+/*
+ * Show fatal error indicated by Kinght Rider(tm) effect
+ * in LEDS 0-7. LEDS 8-11 contain 4 bit error code.
+ * Note: this function will not terminate.
+ */
+void fatal_error(unsigned int error_code)
+{
+    int i, d;
+
+    for (i = 0; i < 12; i++) {
+	set_led(i, LED_0);
+    }
+
+    /*
+     * Write error code.
+     */
+    set_led(8,  (error_code & 0x01) ? LED_1 : LED_0);
+    set_led(9,  (error_code & 0x02) ? LED_1 : LED_0);
+    set_led(10, (error_code & 0x04) ? LED_1 : LED_0);
+    set_led(11, (error_code & 0x08) ? LED_1 : LED_0);
+
+    /*
+     * Yay - Knight Rider effect!
+     */
+    while(1) {
+	unsigned int delay = 2000;
+
+	for (i = 0; i < 8; i++) {
+	    set_led(i, LED_1);
+	    for (d = 0; d < delay; d++);
+	    set_led(i, LED_0);
+	}
+
+	for (i = 7; i > 0; i--) {
+	    set_led(i, LED_1);
+	    for (d = 0; d < delay; d++);
+	    set_led(i, LED_0);
+	}
+    }
+}
diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c
new file mode 100755
index 0000000..377aaa8
--- /dev/null
+++ b/board/pn62/pn62.c
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+#include "pn62.h"
+
+
+static int get_serial_number (char *string, int size);
+static int get_mac_address (int id, u8 * mac, char *string, int size);
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress (int phase)
+{
+	/*
+	 * Show phases of the bootm command on the front panel
+	 * LEDs and the scratchpad register #3 as well. We use
+	 * blinking LEDs for logical "1".
+	 */
+	if (phase > 0) {
+		set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0);
+		set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0);
+		set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0);
+		set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0);
+	}
+	i2155x_write_scrapad (BOOT_STATUS, phase);
+	if (phase < 0)
+		i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
+}
+#endif
+
+void show_startup_phase (int phase)
+{
+	/*
+	 * Show the phase of U-Boot startup on the front panel
+	 * LEDs and the scratchpad register #3 as well.
+	 */
+	if (phase > 0) {
+		set_led (8, (phase & 0x1) ? LED_1 : LED_0);
+		set_led (9, (phase & 0x2) ? LED_1 : LED_0);
+		set_led (10, (phase & 0x4) ? LED_1 : LED_0);
+		set_led (11, (phase & 0x8) ? LED_1 : LED_0);
+	}
+	i2155x_write_scrapad (BOOT_STATUS, phase);
+	if (phase < 0)
+		i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
+}
+
+int checkboard (void)
+{
+	show_startup_phase (1);
+	puts ("Board: PN62\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	show_startup_phase (2);
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg (MEAR1);
+	emear1 = mpc824x_mpc107_getreg (EMEAR1);
+	mear1 = (mear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg (MEAR1, mear1);
+	mpc824x_mpc107_setreg (EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices. We rely on auto-configuration.
+ */
+#ifndef CONFIG_PCI_PNP
+#error "CONFIG_PCI_PNP is not defined, please correct!"
+#endif
+
+struct pci_controller hose = {
+};
+
+void pci_init_board (void)
+{
+	show_startup_phase (4);
+	pci_mpc824x_init (&hose);
+
+	show_startup_phase (5);
+	i2155x_init ();
+	show_startup_phase (6);
+	am79c95x_init ();
+	show_startup_phase (7);
+}
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char str[20];
+	u8 mac[6];
+
+	show_startup_phase (8);
+	/*
+	 * Get serial number and ethernet addresses if not already defined
+	 * and update the board info structure and the environment.
+	 */
+	if (getenv ("serial#") == NULL &&
+		get_serial_number (str, strlen (str)) > 0) {
+		setenv ("serial#", str);
+	}
+	show_startup_phase (9);
+
+	if (getenv ("ethaddr") == NULL &&
+		get_mac_address (0, mac, str, sizeof (str)) > 0) {
+		setenv ("ethaddr", str);
+		memcpy (gd->bd->bi_enetaddr, mac, 6);
+	}
+	show_startup_phase (10);
+
+#ifdef CONFIG_HAS_ETH1
+	if (getenv ("eth1addr") == NULL &&
+		get_mac_address (1, mac, str, sizeof (str)) > 0) {
+		setenv ("eth1addr", str);
+		memcpy (gd->bd->bi_enet1addr, mac, 6);
+	}
+#endif /* CONFIG_HAS_ETH1 */
+	show_startup_phase (11);
+
+	/* Tell everybody that U-Boot is up and runnig */
+	i2155x_write_scrapad (0, 0x12345678);
+	return (0);
+}
+
+static int get_serial_number (char *string, int size)
+{
+	int i;
+	char c;
+
+	if (size < I2155X_VPD_SN_SIZE)
+		size = I2155X_VPD_SN_SIZE;
+	for (i = 0; i < (size - 1); i++) {
+		i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c);
+		if (c == '\0')
+			break;
+		string[i] = c;
+	}
+	string[i] = '\0';			/* make sure it's terminated */
+
+	return i;
+}
+
+static int get_mac_address (int id, u8 * mac, char *string, int size)
+{
+	if (size < 6 * 3)
+		return -1;
+
+	i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac);
+	return sprintf (string, "%02x:%02x:%02x:%02x:%02x:%02x",
+				mac[0], mac[1], mac[2],
+				mac[3], mac[4], mac[5]);
+}
diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h
new file mode 100755
index 0000000..7bda0ad
--- /dev/null
+++ b/board/pn62/pn62.h
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PN62_H_
+#define _PN62_H_
+
+/*
+ * Definitions for the Intel Bridge 21554 or 21555.
+ */
+#define I2155X_VPD_ADDR 	0xe6
+#define I2155X_VPD_DATA 	0xe8
+
+#define I2155X_VPD_START	0x80
+#define I2155X_VPD_SN_START	0x80
+#define I2155X_VPD_SN_SIZE	0x10
+#define I2155X_VPD_MAC0_START	0x90
+#define I2155X_VPD_MAC1_START	0x96
+
+#define I2155X_SCRAPAD_ADDR	0xa8
+#define I2155X_SCRAPAD_MAX	8
+
+#define I2155X_BAR2_BASE	0x98
+#define I2155X_BAR3_BASE	0x9c
+#define I2155X_BAR4_BASE	0xa0
+
+#define I2155X_BAR2_SETUP	0xb0
+#define I2155X_BAR3_SETUP	0xb4
+#define I2155X_BAR4_SETUP	0xb8
+
+/*
+ * Interrupt request numbers
+ */
+#define PN62_IRQ_HOST		0x0
+#define PN62_IRQ_PLX9054	0x1
+#define PN62_IRQ_ETH0		0x2
+#define PN62_IRQ_ETH1		0x3
+#define PN62_IRQ_COM1		0x4
+#define PN62_IRQ_COM2		0x4
+
+/*
+ * Miscellaneous definitons.
+ */
+#define PN62_SMEM_DEFAULT	0x1f00000
+
+/*
+ * Definitions for boot protocol using Scratchpad registers.
+ */
+#define BOOT_DONE		0
+#define BOOT_DONE_CLEAR  	  0x00dead00
+#define BOOT_DONE_ERROR  	  0xbad0dead
+#define BOOT_DONE_U_BOOT 	  0x12345678
+#define BOOT_DONE_LINUX   	  0x87654321
+#define BOOT_CMD 		1
+#define BOOT_CMD_MOVE   	  0x1
+#define BOOT_CMD_BOOT		  0x2
+#define BOOT_DATA		2
+#define BOOT_PROTO		3
+#define BOOT_PROTO_READY	  0x23456789
+#define BOOT_PROTO_CLEAR	  0x00000000
+#define BOOT_STATUS		4
+
+/*
+ * LED Definitions:
+ */
+#define PN62_LED_BASE		0xff800300
+#define PN62_LED_MAX		12
+
+/*
+ * LED0 - 7 mounted on top of board, D1 - D8
+ * LED8 - 11 upper four LEDs on the front panel of the board.
+ */
+#define LED_0			0x00	/* OFF */
+#define LED_1			0x01	/* ON */
+#define LED_SLOW_CLOCK		0x02	/* SLOW 1Hz ish */
+#define LED_nSLOW_CLOCK		0x03	/* inverse of above */
+#define LED_WATCHDOG_OUT	0x06	/* Reset Watchdog level */
+#define LED_WATCHDOG_CLOCK	0x07	/* clock to watchdog */
+
+/*
+ * LED's currently setup in AMD79C973 device as the following:
+ * LED0 100Mbit
+ * LED1 LNKSE
+ * LED2 TX Activity
+ * LED3 RX Activity
+ */
+#define LED_E0_LED0		0x08	/* Ethernet Port 0 LED 0 */
+#define LED_E0_LED1		0x09	/* Ethernet Port 0 LED 1 */
+#define LED_E0_LED2		0x0A	/* Ethernet Port 0 LED 2 */
+#define LED_E0_LED3		0x0B	/* Ethernet Port 0 LED 3 */
+#define LED_E1_LED0		0x0C	/* Ethernet Port 1 LED 0 */
+#define LED_E1_LED1		0x0D	/* Ethernet Port 1 LED 1 */
+#define LED_E1_LED2		0x0E	/* Ethernet Port 1 LED 2 */
+#define LED_E1_LED3		0x0F	/* Ethernet Port 1 LED 3 */
+#define LED_STROBE0		0x10	/* Processor Strobe 0 */
+#define LED_STROBE1		0x11	/* Processor Strobe 1 */
+#define LED_STROBE2		0x12	/* Processor Strobe 2 */
+#define LED_STROBE3		0x13	/* Processor Strobe 3 */
+#define LED_STROBE4		0x14	/* Processor Strobe 4 */
+#define LED_STROBE5		0x15	/* Processor Strobe 5 */
+#define LED_STROBE6		0x16	/* Processor Strobe 6 */
+#define LED_STROBE7		0x17	/* Processor Strobe 7 */
+#define LED_HOST_STROBE0	0x18	/* Host strobe 0 */
+#define LED_HOST_STROBE1	0x19	/* Host strobe 1 */
+#define LED_HOST_STROBE2	0x1A	/* Host strobe 2 */
+#define LED_HOST_STROBE3	0x1B	/* Host strobe 3 */
+#define LED_HOST_STROBE4	0x1C	/* Host strobe 4 */
+#define LED_HOST_STROBE5	0x1D	/* Host strobe 5 */
+#define LED_HOST_STROBE6	0x1E	/* Host strobe 6 */
+#define LED_HOST_STROBE7	0x1F	/* Host strobe 7 */
+#define LED_MPC_INT0		0x20	/* MPC8240 INT 0 */
+#define LED_MPC_INT1		0x21	/* MPC8240 INT 1 */
+#define	LED_MPC_INT2		0x22	/* MPC8240 INT 2 */
+#define	LED_MPC_INT3		0x23	/* MPC8240 INT 3 */
+#define	LED_MPC_INT4		0x24	/* MPC8240 INT 4 */
+#define	LED_UART0_CS		0x25	/* UART 0 Chip Select */
+#define	LED_UART1_CS		0x26	/* UART 1 Chip Select */
+#define	LED_SRAM_CS		0x27	/* SRAM Chip Select */
+#define	LED_SRAM_WR		0x28	/* SRAM WR Signal */
+#define	LED_SRAM_RD		0x29	/* SRAM RD Signal */
+#define	LED_MPC_RCS0		0x2A	/* MPC8240 RCS0 Signal */
+#define	LED_S_PCI_FRAME		0x2B	/* Secondary PCI Frame Signal */
+#define	LED_MPC_CS0		0x2C	/* MPC8240 CS0 Signal */
+#define	LED_HOST_INT		0x2D	/* MPC8240 to Host Interrupt signal */
+#define LED_LAST_FUNCTION	LED_HOST_INT	/* last function */
+
+/*
+ * Forward declarations
+ */
+int  i2155x_init         (void);
+void i2155x_write_scrapad(int idx, u32 val);
+u32  i2155x_read_scrapad (int idx);
+void i2155x_set_bar_base (int bar, u32 addr);
+int  i2155x_read_vpd     (int offset, int size, unsigned char *data);
+
+int  am79c95x_init	 (void);
+
+void set_led             (unsigned int number, unsigned int function);
+void fatal_error	 (unsigned int error_code);
+void show_startup_phase  (int phase);
+
+
+#endif /* _PN62_H_ */
diff --git a/board/pn62/u-boot.lds b/board/pn62/u-boot.lds
new file mode 100755
index 0000000..eaee3fd
--- /dev/null
+++ b/board/pn62/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile
new file mode 100755
index 0000000..351f4ee
--- /dev/null
+++ b/board/ppmc8260/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ppmc8260.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ppmc8260/config.mk b/board/ppmc8260/config.mk
new file mode 100755
index 0000000..d06fcea
--- /dev/null
+++ b/board/ppmc8260/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MBX8xx boards
+#
+
+TEXT_BASE = 0xfe000000
+TEXT_END  = 0xfe080000
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c
new file mode 100755
index 0000000..2b20c26
--- /dev/null
+++ b/board/ppmc8260/ppmc8260.c
@@ -0,0 +1,307 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTCA   */
+	/* PA29 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTSOC  */
+	/* PA28 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   1,   0,   0,   1,   0,   0   }, /* TDM_A1:L1TSYNC */
+	/* PA6  */ {   1,   0,   0,   1,   0,   0   }, /* TDN_A1:L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   0,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   0,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   0,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   0,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_A1:L1CLK0 */
+	/* PB15 */ {   1,   0,   0,   1,   0,   1   }, /* /FETHRST */
+	/* PB14 */ {   1,   0,   0,   1,   0,   0   }, /* FETHDIS */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_B1:L1CLK0 */
+	/* PB11 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1TXD */
+	/* PB10 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1RXD */
+	/* PB9  */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1TSYNC */
+	/* PB8  */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1RSYNC */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   0,   0,   0,   0,   0   }, /* PC28 */
+	/* PC28 */ {   1,   1,   0,   0,   0,   0   }, /* CLK4 */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   1,   1,   0,   0,   0,   0   }, /* CLK7 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   1,   0,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* PC22 */
+	/* PC21 */ {   0,   0,   0,   0,   0,   0   }, /* PC23 */
+	/* PC20 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:TxAddr[0] */
+	/* PC14 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[0] */
+	/* PC13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:TxAddr[1] */
+	/* PC12 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[1] */
+	/* PC11 */ {   1,   1,   0,   1,   0,   0   }, /* TDM_D1:L1CLK0 */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:TxAddr[2]*/
+	/* PC6  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[2] */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA2:DACK */
+	/* PC2  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA2:DONE */
+	/* PC1  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA2:DREQ */
+	/* PC0  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA1:DREQ */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   0,   0,   0,   0,   0   }, /* PD31 */
+	/* PD30 */ {   0,   0,   0,   0,   0,   0   }, /* PD30 */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[3] */
+	/* PD28 */ {   0,   0,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* PD27 */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_C1:L1RSYNC */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1TXD */
+	/* PD12 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1RXD */
+	/* PD11 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1TSYNC */
+	/* PD10 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1RSYNC*/
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1:TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1:RXD */
+	/* PD7  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1:SMSYN */
+	/* PD6  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA1:DACK */
+	/* PD5  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA1:DONE */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: Wind River PPMC8260\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0xff;
+	volatile uchar *ramaddr0 = (uchar *) (CFG_SDRAM0_BASE);
+	volatile uchar *ramaddr1 = (uchar *) (CFG_SDRAM1_BASE);
+	ulong psdmr = CFG_PSDMR;
+	volatile uchar *ramaddr2 = (uchar *) (CFG_SDRAM2_BASE);
+	ulong lsdmr = CFG_LSDMR;
+	int i;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr0++ = c;
+	*ramaddr1++ = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++) {
+		*ramaddr0++ = c;
+		*ramaddr1++ = c;
+	}
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	ramaddr0 = (uchar *) (CFG_SDRAM0_BASE + 0x110);
+	ramaddr1 = (uchar *) (CFG_SDRAM1_BASE + 0x110);
+	*ramaddr0 = c;
+	*ramaddr1 = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr0 = c;
+	*ramaddr1 = c;
+
+	memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
+	*ramaddr2++ = c;
+
+	memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++) {
+		*ramaddr2++ = c;
+	}
+
+	memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
+	*ramaddr2++ = c;
+
+	memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr2 = c;
+#endif
+
+	/* return total ram size */
+	return ((CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE) * 1024 * 1024);
+}
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r (void)
+{
+#ifdef CFG_LED_BASE
+	uchar ds = *(unsigned char *) (CFG_LED_BASE + 1);
+	uchar ss;
+	uchar tmp[64];
+	int res;
+
+	if ((ds != 0) && (ds != 0xff)) {
+		res = getenv_r ("ethaddr", (char *)tmp, sizeof (tmp));
+		if (res > 0) {
+			ss = ((ds >> 4) & 0x0f);
+			ss += ss < 0x0a ? '0' : ('a' - 10);
+			tmp[15] = ss;
+
+			ss = (ds & 0x0f);
+			ss += ss < 0x0a ? '0' : ('a' - 10);
+			tmp[16] = ss;
+
+			tmp[17] = '\0';
+			setenv ("ethaddr", (char *)tmp);
+			/* set the led to show the address */
+			*((unsigned char *) (CFG_LED_BASE + 1)) = ds;
+		}
+	}
+#endif /* CFG_LED_BASE */
+	return (0);
+}
+#endif /* CONFIG_MISC_INIT_R */
diff --git a/board/ppmc8260/strataflash.c b/board/ppmc8260/strataflash.c
new file mode 100755
index 0000000..f9abfac
--- /dev/null
+++ b/board/ppmc8260/strataflash.c
@@ -0,0 +1,752 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+
+#define FLASH_MAN_CFI			0x01000000
+
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n");
+		printf (" %08lX%5s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : " "
+			);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+		        retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/ppmc8260/u-boot.lds b/board/ppmc8260/u-boot.lds
new file mode 100755
index 0000000..84d4b78
--- /dev/null
+++ b/board/ppmc8260/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile
new file mode 100755
index 0000000..47116d3
--- /dev/null
+++ b/board/prodrive/p3p440/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk
new file mode 100755
index 0000000..e5722dd
--- /dev/null
+++ b/board/prodrive/p3p440/config.mk
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFFC0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S
new file mode 100755
index 0000000..ee6b706
--- /dev/null
+++ b/board/prodrive/p3p440/init.S
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+    tlbtab_end
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
new file mode 100755
index 0000000..d42a643
--- /dev/null
+++ b/board/prodrive/p3p440/p3p440.c
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+
+#include "p3p440.h"
+
+void set_led(int color)
+{
+	switch (color) {
+	case LED_OFF:
+		out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
+		break;
+
+	case LED_GREEN:
+		out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
+		break;
+
+	case LED_RED:
+		out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
+		break;
+
+	case LED_ORANGE:
+		out32(GPIO0_OR,  in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
+		break;
+	}
+}
+
+static int is_monarch(void)
+{
+	out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_GPIO_RDY);
+	udelay(1000);
+
+	if (in32(GPIO0_IR) & CFG_MONARCH_IO)
+		return 0;
+	else
+		return 1;
+}
+
+static void wait_for_pci_ready(void)
+{
+	/*
+	 * Configure EREADY_IO as input
+	 */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
+	udelay(1000);
+
+	for (;;) {
+		if (in32(GPIO0_IR) & CFG_EREADY_IO)
+			return;
+	}
+
+}
+
+int board_early_init_f(void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(ebccfga, xbcfg);
+	reg = mfdcr(ebccfgd);
+	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
+
+	/*--------------------------------------------------------------------
+	 * Setup pin multiplexing (GPIO/IRQ...)
+	 *-------------------------------------------------------------------*/
+	mtdcr(cpc0_gpio, 0x03F01F80);
+
+	out32(GPIO0_ODR, 0x00000000);	/* no open drain pins      */
+	out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
+	out32(GPIO0_OR,  CFG_GPIO_RDY);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000001);	/* UIC1 crit is critical */
+	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: P3P440");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	if (is_monarch()) {
+		puts(", Monarch");
+	} else {
+		puts(", None-Monarch");
+	}
+
+	putc('\n');
+
+	return (0);
+}
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*
+	 * Adjust flash start and offset to detected values
+	 */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Check if only one FLASH bank is available
+	 */
+	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
+		mtebc(pb1cr, 0);			/* disable cs */
+		mtebc(pb1ap, 0);
+		mtebc(pb2cr, 0);			/* disable cs */
+		mtebc(pb2ap, 0);
+		mtebc(pb3cr, 0);			/* disable cs */
+		mtebc(pb3ap, 0);
+	}
+
+	return 0;
+}
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 *	The P3P440 board is always configured as the host & requires the
+	 *	PCI arbiter to be disabled because it's an PMC module.
+	 *--------------------------------------------------------------------------*/
+	strap = mfdcr(cpc0_strp1);
+	if (strap & 0x00100000) {
+		printf("PCI: CPC0_STRP1[PAE] set.\n");
+		return 0;
+	}
+
+	return 1;
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r(PCIX0_PIM0SA, 0);	/* disable */
+	out32r(PCIX0_PIM1SA, 0);	/* disable */
+	out32r(PCIX0_PIM2SA, 0);	/* disable */
+	out32r(PCIX0_EROMBA, 0);	/* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+	out32r(PCIX0_PIM0LAH, 0);
+	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
+
+	out32r(PCIX0_BAR0, 0);
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
+	out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+
+	out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	if (is_monarch()) {
+		wait_for_pci_ready();
+		return 1;		/* return 1 for host controller */
+	} else {
+		return 0;		/* return 0 for adapter controller */
+	}
+}
+#endif				/* defined(CONFIG_PCI) */
diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h
new file mode 100755
index 0000000..e4e87d1
--- /dev/null
+++ b/board/prodrive/p3p440/p3p440.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __P3P440_H__
+#define __P3P440_H__
+
+#define CFG_GPIO_RDY	(0x80000000 >> 11)
+#define CFG_MONARCH_IO	(0x80000000 >> 18)
+#define CFG_EREADY_IO	(0x80000000 >> 20)
+#define CFG_LED_GREEN	(0x80000000 >> 21)
+#define CFG_LED_RED	(0x80000000 >> 22)
+
+#define LED_OFF		1
+#define LED_GREEN	2
+#define LED_RED		3
+#define LED_ORANGE	4
+
+long int fixed_sdram(void);
+
+#endif /* __P3P440_H__ */
diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds
new file mode 100755
index 0000000..92bb740
--- /dev/null
+++ b/board/prodrive/p3p440/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/prodrive/p3p440/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c
new file mode 100755
index 0000000..4965743
--- /dev/null
+++ b/board/psyent/common/AMDLV065D.c
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#if defined(CONFIG_NIOS)
+#include <nios.h>
+#else
+#include <nios2.h>
+#endif
+
+#define SECTSZ		(64 * 1024)
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*----------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = CFG_FLASH_SIZE;
+	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
+
+	addr = CFG_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+		fli->protect[i] = 1;
+	}
+
+	return (CFG_FLASH_SIZE);
+}
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	unsigned long size;
+	int erased;
+	volatile unsigned char *flash;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]);
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			CACHE_NO_BYPASS(info->start[i]),
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)
+		CACHE_BYPASS(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int prot, sect;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *)
+				CACHE_BYPASS((info->start[sect]));
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr = 0x80;
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr2 = 0x30;
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait.
+			 */
+			start = get_timer (0);
+			while (*addr2 != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+		}
+	}
+	printf ("\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+
+	vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]);
+	vu_char *dst = (vu_char *) CACHE_BYPASS(addr);
+	unsigned char b;
+	ulong start;
+
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((*dst & b) != b) {
+			printf ("%02x : %02x\n", *dst, b);
+			return (2);
+		}
+
+		*cmd = 0xaa;
+		*cmd = 0x55;
+		*cmd = 0xa0;
+		*dst = b;
+
+		/* Verify write */
+		start = get_timer (0);
+		while (*dst != b) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+	}
+
+	return (0);
+}
diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile
new file mode 100755
index 0000000..8e55c9b
--- /dev/null
+++ b/board/psyent/pci5441/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COMOBJS := ../common/AMDLV065D.o
+
+OBJS	:= $(BOARD).o $(COMOBJS)
+
+SOBJS	=
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk
new file mode 100755
index 0000000..d72bcee
--- /dev/null
+++ b/board/psyent/pci5441/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x018e0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/psyent/pci5441/pci5441.c b/board/psyent/pci5441/pci5441.c
new file mode 100755
index 0000000..ea80dd1
--- /dev/null
+++ b/board/psyent/pci5441/pci5441.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("BOARD : Psyent PCI-5441\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}
diff --git a/board/psyent/pci5441/u-boot.lds b/board/psyent/pci5441/u-boot.lds
new file mode 100755
index 0000000..8f9cd8f
--- /dev/null
+++ b/board/psyent/pci5441/u-boot.lds
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(.rodata)
+	  *(.rodata.*)
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile
new file mode 100755
index 0000000..5c1db03
--- /dev/null
+++ b/board/psyent/pk1c20/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COMOBJS := ../common/AMDLV065D.o
+
+OBJS	:= $(BOARD).o led.o $(COMOBJS)
+
+SOBJS	=
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk
new file mode 100755
index 0000000..d72bcee
--- /dev/null
+++ b/board/psyent/pk1c20/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x018e0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c
new file mode 100755
index 0000000..c175c9b
--- /dev/null
+++ b/board/psyent/pk1c20/led.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nios2.h>
+#include <nios2-io.h>
+#include <status_led.h>
+
+/* The LED port is configured as output only, so we
+ * must track the state manually.
+ */
+static led_id_t val = 0;
+
+void __led_init (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	pio->data = val;
+}
+
+void __led_set (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	pio->data = val;
+}
+
+void __led_toggle (led_id_t mask)
+{
+	nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+
+	val ^= mask;
+	pio->data = val;
+}
diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c
new file mode 100755
index 0000000..1924ae3
--- /dev/null
+++ b/board/psyent/pk1c20/pk1c20.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("BOARD : Psyent PK-1C20\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}
diff --git a/board/psyent/pk1c20/u-boot.lds b/board/psyent/pk1c20/u-boot.lds
new file mode 100755
index 0000000..8f9cd8f
--- /dev/null
+++ b/board/psyent/pk1c20/u-boot.lds
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(.rodata)
+	  *(.rodata.*)
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}
diff --git a/board/purple/Makefile b/board/purple/Makefile
new file mode 100755
index 0000000..b2f2fc0
--- /dev/null
+++ b/board/purple/Makefile
@@ -0,0 +1,42 @@
+
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o sconsole.o
+SOBJS	= lowlevel_init.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/purple/config.mk b/board/purple/config.mk
new file mode 100755
index 0000000..ea478ed
--- /dev/null
+++ b/board/purple/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Purple board with MIPS 5Kc CPU core
+#
+
+# ROM version
+TEXT_BASE = 0xB0000000
+
+# RAM version
+#TEXT_BASE = 0x80100000
diff --git a/board/purple/flash.c b/board/purple/flash.c
new file mode 100755
index 0000000..7522580
--- /dev/null
+++ b/board/purple/flash.c
@@ -0,0 +1,596 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/inca-ip.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFFFFFF
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+#define FLASH29_REG_ADRS(reg) ((FPWV *)PHYS_FLASH_1 + (reg))
+
+/* FLASH29 command register addresses */
+
+#define FLASH29_REG_FIRST_CYCLE		FLASH29_REG_ADRS (0x1555)
+#define FLASH29_REG_SECOND_CYCLE	FLASH29_REG_ADRS (0x2aaa)
+#define FLASH29_REG_THIRD_CYCLE		FLASH29_REG_ADRS (0x3555)
+#define	FLASH29_REG_FOURTH_CYCLE	FLASH29_REG_ADRS (0x4555)
+#define	FLASH29_REG_FIFTH_CYCLE		FLASH29_REG_ADRS (0x5aaa)
+#define	FLASH29_REG_SIXTH_CYCLE		FLASH29_REG_ADRS (0x6555)
+
+/* FLASH29 command definitions */
+
+#define	FLASH29_CMD_FIRST		0xaaaaaaaa
+#define	FLASH29_CMD_SECOND		0x55555555
+#define	FLASH29_CMD_FOURTH		0xaaaaaaaa
+#define	FLASH29_CMD_FIFTH		0x55555555
+#define	FLASH29_CMD_SIXTH		0x10101010
+
+#define	FLASH29_CMD_SECTOR		0x30303030
+#define	FLASH29_CMD_PROGRAM		0xa0a0a0a0
+#define	FLASH29_CMD_CHIP_ERASE		0x80808080
+#define	FLASH29_CMD_READ_RESET		0xf0f0f0f0
+#define	FLASH29_CMD_AUTOSELECT		0x90909090
+#define FLASH29_CMD_READ		0x70707070
+
+#define IN_RAM_CMD_READ		0x1
+#define IN_RAM_CMD_WRITE	0x2
+
+#define FLASH_WRITE_CMD	((ulong)(flash_write_cmd) & 0x7)+0xbf008000
+#define FLASH_READ_CMD  ((ulong)(flash_read_cmd) & 0x7)+0xbf008000
+
+typedef void (*FUNCPTR_CP)(ulong *source, ulong *destination, ulong nlongs);
+typedef void (*FUNCPTR_RD)(int cmd, FPWV * pFA, char * string, int strLen);
+typedef void (*FUNCPTR_WR)(int cmd, FPWV * pFA, FPW value);
+
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static int write_word(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+static flash_info_t *flash_get_info(ulong base);
+
+static void load_cmd(ulong cmd);
+static ulong in_ram_cmd = 0;
+
+
+/******************************************************************************
+*
+* Don't change the program architecture
+* This architecture assure the program
+* can be relocated to scratch ram
+*/
+static void flash_read_cmd(int cmd, FPWV * pFA, char * string, int strLen)
+{
+	int i,j;
+	FPW temp,temp1;
+	FPWV *str;
+
+	str = (FPWV *)string;
+
+	j=  strLen/4;
+
+	if(cmd == FLASH29_CMD_AUTOSELECT)
+	   {
+	    *(FLASH29_REG_FIRST_CYCLE)  = FLASH29_CMD_FIRST;
+	    *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_AUTOSELECT;
+	   }
+
+	if(cmd == FLASH29_CMD_READ)
+	   {
+	    i = 0;
+	    while(i<j)
+	    {
+		temp = *pFA++;
+		temp1 = *(int *)0xa0000000;
+		*(int *)0xbf0081f8 = temp1 + temp;
+		*str++ = temp;
+		i++;
+	    }
+	   }
+
+	 if(cmd == FLASH29_CMD_READ_RESET)
+	 {
+	    *(FLASH29_REG_FIRST_CYCLE)  = FLASH29_CMD_FIRST;
+	    *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_READ_RESET;
+	 }
+
+	*(int *)0xbf0081f8 = *(int *)0xa0000000;	/* dummy read switch back to sdram interface */
+}
+
+/******************************************************************************
+*
+* Don't change the program architecture
+* This architecture assure the program
+* can be relocated to scratch ram
+*/
+static void flash_write_cmd(int cmd, FPWV * pFA, FPW value)
+{
+	*(FLASH29_REG_FIRST_CYCLE)  = FLASH29_CMD_FIRST;
+	*(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
+
+	if (cmd == FLASH29_CMD_SECTOR)
+	   {
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_CHIP_ERASE;
+	    *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
+	    *(FLASH29_REG_FIFTH_CYCLE)  = FLASH29_CMD_FIFTH;
+	    *pFA		        = FLASH29_CMD_SECTOR;
+	   }
+
+	if (cmd == FLASH29_CMD_SIXTH)
+	   {
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_CHIP_ERASE;
+	    *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
+	    *(FLASH29_REG_FIFTH_CYCLE)  = FLASH29_CMD_FIFTH;
+	    *(FLASH29_REG_SIXTH_CYCLE)  = FLASH29_CMD_SIXTH;
+	   }
+
+	if (cmd == FLASH29_CMD_PROGRAM)
+	   {
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_PROGRAM;
+	    *pFA = value;
+	   }
+
+	if (cmd == FLASH29_CMD_READ_RESET)
+	   {
+	    *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_READ_RESET;
+	   }
+
+	*(int *)0xbf0081f8 = *(int *)0xa0000000;	/* dummy read switch back to sdram interface */
+}
+
+static void load_cmd(ulong cmd)
+{
+	ulong *src;
+	ulong *dst;
+	FUNCPTR_CP absEntry;
+	ulong func;
+
+	if (in_ram_cmd & cmd) return;
+
+	if (cmd == IN_RAM_CMD_READ)
+	{
+		func = (ulong)flash_read_cmd;
+	}
+	else
+	{
+		func = (ulong)flash_write_cmd;
+	}
+
+	src = (ulong *)(func & 0xfffffff8);
+	dst = (ulong *)0xbf008000;
+	absEntry = (FUNCPTR_CP)(0xbf0081d0);
+	absEntry(src,dst,0x38);
+
+	in_ram_cmd = cmd;
+}
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	load_cmd(IN_RAM_CMD_READ);
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		ulong flashbase = PHYS_FLASH_1;
+		ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0;
+
+		/* Disable write protection */
+		*buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
+
+#if 1
+		memset(&flash_info[i], 0, sizeof(flash_info_t));
+#endif
+
+		flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
+			i, flash_info[i].size);
+		}
+
+		size += flash_info[i].size;
+	}
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM160B) {
+
+		int bootsect_size[4];	/* number of bytes/boot sector  */
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size[0] = 0x00008000;
+		bootsect_size[1] = 0x00004000;
+		bootsect_size[2] = 0x00004000;
+		bootsect_size[3] = 0x00010000;
+		sect_size =        0x00020000;
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			base += i < 4 ? bootsect_size[i] : sect_size;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->start[0] <= base && base < info->start[0] + info->size)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	uchar *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160B:
+		fmt = "29LV160B%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	FUNCPTR_RD absEntry;
+	FPW retValue;
+	int flag;
+
+	load_cmd(IN_RAM_CMD_READ);
+	absEntry = (FUNCPTR_RD)FLASH_READ_CMD;
+
+	flag = disable_interrupts();
+	absEntry(FLASH29_CMD_AUTOSELECT,0,0,0);
+	if (flag) enable_interrupts();
+
+	udelay(100);
+
+	flag = disable_interrupts();
+	absEntry(FLASH29_CMD_READ, addr + 1, (char *)&retValue, sizeof(retValue));
+	absEntry(FLASH29_CMD_READ_RESET,0,0,0);
+	if (flag) enable_interrupts();
+
+	udelay(100);
+
+	switch (retValue) {
+
+	case (FPW)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	ulong start, now, last;
+	int rcode = 0;
+	FUNCPTR_WR absEntry;
+
+	load_cmd(IN_RAM_CMD_WRITE);
+	absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM160B:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	last  = get_timer(0);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		absEntry(FLASH29_CMD_SECTOR, addr, 0);
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		start = get_timer(0);
+
+		while ((now = get_timer(start)) <= CFG_FLASH_ERASE_TOUT) {
+
+			/* show that we're waiting */
+			if ((get_timer(last)) > CFG_HZ) {/* every second */
+				putc ('.');
+				last = get_timer(0);
+			}
+		}
+
+		flag = disable_interrupts();
+		absEntry(FLASH29_CMD_READ_RESET,0,0);
+		if (flag)
+			enable_interrupts();
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+    int bytes;	  /* number of bytes to program in current word		*/
+    int left;	  /* number of bytes left to program			*/
+    int i, res;
+
+    for (left = cnt, res = 0;
+	 left > 0 && res == 0;
+	 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+	bytes = addr & (sizeof(data) - 1);
+	addr &= ~(sizeof(data) - 1);
+
+	/* combine source and destination data so can program
+	 * an entire word of 16 or 32 bits
+	 */
+	for (i = 0; i < sizeof(data); i++) {
+	    data <<= 8;
+	    if (i < bytes || i - bytes >= left )
+		data += *((uchar *)addr + i);
+	    else
+		data += *src++;
+	}
+
+	res = write_word(info, (FPWV *)addr, data);
+    }
+
+    return (res);
+}
+
+static int write_word (flash_info_t *info, FPWV *dest, FPW data)
+{
+    int res = 0;	/* result, assume success	*/
+    FUNCPTR_WR absEntry;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+    if (info->start[0] != PHYS_FLASH_1)
+    {
+	return (3);
+    }
+
+    load_cmd(IN_RAM_CMD_WRITE);
+    absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
+
+    flag = disable_interrupts();
+    absEntry(FLASH29_CMD_PROGRAM,dest,data);
+    if (flag) enable_interrupts();
+
+    udelay(100);
+
+    flag = disable_interrupts();
+    absEntry(FLASH29_CMD_READ_RESET,0,0);
+    if (flag) enable_interrupts();
+
+    return (res);
+}
diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S
new file mode 100755
index 0000000..668124a
--- /dev/null
+++ b/board/purple/lowlevel_init.S
@@ -0,0 +1,37 @@
+/*
+ *  Memory sub-system initialization code for PURPLE development board.
+ *
+ *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+#define MC_IOGP	0xBF800800
+
+	.globl	lowlevel_init
+lowlevel_init:
+	li	t0, MC_IOGP
+	li	t1, 0xf24
+	sw	t1, 0(t0)
+	j	ra
+	nop
diff --git a/board/purple/purple.c b/board/purple/purple.c
new file mode 100755
index 0000000..4c3e5b4
--- /dev/null
+++ b/board/purple/purple.c
@@ -0,0 +1,266 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/inca-ip.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#include "sconsole.h"
+
+#define cache_unroll(base,op)	        	\
+	__asm__ __volatile__("	         	\
+		.set noreorder;		        \
+		.set mips3;		        \
+		cache %1, (%0);	                \
+		.set mips0;			\
+		.set reorder"			\
+		:				\
+		: "r" (base),			\
+		  "i" (op));
+
+typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs);
+
+extern void	asc_serial_init		(void);
+extern void	asc_serial_putc 	(char);
+extern void	asc_serial_puts 	(const char *);
+extern int	asc_serial_getc 	(void);
+extern int	asc_serial_tstc 	(void);
+extern void	asc_serial_setbrg 	(void);
+
+static void sdram_timing_init (ulong size)
+{
+	register uint pass;
+	register uint done;
+	register uint count;
+	register uint p0, p1, p2, p3, p4;
+	register uint addr;
+
+#define WRITE_MC_IOGP_1 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+(p4<<8)+(p0<<4)+p3;
+#define WRITE_MC_IOGP_2 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+((p4-16)<<8)+(p0<<4)+p3;
+
+	done = 0;
+	p0 = 2;
+	while (p0 < 4 && done == 0) {
+	    p1 = 0;
+	    while (p1 < 2 && done == 0) {
+		p2 = 0;
+		while (p2 < 2 && done == 0) {
+		    p3 = 0;
+		    while (p3 < 16 && done == 0) {
+			count = 0;
+			p4 = 0;
+			while (p4 < 32 && done == 0) {
+			    WRITE_MC_IOGP_1;
+
+			    for (addr = KSEG1 + 0x4000;
+				 addr < KSEG1ADDR (size);
+				 addr = addr + 4) {
+					*(uint *) addr = 0xaa55aa55;
+			    }
+
+			    pass = 1;
+
+			    for (addr = KSEG1 + 0x4000;
+				 addr < KSEG1ADDR (size) && pass == 1;
+				 addr = addr + 4) {
+					if (*(uint *) addr != 0xaa55aa55)
+						pass = 0;
+			    }
+
+			    if (pass == 1) {
+				count++;
+			    } else {
+				count = 0;
+			    }
+
+			    if (count == 32) {
+				WRITE_MC_IOGP_2;
+				done = 1;
+			    }
+			    p4++;
+			}
+			p3++;
+		    }
+		    p2++;
+		}
+		p1++;
+	    }
+	    p0++;
+	    if (p0 == 1)
+		p0++;
+	}
+}
+
+long int initdram(int board_type)
+{
+	/* The only supported number of SDRAM banks is 4.
+	 */
+#define CFG_NB	4
+
+	ulong	cfgpb0	= *INCA_IP_SDRAM_MC_CFGPB0;
+	ulong	cfgdw	= *INCA_IP_SDRAM_MC_CFGDW;
+	int	cols	= cfgpb0 & 0xF;
+	int	rows	= (cfgpb0 & 0xF0) >> 4;
+	int	dw	= cfgdw & 0xF;
+	ulong	size	= (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
+	void (*  sdram_init) (ulong);
+
+	sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init);
+
+	sdram_init(0x10000);
+
+	return size;
+}
+
+int checkboard (void)
+{
+
+	unsigned long chipid = *(unsigned long *)0xB800C800;
+
+	printf ("Board: Purple PLB 2800 chip version %ld, ", chipid & 0xF);
+
+	printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	asc_serial_init ();
+
+	sconsole_putc   = asc_serial_putc;
+	sconsole_puts   = asc_serial_puts;
+	sconsole_getc   = asc_serial_getc;
+	sconsole_tstc   = asc_serial_tstc;
+	sconsole_setbrg = asc_serial_setbrg;
+
+	sconsole_flush ();
+	return (0);
+}
+
+/*******************************************************************************
+*
+* copydwords - copy one buffer to another a long at a time
+*
+* This routine copies the first <nlongs> longs from <source> to <destination>.
+*/
+static void copydwords (ulong *source, ulong *destination, ulong nlongs)
+{
+	ulong temp,temp1;
+	ulong *dstend = destination + nlongs;
+
+	while (destination < dstend)
+	{
+		temp = *source++;
+		/* dummy read from sdram */
+		temp1 = *(ulong *)0xa0000000;
+		/* avoid optimization from compliler */
+		*(ulong *)0xbf0081f8 = temp1 + temp;
+		*destination++ = temp;
+
+	}
+}
+
+/*******************************************************************************
+*
+* copyLongs - copy one buffer to another a long at a time
+*
+* This routine copies the first <nlongs> longs from <source> to <destination>.
+*/
+static void copyLongs (ulong *source, ulong *destination, ulong nlongs)
+{
+	FUNCPTR absEntry;
+
+	absEntry = (FUNCPTR)(0xbf008000+((ulong)copydwords & 0x7));
+	absEntry(source, destination, nlongs);
+}
+
+/*******************************************************************************
+*
+* programLoad - load program into ram
+*
+* This routine load copydwords into ram
+*
+*/
+static void programLoad(void)
+{
+	FUNCPTR absEntry;
+	ulong *src,*dst;
+
+	src = (ulong *)(TEXT_BASE + 0x428);
+	dst = (ulong *)0xbf0081d0;
+
+	absEntry = (FUNCPTR)(TEXT_BASE + 0x400);
+	absEntry(src,dst,0x6);
+
+	src = (ulong *)((ulong)copydwords & 0xfffffff8);
+	dst = (ulong *)0xbf008000;
+
+	absEntry(src,dst,0x38);
+}
+
+/*******************************************************************************
+*
+* copy_code - copy u-boot image from flash to RAM
+*
+* This routine is needed to solve flash problems on this board
+*
+*/
+void copy_code (ulong dest_addr)
+{
+	extern long uboot_end_data;
+	unsigned long start;
+	unsigned long end;
+
+	/* load copydwords into ram
+	 */
+	programLoad();
+
+	/* copy u-boot code
+	 */
+	copyLongs((ulong *)CFG_MONITOR_BASE,
+		  (ulong *)dest_addr,
+		  ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4);
+
+
+	/* flush caches
+	 */
+
+	start = KSEG0;
+	end = start + CFG_DCACHE_SIZE;
+	while(start < end) {
+		cache_unroll(start,Index_Writeback_Inv_D);
+		start += CFG_CACHELINE_SIZE;
+	}
+
+	start = KSEG0;
+	end = start + CFG_ICACHE_SIZE;
+	while(start < end) {
+		cache_unroll(start,Index_Invalidate_I);
+		start += CFG_CACHELINE_SIZE;
+	}
+}
diff --git a/board/purple/sconsole.c b/board/purple/sconsole.c
new file mode 100755
index 0000000..f52d50d
--- /dev/null
+++ b/board/purple/sconsole.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+
+#include "sconsole.h"
+
+void	(*sconsole_putc) (char) = 0;
+void	(*sconsole_puts) (const char *) = 0;
+int	(*sconsole_getc) (void) = 0;
+int	(*sconsole_tstc) (void) = 0;
+void	(*sconsole_setbrg) (void) = 0;
+
+int serial_init (void)
+{
+	sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+	sb->pos  = 0;
+	sb->size = 0;
+	sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
+
+	return (0);
+}
+
+void serial_putc (char c)
+{
+	if (sconsole_putc) {
+		(*sconsole_putc) (c);
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		if (c) {
+			sb->data[sb->pos++] = c;
+			if (sb->pos == sb->max_size) {
+				sb->pos = 0;
+			}
+			if (sb->size < sb->max_size) {
+				sb->size++;
+			}
+		}
+	}
+}
+
+void serial_puts (const char *s)
+{
+	if (sconsole_puts) {
+		(*sconsole_puts) (s);
+	} else {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+
+		while (*s) {
+			sb->data[sb->pos++] = *s++;
+			if (sb->pos == sb->max_size) {
+				sb->pos = 0;
+			}
+			if (sb->size < sb->max_size) {
+				sb->size++;
+			}
+		}
+	}
+}
+
+int serial_getc (void)
+{
+	if (sconsole_getc) {
+		return (*sconsole_getc) ();
+	} else {
+		return 0;
+	}
+}
+
+int serial_tstc (void)
+{
+	if (sconsole_tstc) {
+		return (*sconsole_tstc) ();
+	} else {
+		return 0;
+	}
+}
+
+void serial_setbrg (void)
+{
+	if (sconsole_setbrg) {
+		(*sconsole_setbrg) ();
+	}
+}
+
+void sconsole_flush (void)
+{
+	if (sconsole_putc) {
+		sconsole_buffer_t *sb = SCONSOLE_BUFFER;
+		unsigned int end = sb->pos < sb->size
+				? sb->pos + sb->max_size - sb->size
+				: sb->pos - sb->size;
+
+		while (sb->size) {
+			(*sconsole_putc) (sb->data[end++]);
+			if (end == sb->max_size) {
+				end = 0;
+			}
+			sb->size--;
+		}
+	}
+}
diff --git a/board/purple/sconsole.h b/board/purple/sconsole.h
new file mode 100755
index 0000000..d441f37
--- /dev/null
+++ b/board/purple/sconsole.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SCONSOLE_H_
+#define _SCONSOLE_H_
+
+#include <config.h>
+
+typedef struct sconsole_buffer_s
+{
+  unsigned long		size;
+  unsigned long		max_size;
+  unsigned long 	pos;
+  char			data [1];
+} sconsole_buffer_t;
+
+#define SCONSOLE_BUFFER		((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)
+
+extern void	(* sconsole_putc) 	(char);
+extern void	(* sconsole_puts) 	(const char *);
+extern int	(* sconsole_getc) 	(void);
+extern int	(* sconsole_tstc) 	(void);
+extern void	(* sconsole_setbrg) 	(void);
+
+extern void	sconsole_flush		(void);
+
+#endif
diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds
new file mode 100755
index 0000000..1bdac1f
--- /dev/null
+++ b/board/purple/u-boot.lds
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  cpu/mips/start.o		(.text)
+	  board/purple/lowlevel_init.o	(.text)
+	  cpu/mips/cache.o		(.text)
+	  common/main.o			(.text)
+	  common/dlmalloc.o		(.text)
+	  common/cmd_boot.o		(.text)
+	  lib_generic/zlib.o		(.text)
+	  . = DEFINED(env_offset) ? env_offset : .;
+	  common/environment.o	(.ppcenv)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile
new file mode 100755
index 0000000..b5f352a
--- /dev/null
+++ b/board/pxa255_idp/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= pxa_idp.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/pxa255_idp/README b/board/pxa255_idp/README
new file mode 100755
index 0000000..0cc2f2a
--- /dev/null
+++ b/board/pxa255_idp/README
@@ -0,0 +1,11 @@
+Tested:
+
+- MMC
+- Ethernet
+- BL console (on serial port connector J5)
+- flash support
+
+Todo:
+
+- display support
+- PCMCIA support
diff --git a/board/pxa255_idp/config.mk b/board/pxa255_idp/config.mk
new file mode 100755
index 0000000..d2a2040
--- /dev/null
+++ b/board/pxa255_idp/config.mk
@@ -0,0 +1,3 @@
+#TEXT_BASE = 0xa1700000
+TEXT_BASE = 0xa3000000
+#TEXT_BASE = 0
diff --git a/board/pxa255_idp/idp_notes.txt b/board/pxa255_idp/idp_notes.txt
new file mode 100755
index 0000000..4746748
--- /dev/null
+++ b/board/pxa255_idp/idp_notes.txt
@@ -0,0 +1,46 @@
+Notes on the Vibren PXA255 IDP.
+
+Chip select usage:
+
+CS0 - flash
+CS1 - alt flash (Mdoc or main flash)
+CS2 - high speed expansion bus
+CS3 - Media Q, low speed exp bus
+CS4 - low speed exp bus
+CS5 - low speed exp bus
+  - IDE: offset 0x03000000 (abs: 0x17000000)
+  - Eth: offset 0x03400000 (abs: 0x17400000)
+  - core voltage latch: offset 0x03800000 (abs: 0x17800000)
+  - CPLD: offset 0x03C00000 (abs: 0x17C00000)
+
+PCMCIA Power control
+
+MAX1602EE w/ code pulled high (Cirrus code)
+vx = 5v
+vy = 3v
+
+			Bit pattern
+			PWR 3,2,1,0
+vcc	     vpp	A1VCC  A0VCC   A1VPP   A0VPP
+=====================================================
+0	     0            0      0       0       0	0x0
+3 (vy)	     0            1      0       1       1	0xB
+3 (vy)	     3 (vy)       1      0       0       1	0x9
+3 (vy)	     12(12in)     1      0       1       0	0xA
+5 (vx)	     0            0      1       1       1	0x7
+5 (vx)	     5 (vx)       0      1       0       1	0x5
+5 (vx	     12(12in)     0      1       1       0	0x6
+
+Display power sequencing:
+
+- VDD applied
+- within 1sec, activate scanning signals
+- wait at least 50mS - scanning signals must be active before activating DISP
+
+Signal mapping:
+Schematic            LV8V31 signal name
+=========================================
+LCD_ENAVLCD		DISP
+LCD_PWR			Applies VDD to board
+
+Both of the above signals are controlled by the CPLD
diff --git a/board/pxa255_idp/memsetup.S b/board/pxa255_idp/memsetup.S
new file mode 100755
index 0000000..7e485a2
--- /dev/null
+++ b/board/pxa255_idp/memsetup.S
@@ -0,0 +1,496 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/memsetup.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+	.macro CPWAIT reg
+	mrc  p15,0,\reg,c2,c0,0
+	mov  \reg,\reg
+	sub  pc,pc,#4
+	.endm
+
+/*
+ * 	Memory setup
+ */
+.globl memsetup
+memsetup:
+
+	mov      r10, lr
+
+#ifdef DEBUG_BLINK_ENABLE
+	/* 3rd blink */
+	bl	blink
+#endif
+
+	/* Set up GPIO pins first ----------------------------------------- */
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr	r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+#ifdef DEBUG_BLINK_ENABLE
+	/* 4th debug blink */
+	bl 	blink
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr     r2,   =CFG_MSC0_VAL
+	str     r2,   [r1, #MSC0_OFFSET]
+	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */
+	/* MSC1: nCS(2,3)                                                   */
+	ldr     r2,  =CFG_MSC1_VAL
+	str     r2,  [r1, #MSC1_OFFSET]
+	ldr     r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr     r2,  =CFG_MSC2_VAL
+	str     r2,  [r1, #MSC2_OFFSET]
+	ldr     r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr     r2,  =CFG_MECR_VAL
+	str     r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr     r2,  =CFG_MCMEM0_VAL
+	str     r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr     r2,  =CFG_MCMEM1_VAL
+	str     r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr     r2,  =CFG_MCATT0_VAL
+	str     r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr     r2,  =CFG_MCATT1_VAL
+	str     r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr     r2,  =CFG_MCIO0_VAL
+	str     r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr     r2,  =CFG_MCIO1_VAL
+	str     r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+#ifdef DEBUG_BLINK_ENABLE
+	/* 5th blink */
+	bl 	blink
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DRI field.                           */
+
+	ldr     r3,     =CFG_MDREFR_VAL
+	ldr     r2,     =0xFFF
+	and     r3,     r3,  r2
+	ldr	r4,	=0x03ca4000
+	orr     r4,     r4,  r3
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+	/* Note: preserve the mdrefr value in r4                            */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	/* set MDREFR according to user define with exception of a few bits */
+
+	ldr     r4,     =CFG_MDREFR_VAL
+	orr	r4,	r4,	#(MDREFR_SLFRSH)
+	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
+
+	bic	r4,	r4,	#(MDREFR_SLFRSH)
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
+
+	ldr     r4,     =CFG_MDREFR_VAL
+	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r4,     [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+
+	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+	ldr     r4,     [r1, #MDCNFG_OFFSET]
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	    str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	    ldr r2, [r3]
+	    cmp r4, r2
+	    bgt 1b
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
+
+	ldr     r3,  [r1, #MDCNFG_OFFSET]
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	str     r3,  [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2,  =CFG_MDMRS_VAL
+	str     r2,  [r1, #MDMRS_OFFSET]
+
+	/* We are finished with Intel's memory controller initialisation    */
+#if 0
+	/* FIXME turn on serial ports */
+	/* look into moving this to board_init() */
+	ldr 	r2, =(PXA_CS5_PHYS + 0x03C0002c)
+	mov	r3, #0x13
+	str	r3, [r2]
+#endif
+
+#ifdef DEBUG_BLINK_ENABLE
+	/* 6th blink */
+	bl 	blink
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2,  =ICLR
+	str     r1,  [r2]
+
+	ldr     r2,  =ICMR	/* mask all interrupts at the controller    */
+	str     r1,  [r2]
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+	/* (hard-coding at 398.12MHz for now).                              */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+#if 0
+	ldr     r1,  =CKEN
+	mov     r2,  #0
+	str     r2,  [r1]
+
+	/* default value in case no valid rotary switch setting is found    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1,  =CCCR
+	str     r2,  [r1]
+
+#endif
+
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+
+	ldr     r1,  =OSCC
+	mov     r2,  #OSCC_OON
+	str     r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size */
+	ldr     r1, =DRAM_SIZE
+	 str	   r8, [r1]
+
+	/* Interrupt init: Mask all interrupts                              */
+	ldr	r0, =ICMR /* enable no sources */
+	mov r1, #0
+	str r1, [r0]
+
+	/* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End memsetup                                                     */
+	/* ---------------------------------------------------------------- */
+
+#ifdef DEBUG_BLINK_ENABLE
+	/* 7th blink */
+	bl 	blink
+#endif
+
+endmemsetup:
+
+	mov     pc, r10
+
+
+#ifdef DEBUG_BLINK_ENABLE
+
+/* debug LED code */
+
+/* delay about 200ms */
+delay:
+
+	/* reset OSCR to 0 */
+	ldr	r8, =OSCR
+	mov	r9, #0
+	str	r9, [r8]
+
+	/* make sure new value has stuck */
+1:
+	ldr	r8, =OSCR
+	ldr	r9, [r8]
+	mov	r8, #0x10000
+	cmp	r9, r8
+	bgt	1b
+
+	/* now, wait for delay to expire */
+1:
+	ldr	r8, =OSCR
+	ldr	r9, [r8]
+	mov	r8, #0xd4000
+	cmp	r8, r9
+	bgt	1b
+
+	mov	pc, lr
+
+/* blink code -- trashes r7, r8, r9 */
+
+.globl blink
+blink:
+
+	mov	r7, lr
+
+	/* set GPIO10 as outout */
+	ldr	r8,  =GPDR0
+	ldr	r9,  [r8]
+	orr	r9,  r9, #(1<<10)
+	str	r9,  [r8]
+
+	/* turn LED off */
+	mov	r9,  #(1<<10)
+	ldr	r8,  =GPCR0
+	str	r9, [r8]
+	bl	delay
+
+	/* turn LED on */
+	mov	r9,  #(1<<10)
+	ldr	r8,  =GPSR0
+	str	r9, [r8]
+	bl	delay
+
+	/* turn LED off */
+	mov	r9,  #(1<<10)
+	ldr	r8,  =GPCR0
+	str	r9, [r8]
+
+	mov	pc, r7
+
+#endif
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
new file mode 100755
index 0000000..d5b993a
--- /dev/null
+++ b/board/pxa255_idp/pxa_idp.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2004
+ * BEC Systems <http://bec-systems.com>
+ * Cliff Brake <cliff.brake@gmail.com>
+ * Support for Accelent/Vibren PXA255 IDP
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of Lubbock-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PXA_IDP;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	/* turn on serial ports */
+	*(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C0002c) = 0x13;
+
+	/* set PWM for LCD */
+	/* a value that works is 60Hz, 77% duty cycle */
+	CKEN |= CKEN0_PWM0;
+	PWM_CTRL0 = 0x3f;
+	PWM_PERVAL0 = 0x3ff;
+	PWM_PWDUTY0 = 792;
+
+	/* clear reset to AC97 codec */
+	CKEN |= CKEN2_AC97;
+	GCR = GCR_COLD_RST;
+
+	/* enable LCD backlight */
+	/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
+
+	/* test display */
+	/* lcd_puts("This is a test\nTest #2\n"); */
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
+
+
+#ifdef DEBUG_BLINKC_ENABLE
+
+void delay_c(void)
+{
+	/* reset OSCR to 0 */
+	OSCR = 0;
+	while(OSCR > 0x10000)
+		;
+
+	while(OSCR < 0xd4000)
+		;
+}
+
+void blink_c(void)
+{
+	int led_bit = (1<<10);
+
+	GPDR0 = led_bit;
+	GPCR0 = led_bit;
+	delay_c();
+	GPSR0 = led_bit;
+	delay_c();
+	GPCR0 = led_bit;
+}
+
+int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	printf("IDPCMD started\n");
+	return 0;
+}
+
+U_BOOT_CMD(idpcmd, CFG_MAXARGS, 0, do_idpcmd,
+	   "idpcmd    - custom IDP command\n",
+	   "no args at this time\n"
+);
+
+#endif
diff --git a/board/pxa255_idp/pxa_reg_calcs.out b/board/pxa255_idp/pxa_reg_calcs.out
new file mode 100755
index 0000000..bda9946
--- /dev/null
+++ b/board/pxa255_idp/pxa_reg_calcs.out
@@ -0,0 +1,119 @@
+gafr0_l: 0x80001005
+gafr0_u: 0xa5128012
+gafr1_l: 0x699a9558
+gafr1_u: 0xaaa5aa6a
+gafr2_l: 0xaaaaaaaa
+gafr2_u: 0x2
+gpcr0: 0x1800400
+gpcr1: 0x0
+gpcr2: 0x0
+gpdr0: 0xc1818440
+gpdr1: 0xfcffab82
+gpdr2: 0x1ffff
+gpsr0: 0x8000
+gpsr1: 0x3f0002
+gpsr2: 0x1c000
+
+
+#define CFG_GAFR0_L_VAL	0x80001005
+#define CFG_GAFR0_U_VAL	0xa5128012
+#define CFG_GAFR1_L_VAL	0x699a9558
+#define CFG_GAFR1_U_VAL	0xaaa5aa6a
+#define CFG_GAFR2_L_VAL	0xaaaaaaaa
+#define CFG_GAFR2_U_VAL	0x2
+#define CFG_GPCR0_VAL	0x1800400
+#define CFG_GPCR1_VAL	0x0
+#define CFG_GPCR2_VAL	0x0
+#define CFG_GPDR0_VAL	0xc1818440
+#define CFG_GPDR1_VAL	0xfcffab82
+#define CFG_GPDR2_VAL	0x1ffff
+#define CFG_GPSR0_VAL	0x8000
+#define CFG_GPSR1_VAL	0x3f0002
+#define CFG_GPSR2_VAL	0x1c000
+
+
+GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
+GPIO: 1, dir=0, set=0, clr=0, alt=gpio reset, desc=USER_RESET#
+GPIO: 2, dir=0, set=0, clr=0, alt=gpio, desc=BAT_DATA
+GPIO: 3, dir=0, set=0, clr=0, alt=gpio, desc=MQ_IRQ#
+GPIO: 4, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_ETH
+GPIO: 5, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_TOUCH#
+GPIO: 6, dir=1, set=0, clr=0, alt=MMC clk, desc=MMC_CLK
+GPIO: 7, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S0_CD#
+GPIO: 8, dir=0, set=0, clr=0, alt=gpio, desc=PCC_S1_CD#
+GPIO: 9, dir=0, set=0, clr=0, alt=gpio, desc=MMC_CD#
+GPIO: 10, dir=1, set=0, clr=1, alt=gpio, desc=GPIO_10/RTC_CLK/debug LED
+GPIO: 11, dir=0, set=0, clr=0, alt=gpio, desc=3M6_CLK
+GPIO: 12, dir=0, set=0, clr=0, alt=gpio, desc=GPIO_12/32K_CLK
+GPIO: 13, dir=0, set=0, clr=0, alt=gpio, desc=MBGNT
+GPIO: 14, dir=0, set=0, clr=0, alt=gpio, desc=MBREQ
+GPIO: 15, dir=1, set=1, clr=0, alt=nCS_1, desc=CS1#
+GPIO: 16, dir=1, set=0, clr=0, alt=PWM0, desc=PWM0
+GPIO: 17, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_AXB
+GPIO: 18, dir=0, set=0, clr=0, alt=RDY, desc=RDY
+GPIO: 19, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ1, PCC_SO_IRQ_O#
+GPIO: 20, dir=0, set=0, clr=0, alt=gpio, desc=XB_DREQ0
+GPIO: 21, dir=0, set=0, clr=0, alt=gpio, desc=IRQ_IDE, PFI
+GPIO: 22, dir=0, set=0, clr=0, alt=gpio, desc=Consumer IR, PCC_S1_IRQ_O#
+GPIO: 23, dir=1, set=0, clr=1, alt=SSP SCLK, desc=SSP_SCLK
+GPIO: 24, dir=1, set=0, clr=1, alt=SSP SFRM, desc=SSP_SFRM
+GPIO: 25, dir=0, set=0, clr=0, alt=gpio, desc=SSP_TXD
+GPIO: 26, dir=0, set=0, clr=0, alt=SSP RXD, desc=SSP_RXD
+GPIO: 27, dir=0, set=0, clr=0, alt=gpio, desc=SSP_EXTCLK
+GPIO: 28, dir=0, set=0, clr=0, alt=AC97 bitclk in, I2S bitclock out, desc=AC_BITCLK
+GPIO: 29, dir=0, set=0, clr=0, alt=AC97 SDATA_IN0, desc=AUD_SDIN0
+GPIO: 30, dir=1, set=0, clr=0, alt=AC97 SDATA_OUT, desc=AC_SDOUT
+GPIO: 31, dir=1, set=0, clr=0, alt=AC97 SYNC, desc=AC_SYNC
+GPIO: 32, dir=0, set=0, clr=0, alt=gpio, desc=AUD_SDIN1
+GPIO: 33, dir=1, set=1, clr=0, alt=nCS_5, desc=CS5#
+GPIO: 34, dir=0, set=0, clr=0, alt=FF RXD, desc=FF_RXD
+GPIO: 35, dir=0, set=0, clr=0, alt=FF CTS, desc=FF_CTS
+GPIO: 36, dir=0, set=0, clr=0, alt=FF DCD, desc=FF_DCD
+GPIO: 37, dir=0, set=0, clr=0, alt=FF DSR, desc=FF_DSR
+GPIO: 38, dir=0, set=0, clr=0, alt=FF RI, desc=FF_RI
+GPIO: 39, dir=1, set=0, clr=0, alt=FF TXD, desc=FF_TXD
+GPIO: 40, dir=1, set=0, clr=0, alt=FF DTR, desc=FF_DTR
+GPIO: 41, dir=1, set=0, clr=0, alt=FF RTS, desc=FF_RTS
+GPIO: 42, dir=0, set=0, clr=0, alt=BT RXD, desc=BT_RXD
+GPIO: 43, dir=1, set=0, clr=0, alt=BT TXD, desc=BT_TXD
+GPIO: 44, dir=0, set=0, clr=0, alt=BT CTS, desc=BT_CTS
+GPIO: 45, dir=1, set=0, clr=0, alt=BT RTS, desc=BT_RTS
+GPIO: 46, dir=0, set=0, clr=0, alt=STD RXD, desc=IR_RXD
+GPIO: 47, dir=1, set=0, clr=0, alt=STD TXD, desc=IR_TXD
+GPIO: 48, dir=1, set=1, clr=0, alt=nPOE, desc=PCC_OE#
+GPIO: 49, dir=1, set=1, clr=0, alt=nPWE, desc=PCC_WE#
+GPIO: 50, dir=1, set=1, clr=0, alt=nPIOR, desc=PCC_IOR#
+GPIO: 51, dir=1, set=1, clr=0, alt=nPIOW, desc=PCC_IOW#
+GPIO: 52, dir=1, set=1, clr=0, alt=nPCE[1], desc=PCC_CE1#
+GPIO: 53, dir=1, set=1, clr=0, alt=nPCE[2], desc=PCC_CE2#
+GPIO: 54, dir=1, set=0, clr=0, alt=nPSKSEL, desc=PCC_SCKSEL
+GPIO: 55, dir=1, set=0, clr=0, alt=nPREG, desc=PCC_REG#
+GPIO: 56, dir=0, set=0, clr=0, alt=nPWAIT, desc=PCC_WAIT#
+GPIO: 57, dir=0, set=0, clr=0, alt=nIOIS16, desc=PCC_IOIS16#
+GPIO: 58, dir=1, set=0, clr=0, alt=LDD[0], desc=LDD0
+GPIO: 59, dir=1, set=0, clr=0, alt=LDD[1], desc=LDD1
+GPIO: 60, dir=1, set=0, clr=0, alt=LDD[2], desc=LDD2
+GPIO: 61, dir=1, set=0, clr=0, alt=LDD[3], desc=LDD3
+GPIO: 62, dir=1, set=0, clr=0, alt=LDD[4], desc=LDD4
+GPIO: 63, dir=1, set=0, clr=0, alt=LDD[5], desc=LDD5
+GPIO: 64, dir=1, set=0, clr=0, alt=LDD[6], desc=LDD6
+GPIO: 65, dir=1, set=0, clr=0, alt=LDD[7], desc=LDD7
+GPIO: 66, dir=1, set=0, clr=0, alt=LDD[8], desc=LDD8
+GPIO: 67, dir=1, set=0, clr=0, alt=LDD[9], desc=LDD9
+GPIO: 68, dir=1, set=0, clr=0, alt=LDD[10], desc=LDD10
+GPIO: 69, dir=1, set=0, clr=0, alt=LDD[11], desc=LDD11
+GPIO: 70, dir=1, set=0, clr=0, alt=LDD[12], desc=LDD12
+GPIO: 71, dir=1, set=0, clr=0, alt=LDD[13], desc=LDD13
+GPIO: 72, dir=1, set=0, clr=0, alt=LDD[14], desc=LDD14
+GPIO: 73, dir=1, set=0, clr=0, alt=LDD[15], desc=LDD15
+GPIO: 74, dir=1, set=0, clr=0, alt=LCD_FCLK, desc=FCLK
+GPIO: 75, dir=1, set=0, clr=0, alt=LCD_LCLK, desc=LCLK
+GPIO: 76, dir=1, set=0, clr=0, alt=LCD_PCLK, desc=PCLK
+GPIO: 77, dir=1, set=0, clr=0, alt=LCD_ACBIAS, desc=ACBIAS
+GPIO: 78, dir=1, set=1, clr=0, alt=nCS_2, desc=CS2#
+GPIO: 79, dir=1, set=1, clr=0, alt=nCS_3, desc=CS3#
+GPIO: 80, dir=1, set=1, clr=0, alt=nCS_4, desc=CS4#
+GPIO: 81, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 82, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 83, dir=0, set=0, clr=0, alt=gpio, desc=
+GPIO: 84, dir=0, set=0, clr=0, alt=gpio, desc=
diff --git a/board/pxa255_idp/pxa_reg_calcs.py b/board/pxa255_idp/pxa_reg_calcs.py
new file mode 100755
index 0000000..c4bcb4b
--- /dev/null
+++ b/board/pxa255_idp/pxa_reg_calcs.py
@@ -0,0 +1,311 @@
+#!/usr/bin/python
+
+# (C) Copyright 2004
+# BEC Systems <http://bec-systems.com>
+# Cliff Brake <cliff.brake@gmail.com>
+
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+# calculations for PXA255 registers
+
+class gpio:
+	dir = '0'
+	set = '0'
+	clr = '0'
+	alt = '0'
+	desc = ''
+
+	def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
+		self.dir = dir
+		self.set = set
+		self.clr = clr
+		self.alt = alt
+		self.desc = desc
+		
+
+# the following is a dictionary of all GPIOs in the system
+# the key is the GPIO number
+
+
+pxa255_alt_func = {
+	0: ['gpio', 'none', 'none', 'none'],
+	1: ['gpio', 'gpio reset', 'none', 'none'],
+	2: ['gpio', 'none', 'none', 'none'],
+	3: ['gpio', 'none', 'none', 'none'],
+	4: ['gpio', 'none', 'none', 'none'],
+	5: ['gpio', 'none', 'none', 'none'],
+	6: ['gpio', 'MMC clk', 'none', 'none'],
+	7: ['gpio', '48MHz clock', 'none', 'none'],
+	8: ['gpio', 'MMC CS0', 'none', 'none'],
+	9: ['gpio', 'MMC CS1', 'none', 'none'],
+	10: ['gpio', 'RTC Clock', 'none', 'none'],
+	11: ['gpio', '3.6MHz', 'none', 'none'],
+	12: ['gpio', '32KHz', 'none', 'none'],
+	13: ['gpio', 'none', 'MBGNT', 'none'],
+	14: ['gpio', 'MBREQ', 'none', 'none'],
+	15: ['gpio', 'none', 'nCS_1', 'none'],
+	16: ['gpio', 'none', 'PWM0', 'none'],
+	17: ['gpio', 'none', 'PWM1', 'none'],
+	18: ['gpio', 'RDY', 'none', 'none'],
+	19: ['gpio', 'DREQ[1]', 'none', 'none'],
+	20: ['gpio', 'DREQ[0]', 'none', 'none'],
+	21: ['gpio', 'none', 'none', 'none'],
+	22: ['gpio', 'none', 'none', 'none'],
+	23: ['gpio', 'none', 'SSP SCLK', 'none'],
+	24: ['gpio', 'none', 'SSP SFRM', 'none'],
+	25: ['gpio', 'none', 'SSP TXD', 'none'],
+	26: ['gpio', 'SSP RXD', 'none', 'none'],
+	27: ['gpio', 'SSP EXTCLK', 'none', 'none'],
+	28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'],
+	29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'],
+	30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'],
+	31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'],
+	32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'],
+	33: ['gpio', 'none', 'nCS_5', 'none'],
+	34: ['gpio', 'FF RXD', 'MMC CS0', 'none'],
+	35: ['gpio', 'FF CTS', 'none', 'none'],
+	36: ['gpio', 'FF DCD', 'none', 'none'],
+	37: ['gpio', 'FF DSR', 'none', 'none'],
+	38: ['gpio', 'FF RI', 'none', 'none'],
+	39: ['gpio', 'MMC CS1', 'FF TXD', 'none'],
+	40: ['gpio', 'none', 'FF DTR', 'none'],
+	41: ['gpio', 'none', 'FF RTS', 'none'],
+	42: ['gpio', 'BT RXD', 'none', 'HW RXD'],
+	43: ['gpio', 'none', 'BT TXD', 'HW TXD'],
+	44: ['gpio', 'BT CTS', 'none', 'HW CTS'],
+	45: ['gpio', 'none', 'BT RTS', 'HW RTS'],
+	46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'],
+	47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'],
+	48: ['gpio', 'HW TXD', 'nPOE', 'none'],
+	49: ['gpio', 'HW RXD', 'nPWE', 'none'],
+	50: ['gpio', 'HW CTS', 'nPIOR', 'none'],
+	51: ['gpio', 'nPIOW', 'HW RTS', 'none'],
+	52: ['gpio', 'none', 'nPCE[1]', 'none'],
+	53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'],
+	54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'],
+	55: ['gpio', 'none', 'nPREG', 'none'],
+	56: ['gpio', 'nPWAIT', 'none', 'none'],
+	57: ['gpio', 'nIOIS16', 'none', 'none'],
+	58: ['gpio', 'none', 'LDD[0]', 'none'],
+	59: ['gpio', 'none', 'LDD[1]', 'none'],
+	60: ['gpio', 'none', 'LDD[2]', 'none'],
+	61: ['gpio', 'none', 'LDD[3]', 'none'],
+	62: ['gpio', 'none', 'LDD[4]', 'none'],
+	63: ['gpio', 'none', 'LDD[5]', 'none'],
+	64: ['gpio', 'none', 'LDD[6]', 'none'],
+	65: ['gpio', 'none', 'LDD[7]', 'none'],
+	66: ['gpio', 'MBREQ', 'LDD[8]', 'none'],
+	67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'],
+	68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'],
+	69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'],
+	70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'],
+	71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'],
+	72: ['gpio', '32 KHz', 'LDD[14]', 'none'],
+	73: ['gpio', 'MBGNT', 'LDD[15]', 'none'],
+	74: ['gpio', 'none', 'LCD_FCLK', 'none'],
+	75: ['gpio', 'none', 'LCD_LCLK', 'none'],
+	76: ['gpio', 'none', 'LCD_PCLK', 'none'],
+	77: ['gpio', 'none', 'LCD_ACBIAS', 'none'],
+	78: ['gpio', 'none', 'nCS_2', 'none'],
+	79: ['gpio', 'none', 'nCS_3', 'none'],
+	80: ['gpio', 'none', 'nCS_4', 'none'],
+	81: ['gpio', 'NSSPSCLK', 'none', 'none'],
+	82: ['gpio', 'NSSPSFRM', 'none', 'none'],
+	83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
+	84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'],
+}
+
+
+#def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''):
+
+gpio_list = []
+
+for i in range(0,85):
+	gpio_list.append(gpio())
+
+#chip select GPIOs
+gpio_list[18] = gpio(0, 0, 0, 1, 'RDY')
+gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#')
+gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#')
+gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#')
+gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#')
+gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#')
+gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#')
+gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI')
+gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#')
+gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
+gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0')
+gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB')
+gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0')
+
+# PCMCIA stuff
+gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#')
+gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#')
+gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#')
+gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL')
+gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#')
+gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#')
+gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#')
+gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#')
+gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#')
+gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#')
+
+# SSP port
+gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD')
+gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD')
+gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM')
+gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK')
+gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK')
+
+# audio codec
+gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1')
+gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC')
+gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT')
+gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0')
+gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK')
+
+# serial ports
+gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD')
+gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD')
+gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS')
+gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS')
+gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR')
+gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR')
+gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI')
+gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD')
+
+gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD')
+gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD')
+gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS')
+gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS')
+
+gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD')
+gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD')
+
+# misc GPIO signals
+gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ')
+gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT')
+gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK')
+gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK')
+gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED')
+gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#')
+gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#')
+gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#')
+gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK')
+gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#')
+gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH')
+gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#')
+gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA')
+gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#')
+gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#')
+
+# LCD GPIOs
+gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0')
+gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1')
+gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2')
+gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3')
+gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4')
+gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5')
+gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6')
+gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7')
+gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8')
+gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9')
+gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10')
+gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11')
+gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12')
+gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13')
+gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14')
+gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15')
+gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK')
+gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK')
+gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK')
+gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS')
+
+# calculate registers
+pxa_regs = {
+	'gpdr0':0, 'gpdr1':0, 'gpdr2':0,
+	'gpsr0':0, 'gpsr1':0, 'gpsr2':0,
+	'gpcr0':0, 'gpcr1':0, 'gpcr2':0,
+	'gafr0_l':0, 'gafr0_u':0,
+	'gafr1_l':0, 'gafr1_u':0,
+	'gafr2_l':0, 'gafr2_u':0,
+}
+
+# U-boot define names
+uboot_reg_names = {
+	'gpdr0':'CFG_GPDR0_VAL', 'gpdr1':'CFG_GPDR1_VAL', 'gpdr2':'CFG_GPDR2_VAL',
+	'gpsr0':'CFG_GPSR0_VAL', 'gpsr1':'CFG_GPSR1_VAL', 'gpsr2':'CFG_GPSR2_VAL',
+	'gpcr0':'CFG_GPCR0_VAL', 'gpcr1':'CFG_GPCR1_VAL', 'gpcr2':'CFG_GPCR2_VAL',
+	'gafr0_l':'CFG_GAFR0_L_VAL', 'gafr0_u':'CFG_GAFR0_U_VAL',
+	'gafr1_l':'CFG_GAFR1_L_VAL', 'gafr1_u':'CFG_GAFR1_U_VAL',
+	'gafr2_l':'CFG_GAFR2_L_VAL', 'gafr2_u':'CFG_GAFR2_U_VAL',
+}
+
+# bit mappings
+
+bit_mappings = [
+
+{ 'gpio':(0,32),  'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} },
+{ 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} },
+{ 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} },
+{ 'gpio':(0,16),  'shift':2, 'regs':{'alt':'gafr0_l'} },
+{ 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} },
+{ 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} },
+{ 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} },
+{ 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} },
+{ 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} },
+
+]
+
+def stuff_bits(bit_mapping, gpio_list):
+	gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1])
+
+	for gpio in gpios:
+		for reg in bit_mapping['regs'].keys():
+			value = eval( 'gpio_list[gpio].%s' % (reg) )
+			if ( value ):
+				# we have a high bit
+				bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift']
+				bit = value << (bit_shift)
+				pxa_regs[bit_mapping['regs'][reg]] |= bit
+
+for i in bit_mappings:
+	stuff_bits(i, gpio_list)
+
+# now print out all regs
+registers = pxa_regs.keys()
+registers.sort()
+for reg in registers:
+	print '%s: 0x%x' % (reg, pxa_regs[reg])
+
+# print define to past right into U-Boot source code
+
+print 
+print 
+
+for reg in registers:
+	print '#define %s	0x%x' % (uboot_reg_names[reg], pxa_regs[reg])
+
+# print all GPIOS
+print
+print
+
+for i in range(len(gpio_list)):
+	gpio_i = gpio_list[i]
+	alt_func_desc = pxa255_alt_func[i][gpio_i.alt]
+	print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc)
+
+
diff --git a/board/pxa255_idp/u-boot.lds b/board/pxa255_idp/u-boot.lds
new file mode 100755
index 0000000..20ce108
--- /dev/null
+++ b/board/pxa255_idp/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/quantum/Makefile b/board/quantum/Makefile
new file mode 100755
index 0000000..e50f5ff
--- /dev/null
+++ b/board/quantum/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o fpga.o
+
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/quantum/config.mk b/board/quantum/config.mk
new file mode 100755
index 0000000..7cb374e
--- /dev/null
+++ b/board/quantum/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RMU boards
+#
+
+TEXT_BASE = 0xfff00000
diff --git a/board/quantum/fpga.c b/board/quantum/fpga.c
new file mode 100755
index 0000000..75c2658
--- /dev/null
+++ b/board/quantum/fpga.c
@@ -0,0 +1,263 @@
+/*
+ * (C) Copyright 2001-2003
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* The DEBUG define must be before common to enable debugging */
+#undef DEBUG
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include "fpga.h"
+/* ------------------------------------------------------------------------- */
+
+#define MAX_ONES               226
+
+/* MPC850 port D */
+#define PD(bit) (1 << (15 - (bit)))
+# define FPGA_INIT             PD(11)	/* FPGA init pin (ppc input)     */
+# define FPGA_PRG              PD(12)	/* FPGA program pin (ppc output) */
+# define FPGA_CLK              PD(13)	/* FPGA clk pin (ppc output)     */
+# define FPGA_DATA             PD(14)	/* FPGA data pin (ppc output)    */
+# define FPGA_DONE             PD(15)	/* FPGA done pin (ppc input)     */
+
+
+/* DDR 0 - input, 1 - output */
+#define FPGA_INIT_PDDIR          FPGA_PRG | FPGA_CLK | FPGA_DATA	/* just set outputs */
+
+
+#define SET_FPGA(data)         immr->im_ioport.iop_pddat = (data)
+#define GET_FPGA               immr->im_ioport.iop_pddat
+
+#define FPGA_WRITE_1 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);}	/* set data to 1  */
+
+#define FPGA_WRITE_0 {                                                    \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);}	/* set data to 1  */
+
+
+int fpga_boot (unsigned char *fpgadata, int size)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	int i, index, len;
+	int count;
+
+#ifdef CFG_FPGA_SPARTAN2
+	int j;
+	unsigned char data;
+#else
+	unsigned char b;
+	int bit;
+#endif
+
+	debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size);
+
+	/* display infos on fpgaimage */
+	printf ("FPGA:");
+	index = 15;
+	for (i = 0; i < 4; i++) {
+		len = fpgadata[index];
+		printf (" %s", &(fpgadata[index + 1]));
+		index += len + 3;
+	}
+	printf ("\n");
+
+
+	index = 0;
+
+#ifdef CFG_FPGA_SPARTAN2
+	/* search for preamble 0xFFFFFFFF */
+	while (1) {
+		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
+		    && (fpgadata[index + 2] == 0xff)
+		    && (fpgadata[index + 3] == 0xff))
+			break;	/* preamble found */
+		else
+			index++;
+	}
+#else
+	/* search for preamble 0xFF2X */
+	for (index = 0; index < size - 1; index++) {
+		if ((fpgadata[index] == 0xff)
+		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
+			break;
+	}
+	index += 2;
+#endif
+
+	debug ("FPGA: configdata starts at position 0x%x\n", index);
+	debug ("FPGA: length of fpga-data %d\n", size - index);
+
+	/*
+	 * Setup port pins for fpga programming
+	 */
+	immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR;
+
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Init fpga by asserting and deasserting PROGRAM*
+	 */
+	SET_FPGA (FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA init line low */
+	count = 0;
+	while (GET_FPGA & FPGA_INIT) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout - 100us max, so use 3ms */
+		if (count++ > 3) {
+			debug ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_LOW;
+		}
+	}
+
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/* deassert PROGRAM* */
+	SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
+
+	/* Wait for FPGA end of init period .  */
+	count = 0;
+	while (!(GET_FPGA & FPGA_INIT)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			debug ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_INIT_HIGH;
+		}
+	}
+
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	debug ("write configuration data into fpga\n");
+	/* write configuration-data into fpga... */
+
+#ifdef CFG_FPGA_SPARTAN2
+	/*
+	 * Load uncompressed image into fpga
+	 */
+	for (i = index; i < size; i++) {
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		if ((i % 1024) == 0)
+			printf ("%6d out of %6d\r", i, size);	/* let them know we are alive */
+#endif
+
+		data = fpgadata[i];
+		for (j = 0; j < 8; j++) {
+			if ((data & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			data <<= 1;
+		}
+	}
+	/* add some 0xff to the end of the file */
+	for (i = 0; i < 8; i++) {
+		data = 0xff;
+		for (j = 0; j < 8; j++) {
+			if ((data & 0x80) == 0x80) {
+				FPGA_WRITE_1;
+			} else {
+				FPGA_WRITE_0;
+			}
+			data <<= 1;
+		}
+	}
+#else
+	/* send 0xff 0x20 */
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_1;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+	FPGA_WRITE_0;
+
+	/*
+	 ** Bit_DeCompression
+	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
+	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
+	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
+	 **        255                        :                   '1'
+	 */
+
+	for (i = index; i < size; i++) {
+		b = fpgadata[i];
+		if ((b >= 1) && (b <= MAX_ONES)) {
+			for (bit = 0; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+			FPGA_WRITE_0;
+		} else if (b == (MAX_ONES + 1)) {
+			for (bit = 1; bit < b; bit++) {
+				FPGA_WRITE_1;
+			}
+		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
+			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
+				FPGA_WRITE_0;
+			}
+			FPGA_WRITE_1;
+		} else if (b == 255) {
+			FPGA_WRITE_1;
+		}
+	}
+#endif
+	debug ("\n\n");
+	debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
+	debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
+
+	/*
+	 * Check if fpga's DONE signal - correctly booted ?
+	 */
+
+	/* Wait for FPGA end of programming period .  */
+	count = 0;
+	while (!(GET_FPGA & FPGA_DONE)) {
+		udelay (1000);	/* wait 1ms */
+		/* Check for timeout */
+		if (count++ > 3) {
+			debug ("FPGA: Booting failed!\n");
+			return ERROR_FPGA_PRG_DONE;
+		}
+	}
+
+	debug ("FPGA: Booting successful!\n");
+	return 0;
+}
diff --git a/board/quantum/fpga.h b/board/quantum/fpga.h
new file mode 100755
index 0000000..2ef45e5
--- /dev/null
+++ b/board/quantum/fpga.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Virtex2 FPGA configuration support for the QUANTUM computer
+ */
+int fpga_boot(unsigned char *fpgadata, int size);
+
+#define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
+#define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
+#define ERROR_FPGA_PRG_DONE      -3        /* Timeout after programming     */
+/* vim: set ts=4 sw=4 tw=78: */
diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c
new file mode 100755
index 0000000..2861bc3
--- /dev/null
+++ b/board/quantum/quantum.c
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "fpga.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+unsigned long flash_init (void);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 * (Initialization code at 0x36)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	puts ("Board QUANTUM, Serial No: ");
+
+	for (; s && *s; ++s) {
+		if (*s == ' ')
+			break;
+		putc (*s);
+	}
+	putc ('\n');
+	return (0);		/* success */
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002136;	/* SDRAM bank 0 */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size,
+	 * 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+			   SDRAM_MAX_SIZE);
+	/*
+	 * Final mapping:
+	 */
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	udelay (1000);
+
+	return (size9);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile ulong *addr;
+	ulong cnt, val, size;
+	ulong save[32];		/* to make test non-destructive */
+	unsigned char i = 0;
+
+	memctl->memc_mamr = mamr_value;
+
+	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	/* write 0 to base address */
+	addr = base;
+	save[i] = *addr;
+	*addr = 0;
+
+	/* check at base address */
+	if ((val = *addr) != 0) {
+		/* Restore the original data before leaving the function.
+		 */
+		*addr = save[i];
+		for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+			addr = (volatile ulong *) base + cnt;
+			*addr = save[--i];
+		}
+		return (0);
+	}
+
+	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
+		addr = base + cnt;	/* pointer arith! */
+
+		val = *addr;
+		*addr = save[--i];
+
+		if (val != (~cnt)) {
+			size = cnt * sizeof (long);
+			/* Restore the original data before returning
+			 */
+			for (cnt <<= 1; cnt <= maxsize / sizeof (long);
+			     cnt <<= 1) {
+				addr = (volatile ulong *) base + cnt;
+				*addr = save[--i];
+			}
+			return (size);
+		}
+	}
+	return (maxsize);
+}
+
+/*
+ * Miscellaneous intialization
+ */
+int misc_init_r (void)
+{
+	char *fpga_data_str = getenv ("fpgadata");
+	char *fpga_size_str = getenv ("fpgasize");
+	void *fpga_data;
+	int fpga_size;
+	int status;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	int flash_size;
+
+	/* Remap FLASH according to real size */
+	flash_size = flash_init ();
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	if (fpga_data_str && fpga_size_str) {
+		fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
+		fpga_size = simple_strtoul (fpga_size_str, NULL, 10);
+
+		status = fpga_boot (fpga_data, fpga_size);
+		if (status != 0) {
+			printf ("\nFPGA: Booting failed ");
+			switch (status) {
+			case ERROR_FPGA_PRG_INIT_LOW:
+				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_INIT_HIGH:
+				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				break;
+			case ERROR_FPGA_PRG_DONE:
+				printf ("(Timeout: DONE not high after programming FPGA)\n ");
+				break;
+			}
+		}
+	}
+	return 0;
+}
diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds
new file mode 100755
index 0000000..049f990
--- /dev/null
+++ b/board/quantum/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+/* XXX ?
+    . = env_offset;
+*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug
new file mode 100755
index 0000000..894b9bd
--- /dev/null
+++ b/board/quantum/u-boot.lds.debug
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/r360mpi/Makefile b/board/r360mpi/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/r360mpi/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/r360mpi/config.mk b/board/r360mpi/config.mk
new file mode 100755
index 0000000..9d6080b
--- /dev/null
+++ b/board/r360mpi/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8xxL boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/r360mpi/flash.c b/board/r360mpi/flash.c
new file mode 100755
index 0000000..9b42960
--- /dev/null
+++ b/board/r360mpi/flash.c
@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#else
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#endif
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+				CFG_FLASH_BASE,
+				CFG_FLASH_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	FPW value;
+
+	/* Make sure Block Lock Bits get cleared */
+	addr[0] = (FPW) 0x00FF00FF;
+	addr[0] = (FPW) 0x00600060;
+	addr[0] = (FPW) 0x00D000D0;
+	addr[0] = (FPW) 0x00FF00FF;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	value = addr[1];			/* device ID        */
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 4 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+				rcode = 1;
+				break;
+			    }
+
+			    /* show that we're waiting */
+			    if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			    }
+			}
+
+			*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+
+	int i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c
new file mode 100755
index 0000000..ffb4c0e
--- /dev/null
+++ b/board/r360mpi/r360mpi.c
@@ -0,0 +1,419 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+#include <i2c.h>
+
+#include <commproc.h>
+#include <command.h>
+#include <malloc.h>
+
+#include <linux/types.h>
+#include <linux/string.h>       /* for strdup */
+
+
+/*
+ *  Memory Controller Using
+ *
+ *  CS0 - Flash memory		(0x40000000)
+ *  CS1 - FLASH memory		(0x????????)
+ *  CS2 - SDRAM			(0x00000000)
+ *  CS3 -
+ *  CS4 -
+ *  CS5 -
+ *  CS6 - PCMCIA device
+ *  CS7 - PCMCIA device
+ */
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_	0xffffffff
+
+const uint sdram_table[]=
+{
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* MRS initialization (offset 5) */
+
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_ };
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: R360 MPI Board\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
+	unsigned long reg;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 2 to the SDRAM bank at
+	 * preliminary address - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or2 = CFG_OR2_PRELIM;
+	memctl->memc_br2 = CFG_BR2_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+	udelay (200);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
+	udelay (200);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 2 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {		/* leave configuration at 9 columns */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {			/* back to 8 columns            */
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;		/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+#ifdef CONFIG_CAN_DRIVER
+	/* Initialize OR3 / BR3 */
+	memctl->memc_or3 = CFG_OR3_CAN;		/* switch GPLB_5 to GPLA_5 */
+	memctl->memc_br3 = CFG_BR3_CAN;
+
+	/* Initialize MBMR */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 works as UPWAITB */
+
+	/* Initialize UPMB for CAN: single read */
+	memctl->memc_mdr = 0xFFFFC004;
+	memctl->memc_mcr = 0x0100 | UPMB;
+
+	memctl->memc_mdr = 0x0FFFD004;
+	memctl->memc_mcr = 0x0101 | UPMB;
+
+	memctl->memc_mdr = 0x0FFFC000;
+	memctl->memc_mcr = 0x0102 | UPMB;
+
+	memctl->memc_mdr = 0x3FFFC004;
+	memctl->memc_mcr = 0x0103 | UPMB;
+
+	memctl->memc_mdr = 0xFFFFDC05;
+	memctl->memc_mcr = 0x0104 | UPMB;
+
+	/* Initialize UPMB for CAN: single write */
+	memctl->memc_mdr = 0xFFFCC004;
+	memctl->memc_mcr = 0x0118 | UPMB;
+
+	memctl->memc_mdr = 0xCFFCD004;
+	memctl->memc_mcr = 0x0119 | UPMB;
+
+	memctl->memc_mdr = 0x0FFCC000;
+	memctl->memc_mcr = 0x011A | UPMB;
+
+	memctl->memc_mdr = 0x7FFCC004;
+	memctl->memc_mcr = 0x011B | UPMB;
+
+	memctl->memc_mdr = 0xFFFDCC05;
+	memctl->memc_mcr = 0x011C | UPMB;
+#endif
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value,
+			   long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void r360_i2c_lcd_write (uchar data0, uchar data1)
+{
+	if (i2c_write (CFG_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
+		printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*-----------------------------------------------------------------------
+ * Keyboard Controller
+ */
+
+/* Number of bytes returned from Keyboard Controller */
+#define KEYBD_KEY_MAX	16				/* maximum key number */
+#define KEYBD_DATALEN	((KEYBD_KEY_MAX + 7) / 8)	/* normal key scan data */
+
+static uchar *key_match (uchar *);
+
+int misc_init_r (void)
+{
+	char kbd_data[KEYBD_DATALEN];
+	char keybd_env[2 * KEYBD_DATALEN + 1];
+	char *str;
+	int i;
+
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	i2c_read (CFG_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
+
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+	}
+	setenv ("keybd", keybd_env);
+
+	str = strdup ((char *)key_match ((uchar *)keybd_env));	/* decode keys */
+
+#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
+	setenv ("preboot", str);	/* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+	if (str != NULL) {
+		free (str);
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Check if pressed key(s) match magic sequence,
+ * and return the command string associated with that key(s).
+ *
+ * If no key press was decoded, NULL is returned.
+ *
+ * Note: the first character of the argument will be overwritten with
+ * the "magic charcter code" of the decoded key(s), or '\0'.
+ *
+ *
+ * Note: the string points to static environment data and must be
+ * saved before you call any function that modifies the environment.
+ */
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static uchar *key_match (uchar * kbd_str)
+{
+	uchar magic[sizeof (kbd_magic_prefix) + 1];
+	uchar cmd_name[sizeof (kbd_command_prefix) + 1];
+	uchar *str, *suffix;
+	uchar *kbd_magic_keys;
+	char *cmd;
+
+	/*
+	 * The following string defines the characters that can pe appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) {
+		/* loop over all magic keys;
+		 * use '\0' suffix in case of empty string
+		 */
+		for (suffix = kbd_magic_keys;
+		     *suffix || suffix == kbd_magic_keys;
+		     ++suffix) {
+			sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix);
+
+#if 0
+			printf ("### Check magic \"%s\"\n", magic);
+#endif
+
+			if ((str = (uchar *)getenv ((char *)magic)) != 0) {
+
+#if 0
+				printf ("### Compare \"%s\" \"%s\"\n",
+					kbd_str, str);
+#endif
+				if (strcmp ((char *)kbd_str, (char *)str) == 0) {
+					sprintf ((char *)cmd_name, "%s%c",
+						 kbd_command_prefix,
+						 *suffix);
+
+					if ((cmd = getenv ((char *)cmd_name)) != 0) {
+#if 0
+						printf ("### Set PREBOOT to $(%s): \"%s\"\n",
+							cmd_name, cmd);
+#endif
+						return ((uchar *)cmd);
+					}
+				}
+			}
+		}
+	}
+#if 0
+	printf ("### Delete PREBOOT\n");
+#endif
+	*kbd_str = '\0';
+	return (NULL);
+}
+#endif	/* CONFIG_PREBOOT */
+
+/* Read Keyboard status */
+int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	uchar kbd_data[KEYBD_DATALEN];
+	uchar keybd_env[2 * KEYBD_DATALEN + 1];
+	int i;
+
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/* Read keys */
+	i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
+
+	puts ("Keys:");
+	for (i = 0; i < KEYBD_DATALEN; ++i) {
+		sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]);
+		printf (" %02x", kbd_data[i]);
+	}
+	putc ('\n');
+	setenv ("keybd", (char *)keybd_env);
+	return 0;
+}
+
+U_BOOT_CMD(
+	kbd,	1,	1,	do_kbd,
+	"kbd     - read keyboard status\n",
+	NULL
+);
diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds
new file mode 100755
index 0000000..8b06af7
--- /dev/null
+++ b/board/r360mpi/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/cpu_init.o	(.text)
+    cpu/mpc8xx/interrupts.o	(.text)
+    cpu/mpc8xx/traps.o		(.text)
+/***
+    . = env_offset;
+    common/environment.o	(.text)
+***/
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+  . = ALIGN(128 * 1024);
+  .ppcenv	:
+  {
+    common/environment.o (.ppcenv)
+  }
+}
diff --git a/board/rattler/Makefile b/board/rattler/Makefile
new file mode 100755
index 0000000..52f0fd6
--- /dev/null
+++ b/board/rattler/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/rattler/config.mk b/board/rattler/config.mk
new file mode 100755
index 0000000..5fca8c7
--- /dev/null
+++ b/board/rattler/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Rattler series boards by Analogue & Micro
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c
new file mode 100755
index 0000000..be7977d
--- /dev/null
+++ b/board/rattler/rattler.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Rattler boards family.
+ * Tested on Rattler8248.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <ioports.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
+	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
+	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
+	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
+	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
+	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
+	/* PA22 */ { 1,          0,   0,   1,   0,   1 }, /* Eth PHYs reset  */
+	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
+	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
+	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
+	/* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK10) */
+	/* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK11) */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
+	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19            */
+	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
+	/* PC17 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK15) */
+	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
+	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
+	/* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
+	/* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
+	/* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
+	/* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
+	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
+	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
+	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
+	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
+	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
+	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
+	/* PD15 */ { 0,          0,   0,   0,   0,   0 }, /* PD15            */
+	/* PD14 */ { 0,          0,   0,   0,   0,   0 }, /* PD14            */
+	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
+	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
+	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
+	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
+	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
+	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
+    }
+};
+
+long int initdram(int board_type)
+{
+	long int msize = CFG_SDRAM_SIZE;
+
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
+	uchar c = 0xFF;
+	uint psdmr = CFG_PSDMR;
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or1  = CFG_SDRAM_OR;
+	memctl->memc_br1  = CFG_SDRAM_BR;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+	*ramaddr = c;
+#endif /* !CFG_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
+	return 0;
+}
diff --git a/board/rattler/u-boot.lds b/board/rattler/u-boot.lds
new file mode 100755
index 0000000..522e6da
--- /dev/null
+++ b/board/rattler/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/rbc823/Makefile b/board/rbc823/Makefile
new file mode 100755
index 0000000..0121ddc
--- /dev/null
+++ b/board/rbc823/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o kbd.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/rbc823/config.mk b/board/rbc823/config.mk
new file mode 100755
index 0000000..199ea3c
--- /dev/null
+++ b/board/rbc823/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RBC823 boards
+#
+
+TEXT_BASE = 0xFFF00000
diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c
new file mode 100755
index 0000000..84ae5c1
--- /dev/null
+++ b/board/rbc823/flash.c
@@ -0,0 +1,469 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+	    flash_info[i].flash_id = FLASH_UNKNOWN;
+
+	/* Detect size */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	/* Setup offsets */
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* Monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	size_b1 = 0 ;
+
+	flash_info[1].flash_id = FLASH_UNKNOWN;
+	flash_info[1].sector_count = -1;
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ * Fix this to support variable sector sizes
+*/
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+	{
+		puts ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case FLASH_MAN_AMD:	printf ("AMD ");		break;
+		case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+		case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+		default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK)
+	{
+		case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+			break;
+		case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+					break;
+		case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+					break;
+		case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+					break;
+		default:		printf ("Unknown Chip Type\n");
+					break;
+	}
+
+	if (info->size >> 20) {
+	    printf ("  Size: %ld MB in %d Sectors\n",
+	    	info->size >> 20,
+		info->sector_count);
+	} else {
+	    printf ("  Size: %ld KB in %d Sectors\n",
+	    	info->size >> 10,
+		info->sector_count);
+	}
+
+	puts ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i)
+	{
+		if ((i % 5) == 0)
+		{
+			puts ("\n   ");
+		}
+
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	putc ('\n');
+	return;
+}
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	volatile unsigned char *caddr;
+	char value;
+
+	caddr = (volatile unsigned char *)addr ;
+
+	/* Write auto select command: read Manufacturer ID */
+
+#if 0
+	printf("Base address is: %08x\n", caddr);
+#endif
+
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	value = caddr[0];
+
+#if 0
+	printf("Manufact ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case 0x01: /*AMD_MANUFACT*/
+			info->flash_id = FLASH_MAN_AMD;
+		break;
+
+		case 0x04: /*FUJ_MANUFACT*/
+			info->flash_id = FLASH_MAN_FUJ;
+		break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+	}
+
+	value = caddr[1];			/* device ID		*/
+#if 0
+	printf("Device ID: %02x\n", value);
+#endif
+	switch (value)
+	{
+		case AMD_ID_LV040B:
+			info->flash_id += FLASH_AM040;
+			info->sector_count = 8;
+			info->size = 0x00080000;
+			break;				/* => 512Kb 		*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);			/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets ((ulong)addr, &flash_info[0]);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++)
+	{
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN)
+	{
+		caddr = (volatile unsigned char *)info->start[0];
+		*caddr = 0xF0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (volatile unsigned char *)(info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile unsigned char *)(info->start[l_sect]);
+
+	while ((addr[0] & 0xFF) != 0xFF)
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned char *)info->start[0];
+
+	addr[0] = 0xF0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]),
+				*cdest,*cdata;
+	ulong start;
+	int flag, count = 4 ;
+
+	cdest = (volatile unsigned char *)dest ;
+	cdata = (volatile unsigned char *)&data ;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	while(count--)
+	{
+	    /* Disable interrupts which might cause a timeout here */
+	    flag = disable_interrupts();
+
+	    addr[0x0555] = 0xAA;
+	    addr[0x02AA] = 0x55;
+	    addr[0x0555] = 0xA0;
+
+	    *cdest = *cdata;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	    	enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((*cdest ^ *cdata) & 0x80)
+	    {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	    }
+
+	    cdata++ ;
+	    cdest++ ;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c
new file mode 100755
index 0000000..c27929d
--- /dev/null
+++ b/board/rbc823/kbd.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Modified by Udi Finkelstein
+ *
+ * This file includes communication routines for SMC1 that can run even if
+ * SMC2 have already been initialized.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <commproc.h>
+#include <devices.h>
+#include <lcd.h>
+
+#define	SMC_INDEX	0
+#define PROFF_SMC	PROFF_SMC1
+#define CPM_CR_CH_SMC	CPM_CR_CH_SMC1
+
+#define RBC823_KBD_BAUDRATE	38400
+#define CPM_KEYBOARD_BASE	0x1000
+/*
+ * Minimal serial functions needed to use one of the SMC ports
+ * as serial console interface.
+ */
+
+void smc1_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+
+	/* Set up the baud rate generator.
+	 * See 8xx_io/commproc.c for details.
+	 *
+	 * Wire BRG2 to SMC1, BRG1 to SMC2
+	 */
+
+	cp->cp_simode = 0x00001000;
+
+	cp->cp_brgc2 =
+		(((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
+}
+
+int smc1_init (void)
+{
+	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile smc_t *sp;
+	volatile smc_uart_t *up;
+	volatile cbd_t *tbdf, *rbdf;
+	volatile cpm8xx_t *cp = &(im->im_cpm);
+	uint	dpaddr;
+
+	/* initialize pointers to SMC */
+
+	sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
+	up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
+
+	/* Disable transmitter/receiver.
+	*/
+	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+
+	/* Enable SDMA.
+	*/
+	im->im_siu_conf.sc_sdcr = 1;
+
+	/* clear error conditions */
+#ifdef	CFG_SDSR
+	im->im_sdma.sdma_sdsr = CFG_SDSR;
+#else
+	im->im_sdma.sdma_sdsr = 0x83;
+#endif
+
+	/* clear SDMA interrupt mask */
+#ifdef	CFG_SDMR
+	im->im_sdma.sdma_sdmr = CFG_SDMR;
+#else
+	im->im_sdma.sdma_sdmr = 0x00;
+#endif
+
+	/* Use Port B for SMC1 instead of other functions.
+	*/
+	cp->cp_pbpar |=  0x000000c0;
+	cp->cp_pbdir &= ~0x000000c0;
+	cp->cp_pbodr &= ~0x000000c0;
+
+	/* Set the physical address of the host memory buffers in
+	 * the buffer descriptors.
+	 */
+
+#ifdef CFG_ALLOC_DPRAM
+	dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
+#else
+	dpaddr = CPM_KEYBOARD_BASE ;
+#endif
+
+	/* Allocate space for two buffer descriptors in the DP ram.
+	 * For now, this address seems OK, but it may have to
+	 * change with newer versions of the firmware.
+	 * damm: allocating space after the two buffers for rx/tx data
+	 */
+
+	rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
+	rbdf->cbd_bufaddr = (uint) (rbdf+2);
+	rbdf->cbd_sc = 0;
+	tbdf = rbdf + 1;
+	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
+	tbdf->cbd_sc = 0;
+
+	/* Set up the uart parameters in the parameter ram.
+	*/
+	up->smc_rbase = dpaddr;
+	up->smc_tbase = dpaddr+sizeof(cbd_t);
+	up->smc_rfcr = SMC_EB;
+	up->smc_tfcr = SMC_EB;
+
+	/* Set UART mode, 8 bit, no parity, one stop.
+	 * Enable receive and transmit.
+	 */
+	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
+
+	/* Mask all interrupts and remove anything pending.
+	*/
+	sp->smc_smcm = 0;
+	sp->smc_smce = 0xff;
+
+	/* Set up the baud rate generator.
+	*/
+	smc1_setbrg ();
+
+	/* Make the first buffer the only buffer.
+	*/
+	tbdf->cbd_sc |= BD_SC_WRAP;
+	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+
+	/* Single character receive.
+	*/
+	up->smc_mrblr = 1;
+	up->smc_maxidl = 0;
+
+	/* Initialize Tx/Rx parameters.
+	*/
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	/* Enable transmitter/receiver.
+	*/
+	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+
+	return (0);
+}
+
+void smc1_putc(const char c)
+{
+	volatile cbd_t		*tbdf;
+	volatile char		*buf;
+	volatile smc_uart_t	*up;
+	volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
+
+	/* Wait for last character to go.
+	*/
+
+	buf = (char *)tbdf->cbd_bufaddr;
+
+	*buf = c;
+	tbdf->cbd_datlen = 1;
+	tbdf->cbd_sc |= BD_SC_READY;
+	__asm__("eieio");
+
+	while (tbdf->cbd_sc & BD_SC_READY) {
+		WATCHDOG_RESET ();
+		__asm__("eieio");
+	}
+}
+
+int smc1_getc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile unsigned char	*buf;
+	volatile smc_uart_t	*up;
+	volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+	unsigned char		c;
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+
+	/* Wait for character to show up.
+	*/
+	buf = (unsigned char *)rbdf->cbd_bufaddr;
+
+	while (rbdf->cbd_sc & BD_SC_EMPTY)
+		WATCHDOG_RESET ();
+
+	c = *buf;
+	rbdf->cbd_sc |= BD_SC_EMPTY;
+
+	return(c);
+}
+
+int smc1_tstc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile smc_uart_t	*up;
+	volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
+
+	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
+
+	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
+
+	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
+}
+
+/* search for keyboard and register it if found */
+int drv_keyboard_init(void)
+{
+	int error = 0;
+	device_t kbd_dev;
+
+	if (0) {
+		/* register the keyboard */
+		memset (&kbd_dev, 0, sizeof(device_t));
+		strcpy(kbd_dev.name, "kbd");
+		kbd_dev.flags =  DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+		kbd_dev.putc = NULL;
+		kbd_dev.puts = NULL;
+		kbd_dev.getc = smc1_getc;
+		kbd_dev.tstc = smc1_tstc;
+		error = device_register (&kbd_dev);
+	} else {
+		lcd_is_enabled = 0;
+		lcd_disable();
+	}
+	return error;
+}
diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c
new file mode 100755
index 0000000..9e60c2b
--- /dev/null
+++ b/board/rbc823/rbc823.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "mpc8xx.h"
+#include <linux/mtd/doc2000.h>
+
+extern int kbd_init(void);
+extern int drv_kbd_init(void);
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x1FF7FC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+const uint static_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
+	0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
+	0xFFFFFC04, 0xFFFFFC05, /* last */
+	                        _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
+	0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Return 1 for "L" type, 0 else.
+ */
+
+int checkboard (void)
+{
+	char *s = getenv ("serial#");
+
+	if (!s || strncmp (s, "TQM8", 4)) {
+		printf ("### No HW ID - assuming RBC823\n");
+		return (0);
+	}
+
+	puts (s);
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0, size8, size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * 1 Bank of 64Mbit x 2 devices
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller SDRAM bank 0
+	 */
+	memctl->memc_or4 = CFG_OR4_PRELIM;
+	memctl->memc_br4 = CFG_BR4_PRELIM;
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	udelay (200);
+
+	/*
+	 * Perform SDRAM initializsation sequence
+	 */
+	memctl->memc_mcr = 0x80008105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
+	udelay (200);
+	memctl->memc_mcr = 0x80008130;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+	memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
+	udelay (200);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+	udelay (1000);
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;	/* 16: but should be: CFG_MPTPR_1BK_4K */
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
+			   SDRAM_MAX_SIZE);
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	if (size8 < size9) {	/* leave configuration at 9 columns     */
+		size_b0 = size9;
+/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
+	} else {		/* back to 8 columns                    */
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
+	}
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/* SDRAM Bank 0 is bigger - map first       */
+
+	memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	udelay (10000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+void doc_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig (UPMB, (uint *) static_table,
+		   sizeof (static_table) / sizeof (uint));
+	memctl->memc_mbmr = MAMR_DSA_1_CYCL;
+
+	doc_probe (FLASH_BASE1_PRELIM);
+}
diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds
new file mode 100755
index 0000000..68ca856
--- /dev/null
+++ b/board/rbc823/u-boot.lds
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/rmu/Makefile b/board/rmu/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/rmu/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/rmu/config.mk b/board/rmu/config.mk
new file mode 100755
index 0000000..7cb374e
--- /dev/null
+++ b/board/rmu/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RMU boards
+#
+
+TEXT_BASE = 0xfff00000
diff --git a/board/rmu/flash.c b/board/rmu/flash.c
new file mode 100755
index 0000000..0f2c327
--- /dev/null
+++ b/board/rmu/flash.c
@@ -0,0 +1,540 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	debug ("\n## Get flash bank size @ 0x%08x\n", FLASH_BASE_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE_PRELIM, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	debug  ("## Before remap:  BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+#if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND)
+	debug ("Protect redundand environment: %08lx ... %08lx\n",
+		(ulong)CFG_ENV_ADDR_REDUND,
+		(ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE - 1);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR_REDUND,
+		      CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+		      &flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	debug ("## Final Flash bank size: %08lx\n", size_b0);
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00010000;
+		info->start[2] = base + 0x00018000;
+		info->start[3] = base + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0xAAAAAAAA ;
+	addr[0x555] = 0x55555555 ;
+	addr[0xAAA] = 0x90909090 ;
+
+	value = addr[0] ;
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;		/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_LV400T & 0x00FF00FF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & 0x00FF00FF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & 0x00FF00FF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & 0x00FF00FF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/*%%% Size doubled by yooth */
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160T & 0x00FF00FF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & 0x00FF00FF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+	case (AMD_ID_LV320T & 0x00FF00FF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_LV320B & 0x00FF00FF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00010000;
+		info->start[2] = base + 0x00018000;
+		info->start[3] = base + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[4] & 1 ;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c
new file mode 100755
index 0000000..8cb03c7
--- /dev/null
+++ b/board/rmu/rmu.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 * (Initialization code at 0x36)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RMU\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80002136;	/* SDRAM bank 0 */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/* Check Bank 0 Memory Size,
+	 * 9 column mode
+	 */
+
+	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	udelay (1000);
+
+	return (size9);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/board/rmu/u-boot.lds b/board/rmu/u-boot.lds
new file mode 100755
index 0000000..049f990
--- /dev/null
+++ b/board/rmu/u-boot.lds
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+/* XXX ?
+    . = env_offset;
+*/
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/rmu/u-boot.lds.debug b/board/rmu/u-boot.lds.debug
new file mode 100755
index 0000000..894b9bd
--- /dev/null
+++ b/board/rmu/u-boot.lds.debug
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile
new file mode 100755
index 0000000..4535106
--- /dev/null
+++ b/board/rpxsuper/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= rpxsuper.o flash.o mii_phy.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/rpxsuper/config.mk b/board/rpxsuper/config.mk
new file mode 100755
index 0000000..4b8c5d3
--- /dev/null
+++ b/board/rpxsuper/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MBX8xx boards
+#
+
+TEXT_BASE = 0x80F00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c
new file mode 100755
index 0000000..d80e778
--- /dev/null
+++ b/board/rpxsuper/flash.c
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AMD 29F080B devices
+ * Added support for 64bit and AMD 29DL323B
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/io.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#define RD_SWP32(x) in_le32((volatile u32*)x)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    unsigned long size;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* for now, only support the 4 MB Flash SIMM */
+    size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]);
+
+    /*
+     * protect monitor and environment sectors
+     */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_MONITOR_BASE,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_ENV_ADDR,
+		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+
+    return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+    case (AMD_MANUFACT & FLASH_VENDMASK):
+	printf ("AMD ");
+	break;
+    case (FUJ_MANUFACT & FLASH_VENDMASK):
+	printf ("FUJITSU ");
+	break;
+    case (SST_MANUFACT & FLASH_VENDMASK):
+	printf ("SST ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case (AMD_ID_DL323B & FLASH_TYPEMASK):
+	printf("AM29DL323B (32 MBit)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+	    info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i = 0; i < info->sector_count; ++i) {
+	if ((i % 5) == 0) printf ("\n   ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "     "
+		);
+    }
+    printf ("\n");
+    return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    vu_long vendor[2], devid[2];
+    ulong base = (ulong)addr;
+
+    /* Reset and Write auto select command: read Manufacturer ID */
+    addr[0] = 0xf0f0f0f0;
+    addr[2 * 0x0555] = 0xAAAAAAAA;
+    addr[2 * 0x02AA] = 0x55555555;
+    addr[2 * 0x0555] = 0x90909090;
+    addr[1] = 0xf0f0f0f0;
+    addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+    addr[2 * 0x02AA + 1] = 0x55555555;
+    addr[2 * 0x0555 + 1] = 0x90909090;
+    udelay (1000);
+
+    vendor[0] = RD_SWP32(&addr[0]);
+    vendor[1] = RD_SWP32(&addr[1]);
+    if (vendor[0] != vendor[1] || vendor[0] != AMD_MANUFACT) {
+	info->size = 0;
+	goto out;
+    }
+
+    devid[0] = RD_SWP32(&addr[2]);
+    devid[1] = RD_SWP32(&addr[3]);
+
+    if (devid[0] == AMD_ID_DL323B) {
+	/*
+	* we have 2 Banks
+	* Bank 1 (23 Sectors): 0-7=8kbyte, 8-22=64kbyte
+	* Bank 2 (48 Sectors): 23-70=64kbyte
+	*/
+	info->flash_id     = (AMD_MANUFACT & FLASH_VENDMASK) |
+			     (AMD_ID_DL323B & FLASH_TYPEMASK);
+	info->sector_count = 71;
+	info->size         = 4 * (8 * 8 + 63 * 64) * 1024;
+    }
+    else {
+	info->size = 0;
+	goto out;
+    }
+
+    /* set up sector start address table */
+    for (i = 0; i < 8; i++) {
+	info->start[i] = base + (i * 0x8000);
+    }
+    for (i = 8; i < info->sector_count; i++) {
+	info->start[i] = base + (i * 0x40000) + 8 * 0x8000 - 8 * 0x40000;
+    }
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* read sector protection at sector address */
+	addr = (volatile unsigned long *)(info->start[i]);
+	addr[2 * 0x0555] = 0xAAAAAAAA;
+	addr[2 * 0x02AA] = 0x55555555;
+	addr[2 * 0x0555] = 0x90909090;
+	addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+	addr[2 * 0x02AA + 1] = 0x55555555;
+	addr[2 * 0x0555 + 1] = 0x90909090;
+	udelay (1000);
+	base = RD_SWP32(&addr[4]);
+	base |= RD_SWP32(&addr[5]);
+	info->protect[i] = base & 0x00010001 ? 1 : 0;
+    }
+    addr = (vu_long*)info->start[0];
+
+out:
+    /* reset command */
+    addr[0] = 0xf0f0f0f0;
+    addr[1] = 0xf0f0f0f0;
+
+    return info->size;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[2 * 0x0555] = 0xAAAAAAAA;
+    addr[2 * 0x02AA] = 0x55555555;
+    addr[2 * 0x0555] = 0x80808080;
+    addr[2 * 0x0555] = 0xAAAAAAAA;
+    addr[2 * 0x02AA] = 0x55555555;
+    addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+    addr[2 * 0x02AA + 1] = 0x55555555;
+    addr[2 * 0x0555 + 1] = 0x80808080;
+    addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+    addr[2 * 0x02AA + 1] = 0x55555555;
+    udelay (100);
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) {	/* not protected */
+	    addr = (vu_long*)(info->start[sect]);
+	    addr[0] = 0x30303030;
+	    addr[1] = 0x30303030;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+      goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_long*)(info->start[l_sect]);
+    while (	(addr[0] & 0x80808080) != 0x80808080 ||
+		(addr[1] & 0x80808080) != 0x80808080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {	/* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+    DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned long *)info->start[0];
+    addr[0] = 0xF0F0F0F0;	/* reset bank */
+    addr[1] = 0xF0F0F0F0;	/* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_long *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    if ((dest & 0x00000004) == 0) {
+	addr[2 * 0x0555] = 0xAAAAAAAA;
+	addr[2 * 0x02AA] = 0x55555555;
+	addr[2 * 0x0555] = 0xA0A0A0A0;
+    }
+    else {
+	addr[2 * 0x0555 + 1] = 0xAAAAAAAA;
+	addr[2 * 0x02AA + 1] = 0x55555555;
+	addr[2 * 0x0555 + 1] = 0xA0A0A0A0;
+    }
+
+    *((vu_long *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c
new file mode 100755
index 0000000..ef99aff
--- /dev/null
+++ b/board/rpxsuper/mii_phy.c
@@ -0,0 +1,107 @@
+#include <common.h>
+#include <mii_phy.h>
+#include "rpxsuper.h"
+
+#define MII_MDIO	0x01
+#define MII_MDCK	0x02
+#define MII_MDIR	0x04
+
+void
+mii_discover_phy(void)
+{
+    int known;
+    unsigned short phy_reg;
+    unsigned long phy_id;
+
+    known = 0;
+    printf("Discovering phy @ 0: ");
+    phy_id = mii_phy_read(2) << 16;
+    phy_id |= mii_phy_read(3);
+    if ((phy_id & 0xFFFFFC00) == 0x00137800) {
+	printf("Level One ");
+	if ((phy_id & 0x000003F0) == 0xE0) {
+	    printf("LXT971A Revision %d\n", (int)(phy_id & 0xF));
+	    known = 1;
+	}
+	else printf("unknown type\n");
+    }
+    else printf("unknown OUI = 0x%08lX\n", phy_id);
+
+    phy_reg = mii_phy_read(1);
+    if (!(phy_reg & 0x0004)) printf("Link is down\n");
+    if (!(phy_reg & 0x0020)) printf("Auto-negotiation not complete\n");
+    if (phy_reg & 0x0002) printf("Jabber condition detected\n");
+    if (phy_reg & 0x0010) printf("Remote fault condition detected \n");
+
+    if (known) {
+	phy_reg = mii_phy_read(17);
+	if (phy_reg & 0x0400)
+	    printf("Phy operating at %d MBit/s in %s-duplex mode\n",
+		phy_reg & 0x4000 ? 100 : 10,
+		phy_reg & 0x0200 ? "full" : "half");
+	else
+	    printf("bad link!!\n");
+/*
+left  off: no link, green 100MBit, yellow 10MBit
+right off: no activity, green full-duplex, yellow half-duplex
+*/
+	mii_phy_write(20, 0x0452);
+    }
+}
+
+unsigned short
+mii_phy_read(unsigned short reg)
+{
+    int i;
+    unsigned short tmp, val = 0, adr = 0;
+    t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+
+    tmp = 0x6002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    regs->bcsr4 |= MII_MDIR;
+    for (i = 0; i < 16; i++) {
+	val <<= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 | MII_MDCK);
+	if (regs->bcsr4 & MII_MDIO) val |= 1;
+	regs->bcsr4 = MII_MDIO | (regs->bcsr4 &= ~MII_MDCK);
+    }
+    return val;
+}
+
+void
+mii_phy_write(unsigned short reg, unsigned short val)
+{
+    int i;
+    unsigned short tmp, adr = 0;
+    t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+
+    tmp = 0x5002 | (adr << 7) | (reg << 2);
+    regs->bcsr4 = 0xC3;
+    for (i = 0; i < 64; i++) {
+	regs->bcsr4 ^= MII_MDCK;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (tmp & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	tmp <<= 1;
+    }
+    for (i = 0; i < 16; i++) {
+	regs->bcsr4 &= ~MII_MDCK;
+	if (val & 0x8000) regs->bcsr4 |= MII_MDIO;
+	else regs->bcsr4 &= ~MII_MDIO;
+	regs->bcsr4 |= MII_MDCK;
+	val <<= 1;
+    }
+}
diff --git a/board/rpxsuper/readme b/board/rpxsuper/readme
new file mode 100755
index 0000000..21267bd
--- /dev/null
+++ b/board/rpxsuper/readme
@@ -0,0 +1,30 @@
+Hi,
+
+so this is the port to the Embedded Planet RPX Super Board.
+
+ATTENTION
+This code is only tested on the AY-Version, which is an early release with some
+hardware bugs. The main problem is that this board uses the default Hard Reset
+Configuration Word and not the 4 bytes located at start of FLASH because at
+0xFE000000 is no FLASH. The FLASH consists out of 4 chips each 16bits wide. Be
+carefull, the bytes are swapped. So DQ0-7 is the high byte, DQ8-15 ist the low
+byte.
+
+The icache can only manually be enabled after reset.
+The FLASH and main SDRAM is working with icache enabled.
+The local SDRAM can only be used as data memory when icache is enabled.
+If U-Boot runs in local SDRAM, TFTP does not work.
+The functions in mii_phy.c are all working. Call mii_phy_discover() out of
+eth_init() and solve the linker error.
+I2C, RTC/NVRAM and PCMCIA are not working yet.
+
+TODO
+The 32MB local SDRAM is working but not shown in the startup messages of
+U-Boot. If you locate U-Boot or any other program to this area it won't run.
+Turning the ichache off does not solve this problem.
+
+As I won't buy another RPX Super there might be some little work to do for you
+getting this U-Boot port running on the final board.
+
+
+frank.morauf@salzbrenner.com
diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c
new file mode 100755
index 0000000..b4331f1
--- /dev/null
+++ b/board/rpxsuper/rpxsuper.c
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "rpxsuper.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTCA   */
+	/* PA29 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTSOC  */
+	/* PA28 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   1,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   0,   0,   0   }, /* PA6 */
+	/* PA5  */ {   1,   0,   0,   0,   0,   0   }, /* PA5 */
+	/* PA4  */ {   1,   0,   0,   0,   0,   0   }, /* PA4 */
+	/* PA3  */ {   1,   0,   0,   0,   0,   0   }, /* PA3 */
+	/* PA2  */ {   1,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* PA1 */
+	/* PA0  */ {   1,   0,   0,   0,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   1,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   1,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   1,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
+	/* PC26 */ {   1,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   1,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   1,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   1,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
+	/* PC15 */ {   1,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   1,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   1,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   1,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+	/* PC8  */ {   1,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   1,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   1,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   1,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   1,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   1,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   1,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   1,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   1,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   0,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   1,   0,   0,   0,   0,   0   }, /* PD27 */
+	/* PD26 */ {   1,   0,   0,   0,   0,   0   }, /* PD26 */
+	/* PD25 */ {   1,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   1,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   1,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   1,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   1,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   1,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   1,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   1,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD17 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   1,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   1,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   1,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   1,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   1,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   1,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   1,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   1,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   1,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Setup CS4 to enable the Board Control/Status registers.
+ * Otherwise the smcs won't work.
+*/
+int board_early_init_f (void)
+{
+    volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8260_t *memctl = &immap->im_memctl;
+    memctl->memc_br4 = CFG_BR4_PRELIM;
+    memctl->memc_or4 = CFG_OR4_PRELIM;
+    regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */
+    regs->bcsr2 = 0x20;	/* mut be written to enable writing FLASH */
+    return 0;
+}
+
+void
+reset_phy(void)
+{
+    volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+    regs->bcsr4 = 0xC3;
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+    volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+    printf ("Board: Embedded Planet RPX Super, Revision %d\n",
+	regs->bcsr0 >> 4);
+
+    return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram(int board_type)
+{
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8260_t *memctl = &immap->im_memctl;
+    volatile uchar c = 0, *ramaddr;
+    ulong psdmr, lsdmr, bcr;
+    long size = 0;
+    int i;
+
+    psdmr = CFG_PSDMR;
+    lsdmr = CFG_LSDMR;
+
+    /*
+     * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+     *
+     * "At system reset, initialization software must set up the
+     *  programmable parameters in the memory controller banks registers
+     *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+     *  system software should execute the following initialization sequence
+     *  for each SDRAM device.
+     *
+     *  1. Issue a PRECHARGE-ALL-BANKS command
+     *  2. Issue eight CBR REFRESH commands
+     *  3. Issue a MODE-SET command to initialize the mode register
+     *
+     *  The initial commands are executed by setting P/LSDMR[OP] and
+     *  accessing the SDRAM with a single-byte transaction."
+     *
+     * The appropriate BRx/ORx registers have already been set when we
+     * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+     */
+
+    size = CFG_SDRAM0_SIZE;
+    bcr = immap->im_siu_conf.sc_bcr;
+    immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM);
+
+    memctl->memc_mptpr = CFG_MPTPR;
+
+    ramaddr = (uchar *)(CFG_SDRAM0_BASE);
+    memctl->memc_psrt = CFG_PSRT;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+    for (i = 0; i < 8; i++)
+	*ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+    *ramaddr = c;
+
+    immap->im_siu_conf.sc_bcr = bcr;
+
+#ifndef CFG_RAMBOOT
+/*    size += CFG_SDRAM1_SIZE; */
+    ramaddr = (uchar *)(CFG_SDRAM1_BASE);
+    memctl->memc_lsrt = CFG_LSRT;
+
+    memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
+    *ramaddr = c;
+
+    memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
+    for (i = 0; i < 8; i++)
+	*ramaddr = c;
+
+    memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
+    *ramaddr = c;
+
+    memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+    *ramaddr = c;
+#endif
+
+    /* return total ram size */
+    return (size * 1024 * 1024);
+}
diff --git a/board/rpxsuper/rpxsuper.h b/board/rpxsuper/rpxsuper.h
new file mode 100755
index 0000000..af31060
--- /dev/null
+++ b/board/rpxsuper/rpxsuper.h
@@ -0,0 +1,25 @@
+#ifndef __RPX8260_H__
+#define __RPX8260_H__
+
+typedef struct tt_rpx_regs
+{
+    volatile unsigned char bcsr0;
+    volatile unsigned char bcsr1;
+    volatile unsigned char bcsr2;
+    volatile unsigned char bcsr3;
+    volatile unsigned char bcsr4;
+    volatile unsigned char bcsr5;
+    volatile unsigned char bcsr6;
+    volatile unsigned char bcsr7;
+    volatile unsigned char bcsr8;
+    volatile unsigned char bcsr9;
+    volatile unsigned char bcsr10;
+    volatile unsigned char bcsr11;
+    volatile unsigned char bcsr12;
+    volatile unsigned char bcsr13;
+    volatile unsigned char bcsr14;
+    volatile unsigned char bcsr15;
+} t_rpx_regs;
+typedef t_rpx_regs* tp_rpx_regs;
+
+#endif
diff --git a/board/rpxsuper/u-boot.lds b/board/rpxsuper/u-boot.lds
new file mode 100755
index 0000000..9e623d0
--- /dev/null
+++ b/board/rpxsuper/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile
new file mode 100755
index 0000000..9934787
--- /dev/null
+++ b/board/rsdproto/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= rsdproto.o flash.o
+SOBJS	:= flash_asm.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/rsdproto/config.mk b/board/rsdproto/config.mk
new file mode 100755
index 0000000..5844ec1
--- /dev/null
+++ b/board/rsdproto/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MBX8xx boards
+#
+
+TEXT_BASE = 0xff000000
+/*TEXT_BASE  = 0x00200000 */
diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c
new file mode 100755
index 0000000..5ad3218
--- /dev/null
+++ b/board/rsdproto/flash.c
@@ -0,0 +1,402 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AM290[48]0B devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* flash hardware ids */
+#define VENDOR_AMD     0x0001
+#define AMD_29DL323C_B 0x2253
+
+/* Define this to include autoselect sequence in flash_init(). Does NOT
+ * work when executing from flash itself, so this should be turned
+ * on only when debugging the RAM version.
+ */
+#undef WITH_AUTOSELECT
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if 1
+#define D(x)
+#else
+#define D(x) printf x
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static unsigned char write_ull(flash_info_t *info,
+			       unsigned long address,
+			       volatile unsigned long long data);
+
+/* from flash_asm.S */
+extern void ull_write(unsigned long long volatile *address,
+		      unsigned long long volatile *data);
+extern void ull_read(unsigned long long volatile *address,
+		     unsigned long long volatile *data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    int i;
+    ulong addr;
+
+#ifdef WITH_AUTOSELECT
+	{
+		unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH;
+		unsigned long long f_command, vendor, device;
+		/* Perform Autoselect */
+		f_command 	= 0x00AA00AA00AA00AAULL;
+		ull_write(&f_addr[0x555], &f_command);
+		f_command 	= 0x0055005500550055ULL;
+		ull_write(&f_addr[0x2AA], &f_command);
+		f_command 	= 0x0090009000900090ULL;
+		ull_write(&f_addr[0x555], &f_command);
+		ull_read(&f_addr[0], &vendor);
+		vendor &= 0xffff;
+		ull_read(&f_addr[1], &device);
+		device &= 0xffff;
+		f_command 	= 0x00F000F000F000F0ULL;
+		ull_write(&f_addr[0x555], &f_command);
+		if (vendor != VENDOR_AMD || device != AMD_29DL323C_B)
+		  return 0;
+	}
+#endif
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+	/* 1st bank: 8 x 32 KB sectors */
+	flash_info[0].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
+	flash_info[0].sector_count = 8;
+	flash_info[0].size = flash_info[0].sector_count * 32 * 1024;
+	addr = PHYS_FLASH;
+    for(i = 0; i < flash_info[0].sector_count; i++) {
+		flash_info[0].start[i] = addr;
+		addr += flash_info[0].size / flash_info[0].sector_count;
+	}
+	/* 1st bank: 63 x 256 KB sectors */
+	flash_info[1].flash_id = VENDOR_AMD << 16 | AMD_29DL323C_B;
+	flash_info[1].sector_count = 63;
+	flash_info[1].size = flash_info[1].sector_count * 256 * 1024;
+    for(i = 0; i < flash_info[1].sector_count; i++) {
+		flash_info[1].start[i] = addr;
+		addr += flash_info[1].size / flash_info[1].sector_count;
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= PHYS_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[1]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[1]);
+#endif
+
+    return flash_info[0].size + flash_info[1].size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+    }
+
+    switch (info->flash_id >> 16) {
+    case VENDOR_AMD:
+		printf ("AMD ");
+		break;
+    default:
+		printf ("Unknown Vendor ");
+		break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_29DL323C_B:
+		printf ("AM29DL323CB (32 Mbit)\n");
+		break;
+    default:
+		printf ("Unknown Chip Type\n");
+		break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+		  printf ("\n   ");
+		printf (" %08lX%s",
+				info->start[i],
+				info->protect[i] ? " (RO)" : "     "
+				);
+    }
+    printf ("\n");
+    return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    int flag, prot, sect, l_sect;
+    ulong start;
+	unsigned long long volatile *f_addr;
+	unsigned long long volatile f_command;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+    }
+    if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+    } else {
+		printf ("\n");
+    }
+
+	f_addr 	= (unsigned long long *)info->start[0];
+	f_command 	= 0x00AA00AA00AA00AAULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command 	= 0x0055005500550055ULL;
+	ull_write(&f_addr[0x2AA], &f_command);
+	f_command 	= 0x0080008000800080ULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command 	= 0x00AA00AA00AA00AAULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command 	= 0x0055005500550055ULL;
+	ull_write(&f_addr[0x2AA], &f_command);
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+    for (l_sect = -1, sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+
+			f_addr 	=
+			  (unsigned long long *)(info->start[sect]);
+			f_command 	= 0x0030003000300030ULL;
+			ull_write(f_addr, &f_command);
+			l_sect = sect;
+		}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+	start = get_timer (0);
+	do
+	{
+		if (get_timer(start) > CFG_FLASH_ERASE_TOUT)
+		{	/* write reset command, command address is unimportant */
+			/* this command turns the flash back to read mode     */
+			f_addr =
+			  (unsigned long long *)(info->start[l_sect]);
+			f_command 	= 0x00F000F000F000F0ULL;
+			ull_write(f_addr, &f_command);
+			printf (" timeout\n");
+			return 1;
+	}
+	} while(*f_addr != 0xFFFFFFFFFFFFFFFFULL);
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    unsigned long cp, wp;
+	unsigned long long data;
+    int i, l, rc;
+
+    wp = (addr & ~7);	/* get lower long long aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<8 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<8; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_ull(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+    }
+
+    /*
+     * handle long long aligned part
+     */
+    while (cnt >= 8) {
+		data = 0;
+		for (i=0; i<8; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_ull(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp  += 8;
+		cnt -= 8;
+    }
+
+    if (cnt == 0) {
+		return ERR_OK;
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+    }
+    for (; i<8; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return write_ull(info, wp, data);
+}
+
+/*---------------------------------------------------------------------------
+*
+* FUNCTION NAME:  write_ull
+*
+* DESCRIPTION:   writes 8 bytes to flash
+*
+* EXTERNAL EFFECT: nothing
+*
+* PARAMETERS:   32 bit long pointer to address, 64 bit long pointer to data
+*
+* RETURNS: 	0 if OK, 1 if timeout, 4 if parameter error
+*--------------------------------------------------------------------------*/
+
+static unsigned char write_ull(flash_info_t *info,
+							   unsigned long address,
+							   volatile unsigned long long data)
+{
+	static unsigned long long f_command;
+	static unsigned long long *f_addr;
+	ulong start;
+
+	/* address muss be 8-aligned! */
+	if (address & 0x7)
+	  return ERR_ALIGN;
+
+	f_addr 	= (unsigned long long *)info->start[0];
+	f_command 	= 0x00AA00AA00AA00AAULL;
+	ull_write(&f_addr[0x555], &f_command);
+	f_command 	= 0x0055005500550055ULL;
+	ull_write(&f_addr[0x2AA], &f_command);
+	f_command 	= 0x00A000A000A000A0ULL;
+	ull_write(&f_addr[0x555], &f_command);
+
+	f_addr 	= (unsigned long long *)address;
+	f_command 	= data;
+	ull_write(f_addr, &f_command);
+
+	start = get_timer (0);
+	do
+	{
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+		{
+			/* write reset command, command address is unimportant */
+			/* this command turns the flash back to read mode     */
+			f_addr 	= (unsigned long long *)info->start[0];
+			f_command 	= 0x00F000F000F000F0ULL;
+			ull_write(f_addr, &f_command);
+			return ERR_TIMOUT;
+		}
+	} while(*((unsigned long long *)address) != data);
+
+	return 0;
+}
diff --git a/board/rsdproto/flash_asm.S b/board/rsdproto/flash_asm.S
new file mode 100755
index 0000000..557cac0
--- /dev/null
+++ b/board/rsdproto/flash_asm.S
@@ -0,0 +1,39 @@
+/*
+ * -*- mode:c -*-
+ *
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * void ull_write(unsigned long long volatile *address,
+ *                unsigned long long volatile *data)
+ * r3 = address
+ * r4 = data
+ *
+ * void ull_read(unsigned long long volatile *address,
+ *                unsigned long long volatile *data)
+ * r3 = address
+ * r4 = data
+ *
+ * Uses the floating point unit to read and write 64 bit wide
+ * data (unsigned long long) on the 60x bus. This is necessary
+ * because all 4 flash chips use the /WE line from byte lane 0
+ *
+ * IMPORTANT: data should always be 8-aligned, otherwise an exception will
+ * occur.
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+	.globl	ull_write
+ull_write:
+	lfd		0,0(r4)
+	stfd	0,0(r3)
+	blr
+
+	.globl	ull_read
+ull_read:
+	lfd		0, 0(r3)
+	stfd	0, 0(r4)
+	blr
diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c
new file mode 100755
index 0000000..bf4fd53
--- /dev/null
+++ b/board/rsdproto/rsdproto.c
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <i2c.h>
+
+/* define to initialise the SDRAM on the local bus */
+#undef INIT_LOCAL_BUS_SDRAM
+
+/* I2C Bus adresses for PPC & Protocol board */
+#define PPC8260_I2C_ADR		0x30	/*(0)011.0000 */
+#define LM84_PPC_I2C_ADR	0x2A	/*(0)010.1010 */
+#define LM84_SHARC_I2C_ADR	0x29	/*(0)010.1001 */
+#define VIRTEX_I2C_ADR		0x25	/*(0)010.0101 */
+#define X24645_PPC_I2C_ADR	0x00	/*(0)00X.XXXX  -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */
+#define RS5C372_PPC_I2C_ADR	0x32	/*(0)011.0010  -> this adress is programmed by the manufacturer and cannot be changed !!! */
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA30 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA29 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA28 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA27 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA26 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA25 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA24 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA23 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA22 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA21 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA20 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA19 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA18 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA17 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA15 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA14 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA10 */ {   0,   0,   0,   0,   0,   0   },
+	/* PA9  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA3  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   },
+	/* PA0  */ {   0,   0,   0,   0,   0,   0   }
+    },
+
+
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   },
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC29 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC28 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC21 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC20 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   },
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* ETHRXCLK: CLK14 */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* ETHTXCLK: CLK15 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART CD/ */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDC: GP */
+	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* ETHMDIO: GP */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }
+    },
+
+
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
+	/* PD29 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD28 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD26 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   },
+	/* PD9  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD8  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   },
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+struct tm {
+	unsigned int tm_sec;
+	unsigned int tm_min;
+	unsigned int tm_hour;
+	unsigned int tm_wday;
+	unsigned int tm_mday;
+	unsigned int tm_mon;
+	unsigned int tm_year;
+};
+
+void read_RS5C372_time (struct tm *timedate)
+{
+	unsigned char buffer[8];
+
+#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
+
+	if (i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
+		timedate->tm_sec = BCD_TO_BIN (buffer[0]);
+		timedate->tm_min = BCD_TO_BIN (buffer[1]);
+		timedate->tm_hour = BCD_TO_BIN (buffer[2]);
+		timedate->tm_wday = BCD_TO_BIN (buffer[3]);
+		timedate->tm_mday = BCD_TO_BIN (buffer[4]);
+		timedate->tm_mon = BCD_TO_BIN (buffer[5]);
+		timedate->tm_year = BCD_TO_BIN (buffer[6]) + 2000;
+	} else {
+		/*printf("i2c error %02x\n", rc); */
+		memset (timedate, 0, sizeof (struct tm));
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+int read_LM84_temp (int address)
+{
+	unsigned char buffer[8];
+	/*int rc;*/
+
+	if (i2c_read (address, 0, 1, buffer, 1)) {
+		return (int) buffer[0];
+	} else {
+		/*printf("i2c error %02x\n", rc); */
+		return -42;
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	struct tm timedate;
+	unsigned int ppctemp, prottemp;
+
+	puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
+
+	/* initialise i2c */
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	read_RS5C372_time (&timedate);
+	printf ("  Time:  %02d:%02d:%02d\n",
+			timedate.tm_hour, timedate.tm_min, timedate.tm_sec);
+	printf ("  Date:  %02d-%02d-%04d\n",
+			timedate.tm_mday, timedate.tm_mon, timedate.tm_year);
+	ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR);
+	prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR);
+	printf ("  Temp:  PPC %d C, Protocol Board %d C\n",
+			ppctemp, prottemp);
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations while still
+ * running in flash
+ */
+
+int misc_init_f (void)
+{
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifdef INIT_LOCAL_BUS_SDRAM
+	volatile uchar *ramaddr8;
+#endif
+	volatile ulong *ramaddr32;
+	ulong sdmr;
+	int i;
+
+	/*
+	 * Only initialize SDRAM when running from FLASH.
+	 * When running from RAM, don't touch it.
+	 */
+	if ((ulong) initdram & 0xff000000) {
+		immap->im_siu_conf.sc_ppc_acr = 0x02;
+		immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+		immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
+		immap->im_siu_conf.sc_lcl_acr = 0x02;
+		immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
+		immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
+		/*
+		 * Program local/60x bus Transfer Error Status and Control Regs:
+		 * Disable parity errors
+		 */
+		immap->im_siu_conf.sc_tescr1 = 0x00040000;
+		immap->im_siu_conf.sc_ltescr1 = 0x00040000;
+
+		/*
+		 * Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2)
+		 *
+		 * The appropriate BRx/ORx registers have already
+		 * been set when we get here (see cpu_init_f). The
+		 * SDRAM can be accessed at the address CFG_SDRAM_BASE.
+		 */
+		memctl->memc_mptpr = 0x2000;
+		memctl->memc_mar = 0x0200;
+#ifdef INIT_LOCAL_BUS_SDRAM
+		/* initialise local bus ram
+		 *
+		 * (using the PSRMR_ definitions is NOT an error here
+		 * - the LSDMR has the same fields as the PSDMR!)
+		 */
+		memctl->memc_lsrt = 0x0b;
+		memctl->memc_lurt = 0x00;
+		ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
+		sdmr = CFG_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
+		*ramaddr = 0xff;
+		for (i = 0; i < 8; i++) {
+			memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR;
+			*ramaddr = 0xff;
+		}
+		memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
+		*ramaddr = 0xff;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_NORM;
+#endif
+		/* initialise 60x bus ram */
+		memctl->memc_psrt = 0x0b;
+		memctl->memc_purt = 0x08;
+		ramaddr32 = (ulong *) PHYS_SDRAM_60X;
+		sdmr = CFG_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
+		ramaddr32[0] = 0x00ff00ff;
+		ramaddr32[1] = 0x00ff00ff;
+		memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR;
+		for (i = 0; i < 8; i++) {
+			ramaddr32[0] = 0x00ff00ff;
+			ramaddr32[1] = 0x00ff00ff;
+		}
+		memctl->memc_psdmr = sdmr | PSDMR_OP_MRW;
+		ramaddr32[0] = 0x00ff00ff;
+		ramaddr32[1] = 0x00ff00ff;
+		memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	}
+
+	/* return the size of the 60x bus ram */
+	return PHYS_SDRAM_60X_SIZE;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations after monitor
+ * has been relocated into ram
+ */
+
+int misc_init_r (void)
+{
+	printf ("misc_init_r\n");
+	return (0);
+}
diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds
new file mode 100755
index 0000000..70fc3a5
--- /dev/null
+++ b/board/rsdproto/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    /*. = env_offset; */
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile
new file mode 100755
index 0000000..baefa4a
--- /dev/null
+++ b/board/sacsng/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= sacsng.o flash.o clkinit.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c
new file mode 100755
index 0000000..ea4c65d
--- /dev/null
+++ b/board/sacsng/clkinit.c
@@ -0,0 +1,1025 @@
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Jon Diekema <diekema@cideas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/cpm_8260.h>
+#include <configs/sacsng.h>
+
+#include "clkinit.h"
+
+int Daq64xSampling = 0;
+
+
+void Daq_BRG_Reset(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+     *brg_ptr |=  CPM_BRG_RST;
+     *brg_ptr &= ~CPM_BRG_RST;
+}
+
+void Daq_BRG_Disable(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+     *brg_ptr &= ~CPM_BRG_EN;
+}
+
+void Daq_BRG_Enable(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+     *brg_ptr |= CPM_BRG_EN;
+}
+
+uint Daq_BRG_Get_Div16(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     if (*brg_ptr & CPM_BRG_DIV16) {
+	 /* DIV16 active */
+	 return (TRUE);
+     }
+     else {
+	 /* DIV16 inactive */
+	 return (FALSE);
+     }
+}
+
+void Daq_BRG_Set_Div16(uint brg, uint div16)
+{
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     if (div16) {
+	 /* DIV16 active */
+	 *brg_ptr |=  CPM_BRG_DIV16;
+     }
+     else {
+	 /* DIV16 inactive */
+	 *brg_ptr &= ~CPM_BRG_DIV16;
+     }
+}
+
+uint Daq_BRG_Get_Count(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     uint *brg_ptr;
+     uint brg_cnt;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     /* Get the clock divider
+      *
+      * Note: A clock divider of 0 means divide by 1,
+      *       therefore we need to add 1 to the count.
+      */
+     brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
+     brg_cnt++;
+     if (*brg_ptr & CPM_BRG_DIV16) {
+	 brg_cnt *= 16;
+     }
+
+    return (brg_cnt);
+}
+
+void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
+{
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     /*
+      * Note: A clock divider of 0 means divide by 1,
+      *	 therefore we need to subtract 1 from the count.
+      */
+     if (brg_cnt > 4096) {
+	 /* Prescale = Divide by 16 */
+	 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK)   |
+	     (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
+	 *brg_ptr |= CPM_BRG_DIV16;
+     }
+     else {
+	 /* Prescale = Divide by 1 */
+	 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
+	     ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
+	 *brg_ptr &= ~CPM_BRG_DIV16;
+     }
+}
+
+uint Daq_BRG_Get_ExtClk(uint brg)
+{
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
+}
+
+char* Daq_BRG_Get_ExtClk_Description(uint brg)
+{
+     uint extc;
+
+     extc = Daq_BRG_Get_ExtClk(brg);
+
+     switch (brg + 1) {
+	 case 1:
+	 case 2:
+	 case 5:
+	 case 6: {
+	     switch (extc) {
+		 case 0: {
+		     return ("BRG_INT");
+		 }
+		 case 1: {
+		     return ("CLK3");
+		 }
+		 case 2: {
+		     return ("CLK5");
+		 }
+	     }
+	     return ("??1245??");
+	 }
+	 case 3:
+	 case 4:
+	 case 7:
+	 case 8: {
+	     switch (extc) {
+		 case 0: {
+		     return ("BRG_INT");
+		 }
+		 case 1: {
+		     return ("CLK9");
+		 }
+		 case 2: {
+		     return ("CLK15");
+		 }
+	     }
+	     return ("??3478??");
+	 }
+     }
+     return ("??9876??");
+}
+
+void Daq_BRG_Set_ExtClk(uint brg, uint extc)
+{
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     uint *brg_ptr;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg -= 4;
+     }
+     brg_ptr += brg;
+
+     *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
+		((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
+}
+
+uint Daq_BRG_Rate(uint brg)
+{
+     DECLARE_GLOBAL_DATA_PTR;
+     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     uint *brg_ptr;
+     uint brg_cnt;
+     uint brg_freq = 0;
+
+     brg_ptr = (uint *)&immr->im_brgc1;
+     brg_ptr += brg;
+     if (brg >= 5) {
+	 brg_ptr = (uint *)&immr->im_brgc5;
+	 brg_ptr += (brg - 4);
+     }
+
+    brg_cnt = Daq_BRG_Get_Count(brg);
+
+    switch (Daq_BRG_Get_ExtClk(brg)) {
+	case CPM_BRG_EXTC_CLK3:
+	case CPM_BRG_EXTC_CLK5: {
+	    brg_freq = brg_cnt;
+	    break;
+	}
+	default: {
+	    brg_freq = (uint)BRG_INT_CLK / brg_cnt;
+	}
+    }
+    return (brg_freq);
+}
+
+uint Daq_Get_SampleRate(void)
+{
+     /*
+      * Read the BRG's to return the actual sample rate.
+      */
+     return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
+}
+
+void Daq_Init_Clocks(int sample_rate, int sample_64x)
+{
+    DECLARE_GLOBAL_DATA_PTR;
+    volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
+    uint mclk_divisor; /* MCLK divisor */
+    int  flag;         /* Interrupt state */
+
+    /* Save off the clocking data */
+    Daq64xSampling = sample_64x;
+
+    /*
+     * Limit the sample rate to some sensible values.
+     */
+    if (sample_rate > MAX_64x_SAMPLE_RATE) {
+	sample_rate = MAX_64x_SAMPLE_RATE;
+    }
+    if (sample_rate < MIN_SAMPLE_RATE) {
+	sample_rate = MIN_SAMPLE_RATE;
+    }
+
+    /*
+     * Initialize the MCLK/SCLK/LRCLK baud rate generators.
+     */
+
+    /* Setup MCLK */
+    Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+
+    /* Setup SCLK */
+#   ifdef RUN_SCLK_ON_BRG_INT
+	Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+#   else
+	Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
+#   endif
+
+    /* Setup LRCLK */
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
+#   else
+	Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
+#   endif
+
+    /*
+     * Dynamically adjust MCLK based on the new sample rate.
+     */
+
+    /* Compute the divisors */
+    mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
+
+    /*
+     * Disable interrupt and save the current state
+     */
+    flag = disable_interrupts();
+
+    /* Setup MCLK */
+    Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
+
+    /* Setup SCLK */
+#   ifdef RUN_SCLK_ON_BRG_INT
+	Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
+#   else
+	Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
+#   endif
+
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	Daq_BRG_Set_Count(LRCLK_BRG,
+			  mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
+#   else
+	Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
+#   endif
+
+    /*
+     * Restore the Interrupt state
+     */
+     if (flag) {
+	 enable_interrupts();
+     }
+
+    /* Enable the clock drivers */
+    iopa->pdat &= ~SLRCLK_EN_MASK;
+}
+
+void Daq_Stop_Clocks(void)
+
+{
+#ifdef TIGHTEN_UP_BRG_TIMING
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    register uint mclk_brg;       /* MCLK  BRG value */
+    register uint sclk_brg;       /* SCLK  BRG value */
+    register uint lrclk_brg;      /* LRCLK BRG value */
+    unsigned long flag;           /* Interrupt flags */
+#endif
+
+#   ifdef TIGHTEN_UP_BRG_TIMING
+	/*
+	 * Obtain MCLK BRG reset/disabled value
+	 */
+#       if (MCLK_BRG == 0)
+	    mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 1)
+	    mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 2)
+	    mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 3)
+	    mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 4)
+	    mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 5)
+	    mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 6)
+	    mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 7)
+	    mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain SCLK BRG reset/disabled value
+	 */
+#       if (SCLK_BRG == 0)
+	    sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 1)
+	    sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 2)
+	    sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 3)
+	    sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 4)
+	    sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 5)
+	    sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 6)
+	    sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 7)
+	    sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain LRCLK BRG reset/disabled value
+	 */
+#       if (LRCLK_BRG == 0)
+	    lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Disable interrupt and save the current state
+	 */
+	flag = disable_interrupts();
+
+	/*
+	 * Set reset on MCLK BRG
+	 */
+#       if (MCLK_BRG == 0)
+	    *IM_BRGC1 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 1)
+	    *IM_BRGC2 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 2)
+	    *IM_BRGC3 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 3)
+	    *IM_BRGC4 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 4)
+	    *IM_BRGC5 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 5)
+	    *IM_BRGC6 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 6)
+	    *IM_BRGC7 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 7)
+	    *IM_BRGC8 = mclk_brg;
+#       endif
+
+	/*
+	 * Set reset on SCLK BRG
+	 */
+#       if (SCLK_BRG == 0)
+	    *IM_BRGC1 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 1)
+	    *IM_BRGC2 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 2)
+	    *IM_BRGC3 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 3)
+	    *IM_BRGC4 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 4)
+	    *IM_BRGC5 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 5)
+	    *IM_BRGC6 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 6)
+	    *IM_BRGC7 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 7)
+	    *IM_BRGC8 = sclk_brg;
+#       endif
+
+	/*
+	 * Set reset on LRCLK BRG
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = lrclk_brg;
+#       endif
+
+	/*
+	 * Clear reset on MCLK BRG
+	 */
+#       if (MCLK_BRG == 0)
+	    *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 1)
+	    *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 2)
+	    *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 3)
+	    *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 4)
+	    *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 5)
+	    *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 6)
+	    *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (MCLK_BRG == 7)
+	    *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
+#       endif
+
+	/*
+	 * Clear reset on SCLK BRG
+	 */
+#       if (SCLK_BRG == 0)
+	    *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 1)
+	    *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 2)
+	    *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 3)
+	    *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 4)
+	    *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 5)
+	    *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 6)
+	    *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (SCLK_BRG == 7)
+	    *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
+#       endif
+
+	/*
+	 * Clear reset on LRCLK BRG
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
+#       endif
+
+	/*
+	 * Restore the Interrupt state
+	 */
+	if (flag) {
+	    enable_interrupts();
+	}
+#   else
+	/*
+	 * Reset the clocks
+	 */
+	Daq_BRG_Reset(MCLK_BRG);
+	Daq_BRG_Reset(SCLK_BRG);
+	Daq_BRG_Reset(LRCLK_BRG);
+#   endif
+}
+
+void Daq_Start_Clocks(int sample_rate)
+
+{
+#ifdef TIGHTEN_UP_BRG_TIMING
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+    register uint mclk_brg;       /* MCLK  BRG value */
+    register uint sclk_brg;       /* SCLK  BRG value */
+    register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
+    register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
+    uint          lrclk_brg;      /* LRCLK BRG value */
+    unsigned long flags;          /* Interrupt flags */
+    uint          sclk_cnt;       /* SCLK count */
+    uint          delay_cnt;      /* Delay count */
+#endif
+
+#   ifdef TIGHTEN_UP_BRG_TIMING
+	/*
+	 * Obtain the enabled MCLK BRG value
+	 */
+#       if (MCLK_BRG == 0)
+	    mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 1)
+	    mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 2)
+	    mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 3)
+	    mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 4)
+	    mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 5)
+	    mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 6)
+	    mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (MCLK_BRG == 7)
+	    mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain the enabled SCLK BRG value
+	 */
+#       if (SCLK_BRG == 0)
+	    sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 1)
+	    sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 2)
+	    sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 3)
+	    sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 4)
+	    sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 5)
+	    sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 6)
+	    sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (SCLK_BRG == 7)
+	    sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+
+	/*
+	 * Obtain the enabled LRCLK BRG value
+	 */
+#       if (LRCLK_BRG == 0)
+	    lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
+#       endif
+
+	/* Save off the real LRCLK value */
+	real_lrclk_brg = lrclk_brg;
+
+	/* Obtain the current SCLK count */
+	sclk_cnt  = ((sclk_brg & 0x00001FFE) >> 1) + 1;
+
+	/* Compute the delay as a function of SCLK count */
+	delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
+	if (DaqSampleRate == 43402) {
+	  delay_cnt++;
+	}
+
+	/* Clear out the count */
+	temp_lrclk_brg = sclk_brg & ~0x00001FFE;
+
+	/* Insert the count */
+	temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) &  0x00001FFE;
+
+	/*
+	 * Disable interrupt and save the current state
+	 */
+	flag = disable_interrupts();
+
+	/*
+	 * Enable MCLK BRG
+	 */
+#       if (MCLK_BRG == 0)
+	    *IM_BRGC1 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 1)
+	    *IM_BRGC2 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 2)
+	    *IM_BRGC3 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 3)
+	    *IM_BRGC4 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 4)
+	    *IM_BRGC5 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 5)
+	    *IM_BRGC6 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 6)
+	    *IM_BRGC7 = mclk_brg;
+#       endif
+#       if (MCLK_BRG == 7)
+	    *IM_BRGC8 = mclk_brg;
+#       endif
+
+	/*
+	 * Enable SCLK BRG
+	 */
+#       if (SCLK_BRG == 0)
+	    *IM_BRGC1 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 1)
+	    *IM_BRGC2 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 2)
+	    *IM_BRGC3 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 3)
+	    *IM_BRGC4 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 4)
+	    *IM_BRGC5 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 5)
+	    *IM_BRGC6 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 6)
+	    *IM_BRGC7 = sclk_brg;
+#       endif
+#       if (SCLK_BRG == 7)
+	    *IM_BRGC8 = sclk_brg;
+#       endif
+
+	/*
+	 * Enable LRCLK BRG (1st time - temporary)
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = temp_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = temp_lrclk_brg;
+#       endif
+
+	/*
+	 * Enable LRCLK BRG (2nd time - permanent)
+	 */
+#       if (LRCLK_BRG == 0)
+	    *IM_BRGC1 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 1)
+	    *IM_BRGC2 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 2)
+	    *IM_BRGC3 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 3)
+	    *IM_BRGC4 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 4)
+	    *IM_BRGC5 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 5)
+	    *IM_BRGC6 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 6)
+	    *IM_BRGC7 = real_lrclk_brg;
+#       endif
+#       if (LRCLK_BRG == 7)
+	    *IM_BRGC8 = real_lrclk_brg;
+#       endif
+
+	/*
+	 * Restore the Interrupt state
+	 */
+	if (flag) {
+	    enable_interrupts();
+	}
+#   else
+	/*
+	 * Enable the clocks
+	 */
+	Daq_BRG_Enable(LRCLK_BRG);
+	Daq_BRG_Enable(SCLK_BRG);
+	Daq_BRG_Enable(MCLK_BRG);
+#   endif
+}
+
+void Daq_Display_Clocks(void)
+
+{
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    uint mclk_divisor; /* Detected MCLK divisor */
+    uint sclk_divisor; /* Detected SCLK divisor */
+
+    printf("\nBRG:\n");
+    if (immr->im_brgc4 != 0) {
+	printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  MCLK\n",
+	       immr->im_brgc4,
+	       (uint)&(immr->im_brgc4),
+	       Daq_BRG_Get_Count(3),
+	       Daq_BRG_Get_ExtClk(3),
+	       Daq_BRG_Get_ExtClk_Description(3));
+    }
+    if (immr->im_brgc8 != 0) {
+	printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCLK\n",
+	       immr->im_brgc8,
+	       (uint)&(immr->im_brgc8),
+	       Daq_BRG_Get_Count(7),
+	       Daq_BRG_Get_ExtClk(7),
+	       Daq_BRG_Get_ExtClk_Description(7));
+    }
+    if (immr->im_brgc6 != 0) {
+	printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  LRCLK\n",
+	       immr->im_brgc6,
+	       (uint)&(immr->im_brgc6),
+	       Daq_BRG_Get_Count(5),
+	       Daq_BRG_Get_ExtClk(5),
+	       Daq_BRG_Get_ExtClk_Description(5));
+    }
+    if (immr->im_brgc1 != 0) {
+	printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC1\n",
+	       immr->im_brgc1,
+	       (uint)&(immr->im_brgc1),
+	       Daq_BRG_Get_Count(0),
+	       Daq_BRG_Get_ExtClk(0),
+	       Daq_BRG_Get_ExtClk_Description(0));
+    }
+    if (immr->im_brgc2 != 0) {
+	printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC2\n",
+	       immr->im_brgc2,
+	       (uint)&(immr->im_brgc2),
+	       Daq_BRG_Get_Count(1),
+	       Daq_BRG_Get_ExtClk(1),
+	       Daq_BRG_Get_ExtClk_Description(1));
+    }
+    if (immr->im_brgc3 != 0) {
+	printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCC1\n",
+	       immr->im_brgc3,
+	       (uint)&(immr->im_brgc3),
+	       Daq_BRG_Get_Count(2),
+	       Daq_BRG_Get_ExtClk(2),
+	       Daq_BRG_Get_ExtClk_Description(2));
+    }
+    if (immr->im_brgc5 != 0) {
+	printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+	       immr->im_brgc5,
+	       (uint)&(immr->im_brgc5),
+	       Daq_BRG_Get_Count(4),
+	       Daq_BRG_Get_ExtClk(4),
+	       Daq_BRG_Get_ExtClk_Description(4));
+    }
+    if (immr->im_brgc7 != 0) {
+	printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
+	       immr->im_brgc7,
+	       (uint)&(immr->im_brgc7),
+	       Daq_BRG_Get_Count(6),
+	       Daq_BRG_Get_ExtClk(6),
+	       Daq_BRG_Get_ExtClk_Description(6));
+    }
+
+#   ifdef RUN_SCLK_ON_BRG_INT
+	mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
+#   else
+	mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
+#   endif
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
+#   else
+	sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
+#   endif
+
+    printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
+    printf("\tMCLK  %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
+	   Daq_BRG_Rate(MCLK_BRG),
+	   mclk_divisor,
+	   mclk_divisor * sclk_divisor);
+#   ifdef RUN_SCLK_ON_BRG_INT
+	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
+	       Daq_BRG_Rate(SCLK_BRG),
+	       sclk_divisor);
+#   else
+	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
+	       Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
+	       sclk_divisor);
+#   endif
+#   ifdef RUN_LRCLK_ON_BRG_INT
+	printf("\tLRCLK %8d Hz\n",
+	       Daq_BRG_Rate(LRCLK_BRG));
+#   else
+#       ifdef RUN_SCLK_ON_BRG_INT
+	    printf("\tLRCLK %8d Hz\n",
+		   Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
+#       else
+	    printf("\tLRCLK %8d Hz\n",
+		   Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
+#       endif
+#   endif
+    printf("\n");
+}
diff --git a/board/sacsng/clkinit.h b/board/sacsng/clkinit.h
new file mode 100755
index 0000000..011638f
--- /dev/null
+++ b/board/sacsng/clkinit.h
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Jon Diekema <diekema@cideas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE (!FALSE)
+#endif
+
+#define SLRCLK_EN_MASK  0x00040000 /* PA13 - SLRCLK_EN*     */
+
+#define MIN_SAMPLE_RATE       4000 /* Minimum sample rate */
+#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
+#define MAX_64x_SAMPLE_RATE  86805 /* Maximum  64x sample rate */
+
+#define KHZ          ((uint)1000)
+#define MHZ          ((uint)(1000 * KHZ))
+
+#define MCLK_BRG     3        /* MCLK, Master CLocK for the A/D & D/A   */
+#define SCLK_BRG     7        /* SCLK, Sample CLocK for the A/D & D/A   */
+#define LRCLK_BRG    5        /* LRCLK, L/R CLocK for the A/D & D/A     */
+			      /*   0 == BRG1 (used for SMC1)            */
+			      /*   1 == BRG2 (used for SMC2)            */
+			      /*   2 == BRG3 (used for SCC1)            */
+			      /*   3 == BRG4 (MCLK)                     */
+			      /*   4 == BRG5                            */
+			      /*   5 == BRG6 (LRCLK)                    */
+			      /*   6 == BRG7                            */
+			      /*   7 == BRG8 (SCLK)                     */
+
+#define MCLK_DIVISOR  4       /*  SCLK = MCLK / MCLK_DIVISOR */
+#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
+			      /* LRCLK = SCLK / SCLK_DIVISOR */
+
+#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing      */
+#define RUN_SCLK_ON_BRG_INT      /* Run SCLK on BRG_INT instead of MCLK   */
+				 /* The 8260 (Mask B.3) seems to have     */
+				 /* problems generating SCLK from MCLK    */
+				 /* via CLK9.                             */
+#define RUN_LRCLK_ON_BRG_INT     /* Run LRCLK on BRG_INT instead of SCLK  */
+				 /* The 8260 (Mask B.3) seems to have     */
+				 /* problems generating LRCLK from SCLK   */
+
+#define NUM_LRCLKS_TO_STABILIZE 1  /* Number of LRCLK period (sample)     */
+				   /* to wait for the clock to stabilize  */
+
+#define CPM_CLK      (gd->bd->bi_cpmfreq)
+#define DFBRG        4
+#define BRG_INT_CLK  (CPM_CLK * 2 / DFBRG)
+			      /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
+			      /* BRG = CPM * 2 / 4                */
+			      /* BRG = CPM / 2                    */
+
+#define CPM_BRG_EXTC_MASK	((uint)0x0000C000)
+#define CPM_BRG_EXTC_SHIFT      14
+
+#define CPM_BRG_DIV16_MASK	((uint)0x00000001)
+#define CPM_BRG_DIV16_SHIFT     1
+
+#define CPM_BRG_EXTC_BRGCLK     0
+#define CPM_BRG_EXTC_CLK3       1
+#define CPM_BRG_EXTC_CLK9       CPM_BRG_EXTC_CLK3
+#define CPM_BRG_EXTC_CLK5       2
+#define CPM_BRG_EXTC_CLK15      CPM_BRG_EXTC_CLK5
+
+#define IM_BRGC1 ((uint *)0xf00119f0)
+#define IM_BRGC2 ((uint *)0xf00119f4)
+#define IM_BRGC3 ((uint *)0xf00119f8)
+#define IM_BRGC4 ((uint *)0xf00119fc)
+#define IM_BRGC5 ((uint *)0xf00115f0)
+#define IM_BRGC6 ((uint *)0xf00115f4)
+#define IM_BRGC7 ((uint *)0xf00115f8)
+#define IM_BRGC8 ((uint *)0xf00115fc)
+
+/*
+ * External declarations
+ */
+
+extern int Daq64xSampling;
+
+extern void Daq_BRG_Reset(uint brg);
+extern void Daq_BRG_Run(uint brg);
+
+extern void Daq_BRG_Disable(uint brg);
+extern void Daq_BRG_Enable(uint brg);
+
+extern uint Daq_BRG_Get_Div16(uint brg);
+extern void Daq_BRG_Set_Div16(uint brg, uint div16);
+
+extern uint Daq_BRG_Get_Count(uint brg);
+extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
+
+extern uint Daq_BRG_Get_ExtClk(uint brg);
+extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
+extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
+
+extern uint Daq_BRG_Rate(uint brg);
+
+extern uint Daq_Get_SampleRate(void);
+
+extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
+extern void Daq_Stop_Clocks(void);
+extern void Daq_Start_Clocks(int sample_rate);
+extern void Daq_Display_Clocks(void);
diff --git a/board/sacsng/config.mk b/board/sacsng/config.mk
new file mode 100755
index 0000000..220b218
--- /dev/null
+++ b/board/sacsng/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# 82xx boards
+#
+
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/sacsng/flash.c b/board/sacsng/flash.c
new file mode 100755
index 0000000..52e01de
--- /dev/null
+++ b/board/sacsng/flash.c
@@ -0,0 +1,523 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <configs/sacsng.h>
+
+
+#undef  DEBUG
+
+#ifndef	CFG_ENV_ADDR
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+#ifndef CFG_ENV_SIZE
+#define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+#endif
+
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_short *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_short *)CFG_FLASH0_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_short *)CFG_FLASH1_BASE, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	/*
+	 * We only report the primary flash for U-Boot's use.
+	 */
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_short *addr, flash_info_t *info)
+{
+	short i;
+	ushort value;
+	ulong  base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAAAA;
+	addr[0x02AA] = 0x5555;
+	addr[0x0555] = 0x9090;
+	__asm__ __volatile__(" sync\n ");
+
+	value = addr[0];
+#ifdef DEBUG
+	printf("Flash manufacturer 0x%04X\n", value);
+#endif
+
+	if(value == (ushort)AMD_MANUFACT) {
+		info->flash_id = FLASH_MAN_AMD;
+	} else if (value == (ushort)FUJ_MANUFACT) {
+		info->flash_id = FLASH_MAN_FUJ;
+	} else {
+#ifdef DEBUG
+		printf("Unknown flash manufacturer 0x%04X\n", value);
+#endif
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+#ifdef DEBUG
+	printf("Flash type 0x%04X\n", value);
+#endif
+
+	if(value == (ushort)AMD_ID_LV400T) {
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;	/* => 0.5 MB		*/
+	} else if(value == (ushort)AMD_ID_LV400B) {
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;	/* => 0.5 MB		*/
+	} else if(value == (ushort)AMD_ID_LV800T) {
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MB		*/
+	} else if(value == (ushort)AMD_ID_LV800B) {
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;	/* => 1 MB		*/
+	} else if(value == (ushort)AMD_ID_LV160T) {
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MB		*/
+	} else if(value == (ushort)AMD_ID_LV160B) {
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;	/* => 2 MB		*/
+	} else if(value == (ushort)AMD_ID_LV320T) {
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;	/* => 4 MB		*/
+	} else if(value == (ushort)AMD_ID_LV320B) {
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;	/* => 4 MB		*/
+	} else {
+#ifdef DEBUG
+		printf("Unknown flash type 0x%04X\n", value);
+		info->size = CFG_FLASH_SIZE;
+#else
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+#endif
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 3) * 0x00010000);
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned short *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned short *)info->start[0];
+
+	}
+
+	addr[0] = 0xF0F0;	/* reset bank */
+	__asm__ __volatile__(" sync\n ");
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAAAA;
+	addr[0x02AA] = 0x5555;
+	addr[0x0555] = 0x8080;
+	addr[0x0555] = 0xAAAA;
+	addr[0x02AA] = 0x5555;
+	__asm__ __volatile__(" sync\n ");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_short*)(info->start[sect]);
+			addr[0] = 0x3030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_short*)(info->start[l_sect]);
+	while ((addr[0] & 0x0080) != 0x0080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			addr[0] = 0xF0F0;	/* reset bank */
+			__asm__ __volatile__(" sync\n ");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_short*)info->start[0];
+	addr[0] = 0xF0F0;	/* reset bank */
+	__asm__ __volatile__(" sync\n ");
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	ulong start;
+	int flag;
+	int j;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((*(vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* The original routine was designed to write 32 bit words to
+	 * 32 bit wide memory.	We have 16 bit wide memory so we do
+	 * two writes.	We write the LSB first at dest+2 and then the
+	 * MSB at dest (lousy big endian).
+	 */
+	dest += 2;
+	for(j = 0; j < 2; j++) {
+		addr[0x0555] = 0xAAAA;
+		addr[0x02AA] = 0x5555;
+		addr[0x0555] = 0xA0A0;
+		__asm__ __volatile__(" sync\n ");
+
+		*((vu_short *)dest) = (ushort)data;
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while (*(vu_short *)dest != (ushort)data) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+		dest -= 2;
+		data >>= 16;
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/sacsng/ioconfig.h b/board/sacsng/ioconfig.h
new file mode 100755
index 0000000..be1ce7c
--- /dev/null
+++ b/board/sacsng/ioconfig.h
@@ -0,0 +1,217 @@
+/*
+ * I/O Port configuration table
+ *
+ * If conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#ifdef SKIP
+#undef SKIP
+#endif
+
+#ifdef CONF
+#undef CONF
+#endif
+
+#ifdef DIN
+#undef DIN
+#endif
+
+#ifdef DOUT
+#undef DOUT
+#endif
+
+#ifdef GPIO
+#undef GPIO
+#endif
+
+#ifdef SPEC
+#undef SPEC
+#endif
+
+#ifdef ACTV
+#undef ACTV
+#endif
+
+#ifdef OPEN
+#undef OPEN
+#endif
+
+#define SKIP 0  /* SKIP over this port */
+#define CONF 1  /* CONFiguration the port */
+
+#define DIN  0  /* PDIRx 0: Direction IN  */
+#define DOUT 1  /* PDIRx 1: Direction OUT */
+
+#define GPIO 0  /* PPARx 0: General Purpose I/O */
+#define SPEC 1  /* PPARx 1: dedicated to a peripheral function, */
+		/*          i.e. the port has a SPECial use. */
+
+#define ACTV 0  /* PODRx 0: ACTiVely driven as an output */
+#define OPEN 1  /* PODRx 1: OPEN-drain driver */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	     conf  ppar  psor  pdir  podr  pdat */
+	/* PA31 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS8*        */
+	/* PA30 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS7*        */
+	/* PA29 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS6*        */
+	/* PA28 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS5*        */
+	/* PA27 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS4*        */
+	/* PA26 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS3*        */
+	/* PA25 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS2*        */
+	/* PA24 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS1*        */
+	/* PA23 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* ODIS_EN*       */
+	/* PA22 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* STLED2_EN*     */
+	/* PA21 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* STLED1_EN*     */
+	/* PA20 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PLED3_EN*      */
+	/* PA19 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PLED2_EN*      */
+	/* PA18 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* PLED1_EN*      */
+	/* PA17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PA16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* DAC_RST*       */
+	/* PA15 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* CH34SDATA_PU   */
+	/* PA14 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* CH12SDATA_PU   */
+	/* PA13 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SLRCLK_EN*     */
+	/* PA12 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4ACDC*    */
+	/* PA11 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4TEDS*    */
+	/* PA10 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4XTDS*    */
+	/* PA9  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3ACDC*    */
+	/* PA8  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3TEDS*    */
+	/* PA7  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3XTDS*    */
+	/* PA6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2ACDC*    */
+	/* PA5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2TEDS*    */
+	/* PA4  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2XTDS*    */
+	/* PA3  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PA2  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_1ACDC*    */
+	/* PA1  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_1TEDS*    */
+	/* PA0  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }  /* MTRX_1XTDS*    */
+    },
+
+    /* Port B configuration */
+    {	/*	     conf  ppar  psor  pdir  podr  pdat */
+	/* PB31 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TX_ER */
+	/* PB30 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RX_DV */
+	/* PB29 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* FCC2 MII_TX_EN */
+	/* PB28 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RX_ER */
+	/* PB27 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_COL   */
+	/* PB26 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_CRS   */
+	/* PB25 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD3  */
+	/* PB24 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD2  */
+	/* PB23 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD1  */
+	/* PB22 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD0  */
+	/* PB21 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD0  */
+	/* PB20 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD1  */
+	/* PB19 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD2  */
+	/* PB18 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD3  */
+	/* PB17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB15 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB14 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RXDC1,   BSDATA_ADC12 */
+	/* PB13 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB12 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RSYNCC1, LRCLK  */
+	/* PB11 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1TXDD1,   RSDATA_DAC12 */
+	/* PB10 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RXDD1,   BSDATA_ADC34 */
+	/* PB9  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB8  */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RSYNCD1, LRCLK  */
+	/* PB7  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PB6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* XCITE_SHDN     */
+	/* PB5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* TRIGGER        */
+	/* PB4  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* ARM            */
+	/* PB3  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PB2  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PB1  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PB0  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar  psor  pdir  podr  pdat */
+	/* PC31 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC30 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC29 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK3,  MCLK    */
+	/* PC28 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* TOUT2*         */
+#ifdef QQQ
+	/* PC28 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TOUT2*         */
+#endif
+	/* PC27 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK5,  SCLK    */
+	/* PC26 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC25 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK7,  SCLK    */
+	/* PC24 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC23 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK9,  MCLK    */
+	/* PC22 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC21 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* BRGO6 (LRCLK)  */
+	/* PC20 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC19 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK13, MII_RXCLK  */
+	/* PC18 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK14, MII_TXCLK  */
+	/* PC17 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* BRGO8 (SCLK)   */
+	/* PC16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC15 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* SMC2_TX        */
+	/* PC14 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC13 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC12 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB3      */
+	/* PC11 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC10 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* TDM_STRB4      */
+	/* PC9  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN3      */
+	/* PC8  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN2      */
+	/* PC7  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN1      */
+	/* PC6  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PC5  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BTST_IN2*      */
+	/* PC4  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BTST_IN1*      */
+	/* PC3  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* MUSH_STAT      */
+	/* PC2  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* OUTDRV_STAT    */
+	/* PC1  */ { CONF, GPIO,   0,  DOUT, OPEN,   1   }, /* PHY_MDIO       */
+	/* PC0  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PHY_MDC        */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar  psor  pdir  podr  pdat */
+	/* PD31 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* SCC1_RX        */
+	/* PD30 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SCC1_TX        */
+	/* PD29 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD28 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD27 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD26 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD25 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD24 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD23 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD22 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD21 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD20 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SPI_ADC_CS*    */
+	/* PD19 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SPI_DAC_CS*    */
+#if defined(CONFIG_SOFT_SPI)
+	/* PD18 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* SPI_CLK        */
+	/* PD17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* SPI_MOSI       */
+	/* PD16 */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* SPI_MISO       */
+#else
+	/* PD18 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SPI_CLK        */
+	/* PD17 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SPI_MOSI       */
+	/* PD16 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* SPI_MISO       */
+#endif
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ { CONF, GPIO,   0,  DOUT, OPEN,   1   }, /* I2C_SDA        */
+	/* PD14 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* I2C_SCL        */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ { CONF, SPEC,   1,  DIN,  OPEN,   0   }, /* I2C_SDA        */
+	/* PD14 */ { CONF, SPEC,   1,  DIN,  OPEN,   0   }, /* I2C_SCL        */
+#else /* normal I/O port pins */
+	/* PD15 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* I2C_SDA        */
+	/* PD14 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* I2C_SCL        */
+#endif
+#endif
+	/* PD13 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB1      */
+	/* PD12 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB2      */
+	/* PD11 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
+	/* PD10 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* BRGO4 (MCLK)   */
+	/* PD9  */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* SMC1_TX        */
+	/* PD8  */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* SMC1_RX        */
+	/* PD7  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
+	/* PD6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
+	/* PD5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
+	/* PD4  */ { CONF, SPEC,   1,  DOUT, ACTV,   1   }, /* SMC2_RX        */
+	/* PD3  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PD2  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PD1  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
+	/* PD0  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }  /* pin doesn't exist */
+    }
+};
diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c
new file mode 100755
index 0000000..e50b747
--- /dev/null
+++ b/board/sacsng/sacsng.c
@@ -0,0 +1,890 @@
+/*
+ * (C) Copyright 2002
+ * Custom IDEAS, Inc. <www.cideas.com>
+ * Gerald Van Baren <vanbaren@cideas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/u-boot.h>
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <i2c.h>
+#include <spi.h>
+#include <command.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+extern void eth_loopback_test(void);
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+#include "clkinit.h"
+#include "ioconfig.h" /* I/O configuration table */
+
+/*
+ * PBI Page Based Interleaving
+ *   PSDMR_PBI page based interleaving
+ *   0         bank based interleaving
+ * External Address Multiplexing (EAMUX) adds a clock to address cycles
+ *   (this can help with marginal board layouts)
+ *   PSDMR_EAMUX  adds a clock
+ *   0            no extra clock
+ * Buffer Command (BUFCMD) adds a clock to command cycles.
+ *   PSDMR_BUFCMD adds a clock
+ *   0            no extra clock
+ */
+#define CONFIG_PBI		PSDMR_PBI
+#define PESSIMISTIC_SDRAM	0
+#define EAMUX			0	/* EST requires EAMUX */
+#define BUFCMD			0
+
+/*
+ * ADC/DAC Defines:
+ */
+#define INITIAL_SAMPLE_RATE 10016     /* Initial Daq sample rate */
+#define INITIAL_RIGHT_JUST  0         /* Initial DAC right justification */
+#define INITIAL_MCLK_DIVIDE 0         /* Initial MCLK Divide */
+#define INITIAL_SAMPLE_64X  1         /* Initial  64x clocking mode */
+#define INITIAL_SAMPLE_128X 0         /* Initial 128x clocking mode */
+
+/*
+ * ADC Defines:
+ */
+#define I2C_ADC_1_ADDR 0x0E           /* I2C Address of the ADC #1 */
+#define I2C_ADC_2_ADDR 0x0F           /* I2C Address of the ADC #2 */
+
+#define ADC_SDATA1_MASK 0x00020000    /* PA14 - CH12SDATA_PU   */
+#define ADC_SDATA2_MASK 0x00010000    /* PA15 - CH34SDATA_PU   */
+
+#define ADC_VREF_CAP   100            /* VREF capacitor in uF */
+#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
+#define ADC_SDATA_DELAY    100        /* ADC SDATA release delay in usec */
+#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
+				      /* Wait at least 4100 LRCLK's */
+
+#define ADC_REG1_FRAME_START    0x80  /* Frame start */
+#define ADC_REG1_GROUND_CAL     0x40  /* Ground calibration enable */
+#define ADC_REG1_ANA_MOD_PDOWN  0x20  /* Analog modulator section in power down */
+#define ADC_REG1_DIG_MOD_PDOWN  0x10  /* Digital modulator section in power down */
+
+#define ADC_REG2_128x           0x80  /* Oversample at 128x */
+#define ADC_REG2_CAL            0x40  /* System calibration enable */
+#define ADC_REG2_CHANGE_SIGN    0x20  /* Change sign enable */
+#define ADC_REG2_LR_DISABLE     0x10  /* Left/Right output disable */
+#define ADC_REG2_HIGH_PASS_DIS  0x08  /* High pass filter disable */
+#define ADC_REG2_SLAVE_MODE     0x04  /* Slave mode */
+#define ADC_REG2_DFS            0x02  /* Digital format select */
+#define ADC_REG2_MUTE           0x01  /* Mute */
+
+#define ADC_REG7_ADDR_ENABLE    0x80  /* Address enable */
+#define ADC_REG7_PEAK_ENABLE    0x40  /* Peak enable */
+#define ADC_REG7_PEAK_UPDATE    0x20  /* Peak update */
+#define ADC_REG7_PEAK_FORMAT    0x10  /* Peak display format */
+#define ADC_REG7_DIG_FILT_PDOWN 0x04  /* Digital filter power down enable */
+#define ADC_REG7_FIR2_IN_EN     0x02  /* External FIR2 input enable */
+#define ADC_REG7_PSYCHO_EN      0x01  /* External pyscho filter input enable */
+
+/*
+ * DAC Defines:
+ */
+
+#define I2C_DAC_ADDR 0x11             /* I2C Address of the DAC */
+
+#define DAC_RST_MASK 0x00008000       /* PA16 - DAC_RST*  */
+#define DAC_RESET_DELAY    100        /* DAC reset delay in usec */
+#define DAC_INITIAL_DELAY 5000        /* DAC initialization delay in usec */
+
+#define DAC_REG1_AMUTE   0x80         /* Auto-mute */
+
+#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4) /* Fmt 0: Left justified 24 bit  */
+#define DAC_REG1_I2S_24_BIT       (1 << 4) /* Fmt 1: I2S up to 24 bit       */
+#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4) /* Fmt 2: Right justified 16 bit */
+#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4) /* Fmt 3: Right justified 24 bit */
+#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4) /* Fmt 4: Right justified 20 bit */
+#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4) /* Fmt 5: Right justified 18 bit */
+
+#define DAC_REG1_DEM_NO           (0 << 2) /* No      De-emphasis  */
+#define DAC_REG1_DEM_44KHZ        (1 << 2) /* 44.1KHz De-emphasis  */
+#define DAC_REG1_DEM_48KHZ        (2 << 2) /* 48KHz   De-emphasis  */
+#define DAC_REG1_DEM_32KHZ        (3 << 2) /* 32KHz   De-emphasis  */
+
+#define DAC_REG1_SINGLE 0             /*   4- 50KHz sample rate  */
+#define DAC_REG1_DOUBLE 1             /*  50-100KHz sample rate  */
+#define DAC_REG1_QUAD   2             /* 100-200KHz sample rate  */
+#define DAC_REG1_DSD    3             /* Direct Stream Data, DSD */
+
+#define DAC_REG5_INVERT_A   0x80      /* Invert channel A */
+#define DAC_REG5_INVERT_B   0x40      /* Invert channel B */
+#define DAC_REG5_I2C_MODE   0x20      /* Control port (I2C) mode */
+#define DAC_REG5_POWER_DOWN 0x10      /* Power down mode */
+#define DAC_REG5_MUTEC_A_B  0x08      /* Mutec A=B */
+#define DAC_REG5_FREEZE     0x04      /* Freeze */
+#define DAC_REG5_MCLK_DIV   0x02      /* MCLK divide by 2 */
+#define DAC_REG5_RESERVED   0x01      /* Reserved */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+    printf ("SACSng\n");
+
+    return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram(int board_type)
+{
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8260_t *memctl = &immap->im_memctl;
+    volatile uchar c = 0;
+    volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
+    uint  psdmr = CFG_PSDMR;
+    int   i;
+    uint   psrt = 14;					/* for no SPD */
+    uint   chipselects = 1;				/* for no SPD */
+    uint   sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024;	/* for no SPD */
+    uint   or = CFG_OR2_PRELIM;				/* for no SPD */
+#ifdef SDRAM_SPD_ADDR
+    uint   data_width;
+    uint   rows;
+    uint   banks;
+    uint   cols;
+    uint   caslatency;
+    uint   width;
+    uint   rowst;
+    uint   sdam;
+    uint   bsma;
+    uint   sda10;
+    u_char spd_size;
+    u_char data;
+    u_char cksum;
+    int    j;
+#endif
+
+#ifdef SDRAM_SPD_ADDR
+    /* Keep the compiler from complaining about potentially uninitialized vars */
+    data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
+
+    /*
+     * Read the SDRAM SPD EEPROM via I2C.
+     */
+    i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
+    spd_size = data;
+    cksum    = data;
+    for(j = 1; j < 64; j++) {	/* read only the checksummed bytes */
+	/* note: the I2C address autoincrements when alen == 0 */
+	i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
+	     if(j ==  5) chipselects = data & 0x0F;
+	else if(j ==  6) data_width  = data;
+	else if(j ==  7) data_width |= data << 8;
+	else if(j ==  3) rows        = data & 0x0F;
+	else if(j ==  4) cols        = data & 0x0F;
+	else if(j == 12) {
+	    /*
+	     * Refresh rate: this assumes the prescaler is set to
+	     * approximately 1uSec per tick.
+	     */
+	    switch(data & 0x7F) {
+		default:
+		case 0:  psrt =  14 ; /*  15.625uS */  break;
+		case 1:  psrt =   2;  /*   3.9uS   */  break;
+		case 2:  psrt =   6;  /*   7.8uS   */  break;
+		case 3:  psrt =  29;  /*  31.3uS   */  break;
+		case 4:  psrt =  60;  /*  62.5uS   */  break;
+		case 5:  psrt = 120;  /* 125uS     */  break;
+	    }
+	}
+	else if(j == 17) banks       = data;
+	else if(j == 18) {
+	    caslatency = 3; /* default CL */
+#if(PESSIMISTIC_SDRAM)
+		 if((data & 0x04) != 0) caslatency = 3;
+	    else if((data & 0x02) != 0) caslatency = 2;
+	    else if((data & 0x01) != 0) caslatency = 1;
+#else
+		 if((data & 0x01) != 0) caslatency = 1;
+	    else if((data & 0x02) != 0) caslatency = 2;
+	    else if((data & 0x04) != 0) caslatency = 3;
+#endif
+	    else {
+		printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
+			data);
+	    }
+	}
+	else if(j == 63) {
+	    if(data != cksum) {
+		printf ("WARNING: Configuration data checksum failure:"
+			" is 0x%02x, calculated 0x%02x\n",
+			data, cksum);
+	    }
+	}
+	cksum += data;
+    }
+
+    /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
+    if(caslatency < 2) {
+	printf("WARNING: CL was %d, forcing to 2\n", caslatency);
+	caslatency = 2;
+    }
+    if(rows > 14) {
+	printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
+	rows = 14;
+    }
+    if(cols > 11) {
+	printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
+	cols = 11;
+    }
+
+    if((data_width != 64) && (data_width != 72))
+    {
+	printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
+	    data_width);
+    }
+    width = 3;		/* 2^3 = 8 bytes = 64 bits wide */
+    /*
+     * Convert banks into log2(banks)
+     */
+    if     (banks == 2)	banks = 1;
+    else if(banks == 4)	banks = 2;
+    else if(banks == 8)	banks = 3;
+
+    sdram_size = 1 << (rows + cols + banks + width);
+
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    rowst = ((32 - 6) - (rows + cols + width)) * 2;
+#else
+    rowst = 32 - (rows + banks + cols + width);
+#endif
+
+    or = ~(sdram_size - 1)    |	/* SDAM address mask	*/
+	  ((banks-1) << 13)   |	/* banks per device	*/
+	  (rowst << 9)        |	/* rowst		*/
+	  ((rows - 9) << 6);	/* numr			*/
+
+    memctl->memc_or2 = or;
+
+    /*
+     * SDAM specifies the number of columns that are multiplexed
+     * (reference AN2165/D), defined to be (columns - 6) for page
+     * interleave, (columns - 8) for bank interleave.
+     *
+     * BSMA is 14 - max(rows, cols).  The bank select lines come
+     * into play above the highest "address" line going into the
+     * the SDRAM.
+     */
+#if(CONFIG_PBI == 0)	/* bank-based interleaving */
+    sdam = cols - 8;
+    bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+    sda10 = sdam + 2;
+#else
+    sdam = cols - 6;
+    bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
+    sda10 = sdam;
+#endif
+#if(PESSIMISTIC_SDRAM)
+    psdmr = (CONFIG_PBI              |\
+	     PSDMR_RFEN              |\
+	     PSDMR_RFRC_16_CLK       |\
+	     PSDMR_PRETOACT_8W       |\
+	     PSDMR_ACTTORW_8W        |\
+	     PSDMR_WRC_4C            |\
+	     PSDMR_EAMUX             |\
+	     PSDMR_BUFCMD)           |\
+	     caslatency              |\
+	     ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */ \
+	     (sdam << 24)            |\
+	     (bsma << 21)            |\
+	     (sda10 << 18);
+#else
+    psdmr = (CONFIG_PBI              |\
+	     PSDMR_RFEN              |\
+	     PSDMR_RFRC_7_CLK        |\
+	     PSDMR_PRETOACT_3W       |	/* 1 for 7E parts (fast PC-133) */ \
+	     PSDMR_ACTTORW_2W        |	/* 1 for 7E parts (fast PC-133) */ \
+	     PSDMR_WRC_1C            |	/* 1 clock + 7nSec */
+	     EAMUX                   |\
+	     BUFCMD)                 |\
+	     caslatency              |\
+	     ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */ \
+	     (sdam << 24)            |\
+	     (bsma << 21)            |\
+	     (sda10 << 18);
+#endif
+#endif
+
+    /*
+     * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+     *
+     * "At system reset, initialization software must set up the
+     *  programmable parameters in the memory controller banks registers
+     *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+     *  system software should execute the following initialization sequence
+     *  for each SDRAM device.
+     *
+     *  1. Issue a PRECHARGE-ALL-BANKS command
+     *  2. Issue eight CBR REFRESH commands
+     *  3. Issue a MODE-SET command to initialize the mode register
+     *
+     * Quote from Micron MT48LC8M16A2 data sheet:
+     *
+     *  "...the SDRAM requires a 100uS delay prior to issuing any
+     *  command other than a COMMAND INHIBIT or NOP.  Starting at some
+     *  point during this 100uS period and continuing at least through
+     *  the end of this period, COMMAND INHIBIT or NOP commands should
+     *  be applied."
+     *
+     *  "Once the 100uS delay has been satisfied with at least one COMMAND
+     *  INHIBIT or NOP command having been applied, a /PRECHARGE command/
+     *  should be applied.  All banks must then be precharged, thereby
+     *  placing the device in the all banks idle state."
+     *
+     *  "Once in the idle state, /two/ AUTO REFRESH cycles must be
+     *  performed.  After the AUTO REFRESH cycles are complete, the
+     *  SDRAM is ready for mode register programming."
+     *
+     *  (/emphasis/ mine, gvb)
+     *
+     *  The way I interpret this, Micron start up sequence is:
+     *  1. Issue a PRECHARGE-BANK command (initial precharge)
+     *  2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
+     *  3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
+     *  4. Issue a MODE-SET command to initialize the mode register
+     *
+     *  --------
+     *
+     *  The initial commands are executed by setting P/LSDMR[OP] and
+     *  accessing the SDRAM with a single-byte transaction."
+     *
+     * The appropriate BRx/ORx registers have already been set when we
+     * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+     */
+
+    memctl->memc_mptpr = CFG_MPTPR;
+    memctl->memc_psrt  = psrt;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+    for (i = 0; i < 8; i++)
+	*ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+    *ramaddr = c;
+
+    memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+    *ramaddr = c;
+
+    /*
+     * Do it a second time for the second set of chips if the DIMM has
+     * two chip selects (double sided).
+     */
+    if(chipselects > 1) {
+	ramaddr += sdram_size;
+
+	memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
+	memctl->memc_or3 = or;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+	    *ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+    }
+
+    /* return total ram size */
+    return (sdram_size * chipselects);
+}
+
+/*-----------------------------------------------------------------------
+ * Board Control Functions
+ */
+void board_poweroff (void)
+{
+    while (1);		/* hang forever */
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r(void)
+{
+    /*
+     * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
+     */
+    volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
+    volatile ioport_t *iop  = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+
+    int  reg;          /* I2C register value */
+    char *ep;          /* Environment pointer */
+    char str_buf[12] ; /* sprintf output buffer */
+    int  sample_rate;  /* ADC/DAC sample rate */
+    int  sample_64x;   /* Use  64/4 clocking for the ADC/DAC */
+    int  sample_128x;  /* Use 128/4 clocking for the ADC/DAC */
+    int  right_just;   /* Is the data to the DAC right justified? */
+    int  mclk_divide;  /* MCLK Divide */
+    int  quiet;        /* Quiet or minimal output mode */
+
+    quiet = 0;
+    if ((ep = getenv("quiet")) != NULL) {
+	quiet = simple_strtol(ep, NULL, 10);
+    }
+    else {
+	setenv("quiet", "0");
+    }
+
+    /*
+     * SACSng custom initialization:
+     *    Start the ADC and DAC clocks, since the Crystal parts do not
+     *    work on the I2C bus until the clocks are running.
+     */
+
+    sample_rate = INITIAL_SAMPLE_RATE;
+    if ((ep = getenv("DaqSampleRate")) != NULL) {
+	sample_rate = simple_strtol(ep, NULL, 10);
+    }
+
+    sample_64x  = INITIAL_SAMPLE_64X;
+    sample_128x = INITIAL_SAMPLE_128X;
+    if ((ep = getenv("Daq64xSampling")) != NULL) {
+	sample_64x = simple_strtol(ep, NULL, 10);
+	if (sample_64x) {
+	    sample_128x = 0;
+	}
+	else {
+	    sample_128x = 1;
+	}
+    }
+    else {
+	if ((ep = getenv("Daq128xSampling")) != NULL) {
+	    sample_128x = simple_strtol(ep, NULL, 10);
+	    if (sample_128x) {
+		sample_64x = 0;
+	    }
+	    else {
+		sample_64x = 1;
+	    }
+	}
+    }
+
+    /*
+     * Stop the clocks and wait for at least 1 LRCLK period
+     * to make sure the clocking has really stopped.
+     */
+    Daq_Stop_Clocks();
+    udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+    /*
+     * Initialize the clocks with the new rates
+     */
+    Daq_Init_Clocks(sample_rate, sample_64x);
+    sample_rate = Daq_Get_SampleRate();
+
+    /*
+     * Start the clocks and wait for at least 1 LRCLK period
+     * to make sure the clocking has become stable.
+     */
+    Daq_Start_Clocks(sample_rate);
+    udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+    sprintf(str_buf, "%d", sample_rate);
+    setenv("DaqSampleRate", str_buf);
+
+    if (sample_64x) {
+	setenv("Daq64xSampling",  "1");
+	setenv("Daq128xSampling", NULL);
+    }
+    else {
+	setenv("Daq64xSampling",  NULL);
+	setenv("Daq128xSampling", "1");
+    }
+
+    /*
+     * Display the ADC/DAC clocking information
+     */
+    if (!quiet) {
+	Daq_Display_Clocks();
+    }
+
+    /*
+     * Determine the DAC data justification
+     */
+
+    right_just = INITIAL_RIGHT_JUST;
+    if ((ep = getenv("DaqDACRightJustified")) != NULL) {
+	right_just = simple_strtol(ep, NULL, 10);
+    }
+
+    sprintf(str_buf, "%d", right_just);
+    setenv("DaqDACRightJustified", str_buf);
+
+    /*
+     * Determine the DAC MCLK Divide
+     */
+
+    mclk_divide = INITIAL_MCLK_DIVIDE;
+    if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
+	mclk_divide = simple_strtol(ep, NULL, 10);
+    }
+
+    sprintf(str_buf, "%d", mclk_divide);
+    setenv("DaqDACMClockDivide", str_buf);
+
+    /*
+     * Initializing the I2C address in the Crystal A/Ds:
+     *
+     * 1) Wait for VREF cap to settle (10uSec per uF)
+     * 2) Release pullup on SDATA
+     * 3) Write the I2C address to register 6
+     * 4) Enable address matching by setting the MSB in register 7
+     */
+
+    if (!quiet) {
+	printf("Initializing the ADC...\n");
+    }
+    udelay(ADC_INITIAL_DELAY);		/* 10uSec per uF of VREF cap */
+
+    iopa->pdat &= ~ADC_SDATA1_MASK;     /* release SDATA1 */
+    udelay(ADC_SDATA_DELAY);		/* arbitrary settling time */
+
+    i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR);	/* set address */
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x07,         /* turn on ADDREN */
+		  ADC_REG7_ADDR_ENABLE);
+
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
+		  (sample_64x ? 0 : ADC_REG2_128x) |
+		  ADC_REG2_HIGH_PASS_DIS |
+		  ADC_REG2_SLAVE_MODE);
+
+    reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
+    if(reg != I2C_ADC_1_ADDR)
+	printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
+	       reg, I2C_ADC_1_ADDR);
+
+    iopa->pdat &= ~ADC_SDATA2_MASK;	/* release SDATA2 */
+    udelay(ADC_SDATA_DELAY);		/* arbitrary settling time */
+
+    i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);	/* set address (do not set ADDREN yet) */
+
+    i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
+		  (sample_64x ? 0 : ADC_REG2_128x) |
+		  ADC_REG2_HIGH_PASS_DIS |
+		  ADC_REG2_SLAVE_MODE);
+
+    reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
+    if(reg != I2C_ADC_2_ADDR)
+	printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
+	       reg, I2C_ADC_2_ADDR);
+
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
+		  ADC_REG1_FRAME_START |
+		  ADC_REG1_GROUND_CAL);
+
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
+		  (sample_64x ? 0 : ADC_REG2_128x) |
+		  ADC_REG2_CAL |
+		  ADC_REG2_HIGH_PASS_DIS |
+		  ADC_REG2_SLAVE_MODE);
+
+    udelay(ADC_CAL_DELAY);		/* a minimum of 4100 LRCLKs */
+    i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00);	/* remove GNDCAL */
+
+    /*
+     * Now that we have synchronized the ADC's, enable address
+     * selection on the second ADC as well as the first.
+     */
+    i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
+
+    /*
+     * Initialize the Crystal DAC
+     *
+     * Two of the config lines are used for I2C so we have to set them
+     * to the proper initialization state without inadvertantly
+     * sending an I2C "start" sequence.  When we bring the I2C back to
+     * the normal state, we send an I2C "stop" sequence.
+     */
+    if (!quiet) {
+	printf("Initializing the DAC...\n");
+    }
+
+    /*
+     * Bring the I2C clock and data lines low for initialization
+     */
+    I2C_SCL(0);
+    I2C_DELAY;
+    I2C_SDA(0);
+    I2C_ACTIVE;
+    I2C_DELAY;
+
+    /* Reset the DAC */
+    iopa->pdat &= ~DAC_RST_MASK;
+    udelay(DAC_RESET_DELAY);
+
+    /* Release the DAC reset */
+    iopa->pdat |=  DAC_RST_MASK;
+    udelay(DAC_INITIAL_DELAY);
+
+    /*
+     * Cause the DAC to:
+     *     Enable control port (I2C mode)
+     *     Going into power down
+     */
+    i2c_reg_write(I2C_DAC_ADDR, 0x05,
+		  DAC_REG5_I2C_MODE |
+		  DAC_REG5_POWER_DOWN);
+
+    /*
+     * Cause the DAC to:
+     *     Enable control port (I2C mode)
+     *     Going into power down
+     *         . MCLK divide by 1
+     *         . MCLK divide by 2
+     */
+    i2c_reg_write(I2C_DAC_ADDR, 0x05,
+		  DAC_REG5_I2C_MODE |
+		  DAC_REG5_POWER_DOWN |
+		  (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+    /*
+     * Cause the DAC to:
+     *     Auto-mute disabled
+     *         . Format 0, left  justified 24 bits
+     *         . Format 3, right justified 24 bits
+     *     No de-emphasis
+     *         . Single speed mode
+     *         . Double speed mode
+     */
+    i2c_reg_write(I2C_DAC_ADDR, 0x01,
+		  (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
+				DAC_REG1_LEFT_JUST_24_BIT) |
+		  DAC_REG1_DEM_NO |
+		  (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
+
+    sprintf(str_buf, "%d",
+	    sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
+    setenv("DaqDACFunctionalMode", str_buf);
+
+    /*
+     * Cause the DAC to:
+     *     Enable control port (I2C mode)
+     *     Remove power down
+     *         . MCLK divide by 1
+     *         . MCLK divide by 2
+     */
+    i2c_reg_write(I2C_DAC_ADDR, 0x05,
+		  DAC_REG5_I2C_MODE |
+		  (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
+
+    /*
+     * Create a I2C stop condition:
+     *     low->high on data while clock is high.
+     */
+    I2C_SCL(1);
+    I2C_DELAY;
+    I2C_SDA(1);
+    I2C_DELAY;
+    I2C_TRISTATE;
+
+    if (!quiet) {
+	printf("\n");
+    }
+
+#ifdef CONFIG_ETHER_LOOPBACK_TEST
+    /*
+     * Run the Ethernet loopback test
+     */
+    eth_loopback_test ();
+#endif /* CONFIG_ETHER_LOOPBACK_TEST */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+    /*
+     * Turn off the RED fail LED now that we are up and running.
+     */
+    status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+#endif
+
+    return 0;
+}
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+/*
+ * Show boot status: flash the LED if something goes wrong, indicating
+ * that last thing that worked and thus, by implication, what is broken.
+ *
+ * This stores the last OK value in RAM so this will not work properly
+ * before RAM is initialized.  Since it is being used for indicating
+ * boot status (i.e. after RAM is initialized), that is OK.
+ */
+static void flash_code(uchar number, uchar modulo, uchar digits)
+{
+    int   j;
+
+    /*
+     * Recursively do upper digits.
+     */
+    if(digits > 1) {
+	flash_code(number / modulo, modulo, digits - 1);
+    }
+
+    number = number % modulo;
+
+    /*
+     * Zero is indicated by one long flash (dash).
+     */
+    if(number == 0) {
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+	udelay(1000000);
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+	udelay(200000);
+    } else {
+	/*
+	 * Non-zero is indicated by short flashes, one per count.
+	 */
+	for(j = 0; j < number; j++) {
+	    status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+	    udelay(100000);
+	    status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+	    udelay(200000);
+	}
+    }
+    /*
+     * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
+     */
+    udelay(700000);
+}
+
+static int last_boot_progress;
+
+void show_boot_progress (int status)
+{
+    int i,j;
+    if(status > 0) {
+	last_boot_progress = status;
+    } else {
+	/*
+	 * If a specific failure code is given, flash this code
+	 * else just use the last success code we've seen
+	 */
+	if(status < -1)
+	    last_boot_progress = -status;
+
+	/*
+	 * Flash this code 5 times
+	 */
+	for(j=0; j<5; j++) {
+	    /*
+	     * Houston, we have a problem.
+	     * Blink the last OK status which indicates where things failed.
+	     */
+	    status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+	    flash_code(last_boot_progress, 5, 3);
+
+	    /*
+	     * Delay 5 seconds between repetitions,
+	     * with the fault LED blinking
+	     */
+	    for(i=0; i<5; i++) {
+		status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+		udelay(500000);
+		status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+		udelay(500000);
+	    }
+	}
+
+	/*
+	 * Reset the board to retry initialization.
+	 */
+	do_reset (NULL, 0, 0, NULL);
+    }
+}
+#endif /* CONFIG_SHOW_BOOT_PROGRESS */
+
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_SPI)
+
+#define SPI_ADC_CS_MASK	0x00000800
+#define SPI_DAC_CS_MASK	0x00001000
+
+void spi_adc_chipsel(int cs)
+{
+    volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
+
+    if(cs)
+	iopd->pdat &= ~SPI_ADC_CS_MASK;	/* activate the chip select */
+    else
+	iopd->pdat |=  SPI_ADC_CS_MASK;	/* deactivate the chip select */
+}
+
+void spi_dac_chipsel(int cs)
+{
+    volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
+
+    if(cs)
+	iopd->pdat &= ~SPI_DAC_CS_MASK;	/* activate the chip select */
+    else
+	iopd->pdat |=  SPI_DAC_CS_MASK;	/* deactivate the chip select */
+}
+
+/*
+ * The SPI command uses this table of functions for controlling the SPI
+ * chip selects: it calls the appropriate function to control the SPI
+ * chip selects.
+ */
+spi_chipsel_type spi_chipsel[] = {
+	spi_adc_chipsel,
+	spi_dac_chipsel
+};
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
+#endif /* CFG_CMD_SPI */
+
+#endif /* CONFIG_MISC_INIT_R */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;	/* No hotkeys supported */
+}
+
+#endif
diff --git a/board/sacsng/u-boot.lds b/board/sacsng/u-boot.lds
new file mode 100755
index 0000000..9e623d0
--- /dev/null
+++ b/board/sacsng/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c
new file mode 100755
index 0000000..762fb73
--- /dev/null
+++ b/board/sandburst/common/flash.c
@@ -0,0 +1,512 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * Ported from Ebony flash support
+ * Travis B. Sawyer
+ * Sandburst Corporation
+ */
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+	{0xfff80000}	/* Boot Flash */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+
+#define ADDR0		0x5555
+#define ADDR1		0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size(
+			(vu_long *)flash_addr_table[index][i], &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, size_b[i], size_b[i]<<20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	 /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		{
+			if (*flash++ != 0xffffffff)
+			{
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+			printf (" %08lX%s%s",
+				info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   "
+				);
+			}
+		printf ("\n");
+		return;
+	}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
+
+	/* Write auto select command: read Manufacturer ID */
+	udelay(10000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	udelay(1000);
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	udelay(1000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[1];			/* device ID		*/
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000; /* => 512 kb */
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id  == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/* reset to return to reading data */
+	addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+			DEBUGF("Erasing sector %p\n", addr2);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00500050;	 /* block erase */
+				for (i=0; i<50; i++)
+					udelay(1000);  /* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00300030;	 /* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c
new file mode 100755
index 0000000..859dd7a
--- /dev/null
+++ b/board/sandburst/common/ppc440gx_i2c.c
@@ -0,0 +1,512 @@
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by
+ * Travis B. Sawyer
+ * Sandburst Corporation.
+ */
+#include <common.h>
+#include <ppc4xx.h>
+#if defined(CONFIG_440)
+#   include <440_i2c.h>
+#else
+#   include <405gp_i2c.h>
+#endif
+#include <i2c.h>
+#include <440_i2c.h>
+#include <command.h>
+#include "ppc440gx_i2c.h"
+
+#ifdef CONFIG_I2C_BUS1
+
+#define IIC_OK		0
+#define IIC_NOK		1
+#define IIC_NOK_LA	2		/* Lost arbitration */
+#define IIC_NOK_ICT	3		/* Incomplete transfer */
+#define IIC_NOK_XFRA	4		/* Transfer aborted */
+#define IIC_NOK_DATA	5		/* No data in buffer */
+#define IIC_NOK_TOUT	6		/* Transfer timeout */
+
+#define IIC_TIMEOUT 1			/* 1 second */
+#if defined(CFG_I2C_NOPROBES)
+static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
+#endif
+
+static void _i2c_bus1_reset (void)
+{
+	int i, status;
+
+	/* Reset status register */
+	/* write 1 in SCMP and IRQA to clear these fields */
+	out8 (IIC_STS1, 0x0A);
+
+	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
+	out8 (IIC_EXTSTS1, 0x8F);
+	__asm__ volatile ("eieio");
+
+	/*
+	 * Get current state, reset bus
+	 * only if no transfers are pending.
+	 */
+	i = 10;
+	do {
+		/* Get status */
+		status = in8 (IIC_STS1);
+		udelay (500);			/* 500us */
+		i--;
+	} while ((status & IIC_STS_PT) && (i > 0));
+	/* Soft reset controller */
+	status = in8 (IIC_XTCNTLSS1);
+	out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
+	__asm__ volatile ("eieio");
+
+	/* make sure where in initial state, data hi, clock hi */
+	out8 (IIC_DIRECTCNTL1, 0xC);
+	for (i = 0; i < 10; i++) {
+		if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
+			/* clock until we get to known state */
+			out8 (IIC_DIRECTCNTL1, 0x8);	/* clock lo */
+			udelay (100);		/* 100us */
+			out8 (IIC_DIRECTCNTL1, 0xC);	/* clock hi */
+			udelay (100);		/* 100us */
+		} else {
+			break;
+		}
+	}
+	/* send start condition */
+	out8 (IIC_DIRECTCNTL1, 0x4);
+	udelay (1000);				/* 1ms */
+	/* send stop condition */
+	out8 (IIC_DIRECTCNTL1, 0xC);
+	udelay (1000);				/* 1ms */
+	/* Unreset controller */
+	out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
+	udelay (1000);				/* 1ms */
+}
+
+void i2c1_init (int speed, int slaveadd)
+{
+	sys_info_t sysInfo;
+	unsigned long freqOPB;
+	int val, divisor;
+
+#ifdef CFG_I2C_INIT_BOARD
+	/* call board specific i2c bus reset routine before accessing the   */
+	/* environment, which might be in a chip on that bus. For details   */
+	/* about this problem see doc/I2C_Edge_Conditions.                  */
+	i2c_init_board();
+#endif
+
+	/* Handle possible failed I2C state */
+	/* FIXME: put this into i2c_init_board()? */
+	_i2c_bus1_reset ();
+
+	/* clear lo master address */
+	out8 (IIC_LMADR1, 0);
+
+	/* clear hi master address */
+	out8 (IIC_HMADR1, 0);
+
+	/* clear lo slave address */
+	out8 (IIC_LSADR1, 0);
+
+	/* clear hi slave address */
+	out8 (IIC_HSADR1, 0);
+
+	/* Clock divide Register */
+	/* get OPB frequency */
+	get_sys_info (&sysInfo);
+	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
+	/* set divisor according to freqOPB */
+	divisor = (freqOPB - 1) / 10000000;
+	if (divisor == 0)
+		divisor = 1;
+	out8 (IIC_CLKDIV1, divisor);
+
+	/* no interrupts */
+	out8 (IIC_INTRMSK1, 0);
+
+	/* clear transfer count */
+	out8 (IIC_XFRCNT1, 0);
+
+	/* clear extended control & stat */
+	/* write 1 in SRC SRS SWC SWS to clear these fields */
+	out8 (IIC_XTCNTLSS1, 0xF0);
+
+	/* Mode Control Register
+	   Flush Slave/Master data buffer */
+	out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
+	__asm__ volatile ("eieio");
+
+
+	val = in8(IIC_MDCNTL1);
+	__asm__ volatile ("eieio");
+
+	/* Ignore General Call, slave transfers are ignored,
+	   disable interrupts, exit unknown bus state, enable hold
+	   SCL
+	   100kHz normaly or FastMode for 400kHz and above
+	*/
+
+	val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
+	if( speed >= 400000 ){
+		val |= IIC_MDCNTL_FSM;
+	}
+	out8 (IIC_MDCNTL1, val);
+
+	/* clear control reg */
+	out8 (IIC_CNTL1, 0x00);
+	__asm__ volatile ("eieio");
+
+}
+
+/*
+  This code tries to use the features of the 405GP i2c
+  controller. It will transfer up to 4 bytes in one pass
+  on the loop. It only does out8(lbz) to the buffer when it
+  is possible to do out16(lhz) transfers.
+
+  cmd_type is 0 for write 1 for read.
+
+  addr_len can take any value from 0-255, it is only limited
+  by the char, we could make it larger if needed. If it is
+  0 we skip the address write cycle.
+
+  Typical case is a Write of an addr followd by a Read. The
+  IBM FAQ does not cover this. On the last byte of the write
+  we don't set the creg CHT bit, and on the first bytes of the
+  read we set the RPST bit.
+
+  It does not support address only transfers, there must be
+  a data part. If you want to write the address yourself, put
+  it in the data pointer.
+
+  It does not support transfer to/from address 0.
+
+  It does not check XFRCNT.
+*/
+static
+int i2c_transfer1(unsigned char cmd_type,
+		  unsigned char chip,
+		  unsigned char addr[],
+		  unsigned char addr_len,
+		  unsigned char data[],
+		  unsigned short data_len )
+{
+	unsigned char* ptr;
+	int reading;
+	int tran,cnt;
+	int result;
+	int status;
+	int i;
+	uchar creg;
+
+	if( data == 0 || data_len == 0 ){
+		/*Don't support data transfer of no length or to address 0*/
+		printf( "i2c_transfer: bad call\n" );
+		return IIC_NOK;
+	}
+	if( addr && addr_len ){
+		ptr = addr;
+		cnt = addr_len;
+		reading = 0;
+	}else{
+		ptr = data;
+		cnt = data_len;
+		reading = cmd_type;
+	}
+
+	/*Clear Stop Complete Bit*/
+	out8(IIC_STS1,IIC_STS_SCMP);
+	/* Check init */
+	i=10;
+	do {
+		/* Get status */
+		status = in8(IIC_STS1);
+		__asm__ volatile("eieio");
+		i--;
+	} while ((status & IIC_STS_PT) && (i>0));
+
+	if (status & IIC_STS_PT) {
+		result = IIC_NOK_TOUT;
+		return(result);
+	}
+	/*flush the Master/Slave Databuffers*/
+	out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
+	/*need to wait 4 OPB clocks? code below should take that long*/
+
+	/* 7-bit adressing */
+	out8(IIC_HMADR1,0);
+	out8(IIC_LMADR1, chip);
+	__asm__ volatile("eieio");
+
+	tran = 0;
+	result = IIC_OK;
+	creg = 0;
+
+	while ( tran != cnt && (result == IIC_OK)) {
+		int  bc,j;
+
+		/* Control register =
+		   Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
+		   Transfer is a sequence of transfers
+		*/
+		creg |= IIC_CNTL_PT;
+
+		bc = (cnt - tran) > 4 ? 4 :
+			cnt - tran;
+		creg |= (bc-1)<<4;
+		/* if the real cmd type is write continue trans*/
+		if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
+			creg |= IIC_CNTL_CHT;
+
+		if (reading)
+			creg |= IIC_CNTL_READ;
+		else {
+			for(j=0; j<bc; j++) {
+				/* Set buffer */
+				out8(IIC_MDBUF1,ptr[tran+j]);
+				__asm__ volatile("eieio");
+			}
+		}
+		out8(IIC_CNTL1, creg );
+		__asm__ volatile("eieio");
+
+		/* Transfer is in progress
+		   we have to wait for upto 5 bytes of data
+		   1 byte chip address+r/w bit then bc bytes
+		   of data.
+		   udelay(10) is 1 bit time at 100khz
+		   Doubled for slop. 20 is too small.
+		*/
+		i=2*5*8;
+		do {
+			/* Get status */
+			status = in8(IIC_STS1);
+			__asm__ volatile("eieio");
+			udelay (10);
+			i--;
+		} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
+			 && (i>0));
+
+		if (status & IIC_STS_ERR) {
+			result = IIC_NOK;
+			status = in8 (IIC_EXTSTS1);
+			/* Lost arbitration? */
+			if (status & IIC_EXTSTS_LA)
+				result = IIC_NOK_LA;
+			/* Incomplete transfer? */
+			if (status & IIC_EXTSTS_ICT)
+				result = IIC_NOK_ICT;
+			/* Transfer aborted? */
+			if (status & IIC_EXTSTS_XFRA)
+				result = IIC_NOK_XFRA;
+		} else if ( status & IIC_STS_PT) {
+			result = IIC_NOK_TOUT;
+		}
+		/* Command is reading => get buffer */
+		if ((reading) && (result == IIC_OK)) {
+			/* Are there data in buffer */
+			if (status & IIC_STS_MDBS) {
+				/*
+				  even if we have data we have to wait 4OPB clocks
+				  for it to hit the front of the FIFO, after that
+				  we can just read. We should check XFCNT here and
+				  if the FIFO is full there is no need to wait.
+				*/
+				udelay (1);
+				for(j=0;j<bc;j++) {
+					ptr[tran+j] = in8(IIC_MDBUF1);
+					__asm__ volatile("eieio");
+				}
+			} else
+				result = IIC_NOK_DATA;
+		}
+		creg = 0;
+		tran+=bc;
+		if( ptr == addr && tran == cnt ) {
+			ptr = data;
+			cnt = data_len;
+			tran = 0;
+			reading = cmd_type;
+			if( reading )
+				creg = IIC_CNTL_RPST;
+		}
+	}
+	return (result);
+}
+
+int i2c_probe1 (uchar chip)
+{
+	uchar buf[1];
+
+	buf[0] = 0;
+
+	/*
+	 * What is needed is to send the chip address and verify that the
+	 * address was <ACK>ed (i.e. there was a chip at that address which
+	 * drove the data line low).
+	 */
+	return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
+}
+
+
+int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+	uchar xaddr[4];
+	int ret;
+
+	if ( alen > 4 ) {
+		printf ("I2C read: addr len %d not supported\n", alen);
+		return 1;
+	}
+
+	if ( alen > 0 ) {
+		xaddr[0] = (addr >> 24) & 0xFF;
+		xaddr[1] = (addr >> 16) & 0xFF;
+		xaddr[2] = (addr >> 8) & 0xFF;
+		xaddr[3] = addr & 0xFF;
+	}
+
+
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+	/*
+	 * EEPROM chips that implement "address overflow" are ones
+	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	 * address and the extra bits end up in the "chip address"
+	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+	 * four 256 byte chips.
+	 *
+	 * Note that we consider the length of the address field to
+	 * still be one byte because the extra address bits are
+	 * hidden in the chip address.
+	 */
+	if( alen > 0 )
+		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+	if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
+		printf( "I2c read: failed %d\n", ret);
+		return 1;
+	}
+	return 0;
+}
+
+int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+	uchar xaddr[4];
+
+	if ( alen > 4 ) {
+		printf ("I2C write: addr len %d not supported\n", alen);
+		return 1;
+
+	}
+	if ( alen > 0 ) {
+		xaddr[0] = (addr >> 24) & 0xFF;
+		xaddr[1] = (addr >> 16) & 0xFF;
+		xaddr[2] = (addr >> 8) & 0xFF;
+		xaddr[3] = addr & 0xFF;
+	}
+
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+	/*
+	 * EEPROM chips that implement "address overflow" are ones
+	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+	 * address and the extra bits end up in the "chip address"
+	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+	 * four 256 byte chips.
+	 *
+	 * Note that we consider the length of the address field to
+	 * still be one byte because the extra address bits are
+	 * hidden in the chip address.
+	 */
+	if( alen > 0 )
+		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+#endif
+
+	return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+}
+
+/*-----------------------------------------------------------------------
+ * Read a register
+ */
+uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
+{
+	uchar buf;
+
+	i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
+
+	return(buf);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a register
+ */
+void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c_write1(i2c_addr, reg, 1, &val, 1);
+}
+
+
+int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int j;
+#if defined(CFG_I2C_NOPROBES)
+	int k, skip;
+#endif
+
+	puts ("Valid chip addresses:");
+	for(j = 0; j < 128; j++) {
+#if defined(CFG_I2C_NOPROBES)
+		skip = 0;
+		for (k = 0; k < sizeof(i2c_no_probes); k++){
+			if (j == i2c_no_probes[k]){
+				skip = 1;
+				break;
+			}
+		}
+		if (skip)
+			continue;
+#endif
+		if(i2c_probe1(j) == 0) {
+			printf(" %02X", j);
+		}
+	}
+	putc ('\n');
+
+#if defined(CFG_I2C_NOPROBES)
+	puts ("Excluded chip addresses:");
+	for( k = 0; k < sizeof(i2c_no_probes); k++ )
+		printf(" %02X", i2c_no_probes[k] );
+	putc ('\n');
+#endif
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	iprobe1,	1,	1,	do_i2c1_probe,
+	"iprobe1  - probe to discover valid I2C chip addresses\n",
+	"\n    -discover valid I2C chip addresses\n"
+);
+
+#endif	/* CONFIG_I2C_BUS1 */
diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h
new file mode 100755
index 0000000..cd4fc86
--- /dev/null
+++ b/board/sandburst/common/ppc440gx_i2c.h
@@ -0,0 +1,64 @@
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Ported from i2c driver for ppc4xx by AS HARNOIS by
+ * Travis B. Sawyer
+ * Sandburst Corporation
+ */
+#include <common.h>
+#include <ppc4xx.h>
+#if defined(CONFIG_440)
+#   include <440_i2c.h>
+#else
+#   include <405gp_i2c.h>
+#endif
+#include <i2c.h>
+
+#ifdef CONFIG_HARD_I2C
+
+#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500)
+#define	   I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR
+#define    IIC_MDBUF1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF)
+#define    IIC_SDBUF1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF)
+#define    IIC_LMADR1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR)
+#define    IIC_HMADR1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR)
+#define    IIC_CNTL1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL)
+#define    IIC_MDCNTL1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL)
+#define    IIC_STS1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS)
+#define    IIC_EXTSTS1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS)
+#define    IIC_LSADR1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR)
+#define    IIC_HSADR1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR)
+#define    IIC_CLKDIV1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV)
+#define    IIC_INTRMSK1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK)
+#define    IIC_XFRCNT1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT)
+#define    IIC_XTCNTLSS1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS)
+#define    IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL)
+
+void i2c1_init (int speed, int slaveadd);
+int i2c_probe1 (uchar chip);
+int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
+int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len);
+uchar i2c_reg_read1(uchar i2c_addr, uchar reg);
+void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val);
+
+#endif	/* CONFIG_HARD_I2C */
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
new file mode 100755
index 0000000..3530416
--- /dev/null
+++ b/board/sandburst/common/sb_common.c
@@ -0,0 +1,451 @@
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "ppc440gx_i2c.h"
+#include "sb_common.h"
+
+long int fixed_sdram (void);
+
+/*************************************************************************
+ *  metrobox_get_master
+ *
+ *  PRI_N - active low signal.	If the GPIO pin is low we are the master
+ *
+ ************************************************************************/
+int sbcommon_get_master(void)
+{
+	ppc440_gpio_regs_t *gpio_regs;
+
+	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+
+	if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
+		return 0;
+	}
+	else {
+		return 1;
+	}
+}
+
+/*************************************************************************
+ *  metrobox_secondary_present
+ *
+ *  Figure out if secondary/slave board is present
+ *
+ ************************************************************************/
+int sbcommon_secondary_present(void)
+{
+	ppc440_gpio_regs_t *gpio_regs;
+
+	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+
+	if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
+		return 0;
+	else
+		return 1;
+}
+
+/*************************************************************************
+ *  sbcommon_get_serial_number
+ *
+ *  Retrieve the board serial number via the mac address in eeprom
+ *
+ ************************************************************************/
+unsigned short sbcommon_get_serial_number(void)
+{
+	unsigned char buff[0x100];
+	unsigned short sernum;
+
+	/* Get the board serial number from eeprom */
+	/* Initialize I2C */
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/* Read 256 bytes in EEPROM */
+	i2c_read (0x50, 0, 1, buff, 0x100);
+
+	memcpy(&sernum, &buff[0xF4], 2);
+	sernum /= 32;
+
+	return (sernum);
+}
+
+/*************************************************************************
+ *  sbcommon_fans
+ *
+ *  Spin up fans 2 & 3 to get some air moving.	OS will take care
+ *  of the rest.  This is mostly a precaution...
+ *
+ *  Assumes i2c bus 1 is ready.
+ *
+ ************************************************************************/
+void sbcommon_fans(void)
+{
+	/*
+	 * Attempt to turn on 2 of the fans...
+	 * Need to go through the bridge
+	 */
+	puts ("FANS:  ");
+
+	/* select fan4 through the bridge */
+	i2c_reg_write1(0x73, /* addr */
+		       0x00, /* reg */
+		       0x08); /* val = bus 4 */
+
+	/* Turn on FAN 4 */
+	i2c_reg_write1(0x2e,
+		       1,
+		       0x80);
+
+	i2c_reg_write1(0x2e,
+		       0,
+		       0x19);
+
+	/* Deselect bus 4 on the bridge */
+	i2c_reg_write1(0x73,
+		       0x00,
+		       0x00);
+
+	/* select fan3 through the bridge */
+	i2c_reg_write1(0x73, /* addr */
+		       0x00, /* reg */
+		       0x04); /* val = bus 3 */
+
+	/* Turn on FAN 3 */
+	i2c_reg_write1(0x2e,
+		       1,
+		       0x80);
+
+	i2c_reg_write1(0x2e,
+		       0,
+		       0x19);
+
+	/* Deselect bus 3 on the bridge */
+	i2c_reg_write1(0x73,
+		       0x00,
+		       0x00);
+
+	/* select fan2 through the bridge */
+	i2c_reg_write1(0x73, /* addr */
+		       0x00, /* reg */
+		       0x02); /* val = bus 4 */
+
+	/* Turn on FAN 2 */
+	i2c_reg_write1(0x2e,
+		       1,
+		       0x80);
+
+	i2c_reg_write1(0x2e,
+		       0,
+		       0x19);
+
+	/* Deselect bus 2 on the bridge */
+	i2c_reg_write1(0x73,
+		       0x00,
+		       0x00);
+
+	/* select fan1 through the bridge */
+	i2c_reg_write1(0x73, /* addr */
+		       0x00, /* reg */
+		       0x01); /* val = bus 0 */
+
+	/* Turn on FAN 1 */
+	i2c_reg_write1(0x2e,
+		       1,
+		       0x80);
+
+	i2c_reg_write1(0x2e,
+		       0,
+		       0x19);
+
+	/* Deselect bus 1 on the bridge */
+	i2c_reg_write1(0x73,
+		       0x00,
+		       0x00);
+
+	puts ("on\n");
+
+	return;
+
+}
+
+/*************************************************************************
+ *  initdram
+ *
+ *  Initialize sdram
+ *
+ ************************************************************************/
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram (0);
+#else
+	dram_size = fixed_sdram ();
+#endif
+	return dram_size;
+}
+
+
+/*************************************************************************
+ *  testdram
+ *
+ *
+ ************************************************************************/
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing SDRAM: ");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("OK\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:	128 MB, non-ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)		*/
+	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0		*/
+	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)		*/
+	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0			*/
+	mtsdram (mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0	*/
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (mem_tr0, 0x410a4012);	/* WR=2	 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3			    */
+	mtsdram (mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB	    */
+	mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)	    */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit	    */
+	for (;;) {
+		mfsdram (mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB			    */
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+
+	/*--------------------------------------------------------------------------+
+	 *	The metrobox is always configured as the host & requires the
+	 *	PCI arbiter to be enabled.
+	 *--------------------------------------------------------------------------*/
+	mfsdr(sdr_sdstp1, strap);
+	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
+		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
+		return 0;
+	}
+
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+    /* The metrobox is always configured as host. */
+    return(1);
+}
+#endif /* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ *  board_get_enetaddr
+ *
+ *  Get the ethernet MAC address for the management ethernet from the
+ *  strap EEPROM.  Note that is the BASE address for the range of
+ *  external ethernet MACs on the board.  The base + 31 is the actual
+ *  mgmt mac address.
+ *
+ ************************************************************************/
+static int macaddr_idx = 0;
+
+void board_get_enetaddr (uchar * enet)
+{
+	int i;
+	unsigned short tmp;
+	unsigned char buff[0x100], *cp;
+
+	if (0 == macaddr_idx) {
+
+		/* Initialize I2C */
+		i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+		/* Read 256 bytes in EEPROM */
+		i2c_read (0x50, 0, 1, buff, 0x100);
+
+		cp = &buff[0xF0];
+
+		for (i = 0; i < 6; i++,cp++)
+			enet[i] = *cp;
+
+		memcpy(&tmp, &enet[4], 2);
+		tmp += 31;
+		memcpy(&enet[4], &tmp, 2);
+
+		macaddr_idx++;
+	} else {
+		enet[0] = 0x02;
+		enet[1] = 0x00;
+		enet[2] = 0x00;
+		enet[3] = 0x00;
+		enet[4] = 0x00;
+		if (1 == sbcommon_get_master() ) {
+			/* Master/Primary card */
+			enet[5] = 0x01;
+		} else {
+			/* Slave/Secondary card */
+			enet [5] = 0x02;
+		}
+	}
+
+	return;
+}
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+	return (ctrlc());
+}
+#endif
diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h
new file mode 100755
index 0000000..888e4f0
--- /dev/null
+++ b/board/sandburst/common/sb_common.h
@@ -0,0 +1,76 @@
+#ifndef __SBCOMMON_H__
+#define __SBCOMMON_H__
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "ppc440gx_i2c.h"
+
+/*
+ * GPIO Settings
+ */
+/* Chassis settings */
+#define SBCOMMON_GPIO_PRI_N		0x00001000  /* 0 = Chassis Master, 1 = Slave */
+#define SBCOMMON_GPIO_SEC_PRES		0x00000800  /* 1 = Other board present */
+
+/* Debug LEDs */
+#define SBCOMMON_GPIO_DBGLED_0		0x00000400
+#define SBCOMMON_GPIO_DBGLED_1		0x00000200
+#define SBCOMMON_GPIO_DBGLED_2		0x00100000
+#define SBCOMMON_GPIO_DBGLED_3		0x00000100
+
+#define SBCOMMON_GPIO_DBGLEDS		(SBCOMMON_GPIO_DBGLED_0 | \
+					 SBCOMMON_GPIO_DBGLED_1 | \
+					 SBCOMMON_GPIO_DBGLED_2 | \
+					 SBCOMMON_GPIO_DBGLED_3)
+
+#define SBCOMMON_GPIO_SYS_FAULT		0x00000080
+#define SBCOMMON_GPIO_SYS_OTEMP		0x00000040
+#define SBCOMMON_GPIO_SYS_STATUS	0x00000020
+
+#define SBCOMMON_GPIO_SYS_LEDS		(SBCOMMON_GPIO_SYS_STATUS)
+
+#define SBCOMMON_GPIO_LEDS		(SBCOMMON_GPIO_DBGLED_0 | \
+					 SBCOMMON_GPIO_DBGLED_1 | \
+					 SBCOMMON_GPIO_DBGLED_2 | \
+					 SBCOMMON_GPIO_DBGLED_3 | \
+					 SBCOMMON_GPIO_SYS_STATUS)
+
+typedef struct ppc440_gpio_regs {
+	volatile unsigned long out;
+	volatile unsigned long tri_state;
+	volatile unsigned long dummy[4];
+	volatile unsigned long open_drain;
+	volatile unsigned long in;
+}  __attribute__((packed)) ppc440_gpio_regs_t;
+
+int sbcommon_get_master(void);
+int sbcommon_secondary_present(void);
+unsigned short sbcommon_get_serial_number(void);
+void sbcommon_fans(void);
+
+#endif /* __SBCOMMON_H__ */
diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile
new file mode 100755
index 0000000..8b3173c
--- /dev/null
+++ b/board/sandburst/karef/Makefile
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+# Travis B. Sawyer
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# TBS: add for debugging purposes
+BUILDUSER := $(shell whoami)
+FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
+
+CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
+# TBS: end debugging
+
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+	../common/sb_common.o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk
new file mode 100755
index 0000000..65c1e48
--- /dev/null
+++ b/board/sandburst/karef/config.mk
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2005
+# Sandburst Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Sandburst Corporation Metrobox Reference Design
+# Travis B. Sawyer
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h
new file mode 100755
index 0000000..cc501c9
--- /dev/null
+++ b/board/sandburst/karef/hal_ka_of_auto.h
@@ -0,0 +1,324 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_of
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_OF_AUTO_H
+#define HAL_KA_OF_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'ofem'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define OFEM_BLOCK_ADDR_BIT_L 6
+#define OFEM_BLOCK_ADDR_BIT_H 9
+#define OFEM_BLOCK_ADDR_WIDTH 4
+
+#define  OFEM_ADDR  0x0
+
+/* ---- Reg addressing (within block) */
+#define OFEM_REG_ADDR_BIT_L 2
+#define OFEM_REG_ADDR_BIT_H 5
+#define OFEM_REG_ADDR_WIDTH 4
+
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET    0x000
+#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_REVISION_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_REVISION_MSB     31
+#define SAND_HAL_KA_OF_OFEM_REVISION_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET    0x004
+#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_RESET_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_RESET_MSB     31
+#define SAND_HAL_KA_OF_OFEM_RESET_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET    0x018
+#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_CNTL_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_CNTL_MSB     31
+#define SAND_HAL_KA_OF_OFEM_CNTL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET    0x01c
+#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB     31
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET    0x008
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB     31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET    0x00c
+#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB     31
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET    0x010
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB     31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB      0
+
+/* ================================================================
+ * ---- Register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET    0x014
+#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB     31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB      0
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_REVISION */
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK    0x0000ff00
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB    15
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB    8
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT    0x00000024
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK    0x000000ff
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB    7
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB    0
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_RESET */
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK    0x00000004
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB    2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB    2
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK    0x00000002
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT    1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB    1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB    1
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK    0x00000001
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB    0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB    0
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_CNTL */
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK    0x000000c0
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT    6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB    7
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB    6
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK    0x00000030
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB    5
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB    4
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK    0x0000000c
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB    3
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB    2
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK    0x00000003
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB    1
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB    0
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK    0x00000100
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB    8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB    8
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK    0x00000010
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB    4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB    4
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK    0x0000000f
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB    3
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB    0
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK    0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK    0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK    0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK    0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK    0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK    0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK    0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK    0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_INTERRUPT_MASK */
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK    0x00000100
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB    8
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK    0x00000080
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB    7
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK    0x00000040
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB    6
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK    0x00000020
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB    5
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK    0x00000010
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB    4
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK    0x00000008
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB    3
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK    0x00000004
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB    2
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK    0x00000002
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB    1
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK    0x00000001
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB    0
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB    31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_OF_OFEM_SCRATCH_MASK */
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
+
+#endif /* matches #ifndef HAL_KA_OF_AUTO_H */
diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h
new file mode 100755
index 0000000..db1cec2
--- /dev/null
+++ b/board/sandburst/karef/hal_ka_sc_auto.h
@@ -0,0 +1,836 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip ka_sc
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_KA_SC_AUTO_H
+#define HAL_KA_SC_AUTO_H
+
+
+/* ----------------------------------------------------------------
+ * For block: 'scan'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define SCAN_BLOCK_ADDR_BIT_L 7
+#define SCAN_BLOCK_ADDR_BIT_H 9
+#define SCAN_BLOCK_ADDR_WIDTH 3
+
+#define  SCAN_ADDR  0x0
+
+/* ---- Reg addressing (within block) */
+#define SCAN_REG_ADDR_BIT_L 2
+#define SCAN_REG_ADDR_BIT_H 6
+#define SCAN_REG_ADDR_WIDTH 5
+
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET    0x000
+#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_REVISION_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_REVISION_MSB     31
+#define SAND_HAL_KA_SC_SCAN_REVISION_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET    0x004
+#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_RESET_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_RESET_MSB     31
+#define SAND_HAL_KA_SC_SCAN_RESET_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET    0x008
+#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_STATUS_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_STATUS_MSB     31
+#define SAND_HAL_KA_SC_SCAN_STATUS_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET    0x01c
+#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CNTL_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CNTL_MSB     31
+#define SAND_HAL_KA_SC_SCAN_CNTL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET    0x020
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET    0x024
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET    0x028
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET    0x02c
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET    0x030
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET    0x034
+#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET    0x038
+#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB     31
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET    0x03c
+#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET    0x040
+#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET    0x044
+#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET    0x048
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET    0x04c
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET    0x050
+#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB     31
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET    0x054
+#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_MISC_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_MISC_MSB     31
+#define SAND_HAL_KA_SC_SCAN_MISC_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET    0x00c
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB     31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET    0x010
+#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB     31
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET    0x014
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB      0
+
+/* ================================================================
+ * ---- Register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET    0x018
+#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB     31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB      0
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_REVISION */
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK    0x0000ff00
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB    15
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB    8
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT    0x00000023
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK    0x000000ff
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB    7
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB    0
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_RESET */
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB    9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB    9
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB    8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB    8
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK    0x00000080
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT    7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB    7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB    7
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK    0x00000040
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB    6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB    6
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK    0x00000020
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT    5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB    5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB    5
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB    4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB    4
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB    3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB    3
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB    1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB    1
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB    0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB    0
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_STATUS */
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK    0x00000040
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB    6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB    6
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK    0x00000020
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT    5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB    5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB    5
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB    4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB    4
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB    3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB    3
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB    2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB    2
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB    1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB    1
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB    0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB    0
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CNTL */
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK    0x00000400
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT    10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB    10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB    10
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB    9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB    9
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB    8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB    8
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK    0x000000c0
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB    7
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB    6
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK    0x00000030
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB    5
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB    4
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK    0x0000000c
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB    3
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB    2
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK    0x00000003
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB    1
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB    0
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_INFO */
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK    0x0000f000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT    12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB    15
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB    12
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK    0x00000300
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB    9
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB    8
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK    0x000000f0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB    7
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB    4
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK    0x00000003
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB    1
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_FROM_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_0 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_TO_1 */
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCAN_CTRL */
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK    0x04000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT    26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB    26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB    26
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK    0x03000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB    25
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB    24
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK    0x00100000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT    20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB    20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB    20
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK    0x00080000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT    19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB    19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB    19
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK    0x00040000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT    18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB    18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB    18
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK    0x00020000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT    17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB    17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB    17
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK    0x00010000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT    16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB    16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB    16
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK    0x00001000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT    12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB    12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB    12
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK    0x00000800
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT    11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB    11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB    11
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK    0x00000400
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT    10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB    10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB    10
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB    9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB    9
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB    8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB    8
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK    0x00000018
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB    4
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB    3
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB    2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB    2
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB    1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB    1
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_PLL_CTRL */
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK    0x00002000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT    13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB    13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB    13
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK    0x00001000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT    12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB    12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB    12
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK    0x00000800
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT    11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB    11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB    11
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK    0x00000400
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT    10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB    10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB    10
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK    0x00000200
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT    9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB    9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB    9
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK    0x00000100
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT    8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB    8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB    8
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK    0x00000080
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT    7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB    7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB    7
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK    0x00000040
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT    6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB    6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB    6
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK    0x00000020
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT    5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB    5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB    5
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB    4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB    4
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB    3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB    3
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK    0x00000007
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB    2
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB    0
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK    0x02000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT    25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB    25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB    25
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK    0x01000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB    24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB    24
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK    0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB    23
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_DR_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK    0x02000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT    25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB    25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB    25
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK    0x01000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB    24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB    24
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK    0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB    23
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK    0x02000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT    25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB    25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB    25
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK    0x01000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT    24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB    24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB    24
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK    0x00ffffff
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB    23
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK    0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB    20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK    0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB    20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_BRD_BRD_IN */
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK    0x001fffff
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB    20
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB    0
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_MISC */
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB    1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB    1
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB    0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB    0
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT    0x00000000
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_INTERRUPT_MASK */
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK    0x00000010
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB    4
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK    0x00000008
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB    3
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK    0x00000004
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB    2
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK    0x00000002
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB    1
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK    0x00000001
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register KA_SC_SCAN_SCRATCH_MASK */
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
+
+#endif /* matches #ifndef HAL_KA_SC_AUTO_H */
diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S
new file mode 100755
index 0000000..b1d47a4
--- /dev/null
+++ b/board/sandburst/karef/init.S
@@ -0,0 +1,101 @@
+/*
+*  Copyright (C) 2005 Sandburst Corporation
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+/*
+ * Ported from Ebony init.S by Travis B. Sawyer
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbtab_end
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
new file mode 100755
index 0000000..2d71d3b
--- /dev/null
+++ b/board/sandburst/karef/karef.c
@@ -0,0 +1,570 @@
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *  Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include "karef.h"
+#include "karef_version.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "../common/sb_common.h"
+#include "../common/ppc440gx_i2c.h"
+
+void fpga_init (void);
+
+KAREF_BOARD_ID_ST board_id_as[] =
+{
+	{"Undefined"},			     /* Not specified */
+	{"Kamino Reference Design"},
+	{"Reserved"},			     /* Reserved for future use */
+	{"Reserved"},			     /* Reserved for future use */
+};
+
+KAREF_BOARD_ID_ST ofem_board_id_as[] =
+{
+	{"Undefined"},
+	{"1x10 + 10x2"},
+	{"Reserved"},
+	{"Reserved"},
+};
+
+/*************************************************************************
+ *  board_early_init_f
+ *
+ *  Setup chip selects, initialize the Opto-FPGA, initialize
+ *  interrupt polarity and triggers.
+ ************************************************************************/
+int board_early_init_f (void)
+{
+	ppc440_gpio_regs_t *gpio_regs;
+
+	/* Enable GPIO interrupts */
+	mtsdr(sdr_pfc0, 0x00103E00);
+
+	/* Setup access for LEDs, and system topology info */
+	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
+	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
+
+	/* Turn on all the leds for now */
+	gpio_regs->out = SBCOMMON_GPIO_LEDS;
+
+	/*--------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------*/
+	mtebc(xbcfg,
+	      EBC_CFG_LE_UNLOCK	   | EBC_CFG_PTD_ENABLE |
+	      EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
+	      EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
+	      EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
+	      EBC_CFG_PR_32);
+
+	/*--------------------------------------------------------------------+
+	  | 1/2 MB FLASH. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb0ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+	/*--------------------------------------------------------------------+
+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb1ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(pb2ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | KaRef Scan FPGA. Initialize bank 3 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb5ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
+	  | Initialize bank 4 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb4ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
+	      EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | OFEM FPGA  Initialize bank 5 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb3ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+
+	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(pb6ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | BME-32. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb7ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 +-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000000);	/* all non- critical */
+	mtdcr (uic0pr, 0xfffffe03);	/* polarity */
+	mtdcr (uic0tr, 0x01c00000);	/* trigger edge vs level */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffc8ff);	/* polarity */
+	mtdcr (uic1tr, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffff83ff);	/* polarity */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
+	mtdcr (uicb0er, 0x00000000);	/* disable all */
+	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000);
+	mtdcr (uicb0tr, 0x00000000);
+	mtdcr (uicb0vr, 0x00000001);
+
+	fpga_init();
+
+	return 0;
+}
+
+
+/*************************************************************************
+ *  checkboard
+ *
+ *  Dump pertinent info to the console
+ ************************************************************************/
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	unsigned char brd_rev, brd_id;
+	unsigned short sernum;
+	unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
+	unsigned char ofem_brd_rev, ofem_brd_id;
+	KAREF_FPGA_REGS_ST *karef_ps;
+	OFEM_FPGA_REGS_ST *ofem_ps;
+
+	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+	ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+
+	scan_id = (unsigned char)((karef_ps->revision_ul &
+				   SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
+				  >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
+
+	scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
+				   >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
+
+	brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
+				  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
+
+	brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
+				 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
+
+	ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+				      >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+
+	ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
+				       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
+
+	if (0xF != ofem_brd_id) {
+		ofem_id = (unsigned char)((ofem_ps->revision_ul &
+					   SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
+					  >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
+
+		ofem_rev = (unsigned char)((ofem_ps->revision_ul &
+					    SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
+					   >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
+	}
+
+	get_sys_info (&sysinfo);
+
+	sernum = sbcommon_get_serial_number();
+
+	printf ("Board: Sandburst Corporation Kamino Reference Design "
+		"Serial Number: %d\n", sernum);
+	printf ("%s\n", KAREF_U_BOOT_REL_STR);
+
+	printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+	if (sbcommon_get_master()) {
+		printf("Slot 0 - Master\nSlave board");
+		if (sbcommon_secondary_present())
+			printf(" present\n");
+		else
+			printf(" not detected\n");
+	} else {
+		printf("Slot 1 - Slave\n\n");
+	}
+
+	printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
+	printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
+	if(0xF != ofem_brd_id) {
+		printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
+		printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
+	}
+
+	/* Fix the ack in the bme 32 */
+	udelay(5000);
+	out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+	asm("eieio");
+
+
+	return (0);
+}
+
+/*************************************************************************
+ *  misc_init_f
+ *
+ *  Initialize I2C bus one to gain access to the fans
+ ************************************************************************/
+int misc_init_f (void)
+{
+	/* Turn on i2c bus 1 */
+	puts ("I2C1:  ");
+	i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	puts ("ready\n");
+
+	/* Turn on fans 3 & 4 */
+	sbcommon_fans();
+
+	return (0);
+}
+
+/*************************************************************************
+ *  misc_init_r
+ *
+ *  Do nothing.
+ ************************************************************************/
+int misc_init_r (void)
+{
+	unsigned short sernum;
+	char envstr[255];
+	KAREF_FPGA_REGS_ST *karef_ps;
+	OFEM_FPGA_REGS_ST *ofem_ps;
+
+	if(NULL != getenv("secondserial")) {
+		puts("secondserial is set, switching to second serial port\n");
+		setenv("stderr", "serial1");
+		setenv("stdout", "serial1");
+		setenv("stdin", "serial1");
+	}
+
+	setenv("ubrelver", KAREF_U_BOOT_REL_STR);
+
+	memset(envstr, 0, 255);
+	sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+	setenv("bldstr", envstr);
+	saveenv();
+
+	if( getenv("autorecover")) {
+		setenv("autorecover", NULL);
+		saveenv();
+		sernum = sbcommon_get_serial_number();
+
+		printf("\nSetting up environment for automatic filesystem recovery\n");
+		/*
+		 * Setup default bootargs
+		 */
+		memset(envstr, 0, 255);
+
+		sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+			"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+			sernum, sernum);
+		setenv("bootargs", envstr);
+
+		/*
+		 * Setup Default boot command
+		 */
+		setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+		       "fatload ide 0 8100000 pramdisk;"
+		       "bootm 8000000 8100000");
+
+		printf("Done.  Please type allow the system to continue to boot\n");
+	}
+
+	if( getenv("fakeled")) {
+		karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+		ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+		ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
+		karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
+		setenv("bootdelay", "-1");
+		saveenv();
+		printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
+	}
+
+	return (0);
+}
+
+/*************************************************************************
+ *  ide_set_reset
+ ************************************************************************/
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	KAREF_FPGA_REGS_ST *karef_ps;
+	/* TODO: ide reset */
+	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+
+	if (on) {
+		karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+	} else {
+		karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+/*************************************************************************
+ *  fpga_init
+ ************************************************************************/
+void fpga_init(void)
+{
+	KAREF_FPGA_REGS_ST *karef_ps;
+	OFEM_FPGA_REGS_ST *ofem_ps;
+	unsigned char ofem_id;
+	unsigned long tmp;
+
+	/* Ensure we have power all around */
+	udelay(500);
+
+	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+	tmp =
+		SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
+		SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
+
+	karef_ps->reset_ul = tmp;
+
+	/*
+	 * Wait a bit to allow the ofem fpga to get its brains
+	 */
+	udelay(5000);
+
+	/*
+	 * Check to see if the ofem is there
+	 */
+	ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
+				  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
+	if(0xF != ofem_id) {
+		tmp =
+			SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
+			SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
+			SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
+
+		ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+		ofem_ps->reset_ul = tmp;
+
+		ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
+	}
+
+	karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
+
+	asm("eieio");
+
+	return;
+}
+
+int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	memset(envstr, 0, 255);
+	/*
+	 * Setup our ip address
+	 */
+	sprintf(envstr, "10.100.70.%d", sernum);
+
+	setenv("ipaddr", envstr);
+	/*
+	 * Setup the host ip address
+	 */
+	setenv("serverip", "10.100.17.10");
+
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
+		"rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
+		"nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
+		"255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
+		sernum, sernum, sernum);
+
+	setenv("bootargs_nfs", envstr);
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup CF bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
+		"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
+		sernum, sernum);
+
+	setenv("bootargs_cf", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+	setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
+	setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
+
+	/*
+	 * Setup compact flash boot command
+	 */
+	setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
+
+	saveenv();
+
+	return(1);
+}
+
+int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	printf("\nSetting up environment for filesystem recovery\n");
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+		"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
+		sernum, sernum);
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+
+	setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
+	       "fatload ide 0 8100000 pramdisk;"
+	       "bootm 8000000 8100000");
+
+	printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
+	       " please type fsrecover.sh<cr>\n");
+
+	return(1);
+}
+
+U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
+	   "kasetup - Set environment to factory defaults\n", NULL);
+
+U_BOOT_CMD(karecover, 1, 1, karefRecover,
+	   "karecover - Set environment to allow for fs recovery\n", NULL);
diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h
new file mode 100755
index 0000000..5de7cb5
--- /dev/null
+++ b/board/sandburst/karef/karef.h
@@ -0,0 +1,76 @@
+#ifndef __KAREF_H__
+#define __KAREF_H__
+/*
+ * (C) Copyright 2005
+ * Sandburst Corporation
+ * Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Ka Reference Design OFEM FPGA Registers & definitions */
+#include "hal_ka_sc_auto.h"
+#include "hal_ka_of_auto.h"
+
+typedef struct karef_board_id_s {
+	const char name[40];
+} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST;
+
+/* SCAN FPGA */
+typedef struct karef_fpga_regs_s
+{
+    volatile unsigned long revision_ul;       /* Read Only  */
+    volatile unsigned long reset_ul;          /* Read/Write */
+    volatile unsigned long interrupt_ul;      /* Read Only  */
+    volatile unsigned long mask_ul;           /* Read/Write */
+    volatile unsigned long scratch_ul;        /* Read/Write */
+    volatile unsigned long scrmask_ul;        /* Read/Write */
+    volatile unsigned long status_ul;         /* Read Only  */
+    volatile unsigned long control_ul;        /* Read/Write */
+    volatile unsigned long boardinfo_ul;      /* Read Only  */
+    volatile unsigned long scan_from0_ul;     /* Read Only  */
+    volatile unsigned long scan_from1_ul;     /* Read Only  */
+    volatile unsigned long scan_to0_ul;       /* Read/Write */
+    volatile unsigned long scan_to1_ul;       /* Read/Write */
+    volatile unsigned long scan_control_ul;   /* Read/Write */
+    volatile unsigned long pll_control_ul;    /* Read/Write */
+    volatile unsigned long core_clock_cnt_ul; /* Read/Write */
+    volatile unsigned long dr_clock_cnt_ul;   /* Read/Write */
+    volatile unsigned long spi_clock_cnt_ul;  /* Read/Write */
+    volatile unsigned long brdout_data_ul;    /* Read/Write */
+    volatile unsigned long brdout_enable_ul;  /* Read/Write */
+    volatile unsigned long brdin_data_ul;     /* Read Only  */
+    volatile unsigned long misc_ul;           /* Read/Write */
+} __attribute__((packed)) KAREF_FPGA_REGS_ST , * KAREF_FPGA_REGS_PST;
+
+/* OFEM FPGA */
+typedef struct ofem_fpga_regs_s
+{
+    volatile unsigned long revision_ul;       /* Read Only  */
+    volatile unsigned long reset_ul;          /* Read/Write */
+    volatile unsigned long interrupt_ul;      /* Read Only  */
+    volatile unsigned long mask_ul;           /* Read/Write */
+    volatile unsigned long scratch_ul;        /* Read/Write */
+    volatile unsigned long scrmask_ul;        /* Read/Write */
+    volatile unsigned long control_ul;        /* Read/Write */
+    volatile unsigned long mac_flow_ctrl_ul;  /* Read/Write */
+} __attribute__((packed)) OFEM_FPGA_REGS_ST , * OFEM_FPGA_REGS_PST;
+
+
+#endif /* __KAREF_H__ */
diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h
new file mode 100755
index 0000000..9960b9a
--- /dev/null
+++ b/board/sandburst/karef/karef_version.h
@@ -0,0 +1,26 @@
+#ifndef _KAREF_VERSION_H_
+#define _KAREF_VERSION_H_
+/*
+ *  Copyright (C) 2005 Sandburst Corporation
+ *  Travis B. Sawyer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define KAREF_U_BOOT_REL_STR "Release 0.0.7"
+#endif
diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds
new file mode 100755
index 0000000..9e9e990
--- /dev/null
+++ b/board/sandburst/karef/u-boot.lds
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/sandburst/karef/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug
new file mode 100755
index 0000000..47d80fa
--- /dev/null
+++ b/board/sandburst/karef/u-boot.lds.debug
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/sandburst/karef/init.o (.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile
new file mode 100755
index 0000000..06a9a22
--- /dev/null
+++ b/board/sandburst/metrobox/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2005
+# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# TBS: add for debugging purposes
+BUILDUSER := $(shell whoami)
+FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o)
+
+CFLAGS += -DBUILDUSER='"$(BUILDUSER)"'
+# TBS: end debugging
+
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \
+	../common/sb_common.o
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk
new file mode 100755
index 0000000..91aee2f
--- /dev/null
+++ b/board/sandburst/metrobox/config.mk
@@ -0,0 +1,38 @@
+#
+# (C) Copyright 2005
+# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h
new file mode 100755
index 0000000..c99b38c
--- /dev/null
+++ b/board/sandburst/metrobox/hal_xc_auto.h
@@ -0,0 +1,553 @@
+/* ****************************************************************
+ * Common defs for reg spec for chip xc
+ * Auto-generated by trex2: DO NOT HAND-EDIT!!
+ * ****************************************************************
+ */
+
+#ifndef HAL_XC_AUTO_H
+#define HAL_XC_AUTO_H
+
+/* ----------------------------------------------------------------
+ * For block: 'xcvr_cntl'
+ */
+
+/* ---- Block instance addressing (for block-select) */
+#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6
+#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9
+#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4
+
+#define  XCVR_CNTL_ADDR  0x0
+
+/* ---- Reg addressing (within block) */
+#define XCVR_CNTL_REG_ADDR_BIT_L 2
+#define XCVR_CNTL_REG_ADDR_BIT_H 5
+#define XCVR_CNTL_REG_ADDR_WIDTH 4
+
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_REVISION */
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET    0x000
+#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_RESET */
+#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET    0x004
+#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_STATUS */
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET    0x008
+#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_CNTL */
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET    0x01c
+#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_BRD_INFO */
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET    0x020
+#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET    0x024
+#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_INTERRUPT */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET    0x00c
+#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET    0x010
+#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_SCRATCH */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET    0x014
+#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB      0
+
+/* ================================================================
+ * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET    0x018
+#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK    0x000
+#endif
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB     31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB      0
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_REVISION */
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK    0x0000ff00
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB    15
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK    0x000000ff
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_RESET */
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK    0x00020000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT    17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB    17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB    17
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK    0x00010000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT    16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB    16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB    16
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK    0x00008000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT    15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB    15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB    15
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK    0x00004000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT    14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB    14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB    14
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK    0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT    13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB    13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB    13
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK    0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT    12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB    12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB    12
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK    0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT    11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB    11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB    11
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK    0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT    10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB    10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB    10
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK    0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT    9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB    9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB    9
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK    0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB    8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK    0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT    7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB    7
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK    0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT    6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB    6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB    6
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK    0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT    5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB    5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB    5
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK    0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB    4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK    0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT    3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB    3
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK    0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB    2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_STATUS */
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK    0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB    2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_CNTL */
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK    0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT    10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB    10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB    10
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK    0x00000300
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB    9
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK    0x000000c0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT    6
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB    6
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK    0x00000030
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB    5
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK    0x0000000c
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_BRD_INFO */
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK    0x000000f0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK    0x00000003
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK    0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT    12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB    12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB    12
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK    0x00000f00
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB    11
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK    0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB    4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK    0x0000000f
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_INTERRUPT */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK    0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK    0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK    0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK    0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK    0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK    0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK    0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK    0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK    0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK    0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK    0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK    0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT    0x00000000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK    0x00002000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB    13
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK    0x00001000
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB    12
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK    0x00000800
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB    11
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK    0x00000400
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB    10
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK    0x00000200
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB    9
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK    0x00000100
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB    8
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK    0x00000080
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB    7
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK    0x00000040
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB    6
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK    0x00000020
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB    5
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK    0x00000010
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB    4
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK    0x00000008
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB    3
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK    0x00000004
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB    2
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK    0x00000002
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB    1
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK    0x00000001
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT    0x00000001
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_SCRATCH */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB    31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT    0x00000000
+
+/* ================================================================
+ * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
+#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
+
+#endif /* matches #ifndef HAL_XC_AUTO_H */
diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S
new file mode 100755
index 0000000..e398f00
--- /dev/null
+++ b/board/sandburst/metrobox/init.S
@@ -0,0 +1,99 @@
+/*
+*  Copyright (C) 2005
+*  Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbtab_end
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
new file mode 100755
index 0000000..86d259f
--- /dev/null
+++ b/board/sandburst/metrobox/metrobox.c
@@ -0,0 +1,536 @@
+/*
+ *  Copyright (c) 2005
+ *  Travis B. Sawyer,  Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include "metrobox.h"
+#include "metrobox_version.h"
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include "../common/ppc440gx_i2c.h"
+#include "../common/sb_common.h"
+
+void fpga_init (void);
+
+METROBOX_BOARD_ID_ST board_id_as[] =
+{	{"Undefined"},			    /* Not specified */
+	{"2x10Gb"},			    /* 2 ports, 10 GbE */
+	{"20x1Gb"},			    /* 20 ports, 1 GbE */
+	{"Reserved"},			     /* Reserved for future use */
+};
+
+/*************************************************************************
+ *  board_early_init_f
+ *
+ *  Setup chip selects, initialize the Opto-FPGA, initialize
+ *  interrupt polarity and triggers.
+ ************************************************************************/
+int board_early_init_f (void)
+{
+	ppc440_gpio_regs_t *gpio_regs;
+
+	/* Enable GPIO interrupts */
+	mtsdr(sdr_pfc0, 0x00103E00);
+
+	/* Setup access for LEDs, and system topology info */
+	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
+	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
+
+	/* Turn on all the leds for now */
+	gpio_regs->out = SBCOMMON_GPIO_LEDS;
+
+	/*--------------------------------------------------------------------+
+	  | Initialize EBC CONFIG
+	  +-------------------------------------------------------------------*/
+	mtebc(xbcfg,
+	      EBC_CFG_LE_UNLOCK	   | EBC_CFG_PTD_ENABLE |
+	      EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
+	      EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
+	      EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
+	      EBC_CFG_PR_32);
+
+	/*--------------------------------------------------------------------+
+	  | 1/2 MB FLASH. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb0ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+	/*--------------------------------------------------------------------+
+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb1ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(pb2ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | OPTO & OFEM FPGA. Initialize bank 3 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb3ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | MAC A for metrobox
+	  | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
+	  | Initialize bank 4 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb4ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | Metrobox MAC B  Initialize bank 5 with default values.
+	  | KA REF FPGA	 Initialize bank 5 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb5ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	  | Compact Flash, uses 2 Chip Selects (2 & 6)
+	  +-------------------------------------------------------------------*/
+	mtebc(pb6ap,
+	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
+	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
+	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
+	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
+	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
+	      EBC_BXAP_PEN_DISABLED);
+
+	mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
+
+	/*--------------------------------------------------------------------+
+	  | BME-32. Initialize bank 7 with default values.
+	  +-------------------------------------------------------------------*/
+	mtebc(pb7ap,
+	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
+	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
+	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
+	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
+	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
+
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
+	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
+
+	/*--------------------------------------------------------------------+
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 +-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000000);	/* all non- critical */
+	mtdcr (uic0pr, 0xfffffe03);	/* polarity */
+	mtdcr (uic0tr, 0x01c00000);	/* trigger edge vs level */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffc8ff);	/* polarity */
+	mtdcr (uic1tr, 0x00ff0000);	/* trigger edge vs level */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffff83ff);	/* polarity */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* trigger edge vs level */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
+	mtdcr (uicb0er, 0x00000000);	/* disable all */
+	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000);
+	mtdcr (uicb0tr, 0x00000000);
+	mtdcr (uicb0vr, 0x00000001);
+
+	fpga_init();
+
+	return 0;
+}
+
+/*************************************************************************
+ *  checkboard
+ *
+ *  Dump pertinent info to the console
+ ************************************************************************/
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+	unsigned char brd_rev, brd_id;
+	unsigned short sernum;
+	unsigned char opto_rev, opto_id;
+	OPTO_FPGA_REGS_ST *opto_ps;
+
+	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+	opto_rev = (unsigned char)((opto_ps->revision_ul &
+				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+				   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+
+	opto_id = (unsigned char)((opto_ps->revision_ul &
+				   SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
+				  >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
+
+	brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
+				   SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
+				  >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
+
+	brd_id = (unsigned char)((opto_ps->boardinfo_ul &
+				  SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
+				 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
+
+	get_sys_info (&sysinfo);
+
+	sernum = sbcommon_get_serial_number();
+	printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
+	printf ("%s\n", METROBOX_U_BOOT_REL_STR);
+
+	printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+	if (sbcommon_get_master()) {
+		printf("Slot 0 - Master\nSlave board");
+		if (sbcommon_secondary_present())
+			printf(" present\n");
+		else
+			printf(" not detected\n");
+	} else {
+		printf("Slot 1 - Slave\n\n");
+	}
+
+	printf ("OptoFPGA ID:\t0x%02X\tRev:  0x%02X\n", opto_id, opto_rev);
+	printf ("Board Rev:\t0x%02X\tID:  %s\n", brd_rev, board_id_as[brd_id]);
+
+	/* Fix the ack in the bme 32 */
+	udelay(5000);
+	out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+	asm("eieio");
+
+
+	return (0);
+}
+
+/*************************************************************************
+ *  misc_init_f
+ *
+ *  Initialize I2C bus one to gain access to the fans
+ ************************************************************************/
+int misc_init_f (void)
+{
+	/* Turn on i2c bus 1 */
+	puts ("I2C1:  ");
+	i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	puts ("ready\n");
+
+	/* Turn on fans */
+	sbcommon_fans();
+
+	return (0);
+}
+
+/*************************************************************************
+ *  misc_init_r
+ *
+ *  Do nothing.
+ ************************************************************************/
+int misc_init_r (void)
+{
+	unsigned short sernum;
+	char envstr[255];
+	unsigned char opto_rev;
+	OPTO_FPGA_REGS_ST *opto_ps;
+
+	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+	if(NULL != getenv("secondserial")) {
+	    puts("secondserial is set, switching to second serial port\n");
+	    setenv("stderr", "serial1");
+	    setenv("stdout", "serial1");
+	    setenv("stdin", "serial1");
+	}
+
+	setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
+
+	memset(envstr, 0, 255);
+	sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+	setenv("bldstr", envstr);
+	saveenv();
+
+	if( getenv("autorecover")) {
+		setenv("autorecover", NULL);
+		saveenv();
+		sernum = sbcommon_get_serial_number();
+
+		printf("\nSetting up environment for automatic filesystem recovery\n");
+		/*
+		 * Setup default bootargs
+		 */
+		memset(envstr, 0, 255);
+		sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+			"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
+			sernum, sernum);
+		setenv("bootargs", envstr);
+
+		/*
+		 * Setup Default boot command
+		 */
+		setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
+		       "fatload ide 0 8100000 pramdisk;"
+		       "bootm 8000000 8100000");
+
+		printf("Done.  Please type allow the system to continue to boot\n");
+	}
+
+	if( getenv("fakeled")) {
+		setenv("bootdelay", "-1");
+		saveenv();
+		printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
+		opto_rev = (unsigned char)((opto_ps->revision_ul &
+					    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+					   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+
+		if(0x12 <= opto_rev) {
+			opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
+		}
+	}
+
+	return (0);
+}
+
+/*************************************************************************
+ *  ide_set_reset
+ ************************************************************************/
+#ifdef CONFIG_IDE_RESET
+void ide_set_reset(int on)
+{
+	OPTO_FPGA_REGS_ST *opto_ps;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+	if (on) {		/* assert RESET */
+	    opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
+	} else {		/* release RESET */
+	    opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
+	}
+}
+#endif /* CONFIG_IDE_RESET */
+
+/*************************************************************************
+ *  fpga_init
+ ************************************************************************/
+void fpga_init(void)
+{
+	OPTO_FPGA_REGS_ST *opto_ps;
+	unsigned char opto_rev;
+	unsigned long tmp;
+
+	/* Ensure we have power all around */
+	udelay(500);
+
+	/*
+	 * Take appropriate hw bits out of reset
+	 */
+	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+
+	tmp =
+	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
+	    SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
+	opto_ps->reset_ul = tmp;
+	/*
+	 * Turn on the 'Slow Blink' for the System Error Led.
+	 * Ensure FPGA rev is up to at least rev 0x12
+	 */
+	opto_rev = (unsigned char)((opto_ps->revision_ul &
+				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
+				   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
+	if(0x12 <= opto_rev) {
+	    opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
+	}
+
+	asm("eieio");
+
+	return;
+}
+
+int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	memset(envstr, 0, 255);
+	/*
+	 * Setup our ip address
+	 */
+	sprintf(envstr, "10.100.60.%d", sernum);
+
+	setenv("ipaddr", envstr);
+	/*
+	 * Setup the host ip address
+	 */
+	setenv("serverip", "10.100.17.10");
+
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
+		"rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
+		"nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
+		":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
+		sernum, sernum, sernum);
+
+	setenv("bootargs_nfs", envstr);
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup CF bootargs
+	 */
+	memset(envstr, 0, 255);
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
+		"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
+		sernum, sernum);
+
+	setenv("bootargs_cf", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+	setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
+	setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
+
+	/*
+	 * Setup compact flash boot command
+	 */
+	setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
+
+	saveenv();
+
+
+	return(1);
+}
+
+int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned short sernum;
+	char envstr[255];
+
+	sernum = sbcommon_get_serial_number();
+
+	printf("\nSetting up environment for filesystem recovery\n");
+	/*
+	 * Setup default bootargs
+	 */
+	memset(envstr, 0, 255);
+	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
+		"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
+		sernum, sernum);
+
+	setenv("bootargs", envstr);
+
+	/*
+	 * Setup Default boot command
+	 */
+	setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
+	       "fatload ide 0 8100000 pramdisk;"
+	       "bootm 8000000 8100000");
+
+	printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
+	       " please type fsrecover.sh<cr>\n");
+
+	return(1);
+}
+
+U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
+	   "mbsetup - Set environment to factory defaults\n", NULL);
+
+U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
+	   "mbrecover - Set environment to allow for fs recovery\n", NULL);
diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h
new file mode 100755
index 0000000..3f28f00
--- /dev/null
+++ b/board/sandburst/metrobox/metrobox.h
@@ -0,0 +1,45 @@
+#ifndef __METROBOX_H__
+#define __METROBOX_H__
+/*
+ * (C) Copyright 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+typedef struct metrobox_board_id_s {
+	const char name[40];
+} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST;
+
+
+/* Metrobox Opto-FPGA registers and definitions */
+#include "hal_xc_auto.h"
+typedef struct opto_fpga_regs_s {
+	volatile unsigned long revision_ul;	/* Read Only  */
+	volatile unsigned long reset_ul;	/* Read/Write */
+	volatile unsigned long status_ul;	/* Read Only  */
+	volatile unsigned long interrupt_ul;	/* Read Only  */
+	volatile unsigned long mask_ul;	/* Read/Write */
+	volatile unsigned long scratch_ul;	/* Read/Write */
+	volatile unsigned long scrmask_ul;	/* Read/Write */
+	volatile unsigned long control_ul;	/* Read/Write */
+	volatile unsigned long boardinfo_ul;	/* Read Only  */
+} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST;
+
+#endif /* __METROBOX_H__ */
diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h
new file mode 100755
index 0000000..1b6fee5
--- /dev/null
+++ b/board/sandburst/metrobox/metrobox_version.h
@@ -0,0 +1,27 @@
+#ifndef _METROBOX_VERSION_H_
+#define _METROBOX_VERSION_H_
+/*
+ * (C) Copyright 2005
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define METROBOX_U_BOOT_REL_STR "Release 2.0.3"
+
+#endif
diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds
new file mode 100755
index 0000000..a17401a
--- /dev/null
+++ b/board/sandburst/metrobox/u-boot.lds
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/sandburst/metrobox/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug
new file mode 100755
index 0000000..fef4c42
--- /dev/null
+++ b/board/sandburst/metrobox/u-boot.lds.debug
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/sandburst/metrobox/init.o (.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile
new file mode 100755
index 0000000..d6bbf2f
--- /dev/null
+++ b/board/sandpoint/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS =  $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sandpoint/README b/board/sandpoint/README
new file mode 100755
index 0000000..9e48168
--- /dev/null
+++ b/board/sandpoint/README
@@ -0,0 +1,15 @@
+This port of U-Boot will run on a Motorola Sandpoint 3 development
+system equipped with a Unity X4 PPMC card (MPC8240 CPU) only. It is a
+snapshot of work in progress and far from being completed. In order
+to run it on the target system, it has to be downloaded using the
+DINK32 monitor program that came with your Sandpoint system. Please
+note that DINK32 does not accept the S-Record file created by the
+U-Boot build process unmodified, because it contains CR/LF line
+terminators. You have to strip the CR characters first. There is a
+tiny script named 'dinkdl' I created for this purpose.
+
+The Sandpoint port is based on the work of Rob Taylor, who does not
+seem to maintain it any more. I can be reached by mail as
+tkoeller@gmx.net.
+
+Thomas Koeller
diff --git a/board/sandpoint/config.mk b/board/sandpoint/config.mk
new file mode 100755
index 0000000..b3f65eb
--- /dev/null
+++ b/board/sandpoint/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Sandpoint boards
+#
+
+#TEXT_BASE = 0x00090000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/sandpoint/dinkdl b/board/sandpoint/dinkdl
new file mode 100755
index 0000000..f281452
--- /dev/null
+++ b/board/sandpoint/dinkdl
@@ -0,0 +1,2 @@
+#! /bin/bash
+tr -d "\r" <$1 >/dev/tts/1
diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S
new file mode 100755
index 0000000..07dafb7
--- /dev/null
+++ b/board/sandpoint/early_init.S
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2001
+ * Thomas Koeller, tkoeller@gmx.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASSEMBLY__
+#define __ASSEMBLY__	1
+#endif
+
+#include <config.h>
+#include <asm/processor.h>
+#include <mpc824x.h>
+#include <ppc_asm.tmpl>
+
+#if defined(USE_DINK32)
+  /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
+  #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+#else
+  #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
+#endif
+
+	.text
+
+	/* Values to program into memory controller registers */
+tbl:	.long	MCCR1, MCCR1VAL
+	.long	MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR3
+	.long	(((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CFG_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	MCCR4
+	.long	(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CFG_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
+		(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	MSAR1
+	.long	(((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR1
+	.long	(((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MSAR2
+	.long	(((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMSAR2
+	.long	(((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR1
+	.long	(((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR1
+	.long	(((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	MEAR2
+	.long	(((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	EMEAR2
+	.long	(((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	0
+
+
+	/*
+	 * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
+	 * must be done in assembly, since we have no stack at this point.
+	 */
+	.global	early_init_f
+early_init_f:
+	mflr	r10
+
+	/* basic memory controller configuration */
+	lis	r3, CONFIG_ADDR_HIGH
+	lis	r4, CONFIG_DATA_HIGH
+	bl	lab
+lab:	mflr	r5
+	lwzu	r0, tbl - lab(r5)
+loop:	lwz	r1, 4(r5)
+	stwbrx	r0, 0, r3
+	eieio
+	stwbrx	r1, 0, r4
+	eieio
+	lwzu	r0, 8(r5)
+	cmpli	cr0, 0, r0, 0
+	bne	cr0, loop
+
+	/* set bank enable bits */
+	lis	r0, MBER@h
+	ori	r0, 0, MBER@l
+	li	r1, CFG_BANK_ENABLE
+	stwbrx	r0, 0, r3
+	eieio
+	stb	r1, 0(r4)
+	eieio
+
+	/* delay loop */
+	lis	r0, 0x0003
+	mtctr   r0
+delay:	bdnz	delay
+
+	/* enable memory controller */
+	lis	r0, MCCR1@h
+	ori	r0, 0, MCCR1@l
+	stwbrx	r0, 0, r3
+	eieio
+	lwbrx	r0, 0, r4
+	oris	r0, 0, MCCR1_MEMGO@h
+	stwbrx	r0, 0, r4
+	eieio
+
+	/* set up stack pointer */
+	lis	r1, CFG_INIT_SP_OFFSET@h
+	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+
+	mtlr	r10
+	blr
diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c
new file mode 100755
index 0000000..a9f73ff
--- /dev/null
+++ b/board/sandpoint/flash.c
@@ -0,0 +1,764 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+#include <w83c553f.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR  (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+#if 0
+static void flash_get_offsets (ulong base, flash_info_t *info);
+#endif /* 0 */
+
+/*flash command address offsets*/
+
+#if 0
+#define ADDR0           (0x555)
+#define ADDR1           (0x2AA)
+#define ADDR3           (0x001)
+#else
+#define ADDR0		(0xAAA)
+#define ADDR1		(0x555)
+#define ADDR3		(0x001)
+#endif
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+#if 0
+static int byte_parity_odd(unsigned char x) __attribute__ ((const));
+#endif /* 0 */
+static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const));
+
+typedef struct
+{
+  FLASH_WORD_SIZE extval;
+  unsigned short intval;
+} map_entry;
+
+#if 0
+static int
+byte_parity_odd(unsigned char x)
+{
+  x ^= x >> 4;
+  x ^= x >> 2;
+  x ^= x >> 1;
+  return (x & 0x1) != 0;
+}
+#endif /* 0 */
+
+
+static unsigned long
+flash_id(unsigned char mfct, unsigned char chip)
+{
+  static const map_entry mfct_map[] =
+    {
+      {(FLASH_WORD_SIZE) AMD_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
+      {(FLASH_WORD_SIZE) FUJ_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
+      {(FLASH_WORD_SIZE) STM_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
+      {(FLASH_WORD_SIZE) MT_MANUFACT,	(unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
+      {(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
+      {(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
+    };
+
+  static const map_entry chip_map[] =
+  {
+    {AMD_ID_F040B,	FLASH_AM040},
+    {(FLASH_WORD_SIZE) STM_ID_x800AB,	FLASH_STM800AB}
+  };
+
+  const map_entry *p;
+  unsigned long result = FLASH_UNKNOWN;
+
+  /* find chip id */
+  for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
+    if(p->extval == chip)
+    {
+      result = FLASH_VENDMASK | p->intval;
+      break;
+    }
+
+  /* find vendor id */
+  for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
+    if(p->extval == mfct)
+    {
+      result &= ~FLASH_VENDMASK;
+      result |= (unsigned long) p->intval << 16;
+      break;
+    }
+
+  return result;
+}
+
+
+unsigned long
+flash_init(void)
+{
+  unsigned long i;
+  unsigned char j;
+  static const ulong flash_banks[] = CFG_FLASH_BANKS;
+
+  /* Init: no FLASHes known */
+  for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+  {
+    flash_info_t * const pflinfo = &flash_info[i];
+    pflinfo->flash_id = FLASH_UNKNOWN;
+    pflinfo->size = 0;
+    pflinfo->sector_count = 0;
+  }
+
+  /* Enable writes to Sandpoint flash */
+  {
+    register unsigned char temp;
+    CONFIG_READ_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
+    temp &= ~0x20; /* clear BIOSWP bit */
+    CONFIG_WRITE_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
+  }
+
+  for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++)
+  {
+    flash_info_t * const pflinfo = &flash_info[i];
+    const unsigned long base_address = flash_banks[i];
+    volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address;
+#if 0
+    volatile FLASH_WORD_SIZE * addr2;
+#endif
+#if 0
+    /* write autoselect sequence */
+    flash[0x5555] = 0xaa;
+    flash[0x2aaa] = 0x55;
+    flash[0x5555] = 0x90;
+#else
+    flash[0xAAA << (3 * i)] = 0xaa;
+    flash[0x555 << (3 * i)] = 0x55;
+    flash[0xAAA << (3 * i)] = 0x90;
+#endif
+    __asm__ __volatile__("sync");
+
+#if 0
+    pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]);
+#else
+    pflinfo->flash_id = flash_id(flash[0x0], flash[0x2 + 14 * i]);
+#endif
+
+    switch(pflinfo->flash_id & FLASH_TYPEMASK)
+    {
+      case FLASH_AM040:
+	pflinfo->size = 0x00080000;
+	pflinfo->sector_count = 8;
+	for(j = 0; j < 8; j++)
+	{
+	  pflinfo->start[j] = base_address + 0x00010000 * j;
+	  pflinfo->protect[j] = flash[(j << 16) | 0x2];
+	}
+	break;
+      case FLASH_STM800AB:
+	pflinfo->size = 0x00100000;
+	pflinfo->sector_count = 19;
+	pflinfo->start[0] = base_address;
+	pflinfo->start[1] = base_address + 0x4000;
+	pflinfo->start[2] = base_address + 0x6000;
+	pflinfo->start[3] = base_address + 0x8000;
+	for(j = 1; j < 16; j++)
+	{
+	  pflinfo->start[j+3] = base_address + 0x00010000 * j;
+	}
+#if 0
+	/* check for protected sectors */
+	for (j = 0; j < pflinfo->sector_count; j++) {
+	  /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	  /* D0 = 1 if protected */
+	  addr2 = (volatile FLASH_WORD_SIZE *)(pflinfo->start[j]);
+	    if (pflinfo->flash_id & FLASH_MAN_SST)
+	      pflinfo->protect[j] = 0;
+	    else
+	      pflinfo->protect[j] = addr2[2] & 1;
+	}
+#endif
+	break;
+    }
+    /* Protect monitor and environment sectors
+     */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+    flash_protect(FLAG_PROTECT_SET,
+		CFG_MONITOR_BASE,
+		CFG_MONITOR_BASE + monitor_flash_len - 1,
+		&flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+    flash_protect(FLAG_PROTECT_SET,
+		CFG_ENV_ADDR,
+		CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		&flash_info[0]);
+#endif
+
+    /* reset device to read mode */
+    flash[0x0000] = 0xf0;
+    __asm__ __volatile__("sync");
+  }
+
+    return flash_info[0].size + flash_info[1].size;
+}
+
+#if 0
+static void
+flash_get_offsets (ulong base, flash_info_t *info)
+{
+    int i;
+
+    /* set up sector start address table */
+	if (info->flash_id & FLASH_MAN_SST)
+	  {
+	    for (i = 0; i < info->sector_count; i++)
+	      info->start[i] = base + (i * 0x00010000);
+	  }
+	else
+    if (info->flash_id & FLASH_BTYPE) {
+	/* set sector offsets for bottom boot block type    */
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00004000;
+	info->start[2] = base + 0x00006000;
+	info->start[3] = base + 0x00008000;
+	for (i = 4; i < info->sector_count; i++) {
+	    info->start[i] = base + (i * 0x00010000) - 0x00030000;
+	}
+    } else {
+	/* set sector offsets for top boot block type       */
+	i = info->sector_count - 1;
+	info->start[i--] = base + info->size - 0x00004000;
+	info->start[i--] = base + info->size - 0x00006000;
+	info->start[i--] = base + info->size - 0x00008000;
+	for (; i >= 0; i--) {
+	    info->start[i] = base + i * 0x00010000;
+	}
+    }
+
+}
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------
+ */
+void
+flash_print_info(flash_info_t *info)
+{
+  static const char unk[] = "Unknown";
+  const char *mfct = unk, *type = unk;
+  unsigned int i;
+
+  if(info->flash_id != FLASH_UNKNOWN)
+  {
+    switch(info->flash_id & FLASH_VENDMASK)
+    {
+      case FLASH_MAN_AMD:	mfct = "AMD";				break;
+      case FLASH_MAN_FUJ:	mfct = "FUJITSU";			break;
+      case FLASH_MAN_STM:	mfct = "STM";				break;
+      case FLASH_MAN_SST:	mfct = "SST";				break;
+      case FLASH_MAN_BM:	mfct = "Bright Microelectonics";	break;
+      case FLASH_MAN_INTEL:	mfct = "Intel";				break;
+    }
+
+    switch(info->flash_id & FLASH_TYPEMASK)
+    {
+      case FLASH_AM040:		type = "AM29F040B (512K * 8, uniform sector size)";	break;
+      case FLASH_AM400B:	type = "AM29LV400B (4 Mbit, bottom boot sect)";		break;
+      case FLASH_AM400T:	type = "AM29LV400T (4 Mbit, top boot sector)";		break;
+      case FLASH_AM800B:	type = "AM29LV800B (8 Mbit, bottom boot sect)";		break;
+      case FLASH_AM800T:	type = "AM29LV800T (8 Mbit, top boot sector)";		break;
+      case FLASH_AM160T:	type = "AM29LV160T (16 Mbit, top boot sector)";		break;
+      case FLASH_AM320B:	type = "AM29LV320B (32 Mbit, bottom boot sect)";	break;
+      case FLASH_AM320T:	type = "AM29LV320T (32 Mbit, top boot sector)";		break;
+      case FLASH_STM800AB:	type = "M29W800AB (8 Mbit, bottom boot sect)";		break;
+      case FLASH_SST800A:	type = "SST39LF/VF800 (8 Mbit, uniform sector size)";	break;
+      case FLASH_SST160A:	type = "SST39LF/VF160 (16 Mbit, uniform sector size)";	break;
+    }
+  }
+
+  printf(
+    "\n  Brand: %s Type: %s\n"
+    "  Size: %lu KB in %d Sectors\n",
+    mfct,
+    type,
+    info->size >> 10,
+    info->sector_count
+  );
+
+  printf ("  Sector Start Addresses:");
+
+  for (i = 0; i < info->sector_count; i++)
+  {
+    unsigned long size;
+    unsigned int erased;
+    unsigned long * flash = (unsigned long *) info->start[i];
+
+    /*
+     * Check if whole sector is erased
+     */
+    size =
+      (i != (info->sector_count - 1)) ?
+      (info->start[i + 1] - info->start[i]) >> 2 :
+      (info->start[0] + info->size - info->start[i]) >> 2;
+
+    for(
+      flash = (unsigned long *) info->start[i], erased = 1;
+      (flash != (unsigned long *) info->start[i] + size) && erased;
+      flash++
+    )
+      erased = *flash == ~0x0UL;
+
+    printf(
+      "%s %08lX %s %s",
+      (i % 5) ? "" : "\n   ",
+      info->start[i],
+      erased ? "E" : " ",
+      info->protect[i] ? "RO" : "  "
+    );
+  }
+
+  puts("\n");
+  return;
+}
+
+#if 0
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong
+flash_get_size (vu_long *addr, flash_info_t *info)
+{
+   short i;
+    FLASH_WORD_SIZE value;
+    ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+    printf("flash_get_size: \n");
+    /* Write auto select command: read Manufacturer ID */
+    eieio();
+    addr2[ADDR0] = (FLASH_WORD_SIZE)0xAA;
+    addr2[ADDR1] = (FLASH_WORD_SIZE)0x55;
+    addr2[ADDR0] = (FLASH_WORD_SIZE)0x90;
+    value = addr2[0];
+
+    switch (value) {
+    case (FLASH_WORD_SIZE)AMD_MANUFACT:
+	info->flash_id = FLASH_MAN_AMD;
+	break;
+    case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+	info->flash_id = FLASH_MAN_FUJ;
+	break;
+    case (FLASH_WORD_SIZE)SST_MANUFACT:
+	info->flash_id = FLASH_MAN_SST;
+	break;
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	info->sector_count = 0;
+	info->size = 0;
+	return (0);         /* no or unknown flash  */
+    }
+    printf("recognised manufacturer");
+
+    value = addr2[ADDR3];          /* device ID        */
+	debug ("\ndev_code=%x\n", value);
+
+    switch (value) {
+    case (FLASH_WORD_SIZE)AMD_ID_LV400T:
+	info->flash_id += FLASH_AM400T;
+	info->sector_count = 11;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB        */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV400B:
+	info->flash_id += FLASH_AM400B;
+	info->sector_count = 11;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB        */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV800T:
+	info->flash_id += FLASH_AM800T;
+	info->sector_count = 19;
+	info->size = 0x00100000;
+	break;              /* => 1 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV800B:
+	info->flash_id += FLASH_AM800B;
+	info->sector_count = 19;
+	info->size = 0x00100000;
+	break;              /* => 1 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV160T:
+	info->flash_id += FLASH_AM160T;
+	info->sector_count = 35;
+	info->size = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_LV160B:
+	info->flash_id += FLASH_AM160B;
+	info->sector_count = 35;
+	info->size = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)SST_ID_xF800A:
+	info->flash_id += FLASH_SST800A;
+	info->sector_count = 16;
+	info->size = 0x00100000;
+	break;              /* => 1 MB      */
+
+    case (FLASH_WORD_SIZE)SST_ID_xF160A:
+	info->flash_id += FLASH_SST160A;
+	info->sector_count = 32;
+	info->size = 0x00200000;
+	break;              /* => 2 MB      */
+
+    case (FLASH_WORD_SIZE)AMD_ID_F040B:
+	info->flash_id += FLASH_AM040;
+	info->sector_count = 8;
+	info->size = 0x00080000;
+	break;              /* => 0.5 MB      */
+
+    default:
+	info->flash_id = FLASH_UNKNOWN;
+	return (0);         /* => no or unknown flash */
+
+    }
+
+    printf("flash id %lx; sector count %x, size %lx\n", info->flash_id,info->sector_count,info->size);
+    /* set up sector start address table */
+	if (info->flash_id & FLASH_MAN_SST)
+	  {
+	    for (i = 0; i < info->sector_count; i++)
+	      info->start[i] = base + (i * 0x00010000);
+	  }
+	else
+    if (info->flash_id & FLASH_BTYPE) {
+	/* set sector offsets for bottom boot block type    */
+	info->start[0] = base + 0x00000000;
+	info->start[1] = base + 0x00004000;
+	info->start[2] = base + 0x00006000;
+	info->start[3] = base + 0x00008000;
+	for (i = 4; i < info->sector_count; i++) {
+	    info->start[i] = base + (i * 0x00010000) - 0x00030000;
+	}
+    } else {
+	/* set sector offsets for top boot block type       */
+	i = info->sector_count - 1;
+	info->start[i--] = base + info->size - 0x00004000;
+	info->start[i--] = base + info->size - 0x00006000;
+	info->start[i--] = base + info->size - 0x00008000;
+	for (; i >= 0; i--) {
+	    info->start[i] = base + i * 0x00010000;
+	}
+    }
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if (info->flash_id & FLASH_MAN_SST)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[2] & 1;
+    }
+
+    /*
+     * Prevent writes to uninitialized FLASH.
+     */
+    if (info->flash_id != FLASH_UNKNOWN) {
+       addr2 = (FLASH_WORD_SIZE *)info->start[0];
+	*addr2 = (FLASH_WORD_SIZE)0x00F000F0;   /* reset bank */
+    }
+
+    return (info->size);
+}
+
+#endif
+
+
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+    volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+    unsigned char sh8b;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    if ((info->flash_id == FLASH_UNKNOWN) ||
+	(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+	    prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Check the ROM CS */
+    if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START))
+      sh8b = 3;
+    else
+      sh8b = 0;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) { /* not protected */
+	    addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+				(info->start[sect] - info->start[0]) << sh8b));
+			if (info->flash_id & FLASH_MAN_SST)
+			  {
+			    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+			    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
+			    addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+			    addr[0] = (FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			    udelay(30000);  /* wait 30 ms */
+			  }
+			else
+			  addr[0] = (FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+	goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (FLASH_WORD_SIZE *)(info->start[0] + (
+			(info->start[l_sect] - info->start[0]) << sh8b));
+    while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {  /* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+DONE:
+    /* reset to read mode */
+    addr = (FLASH_WORD_SIZE *)info->start[0];
+    addr[0] = (FLASH_WORD_SIZE)0x00F000F0;  /* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);   /* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+    ulong start;
+    int flag;
+	int i;
+    unsigned char sh8b;
+
+    /* Check the ROM CS */
+    if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START))
+      sh8b = 3;
+    else
+      sh8b = 0;
+
+    dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) +
+				info->start[0]);
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
+	    addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
+
+	    dest2[i << sh8b] = data2[i];
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();
+
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }
+
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c
new file mode 100755
index 0000000..d3445bd
--- /dev/null
+++ b/board/sandpoint/sandpoint.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Sandpoint "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" Unity ##Test not implemented yet##\n");
+	return 0;
+}
+
+#if 0 	/* NOT USED */
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("## Test not implemented yet ##\n");
+
+	return (0);
+}
+#endif
+
+long int initdram (int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_sandpoint_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_sandpoint_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h
new file mode 100755
index 0000000..b66393b
--- /dev/null
+++ b/board/sandpoint/speed.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK	      		CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */
diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds
new file mode 100755
index 0000000..2a5cd2e
--- /dev/null
+++ b/board/sandpoint/u-boot.lds
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile
new file mode 100755
index 0000000..c4198c4
--- /dev/null
+++ b/board/sbc405/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o strataflash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sbc405/config.mk b/board/sbc405/config.mk
new file mode 100755
index 0000000..bd57217
--- /dev/null
+++ b/board/sbc405/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000, 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Wind River sbc405 boards
+#
+
+TEXT_BASE = 0xFFFC0000
diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c
new file mode 100755
index 0000000..cad5873
--- /dev/null
+++ b/board/sbc405/sbc405.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2001
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <command.h>
+#include <malloc.h>
+#include <spd_sdram.h>
+
+
+int board_early_init_f (void)
+{
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 */
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+	mtdcr(uicer, 0x00000000);       /* disable all ints */
+	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
+	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+
+	/*
+	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+	 */
+	mtebc (epcr, 0xa8400000);
+
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_f (void)
+{
+	return 0;  /* dummy implementation */
+}
+
+
+int misc_init_r (void)
+{
+	return (0);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming sbc405");
+	} else {
+		puts(str);
+	}
+
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	return  spd_sdram (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("test: 64 MB - ok\n");
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c
new file mode 100755
index 0000000..d21d885
--- /dev/null
+++ b/board/sbc405/strataflash.c
@@ -0,0 +1,793 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+
+#define FLASH_MAN_CFI			0x01000000
+
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	unsigned char * cp;
+	unsigned short *wp;
+	unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+	unsigned long  address;
+
+
+	/* The flash is positioned back to back, with the demultiplexing of the chip
+	 * based on the A24 address line.
+	 *
+	 */
+
+	address = CFG_FLASH_BASE;
+	size = 0;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(address, i);
+		address += CFG_FLASH_INCREMENT;
+		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+				flash_info[0].size, flash_info[i].size<<20);
+		}
+	}
+
+#if 0 /* test-only */
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+		(void)flash_real_protect(&flash_info[0], i, 1);
+#endif
+#else
+	/* monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       - CFG_MONITOR_LEN,
+		       - 1, &flash_info[1]);
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		int k;
+		int size;
+		int erased;
+		volatile unsigned long *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+			retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+#ifdef DEBUG_FLASH
+		printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
+#endif
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/sbc405/u-boot.lds b/board/sbc405/u-boot.lds
new file mode 100755
index 0000000..39fba61
--- /dev/null
+++ b/board/sbc405/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sbc8240/Makefile b/board/sbc8240/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/sbc8240/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sbc8240/README b/board/sbc8240/README
new file mode 100755
index 0000000..71595b4
--- /dev/null
+++ b/board/sbc8240/README
@@ -0,0 +1,140 @@
+The supported features of the SBC8240/8245 board are:
+    8240 or 8245 processor
+    66MHz & 100MHz bus speed
+    Decrementer timer
+    1 UART channel (Console channel)
+    8240 Interrupt Controller
+    8240 PCI bridge
+    8240 Memory Controller
+    SDRAM (16, 64 MB Memory DIMM)
+    FLASH 512K On board
+    FLASH 4MB On board
+
+
+Memory Map from CPU point of view:
+
+    Start	 Size	Access to
+    -----------------------------------------------------
+    0x00000000	 64MB	SDRAM DIMM
+    0xFF000000	  4MB	On Board FLASH
+    0xFFF00000	512K	On Board FLASH or SRAM (Configured by jumper)
+    0xFFE00000	  8K	EEPROM
+    0xFFE80000	  8Bit	LED
+    0xFFF80000	  8Bit	UART
+
+
+Setting the board Jumpers & Switches:
+
+   In order to get the board running with the default configuration the
+   jumpers need to be set as follows:
+
+  General Jumpers:
+    ____________________________________________
+   |   Jumpers	 |   Jumpers	|    Jumpers	|
+   |-------------|--------------|---------------|
+   |JP1	    1-2	 | JP14	   1-2	| JP27	  1-2	|
+   |JP5	    Open | JP15	   1-2	| JP28	  2-3	|
+   |JP8	    1-2	 | JP16	   1-2	| JP33	  Open	|
+   |JP9	    1-2	 | JP17	   1-2	| JP37	  Close |
+   |JP10    1-2	 | JP18	   1-2	|		|
+   |JP11    2-3	 | JP19	   1-2	|		|
+   |JP12    1-2	 | JP20	   1-2	|		|
+   |JP13    1-2	 | JP25	   Open |		|
+   |_____________|______________|_______________|
+
+  Bus speed Jumpers:
+    _________________________
+   | 100MHz Bus | 66 MHz Bus |
+   |------------|------------|
+   | JP2    1-2 | JP2	 1-2 |
+   | JP3    1-2 | JP3	 2-3 |
+   | JP4    1-2 | JP4	 2-3 |
+   | JP6    1-2 | JP6	 2-3 |
+   | JP7    1-2 | JP7	 1-2 |
+   |____________|____________|
+
+
+U-Boot 1.1.2 (Jun 24 2004 - 17:01:04)
+
+CPU:   MPC8240 Revision 1.1 at 247.500 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: sbc8240 Revision 255 Local Bus at 99 MHz
+DRAM:  64 MB
+FLASH: 512 kB
+	00  11	8086  1229  0200  00
+In:    serial
+Out:   serial
+Err:   serial
+Net:   i82559#0
+
+Welcome to U-Boot for the sbc8240
+
+Type ? or help to get on-line help
+
+Hit any key to stop autoboot:  0
+=> printenv
+bootcmd=version;echo;tftpboot $loadaddr $loadfile;bootvx
+bootdelay=5
+baudrate=9600
+ethaddr=DE:AD:BE:EF:01:01
+ipaddr=192.168.193.102
+preboot=echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type "? or help" to get on-line help;echo
+netmask=255.255.255.248
+clocks_in_mhz=1
+bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei
+ipaddr=192.168.193.102
+loadfile=vxWorks.st
+loadaddr=0x01000000
+net_load=tftpboot $loadaddr $loadfile
+serverip=192.168.193.99
+ethact=i82559#0
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 631/16380 bytes
+=> boot
+
+U-Boot 1.1.2 (Jun 24 2004 - 17:01:04)
+
+Using i82559#0 device
+TFTP from server 192.168.193.99; our IP address is 192.168.193.102
+Filename 'vxWorks.st'.
+Load address: 0x1000000
+Loading: #################################################################
+	 #################################################################
+	 ##############################################################
+done
+Bytes transferred = 979927 (ef3d7 hex)
+## Ethernet MAC address not copied to NV RAM
+Loading .text @ 0x00100000 (758848 bytes)
+Loading .data @ 0x001b9440 (79904 bytes)
+Clearing .bss @ 0x001ccc60 (20288 bytes)
+## Using bootline (@ 0x4200): $fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 tn=sbc8240 o=fei
+## Starting vxWorks at 0x00100000 ...
+
+Adding 2845 symbols for standalone.
+
+
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+      ]]]]]]]]]]]  ]]]]	    ]]]]]]]]]]	     ]]		     ]]]]	  (R)
+ ]     ]]]]]]]]]  ]]]]]]     ]]]]]]]]	    ]]		     ]]]]
+ ]]	]]]]]]]	 ]]]]]]]]     ]]]]]] ]	   ]]		     ]]]]
+ ]]]	 ]]]]] ]    ]]]	 ]     ]]]] ]]]	  ]]]]]]]]]  ]]]] ]] ]]]]  ]]	]]]]]
+ ]]]]	  ]]]  ]]    ]	]]]	]] ]]]]] ]]]]]]	  ]] ]]]]]]] ]]]] ]]   ]]]]
+ ]]]]]	   ]  ]]]]     ]]]]]	  ]]]]]]]] ]]]]	  ]] ]]]]    ]]]]]]]	]]]]
+ ]]]]]]	     ]]]]]     ]]]]]]	 ]  ]]]]]  ]]]]	  ]] ]]]]    ]]]]]]]]	 ]]]]
+ ]]]]]]]    ]]]]]  ]	]]]]]]	]    ]]]   ]]]]	  ]] ]]]]    ]]]] ]]]]	  ]]]]
+ ]]]]]]]]  ]]]]]  ]]]	 ]]]]]]]      ]	    ]]]]]]]  ]]]]    ]]]]  ]]]] ]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]	     Development System
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]]
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]]	   VxWorks version 5.5.1
+ ]]]]]]]]]]]]]]]]]]]]]]]]]]	  KERNEL: WIND version 2.6
+ ]]]]]]]]]]]]]]]]]]]]]]]]]	 Copyright Wind River Systems, Inc., 1984-2003
+
+			       CPU: MPC8240 -- Wind River BSP. SBC8240 Board.  Processor #0.
+			      Memory Size: 0x2000000.  BSP version 1.2/28.
+
+->
diff --git a/board/sbc8240/config.mk b/board/sbc8240/config.mk
new file mode 100755
index 0000000..1e97960
--- /dev/null
+++ b/board/sbc8240/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# sbc8240 board
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/sbc8240/flash.c b/board/sbc8240/flash.c
new file mode 100755
index 0000000..dec6156
--- /dev/null
+++ b/board/sbc8240/flash.c
@@ -0,0 +1,638 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#if CFG_MAX_FLASH_BANKS != 1
+#error "CFG_MAX_FLASH_BANKS must be 1"
+#endif
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info);
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+#define ADDR0           0x5555
+#define ADDR1           0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+
+	/* Init: no FLASHes known */
+	flash_info[0].flash_id = FLASH_UNKNOWN;
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	/* Setup offsets */
+	flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+			      FLASH_BASE0_PRELIM,
+			      FLASH_BASE0_PRELIM + monitor_flash_len - 1,
+			      &flash_info[0]);
+	flash_info[0].size = size_b0;
+
+	return size_b0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:
+		printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:
+		printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *) info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ", info->protect[i] ? "RO " : "   "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long * addr, flash_info_t * info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
+
+	value = addr2[0];
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE) FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE) SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+
+	switch (value) {
+	case (FLASH_WORD_SIZE) AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
+	case (FLASH_WORD_SIZE) AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;		/* => 0.5 MB            */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+#if 0				/* enable when device IDs are available */
+	case (FLASH_WORD_SIZE) AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#endif
+	case (FLASH_WORD_SIZE) SST_ID_xF800A:
+		info->flash_id += FLASH_SST800A;
+		info->sector_count = 16;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (FLASH_WORD_SIZE) SST_ID_xF160A:
+		info->flash_id += FLASH_SST160A;
+		info->sector_count = 32;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    (info->flash_id == FLASH_AM040)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type           */
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (FLASH_WORD_SIZE *) info->start[0];
+		*addr2 = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7 (flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr =
+		(FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer (0);
+	last = start;
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+	       (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+			printf ("Erasing sector %p\n", addr2);	/* CLH */
+
+			if ((info->flash_id & FLASH_VENDMASK) ==
+			    FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				for (i = 0; i < 50; i++)
+					udelay (1000);	/* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7 (info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7 (info, l_sect);
+
+      DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 =
+		(FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c
new file mode 100755
index 0000000..a6d3bab
--- /dev/null
+++ b/board/sbc8240/sbc8240.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <pci.h>
+
+#define BOARD_REV_REG 0xFE80002B
+
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char  revision = *(volatile char *)(BOARD_REV_REG);
+	char  buf[32];
+
+	puts ("Board: sbc8240 ");
+	printf("Revision %d ", revision);
+	printf("Local Bus at %s MHz\n", strmhz(buf, gd->bus_clk));
+
+	return 0;
+}
+
+long int initdram(int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1,  mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_sandpoint_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_sandpoint_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r (void)
+{
+#ifdef CFG_LED_BASE
+	*((unsigned char *) (CFG_LED_BASE)) = 0xFF;
+#endif /* CFG_LED_BASE */
+
+	return (0);
+}
+#endif /* CONFIG_MISC_INIT_R */
diff --git a/board/sbc8240/u-boot.lds b/board/sbc8240/u-boot.lds
new file mode 100755
index 0000000..7be85e4
--- /dev/null
+++ b/board/sbc8240/u-boot.lds
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o (.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+		. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+		*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sbc8260/Makefile b/board/sbc8260/Makefile
new file mode 100755
index 0000000..14ed457
--- /dev/null
+++ b/board/sbc8260/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= sbc8260.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sbc8260/config.mk b/board/sbc8260/config.mk
new file mode 100755
index 0000000..1f18260
--- /dev/null
+++ b/board/sbc8260/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MBX8xx boards
+#
+
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/sbc8260/flash.c b/board/sbc8260/flash.c
new file mode 100755
index 0000000..9a8b952
--- /dev/null
+++ b/board/sbc8260/flash.c
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2000
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AMD 29F080B devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    unsigned long size;
+    int i;
+
+    /* Init: no FLASHes known */
+    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* for now, only support the 4 MB Flash SIMM */
+    size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]);
+
+    /*
+     * protect monitor and environment sectors
+     */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_MONITOR_BASE,
+		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_ENV_ADDR,
+		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+
+    return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch ((info->flash_id >> 16) & 0xff) {
+    case 0x1:
+	printf ("AMD ");
+	break;
+    default:
+	printf ("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case AMD_ID_F040B:
+	printf ("AM29F040B (4 Mbit)\n");
+	break;
+    case AMD_ID_F080B:
+	printf ("AM29F080B (8 Mbit)\n");
+	break;
+    default:
+	printf ("Unknown Chip Type\n");
+	break;
+    }
+
+    printf ("  Size: %ld MB in %d Sectors\n",
+	    info->size >> 20, info->sector_count);
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	if ((i % 5) == 0)
+	  printf ("\n   ");
+	printf (" %08lX%s",
+		info->start[i],
+		info->protect[i] ? " (RO)" : "     "
+		);
+    }
+    printf ("\n");
+    return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    vu_long vendor, devid;
+    ulong base = (ulong)addr;
+
+/*    printf("addr   = %08lx\n", (unsigned long)addr); */
+
+    /* Reset and Write auto select command: read Manufacturer ID */
+    addr[0] = 0xf0f0f0f0;
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x90909090;
+    udelay (1000);
+
+    vendor = addr[0];
+/*    printf("vendor = %08lx\n", vendor); */
+    if (vendor != 0x01010101) {
+	info->size = 0;
+	goto out;
+    }
+
+    devid = addr[1];
+/*    printf("devid  = %08lx\n", devid); */
+
+    if ((devid & 0xff) == AMD_ID_F080B) {
+	info->flash_id     = (vendor & 0xff) << 16 | AMD_ID_F080B;
+	/* we have 16 sectors with 64KB each x 4 */
+	info->sector_count = 16;
+	info->size         = 4 * info->sector_count * 64*1024;
+    }
+    else {
+	info->size = 0;
+	goto out;
+    }
+
+    /* check for protected sectors */
+    for (i = 0; i < info->sector_count; i++) {
+	/* sector base address */
+	info->start[i] = base + i * (info->size / info->sector_count);
+	/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+	/* D0 = 1 if protected */
+	addr = (volatile unsigned long *)(info->start[i]);
+	info->protect[i] = addr[2] & 1;
+    }
+
+    /* reset command */
+    addr = (vu_long *)info->start[0];
+
+out:
+    addr[0] = 0xf0f0f0f0;
+
+    return info->size;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    int flag, prot, sect, l_sect;
+    ulong start, now, last;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN) {
+	    printf ("- missing\n");
+	} else {
+	    printf ("- no sectors to erase\n");
+	}
+	return 1;
+    }
+
+    prot = 0;
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+
+    if (prot) {
+	printf ("- Warning: %d protected sectors will not be erased!\n",
+		prot);
+    } else {
+	printf ("\n");
+    }
+
+    l_sect = -1;
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0x80808080;
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    udelay (100);
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last; sect++) {
+	if (info->protect[sect] == 0) {	/* not protected */
+	    addr = (vu_long*)(info->start[sect]);
+	    addr[0] = 0x30303030;
+	    l_sect = sect;
+	}
+    }
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /*
+     * We wait for the last triggered sector
+     */
+    if (l_sect < 0)
+      goto DONE;
+
+    start = get_timer (0);
+    last  = start;
+    addr = (vu_long*)(info->start[l_sect]);
+    while ((addr[0] & 0x80808080) != 0x80808080) {
+	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	    printf ("Timeout\n");
+	    return 1;
+	}
+	/* show that we're waiting */
+	if ((now - last) > 1000) {	/* every second */
+	    serial_putc ('.');
+	    last = now;
+	}
+    }
+
+    DONE:
+    /* reset to read mode */
+    addr = (volatile unsigned long *)info->start[0];
+    addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+    printf (" done\n");
+    return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int i, l, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long*)(info->start[0]);
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*((vu_long *)dest) & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    addr[0x0555] = 0xAAAAAAAA;
+    addr[0x02AA] = 0x55555555;
+    addr[0x0555] = 0xA0A0A0A0;
+
+    *((vu_long *)dest) = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+      enable_interrupts();
+
+    /* data polling for D7 */
+    start = get_timer (0);
+    while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    return (1);
+	}
+    }
+    return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c
new file mode 100755
index 0000000..48aefa0
--- /dev/null
+++ b/board/sbc8260/sbc8260.c
@@ -0,0 +1,289 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTCA   */
+	/* PA29 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTSOC  */
+	/* PA28 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   1,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   1,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   1,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   1,   0,   0,   1,   0,   0   }, /* PB17 */
+	/* PB16 */ {   1,   0,   0,   1,   0,   0   }, /* PB16 */
+	/* PB15 */ {   1,   0,   0,   1,   0,   0   }, /* PB15 */
+	/* PB14 */ {   1,   0,   0,   1,   0,   0   }, /* PB14 */
+	/* PB13 */ {   1,   0,   0,   1,   0,   0   }, /* PB13 */
+	/* PB12 */ {   1,   0,   0,   1,   0,   0   }, /* PB12 */
+	/* PB11 */ {   1,   0,   0,   1,   0,   0   }, /* PB11 */
+	/* PB10 */ {   1,   0,   0,   1,   0,   0   }, /* PB10 */
+	/* PB9  */ {   1,   0,   0,   1,   0,   0   }, /* PB9 */
+	/* PB8  */ {   1,   0,   0,   1,   0,   0   }, /* PB8 */
+	/* PB7  */ {   1,   0,   0,   1,   0,   0   }, /* PB7 */
+	/* PB6  */ {   1,   0,   0,   1,   0,   0   }, /* PB6 */
+	/* PB5  */ {   1,   0,   0,   1,   0,   0   }, /* PB5 */
+	/* PB4  */ {   1,   0,   0,   1,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   1,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   1,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   1,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   1,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   1,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   1,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   1,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   1,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   1,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   1,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   1,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   1,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   1,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   1,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   1,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+	/* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+	/* PC8  */ {   1,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   1,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   1,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   1,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   1,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   1,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   1,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   1,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   1,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   1,   0,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   1,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   1,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   1,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   1,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   1,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   1,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   1,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   1,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   0,   0,   1,   0,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   0,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   1,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   1,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   1,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   1,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   1,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   1,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   1,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   1,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: EST SBC8260\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
+	ulong psdmr = CFG_PSDMR;
+	int i;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+	*ramaddr = c;
+
+	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*ramaddr = c;
+
+	/* return total ram size */
+	return (CFG_SDRAM0_SIZE * 1024 * 1024);
+}
+
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+int misc_init_r (void)
+{
+#ifdef CFG_LED_BASE
+	uchar ds = *(unsigned char *) (CFG_LED_BASE + 1);
+	uchar ss;
+	uchar tmp[64];
+	int res;
+
+	if ((ds != 0) && (ds != 0xff)) {
+		res = getenv_r ("ethaddr", tmp, sizeof (tmp));
+		if (res > 0) {
+			ss = ((ds >> 4) & 0x0f);
+			ss += ss < 0x0a ? '0' : ('a' - 10);
+			tmp[15] = ss;
+
+			ss = (ds & 0x0f);
+			ss += ss < 0x0a ? '0' : ('a' - 10);
+			tmp[16] = ss;
+
+			tmp[17] = '\0';
+			setenv ("ethaddr", tmp);
+			/* set the led to show the address */
+			*((unsigned char *) (CFG_LED_BASE + 1)) = ds;
+		}
+	}
+#endif /* CFG_LED_BASE */
+	return (0);
+}
+#endif /* CONFIG_MISC_INIT_R */
diff --git a/board/sbc8260/u-boot.lds b/board/sbc8260/u-boot.lds
new file mode 100755
index 0000000..9e623d0
--- /dev/null
+++ b/board/sbc8260/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile
new file mode 100755
index 0000000..da295fb
--- /dev/null
+++ b/board/sbc8560/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8560 board
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sbc8560/config.mk b/board/sbc8560/config.mk
new file mode 100755
index 0000000..6d9ae45
--- /dev/null
+++ b/board/sbc8560/config.mk
@@ -0,0 +1,33 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+# Added support for Wind River SBC8560 board
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+# based on mpc8560ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 256K
+#
+TEXT_BASE = 0xfffc0000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S
new file mode 100755
index 0000000..3d8d180
--- /dev/null
+++ b/board/sbc8560/init.S
@@ -0,0 +1,165 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+* Added support for Wind River SBC8560 board
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(512M) -or- larger
+ * c000_0000-cfff_ffff: PCI(256M)
+ * d000_0000-dfff_ffff: RapidIO(256M)
+ * e000_0000-ffff_ffff: localbus(512M)
+ *   e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
+ *   e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
+ *   e800_0000-efff_ffff: LBC 128M, nothing here
+ *   f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
+ *   f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
+ *   f800_0000-fdff_ffff: LBC 64M, nothing here
+ *   fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
+ *   fd00_0000-fdff_ffff: LBC 16M, nothing here
+ *   fe00_0000-feff_ffff: LBC 16M, nothing here
+ *   ff00_0000-ff6f_ffff: LBC 7M, nothing here
+ *   ff70_0000-ff7f_ffff: CCSRBAR 1M
+ *   ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+  #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+  #define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#else
+  #define LAWBAR0 0
+  #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR2 ((0xe0000000>>12) & 0xfffff)
+#define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+	.section .bootpg, "ax"
+	.globl  law_entry
+law_entry:
+	entry_start
+	.long 0x03
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	entry_end
+
+/* TLB1 entries configuration: */
+
+	.section	.bootpg, "ax"
+	.globl		tlb1_entry
+
+tlb1_entry:
+	entry_start
+
+	.long 0x08	/* the following data table uses a few of 16 TLB entries */
+
+/* TLB for CCSRBAR (IMMR) */
+
+	.long TLB1_MAS0(1,1,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+/* TLB for Local Bus stuff, just map the whole 512M */
+/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
+
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+#else
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+#endif
+
+	.long TLB1_MAS0(1,6,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+#ifdef CONFIG_L2_INIT_RAM
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+#else
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+#endif
+	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,7,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+#else
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+#endif
+	entry_end
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
new file mode 100755
index 0000000..e8b9929
--- /dev/null
+++ b/board/sbc8560/sbc8560.c
@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+ * Added support for Wind River SBC8560 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+
+long int fixed_sdram (void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
+	/* PD27 */ {   1,   1,   1,   1,   0,   0   }, /* SCC2 TxD */
+	/* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+int board_early_init_f (void)
+{
+#if defined(CONFIG_PCI)
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+    pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+	volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR;
+#endif
+	/* reset Giga bit Ethernet port if needed here */
+
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr[0] &= ~0x20;
+	udelay(2);
+	bcsr[0] |= 0x20;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr[0] &= ~0x10;
+	udelay(2);
+	bcsr[0] |= 0x10;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	/* reset PHY */
+	miiphy_reset("FCC1 ETHERNET", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info (&sysinfo);
+
+#ifdef CONFIG_SBC8560
+	printf ("Board: Wind River SBC8560 Board\n");
+#else
+	printf ("Board: Wind River SBC8540 Board\n");
+#endif
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+		|| (CFG_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+	} else {
+		printf("\tLBC: unknown\n");
+	}
+	printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if 0
+#if !defined(CONFIG_RAM_AS_FLASH)
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	sys_info_t sysinfo;
+	uint temp_lbcdll = 0;
+#endif
+#endif /* 0 */
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+	volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+	uint temp_ddrdll = 0;
+
+	/* Work around to stabilize DDR DLL */
+	temp_ddrdll = gur->ddrdllcr;
+	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if 0
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
+	get_sys_info(&sysinfo);
+	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	} else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		udelay(200);
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+#endif
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	{
+		/* Initialize all of memory for ECC, then
+		 * enable errors */
+		uint *p = 0;
+		uint i = 0;
+		volatile immap_t *immap = (immap_t *)CFG_IMMR;
+		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		dma_init();
+		for (*p = 0; p < (uint *)(8 * 1024); p++) {
+			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+			*p = (unsigned int)0xdeadbeef;
+			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+		}
+
+		/* 8K */
+		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+		/* 16K */
+		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+		/* 32K */
+		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+		/* 64K */
+		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+		/* 128k */
+		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+		/* 256k */
+		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+		/* 512k */
+		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+		/* 1M */
+		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+		/* 2M */
+		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+		/* 4M */
+		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+		for (i = 1; i < dram_size / 0x800000; i++) {
+			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+		}
+
+		/* Enable errors for ECC */
+		ddr->err_disable = 0x00000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+
+#define CFG_DDR_CONTROL 0xc2000000
+
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds		= 0x00000007;
+	ddr->cs1_bnds		= 0x0010001f;
+	ddr->cs2_bnds		= 0x00000000;
+	ddr->cs3_bnds		= 0x00000000;
+	ddr->cs0_config		= 0x80000102;
+	ddr->cs1_config		= 0x80000102;
+	ddr->cs2_config		= 0x00000000;
+	ddr->cs3_config		= 0x00000000;
+	ddr->timing_cfg_1	= 0x37334321;
+	ddr->timing_cfg_2	= 0x00000800;
+	ddr->sdram_cfg		= 0x42000000;
+	ddr->sdram_mode		= 0x00000022;
+	ddr->sdram_interval	= 0x05200100;
+	ddr->err_sbe		= 0x00ff0000;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds
new file mode 100755
index 0000000..48e19fe
--- /dev/null
+++ b/board/sbc8560/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+ * Added support for Wind River SBC8560 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/sbc8560/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/sbc8560/init.o (.text)
+    cpu/mpc85xx/commproc.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/serial_scc.o (.text)
+    cpu/mpc85xx/ether_fcc.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/i2c.o (.text)
+    cpu/mpc85xx/spd_sdram.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile
new file mode 100755
index 0000000..ab06ebc
--- /dev/null
+++ b/board/sc520_cdp/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= sc520_cdp.o flash.o
+SOBJS	:= sc520_cdp_asm.o sc520_cdp_asm16.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sc520_cdp/config.mk b/board/sc520_cdp/config.mk
new file mode 100755
index 0000000..2253815
--- /dev/null
+++ b/board/sc520_cdp/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+TEXT_BASE = 0x387c0000
diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c
new file mode 100755
index 0000000..d52a847
--- /dev/null
+++ b/board/sc520_cdp/flash.c
@@ -0,0 +1,637 @@
+/*
+ * (C) Copyright 2002, 2003
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <asm/ic/sc520.h>
+
+#define PROBE_BUFFER_SIZE 1024
+static unsigned char buffer[PROBE_BUFFER_SIZE];
+
+#define SC520_MAX_FLASH_BANKS  3
+#define SC520_FLASH_BANK0_BASE 0x38000000  /* BOOTCS */
+#define SC520_FLASH_BANK1_BASE 0x30000000  /* ROMCS0 */
+#define SC520_FLASH_BANK2_BASE 0x28000000  /* ROMCS1 */
+#define SC520_FLASH_BANKSIZE   0x8000000
+
+#define AMD29LV016B_SIZE        0x200000
+#define AMD29LV016B_SECTORS     32
+
+flash_info_t    flash_info[SC520_MAX_FLASH_BANKS];
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+
+static u32 _probe_flash(u32 addr, u32 bw, int il)
+{
+	u32 result=0;
+
+	/* First do an unlock cycle for the benefit of
+	 * devices that need it */
+
+	switch (bw) {
+
+	case 1:
+		*(volatile u8*)(addr+0x5555) = 0xaa;
+		*(volatile u8*)(addr+0x2aaa) = 0x55;
+		*(volatile u8*)(addr+0x5555) = 0x90;
+
+		/* Read vendor */
+		result = *(volatile u8*)addr;
+		result <<= 16;
+
+		/* Read device */
+		result |= *(volatile u8*)(addr+2);
+
+		/* Return device to data mode */
+		*(volatile u8*)addr = 0xff;
+		*(volatile u8*)(addr+0x5555), 0xf0;
+		break;
+
+	case 2:
+		*(volatile u16*)(addr+0xaaaa) = 0xaaaa;
+		*(volatile u16*)(addr+0x5554) = 0x5555;
+
+		/* Issue identification command */
+		if (il == 2) {
+			*(volatile u16*)(addr+0xaaaa) = 0x9090;
+
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u8*)(addr+2);
+
+			/* Return device to data mode */
+			*(volatile u16*)addr =  0xffff;
+			*(volatile u16*)(addr+0xaaaa), 0xf0f0;
+
+		} else {
+			*(volatile u8*)(addr+0xaaaa) = 0x90;
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u16*)(addr+2);
+
+			/* Return device to data mode */
+			*(volatile u8*)addr = 0xff;
+			*(volatile u8*)(addr+0xaaaa), 0xf0;
+		}
+
+		break;
+
+	 case 4:
+		*(volatile u32*)(addr+0x5554) = 0xaaaaaaaa;
+		*(volatile u32*)(addr+0xaaa8) = 0x55555555;
+
+		switch (il) {
+		case 1:
+			/* Issue identification command */
+			*(volatile u8*)(addr+0x5554) = 0x90;
+
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+
+			/* Return device to data mode */
+			*(volatile u8*)addr =  0xff;
+			*(volatile u8*)(addr+0x5554), 0xf0;
+			break;
+
+		case 2:
+			/* Issue identification command */
+			*(volatile u32*)(addr + 0x5554) = 0x00900090;
+
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0x00ff00ff;
+			*(volatile u32*)(addr+0x5554), 0x00f000f0;
+			break;
+
+		case 4:
+			/* Issue identification command */
+			*(volatile u32*)(addr+0x5554) = 0x90909090;
+
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u8*)(addr+4);
+
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0xffffffff;
+			*(volatile u32*)(addr+0x5554), 0xf0f0f0f0;
+			break;
+		}
+		break;
+	}
+
+
+	return result;
+}
+
+extern int _probe_flash_end;
+asm ("_probe_flash_end:\n"
+     ".long 0\n");
+
+static int identify_flash(unsigned address, int width)
+{
+	int is;
+	int device;
+	int vendor;
+	int size;
+	unsigned res;
+
+	u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il);
+
+	size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash;
+
+	if (size > PROBE_BUFFER_SIZE) {
+		printf("_probe_flash() routine too large (%d) %p - %p\n",
+		       size, &_probe_flash_end, _probe_flash);
+		return 0;
+	}
+
+	memcpy(buffer, _probe_flash, size);
+	_probe_flash_ptr = (void*)buffer;
+
+	is = disable_interrupts();
+	res = _probe_flash_ptr(address, width, 1);
+	if (is) {
+		enable_interrupts();
+	}
+
+
+	vendor = res >> 16;
+	device = res & 0xffff;
+
+
+	return res;
+}
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
+		unsigned id;
+		ulong flashbase = 0;
+		int sectsize = 0;
+
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		case 1:
+			flashbase = SC520_FLASH_BANK1_BASE;
+			break;
+		case 2:
+			flashbase = SC520_FLASH_BANK2_BASE;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+		}
+
+		id = identify_flash(flashbase, 4);
+		switch (id & 0x00ff00ff) {
+		case 0x000100c8:
+			/* 29LV016B/29LV017B */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV016B & FLASH_TYPEMASK);
+
+			flash_info[i].size = AMD29LV016B_SIZE*4;
+			flash_info[i].sector_count = AMD29LV016B_SECTORS;
+			sectsize = (AMD29LV016B_SIZE*4)/AMD29LV016B_SECTORS;
+			printf("Bank %d: 4 x AMD 29LV017B\n", i);
+			break;
+
+
+		default:
+			printf("Bank %d have unknown flash %08x\n", i, id);
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			continue;
+		}
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * sectsize;
+		}
+		size += flash_info[i].size;
+
+		flash_protect(FLAG_PROTECT_CLEAR,
+			      flash_info[i].start[0],
+			       flash_info[i].start[0] + flash_info[i].size - 1,
+			      &flash_info[i]);
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      i386boot_start,
+		      i386boot_end,
+		      &flash_info[0]);
+#ifdef CFG_ENV_ADDR
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf("AMD:   ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (AMD_ID_LV016B & FLASH_TYPEMASK):
+			printf("4x AMD29LV017B (4x16Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */
+#define __udelay(delay) \
+{	\
+	unsigned micro; \
+	unsigned milli=0; \
+	\
+	micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+	 \
+	for (;;) { \
+		\
+		milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+		micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \
+		\
+		if ((delay) <= (micro + (milli * 1000))) { \
+			break; \
+		} \
+	} \
+} while (0)
+
+static u32 _amd_erase_flash(u32 addr, u32 sector)
+{
+	unsigned elapsed;
+
+	/* Issue erase */
+	*(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA;
+	*(volatile u32*)(addr + 0xaaa8) = 0x55555555;
+	*(volatile u32*)(addr + 0x5554) = 0x80808080;
+	/* And one unlock */
+	*(volatile u32*)(addr + 0x5554) = 0xAAAAAAAA;
+	*(volatile u32*)(addr + 0xaaa8) = 0x55555555;
+	/* Sector erase command comes last */
+	*(volatile u32*)(addr + sector) = 0x30303030;
+
+	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = 0;
+	__udelay(50);
+	while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) {
+
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+			*(volatile u32*)(addr) = 0xf0f0f0f0;
+			return 1;
+		}
+	}
+
+	*(volatile u32*)(addr) = 0xf0f0f0f0;
+
+	return 0;
+}
+
+extern int _amd_erase_flash_end;
+asm ("_amd_erase_flash_end:\n"
+     ".long 0\n");
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	u32 (*_erase_flash_ptr)(u32 a, u32 so);
+	int prot;
+	int sect;
+	unsigned size;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash;
+
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_erase_flash() routine too large (%d) %p - %p\n",
+			       size, &_amd_erase_flash_end, _amd_erase_flash);
+			return 0;
+		}
+
+		memcpy(buffer, _amd_erase_flash, size);
+		_erase_flash_ptr = (void*)buffer;
+
+	}  else {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+
+		if (info->protect[sect] == 0) { /* not protected */
+			int res;
+			int flag;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]);
+
+			/* re-enable interrupts if necessary */
+			if (flag) {
+				enable_interrupts();
+			}
+
+
+			if (res) {
+				printf("Erase timed out, sector %d\n", sect);
+				return res;
+			}
+
+			putc('.');
+		}
+	}
+
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int _amd_write_word(unsigned start, unsigned dest, unsigned data)
+{
+	volatile u32 *addr2 = (u32*)start;
+	volatile u32 *dest2 = (u32*)dest;
+	volatile u32 *data2 = (u32*)&data;
+	unsigned elapsed;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile u32*)dest) & (u32)data) != (u32)data) {
+		return 2;
+	}
+
+	addr2[0x5554] = 0xAAAAAAAA;
+	addr2[0xaaa8] = 0x55555555;
+	addr2[0x5554] = 0xA0A0A0A0;
+
+	dest2[0] = data;
+
+	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = 0;
+
+	/* data polling for D7 */
+	while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) {
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+			addr2[0] = 0xf0f0f0f0;
+			return 1;
+		}
+	}
+
+
+	addr2[0] = 0xf0f0f0f0;
+
+	return 0;
+}
+
+extern int _amd_write_word_end;
+asm ("_amd_write_word_end:\n"
+     ".long 0\n");
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - Unsupported flash type
+ */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	int flag;
+	u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data);
+	unsigned size;
+
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word;
+
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_write_word() routine too large (%d) %p - %p\n",
+			       size, &_amd_write_word_end, _amd_write_word);
+			return 0;
+		}
+
+		memcpy(buffer, _amd_write_word, size);
+		_write_word_ptr = (void*)buffer;
+
+	} else {
+		printf ("Can't program unknown flash type - aborted\n");
+		return 3;
+	}
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data |= (*(uchar *)cp) << (8*i);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data |= *src++ << (8*i);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data |= (*(uchar *)cp)  << (8*i);
+		}
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		rc = _write_word_ptr(info->start[0], wp, data);
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+
+		for (i=0; i<4; ++i) {
+			data |= *src++ << (8*i);
+		}
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		rc = _write_word_ptr(info->start[0], wp, data);
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return 0;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data |= *src++ << (8*i);
+		--cnt;
+	}
+
+	for (; i<4; ++i, ++cp) {
+		data |= (*(uchar *)cp) << (8*i);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	rc = _write_word_ptr(info->start[0], wp, data);
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+
+	return rc;
+
+}
diff --git a/board/sc520_cdp/flash_old.c b/board/sc520_cdp/flash_old.c
new file mode 100755
index 0000000..3c0f6d6
--- /dev/null
+++ b/board/sc520_cdp/flash_old.c
@@ -0,0 +1,458 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+ulong myflush(void);
+
+
+#define SC520_MAX_FLASH_BANKS  3
+#define SC520_FLASH_BANK0_BASE 0x38000000  /* BOOTCS */
+#define SC520_FLASH_BANK1_BASE 0x30000000  /* ROMCS0 */
+#define SC520_FLASH_BANK2_BASE 0x28000000  /* ROMCS1 */
+#define SC520_FLASH_BANKSIZE   0x8000000
+
+#define AMD29LV016_SIZE        0x200000
+#define AMD29LV016_SECTORS     32
+
+flash_info_t    flash_info[SC520_MAX_FLASH_BANKS];
+
+#define CMD_READ_ARRAY		0x00F000F0
+#define CMD_UNLOCK1		0x00AA00AA
+#define CMD_UNLOCK2		0x00550055
+#define CMD_ERASE_SETUP		0x00800080
+#define CMD_ERASE_CONFIRM	0x00300030
+#define CMD_PROGRAM		0x00A000A0
+#define CMD_UNLOCK_BYPASS	0x00200020
+
+
+#define BIT_ERASE_DONE		0x00800080
+#define BIT_RDY_MASK		0x00800080
+#define BIT_PROGRAM_ERROR	0x00200020
+#define BIT_TIMEOUT		0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		int sectsize = 0;
+		if (i==0 || i==2) {
+			/* FixMe: this assumes that bank 0 and 2
+			 * are mapped to the two 8Mb banks */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV016B & FLASH_TYPEMASK);
+
+			flash_info[i].size = AMD29LV016_SIZE*4;
+			flash_info[i].sector_count = AMD29LV016_SECTORS;
+			sectsize = (AMD29LV016_SIZE*4)/AMD29LV016_SECTORS;
+		} else {
+			/* FixMe: this assumes that bank1 is unmapped
+			 * (or mapped to the same flash bank as BOOTCS) */
+			flash_info[i].flash_id = 0;
+			flash_info[i].size = 0;
+			flash_info[i].sector_count = 0;
+			sectsize=0;
+		}
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		case 1:
+			flashbase = SC520_FLASH_BANK1_BASE;
+			break;
+		case 2:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+		}
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = sectsize;
+			flash_info[i].start[j] = flashbase + j * sectsize;
+		}
+		size += flash_info[i].size;
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      i386boot_start-SC520_FLASH_BANK0_BASE,
+		      i386boot_end-SC520_FLASH_BANK0_BASE,
+		      &flash_info[0]);
+
+#ifdef CFG_ENV_ADDR
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf("AMD: ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_LV016B & FLASH_TYPEMASK):
+		printf("4x Amd29LV016B (16Mbit)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		goto done;
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+	done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1, chip2;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return ERR_UNKNOWN_FLASH_TYPE;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		return ERR_PROTECTED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
+		printf("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer();
+
+		if (info->protect[sect] == 0) {
+			/* not protected */
+			ulong addr = info->start[sect];
+
+			writel(CMD_UNLOCK1, addr + 1);
+			writel(CMD_UNLOCK2, addr + 2);
+			writel(CMD_ERASE_SETUP, addr + 1);
+
+			writel(CMD_UNLOCK1, addr + 1);
+			writel(CMD_UNLOCK2, addr + 2);
+			writel(CMD_ERASE_CONFIRM, addr);
+
+
+			/* wait until flash is ready */
+			chip1 = chip2 = 0;
+
+			do {
+				result = readl(addr);
+
+				/* check timeout */
+				if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
+					writel(CMD_READ_ARRAY, addr + 1);
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) {
+					chip1 = READY;
+				}
+
+				if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) {
+					chip1 = ERR;
+				}
+
+				if (!chip2 && (result >> 16) & BIT_ERASE_DONE) {
+					chip2 = READY;
+				}
+
+				if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) {
+					chip2 = ERR;
+				}
+
+			}  while (!chip1 || !chip2);
+
+			writel(CMD_READ_ARRAY, addr + 1);
+
+			if (chip1 == ERR || chip2 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf("ok.\n");
+		} else { /* it was protected */
+
+			printf("protected!\n");
+		}
+	}
+
+	if (ctrlc()) {
+		printf("User Interrupt!\n");
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay(10000);
+
+	if (iflag) {
+		enable_interrupts();
+	}
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	ulong addr = dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+	int chip1, chip2;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = readl(addr);
+	if ((result & data) != data) {
+		return ERR_NOT_ERASED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	iflag = disable_interrupts();
+
+	writel(CMD_UNLOCK1, addr + 1);
+	writel(CMD_UNLOCK2, addr + 2);
+	writel(CMD_UNLOCK_BYPASS, addr + 1);
+	writel(addr, CMD_PROGRAM);
+	writel(addr, data);
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer();
+
+	/* wait until flash is ready */
+	chip1 = chip2 = 0;
+	do {
+		result = readl(addr);
+
+		/* check timeout */
+		if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+
+		if (!chip1 && ((result & 0x80) == (data & 0x80))) {
+			chip1 = READY;
+		}
+
+		if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = readl(addr);
+
+			if ((result & 0x80) == (data & 0x80)) {
+				chip1 = READY;
+			} else {
+				chip1 = ERR;
+			}
+		}
+
+		if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) {
+			chip2 = READY;
+		}
+
+		if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) {
+			result = readl(addr);
+
+			if ((result & (0x80 << 16)) == (data & (0x80 << 16))) {
+				chip2 = READY;
+			} else {
+				chip2 = ERR;
+			}
+		}
+
+	}  while (!chip1 || !chip2);
+
+	writel(CMD_READ_ARRAY, addr);
+
+	if (chip1 == ERR || chip2 == ERR || readl(addr) != data) {
+		rc = ERR_PROG_ERROR;
+	}
+
+	if (iflag) {
+		enable_interrupts();
+	}
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *)cp << 24);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long*)src);
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return rc;
+		}
+		src += 4;
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+
+	return write_word(info, wp, data);
+}
diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
new file mode 100755
index 0000000..cd52324
--- /dev/null
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -0,0 +1,630 @@
+/*
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+#include <asm/ic/ali512x.h>
+#include <spi.h>
+
+#undef SC520_CDP_DEBUG
+
+#ifdef	SC520_CDP_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Theory:
+ * We first set up all IRQs to be non-pci, edge triggered,
+ * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
+ * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
+ * as needed. Whe choose the irqs to gram from a configurable list
+ * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
+ * such as 0 thngas will not work)
+ */
+
+static void irq_init(void)
+{
+	/* disable global interrupt mode */
+	write_mmcr_byte(SC520_PICICR, 0x40);
+
+	/* set all irqs to edge */
+	write_mmcr_byte(SC520_MPICMODE, 0x00);
+	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
+	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+
+	/* active low polarity on PIC interrupt pins,
+	 *  active high polarity on all other irq pins */
+	write_mmcr_word(SC520_INTPINPOL, 0x0000);
+
+	/* set irq number mapping */
+	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
+	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
+	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
+	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
+	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
+	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
+	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
+	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
+	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
+	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
+	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
+	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED);      /* disable Synchronius serial INT */
+	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
+	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
+	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
+	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
+	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
+
+	if (CFG_USE_SIO_UART) {
+		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
+		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
+		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3);          /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
+		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4);          /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
+	} else {
+		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);         /* Set internal UART2 INT to IRQ4 */
+		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);         /* Set internal UART2 INT to IRQ3 */
+		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ3 (ISA IRQ3) */
+		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ4 (ISA IRQ4) */
+	}
+
+	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1);             /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
+	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5);             /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
+	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6);             /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
+	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7);             /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
+	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8);             /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
+	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9);             /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
+	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11);            /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
+	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12);            /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
+	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14);            /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
+
+	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);                /* Map PCI hostbridge INT to NMI */
+	write_mmcr_word(SC520_ECCMAP, 0x100);                    /* Map SDRAM ECC failure INT to NMI */
+
+}
+
+
+/* PCI stuff */
+static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CFG_FIRST_PCI_IRQ,
+		CFG_SECOND_PCI_IRQ,
+		CFG_THIRD_PCI_IRQ,
+		CFG_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+
+	char tmp_pin;
+	int pin;
+
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
+
+
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 20:
+		pin+=SC520_PCI_INTA;
+		break;
+
+	case 19:
+		pin+=SC520_PCI_INTB;
+		break;
+
+	case 18:
+		pin+=SC520_PCI_INTC;
+		break;
+
+	case 17:
+		pin+=SC520_PCI_INTD;
+		break;
+
+	default:
+		return;
+	}
+
+	pin&=3; /* wrap around */
+
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+			return;
+		}
+		next_irq_index++;
+	}
+
+
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+					   sc520_pci_ints[pin]);
+	}
+	PRINTF("fixup_irq: device %d pin %c irq %d\n",
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+}
+
+static struct pci_controller sc520_cdp_hose = {
+	fixup_irq: pci_sc520_cdp_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&sc520_cdp_hose);
+}
+
+
+static void silence_uart(int port)
+{
+	outb(0, port+1);
+}
+
+void setup_ali_sio(int uart_primary)
+{
+	ali512x_init();
+
+	ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
+	ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
+	ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
+	ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3);
+	ali512x_set_rtc(ALI_DISABLED, 0, 0);
+	ali512x_set_kbc(ALI_ENABLED, 1, 12);
+	ali512x_set_cio(ALI_ENABLED);
+
+	/* IrDa pins */
+	ali512x_cio_function(12, 1, 0, 0);
+	ali512x_cio_function(13, 1, 0, 0);
+
+	/* SSI chip select pins */
+	ali512x_cio_function(14, 0, 0, 0);  /* SSI_CS */
+	ali512x_cio_function(15, 0, 0, 0);  /* SSI_MV */
+	ali512x_cio_function(16, 0, 0, 0);  /* SSI_SPI# */
+
+	/* Board REV pins */
+	ali512x_cio_function(20, 0, 0, 1);
+	ali512x_cio_function(21, 0, 0, 1);
+	ali512x_cio_function(22, 0, 0, 1);
+	ali512x_cio_function(23, 0, 0, 1);
+}
+
+
+/* set up the ISA bus timing and system address mappings */
+static void bus_init(void)
+{
+
+	/* set up the GP IO pins */
+	write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); 	/* set the GPIO pin function 31-16 reg */
+	write_mmcr_word(SC520_PIOPFS15_0, 0xffff);  	/* set the GPIO pin function 15-0 reg */
+	write_mmcr_byte(SC520_CSPFS, 0xf8);  		/* set the CS pin function  reg */
+	write_mmcr_byte(SC520_CLKSEL, 0x70);
+
+
+	write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
+	write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
+	write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
+	write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
+	write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
+	write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
+	write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
+
+	write_mmcr_word(SC520_BOOTCSCTL, 0x1823);		/* set up timing of BOOTCS */
+	write_mmcr_word(SC520_ROMCS1CTL, 0x1823);		/* set up timing of ROMCS1 */
+	write_mmcr_word(SC520_ROMCS2CTL, 0x1823);		/* set up timing of ROMCS2 */
+
+	/* adjust the memory map:
+	 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
+	 * and 256MB to 1G-128k  (0x1000000 - 0x37ffffff) is mapped to PCI mmio
+	 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
+
+
+	/* SRAM = GPCS3 128k @ d0000-effff*/
+	write_mmcr_long(SC520_PAR2,  0x4e00400d);
+
+	/* IDE0 = GPCS6 1f0-1f7 */
+	write_mmcr_long(SC520_PAR3,  0x380801f0);
+
+	/* IDE1 = GPCS7 3f6 */
+	write_mmcr_long(SC520_PAR4,  0x3c0003f6);
+	/* bootcs */
+	write_mmcr_long(SC520_PAR12, 0x8bffe800);
+	/* romcs2 */
+	write_mmcr_long(SC520_PAR13, 0xcbfff000);
+	/* romcs1 */
+	write_mmcr_long(SC520_PAR14, 0xabfff800);
+	/* 680 LEDS */
+	write_mmcr_long(SC520_PAR15, 0x30000640);
+
+	write_mmcr_byte(SC520_ADDDECCTL, 0);
+
+	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
+
+	if (CFG_USE_SIO_UART) {
+		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
+		setup_ali_sio(1);
+	} else {
+		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
+		setup_ali_sio(0);
+		silence_uart(0x3e8);
+		silence_uart(0x2e8);
+	}
+
+}
+
+/* GPCS usage
+ * GPCS0       PIO27 (NMI)
+ * GPCS1       ROMCS1
+ * GPCS2       ROMCS2
+ * GPCS3       SRAMCS       PAR2
+ * GPCS4       unused       PAR3
+ * GPCS5       unused       PAR4
+ * GPCS6       IDE
+ * GPCS7       IDE
+ */
+
+
+/* par usage:
+ * PAR0   legacy_video
+ * PAR1   PCI ROM mapping
+ * PAR2   SRAM
+ * PAR3   IDE
+ * PAR4   IDE
+ * PAR5   legacy_video
+ * PAR6   legacy_video
+ * PAR7   legacy_video
+ * PAR8   legacy_video
+ * PAR9   legacy_video
+ * PAR10  legacy_video
+ * PAR11  ISAROM
+ * PAR12  BOOTCS
+ * PAR13  ROMCS1
+ * PAR14  ROMCS2
+ * PAR15  Port 0x680 LED display
+ */
+
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ *
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size)
+{
+	u32 par;
+
+	PRINTF("isa_map_rom asked to map %d bytes at %x\n",
+	       size, bus_addr);
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+
+	PRINTF ("setting PAR11 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR11,  par);
+
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	PRINTF("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
+		write_mmcr_long(SC520_PAR11, 0);
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+}
+
+#ifdef CONFIG_PCI
+#define PCI_ROM_TEMP_SPACE 0x10000
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size)
+{
+	u32 par;
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+
+	PRINTF ("setting PAR1 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR1,  par);
+
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	PRINTF("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		write_mmcr_long(SC520_PAR1, 0);
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus.
+ * After this function accesses to I/O ports 0x3b0-0x3bb and
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ *
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	write_mmcr_long(SC520_PAR0,  0x7200400a);
+
+	/* forward all I/O accesses to PCI */
+	write_mmcr_byte(SC520_ADDDECCTL,
+			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
+
+
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers
+	 */
+
+	/* bring 0x100 - 0x1ef back to ISA using PAR5 */
+	write_mmcr_long(SC520_PAR5, 0x30ef0100);
+
+	/* IDE use 1f0-1f7 */
+
+	/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
+	write_mmcr_long(SC520_PAR6, 0x30ff01f8);
+
+	/* com2 use 2f8-2ff */
+
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	write_mmcr_long(SC520_PAR7, 0x30af0300);
+
+	/* vga use 3b0-3bb */
+
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	write_mmcr_long(SC520_PAR8, 0x300303bc);
+
+	/* vga use 3c0-3df */
+
+	/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
+	write_mmcr_long(SC520_PAR9, 0x301503e0);
+
+	/* ide use 3f6 */
+
+	/* bring 0x3f7  back to ISA using PAR10 */
+	write_mmcr_long(SC520_PAR10, 0x300003f7);
+
+	/* com1 use 3f8-3ff */
+
+	return 0;
+}
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	init_sc520();
+	bus_init();
+	irq_init();
+
+	/* max drive current on SDRAM */
+	write_mmcr_word(SC520_DSCTL, 0x0100);
+
+	/* enter debug mode after next reset (only if jumper is also set) */
+	write_mmcr_byte(SC520_RESCFG, 0x08);
+	/* configure the software timer to 33.333MHz */
+	write_mmcr_byte(SC520_SWTMRCFG, 0);
+	gd->bus_clk = 33333000;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	init_sc520_dram();
+	return 0;
+}
+
+void show_boot_progress(int val)
+{
+	outb(val&0xff, 0x80);
+	outb((val&0xff00)>>8, 0x680);
+}
+
+
+int last_stage_init(void)
+{
+	int minor;
+	int major;
+
+	major = minor = 0;
+	major |= ali512x_cio_in(23)?2:0;
+	major |= ali512x_cio_in(22)?1:0;
+	minor |= ali512x_cio_in(21)?2:0;
+	minor |= ali512x_cio_in(20)?1:0;
+
+	printf("AMD SC520 CDP revision %d.%d\n", major, minor);
+
+	return 0;
+}
+
+
+void ssi_chip_select(int dev)
+{
+
+	/* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
+	switch (dev) {
+	case 1: /* SPI EEPROM */
+		ali512x_cio_out(16, 0);
+		break;
+
+	case 2: /* MW EEPROM */
+		ali512x_cio_out(15, 1);
+		break;
+
+	case 3: /* AUX */
+		ali512x_cio_out(14, 1);
+		break;
+
+	case 0:
+		ali512x_cio_out(16, 1);
+		ali512x_cio_out(15, 0);
+		ali512x_cio_out(14, 0);
+		break;
+
+	default:
+		printf("Illegal SSI device requested: %d\n", dev);
+	}
+}
+
+void spi_eeprom_probe(int x)
+{
+}
+
+int spi_eeprom_read(int x, int offset, char *buffer, int len)
+{
+       return 0;
+}
+
+int spi_eeprom_write(int x, int offset, char *buffer, int len)
+{
+       return 0;
+}
+
+void spi_init_f(void)
+{
+#ifdef CONFIG_SC520_CDP_USE_SPI
+	spi_eeprom_probe(1);
+#endif
+#ifdef CONFIG_SC520_CDP_USE_MW
+	mw_eeprom_probe(2);
+#endif
+}
+
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
+{
+	int offset;
+	int i;
+	ssize_t res;
+
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+
+#ifdef CONFIG_SC520_CDP_USE_SPI
+	res = spi_eeprom_read(1, offset, buffer, len);
+#endif
+#ifdef CONFIG_SC520_CDP_USE_MW
+	res = mw_eeprom_read(2, offset, buffer, len);
+#endif
+#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
+	res = 0;
+#endif
+	return res;
+}
+
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
+{
+	int offset;
+	int i;
+	ssize_t res;
+
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+
+#ifdef CONFIG_SC520_CDP_USE_SPI
+	res = spi_eeprom_write(1, offset, buffer, len);
+#endif
+#ifdef CONFIG_SC520_CDP_USE_MW
+	res = mw_eeprom_write(2, offset, buffer, len);
+#endif
+#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
+	res = 0;
+#endif
+	return res;
+}
diff --git a/board/sc520_cdp/sc520_cdp_asm.S b/board/sc520_cdp/sc520_cdp_asm.S
new file mode 100755
index 0000000..be7b2bb
--- /dev/null
+++ b/board/sc520_cdp/sc520_cdp_asm.S
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* now setup the General purpose bus to give us access to the LEDs.
+ * We can then use the leds to display status information.
+ */
+
+sc520_cdp_registers:
+/* size    offset        value */
+.word 1 ; .word 0x040 ; .long 0x00       /* SDRAM buffer control */
+.word 2 ; .word 0xc08 ; .long 0x0001     /* GP CS offset */
+.word 2 ; .word 0xc09 ; .long 0x0003     /* GP CS width */
+.word 2 ; .word 0xc0a ; .long 0x0001     /* GP CS width */
+.word 2 ; .word 0xc0b ; .long 0x0003     /* GP RD pulse width */
+.word 2 ; .word 0xc0c ; .long 0x0001     /* GP RD offse */
+.word 2 ; .word 0xc0d ; .long 0x0003     /* GP WR pulse width */
+.word 2 ; .word 0xc0e ; .long 0x0001     /* GP WR offset */
+.word 2 ; .word 0xc2c ; .long 0x0000     /* GPIO directionreg */
+.word 2 ; .word 0xc2a ; .long 0x0000     /* GPIO directionreg */
+.word 2 ; .word 0xc22 ; .long 0xffff     /* GPIO pin function 31-16 reg */
+.word 2 ; .word 0xc20 ; .long 0xffff     /* GPIO pin function 15-0 reg */
+.word 2 ; .word 0x0c4 ; .long 0x28000680 /* PAR 15 for access to led 680 */
+.word 0 ; .word 0x000 ; .long 0x00
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+	movl    $sc520_cdp_registers,%esi
+init_loop:
+	movl    $0xfffef000,%edi     /* MMCR base to edi */
+	movw	(%esi), %bx          /* load sizer to bx */
+	cmpw	$0, %bx              /* if sie is 0 we're done */
+	je	done
+	xorl	%edx,%edx
+	movw	2(%esi), %dx        /* load MMCR offset to dx */
+	addl	%edx, %edi          /* add offset to base in edi */
+	movl	4(%esi), %eax       /* load value in eax */
+	cmpw	$1, %bx
+	je	byte                 /* byte op? */
+	cmpw	$2, %bx
+	je	word                 /* word op? */
+	movl	%eax, (%edi)         /* must be long, then */
+	jmp	next
+byte:   movb    %al,(%edi)
+	jmp	next
+word:	movw	%ax,(%edi)
+next:	addl	$8, %esi             /* advance esi */
+	jmp	init_loop
+
+	/* the leds ad 0x80 and 0x680 should now work */
+done:   movb	$0x88, %al
+	out	%al, $0x80
+	movw	$0x680, %dx
+	out	%al, %dx
+
+	jmp 	*%ebp		     /* return to caller */
+
+
+.globl __show_boot_progress
+__show_boot_progress:
+	out	%al, $0x80
+	xchg	%al, %ah
+	movw	$0x680, %dx
+	out	%al, %dx
+	jmp	*%ebp
diff --git a/board/sc520_cdp/sc520_cdp_asm16.S b/board/sc520_cdp/sc520_cdp_asm16.S
new file mode 100755
index 0000000..a3e700a
--- /dev/null
+++ b/board/sc520_cdp/sc520_cdp_asm16.S
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 16bit initialization code.
+ * This code have to map the area of the boot flash
+ * that is used by U-boot to its final destination.
+ */
+
+.text
+.section .start16, "ax"
+.code16
+.globl board_init16
+board_init16:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax
+	outl	%eax, %dx
+
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax
+	movw	%ax, %ds
+
+	/* Map the entire flash at 0x38000000
+	 * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */
+	movl    $0xc0, %edi
+	movl	$0x8bfff800, %eax
+	movl	%eax, (%di)
+
+	/* Disable SDRAM write buffer */
+	movw    $0x40,%di
+	xorw    %ax,%ax
+	movb    %al, (%di)
+
+	/* Disabe MMCR alias */
+	movw	$0xfffc, %dx
+	movl	$0x000000cb, %eax
+	outl	%eax, %dx
+
+	/* the return address is tored in bp */
+	jmp	*%bp
+
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+realmode_reset:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax
+	outl	%eax, %dx
+
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax
+	movw	%ax, %ds
+
+	/* issue software reset thorugh MMCR */
+	movl    $0xd72, %edi
+	movb	$0x01, %al
+	movb	%al, (%di)
+
+1:	hlt
+	jmp	1
diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds
new file mode 100755
index 0000000..72164a1
--- /dev/null
+++ b/board/sc520_cdp/u-boot.lds
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0x387c0000;                     /* Where bootcode in the flash is mapped */
+	.text  : { *(.text); }
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) }
+
+	. = 0x400000; 	                    /* Ram data segment to use */
+	_i386boot_romdata_dest = ABSOLUTE(.);
+	.data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
+	_i386boot_romdata_start = LOADADDR(.data);
+
+	. = ALIGN(4);
+	.got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
+	_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got);
+
+
+	. = ALIGN(4);
+	_i386boot_bss_start = ABSOLUTE(.);
+	.bss : { *(.bss) }
+	_i386boot_bss_size = SIZEOF(.bss);
+
+
+	/* 16bit realmode trampoline code */
+	.realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) }
+
+	_i386boot_realmode = LOADADDR(.realmode);
+	_i386boot_realmode_size = SIZEOF(.realmode);
+
+	/* 16bit BIOS emulation code (just enough to boot Linux) */
+	.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
+
+	_i386boot_bios = LOADADDR(.bios);
+	_i386boot_bios_size = SIZEOF(.bios);
+
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+	/* The load addresses below assumes that the flash
+	 * will be mapped so that 0x387f0000 == 0xffff0000
+	 * at reset time
+	 *
+	 * The fe00 and ff00 offsets of the start32 and start16
+	 * segments are arbitrary, the just have to be mapped
+	 * at reset and the code have to fit.
+	 * The fff0 offset of reset is important, however.
+	 */
+
+
+	. = 0xfffffe00;
+	.start32 : AT (0x387ffe00) { *(.start32); }
+
+	. = 0xff00;
+	.start16 : AT (0x387fff00) { *(.start16); }
+
+	. = 0xfff0;
+	.reset : AT (0x387ffff0) { *(.reset); }
+	_i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
+}
diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile
new file mode 100755
index 0000000..242d53c
--- /dev/null
+++ b/board/sc520_spunk/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= sc520_spunk.o flash.o
+SOBJS	:= sc520_spunk_asm.o sc520_spunk_asm16.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sc520_spunk/config.mk b/board/sc520_spunk/config.mk
new file mode 100755
index 0000000..2253815
--- /dev/null
+++ b/board/sc520_spunk/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+TEXT_BASE = 0x387c0000
diff --git a/board/sc520_spunk/flash.c b/board/sc520_spunk/flash.c
new file mode 100755
index 0000000..4942e59
--- /dev/null
+++ b/board/sc520_spunk/flash.c
@@ -0,0 +1,809 @@
+/*
+ * (C) Copyright 2002, 2003
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <asm/ic/sc520.h>
+
+#define PROBE_BUFFER_SIZE 1024
+static unsigned char buffer[PROBE_BUFFER_SIZE];
+
+
+#define SC520_MAX_FLASH_BANKS  1
+#define SC520_FLASH_BANK0_BASE 0x38000000  /* BOOTCS */
+#define SC520_FLASH_BANKSIZE   0x8000000
+
+#define A29LV641DH_SIZE        0x800000
+#define A29LV641DH_SECTORS     128
+
+#define A29LV641MH_SIZE        0x800000
+#define A29LV641MH_SECTORS     128
+
+#define I28F320J3A_SIZE        0x400000
+#define I28F320J3A_SECTORS     32
+
+#define I28F640J3A_SIZE        0x800000
+#define I28F640J3A_SECTORS     64
+
+#define I28F128J3A_SIZE        0x1000000
+#define I28F128J3A_SECTORS     128
+
+flash_info_t    flash_info[SC520_MAX_FLASH_BANKS];
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+
+static u32 _probe_flash(u32 addr, u32 bw, int il)
+{
+	u32 result=0;
+
+	/* First do an unlock cycle for the benefit of
+	 * devices that need it */
+
+	switch (bw) {
+
+	case 1:
+		*(volatile u8*)(addr+0x5555) = 0xaa;
+		*(volatile u8*)(addr+0x2aaa) = 0x55;
+		*(volatile u8*)(addr+0x5555) = 0x90;
+
+		/* Read vendor */
+		result = *(volatile u8*)addr;
+		result <<= 16;
+
+		/* Read device */
+		result |= *(volatile u8*)(addr+2);
+
+		/* Return device to data mode */
+		*(volatile u8*)addr = 0xff;
+		*(volatile u8*)(addr+0x5555), 0xf0;
+		break;
+
+	case 2:
+		*(volatile u16*)(addr+0xaaaa) = 0xaaaa;
+		*(volatile u16*)(addr+0x5554) = 0x5555;
+
+		/* Issue identification command */
+		if (il == 2) {
+			*(volatile u16*)(addr+0xaaaa) = 0x9090;
+
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u8*)(addr+2);
+
+			/* Return device to data mode */
+			*(volatile u16*)addr =  0xffff;
+			*(volatile u16*)(addr+0xaaaa), 0xf0f0;
+
+		} else {
+			*(volatile u8*)(addr+0xaaaa) = 0x90;
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u16*)(addr+2);
+
+			/* Return device to data mode */
+			*(volatile u8*)addr = 0xff;
+			*(volatile u8*)(addr+0xaaaa), 0xf0;
+		}
+
+		break;
+
+	 case 4:
+		*(volatile u32*)(addr+0x5554) = 0xaaaaaaaa;
+		*(volatile u32*)(addr+0xaaa8) = 0x55555555;
+
+		switch (il) {
+		case 1:
+			/* Issue identification command */
+			*(volatile u8*)(addr+0x5554) = 0x90;
+
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+
+			/* Return device to data mode */
+			*(volatile u8*)addr =  0xff;
+			*(volatile u8*)(addr+0x5554), 0xf0;
+			break;
+
+		case 2:
+			/* Issue identification command */
+			*(volatile u32*)(addr + 0x5554) = 0x00900090;
+
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0x00ff00ff;
+			*(volatile u32*)(addr+0x5554), 0x00f000f0;
+			break;
+
+		case 4:
+			/* Issue identification command */
+			*(volatile u32*)(addr+0x5554) = 0x90909090;
+
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+
+			/* Read device */
+			result |= *(volatile u8*)(addr+4);
+
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0xffffffff;
+			*(volatile u32*)(addr+0x5554), 0xf0f0f0f0;
+			break;
+		}
+		break;
+	}
+
+
+	return result;
+}
+
+extern int _probe_flash_end;
+asm ("_probe_flash_end:\n"
+     ".long 0\n");
+
+static int identify_flash(unsigned address, int width)
+{
+	int is;
+	int device;
+	int vendor;
+	int size;
+	unsigned res;
+
+	u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il);
+
+	size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash;
+
+	if (size > PROBE_BUFFER_SIZE) {
+		printf("_probe_flash() routine too large (%d) %p - %p\n",
+		       size, &_probe_flash_end, _probe_flash);
+		return 0;
+	}
+
+	memcpy(buffer, _probe_flash, size);
+	_probe_flash_ptr = (void*)buffer;
+
+	is = disable_interrupts();
+	res = _probe_flash_ptr(address, width, 1);
+	if (is) {
+		enable_interrupts();
+	}
+
+
+	vendor = res >> 16;
+	device = res & 0xffff;
+
+
+	return res;
+}
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
+		unsigned id;
+		ulong flashbase = 0;
+		int sectsize = 0;
+
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+		}
+
+		id = identify_flash(flashbase, 2);
+		switch (id) {
+		case 0x000122d7:
+			/* 29LV641DH */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV640U & FLASH_TYPEMASK);
+
+			flash_info[i].size = A29LV641DH_SIZE;
+			flash_info[i].sector_count = A29LV641DH_SECTORS;
+			sectsize = A29LV641DH_SIZE/A29LV641DH_SECTORS;
+			printf("Bank %d: AMD 29LV641DH\n", i);
+			break;
+
+		case 0x0001227E:
+			/* 29LV641MH */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_DL640 & FLASH_TYPEMASK);
+
+			flash_info[i].size = A29LV641MH_SIZE;
+			flash_info[i].sector_count = A29LV641MH_SECTORS;
+			sectsize = A29LV641MH_SIZE/A29LV641MH_SECTORS;
+			printf("Bank %d: AMD 29LV641MH\n", i);
+			break;
+
+		case 0x00890016:
+			/* 28F320J3A */
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F320J3A & FLASH_TYPEMASK);
+
+			flash_info[i].size = I28F320J3A_SIZE;
+			flash_info[i].sector_count = I28F320J3A_SECTORS;
+			sectsize = I28F320J3A_SIZE/I28F320J3A_SECTORS;
+			printf("Bank %d: Intel 28F320J3A\n", i);
+			break;
+
+		case 0x00890017:
+			/* 28F640J3A */
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
+
+			flash_info[i].size = I28F640J3A_SIZE;
+			flash_info[i].sector_count = I28F640J3A_SECTORS;
+			sectsize = I28F640J3A_SIZE/I28F640J3A_SECTORS;
+			printf("Bank %d: Intel 28F640J3A\n", i);
+			break;
+
+		case 0x00890018:
+			/* 28F128J3A */
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F128J3A & FLASH_TYPEMASK);
+
+			flash_info[i].size = I28F128J3A_SIZE;
+			flash_info[i].sector_count = I28F128J3A_SECTORS;
+			sectsize = I28F128J3A_SIZE/I28F128J3A_SECTORS;
+			printf("Bank %d: Intel 28F128J3A\n", i);
+			break;
+
+		default:
+			printf("Bank %d have unknown flash %08x\n", i, id);
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			continue;
+		}
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * sectsize;
+		}
+		size += flash_info[i].size;
+
+		flash_protect(FLAG_PROTECT_CLEAR,
+			      flash_info[i].start[0],
+			       flash_info[i].start[0] + flash_info[i].size - 1,
+			      &flash_info[i]);
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      i386boot_start,
+		      i386boot_end,
+		      &flash_info[0]);
+#ifdef CFG_ENV_ADDR
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf("INTEL: ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
+			printf("1x I28F320J3A (32Mbit)\n");
+			break;
+		case (INTEL_ID_28F640J3A & FLASH_TYPEMASK):
+			printf("1x I28F640J3A (64Mbit)\n");
+			break;
+		case (INTEL_ID_28F128J3A & FLASH_TYPEMASK):
+			printf("1x I28F128J3A (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+
+		break;
+
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf("AMD:   ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (AMD_ID_LV640U & FLASH_TYPEMASK):
+			printf("1x AMD29LV641DH (64Mbit)\n");
+			break;
+		case (AMD_ID_DL640 & FLASH_TYPEMASK):
+			printf("1x AMD29LV641MH (64Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+	done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+static u32 _amd_erase_flash(u32 addr, u32 sector)
+{
+	unsigned elapsed;
+
+	/* Issue erase */
+	*(volatile u16*)(addr + 0xaaaa) = 0x00AA;
+	*(volatile u16*)(addr + 0x5554) = 0x0055;
+	*(volatile u16*)(addr + 0xaaaa) = 0x0080;
+	/* And one unlock */
+	*(volatile u16*)(addr + 0xaaaa) = 0x00AA;
+	*(volatile u16*)(addr + 0x5554) = 0x0055;
+	/* Sector erase command comes last */
+	*(volatile u16*)(addr + sector) = 0x0030;
+
+	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = 0;
+	while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) {
+
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+			*(volatile u16*)(addr) = 0x00f0;
+			return 1;
+		}
+	}
+
+	*(volatile u16*)(addr) = 0x00f0;
+
+	return 0;
+}
+
+extern int _amd_erase_flash_end;
+asm ("_amd_erase_flash_end:\n"
+     ".long 0\n");
+
+/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */
+#define __udelay(delay) \
+{	\
+	unsigned micro; \
+	unsigned milli=0; \
+	\
+	micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+	 \
+	for (;;) { \
+		\
+		milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+		micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \
+		\
+		if ((delay) <= (micro + (milli * 1000))) { \
+			break; \
+		} \
+	} \
+} while (0)
+
+static u32 _intel_erase_flash(u32 addr, u32 sector)
+{
+	unsigned elapsed;
+
+	*(volatile u16*)(addr + sector) = 0x0050;   /* clear status register */
+	*(volatile u16*)(addr + sector) = 0x0020;   /* erase setup */
+	*(volatile u16*)(addr + sector) = 0x00D0;   /* erase confirm */
+
+
+	/* Wait at least 80us - let's wait 1 ms */
+	__udelay(1000);
+
+	elapsed = 0;
+	while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) {
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+			*(volatile u16*)(addr + sector) = 0x00B0;  /* suspend erase      */
+			*(volatile u16*)(addr + sector) = 0x00FF;  /* reset to read mode */
+			return 1;
+		}
+	}
+
+	*(volatile u16*)(addr + sector) = 0x00FF;  /* reset to read mode */
+
+	return 0;
+}
+
+
+extern int _intel_erase_flash_end;
+asm ("_intel_erase_flash_end:\n"
+     ".long 0\n");
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	u32 (*_erase_flash_ptr)(u32 a, u32 so);
+	int prot;
+	int sect;
+	unsigned size;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash;
+
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_erase_flash() routine too large (%d) %p - %p\n",
+			       size, &_amd_erase_flash_end, _amd_erase_flash);
+			return 0;
+		}
+
+		memcpy(buffer, _amd_erase_flash, size);
+		_erase_flash_ptr = (void*)buffer;
+
+	} else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_intel_erase_flash_end - (unsigned)_intel_erase_flash;
+
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_intel_erase_flash() routine too large (%d) %p - %p\n",
+			       size, &_intel_erase_flash_end, _intel_erase_flash);
+			return 0;
+		}
+
+		memcpy(buffer, _intel_erase_flash, size);
+		_erase_flash_ptr = (void*)buffer;
+	} else {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+
+		if (info->protect[sect] == 0) { /* not protected */
+			int res;
+			int flag;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]);
+
+			/* re-enable interrupts if necessary */
+			if (flag) {
+				enable_interrupts();
+			}
+
+
+			if (res) {
+				printf("Erase timed out, sector %d\n", sect);
+				return res;
+			}
+
+			putc('.');
+		}
+	}
+
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int _amd_write_word(unsigned start, unsigned dest, unsigned data)
+{
+	volatile u16 *addr2 = (u16*)start;
+	volatile u16 *dest2 = (u16*)dest;
+	volatile u16 *data2 = (u16*)&data;
+	int i;
+	unsigned elapsed;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile u16*)dest) & (u16)data) != (u16)data) {
+		return 2;
+	}
+
+	for (i = 0; i < 2; i++) {
+
+
+		addr2[0x5555] = 0x00AA;
+		addr2[0x2aaa] = 0x0055;
+		addr2[0x5555] = 0x00A0;
+
+		dest2[i] = (data >> (i*16)) & 0xffff;
+
+		elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+		elapsed = 0;
+
+		/* data polling for D7 */
+		while ((dest2[i] & 0x0080) != (data2[i] & 0x0080)) {
+			elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+			if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+				addr2[i] = 0x00f0;
+				return 1;
+			}
+		}
+	}
+
+	addr2[i] = 0x00f0;
+
+	return 0;
+}
+
+extern int _amd_write_word_end;
+asm ("_amd_write_word_end:\n"
+     ".long 0\n");
+
+
+static int _intel_write_word(unsigned start, unsigned dest, unsigned data)
+{
+	int i;
+	unsigned elapsed;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile u16*)dest) & (u16)data) != (u16)data) {
+		return 2;
+	}
+
+	for (i = 0; i < 2; i++) {
+
+		*(volatile u16*)(dest+2*i) = 0x0040; /* write setup */
+		*(volatile u16*)(dest+2*i) = (data >> (i*16)) & 0xffff;
+
+		elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+		elapsed = 0;
+
+		/* data polling for D7 */
+		while ((*(volatile u16*)dest & 0x0080) != 0x0080) {
+			elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+			if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+				*(volatile u16*)dest = 0x00ff;
+				return 1;
+			}
+		}
+	}
+
+	*(volatile u16*)dest = 0x00ff;
+
+
+	return 0;
+
+}
+
+extern int _intel_write_word_end;
+asm ("_intel_write_word_end:\n"
+     ".long 0\n");
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - Unsupported flash type
+ */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	int flag;
+	u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data);
+	unsigned size;
+
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word;
+
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_write_word() routine too large (%d) %p - %p\n",
+			       size, &_amd_write_word_end, _amd_write_word);
+			return 0;
+		}
+
+		memcpy(buffer, _amd_write_word, size);
+		_write_word_ptr = (void*)buffer;
+
+	} else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_intel_write_word_end - (unsigned)_intel_write_word;
+
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_intel_write_word() routine too large (%d) %p - %p\n",
+			       size, &_intel_write_word_end, _intel_write_word);
+			return 0;
+		}
+
+		memcpy(buffer, _intel_write_word, size);
+		_write_word_ptr = (void*)buffer;
+	} else {
+		printf ("Can't program unknown flash type - aborted\n");
+		return 3;
+	}
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data |= (*(uchar *)cp) << (8*i);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data |= *src++ << (8*i);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data |= (*(uchar *)cp)  << (8*i);
+		}
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		rc = _write_word_ptr(info->start[0], wp, data);
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+
+		for (i=0; i<4; ++i) {
+			data |= *src++ << (8*i);
+		}
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		rc = _write_word_ptr(info->start[0], wp, data);
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return 0;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data |= *src++ << (8*i);
+		--cnt;
+	}
+
+	for (; i<4; ++i, ++cp) {
+		data |= (*(uchar *)cp) << (8*i);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	rc = _write_word_ptr(info->start[0], wp, data);
+
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+
+	return rc;
+
+}
diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
new file mode 100755
index 0000000..e7a7d51
--- /dev/null
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -0,0 +1,681 @@
+/*
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <ssi.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Theory:
+ * We first set up all IRQs to be non-pci, edge triggered,
+ * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
+ * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
+ * as needed. Whe choose the irqs to gram from a configurable list
+ * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
+ * such as 0 thngas will not work)
+ */
+
+static void irq_init(void)
+{
+	/* disable global interrupt mode */
+	write_mmcr_byte(SC520_PICICR, 0x40);
+
+	/* set all irqs to edge */
+	write_mmcr_byte(SC520_MPICMODE, 0x00);
+	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
+	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+
+	/* active low polarity on PIC interrupt pins,
+	 *  active high polarity on all other irq pins */
+	write_mmcr_word(SC520_INTPINPOL, 0x0000);
+
+	/* set irq number mapping */
+	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
+	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
+	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
+	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
+	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
+	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
+	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
+	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
+	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
+	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
+	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
+	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6);              /* Set Synchronius serial INT to IRQ6*/
+	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
+	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
+	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
+	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
+	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
+
+	write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);            /* Set internal UART2 INT to IRQ4 */
+	write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);            /* Set internal UART2 INT to IRQ3 */
+
+	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7);             /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
+	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14);            /* Set GPIRQ1 (CF IRQ) to IRQ14 */
+	write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5);             /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
+	write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);     /* disbale GIRQ4 ( IRR IRQ ) */
+	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ5 */
+	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ6 */
+	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ7 */
+	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ8 */
+	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ9 */
+	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ2 */
+	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED);     /* disable GPIRQ10 */
+
+	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);               /* Map PCI hostbridge INT to NMI */
+	write_mmcr_word(SC520_ECCMAP, 0x100);                   /* Map SDRAM ECC failure INT to NMI */
+
+}
+
+
+/* PCI stuff */
+static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	int version = read_mmcr_byte(SC520_SYSINFO);
+
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CFG_FIRST_PCI_IRQ,
+		CFG_SECOND_PCI_IRQ,
+		CFG_THIRD_PCI_IRQ,
+		CFG_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+
+	char tmp_pin;
+	int pin;
+
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
+
+
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 6:  /* ETH0 */
+		pin+=SC520_PCI_INTA;
+		break;
+
+	case 7:  /* ETH1 */
+		pin+=SC520_PCI_INTB;
+		break;
+
+	case 8:  /* Crypto */
+		pin+=SC520_PCI_INTC;
+		break;
+
+	case 9: /* PMC slot */
+		pin+=SC520_PCI_INTD;
+		break;
+
+	case 10: /* PC-Card */
+
+		if (version < 10) {
+			pin+=SC520_PCI_INTD;
+		} else {
+			pin+=SC520_PCI_INTC;
+		}
+		break;
+
+	default:
+		return;
+	}
+
+	pin&=3; /* wrap around */
+
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+			return;
+		}
+		next_irq_index++;
+	}
+
+
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+					   sc520_pci_ints[pin]);
+	}
+#if 0
+	printf("fixup_irq: device %d pin %c irq %d\n",
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+#endif
+}
+
+
+static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
+					      pci_dev_t dev, struct pci_config_table *te)
+{
+	u32 io_base;
+	u32 temp;
+
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
+	pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
+	pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
+	pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
+	pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
+
+	pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */
+	pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */
+	/* route MF0 to ~INT and MF3 to IRQ7
+	 * reserve all others */
+	pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
+	pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
+	pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
+
+	if (te->device != 0xac56) {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
+		pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
+	} else {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
+	}
+	pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
+
+
+	pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
+	io_base &= ~0xfL;
+
+	writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
+	writel(0, io_base+0x10);     /* CLKRUN default */
+	writel(0, io_base+0x20);     /* CLKRUN default */
+
+}
+
+
+static struct pci_config_table pci_sc520_spunk_config_table[] = {
+	{ 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
+	{ 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
+	{ 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
+};
+
+static struct pci_controller sc520_spunk_hose = {
+	fixup_irq: pci_sc520_spunk_fixup_irq,
+	config_table: pci_sc520_spunk_config_table,
+	first_busno: 0x00,
+	last_busno: 0xff,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&sc520_spunk_hose);
+}
+
+
+/* set up the ISA bus timing and system address mappings */
+static void bus_init(void)
+{
+	/* versions
+	 * 0   Hyglo versions 0.95 and 0.96 (large baords)
+	 * ??  Hyglo version 0.97 (small board)
+	 * 10  Spunk board
+	 */
+	int version = read_mmcr_byte(SC520_SYSINFO);
+
+	if (version) {
+		/* set up the GP IO pins (for the Spunk board) */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); 	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0,  0x000f);  	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x000f); 	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);  	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0xc0);  		/* set the CS pin function reg */
+		write_mmcr_byte(SC520_CLKSEL, 0x70);
+
+		write_mmcr_word(SC520_PIOCLR31_16, 0x0003);     /* reset SSI chip-selects */
+		write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+
+	} else {
+		/* set up the GP IO pins (for the Hyglo board) */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); 	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f);  	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x003f); 	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0, 0xe180);  	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0x00);  		/* set the CS pin function reg */
+		write_mmcr_byte(SC520_CLKSEL, 0x70);
+
+		write_mmcr_word(SC520_PIOCLR15_0, 0x0180);      /* reset SSI chip-selects */
+	}
+
+	write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
+	write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
+	write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
+	write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
+	write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
+	write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
+	write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
+
+	write_mmcr_word(SC520_BOOTCSCTL, 0x0407);		/* set up timing of BOOTCS */
+
+	/* adjust the memory map:
+	 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
+	 * and 256MB to 1G-128k  (0x1000000 - 0x37ffffff) is mapped to PCI mmio
+	 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
+
+
+	/* bootcs */
+	write_mmcr_long(SC520_PAR12, 0x8bffe800);
+
+	/* IDE0 = GPCS6 1f0-1f7 */
+	write_mmcr_long(SC520_PAR3,  0x380801f0);
+
+	/* IDE1 = GPCS7 3f6 */
+	write_mmcr_long(SC520_PAR4,  0x3c0003f6);
+
+	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
+
+	write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
+
+}
+
+
+/* par usage:
+ * PAR0   (legacy_video)
+ * PAR1   (PCI ROM mapping)
+ * PAR2
+ * PAR3   IDE
+ * PAR4   IDE
+ * PAR5   (legacy_video)
+ * PAR6
+ * PAR7   (legacy_video)
+ * PAR8   (legacy_video)
+ * PAR9   (legacy_video)
+ * PAR10
+ * PAR11  (ISAROM)
+ * PAR12  BOOTCS
+ * PAR13
+ * PAR14
+ * PAR15
+ */
+
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ *
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size)
+{
+	u32 par;
+
+	printf("isa_map_rom asked to map %d bytes at %x\n",
+	       size, bus_addr);
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+
+	printf ("setting PAR11 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR11,  par);
+
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	printf("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
+		write_mmcr_long(SC520_PAR11, 0);
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+}
+
+#ifdef CONFIG_PCI
+#define PCI_ROM_TEMP_SPACE 0x10000
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size)
+{
+	u32 par;
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+
+	printf ("setting PAR1 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR1,  par);
+
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	printf("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		write_mmcr_long(SC520_PAR1, 0);
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus.
+ * After this function accesses to I/O ports 0x3b0-0x3bb and
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ *
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	write_mmcr_long(SC520_PAR0,  0x7200400a);
+
+	/* forward all I/O accesses to PCI */
+	write_mmcr_byte(SC520_ADDDECCTL,
+			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
+
+
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers
+	 */
+
+	/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
+	write_mmcr_long(SC520_PAR5, 0x31f70100);
+
+	/* com2 use 2f8-2ff */
+
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	write_mmcr_long(SC520_PAR7, 0x30af0300);
+
+	/* vga use 3b0-3bb */
+
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	write_mmcr_long(SC520_PAR8, 0x300303bc);
+
+	/* vga use 3c0-3df */
+
+	/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
+	write_mmcr_long(SC520_PAR9, 0x301703e0);
+
+	/* com1 use 3f8-3ff */
+
+	return 0;
+}
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	init_sc520();
+	bus_init();
+	irq_init();
+
+	/* max drive current on SDRAM */
+	write_mmcr_word(SC520_DSCTL, 0x0100);
+
+	/* enter debug mode after next reset (only if jumper is also set) */
+	write_mmcr_byte(SC520_RESCFG, 0x08);
+	/* configure the software timer to 33.000MHz */
+	write_mmcr_byte(SC520_SWTMRCFG, 1);
+	gd->bus_clk = 33000000;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	init_sc520_dram();
+	return 0;
+}
+
+void show_boot_progress(int val)
+{
+	int version = read_mmcr_byte(SC520_SYSINFO);
+
+	if (version == 0) {
+		/* PIO31-PIO16 Data */
+		write_mmcr_word(SC520_PIODATA31_16,
+				(read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
+
+		/* PIO0-PIO15 Data */
+		write_mmcr_word(SC520_PIODATA15_0,
+				(read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
+	} else {
+		/* newer boards use PIO4-PIO12 */
+		/* PIO0-PIO15 Data */
+#if 0
+		val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3);
+#else
+		val = (val & 0x007) | ((val & 0x07e) << 2);
+#endif
+		write_mmcr_word(SC520_PIODATA15_0,
+				(read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
+	}
+}
+
+
+int last_stage_init(void)
+{
+
+	int version = read_mmcr_byte(SC520_SYSINFO);
+
+	printf("Omicron Ceti SC520 Spunk revision %x\n", version);
+
+#if 0
+	if (version) {
+		int x, y;
+
+		printf("eeprom probe %d\n", spi_eeprom_probe(1));
+
+		spi_eeprom_read(1, 0, (u8*)&x, 2);
+		spi_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+		x ^= 0xffff;
+		y ^= 0xffff;
+		spi_eeprom_write(1, 0, (u8*)&x, 2);
+		spi_eeprom_write(1, 1, (u8*)&y, 2);
+
+		spi_eeprom_read(1, 0, (u8*)&x, 2);
+		spi_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+
+	} else {
+		int x, y;
+
+		printf("eeprom probe %d\n", mw_eeprom_probe(1));
+
+		mw_eeprom_read(1, 0, (u8*)&x, 2);
+		mw_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+
+		x ^= 0xffff;
+		y ^= 0xffff;
+		mw_eeprom_write(1, 0, (u8*)&x, 2);
+		mw_eeprom_write(1, 1, (u8*)&y, 2);
+
+		mw_eeprom_read(1, 0, (u8*)&x, 2);
+		mw_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+
+
+	}
+#endif
+
+	ds1722_probe(2);
+
+	return 0;
+}
+
+void ssi_chip_select(int dev)
+{
+	int version = read_mmcr_byte(SC520_SYSINFO);
+
+	if (version) {
+		/* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
+		switch (dev) {
+		case 1: /* EEPROM */
+			write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
+			break;
+
+		case 2: /* Temp Probe */
+			write_mmcr_word(SC520_PIOSET31_16, 0x0002);
+			break;
+
+		case 3: /* CAN */
+			write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
+			break;
+
+		case 4: /* AUX */
+			write_mmcr_word(SC520_PIOSET31_16, 0x0001);
+			break;
+
+		case 0:
+			write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
+			write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+			break;
+
+		default:
+			printf("Illegal SSI device requested: %d\n", dev);
+		}
+	} else {
+
+		/* Globox board: Both EEPROM and TEMP are active-high */
+
+		switch (dev) {
+		case 1: /* EEPROM */
+			write_mmcr_word(SC520_PIOSET15_0, 0x0100);
+			break;
+
+		case 2: /* Temp Probe */
+			write_mmcr_word(SC520_PIOSET15_0, 0x0080);
+			break;
+
+		case 0:
+			write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
+			break;
+
+		default:
+			printf("Illegal SSI device requested: %d\n", dev);
+		}
+	}
+}
+
+
+void spi_init_f(void)
+{
+	read_mmcr_byte(SC520_SYSINFO) ?
+		spi_eeprom_probe(1) :
+	mw_eeprom_probe(1);
+
+}
+
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
+{
+	int offset;
+	int i;
+
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+
+	return 	read_mmcr_byte(SC520_SYSINFO) ?
+		spi_eeprom_read(1, offset, buffer, len) :
+	mw_eeprom_read(1, offset, buffer, len);
+}
+
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
+{
+	int offset;
+	int i;
+
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+
+	return 	read_mmcr_byte(SC520_SYSINFO) ?
+		spi_eeprom_write(1, offset, buffer, len) :
+	mw_eeprom_write(1, offset, buffer, len);
+}
diff --git a/board/sc520_spunk/sc520_spunk_asm.S b/board/sc520_spunk/sc520_spunk_asm.S
new file mode 100755
index 0000000..8b34103
--- /dev/null
+++ b/board/sc520_spunk/sc520_spunk_asm.S
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* now setup the General purpose bus to give us access to the LEDs.
+ * We can then use the leds to display status information.
+ */
+
+sc520_cdp_registers:
+/* size    offset        value */
+.word 1 ; .word 0x040 ; .long 0x00       /* SDRAM buffer control */
+.word 2 ; .word 0xc08 ; .long 0x0001     /* GP CS offset */
+.word 2 ; .word 0xc09 ; .long 0x0003     /* GP CS width */
+.word 2 ; .word 0xc0a ; .long 0x0001     /* GP CS width */
+.word 2 ; .word 0xc0b ; .long 0x0003     /* GP RD pulse width */
+.word 2 ; .word 0xc0c ; .long 0x0001     /* GP RD offse */
+.word 2 ; .word 0xc0d ; .long 0x0003     /* GP WR pulse width */
+.word 2 ; .word 0xc0e ; .long 0x0001     /* GP WR offset */
+.word 2 ; .word 0xc2c ; .long 0x003f     /* GPIO directionreg 31-16 */
+.word 2 ; .word 0xc2a ; .long 0xe000     /* GPIO directionreg 15-0 */
+.word 2 ; .word 0xc22 ; .long 0xffc0     /* GPIO pin function 31-16 reg */
+.word 2 ; .word 0xc20 ; .long 0x1fff     /* GPIO pin function 15-0 reg */
+.word 0 ; .word 0x000 ; .long 0x00
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+	movl    $sc520_cdp_registers,%esi
+init_loop:
+	movl    $0xfffef000,%edi     /* MMCR base to edi */
+	movw	(%esi), %bx          /* load size to bx */
+	cmpw	$0, %bx              /* if size is 0 we're done */
+	je	done
+	xorl	%edx,%edx
+	movw	2(%esi), %dx        /* load MMCR offset to dx */
+	addl	%edx, %edi          /* add offset to base in edi */
+	movl	4(%esi), %eax       /* load value in eax */
+	cmpw	$1, %bx
+	je	byte                 /* byte op? */
+	cmpw	$2, %bx
+	je	word                 /* word op? */
+	movl	%eax, (%edi)         /* must be long, then */
+	jmp	next
+byte:   movb    %al,(%edi)
+	jmp	next
+word:	movw	%ax,(%edi)
+next:	addl	$8, %esi             /* advance esi */
+	jmp	init_loop
+
+	/* light all leds */
+done:   movl    $0xfffefc32,%edx
+	movw    $0000,(%edx)
+
+	jmp 	*%ebp		     /* return to caller */
+
+
+.globl __show_boot_progress
+__show_boot_progress:
+	movl    $0xfffefc32,%edx
+	xorw    $0xffff, %ax
+	movw    %ax,(%edx)
+	jmp	*%ebp
diff --git a/board/sc520_spunk/sc520_spunk_asm16.S b/board/sc520_spunk/sc520_spunk_asm16.S
new file mode 100755
index 0000000..8bb1766
--- /dev/null
+++ b/board/sc520_spunk/sc520_spunk_asm16.S
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 16bit initialization code.
+ * This code have to map the area of the boot flash
+ * that is used by U-boot to its final destination.
+ */
+
+.text
+.section .start16, "ax"
+.code16
+.globl board_init16
+board_init16:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax
+	outl	%eax, %dx
+
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax
+	movw	%ax, %ds
+
+	/* Map the entire flash at 0x38000000
+	 * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */
+	movl    $0xc0, %edi
+	movl	$0x8bfff800, %eax
+	movl	%eax, (%di)
+
+	/* Disable SDRAM write buffer */
+	movw    $0x40,%di
+	xorw    %ax,%ax
+	movb    %al, (%di)
+
+	/* Disabe MMCR alias */
+	movw	$0xfffc, %dx
+	movl	$0x000000cb, %eax
+	outl	%eax, %dx
+
+	/* the return address is stored in bp */
+	jmp	*%bp
+
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+realmode_reset:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax
+	outl	%eax, %dx
+
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax
+	movw	%ax, %ds
+
+	/* issue software reset thorugh MMCR */
+	movl    $0xd72, %edi
+	movb	$0x01, %al
+	movb	%al, (%di)
+
+1:	hlt
+	jmp	1
diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds
new file mode 100755
index 0000000..127d707
--- /dev/null
+++ b/board/sc520_spunk/u-boot.lds
@@ -0,0 +1,92 @@
+
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0x387c0000;                     /* Where bootcode in the flash is mapped */
+	.text  : { *(.text); }
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = 0x400000; 	                    /* Ram data segment to use */
+	_i386boot_romdata_dest = ABSOLUTE(.);
+	.data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
+	_i386boot_romdata_start = LOADADDR(.data);
+
+	. = ALIGN(4);
+	.got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
+	_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got);
+
+
+	. = ALIGN(4);
+	_i386boot_bss_start = ABSOLUTE(.);
+	.bss : { *(.bss) }
+	_i386boot_bss_size = SIZEOF(.bss);
+
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+	/* 16bit realmode trampoline code */
+	.realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) }
+
+	_i386boot_realmode = LOADADDR(.realmode);
+	_i386boot_realmode_size = SIZEOF(.realmode);
+
+	/* 16bit BIOS emulation code (just enough to boot Linux) */
+	.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
+
+	_i386boot_bios = LOADADDR(.bios);
+	_i386boot_bios_size = SIZEOF(.bios);
+
+
+	/* The load addresses below assumes that the flash
+	 * will be mapped so that 0x387f0000 == 0xffff0000
+	 * at reset time
+	 *
+	 * The fe00 and ff00 offsets of the start32 and start16
+	 * segments are arbitrary, the just have to be mapped
+	 * at reset and the code have to fit.
+	 * The fff0 offset of reset is important, however.
+	 */
+
+
+	. = 0xfffffe00;
+	.start32 : AT (0x387ffe00) { *(.start32); }
+
+	. = 0xff00;
+	.start16 : AT (0x387fff00) { *(.start16); }
+
+	. = 0xfff0;
+	.reset : AT (0x387ffff0) { *(.reset); }
+	_i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
+}
diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile
new file mode 100755
index 0000000..5dc3fd4
--- /dev/null
+++ b/board/scb9328/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= scb9328.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/scb9328/config.mk b/board/scb9328/config.mk
new file mode 100755
index 0000000..8d1d79a
--- /dev/null
+++ b/board/scb9328/config.mk
@@ -0,0 +1,10 @@
+#
+# This config file is used for compilation of scb93328 sources
+#
+# You might change location of U-Boot in memory by setting right TEXT_BASE.
+# This allows for example having one copy located at the end of ram and stored
+# in flash device and later on while developing use other location to test
+# the code in RAM device only.
+#
+
+TEXT_BASE = 0x08f00000
diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c
new file mode 100755
index 0000000..1b56f8c
--- /dev/null
+++ b/board/scb9328/flash.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This code was inspired by Marius Groeger and Kyle Harris code
+ * available in other board ports for U-Boot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ */
+
+#include <common.h>
+#include "intel.h"
+
+
+/*
+ * This code should handle CFI FLASH memory device. This code is very
+ * minimalistic approach without many essential error handling code as well.
+ * Because U-Boot actually is missing smart handling of FLASH device,
+ * we just set flash_id to anything else to FLASH_UNKNOW, so common code
+ * can call us without any restrictions.
+ * TODO: Add CFI Query, to be able to determine FLASH device.
+ * TODO: Add error handling code
+ * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
+ *       hopefully may work with other configurations.
+ */
+
+#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
+#  define FLASH_BUS vu_char
+#  if ( SCB9328_FLASH_INTERLEAVE == 1 )
+#    define FLASH_CMD( x ) x
+#  else
+#    error "With 8bit bus only one chip is allowed"
+#  endif
+
+
+#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
+#  define FLASH_BUS vu_short
+#  if ( SCB9328_FLASH_INTERLEAVE == 1 )
+#    define FLASH_CMD( x ) x
+#  elif ( SCB9328_FLASH_INTERLEAVE == 2 )
+#    define FLASH_CMD( x ) (( x << 8 )| x )
+#  else
+#    error "With 16bit bus only 1 or 2 chip(s) are allowed"
+#  endif
+
+
+#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
+#  define FLASH_BUS vu_long
+#  if ( SCB9328_FLASH_INTERLEAVE == 1 )
+#    define FLASH_CMD( x ) x
+#  elif ( SCB9328_FLASH_INTERLEAVE == 2 )
+#    define FLASH_CMD( x ) (( x << 16 )| x )
+#  elif ( SCB9328_FLASH_INTERLEAVE == 4 )
+#    define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
+#  else
+#    error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
+#  endif
+
+#else
+#  error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
+#endif
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+static FLASH_BUS flash_status_reg (void)
+{
+
+	FLASH_BUS *addr = (FLASH_BUS *) 0;
+
+	*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
+
+	return *addr;
+}
+
+static int flash_ready (ulong timeout)
+{
+	int ok = 1;
+
+	reset_timer_masked ();
+	while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
+		   FLASH_CMD (CFI_INTEL_SR_READY)) {
+		if (get_timer_masked () > timeout && timeout != 0) {
+			ok = 0;
+			break;
+		}
+	}
+	return ok;
+}
+
+#if ( CFG_MAX_FLASH_BANKS != 1 )
+#  error "SCB9328 platform has only one flash bank!"
+#endif
+
+
+ulong flash_init (void)
+{
+	int i;
+	unsigned long address = SCB9328_FLASH_BASE;
+
+	flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
+	flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
+	flash_info[0].flash_id = INTEL_MANUFACT;
+	memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
+
+	for (i = 0; i < CFG_MAX_FLASH_SECT; i++) {
+		flash_info[0].start[i] = address;
+#ifdef SCB9328_FLASH_UNLOCK
+		/* Some devices are hw locked after start. */
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
+		flash_ready (0);
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+#endif
+		address += SCB9328_FLASH_SECT_SIZE;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+				   CFG_FLASH_BASE,
+				   CFG_FLASH_BASE + monitor_flash_len - 1,
+				   &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+				   CFG_ENV_ADDR,
+				   CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return SCB9328_FLASH_BANK_SIZE;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	printf (" Intel vendor\n");
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if (!(i % 5)) {
+			printf ("\n");
+		}
+
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, non_protected = 0, sector;
+	int rc = ERR_OK;
+
+	FLASH_BUS *address;
+
+	for (sector = s_first; sector <= s_last; sector++) {
+		if (!info->protect[sector]) {
+			non_protected++;
+		}
+	}
+
+	if (!non_protected) {
+		return ERR_PROTECTED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+
+	/* Start erase on unprotected sectors */
+	for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
+		if (info->protect[sector]) {
+			printf ("Protected sector %2d skipping...\n", sector);
+			continue;
+		} else {
+			printf ("Erasing sector %2d ... ", sector);
+		}
+
+		address = (FLASH_BUS *) (info->start[sector]);
+
+		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
+		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
+		if (flash_ready (CFG_FLASH_ERASE_TOUT)) {
+			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+			printf ("ok.\n");
+		} else {
+			*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+			rc = ERR_TIMOUT;
+			printf ("timeout! Aborting...\n");
+			break;
+		}
+		*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+	if (flag) {
+		enable_interrupts ();
+	}
+
+	return rc;
+}
+
+static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
+{
+	FLASH_BUS *address = (FLASH_BUS *) dest;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*address & data) != data) {
+		return ERR_NOT_ERASED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	flag = disable_interrupts ();
+
+	*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
+	*address = data;
+
+	if (!flash_ready (CFG_FLASH_WRITE_TOUT)) {
+		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+		rc = ERR_TIMOUT;
+		printf ("timeout! Aborting...\n");
+	}
+
+	*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+	if (flag) {
+		enable_interrupts ();
+	}
+
+	return rc;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong read_addr, write_addr;
+	FLASH_BUS data;
+	int i, result = ERR_OK;
+
+
+	read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
+	write_addr = read_addr;
+	if (read_addr != addr) {
+		data = 0;
+		for (i = 0; i < sizeof (FLASH_BUS); i++) {
+			if (read_addr < addr || cnt == 0) {
+				data |= *((uchar *) read_addr) << i * 8;
+			} else {
+				data |= (*src++) << i * 8;
+				cnt--;
+			}
+			read_addr++;
+		}
+		if ((result = write_data (info, write_addr, data)) != ERR_OK) {
+			return result;
+		}
+		write_addr += sizeof (FLASH_BUS);
+	}
+	for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
+		if ((result = write_data (info, write_addr,
+								  *((FLASH_BUS *) src))) != ERR_OK) {
+			return result;
+		}
+		write_addr += sizeof (FLASH_BUS);
+		src += sizeof (FLASH_BUS);
+	}
+	if (cnt > 0) {
+		read_addr = write_addr;
+		data = 0;
+		for (i = 0; i < sizeof (FLASH_BUS); i++) {
+			if (cnt > 0) {
+				data |= (*src++) << i * 8;
+				cnt--;
+			} else {
+				data |= *((uchar *) read_addr) << i * 8;
+			}
+			read_addr++;
+		}
+		if ((result = write_data (info, write_addr, data)) != 0) {
+			return result;
+		}
+	}
+	return ERR_OK;
+}
diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h
new file mode 100755
index 0000000..77498b6
--- /dev/null
+++ b/board/scb9328/intel.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef	FLASH_INTEL_H
+#define	FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define	CFI_CHIP_INTEL_28F320J3A		0x0016
+#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
+#define	CFI_CHIP_INTEL_28F640J3A		0x0017
+#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
+#define	CFI_CHIP_INTEL_28F128J3A		0x0018
+#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define	CFI_CHIP_INTEL_28F640K3			0x8801
+#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
+#define	CFI_CHIP_INTEL_28F128K3			0x8802
+#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
+#define	CFI_CHIP_INTEL_28F256K3			0x8803
+#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
+#define	CFI_CHIP_INTEL_28F640K18		0x8805
+#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
+#define	CFI_CHIP_INTEL_28F128K18		0x8806
+#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
+#define	CFI_CHIP_INTEL_28F256K18		0x8807
+#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
+
+#endif /* FLASH_INTEL_H */
diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S
new file mode 100755
index 0000000..ba3b6d2
--- /dev/null
+++ b/board/scb9328/lowlevel_init.S
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+	ldr		r0,	=PCDR
+	ldr		r1,	=CFG_PCDR_VAL
+	str		r1,   [r0]
+
+/* set MCU PLL Control Register 0 */
+
+	ldr		r0,	=MPCTL0
+	ldr		r1,	=CFG_MPCTL0_VAL
+	str		r1,   [r0]
+
+/* set mpll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<21)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+/* set System PLL Control Register 0 */
+
+	ldr		r0,	=SPCTL0
+	ldr		r1,	=CFG_SPCTL0_VAL
+	str		r1,   [r0]
+
+/* set spll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<22)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+	ldr		r0,   =CSCR
+	ldr		r1,   =CFG_CSCR_VAL
+	str		r1,   [r0]
+
+/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ *this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too!  Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+
+ * Slapping this into my bootloader does the trick...
+
+ * MRC p15,0,r0,c1,c0,0    ; read core configuration register
+ * ORR r0,r0,#0xC0000000   ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0    ; write modified value to core configuration
+ * register
+ */
+	MRC p15,0,r0,c1,c0,0
+	ORR r0,r0,#0xC0000000
+	MCR p15,0,r0,c1,c0,0
+
+	ldr		r0,	=GPR(0)
+	ldr		r1,	=CFG_GPR_A_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GIUS(0)
+	ldr		r1,	=CFG_GIUS_A_VAL
+	str		r1,   [r0]
+
+/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
+
+	ldr		r0,	=FMCR
+	ldr		r1,	=CFG_FMCR_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0U
+	ldr		r1,	=CFG_CS0U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0L
+	ldr		r1,	=CFG_CS0L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1U
+	ldr		r1,	=CFG_CS1U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1L
+	ldr		r1,	=CFG_CS1L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS2U
+	ldr		r1,	=CFG_CS2U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS2L
+	ldr		r1,	=CFG_CS2L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS3U
+	ldr		r1,	=CFG_CS3U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS3L
+	ldr		r1,	=CFG_CS3L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4U
+	ldr		r1,	=CFG_CS4U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4L
+	ldr		r1,	=CFG_CS4L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5U
+	ldr		r1,	=CFG_CS5U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5L
+	ldr		r1,	=CFG_CS5L_VAL
+	str		r1,   [r0]
+
+/* SDRAM Setup */
+
+	ldr		r0, =SDCTL0
+	ldr		r1, =PRECHARGE_CMD
+	str		r1,   [r0]
+
+	ldr		r0, =0x08200000
+	ldr		r1, =0x0 /* Issue Precharge all Command */
+	str		r1,   [r0]
+
+	ldr		r0, =SDCTL0
+	ldr		r1, =AUTOREFRESH_CMD
+	str		r1,   [r0]
+
+	ldr		r0, =0x08000000
+	ldr		r1, =0x0 /* Issue AutoRefresh Command */
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+	str		r1,   [r0]
+
+	ldr		r0, =SDCTL0
+	ldr		r1, =0xb10a8300
+	str		r1,   [r0]
+
+	ldr		r0, =0x08223000 /* CAS Latency 2 */
+	ldr		r1, =0x0   /* Issue Mode Register Command, Burst Length = 8 */
+	str		r1,   [r0]
+
+	ldr		r0, =SDCTL0
+	ldr		r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
+	str		r1,   [r0]
+
+	mov	pc,r10
diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c
new file mode 100755
index 0000000..3ed8753
--- /dev/null
+++ b/board/scb9328/scb9328.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+int board_init( void ){
+  DECLARE_GLOBAL_DATA_PTR;
+
+  gd->bd->bi_arch_number = MACH_TYPE_SCB9328;
+  gd->bd->bi_boot_params = 0x08000100;
+
+  return 0;
+}
+
+int dram_init( void ){
+  DECLARE_GLOBAL_DATA_PTR;
+
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+  gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
+  gd->bd->bi_dram[0].size  = SCB9328_SDRAM_1_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 1 )
+  gd->bd->bi_dram[1].start = SCB9328_SDRAM_2;
+  gd->bd->bi_dram[1].size  = SCB9328_SDRAM_2_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 2 )
+  gd->bd->bi_dram[2].start = SCB9328_SDRAM_3;
+  gd->bd->bi_dram[2].size  = SCB9328_SDRAM_3_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 3 )
+  gd->bd->bi_dram[3].start = SCB9328_SDRAM_4;
+  gd->bd->bi_dram[3].size  = SCB9328_SDRAM_4_SIZE;
+#endif
+
+  return 0;
+}
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ * The CSB226 does only have 3 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
+ */
+
+void show_boot_progress (int status)
+{
+	return;
+}
diff --git a/board/scb9328/u-boot.lds b/board/scb9328/u-boot.lds
new file mode 100755
index 0000000..1d1669c
--- /dev/null
+++ b/board/scb9328/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/arm920t/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/shannon/Makefile b/board/shannon/Makefile
new file mode 100755
index 0000000..f66b096
--- /dev/null
+++ b/board/shannon/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= shannon.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/shannon/config.mk b/board/shannon/config.mk
new file mode 100755
index 0000000..ca45733
--- /dev/null
+++ b/board/shannon/config.mk
@@ -0,0 +1,23 @@
+#
+# LART board with SA1100 cpu
+#
+# see http://www.lart.tudelft.nl/ for more information on LART
+#
+
+#
+# Tuxscreen has 4 banks of 4 MB DRAM each
+#
+# c000'0000
+# c800'0000
+# d000'0000
+# d800'0000
+#
+# Linux-Kernel is expected to be at c000'8000, entry c000'8000
+#
+# we load ourself to d838'0000, the upper 1 MB of the last (4th) bank
+#
+# download areas is c800'0000
+#
+
+
+TEXT_BASE = 0xd8380000
diff --git a/board/shannon/flash.c b/board/shannon/flash.c
new file mode 100755
index 0000000..13c01d8
--- /dev/null
+++ b/board/shannon/flash.c
@@ -0,0 +1,473 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush(void);
+
+
+#define FLASH_BANK_SIZE 0x400000	/* 4 MB */
+#define MAIN_SECT_SIZE  0x20000		/* 128 KB */
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00F000F0
+#define CMD_UNLOCK1		0x00AA00AA
+#define CMD_UNLOCK2		0x00550055
+#define CMD_ERASE_SETUP		0x00800080
+#define CMD_ERASE_CONFIRM	0x00300030
+#define CMD_PROGRAM		0x00A000A0
+#define CMD_UNLOCK_BYPASS	0x00200020
+
+#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
+#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
+
+#define BIT_ERASE_DONE		0x00800080
+#define BIT_RDY_MASK		0x00800080
+#define BIT_PROGRAM_ERROR	0x00200020
+#define BIT_TIMEOUT		0x80000000 /* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init(void)
+{
+    int i, j;
+    ulong size = 0;
+
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    {
+	ulong flashbase = 0;
+	flash_info[i].flash_id =
+	  (AMD_MANUFACT & FLASH_VENDMASK) |
+	  (AMD_ID_LV160B & FLASH_TYPEMASK);
+	flash_info[i].size = FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	if (i == 0)
+	  flashbase = PHYS_FLASH_1;
+	else
+	  panic("configured too many flash banks!\n");
+	for (j = 0; j < flash_info[i].sector_count; j++)
+	{
+
+	    if (j <= 3)
+	    {
+		/* 1st one is 32 KB */
+		if (j == 0)
+		{
+			flash_info[i].start[j] = flashbase + 0;
+		}
+
+		/* 2nd and 3rd are both 16 KB */
+		if ((j == 1) || (j == 2))
+		{
+			flash_info[i].start[j] = flashbase + 0x8000 + (j-1)*0x4000;
+		}
+
+		/* 4th 64 KB */
+		if (j == 3)
+		{
+			flash_info[i].start[j] = flashbase + 0x10000;
+		}
+	    }
+	    else
+	    {
+		flash_info[i].start[j] = flashbase + (j - 3)*MAIN_SECT_SIZE;
+	    }
+	}
+	size += flash_info[i].size;
+    }
+
+    /*
+     * Protect monitor and environment sectors
+     * Inferno is complicated, it's hardware locked
+     */
+#ifdef CONFIG_INFERNO
+    /* first one, 0x00000 to 0x07fff */
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_FLASH_BASE + 0x00000,
+		  CFG_FLASH_BASE + 0x08000 - 1,
+		  &flash_info[0]);
+
+    /* third to 10th, 0x0c000 - 0xdffff */
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_FLASH_BASE + 0x0c000,
+		  CFG_FLASH_BASE + 0xe0000 - 1,
+		  &flash_info[0]);
+#else
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_FLASH_BASE,
+		  CFG_FLASH_BASE + monitor_flash_len - 1,
+		  &flash_info[0]);
+
+    flash_protect(FLAG_PROTECT_SET,
+		  CFG_ENV_ADDR,
+		  CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		  &flash_info[0]);
+#endif
+    return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+
+    switch (info->flash_id & FLASH_VENDMASK)
+    {
+    case (AMD_MANUFACT & FLASH_VENDMASK):
+	printf("AMD: ");
+	break;
+    default:
+	printf("Unknown Vendor ");
+	break;
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK)
+    {
+    case (AMD_ID_LV160B & FLASH_TYPEMASK):
+	printf("2x Amd29F160BB (16Mbit)\n");
+	break;
+    default:
+	printf("Unknown Chip Type\n");
+	goto Done;
+	break;
+    }
+
+    printf("  Size: %ld MB in %d Sectors\n",
+	   info->size >> 20, info->sector_count);
+
+    printf("  Sector Start Addresses:");
+    for (i = 0; i < info->sector_count; i++)
+    {
+	if ((i % 5) == 0)
+	{
+	    printf ("\n   ");
+	}
+	printf (" %08lX%s", info->start[i],
+		info->protect[i] ? " (RO)" : "     ");
+    }
+    printf ("\n");
+
+Done:
+    ;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+    ulong result;
+    int iflag, cflag, prot, sect;
+    int rc = ERR_OK;
+    int chip1, chip2;
+
+    /* first look for protection bits */
+
+    if (info->flash_id == FLASH_UNKNOWN)
+	return ERR_UNKNOWN_FLASH_TYPE;
+
+    if ((s_first < 0) || (s_first > s_last)) {
+	return ERR_INVAL;
+    }
+
+    if ((info->flash_id & FLASH_VENDMASK) !=
+	(AMD_MANUFACT & FLASH_VENDMASK)) {
+	return ERR_UNKNOWN_FLASH_VENDOR;
+    }
+
+    prot = 0;
+    for (sect=s_first; sect<=s_last; ++sect) {
+	if (info->protect[sect]) {
+	    prot++;
+	}
+    }
+    if (prot)
+	return ERR_PROTECTED;
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect<=s_last && !ctrlc(); sect++)
+    {
+	printf("Erasing sector %2d ... ", sect);
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked();
+
+	if (info->protect[sect] == 0)
+	{	/* not protected */
+	    vu_long *addr = (vu_long *)(info->start[sect]);
+
+	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	    MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+	    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	    *addr = CMD_ERASE_CONFIRM;
+
+	    /* wait until flash is ready */
+	    chip1 = chip2 = 0;
+
+	    do
+	    {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+		{
+		    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+		    chip1 = TMO;
+		    break;
+		}
+
+		if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
+			chip1 = READY;
+
+		if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+			chip1 = ERR;
+
+		if (!chip2 && (result >> 16) & BIT_ERASE_DONE)
+			chip2 = READY;
+
+		if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR)
+			chip2 = ERR;
+
+	    }  while (!chip1 || !chip2);
+
+	    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+	    if (chip1 == ERR || chip2 == ERR)
+	    {
+		rc = ERR_PROG_ERROR;
+		goto outahere;
+	    }
+	    if (chip1 == TMO)
+	    {
+		rc = ERR_TIMOUT;
+		goto outahere;
+	    }
+
+	    printf("ok.\n");
+	}
+	else /* it was protected */
+	{
+	    printf("protected!\n");
+	}
+    }
+
+    if (ctrlc())
+      printf("User Interrupt!\n");
+
+outahere:
+    /* allow flash to settle - wait 10 ms */
+    udelay_masked(10000);
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long *)dest;
+    ulong result;
+    int rc = ERR_OK;
+    int cflag, iflag;
+    int chip1, chip2;
+
+    /*
+     * Check if Flash is (sufficiently) erased
+     */
+    result = *addr;
+    if ((result & data) != data)
+	return ERR_NOT_ERASED;
+
+
+    /*
+     * Disable interrupts which might cause a timeout
+     * here. Remember that our exception vectors are
+     * at address 0 in the flash, and we don't want a
+     * (ticker) exception to happen while the flash
+     * chip is in programming mode.
+     */
+    cflag = icache_status();
+    icache_disable();
+    iflag = disable_interrupts();
+
+    MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+    MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+    MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+    *addr = CMD_PROGRAM;
+    *addr = data;
+
+    /* arm simple, non interrupt dependent timer */
+    reset_timer_masked();
+
+    /* wait until flash is ready */
+    chip1 = chip2 = 0;
+    do
+    {
+	result = *addr;
+
+	/* check timeout */
+	if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+	{
+	    chip1 = ERR | TMO;
+	    break;
+	}
+	if (!chip1 && ((result & 0x80) == (data & 0x80)))
+		chip1 = READY;
+
+	if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR))
+	{
+		result = *addr;
+
+		if ((result & 0x80) == (data & 0x80))
+			chip1 = READY;
+		else
+			chip1 = ERR;
+	}
+
+	if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16))))
+		chip2 = READY;
+
+	if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR))
+	{
+		result = *addr;
+
+		if ((result & (0x80 << 16)) == (data & (0x80 << 16)))
+			chip2 = READY;
+		else
+			chip2 = ERR;
+	}
+
+    }  while (!chip1 || !chip2);
+
+    *addr = CMD_READ_ARRAY;
+
+    if (chip1 == ERR || chip2 == ERR || *addr != data)
+	rc = ERR_PROG_ERROR;
+
+    if (iflag)
+      enable_interrupts();
+
+    if (cflag)
+      icache_enable();
+
+    return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    int l;
+    int i, rc;
+
+    wp = (addr & ~3);	/* get lower word aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data >> 8) | (*src++ << 24);
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data >> 8) | (*(uchar *)cp << 24);
+	}
+
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = *((vu_long*)src);
+	if ((rc = write_word(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	src += 4;
+	wp  += 4;
+	cnt -= 4;
+    }
+
+    if (cnt == 0) {
+	return ERR_OK;
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data >> 8) | (*src++ << 24);
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data >> 8) | (*(uchar *)cp << 24);
+    }
+
+    return write_word(info, wp, data);
+}
diff --git a/board/shannon/inferno.header b/board/shannon/inferno.header
new file mode 100755
index 0000000..28ee85a
--- /dev/null
+++ b/board/shannon/inferno.header
diff --git a/board/shannon/lowlevel_init.S b/board/shannon/lowlevel_init.S
new file mode 100755
index 0000000..0655c42
--- /dev/null
+++ b/board/shannon/lowlevel_init.S
@@ -0,0 +1,92 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+MEM_BASE:	.long	0xa0000000
+MEM_START:	.long	0xc0000000
+
+#define	MDCNFG	0x00
+#define MDCAS0	0x04
+#define MDCAS1	0x08
+#define MDCAS2	0x0c
+#define MSC0	0x10
+#define MSC1	0x14
+#define MECR	0x18
+
+mdcas0:		.long	0xc71c703f @ cccccccf
+mdcas1:		.long	0xffc71c71 @ fffffffc
+mdcas2:		.long	0xffffffff @ ffffffff
+mdcnfg:		.long	0x0334b21f @ 9326991f
+msc0:		.long   0xfff84458 @ 42304230
+msc1:		.long	0xffffffff @ 20182018
+mecr:		.long	0x7fff7fff @ 01000000
+
+/* setting up the memory */
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	r0, MEM_BASE
+
+	/* Setup the flash memory */
+	ldr	r1, msc0
+	str	r1, [r0, #MSC0]
+
+	/* Set up the DRAM */
+
+	/* MDCAS0 */
+	ldr	r1, mdcas0
+	str	r1, [r0, #MDCAS0]
+
+	/* MDCAS1 */
+	ldr	r1, mdcas1
+	str	r1, [r0, #MDCAS1]
+
+	/* MDCAS2 */
+	ldr	r1, mdcas2
+	str	r1, [r0, #MDCAS2]
+
+	/* MDCNFG */
+	ldr	r1, mdcnfg
+	str	r1, [r0, #MDCNFG]
+
+	/* Set up PCMCIA space */
+	ldr	r1, mecr
+	str	r1, [r0, #MECR]
+
+	/* Load something to activate bank */
+	ldr	r1, MEM_START
+
+.rept	8
+	ldr	r0, [r1]
+.endr
+
+	/* everything is fine now */
+	mov	pc, lr
diff --git a/board/shannon/shannon.c b/board/shannon/shannon.c
new file mode 100755
index 0000000..0d9f146
--- /dev/null
+++ b/board/shannon/shannon.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* but if we use InfernoLoader, we must do some inits here */
+
+#ifdef CONFIG_INFERNO
+	{
+	unsigned long temp;
+	__asm__ __volatile__(/* disable MMU, enable icache */
+			     "mrc p15, 0, %0, c1, c0\n"
+			     "bic %0, %0, #0x00002000\n"
+			     "bic %0, %0, #0x0000000f\n"
+			     "orr %0, %0, #0x00001000\n"
+			     "orr %0, %0, #0x00000002\n"
+			     "mcr p15, 0, %0, c1, c0\n"
+			     /* flush caches */
+			     "mov %0, #0\n"
+			     "mcr p15, 0, %0, c7, c7, 0\n"
+			     "mcr p15, 0, %0, c8, c7, 0\n"
+			     : "=r" (temp)
+			     :
+			     : "memory");
+	/* setup PCMCIA timing */
+	temp = 0xa0000018;
+	*(unsigned long *)temp = 0x00060006;
+
+	}
+#endif /* CONFIG_INFERNO */
+
+	/* arch number for shannon */
+	gd->bd->bi_arch_number = MACH_TYPE_SHANNON;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+#if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \
+    defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4)
+	DECLARE_GLOBAL_DATA_PTR;
+	bd_t *bd = gd->bd;
+#endif
+
+#ifdef PHYS_SDRAM_1
+	bd->bi_dram[0].start = PHYS_SDRAM_1;
+	bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#endif
+
+#ifdef PHYS_SDRAM_2
+	bd->bi_dram[1].start = PHYS_SDRAM_2;
+	bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+
+#ifdef PHYS_SDRAM_3
+	bd->bi_dram[2].start = PHYS_SDRAM_3;
+	bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+#endif
+
+#ifdef PHYS_SDRAM_4
+	bd->bi_dram[3].start = PHYS_SDRAM_4;
+	bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+#endif
+
+	return (0);
+}
diff --git a/board/shannon/u-boot.lds b/board/shannon/u-boot.lds
new file mode 100755
index 0000000..258bece
--- /dev/null
+++ b/board/shannon/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/sa1100/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/siemens/CCM/Makefile b/board/siemens/CCM/Makefile
new file mode 100755
index 0000000..ee2fc53
--- /dev/null
+++ b/board/siemens/CCM/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= ccm.o flash.o fpga_ccm.o ../common/fpga.o \
+	  ../../tqm8xx/load_sernum_ethaddr.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c
new file mode 100755
index 0000000..5a32e45
--- /dev/null
+++ b/board/siemens/CCM/ccm.c
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+void can_driver_enable (void);
+void can_driver_disable (void);
+
+int fpga_init(void);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
+	0x1FF5FC47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Always return 1 (no second DRAM bank since based on TQM8xxL module)
+ */
+
+int checkboard (void)
+{
+    unsigned char *s;
+    unsigned char buf[64];
+
+    s = (getenv_r ("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL;
+
+    puts ("Board: Siemens CCM");
+
+    if (s) {
+	    puts (" (");
+
+	    for (; *s; ++s) {
+		if (*s == ' ')
+		    break;
+		putc (*s);
+	    }
+	    putc (')');
+    }
+
+    putc ('\n');
+
+    return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * If Power-On-Reset switch off the Red and Green LED: At reset, the
+ * data direction registers are cleared and must therefore be restored.
+ */
+#define RSR_CSRS	0x08000000
+
+int power_on_reset(void)
+{
+    /* Test Reset Status Register */
+    return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
+}
+
+#define PB_LED_GREEN	0x10000		/* red LED is on PB.15 */
+#define PB_LED_RED	0x20000		/* red LED is on PB.14 */
+#define PB_LEDS		(PB_LED_GREEN | PB_LED_RED);
+
+static void init_leds (void)
+{
+    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+
+    immap->im_cpm.cp_pbpar &= ~PB_LEDS;
+    immap->im_cpm.cp_pbodr &= ~PB_LEDS;
+    immap->im_cpm.cp_pbdir |=  PB_LEDS;
+    /* Check stop reset status */
+    if (power_on_reset()) {
+	    immap->im_cpm.cp_pbdat &= ~PB_LEDS;
+    }
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    long int size8, size9;
+    long int size = 0;
+    unsigned long reg;
+
+    upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+    /*
+     * Preliminary prescaler for refresh (depends on number of
+     * banks): This value is selected for four cycles every 62.4 us
+     * with two SDRAM banks or four cycles every 31.2 us with one
+     * bank. It will be adjusted after memory sizing.
+     */
+    memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+    memctl->memc_mar  = 0x00000088;
+
+    /*
+     * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+     * preliminary addresses - these have to be modified after the
+     * SDRAM size has been determined.
+     */
+    memctl->memc_or2 = CFG_OR2_PRELIM;
+    memctl->memc_br2 = CFG_BR2_PRELIM;
+
+    memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+
+    udelay(200);
+
+    /* perform SDRAM initializsation sequence */
+
+    memctl->memc_mcr  = 0x80004105;	/* SDRAM bank 0 */
+    udelay(1);
+    memctl->memc_mcr  = 0x80004230;	/* SDRAM bank 0 - execute twice */
+    udelay(1);
+
+    memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+    udelay (1000);
+
+    /*
+     * Check Bank 0 Memory Size for re-configuration
+     *
+     * try 8 column mode
+     */
+    size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+
+    udelay (1000);
+
+    /*
+     * try 9 column mode
+     */
+    size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+
+    if (size8 < size9) {		/* leave configuration at 9 columns	*/
+	size = size9;
+/*	debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20);	*/
+    } else {				/* back to 8 columns			*/
+	size = size8;
+	memctl->memc_mamr = CFG_MAMR_8COL;
+	udelay(500);
+/*	debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20);	*/
+    }
+
+    udelay (1000);
+
+    /*
+     * Adjust refresh rate depending on SDRAM type
+     * For types > 128 MBit leave it at the current (fast) rate
+     */
+    if (size < 0x02000000) {
+	/* reduce to 15.6 us (62.4 us / quad) */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+	udelay(1000);
+    }
+
+    /*
+     * Final mapping
+     */
+
+    memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+    memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+
+    /* adjust refresh rate depending on SDRAM type, one bank */
+    reg = memctl->memc_mptpr;
+    reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+    memctl->memc_mptpr = reg;
+
+    can_driver_enable ();
+    init_leds ();
+
+    udelay(10000);
+
+    return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Warning - both the PUMA load mode and the CAN driver use UPM B,
+ * so make sure only one of both is active.
+ */
+void can_driver_enable (void)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+    /* Initialize MBMR */
+    memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
+
+    /* Initialize UPMB for CAN: single read */
+    memctl->memc_mdr = 0xFFFFC004;
+    memctl->memc_mcr = 0x0100 | UPMB;
+
+    memctl->memc_mdr = 0x0FFFD004;
+    memctl->memc_mcr = 0x0101 | UPMB;
+
+    memctl->memc_mdr = 0x0FFFC000;
+    memctl->memc_mcr = 0x0102 | UPMB;
+
+    memctl->memc_mdr = 0x3FFFC004;
+    memctl->memc_mcr = 0x0103 | UPMB;
+
+    memctl->memc_mdr = 0xFFFFDC05;
+    memctl->memc_mcr = 0x0104 | UPMB;
+
+    /* Initialize UPMB for CAN: single write */
+    memctl->memc_mdr = 0xFFFCC004;
+    memctl->memc_mcr = 0x0118 | UPMB;
+
+    memctl->memc_mdr = 0xCFFCD004;
+    memctl->memc_mcr = 0x0119 | UPMB;
+
+    memctl->memc_mdr = 0x0FFCC000;
+    memctl->memc_mcr = 0x011A | UPMB;
+
+    memctl->memc_mdr = 0x7FFCC004;
+    memctl->memc_mcr = 0x011B | UPMB;
+
+    memctl->memc_mdr = 0xFFFDCC05;
+    memctl->memc_mcr = 0x011C | UPMB;
+
+    /* Initialize OR3 / BR3 for CAN Bus Controller */
+    memctl->memc_or3 = CFG_OR3_CAN;
+    memctl->memc_br3 = CFG_BR3_CAN;
+}
+
+void can_driver_disable (void)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+    /* Reset OR3 / BR3 to disable  CAN Bus Controller */
+    memctl->memc_br3 = 0;
+    memctl->memc_or3 = 0;
+
+    memctl->memc_mbmr = 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+    memctl->memc_mamr = mamr_value;
+
+    return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define	ETH_CFG_BITS	(CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2  | CFG_PB_ETH_CFG3 )
+
+#define ETH_ALL_BITS	(ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN)
+
+void	reset_phy(void)
+{
+	immap_t *immr = (immap_t *)CFG_IMMR;
+	ulong value;
+
+	/* Configure all needed port pins for GPIO */
+#ifdef CFG_ETH_MDDIS_VALUE
+	immr->im_ioport.iop_padat |=   CFG_PA_ETH_MDDIS;
+#else
+	immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* Set low */
+#endif
+	immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* GPIO */
+	immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* active output */
+	immr->im_ioport.iop_padir |=   CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET;	/* output */
+
+	immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS);	/* active output */
+
+	value  = immr->im_cpm.cp_pbdat;
+
+	/* Assert Powerdown and Reset signals */
+	value |=  CFG_PB_ETH_POWERDOWN;
+
+	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
+#ifdef CFG_ETH_CFG1_VALUE
+	value |=   CFG_PB_ETH_CFG1;
+#else
+	value &= ~(CFG_PB_ETH_CFG1);
+#endif
+#ifdef CFG_ETH_CFG2_VALUE
+	value |=   CFG_PB_ETH_CFG2;
+#else
+	value &= ~(CFG_PB_ETH_CFG2);
+#endif
+#ifdef CFG_ETH_CFG3_VALUE
+	value |=   CFG_PB_ETH_CFG3;
+#else
+	value &= ~(CFG_PB_ETH_CFG3);
+#endif
+
+	/* Drive output signals to initial state */
+	immr->im_cpm.cp_pbdat  = value;
+	immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
+	udelay (10000);
+
+	/* De-assert Ethernet Powerdown */
+	immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
+	udelay (10000);
+
+	/* de-assert RESET signal of PHY */
+	immr->im_ioport.iop_padat |= CFG_PA_ETH_RESET;
+	udelay (1000);
+}
+
+
+int misc_init_r (void)
+{
+	fpga_init();
+	return (0);
+}
+/* ------------------------------------------------------------------------- */
diff --git a/board/siemens/CCM/config.mk b/board/siemens/CCM/config.mk
new file mode 100755
index 0000000..9c72c79
--- /dev/null
+++ b/board/siemens/CCM/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8xxL boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c
new file mode 100755
index 0000000..9c32785
--- /dev/null
+++ b/board/siemens/CCM/flash.c
@@ -0,0 +1,553 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V;
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c
new file mode 100755
index 0000000..11b97bc
--- /dev/null
+++ b/board/siemens/CCM/fpga_ccm.c
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+#include <common.h>
+
+#include "../common/fpga.h"
+
+fpga_t fpga_list[] = {
+    { "PUMA" , PUMA_CONF_BASE ,
+      CFG_PC_PUMA_INIT , CFG_PC_PUMA_PROG , CFG_PC_PUMA_DONE  }
+};
+int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
+
+void can_driver_enable (void);
+void can_driver_disable (void);
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/*
+ * PUMA access using UPM B
+ */
+const uint puma_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+	/*
+	 * Precharge and MRS
+	 */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+ulong fpga_control (fpga_t* fpga, int cmd)
+{
+    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+    switch (cmd) {
+    case FPGA_INIT_IS_HIGH:
+	immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */
+	return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0;
+
+    case FPGA_INIT_SET_LOW:
+	immr->im_ioport.iop_pcdir |=  fpga->init_mask; /* output */
+	immr->im_ioport.iop_pcdat &= ~fpga->init_mask;
+	break;
+
+    case FPGA_INIT_SET_HIGH:
+	immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
+	immr->im_ioport.iop_pcdat |= fpga->init_mask;
+	break;
+
+    case FPGA_PROG_SET_LOW:
+	immr->im_ioport.iop_pcdat &= ~fpga->prog_mask;
+	break;
+
+    case FPGA_PROG_SET_HIGH:
+	immr->im_ioport.iop_pcdat |= fpga->prog_mask;
+	break;
+
+    case FPGA_DONE_IS_HIGH:
+	return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0;
+
+    case FPGA_READ_MODE:
+	/* disable FPGA in memory controller */
+	memctl->memc_br4 = 0;
+	memctl->memc_or4 = PUMA_CONF_OR_READ;
+	memctl->memc_br4 = PUMA_CONF_BR_READ;
+
+	/* (re-) enable CAN drivers */
+	can_driver_enable ();
+
+	break;
+
+    case FPGA_LOAD_MODE:
+	/* disable FPGA in memory controller */
+	memctl->memc_br4 = 0;
+	/*
+	 * We must disable the CAN drivers first because
+	 * they use UPM B, too.
+	 */
+	can_driver_disable ();
+	/*
+	 * Configure UPMB for FPGA
+	 */
+	upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
+	memctl->memc_or4 = PUMA_CONF_OR_LOAD;
+	memctl->memc_br4 = PUMA_CONF_BR_LOAD;
+	break;
+
+    case FPGA_GET_ID:
+	return *(volatile ulong *)fpga->conf_base;
+
+    case FPGA_INIT_PORTS:
+	immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */
+	immr->im_ioport.iop_pcso  &= ~fpga->init_mask;
+	immr->im_ioport.iop_pcdir &= ~fpga->init_mask;
+
+	immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */
+	immr->im_ioport.iop_pcso  &= ~fpga->prog_mask;
+	immr->im_ioport.iop_pcdir |=  fpga->prog_mask;
+
+	immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */
+	immr->im_ioport.iop_pcso  &= ~fpga->done_mask;
+	immr->im_ioport.iop_pcdir &= ~fpga->done_mask;
+
+	break;
+
+    }
+    return 0;
+}
diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds
new file mode 100755
index 0000000..cdf550f
--- /dev/null
+++ b/board/siemens/CCM/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug
new file mode 100755
index 0000000..3b50272
--- /dev/null
+++ b/board/siemens/CCM/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+/*
+    . = env_offset;
+    common/environment.o(.text)
+*/
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c
new file mode 100755
index 0000000..e498937
--- /dev/null
+++ b/board/siemens/IAD210/IAD210.c
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2001
+ * Paul Geerinckx
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "atm.h"
+#include <i2c.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+/* used PLD registers */
+#  define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
+#  define PLD_EXT_RES  (unsigned char *) (0x10000000 + 10)
+#  define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
+#  define PLD_EXT_LED  (unsigned char *) (0x10000000 + 12)
+#  define PLD_EXT_X21  (unsigned char *) (0x10000000 + 13)
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47,	/* last */
+	_NOT_USED_,
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0xFFFAF834, 0xFFE5B435,	/* last */
+	_NOT_USED_,
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
+	0xF0AFFC00, 0xF0AAF800, 0xF1A5E447,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0xFE29B300, 0xF1A27304, 0xFFA5F747,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+	0xF1AAF804, 0xFFA5F447,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
+	0xFFAFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * MRS sequence  (Offset 38 in UPMA RAM)
+	 */
+	0xFFAAB834, 0xFFA57434, 0xFFAFFC05,	/* last */
+	_NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0xFFAFFC04, 0xFFAFFC05,	/* last */
+	_NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile iop8xx_t *iop = &immap->im_ioport;
+	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+	long int size;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or2 = CFG_OR2_PRELIM;
+	memctl->memc_br2 = CFG_BR2_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM precharge */
+	udelay (1);
+	memctl->memc_mcr = 0x80004030;	/* SDRAM 16x autorefresh */
+	udelay (1);
+	memctl->memc_mcr = 0x80004138;	/* SDRAM upload parameters */
+	udelay (1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 */
+	size = dram_size (CFG_MAMR, (long *) SDRAM_BASE_PRELIM,
+			  SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+
+	memctl->memc_mamr = CFG_MAMR;
+	udelay (1000);
+
+	/*
+	 * Final mapping
+	 */
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
+	memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
+
+	udelay (10000);
+
+	/* prepare pin multiplexing for fast ethernet */
+
+	atmLoad ();
+	fecp->fec_ecntrl = 0x00000004;	/* rev D3 pinmux SET */
+	iop->iop_pdpar |= 0x0080;	/* set pin as MII_clock */
+
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	return (0);
+}
+
+void board_serial_init (void)
+{
+	;			/* nothing to do here */
+}
+
+void board_ether_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile iop8xx_t *iop = &immap->im_ioport;
+	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
+
+	atmLoad ();
+	fecp->fec_ecntrl = 0x00000004;	/* rev D3 pinmux SET */
+	iop->iop_pdpar |= 0x0080;	/* set pin as MII_clock */
+}
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	volatile iop8xx_t *iop = &immap->im_ioport;
+
+	/* configure the LED timing output pins - port A pin 4 */
+	iop->iop_papar = 0x0800;
+	iop->iop_padir = 0x0800;
+
+	/* start timer 2 for the 4hz LED blink rate */
+	timers->cpmt_tmr2 = 0xff2c;	/* 4hz for 64mhz */
+	timers->cpmt_trr2 = 0x000003d0;	/* clk/16 , prescale=256 */
+	timers->cpmt_tgcr = 0x00000810;	/* run timer 2 */
+
+	/* chip select for PLD access */
+	memctl->memc_br6 = 0x10000401;
+	memctl->memc_or6 = 0xFC000908;
+
+	/* PLD initial values ( set LEDs, remove reset on LXT) */
+
+	*PLD_GCR1_REG = 0x06;
+	*PLD_EXT_RES = 0xC0;
+	*PLD_EXT_FETH = 0x40;
+	*PLD_EXT_LED = 0xFF;
+	*PLD_EXT_X21 = 0x04;
+	return 0;
+}
+
+void board_get_enetaddr (uchar * addr)
+{
+	int i;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	unsigned int rccrtmp;
+
+	char default_mac_addr[] = { 0x00, 0x08, 0x01, 0x02, 0x03, 0x04 };
+
+	for (i = 0; i < 6; i++)
+		addr[i] = default_mac_addr[i];
+
+	printf ("There is an error in the i2c driver .. /n");
+	printf ("You need to fix it first....../n");
+
+	rccrtmp = cpm->cp_rccr;
+	cpm->cp_rccr |= 0x0020;
+
+	i2c_reg_read (0xa0, 0);
+	printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
+		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
+		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
+		i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
+
+	cpm->cp_rccr = rccrtmp;
+}
diff --git a/board/siemens/IAD210/Makefile b/board/siemens/IAD210/Makefile
new file mode 100755
index 0000000..87a6893
--- /dev/null
+++ b/board/siemens/IAD210/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o atm.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c
new file mode 100755
index 0000000..c77e359
--- /dev/null
+++ b/board/siemens/IAD210/atm.c
@@ -0,0 +1,653 @@
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+
+#include "atm.h"
+#include <linux/stddef.h>
+
+#define SYNC __asm__("sync")
+#define ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1)))
+
+#define FALSE  1
+#define TRUE   0
+#define OK     0
+#define ERROR -1
+
+struct atm_connection_t g_conn[NUM_CONNECTIONS] =
+{
+  { NULL, 10, NULL, 10,  NULL, NULL, NULL, NULL }, /* OAM  */
+};
+
+struct atm_driver_t g_atm =
+{
+  FALSE,   /* loaded */
+  FALSE,   /* started */
+  NULL,    /* csram */
+  0,       /* csram_size */
+  NULL,    /* am_top */
+  NULL,    /* ap_top */
+  NULL,    /* int_reload_ptr */
+  NULL,    /* int_serv_ptr */
+  NULL,    /* rbd_base_ptr */
+  NULL,    /* tbd_base_ptr */
+  0        /* linerate */
+};
+
+char csram[1024]; /* more than enough for doing nothing*/
+
+int    atmLoad(void);
+void   atmUnload(void);
+int    atmMemInit(void);
+void   atmIntInit(void);
+void   atmApcInit(void);
+void   atmAmtInit(void);
+void   atmCpmInit(void);
+void   atmUtpInit(void);
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmLoad
+ *
+ * DESCRIPTION: Basic ATM initialization.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: OK or ERROR
+ *
+ ****************************************************************************/
+int atmLoad()
+{
+  volatile immap_t       *immap  = (immap_t *)CFG_IMMR;
+  volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+  volatile iop8xx_t      *iop    = &immap->im_ioport;
+
+  timers->cpmt_tgcr &=  0x0FFF; SYNC;             /* Disable Timer 4 */
+  immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC; /* Disable SCC4 */
+  iop->iop_pdpar &= 0x3FFF; SYNC;                 /* Disable SAR and UTOPIA */
+
+  if ( atmMemInit() != OK ) return ERROR;
+
+  atmIntInit();
+  atmApcInit();
+  atmAmtInit();
+  atmCpmInit();
+  atmUtpInit();
+
+  g_atm.loaded = TRUE;
+
+  return OK;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmUnload
+ *
+ * DESCRIPTION: Disables ATM and UTOPIA.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ ****************************************************************************/
+void atmUnload()
+{
+  volatile immap_t       *immap  = (immap_t *)CFG_IMMR;
+  volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
+  volatile iop8xx_t      *iop    = &immap->im_ioport;
+
+  timers->cpmt_tgcr &=  0x0FFF; SYNC;             /* Disable Timer 4 */
+  immap->im_cpm.cp_scc[4].scc_gsmrl = 0x0; SYNC;  /* Disable SCC4 */
+  iop->iop_pdpar &= 0x3FFF; SYNC;                 /* Disable SAR and UTOPIA */
+  g_atm.loaded = FALSE;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmMemInit
+ *
+ * DESCRIPTION:
+ *
+ * The ATM driver uses the following resources:
+ *
+ * A. Memory in DPRAM to hold
+ *
+ *     1/ CT          = Connection Table ( RCT & TCT )
+ *     2/ TCTE        = Transmit Connection Table Extension
+ *     3/ MPHYPT      = Multi-PHY Pointing Table
+ *     4/ APCP        = APC Parameter Table
+ *     5/ APCT_PRIO_1 = APC Table ( priority 1 for AAL1/2 )
+ *     6/ APCT_PRIO_2 = APC Table ( priority 2 for VBR )
+ *     7/ APCT_PRIO_3 = APC Table ( priority 3 for UBR )
+ *     8/ TQ          = Transmit Queue
+ *     9/ AM          = Address Matching Table
+ *    10/ AP          = Address Pointing Table
+ *
+ * B. Memory in cache safe RAM to hold
+ *
+ *     1/ INT         = Interrupt Queue
+ *     2/ RBD         = Receive Buffer Descriptors
+ *     3/ TBD         = Transmit Buffer Descriptors
+ *
+ * This function
+ * 1. clears the ATM DPRAM area,
+ * 2. Allocates and clears cache safe memory,
+ * 3. Initializes 'g_conn'.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: OK or ERROR
+ *
+ ****************************************************************************/
+int atmMemInit()
+{
+  int i;
+  unsigned immr = CFG_IMMR;
+  int total_num_rbd = 0;
+  int total_num_tbd = 0;
+
+  memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
+
+  g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
+
+  for ( i = 0; i < NUM_CONNECTIONS; ++i ) {
+    total_num_rbd += g_conn[i].num_rbd;
+    total_num_tbd += g_conn[i].num_tbd;
+  }
+
+  g_atm.csram_size += total_num_rbd * SIZE_OF_RBD + total_num_tbd * SIZE_OF_TBD + 4;
+
+  g_atm.csram = &csram[0];
+  memset(&(g_atm.csram), 0x00, g_atm.csram_size);
+
+  g_atm.int_reload_ptr = (uint32 *)ALIGN(g_atm.csram, 4);
+  g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES);
+  g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd);
+
+  g_conn[0].rbd_ptr = g_atm.rbd_base_ptr;
+  g_conn[0].tbd_ptr = g_atm.tbd_base_ptr;
+  g_conn[0].ct_ptr = CT_PTR(immr);
+  g_conn[0].tcte_ptr = TCTE_PTR(immr);
+
+  return OK;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmIntInit
+ *
+ * DESCRIPTION:
+ *
+ * Initialization of the MPC860 ESAR Interrupt Queue.
+ * This function
+ * - clears all entries in the INT,
+ * - sets the WRAP bit of the last INT entry,
+ * - initializes the 'int_serv_ptr' attribuut of the AtmDriver structure
+ *   to the first INT entry.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ * REMARKS:
+ *
+ * - The INT resides in external cache safe memory.
+ * - The base address of the INT is stored in g_atm.int_reload_ptr.
+ * - The number of entries in the INT is given by NUM_INT_ENTRIES.
+ * - The INTBASE field in SAR Parameter RAM is set by atmCpmInit().
+ *
+ ****************************************************************************/
+void atmIntInit()
+{
+  int i;
+  for ( i = 0; i < NUM_INT_ENTRIES - 1; ++i) g_atm.int_reload_ptr[i] = 0;
+  g_atm.int_reload_ptr[i] = INT_WRAP;
+  g_atm.int_serv_ptr = g_atm.int_reload_ptr;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmApcInit
+ *
+ * DESCRIPTION:
+ *
+ * This function initializes the following ATM Pace Controller related
+ * data structures:
+ *
+ * - 1 MPHY Pointing Table (contains only one entry)
+ * - 3 APC Parameter Tables (one PHY with 3 priorities)
+ * - 3 APC Tables (one table for each priority)
+ * - 1 Transmit Queue (one transmit queue per PHY)
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ ****************************************************************************/
+void atmApcInit()
+{
+  int i;
+  /* unsigned immr = CFG_IMMR; */
+  uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR);
+  struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR);
+  uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR);
+  uint16 * tq_ptr = TQ_PTR(CFG_IMMR);
+  /***************************************************/
+  /* Initialize MPHY Pointing Table (only one entry) */
+  /***************************************************/
+  *mphypt_ptr = APCP_BASE;
+
+  /********************************************/
+  /* Initialize APC parameters for priority 1 */
+  /********************************************/
+  apcp_ptr->apct_base1 = APCT_PRIO_1_BASE;
+  apcp_ptr->apct_end1  =  APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * 2;
+  apcp_ptr->apct_ptr1  =  APCT_PRIO_1_BASE;
+  apcp_ptr->apct_sptr1 = APCT_PRIO_1_BASE;
+  apcp_ptr->etqbase    = TQ_BASE;
+  apcp_ptr->etqend     =  TQ_BASE + ( NUM_TQ_ENTRIES - 1 ) * 2;
+  apcp_ptr->etqaptr    = TQ_BASE;
+  apcp_ptr->etqtptr    = TQ_BASE;
+  apcp_ptr->apc_mi     = 8;
+  apcp_ptr->ncits      = 0x0100;   /* NCITS = 1 */
+  apcp_ptr->apcnt      = 0;
+  apcp_ptr->reserved1  = 0;
+  apcp_ptr->eapcst     = 0x2009;  /* LAST, ESAR, MPHY */
+  apcp_ptr->ptp_counter = 0;
+  apcp_ptr->ptp_txch   = 0;
+  apcp_ptr->reserved2  = 0;
+
+
+  /***************************************************/
+  /* Initialize APC Tables with empty slots (0xFFFF) */
+  /***************************************************/
+  for ( i = 0; i < NUM_APCT_PRIO_1_ENTRIES; ++i ) *(apct_prio1_ptr++) = 0xFFFF;
+
+  /************************/
+  /* Clear Transmit Queue */
+  /************************/
+  for ( i = 0; i < NUM_TQ_ENTRIES; ++i ) *(tq_ptr++) = 0;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmAmtInit
+ *
+ * DESCRIPTION:
+ *
+ * This function clears the first entry in the Address Matching Table and
+ * lets the first entry in the Address Pointing table point to the first
+ * entry in the TCT table (i.e. the raw cell channel).
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ * REMARKS:
+ *
+ * The values for the AMBASE, AMEND and APBASE registers in SAR parameter
+ * RAM are initialized by atmCpmInit().
+ *
+ ****************************************************************************/
+void atmAmtInit()
+{
+  unsigned immr = CFG_IMMR;
+
+  g_atm.am_top = AM_PTR(immr);
+  g_atm.ap_top = AP_PTR(immr);
+
+  *(g_atm.ap_top--) = CT_BASE;
+  *(g_atm.am_top--) = 0;
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmCpmInit
+ *
+ * DESCRIPTION:
+ *
+ * This function initializes the Utopia Interface Parameter RAM Map
+ * (SCC4, ATM Protocol) of the Communication Processor Modudule.
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ ****************************************************************************/
+void atmCpmInit()
+{
+  unsigned immr = CFG_IMMR;
+
+  memset((char *)immr + 0x3F00, 0x00, 0xC0);
+
+  /*-----------------------------------------------------------------*/
+  /* RBDBASE - Receive buffer descriptors base address               */
+  /* The RBDs reside in cache safe external memory.                  */
+  /*-----------------------------------------------------------------*/
+  *RBDBASE(immr) = (uint32)g_atm.rbd_base_ptr;
+
+  /*-----------------------------------------------------------------*/
+  /* SRFCR - SAR receive function code                               */
+  /* 0-2 rsvd = 000                                                  */
+  /* 3-4 BO   = 11  Byte ordering (big endian).                      */
+  /* 5-7 FC   = 000 Value driven on the address type signals AT[1-3] */
+  /*                when the SDMA channel accesses memory.           */
+  /*-----------------------------------------------------------------*/
+  *SRFCR(immr) = 0x18;
+
+  /*-----------------------------------------------------------------*/
+  /* SRSTATE - SAR receive status                                    */
+  /* 0 EXT  = 0 Extended mode off.                                   */
+  /* 1 ACP  = 0 Valid only if EXT = 1.                               */
+  /* 2 EC   = 0 Standard 53-byte ATM cell.                           */
+  /* 3 SNC  = 0 In sync. Must be set to 0 during initialization.     */
+  /* 4 ESAR = 1 Enhanced SAR functionality enabled.                  */
+  /* 5 MCF  = 1 Management Cell Filter active.                       */
+  /* 6 SER  = 0 UTOPIA mode.                                         */
+  /* 7 MPY  = 1 Multiple PHY mode.                                   */
+  /*-----------------------------------------------------------------*/
+  *SRSTATE(immr) = 0x0D;
+
+  /*-----------------------------------------------------------------*/
+  /* MRBLR - Maximum receive buffer length register.                 */
+  /* Must be cleared for ATM operation (see also SMRBLR).            */
+  /*-----------------------------------------------------------------*/
+  *MRBLR(immr) = 0;
+
+  /*-----------------------------------------------------------------*/
+  /* RSTATE - SCC internal receive state parameters                  */
+  /* The first byte must be initialized with the value of SRFCR.     */
+  /*-----------------------------------------------------------------*/
+  *RSTATE(immr) = (uint32)(*SRFCR(immr)) << 24;
+
+  /*-----------------------------------------------------------------*/
+  /* STFCR - SAR transmit function code                              */
+  /* 0-2 rsvd = 000                                                  */
+  /* 3-4 BO   = 11  Byte ordering (big endian).                      */
+  /* 5-7 FC   = 000 Value driven on the address type signals AT[1-3] */
+  /*                when the SDMA channel accesses memory.           */
+  /*-----------------------------------------------------------------*/
+  *STFCR(immr) = 0x18;
+
+  /*-----------------------------------------------------------------*/
+  /* SRSTATE - SAR transmit status                                   */
+  /* 0 EXT  = 0 : Extended mode off                                  */
+  /* 1 rsvd = 0 :                                                    */
+  /* 2 EC   = 0 : Standard 53-byte ATM cell                          */
+  /* 3 rsvd = 0 :                                                    */
+  /* 4 ESAR = 1 : Enhanced SAR functionality enabled                 */
+  /* 5 rsvd = 0 :                                                    */
+  /* 6 SER  = 0 : UTOPIA mode                                        */
+  /* 7 MPY  = 1 : Multiple PHY mode                                  */
+  /*-----------------------------------------------------------------*/
+  *STSTATE(immr) = 0x09;
+
+  /*-----------------------------------------------------------------*/
+  /* TBDBASE - Transmit buffer descriptors base address              */
+  /* The TBDs reside in cache safe external memory.                  */
+  /*-----------------------------------------------------------------*/
+  *TBDBASE(immr) = (uint32)g_atm.tbd_base_ptr;
+
+  /*-----------------------------------------------------------------*/
+  /* TSTATE - SCC internal transmit state parameters                 */
+  /* The first byte must be initialized with the value of STFCR.     */
+  /*-----------------------------------------------------------------*/
+  *TSTATE(immr) = (uint32)(*STFCR(immr)) << 24;
+
+  /*-----------------------------------------------------------------*/
+  /* CTBASE - Connection table base address                          */
+  /* Offset from the beginning of DPRAM (64-byte aligned).           */
+  /*-----------------------------------------------------------------*/
+  *CTBASE(immr) = CT_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* INTBASE - Interrupt queue base pointer.                         */
+  /* The interrupt queue resides in cache safe external memory.      */
+  /*-----------------------------------------------------------------*/
+  *INTBASE(immr) = (uint32)g_atm.int_reload_ptr;
+
+  /*-----------------------------------------------------------------*/
+  /* INTPTR - Pointer into interrupt queue.                          */
+  /* Initialize to INTBASE.                                          */
+  /*-----------------------------------------------------------------*/
+  *INTPTR(immr) = *INTBASE(immr);
+
+  /*-----------------------------------------------------------------*/
+  /* C_MASK - Constant mask for CRC32                                */
+  /* Must be initialized to 0xDEBB20E3.                              */
+  /*-----------------------------------------------------------------*/
+  *C_MASK(immr) = 0xDEBB20E3;
+
+  /*-----------------------------------------------------------------*/
+  /* INT_ICNT - Interrupt threshold value                            */
+  /*-----------------------------------------------------------------*/
+  *INT_ICNT(immr) = 1;
+
+  /*-----------------------------------------------------------------*/
+  /* INT_CNT - Interrupt counter                                     */
+  /* Initalize to INT_ICNT. Decremented for each interrupt entry     */
+  /* reported in the interrupt queue. On zero an interrupt is        */
+  /* signaled to the host by setting the GINT bit in the event       */
+  /* register. The counter is reinitialized with INT_ICNT.           */
+  /*-----------------------------------------------------------------*/
+  *INT_CNT(immr) = *INT_ICNT(immr);
+
+  /*-----------------------------------------------------------------*/
+  /* SMRBLR - SAR maximum receive buffer length register.            */
+  /* Must be a multiple of 48 bytes. Common for all ATM connections. */
+  /*-----------------------------------------------------------------*/
+  *SMRBLR(immr) = SAR_RXB_SIZE;
+
+  /*-----------------------------------------------------------------*/
+  /* APCST - APC status register.                                    */
+  /* 0     rsvd 0                                                    */
+  /* 1-2   CSER 11  Initialize with the same value as NSER.          */
+  /* 3-4   NSER 11  Next serial or UTOPIA channel.                   */
+  /* 5-7   rsvd 000                                                  */
+  /* 8-10  rsvd 000                                                  */
+  /* 11    rsvd 0                                                    */
+  /* 12    ESAR 1   UTOPIA Level 2 MPHY enabled.                     */
+  /* 13    DIS  0   APC disable. Must be initiazed to 0.             */
+  /* 14    PL2  0   Not used.                                        */
+  /* 15    MPY  1   Multiple PHY mode on.                            */
+  /*-----------------------------------------------------------------*/
+  *APCST(immr) = 0x7809;
+
+  /*-----------------------------------------------------------------*/
+  /* APCPTR - Pointer to the APC parameter table                     */
+  /* In MPHY master mode this parameter points to the MPHY pointing  */
+  /* table. 2-byte aligned.                                          */
+  /*-----------------------------------------------------------------*/
+  *APCPTR(immr) = MPHYPT_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* HMASK - Header mask                                             */
+  /* Each incoming cell is masked with HMASK before being compared   */
+  /* to the entries in the address matching table.                   */
+  /*-----------------------------------------------------------------*/
+  *HMASK(immr) = AM_HMASK;
+
+  /*-----------------------------------------------------------------*/
+  /* AMBASE - Address matching table base address                    */
+  /*-----------------------------------------------------------------*/
+  *AMBASE(immr) = AM_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* AMEND - Address matching table end address                      */
+  /*-----------------------------------------------------------------*/
+  *AMEND(immr) = AM_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* APBASE - Address pointing table base address                    */
+  /*-----------------------------------------------------------------*/
+  *APBASE(immr) = AP_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* MPHYST - MPHY status register                                   */
+  /* 0-1   rsvd  00                                                  */
+  /* 2-6   NMPHY 00000 1 PHY                                         */
+  /* 7-9   rsvd  000                                                 */
+  /* 10-14 CMPHY 00000 Initialize with same value as NMPHY           */
+  /*-----------------------------------------------------------------*/
+  *MPHYST(immr) = 0x0000;
+
+  /*-----------------------------------------------------------------*/
+  /* TCTEBASE - Transmit connection table extension base address     */
+  /* Offset from the beginning of DPRAM (32-byte aligned).           */
+  /*-----------------------------------------------------------------*/
+  *TCTEBASE(immr) = TCTE_BASE;
+
+  /*-----------------------------------------------------------------*/
+  /* Clear not used registers.                                       */
+  /*-----------------------------------------------------------------*/
+}
+
+/*****************************************************************************
+ *
+ * FUNCTION NAME: atmUtpInit
+ *
+ * DESCRIPTION:
+ *
+ * This function initializes the ATM interface for
+ *
+ * - UTOPIA mode
+ * - muxed bus
+ * - master operation
+ * - multi PHY (because of a bug in the MPC860P rev. E.0)
+ * - internal clock = SYSCLK / 2
+ *
+ * EXTERNAL EFFECTS:
+ *
+ * After calling this function, the MPC860ESAR UTOPIA bus is
+ * active and uses the following ports/pins:
+ *
+ * Port    Pin  Signal   Description
+ * ------  ---  -------  -------------------------------------------
+ * PB[15]  R17  TxClav   Transmit cell available input/output signal
+ * PC[15]  D16  RxClav   Receive cell available input/output signal
+ * PD[15]  U17  UTPB[0]  UTOPIA bus bit 0 input/output signal
+ * PD[14]  V19  UTPB[1]  UTOPIA bus bit 1 input/output signal
+ * PD[13]  V18  UTPB[2]  UTOPIA bus bit 2 input/output signal
+ * PD[12]  R16  UTPB[3]  UTOPIA bus bit 3 input/output signal
+ * PD[11]  T16  RXENB    Receive enable input/output signal
+ * PD[10]  W18  TXENB    Transmit enable input/output signal
+ * PD[9]   V17  UTPCLK   UTOPIA clock input/output signal
+ * PD[7]   T15  UTPB[4]  UTOPIA bus bit 4 input/output signal
+ * PD[6]   V16  UTPB[5]  UTOPIA bus bit 5 input/output signal
+ * PD[5]   U15  UTPB[6]  UTOPIA bus bit 6 input/output signal
+ * PD[4]   U16  UTPB[7]  UTOPIA bus bit 7 input/output signal
+ * PD[3]   W16  SOC      Start of cell input/output signal
+ *
+ * PARAMETERS: none
+ *
+ * RETURNS: void
+ *
+ * REMARK:
+ *
+ * The ATM parameters and data structures must be configured before
+ * initializing the UTOPIA port. The UTOPIA port activates immediately
+ * upon initialization, and if its associated data structures are not
+ * initialized, the CPM will lock up.
+ *
+ ****************************************************************************/
+void atmUtpInit()
+{
+  volatile immap_t       *immap  = (immap_t *)CFG_IMMR;
+  volatile iop8xx_t      *iop    = &immap->im_ioport;
+  volatile car8xx_t	 *car    = &immap->im_clkrst;
+  volatile cpm8xx_t	 *cpm    = &immap->im_cpm;
+  int flag;
+
+  flag = disable_interrupts();
+
+  /*-----------------------------------------------------------------*/
+  /* SCCR - System Clock Control Register                            */
+  /*                                                                 */
+  /* The UTOPIA clock can be selected to be internal clock or        */
+  /* external clock (selected by the UTOPIA mode register).          */
+  /* In case of internal clock, the UTOPIA clock is derived from     */
+  /* the system frequency divided by two dividers.                   */
+  /* Bits 27-31 of the SCCR register are defined to control the      */
+  /* UTOPIA clock.                                                   */
+  /*                                                                 */
+  /* SCCR[27:29] DFUTP  Division factor. Divide the system clock     */
+  /*                    by 2^DFUTP.                                  */
+  /* SCCR[30:31] DFAUTP Additional division factor. Divide the       */
+  /*                    system clock by the following value:         */
+  /*                    00 = divide by 1                             */
+  /*                    00 = divide by 3                             */
+  /*                    10 = divide by 5                             */
+  /*                    11 = divide by 7                             */
+  /*                                                                 */
+  /* Note that the UTOPIA clock must be programmed as to operate     */
+  /* within the range SYSCLK/10 .. 50Mhz.                            */
+  /*-----------------------------------------------------------------*/
+  car->car_sccr &= 0xFFFFFFE0;
+  car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */
+
+  /*-----------------------------------------------------------------*/
+  /* RCCR - RISC Controller Configuration Register                   */
+  /*                                                                 */
+  /* RCCR[8]     DR1M IDMA Request 0 Mode                            */
+  /*                  0 = edge sensitive                             */
+  /*                  1 = level sensitive                            */
+  /* RCCR[9]     DR0M IDMA Request 0 Mode                            */
+  /*                  0 = edge sensitive                             */
+  /*                  1 = level sensitive                            */
+  /* RCCR[10:11] DRQP IDMA Request Priority                          */
+  /*                  00 = IDMA req. have more prio. than SCCs       */
+  /*                  01 = IDMA req. have less prio. then SCCs       */
+  /*                  10 = IDMA requests have the lowest prio.       */
+  /*                  11 = reserved                                  */
+  /*                                                                 */
+  /* The RCCR[DR0M] and RCCR[DR1M] bits must be set to enable UTOPIA */
+  /* operation. Also, program RCCR[DPQP] to 01 to give SCC transfers */
+  /* higher priority.                                                */
+  /*-----------------------------------------------------------------*/
+  cpm->cp_rccr &= 0xFF0F;
+  cpm->cp_rccr |= 0x00D0;
+
+  /*-----------------------------------------------------------------*/
+  /* Port B - TxClav Signal                                          */
+  /*-----------------------------------------------------------------*/
+  cpm->cp_pbpar |= 0x00010000; /* PBPAR[15] = 1 */
+  cpm->cp_pbdir &= 0xFFFEFFFF; /* PBDIR[15] = 0 */
+
+  /*-----------------------------------------------------------------*/
+  /* UTOPIA Mode Register                                            */
+  /*                                                                 */
+  /* - muxed bus (master operation only)                             */
+  /* - multi PHY (because of a bug in the MPC860P rev.E.0)           */
+  /* - internal clock                                                */
+  /* - no loopback                                                   */
+  /* - do no activate statistical counters                           */
+  /*-----------------------------------------------------------------*/
+  iop->utmode = 0x00000004; SYNC;
+
+  /*-----------------------------------------------------------------*/
+  /* Port D - UTOPIA Data and Control Signals                        */
+  /*                                                                 */
+  /* 15-12 UTPB[0:3] UTOPIA bus bit 0 - 3 input/output signals       */
+  /* 11    RXENB     UTOPIA receive enable input/output signal       */
+  /* 10    TXENB     UTOPIA transmit enable input/output signal      */
+  /* 9     TUPCLK    UTOPIA clock input/output signal                */
+  /* 8     MII-MDC   Used by MII in simult. MII and UTOPIA operation */
+  /* 7-4   UTPB[4:7] UTOPIA bus bit 4 - 7 input/output signals       */
+  /* 3     SOC       UTOPIA Start of cell input/output signal        */
+  /* 2               Reserved                                        */
+  /* 1               Enable UTOPIA mode                              */
+  /* 0               Enable SAR                                      */
+  /*-----------------------------------------------------------------*/
+  iop->iop_pdpar |= 0xDF7F; SYNC;
+  iop->iop_pddir &= 0x2080; SYNC;
+
+  /*-----------------------------------------------------------------*/
+  /* Port C - RxClav Signal                                          */
+  /*-----------------------------------------------------------------*/
+  iop->iop_pcpar  |= 0x0001; /* PCPAR[15] = 1 */
+  iop->iop_pcdir  &= 0xFFFE; /* PCDIR[15] = 0 */
+  iop->iop_pcso   &= 0xFFFE; /* PCSO[15]  = 0 */
+
+  if (flag)
+    enable_interrupts();
+}
diff --git a/board/siemens/IAD210/atm.h b/board/siemens/IAD210/atm.h
new file mode 100755
index 0000000..71b0497
--- /dev/null
+++ b/board/siemens/IAD210/atm.h
@@ -0,0 +1,287 @@
+typedef unsigned char uint8;
+typedef unsigned short uint16;
+typedef unsigned int uint32;
+typedef volatile unsigned char vuint8;
+typedef volatile unsigned short vuint16;
+typedef volatile unsigned int vuint32;
+
+
+#define DPRAM_ATM CFG_IMMR + 0x3000
+
+#define ATM_DPRAM_BEGIN  (DPRAM_ATM - CFG_IMMR - 0x2000)
+#define NUM_CONNECTIONS  1
+#define SAR_RXB_SIZE     1584
+#define AM_HMASK         0x0FFFFFF0
+
+#define NUM_CT_ENTRIES           (NUM_CONNECTIONS)
+#define NUM_TCTE_ENTRIES         (NUM_CONNECTIONS)
+#define NUM_AM_ENTRIES           (NUM_CONNECTIONS+1)
+#define NUM_AP_ENTRIES           (NUM_CONNECTIONS+1)
+#define NUM_MPHYPT_ENTRIES       1
+#define NUM_APCP_ENTRIES         1
+#define NUM_APCT_PRIO_1_ENTRIES  146	/* Determines minimum rate */
+#define NUM_TQ_ENTRIES           12
+
+#define SIZE_OF_CT_ENTRY         64
+#define SIZE_OF_TCTE_ENTRY       32
+#define SIZE_OF_AM_ENTRY         4
+#define SIZE_OF_AP_ENTRY         2
+#define SIZE_OF_MPHYPT_ENTRY     2
+#define SIZE_OF_APCP_ENTRY       32
+#define SIZE_OF_APCT_ENTRY       2
+#define SIZE_OF_TQ_ENTRY         2
+
+#define CT_BASE           ((ATM_DPRAM_BEGIN + 63) & 0xFFC0)	/*64 */
+#define TCTE_BASE         (CT_BASE + NUM_CT_ENTRIES * SIZE_OF_CT_ENTRY)	/*32 */
+#define APCP_BASE         (TCTE_BASE + NUM_TCTE_ENTRIES * SIZE_OF_TCTE_ENTRY)	/*32 */
+#define AM_BEGIN          (APCP_BASE + NUM_APCP_ENTRIES * SIZE_OF_APCP_ENTRY)	/*4 */
+#define AM_BASE           (AM_BEGIN + (NUM_AM_ENTRIES - 1) * SIZE_OF_AM_ENTRY)
+#define AP_BEGIN          (AM_BEGIN + NUM_AM_ENTRIES * SIZE_OF_AM_ENTRY)	/*2 */
+#define AP_BASE           (AP_BEGIN + (NUM_AP_ENTRIES - 1) * SIZE_OF_AP_ENTRY)
+#define MPHYPT_BASE       (AP_BEGIN + NUM_AP_ENTRIES * SIZE_OF_AP_ENTRY)	/*2 */
+#define APCT_PRIO_1_BASE  (MPHYPT_BASE + NUM_MPHYPT_ENTRIES * SIZE_OF_MPHYPT_ENTRY)	/*2 */
+#define TQ_BASE           (APCT_PRIO_1_BASE + NUM_APCT_PRIO_1_ENTRIES * SIZE_OF_APCT_ENTRY)	/*2 */
+#define ATM_DPRAM_SIZE    ((TQ_BASE + NUM_TQ_ENTRIES * SIZE_OF_TQ_ENTRY) - ATM_DPRAM_BEGIN)
+
+#define CT_PTR(base)      ((struct ct_entry_t *)((char *)(base) + 0x2000 + CT_BASE))
+#define TCTE_PTR(base)    ((struct tcte_entry_t *)((char *)(base) + 0x2000 + TCTE_BASE))
+#define AM_PTR(base)      ((uint32 *)((char *)(base) + 0x2000 + AM_BASE))
+#define AP_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + AP_BASE))
+#define MPHYPT_PTR(base)  ((uint16 *)((char *)(base) + 0x2000 + MPHYPT_BASE))
+#define APCP_PTR(base)    ((struct apc_params_t *)((char*)(base) + 0x2000 + APCP_BASE))
+#define APCT1_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_1_BASE))
+#define APCT2_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_2_BASE))
+#define APCT3_PTR(base)   ((uint16 *)((char *)(base) + 0x2000 + APCT_PRIO_3_BASE))
+#define TQ_PTR(base)      ((uint16 *)((char *)(base) + 0x2000 + TQ_BASE))
+
+/* SAR registers */
+#define RBDBASE(base)	  ((vuint32 *)(base + 0x3F00))	/* Base address of RxBD-List */
+#define SRFCR(base)	  ((vuint8 *)(base + 0x3F04))	/* DMA Receive function code */
+#define SRSTATE(base)	  ((vuint8 *)(base + 0x3F05))	/* DMA Receive status */
+#define MRBLR(base)	  ((vuint16 *)(base + 0x3F06))	/* Init to 0 for ATM */
+#define RSTATE(base)	  ((vuint32 *)(base + 0x3F08))	/* Do not write to */
+#define R_CNT(base)	  ((vuint16 *)(base + 0x3F10))	/* Do not write to */
+#define STFCR(base)	  ((vuint8 *)(base + 0x3F12))	/* DMA Transmit function code */
+#define STSTATE(base)	  ((vuint8 *)(base + 0x3F13))	/* DMA Transmit status */
+#define TBDBASE(base)	  ((vuint32 *)(base + 0x3F14))	/* Base address of TxBD-List */
+#define TSTATE(base)	  ((vuint32 *)(base + 0x3F18))	/* Do not write to */
+#define COMM_CH(base)	  ((vuint16 *)(base + 0x3F1C))	/* Command channel */
+#define STCHNUM(base)	  ((vuint16 *)(base + 0x3F1E))	/* Do not write to */
+#define T_CNT(base)	  ((vuint16 *)(base + 0x3F20))	/* Do not write to */
+#define CTBASE(base)	  ((vuint16 *)(base + 0x3F22))	/* Base address of Connection-table */
+#define ECTBASE(base)	  ((vuint32 *)(base + 0x3F24))	/* Valid only for external Conn.-table */
+#define INTBASE(base)	  ((vuint32 *)(base + 0x3F28))	/* Base address of Interrupt-table */
+#define INTPTR(base)	  ((vuint32 *)(base + 0x3F2C))	/* Pointer to Interrupt-queue */
+#define C_MASK(base)	  ((vuint32 *)(base + 0x3F30))	/* CRC-mask */
+#define SRCHNUM(base)	  ((vuint16 *)(base + 0x3F34))	/* Do not write to */
+#define INT_CNT(base)	  ((vuint16 *)(base + 0x3F36))	/* Interrupt-Counter */
+#define INT_ICNT(base)	  ((vuint16 *)(base + 0x3F38))	/* Interrupt threshold */
+#define TSTA(base)	  ((vuint16 *)(base + 0x3F3A))	/* Time-stamp-address */
+#define OLDLEN(base)	  ((vuint16 *)(base + 0x3F3C))	/* Do not write to */
+#define SMRBLR(base)	  ((vuint16 *)(base + 0x3F3E))	/* SAR max RXBuffer length */
+#define EHEAD(base)	  ((vuint32 *)(base + 0x3F40))	/* Valid for serial mode */
+#define EPAYLOAD(base)	  ((vuint32 *)(base + 0x3F44))	/* Valid for serial mode */
+#define TQBASE(base)	  ((vuint16 *)(base + 0x3F48))	/* Base address of Tx queue */
+#define TQEND(base)	  ((vuint16 *)(base + 0x3F4A))	/* End address of Tx queue */
+#define TQAPTR(base)	  ((vuint16 *)(base + 0x3F4C))	/* TQ APC pointer */
+#define TQTPTR(base)	  ((vuint16 *)(base + 0x3F4E))	/* TQ Tx pointer */
+#define APCST(base)	  ((vuint16 *)(base + 0x3F50))	/* APC status */
+#define APCPTR(base)	  ((vuint16 *)(base + 0x3F52))	/* APC parameter pointer */
+#define HMASK(base)	  ((vuint32 *)(base + 0x3F54))	/* Header mask */
+#define AMBASE(base)	  ((vuint16 *)(base + 0x3F58))	/* Address match table base */
+#define AMEND(base)	  ((vuint16 *)(base + 0x3F5A))	/* Address match table end */
+#define APBASE(base)	  ((vuint16 *)(base + 0x3F5C))	/* Address match parameter */
+#define FLBASE(base)	  ((vuint32 *)(base + 0x3F54))	/* First-level table base */
+#define SLBASE(base)	  ((vuint32 *)(base + 0x3F58))	/* Second-level table base */
+#define FLMASK(base)	  ((vuint16 *)(base + 0x3F5C))	/* First-level mask */
+#define ECSIZE(base)	  ((vuint16 *)(base + 0x3F5E))	/* Valid for extended mode */
+#define APCT_REAL(base)	  ((vuint32 *)(base + 0x3F60))	/* APC 32 bit counter */
+#define R_PTR(base)	  ((vuint32 *)(base + 0x3F64))	/* Do not write to */
+#define RTEMP(base)	  ((vuint32 *)(base + 0x3F68))	/* Do not write to */
+#define T_PTR(base)	  ((vuint32 *)(base + 0x3F6C))	/* Do not write to */
+#define TTEMP(base)	  ((vuint32 *)(base + 0x3F70))	/* Do not write to */
+
+/* ESAR registers */
+#define FMCTIMESTMP(base) ((vuint32 *)(base + 0x3F80))	/* Perf.Mon.Timestamp */
+#define FMCTEMPLATE(base) ((vuint32 *)(base + 0x3F84))	/* Perf.Mon.Template */
+#define PMPTR(base)       ((vuint16 *)(base + 0x3F88))	/* Perf.Mon.Table */
+#define PMCHANNEL(base)	  ((vuint16 *)(base + 0x3F8A))	/* Perf.Mon.Channel */
+#define MPHYST(base)	  ((vuint16 *)(base + 0x3F90))	/* Multi-PHY Status */
+#define TCTEBASE(base)	  ((vuint16 *)(base + 0x3F92))	/* Internal TCT Extension Base */
+#define ETCTEBASE(base)	  ((vuint32 *)(base + 0x3F94))	/* External TCT Extension Base */
+#define COMM_CH2(base)	  ((vuint32 *)(base + 0x3F98))	/* 2nd command channel word */
+#define STATBASE(base)	  ((vuint16 *)(base + 0x3F9C))	/* Statistics table pointer */
+
+/* UTOPIA Mode Register */
+#define UTMODE(base)      (CAST(vuint32 *)(base + 0x0978))
+
+/* SAR commands */
+#define TRANSMIT_CHANNEL_ACTIVATE_CMD   0x0FC1
+#define TRANSMIT_CHANNEL_DEACTIVATE_CMD 0x1FC1
+#define STOP_TRANSMIT_CMD               0x2FC1
+#define RESTART_TRANSMIT_CMD            0x3FC1
+#define STOP_RECEIVE_CMD                0x4FC1
+#define RESTART_RECEIVE_CMD             0x5FC1
+#define APC_BYPASS_CMD                  0x6FC1
+#define MEM_WRITE_CMD                   0x7FC1
+#define CPCR_FLG                        0x0001
+
+/* INT flags */
+#define INT_VALID	0x80000000
+#define INT_WRAP	0x40000000
+#define INT_APCO	0x00800000
+#define INT_TQF		0x00200000
+#define INT_RXF		0x00080000
+#define INT_BSY		0x00040000
+#define INT_TXB		0x00020000
+#define INT_RXB		0x00010000
+
+#define NUM_INT_ENTRIES   80
+#define SIZE_OF_INT_ENTRY 4
+
+struct apc_params_t {
+	vuint16 apct_base1;	/* APC Table - First Priority Base pointer */
+	vuint16 apct_end1;	/* First APC Table - Length */
+	vuint16 apct_ptr1;	/* First APC Table Pointer */
+	vuint16 apct_sptr1;	/* APC Table First Priority Service pointer */
+	vuint16 etqbase;	/* Enhanced Transmit Queue Base pointer */
+	vuint16 etqend;		/* Enhanced Transmit Queue End pointer */
+	vuint16 etqaptr;	/* Enhanced Transmit Queue APC pointer */
+	vuint16 etqtptr;	/* Enhanced Transmit Queue Transmitter pointer */
+	vuint16 apc_mi;		/* APC - Max Iteration */
+	vuint16 ncits;		/* Number of Cells In TimeSlot  */
+	vuint16 apcnt;		/* APC - N Timer */
+	vuint16 reserved1;	/* reserved */
+	vuint16 eapcst;		/* APC status */
+	vuint16 ptp_counter;	/* PTP queue length */
+	vuint16 ptp_txch;	/* PTP channel */
+	vuint16 reserved2;	/* reserved */
+};
+
+struct ct_entry_t {
+	/* RCT */
+	unsigned fhnt:1;
+	unsigned pm_rct:1;
+	unsigned reserved0:6;
+	unsigned hec:1;
+	unsigned clp:1;
+	unsigned cng_ncrc:1;
+	unsigned inf_rct:1;
+	unsigned cngi_ptp:1;
+	unsigned cdis_rct:1;
+	unsigned aal_rct:2;
+	uint16 rbalen;
+	uint32 rcrc;
+	uint32 rb_ptr;
+	uint16 rtmlen;
+	uint16 rbd_ptr;
+	uint16 rbase;
+	uint16 tstamp;
+	uint16 imask;
+	unsigned ft:2;
+	unsigned nim:1;
+	unsigned reserved1:2;
+	unsigned rpmt:6;
+	unsigned reserved2:5;
+	uint8 reserved3[8];
+	/* TCT */
+	unsigned reserved4:1;
+	unsigned pm_tct:1;
+	unsigned reserved5:6;
+	unsigned pc:1;
+	unsigned reserved6:2;
+	unsigned inf_tct:1;
+	unsigned cr10:1;
+	unsigned cdis_tct:1;
+	unsigned aal_tct:2;
+	uint16 tbalen;
+	uint32 tcrc;
+	uint32 tb_ptr;
+	uint16 ttmlen;
+	uint16 tbd_ptr;
+	uint16 tbase;
+	unsigned reserved7:5;
+	unsigned tpmt:6;
+	unsigned reserved8:3;
+	unsigned avcf:1;
+	unsigned act:1;
+	uint32 chead;
+	uint16 apcl;
+	uint16 apcpr;
+	unsigned out:1;
+	unsigned bnr:1;
+	unsigned tservice:2;
+	unsigned apcp:12;
+	uint16 apcpf;
+};
+
+struct tcte_entry_t {
+	unsigned res1:4;
+	unsigned scr:12;
+	uint16 scrf;
+	uint16 bt;
+	uint16 buptrh;
+	uint32 buptrl;
+	unsigned vbr2:1;
+	unsigned res2:15;
+	uint16 oobr;
+	uint16 res3[8];
+};
+
+#define SIZE_OF_RBD  12
+#define SIZE_OF_TBD  12
+
+struct atm_bd_t {
+	vuint16 flags;
+	vuint16 length;
+	unsigned char *buffer_ptr;
+	vuint16 cpcs_uu_cpi;
+	vuint16 reserved;
+};
+
+/* BD flags */
+#define EMPTY		0x8000
+#define READY		0x8000
+#define WRAP		0x2000
+#define INTERRUPT	0x1000
+#define LAST		0x0800
+#define FIRST		0x0400
+#define OAM             0x0400
+#define CONTINUOUS	0x0200
+#define HEC_ERROR	0x0080
+#define CELL_LOSS	0x0040
+#define CONGESTION	0x0020
+#define ABORT		0x0010
+#define LEN_ERROR	0x0002
+#define CRC_ERROR	0x0001
+
+struct atm_connection_t {
+	struct atm_bd_t *rbd_ptr;
+	int num_rbd;
+	struct atm_bd_t *tbd_ptr;
+	int num_tbd;
+	struct ct_entry_t *ct_ptr;
+	struct tcte_entry_t *tcte_ptr;
+	void *drv;
+	void (*notify) (void *drv, int event);
+};
+
+struct atm_driver_t {
+	int loaded;
+	int started;
+	char *csram;
+	int csram_size;
+	uint32 *am_top;
+	uint16 *ap_top;
+	uint32 *int_reload_ptr;
+	uint32 *int_serv_ptr;
+	struct atm_bd_t *rbd_base_ptr;
+	struct atm_bd_t *tbd_base_ptr;
+	unsigned linerate_in_bps;
+};
+
+extern struct atm_connection_t g_conn[NUM_CONNECTIONS];
+extern struct atm_driver_t g_atm;
+
+extern int atmLoad (void);
+extern void atmUnload (void);
diff --git a/board/siemens/IAD210/config.mk b/board/siemens/IAD210/config.mk
new file mode 100755
index 0000000..c30abcb
--- /dev/null
+++ b/board/siemens/IAD210/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# iad210 boards
+#
+
+TEXT_BASE = 0x08000000
+/*TEXT_BASE  = 0x00200000 */
diff --git a/board/siemens/IAD210/flash.c b/board/siemens/IAD210/flash.c
new file mode 100755
index 0000000..110858d
--- /dev/null
+++ b/board/siemens/IAD210/flash.c
@@ -0,0 +1,502 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+  volatile memctl8xx_t *memctl = &immap->im_memctl;
+  unsigned long size;
+  int i;
+
+  /* Init: no FLASHes known */
+  for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+    flash_info[i].flash_id = FLASH_UNKNOWN;
+  }
+
+  /* Static FLASH Bank configuration here - FIXME XXX */
+
+  size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+  if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+    printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+  }
+
+
+  /* Remap FLASH according to real size */
+  memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+  memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+  /* Re-do sizing to get full correct info */
+  size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+  flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+  flash_info[0].size = size;
+
+  return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+  int i;
+
+  /* set up sector start address table */
+  if (info->flash_id & FLASH_BTYPE) {
+    /* set sector offsets for bottom boot block type	*/
+    info->start[0] = base + 0x00000000;
+    info->start[1] = base + 0x00008000;
+    info->start[2] = base + 0x0000C000;
+    info->start[3] = base + 0x00010000;
+    for (i = 4; i < info->sector_count; i++) {
+      info->start[i] = base + (i * 0x00020000) - 0x00060000;
+    }
+  } else {
+    /* set sector offsets for top boot block type		*/
+    i = info->sector_count - 1;
+    info->start[i--] = base + info->size - 0x00008000;
+    info->start[i--] = base + info->size - 0x0000C000;
+    info->start[i--] = base + info->size - 0x00010000;
+    for (; i >= 0; i--) {
+      info->start[i] = base + i * 0x00020000;
+    }
+  }
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+  int i;
+
+  if (info->flash_id == FLASH_UNKNOWN) {
+    printf ("missing or unknown FLASH type\n");
+    return;
+  }
+
+  switch (info->flash_id & FLASH_VENDMASK) {
+  case FLASH_MAN_AMD:	printf ("AMD ");		break;
+  case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+  default:		printf ("Unknown Vendor ");	break;
+  }
+
+  switch (info->flash_id & FLASH_TYPEMASK) {
+  case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+    break;
+  case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+    break;
+  case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+    break;
+  case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+    break;
+  case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+    break;
+  case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+    break;
+  case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+    break;
+  case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+    break;
+  default:		printf ("Unknown Chip Type\n");
+    break;
+  }
+
+  printf ("  Size: %ld MB in %d Sectors\n",
+	  info->size >> 20, info->sector_count);
+
+  printf ("  Sector Start Addresses:");
+  for (i=0; i<info->sector_count; ++i) {
+    if ((i % 5) == 0)
+      printf ("\n   ");
+    printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+	    );
+  }
+  printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+  short i;
+  ulong value;
+  ulong base = (ulong)addr;
+
+
+  /* Write auto select command: read Manufacturer ID */
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+  addr[0x0555] = 0x00900090;
+
+  value = addr[0];
+
+  switch (value) {
+  case AMD_MANUFACT:
+    info->flash_id = FLASH_MAN_AMD;
+    break;
+  case FUJ_MANUFACT:
+    info->flash_id = FLASH_MAN_FUJ;
+    break;
+  default:
+    info->flash_id = FLASH_UNKNOWN;
+    info->sector_count = 0;
+    info->size = 0;
+    return (0);			/* no or unknown flash	*/
+  }
+
+  value = addr[1];			/* device ID		*/
+
+  switch (value) {
+  case AMD_ID_LV400T:
+    info->flash_id += FLASH_AM400T;
+    info->sector_count = 11;
+    info->size = 0x00100000;
+    break;				/* => 1 MB		*/
+
+  case AMD_ID_LV400B:
+    info->flash_id += FLASH_AM400B;
+    info->sector_count = 11;
+    info->size = 0x00100000;
+    break;				/* => 1 MB		*/
+
+  case AMD_ID_LV800T:
+    info->flash_id += FLASH_AM800T;
+    info->sector_count = 19;
+    info->size = 0x00200000;
+    break;				/* => 2 MB		*/
+
+  case AMD_ID_LV800B:
+    info->flash_id += FLASH_AM800B;
+    info->sector_count = 19;
+    info->size = 0x00200000;
+    break;				/* => 2 MB		*/
+
+  case AMD_ID_LV160T:
+    info->flash_id += FLASH_AM160T;
+    info->sector_count = 35;
+    info->size = 0x00400000;
+    break;				/* => 4 MB		*/
+
+  case AMD_ID_LV160B:
+    info->flash_id += FLASH_AM160B;
+    info->sector_count = 35;
+    info->size = 0x00400000;
+    break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+  case AMD_ID_LV320T:
+    info->flash_id += FLASH_AM320T;
+    info->sector_count = 67;
+    info->size = 0x00800000;
+    break;				/* => 8 MB		*/
+
+  case AMD_ID_LV320B:
+    info->flash_id += FLASH_AM320B;
+    info->sector_count = 67;
+    info->size = 0x00800000;
+    break;				/* => 8 MB		*/
+#endif
+  default:
+    info->flash_id = FLASH_UNKNOWN;
+    return (0);			/* => no or unknown flash */
+
+  }
+
+  /* set up sector start address table */
+  if (info->flash_id & FLASH_BTYPE) {
+    /* set sector offsets for bottom boot block type	*/
+    info->start[0] = base + 0x00000000;
+    info->start[1] = base + 0x00008000;
+    info->start[2] = base + 0x0000C000;
+    info->start[3] = base + 0x00010000;
+    for (i = 4; i < info->sector_count; i++) {
+      info->start[i] = base + (i * 0x00020000) - 0x00060000;
+    }
+  } else {
+    /* set sector offsets for top boot block type		*/
+    i = info->sector_count - 1;
+    info->start[i--] = base + info->size - 0x00008000;
+    info->start[i--] = base + info->size - 0x0000C000;
+    info->start[i--] = base + info->size - 0x00010000;
+    for (; i >= 0; i--) {
+      info->start[i] = base + i * 0x00020000;
+    }
+  }
+
+  /* check for protected sectors */
+  for (i = 0; i < info->sector_count; i++) {
+    /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+    /* D0 = 1 if protected */
+    addr = (volatile unsigned long *)(info->start[i]);
+    info->protect[i] = addr[2] & 1;
+  }
+
+  /*
+   * Prevent writes to uninitialized FLASH.
+   */
+  if (info->flash_id != FLASH_UNKNOWN) {
+    addr = (volatile unsigned long *)info->start[0];
+
+    *addr = 0x00F000F0;	/* reset bank */
+  }
+
+  return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+  vu_long *addr = (vu_long*)(info->start[0]);
+  int flag, prot, sect, l_sect;
+  ulong start, now, last;
+
+  if ((s_first < 0) || (s_first > s_last)) {
+    if (info->flash_id == FLASH_UNKNOWN) {
+      printf ("- missing\n");
+    } else {
+      printf ("- no sectors to erase\n");
+    }
+    return 1;
+  }
+
+  if ((info->flash_id == FLASH_UNKNOWN) ||
+      (info->flash_id > FLASH_AMD_COMP)) {
+    printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+    return 1;
+  }
+
+  prot = 0;
+  for (sect=s_first; sect<=s_last; ++sect) {
+    if (info->protect[sect]) {
+      prot++;
+    }
+  }
+
+  if (prot) {
+    printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+  } else {
+    printf ("\n");
+  }
+
+  l_sect = -1;
+
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+  addr[0x0555] = 0x00800080;
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+
+  /* Start erase on unprotected sectors */
+  for (sect = s_first; sect<=s_last; sect++) {
+    if (info->protect[sect] == 0) {	/* not protected */
+      addr = (vu_long*)(info->start[sect]);
+      addr[0] = 0x00300030;
+      l_sect = sect;
+    }
+  }
+
+  /* re-enable interrupts if necessary */
+  if (flag)
+    enable_interrupts();
+
+  /* wait at least 80us - let's wait 1 ms */
+  udelay (1000);
+
+  /*
+   * We wait for the last triggered sector
+   */
+  if (l_sect < 0)
+    goto DONE;
+
+  start = get_timer (0);
+  last  = start;
+  addr = (vu_long*)(info->start[l_sect]);
+  while ((addr[0] & 0x00800080) != 0x00800080) {
+    if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+      printf ("Timeout\n");
+      return 1;
+    }
+    /* show that we're waiting */
+    if ((now - last) > 1000) {	/* every second */
+      putc ('.');
+      last = now;
+    }
+  }
+
+ DONE:
+  /* reset to read mode */
+  addr = (volatile unsigned long *)info->start[0];
+  addr[0] = 0x00F000F0;	/* reset bank */
+
+  printf (" done\n");
+  return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+  ulong cp, wp, data;
+  int i, l, rc;
+
+  wp = (addr & ~3);	/* get lower word aligned address */
+
+  /*
+   * handle unaligned start bytes
+   */
+  if ((l = addr - wp) != 0) {
+    data = 0;
+    for (i=0, cp=wp; i<l; ++i, ++cp) {
+      data = (data << 8) | (*(uchar *)cp);
+    }
+    for (; i<4 && cnt>0; ++i) {
+      data = (data << 8) | *src++;
+      --cnt;
+      ++cp;
+    }
+    for (; cnt==0 && i<4; ++i, ++cp) {
+      data = (data << 8) | (*(uchar *)cp);
+    }
+
+    if ((rc = write_word(info, wp, data)) != 0) {
+      return (rc);
+    }
+    wp += 4;
+  }
+
+  /*
+   * handle word aligned part
+   */
+  while (cnt >= 4) {
+    data = 0;
+    for (i=0; i<4; ++i) {
+      data = (data << 8) | *src++;
+    }
+    if ((rc = write_word(info, wp, data)) != 0) {
+      return (rc);
+    }
+    wp  += 4;
+    cnt -= 4;
+  }
+
+  if (cnt == 0) {
+    return (0);
+  }
+
+  /*
+   * handle unaligned tail bytes
+   */
+  data = 0;
+  for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+    data = (data << 8) | *src++;
+    --cnt;
+  }
+  for (; i<4; ++i, ++cp) {
+    data = (data << 8) | (*(uchar *)cp);
+  }
+
+  return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+  vu_long *addr = (vu_long*)(info->start[0]);
+  ulong start;
+  int flag;
+
+  /* Check if Flash is (sufficiently) erased */
+  if ((*((vu_long *)dest) & data) != data) {
+    return (2);
+  }
+  /* Disable interrupts which might cause a timeout here */
+  flag = disable_interrupts();
+
+  addr[0x0555] = 0x00AA00AA;
+  addr[0x02AA] = 0x00550055;
+  addr[0x0555] = 0x00A000A0;
+
+  *((vu_long *)dest) = data;
+
+  /* re-enable interrupts if necessary */
+  if (flag)
+    enable_interrupts();
+
+  /* data polling for D7 */
+  start = get_timer (0);
+  while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+    if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+      return (1);
+    }
+  }
+  return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds
new file mode 100755
index 0000000..42e1b83
--- /dev/null
+++ b/board/siemens/IAD210/u-boot.lds
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    cpu/mpc8xx/interrupts.o (.text)
+    lib_ppc/time.o		(.text)
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile
new file mode 100755
index 0000000..af646e4
--- /dev/null
+++ b/board/siemens/SCM/Makefile
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= scm.o flash.o fpga_scm.o ../common/fpga.o \
+	  ../../tqm8xx/load_sernum_ethaddr.o
+
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/siemens/SCM/config.mk b/board/siemens/SCM/config.mk
new file mode 100755
index 0000000..855ae38
--- /dev/null
+++ b/board/siemens/SCM/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Siemens SCM boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_SCM.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c
new file mode 100755
index 0000000..056fe81
--- /dev/null
+++ b/board/siemens/SCM/flash.c
@@ -0,0 +1,488 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AMD devices on the TQM8260 board
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset (void)
+{
+	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
+		V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
+		V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	/* Write auto select command sequence and test FLASH answer */
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
+
+	flashtest_h = V_ULONG (baseaddr);	/* manufacturer ID     */
+	flashtest_l = V_ULONG (baseaddr + 4);
+
+	switch ((int) flashtest_h) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash     */
+	}
+
+	flashtest_h = V_ULONG (baseaddr + 8);	/* device ID           */
+	flashtest_l = V_ULONG (baseaddr + 12);
+	if (flashtest_h != flashtest_l) {
+		info->flash_id = FLASH_UNKNOWN;
+	} else {
+		switch (flashtest_h) {
+		case AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV800B:
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV160T:
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_LV160B:
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_DL322T:
+			info->flash_id += FLASH_AMDL322T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL322B:
+			info->flash_id += FLASH_AMDL322B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323T:
+			info->flash_id += FLASH_AMDL323T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323B:
+			info->flash_id += FLASH_AMDL323B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_LV640U:
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x02000000;
+			break;			/* 4 * 8 MB = 32 MB */
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);		/* no or unknown flash     */
+		}
+	}
+
+	if (flashtest_h == AMD_ID_LV640U) {
+
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+
+	} else if (info->flash_id & FLASH_BTYPE) {
+
+		/* set up sector start adress table (bottom sector type) */
+		info->start[0] = baseaddr + 0x00000000;
+		info->start[1] = baseaddr + 0x00010000;
+		info->start[2] = baseaddr + 0x00018000;
+		info->start[3] = baseaddr + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
+		}
+
+	} else {
+
+		/* set up sector start adress table (top sector type) */
+		i = info->sector_count - 1;
+		info->start[i--] = baseaddr + info->size - 0x00010000;
+		info->start[i--] = baseaddr + info->size - 0x00018000;
+		info->start[i--] = baseaddr + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = baseaddr + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
+			(V_ULONG (info->start[i] + 20) & 0x00010001)) {
+			info->protect[i] = 1;	/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset ();
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		printf ("29LV800T (8 M, top sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("29LV800T (8 M, bottom sector)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("29LV160T (16 M, top sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("29LV160B (16 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:
+		printf ("29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:
+		printf ("29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:
+		printf ("29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:
+		printf ("29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AM640U:
+		printf ("29LV640D (64 M, uniform sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			V_ULONG (info->start[sect]) = 0x00300030;
+			V_ULONG (info->start[sect] + 4) = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
+	       (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
+	{
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+static int write_dword (flash_info_t *, ulong, unsigned char *);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);		/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
+		if ((rc = write_dword (info, dp, bb)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword (info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
+	}
+	return (write_dword (info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
+{
+	ulong start, cl, ch;
+	int flag, i;
+
+	for (ch = 0, i = 0; i < 4; i++)
+		ch = (ch << 8) + *pdata++;	/* high word    */
+	for (cl = 0, i = 0; i < 4; i++)
+		cl = (cl << 8) + *pdata++;	/* low word */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & ch) != ch
+		|| (*((vu_long *) (dest + 4)) & cl) != cl) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest) = ch;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest + 4) = cl;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
+		   ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c
new file mode 100755
index 0000000..661bf66
--- /dev/null
+++ b/board/siemens/SCM/fpga_scm.c
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <mpc8260.h>
+#include <common.h>
+#include "../common/fpga.h"
+
+fpga_t fpga_list[] = {
+	{"FIOX", CFG_FIOX_BASE,
+	 CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE}
+	,
+	{"FDOHM", CFG_FDOHM_BASE,
+	 CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE}
+};
+int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
+
+
+ulong fpga_control (fpga_t * fpga, int cmd)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	switch (cmd) {
+	case FPGA_INIT_IS_HIGH:
+		immr->im_ioport.iop_pdird &= ~fpga->init_mask;	/* input */
+		return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1 : 0;
+
+	case FPGA_INIT_SET_LOW:
+		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
+		immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
+		break;
+
+	case FPGA_INIT_SET_HIGH:
+		immr->im_ioport.iop_pdird |= fpga->init_mask;	/* output */
+		immr->im_ioport.iop_pdatd |= fpga->init_mask;
+		break;
+
+	case FPGA_PROG_SET_LOW:
+		immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
+		break;
+
+	case FPGA_PROG_SET_HIGH:
+		immr->im_ioport.iop_pdatd |= fpga->prog_mask;
+		break;
+
+	case FPGA_DONE_IS_HIGH:
+		return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1 : 0;
+
+	case FPGA_READ_MODE:
+		break;
+
+	case FPGA_LOAD_MODE:
+		break;
+
+	case FPGA_GET_ID:
+		if (fpga->conf_base == CFG_FIOX_BASE) {
+			ulong ver =
+				*(volatile ulong *) (fpga->conf_base + 0x10);
+			return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
+		} else if (fpga->conf_base == CFG_FDOHM_BASE) {
+			return (*(volatile ushort *) fpga->conf_base) & 0xff;
+		} else {
+			return *(volatile ulong *) fpga->conf_base;
+		}
+
+	case FPGA_INIT_PORTS:
+		immr->im_ioport.iop_ppard &= ~fpga->init_mask;	/* INIT I/O */
+		immr->im_ioport.iop_psord &= ~fpga->init_mask;
+		immr->im_ioport.iop_pdird &= ~fpga->init_mask;
+
+		immr->im_ioport.iop_ppard &= ~fpga->prog_mask;	/* PROG Output */
+		immr->im_ioport.iop_psord &= ~fpga->prog_mask;
+		immr->im_ioport.iop_pdird |= fpga->prog_mask;
+
+		immr->im_ioport.iop_ppard &= ~fpga->done_mask;	/* DONE Input */
+		immr->im_ioport.iop_psord &= ~fpga->done_mask;
+		immr->im_ioport.iop_pdird &= ~fpga->done_mask;
+
+		break;
+
+	}
+	return 0;
+}
diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c
new file mode 100755
index 0000000..d20688d
--- /dev/null
+++ b/board/siemens/SCM/scm.c
@@ -0,0 +1,540 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+#include "scm.h"
+
+static void config_scoh_cs(void);
+extern int  fpga_init(void);
+
+#if 0
+#define DEBUGF(fmt,args...)   printf (fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1]*/
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   },
+	/* PA9  */ {   1,   1,   1,   1,   0,   0   }, /* TDM_A1 L1TXD0 */
+	/* PA8  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RXD0 */
+	/* PA7  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1TSYNC */
+	/* PA6  */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A1 L1RSYNC */
+	/* PA5  */ {   1,   0,   0,   0,   0,   0   }, /* FIOX_FPGA_PR */
+	/* PA4  */ {   1,   0,   0,   0,   0,   0   }, /* DOHM_FPGA_PR */
+	/* PA3  */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK4 */
+	/* PA2  */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK4 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   },
+	/* PA0  */ {   1,   0,   0,   0,   0,   0   }  /* BUSY */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MIN */
+	/* PB30 */ {   1,   0,   0,   1,   0,   0   }, /* EQ_ALARM_MAJ */
+	/* PB29 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MIN */
+	/* PB28 */ {   1,   0,   0,   1,   0,   0   }, /* COM_ALARM_MAJ */
+	/* PB27 */ {   0,   1,   0,   0,   0,   0   },
+	/* PB26 */ {   0,   1,   0,   0,   0,   0   },
+	/* PB25 */ {   1,   0,   0,   1,   0,   0   }, /* LED_GREEN_L */
+	/* PB24 */ {   1,   0,   0,   1,   0,   0   }, /* LED_RED_L */
+	/* PB23 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TXD */
+	/* PB22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RXD */
+	/* PB21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1TSYNC */
+	/* PB20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_D2 L1RSYNC */
+	/* PB19 */ {   1,   0,   0,   0,   0,   0   }, /* UID */
+	/* PB18 */ {   0,   1,   0,   0,   0,   0   },
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_DV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_ER */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_ER */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[3] */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[2] */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[1] */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RxD[0] */
+	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[3] */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[2] */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[1] */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3 MII TxD[0] */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK1 */
+	/* PC30 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK1 */
+	/* PC29 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK3 */
+	/* PC28 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK3 */
+	/* PC27 */ {   1,   1,   0,   0,   0,   0   }, /* TDM RXCLK2 */
+	/* PC26 */ {   1,   1,   0,   0,   0,   0   }, /* TDM TXCLK2 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   },
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC19 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC18 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII RX_CLK */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3 MII TX_CLK */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   },
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* RES_PHY_L */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   },
+	/* PC9  */ {   0,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TSYNC */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* FEP_RDY */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   },
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* UC4_ALARM_L */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* UC3_ALARM_L */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* UC2_ALARM_L */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* RES_MISC_L */
+	/* PC2  */ {   0,   0,   0,   1,   0,   0   }, /* RES_OH_L */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* RES_DOHM_L */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* RES_FIOX_L */
+    },
+
+    /* Port D configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* INIT_F */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_F */
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* INIT_D */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* DONE_D */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   },
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   },
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   },
+	/* PD22 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1TXD */
+	/* PD21 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RXD */
+	/* PD20 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_A2 L1RSYNC */
+	/* PD19 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPISEL */
+	/* PD18 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPICLK */
+	/* PD17 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSI */
+	/* PD16 */ {   1,   1,   1,   0,   0,   0   }, /* SPI SPIMOSO */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TXD */
+	/* PD12 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RXD */
+	/* PD11 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1TSYNC */
+	/* PD10 */ {   1,   1,   1,   0,   0,   0   }, /* TDM_B1 L1RSYNC */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   },
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   },
+	/* PD5  */ {   0,   0,   0,   1,   0,   0   }, /* PROG_F */
+	/* PD4  */ {   0,   0,   0,   1,   0,   0   }, /* PROG_D */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (!i || strncmp (str, "TQM8260", 7)) {
+		puts ("### No HW ID - assuming TQM8260\n");
+		return (0);
+	}
+
+	puts (str);
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
+	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+/*
+ * Test Power-On-Reset.
+ */
+int power_on_reset (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Test Reset Status Register */
+	return gd->reset_status & RSR_CSRS ? 0 : 1;
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	long size8, size9;
+#endif
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#if 0							/* Just for debugging */
+#define	prt_br_or(brX,orX) do {				\
+    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
+    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
+    printf ("\n"					\
+	    #brX " 0x%08x  " #orX " 0x%08x "		\
+	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
+	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
+	start, start+sizem, (sizem+1)>>20);		\
+    } while (0)
+	prt_br_or (br0, or0);
+	prt_br_or (br1, or1);
+	prt_br_or (br2, or2);
+	prt_br_or (br3, or3);
+#endif
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+					  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
+					  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL - %ld MB, ", psize >> 20);
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+						  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL - %ld MB, ", psize >> 20);
+	}
+
+	/* Local SDRAM setup:
+	 */
+#ifdef CFG_INIT_LOCAL_SDRAM
+	memctl->memc_lsrt = CFG_LSRT;
+	size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+	size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+
+	if (size8 < size9) {
+		lsize = size9;
+		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
+	} else {
+		lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+						  (uchar *) SDRAM_BASE2_PRELIM);
+		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
+	}
+
+#if 0
+	/* Set up BR2 so that the local SDRAM goes
+	 * right after the 60x SDRAM
+	 */
+	memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
+			(CFG_SDRAM_BASE + psize);
+#endif
+#endif /* CFG_INIT_LOCAL_SDRAM */
+#endif /* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	config_scoh_cs ();
+
+	return (psize);
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void config_scoh_cs (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+	volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE;
+	volatile uint tmp, i;
+
+	/* Initialize OR3 / BR3 for CAN Bus Controller 0 */
+	memctl->memc_or3 = CFG_CAN0_OR3;
+	memctl->memc_br3 = CFG_CAN0_BR3;
+	/* Initialize OR4 / BR4 for CAN Bus Controller 1 */
+	memctl->memc_or4 = CFG_CAN1_OR4;
+	memctl->memc_br4 = CFG_CAN1_BR4;
+
+	/* Initialize MAMR to write in the array at address 0x0 */
+	memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
+
+	/* Initialize UPMA for CAN: single read */
+	memctl->memc_mdr = 0xcffeec00;
+	udelay (1);					/* Necessary to have the data correct in the UPM array!!!! */
+	/* The read on the CAN controller write the data of mdr in UPMA array. */
+	/* The index to the array will be incremented automatically
+	   through this read */
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcfc00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x0ffcfc00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0xfffdec07;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+
+	/* Initialize MAMR to write in the array at address 0x18 */
+	memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
+
+	/* Initialize UPMA for CAN: single write */
+	memctl->memc_mdr = 0xfcffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00ffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00ffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00ffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00ffec00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00fffc00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x00fffc00;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	memctl->memc_mdr = 0x30ffec07;
+	udelay (1);
+	tmp = can->cpu_interface;
+
+	/* Initialize MAMR */
+	memctl->memc_mamr = MxMR_GPL_x4DIS;	/* GPL_B4 ouput line Disable */
+
+
+	/* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
+	memctl->memc_or5 = CFG_EXTPROM_OR5;
+	memctl->memc_br5 = CFG_EXTPROM_BR5;
+	/* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
+	memctl->memc_or6 = CFG_EXTPROM_OR6;
+	memctl->memc_br6 = CFG_EXTPROM_BR6;
+
+	/* Initialize OR7 / BR7 for the Glue Logic */
+	memctl->memc_or7 = CFG_FIOX_OR7;
+	memctl->memc_br7 = CFG_FIOX_BR7;
+
+	/* Initialize OR8 / BR8 for the DOH Logic */
+	memctl->memc_or8 = CFG_FDOHM_OR8;
+	memctl->memc_br8 = CFG_FDOHM_BR8;
+
+	DEBUGF ("OR0 %08x   BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
+	DEBUGF ("OR1 %08x   BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
+	DEBUGF ("OR2 %08x   BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
+	DEBUGF ("OR3 %08x   BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
+	DEBUGF ("OR4 %08x   BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
+	DEBUGF ("OR5 %08x   BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
+	DEBUGF ("OR6 %08x   BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
+	DEBUGF ("OR7 %08x   BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
+	DEBUGF ("OR8 %08x   BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
+
+	DEBUGF ("UPMA  addr 0x0\n");
+	memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
+	for (i = 0; i < 0x8; i++) {
+		tmp = can->cpu_interface;
+		udelay (1);
+		DEBUGF (" %08x ", memctl->memc_mdr);
+	}
+	DEBUGF ("\nUPMA  addr 0x18\n");
+	memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
+	for (i = 0; i < 0x8; i++) {
+		tmp = can->cpu_interface;
+		udelay (1);
+		DEBUGF (" %08x ", memctl->memc_mdr);
+	}
+	DEBUGF ("\n");
+	memctl->memc_mamr = MxMR_GPL_x4DIS;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r (void)
+{
+	fpga_init ();
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/siemens/SCM/scm.h b/board/siemens/SCM/scm.h
new file mode 100755
index 0000000..70c12e6
--- /dev/null
+++ b/board/siemens/SCM/scm.h
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SCM_H
+#define __SCM_H
+
+/*----------------*/
+/* CAN Structures */
+/*----------------*/
+
+/* Message */
+typedef struct can_msg {
+    uchar	ctrl_0;
+    uchar	ctrl_1;
+    uchar	arbit_0;
+    uchar	arbit_1;
+    uchar	arbit_2;
+    uchar	arbit_3;
+    uchar	config;
+    uchar	data[8];
+} can_msg_t;
+
+/* CAN Register */
+typedef struct can_reg {
+    uchar	ctrl;
+    uchar	status;
+    uchar	cpu_interface;
+    uchar	resv0;
+    ushort	high_speed_rd;
+    ushort	gbl_mask_std;
+    uint	gbl_mask_extd;
+    uint	msg15_mask;
+    can_msg_t	msg1 __attribute__ ((packed));
+    uchar	clkout;
+    can_msg_t	msg2 __attribute__ ((packed));
+    uchar	bus_config;
+    can_msg_t	msg3 __attribute__ ((packed));
+    uchar	bit_timing_0;
+    can_msg_t	msg4 __attribute__ ((packed));
+    uchar	bit_timing_1;
+    can_msg_t	msg5 __attribute__ ((packed));
+    uchar	interrupt;
+    can_msg_t	msg6 __attribute__ ((packed));
+    uchar	resv1;
+    can_msg_t	msg7 __attribute__ ((packed));
+    uchar	resv2;
+    can_msg_t	msg8 __attribute__ ((packed));
+    uchar	resv3;
+    can_msg_t	msg9 __attribute__ ((packed));
+    uchar	p1conf;
+    can_msg_t	msg10 __attribute__ ((packed));
+    uchar	p2conf;
+    can_msg_t	msg11 __attribute__ ((packed));
+    uchar	p1in;
+    can_msg_t	msg12 __attribute__ ((packed));
+    uchar	p2in;
+    can_msg_t	msg13 __attribute__ ((packed));
+    uchar	p1out;
+    can_msg_t	msg14 __attribute__ ((packed));
+    uchar	p2out;
+    can_msg_t	msg15 __attribute__ ((packed));
+    uchar	ser_res_addr;
+    uchar	resv_cs[0x8000-0x100];	/* 0x8000 is the min size for CS */
+} can_reg_t;
+
+
+#endif /* __SCM_H */
diff --git a/board/siemens/SCM/u-boot.lds b/board/siemens/SCM/u-boot.lds
new file mode 100755
index 0000000..05f29c6
--- /dev/null
+++ b/board/siemens/SCM/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/siemens/common/README b/board/siemens/common/README
new file mode 100755
index 0000000..7f1c8cd
--- /dev/null
+++ b/board/siemens/common/README
@@ -0,0 +1,27 @@
+CCM/SCM-Ergaenzungen fuer U-Boot und Linux:
+-------------------------------------------
+
+Es gibt nun ein gemeinsames Kommando zum Laden der FPGAs:
+
+  => help fpga
+  fpga fpga status [name] - print FPGA status
+  fpga reset  [name] - reset FPGA
+  fpga load [name] addr - load FPGA configuration data
+
+Der Name kann beim CCM-Module auch weggelassen werden.
+Die Laengenangabe und damit "puma_len" ist nicht mehr
+noetig:
+
+  => fpga load puma 40600000
+  FPGA load PUMA: addr 40600000: (00000005)... done
+
+Die MTD-Partitionierung kann nun mittels "bootargs" ueber-
+geben werden:
+
+  => printenv addmtd
+  addmtd=setenv bootargs ${bootargs}
+    mtdparts=0:256k(U-Boot)ro,768k(Kernel),-(Rest)\;1:-(myJFFS2)
+
+Die Portierung auf SMC ist natuerlich noch nicht getestet.
+
+Wolfgang Grandegger (04.06.2002)
diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c
new file mode 100755
index 0000000..e9941cd
--- /dev/null
+++ b/board/siemens/common/fpga.c
@@ -0,0 +1,364 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <common.h>
+
+#include "fpga.h"
+
+int  power_on_reset(void);
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+
+static int fpga_get_version(fpga_t* fpga, char* name)
+{
+    char vname[12];
+    /*
+     * Net-list string format:
+     *     "vvvvvvvvddddddddn...".
+     *     Version Date    Name
+     *     "0000000322042002PUMA" = PUMA version 3 from 22.04.2002.
+     */
+    if (strlen(name) < (16 + strlen(fpga->name)))
+	goto failure;
+    /* Check FPGA name */
+    if (strcmp(&name[16], fpga->name) != 0)
+	goto failure;
+    /* Get version number */
+    memcpy(vname, name, 8);
+    vname[8] = '\0';
+    return simple_strtoul(vname, NULL, 16);
+
+ failure:
+    printf("Image name %s is invalid\n", name);
+    return -1;
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static fpga_t* fpga_get(char* fpga_name)
+{
+    char name[FPGA_NAME_LEN];
+    int i;
+
+    if (strlen(fpga_name) >= FPGA_NAME_LEN)
+	goto failure;
+    for (i = 0; i < strlen(fpga_name); i++)
+	name[i] = toupper(fpga_name[i]);
+    name[i] = '\0';
+    for (i = 0; i < fpga_count; i++) {
+	if (strcmp(name, fpga_list[i].name) == 0)
+	    return &fpga_list[i];
+    }
+ failure:
+    printf("FPGA: name %s is invalid\n", fpga_name);
+    return NULL;
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static void fpga_status (fpga_t* fpga)
+{
+    /* Check state */
+    if (fpga_control(fpga, FPGA_DONE_IS_HIGH))
+	printf ("%s is loaded (%08lx)\n",
+		fpga->name, fpga_control(fpga, FPGA_GET_ID));
+    else
+	printf ("%s is NOT loaded\n", fpga->name);
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+#define FPGA_RESET_TIMEOUT 100 /* = 10 ms */
+
+static int fpga_reset (fpga_t* fpga)
+{
+    int i;
+
+    /* Set PROG to low and wait til INIT goes low */
+    fpga_control(fpga, FPGA_PROG_SET_LOW);
+    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
+	udelay (100);
+	if (!fpga_control(fpga, FPGA_INIT_IS_HIGH))
+	    break;
+    }
+    if (i == FPGA_RESET_TIMEOUT)
+	goto failure;
+
+    /* Set PROG to high and wait til INIT goes high */
+    fpga_control(fpga, FPGA_PROG_SET_HIGH);
+    for (i = 0; i < FPGA_RESET_TIMEOUT; i++) {
+	udelay (100);
+	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
+	    break;
+    }
+    if (i == FPGA_RESET_TIMEOUT)
+	goto failure;
+
+    return 0;
+ failure:
+    return 1;
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+#define FPGA_LOAD_TIMEOUT 100 /* = 10 ms */
+
+static int fpga_load (fpga_t* fpga, ulong addr, int checkall)
+{
+    volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base;
+    image_header_t hdr;
+    ulong len, checksum;
+    uchar *data = (uchar *)&hdr;
+    char *s, msg[32];
+    int verify, i;
+
+    /*
+     * Check the image header and data of the net-list
+     */
+    memcpy (&hdr, (char *)addr, sizeof(image_header_t));
+
+    if (hdr.ih_magic != IH_MAGIC) {
+	strcpy (msg, "Bad Image Magic Number");
+	goto failure;
+    }
+
+    len  = sizeof(image_header_t);
+
+    checksum = hdr.ih_hcrc;
+    hdr.ih_hcrc = 0;
+
+    if (crc32 (0, data, len) != checksum) {
+	strcpy (msg, "Bad Image Header CRC");
+	goto failure;
+    }
+
+    data = (uchar*)(addr + sizeof(image_header_t));
+    len  = hdr.ih_size;
+
+    s = getenv ("verify");
+    verify = (s && (*s == 'n')) ? 0 : 1;
+    if (verify) {
+	if (crc32 (0, data, len) != hdr.ih_dcrc) {
+	    strcpy (msg, "Bad Image Data CRC");
+	    goto failure;
+	}
+    }
+
+    if (checkall && fpga_get_version(fpga, (char *)(hdr.ih_name)) < 0)
+	return 1;
+
+    /* align length */
+    if (len & 1)
+	++len;
+
+    /*
+     * Reset FPGA and wait for completion
+     */
+    if (fpga_reset(fpga)) {
+	strcpy (msg, "Reset Timeout");
+	goto failure;
+    }
+
+    printf ("(%s)... ", hdr.ih_name);
+    /*
+     * Copy data to FPGA
+     */
+    fpga_control (fpga, FPGA_LOAD_MODE);
+    while (len--) {
+	*fpga_addr = *data++;
+    }
+    fpga_control (fpga, FPGA_READ_MODE);
+
+    /*
+     * Wait for completion and check error status if timeout
+     */
+    for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) {
+	udelay (100);
+	if (fpga_control (fpga, FPGA_DONE_IS_HIGH))
+	    break;
+    }
+    if (i == FPGA_LOAD_TIMEOUT) {
+	if (fpga_control(fpga, FPGA_INIT_IS_HIGH))
+	    strcpy(msg, "Invalid Size");
+	else
+	    strcpy(msg, "CRC Error");
+	goto failure;
+    }
+
+    printf("done\n");
+    return 0;
+
+ failure:
+
+    printf("ERROR: %s\n", msg);
+    return 1;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+    ulong addr = 0;
+    int i;
+    fpga_t* fpga;
+
+    if (argc < 2)
+	goto failure;
+
+    if (strncmp(argv[1], "stat", 4) == 0) {		/* status */
+	if (argc == 2) {
+	    for (i = 0; i < fpga_count; i++) {
+		fpga_status (&fpga_list[i]);
+	    }
+	}
+	else if (argc == 3) {
+	    if ((fpga = fpga_get(argv[2])) == 0)
+		goto failure;
+	    fpga_status (fpga);
+	}
+	else
+	    goto failure;
+    }
+    else if (strcmp(argv[1],"load") == 0) {		/* load */
+	if (argc == 3 && fpga_count == 1) {
+	    fpga = &fpga_list[0];
+	}
+	else if (argc == 4) {
+	    if ((fpga = fpga_get(argv[2])) == 0)
+		goto failure;
+	}
+	else
+	    goto failure;
+
+	addr = simple_strtoul(argv[argc-1], NULL, 16);
+
+	printf ("FPGA load %s: addr %08lx: ",
+		fpga->name, addr);
+	fpga_load (fpga, addr, 1);
+
+    }
+    else if (strncmp(argv[1], "rese", 4) == 0) {	/* reset */
+	if (argc == 2 && fpga_count == 1) {
+	    fpga = &fpga_list[0];
+	}
+	else if (argc == 3) {
+	    if ((fpga = fpga_get(argv[2])) == 0)
+		goto failure;
+	}
+	else
+	    goto failure;
+
+	printf ("FPGA reset %s: ", fpga->name);
+	if (fpga_reset(fpga))
+	    printf ("ERROR: Timeout\n");
+	else
+	    printf ("done\n");
+    }
+    else
+	goto failure;
+
+    return 0;
+
+ failure:
+    printf ("Usage:\n%s\n", cmdtp->usage);
+    return 1;
+}
+
+U_BOOT_CMD(
+	fpga,	4,	1,	do_fpga,
+	"fpga    - access FPGA(s)\n",
+	"fpga status [name] - print FPGA status\n"
+	"fpga reset  [name] - reset FPGA\n"
+	"fpga load [name] addr - load FPGA configuration data\n"
+);
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_BSP */
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+int fpga_init (void)
+{
+    ulong addr;
+    ulong new_id, old_id = 0;
+    image_header_t *hdr;
+    fpga_t* fpga;
+    int do_load, i, j;
+    char name[16], *s;
+
+    /*
+     *  Port setup for FPGA control
+     */
+    for (i = 0; i < fpga_count; i++) {
+	fpga_control(&fpga_list[i], FPGA_INIT_PORTS);
+    }
+
+    /*
+     * Load FPGA(s): a new net-list is loaded if the FPGA is
+     * empty, Power-on-Reset or the old one is not up-to-date
+     */
+    for (i = 0; i < fpga_count; i++) {
+	fpga = &fpga_list[i];
+	printf ("%s:  ", fpga->name);
+
+	for (j = 0; j < strlen(fpga->name); j++)
+	    name[j] = tolower(fpga->name[j]);
+	name[j] = '\0';
+	sprintf(name, "%s_addr", name);
+	addr = 0;
+	if ((s = getenv(name)) != NULL)
+	    addr = simple_strtoul(s, NULL, 16);
+
+	if (!addr) {
+	    printf ("env. variable %s undefined\n", name);
+	    return 1;
+	}
+
+	hdr = (image_header_t *)addr;
+	if ((new_id = fpga_get_version(fpga, (char *)(hdr->ih_name))) == -1)
+	    return 1;
+
+	do_load = 1;
+
+	if (!power_on_reset() && fpga_control(fpga, FPGA_DONE_IS_HIGH)) {
+	    old_id = fpga_control(fpga, FPGA_GET_ID);
+	    if (new_id == old_id)
+		do_load = 0;
+	}
+
+	if (do_load) {
+	    printf ("loading ");
+	    fpga_load (fpga, addr, 0);
+	} else {
+	    printf ("loaded (%08lx)\n", old_id);
+	}
+    }
+
+    return 0;
+}
diff --git a/board/siemens/common/fpga.h b/board/siemens/common/fpga.h
new file mode 100755
index 0000000..2de25b0
--- /dev/null
+++ b/board/siemens/common/fpga.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+#define FPGA_INIT_IS_HIGH   0
+#define FPGA_INIT_SET_HIGH  1
+#define FPGA_INIT_SET_LOW   2
+#define FPGA_PROG_SET_HIGH  3
+#define FPGA_PROG_SET_LOW   4
+#define FPGA_DONE_IS_HIGH   5
+#define	FPGA_READ_MODE      6
+#define FPGA_LOAD_MODE      7
+#define FPGA_GET_ID         8
+#define FPGA_INIT_PORTS     9
+
+#define FPGA_NAME_LEN       8
+typedef struct {
+    char  name[FPGA_NAME_LEN];
+    ulong conf_base;
+    uint  init_mask;
+    uint  prog_mask;
+    uint  done_mask;
+} fpga_t;
+
+extern fpga_t fpga_list[];
+extern int    fpga_count;
+
+ulong fpga_control (fpga_t* fpga, int cmd);
+
+#endif /* _FPGA_H_ */
diff --git a/board/siemens/pcu_e/Makefile b/board/siemens/pcu_e/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/siemens/pcu_e/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/siemens/pcu_e/config.mk b/board/siemens/pcu_e/config.mk
new file mode 100755
index 0000000..10f3773
--- /dev/null
+++ b/board/siemens/pcu_e/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Siemens PCU E Boards
+#
+
+TEXT_BASE = 0xFFF00000
diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c
new file mode 100755
index 0000000..05c364b
--- /dev/null
+++ b/board/siemens/pcu_e/flash.c
@@ -0,0 +1,700 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ *
+ * The PCU E uses an address map where flash banks are aligned top
+ * down, so that the "first" flash bank ends at top of memory, and
+ * the monitor entry point is at address (0xFFF00100). The second
+ * flash bank is mapped immediately below bank 0.
+ *
+ * This is NOT in conformance to the "official" memory map!
+ *
+ */
+
+#define PCU_MONITOR_BASE   ( (flash_info[0].start[0] + flash_info[0].size - 1) \
+			   - (0xFFFFFFFF - CFG_MONITOR_BASE) )
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long base, size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	/*
+	 * Warning:
+	 *
+	 * Since the PCU E memory map assigns flash banks top down,
+	 * we swap the numbering later if both banks are equipped,
+	 * so they look like a contiguous area of memory.
+	 */
+	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE6_PRELIM);
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE6_PRELIM, &flash_info[1]);
+
+	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n", size_b0, size_b1);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	DEBUGF ("## Before remap: "
+		"BR0: 0x%08x    OR0: 0x%08x    "
+		"BR6: 0x%08x    OR6: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0,
+		memctl->memc_br6, memctl->memc_or6);
+
+	/* Remap FLASH according to real size */
+	base = 0 - size_b0;
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+
+	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)base, &flash_info[0]);
+	base = 0 - size_b0;
+
+	flash_info[0].size = size_b0;
+
+	flash_get_offsets (base, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      PCU_MONITOR_BASE,
+		      PCU_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		flash_info_t tmp_info;
+
+		memctl->memc_or6 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) |
+				    BR_PS_16 | BR_MS_GPCM | BR_V;
+
+		DEBUGF("## New BR6: 0x%08x    OR6: 0x%08x\n",
+			memctl->memc_br6, memctl->memc_or6);
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(base - size_b1),
+					  &flash_info[1]);
+		base -= size_b1;
+
+		flash_get_offsets (base, &flash_info[1]);
+
+		flash_info[1].size = size_b1;
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+			      &flash_info[1]);
+#endif
+		/*
+		 * Swap bank numbers so that addresses are in ascending order
+		 */
+		tmp_info = flash_info[0];
+		flash_info[0] = flash_info[1];
+		flash_info[1] = tmp_info;
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+
+	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	short n;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) {
+		return;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDL322T:
+	case FLASH_AMDL323T:
+	case FLASH_AMDL324T:
+		/* set sector offsets for top boot block type		*/
+
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		return;
+	case FLASH_AMDL322B:
+	case FLASH_AMDL323B:
+	case FLASH_AMDL324B:
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (base < info->size) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+		return;
+	case FLASH_AMDL640:
+		/* set sector offsets for dual boot block type		*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		n = info->sector_count - 8;
+		while (i < n) {			/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+		while (i < info->sector_count) { /* 8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+			++i;
+		}
+		return;
+	default:
+		return;
+	}
+	/* NOTREACHED */
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDL324B:	printf ("AM29DL324B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AMDL324T:	printf ("AM29DL324T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDL640:	printf ("AM29DL640D (64 Mbit, dual boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type 0x%lX\n",
+					info->flash_id);
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ushort value;
+	vu_short *saddr = (vu_short *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	saddr[0x0555] = 0x00AA;
+	saddr[0x02AA] = 0x0055;
+	saddr[0x0555] = 0x0090;
+
+	value = saddr[0];
+
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value);
+
+	switch (value) {
+	case (AMD_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFFFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		DEBUGF("Unknown Manufacturer ID\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = saddr[1];			/* device ID		*/
+
+	DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+
+	case (AMD_ID_DL322T & 0xFFFF):
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_DL322B & 0xFFFF):
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_DL323T & 0xFFFF):
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_DL323B & 0xFFFF):
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_DL324T & 0xFFFF):
+		info->flash_id += FLASH_AMDL324T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_DL324B & 0xFFFF):
+		info->flash_id += FLASH_AMDL324B;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 8 MB		*/
+	case (AMD_ID_DL640  & 0xFFFF):
+		info->flash_id += FLASH_AMDL640;
+		info->sector_count = 142;
+		info->size = 0x00800000;
+		break;
+	default:
+		DEBUGF("Unknown Device ID\n");
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	flash_get_offsets ((ulong)addr, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+#if 0
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		saddr = (vu_short *)(info->start[i]);
+		info->protect[i] = saddr[2] & 1;
+#else
+		info->protect[i] =0;
+#endif
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	saddr = (vu_short *)info->start[0];
+	*saddr = 0x00F0;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+	addr[0x0555] = 0x0080;
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_short*)(info->start[sect]);
+			addr[0] = 0x0030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_short*)(info->start[l_sect]);
+	while ((addr[0] & 0x0080) != 0x0080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_short *)info->start[0];
+	addr[0] = 0x00F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+#define FLASH_WIDTH	2	/* flash bus width in bytes */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower FLASH_WIDTH aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<FLASH_WIDTH && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		data = 0;
+		for (i=0; i<FLASH_WIDTH; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<FLASH_WIDTH; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_data(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_short *addr  = (vu_short*)(info->start[0]);
+	vu_short *sdest = (vu_short *)dest;
+	ushort sdata = (ushort)data;
+	ushort sval;
+	ulong start, passed;
+	int flag, rc;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*sdest & sdata) != sdata) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+	addr[0x0555] = 0x00A0;
+
+#ifdef WORKAROUND_FOR_BROKEN_HARDWARE
+	/* work around the timeout bugs */
+	udelay(20);
+#endif
+
+	*sdest = sdata;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	rc = 0;
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	for (passed=0; passed < CFG_FLASH_WRITE_TOUT; passed=get_timer(start)) {
+
+		sval = *sdest;
+
+		if ((sval & 0x0080) == (sdata & 0x0080))
+			break;
+
+		if ((sval & 0x0020) == 0)	/* DQ5: Timeout? */
+			continue;
+
+		sval = *sdest;
+
+		if ((sval & 0x0080) != (sdata & 0x0080))
+			rc = 1;
+
+		break;
+	}
+
+	if (rc) {
+	    DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n",
+		 dest, sval, sdata);
+	}
+
+	if (passed >= CFG_FLASH_WRITE_TOUT) {
+		DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n",
+			dest, sval, sdata);
+		rc = 1;
+	}
+
+	/* reset to read mode */
+	addr = (vu_short *)info->start[0];
+	addr[0] = 0x00F0;	/* reset bank */
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c
new file mode 100755
index 0000000..3f05e4a
--- /dev/null
+++ b/board/siemens/pcu_e/pcu_e.c
@@ -0,0 +1,563 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+#include <i2c.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+static void puma_status (void);
+static void puma_set_mode (int mode);
+static int puma_init_done (void);
+static void puma_load (ulong addr, ulong len);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+/*
+ * 50 MHz SDRAM access using UPM A
+ */
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
+	0x1ffddc47,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPM RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1ffddc35, 0xefceac34, 0x1f3d5c35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
+	0xf0affc00, 0xe1beec04, 0x1ffddc47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7ffffc07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * PUMA access using UPM B
+ */
+const uint puma_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+	/*
+	 * Precharge and MRS
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x0ffff804, 0x0ffff400, 0x3ffffc47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7ffffc07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+	puts ("Board: Siemens PCU E\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+	long int size_b0, reg;
+	int i;
+
+	/*
+	 * Configure UPMA for SDRAM
+	 */
+	upmconfig (UPMA, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	/* burst length=4, burst type=sequential, CAS latency=2 */
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 2 to the SDRAM bank at preliminary address.
+	 */
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+	memctl->memc_or5 = CFG_OR5_PRELIM;
+	memctl->memc_br5 = CFG_BR5_PRELIM;
+#else  /* XXX */
+	memctl->memc_or2 = CFG_OR2_PRELIM;
+	memctl->memc_br2 = CFG_BR2_PRELIM;
+#endif /* XXX */
+
+	/* initialize memory address register */
+	memctl->memc_mamr = CFG_MAMR;	/* refresh not enabled yet */
+
+	/* mode initialization (offset 5) */
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+	udelay (200);		/* 0x8000A105 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
+#else  /* XXX */
+	udelay (200);		/* 0x80004105 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
+#endif /* XXX */
+
+	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+	udelay (1);		/* 0x8000A830 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
+#else  /* XXX */
+	udelay (1);		/* 0x80004830 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
+#endif /* XXX */
+
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+	udelay (1);		/* 0x8000A106 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
+#else  /* XXX */
+	udelay (1);		/* 0x80004106 */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
+#endif /* XXX */
+
+	reg = memctl->memc_mamr;
+	reg &= ~MAMR_TLFA_MSK;	/* switch timer loop ... */
+	reg |= MAMR_TLFA_4X;	/* ... to 4x */
+	reg |= MAMR_PTAE;	/* enable refresh */
+	memctl->memc_mamr = reg;
+
+	udelay (200);
+
+	/* Need at least 10 DRAM accesses to stabilize */
+	for (i = 0; i < 10; ++i) {
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+		volatile unsigned long *addr =
+			(volatile unsigned long *) SDRAM_BASE5_PRELIM;
+#else  /* XXX */
+		volatile unsigned long *addr =
+			(volatile unsigned long *) SDRAM_BASE2_PRELIM;
+#endif /* XXX */
+		unsigned long val;
+
+		val = *(addr + i);
+		*(addr + i) = val;
+	}
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 */
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+	size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
+#else  /* XXX */
+	size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+#endif /* XXX */
+
+	memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
+
+	/*
+	 * Final mapping:
+	 */
+
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+	memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
+	memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+#else  /* XXX */
+	memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
+	memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+#endif /* XXX */
+	udelay (1000);
+
+	/*
+	 * Configure UPMB for PUMA
+	 */
+	upmconfig (UPMB, (uint *) puma_table,
+		   sizeof (puma_table) / sizeof (uint));
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+#define	ETH_CFG_BITS	(CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2  | CFG_PB_ETH_CFG3 )
+#else  /* XXX */
+#define	ETH_CFG_BITS	(CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
+			 CFG_PB_ETH_CFG2  | CFG_PB_ETH_CFG3 )
+#endif /* XXX */
+
+#define ETH_ALL_BITS	(ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
+
+void reset_phy (void)
+{
+	immap_t *immr = (immap_t *) CFG_IMMR;
+	ulong value;
+
+	/* Configure all needed port pins for GPIO */
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+# ifdef CFG_ETH_MDDIS_VALUE
+	immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
+# else
+	immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS);	/* Set low */
+# endif
+	immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS);	/* GPIO */
+	immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS);	/* active output */
+	immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS;	/* output */
+#endif /* XXX */
+	immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS);	/* active output */
+
+	value = immr->im_cpm.cp_pbdat;
+
+	/* Assert Powerdown and Reset signals */
+	value |= CFG_PB_ETH_POWERDOWN;
+	value &= ~(CFG_PB_ETH_RESET);
+
+	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
+#if !PCU_E_WITH_SWAPPED_CS
+# ifdef CFG_ETH_MDDIS_VALUE
+	value |= CFG_PB_ETH_MDDIS;
+# else
+	value &= ~(CFG_PB_ETH_MDDIS);
+# endif
+#endif
+#ifdef CFG_ETH_CFG1_VALUE
+	value |= CFG_PB_ETH_CFG1;
+#else
+	value &= ~(CFG_PB_ETH_CFG1);
+#endif
+#ifdef CFG_ETH_CFG2_VALUE
+	value |= CFG_PB_ETH_CFG2;
+#else
+	value &= ~(CFG_PB_ETH_CFG2);
+#endif
+#ifdef CFG_ETH_CFG3_VALUE
+	value |= CFG_PB_ETH_CFG3;
+#else
+	value &= ~(CFG_PB_ETH_CFG3);
+#endif
+
+	/* Drive output signals to initial state */
+	immr->im_cpm.cp_pbdat = value;
+	immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
+	udelay (10000);
+
+	/* De-assert Ethernet Powerdown */
+	immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN);	/* Enable PHY power */
+	udelay (10000);
+
+	/* de-assert RESET signal of PHY */
+	immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
+	udelay (1000);
+}
+
+/*-----------------------------------------------------------------------
+ * Board Special Commands: access functions for "PUMA" FPGA
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#define	PUMA_READ_MODE	0
+#define PUMA_LOAD_MODE	1
+
+int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	ulong addr, len;
+
+	switch (argc) {
+	case 2:		/* PUMA reset */
+		if (strncmp (argv[1], "stat", 4) == 0) {	/* Reset */
+			puma_status ();
+			return 0;
+		}
+		break;
+	case 4:		/* PUMA load addr len */
+		if (strcmp (argv[1], "load") != 0)
+			break;
+
+		addr = simple_strtoul (argv[2], NULL, 16);
+		len = simple_strtoul (argv[3], NULL, 16);
+
+		printf ("PUMA load: addr %08lX len %ld (0x%lX):  ",
+			addr, len, len);
+		puma_load (addr, len);
+
+		return 0;
+	default:
+		break;
+	}
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD (puma, 4, 1, do_puma,
+	    "puma    - access PUMA FPGA\n",
+	    "status - print PUMA status\n"
+	    "puma load addr len - load PUMA configuration data\n");
+
+#endif /* CFG_CMD_BSP */
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static void puma_set_mode (int mode)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immr->im_memctl;
+
+	/* disable PUMA in memory controller */
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+	memctl->memc_br3 = 0;
+#else  /* XXX */
+	memctl->memc_br4 = 0;
+#endif /* XXX */
+
+	switch (mode) {
+	case PUMA_READ_MODE:
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+		memctl->memc_or3 = PUMA_CONF_OR_READ;
+		memctl->memc_br3 = PUMA_CONF_BR_READ;
+#else  /* XXX */
+		memctl->memc_or4 = PUMA_CONF_OR_READ;
+		memctl->memc_br4 = PUMA_CONF_BR_READ;
+#endif /* XXX */
+		break;
+	case PUMA_LOAD_MODE:
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+		memctl->memc_or3 = PUMA_CONF_OR_LOAD;
+		memctl->memc_br3 = PUMA_CONF_BR_LOAD;
+#else  /* XXX */
+		memctl->memc_or4 = PUMA_CONF_OR_READ;
+		memctl->memc_br4 = PUMA_CONF_BR_READ;
+#endif /* XXX */
+		break;
+	}
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+#define	PUMA_INIT_TIMEOUT	1000	/* max. 1000 ms = 1 second */
+
+static void puma_load (ulong addr, ulong len)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE;	/* XXX ??? */
+	uchar *data = (uchar *) addr;
+	int i;
+
+	/* align length */
+	if (len & 1)
+		++len;
+
+	/* Reset FPGA */
+	immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT);	/* make input */
+	immr->im_ioport.iop_pcso  &= ~(CFG_PC_PUMA_INIT);
+	immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
+
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+	immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG);		/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG);		/* active output */
+	immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG);		/* Set low */
+	immr->im_cpm.cp_pbdir |=   CFG_PB_PUMA_PROG;		/* output */
+#else
+	immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG);	/* GPIO */
+	immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG);	/* Set low */
+	immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG);	/* active output */
+	immr->im_ioport.iop_padir |=   CFG_PA_PUMA_PROG;	/* output */
+#endif /* XXX */
+	udelay (100);
+
+#if PCU_E_WITH_SWAPPED_CS	/* XXX */
+	immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG;	/* release reset */
+#else
+	immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG;	/* release reset */
+#endif /* XXX */
+
+	/* wait until INIT indicates completion of reset */
+	for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
+		udelay (1000);
+		if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
+			break;
+	}
+	if (i == PUMA_INIT_TIMEOUT) {
+		printf ("*** PUMA init timeout ***\n");
+		return;
+	}
+
+	puma_set_mode (PUMA_LOAD_MODE);
+
+	while (len--)
+		*fpga_addr = *data++;
+
+	puma_set_mode (PUMA_READ_MODE);
+
+	puma_status ();
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static void puma_status (void)
+{
+	/* Check state */
+	printf ("PUMA initialization is %scomplete\n",
+		puma_init_done ()? "" : "NOT ");
+}
+
+/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
+
+static int puma_init_done (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/* make sure pin is GPIO input */
+	immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
+	immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
+	immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
+
+	return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int misc_init_r (void)
+{
+	ulong addr = 0;
+	ulong len = 0;
+	char *s;
+
+	printf ("PUMA:  ");
+	if (puma_init_done ()) {
+		printf ("initialized\n");
+		return 0;
+	}
+
+	if ((s = getenv ("puma_addr")) != NULL)
+		addr = simple_strtoul (s, NULL, 16);
+
+	if ((s = getenv ("puma_len")) != NULL)
+		len = simple_strtoul (s, NULL, 16);
+
+	if ((!addr) || (!len)) {
+		printf ("net list undefined\n");
+		return 0;
+	}
+
+	printf ("loading... ");
+
+	puma_load (addr, len);
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds
new file mode 100755
index 0000000..6505d45
--- /dev/null
+++ b/board/siemens/pcu_e/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    common/environment.o(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug
new file mode 100755
index 0000000..828afbb
--- /dev/null
+++ b/board/siemens/pcu_e/u-boot.lds.debug
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sixnet/Makefile b/board/sixnet/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/sixnet/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sixnet/config.mk b/board/sixnet/config.mk
new file mode 100755
index 0000000..0cd8f44
--- /dev/null
+++ b/board/sixnet/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# SIXNET boards
+#
+
+TEXT_BASE = 0xF8000000
diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c
new file mode 100755
index 0000000..61d7580
--- /dev/null
+++ b/board/sixnet/flash.c
@@ -0,0 +1,790 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+/* environment.h defines the various CFG_ENV_... values in terms
+ * of whichever ones are given in the configuration file.
+ */
+#include <environment.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t *info);
+#endif
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b;
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b);
+	}
+
+	/* Remap FLASH according to real size, so only at proper address */
+	memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b);
+
+	/* Do this again (was done already in flast_get_size), just
+	 * in case we move it when remap the FLASH.
+	 */
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#ifdef CFG_FLASH_PROTECTION
+	/* read the hardware protection status (if any) into the
+	 * protection array in flash_info.
+	 */
+	flash_sync_real_protect(&flash_info[0]);
+#endif
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_ADDR
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+	return (size_b);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for( i = 0; i < info->sector_count; i++ )
+			info->start[i] = base + (i * sect_size);
+	}
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (top boot sector type) */
+		for (i = 0; i < info->sector_count - 3; i++)
+			info->start[i] = base + (i * sect_size);
+		i = info->sector_count - 1;
+		info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2);
+		info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2);
+		info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2);
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	}
+	else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		fmt = "29LV800B%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf (fmt, bootletter, boottype);
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[0x0555] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[0x02AA] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[0x0555] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
+
+	case (FPW)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MiB	*/
+
+	case (FPW)AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F800C3B:
+		info->flash_id += FLASH_28F800C3B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F800B3B:
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00100000 * (sizeof(FPW)/2);
+		break;				/* => 1 or 2 MB		*/
+
+	case (FPW)INTEL_ID_28F160C3B:
+		info->flash_id += FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F160B3B:
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00200000 * (sizeof(FPW)/2);
+		break;				/* => 2 or 4 MB		*/
+
+	case (FPW)INTEL_ID_28F320C3B:
+		info->flash_id += FLASH_28F320C3B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F320B3B:
+		info->flash_id += FLASH_INTEL320B;
+		info->sector_count = 71;
+		info->size = 0x00400000 * (sizeof(FPW)/2);
+		break;				/* => 4 or 8 MB		*/
+
+	case (FPW)INTEL_ID_28F640C3B:
+		info->flash_id += FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	case (FPW)INTEL_ID_28F640B3B:
+		info->flash_id += FLASH_INTEL640B;
+		info->sector_count = 135;
+		info->size = 0x00800000 * (sizeof(FPW)/2);
+		break;				/* => 8 or 16 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_sync_real_protect(flash_info_t *info)
+{
+    FPWV *addr = (FPWV *)(info->start[0]);
+    FPWV *sect;
+    int i;
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case FLASH_28F800C3B:
+    case FLASH_28F800C3T:
+    case FLASH_28F160C3B:
+    case FLASH_28F160C3T:
+    case FLASH_28F320C3B:
+    case FLASH_28F320C3T:
+    case FLASH_28F640C3B:
+    case FLASH_28F640C3T:
+	/* check for protected sectors */
+	*addr = (FPW)0x00900090;
+	for (i = 0; i < info->sector_count; i++) {
+	    /* read sector protection at sector address, (A7 .. A0) = 0x02.
+	     * D0 = 1 for each device if protected.
+	     * If at least one device is protected the sector is marked
+	     * protected, but mixed protected and  unprotected devices
+	     * within a sector should never happen.
+	     */
+	    sect = (FPWV *)(info->start[i]);
+	    info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+	break;
+
+    case FLASH_AM640U:
+    case FLASH_AM800T:
+    default:
+	/* no hardware protect that we support */
+	break;
+    }
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer(0);
+	last  = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; /* clear status register */
+			*addr = (FPW)0x00200020; /* erase setup */
+			*addr = (FPW)0x00D000D0; /* erase confirm */
+		}
+		else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+
+			base = (FPWV *)(info->start[0]);
+			base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW)0x00550055;	/* unlock */
+			base[0x0555] = (FPW)0x00800080;	/* erase mode */
+			base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay (1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+    int bytes;	  /* number of bytes to program in current word		*/
+    int left;	  /* number of bytes left to program			*/
+    int i, res;
+
+    for (left = cnt, res = 0;
+	 left > 0 && res == 0;
+	 addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+	bytes = addr & (sizeof(data) - 1);
+	addr &= ~(sizeof(data) - 1);
+
+	/* combine source and destination data so can program
+	 * an entire word of 16 or 32 bits
+	 */
+	for (i = 0; i < sizeof(data); i++) {
+	    data <<= 8;
+	    if (i < bytes || i - bytes >= left )
+		data += *((uchar *)addr + i);
+	    else
+		data += *src++;
+	}
+
+	/* write one word to the flash */
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		res = write_word_amd(info, (FPWV *)addr, data);
+		break;
+	case FLASH_MAN_INTEL:
+		res = write_word_intel(info, (FPWV *)addr, data);
+		break;
+	default:
+		/* unknown flash type, error! */
+		printf ("missing or unknown FLASH type\n");
+		res = 1;	/* not really a timeout, but gives error */
+		break;
+	}
+    }
+
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+    FPWV *base;		/* first address in flash bank	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+
+    base = (FPWV *)(info->start[0]);
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+    base[0x02AA] = (FPW)0x00550055;	/* unlock */
+    base[0x0555] = (FPW)0x00A000A0;	/* selects program mode */
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    /* data polling for D7 */
+    while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00F000F0;	/* reset bank */
+	    res = 1;
+	}
+    }
+
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;	/* result, assume success	*/
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+	return (2);
+    }
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+    *dest = (FPW)0x00400040;	/* program setup		*/
+
+    *dest = data;		/* start programming the data	*/
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    *dest = (FPW)0x00B000B0;	/* Suspend program	*/
+	    res = 1;
+	}
+    }
+
+    if (res == 0 && (*dest & (FPW)0x00100010))
+	res = 1;	/* write failed, time out error is close enough	*/
+
+    *dest = (FPW)0x00500050;	/* clear status register	*/
+    *dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+    return (res);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect (flash_info_t * info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset (info);		/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset (info);		/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect (info);
+		break;
+
+	case FLASH_AM640U:
+	case FLASH_AM800T:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
diff --git a/board/sixnet/fpgadata.c b/board/sixnet/fpgadata.c
new file mode 100755
index 0000000..2d3a7b3
--- /dev/null
+++ b/board/sixnet/fpgadata.c
@@ -0,0 +1,1719 @@
+	0xff, 0x87, 0xff, 0x88, 0x7f, 0xff, 0xf9, 0xff,
+	0xff, 0xf5, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0xf9,
+	0xff, 0xef, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xcf,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+	0x7f, 0x7b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x77, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x86, 0xf6, 0xf0, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x0f, 0x7f,
+	0xc1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xf8, 0xff, 0xff, 0xf6, 0xf0, 0xff, 0xff,
+	0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x0f, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0xf8, 0xf7, 0x8f, 0xcf, 0xf0, 0xf6, 0xff,
+	0xff, 0xef, 0xff, 0xfb, 0x7f, 0x2f, 0x1f, 0x71,
+	0xf5, 0xff, 0xff, 0xef, 0x7f,
+	0xff, 0x7f, 0xff, 0xf7, 0xf6, 0xfe, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xf7, 0x7f, 0x77, 0xf7, 0xff, 0xfb,
+	0x0f, 0xff, 0xf0, 0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xfe, 0xff, 0x8f, 0x7f, 0xf1,
+	0xff, 0xff, 0xfa, 0xce, 0xff, 0xfd, 0xff, 0xff,
+	0x9f, 0xff, 0x8e, 0xff, 0xf0, 0xbf, 0x7f, 0xf5,
+	0xff, 0xef, 0x9f, 0xfd, 0x81,
+	0xff, 0xf9, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff,
+	0xff, 0xef, 0x9f, 0xfb, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x7f,
+	0xff, 0x77, 0xfa, 0xb6, 0xff, 0x78, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xbf, 0xfd, 0x0f, 0x7f, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xf6, 0xf7, 0xf6, 0x7f, 0xbf, 0xff, 0xff,
+	0xff, 0xff, 0xef, 0xbf, 0xf2, 0x7f, 0xef, 0xff,
+	0xfe, 0xfb, 0xff, 0xef, 0xff,
+	0xff, 0xf7, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xbf,
+	0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xf7, 0xff, 0xf7, 0xcf, 0x8f, 0xff, 0xf0,
+	0xef, 0xf9, 0xfb, 0xff, 0xff, 0xff, 0x9f, 0x0f,
+	0x65, 0xe1, 0xfb, 0x7b, 0xf3,
+	0xff, 0xf7, 0xf6, 0xfe, 0xff, 0x8f, 0xf6, 0xe8,
+	0xf6, 0xf1, 0xff, 0xff, 0xff, 0xf9, 0xff, 0xff,
+	0x6f, 0x61, 0xf1, 0xfb, 0xff,
+	0xff, 0xde, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+	0xf7, 0xbf, 0xff, 0xd4, 0x8f, 0x0f, 0x71, 0xc1,
+	0x6f, 0xd1, 0xeb, 0x5f, 0xfd,
+	0xff, 0x9f, 0xff, 0xfb, 0xff, 0x8f, 0x9f, 0xf7,
+	0x9f, 0xff, 0xf4, 0xb7, 0xfd, 0xff, 0xfe, 0x8f,
+	0xbf, 0x71, 0x1f, 0xff, 0x7f,
+	0xff, 0xfd, 0x87, 0x87, 0xf0, 0x70, 0x1f, 0xf7,
+	0xbf, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0x81,
+	0xbf, 0x3e, 0x7f, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0xff, 0x07, 0xff, 0xf0, 0xff, 0xff, 0xff,
+	0xfe, 0xff, 0xff, 0xf7, 0x8d, 0x7f, 0xf1, 0xff,
+	0xff, 0x9f, 0x6f, 0xf1, 0xff,
+	0xbf, 0x71, 0x87, 0xfe, 0xf0, 0x8f, 0x8f, 0xf0,
+	0xfb, 0xcb, 0xff, 0xf0, 0x8f, 0x7f, 0xf1, 0x8f,
+	0x1e, 0xe1, 0x7e, 0x91, 0x7f,
+	0xbf, 0x1a, 0xff, 0x71, 0xff, 0x9f, 0x8f, 0xf6,
+	0xf8, 0xdf, 0xf7, 0xf4, 0xff, 0xff, 0xff, 0x8f,
+	0x1f, 0xf0, 0x7f, 0x97, 0xff,
+	0xbf, 0x97, 0xff, 0xfb, 0xbf, 0xdf, 0xff, 0xf7,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0xdf,
+	0xf9, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xdf, 0xff, 0xf1, 0xff,
+	0xff, 0x9f, 0xfc, 0xfb, 0xff, 0xf0, 0xfe, 0xff,
+	0xff, 0xff, 0x9d, 0xff, 0xf4, 0xcf, 0xff, 0x7f,
+	0xf7, 0xff, 0xff, 0xff, 0xcf,
+	0xff, 0x97, 0xff, 0xfa, 0xff, 0x8f, 0xf8, 0xf0,
+	0xff, 0xff, 0xff, 0xdf, 0xff, 0xfd, 0xff, 0x0f,
+	0x7f, 0xe1, 0xff, 0xf1, 0xff,
+	0xff, 0x83, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x6f, 0x7f, 0x77, 0x7d, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x6f, 0xf1,
+	0xff, 0xd7, 0xff, 0xfe, 0xff, 0xff, 0x9f, 0xfd,
+	0x78, 0xef, 0xff, 0xbf, 0xff, 0xf5, 0xff, 0xff,
+	0xbf, 0x0f, 0x79, 0xd1, 0xff,
+	0xff, 0xd2, 0xff, 0x72, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xfe, 0x70, 0x9d, 0xff, 0xf4, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xbf, 0x7f,
+	0xff, 0x07, 0xff, 0x78, 0xff, 0x9f, 0xff, 0xfe,
+	0xff, 0x77, 0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x8f,
+	0x7f, 0xe1, 0x0f, 0x71, 0xf1,
+	0xff, 0xfe, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xfd, 0xff, 0xba, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0xef, 0x7f, 0xa1, 0x7f,
+	0xff, 0xbd, 0x7f, 0xf7, 0xf9, 0xfd, 0xfb, 0xff,
+	0xff, 0x8f, 0xbf, 0xb7, 0x8f, 0xaf, 0xdf, 0xff,
+	0xff, 0xff, 0xff, 0x5f, 0xeb,
+	0xbf, 0xfd, 0xf8, 0xff, 0xff, 0xfb, 0xff, 0xfb,
+	0xff, 0xf7, 0xcf, 0xfb, 0xf0, 0xff, 0xff, 0xdf,
+	0xff, 0xff, 0xef, 0x7f, 0xab,
+	0xff, 0xfd, 0xfa, 0xbf, 0x8f, 0xbf, 0xca, 0xfe,
+	0xff, 0xff, 0xdf, 0x6f, 0xd4, 0xf6, 0x0f, 0x3f,
+	0x11, 0xf9, 0xff, 0x7f, 0x8b,
+	0xbf, 0xff, 0x8f, 0xff, 0xc0, 0xfb, 0xf5, 0xef,
+	0xf7, 0x7f, 0xff, 0xff, 0xfb, 0x7f, 0xff, 0x7f,
+	0xff, 0x6f, 0xff, 0xff, 0xff,
+	0xbf, 0x87, 0xbb, 0xf8, 0xfb, 0xcf, 0xfe, 0xfe,
+	0xff, 0xef, 0xff, 0xfb, 0x7f, 0xff, 0xff, 0x8f,
+	0xff, 0xe1, 0x7f, 0x7b, 0xff,
+	0xbf, 0x80, 0x89, 0x88, 0xb0, 0xf5, 0xf0, 0xff,
+	0xf7, 0xdf, 0xfe, 0x7c, 0x8f, 0x0f, 0x71, 0xe1,
+	0xff, 0xf1, 0xe5, 0x0e, 0x2b,
+	0xff, 0xff, 0xff, 0xbf, 0xff, 0xcf, 0xf5, 0x9f,
+	0xff, 0xff, 0xfe, 0xff, 0x8f, 0x7f, 0x71, 0x8f,
+	0xff, 0x91, 0x7f, 0xfb, 0xff,
+	0xff, 0x7f, 0x7f, 0xcf, 0x8a, 0xff, 0xf0, 0xff,
+	0x57, 0xfe, 0xfb, 0x8f, 0xff, 0xf0, 0xff, 0x7e,
+	0xff, 0xff, 0x9a, 0xff, 0xf1,
+	0xff, 0xff, 0xcf, 0xb7, 0xce, 0xff, 0xf4, 0xff,
+	0xff, 0x7f, 0xf7, 0xfb, 0xff, 0xfe, 0xff, 0x7f,
+	0xff, 0xfd, 0xfe, 0x75, 0xfd,
+	0xff, 0xef, 0xcf, 0xff, 0xf5, 0xff, 0xf5, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff,
+	0xcf, 0x7f, 0x31, 0x7f, 0xff,
+	0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x0f, 0x0f, 0xf1, 0xf1, 0xdf, 0xff, 0xff,
+	0xff, 0x9f, 0xff, 0x84, 0x0e,
+	0xff, 0xf8, 0x7f, 0xf7, 0x7f, 0xff, 0xff, 0x8f,
+	0x8f, 0x80, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xfe, 0x9f, 0x8e, 0x05, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+	0xfe, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xf7, 0xff, 0xff, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x9f, 0xff, 0x8f, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0xff, 0x8f,
+	0xff, 0x87, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x7f, 0xf1,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x8f,
+	0xff, 0xf0, 0x0f, 0xff, 0x70, 0xff, 0x8f, 0x7e,
+	0xf1, 0xdf, 0xff, 0xfb, 0x8e,
+	0xff, 0x80, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xaf, 0x7f, 0x84, 0xff, 0xf1, 0xff, 0xfe,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xdf, 0xdf, 0xff, 0xdf, 0xff,
+	0xff, 0xff, 0x8f, 0x7f, 0xf1,
+	0xff, 0xfd, 0xff, 0xff, 0xff, 0x0f, 0xff, 0x80,
+	0xff, 0xf0, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0x8e,
+	0x0f, 0x01, 0x71, 0xf1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0x8f, 0x8f, 0xd0, 0xf0, 0xdf, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd,
+	0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xfe,
+	0xff, 0xdf, 0xff, 0xfb, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfd,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xaf, 0xfe, 0xf5, 0xff, 0xff,
+	0xff, 0xff, 0x0f, 0x8f, 0xf0, 0x80, 0xff, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0x1f, 0xaf, 0x71, 0xa7,
+	0x6f, 0xf5, 0xfe, 0xff, 0xff,
+	0xff, 0x77, 0x79, 0x8f, 0xff, 0xf0, 0x8f, 0xff,
+	0x00, 0xff, 0xd0, 0x4f, 0x3d, 0xf0, 0xf7, 0xfd,
+	0x8f, 0x7f, 0x81, 0x7f, 0xd1,
+	0xff, 0xcd, 0xff, 0xff, 0x8f, 0x0f, 0x70, 0xf0,
+	0xff, 0x7f, 0x7f, 0xff, 0xff, 0xdb, 0x8d, 0x4b,
+	0x73, 0xf9, 0xff, 0xdf, 0xff,
+	0x3f, 0xfc, 0xff, 0x8f, 0xff, 0xf2, 0x8f, 0x8f,
+	0x70, 0x7a, 0x3f, 0xbc, 0xf7, 0xdb, 0xff, 0xf9,
+	0xff, 0xff, 0xff, 0xff, 0xee,
+	0xff, 0xe8, 0xf7, 0x8f, 0xfd, 0x80, 0xff, 0xf0,
+	0x9f, 0xa5, 0x7a, 0xf4, 0x6f, 0x3f, 0xcf, 0x07,
+	0x6a, 0xe1, 0xff, 0x8f, 0x7f,
+	0xff, 0xff, 0x77, 0xf1, 0x8f, 0x8f, 0xf0, 0xf0,
+	0xbf, 0xff, 0xe7, 0x7f, 0x8f, 0x24, 0x03, 0x77,
+	0xf3, 0xff, 0xfe, 0xff, 0xff,
+	0xbf, 0x9f, 0x77, 0x8b, 0xff, 0xf0, 0xff, 0xef,
+	0x7d, 0x7f, 0xff, 0x9f, 0xeb, 0x3d, 0xff, 0xf7,
+	0xff, 0xfb, 0xfe, 0xff, 0xdf,
+	0xff, 0xff, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbb, 0x5d,
+	0xf5, 0xbb, 0xef, 0xff, 0xff,
+	0xff, 0x7f, 0x8f, 0x8f, 0xf0, 0xf8, 0xff, 0xff,
+	0xf7, 0x7f, 0xff, 0xff, 0xaf, 0xbf, 0x75, 0xb7,
+	0xff, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0x87, 0x7f, 0xf8, 0xff, 0xf7, 0xf7,
+	0x8f, 0xff, 0xf0, 0x7f, 0xf7, 0xff, 0xad, 0xff,
+	0xf7, 0xee, 0x9f, 0xff, 0xf5,
+	0xff, 0xf8, 0x07, 0xff, 0x80, 0x8f, 0x80, 0x80,
+	0xf0, 0x8f, 0x7f, 0x70, 0x4f, 0x0f, 0x79, 0xf1,
+	0xfd, 0xff, 0xef, 0x8f, 0x7f,
+	0xbf, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xd0, 0xbf, 0xdb, 0xe5,
+	0x3b, 0xfe, 0xf7, 0xff, 0x8f,
+	0xff, 0xff, 0x8f, 0x77, 0x80, 0xff, 0xf0, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xbd, 0xef, 0x07, 0x7f,
+	0xf1, 0xfe, 0xff, 0xfe, 0xff,
+	0x7f, 0x7f, 0xff, 0xf7, 0xf7, 0xff, 0xf7, 0x8f,
+	0xbf, 0x70, 0xf5, 0x7f, 0xff, 0xef, 0x3f, 0x7d,
+	0xf7, 0xff, 0xff, 0xfe, 0xfe,
+	0xff, 0x97, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
+	0x7e, 0xff, 0xff, 0x9f, 0xdf, 0xf7, 0x3b, 0xff,
+	0xf7, 0xff, 0x7f, 0xfe, 0xff,
+	0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x1f, 0x1f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x80, 0x0e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
+	0x9f, 0x80, 0xe1, 0xf1, 0xff, 0xff, 0xef, 0xff,
+	0xfe, 0x9f, 0x0e, 0x01, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xef,
+	0xfe, 0xef, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x9f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xef, 0xff, 0xff, 0xef, 0xfe, 0xef,
+	0xef, 0xff, 0xff, 0xef, 0xff,
+	0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xe0, 0xff, 0xff,
+	0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xef, 0xff, 0xff,
+	0xff, 0xff, 0xee, 0xef, 0x9f,
+	0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xe0, 0xff, 0xff,
+	0xff, 0xef, 0x8e, 0x7f, 0xf1,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xef, 0xff, 0xfe, 0x8f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xdf,
+	0xff, 0xf0, 0x0f, 0xff, 0x70, 0xff, 0x8f, 0x7e,
+	0xe1, 0xdf, 0xff, 0xf7, 0x8e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xef, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0x7f, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0x1f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x7e, 0xf1,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0x0f, 0x8f, 0x80,
+	0xf7, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9e,
+	0x6f, 0x91, 0x71, 0xf1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xef, 0xff, 0xff,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xdf, 0x8f,
+	0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
+	0xff, 0xef, 0xff, 0xd7, 0xff,
+	0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0x8f, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
+	0xff, 0xfe, 0xf9, 0xdf, 0xff,
+	0xff, 0xff, 0x8f, 0xbf, 0xf7, 0x9f, 0xf8, 0xf0,
+	0xff, 0xff, 0x77, 0xff, 0x0e, 0x1f, 0x61, 0x81,
+	0x7f, 0xf1, 0xfe, 0xff, 0xff,
+	0xff, 0x7f, 0xb9, 0xcf, 0xff, 0xff, 0x0f, 0xff,
+	0x00, 0xff, 0xd0, 0x7f, 0x75, 0x8b, 0x7f, 0xf1,
+	0x8f, 0x7f, 0x80, 0x7e, 0x91,
+	0xff, 0xbf, 0xdf, 0xff, 0xa7, 0x47, 0x70, 0xf7,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0x0f,
+	0x61, 0xf1, 0xef, 0xff, 0xff,
+	0x7f, 0xfe, 0xef, 0x5f, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xe7, 0xb7, 0xfc, 0xeb, 0x9f, 0x7f, 0xf1,
+	0x9f, 0x0f, 0x71, 0xf1, 0xee,
+	0xff, 0xf0, 0xf7, 0x3f, 0xef, 0x97, 0xf8, 0xe8,
+	0xff, 0x9f, 0x7f, 0xf0, 0x7f, 0x9f, 0x6f, 0x91,
+	0x7e, 0xf1, 0x9f, 0x8f, 0x57,
+	0xff, 0xff, 0x26, 0xb9, 0xb8, 0xff, 0xf0, 0xff,
+	0xff, 0xff, 0xf7, 0x7f, 0x6f, 0xf4, 0x9f, 0x1f,
+	0x71, 0xe1, 0xfe, 0x7f, 0xff,
+	0xbf, 0xff, 0x71, 0xbb, 0xe8, 0xff, 0xff, 0xf8,
+	0xbf, 0xff, 0xaf, 0xff, 0xf8, 0x9d, 0x6f, 0xf1,
+	0xbf, 0xff, 0xb7, 0xff, 0xbd,
+	0xbf, 0xff, 0xff, 0xdf, 0x97, 0xc7, 0xf7, 0xf0,
+	0xff, 0xff, 0x93, 0xff, 0xff, 0xef, 0xcf, 0x5f,
+	0xf1, 0xf7, 0xdf, 0xf5, 0x9f,
+	0xff, 0xff, 0x87, 0xbf, 0xe0, 0xbf, 0xf7, 0xff,
+	0xf7, 0x7f, 0xff, 0xff, 0x8f, 0x5f, 0x21, 0xb1,
+	0xff, 0x6d, 0xff, 0xef, 0xff,
+	0xff, 0xff, 0xd7, 0xff, 0xb8, 0xff, 0xff, 0xff,
+	0x3f, 0xef, 0xf0, 0x7f, 0xd7, 0x7f, 0xf1, 0xff,
+	0xef, 0xee, 0xbf, 0x7f, 0xf1,
+	0xff, 0xf8, 0x47, 0x0f, 0xc7, 0xf0, 0x7f, 0xf0,
+	0xf0, 0x90, 0x7f, 0x70, 0x8f, 0x2f, 0xc1, 0x0f,
+	0x11, 0x1f, 0xef, 0xaf, 0x7f,
+	0xbf, 0x7f, 0xf0, 0x9f, 0xe7, 0xf7, 0x38, 0xff,
+	0xff, 0xff, 0x8f, 0x7f, 0xf0, 0xaf, 0xff, 0xff,
+	0xbf, 0xfe, 0xfd, 0xdf, 0x8f,
+	0xff, 0xff, 0xbf, 0xf7, 0x8f, 0xff, 0xf7, 0xff,
+	0xeb, 0xff, 0xff, 0xff, 0x8d, 0x3f, 0x81, 0x7f,
+	0xd1, 0xfe, 0xdf, 0xfe, 0xff,
+	0x7f, 0xff, 0xff, 0xdf, 0xa8, 0xff, 0xf0, 0xff,
+	0xff, 0xf0, 0xf7, 0xff, 0xff, 0xff, 0xef, 0xef,
+	0xef, 0x9f, 0x7f, 0x7e, 0xfe,
+	0xff, 0xff, 0xef, 0xff, 0xa7, 0x77, 0xff, 0xff,
+	0xef, 0xff, 0xff, 0xdf, 0xff, 0xe7, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xfe, 0xff,
+	0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xbf,
+	0xff, 0x0f, 0x0f, 0xf1, 0xe1, 0xff, 0xff, 0xef,
+	0xef, 0xff, 0xff, 0x8e, 0x0e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
+	0x8f, 0x80, 0xf1, 0xf1, 0xef, 0xaf, 0xaf, 0xff,
+	0xee, 0xdf, 0x0e, 0x01, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0xef, 0x8f, 0x9f, 0xf1, 0xe1, 0xff, 0xaf, 0xef,
+	0xfe, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x9f, 0x9f, 0xf1, 0xf1, 0xef, 0xff, 0xaf, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xef, 0xbf, 0xef, 0xff,
+	0xef, 0xbf, 0xff, 0xef, 0xff,
+	0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xfe,
+	0xcf, 0x3f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf,
+	0xff, 0x88, 0xff, 0xf0, 0xff, 0xff, 0xef, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x6e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xe0, 0xff, 0xef, 0xff,
+	0xff, 0xff, 0xee, 0xef, 0x9f,
+	0xff, 0x8f, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xa0, 0xff, 0xfe,
+	0xff, 0xbf, 0x8e, 0x6f, 0xf1,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x6f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xcf,
+	0xff, 0xb0, 0x0f, 0xaf, 0x70, 0xff, 0x8f, 0x7e,
+	0xf1, 0xff, 0xff, 0xf1, 0x9e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xef, 0x8f, 0x7f, 0x90, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xaf, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x3f, 0xdf, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x9f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xbf, 0x7e, 0xf1,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0x0f, 0xaf, 0x80,
+	0xf0, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xde,
+	0x0f, 0x91, 0x7f, 0xf1, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xfe,
+	0xff, 0xff, 0xbf, 0xff, 0xfb,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xdf, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xdf, 0xbf, 0xff, 0xef, 0xff,
+	0xff, 0xaf, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xdf, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xaf, 0xff,
+	0xf0, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff,
+	0xdf, 0xfe, 0xfe, 0xff, 0xff,
+	0xff, 0xff, 0x0f, 0x8f, 0xf0, 0x8f, 0xff, 0xf0,
+	0xf9, 0xff, 0xf7, 0xff, 0x0f, 0x5f, 0x29, 0x89,
+	0x77, 0xf1, 0xfa, 0xff, 0xde,
+	0xff, 0xc3, 0x3f, 0x4b, 0x7f, 0xe9, 0x0f, 0xff,
+	0x00, 0xff, 0x90, 0x0f, 0xd7, 0xff, 0x7f, 0xf9,
+	0x8f, 0x7f, 0x81, 0x7f, 0x81,
+	0xff, 0xff, 0xfb, 0x7d, 0x80, 0x46, 0x76, 0xf0,
+	0xff, 0xff, 0x6f, 0xff, 0xff, 0xad, 0xcf, 0x3f,
+	0x71, 0xf9, 0xff, 0xff, 0xff,
+	0x3f, 0xba, 0xff, 0xc7, 0xf7, 0xb9, 0xcf, 0xde,
+	0x77, 0xb7, 0x77, 0xfe, 0xff, 0xbf, 0x6f, 0xf9,
+	0xff, 0x7e, 0x79, 0xb9, 0xfe,
+	0xff, 0xe4, 0xf7, 0x8f, 0xfe, 0x07, 0xfe, 0xf8,
+	0xff, 0x89, 0x7f, 0xe8, 0x7f, 0xd7, 0x7f, 0x99,
+	0x76, 0xf1, 0xff, 0x0f, 0x7b,
+	0xbf, 0xff, 0xb6, 0xb9, 0x8f, 0xdf, 0xf6, 0xff,
+	0xff, 0xf7, 0xff, 0xff, 0x8f, 0xdd, 0x87, 0x7f,
+	0x71, 0xf1, 0xfe, 0xff, 0xff,
+	0xff, 0x7f, 0xf1, 0x8a, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0xff, 0xcf, 0xfb, 0xe8, 0x9d, 0x77, 0xa9,
+	0xff, 0x77, 0xda, 0x7f, 0xff,
+	0xbf, 0xff, 0xf7, 0xf7, 0x86, 0xe5, 0xf0, 0xe0,
+	0xff, 0xff, 0xbf, 0xff, 0xff, 0xef, 0x8f, 0x7f,
+	0xbd, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xef, 0x86, 0x8f, 0xf0, 0xff, 0xf6, 0x9f,
+	0xff, 0x7f, 0xff, 0xff, 0xcf, 0x1f, 0x71, 0xdd,
+	0x7f, 0xe1, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xc7, 0xf7, 0xb9, 0xff, 0xff, 0xfa,
+	0x3f, 0xef, 0xf0, 0xff, 0xef, 0x7f, 0xd5, 0xff,
+	0xfb, 0xff, 0xf7, 0x6e, 0xf1,
+	0xff, 0xfc, 0xc7, 0xbf, 0xc8, 0xc0, 0x59, 0xff,
+	0xdf, 0xff, 0x7b, 0xf0, 0xa7, 0x1f, 0xa9, 0x77,
+	0x79, 0x71, 0x11, 0xff, 0x79,
+	0xbf, 0xfb, 0x70, 0xbf, 0xff, 0xf9, 0x37, 0xbe,
+	0xff, 0xff, 0x8f, 0x7f, 0xf4, 0x9f, 0xff, 0xff,
+	0xd7, 0x7f, 0xff, 0xff, 0xaf,
+	0xff, 0xff, 0x9e, 0xf7, 0x9f, 0xfe, 0xe4, 0xff,
+	0xcf, 0xcf, 0xff, 0xff, 0xdf, 0x7f, 0x8d, 0x7f,
+	0xf9, 0xfa, 0xdf, 0x9f, 0xef,
+	0x7f, 0xef, 0xff, 0xff, 0xbe, 0xfd, 0xd2, 0xdf,
+	0xff, 0x7e, 0xf7, 0xff, 0xff, 0xab, 0x97, 0xef,
+	0xf3, 0xfe, 0x7f, 0x71, 0xfe,
+	0xff, 0x9f, 0xff, 0xff, 0xb6, 0xfb, 0xf7, 0xff,
+	0xff, 0xf7, 0xff, 0xbf, 0xff, 0xb7, 0xdb, 0xff,
+	0xbb, 0xef, 0xff, 0xff, 0xff,
+	0x3f, 0x68, 0xfe, 0xfd, 0xfb, 0xff, 0xff, 0xef,
+	0xf1, 0x1e, 0x1b, 0xf1, 0xf5, 0xff, 0xff, 0xff,
+	0xff, 0x9f, 0xfb, 0x9a, 0x36,
+	0xff, 0xfc, 0x7d, 0xff, 0x73, 0xf7, 0xff, 0xaf,
+	0x9f, 0x94, 0xfd, 0xf5, 0xff, 0xf7, 0xff, 0xfb,
+	0xfe, 0xef, 0x3e, 0x07, 0x4d,
+	0xbf, 0xe8, 0xf8, 0xff, 0x7f, 0xff, 0xf7, 0xf7,
+	0xf1, 0x8f, 0xaf, 0xd1, 0xf7, 0xf9, 0xfd, 0xff,
+	0xf8, 0xdf, 0xfb, 0x8f, 0x2f,
+	0xff, 0xf8, 0x7f, 0xff, 0xf7, 0xf7, 0xff, 0xff,
+	0xa7, 0xaf, 0xf7, 0xf3, 0xdf, 0xff, 0xfd, 0xff,
+	0xfd, 0xff, 0xae, 0x0f, 0x71,
+	0xff, 0xff, 0xff, 0xf9, 0xff, 0xff, 0xf3, 0xf3,
+	0xff, 0xf3, 0xff, 0xf7, 0xfb, 0xf3, 0xff, 0xff,
+	0xff, 0xeb, 0xff, 0xf3, 0xdb,
+	0xff, 0xeb, 0x7b, 0xfb, 0xf7, 0xff, 0x8b, 0xf7,
+	0xfc, 0xf7, 0xfb, 0xff, 0xfb, 0xf3, 0xff, 0xff,
+	0x8b, 0x7f, 0xd4, 0xfb, 0xff,
+	0x7f, 0xec, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xf7,
+	0xff, 0x8e, 0xff, 0xf8, 0xf7, 0xfb, 0xfd, 0xff,
+	0xfd, 0x9f, 0xf7, 0x9f, 0x7e,
+	0xbf, 0xfb, 0x7c, 0xff, 0xf7, 0xff, 0xff, 0xfb,
+	0xfb, 0xf1, 0x8f, 0xf3, 0xdc, 0xf7, 0xfd, 0xff,
+	0xe9, 0xeb, 0xef, 0xc3, 0xb7,
+	0xff, 0x07, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xf7,
+	0x8f, 0xff, 0xf4, 0x8f, 0xfb, 0xfc, 0xff, 0xef,
+	0xff, 0xf7, 0x8f, 0x7f, 0xd1,
+	0xff, 0xfa, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff,
+	0xf3, 0x89, 0xef, 0xf8, 0xff, 0xf7, 0xff, 0xef,
+	0xef, 0xf7, 0xf3, 0xab, 0x7f,
+	0x3f, 0xf9, 0x7e, 0xf9, 0x8f, 0x7f, 0xf0, 0xef,
+	0xff, 0xfc, 0x1b, 0xff, 0x7c, 0xff, 0x8f, 0x6e,
+	0xf1, 0xf7, 0x73, 0xff, 0xa6,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xf9, 0x8f, 0x7f, 0x84, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xfa, 0x8f, 0x7f,
+	0xff, 0x96, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff,
+	0x57, 0xaf, 0xfb, 0x85, 0x7f, 0xf4, 0xff, 0xfe,
+	0xef, 0xff, 0xef, 0xbf, 0x53,
+	0xff, 0x7d, 0xff, 0xff, 0xe3, 0xff, 0xff, 0xff,
+	0x97, 0x71, 0xf8, 0xff, 0xff, 0xff, 0xdb, 0xef,
+	0xef, 0xe7, 0x97, 0x72, 0xfd,
+	0xff, 0xff, 0xff, 0xff, 0xf3, 0x0f, 0xe3, 0x86,
+	0xf0, 0xf4, 0xfb, 0xff, 0xdf, 0xff, 0xfb, 0x8e,
+	0x0b, 0xa5, 0x72, 0xf9, 0xff,
+	0xff, 0xfb, 0xff, 0xff, 0xf7, 0xff, 0xf3, 0xff,
+	0xf7, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xfb, 0xee,
+	0xfb, 0xff, 0xef, 0xff, 0xff,
+	0xbf, 0x82, 0xf8, 0xf8, 0xf7, 0x7f, 0xf7, 0xff,
+	0xff, 0xef, 0x87, 0x87, 0xf0, 0xf0, 0xfb, 0xff,
+	0xfb, 0xf7, 0xef, 0xef, 0x87,
+	0xff, 0xf6, 0xff, 0xfa, 0xf1, 0xef, 0xf3, 0xf7,
+	0x7f, 0xff, 0xff, 0xef, 0xff, 0xf7, 0xff, 0xff,
+	0xfb, 0xf7, 0xff, 0xfe, 0xff,
+	0xff, 0xf7, 0xfb, 0xf2, 0xf3, 0xff, 0xf1, 0xf7,
+	0xff, 0xef, 0xf7, 0xef, 0xf7, 0xf7, 0xff, 0xfe,
+	0xff, 0xff, 0xef, 0xff, 0xe7,
+	0xff, 0xfb, 0xfb, 0xff, 0xf5, 0xef, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0x77, 0xff, 0xff, 0xfe,
+	0xff, 0xf7, 0xff, 0xef, 0xef,
+	0xff, 0xff, 0xff, 0xff, 0xf7, 0xef, 0xe5, 0xff,
+	0xfe, 0x61, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x9f, 0xef, 0xef, 0xf3, 0xf7,
+	0xff, 0xff, 0x0f, 0x9f, 0xfa, 0x87, 0xff, 0xf6,
+	0xeb, 0xff, 0xff, 0xef, 0x0f, 0x6f, 0xfd, 0x0d,
+	0x53, 0xf1, 0xf3, 0xff, 0xff,
+	0xbf, 0x1b, 0x7f, 0x96, 0xfe, 0xff, 0x8f, 0xfb,
+	0x00, 0xff, 0xb0, 0x17, 0x7c, 0x8f, 0xff, 0xfd,
+	0x8f, 0x7f, 0x81, 0x7e, 0xf1,
+	0xff, 0xfd, 0xed, 0xee, 0x9e, 0x0b, 0x79, 0xff,
+	0xfb, 0x77, 0x5b, 0xff, 0x9f, 0xff, 0x4f, 0x0f,
+	0x71, 0xf0, 0xdb, 0xff, 0xf7,
+	0x7f, 0xe7, 0xef, 0x18, 0xff, 0xff, 0x9d, 0x8e,
+	0x67, 0xbf, 0x4f, 0xff, 0xff, 0xae, 0xff, 0xf1,
+	0xeb, 0xef, 0xfd, 0xad, 0xf6,
+	0xff, 0xfc, 0xf7, 0x1f, 0xff, 0x9f, 0xfb, 0xfc,
+	0xff, 0x8f, 0x77, 0xec, 0x5f, 0x6f, 0xdf, 0x25,
+	0x7e, 0xd9, 0xe6, 0x97, 0x3f,
+	0xff, 0xf7, 0x67, 0xec, 0x92, 0xbe, 0xf1, 0xfb,
+	0xff, 0x7f, 0xdf, 0x7b, 0x5e, 0x7d, 0xe7, 0x5f,
+	0xf1, 0xf1, 0xfb, 0xff, 0xf7,
+	0xbf, 0xf7, 0x71, 0x9a, 0xfd, 0xff, 0xf7, 0xfb,
+	0x5f, 0x7f, 0xaf, 0xdf, 0xf9, 0xe7, 0x77, 0xdd,
+	0x6f, 0xf7, 0xbb, 0xff, 0x8b,
+	0xbf, 0xff, 0x77, 0xff, 0x93, 0xfe, 0xf8, 0xfe,
+	0xbf, 0xfe, 0xbf, 0xff, 0xff, 0xbf, 0xab, 0x7f,
+	0xfd, 0xff, 0xcf, 0x67, 0xff,
+	0xff, 0x7f, 0x07, 0x9f, 0xe4, 0xdb, 0xff, 0xf1,
+	0xf7, 0x7f, 0xff, 0xff, 0x8f, 0x6f, 0xd1, 0x6d,
+	0x73, 0xff, 0xff, 0xfb, 0xff,
+	0xff, 0x6f, 0x9f, 0x7b, 0xfd, 0xff, 0xf6, 0xfd,
+	0x27, 0xff, 0xfc, 0xff, 0xaf, 0xff, 0xfd, 0xfe,
+	0x7f, 0xdf, 0xff, 0x7f, 0xef,
+	0xff, 0xfe, 0x81, 0xe7, 0x93, 0x91, 0x83, 0x85,
+	0xef, 0x8f, 0x7f, 0x74, 0x8d, 0x1b, 0x2d, 0xe2,
+	0xcd, 0xe5, 0xb5, 0x9f, 0x77,
+	0xbf, 0x7f, 0xe4, 0xef, 0xff, 0xf7, 0xdb, 0xfd,
+	0x7f, 0xfe, 0xab, 0x7f, 0xfc, 0xbf, 0xff, 0xde,
+	0x77, 0xfb, 0xdf, 0xef, 0xbf,
+	0xff, 0xff, 0x1e, 0x7f, 0x8f, 0xff, 0x92, 0xf3,
+	0xdf, 0x7b, 0xff, 0x7b, 0xff, 0xdb, 0x3d, 0x5f,
+	0xf9, 0xf6, 0xff, 0xf2, 0xf7,
+	0x7f, 0x7f, 0xff, 0xff, 0xef, 0xd2, 0xf0, 0xb7,
+	0xfb, 0x7f, 0xfc, 0x77, 0xd7, 0x3f, 0xc7, 0x7f,
+	0xf3, 0xe7, 0xff, 0xfd, 0xfe,
+	0xff, 0xff, 0xef, 0x7b, 0xef, 0xf5, 0xda, 0xff,
+	0x7c, 0xff, 0xff, 0xff, 0xff, 0x7b, 0xeb, 0xfb,
+	0xef, 0xff, 0xef, 0xff, 0xff,
+	0x3f, 0x60, 0xfc, 0xfb, 0xf7, 0xff, 0xff, 0xff,
+	0xfb, 0x00, 0x0f, 0xf1, 0xf5, 0xfb, 0xff, 0xff,
+	0xff, 0xff, 0xf3, 0x86, 0x3e,
+	0xff, 0xf8, 0x7f, 0xfb, 0x73, 0xff, 0xff, 0x9f,
+	0xab, 0x8c, 0xf5, 0xd1, 0xff, 0xfb, 0xff, 0xff,
+	0xfe, 0xeb, 0x36, 0x0d, 0x49,
+	0xbf, 0xf0, 0xfc, 0xfb, 0x73, 0xff, 0xf3, 0xff,
+	0xff, 0xab, 0xa7, 0xf1, 0xf9, 0xff, 0xf7, 0xdf,
+	0xfa, 0xfb, 0xff, 0xa7, 0x3f,
+	0xff, 0xf8, 0x7f, 0xff, 0xfb, 0xfb, 0xfb, 0xff,
+	0xaf, 0x8f, 0xf9, 0xf9, 0xdf, 0xdf, 0xf7, 0xdb,
+	0xff, 0xff, 0xba, 0x2f, 0x69,
+	0xff, 0xe7, 0xfb, 0xfb, 0xff, 0xff, 0xff, 0xfb,
+	0xff, 0xfb, 0xd7, 0xff, 0xdf, 0xf7, 0xd7, 0xdf,
+	0xf3, 0xdb, 0xff, 0xdb, 0xff,
+	0xff, 0xe3, 0x7b, 0xf9, 0xfb, 0xff, 0x8f, 0xfb,
+	0xf8, 0xff, 0xff, 0xef, 0xdf, 0xf3, 0xd7, 0xdf,
+	0xa3, 0x5b, 0xc4, 0xfb, 0xef,
+	0x7f, 0xe0, 0xfd, 0xfb, 0xfb, 0xff, 0xfb, 0xeb,
+	0xff, 0x8c, 0xeb, 0xf0, 0xd3, 0xff, 0xd7, 0xff,
+	0xf7, 0xbb, 0x7f, 0x8f, 0x7e,
+	0xbf, 0xfb, 0x6c, 0xfb, 0xfb, 0xff, 0xfb, 0xff,
+	0xfb, 0xf3, 0x8b, 0xf3, 0xf4, 0xf7, 0xd7, 0xff,
+	0xf3, 0xff, 0xfe, 0xc2, 0xbf,
+	0xff, 0x87, 0x7f, 0xfa, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf4, 0xff, 0xdf,
+	0xff, 0xfb, 0x8f, 0x7f, 0xc5,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb,
+	0xf3, 0x87, 0xef, 0xfc, 0xfd, 0xfb, 0xff, 0xff,
+	0xdf, 0xff, 0xfb, 0xab, 0x7f,
+	0x3f, 0xf3, 0xfa, 0xf9, 0x8f, 0x7f, 0xf0, 0xeb,
+	0xfb, 0xec, 0x1f, 0xcf, 0x7e, 0xff, 0x8f, 0x5e,
+	0xd1, 0xbf, 0xff, 0xfe, 0xaa,
+	0xff, 0x80, 0x7d, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xf7, 0x8f, 0x5f, 0x8c, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xfa, 0x9f, 0x6f,
+	0xff, 0x9a, 0xfd, 0xfc, 0xff, 0xff, 0xff, 0xff,
+	0x6f, 0xbf, 0xd7, 0x89, 0x7f, 0xf4, 0xff, 0xfe,
+	0xff, 0xff, 0xdf, 0xbf, 0x6f,
+	0xff, 0xfd, 0xff, 0xff, 0xef, 0xff, 0xfb, 0xff,
+	0x2b, 0x73, 0xf0, 0xf3, 0xff, 0xff, 0xc3, 0xff,
+	0xff, 0xff, 0x8b, 0x62, 0xfd,
+	0xff, 0xef, 0xff, 0xff, 0xfb, 0x0f, 0x8b, 0x8e,
+	0xf0, 0xdc, 0xf7, 0xff, 0xff, 0xff, 0xfb, 0xae,
+	0x43, 0xa9, 0x73, 0xf9, 0xfb,
+	0x7f, 0xf9, 0xff, 0xff, 0xfd, 0xff, 0xf9, 0xff,
+	0xfb, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xf3, 0xfe,
+	0xf3, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0x87, 0xf8, 0xf8, 0xf9, 0x7f, 0xf9, 0xff,
+	0xff, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, 0xf3, 0xff,
+	0xf3, 0xfb, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff,
+	0xfb, 0xef, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xf7, 0xf9, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xfe,
+	0xf3, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xf1, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xfe,
+	0xfb, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xf1, 0xff, 0x85, 0xff,
+	0xfe, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff,
+	0xf3, 0xde, 0xff, 0xf3, 0xff,
+	0xbf, 0xff, 0x0f, 0x9f, 0xfa, 0x9f, 0xeb, 0xf2,
+	0xe7, 0xff, 0x7b, 0xff, 0x4f, 0x73, 0x31, 0x81,
+	0x5f, 0xf1, 0xfe, 0xff, 0xbf,
+	0xff, 0xaf, 0x7f, 0x94, 0xfb, 0xfe, 0x8f, 0xff,
+	0x00, 0xff, 0xf0, 0xef, 0xef, 0x5f, 0xfb, 0xf5,
+	0x8f, 0x7f, 0x81, 0x5e, 0xf1,
+	0xff, 0xf9, 0xff, 0xef, 0x86, 0x0f, 0x71, 0xf6,
+	0xff, 0x7f, 0x7f, 0x97, 0xcf, 0xfd, 0xbf, 0x5f,
+	0xf9, 0xf1, 0xf3, 0xff, 0xff,
+	0x3f, 0xdb, 0xed, 0x1e, 0xff, 0xf6, 0x95, 0x9a,
+	0x6f, 0x3d, 0xff, 0xf8, 0xfb, 0xdf, 0xf7, 0xfd,
+	0xfb, 0xf7, 0xfd, 0xed, 0xde,
+	0x7f, 0xf0, 0xf7, 0x87, 0x7f, 0x9b, 0xff, 0xec,
+	0x9f, 0xbf, 0x7f, 0xcd, 0x7f, 0xf7, 0x3b, 0xad,
+	0x7e, 0xf8, 0xff, 0xbb, 0x79,
+	0xff, 0xff, 0xe3, 0x7c, 0x01, 0x8d, 0xf5, 0xfb,
+	0xe7, 0xf7, 0xff, 0xff, 0x9e, 0x7d, 0x0f, 0x7f,
+	0xf1, 0xcd, 0xfe, 0xf7, 0xff,
+	0x3f, 0xd7, 0xf4, 0x9a, 0xf7, 0xed, 0xff, 0xf3,
+	0xb7, 0xff, 0xef, 0xff, 0xbd, 0xe7, 0x5f, 0xbd,
+	0xff, 0xef, 0xfe, 0x7f, 0xf1,
+	0x3f, 0xff, 0xe7, 0xff, 0xcf, 0xfa, 0xf8, 0xff,
+	0xff, 0xdf, 0xbf, 0xfe, 0xdf, 0xff, 0xd3, 0x1f,
+	0xfd, 0xef, 0x7f, 0xff, 0xcf,
+	0x7f, 0xff, 0x93, 0xdf, 0xf0, 0xef, 0xf3, 0xd4,
+	0x77, 0x6f, 0xff, 0xff, 0xbf, 0x7f, 0x7d, 0xfd,
+	0x7f, 0x7d, 0xff, 0xff, 0xf7,
+	0xff, 0xf7, 0xdf, 0xfb, 0xbc, 0xef, 0xff, 0xfd,
+	0xff, 0xff, 0xfc, 0x7f, 0xb7, 0xff, 0xfd, 0x5f,
+	0xcf, 0xff, 0xef, 0x7f, 0xfd,
+	0xff, 0xee, 0x87, 0xef, 0x92, 0xf0, 0x7e, 0xe5,
+	0xbf, 0x8f, 0x7f, 0x60, 0xd9, 0xdb, 0x71, 0xb3,
+	0x2d, 0x49, 0x6c, 0x29, 0x7f,
+	0xbf, 0xff, 0xe4, 0x6f, 0xf3, 0xfa, 0x57, 0xfd,
+	0xff, 0xfe, 0xb7, 0x7f, 0xfc, 0xff, 0x73, 0xdf,
+	0xf3, 0x7f, 0xfd, 0xff, 0xbf,
+	0xff, 0xef, 0x8b, 0x7f, 0x8f, 0xff, 0xf2, 0xff,
+	0xff, 0xf7, 0xfb, 0xff, 0xff, 0xdf, 0xed, 0xef,
+	0xf1, 0xf7, 0xfd, 0xdf, 0xf7,
+	0xff, 0xff, 0xff, 0xf7, 0xe7, 0xe6, 0xf1, 0xff,
+	0xdf, 0xfb, 0xe9, 0xfe, 0xbf, 0xff, 0xbf, 0x5f,
+	0xff, 0xbf, 0x0e, 0x75, 0xfa,
+	0xff, 0xff, 0xff, 0x6f, 0xfb, 0xf9, 0xff, 0xff,
+	0xf3, 0xff, 0xfb, 0xbf, 0xef, 0xff, 0xf3, 0x7f,
+	0xff, 0xff, 0xff, 0xfb, 0xff,
+	0xff, 0x38, 0xf8, 0xf7, 0xff, 0xff, 0xdf, 0x9f,
+	0xf7, 0x0b, 0x0f, 0xf5, 0xf5, 0xff, 0xff, 0xff,
+	0xbf, 0xf7, 0xf3, 0x8e, 0x0e,
+	0xbf, 0xe8, 0x6f, 0xef, 0x7f, 0xff, 0xdf, 0xdf,
+	0xef, 0x88, 0xf5, 0x91, 0xfb, 0xff, 0xff, 0xbf,
+	0xfe, 0xbf, 0xa6, 0x81, 0x71,
+	0xff, 0xf0, 0xf8, 0xff, 0x67, 0xef, 0xff, 0xb7,
+	0xf7, 0x8f, 0x2f, 0xd1, 0x41, 0xff, 0xcf, 0x5f,
+	0xfe, 0xff, 0x7b, 0x8f, 0x9f,
+	0xff, 0xf8, 0x6f, 0xef, 0xf7, 0xe7, 0xff, 0xff,
+	0xbf, 0x8f, 0xd1, 0xf1, 0xcf, 0xdf, 0xcf, 0xdf,
+	0xff, 0xff, 0x9f, 0x8f, 0xe1,
+	0xff, 0xe7, 0xff, 0xf7, 0xe7, 0x6f, 0xf7, 0xe7,
+	0xe7, 0x77, 0xef, 0xef, 0x6f, 0xff, 0xff, 0xdf,
+	0xff, 0xdf, 0xdf, 0xff, 0xff,
+	0xff, 0xa7, 0x6f, 0xff, 0xf7, 0xef, 0x97, 0xe7,
+	0xf0, 0xef, 0x7f, 0xaf, 0x4f, 0xff, 0xff, 0xdf,
+	0xbf, 0x5f, 0xe0, 0x7f, 0xef,
+	0x7f, 0xa0, 0xef, 0xff, 0xe7, 0xff, 0xf7, 0xf7,
+	0xff, 0x8b, 0xbf, 0xf8, 0xdf, 0xff, 0xcf, 0x7e,
+	0xff, 0xdf, 0x7f, 0x8e, 0x5f,
+	0xff, 0xff, 0x38, 0xff, 0xf7, 0xff, 0xf7, 0xf7,
+	0xf7, 0xf7, 0x8f, 0xf7, 0xf8, 0xf7, 0xcf, 0xff,
+	0xff, 0xff, 0xfe, 0xcb, 0x3f,
+	0x3f, 0x9f, 0x7f, 0xf8, 0xff, 0xef, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0xaf, 0xff, 0xf0, 0xff, 0xdf,
+	0xff, 0xff, 0xae, 0x7f, 0xc1,
+	0x7f, 0xf0, 0x7f, 0xff, 0xff, 0xff, 0xef, 0xff,
+	0xf7, 0xbf, 0xbf, 0xd0, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xff, 0x9b, 0xff,
+	0x7f, 0xcf, 0xf8, 0xff, 0x8f, 0x6f, 0xe0, 0xd7,
+	0xf7, 0xf7, 0xff, 0xfe, 0xf0, 0xfe, 0x8f, 0x5e,
+	0xd1, 0xff, 0xdf, 0xdf, 0xbe,
+	0xff, 0x84, 0x7f, 0xf8, 0xff, 0x7f, 0xdf, 0xff,
+	0xff, 0xaf, 0x7f, 0x81, 0x7f, 0xf5, 0xff, 0xff,
+	0xff, 0xff, 0xfa, 0x9f, 0x3f,
+	0xff, 0xd8, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x0f, 0xff, 0x85, 0x7f, 0xf0, 0xff, 0xfe,
+	0xbf, 0xff, 0xdf, 0x6f, 0xbf,
+	0xff, 0xff, 0xff, 0xff, 0xaf, 0xff, 0xf7, 0xdf,
+	0xf7, 0x47, 0xf4, 0xff, 0xef, 0xff, 0xdf, 0x7f,
+	0xff, 0xbf, 0xcf, 0x5a, 0xf1,
+	0xff, 0xbf, 0xbf, 0xff, 0xff, 0x3f, 0x8f, 0xc0,
+	0xf3, 0xd1, 0xff, 0xfb, 0xef, 0xff, 0xdf, 0xbe,
+	0x0f, 0x25, 0xe9, 0xd1, 0xff,
+	0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xf7, 0xf7,
+	0x2f, 0xaf, 0xf3, 0xfb, 0xef, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xcf, 0xbf, 0xfb,
+	0xbf, 0x87, 0xf8, 0xf8, 0xdf, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xeb, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
+	0xfb, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xdf, 0xf7, 0xff, 0xff, 0xcf, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xfe,
+	0xcf, 0xff, 0x7b, 0xfd, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xdf, 0xff, 0xbf, 0xff,
+	0xfb, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xef, 0xff,
+	0xfb, 0xbe, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xd4, 0xbf, 0xf0,
+	0xbf, 0xff, 0xff, 0xff, 0x93, 0x2f, 0xfd, 0xad,
+	0xf7, 0x75, 0xff, 0xff, 0xfe,
+	0xbf, 0x7f, 0xff, 0x9a, 0xff, 0xf4, 0x0f, 0xff,
+	0x00, 0xde, 0xf0, 0xf3, 0xf9, 0xbf, 0x7d, 0xff,
+	0x8f, 0x7f, 0x81, 0x0f, 0xd1,
+	0xff, 0xfb, 0xdf, 0xee, 0x8b, 0x0b, 0x78, 0xf0,
+	0xff, 0xfa, 0x7f, 0xbf, 0xff, 0xd5, 0x8f, 0x8f,
+	0xe1, 0xf7, 0xfb, 0xfb, 0xff,
+	0x7f, 0xb7, 0x99, 0xef, 0xdf, 0xf4, 0xff, 0xff,
+	0xe4, 0xf4, 0x5d, 0xf6, 0xef, 0x9f, 0xef, 0xf7,
+	0x3b, 0x3f, 0xdf, 0xbf, 0xec,
+	0xff, 0xec, 0xf7, 0xb9, 0x6b, 0xbc, 0xfb, 0xf7,
+	0xef, 0xff, 0x7e, 0xfd, 0x7e, 0xbb, 0xdf, 0x85,
+	0xfe, 0xf7, 0xff, 0x7b, 0x7f,
+	0xff, 0xff, 0xa7, 0xee, 0xe7, 0x5f, 0xe0, 0xf0,
+	0xff, 0xff, 0xff, 0x5f, 0xe6, 0x6f, 0x81, 0x8d,
+	0xd5, 0xf7, 0xbf, 0xef, 0xb6,
+	0xff, 0xd7, 0xf4, 0xee, 0xb7, 0x7c, 0xff, 0xd7,
+	0xaf, 0x7f, 0xed, 0x9f, 0xe5, 0xbf, 0xf7, 0x7d,
+	0xfb, 0xb7, 0xad, 0xd7, 0xfd,
+	0xbf, 0xff, 0xff, 0xc7, 0x8b, 0xff, 0xf0, 0xf6,
+	0xff, 0xfd, 0xfb, 0xff, 0xdf, 0xbe, 0x0f, 0x7f,
+	0xd5, 0xf7, 0xff, 0xf2, 0xfe,
+	0xff, 0xff, 0xc5, 0xff, 0xf0, 0x7c, 0xff, 0xad,
+	0x7f, 0x7f, 0xef, 0xff, 0xcf, 0x4f, 0xf1, 0xf5,
+	0x7b, 0xdd, 0xff, 0xdf, 0xff,
+	0xff, 0x77, 0xef, 0xff, 0xd8, 0xbf, 0xf7, 0xf3,
+	0x5f, 0xfb, 0xf9, 0x7f, 0xe7, 0xff, 0xd7, 0x7f,
+	0xad, 0xff, 0xfb, 0xfb, 0xf3,
+	0xff, 0xcc, 0x95, 0x8f, 0xd8, 0xf3, 0xfc, 0xbc,
+	0xdc, 0xdf, 0xbb, 0x44, 0x8b, 0xcb, 0x87, 0xb1,
+	0xb7, 0xa7, 0x97, 0xee, 0xf3,
+	0xff, 0x7f, 0xb4, 0xbf, 0xff, 0xc7, 0x7f, 0xcb,
+	0xfd, 0xbf, 0x7f, 0x7f, 0x74, 0xe7, 0xdf, 0xf5,
+	0xbb, 0xcf, 0xed, 0xfe, 0xfd,
+	0xff, 0x3f, 0xfb, 0x77, 0xcc, 0xbb, 0xf0, 0xfb,
+	0xff, 0xef, 0xbe, 0xff, 0xcf, 0xff, 0x85, 0x3f,
+	0xb5, 0xff, 0xf7, 0x37, 0x7f,
+	0x3f, 0xf7, 0xbf, 0xcf, 0x9f, 0xd7, 0xf7, 0xef,
+	0xff, 0x78, 0xe7, 0xff, 0xff, 0xff, 0x1f, 0x7f,
+	0x65, 0xbf, 0xbf, 0xff, 0xe7,
+	0xff, 0xff, 0xff, 0xff, 0xdb, 0xf7, 0xdf, 0xff,
+	0x77, 0x7f, 0xff, 0xff, 0xbf, 0xbf, 0xde, 0x77,
+	0xdd, 0xff, 0xff, 0xfe, 0xff,
+	0xbf, 0x68, 0xf8, 0xff, 0xf7, 0xff, 0xcf, 0xcf,
+	0xf3, 0x17, 0x3f, 0xd5, 0xdd, 0xf7, 0xff, 0xff,
+	0xcf, 0xdf, 0x73, 0x95, 0x3f,
+	0xff, 0xac, 0x6f, 0xef, 0x77, 0xdf, 0xff, 0xf7,
+	0xbb, 0x85, 0xdd, 0xe1, 0xf7, 0xfb, 0x7b, 0xdf,
+	0xfe, 0xff, 0xb7, 0x9f, 0x79,
+	0xff, 0xd8, 0xac, 0xfb, 0x47, 0xaf, 0xeb, 0xf7,
+	0xff, 0xaf, 0x2e, 0x70, 0xd9, 0xf7, 0xfb, 0xdf,
+	0xea, 0xfb, 0xfb, 0x1b, 0x5f,
+	0xff, 0xf8, 0x6f, 0xaf, 0xd7, 0xb7, 0xeb, 0xff,
+	0xe7, 0xaf, 0x7c, 0x70, 0xfb, 0xdf, 0xff, 0x7b,
+	0xfb, 0xff, 0xda, 0x9f, 0xf9,
+	0xff, 0x95, 0xbb, 0xfd, 0xc7, 0xcf, 0xfb, 0x83,
+	0xef, 0xf3, 0xbf, 0xcf, 0x47, 0xf7, 0xe7, 0x1f,
+	0xd7, 0x8b, 0x6f, 0x33, 0xbe,
+	0xff, 0xc7, 0x6f, 0xfd, 0x97, 0x2f, 0xeb, 0xb7,
+	0xdc, 0x77, 0xd7, 0x1f, 0x67, 0xf7, 0xe7, 0x9e,
+	0xe7, 0xdb, 0x34, 0xdb, 0xfb,
+	0x7f, 0xa8, 0xef, 0xff, 0xe7, 0xef, 0xff, 0xf7,
+	0xff, 0x8b, 0xbf, 0xd8, 0xef, 0xff, 0xe7, 0xdf,
+	0xf7, 0xfb, 0xf7, 0x9f, 0x66,
+	0xff, 0xfb, 0x6c, 0xff, 0xb7, 0x9f, 0xcf, 0xcb,
+	0xbb, 0x93, 0xaf, 0xff, 0xa8, 0xff, 0xc7, 0x3f,
+	0xa7, 0xcf, 0xfe, 0xe3, 0x3f,
+	0x3f, 0xdf, 0x7b, 0xfa, 0xff, 0xff, 0xff, 0xf7,
+	0x8f, 0x3f, 0xd0, 0xd3, 0x7f, 0xfc, 0xff, 0x8e,
+	0xff, 0xf3, 0x8f, 0x4e, 0xe4,
+	0x7f, 0xb8, 0xff, 0xff, 0xff, 0xef, 0x8f, 0xdf,
+	0xf3, 0xbb, 0x3f, 0xe0, 0xf3, 0xff, 0xff, 0xef,
+	0x8f, 0xd7, 0xf3, 0xab, 0xef,
+	0x7f, 0x8f, 0xf8, 0xfb, 0x8f, 0x6f, 0xa0, 0xff,
+	0xff, 0xdc, 0xff, 0x5f, 0xfc, 0xf3, 0x8f, 0x6e,
+	0xb1, 0xf7, 0xf7, 0xf7, 0x3e,
+	0xff, 0x90, 0x7b, 0xf8, 0xff, 0x7f, 0xdf, 0xff,
+	0xfb, 0x9f, 0x7f, 0xa0, 0xf3, 0xf1, 0xff, 0xff,
+	0xdf, 0xff, 0xdb, 0xbf, 0x3f,
+	0xff, 0xdc, 0xfb, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x77, 0xaf, 0xff, 0xad, 0xf3, 0xf8, 0xff, 0xfe,
+	0xef, 0xff, 0xff, 0x6f, 0xbf,
+	0xff, 0xff, 0xcf, 0xff, 0xa3, 0xff, 0xaf, 0xcf,
+	0x93, 0xc3, 0x74, 0xef, 0xdf, 0xff, 0xab, 0x2f,
+	0xe7, 0xc7, 0xf3, 0x73, 0x79,
+	0xff, 0xff, 0xcf, 0xff, 0xc3, 0x7f, 0x83, 0xe4,
+	0xd3, 0xbc, 0x7b, 0xdb, 0xdf, 0x7f, 0x8b, 0x8e,
+	0x83, 0x01, 0x51, 0xd5, 0x7b,
+	0xff, 0xfb, 0xdf, 0xff, 0xc3, 0xef, 0xb3, 0xff,
+	0xb7, 0xff, 0xfe, 0xbf, 0xdf, 0xff, 0x8b, 0x6e,
+	0xf3, 0xfb, 0xb7, 0x1f, 0xfe,
+	0xbf, 0x82, 0xc8, 0xf8, 0xd3, 0x7f, 0xf3, 0xfb,
+	0xff, 0xef, 0x87, 0x87, 0xd0, 0x70, 0x8b, 0xff,
+	0xf3, 0xff, 0xef, 0xef, 0x87,
+	0xff, 0xff, 0xff, 0xff, 0x47, 0xff, 0xf3, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xdf, 0x7f, 0xcb, 0xef,
+	0xf2, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xf7, 0xef, 0xf2, 0xf7, 0xff, 0xf7, 0xff,
+	0xff, 0xff, 0xf7, 0xef, 0xdf, 0xf7, 0xca, 0x7f,
+	0xf3, 0xf7, 0xef, 0xff, 0xf6,
+	0xff, 0xfa, 0xfb, 0xff, 0xe7, 0xff, 0xf7, 0xff,
+	0xff, 0xef, 0xff, 0xf7, 0x57, 0x7f, 0xca, 0xef,
+	0xf3, 0xff, 0xff, 0xef, 0xef,
+	0xff, 0xf6, 0xeb, 0xfa, 0xf7, 0xff, 0xf7, 0x8f,
+	0xff, 0xe3, 0xf7, 0xef, 0xd7, 0xf7, 0xcb, 0x7f,
+	0xf3, 0x8f, 0x6c, 0xf2, 0xe7,
+	0xff, 0xff, 0x2f, 0xff, 0xf1, 0x9d, 0x9e, 0xf4,
+	0xff, 0xff, 0xff, 0xef, 0x0f, 0xff, 0xf1, 0x09,
+	0x3f, 0xf9, 0xbf, 0xf7, 0xfb,
+	0xff, 0xef, 0x7f, 0xf6, 0xfb, 0xf5, 0x0f, 0xdf,
+	0x00, 0xff, 0xd0, 0xbf, 0xc0, 0xbf, 0xf9, 0xff,
+	0x8f, 0x7f, 0x81, 0x6f, 0xe1,
+	0xff, 0xff, 0x9e, 0xaf, 0xf7, 0x0f, 0x18, 0xd9,
+	0xbf, 0x6f, 0x37, 0xef, 0x8f, 0xff, 0x9e, 0x06,
+	0x75, 0xf7, 0xf6, 0xff, 0xef,
+	0x7f, 0xf7, 0xcf, 0xbb, 0xfb, 0x6d, 0xfb, 0xef,
+	0x7d, 0xe9, 0xff, 0xff, 0xbf, 0xc2, 0xf7, 0x6f,
+	0xff, 0xdc, 0xff, 0xf3, 0xfa,
+	0x7f, 0x6f, 0xf7, 0xf9, 0xff, 0x6d, 0xfe, 0x9c,
+	0xbf, 0xbf, 0x7d, 0xe2, 0x7f, 0x77, 0x9f, 0xcd,
+	0xb7, 0xb5, 0xff, 0xff, 0x7f,
+	0x7f, 0xff, 0x87, 0xae, 0x86, 0xdf, 0xc0, 0xfd,
+	0xfb, 0xfa, 0xff, 0xff, 0x8e, 0x6d, 0xd5, 0x3d,
+	0xf1, 0xff, 0xfe, 0xef, 0xff,
+	0xff, 0x3f, 0xd2, 0xa4, 0xfe, 0xd9, 0xf7, 0xfe,
+	0xdf, 0xff, 0xcb, 0xff, 0xdd, 0x7e, 0xbb, 0xdd,
+	0x5f, 0xf7, 0xbf, 0xff, 0xed,
+	0xff, 0xfe, 0xf5, 0xff, 0xb7, 0xf6, 0xb4, 0xae,
+	0xfe, 0xef, 0xf7, 0xff, 0xff, 0x8f, 0x07, 0x7b,
+	0xfb, 0xff, 0x7f, 0xff, 0xf7,
+	0xff, 0x7b, 0xa3, 0xbf, 0xe3, 0xff, 0xff, 0xf7,
+	0xf7, 0xfd, 0xdf, 0xff, 0x8f, 0x7f, 0x9b, 0xdf,
+	0xfb, 0xef, 0xfe, 0xff, 0x3f,
+	0xff, 0x6f, 0xff, 0x7f, 0xb3, 0x7f, 0xdf, 0xbd,
+	0x78, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xef, 0xff,
+	0xdf, 0xee, 0x9d, 0xfd, 0xef,
+	0xff, 0xf8, 0x05, 0x8e, 0xb0, 0x58, 0xf7, 0xfc,
+	0xa4, 0x85, 0xdd, 0xbc, 0x0b, 0x05, 0x61, 0xf8,
+	0xb7, 0xff, 0xeb, 0xef, 0x7f,
+	0xbf, 0xff, 0xc7, 0xbb, 0xd8, 0x6f, 0x79, 0xde,
+	0xff, 0xff, 0xcf, 0xff, 0xba, 0xaf, 0xd9, 0x7b,
+	0xfd, 0xff, 0xf5, 0xdf, 0xbf,
+	0xff, 0xff, 0xaf, 0x7f, 0x88, 0x7f, 0xf0, 0xea,
+	0xfe, 0x7f, 0xf2, 0xff, 0xdf, 0xd7, 0x4f, 0x7f,
+	0xe3, 0xde, 0xff, 0xff, 0xf7,
+	0xff, 0x7d, 0x6f, 0x5f, 0xab, 0xff, 0x7a, 0xb6,
+	0xbf, 0x78, 0xdd, 0x7f, 0xde, 0xef, 0x4b, 0x9b,
+	0xeb, 0x7f, 0x76, 0x9f, 0xac,
+	0xff, 0xcf, 0xff, 0xff, 0xb7, 0x7f, 0xae, 0xef,
+	0xdb, 0xef, 0xff, 0xf7, 0xff, 0xfb, 0xe7, 0xfe,
+	0xbf, 0x7e, 0xfb, 0xf7, 0xfb,
+	0xff, 0xff, 0xff, 0xff, 0xcf, 0xbf, 0xff, 0xff,
+	0xf3, 0xff, 0xff, 0xff, 0xff, 0xef, 0xd7, 0xff,
+	0xe9, 0xef, 0xf2, 0xfe, 0xff,
+	0xff, 0xff, 0xff, 0xef, 0xff, 0x8d, 0xaf, 0xf2,
+	0x71, 0xff, 0xfe, 0xff, 0xff, 0x7f, 0xff, 0xcf,
+	0x0f, 0x75, 0xf1, 0xff, 0xff,
+	0x3f, 0x78, 0xbc, 0xfb, 0xfe, 0xff, 0xff, 0xbf,
+	0xf3, 0x0f, 0x3f, 0xc9, 0xe9, 0x7f, 0xf7, 0xdf,
+	0xff, 0xff, 0x57, 0x82, 0x2e,
+	0xff, 0xf8, 0x7f, 0xfb, 0x7a, 0xfb, 0xff, 0xff,
+	0xeb, 0x87, 0x9b, 0xf1, 0xe5, 0x7f, 0x75, 0x7f,
+	0xfe, 0xff, 0xbe, 0x39, 0x79,
+	0xff, 0xcd, 0xbf, 0xfd, 0x7e, 0xff, 0xfb, 0xf4,
+	0xf7, 0xed, 0x6f, 0xf3, 0x6b, 0xf7, 0xd7, 0xbf,
+	0xfe, 0xfd, 0xf7, 0x8f, 0xef,
+	0xff, 0xf8, 0x7a, 0xff, 0xfa, 0xf0, 0xff, 0xff,
+	0xe6, 0x8f, 0x9b, 0xf1, 0xad, 0xbf, 0xf7, 0xfd,
+	0xbf, 0xfd, 0xef, 0x8f, 0x3f,
+	0xbf, 0xff, 0xad, 0xfb, 0xf4, 0xbf, 0xf3, 0x90,
+	0xdd, 0xf0, 0xfa, 0xcf, 0xe7, 0xf2, 0xf7, 0x7f,
+	0xff, 0xad, 0xff, 0xf5, 0xdf,
+	0xff, 0xcb, 0x7b, 0xfa, 0xd2, 0x7f, 0xc7, 0xf3,
+	0xa9, 0xf7, 0xe7, 0x8b, 0xe7, 0xf1, 0xf7, 0x3f,
+	0x8f, 0x7f, 0xb0, 0xdf, 0xfd,
+	0x7f, 0xf8, 0xff, 0xfb, 0xf2, 0xff, 0xd2, 0xe3,
+	0xdf, 0x87, 0xd3, 0xf0, 0xed, 0xff, 0xf7, 0x7f,
+	0xff, 0xef, 0x77, 0xaa, 0x7f,
+	0xbf, 0xea, 0xfc, 0xfb, 0xb3, 0xbf, 0xb3, 0xff,
+	0xd8, 0x93, 0xab, 0xf1, 0xac, 0xff, 0xf7, 0x3f,
+	0xaf, 0xef, 0xed, 0xc7, 0xad,
+	0xff, 0xd6, 0xff, 0xfd, 0xff, 0xdf, 0xff, 0xf4,
+	0x8f, 0xbf, 0xb1, 0xed, 0xf5, 0xfb, 0xff, 0xef,
+	0xff, 0xf5, 0x8f, 0xdf, 0xf1,
+	0xff, 0xf8, 0xfe, 0xfb, 0xff, 0xdf, 0x9f, 0xf8,
+	0xf0, 0xef, 0xff, 0xd0, 0xfd, 0xf7, 0xff, 0xef,
+	0xaf, 0xf5, 0xf7, 0xce, 0x7f,
+	0x7f, 0x83, 0x7d, 0xfa, 0x8f, 0x5f, 0xd0, 0xcb,
+	0xe9, 0xbb, 0x76, 0x9f, 0x7b, 0xf7, 0x8f, 0x6e,
+	0xb1, 0xd5, 0xf7, 0x5f, 0xc6,
+	0xff, 0xa3, 0x7f, 0xfc, 0xff, 0x7f, 0xff, 0xff,
+	0xdf, 0x9f, 0x7f, 0xa8, 0x77, 0xf5, 0xff, 0xfe,
+	0xff, 0xff, 0xfe, 0x7f, 0x2d,
+	0xff, 0x96, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff,
+	0x37, 0x6f, 0xfd, 0xaf, 0x77, 0xf8, 0xff, 0xff,
+	0xef, 0xff, 0xff, 0xff, 0x4b,
+	0xff, 0x72, 0xaf, 0xff, 0xe5, 0xdf, 0x99, 0xfc,
+	0x10, 0x63, 0xf0, 0xef, 0xef, 0x7f, 0x8b, 0xef,
+	0xaf, 0xe7, 0xf5, 0xf7, 0x7d,
+	0xff, 0xef, 0x8f, 0xff, 0xa1, 0x4f, 0x81, 0xe7,
+	0xb0, 0xfa, 0xfe, 0xd7, 0xcf, 0xff, 0xca, 0xcf,
+	0x0b, 0x85, 0x71, 0xfa, 0xff,
+	0xff, 0xdd, 0xef, 0xff, 0xa4, 0xdf, 0xb1, 0xdc,
+	0xd3, 0xff, 0xf8, 0xff, 0xcf, 0x7f, 0xcb, 0x7f,
+	0xff, 0xf5, 0xff, 0xbf, 0xfd,
+	0xbf, 0x82, 0xc8, 0xf8, 0xe1, 0x7f, 0xf0, 0xdf,
+	0xff, 0xef, 0x87, 0x87, 0xc0, 0xf0, 0xca, 0x2f,
+	0xfb, 0xff, 0xef, 0xee, 0x97,
+	0xff, 0xff, 0x8f, 0xfa, 0xa5, 0xdf, 0xd1, 0xf7,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0xdb, 0xef,
+	0xff, 0xf5, 0xfd, 0xff, 0xff,
+	0xff, 0xf6, 0x8b, 0xf2, 0x94, 0xff, 0xf1, 0xf7,
+	0xff, 0xff, 0xf7, 0xef, 0xd7, 0xf7, 0xdf, 0xee,
+	0xfb, 0xff, 0xef, 0xff, 0xf7,
+	0xff, 0xf3, 0xcb, 0xff, 0xe6, 0xff, 0xf1, 0xef,
+	0xff, 0xef, 0xff, 0xe7, 0xd7, 0x7f, 0xdb, 0x7e,
+	0xfd, 0xf7, 0xff, 0xef, 0xef,
+	0xff, 0xfe, 0xcf, 0xff, 0xc4, 0xff, 0xf2, 0x9f,
+	0xff, 0xe0, 0xf7, 0xff, 0xdf, 0xff, 0xdf, 0x7f,
+	0xdb, 0xac, 0xef, 0xf1, 0xf7,
+	0x7f, 0xef, 0x0f, 0x5f, 0xb4, 0x8f, 0xff, 0xf6,
+	0xfd, 0xff, 0x6f, 0xff, 0x8f, 0xff, 0xe9, 0x8d,
+	0x7f, 0xf1, 0xd1, 0xf7, 0xfe,
+	0xff, 0xe7, 0x7f, 0x87, 0xfd, 0xe7, 0x8f, 0x9b,
+	0x00, 0xff, 0xb0, 0x7d, 0xfd, 0xcf, 0xfb, 0xfd,
+	0x8f, 0x7f, 0x81, 0x6d, 0xd1,
+	0xff, 0xbc, 0xed, 0xff, 0x86, 0x6e, 0x10, 0xf1,
+	0xf4, 0x5f, 0x7f, 0xfe, 0x9f, 0x37, 0xc3, 0x8f,
+	0xf7, 0xe5, 0xfb, 0xff, 0xff,
+	0x7f, 0xfe, 0xff, 0xfd, 0x97, 0xff, 0xfb, 0xff,
+	0x3f, 0xff, 0xf9, 0xc3, 0x1f, 0xf8, 0xff, 0xb5,
+	0x5f, 0xef, 0xdc, 0xff, 0xbe,
+	0xff, 0xcb, 0xe7, 0xfd, 0x69, 0xe7, 0xfc, 0xb6,
+	0xef, 0x9a, 0x77, 0xb6, 0x67, 0xdf, 0xef, 0xf7,
+	0xfe, 0xdf, 0xff, 0xf5, 0x7f,
+	0xff, 0xf7, 0x97, 0xbe, 0xf4, 0xff, 0xf1, 0xba,
+	0xfe, 0xff, 0x97, 0x7f, 0xbf, 0x77, 0x55, 0xdf,
+	0xd9, 0xf1, 0xff, 0xdf, 0xff,
+	0xbf, 0xbf, 0x72, 0xf2, 0xdd, 0xff, 0xe4, 0xff,
+	0x7f, 0xef, 0xff, 0xf7, 0xfe, 0xfb, 0xb9, 0xff,
+	0xff, 0xf5, 0xff, 0xfb, 0x96,
+	0xff, 0x7f, 0xf7, 0xef, 0x83, 0xf7, 0xf7, 0xff,
+	0xdf, 0xff, 0xf7, 0xfd, 0xd5, 0x9f, 0x0f, 0x7f,
+	0xf0, 0xfb, 0xae, 0xff, 0xec,
+	0xff, 0x7b, 0x85, 0xf7, 0xf3, 0xef, 0xff, 0xf7,
+	0xff, 0xed, 0xff, 0xe7, 0x8f, 0x7f, 0xc7, 0x97,
+	0x3f, 0xfc, 0xff, 0xf7, 0xde,
+	0xff, 0xfd, 0x8b, 0xff, 0xf7, 0x1f, 0xfb, 0xff,
+	0x2f, 0xfb, 0xf7, 0xff, 0xbf, 0xff, 0xff, 0x6f,
+	0xf7, 0xf9, 0xe7, 0xff, 0x33,
+	0xff, 0x9e, 0xe7, 0x8b, 0xf0, 0x50, 0xf1, 0xde,
+	0xff, 0x9f, 0x1b, 0x28, 0x1b, 0x8d, 0xb4, 0xe1,
+	0xf5, 0xf3, 0xfe, 0xef, 0xfa,
+	0xff, 0x7f, 0xf6, 0xff, 0xfe, 0x07, 0xec, 0xfb,
+	0x7f, 0xff, 0xfd, 0xff, 0xd6, 0x8f, 0xff, 0xf9,
+	0xff, 0x37, 0x7f, 0xfb, 0xdd,
+	0xff, 0xff, 0xff, 0x63, 0xef, 0xdf, 0xfa, 0xf1,
+	0xff, 0xfc, 0xfe, 0xdf, 0xfb, 0xff, 0x8f, 0x7f,
+	0xf9, 0xeb, 0xef, 0xfd, 0xff,
+	0x7f, 0x7f, 0xfb, 0xe7, 0x9f, 0x9b, 0xe5, 0xcf,
+	0xfd, 0xf7, 0xcf, 0xff, 0xf3, 0xbf, 0x5f, 0x5d,
+	0x67, 0x9f, 0xdf, 0x7f, 0xf9,
+	0xff, 0xff, 0xff, 0x1f, 0xfe, 0xff, 0xf5, 0xdf,
+	0x5f, 0xfb, 0xfb, 0xbf, 0xcf, 0xdf, 0xfb, 0x7f,
+	0xb7, 0xff, 0xfb, 0xff, 0xf7,
+	0x3f, 0x78, 0xfc, 0xf3, 0xff, 0xff, 0xdf, 0xbf,
+	0xf3, 0x05, 0x3f, 0xc1, 0xf1, 0xff, 0xf7, 0xef,
+	0xef, 0xff, 0xfb, 0x97, 0x1f,
+	0xff, 0xd8, 0x7f, 0xfb, 0x7b, 0xfb, 0xf7, 0xbf,
+	0xbb, 0x8e, 0xd3, 0xe1, 0xff, 0xfd, 0xf7, 0xed,
+	0xfe, 0x8b, 0x5e, 0x0f, 0x69,
+	0xbf, 0xf8, 0xfc, 0xfb, 0x7b, 0xff, 0xdf, 0xed,
+	0xf7, 0x8f, 0xbf, 0xce, 0xfe, 0xff, 0xf3, 0xff,
+	0xf6, 0xff, 0xfe, 0x8f, 0x0f,
+	0xff, 0xfc, 0x7d, 0xff, 0xff, 0xfd, 0xf3, 0xff,
+	0xbf, 0x8f, 0xe3, 0xf0, 0xfe, 0xff, 0xfb, 0xff,
+	0xff, 0xff, 0xae, 0x0f, 0x5d,
+	0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xd1,
+	0xfd, 0xf1, 0xd3, 0xdd, 0xfd, 0xf1, 0xfb, 0xff,
+	0xfb, 0xfd, 0xff, 0xfd, 0xf6,
+	0xff, 0xff, 0x7f, 0xfe, 0xfd, 0xff, 0x87, 0xff,
+	0xcc, 0xf3, 0xdf, 0xcb, 0xff, 0xfb, 0xfb, 0xff,
+	0x8b, 0x7f, 0xfa, 0xff, 0xff,
+	0x7f, 0xf8, 0xfe, 0xff, 0xef, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xe8, 0xff, 0xff, 0xf9, 0xff,
+	0xfb, 0xaf, 0x7f, 0x8f, 0x7e,
+	0xbf, 0xfb, 0x78, 0xff, 0xff, 0xff, 0xd7, 0xd3,
+	0xfd, 0xc3, 0x95, 0xc5, 0xf8, 0xff, 0xfb, 0xff,
+	0xfb, 0xff, 0xfc, 0xf2, 0x8f,
+	0xff, 0x8b, 0x7b, 0xff, 0xff, 0xdf, 0xff, 0xfd,
+	0x8f, 0xef, 0xf4, 0xb7, 0xff, 0xfe, 0xff, 0xfe,
+	0xff, 0xff, 0x8f, 0x6f, 0xf4,
+	0xff, 0xfd, 0xff, 0xfe, 0xff, 0xdf, 0xdf, 0xfd,
+	0xf1, 0xb3, 0xff, 0xd8, 0xff, 0xfd, 0xff, 0xff,
+	0xff, 0xfd, 0xf5, 0x87, 0x7f,
+	0x3f, 0xef, 0xff, 0xff, 0x8f, 0x5f, 0xf0, 0xff,
+	0xf1, 0xef, 0x39, 0xc7, 0x7e, 0xf3, 0x8f, 0x7e,
+	0xf1, 0xbd, 0xed, 0xfa, 0x9a,
+	0xff, 0x98, 0x7f, 0xfa, 0xff, 0x7f, 0xff, 0xff,
+	0xf3, 0x8f, 0x5f, 0x8a, 0xfb, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xf7, 0xaf, 0x5f,
+	0xff, 0x86, 0xff, 0xfc, 0xff, 0xff, 0xdf, 0xff,
+	0x7f, 0xbf, 0xcb, 0xbd, 0x77, 0xf2, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xbf, 0x77,
+	0xff, 0xff, 0xef, 0xff, 0xed, 0xdf, 0xff, 0xdd,
+	0x11, 0x73, 0xfc, 0xfc, 0xef, 0xff, 0xfb, 0xff,
+	0xfd, 0xfd, 0x9d, 0xf3, 0xff,
+	0xff, 0xf9, 0xef, 0xff, 0xf3, 0x0f, 0x83, 0x9e,
+	0xf0, 0xf0, 0xff, 0xed, 0xef, 0xff, 0xe9, 0x8e,
+	0x7b, 0x9d, 0x70, 0xe9, 0xf7,
+	0xff, 0xff, 0xef, 0xff, 0xef, 0xff, 0xf3, 0xf9,
+	0xf7, 0xff, 0xfb, 0xf3, 0xef, 0xfd, 0xeb, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xf8,
+	0x3f, 0x87, 0xec, 0xf8, 0xe5, 0x7f, 0xfb, 0xff,
+	0xff, 0xff, 0x8f, 0x87, 0xe8, 0xf0, 0xeb, 0xff,
+	0xff, 0xfd, 0xff, 0xff, 0x97,
+	0xff, 0xff, 0xef, 0xff, 0xed, 0xdf, 0xd3, 0xbf,
+	0x7f, 0xfe, 0xff, 0xff, 0xef, 0xff, 0xe3, 0xef,
+	0xff, 0xff, 0xff, 0xfe, 0xff,
+	0xff, 0x77, 0xef, 0xfa, 0xe7, 0xff, 0xfb, 0xff,
+	0xff, 0xff, 0xef, 0xef, 0xef, 0xf7, 0xea, 0xfe,
+	0xf3, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xf7, 0xeb, 0xf3, 0xef, 0xff, 0xf3, 0xff,
+	0xf1, 0x7f, 0xff, 0xe7, 0xe7, 0xf7, 0xea, 0xee,
+	0xf7, 0xff, 0xf1, 0xff, 0xe7,
+	0xff, 0xfb, 0x6f, 0xf6, 0xe5, 0xff, 0xeb, 0xdf,
+	0xef, 0xff, 0xff, 0xf7, 0xef, 0xff, 0xe3, 0xef,
+	0xff, 0xfe, 0xff, 0xfe, 0xf7,
+	0x7f, 0xff, 0x4f, 0x5f, 0xe1, 0xc7, 0xef, 0xf1,
+	0xfe, 0x7f, 0x7b, 0xff, 0x6f, 0xff, 0x93, 0x0b,
+	0x7f, 0xf1, 0xfa, 0xdf, 0xff,
+	0xff, 0xfb, 0x7f, 0xdf, 0xf7, 0xef, 0x8f, 0xff,
+	0x00, 0xef, 0xf0, 0xdf, 0x7f, 0xef, 0xff, 0xfb,
+	0x8f, 0x7f, 0x81, 0x6f, 0xd1,
+	0xff, 0xde, 0xff, 0xef, 0xb9, 0x49, 0x74, 0xf3,
+	0xef, 0x7b, 0x7f, 0xff, 0xeb, 0xf7, 0x85, 0x67,
+	0xf1, 0xf0, 0xe1, 0xff, 0xf7,
+	0x3f, 0xab, 0xff, 0xc4, 0xbb, 0xff, 0x8c, 0x9d,
+	0x7e, 0x3a, 0xb5, 0xbb, 0xe3, 0xfb, 0xf3, 0xcd,
+	0xe3, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xdc, 0xf7, 0xf8, 0x77, 0x8f, 0xf7, 0xfe,
+	0x9f, 0x97, 0x7a, 0xf2, 0x7f, 0xfb, 0x8f, 0x1f,
+	0x7d, 0xfd, 0xef, 0xb1, 0x7d,
+	0xff, 0xef, 0xa6, 0xef, 0x98, 0x9d, 0xf0, 0xf4,
+	0xf4, 0xff, 0xff, 0x7f, 0x8f, 0x7f, 0x89, 0x7f,
+	0xe7, 0xff, 0xff, 0xf7, 0xfb,
+	0xbf, 0xa7, 0xb7, 0xdf, 0xba, 0xfd, 0xfe, 0xeb,
+	0xff, 0xff, 0xc4, 0xef, 0x8f, 0x7c, 0xf7, 0x8f,
+	0x7f, 0xf9, 0xfb, 0xff, 0xfb,
+	0xff, 0xff, 0xff, 0xeb, 0x87, 0xfd, 0xf4, 0xf7,
+	0x6f, 0xff, 0xbf, 0xff, 0xff, 0xef, 0xef, 0xdf,
+	0xff, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xf7, 0x85, 0xdb, 0xf2, 0xbf, 0xd7, 0xff,
+	0xff, 0xfd, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xaf,
+	0x7d, 0xff, 0xf7, 0xeb, 0xff,
+	0xbf, 0xfd, 0x8f, 0xff, 0xfa, 0x3f, 0xff, 0xf6,
+	0xb7, 0xff, 0xfe, 0xfb, 0x8f, 0x7f, 0xff, 0xff,
+	0xf3, 0xee, 0xbf, 0x7f, 0xff,
+	0xff, 0x67, 0xc6, 0xaf, 0xc3, 0x74, 0xf7, 0xfe,
+	0xee, 0x8a, 0x37, 0x6e, 0xec, 0x87, 0x71, 0x91,
+	0x13, 0x7d, 0xec, 0x87, 0xff,
+	0xbf, 0x7b, 0xf0, 0xef, 0xfb, 0x3f, 0xb7, 0xfc,
+	0xff, 0xff, 0x97, 0x7d, 0xe8, 0xef, 0x9d, 0x77,
+	0xfd, 0xfb, 0xff, 0xfb, 0xbf,
+	0xff, 0xff, 0xde, 0x77, 0xcd, 0xff, 0xf1, 0xfb,
+	0xff, 0xff, 0xf9, 0xe3, 0xff, 0xff, 0xef, 0xff,
+	0xff, 0xfc, 0xcf, 0xff, 0xf3,
+	0x7f, 0xff, 0xfe, 0x77, 0xaf, 0xf7, 0xf8, 0xef,
+	0xff, 0x76, 0xfa, 0xff, 0x99, 0x6d, 0x9f, 0x6f,
+	0xf1, 0xbf, 0x7f, 0x7f, 0xfc,
+	0xff, 0xff, 0xef, 0xbf, 0xeb, 0xfa, 0xdd, 0xef,
+	0xbc, 0xfd, 0xfd, 0xdf, 0xff, 0xf7, 0xff, 0xff,
+	0xd1, 0xfe, 0xff, 0xfb, 0xff,
+	0x3f, 0x70, 0xf8, 0xff, 0xf5, 0xff, 0xff, 0x9f,
+	0xf3, 0x09, 0x1f, 0xe1, 0xf3, 0xfd, 0xfd, 0xff,
+	0xef, 0xff, 0xf7, 0x8e, 0x1e,
+	0xff, 0xf8, 0x7f, 0xff, 0x77, 0xff, 0xff, 0x9b,
+	0x8f, 0x8e, 0xfb, 0xf1, 0xef, 0xe5, 0xfd, 0xef,
+	0xfe, 0x9f, 0x16, 0x03, 0x61,
+	0xbf, 0xf8, 0xfa, 0xfd, 0x73, 0xff, 0xff, 0xf7,
+	0xf7, 0x8d, 0x9f, 0xe1, 0xf1, 0xff, 0xef, 0xff,
+	0xfc, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xf7, 0xf7, 0xfd, 0xff,
+	0x9f, 0x8f, 0xe1, 0xf1, 0xef, 0xff, 0xff, 0xff,
+	0xfd, 0xff, 0x8e, 0x0f, 0x7d,
+	0xff, 0xf7, 0xf9, 0xfe, 0xf3, 0x7f, 0xff, 0xf7,
+	0xf7, 0xf3, 0xfd, 0xef, 0xff, 0xf9, 0xed, 0xff,
+	0xff, 0xef, 0xff, 0xf7, 0xff,
+	0xff, 0xf7, 0x7e, 0xfe, 0xf7, 0xff, 0x8b, 0xf7,
+	0xfc, 0xeb, 0xeb, 0xed, 0xeb, 0xf9, 0xfd, 0xff,
+	0x8f, 0x7f, 0xf2, 0xfe, 0xed,
+	0x7f, 0xf8, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7,
+	0xf7, 0x8d, 0xff, 0xe8, 0xff, 0xfd, 0xef, 0xfe,
+	0xfd, 0xdf, 0xf6, 0x8f, 0x6f,
+	0xbf, 0xff, 0x78, 0xff, 0xf7, 0xff, 0xfb, 0xff,
+	0xff, 0xe3, 0x9f, 0xe5, 0xea, 0xf5, 0xfd, 0xff,
+	0xed, 0xef, 0xff, 0xf7, 0x8f,
+	0xff, 0x07, 0xff, 0xf9, 0xff, 0xff, 0xff, 0xf7,
+	0x8f, 0xff, 0xf3, 0x93, 0xff, 0xff, 0xff, 0xef,
+	0xff, 0xf7, 0x8f, 0x7f, 0xf3,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf7, 0x8b, 0xff, 0xe8, 0xfb, 0xff, 0xff, 0xef,
+	0xef, 0xf7, 0xf5, 0x8e, 0x7f,
+	0x3f, 0xec, 0xf9, 0xfc, 0x8f, 0x7f, 0xf0, 0xef,
+	0xef, 0xff, 0x1d, 0xed, 0x7e, 0xfd, 0x8f, 0x6e,
+	0xf1, 0xd7, 0xf7, 0xde, 0x8c,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xfb, 0x8f, 0x6f, 0x90, 0xff, 0xf3, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0x87, 0xfb, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x9f, 0xff, 0x93, 0x7f, 0xf2, 0xff, 0xfe,
+	0xef, 0xff, 0xff, 0x9f, 0x69,
+	0xff, 0xfb, 0xef, 0xff, 0xf6, 0xff, 0xff, 0xff,
+	0x1f, 0x73, 0xfe, 0xf6, 0xff, 0xff, 0xff, 0xef,
+	0xef, 0xe7, 0x97, 0x77, 0xf7,
+	0xff, 0xff, 0xff, 0xff, 0xe7, 0x1f, 0x86, 0x95,
+	0xf0, 0xf6, 0xf7, 0xff, 0xff, 0xff, 0xfe, 0x8f,
+	0x6d, 0x93, 0x71, 0xf8, 0xfd,
+	0xff, 0xfe, 0xef, 0xfd, 0xf2, 0xff, 0xf6, 0xff,
+	0x6f, 0xef, 0xf7, 0xfd, 0xff, 0xff, 0xfd, 0xff,
+	0xfd, 0xff, 0xef, 0xff, 0xf5,
+	0x3f, 0x82, 0xf8, 0xf8, 0xe6, 0x7f, 0xf2, 0xff,
+	0xff, 0xff, 0x87, 0x87, 0xf0, 0xf0, 0xfc, 0xef,
+	0xfd, 0xf7, 0xef, 0xee, 0x87,
+	0xff, 0xff, 0xef, 0xff, 0xe7, 0xff, 0xf6, 0xf7,
+	0x7f, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
+	0xff, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xf7, 0xff, 0xf2, 0xe6, 0xff, 0xf5, 0xf7,
+	0xff, 0xff, 0xff, 0xe7, 0xff, 0xf7, 0xff, 0xfe,
+	0xff, 0xf7, 0xef, 0xff, 0xf7,
+	0xff, 0xfa, 0xeb, 0xff, 0xe3, 0xff, 0xf5, 0xff,
+	0xff, 0xff, 0xf7, 0xef, 0xf7, 0xff, 0xfd, 0xee,
+	0xfd, 0xff, 0xff, 0xef, 0xef,
+	0xff, 0xf6, 0xfb, 0x7a, 0xe7, 0xff, 0x91, 0xef,
+	0xff, 0xe2, 0xff, 0xf7, 0xf7, 0xf7, 0xfd, 0xff,
+	0xfd, 0xef, 0xeb, 0xf5, 0xe7,
+	0xff, 0xff, 0x8f, 0xbe, 0xf1, 0x93, 0xfd, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0x2e, 0x2f, 0x59, 0x8f,
+	0x6f, 0xf9, 0xf7, 0xff, 0xfa,
+	0xff, 0x4f, 0xbf, 0xc4, 0xfb, 0xf5, 0x0f, 0xff,
+	0x00, 0xff, 0xd0, 0x7f, 0x70, 0xaf, 0x7f, 0xff,
+	0x8f, 0x7f, 0x81, 0x7f, 0xb1,
+	0xff, 0xff, 0xda, 0xff, 0x2f, 0x4f, 0x7e, 0xf9,
+	0xfb, 0xff, 0x5f, 0xef, 0xff, 0xff, 0x99, 0x29,
+	0x71, 0xf1, 0xed, 0xff, 0xff,
+	0x3f, 0xb7, 0xef, 0xdf, 0xff, 0xf9, 0xfe, 0xfd,
+	0xff, 0xff, 0xb7, 0x9f, 0xff, 0xab, 0x73, 0xfd,
+	0xad, 0x3c, 0x6b, 0xff, 0xfa,
+	0xff, 0xe8, 0xf7, 0xbf, 0x6f, 0x8f, 0xff, 0xfe,
+	0xff, 0x87, 0x7f, 0xe0, 0x7f, 0xbf, 0x5f, 0x93,
+	0x7e, 0xe4, 0xf6, 0x97, 0x7b,
+	0xff, 0xdf, 0x27, 0xaf, 0xa7, 0xff, 0xf4, 0xf6,
+	0xff, 0xff, 0xff, 0x5f, 0xdf, 0xfb, 0x87, 0x1f,
+	0x70, 0xf3, 0xfe, 0x7f, 0xfb,
+	0xbf, 0xb7, 0x61, 0xb5, 0xfc, 0xff, 0xf7, 0xff,
+	0xbf, 0xff, 0xa2, 0xff, 0xd8, 0xa1, 0x77, 0xdf,
+	0xe6, 0xff, 0xff, 0x7e, 0xc4,
+	0xff, 0xff, 0xf6, 0xd7, 0x97, 0xdb, 0xe8, 0xff,
+	0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xb9, 0x3b,
+	0xf8, 0xff, 0xef, 0xe7, 0xbe,
+	0xff, 0xff, 0x86, 0xbf, 0xe2, 0xad, 0xff, 0xff,
+	0xff, 0xff, 0x9f, 0xff, 0x8f, 0x3f, 0x63, 0xcf,
+	0x7b, 0xfe, 0xff, 0xfd, 0xfe,
+	0xff, 0xff, 0xdf, 0xff, 0xba, 0x7f, 0xf7, 0xee,
+	0x17, 0xf7, 0xee, 0xef, 0x97, 0x7f, 0xf7, 0xff,
+	0xff, 0xfd, 0x9e, 0x77, 0xf3,
+	0xff, 0xfb, 0xc3, 0x8f, 0xc1, 0x70, 0x71, 0xff,
+	0xf7, 0x9f, 0x77, 0x7e, 0xb6, 0x4f, 0xb9, 0x01,
+	0x1f, 0x1b, 0x7a, 0x9a, 0x7e,
+	0xbf, 0xff, 0xf0, 0x9f, 0xef, 0x79, 0x3f, 0xf6,
+	0xff, 0xfd, 0x9d, 0x7b, 0xf2, 0xff, 0xc9, 0xf3,
+	0xff, 0x7d, 0xfb, 0xfd, 0xbf,
+	0xff, 0xfd, 0xbf, 0x77, 0x8f, 0xff, 0xf1, 0xf7,
+	0xff, 0xff, 0xff, 0xfd, 0xbb, 0x7f, 0xbf, 0x6f,
+	0xf3, 0xfe, 0xff, 0xe7, 0xbf,
+	0x7f, 0xff, 0xff, 0x5f, 0xaf, 0xf1, 0xfc, 0xf7,
+	0xff, 0x77, 0xfe, 0xff, 0xdf, 0xff, 0xdf, 0xff,
+	0xe3, 0x9e, 0x7f, 0x7a, 0xe3,
+	0xff, 0xff, 0x6f, 0xff, 0xaf, 0xfc, 0xff, 0xff,
+	0xfe, 0xfe, 0xfe, 0xff, 0xff, 0xff, 0xf3, 0xfb,
+	0xf7, 0xff, 0xf9, 0xfe, 0xff,
+	0x3f, 0x70, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0x0f, 0x0f, 0xf1, 0xf1, 0xff, 0xf7, 0xff,
+	0xef, 0xff, 0xf7, 0x8c, 0x1e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xf7, 0xff, 0x8f,
+	0x8f, 0x88, 0xf1, 0xf1, 0xef, 0xff, 0xf7, 0xff,
+	0xee, 0x97, 0x1e, 0x01, 0x61,
+	0xbf, 0xf0, 0xfa, 0xfd, 0x75, 0xff, 0xf5, 0xff,
+	0xff, 0x8f, 0x9f, 0xe1, 0xf1, 0xff, 0xf7, 0xef,
+	0xfe, 0xff, 0xff, 0x8f, 0x1f,
+	0xff, 0xfa, 0x7f, 0xff, 0xfd, 0xff, 0xfd, 0xff,
+	0x9f, 0x9f, 0xf9, 0xf9, 0xff, 0xef, 0xf7, 0xff,
+	0xff, 0xff, 0x9e, 0x0f, 0x75,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,
+	0xff, 0xf7, 0xf7, 0xff, 0xef, 0xf7, 0xe7, 0xef,
+	0xef, 0xef, 0xff, 0xff, 0xef,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf8, 0xf7, 0xff, 0xf7, 0xff, 0xf7, 0xe7, 0xef,
+	0x9f, 0x6f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf8, 0xff, 0xff, 0xfd, 0xff, 0xfd, 0x8f,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf7, 0xef,
+	0xf7, 0xff, 0xff, 0x9d, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xfd, 0xff, 0xfd, 0xf7,
+	0xff, 0xf7, 0x8f, 0xf7, 0xf0, 0xf7, 0xf7, 0xff,
+	0xf7, 0xef, 0xfe, 0xe7, 0x9f,
+	0xff, 0x8f, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf8, 0x8f, 0xff, 0xf8, 0xff, 0xef,
+	0xff, 0xff, 0x8e, 0x6f, 0xe1,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf7, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xef, 0xef, 0xff, 0x9f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x9f,
+	0xf7, 0xfb, 0x07, 0xe7, 0x78, 0xf7, 0x8f, 0x7e,
+	0xf1, 0x9f, 0x7f, 0xff, 0x9e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xf7, 0x8f, 0x6f, 0x80, 0xff, 0xf1, 0xff, 0xff,
+	0xef, 0xff, 0xfe, 0x9f, 0x7f,
+	0xff, 0x88, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x9f, 0xef, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xef, 0x9f, 0x7f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x97, 0x77, 0xf8, 0xff, 0xef, 0xff, 0xf7, 0xff,
+	0xef, 0xef, 0x8f, 0x76, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0xf7, 0x0f, 0xf7, 0x88,
+	0xf7, 0xf0, 0xff, 0xff, 0xef, 0xff, 0xef, 0x8e,
+	0x07, 0x99, 0x61, 0xe1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xf7,
+	0xff, 0xff, 0xf7, 0xf7, 0xef, 0xff, 0xe7, 0xee,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xf7, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xef, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xef, 0xff, 0xe7, 0xff,
+	0xf6, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x6f, 0xff, 0xe7, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xf7, 0xff, 0xff, 0xef, 0xff, 0xef, 0xff,
+	0x97, 0xee, 0xf9, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x80, 0x88, 0xff, 0xf8,
+	0xff, 0xff, 0xf7, 0xff, 0x0f, 0x1f, 0x79, 0x9b,
+	0x7f, 0xf0, 0xfe, 0xff, 0xff,
+	0xff, 0x4f, 0x7b, 0xf7, 0xf7, 0xf8, 0x0f, 0xff,
+	0x00, 0xff, 0xd0, 0x4f, 0x75, 0x8c, 0x79, 0xff,
+	0x8f, 0x7f, 0x81, 0x7e, 0xb1,
+	0xff, 0xf7, 0xff, 0xfe, 0x8f, 0x7f, 0x70, 0xf0,
+	0xff, 0xf7, 0x7f, 0xff, 0xf7, 0xff, 0x84, 0x0e,
+	0x73, 0xff, 0xf7, 0xff, 0xff,
+	0x3f, 0xbd, 0xfd, 0xfb, 0xf7, 0xe8, 0xff, 0xff,
+	0x78, 0xf0, 0x3f, 0xbf, 0xe3, 0x9b, 0x6f, 0xff,
+	0x97, 0x1f, 0x7f, 0xcf, 0xfe,
+	0xff, 0xf8, 0xf7, 0xff, 0x8f, 0x80, 0xff, 0xf8,
+	0xff, 0x8f, 0x78, 0xf0, 0x7f, 0x9f, 0x7f, 0x9b,
+	0x7f, 0xf1, 0xff, 0x97, 0x7f,
+	0xff, 0xff, 0x07, 0xff, 0x87, 0x7f, 0xf0, 0xf8,
+	0xff, 0x7f, 0xfb, 0x7f, 0xee, 0xfb, 0x99, 0x19,
+	0x73, 0xef, 0xf7, 0xef, 0xff,
+	0xbf, 0x87, 0x04, 0xfc, 0xff, 0x08, 0xf7, 0xff,
+	0x7b, 0x7f, 0x8e, 0x8f, 0xf9, 0x98, 0x6f, 0xf3,
+	0xff, 0xef, 0xff, 0xff, 0xdf,
+	0xff, 0xff, 0x73, 0xff, 0xf7, 0x9f, 0xf8, 0xfb,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x3d,
+	0x61, 0xff, 0xef, 0xff, 0xff,
+	0xff, 0x7f, 0x07, 0xff, 0xf8, 0x78, 0xff, 0xee,
+	0xfb, 0xff, 0xff, 0xff, 0x87, 0x1f, 0x71, 0xe3,
+	0xff, 0xfb, 0xff, 0xff, 0xff,
+	0xff, 0x77, 0x8b, 0x7f, 0xf8, 0x7f, 0xff, 0xff,
+	0x07, 0xe7, 0xfa, 0x77, 0x8f, 0x7f, 0xff, 0xef,
+	0xf1, 0xef, 0x9f, 0x77, 0xf9,
+	0xff, 0xf8, 0x73, 0x8f, 0xf8, 0x0f, 0x88, 0x88,
+	0xf8, 0x98, 0x77, 0x78, 0x8f, 0x6f, 0x87, 0x7b,
+	0xf7, 0xff, 0xef, 0x87, 0x6f,
+	0xbf, 0x7f, 0xf0, 0xff, 0x8f, 0x7f, 0xff, 0xff,
+	0x7e, 0xff, 0x9f, 0x7f, 0xf0, 0xff, 0xff, 0xeb,
+	0xef, 0xff, 0xfb, 0xff, 0x9f,
+	0xff, 0xff, 0xff, 0x77, 0xf8, 0x7f, 0xf8, 0xf7,
+	0xff, 0x7f, 0xf7, 0xff, 0x9f, 0x7f, 0x9b, 0x6f,
+	0xf1, 0xfe, 0xff, 0xfe, 0xff,
+	0x7f, 0x7f, 0x8f, 0xff, 0x8f, 0xff, 0x7f, 0x8f,
+	0xff, 0x70, 0xfb, 0x6f, 0xff, 0xff, 0xff, 0xf5,
+	0xf9, 0xff, 0xff, 0xff, 0xf4,
+	0xff, 0x87, 0xff, 0x74, 0xff, 0x7f, 0xff, 0xff,
+	0x7e, 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff,
+	0xe9, 0xff, 0xf7, 0xff, 0xff,
+	0xbf, 0x78, 0xf8, 0x7f, 0xf7, 0xff, 0xff, 0xff,
+	0xf7, 0x07, 0x1f, 0xe1, 0xf1, 0xff, 0xf7, 0xff,
+	0xef, 0xef, 0xff, 0x8e, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87,
+	0x9f, 0x88, 0xf1, 0xe1, 0xff, 0xef, 0xf7, 0xef,
+	0xfe, 0x9f, 0x0f, 0x09, 0x71,
+	0xbf, 0xf0, 0xf8, 0xff, 0x77, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xf7, 0xff,
+	0xfe, 0xf7, 0xff, 0x8e, 0x1f,
+	0x7f, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x8f, 0xf9, 0xf8, 0xfe, 0xff, 0xe7, 0xf7,
+	0xff, 0xff, 0x96, 0x0f, 0x61,
+	0x7f, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xf7, 0xef, 0xff, 0xf7, 0xe7, 0xef,
+	0xff, 0xe7, 0xff, 0xf7, 0xfe,
+	0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf8, 0xef, 0xef, 0xef, 0xff, 0xf7, 0xf7, 0xff,
+	0x9f, 0x67, 0xf0, 0xff, 0xff,
+	0x7f, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0x8f, 0xff, 0xe0, 0xf7, 0xff, 0xf7, 0xfe,
+	0xf7, 0xf7, 0xff, 0x8f, 0x6e,
+	0x3f, 0xfb, 0x7c, 0xff, 0xff, 0xff, 0xf7, 0xff,
+	0xff, 0xe7, 0x9f, 0xef, 0xf0, 0xff, 0xe7, 0xef,
+	0xf7, 0xef, 0xf6, 0xf6, 0x87,
+	0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf4, 0x9f, 0xff, 0xfc, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x7f, 0xf0,
+	0x7f, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf7, 0x87, 0xff, 0xe8, 0xff, 0xf7, 0xff, 0xff,
+	0xef, 0xe7, 0xf7, 0x8f, 0x6f,
+	0x3f, 0xff, 0xfc, 0xff, 0x8f, 0x7f, 0xf0, 0xcf,
+	0xef, 0xe8, 0x1b, 0xef, 0x7c, 0xff, 0x8f, 0x7e,
+	0xe1, 0x97, 0x77, 0xff, 0x9e,
+	0xff, 0x80, 0x7f, 0xfc, 0xff, 0x7f, 0xff, 0xff,
+	0xf7, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xfe,
+	0xef, 0xff, 0xff, 0x9f, 0x7f,
+	0xff, 0x84, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x6f, 0x9f, 0xff, 0x91, 0x7f, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0xfb, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff,
+	0x1f, 0x77, 0xf8, 0xf7, 0xef, 0xff, 0xf7, 0xff,
+	0xf7, 0xef, 0x87, 0x67, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x8b, 0x8c,
+	0xf0, 0xf8, 0xf7, 0xff, 0xef, 0xff, 0xe7, 0x9e,
+	0x67, 0x89, 0x77, 0xf1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff,
+	0xff, 0xef, 0xfb, 0xff, 0xef, 0xff, 0xe7, 0xff,
+	0xf7, 0xf7, 0xff, 0xff, 0xf7,
+	0xbf, 0x87, 0xf8, 0xf8, 0xf7, 0x7f, 0xfb, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xe7, 0xfe,
+	0xf7, 0xff, 0xff, 0xff, 0x8e,
+	0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xfb, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xfb, 0xff, 0xfb, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff,
+	0xf7, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x7f, 0xf7, 0xff, 0x8b, 0xff,
+	0xfc, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xee, 0xff, 0xf6, 0xff,
+	0xff, 0xf7, 0x8f, 0xbf, 0xf9, 0x8f, 0xff, 0xf0,
+	0xff, 0xff, 0x7f, 0xff, 0x1f, 0x1f, 0x71, 0x89,
+	0x7f, 0xf1, 0xff, 0xff, 0xff,
+	0xff, 0x4f, 0xb8, 0xc6, 0xfb, 0xfd, 0x0f, 0xff,
+	0x00, 0xff, 0xd0, 0x7f, 0x79, 0x90, 0x7f, 0xf9,
+	0x8f, 0x7f, 0x81, 0x7f, 0x81,
+	0xff, 0xff, 0xcf, 0xff, 0xb0, 0x4f, 0x77, 0xf4,
+	0xff, 0xff, 0x7f, 0xe7, 0xee, 0xff, 0x97, 0x07,
+	0x69, 0xf1, 0xf7, 0xff, 0xff,
+	0x3f, 0xba, 0xff, 0x4d, 0xfe, 0xe5, 0xff, 0xff,
+	0x7f, 0xef, 0xbf, 0x9f, 0xe7, 0x9f, 0x77, 0xe9,
+	0x9f, 0x1f, 0x79, 0xc1, 0xfe,
+	0xff, 0xf8, 0xf7, 0x3f, 0xff, 0x9f, 0xf7, 0xf8,
+	0xff, 0x87, 0x7f, 0xf0, 0x7f, 0x97, 0x7f, 0x89,
+	0x7e, 0xf1, 0xff, 0x9f, 0x7f,
+	0xff, 0xff, 0x37, 0xbf, 0xb3, 0x7f, 0xf2, 0xff,
+	0xff, 0xf7, 0xff, 0x7f, 0x7b, 0xfe, 0x87, 0x1f,
+	0x71, 0xf1, 0xff, 0x7f, 0xfb,
+	0xff, 0xff, 0x70, 0xb7, 0xfe, 0x7b, 0xff, 0xf3,
+	0xbf, 0xf7, 0xff, 0xff, 0xf9, 0x9f, 0x7f, 0xf1,
+	0xff, 0xf7, 0xff, 0xff, 0xfb,
+	0xbf, 0xff, 0xf4, 0xcf, 0x87, 0xd8, 0xf8, 0xf8,
+	0xff, 0xff, 0x8f, 0xff, 0xe9, 0xff, 0x8f, 0x1f,
+	0x71, 0xff, 0xef, 0xff, 0x8d,
+	0xff, 0xff, 0x87, 0xbf, 0xf9, 0x3f, 0xff, 0xf7,
+	0xff, 0xff, 0xff, 0xff, 0x9f, 0x1f, 0x71, 0xf9,
+	0xff, 0x7b, 0xff, 0xfe, 0xff,
+	0xff, 0xff, 0xcb, 0xff, 0xbd, 0x7f, 0xfb, 0xff,
+	0x8f, 0xff, 0xf8, 0x7f, 0x9f, 0x7f, 0xf1, 0xef,
+	0xff, 0xf7, 0x8f, 0x7f, 0xf9,
+	0xff, 0xf8, 0x43, 0x8f, 0xc4, 0x75, 0x7d, 0xff,
+	0xff, 0x97, 0x7f, 0x78, 0x8f, 0x6f, 0x99, 0x17,
+	0x19, 0x71, 0xf9, 0x8f, 0x6f,
+	0xbf, 0x7f, 0xf0, 0x8f, 0xf6, 0x7d, 0x37, 0xff,
+	0xff, 0xff, 0x9f, 0x7f, 0xe0, 0xff, 0xff, 0xef,
+	0xff, 0xf7, 0xfb, 0xff, 0x8f,
+	0xff, 0xff, 0xbf, 0x77, 0x8e, 0xff, 0xf0, 0xff,
+	0xff, 0xf7, 0xf7, 0x7f, 0x97, 0x7f, 0x99, 0x7f,
+	0xf9, 0xfe, 0xff, 0xfe, 0xff,
+	0x7f, 0xff, 0xff, 0xcf, 0xbf, 0xf9, 0xfa, 0xff,
+	0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xf7, 0x8f, 0x7f, 0x71, 0xf6,
+	0xff, 0xff, 0xff, 0x7f, 0xb7, 0xfe, 0xfb, 0xff,
+	0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,
+	0xff, 0xff, 0xf7, 0xff, 0xff,
+	0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0x08, 0x0f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8e, 0x0e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
+	0x8f, 0x80, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xfe, 0x8f, 0x0e, 0x01, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+	0xfe, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0x88, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xf7, 0x8f, 0xf7, 0xf0, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0xff, 0x8f,
+	0xff, 0x87, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf8, 0x8f, 0xf7, 0xf8, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x7f, 0xf1,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xdf,
+	0xff, 0xf6, 0x07, 0xff, 0x78, 0xff, 0x8f, 0x7e,
+	0xf1, 0x9f, 0x7f, 0xfd, 0x8e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xf7, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x77, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x6e, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x8f, 0x88,
+	0xf0, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8e,
+	0x7f, 0x81, 0x7f, 0xf1, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xf7, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0x87, 0xff,
+	0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xfe, 0xfe, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x3f, 0x8f, 0xf0, 0x85, 0xff, 0xf0,
+	0xff, 0xff, 0xff, 0x7f, 0x0d, 0x0f, 0x71, 0x81,
+	0x7e, 0xf1, 0xfe, 0xff, 0xff,
+	0xff, 0x5f, 0x3d, 0xf0, 0xf5, 0xfa, 0x0f, 0xff,
+	0x00, 0xff, 0x80, 0x0f, 0xf1, 0x88, 0x7f, 0xf1,
+	0x8f, 0x7e, 0x81, 0x7e, 0xc1,
+	0xff, 0xff, 0xff, 0xff, 0xba, 0x4f, 0x75, 0xfa,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0x0f,
+	0x71, 0xf1, 0xff, 0xff, 0xff,
+	0x3f, 0xbf, 0xff, 0xcf, 0xff, 0xfa, 0xff, 0xfe,
+	0x7f, 0xdf, 0x7f, 0xf4, 0xff, 0x8f, 0x7f, 0xf1,
+	0x8f, 0x0f, 0x71, 0xf1, 0xbe,
+	0xff, 0xf8, 0xf7, 0xbb, 0x7f, 0x85, 0xff, 0xf0,
+	0xff, 0x8f, 0x7f, 0xf0, 0x7f, 0x87, 0x7f, 0x81,
+	0x7e, 0xf1, 0x8f, 0x0f, 0x71,
+	0xff, 0xff, 0x87, 0x8f, 0x8d, 0xfd, 0xf5, 0xff,
+	0xfb, 0xff, 0xff, 0xff, 0xf7, 0xfe, 0x8f, 0x0f,
+	0x71, 0xf1, 0xfe, 0x7f, 0xf7,
+	0xbf, 0x07, 0xc0, 0xbf, 0xf7, 0xfd, 0xff, 0xff,
+	0xbf, 0xff, 0x85, 0x8f, 0xf9, 0x8f, 0x7f, 0xf1,
+	0xff, 0x7f, 0xf6, 0xff, 0x83,
+	0xff, 0xff, 0xf4, 0xff, 0x8f, 0xda, 0xf0, 0xb6,
+	0xdf, 0xfd, 0xf6, 0xff, 0xf9, 0xff, 0x8f, 0x1f,
+	0x71, 0xfd, 0x8f, 0x7b, 0xfd,
+	0xff, 0xff, 0xb7, 0x8f, 0xf0, 0xbd, 0xff, 0xfd,
+	0xf7, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0xf1,
+	0xff, 0x7b, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xba, 0x7f, 0xf5, 0xf7,
+	0x0f, 0xf7, 0xf0, 0x7f, 0x87, 0x7f, 0xf1, 0xff,
+	0xff, 0xfe, 0x8f, 0x7f, 0xf1,
+	0xff, 0xf8, 0x47, 0x8f, 0xca, 0x70, 0x7a, 0xff,
+	0xff, 0x8f, 0x7f, 0x70, 0x8f, 0x7f, 0x81, 0x0e,
+	0x01, 0x01, 0x71, 0x81, 0x7f,
+	0xbf, 0x7f, 0xf0, 0x8f, 0xff, 0x70, 0x3f, 0xff,
+	0xfd, 0xfe, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff,
+	0xff, 0xfe, 0xfb, 0xff, 0x8f,
+	0xff, 0xff, 0xbf, 0x7f, 0x85, 0x7f, 0xf0, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0x81, 0x7f,
+	0x81, 0xfe, 0xf1, 0xff, 0xff,
+	0x7f, 0xff, 0xff, 0xcf, 0x87, 0xfa, 0x75, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x7f, 0x70, 0xfe,
+	0xff, 0x87, 0xff, 0x4b, 0xbf, 0x7f, 0xfd, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xfe, 0xff, 0xfe, 0xff,
+	0x3f, 0x78, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0x8e, 0x0e,
+	0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0x7f, 0x8f,
+	0x8f, 0x00, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xfe, 0x8f, 0x0e, 0x01, 0x71,
+	0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0x7f, 0xff,
+	0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff,
+	0xfe, 0xff, 0xff, 0x8f, 0x0f,
+	0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0x7f, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0x7f, 0x8f, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xff, 0xff,
+	0x7f, 0xf8, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7e,
+	0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0x7f, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0xff, 0x8f,
+	0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x7f, 0xf1,
+	0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x8f,
+	0xff, 0xfc, 0x8f, 0xff, 0xf0, 0xff, 0x8f, 0x7e,
+	0xf1, 0x8f, 0x7f, 0xf3, 0x8e,
+	0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0x8f, 0x7f, 0x80, 0x7f, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+	0x7f, 0x8f, 0x7f, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0x7f, 0xf1,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0xff, 0x80,
+	0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x8e,
+	0x0f, 0x01, 0x71, 0xf0, 0xff,
+	0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xef, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0xff, 0xff, 0xf7,
+	0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+	0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, 0xfe, 0xff,
+	0xff, 0xff, 0xff, 0xfe, 0x8f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7e,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7e,
+	0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0xff,
+	0x7f, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f,
+	0x8f, 0xfe, 0xf0, 0xff, 0xff,
+	0xbf, 0xff, 0x0e, 0x8f, 0x70, 0x80, 0xff, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0x0f, 0x7f, 0xf1, 0x0f,
+	0x7f, 0xf1, 0xfe, 0xff, 0x9f,
+	0xbf, 0x1f, 0xfb, 0x0c, 0xff, 0xf0, 0x8f, 0xff,
+	0x00, 0xff, 0xb0, 0x3f, 0x71, 0x80, 0xff, 0xf1,
+	0x8f, 0x7f, 0x81, 0x7e, 0xc1,
+	0xff, 0xff, 0xff, 0x7f, 0x8f, 0x0f, 0x70, 0xf0,
+	0x8f, 0x7f, 0x70, 0xcf, 0x8f, 0xff, 0x71, 0x0f,
+	0x7e, 0xf1, 0x8f, 0x7f, 0xf1,
+	0x7f, 0xff, 0x7f, 0x0f, 0xff, 0x78, 0x8f, 0x8f,
+	0x70, 0x70, 0x7f, 0xfe, 0xff, 0x8f, 0xff, 0x70,
+	0xff, 0xfe, 0xff, 0xff, 0xbe,
+	0xff, 0xf8, 0xf7, 0x0b, 0xf7, 0x88, 0xf7, 0xf0,
+	0x8f, 0x8f, 0x70, 0xf0, 0x7e, 0x73, 0xff, 0x8f,
+	0x7e, 0xf0, 0xff, 0x8f, 0x7f,
+	0xff, 0x78, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0,
+	0xff, 0x8f, 0x77, 0x70, 0x77, 0x7f, 0xff, 0x7f,
+	0xff, 0xff, 0xfe, 0x8f, 0x7f,
+	0xff, 0xff, 0x77, 0x8f, 0xff, 0xf0, 0xff, 0xff,
+	0x77, 0x7f, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xef, 0x7f, 0xff, 0xbf,
+	0xbf, 0xff, 0x74, 0xff, 0xff, 0x8f, 0xff, 0xfc,
+	0x0f, 0xf3, 0x8c, 0xff, 0xfd, 0xff, 0xff, 0x8f,
+	0x7f, 0xf1, 0x8f, 0x7d, 0x83,
+	0xff, 0x7f, 0x77, 0xff, 0xff, 0xff, 0xff, 0xfb,
+	0xf7, 0x7f, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x78, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
+	0x0f, 0x8f, 0x70, 0x70, 0xf7, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8e, 0x0f, 0x71,
+	0xff, 0xf8, 0xf7, 0x7f, 0xff, 0x8f, 0x8f, 0x80,
+	0x80, 0x81, 0x70, 0x70, 0x7f, 0xff, 0xff, 0xff,
+	0xff, 0x6f, 0x8f, 0x0f, 0x71,
+	0xbf, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0x7b, 0xff, 0x9f, 0xff, 0x70, 0xff, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xfe, 0x8f,
+	0xff, 0x87, 0x7f, 0x78, 0xfe, 0xff, 0x9e, 0xff,
+	0xf2, 0x7f, 0xff, 0x0f, 0xff, 0xf0, 0xff, 0xef,
+	0xff, 0x7f, 0xff, 0xff, 0xff,
+	0x7f, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0xfe, 0x8f,
+	0xff, 0x70, 0xff, 0x7f, 0xff, 0xff, 0xdf, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xfe,
+	0xff, 0xff, 0x7f, 0xf7, 0xff, 0xfe, 0xff, 0xff,
+	0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xaf, 0x0f,
+	0x70, 0xd1, 0xff, 0xf8, 0xfe,
+	0xff, 0xff, 0xff, 0xf7, 0xaf, 0x8f, 0xfa, 0xf0,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0x8f, 0x0f,
+	0x79, 0xe1, 0xff, 0xfe, 0xff,
+	0xbf, 0xff, 0xff, 0x7a, 0x8f, 0xff, 0xf0, 0xef,
+	0xff, 0xfb, 0xff, 0xaf, 0xff, 0xfb, 0x8f, 0x7f,
+	0xf1, 0xdf, 0xff, 0xf9, 0xff,
+	0xbf, 0xff, 0xff, 0xf7, 0xff, 0xaf, 0xff, 0xba,
+	0xaf, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xef, 0xdf,
+	0xff, 0xfd, 0xbe, 0xf7, 0xf5,
+	0xff, 0xf8, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff,
+	0xff, 0x8f, 0xf7, 0xf0, 0xff, 0xff, 0x8f, 0x3f,
+	0x11, 0xeb, 0xdb, 0xcf, 0x7f,
+	0xbf, 0xf0, 0x8f, 0x87, 0xf0, 0xf0, 0xff, 0xbf,
+	0xff, 0x8f, 0xff, 0xf1, 0x8f, 0x0f, 0x31, 0xf1,
+	0x9f, 0xdf, 0xf9, 0x85, 0x7f,
+	0xbf, 0xff, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff,
+	0xee, 0xff, 0xfb, 0xf7, 0x8f, 0x7f, 0xb1, 0xff,
+	0xff, 0xff, 0xff, 0xdf, 0xfd,
+	0xff, 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0x80, 0xff,
+	0xf0, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x2f, 0x71,
+	0xc1, 0x7f, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xbf,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xd1,
+	0x9f, 0xff, 0x7b, 0xb7, 0xff,
+	0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xfe, 0x8f, 0xff, 0xf1, 0xff, 0xff,
+	0xff, 0xff, 0xbf, 0xb7, 0xff,
+	0xff, 0xa4, 0xf7, 0x88, 0xff, 0xf0, 0xaf, 0xbf,
+	0xfb, 0xef, 0xff, 0xf7, 0xff, 0x8f, 0x7f, 0xf1,
+	0xff, 0xdd, 0xf7, 0x97, 0x7f,
+	0xff, 0xff, 0xf7, 0xff, 0x8f, 0xff, 0xf0, 0xff,
+	0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xf7, 0xaf, 0x0f, 0xa0, 0xf0,
+	0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f,
+	0x71, 0xb1, 0x37, 0xf7, 0xff,
+	0xff, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf0, 0xfe, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x7f,
+	0xbf, 0xff, 0xf8, 0xf7, 0xff, 0xa7, 0xff, 0xf0,
+	0xff, 0xff, 0x8f, 0xfe, 0xf0, 0xff, 0xff, 0x8f,
+	0x7f, 0xf1, 0xff, 0xff, 0xcf,
+	0xff, 0xff, 0xf7, 0x9f, 0xf7, 0xf3, 0xff, 0xff,
+	0xff, 0xff, 0x7f, 0xff, 0xff, 0xbf, 0x7f, 0xf9,
+	0xff, 0xfe, 0xff, 0xff, 0xdf,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f,
+	0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xbf, 0xbf,
+	0xff, 0xff, 0xff, 0xaf, 0xff, 0xf0, 0xff, 0xff,
+	0x9f, 0xfe, 0xf1, 0xff, 0xff, 0xcf, 0x7f, 0xf1,
+	0xff, 0xff, 0xdf, 0xff, 0xf1,
+	0xbf, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf0, 0xbf, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0x6f,
+	0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xbf,
+	0xff, 0xf8, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xcf, 0xff,
+	0xff, 0xd8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0x8f, 0x3f,
+	0xff, 0xdf, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff,
+	0xff, 0xff, 0xff, 0xef, 0xff, 0xdf, 0x8e, 0x7f,
+	0xf1, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xbf, 0xbf, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xe1, 0xff,
+	0xdf, 0xff, 0x7f, 0xff, 0xbf,
+	0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff,
+	0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xb1,
+	0xff, 0xef, 0xff, 0x7f, 0xff,
diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c
new file mode 100755
index 0000000..867589f
--- /dev/null
+++ b/board/sixnet/sixnet.c
@@ -0,0 +1,603 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Dave Ellis, SIXNET, dge@sixnetio.com.
+ *  Based on code by:
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * and other contributors to U-Boot. See file CREDITS for list
+ * of people who contributed to this  project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <jffs2/jffs2.h>
+#include <mpc8xx.h>
+#include <net.h>	/* for eth_init() */
+#include <rtc.h>
+#include "sixnet.h"
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+#endif
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+static long ram_size(ulong *, long);
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress (int status)
+{
+#if defined(CONFIG_STATUS_LED)
+# if defined(STATUS_LED_BOOT)
+	if (status == 15) {
+		/* ready to transfer to kernel, make sure LED is proper state */
+		status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
+	}
+# endif /* STATUS_LED_BOOT */
+#endif /* CONFIG_STATUS_LED */
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ * returns 0 if recognized, -1 if unknown
+ */
+
+int checkboard (void)
+{
+	puts ("Board: SIXNET SXNI855T\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#error "SXNI855T has no PCMCIA port"
+#endif	/* CFG_CMD_PCMCIA */
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_ 0xffffffff
+
+/* UPMB table for dual UART. */
+
+/* this table is for 50MHz operation, it should work at all lower speeds */
+const uint duart_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
+	0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
+
+	/* burst read. (offset 8 in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
+	0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
+
+	/* burst write. (offset 20 in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	_not_used_, _not_used_, _not_used_, _not_used_,
+};
+
+/* Load FPGA very early in boot sequence, since it must be
+ * loaded before the 16C2550 serial channels can be used as
+ * console channels.
+ *
+ * Note: Much of the configuration is not complete. The
+ *       stack is in DPRAM since SDRAM has not been initialized,
+ *       so the stack must be kept small. Global variables
+ *       are still in FLASH, so they cannot be written.
+ *	 Only the FLASH, DPRAM, immap and FPGA can be addressed,
+ *       the other chip selects may not have been initialized.
+ *       The clocks have been initialized, so udelay() can be
+ *       used.
+ */
+#define FPGA_DONE	0x0080	/* PA8, input, high when FPGA load complete */
+#define FPGA_PROGRAM_L	0x0040	/* PA9, output, low to reset, high to start */
+#define FPGA_INIT_L	0x0020	/* PA10, input, low indicates not ready	*/
+#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG))	/* FPGA port */
+
+int board_postclk_init (void)
+{
+
+	/* the data to load to the XCSxxXL FPGA */
+	static const unsigned char fpgadata[] = {
+# include "fpgadata.c"
+	};
+
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+#define porta (immap->im_ioport.iop_padat)
+	const unsigned char* pdata;
+
+	/* /INITFPGA and DONEFPGA signals are inputs */
+	immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
+
+	/* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
+	porta &= ~FPGA_PROGRAM_L;
+
+	/* Set FPGA as an output */
+	immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
+
+	/* delay a little to make sure FPGA sees it, really
+	 * only need less than a microsecond.
+	 */
+	udelay(10);
+
+	/* unassert /PROGRAM */
+	porta |= FPGA_PROGRAM_L;
+
+	/* delay while FPGA does last erase, indicated by
+	 * /INITFPGA going high. This should happen within a
+	 * few milliseconds.
+	 */
+	/* ### FIXME - a timeout check would be good, maybe flash
+	 * the status LED to indicate the error?
+	 */
+	while ((porta & FPGA_INIT_L) == 0)
+		; /* waiting */
+
+	/* write program data to FPGA at the programming address
+	 * so extra /CS1 strobes at end of configuration don't actually
+	 * write to any registers.
+	 */
+	fpga = 0xff;		/* first write is ignored	*/
+	fpga = 0xff;		/* fill byte			*/
+	fpga = 0xff;		/* fill byte			*/
+	fpga = 0x4f;		/* preamble code		*/
+	fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
+	fpga = 0x4b;		/* field check code */
+
+	pdata = fpgadata;
+	/* while no error write out each of the 28 byte frames */
+	while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
+	       && pdata < fpgadata + sizeof(fpgadata)) {
+
+		fpga = 0x4f;	/* preamble code */
+
+		/* 21 bytes of data in a frame */
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++); fpga = *(pdata++);
+		fpga = *(pdata++);
+
+		fpga = 0x4b;	/* field check code		*/
+		fpga = 0xff;	/* extended write cycle		*/
+		fpga = 0x4b;	/* extended write cycle
+				 * (actually 0x4b from bitgen.exe)
+				 */
+		fpga = 0xff;	/* extended write cycle		*/
+		fpga = 0xff;	/* extended write cycle		*/
+		fpga = 0xff;	/* extended write cycle		*/
+	}
+
+	fpga = 0xff;		/* startup byte			*/
+	fpga = 0xff;		/* startup byte			*/
+	fpga = 0xff;		/* startup byte			*/
+	fpga = 0xff;		/* startup byte			*/
+
+#if 0 /* ### FIXME */
+	/* If didn't load all the data or FPGA_DONE is low the load failed.
+	 * Maybe someday stop here and flash the status LED? The console
+	 * is not configured, so can't print an error message. Can't write
+	 * global variables to set a flag (except gd?).
+	 * For now it must work.
+	 */
+#endif
+
+	/* Now that the FPGA is loaded, set up the Dual UART chip
+	 * selects. Must be done here since it may be used as the console.
+	 */
+	upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
+
+	memctl->memc_mbmr = DUART_MBMR;
+	memctl->memc_or5 = DUART_OR_VALUE;
+	memctl->memc_br5 = DUART_BR5_VALUE;
+	memctl->memc_or6 = DUART_OR_VALUE;
+	memctl->memc_br6 = DUART_BR6_VALUE;
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* base address for SRAM, assume 32-bit port,  valid */
+#define NVRAM_BR_VALUE   (CFG_SRAM_BASE | BR_PS_32 | BR_V)
+
+/*  up to 64MB - will be adjusted for actual size */
+#define NVRAM_OR_PRELIM  (ORMASK(CFG_SRAM_SIZE) \
+	| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
+/*
+ * Miscellaneous platform dependent initializations after running in RAM.
+ */
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	char* s;
+	char* e;
+	int reg;
+	bd_t *bd = gd->bd;
+
+	memctl->memc_or2 = NVRAM_OR_PRELIM;
+	memctl->memc_br2 = NVRAM_BR_VALUE;
+
+	/* Is there any SRAM? Is it 16 or 32 bits wide? */
+
+	/* First look for 32-bit SRAM */
+	bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+
+	if (bd->bi_sramsize == 0) {
+	    /* no 32-bit SRAM, but there could be 16-bit SRAM since
+	     * it would report size 0 when configured for 32-bit bus.
+	     * Try again with a 16-bit bus.
+	     */
+	    memctl->memc_br2 |= BR_PS_16;
+	    bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+	}
+
+	if (bd->bi_sramsize == 0) {
+	    memctl->memc_br2 = 0;	/* disable select since nothing there */
+	}
+	else {
+	    /* adjust or2 for actual size of SRAM */
+	    memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
+	    bd->bi_sramstart = CFG_SRAM_BASE;
+	    printf("SRAM:  %lu KB\n", bd->bi_sramsize >> 10);
+	}
+
+
+	/* set standard MPC8xx clock so kernel will see the time
+	 * even if it doesn't have a DS1306 clock driver.
+	 * This helps with experimenting with standard kernels.
+	 */
+	{
+	    ulong tim;
+	    struct rtc_time tmp;
+
+	    rtc_get(&tmp);	/* get time from DS1306 RTC */
+
+	    /* convert to seconds since 1970 */
+	    tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+			 tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
+
+	    immap->im_sitk.sitk_rtck = KAPWR_KEY;
+	    immap->im_sit.sit_rtc = tim;
+	}
+
+	/* set up ethernet address for SCC ethernet. If eth1addr
+	 * is present it gets a unique address, otherwise it
+	 * shares the FEC address.
+	 */
+	s = getenv("eth1addr");
+	if (s == NULL)
+		s = getenv("ethaddr");
+	for (reg=0; reg<6; ++reg) {
+		bd->bi_enet1addr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
+		if (s)
+			s = (*e) ? e+1 : e;
+	}
+
+	return (0);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_init(void)
+{
+	unsigned long totlen = nand_probe(CFG_DFLASH_BASE);
+
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'.
+ *
+ * The memory size MUST be a power of 2 for this to work.
+ *
+ * The only memory modified is 8 bytes at offset 0. This is important
+ * since for the SRAM this location is reserved for autosizing, so if
+ * it is modified and the board is reset before ram_size() completes
+ * no damage is  done. Normally even the memory at 0 is preserved. The
+ * higher SRAM addresses may contain battery backed RAM disk data which
+ * must never be corrupted.
+ */
+
+static long ram_size(ulong *base, long maxsize)
+{
+    volatile long	*test_addr;
+    volatile ulong	*base_addr = base;
+    ulong		ofs;		/* byte offset from base_addr */
+    ulong		save;		/* to make test non-destructive */
+    ulong		save2;		/* to make test non-destructive */
+    long		ramsize = -1;	/* size not determined yet */
+
+    save = *base_addr;		/* save value at 0 so can restore */
+    save2 = *(base_addr+1);	/* save value at 4 so can restore */
+
+    /* is any SRAM present? */
+    *base_addr = 0x5555aaaa;
+
+    /* It is important to drive the data bus with different data so
+     * it doesn't remember the value and look like RAM that isn't there.
+     */
+    *(base_addr + 1) = 0xaaaa5555;	/* use write to modify data bus */
+
+    if (*base_addr != 0x5555aaaa)
+	ramsize = 0;		/* no RAM present, or defective */
+    else {
+	*base_addr = 0xaaaa5555;
+	*(base_addr + 1) = 0x5555aaaa;	/* use write to modify data bus */
+	if (*base_addr != 0xaaaa5555)
+	    ramsize = 0;	/* no RAM present, or defective */
+    }
+
+    /* now size it if any is present */
+    for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
+	test_addr = (long*)((long)base_addr + ofs);	/* location to test */
+
+	*base_addr = ~*test_addr;
+	if (*base_addr == *test_addr)
+	    ramsize = ofs;	/* wrapped back to 0, so this is the size */
+    }
+
+    *base_addr = save;		/* restore value at 0 */
+    *(base_addr+1) = save2;	/* restore value at 4 */
+    return (ramsize);
+}
+
+/* ------------------------------------------------------------------------- */
+/* sdram table based on the FADS manual                                      */
+/* for chip MB811171622A-100                                                 */
+
+/* this table is for 50MHz operation, it should work at all lower speeds */
+
+const uint sdram_table[] =
+{
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* precharge and Mode Register Set initialization (offset 5).
+	 * This is also entered at offset 6 to do Mode Register Set
+	 * without the precharge.
+	 */
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	/* FADS had 0x1f27fc04, ...
+	 * but most other boards have 0x1f07fc04, which
+	 * sets GPL0 from A11MPC to 0 1/4 clock earlier,
+	 * like the single read.
+	 * This seems better so I am going with the change.
+	 */
+	0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_ };
+
+/* ------------------------------------------------------------------------- */
+
+#define	SDRAM_MAX_SIZE		0x10000000	/* max 256 MB SDRAM */
+
+/* precharge and set Mode Register */
+#define SDRAM_MCR_PRE    (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
+			  MCR_MB_CS3 |			/* chip select    */ \
+			  MCR_MLCF(1) | MCR_MAD(5))	/* 1 time at 0x05 */
+
+/* set Mode Register, no precharge */
+#define SDRAM_MCR_MRS    (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
+			  MCR_MB_CS3 |			/* chip select    */ \
+			  MCR_MLCF(1) | MCR_MAD(6))	/* 1 time at 0x06 */
+
+/* runs refresh loop twice so get 8 refresh cycles */
+#define SDRAM_MCR_REFR   (MCR_OP_RUN | MCR_UPM_A |	/* select UPM     */ \
+			  MCR_MB_CS3 |			/* chip select    */ \
+			  MCR_MLCF(2) | MCR_MAD(0x30))	/* twice at 0x30  */
+
+/* MAMR values work in either mamr or mbmr */
+#define SDRAM_MAMR_BASE  /* refresh at 50MHz */				  \
+			 ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE		  \
+			 | MAMR_DSA_1_CYCL	/* 1 cycle disable */	  \
+			 | MAMR_RLFA_1X		/* Read loop 1 time */	  \
+			 | MAMR_WLFA_1X		/* Write loop 1 time */	  \
+			 | MAMR_TLFA_4X)	/* Timer loop 4 times */
+/* 8 column SDRAM */
+#define SDRAM_MAMR_8COL	(SDRAM_MAMR_BASE				  \
+			 | MAMR_AMA_TYPE_0	/* Address MUX 0 */	  \
+			 | MAMR_G0CLA_A11)	/* GPL0 A11[MPC] */
+
+/* 9 column SDRAM */
+#define SDRAM_MAMR_9COL	(SDRAM_MAMR_BASE				  \
+			 | MAMR_AMA_TYPE_1	/* Address MUX 1 */	  \
+			 | MAMR_G0CLA_A10)	/* GPL0 A10[MPC] */
+
+/* base address 0, 32-bit port, SDRAM UPM, valid */
+#define SDRAM_BR_VALUE   (BR_PS_32 | BR_MS_UPMA | BR_V)
+
+/*  up to 256MB, SAM, G5LS - will be adjusted for actual size */
+#define SDRAM_OR_PRELIM  (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
+
+/* This is the Mode Select Register value for the SDRAM.
+ * Burst length: 4
+ * Burst Type: sequential
+ * CAS Latency: 2
+ * Write Burst Length: burst
+ */
+#define SDRAM_MODE   0x22	/* CAS latency 2, burst length 4 */
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram(int board_type)
+{
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	uint size_sdram = 0;
+	uint size_sdram9 = 0;
+	uint base = 0;		/* SDRAM must start at 0 */
+	int i;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Configure the refresh (mostly).  This needs to be
+	 * based upon processor clock speed and optimized to provide
+	 * the highest level of performance.
+	 *
+	 * Preliminary prescaler for refresh.
+	 * This value is selected for four cycles in 31.2 us,
+	 * which gives 8192 cycles in 64 milliseconds.
+	 * This may be too fast, but works for any memory.
+	 * It is adjusted to 4096 cycles in 64 milliseconds if
+	 * possible once we know what memory we have.
+	 *
+	 * We have to be careful changing UPM registers after we
+	 * ask it to run these commands.
+	 *
+	 * PTA - periodic timer period for our design is
+	 *       50 MHz x 31.2us
+	 *       ---------------  = 195
+	 *       1 x 8 x 1
+	 *
+	 *    50MHz clock
+	 *    31.2us refresh interval
+	 *    SCCR[DFBRG] 0
+	 *    PTP divide by 8
+	 *    1 chip select
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;	/* 0x0800 */
+	memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
+
+	/* The SDRAM Mode Register value is shifted left 2 bits since
+	 * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
+	 */
+	memctl->memc_mar = SDRAM_MODE << 2;	/* MRS code */
+	udelay(200);		/* SDRAM needs 200uS before set it up */
+
+	/* Now run the precharge/nop/mrs commands. */
+	memctl->memc_mcr = SDRAM_MCR_PRE;
+	udelay(2);
+
+	/* Run 8 refresh cycles (2 sets of 4) */
+	memctl->memc_mcr = SDRAM_MCR_REFR;	/* run refresh twice */
+	udelay(2);
+
+	/* some brands want Mode Register set after the refresh
+	 * cycles. This shouldn't hurt anything for the brands
+	 * that were happy with the first time we set it.
+	 */
+	memctl->memc_mcr = SDRAM_MCR_MRS;
+	udelay(2);
+
+	memctl->memc_mamr = SDRAM_MAMR_8COL;	/* enable refresh */
+	memctl->memc_or3 = SDRAM_OR_PRELIM;
+	memctl->memc_br3 = SDRAM_BR_VALUE + base;
+
+	/* Some brands need at least 10 DRAM accesses to stabilize.
+	 * It wont hurt the brands that don't.
+	 */
+	for (i=0; i<10; ++i) {
+		volatile ulong *addr = (volatile ulong *)base;
+		ulong val;
+
+		val = *(addr + i);
+		*(addr + i) = val;
+	}
+
+	/* Check SDRAM memory Size in 8 column mode.
+	 * For a 9 column memory we will get half the actual size.
+	 */
+	size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
+
+	/* Check SDRAM memory Size in 9 column mode.
+	 * For an 8 column memory we will see at most 4 megabytes.
+	 */
+	memctl->memc_mamr = SDRAM_MAMR_9COL;
+	size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
+
+	if (size_sdram < size_sdram9)	/* leave configuration at 9 columns */
+		size_sdram = size_sdram9;
+	else				/* go back to 8 columns */
+		memctl->memc_mamr = SDRAM_MAMR_8COL;
+
+	/* adjust or3 for actual size of SDRAM
+	 */
+	memctl->memc_or3 |= ORMASK(size_sdram);
+
+	/* Adjust refresh rate depending on SDRAM type.
+	 * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
+	 * it at the current (fast) rate.
+	 * For 16, 64 and 128 MBit half the rate will do.
+	 */
+	if (size_sdram <= 32 * 1024 * 1024)
+		memctl->memc_mptpr = MPTPR_PTP_DIV16;	/* 0x0400 */
+
+	return (size_sdram);
+}
diff --git a/board/sixnet/sixnet.h b/board/sixnet/sixnet.h
new file mode 100755
index 0000000..e631874
--- /dev/null
+++ b/board/sixnet/sixnet.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Memory map:
+ *
+ *   ff100000 -> ff13ffff : FPGA        CS1
+ *   ff030000 -> ff03ffff : EXPANSION   CS7
+ *   ff020000 -> ff02ffff : DATA FLASH  CS4
+ *   ff018000 -> ff01ffff : UART B      CS6/UPMB
+ *   ff010000 -> ff017fff : UART A      CS5/UPMB
+ *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
+ *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
+ *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
+ *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
+ */
diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds
new file mode 100755
index 0000000..1513a85
--- /dev/null
+++ b/board/sixnet/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    common/environment.o(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sl8245/Makefile b/board/sl8245/Makefile
new file mode 100755
index 0000000..6d11240
--- /dev/null
+++ b/board/sl8245/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001 - 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS 	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/sl8245/config.mk b/board/sl8245/config.mk
new file mode 100755
index 0000000..022512b
--- /dev/null
+++ b/board/sl8245/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2001 - 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# SL8245 board
+#
+
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
+PLATFORM_LIBS += $(shell $(CC) -print-libgcc-file-name)
diff --git a/board/sl8245/flash.c b/board/sl8245/flash.c
new file mode 100755
index 0000000..553dc98
--- /dev/null
+++ b/board/sl8245/flash.c
@@ -0,0 +1,488 @@
+/*
+ * (C) Copyright 2001 - 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#define FLASH_BANK_SIZE 0x800000
+#define MAIN_SECT_SIZE  0x40000
+#define PARAM_SECT1_SIZE 0x20000
+#define PARAM_SECT23_SIZE 0x8000
+#define PARAM_SECT4_SIZE 0x10000
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+static int write_data (flash_info_t *info, ulong dest, ulong *data);
+static void write_via_fpu(vu_long *addr, ulong *data);
+static __inline__ unsigned long get_msr(void);
+static __inline__ void set_msr(unsigned long msr);
+
+/*---------------------------------------------------------------------*/
+#undef	DEBUG_FLASH
+
+/*---------------------------------------------------------------------*/
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+#define __align__ __attribute__ ((aligned (8)))
+static __align__ ulong precmd0[2]   = { 0x00aa00aa, 0x00aa00aa };
+static __align__ ulong precmd1[2]   = { 0x00550055, 0x00550055 };
+static __align__ ulong cmdid[2]     = { 0x00900090, 0x00900090 };
+static __align__ ulong cmderase[2]  = { 0x00800080, 0x00800080 };
+static __align__ ulong cmdersusp[2] = { 0x00b000b0, 0x00b000b0 };
+static __align__ ulong cmdsecter[2] = { 0x00300030, 0x00300030 };
+static __align__ ulong cmdprog[2]   = { 0x00a000a0, 0x00a000a0 };
+static __align__ ulong cmdres[2]    = { 0x00f000f0, 0x00f000f0 };
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+		write_via_fpu (&addr[0xaaa], precmd0);
+		write_via_fpu (&addr[0x554], precmd1);
+		write_via_fpu (&addr[0xaaa], cmdid);
+
+		DEBUGF ("Flash bank # %d:\n"
+			"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+			"\tDevice ID @ 0x%08lX: 0x%08lX\n",
+			i,
+			(ulong) (&addr[0]), addr[0],
+			(ulong) (&addr[2]), addr[2]);
+
+		if ((addr[0] == addr[1]) && (addr[0] == AMD_MANUFACT) &&
+			(addr[2] == addr[3]) && (addr[2] == AMD_ID_LV160T)) {
+			flash_info[i].flash_id = (FLASH_MAN_AMD & FLASH_VENDMASK) |
+					(FLASH_AM160T & FLASH_TYPEMASK);
+		} else {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			write_via_fpu (addr, cmdres);
+			goto Done;
+		}
+
+		DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+		write_via_fpu (addr, cmdres);
+
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		for (j = 0; j < 32; j++) {
+			flash_info[i].start[j] = CFG_FLASH_BASE +
+					i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE;
+		}
+		flash_info[i].start[32] =
+				flash_info[i].start[31] + PARAM_SECT1_SIZE;
+		flash_info[i].start[33] =
+				flash_info[i].start[32] + PARAM_SECT23_SIZE;
+		flash_info[i].start[34] =
+				flash_info[i].start[33] + PARAM_SECT23_SIZE;
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_MONITOR_BASE,
+			CFG_MONITOR_BASE + monitor_flash_len - 1,
+			&flash_info[1]);
+#else
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_MONITOR_BASE,
+			CFG_MONITOR_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+#endif
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
+#else
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+#endif
+
+Done:
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch ((i = info->flash_id & FLASH_VENDMASK)) {
+	case (FLASH_MAN_AMD & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor 0x%04x ", i);
+		break;
+	}
+
+	switch ((i = info->flash_id & FLASH_TYPEMASK)) {
+	case (FLASH_AM160T & FLASH_TYPEMASK):
+		printf ("AM29LV160BT (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type 0x%04x\n", i);
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+  Done:
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	DEBUGF ("Erase flash bank %d sect %d ... %d\n",
+		info - &flash_info[0], s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(FLASH_MAN_AMD & FLASH_VENDMASK)) {
+		printf ("Can erase only AMD flash types - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+
+			DEBUGF ("Erase sect %d @ 0x%08lX\n", sect, (ulong) addr);
+
+			/* Disable interrupts which might cause a timeout
+			 * here.
+			 */
+			flag = disable_interrupts ();
+
+			write_via_fpu (&addr[0xaaa], precmd0);
+			write_via_fpu (&addr[0x554], precmd1);
+			write_via_fpu (&addr[0xaaa], cmderase);
+			write_via_fpu (&addr[0xaaa], precmd0);
+			write_via_fpu (&addr[0x554], precmd1);
+			write_via_fpu (&addr[0xaaa], cmdsecter);
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((addr[0] & 0x00800080) != 0x00800080) ||
+				   ((addr[1] & 0x00800080) != 0x00800080)) {
+				if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					write_via_fpu (addr, cmdersusp);
+					write_via_fpu (addr, cmdres);
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second  */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			write_via_fpu (addr, cmdres);
+		}
+	}
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+#define	FLASH_WIDTH	8		/* flash bus width in bytes */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, cp, msr;
+	int l, rc, i;
+	ulong data[2];
+	ulong *datah = &data[0];
+	ulong *datal = &data[1];
+
+	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
+		addr, (ulong) src, cnt);
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	msr = get_msr ();
+	set_msr (msr | MSR_FP);
+
+	wp = (addr & ~(FLASH_WIDTH - 1));	/* get lower aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		*datah = *datal = 0;
+
+		for (i = 0, cp = wp; i < l; i++, cp++) {
+			if (i >= 4) {
+				*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | (*(uchar *) cp);
+		}
+		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
+			char tmp;
+
+			tmp = *src;
+
+			src++;
+
+			if (i >= 4) {
+				*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datal << 8) | tmp;
+
+			--cnt;
+			++cp;
+		}
+
+		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
+			if (i >= 4) {
+				*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+			}
+
+			*datal = (*datah << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
+			return (rc);
+		}
+
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		*datah = *(ulong *) src;
+		*datal = *(ulong *) (src + 4);
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+		src += FLASH_WIDTH;
+	}
+
+	if (cnt == 0) {
+		set_msr (msr);
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	*datah = *datal = 0;
+	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
+		char tmp;
+
+		tmp = *src;
+
+		src++;
+
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+		}
+
+		*datal = (*datal << 8) | tmp;
+
+		--cnt;
+	}
+
+	for (; i < FLASH_WIDTH; ++i, ++cp) {
+		if (i >= 4) {
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+		}
+
+		*datal = (*datal << 8) | (*(uchar *) cp);
+	}
+
+	rc = write_data (info, wp, data);
+	set_msr (msr);
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, ulong * data)
+{
+	vu_long *chip = (vu_long *) (info->start[0]);
+	vu_long *addr = (vu_long *) dest;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if (((addr[0] & data[0]) != data[0]) ||
+		((addr[1] & data[1]) != data[1])) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	write_via_fpu (&chip[0xaaa], precmd0);
+	write_via_fpu (&chip[0x554], precmd1);
+	write_via_fpu (&chip[0xaaa], cmdprog);
+	write_via_fpu (addr, data);
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((addr[0] & 0x00800080) != (data[0] & 0x00800080)) ||
+	       ((addr[1] & 0x00800080) != (data[1] & 0x00800080))) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			write_via_fpu (chip, cmdres);
+			return (1);
+		}
+	}
+
+	write_via_fpu (chip, cmdres);
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu (vu_long * addr, ulong * data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
+}
+
+/*-----------------------------------------------------------------------
+ */
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+
+	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+}
diff --git a/board/sl8245/sl8245.c b/board/sl8245/sl8245.c
new file mode 100755
index 0000000..593eb4e
--- /dev/null
+++ b/board/sl8245/sl8245.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+int checkboard (void)
+{
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	printf("Board: SL8245, local bus @ %s MHz\n", strmhz(buf, busfreq));
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+#ifndef CFG_RAMBOOT
+	long size;
+	long new_bank0_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+	mear1 = (mear1  & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+	emear1 = (emear1 & 0xFFFFFF00) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+#else
+	return CFG_MAX_RAM_SIZE;
+#endif
+}
+
+static struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
diff --git a/board/sl8245/u-boot.lds b/board/sl8245/u-boot.lds
new file mode 100755
index 0000000..acb9ffd
--- /dev/null
+++ b/board/sl8245/u-boot.lds
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/smdk2400/Makefile b/board/smdk2400/Makefile
new file mode 100755
index 0000000..fc3d48f
--- /dev/null
+++ b/board/smdk2400/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= smdk2400.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/smdk2400/config.mk b/board/smdk2400/config.mk
new file mode 100755
index 0000000..82400bf
--- /dev/null
+++ b/board/smdk2400/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# SAMSUNG board with S3C2400X (ARM920T) CPU
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# SAMSUNG has 1 bank of 32 MB DRAM
+#
+# 0C00'0000 to 0E00'0000
+#
+# Linux-Kernel is expected to be at 0cf0'0000, entry 0cf0'0000
+# optionally with a ramdisk at 0c80'0000
+#
+# we load ourself to 0CF80000 (must be high enough not to be
+# overwritten by the uncompessing Linux kernel)
+#
+# download area is 0C80'0000
+#
+
+
+TEXT_BASE = 0x0CF80000
diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c
new file mode 100755
index 0000000..a108af7
--- /dev/null
+++ b/board/smdk2400/flash.c
@@ -0,0 +1,491 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <environment.h>
+
+#define FLASH_BANK_SIZE 0x1000000	/* 2 x   8 MB */
+#define MAIN_SECT_SIZE  0x40000		/* 2 x 128 kB */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00FF00FF
+#define CMD_IDENTIFY		0x00900090
+#define CMD_ERASE_SETUP		0x00200020
+#define CMD_ERASE_CONFIRM	0x00D000D0
+#define CMD_PROGRAM		0x00400040
+#define CMD_RESUME		0x00D000D0
+#define CMD_SUSPEND		0x00B000B0
+#define CMD_STATUS_READ		0x00700070
+#define CMD_STATUS_RESET	0x00500050
+
+#define BIT_BUSY		0x00800080
+#define BIT_ERASE_SUSPEND	0x00400040
+#define BIT_ERASE_ERROR		0x00200020
+#define BIT_PROGRAM_ERROR	0x00100010
+#define BIT_VPP_RANGE_ERROR	0x00080008
+#define BIT_PROGRAM_SUSPEND	0x00040004
+#define BIT_PROTECT_ERROR	0x00020002
+#define BIT_UNDEFINED		0x00010001
+
+#define BIT_SEQUENCE_ERROR	0x00300030
+#define BIT_TIMEOUT		0x80000000
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT     & FLASH_VENDMASK) |
+			(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = CFG_FLASH_BASE;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase;
+
+			/* uniform sector size */
+			flashbase += MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F640J3A & FLASH_TYPEMASK):
+		printf ("2x 28F640J3A (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_error (ulong code)
+{
+	/* Check bit patterns */
+	/* SR.7=0 is busy, SR.7=1 is ready */
+	/* all other flags indicate error on 1 */
+	/* SR.0 is undefined */
+	/* Timeout is our faked flag */
+
+	/* sequence is described in Intel 290644-005 document */
+
+	/* check Timeout */
+	if (code & BIT_TIMEOUT) {
+		puts ("Timeout\n");
+		return ERR_TIMOUT;
+	}
+
+	/* check Busy, SR.7 */
+	if (~code & BIT_BUSY) {
+		puts ("Busy\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Vpp low, SR.3 */
+	if (code & BIT_VPP_RANGE_ERROR) {
+		puts ("Vpp range error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Device Protect Error, SR.1 */
+	if (code & BIT_PROTECT_ERROR) {
+		puts ("Device protect error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Command Seq Error, SR.4 & SR.5 */
+	if (code & BIT_SEQUENCE_ERROR) {
+		puts ("Command seqence error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Error, SR.5 */
+	if (code & BIT_ERASE_ERROR) {
+		puts ("Block erase error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Error, SR.4 */
+	if (code & BIT_PROGRAM_ERROR) {
+		puts ("Program error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Suspended, SR.6 */
+	if (code & BIT_ERASE_SUSPEND) {
+		puts ("Block erase suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Suspended, SR.2 */
+	if (code & BIT_PROGRAM_SUSPEND) {
+		puts ("Program suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* OK, no error */
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result, result1;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	debug ("flash_erase: s_first %d  s_last %d\n", s_first, s_last);
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		debug ("Erasing sector %2d @ %08lX... ",
+			sect, info->start[sect]);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+			ulong bsR7, bsR7_2, bsR5, bsR5_2;
+
+			/* *addr = CMD_STATUS_RESET; */
+			*addr = CMD_ERASE_SETUP;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			do {
+				/* check timeout */
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					*addr = CMD_STATUS_RESET;
+					result = BIT_TIMEOUT;
+					break;
+				}
+
+				*addr = CMD_STATUS_READ;
+				result = *addr;
+				bsR7 = result & (1 << 7);
+				bsR7_2 = result & (1 << 23);
+			} while (!bsR7 | !bsR7_2);
+
+			*addr = CMD_STATUS_READ;
+			result1 = *addr;
+			bsR5 = result1 & (1 << 5);
+			bsR5_2 = result1 & (1 << 21);
+#ifdef SAMSUNG_FLASH_DEBUG
+			printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+			if (bsR5 != 0 && bsR5_2 != 0)
+				printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+#endif
+
+			*addr = CMD_READ_ARRAY;
+			*addr = CMD_RESUME;
+
+			if ((rc = flash_error (result)) != ERR_OK)
+				goto outahere;
+#if 0
+			printf ("ok.\n");
+		} else {		/* it was protected */
+
+			printf ("protected!\n");
+#endif
+		}
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t * info, ulong dest,
+								ulong data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* *addr = CMD_STATUS_RESET; */
+	*addr = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	do {
+		/* check timeout */
+		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+			*addr = CMD_SUSPEND;
+			result = BIT_TIMEOUT;
+			break;
+		}
+
+		*addr = CMD_STATUS_READ;
+		result = *addr;
+	} while (~result & BIT_BUSY);
+
+	/* *addr = CMD_READ_ARRAY; */
+	*addr = CMD_STATUS_READ;
+	result = *addr;
+
+	rc = flash_error (result);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	*addr = CMD_READ_ARRAY;
+	*addr = CMD_RESUME;
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);			/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 4;
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 24);
+	}
+
+	return write_word (info, wp, data);
+}
diff --git a/board/smdk2400/lowlevel_init.S b/board/smdk2400/lowlevel_init.S
new file mode 100755
index 0000000..a5de806
--- /dev/null
+++ b/board/smdk2400/lowlevel_init.S
@@ -0,0 +1,163 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung development board by
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S
+ *
+ * Copyright (C) 2001 Samsung Electronics by chc, 010406
+ *
+ * S3C2400 specific tweaks.
+ *
+ */
+
+/* memory controller */
+#define BWSCON 0x14000000
+#define BANKCON3 0x14000010	/* for cs8900, ethernet */
+
+/* Bank0 */
+#define B0_Tacs	0x0	/* 0 clk */
+#define B0_Tcos	0x0	/* 0 clk */
+#define B0_Tacc	0x7	/* 14 clk */
+#define B0_Tcoh	0x0	/* 0 clk */
+#define B0_Tah	0x0	/* 0 clk */
+#define B0_Tacp	0x0
+#define B0_PMC	0x0	/* normal */
+
+/* Bank1 */
+#define B1_Tacs	0x0	/* 0 clk */
+#define B1_Tcos	0x0	/* 0 clk */
+#define B1_Tacc	0x7	/* 14 clk */
+#define B1_Tcoh	0x0	/* 0 clk */
+#define B1_Tah	0x0	/* 0 clk */
+#define B1_Tacp	0x0
+#define B1_PMC	0x0	/* normal */
+
+/* Bank2 */
+#define B2_Tacs	0x0	/* 0 clk */
+#define B2_Tcos	0x0	/* 0 clk */
+#define B2_Tacc	0x7	/* 14 clk */
+#define B2_Tcoh	0x0	/* 0 clk */
+#define B2_Tah	0x0	/* 0 clk */
+#define B2_Tacp	0x0
+#define B2_PMC	0x0	/* normal */
+
+/* Bank3 - setup for the cs8900 */
+#define B3_Tacs	0x0	/* 0 clk */
+#define B3_Tcos	0x3	/* 4 clk */
+#define B3_Tacc	0x7	/* 14 clk */
+#define B3_Tcoh	0x1	/* 1 clk */
+#define B3_Tah	0x0	/* 0 clk */
+#define B3_Tacp	0x3	/* 6 clk */
+#define B3_PMC	0x0	/* normal */
+
+/* Bank4 */
+#define B4_Tacs	0x0	/* 0 clk */
+#define B4_Tcos	0x0	/* 0 clk */
+#define B4_Tacc	0x7	/* 14 clk */
+#define B4_Tcoh	0x0	/* 0 clk */
+#define B4_Tah	0x0	/* 0 clk */
+#define B4_Tacp	0x0
+#define B4_PMC	0x0	/* normal */
+
+/* Bank5 */
+#define B5_Tacs	0x0	/* 0 clk */
+#define B5_Tcos	0x0	/* 0 clk */
+#define B5_Tacc	0x7	/* 14 clk */
+#define B5_Tcoh	0x0	/* 0 clk */
+#define B5_Tah	0x0	/* 0 clk */
+#define B5_Tacp	0x0
+#define B5_PMC	0x0	/* normal */
+
+/* Bank6 */
+#define	B6_MT	0x3	/* SDRAM */
+#define	B6_Trcd	0x1	/* 3clk */
+#define	B6_SCAN	0x1	/* 9 bit */
+
+/* Bank7 */
+#define	B7_MT	0x3	/* SDRAM */
+#define	B7_Trcd	0x1	/* 3clk */
+#define	B7_SCAN	0x1	/* 9 bit */
+
+/* refresh parameter */
+#define REFEN	0x1	/* enable refresh */
+#define TREFMD	0x0	/* CBR(CAS before RAS)/auto refresh */
+#define Trp	0x0	/* 2 clk */
+#define Trc	0x3	/* 7 clk */
+#define Tchr	0x2 	/* 3 clk */
+
+#define REFCNT	1113	/* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #52
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+SMRDATA:
+	.word	0x2211d114	/* d->Ethernet, BUSWIDTH=32 */
+	.word	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
+	.word	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
+	.word	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
+	.word	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
+	.word	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
+	.word	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
+	.word	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
+	.word	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
+	.word	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+	.word	0x10	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
+	.word	0x30	/* MRSR6, CL=3clk */
+	.word	0x30	/* MRSR7 */
diff --git a/board/smdk2400/smdk2400.c b/board/smdk2400/smdk2400.c
new file mode 100755
index 0000000..cb70218
--- /dev/null
+++ b/board/smdk2400/smdk2400.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2400.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void);
+int mdm_init (bd_t *);
+extern void disable_putc(void);
+extern void enable_putc(void);
+extern int hwflow_onoff(int);
+extern int do_mdm_init; /* defined in common/main.c */
+#endif /* CONFIG_MODEM_SUPPORT */
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* change the clock to be 50 MHz 1:1:1 */
+	clk_power->MPLLCON = 0x5c042;
+	clk_power->CLKDIVN = 0;
+	/* set up the I/O ports */
+	gpio->PACON = 0x3ffff;
+	gpio->PBCON = 0xaaaaaaaa;
+	gpio->PBUP = 0xffff;
+	gpio->PECON = 0x0;
+	gpio->PEUP = 0x0;
+#ifdef CONFIG_HWFLOW
+	/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
+	/*   10,   10,   00,   00,    10,   00,    10 */
+	gpio->PFCON=0xa22;
+	/* Disable pull-up on Rx, Tx, CTS and RTS pins */
+	gpio->PFUP=0x35;
+#else
+	/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
+	/*   00,   00,   00,   00,    10,   00,    10 */
+	gpio->PFCON = 0x22;
+	/* Disable pull-up on Rx and Tx pins */
+	gpio->PFUP = 0x5;
+#endif	/* CONFIG_HWFLOW */
+	gpio->PGCON = 0x0;
+	gpio->PGUP = 0x0;
+	gpio->OPENCR = 0x0;
+
+	/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
+	gd->bd->bi_arch_number = MACH_TYPE_SMDK2400;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x0C000100;
+
+#ifdef CONFIG_MODEM_SUPPORT
+	if (key_pressed()) {
+		disable_putc();	/* modem doesn't understand banner etc */
+		do_mdm_init = 1;
+	}
+#endif	/* CONFIG_MODEM_SUPPORT */
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void)
+{
+	int rc;
+	if (1) {	/* check for button push here, now just return 1 */
+		rc = 1;
+	}
+
+	return rc;
+}
+#endif	/* CONFIG_MODEM_SUPPORT */
diff --git a/board/smdk2400/u-boot.lds b/board/smdk2400/u-boot.lds
new file mode 100755
index 0000000..f4fbf96
--- /dev/null
+++ b/board/smdk2400/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/smdk2410/Makefile b/board/smdk2410/Makefile
new file mode 100755
index 0000000..4ee21f5
--- /dev/null
+++ b/board/smdk2410/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= smdk2410.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/smdk2410/config.mk b/board/smdk2410/config.mk
new file mode 100755
index 0000000..1af85da
--- /dev/null
+++ b/board/smdk2410/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# SMDK2410 has 1 bank of 64 MB DRAM
+#
+# 3000'0000 to 3400'0000
+#
+# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
+# optionally with a ramdisk at 3080'0000
+#
+# we load ourself to 33F8'0000
+#
+# download area is 3300'0000
+#
+
+
+TEXT_BASE = 0x33F80000
diff --git a/board/smdk2410/flash.c b/board/smdk2410/flash.c
new file mode 100755
index 0000000..993946b
--- /dev/null
+++ b/board/smdk2410/flash.c
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+ulong myflush (void);
+
+
+#define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
+#define MAIN_SECT_SIZE  0x10000	/* 64 KB */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x000000F0
+#define CMD_UNLOCK1		0x000000AA
+#define CMD_UNLOCK2		0x00000055
+#define CMD_ERASE_SETUP		0x00000080
+#define CMD_ERASE_CONFIRM	0x00000030
+#define CMD_PROGRAM		0x000000A0
+#define CMD_UNLOCK_BYPASS	0x00000020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+
+#define BIT_ERASE_DONE		0x00000080
+#define BIT_RDY_MASK		0x00000080
+#define BIT_PROGRAM_ERROR	0x00000020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+#if defined(CONFIG_AMD_LV400)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV400B & FLASH_TYPEMASK);
+#elif defined(CONFIG_AMD_LV800)
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_LV800B & FLASH_TYPEMASK);
+#else
+#error "Unknown flash configured"
+#endif
+			flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j <= 3) {
+				/* 1st one is 16 KB */
+				if (j == 0) {
+					flash_info[i].start[j] =
+						flashbase + 0;
+				}
+
+				/* 2nd and 3rd are both 8 KB */
+				if ((j == 1) || (j == 2)) {
+					flash_info[i].start[j] =
+						flashbase + 0x4000 + (j -
+								      1) *
+						0x2000;
+				}
+
+				/* 4th 32 KB */
+				if (j == 3) {
+					flash_info[i].start[j] =
+						flashbase + 0x8000;
+				}
+			} else {
+				flash_info[i].start[j] =
+					flashbase + (j - 3) * MAIN_SECT_SIZE;
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_LV400B & FLASH_TYPEMASK):
+		printf ("1x Amd29LV400BB (4Mbit)\n");
+		break;
+	case (AMD_ID_LV800B & FLASH_TYPEMASK):
+		printf ("1x Amd29LV800BB (8Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+      Done:;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ushort result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_short *addr = (vu_short *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip = TMO;
+					break;
+				}
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip = READY;
+
+				if (!chip
+				    && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+					chip = ERR;
+
+			} while (!chip);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_hword (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) dest;
+	ushort result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+	*addr = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+			chip = ERR | TMO;
+			break;
+		}
+		if (!chip && ((result & 0x80) == (data & 0x80)))
+			chip = READY;
+
+		if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = *addr;
+
+			if ((result & 0x80) == (data & 0x80))
+				chip = READY;
+			else
+				chip = ERR;
+		}
+
+	} while (!chip);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	int l;
+	int i, rc;
+	ushort data;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 2) {
+		data = *((vu_short *) src);
+		if ((rc = write_hword (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_hword (info, wp, data);
+}
diff --git a/board/smdk2410/lowlevel_init.S b/board/smdk2410/lowlevel_init.S
new file mode 100755
index 0000000..310f2a0
--- /dev/null
+++ b/board/smdk2410/lowlevel_init.S
@@ -0,0 +1,167 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the Samsung SMDK2410 by
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
+ *
+ * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
+ *
+ */
+
+#define BWSCON	0x48000000
+
+/* BWSCON */
+#define DW8		 	(0x0)
+#define DW16		 	(0x1)
+#define DW32		 	(0x2)
+#define WAIT		 	(0x1<<2)
+#define UBLB		 	(0x1<<3)
+
+#define B1_BWSCON	  	(DW32)
+#define B2_BWSCON	  	(DW16)
+#define B3_BWSCON	  	(DW16 + WAIT + UBLB)
+#define B4_BWSCON	  	(DW16)
+#define B5_BWSCON	  	(DW16)
+#define B6_BWSCON	  	(DW32)
+#define B7_BWSCON	  	(DW32)
+
+/* BANK0CON */
+#define B0_Tacs		 	0x0	/*  0clk */
+#define B0_Tcos		 	0x0	/*  0clk */
+#define B0_Tacc		 	0x7	/* 14clk */
+#define B0_Tcoh		 	0x0	/*  0clk */
+#define B0_Tah		 	0x0	/*  0clk */
+#define B0_Tacp		 	0x0
+#define B0_PMC		 	0x0	/* normal */
+
+/* BANK1CON */
+#define B1_Tacs		 	0x0	/*  0clk */
+#define B1_Tcos		 	0x0	/*  0clk */
+#define B1_Tacc		 	0x7	/* 14clk */
+#define B1_Tcoh		 	0x0	/*  0clk */
+#define B1_Tah		 	0x0	/*  0clk */
+#define B1_Tacp		 	0x0
+#define B1_PMC		 	0x0
+
+#define B2_Tacs		 	0x0
+#define B2_Tcos		 	0x0
+#define B2_Tacc		 	0x7
+#define B2_Tcoh		 	0x0
+#define B2_Tah		 	0x0
+#define B2_Tacp		 	0x0
+#define B2_PMC		 	0x0
+
+#define B3_Tacs		 	0x0	/*  0clk */
+#define B3_Tcos		 	0x3	/*  4clk */
+#define B3_Tacc		 	0x7	/* 14clk */
+#define B3_Tcoh		 	0x1	/*  1clk */
+#define B3_Tah		 	0x0	/*  0clk */
+#define B3_Tacp		 	0x3     /*  6clk */
+#define B3_PMC		 	0x0	/* normal */
+
+#define B4_Tacs		 	0x0	/*  0clk */
+#define B4_Tcos		 	0x0	/*  0clk */
+#define B4_Tacc		 	0x7	/* 14clk */
+#define B4_Tcoh		 	0x0	/*  0clk */
+#define B4_Tah		 	0x0	/*  0clk */
+#define B4_Tacp		 	0x0
+#define B4_PMC		 	0x0	/* normal */
+
+#define B5_Tacs		 	0x0	/*  0clk */
+#define B5_Tcos		 	0x0	/*  0clk */
+#define B5_Tacc		 	0x7	/* 14clk */
+#define B5_Tcoh		 	0x0	/*  0clk */
+#define B5_Tah		 	0x0	/*  0clk */
+#define B5_Tacp		 	0x0
+#define B5_PMC		 	0x0	/* normal */
+
+#define B6_MT		 	0x3	/* SDRAM */
+#define B6_Trcd	 	 	0x1
+#define B6_SCAN		 	0x1	/* 9bit */
+
+#define B7_MT		 	0x3	/* SDRAM */
+#define B7_Trcd		 	0x1	/* 3clk */
+#define B7_SCAN		 	0x1	/* 9bit */
+
+/* REFRESH parameter */
+#define REFEN		 	0x1	/* Refresh enable */
+#define TREFMD		 	0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp		 	0x0	/* 2clk */
+#define Trc		 	0x3	/* 7clk */
+#define Tchr		 	0x2	/* 3clk */
+#define REFCNT		 	1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+/**************************************/
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #13*4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+SMRDATA:
+    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0x32
+    .word 0x30
+    .word 0x30
diff --git a/board/smdk2410/smdk2410.c b/board/smdk2410/smdk2410.c
new file mode 100755
index 0000000..9623aef
--- /dev/null
+++ b/board/smdk2410/smdk2410.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2410.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV	0xC3
+#define M_PDIV	0x4
+#define M_SDIV	0x1
+#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#define M_MDIV	0xA1
+#define M_PDIV	0x3
+#define M_SDIV	0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV	0xA1
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV	0x48
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x2
+#endif
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+	  "subs %0, %1, #1\n"
+	  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* to reduce PLL lock time, adjust the LOCKTIME register */
+	clk_power->LOCKTIME = 0xFFFFFF;
+
+	/* configure MPLL */
+	clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (4000);
+
+	/* configure UPLL */
+	clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	delay (8000);
+
+	/* set up the I/O ports */
+	gpio->GPACON = 0x007FFFFF;
+	gpio->GPBCON = 0x00044555;
+	gpio->GPBUP = 0x000007FF;
+	gpio->GPCCON = 0xAAAAAAAA;
+	gpio->GPCUP = 0x0000FFFF;
+	gpio->GPDCON = 0xAAAAAAAA;
+	gpio->GPDUP = 0x0000FFFF;
+	gpio->GPECON = 0xAAAAAAAA;
+	gpio->GPEUP = 0x0000FFFF;
+	gpio->GPFCON = 0x000055AA;
+	gpio->GPFUP = 0x000000FF;
+	gpio->GPGCON = 0xFF95FFBA;
+	gpio->GPGUP = 0x0000FFFF;
+	gpio->GPHCON = 0x002AFAAA;
+	gpio->GPHUP = 0x000007FF;
+
+	/* arch number of SMDK2410-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x30000100;
+
+	icache_enable();
+	dcache_enable();
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff --git a/board/smdk2410/u-boot.lds b/board/smdk2410/u-boot.lds
new file mode 100755
index 0000000..f4fbf96
--- /dev/null
+++ b/board/smdk2410/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/snmc/qs850/Makefile b/board/snmc/qs850/Makefile
new file mode 100755
index 0000000..e5d8446
--- /dev/null
+++ b/board/snmc/qs850/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/snmc/qs850/config.mk b/board/snmc/qs850/config.mk
new file mode 100755
index 0000000..905f692
--- /dev/null
+++ b/board/snmc/qs850/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2002-2003
+# Simple Network Magic Corporation, dnevil@snmc.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# QS850
+# Start address of Bootloader in Flash
+#
+
+TEXT_BASE = 0xFFF00000
diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c
new file mode 100755
index 0000000..d2f169b
--- /dev/null
+++ b/board/snmc/qs850/flash.c
@@ -0,0 +1,616 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+#define FLASH_WORD_SIZE unsigned long
+#define FLASH_ID_MASK 0xFFFFFFFF
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+/* stolen from esteem192e/flash.c */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
+
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+	volatile FLASH_WORD_SIZE* flash_base;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here */
+	/* Test for 8M Flash first */
+	debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_8M_PRELIM);
+	flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_8M_PRELIM);
+	size_b0 = flash_get_size(flash_base, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		size_b0, size_b0<<20);
+		return 0;
+	}
+
+	if (size_b0 < 8*1024*1024) {
+		/* Not quite 8M, try 4M Flash base address */
+		debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_4M_PRELIM);
+		flash_base = (volatile FLASH_WORD_SIZE*)(FLASH_BASE0_4M_PRELIM);
+		size_b0 = flash_get_size(flash_base, &flash_info[0]);
+	}
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+		size_b0, size_b0<<20);
+		return 0;
+	}
+
+	/* Only one bank */
+	if (CFG_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets ((ulong)flash_base, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+			CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
+		size_b1 = 0 ;
+		flash_info[0].size = size_b0;
+		return(size_b0);
+	}
+
+	/* We have 2 banks */
+	size_b1 = flash_get_size(flash_base, &flash_info[1]);
+
+	/* Re-do sizing to get full correct info */
+	if (size_b1) {
+		mtdcr(ebccfga, pb0cr);
+		pbcr = mfdcr(ebccfgd);
+		mtdcr(ebccfga, pb0cr);
+		base_b1 = -size_b1;
+		pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
+		mtdcr(ebccfgd, pbcr);
+	}
+
+	if (size_b0) {
+		mtdcr(ebccfga, pb1cr);
+		pbcr = mfdcr(ebccfgd);
+		mtdcr(ebccfga, pb1cr);
+		base_b0 = base_b1 - size_b0;
+		pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+		mtdcr(ebccfgd, pbcr);
+	}
+
+	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
+	flash_get_offsets (base_b0, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+		CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
+
+	if (size_b1) {
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
+		flash_get_offsets (base_b1, &flash_info[1]);
+
+		/* monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CFG_MONITOR_LEN,
+			base_b1+size_b1-1, &flash_info[1]);
+
+		/* monitor protection OFF by default (one is enough) */
+		(void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CFG_MONITOR_LEN,
+			base_b0+size_b0-1, &flash_info[0]);
+	} else {
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ This code is specific to the AM29DL163/AM29DL232 for the QS850/QS823.
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+	long large_sect_size;
+	long small_sect_size;
+
+	/* set up sector start adress table */
+	large_sect_size = info->size / (info->sector_count - 8 + 1);
+	small_sect_size = large_sect_size / 8;
+
+	if (info->flash_id & FLASH_BTYPE) {
+
+		/* set sector offsets for bottom boot block type */
+		for (i = 0; i < 7; i++) {
+			info->start[i] = base;
+			base += small_sect_size;
+		}
+
+		for (; i < info->sector_count; i++) {
+			info->start[i] = base;
+			base += large_sect_size;
+		}
+	}
+	else
+	{
+		/* set sector offsets for top boot block type */
+		for (i = 0; i < (info->sector_count - 8); i++) {
+			info->start[i] = base;
+			base += large_sect_size;
+		}
+
+		for (; i < info->sector_count; i++) {
+			info->start[i] = base;
+			base += small_sect_size;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[]=", bottom boot sect)\n";
+	uchar topboot[]=", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			printf ("AMD ");
+			break;
+		case FLASH_MAN_FUJ:
+			printf ("FUJITSU ");
+			break;
+		case FLASH_MAN_SST:
+			printf ("SST ");
+			break;
+		case FLASH_MAN_STM:
+			printf ("STM ");
+			break;
+		case FLASH_MAN_INTEL:
+			printf ("INTEL ");
+			break;
+		default:
+			printf ("Unknown Vendor ");
+			break;
+	}
+
+	if (info->flash_id & 0x0001 ) {
+		boottype = botboot;
+	} else {
+		boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM160B:
+			printf ("AM29LV160B (16 Mbit%s",boottype);
+			break;
+		case FLASH_AM160T:
+			printf ("AM29LV160T (16 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL163T:
+			printf ("AM29DL163T (16 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL163B:
+			printf ("AM29DL163B (16 Mbit%s",boottype);
+			break;
+		case FLASH_AM320B:
+			printf ("AM29LV320B (32 Mbit%s",boottype);
+			break;
+		case FLASH_AM320T:
+			printf ("AM29LV320T (32 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL323T:
+			printf ("AM29DL323T (32 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL323B:
+			printf ("AM29DL323B (32 Mbit%s",boottype);
+			break;
+		case FLASH_AMDL322T:
+			printf ("AM29DL322T (32 Mbit%s",boottype);
+			break;
+		default:
+			printf ("Unknown Chip Type\n");
+			break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+	info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	short i;
+	ulong base = (ulong)addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if(addr[0x0000] != 0x00890089){
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+	}
+	value = addr[0];
+
+	switch (value) {
+		case (AMD_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		case (FUJ_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+		case (STM_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_STM;
+			break;
+		case (SST_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_SST;
+			break;
+		case (INTEL_MANUFACT & FLASH_ID_MASK):
+			info->flash_id = FLASH_MAN_INTEL;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0); /* no or unknown flash */
+	}
+
+	value = addr[1]; /* device ID */
+
+	switch (value) {
+		case (AMD_ID_LV160T & FLASH_ID_MASK):
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break; /* => 4 MB */
+
+		case (AMD_ID_LV160B & FLASH_ID_MASK):
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00400000;
+			break; /* => 4 MB */
+
+		case (AMD_ID_DL163T & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL163T;
+			info->sector_count = 39;
+			info->size = 0x00400000;
+			break; /* => 4 MB */
+
+		case (AMD_ID_DL163B & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL163B;
+			info->sector_count = 39;
+			info->size = 0x00400000;
+			break; /* => 4 MB */
+
+		case (AMD_ID_DL323T & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL323T;
+			info->sector_count = 71;
+			info->size = 0x00800000;
+			break; /* => 8 MB */
+
+		case (AMD_ID_DL323B & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL323B;
+			info->sector_count = 71;
+			info->size = 0x00800000;
+			break; /* => 8 MB */
+
+		case (AMD_ID_DL322T & FLASH_ID_MASK):
+			info->flash_id += FLASH_AMDL322T;
+			info->sector_count = 71;
+			info->size = 0x00800000;
+			break; /* => 8 MB */
+
+		default:
+			/* FIXME*/
+			info->flash_id = FLASH_UNKNOWN;
+			return (0); /* => no or unknown flash */
+	}
+
+	flash_get_offsets(base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+		*addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+		(info->flash_id > FLASH_AMD_COMP) ) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+			addr[0] = (0x00300030 & FLASH_ID_MASK);
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
+	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
+			(0x00800080&FLASH_ID_MASK)  )
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) { /* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
+
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3); /* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* AMD stuff */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+	return (0);
+}
diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c
new file mode 100755
index 0000000..637f125
--- /dev/null
+++ b/board/snmc/qs850/qs850.c
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation, dnevil@snmc.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long  int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x0f07cc04,  0x00adcc04,  0x00a74c00,  0x00bfcc04,
+	0x1fffcc05,  0xffffcc05,  0xffffcc05,  0xffffcc05,
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x0ff7fc04,  0x0ffffc04,  0x00bdfc04,  0x00fffc00,
+	0x00fffc00,  0x00fffc00,  0x0ff77c00,  0x1ffffc05,
+	0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
+	0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x0f07cc04,  0x0fafcc00,  0x01ad0c04,  0x1ff74c07,
+	0xffffcc05,  0xffffcc05,  0xffffcc05,  0xffffcc05,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x0ff7fc04,  0x0ffffc00,  0x00bd7c00,  0x00fffc00,
+	0x00fffc00,  0x00fffc00,  0x0ffffc04,  0x0ff77c04,
+	0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
+	0x1ffffc05,  0x1ffffc05,  0x1ffffc05,  0x1ffffc05,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0xffffcc04,  0x1ff5cc84,  0xffffcc04,  0xffffcc04,
+	0xffffcc84,  0xffffcc05,  0xffffcc04,  0xffffcc04,
+	0xffffcc04,  0xffffcc04,  0xffffcc04,  0xffffcc04,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x1ff74c04,  0xffffcc07,  0xffffaa34,  0x1fb54a37
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (QS850, QS823, ...)
+ *
+ * Always return 1
+ */
+
+int checkboard (void)
+{
+	char *s, *e;
+	char buf[64];
+	int i;
+
+	i = getenv_r("serial#", buf, sizeof(buf));
+	s = (i>0) ? buf : NULL;
+
+#ifdef CONFIG_QS850
+	if (!s || strncmp(s, "QS850", 5)) {
+		puts ("### No HW ID - assuming QS850");
+#endif
+#ifdef CONFIG_QS823
+	if (!s || strncmp(s, "QS823", 5)) {
+		puts ("### No HW ID - assuming QS823");
+#endif
+	} else {
+		for (e=s; *e; ++e) {
+		if (*e == ' ')
+		break;
+	}
+
+	for ( ; s<e; ++s) {
+		putc (*s);
+		}
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+/* SDRAM Mode Register Definitions */
+
+/* Set SDRAM Burst Length to 4 (010) */
+/* See Motorola MPC850 User Manual, Page 13-14 */
+#define SDRAM_BURST_LENGTH      (2)
+
+/* Set Wrap Type to Sequential (0) */
+/* See Motorola MPC850 User Manual, Page 13-14 */
+#define SDRAM_WRAP_TYPE         (0 << 3)
+
+/* Set /CAS Latentcy to 2 clocks */
+#define SDRAM_CAS_LATENTCY      (2 << 4)
+
+/* The Mode Register value must be shifted left by 2, since it is */
+/* placed on the address bus, and the 2 LSBs are ignored for 32-bit accesses */
+#define SDRAM_MODE_REG  ((SDRAM_BURST_LENGTH|SDRAM_WRAP_TYPE|SDRAM_CAS_LATENTCY) << 2)
+
+#define UPMA_RUN(loops,index)   (0x80002000 + (loops<<8) + index)
+
+/* Please note a value of zero = 16 loops */
+#define REFRESH_INIT_LOOPS (0)
+
+
+long int initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/*
+	* Prescaler for refresh
+	*/
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	/*
+	* Map controller bank 1 to the SDRAM address
+	*/
+	memctl->memc_or1 = CFG_OR1;
+	memctl->memc_br1 = CFG_BR1;
+	udelay(1000);
+
+	/* perform SDRAM initialization sequence */
+	memctl->memc_mamr = CFG_16M_MAMR;
+	udelay(100);
+
+	/* Program the SDRAM's Mode Register */
+	memctl->memc_mar  = SDRAM_MODE_REG;
+
+	/* Run the Prechard Pattern at 0x3C */
+	memctl->memc_mcr  = UPMA_RUN(1,0x3c);
+	udelay(1);
+
+	/* Run the Refresh program residing at MAD index 0x30 */
+	/* This contains the CBR Refresh command with a loop */
+	/* The SDRAM must be refreshed at least 2 times */
+	/* Please note a value of zero = 16 loops */
+	memctl->memc_mcr  = UPMA_RUN(REFRESH_INIT_LOOPS,0x30);
+	udelay(1);
+
+	/* Run the Exception program residing at MAD index 0x3E */
+	/* This contains the Write Mode Register command */
+	/* The Write Mode Register command uses the value written to MAR */
+	memctl->memc_mcr  = UPMA_RUN(1,0x3e);
+
+	udelay (1000);
+
+	/*
+	* Check for 32M SDRAM Memory Size
+	*/
+	size = dram_size(CFG_32M_MAMR|MAMR_PTAE,
+	(long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
+	udelay (1000);
+
+	/*
+	* Check for 16M SDRAM Memory Size
+	*/
+	if (size != SDRAM_32M_MAX_SIZE) {
+	size = dram_size(CFG_16M_MAMR|MAMR_PTAE,
+	(long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+	udelay (1000);
+	}
+
+	udelay(10000);
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds
new file mode 100755
index 0000000..cb3f456
--- /dev/null
+++ b/board/snmc/qs850/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+	cpu/mpc8xx/start.o		(.text)
+	cpu/mpc8xx/traps.o		(.text)
+	common/dlmalloc.o		(.text)
+	lib_ppc/ppcstring.o		(.text)
+	lib_generic/vsprintf.o	(.text)
+	lib_generic/crc32.o		(.text)
+	lib_generic/zlib.o		(.text)
+	lib_ppc/cache.o		(.text)
+	lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+	common/environment.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/snmc/qs860t/Makefile b/board/snmc/qs860t/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/snmc/qs860t/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/snmc/qs860t/config.mk b/board/snmc/qs860t/config.mk
new file mode 100755
index 0000000..f6ab260
--- /dev/null
+++ b/board/snmc/qs860t/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2002
+# Simple Network Magic Corporation, dnevil@snmc.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# QS860T
+# Start address of 512K Socketed Flash
+#
+
+TEXT_BASE = 0xFFF00000
diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c
new file mode 100755
index 0000000..c84d08d
--- /dev/null
+++ b/board/snmc/qs860t/flash.c
@@ -0,0 +1,1120 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+
+#ifdef CFG_FLASH_16BIT
+#define FLASH_WORD_SIZE	unsigned short
+#define FLASH_ID_MASK	0xFFFF
+#else
+#define FLASH_WORD_SIZE unsigned long
+#define FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+/* stolen from esteem192e/flash.c */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
+
+#ifndef CFG_FLASH_16BIT
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+#else
+static int write_short (flash_info_t *info, ulong dest, ushort data);
+#endif
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	/* Only one bank */
+	if (CFG_MAX_FLASH_BANKS == 1)
+	{
+		/* Setup offsets */
+		flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+#if 0	/* sand: */
+		(void)flash_protect(FLAG_PROTECT_SET,
+			FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0,
+			FLASH_BASE1_PRELIM-1+size_b0,
+			&flash_info[0]);
+#else
+		(void)flash_protect(FLAG_PROTECT_SET,
+			CFG_MONITOR_BASE,
+			CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			&flash_info[0]);
+#endif
+		size_b1 = 0 ;
+		flash_info[0].size = size_b0;
+	}
+	/* 2 banks */
+	else
+	{
+		size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+		/* Re-do sizing to get full correct info */
+		if (size_b1)
+		{
+			mtdcr(ebccfga, pb0cr);
+			pbcr = mfdcr(ebccfgd);
+			mtdcr(ebccfga, pb0cr);
+			base_b1 = -size_b1;
+			pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
+			mtdcr(ebccfgd, pbcr);
+		}
+
+		if (size_b0)
+		{
+			mtdcr(ebccfga, pb1cr);
+			pbcr = mfdcr(ebccfgd);
+			mtdcr(ebccfga, pb1cr);
+			base_b0 = base_b1 - size_b0;
+			pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+			mtdcr(ebccfgd, pbcr);
+		}
+
+		size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
+
+		flash_get_offsets (base_b0, &flash_info[0]);
+
+		/* monitor protection ON by default */
+#if 0	/* sand: */
+		(void)flash_protect(FLAG_PROTECT_SET,
+			FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0,
+			FLASH_BASE1_PRELIM-1+size_b0,
+			&flash_info[0]);
+#else
+		(void)flash_protect(FLAG_PROTECT_SET,
+			CFG_MONITOR_BASE,
+			CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			&flash_info[0]);
+#endif
+
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
+
+			flash_get_offsets (base_b1, &flash_info[1]);
+
+			/* monitor protection ON by default */
+			(void)flash_protect(FLAG_PROTECT_SET,
+				base_b1+size_b1-CFG_MONITOR_LEN,
+				base_b1+size_b1-1,
+				&flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void)flash_protect(FLAG_PROTECT_CLEAR,
+				base_b0+size_b0-CFG_MONITOR_LEN,
+				base_b0+size_b0-1,
+				&flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
+
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}/* else 2 banks */
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if ((info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F320J3A ||
+		(info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F640J3A ||
+		(info->flash_id & FLASH_TYPEMASK) == INTEL_ID_28F128J3A) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * info->size/info->sector_count);
+		}
+	}
+	else if (info->flash_id & FLASH_BTYPE) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CFG_FLASH_16BIT
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00008000;
+			info->start[3] = base + 0x0000C000;
+			info->start[4] = base + 0x00010000;
+			info->start[5] = base + 0x00014000;
+			info->start[6] = base + 0x00018000;
+			info->start[7] = base + 0x0001C000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00020000) - 0x000E0000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00020000) - 0x00060000;
+			}
+		}
+#else
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000A000;
+			info->start[6] = base + 0x0000C000;
+			info->start[7] = base + 0x0000E000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00070000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		}
+#endif
+	} else {
+		/* set sector offsets for top boot block type */
+		i = info->sector_count - 1;
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CFG_FLASH_16BIT
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			info->start[i--] = base + info->size - 0x00014000;
+			info->start[i--] = base + info->size - 0x00018000;
+			info->start[i--] = base + info->size - 0x0001C000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		} else {
+
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+#else
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000A000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x0000E000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		} else {
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+#endif
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[]=", bottom boot sect)\n";
+	uchar topboot[]=", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	if (info->flash_id & 0x0001 ) {
+		boottype = botboot;
+	} else {
+		boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit%s",boottype);
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit%s",boottype);
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit%s",boottype);
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit%s",boottype);
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit%s",boottype);
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit%s",boottype);
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit%s",boottype);
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL800B:	printf ("INTEL28F800B (8 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL800T:	printf ("INTEL28F800T (8 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL160B:	printf ("INTEL28F160B (16 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL160T:	printf ("INTEL28F160T (16 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL320B:	printf ("INTEL28F320B (32 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL320T:	printf ("INTEL28F320T (32 Mbit%s",boottype);
+				break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 Mbit%s",boottype);
+				break;
+
+#if 0 /* enable when devices are available */
+
+	case FLASH_INTEL640B:	printf ("INTEL28F640B (64 Mbit%s",boottype);
+				break;
+	case FLASH_INTEL640T:	printf ("INTEL28F640T (64 Mbit%s",boottype);
+				break;
+#endif
+	case INTEL_ID_28F320J3A:	printf ("INTEL28F320JA3 (32 Mbit%s",boottype);
+				break;
+	case INTEL_ID_28F640J3A:	printf ("INTEL28F640JA3 (64 Mbit%s",boottype);
+				break;
+	case INTEL_ID_28F128J3A:	printf ("INTEL28F128JA3 (128 Mbit%s",boottype);
+				break;
+
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	short i;
+	ulong base = (ulong)addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+
+#ifndef CFG_FLASH_16BIT
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if(addr[0x0000] != 0x00890089){
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+#else
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x0089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x0090;
+
+	if(addr[0x0000] != 0x0089){
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0090;
+#endif
+	}
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0); /* no or unknown flash */
+
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+
+	case (AMD_ID_LV400T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV400B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case (AMD_ID_LV800T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV800B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (AMD_ID_LV160T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (AMD_ID_LV160B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case (AMD_ID_LV320T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (AMD_ID_LV320B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+
+	case (AMD_ID_DL322T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800T;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160T;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+#if 0 /* enable when devices are available */
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;				/* => 16 MB		*/
+#endif
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 32 MBit  	*/
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 64 MBit  	*/
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 128 MBit  	*/
+
+	default:
+		/* FIXME*/
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	flash_get_offsets(base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+		if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){
+			*addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+		} else {
+			*addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+		}
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+
+	volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
+	int flag, prot, sect, l_sect, barf;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+		((info->flash_id > FLASH_AMD_COMP) &&
+		( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+    if(info->flash_id < FLASH_AMD_COMP) {
+#ifndef CFG_FLASH_16BIT
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+#else
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+	addr[0x0555] = 0x0080;
+	addr[0x0555] = 0x00AA;
+	addr[0x02AA] = 0x0055;
+#endif
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+			addr[0] = (0x00300030 & FLASH_ID_MASK);
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
+	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
+		(0x00800080&FLASH_ID_MASK)  )
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+    } else {
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			barf = 0;
+#ifndef CFG_FLASH_16BIT
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00200020;
+			addr[0] = 0x00D000D0;
+			while(!(addr[0] & 0x00800080));	/* wait for error or finish */
+			if( addr[0] & 0x003A003A) {	/* check for error */
+				barf = addr[0] & 0x003A0000;
+				if( barf ) {
+					barf >>=16;
+				} else {
+					barf = addr[0] & 0x0000003A;
+				}
+			}
+#else
+			addr = (vu_short*)(info->start[sect]);
+			addr[0] = 0x0020;
+			addr[0] = 0x00D0;
+			while(!(addr[0] & 0x0080));	/* wait for error or finish */
+			if( addr[0] & 0x003A)	/* check for error */
+				barf = addr[0] & 0x003A;
+#endif
+			if(barf) {
+				printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
+				if(barf & 0x0002) printf("Block locked, not erased.\n");
+				if((barf & 0x0030) == 0x0030)
+					printf("Command Sequence error.\n");
+				if((barf & 0x0030) == 0x0020)
+					printf("Block Erase error.\n");
+				if(barf & 0x0008) printf("Vpp Low error.\n");
+				rcode = 1;
+			} else printf(".");
+			l_sect = sect;
+		}
+	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+
+	}
+
+    }
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*flash_info_t *addr2info (ulong addr)
+{
+	flash_info_t *info;
+	int i;
+
+	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+		if ((addr >= info->start[0]) &&
+		    (addr < (info->start[0] + info->size)) ) {
+			return (info);
+		}
+	}
+
+	return (NULL);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+
+/*int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+	int i;
+	ulong         end        = addr + cnt - 1;
+	flash_info_t *info_first = addr2info (addr);
+	flash_info_t *info_last  = addr2info (end );
+	flash_info_t *info;
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	if (!info_first || !info_last) {
+		return (8);
+	}
+
+	for (info = info_first; info <= info_last; ++info) {
+		ulong b_end = info->start[0] + info->size;*/	/* bank end addr */
+/*		short s_end = info->sector_count - 1;
+		for (i=0; i<info->sector_count; ++i) {
+			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+			if ((end >= info->start[i]) && (addr < e_addr) &&
+			    (info->protect[i] != 0) ) {
+				return (4);
+			}
+		}
+	}
+
+*/	/* finally write data to flash */
+/*	for (info = info_first; info <= info_last && cnt>0; ++info) {
+		ulong len;
+
+		len = info->start[0] + info->size - addr;
+		if (len > cnt)
+			len = cnt;
+		if ((i = write_buff(info, src, addr, len)) != 0) {
+			return (i);
+		}
+		cnt  -= len;
+		addr += len;
+		src  += len;
+	}
+	return (0);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+#ifndef CFG_FLASH_16BIT
+	ulong cp, wp, data;
+	int l;
+#else
+	ulong cp, wp;
+	ushort data;
+#endif
+	int i, rc;
+
+#ifndef CFG_FLASH_16BIT
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+
+#else
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+/*	l = 0; used for debuging  */
+	while (cnt >= 2) {
+		data = 0;
+		for (i=0; i<2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+/*		if(!l){
+			printf("%x",data);
+			l = 1;
+		}  used for debuging */
+
+		if ((rc = write_short(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_short(info, wp, data));
+
+
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifndef CFG_FLASH_16BIT
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start,barf;
+	int flag;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	if(info->flash_id > FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00A000A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00400040;
+	}
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if(info->flash_id > FLASH_AMD_COMP) {
+		while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	} else {
+		while(!(addr[0] & 0x00800080)) {  	/* wait for error or finish */
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+
+		if( addr[0] & 0x003A003A) {	/* check for error */
+			barf = addr[0] & 0x003A0000;
+			if( barf ) {
+				barf >>=16;
+			} else {
+				barf = addr[0] & 0x0000003A;
+			}
+			printf("\nFlash write error at address %lx\n",(unsigned long)dest);
+			if(barf & 0x0002) printf("Block locked, not erased.\n");
+			if(barf & 0x0010) printf("Programming error.\n");
+			if(barf & 0x0008) printf("Vpp Low error.\n");
+			return(2);
+		}
+	}
+
+	return (0);
+}
+
+#else
+
+static int write_short (flash_info_t *info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	ulong start,barf;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	if(info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00D0;
+		*addr = 0x0040;
+	}
+	*((vu_short *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if(info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+
+	} else {
+		/* intel stuff */
+		while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+		}
+
+		if( addr[0] & 0x003A) {	/* check for error */
+			barf = addr[0] & 0x003A;
+			printf("\nFlash write error at address %lx\n",(unsigned long)dest);
+			if(barf & 0x0002) printf("Block locked, not erased.\n");
+			if(barf & 0x0010) printf("Programming error.\n");
+			if(barf & 0x0008) printf("Vpp Low error.\n");
+			return(2);
+		}
+		*addr = 0x00B0;
+		*addr = 0x0070;
+		while(!(addr[0] & 0x0080)){  	/* wait for error or finish */
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+		}
+		*addr = 0x00FF;
+	}
+	return (0);
+}
+
+
+#endif
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c
new file mode 100755
index 0000000..a11d863
--- /dev/null
+++ b/board/snmc/qs860t/qs860t.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation, dnevil@snmc.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/u-boot.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long  int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35,
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, 0xFFFFEC04,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, 0xFFFFEC04, 0xFFFFEC04,
+	0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, 0xFFFFEC04, 0xFFFFEC04, 0xFFFFEC04
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (QS860T...)
+ *
+ * Always return 1
+ */
+
+int checkboard (void)
+{
+	char *s, *e;
+	char buf[64];
+	int i;
+
+	i = getenv_r("serial#", buf, sizeof(buf));
+	s = (i>0) ? buf : NULL;
+
+	if (!s || strncmp(s, "QS860T", 6)) {
+		puts ("### No HW ID - assuming QS860T");
+	} else {
+		for (e=s; *e; ++e) {
+			if (*e == ' ')
+			break;
+		}
+
+		for ( ; s<e; ++s) {
+			putc (*s);
+		}
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+
+	upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/*
+	* Prescaler for refresh
+	*/
+	memctl->memc_mptpr = 0x0400;
+
+	/*
+	* Map controller bank 2 to the SDRAM address
+	*/
+	memctl->memc_or2 = CFG_OR2;
+	memctl->memc_br2 = CFG_BR2;
+	udelay(200);
+
+	/* perform SDRAM initialization sequence */
+	memctl->memc_mbmr = CFG_16M_MBMR;
+	udelay(100);
+
+	memctl->memc_mar  = 0x00000088;
+	memctl->memc_mcr  = 0x80804105;	/* run precharge pattern */
+	udelay(1);
+
+	/* Run two refresh cycles on SDRAM */
+	memctl->memc_mbmr = 0x18802118;
+	memctl->memc_mcr  = 0x80804130;
+	memctl->memc_mbmr = 0x18802114;
+	memctl->memc_mcr  = 0x80804106;
+
+	udelay (1000);
+
+#if 0
+	/*
+	* Check for 64M SDRAM Memory Size
+	*/
+	size = dram_size (CFG_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);
+	udelay (1000);
+
+	/*
+	* Check for 16M SDRAM Memory Size
+	*/
+	if (size != SDRAM_64M_MAX_SIZE) {
+#endif
+	size = dram_size (CFG_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+	udelay (1000);
+#if 0
+	}
+
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
+#endif
+
+
+	udelay(10000);
+
+
+#if 0
+
+	/*
+	* Also, map other memory to correct position
+	*/
+
+	/*
+	* Map the 8M Intel Flash device to chip select 1
+	*/
+	memctl->memc_or1 = CFG_OR1;
+	memctl->memc_br1 = CFG_BR1;
+
+
+	/*
+	* Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg
+	* to chip select 3
+	*/
+	memctl->memc_or3 = CFG_OR3;
+	memctl->memc_br3 = CFG_BR3;
+
+	/*
+	* Map chip selects 4, 5, 6, & 7 for external expansion connector
+	*/
+	memctl->memc_or4 = CFG_OR4;
+	memctl->memc_br4 = CFG_BR4;
+
+	memctl->memc_or5 = CFG_OR5;
+	memctl->memc_br5 = CFG_BR5;
+
+	memctl->memc_or6 = CFG_OR6;
+	memctl->memc_br6 = CFG_BR6;
+
+	memctl->memc_or7 = CFG_OR7;
+	memctl->memc_br7 = CFG_BR7;
+
+#endif
+
+	return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mbmr = mbmr_value;
+
+	return (get_ram_size(base, maxsize));
+}
diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds
new file mode 100755
index 0000000..cb3f456
--- /dev/null
+++ b/board/snmc/qs860t/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+	cpu/mpc8xx/start.o		(.text)
+	cpu/mpc8xx/traps.o		(.text)
+	common/dlmalloc.o		(.text)
+	lib_ppc/ppcstring.o		(.text)
+	lib_generic/vsprintf.o	(.text)
+	lib_generic/crc32.o		(.text)
+	lib_generic/zlib.o		(.text)
+	lib_ppc/cache.o		(.text)
+	lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+	common/environment.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sorcery/Makefile b/board/sorcery/Makefile
new file mode 100755
index 0000000..3d6d673
--- /dev/null
+++ b/board/sorcery/Makefile
@@ -0,0 +1,45 @@
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sorcery/config.mk b/board/sorcery/config.mk
new file mode 100755
index 0000000..25de0b5
--- /dev/null
+++ b/board/sorcery/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# sorcery board
+#
+
+TEXT_BASE = 0xfff00000
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c
new file mode 100755
index 0000000..35d6a06
--- /dev/null
+++ b/board/sorcery/sorcery.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2004, Freescale Inc.
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8220.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <pci.h>
+
+long int initdram (int board_type)
+{
+	ulong size;
+
+	size = dramSetup ();
+
+	return get_ram_size((ulong *)CFG_SDRAM_BASE, size);
+}
+
+int checkboard (void)
+{
+	puts ("Board: Sorcery-C MPC8220\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+
+#endif /* CONFIG_PCI */
+
+void pci_init_board (void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc8220_init (struct pci_controller *hose);
+	pci_mpc8220_init (&hose);
+#endif /* CONFIG_PCI */
+}
diff --git a/board/sorcery/u-boot.lds b/board/sorcery/u-boot.lds
new file mode 100755
index 0000000..889bc77
--- /dev/null
+++ b/board/sorcery/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8220/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/spd8xx/Makefile b/board/spd8xx/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/spd8xx/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/spd8xx/config.mk b/board/spd8xx/config.mk
new file mode 100755
index 0000000..e1e0192
--- /dev/null
+++ b/board/spd8xx/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# SPD823TS boards
+#
+
+TEXT_BASE = 0xFF000000
diff --git a/board/spd8xx/flash.c b/board/spd8xx/flash.c
new file mode 100755
index 0000000..8c0bb4f
--- /dev/null
+++ b/board/spd8xx/flash.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	/* All Speech Design board memory (DRAM and EPROM) initialisation is
+	done in dram_init().
+	The caller of ths function here expects the total size and will hang,
+	if we give here back 0. So we return the EPROM size. */
+
+	return (1024 * 1024); /* 1 MB */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	printf("no FLASH memory in MPC823TS board\n");
+	return;
+}
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	return 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c
new file mode 100755
index 0000000..c79b9b0
--- /dev/null
+++ b/board/spd8xx/spd8xx.c
@@ -0,0 +1,294 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sharc_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
+	0xFFFFEC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
+	0xFFFFEC05,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+
+const uint sdram_table[] = {
+	/*
+	 * Single Read. (Offset 0 in UPM RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
+	0x1FF77C47,		/* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPM RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+	0x1FF77C35, 0xEFEABC34, 0x1FB57C35,	/* last */
+	/*
+	 * Burst Read. (Offset 8 in UPM RAM)
+	 */
+	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPM RAM)
+	 */
+	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47,	/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPM RAM)
+	 */
+	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,	/* last */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPM RAM)
+	 */
+	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07,	/* last */
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPM RAM)
+	 */
+	0x7FFFFC07,		/* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ */
+
+int checkboard (void)
+{
+	puts ("Board: SPD823TS\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0;
+
+#if 0
+	/*
+	 * Map controller bank 2 to the SRAM bank at preliminary address.
+	 */
+	memctl->memc_or2 = CFG_OR2;
+	memctl->memc_br2 = CFG_BR2;
+#endif
+
+	/*
+	 * Map controller bank 4 to the PER8 bank.
+	 */
+	memctl->memc_or4 = CFG_OR4;
+	memctl->memc_br4 = CFG_BR4;
+
+#if 0
+	/* Configure SHARC at UMA */
+	upmconfig (UPMA, (uint *) sharc_table,
+		   sizeof (sharc_table) / sizeof (uint));
+	/* Map controller bank 5 to the SHARC */
+	memctl->memc_or5 = CFG_OR5;
+	memctl->memc_br5 = CFG_BR5;
+#endif
+
+	memctl->memc_mamr = 0x00001000;
+
+	/* Configure SDRAM at UMB */
+	upmconfig (UPMB, (uint *) sdram_table,
+		   sizeof (sdram_table) / sizeof (uint));
+
+	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mbmr = CFG_MBMR_8COL;	/* refresh not enabled yet */
+
+	udelay (200);
+	memctl->memc_mcr = 0x80806105;
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;
+	udelay (1);
+	memctl->memc_mcr = 0x80806130;
+	udelay (1);
+	memctl->memc_mcr = 0x80806106;
+
+	memctl->memc_mbmr |= MBMR_PTBE;	/* refresh enabled */
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 */
+	size_b0 =
+		dram_size (CFG_MBMR_8COL, SDRAM_BASE3_PRELIM,
+			   SDRAM_MAX_SIZE);
+
+	memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mbmr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy (void)
+{
+	immap_t *immr = (immap_t *) CFG_IMMR;
+	ushort sreg;
+
+	/* Configure extra port pins for NS DP83843 PHY */
+	immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
+
+	sreg = immr->im_ioport.iop_padir;
+	sreg |= PA_ENET_MDC;	/* Mgmt. Data Clock is Output */
+	sreg &= ~(PA_ENET_MDIO);	/* Mgmt. Data I/O is bidirect. => Input */
+	immr->im_ioport.iop_padir = sreg;
+
+	immr->im_ioport.iop_padat &= ~(PA_ENET_MDC);	/* set MDC = 0 */
+
+	/*
+	 * RESET in implemented by a positive pulse of at least 1 us
+	 * at the reset pin.
+	 *
+	 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
+	 *
+	 * Note: The RESET pin is high active, but there is an
+	 *       inverter on the SPD823TS board...
+	 */
+	immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
+	immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
+	/* assert RESET signal of PHY */
+	immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
+	udelay (10);
+	/* de-assert RESET signal of PHY */
+	immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
+	udelay (10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void ide_set_reset (int on)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/*
+	 * Configure PC for IDE Reset Pin
+	 */
+	if (on) {		/* assert RESET */
+		immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+	} else {		/* release RESET */
+		immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+	}
+
+	/* program port pin as GPIO output */
+	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
+	immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
+	immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds
new file mode 100755
index 0000000..f9150ab
--- /dev/null
+++ b/board/spd8xx/u-boot.lds
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    common/environment.o(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug
new file mode 100755
index 0000000..650572d
--- /dev/null
+++ b/board/spd8xx/u-boot.lds.debug
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/ssv/adnpesc1/Makefile b/board/ssv/adnpesc1/Makefile
new file mode 100755
index 0000000..9182a4e
--- /dev/null
+++ b/board/ssv/adnpesc1/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o misc.o
+
+SOBJS  = vectors.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ssv/adnpesc1/adnpesc1.c b/board/ssv/adnpesc1/adnpesc1.c
new file mode 100755
index 0000000..2f704a0
--- /dev/null
+++ b/board/ssv/adnpesc1/adnpesc1.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nios-io.h>
+#include <spi.h>
+
+#if	defined(CONFIG_HW_WATCHDOG)
+extern void ssv_wd_pio_init(void);	/* comes from ../common/wd_pio.c
+					   included by ./misc.c */
+#endif
+
+void _default_hdlr (void)
+{
+	printf ("default_hdlr\n");
+}
+
+int board_early_init_f (void)
+{
+#if	defined(CONFIG_HW_WATCHDOG)
+	ssv_wd_pio_init();
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts (	"Board: SSV DilNetPC ADNP/ESC1"
+#if	defined(CONFIG_DNPEVA2)
+		" on DNP/EVA2"
+#endif
+		"\n");
+#if     defined(CONFIG_NIOS_BASE_32)
+	puts ("Conf.: SSV Base 32 (nios_32)\n");
+#endif
+
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}
+
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_SPI) && CONFIG_NIOS_SPI
+
+#define	SPI_RTC_CS_MASK	0x00000001
+
+void spi_rtc_chipsel(int cs)
+{
+	nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
+
+	if (cs)
+		spi->slaveselect = SPI_RTC_CS_MASK;	/* activate (1) */
+	else
+		spi->slaveselect = 0;			/* deactivate (0) */
+}
+
+/*
+ * The SPI command uses this table of functions for controlling the SPI
+ * chip selects: it calls the appropriate function to control the SPI
+ * chip selects.
+ */
+spi_chipsel_type spi_chipsel[] = {
+	spi_rtc_chipsel
+};
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
+#endif /* CFG_CMD_SPI */
+
+#if	defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+	return 0;       /* No hotkeys supported */
+}
+#endif /* CONFIG_POST */
diff --git a/board/ssv/adnpesc1/config.mk b/board/ssv/adnpesc1/config.mk
new file mode 100755
index 0000000..7d8eb03
--- /dev/null
+++ b/board/ssv/adnpesc1/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2004
+# Li-Pro.Net <www.li-pro.net>
+# Stephan Linz <linz@li-pro.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x02fc0000	# ATTENTION: notice your CFG_MONITOR_LEN setting
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/ssv/adnpesc1/flash.c b/board/ssv/adnpesc1/flash.c
new file mode 100755
index 0000000..fd8379b
--- /dev/null
+++ b/board/ssv/adnpesc1/flash.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+/*
+ * include common flash code (for ssv boards)
+ */
+#include "../common/flash.c"
+
+/*---------------------------------------------------------------------*/
+#define	BANKSZ	(8 * 1024 * 1024)
+#define	SECTSZ	(64 * 1024)
+#define	UBOOTSECS ((CFG_MONITOR_LEN + CFG_ENV_SIZE) / SECTSZ)
+#define	UBOOTAREA (UBOOTSECS * 64 * 1024)	/* monitor / env area */
+
+/*---------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = BANKSZ;
+	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMLV640U;
+
+	addr = CFG_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+
+		/* Protect monitor / environment area */
+		if (addr <= (CFG_FLASH_BASE + UBOOTAREA))
+			fli->protect[i] = 1;
+		else
+			fli->protect[i] = 0;
+	}
+
+	return (BANKSZ);
+}
diff --git a/board/ssv/adnpesc1/misc.c b/board/ssv/adnpesc1/misc.c
new file mode 100755
index 0000000..1c5fcb9
--- /dev/null
+++ b/board/ssv/adnpesc1/misc.c
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * board/ssv/adnpesc1/misc.c
+ *
+ * miscellaneous board interfaces / drivers
+ */
+
+#include <common.h>
+
+#if	defined(CONFIG_STATUS_LED)
+#include "../common/cmd_sled.c"
+#endif
+
+#if	defined(CONFIG_HW_WATCHDOG)
+#include "../common/wd_pio.c"
+#endif
+
+#if	defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+#include "../common/post.c"
+#endif
diff --git a/board/ssv/adnpesc1/u-boot.lds b/board/ssv/adnpesc1/u-boot.lds
new file mode 100755
index 0000000..8b01f45
--- /dev/null
+++ b/board/ssv/adnpesc1/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-nios")
+OUTPUT_ARCH(nios)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios/start.o (.text)
+	  *(.text)
+	}
+	__text_end = .;
+
+	. = ALIGN(4);
+	.rodata :
+	{
+		*(.rodata)
+	}
+	__rodata_end = .;
+
+	. = ALIGN(4);
+	.data :
+	{
+		*(.data)
+	}
+	. = ALIGN(4);
+	__data_end = .;
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	__bss_start = .;
+	. = ALIGN(4);
+	.bss :
+	{
+		*(.bss)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+}
diff --git a/board/ssv/adnpesc1/vectors.S b/board/ssv/adnpesc1/vectors.S
new file mode 100755
index 0000000..fb7e17e
--- /dev/null
+++ b/board/ssv/adnpesc1/vectors.S
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+
+/*************************************************************************
+ * Exception Vector Table
+ *
+ * This could have gone in the cpu soure tree, but the whole point of
+ * Nios is customization -- and polluting the cpu source tree with
+ * board-specific ifdef's really defeats the purpose, no? With this in
+ * the board-specific tree, each board has the freedom to organize
+ * vectors/traps, etc anyway it wants. The init code copies this table
+ * to the proper location.
+ *
+ * Each board can do what it likes here. But there are four "standard"
+ * handlers availble:
+ *
+ *	_cwp_lolimit	-Handles register window underflows.
+ *	_cwp_hilimit	-Handles register window overflows.
+ *	_timebase_int	-Increments the timebase.
+ *	_def_xhandler	-Default exception handler.
+ *
+ * _timebase_int handles a Nios Timer interrupt and increments the
+ * timestamp used for the get_timer(), reset_timer(), etc. routines. It
+ * expects the timer to be configured like the standard-32 low priority
+ * timer.
+ *
+ * _def_xhandler dispatches exceptions/traps via the external_interrupt()
+ * routine. This lets you use the irq_install_handler() and handle your
+ * interrupts/traps with code written in C.
+ ************************************************************************/
+
+	.data
+	.global _vectors
+	.align	4
+_vectors:
+
+#if	defined(CFG_NIOS_CPU_OCI_BASE)
+	/* OCI does the reset job */
+	.long	_def_xhandler@h		/* Vector 0  - NMI / Reset */
+#else
+	/* there is no OCI, so we have to do a direct reset jump here */
+	.long	CFG_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
+#endif
+	.long	_cwp_lolimit@h		/* Vector 1  - underflow */
+	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
+
+	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 6 - future reserved */
+	.long	_def_xhandler@h		/* Vector 7 - future reserved */
+	.long	_def_xhandler@h		/* Vector 8 - future reserved */
+	.long	_def_xhandler@h		/* Vector 9 - future reserved */
+	.long	_def_xhandler@h		/* Vector 10 - future reserved */
+	.long	_def_xhandler@h		/* Vector 11 - future reserved */
+	.long	_def_xhandler@h		/* Vector 12 - future reserved */
+	.long	_def_xhandler@h		/* Vector 13 - future reserved */
+	.long	_def_xhandler@h		/* Vector 14 - future reserved */
+	.long	_def_xhandler@h		/* Vector 15 - future reserved */
+#if	(CFG_NIOS_TMRIRQ == 16)
+	.long	_timebase_int@h		/* Vector 16 - lopri timer*/
+#else
+	.long	_def_xhandler@h		/* Vector 16 */
+#endif
+	.long	_def_xhandler@h		/* Vector 17 */
+	.long	_def_xhandler@h		/* Vector 18 */
+	.long	_def_xhandler@h		/* Vector 19 */
+	.long	_def_xhandler@h		/* Vector 20 */
+	.long	_def_xhandler@h		/* Vector 21 */
+	.long	_def_xhandler@h		/* Vector 22 */
+	.long	_def_xhandler@h		/* Vector 23 */
+	.long	_def_xhandler@h		/* Vector 24 */
+	.long	_def_xhandler@h		/* Vector 25 */
+	.long	_def_xhandler@h		/* Vector 26 */
+	.long	_def_xhandler@h		/* Vector 27 */
+	.long	_def_xhandler@h		/* Vector 28 */
+	.long	_def_xhandler@h		/* Vector 29 */
+	.long	_def_xhandler@h		/* Vector 30 */
+	.long	_def_xhandler@h		/* Vector 31 */
+	.long	_def_xhandler@h		/* Vector 32 */
+	.long	_def_xhandler@h		/* Vector 33 */
+	.long	_def_xhandler@h		/* Vector 34 */
+	.long	_def_xhandler@h		/* Vector 35 */
+	.long	_def_xhandler@h		/* Vector 36 */
+	.long	_def_xhandler@h		/* Vector 37 */
+	.long	_def_xhandler@h		/* Vector 38 */
+	.long	_def_xhandler@h		/* Vector 39 */
+	.long	_def_xhandler@h		/* Vector 40 */
+	.long	_def_xhandler@h		/* Vector 41 */
+	.long	_def_xhandler@h		/* Vector 42 */
+	.long	_def_xhandler@h		/* Vector 43 */
+	.long	_def_xhandler@h		/* Vector 44 */
+	.long	_def_xhandler@h		/* Vector 45 */
+	.long	_def_xhandler@h		/* Vector 46 */
+	.long	_def_xhandler@h		/* Vector 47 */
+	.long	_def_xhandler@h		/* Vector 48 */
+	.long	_def_xhandler@h		/* Vector 49 */
+#if	(CFG_NIOS_TMRIRQ == 50)
+	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
+#else
+	.long	_def_xhandler@h		/* Vector 50 */
+#endif
+	.long	_def_xhandler@h		/* Vector 51 */
+	.long	_def_xhandler@h		/* Vector 52 */
+	.long	_def_xhandler@h		/* Vector 53 */
+	.long	_def_xhandler@h		/* Vector 54 */
+	.long	_def_xhandler@h		/* Vector 55 */
+	.long	_def_xhandler@h		/* Vector 56 */
+	.long	_def_xhandler@h		/* Vector 57 */
+	.long	_def_xhandler@h		/* Vector 58 */
+	.long	_def_xhandler@h		/* Vector 59 */
+	.long	_def_xhandler@h		/* Vector 60 */
+	.long	_def_xhandler@h		/* Vector 61 */
+	.long	_def_xhandler@h		/* Vector 62 */
+	.long	_def_xhandler@h		/* Vector 63 */
diff --git a/board/ssv/common/cmd_sled.c b/board/ssv/common/cmd_sled.c
new file mode 100755
index 0000000..d61fa3e
--- /dev/null
+++ b/board/ssv/common/cmd_sled.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <status_led.h>
+
+#if	defined(CONFIG_STATUS_LED)
+
+/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+ * !!!!!       Q u i c k   &   D i r t y   H a c k	 !!!!!
+ * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+ * !!!!!						 !!!!!
+ * !!!!! Next type definition was coming from original	 !!!!!
+ * !!!!! status LED driver drivers/status_led.c and	 !!!!!
+ * !!!!! should exported for using here.		 !!!!!
+ * !!!!!						 !!!!!
+ * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
+
+typedef struct {
+	led_id_t mask;
+	int state;
+	int period;
+	int cnt;
+} led_dev_t;
+
+extern led_dev_t led_dev[];
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int led_id = 0;
+
+	if (argc > 1) {
+#ifdef	STATUS_LED_BOOT
+		if (!strcmp (argv[1], "boot")) {
+			led_id = STATUS_LED_BOOT + 1;
+		}
+#endif
+#ifdef	STATUS_LED_RED
+		if (!strcmp (argv[1], "red")) {
+			led_id = STATUS_LED_RED + 1;
+		}
+#endif
+#ifdef	STATUS_LED_YELLOW
+		if (!strcmp (argv[1], "yellow")) {
+			led_id = STATUS_LED_YELLOW + 1;
+		}
+#endif
+#ifdef	STATUS_LED_GREEN
+		if (!strcmp (argv[1], "green")) {
+			led_id = STATUS_LED_GREEN + 1;
+		}
+#endif
+	}
+
+	switch (argc) {
+	case 1:
+#if	(STATUS_LED_BITS > 3)
+		for (; led_id < 4; led_id++)
+#elif	(STATUS_LED_BITS > 2)
+		for (; led_id < 3; led_id++)
+#elif	(STATUS_LED_BITS > 1)
+		for (; led_id < 2; led_id++)
+#elif	(STATUS_LED_BITS > 0)
+		for (; led_id < 1; led_id++)
+#else
+#error "*** STATUS_LED_BITS not correct defined ***"
+#endif
+		{
+			printf ("Status LED '%s' is %s\n",
+				led_id == STATUS_LED_BOOT ? "boot"
+				: led_id == STATUS_LED_RED ? "red"
+				: led_id == STATUS_LED_YELLOW ? "yellow"
+				: led_id ==
+				STATUS_LED_GREEN ? "green" : "unknown",
+				led_dev[led_id].state ==
+				STATUS_LED_ON ? "on" : led_dev[led_id].
+				state ==
+				STATUS_LED_OFF ? "off" : led_dev[led_id].
+				state ==
+				STATUS_LED_BLINKING ? "blinking" : "unknown");
+		}
+		return 0;
+	case 2:
+		if (led_id) {
+			printf ("Status LED '%s' is %s\n", argv[1],
+				led_dev[led_id - 1].state ==
+				STATUS_LED_ON ? "on" : led_dev[led_id -
+							       1].state ==
+				STATUS_LED_OFF ? "off" : led_dev[led_id -
+								 1].state ==
+				STATUS_LED_BLINKING ? "blinking" : "unknown");
+			return 0;
+		} else
+			break;
+	case 3:
+		if (led_id) {
+			if (!strcmp (argv[2], "on")) {
+				status_led_set (led_id - 1, STATUS_LED_ON);
+				return 0;
+			} else if (!strcmp (argv[2], "off")) {
+				status_led_set (led_id - 1, STATUS_LED_OFF);
+				return 0;
+			} else if (!strcmp (argv[2], "blink")) {
+				status_led_set (led_id - 1,
+						STATUS_LED_BLINKING);
+				return 0;
+			} else
+				break;
+		} else
+			break;
+	default:
+		break;
+	}
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+#ifdef	STATUS_LED_BOOT
+#ifdef	STATUS_LED_RED
+#ifdef	STATUS_LED_YELLOW
+#ifdef	STATUS_LED_GREEN
+#define __NAME_STR		"    - name: boot|red|yellow|green\n"
+#else
+#define __NAME_STR		"    - name: boot|red|yellow\n"
+#endif
+#else
+#define __NAME_STR		"    - name: boot|red\n"
+#endif
+#else
+#define __NAME_STR		"    - name: boot\n"
+#endif
+#else
+#define __NAME_STR		"    - name: (no such defined)\n"
+#endif
+
+U_BOOT_CMD (sled, 3, 0, do_sled,
+	    "sled    - check and set status led\n",
+	    "sled [name [state]]\n" __NAME_STR "    - state: on|off|blink\n");
+#endif /* CFG_CMD_BSP */
+#endif	/* CONFIG_STATUS_LED */
diff --git a/board/ssv/common/flash.c b/board/ssv/common/flash.c
new file mode 100755
index 0000000..70cab7f
--- /dev/null
+++ b/board/ssv/common/flash.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <watchdog.h>
+#include <nios.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	unsigned long size;
+	int erased;
+	volatile unsigned char *flash;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned char *) info->start[i];
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s", info->start[i], erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int prot, sect, wait;
+	unsigned oldpri;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	for (sect = s_first; sect <= s_last; sect++) {
+		printf("- Erase: Sect: %i @ 0x%08x\n", sect,  info->start[sect]);
+	}
+#endif
+
+	/* NOTE: disabling interrupts on Nios can be very bad since it
+	 * also disables the LO_LIMIT exception. It's better here to
+	 * set the interrupt priority to 3 & restore it when we're done.
+	 */
+	oldpri = ipri (3);
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			*addr = 0xf0;
+			*(addr+0xAAA/2) = 0xaa;
+			*(addr+0x554/2) = 0x55;
+			*(addr+0xAAA/2) = 0x80;
+			*(addr+0xAAA/2) = 0xaa;
+			*(addr+0x554/2) = 0x55;
+			*addr2 = 0x30;
+			/* Now just wait for 0xffff & provide some user
+			 * feedback while we wait. Here we have to grant
+			 * timer interrupts. Otherwise get_timer() can't
+			 * work right. */
+			ipri(oldpri);
+			start = get_timer (0);
+			while (*addr2 != 0xffff) {
+				for (wait = 8; wait; wait--) {
+					udelay (125 * 1000);
+				}
+				putc ('.');
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+			oldpri = ipri (3); /* disallow non important irqs again */
+		}
+	}
+
+	printf ("\n");
+	*addr = 0xf0;
+
+	/* Restore interrupt priority */
+	ipri (oldpri);
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * srcbuffer, ulong addr, ulong cnt)
+{
+
+	volatile CFG_FLASH_WORD_SIZE *cmd = (vu_short *) info->start[0];
+	volatile CFG_FLASH_WORD_SIZE *dst = (vu_short *) addr;
+	CFG_FLASH_WORD_SIZE *src = (void *) srcbuffer;
+	CFG_FLASH_WORD_SIZE b;
+	unsigned oldpri;
+	ulong start;
+
+	cnt /= sizeof(CFG_FLASH_WORD_SIZE);
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((*dst & b) != b) {
+			printf ("%02x : %02x\n", *dst, b);
+			return (2);
+		}
+
+		/* Disable interrupts other than window underflow
+		 * (interrupt priority 2)
+		 */
+		oldpri = ipri (3);
+		*(cmd+0xAAA/2) = 0xaa;
+		*(cmd+0x554/2) = 0x55;
+		*(cmd+0xAAA/2) = 0xa0;
+		ipri (oldpri);
+		*dst = b;
+
+		/* Verify write */
+		start = get_timer (0);
+		while (*dst != b) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				*cmd = 0xf0;
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+	}
+
+	*cmd = 0xf0;
+	return (0);
+}
diff --git a/board/ssv/common/post.c b/board/ssv/common/post.c
new file mode 100755
index 0000000..a5f29c1
--- /dev/null
+++ b/board/ssv/common/post.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+#if !defined(CFG_NIOS_POST_WORD_ADDR)
+#error "*** CFG_NIOS_POST_WORD_ADDR not defined ***"
+#endif
+
+void post_word_store (ulong a)
+{
+	volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR);
+	*(volatile ulong *) save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+	volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR);
+	return *(volatile ulong *) save_addr;
+}
+
+#endif	/* CONFIG_POST || CONFIG_LOGBUFFER*/
diff --git a/board/ssv/common/wd_pio.c b/board/ssv/common/wd_pio.c
new file mode 100755
index 0000000..3215ac9
--- /dev/null
+++ b/board/ssv/common/wd_pio.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <nios.h>
+#include <nios-io.h>
+
+#if	defined(CONFIG_HW_WATCHDOG)
+
+#if !defined(CONFIG_HW_WDENA_BASE)
+#error "*** CONFIG_HW_WDENA_BASE not defined ***"
+#if !defined(CONFIG_HW_WDENA_BIT)
+#error "*** CONFIG_HW_WDENA_BIT not defined ***"
+#endif
+#endif
+
+#if !defined(CONFIG_HW_WDTOG_BASE)
+#error "*** CONFIG_HW_WDTOG_BASE not defined ***"
+#if !defined(CONFIG_HW_WDTOG_BIT)
+#error "*** CONFIG_HW_WDTOG_BIT not defined ***"
+#endif
+#endif
+
+#ifdef	CONFIG_HW_WDPORT_WRONLY	/* emulate read access */
+static unsigned __wd_ena_pio_portval = 0;
+#endif
+
+#define	WD_PIO_INIT_DONE(V)	((V) & (1 << CONFIG_HW_WDENA_BIT))
+
+void ssv_wd_pio_init(void)
+{
+	nios_pio_t *ena_piop	 = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
+	nios_pio_t *trg_piop	 = (nios_pio_t*)CONFIG_HW_WDTOG_BASE;
+
+	trg_piop->data		&= ~(1 << CONFIG_HW_WDTOG_BIT);
+
+#ifdef	CONFIG_HW_WDPORT_WRONLY	/* emulate read access */
+
+	__wd_ena_pio_portval	|= (1 << CONFIG_HW_WDENA_BIT);
+	ena_piop->data		 = __wd_ena_pio_portval;
+
+#else	/* !CONFIG_HW_WDPORT_WRONLY */
+
+	trg_piop->direction	|= (1 << CONFIG_HW_WDTOG_BIT);
+
+	ena_piop->data		|= (1 << CONFIG_HW_WDENA_BIT);
+	ena_piop->direction	|= (1 << CONFIG_HW_WDENA_BIT);
+
+#endif	/* CONFIG_HW_WDPORT_WRONLY */
+}
+
+void ssv_wd_pio_done(void)
+{
+	nios_pio_t *piop	 = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
+
+#ifdef	CONFIG_HW_WDPORT_WRONLY	/* emulate read access */
+
+	__wd_ena_pio_portval	&= ~(1 << CONFIG_HW_WDENA_BIT);
+	piop->data		 = __wd_ena_pio_portval;
+
+#else	/* !CONFIG_HW_WDPORT_WRONLY */
+
+	piop->data		&= ~(1 << CONFIG_HW_WDENA_BIT);
+
+#endif	/* CONFIG_HW_WDPORT_WRONLY */
+}
+
+void ssv_wd_pio_reset(void)
+{
+	nios_pio_t *trg_piop	 = (nios_pio_t*)CONFIG_HW_WDTOG_BASE;
+
+#ifdef	CONFIG_HW_WDPORT_WRONLY
+	if (WD_PIO_INIT_DONE(__wd_ena_pio_portval))
+#else
+	nios_pio_t *ena_piop	 = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
+
+	if (WD_PIO_INIT_DONE(ena_piop->data))
+#endif
+	{
+		trg_piop->data	|=  (1 << CONFIG_HW_WDTOG_BIT);
+		trg_piop->data	&= ~(1 << CONFIG_HW_WDTOG_BIT);
+	}
+}
+
+void hw_watchdog_reset(void)
+{
+	int re_enable = disable_interrupts ();
+
+	ssv_wd_pio_reset();
+	if (re_enable)
+		enable_interrupts ();
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	nios_pio_t *ena_piop	 = (nios_pio_t*)CONFIG_HW_WDENA_BASE;
+
+	switch (argc)
+	{
+	case 1:
+		printf ("Watchdog timer status is %s\n",
+#ifdef	CONFIG_HW_WDPORT_WRONLY
+				WD_PIO_INIT_DONE(__wd_ena_pio_portval)
+#else
+				WD_PIO_INIT_DONE(ena_piop->data)
+#endif
+				? "on" : "off");
+		return 0;
+	case 2:
+		if (!strcmp(argv[1],"on"))
+		{
+			ssv_wd_pio_init();
+			printf("Watchdog timer now is on\n");
+			return 0;
+		}
+		else if (!strcmp(argv[1],"off"))
+		{
+			ssv_wd_pio_done();
+			printf("Watchdog timer now is off\n");
+			return 0;
+		}
+		break;
+	default:
+		break;
+	}
+	printf ("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	wd,	2,	1,	do_wd,
+	"wd      - check and set watchdog\n",
+	"on   - switch watchDog on\n"
+	"wd off  - switch watchdog off\n"
+	"wd      - print current status\n"
+);
+#endif	/* CFG_CMD_BSP */
+#endif	/* CONFIG_HW_WATCHDOG */
diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile
new file mode 100755
index 0000000..d150df8
--- /dev/null
+++ b/board/stxgp3/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/stxgp3/config.mk b/board/stxgp3/config.mk
new file mode 100755
index 0000000..2427818
--- /dev/null
+++ b/board/stxgp3/config.mk
@@ -0,0 +1,32 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# Copied from ADS85xx for STx GP3 - Dan Malek
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/stxgp3/flash.c b/board/stxgp3/flash.c
new file mode 100755
index 0000000..032989b
--- /dev/null
+++ b/board/stxgp3/flash.c
@@ -0,0 +1,515 @@
+/*
+ * (C) Copyright 2003, Dan Malek, Embedded Edge, LLC.  <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updated to support the Silicon Tx GP3 8560.  We should only find
+ * two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash),
+ * but I left other code here in case people order custom boards.
+ *
+ * (C) Copyright 2003 Motorola Inc.
+ *  Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F640C3T:	printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+#ifdef DEBUG
+	printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+	udelay(20);
+	asm("sync");
+
+	value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+	printf("manufacturer=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case MT_MANUFACT:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];             /* device ID            */
+
+#ifdef DEBUG
+	printf("deviceID=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+
+	case (INTEL_ID_28F640C3T):
+		info->flash_id += FLASH_28F640C3T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		sector_offset = 0x20000;
+		break;				/* => 2x8 MB		*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table
+	 * The first 127 blocks are large, the last 8 are small.
+	 */
+	for (i = 0; i < 127; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* Sectors are locked upon reset */
+		info->protect[i] = 0;
+	}
+	for (i = 127; i < 135; i++) {
+		info->start[i] = base;
+		base += 0x4000;
+		/* Sectors are locked upon reset */
+		info->protect[i] = 0;
+	}
+
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+		asm("sync");
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	printf("\nFlash Erase:\n");
+#endif
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+	/* Start erase on unprotected sectors */
+#if defined(DEBUG)
+	printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+			asm("sync");
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Reset Array */
+			*addr = 0xffffffff;
+			asm("sync");
+			/* Clear Status Register */
+			*addr = 0x50505050;
+			asm("sync");
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			asm("sync");
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+			asm("sync");
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = 0xD0D0D0D0;
+			    asm("sync");
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if(*addr & 0x00200020){
+					printf("Error in Block Erase - Lock Bit may be set!\n");
+					printf("Status Register = 0x%X\n", (uint)*addr);
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+			asm("sync");
+		}
+	}
+
+	printf ("flash erase done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+	asm("sync");
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+
+	while (((csr = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x40404040) {
+		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	asm("sync");
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+	asm("sync");
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long  * addr)
+{
+	ulong start, now;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	asm("sync");
+	/* Clear Status Register */
+	*addr = 0x50505050;
+	asm("sync");
+
+	*addr = 0x60606060;
+	asm("sync");
+	*addr = 0xd0d0d0d0;
+	asm("sync");
+
+	start = get_timer (0);
+	while((*addr & 0x00800080) != 0x00800080){
+		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			asm("sync");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S
new file mode 100755
index 0000000..d504289
--- /dev/null
+++ b/board/stxgp3/init.S
@@ -0,0 +1,286 @@
+/*
+ * Copyright (C) 2004 Embedded Edge, LLC
+ * Dan Malek <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updates for Silicon Tx GP3 8560.  We only support 32-bit flash
+ * and DDR with SPD EEPROM configuration.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xfc000000	16K	Configuration Latch register
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 8, 9:	128M	DDR
+	 * 0x00000000	64M	DDR System memory
+	 * 0x04000000	64M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+#error("Update the number of table entries in tlb1_entry")
+	.long TLB1_MAS0(1, 8, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1, 9, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,1,0,1,0,1)
+#endif
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xfc00_0000     0xfc00_ffff     Config Latch            64K
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x05
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4
+	entry_end
diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c
new file mode 100755
index 0000000..2b3949c
--- /dev/null
+++ b/board/stxgp3/stxgp3.c
@@ -0,0 +1,382 @@
+/*
+ * (C) Copyright 2003, Embedded Edge, LLC
+ * Dan Malek, <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updates for Silicon Tx GP3 8560
+ *
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <asm/io.h>
+#include <spd.h>
+#include <miiphy.h>
+
+long int fixed_sdram (void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RxD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TxD */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   0,   0   }, /* I2C CLK */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+static	uint64_t	next_led_update;
+static	uint		led_bit;
+
+int
+board_early_init_f(void)
+{
+#if defined(CONFIG_PCI)
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+    pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+void
+reset_phy(void)
+{
+	volatile uint *blatch;
+
+	blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE;
+
+	/* reset Giga bit Ethernet port if needed here */
+
+	*blatch &= ~0x000000c0;
+	udelay(100);
+	*blatch = 0x000000c1;	/* Light one led, too */
+	udelay(1000);
+
+#if 0	/* This is the port we really want to use for debugging. */
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr->bcsr2 &= ~FETH2_RST;
+	udelay(2);
+	bcsr->bcsr2 |=  FETH2_RST;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr->bcsr3 &= ~FETH3_RST;
+	udelay(2);
+	bcsr->bcsr3 |=  FETH3_RST;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	/* reset PHY */
+	miiphy_reset("FCC1 ETHERNET", 0x0);
+
+	/* change PHY address to 0x02 */
+	bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+	bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+#endif
+}
+
+int
+checkboard(void)
+{
+	printf ("Board: Silicon Tx GPPP 8560 Board\n");
+	return (0);
+}
+
+/* Blinkin' LEDS for Robert.
+*/
+void
+show_activity(int flag)
+{
+	volatile uint *blatch;
+
+	if (next_led_update > get_ticks())
+		return;
+
+	blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE;
+
+	led_bit >>= 1;
+	if (led_bit == 0)
+		led_bit = 0x08;
+	*blatch = (0xc0 | led_bit);
+	eieio();
+	next_led_update += (get_tbclk() / 4);
+}
+
+long int
+initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+#if defined(CONFIG_DDR_DLL)
+	{
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+		uint temp_ddrdll = 0;
+
+		/* Work around to stabilize DDR DLL */
+		temp_ddrdll = gur->ddrdllcr;
+		gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	dram_size = spd_sdram ();
+
+#if defined(CONFIG_DDR_ECC)
+	/* Initialize and enable DDR ECC.
+	*/
+	ddr_enable_ecc(dram_size);
+#endif
+
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_stxgp3_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_stxgp3_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds
new file mode 100755
index 0000000..3bc6150
--- /dev/null
+++ b/board/stxgp3/u-boot.lds
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2003 Embedded Edge, LLC
+ * Dan Malek, <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updates for Silicon Tx GP3 8560.
+ *
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/stxgp3/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/stxgp3/init.o (.text)
+    cpu/mpc85xx/commproc.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/serial_scc.o (.text)
+    cpu/mpc85xx/ether_fcc.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/i2c.o (.text)
+    cpu/mpc85xx/spd_sdram.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/stxxtc/Makefile b/board/stxxtc/Makefile
new file mode 100755
index 0000000..11065cf
--- /dev/null
+++ b/board/stxxtc/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o oftree.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+%.dtb: %.dts
+	dtc -f -V 0x10 -I dts -O dtb $< >$@
+
+%.c: %.dtb
+	xxd -i $< \
+	   | sed -e "s/^unsigned char/const unsigned char/g" \
+	   | sed -e "s/^unsigned int/const unsigned int/g" > $@
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/stxxtc/config.mk b/board/stxxtc/config.mk
new file mode 100755
index 0000000..f5dc034
--- /dev/null
+++ b/board/stxxtc/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# STx XTc
+#
+
+TEXT_BASE = 0x40F00000
diff --git a/board/stxxtc/oftree.dts b/board/stxxtc/oftree.dts
new file mode 100755
index 0000000..e3f3017
--- /dev/null
+++ b/board/stxxtc/oftree.dts
@@ -0,0 +1,52 @@
+/ {
+	model = "STXXTC V1";
+	compatible = "STXXTC";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		linux,phandle = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		PowerPC,MPC870@0 {
+			linux,phandle = <3>;
+			name = "PowerPC,MPC870";
+			device_type = "cpu";
+			reg = <0>;
+			clock-frequency = <0>;		/* place-holder for runtime fillup */
+			timebase-frequency = <0>;	/* dido */
+			linux,boot-cpu;
+			i-cache-size = <2000>;
+			d-cache-size = <2000>;
+			32-bit;
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <00000000 00000000 00000000 20000000>;
+	};
+
+	/* copy of the bd_t information (place-holders) */
+	bd_t {
+		memstart	= <0>;
+		memsize		= <0>;
+		flashstart	= <0>;
+		flashsize	= <0>;
+		flashoffset	= <0>;
+		sramstart	= <0>;
+		sramsize	= <0>;
+
+		immr_base	= <0>;
+
+		bootflags	= <0>;
+		ip_addr		= <0>;
+		enetaddr	= [ 00 00 00 00 00 00 ];
+		ethspeed	= <0>;
+		intfreq		= <0>;
+		busfreq		= <0>;
+
+		baudrate	= <0>;
+	};
+
+};
diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c
new file mode 100755
index 0000000..aa3d129
--- /dev/null
+++ b/board/stxxtc/stxxtc.c
@@ -0,0 +1,638 @@
+/*
+ * (C) Copyright 2000-2004
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2005
+ * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * U-Boot port on STx XTc board
+ * Mostly copied from Netta
+ */
+
+#include <common.h>
+#include <miiphy.h>
+
+#include "mpc8xx.h"
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+/****************************************************************/
+
+/* some sane bit macros */
+#define _BD(_b)				(1U << (31-(_b)))
+#define _BDR(_l, _h)			(((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
+
+#define _BW(_b)				(1U << (15-(_b)))
+#define _BWR(_l, _h)			(((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
+
+#define _BB(_b)				(1U << (7-(_b)))
+#define _BBR(_l, _h)			(((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
+
+#define _B(_b)				_BD(_b)
+#define _BR(_l, _h)			_BDR(_l, _h)
+
+/****************************************************************/
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 always.
+ */
+
+int checkboard(void)
+{
+	printf ("Silicon Turnkey eXpress XTc\n");
+	return (0);
+}
+
+/****************************************************************/
+
+#define _NOT_USED_	0xFFFFFFFF
+
+/****************************************************************/
+
+#define CS_0000		0x00000000
+#define CS_0001		0x10000000
+#define CS_0010		0x20000000
+#define CS_0011		0x30000000
+#define CS_0100		0x40000000
+#define CS_0101		0x50000000
+#define CS_0110		0x60000000
+#define CS_0111		0x70000000
+#define CS_1000		0x80000000
+#define CS_1001		0x90000000
+#define CS_1010		0xA0000000
+#define CS_1011		0xB0000000
+#define CS_1100		0xC0000000
+#define CS_1101		0xD0000000
+#define CS_1110		0xE0000000
+#define CS_1111		0xF0000000
+
+#define BS_0000		0x00000000
+#define BS_0001		0x01000000
+#define BS_0010		0x02000000
+#define BS_0011		0x03000000
+#define BS_0100		0x04000000
+#define BS_0101		0x05000000
+#define BS_0110		0x06000000
+#define BS_0111		0x07000000
+#define BS_1000		0x08000000
+#define BS_1001		0x09000000
+#define BS_1010		0x0A000000
+#define BS_1011		0x0B000000
+#define BS_1100		0x0C000000
+#define BS_1101		0x0D000000
+#define BS_1110		0x0E000000
+#define BS_1111		0x0F000000
+
+#define GPL0_AAAA	0x00000000
+#define GPL0_AAA0	0x00200000
+#define GPL0_AAA1	0x00300000
+#define GPL0_000A	0x00800000
+#define GPL0_0000	0x00A00000
+#define GPL0_0001	0x00B00000
+#define GPL0_111A	0x00C00000
+#define GPL0_1110	0x00E00000
+#define GPL0_1111	0x00F00000
+
+#define GPL1_0000	0x00000000
+#define GPL1_0001	0x00040000
+#define GPL1_1110	0x00080000
+#define GPL1_1111	0x000C0000
+
+#define GPL2_0000	0x00000000
+#define GPL2_0001	0x00010000
+#define GPL2_1110	0x00020000
+#define GPL2_1111	0x00030000
+
+#define GPL3_0000	0x00000000
+#define GPL3_0001	0x00004000
+#define GPL3_1110	0x00008000
+#define GPL3_1111	0x0000C000
+
+#define GPL4_0000	0x00000000
+#define GPL4_0001	0x00001000
+#define GPL4_1110	0x00002000
+#define GPL4_1111	0x00003000
+
+#define GPL5_0000	0x00000000
+#define GPL5_0001	0x00000400
+#define GPL5_1110	0x00000800
+#define GPL5_1111	0x00000C00
+#define LOOP		0x00000080
+
+#define EXEN		0x00000040
+
+#define AMX_COL		0x00000000
+#define AMX_ROW		0x00000020
+#define AMX_MAR		0x00000030
+
+#define NA		0x00000008
+
+#define UTA		0x00000004
+
+#define TODT		0x00000002
+
+#define LAST		0x00000001
+
+#define A10_AAAA	GPL0_AAAA
+#define A10_AAA0	GPL0_AAA0
+#define A10_AAA1	GPL0_AAA1
+#define A10_000A	GPL0_000A
+#define A10_0000	GPL0_0000
+#define A10_0001	GPL0_0001
+#define A10_111A	GPL0_111A
+#define A10_1110	GPL0_1110
+#define A10_1111	GPL0_1111
+
+#define RAS_0000	GPL1_0000
+#define RAS_0001	GPL1_0001
+#define RAS_1110	GPL1_1110
+#define RAS_1111	GPL1_1111
+
+#define CAS_0000	GPL2_0000
+#define CAS_0001	GPL2_0001
+#define CAS_1110	GPL2_1110
+#define CAS_1111	GPL2_1111
+
+#define WE_0000		GPL3_0000
+#define WE_0001		GPL3_0001
+#define WE_1110		GPL3_1110
+#define WE_1111		GPL3_1111
+
+/* #define CAS_LATENCY	3  */
+#define CAS_LATENCY	2
+
+const uint sdram_table[0x40] = {
+
+#if CAS_LATENCY == 3
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,				/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,		/* NOP	 */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP	 */
+	CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,			/* PALL  */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+#endif
+
+#if CAS_LATENCY == 2
+	/* RSS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* RBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,			/* READ  */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,			/* WRITE */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/* WBS */
+	CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* ACT   */
+	CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,				/* NOP   */
+	CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,				/* WRITE */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,				/* NOP   */
+	CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,			/* NOP   */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,	/* PALL  */
+	_NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+#endif
+
+	/* UPT */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,		/* ATRFR */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,			/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,		/* NOP   */
+	CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,	/* NOP   */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
+	CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
+};
+
+static const uint nandcs_table[0x40] = {
+	/* RSS */
+	CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_0000 | GPL5_1111,
+	CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,	/* NOP   */
+
+	/* RBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* WSS */
+	CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
+	CS_0000 | GPL4_1111 | GPL5_1111,
+	CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
+
+	/* WBS */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+
+	/* UPT */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_,
+
+	/* EXC */
+	CS_0001 | LAST,
+	_NOT_USED_,
+
+	/* REG */
+	CS_1110 ,
+	CS_0001 | LAST,
+};
+
+/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
+/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
+#define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
+
+/* 9 */
+#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+void check_ram(unsigned int addr, unsigned int size)
+{
+	unsigned int i, j, v, vv;
+	volatile unsigned int *p;
+	unsigned int pv;
+
+	p = (unsigned int *)addr;
+	pv = (unsigned int)p;
+	for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
+		*p++ = pv;
+
+	p = (unsigned int *)addr;
+	for (i = 0; i < size / sizeof(unsigned int); i++) {
+		v = (unsigned int)p;
+		vv = *p;
+		if (vv != v) {
+			printf("%p: read %08x instead of %08x\n", p, vv, v);
+			hang();
+		}
+		p++;
+	}
+
+	for (j = 0; j < 5; j++) {
+		switch (j) {
+			case 0: v = 0x00000000; break;
+			case 1: v = 0xffffffff; break;
+			case 2: v = 0x55555555; break;
+			case 3: v = 0xaaaaaaaa; break;
+			default:v = 0xdeadbeef; break;
+		}
+		p = (unsigned int *)addr;
+		for (i = 0; i < size / sizeof(unsigned int); i++) {
+			*p = v;
+			vv = *p;
+			if (vv != v) {
+				printf("%p: read %08x instead of %08x\n", p, vv, v);
+				hang();
+			}
+			*p = ~v;
+			p++;
+		}
+	}
+}
+
+#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
+
+long int initdram(int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size;
+	u32 d1, d2;
+
+	upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
+
+	/*
+	 * Preliminary prescaler for refresh
+	 */
+	memctl->memc_mptpr = MPTPR_PTP_DIV8;
+
+	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
+
+	/*
+	 * Map controller bank 3 to the SDRAM bank at preliminary address.
+	 */
+	memctl->memc_or4 = CFG_OR4_PRELIM;
+	memctl->memc_br4 = CFG_BR4_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+
+	udelay(200);
+
+	/* perform SDRAM initialisation sequence */
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C);	/* precharge all		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30);	/* refresh 2 times(0)		*/
+	udelay(1);
+
+	memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E);	/* exception program (write mar)*/
+	udelay(1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay(10000);
+
+
+	d1 = 0xAA55AA55;
+	*(volatile u32 *)0 = d1;
+	d2 = *(volatile u32 *)0;
+	if (d1 != d2) {
+		printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+		DO_LOOP;
+	}
+
+	d1 = 0x55AA55AA;
+	*(volatile u32 *)0 = d1;
+	d2 = *(volatile u32 *)0;
+	if (d1 != d2) {
+		printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+		DO_LOOP;
+	}
+
+	d1 = 0x12345678;
+	*(volatile u32 *)0 = d1;
+	d2 = *(volatile u32 *)0;
+	if (d1 != d2) {
+		printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
+		DO_LOOP;
+	}
+
+	size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
+
+	return size;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phys(void)
+{
+	int phyno;
+	unsigned short v;
+
+	udelay(10000);
+	/* reset the damn phys */
+	mii_init();
+
+	for (phyno = 0; phyno < 32; ++phyno) {
+		miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v);
+		if (v == 0xFFFF)
+			continue;
+		miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD);
+		udelay(10000);
+		miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+		udelay(10000);
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* GP = general purpose, SP = special purpose (on chip peripheral) */
+
+/* bits that can have a special purpose or can be configured as inputs/outputs */
+#define PA_GP_INMASK	_BW(6)
+#define PA_GP_OUTMASK	(_BW(7))
+#define PA_SP_MASK	0
+#define PA_ODR_VAL	0
+#define PA_GP_OUTVAL	(_BW(7))
+#define PA_SP_DIRVAL	0
+
+#define PB_GP_INMASK	0
+#define PB_GP_OUTMASK	(_B(23))
+#define PB_SP_MASK	0
+#define PB_ODR_VAL	0
+#define PB_GP_OUTVAL	(_B(23))
+#define PB_SP_DIRVAL	0
+
+#define PC_GP_INMASK	0
+#define PC_GP_OUTMASK	(_BW(15))
+
+#define PC_SP_MASK	0
+#define PC_SOVAL	0
+#define PC_INTVAL	0
+#define PC_GP_OUTVAL	0
+#define PC_SP_DIRVAL	0
+
+#define PE_GP_INMASK	0
+#define PE_GP_OUTMASK	0
+#define PE_GP_OUTVAL	0
+
+#define PE_SP_MASK	0
+#define PE_ODR_VAL	0
+#define PE_SP_DIRVAL	0
+
+int board_early_init_f(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile iop8xx_t *ioport = &immap->im_ioport;
+	volatile cpm8xx_t *cpm = &immap->im_cpm;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	(void)ioport;
+	(void)cpm;
+#if 1
+	/* NAND chip select */
+	upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
+	memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
+	memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
+	memctl->memc_mbmr = 0;	/* all clear */
+#endif
+
+	memctl->memc_br5 &= ~BR_V;
+	memctl->memc_br6 &= ~BR_V;
+	memctl->memc_br7 &= ~BR_V;
+
+#if 1
+	ioport->iop_padat	= PA_GP_OUTVAL;
+	ioport->iop_paodr	= PA_ODR_VAL;
+	ioport->iop_padir	= PA_GP_OUTMASK | PA_SP_DIRVAL;
+	ioport->iop_papar	= PA_SP_MASK;
+
+	cpm->cp_pbdat		= PB_GP_OUTVAL;
+	cpm->cp_pbodr		= PB_ODR_VAL;
+	cpm->cp_pbdir		= PB_GP_OUTMASK | PB_SP_DIRVAL;
+	cpm->cp_pbpar		= PB_SP_MASK;
+
+	ioport->iop_pcdat	= PC_GP_OUTVAL;
+	ioport->iop_pcdir	= PC_GP_OUTMASK | PC_SP_DIRVAL;
+	ioport->iop_pcso	= PC_SOVAL;
+	ioport->iop_pcint	= PC_INTVAL;
+	ioport->iop_pcpar	= PC_SP_MASK;
+
+	cpm->cp_pedat		= PE_GP_OUTVAL;
+	cpm->cp_peodr		= PE_ODR_VAL;
+	cpm->cp_pedir		= PE_GP_OUTMASK | PE_SP_DIRVAL;
+	cpm->cp_pepar		= PE_SP_MASK;
+#endif
+
+	return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <linux/mtd/nand.h>
+
+extern ulong nand_probe(ulong physadr);
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+void nand_init(void)
+{
+	unsigned long totlen;
+
+	totlen = nand_probe(CFG_NAND_BASE);
+	printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
+#ifdef CONFIG_HW_WATCHDOG
+
+void hw_watchdog_reset(void)
+{
+	/* XXX add here the really funky stuff */
+}
+
+#endif
+
+#ifdef CONFIG_SHOW_ACTIVITY
+
+/* called from timer interrupt every 1/CFG_HZ sec */
+void board_show_activity(ulong timestamp)
+{
+}
+
+/* called when looping */
+void show_activity(int arg)
+{
+}
+
+#endif
+
+#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	/* printf("overwrite_console called\n"); */
+	return 0;
+}
+#endif
+
+extern int drv_phone_init(void);
+extern int drv_phone_use_me(void);
+extern int drv_phone_is_idle(void);
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	reset_phys();
+
+	return 0;
+}
diff --git a/board/stxxtc/u-boot.lds b/board/stxxtc/u-boot.lds
new file mode 100755
index 0000000..9f2901c
--- /dev/null
+++ b/board/stxxtc/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp		: { *(.interp)		}
+  .hash         : { *(.hash)		}
+  .dynsym       : { *(.dynsym)		}
+  .dynstr       : { *(.dynstr)		}
+  .rel.text     : { *(.rel.text)	}
+  .rela.text    : { *(.rela.text) 	}
+  .rel.data     : { *(.rel.data)	}
+  .rela.data    : { *(.rela.data) 	}
+  .rel.rodata   : { *(.rel.rodata) 	}
+  .rela.rodata  : { *(.rela.rodata)	}
+  .rel.got      : { *(.rel.got)		}
+  .rela.got     : { *(.rela.got)	}
+  .rel.ctors    : { *(.rel.ctors)	}
+  .rela.ctors   : { *(.rela.ctors)	}
+  .rel.dtors    : { *(.rel.dtors)	}
+  .rela.dtors   : { *(.rela.dtors)	}
+  .rel.bss      : { *(.rel.bss)		}
+  .rela.bss     : { *(.rela.bss)	}
+  .rel.plt      : { *(.rel.plt)		}
+  .rela.plt     : { *(.rela.plt)	}
+  .init         : { *(.init)		}
+  .plt			: { *(.plt) 		}
+  .text      	:
+  {
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/stxxtc/u-boot.lds.debug b/board/stxxtc/u-boot.lds.debug
new file mode 100755
index 0000000..004e7fd
--- /dev/null
+++ b/board/stxxtc/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/svm_sc8xx/Makefile b/board/svm_sc8xx/Makefile
new file mode 100755
index 0000000..13ce9fc
--- /dev/null
+++ b/board/svm_sc8xx/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/svm_sc8xx/config.mk b/board/svm_sc8xx/config.mk
new file mode 100755
index 0000000..4bec9cb
--- /dev/null
+++ b/board/svm_sc8xx/config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c
new file mode 100755
index 0000000..25e61dd
--- /dev/null
+++ b/board/svm_sc8xx/flash.c
@@ -0,0 +1,797 @@
+/*
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef	CFG_ENV_ADDR
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+#if 0
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+#endif
+#ifdef  CONFIG_BOOT_8B
+static int my_in_8( unsigned char *addr);
+static  void my_out_8( unsigned char *addr, int val);
+#endif
+#ifdef  CONFIG_BOOT_16B
+static  int my_in_be16( unsigned short *addr);
+static  void my_out_be16( unsigned short *addr, int val);
+#endif
+#ifdef  CONFIG_BOOT_32B
+static  unsigned my_in_be32( unsigned *addr);
+static  void my_out_be32( unsigned *addr, int val);
+#endif
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	size_b0=0;
+	size_b1=0;
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+#ifdef CFG_DOC_BASE
+#ifndef CONFIG_FEL8xx_AT
+	memctl->memc_or5 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */
+	memctl->memc_br5 = CFG_DOC_BASE | 0x401;
+#else
+	memctl->memc_or3 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */
+	memctl->memc_br3 = CFG_DOC_BASE | 0x401;
+#endif
+#endif
+#if defined( CONFIG_BOOT_8B)
+/*        memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */
+/*        memctl->memc_br0 = 0x40000401; */
+	size_b0 = 0x80000;  /* 512 K */
+	flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040;
+	flash_info[0].sector_count = 8;
+	flash_info[0].size = 0x00080000;
+	/* set up sector start address table */
+	for (i = 0; i < flash_info[0].sector_count; i++)
+	flash_info[0].start[i] = 0x40000000 + (i * 0x10000);
+	/* protect all sectors */
+	for (i = 0; i < flash_info[0].sector_count; i++)
+	flash_info[0].protect[i] = 0x1;
+#elif defined (CONFIG_BOOT_16B)
+/*        memctl->memc_or0 = 0xfff80ff4; /###* 4MB bytes */
+/*        memctl->memc_br0 = 0x40000401; */
+	size_b0 = 0x400000;  /* 4MB , assume AMD29LV320B */
+	flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B;
+	flash_info[0].sector_count = 67;
+	flash_info[0].size = 0x00400000;
+	/* set up sector start address table */
+	flash_info[0].start[0] = 0x40000000  ;
+	flash_info[0].start[1] = 0x40000000 + 0x4000;
+	flash_info[0].start[2] = 0x40000000 + 0x6000;
+	flash_info[0].start[3] = 0x40000000 + 0x8000;
+	for (i = 4; i < flash_info[0].sector_count; i++)
+	flash_info[0].start[i] = 0x40000000 + 0x10000 + ((i-4) * 0x10000);
+	/* protect all sectors */
+	for (i = 0; i < flash_info[0].sector_count; i++)
+	flash_info[0].protect[i] = 0x1;
+#endif
+
+
+#ifdef CONFIG_BOOT_32B
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V;
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+	}
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+
+#endif  /* CONFIG_BOOT_32B */
+
+	return (size_b0 + size_b1);
+}
+#if 0
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+}
+#endif
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#if 0
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	switch (value) {
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect,in_mid,in_did;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+#if defined (CONFIG_BOOT_8B )
+	my_out_8( (unsigned char * )  ((ulong)addr+0x555) , 0xaa );
+	my_out_8( (unsigned char * )  ((ulong)addr+0x2aa) , 0x55 );
+	my_out_8( (unsigned char * )  ((ulong)addr+0x555) , 0x90 );
+	in_mid=my_in_8( (unsigned char * ) addr );
+	in_did=my_in_8( (unsigned char * ) ((ulong)addr+1) );
+	printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
+	my_out_8( (unsigned char *)addr, 0xf0);
+	udelay(1);
+	my_out_8(     (unsigned char *) ((ulong)addr+0x555),0xaa );
+	my_out_8(     (unsigned char *) ((ulong)addr+0x2aa),0x55 );
+	my_out_8(     (unsigned char *) ((ulong)addr+0x555),0x80 );
+	my_out_8(     (unsigned char *) ((ulong)addr+0x555),0xaa );
+	my_out_8(     (unsigned char *) ((ulong)addr+0x2aa),0x55 );
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			/*addr[0] = 0x00300030; */
+			my_out_8(     (unsigned char *) ((ulong)addr),0x30 );
+			l_sect = sect;
+		}
+	}
+#elif defined(CONFIG_BOOT_16B )
+	my_out_be16( (unsigned short * )  ((ulong)addr+ (0xaaa)) , 0xaa );
+	my_out_be16( (unsigned short * )  ((ulong)addr+ (0x554)) , 0x55 );
+	my_out_be16( (unsigned short * )  ((ulong)addr+ (0xaaa)) , 0x90 );
+	in_mid=my_in_be16( (unsigned short * ) addr );
+	in_did=my_in_be16 ( (unsigned short * ) ((ulong)addr+2) );
+	printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
+	my_out_be16( (unsigned short *)addr, 0xf0);
+	udelay(1);
+	my_out_be16(     (unsigned short *) ((ulong)addr+ 0xaaa),0xaa );
+	my_out_be16(     (unsigned short *) ((ulong)addr+0x554),0x55 );
+	my_out_be16(     (unsigned short *) ((ulong)addr+0xaaa),0x80 );
+	my_out_be16(     (unsigned short *) ((ulong)addr+0xaaa),0xaa );
+	my_out_be16(     (unsigned short *) ((ulong)addr+0x554),0x55 );
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			my_out_be16(     (unsigned short *) ((ulong)addr),0x30 );
+			l_sect = sect;
+		}
+	}
+
+#elif defined(CONFIG_BOOT_32B)
+	my_out_be32( (unsigned * )  ((ulong)addr+0x1554) , 0xaa );
+	my_out_be32( (unsigned * )  ((ulong)addr+0xaa8) , 0x55 );
+	my_out_be32( (unsigned  *)  ((ulong)addr+0x1554) , 0x90 );
+	in_mid=my_in_be32( (unsigned  * ) addr );
+	in_did=my_in_be32( (unsigned  * ) ((ulong)addr+4) );
+	printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
+	my_out_be32( (unsigned *)addr, 0xf0);
+	udelay(1);
+	my_out_be32(     (unsigned  *) ((ulong)addr+0x1554),0xaa );
+	my_out_be32(     (unsigned  *) ((ulong)addr+0xaa8),0x55 );
+	my_out_be32(     (unsigned  *) ((ulong)addr+0x1554),0x80 );
+	my_out_be32(     (unsigned  *) ((ulong)addr+0x1554),0xaa );
+	my_out_be32(     (unsigned  *) ((ulong)addr+0xaa8),0x55 );
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			my_out_be32(     (unsigned *) ((ulong)addr),0x00300030 );
+			l_sect = sect;
+		}
+	}
+
+#else
+# error CONFIG_BOOT_(size)B missing.
+#endif
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+#if defined (CONFIG_BOOT_8B)
+	while (  (my_in_8((unsigned char *)addr) & 0x80) != 0x80 )
+#elif defined(CONFIG_BOOT_16B )
+	while (  (my_in_be16((unsigned short *)addr) & 0x0080) != 0x0080 )
+#elif defined(CONFIG_BOOT_32B)
+	while (  (my_in_be32((unsigned  *)addr) & 0x00800080) != 0x00800080 )
+#else
+# error CONFIG_BOOT_(size)B missing.
+#endif
+	{
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+#if defined (CONFIG_BOOT_8B)
+	my_out_8( (unsigned char *)addr, 0xf0);
+#elif defined(CONFIG_BOOT_16B )
+	my_out_be16( (unsigned short * ) addr , 0x00f0 );
+#elif defined(CONFIG_BOOT_32B)
+	my_out_be32 ( (unsigned *)addr,  0x00F000F0 );	/* reset bank */
+#else
+# error CONFIG_BOOT_(size)B missing.
+#endif
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	ulong addr = (ulong)(info->start[0]);
+	ulong start,last;
+	int flag;
+	ulong i;
+	int  data_short[2];
+
+	/* Check if Flash is (sufficiently) erased */
+	if ( ((ulong)  *(ulong *)dest & data) != data ) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+#if defined(CONFIG_BOOT_8B)
+#ifdef DEBUG
+	{
+	int in_mid,in_did;
+	my_out_8( (unsigned char * )  (addr+0x555) , 0xaa );
+	my_out_8( (unsigned char * )  (addr+0x2aa) , 0x55 );
+	my_out_8( (unsigned char * )  (addr+0x555) , 0x90 );
+	in_mid=my_in_8( (unsigned char * ) addr );
+	in_did=my_in_8( (unsigned char * ) (addr+1) );
+	printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did );
+	my_out_8( (unsigned char *)addr, 0xf0);
+	udelay(1);
+	}
+#endif
+      {
+	int  data_ch[4];
+	data_ch[0]=(int ) ((data>>24) & 0xff);
+	data_ch[1]=(int ) ((data>>16) &0xff );
+	data_ch[2]=(int ) ((data >>8) & 0xff);
+	data_ch[3]=(int ) (data & 0xff);
+	for (i=0;i<4;i++ ){
+	  my_out_8( (unsigned char *) (addr+0x555),0xaa);
+	  my_out_8((unsigned char *) (addr+0x2aa),0x55);
+	  my_out_8( (unsigned char *)  (addr+0x555),0xa0);
+	  my_out_8((unsigned char *)  (dest+i) ,data_ch[i]);
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	  start = get_timer (0);
+	last  = start;
+	  while(  ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i]  ) ) {
+		  if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) {
+			  return 1;
+		  }
+	  }
+	}/* for */
+     }
+#elif defined( CONFIG_BOOT_16B)
+	data_short[0]=(int) (data>>16) & 0xffff;
+	data_short[1]=(int ) data & 0xffff ;
+	for (i=0;i<2;i++ ){
+	my_out_be16(     (unsigned short *) ((ulong)addr+ 0xaaa),0xaa );
+	my_out_be16(     (unsigned short *) ((ulong)addr+ 0x554),0x55 );
+	my_out_be16(     (unsigned short *) ((ulong)addr+ 0xaaa),0xa0 );
+	my_out_be16(  (unsigned short *) (dest+(i*2)) ,data_short[i]);
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+	  start = get_timer (0);
+	last  = start;
+	  while(  ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i]  ) ) {
+		  if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) {
+			  return 1;
+		  }
+	  }
+	}
+#elif defined( CONFIG_BOOT_32B)
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+#endif
+
+
+	return (0);
+}
+#ifdef  CONFIG_BOOT_8B
+static int my_in_8  ( unsigned char *addr)
+{
+       int ret;
+       __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+       return ret;
+}
+
+static void my_out_8  ( unsigned char *addr, int val)
+{
+       __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+#endif
+#ifdef  CONFIG_BOOT_16B
+static int my_in_be16( unsigned short *addr)
+{
+       int ret;
+	__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+				return ret;
+}
+static void my_out_be16( unsigned short *addr, int val)
+{
+       __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+#endif
+#ifdef  CONFIG_BOOT_32B
+static  unsigned my_in_be32( unsigned *addr)
+{
+	unsigned ret;
+	__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+				return ret;
+}
+static  void my_out_be32( unsigned *addr, int val)
+{
+       __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+#endif
diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c
new file mode 100755
index 0000000..9bb9fd0
--- /dev/null
+++ b/board/svm_sc8xx/svm_sc8xx.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+const uint sdram_table[] =
+{
+/*-----------------
+ UPM A contents:
+----------------- */
+/*---------------------------------------------------
+ Read Single Beat Cycle. Offset 0 in the RAM array.
+---------------------------------------------------- */
+0x1f07fc04,  0xeeaefc04,  0x11adfc04,  0xefbbbc00 ,
+0x1ff77c47,  0x1ff77c35,  0xefeabc34,  0x1fb57c35 ,
+/*------------------------------------------------
+ Read Burst Cycle. Offset 0x8 in the RAM array.
+------------------------------------------------ */
+0x1f07fc04,  0xeeaefc04,  0x10adfc04,  0xf0affc00,
+0xf0affc00,  0xf1affc00,  0xefbbbc00,  0x1ff77c47,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff,
+/*-------------------------------------------------------
+ Write Single Beat Cycle. Offset 0x18 in the RAM array
+------------------------------------------------------- */
+0x1f27fc04,  0xeeaebc00,  0x01b93c04,  0x1ff77c47 ,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
+/*-------------------------------------------------
+ Write Burst Cycle. Offset 0x20 in the RAM array
+------------------------------------------------- */
+0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
+/*------------------------------------------------------------------------
+ Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array
+------------------------------------------------------------------------ */
+0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
+0xffffffff,  0xffffffff,  0xffffffff,  0xffffffff ,
+/*-----------
+*  Exception:
+*  ----------- */
+0x7ffefc07,  0xffffffff,  0xffffffff,  0xffffffff ,
+};
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (SVM8...)
+ *
+ * Return 1 for "SC8xx" type, 0 else.
+ */
+
+int checkboard (void)
+{
+    char *s = getenv("serial#");
+    int board_type;
+
+    if (!s || strncmp(s, "SVM8", 4)) {
+	printf ("### No HW ID - assuming SVM SC8xx\n");
+	return (0);
+    }
+
+    board_type = 1;
+
+    for (; *s; ++s) {
+	if (*s == ' ')
+	    break;
+	putc (*s);
+    }
+
+    putc ('\n');
+
+    return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size_b0 = 0;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	memctl->memc_mptpr = CFG_MPTPR;
+#if defined (CONFIG_SDRAM_16M)
+	memctl->memc_mamr = 0x00802114 | CFG_MxMR_PTx;
+	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
+	udelay(1);
+	memctl->memc_mcr  = 0x80002830;
+	udelay(1);
+	memctl->memc_mar  = 0x00000088;
+	udelay(1);
+	memctl->memc_mcr  = 0x80002106;
+	udelay(1);
+	memctl->memc_or1 =  0xff000a00;
+	size_b0 = 0x01000000;
+#elif defined (CONFIG_SDRAM_32M)
+	memctl->memc_mamr = 0x00904114 | CFG_MxMR_PTx;
+	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
+	udelay(1);
+	memctl->memc_mcr  = 0x80002830;
+	udelay(1);
+	memctl->memc_mar  = 0x00000088;
+	udelay(1);
+	memctl->memc_mcr  = 0x80002106;
+	udelay(1);
+	memctl->memc_or1 =  0xfe000a00;
+	size_b0 = 0x02000000;
+#elif defined (CONFIG_SDRAM_64M)
+	memctl->memc_mamr = 0x00a04114 | CFG_MxMR_PTx;
+	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
+	udelay(1);
+	memctl->memc_mcr  = 0x80002830;
+	udelay(1);
+	memctl->memc_mar  = 0x00000088;
+	udelay(1);
+	memctl->memc_mcr  = 0x80002106;
+	udelay(1);
+	memctl->memc_or1 =  0xfc000a00;
+	size_b0 = 0x04000000;
+#else
+#error SDRAM size configuration missing.
+#endif
+	memctl->memc_br1 =  0x00000081;
+	udelay(200);
+	return (size_b0 );
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	        doc_probe (CFG_DOC_BASE);
+}
+#endif
diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds
new file mode 100755
index 0000000..d7f7dc1
--- /dev/null
+++ b/board/svm_sc8xx/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = env_offset;
+    common/environment.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug
new file mode 100755
index 0000000..894b9bd
--- /dev/null
+++ b/board/svm_sc8xx/u-boot.lds.debug
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/sx1/Makefile b/board/sx1/Makefile
new file mode 100755
index 0000000..8fbdf2a
--- /dev/null
+++ b/board/sx1/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= sx1.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sx1/config.mk b/board/sx1/config.mk
new file mode 100755
index 0000000..4902e82
--- /dev/null
+++ b/board/sx1/config.mk
@@ -0,0 +1,19 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# SX1 board with OMAP1510 (ARM925T) cpu
+# see http://www.ti.com/ for more information on Texas Insturments
+#
+# SX1 has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+TEXT_BASE = 0x11080000
diff --git a/board/sx1/lowlevel_init.S b/board/sx1/lowlevel_init.S
new file mode 100755
index 0000000..bdf812e
--- /dev/null
+++ b/board/sx1/lowlevel_init.S
@@ -0,0 +1,397 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * -- Some bits of code used from rrload's head_OMAP1510.s --
+ * Copyright (C) 2002 RidgeRun, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_OMAP1510)
+#include <./configs/omap1510.h>
+#endif
+
+#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE	 /* sdram load addr from config.mk */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/*
+	 * Configure 1510 pins functions to match our board.
+	 */
+	ldr	r0, REG_PULL_DWN_CTRL_0
+	ldr	r1, VAL_PULL_DWN_CTRL_0
+	str	r1, [r0]
+	ldr	r0, REG_PULL_DWN_CTRL_1
+	ldr	r1, VAL_PULL_DWN_CTRL_1
+	str	r1, [r0]
+	ldr	r0, REG_PULL_DWN_CTRL_2
+	ldr	r1, VAL_PULL_DWN_CTRL_2
+	str	r1, [r0]
+	ldr	r0, REG_PULL_DWN_CTRL_3
+	ldr	r1, VAL_PULL_DWN_CTRL_3
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_4
+	ldr	r1, VAL_FUNC_MUX_CTRL_4
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_5
+	ldr	r1, VAL_FUNC_MUX_CTRL_5
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_6
+	ldr	r1, VAL_FUNC_MUX_CTRL_6
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_7
+	ldr	r1, VAL_FUNC_MUX_CTRL_7
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_8
+	ldr	r1, VAL_FUNC_MUX_CTRL_8
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_9
+	ldr	r1, VAL_FUNC_MUX_CTRL_9
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_A
+	ldr	r1, VAL_FUNC_MUX_CTRL_A
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_B
+	ldr	r1, VAL_FUNC_MUX_CTRL_B
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_C
+	ldr	r1, VAL_FUNC_MUX_CTRL_C
+	str	r1, [r0]
+	ldr	r0, REG_FUNC_MUX_CTRL_D
+	ldr	r1, VAL_FUNC_MUX_CTRL_D
+	str	r1, [r0]
+	ldr	r0, REG_VOLTAGE_CTRL_0
+	ldr	r1, VAL_VOLTAGE_CTRL_0
+	str	r1, [r0]
+	ldr	r0, REG_TEST_DBG_CTRL_0
+	ldr	r1, VAL_TEST_DBG_CTRL_0
+	str	r1, [r0]
+	ldr	r0, REG_MOD_CONF_CTRL_0
+	ldr	r1, VAL_MOD_CONF_CTRL_0
+	str	r1, [r0]
+
+	/* Move to 1510 mode */
+	ldr	r0, REG_COMP_MODE_CTRL_0
+	ldr	r1, VAL_COMP_MODE_CTRL_0
+	str	r1, [r0]
+
+	/* Set up Traffic Ctlr*/
+	ldr r0, REG_TC_IMIF_PRIO
+	mov r1, #0x0
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFS_PRIO
+	str r1, [r0]
+	ldr r0, REG_TC_EMIFF_PRIO
+	str r1, [r0]
+
+	ldr r0, REG_TC_EMIFS_CONFIG
+	ldr r1, [r0]
+	bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
+	bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
+	str r1, [r0]	    /* EMIFS GlB Configuration. (value 0x12 most likely) */
+
+	ldr r0, _GPIO_PIN_CONTROL_REG
+	mov r1,#0
+	orr r1, r1, #0x0001 /* M_PCM_SYNC */
+	orr r1, r1, #0x4000 /* IPC_ACTIVE */
+	strh r1,[r0]
+
+	ldr r0, _GPIO_DIR_CONTROL_REG
+	mov r1,#0
+	bic r1, r1, #0x0001 /* M_PCM_SYNC */
+	bic r1, r1, #0x4000 /* IPC_ACTIVE */
+	strh r1,[r0]
+
+	ldr r0, _GPIO_DATA_OUTPUT_REG
+	mov r1,#0
+	bic r1, r1, #0x0001 /* M_PCM_SYNC */
+	orr r1, r1, #0x4000 /* IPC_ACTIVE */
+	strh r1,[r0]
+
+	/* Setup some clock domains */
+	ldr r1, =OMAP1510_CLKS
+	ldr r0, REG_ARM_IDLECT2
+	strh r1, [r0]  /* CLKM, Clock domain control. */
+
+	mov r1, #0x01  /* PER_EN bit */
+	ldr r0, REG_ARM_RSTCT2
+	strh r1, [r0]  /* CLKM; Peripheral reset. */
+
+	/* Set CLKM to Sync-Scalable  */
+	/* I supposidly need to enable the dsp clock before switching */
+	mov r1, #0x1000
+	ldr r0, REG_ARM_SYSST
+	strh r1, [r0]
+	mov r0, #0x400
+1:
+	subs r0, r0, #0x1   /* wait for any bubbles to finish */
+	bne 1b
+
+	ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
+	ldr r0, REG_ARM_CKCTL
+	strh r1, [r0]
+
+	/* setup DPLL 1 */
+	ldr r1, VAL_DPLL1_CTL
+	ldr r0, REG_DPLL1_CTL
+	strh r1, [r0]
+	ands r1, r1, #0x10  /* Check if PLL is enabled. */
+	beq lock_end	    /* Do not look for lock if BYPASS selected */
+2:
+	ldrh r1, [r0]
+	ands r1, r1, #0x01  /* Check the LOCK bit. */
+	beq 2b		    /* ...loop until bit goes hi. */
+lock_end:
+
+	/* Set memory timings corresponding to the new clock speed */
+
+	/* Check execution location to determine current execution location
+	 * and branch to appropriate initialization code.
+	 */
+	mov r0, #0x10000000		    /* Load physical SDRAM base. */
+	mov r1, pc			    /* Get current execution location. */
+	cmp r1, r0			    /* Compare. */
+	bge skip_sdram			    /* Skip over EMIF-fast initialization if running from SDRAM. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800			       /* value should be checked */
+3:
+	subs r3, r3, #0x1		      /* Decrement count */
+	bne 3b
+
+	/*
+	 * Set SDRAM control values. Disable refresh before MRS command.
+	 */
+	ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
+	bic r3, r0, #0xC		    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
+	orr r3, r3, #0x8000000		    /* (BIT27) Disable CLK when Power down or Self-Refresh */
+	orr r3, r3, #0x4000000		    /* BIT26 Power Down Enable */
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r3, [r2]			    /* Store the passed value with AR disabled. */
+
+	ldr r1, VAL_TC_EMIFF_MRS	    /* get MRS value */
+	ldr r2, REG_TC_EMIFF_MRS	    /* Point to MRS register. */
+	str r1, [r2]			    /* Store the passed value.*/
+
+	ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
+	str r0, [r2]			    /* Store the passed value. */
+
+	/*
+	 * Delay for SDRAM initialization.
+	 */
+	mov r3, #0x1800
+4:
+	subs r3, r3, #1			    /* Decrement count. */
+	bne 4b
+
+skip_sdram:
+
+	/* slow interface */
+	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
+	ldr r0, REG_TC_EMIFS_CS0_CONFIG
+	str r1, [r0] /* Chip Select 0 */
+	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
+	ldr r0, REG_TC_EMIFS_CS1_CONFIG
+	str r1, [r0] /* Chip Select 1 */
+	ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+	ldr r0, REG_TC_EMIFS_CS2_CONFIG
+	str r1, [r0] /* Chip Select 2 */
+	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+	ldr r0, REG_TC_EMIFS_CS3_CONFIG
+	str r1, [r0] /* Chip Select 3 */
+
+	/* back to arch calling code */
+	mov	pc, lr
+
+/* the literal pools origin */
+	.ltorg
+
+/* OMAP configuration registers */
+REG_FUNC_MUX_CTRL_0:		/* 32 bits */
+	.word 0xfffe1000
+REG_FUNC_MUX_CTRL_1:		/* 32 bits */
+	.word 0xfffe1004
+REG_FUNC_MUX_CTRL_2:		/* 32 bits */
+	.word 0xfffe1008
+REG_COMP_MODE_CTRL_0:		/* 32 bits */
+	.word 0xfffe100c
+REG_FUNC_MUX_CTRL_3:		/* 32 bits */
+	.word 0xfffe1010
+REG_FUNC_MUX_CTRL_4:		/* 32 bits */
+	.word 0xfffe1014
+REG_FUNC_MUX_CTRL_5:		/* 32 bits */
+	.word 0xfffe1018
+REG_FUNC_MUX_CTRL_6:		/* 32 bits */
+	.word 0xfffe101c
+REG_FUNC_MUX_CTRL_7:		/* 32 bits */
+	.word 0xfffe1020
+REG_FUNC_MUX_CTRL_8:		/* 32 bits */
+	.word 0xfffe1024
+REG_FUNC_MUX_CTRL_9:		/* 32 bits */
+	.word 0xfffe1028
+REG_FUNC_MUX_CTRL_A:		/* 32 bits */
+	.word 0xfffe102C
+REG_FUNC_MUX_CTRL_B:		/* 32 bits */
+	.word 0xfffe1030
+REG_FUNC_MUX_CTRL_C:		/* 32 bits */
+	.word 0xfffe1034
+REG_FUNC_MUX_CTRL_D:		/* 32 bits */
+	.word 0xfffe1038
+REG_PULL_DWN_CTRL_0:		/* 32 bits */
+	.word 0xfffe1040
+REG_PULL_DWN_CTRL_1:		/* 32 bits */
+	.word 0xfffe1044
+REG_PULL_DWN_CTRL_2:		/* 32 bits */
+	.word 0xfffe1048
+REG_PULL_DWN_CTRL_3:		/* 32 bits */
+	.word 0xfffe104c
+REG_VOLTAGE_CTRL_0:		/* 32 bits */
+	.word 0xfffe1060
+REG_TEST_DBG_CTRL_0:		/* 32 bits */
+	.word 0xfffe1070
+REG_MOD_CONF_CTRL_0:		/* 32 bits */
+	.word 0xfffe1080
+REG_TC_IMIF_PRIO:		/* 32 bits */
+	.word 0xfffecc00
+REG_TC_EMIFS_PRIO:		/* 32 bits */
+	.word 0xfffecc04
+REG_TC_EMIFF_PRIO:		/* 32 bits */
+	.word 0xfffecc08
+REG_TC_EMIFS_CONFIG:		/* 32 bits */
+	.word 0xfffecc0c
+REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
+	.word 0xfffecc10
+REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
+	.word 0xfffecc14
+REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
+	.word 0xfffecc18
+REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
+	.word 0xfffecc1c
+REG_TC_EMIFF_SDRAM_CONFIG:	/* 32 bits */
+	.word 0xfffecc20
+REG_TC_EMIFF_MRS:		/* 32 bits */
+	.word 0xfffecc24
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL:			/* 16 bits */
+	.word 0xfffece00
+REG_ARM_IDLECT2:		/* 16 bits */
+	.word 0xfffece08
+REG_ARM_RSTCT2:			/* 16 bits */
+	.word 0xfffece14
+REG_ARM_SYSST:			/* 16 bits */
+	.word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL:			/* 16 bits */
+	.word 0xfffecf00
+/* identification code register */
+REG_IDCODE:			/* 32 bits */
+	.word 0xfffed404
+
+/* SX1 specific */
+_GPIO_PIN_CONTROL_REG:
+	.word GPIO_PIN_CONTROL_REG
+_GPIO_DIR_CONTROL_REG:
+	.word GPIO_DIR_CONTROL_REG
+_GPIO_DATA_OUTPUT_REG:
+	.word GPIO_DATA_OUTPUT_REG
+
+VAL_COMP_MODE_CTRL_0:
+	.word 0x0000eaef
+VAL_FUNC_MUX_CTRL_4:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_5:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_6:
+	.word 0x00000001
+VAL_FUNC_MUX_CTRL_7:
+	.word 0x00001000
+VAL_FUNC_MUX_CTRL_8:
+	.word 0x00001240       /*[Knoller]  Value of Symbian Image Wing B2*/
+VAL_FUNC_MUX_CTRL_9:
+	.word 0x00201008
+VAL_FUNC_MUX_CTRL_A:
+	.word 0x00001000
+VAL_FUNC_MUX_CTRL_B:
+	.word 0x00000000
+VAL_FUNC_MUX_CTRL_C:
+	.word 0x09008001       /*[Knoller]  Value of Symbian Image Wing B2*/
+VAL_FUNC_MUX_CTRL_D:
+	.word 0x00000000
+VAL_PULL_DWN_CTRL_0:
+	.word 0xfffeffff
+VAL_PULL_DWN_CTRL_1:
+	.word 0xd1ffffec
+VAL_PULL_DWN_CTRL_2:
+	.word 0xffa80c5b
+VAL_PULL_DWN_CTRL_3:
+	.word 0xffffc0fe
+VAL_VOLTAGE_CTRL_0:
+	.word 0x00000007
+VAL_TEST_DBG_CTRL_0:
+	/* The OMAP5910 TRM says this register must be 0, but HelenConfRegs
+	 * says to write a 7.  Don't know what the right thing is to do, so
+	 * I'm leaving it at 7 since that's what was already here.
+	 */
+	.word 0x00000007
+VAL_MOD_CONF_CTRL_0:
+	.word 0x0da20000       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_ARM_CKCTL:
+	.word 0x010D
+
+VAL_DPLL1_CTL:
+	.word 0x3A33   /*[Hertle] Value of Symbian Image*/
+
+VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
+	.word 0x00001149
+
+VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
+	.word 0x00004158
+
+VAL_TC_EMIFS_CS0_CONFIG:
+	.word 0x00213090       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFS_CS1_CONFIG:
+	.word 0x00215070       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFS_CS2_CONFIG:
+	.word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFS_CS3_CONFIG:
+	.word 0x00001139       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+	.word 0x0105f0b4       /*[Knoller]  Value of Symbian Image Wing B2*/
+
+
+VAL_TC_EMIFF_MRS:
+	.word 0x00000027       /*[Knoller]  Value of Symbian Image Wing B2*/
diff --git a/board/sx1/sx1.c b/board/sx1/sx1.c
new file mode 100755
index 0000000..e45f6ae
--- /dev/null
+++ b/board/sx1/sx1.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+static void flash__init (void);
+static void ether__init (void);
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+			  "subs %0, %1, #1\n"
+			  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of SX1 Board */
+	gd->bd->bi_arch_number = MACH_TYPE_SX1;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+/* kk - this speeds up your boot a quite a bit.	 However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
+	/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
+
+	/* setup gpio direction to match board (no floats!) */
+	/**gdir = 0xCFF9; */
+	/**mdir = 0x103F; */
+
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void flash__init (void)
+{
+#define CS0_CHIP_SELECT_REG 0xfffecc10
+#define CS3_CHIP_SELECT_REG 0xfffecc1c
+#define EMIFS_GlB_Config_REG 0xfffecc0c
+
+	unsigned int regval;
+
+	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
+	regval = regval | 0x0001;	/* Turn off write protection for flash devices. */
+	if (regval & 0x0002) {
+		regval = regval & 0xfffd;	/* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
+		/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
+		/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
+		/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
+	}
+	*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
+}
+
+
+/******************************
+ Routine:
+ Description:
+******************************/
+static void ether__init (void)
+{
+#define ETH_CONTROL_REG 0x0800000b
+	/* take the Ethernet controller out of reset and wait
+	 * for the EEPROM load to complete.
+	 */
+	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+	udelay (3);
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff --git a/board/sx1/u-boot.lds b/board/sx1/u-boot.lds
new file mode 100755
index 0000000..d28155f
--- /dev/null
+++ b/board/sx1/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  cpu/arm925t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/tb0229/Makefile b/board/tb0229/Makefile
new file mode 100755
index 0000000..4375073
--- /dev/null
+++ b/board/tb0229/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o vr4131-pci.o
+SOBJS	= lowlevel_init.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/tb0229/config.mk b/board/tb0229/config.mk
new file mode 100755
index 0000000..9a50850
--- /dev/null
+++ b/board/tb0229/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Masami Komiya <mkomiya@sonare.it> 2004
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# ROM version
+TEXT_BASE = 0xBFC00000
+
+# RAM version
+#TEXT_BASE = 0x80400000
diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c
new file mode 100755
index 0000000..e9f6418
--- /dev/null
+++ b/board/tb0229/flash.c
@@ -0,0 +1,1198 @@
+/*
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+
+#ifdef CFG_FLASH_16BIT
+#define FLASH_WORD_SIZE	unsigned short
+#define	FLASH_ID_MASK	0xFFFF
+#else
+#define FLASH_WORD_SIZE unsigned long
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+/* stolen from esteem192e/flash.c */
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
+
+#ifndef CFG_FLASH_16BIT
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+#else
+static int write_short (flash_info_t * info, ulong dest, ushort data);
+#endif
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	uint pbcr;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size_b0 =
+		flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE,
+				&flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
+	}
+
+	/* Only one bank */
+	if (CFG_MAX_FLASH_BANKS == 1) {
+		/* Setup offsets */
+		flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+		/* Monitor protection ON by default */
+#if 0				/* sand: */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      FLASH_BASE0_PRELIM - monitor_flash_len +
+				      size_b0,
+				      FLASH_BASE0_PRELIM - 1 + size_b0,
+				      &flash_info[0]);
+#else
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      CFG_MONITOR_BASE,
+				      CFG_MONITOR_BASE + monitor_flash_len -
+				      1, &flash_info[0]);
+#endif
+		size_b1 = 0;
+		flash_info[0].size = size_b0;
+	}
+#ifdef CFG_FLASH_BASE_2
+	/* 2 banks */
+	else {
+		size_b1 =
+			flash_get_size ((volatile FLASH_WORD_SIZE *)
+					CFG_FLASH_BASE_2, &flash_info[1]);
+
+		/* Re-do sizing to get full correct info */
+
+		if (size_b1) {
+			mtdcr (ebccfga, pb0cr);
+			pbcr = mfdcr (ebccfgd);
+			mtdcr (ebccfga, pb0cr);
+			base_b1 = -size_b1;
+			pbcr = (pbcr & 0x0001ffff) | base_b1 |
+				(((size_b1 / 1024 / 1024) - 1) << 17);
+			mtdcr (ebccfgd, pbcr);
+			/*          printf("pb1cr = %x\n", pbcr); */
+		}
+
+		if (size_b0) {
+			mtdcr (ebccfga, pb1cr);
+			pbcr = mfdcr (ebccfgd);
+			mtdcr (ebccfga, pb1cr);
+			base_b0 = base_b1 - size_b0;
+			pbcr = (pbcr & 0x0001ffff) | base_b0 |
+				(((size_b0 / 1024 / 1024) - 1) << 17);
+			mtdcr (ebccfgd, pbcr);
+			/*            printf("pb0cr = %x\n", pbcr); */
+		}
+
+		size_b0 =
+			flash_get_size ((volatile FLASH_WORD_SIZE *) base_b0,
+					&flash_info[0]);
+
+		flash_get_offsets (base_b0, &flash_info[0]);
+
+		/* monitor protection ON by default */
+#if 0				/* sand: */
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      FLASH_BASE0_PRELIM - monitor_flash_len +
+				      size_b0,
+				      FLASH_BASE0_PRELIM - 1 + size_b0,
+				      &flash_info[0]);
+#else
+		(void) flash_protect (FLAG_PROTECT_SET,
+				      CFG_MONITOR_BASE,
+				      CFG_MONITOR_BASE + monitor_flash_len -
+				      1, &flash_info[0]);
+#endif
+
+		if (size_b1) {
+			/* Re-do sizing to get full correct info */
+			size_b1 =
+				flash_get_size ((volatile FLASH_WORD_SIZE *)
+						base_b1, &flash_info[1]);
+
+			flash_get_offsets (base_b1, &flash_info[1]);
+
+			/* monitor protection ON by default */
+			(void) flash_protect (FLAG_PROTECT_SET,
+					      base_b1 + size_b1 -
+					      monitor_flash_len,
+					      base_b1 + size_b1 - 1,
+					      &flash_info[1]);
+			/* monitor protection OFF by default (one is enough) */
+			(void) flash_protect (FLAG_PROTECT_CLEAR,
+					      base_b0 + size_b0 -
+					      monitor_flash_len,
+					      base_b0 + size_b0 - 1,
+					      &flash_info[0]);
+		} else {
+			flash_info[1].flash_id = FLASH_UNKNOWN;
+			flash_info[1].sector_count = -1;
+		}
+
+		flash_info[0].size = size_b0;
+		flash_info[1].size = size_b1;
+	}			/* else 2 banks */
+#endif
+	return (size_b0 + size_b1);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start adress table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F320J3A ||
+	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A ||
+	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] =
+				base + (i * info->size / info->sector_count);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CFG_FLASH_16BIT
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00008000;
+			info->start[3] = base + 0x0000C000;
+			info->start[4] = base + 0x00010000;
+			info->start[5] = base + 0x00014000;
+			info->start[6] = base + 0x00018000;
+			info->start[7] = base + 0x0001C000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x000E0000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00008000;
+			info->start[2] = base + 0x0000C000;
+			info->start[3] = base + 0x00010000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00020000) - 0x00060000;
+			}
+		}
+#else
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00002000;
+			info->start[2] = base + 0x00004000;
+			info->start[3] = base + 0x00006000;
+			info->start[4] = base + 0x00008000;
+			info->start[5] = base + 0x0000A000;
+			info->start[6] = base + 0x0000C000;
+			info->start[7] = base + 0x0000E000;
+			for (i = 8; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00070000;
+			}
+		} else {
+			/* set sector offsets for bottom boot block type        */
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] =
+					base + (i * 0x00010000) - 0x00030000;
+			}
+		}
+#endif
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+
+#ifndef CFG_FLASH_16BIT
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			info->start[i--] = base + info->size - 0x00014000;
+			info->start[i--] = base + info->size - 0x00018000;
+			info->start[i--] = base + info->size - 0x0001C000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x00010000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00020000;
+			}
+		}
+#else
+			info->start[i--] = base + info->size - 0x00002000;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			info->start[i--] = base + info->size - 0x0000A000;
+			info->start[i--] = base + info->size - 0x0000C000;
+			info->start[i--] = base + info->size - 0x0000E000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+
+		} else {
+
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+#endif
+	}
+
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+	uchar *boottype;
+	uchar botboot[] = ", bottom boot sect)\n";
+	uchar topboot[] = ", top boot sector)\n";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf ("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf ("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	if (info->flash_id & 0x0001) {
+		boottype = botboot;
+	} else {
+		boottype = topboot;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:
+		printf ("AM29LV400B (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM400T:
+		printf ("AM29LV400T (4 Mbit%s", boottype);
+		break;
+	case FLASH_AM800B:
+		printf ("AM29LV800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM800T:
+		printf ("AM29LV800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM160T:
+		printf ("AM29LV160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_AM320B:
+		printf ("AM29LV320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_AM320T:
+		printf ("AM29LV320T (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800B:
+		printf ("INTEL28F800B (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL800T:
+		printf ("INTEL28F800T (8 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160B:
+		printf ("INTEL28F160B (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL160T:
+		printf ("INTEL28F160T (16 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320B:
+		printf ("INTEL28F320B (32 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL320T:
+		printf ("INTEL28F320T (32 Mbit%s", boottype);
+		break;
+
+#if 0				/* enable when devices are available */
+
+	case FLASH_INTEL640B:
+		printf ("INTEL28F640B (64 Mbit%s", boottype);
+		break;
+	case FLASH_INTEL640T:
+		printf ("INTEL28F640T (64 Mbit%s", boottype);
+		break;
+#endif
+	case FLASH_28F320J3A:
+		printf ("INTEL28F320J3A (32 Mbit%s", boottype);
+		break;
+	case FLASH_28F640J3A:
+		printf ("INTEL28F640J3A (64 Mbit%s", boottype);
+		break;
+	case FLASH_28F128J3A:
+		printf ("INTEL28F128J3A (128 Mbit%s", boottype);
+		break;
+
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info)
+{
+	short i;
+	ulong base = (ulong) addr;
+	FLASH_WORD_SIZE value;
+
+	/* Write auto select command: read Manufacturer ID */
+
+
+#ifndef CFG_FLASH_16BIT
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x00890089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x00900090;
+	if (addr[0x0000] != 0x00890089) {
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00900090;
+#else
+
+	/*
+	 * Note: if it is an AMD flash and the word at addr[0000]
+	 * is 0x0089 this routine will think it is an Intel
+	 * flash device and may(most likely) cause trouble.
+	 */
+
+	addr[0x0000] = 0x0090;
+
+	if (addr[0x0000] != 0x0089) {
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0090;
+#endif
+	}
+	value = addr[0];
+
+	switch (value) {
+	case (AMD_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (STM_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	case (SST_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);	/* no or unknown flash  */
+
+	}
+
+	value = addr[1];	/* device ID            */
+
+	switch (value) {
+
+	case (AMD_ID_LV400T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (AMD_ID_LV400B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;		/* => 1 MB              */
+
+	case (AMD_ID_LV800T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (AMD_ID_LV800B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (AMD_ID_LV160T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (AMD_ID_LV160B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+#if 0				/* enable when device IDs are available */
+	case (AMD_ID_LV320T & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case (AMD_ID_LV320B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+#endif
+
+	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800T;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL800B;
+		info->sector_count = 23;
+		info->size = 0x00200000;
+		break;		/* => 2 MB              */
+
+	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160T;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL160B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;		/* => 4 MB              */
+
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;		/* => 8 MB              */
+
+#if 0				/* enable when devices are available */
+	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
+		info->flash_id += FLASH_INTEL320T;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;		/* => 16 MB             */
+
+	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 135;
+		info->size = 0x01000000;
+		break;		/* => 16 MB             */
+#endif
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;		/* => 32 MBit   */
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 64 MBit   */
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 128 MBit          */
+
+	default:
+		/* FIXME */
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);	/* => no or unknown flash */
+	}
+
+	flash_get_offsets (base, info);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) {
+			*addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+		} else {
+			*addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+		}
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+
+	volatile FLASH_WORD_SIZE *addr =
+		(volatile FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect, barf;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    ((info->flash_id > FLASH_AMD_COMP) &&
+	     ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	if (info->flash_id < FLASH_AMD_COMP) {
+#ifndef CFG_FLASH_16BIT
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00800080;
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+#else
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x0080;
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+#endif
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				addr = (volatile FLASH_WORD_SIZE *) (info->
+								     start
+								     [sect]);
+				addr[0] = (0x00300030 & FLASH_ID_MASK);
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto DONE;
+
+		start = get_timer (0);
+		last = start;
+		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
+		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
+		       (0x00800080 & FLASH_ID_MASK)) {
+			if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000000) {	/* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+	      DONE:
+		/* reset to read mode */
+		addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+		addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
+	} else {
+
+
+		for (sect = s_first; sect <= s_last; sect++) {
+			if (info->protect[sect] == 0) {	/* not protected */
+				barf = 0;
+#ifndef CFG_FLASH_16BIT
+				addr = (vu_long *) (info->start[sect]);
+				addr[0] = 0x00500050;
+				addr[0] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				while (!(addr[0] & 0x00800080));	/* wait for error or finish */
+				if (addr[0] & 0x003A003A) {	/* check for error */
+					barf = addr[0] & 0x003A0000;
+					if (barf) {
+						barf >>= 16;
+					} else {
+						barf = addr[0] & 0x0000003A;
+					}
+				}
+#else
+				addr = (vu_short *) (info->start[sect]);
+				addr[0] = 0x0050;	/* clear status register */
+				addr[0] = 0x0020;
+				addr[0] = 0x00D0;
+				while (!(addr[0] & 0x0080));	/* wait for error or finish */
+				if (addr[0] & 0x003A)	/* check for error */
+					barf = addr[0] & 0x003A;
+#endif
+				if (barf) {
+					printf ("\nFlash error in sector at %lx\n", (unsigned long) addr);
+					if (barf & 0x0002)
+						printf ("Block locked, not erased.\n");
+					if ((barf & 0x0030) == 0x0030)
+						printf ("Command Sequence error.\n");
+					if ((barf & 0x0030) == 0x0020)
+						printf ("Block Erase error.\n");
+					if (barf & 0x0008)
+						printf ("Vpp Low error.\n");
+					rcode = 1;
+				} else
+					printf (".");
+				l_sect = sect;
+			}
+			addr = (volatile FLASH_WORD_SIZE *) info->start[0];
+#ifndef CFG_FLASH_16BIT
+			addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
+#else
+			addr[0] = (0x00FF & FLASH_ID_MASK);	/* reset bank */
+#endif
+		}
+
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*flash_info_t *addr2info (ulong addr)
+{
+	flash_info_t *info;
+	int i;
+
+	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+		if ((addr >= info->start[0]) &&
+		    (addr < (info->start[0] + info->size)) ) {
+			return (info);
+		}
+	}
+
+	return (NULL);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+
+/*int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+	int i;
+	ulong         end        = addr + cnt - 1;
+	flash_info_t *info_first = addr2info (addr);
+	flash_info_t *info_last  = addr2info (end );
+	flash_info_t *info;
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	if (!info_first || !info_last) {
+		return (8);
+	}
+
+	for (info = info_first; info <= info_last; ++info) {
+										ulong b_end = info->start[0] + info->size;*/ /* bank end addr */
+/*		short s_end = info->sector_count - 1;
+		for (i=0; i<info->sector_count; ++i) {
+			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+			if ((end >= info->start[i]) && (addr < e_addr) &&
+			    (info->protect[i] != 0) ) {
+				return (4);
+			}
+		}
+	}
+
+*/ /* finally write data to flash */
+/*	for (info = info_first; info <= info_last && cnt>0; ++info) {
+		ulong len;
+
+		len = info->start[0] + info->size - addr;
+		if (len > cnt)
+			len = cnt;
+		if ((i = write_buff(info, src, addr, len)) != 0) {
+			return (i);
+		}
+		cnt  -= len;
+		addr += len;
+		src  += len;
+	}
+	return (0);
+}
+*/
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+#ifndef CFG_FLASH_16BIT
+	ulong cp, wp, data;
+	int l;
+#else
+	ulong cp, wp;
+	ushort data;
+#endif
+	int i, rc;
+
+#ifndef CFG_FLASH_16BIT
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+
+#else
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start byte
+	 */
+	if (addr - wp) {
+		data = 0;
+		data = (data << 8) | *src++;
+		--cnt;
+		if ((rc = write_short (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+/*	l = 0; used for debuging  */
+	while (cnt >= 2) {
+		data = 0;
+		for (i = 0; i < 2; ++i) {
+			data = (data << 8) | *src++;
+		}
+
+/*		if(!l){
+			printf("%x",data);
+			l = 1;
+		}  used for debuging */
+
+		if ((rc = write_short (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_short (info, wp, data));
+
+
+#endif
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifndef CFG_FLASH_16BIT
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *) (info->start[0]);
+	ulong start, barf;
+	int flag;
+
+#if defined (__MIPSEL__)
+	data = cpu_to_be32 (data);
+#endif
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA00AA;
+		addr[0x02AA] = 0x00550055;
+		addr[0x0555] = 0x00A000A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00400040;
+	}
+
+	*((vu_long *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+
+		while ((*((vu_long *) dest) & 0x00800080) !=
+		       (data & 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				printf ("timeout\n");
+				return (1);
+			}
+		}
+
+	} else {
+
+		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				printf ("timeout\n");
+				return (1);
+			}
+		}
+
+		if (addr[0] & 0x003A003A) {	/* check for error */
+			barf = addr[0] & 0x003A0000;
+			if (barf) {
+				barf >>= 16;
+			} else {
+				barf = addr[0] & 0x0000003A;
+			}
+			printf ("\nFlash write error at address %lx\n",
+				(unsigned long) dest);
+			if (barf & 0x0002)
+				printf ("Block locked, not erased.\n");
+			if (barf & 0x0010)
+				printf ("Programming error.\n");
+			if (barf & 0x0008)
+				printf ("Vpp Low error.\n");
+			return (2);
+		}
+
+
+	}
+
+	return (0);
+}
+
+#else
+
+static int write_short (flash_info_t * info, ulong dest, ushort data)
+{
+	vu_short *addr = (vu_short *) (info->start[0]);
+	ulong start, barf;
+	int flag;
+
+#if defined (__MIPSEL__)
+	data = cpu_to_be16 (data);
+#endif
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_short *) dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		addr[0x0555] = 0x00AA;
+		addr[0x02AA] = 0x0055;
+		addr[0x0555] = 0x00A0;
+	} else {
+		/* intel stuff */
+		*addr = 0x00D0;
+		*addr = 0x0040;
+	}
+	*((vu_short *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+
+	if (info->flash_id < FLASH_AMD_COMP) {
+		/* AMD stuff */
+		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+
+	} else {
+		/* intel stuff */
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+
+		if (addr[0] & 0x003A) {	/* check for error */
+			barf = addr[0] & 0x003A;
+			printf ("\nFlash write error at address %lx\n",
+				(unsigned long) dest);
+			if (barf & 0x0002)
+				printf ("Block locked, not erased.\n");
+			if (barf & 0x0010)
+				printf ("Programming error.\n");
+			if (barf & 0x0008)
+				printf ("Vpp Low error.\n");
+			return (2);
+		}
+		*addr = 0x00B0;
+		*addr = 0x0070;
+		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+
+		*addr = 0x00FF;
+
+	}
+
+	return (0);
+
+}
+#endif
diff --git a/board/tb0229/lowlevel_init.S b/board/tb0229/lowlevel_init.S
new file mode 100755
index 0000000..df31806
--- /dev/null
+++ b/board/tb0229/lowlevel_init.S
@@ -0,0 +1,71 @@
+/*
+ *  Memory sub-system initialization code for TANBAC Evaluation board TB0229.
+ *
+ *  Copyright (c) 2003  Masami Komiya <mkomiya@sonare.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+
+
+	.globl  lowlevel_init
+lowlevel_init:
+
+	/* BCUCNTREG1 = 0x0040 */
+	la	t0, 0xaf000000
+	li	t1, 0x0040
+	sh	t1, 0(t0)
+
+	/* ROMSIZEREG = 0x3333 */
+	la	t0, 0xaf000004
+	li	t1, 0x3333
+	sh	t1, 0(t0)
+
+	/* ROMSPEEDREG = 0x3003 */
+	la	t0, 0xaf000006
+	li	t1, 0x3003
+	sh	t1, 0(t0)
+
+	/* BCUCNTREG3 = 0 */
+	la	t0, 0xaf000016
+	li	t1, 0x0000
+	sh	t1, 0(t0)
+
+	/* CMUCLKMSK */
+	la	t0, 0xaf000060
+	li	t1, 0x39a2
+	sh	t1, 0(t0)
+
+	/* PMUCNTREG */
+	la	t0, 0xaf0000c2
+	li	t1, 0x0006
+	sh	t1, 0(t0)
+
+	/* SDRAMMODEREG = 0x8029 */
+	la	t0, 0xaf000400
+	li	t1, 0x8029
+	sh	t1, 0(t0)
+
+	/* SDRAMCNTREG = 0x2322 */
+	la	t0, 0xaf000402
+	li	t1, 0x2322
+	sh	t1, 0(t0)
+
+	/* BCURFCNTREG = 0x0106 */
+	la	t0, 0xaf000404
+	li	t1, 0x0106
+	sh	t1, 0(t0)
+
+	/* RAMSZEREG = 0x5555 (64MB Bank) */
+	la	t0, 0xaf000408
+	li	t1, 0x5555
+	sh	t1, 0(t0)
+
+	j       ra
+	nop
diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c
new file mode 100755
index 0000000..e7914bd
--- /dev/null
+++ b/board/tb0229/tb0229.c
@@ -0,0 +1,42 @@
+/*
+ * Board initialize code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/addrspace.h>
+#include <asm/inca-ip.h>
+#include <pci.h>
+
+unsigned long mips_io_port_base = 0;
+
+#if defined(CONFIG_PCI)
+static struct pci_controller hose;
+
+void pci_init_board (void)
+{
+	init_vr4131_pci(&hose);
+}
+#endif
+
+
+long int initdram(int board_type)
+{
+	return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
+}
+
+
+int checkboard (void)
+{
+	printf("Board: TANBAC TB0229 ");
+	printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000);
+
+	return 0;
+}
diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds
new file mode 100755
index 0000000..30a2bc5
--- /dev/null
+++ b/board/tb0229/u-boot.lds
@@ -0,0 +1,69 @@
+/*
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c
new file mode 100755
index 0000000..0ee4bf3
--- /dev/null
+++ b/board/tb0229/vr4131-pci.c
@@ -0,0 +1,254 @@
+/*
+ * VR4131 PCIU support code for TANBAC Evaluation board TB0229.
+ *
+ * (C) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2, or (at
+ * your option) any later version.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/addrspace.h>
+
+#define VR4131_PCIMMAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c00)
+#define VR4131_PCIMMAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c04)
+#define VR4131_PCITAW1REG	(volatile unsigned int*)(KSEG1 + 0x0f000c08)
+#define VR4131_PCITAW2REG	(volatile unsigned int*)(KSEG1 + 0x0f000c0c)
+#define VR4131_PCIMIOAWREG	(volatile unsigned int*)(KSEG1 + 0x0f000c10)
+#define VR4131_PCICONFDREG	(volatile unsigned int*)(KSEG1 + 0x0f000c14)
+#define VR4131_PCICONFAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c18)
+#define VR4131_PCIMAILREG	(volatile unsigned int*)(KSEG1 + 0x0f000c1c)
+#define VR4131_BUSERRADREG	(volatile unsigned int*)(KSEG1 + 0x0f000c24)
+#define VR4131_INTCNTSTAREG	(volatile unsigned int*)(KSEG1 + 0x0f000c28)
+#define VR4131_PCIEXACCREG	(volatile unsigned int*)(KSEG1 + 0x0f000c2c)
+#define VR4131_PCIRECONTREG	(volatile unsigned int*)(KSEG1 + 0x0f000c30)
+#define VR4131_PCIENREG		(volatile unsigned int*)(KSEG1 + 0x0f000c34)
+#define VR4131_PCICLKSELREG	(volatile unsigned int*)(KSEG1 + 0x0f000c38)
+#define VR4131_PCITRDYREG	(volatile unsigned int*)(KSEG1 + 0x0f000c3c)
+#define VR4131_PCICLKRUNREG	(volatile unsigned int*)(KSEG1 + 0x0f000c60)
+#define VR4131_PCIHOSTCONFIG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_VENDORIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_DEVICEIDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d00)
+#define VR4131_COMMANDREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
+#define VR4131_STATUSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d04)
+#define VR4131_REVREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
+#define VR4131_CLASSREG		(volatile unsigned int*)(KSEG1 + 0x0f000d08)
+#define VR4131_CACHELSREG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
+#define VR4131_LATTIMERRG	(volatile unsigned int*)(KSEG1 + 0x0f000d0c)
+#define VR4131_MAILBAREG	(volatile unsigned int*)(KSEG1 + 0x0f000d10)
+#define VR4131_PCIMBA1REG	(volatile unsigned int*)(KSEG1 + 0x0f000d14)
+#define VR4131_PCIMBA2REG	(volatile unsigned int*)(KSEG1 + 0x0f000d18)
+
+/*#define VR41XX_PCIIRQ_OFFSET    (VR41XX_IRQ_MAX + 1)	*/
+/*#define VR41XX_PCIIRQ_MAX       (VR41XX_IRQ_MAX + 12)	*/
+/*#define VR4122_PCI_HOST_BASE    0xa0000000		*/
+
+volatile unsigned int *pciconfigaddr;
+volatile unsigned int *pciconfigdata;
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+/*
+ *	Access PCI Configuration Register for VR4131
+ */
+
+static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
+				     u32 * data)
+{
+	u32 bus;
+	u32 device;
+
+	bus = ((dev & 0xff0000) >> 16);
+	device = ((dev & 0xf800) >> 11);
+
+	if (bus == 0) {
+		/* Type 0 Configuration */
+		*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc));
+	} else {
+		/* Type 1 Configuration */
+		*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
+	}
+
+	if (access_type == PCI_ACCESS_WRITE) {
+		*VR4131_PCICONFDREG = *data;
+	} else {
+		*data = *VR4131_PCICONFDREG;
+	}
+
+	return (0);
+}
+
+static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
+{
+	u32 data;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
+{
+	u32 data;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = (data >> ((reg & 3) << 3)) & 0xffff;
+
+	return 0;
+}
+
+
+static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
+					 u32 * val)
+{
+	u32 data = 0;
+
+	if (reg & 3)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	*val = data;
+
+	return (0);
+}
+
+static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
+{
+	u32 data = 0;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
+						       ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+
+static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
+{
+	u32 data = 0;
+
+	if (reg & 1)
+		return -1;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
+		return -1;
+
+	data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
+							 ((reg & 3) << 3));
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return 0;
+}
+
+static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
+{
+	u32 data;
+
+	if (reg & 3) {
+		return -1;
+	}
+
+	data = val;
+
+	if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
+		return -1;
+
+	return (0);
+}
+
+
+/*
+ *	Initialize VR4131 PCIU
+ */
+
+vr4131_pciu_init ()
+{
+	/* PCI clock */
+	*VR4131_PCICLKSELREG = 0x00000002;
+
+	/* PCI memory and I/O space */
+	*VR4131_PCIMMAW1REG = 0x100F9010;
+	*VR4131_PCIMMAW2REG = 0x140FD014;
+	*VR4131_PCIMIOAWREG = 0x160FD000;
+
+	/* Target memory window */
+	*VR4131_PCITAW1REG = 0x00081000;	/* 64MB */
+	*VR4131_PCITAW2REG = 0x00000000;
+
+	*VR4131_MAILBAREG = 0UL;
+	*VR4131_PCIMBA1REG = 0UL;
+
+	*VR4131_PCITRDYREG = 0x00008004;
+
+	*VR4131_PCIENREG = 0x00000004;	/* PCI enable */
+	*VR4131_COMMANDREG = 0x02000007;
+}
+
+/*
+ *	Initialize Module
+ */
+
+void init_vr4131_pci (struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	vr4131_pciu_init ();	/* Initialize VR4131 PCIU */
+
+	/* PCI memory space #1 */
+	pci_set_region (hose->regions + 0,
+			0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
+
+	/* PCI memory space #2 */
+	pci_set_region (hose->regions + 1,
+			0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
+
+
+	/* PCI I/O space */
+	pci_set_region (hose->regions + 2,
+			0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region (hose->regions + 3,
+			0x00000000,
+			0x80000000,
+			0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 4;
+
+	hose->read_byte = vr4131_pci_read_config_byte;
+	hose->read_word = vr4131_pci_read_config_word;
+	hose->read_dword = vr4131_pci_read_config_dword;
+	hose->write_byte = vr4131_pci_write_config_byte;
+	hose->write_word = vr4131_pci_write_config_word;
+	hose->write_dword = vr4131_pci_write_config_dword;
+
+	pci_register_hose (hose);
+
+	hose->last_busno = pci_hose_scan (hose);
+
+	return;
+}
diff --git a/board/total5200/Makefile b/board/total5200/Makefile
new file mode 100755
index 0000000..232956a
--- /dev/null
+++ b/board/total5200/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o sdram.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/total5200/config.mk b/board/total5200/config.mk
new file mode 100755
index 0000000..1a7a7cf
--- /dev/null
+++ b/board/total5200/config.mk
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Total5200 board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFF00000   boot high (standard configuration)
+#	0xFE000000   boot low
+#	0x00100000   boot from RAM (for testing only)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h
new file mode 100755
index 0000000..5b0923e
--- /dev/null
+++ b/board/total5200/mt48lc16m16a2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h
new file mode 100755
index 0000000..4b5ac80
--- /dev/null
+++ b/board/total5200/mt48lc32m16a2-75.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Micron MT48LC32M16A2-75 is compatible to:
+ *  - Infineon HYB39S512160AT-75
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x514F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#else
+#error CONFIG_MPC5200 is not defined
+#endif
diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c
new file mode 100755
index 0000000..a1601f2
--- /dev/null
+++ b/board/total5200/sdram.c
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+#include "sdram.h"
+
+#ifndef CFG_RAMBOOT
+static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	if (sdram_conf->ddr) {
+		/* set mode register: extended mode */
+		*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode;
+		__asm__ volatile ("sync");
+
+		/* set mode register: reset DLL */
+		*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000;
+		__asm__ volatile ("sync");
+	}
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
+	__asm__ volatile ("sync");
+
+	if (sdram_conf->ddr) {
+		/* set tap delay */
+		*(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay;
+		__asm__ volatile ("sync");
+	}
+
+	/* find RAM size using SDRAM CS0 only */
+	mpc5xxx_sdram_start(sdram_conf, 0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	mpc5xxx_sdram_start(sdram_conf, 1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		mpc5xxx_sdram_start(sdram_conf, 0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	mpc5xxx_sdram_start(sdram_conf, 0);
+	test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	mpc5xxx_sdram_start(sdram_conf, 1);
+	test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (test1 > test2) {
+		mpc5xxx_sdram_start(sdram_conf, 0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	mpc5xxx_sdram_start(sdram_conf, 0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	mpc5xxx_sdram_start(sdram_conf, 1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		mpc5xxx_sdram_start(sdram_conf, 0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h
new file mode 100755
index 0000000..bc21e1d
--- /dev/null
+++ b/board/total5200/sdram.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+typedef struct {
+	ulong ddr;
+	ulong mode;
+	ulong emode;
+	ulong control;
+	ulong config1;
+	ulong config2;
+#if defined(CONFIG_MPC5200)
+	ulong tapdelay;
+#endif
+#if defined(CONFIG_MGT5100)
+	ulong addrsel;
+#endif
+} sdram_conf_t;
+
+long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf);
diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c
new file mode 100755
index 0000000..1a35187
--- /dev/null
+++ b/board/total5200/total5200.c
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include "sdram.h"
+
+#if CONFIG_TOTAL5200_REV==2
+#include "mt48lc32m16a2-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+long int initdram (int board_type)
+{
+	sdram_conf_t sdram_conf;
+
+	sdram_conf.ddr = SDRAM_DDR;
+	sdram_conf.mode = SDRAM_MODE;
+	sdram_conf.emode = 0;
+	sdram_conf.control = SDRAM_CONTROL;
+	sdram_conf.config1 = SDRAM_CONFIG1;
+	sdram_conf.config2 = SDRAM_CONFIG2;
+#if defined(CONFIG_MPC5200)
+	sdram_conf.tapdelay = 0;
+#endif
+#if defined(CONFIG_MGT5100)
+	sdram_conf.addrsel = SDRAM_ADDRSEL;
+#endif
+	return mpc5xxx_sdram_init (&sdram_conf);
+}
+
+int checkboard (void)
+{
+#if defined(CONFIG_MPC5200)
+#if CONFIG_TOTAL5200_REV==2
+	puts ("Board: Total5200 Rev.2 ");
+#else
+	puts ("Board: Total5200 ");
+#endif
+#elif defined(CONFIG_MGT5100)
+	puts ("Board: Total5100 ");
+#endif
+
+/*
+ * Retrieve FPGA Revision.
+ */
+printf ("(FPGA %08X)\n", *(vu_long *) (CFG_FPGA_BASE + 0x400));
+
+/*
+ * Take all peripherals in power-up mode.
+ */
+#if CONFIG_TOTAL5200_REV==2
+	*(vu_char *) (CFG_CPLD_BASE + 0x46) = 0x70;
+#else
+	*(vu_long *) (CFG_CPLD_BASE + 0x400) = 0x70;
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_MGT5100)
+int board_early_init_r(void)
+{
+	/*
+	 * Now, when we are in RAM, enable CS0
+	 * because CS_BOOT cannot be written.
+	 */
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+
+	return 0;
+}
+#endif
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+/* IRDA_1 aka PSC6_3 (pin C13) */
+#define GPIO_IRDA_1	0x20000000UL
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+    	/* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1;
+	*(vu_long *) MPC5XXX_GPIO_DIR    |= GPIO_IRDA_1;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_GPIO_DATA_O &= ~GPIO_IRDA_1;
+	} else {
+		*(vu_long *) MPC5XXX_GPIO_DATA_O |=  GPIO_IRDA_1;
+	}
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#ifdef CONFIG_VIDEO_SED13806
+#include <sed13806.h>
+
+#define DISPLAY_WIDTH   640
+#define DISPLAY_HEIGHT  480
+
+#ifdef CONFIG_VIDEO_SED13806_8BPP
+#error CONFIG_VIDEO_SED13806_8BPP not supported.
+#endif /* CONFIG_VIDEO_SED13806_8BPP */
+
+#ifdef CONFIG_VIDEO_SED13806_16BPP
+static const S1D_REGS init_regs [] =
+{
+    {0x0001,0x00},   /* Miscellaneous Register */
+    {0x01FC,0x00},   /* Display Mode Register */
+    {0x0004,0x00},   /* General IO Pins Configuration Register 0 */
+    {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
+    {0x0008,0x00},   /* General IO Pins Control Register 0 */
+    {0x0009,0x00},   /* General IO Pins Control Register 1 */
+    {0x0010,0x02},   /* Memory Clock Configuration Register */
+    {0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
+    {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
+    {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
+    {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
+    {0x0021,0x03},   /* DRAM Refresh Rate Register */
+    {0x002A,0x00},   /* DRAM Timings Control Register 0 */
+    {0x002B,0x01},   /* DRAM Timings Control Register 1 */
+    {0x0020,0x80},   /* Memory Configuration Register */
+    {0x0030,0x25},   /* Panel Type Register */
+    {0x0031,0x00},   /* MOD Rate Register */
+    {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
+    {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
+    {0x0035,0x01},   /* TFT FPLINE Start Position Register */
+    {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
+    {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
+    {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
+    {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
+    {0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
+    {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
+    {0x0040,0x05},   /* LCD Display Mode Register */
+    {0x0041,0x00},   /* LCD Miscellaneous Register */
+    {0x0042,0x00},   /* LCD Display Start Address Register 0 */
+    {0x0043,0x00},   /* LCD Display Start Address Register 1 */
+    {0x0044,0x00},   /* LCD Display Start Address Register 2 */
+    {0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
+    {0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
+    {0x0048,0x00},   /* LCD Pixel Panning Register */
+    {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
+    {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
+    {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
+    {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
+    {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
+    {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
+    {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
+    {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
+    {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
+    {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
+    {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
+    {0x005B,0x10},   /* TV Output Control Register */
+    {0x0060,0x05},   /* CRT/TV Display Mode Register */
+    {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
+    {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
+    {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
+    {0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
+    {0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
+    {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
+    {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
+    {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
+    {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
+    {0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
+    {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
+    {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
+    {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
+    {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
+    {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
+    {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
+    {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
+    {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
+    {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
+    {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
+    {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
+    {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
+    {0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
+    {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
+    {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
+    {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
+    {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
+    {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
+    {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
+    {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
+    {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
+    {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
+    {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
+    {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
+    {0x0100,0x00},   /* BitBlt Control Register 0 */
+    {0x0101,0x00},   /* BitBlt Control Register 1 */
+    {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
+    {0x0103,0x00},   /* BitBlt Operation Register */
+    {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
+    {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
+    {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
+    {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
+    {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
+    {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
+    {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
+    {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
+    {0x0110,0x00},   /* BitBlt Width Register 0 */
+    {0x0111,0x00},   /* BitBlt Width Register 1 */
+    {0x0112,0x00},   /* BitBlt Height Register 0 */
+    {0x0113,0x00},   /* BitBlt Height Register 1 */
+    {0x0114,0x00},   /* BitBlt Background Color Register 0 */
+    {0x0115,0x00},   /* BitBlt Background Color Register 1 */
+    {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
+    {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
+    {0x01E0,0x00},   /* Look-Up Table Mode Register */
+    {0x01E2,0x00},   /* Look-Up Table Address Register */
+    {0x01E4,0x00},   /* Look-Up Table Data Register */
+    {0x01F0,0x00},   /* Power Save Configuration Register */
+    {0x01F1,0x00},   /* Power Save Status Register */
+    {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
+    {0x01FC,0x01},   /* Display Mode Register */
+    {0, 0}
+};
+#endif /* CONFIG_VIDEO_SED13806_16BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/* Return text to be printed besides the logo. */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1) {
+#ifdef CONFIG_MGT5100
+		strcpy (info, " Total5100");
+#elif CONFIG_TOTAL5200_REV==1
+		strcpy (info, " Total5200");
+#elif CONFIG_TOTAL5200_REV==2
+		strcpy (info, " Total5200 Rev.2");
+#else
+#error CONFIG_TOTAL5200_REV must be 1 or 2.
+#endif
+	} else {
+		info [0] = '\0';
+	}
+}
+#endif
+
+/* Returns  SED13806 base address. First thing called in the driver. */
+unsigned int board_video_init (void)
+{
+	return CFG_LCD_BASE;
+}
+
+/* Called after initializing the SED13806 and before clearing the screen. */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/* Return a pointer to the initialization sequence. */
+const S1D_REGS *board_get_regs (void)
+{
+	return init_regs;
+}
+
+int board_get_width (void)
+{
+	return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+	return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SED13806 */
diff --git a/board/total5200/u-boot.lds b/board/total5200/u-boot.lds
new file mode 100755
index 0000000..3cc2968
--- /dev/null
+++ b/board/total5200/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile
new file mode 100755
index 0000000..c234332
--- /dev/null
+++ b/board/tqm5200/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+#OBJS	:= $(BOARD).o flash.o
+OBJS	:= $(BOARD).o cmd_stk52xx.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c
new file mode 100755
index 0000000..8b9057f
--- /dev/null
+++ b/board/tqm5200/cmd_stk52xx.c
@@ -0,0 +1,1221 @@
+/*
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * SKT52XX specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#define DEFAULT_VOL	45
+#define DEFAULT_FREQ	500
+#define DEFAULT_DURATION	200
+#define LEFT		1
+#define RIGHT		2
+#define LEFT_RIGHT	3
+#define BL_OFF		0
+#define BL_ON		1
+
+#define SM501_GPIO_CTRL_LOW		0x00000008UL
+#define SM501_GPIO_CTRL_HIGH		0x0000000CUL
+#define SM501_POWER_MODE0_GATE		0x00000040UL
+#define SM501_POWER_MODE1_GATE		0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
+#define SM501_GPIO_DATA_LOW 		0x00010000UL
+#define SM501_GPIO_DATA_HIGH		0x00010004UL
+#define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
+#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
+#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+			  unsigned int channel);
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+			unsigned int channel);
+static void spi_init(void);
+static int spi_transmit(unsigned char data);
+static void pcm1772_write_reg(unsigned char addr, unsigned char data);
+static void set_attenuation(unsigned char attenuation);
+
+#ifdef CONFIG_STK52XX
+static void spi_init(void)
+{
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	/* PSC3 as SPI and GPIOs */
+	gpio->port_config &= 0xFFFFF0FF;
+	gpio->port_config |= 0x00000800;
+	/*
+	 * Its important to use the correct order when initializing the
+	 * registers
+	 */
+	spi->ddr = 0x0F; /* set all SPI pins as output */
+	spi->pdr = 0x08; /* set SS high */
+	spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */
+	spi->cr2 = 0x00; /* normal operation */
+	spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */
+}
+
+static int spi_transmit(unsigned char data)
+{
+	int dummy;
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+	spi->dr = data;
+	/* wait for SPI transmission completed */
+	while(!(spi->sr & 0x80))
+	{
+		if (spi->sr & 0x40)	/* if write collision occured */
+		{
+			/* do dummy read to clear status register */
+			dummy = spi->dr;
+			printf ("SPI write collision\n");
+			return -1;
+		}
+	}
+	return (spi->dr);
+}
+
+static void pcm1772_write_reg(unsigned char addr, unsigned char data)
+{
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+	spi->pdr = 0x00; /* Set SS low */
+	spi_transmit(addr);
+	spi_transmit(data);
+	/* wait some time to meet MS# hold time of PCM1772 */
+	udelay (1);
+	spi->pdr = 0x08; /* set SS high */
+}
+
+static void set_attenuation(unsigned char attenuation)
+{
+	pcm1772_write_reg(0x01, attenuation); /* left channel */
+	debug ("PCM1772 attenuation left set to %d.\n", attenuation);
+	pcm1772_write_reg(0x02, attenuation); /* right channel */
+	debug ("PCM1772 attenuation right set to %d.\n", attenuation);
+}
+
+void amplifier_init(void)
+{
+	static int init_done = 0;
+	int i;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	/* Do this only once, because of the long time delay */
+	if (!init_done) {
+		/* configure PCM1772 audio format as I2S */
+		pcm1772_write_reg(0x03, 0x01);
+		/* enable audio amplifier */
+		gpio->sint_gpioe |=  0x02;	/* PSC3_5 as GPIO */
+		gpio->sint_ode &= ~0x02;	/* PSC3_5 is not open Drain */
+		gpio->sint_dvo &= ~0x02;	/* PSC3_5 is LOW */
+		gpio->sint_ddr |=  0x02;	/* PSC3_5 as output */
+		/*
+		 * wait some time to allow amplifier to recover from shutdown
+		 * mode.
+		 */
+		for(i = 0; i < 350; i++)
+			udelay(1000);
+		/*
+		 * The used amplifier (LM4867) has a so called "pop and click"
+		 * elmination filter. The input signal of the amplifier must
+		 * exceed a certain level once after power up to activate the
+		 * generation of the output signal. This is achieved by
+		 * sending a low frequent (nearly inaudible) sawtooth with a
+		 * sufficient signal level.
+		 */
+		set_attenuation(50);
+		i2s_sawtooth (200, 5, LEFT_RIGHT);
+		init_done = 1;
+	}
+}
+
+static void i2s_init(void)
+{
+	unsigned long i;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+	psc->sicr = 0x22E00000;		/* 16 bit data; I2S */
+
+	*(vu_long *)(CFG_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
+						  * 5.617 MHz */
+	*(vu_long *)(CFG_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
+						       * register */
+	psc->ccr = 0x1F03;	/* 16 bit data width; 5.617MHz MCLK */
+	psc->ctur = 0x0F;	/* 16 bit frame width */
+
+	for(i=0;i<128;i++)
+	{
+		psc->psc_buffer_32 = 0; /* clear tx fifo */
+	}
+}
+
+static int i2s_play_wave(unsigned long addr, unsigned long len)
+{
+	unsigned long i;
+	unsigned char *wave_file = (uchar *)addr + 44;	/* quick'n dirty: skip
+							 * wav header*/
+	unsigned char swapped[4];
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+	/*
+	 * play wave file in memory; bytes/words are be swapped
+	 */
+	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	for(i = 0;i < (len / 4); i++) {
+		swapped[3]=*wave_file++;
+		swapped[2]=*wave_file++;
+		swapped[1]=*wave_file++;
+		swapped[0]=*wave_file++;
+		psc->psc_buffer_32 =  *((unsigned long*)swapped);
+		while (psc->tfnum > 400) {
+			if(ctrlc())
+				return 0;
+		}
+	}
+	while (psc->tfnum > 0);		/* wait for fifo empty */
+	udelay (100);
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+	return 0;
+}
+
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+			unsigned int channel)
+{
+	long i,j;
+	unsigned long data;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	/*
+	 * Generate sawtooth. Start with middle level up to highest level. Then
+	 * go to lowest level and back to middle level.
+	 */
+	for(j = 0; j < ((duration * freq) / 1000); j++)	{
+		for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4))))	{
+			data = (i & 0xFFFF);
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+		for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) {
+			data = (i & 0xFFFF);
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+		for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) {
+			data = (i & 0xFFFF);
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+	}
+	while (psc->tfnum > 0);		/* wait for fifo empty */
+	udelay (100);
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+	return 0;
+}
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+			 unsigned int channel)
+{
+	long i,j;
+	unsigned long data;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	/*
+	 * Generate sqarewave. Start with high level, duty cycle 1:1.
+	 */
+	for(j = 0; j < ((duration * freq) / 1000); j++)	{
+		for(i = 0; i < (44100/(freq*2)); i ++) {
+			data = 0x7FFF;
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+		for(i = 0; i < (44100/(freq*2)); i ++) {
+			data = 0x8000;
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+	}
+	while (psc->tfnum > 0);		/* wait for fifo empty */
+	udelay (100);
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+	return 0;
+}
+
+static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned long reg, val, duration;
+	char *tmp;
+	unsigned int freq, channel;
+	unsigned char volume;
+	int rcode = 1;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	spi_init();
+	i2s_init();
+	amplifier_init();
+
+	if ((tmp = getenv ("volume")) != NULL) {
+		volume = simple_strtoul (tmp, NULL, 10);
+	} else {
+		volume = DEFAULT_VOL;
+	}
+	set_attenuation(volume);
+
+	switch (argc) {
+	case 0:
+	case 1:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 2:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			printf ("Play sawtooth\n");
+			rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ,
+					      LEFT_RIGHT);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ,
+						LEFT_RIGHT);
+			return rcode;
+		}
+
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 3:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			printf ("Play sawtooth\n");
+			rcode = i2s_sawtooth (duration, DEFAULT_FREQ,
+					      LEFT_RIGHT);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (duration, DEFAULT_FREQ,
+						LEFT_RIGHT);
+			return rcode;
+		}
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 4:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			printf ("Play sawtooth\n");
+			rcode = i2s_sawtooth (duration, freq,
+					      LEFT_RIGHT);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (duration, freq,
+						LEFT_RIGHT);
+			return rcode;
+		} else if (strcmp(argv[1],"pcm1772") == 0) {
+			reg = simple_strtoul(argv[2], NULL, 10);
+			val = simple_strtoul(argv[3], NULL, 10);
+			printf("Set PCM1772 %lu. %lu\n", reg, val);
+			pcm1772_write_reg((uchar)reg, (uchar)val);
+			return 0;
+		}
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	case 5:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			if (strncmp(argv[4],"l",1) == 0)
+				channel = LEFT;
+			else if (strncmp(argv[4],"r",1) == 0)
+				channel = RIGHT;
+			else
+				channel = LEFT_RIGHT;
+			printf ("Play squarewave\n");
+			rcode = i2s_sawtooth (duration, freq,
+					      channel);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			if (strncmp(argv[4],"l",1) == 0)
+				channel = LEFT;
+			else if (strncmp(argv[4],"r",1) == 0)
+				channel = RIGHT;
+			else
+				channel = LEFT_RIGHT;
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (duration, freq,
+						channel);
+			return rcode;
+		}
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+	printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
+	return 1;
+}
+
+static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned long length, addr;
+	unsigned char volume;
+	int rcode = 1;
+	char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	spi_init();
+	i2s_init();
+	amplifier_init();
+
+	switch (argc) {
+
+	case 3:
+		length = simple_strtoul(argv[2], NULL, 16);
+		addr = simple_strtoul(argv[1], NULL, 16);
+		break;
+
+	case 2:
+		if ((tmp = getenv ("filesize")) != NULL) {
+			length = simple_strtoul (tmp, NULL, 16);
+		} else {
+			puts ("No filesize provided\n");
+			return 1;
+		}
+		addr = simple_strtoul(argv[1], NULL, 16);
+
+	case 1:
+		if ((tmp = getenv ("filesize")) != NULL) {
+			length = simple_strtoul (tmp, NULL, 16);
+		} else {
+			puts ("No filesize provided\n");
+			return 1;
+		}
+		if ((tmp = getenv ("loadaddr")) != NULL) {
+			addr = simple_strtoul (tmp, NULL, 16);
+		} else {
+			puts ("No loadaddr provided\n");
+			return 1;
+		}
+		break;
+
+	default:
+		printf("Usage:\nwav <addr> <length[s]\n");
+		return 1;
+		break;
+	}
+
+	if ((tmp = getenv ("volume")) != NULL) {
+		volume = simple_strtoul (tmp, NULL, 10);
+	} else {
+		volume = DEFAULT_VOL;
+	}
+	set_attenuation(volume);
+
+	printf("Play wave file at %#p with length %#x\n", addr, length);
+	rcode = i2s_play_wave(addr, length);
+
+	return rcode;
+}
+
+static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned char volume;
+	unsigned int channel;
+	int rcode;
+	char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	spi_init();
+	i2s_init();
+	amplifier_init();
+
+	switch (argc) {
+	case 0:
+	case 1:
+		channel = LEFT_RIGHT;
+		break;
+	case 2:
+		if (strncmp(argv[1],"l",1) == 0)
+			channel = LEFT;
+		else if (strncmp(argv[1],"r",1) == 0)
+			channel = RIGHT;
+		else
+			channel = LEFT_RIGHT;
+		break;
+	default:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if ((tmp = getenv ("volume")) != NULL) {
+		volume = simple_strtoul (tmp, NULL, 10);
+	} else {
+		volume = DEFAULT_VOL;
+	}
+	set_attenuation(volume);
+
+	printf("Beep on ");
+	if (channel == LEFT)
+		printf ("left ");
+	else if (channel == RIGHT)
+		printf ("right ");
+	else
+		printf ("left and right ");
+	printf ("channel\n");
+
+	rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel);
+
+	return rcode;
+}
+
+void led_init(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	/* configure PSC3 for SPI and GPIO */
+	gpio->port_config &= ~(0x00000F00);
+	gpio->port_config |=   0x00000800;
+
+	gpio->simple_gpioe &= ~(0x00000F00);
+	gpio->simple_gpioe |=   0x00000F00;
+
+	gpio->simple_ddr &= ~(0x00000F00);
+	gpio->simple_ddr |=   0x00000F00;
+
+	/* configure timer 4-7 for simple GPIO output */
+	gpt->gpt4.emsr |=  0x00000024;
+	gpt->gpt5.emsr |=  0x00000024;
+	gpt->gpt6.emsr |=  0x00000024;
+	gpt->gpt7.emsr |=  0x00000024;
+
+
+	/* enable SM501 GPIO control (in both power modes) */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+
+	/* configure SM501 gpio pins 24-27 as output */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24);
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24);
+
+	/* configure SM501 gpio pins 48-51 as output */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
+}
+
+/*
+ * return 1 if led number unknown
+ * return 0 else
+ */
+int do_led(char *argv[])
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	switch 	(simple_strtoul(argv[2], NULL, 10)) {
+
+	case 0:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 8);
+		} else {
+			gpio->simple_dvo &= ~(1 << 8);
+		}
+		break;
+
+	case 1:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 9);
+		} else {
+			gpio->simple_dvo &= ~(1 << 9);
+		}
+		break;
+
+	case 2:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 10);
+		} else {
+			gpio->simple_dvo &= ~(1 << 10);
+		}
+		break;
+
+	case 3:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 11);
+		} else {
+			gpio->simple_dvo &= ~(1 << 11);
+		}
+		break;
+
+	case 4:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt4.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt4.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 5:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt5.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt5.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 6:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt6.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt6.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 7:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt7.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt7.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 24:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 24);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 24);
+		}
+		break;
+
+	case 25:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 25);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 25);
+		}
+		break;
+
+	case 26:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 26);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 26);
+		}
+		break;
+
+	case 27:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 27);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 27);
+		}
+		break;
+
+	case 48:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 16);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 16);
+		}
+		break;
+
+	case 49:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 17);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 17);
+		}
+		break;
+
+	case 50:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 18);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 18);
+		}
+		break;
+
+	case 51:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 19);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 19);
+		}
+		break;
+
+	default:
+		printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * return 1 on CAN initialization failure
+ * return 0 if no failure
+ */
+int can_init(void)
+{
+	static int init_done = 0;
+	int i;
+	struct mpc5xxx_mscan *can1 =
+		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 =
+		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+
+	/* GPIO configuration of the CAN pins is done in TQM5200.h */
+
+	if (!init_done) {
+		/* init CAN 1 */
+		can1->canctl1 |= 0x80;	/* CAN enable */
+		udelay(100);
+
+		i = 0;
+		can1->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can1->canctl1 & 0x02)) {
+			udelay(10);
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 initialize error, "
+				"can not enter sleep mode!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		}
+		i = 0;
+		can1->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can1->canctl1 & 0x01)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can1->canctl1 = 0x80;
+		can1->canctl1 |= 0x40;
+		can1->canbtr0 = 0x0F;
+		can1->canbtr1 = 0x7F;
+		can1->canidac &= ~(0x30);
+		can1->canidar1 = 0x00;
+		can1->canidar3 = 0x00;
+		can1->canidar5 = 0x00;
+		can1->canidar7 = 0x00;
+		can1->canidmr0 = 0xFF;
+		can1->canidmr1 = 0xFF;
+		can1->canidmr2 = 0xFF;
+		can1->canidmr3 = 0xFF;
+		can1->canidmr4 = 0xFF;
+		can1->canidmr5 = 0xFF;
+		can1->canidmr6 = 0xFF;
+		can1->canidmr7 = 0xFF;
+
+		i = 0;
+		can1->canctl0 &= ~(0x01);	/* leave init mode */
+		can1->canctl0 &= ~(0x02);
+		/* wait until init and sleep mode left */
+		while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+
+		/* init CAN 2 */
+		can2->canctl1 |= 0x80;	/* CAN enable */
+		udelay(100);
+
+		i = 0;
+		can2->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can2->canctl1 & 0x02))	{
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		i = 0;
+		can2->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can2->canctl1 & 0x01))	{
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can2->canctl1 = 0x80;
+		can2->canctl1 |= 0x40;
+		can2->canbtr0 = 0x0F;
+		can2->canbtr1 = 0x7F;
+		can2->canidac &= ~(0x30);
+		can2->canidar1 = 0x00;
+		can2->canidar3 = 0x00;
+		can2->canidar5 = 0x00;
+		can2->canidar7 = 0x00;
+		can2->canidmr0 = 0xFF;
+		can2->canidmr1 = 0xFF;
+		can2->canidmr2 = 0xFF;
+		can2->canidmr3 = 0xFF;
+		can2->canidmr4 = 0xFF;
+		can2->canidmr5 = 0xFF;
+		can2->canidmr6 = 0xFF;
+		can2->canidmr7 = 0xFF;
+		can2->canctl0 &= ~(0x01);	/* leave init mode */
+		can2->canctl0 &= ~(0x02);
+
+		i = 0;
+		/* wait until init mode left */
+		while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		init_done = 1;
+	}
+	return 0;
+}
+
+/*
+ * return 1 on CAN failure
+ * return 0 if no failure
+ */
+int do_can(char *argv[])
+{
+	int i;
+	struct mpc5xxx_mscan *can1 =
+		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 =
+		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+
+	/* send a message on CAN1 */
+	can1->cantbsel = 0x01;
+	can1->cantxfg.idr[0] = 0x55;
+	can1->cantxfg.idr[1] = 0x00;
+	can1->cantxfg.idr[1] &= ~0x8;
+	can1->cantxfg.idr[1] &= ~0x10;
+	can1->cantxfg.dsr[0] = 0xCC;
+	can1->cantxfg.dlr = 1;
+	can1->cantxfg.tbpr = 0;
+	can1->cantflg = 0x01;
+
+	i = 0;
+	while ((can1->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 send timeout, "
+				"can not send message!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+	udelay(1000);
+
+	i = 0;
+	while (!(can2->canrflg & 0x01))	{
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 receive timeout, "
+				"no message received!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+
+	if (can2->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN2 receive error, "
+			 "data mismatch!\n",
+			__FUNCTION__);
+		return 1;
+	}
+
+	/* send a message on CAN2 */
+	can2->cantbsel = 0x01;
+	can2->cantxfg.idr[0] = 0x55;
+	can2->cantxfg.idr[1] = 0x00;
+	can2->cantxfg.idr[1] &= ~0x8;
+	can2->cantxfg.idr[1] &= ~0x10;
+	can2->cantxfg.dsr[0] = 0xCC;
+	can2->cantxfg.dlr = 1;
+	can2->cantxfg.tbpr = 0;
+	can2->cantflg = 0x01;
+
+	i = 0;
+	while ((can2->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 send error, "
+				"can not send message!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+	udelay(1000);
+
+	i = 0;
+	while (!(can1->canrflg & 0x01))	{
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 receive timeout, "
+				"no message received!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+
+	if (can1->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN1 receive error 0x%02x\n",
+			__FUNCTION__, (can1->canrxfg.dsr[0]));
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * return 1 if rs232 port unknown
+ * return 2 on txd/rxd failure (only rs232 2)
+ * return 3 on rts/cts failure
+ * return 0 if no failure
+ */
+int do_rs232(char *argv[])
+{
+	int error_status = 0;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+	switch 	(simple_strtoul(argv[2], NULL, 10)) {
+
+	case 1:
+		/* check RTS <-> CTS loop */
+		/* set rts to 0 */
+		psc1->op1 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 0) {
+			error_status = 3;
+			printf ("%s: failure at rs232_1, cts status is %d "
+				"(should be 0)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+
+		/* set rts to 1 */
+		psc1->op0 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 1) {
+			error_status = 3;
+			printf ("%s: failure at rs232_1, cts status is %d "
+				"(should be 1)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+
+		break;
+
+	case 2:
+		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
+		gpio->simple_ddr &= ~(0x00000F00);
+		gpio->simple_ddr |=   0x00000500;
+
+		/* check TXD <-> RXD loop */
+		/* set TXD to 1 */
+		gpio->simple_dvo |=   (1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
+			error_status = 2;
+			printf ("%s: failure at rs232_2, rxd status is %d "
+				"(should be 1)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* set TXD to 0 */
+		gpio->simple_dvo &= ~(1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
+			error_status = 2;
+			printf ("%s: failure at rs232_2, rxd status is %d "
+				"(should be 0)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* check RTS <-> CTS loop */
+		/* set RTS to 1 */
+		gpio->simple_dvo |=   (1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
+			error_status = 3;
+			printf ("%s: failure at rs232_2, cts status is %d "
+				"(should be 1)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+
+		/* set RTS to 0 */
+		gpio->simple_dvo &= ~(1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
+			error_status = 3;
+			printf ("%s: failure at rs232_2, cts status is %d "
+				"(should be 0)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+
+		/* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */
+		gpio->simple_ddr &= ~(0x00000F00);
+		gpio->simple_ddr |=   0x00000F00;
+		break;
+
+	default:
+		printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
+		error_status = 1;
+		break;
+	}
+
+	return error_status;
+}
+
+static void sm501_backlight (unsigned int state)
+{
+	if (state == BL_ON) {
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+			(1 << 26) | (1 << 27);
+	} else if (state == BL_OFF)
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+			~((1 << 26) | (1 << 27));
+}
+
+int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int rcode;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	led_init();
+	can_init();
+
+	switch (argc) {
+
+	case 0:
+	case 1:
+		break;
+
+	case 2:
+		if (strncmp (argv[1], "can", 3) == 0) {
+			rcode = do_can (argv);
+			if (rcode == 0)
+				printf ("OK\n");
+			else
+				printf ("Error\n");
+			return rcode;
+		}
+		break;
+
+	case 3:
+		if (strncmp (argv[1], "rs232", 3) == 0) {
+			rcode = do_rs232 (argv);
+			if (rcode == 0)
+				printf ("OK\n");
+			else
+				printf ("Error\n");
+			return rcode;
+		} else if (strncmp (argv[1], "backlight", 4) == 0) {
+			if (strncmp (argv[2], "on", 2) == 0) {
+				sm501_backlight (BL_ON);
+				return 0;
+			}
+			else if (strncmp (argv[2], "off", 3) == 0) {
+				sm501_backlight (BL_OFF);
+				return 0;
+			}
+		}
+		break;
+
+	case 4:
+		if (strcmp (argv[1], "led") == 0) {
+			return (do_led (argv));
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n");
+	return 1;
+}
+
+
+U_BOOT_CMD(
+	sound ,    5,    1,     cmd_sound,
+	"sound   - Sound sub-system\n",
+	"saw [duration] [freq] [channel]\n"
+	"    - generate sawtooth for 'duration' ms with frequency 'freq'\n"
+	"      on left \"l\" or right \"r\" channel\n"
+	"sound square [duration] [freq] [channel]\n"
+	"    - generate squarewave for 'duration' ms with frequency 'freq'\n"
+	"      on left \"l\" or right \"r\" channel\n"
+	"pcm1772 reg val\n"
+);
+
+U_BOOT_CMD(
+	wav ,    3,    1,     cmd_wav,
+	"wav     - play wav file\n",
+	"[addr] [bytes]\n"
+	"    - play wav file at address 'addr' with length 'bytes'\n"
+);
+
+U_BOOT_CMD(
+	beep ,    2,    1,     cmd_beep,
+	"beep    - play short beep\n",
+	"[channel]\n"
+	"    - play short beep on \"l\"eft or \"r\"ight channel\n"
+);
+
+U_BOOT_CMD(
+	fkt ,	4,	1,	cmd_fkt,
+	"fkt     - Function test routines\n",
+	"led number on/off\n"
+	"     - 'number's like printed on SKT52XX board\n"
+	"fkt can\n"
+	"     - loopback plug for X83 required\n"
+	"fkt rs232 number\n"
+	"     - loopback plug(s) for X2 required\n"
+	"fkt backlight on/off\n"
+	"     - switch backlight on or off\n"
+);
+#endif /* CONFIG_STK52XX */
+#endif /* CFG_CMD_BSP */
diff --git a/board/tqm5200/config.mk b/board/tqm5200/config.mk
new file mode 100755
index 0000000..585a99a
--- /dev/null
+++ b/board/tqm5200/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM5200 board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFC000000   boot low (standard configuration with room for max 64 MByte
+#		     Flash ROM)
+#	0x00100000   boot from RAM (for testing only)
+#
+
+ifndef TEXT_BASE
+## Standard: boot low
+TEXT_BASE = 0xFC000000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/tqm5200/flash.c b/board/tqm5200/flash.c
new file mode 100755
index 0000000..af4d78a
--- /dev/null
+++ b/board/tqm5200/flash.c
@@ -0,0 +1,497 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * CPU to flash interface is 32-bit, so make declaration accordingly
+ */
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define FLASH_CYCLE1	0x0555
+#define FLASH_CYCLE2	0x02aa
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static flash_info_t *flash_get_info(ulong base);
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	extern void flash_preinit(void);
+	ulong flashbase = CFG_FLASH_BASE;
+
+	flash_preinit();
+
+	/* Init: no FLASHes known */
+	memset(&flash_info[0], 0, sizeof(flash_info_t));
+
+	flash_info[0].size =
+		flash_get_size((FPW *)flashbase, &flash_info[0]);
+
+	size = flash_info[0].size;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CFG_MONITOR_BASE));
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+		      flash_get_info(CFG_ENV_ADDR));
+#endif
+
+	return size ? size : 1;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static flash_info_t *flash_get_info(ulong base)
+{
+	int i;
+	flash_info_t * info;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+		info = & flash_info[i];
+		if (info->size && info->start[0] <= base &&
+		    base <= info->start[0] + info->size - 1)
+			break;
+	}
+
+	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_STM:	printf ("STM ");		break;
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV128U:
+		printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
+{
+	int i;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	/* Write auto select command sequence and test FLASH answer */
+	addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE2] = (FPW)0x00550055;	/* for AMD, Intel ignores this */
+	addr[FLASH_CYCLE1] = (FPW)0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	udelay(100);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		debug ("Manufacturer: AMD (Spansion)\n");
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		debug ("Manufacturer: Intel (not supported yet)\n");
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
+
+	case (FPW)AMD_ID_LV160B:
+		debug ("Chip: AM29LV160MB\n");
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		/*
+		 * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
+		 * the other ones are 64 kB
+		 */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for( i = 4; i < info->sector_count; i++ )
+			info->start[i] =
+				base + (i * 2 * (64 << 10)) - 0x00060000;
+		break;		/* => 4 MB */
+
+	case AMD_ID_MIRROR:
+		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
+			addr[14], addr[15]);
+
+		switch(addr[14]) {
+		case AMD_ID_LV128U_2:
+			if (addr[15] != AMD_ID_LV128U_3) {
+				debug ("Chip: AM29LVxxxM -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+				info->sector_count = 0;
+				info->size = 0;
+			} else {
+				debug ("Chip: AM29LV128M\n");
+				info->flash_id += FLASH_AMLV128U;
+				info->sector_count = 256;
+				info->size = 0x02000000;
+				for (i = 0; i < info->sector_count; i++) {
+					info->start[i] = base;
+					base += 0x20000;
+				}
+			}
+			break;	/* => 32 MB	*/
+		default:
+			debug ("Chip: *** unknown ***\n");
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			break;
+		}
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+	}
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	/*
+	 * Get lower word aligned address. Assumes 32 bit flash bus width.
+	 */
+	wp = (addr & ~3);
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word_amd(info, (FPW *)wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[FLASH_CYCLE1] = (FPW)0x00AA00AA;	/* unlock */
+	base[FLASH_CYCLE2] = (FPW)0x00550055;	/* unlock */
+	base[FLASH_CYCLE1] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer (0);
+
+	/* data polling for D7 */
+	while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/tqm5200/mt48lc16m16a2-75.h b/board/tqm5200/mt48lc16m16a2-75.h
new file mode 100755
index 0000000..3f1e169
--- /dev/null
+++ b/board/tqm5200/mt48lc16m16a2-75.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2	0x8AD70000
+/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c
new file mode 100755
index 0000000..6aad920
--- /dev/null
+++ b/board/tqm5200/tqm5200.c
@@ -0,0 +1,673 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+#endif
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+		hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
+
+	/* find RAM size using SDRAM CS1 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+/*	return dramsize + dramsize2; */
+	return dramsize;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
+int checkboard (void)
+{
+#if defined (CONFIG_AEVFIFO)
+	puts ("Board: AEVFIFO\n");
+	return 0;
+#endif
+#if defined (CONFIG_TQM5200_AA)
+	puts ("Board: TQM5200-AA (TQ-Components GmbH)\n");
+#elif defined (CONFIG_TQM5200_AB)
+	puts ("Board: TQM5200-AB (TQ-Components GmbH)\n");
+#elif defined (CONFIG_TQM5200_AC)
+	puts ("Board: TQM5200-AC (TQ-Components GmbH)\n");
+#elif defined (CONFIG_TQM5200)
+	puts ("Board: TQM5200 (TQ-Components GmbH)\n");
+#endif
+#if defined (CONFIG_STK52XX)
+	puts ("       on a STK52XX baseboard\n");
+#endif
+
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+#if defined(CONFIG_MGT5100)
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+#endif
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#if defined (CONFIG_MINIFAP)
+#define SM501_POWER_MODE0_GATE		0x00000040UL
+#define SM501_POWER_MODE1_GATE		0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
+#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
+#define SM501_GPIO_DATA_HIGH		0x00010004UL
+#define SM501_GPIO_51			0x00080000UL
+#else
+#define GPIO_PSC1_4	0x01000000UL
+#endif
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+#if defined (CONFIG_MINIFAP)
+	/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
+
+	/* enable GPIO control (in both power modes) */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+	/* configure GPIO51 as output */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
+		SM501_GPIO_51;
+#else
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+#endif
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+#if defined (CONFIG_MINIFAP)
+	if (idereset) {
+		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+			~SM501_GPIO_51;
+	} else {
+		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+			SM501_GPIO_51;
+	}
+#else
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+	}
+#endif
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+#ifdef CONFIG_POST
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+	struct mpc5xxx_gpio *gpio;
+
+	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
+
+	/*
+	 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
+	 * CODEC or UART mode. Consumer IrDA should still be possible.
+	 */
+	gpio->port_config &= ~(0x07000000);
+	gpio->port_config |=   0x03000000;
+
+	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+	gpio->simple_gpioe |= 0x20000000;
+
+	/* Configure GPIO_IRDA_1 as input */
+	gpio->simple_ddr &= ~(0x20000000);
+
+	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
+}
+#endif
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+void post_word_store (ulong a)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
+
+	*save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
+
+	return *save_addr;
+}
+#endif	/* CONFIG_POST || CONFIG_LOGBUFFER*/
+
+#ifdef CONFIG_PS2MULT
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+	ps2mult_early_init();
+	return (0);
+}
+#endif
+#endif /* CONFIG_PS2MULT */
+
+#if defined(CONFIG_CS_AUTOCONF)
+int last_stage_init (void)
+{
+	/*
+	 * auto scan for really existing devices and re-set chip select
+	 * configuration.
+	 */
+	u16 save, tmp;
+	int restore;
+
+	/*
+	 * Check for SRAM and SRAM size
+	 */
+
+	/* save original SRAM content  */
+	save = *(volatile u16 *)CFG_CS2_START;
+	restore = 1;
+
+	/* write test pattern to SRAM */
+	*(volatile u16 *)CFG_CS2_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in SRAM detection\n");
+
+	if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
+		/* no SRAM at all, disable cs */
+		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
+		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
+		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
+		restore = 0;
+		__asm__ volatile ("sync");
+	} else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
+		/* make sure that we access a mirrored address */
+		*(volatile u16 *)CFG_CS2_START = 0x1111;
+		__asm__ volatile ("sync");
+		if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
+			/* SRAM size = 512 kByte */
+			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
+								0x80000);
+			__asm__ volatile ("sync");
+			puts ("SRAM:  512 kB\n");
+		}
+		else
+			puts ("!! possible error in SRAM detection\n");
+	} else {
+		puts ("SRAM:  1 MB\n");
+	}
+	/* restore origianl SRAM content  */
+	if (restore) {
+		*(volatile u16 *)CFG_CS2_START = save;
+		__asm__ volatile ("sync");
+	}
+
+	/*
+	 * Check for Grafic Controller
+	 */
+
+	/* save origianl FB content  */
+	save = *(volatile u16 *)CFG_CS1_START;
+	restore = 1;
+
+	/* write test pattern to FB memory */
+	*(volatile u16 *)CFG_CS1_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in grafic controller detection\n");
+
+	if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+		/* no grafic controller at all, disable cs */
+		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
+		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
+		*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
+		restore = 0;
+		__asm__ volatile ("sync");
+	} else {
+		puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
+	}
+	/* restore origianl FB content  */
+	if (restore) {
+		*(volatile u16 *)CFG_CS1_START = save;
+		__asm__ volatile ("sync");
+	}
+
+	return 0;
+}
+#endif /* CONFIG_CS_AUTOCONF */
+
+#ifdef CONFIG_VIDEO_SM501
+
+#define DISPLAY_WIDTH   640
+#define DISPLAY_HEIGHT  480
+
+#ifdef CONFIG_VIDEO_SM501_8BPP
+#error CONFIG_VIDEO_SM501_8BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_8BPP */
+
+#ifdef CONFIG_VIDEO_SM501_16BPP
+#error CONFIG_VIDEO_SM501_16BPP not supported.
+#endif /* CONFIG_VIDEO_SM501_16BPP */
+#ifdef CONFIG_VIDEO_SM501_32BPP
+static const SMI_REGS init_regs [] =
+{
+#if 0 /* CRT only */
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x10090a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x10090a01},
+	{0x00054, 0x0},
+	{0x80200, 0x00010000},
+	{0x80204, 0x0},
+	{0x80208, 0x0A000A00},
+	{0x8020C, 0x02fa027f},
+	{0x80210, 0x004a028b},
+	{0x80214, 0x020c01df},
+	{0x80218, 0x000201e9},
+	{0x80200, 0x00013306},
+#else  /* panel + CRT */
+	{0x00004, 0x0},
+	{0x00048, 0x00021807},
+	{0x0004C, 0x091a0a01},
+	{0x00054, 0x1},
+	{0x00040, 0x00021807},
+	{0x00044, 0x091a0a01},
+	{0x00054, 0x0},
+	{0x80000, 0x0f013106},
+	{0x80004, 0xc428bb17},
+	{0x8000C, 0x00000000},
+	{0x80010, 0x0a000a00},
+	{0x80014, 0x02800000},
+	{0x80018, 0x01e00000},
+	{0x8001C, 0x00000000},
+	{0x80020, 0x01e00280},
+	{0x80024, 0x02fa027f},
+	{0x80028, 0x004a028b},
+	{0x8002C, 0x020c01df},
+	{0x80030, 0x000201e9},
+	{0x80200, 0x00010000},
+#endif
+	{0, 0}
+};
+#endif /* CONFIG_VIDEO_SM501_32BPP */
+
+#ifdef CONFIG_CONSOLE_EXTRA_INFO
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1) {
+#if defined (CONFIG_TQM5200_AA)
+		strcpy (info, " Board: TQM5200-AA (TQ-Components GmbH)");
+#elif defined (CONFIG_TQM5200_AB)
+		strcpy (info, " Board: TQM5200-AB (TQ-Components GmbH)");
+#elif defined (CONFIG_TQM5200_AC)
+		strcpy (info, " Board: TQM5200-AC (TQ-Components GmbH)");
+#elif defined (CONFIG_TQM5200)
+		strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
+#else
+#error No supported board selected
+#endif
+#if defined (CONFIG_STK52XX)
+	} else if (line_number == 2) {
+		strcpy (info, "        on a STK52XX baseboard");
+#endif
+	}
+	else {
+		info [0] = '\0';
+	}
+}
+#endif
+
+/*
+ * Returns SM501 register base address. First thing called in the
+ * driver. Checks if SM501 is physically present.
+ */
+unsigned int board_video_init (void)
+{
+	u16 save, tmp;
+	int restore, ret;
+
+	/*
+	 * Check for Grafic Controller
+	 */
+
+	/* save origianl FB content  */
+	save = *(volatile u16 *)CFG_CS1_START;
+	restore = 1;
+
+	/* write test pattern to FB memory */
+	*(volatile u16 *)CFG_CS1_START = 0xA5A5;
+	__asm__ volatile ("sync");
+	/*
+	 * Put a different pattern on the data lines: otherwise they may float
+	 * long enough to read back what we wrote.
+	 */
+	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	if (tmp == 0xA5A5)
+		puts ("!! possible error in grafic controller detection\n");
+
+	if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+		/* no grafic controller found */
+		restore = 0;
+		ret = 0;
+	} else {
+		ret = SM501_MMIO_BASE;
+	}
+
+	if (restore) {
+		*(volatile u16 *)CFG_CS1_START = save;
+		__asm__ volatile ("sync");
+	}
+	return ret;
+}
+
+/*
+ * Returns SM501 framebuffer address
+ */
+unsigned int board_video_get_fb (void)
+{
+	return SM501_FB_BASE;
+}
+
+/*
+ * Called after initializing the SM501 and before clearing the screen.
+ */
+void board_validate_screen (unsigned int base)
+{
+}
+
+/*
+ * Return a pointer to the initialization sequence.
+ */
+const SMI_REGS *board_get_regs (void)
+{
+	return init_regs;
+}
+
+int board_get_width (void)
+{
+	return DISPLAY_WIDTH;
+}
+
+int board_get_height (void)
+{
+	return DISPLAY_HEIGHT;
+}
+
+#endif /* CONFIG_VIDEO_SM501 */
diff --git a/board/tqm5200/u-boot.lds b/board/tqm5200/u-boot.lds
new file mode 100755
index 0000000..3cc2968
--- /dev/null
+++ b/board/tqm5200/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/tqm8260/Makefile b/board/tqm8260/Makefile
new file mode 100755
index 0000000..c10b9fe
--- /dev/null
+++ b/board/tqm8260/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/tqm8260/config.mk b/board/tqm8260/config.mk
new file mode 100755
index 0000000..1fe9952
--- /dev/null
+++ b/board/tqm8260/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8260 boards
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+TEXT_BASE = 0x40000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
diff --git a/board/tqm8260/flash.c b/board/tqm8260/flash.c
new file mode 100755
index 0000000..056fe81
--- /dev/null
+++ b/board/tqm8260/flash.c
@@ -0,0 +1,488 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for AMD devices on the TQM8260 board
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#define V_ULONG(a)	(*(volatile unsigned long *)( a ))
+#define V_BYTE(a)	(*(volatile unsigned char *)( a ))
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset (void)
+{
+	if (flash_info[0].flash_id != FLASH_UNKNOWN) {
+		V_ULONG (flash_info[0].start[0]) = 0x00F000F0;
+		V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0;
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	/* Write auto select command sequence and test FLASH answer */
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055;
+	V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090;
+
+	flashtest_h = V_ULONG (baseaddr);	/* manufacturer ID     */
+	flashtest_l = V_ULONG (baseaddr + 4);
+
+	switch ((int) flashtest_h) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash     */
+	}
+
+	flashtest_h = V_ULONG (baseaddr + 8);	/* device ID           */
+	flashtest_l = V_ULONG (baseaddr + 12);
+	if (flashtest_h != flashtest_l) {
+		info->flash_id = FLASH_UNKNOWN;
+	} else {
+		switch (flashtest_h) {
+		case AMD_ID_LV800T:
+			info->flash_id += FLASH_AM800T;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV800B:
+			info->flash_id += FLASH_AM800B;
+			info->sector_count = 19;
+			info->size = 0x00400000;
+			break;			/* 4 * 1 MB = 4 MB  */
+		case AMD_ID_LV160T:
+			info->flash_id += FLASH_AM160T;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_LV160B:
+			info->flash_id += FLASH_AM160B;
+			info->sector_count = 35;
+			info->size = 0x00800000;
+			break;			/* 4 * 2 MB = 8 MB  */
+		case AMD_ID_DL322T:
+			info->flash_id += FLASH_AMDL322T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL322B:
+			info->flash_id += FLASH_AMDL322B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323T:
+			info->flash_id += FLASH_AMDL323T;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_DL323B:
+			info->flash_id += FLASH_AMDL323B;
+			info->sector_count = 71;
+			info->size = 0x01000000;
+			break;			/* 4 * 4 MB = 16 MB */
+		case AMD_ID_LV640U:
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x02000000;
+			break;			/* 4 * 8 MB = 32 MB */
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);		/* no or unknown flash     */
+		}
+	}
+
+	if (flashtest_h == AMD_ID_LV640U) {
+
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+
+	} else if (info->flash_id & FLASH_BTYPE) {
+
+		/* set up sector start adress table (bottom sector type) */
+		info->start[0] = baseaddr + 0x00000000;
+		info->start[1] = baseaddr + 0x00010000;
+		info->start[2] = baseaddr + 0x00018000;
+		info->start[3] = baseaddr + 0x00020000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
+		}
+
+	} else {
+
+		/* set up sector start adress table (top sector type) */
+		i = info->sector_count - 1;
+		info->start[i--] = baseaddr + info->size - 0x00010000;
+		info->start[i--] = baseaddr + info->size - 0x00018000;
+		info->start[i--] = baseaddr + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = baseaddr + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		if ((V_ULONG (info->start[i] + 16) & 0x00010001) ||
+			(V_ULONG (info->start[i] + 20) & 0x00010001)) {
+			info->protect[i] = 1;	/* D0 = 1 if protected */
+		} else {
+			info->protect[i] = 0;
+		}
+	}
+
+	flash_reset ();
+	return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 >> 20);
+	}
+
+	/*
+	 * protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf ("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf ("FUJITSU ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM800T:
+		printf ("29LV800T (8 M, top sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf ("29LV800T (8 M, bottom sector)\n");
+		break;
+	case FLASH_AM160T:
+		printf ("29LV160T (16 M, top sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf ("29LV160B (16 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:
+		printf ("29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:
+		printf ("29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:
+		printf ("29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:
+		printf ("29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AM640U:
+		printf ("29LV640D (64 M, uniform sector)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	udelay (1000);
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			V_ULONG (info->start[sect]) = 0x00300030;
+			V_ULONG (info->start[sect] + 4) = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
+	       (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
+	{
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	flash_reset ();
+
+	printf (" done\n");
+	return 0;
+}
+
+static int write_dword (flash_info_t *, ulong, unsigned char *);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong dp;
+	static unsigned char bb[8];
+	int i, l, rc, cc = cnt;
+
+	dp = (addr & ~7);		/* get lower dword aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - dp) != 0) {
+		for (i = 0; i < 8; i++)
+			bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++;
+		if ((rc = write_dword (info, dp, bb)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		cc -= 8 - l;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cc >= 8) {
+		if ((rc = write_dword (info, dp, src)) != 0) {
+			return (rc);
+		}
+		dp += 8;
+		src += 8;
+		cc -= 8;
+	}
+
+	if (cc <= 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	for (i = 0; i < 8; i++) {
+		bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i);
+	}
+	return (write_dword (info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
+{
+	ulong start, cl, ch;
+	int flag, i;
+
+	for (ch = 0, i = 0; i < 4; i++)
+		ch = (ch << 8) + *pdata++;	/* high word    */
+	for (cl = 0, i = 0; i < 4; i++)
+		cl = (cl << 8) + *pdata++;	/* low word */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *) dest) & ch) != ch
+		|| (*((vu_long *) (dest + 4)) & cl) != cl) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest) = ch;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA;
+	V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055;
+	V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0;
+	V_ULONG (dest + 4) = cl;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
+		   ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/tqm8260/tqm8260.c b/board/tqm8260/tqm8260.c
new file mode 100755
index 0000000..029863b
--- /dev/null
+++ b/board/tqm8260/tqm8260.c
@@ -0,0 +1,368 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 *ATMTXEN */
+	/* PA30 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTCA   */
+	/* PA29 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTSOC  */
+	/* PA28 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 *ATMRXEN */
+	/* PA27 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRSOC */
+	/* PA26 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRCA */
+	/* PA25 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   0,   0,   1,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   1,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   1,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   1,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   1,   0,   0   }, /* PC15 */
+	/* PC14 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+	/* PC9  */ {   0,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,   0,   1,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof (str));
+
+	puts ("Board: ");
+
+	if (!i || strncmp (str, "TQM82", 5)) {
+		puts ("### No HW ID - assuming TQM8260\n");
+		return (0);
+	}
+
+	puts (str);
+	putc ('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
+	orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	long size8, size9;
+#endif
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#if 0							/* Just for debugging */
+#define	prt_br_or(brX,orX) do {				\
+    ulong start =  memctl->memc_ ## brX & 0xFFFF8000;	\
+    ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF;	\
+    printf ("\n"					\
+    	    #brX " 0x%08x  " #orX " 0x%08x "		\
+	    "==> 0x%08lx ... 0x%08lx = %ld MB\n",	\
+	memctl->memc_ ## brX, memctl->memc_ ## orX,	\
+	start, start+sizem, (sizem+1)>>20);		\
+    } while (0)
+	prt_br_or (br0, or0);
+	prt_br_or (br1, or1);
+	prt_br_or (br2, or2);
+	prt_br_or (br3, or3);
+#endif
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+					  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
+					  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL - %ld MB, ", psize >> 20);
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
+						  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL - %ld MB, ", psize >> 20);
+	}
+
+	/* Local SDRAM setup:
+	 */
+#ifdef CFG_INIT_LOCAL_SDRAM
+	memctl->memc_lsrt = CFG_LSRT;
+	size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+	size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
+					  (uchar *) SDRAM_BASE2_PRELIM);
+
+	if (size8 < size9) {
+		lsize = size9;
+		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
+	} else {
+		lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+						  (uchar *) SDRAM_BASE2_PRELIM);
+		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
+	}
+
+#if 0
+	/* Set up BR2 so that the local SDRAM goes
+	 * right after the 60x SDRAM
+	 */
+	memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
+			(CFG_SDRAM_BASE + psize);
+#endif
+#endif /* CFG_INIT_LOCAL_SDRAM */
+#endif /* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/tqm8260/u-boot.lds b/board/tqm8260/u-boot.lds
new file mode 100755
index 0000000..05f29c6
--- /dev/null
+++ b/board/tqm8260/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/tqm834x/Makefile b/board/tqm834x/Makefile
new file mode 100755
index 0000000..3ecc7d0
--- /dev/null
+++ b/board/tqm834x/Makefile
@@ -0,0 +1,45 @@
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o pci.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/tqm834x/config.mk b/board/tqm834x/config.mk
new file mode 100755
index 0000000..f172c4e
--- /dev/null
+++ b/board/tqm834x/config.mk
@@ -0,0 +1,23 @@
+#
+# Copyright 2004 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE   =   0x80000000
diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c
new file mode 100755
index 0000000..5a23e6c
--- /dev/null
+++ b/board/tqm834x/pci.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <asm/mmu.h>
+#include <common.h>
+#include <pci.h>
+
+#ifdef CONFIG_PCI
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_tqm834x_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ 	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+		}
+	},
+	{}
+};
+#endif
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_tqm834x_config_table,
+#endif
+};
+
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
+ * per TQM834x design physical connections to external devices (PCI sockets)
+ * are routed only to the PCI1 we do not account for the second one - this code
+ * supports PCI1 module only. Should support for the PCI2 be required in the
+ * future it needs a separate pci_controller structure (above) and handling -
+ * please refer to other boards' implementation for dual PCI host controllers,
+ * for example board/Marvell/db64360/pci.c, pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *	immr;
+	volatile clk8349_t *	clk;
+	volatile law8349_t *	pci_law;
+	volatile pot8349_t *	pci_pot;
+	volatile pcictrl8349_t *	pci_ctrl;
+	volatile pciconf8349_t *	pci_conf;
+	u16 reg16;
+	u32 reg32;
+	struct	pci_controller * hose;
+
+	immr = (immap_t *)CFG_IMMRBAR;
+	clk = (clk8349_t *)&immr->clk;
+	pci_law = immr->sysconf.pcilaw;
+	pci_pot = immr->ios.pot;
+	pci_ctrl = immr->pci_ctrl;
+	pci_conf = immr->pci_conf;
+
+	hose = &pci1_hose;
+
+	/*
+	 * Configure PCI controller and PCI_CLK_OUTPUT
+	 */
+
+	/*
+	 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
+	 * line actually used for clocking all external PCI devices in TQM83xx.
+	 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
+	 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
+	 * are known to hang the board; this issue is under investigation
+	 * (13 oct 05)
+	 */
+	reg32 = OCCR_PCICOE1;
+#if 0
+	/* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
+	reg32 = 0xff000000;
+#endif
+	if (clk->spmr & SPMR_CKID) {
+		/* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
+		 * fields accordingly */
+		reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
+
+		reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
+			  | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
+			  | OCCR_PCICD6 | OCCR_PCICD7);
+	}
+
+	clk->occr = reg32;
+	udelay(2000);
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	pci_ctrl[0].gcr = 0;
+	udelay(2000);
+	pci_ctrl[0].gcr = 1;
+	udelay(2000);
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
+
+	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI1 mem space */
+	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
+
+	/* PCI1 IO space */
+	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	pci_ctrl[0].pitar1 = 0x0;
+	pci_ctrl[0].pibar1 = 0x0;
+	pci_ctrl[0].piebar1 = 0x0;
+	pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M;
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI1_MEM_BASE,
+		       CFG_PCI1_MEM_PHYS,
+		       CFG_PCI1_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI1_IO_BASE,
+		       CFG_PCI1_IO_PHYS,
+		       CFG_PCI1_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 2,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       CONFIG_PCI_SYS_MEM_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	hose->region_count = 3;
+
+	pci_setup_indirect(hose,
+			   (CFG_IMMRBAR+0x8300),
+			   (CFG_IMMRBAR+0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
+					&reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
+					reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
+					0xffff);
+	pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
+					0x80);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+#endif /* CONFIG_PCI */
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
new file mode 100755
index 0000000..dada673
--- /dev/null
+++ b/board/tqm834x/tqm834x.c
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc83xx.h>
+#include <asm/mpc8349_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <asm-ppc/mmu.h>
+#include <pci.h>
+
+#define IOSYNC			asm("eieio")
+#define ISYNC			asm("isync")
+#define SYNC			asm("sync")
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+#define DDR_MAX_SIZE_PER_CS	0x20000000
+
+#if defined(DDR_CASLAT_20)
+#define TIMING_CASLAT		TIMING_CFG1_CASLAT_20
+#define MODE_CASLAT		DDR_MODE_CASLAT_20
+#else
+#define TIMING_CASLAT		TIMING_CFG1_CASLAT_25
+#define MODE_CASLAT		DDR_MODE_CASLAT_25
+#endif
+
+#define INITIAL_CS_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
+				CSCONFIG_COL_BIT_9)
+
+/* Global variable used to store detected number of banks */
+int tqm834x_num_flash_banks;
+
+/* External definitions */
+ulong flash_get_size (ulong base, int banknum);
+extern flash_info_t flash_info[];
+extern long spd_sdram (void);
+
+/* Local functions */
+static int detect_num_flash_banks(void);
+static long int get_ddr_bank_size(short cs, volatile long *base);
+static void set_cs_bounds(short cs, long base, long size);
+static void set_cs_config(short cs, long config);
+static void set_ddr_config(void);
+
+/* Local variable */
+static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+
+/**************************************************************************
+ * Board initialzation after relocation to RAM. Used to detect the number
+ * of Flash banks on TQM834x.
+ */
+int board_early_init_r (void) {
+	/* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return 0;
+
+	/* detect the number of Flash banks */
+	return detect_num_flash_banks();
+}
+
+/**************************************************************************
+ * DRAM initalization and size detection
+ */
+long int initdram (int board_type)
+{
+	long bank_size;
+	long size;
+	int cs;
+
+	/* during size detection, set up the max DDRLAW size */
+	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
+	im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
+
+	/* set CS bounds to maximum size */
+	for(cs = 0; cs < 4; ++cs) {
+		set_cs_bounds(cs,
+			CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+			DDR_MAX_SIZE_PER_CS);
+
+		set_cs_config(cs, INITIAL_CS_CONFIG);
+	}
+
+	/* configure ddr controller */
+	set_ddr_config();
+
+	udelay(200);
+
+	/* enable DDR controller */
+	im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
+		SDRAM_CFG_SREN |
+		SDRAM_CFG_SDRAM_TYPE_DDR);
+	SYNC;
+
+	/* size detection */
+	debug("\n");
+	size = 0;
+	for(cs = 0; cs < 4; ++cs) {
+		debug("\nDetecting Bank%d\n", cs);
+
+		bank_size = get_ddr_bank_size(cs,
+			(volatile long*)(CFG_DDR_BASE + size));
+		size += bank_size;
+
+		debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
+
+		/* exit if less than one bank */
+		if(size < DDR_MAX_SIZE_PER_CS) break;
+	}
+
+	return size;
+}
+
+/**************************************************************************
+ * checkboard()
+ */
+int checkboard (void)
+{
+	puts("Board: TQM834x\n");
+
+#ifdef CONFIG_PCI
+	DECLARE_GLOBAL_DATA_PTR;
+	volatile immap_t * immr;
+	u32 w, f;
+
+	immr = (immap_t *)CFG_IMMRBAR;
+	if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
+		printf("PCI:   NOT in host mode..?!\n");
+		return 0;
+	}
+
+	/* get bus width */
+	w = 32;
+	if (immr->reset.rcwh & RCWH_PCI64)
+		w = 64;
+
+	/* get clock */
+	f = gd->pci_clk;
+
+	printf("PCI1:  %d bit, %d MHz\n", w, f / 1000000);
+#else
+	printf("PCI:   disabled\n");
+#endif
+	return 0;
+}
+
+
+/**************************************************************************
+ *
+ * Local functions
+ *
+ *************************************************************************/
+
+/**************************************************************************
+ * Detect the number of flash banks (1 or 2). Store it in
+ * a global variable tqm834x_num_flash_banks.
+ * Bank detection code based on the Monitor code.
+ */
+static int detect_num_flash_banks(void)
+{
+	typedef unsigned long FLASH_PORT_WIDTH;
+	typedef volatile unsigned long FLASH_PORT_WIDTHV;
+	FPWV *bank1_base;
+	FPWV *bank2_base;
+	FPW bank1_read;
+	FPW bank2_read;
+	ulong bank1_size;
+	ulong bank2_size;
+	ulong total_size;
+
+	tqm834x_num_flash_banks = 2;	/* assume two banks */
+
+	/* Get bank 1 and 2 information */
+	bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
+	debug("Bank1 size: %lu\n", bank1_size);
+	bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
+	debug("Bank2 size: %lu\n", bank2_size);
+	total_size = bank1_size + bank2_size;
+
+	if (bank2_size > 0) {
+		/* Seems like we've got bank 2, but maybe it's mirrored 1 */
+
+		/* Set the base addresses */
+		bank1_base = (FPWV *) (CFG_FLASH_BASE);
+		bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
+
+		/* Put bank 2 into CFI command mode and read */
+		bank2_base[0x55] = 0x00980098;
+		IOSYNC;
+		ISYNC;
+		bank2_read = bank2_base[0x10];
+
+		/* Read from bank 1 (it's in read mode) */
+		bank1_read = bank1_base[0x10];
+
+		/* Reset Flash */
+		bank1_base[0] = 0x00F000F0;
+		bank2_base[0] = 0x00F000F0;
+
+		if (bank2_read == bank1_read) {
+			/*
+			 * Looks like just one bank, but not sure yet. Let's
+			 * read from bank 2 in autosoelect mode.
+			 */
+			bank2_base[0x0555] = 0x00AA00AA;
+			bank2_base[0x02AA] = 0x00550055;
+			bank2_base[0x0555] = 0x00900090;
+			IOSYNC;
+			ISYNC;
+			bank2_read = bank2_base[0x10];
+
+			/* Read from bank 1 (it's in read mode) */
+			bank1_read = bank1_base[0x10];
+
+			/* Reset Flash */
+			bank1_base[0] = 0x00F000F0;
+			bank2_base[0] = 0x00F000F0;
+
+			if (bank2_read == bank1_read) {
+				/*
+				 * In both CFI command and autoselect modes,
+				 * we got the some data reading from Flash.
+				 * There is only one mirrored bank.
+				 */
+				tqm834x_num_flash_banks = 1;
+				total_size = bank1_size;
+			}
+		}
+	}
+
+	debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
+
+	/* set OR0 and BR0 */
+	im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
+		(-(total_size) & OR_GPCM_AM);
+	im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
+		(BR_MS_GPCM | BR_PS_32 | BR_V);
+
+	return (0);
+}
+
+/*************************************************************************
+ * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
+ */
+static long int get_ddr_bank_size(short cs, volatile long *base)
+{
+	/* This array lists all valid DDR SDRAM configurations, with
+	 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
+	 * The last entry has to to have size equal 0 and is igonred during
+	 * autodection. Bank sizes must be in increasing order of size
+	 */
+	struct {
+		long row;
+		long col;
+		long size;
+	} conf[] = {
+		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_8,	32 << 20},
+		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_9,	64 << 20},
+		{CSCONFIG_ROW_BIT_12,	CSCONFIG_COL_BIT_10,	128 << 20},
+		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_9,	128 << 20},
+		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_10,	256 << 20},
+		{CSCONFIG_ROW_BIT_13,	CSCONFIG_COL_BIT_11,	512 << 20},
+		{CSCONFIG_ROW_BIT_14,	CSCONFIG_COL_BIT_10,	512 << 20},
+		{CSCONFIG_ROW_BIT_14,	CSCONFIG_COL_BIT_11,	1024 << 20},
+		{0,			0,			0}
+	};
+
+	int i;
+	int detected;
+	long size;
+
+	detected = -1;
+	for(i = 0; conf[i].size != 0; ++i) {
+
+		/* set sdram bank configuration */
+		set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
+
+		debug("Getting RAM size...\n");
+		size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
+
+		if((size == conf[i].size) && (i == detected + 1))
+			detected = i;
+
+		debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
+			conf[i].row,
+			conf[i].col,
+			conf[i].size >> 20,
+			base,
+			size >> 20);
+	}
+
+	if(detected == -1){
+		/* disable empty cs */
+		debug("\nNo valid configurations for CS%d, disabling...\n", cs);
+		set_cs_config(cs, 0);
+		return 0;
+	}
+
+	debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
+			conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
+
+	/* configure cs ro detected params */
+	set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
+			conf[detected].col);
+
+	set_cs_bounds(cs, (long)base, conf[detected].size);
+
+	return(conf[detected].size);
+}
+
+/**************************************************************************
+ * Sets DDR bank CS bounds.
+ */
+static void set_cs_bounds(short cs, long base, long size)
+{
+	debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
+	if(size == 0){
+		im->ddr.csbnds[cs].csbnds = 0x00000000;
+	} else {
+		im->ddr.csbnds[cs].csbnds =
+			((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+			(((base + size - 1) >> CSBNDS_EA_SHIFT) &
+				CSBNDS_EA);
+	}
+	SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR banks CS configuration.
+ * config == 0x00000000 disables the CS.
+ */
+static void set_cs_config(short cs, long config)
+{
+	debug("Setting config %08x for cs %d\n", config, cs);
+	im->ddr.cs_config[cs] = config;
+	SYNC;
+}
+
+/**************************************************************************
+ * Sets DDR clocks, timings and configuration.
+ */
+static void set_ddr_config(void) {
+	/* clock control */
+	im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
+		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
+	SYNC;
+
+	/* timing configuration */
+	im->ddr.timing_cfg_1 =
+		(4 << TIMING_CFG1_PRETOACT_SHIFT) |
+		(7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
+		(4 << TIMING_CFG1_ACTTORW_SHIFT)  |
+		(5 << TIMING_CFG1_REFREC_SHIFT)   |
+		(3 << TIMING_CFG1_WRREC_SHIFT)    |
+		(3 << TIMING_CFG1_ACTTOACT_SHIFT) |
+		(1 << TIMING_CFG1_WRTORD_SHIFT)   |
+		(TIMING_CFG1_CASLAT & TIMING_CASLAT);
+
+	im->ddr.timing_cfg_2 =
+		TIMING_CFG2_CPO_DEF |
+		(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
+	SYNC;
+
+	/* don't enable DDR controller yet */
+	im->ddr.sdram_cfg =
+		SDRAM_CFG_SREN |
+		SDRAM_CFG_SDRAM_TYPE_DDR;
+	SYNC;
+
+	/* Set SDRAM mode */
+	im->ddr.sdram_mode =
+		((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
+			SDRAM_MODE_ESD_SHIFT) |
+		((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
+			SDRAM_MODE_SD_SHIFT) |
+		((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
+			MODE_CASLAT);
+	SYNC;
+
+	/* Set fast SDRAM refresh rate */
+	im->ddr.sdram_interval =
+		(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
+		(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
+	SYNC;
+}
diff --git a/board/tqm834x/u-boot.lds b/board/tqm834x/u-boot.lds
new file mode 100755
index 0000000..020cfa6
--- /dev/null
+++ b/board/tqm834x/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc83xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/tqm85xx/Makefile b/board/tqm85xx/Makefile
new file mode 100755
index 0000000..3933d46
--- /dev/null
+++ b/board/tqm85xx/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o sdram.o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/tqm85xx/config.mk b/board/tqm85xx/config.mk
new file mode 100755
index 0000000..52e84ad
--- /dev/null
+++ b/board/tqm85xx/config.mk
@@ -0,0 +1,29 @@
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# tqm85xx board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 256k
+#
+TEXT_BASE = 0xfffc0000
diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S
new file mode 100755
index 0000000..1f61038
--- /dev/null
+++ b/board/tqm85xx/init.S
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+	mflr	r1	;	\
+	bl	0f	;
+
+#define entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13
+
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)
+
+
+	/*
+	 * TLB 0, 1:	128M	Non-cacheable, guarded
+	 * 0xf8000000	128M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7+8:	512M	DDR, cache disabled (needed for memory test)
+	 * 0x00000000  512M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(1, 8, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
+
+	entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
+ * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
+ * 0xc000_0000	   0xdfff_ffff	   RapidIO		   512M
+ * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
+ * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
+ * 0xf800_0000	   0xf80f_ffff	   BCSR			   1M
+ * 0xfe00_0000	   0xffff_ffff	   FLASH (boot bank)	   32M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x05
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4
+	entry_end
diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c
new file mode 100755
index 0000000..9c1f087
--- /dev/null
+++ b/board/tqm85xx/sdram.c
@@ -0,0 +1,226 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <spd.h>
+
+struct sdram_conf_s {
+	unsigned long size;
+	unsigned long reg;
+};
+
+typedef struct sdram_conf_s sdram_conf_t;
+
+sdram_conf_t ddr_cs_conf[] = {
+	{(512 << 20), 0x80000202},	/* 512MB, 14x10(4)	*/
+	{(256 << 20), 0x80000102},	/* 256MB, 13x10(4)	*/
+	{(128 << 20), 0x80000101},	/* 128MB, 13x9(4)	*/
+	{(64  << 20), 0x80000001},	/* 64MB,  12x9(4)	*/
+};
+
+#define	N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
+
+int cas_latency(void);
+
+/*
+ * Autodetect onboard DDR SDRAM on 85xx platforms
+ *
+ * NOTE: Some of the hardcoded values are hardware dependant,
+ *       so this should be extended for other future boards
+ *       using this routine!
+ */
+long int sdram_setup(int casl)
+{
+	int i;
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+	unsigned long cfg_ddr_timing1;
+	unsigned long cfg_ddr_mode;
+
+	/*
+	 * Disable memory controller.
+	 */
+	ddr->cs0_config = 0;
+	ddr->sdram_cfg = 0;
+
+	switch (casl) {
+	case 20:
+		cfg_ddr_timing1 = 0x47405331 | (3 << 16);
+		cfg_ddr_mode = 0x40020002 | (2 << 4);
+		break;
+
+	case 25:
+		cfg_ddr_timing1 = 0x47405331 | (4 << 16);
+		cfg_ddr_mode = 0x40020002 | (6 << 4);
+		break;
+
+	case 30:
+	default:
+		cfg_ddr_timing1 = 0x47405331 | (5 << 16);
+		cfg_ddr_mode = 0x40020002 | (3 << 4);
+		break;
+	}
+
+	ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
+	ddr->cs0_config = ddr_cs_conf[0].reg;
+	ddr->timing_cfg_1 = cfg_ddr_timing1;
+	ddr->timing_cfg_2 = 0x00000800;		/* P9-45,may need tuning */
+	ddr->sdram_mode = cfg_ddr_mode;
+	ddr->sdram_interval = 0x05160100;	/* autocharge,no open page */
+	ddr->err_disable = 0x0000000D;
+
+	asm ("sync;isync;msync");
+	udelay(1000);
+
+	ddr->sdram_cfg = 0xc2000000;		/* unbuffered,no DYN_PWR */
+	asm ("sync; isync; msync");
+	udelay(1000);
+
+	for (i=0; i<N_DDR_CS_CONF; i++) {
+		ddr->cs0_config = ddr_cs_conf[i].reg;
+
+		if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
+			/*
+			 * OK, size detected -> all done
+			 */
+			return ddr_cs_conf[i].size;
+		}
+	}
+
+	return 0;				/* nothing found !		*/
+}
+
+void board_add_ram_info(int use_default)
+{
+	int casl;
+
+	if (use_default)
+		casl = CONFIG_DDR_DEFAULT_CL;
+	else
+		casl = cas_latency();
+
+	puts(" (CL=");
+	switch (casl) {
+	case 20:
+		puts("2)");
+		break;
+
+	case 25:
+		puts("2.5)");
+		break;
+
+	case 30:
+		puts("3)");
+		break;
+	}
+}
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+	int casl;
+
+#if defined(CONFIG_DDR_DLL)
+	/*
+	 * This DLL-Override only used on TQM8540 and TQM8560
+	 */
+	{
+		volatile immap_t *immap = (immap_t *) CFG_IMMR;
+		volatile ccsr_gur_t *gur= &immap->im_gur;
+		int i,x;
+
+		x = 10;
+
+		/*
+		 * Work around to stabilize DDR DLL
+		 */
+		gur->ddrdllcr = 0x81000000;
+		asm("sync;isync;msync");
+		udelay (200);
+		while (gur->ddrdllcr != 0x81000100) {
+			gur->devdisr = gur->devdisr | 0x00010000;
+			asm("sync;isync;msync");
+			for (i=0; i<x; i++)
+				;
+			gur->devdisr = gur->devdisr & 0xfff7ffff;
+			asm("sync;isync;msync");
+			x++;
+		}
+	}
+#endif
+
+	casl = cas_latency();
+	dram_size = sdram_setup(casl);
+	if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
+		/*
+		 * Try again with default CAS latency
+		 */
+		puts("Problem with CAS lantency");
+		board_add_ram_info(1);
+		puts(", using default CL!\n");
+		casl = CONFIG_DDR_DEFAULT_CL;
+		dram_size = sdram_setup(casl);
+		puts("       ");
+	}
+
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf ("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf ("SDRAM test passed.\n");
+	return 0;
+}
+#endif
diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c
new file mode 100755
index 0000000..13ea6f4
--- /dev/null
+++ b/board/tqm85xx/tqm85xx.c
@@ -0,0 +1,411 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <flash.h>
+
+extern flash_info_t flash_info[];	/* FLASH chips info */
+
+void local_bus_init (void);
+long int fixed_sdram (void);
+ulong flash_get_size (ulong base, int banknum);
+
+#ifdef CONFIG_CPM2
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   0,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   1,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+#endif /*  CONFIG_CPM2 */
+
+#define CASL_STRING1	"casl=xx"
+#define CASL_STRING2	"casl="
+
+static const int casl_table[] = { 20, 25, 30 };
+#define	N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
+
+int cas_latency(void)
+{
+	char *s = getenv("serial#");
+	int casl;
+	int val;
+	int i;
+
+	casl = CONFIG_DDR_DEFAULT_CL;
+
+	if (s != NULL) {
+		if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
+			    strlen(CASL_STRING2)) == 0) {
+			val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
+
+			for (i=0; i<N_CASL; ++i) {
+				if (val == casl_table[i]) {
+					return val;
+				}
+			}
+		}
+	}
+
+	return casl;
+}
+
+int checkboard (void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: %s", CONFIG_BOARDNAME);
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+#ifdef CONFIG_PCI
+	printf ("PCI1:  32 bit, %d MHz (compiled)\n",
+		CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf ("PCI1:  disabled\n");
+#endif
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	volatile immap_t    *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+
+	/*
+	 * Adjust flash start and offset to detected values
+	 */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/*
+	 * Check if boot FLASH isn't max size
+	 */
+	if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
+		memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
+		memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
+
+		/*
+		 * Re-check to get correct base address
+		 */
+		flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+	}
+
+	/*
+	 * Check if only one FLASH bank is available
+	 */
+	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
+		memctl->or1 = 0;
+		memctl->br1 = 0;
+
+		/*
+		 * Re-do flash protection upon new addresses
+		 */
+		flash_protect (FLAG_PROTECT_CLEAR,
+			       gd->bd->bi_flashstart, 0xffffffff,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+		/* Monitor protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_MONITOR_BASE, 0xffffffff,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+		/* Environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR,
+			       CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+
+		/* Redundant environment protection ON by default */
+		flash_protect (FLAG_PROTECT_SET,
+			       CFG_ENV_ADDR_REDUND,
+			       CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+	}
+
+	return 0;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void local_bus_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info (&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+		lbc->ltedr = 0xa4c80000;	/* DK: !!! */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);	/* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr ();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);	/* DLL Enabled */
+		udelay (200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+		asm ("sync;isync;msync");
+	}
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
+	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+				     PCI_ENET0_MEMADDR,
+				     PCI_COMMAND_MEMORY |
+				     PCI_COMMAND_MASTER}},
+	{}
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table:pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void pci_init_board (void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init (struct pci_controller *hose);
+
+	pci_mpc85xx_init (&hose);
+#endif /* CONFIG_PCI */
+}
diff --git a/board/tqm85xx/u-boot.lds b/board/tqm85xx/u-boot.lds
new file mode 100755
index 0000000..4cc825b
--- /dev/null
+++ b/board/tqm85xx/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o (.bootpg)
+    board/tqm85xx/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash		 : { *(.hash)		}
+  .dynsym	 : { *(.dynsym)		}
+  .dynstr	 : { *(.dynstr)		}
+  .rel.text	 : { *(.rel.text)		}
+  .rela.text	 : { *(.rela.text)	}
+  .rel.data	 : { *(.rel.data)		}
+  .rela.data	 : { *(.rela.data)	}
+  .rel.rodata	 : { *(.rel.rodata)	}
+  .rela.rodata	 : { *(.rela.rodata)	}
+  .rel.got	 : { *(.rel.got)		}
+  .rela.got	 : { *(.rela.got)		}
+  .rel.ctors	 : { *(.rel.ctors)	}
+  .rela.ctors	 : { *(.rela.ctors)	}
+  .rel.dtors	 : { *(.rel.dtors)	}
+  .rela.dtors	 : { *(.rela.dtors)	}
+  .rel.bss	 : { *(.rel.bss)		}
+  .rela.bss	 : { *(.rela.bss)		}
+  .rel.plt	 : { *(.rel.plt)		}
+  .rela.plt	 : { *(.rela.plt)		}
+  .init		 : { *(.init)	}
+  .plt : { *(.plt) }
+  .text	     :
+  {
+    cpu/mpc85xx/start.o (.text)
+    board/tqm85xx/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini	     : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data	   :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss	     :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/tqm8xx/Makefile b/board/tqm8xx/Makefile
new file mode 100755
index 0000000..2ff9b4d
--- /dev/null
+++ b/board/tqm8xx/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o load_sernum_ethaddr.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/tqm8xx/config.mk b/board/tqm8xx/config.mk
new file mode 100755
index 0000000..9d6080b
--- /dev/null
+++ b/board/tqm8xx/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# TQM8xxL boards
+#
+
+TEXT_BASE = 0x40000000
diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c
new file mode 100755
index 0000000..97bb5c3
--- /dev/null
+++ b/board/tqm8xx/flash.c
@@ -0,0 +1,829 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <environment.h>
+
+#include <asm/processor.h>
+
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
+#  define CFG_OR_TIMING_FLASH_AT_50MHZ	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+					 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+# endif
+#endif /* CONFIG_TQM8xxL/M, !TQM866M */
+
+#ifndef	CFG_ENV_ADDR
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+#ifdef	CFG_OR_TIMING_FLASH_AT_50MHZ
+	int scy, trlx, flash_or_timing, clk_diff;
+
+	DECLARE_GLOBAL_DATA_PTR;
+
+	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+		trlx = OR_TRLX;
+		scy *= 2;
+	} else
+		trlx = 0;
+
+		/* We assume that each 10MHz of bus clock require 1-clk SCY
+		 * adjustment.
+		 */
+	clk_diff = (gd->bus_clk / 1000000) - 50;
+
+		/* We need proper rounding here. This is what the "+5" and "-5"
+		 * are here for.
+		 */
+	if (clk_diff >= 0)
+		scy += (clk_diff + 5) / 10;
+	else
+		scy += (clk_diff - 5) / 10;
+
+		/* For bus frequencies above 50MHz, we want to use relaxed timing
+		 * (OR_TRLX).
+		 */
+	if (gd->bus_clk >= 50000000)
+		trlx = OR_TRLX;
+	else
+		trlx = 0;
+
+	if (trlx)
+		scy /= 2;
+
+	if (scy > 0xf)
+		scy = 0xf;
+	if (scy < 1)
+		scy = 1;
+
+	flash_or_timing = (scy << 4) | trlx |
+	                  (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+#endif
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+
+	debug  ("## Before remap: "
+		"BR0: 0x%08x    OR0: 0x%08x    "
+		"BR1: 0x%08x    OR1: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0,
+		memctl->memc_br1, memctl->memc_or1);
+
+	/* Remap FLASH according to real size */
+#ifndef	CFG_OR_TIMING_FLASH_AT_50MHZ
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+#else
+	memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
+#endif
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	debug ("Protect monitor: %08lx ... %08lx\n",
+		(ulong)CFG_MONITOR_BASE,
+		(ulong)CFG_MONITOR_BASE + monitor_flash_len - 1);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE + monitor_flash_len - 1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+# ifdef CFG_ENV_ADDR_REDUND
+	debug ("Protect primary   environment: %08lx ... %08lx\n",
+		(ulong)CFG_ENV_ADDR,
+		(ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
+# else
+	debug ("Protect environment: %08lx ... %08lx\n",
+		(ulong)CFG_ENV_ADDR,
+		(ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
+# endif
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
+		      &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_ADDR_REDUND
+	debug ("Protect redundand environment: %08lx ... %08lx\n",
+		(ulong)CFG_ENV_ADDR_REDUND,
+		(ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR_REDUND,
+		      CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+#ifndef	CFG_OR_TIMING_FLASH_AT_50MHZ
+		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+#else
+		memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000);
+#endif
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				    BR_MS_GPCM | BR_V;
+
+		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR+CFG_ENV_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+		memctl->memc_br1 = 0;		/* invalidate bank */
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+		flash_info[1].size = 0;
+
+		debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+	}
+
+	debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+#ifdef CONFIG_TQM8xxM	/* mirror bit flash */
+	case FLASH_AMLV128U:	printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV320U:	printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV320B:	printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
+				break;
+# else	/* ! TQM8xxM */
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+#endif	/* TQM8xxM */
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDL163B:	printf ("AM29DL163B (16 Mbit, bottom boot sect)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		debug ("Manufacturer: AMD\n");
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		debug ("Manufacturer: FUJITSU\n");
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		debug ("Manufacturer: *** unknown ***\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+#ifdef CONFIG_TQM8xxM	/* mirror bit flash */
+	case AMD_ID_MIRROR:
+		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
+			addr[14], addr[15]);
+		/* Special case for AMLV320MH/L */
+		if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
+		    (addr[15] & 0x00ff00ff) == 0x00000000) {
+			debug ("Chip: AMLV320MH/L\n");
+			info->flash_id += FLASH_AMLV320U;
+			info->sector_count = 64;
+			info->size = 0x00800000;	/* => 8 MB */
+			break;
+		}
+		switch(addr[14]) {
+		case AMD_ID_LV128U_2:
+			if (addr[15] != AMD_ID_LV128U_3) {
+				debug ("Chip: AMLV128U -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV128U\n");
+				info->flash_id += FLASH_AMLV128U;
+				info->sector_count = 256;
+				info->size = 0x02000000;
+			}
+			break;				/* => 32 MB	*/
+		case AMD_ID_LV640U_2:
+			if (addr[15] != AMD_ID_LV640U_3) {
+				debug ("Chip: AMLV640U -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV640U\n");
+				info->flash_id += FLASH_AMLV640U;
+				info->sector_count = 128;
+				info->size = 0x01000000;
+			}
+			break;				/* => 16 MB	*/
+		case AMD_ID_LV320B_2:
+			if (addr[15] != AMD_ID_LV320B_3) {
+				debug ("Chip: AMLV320B -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV320B\n");
+				info->flash_id += FLASH_AMLV320B;
+				info->sector_count = 71;
+				info->size = 0x00800000;
+			}
+			break;				/* =>  8 MB	*/
+		default:
+			debug ("Chip: *** unknown ***\n");
+			info->flash_id = FLASH_UNKNOWN;
+			break;
+		}
+		break;
+# else	/* ! TQM8xxM */
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;					/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;					/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;					/* => 2 MB	*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;					/* => 2 MB	*/
+
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;					/* => 8 MB	*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+		break;					/* => 8 MB	*/
+#endif	/* TQM8xxM */
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;					/* => 4 MB	*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;					/* => 4 MB	*/
+
+	case AMD_ID_DL163B:
+		info->flash_id += FLASH_AMDL163B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;					/* => 4 MB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	switch (value) {
+#ifdef CONFIG_TQM8xxM	/* mirror bit flash */
+	case AMD_ID_MIRROR:
+		switch (info->flash_id & FLASH_TYPEMASK) {
+			/* only known types here - no default */
+		case FLASH_AMLV128U:
+		case FLASH_AMLV640U:
+		case FLASH_AMLV320U:
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				base += 0x20000;
+			}
+			break;
+		case FLASH_AMLV320B:
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				/*
+				 * The first 8 sectors are 8 kB,
+				 * all the other ones  are 64 kB
+				 */
+				base += (i < 8)
+					?  2 * ( 8 << 10)
+					:  2 * (64 << 10);
+			}
+			break;
+		}
+		break;
+# else	/* ! TQM8xxM */
+	case AMD_ID_LV400B:
+	case AMD_ID_LV800B:
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+		break;
+	case AMD_ID_LV400T:
+	case AMD_ID_LV800T:
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+		break;
+	case AMD_ID_LV320B:
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			/*
+			 * The first 8 sectors are 8 kB,
+			 * all the other ones  are 64 kB
+			 */
+			base += (i < 8)
+				?  2 * ( 8 << 10)
+				:  2 * (64 << 10);
+		}
+		break;
+	case AMD_ID_LV320T:
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			/*
+			 * The last 8 sectors are 8 kB,
+			 * all the other ones  are 64 kB
+			 */
+			base += (i < (info->sector_count - 8))
+				?  2 * (64 << 10)
+				:  2 * ( 8 << 10);
+		}
+		break;
+#endif	/* TQM8xxM */
+	case AMD_ID_LV160B:
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+		break;
+	case AMD_ID_LV160T:
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+		break;
+	case AMD_ID_DL163B:
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			/*
+			 * The first 8 sectors are 8 kB,
+			 * all the other ones  are 64 kB
+			 */
+			base += (i < 8)
+				?  2 * ( 8 << 10)
+				:  2 * (64 << 10);
+		}
+		break;
+	default:
+		return (0);
+		break;
+	}
+
+#if 0
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+#endif
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/tqm8xx/load_sernum_ethaddr.c b/board/tqm8xx/load_sernum_ethaddr.c
new file mode 100755
index 0000000..143f368
--- /dev/null
+++ b/board/tqm8xx/load_sernum_ethaddr.c
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*-----------------------------------------------------------------------
+ * Process Hardware Information Block:
+ *
+ * If we boot on a system fresh from factory, check if the Hardware
+ * Information Block exists and save the information it contains.
+ *
+ * The TQM8xxL / TQM82xx Hardware Information Block is defined as
+ * follows:
+ * - located in first flash bank
+ * - starts at offset 0x0003FFC0
+ * - size 0x00000040
+ *
+ * Internal structure:
+ * - sequence of ASCII character strings
+ * - fields separated by a single space character (0x20)
+ * - last field terminated by NUL character (0x00)
+ * - remaining space filled with NUL characters (0x00)
+ *
+ * Fields in Hardware Information Block:
+ * 1) Module Type
+ * 2) Serial Number
+ * 3) First MAC Address
+ * 4) Number of additional MAC addresses
+ */
+
+void load_sernum_ethaddr (void)
+{
+	unsigned char *hwi;
+	unsigned char  serial [CFG_HWINFO_SIZE];
+	unsigned char  ethaddr[CFG_HWINFO_SIZE];
+	unsigned short ih, is, ie, part;
+
+	hwi = (unsigned char *)(CFG_FLASH_BASE + CFG_HWINFO_OFFSET);
+	ih = is = ie = 0;
+
+	if (*((unsigned long *)hwi) != (unsigned long)CFG_HWINFO_MAGIC) {
+		return;
+	}
+
+	part = 1;
+
+	/* copy serial # / MAC address */
+	while ((hwi[ih] != '\0') && (ih < CFG_HWINFO_SIZE)) {
+		if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */
+			return;
+		}
+		switch (part) {
+		default:		/* Copy serial # */
+			if (hwi[ih] == ' ') {
+				++part;
+			}
+			serial[is++] = hwi[ih];
+			break;
+		case 3:			/* Copy MAC address */
+			if (hwi[ih] == ' ') {
+				++part;
+				break;
+			}
+			ethaddr[ie++] = hwi[ih];
+			if ((ie % 3) == 2)
+				ethaddr[ie++] = ':';
+			break;
+		}
+		++ih;
+	}
+	serial[is]  = '\0';
+	if (ie && ethaddr[ie-1] == ':')
+		--ie;
+	ethaddr[ie] = '\0';
+
+	/* set serial# and ethaddr if not yet defined */
+	if (getenv("serial#") == NULL) {
+		setenv ((char *)"serial#", (char *)serial);
+	}
+
+	if (getenv("ethaddr") == NULL) {
+		setenv ((char *)"ethaddr", (char *)ethaddr);
+	}
+}
diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
new file mode 100755
index 0000000..017bdf9
--- /dev/null
+++ b/board/tqm8xx/tqm8xx.c
@@ -0,0 +1,501 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <mpc8xx.h>
+#ifdef CONFIG_PS2MULT
+#include <ps2mult.h>
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 0 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
+	0x1FF5FC47, /* last */
+	/*
+	 * SDRAM Initialization (offset 5 in UPMA RAM)
+	 *
+	 * This is no UPM entry point. The following definition uses
+	 * the remaining space to establish an initialization
+	 * sequence, which is executed by a RUN command.
+	 *
+	 */
+		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+	/*
+	 * Burst Read. (Offset 8 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
+	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Single Write. (Offset 18 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Burst Write. (Offset 20 in UPMA RAM)
+	 */
+	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
+	0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
+					    _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Refresh  (Offset 30 in UPMA RAM)
+	 */
+	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, /* last */
+				_NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	/*
+	 * Exception. (Offset 3c in UPMA RAM)
+	 */
+	0x7FFFFC07, /* last */
+		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test TQ ID string (TQM8xx...)
+ * If present, check for "L" type (no second DRAM bank),
+ * otherwise "L" type is assumed as default.
+ *
+ * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
+ */
+
+int checkboard (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	char *s = getenv ("serial#");
+
+	puts ("Board: ");
+
+	if (!s || strncmp (s, "TQM8", 4)) {
+		puts ("### No HW ID - assuming TQM8xxL\n");
+		return (0);
+	}
+
+	if ((*(s + 6) == 'L')) {	/* a TQM8xxL type */
+		gd->board_type = 'L';
+	}
+
+	if ((*(s + 6) == 'M')) {	/* a TQM8xxM type */
+		gd->board_type = 'M';
+	}
+
+	for (; *s; ++s) {
+		if (*s == ' ')
+			break;
+		putc (*s);
+	}
+	putc ('\n');
+
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9, size10;
+	long int size_b0 = 0;
+	long int size_b1 = 0;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	/*
+	 * The following value is used as an address (i.e. opcode) for
+	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
+	 * the port size is 32bit the SDRAM does NOT "see" the lower two
+	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
+	 * MICRON SDRAMs:
+	 * ->    0 00 010 0 010
+	 *       |  |   | |   +- Burst Length = 4
+	 *       |  |   | +----- Burst Type   = Sequential
+	 *       |  |   +------- CAS Latency  = 2
+	 *       |  +----------- Operating Mode = Standard
+	 *       +-------------- Write Burst Mode = Programmed Burst Length
+	 */
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
+	 * preliminary addresses - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or2 = CFG_OR2_PRELIM;
+	memctl->memc_br2 = CFG_BR2_PRELIM;
+
+#ifndef	CONFIG_CAN_DRIVER
+	if ((board_type != 'L') &&
+	    (board_type != 'M') ) {	/* "L" and "M" type boards have only one bank SDRAM */
+		memctl->memc_or3 = CFG_OR3_PRELIM;
+		memctl->memc_br3 = CFG_BR3_PRELIM;
+	}
+#endif							/* CONFIG_CAN_DRIVER */
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
+	udelay (1);
+	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
+	udelay (1);
+
+#ifndef	CONFIG_CAN_DRIVER
+	if ((board_type != 'L') &&
+	    (board_type != 'M') ) {	/* "L" and "M" type boards have only one bank SDRAM */
+		memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
+		udelay (1);
+		memctl->memc_mcr = 0x80006230;	/* SDRAM bank 1 - execute twice */
+		udelay (1);
+	}
+#endif							/* CONFIG_CAN_DRIVER */
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
+					   SDRAM_MAX_SIZE);
+	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
+
+	udelay(1000);
+
+#if defined(CFG_MAMR_10COL)
+	/*
+	 * try 10 column mode
+	 */
+	size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
+					     SDRAM_MAX_SIZE);
+	debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
+#else
+	size10 = 0;
+#endif /* CFG_MAMR_10COL */
+
+	if ((size8 < size10) && (size9 < size10)) {
+		size_b0 = size10;
+	} else if ((size8 < size9) && (size10 < size9)) {
+		size_b0 = size9;
+		memctl->memc_mamr = CFG_MAMR_9COL;
+		udelay (500);
+	} else {
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+	}
+	debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
+
+#ifndef	CONFIG_CAN_DRIVER
+	if ((board_type != 'L') &&
+	    (board_type != 'M') ) {	/* "L" and "M" type boards have only one bank SDRAM */
+		/*
+		 * Check Bank 1 Memory Size
+		 * use current column settings
+		 * [9 column SDRAM may also be used in 8 column mode,
+		 *  but then only half the real size will be used.]
+		 */
+		size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
+				     SDRAM_MAX_SIZE);
+		debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
+	} else {
+		size_b1 = 0;
+	}
+#endif	/* CONFIG_CAN_DRIVER */
+
+	udelay (1000);
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping: map bigger bank first
+	 */
+	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
+
+		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b0 > 0) {
+			/*
+			 * Position Bank 0 immediately above Bank 1
+			 */
+			memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+			memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					   + size_b1;
+		} else {
+			unsigned long reg;
+
+			/*
+			 * No bank 0
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br2 = 0;
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+
+	} else {					/* SDRAM Bank 0 is bigger - map first   */
+
+		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_br2 =
+				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+		if (size_b1 > 0) {
+			/*
+			 * Position Bank 1 immediately above Bank 0
+			 */
+			memctl->memc_or3 =
+					((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+			memctl->memc_br3 =
+					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					+ size_b0;
+		} else {
+			unsigned long reg;
+
+#ifndef	CONFIG_CAN_DRIVER
+			/*
+			 * No bank 1
+			 *
+			 * invalidate bank
+			 */
+			memctl->memc_br3 = 0;
+#endif							/* CONFIG_CAN_DRIVER */
+
+			/* adjust refresh rate depending on SDRAM type, one bank */
+			reg = memctl->memc_mptpr;
+			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			memctl->memc_mptpr = reg;
+		}
+	}
+
+	udelay (10000);
+
+#ifdef	CONFIG_CAN_DRIVER
+	/* Initialize OR3 / BR3 */
+	memctl->memc_or3 = CFG_OR3_CAN;
+	memctl->memc_br3 = CFG_BR3_CAN;
+
+	/* Initialize MBMR */
+	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
+
+	/* Initialize UPMB for CAN: single read */
+	memctl->memc_mdr = 0xFFFFC004;
+	memctl->memc_mcr = 0x0100 | UPMB;
+
+	memctl->memc_mdr = 0x0FFFD004;
+	memctl->memc_mcr = 0x0101 | UPMB;
+
+	memctl->memc_mdr = 0x0FFFC000;
+	memctl->memc_mcr = 0x0102 | UPMB;
+
+	memctl->memc_mdr = 0x3FFFC004;
+	memctl->memc_mcr = 0x0103 | UPMB;
+
+	memctl->memc_mdr = 0xFFFFDC05;
+	memctl->memc_mcr = 0x0104 | UPMB;
+
+	/* Initialize UPMB for CAN: single write */
+	memctl->memc_mdr = 0xFFFCC004;
+	memctl->memc_mcr = 0x0118 | UPMB;
+
+	memctl->memc_mdr = 0xCFFCD004;
+	memctl->memc_mcr = 0x0119 | UPMB;
+
+	memctl->memc_mdr = 0x0FFCC000;
+	memctl->memc_mcr = 0x011A | UPMB;
+
+	memctl->memc_mdr = 0x7FFCC004;
+	memctl->memc_mcr = 0x011B | UPMB;
+
+	memctl->memc_mdr = 0xFFFDCC05;
+	memctl->memc_mcr = 0x011C | UPMB;
+#endif							/* CONFIG_CAN_DRIVER */
+
+#ifdef	CONFIG_ISP1362_USB
+	/* Initialize OR5 / BR5 */
+	memctl->memc_or5 = CFG_OR5_ISP1362;
+	memctl->memc_br5 = CFG_BR5_ISP1362;
+#endif							/* CONFIG_ISP1362_USB */
+
+
+	return (size_b0 + size_b1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_PS2MULT
+
+#ifdef CONFIG_HMI10
+#define BASE_BAUD ( 1843200 / 16 )
+struct serial_state rs_table[] = {
+	{ BASE_BAUD, 4,  (void*)0xec140000 },
+	{ BASE_BAUD, 2,  (void*)0xec150000 },
+	{ BASE_BAUD, 6,  (void*)0xec160000 },
+	{ BASE_BAUD, 10, (void*)0xec170000 },
+};
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+	ps2mult_early_init();
+	return (0);
+}
+#endif
+#endif /* CONFIG_HMI10 */
+
+#endif /* CONFIG_PS2MULT */
+
+/* ---------------------------------------------------------------------------- */
+/* HMI10 specific stuff								*/
+/* ---------------------------------------------------------------------------- */
+#ifdef CONFIG_HMI10
+
+int misc_init_r (void)
+{
+# ifdef CONFIG_IDE_LED
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	/* Configure PA15 as output port */
+	immap->im_ioport.iop_padir |= 0x0001;
+	immap->im_ioport.iop_paodr |= 0x0001;
+	immap->im_ioport.iop_papar &= ~0x0001;
+	immap->im_ioport.iop_padat &= ~0x0001;	/* turn it off */
+# endif
+	return (0);
+}
+
+# ifdef CONFIG_IDE_LED
+void ide_led (uchar led, uchar status)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	/* We have one led for both pcmcia slots */
+	if (status) {				/* led on */
+		immap->im_ioport.iop_padat |= 0x0001;
+	} else {
+		immap->im_ioport.iop_padat &= ~0x0001;
+	}
+}
+# endif
+#endif	/* CONFIG_HMI10 */
+
+/* ---------------------------------------------------------------------------- */
+/* NSCU specific stuff								*/
+/* ---------------------------------------------------------------------------- */
+#ifdef CONFIG_NSCU
+
+int misc_init_r (void)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	/* wake up ethernet module */
+	immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin	*/
+	immr->im_ioport.iop_pcdir |=  0x0004; /* output		*/
+	immr->im_ioport.iop_pcso  &= ~0x0004; /* for clarity	*/
+	immr->im_ioport.iop_pcdat |=  0x0004; /* enable		*/
+
+	return (0);
+}
+#endif	/* CONFIG_NSCU */
+
+/* ------------------------------------------------------------------------- */
diff --git a/board/tqm8xx/u-boot.lds b/board/tqm8xx/u-boot.lds
new file mode 100755
index 0000000..d526d1d
--- /dev/null
+++ b/board/tqm8xx/u-boot.lds
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/tqm8xx/u-boot.lds.debug b/board/tqm8xx/u-boot.lds.debug
new file mode 100755
index 0000000..ddd4678
--- /dev/null
+++ b/board/tqm8xx/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/trab/Makefile b/board/trab/Makefile
new file mode 100755
index 0000000..ced9bc5
--- /dev/null
+++ b/board/trab/Makefile
@@ -0,0 +1,65 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o
+SOBJS	:= lowlevel_init.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0xc100000
+
+#########################################################################
+
+all:	$(LIB) trab_fkt.srec trab_fkt.bin
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+trab_fkt.srec:	trab_fkt.o rs485.o tsc2000.o $(LIB)
+	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ $(LIB) \
+		-L../../examples -lstubs \
+		-L../../lib_generic -lgeneric \
+		-L$(gcclibdir) -lgcc
+	$(OBJCOPY) -O srec $(<:.o=) $@
+
+trab_fkt.bin:	trab_fkt.srec
+	$(OBJCOPY) -O binary $< $@ 2>/dev/null
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/trab/Pt1000_temp_data.h b/board/trab/Pt1000_temp_data.h
new file mode 100755
index 0000000..17e9ed7
--- /dev/null
+++ b/board/trab/Pt1000_temp_data.h
@@ -0,0 +1,71 @@
+/*
+ * Data file for tsc2000 driver.
+ * Copyright (C) 2002, 2003 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ */
+
+#ifndef _PT1000_TEMP_DATA_H
+#define _PT1000_TEMP_DATA_H
+
+long Pt1000_temp_table[][2] = {
+	/* For quick range checking the largest element
+	 * is placed at index 0.
+	 * U, nV    T, C*100
+	 */
+	{ 44000000 , 12165 },
+	{ -10000000 , -2644 },
+	{ -9000000 , -2381 },
+	{ -8000000 , -2118 },
+	{ -7000000 , -1855 },
+	{ -6000000 , -1591 },
+	{ -5000000 , -1327 },
+	{ -4000000 , -1063 },
+	{ -3000000 , -798 },
+	{ -2000000 , -532 },
+	{ -1000000 , -266 },
+	{ 0 , 000 },
+	{ 1000000 , 267 },
+	{ 2000000 , 534 },
+	{ 3000000 , 802 },
+	{ 4000000 , 1070 },
+	{ 5000000 , 1338 },
+	{ 6000000 , 1607 },
+	{ 7000000 , 1876 },
+	{ 8000000 , 2146 },
+	{ 9000000 , 2416 },
+	{ 10000000 , 2687 },
+	{ 11000000 , 2958 },
+	{ 12000000 , 3230 },
+	{ 13000000 , 3502 },
+	{ 14000000 , 3774 },
+	{ 15000000 , 4047 },
+	{ 16000000 , 4321 },
+	{ 17000000 , 4595 },
+	{ 18000000 , 4869 },
+	{ 19000000 , 5144 },
+	{ 20000000 , 5419 },
+	{ 21000000 , 5694 },
+	{ 22000000 , 5971 },
+	{ 23000000 , 6247 },
+	{ 24000000 , 6524 },
+	{ 25000000 , 6802 },
+	{ 26000000 , 7080 },
+	{ 27000000 , 7358 },
+	{ 28000000 , 7637 },
+	{ 29000000 , 7916 },
+	{ 30000000 , 8196 },
+	{ 31000000 , 8476 },
+	{ 32000000 , 8757 },
+	{ 33000000 , 9039 },
+	{ 34000000 , 9320 },
+	{ 35000000 , 9602 },
+	{ 36000000 , 9885 },
+	{ 37000000 , 10168 },
+	{ 38000000 , 10452 },
+	{ 39000000 , 10736 },
+	{ 40000000 , 11021 },
+	{ 41000000 , 11306 },
+	{ 42000000 , 11592 },
+	{ 43000000 , 11879 },
+	{ 44000000 , 12165 },
+};
+#endif /* _PT1000_TEMP_DATA_H */
diff --git a/board/trab/README.kbd b/board/trab/README.kbd
new file mode 100755
index 0000000..3db00bc
--- /dev/null
+++ b/board/trab/README.kbd
@@ -0,0 +1,44 @@
+
+The TRAB keyboard implementation is similar to that for LWMON and
+R360MPI boards. The only difference concerns key naming. There are 4
+keys on TRAB: 1, 2, 3, 4.
+
+1) The "kbd" command provides information about the current state of
+   the keys. For example,
+
+	TRAB # kbd
+	Keys: 1 0 1 0
+
+   means that keys 1 and 3 are pressed. The keyboard status is also
+   stored in the "keybd" environment variable. In this example we get
+
+	keybd=1010
+
+2) The "preboot" variable is set according to current environment
+   settings and keys pressed. This is an example:
+
+	TRAB # setenv magic_keys XY
+	TRAB # setenv key_magicX 12
+	TRAB # setenv key_cmdX echo ## Keys 1 + 2 pressed ##\;echo
+	TRAB # setenv key_magicY 13
+	TRAB # setenv key_cmdY echo ## Keys 1 + 3 pressed ##\;echo
+
+   Here "magic_keys=XY" means that the "key_magicX" and "key_magicY"
+   variables will be checked for a match. Each variable "key_magic*"
+   defines a set of keys. In the our example, if keys 1 and 3 are
+   pressed during reset, then "key_magicY" matches, so the "preboot"
+   variable will be set to the contents of "key_cmdY":
+
+	preboot=echo ## Keys 1 + 3 pressed ##;echo
+
+3) The TRAB board has optional modem support. When a certain key
+   combination is pressed on the keyboard at power-on, the firmware
+   performs the necessary initialization of the modem and allows for
+   dial-in. The key combination is specified in the
+   "include/configs/trab.h" file. For example:
+
+	#define        CONFIG_MODEM_KEY_MAGIC  "23"
+
+   means that modem will be initialized if and only if both keys 2, 3
+   are pressed. Note that the format of this string is similar to the
+   format of "key_magic*" environment variables described above.
diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c
new file mode 100755
index 0000000..056e562
--- /dev/null
+++ b/board/trab/auto_update.c
@@ -0,0 +1,656 @@
+/*
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering, gj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <image.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+
+#ifdef CFG_HUSH_PARSER
+#include <hush.h>
+#endif
+
+#ifdef CONFIG_AUTO_UPDATE
+
+#ifndef CONFIG_USB_OHCI
+#error "must define CONFIG_USB_OHCI"
+#endif
+
+#ifndef CONFIG_USB_STORAGE
+#error "must define CONFIG_USB_STORAGE"
+#endif
+
+#ifndef CFG_HUSH_PARSER
+#error "must define CFG_HUSH_PARSER"
+#endif
+
+#if !(CONFIG_COMMANDS & CFG_CMD_FAT)
+#error "must define CFG_CMD_FAT"
+#endif
+
+/*
+ * Check whether a USB memory stick is plugged in.
+ * If one is found:
+ *	1) if prepare.img ist found load it into memory. If it is
+ *		valid then run it.
+ *	2) if preinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ *	3) if firmware.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	4) if kernel.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	5) if app.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	6) if disk.img is found load it into memory. If it is valid,
+ *		burn it into FLASH and update the EEPROM.
+ *	7) if postinst.img is found load it into memory. If it is
+ *		valid then run it. Update the EEPROM.
+ */
+
+#undef AU_DEBUG
+
+#undef debug
+#ifdef	AU_DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#else
+#define debug(fmt,args...)
+#endif	/* AU_DEBUG */
+
+/* possible names of files on the USB stick. */
+#define AU_PREPARE	"prepare.img"
+#define AU_PREINST	"preinst.img"
+#define AU_FIRMWARE	"firmware.img"
+#define AU_KERNEL	"kernel.img"
+#define AU_APP		"app.img"
+#define AU_DISK		"disk.img"
+#define AU_POSTINST	"postinst.img"
+
+struct flash_layout
+{
+	long start;
+	long end;
+};
+
+/* layout of the FLASH. ST = start address, ND = end address. */
+#ifndef CONFIG_FLASH_8MB			/* 16 MB Flash, 32 MB RAM */
+#define AU_FL_FIRMWARE_ST	0x00000000
+#define AU_FL_FIRMWARE_ND	0x0009FFFF
+#define AU_FL_VFD_ST		0x000A0000
+#define AU_FL_VFD_ND		0x000BFFFF
+#define AU_FL_KERNEL_ST		0x000C0000
+#define AU_FL_KERNEL_ND		0x001BFFFF
+#define AU_FL_APP_ST		0x001C0000
+#define AU_FL_APP_ND		0x005BFFFF
+#define AU_FL_DISK_ST		0x005C0000
+#define AU_FL_DISK_ND		0x00FFFFFF
+#else						/*  8 MB Flash, 32 MB RAM */
+#define AU_FL_FIRMWARE_ST	0x00000000
+#define AU_FL_FIRMWARE_ND	0x0005FFFF
+#define AU_FL_KERNEL_ST		0x00060000
+#define AU_FL_KERNEL_ND		0x0013FFFF
+#define AU_FL_APP_ST		0x00140000
+#define AU_FL_APP_ND		0x0067FFFF
+#define AU_FL_DISK_ST		0x00680000
+#define AU_FL_DISK_ND		0x007DFFFF
+#define AU_FL_VFD_ST		0x007E0000
+#define AU_FL_VFD_ND		0x007FFFFF
+#endif	/* CONFIG_FLASH_8MB */
+
+/* a structure with the offsets to values in the EEPROM */
+struct eeprom_layout
+{
+	int time;
+	int size;
+	int dcrc;
+};
+
+/* layout of the EEPROM - offset from the start. All entries are 32 bit. */
+#define AU_EEPROM_TIME_PREINST	64
+#define AU_EEPROM_SIZE_PREINST	68
+#define AU_EEPROM_DCRC_PREINST	72
+#define AU_EEPROM_TIME_FIRMWARE	76
+#define AU_EEPROM_SIZE_FIRMWARE	80
+#define AU_EEPROM_DCRC_FIRMWARE	84
+#define AU_EEPROM_TIME_KERNEL	88
+#define AU_EEPROM_SIZE_KERNEL	92
+#define AU_EEPROM_DCRC_KERNEL	96
+#define AU_EEPROM_TIME_APP	100
+#define AU_EEPROM_SIZE_APP	104
+#define AU_EEPROM_DCRC_APP	108
+#define AU_EEPROM_TIME_DISK	112
+#define AU_EEPROM_SIZE_DISK	116
+#define AU_EEPROM_DCRC_DISK	120
+#define AU_EEPROM_TIME_POSTINST 124
+#define AU_EEPROM_SIZE_POSTINST 128
+#define AU_EEPROM_DCRC_POSTINST 132
+
+static int au_usb_stor_curr_dev; /* current device */
+
+/* index of each file in the following arrays */
+#define IDX_PREPARE	0
+#define IDX_PREINST	1
+#define IDX_FIRMWARE	2
+#define IDX_KERNEL	3
+#define IDX_APP		4
+#define IDX_DISK	5
+#define IDX_POSTINST	6
+/* max. number of files which could interest us */
+#define AU_MAXFILES 7
+/* pointers to file names */
+char *aufile[AU_MAXFILES];
+/* sizes of flash areas for each file */
+long ausize[AU_MAXFILES];
+/* offsets into the EEEPROM */
+struct eeprom_layout auee_off[AU_MAXFILES] = { \
+	{0}, \
+	{AU_EEPROM_TIME_PREINST, AU_EEPROM_SIZE_PREINST, AU_EEPROM_DCRC_PREINST,}, \
+	{AU_EEPROM_TIME_FIRMWARE, AU_EEPROM_SIZE_FIRMWARE, AU_EEPROM_DCRC_FIRMWARE,}, \
+	{AU_EEPROM_TIME_KERNEL, AU_EEPROM_SIZE_KERNEL, AU_EEPROM_DCRC_KERNEL,}, \
+	{AU_EEPROM_TIME_APP, AU_EEPROM_SIZE_APP, AU_EEPROM_DCRC_APP,}, \
+	{AU_EEPROM_TIME_DISK, AU_EEPROM_SIZE_DISK, AU_EEPROM_DCRC_DISK,}, \
+	{AU_EEPROM_TIME_POSTINST, AU_EEPROM_SIZE_POSTINST, AU_EEPROM_DCRC_POSTINST,} \
+	};
+/* array of flash areas start and end addresses */
+struct flash_layout aufl_layout[AU_MAXFILES - 3] = { \
+	{AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND,}, \
+	{AU_FL_KERNEL_ST, AU_FL_KERNEL_ND,}, \
+	{AU_FL_APP_ST, AU_FL_APP_ND,}, \
+	{AU_FL_DISK_ST, AU_FL_DISK_ND,}, \
+};
+/* convert the index into aufile[] to an index into aufl_layout[] */
+#define FIDX_TO_LIDX(idx) ((idx) - 2)
+
+/* where to load files into memory */
+#define LOAD_ADDR ((unsigned char *)0x0C100000)
+/* the app is the largest image */
+#define MAX_LOADSZ ausize[IDX_APP]
+
+/* externals */
+extern int fat_register_device(block_dev_desc_t *, int);
+extern int file_fat_detectfs(void);
+extern long file_fat_read(const char *, void *, unsigned long);
+extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
+extern int i2c_write (uchar, uint, int , uchar* , int);
+#ifdef CONFIG_VFD
+extern int trab_vfd (ulong);
+extern int transfer_pic(unsigned char, unsigned char *, int, int);
+#endif
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (char *, ulong, ulong);
+/* change char* to void* to shutup the compiler */
+extern int i2c_write_multiple (uchar, uint, int, void *, int);
+extern int i2c_read_multiple (uchar, uint, int, void *, int);
+extern block_dev_desc_t *get_dev (char*, int);
+extern int u_boot_hush_start(void);
+
+int
+au_check_cksum_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size)))
+	{
+		printf ("Image %s bad total SIZE\n", aufile[idx]);
+		return -1;
+	}
+	/* check the data CRC */
+	checksum = ntohl(hdr->ih_dcrc);
+
+	if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size))
+		!= checksum)
+	{
+		printf ("Image %s bad data checksum\n", aufile[idx]);
+		return -1;
+	}
+	return 0;
+}
+
+int
+au_check_header_valid(int idx, long nbytes)
+{
+	image_header_t *hdr;
+	unsigned long checksum;
+	unsigned char buf[4];
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* check the easy ones first */
+#undef CHECK_VALID_DEBUG
+#ifdef CHECK_VALID_DEBUG
+	printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC);
+	printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_ARM);
+	printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes);
+	printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL);
+#endif
+	if (nbytes < sizeof(*hdr))
+	{
+		printf ("Image %s bad header SIZE\n", aufile[idx]);
+		return -1;
+	}
+	if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_ARM)
+	{
+		printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
+		return -1;
+	}
+	/* check the hdr CRC */
+	checksum = ntohl(hdr->ih_hcrc);
+	hdr->ih_hcrc = 0;
+
+	if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) {
+		printf ("Image %s bad header checksum\n", aufile[idx]);
+		return -1;
+	}
+	hdr->ih_hcrc = htonl(checksum);
+	/* check the type - could do this all in one gigantic if() */
+	if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_DISK) && (hdr->ih_type != IH_TYPE_FILESYSTEM)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK)
+	    && (hdr->ih_type != IH_TYPE_FILESYSTEM)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_PREPARE || idx == IDX_PREINST || idx == IDX_POSTINST)
+		&& (hdr->ih_type != IH_TYPE_SCRIPT))
+	{
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	/* special case for prepare.img */
+	if (idx == IDX_PREPARE)
+		return 0;
+	/* recycle checksum */
+	checksum = ntohl(hdr->ih_size);
+	/* for kernel and app the image header must also fit into flash */
+	if ((idx != IDX_DISK) && (idx != IDX_FIRMWARE))
+		checksum += sizeof(*hdr);
+	/* check the size does not exceed space in flash. HUSH scripts */
+	/* all have ausize[] set to 0 */
+	if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
+		printf ("Image %s is bigger than FLASH\n", aufile[idx]);
+		return -1;
+	}
+	/* check the time stamp from the EEPROM */
+	/* read it in */
+	i2c_read_multiple(0x54, auee_off[idx].time, 1, buf, sizeof(buf));
+#ifdef CHECK_VALID_DEBUG
+	printf ("buf[0] %#x buf[1] %#x buf[2] %#x buf[3] %#x "
+		"as int %#x time %#x\n",
+		buf[0], buf[1], buf[2], buf[3],
+		*((unsigned int *)buf), ntohl(hdr->ih_time));
+#endif
+	/* check it */
+	if (*((unsigned int *)buf) >= ntohl(hdr->ih_time)) {
+		printf ("Image %s is too old\n", aufile[idx]);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* power control defines */
+#define CPLD_VFD_BK ((volatile char *)0x04038002)
+#define POWER_OFF (1 << 1)
+
+int
+au_do_update(int idx, long sz)
+{
+	image_header_t *hdr;
+	char *addr;
+	long start, end;
+	int off, rc;
+	uint nbytes;
+
+	hdr = (image_header_t *)LOAD_ADDR;
+
+	/* disable the power switch */
+	*CPLD_VFD_BK |= POWER_OFF;
+
+	/* execute a script */
+	if (hdr->ih_type == IH_TYPE_SCRIPT) {
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+		/* stick a NULL at the end of the script, otherwise */
+		/* parse_string_outer() runs off the end. */
+		addr[ntohl(hdr->ih_size)] = 0;
+		addr += 8;
+		parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
+		return 0;
+	}
+
+	start = aufl_layout[FIDX_TO_LIDX(idx)].start;
+	end = aufl_layout[FIDX_TO_LIDX(idx)].end;
+
+	/* unprotect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE) {
+#undef AU_UPDATE_TEST
+#ifdef AU_UPDATE_TEST
+		/* erase it where Linux goes */
+		start = aufl_layout[1].start;
+		end = aufl_layout[1].end;
+#endif
+		flash_sect_protect(0, start, end);
+	}
+
+	/*
+	 * erase the address range.
+	 */
+	debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+	flash_sect_erase(start, end);
+	wait_ms(100);
+	/* strip the header - except for the kernel and ramdisk */
+	if (hdr->ih_type == IH_TYPE_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK) {
+		addr = (char *)hdr;
+		off = sizeof(*hdr);
+		nbytes = sizeof(*hdr) + ntohl(hdr->ih_size);
+	} else {
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+#ifdef AU_UPDATE_TEST
+		/* copy it to where Linux goes */
+		if (idx == IDX_FIRMWARE)
+			start = aufl_layout[1].start;
+#endif
+		off = 0;
+		nbytes = ntohl(hdr->ih_size);
+	}
+
+	/* copy the data from RAM to FLASH */
+	debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
+	rc = flash_write(addr, start, nbytes);
+	if (rc != 0) {
+		printf("Flashing failed due to error %d\n", rc);
+		return -1;
+	}
+
+	/* check the dcrc of the copy */
+	if (crc32 (0, (char *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) {
+		printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]);
+		return -1;
+	}
+
+	/* protect the address range */
+	/* this assumes that ONLY the firmware is protected! */
+	if (idx == IDX_FIRMWARE)
+		flash_sect_protect(1, start, end);
+	return 0;
+}
+
+int
+au_update_eeprom(int idx)
+{
+	image_header_t *hdr;
+	int off;
+	uint32_t val;
+
+	/* special case for prepare.img */
+	if (idx == IDX_PREPARE) {
+		/* enable the power switch */
+		*CPLD_VFD_BK &= ~POWER_OFF;
+		return 0;
+	}
+
+	hdr = (image_header_t *)LOAD_ADDR;
+	/* write the time field into EEPROM */
+	off = auee_off[idx].time;
+	val = ntohl(hdr->ih_time);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* write the size field into EEPROM */
+	off = auee_off[idx].size;
+	val = ntohl(hdr->ih_size);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* write the dcrc field into EEPROM */
+	off = auee_off[idx].dcrc;
+	val = ntohl(hdr->ih_dcrc);
+	i2c_write_multiple(0x54, off, 1, &val, sizeof(val));
+	/* enable the power switch */
+	*CPLD_VFD_BK &= ~POWER_OFF;
+	return 0;
+}
+
+/*
+ * this is called from board_init() after the hardware has been set up
+ * and is usable. That seems like a good time to do this.
+ * Right now the return value is ignored.
+ */
+int
+do_auto_update(void)
+{
+	block_dev_desc_t *stor_dev;
+	long sz;
+	int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc;
+	char *env;
+	long start, end;
+
+#undef ERASE_EEPROM
+#ifdef ERASE_EEPROM
+	int arr[18];
+	memset(arr, 0, sizeof(arr));
+	i2c_write_multiple(0x54, 64, 1, arr, sizeof(arr));
+#endif
+	au_usb_stor_curr_dev = -1;
+	/* start USB */
+	if (usb_stop() < 0) {
+		debug ("usb_stop failed\n");
+		return -1;
+	}
+	if (usb_init() < 0) {
+		debug ("usb_init failed\n");
+		return -1;
+	}
+	/*
+	 * check whether a storage device is attached (assume that it's
+	 * a USB memory stick, since nothing else should be attached).
+	 */
+	au_usb_stor_curr_dev = usb_stor_scan(0);
+	if (au_usb_stor_curr_dev == -1) {
+		debug ("No device found. Not initialized?\n");
+		return -1;
+	}
+	/* check whether it has a partition table */
+	stor_dev = get_dev("usb", 0);
+	if (stor_dev == NULL) {
+		debug ("uknown device type\n");
+		return -1;
+	}
+	if (fat_register_device(stor_dev, 1) != 0) {
+		debug ("Unable to use USB %d:%d for fatls\n",
+			au_usb_stor_curr_dev, 1);
+		return -1;
+	}
+	if (file_fat_detectfs() != 0) {
+		debug ("file_fat_detectfs failed\n");
+	}
+
+	/* initialize the array of file names */
+	memset(aufile, 0, sizeof(aufile));
+	aufile[IDX_PREPARE] = AU_PREPARE;
+	aufile[IDX_PREINST] = AU_PREINST;
+	aufile[IDX_FIRMWARE] = AU_FIRMWARE;
+	aufile[IDX_KERNEL] = AU_KERNEL;
+	aufile[IDX_APP] = AU_APP;
+	aufile[IDX_DISK] = AU_DISK;
+	aufile[IDX_POSTINST] = AU_POSTINST;
+	/* initialize the array of flash sizes */
+	memset(ausize, 0, sizeof(ausize));
+	ausize[IDX_FIRMWARE] = (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST;
+	ausize[IDX_KERNEL] = (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST;
+	ausize[IDX_APP] = (AU_FL_APP_ND + 1) - AU_FL_APP_ST;
+	ausize[IDX_DISK] = (AU_FL_DISK_ND + 1) - AU_FL_DISK_ST;
+	/*
+	 * now check whether start and end are defined using environment
+	 * variables.
+	 */
+	start = -1;
+	end = 0;
+	env = getenv("firmware_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("firmware_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_FIRMWARE] = (end + 1) - start;
+		aufl_layout[0].start = start;
+		aufl_layout[0].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("kernel_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("kernel_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_KERNEL] = (end + 1) - start;
+		aufl_layout[1].start = start;
+		aufl_layout[1].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("app_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("app_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_APP] = (end + 1) - start;
+		aufl_layout[2].start = start;
+		aufl_layout[2].end = end;
+	}
+	start = -1;
+	end = 0;
+	env = getenv("disk_st");
+	if (env != NULL)
+		start = simple_strtoul(env, NULL, 16);
+	env = getenv("disk_nd");
+	if (env != NULL)
+		end = simple_strtoul(env, NULL, 16);
+	if (start >= 0 && end && end > start) {
+		ausize[IDX_DISK] = (end + 1) - start;
+		aufl_layout[3].start = start;
+		aufl_layout[3].end = end;
+	}
+	/* make certain that HUSH is runnable */
+	u_boot_hush_start();
+	/* make sure that we see CTRL-C and save the old state */
+	old_ctrlc = disable_ctrlc(0);
+
+	bitmap_first = 0;
+	/* just loop thru all the possible files */
+	for (i = 0; i < AU_MAXFILES; i++) {
+		/* just read the header */
+		sz = file_fat_read(aufile[i], LOAD_ADDR, sizeof(image_header_t));
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, sizeof(image_header_t));
+		if (sz <= 0 || sz < sizeof(image_header_t)) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_header_valid(i, sz) < 0) {
+			debug ("%s header not valid\n", aufile[i]);
+			continue;
+		}
+		sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ);
+		debug ("read %s sz %ld hdr %d\n",
+			aufile[i], sz, sizeof(image_header_t));
+		if (sz <= 0 || sz <= sizeof(image_header_t)) {
+			debug ("%s not found\n", aufile[i]);
+			continue;
+		}
+		if (au_check_cksum_valid(i, sz) < 0) {
+			debug ("%s checksum not valid\n", aufile[i]);
+			continue;
+		}
+#ifdef CONFIG_VFD
+		/* now that we have a valid file we can display the */
+		/* bitmap. */
+		if (bitmap_first == 0) {
+			env = getenv("bitmap2");
+			if (env == NULL) {
+				trab_vfd(0);
+			} else {
+				/* not so simple - bitmap2 is supposed to */
+				/* contain the address of the bitmap */
+				env = (char *)simple_strtoul(env, NULL, 16);
+/* NOTE: these are taken from vfd_logo.h. If that file changes then */
+/* these defines MUST also be updated! These may be wrong for bitmap2. */
+#define VFD_LOGO_WIDTH 112
+#define VFD_LOGO_HEIGHT 72
+				/* must call transfer_pic directly */
+				transfer_pic(3, env, VFD_LOGO_HEIGHT, VFD_LOGO_WIDTH);
+			}
+			bitmap_first = 1;
+		}
+#endif
+		/* this is really not a good idea, but it's what the */
+		/* customer wants. */
+		cnt = 0;
+		got_ctrlc = 0;
+		do {
+			res = au_do_update(i, sz);
+			/* let the user break out of the loop */
+			if (ctrlc() || had_ctrlc()) {
+				clear_ctrlc();
+				if (res < 0)
+					got_ctrlc = 1;
+				break;
+			}
+			cnt++;
+#ifdef AU_TEST_ONLY
+		} while (res < 0 && cnt < 3);
+		if (cnt < 3)
+#else
+		} while (res < 0);
+#endif
+		/*
+		 * it doesn't make sense to update the EEPROM if the
+		 * update was interrupted by the user due to errors.
+		 */
+		if (got_ctrlc == 0)
+			au_update_eeprom(i);
+		else
+			/* enable the power switch */
+			*CPLD_VFD_BK &= ~POWER_OFF;
+	}
+	usb_stop();
+	/* restore the old state */
+	disable_ctrlc(old_ctrlc);
+	return 0;
+}
+#endif /* CONFIG_AUTO_UPDATE */
diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c
new file mode 100755
index 0000000..00eb385
--- /dev/null
+++ b/board/trab/cmd_trab.c
@@ -0,0 +1,895 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <common.h>
+#include <command.h>
+#include <s3c2400.h>
+#include <rtc.h>
+
+/*
+ * TRAB board specific commands. Especially commands for burn-in and function
+ * test.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+/* limits for valid range of VCC5V in mV  */
+#define VCC5V_MIN       4500
+#define VCC5V_MAX       5500
+
+/*
+ * Test strings for EEPROM test. Length of string 2 must not exceed length of
+ * string 1. Otherwise a buffer overrun could occur!
+ */
+#define EEPROM_TEST_STRING_1    "0987654321 :tset a si siht"
+#define EEPROM_TEST_STRING_2    "this is a test: 1234567890"
+
+/*
+ * min/max limits for valid contact temperature during burn in test (in
+ * degree Centigrade * 100)
+ */
+#define MIN_CONTACT_TEMP        -1000
+#define MAX_CONTACT_TEMP        +9000
+
+/* blinking frequency of status LED */
+#define LED_BLINK_FREQ          5
+
+/* delay time between burn in cycles in seconds */
+#ifndef BURN_IN_CYCLE_DELAY     /* if not defined in include/configs/trab.h */
+#define BURN_IN_CYCLE_DELAY     5
+#endif
+
+/* physical SRAM parameters */
+#define SRAM_ADDR       0x02000000 /* GCS1 */
+#define SRAM_SIZE       0x40000 /* 256 kByte */
+
+/* CPLD-Register for controlling TRAB hardware functions */
+#define CPLD_BUTTONS            ((volatile unsigned long *)0x04020000)
+#define CPLD_FILL_LEVEL         ((volatile unsigned long *)0x04008000)
+#define CPLD_ROTARY_SWITCH      ((volatile unsigned long *)0x04018000)
+#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
+
+/* I2C EEPROM device address */
+#define I2C_EEPROM_DEV_ADDR     0x54
+
+/* EEPROM address map */
+#define EE_ADDR_TEST                    192
+#define EE_ADDR_MAX_CYCLES              256
+#define EE_ADDR_STATUS                  258
+#define EE_ADDR_PASS_CYCLES             259
+#define EE_ADDR_FIRST_ERROR_CYCLE       261
+#define EE_ADDR_FIRST_ERROR_NUM         263
+#define EE_ADDR_FIRST_ERROR_NAME        264
+#define EE_ADDR_ACT_CYCLE               280
+
+/* Bit definitions for ADCCON */
+#define ADC_ENABLE_START     0x1
+#define ADC_READ_START       0x2
+#define ADC_STDBM            0x4
+#define ADC_INP_AIN0         (0x0 << 3)
+#define ADC_INP_AIN1         (0x1 << 3)
+#define ADC_INP_AIN2         (0x2 << 3)
+#define ADC_INP_AIN3         (0x3 << 3)
+#define ADC_INP_AIN4         (0x4 << 3)
+#define ADC_INP_AIN5         (0x5 << 3)
+#define ADC_INP_AIN6         (0x6 << 3)
+#define ADC_INP_AIN7         (0x7 << 3)
+#define ADC_PRSCEN           0x4000
+#define ADC_ECFLG            0x800
+
+/* misc */
+
+/* externals */
+extern int memory_post_tests (unsigned long start, unsigned long size);
+extern int i2c_write (uchar, uint, int , uchar* , int);
+extern int i2c_read (uchar, uint, int , uchar* , int);
+extern void tsc2000_reg_init (void);
+extern s32 tsc2000_contact_temp (void);
+extern void spi_init(void);
+
+/* function declarations */
+int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len);
+int i2c_read_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len);
+int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+/* helper functions */
+static void adc_init (void);
+static int adc_read (unsigned int channel);
+static int read_dip (void);
+static int read_vcc5v (void);
+static int test_dip (void);
+static int test_vcc5v (void);
+static int test_rotary_switch (void);
+static int test_sram (void);
+static int test_eeprom (void);
+static int test_contact_temp (void);
+static void led_set (unsigned int);
+static void led_blink (void);
+static void led_init (void);
+static void sdelay (unsigned long seconds); /* delay in seconds */
+static int dummy (void);
+static int read_max_cycles(void);
+static void test_function_table_init (void);
+static void global_vars_init (void);
+static int global_vars_write_to_eeprom (void);
+
+/* globals */
+u16 max_cycles;
+u8 status;
+u16 pass_cycles;
+u16 first_error_cycle;
+u8 first_error_num;
+unsigned char first_error_name[16];
+u16 act_cycle;
+
+typedef struct test_function_s {
+	unsigned char *name;
+	int (*pf)(void);
+} test_function_t;
+
+/* max number of Burn In Functions */
+#define BIF_MAX 6
+
+/* table with burn in functions */
+test_function_t test_function[BIF_MAX];
+
+
+int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i;
+	int cycle_status;
+
+	if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	led_init ();
+	global_vars_init ();
+	test_function_table_init ();
+	spi_init ();
+
+	if (global_vars_write_to_eeprom () != 0) {
+		printf ("%s: error writing global_vars to eeprom\n",
+			__FUNCTION__);
+		return (1);
+	}
+
+	if (read_max_cycles () != 0) {
+		printf ("%s: error reading max_cycles from eeprom\n",
+			__FUNCTION__);
+		return (1);
+	}
+
+	if (max_cycles == 0) {
+		printf ("%s: error, burn in max_cycles = 0\n", __FUNCTION__);
+		return (1);
+	}
+
+	status = 0;
+	for (act_cycle = 1; act_cycle <= max_cycles; act_cycle++) {
+
+		cycle_status = 0;
+
+		/*
+		 * avoid timestamp overflow problem after about 68 minutes of
+		 * udelay() time.
+		 */
+		reset_timer_masked ();
+		for (i = 0; i < BIF_MAX; i++) {
+
+			/* call test function */
+			if ((*test_function[i].pf)() != 0) {
+				printf ("error in %s test\n",
+					test_function[i].name);
+
+				/* is it the first error? */
+				if (status == 0) {
+					status = 1;
+					first_error_cycle = act_cycle;
+
+					/* do not use error_num 0 */
+					first_error_num = i+1;
+					strncpy (first_error_name,
+						 test_function[i].name,
+						 sizeof (first_error_name));
+					led_set (0);
+				}
+				cycle_status = 1;
+			}
+		}
+		/* were all tests of actual cycle OK? */
+		if (cycle_status == 0)
+			pass_cycles++;
+
+		/* set status LED if no error is occoured since yet */
+		if (status == 0)
+			led_set (1);
+
+		printf ("%s: cycle %d finished\n", __FUNCTION__, act_cycle);
+
+		/* pause between cycles */
+		sdelay (BURN_IN_CYCLE_DELAY);
+	}
+
+	if (global_vars_write_to_eeprom () != 0) {
+		led_set (0);
+		printf ("%s: error writing global_vars to eeprom\n",
+			__FUNCTION__);
+		status = 1;
+	}
+
+	if (status == 0) {
+		led_blink ();   /* endless loop!! */
+		return (0);
+	} else {
+		led_set (0);
+		return (1);
+	}
+}
+
+U_BOOT_CMD(
+	burn_in,	1,	1,	do_burn_in,
+	"burn_in - start burn-in test application on TRAB\n",
+	"\n"
+	"    -  start burn-in test application\n"
+	"       The burn-in test could took a while to finish!\n"
+	"       The content of the onboard EEPROM is modified!\n"
+);
+
+
+int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i, dip;
+
+	if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if ((dip = read_dip ()) == -1) {
+		return 1;
+	}
+
+	for (i = 0; i < 4; i++) {
+		if ((dip & (1 << i)) == 0)
+			printf("0");
+		else
+			printf("1");
+	}
+	printf("\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	dip,	1,	1,	do_dip,
+	"dip     - read dip switch on TRAB\n",
+	"\n"
+	"    - read state of dip switch (S1) on TRAB board\n"
+	"      read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\"\n"
+);
+
+
+int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int vcc5v;
+
+	if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if ((vcc5v = read_vcc5v ()) == -1) {
+		return (1);
+	}
+
+	printf ("%d", (vcc5v / 1000));
+	printf (".%d", (vcc5v % 1000) / 100);
+	printf ("%d V\n", (vcc5v % 100) / 10) ;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	vcc5v,	1,	1,	do_vcc5v,
+	"vcc5v   - read VCC5V on TRAB\n",
+	"\n"
+	"    - read actual value of voltage VCC5V\n"
+);
+
+
+int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int contact_temp;
+
+	if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	spi_init ();
+
+	contact_temp = tsc2000_contact_temp();
+	printf ("%d degree C * 100\n", contact_temp) ;
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	c_temp,	1,	1,	do_contact_temp,
+	"c_temp  - read contact temperature on TRAB\n",
+	"\n"
+	"    -  reads the onboard temperature (=contact temperature)\n"
+);
+
+
+int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	if (argc > 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
+				(unsigned char*) &status, 1)) {
+		return (1);
+	}
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
+				(unsigned char*) &pass_cycles, 2)) {
+		return (1);
+	}
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
+				1, (unsigned char*) &first_error_cycle, 2)) {
+		return (1);
+	}
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
+				1, (unsigned char*) &first_error_num, 1)) {
+		return (1);
+	}
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
+			       1, first_error_name,
+			       sizeof (first_error_name))) {
+		return (1);
+	}
+
+	if (read_max_cycles () != 0) {
+		return (1);
+	}
+
+	printf ("max_cycles = %d\n", max_cycles);
+	printf ("status = %d\n", status);
+	printf ("pass_cycles = %d\n", pass_cycles);
+	printf ("first_error_cycle = %d\n", first_error_cycle);
+	printf ("first_error_num = %d\n", first_error_num);
+	printf ("first_error_name = %.*s\n",(int) sizeof(first_error_name),
+		first_error_name);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bis,	1,	1,	do_burn_in_status,
+	"bis     - print burn in status on TRAB\n",
+	"\n"
+	"    -  prints the status variables of the last burn in test\n"
+	"       stored in the onboard EEPROM on TRAB board\n"
+);
+
+static int read_dip (void)
+{
+	unsigned int result = 0;
+	int adc_val;
+	int i;
+
+	/***********************************************************
+	 DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3):
+	   SW1 - AIN4
+	   SW2 - AIN5
+	   SW3 - AIN6
+	   SW4 - AIN7
+
+	   "On" DIP switch position short-circuits the voltage from
+	   the input channel (i.e. '0' conversion result means "on").
+	*************************************************************/
+
+	for (i = 7; i > 3; i--) {
+
+		if ((adc_val = adc_read (i)) == -1) {
+			printf ("%s: Channel %d could not be read\n",
+				 __FUNCTION__, i);
+			return (-1);
+		}
+
+		/*
+		 * Input voltage (switch open) is 1.8 V.
+		 * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736
+		 * Set trigger at halve that value.
+		 */
+		if (adc_val < 368)
+			result |= (1 << (i-4));
+	}
+	return (result);
+}
+
+
+static int read_vcc5v (void)
+{
+	s32 result;
+
+	/* VCC5V is connected to channel 2 */
+
+	if ((result = adc_read (2)) == -1) {
+		printf ("%s: VCC5V could not be read\n", __FUNCTION__);
+		return (-1);
+	}
+	/*
+	 * Calculate voltage value. Split in two parts because there is no
+	 * floating point support.  VCC5V is connected over an resistor divider:
+	 * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K.
+	 */
+	result = result * 10 * 1000 / 1023; /* result in mV */
+
+	return (result);
+}
+
+
+static int test_dip (void)
+{
+	static int first_run = 1;
+	static int first_dip;
+
+	if (first_run) {
+		if ((first_dip = read_dip ()) == -1) {
+			return (1);
+		}
+		first_run = 0;
+		debug ("%s: first_dip=%d\n", __FUNCTION__, first_dip);
+	}
+	if (first_dip != read_dip ()) {
+		return (1);
+	} else {
+		return (0);
+	}
+}
+
+
+static int test_vcc5v (void)
+{
+	int vcc5v;
+
+	if ((vcc5v = read_vcc5v ()) == -1) {
+		return (1);
+	}
+
+	if ((vcc5v > VCC5V_MAX) || (vcc5v < VCC5V_MIN)) {
+		printf ("%s: vcc5v[V/100]=%d\n", __FUNCTION__, vcc5v);
+		return (1);
+	} else {
+		return (0);
+	}
+}
+
+
+static int test_rotary_switch (void)
+{
+	static int first_run = 1;
+	static int first_rs;
+
+	if (first_run) {
+		/*
+		 * clear bits in CPLD, because they have random values after
+		 * power-up or reset.
+		 */
+		*CPLD_ROTARY_SWITCH |= (1 << 16) | (1 << 17);
+
+		first_rs = ((*CPLD_ROTARY_SWITCH >> 16) & 0x7);
+		first_run = 0;
+		debug ("%s: first_rs=%d\n", __FUNCTION__, first_rs);
+	}
+
+	if (first_rs != ((*CPLD_ROTARY_SWITCH >> 16) & 0x7)) {
+		return (1);
+	} else {
+		return (0);
+	}
+}
+
+
+static int test_sram (void)
+{
+	return (memory_post_tests (SRAM_ADDR, SRAM_SIZE));
+}
+
+
+static int test_eeprom (void)
+{
+	unsigned char temp[sizeof (EEPROM_TEST_STRING_1)];
+	int result = 0;
+
+	/* write test string 1, read back and verify */
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+				EEPROM_TEST_STRING_1,
+				sizeof (EEPROM_TEST_STRING_1))) {
+		return (1);
+	}
+
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+			       temp, sizeof (EEPROM_TEST_STRING_1))) {
+		return (1);
+	}
+
+	if (strcmp (temp, EEPROM_TEST_STRING_1) != 0) {
+		result = 1;
+		printf ("%s: error; read_str = \"%s\"\n", __FUNCTION__, temp);
+	}
+
+	/* write test string 2, read back and verify */
+	if (result == 0) {
+		if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+					EEPROM_TEST_STRING_2,
+					sizeof (EEPROM_TEST_STRING_2))) {
+			return (1);
+		}
+
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_TEST, 1,
+				       temp, sizeof (EEPROM_TEST_STRING_2))) {
+			return (1);
+		}
+
+		if (strcmp (temp, EEPROM_TEST_STRING_2) != 0) {
+			result = 1;
+			printf ("%s: error; read str = \"%s\"\n",
+				__FUNCTION__, temp);
+		}
+	}
+	return (result);
+}
+
+
+static int test_contact_temp (void)
+{
+	int contact_temp;
+
+	contact_temp = tsc2000_contact_temp ();
+
+	if ((contact_temp < MIN_CONTACT_TEMP)
+	    || (contact_temp > MAX_CONTACT_TEMP))
+		return (1);
+	else
+		return (0);
+}
+
+
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+	int i;
+
+	if (alen != 1) {
+		printf ("%s: addr len other than 1 not supported\n",
+			 __FUNCTION__);
+		return (1);
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_write (chip, addr+i, alen, buffer+i, 1)) {
+			printf ("%s: could not write to i2c device %d"
+				 ", addr %d\n", __FUNCTION__, chip, addr);
+			return (1);
+		}
+#if 0
+		printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i="
+			"%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i,
+			alen, buffer, i, buffer+i, buffer+i);
+#endif
+
+		udelay (30000);
+	}
+	return (0);
+}
+
+
+int i2c_read_multiple ( uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+	int i;
+
+	if (alen != 1) {
+		printf ("%s: addr len other than 1 not supported\n",
+			 __FUNCTION__);
+		return (1);
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_read (chip, addr+i, alen, buffer+i, 1)) {
+			printf ("%s: could not read from i2c device %#x"
+				 ", addr %d\n", __FUNCTION__, chip, addr);
+			return (1);
+		}
+	}
+	return (0);
+}
+
+
+static int adc_read (unsigned int channel)
+{
+	int j = 1000; /* timeout value for wait loop in us */
+	int result;
+	S3C2400_ADC *padc;
+
+	padc = S3C2400_GetBase_ADC();
+	channel &= 0x7;
+
+	adc_init ();
+
+	padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
+	padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
+	padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+
+	while (j--) {
+		if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+			break;
+		udelay (1);
+	}
+
+	if (j == 0) {
+		printf("%s: ADC timeout\n", __FUNCTION__);
+		padc->ADCCON |= ADC_STDBM; /* select standby mode */
+		return -1;
+	}
+
+	result = padc->ADCDAT & 0x3FF;
+
+	padc->ADCCON |= ADC_STDBM; /* select standby mode */
+
+	debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
+	       (padc->ADCCON >> 3) & 0x7, result);
+
+	/*
+	 * Wait for ADC to be ready for next conversion. This delay value was
+	 * estimated, because the datasheet does not specify a value.
+	 */
+	udelay (1000);
+
+	return (result);
+}
+
+
+static void adc_init (void)
+{
+	S3C2400_ADC *padc;
+
+	padc = S3C2400_GetBase_ADC();
+
+	padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
+	padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+
+	/*
+	 * Wait some time to avoid problem with very first call of
+	 * adc_read(). Without this delay, sometimes the first read
+	 * adc value is 0. Perhaps because the adjustment of prescaler
+	 * takes some clock cycles?
+	 */
+	udelay (1000);
+
+	return;
+}
+
+
+static void led_set (unsigned int state)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	led_init ();
+
+	switch (state) {
+	case 0: /* turn LED off */
+		gpio->PADAT |= (1 << 12);
+		break;
+	case 1: /* turn LED on */
+		gpio->PADAT &= ~(1 << 12);
+		break;
+	default:
+		break;
+	}
+}
+
+static void led_blink (void)
+{
+	led_init ();
+
+	/* blink LED. This function does not return! */
+	while (1) {
+		led_set (1);
+		udelay (1000000 / LED_BLINK_FREQ / 2);
+		led_set (0);
+		udelay (1000000 / LED_BLINK_FREQ / 2);
+	}
+}
+
+
+static void led_init (void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* configure GPA12 as output and set to High -> LED off */
+	gpio->PACON &= ~(1 << 12);
+	gpio->PADAT |= (1 << 12);
+}
+
+
+static void sdelay (unsigned long seconds)
+{
+	unsigned long i;
+
+	for (i = 0; i < seconds; i++) {
+		udelay (1000000);
+	}
+}
+
+
+static int global_vars_write_to_eeprom (void)
+{
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_STATUS, 1,
+				(unsigned char*) &status, 1)) {
+		return (1);
+	}
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_PASS_CYCLES, 1,
+				(unsigned char*) &pass_cycles, 2)) {
+		return (1);
+	}
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_CYCLE,
+				1, (unsigned char*) &first_error_cycle, 2)) {
+		return (1);
+	}
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NUM,
+				1, (unsigned char*) &first_error_num, 1)) {
+		return (1);
+	}
+	if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_FIRST_ERROR_NAME,
+				1, first_error_name,
+				sizeof(first_error_name))) {
+		return (1);
+	}
+	return (0);
+}
+
+static void global_vars_init (void)
+{
+	status                  = 1; /* error */
+	pass_cycles             = 0;
+	first_error_cycle       = 0;
+	first_error_num         = 0;
+	first_error_name[0]     = '\0';
+	act_cycle               = 0;
+	max_cycles              = 0;
+}
+
+
+static void test_function_table_init (void)
+{
+	int i;
+
+	for (i = 0; i < BIF_MAX; i++)
+		test_function[i].pf = dummy;
+
+	/*
+	 * the length of "name" must not exceed 16, including the '\0'
+	 * termination. See also the EEPROM address map.
+	 */
+	test_function[0].pf = test_dip;
+	test_function[0].name = "dip";
+
+	test_function[1].pf = test_vcc5v;
+	test_function[1].name = "vcc5v";
+
+	test_function[2].pf = test_rotary_switch;
+	test_function[2].name = "rotary_switch";
+
+	test_function[3].pf = test_sram;
+	test_function[3].name = "sram";
+
+	test_function[4].pf = test_eeprom;
+	test_function[4].name = "eeprom";
+
+	test_function[5].pf = test_contact_temp;
+	test_function[5].name = "contact_temp";
+}
+
+
+static int read_max_cycles (void)
+{
+	if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, EE_ADDR_MAX_CYCLES, 1,
+			       (unsigned char *) &max_cycles, 2) != 0) {
+		return (1);
+	}
+
+	return (0);
+}
+
+static int dummy(void)
+{
+	return (0);
+}
+
+int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int contact_temp;
+	int delay = 0;
+#if (CONFIG_COMMANDS & CFG_CMD_DATE)
+	struct rtc_time tm;
+#endif
+
+	if (argc > 2) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (argc > 1) {
+		delay = simple_strtoul(argv[1], NULL, 10);
+	}
+
+	spi_init ();
+	while (1) {
+
+#if (CONFIG_COMMANDS & CFG_CMD_DATE)
+		rtc_get (&tm);
+		printf ("%4d-%02d-%02d %2d:%02d:%02d - ",
+			tm.tm_year, tm.tm_mon, tm.tm_mday,
+			tm.tm_hour, tm.tm_min, tm.tm_sec);
+#endif
+
+		contact_temp = tsc2000_contact_temp();
+		printf ("%d\n", contact_temp) ;
+
+		if (delay != 0)
+			/*
+			 * reset timer to avoid timestamp overflow problem
+			 * after about 68 minutes of udelay() time.
+			 */
+			reset_timer_masked ();
+			sdelay (delay);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	tlog,	2,	1,	do_temp_log,
+	"tlog    - log contact temperature [1/100 C] to console (endlessly)\n",
+	"delay\n"
+	"    - contact temperature [1/100 C] is printed endlessly to console\n"
+	"      <delay> specifies the seconds to wait between two measurements\n"
+	"      For each measurment a timestamp is printeted\n"
+);
+
+#endif	/* CFG_CMD_BSP */
diff --git a/board/trab/config.mk b/board/trab/config.mk
new file mode 100755
index 0000000..f2411d0
--- /dev/null
+++ b/board/trab/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# TRAB board with S3C2400X (arm920t) cpu
+#
+# see http://www.samsung.com/ for more information on SAMSUNG
+#
+
+#
+# TRAB has 1 bank of 16 MB or 32 MB DRAM
+#
+# 0c00'0000 to 0e00'0000
+#
+# Linux-Kernel is expected to be at 0c00'8000, entry 0c00'8000
+#
+# we load ourself to 0CF0'0000	/ 0DF0'0000
+#
+# download areas is 0C80'0000
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0x0DF40000
+endif
diff --git a/board/trab/flash.c b/board/trab/flash.c
new file mode 100755
index 0000000..b4435e3
--- /dev/null
+++ b/board/trab/flash.c
@@ -0,0 +1,568 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <environment.h>
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00F000F0
+#define CMD_UNLOCK1		0x00AA00AA
+#define CMD_UNLOCK2		0x00550055
+#define CMD_ERASE_SETUP		0x00800080
+#define CMD_ERASE_CONFIRM	0x00300030
+#define CMD_PROGRAM		0x00A000A0
+#define CMD_UNLOCK_BYPASS	0x00200020
+#define CMD_READ_MANF_ID	0x00900090
+#define CMD_UNLOCK_BYPASS_RES1	0x00900090
+#define CMD_UNLOCK_BYPASS_RES2	0x00000000
+
+#define MEM_FLASH_ADDR		(*(volatile u32 *)CFG_FLASH_BASE)
+#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
+#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
+
+#define BIT_ERASE_DONE		0x00800080
+#define BIT_RDY_MASK		0x00800080
+#define BIT_PROGRAM_ERROR	0x00200020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		ulong flashbase = 0;
+		flash_info_t *info = &flash_info[i];
+
+		/* Init: no FLASHes known */
+		info->flash_id = FLASH_UNKNOWN;
+
+		size += flash_get_size (CFG_FLASH_BASE, info);
+
+		if (i == 0)
+			flashbase = CFG_FLASH_BASE;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < info->sector_count; j++) {
+
+			info->protect[j] = 0;
+			info->start[j] = flashbase;
+
+			switch (info->flash_id & FLASH_TYPEMASK) {
+			case (FLASH_AM320B & FLASH_TYPEMASK):
+			case (FLASH_MXLV320B & FLASH_TYPEMASK):
+				/* Boot sector type: 8 x 8 + N x 128 kB */
+				flashbase += (j < 8) ? 0x4000 : 0x20000;
+				break;
+			case (FLASH_AM640U & FLASH_TYPEMASK):
+				/* Uniform sector type: 128 kB */
+				flashbase += 0x20000;
+				break;
+			default:
+				printf ("## Bad flash chip type 0x%04lX\n",
+					info->flash_id & FLASH_TYPEMASK);
+			}
+		}
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (FLASH_MAN_AMD & FLASH_VENDMASK):
+			printf ("AMD ");		break;
+	case (FLASH_MAN_FUJ & FLASH_VENDMASK):
+			printf ("FUJITSU ");		break;
+	case (FLASH_MAN_MX  & FLASH_VENDMASK):
+			printf ("MACRONIX ");		break;
+	default:	printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (FLASH_AM320B & FLASH_TYPEMASK):
+		printf ("2x Am29LV320DB (32Mbit)\n");
+		break;
+	case (FLASH_MXLV320B & FLASH_TYPEMASK):
+		printf ("2x MX29LV320DB (32Mbit)\n");
+		break;
+	case (FLASH_AM640U & FLASH_TYPEMASK):
+		printf ("2x Am29LV640D (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:	;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+
+#if 0
+	int cflag;
+#endif
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1, chip2;
+
+	debug ("flash_erase: s_first %d  s_last %d\n", s_first, s_last);
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (FLASH_MAN_AMD & FLASH_VENDMASK):	break;	/* OK */
+	case (FLASH_MAN_FUJ & FLASH_VENDMASK):	break;	/* OK */
+	case (FLASH_MAN_MX  & FLASH_VENDMASK):	break;	/* OK */
+	default:
+		debug ("## flash_erase: unknown manufacturer\n");
+		return (ERR_UNKNOWN_FLASH_VENDOR);
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#if 0
+	cflag = icache_status ();
+	icache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		debug ("Erasing sector %2d @ %08lX... ",
+			sect, info->start[sect]);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked ();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = chip2 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+				if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
+					chip1 = ERR;
+
+				if (!chip2 && (result >> 16) & BIT_ERASE_DONE)
+					chip2 = READY;
+
+				if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR)
+					chip2 = ERR;
+
+			} while (!chip1 || !chip2);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR || chip2 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+		}
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+#if 0
+	if (cflag)
+		icache_enable ();
+#endif
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t * info, ulong dest,
+								ulong data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong result;
+	int rc = ERR_OK;
+
+#if 0
+	int cflag;
+#endif
+	int iflag;
+	int chip1, chip2;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#if 0
+	cflag = icache_status ();
+	icache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	*addr = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	chip1 = chip2 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+		if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
+			result = *addr;
+
+			if ((result & 0x80) == (data & 0x80))
+				chip1 = READY;
+			else
+				chip1 = ERR;
+		}
+
+		if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16))))
+			chip2 = READY;
+
+		if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) {
+			result = *addr;
+
+			if ((result & (0x80 << 16)) == (data & (0x80 << 16)))
+				chip2 = READY;
+			else
+				chip2 = ERR;
+		}
+
+	} while (!chip1 || !chip2);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || chip2 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+#if 0
+	if (cflag)
+		icache_enable ();
+#endif
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			goto Done;
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		if (((ulong)src) & 0x3) {
+			for (i = 0; i < 4; i++) {
+				((char *)&data)[i] = ((vu_char *)src)[i];
+			}
+		}
+		else {
+			data = *((vu_long *) src);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			goto Done;
+		}
+		src += 4;
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		rc = ERR_OK;
+		goto Done;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 24);
+	}
+
+	rc = write_word (info, wp, data);
+
+	Done:
+
+	MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES1;
+	MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES2;
+
+	return (rc);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	ulong value;
+
+	/* Write auto select command sequence and read Manufacturer ID */
+	addr[0x0555] = CMD_UNLOCK1;
+	addr[0x02AA] = CMD_UNLOCK2;
+	addr[0x0555] = CMD_READ_MANF_ID;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case MX_MANUFACT:
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0x00FF00FF;		/* restore read mode */
+		debug ("## flash_init: unknown manufacturer\n");
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+
+		addr[0] = 0x00FF00FF;		/* restore read mode */
+		break;				/* =>  8 MB		*/
+
+	case AMD_ID_LV640U:
+		info->flash_id += FLASH_AM640U;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+
+		addr[0] = 0x00F000F0;		/* restore read mode */
+		break;				/* => 16 MB		*/
+
+	case MX_ID_LV320B:
+		info->flash_id += FLASH_MXLV320B;
+		info->sector_count = 71;
+		info->size = 0x00800000;
+
+		addr[0] = 0x00FF00FF;		/* restore read mode */
+		break;				/* =>  8 MB		*/
+
+	default:
+		debug ("## flash_init: unknown flash chip\n");
+		info->flash_id = FLASH_UNKNOWN;
+		addr[0] = 0x00FF00FF;		/* restore read mode */
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	return (info->size);
+}
diff --git a/board/trab/lowlevel_init.S b/board/trab/lowlevel_init.S
new file mode 100755
index 0000000..128ae7e
--- /dev/null
+++ b/board/trab/lowlevel_init.S
@@ -0,0 +1,182 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the TRAB board by
+ * (C) Copyright 2002-2003
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+/*
+ *
+ * Copied from linux/arch/arm/boot/compressed/head-s3c2400.S
+ *
+ * Copyright (C) 2001 Samsung Electronics by chc, 010406
+ *
+ * TRAB specific tweaks.
+ *
+ */
+
+/* memory controller */
+#define BWSCON 0x14000000
+
+/* Bank0 */
+#define B0_Tacs	0x1	/* 1 clk */
+#define B0_Tcos	0x1	/* 1 clk */
+#define B0_Tacc	0x5	/* 8 clk */
+#define B0_Tcoh	0x1	/* 1 clk */
+#define B0_Tah	0x1	/* 1 clk */
+#define B0_Tacp	0x0
+#define B0_PMC	0x0	/* normal */
+
+/* Bank1 - SRAM */
+#define B1_Tacs	0x1	/* 1 clk */
+#define B1_Tcos	0x1	/* 1 clk */
+#define B1_Tacc	0x5	/* 8 clk */
+#define B1_Tcoh	0x1	/* 1 clk */
+#define B1_Tah	0x1	/* 1 clk */
+#define B1_Tacp	0x0
+#define B1_PMC	0x0	/* normal */
+
+/* Bank2 - CPLD */
+#define B2_Tacs	0x1	/* 1 clk */
+#define B2_Tcos	0x1	/* 1 clk */
+#define B2_Tacc	0x5	/* 8 clk */
+#define B2_Tcoh	0x1	/* 1 clk */
+#define B2_Tah	0x1	/* 1 clk */
+#define B2_Tacp	0x0
+#define B2_PMC	0x0	/* normal */
+
+/* Bank3 - setup for the cs8900 */
+#define B3_Tacs	0x3	/* 4 clk */
+#define B3_Tcos	0x3	/* 4 clk */
+#define B3_Tacc	0x7	/* 14 clk */
+#define B3_Tcoh	0x1	/* 1 clk */
+#define B3_Tah	0x0	/* 0 clk */
+#define B3_Tacp	0x3	/* 6 clk */
+#define B3_PMC	0x0	/* normal */
+
+/* Bank4 */
+#define B4_Tacs	0x0	/* 0 clk */
+#define B4_Tcos	0x0	/* 0 clk */
+#define B4_Tacc	0x7	/* 14 clk */
+#define B4_Tcoh	0x0	/* 0 clk */
+#define B4_Tah	0x0	/* 0 clk */
+#define B4_Tacp	0x0
+#define B4_PMC	0x0	/* normal */
+
+/* Bank5 */
+#define B5_Tacs	0x0	/* 0 clk */
+#define B5_Tcos	0x0	/* 0 clk */
+#define B5_Tacc	0x7	/* 14 clk */
+#define B5_Tcoh	0x0	/* 0 clk */
+#define B5_Tah	0x0	/* 0 clk */
+#define B5_Tacp	0x0
+#define B5_PMC	0x0	/* normal */
+
+#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
+/* Bank6 */
+#define	B6_MT	0x3	/* SDRAM */
+#define	B6_Trcd	0x0	/* 2clk */
+#define	B6_SCAN	0x1	/* 9 bit */
+
+/* Bank7 */
+#define	B7_MT	0x3	/* SDRAM */
+#define	B7_Trcd	0x0	/* 2clk */
+#define	B7_SCAN	0x1	/* 9 bit */
+#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
+/* Bank6 */
+#define	B6_MT	0x3	/* SDRAM */
+#define	B6_Trcd	0x1	/* 2clk */
+#define	B6_SCAN	0x0	/* 8 bit */
+
+/* Bank7 */
+#define	B7_MT	0x3	/* SDRAM */
+#define	B7_Trcd	0x1	/* 2clk */
+#define	B7_SCAN	0x0	/* 8 bit */
+#endif	/* CONFIG_RAM_16MB */
+
+/* refresh parameter */
+#define REFEN	0x1	/* enable refresh */
+#define TREFMD	0x0	/* CBR(CAS before RAS)/auto refresh */
+#define Trp	0x0	/* 2 clk */
+#define Trc	0x3	/* 7 clk */
+#define Tchr	0x2 	/* 3 clk */
+
+#ifdef CONFIG_TRAB_50MHZ
+#define REFCNT	1269	/* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */
+#else
+#define REFCNT	1011	/* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */
+#endif
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads SMRDATA out of FLASH rather than memory ! */
+	ldr     r0, =SMRDATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	ldr	r1, =BWSCON	/* Bus Width Status Controller */
+	add     r2, r0, #52
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+SMRDATA:
+	.word	0x2211d644	/* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */
+	.word	((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
+	.word	((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
+	.word	((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
+	.word	((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
+	.word	((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
+	.word	((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
+	.word	((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
+	.word	((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
+	.word	((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+#ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
+	.word	0x10	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
+#else	/* CONFIG_RAM_16MB	=  16 MB RAM */
+	.word	0x17	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
+#endif	/* CONFIG_RAM_16MB */
+	.word	0x20	/* MRSR6, CL=2clk */
+	.word	0x20	/* MRSR7 */
diff --git a/board/trab/memory.c b/board/trab/memory.c
new file mode 100755
index 0000000..9104413
--- /dev/null
+++ b/board/trab/memory.c
@@ -0,0 +1,485 @@
+/*
+ * (C) Copyright 2002-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* Memory test
+ *
+ * General observations:
+ * o The recommended test sequence is to test the data lines: if they are
+ *   broken, nothing else will work properly.  Then test the address
+ *   lines.  Finally, test the cells in the memory now that the test
+ *   program knows that the address and data lines work properly.
+ *   This sequence also helps isolate and identify what is faulty.
+ *
+ * o For the address line test, it is a good idea to use the base
+ *   address of the lowest memory location, which causes a '1' bit to
+ *   walk through a field of zeros on the address lines and the highest
+ *   memory location, which causes a '0' bit to walk through a field of
+ *   '1's on the address line.
+ *
+ * o Floating buses can fool memory tests if the test routine writes
+ *   a value and then reads it back immediately.  The problem is, the
+ *   write will charge the residual capacitance on the data bus so the
+ *   bus retains its state briefely.  When the test program reads the
+ *   value back immediately, the capacitance of the bus can allow it
+ *   to read back what was written, even though the memory circuitry
+ *   is broken.  To avoid this, the test program should write a test
+ *   pattern to the target location, write a different pattern elsewhere
+ *   to charge the residual capacitance in a differnt manner, then read
+ *   the target location back.
+ *
+ * o Always read the target location EXACTLY ONCE and save it in a local
+ *   variable.  The problem with reading the target location more than
+ *   once is that the second and subsequent reads may work properly,
+ *   resulting in a failed test that tells the poor technician that
+ *   "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
+ *   doesn't help him one bit and causes puzzled phone calls.  Been there,
+ *   done that.
+ *
+ * Data line test:
+ * ---------------
+ * This tests data lines for shorts and opens by forcing adjacent data
+ * to opposite states. Because the data lines could be routed in an
+ * arbitrary manner the must ensure test patterns ensure that every case
+ * is tested. By using the following series of binary patterns every
+ * combination of adjacent bits is test regardless of routing.
+ *
+ *     ...101010101010101010101010
+ *     ...110011001100110011001100
+ *     ...111100001111000011110000
+ *     ...111111110000000011111111
+ *
+ * Carrying this out, gives us six hex patterns as follows:
+ *
+ *     0xaaaaaaaaaaaaaaaa
+ *     0xcccccccccccccccc
+ *     0xf0f0f0f0f0f0f0f0
+ *     0xff00ff00ff00ff00
+ *     0xffff0000ffff0000
+ *     0xffffffff00000000
+ *
+ * To test for short and opens to other signals on our boards, we
+ * simply test with the 1's complemnt of the paterns as well, resulting
+ * in twelve patterns total.
+ *
+ * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
+ * written to a different address in case the data lines are floating.
+ * Thus, if a byte lane fails, you will see part of the special
+ * pattern in that byte lane when the test runs.  For example, if the
+ * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
+ * (for the 'a' test pattern).
+ *
+ * Address line test:
+ * ------------------
+ *  This function performs a test to verify that all the address lines
+ *  hooked up to the RAM work properly.  If there is an address line
+ *  fault, it usually shows up as two different locations in the address
+ *  map (related by the faulty address line) mapping to one physical
+ *  memory storage location.  The artifact that shows up is writing to
+ *  the first location "changes" the second location.
+ *
+ * To test all address lines, we start with the given base address and
+ * xor the address with a '1' bit to flip one address line.  For each
+ * test, we shift the '1' bit left to test the next address line.
+ *
+ * In the actual code, we start with address sizeof(ulong) since our
+ * test pattern we use is a ulong and thus, if we tried to test lower
+ * order address bits, it wouldn't work because our pattern would
+ * overwrite itself.
+ *
+ * Example for a 4 bit address space with the base at 0000:
+ *   0000 <- base
+ *   0001 <- test 1
+ *   0010 <- test 2
+ *   0100 <- test 3
+ *   1000 <- test 4
+ * Example for a 4 bit address space with the base at 0010:
+ *   0010 <- base
+ *   0011 <- test 1
+ *   0000 <- (below the base address, skipped)
+ *   0110 <- test 2
+ *   1010 <- test 3
+ *
+ * The test locations are successively tested to make sure that they are
+ * not "mirrored" onto the base address due to a faulty address line.
+ * Note that the base and each test location are related by one address
+ * line flipped.  Note that the base address need not be all zeros.
+ *
+ * Memory tests 1-4:
+ * -----------------
+ * These tests verify RAM using sequential writes and reads
+ * to/from RAM. There are several test cases that use different patterns to
+ * verify RAM. Each test case fills a region of RAM with one pattern and
+ * then reads the region back and compares its contents with the pattern.
+ * The following patterns are used:
+ *
+ *  1a) zero pattern (0x00000000)
+ *  1b) negative pattern (0xffffffff)
+ *  1c) checkerboard pattern (0x55555555)
+ *  1d) checkerboard pattern (0xaaaaaaaa)
+ *  2)  bit-flip pattern ((1 << (offset % 32))
+ *  3)  address pattern (offset)
+ *  4)  address pattern (~offset)
+ *
+ * Being run in normal mode, the test verifies only small 4Kb
+ * regions of RAM around each 1Mb boundary. For example, for 64Mb
+ * RAM the following areas are verified: 0x00000000-0x00000800,
+ * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
+ * 0x04000000. If the test is run in slow-test mode, it verifies
+ * the whole RAM.
+ */
+
+/* #ifdef CONFIG_POST */
+
+#include <post.h>
+#include <watchdog.h>
+
+/* #if CONFIG_POST & CFG_POST_MEMORY */
+
+/*
+ * Define INJECT_*_ERRORS for testing error detection in the presence of
+ * _good_ hardware.
+ */
+#undef  INJECT_DATA_ERRORS
+#undef  INJECT_ADDRESS_ERRORS
+
+#ifdef INJECT_DATA_ERRORS
+#warning "Injecting data line errors for testing purposes"
+#endif
+
+#ifdef INJECT_ADDRESS_ERRORS
+#warning "Injecting address line errors for testing purposes"
+#endif
+
+
+/*
+ * This function performs a double word move from the data at
+ * the source pointer to the location at the destination pointer.
+ * This is helpful for testing memory on processors which have a 64 bit
+ * wide data bus.
+ *
+ * On those PowerPC with FPU, use assembly and a floating point move:
+ * this does a 64 bit move.
+ *
+ * For other processors, let the compiler generate the best code it can.
+ */
+static void move64(unsigned long long *src, unsigned long long *dest)
+{
+#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
+	asm ("lfd  0, 0(3)\n\t" /* fpr0	  =  *scr	*/
+	 "stfd 0, 0(4)"		/* *dest  =  fpr0	*/
+	 : : : "fr0" );		/* Clobbers fr0		*/
+    return;
+#else
+	*dest = *src;
+#endif
+}
+
+/*
+ * This is 64 bit wide test patterns.  Note that they reside in ROM
+ * (which presumably works) and the tests write them to RAM which may
+ * not work.
+ *
+ * The "otherpattern" is written to drive the data bus to values other
+ * than the test pattern.  This is for detecting floating bus lines.
+ *
+ */
+const static unsigned long long pattern[] = {
+	0xaaaaaaaaaaaaaaaaULL,
+	0xccccccccccccccccULL,
+	0xf0f0f0f0f0f0f0f0ULL,
+	0xff00ff00ff00ff00ULL,
+	0xffff0000ffff0000ULL,
+	0xffffffff00000000ULL,
+	0x00000000ffffffffULL,
+	0x0000ffff0000ffffULL,
+	0x00ff00ff00ff00ffULL,
+	0x0f0f0f0f0f0f0f0fULL,
+	0x3333333333333333ULL,
+	0x5555555555555555ULL,
+};
+const unsigned long long otherpattern = 0x0123456789abcdefULL;
+
+
+static int memory_post_dataline(unsigned long long * pmem)
+{
+	unsigned long long temp64;
+	int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
+	int i;
+	unsigned int hi, lo, pathi, patlo;
+	int ret = 0;
+
+	for ( i = 0; i < num_patterns; i++) {
+		move64((unsigned long long *)&(pattern[i]), pmem++);
+		/*
+		 * Put a different pattern on the data lines: otherwise they
+		 * may float long enough to read back what we wrote.
+		 */
+		move64((unsigned long long *)&otherpattern, pmem--);
+		move64(pmem, &temp64);
+
+#ifdef INJECT_DATA_ERRORS
+		temp64 ^= 0x00008000;
+#endif
+
+		if (temp64 != pattern[i]){
+			pathi = (pattern[i]>>32) & 0xffffffff;
+			patlo = pattern[i] & 0xffffffff;
+
+			hi = (temp64>>32) & 0xffffffff;
+			lo = temp64 & 0xffffffff;
+
+			printf ("Memory (date line) error at %08lx, "
+				  "wrote %08x%08x, read %08x%08x !\n",
+					  (ulong)pmem, pathi, patlo, hi, lo);
+			ret = -1;
+		}
+	}
+	return ret;
+}
+
+static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
+{
+	ulong *target;
+	ulong *end;
+	ulong readback;
+	ulong xor;
+	int   ret = 0;
+
+	end = (ulong *)((ulong)base + size);	/* pointer arith! */
+	xor = 0;
+	for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
+		target = (ulong *)((ulong)testaddr ^ xor);
+		if((target >= base) && (target < end)) {
+			*testaddr = ~*target;
+			readback  = *target;
+
+#ifdef INJECT_ADDRESS_ERRORS
+			if(xor == 0x00008000) {
+				readback = *testaddr;
+			}
+#endif
+			if(readback == *testaddr) {
+				printf ("Memory (address line) error at %08lx<->%08lx, "
+				  	"XOR value %08lx !\n",
+					(ulong)testaddr, (ulong)target,
+					xor);
+				ret = -1;
+			}
+		}
+	}
+	return ret;
+}
+
+static int memory_post_test1 (unsigned long start,
+			      unsigned long size,
+			      unsigned long val)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = val;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != val) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), val, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test2 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = 1 << (i % 32);
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != (1 << (i % 32))) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08x, read %08lx !\n",
+					  (ulong)(mem + i), 1 << (i % 32), readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test3 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = i;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != i) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), i, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+static int memory_post_test4 (unsigned long start, unsigned long size)
+{
+	unsigned long i;
+	ulong *mem = (ulong *) start;
+	ulong readback;
+	int ret = 0;
+
+	for (i = 0; i < size / sizeof (ulong); i++) {
+		mem[i] = ~i;
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) {
+		readback = mem[i];
+		if (readback != ~i) {
+			printf ("Memory error at %08lx, "
+				  "wrote %08lx, read %08lx !\n",
+					  (ulong)(mem + i), ~i, readback);
+
+			ret = -1;
+			break;
+		}
+		if (i % 1024 == 0)
+			WATCHDOG_RESET ();
+	}
+
+	return ret;
+}
+
+int memory_post_tests (unsigned long start, unsigned long size)
+{
+	int ret = 0;
+
+	if (ret == 0)
+		ret = memory_post_dataline ((long long *)start);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_addrline ((long *)start, (long *)start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_addrline ((long *)(start + size - 8),
+					    (long *)start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0x00000000);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0xffffffff);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0x55555555);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test1 (start, size, 0xaaaaaaaa);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test2 (start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test3 (start, size);
+	WATCHDOG_RESET ();
+	if (ret == 0)
+		ret = memory_post_test4 (start, size);
+	WATCHDOG_RESET ();
+
+	return ret;
+}
+
+#if 0
+int memory_post_test (int flags)
+{
+	int ret = 0;
+	DECLARE_GLOBAL_DATA_PTR;
+	bd_t *bd = gd->bd;
+	unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
+				 256 << 20 : bd->bi_memsize) - (1 << 20);
+
+
+	if (flags & POST_SLOWTEST) {
+		ret = memory_post_tests (CFG_SDRAM_BASE, memsize);
+	} else {			/* POST_NORMAL */
+
+		unsigned long i;
+
+		for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+			if (ret == 0)
+				ret = memory_post_tests (i << 20, 0x800);
+			if (ret == 0)
+				ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+		}
+	}
+
+	return ret;
+}
+#endif /* 0 */
+
+/* #endif */ /* CONFIG_POST & CFG_POST_MEMORY */
+/* #endif */ /* CONFIG_POST */
diff --git a/board/trab/rs485.c b/board/trab/rs485.c
new file mode 100755
index 0000000..2aedd2d
--- /dev/null
+++ b/board/trab/rs485.c
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
+ *
+ * Based on cpu/arm920t/serial.c, by Gary Jennejohn
+ * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <s3c2400.h>
+#include "rs485.h"
+
+static void rs485_setbrg (void);
+static void rs485_cfgio (void);
+static void set_rs485re(unsigned char rs485re_state);
+static void set_rs485de(unsigned char rs485de_state);
+static void rs485_setbrg (void);
+#ifdef	NOT_USED
+static void trab_rs485_disable_tx(void);
+static void trab_rs485_disable_rx(void);
+#endif
+
+#define UART_NR	S3C24X0_UART1
+
+/* CPLD-Register for controlling TRAB hardware functions */
+#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
+
+static void rs485_setbrg (void)
+{
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+	int i;
+	unsigned int reg = 0;
+
+	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
+	/* reg = (33000000 / (16 * gd->baudrate)) - 1; */
+	reg = (33000000 / (16 * 38400)) - 1;
+
+	/* FIFO enable, Tx/Rx FIFO clear */
+	uart->UFCON = 0x07;
+	uart->UMCON = 0x0;
+	/* Normal,No parity,1 stop,8 bit */
+	uart->ULCON = 0x3;
+	/*
+	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
+	 * normal,interrupt or polling
+	 */
+	uart->UCON = 0x245;
+	uart->UBRDIV = reg;
+
+	for (i = 0; i < 100; i++);
+}
+
+static void rs485_cfgio (void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->PFCON &= ~(0x3 << 2);
+	gpio->PFCON |=  (0x2 << 2); /* configure GPF1 as RXD1 */
+
+	gpio->PFCON &= ~(0x3 << 6);
+	gpio->PFCON |=  (0x2 << 6); /* configure GPF3 as TXD1 */
+
+	gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
+	gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */
+
+	gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
+}
+
+/*
+ * Initialise the rs485 port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int rs485_init (void)
+{
+	rs485_cfgio ();
+	rs485_setbrg ();
+
+	return (0);
+}
+
+/*
+ * Read a single byte from the rs485 port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int rs485_getc (void)
+{
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+
+	/* wait for character to arrive */
+	while (!(uart->UTRSTAT & 0x1));
+
+	return uart->URXH & 0xff;
+}
+
+/*
+ * Output a single byte to the rs485 port.
+ */
+void rs485_putc (const char c)
+{
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+
+	/* wait for room in the tx FIFO */
+	while (!(uart->UTRSTAT & 0x2));
+
+	uart->UTXH = c;
+
+	/* If \n, also do \r */
+	if (c == '\n')
+		rs485_putc ('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int rs485_tstc (void)
+{
+	S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+
+	return uart->UTRSTAT & 0x1;
+}
+
+void rs485_puts (const char *s)
+{
+	while (*s) {
+		rs485_putc (*s++);
+	}
+}
+
+
+/*
+ * State table:
+ *	RE	DE	Result
+ *	1	1	XMIT
+ *	0	0	RCV
+ *	1	0	Shutdown
+ */
+
+/* function that controls the receiver enable for the rs485 */
+/* rs485re_state reflects the level (0/1) of the RE pin */
+
+static void set_rs485re(unsigned char rs485re_state)
+{
+	if(rs485re_state)
+		*CPLD_RS485_RE = 0x010000;
+	else
+		*CPLD_RS485_RE = 0x0;
+}
+
+/* function that controls the sender enable for the rs485 */
+/* rs485de_state reflects the level (0/1) of the DE pin */
+
+static void set_rs485de(unsigned char rs485de_state)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* This is on PORT A bit 11 */
+	if(rs485de_state)
+		gpio->PADAT |= (1 << 11);
+	else
+		gpio->PADAT &= ~(1 << 11);
+}
+
+
+void trab_rs485_enable_tx(void)
+{
+	set_rs485de(1);
+	set_rs485re(1);
+}
+
+void trab_rs485_enable_rx(void)
+{
+	set_rs485re(0);
+	set_rs485de(0);
+}
+
+#ifdef	NOT_USED
+static void trab_rs485_disable_tx(void)
+{
+	set_rs485de(0);
+}
+
+static void trab_rs485_disable_rx(void)
+{
+	set_rs485re(1);
+}
+#endif
diff --git a/board/trab/rs485.h b/board/trab/rs485.h
new file mode 100755
index 0000000..d4a008a
--- /dev/null
+++ b/board/trab/rs485.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, <martin.krause@tqs.de>
+ *
+ * Based on cpu/arm920t/serial.c, by Gary Jennejohn
+ * (C) Copyright 2002 Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _RS485_H_
+#define _RS485_H_
+
+#include <s3c2400.h>
+
+int rs485_init (void);
+int rs485_getc (void);
+void rs485_putc (const char c);
+int rs485_tstc (void);
+void rs485_puts (const char *s);
+void trab_rs485_enable_tx(void);
+void trab_rs485_enable_rx(void);
+
+#endif	/* _RS485_H_ */
diff --git a/board/trab/trab.c b/board/trab/trab.c
new file mode 100755
index 0000000..e8dfd2c
--- /dev/null
+++ b/board/trab/trab.c
@@ -0,0 +1,412 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <malloc.h>
+#include <s3c2400.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CFG_BRIGHTNESS
+static void spi_init(void);
+static void wait_transmit_done(void);
+static void tsc2000_write(unsigned int page, unsigned int reg,
+						  unsigned int data);
+static void tsc2000_set_brightness(void);
+#endif
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void);
+extern void disable_putc(void);
+extern int do_mdm_init; /* defined in common/main.c */
+
+/*
+ * We need a delay of at least 500 us after turning on the VFD clock
+ * before we can read any useful information for the CPLD controlling
+ * the keyboard switches. Let's play safe and wait 5 ms. The problem
+ * is that timers are not available yet, so we use a manually timed
+ * loop.
+ */
+#define KBD_MDELAY	5000
+static void udelay_no_timer (int usec)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int i;
+	int delay = usec * 3;
+
+	for (i = 0; i < delay; i ++) gd->bd->bi_arch_number = MACH_TYPE_TRAB;
+}
+#endif /* CONFIG_MODEM_SUPPORT */
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init ()
+{
+#if defined(CONFIG_VFD)
+	extern int vfd_init_clocks(void);
+#endif
+	DECLARE_GLOBAL_DATA_PTR;
+	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* memory and cpu-speed are setup before relocation */
+#ifdef CONFIG_TRAB_50MHZ
+	/* change the clock to be 50 MHz 1:1:1 */
+	/* MDIV:0x5c PDIV:4 SDIV:2 */
+	clk_power->MPLLCON = 0x5c042;
+	clk_power->CLKDIVN = 0;
+#else
+	/* change the clock to be 133 MHz 1:2:4 */
+	/* MDIV:0x7d PDIV:4 SDIV:1 */
+	clk_power->MPLLCON = 0x7d041;
+	clk_power->CLKDIVN = 3;
+#endif
+
+	/* set up the I/O ports */
+	gpio->PACON = 0x3ffff;
+	gpio->PBCON = 0xaaaaaaaa;
+	gpio->PBUP  = 0xffff;
+	/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0]	*/
+	/*  00,    10,      10,      10,      10,      10,      10 	*/
+	gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
+#ifdef CONFIG_HWFLOW
+	/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
+	gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);
+#else
+	/* do not pull up RXD0, RXD1, TXD0, TXD1 */
+	gpio->PFUP  = (1<<0) | (1<<1) | (1<<2) | (1<<3);
+#endif
+	gpio->PGCON = 0x0;
+	gpio->PGUP  = 0x0;
+	gpio->OPENCR= 0x0;
+
+	/* suppress flicker of the VFDs */
+	gpio->MISCCR = 0x40;
+	gpio->PFCON |= (2<<12);
+
+	gd->bd->bi_arch_number = MACH_TYPE_TRAB;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x0c000100;
+
+	/* Make sure both buzzers are turned off */
+	gpio->PDCON |= 0x5400;
+	gpio->PDDAT &= ~0xE0;
+
+#ifdef CONFIG_VFD
+	vfd_init_clocks();
+#endif /* CONFIG_VFD */
+
+#ifdef CONFIG_MODEM_SUPPORT
+	udelay_no_timer (KBD_MDELAY);
+
+	if (key_pressed()) {
+		disable_putc();	/* modem doesn't understand banner etc */
+		do_mdm_init = 1;
+	}
+#endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+	/* Configure I/O ports PG5 und PG6 for I2C */
+ 	gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
+#endif /* CONFIG_DRIVER_S3C24X0_I2C */
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Keyboard Controller
+ */
+
+/* Maximum key number */
+#define KEYBD_KEY_NUM		4
+
+#define KBD_DATA	(((*(volatile ulong *)0x04020000) >> 16) & 0xF)
+
+static uchar *key_match (ulong);
+
+int misc_init_r (void)
+{
+	ulong kbd_data = KBD_DATA;
+	uchar keybd_env[KEYBD_KEY_NUM + 1];
+	uchar *str;
+	int i;
+
+#ifdef CONFIG_AUTO_UPDATE
+	extern int do_auto_update(void);
+	/* this has priority over all else */
+	do_auto_update();
+#endif
+
+	for (i = 0; i < KEYBD_KEY_NUM; ++i) {
+		keybd_env[i] = '0' + ((kbd_data >> i) & 1);
+	}
+	keybd_env[i] = '\0';
+	debug ("** Setting keybd=\"%s\"\n", keybd_env);
+	setenv ("keybd", keybd_env);
+
+	str = strdup (key_match (kbd_data));	/* decode keys */
+
+#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
+	debug ("** Setting preboot=\"%s\"\n", str);
+	setenv ("preboot", str);	/* set or delete definition */
+#endif /* CONFIG_PREBOOT */
+	if (str != NULL) {
+		free (str);
+	}
+
+#ifdef CFG_BRIGHTNESS
+	tsc2000_set_brightness();
+#endif
+	return (0);
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+static int compare_magic (ulong kbd_data, uchar *str)
+{
+	uchar key_mask;
+
+	debug ("compare_magic: kbd: %04lx  str: \"%s\"\n",kbd_data,str);
+	for (; *str; str++)
+	{
+		uchar c = *str - '1';
+
+		if (c >= KEYBD_KEY_NUM)		/* bad key number */
+			return -1;
+
+		key_mask = 1 << c;
+
+		if (!(kbd_data & key_mask)) {	/* key not pressed */
+			debug ( "compare_magic: "
+				"kbd: %04lx mask: %04lx - key not pressed\n",
+				kbd_data, key_mask );
+			return -1;
+		}
+
+		kbd_data &= ~key_mask;
+	}
+
+	if (kbd_data) {				/* key(s) not released */
+		debug ( "compare_magic: "
+			"kbd: %04lx - key(s) not released\n", kbd_data);
+		return -1;
+	}
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Check if pressed key(s) match magic sequence,
+ * and return the command string associated with that key(s).
+ *
+ * If no key press was decoded, NULL is returned.
+ *
+ * Note: the first character of the argument will be overwritten with
+ * the "magic charcter code" of the decoded key(s), or '\0'.
+ *
+ *
+ * Note: the string points to static environment data and must be
+ * saved before you call any function that modifies the environment.
+ */
+static uchar *key_match (ulong kbd_data)
+{
+	uchar magic[sizeof (kbd_magic_prefix) + 1];
+	uchar cmd_name[sizeof (kbd_command_prefix) + 1];
+	uchar *suffix;
+	uchar *kbd_magic_keys;
+
+	/*
+	 * The following string defines the characters that can pe appended
+	 * to "key_magic" to form the names of environment variables that
+	 * hold "magic" key codes, i. e. such key codes that can cause
+	 * pre-boot actions. If the string is empty (""), then only
+	 * "key_magic" is checked (old behaviour); the string "125" causes
+	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+	 */
+	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+		kbd_magic_keys = "";
+
+	debug ("key_match: magic_keys=\"%s\"\n", kbd_magic_keys);
+
+	/* loop over all magic keys;
+	 * use '\0' suffix in case of empty string
+	 */
+	for (suffix=kbd_magic_keys; *suffix || suffix==kbd_magic_keys; ++suffix)
+	{
+		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+
+		debug ("key_match: magic=\"%s\"\n",
+			getenv(magic) ? getenv(magic) : "<UNDEFINED>");
+
+		if (compare_magic(kbd_data, getenv(magic)) == 0)
+		{
+			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+			debug ("key_match: cmdname %s=\"%s\"\n",
+				cmd_name,
+				getenv (cmd_name) ?
+					getenv (cmd_name) :
+					"<UNDEFINED>");
+			return (getenv (cmd_name));
+		}
+	}
+	debug ("key_match: no match\n");
+	return (NULL);
+}
+#endif							/* CONFIG_PREBOOT */
+
+/* Read Keyboard status */
+int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	ulong kbd_data = KBD_DATA;
+	uchar keybd_env[KEYBD_KEY_NUM + 1];
+	int i;
+
+	puts ("Keys:");
+	for (i = 0; i < KEYBD_KEY_NUM; ++i) {
+		keybd_env[i] = '0' + ((kbd_data >> i) & 1);
+		printf (" %c", keybd_env[i]);
+	}
+	keybd_env[i] = '\0';
+	putc ('\n');
+	setenv ("keybd", keybd_env);
+	return 0;
+}
+
+U_BOOT_CMD(
+ 	kbd,	1,	1,	do_kbd,
+ 	"kbd     - read keyboard status\n",
+ 	NULL
+);
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int key_pressed(void)
+{
+	return (compare_magic(KBD_DATA, CONFIG_MODEM_KEY_MAGIC) == 0);
+}
+#endif	/* CONFIG_MODEM_SUPPORT */
+
+#ifdef CFG_BRIGHTNESS
+
+static inline void SET_CS_TOUCH(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->PDDAT &= 0x5FF;
+}
+
+static inline void CLR_CS_TOUCH(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->PDDAT |= 0x200;
+}
+
+static void spi_init(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+	int i;
+
+	/* Configure I/O ports. */
+ 	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
+	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
+	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+
+	CLR_CS_TOUCH();
+
+	spi->ch[0].SPPRE = 0x1F; /* Baudrate ca. 514kHz */
+	spi->ch[0].SPPIN = 0x01;  /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].SPCON = 0x1A;  /* Polling, Prescaler, Master, CPOL=0, CPHA=1 */
+
+	/* Dummy byte ensures clock to be low. */
+	for (i = 0; i < 10; i++) {
+		spi->ch[0].SPTDAT = 0xFF;
+	}
+	wait_transmit_done();
+}
+
+static void wait_transmit_done(void)
+{
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+
+	while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+}
+
+static void tsc2000_write(unsigned int page, unsigned int reg,
+						  unsigned int data)
+{
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+	unsigned int command;
+
+	SET_CS_TOUCH();
+	command = 0x0000;
+	command |= (page << 11);
+	command |= (reg << 5);
+
+	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	wait_transmit_done();
+	spi->ch[0].SPTDAT = (command & 0x00FF);
+	wait_transmit_done();
+	spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+	wait_transmit_done();
+	spi->ch[0].SPTDAT = (data & 0x00FF);
+	wait_transmit_done();
+
+	CLR_CS_TOUCH();
+}
+
+static void tsc2000_set_brightness(void)
+{
+	uchar tmp[10];
+	int i, br;
+
+	spi_init();
+	tsc2000_write(1, 2, 0x0); /* Power up DAC */
+
+	i = getenv_r("brightness", tmp, sizeof(tmp));
+	br = (i > 0)
+		? (int) simple_strtoul (tmp, NULL, 10)
+		: CFG_BRIGHTNESS;
+
+	tsc2000_write(0, 0xb, br & 0xff);
+}
+#endif
diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c
new file mode 100755
index 0000000..abb3b29
--- /dev/null
+++ b/board/trab/trab_fkt.c
@@ -0,0 +1,1411 @@
+/*
+ * (C) Copyright 2003
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define	DEBUG
+
+#include <common.h>
+#include <exports.h>
+#include <s3c2400.h>
+#include "tsc2000.h"
+#include "rs485.h"
+
+/*
+ * define, to wait for the touch to be pressed, before reading coordinates in
+ * command do_touch. If not defined, an error message is printed, when the
+ * command do_touch is invoked and the touch is not pressed within an specific
+ * interval.
+ */
+#undef	CONFIG_TOUCH_WAIT_PRESSED
+
+/* max time to wait for touch is pressed */
+#ifndef CONFIG_TOUCH_WAIT_PRESSED
+#define TOUCH_TIMEOUT   5
+#endif /* !CONFIG_TOUCH_WAIT_PRESSED */
+
+/* assignment of CPU internal ADC channels with TRAB hardware */
+#define VCC5V   2
+#define VCC12V  3
+
+/* CPLD-Register for controlling TRAB hardware functions */
+#define CPLD_BUTTONS            ((volatile unsigned long *)0x04020000)
+#define CPLD_FILL_LEVEL         ((volatile unsigned long *)0x04008000)
+#define CPLD_ROTARY_SWITCH      ((volatile unsigned long *)0x04018000)
+#define CPLD_RS485_RE           ((volatile unsigned long *)0x04028000)
+
+/* timer configuration bits for buzzer and PWM */
+#define START2		(1 << 12)
+#define UPDATE2         (1 << 13)
+#define INVERT2         (1 << 14)
+#define RELOAD2         (1 << 15)
+#define START3		(1 << 16)
+#define UPDATE3         (1 << 17)
+#define INVERT3         (1 << 18)
+#define RELOAD3         (1 << 19)
+
+#define PCLK		66000000
+#define BUZZER_FREQ     1000    /* frequency in Hz */
+#define PWM_FREQ        500
+
+
+/* definitions of I2C EEPROM device address */
+#define I2C_EEPROM_DEV_ADDR     0x54
+
+/* definition for touch panel calibration points */
+#define CALIB_TL 0              /* calibration point in (T)op (L)eft corner */
+#define CALIB_DR 1              /* calibration point in (D)own (R)ight corner */
+
+/* EEPROM address map */
+#define SERIAL_NUMBER           8
+#define TOUCH_X0                52
+#define TOUCH_Y0                54
+#define TOUCH_X1                56
+#define TOUCH_Y1                58
+#define CRC16                   60
+
+/* EEPROM stuff */
+#define EEPROM_MAX_CRC_BUF      64
+
+/* RS485 stuff */
+#define RS485_MAX_RECEIVE_BUF_LEN  100
+
+/* Bit definitions for ADCCON */
+#define ADC_ENABLE_START     0x1
+#define ADC_READ_START       0x2
+#define ADC_STDBM            0x4
+#define ADC_INP_AIN0         (0x0 << 3)
+#define ADC_INP_AIN1         (0x1 << 3)
+#define ADC_INP_AIN2         (0x2 << 3)
+#define ADC_INP_AIN3         (0x3 << 3)
+#define ADC_INP_AIN4         (0x4 << 3)
+#define ADC_INP_AIN5         (0x5 << 3)
+#define ADC_INP_AIN6         (0x6 << 3)
+#define ADC_INP_AIN7         (0x7 << 3)
+#define ADC_PRSCEN           0x4000
+#define ADC_ECFLG            0x8000
+
+/* function test functions */
+int do_dip (void);
+int do_info (void);
+int do_vcc5v (void);
+int do_vcc12v (void);
+int do_buttons (void);
+int do_fill_level (void);
+int do_rotary_switch (void);
+int do_pressure (void);
+int do_v_bat (void);
+int do_vfd_id (void);
+int do_buzzer (char **);
+int do_led (char **);
+int do_full_bridge (char **);
+int do_dac (char **);
+int do_motor_contact (void);
+int do_motor (char **);
+int do_pwm (char **);
+int do_thermo (char **);
+int do_touch (char **);
+int do_rs485 (char **);
+int do_serial_number (char **);
+int do_crc16 (void);
+int do_power_switch (void);
+int do_gain (char **);
+int do_eeprom (char **);
+
+/* helper functions */
+static void adc_init (void);
+static int adc_read (unsigned int channel);
+static void print_identifier (void);
+
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
+static void touch_wait_pressed (void);
+#else
+static int touch_check_pressed (void);
+#endif /* CONFIG_TOUCH_WAIT_PRESSED */
+
+static void touch_read_x_y (int *x, int *y);
+static int touch_write_clibration_values (int calib_point, int x, int y);
+static int rs485_send_line (const char *data);
+static int rs485_receive_chars (char *data, int timeout);
+static unsigned short updcrc(unsigned short icrc, unsigned char *icp,
+			     unsigned int icnt);
+
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+static int trab_eeprom_read (char **argv);
+static int trab_eeprom_write (char **argv);
+int i2c_write_multiple (uchar chip, uint addr, int alen, uchar *buffer,
+			int len);
+int i2c_read_multiple ( uchar chip, uint addr, int alen, uchar *buffer,
+			int len);
+#endif /* CFG_CMD_I2C */
+
+/*
+ * TRAB board specific commands. Especially commands for burn-in and function
+ * test.
+ */
+
+int trab_fkt (int argc, char *argv[])
+{
+	int i;
+
+	app_startup(argv);
+	if (get_version () != XF_VERSION) {
+		printf ("Wrong XF_VERSION. Please re-compile with actual "
+			"u-boot sources\n");
+		printf ("Example expects ABI version %d\n", XF_VERSION);
+		printf ("Actual U-Boot ABI version %d\n", (int)get_version());
+		return 1;
+	}
+
+	debug ("argc = %d\n", argc);
+
+	for (i=0; i<=argc; ++i) {
+		debug ("argv[%d] = \"%s\"\n", i, argv[i] ? argv[i] : "<NULL>");
+	}
+
+	adc_init ();
+
+	switch (argc) {
+
+	case 0:
+	case 1:
+		break;
+
+	case 2:
+		if (strcmp (argv[1], "info") == 0) {
+			return (do_info ());
+		}
+		if (strcmp (argv[1], "dip") == 0) {
+			return (do_dip ());
+		}
+		if (strcmp (argv[1], "vcc5v") == 0) {
+			return (do_vcc5v ());
+		}
+		if (strcmp (argv[1], "vcc12v") == 0) {
+			return (do_vcc12v ());
+		}
+		if (strcmp (argv[1], "buttons") == 0) {
+			return (do_buttons ());
+		}
+		if (strcmp (argv[1], "fill_level") == 0) {
+			return (do_fill_level ());
+		}
+		if (strcmp (argv[1], "rotary_switch") == 0) {
+			return (do_rotary_switch ());
+		}
+		if (strcmp (argv[1], "pressure") == 0) {
+			return (do_pressure ());
+		}
+		if (strcmp (argv[1], "v_bat") == 0) {
+			return (do_v_bat ());
+		}
+		if (strcmp (argv[1], "vfd_id") == 0) {
+			return (do_vfd_id ());
+		}
+		if (strcmp (argv[1], "motor_contact") == 0) {
+			return (do_motor_contact ());
+		}
+		if (strcmp (argv[1], "crc16") == 0) {
+			return (do_crc16 ());
+		}
+		if (strcmp (argv[1], "power_switch") == 0) {
+			return (do_power_switch ());
+		}
+		break;
+
+	case 3:
+		if (strcmp (argv[1], "full_bridge") == 0) {
+			return (do_full_bridge (argv));
+		}
+		if (strcmp (argv[1], "dac") == 0) {
+			return (do_dac (argv));
+		}
+		if (strcmp (argv[1], "motor") == 0) {
+			return (do_motor (argv));
+		}
+		if (strcmp (argv[1], "pwm") == 0) {
+			return (do_pwm (argv));
+		}
+		if (strcmp (argv[1], "thermo") == 0) {
+			return (do_thermo (argv));
+		}
+		if (strcmp (argv[1], "touch") == 0) {
+			return (do_touch (argv));
+		}
+		if (strcmp (argv[1], "serial_number") == 0) {
+			return (do_serial_number (argv));
+		}
+		if (strcmp (argv[1], "buzzer") == 0) {
+			return (do_buzzer (argv));
+		}
+		if (strcmp (argv[1], "gain") == 0) {
+			return (do_gain (argv));
+		}
+		break;
+
+	case 4:
+		if (strcmp (argv[1], "led") == 0) {
+			return (do_led (argv));
+		}
+		if (strcmp (argv[1], "rs485") == 0) {
+			return (do_rs485 (argv));
+		}
+		if (strcmp (argv[1], "serial_number") == 0) {
+			return (do_serial_number (argv));
+		}
+		break;
+
+	case 5:
+		if (strcmp (argv[1], "eeprom") == 0) {
+			return (do_eeprom (argv));
+		}
+		break;
+
+	case 6:
+		if (strcmp (argv[1], "eeprom") == 0) {
+			return (do_eeprom (argv));
+		}
+		break;
+
+	default:
+		break;
+	}
+
+	printf ("Usage:\n<command> <parameter1> <parameter2> ...\n");
+	return 1;
+}
+
+int do_info (void)
+{
+	printf ("Stand-alone application for TRAB board function test\n");
+	printf ("Built: %s at %s\n", __DATE__ , __TIME__ );
+
+	return 0;
+}
+
+int do_dip (void)
+{
+	unsigned int result = 0;
+	int adc_val;
+	int i;
+
+	/***********************************************************
+	 DIP switch connection (according to wa4-cpu.sp.301.pdf, page 3):
+	   SW1 - AIN4
+	   SW2 - AIN5
+	   SW3 - AIN6
+	   SW4 - AIN7
+
+	   "On" DIP switch position short-circuits the voltage from
+	   the input channel (i.e. '0' conversion result means "on").
+	*************************************************************/
+
+	for (i = 7; i > 3; i--) {
+
+		if ((adc_val = adc_read (i)) == -1) {
+			printf ("Channel %d could not be read\n", i);
+			return 1;
+		}
+
+		/*
+		 * Input voltage (switch open) is 1.8 V.
+		 * (Vin_High/VRef)*adc_res = (1,8V/2,5V)*1023) = 736
+		 * Set trigger at halve that value.
+		 */
+		if (adc_val < 368)
+			result |= (1 << (i-4));
+	}
+
+	/* print result to console */
+	print_identifier ();
+	for (i = 0; i < 4; i++) {
+		if ((result & (1 << i)) == 0)
+			printf("0");
+		else
+			printf("1");
+	}
+	printf("\n");
+
+	return 0;
+}
+
+
+int do_vcc5v (void)
+{
+	int result;
+
+	/* VCC5V is connected to channel 2 */
+
+	if ((result = adc_read (VCC5V)) == -1) {
+		printf ("VCC5V could not be read\n");
+		return 1;
+	}
+
+	/*
+	 * Calculate voltage value. Split in two parts because there is no
+	 * floating point support.  VCC5V is connected over an resistor divider:
+	 * VCC5V=ADCval*2,5V/1023*(10K+30K)/10K.
+	 */
+	print_identifier ();
+	printf ("%d", (result & 0x3FF)* 10 / 1023);
+	printf (".%d", ((result & 0x3FF)* 10 % 1023)* 10 / 1023);
+	printf ("%d V\n", (((result & 0x3FF) * 10 % 1023 ) * 10 % 1023)
+		* 10 / 1024);
+
+	return 0;
+}
+
+
+int do_vcc12v (void)
+{
+	int result;
+
+	if ((result = adc_read (VCC12V)) == -1) {
+		printf ("VCC12V could not be read\n");
+		return 1;
+	}
+
+	/*
+	 * Calculate voltage value. Split in two parts because there is no
+	 * floating point support.  VCC5V is connected over an resistor divider:
+	 * VCC12V=ADCval*2,5V/1023*(30K+270K)/30K.
+	 */
+	print_identifier ();
+	printf ("%d", (result & 0x3FF)* 25 / 1023);
+	printf (".%d V\n", ((result & 0x3FF)* 25 % 1023) * 10 / 1023);
+
+	return 0;
+}
+
+static int adc_read (unsigned int channel)
+{
+	int j = 1000; /* timeout value for wait loop in us */
+	int result;
+	S3C2400_ADC *padc;
+
+	padc = S3C2400_GetBase_ADC();
+	channel &= 0x7;
+
+	padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
+	padc->ADCCON &= ~(0x7 << 3); /* clear the channel bits */
+	padc->ADCCON |= ((channel << 3) | ADC_ENABLE_START);
+
+	while (j--) {
+		if ((padc->ADCCON & ADC_ENABLE_START) == 0)
+			break;
+		udelay (1);
+	}
+
+	if (j == 0) {
+		printf("%s: ADC timeout\n", __FUNCTION__);
+		padc->ADCCON |= ADC_STDBM; /* select standby mode */
+		return -1;
+	}
+
+	result = padc->ADCDAT & 0x3FF;
+
+	padc->ADCCON |= ADC_STDBM; /* select standby mode */
+
+	debug ("%s: channel %d, result[DIGIT]=%d\n", __FUNCTION__,
+	       (padc->ADCCON >> 3) & 0x7, result);
+
+	/*
+	 * Wait for ADC to be ready for next conversion. This delay value was
+	 * estimated, because the datasheet does not specify a value.
+	 */
+	udelay (1000);
+
+	return (result);
+}
+
+
+static void adc_init (void)
+{
+	S3C2400_ADC *padc;
+
+	padc = S3C2400_GetBase_ADC();
+
+	padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
+	padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
+
+	/*
+	 * Wait some time to avoid problem with very first call of
+	 * adc_read(). Without * this delay, sometimes the first read adc
+	 * value is 0. Perhaps because the * adjustment of prescaler takes
+	 * some clock cycles?
+	 */
+	udelay (1000);
+
+	return;
+}
+
+
+int do_buttons (void)
+{
+	int result;
+	int i;
+
+	result = *CPLD_BUTTONS; /* read CPLD */
+	debug ("%s: cpld_taster (32 bit) %#x\n", __FUNCTION__, result);
+
+	/* print result to console */
+	print_identifier ();
+	for (i = 16; i <= 19; i++) {
+		if ((result & (1 << i)) == 0)
+			printf("0");
+		else
+			printf("1");
+	}
+	printf("\n");
+	return 0;
+}
+
+
+int do_power_switch (void)
+{
+	int result;
+
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* configure GPE7 as input */
+	gpio->PECON &= ~(0x3 << (2 * 7));
+
+	/* signal GPE7 from power switch is low active: 0=on , 1=off */
+	result = ((gpio->PEDAT & (1 << 7)) == (1 << 7)) ? 0 : 1;
+
+	print_identifier ();
+	printf("%d\n", result);
+	return 0;
+}
+
+
+int do_fill_level (void)
+{
+	int result;
+
+	result = *CPLD_FILL_LEVEL; /* read CPLD */
+	debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result);
+
+	/* print result to console */
+	print_identifier ();
+	if ((result & (1 << 16)) == 0)
+		printf("0\n");
+	else
+		printf("1\n");
+	return 0;
+}
+
+
+int do_rotary_switch (void)
+{
+	int result;
+	/*
+	 * Please note, that the default values of the direction bits are
+	 * undefined after reset. So it is a good idea, to make first a dummy
+	 * call to this function, to clear the direction bits and set so to
+	 * proper values.
+	 */
+
+	result = *CPLD_ROTARY_SWITCH; /* read CPLD */
+	debug ("%s: cpld_inc (32 bit) %#x\n", __FUNCTION__, result);
+
+	*CPLD_ROTARY_SWITCH |= (3 << 16); /* clear direction bits in CPLD */
+
+	/* print result to console */
+	print_identifier ();
+	if ((result & (1 << 16)) == (1 << 16))
+		printf("R");
+	if ((result & (1 << 17)) == (1 << 17))
+		printf("L");
+	if (((result & (1 << 16)) == 0) && ((result & (1 << 17)) == 0))
+		printf("0");
+	if ((result & (1 << 18)) == 0)
+		printf("0\n");
+	else
+		printf("1\n");
+	return 0;
+}
+
+
+int do_vfd_id (void)
+{
+	int i;
+	long int pcup_old, pccon_old;
+	int vfd_board_id;
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* try to red vfd board id from the value defined by pull-ups */
+
+	pcup_old = gpio->PCUP;
+	pccon_old = gpio->PCCON;
+
+	gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate  GPC0...GPC3 pull-ups */
+	gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as
+						   * inputs */
+	udelay (10);            /* allow signals to settle */
+	vfd_board_id = (~gpio->PCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
+
+	gpio->PCCON = pccon_old;
+	gpio->PCUP = pcup_old;
+
+	/* print vfd_board_id to console */
+	print_identifier ();
+	for (i = 0; i < 4; i++) {
+		if ((vfd_board_id & (1 << i)) == 0)
+			printf("0");
+		else
+			printf("1");
+	}
+	printf("\n");
+	return 0;
+}
+
+int do_buzzer (char **argv)
+{
+	int counter;
+
+	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* set prescaler for timer 2, 3 and 4 */
+	timers->TCFG0 &= ~0xFF00;
+	timers->TCFG0 |=  0x0F00;
+
+	/* set divider for timer 2 */
+	timers->TCFG1 &= ~0xF00;
+	timers->TCFG1 |=  0x300;
+
+	/* set frequency */
+	counter = (PCLK / BUZZER_FREQ) >> 9;
+	timers->ch[2].TCNTB = counter;
+	timers->ch[2].TCMPB = counter / 2;
+
+	if (strcmp (argv[2], "on") == 0) {
+		debug ("%s: frequency: %d\n", __FUNCTION__,
+		       BUZZER_FREQ);
+
+		/* configure pin GPD7 as TOUT2 */
+		gpio->PDCON &= ~0xC000;
+		gpio->PDCON |= 0x8000;
+
+		/* start */
+		timers->TCON = (timers->TCON | UPDATE2 | RELOAD2) &
+				~INVERT2;
+		timers->TCON = (timers->TCON | START2) & ~UPDATE2;
+		return (0);
+	}
+	else if (strcmp (argv[2], "off") == 0) {
+		/* stop */
+		timers->TCON &= ~(START2 | RELOAD2);
+
+		/* configure GPD7 as output and set to low */
+		gpio->PDCON &= ~0xC000;
+		gpio->PDCON |= 0x4000;
+		gpio->PDDAT &= ~0x80;
+		return (0);
+	}
+
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+
+int do_led (char **argv)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* configure PC14 and PC15 as output */
+	gpio->PCCON &= ~(0xF << 28);
+	gpio->PCCON |= (0x5 << 28);
+
+	/* configure PD0 and PD4 as output */
+	gpio->PDCON &= ~((0x3 << 8) | 0x3);
+	gpio->PDCON |= ((0x1 << 8) | 0x1);
+
+	switch (simple_strtoul(argv[2], NULL, 10)) {
+
+	case 0:
+	case 1:
+		break;
+
+	case 2:
+		if (strcmp (argv[3], "on") == 0)
+			gpio->PCDAT |= (1 << 14);
+		else
+			gpio->PCDAT &= ~(1 << 14);
+		return 0;
+
+	case 3:
+		if (strcmp (argv[3], "on") == 0)
+			gpio->PCDAT |= (1 << 15);
+		else
+			gpio->PCDAT &= ~(1 << 15);
+		return 0;
+
+	case 4:
+		if (strcmp (argv[3], "on") == 0)
+			gpio->PDDAT |= (1 << 0);
+		else
+			gpio->PDDAT &= ~(1 << 0);
+		return 0;
+
+	case 5:
+		if (strcmp (argv[3], "on") == 0)
+			gpio->PDDAT |= (1 << 4);
+		else
+			gpio->PDDAT &= ~(1 << 4);
+		return 0;
+
+	default:
+		break;
+
+	}
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+
+int do_full_bridge (char **argv)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* configure PD5 and PD6 as output */
+	gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2));
+	gpio->PDCON |= ((0x1 << 5*2) | (0x1 << 6*2));
+
+	if (strcmp (argv[2], "+") == 0) {
+	      gpio->PDDAT |= (1 << 5);
+	      gpio->PDDAT |= (1 << 6);
+	      return 0;
+	}
+	else if (strcmp (argv[2], "-") == 0) {
+		gpio->PDDAT &= ~(1 << 5);
+		gpio->PDDAT |= (1 << 6);
+		return 0;
+	}
+	else if (strcmp (argv[2], "off") == 0) {
+		gpio->PDDAT &= ~(1 << 5);
+		gpio->PDDAT &= ~(1 << 6);
+		return 0;
+	}
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+/* val must be in [0, 4095] */
+static inline unsigned long tsc2000_to_uv (u16 val)
+{
+	return ((250000 * val) / 4096) * 10;
+}
+
+
+int do_dac (char **argv)
+{
+	int brightness;
+
+	/* initialize SPI */
+	spi_init ();
+
+	if  (((brightness = simple_strtoul (argv[2], NULL, 10)) < 0) ||
+	     (brightness > 255)) {
+		printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+		return 1;
+	}
+	tsc2000_write(TSC2000_REG_DACCTL, 0x0); /* Power up DAC */
+	tsc2000_write(TSC2000_REG_DAC, brightness & 0xff);
+
+	return 0;
+}
+
+
+int do_v_bat (void)
+{
+	unsigned long ret, res;
+
+	/* initialize SPI */
+	spi_init ();
+
+	tsc2000_write(TSC2000_REG_ADC, 0x1836);
+
+	/* now wait for data available */
+	adc_wait_conversion_done();
+
+	ret = tsc2000_read(TSC2000_REG_BAT1);
+	res = (tsc2000_to_uv(ret) + 1250) / 2500;
+	res += (ERROR_BATTERY * res) / 1000;
+
+	print_identifier ();
+	printf ("%ld", (res / 100));
+	printf (".%ld", ((res % 100) / 10));
+	printf ("%ld V\n", (res % 10));
+	return 0;
+}
+
+
+int do_pressure (void)
+{
+	/* initialize SPI */
+	spi_init ();
+
+	tsc2000_write(TSC2000_REG_ADC, 0x2436);
+
+	/* now wait for data available */
+	adc_wait_conversion_done();
+
+	print_identifier ();
+	printf ("%d\n", tsc2000_read(TSC2000_REG_AUX2));
+	return 0;
+}
+
+
+int do_motor_contact (void)
+{
+	int result;
+
+	result = *CPLD_FILL_LEVEL; /* read CPLD */
+	debug ("%s: cpld_fuellstand (32 bit) %#x\n", __FUNCTION__, result);
+
+	/* print result to console */
+	print_identifier ();
+	if ((result & (1 << 17)) == 0)
+		printf("0\n");
+	else
+		printf("1\n");
+	return 0;
+}
+
+int do_motor (char **argv)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	/* Configure I/O port */
+	gpio->PGCON &= ~(0x3 << 0);
+	gpio->PGCON |= (0x1 << 0);
+
+	if (strcmp (argv[2], "on") == 0) {
+		gpio->PGDAT &= ~(1 << 0);
+		return 0;
+	}
+	if (strcmp (argv[2], "off") == 0) {
+		gpio->PGDAT |= (1 << 0);
+		return 0;
+	}
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+static void print_identifier (void)
+{
+	printf ("## FKT: ");
+}
+
+int do_pwm (char **argv)
+{
+	int counter;
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+
+	if (strcmp (argv[2], "on") == 0) {
+		/* configure pin GPD8 as TOUT3 */
+		gpio->PDCON &= ~(0x3 << 8*2);
+		gpio->PDCON |= (0x2 << 8*2);
+
+		/* set prescaler for timer 2, 3 and 4 */
+		timers->TCFG0 &= ~0xFF00;
+		timers->TCFG0 |= 0x0F00;
+
+		/* set divider for timer 3 */
+		timers->TCFG1 &= ~(0xf << 12);
+		timers->TCFG1 |= (0x3 << 12);
+
+		/* set frequency */
+		counter = (PCLK / PWM_FREQ) >> 9;
+		timers->ch[3].TCNTB = counter;
+		timers->ch[3].TCMPB = counter / 2;
+
+		/* start timer */
+		timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
+		timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+		return 0;
+	}
+	if (strcmp (argv[2], "off") == 0) {
+
+		/* stop timer */
+		timers->TCON &= ~(START2 | RELOAD2);
+
+		/* configure pin GPD8 as output and set to 0 */
+		gpio->PDCON &= ~(0x3 << 8*2);
+		gpio->PDCON |= (0x1 << 8*2);
+		gpio->PDDAT &= ~(1 << 8);
+		return 0;
+	}
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return 1;
+}
+
+
+int do_thermo (char **argv)
+{
+	int     channel, res;
+
+	tsc2000_reg_init ();
+
+	if (strcmp (argv[2], "all") == 0) {
+		int i;
+		for (i=0; i <= 15; i++) {
+			res = tsc2000_read_channel(i);
+			print_identifier ();
+			printf ("c%d: %d\n", i, res);
+		}
+		return 0;
+	}
+	channel = simple_strtoul (argv[2], NULL, 10);
+	res = tsc2000_read_channel(channel);
+	print_identifier ();
+	printf ("%d\n", res);
+	return 0;                 /* return OK */
+}
+
+
+int do_touch (char **argv)
+{
+	int     x, y;
+
+	if (strcmp (argv[2], "tl") == 0) {
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
+		touch_wait_pressed();
+#else
+		{
+			int i;
+			for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) {
+				if (touch_check_pressed ()) {
+					break;
+				}
+				udelay (1000);  /* pause 1 ms */
+			}
+		}
+		if (!touch_check_pressed()) {
+			print_identifier ();
+			printf ("error: touch not pressed\n");
+			return 1;
+		}
+#endif /* CONFIG_TOUCH_WAIT_PRESSED */
+		touch_read_x_y (&x, &y);
+
+		print_identifier ();
+		printf ("x=%d y=%d\n", x, y);
+		return touch_write_clibration_values (CALIB_TL, x, y);
+	}
+	else if (strcmp (argv[2], "dr") == 0) {
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
+		touch_wait_pressed();
+#else
+		{
+			int i;
+			for (i = 0; i < (TOUCH_TIMEOUT * 1000); i++) {
+				if (touch_check_pressed ()) {
+					break;
+				}
+				udelay (1000);  /* pause 1 ms */
+			}
+		}
+		if (!touch_check_pressed()) {
+			print_identifier ();
+			printf ("error: touch not pressed\n");
+			return 1;
+		}
+#endif /* CONFIG_TOUCH_WAIT_PRESSED */
+		touch_read_x_y (&x, &y);
+
+		print_identifier ();
+		printf ("x=%d y=%d\n", x, y);
+
+		return touch_write_clibration_values (CALIB_DR, x, y);
+	}
+	return 1;                 /* not "tl", nor "dr", so return error */
+}
+
+
+#ifdef CONFIG_TOUCH_WAIT_PRESSED
+static void touch_wait_pressed (void)
+{
+	while (!(tsc2000_read(TSC2000_REG_ADC) & TC_PSM));
+}
+
+#else
+static int touch_check_pressed (void)
+{
+	return (tsc2000_read(TSC2000_REG_ADC) & TC_PSM);
+}
+#endif /* CONFIG_TOUCH_WAIT_PRESSED */
+
+static int touch_write_clibration_values (int calib_point, int x, int y)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+	int x_verify = 0;
+	int y_verify = 0;
+
+	tsc2000_reg_init ();
+
+	if (calib_point == CALIB_TL) {
+		if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1,
+			       (char *)&x, 2)) {
+			return 1;
+		}
+		if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1,
+			       (char *)&y, 2)) {
+			return 1;
+		}
+
+		/* verify written values */
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X0, 1,
+			      (char *)&x_verify, 2)) {
+			return 1;
+		}
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y0, 1,
+			       (char *)&y_verify, 2)) {
+			return 1;
+		}
+		if ((y != y_verify) || (x != x_verify)) {
+			print_identifier ();
+			printf ("error: verify error\n");
+			return 1;
+		}
+		return 0;       /* no error */
+	}
+	else if (calib_point == CALIB_DR) {
+		  if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1,
+			       (char *)&x, 2)) {
+			return 1;
+		  }
+		if (i2c_write_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1,
+			       (char *)&y, 2)) {
+			return 1;
+		}
+
+		/* verify written values */
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_X1, 1,
+				       (char *)&x_verify, 2)) {
+			return 1;
+		}
+		if (i2c_read_multiple (I2C_EEPROM_DEV_ADDR, TOUCH_Y1, 1,
+			       (char *)&y_verify, 2)) {
+			return 1;
+		}
+		if ((y != y_verify) || (x != x_verify)) {
+			print_identifier ();
+			printf ("error: verify error\n");
+			return 1;
+		}
+		return 0;
+	}
+	return 1;
+#else
+	printf ("No I2C support enabled (CFG_CMD_I2C), could not write "
+		"to EEPROM\n");
+	return (1);
+#endif /* CFG_CMD_I2C */
+}
+
+
+static void touch_read_x_y (int *px, int *py)
+{
+	tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD0 | TC_AD1);
+	adc_wait_conversion_done();
+	*px = tsc2000_read(TSC2000_REG_X);
+
+	tsc2000_write(TSC2000_REG_ADC, DEFAULT_ADC | TC_AD2);
+	adc_wait_conversion_done();
+	*py = tsc2000_read(TSC2000_REG_Y);
+}
+
+
+int do_rs485 (char **argv)
+{
+	int timeout;
+	char data[RS485_MAX_RECEIVE_BUF_LEN];
+
+	if (strcmp (argv[2], "send") == 0) {
+		return (rs485_send_line (argv[3]));
+	}
+	else if (strcmp (argv[2], "receive") == 0) {
+		timeout = simple_strtoul(argv[3], NULL, 10);
+		if (rs485_receive_chars (data, timeout) != 0) {
+			print_identifier ();
+			printf ("## nothing received\n");
+			return (1);
+		}
+		else {
+			print_identifier ();
+			printf ("%s\n", data);
+			return (0);
+		}
+	}
+	printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]);
+	return (1);             /* unknown command, return error */
+}
+
+
+static int rs485_send_line (const char *data)
+{
+	rs485_init ();
+	trab_rs485_enable_tx ();
+	rs485_puts (data);
+	rs485_putc ('\n');
+
+	return (0);
+}
+
+
+static int rs485_receive_chars (char *data, int timeout)
+{
+	int i;
+	int receive_count = 0;
+
+	rs485_init ();
+	trab_rs485_enable_rx ();
+
+	/* test every 1 ms for received characters to avoid a receive FIFO
+	 * overrun (@ 38.400 Baud) */
+	for (i = 0; i < (timeout * 1000); i++) {
+		while (rs485_tstc ()) {
+			if (receive_count >= RS485_MAX_RECEIVE_BUF_LEN-1)
+				break;
+			*data++ = rs485_getc ();
+			receive_count++;
+		}
+		udelay (1000);  /* pause 1 ms */
+	}
+	*data = '\0';           /* terminate string */
+
+	if (receive_count == 0)
+		return (1);
+	else
+		return (0);
+}
+
+
+int do_serial_number (char **argv)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+	unsigned int serial_number;
+
+	if (strcmp (argv[2], "read") == 0) {
+		if (i2c_read (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1,
+			      (char *)&serial_number, 4)) {
+			printf ("could not read from eeprom\n");
+			return (1);
+		}
+		print_identifier ();
+		printf ("%08d\n", serial_number);
+		return (0);
+	}
+	else if (strcmp (argv[2], "write") == 0) {
+		serial_number = simple_strtoul(argv[3], NULL, 10);
+		if (i2c_write (I2C_EEPROM_DEV_ADDR, SERIAL_NUMBER, 1,
+			      (char *)&serial_number, 4)) {
+			printf ("could not write to eeprom\n");
+			return (1);
+		}
+		return (0);
+	}
+	printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]);
+	return (1);             /* unknown command, return error */
+#else
+	printf ("No I2C support enabled (CFG_CMD_I2C), could not write "
+		"to EEPROM\n");
+	return (1);
+#endif /* CFG_CMD_I2C */
+}
+
+
+int do_crc16 (void)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+	int crc;
+	char buf[EEPROM_MAX_CRC_BUF];
+
+	if (i2c_read (I2C_EEPROM_DEV_ADDR, 0, 1, buf, 60)) {
+		printf ("could not read from eeprom\n");
+		return (1);
+	}
+	crc = 0;                /* start value of crc calculation */
+	crc = updcrc (crc, buf, 60);
+
+	print_identifier ();
+	printf ("crc16=%#04x\n", crc);
+
+	if (i2c_write (I2C_EEPROM_DEV_ADDR, CRC16, 1, (char *)&crc,
+		       sizeof (crc))) {
+		printf ("could not read from eeprom\n");
+		return (1);
+	}
+	return (0);
+#else
+	printf ("No I2C support enabled (CFG_CMD_I2C), could not write "
+		"to EEPROM\n");
+	return (1);
+#endif /* CFG_CMD_I2C */
+}
+
+
+/*
+ * Calculate, intelligently, the CRC of a dataset incrementally given a
+ * buffer full at a time.
+ * Initialize crc to 0 for XMODEM, -1 for CCITT.
+ *
+ * Usage:
+ *   newcrc = updcrc( oldcrc, bufadr, buflen )
+ *        unsigned int oldcrc, buflen;
+ *        char *bufadr;
+ *
+ * Compile with -DTEST to generate program that prints CRC of stdin to stdout.
+ * Compile with -DMAKETAB to print values for crctab to stdout
+ */
+
+    /* the CRC polynomial. This is used by XMODEM (almost CCITT).
+     * If you change P, you must change crctab[]'s initial value to what is
+     * printed by initcrctab()
+     */
+#define   P    0x1021
+
+    /* number of bits in CRC: don't change it. */
+#define W 16
+
+    /* this the number of bits per char: don't change it. */
+#define B 8
+
+static unsigned short crctab[1<<B] = { /* as calculated by initcrctab() */
+    0x0000,  0x1021,  0x2042,  0x3063,  0x4084,  0x50a5,  0x60c6,  0x70e7,
+    0x8108,  0x9129,  0xa14a,  0xb16b,  0xc18c,  0xd1ad,  0xe1ce,  0xf1ef,
+    0x1231,  0x0210,  0x3273,  0x2252,  0x52b5,  0x4294,  0x72f7,  0x62d6,
+    0x9339,  0x8318,  0xb37b,  0xa35a,  0xd3bd,  0xc39c,  0xf3ff,  0xe3de,
+    0x2462,  0x3443,  0x0420,  0x1401,  0x64e6,  0x74c7,  0x44a4,  0x5485,
+    0xa56a,  0xb54b,  0x8528,  0x9509,  0xe5ee,  0xf5cf,  0xc5ac,  0xd58d,
+    0x3653,  0x2672,  0x1611,  0x0630,  0x76d7,  0x66f6,  0x5695,  0x46b4,
+    0xb75b,  0xa77a,  0x9719,  0x8738,  0xf7df,  0xe7fe,  0xd79d,  0xc7bc,
+    0x48c4,  0x58e5,  0x6886,  0x78a7,  0x0840,  0x1861,  0x2802,  0x3823,
+    0xc9cc,  0xd9ed,  0xe98e,  0xf9af,  0x8948,  0x9969,  0xa90a,  0xb92b,
+    0x5af5,  0x4ad4,  0x7ab7,  0x6a96,  0x1a71,  0x0a50,  0x3a33,  0x2a12,
+    0xdbfd,  0xcbdc,  0xfbbf,  0xeb9e,  0x9b79,  0x8b58,  0xbb3b,  0xab1a,
+    0x6ca6,  0x7c87,  0x4ce4,  0x5cc5,  0x2c22,  0x3c03,  0x0c60,  0x1c41,
+    0xedae,  0xfd8f,  0xcdec,  0xddcd,  0xad2a,  0xbd0b,  0x8d68,  0x9d49,
+    0x7e97,  0x6eb6,  0x5ed5,  0x4ef4,  0x3e13,  0x2e32,  0x1e51,  0x0e70,
+    0xff9f,  0xefbe,  0xdfdd,  0xcffc,  0xbf1b,  0xaf3a,  0x9f59,  0x8f78,
+    0x9188,  0x81a9,  0xb1ca,  0xa1eb,  0xd10c,  0xc12d,  0xf14e,  0xe16f,
+    0x1080,  0x00a1,  0x30c2,  0x20e3,  0x5004,  0x4025,  0x7046,  0x6067,
+    0x83b9,  0x9398,  0xa3fb,  0xb3da,  0xc33d,  0xd31c,  0xe37f,  0xf35e,
+    0x02b1,  0x1290,  0x22f3,  0x32d2,  0x4235,  0x5214,  0x6277,  0x7256,
+    0xb5ea,  0xa5cb,  0x95a8,  0x8589,  0xf56e,  0xe54f,  0xd52c,  0xc50d,
+    0x34e2,  0x24c3,  0x14a0,  0x0481,  0x7466,  0x6447,  0x5424,  0x4405,
+    0xa7db,  0xb7fa,  0x8799,  0x97b8,  0xe75f,  0xf77e,  0xc71d,  0xd73c,
+    0x26d3,  0x36f2,  0x0691,  0x16b0,  0x6657,  0x7676,  0x4615,  0x5634,
+    0xd94c,  0xc96d,  0xf90e,  0xe92f,  0x99c8,  0x89e9,  0xb98a,  0xa9ab,
+    0x5844,  0x4865,  0x7806,  0x6827,  0x18c0,  0x08e1,  0x3882,  0x28a3,
+    0xcb7d,  0xdb5c,  0xeb3f,  0xfb1e,  0x8bf9,  0x9bd8,  0xabbb,  0xbb9a,
+    0x4a75,  0x5a54,  0x6a37,  0x7a16,  0x0af1,  0x1ad0,  0x2ab3,  0x3a92,
+    0xfd2e,  0xed0f,  0xdd6c,  0xcd4d,  0xbdaa,  0xad8b,  0x9de8,  0x8dc9,
+    0x7c26,  0x6c07,  0x5c64,  0x4c45,  0x3ca2,  0x2c83,  0x1ce0,  0x0cc1,
+    0xef1f,  0xff3e,  0xcf5d,  0xdf7c,  0xaf9b,  0xbfba,  0x8fd9,  0x9ff8,
+    0x6e17,  0x7e36,  0x4e55,  0x5e74,  0x2e93,  0x3eb2,  0x0ed1,  0x1ef0
+    };
+
+static unsigned short updcrc(unsigned short icrc, unsigned char *icp,
+			     unsigned int icnt )
+{
+	register unsigned short crc = icrc;
+	register unsigned char *cp = icp;
+	register unsigned int cnt = icnt;
+
+	while (cnt--)
+		crc = (crc<<B) ^ crctab[(crc>>(W-B)) ^ *cp++];
+
+	return (crc);
+}
+
+
+int do_gain (char **argv)
+{
+	int range;
+
+	range = simple_strtoul (argv[2], NULL, 10);
+	if ((range < 1) || (range > 3))
+	{
+		printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+		return 1;
+	}
+
+	tsc2000_set_range (range);
+	return (0);
+}
+
+
+int do_eeprom (char **argv)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+	if (strcmp (argv[2], "read") == 0) {
+		return (trab_eeprom_read (argv));
+	}
+
+	else if (strcmp (argv[2], "write") == 0) {
+		return (trab_eeprom_write (argv));
+	}
+
+	printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]);
+	return (1);
+#else
+	printf ("No I2C support enabled (CFG_CMD_I2C), could not write "
+		"to EEPROM\n");
+	return (1);
+#endif /* CFG_CMD_I2C */
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+static int trab_eeprom_read (char **argv)
+{
+	int i;
+	int len;
+	unsigned int addr;
+	long int value = 0;
+	uchar *buffer;
+
+	buffer = (uchar *) &value;
+	addr = simple_strtoul (argv[3], NULL, 10);
+	addr &= 0xfff;
+	len = simple_strtoul (argv[4], NULL, 10);
+	if ((len < 1) || (len > 4)) {
+		printf ("%s: invalid parameter %s\n", __FUNCTION__,
+			argv[4]);
+		return (1);
+	}
+	for (i = 0; i < len; i++) {
+		if (i2c_read (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) {
+			printf ("%s: could not read from i2c device %#x"
+				", addr %d\n", __FUNCTION__,
+				I2C_EEPROM_DEV_ADDR, addr);
+			return (1);
+		}
+	}
+	print_identifier ();
+	if (strcmp (argv[5], "-") == 0) {
+		if (len == 1)
+			printf ("%d\n", (signed char) value);
+		else if (len == 2)
+			printf ("%d\n", (signed short int) value);
+		else
+			printf ("%ld\n", value);
+	}
+	else {
+		if (len == 1)
+			printf ("%d\n", (unsigned char) value);
+		else if (len == 2)
+			printf ("%d\n", (unsigned short int) value);
+		else
+			printf ("%ld\n", (unsigned long int) value);
+	}
+	return (0);
+}
+
+static int trab_eeprom_write (char **argv)
+{
+	int i;
+	int len;
+	unsigned int addr;
+	long int value = 0;
+	uchar *buffer;
+
+	buffer = (uchar *) &value;
+	addr = simple_strtoul (argv[3], NULL, 10);
+	addr &= 0xfff;
+	len = simple_strtoul (argv[4], NULL, 10);
+	if ((len < 1) || (len > 4)) {
+		printf ("%s: invalid parameter %s\n", __FUNCTION__,
+			argv[4]);
+		return (1);
+	}
+	value = simple_strtol (argv[5], NULL, 10);
+	debug ("value=%ld\n", value);
+	for (i = 0; i < len; i++) {
+		if (i2c_write (I2C_EEPROM_DEV_ADDR, addr+i, 1, buffer+i, 1)) {
+			printf ("%s: could not write to i2c device %d"
+				", addr %d\n", __FUNCTION__,
+				I2C_EEPROM_DEV_ADDR, addr);
+			return (1);
+		}
+#if 0
+		printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i="
+			"%#x+%d=%p=%#x \n",I2C_EEPROM_DEV_ADDR_DEV_ADDR , addr,
+			i, addr+i, 1, buffer, i, buffer+i, *(buffer+i));
+#endif
+		udelay (30000); /* wait for EEPROM ready */
+	}
+	return (0);
+}
+
+int i2c_write_multiple (uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+	int i;
+
+	if (alen != 1) {
+		printf ("%s: addr len other than 1 not supported\n",
+			 __FUNCTION__);
+		return (1);
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_write (chip, addr+i, alen, buffer+i, 1)) {
+			printf ("%s: could not write to i2c device %d"
+				 ", addr %d\n", __FUNCTION__, chip, addr);
+			return (1);
+		}
+#if 0
+		printf ("chip=%#x, addr+i=%#x+%d=%p, alen=%d, *buffer+i="
+			"%#x+%d=%p=\"%.1s\"\n", chip, addr, i, addr+i,
+			alen, buffer, i, buffer+i, buffer+i);
+#endif
+
+		udelay (30000);
+	}
+	return (0);
+}
+
+int i2c_read_multiple ( uchar chip, uint addr, int alen,
+			uchar *buffer, int len)
+{
+	int i;
+
+	if (alen != 1) {
+		printf ("%s: addr len other than 1 not supported\n",
+			 __FUNCTION__);
+		return (1);
+	}
+
+	for (i = 0; i < len; i++) {
+		if (i2c_read (chip, addr+i, alen, buffer+i, 1)) {
+			printf ("%s: could not read from i2c device %#x"
+				 ", addr %d\n", __FUNCTION__, chip, addr);
+			return (1);
+		}
+	}
+	return (0);
+}
+#endif /* CFG_CMD_I2C */
diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c
new file mode 100755
index 0000000..ca68682
--- /dev/null
+++ b/board/trab/tsc2000.c
@@ -0,0 +1,362 @@
+/*
+ * Functions to access the TSC2000 controller on TRAB board (used for scanning
+ * thermo sensors)
+ *
+ * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <s3c2400.h>
+#include "tsc2000.h"
+
+#include "Pt1000_temp_data.h"
+
+/* helper function */
+#define abs(value) (((value) < 0) ? ((value)*-1) : (value))
+
+/*
+ * Maximal allowed deviation between two immediate meassurments of an analog
+ * thermo channel. 1 DIGIT = 0.0276 °C. This is used to filter sporadic
+ * "jumps" in measurment.
+ */
+#define MAX_DEVIATION	18	/* unit: DIGITs of adc; 18 DIGIT = 0.5 °C */
+
+void spi_init(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+	int i;
+
+	/* Configure I/O ports. */
+	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
+	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
+	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
+
+	CLR_CS_TOUCH();
+
+	spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
+	spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
+	spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
+				    CPHA=1 */
+
+	/* Dummy byte ensures clock to be low. */
+	for (i = 0; i < 10; i++) {
+		spi->ch[0].SPTDAT = 0xFF;
+	}
+	spi_wait_transmit_done();
+}
+
+
+void spi_wait_transmit_done(void)
+{
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+
+	while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
+}
+
+
+void tsc2000_write(unsigned short reg, unsigned short data)
+{
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+	unsigned int command;
+
+	SET_CS_TOUCH();
+	command = reg;
+	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi_wait_transmit_done();
+	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi_wait_transmit_done();
+	spi->ch[0].SPTDAT = (data & 0xFF00) >> 8;
+	spi_wait_transmit_done();
+	spi->ch[0].SPTDAT = (data & 0x00FF);
+	spi_wait_transmit_done();
+
+	CLR_CS_TOUCH();
+}
+
+
+unsigned short tsc2000_read (unsigned short reg)
+{
+	unsigned short command, data;
+	S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+
+	SET_CS_TOUCH();
+	command = 0x8000 | reg;
+
+	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi_wait_transmit_done();
+	spi->ch[0].SPTDAT = (command & 0x00FF);
+	spi_wait_transmit_done();
+
+	spi->ch[0].SPTDAT = 0xFF;
+	spi_wait_transmit_done();
+	data = spi->ch[0].SPRDAT;
+	spi->ch[0].SPTDAT = 0xFF;
+	spi_wait_transmit_done();
+
+	CLR_CS_TOUCH();
+	return (spi->ch[0].SPRDAT & 0x0FF) | (data << 8);
+}
+
+
+void tsc2000_set_mux (unsigned int channel)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
+	CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
+	switch (channel) {
+	case 0:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 1:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 2:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 3:
+		SET_MUX0; SET_MUX1;
+		SET_MUX1_ENABLE;
+		break;
+	case 4:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 5:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 6:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 7:
+		SET_MUX0; SET_MUX1;
+		SET_MUX2_ENABLE;
+		break;
+	case 8:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 9:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 10:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 11:
+		SET_MUX0; SET_MUX1;
+		SET_MUX3_ENABLE;
+		break;
+	case 12:
+		CLR_MUX0; CLR_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	case 13:
+		SET_MUX0; CLR_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	case 14:
+		CLR_MUX0; SET_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	case 15:
+		SET_MUX0; SET_MUX1;
+		SET_MUX4_ENABLE;
+		break;
+	default:
+		CLR_MUX0; CLR_MUX1;
+	}
+}
+
+
+void tsc2000_set_range (unsigned int range)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	switch (range) {
+	case 1:
+		CLR_SEL_TEMP_V_0; SET_SEL_TEMP_V_1;
+		CLR_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3;
+		break;
+	case 2:
+		CLR_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1;
+		CLR_SEL_TEMP_V_2; SET_SEL_TEMP_V_3;
+		break;
+	case 3:
+		SET_SEL_TEMP_V_0; CLR_SEL_TEMP_V_1;
+		SET_SEL_TEMP_V_2; CLR_SEL_TEMP_V_3;
+		break;
+	}
+}
+
+
+u16 tsc2000_read_channel (unsigned int channel)
+{
+	u16 res;
+
+	tsc2000_set_mux(channel);
+	udelay(3 * TSC2000_DELAY_BASE);
+
+	tsc2000_write(TSC2000_REG_ADC, 0x2036);
+	adc_wait_conversion_done ();
+	res = tsc2000_read(TSC2000_REG_AUX1);
+	return res;
+}
+
+
+s32 tsc2000_contact_temp (void)
+{
+	long adc_pt1000, offset;
+	long u_pt1000;
+	long contact_temp;
+	long temp1, temp2;
+
+	tsc2000_reg_init ();
+	tsc2000_set_range (3);
+
+	/*
+	 * Because of sporadic "jumps" in the measured adc values every
+	 * channel is read two times. If there is a significant difference
+	 * between the two measurements, then print an error and do a third
+	 * measurement, because it is very unlikely that a successive third
+	 * measurement goes also wrong.
+	 */
+	temp1 = tsc2000_read_channel (14);
+	temp2 = tsc2000_read_channel (14);
+	if (abs(temp2 - temp1) < MAX_DEVIATION)
+		adc_pt1000 = temp2;
+	else {
+		printf ("%s: read adc value (channel 14) exceeded max allowed "
+			"deviation: %d * 0.0276 °C\n",
+			__FUNCTION__, MAX_DEVIATION);
+		printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n",
+			temp1, temp2);
+		adc_pt1000 = tsc2000_read_channel (14);
+		printf ("use (third read) adc value: adc_pt1000 = "
+			"%ld DIGITs\n",	adc_pt1000);
+	}
+	debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
+
+	temp1 = tsc2000_read_channel (15);
+	temp2 = tsc2000_read_channel (15);
+	if (abs(temp2 - temp1) < MAX_DEVIATION)
+		offset = temp2;
+	else {
+		printf ("%s: read adc value (channel 15) exceeded max allowed "
+			"deviation: %d * 0.0276 °C\n",
+			__FUNCTION__, MAX_DEVIATION);
+		printf ("adc value 1: %ld DIGITs\nadc value 2: %ld DIGITs\n",
+			temp1, temp2);
+		offset = tsc2000_read_channel (15);
+		printf ("use (third read) adc value: offset = %ld DIGITs\n",
+			offset);
+	}
+	debug ("read channel 15 (offset): %ld\n", offset);
+
+	/*
+	 * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
+	 * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
+	 * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
+	 * error correction Values err_vref and err_amp3 are assumed as 0 in
+	 * u-boot, because this could cause only a very small error (< 1%).
+	 */
+	u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
+	debug ("u_pt1000: %ld\n", u_pt1000);
+
+	if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
+				&contact_temp) == -1) {
+		printf ("%s: error interpolating PT1000 vlaue\n",
+			 __FUNCTION__);
+		return (-1000);
+	}
+	debug ("contact_temp: %ld\n", contact_temp);
+
+	return contact_temp;
+}
+
+
+void tsc2000_reg_init (void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	tsc2000_write(TSC2000_REG_ADC, 0x2036);
+	tsc2000_write(TSC2000_REG_REF, 0x0011);
+	tsc2000_write(TSC2000_REG_DACCTL, 0x0000);
+
+	CON_MUX0;
+	CON_MUX1;
+
+	CON_MUX1_ENABLE;
+	CON_MUX2_ENABLE;
+	CON_MUX3_ENABLE;
+	CON_MUX4_ENABLE;
+
+	CON_SEL_TEMP_V_0;
+	CON_SEL_TEMP_V_1;
+	CON_SEL_TEMP_V_2;
+	CON_SEL_TEMP_V_3;
+
+	tsc2000_set_mux(0);
+	tsc2000_set_range(0);
+}
+
+
+int tsc2000_interpolate(long value, long data[][2], long *result)
+{
+	int i;
+
+	/* the data is sorted and the first element is upper
+	 * limit so we can easily check for out-of-band values
+	 */
+	if (data[0][0] < value || data[1][0] > value)
+		return -1;
+
+	i = 1;
+	while (data[i][0] < value)
+		i++;
+
+	/* To prevent overflow we have to store the intermediate
+	   result in 'long long'.
+	*/
+
+	*result = data[i-1][1] +
+		((unsigned long long)(data[i][1] - data[i-1][1])
+		 * (unsigned long long)(value - data[i-1][0]))
+		/ (data[i][0] - data[i-1][0]);
+
+	return 0;
+}
+
+
+void adc_wait_conversion_done(void)
+{
+	while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
+}
diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h
new file mode 100755
index 0000000..aac9c0c
--- /dev/null
+++ b/board/trab/tsc2000.h
@@ -0,0 +1,145 @@
+/*
+ * Functions to access the TSC2000 controller on TRAB board (used for scanning
+ * thermo sensors)
+ *
+ * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TSC2000_H_
+#define _TSC2000_H_
+
+/* temperature channel multiplexer definitions */
+#define CON_MUX0         	(gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100)
+#define CLR_MUX0         	(gpio->PCDAT &= 0x0FFEF)
+#define SET_MUX0         	(gpio->PCDAT |= 0x00010)
+
+#define CON_MUX1         	(gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400)
+#define CLR_MUX1         	(gpio->PCDAT &= 0x0FFDF)
+#define SET_MUX1         	(gpio->PCDAT |= 0x00020)
+
+#define CON_MUX1_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000)
+#define CLR_MUX1_ENABLE  	(gpio->PCDAT |= 0x00040)
+#define SET_MUX1_ENABLE  	(gpio->PCDAT &= 0x0FFBF)
+
+#define CON_MUX2_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000)
+#define CLR_MUX2_ENABLE  	(gpio->PCDAT |= 0x00080)
+#define SET_MUX2_ENABLE  	(gpio->PCDAT &= 0x0FF7F)
+
+#define CON_MUX3_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000)
+#define CLR_MUX3_ENABLE  	(gpio->PCDAT |= 0x00100)
+#define SET_MUX3_ENABLE  	(gpio->PCDAT &= 0x0FEFF)
+
+#define CON_MUX4_ENABLE  	(gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000)
+#define CLR_MUX4_ENABLE  	(gpio->PCDAT |= 0x00200)
+#define SET_MUX4_ENABLE  	(gpio->PCDAT &= 0x0FDFF)
+
+#define CON_SEL_TEMP_V_0 	(gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000)
+#define CLR_SEL_TEMP_V_0 	(gpio->PCDAT &= 0x0FBFF)
+#define SET_SEL_TEMP_V_0 	(gpio->PCDAT |= 0x00400)
+
+#define CON_SEL_TEMP_V_1 	(gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000)
+#define CLR_SEL_TEMP_V_1 	(gpio->PCDAT &= 0x0F7FF)
+#define SET_SEL_TEMP_V_1 	(gpio->PCDAT |= 0x00800)
+
+#define CON_SEL_TEMP_V_2 	(gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000)
+#define CLR_SEL_TEMP_V_2 	(gpio->PCDAT &= 0x0EFFF)
+#define SET_SEL_TEMP_V_2 	(gpio->PCDAT |= 0x01000)
+
+#define CON_SEL_TEMP_V_3 	(gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000)
+#define CLR_SEL_TEMP_V_3 	(gpio->PCDAT &= 0x0DFFF)
+#define SET_SEL_TEMP_V_3 	(gpio->PCDAT |= 0x02000)
+
+/* TSC2000 register definition */
+#define TSC2000_REG_X		((0 << 11) | (0 << 5))
+#define TSC2000_REG_Y		((0 << 11) | (1 << 5))
+#define TSC2000_REG_Z1		((0 << 11) | (2 << 5))
+#define TSC2000_REG_Z2		((0 << 11) | (3 << 5))
+#define TSC2000_REG_BAT1	((0 << 11) | (5 << 5))
+#define TSC2000_REG_BAT2	((0 << 11) | (6 << 5))
+#define TSC2000_REG_AUX1	((0 << 11) | (7 << 5))
+#define TSC2000_REG_AUX2	((0 << 11) | (8 << 5))
+#define TSC2000_REG_TEMP1	((0 << 11) | (9 << 5))
+#define TSC2000_REG_TEMP2	((0 << 11) | (0xA << 5))
+#define TSC2000_REG_DAC		((0 << 11) | (0xB << 5))
+#define TSC2000_REG_ZERO	((0 << 11) | (0x10 << 5))
+#define TSC2000_REG_ADC		((1 << 11) | (0 << 5))
+#define TSC2000_REG_DACCTL	((1 << 11) | (2 << 5))
+#define TSC2000_REG_REF		((1 << 11) | (3 << 5))
+#define TSC2000_REG_RESET	((1 << 11) | (4 << 5))
+#define TSC2000_REG_CONFIG	((1 << 11) | (5 << 5))
+
+/* bit definition of TSC2000 ADC register */
+#define TC_PSM          (1 << 15)
+#define TC_STS          (1 << 14)
+#define TC_AD3          (1 << 13)
+#define TC_AD2          (1 << 12)
+#define TC_AD1          (1 << 11)
+#define TC_AD0          (1 << 10)
+#define TC_RS1          (1 << 9)
+#define TC_RS0          (1 << 8)
+#define TC_AV1          (1 << 7)
+#define TC_AV0          (1 << 6)
+#define TC_CL1          (1 << 5)
+#define TC_CL0          (1 << 4)
+#define TC_PV2          (1 << 3)
+#define TC_PV1          (1 << 2)
+#define TC_PV0          (1 << 1)
+
+/* default value for TSC2000 ADC register for use with touch functions */
+#define DEFAULT_ADC		(TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0)
+
+#define TSC2000_DELAY_BASE	500
+#define TSC2000_NO_SENSOR	-0x10000
+
+#define ERROR_BATTERY   220     /* must be adjusted, if R68 is changed on
+				 * TRAB */
+
+void tsc2000_write(unsigned short, unsigned short);
+unsigned short tsc2000_read (unsigned short);
+u16 tsc2000_read_channel (unsigned int);
+void tsc2000_set_mux (unsigned int);
+void tsc2000_set_range (unsigned int);
+void tsc2000_reg_init (void);
+s32 tsc2000_contact_temp (void);
+void spi_wait_transmit_done (void);
+void spi_init(void);
+int tsc2000_interpolate(long value, long data[][2], long *result);
+void adc_wait_conversion_done(void);
+
+
+static inline void SET_CS_TOUCH(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->PDDAT &= 0x5FF;
+}
+
+
+static inline void CLR_CS_TOUCH(void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	gpio->PDDAT |= 0x200;
+}
+
+#endif	/* _TSC2000_H_ */
diff --git a/board/trab/u-boot.lds b/board/trab/u-boot.lds
new file mode 100755
index 0000000..e56cdd3
--- /dev/null
+++ b/board/trab/u-boot.lds
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  lib_arm/_umodsi3.o	(.text)
+	  lib_generic/zlib.o	(.text)
+	  lib_generic/crc32.o	(.text)
+	  lib_generic/string.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+	  common/environment.o	(.ppcenv)
+
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
new file mode 100755
index 0000000..f510ee5
--- /dev/null
+++ b/board/trab/vfd.c
@@ -0,0 +1,571 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************/
+/* ** DEBUG SETTINGS							*/
+/************************************************************************/
+
+/* #define DEBUG	*/
+
+/************************************************************************/
+/* ** HEADER FILES							*/
+/************************************************************************/
+
+#include <config.h>
+#include <common.h>
+#include <version.h>
+#include <stdarg.h>
+#include <linux/types.h>
+#include <devices.h>
+#include <s3c2400.h>
+
+#ifdef CONFIG_VFD
+
+/************************************************************************/
+/* ** CONFIG STUFF -- should be moved to board config file		*/
+/************************************************************************/
+
+/************************************************************************/
+
+#ifndef PAGE_SIZE
+#define	PAGE_SIZE	4096
+#endif
+
+#define ROT	0x09
+#define BLAU	0x0C
+#define VIOLETT	0X0D
+
+/* MAGIC */
+#define	FRAME_BUF_SIZE	((256*4*56)/8)
+#define frame_buf_offs 4
+
+/* defines for starting Timer3 as CPLD-Clk */
+#define START3			(1 << 16)
+#define UPDATE3			(1 << 17)
+#define INVERT3			(1 << 18)
+#define RELOAD3			(1 << 19)
+
+/* CPLD-Register for controlling vfd-blank-signal */
+#define VFD_DISABLE	(*(volatile uchar *)0x04038000=0x0000)
+#define VFD_ENABLE	(*(volatile uchar *)0x04038000=0x0001)
+
+/* Supported VFD Types */
+#define	VFD_TYPE_T119C		1	/* Noritake T119C VFD */
+#define	VFD_TYPE_MN11236	2
+
+/*#define NEW_CPLD_CLK*/
+
+int vfd_board_id;
+
+/* taken from armboot/common/vfd.c */
+unsigned long adr_vfd_table[112][18][2][4][2];
+unsigned char bit_vfd_table[112][18][2][4][2];
+
+/*
+ * initialize the values for the VFD-grid-control in the framebuffer
+ */
+void init_grid_ctrl(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	ulong adr, grid_cycle;
+	unsigned int bit, display;
+	unsigned char temp, bit_nr;
+
+	/*
+	 * clear frame buffer (logical clear => set to "black")
+	 */
+	memset ((void *)(gd->fb_base), 0, FRAME_BUF_SIZE);
+
+	switch (gd->vfd_type) {
+	case VFD_TYPE_T119C:
+	    for (display=0; display<4; display++) {
+		for(grid_cycle=0; grid_cycle<56; grid_cycle++) {
+			bit = grid_cycle * 256  * 4 +
+			     (grid_cycle + 200) * 4 +
+			     frame_buf_offs + display;
+ 			/* wrap arround if offset (see manual S3C2400) */
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit - (FRAME_BUF_SIZE * 8);
+			adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8);
+			bit_nr = bit % 8;
+			bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4;
+			temp=(*(volatile unsigned char*)(adr));
+			temp |=  (1<<bit_nr);
+			(*(volatile unsigned char*)(adr))=temp;
+
+			if(grid_cycle<55)
+				bit = grid_cycle*256*4+(grid_cycle+201)*4+frame_buf_offs+display;
+			else
+				bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4; 	/* grid nr. 0 */
+			/* wrap arround if offset (see manual S3C2400) */
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit-(FRAME_BUF_SIZE*8);
+			adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8);
+			bit_nr = bit%8;
+			bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
+			temp=(*(volatile unsigned char*)(adr));
+			temp |=  (1<<bit_nr);
+			(*(volatile unsigned char*)(adr))=temp;
+		}
+	    }
+	    break;
+	case VFD_TYPE_MN11236:
+	    for (display=0; display<4; display++) {
+		for (grid_cycle=0; grid_cycle<38; grid_cycle++) {
+			bit = grid_cycle * 256  * 4 +
+			     (253 - grid_cycle) * 4 +
+			     frame_buf_offs + display;
+			/* wrap arround if offset (see manual S3C2400) */
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit - (FRAME_BUF_SIZE * 8);
+			adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8);
+			bit_nr = bit % 8;
+			bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4;
+			temp=(*(volatile unsigned char*)(adr));
+			temp |=  (1<<bit_nr);
+			(*(volatile unsigned char*)(adr))=temp;
+
+			if(grid_cycle<37)
+				bit = grid_cycle*256*4+(252-grid_cycle)*4+frame_buf_offs+display;
+
+			/* wrap arround if offset (see manual S3C2400) */
+			if (bit>=FRAME_BUF_SIZE*8)
+				bit = bit-(FRAME_BUF_SIZE*8);
+			adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8);
+			bit_nr = bit%8;
+			bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
+			temp=(*(volatile unsigned char*)(adr));
+			temp |=  (1<<bit_nr);
+			(*(volatile unsigned char*)(adr))=temp;
+		}
+	    }
+	    break;
+	default:
+	    printf ("Warning: unknown display type\n");
+	    break;
+	}
+}
+
+/*
+ *create translation table for getting easy the right position in the
+ *physical framebuffer for some x/y-coordinates of the VFDs
+ */
+void create_vfd_table(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned long vfd_table[112][18][2][4][2];
+	unsigned int x, y, color, display, entry, pixel;
+	unsigned int x_abcdef = 0;
+
+	switch (gd->vfd_type) {
+	case VFD_TYPE_T119C:
+	    for(y=0; y<=17; y++) {	/* Line */
+		for(x=0; x<=111; x++) {	/* Column */
+		    for(display=0; display <=3; display++) {
+
+			    /* Display 0 blue pixels */
+			    vfd_table[x][y][0][display][0] =
+				(x==0) ? y*16+display
+				       : (x%4)*4+y*16+((x-1)/2)*1024+display;
+			    /* Display 0 red pixels */
+			    vfd_table[x][y][1][display][0] =
+				(x==0) ? y*16+512+display
+			    	       : (x%4)*4+y*16+((x-1)/2)*1024+512+display;
+		    }
+		}
+	    }
+	    break;
+	case VFD_TYPE_MN11236:
+	    for(y=0; y<=17; y++) {	/* Line */
+		for(x=0; x<=111; x++) {	/* Column */
+		    for(display=0; display <=3; display++) {
+
+			    vfd_table[x][y][0][display][0]=0;
+			    vfd_table[x][y][0][display][1]=0;
+			    vfd_table[x][y][1][display][0]=0;
+			    vfd_table[x][y][1][display][1]=0;
+
+			    switch (x%6) {
+			    case 0: x_abcdef=0; break; /* a -> a */
+			    case 1: x_abcdef=2; break; /* b -> c */
+			    case 2: x_abcdef=4; break; /* c -> e */
+			    case 3: x_abcdef=5; break; /* d -> f */
+			    case 4: x_abcdef=3; break; /* e -> d */
+			    case 5: x_abcdef=1; break; /* f -> b */
+			    }
+
+			    /* blue pixels */
+			    vfd_table[x][y][0][display][0] =
+				(x>1) ? x_abcdef*4+((x-1)/3)*1024+y*48+display
+				      : x_abcdef*4+             0+y*48+display;
+			    /* blue pixels */
+			    if (x>1 && (x-1)%3)
+				    vfd_table[x][y][0][display][1] = x_abcdef*4+((x-1)/3+1)*1024+y*48+display;
+
+			    /* red pixels */
+			    vfd_table[x][y][1][display][0] =
+				(x>1) ? x_abcdef*4+24+((x-1)/3)*1024+y*48+display
+				      : x_abcdef*4+24+             0+y*48+display;
+			    /* red pixels */
+			    if (x>1 && (x-1)%3)
+				    vfd_table[x][y][1][display][1] = x_abcdef*4+24+((x-1)/3+1)*1024+y*48+display;
+		    }
+		}
+	    }
+	    break;
+	default:
+	    /* do nothing */
+	    return;
+	}
+
+	/*
+	 * Create table with entries for physical byte adresses and
+	 * bit-number within the byte
+	 * from table with bit-numbers within the total framebuffer
+	 */
+	for(y=0;y<18;y++) {
+	    for(x=0;x<112;x++) {
+		for(color=0;color<2;color++) {
+		    for(display=0;display<4;display++) {
+			for(entry=0;entry<2;entry++) {
+			    unsigned long adr  = gd->fb_base;
+			    unsigned int bit_nr = 0;
+
+			    if (vfd_table[x][y][color][display][entry]) {
+
+				pixel  = vfd_table[x][y][color][display][entry] + frame_buf_offs;
+				 /*
+				  * wrap arround if offset
+				  * (see manual S3C2400)
+				  */
+				if (pixel>=FRAME_BUF_SIZE*8)
+					pixel = pixel-(FRAME_BUF_SIZE*8);
+				adr    = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8);
+				bit_nr = pixel%8;
+				bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
+			    }
+			    adr_vfd_table[x][y][color][display][entry] = adr;
+			    bit_vfd_table[x][y][color][display][entry] = bit_nr;
+			}
+		    }
+		}
+	    }
+	}
+}
+
+/*
+ * Set/clear pixel of the VFDs
+ */
+void set_vfd_pixel(unsigned char x, unsigned char y,
+		   unsigned char color, unsigned char display,
+		   unsigned char value)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	ulong adr;
+	unsigned char bit_nr, temp;
+
+	if (! gd->vfd_type) {
+		/* Unknown type. */
+		return;
+	}
+
+	/* Pixel-Eintrag Nr. 1 */
+	adr = adr_vfd_table[x][y][color][display][0];
+	/* Pixel-Eintrag Nr. 1 */
+	bit_nr = bit_vfd_table[x][y][color][display][0];
+	temp=(*(volatile unsigned char*)(adr));
+
+	if (value)
+		temp |=  (1<<bit_nr);
+	else
+		temp &= ~(1<<bit_nr);
+
+	(*(volatile unsigned char*)(adr))=temp;
+}
+
+/*
+ * transfer image from BMP-File
+ */
+void transfer_pic(int display, unsigned char *adr, int height, int width)
+{
+	int x, y;
+	unsigned char temp;
+
+	for (; height > 0; height -= 18)
+	{
+		if (height > 18)
+			y = 18;
+		else
+			y = height;
+		for (; y > 0; y--)
+		{
+			for (x = 0; x < width; x += 2)
+			{
+				temp = *adr++;
+				set_vfd_pixel(x, y-1, 0, display, 0);
+				set_vfd_pixel(x, y-1, 1, display, 0);
+				if ((temp >> 4) == BLAU)
+					set_vfd_pixel(x, y-1, 0, display, 1);
+				else if ((temp >> 4) == ROT)
+					set_vfd_pixel(x, y-1, 1, display, 1);
+				else if ((temp >> 4) == VIOLETT)
+				{
+					set_vfd_pixel(x, y-1, 0, display, 1);
+					set_vfd_pixel(x, y-1, 1, display, 1);
+				}
+				set_vfd_pixel(x+1, y-1, 0, display, 0);
+				set_vfd_pixel(x+1, y-1, 1, display, 0);
+				if ((temp & 0x0F) == BLAU)
+					set_vfd_pixel(x+1, y-1, 0, display, 1);
+				else if ((temp & 0x0F) == ROT)
+					set_vfd_pixel(x+1, y-1, 1, display, 1);
+				else if ((temp & 0x0F) == VIOLETT)
+				{
+					set_vfd_pixel(x+1, y-1, 0, display, 1);
+					set_vfd_pixel(x+1, y-1, 1, display, 1);
+				}
+			}
+		}
+		if (display > 0)
+			display--;
+		else
+			display = 3;
+	}
+}
+
+/*
+ * This function initializes VFD clock that is needed for the CPLD that
+ * manages the keyboard.
+ */
+int vfd_init_clocks (void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+	S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
+
+	/* try to determine display type from the value
+	 * defined by pull-ups
+	 */
+	gpio->PCUP = (gpio->PCUP & 0xFFF0);	/* activate  GPC0...GPC3 pullups */
+	gpio->PCCON = (gpio->PCCON & 0xFFFFFF00);	/* configure GPC0...GPC3 as inputs */
+	udelay (10);				/* allow signals to settle */
+	vfd_board_id = (~gpio->PCDAT) & 0x000F;	/* read GPC0...GPC3 port pins */
+
+	VFD_DISABLE;				/* activate blank for the vfd */
+
+#define	NEW_CPLD_CLK
+
+#ifdef NEW_CPLD_CLK
+	if (vfd_board_id) {
+		/* If new board revision, then use PWM 3 as cpld-clock */
+		/* Enable 500 Hz timer for fill level sensor to operate properly */
+		/* Configure TOUT3 as functional pin, disable pull-up */
+		gpio->PDCON &= ~0x30000;
+		gpio->PDCON |= 0x20000;
+		gpio->PDUP |= (1 << 8);
+
+		/* Configure the prescaler */
+		timers->TCFG0 &= ~0xff00;
+		timers->TCFG0 |= 0x0f00;
+
+		/* Select MUX input (divider) for timer3 (1/16) */
+		timers->TCFG1 &= ~0xf000;
+		timers->TCFG1 |= 0x3000;
+
+		/* Enable autoreload and set the counter and compare
+		 * registers to values for the 500 Hz clock
+		 * (for a given  prescaler (15) and divider (16)):
+		 * counter = (66000000 / 500) >> 9;
+		 */
+		timers->ch[3].TCNTB = 0x101;
+		timers->ch[3].TCMPB = 0x101 / 2;
+
+		/* Start timer */
+		timers->TCON = (timers->TCON | UPDATE3 | RELOAD3) & ~INVERT3;
+		timers->TCON = (timers->TCON | START3) & ~UPDATE3;
+	}
+#endif
+	/* If old board revision, then use vm-signal as cpld-clock */
+	lcd->LCDCON2 = 0x00FFC000;
+	lcd->LCDCON3 = 0x0007FF00;
+	lcd->LCDCON4 = 0x00000000;
+	lcd->LCDCON5 = 0x00000400;
+	lcd->LCDCON1 = 0x00000B75;
+	/* VM (GPD1) is used as clock for the CPLD */
+	gpio->PDCON = (gpio->PDCON & 0xFFFFFFF3) | 0x00000008;
+
+	return 0;
+}
+
+/*
+ * initialize LCD-Controller of the S3C2400 for using VFDs
+ *
+ * VFD detection depends on the board revision:
+ * starting from Rev. 200 a type code can be read from the data pins,
+ * driven by some pull-up resistors; all earlier systems must be
+ * manually configured. The type is set in the "vfd_type" environment
+ * variable.
+ */
+int drv_vfd_init(void)
+{
+	S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	char *tmp;
+	ulong palette;
+	static int vfd_init_done = 0;
+	int vfd_inv_data = 0;
+
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (vfd_init_done != 0)
+		return (0);
+	vfd_init_done = 1;
+
+	debug("Detecting Revison of WA4-VFD: ID=0x%X\n", vfd_board_id);
+
+	switch (vfd_board_id) {
+	case 0:			/* board revision < Rev.200 */
+		if ((tmp = getenv ("vfd_type")) == NULL) {
+			break;
+		}
+		if (strcmp(tmp, "T119C") == 0) {
+			gd->vfd_type = VFD_TYPE_T119C;
+		} else if (strcmp(tmp, "MN11236") == 0) {
+			gd->vfd_type = VFD_TYPE_MN11236;
+		} else {
+			/* cannot use printf for a warning here */
+			gd->vfd_type = 0;	/* unknown */
+		}
+
+		break;
+	default:		/* default to MN11236, data inverted */
+		gd->vfd_type = VFD_TYPE_MN11236;
+		vfd_inv_data = 1;
+		setenv ("vfd_type", "MN11236");
+	}
+	debug ("VFD type: %s%s\n",
+		(gd->vfd_type == VFD_TYPE_T119C)   ? "T119C" :
+		(gd->vfd_type == VFD_TYPE_MN11236) ? "MN11236" :
+		"unknown",
+		vfd_inv_data ? ", inverted data" : "");
+
+	gd->fb_base = gd->fb_base;
+	create_vfd_table();
+	init_grid_ctrl();
+
+	for (palette=0; palette < 16; palette++)
+		(*(volatile unsigned int*)(PALETTE+(palette*4)))=palette;
+	for (palette=16; palette < 256; palette++)
+		(*(volatile unsigned int*)(PALETTE+(palette*4)))=0x00;
+
+	/*
+	 * Hinweis: Der Framebuffer ist um genau ein Nibble verschoben
+	 * Das erste angezeigte Pixel wird aus dem zweiten Nibble geholt
+	 * das letzte angezeigte Pixel wird aus dem ersten Nibble geholt
+	 * (wrap around)
+	 * see manual S3C2400
+	 */
+	/* Stopp LCD-Controller */
+	lcd->LCDCON1 = 0x00000000;
+	/* frame buffer startadr */
+	lcd->LCDSADDR1 = gd->fb_base >> 1;
+ 	/* frame buffer endadr */
+	lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1;
+	lcd->LCDSADDR3 = ((256/4));
+	lcd->LCDCON2 = 0x000DC000;
+	if(gd->vfd_type == VFD_TYPE_MN11236)
+		lcd->LCDCON2 = 37 << 14;	/* MN11236: 38 lines */
+	else
+		lcd->LCDCON2 = 55 << 14;	/* T119C:   56 lines */
+	lcd->LCDCON3 = 0x0051000A;
+	lcd->LCDCON4 = 0x00000001;
+	if (gd->vfd_type && vfd_inv_data)
+		lcd->LCDCON5 = 0x000004C0;
+	else
+		lcd->LCDCON5 = 0x00000440;
+
+	/* Port pins as LCD output */
+	gpio->PCCON =   (gpio->PCCON & 0xFFFFFF00)| 0x000000AA;
+	gpio->PDCON =   (gpio->PDCON & 0xFFFFFF03)| 0x000000A8;
+
+	/* Synchronize VFD enable with LCD controller to avoid flicker	*/
+	lcd->LCDCON1 = 0x00000B75;			/* Start LCD-Controller	*/
+	while((lcd->LCDCON5 & 0x180000)!=0x100000);	/* Wait for end of VSYNC */
+	while((lcd->LCDCON5 & 0x060000)!=0x040000);	/* Wait for next HSYNC	*/
+	while((lcd->LCDCON5 & 0x060000)==0x040000);
+	while((lcd->LCDCON5 & 0x060000)!=0x000000);
+	if(gd->vfd_type)
+		VFD_ENABLE;
+
+	debug ("LCDSADDR1: %lX\n", lcd->LCDSADDR1);
+	debug ("LCDSADDR2: %lX\n", lcd->LCDSADDR2);
+	debug ("LCDSADDR3: %lX\n", lcd->LCDSADDR3);
+
+	return 0;
+}
+
+/*
+ * Disable VFD: should be run before resetting the system:
+ * disable VM, enable pull-up
+ */
+void disable_vfd (void)
+{
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+
+	VFD_DISABLE;
+	gpio->PDCON &= ~0xC;
+	gpio->PDUP  &= ~0x2;
+}
+
+/************************************************************************/
+/* ** ROM capable initialization part - needed to reserve FB memory	*/
+/************************************************************************/
+
+/*
+ * This is called early in the system initialization to grab memory
+ * for the VFD controller.
+ *
+ * Note that this is running from ROM, so no write access to global data.
+ */
+ulong vfd_setmem (ulong addr)
+{
+	ulong size;
+
+	/* Round up to nearest full page */
+	size = (FRAME_BUF_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+
+	debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr);
+
+	return (size);
+}
+
+/*
+ * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
+ * descriptors and palette areas.
+ */
+ulong calc_fbsize (void)
+{
+	return FRAME_BUF_SIZE;
+}
+
+#endif /* CONFIG_VFD */
diff --git a/board/uc100/Makefile b/board/uc100/Makefile
new file mode 100755
index 0000000..eb81625
--- /dev/null
+++ b/board/uc100/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+#OBJS	= $(BOARD).o flash.o
+OBJS	= $(BOARD).o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/uc100/config.mk b/board/uc100/config.mk
new file mode 100755
index 0000000..a65a8ba
--- /dev/null
+++ b/board/uc100/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# UC100 boards
+#
+
+#TEXT_BASE = 0x40000000
+TEXT_BASE = 0x40700000
diff --git a/board/uc100/u-boot.lds b/board/uc100/u-boot.lds
new file mode 100755
index 0000000..d7c798e
--- /dev/null
+++ b/board/uc100/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/uc100/u-boot.lds.debug b/board/uc100/u-boot.lds.debug
new file mode 100755
index 0000000..d9bb868
--- /dev/null
+++ b/board/uc100/u-boot.lds.debug
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c
new file mode 100755
index 0000000..4f2cff6
--- /dev/null
+++ b/board/uc100/uc100.c
@@ -0,0 +1,282 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <i2c.h>
+#include <miiphy.h>
+
+int fec8xx_miiphy_write(char *devname, unsigned char  addr,
+		unsigned char  reg, unsigned short value);
+
+/*********************************************************************/
+/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B)     */
+/*********************************************************************/
+const uint sdram_init_upm_table[] = {
+	/* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
+	/* NOP    - Precharge - AutoRefr  - NOP       - NOP        */
+	/* NOP    - AutoRefr  - NOP                                */
+	/* NOP    - NOP       - LoadModeR - NOP       - Active     */
+	/* Position of Single Read                                 */
+	0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
+	0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
+
+	/* Burst Read. (offset 8 in UPMA RAM)     */
+	/* Cycle lent for Initialisation WV */
+	0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Single Write. (offset 18 in UPMA RAM) */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Burst Write. (offset 20 in UPMA RAM) */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Refresh  (offset 30 in UPMA RAM) */
+	0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
+	0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Exception. (offset 3c in UPMA RAM) */
+	0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+/*********************************************************************/
+/* UPMA initilization table.                                         */
+/*********************************************************************/
+const uint sdram_upm_table[] = {
+	/* single read. (offset 0 in UPMA RAM) */
+	0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     /* 0x05-0x07 new WV */
+
+	/* Burst Read. (offset 8 in UPMA RAM) */
+	0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
+	0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Single Write. (offset 18 in UPMA RAM) */
+	0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
+	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Burst Write. (offset 20 in UPMA RAM) */
+	0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
+	0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Refresh  (offset 30 in UPMA RAM) */
+	0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
+	0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Exception. (offset 3c in UPMA RAM) */
+	0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
+};
+
+/*********************************************************************/
+/* UPMB initilization table.                                         */
+/*********************************************************************/
+const uint mpm_upm_table[] = {
+	/*  single read. (offset 0 in upm RAM) */
+	0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
+	0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* burst read. (Offset 8 in upm RAM)   */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* single write. (Offset 0x18 in upm RAM) */
+	0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
+	0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*  burst write. (Offset 0x20 in upm RAM) */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Refresh cycle, offset 0x30 */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Exception, 0ffset 0x3C */
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+
+int board_switch(void)
+{
+	volatile pcmconf8xx_t	*pcmp;
+
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+
+	return ((pcmp->pcmc_pipr >> 24) & 0xf);
+}
+
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	char str[64];
+	int i = getenv_r ("serial#", str, sizeof(str));
+
+	puts ("Board: ");
+
+	if (i == -1) {
+		puts ("### No HW ID - assuming UC100");
+	} else {
+		puts(str);
+	}
+
+	printf (" (SWITCH=%1X)\n", board_switch());
+
+	return 0;
+}
+
+
+/*
+ * Initialize SDRAM
+ */
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/*---------------------------------------------------------------------*/
+	/* Initialize the UPMA/UPMB registers with the appropriate table.      */
+	/*---------------------------------------------------------------------*/
+	upmconfig (UPMA, (uint *) sdram_init_upm_table,
+		   sizeof (sdram_init_upm_table) / sizeof (uint));
+	upmconfig (UPMB, (uint *) mpm_upm_table,
+		   sizeof (mpm_upm_table) / sizeof (uint));
+
+	/*---------------------------------------------------------------------*/
+	/* Memory Periodic Timer Prescaler: divide by 16                       */
+	/*---------------------------------------------------------------------*/
+	memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
+
+	memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
+   	memctl->memc_mbmr = CFG_MBMR_VAL;
+
+	/*---------------------------------------------------------------------*/
+	/* Initialize the Memory Controller registers, MPTPR, Chip Select 1    */
+	/* for SDRAM                                                           */
+	/*                                                                     */
+	/* NOTE: The refresh rate in MAMR reg is set according to the lowest   */
+	/*       clock rate (16.67MHz) to allow proper operation for all ADS   */
+	/*       clock frequencies.                                            */
+	/*---------------------------------------------------------------------*/
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	/*-------------------------------------------------------------------*/
+	/* Wait at least 200 usec for DRAM to stabilize, this magic number   */
+	/* obtained from the init code.                                      */
+	/*-------------------------------------------------------------------*/
+	udelay(200);
+
+	memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
+
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+
+	/*---------------------------------------------------------------------*/
+	/* run MRS command in location 5-8 of UPMB.                            */
+	/*---------------------------------------------------------------------*/
+	memctl->memc_mar = 0x88;
+	/* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
+
+	memctl->memc_mcr = 0x80002100;
+	/* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
+
+	udelay(200);
+
+	/*---------------------------------------------------------------------*/
+	/* Initialisation for normal access WV                                 */
+	/*---------------------------------------------------------------------*/
+
+	/*---------------------------------------------------------------------*/
+	/* Initialize the UPMA register with the appropriate table.            */
+	/*---------------------------------------------------------------------*/
+	upmconfig (UPMA, (uint *) sdram_upm_table,
+		   sizeof (sdram_upm_table) / sizeof (uint));
+
+	/*---------------------------------------------------------------------*/
+	/* rerstore MBMR value (4-beat refresh burst.)                         */
+	/*---------------------------------------------------------------------*/
+	memctl->memc_mamr = CFG_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
+
+	udelay(200);
+
+	return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
+}
+
+
+int misc_init_r (void)
+{
+	uchar val;
+
+	/*
+	 * Make sure that RTC has clock output enabled (triggers watchdog!)
+	 */
+	val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D);
+	val |= 0x80;
+	i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val);
+
+	/*
+	 * Configure PHY to setup LED's correctly and use 100MBit, FD
+	 */
+	mii_init();
+
+	/* disable auto-negotiation, 100mbit, full-duplex */
+	fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100);
+
+	/* set LED's to Link, Transmit, Receive           */
+	fec8xx_miiphy_write(NULL,  0, PHY_FCSCR, 0x4122);
+
+	return 0;
+}
+
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed (void)
+{
+	return 0;		/* No hotkeys supported */
+}
+#endif
diff --git a/board/utx8245/Makefile b/board/utx8245/Makefile
new file mode 100755
index 0000000..e698afc
--- /dev/null
+++ b/board/utx8245/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Gregory E. Allen, gallen@arlut.utexas.edu
+# Matthew E. Karger, karger@arlut.utexas.edu
+# Applied Research Laboratories, The University of Texas at Austin
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+SOBJS	=
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/utx8245/config.mk b/board/utx8245/config.mk
new file mode 100755
index 0000000..a33faa7
--- /dev/null
+++ b/board/utx8245/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Gregory E. Allen, gallen@arlut.utexas.edu
+# Matthew E. Karger, karger@arlut.utexas.edu
+# Applied Research Laboratories, The University of Texas at Austin
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# UTX8245 boards
+#
+TEXT_BASE = 0xFFF00000
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c
new file mode 100755
index 0000000..3271827
--- /dev/null
+++ b/board/utx8245/flash.c
@@ -0,0 +1,560 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+
+#define ROM_CS0_START	0xFF800000
+#define ROM_CS1_START	0xFF000000
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#define	FLASH_BANK_SIZE	((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
+#define	MAIN_SECT_SIZE 	0x10000
+#define	SECT_SIZE_32KB	0x8000
+#define	SECT_SIZE_8KB	0x2000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+static int write_word (flash_info_t * info, ulong dest, ulong data);
+#if 0
+static void write_via_fpu (vu_long * addr, ulong * data);
+#endif
+static __inline__ unsigned long get_msr (void);
+static __inline__ void set_msr (unsigned long msr);
+
+/*flash command address offsets*/
+#define ADDR0		(0x555)
+#define ADDR1		(0xAAA)
+#define ADDR3		(0x001)
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*---------------------------------------------------------------------*/
+/*#define	DEBUG_FLASH	1 */
+
+/*---------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+	int i;		/* flash bank counter */
+	int j;		/* flash device sector counter */
+	int k;		/* flash size calculation loop counter */
+	int N;		/* pow(2,N) is flash size, but we don't have <math.h> */
+	ulong total_size = 0, device_size = 1;
+	unsigned char manuf_id, device_id;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		vu_char *addr = (vu_char *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+		addr[0x555] = 0xAA;		/* get manuf/device info command */
+		addr[0x2AA] = 0x55;		/* 3-cycle command */
+		addr[0x555] = 0x90;
+
+		manuf_id = addr[0];		/* read back manuf/device info */
+		device_id = addr[1];
+
+		addr[0x55] = 0x98;		/* CFI command */
+		N = addr[0x27];			/* read back device_size = pow(2,N) */
+
+		for (k = 0; k < N; k++)	/* calculate device_size = pow(2,N) */
+			device_size *= 2;
+
+		flash_info[i].size = device_size;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+
+#if defined DEBUG_FLASH
+		printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id);
+#endif
+		/* find out what kind of flash we are using */
+		if ((manuf_id == (uchar) (AMD_MANUFACT))
+			&& (device_id == AMD_ID_LV033C)) {
+			flash_info[i].flash_id =
+					((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) |
+					(FLASH_AM033C & FLASH_TYPEMASK);
+
+			/* set individual sector start addresses */
+			for (j = 0; j < flash_info[i].sector_count; j++) {
+				flash_info[i].start[j] =
+						(CFG_FLASH_BASE + i * FLASH_BANK_SIZE +
+						 j * MAIN_SECT_SIZE);
+			}
+		}
+
+		else if ((manuf_id == (uchar) (AMD_MANUFACT)) &&
+				 (device_id == AMD_ID_LV116DT)) {
+			flash_info[i].flash_id =
+					((FLASH_MAN_AMD & FLASH_VENDMASK) << 16) |
+					(FLASH_AM160T & FLASH_TYPEMASK);
+
+			/* set individual sector start addresses */
+			for (j = 0; j < flash_info[i].sector_count; j++) {
+				flash_info[i].start[j] =
+						(CFG_FLASH_BASE + i * FLASH_BANK_SIZE +
+						 j * MAIN_SECT_SIZE);
+
+				if (j < (CFG_MAX_FLASH_SECT - 3)) {
+					flash_info[i].start[j] =
+							(CFG_FLASH_BASE + i * FLASH_BANK_SIZE +
+							 j * MAIN_SECT_SIZE);
+				} else if (j == (CFG_MAX_FLASH_SECT - 3)) {
+					flash_info[i].start[j] =
+							(flash_info[i].start[j - 1] + SECT_SIZE_32KB);
+
+				} else {
+					flash_info[i].start[j] =
+							(flash_info[i].start[j - 1] + SECT_SIZE_8KB);
+				}
+			}
+		}
+
+		else {
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			addr[0] = 0xFF;
+			goto Done;
+		}
+
+#if defined DEBUG_FLASH
+		printf ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+#endif
+
+		addr[0] = 0xFF;
+
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+
+		total_size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE,
+				   CFG_MONITOR_BASE + monitor_flash_len - 1,
+				   &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+	flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+  Done:
+	return total_size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	static const char unk[] = "Unknown";
+	const char *mfct = unk, *type = unk;
+	unsigned int i;
+
+	if (info->flash_id != FLASH_UNKNOWN) {
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			mfct = "AMD";
+			break;
+		case FLASH_MAN_FUJ:
+			mfct = "FUJITSU";
+			break;
+		case FLASH_MAN_STM:
+			mfct = "STM";
+			break;
+		case FLASH_MAN_SST:
+			mfct = "SST";
+			break;
+		case FLASH_MAN_BM:
+			mfct = "Bright Microelectonics";
+			break;
+		case FLASH_MAN_INTEL:
+			mfct = "Intel";
+			break;
+		}
+
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_AM033C:
+			type = "AM29LV033C (32 Mbit, uniform sector size)";
+			break;
+		case FLASH_AM160T:
+			type = "AM29LV160T (16 Mbit, top boot sector)";
+			break;
+		case FLASH_AM040:
+			type = "AM29F040B (512K * 8, uniform sector size)";
+			break;
+		case FLASH_AM400B:
+			type = "AM29LV400B (4 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM400T:
+			type = "AM29LV400T (4 Mbit, top boot sector)";
+			break;
+		case FLASH_AM800B:
+			type = "AM29LV800B (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM800T:
+			type = "AM29LV800T (8 Mbit, top boot sector)";
+			break;
+		case FLASH_AM320B:
+			type = "AM29LV320B (32 Mbit, bottom boot sect)";
+			break;
+		case FLASH_AM320T:
+			type = "AM29LV320T (32 Mbit, top boot sector)";
+			break;
+		case FLASH_STM800AB:
+			type = "M29W800AB (8 Mbit, bottom boot sect)";
+			break;
+		case FLASH_SST800A:
+			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
+			break;
+		case FLASH_SST160A:
+			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
+			break;
+		}
+	}
+
+	printf ("\n  Brand: %s Type: %s\n"
+			"  Size: %lu KB in %d Sectors\n",
+			mfct, type, info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; i++) {
+		unsigned long size;
+		unsigned int erased;
+		unsigned long *flash = (unsigned long *) info->start[i];
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (i != (info->sector_count - 1)) ?
+				(info->start[i + 1] - info->start[i]) >> 2 :
+				(info->start[0] + info->size - info->start[i]) >> 2;
+
+		for (flash = (unsigned long *) info->start[i], erased = 1;
+			 (flash != (unsigned long *) info->start[i] + size) && erased;
+			 flash++)
+			erased = *flash == ~0x0UL;
+
+		printf ("%s %08lX %s %s",
+				(i % 5) ? "" : "\n   ",
+				info->start[i],
+				erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
+	}
+
+	puts ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+	unsigned char sh8b;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+		(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+		&& (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->
+														   start[sect] -
+														   info->
+														   start[0]) <<
+														  sh8b));
+
+			if (info->flash_id & FLASH_MAN_SST) {
+				addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
+				addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				udelay (30000);	/* wait 30 ms */
+			} else {
+				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			}
+
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last = start;
+	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
+												   info->
+												   start[0]) << sh8b));
+	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
+		   (FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			serial_putc ('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);			/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_word (info, wp, data));
+}
+
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
+	volatile FLASH_WORD_SIZE *dest2;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int flag;
+	int i;
+	unsigned char sh8b;
+
+	/* Check the ROM CS */
+	if ((info->start[0] >= ROM_CS1_START)
+		&& (info->start[0] < ROM_CS0_START))
+		sh8b = 3;
+	else
+		sh8b = 0;
+
+	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
+								 info->start[0]);
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i << sh8b] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
+			   (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+#if 0
+static void write_via_fpu (vu_long * addr, ulong * data)
+{
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+
+	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+}
diff --git a/board/utx8245/u-boot.lds b/board/utx8245/u-boot.lds
new file mode 100755
index 0000000..45f3018
--- /dev/null
+++ b/board/utx8245/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o		(.text)
+    lib_ppc/board.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c
new file mode 100755
index 0000000..834fd84
--- /dev/null
+++ b/board/utx8245/utx8245.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <pci.h>
+
+#define	SAVE_SZ	32
+
+
+int checkboard(void)
+{
+	ulong busfreq  = get_bus_freq(0);
+	char  buf[32];
+
+	printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq));
+	return 0;
+}
+
+
+long int initdram(int board_type)
+{
+	long size;
+	long new_bank0_end;
+	long new_bank1_end;
+	long mear1;
+	long emear1;
+
+	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+
+	new_bank0_end = size/2 - 1;
+	new_bank1_end = size - 1;
+	mear1 = mpc824x_mpc107_getreg(MEAR1);
+	emear1 = mpc824x_mpc107_getreg(EMEAR1);
+
+	mear1 = (mear1  & 0xFFFF0000) |
+		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+		((new_bank1_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT << 8);
+	emear1 = (emear1 & 0xFFFF0000) |
+		((new_bank0_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+		((new_bank1_end & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT << 8);
+
+	mpc824x_mpc107_setreg(MEAR1, mear1);
+	mpc824x_mpc107_setreg(EMEAR1, emear1);
+
+	return (size);
+}
+
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+static struct pci_config_table pci_utx8245_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR,
+				       PCI_FIREWIRE_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+#endif /*CONFIG_PCI_PNP*/
+	{ }
+};
+
+
+static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	if (PCI_DEV(dev) == 11)
+		/* assign serial interrupt line 9 (int25) to FireWire */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25);
+
+	else if (PCI_DEV(dev) == 12)
+		/* assign serial interrupt line 8 (int24) to Ethernet */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24);
+
+	else if (PCI_DEV(dev) == 14)
+		/* assign serial interrupt line 0 (int16) to PMC slot 0 */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16);
+
+	else if (PCI_DEV(dev) == 15)
+		/* assign serial interrupt line 1 (int17) to PMC slot 1 */
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17);
+}
+
+static struct pci_controller utx8245_hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_utx8245_config_table,
+	fixup_irq: pci_utx8245_fixup_irq,
+	write_byte: pci_hose_write_config_byte
+#endif /*CONFIG_PCI_PNP*/
+};
+
+void pci_init_board (void)
+{
+	pci_mpc824x_init(&utx8245_hose);
+
+	icache_enable();
+}
diff --git a/board/v37/Makefile b/board/v37/Makefile
new file mode 100755
index 0000000..7a17067
--- /dev/null
+++ b/board/v37/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/v37/config.mk b/board/v37/config.mk
new file mode 100755
index 0000000..50cac97
--- /dev/null
+++ b/board/v37/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Marel V37 boards
+#
+TEXT_BASE = 0x40000000
diff --git a/board/v37/flash.c b/board/v37/flash.c
new file mode 100755
index 0000000..6a31972
--- /dev/null
+++ b/board/v37/flash.c
@@ -0,0 +1,559 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * Some of flash control words are modified. (from 2x16bit device
+ * to 4x8bit device)
+ * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
+ * are not tested.
+ *
+ * (?) Does an RPXLite board which
+ * 	does not use AM29LV800 flash memory exist ?
+ *	I don't know...
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips);
+static void flash_get_id_word( void *ptr,  short *ptr_manuf, short *ptr_dev_id);
+static void flash_get_id_long( void *ptr,  short *ptr_manuf, short *ptr_dev_id);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	short manu, dev_id;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Do sizing to get full correct info */
+
+	flash_get_id_word((void*)CFG_FLASH_BASE0,&manu,&dev_id);
+
+	size_b0 = flash_get_size(manu, dev_id, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE0, &flash_info[0],0);
+
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (0 - size_b0);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE0
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+	flash_get_id_long((void*)CFG_FLASH_BASE1,&manu,&dev_id);
+
+	size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]);
+
+	flash_get_offsets(CFG_FLASH_BASE1, &flash_info[1],1);
+
+	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (0 - size_b1);
+
+	flash_info[0].size = size_b0;
+	flash_info[1].size = size_b1;
+
+	return (size_b0+size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips)
+{
+	int i, addr_shift;
+	vu_short *addr = (vu_short*)base;
+
+	addr[0x555] = 0x00AA ;
+	addr[0xAAA] = 0x0055 ;
+	addr[0x555] = 0x0090 ;
+
+	addr_shift = (two_chips ? 2 : 1 );
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + (0x00000000<<addr_shift);
+		info->start[1] = base + (0x00002000<<addr_shift);
+		info->start[2] = base + (0x00003000<<addr_shift);
+		info->start[3] = base + (0x00004000<<addr_shift);
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-3) * (0x00008000<<addr_shift)) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - (0x00002000<<addr_shift);
+		info->start[i--] = base + info->size - (0x00003000<<addr_shift);
+		info->start[i--] = base + info->size - (0x00004000<<addr_shift);
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * (0x00008000<<addr_shift);
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (vu_short *)(info->start[i]);
+		info->protect[i] = addr[1<<addr_shift] & 1 ;
+	}
+
+	addr = (vu_short *)info->start[0];
+	*addr = 0xF0F0;	/* reset bank */
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_TOSH:	printf ("TOSHIBA ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static void flash_get_id_word( void *ptr,  short *ptr_manuf, short *ptr_dev_id)
+{
+	vu_short *addr = (vu_short*)ptr;
+
+	addr[0x555] = 0x00AA ;
+	addr[0xAAA] = 0x0055 ;
+	addr[0x555] = 0x0090 ;
+
+	*ptr_manuf  = addr[0];
+	*ptr_dev_id = addr[1];
+
+	addr[0] = 0xf0f0;       /* return to normal */
+}
+
+static void flash_get_id_long( void *ptr,  short *ptr_manuf, short *ptr_dev_id)
+{
+	vu_short *addr = (vu_short*)ptr;
+	vu_short *addr1, *addr2, *addr3;
+
+	addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) );
+	addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) );
+	addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) );
+
+	*addr1 = 0xAAAA;
+	*addr2 = 0x5555;
+	*addr3 = 0x9090;
+
+	*ptr_manuf  = addr[0];
+	*ptr_dev_id = addr[2];
+
+	addr[0] = 0xf0f0;       /* return to normal */
+}
+
+static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info)
+{
+	switch (manu) {
+	case ((short)AMD_MANUFACT):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case ((short)FUJ_MANUFACT):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case ((short)TOSH_MANUFACT):
+		info->flash_id = FLASH_MAN_TOSH;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+
+	switch (dev_id) {
+	case ((short)TOSH_ID_FVT160):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 1 MB		*/
+
+	case ((short)TOSH_ID_FVB160):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 1 MB		*/
+
+	case ((short)AMD_ID_LV400T):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case ((short)AMD_ID_LV400B):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case ((short)AMD_ID_LV800T):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case ((short)AMD_ID_LV800B):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/*%%% Size doubled by yooth */
+		break;				/* => 4 MB		*/
+
+	case ((short)AMD_ID_LV160T):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 4 MB		*/
+
+	case ((short)AMD_ID_LV160B):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 4 MB		*/
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_short *addr = (vu_short*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x555] = (vu_short)0xAAAAAAAA;
+	addr[0xAAA] = (vu_short)0x55555555;
+	addr[0x555] = (vu_short)0x80808080;
+	addr[0x555] = (vu_short)0xAAAAAAAA;
+	addr[0xAAA] = (vu_short)0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_short *)(info->start[sect]) ;
+			addr[0] = (vu_short)0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_short *)(info->start[l_sect]);
+	while ((addr[0] & 0x8080) != 0x8080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_short *)info->start[0];
+	addr[0] = (vu_short)0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_short *addr = (vu_short *)(info->start[0]);
+	vu_short sdata;
+
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* First write upper 16 bits */
+	sdata = (short)(data>>16);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x555] = 0xAAAA;
+	addr[0xAAA] = 0x5555;
+	addr[0x555] = 0xA0A0;
+
+	*((vu_short *)dest) = sdata;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+
+	/* Now write lower 16 bits */
+	sdata = (short)(data&0xffff);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x555] = 0xAAAA;
+	addr[0xAAA] = 0x5555;
+	addr[0x555] = 0xA0A0;
+
+	*((vu_short *)dest + 1) = sdata;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds
new file mode 100755
index 0000000..f9722db
--- /dev/null
+++ b/board/v37/u-boot.lds
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o		(.text)
+    cpu/mpc8xx/traps.o		(.text)
+    common/dlmalloc.o		(.text)
+    lib_ppc/ppcstring.o		(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_ppc/time.o		(.text)
+
+/*
+    . = env_offset;
+*/
+    common/environment.o	(.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/v37/v37.c b/board/v37/v37.c
new file mode 100755
index 0000000..1ef879d
--- /dev/null
+++ b/board/v37/v37.c
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * DRAM related UPMA register values are modified.
+ * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
+ */
+
+#include <common.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (void);
+
+/* ------------------------------------------------------------------------- */
+
+#define MBYTE 		(1024*1024)
+#define DRAM_DELAY  	0x00000379  /* DRAM delay count */
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*  single read. (offset 0 in upm RAM) */
+	0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
+	0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
+
+	/* burst read. (Offset 8 in upm RAM)   */
+	0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
+	0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* single write. (Offset 0x18 in upm RAM) */
+	0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/*  burst write. (Offset 0x20 in upm RAM) */
+	0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
+	0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Refresh cycle, offset 0x30 */
+	0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+	0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* Exception, 0ffset 0x3C */
+	0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Return 1 for now.
+ *
+ */
+
+int checkboard (void)
+{
+	printf("Marel V37\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile memctl8xx_t *memctl = &immap->im_memctl;
+    unsigned long temp;
+    volatile int delay_cnt;
+    long int ramsize;
+
+    ramsize = dram_size();
+
+	/* Refresh clock prescalar */
+    memctl->memc_mptpr = 0x400 ;
+
+    if( ramsize == 32*MBYTE )
+       temp = 0xd0904110;
+   else				/* 16MB */
+       temp = 0xd0802110;
+
+    memctl->memc_mbmr = temp;
+
+    upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Map controller banks 2 to the SDRAM bank */
+    memctl->memc_or2 = 0xA00 | (0 - ramsize);
+    memctl->memc_br2 = 0xC1;
+
+    memctl->memc_mbmr = temp | 0x08;
+    memctl->memc_mcr  = 0x80804130;
+
+    delay_cnt = 0;
+    while( delay_cnt++ < DRAM_DELAY )
+	;
+
+    /* Run MRS command in location 5-8 of UPMB */
+
+    memctl->memc_mbmr = temp | 0x04;
+    memctl->memc_mar  = 0x88;
+
+    memctl->memc_mcr  = 0x80804105;
+
+    delay_cnt = 0;
+    while( delay_cnt++ < DRAM_DELAY )
+	;
+
+#ifdef	CONFIG_CAN_DRIVER
+    /* Initialize OR3 / BR3 */
+    memctl->memc_or3 = CFG_OR3_CAN;
+    memctl->memc_br3 = CFG_BR3_CAN;
+
+    /* Initialize MBMR */
+    memctl->memc_mamr = MAMR_GPL_A4DIS;	/* GPL_A4 ouput line Disable */
+
+    /* Initialize UPMB for CAN: single read */
+    memctl->memc_mdr = 0xFFFFC004;
+    memctl->memc_mcr = 0x0100 | UPMA;
+
+    memctl->memc_mdr = 0x0FFFD004;
+    memctl->memc_mcr = 0x0101 | UPMA;
+
+    memctl->memc_mdr = 0x0FFFC000;
+    memctl->memc_mcr = 0x0102 | UPMA;
+
+    memctl->memc_mdr = 0x3FFFC004;
+    memctl->memc_mcr = 0x0103 | UPMA;
+
+    memctl->memc_mdr = 0xFFFFDC05;
+    memctl->memc_mcr = 0x0104 | UPMA;
+
+    /* Initialize UPMB for CAN: single write */
+    memctl->memc_mdr = 0xFFFCC004;
+    memctl->memc_mcr = 0x0118 | UPMA;
+
+    memctl->memc_mdr = 0xCFFCD004;
+    memctl->memc_mcr = 0x0119 | UPMA;
+
+    memctl->memc_mdr = 0x0FFCC000;
+    memctl->memc_mcr = 0x011A | UPMA;
+
+    memctl->memc_mdr = 0x7FFCC004;
+    memctl->memc_mcr = 0x011B | UPMA;
+
+    memctl->memc_mdr = 0xFFFDCC05;
+    memctl->memc_mcr = 0x011C | UPMA;
+#endif	/* CONFIG_CAN_DRIVER */
+
+    return (dram_size());
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Find size of RAM from configuration pins.
+ * The input pins that contain the memory size are also the debug port
+ * pins.  Normally they are configured as debug port pins.  To be able
+ * to read the memory configuration, we must deactivate the debug port
+ * and enable the pcmcia input pins.  Then return the register to
+ * previous state.
+ */
+
+static long int dram_size ()
+{
+    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile sysconf8xx_t *siu = &immap->im_siu_conf;
+    volatile pcmconf8xx_t *pcm = &immap->im_pcmcia;
+    long int		  i, memory=1;
+    unsigned long siu_mcr;
+
+    siu_mcr = siu->sc_siumcr;
+    siu->sc_siumcr = siu_mcr & 0xFF9FFFFF;
+    for(i=0; i<10; i++) i = i;
+
+    memory = (pcm->pcmc_pipr>>12) & 0x3;
+
+    siu->sc_siumcr = siu_mcr;
+
+    switch( memory )
+    {
+	case 1:
+	    return( 32*MBYTE );
+	case 2:
+	    return( 64*MBYTE );
+	default:
+	    break;
+    }
+    return( 16*MBYTE );
+}
diff --git a/board/versatile/Makefile b/board/versatile/Makefile
new file mode 100755
index 0000000..fbdc627
--- /dev/null
+++ b/board/versatile/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= versatile.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/versatile/config.mk b/board/versatile/config.mk
new file mode 100755
index 0000000..25b79b3
--- /dev/null
+++ b/board/versatile/config.mk
@@ -0,0 +1,5 @@
+#
+# image should be loaded at 0x01000000
+#
+
+TEXT_BASE = 0x01000000
diff --git a/board/versatile/flash.c b/board/versatile/flash.c
new file mode 100755
index 0000000..7153371
--- /dev/null
+++ b/board/versatile/flash.c
@@ -0,0 +1,514 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)			__swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)			__swab32(x)
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+	unsigned int sector_number;
+	unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256K3[] = {
+	{256, 128 * 1024},		/* 256 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_vpp(int on)
+{
+	unsigned int tmp;
+
+	tmp = *(unsigned int *)(VERSATILE_FLASHCTRL);
+
+	if (on)
+	    tmp |= VERSATILE_FLASHPROG_FLVPPEN;
+	else
+    	    tmp &= ~VERSATILE_FLASHPROG_FLVPPEN;
+
+	*(unsigned int *)(VERSATILE_FLASHCTRL) = tmp;
+}
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+		        flash_vpp(1);
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			flash_vpp(0);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+	OrgDef *pOrgDef;
+
+	pOrgDef = OrgIntel_28F256K3;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			if (i > 255) {
+				info->start[i] = base + (i * 0x8000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base +
+						(i * PHYS_FLASH_SECT_SIZE);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F256L18T:
+		printf ("FLASH 28F256L18T\n");
+		break;
+	case FLASH_28F256K3:
+		printf ("FLASH 28F256K3\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);		/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID        */
+	switch (value) {
+
+	case (FPW) (INTEL_ID_28F256L18T):
+		info->flash_id += FLASH_28F256L18T;
+		info->sector_count = 259;
+		info->size = 0x02000000;
+		break;			/* => 32 MB     */
+
+	case (FPW)(INTEL_ID_28F256K3):
+		info->flash_id += FLASH_28F256K3;
+		info->sector_count = 256;
+		info->size = 0x02000000;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK    0x0080
+
+	*addr = (FPW) 0x00500050;	/* clear status register */
+
+	/* this sends the clear lock bit command */
+	*addr = (FPW) 0x00600060;
+	*addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+				info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	flash_vpp(1);
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			flash_unprotect_sectors (addr);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;/* clear status register */
+			*addr = (FPW) 0x00200020;/* erase setup */
+			*addr = (FPW) 0x00D000D0;/* erase confirm */
+
+			while (((status =
+				*addr) & (FPW) 0x00800080) !=
+				(FPW) 0x00800080) {
+					if (get_timer_masked () >
+					CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					/* suspend erase     */
+					*addr = (FPW) 0x00B000B0;
+					/* reset to read mode */
+					*addr = (FPW) 0x00FF00FF;
+					rcode = 1;
+					break;
+				}
+			}
+
+			/* clear status register cmd.   */
+			*addr = (FPW) 0x00500050;
+			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
+			printf (" done\n");
+		}
+	}
+
+	flash_vpp(0);
+
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	flash_vpp(1);
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			flash_vpp(0);
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			flash_vpp(0);
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		flash_vpp(0);
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	rc = write_data (info, wp, SWAP (data));
+
+	flash_vpp(0);
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+
+	flash_vpp(1);
+
+	flash_unprotect_sectors (addr);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			flash_vpp(0);
+			return (1);
+		}
+	}
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+	flash_vpp(0);
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/versatile/lowlevel_init.S b/board/versatile/lowlevel_init.S
new file mode 100755
index 0000000..bdfce2d
--- /dev/null
+++ b/board/versatile/lowlevel_init.S
@@ -0,0 +1,34 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+
+	/* All done by Versatile's boot monitor! */
+	mov pc, lr
diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh
new file mode 100755
index 0000000..35c663e
--- /dev/null
+++ b/board/versatile/split_by_variant.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+# ---------------------------------------------------------
+#  Set the core module defines according to Core Module
+# ---------------------------------------------------------
+# ---------------------------------------------------------
+# Set up the Versatile type define
+# ---------------------------------------------------------
+variant=PB926EJ-S
+if [ "$1" == "" ]
+then
+	echo "$0:: No parameters - using versatilepb_config"
+	echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+	variant=PB926EJ-S
+else
+	case "$1" in
+	versatilepb_config	|	\
+	versatile_config)
+	echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+	;;
+
+	versatileab_config)
+	echo "#define CONFIG_ARCH_VERSATILE_AB" > ./include/config.h
+	variant=AB926EJ-S
+	;;
+
+
+	*)
+	echo "$0:: Unrecognised config - using versatilepb_config"
+	echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h
+	variant=PB926EJ-S
+	;;
+
+	esac
+
+fi
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+./mkconfig -a versatile arm arm926ejs versatile
+echo "Variant:: $variant"
diff --git a/board/versatile/u-boot.lds b/board/versatile/u-boot.lds
new file mode 100755
index 0000000..cb6ee18
--- /dev/null
+++ b/board/versatile/u-boot.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c
new file mode 100755
index 0000000..0274027
--- /dev/null
+++ b/board/versatile/versatile.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void flash__init (void);
+void ether__init (void);
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+    printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+static inline void delay (unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+
+	/*
+	 * set clock frequency:
+	 *	VERSATILE_REFCLK is 32KHz
+	 *	VERSATILE_TIMCLK is 1MHz
+	 */
+	*(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
+	  ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
+	   (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
+
+	/* arch number of Versatile Board */
+	gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	gd->flags = 0;
+
+	icache_enable ();
+
+	flash__init ();
+	ether__init ();
+	return 0;
+}
+
+
+int misc_init_r (void)
+{
+	setenv("verify", "n");
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+	  		   for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	return 0;
+}
diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile
new file mode 100755
index 0000000..6302fa8
--- /dev/null
+++ b/board/voiceblue/Makefile
@@ -0,0 +1,66 @@
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# (C) Copyright 2005
+# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= voiceblue.o
+SOBJS	:= setup.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds
+
+all:	$(LIB) eeprom.srec eeprom.bin
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+eeprom.srec:	eeprom.o eeprom_start.o
+	$(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \
+		-o $(<:.o=) -e $(<:.o=) $^ \
+		-L../../examples -lstubs \
+		-L../../lib_generic -lgeneric \
+		-L$(gcclibdir) -lgcc
+	$(OBJCOPY) -O srec $(<:.o=) $@
+
+eeprom.bin:	eeprom.srec
+	$(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null
+
+clean:
+	rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin
+
+distclean:	clean
+	rm -f $(LIB) core config.tmp *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/voiceblue/config.mk b/board/voiceblue/config.mk
new file mode 100755
index 0000000..c73cd27
--- /dev/null
+++ b/board/voiceblue/config.mk
@@ -0,0 +1,16 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifeq ($(VOICEBLUE_SMALL_FLASH),y)
+# We load ourself to internal SRAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+TEXT_BASE = 0x20012000
+else
+# Running in SDRAM...
+TEXT_BASE = 0x13000000
+endif
diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c
new file mode 100755
index 0000000..0ad1b66
--- /dev/null
+++ b/board/voiceblue/eeprom.c
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Some code shamelessly stolen back from Robin Getz.
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <exports.h>
+#include "../drivers/smc91111.h"
+
+#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
+
+static u16 read_eeprom_reg(u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(2);
+	SMC_outw(reg, PTR_REG);
+
+	SMC_SELECT_BANK(1);
+	SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
+		 CTL_REG);
+	timeout = 100;
+	while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+		udelay(100);
+	if (timeout == 0) {
+		printf("Timeout Reading EEPROM register %02x\n", reg);
+		return 0;
+	}
+
+	return SMC_inw (GP_REG);
+}
+
+static int write_eeprom_reg(u16 value, u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(2);
+	SMC_outw(reg, PTR_REG);
+
+	SMC_SELECT_BANK(1);
+	SMC_outw(value, GP_REG);
+	SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+	timeout = 100;
+	while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout)
+		udelay (100);
+	if (timeout == 0) {
+		printf("Timeout Writing EEPROM register %02x\n", reg);
+		return 0;
+	}
+
+	return 1;
+}
+
+static int write_data(u16 *buf, int len)
+{
+	u16 reg = 0x23;
+
+	while (len--)
+		write_eeprom_reg(*buf++, reg++);
+
+	return 0;
+}
+
+static int verify_macaddr(char *s)
+{
+	u16 reg;
+	int i, err = 0;
+
+	printf("MAC Address: ");
+	err = i = 0;
+	for (i = 0; i < 3; i++) {
+		reg = read_eeprom_reg(0x20 + i);
+		printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
+		if (s)
+			err |= reg != ((u16 *)s)[i];
+	}
+
+	return err ? 0 : 1;
+}
+
+static int set_mac(char *s)
+{
+	int i;
+	char *e, eaddr[6];
+
+	/* turn string into mac value */
+	for (i = 0; i < 6; i++) {
+		eaddr[i] = simple_strtoul(s, &e, 16);
+		s = (*e) ? e+1 : e;
+	}
+
+	for (i = 0; i < 3; i++)
+		write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+
+	return 0;
+}
+
+static int parse_element(char *s, unsigned char *buf, int len)
+{
+	int cnt;
+	char *p, num[3];
+	unsigned char id;
+
+	id = simple_strtoul(s, &p, 16);
+	if (*p++ != ':')
+		return -1;
+	cnt = 2;
+	num[2] = 0;
+	for (; *p; p += 2) {
+		if (p[1] == 0)
+			return -2;
+		if (cnt + 3 > len)
+			return -3;
+		num[0] = p[0];
+		num[1] = p[1];
+		buf[cnt++] = simple_strtoul(num, NULL, 16);
+	}
+	buf[0] = id;
+	buf[1] = cnt - 2;
+
+	return cnt;
+}
+
+int eeprom(int argc, char *argv[])
+{
+	int i, len, ret;
+	unsigned char buf[58], *p;
+
+	app_startup(argv);
+	if (get_version() != XF_VERSION) {
+		printf("Wrong XF_VERSION.\n");
+		printf("Application expects ABI version %d\n", XF_VERSION);
+		printf("Actual U-Boot ABI version %d\n", (int)get_version());
+		return 1;
+	}
+
+	if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+		printf("SMSC91111 not found.\n");
+		return 2;
+	}
+
+	/* Called without parameters - print MAC address */
+	if (argc < 2) {
+		verify_macaddr(NULL);
+		return 0;
+	}
+
+	/* Print help message */
+	if (argv[1][1] == 'h') {
+		printf("VoiceBlue EEPROM writer\n");
+		printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+		printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
+		return 0;
+	}
+
+	/* Try to parse information elements */
+	len = sizeof(buf);
+	p = buf;
+	for (i = 2; i < argc; i++) {
+		ret = parse_element(argv[i], p, len);
+		switch (ret) {
+		case -1:
+			printf("Element %d: malformed\n", i - 1);
+			return 3;
+		case -2:
+			printf("Element %d: odd character count\n", i - 1);
+			return 3;
+		case -3:
+			printf("Out of EEPROM memory\n");
+			return 3;
+		default:
+			p += ret;
+			len -= ret;
+		}
+	}
+
+	/* First argument (MAC) is mandatory */
+	set_mac(argv[1]);
+	if (verify_macaddr(argv[1])) {
+		printf("*** MAC address does not match! ***\n");
+		return 4;
+	}
+
+	while (len--)
+		*p++ = 0;
+
+	write_data((u16 *)buf, sizeof(buf) >> 1);
+
+	return 0;
+}
diff --git a/board/voiceblue/eeprom.lds b/board/voiceblue/eeprom.lds
new file mode 100755
index 0000000..317550d
--- /dev/null
+++ b/board/voiceblue/eeprom.lds
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = ALIGN(4);
+	.text      :
+	{
+	  eeprom_start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/voiceblue/eeprom_start.S b/board/voiceblue/eeprom_start.S
new file mode 100755
index 0000000..8f88de5
--- /dev/null
+++ b/board/voiceblue/eeprom_start.S
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2005  2N Telekomunikace
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ */
+
+.globl	_start
+_start:	b	eeprom
diff --git a/board/voiceblue/setup.S b/board/voiceblue/setup.S
new file mode 100755
index 0000000..dcf37b5
--- /dev/null
+++ b/board/voiceblue/setup.S
@@ -0,0 +1,280 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
+ * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* SDRAM load addr from config.mk */
+
+OMAP5910_LPG1_BASE:		.word 0xfffbd000
+OMAP5910_TIPB_SWITCHES_BASE:	.word 0xfffbc800
+OMAP5910_MPU_TC_BASE:		.word 0xfffecc00
+OMAP5910_MPU_CLKM_BASE:		.word 0xfffece00
+OMAP5910_ULPD_PWR_MNG_BASE:	.word 0xfffe0800
+OMAP5910_DPLL1_BASE:		.word 0xfffecf00
+OMAP5910_GPIO_BASE:		.word 0xfffce000
+OMAP5910_MPU_WD_TIMER_BASE:	.word 0xfffec800
+OMAP5910_MPUI_BASE:		.word 0xfffec900
+
+_OMAP5910_ARM_CKCTL:		.word OMAP5910_ARM_CKCTL
+_OMAP5910_ARM_EN_CLK:		.word OMAP5910_ARM_EN_CLK
+
+OMAP5910_MPUI_CTRL:		.word 0x0000ff1b
+
+VAL_EMIFS_CS0_CONFIG:		.word 0x00009090
+VAL_EMIFS_CS1_CONFIG:		.word 0x00003031
+VAL_EMIFS_CS2_CONFIG:		.word 0x00003031
+VAL_EMIFS_CS3_CONFIG:		.word 0x0000c0c0
+VAL_EMIFS_DYN_WAIT:		.word 0x00000000
+/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
+				/*     SLRF       SD_RET     ARE        SDRAM_TYPE   ARCV           SDRAM_FREQUENCY PWD     CLK */
+VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
+VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003
+VAL_EMIFF_MRS:			.word 0x00000037
+
+/*
+ * GPIO04 - D4 (Onboard LED)
+ * GPIO07 - LAN91C111 reset
+ */
+GPIO_DIRECTION:
+	.word 0x0000ff6f
+/*
+ * Disable everything, but D4 LED (connected through invertor)
+ */
+GPIO_OUTPUT:
+	.word 0x00000010
+
+MUX_CONFIG_BASE:
+	.word 0xfffe1000
+
+MUX_CONFIG_VALUES:
+	.align 4
+	.word 0x00000000	@ FUNC_MUX_CTRL_0
+	.word 0x00000000	@ FUNC_MUX_CTRL_1
+	.word 0x00000000	@ FUNC_MUX_CTRL_2
+	.word 0x00000000	@ FUNC_MUX_CTRL_3
+	.word 0x00000000	@ FUNC_MUX_CTRL_4
+	.word 0x12082480	@ FUNC_MUX_CTRL_5
+	.word 0x00000004	@ FUNC_MUX_CTRL_6
+	.word 0x00000003	@ FUNC_MUX_CTRL_7
+	.word 0x10001200	@ FUNC_MUX_CTRL_8
+	.word 0x01201012	@ FUNC_MUX_CTRL_9
+	.word 0x02081248	@ FUNC_MUX_CTRL_A
+	.word 0x00001248	@ FUNC_MUX_CTRL_B
+	.word 0x12240000	@ FUNC_MUX_CTRL_C
+	.word 0x00002000	@ FUNC_MUX_CTRL_D
+	.word 0x00000000	@ PULL_DWN_CTRL_0
+	.word 0x0000085f	@ PULL_DWN_CTRL_1
+	.word 0x01001000	@ PULL_DWN_CTRL_2
+	.word 0x00000000	@ PULL_DWN_CTRL_3
+	.word 0x00000000	@ GATE_INH_CTRL_0
+	.word 0x00000000	@ VOLTAGE_CTRL_0
+	.word 0x00000000	@ TEST_DBG_CTRL_0
+	.word 0x00000006	@ MOD_CONF_CTRL_0
+	.word 0x0000eaef	@ COMP_MODE_CTRL_0
+
+MUX_CONFIG_OFFSETS:
+	.align 1
+	.byte 0x00		@ FUNC_MUX_CTRL_0
+	.byte 0x04		@ FUNC_MUX_CTRL_1
+	.byte 0x08		@ FUNC_MUX_CTRL_2
+	.byte 0x10		@ FUNC_MUX_CTRL_3
+	.byte 0x14		@ FUNC_MUX_CTRL_4
+	.byte 0x18		@ FUNC_MUX_CTRL_5
+	.byte 0x1c		@ FUNC_MUX_CTRL_6
+	.byte 0x20		@ FUNC_MUX_CTRL_7
+	.byte 0x24		@ FUNC_MUX_CTRL_8
+	.byte 0x28		@ FUNC_MUX_CTRL_9
+	.byte 0x2c		@ FUNC_MUX_CTRL_A
+	.byte 0x30		@ FUNC_MUX_CTRL_B
+	.byte 0x34		@ FUNC_MUX_CTRL_C
+	.byte 0x38		@ FUNC_MUX_CTRL_D
+	.byte 0x40		@ PULL_DWN_CTRL_0
+	.byte 0x44		@ PULL_DWN_CTRL_1
+	.byte 0x48		@ PULL_DWN_CTRL_2
+	.byte 0x4c		@ PULL_DWN_CTRL_3
+	.byte 0x50		@ GATE_INH_CTRL_0
+	.byte 0x60		@ VOLTAGE_CTRL_0
+	.byte 0x70		@ TEST_DBG_CTRL_0
+	.byte 0x80		@ MOD_CONF_CTRL_0
+	.byte 0x0c		@ COMP_MODE_CTRL_0
+	.byte 0xff
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Improve performance a bit... */
+	mrc	p15, 0, r1, c0, c0, 0		@ read C15 ID register
+	mrc	p15, 0, r1, c0, c0, 1		@ read C15 Cache information register
+	mrc	p15, 0, r1, c1, c0, 0		@ read C15 Control register
+	orr	r1, r1, #0x1000			@ enable I-cache, map interrupt vector 0xffff0000
+	mcr	p15, 0, r1, c1, c0, 0		@ write C15 Control register
+	mov	r1, #0x00
+	mcr	p15, 0, r1, c7, c5, 0		@ Flush I-cache
+	nop
+	nop
+	nop
+	nop
+
+	/* Setup clocking mode */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ prepare base of CLOCK unit
+	ldrh	r1, [r0, #0x18]			@ get reset status
+	bic	r1, r1, #(7 << 11)		@ clear clock select
+	orr	r1, r1, #(2 << 11)		@ set synchronous scalable
+	mov	r2, #0				@ set wait counter to 100 clock cycles
+
+icache_loop:
+	cmp	r2, #0x01
+	streqh	r1, [r0, #0x18]
+	add	r2, r2, #0x01
+	cmp	r2, #0x10
+	bne	icache_loop
+	nop
+
+	/* Setup clock divisors */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	ldr	r1, _OMAP5910_ARM_CKCTL
+	orr	r1, r1, #0x2000			@ enable DSP clock
+	strh	r1, [r0, #0x00]			@ setup clock divisors
+
+	/* Setup DPLL to generate requested freq */
+	ldr	r0, OMAP5910_DPLL1_BASE		@ base of DPLL1 register
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	orr	r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+	orr	r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+	strh	r1, [r0]			@ write
+
+locking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #0x01
+	beq	locking				@ while LOCK not set
+
+	/* Enable clock */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	mov	r1, #(1 << 10)			@ disable idle mode do not check
+						@ nWAKEUP pin, other remain active
+	strh	r1, [r0, #0x04]
+	ldr	r1, _OMAP5910_ARM_EN_CLK
+	strh	r1, [r0, #0x08]
+	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
+						@ max delayed ( 32 x CLKIN )
+	strh	r1, [r0, #0x0c]
+
+	/* Configure 5910 pins functions to match our board. */
+	ldr     r0, MUX_CONFIG_BASE
+	adr	r1, MUX_CONFIG_VALUES
+	adr	r2, MUX_CONFIG_OFFSETS
+next_mux_cfg:
+	ldrb	r3, [r2], #1
+	ldr	r4, [r1], #4
+	cmp	r3, #0xff
+	strne	r4, [r0, r3]
+	bne	next_mux_cfg
+
+	/* Configure GPIO pins (also enables onboard LED) */
+	ldr	r0, OMAP5910_GPIO_BASE
+	ldr	r1, GPIO_OUTPUT
+	strh    r1, [r0, #0x04]
+	ldr	r1, GPIO_DIRECTION
+	strh	r1, [r0, #0x08]
+
+	/* EnablePeripherals */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ CLOCK unit
+	mov	r1, #0x0001			@ Peripheral enable
+	strh	r1, [r0, #0x14]
+
+	/* Program LED Pulse Generator */
+	ldr	r0, OMAP5910_LPG1_BASE		@ 1st LED Pulse Generator
+	mov	r1, #0x7F			@ Set obscure frequency in
+	strb	r1, [r0, #0x00]			@ LCR
+	mov	r1, #0x01			@ Enable clock (CLK_EN) in
+	strb    r1, [r0, #0x04]			@ PMR
+
+	/* TIPB Lock UART1 */
+	ldr	r0, OMAP5910_TIPB_SWITCHES_BASE	@ prepare base of TIPB switches
+	mov	r1, #1				@ ARM allocated
+	strh	r1, [r0,#0x04]			@ clear IRQ line and status bits
+	strh	r1, [r0,#0x00]
+	ldrh	r1, [r0,#0x04]
+
+	/* Disable watchdog */
+	ldr	r0, OMAP5910_MPU_WD_TIMER_BASE
+	mov	r1, #0xf5
+	strh	r1, [r0, #0x8]
+	mov	r1, #0xa0
+	strh	r1, [r0, #0x8]
+
+	/* Enable MCLK */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE
+	mov	r1, #0x6
+	strh	r1, [r0, #0x34]
+	strh	r1, [r0, #0x34]
+
+	/* Setup clock divisors */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register
+
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	strh	r1, [r0]			@ write
+
+ulocking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #1
+	beq	ulocking			@ while LOCK not set
+
+	/* EMIF init */
+	ldr	r0, OMAP5910_MPU_TC_BASE
+	ldrh	r1, [r0, #0x0c]			@ EMIFS_CONFIG_REG
+	bic	r1, r1, #0x0c			@ pwr down disabled, flash WP
+	orr	r1, r1, #0x01
+	str	r1, [r0, #0x0c]
+
+	ldr	r1, VAL_EMIFS_CS0_CONFIG
+	str	r1, [r0, #0x10]			@ EMIFS_CS0_CONFIG
+	ldr	r1, VAL_EMIFS_CS1_CONFIG
+	str	r1, [r0, #0x14]			@ EMIFS_CS1_CONFIG
+	ldr	r1, VAL_EMIFS_CS2_CONFIG
+	str	r1, [r0, #0x18]			@ EMIFS_CS2_CONFIG
+	ldr	r1, VAL_EMIFS_CS3_CONFIG
+	str	r1, [r0, #0x1c]			@ EMIFS_CS3_CONFIG
+	ldr	r1, VAL_EMIFS_DYN_WAIT
+	str	r1, [r0, #0x40]			@ EMIFS_CFG_DYN_WAIT
+
+	/* Setup SDRAM */
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG
+	str	r1, [r0, #0x20]			@ EMIFF_SDRAM_CONFIG
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG2
+	str	r1, [r0, #0x3c]			@ EMIFF_SDRAM_CONFIG2
+	ldr	r1, VAL_EMIFF_MRS
+	str	r1, [r0, #0x24]			@ EMIFF_MRS
+	/* SDRAM needs 100us to stabilize */
+	mov	r0, #0x4000
+sdelay:
+	subs	r0, r0, #0x1
+	bne 	sdelay
+
+	/* back to arch calling code */
+	mov	pc, lr
+.end
diff --git a/board/voiceblue/u-boot.lds b/board/voiceblue/u-boot.lds
new file mode 100755
index 0000000..f35a3ab
--- /dev/null
+++ b/board/voiceblue/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm925t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c
new file mode 100755
index 0000000..7a2d243
--- /dev/null
+++ b/board/voiceblue/voiceblue.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa;
+
+	/* arch number of VoiceBlue board */
+	/* TODO: use define from asm/mach-types.h */
+	gd->bd->bi_arch_number = 218;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff;
+
+ 	/* Take the Ethernet controller out of reset and wait
+ 	 * for the EEPROM load to complete. */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
+	udelay(10);	/* doesn't work before interrupt_init call */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
+	udelay(500);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00;
+
+	return 0;
+}
diff --git a/board/w7o/Makefile b/board/w7o/Makefile
new file mode 100755
index 0000000..d008f89
--- /dev/null
+++ b/board/w7o/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \
+	  watchdog.o
+SOBJS	= init.o post1.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c
new file mode 100755
index 0000000..449089e
--- /dev/null
+++ b/board/w7o/cmd_vpd.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+#include "vpd.h"
+
+/* ======================================================================
+ * Interpreter command to retrieve board specific Vital Product Data, "VPD"
+ * ======================================================================
+ */
+int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	VPD vpd;			/* Board specific data struct */
+	uchar dev_addr = CFG_DEF_EEPROM_ADDR;
+
+	/* Validate usage */
+	if (argc > 2) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	/* Passed in EEPROM address */
+	if (argc == 2)
+		dev_addr = (uchar) simple_strtoul (argv[1], NULL, 16);
+
+	/* Read VPD and output it */
+	if (!vpd_get_data (dev_addr, &vpd)) {
+		vpd_print (&vpd);
+		return 0;
+	}
+
+	return 1;
+}
+
+U_BOOT_CMD(
+	  vpd,	2,	1,	do_vpd,
+	  "vpd     - Read Vital Product Data\n",
+	  "[dev_addr]\n"
+	  "        - Read VPD Data from default address, or device address 'dev_addr'.\n"
+);
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_BSP) */
diff --git a/board/w7o/config.mk b/board/w7o/config.mk
new file mode 100755
index 0000000..bc341ca
--- /dev/null
+++ b/board/w7o/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2001
+# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Wave 7 Optics boards
+#
+
+#TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
+
+#PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARD)
diff --git a/board/w7o/errors.h b/board/w7o/errors.h
new file mode 100755
index 0000000..05b4eae
--- /dev/null
+++ b/board/w7o/errors.h
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ERRORS_H_
+#define _ERRORS_H_
+
+#define ERR_FF		-1	/* led test value(2) */
+#define ERR_00		0x0000	/* led test value(2) */
+#define ERR_LED		0x01	/* led test failed (1)(3)(4) */
+#define ERR_RAMG	0x04	/* start SDRAM data bus test (2) */
+#define ERR_RAML	0x05	/* SDRAM data bus fault in LSW chip (5) */
+#define ERR_RAMH	0x06	/* SDRAM data bus fault in MSW chip (6) */
+#define ERR_RAMB	0x07	/* SDRAM data bus fault both chips (5)(6)(7) */
+#define ERR_ADDG	0x08	/* start Address ghosting test (13) */
+#define ERR_ADDF	0x09	/* fault during Address ghosting test (13) */
+#define ERR_POST1	0x0a	/* post1 tests complete */
+#define ERR_TMP1	0x0b	/* */
+#define ERR_R55G	0x0c	/* start SDRAM fill 55 test (2) */
+#define ERR_R55L	0x0d	/* SDRAM fill test 55 failed in LSW chip (8) */
+#define ERR_R55H	0x0e	/* SDRAM fill test 55 failed in MSW chip (9) */
+#define ERR_R55B	0x0f	/* SDRAM fill test 55 fail in both chips (10) */
+#define ERR_RAAG	0x10	/* start SDRAM fill aa test (2) */
+#define ERR_RAAL	0x11	/* SDRAM fill test aa failed in LSW chip (8) */
+#define ERR_RAAH	0x12	/* SDRAM fill test aa failed in MSW chip (9) */
+#define ERR_RAAB	0x13	/* SDRAM fill test aa fail in both chips (10) */
+#define ERR_R00G	0x14	/* start SDRAM fill 00 test (2) */
+#define ERR_R00L	0x15	/* SDRAM fill test 00 failed in LSW chip (8) */
+#define ERR_R00H	0x16	/* SDRAM fill test 00 failed in MSW chip (9) */
+#define ERR_R00B	0x17	/* SDRAM fill test 00 fail in both chips (10) */
+#define ERR_RTCG	0x18	/* start RTC test */
+#define ERR_RTCBAT	0x19	/* RTC battery failure */
+#define ERR_RTCTIM	0x1A	/* RTC invalid time/date values */
+#define ERR_RTCVAL	0x1B	/* RTC NVRAM not accessable */
+#define ERR_FPGAG	0x20	/* fault during FPGA programming */
+#define ERR_XRW1	0x21	/* Xilinx - can't read/write regs on FPGA 1 */
+#define ERR_XRW2	0x22	/* Xilinx - can't read/write regs on FPGA 2 */
+#define ERR_XRW3	0x23	/* Xilinx - can't read/write regs on FPGA 3 */
+#define ERR_XRW4	0x24	/* Xilinx - can't read/write regs on FPGA 4 */
+#define ERR_XRW5	0x25	/* Xilinx - can't read/write regs on FPGA 5 */
+#define ERR_XRW6	0x26	/* Xilinx - can't read/write regs on FPGA 6 */
+#define ERR_XINIT0	0x27	/* Xilinx - INIT line failed to go low */
+#define ERR_XINIT1	0x28	/* Xilinx - INIT line failed to go high */
+#define ERR_XDONE1	0x29	/* Xilinx - DONE line failed to go high */
+#define ERR_XIMAGE	0x2A	/* Xilinx - Bad FPGA image in Flash */
+#define ERR_TempG	0x2b	/* start temp sensor tests */
+#define ERR_Tinit0	0x2C	/* temp sensor 0 failed to init */
+#define ERR_Tinit1	0x2D	/* temp sensor 1 failed to init */
+#define ERR_Ttest0	0x2E	/* temp sensor 0 failed test */
+#define ERR_Ttest1	0x2F	/* temp sensor 1 failed test */
+#define ERR_lm75r	0x30	/* temp sensor read failure */
+#define ERR_lm75w	0x31	/* temp sensor write failure */
+
+
+#define ERR_POSTOK	0x55	/* PANIC: psych... OK */
+
+#if !defined(__ASSEMBLY__)
+extern void log_stat(int errcode);
+extern void log_warn(int errcode);
+extern void log_err(int errcode);
+#endif
+
+/*
+Debugging suggestions:
+(1) periferal data bus shorted or crossed
+(2) general processor halt, check reset, watch dog, power supply ripple, processor clock.
+(3) check p_we, p_r/w, p_oe, p_rdy lines.
+(4) check LED buffers
+(5) check SDRAM data bus bits 16-31, check LSW SDRAM chip.
+(6) check SDRAM data bus bits 0-15, check MSW SDRAM chip.
+(7) check SDRAM control lines and clocks
+(8) check decoupling caps, replace LSW SDRAM
+(9) check decoupling caps, replace MSW SDRAM
+(10)
+(11)
+(12)
+(13) SDRAM address shorted or unconnected, check sdram caps
+*/
+#endif /* _ERRORS_H_ */
diff --git a/board/w7o/flash.c b/board/w7o/flash.c
new file mode 100755
index 0000000..32815fb
--- /dev/null
+++ b/board/w7o/flash.c
@@ -0,0 +1,940 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *  Based on code by:
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+#include <watchdog.h>
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word8(flash_info_t *info, ulong dest, ulong data);
+static int write_word32 (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+    int i;
+    unsigned long size_b0, base_b0;
+    unsigned long size_b1, base_b1;
+
+    /* Init: no FLASHes known */
+    for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	flash_info[i].flash_id = FLASH_UNKNOWN;
+    }
+
+    /* Get Size of Boot and Main Flashes */
+    size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+    if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+	printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+	    size_b0, size_b0<<20);
+	return 0;
+    }
+    size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+    if (flash_info[1].flash_id == FLASH_UNKNOWN) {
+	printf ("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+	    size_b1, size_b1<<20);
+	return 0;
+    }
+
+    /* Calculate base addresses */
+    base_b0 = -size_b0;
+    base_b1 = -size_b1;
+
+    /* Setup offsets for Boot Flash */
+    flash_get_offsets (base_b0, &flash_info[0]);
+
+    /* Protect board level data */
+    (void)flash_protect(FLAG_PROTECT_SET,
+			base_b0,
+			flash_info[0].start[1] - 1,
+			&flash_info[0]);
+
+
+    /* Monitor protection ON by default */
+    (void)flash_protect(FLAG_PROTECT_SET,
+			base_b0 + size_b0 - monitor_flash_len,
+			base_b0 + size_b0 - 1,
+			&flash_info[0]);
+
+    /* Protect the FPGA image */
+    (void)flash_protect(FLAG_PROTECT_SET,
+			FLASH_BASE1_PRELIM,
+			FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN - 1,
+			&flash_info[1]);
+
+    /* Protect the default boot image */
+    (void)flash_protect(FLAG_PROTECT_SET,
+			FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN,
+			FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN + 0x600000 - 1,
+			&flash_info[1]);
+
+    /* Setup offsets for Main Flash */
+    flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[1]);
+
+    return (size_b0 + size_b1);
+} /* end flash_init() */
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+    int i;
+
+    /* set up sector start address table - FOR BOOT ROM ONLY!!! */
+    if ((info->flash_id & FLASH_TYPEMASK)  == FLASH_AM040) {
+	for (i = 0; i < info->sector_count; i++)
+	    info->start[i] = base + (i * 0x00010000);
+    }
+} /* end flash_get_offsets() */
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+    int i;
+    int k;
+    int size;
+    int erased;
+    volatile unsigned long *flash;
+
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("missing or unknown FLASH type\n");
+	return;
+    }
+
+    switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:     printf ("1 x AMD ");    break;
+	case FLASH_MAN_STM:	printf ("1 x STM ");	break;
+	case FLASH_MAN_INTEL:   printf ("2 x Intel ");  break;
+	default:                printf ("Unknown Vendor ");
+    }
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+	    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		printf ("AM29LV040 (4096 Kbit, uniform sector size)\n");
+	    else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM)
+		printf ("M29W040B (4096 Kbit, uniform block size)\n");
+	    else
+		printf ("UNKNOWN 29x040x (4096 Kbit, uniform sector size)\n");
+	    break;
+	case FLASH_28F320J3A:
+	    printf ("28F320J3A (32 Mbit = 128K x 32)\n");
+	    break;
+	case FLASH_28F640J3A:
+	    printf ("28F640J3A (64 Mbit = 128K x 64)\n");
+	    break;
+	case FLASH_28F128J3A:
+	    printf ("28F128J3A (128 Mbit = 128K x 128)\n");
+	    break;
+	default:
+	    printf ("Unknown Chip Type\n");
+    }
+
+    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
+	printf ("  Size: %ld KB in %d Blocks\n",
+		info->size >> 10, info->sector_count);
+    } else {
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+    }
+
+    printf ("  Sector Start Addresses:");
+    for (i=0; i<info->sector_count; ++i) {
+	/*
+	 * Check if whole sector is erased
+	 */
+	if (i != (info->sector_count-1))
+	    size = info->start[i+1] - info->start[i];
+	else
+	    size = info->start[0] + info->size - info->start[i];
+	erased = 1;
+	flash = (volatile unsigned long *)info->start[i];
+	size = size >> 2;        /* divide by 4 for longword access */
+	for (k=0; k<size; k++)
+	{
+	    if (*flash++ != 0xffffffff)
+	    {
+		erased = 0;
+		break;
+	    }
+	}
+
+	if ((i % 5) == 0)
+	    printf ("\n   ");
+	printf (" %08lX%s%s",
+	    info->start[i],
+	    erased ? " E" : "  ",
+	    info->protect[i] ? "RO " : "   "
+	);
+    }
+    printf ("\n");
+} /* end flash_print_info() */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+    short i;
+    ulong base = (ulong)addr;
+
+    /* Setup default type */
+    info->flash_id = FLASH_UNKNOWN;
+    info->sector_count =0;
+    info->size = 0;
+
+    /* Test for Boot Flash */
+    if (base == FLASH_BASE0_PRELIM) {
+	unsigned char value;
+	volatile unsigned char * addr2 = (unsigned char *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	*(addr2 + 0x555) = 0xaa;
+	*(addr2 + 0x2aa) = 0x55;
+	*(addr2 + 0x555) = 0x90;
+
+	/* Manufacture ID */
+	value = *addr2;
+	switch (value) {
+	    case (unsigned char)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	    case (unsigned char)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	    default:
+		*addr2 = 0xf0;              /* no or unknown flash  */
+		return 0;
+	}
+
+	/* Device ID */
+	value = *(addr2 + 1);
+	switch (value) {
+	    case (unsigned char)AMD_ID_LV040B:
+	    case (unsigned char)STM_ID_29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;                       /* => 512Kb */
+	    default:
+		*addr2 = 0xf0;               /* => no or unknown flash */
+		return 0;
+	}
+    }
+    else { /* MAIN Flash */
+	unsigned long value;
+	volatile unsigned long * addr2 = (unsigned long *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	*addr2 = 0x90909090;
+
+	/* Manufacture ID */
+	value = *addr2;
+	switch (value) {
+	    case (unsigned long)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	    default:
+		*addr2 = 0xff;              /* no or unknown flash  */
+		return 0;
+	}
+
+	/* Device ID - This shit is interleaved... */
+	value = *(addr2 + 1);
+	switch (value) {
+	    case (unsigned long)INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000 * 2;
+		break;                       /* => 2 X 4 MB */
+	    case (unsigned long)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000 * 2;
+		break;                       /* => 2 X 8 MB */
+	    case (unsigned long)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000 * 2;
+		break;                       /* => 2 X 16 MB */
+	    default:
+		*addr2 = 0xff;               /* => no or unknown flash */
+	}
+    }
+
+    /* Make sure we don't exceed CFG_MAX_FLASH_SECT */
+    if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	printf ("** ERROR: sector count %d > max (%d) **\n",
+		info->sector_count, CFG_MAX_FLASH_SECT);
+	info->sector_count = CFG_MAX_FLASH_SECT;
+    }
+
+    /* set up sector start address table */
+    switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00010000);
+	    break;
+	case FLASH_28F320J3A:
+	case FLASH_28F640J3A:
+	case FLASH_28F128J3A:
+	    for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00020000 * 2); /* 2 Banks */
+	    break;
+    }
+
+    /* Test for Boot Flash */
+    if (base == FLASH_BASE0_PRELIM) {
+	volatile unsigned char *addr2;
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+	    /* read sector protection at sector address, (AX .. A0) = 0x02 */
+	    /* D0 = 1 if protected */
+	    addr2 = (volatile unsigned char *)(info->start[i]);
+	    info->protect[i] = *(addr2 + 2) & 1;
+	}
+
+	/* Restore read mode */
+	*(unsigned char *)base = 0xF0;       /* Reset NORMAL Flash */
+    }
+    else { /* Main Flash */
+	volatile unsigned long *addr2;
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+	    /* read sector protection at sector address, (AX .. A0) = 0x02 */
+	    /* D0 = 1 if protected */
+	    addr2 = (volatile unsigned long *)(info->start[i]);
+	    info->protect[i] = *(addr2 + 2) & 0x1;
+	}
+
+	/* Restore read mode */
+	*(unsigned long *)base = 0xFFFFFFFF; /* Reset  Flash */
+    }
+
+    return (info->size);
+} /* end flash_get_size() */
+
+/*-----------------------------------------------------------------------
+ */
+
+static int wait_for_DQ7(ulong addr, uchar cmp_val, ulong tout)
+{
+    int i;
+
+    volatile uchar *vaddr =  (uchar *)addr;
+
+    /* Loop X times */
+    for (i = 1; i <= (100 * tout); i++) {    /* Wait up to tout ms */
+	udelay(10);
+	/* Pause 10 us */
+
+	/* Check for completion */
+	if ((vaddr[0] & 0x80) == (cmp_val & 0x80)) {
+	    return 0;
+	}
+
+	/* KEEP THE LUSER HAPPY - Print a dot every 1.1 seconds */
+	if (!(i % 110000))
+	    putc('.');
+
+	/* Kick the dog if needed */
+	WATCHDOG_RESET();
+    }
+
+    return 1;
+} /* wait_for_DQ7() */
+
+/*-----------------------------------------------------------------------
+ */
+
+static int flash_erase8(flash_info_t *info, int s_first, int s_last)
+{
+    int tcode, rcode = 0;
+    volatile uchar *addr = (uchar *)(info->start[0]);
+    volatile uchar *sector_addr;
+    int flag, prot, sect;
+
+    /* Validate arguments */
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN)
+	    printf ("- missing\n");
+	else
+	    printf ("- no sectors to erase\n");
+	return 1;
+    }
+
+    /* Check for KNOWN flash type */
+    if (info->flash_id == FLASH_UNKNOWN) {
+	printf ("Can't erase unknown flash type - aborted\n");
+	return 1;
+    }
+
+    /* Check for protected sectors */
+    prot = 0;
+    for (sect = s_first; sect <= s_last; ++sect) {
+	if (info->protect[sect])
+	    prot++;
+    }
+    if (prot)
+	printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+    else
+	printf ("\n");
+
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect <= s_last; sect++) {
+	if (info->protect[sect] == 0) {      /* not protected */
+	    sector_addr = (uchar *)(info->start[sect]);
+
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM)
+		    printf("Erasing block %p\n", sector_addr);
+		else
+		    printf("Erasing sector %p\n", sector_addr);
+
+	    /* Disable interrupts which might cause Flash to timeout */
+	    flag = disable_interrupts();
+
+	    *(addr + 0x555) = (uchar)0xAA;
+	    *(addr + 0x2aa) = (uchar)0x55;
+	    *(addr + 0x555) = (uchar)0x80;
+	    *(addr + 0x555) = (uchar)0xAA;
+	    *(addr + 0x2aa) = (uchar)0x55;
+	    *sector_addr = (uchar)0x30;      /* sector erase */
+
+	    /*
+	     * Wait for each sector to complete, it's more
+	     * reliable.  According to AMD Spec, you must
+	     * issue all erase commands within a specified
+	     * timeout.  This has been seen to fail, especially
+	     * if printf()s are included (for debug)!!
+	     * Takes up to 6 seconds.
+	     */
+	    tcode  = wait_for_DQ7((ulong)sector_addr, 0x80, 6000);
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    /* Make sure we didn't timeout */
+	    if (tcode) {
+		printf ("Timeout\n");
+		rcode = 1;
+	    }
+	}
+    }
+
+    /* wait at least 80us - let's wait 1 ms */
+    udelay (1000);
+
+    /* reset to read mode */
+    addr = (uchar *)info->start[0];
+    *addr = (uchar)0xF0;                     /* reset bank */
+
+    printf (" done\n");
+    return rcode;
+} /* end flash_erase8() */
+
+static int flash_erase32(flash_info_t *info, int s_first, int s_last)
+{
+    int flag, sect;
+    ulong start, now, last;
+    int prot = 0;
+
+    /* Validate arguments */
+    if ((s_first < 0) || (s_first > s_last)) {
+	if (info->flash_id == FLASH_UNKNOWN)
+	    printf ("- missing\n");
+	else
+	    printf ("- no sectors to erase\n");
+	return 1;
+    }
+
+    /* Check for KNOWN flash type */
+    if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+	printf ("Can erase only Intel flash types - aborted\n");
+	return 1;
+    }
+
+    /* Check for protected sectors */
+    for (sect = s_first; sect <= s_last; ++sect) {
+	if (info->protect[sect])
+	    prot++;
+    }
+    if (prot)
+	printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+    else
+	printf ("\n");
+
+    start = get_timer (0);
+    last  = start;
+    /* Start erase on unprotected sectors */
+    for (sect = s_first; sect <= s_last; sect++) {
+	WATCHDOG_RESET();
+	if (info->protect[sect] == 0) {      /* not protected */
+	    vu_long *addr = (vu_long *)(info->start[sect]);
+	    unsigned long status;
+
+	    /* Disable interrupts which might cause a timeout here */
+	    flag = disable_interrupts();
+
+	    *addr = 0x00500050;              /* clear status register */
+	    *addr = 0x00200020;              /* erase setup */
+	    *addr = 0x00D000D0;              /* erase confirm */
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    /* Wait at least 80us - let's wait 1 ms */
+	    udelay (1000);
+
+	    while (((status = *addr) & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		    printf ("Timeout\n");
+		    *addr = 0x00B000B0;      /* suspend erase      */
+		    *addr = 0x00FF00FF;      /* reset to read mode */
+		    return 1;
+		}
+
+		/* show that we're waiting */
+		if ((now - last) > 990) {   /* every second */
+		    putc ('.');
+		    last = now;
+		}
+	    }
+	    *addr = 0x00FF00FF;              /* reset to read mode */
+	}
+    }
+    printf (" done\n");
+    return 0;
+} /* end flash_erase32() */
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+    if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+	return flash_erase8(info, s_first, s_last);
+    else
+	return flash_erase32(info, s_first, s_last);
+} /* end flash_erase() */
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_buff8(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    ulong cp, wp, data;
+    ulong start;
+    int i, l, rc;
+
+    start = get_timer (0);
+
+    wp = (addr & ~3);                        /* get lower word
+						aligned address */
+
+    /*
+     * handle unaligned start bytes
+     */
+    if ((l = addr - wp) != 0) {
+	data = 0;
+	for (i=0, cp=wp; i<l; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+	for (; i<4 && cnt>0; ++i) {
+	    data = (data << 8) | *src++;
+	    --cnt;
+	    ++cp;
+	}
+	for (; cnt==0 && i<4; ++i, ++cp) {
+	    data = (data << 8) | (*(uchar *)cp);
+	}
+
+	if ((rc = write_word8(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp += 4;
+    }
+
+    /*
+     * handle word aligned part
+     */
+    while (cnt >= 4) {
+	data = 0;
+	for (i=0; i<4; ++i) {
+	    data = (data << 8) | *src++;
+	}
+	if ((rc = write_word8(info, wp, data)) != 0) {
+	    return (rc);
+	}
+	wp  += 4;
+	cnt -= 4;
+	if (get_timer(start) > 1000) {   /* every second */
+	   WATCHDOG_RESET();
+	   putc ('.');
+	   start = get_timer(0);
+	}
+    }
+
+    if (cnt == 0) {
+	return (0);
+    }
+
+    /*
+     * handle unaligned tail bytes
+     */
+    data = 0;
+    for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+	data = (data << 8) | *src++;
+	--cnt;
+    }
+    for (; i<4; ++i, ++cp) {
+	data = (data << 8) | (*(uchar *)cp);
+    }
+
+    return (write_word8(info, wp, data));
+} /* end write_buff8() */
+
+#define	FLASH_WIDTH	4	/* flash bus width in bytes */
+static int write_buff32 (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	ulong start;
+
+	start = get_timer (0);
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower FLASH_WIDTH aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<FLASH_WIDTH && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word32(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += FLASH_WIDTH;
+	}
+
+	/*
+	 * handle FLASH_WIDTH aligned part
+	 */
+	while (cnt >= FLASH_WIDTH) {
+		data = 0;
+		for (i=0; i<FLASH_WIDTH; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word32(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += FLASH_WIDTH;
+		cnt -= FLASH_WIDTH;
+	  if (get_timer(start) > 990) {   /* every second */
+			putc ('.');
+			start = get_timer(0);
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<FLASH_WIDTH; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word32(info, wp, data));
+} /* write_buff32() */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+    int retval;
+
+    if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040)
+	retval = write_buff8(info, src, addr, cnt);
+    else
+	retval = write_buff32(info, src, addr, cnt);
+
+    return retval;
+} /* end write_buff() */
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+static int write_word8(flash_info_t *info, ulong dest, ulong data)
+{
+    volatile uchar *addr2 = (uchar *)(info->start[0]);
+    volatile uchar *dest2 = (uchar *)dest;
+    volatile uchar *data2 = (uchar *)&data;
+    int flag;
+    int i, tcode, rcode = 0;
+
+    /* Check if Flash is (sufficently) erased */
+    if ((*((volatile uchar *)dest) &
+	(uchar)data) != (uchar)data) {
+	return (2);
+    }
+
+    for (i=0; i < (4 / sizeof(uchar)); i++) {
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*(addr2 + 0x555) = (uchar)0xAA;
+	*(addr2 + 0x2aa) = (uchar)0x55;
+	*(addr2 + 0x555) = (uchar)0xA0;
+
+	dest2[i] = data2[i];
+
+	/* Wait for write to complete, up to 1ms */
+	tcode = wait_for_DQ7((ulong)&dest2[i], data2[i], 1);
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+	    enable_interrupts();
+
+	/* Make sure we didn't timeout */
+	if (tcode) {
+	    rcode = 1;
+	}
+    }
+
+    return rcode;
+} /* end write_word8() */
+
+static int write_word32(flash_info_t *info, ulong dest, ulong data)
+{
+    vu_long *addr = (vu_long *)dest;
+    ulong status;
+    ulong start;
+    int flag;
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*addr & data) != data) {
+	return (2);
+    }
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    *addr = 0x00400040;                      /* write setup */
+    *addr = data;
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+	enable_interrupts();
+
+    start = get_timer (0);
+
+    while (((status = *addr) & 0x00800080) != 0x00800080) {
+	WATCHDOG_RESET();
+	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    *addr = 0x00FF00FF;              /* restore read mode */
+	    return (1);
+	}
+    }
+
+    *addr = 0x00FF00FF;                      /* restore read mode */
+
+    return (0);
+} /* end write_word32() */
+
+
+static int _flash_protect(flash_info_t *info, long sector)
+{
+    int i;
+    int flag;
+    ulong status;
+    int rcode = 0;
+    volatile long *addr = (long *)sector;
+
+    switch(info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+	case FLASH_28F640J3A:
+	case FLASH_28F128J3A:
+	    /* Disable interrupts which might cause Flash to timeout */
+	    flag = disable_interrupts();
+
+	    /* Issue command */
+	    *addr = 0x00500050L;             /* Clear the status register */
+	    *addr = 0x00600060L;             /* Set lock bit setup */
+	    *addr = 0x00010001L;             /* Set lock bit confirm */
+
+	    /* Wait for command completion */
+	    for (i = 0; i < 10; i++) {       /* 75us timeout, wait 100us */
+		udelay(10);
+		if ((*addr & 0x00800080L) == 0x00800080L)
+		    break;
+	    }
+
+	    /* Not successful? */
+	    status = *addr;
+	    if (status != 0x00800080L) {
+		printf("Protect %x sector failed: %x\n",
+		       (uint)sector, (uint)status);
+		rcode = 1;
+	    }
+
+	    /* Restore read mode */
+	    *addr = 0x00ff00ffL;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    break;
+	case FLASH_AM040:                    /* No soft sector protection */
+	    break;
+    }
+
+    /* Turn protection on for this sector */
+    for (i = 0; i < info->sector_count; i++) {
+	if (info->start[i] == sector) {
+	    info->protect[i] = 1;
+	    break;
+	}
+    }
+
+    return rcode;
+} /* end _flash_protect() */
+
+static int _flash_unprotect(flash_info_t *info, long sector)
+{
+    int i;
+    int flag;
+    ulong status;
+    int rcode = 0;
+    volatile long *addr = (long *)sector;
+
+    switch(info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+	case FLASH_28F640J3A:
+	case FLASH_28F128J3A:
+	    /* Disable interrupts which might cause Flash to timeout */
+	    flag = disable_interrupts();
+
+	    *addr = 0x00500050L;             /* Clear the status register */
+	    *addr = 0x00600060L;             /* Clear lock bit setup */
+	    *addr = 0x00D000D0L;             /* Clear lock bit confirm */
+
+	    /* Wait for command completion */
+	    for (i = 0; i < 80 ; i++) {      /* 700ms timeout, wait 800 */
+		udelay(10000);               /* Delay 10ms */
+		if ((*addr & 0x00800080L) == 0x00800080L)
+		    break;
+	    }
+
+	    /* Not successful? */
+	    status = *addr;
+	    if (status != 0x00800080L) {
+		printf("Un-protect %x sector failed: %x\n",
+		       (uint)sector, (uint)status);
+		*addr = 0x00ff00ffL;
+		rcode = 1;
+	    }
+
+	    /* restore read mode */
+	    *addr = 0x00ff00ffL;
+
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+		enable_interrupts();
+
+	    break;
+	case FLASH_AM040:                    /* No soft sector protection */
+	    break;
+    }
+
+    /*
+     * Fix Intel's little red wagon.  Reprotect
+     * sectors that were protected before we undid
+     * protection on a specific sector.
+     */
+    for (i = 0; i < info->sector_count; i++) {
+	if (info->start[i] != sector) {
+	    if (info->protect[i]) {
+		if (_flash_protect(info, info->start[i]))
+		    rcode = 1;
+	    }
+	}
+	else /* Turn protection off for this sector */
+	    info->protect[i] = 0;
+    }
+
+    return rcode;
+} /* end _flash_unprotect() */
+
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+    int rcode;
+
+    if (prot)
+	rcode = _flash_protect(info, info->start[sector]);
+    else
+	rcode = _flash_unprotect(info, info->start[sector]);
+
+    return rcode;
+} /* end flash_real_protect() */
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/w7o/fpga.c b/board/w7o/fpga.c
new file mode 100755
index 0000000..100bce4
--- /dev/null
+++ b/board/w7o/fpga.c
@@ -0,0 +1,379 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *  and
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+#include <common.h>
+#include "w7o.h"
+#include <asm/processor.h>
+#include "errors.h"
+
+static void
+fpga_img_write(unsigned long *src, unsigned long len, unsigned short *daddr)
+{
+    unsigned long i;
+    volatile unsigned long val;
+    volatile unsigned short *dest = daddr;	/* volatile-bypass optimizer */
+
+    for (i = 0; i < len; i++, src++) {
+	val = *src;
+	*dest = (unsigned short)((val & 0xff000000L) >> 16);
+	*dest = (unsigned short)((val & 0x00ff0000L) >> 8);
+	*dest = (unsigned short)(val & 0x0000ff00L);
+	*dest = (unsigned short)((val & 0x000000ffL) << 8);
+    }
+
+    /* Terminate programming with 4 C clocks */
+    dest = daddr;
+    val = *(unsigned short *)dest;
+    val = *(unsigned short *)dest;
+    val = *(unsigned short *)dest;
+    val = *(unsigned short *)dest;
+
+}
+
+
+int
+fpgaDownload(unsigned char *saddr,
+	     unsigned long size,
+	     unsigned short *daddr)
+{
+    int i;					/* index, intr disable flag */
+    int start;					/* timer */
+    unsigned long greg, grego;			/* GPIO & output register */
+    unsigned long length;			/* image size in words */
+    unsigned long *source;			/* image source addr */
+    unsigned short *dest;			/* destination FPGA addr */
+    volatile unsigned short *ndest;		/* temp dest FPGA addr */
+    volatile unsigned short val;		/* temp val */
+    unsigned long cnfg = GPIO_XCV_CNFG;		/* FPGA CNFG */
+    unsigned long eirq = GPIO_XCV_IRQ;
+    int retval = -1;				/* Function return value */
+
+    /* Setup some basic values */
+    length = (size / 4) + 1;			/* size in words, rounding UP
+						    is OK */
+    source = (unsigned long *)saddr;
+    dest = (unsigned short *)daddr;
+
+    /* Get DCR output register */
+    grego = in32(PPC405GP_GPIO0_OR);
+
+    /* Reset FPGA */
+    grego &= ~GPIO_XCV_PROG;			/* PROG line low */
+    out32(PPC405GP_GPIO0_OR, grego);
+
+    /* Setup timeout timer */
+    start = get_timer(0);
+
+    /* Wait for FPGA init line */
+    while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
+	/* Check for timeout - 100us max, so use 3ms */
+	if (get_timer(start) > 3) {
+	    printf("     failed to start init.\n");
+	    log_warn(ERR_XINIT0);		/* Don't halt */
+
+	    /* Reset line stays low */
+	    goto done;				/* I like gotos... */
+	}
+    }
+
+    /* Unreset FPGA */
+    grego |= GPIO_XCV_PROG;			/* PROG line high */
+    out32(PPC405GP_GPIO0_OR, grego);
+
+    /* Wait for FPGA end of init period .  */
+    while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
+
+	/* Check for timeout */
+	if (get_timer(start) > 3) {
+	    printf("     failed to exit init.\n");
+	    log_warn(ERR_XINIT1);
+
+	    /* Reset FPGA */
+	    grego &= ~GPIO_XCV_PROG;		/* PROG line low */
+	    out32(PPC405GP_GPIO0_OR, grego);
+
+	    goto done;
+	}
+    }
+
+    /* Now program FPGA ... */
+    ndest = dest;
+    for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+	/* Toggle IRQ/GPIO */
+	greg = mfdcr(CPC0_CR0);			/* get chip ctrl register */
+	greg |= eirq;				/* toggle irq/gpio */
+	mtdcr(CPC0_CR0, greg);			/*  ... just do it */
+
+	/* turn on open drain for CNFG */
+	greg = in32(PPC405GP_GPIO0_ODR);	/* get open drain register */
+	greg |= cnfg;				/* CNFG open drain */
+	out32(PPC405GP_GPIO0_ODR, greg);	/*  .. just do it */
+
+	/* Turn output enable on for CNFG */
+	greg = in32(PPC405GP_GPIO0_TCR);	/* get tristate register */
+	greg |= cnfg;				/* CNFG tristate inactive */
+	out32(PPC405GP_GPIO0_TCR, greg);	/*  ... just do it */
+
+	/* Setup FPGA for programming */
+	grego &= ~cnfg;				/* CONFIG line low */
+	out32(PPC405GP_GPIO0_OR, grego);
+
+	/*
+	 * Program the FPGA
+	 */
+	printf("\n       destination: 0x%lx ", (unsigned long)ndest);
+
+	fpga_img_write(source,  length,  (unsigned short *)ndest);
+
+	/* Done programming */
+	grego |= cnfg;				/* CONFIG line high */
+	out32(PPC405GP_GPIO0_OR, grego);
+
+	/* Turn output enable OFF for CNFG */
+	greg = in32(PPC405GP_GPIO0_TCR);	/* get tristate register */
+	greg &= ~cnfg;				/* CNFG tristate inactive */
+	out32(PPC405GP_GPIO0_TCR, greg);	/*  ... just do it */
+
+	/* Toggle IRQ/GPIO */
+	greg = mfdcr(CPC0_CR0);			/* get chip ctrl register */
+	greg &= ~eirq;				/* toggle irq/gpio */
+	mtdcr(CPC0_CR0, greg);			/*  ... just do it */
+
+	ndest = (unsigned short *)((char *)ndest + 0x00100000L); /* XXX - Next FPGA addr */
+	cnfg >>= 1;				/* XXX - Next  */
+	eirq >>= 1;
+    }
+
+    /* Terminate programming with 4 C clocks */
+    ndest = dest;
+    for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+	val = *ndest;
+	val = *ndest;
+	val = *ndest;
+	val = *ndest;
+	ndest = (unsigned short *)((char *)ndest + 0x00100000L);
+    }
+
+    /* Setup timer */
+    start = get_timer(0);
+
+    /* Wait for FPGA end of programming period .  */
+    while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
+
+	/* Check for timeout */
+	if (get_timer(start) > 3) {
+	    printf("     done failed to come high.\n");
+	    log_warn(ERR_XDONE1);
+
+	    /* Reset FPGA */
+	    grego &= ~GPIO_XCV_PROG;		/* PROG line low */
+	    out32(PPC405GP_GPIO0_OR, grego);
+
+	    goto done;
+	}
+    }
+
+    printf("\n       FPGA load succeeded\n");
+    retval = 0;					/* Program OK */
+
+done:
+    return retval;
+}
+
+/* FPGA image is stored in flash */
+extern flash_info_t    flash_info[];
+
+int init_fpga(void)
+{
+    unsigned int i,j,ptr;			/* General purpose */
+    unsigned char bufchar;			/* General purpose character */
+    unsigned char *buf;				/* Start of image pointer */
+    unsigned long len;				/* Length of image */
+    unsigned char *fn_buf;			/* Start of filename string */
+    unsigned int fn_len;			/* Length of filename string */
+    unsigned char *xcv_buf;			/* Pointer to start of image */
+    unsigned long xcv_len;			/* Length of image */
+    unsigned long crc;				/* 30bit crc in image */
+    unsigned long calc_crc;			/* Calc'd 30bit crc */
+    int retval = -1;
+
+    /* Tell the world what we are doing */
+    printf("FPGA:  ");
+
+    /*
+     * Get address of first sector where the FPGA
+     * image is stored.
+     */
+    buf = (unsigned char *)flash_info[1].start[0];
+
+    /*
+     * Get the stored image's CRC & length.
+     */
+    crc = *(unsigned long *)(buf+4);		/* CRC is first long word */
+    len = *(unsigned long *)(buf+8);		/* Image len is next long */
+
+    /* Pedantic */
+    if ((len < 0x133A4) || (len > 0x80000))
+	goto bad_image;
+
+    /*
+     * Get the file name pointer and length.
+     */
+    fn_len = (*(unsigned short *)(buf+12) & 0xff); /* filename length
+						      is next short */
+    fn_buf = buf + 14;
+
+    /*
+     * Get the FPGA image pointer and length length.
+     */
+    xcv_buf = fn_buf + fn_len;			/* pointer to fpga image */
+    xcv_len = len - 14 - fn_len;		/* fpga image length */
+
+    /* Check for uninitialized FLASH */
+    if ((strncmp((char *)buf, "w7o", 3)!=0) || (len > 0x0007ffffL) || (len == 0))
+	goto bad_image;
+
+    /*
+     * Calculate and Check the image's CRC.
+     */
+    calc_crc = crc32(0, xcv_buf, xcv_len);
+    if (crc != calc_crc) {
+	printf("\nfailed - bad CRC\n");
+	goto done;
+    }
+
+    /* Output the file name */
+    printf("file name  : ");
+    for (i=0;i<fn_len;i++) {
+	bufchar = fn_buf[+i];
+	if (bufchar<' ' || bufchar>'~') bufchar = '.';
+	putc(bufchar);
+    }
+
+    /*
+     * find rest of display data
+     */
+    ptr = 15;					/* Offset to ncd filename
+						   length in fpga image */
+    j = xcv_buf[ptr];				/* Get len of ncd filename */
+    if (j > 32) goto bad_image;
+    ptr = ptr + j + 3;				/* skip ncd filename string +
+						   3 bytes more bytes */
+
+    /*
+     * output target device string
+     */
+    j = xcv_buf[ptr++] - 1;			/* len of targ str less term */
+    if (j > 32) goto bad_image;
+    printf("\n       target     : ");
+    for (i = 0; i < j; i++) {
+	bufchar = (xcv_buf[ptr++]);
+	if (bufchar<' ' || bufchar>'~') bufchar = '.';
+	putc(bufchar);
+    }
+
+    /*
+     * output compilation date string and time string
+     */
+    ptr += 3;					/* skip 2 bytes */
+    printf("\n       synth time : ");
+    j = (xcv_buf[ptr++] - 1);			/* len of date str less term */
+    if (j > 32) goto bad_image;
+    for (i = 0; i < j; i++) {
+	bufchar = (xcv_buf[ptr++]);
+	if (bufchar<' ' || bufchar>'~') bufchar = '.';
+	putc(bufchar);
+    }
+
+    ptr += 3;					/* Skip 2 bytes */
+    printf(" - ");
+    j = (xcv_buf[ptr++] - 1);			/* slen = targ dev str len */
+    if (j > 32) goto bad_image;
+    for (i = 0; i < j; i++) {
+	bufchar = (xcv_buf[ptr++]);
+	if (bufchar<' ' || bufchar>'~') bufchar = '.';
+	putc(bufchar);
+    }
+
+    /*
+     * output crc and length strings
+     */
+    printf("\n       len & crc  : 0x%lx  0x%lx", len, crc);
+
+    /*
+     * Program the FPGA.
+     */
+    retval = fpgaDownload((unsigned char*)xcv_buf, xcv_len,
+			  (unsigned short *)0xfd000000L);
+    return retval;
+
+bad_image:
+    printf("\n       BAD FPGA image format @ %lx\n", flash_info[1].start[0]);
+    log_warn(ERR_XIMAGE);
+done:
+    return retval;
+}
+
+void test_fpga(unsigned short *daddr)
+{
+    int i;
+    volatile unsigned short *ndest = daddr;
+
+    for (i = 0; i < CONFIG_NUM_FPGAS; i++) {
+#if defined(CONFIG_W7OLMG)
+	ndest[0x7e] = 0x55aa;
+	if (ndest[0x7e] != 0x55aa)
+	    log_warn(ERR_XRW1 + i);
+	ndest[0x7e] = 0xaa55;
+	if (ndest[0x7e] != 0xaa55)
+	    log_warn(ERR_XRW1 + i);
+	ndest[0x7e] = 0xc318;
+	if (ndest[0x7e] != 0xc318)
+	    log_warn(ERR_XRW1 + i);
+
+#elif defined(CONFIG_W7OLMC)
+	ndest[0x800] = 0x55aa;
+	ndest[0x801] = 0xaa55;
+	ndest[0x802] = 0xc318;
+	ndest[0x4800] = 0x55aa;
+	ndest[0x4801] = 0xaa55;
+	ndest[0x4802] = 0xc318;
+	if ((ndest[0x800] != 0x55aa) ||
+	    (ndest[0x801] != 0xaa55) ||
+	    (ndest[0x802] != 0xc318))
+	    log_warn(ERR_XRW1 + (2 * i));       /* Auto gen error code */
+	if ((ndest[0x4800] != 0x55aa) ||
+	    (ndest[0x4801] != 0xaa55) ||
+	    (ndest[0x4802] != 0xc318))
+	    log_warn(ERR_XRW2 + (2 * i));       /* Auto gen error code */
+
+#else
+# error "Unknown W7O board configuration"
+#endif
+    }
+
+    printf("       FPGA ready\n");
+    return;
+}
diff --git a/board/w7o/fsboot.c b/board/w7o/fsboot.c
new file mode 100755
index 0000000..0ef9a61
--- /dev/null
+++ b/board/w7o/fsboot.c
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2001
+ * Wave 7 Optics, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+
+/*
+ * FIXME: Add code to test image and it's header.
+ */
+extern int valid_elf_image (unsigned long addr);
+
+static int
+image_check(ulong addr)
+{
+    return valid_elf_image(addr);
+}
+
+void
+init_fsboot(void)
+{
+    char  *envp;
+    ulong loadaddr;
+    ulong testaddr;
+    ulong alt_loadaddr;
+    char buf[9];
+
+    /*
+     * Get test image address
+     */
+    if ((envp = getenv("testaddr")) != NULL)
+	testaddr = simple_strtoul(envp, NULL, 16);
+    else
+	testaddr = -1;
+
+    /*
+     * Are we going to test boot and image?
+     */
+    if ((testaddr != -1) && image_check(testaddr)) {
+
+	/* Set alt_loadaddr */
+	alt_loadaddr = testaddr;
+	sprintf(buf, "%lX", alt_loadaddr);
+	setenv("alt_loadaddr", buf);
+
+	/* Clear test_addr */
+	setenv("testaddr", NULL);
+
+	/*
+	 * Save current environment with alt_loadaddr,
+	 * and cleared testaddr.
+	 */
+	saveenv();
+
+	/*
+	 * Setup temporary loadaddr to alt_loadaddr
+	 * XXX - DO NOT SAVE ENVIRONMENT!
+	 */
+	loadaddr = alt_loadaddr;
+	sprintf(buf, "%lX", loadaddr);
+	setenv("loadaddr", buf);
+
+    } else { /* Normal boot */
+	setenv("alt_loadaddr", NULL);		/* Clear alt_loadaddr */
+	setenv("testaddr", NULL);		/* Clear testaddr */
+	saveenv();
+    }
+
+    return;
+}
diff --git a/board/w7o/init.S b/board/w7o/init.S
new file mode 100755
index 0000000..35d7dbc
--- /dev/null
+++ b/board/w7o/init.S
@@ -0,0 +1,264 @@
+/******************************************************************************
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	addi	r3, 0, epcr
+	mtdcr	ebccfga, r3
+	addis	r4, 0, 0xb040		/* Device base timeout = 1024 cycles */
+	ori	r4, r4, 0x0		/* Drive CS with external master */
+	mtdcr	ebccfgd, r4
+
+	/********************************************************************
+	 * Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, cntrl1
+	ori	r4, r4, 0x4000
+	mtdcr	cntrl1, r4
+
+	/********************************************************************
+	 * Memory Bank 0 (Flash Bank 0) initialization
+	 *******************************************************************/
+	addi	r3, 0, pb0ap
+	mtdcr	ebccfga, r3
+	addis	r4, 0, CFG_W7O_EBC_PB0AP@h
+	ori	r4, r4, CFG_W7O_EBC_PB0AP@l
+	mtdcr	ebccfgd, r4
+
+	addi	r3, 0, pb0cr
+	mtdcr	ebccfga, r3
+	addis	r4, 0, CFG_W7O_EBC_PB0CR@h
+	ori	r4, r4, CFG_W7O_EBC_PB0CR@l
+	mtdcr	ebccfgd, r4
+
+	/********************************************************************
+	 * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
+	 *******************************************************************/
+	addi	r3, 0, pb7ap
+	mtdcr	ebccfga, r3
+	addis	r4, 0, CFG_W7O_EBC_PB7AP@h
+	ori	r4, r4, CFG_W7O_EBC_PB7AP@l
+	mtdcr	ebccfgd, r4
+
+	addi	r3, 0, pb7cr
+	mtdcr	ebccfga, r3
+	addis	r4, 0, CFG_W7O_EBC_PB7CR@h
+	ori	r4, r4, CFG_W7O_EBC_PB7CR@l
+	mtdcr	ebccfgd, r4
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ *		Serial Presence Detect, "SPD," reads the SDRAM EEPROM
+ *		via the IIC bus and then configures the SDRAM memory
+ *		banks appropriately. If Auto Memory Configuration is
+ *		is not used, it is assumed that a 4MB 11x8x2, non-ECC,
+ *		SDRAM is soldered down.
+ *
+ * Notes:	Expects that the stack is already setup.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -8(r1)		/* Save back chain and move SP */
+	stw	r0, +12(r1)		/* Save link register */
+
+	/*
+	 * First call spd_sdram to try to init SDRAM according to the
+	 * contents of the SPD EEPROM.  If the SPD EEPROM is blank or
+	 * erronious, spd_sdram returns 0 in R3.
+	 */
+	li	r3,0
+	bl	spd_sdram
+	addic.	r3, r3, 0		/* Check for error, save dram size */
+	bne	..sdri_done		/* If it worked, we're done... */
+
+	/********************************************************************
+	 * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
+	 * is the SMALLEST SDRAM size the 405 supports.  We can do this
+	 * because W7O boards have soldered on RAM, and there will always
+	 * be some amount present.  If we were using DIMMs, we should hang
+	 * the board instead, since it doesn't have any RAM to continue
+	 * running with.
+	 *******************************************************************/
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	addi    r3, 0, mem_mcopt1
+	mtdcr   memcfga, r3
+	addis   r4, 0, 0x0
+	ori     r4, r4, 0x0
+	mtdcr   memcfgd, r4
+
+	/*
+	 * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
+	 * All other banks are disabled.
+	 */
+	addi	r3, 0, mem_mb0cf
+	mtdcr	memcfga, r3
+	addis	r4, 0, 0x0000		/* BA=0x0, SZ=4MB */
+	ori	r4, r4, 0x8001		/* Mode is 5, 11x8x2or4, BE=Enabled */
+	mtdcr	memcfgd, r4
+
+	/* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
+	addi	r4, 0, 0		/* Zero the data reg */
+
+	addi	r3, r3, 4		/* Point to MB1CF reg */
+	mtdcr	memcfga, r3		/* Set the address */
+	mtdcr	memcfgd, r4		/* Zero the reg */
+
+	addi	r3, r3, 4		/* Point to MB2CF reg */
+	mtdcr	memcfga, r3		/* Set the address */
+	mtdcr	memcfgd, r4		/* Zero the reg */
+
+	addi	r3, r3, 4		/* Point to MB3CF reg */
+	mtdcr	memcfga, r3		/* Set the address */
+	mtdcr	memcfgd, r4		/* Zero the reg */
+
+	/********************************************************************
+	 * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
+	 * To set the appropriate timings, we assume sdram is
+	 * 100MHz (pc100 compliant).
+	 *******************************************************************/
+
+	/*
+	 * Set up SDTR1
+	 */
+	addi    r3, 0, mem_sdtr1
+	mtdcr   memcfga, r3
+	addis   r4, 0, 0x0086		/* SDTR1 value for 100Mhz */
+	ori     r4, r4, 0x400D
+	mtdcr   memcfgd, r4
+
+	/*
+	 * Set RTR
+	 */
+	addi    r3, 0, mem_rtr
+	mtdcr   memcfga, r3
+	addis   r4, 0, 0x05F0		/* RTR refresh val = 15.625ms@100Mhz */
+	mtdcr   memcfgd, r4
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait 200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	addi    r3, 0, mem_mcopt1
+	mtdcr   memcfga, r3
+	addis   r4, 0, 0x80E0		/* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
+	ori     r4, r4, 0x0000		/* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
+	mtdcr   memcfgd, r4		/* EMDULR=1 */
+
+..sdri_done:
+	/* restore and return */
+	lwz	r0, +12(r1)		/* Get saved link register */
+	addi	r1, r1, +8		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
diff --git a/board/w7o/post1.S b/board/w7o/post1.S
new file mode 100755
index 0000000..21d206e
--- /dev/null
+++ b/board/w7o/post1.S
@@ -0,0 +1,742 @@
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, william.hunter@mediaone.net
+ *  and
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * Description:
+ *	Routine to exercise memory for the bringing up of our boards.
+ */
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#include <watchdog.h>
+
+#include "errors.h"
+
+#define _ASMLANGUAGE
+
+	.globl	test_sdram
+	.globl	test_led
+	.globl	log_stat
+	.globl	log_warn
+	.globl	log_err
+	.globl  temp_uart_init
+	.globl  post_puts
+	.globl  disp_hex
+
+/*****************************************************
+*******   Text Strings for low level printing   ******
+*******          In section got2               *******
+*****************************************************/
+
+/*
+ * Define the text strings for errors and warnings.
+ * Switch to .data section.
+ */
+	.section ".data"
+err_str: 	.asciz "*** POST ERROR   = "
+warn_str:	.asciz "*** POST WARNING = "
+end_str:  .asciz "\r\n"
+
+/*
+ * Enter the labels in Global Entry Table (GOT).
+ * Switch to .got2 section.
+ */
+	START_GOT
+	GOT_ENTRY(err_str)
+	GOT_ENTRY(warn_str)
+	GOT_ENTRY(end_str)
+	END_GOT
+
+/*
+ * Switch  back to .text section.
+ */
+	.text
+
+/****************************************
+ ****************************************
+ ********    LED register test   ********
+ ****************************************
+ ***************************************/
+test_led:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+
+	WATCHDOG_RESET        		/* Reset the watchdog */
+
+	addi    r3, 0, ERR_FF		/* first test value is ffff */
+	addi	r4, r3, 0		/* save copy of pattern */
+	bl	set_led			/* store first test value */
+	bl	get_led			/* read it back */
+	xor.	r4, r4, r3		/* compare to original */
+#if defined(CONFIG_W7OLMC)
+	andi.   r4, r4, 0x00ff		/* lmc has 8 bits */
+#else
+	andi.   r4, r4, 0xffff		/* lmg has 16 bits */
+#endif
+	beq     LED2			/* next test */
+	addi    r3, 0, ERR_LED		/* error code = 1 */
+	bl	log_err			/* display error and halt */
+LED2:	addi    r3, 0, ERR_00		/* 2nd test value is 0000 */
+	addi	r4, r3, 0		/* save copy of pattern */
+	bl	set_led			/* store first test value */
+	bl	get_led			/* read it back */
+	xor.	r4, r4, r3		/* compare to original */
+#if defined(CONFIG_W7OLMC)
+	andi.   r4, r4, 0x00ff		/* lmc has 8 bits */
+#else
+	andi.   r4, r4, 0xffff		/* lmg has 16 bits */
+#endif
+	beq     LED3			/* next test */
+	addi    r3, 0, ERR_LED		/* error code = 1 */
+	bl	log_err			/* display error and halt */
+
+LED3:	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	lwz	r4, +8(r1)		/* restore r4 */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+/****************************************
+ ****************************************
+ ********     SDRAM TESTS        ********
+ ****************************************
+ ***************************************/
+test_sdram:
+	/* called with mem size in r3 */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -16(r1)		/* Save back chain and move SP */
+	stw	r0, +20(r1)		/* Save link register */
+	stmw	r30, +8(r1)		/* save R30,R31 */
+					/* r30 is log2(mem size) */
+					/* r31 is mem size */
+
+	/* take log2 of total mem size */
+	addi	r31, r3, 0		/* save total mem size */
+	addi	r30, 0, 0		/* clear r30 */
+l2_loop:
+	srwi.	r31, r31, 1		/* shift right 1 */
+	addi	r30, r30, 1		/* count shifts */
+	bne	l2_loop			/* loop till done */
+	addi	r30, r30, -1		/* correct for over count */
+	addi	r31, r3, 0		/* save original size */
+
+	/* now kick the dog and test the mem */
+	WATCHDOG_RESET        		/* Reset the watchdog */
+	bl	Data_Buster		/* test crossed/shorted data lines */
+	addi	r3, r30, 0		/* get log2(memsize) */
+	addi	r4, r31, 0		/* get memsize */
+	bl	Ghost_Buster		/* test crossed/shorted addr lines */
+	addi	r3, r31, 0		/* get mem size */
+	bl	Bit_Buster		/* check for bad internal bits */
+
+	/* restore stack and return */
+	lmw	r30, +8(r1)		/* Restore r30, r31 */
+	lwz	r0, +20(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	addi	r1, r1, +16		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+
+/****************************************
+ ********  sdram data bus test   ********
+ ***************************************/
+Data_Buster:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -24(r1)		/* Save back chain and move SP */
+	stw	r0, +28(r1)		/* Save link register */
+	stmw	r28, 8(r1)		/* save r28 - r31 on stack */
+					/* r31 i/o register */
+					/* r30 sdram base address */
+					/* r29 5555 syndrom */
+					/* r28 aaaa syndrom */
+
+	/* set up led register for this test */
+	addi    r3, 0, ERR_RAMG		/* set led code to 1 */
+	bl	log_stat		/* store test value */
+	/* now test the dram data bus */
+	xor	r30, r30, r30		/* load r30 with base addr of sdram */
+	addis	r31, 0, 0x5555		/* load r31 with test value */
+	ori	r31, r31, 0x5555
+	stw	r31,0(r30)		/* sto the value */
+	lwz	r29,0(r30)		/* read it back */
+	xor	r29,r31,r29		/* compare it to original */
+	addis	r31, 0, 0xaaaa		/* load r31 with test value */
+	ori	r31, r31, 0xaaaa
+	stw	r31,0(r30)		/* sto the value */
+	lwz	r28,0(r30)		/* read it back */
+	xor	r28,r31,r28		/* compare it to original */
+	or	r3,r28,r29		/* or together both error terms */
+	/*
+	 * Now that we have the error bits,
+	 * we have to decide which part they are in.
+	 */
+	bl	get_idx			/* r5 is now index to error */
+	addi	r3, r3, ERR_RAMG
+	cmpwi	r3, ERR_RAMG		/* check for errors */
+	beq	db_done			/* skip if no errors */
+	bl	log_err			/* log the error */
+
+db_done:
+	lmw	r28, 8(r1)		/* restore r28 - r31 from stack */
+	lwz	r0, +28(r1)		/* Get saved link register */
+	addi	r1, r1, +24		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+
+
+/****************************************************
+ ********  test for address ghosting in dram ********
+ ***************************************************/
+
+Ghost_Buster:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -36(r1)		/* Save back chain and move SP */
+	stw	r0, +40(r1)		/* Save link register */
+	stmw	r25, 8(r1)		/* save r25 - r31 on stack */
+					/* r31 = scratch register */
+					/* r30 is main referance loop counter,
+					   0 to 23 */
+					/* r29 is ghost loop count, 0 to 22 */
+					/* r28 is referance address */
+					/* r27 is ghost address */
+					/* r26 is log2 (mem size) =
+					     number of byte addr bits */
+					/* r25 is mem size */
+
+	/* save the log2(mem size) and mem size */
+	addi	r26, r3, 0		/* r26 is number of byte addr bits */
+	addi	r25, r4, 0		/* r25 is mem size in bytes */
+
+	/* set the leds for address ghost test */
+	addi	r3, 0, ERR_ADDG
+	bl	set_led
+
+	/* first fill memory with zeros */
+	srwi	r31, r25, 2		/* convert bytes to longs */
+	mtctr	r31			/* setup byte counter */
+	addi	r28, 0, 0		/* start at address at 0 */
+	addi	r31, 0, 0		/* data value = 0 */
+clr_loop:
+	stw	r31, 0(r28)		/* Store zero value */
+	addi	r28, r28, 4		/* Increment to next word */
+	andi.	r27, r28, 0xffff	/* check for 2^16 loops */
+	bne	clr_skip		/* if not there, then skip */
+	WATCHDOG_RESET   		/* kick the dog every now and then */
+clr_skip:
+	bdnz	clr_loop		/* Round and round... */
+
+	/* now do main test */
+	addi	r30, 0, 0		/* start referance counter at 0 */
+outside:
+	/*
+	 * Calculate the referance address
+	 *   the referance address is calculated by setting the (r30-1)
+	 *   bit of the base address
+	 * when r30=0, the referance address is the base address.
+	 * thus the sequence 0,1,2,4,8,..,2^(n-1)
+	 * setting the bit is done with the following shift functions.
+	 */
+	WATCHDOG_RESET   		/* Reset the watchdog */
+
+	addi	r31, 0, 1		/* r31 = 1 */
+	slw	r28, r31, r30		/* set bit coresponding to loop cnt */
+	srwi	r28, r28, 1		/* then shift it right one so  */
+					/*   we start at location 0 */
+	/* fill referance address with Fs */
+	addi	r31, 0, 0x00ff		/* r31 = one byte of set bits */
+	stb     r31,0(r28)		/* save ff in referance address */
+
+	/* ghost (inner) loop, now check all posible ghosted addresses */
+	addi	r29, 0, 0		/* start ghosted loop counter at 0 */
+inside:
+	/*
+	 * Calculate the ghost address by flipping one
+	 *  bit of referance address.  This gives the
+	 *  sequence 1,2,4,8,...,2^(n-1)
+	 */
+	addi	r31, 0, 1		/* r31 = 1 */
+	slw     r27, r31, r29		/* set  bit coresponding to loop cnt */
+	xor	r27, r28, r27		/* ghost address = ref addr with
+					     bit flipped*/
+
+	/* now check for ghosting */
+	lbz     r31,0(r27)		/* get content of ghost addr */
+	cmpwi   r31, 0			/* compare read value to 0 */
+	bne	Casper			/*   we found a ghost! */
+
+	/* now close ghost ( inner ) loop */
+	addi 	r29, r29, 1		/* increment inner loop counter */
+	cmpw 	r29, r26		/* check for last inner loop */
+	blt		inside		/* do more inner loops */
+
+	/* now close referance ( outer ) loop */
+	addi 	r31, 0, 0 		/* r31 = zero */
+	stb	r31, 0(28)		/* zero out the altered address loc. */
+	/*
+	 * Increment and check for end, count is zero based.
+	 * With the ble, this gives us one more loops than
+	 * address bits for sequence 0,1,2,4,8,...2^(n-1)
+	*/
+	addi 	r30, r30, 1		/* increment outer loop counter */
+	cmpw 	r30, r26		/* check for last inner loop */
+	ble	outside			/* do more outer loops */
+
+	/* were done, lets go home */
+	b	gb_done
+Casper:					/* we found a ghost !! */
+	addi	r3, 0, ERR_ADDF		/* get indexed error message */
+	bl	log_err			/* log error led error code */
+gb_done: /*  pack your bags, and go home */
+	lmw     r25, 8(r1)              /* restore r25 - r31 from stack */
+	lwz     r0, +40(r1)             /* Get saved link register */
+	addi    r1, r1, +36             /* Remove frame from stack */
+	mtlr    r0                      /* Restore link register */
+	blr                             /* Return to calling function */
+
+/****************************************************
+ ********      SDRAM data fill tests       **********
+ ***************************************************/
+Bit_Buster:
+	/* called with mem size in r3 */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -16(r1)		/* Save back chain and move SP */
+	stw	r0, +20(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+	stw	r5, +12(r1)		/* save r5 */
+
+	addis	r5, r3, 0		/* save mem size */
+
+	/* Test 55555555 */
+	addi	r3, 0, ERR_R55G		/* set up error code in case we fail */
+	bl	log_stat		/* store test value */
+	addis	r4, 0, 0x5555
+	ori	r4, r4, 0x5555
+	bl	fill_test
+
+	/* Test aaaaaaaa  */
+	addi	r3, 0, ERR_RAAG		/* set up error code in case we fail */
+	bl	log_stat		/* store test value */
+	addis	r4, 0, 0xAAAA
+	ori	r4, r4, 0xAAAA
+	bl	fill_test
+
+	/* Test 00000000  */
+	addi	r3, 0, ERR_R00G		/* set up error code in case we fail */
+	bl	log_stat		/* store test value */
+	addis	r4, 0, 0
+	ori	r4, r4, 0
+	bl	fill_test
+
+	/* restore stack and return */
+	lwz	r5, +12(r1)		/* restore r4 */
+	lwz	r4, +8(r1)		/* restore r4 */
+	lwz	r0, +20(r1)		/* Get saved link register */
+	addi	r1, r1, +16		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+
+
+/****************************************************
+ ********             fill test              ********
+ ***************************************************/
+/*	tests memory by filling with value, and reading back */
+/*	r5 = Size of memory in bytes */
+/*	r4 = Value to write */
+/*	r3 = Error code */
+fill_test:
+	mflr    r0                      /* Get link register */
+	stwu    r1, -32(r1)             /* Save back chain and move SP */
+	stw     r0, +36(r1)             /* Save link register */
+	stmw    r27, 8(r1)              /* save r27 - r31 on stack */
+					/* r31 - scratch register */
+					/* r30 - memory address */
+	mr	r27, r3
+	mr	r28, r4
+	mr	r29, r5
+
+	WATCHDOG_RESET   		/* Reset the watchdog */
+
+	/* first fill memory with Value */
+	srawi	r31, r29, 2		/* convert bytes to longs */
+	mtctr	r31			/* setup counter */
+	addi	r30, 0, 0		/* Make r30 = addr 0 */
+ft_0:	stw	r28, 0(r30)		/* Store value */
+	addi	r30, r30, 4		/* Increment to next word */
+	andi.	r31, r30, 0xffff	/* check for 2^16 loops */
+	bne	ft_0a			/* if not there, then skip */
+	WATCHDOG_RESET   		/* kick the dog every now and then */
+ft_0a:	bdnz	ft_0			/* Round and round... */
+
+	WATCHDOG_RESET   		/* Reset the watchdog */
+
+	/* Now confirm Value is in memory */
+	srawi	r31, r29, 2		/* convert bytes to longs */
+	mtctr	r31			/* setup counter */
+	addi	r30, 0, 0		/* Make r30 = addr 0 */
+ft_1:	lwz	r31, 0(r30)		/* get value from memory */
+	xor.	r31, r31, r28		/* Writen = Read ? */
+	bne	ft_err			/* If bad, than halt */
+	addi	r30, r30, 4		/* Increment to next word */
+	andi.	r31, r30, 0xffff	/* check for 2^16 loops*/
+	bne	ft_1a			/* if not there, then skip */
+	WATCHDOG_RESET			/* kick the dog every now and then */
+ft_1a:	bdnz	ft_1			/* Round and round... */
+
+	WATCHDOG_RESET   		/* Reset the watchdog */
+
+	b	fill_done		/* restore and return */
+
+ft_err:	addi	r29, r27, 0		/* save current led code */
+	addi	r27, r31, 0		/* get pattern in r27 */
+	bl	get_idx			/* get index from r27 */
+	add	r27, r27, r29		/* add index to old led code */
+	bl	log_err			/* output led err code, halt CPU */
+
+fill_done:
+	lmw     r27, 8(r1)              /* restore r27 - r31 from stack */
+	lwz     r0, +36(r1)             /* Get saved link register */
+	addi    r1, r1, +32             /* Remove frame from stack */
+	mtlr    r0                      /* Restore link register */
+	blr                             /* Return to calling function */
+
+
+/****************************************************
+ *******  get error index from r3 pattern    ********
+ ***************************************************/
+get_idx:				/* r3 = (MSW(r3) !=0)*2 +
+					    (LSW(r3) !=0) */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+
+	andi.	r4, r3, 0xffff		/* check for lower bits */
+	beq	gi2			/* skip if no bits set */
+	andis.	r4, r3, 0xffff		/* check for upper bits */
+	beq	gi3			/* skip if no bits set */
+	addi	r3, 0, 3		/* both upper and lower bits set */
+	b	gi_done
+gi2:	andis.	r4, r3, 0xffff		/* check for upper bits*/
+	beq	gi4			/* skip if no bits set */
+	addi	r3, 0, 2		/* only upper bits set */
+	b	gi_done
+gi3:	addi	r3, 0, 1		/* only lower bits set */
+	b	gi_done
+gi4:	addi	r3, 0, 0		/* no bits set */
+gi_done:
+	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	lwz	r4, +8(r1)		/* restore r4 */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+/****************************************************
+ ********       set LED to R5 and hang       ********
+ ***************************************************/
+log_stat:				/* output a led code and continue */
+set_led:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+
+	addis	r4, 0, 0xfe00		/* LED buffer is at 0xfe000000 */
+#if defined(CONFIG_W7OLMG)		/* only on gateway, invert outputs */
+	xori	r3,r3, 0xffff		/* complement led code, active low */
+	sth	r3, 0(r4)		/* store first test value */
+	xori	r3,r3, 0xffff		/* complement led code, active low */
+#else					/* if not gateway, then don't invert */
+	sth	r3, 0(r4)		/* store first test value */
+#endif
+
+	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	lwz	r4, +8(r1)		/* restore r4 */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+get_led:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r4, +8(r1)		/* save R4 */
+
+	addis	r4, 0, 0xfe00		/* LED buffer is at 0xfe000000 */
+	lhz	r3, 0(r4)		/* store first test value */
+#if defined(CONFIG_W7OLMG)		/* only on gateway, invert inputs */
+	xori	r3,r3, 0xffff		/* complement led code, active low */
+#endif
+
+	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	lwz	r4, +8(r1)		/* restore r4 */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+log_err:	/* output the error and hang the board ( for now ) */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r3, +8(r1)		/* save a copy of error code */
+	bl	set_led			/* set the led pattern */
+	GET_GOT				/* get GOT address in r14 */
+	lwz	r3,GOT(err_str)		/* get address of string */
+	bl	post_puts		/* output the warning string */
+	lwz	r3, +8(r1)		/* get error code */
+	addi	r4, 0, 2		/* set disp length to 2 nibbles */
+	bl	disp_hex		/* output the error code */
+	lwz	r3,GOT(end_str)		/* get address of string */
+	bl	post_puts		/* output the warning string */
+halt:
+	b	halt			/* hang */
+
+	/* restore stack and return */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+log_warn:	/* output a warning, then continue with operations */
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -16(r1)		/* Save back chain and move SP */
+	stw	r0, +20(r1)		/* Save link register */
+	stw	r3, +8(r1)		/* save a copy of error code */
+	stw	r14, +12(r1)		/* save a copy of r14 (used by GOT) */
+
+	bl	set_led			/* set the led pattern */
+	GET_GOT				/* get GOT address in r14 */
+	lwz	r3,GOT(warn_str)	/* get address of string */
+	bl	post_puts		/* output the warning string */
+	lwz	r3, +8(r1)		/* get error code */
+	addi	r4, 0, 2		/* set disp length to 2 nibbles */
+	bl	disp_hex		/* output the error code */
+	lwz	r3,GOT(end_str)		/* get address of string */
+	bl	post_puts		/* output the warning string */
+
+	addis	r3, 0, 64		/* has a long delay */
+	mtctr	r3
+log_2:
+	WATCHDOG_RESET			/* this keeps dog from barking, */
+					/*   and takes time */
+	bdnz	log_2			/* loop till time expires */
+
+	/* restore stack and return */
+	lwz	r0, +20(r1)		/* Get saved link register */
+	lwz	r14, +12(r1)		/* restore r14 */
+	mtlr	r0			/* Restore link register */
+	addi	r1, r1, +16		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+/*******************************************************************
+ *	temp_uart_init
+ *	Temporary UART initialization routine
+ *	Sets up UART0 to run at 9600N81 off of the internal clock.
+ *	R3-R4 are used.
+ ******************************************************************/
+temp_uart_init:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -8(r1)		/* Save back chain and move SP */
+	stw	r0, +12(r1)		/* Save link register */
+
+	addis   r3, 0, 0xef60
+	ori     r3, r3, 0x0303          /* r3 = UART0_LCR */
+	addi    r4, 0, 0x83             /* n81 format, divisor regs enabled */
+	stb     r4, 0(r3)
+
+	/* set baud rate to use internal clock,
+	   baud = (200e6/16)/31/42 = 9600 */
+
+	addis   r3, 0, 0xef60		/* Address of baud divisor reg */
+	ori     r3, r3, 0x0300		/*   UART0_DLM */
+	addi    r4, 0, +42		/* uart baud divisor LSB = 93 */
+	stb     r4, 0(r3)               /* baud = (200 /16)/14/93 */
+
+	addi    r3, r3, 0x0001		/* uart baud divisor addr */
+	addi    r4, 0, 0
+	stb     r4, 0(r3)               /* Divisor Latch MSB = 0 */
+
+	addis   r3, 0, 0xef60
+	ori     r3, r3, 0x0303          /* r3 = UART0_LCR */
+	addi    r4, 0, 0x03             /* n81 format, tx/rx regs enabled */
+	stb     r4, 0(r3)
+
+	/* output a few line feeds */
+	addi	r3, 0, '\n'		/* load line feed */
+	bl 	post_putc		/* output the char */
+	addi	r3, 0, '\n'		/* load line feed */
+	bl 	post_putc		/* output the char */
+
+	/* restore stack and return */
+	lwz	r0, +12(r1)		/* Get saved link register */
+	mtlr	r0			/* Restore link register */
+	addi	r1, r1, +8		/* Remove frame from stack */
+	blr				/* Return to calling function */
+
+/**********************************************************************
+ **	post_putc
+ **	outputs charactor in R3
+ **	r3 returns the error code ( -1 if there is an error )
+ *********************************************************************/
+
+post_putc:
+
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -20(r1)		/* Save back chain and move SP */
+	stw	r0, +24(r1)		/* Save link register */
+	stmw	r29, 8(r1)		/* save	r29 - r31 on stack
+					   r31 - uart base address
+					   r30 - delay counter
+					   r29 - scratch reg */
+
+     addis   r31, 0, 0xef60		/* Point to uart base */
+     ori     r31, r31, 0x0300
+     addis   r30, 0, 152 		/* Load about 10,000,000 ticks. */
+pputc_lp:
+	lbz     r29, 5(r31) 		/* Read Line Status Register */
+	andi.   r29, r29, 0x20		/* Check THRE status */
+	bne     thre_set		/* Branch if FIFO empty */
+	addic.  r30, r30, -1		/* Decrement and check if empty. */
+	bne     pputc_lp		/* Try, try again */
+	addi    r3, 0, -1		/* Load error code for timeout */
+	b       pputc_done 		/* Bail out with error code set */
+thre_set:
+	stb     r3, 0(r31)		/* Store character to UART */
+	addi	r3, 0, 0		/* clear error code */
+pputc_done:
+	lmw	r29, 8(r1)		/*restore r29 - r31 from stack */
+	lwz	r0, +24(r1)		/* Get saved link register */
+	addi	r1, r1, +20		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+
+
+/****************************************************************
+    post_puts
+    Accepts a null-terminated string pointed to by R3
+    Outputs to the serial port until 0x00 is found.
+    r3 returns the error code ( -1 if there is an error )
+*****************************************************************/
+post_puts:
+
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -12(r1)		/* Save back chain and move SP */
+	stw	r0, +16(r1)		/* Save link register */
+	stw	r31, 8(r1)		/* save r31 - char pointer */
+
+	addi 	r31, r3, 0              /* move pointer to R31 */
+pputs_nxt:
+	lbz	r3, 0(r31)		/* Get next character */
+	addic.  r3, r3, 0		/* Check for zero */
+	beq	pputs_term		/* bail out if zero */
+	bl	post_putc		/* output the char */
+	addic.	r3, r3, 0		/* check for error */
+	bne	pputs_err
+	addi 	r31, r31, 1		/* point to next char */
+	b	pputs_nxt 		/* loop till term */
+pputs_err:
+	addi 	r3, 0, -1		/* set error code */
+	b	pputs_end		/* were outa here */
+pputs_term:
+	addi 	r3, 0, 1		/* set success code */
+	/* restore stack and return */
+pputs_end:
+	lwz	r31, 8(r1)		/* restore r27 - r31 from stack */
+	lwz	r0, +16(r1)		/* Get saved link register */
+	addi	r1, r1, +12		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+
+
+/********************************************************************
+ *****	disp_hex
+ *****	Routine to display a hex value from a register.
+ *****	R3 is value to display
+ *****	R4 is number of nibbles to display ie 2 for byte 8 for (long)word
+ *****	Returns -1 in R3 if there is an error ( ie serial port hangs )
+ *****	Returns 0 in R3 if no error
+ *******************************************************************/
+disp_hex:
+	/* save the return info on stack */
+	mflr	r0			/* Get link register */
+	stwu	r1, -16(r1)		/* Save back chain and move SP */
+	stw	r0, +20(r1)		/* Save link register */
+	stmw	r30, 8(r1)		/* save r30 - r31 on stack */
+					/* r31 output char */
+					/* r30 uart base address */
+	addi 	r30, 0, 8               /* Go through 8 nibbles. */
+	addi 	r31, r3, 0
+pputh_nxt:
+	rlwinm	r31, r31, 4, 0, 31	/* Rotate next nibble into position */
+	andi. 	r3, r31, 0x0f		/* Get nibble. */
+	addi 	r3, r3, 0x30		/* Add zero's ASCII code. */
+	cmpwi	r3, 0x03a
+	blt	pputh_out
+	addi 	r3, r3, 0x07            /* 0x27 for lower case. */
+pputh_out:
+	cmpw 	r30, r4
+	bgt	pputh_skip
+	bl	post_putc
+	addic. 	r3, r3, 0 		/* check for error */
+	bne	pputh_err
+pputh_skip:
+	addic.	r30, r30, -1
+	bne	pputh_nxt
+	xor	r3, r3, r3		/* Clear error code */
+	b	pputh_done
+pputh_err:
+	addi 	r3, 0, -1 		/* set error code */
+pputh_done:
+	/* restore stack and return */
+	lmw	r30, 8(r1)		/*  restore r30 - r31 from stack */
+	lwz	r0, +20(r1)		/* Get saved link register */
+	addi	r1, r1, +16		/* Remove frame from stack */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
diff --git a/board/w7o/post2.c b/board/w7o/post2.c
new file mode 100755
index 0000000..e590128
--- /dev/null
+++ b/board/w7o/post2.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2001
+ * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
+ *   and
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <rtc.h>
+#include "errors.h"
+#include "dtt.h"
+
+#if defined(CONFIG_RTC_M48T35A)
+void rtctest(void)
+{
+    volatile uchar *tchar = (uchar*)(CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 9);
+    struct rtc_time tmp;
+
+    /* set up led code for RTC tests */
+    log_stat(ERR_RTCG);
+
+    /*
+     * Do RTC battery test. The first write after power up
+     * fails if battery is low.
+     */
+    *tchar = 0xaa;
+    if ((*tchar ^ 0xaa) != 0x0) log_warn(ERR_RTCBAT);
+    *tchar = 0x55;				/* Reset test address */
+
+    /*
+     * Now lets check the validity of the values in the RTC.
+     */
+    rtc_get(&tmp);
+    if ((tmp.tm_sec < 0)	| (tmp.tm_sec  > 59)   |
+	(tmp.tm_min < 0)	| (tmp.tm_min  > 59)   |
+	(tmp.tm_hour < 0)	| (tmp.tm_hour > 23)   |
+	(tmp.tm_mday < 1 )	| (tmp.tm_mday > 31)   |
+	(tmp.tm_mon < 1 )	| (tmp.tm_mon  > 12)   |
+	(tmp.tm_year < 2000)	| (tmp.tm_year > 2500) |
+	(tmp.tm_wday < 1 )	| (tmp.tm_wday > 7)) {
+	log_warn(ERR_RTCTIM);
+	rtc_reset();
+    }
+
+    /*
+     * Now lets do a check to see if the NV RAM is there.
+     */
+    *tchar = 0xaa;
+    if ((*tchar ^ 0xaa) != 0x0) log_err(ERR_RTCVAL);
+    *tchar = 0x55;				/* Reset test address */
+
+} /* rtctest() */
+#endif	/* CONFIG_RTC_M48T35A */
+
+
+#ifdef CONFIG_DTT_LM75
+int dtt_test(int sensor)
+{
+    short temp, trip, hyst;
+
+    /* get values */
+    temp = dtt_read(sensor, DTT_READ_TEMP) / 256;
+    trip = dtt_read(sensor, DTT_TEMP_SET) / 256;
+    hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256;
+
+    /* check values */
+    if ((hyst != (CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS)) ||
+	(trip != CFG_DTT_MAX_TEMP) ||
+	(temp < CFG_DTT_LOW_TEMP) || (temp > CFG_DTT_MAX_TEMP))
+	return 1;
+
+    return 0;
+} /* dtt_test() */
+#endif /* CONFIG_DTT_LM75 */
+
+/*****************************************/
+
+void post2(void)
+{
+#if defined(CONFIG_RTC_M48T35A)
+    rtctest();
+#endif	/* CONFIG_RTC_M48T35A */
+
+#ifdef CONFIG_DTT_LM75
+    log_stat(ERR_TempG);
+    if(dtt_test(2) != 0) log_warn(ERR_Ttest0);
+    if(dtt_test(4) != 0) log_warn(ERR_Ttest1);
+#endif /* CONFIG_DTT_LM75 */
+} /* post2() */
diff --git a/board/w7o/u-boot.lds b/board/w7o/u-boot.lds
new file mode 100755
index 0000000..7e3e15d
--- /dev/null
+++ b/board/w7o/u-boot.lds
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/ppc4xx/start.o	(.text)
+    board/w7o/init.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug
new file mode 100755
index 0000000..a0c72c9
--- /dev/null
+++ b/board/w7o/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/w7o/vpd.c b/board/w7o/vpd.c
new file mode 100755
index 0000000..2ce1568
--- /dev/null
+++ b/board/w7o/vpd.c
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(VXWORKS)
+# include <stdio.h>
+# include <string.h>
+# define CFG_DEF_EEPROM_ADDR 0xa0
+extern char iicReadByte( char, char );
+extern ulong_t crc32( unsigned char *, unsigned long );
+#else
+#include <common.h>
+#endif
+
+#include "vpd.h"
+
+/*
+ * vpd_reader() - reads VPD data from I2C EEPROMS.
+ *                returns pointer to buffer or NULL.
+ */
+static unsigned char *
+vpd_reader(unsigned char *buf, unsigned dev_addr, unsigned off, unsigned count)
+{
+    unsigned offset = off;			/* Calculated offset */
+
+    /*
+     * The main board EEPROM contains
+     * SDRAM SPD in the first 128 bytes,
+     * so skew the offset.
+     */
+    if (dev_addr == CFG_DEF_EEPROM_ADDR)
+	offset += SDRAM_SPD_DATA_SIZE;
+
+    /* Try to read the I2C EEPROM */
+#if defined(VXWORKS)
+    {
+	int i;
+	for( i = 0; i < count; ++i ) {
+	    buf[ i ] = iicReadByte( dev_addr, offset+i );
+	}
+    }
+#else
+    if (eeprom_read(dev_addr, offset, buf, count)) {
+	printf("Failed to read %d bytes from VPD EEPROM 0x%x @ 0x%x\n",
+	       count, dev_addr, offset);
+	return NULL;
+    }
+#endif
+
+    return buf;
+} /* vpd_reader() */
+
+
+/*
+ * vpd_get_packet() - returns next VPD packet or NULL.
+ */
+static vpd_packet_t *vpd_get_packet(vpd_packet_t *vpd_packet)
+{
+    vpd_packet_t *packet = vpd_packet;
+
+    if (packet != NULL) {
+	if (packet->identifier == VPD_PID_TERM)
+	    return NULL;
+	else
+	    packet = (vpd_packet_t *)((char *)packet + packet->size + 2);
+    }
+
+    return packet;
+} /* vpd_get_packet() */
+
+
+/*
+ * vpd_find_packet() - Locates and returns the specified
+ *		       VPD packet or NULL on error.
+ */
+static vpd_packet_t *vpd_find_packet(vpd_t *vpd, unsigned char ident)
+{
+    vpd_packet_t *packet = (vpd_packet_t *)&vpd->packets;
+
+    /* Guaranteed illegal */
+    if (ident == VPD_PID_GI)
+	return NULL;
+
+    /* Scan tuples looking for a match */
+    while ((packet->identifier != ident) &&
+	   (packet->identifier != VPD_PID_TERM))
+	packet = vpd_get_packet(packet);
+
+    /* Did we find it? */
+    if ((packet->identifier) && (packet->identifier != ident))
+	return NULL;
+    return packet;
+}
+
+
+/*
+ * vpd_is_valid() - Validates contents of VPD data
+ *		    in I2C EEPROM.  Returns 1 for
+ *		    success or 0 for failure.
+ */
+static int vpd_is_valid(unsigned dev_addr, unsigned char *buf)
+{
+    unsigned	    num_bytes;
+    vpd_packet_t    *packet;
+    vpd_t	    *vpd = (vpd_t *)buf;
+    unsigned short  stored_crc16, calc_crc16 = 0xffff;
+
+    /* Check Eyecatcher */
+    if (strncmp((char *)(vpd->header.eyecatcher), VPD_EYECATCHER, VPD_EYE_SIZE) != 0) {
+	unsigned offset = 0;
+	if (dev_addr == CFG_DEF_EEPROM_ADDR)
+	    offset += SDRAM_SPD_DATA_SIZE;
+	printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr, offset);
+
+	return 0;
+    }
+
+    /* Check Length */
+    if (vpd->header.size> VPD_MAX_EEPROM_SIZE) {
+	printf("Error: VPD EEPROM 0x%x contains bad size 0x%x\n",
+	       dev_addr, vpd->header.size);
+	return 0;
+    }
+
+    /* Now find the termination packet */
+    if ((packet = vpd_find_packet(vpd, VPD_PID_TERM)) == NULL) {
+	printf("Error: VPD EEPROM 0x%x missing termination packet\n",
+	       dev_addr);
+	return 0;
+    }
+
+    /* Calculate data size */
+    num_bytes = (unsigned long)((unsigned char *)packet -
+				(unsigned char *)vpd + sizeof(vpd_packet_t));
+
+    /* Find stored CRC and clear it */
+    if ((packet = vpd_find_packet(vpd, VPD_PID_CRC)) == NULL) {
+	printf("Error: VPD EEPROM 0x%x missing CRC\n", dev_addr);
+	return 0;
+    }
+    stored_crc16 = *((ushort *)packet->data);
+    *(ushort *)packet->data = 0;
+
+    /* OK, lets calculate the CRC and check it */
+#if defined(VXWORKS)
+    calc_crc16 = (0xffff & crc32(buf, num_bytes));
+#else
+    calc_crc16 = (0xffff & crc32(0, buf, num_bytes));
+#endif
+    *(ushort *)packet->data = stored_crc16;     /* Now restore the CRC */
+    if (stored_crc16 != calc_crc16) {
+	printf("Error: VPD EEPROM 0x%x has bad CRC 0x%x\n",
+	       dev_addr, stored_crc16);
+	return 0;
+    }
+
+    return 1;
+} /* vpd_is_valid() */
+
+
+/*
+ * size_ok() - Check to see if packet size matches
+ *	       size of data we want. Returns 1 for
+ *	       good match or 0 for failure.
+ */
+static int size_ok(vpd_packet_t *packet, unsigned long size)
+{
+    if (packet->size != size) {
+	printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
+	return 0;
+    }
+    return 1;
+} /* size_ok() */
+
+
+/*
+ * strlen_ok() - Check to see if packet size matches
+ *		 strlen of the string we want to populate.
+ *		 Returns 1 for valid length or 0 for failure.
+ */
+static int strlen_ok(vpd_packet_t *packet, unsigned long length)
+{
+    if (packet->size >= length) {
+	printf("VPD Packet 0x%x corrupt.\n", packet->identifier);
+	return 0;
+    }
+    return 1;
+} /* strlen_ok() */
+
+
+/*
+ * get_vpd_data() - populates the passed VPD structure 'vpdInfo'
+ *		    with data obtained from the specified
+ *		    I2C EEPROM 'dev_addr'.  Returns 0 for
+ *		    success or 1 for failure.
+ */
+int vpd_get_data(unsigned char dev_addr, VPD *vpdInfo)
+{
+    unsigned char buf[VPD_EEPROM_SIZE];
+    vpd_t *vpd = (vpd_t *)buf;
+    vpd_packet_t *packet;
+
+    if (vpdInfo == NULL)
+	return 1;
+
+     /*
+      * Fill vpdInfo with 0s to blank out
+      * unused fields, fill vpdInfo->ethAddrs
+      * with all 0xffs so that other's code can
+      * determine how many real Ethernet addresses
+      * there are.  OUIs starting with 0xff are
+      * broadcast addresses, and would never be
+      * permantely stored.
+      */
+    memset((void *)vpdInfo, 0, sizeof(VPD));
+    memset((void *)&vpdInfo->ethAddrs, 0xff, sizeof(vpdInfo->ethAddrs));
+    vpdInfo->_devAddr = dev_addr;
+
+    /* Read the minimum size first */
+    if (vpd_reader(buf, dev_addr, 0, VPD_EEPROM_SIZE) == NULL) {
+	return 1;
+    }
+
+    /* Check validity of VPD data */
+    if (!vpd_is_valid(dev_addr, buf)) {
+	printf("VPD Data is INVALID!\n");
+	return 1;
+    }
+
+    /*
+      * Walk all the packets and populate
+      * the VPD info structure.
+      */
+    packet = (vpd_packet_t *)&vpd->packets;
+    do {
+	switch (packet->identifier) {
+	    case VPD_PID_GI:
+		printf("Error: Illegal VPD value\n");
+		break;
+	    case VPD_PID_PID:
+		if (strlen_ok(packet, MAX_PROD_ID)) {
+		    strncpy(vpdInfo->productId,
+			    (char *)(packet->data), packet->size);
+		}
+		break;
+	    case VPD_PID_REV:
+		if (size_ok(packet, sizeof(char)))
+		    vpdInfo->revisionId = *packet->data;
+		break;
+	    case VPD_PID_SN:
+		if (size_ok(packet, sizeof(unsigned long))) {
+		    vpdInfo->serialNum =
+			*(unsigned long *)packet->data;
+		}
+		break;
+	    case VPD_PID_MANID:
+		if (size_ok(packet, sizeof(unsigned char)))
+		    vpdInfo->manuID = *packet->data;
+		break;
+	    case VPD_PID_PCO:
+		if (size_ok(packet, sizeof(unsigned long))) {
+		    vpdInfo->configOpt =
+			*(unsigned long *)packet->data;
+		}
+		break;
+	    case VPD_PID_SYSCLK:
+		if (size_ok(packet, sizeof(unsigned long)))
+		    vpdInfo->sysClk = *(unsigned long *)packet->data;
+		break;
+	    case VPD_PID_SERCLK:
+		if (size_ok(packet, sizeof(unsigned long)))
+		    vpdInfo->serClk = *(unsigned long *)packet->data;
+		break;
+	    case VPD_PID_FLASH:
+		if (size_ok(packet, 9)) {	/* XXX - hardcoded,
+						   padding in struct */
+		    memcpy(&vpdInfo->flashCfg, packet->data, 9);
+		}
+		break;
+	    case VPD_PID_ETHADDR:
+		memcpy(vpdInfo->ethAddrs, packet->data, packet->size);
+		break;
+	    case VPD_PID_POTS:
+		if (size_ok(packet, sizeof(char)))
+		    vpdInfo->numPOTS = (unsigned)*packet->data;
+		break;
+	    case VPD_PID_DS1:
+		if (size_ok(packet, sizeof(char)))
+		    vpdInfo->numDS1 = (unsigned)*packet->data;
+	    case VPD_PID_GAL:
+	    case VPD_PID_CRC:
+	    case VPD_PID_TERM:
+		break;
+	    default:
+		printf("Warning: Found unknown VPD packet ID 0x%x\n",
+		       packet->identifier);
+		break;
+	}
+    } while ((packet = vpd_get_packet(packet)));
+
+    return 0;
+} /* end get_vpd_data() */
+
+
+/*
+ * vpd_init() - Initialize default VPD environment
+ */
+int vpd_init(unsigned char dev_addr)
+{
+    return (0);
+} /* vpd_init() */
+
+
+/*
+ * vpd_print() - Pretty print the VPD data.
+ */
+void vpd_print(VPD *vpdInfo)
+{
+    const char *const sp    = "";
+    const char *const sfmt  = "%4s%-20s: \"%s\"\n";
+    const char *const cfmt  = "%4s%-20s: '%c'\n";
+    const char *const dfmt  = "%4s%-20s: %ld\n";
+    const char *const hfmt  = "%4s%-20s: %08lX\n";
+    const char *const dsfmt = "%4s%-20s: %d\n";
+    const char *const hsfmt = "%4s%-20s: %04X\n";
+    const char *const dhfmt = "%4s%-20s: %ld (%lX)\n";
+
+    printf("VPD read from I2C device: %02X\n", vpdInfo->_devAddr);
+
+    if (vpdInfo->productId[0])
+	printf(sfmt, sp, "Product ID", vpdInfo->productId);
+    else
+	printf(sfmt, sp, "Product ID", "UNKNOWN");
+
+    if (vpdInfo->revisionId)
+	printf(cfmt, sp, "Revision ID", vpdInfo->revisionId);
+
+    if (vpdInfo->serialNum)
+	printf(dfmt, sp, "Serial Number", vpdInfo->serialNum);
+
+    if (vpdInfo->manuID)
+	printf(dfmt, sp, "Manufacture ID", (long)vpdInfo->manuID);
+
+    if (vpdInfo->configOpt)
+	printf(hfmt, sp, "Configuration", vpdInfo->configOpt);
+
+    if (vpdInfo->sysClk)
+	printf(dhfmt, sp, "System Clock", vpdInfo->sysClk, vpdInfo->sysClk);
+
+    if (vpdInfo->serClk)
+	printf(dhfmt, sp, "Serial Clock", vpdInfo->serClk, vpdInfo->serClk);
+
+    if (vpdInfo->numPOTS)
+	printf(dfmt, sp, "Number of POTS lines", vpdInfo->numPOTS);
+
+    if (vpdInfo->numDS1)
+	printf(dfmt, sp, "Number of DS1s", vpdInfo->numDS1);
+
+    /* Print Ethernet Addresses */
+    if (vpdInfo->ethAddrs[0][0] != 0xff) {
+	int i, j;
+	printf("%4sEtherNet Address(es): ", sp);
+	for (i = 0; i < MAX_ETH_ADDRS; i++) {
+	    if (vpdInfo->ethAddrs[i][0] != 0xff) {
+		for (j = 0; j < 6; j++) {
+		    printf("%02X", vpdInfo->ethAddrs[i][j]);
+		    if (((j + 1) % 6) != 0)
+			printf(":");
+		    else
+			printf(" ");
+		}
+		if (((i + 1) % 3) == 0) printf("\n%24s: ", sp);
+	    }
+	}
+	printf("\n");
+    }
+
+    if (vpdInfo->flashCfg.mfg && vpdInfo->flashCfg.dev) {
+	printf("Main Flash Configuration:\n");
+	printf(hsfmt, sp, "Manufacture ID", vpdInfo->flashCfg.mfg);
+	printf(hsfmt, sp, "Device ID",      vpdInfo->flashCfg.dev);
+	printf(dsfmt, sp, "Device Width",   vpdInfo->flashCfg.devWidth);
+	printf(dsfmt, sp, "Num. Devices",   vpdInfo->flashCfg.numDevs);
+	printf(dsfmt, sp, "Num. Columns",   vpdInfo->flashCfg.numCols);
+	printf(dsfmt, sp, "Column Width",   vpdInfo->flashCfg.colWidth);
+	printf(dsfmt, sp, "WE Data Width",  vpdInfo->flashCfg.weDataWidth);
+    }
+} /* vpd_print() */
diff --git a/board/w7o/vpd.h b/board/w7o/vpd.h
new file mode 100755
index 0000000..1b71c8d
--- /dev/null
+++ b/board/w7o/vpd.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _VPD_H_
+#define _VPD_H_
+
+/*
+ * Main Flash Configuration.
+ */
+typedef struct flashCfg_s {
+    unsigned short mfg;				/* Manufacture ID */
+    unsigned short dev;				/* Device ID */
+    unsigned char devWidth;			/* Device Width */
+    unsigned char numDevs;			/* Number of devices */
+    unsigned char numCols;			/* Number of columns */
+    unsigned char colWidth;			/* Width of a column */
+    unsigned char weDataWidth;			/* Write/Erase Data Width */
+} flashCfg_t;
+
+/*
+ * Vital Product Data - VPD
+ */
+#define MAX_PROD_ID		15
+#define MAX_ETH_ADDRS		10
+typedef unsigned char EthAddr[6];
+typedef struct vpd {
+    unsigned char _devAddr;			/* Device address during read */
+    char productId[MAX_PROD_ID];		/* Product ID */
+    char revisionId;				/* Revision ID as a char */
+    unsigned long serialNum;			/* Serial number */
+    unsigned char  manuID;			/* Manufact ID - byte int */
+    unsigned long configOpt;			/* Config Option - bit field */
+    unsigned long sysClk;			/* System clock in Hertz */
+    unsigned long serClk;			/* Ext. clock in Hertz */
+    flashCfg_t flashCfg;			/* Flash configuration */
+    unsigned long numPOTS;			/* Number of POTS lines */
+    unsigned long numDS1;			/* Number of DS1 circuits */
+    EthAddr ethAddrs[MAX_ETH_ADDRS];		/* Ethernet MAC, 1st = craft */
+} VPD;
+
+
+#define VPD_MAX_EEPROM_SIZE	512		/* Max size VPD EEPROM */
+#define SDRAM_SPD_DATA_SIZE	128		/* Size SPD in VPD EEPROM */
+
+/*
+ * PIDs - Packet Identifiers
+ */
+#define VPD_PID_GI		0x0		/* Guaranted Illegal */
+#define VPD_PID_PID		0x1		/* Product Identifier */
+#define VPD_PID_REV		0x2		/* Product Revision */
+#define VPD_PID_SN		0x3		/* Serial Number */
+#define VPD_PID_MANID		0x4		/* Manufacture ID */
+#define VPD_PID_PCO		0x5		/* Product configuration */
+#define VPD_PID_SYSCLK		0x6		/* System Clock */
+#define VPD_PID_SERCLK		0x7		/* Ser. Clk. Speed in Hertz */
+#define VPD_PID_CRC		0x8		/* VPD CRC */
+#define VPD_PID_FLASH		0x9		/* Flash Configuration */
+#define VPD_PID_ETHADDR		0xA		/* Ethernet Address(es) */
+#define VPD_PID_GAL		0xB		/* Galileo Switch Config */
+#define VPD_PID_POTS		0xC		/* Number of POTS Lines */
+#define VPD_PID_DS1		0xD		/* Number of DS1s */
+#define VPD_PID_TERM		0xFF		/* Termination packet */
+
+/*
+ * VPD - Eyecatcher/Magic
+ */
+#define VPD_EYECATCHER		"W7O"
+#define VPD_EYE_SIZE		3
+typedef struct vpd_header {
+    unsigned char eyecatcher[VPD_EYE_SIZE];	/* eyecatcher - "W7O" */
+    unsigned short size __attribute__((packed)); /* size of EEPROM */
+} vpd_header_t;
+
+
+#define VPD_DATA_SIZE (VPD_MAX_EEPROM_SIZE - SDRAM_SPD_DATA_SIZE - \
+			sizeof(vpd_header_t))
+typedef struct vpd_s {
+    vpd_header_t header;
+    unsigned char packets[VPD_DATA_SIZE];
+} vpd_t;
+
+typedef struct vpd_packet {
+    unsigned char identifier;
+    unsigned char size;
+    unsigned char data[1];
+} vpd_packet_t;
+
+/*
+ * VPD configOpt bit mask
+ */
+#define VPD_HAS_BBRAM		0x1		/* Battery backed SRAM */
+#define VPD_HAS_RTC		0x2		/* Battery backed RTC */
+#define VPD_HAS_EXT_SER_CLK	0x4		/* External serial clock */
+#define VPD_HAS_SER_TRANS_1	0x8		/* COM1 transceiver */
+#define VPD_HAS_SER_TRANS_2	0x10		/* COM2 transceiver */
+#define VPD_HAS_CRAFT_PHY	0x20		/* CRAFT Ethernet */
+#define VPD_HAS_DTT_1		0x40		/* I2C Digital therm. #1 */
+#define VPD_HAS_DTT_2		0x80		/* I2C Digital therm. #2 */
+#define VPD_HAS_1000_UP_LASER	0x100		/* GMM - 1000Mbit Uplink */
+#define VPD_HAS_70KM_UP_LASER	0x200		/* CMM - 70KM Uplink laser */
+#define VPD_HAS_2_UPLINKS	0x400		/* CMM - 2 uplink lasers */
+#define VPD_HAS_FPGA		0x800		/* Has 1 or more FPGAs */
+#define VPD_HAS_DFA		0x1000		/* CLM - Has 2 Fiber Inter. */
+#define VPD_HAS_GAL_SWITCH	0x2000		/* GMM - Has a Gal switch */
+#define VPD_HAS_POTS_LINES	0x4000		/* GMM - Has POTS lines */
+#define VPD_HAS_DS1_CHANNELS	0x8000		/* GMM - Has DS1 channels */
+#define VPD_HAS_CABLE_RETURN	0x10000		/* GBM/GBR - Cable ret. path */
+
+#define VPD_EEPROM_SIZE         (256 - SDRAM_SPD_DATA_SIZE) /* Size EEPROM */
+
+extern int vpd_get_data(unsigned char dev_addr, VPD *vpd);
+extern void vpd_print(VPD *vpdInfo);
+
+#endif /* _VPD_H_ */
diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c
new file mode 100755
index 0000000..c56c269
--- /dev/null
+++ b/board/w7o/w7o.c
@@ -0,0 +1,272 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include "w7o.h"
+#include <asm/processor.h>
+
+#include "vpd.h"
+#include "errors.h"
+#include <watchdog.h>
+
+unsigned long get_dram_size (void);
+
+/*
+ * Macros to transform values
+ * into environment strings.
+ */
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+/* ------------------------------------------------------------------------- */
+
+int board_early_init_f (void)
+{
+#if defined(CONFIG_W7OLMG)
+	/*
+	 * Setup GPIO pins - reset devices.
+	 */
+	out32 (PPC405GP_GPIO0_ODR, 0x10000000);	/* one open drain pin */
+	out32 (PPC405GP_GPIO0_OR, 0x3E000000);	/* set output pins to default */
+	out32 (PPC405GP_GPIO0_TCR, 0x7f800000);	/* setup for output */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) XILINX; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) PCI INT A; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) PCI INT B; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) SAM 2; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) Battery Bad; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
+	 */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,
+					   INT0 highest priority */
+
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+#elif defined(CONFIG_W7OLMC)
+	/*
+	 * Setup GPIO pins
+	 */
+	out32 (PPC405GP_GPIO0_ODR, 0x01800000);	/* XCV Done Open Drain */
+	out32 (PPC405GP_GPIO0_OR, 0x03800000);	/* set out pins to default */
+	out32 (PPC405GP_GPIO0_TCR, 0x66C00000);	/* setup for output */
+
+	/*
+	 * IRQ 0-15  405GP internally generated; active high; level sensitive
+	 * IRQ 16    405GP internally generated; active low; level sensitive
+	 * IRQ 17-24 RESERVED
+	 * IRQ 25 (EXT IRQ 0) DBE 0; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) DBE 1; active low; level sensitive
+	 * IRQ 27 (EXT IRQ 2) DBE 2; active low; level sensitive
+	 * IRQ 28 (EXT IRQ 3) DBE Common; active low; level sensitive
+	 * IRQ 29 (EXT IRQ 4) PCI; active low; level sensitive
+	 * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
+	 * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
+	 */
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+	mtdcr (uicer, 0x00000000);	/* disable all ints */
+
+	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
+	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,
+					   INT0 highest priority */
+
+	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
+
+#else  /* Unknown */
+#    error "Unknown W7O board configuration"
+#endif
+
+	WATCHDOG_RESET ();	/* Reset the watchdog */
+	temp_uart_init ();	/* init the uart for debug */
+	WATCHDOG_RESET ();	/* Reset the watchdog */
+	test_led ();		/* test the LEDs */
+	test_sdram (get_dram_size ());	/* test the dram */
+	log_stat (ERR_POST1);	/* log status,post1 complete */
+	return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+int checkboard (void)
+{
+	VPD vpd;
+
+	puts ("Board: ");
+
+	/* VPD data present in I2C EEPROM */
+	if (vpd_get_data (CFG_DEF_EEPROM_ADDR, &vpd) == 0) {
+		/*
+		 * Known board type.
+		 */
+		if (vpd.productId[0] &&
+		    ((strncmp (vpd.productId, "GMM", 3) == 0) ||
+		     (strncmp (vpd.productId, "CMM", 3) == 0))) {
+
+			/* Output board information on startup */
+			printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
+			return (0);
+		}
+	}
+
+	puts ("### Unknown HW ID - assuming NOTHING\n");
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	return get_dram_size ();
+}
+
+unsigned long get_dram_size (void)
+{
+	int tmp, i, regs[4];
+	int size = 0;
+
+	/* Get bank Size registers */
+	mtdcr (memcfga, mem_mb0cf);	/* get bank 0 config reg */
+	regs[0] = mfdcr (memcfgd);
+
+	mtdcr (memcfga, mem_mb1cf);	/* get bank 1 config reg */
+	regs[1] = mfdcr (memcfgd);
+
+	mtdcr (memcfga, mem_mb2cf);	/* get bank 2 config reg */
+	regs[2] = mfdcr (memcfgd);
+
+	mtdcr (memcfga, mem_mb3cf);	/* get bank 3 config reg */
+	regs[3] = mfdcr (memcfgd);
+
+	/* compute the size, add each bank if enabled */
+	for (i = 0; i < 4; i++) {
+		if (regs[i] & 0x0001) {	/* if enabled, */
+			tmp = ((regs[i] >> (31 - 14)) & 0x7);	/* get size bits */
+			tmp = 0x400000 << tmp;	/* Size bits X 4MB = size */
+			size += tmp;
+		}
+	}
+
+	return size;
+}
+
+int misc_init_f (void)
+{
+	return 0;
+}
+
+static void w7o_env_init (VPD * vpd)
+{
+	/*
+	 * Read VPD
+	 */
+	if (vpd_get_data (CFG_DEF_EEPROM_ADDR, vpd) != 0)
+		return;
+
+	/*
+	 * Known board type.
+	 */
+	if (vpd->productId[0] &&
+	    ((strncmp (vpd->productId, "GMM", 3) == 0) ||
+	     (strncmp (vpd->productId, "CMM", 3) == 0))) {
+		char buf[30];
+		char *eth;
+		char *serial = getenv ("serial#");
+		char *ethaddr = getenv ("ethaddr");
+
+		/* Set 'serial#' envvar if serial# isn't set */
+		if (!serial) {
+			sprintf (buf, "%s-%ld", vpd->productId,
+				 vpd->serialNum);
+			setenv ("serial#", buf);
+		}
+
+		/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
+		eth = (char *)(vpd->ethAddrs[0]);
+		if (ethaddr
+		    && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
+			/* Now setup ethaddr */
+			sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
+				 eth[0], eth[1], eth[2], eth[3], eth[4],
+				 eth[5]);
+			setenv ("ethaddr", buf);
+		}
+	}
+}				/* w7o_env_init() */
+
+
+int misc_init_r (void)
+{
+	VPD vpd;		/* VPD information */
+
+#if defined(CONFIG_W7OLMG)
+	unsigned long greg;	/* GPIO Register */
+
+	greg = in32 (PPC405GP_GPIO0_OR);
+
+	/*
+	 * XXX - Unreset devices - this should be moved into VxWorks driver code
+	 */
+	greg |= 0x41800000L;	/* SAM, PHY, Galileo */
+
+	out32 (PPC405GP_GPIO0_OR, greg);	/* set output pins to default */
+#endif /* CONFIG_W7OLMG */
+
+	/*
+	 * Initialize W7O environment variables
+	 */
+	w7o_env_init (&vpd);
+
+	/*
+	 * Initialize the FPGA(s).
+	 */
+	if (init_fpga () == 0)
+		test_fpga ((unsigned short *) CONFIG_FPGAS_BASE);
+
+	/* More POST testing. */
+	post2 ();
+
+	/* Done with hardware initialization and POST. */
+	log_stat (ERR_POSTOK);
+
+	/* Call silly, fail safe boot init routine */
+	init_fsboot ();
+
+	return (0);
+}
diff --git a/board/w7o/w7o.h b/board/w7o/w7o.h
new file mode 100755
index 0000000..d6f50e2
--- /dev/null
+++ b/board/w7o/w7o.h
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _W7O_H_
+#define _W7O_H_
+#include <config.h>
+
+/* AMCC 405GP PowerPC GPIO registers */
+#define PPC405GP_GPIO0_OR	0xef600700L	/* GPIO Output */
+#define PPC405GP_GPIO0_TCR	0xef600704L	/* GPIO Three-State Control */
+#define PPC405GP_GPIO0_ODR	0xef600718L	/* GPIO Open Drain */
+#define PPC405GP_GPIO0_IR	0xef60071cL	/* GPIO Input */
+
+/* AMCC 405GP DCRs */
+#define CPC0_CR0		0xb1		/* Chip control register 0 */
+
+/* LMG FPGA <=> CPU GPIO signals */
+#define LMG_XCV_INIT		0x10000000L
+#define LMG_XCV_PROG		0x04000000L
+#define LMG_XCV_DONE		0x00400000L
+#define LMG_XCV_CNFG_0		0x08000000L
+#define LMG_XCV_IRQ_0		0x0L
+
+/* LMC FPGA <=> CPU GPIO signals */
+#define LMC_XCV_INIT		0x00800000L
+#define LMC_XCV_PROG		0x40000000L
+#define LMC_XCV_DONE		0x01000000L
+#define LMC_XCV_CNFG_0		0x00004000L	/* Shared with IRQ 0 */
+#define LMC_XCV_CNFG_1		0x00002000L	/* Shared with IRQ 1 */
+#define LMC_XCV_CNFG_2		0x00001000L	/* Shared with IRQ 2 */
+#define LMC_XCV_IRQ_0		0x00080000L	/* Shared with GPIO 17 */
+#define LMC_XCV_IRQ_1		0x00040000L	/* Shared with GPIO 18 */
+#define LMC_XCV_IRQ_3		0x00020000L	/* Shared tiwht GPIO 19 */
+
+
+/*
+ * Setup FPGA <=> GPIO mappings
+ */
+#if defined(CONFIG_W7OLMG)
+# define GPIO_XCV_INIT		LMG_XCV_INIT
+# define GPIO_XCV_PROG		LMG_XCV_PROG
+# define GPIO_XCV_DONE		LMG_XCV_DONE
+# define GPIO_XCV_CNFG		LMG_XCV_CNFG_0
+# define GPIO_XCV_IRQ		LMG_XCV_IRQ_0
+# define GPIO_GPIO_1		0x40000000L
+# define GPIO_GPIO_6		0x02000000L
+# define GPIO_GPIO_7		0x01000000L
+# define GPIO_GPIO_8		0x00800000L
+#elif defined(CONFIG_W7OLMC)
+# define GPIO_XCV_INIT		LMC_XCV_INIT
+# define GPIO_XCV_PROG		LMC_XCV_PROG
+# define GPIO_XCV_DONE		LMC_XCV_DONE
+# define GPIO_XCV_CNFG		LMC_XCV_CNFG_0
+# define GPIO_XCV_IRQ		LMC_XCV_IRQ_0
+#else
+# error "Unknown W7O board configuration"
+#endif
+
+/* Power On Self Tests */
+extern void post2(void);
+extern int test_led(void);
+extern int test_sdram(unsigned long size);
+extern void test_fpga(unsigned short *daddr);
+
+/* FGPA */
+extern int init_fpga(void);
+
+/* Misc */
+extern int temp_uart_init(void);
+extern void init_fsboot(void);
+
+#endif /* _W7O_H_ */
diff --git a/board/w7o/watchdog.c b/board/w7o/watchdog.c
new file mode 100755
index 0000000..4bbd94f
--- /dev/null
+++ b/board/w7o/watchdog.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * W7O board level hardware watchdog.
+ */
+#include <common.h>
+#include <config.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+
+void hw_watchdog_reset(void)
+{
+    volatile ushort *hwd = (ushort *)(CFG_W7O_EBC_PB7CR & 0xfff00000);
+
+    /*
+     * Read the LMG's hwd register and toggle the
+     * watchdog bit to reset it.   On the LMC, just
+     * reading it is enough, but toggling the bit
+     * doen't hurt either.
+     */
+    *hwd = *hwd ^ 0x8000;
+
+} /* hw_watchdog_reset() */
+
+#endif /* CONFIG_HW_WATCHDOG */
diff --git a/board/wepep250/Makefile b/board/wepep250/Makefile
new file mode 100755
index 0000000..11ad8fb
--- /dev/null
+++ b/board/wepep250/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= wepep250.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/wepep250/config.mk b/board/wepep250/config.mk
new file mode 100755
index 0000000..8701581
--- /dev/null
+++ b/board/wepep250/config.mk
@@ -0,0 +1,11 @@
+#
+# This is config used for compilation of WEP EP250 sources
+#
+# You might change location of U-Boot in memory by setting right TEXT_BASE.
+# This allows for example having one copy located at the end of ram and stored
+# in flash device and later on while developing use other location to test
+# the code in RAM device only.
+#
+
+TEXT_BASE = 0xa1fe0000
+#TEXT_BASE = 0xa1001000
diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c
new file mode 100755
index 0000000..2a32290
--- /dev/null
+++ b/board/wepep250/flash.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This code was inspired by Marius Groeger and Kyle Harris code
+ * available in other board ports for U-Boot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ */
+
+#include <common.h>
+#include "intel.h"
+
+
+/*
+ * This code should handle CFI FLASH memory device. This code is very
+ * minimalistic approach without many essential error handling code as well.
+ * Because U-Boot actually is missing smart handling of FLASH device,
+ * we just set flash_id to anything else to FLASH_UNKNOW, so common code
+ * can call us without any restrictions.
+ * TODO: Add CFI Query, to be able to determine FLASH device.
+ * TODO: Add error handling code
+ * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
+ *       hopefully may work with other configurations.
+ */
+
+#if ( WEP_FLASH_BUS_WIDTH == 1 )
+#  define FLASH_BUS vu_char
+#  if ( WEP_FLASH_INTERLEAVE == 1 )
+#    define FLASH_CMD( x ) x
+#  else
+#    error "With 8bit bus only one chip is allowed"
+#  endif
+
+
+#elif ( WEP_FLASH_BUS_WIDTH == 2 )
+#  define FLASH_BUS vu_short
+#  if ( WEP_FLASH_INTERLEAVE == 1 )
+#    define FLASH_CMD( x ) x
+#  elif ( WEP_FLASH_INTERLEAVE == 2 )
+#    define FLASH_CMD( x ) (( x << 8 )| x )
+#  else
+#    error "With 16bit bus only 1 or 2 chip(s) are allowed"
+#  endif
+
+
+#elif ( WEP_FLASH_BUS_WIDTH == 4 )
+#  define FLASH_BUS vu_long
+#  if ( WEP_FLASH_INTERLEAVE == 1 )
+#    define FLASH_CMD( x ) x
+#  elif ( WEP_FLASH_INTERLEAVE == 2 )
+#    define FLASH_CMD( x ) (( x << 16 )| x )
+#  elif ( WEP_FLASH_INTERLEAVE == 4 )
+#    define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
+#  else
+#    error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
+#  endif
+
+#else
+#  error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
+#endif
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+static FLASH_BUS flash_status_reg (void)
+{
+
+	FLASH_BUS *addr = (FLASH_BUS *) 0;
+
+	*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
+
+	return *addr;
+}
+
+static int flash_ready (ulong timeout)
+{
+	int ok = 1;
+
+	reset_timer_masked ();
+	while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
+		   FLASH_CMD (CFI_INTEL_SR_READY)) {
+		if (get_timer_masked () > timeout && timeout != 0) {
+			ok = 0;
+			break;
+		}
+	}
+	return ok;
+}
+
+#if ( CFG_MAX_FLASH_BANKS != 1 )
+#  error "WEP platform has only one flash bank!"
+#endif
+
+
+ulong flash_init (void)
+{
+	int i;
+	FLASH_BUS address = WEP_FLASH_BASE;
+
+	flash_info[0].size = WEP_FLASH_BANK_SIZE;
+	flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
+	flash_info[0].flash_id = INTEL_MANUFACT;
+	memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
+
+	for (i = 0; i < CFG_MAX_FLASH_SECT; i++) {
+		flash_info[0].start[i] = address;
+#ifdef WEP_FLASH_UNLOCK
+		/* Some devices are hw locked after start. */
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
+		flash_ready (0);
+		*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+#endif
+		address += WEP_FLASH_SECT_SIZE;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+				   CFG_FLASH_BASE,
+				   CFG_FLASH_BASE + monitor_flash_len - 1,
+				   &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+				   CFG_ENV_ADDR,
+				   CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return WEP_FLASH_BANK_SIZE;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	printf (" Intel vendor\n");
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if (!(i % 5)) {
+			printf ("\n");
+		}
+
+		printf (" %08lX%s", info->start[i],
+				info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, non_protected = 0, sector;
+	int rc = ERR_OK;
+
+	FLASH_BUS *address;
+
+	for (sector = s_first; sector <= s_last; sector++) {
+		if (!info->protect[sector]) {
+			non_protected++;
+		}
+	}
+
+	if (!non_protected) {
+		return ERR_PROTECTED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+	flag = disable_interrupts ();
+
+
+	/* Start erase on unprotected sectors */
+	for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
+		if (info->protect[sector]) {
+			printf ("Protected sector %2d skipping...\n", sector);
+			continue;
+		} else {
+			printf ("Erasing sector %2d ... ", sector);
+		}
+
+		address = (FLASH_BUS *) (info->start[sector]);
+
+		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
+		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
+		if (flash_ready (CFG_FLASH_ERASE_TOUT)) {
+			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+			printf ("ok.\n");
+		} else {
+			*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+			rc = ERR_TIMOUT;
+			printf ("timeout! Aborting...\n");
+			break;
+		}
+		*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+	}
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+	if (flag) {
+		enable_interrupts ();
+	}
+
+	return rc;
+}
+
+static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
+{
+	FLASH_BUS *address = (FLASH_BUS *) dest;
+	int rc = ERR_OK;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*address & data) != data) {
+		return ERR_NOT_ERASED;
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	flag = disable_interrupts ();
+
+	*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
+	*address = data;
+
+	if (!flash_ready (CFG_FLASH_WRITE_TOUT)) {
+		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+		rc = ERR_TIMOUT;
+		printf ("timeout! Aborting...\n");
+	}
+
+	*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+	if (flag) {
+		enable_interrupts ();
+	}
+
+	return rc;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong read_addr, write_addr;
+	FLASH_BUS data;
+	int i, result = ERR_OK;
+
+
+	read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
+	write_addr = read_addr;
+	if (read_addr != addr) {
+		data = 0;
+		for (i = 0; i < sizeof (FLASH_BUS); i++) {
+			if (read_addr < addr || cnt == 0) {
+				data |= *((uchar *) read_addr) << i * 8;
+			} else {
+				data |= (*src++) << i * 8;
+				cnt--;
+			}
+			read_addr++;
+		}
+		if ((result = write_data (info, write_addr, data)) != ERR_OK) {
+			return result;
+		}
+		write_addr += sizeof (FLASH_BUS);
+	}
+	for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
+		if ((result = write_data (info, write_addr,
+								  *((FLASH_BUS *) src))) != ERR_OK) {
+			return result;
+		}
+		write_addr += sizeof (FLASH_BUS);
+		src += sizeof (FLASH_BUS);
+	}
+	if (cnt > 0) {
+		read_addr = write_addr;
+		data = 0;
+		for (i = 0; i < sizeof (FLASH_BUS); i++) {
+			if (cnt > 0) {
+				data |= (*src++) << i * 8;
+				cnt--;
+			} else {
+				data |= *((uchar *) read_addr) << i * 8;
+			}
+			read_addr++;
+		}
+		if ((result = write_data (info, write_addr, data)) != 0) {
+			return result;
+		}
+	}
+	return ERR_OK;
+}
diff --git a/board/wepep250/intel.h b/board/wepep250/intel.h
new file mode 100755
index 0000000..77498b6
--- /dev/null
+++ b/board/wepep250/intel.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef	FLASH_INTEL_H
+#define	FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define	CFI_CHIP_INTEL_28F320J3A		0x0016
+#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
+#define	CFI_CHIP_INTEL_28F640J3A		0x0017
+#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
+#define	CFI_CHIP_INTEL_28F128J3A		0x0018
+#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define	CFI_CHIP_INTEL_28F640K3			0x8801
+#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
+#define	CFI_CHIP_INTEL_28F128K3			0x8802
+#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
+#define	CFI_CHIP_INTEL_28F256K3			0x8803
+#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
+#define	CFI_CHIP_INTEL_28F640K18		0x8805
+#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
+#define	CFI_CHIP_INTEL_28F128K18		0x8806
+#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
+#define	CFI_CHIP_INTEL_28F256K18		0x8807
+#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
+
+#endif /* FLASH_INTEL_H */
diff --git a/board/wepep250/lowlevel_init.S b/board/wepep250/lowlevel_init.S
new file mode 100755
index 0000000..b172cea
--- /dev/null
+++ b/board/wepep250/lowlevel_init.S
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2001, 2002 ETC s.r.o.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
+ * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ * Documentation:
+ * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
+ *     Developer's Manual", February 2002, Order Number: 278522-001
+ * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
+ *     Revision 1.0, February 2002
+ * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
+ *     Revision 1.0, February 2002
+ *
+*/
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	r10, lr
+
+/*	setup memory - see 6.12 in [1]
+ *	Step 1 	- wait 200 us
+ */
+	mov	r0,#0x2700      		/* wait 200 us @ 99.5 MHz */
+1:	subs	r0, r0, #1
+	bne	1b
+/*	TODO: complete step 1 for Synchronous Static memory*/
+
+	ldr	r0, =0x48000000			/* MC_BASE */
+
+
+/* 	step 1.a - setup MSCx
+ */
+	ldr	r1, =0x000012B3			/* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
+	str	r1, [r0, #0x8]			/* MSC0_OFFSET */
+
+/*	step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
+ *	see AUTO REFRESH chapter in section D. in [2] and in [3]
+ *	DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
+ *	DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
+ *	TODO: complete for Synchronous Static memory
+ */
+	ldr	r1, [r0, #4]			/* MDREFR_OFFSET */
+	ldr	r2, =0x01000FFF			/* MDREFR_K1FREE | MDREFR_DRI_MASK */
+	bic	r1, r1, r2
+#if defined( WEP_SDRAM_K4S281633 )
+	orr	r1, r1, #48			/* MDREFR_DRI(48) */
+#elif defined( WEP_SDRAM_K4S561633 )
+	orr	r1, r1, #24			/* MDREFR_DRI(24) */
+#else
+#error SDRAM chip is not defined
+#endif
+
+	str	r1, [r0, #4]			/* MDREFR_OFFSET */
+
+/*	Step 2 - only for Synchronous Static memory (TODO)
+ *
+ *	Step 3 - same as step 4
+ *
+ *	Step 4
+ *
+ *	Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
+ */
+	orr	r1, r1, #0x00010000		/* MDREFR_K1RUN */
+	bic	r1, r1, #0x00020000		/* MDREFR_K1DB2 */
+	str	r1, [r0, #4]			/* MDREFR_OFFSET */
+
+/*	Step 4.b - clear MDREFR:SLFRSH */
+	bic	r1, r1, #0x00400000		/* MDREFR_SLFRSH */
+	str	r1, [r0, #4]			/* MDREFR_OFFSET */
+
+/*	Step 4.c - set MDREFR:E1PIN */
+	orr	r1, r1, #0x00008000		/* MDREFR_E1PIN */
+	str	r1, [r0, #4]			/* MDREFR_OFFSET */
+
+/*	Step 4.d - automatically done
+ *
+ *	Steps 4.e and 4.f - configure SDRAM
+ */
+#if defined( WEP_SDRAM_K4S281633 )
+	ldr	r1, =0x00000AA8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
+#elif defined( WEP_SDRAM_K4S561633 )
+	ldr	r1, =0x00000AC8			/* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
+#else
+#error SDRAM chip is not defined
+#endif
+	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
+
+/*	Step 5 - wait at least 200 us for SDRAM
+ *	see section B. in [2]
+ */
+	mov	r2,#0x2700      		/* wait 200 us @ 99.5 MHz */
+1:	subs	r2, r2, #1
+	bne	1b
+
+/*	Step 6 - after reset dcache is disabled, so automatically done
+ *
+ *	Step 7 - eight refresh cycles
+ */
+	mov	r2, #0xA0000000
+	ldr	r3, [r2]
+	ldr	r3, [r2]
+	ldr	r3, [r2]
+	ldr	r3, [r2]
+	ldr	r3, [r2]
+	ldr	r3, [r2]
+	ldr	r3, [r2]
+	ldr	r3, [r2]
+
+/*	Step 8 - we don't need dcache now
+ *
+ *	Step 9 - enable SDRAM partition 0
+ */
+	orr	r1, r1, #1			/* MDCNFG_DE0 */
+	str	r1, [r0, #0]			/* MDCNFG_OFFSET */
+
+/*	Step 10 - write MDMRS */
+	mov	r1, #0
+	str	r1, [r0, #0x40]			/* MDMRS_OFFSET */
+
+/*	Step 11 - optional (TODO) */
+
+	mov	pc,r10
diff --git a/board/wepep250/u-boot.lds b/board/wepep250/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/wepep250/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c
new file mode 100755
index 0000000..56cb855
--- /dev/null
+++ b/board/wepep250/wepep250.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+int board_init( void ){
+  DECLARE_GLOBAL_DATA_PTR;
+
+  gd->bd->bi_arch_number = MACH_TYPE_WEP_EP250;
+  gd->bd->bi_boot_params = 0xa0000000;
+/*
+ * Setup GPIO stuff to get serial working
+ */
+#if defined( CONFIG_FFUART )
+  GPDR1   = 0x80;
+  GAFR1_L = 0x8010;
+#elif defined( CONFIG_BTUART )
+  GPDR1   = 0x800;
+  GAFR1_L = 0x900000;
+#endif
+  PSSR    = 0x20;
+
+  return 0;
+}
+
+int dram_init( void ){
+  DECLARE_GLOBAL_DATA_PTR;
+
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+  gd->bd->bi_dram[0].start = WEP_SDRAM_1;
+  gd->bd->bi_dram[0].size  = WEP_SDRAM_1_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 1 )
+  gd->bd->bi_dram[1].start = WEP_SDRAM_2;
+  gd->bd->bi_dram[1].size  = WEP_SDRAM_2_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 2 )
+  gd->bd->bi_dram[2].start = WEP_SDRAM_3;
+  gd->bd->bi_dram[2].size  = WEP_SDRAM_3_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 3 )
+  gd->bd->bi_dram[3].start = WEP_SDRAM_4;
+  gd->bd->bi_dram[3].size  = WEP_SDRAM_4_SIZE;
+#endif
+
+  return 0;
+}
diff --git a/board/westel/amx860/Makefile b/board/westel/amx860/Makefile
new file mode 100755
index 0000000..7a2014d
--- /dev/null
+++ b/board/westel/amx860/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c
new file mode 100755
index 0000000..8826667
--- /dev/null
+++ b/board/westel/amx860/amx860.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFFFFF
+
+const uint edo_60ns[] =
+{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
+  0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
+  0x8fffec24, 0x0ffbec04, 0x08f3ec04, 0x07f3ec08,
+  0x08f3ec04, 0x07f3ec48, 0x08f3ec04, 0x07f3ec48,
+  0x08f3ec04, 0x07f3ec48, 0x1ff7ec47, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
+  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
+  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
+  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: AMX860\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+
+	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	/* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */
+
+	upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
+
+#ifndef CONFIG_AMX_RAM_EXT
+	memctl->memc_mptpr = 0x0400; /* divide by 16 */
+#else
+	memctl->memc_mptpr = 0x0200;
+#endif
+
+	memctl->memc_mamr = 0x30a21114;
+	memctl->memc_or2 = 0xffc00800;
+#ifndef CONFIG_AMX_RAM_EXT
+	memctl->memc_br2 = 0x81;
+
+	return (4 << 20);
+#else
+	memctl->memc_or1 = 0xff000800;
+	memctl->memc_br1 = 0x00000081;
+	memctl->memc_br2 = 0x01000081;
+
+	return (20 << 20);
+#endif
+}
diff --git a/board/westel/amx860/config.mk b/board/westel/amx860/config.mk
new file mode 100755
index 0000000..d0ee4a2
--- /dev/null
+++ b/board/westel/amx860/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#TEXT_BASE = 0xFE000000
+TEXT_BASE = 0x40000000
+OBJCFLAGS =	--set-section-flags=.ppcenv=contents,alloc,load,data
diff --git a/board/westel/amx860/flash.c b/board/westel/amx860/flash.c
new file mode 100755
index 0000000..12a1335
--- /dev/null
+++ b/board/westel/amx860/flash.c
@@ -0,0 +1,637 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*---------------------------------------------------------------------*/
+#undef DEBUG_FLASH
+
+#ifdef DEBUG_FLASH
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+/*---------------------------------------------------------------------*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0, size_b1;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
+
+	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0<<20);
+	}
+
+#if defined(FLASH_BASE1_PRELIM) && (FLASH_BASE1_PRELIM != 0)
+	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
+
+	size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
+
+	if (size_b1 > size_b0) {
+		printf ("## ERROR: "
+			"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
+			size_b1, size_b1<<20,
+			size_b0, size_b0<<20
+		);
+		flash_info[0].flash_id	= FLASH_UNKNOWN;
+		flash_info[1].flash_id	= FLASH_UNKNOWN;
+		flash_info[0].sector_count	= -1;
+		flash_info[1].sector_count	= -1;
+		flash_info[0].size		= 0;
+		flash_info[1].size		= 0;
+		return (0);
+	}
+#else
+	size_b1 = 0;
+#endif	/* FLASH_BASE1_PRELIM */
+
+	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	DEBUGF ("## Before remap: "
+		"BR0: 0x%08x    OR0: 0x%08x    "
+		"BR1: 0x%08x    OR1: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0,
+		memctl->memc_br1, memctl->memc_or1);
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+
+	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
+		memctl->memc_br0, memctl->memc_or0);
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size_b0;
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+
+	if (size_b1) {
+		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK);
+		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+				   BR_MS_GPCM | BR_V;
+
+		DEBUGF("## BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+
+		/* Re-do sizing to get full correct info */
+		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+					  &flash_info[1]);
+
+		flash_info[1].size = size_b1;
+
+		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+
+# if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		/* monitor protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_MONITOR_BASE,
+			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      &flash_info[1]);
+# endif
+
+# ifdef CFG_ENV_IS_IN_FLASH
+		/* ENV protection ON by default */
+		flash_protect(FLAG_PROTECT_SET,
+			      CFG_ENV_ADDR,
+			      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+			      &flash_info[1]);
+#endif
+	} else {
+#ifndef CONFIG_AMX_RAM_EXT
+		memctl->memc_br1 = 0;		/* invalidate bank */
+		memctl->memc_or1 = 0;		/* invalidate bank */
+#endif
+
+		DEBUGF("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
+			memctl->memc_br1, memctl->memc_or1);
+
+		flash_info[1].flash_id = FLASH_UNKNOWN;
+		flash_info[1].sector_count = -1;
+		flash_info[1].size = 0;
+	}
+
+	DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		/* set sector offsets for uniform sector type	*/
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00040000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_BM:	printf ("BRIGHT MICRO ");	break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:	printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+				break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	DEBUGF("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	DEBUGF("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case AMD_ID_F040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+
+	case AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+
+	case AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+
+	case AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+#if 0	/* enable when device IDs are available */
+	case AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+
+	case AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00800000;
+		break;				/* => 8 MB		*/
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type	*/
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x0000C000;
+		info->start[3] = base + 0x00010000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000) - 0x00060000;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000C000;
+		info->start[i--] = base + info->size - 0x00010000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00020000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds
new file mode 100755
index 0000000..cdf550f
--- /dev/null
+++ b/board/westel/amx860/u-boot.lds
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug
new file mode 100755
index 0000000..87f228b
--- /dev/null
+++ b/board/westel/amx860/u-boot.lds.debug
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/wmt/Makefile b/board/wmt/Makefile
new file mode 100755
index 0000000..2600357
--- /dev/null
+++ b/board/wmt/Makefile
@@ -0,0 +1,60 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# Some descriptions of such software. Copyright (c) 2008 WonderMedia Technologies, Inc.
+#
+# This program is free software: you can redistribute it and/or modify it under the
+# terms of the GNU General Public License as published by the Free Software Foundation,
+# either version 2 of the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+# WonderMedia Technologies, Inc.
+# 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= wmt.o flash.o main.o \
+           flash/spi_flash_lock.o flash/spi_flash.o flash/nand_flash.o \
+           wmt_clk.o env.o ehci-hcd.o usb_uhci.o wmt_i2c.o wmt_i2c_1.o \
+           wmt_i2c_2.o wmt_i2c_3.o wmt_spi_0.o wmt_ost.o wmt_gpio.o poweroff.o \
+           wmt_battery/wmt_battery.o \
+           wmt_battery/charger/g2214/g2214_charger.o \
+           wmt_battery/charger/mp2625/mp2625_charger.o \
+           wmt_battery/gauge/upi/uG31xx_API_Measurement.o \
+           wmt_battery/gauge/upi/uG31xx_API_Otp.o \
+           wmt_battery/gauge/upi/uG31xx_API_System.o \
+           wmt_battery/gauge/upi/ug31xx_boot.o \
+           wmt_battery/gauge/upi/ug31xx_boot_i2c.o \
+           wmt_battery/gauge/vt1603/vt1603_battery.o \
+           wmt_battery/gauge/sp2541/sp2541_battery.o \
+           wmt_battery/gauge/bq27541/bq_battery_i2c.o \
+	   vt1603/snd-vt1603.o
+
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/wmt/config.mk b/board/wmt/config.mk
new file mode 100755
index 0000000..b194377
--- /dev/null
+++ b/board/wmt/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2002-2004
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# Some descriptions of such software. Copyright (c) 2008 WonderMedia Technologies, Inc.
+#
+# This program is free software: you can redistribute it and/or modify it under the
+# terms of the GNU General Public License as published by the Free Software Foundation,
+# either version 2 of the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+# WonderMedia Technologies, Inc.
+# 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+#
+# WMT project EVB (ARM920T-Like)
+#
+# Suppose WMT has 1 bank of 64 MB DDR-SDRAM
+#
+# 0000'0000 to 0400'0000
+#
+# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000
+# optionally with a ramdisk at 0200'0000
+#
+# we load ourself to 03F8'0000
+#
+#
+TEXT_BASE = 0x03F80000
diff --git a/board/wmt/ehci-core.h b/board/wmt/ehci-core.h
new file mode 100755
index 0000000..39e5c5e
--- /dev/null
+++ b/board/wmt/ehci-core.h
@@ -0,0 +1,29 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Skåne AB
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_CORE_H
+#define USB_EHCI_CORE_H
+
+extern int rootdev;
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+
+#endif
diff --git a/board/wmt/ehci-hcd.c b/board/wmt/ehci-hcd.c
new file mode 100755
index 0000000..6360a44
--- /dev/null
+++ b/board/wmt/ehci-hcd.c
@@ -0,0 +1,1262 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Skåne AB
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ *
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/byteorder.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <watchdog.h>
+
+#include "ehci.h"
+#include "env.h" 
+/*
+*CharlesTu,2011.03.30,support uboot usb storage ehci driver.
+*/
+#ifdef CONFIG_USB_EHCI
+#undef USB_EHCI_DEBUG
+#ifdef	USB_EHCI_DEBUG
+#define	USB_EHCI_PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define USB_EHCI_PRINTF(fmt,args...)
+#endif
+extern int wmt_read_ostc(int *val);
+unsigned char usb_sel = 2;
+unsigned char ConnectPort = 2;
+unsigned char port_connect_status = 0;
+unsigned int MaxDevice;
+int rootdev;
+int usb_flag = 0;
+int pipe_flag = 0;
+int inquiry_flag = 0;
+int length_flag = 0;
+struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
+struct ehci_hcor *hcor;
+struct usb_operation_t g_usb_param;
+
+static uint16_t portreset;
+static struct QH qh_list __attribute__((aligned(32)));
+
+static struct descriptor {
+	struct usb_hub_descriptor hub;
+	struct usb_device_descriptor device;
+	struct usb_linux_config_descriptor config;
+	struct usb_linux_interface_descriptor interface;
+	struct usb_endpoint_descriptor endpoint;
+}  __attribute__ ((packed)) descriptor = {
+	{
+		0x8,		/* bDescLength */
+		0x29,		/* bDescriptorType: hub descriptor */
+		2,		/* bNrPorts -- runtime modified */
+		0,		/* wHubCharacteristics */
+		0xff,		/* bPwrOn2PwrGood */
+		0,		/* bHubCntrCurrent */
+		{},		/* Device removable */
+		{}		/* at most 7 ports! XXX */
+	},
+	{
+		0x12,		/* bLength */
+		1,		/* bDescriptorType: UDESC_DEVICE */
+		cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
+		9,		/* bDeviceClass: UDCLASS_HUB */
+		0,		/* bDeviceSubClass: UDSUBCLASS_HUB */
+		1,		/* bDeviceProtocol: UDPROTO_HSHUBSTT */
+		64,		/* bMaxPacketSize: 64 bytes */
+		0x0000,		/* idVendor */
+		0x0000,		/* idProduct */
+		cpu_to_le16(0x0100), /* bcdDevice */
+		1,		/* iManufacturer */
+		2,		/* iProduct */
+		0,		/* iSerialNumber */
+		1		/* bNumConfigurations: 1 */
+	},
+	{
+		0x9,
+		2,		/* bDescriptorType: UDESC_CONFIG */
+		cpu_to_le16(0x19),
+		1,		/* bNumInterface */
+		1,		/* bConfigurationValue */
+		0,		/* iConfiguration */
+		0x40,		/* bmAttributes: UC_SELF_POWER */
+		0		/* bMaxPower */
+	},
+	{
+		0x9,		/* bLength */
+		4,		/* bDescriptorType: UDESC_INTERFACE */
+		0,		/* bInterfaceNumber */
+		0,		/* bAlternateSetting */
+		1,		/* bNumEndpoints */
+		9,		/* bInterfaceClass: UICLASS_HUB */
+		0,		/* bInterfaceSubClass: UISUBCLASS_HUB */
+		0,		/* bInterfaceProtocol: UIPROTO_HSHUBSTT */
+		0		/* iInterface */
+	},
+	{
+		0x7,		/* bLength */
+		5,		/* bDescriptorType: UDESC_ENDPOINT */
+		0x81,		/* bEndpointAddress:
+				 * UE_DIR_IN | EHCI_INTR_ENDPT
+				 */
+		3,		/* bmAttributes: UE_INTERRUPT */
+		8,		/* wMaxPacketSize */
+		255		/* bInterval */
+	},
+};
+
+#if defined(CONFIG_EHCI_IS_TDI)
+#define ehci_is_TDI()	(1)
+#else
+#define ehci_is_TDI()	(0)
+#endif
+
+#if defined(CONFIG_EHCI_DCACHE)
+/*
+ * Routines to handle (flush/invalidate) the dcache for the QH and qTD
+ * structures and data buffers. This is needed on platforms using this
+ * EHCI support with dcache enabled.
+ */
+static void flush_invalidate(u32 addr, int size, int flush)
+{
+	if (flush)
+		flush_dcache_range(addr, addr + size);
+	else
+		invalidate_dcache_range(addr, addr + size);
+}
+
+static void cache_qtd(struct qTD *qtd, int flush)
+{
+	u32 *ptr = (u32 *)qtd->qt_buffer[0];
+	int len = (qtd->qt_token & 0x7fff0000) >> 16;
+
+	flush_invalidate((u32)qtd, sizeof(struct qTD), flush);
+	if (ptr && len)
+		flush_invalidate((u32)ptr, len, flush);
+}
+
+
+static inline struct QH *qh_addr(struct QH *qh)
+{
+	return (struct QH *)((u32)qh & 0xffffffe0);
+}
+
+static void cache_qh(struct QH *qh, int flush)
+{
+	struct qTD *qtd;
+	struct qTD *next;
+	static struct qTD *first_qtd;
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	/*
+	 * Walk the QH list and flush/invalidate all entries
+	 */
+	while (1) {
+		flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush);
+		if ((u32)qh & QH_LINK_TYPE_QH)
+			break;
+		qh = qh_addr(qh);
+		qh = (struct QH *)qh->qh_link;
+	}
+	qh = qh_addr(qh);
+
+	/*
+	 * Save first qTD pointer, needed for invalidating pass on this QH
+	 */
+	if (flush)
+		first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay &
+						 0xffffffe0);
+	else
+		qtd = first_qtd;
+
+	/*
+	 * Walk the qTD list and flush/invalidate all entries
+	 */
+	while (1) {
+		if (qtd == NULL)
+			break;
+		cache_qtd(qtd, flush);
+		next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0);
+		if (next == qtd)
+			break;
+		qtd = next;
+	}
+}
+
+static inline void ehci_flush_dcache(struct QH *qh)
+{
+	cache_qh(qh, 1);
+}
+
+static inline void ehci_invalidate_dcache(struct QH *qh)
+{
+	cache_qh(qh, 0);
+}
+#else /* CONFIG_EHCI_DCACHE */
+/*
+ *
+ */
+static inline void ehci_flush_dcache(struct QH *qh)
+{
+}
+
+static inline void ehci_invalidate_dcache(struct QH *qh)
+{
+}
+#endif /* CONFIG_EHCI_DCACHE */
+
+static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
+{
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	uint32_t result;
+	do {
+		result = ehci_readl(ptr);
+		udelay(5);
+		if (result == ~(uint32_t)0)
+			return -1;
+		result &= mask;
+		if (result == done)
+			return 0;
+		usec--;
+	} while (usec > 0);
+	return -1;
+}
+
+static void ehci_free(void *p, size_t sz)
+{
+
+}
+
+static int ehci_reset(void)
+{
+	uint32_t cmd;
+	uint32_t tmp;
+	uint32_t *reg_ptr;
+	int ret = 0;
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	cmd = ehci_readl(&hcor->or_usbcmd);
+	cmd = (cmd & ~CMD_RUN) | CMD_RESET;
+	ehci_writel(&hcor->or_usbcmd, cmd);
+	ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
+	if (ret < 0) {
+		printf("EHCI fail to reset\n");
+		goto out;
+	}
+
+	if (ehci_is_TDI()) {
+		reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
+		tmp = ehci_readl(reg_ptr);
+		tmp |= USBMODE_CM_HC;
+#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
+		tmp |= USBMODE_BE;
+#endif
+		ehci_writel(reg_ptr, tmp);
+	}
+out:
+	return ret;
+}
+
+static void *ehci_alloc(size_t sz, size_t align)
+{
+	static struct QH qh __attribute__((aligned(32)));
+	static struct qTD td[3] __attribute__((aligned (32)));
+	static int ntds;
+	void *p;
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	switch (sz) {
+	case sizeof(struct QH):
+		p = &qh;
+		ntds = 0;
+		break;
+	case sizeof(struct qTD):
+		if (ntds == 3) {
+			debug("out of TDs\n");
+			return NULL;
+		}
+		p = &td[ntds];
+		ntds++;
+		break;
+	default:
+		debug("unknown allocation size\n");
+		return NULL;
+	}
+
+	memset(p, 0, sz);
+	return p;
+}
+
+static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
+{
+	uint32_t addr, delta, next;
+	int idx;
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	addr = (uint32_t) buf;
+	idx = 0;
+	while (idx < 5) {
+		td->qt_buffer[idx] = cpu_to_hc32(addr);
+		td->qt_buffer_hi[idx] = 0;
+		next = (addr + 4096) & ~4095;
+		delta = next - addr;
+		if (delta >= sz)
+			break;
+		sz -= delta;
+		addr = next;
+		idx++;
+	}
+
+	if (idx == 5) {
+		debug("out of buffer pointers (%u bytes left)\n", sz);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int
+ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int length, struct devrequest *req)
+{
+	struct QH *qh;
+	struct qTD *td;
+	struct qTD *td_setup;
+	struct qTD *td_data;
+	struct qTD *td_ack;
+	uint32_t *tdp;
+	uint32_t endpt, token, usbsts;
+	uint32_t c, toggle;
+	uint32_t cmd;
+	int  maxsize=64;
+	
+	td_setup = NULL;
+	td_data = NULL;
+	td_ack = NULL;
+	
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+	/*Support new tool chain arm_1103_le-, set maxpacket  issue.*/
+	/*			
+	maxsize = usb_maxpacket(dev, pipe); 
+	if (usb_maxpacket(dev, pipe) < 0x40)
+	maxsize = 0x40;
+	*/
+	if (usb_pipetype(pipe) == PIPE_BULK) 
+		maxsize = 512;
+	if (usb_pipetype(pipe) == PIPE_CONTROL) 
+		maxsize = 64;
+
+	debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p ,maxsize=%d\n", dev, pipe,
+	      buffer, length, req, maxsize);
+	
+	if (req != NULL)
+		debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
+			req->request, req->request,
+			req->requesttype, req->requesttype,
+			le16_to_cpu(req->value), le16_to_cpu(req->value),
+			le16_to_cpu(req->index));
+
+	qh = ehci_alloc(sizeof(struct QH), 32);
+	if (qh == NULL) {
+		debug("unable to allocate QH\n");
+		return -1;
+	}
+	
+	qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
+	c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
+	     usb_pipeendpoint(pipe) == 0) ? 1 : 0;
+		endpt = (8 << 28) |
+		(c << 27) |
+		maxsize << 16 |
+		(0 << 15) |
+		(1 << 14) |
+		(usb_pipespeed(pipe) << 12) |
+		(usb_pipeendpoint(pipe) << 8) |
+		(0 << 7) | (usb_pipedevice(pipe) << 0);
+		qh->qh_endpt1 = cpu_to_hc32(endpt);
+		endpt = (1 << 30) |
+		(dev->portnr << 23) | (0 << 8) | (0 << 0);
+    	 
+	qh->qh_endpt2 = cpu_to_hc32(endpt);
+	qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+
+	td = NULL;
+	
+	tdp = &qh->qh_overlay.qt_next;
+
+	toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
+
+	if (req != NULL) {
+		td_setup = ehci_alloc(sizeof(struct qTD), 32);
+		if (td_setup == NULL) {
+			debug("unable to allocate SETUP td\n");
+			goto fail;
+		}
+		td_setup->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+		td_setup->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+		token = (0 << 31) |
+		    (sizeof(*req) << 16) |
+		    (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
+		td_setup->qt_token = cpu_to_hc32(token);
+		USB_EHCI_PRINTF("td->qt_token 1 : %x \n",td_setup->qt_token);
+		
+		if (ehci_td_buffer(td_setup, req, sizeof(*req)) != 0) {
+			debug("unable construct SETUP td\n");
+			ehci_free(td, sizeof(*td_setup));
+			goto fail;
+		}
+		
+		*tdp = cpu_to_hc32((uint32_t) td_setup);
+		tdp = &td_setup->qt_next;
+		toggle = 1;
+		
+#ifdef	USB_EHCI_DEBUG
+		usb_display_td(td_setup);
+#endif
+	}
+
+	if (length > 0 || req == NULL) {
+		length_flag = length;
+		td_data = ehci_alloc(sizeof(struct qTD), 32);
+		if (td_data == NULL) {
+			debug("unable to allocate DATA td\n");
+			goto fail;
+		}
+		td_data->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+		td_data->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+		token = (toggle << 31) |
+		    (length << 16) |
+		    (0 << 12) |
+		    (3 << 10) |
+		    ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
+		td_data->qt_token = cpu_to_hc32(token);
+		USB_EHCI_PRINTF("td->qt_token 2 : %x \n",td_data->qt_token);
+
+		if (ehci_td_buffer(td_data, buffer, length) != 0) {
+			debug("unable construct DATA td\n");
+			ehci_free(td_data, sizeof(*td_data));
+			goto fail;
+		}
+		*tdp = cpu_to_hc32((uint32_t) td_data);
+		tdp = &td_data->qt_next;
+#ifdef	USB_EHCI_DEBUG
+		usb_display_td(td_data);
+#endif
+
+	}
+
+	if (req != NULL) {
+		td_ack = ehci_alloc(sizeof(struct qTD), 32);
+
+		if (td_ack == NULL) {
+			debug("unable to allocate ACK td\n");
+			goto fail;
+		}
+		td_ack->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+		td_ack->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+		token = (toggle << 31) |
+		    (0 << 16) |
+		    (0 << 12) |
+		    (3 << 10) |
+		    ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
+		td_ack->qt_token = cpu_to_hc32(token);
+		USB_EHCI_PRINTF("td->qt_token 3 : %x \n", td_ack->qt_token);
+
+		*tdp = cpu_to_hc32((uint32_t) td_ack);
+		tdp = &td_ack->qt_next;
+#ifdef	USB_EHCI_DEBUG
+		usb_display_td(td_ack);
+#endif
+
+	}
+
+	qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
+
+	usbsts = ehci_readl(&hcor->or_usbsts);
+	ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
+
+	/* Enable async. schedule. */
+	cmd = ehci_readl(&hcor->or_usbcmd);
+	cmd |= CMD_ASE;
+	ehci_writel(&hcor->or_usbcmd, cmd);
+
+	USB_EHCI_PRINTF("qh->qh_link %x,qh->qh_endpt1 %x qh->qh_endpt2 %x qh->qh_overlay.qt_next %x\n",
+		qh->qh_link,qh->qh_endpt1,qh->qh_endpt2,qh->qh_overlay.qt_next);
+	/*polling qtd active status*/
+	
+	if (pipe_flag == usb_bulk_pipe) {		
+			usb_check_bulk_td(td_data); 			
+	} else if  (pipe_flag == usb_ctl_pipe)
+		usb_check_td(td_ack);
+	qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
+
+	token = hc32_to_cpu(qh->qh_overlay.qt_token);
+	if (!(token & 0x80)) {
+		debug("TOKEN=%#x\n", token);
+		switch (token & 0xfc) {
+		case 0:
+			toggle = token >> 31;
+			usb_settoggle(dev, usb_pipeendpoint(pipe),
+				       usb_pipeout(pipe), toggle);
+			dev->status = 0;
+			break;
+		case 0x40:
+			dev->status = USB_ST_STALLED;
+			break;
+		case 0xa0:
+		case 0x20:
+			dev->status = USB_ST_BUF_ERR;
+			break;
+		case 0x50:
+		case 0x10:
+			dev->status = USB_ST_BABBLE_DET;
+			break;
+		default:
+			dev->status = USB_ST_CRC_ERR;
+			if ((token & 0x40) == 0x40)
+				dev->status |= USB_ST_STALLED;
+			break;
+		}
+		dev->act_len = length - ((token >> 16) & 0x7fff);
+	} else {
+		dev->act_len = 0;
+		debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
+		      dev->devnum, ehci_readl(&hcor->or_usbsts),
+		      ehci_readl(&hcor->or_portsc[0]),
+		      ehci_readl(&hcor->or_portsc[1]));
+	}
+
+	return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
+
+fail:
+	td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
+	while (td != (void *)QT_NEXT_TERMINATE) {
+		qh->qh_overlay.qt_next = td->qt_next;
+		ehci_free(td, sizeof(*td));
+		td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
+	}
+	ehci_free(qh, sizeof(*qh));
+	return -1;
+}
+
+static inline int min3(int a, int b, int c)
+{
+
+	if (b < a)
+		a = b;
+	if (c < a)
+		a = c;
+	return a;
+}
+
+int
+ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
+		 int length, struct devrequest *req)
+{
+	uint8_t tmpbuf[4];
+	u16 typeReq;
+	void *srcptr = NULL;
+	int len, srclen;
+	uint32_t reg;
+	uint32_t *status_reg;
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
+		printf("The request port(%d) is not configured\n",
+			le16_to_cpu(req->index) - 1);
+		return -1;
+	}
+	status_reg = (uint32_t *)&hcor->or_portsc[
+						le16_to_cpu(req->index) - 1];
+	srclen = 0;
+
+	debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
+	      req->request, req->request,
+	      req->requesttype, req->requesttype,
+	      le16_to_cpu(req->value), le16_to_cpu(req->index));
+
+	typeReq = req->request | req->requesttype << 8;
+
+	switch (typeReq) {
+	case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
+		switch (le16_to_cpu(req->value) >> 8) {
+		case USB_DT_DEVICE:
+			debug("USB_DT_DEVICE request\n");
+			srcptr = &descriptor.device;
+			srclen = 0x12;
+			break;
+		case USB_DT_CONFIG:
+			debug("USB_DT_CONFIG config\n");
+			srcptr = &descriptor.config;
+			srclen = 0x19;
+			break;
+		case USB_DT_STRING:
+			debug("USB_DT_STRING config\n");
+			switch (le16_to_cpu(req->value) & 0xff) {
+			case 0:	/* Language */
+				srcptr = "\4\3\1\0";
+				srclen = 4;
+				break;
+			case 1:	/* Vendor */
+				srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
+				srclen = 14;
+				break;
+			case 2:	/* Product */
+				srcptr = "\52\3E\0H\0C\0I\0 "
+					 "\0H\0o\0s\0t\0 "
+					 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
+				srclen = 42;
+				break;
+			default:
+				debug("unknown value DT_STRING %x\n",
+					le16_to_cpu(req->value));
+				goto unknown;
+			}
+			break;
+		default:
+			debug("unknown value %x\n", le16_to_cpu(req->value));
+			goto unknown;
+		}
+		break;
+	case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
+		switch (le16_to_cpu(req->value) >> 8) {
+		case USB_DT_HUB:
+			debug("USB_DT_HUB config\n");
+			srcptr = &descriptor.hub;
+			srclen = 0x8;
+			break;
+		default:
+			debug("unknown value %x\n", le16_to_cpu(req->value));
+			goto unknown;
+		}
+		break;
+	case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
+		debug("USB_REQ_SET_ADDRESS\n");
+		rootdev = le16_to_cpu(req->value);
+		break;
+	case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
+		debug("USB_REQ_SET_CONFIGURATION\n");
+		/* Nothing to do */
+		break;
+	case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
+		tmpbuf[0] = 1;	/* USB_STATUS_SELFPOWERED */
+		tmpbuf[1] = 0;
+		srcptr = tmpbuf;
+		srclen = 2;
+		break;
+	case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
+		memset(tmpbuf, 0, 4);
+		reg = ehci_readl(status_reg);
+		if (reg & EHCI_PS_CS)
+			tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
+		if (reg & EHCI_PS_PE)
+			tmpbuf[0] |= USB_PORT_STAT_ENABLE;
+		if (reg & EHCI_PS_SUSP)
+			tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
+		if (reg & EHCI_PS_OCA)
+			tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
+		if (reg & EHCI_PS_PR)
+			tmpbuf[0] |= USB_PORT_STAT_RESET;
+		if (reg & EHCI_PS_PP)
+			tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
+
+		if (ehci_is_TDI()) {
+			switch ((reg >> 26) & 3) {
+			case 0:
+				break;
+			case 1:
+				tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
+				break;
+			case 2:
+			default:
+				tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
+				break;
+			}
+		} else {
+			tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
+		}
+
+		if (reg & EHCI_PS_CSC)
+			tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
+		if (reg & EHCI_PS_PEC)
+			tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
+		if (reg & EHCI_PS_OCC)
+			tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
+		if (portreset & (1 << le16_to_cpu(req->index)))
+			tmpbuf[2] |= USB_PORT_STAT_C_RESET;
+
+		srcptr = tmpbuf;
+		srclen = 4;
+		break;
+	case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
+		reg = ehci_readl(status_reg);
+		reg &= ~EHCI_PS_CLEAR;
+		switch (le16_to_cpu(req->value)) {
+		case USB_PORT_FEAT_ENABLE:
+			reg |= EHCI_PS_PE;
+			ehci_writel(status_reg, reg);
+			break;
+		case USB_PORT_FEAT_POWER:
+			if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
+				reg |= EHCI_PS_PP;
+				ehci_writel(status_reg, reg);
+			}
+			break;
+		case USB_PORT_FEAT_RESET:
+			if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
+			    !ehci_is_TDI() &&
+			    EHCI_PS_IS_LOWSPEED(reg)) {
+				/* Low speed device, give up ownership. */
+				debug("port %d low speed --> companion\n",
+				      req->index - 1);
+				reg |= EHCI_PS_PO;
+				ehci_writel(status_reg, reg);
+				break;
+			} else {
+				int ret;
+
+				reg |= EHCI_PS_PR;
+				reg &= ~EHCI_PS_PE;
+				ehci_writel(status_reg, reg);
+				/*
+				 * caller must wait, then call GetPortStatus
+				 * usb 2.0 specification say 50 ms resets on
+				 * root
+				 */
+				wait_ms(50);
+				/* terminate the reset */
+				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
+				/*
+				 * A host controller must terminate the reset
+				 * and stabilize the state of the port within
+				 * 2 milliseconds
+				 */
+				ret = handshake(status_reg, EHCI_PS_PR, 0,
+						2 * 1000);
+				if (!ret)
+					portreset |=
+						1 << le16_to_cpu(req->index);
+				else
+					printf("port(%d) reset error\n",
+					le16_to_cpu(req->index) - 1);
+			}
+			break;
+		default:
+			debug("unknown feature %x\n", le16_to_cpu(req->value));
+			goto unknown;
+		}
+		/* unblock posted writes */
+		(void) ehci_readl(&hcor->or_usbcmd);
+		break;
+	case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
+		reg = ehci_readl(status_reg);
+		switch (le16_to_cpu(req->value)) {
+		case USB_PORT_FEAT_ENABLE:
+			reg &= ~EHCI_PS_PE;
+			break;
+		case USB_PORT_FEAT_C_ENABLE:
+			reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
+			break;
+		case USB_PORT_FEAT_POWER:
+			if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
+				reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
+		case USB_PORT_FEAT_C_CONNECTION:
+			reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
+			break;
+		case USB_PORT_FEAT_OVER_CURRENT:
+			reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
+			break;
+		case USB_PORT_FEAT_C_RESET:
+			portreset &= ~(1 << le16_to_cpu(req->index));
+			break;
+		default:
+			debug("unknown feature %x\n", le16_to_cpu(req->value));
+			goto unknown;
+		}
+		ehci_writel(status_reg, reg);
+		/* unblock posted write */
+		(void) ehci_readl(&hcor->or_usbcmd);
+		break;
+	default:
+		debug("Unknown request\n");
+		goto unknown;
+	}
+
+	wait_ms(1);
+	len = min3(srclen, le16_to_cpu(req->length), length);
+	if (srcptr != NULL && len > 0)
+		memcpy(buffer, srcptr, len);
+	else
+		debug("Len is 0\n");
+
+	dev->act_len = len;
+	dev->status = 0;
+	return 0;
+
+unknown:
+	debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
+	      req->requesttype, req->request, le16_to_cpu(req->value),
+	      le16_to_cpu(req->index), le16_to_cpu(req->length));
+
+	dev->act_len = 0;
+	dev->status = USB_ST_STALLED;
+	return -1;
+}
+
+int usb_lowlevel_stop(void)
+{
+	return ehci_hcd_stop();
+}
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	hccr = (struct ehci_hccr *)(0xd8007900);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr + 0x10);
+
+	USB_EHCI_PRINTF("ehci init hccr %x and hcor %x hc_length %d\n",
+		(uint32_t)hccr, (uint32_t)hcor,
+		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	
+	return 0;
+}
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+ 	ehci_reset();
+	return 0;
+}
+/*simple function to string*/
+unsigned char strtochar(unsigned char Value)
+{
+	unsigned char HexValue, CharValue;	
+	CharValue = Value -0x30 ;
+	if(CharValue <= 9)	{
+		HexValue = CharValue ;
+		return HexValue;
+	} else {
+		printf("Warning !, please setenv  uboot_usb 1 or 2 or 4 or 8. \n");
+		return USB_PORT_B;
+	}
+	
+}
+
+#define  usb_env_name  "wmt.usb.param"
+int usb_lowlevel_init(void)
+{
+	uint32_t reg;
+	uint32_t cmd;
+     	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	/*default uhci 1 port B */
+	usb_sel = USB_PORT_B;
+	if (parse_usb_param(usb_env_name) == 0) {
+		if(g_usb_param.port_num <= 0x03 ) {
+			usb_sel = 1 << g_usb_param.port_num;
+		} 
+	} else {
+		return -1;
+	}
+	
+     	
+	/*disable USB gpio*/
+	/* *((unsigned char *)0xd811007c) &= ~0xFF;*/
+	 REG_SET8(0xd811007c,0);
+	*((unsigned int *)0xd81100BC) &= ~0xFF;
+	*((unsigned char *)0xd81104BC) = 0x3C; /* disable USBOC pull up/down */  
+	*((unsigned char *)0xd81104FC) = 0x3C; /* USBOC pull down*/	
+
+	if (ehci_hcd_init() != 0)
+		goto uhci;
+
+	/* EHCI spec section 4.1 */
+	if (ehci_reset() != 0)
+		goto uhci;
+	
+      /* EHCI spec section 4.1 */
+	if (usb_ehci_initial() != USB_TEST_SUCCESS)
+		goto uhci;
+	
+	/* Set head of reclaim list */
+	memset(&qh_list, 0, sizeof(qh_list));
+	qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
+	qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
+	qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
+	qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
+	qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
+	qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
+
+	/* Set async. queue head pointer. */
+	ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
+
+	reg = ehci_readl(&hccr->cr_hcsparams);
+	descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
+	USB_EHCI_PRINTF("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
+	/* Port Indicators */
+	if (HCS_INDICATOR(reg))
+		descriptor.hub.wHubCharacteristics |= 0x80;
+	/* Port Power Control */
+	if (HCS_PPC(reg))
+		descriptor.hub.wHubCharacteristics |= 0x01;
+
+	/* Start the host controller. */
+	cmd = ehci_readl(&hcor->or_usbcmd);
+	/*
+	 * Philips, Intel, and maybe others need CMD_RUN before the
+	 * root hub will detect new devices (why?); NEC doesn't
+	 */
+	cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
+	cmd |= CMD_RUN;
+	ehci_writel(&hcor->or_usbcmd, cmd);
+
+	/* take control over the ports */
+	cmd = ehci_readl(&hcor->or_configflag);
+	cmd |= FLAG_CF;
+	ehci_writel(&hcor->or_configflag, cmd);
+	/* unblock posted write */
+	cmd = ehci_readl(&hcor->or_usbcmd);
+	//wait_ms(5);
+	reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
+	USB_EHCI_PRINTF("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
+
+	rootdev = 0;
+	usb_flag = usb_ehci_flag;
+	return 0;
+uhci: 
+	ehci_disable_port_owner();
+	if (uhci_lowlevel_init() != 0)
+		return -1;
+	return 0;
+}
+
+void ehci_config_port_owner()
+{
+	volatile unsigned int  temp32;
+	pEHCIOPRegister pEhciOPRegs = (pEHCIOPRegister) (BA_EHCI_REG + 0x10);
+     	USB_EHCI_PRINTF("%s\n", __FUNCTION__);
+
+	temp32 = REG_GET32((BA_EHCI_REG + 0x50));
+
+	if (temp32 != 0x00000001)
+		REG_SET32((BA_EHCI_REG + 0x50), 0x00000001);
+	temp32 = REG_GET32((BA_EHCI_REG + 0x50));
+	while (temp32 != 0x00000001) {
+		temp32 = REG_GET32((BA_EHCI_REG + 0x50));
+	}
+
+	if (usb_sel & 0x01) {
+	
+		pEhciOPRegs->Port[0].PortOwer = 0;
+		pEhciOPRegs->Port[1].PortOwer = 1;
+		pEhciOPRegs->Port[2].PortOwer = 1;
+		pEhciOPRegs->Port[3].PortOwer = 1;
+		ConnectPort = 0;
+		printf("usb select port A\n");
+
+	} else if (usb_sel & 0x02) {
+	
+		pEhciOPRegs->Port[0].PortOwer = 1;
+		pEhciOPRegs->Port[1].PortOwer = 0;
+		pEhciOPRegs->Port[2].PortOwer = 1;
+		pEhciOPRegs->Port[3].PortOwer = 1;
+		ConnectPort = 1;
+		printf("usb select port B\n");
+
+	} else if (usb_sel & 0x04) {
+	
+		pEhciOPRegs->Port[0].PortOwer = 1;
+		pEhciOPRegs->Port[1].PortOwer = 1;
+		pEhciOPRegs->Port[2].PortOwer = 0;
+		pEhciOPRegs->Port[3].PortOwer = 1;
+		ConnectPort = 2;
+		printf("usb select port C\n");
+
+	} else if (usb_sel & 0x08) {
+		pEhciOPRegs->Port[0].PortOwer = 1;
+		pEhciOPRegs->Port[1].PortOwer = 1;
+		pEhciOPRegs->Port[2].PortOwer = 1;
+		pEhciOPRegs->Port[3].PortOwer = 0;
+		ConnectPort = 3;
+		printf("usb select port D\n");
+
+	}	 
+	USB_EHCI_PRINTF("ConnectPort:%x\n",ConnectPort);
+		wait_ms(20);	
+
+	USB_EHCI_PRINTF("ehci_config_port_owner()  EHCI CONFIGFLAG = 1 OK!\n");
+}
+
+void ehci_disable_port_owner()
+{
+	volatile unsigned int  temp32;
+	pEHCIOPRegister pEhciOPRegs = (pEHCIOPRegister) (BA_EHCI_REG + 0x10);
+     	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	temp32 = REG_GET32((BA_EHCI_REG + 0x50));
+
+	if (temp32 == 0x00000001)
+		REG_SET32((BA_EHCI_REG + 0x50), 0);
+	temp32 = REG_GET32((BA_EHCI_REG + 0x50));
+	while (temp32 == 1) {
+		temp32 = REG_GET32((BA_EHCI_REG + 0x50));
+	}
+
+	pEhciOPRegs->Port[0].PortOwer = 1;
+	pEhciOPRegs->Port[1].PortOwer = 1;
+	pEhciOPRegs->Port[2].PortOwer = 1;
+	pEhciOPRegs->Port[3].PortOwer = 1;
+		
+	wait_ms(20);	
+
+	USB_EHCI_PRINTF("ehci_disable_port_owner()  EHCI CONFIGFLAG = 0 \n");
+}
+
+int ehci_detect_device()
+{
+	pHCCapability   pEhciCapRegs   =  (pHCCapability) CapRegBase;
+	pEHCIOPRegister pEhciOPRegs  =  (pEHCIOPRegister) OpRegBase;
+	int PortCount;
+	int i, j = 0, detect = 0;
+      port_connect_status=0;
+	/*printf("ehci_detect_device\n");*/
+
+	PortCount = pEhciCapRegs->HCSParams.N_Ports;
+
+	USB_EHCI_PRINTF("EHCI PortCount = 0x%02X\n", PortCount);
+
+	for (i = 0; i < PortCount; i++)  {
+		if (pEhciOPRegs->Port[i].CurrentConStatus) {
+			j++;
+			detect = 1;
+			ConnectPort  =  i;
+			USB_EHCI_PRINTF("EHCI ConnectPort = 0x%02X\n", ConnectPort);
+			break;
+		}
+
+		MaxDevice = j;
+	}
+	/*detect empty port*/
+	for (i = 0; i < PortCount; i++)  {
+		if (pEhciOPRegs->Port[i].CurrentConStatus) {
+			port_connect_status = 1 << i;
+			
+		}
+	}
+	
+	if (detect  ==  1)
+		return USB_TEST_SUCCESS;
+	else
+		return USB_TEST_FAIL;
+
+}
+
+int ehci_enable_port()
+{
+	pEHCIOPRegister pEhciOPRegs  =  (pEHCIOPRegister) OpRegBase;
+     	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+
+	if (pEhciOPRegs->Port[ConnectPort].CurrentConStatus == 0)
+		return USB_TEST_FAIL;
+	if (pEhciOPRegs->CommandReg.RunStop == 0)
+		pEhciOPRegs->CommandReg.RunStop = 1;
+	wait_ms(1);
+
+	/* issue the port reset */
+
+	pEhciOPRegs->Port[ConnectPort].PortEnDisable  =  0;
+	wait_ms(10);
+	pEhciOPRegs->Port[ConnectPort].PortReset  =  1;
+	/* pEhciOPRegs->Port[ConnectPort].PortEnDisable = 0; */
+	wait_ms(10);
+	/* stop port reset */
+	pEhciOPRegs->Port[ConnectPort].PortReset  =  0;
+	while (pEhciOPRegs->Port[ConnectPort].PortReset)
+		;
+	wait_ms(1);/*need wait port enable*/
+     	USB_EHCI_PRINTF("0x%x, 0x%x\n", pEhciOPRegs->Port[ConnectPort], ConnectPort);
+
+	if (pEhciOPRegs->Port[ConnectPort].PortEnDisable)
+		return USB_TEST_SUCCESS;
+
+	return USB_TEST_FAIL;
+}
+
+unsigned char usb_ehci_initial(void)
+{
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+	ehci_config_port_owner();
+	if (ehci_detect_device() == USB_TEST_SUCCESS)  {			
+		if (ehci_enable_port() == USB_TEST_FAIL)  {
+			USB_EHCI_PRINTF("[EHCI] ehci_enable_port() Fail?\n");
+			return USB_TEST_FAIL;
+		} else {			
+			USB_EHCI_PRINTF("[EHCI] ehci_enable_port() OK!\n");
+		}
+			return USB_TEST_SUCCESS;
+	} else
+		return USB_TEST_FAIL;
+}
+
+int
+submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		int length)
+{
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+	pipe_flag = usb_bulk_pipe;
+	if (usb_pipetype(pipe) != PIPE_BULK) {
+		debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
+		return -1;
+	}
+	return ehci_submit_async(dev, pipe, buffer, length, NULL);
+}
+
+int
+submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int length, struct devrequest *setup)
+{
+	USB_EHCI_PRINTF("%s\n",__FUNCTION__);
+	pipe_flag = usb_ctl_pipe;
+
+	if (usb_pipetype(pipe) != PIPE_CONTROL) {
+		debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
+		return -1;
+	}
+
+	return ehci_submit_async(dev, pipe, buffer, length, setup);
+}
+
+int
+submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+	       int length, int interval)
+{
+
+	debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
+	      dev, pipe, buffer, length, interval);
+	return -1;
+}
+
+
+#ifdef	USB_EHCI_DEBUG
+
+int usb_display_td(struct qTD *td)
+{
+	unsigned long tmp;
+
+	printf("TD at %p:\n",td);
+
+	printf("td->qt_next %08x td->qt_altnext %08x td->qt_token %08x td->qt_buffer[0] %08x\n",
+		swap_32(td->qt_next),
+		swap_32(td->qt_altnext),
+		swap_32(td->qt_token),
+		swap_32(td->qt_buffer[0]));
+	if (td->qt_buffer [1])
+		printf("  p1=%08x p2=%08x p3=%08x p4=%08x\n",
+			swap_32(td->qt_buffer [1]),
+			swap_32(td->qt_buffer [2]),
+			swap_32(td->qt_buffer [3]),
+			swap_32(td->qt_buffer [4]));
+
+	tmp=swap_32(td->qt_next);
+	printf("Link points to 0x%08lX, first %s\n",tmp&0xfffffff0,		
+		((tmp & 0x1)==0x1) ? "invalid" : "valid");
+	
+	tmp=swap_32(td->qt_token);
+	printf(" %s %s %s %s %s %s\n     Total bytes  0x%lX\n",
+		(((tmp>>15)&0x1)==0x1) ? "IOC " : "",
+		(((tmp>>7)&0x1)==0x1) ? "Active " : "Inactive ",
+		(((tmp>>6)&0x1)==0x1) ? "Stalled" : "",
+		(((tmp>>5)&0x1)==0x1) ? "Data Buffer Error" : "",
+		(((tmp>>4)&0x1)==0x1) ? "Babble" : "",
+		(((tmp>>3)&0x1)==0x1) ? "XactErr" : "",
+		(tmp>>16&0x7fff));
+		
+	return 0;
+}
+#endif
+
+int usb_check_td(struct qTD *td)
+{
+	 int start_time, end_time;
+	wmt_read_ostc(&start_time); 
+	while ((( swap_32(td->qt_token) >> 7) & 0x1) == 0x1) {
+			
+			if (((swap_32(td->qt_token) >> 7) & 0x1) == 0)	{
+				break;
+			}
+		wmt_read_ostc(&end_time); 
+		if ((end_time - start_time) > 2000000)
+			break;
+	}	
+	return 0;
+}
+int usb_check_bulk_td(struct qTD *td)
+{
+	 int start_time, end_time;
+	wmt_read_ostc(&start_time); 
+	while (((swap_32(td->qt_token) >> 7) & 0x1) == 0x1){						 
+			if (((swap_32(td->qt_token) >> 7) & 0x1) == 0) {
+				break;
+			}				
+			wmt_read_ostc(&end_time); 
+			if ((end_time - start_time) > 2000000)
+				break;
+	}
+	length_flag = 0;
+	return 0;
+}
+
+int parse_usb_param(char *name)
+{   
+	unsigned char idx_max = 4;
+	char *p;
+	char ps[idx_max];
+	char * endp;
+	int i = 0;
+
+	p = getenv(name);
+	if (!p) {
+		printf("please set %s !\n", name);
+		return -1;
+	} else
+		printf("wmt.usb.param: %s\n", p);
+
+	while (i < idx_max) {
+		ps[i++] = simple_strtoul(p, &endp, 16);
+		if (*endp == '\0')
+			break;
+		p = endp + 1;
+		if (*p == '\0')
+			break;        
+	}
+	g_usb_param.enable = ps[0];
+	g_usb_param.port_num = ps[1];
+
+	return 0;
+}
+
+#endif 
diff --git a/board/wmt/ehci.h b/board/wmt/ehci.h
new file mode 100755
index 0000000..6300699
--- /dev/null
+++ b/board/wmt/ehci.h
@@ -0,0 +1,368 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_H
+#define USB_EHCI_H
+//Charles
+#ifndef BYTE
+#define BYTE            unsigned char
+#endif
+
+#ifndef WORD
+#define WORD            unsigned short
+#endif
+
+#ifndef DWORD
+#define DWORD           unsigned long
+#endif
+
+#define CONFIG_SYS_HZ		1000
+#define BA_EHCI_PCI      0xD8007800 /* USB 2.0 EHCI USB Host Configuration Base Address */
+#define BA_EHCI_REG      0xD8007900 /* USB 2.0 EHCI USB Host Register Base Address */
+#define CapRegBase BA_EHCI_REG
+#define OpRegBase  (BA_EHCI_REG + 0x10)
+
+#define USB_TEST_SUCCESS        0
+#define USB_TEST_FAIL           1
+#define USB_TEST_TIMEOUT        2
+
+/* Basic Define*/
+#define REG32               *(volatile unsigned int *)
+#define REG16               *(volatile unsigned short *)
+#define REG8                *(volatile unsigned char *)
+#define REG_GET32(addr)		( REG32(addr) )		/* Read 32 bits Register */
+#define REG_GET16(addr)		( REG16(addr) )		/* Read 16 bits Register */
+#define REG_GET8(addr)		( REG8(addr) )		/* Read  8 bits Register */
+#define REG_SET32(addr, val)	( REG32(addr) = (val) )	/* Write 32 bits Register */
+#define REG_SET16(addr, val)	( REG16(addr) = (val) )	/* Write 16 bits Register */
+#define REG_SET8(addr, val)	( REG8(addr)  = (val) )	/* Write  8 bits Register */
+
+#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	4
+#endif
+
+/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/*
+ * Register Space.
+ */
+struct ehci_hccr {
+	uint32_t cr_capbase;
+#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+	uint32_t cr_hcsparams;
+#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
+#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
+	uint32_t cr_hccparams;
+	uint8_t cr_hcsp_portrt[8];
+} __attribute__ ((packed));
+
+struct ehci_hcor {
+	uint32_t or_usbcmd;
+#define CMD_PARK	(1 << 11)		/* enable "park" */
+#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
+#define CMD_ASE		(1 << 5)		/* async schedule enable */
+#define CMD_LRESET	(1 << 7)		/* partial reset */
+#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
+#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
+#define CMD_RESET	(1 << 1)		/* reset HC not bus */
+#define CMD_RUN		(1 << 0)		/* start/stop HC */
+	uint32_t or_usbsts;
+#define	STD_ASS		(1 << 15)
+#define STS_HALT	(1 << 12)
+	uint32_t or_usbintr;
+#define INTR_UE         (1 << 0)                /* USB interrupt enable */
+#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
+#define INTR_PCE        (1 << 2)                /* Port change detect enable */
+#define INTR_SEE        (1 << 4)                /* system error enable */
+#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
+	uint32_t or_frindex;
+	uint32_t or_ctrldssegment;
+	uint32_t or_periodiclistbase;
+	uint32_t or_asynclistaddr;
+	uint32_t _reserved_[9];
+	uint32_t or_configflag;
+#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
+	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+	uint32_t or_systune;
+} __attribute__ ((packed));
+
+#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
+#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
+#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
+
+/* Interface descriptor */
+struct usb_linux_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+} __attribute__ ((packed));
+
+/* Configuration descriptor information.. */
+struct usb_linux_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+} __attribute__ ((packed));
+
+#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
+#define	ehci_readl(x)		(*((volatile u32 *)(x)))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#else
+#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
+					cpu_to_le32(((volatile u32)b)))
+#endif
+
+#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define hc32_to_cpu(x)		be32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_be32((x))
+#else
+#define hc32_to_cpu(x)		le32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_le32((x))
+#endif
+
+#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
+#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
+#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
+#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS		(3 << 10)	/* RO line status */
+#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
+
+/*
+ * Schedule Interface Space.
+ *
+ * IMPORTANT: Software must ensure that no interface data structure
+ * reachable by the EHCI host controller spans a 4K page boundary!
+ *
+ * Periodic transfers (i.e. isochronous and interrupt transfers) are
+ * not supported.
+ */
+
+/* Queue Element Transfer Descriptor (qTD). */
+struct qTD {
+	/* this part defined by EHCI spec */
+	uint32_t qt_next;		/* see EHCI 3.5.1 */
+#define	QT_NEXT_TERMINATE	1
+	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
+	uint32_t qt_token;		/* see EHCI 3.5.3 */
+	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
+	uint32_t qt_buffer_hi[5];	/* Appendix B */
+	/* pad struct for 32 byte alignment */
+	uint32_t unused[3];
+};
+
+/* Queue Head (QH). */
+struct QH {
+	uint32_t qh_link;
+#define	QH_LINK_TERMINATE	1
+#define	QH_LINK_TYPE_ITD	0
+#define	QH_LINK_TYPE_QH		2
+#define	QH_LINK_TYPE_SITD	4
+#define	QH_LINK_TYPE_FSTN	6
+	uint32_t qh_endpt1;
+	uint32_t qh_endpt2;
+	uint32_t qh_curtd;
+	struct qTD qh_overlay;
+	/*
+	 * Add dummy fill value to make the size of this struct
+	 * aligned to 32 bytes
+	 */
+	uint8_t fill[16];
+};
+//Charles
+typedef struct _HCSPARAMS {
+	DWORD    N_Ports:4;
+	DWORD    PortPowerControl:1;
+	DWORD    Reserved1:2;
+	DWORD    PortRouteRule:1;/*bit 7*/
+	DWORD    NumberPortPerCC:4;/*bit 8-11*/
+	DWORD    NumberOfCC:4;/*bit 12-15*/
+	DWORD    PortIndicator:1;/*bit 16*/
+	DWORD    Reserved2:3;/*bit 17-19*/
+	DWORD    DebugPortNum:4;/*bit 20-23*/
+	DWORD    Reserved3:8;/*bit 24-31*/
+} __attribute__ ((packed))  HCSPARAMS, *pHCSPARAMS;
+
+typedef struct _HCCPARAMS {
+	DWORD    _64BitAddress:1;/*bit 0*/
+	DWORD    ProgrammableFrameList:1;/*bit 1*/
+	DWORD    Reserved1:2;/*bit 2-3*/
+	DWORD    IsoScheduleThreshold:4;/*bit 4-7*/
+	DWORD    Reserved2:24;/* bit 8-31*/
+} __attribute__ ((packed))  HCCPARAMS, *pHCCPARAMS;
+
+typedef struct _HostControllerCapability {
+	BYTE     CapLength;/*byte 0*/
+	BYTE     Reserved;/*byte 1*/
+	WORD     HCIVersion;/*byte 2*/
+	HCSPARAMS HCSParams;/*byte 4*/
+	HCCPARAMS HCCParams;/*byte 8*/
+	BYTE     PortRoute[15];/*byte c-1b*/
+} HCCapability, *pHCCapability;
+
+typedef struct _EHCICommand {
+	DWORD   RunStop:1;/*bit 0*/
+	DWORD   HCReset:1;/*bit 1*/
+	DWORD   FrameListSize:2;/*bit 2-3*/
+	DWORD   PeriodicEnable:1;/*bit 4*/
+	DWORD   AsynchronousEnable:1;/*bit 5*/
+	DWORD   IntOnAsyAdvDoorbell:1;/*bit 6*/
+	DWORD   LightHCReset:1;/*bit 7*/
+	DWORD   Reserved1:8;/*bit 8-15*/
+	DWORD   InterruptThreshold:8;/*bit 16-23*/
+	DWORD   Reserved2:8;/*bit 24-31*/
+}  __attribute__ ((packed)) EHCICommand, *pEHCICommand;
+
+typedef struct _EHCIStatus {
+	DWORD    USBInt:1;/* bit 0*/
+	DWORD    USBErrInt:1;/* bit 1*/
+	DWORD    PortChangeDetect:1;/* bit 2*/
+	DWORD    FrameListRollover:1;/* bit 3*/
+	DWORD    HostSysErr:1;/* bit 4*/
+	DWORD    IntOnAsyncAdv:1;/* bit 5*/
+	DWORD    Reserved1:6;/* bit 6-11*/
+	DWORD    HCHalted:1;/* bit 12*/
+	DWORD    Reclamation:1;/* bit 13*/
+	DWORD    PeriodicSchStatus:1;/* bit 14*/
+	DWORD    AsyncSchStatus:1;/* bit 15*/
+	DWORD    Reserved2:16;/* bit 16-31*/
+} __attribute__ ((packed))  EHCIStatus, *pEHCIStatus;
+
+typedef struct _EHCIIntEnable {
+	DWORD    USBIntEnable:1;/* bit 0*/
+	DWORD    USBErrIntEnable:1;/* bit 1*/
+	DWORD    PortChgIntEnable:1;/* bit 2*/
+	DWORD    FrameListROEnable:1;/* bit 3*/
+	DWORD    HostSysErrEnable:1;/* bit 4*/
+	DWORD    IntOnAsyncAdvEnable:1;/* bit 5*/
+	DWORD    Reserved:26;/* bit 6-31*/
+}  __attribute__ ((packed)) EHCIIntEnable, *pEHCIIntEnable;
+
+typedef struct _EHCIConfigFlag {
+	DWORD    ConfigFlag:1;/* bit 0*/
+	DWORD    Reserved:31;/* bit 1-31*/
+} __attribute__ ((packed)) EHCIConfigFlag, *pEHCIConfigFlag;
+
+typedef struct _EHCIPortControlStatus {
+	DWORD   CurrentConStatus:1;/* bit 0*/
+	DWORD   ConnectStatusChg:1;/* bit 1*/
+	DWORD   PortEnDisable:1;/* bit 2*/
+	DWORD   PortEnDisChg:1;/* bit 3*/
+	DWORD   OverCurrentActive:1;/* bit 4*/
+	DWORD   OverCurrentChg:1;/* bit 5*/
+	DWORD   ForcePortResume:1;/* bit 6*/
+	DWORD   Suspend:1;/* bit 7*/
+	DWORD   PortReset:1;/* bit 8*/
+	DWORD   HighSpdDevice:1;/* bit 9*/
+	DWORD   LineStatus:2;/* bit 10-11*/
+	DWORD   PortPower:1;/* bit 12*/
+	DWORD   PortOwer:1;/* bit 13*/
+	DWORD   PortIndicatorControl:2;/* bit 14-15*/
+	DWORD   PortTestControl:4;/* bit 16-19*/
+	DWORD   WakeOnConEnable:1;/* bit 20*/
+	DWORD   WakeOnDisconEnable:1;/* bit 21*/
+	DWORD   WakeOnOverCurrentEnable:1;/* bit 22*/
+	DWORD   Reserved:9;/* bit 23-31*/
+} __attribute__ ((packed)) EHCIPortCtrlStatus, *pEHCIPortCtrlStatus;
+
+typedef struct _EHCIOperationalReg {
+	EHCICommand     CommandReg;/* byte 00*/
+	EHCIStatus      StatusReg;/* byte 04*/
+	EHCIIntEnable   IntEnableReg;/* byte 08*/
+	DWORD           FrameIndex;/* byte 0c*/
+	DWORD           CTRLSegment;/* byte 10*/
+	DWORD           PeriodicBase;/* byte 14*/
+	DWORD           AsyncBase;/* byte 18*/
+	DWORD           Reserved[9];/* byte 1C-3F*/
+	EHCIConfigFlag  ConfigFlag;/* byte 40*/
+	EHCIPortCtrlStatus Port[10];/* byte 44*/
+} __attribute__ ((packed)) EHCIOPRegister, *pEHCIOPRegister;
+
+/* Low level init functions */
+int ehci_hcd_init(void);
+int ehci_hcd_stop(void);
+void ehci_config_port_owner(void);
+int ehci_detect_device(void);
+int ehci_enable_port(void);
+unsigned char usb_ehci_initial(void);
+unsigned char strtochar(unsigned char Value);
+
+#define	IRQ_UHDC             43
+#define   USB_PORT_A 1
+#define   USB_PORT_B 2
+#define   USB_PORT_C 4
+#define   USB_PORT_D 8
+
+#ifdef	USB_UHCI_DEBUG
+int usb_display_td(struct qTD *td);
+#endif
+
+int usb_check_td(struct qTD *td);
+int usb_check_bulk_td(struct qTD *td);
+int parse_usb_param(char *name);
+struct usb_operation_t {
+	unsigned char enable;
+	unsigned char port_num;	
+};
+
+
+#endif /* USB_EHCI_H */
diff --git a/board/wmt/env.c b/board/wmt/env.c
new file mode 100755
index 0000000..fb10833
--- /dev/null
+++ b/board/wmt/env.c
@@ -0,0 +1,337 @@
+/*
+ * This file is derived from crc32.c in U-Boot 1.1.4.
+ * For conditions of distribution and use, see copyright in crc32.c
+ */
+
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+//#include <stdio.h>
+//#include <stdarg.h>
+//#include <stdlib.h>
+//#include <string.h>
+#include <malloc.h>
+#include "env.h"
+#ifndef NULL
+#define NULL	0
+#endif
+#define printf(...)
+const unsigned int sf_crc_table[256] = {
+  0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419,
+  0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4,
+  0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07,
+  0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
+  0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856,
+  0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
+  0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4,
+  0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+  0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3,
+  0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a,
+  0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599,
+  0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+  0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190,
+  0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f,
+  0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e,
+  0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
+  0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed,
+  0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+  0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3,
+  0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
+  0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a,
+  0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5,
+  0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010,
+  0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+  0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17,
+  0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6,
+  0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615,
+  0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
+  0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344,
+  0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
+  0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a,
+  0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+  0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1,
+  0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c,
+  0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef,
+  0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+  0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe,
+  0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31,
+  0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c,
+  0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
+  0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b,
+  0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
+  0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1,
+  0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
+  0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278,
+  0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7,
+  0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66,
+  0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+  0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605,
+  0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8,
+  0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b,
+  0x2d02ef8d
+};
+
+#define DO1(buf) crc = sf_crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8);
+#define DO2(buf)  do { DO1(buf); DO1(buf); } while (0)
+#define DO4(buf)  do { DO2(buf); DO2(buf); } while (0)
+#define DO8(buf)  do { DO4(buf); DO4(buf); } while (0)
+/* ========================================================================= */
+unsigned int char2int(char c)
+{
+	switch (c) {
+	case '0':
+		return 0;
+	case '1':
+		return 1;
+	case '2':
+		return 2;
+	case '3':
+		return 3;
+	case '4':
+		return 4;
+	case '5':
+		return 5;
+	case '6':
+		return 6;
+	case '7':
+		return 7;
+	case '8':
+		return 8;
+	case '9':
+		return 9;
+	case 'A':
+	case 'a':
+		return 10;
+	case 'B':
+	case 'b':
+		return 11;
+	case 'C':
+	case 'c':
+		return 12;
+	case 'D':
+	case 'd':
+		return 13;
+	case 'E':
+	case 'e':
+		return 14;
+	case 'F':
+	case 'f':
+		return 15;
+	}
+    return c;
+}
+
+int env_find_env(char *name, char *buf, struct env_para_def *para)
+{
+	unsigned int env_name_pos = 0;
+	unsigned int env_para_pos = 0;
+	unsigned int pos = 0;
+
+	if (name == NULL) {
+		printf(" name is NULL\n");
+		return -1;
+	}
+	env_name_pos = 5;
+	while (1) {
+		if (env_cmp_name(env_name_pos, buf, name) == 0) {
+			env_para_pos = env_find_para_pos(env_name_pos, buf);
+			pos = env_para_pos;
+			while (buf[pos])
+				pos++;
+			para->size = pos-env_para_pos;
+			para->npos = env_name_pos;
+			para->ppos = env_para_pos;
+			if (para->size) {
+				para->value = malloc(para->size+1);
+				memset(para->value, 0, para->size+1);
+				memcpy(para->value, &buf[env_para_pos], para->size+1);
+			}
+			return 0;
+		}
+		env_name_pos = env_find_next_pos(env_name_pos, buf);
+		if (!buf[env_name_pos]) {
+			printf(" %s can not found.....\n", name);
+			/* free(buf); */
+			return -1;
+		}
+	}
+}
+
+unsigned int sf_env_crc32(unsigned char *buf)
+{
+	unsigned int crc = 0;
+	unsigned int len = 0xfffb;
+
+	crc = crc ^ 0xffffffff;
+	while (len >= 8) {
+		DO8(buf);
+		len -= 8;
+	}
+	if (len)
+		do {
+			DO1(buf);
+		} while (--len);
+
+	return crc ^ 0xffffffff;
+}
+
+char test_name[100];
+
+int env_cmp_name(unsigned int pos, char *buf, char *name)
+{
+	unsigned int cnt, cnt1;
+	int mach;
+	unsigned int tmppos = 0;
+	unsigned int tmpcnt = 0;
+
+	memset(test_name, 0, 50);
+	tmppos = pos;
+	while (buf[tmppos] != '=') {
+		tmpcnt++;
+		tmppos++;
+	}
+	memcpy(test_name, &buf[pos], tmpcnt);
+	printf(" %s   %s ", name, test_name);
+	cnt1 = 0;
+	while (name[cnt1])
+		cnt1++;
+	mach = 1;
+	cnt = 0;
+	while (1) {
+		if (name[cnt] != buf[pos])
+			mach = 0;
+		if (!mach)
+			break;
+		cnt++;
+		pos++;
+		if ((name[cnt] == 0) || (buf[pos] == '=')) {
+			if ((cnt != cnt1) || (buf[pos] != '='))
+				mach = 0;
+			break;
+		}
+	}
+	if (mach) {
+		printf("..... found\n");
+		return 0;
+	}
+	printf("....... not found\n");
+	return -1;
+}
+
+unsigned int env_find_next_pos(unsigned int pos, char *buf)
+{
+	while (buf[pos])
+		pos++;
+	return pos+1;
+}
+
+unsigned int env_find_para_pos(unsigned int pos, char *buf)
+{
+	while (buf[pos] != '=')
+		pos++;
+	return pos+1;
+}
+
+char *sf_env_init(unsigned int *pos)
+{
+	unsigned int start = 0xfffd0000;
+	char env_sel;
+	char *buf;
+
+	env_sel = *(char *)(start+4);
+	if (!env_sel) {
+		start = 0xfffe0000;
+		env_sel = *(char *)(start+4);
+		if (!env_sel) {
+			printf("can not find U-boot env\n");
+			return NULL;
+		}
+	}
+	*pos = start;
+	buf = malloc(0x10000);
+	memset(buf, 0, 0x10000);
+	memcpy(buf, (char *)start, 0x10000);
+
+	return buf;
+}
+
+int env_read_para1(char *name, struct env_para_def *para)
+{
+	char *buf;
+	unsigned int sf_pos = 0;
+
+	if (name == NULL) {
+		printf("name is NULL\n");
+		return -1;
+	}
+	buf = sf_env_init(&sf_pos);
+	if (!buf) {
+		printf("get spi fial\n");
+		free(buf);
+		return -1;
+	}
+	if (env_find_env(name, buf, para)) {
+		free(buf);
+		return -1;
+	}
+	if (!para->size) {
+		printf("value/string is  NULL\n");
+		free(buf);
+		return -1;
+	}
+	free(buf);
+	return 0;
+}
+
+unsigned int env_get_para_value(char *buf)
+{
+	unsigned int value, pos;
+	unsigned int cnt = 0, tmp;
+
+	value = 0;
+	pos = 0;
+	while (buf[pos] != 0) {
+		value = value | (char2int(buf[pos]) << (cnt * 4));
+		cnt++;
+		pos++;
+		if (cnt > 8) {
+			printf("can not find para end failed\n");
+			break;
+		}
+	}
+	tmp = value;
+	value = 0;
+	cnt--;
+	while (cnt) {
+		value = value | ((tmp & 0x0f) << (cnt * 4));
+		tmp = tmp >> 4;
+		cnt--;
+	}
+	value = value | tmp;
+	return value;
+}
+
+unsigned int env_get_env_value(char *name)
+{
+	struct env_para_def para;
+
+	if (env_read_para1(name, &para))
+		return 0;
+	else
+		return env_get_para_value(para.value);
+}
+
diff --git a/board/wmt/env.h b/board/wmt/env.h
new file mode 100755
index 0000000..d9cd6e7
--- /dev/null
+++ b/board/wmt/env.h
@@ -0,0 +1,41 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef __ENV_H__
+#define __ENV_H__
+
+
+struct env_para_def {
+	char *value;
+	unsigned int npos;
+	unsigned int ppos;
+	unsigned int size;
+};
+
+unsigned int char2int(char c);
+int env_cmp_name(unsigned int pos, char *buf, char *name);
+unsigned int sf_env_crc32(unsigned char *buf);
+int env_find_env(char *name, char *buf, struct env_para_def *para);
+unsigned int env_find_next_pos(unsigned int pos, char *buf);
+unsigned int env_find_para_pos(unsigned int pos, char *buf);
+int env_read_para1(char *name, struct env_para_def *para);
+int env_write_para(char *name, char *para, unsigned int value);
+char *sf_env_init(unsigned int *pos);
+unsigned int env_get_para_value(char *buf);
+unsigned int env_get_env_value(char *name);
+
+#endif
diff --git a/board/wmt/flash.c b/board/wmt/flash.c
new file mode 100755
index 0000000..c027004
--- /dev/null
+++ b/board/wmt/flash.c
@@ -0,0 +1,331 @@
+/*++ 
+Copyright (c) 2013 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Some descriptions of such software. Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "flash/spi_flash.h"
+#include "flash/nor_flash_8bit.h"
+#include "flash/nor_flash_16bit.h"
+/* #include "flash/nor_flash.h" */
+#include "flash/nand_flash.h"
+#include "include/extvars.h"
+
+typedef enum _BOOT_FLASH_TYPE {
+	NOR_FLASH_TYPE = 0,
+	ROM_FLASH_TYPE,
+	NAND_FLASH_TYPE,
+	SPI_FLASH_TYPE,
+	MMC_FLASH_TYPE
+} BOOT_FLASH_TYPE;
+
+typedef enum _BOOT_BIT_TYPE {
+	BOOT_TYPE_8BIT = 0,
+	BOOT_TYPE_16BIT
+} BOOT_BIT_TYPE;
+
+BOOT_FLASH_TYPE flash_type = SPI_FLASH_TYPE;
+BOOT_BIT_TYPE  nor_flash_bit = BOOT_TYPE_16BIT;
+BOOT_BIT_TYPE  nand_flash_bit = BOOT_TYPE_16BIT;
+
+flash_info_t flash_info_nor[CFG_MAX_NOR_FLASH_BANKS];
+flash_info_t flash_info_spi[CFG_MAX_SPI_FLASH_BANKS];
+flash_info_t flash_info_nand[CFG_MAX_NAND_FLASH_BANKS];
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+static unsigned int flash_count;
+/*
+ * get_boot_flash_type()
+ */
+BOOT_FLASH_TYPE get_boot_flash_type(void)
+{
+	unsigned int val = 0;
+	unsigned char rc = SPI_FLASH_TYPE;
+
+	val = *((volatile unsigned int *)(0xd8110100));
+	if ((val&(1<<14)) == 0)
+		rc = MMC_FLASH_TYPE;
+	else if (val&8)
+		rc = ROM_FLASH_TYPE;
+	else
+		rc = SPI_FLASH_TYPE;
+
+	return rc;
+}
+
+/*
+ * get_boot_nand_flash_bit_type()
+ */
+BOOT_BIT_TYPE get_boot_nand_flash_bit_type(void)
+{
+	unsigned int val = 0;
+	unsigned char rc = BOOT_TYPE_8BIT;
+
+	val = *((volatile unsigned int *)(0xd8110100));
+
+	val = (val >> 4) & 0x1;
+
+	switch (val) {
+	case 0:
+		rc = BOOT_TYPE_8BIT;
+		break;
+	case 1:
+		rc = BOOT_TYPE_16BIT;
+		break;
+	default:
+		break;
+	}
+
+	return rc;
+}
+
+static void print_flash_addr(flash_info_t *info)
+{
+	flash_info_t *p = NULL;
+	int i;
+
+	if (!flash_count)
+		return;
+	printf("flash:\n");
+	for (i = 0, p = info; flash_count != 0; p++, i++, flash_count--) {
+		printf("     Bank%d: %08lX -- %08lX", i+1, p->start[0], p->start[0]+p->size-1);
+
+		if (p->flash_id == FLASH_UNKNOWN)
+			printf(" (Missing or Unknown Flash)");
+		printf("\n");
+	}
+}
+
+/*
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init(void)
+{
+	unsigned long rc = 0;
+	int i;
+
+	flash_type = get_boot_flash_type();
+	nand_flash_bit = get_boot_nand_flash_bit_type();
+	flash_count = 0;
+	/* because FLASH_UNKNOWN = 0XFFFffffF, SO WE USE FF INITIAL */
+	memset(flash_info, 0xff, CFG_MAX_FLASH_BANKS * sizeof(flash_info_t));
+	switch (flash_type) {
+	/*case NOR_FLASH_TYPE:
+		printf("boot from nor flash: ");
+		flash_count = CFG_MAX_NOR_FLASH_BANKS;
+		switch (nor_flash_bit) {
+		case BOOT_TYPE_8BIT:
+			printf("8bit mode.\n");
+			rc = nor_flash_8b_init();
+			break;
+		case BOOT_TYPE_16BIT:
+			printf("16bit mode.\n");
+			rc = nor_flash_16b_init();
+			break;
+		}
+		// rc = nor_flash_init();
+		for (i = 0; i < CFG_MAX_NOR_FLASH_BANKS; i++)
+			memcpy(&flash_info[i], &flash_info_nor[i], sizeof(flash_info_t));
+		break;*/
+	case NAND_FLASH_TYPE:
+		printf("boot from nand flash.\n");
+		flash_count = CFG_MAX_NAND_FLASH_BANKS;
+		rc = nand_flash_init();
+		for (i = 0; i < CFG_MAX_NAND_FLASH_BANKS; i++)
+			memcpy(&flash_info[i], &flash_info_nand[i], sizeof(flash_info_t));
+		break;
+	case SPI_FLASH_TYPE:
+		printf("boot from spi flash.\n");
+		flash_count = CFG_MAX_SPI_FLASH_BANKS;
+		rc = spi_flash_init();
+		for (i = 0; i < CFG_MAX_SPI_FLASH_BANKS; i++)
+			memcpy(&flash_info[i], &flash_info_spi[i], sizeof(flash_info_t));
+		break;
+	case ROM_FLASH_TYPE:
+		printf("boot from ROM.\n");
+	default:
+		printf("boot from unknow device====================\n");
+		break;
+	}
+	print_flash_addr(flash_info);
+
+	return rc;
+}
+
+/*
+ */
+void flash_print_info(flash_info_t *info)
+{
+	switch (flash_type) {
+#if 0
+	case NOR_FLASH_TYPE:
+		switch (nor_flash_bit) {
+		case BOOT_TYPE_8BIT:
+			nor_flash_8b_print_info(info);
+			break;
+		case BOOT_TYPE_16BIT:
+			nor_flash_16b_print_info(info);
+			break;
+		}
+
+		/* nor_flash_print_info(info); */
+		break;
+#endif
+	case NAND_FLASH_TYPE:
+		nand_flash_print_info(info);
+		break;
+	case SPI_FLASH_TYPE:
+		spi_flash_print_info(info);
+		break;
+	default:
+		break;
+	}
+}
+
+/*
+ * flash_erase
+ */
+int	flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int rc = 0;
+
+	switch (flash_type) {
+#if 0
+	case NOR_FLASH_TYPE:
+		switch (nor_flash_bit) {
+		case BOOT_TYPE_8BIT:
+			rc = nor_flash_8b_erase(info, s_first, s_last);
+			break;
+		case BOOT_TYPE_16BIT:
+			rc = nor_flash_16b_erase(info, s_first, s_last);
+			break;
+		}
+
+		/* rc = nor_flash_erase(info, s_first, s_last); */
+		break;
+#endif
+	case NAND_FLASH_TYPE:
+		rc = nand_flash_erase(info, s_first, s_last);
+		break;
+	case SPI_FLASH_TYPE:
+    /* sf boot, nand active */
+		rc = spi_flash_erase(info, s_first, s_last);
+		break;
+	default:
+		break;
+	}
+
+	return rc;
+}
+
+/*
+ * Copy flash to memory, returns:
+ * 0 - OK
+ * 1 - write timeout
+ */
+int read_buff(flash_info_t *info, ulong src, ulong addr, ulong cnt)
+{
+	int rc = 0;
+
+	rc = spi_read_buff(info, src, addr, cnt);
+
+	return rc;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	int rc = 0;
+
+	switch (flash_type) {
+#if 0
+	case NOR_FLASH_TYPE:
+		switch (nor_flash_bit) {
+		case BOOT_TYPE_8BIT:
+			rc = nor_flash_8b_write_buff(info, src, addr, cnt);
+			break;
+		case BOOT_TYPE_16BIT:
+			rc = nor_flash_16b_write_buff(info, src, addr, cnt);
+			break;
+		}
+
+		/* rc = nor_write_buff(info, src, addr, cnt); */
+		break;
+#endif
+	case NAND_FLASH_TYPE:
+		rc = nand_write_buff(info, src, addr, cnt);
+		break;
+	case SPI_FLASH_TYPE:
+    /* sf boot, nand active */
+		rc = spi_write_buff(info, src, addr, cnt);
+		break;
+	default:
+		break;
+	}
+
+	return rc;
+}
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int rc = 0;
+
+	switch (flash_type) {
+	case NOR_FLASH_TYPE:
+		/* rc = nor_flash_real_protect(info, info->start[sector], prot); */
+		break;
+	case NAND_FLASH_TYPE:
+		/*rc = nand_flash_real_protect(info, info->start[sector], prot);*/
+		break;
+	case SPI_FLASH_TYPE:
+    /* sf boot, nand active */
+		rc = spi_flash_real_protect(info, sector, prot);
+		break;
+	default:
+		break;
+	}
+
+	return rc;
+} /* end flash_real_protect() */
diff --git a/board/wmt/flash/nand_flash.c b/board/wmt/flash/nand_flash.c
new file mode 100755
index 0000000..8e116b9
--- /dev/null
+++ b/board/wmt/flash/nand_flash.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "nand_flash.h"
+
+extern flash_info_t	flash_info_nand[CFG_MAX_NAND_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t *info);
+#endif
+
+/*-----------------------------------------------------------------------
+ * nand_flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long nand_flash_init(void)
+{
+	unsigned long size_b = 0;
+	return size_b;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void nand_flash_print_info(flash_info_t *info)
+{
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+static void flash_sync_real_protect(flash_info_t *info)
+{
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int	nand_flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int nand_write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	int res = 0;
+	return res;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int nand_flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	return rcode;
+}
+#endif
diff --git a/board/wmt/flash/nand_flash.h b/board/wmt/flash/nand_flash.h
new file mode 100755
index 0000000..ab1f2d5
--- /dev/null
+++ b/board/wmt/flash/nand_flash.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+#ifndef _NAND_FLASH_H_
+#define _NAND_FLASH_H_
+
+#include <common.h>
+
+unsigned long nand_flash_init(void);
+void nand_flash_print_info(flash_info_t *info);
+int nand_flash_erase(flash_info_t *info, int s_first, int s_last);
+int nand_write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+#ifdef CFG_FLASH_PROTECTION
+int nand_flash_real_protect(flash_info_t *info, long sector, int prot);
+#endif
+
+#endif /*_NAND_FLASH_H_*/
diff --git a/board/wmt/flash/nor_flash_16bit.c b/board/wmt/flash/nor_flash_16bit.c
new file mode 100755
index 0000000..25c7604
--- /dev/null
+++ b/board/wmt/flash/nor_flash_16bit.c
@@ -0,0 +1,1225 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+#include <mpc8xx.h>
+#include "nor_flash_16bit.h"
+
+#define CONFIG_EON_FLASH 1
+#define NOR_FLASH_TYPE 2
+#define SPI_FLASH_TYPE 0
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#define CONFIG_FLASH_16BIT 1
+#ifdef CONFIG_FLASH_8BIT
+	typedef unsigned char FLASH_PORT_WIDTH;
+	typedef volatile unsigned char FLASH_PORT_WIDTHV;
+	#define	FLASH_ID_MASK	0xFF
+#else
+#ifdef CONFIG_FLASH_16BIT
+	typedef unsigned short FLASH_PORT_WIDTH;
+	typedef volatile unsigned short FLASH_PORT_WIDTHV;
+	#define SWAP(x)               __swab16(x)
+	#define	FLASH_ID_MASK	0xFFFF
+#else
+	typedef unsigned long FLASH_PORT_WIDTH;
+	typedef volatile unsigned long FLASH_PORT_WIDTHV;
+	#define SWAP(x)               __swab32(x)
+	#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+extern flash_info_t	flash_info_nor[CFG_MAX_NOR_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong nor_flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_eon(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_mx(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t *info);
+#endif
+
+
+
+/*-----------------------------------------------------------------------
+ * nor_flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long nor_flash_16b_init(void)
+{
+	unsigned long size_b, size = 0;
+	int i;
+	unsigned int val = 0;
+	unsigned long flash_base[4];
+	val = *((volatile unsigned int *)(0xd8110100));
+	if (((val>>1)&0x3) == NOR_FLASH_TYPE) {
+		printf("nor boot only nor active\n");
+		flash_base[0] = CFG_NOR_FLASH_BASE_0;
+		flash_base[1] = CFG_NOR_FLASH_BASE_1;
+		flash_base[2] = CFG_NOR_FLASH_BASE_2;
+		flash_base[3] = CFG_NOR_FLASH_BASE_3;
+		#if (NOR_BOOT_ERASE_SIZE_KB == 128)
+		*(volatile unsigned int *)0xd8009460 = CFG_NOR_FLASH_BASE_0 | NOR_FLASH_32M;
+		*(volatile unsigned int *)0xd8009464 = CFG_NOR_FLASH_BASE_1 | NOR_FLASH_32M;
+		*(volatile unsigned int *)0xd8009468 = CFG_NOR_FLASH_BASE_2 | NOR_FLASH_32M;
+		*(volatile unsigned int *)0xd800946c = CFG_NOR_FLASH_BASE_3 | NOR_FLASH_32M;
+		#else
+		*(volatile unsigned int *)0xd8009460 = CFG_NOR_FLASH_BASE_0 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd8009464 = CFG_NOR_FLASH_BASE_1 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd8009468 = CFG_NOR_FLASH_BASE_2 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd800946c = CFG_NOR_FLASH_BASE_3 | NOR_FLASH_8M;
+		#endif
+		/*Configure the NOR Flash clock setting*/
+		*((volatile unsigned int *)(0xd8009408)) &= 0xffffff07;
+		 *((volatile unsigned int *)(0xd8009408)) |= (0x1F<<3);//1F
+	  	*((volatile unsigned int *)(0xd8009418)) &= 0xffffff07;
+	 	*((volatile unsigned int *)(0xd8009418)) |= (0x1F<<3);
+	  	*((volatile unsigned int *)(0xd8009428)) &= 0xffffff07;
+	 	*((volatile unsigned int *)(0xd8009428)) |= (0x1F<<3);
+	  	*((volatile unsigned int *)(0xd8009438)) &= 0xffffff07;
+	 	*((volatile unsigned int *)(0xd8009438)) |= (0x1F<<3);
+	} else if (((val>>1)&0x3) == SPI_FLASH_TYPE) {
+	printf("spi boot, nor NOT active\n");
+		/*flash_base[0] = SPI_BOOT_FLASH_BASE_0;
+		flash_base[1] = SPI_BOOT_FLASH_BASE_1;
+		flash_base[2] = SPI_BOOT_FLASH_BASE_2;
+		flash_base[3] = SPI_BOOT_FLASH_BASE_3;
+		*(volatile unsigned int *)0xd8009460 = SPI_BOOT_FLASH_BASE_0 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd8009464 = SPI_BOOT_FLASH_BASE_1 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd8009468 = SPI_BOOT_FLASH_BASE_2 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd800946c = SPI_BOOT_FLASH_BASE_3 | NOR_FLASH_8M;*/
+	}
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_NOR_FLASH_BANKS; ++i) {
+		flash_info_nor[i].flash_id = FLASH_UNKNOWN;
+
+		size_b = nor_flash_get_size((FPWV *)(flash_base[i]), &flash_info_nor[i]);
+		flash_info_nor[i].size = size_b;
+		size += size_b;
+
+		if (flash_info_nor[i].flash_id == FLASH_UNKNOWN)
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", i, size_b);
+
+		/* Do this again (was done already in flast_get_size), just
+		 * in case we move it when remap the FLASH.
+		 */
+		/* flash_get_offsets (flash_base[i], &flash_info_nor[i]); */
+	}
+#ifdef CFG_FLASH_PROTECTION
+	/* read the hardware protection status (if any) into the
+	 * protection array in flash_info.
+	 */
+	flash_sync_real_protect(&flash_info_nor[0]);
+#endif
+
+#if CFG_MONITOR_BASE >= CFG_NOR_FLASH_BASE_3
+	/* monitor protection ON by default */
+	flash_protect(
+		FLAG_PROTECT_SET,
+		CFG_MONITOR_BASE,
+		CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		&flash_info_nor[3]
+	);
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_EON)
+		*base = (FPW)0x00F000F0;	/* EON Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX)
+		*base = (FPW)0x00F000F0;	/* MX Read Mode */
+  else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_NUM)
+		*base = (FPW)0x00F000F0;
+	else
+		*base = (FPW)0x00F000F0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i)
+			info->start[i] = base + (i * bootsect_size);
+
+		for (i = 8; i < info->sector_count; i++)
+			info->start[i] = base + ((i - 7) * sect_size);
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sect_size);
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_EON
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_EON29LV640U) {
+
+		int sect_size;		/* number of bytes/sector */
+#ifdef CONFIG_FLASH_8BIT
+		sect_size = 0x00008000;
+#else
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+#endif
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++) {
+			/* info->start[i] = base + (i * sect_size); */
+			if (i < 127) {
+				info->start[i] = base + (i * 0x10000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 127 * 0x10000 + ((i-127) * 0x2000);
+				info->protect[i] = 0;
+			}
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_MX29LV640T) {
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++) {
+			if (i < 127) {
+				info->start[i] = base + (i * 0x10000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 127 * 0x10000 + ((i-127) * 0x2000);
+				info->protect[i] = 0;
+			}
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_EON
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_EON29LV640B) {
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++) {
+			if (i < 8) {
+				info->start[i] = base + (i * 0x2000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 8 * 0x2000 + ((i-8) * 0x10000);
+				info->protect[i] = 0;
+			}
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_MX29LV640B) {
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++) {
+			if (i < 8) {
+				info->start[i] = base + (i * 0x2000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 8 * 0x2000 + ((i-8) * 0x10000);
+				info->protect[i] = 0;
+			}
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_MX29GL256E) {
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x20000);
+				info->protect[i] = 0;
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_EON
+	 && (info->flash_id & FLASH_TYPEMASK) == FLASH_EON29LV640H) {
+			int sect_size;		/* number of bytes/sector */
+#ifdef CONFIG_FLASH_8BIT
+		sect_size = 0x00008000;
+#else
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+#endif
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x10000);
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_NUM
+	 && (info->flash_id & FLASH_TYPEMASK) == FLASH_NUM29W640GT) {
+
+		for (i = 0; i < info->sector_count; i++) {
+			if (i < 127) {
+				info->start[i] = base + (i * 0x10000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 127 * 0x10000 + ((i-127) * 0x2000);
+				info->protect[i] = 0;
+			}
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_NUM
+	 && (info->flash_id & FLASH_TYPEMASK) == FLASH_NUM29W640GB) {
+
+		for (i = 0; i < info->sector_count; i++) {
+			if (i < 8) {
+				info->start[i] = base + (i * 0x2000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 8 * 0x2000 + ((i-8) * 0x10000);
+				info->protect[i] = 0;
+			}
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_NUM
+	 && (info->flash_id & FLASH_TYPEMASK) == FLASH_NUM29W640GHL) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x10000);
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_NUM
+	 && (info->flash_id & FLASH_TYPEMASK) == FLASH_NUM29W128GHL) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x20000);
+	} else
+		printf("set flash sector fail\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void nor_flash_16b_print_info(flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_EON:
+		printf("EON ");
+	case FLASH_MAN_MX:
+		printf("MX ");
+		break;
+	case FLASH_MAN_BM:
+		printf("BRIGHT MICRO ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	case FLASH_MAN_NUM:
+		printf("NUM ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	} else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_EON29LV640H:
+#ifdef CONFIG_FLASH_8BIT
+		fmt = "29LV640H (32 Mbit, uniform sectors)\n";
+#else
+		fmt = "29LV640H (64 Mbit, uniform sectors)\n";
+#endif
+		break;
+	case FLASH_EON29LV640U:
+	case FLASH_EON29LV640B:
+#ifdef CONFIG_FLASH_8BIT
+		fmt = "29LV641D (32 Mbit, uniform sectors)\n";
+#else
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+#endif
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_MX29LV640B:
+	case FLASH_MX29LV640T:
+		fmt = "29LV640D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_MX29GL256E:
+		fmt = "29GL256E (256 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_NUM29W640GT:
+	case FLASH_NUM29W640GB:
+	case FLASH_NUM29W640GHL:
+		fmt = "29W640G (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_NUM29W128GHL:
+		fmt = "29W128GL (128 Mbit, uniform sectors)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf(fmt, bootletter, boottype);
+
+	printf("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+
+		printf(" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong nor_flash_get_size(FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+	int DevId, DevId1;
+	/* Write auto select command sequence and test FLASH answer */
+#ifdef	CONFIG_EON_FLASH
+	addr[0x0555] = (FPW)0x00AA00AA;		/* for EON, Intel ignores this */
+	addr[0x02AA] = (FPW)0x00550055;		/* for EON, Intel ignores this */
+#endif
+	addr[0x0555] = (FPW)0x00900090;		/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	DevId = NOR_IDALL((addr[0]&0xFFFF), (addr[1]&0xFFFF));
+	DevId1 = NOR_IDALL((addr[14]&0xFFFF), (addr[15]&0xFFFF));
+	printf("DevId = 0x%x\n", DevId);
+	printf("DevId1 = 0x%x\n", DevId1);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	case (uchar)EON_MANUFACT:
+		info->flash_id = FLASH_MAN_EON;
+		break;
+	case (uchar)MX_MANUFACT:
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (uchar)NUM_MANUFACT:
+		info->flash_id = FLASH_MAN_NUM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN)
+		switch (addr[1]) {
+		/* case (FPW)AMD_ID_LV640U: */ /* 29LV640 and 29LV641 have same ID */
+		/* info->flash_id += FLASH_AM640U; */
+		/* info->sector_count = 128; */
+		/* info->size = 0x00800000 * (sizeof(FPW)/2); */
+		/* break; */ /* => 8 or 16 MB	*/
+
+		case (FPW)EON_ID_LV640U:
+			/* 29LV640 and 29LV641 have same ID */
+			info->flash_id += FLASH_EON29LV640U;
+			info->sector_count = 128;
+#ifdef CONFIG_FLASH_8BIT
+			info->size = 0x00400000;
+#else
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+#endif
+
+			break;
+		case (FPW)EON_ID_LV640B:
+			/* 29LV640 and 29LV641 have same ID */
+			if(info->flash_id == FLASH_MAN_MX)
+				info->flash_id += FLASH_MX29LV640B;
+			else
+				info->flash_id += FLASH_EON29LV640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+			break;			
+		case (FPW)EON_ID_LV640H:
+			if(info->flash_id == FLASH_MAN_NUM) {
+				info->sector_count = 128;
+				info->size = 0x0800000;
+				switch (DevId1) {
+					case NX_M29W640GT:
+						info->flash_id += FLASH_NUM29W640GT;
+						info->sector_count = 135;
+						break;
+					case NX_M29W640GB:
+						info->flash_id += FLASH_NUM29W640GB;
+						info->sector_count = 135;
+						break;
+					case NX_M29W640GH:
+					case NX_M29W640GL:
+						info->flash_id += FLASH_NUM29W640GHL;
+						break;
+					case NX_M29W128GH:
+					case NX_M29W128GL:
+						info->flash_id += FLASH_NUM29W128GHL;
+						info->size = 0x01000000;
+						break;
+					default:
+						info->flash_id += FLASH_NUM29W640GHL;
+						break;
+				}
+			} else if(info->flash_id == FLASH_MAN_EON) {
+				info->flash_id += FLASH_EON29LV640H;
+				info->sector_count = 128;
+				info->size = 0x00800000;
+				//info->size = 0x00800000 * (sizeof(FPW)/2);
+				break;
+			} else if(info->flash_id == FLASH_MAN_MX) {
+				info->flash_id += FLASH_MX29GL256E;
+				info->sector_count = 256;
+				info->size = 0x02000000;
+			}
+			break;
+		case (FPW)EON_ID_LV640T:
+			/* 29LV640 and 29LV641 have same ID */
+			if(info->flash_id == FLASH_MAN_MX)
+				info->flash_id += FLASH_MX29LV640T;
+			else
+				info->flash_id += FLASH_EON29LV640U;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+
+			break;
+
+		case (FPW)INTEL_ID_28F800C3B:
+			info->flash_id += FLASH_28F800C3B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof(FPW)/2);
+			break;				/* => 1 or 2 MB		*/
+
+		case (FPW)INTEL_ID_28F800B3B:
+			info->flash_id += FLASH_INTEL800B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof(FPW)/2);
+			break;				/* => 1 or 2 MB		*/
+
+		case (FPW)INTEL_ID_28F160C3B:
+			info->flash_id += FLASH_28F160C3B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof(FPW)/2);
+			break;				/* => 2 or 4 MB		*/
+
+		case (FPW)INTEL_ID_28F160B3B:
+			info->flash_id += FLASH_INTEL160B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof(FPW)/2);
+			break;				/* => 2 or 4 MB		*/
+
+		case (FPW)INTEL_ID_28F320C3B:
+			info->flash_id += FLASH_28F320C3B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof(FPW)/2);
+			break;				/* => 4 or 8 MB		*/
+
+		case (FPW)INTEL_ID_28F320B3B:
+			info->flash_id += FLASH_INTEL320B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof(FPW)/2);
+			break;				/* => 4 or 8 MB		*/
+
+		case (FPW)INTEL_ID_28F640C3B:
+			info->flash_id += FLASH_28F640C3B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+			break;				/* => 8 or 16 MB	*/
+
+		case (FPW)INTEL_ID_28F640B3B:
+			info->flash_id += FLASH_INTEL640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+			break;				/* => 8 or 16 MB	*/
+
+		/*case (FPW)MX_ID_LV640B:
+			info->flash_id += FLASH_MX29LV640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+			break;
+
+		case (FPW)MX_ID_LV640T:
+			info->flash_id += FLASH_MX29LV640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+			break;*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return 0;			/* => no or unknown flash */
+		}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return info->size;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_sync_real_protect(flash_info_t *info)
+{
+	FPWV *addr = (FPWV *)(info->start[0]);
+	FPWV *sect;
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		/* check for protected sectors */
+		*addr = (FPW)0x00900090;
+		for (i = 0; i < info->sector_count; i++) {
+			/* read sector protection at sector address, (A7 .. A0) = 0x02.
+			* D0 = 1 for each device if protected.
+			* If at least one device is protected the sector is marked
+			* protected, but mixed protected and  unprotected devices
+			* within a sector should never happen.
+			*/
+			sect = (FPWV *)(info->start[i]);
+			info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+		break;
+	case FLASH_EON29LV640H:
+	case FLASH_EON29LV640U:
+	case FLASH_EON29LV640B:
+		for (i = 0; i < info->sector_count; i++) {
+			/* check for protected sectors */
+			sect = (FPWV *)(info->start[i]);
+			sect[0x0555] = (FPW)0x00AA00AA;
+			sect[0x02AA] = (FPW)0x00550055;
+			sect[0x0555] = (FPW)0x00900090;
+
+			info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
+		}
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+		break;
+	case FLASH_MX29LV640T:
+	case FLASH_MX29LV640B:
+	case FLASH_NUM29W640GT:
+	case FLASH_NUM29W640GB:
+	case FLASH_NUM29W640GHL:
+	case FLASH_NUM29W128GHL:
+		for (i = 0; i < info->sector_count; i++) {
+			/* check for protected sectors */
+			sect = (FPWV *)(info->start[i]);
+			sect[0x0555] = (FPW)0x00AA00AA;
+			sect[0x02AA] = (FPW)0x00550055;
+			sect[0x0555] = (FPW)0x00900090;
+
+			info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
+		}
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+		break;
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		break;
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int	nor_flash_16b_erase(flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+	case FLASH_EON29LV640H:
+	case FLASH_EON29LV640U:
+	case FLASH_EON29LV640B:
+	case FLASH_MX29LV640B:
+	case FLASH_MX29LV640T:
+	case FLASH_MX29GL256E:
+	case FLASH_NUM29W640GT:
+	case FLASH_NUM29W640GB:
+	case FLASH_NUM29W640GHL:
+	case FLASH_NUM29W128GHL:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf("\n");
+
+	/* start = get_timer(0); */
+	/* last  = start; */
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+		start = get_timer(0);
+		last  = start;
+
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; 	/* clear status register */
+			*addr = (FPW)0x00200020; 	/* erase setup */
+			*addr = (FPW)0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+			base = (FPWV *)(info->start[0]);
+			base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW)0x00550055;	/* unlock */
+			base[0x0555] = (FPW)0x00800080;	/* erase mode */
+			base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay(1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			now = get_timer(start);
+			if (now > CFG_FLASH_ERASE_TOUT) {
+				printf("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc('.');
+				last = now;
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf(" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int nor_flash_16b_write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		left > 0 && res == 0;
+		addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+		case FLASH_MAN_EON:
+		case FLASH_MAN_NUM:
+			res = write_word_eon(info, (FPWV *)addr, SWAP(data));
+			break;
+		case FLASH_MAN_MX:
+			res = write_word_mx(info, (FPWV *)addr, SWAP(data));
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data)
+		return 2;
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+	base[0x02AA] = (FPW)0x00550055;	/* unlock */
+	base[0x0555] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for EON FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_eon(flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data)
+		return 2;
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+	base[0x02AA] = (FPW)0x00550055;	/* unlock */
+	base[0x0555] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for MX FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_mx(flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data)
+		return 2;
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x0555] = (FPW)0x00AA00AA;	/* unlock */
+	base[0x02AA] = (FPW)0x00550055;	/* unlock */
+	base[0x0555] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return res;
+}
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+	*dest = (FPW)0x00400040;	/* program setup		*/
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00B000B0;	/* Suspend program	*/
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW)0x00100010))
+		res = 1;	/* write failed, time out error is close enough	*/
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+	return res;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int nor_flash_16b_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset(info);		/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset(info);		/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect(info);
+		break;
+
+	case FLASH_EON29LV640H:
+	case FLASH_EON29LV640U:
+	case FLASH_EON29LV640B:
+	case FLASH_MX29LV640B:
+	case FLASH_MX29LV640T:
+	case FLASH_MX29GL256E:
+	case FLASH_NUM29W640GT:
+	case FLASH_NUM29W640GB:
+	case FLASH_NUM29W640GHL:
+	case FLASH_NUM29W128GHL:
+		if (prot == 0)
+			info->protect[sector] = 0;
+		else if (prot == 1)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		break;
+
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
diff --git a/board/wmt/flash/nor_flash_16bit.h b/board/wmt/flash/nor_flash_16bit.h
new file mode 100755
index 0000000..15259ef
--- /dev/null
+++ b/board/wmt/flash/nor_flash_16bit.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#ifndef _NOR_FLASH_16BIT_H_
+#define _NOR_FLASH_16BIT_H_
+
+#include <common.h>
+#include <mpc8xx.h>
+
+unsigned long nor_flash_16b_init(void);
+void nor_flash_16b_print_info(flash_info_t *info);
+int nor_flash_16b_erase(flash_info_t *info, int s_first, int s_last);
+int nor_flash_16b_write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+#ifdef CFG_FLASH_PROTECTION
+int nor_flash_16b_real_protect(flash_info_t *info, long sector, int prot);
+#endif
+
+#endif /*_NOR_FLASH_16BIT_H_*/
diff --git a/board/wmt/flash/nor_flash_8bit.c b/board/wmt/flash/nor_flash_8bit.c
new file mode 100755
index 0000000..b24b2af
--- /dev/null
+++ b/board/wmt/flash/nor_flash_8bit.c
@@ -0,0 +1,1067 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+#include <mpc8xx.h>
+#include "nor_flash_8bit.h"
+
+#define CONFIG_EON_FLASH 1
+#define NOR_FLASH_TYPE 2
+#define SPI_FLASH_TYPE 0
+
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#define CONFIG_FLASH_8BIT 1
+#ifdef CONFIG_FLASH_8BIT
+	typedef unsigned char FLASH_PORT_WIDTH;
+	typedef volatile unsigned char FLASH_PORT_WIDTHV;
+	#define	FLASH_ID_MASK	0xFF
+#else
+#ifdef CONFIG_FLASH_16BIT
+	typedef unsigned short FLASH_PORT_WIDTH;
+	typedef volatile unsigned short FLASH_PORT_WIDTHV;
+	#define SWAP(x)               __swab16(x)
+	#define	FLASH_ID_MASK	0xFFFF
+#else
+	typedef unsigned long FLASH_PORT_WIDTH;
+	typedef volatile unsigned long FLASH_PORT_WIDTHV;
+  #define SWAP(x)               __swab32(x)
+	#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+extern flash_info_t	flash_info_nor[CFG_MAX_NOR_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong nor_flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_eon(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_mx(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t *info);
+#endif
+
+
+
+/*-----------------------------------------------------------------------
+ * nor_flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long nor_flash_8b_init(void)
+{
+	unsigned long size_b, size = 0;
+	int i;
+	unsigned int val = 0;
+	unsigned long flash_base[4];
+	val = *((volatile unsigned int *)(0xd8110100));
+	if (((val>>1)&0x3) == NOR_FLASH_TYPE) {
+		flash_base[0] = CFG_NOR_FLASH_BASE_0;
+		flash_base[1] = CFG_NOR_FLASH_BASE_1;
+		flash_base[2] = CFG_NOR_FLASH_BASE_2;
+		flash_base[3] = CFG_NOR_FLASH_BASE_3;
+		*(volatile unsigned int *)0xd8009460 = CFG_NOR_FLASH_BASE_0 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd8009464 = CFG_NOR_FLASH_BASE_1 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd8009468 = CFG_NOR_FLASH_BASE_2 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd800946c = CFG_NOR_FLASH_BASE_3 | NOR_FLASH_8M;
+	} else if (((val>>1)&0x3) == SPI_FLASH_TYPE) {
+		/*flash_base[0] = SPI_BOOT_FLASH_BASE_0;
+		flash_base[1] = SPI_BOOT_FLASH_BASE_1;
+		flash_base[2] = SPI_BOOT_FLASH_BASE_2;
+		flash_base[3] = SPI_BOOT_FLASH_BASE_3;
+		*(volatile unsigned int *)0xd8009460 = SPI_BOOT_FLASH_BASE_0 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd8009464 = SPI_BOOT_FLASH_BASE_1 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd8009468 = SPI_BOOT_FLASH_BASE_2 | NOR_FLASH_8M;
+		*(volatile unsigned int *)0xd800946c = SPI_BOOT_FLASH_BASE_3 | NOR_FLASH_8M;*/
+	}
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_NOR_FLASH_BANKS; ++i) {
+		flash_info_nor[i].flash_id = FLASH_UNKNOWN;
+
+		size_b = nor_flash_get_size((FPWV *)(flash_base[i]), &flash_info_nor[i]);
+		flash_info_nor[i].size = size_b;
+		size += size_b;
+
+		if (flash_info_nor[i].flash_id == FLASH_UNKNOWN)
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", i, size_b);
+
+		/* Do this again (was done already in flast_get_size), just
+		 * in case we move it when remap the FLASH.
+		 */
+		/*	flash_get_offsets (flash_base[i], &flash_info_nor[i]); */
+	}
+#ifdef CFG_FLASH_PROTECTION
+	/* read the hardware protection status (if any) into the
+	 * protection array in flash_info.
+	 */
+	flash_sync_real_protect(&flash_info_nor[0]);
+#endif
+
+#if CFG_MONITOR_BASE >= CFG_NOR_FLASH_BASE_3
+	/* monitor protection ON by default */
+	flash_protect(
+		FLAG_PROTECT_SET,
+		CFG_MONITOR_BASE,
+		CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		&flash_info_nor[3]
+	);
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+	FPWV *base = (FPWV *)(info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW)0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW)0x00F000F0;	/* AMD Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_EON)
+		*base = (FPW)0x00F000F0;	/* EON Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX)
+		*base = (FPW)0x00F000F0;	/* MX Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector	*/
+		int sect_size;		/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set sector offsets for bottom boot block type	*/
+		for (i = 0; i < 8; ++i)
+			info->start[i] = base + (i * bootsect_size);
+
+		for (i = 8; i < info->sector_count; i++)
+			info->start[i] = base + ((i - 7) * sect_size);
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		&& (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;		/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sect_size);
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_EON
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_EON29LV640B) {
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++) {
+			if (i < 8) {
+				info->start[i] = base + (i * 0x2000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 8 * 0x2000 + ((i-8) * 0x10000);
+				info->protect[i] = 0;
+			}
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX
+		 && (info->flash_id & FLASH_TYPEMASK) == FLASH_MX29LV640B) {
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++) {
+			if (i < 8) {
+				info->start[i] = base + (i * 0x2000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 8 * 0x2000 + ((i-8) * 0x10000);
+				info->protect[i] = 0;
+			}
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_EON
+		&& (info->flash_id & FLASH_TYPEMASK) == FLASH_EON29LV640U) {
+
+		int sect_size;		/* number of bytes/sector */
+#ifdef CONFIG_FLASH_8BIT
+		sect_size = 0x00010000;
+#else
+		sect_size = 0x00008000 * (sizeof(FPW)/2);
+#endif
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++) {
+			if (i < 127) {
+				info->start[i] = base + (i * 0x10000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 127 * 0x10000 + ((i-127) * 0x2000);
+				info->protect[i] = 0;
+			}
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX
+		&& (info->flash_id & FLASH_TYPEMASK) == FLASH_MX29LV640T) {
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++) {
+			if (i < 127) {
+				info->start[i] = base + (i * 0x10000);
+				info->protect[i] = 0;
+			} else {
+				info->start[i] = base + 127 * 0x10000 + ((i-127) * 0x2000);
+				info->protect[i] = 0;
+			}
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+void nor_flash_8b_print_info(flash_info_t *info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	char *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_EON:
+		printf("EON ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MX ");
+		break;
+	case FLASH_MAN_BM:
+		printf("BRIGHT MICRO ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	} else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_EON29LV640U:
+#ifdef CONFIG_FLASH_8BIT
+		fmt = "29LV641D (32 Mbit, uniform sectors)\n";
+#else
+		fmt = "29LV641D (32 Mbit, uniform sectors)\n";
+#endif
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_MX29LV640B:
+	case FLASH_MX29LV640T:
+		fmt = "29LV640D (64 Mbit, uniform sectors)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf(fmt, bootletter, boottype);
+
+	printf("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20,
+		info->sector_count);
+
+	printf("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+
+		printf(" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong nor_flash_get_size(FPWV *addr, flash_info_t *info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+#ifdef	CONFIG_EON_FLASH
+	addr[0x0AAA] = (FPW)0x00AA00AA;		/* for EON, Intel ignores this */
+	addr[0x0555] = (FPW)0x00550055;		/* for EON, Intel ignores this */
+#endif
+	addr[0x0AAA] = (FPW)0x00900090;		/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	printf("flash manufact id = 0x%x\n", addr[0]);
+	printf("flash device   id = 0x%x\n", addr[2]);
+	switch (addr[0] & 0xff) {
+
+	case (uchar)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	case (uchar)EON_MANUFACT:
+		info->flash_id = FLASH_MAN_EON;
+		break;
+	case (uchar)MX_MANUFACT:
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN)
+		switch (addr[2]) {
+		/* case (FPW)AMD_ID_LV640U: */	/* 29LV640 and 29LV641 have same ID */
+		/* info->flash_id += FLASH_AM640U; */
+		/* info->sector_count = 128; */
+		/* info->size = 0x00800000 * (sizeof(FPW)/2); */
+		/* break;	*/ /* => 8 or 16 MB	*/
+
+		case (FPW)EON_ID_LV640U:
+			/* 29LV640 and 29LV641 have same ID */
+			info->flash_id += FLASH_EON29LV640U;
+			info->sector_count = 128;
+#ifdef CONFIG_FLASH_8BIT
+			info->size = 0x00800000;
+#else
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+#endif
+			break;
+		case (FPW)EON_ID_LV640B:
+			/* 29LV640 and 29LV641 have same ID */
+			if(info->flash_id == FLASH_MAN_MX)
+				info->flash_id += FLASH_MX29LV640B;
+			else
+				info->flash_id += FLASH_EON29LV640B;
+			info->sector_count = 135;
+			info->size = 0x00800000;
+			break;
+
+		case (FPW)EON_ID_LV640T:
+			/* 29LV640 and 29LV641 have same ID */
+			if(info->flash_id == FLASH_MAN_MX)
+				info->flash_id += FLASH_MX29LV640T;
+			else
+				info->flash_id += FLASH_EON29LV640U;
+			info->sector_count = 135;
+			info->size = 0x00800000;
+			break;
+
+		case (FPW)INTEL_ID_28F800C3B:
+			info->flash_id += FLASH_28F800C3B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof(FPW)/2);
+			break;				/* => 1 or 2 MB		*/
+
+		case (FPW)INTEL_ID_28F800B3B:
+			info->flash_id += FLASH_INTEL800B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof(FPW)/2);
+			break;				/* => 1 or 2 MB		*/
+
+		case (FPW)INTEL_ID_28F160C3B:
+			info->flash_id += FLASH_28F160C3B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof(FPW)/2);
+			break;				/* => 2 or 4 MB		*/
+
+		case (FPW)INTEL_ID_28F160B3B:
+			info->flash_id += FLASH_INTEL160B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof(FPW)/2);
+			break;				/* => 2 or 4 MB		*/
+
+		case (FPW)INTEL_ID_28F320C3B:
+			info->flash_id += FLASH_28F320C3B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof(FPW)/2);
+			break;				/* => 4 or 8 MB		*/
+
+		case (FPW)INTEL_ID_28F320B3B:
+			info->flash_id += FLASH_INTEL320B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof(FPW)/2);
+			break;				/* => 4 or 8 MB		*/
+
+		case (FPW)INTEL_ID_28F640C3B:
+			info->flash_id += FLASH_28F640C3B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+			break;				/* => 8 or 16 MB	*/
+
+		case (FPW)INTEL_ID_28F640B3B:
+			info->flash_id += FLASH_INTEL640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof(FPW)/2);
+			break;				/* => 8 or 16 MB	*/
+
+		/*case (FPW)MX_ID_LV640B:
+			info->flash_id += FLASH_MX29LV640B;
+			info->sector_count = 135;
+			info->size = 0x00800000;
+			break;
+
+		case (FPW)MX_ID_LV640T:
+			info->flash_id += FLASH_MX29LV640B;
+			info->sector_count = 135;
+			info->size = 0x00800000;
+			break;*/
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return 0;			/* => no or unknown flash */
+	}
+
+	flash_get_offsets((ulong)addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return info->size;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_sync_real_protect(flash_info_t *info)
+{
+	FPWV *addr = (FPWV *)(info->start[0]);
+	FPWV *sect;
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		/* check for protected sectors */
+		*addr = (FPW)0x00900090;
+		for (i = 0; i < info->sector_count; i++) {
+			/* read sector protection at sector address, (A7 .. A0) = 0x02.
+			 * D0 = 1 for each device if protected.
+			 * If at least one device is protected the sector is marked
+			 * protected, but mixed protected and  unprotected devices
+			 * within a sector should never happen.
+			 */
+			sect = (FPWV *)(info->start[i]);
+			info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+		break;
+	case FLASH_EON29LV640U:
+	case FLASH_EON29LV640B:
+		for (i = 0; i < info->sector_count; i++) {
+			/* check for protected sectors */
+			sect = (FPWV *)(info->start[i]);
+			sect[0x0AAA] = (FPW)0x00AA00AA;
+			sect[0x0555] = (FPW)0x00550055;
+			sect[0x0AAA] = (FPW)0x00900090;
+
+			info->protect[i] = (sect[4] & (FPW)(0x00010001)) ? 1 : 0;
+		}
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+		break;
+	case FLASH_MX29LV640T:
+	case FLASH_MX29LV640B:
+		for (i = 0; i < info->sector_count; i++) {
+			/* check for protected sectors */
+			sect = (FPWV *)(info->start[i]);
+			sect[0x0AAA] = (FPW)0x00AA00AA;
+			sect[0x0555] = (FPW)0x00550055;
+			sect[0x0AAA] = (FPW)0x00900090;
+
+			info->protect[i] = (sect[4] & (FPW)(0x00010001)) ? 1 : 0;
+		}
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+		break;
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		break;
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int	nor_flash_8b_erase(flash_info_t *info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+	case FLASH_EON29LV640U:
+	case FLASH_EON29LV640B:
+	case FLASH_MX29LV640B:
+	case FLASH_MX29LV640T:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf("\n");
+
+	/* start = get_timer(0); */
+	/* last  = start; */
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+		start = get_timer(0);
+		last  = start;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *)(info->start[sect]);
+		if (intel) {
+			*addr = (FPW)0x00500050; 	/* clear status register */
+			*addr = (FPW)0x00200020; 	/* erase setup */
+			*addr = (FPW)0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;		/* first address in bank */
+			base = (FPWV *)(info->start[0]);
+			base[0x0AAA] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x0555] = (FPW)0x00550055;	/* unlock */
+			base[0x0AAA] = (FPW)0x00800080;	/* erase mode */
+			base[0x0AAA] = (FPW)0x00AA00AA;	/* unlock */
+			base[0x0555] = (FPW)0x00550055;	/* unlock */
+			*addr = (FPW)0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay(1000);
+
+		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+			now = get_timer(start);
+			if (now > CFG_FLASH_ERASE_TOUT) {
+				printf("Timeout\n");
+
+				if (intel) {
+					/* suspend erase	*/
+					*addr = (FPW)0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;		/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc('.');
+				last = now;
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode	*/
+	}
+
+	printf(" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int nor_flash_8b_write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;	  /* number of bytes to program in current word		*/
+	int left;	  /* number of bytes left to program			*/
+	int i, res;
+
+	for (left = cnt, res = 0;
+		left > 0 && res == 0;
+		addr += sizeof(data), left -= sizeof(data) - bytes) {
+
+		bytes = addr & (sizeof(data) - 1);
+		addr &= ~(sizeof(data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof(data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *)addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *)addr, data);
+		case FLASH_MAN_EON:
+			res = write_word_eon(info, (FPWV *)addr, data);
+			break;
+		case FLASH_MAN_MX:
+			res = write_word_mx(info, (FPWV *)addr, data);
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel(info, (FPWV *)addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data)
+		return 2;
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x0AAA] = (FPW)0x00AA00AA;	/* unlock */
+	base[0x0555] = (FPW)0x00550055;	/* unlock */
+	base[0x0AAA] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for EON FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_eon(flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data)
+		return 2;
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x0AAA] = (FPW)0x00AA00AA;	/* unlock */
+	base[0x0555] = (FPW)0x00550055;	/* unlock */
+	base[0x0AAA] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for MX FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_mx(flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+	FPWV *base;		/* first address in flash bank	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data)
+		return 2;
+
+	base = (FPWV *)(info->start[0]);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x0AAA] = (FPW)0x00AA00AA;	/* unlock */
+	base[0x0555] = (FPW)0x00550055;	/* unlock */
+	base[0x0AAA] = (FPW)0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00F000F0;	/* reset bank */
+			res = 1;
+		}
+	}
+
+	return res;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;	/* result, assume success	*/
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+	*dest = (FPW)0x00400040;	/* program setup		*/
+
+	*dest = data;		/* start programming the data	*/
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW)0x00B000B0;	/* Suspend program	*/
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW)0x00100010))
+		res = 1;	/* write failed, time out error is close enough	*/
+
+	*dest = (FPW)0x00500050;	/* clear status register	*/
+	*dest = (FPW)0x00FF00FF;	/* make sure in read mode	*/
+
+	return res;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int nor_flash_8b_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset(info);		/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset(info);		/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect(info);
+		break;
+
+	case FLASH_EON29LV640U:
+	case FLASH_EON29LV640B:
+	case FLASH_MX29LV640B:
+	case FLASH_MX29LV640T:
+		if (prot == 0)
+			info->protect[sector] = 0;
+		else if (prot == 1)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		break;
+
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
diff --git a/board/wmt/flash/nor_flash_8bit.h b/board/wmt/flash/nor_flash_8bit.h
new file mode 100755
index 0000000..5910bae
--- /dev/null
+++ b/board/wmt/flash/nor_flash_8bit.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#ifndef _NOR_FLASH_8BIT_H_
+#define _NOR_FLASH_8BIT_H_
+
+#include <common.h>
+#include <mpc8xx.h>
+
+unsigned long nor_flash_8b_init(void);
+void nor_flash_8b_print_info(flash_info_t *info);
+int nor_flash_8b_erase(flash_info_t *info, int s_first, int s_last);
+int nor_flash_8b_write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+#ifdef CFG_FLASH_PROTECTION
+int nor_flash_8b_real_protect(flash_info_t *info, long sector, int prot);
+#endif
+
+#endif /*_NOR_FLASH_8BIT_H_*/
diff --git a/board/wmt/flash/spi_flash.c b/board/wmt/flash/spi_flash.c
new file mode 100755
index 0000000..17030d3
--- /dev/null
+++ b/board/wmt/flash/spi_flash.c
@@ -0,0 +1,865 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+/* For UBOOT */
+#include <common.h>
+#include <environment.h>
+#include "../include/wmt_clk.h"
+
+#include "spi_flash.h"
+
+/* ST M25P64 CMD */
+#define SF_CMD_WREN      0x06
+#define SF_CMD_WRDI      0x04
+#define SF_CMD_RDID      0x9F
+#define SF_CMD_RDSR      0x05
+#define SF_CMD_WRSR      0x01
+#define SF_CMD_READ      0x03
+#define SF_CMD_FAST_READ 0x0B
+#define SF_CMD_PP        0x02
+#define SF_CMD_SE        0xD8
+#define SF_CMD_BE        0xC7
+#define SF_CMD_RES       0xAB
+
+#define SF_BIT_WR_PROT_ERR     0x20 /* [5:5] */
+#define SF_BIT_MEM_REGION_ERR  0x10 /* [4:4] */
+#define SF_BIT_PWR_DWN_ACC_ERR 0x8  /* [3:3] */
+#define SF_BIT_PCMD_OP_ERR     0x4  /* [2:2] */
+#define SF_BIT_PCMD_ACC_ERR    0x2  /* [1:1] */
+#define SF_BIT_MASLOCK_ERR     0x1  /* [0:0] */
+
+#define BIT_SEQUENCE_ERROR	0x00300030
+#define BIT_TIMEOUT		0x80000000
+//#define ARRAY_SIZE(a)       (sizeof(a) / sizeof(a[0]))
+
+/* SPI Interface Configuration Register(0x40) */
+#define SF_MANUAL_MODE 0x40
+
+/* SPI Programmable Command Mode Control Register(0x200) */
+#define SF_RUN_CMD   0x01
+
+/*
+ * Chip ID list
+ */
+#define EON_MANUF      0x1C
+#define NUMONYX_MANUF  0x20
+#define MXIC_MANUF     0xC2
+#define SPANSION_MANUF 0x01
+#define SST_MANUF      0xBF
+#define WB_MANUF       0xEF
+#define ATMEL_MANUF    0x1F
+#define GD_MANUF    	 0xC8
+
+/* EON */
+#define EON_25P16_ID   0x2015 /* 2 MB */
+#define EON_25P64_ID   0x2017 /* 8 MB */
+#define EON_25Q64_ID   0x3017 /* 8 MB */
+#define EON_25F40_ID   0x3113 /* 512 KB */
+#define EON_25F16_ID   0x3115 /* 2 MB */
+
+/* NUMONYX */
+#define	NX_25P16_ID	   0x2015 /* 2 MB */
+#define	NX_25P64_ID	   0x2017 /* 8 MB */
+
+/* MXIC */
+#define	MX_L512_ID     0x2010 /* 64 KB , 4KB*/
+#define MX_L4006E_ID   0x2013 /* 512KB */
+#define	MX_L1605D_ID   0x2015 /* 2 MB */
+#define	MX_L3205D_ID   0x2016 /* 4 MB */
+#define	MX_L6405D_ID   0x2017 /* 8 MB */
+#define	MX_L1635D_ID   0x2415 /* 2 MB */
+#define	MX_L3235D_ID   0x5E16 /* 4 MB */
+#define	MX_L12805D_ID  0x2018 /* 16 MB */
+
+/* SPANSION */
+#define SPAN_FL016A_ID 0x0214 /* 2 MB */
+#define SPAN_FL064A_ID 0x0216 /* 8 MB */
+
+/* SST */
+#define SST_VF016B_ID  0x2541 /* 2 MB */
+
+/* WinBond */
+#define WB_X16A_ID     0x3015 /* 2 MB */
+#define WB_X32_ID      0x3016 /* 4 MB */
+#define WB_X64_ID      0x3017 /* 8 MB */
+#define WB_X128_ID     0x4018 /* 16 MB */
+#define WB_X40BV_ID    0x3013 /* 512KB */
+
+/* ATMEL */
+#define AT_25DF041A_ID 0x4401 /* 512KB */
+
+/* GD -Giga Device- */
+#define GD_25Q40_ID			0x4013 /* 512KB */
+#define GD_25Q128_ID		0x4018 /* 16MB */
+
+#define SF_IDALL(x, y)	((x<<16)|y)
+
+struct wm_sf_dev_t {
+	ulong id;
+	ulong size;
+	ulong sector_size;
+};
+
+struct wm_sf_dev_t sf_ids[] = {
+	/* {Device ID, Total Size, Sector Size} */
+	/* EON */
+	{SF_IDALL(EON_MANUF, EON_25P16_ID), 0x200000, 0x10000},
+	{SF_IDALL(EON_MANUF, EON_25P64_ID), 0x800000, 0x10000},
+	{SF_IDALL(EON_MANUF, EON_25F40_ID), 0x80000, 0x10000},
+	{SF_IDALL(EON_MANUF, EON_25F16_ID), 0x200000, 0x10000},
+	{SF_IDALL(EON_MANUF, EON_25Q64_ID), 0x800000, 0x10000},
+	/* NUMONYX */
+	{SF_IDALL(NUMONYX_MANUF, NX_25P16_ID), 0x200000, 0x10000},
+	{SF_IDALL(NUMONYX_MANUF, NX_25P64_ID), 0x800000, 0x10000},
+	/* MXIC */
+	{SF_IDALL(MXIC_MANUF, MX_L512_ID), 0x10000, 0x10000},
+	{SF_IDALL(MXIC_MANUF, MX_L4006E_ID), 0x80000, 0x10000},
+	{SF_IDALL(MXIC_MANUF, MX_L1605D_ID), 0x200000, 0x10000},
+	{SF_IDALL(MXIC_MANUF, MX_L3205D_ID), 0x400000, 0x10000},
+	{SF_IDALL(MXIC_MANUF, MX_L6405D_ID), 0x800000, 0x10000},
+	{SF_IDALL(MXIC_MANUF, MX_L1635D_ID), 0x200000, 0x10000},
+	{SF_IDALL(MXIC_MANUF, MX_L3235D_ID), 0x400000, 0x10000},
+	{SF_IDALL(MXIC_MANUF, MX_L12805D_ID), 0x1000000, 0x10000},
+	/* SPANSION */
+	{SF_IDALL(SPANSION_MANUF, SPAN_FL016A_ID), 0x200000, 0x10000},
+	{SF_IDALL(SPANSION_MANUF, SPAN_FL064A_ID), 0x800000, 0x10000},
+	/* SST */
+	{SF_IDALL(SST_MANUF, SST_VF016B_ID), 0x200000, 0x10000},
+	/*WinBond*/
+	{SF_IDALL(WB_MANUF, WB_X16A_ID), 0x200000, 0x10000},
+	{SF_IDALL(WB_MANUF, WB_X32_ID), 0x400000, 0x10000},
+	{SF_IDALL(WB_MANUF, WB_X64_ID), 0x800000, 0x10000},
+	{SF_IDALL(WB_MANUF, WB_X128_ID), 0x1000000, 0x10000},
+	{SF_IDALL(WB_MANUF, WB_X40BV_ID), 0x80000, 0x10000},
+	/* ATMEL */
+	{SF_IDALL(ATMEL_MANUF, AT_25DF041A_ID), 0x80000, 0x10000},
+	/* GD */
+	{SF_IDALL(GD_MANUF, GD_25Q40_ID), 0x80000, 0x10000},
+	{SF_IDALL(GD_MANUF, GD_25Q128_ID), 0x1000000, 0x10000},
+};
+
+sfreg_t *sfreg ;
+
+static unsigned int phy_flash_addr_0;
+static unsigned int phy_flash_addr_1;
+
+static int spi_flash_sector_erase(unsigned long addr);
+static int flash_error(unsigned long code);
+static int flash_env_init(void);
+static int init_spi_flash(void);
+extern flash_info_t flash_info_spi[CFG_MAX_SPI_FLASH_BANKS] ;/* info for FLASH chips */
+extern int wmt_read_ostc(int *val);
+extern int spi_flash_wmt_protect(flash_info_t *info, long sector, int prot);
+extern int auto_pll_divisor(enum dev_id dev, enum clk_cmd cmd, int unit, int freq);
+
+/*
+#ifdef CFG_FLASH_PROTECTION
+static void flash_syn_real_protect(flash_info_t *info);
+#endif
+*/
+
+/*-----------------------------------------------------------------------
+ * Function
+ */
+/*
+#ifdef CFG_FLASH_PROTECTION
+static void flash_syn_real_protect(flash_info_t *info)
+{
+}
+#endif
+*/
+
+int spi_flash_read_status(int chip, int *value)
+{
+	int temp;
+	if (chip == 0)
+		temp = sfreg->SPI_MEM_0_SR_ACC;
+	else
+		temp = sfreg->SPI_MEM_1_SR_ACC;
+
+	*value = temp;
+	return temp;
+}
+
+int spi_flash_write_status(int chip, int value)
+
+{
+	unsigned long rl_data ;
+	unsigned long temp;
+	int start_time, end_time;
+	int rc ;
+
+	/* SPI flash write enable control register: write enable on chip sel 0 */
+	//tmp1 = get_timer_masked();
+	wmt_read_ostc(&start_time);
+	end_time = start_time + 1;
+	if (chip == 0) {
+		sfreg->SPI_WR_EN_CTR = SF_CS0_WR_EN;
+		sfreg->SPI_MEM_0_SR_ACC = value;
+
+		/* poll status reg of chip 0 for chip erase */
+		do {
+			temp = sfreg->SPI_MEM_0_SR_ACC;
+			temp = sfreg->SPI_MEM_0_SR_ACC;
+
+			/* please SPI flash data sheet */
+			if ((temp & 0x1) == 0x0)
+				break ;
+
+			rc = flash_error(sfreg->SPI_ERROR_STATUS);
+			if (rc != ERR_OK)
+				return rc ;
+
+			wmt_read_ostc(&end_time);
+		} while ((end_time - start_time) < CFG_FLASH_ERASE_TOUT);
+
+		if ((end_time - start_time) >= CFG_FLASH_ERASE_TOUT) {
+			rl_data = BIT_TIMEOUT;
+			rc = flash_error(rl_data);
+			return rc;
+		}
+
+		sfreg->SPI_WR_EN_CTR = SF_CS0_WR_DIS ;
+		return ERR_OK ;
+	} else {
+		sfreg->SPI_WR_EN_CTR = SF_CS1_WR_EN;
+		sfreg->SPI_MEM_1_SR_ACC = value;
+
+
+		/* poll status reg of chip 0 for chip erase */
+		do {
+			temp = sfreg->SPI_MEM_1_SR_ACC ;
+			/* please SPI flash data sheet */
+			if ((temp & 0x1) == 0x0)
+				break ;
+
+			rc = flash_error(sfreg->SPI_ERROR_STATUS);
+			if (rc != ERR_OK)
+				return rc ;
+
+		} while ((end_time - start_time) < CFG_FLASH_ERASE_TOUT);
+
+		if ((end_time - start_time) >= CFG_FLASH_ERASE_TOUT) {
+			rl_data = BIT_TIMEOUT ;
+			rc = flash_error(rl_data) ;
+			return rc;
+		}
+
+		sfreg->SPI_WR_EN_CTR = SF_CS1_WR_DIS ;
+		return ERR_OK ;
+	}
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int spi_flash_real_protect(flash_info_t *info, long sector, int prot)
+
+{
+	int rc = 0;
+	/* printf("SF real protect\n");*/
+	rc = spi_flash_wmt_protect(info, sector, prot);
+	return rc;
+}
+#endif
+
+static int flash_env_init()
+{
+	/* SF reg base address */
+	sfreg = (sfreg_t *)SF_BASE_ADDR ;
+
+	return 0 ;
+}
+
+static int init_spi_flash()
+{
+	unsigned long rl_data;
+	unsigned long phy_flash_size_0 = 0, phy_flash_size_1 = 0;
+	int i, k;
+
+	/* SPI module configuration */
+	/* SPI Read Write Control Register @ bit 0:	SPI Flash Read Speed Field */
+	sfreg->SPI_RD_WR_CTR = 0x1 ; /* read status register & set fast read command */
+
+	for (i = 0; i < CFG_MAX_SPI_FLASH_BANKS; i++) {
+
+		sfreg->SPI_RD_WR_CTR = 0x11 ; /* read ID */
+		if (i == 0)
+			flash_info_spi[i].flash_id = sfreg->SPI_MEM_0_SR_ACC ;
+		else
+			flash_info_spi[i].flash_id = sfreg->SPI_MEM_1_SR_ACC ;
+
+		sfreg->SPI_RD_WR_CTR = 0x1 ; /* read status */
+
+		for (k = 0; k < ARRAY_SIZE(sf_ids); k++) {
+			if (flash_info_spi[i].flash_id == sf_ids[k].id) {
+				printf("SF%1d: ManufID = %X, DeviceID = %X\n",
+					i,
+					flash_info_spi[i].flash_id >> 16,
+					flash_info_spi[i].flash_id & 0xFFFF);
+				flash_info_spi[i].size = sf_ids[k].size;
+				flash_info_spi[i].sector_count = sf_ids[k].size/sf_ids[k].sector_size;
+				break;
+			}
+			if (k == (ARRAY_SIZE(sf_ids) - 1)) {
+				printf("SF%1d: ManufID = %X, DeviceID = %X (Missing or Unknown FLASH)\n",
+					i,
+					flash_info_spi[i].flash_id >> 16,
+					flash_info_spi[i].flash_id & 0xFFFF);
+				printf("     Use Default - Total size = 8MB, Sector size = 64KB\n", i);
+				flash_info_spi[i].size = sf_ids[1].size;
+				flash_info_spi[i].sector_count = sf_ids[1].size/sf_ids[1].sector_size;
+			}
+		}
+
+		if (((flash_info_spi[i].flash_id >> 16) == ATMEL_MANUF) &&
+			(sfreg->SPI_MEM_0_SR_ACC & 0x04)) {
+			printf("     Global Unprotect SF%d !!\n", i);
+			sfreg->SPI_INTF_CFG |= SF_MANUAL_MODE;  /* enter programmable command mode */
+			sfreg->SPI_PROG_CMD_WBF[0] = SF_CMD_WREN; /* Write Enable command */
+			sfreg->SPI_PROG_CMD_CTR = (0x01000000 | (i<<1)); /* set size and chip select */
+			sfreg->SPI_PROG_CMD_CTR |= SF_RUN_CMD;  /* enable programmable command */
+			while (sfreg->SPI_PROG_CMD_CTR & SF_RUN_CMD)
+				;
+			sfreg->SPI_PROG_CMD_WBF[0] = SF_CMD_WRSR; /* Write Status Register command */
+			sfreg->SPI_PROG_CMD_WBF[1] = 0x00; /* Global Unprotect */
+			sfreg->SPI_PROG_CMD_CTR = (0x02000000 | (i<<1)); /* set size and chip select */
+			sfreg->SPI_PROG_CMD_CTR |= SF_RUN_CMD;  /* enable programmable command */
+			while (sfreg->SPI_PROG_CMD_CTR & SF_RUN_CMD)
+				;
+			sfreg->SPI_INTF_CFG &= ~SF_MANUAL_MODE; /* exit programmable command mode */
+		}
+	}
+
+	/* SPI Chip Select 0 Configuration Register */
+	/* bit 31-16:	Starting Address = 16'hff80 @ bit 11-8:	Memory Size = 4'b1000 (8 MB) */
+	phy_flash_addr_0 = (0xFFFFFFFF - flash_info_spi[0].size) + 1;
+	phy_flash_addr_1 = phy_flash_addr_0 - flash_info_spi[1].size;
+	for (i = 0; i < 32; i++) {
+		if ((flash_info_spi[0].size >> i) == 0x8000)
+			phy_flash_size_0 = i;
+		if ((flash_info_spi[1].size >> i) == 0x8000)
+			phy_flash_size_1 = i;
+	}
+
+	sfreg->CHIP_SEL_0_CFG = (phy_flash_addr_0 | (phy_flash_size_0 << 8));
+	rl_data = sfreg->CHIP_SEL_0_CFG ;
+
+	sfreg->CHIP_SEL_1_CFG = (phy_flash_addr_1 | (phy_flash_size_1 << 8));
+	rl_data = sfreg->CHIP_SEL_1_CFG ;
+
+	sfreg->SPI_INTF_CFG = 0x00030000 ;
+	return 0 ;
+}
+
+static int spi_flash_sector_erase(unsigned long addr)
+{
+	unsigned long rl_data ;
+	unsigned long temp;
+	int start_time, end_time;
+	int rc ;
+
+	/* SPI module chip erase */
+	/* SPI flash write enable control register: write enable on chip sel 0 */
+	wmt_read_ostc(&start_time);
+	end_time = start_time + 1;
+	if (addr >= phy_flash_addr_0) {
+		sfreg->SPI_WR_EN_CTR = SF_CS0_WR_EN ;
+
+		/* select sector to erase */
+		addr &= 0xFFFF0000 ;
+		sfreg->SPI_ER_START_ADDR = addr ;
+
+		/* SPI flash erase control register: start chip erase */
+		/* Auto clear when transmit finishes. */
+		sfreg->SPI_ER_CTR = SF_SEC_ER_EN ;
+
+		/* poll status reg of chip 0 for chip erase */
+		do {
+			temp = sfreg->SPI_MEM_0_SR_ACC ;
+			temp = sfreg->SPI_MEM_0_SR_ACC ;
+
+			/* please SPI flash data sheet */
+			if ((temp & 0x1) == 0x0)
+				break ;
+
+			rc = flash_error(sfreg->SPI_ERROR_STATUS);
+			if (rc != ERR_OK)
+				return rc ;
+
+			wmt_read_ostc(&end_time);
+		} while ((end_time - start_time) < CFG_FLASH_ERASE_TOUT);
+
+		if ((end_time - start_time) >= CFG_FLASH_ERASE_TOUT) {
+			rl_data = BIT_TIMEOUT ;
+			rc = flash_error(rl_data) ;
+			return rc;
+		}
+
+		sfreg->SPI_WR_EN_CTR = SF_CS0_WR_DIS ;
+		return ERR_OK ;
+	} else {
+		sfreg->SPI_WR_EN_CTR = SF_CS1_WR_EN ;
+
+		/* select sector to erase */
+		addr &= 0xFFFF0000 ;
+		sfreg->SPI_ER_START_ADDR = addr ;
+
+		/* SPI flash erase control register: start chip erase */
+		/* Auto clear when transmit finishes. */
+		sfreg->SPI_ER_CTR = SF_SEC_ER_EN ;
+
+		/* poll status reg of chip 0 for chip erase */
+		do {
+			temp = sfreg->SPI_MEM_1_SR_ACC ;
+			temp = sfreg->SPI_MEM_1_SR_ACC ;
+
+			/* please SPI flash data sheet */
+			if ((temp & 0x1) == 0x0)
+				break ;
+
+			rc = flash_error(sfreg->SPI_ERROR_STATUS);
+			if (rc != ERR_OK)
+				return rc ;
+
+			wmt_read_ostc(&end_time);
+		} while ((end_time - start_time) < CFG_FLASH_ERASE_TOUT);
+
+		if ((end_time - start_time) >= CFG_FLASH_ERASE_TOUT) {
+			rl_data = BIT_TIMEOUT ;
+			rc = flash_error(rl_data) ;
+			return rc;
+		}
+
+		sfreg->SPI_WR_EN_CTR = SF_CS1_WR_DIS ;
+		return ERR_OK ;
+	}
+}
+
+static int flash_error(unsigned long code)
+{
+	/* check Timeout */
+	if (code & BIT_TIMEOUT) {
+		puts("Serial Flash Timeout\n"); /* For UBOOT */
+	/*	printf("Serial Flash Timeout\n"); // For DLL */
+		sfreg->SPI_ERROR_STATUS = 0x3F ; /* write 1 to clear status */
+		return ERR_TIMOUT;
+	}
+
+	if (code & SF_BIT_WR_PROT_ERR) {
+		puts("Serial Flash Write Protect Error\n") ; /* For UBOOT */
+	/*	printf("Serial Flash Write Protect Error\n") ; // For DLL */
+		sfreg->SPI_ERROR_STATUS = 0x3F ; /* write 1 to clear status */
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & SF_BIT_MEM_REGION_ERR) {
+		puts("Serial Flash Memory Region Error\n") ; /* For UBOOT */
+	/*	printf("Serial Flash Memory Region Error\n") ; // For DLL */
+		sfreg->SPI_ERROR_STATUS = 0x3F ; /* write 1 to clear status */
+		return ERR_PROG_ERROR;
+	}
+
+	if (code & SF_BIT_PWR_DWN_ACC_ERR) {
+		puts("Serial Flash Power Down Access Error\n") ; /* For UBOOT */
+	/*	printf("Serial Flash Power Down Access Error\n") ; // For DLL */
+		sfreg->SPI_ERROR_STATUS = 0x3F ; /* write 1 to clear status */
+		return ERR_PROG_ERROR;
+	}
+
+
+	if (code & SF_BIT_PCMD_OP_ERR) {
+		puts("Serial Flash Program CMD OP Error\n") ; /* For UBOOT */
+	/*	printf("Serial Flash Program CMD OP Error\n") ; // For DLL */
+		sfreg->SPI_ERROR_STATUS = 0x3F ; /* write 1 to clear status */
+		return ERR_PROG_ERROR;
+	}
+
+
+	if (code & SF_BIT_PCMD_ACC_ERR) {
+		puts("Serial Flash Program CMD OP Access Error\n") ; /* For UBOOT */
+	/*	printf("Serial Flash Program CMD OP Access Error\n") ; // For DLL */
+		sfreg->SPI_ERROR_STATUS = 0x3F ; /* write 1 to clear status */
+		return ERR_PROG_ERROR;
+	}
+
+
+	if (code & SF_BIT_MASLOCK_ERR) {
+		puts("Serial Flash Master Lock Error\n") ; /* For UBOOT */
+	/*	printf("Serial Flash Master Lock Error\n") ; // For DLL */
+		sfreg->SPI_ERROR_STATUS = 0x3F ; /* write 1 to clear status */
+		return ERR_PROG_ERROR;
+	}
+
+	/* OK, no error */
+	return ERR_OK;
+}
+
+
+/******************************************************************************
+ *
+ * Public u-boot interface functions below
+ *
+ *****************************************************************************/
+
+/***************************************************************************
+ *
+ * Flash initialization
+ *
+ *****************************************************************************/
+
+unsigned long spi_flash_init(void)
+{
+	int i, j;
+	unsigned long size = 0;
+
+	flash_env_init() ;
+	init_spi_flash() ;
+
+	for (i = 0; i < CFG_MAX_SPI_FLASH_BANKS; i++) {
+		unsigned long flashbase = 0 ;
+
+		/* For UBOOT */
+		 memset(flash_info_spi[i].protect, 0, CFG_MAX_FLASH_SECT);
+		/*
+			for (k = 0 ; k < 128 ; k++) // For DLL, not For UBOOT
+			      flash_info_spi[i].protect[k] = 0 ;
+		*/
+		if (i == 0)
+			flashbase = phy_flash_addr_0;
+		else
+			flashbase = phy_flash_addr_1;
+
+		for (j = 0; j < flash_info_spi[i].sector_count; j++) {
+			if (j >= CFG_MAX_FLASH_SECT) {
+				printf("Error: Sector count of SPI Flash[%d] exceeds %d\n",
+					i,
+					CFG_MAX_FLASH_SECT);
+				break;
+			}
+			flash_info_spi[i].start[j] = flashbase;
+
+			/* uniform sector size */
+			flashbase += (flash_info_spi[i].size/flash_info_spi[i].sector_count);
+		}
+		size += flash_info_spi[i].size;
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+/* For UBOOT
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info_spi[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info_spi[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info_spi[0]);
+#endif
+*/
+	return size;
+}
+
+
+void spi_flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("SST SPI Flash(25P64A-8MB)\n");
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 3) == 0)
+			printf("\n   ");
+
+		printf("[%3d]%08lX%s", i,
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+
+}
+
+int spi_flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+/* For UBOOT */
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	/* debug("flash_erase: s_first %d  s_last %d\n", s_first, s_last); */
+
+	if ((s_first < 0) || (s_first > s_last))
+		return ERR_INVAL;
+
+ /* For UBOOT */
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("\n- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf("\n");
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+#ifdef USE_920T_MMU
+	cflag = dcache_status();
+	dcache_disable();
+#endif
+	iflag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last  && !ctrlc() /*For UBOOT */; sect++) {
+		/* For UBOOT */
+		debug("Erasing sector %2d @ %08lX... ",
+		sect, info->start[sect]);
+
+		/*  printf("Erasing sector %2d @ %08lX... ",  // For DLL */
+		/*			sect, info->start[sect]); */
+
+		/* arm simple, non interrupt dependent timer */
+		/* For UBOOT */
+		reset_timer_masked();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			unsigned long addr ;
+			addr = info->start[sect] ;
+
+
+			rc = spi_flash_sector_erase(addr) ;
+
+			if (rc != ERR_OK)
+				goto outahere;
+
+			printf("ok.\n");
+		} else {
+			/* it was protected */
+			printf("protected!\n");
+		}
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	/* For UBOOT */
+	udelay_masked(10000);
+
+	if (iflag)
+		enable_interrupts();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable();
+#endif
+
+	return rc;
+}
+
+int spi_write_buff(
+	flash_info_t *info,
+	unsigned char *src /*For UBOOT*/,
+	unsigned long addr,
+	unsigned long cnt
+	)
+{
+	unsigned long wp;
+	int iflag;
+	int rc;
+	unsigned char *data;
+
+#ifdef USE_920T_MMU
+	cflag = dcache_status();
+	dcache_disable();
+#endif
+	iflag = disable_interrupts();
+
+	sfreg->SPI_WR_EN_CTR = 0x3 ;
+
+	rc = ERR_OK;
+	wp = addr;
+
+	data = (unsigned char *)addr;
+	while (cnt) {
+		*data = *src;
+		cnt--;
+		src++;
+		data++;
+	}
+
+	sfreg->SPI_WR_EN_CTR = 0x0 ;
+
+/* For UBOOT */
+	if (iflag)
+		enable_interrupts();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable();
+#endif
+
+	return rc ;
+}
+
+static int Manu_ReadData(unsigned int chip, unsigned int byte, unsigned int sector)/*case 5*/
+{
+	sfreg->SPI_PROG_CMD_WBF[0] = 0x03;
+	sfreg->SPI_PROG_CMD_WBF[1] = (sector & 0xFF0000) >> 16;
+	sfreg->SPI_PROG_CMD_WBF[2] = (sector & 0xFF00)>> 8;
+	sfreg->SPI_PROG_CMD_WBF[3] = sector & 0xFF;
+
+	/* set size and enable programmable command */
+	sfreg->SPI_PROG_CMD_CTR = (0x04000001 | chip<<1 | byte<<16);
+
+	return 0;
+}
+
+#if 0
+static int Manu_FastRead(unsigned int chip, unsigned int byte, unsigned int sector)/*case 6*/
+{
+	sfreg->SPI_PROG_CMD_WBF[0] = 0x0B;
+	sfreg->SPI_PROG_CMD_WBF[1] = (sector & 0xFF0000) >> 16;
+	sfreg->SPI_PROG_CMD_WBF[2] = (sector & 0xFF00) >> 8;
+	sfreg->SPI_PROG_CMD_WBF[3] = sector & 0xFF;
+	sfreg->SPI_PROG_CMD_WBF[4] = 0x00;
+
+	/* set size and enable programmable command */
+	sfreg->SPI_PROG_CMD_CTR = (0x05000001 | chip<<1 | byte<<16);
+	return 0;
+}
+#endif
+
+int spi_read_buff(
+	flash_info_t *info,
+	unsigned long src /*sf ofs*/,
+	unsigned long addr,	/*mem_ofs*/
+	unsigned long cnt,
+	unsigned int fast
+	)
+{
+	unsigned long size;
+	int iflag;
+	int rc, t1, t2;
+	unsigned char *wp;
+	unsigned int chip = 0, sector = 0, byte = 64, chip0_base, sf_ofs;
+	int timeout = 0, dma = 64;
+	//int t3, t4;
+	//int fb_param = 0;
+	//char *s, *endp;
+
+	rc = ERR_OK;
+	wp = (unsigned char *)addr;
+	size = cnt;
+	sf_ofs = src;
+	chip0_base = (0xffffffff - info->size) + 1;
+
+
+	auto_pll_divisor(DEV_SF, CLK_ENABLE, 0, 0);
+
+	iflag = disable_interrupts();
+
+	sfreg->SPI_RD_WR_CTR = 0; /* READ instead of FAST_READ */
+	sfreg->SPI_INTF_CFG = 0x00000040; /* enter programmable command mode */
+
+	//printf("1 sf Read chip =%d data size = 0x%x bytes chip0_base=0x%x\n", chip, byte, chip0_base);
+
+	//wmt_read_ostc(&t3);
+
+	while(size) {
+		byte = ((size > dma) ? dma : size);
+		if (sf_ofs >= chip0_base && (sf_ofs + byte) < 0xffffffff) {
+			chip = 0;
+			sector = sf_ofs - chip0_base;
+		}
+		Manu_ReadData(chip, byte, sector);
+
+		size -= byte;
+		sf_ofs += byte;
+		wmt_read_ostc(&t1);
+		timeout = 0;
+		while (1) {
+			if ((sfreg->SPI_PROG_CMD_CTR & 0x1) == 0) {
+				/*printf("Sector Num: PROG_CMD_WBF[1] = 0x%X\n", sfreg->SPI_PROG_CMD_WBF[1]);
+				for (i = 0; i < byte; i += 4) {
+					printf("SPI_PROG_CMD_RBF[%x] = 0x%8.8x \r\n", i,	*((volatile unsigned int *)&sfreg->SPI_PROG_CMD_RBF[i]));
+				}*/
+				break;
+			}
+			wmt_read_ostc(&t2);
+			if ((t2 - t1) > 3000000) {
+				timeout = 1;
+				break;
+			}
+		}
+		if (timeout) {
+			printf("Read chip =%d data size = 0x%x bytes fail! \n", chip, byte);
+		}/* else
+			printf("Read chip =%d data size = 0x%x bytes success \n", chip, byte);*/
+
+		memcpy(wp, sfreg->SPI_PROG_CMD_RBF, byte);
+		//wmt_read_ostc(&t5);
+
+		wp += byte;
+		if (sf_ofs > 0xFFFFFFFF || size == 0)
+			break;
+	}
+
+	//wmt_read_ostc(&t4);
+	//printf("t4-t3=%d t21=%d t51=%d\n", t4-t3, t2-t1, t5-t1);
+
+/* For UBOOT */
+	if (iflag)
+		enable_interrupts();
+
+
+	sfreg->SPI_PROG_CMD_CTR = 0; /* reset programmable command register*/
+	sfreg->SPI_INTF_CFG &= ~SF_MANUAL_MODE; /* exit programmable command mode */
+	sfreg->SPI_RD_WR_CTR = 0x01; /* read status register & set fast read command*/
+
+	/*wmt_read_ostc(&t1);
+	t2 = t1;
+	while(((t2 - t1)/1000) < 100) {
+		wmt_read_ostc(&t2);
+	}*/
+
+	return rc ;
+}
diff --git a/board/wmt/flash/spi_flash.h b/board/wmt/flash/spi_flash.h
new file mode 100755
index 0000000..e2b873e
--- /dev/null
+++ b/board/wmt/flash/spi_flash.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2006
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#ifndef __SPI_FLASH_H_
+#define __SPI_FLASH_H_
+
+#include <asm/arch/common_def.h>	/* WMT common definitions and macros */
+/* GPIO reg */
+#define GPIO_BASE_ADDR 0xD8110000
+#define GPIO_ENABLE_SF_REG  REG32_PTR(GPIO_BASE_ADDR+0x0)
+#define GPIO_STRAPPING_REG  REG32_PTR(GPIO_BASE_ADDR+0x0100)
+
+/* PMC module reg */
+#define PMC_BASE_ADDR 0XD8130000
+#define PMC_SF_CLK_REG  REG32_PTR(PMC_BASE_ADDR + 0x314)
+#define PMC_PLLB_MULTIPLIER_REG  REG32_PTR(PMC_BASE_ADDR + 0x204)
+#define PMC_PLLA_MULTIPLIER_REG  REG32_PTR(PMC_BASE_ADDR + 0x200)
+#define PMC_PLLC_MULTIPLIER_REG  REG32_PTR(PMC_BASE_ADDR + 0x208)
+#define PMC_PLLD_MULTIPLIER_REG  REG32_PTR(PMC_BASE_ADDR + 0x20C)
+
+#define SF_BASE_ADDR 0xD8002000
+
+typedef struct sfreg_s {
+	unsigned long volatile     CHIP_SEL_0_CFG ;    /* 0xD8002000 */
+	unsigned long volatile     Res1 ;              /* 0x04 */
+	unsigned long volatile     CHIP_SEL_1_CFG ;    /* 0xD8002008 */
+	unsigned long volatile     Res2[13] ;          /* 0x0C */
+	unsigned long volatile     SPI_INTF_CFG ;      /* 0xD8002040 */
+	unsigned long volatile     Res3[3] ;           /* 0x44 */
+	unsigned long volatile     SPI_RD_WR_CTR ;     /* 0xD8002050 */
+	unsigned long volatile     Res4[3] ;           /* 0x54 */
+	unsigned long volatile     SPI_WR_EN_CTR ;     /* 0xD8002060 */
+	unsigned long volatile     Res5[3] ;           /* 0x64 */
+	unsigned long volatile     SPI_ER_CTR ;        /* 0xD8002070 */
+	unsigned long volatile     SPI_ER_START_ADDR ; /* 0xD8002074 */
+	unsigned long volatile     Res6[2] ;           /* 0x78 */
+	unsigned long volatile     SPI_ERROR_STATUS ;  /* 0xD8002080 */
+	unsigned long volatile     Res7[31] ;          /* 0x84 */
+	unsigned long volatile     SPI_MEM_0_SR_ACC ;  /* 0xD8002100 */
+	unsigned long volatile     Res8[3] ;           /* 0x104 */
+	unsigned long volatile     SPI_MEM_1_SR_ACC ;  /* 0xD8002110 */
+	unsigned long volatile     Res9[27] ;          /* 0x114 */
+	unsigned long volatile     SPI_PDWN_CTR_0 ;    /* 0xD8002180 */
+	unsigned long volatile     Res10[3] ;          /* 0x184 */
+	unsigned long volatile     SPI_PDWN_CTR_1 ;    /* 0xD8002190 */
+	unsigned long volatile     Res11[27] ;         /* 0x194 */
+	unsigned long volatile     SPI_PROG_CMD_CTR ;  /* 0xD8002200 */
+	unsigned long volatile     Res12[3] ;          /* 0x204 */
+	unsigned long volatile     SPI_USER_CMD_VAL ;  /* 0xD8002210 */
+	unsigned long volatile     Res13[59] ;         /* 0x214 */
+	unsigned char volatile     SPI_PROG_CMD_WBF[64] ;  /* 0xD8002300 */
+	unsigned long volatile     Res14[16] ;         /* 0x340 */
+	unsigned char volatile     SPI_PROG_CMD_RBF[64] ;  /* 0xD8002380 */
+} sfreg_t ;
+
+/* Chip select 0-1 configuration register, 0x0 & 0x8 */
+#define SF_START_ADDR          0xFF800000 /* [36:16] */
+#define SF_MEM_SIZE_8M         0x00000800 /* [11:8] */
+
+/* SPI interface configuration register, 0x40 */
+#define SF_PDWN_DELY           0x0  /* [31:28] */
+#define SF_RES_DELY            0x0  /* [27:24] */
+#define SF_CS_DELY             0x0  /* [18:16] */
+#define SF_PROG_CMD_MOD_EN     0x40 /* [6:6] */
+#define SF_PROG_CMD_MOD_DIS    0x0  /* [6:6] */
+#define SF_USR_WR_CMD_MOD_EN   0x20 /* [5:5] */
+#define SF_USR_WR_CMD_MOD_DIS  0x0  /* [5:5] */
+#define SF_USR_RD_CMD_MOD_EN   0x10 /* [4:4] */
+#define SF_USR_RD_CMD_MOD_DIS  0x0  /* [4:4] */
+#define SF_ADDR_WIDTH_24       0x0  /* [0:0] */
+#define SF_ADDR_WIDTH_32       0x1  /* [0:0] */
+/* SPI flash read/write control register, 0x50 */
+#define SF_ID_RD               0x10 /* [4:4] */
+#define SF_STATUS_RD           0x0  /* [4:4] */
+#define SF_RD_SPD_FAST         0x1  /* [0:0] */
+#define SF_RD_SPD_NOR          0x0  /* [0:0] */
+
+/* SPI flash write enable control register, 0x60 */
+#define SF_CS1_WR_EN           0x2 /* [1:1] */
+#define SF_CS1_WR_DIS          0x0 /* [1:1] */
+#define SF_CS0_WR_EN           0x1 /* [0:0] */
+#define SF_CS0_WR_DIS          0x0 /* [0:0] */
+
+/* SPI flash erase control register, 0x70 */
+#define SF_SEC_ER_EN           0x8000 /* [15:15] */
+#define SF_SEC_ER_DIS          0x0 /* [15:15] */
+#define SF_CHIP_ER_EN          0x1 /* [0:0] */
+#define SF_CHIP_ER_DIS         0x0 /* [0:0] */
+
+/* SPI flash erase start address register, 0x74 */
+#define SF_ER_START_ADDR       0x0 /* [31:16] */
+#define CHIP_ER_CS1            0x2 /* [1:1] */
+#define CHIP_ER_CS0            0x1 /* [0:0] */
+
+/* SPI flash error status register, 0x80 */
+#define SF_WR_PROT_ERR         0x20 /* [5:5] */
+#define SF_MEM_REGION_ERR      0x10 /* [4:4] */
+#define SF_PWR_DWN_ACC_ERR     0x8  /* [3:3] */
+#define SF_PCMD_OP_ERR         0x4  /* [2:2] */
+#define SF_PCMD_ACC_ERR        0x2  /* [1:1] */
+#define SF_MASLOCK_ERR         0x1  /* [0:0] */
+/* SPI power down control register, 0x180 & 0x190 */
+#define PWR_DWN_EN             0x1 /* [0:0] */
+#define PWR_DWN_DIS            0x0 /* [0:0] */
+/* SPI programmable command mode control register, 0x200 */
+#define SF_TX_DATA_SIZE        0x0 /* MACRO [30:24] */
+#define SF_RX_DATA_SIZE        0x0 /* MACRO [22:16] */
+#define SF_CMD_CS1             0x2 /* MACRO [1:1] */
+#define SF_CMD_CS0             0x0 /* MACRO [1:1] */
+#define SF_CMD_EN              0x1 /* [0:0] */
+#define SF_CMD_DIS             0x0 /* [0:0] */
+/* SPI user command value register, 0x210 */
+#define SF_USR_WR_CMD          0x0 /* MACRO [23:16] */
+#define SF_USR_RD_CMD          0x0 /* MACRO [7:0] */
+
+unsigned long spi_flash_init(void);
+int spi_flash_erase(flash_info_t *info, int s_first, int s_last);
+int spi_write_buff(flash_info_t *info, unsigned char *src, unsigned long addr, unsigned long cnt);
+void spi_flash_print_info(flash_info_t *info);
+#ifdef CFG_FLASH_PROTECTION
+int spi_flash_real_protect(flash_info_t *info, long sector, int prot);
+int spi_flash_write_status(int chip, int value);
+int spi_flash_read_status(int chip, int *value);
+#endif
+
+#endif	/* __SPI_FLASH_H_ */
diff --git a/board/wmt/flash/spi_flash_lock.c b/board/wmt/flash/spi_flash_lock.c
new file mode 100755
index 0000000..b82611d
--- /dev/null
+++ b/board/wmt/flash/spi_flash_lock.c
@@ -0,0 +1,82 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2010 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+/* For UBOOT */
+#include <common.h>
+#include "spi_flash.h"
+
+
+int spi_flash_wmt_protect(flash_info_t *info, long sector, int prot)
+{
+	int rc = 0, value;
+	char *key = NULL;
+
+	/*key = getenv("wmt.rsa.pem");
+	if (!key) {
+		return 1;
+	}*/
+	printf("real ");
+	if (prot) {
+		/* lock sf */
+		if (sector == 0) {
+			spi_flash_read_status(0, &value);
+			if ((value&0x9C) != 0x9C)
+				rc = spi_flash_write_status(0, 0x9C);
+			else
+				printf("chip 0 already lock\n");
+		} else {
+			spi_flash_read_status(1, &value);
+			if ((value&0x9C) != 0x9C)
+				rc = spi_flash_write_status(1, 0x9C);
+			else
+				printf("chip 1 already lock\n");
+		}
+		*(volatile unsigned char *)(GPIO_BASE_ADDR + 0xDF) &= ~0x4; /*gpio31 gpio out data*/
+		*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9F) |= 0x4; /*gpio31 enable out enable*/
+		*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5F) |= 0x4; /*gpio31 enable gpio mode*/
+		/* printf("SF protect sec %d\n", sector); */
+	} else {
+		/* unlock sf */
+		*(volatile unsigned char *)(GPIO_BASE_ADDR + 0xDF) |= 0x4; /*gpio31 gpio out data*/
+		*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x9F) |= 0x4; /*gpio31 enable out enable*/
+		*(volatile unsigned char *)(GPIO_BASE_ADDR + 0x5F) |= 0x4; /*gpio31 enable gpio mode*/
+		if (sector == 0) {
+			spi_flash_read_status(0, &value);
+			if ((value&0x9C) != 0)
+				rc = spi_flash_write_status(0, 0);
+			else
+				printf("chip 0 already unlock\n");
+		} else {
+			spi_flash_read_status(1, &value);
+			if ((value&0x9C) != 0)
+				rc = spi_flash_write_status(1, 0);
+			else
+				printf("chip 1 already unlock\n");
+		}
+		if (rc) {
+			*(volatile unsigned char *)(GPIO_BASE_ADDR + 0xDF) &= ~0x4; /*gpio31 gpio pull-high*/
+			/* printf("SF unprotect fail\n", sector);*/
+		}
+	}
+	return rc;
+}
+
+
+
diff --git a/board/wmt/include/chiptop.h b/board/wmt/include/chiptop.h
new file mode 100755
index 0000000..63be132
--- /dev/null
+++ b/board/wmt/include/chiptop.h
@@ -0,0 +1,83 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef _CHIPTOP_H_
+#define _CHIPTOP_H_
+
+#define IN
+#define OUT
+#define IO
+
+#define true    1
+#define false   0
+/*
+#define NULL    0
+
+typedef unsigned char  uchar;
+typedef unsigned int   uint;
+typedef unsigned short ushort;
+typedef unsigned long  ulong;
+typedef unsigned long	 u32;
+*/
+//typedef unsigned short u16;
+//typedef unsigned char  u8;
+typedef unsigned int   err_no_t ;
+
+/*
+ * Internal APB Slaves Memory Address Map
+ */
+#define BA_MC3           0xD8000000	/* DDR/DDR2 Memory Controller Configuration */
+#define BA_MSC           0xD800B000	/* MemoryStick Controller Base Address */
+#define	BA_MSCDMA        0xD800B100	/* MemoryStick Controller DMA Base Address */
+#define BA_DMA           0xD8001000 /* system dma Base Address */
+#define BA_RTC           0xD8100000	/* RTC Base Address */
+#define BA_GPIO          0xD8110000	/* GPIO Base Address */
+#define BA_SCC           0xD8120000	/* System Configuration Control Base Address */
+#define BA_PMC           0xD8130000	/* Power Management Control Base Address */
+#define BA_IC            0xD8140000	/* Interrupt Controller Base Address */
+#define BA_UART0         0xD8200000	/* UART0 Base Address */
+#define BA_UART1         0xD8210000	/* UART1 Base Address */
+#define BA_SPI           0xD8240000	/* SPI Base Address */
+#define SPI_REG_BASE     0xD8240000     /* SPI Base Address */
+#define SPI_REG_BASE1    0xD8250000     /* SPI1 Base Address */
+#define BA_I2C           0xD8290000	/* I2C Base Address */
+#define BA_PATAHC        0xD8008000 /* PATA HC Base Address */
+#define BA_PATAREG       0xD8008270 /* PATA Data /Conmmand Base Address */
+#define BA_PATASG        0xD8008500 /* PATA SG Base Address */
+#define BA_PATAHC_PCI    0xD8008100 /* PATA PCI Base Address */
+#define BA_PATACSREG     0xD8008376 /* PATA Control/Status Base Address */
+/* USB Host Controller (UHCI & EHCI) */
+/* #define BA_USB           0xD8007000 // USB CPAI Register Base Address */
+#define BA_EHCI_PCI      0xD8007800 /* USB 2.0 EHCI USB Host Configuration Base Address */
+#define BA_EHCI_REG      0xD8007900 /* USB 2.0 EHCI USB Host Register Base Address */
+#define BA_UHCI_PCI      0xD8007A00 /* USB 1.1 UHCI USB Host Configuration Base Address */
+#define BA_UHCI_REG      0xD8007B00 /* USB 1.1 UHCI USB Host Register Base Address */
+#define BA_CFC           0xD800C000 /* CFC Base Address */
+#define BA_DMACFC        0xD800C100 /* CFC Dma Base Address */
+
+#define BA_PCISATAREG    0xC0000AF0
+#define BA_PCISATAREG2   0xC0000A70
+#define BA_PCIPATAREG    0xC00001F0
+#define BA_PCISATACSREG  0xC0000AFA
+#define BA_PCISATACSREG2 0xC0000A7A
+#define BA_PCIPATACSREG  0xC00001FA
+#define BA_PCISATASG     0xC000CC00
+#define BA_PCIPATASG     0xC000CC10
+
+/* Public functions */
+
+#endif	/* _CHIPTOP_H_ */
diff --git a/board/wmt/include/common_def.h b/board/wmt/include/common_def.h
new file mode 100755
index 0000000..02c876d
--- /dev/null
+++ b/board/wmt/include/common_def.h
@@ -0,0 +1,169 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef _COMMON_DEF_H
+#define _COMMON_DEF_H
+
+/*
+ *    Common Constant define
+ */
+
+/*
+ *      PTR and VAL
+ */
+
+#define REG32_VAL(addr) (*(volatile unsigned int *)(addr))
+#define REG16_VAL(addr) (*(volatile unsigned short *)(addr))
+#define REG8_VAL(addr)  (*(volatile unsigned char *)(addr))
+
+#define REG32_PTR(addr) ((volatile unsigned int *)(addr))
+#define REG16_PTR(addr) ((volatile unsigned short *)(addr))
+#define REG8_PTR(addr)  ((volatile unsigned char *)(addr))
+
+/*
+ *      PTR and VAL for Memory
+ */
+#define MEM32_VAL(addr) (*(volatile unsigned int *)(addr))
+#define MEM16_VAL(addr) (*(volatile unsigned short *)(addr))
+#define MEM8_VAL(addr)  (*(volatile unsigned char *)(addr))
+
+#define MEM32_PTR(addr) ((volatile unsigned int *)(addr))
+#define MEM16_PTR(addr) ((volatile unsigned short *)(addr))
+#define MEM8_PTR(addr)  ((volatile unsigned char *)(addr))
+
+
+#define U32 unsigned int
+#define U16 unsigned short
+#define S32 int
+#define S16 short int
+#define U8  unsigned char
+#define S8  char
+#define u32 unsigned int
+#define u16 unsigned short
+#define u8  unsigned char
+#define bool char
+
+/*
+ * ------------------------------------------
+ */
+#define BIT0                0x00000001
+#define BIT1                0x00000002
+#define BIT2                0x00000004
+#define BIT3                0x00000008
+#define BIT4                0x00000010
+#define BIT5                0x00000020
+#define BIT6                0x00000040
+#define BIT7                0x00000080
+#define BIT8                0x00000100
+#define BIT9                0x00000200
+#define BIT10               0x00000400
+#define BIT11               0x00000800
+#define BIT12               0x00001000
+#define BIT13               0x00002000
+#define BIT14               0x00004000
+#define BIT15               0x00008000
+#define BIT16               0x00010000
+#define BIT17               0x00020000
+#define BIT18               0x00040000
+#define BIT19               0x00080000
+#define BIT20               0x00100000
+#define BIT21               0x00200000
+#define BIT22               0x00400000
+#define BIT23               0x00800000
+#define BIT24               0x01000000
+#define BIT25               0x02000000
+#define BIT26               0x04000000
+#define BIT27               0x08000000
+#define BIT28               0x10000000
+#define BIT29               0x20000000
+#define BIT30               0x40000000
+#define BIT31               0x80000000
+
+/*
+ * -----------------------------------------
+ */
+#define SIZE_1B             0x00000001
+#define SIZE_2B             0x00000002
+#define SIZE_4B             0x00000004
+#define SIZE_8B             0x00000008
+#define SIZE_16B            0x00000010
+#define SIZE_32B            0x00000020
+#define SIZE_64B            0x00000040
+#define SIZE_128B           0x00000080
+#define SIZE_256B           0x00000100
+#define SIZE_512B           0x00000200
+#define SIZE_1KB            0x00000400
+#define SIZE_2KB            0x00000800
+#define SIZE_4KB            0x00001000
+#define SIZE_8KB            0x00002000
+#define SIZE_16KB           0x00004000
+#define SIZE_32KB           0x00008000
+#define SIZE_64KB           0x00010000
+#define SIZE_128KB          0x00020000
+#define SIZE_256KB          0x00040000
+#define SIZE_512KB          0x00080000
+#define SIZE_1MB            0x00100000
+#define SIZE_2MB            0x00200000
+#define SIZE_4MB            0x00400000
+#define SIZE_8MB            0x00800000
+#define SIZE_16MB           0x01000000
+#define SIZE_32MB           0x02000000
+#define SIZE_64MB           0x04000000
+#define SIZE_128MB          0x08000000
+#define SIZE_256MB          0x10000000
+#define SIZE_512MB          0x20000000
+#define SIZE_1GB            0x40000000
+#define SIZE_2GB            0x80000000
+
+/*
+ * Get any byte from a word
+ */
+#define GET_LE_BYTE0(x)          ((unsigned char)((x) & 0xFF))
+#define GET_LE_BYTE1(x)          ((unsigned char)((x) >> 8 & 0xFF))
+#define GET_LE_BYTE2(x)          ((unsigned char)((x) >> 16 & 0xFF))
+#define GET_LE_BYTE3(x)          ((unsigned char)((x) >> 24 & 0xFF))
+
+/*
+ *  !!! Special Note !!! for packed
+ *
+ *  use packed that will treat all member as "char" type.
+ *  Please use "packed" very carefully.
+ *
+ *  We should take care to use "packed"
+ *  Make sure that each item in the structure will have the same align.
+ *  ======================================================================
+ */
+#ifdef __GNUC__
+    #define MAKE_PACKED(X) X __attribute__((packed))
+
+#else
+   #define MAKE_PACKED(X) __packed X
+   #define __FUNCTION__ __func__
+
+#endif
+/*
+Example for packed structure:
+------------------------------
+typedef MAKE_PACKED( struct Test1_s
+{
+    unsigned short s1 ;
+    unsigned short s2 ;
+    unsigned int   i1 ;
+    unsigned int   i2 ;
+} ) Test1_t  ;
+*/
+#endif /* _COMMON_DEF_H */
diff --git a/board/wmt/include/extvars.h b/board/wmt/include/extvars.h
new file mode 100755
index 0000000..1be3487
--- /dev/null
+++ b/board/wmt/include/extvars.h
@@ -0,0 +1,23 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef _EXTVARS_H_
+#define _EXTVARS_H_
+
+
+extern unsigned long chip_id;
+#endif	/* _EXTVARS_H_ */
diff --git a/board/wmt/include/global.h b/board/wmt/include/global.h
new file mode 100755
index 0000000..934400c
--- /dev/null
+++ b/board/wmt/include/global.h
@@ -0,0 +1,44 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef _GLOBAL_H_
+#define _GLOBAL_H_
+
+#ifndef _COMMON_DEF_H
+#include "common_def.h"
+#endif
+
+#ifndef _CONFIG_H_
+#include "config.h"
+#endif
+
+#ifndef _CHIPTOP_H_
+#include "chiptop.h"
+#endif
+
+#ifndef _USBREG_H_
+#include "../../../drivers/wmt_udcreg.h"
+#endif
+
+#define writel(val, addr)  (*(volatile unsigned long *)(addr) = (val))
+#define writew(val, addr)  (*(volatile unsigned short *)(addr) = (val))
+#define writeb(val, addr)  (*(volatile unsigned char *)(addr) = (val))
+#define readl(addr)   (*(volatile unsigned long *)(addr))
+#define readw(addr)   (*(volatile unsigned short *)(addr))
+#define readb(addr)   (*(volatile unsigned char *)(addr))
+
+#endif  /* _GLOBAL_H_ */
diff --git a/board/wmt/include/i2c.h b/board/wmt/include/i2c.h
new file mode 100755
index 0000000..b7ba557
--- /dev/null
+++ b/board/wmt/include/i2c.h
@@ -0,0 +1,255 @@
+/*++ 

+Copyright (c) 2010 WonderMedia Technologies, Inc.

+

+This program is free software: you can redistribute it and/or modify it under

+the terms of the GNU General Public License as published by the Free Software 

+Foundation, either version 2 of the License, or (at your option) any later version.

+

+This program is distributed in the hope that it will be useful, but WITHOUT ANY

+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A

+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You

+should have received a copy of the GNU General Public License along with this

+program. If not, see http://www.gnu.org/licenses/>.

+

+WonderMedia Technologies, Inc.

+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.

+--*/
+
+#ifndef __I2C_H__
+#define __I2C_H__
+
+/*
+ *   I2C register struct
+ *
+ */
+
+#define BA_I2C0 0xD8280000
+#define BA_I2C1 0xD8320000
+#define BA_I2C2 0xD83A0000  /* I2C2 Base Address */

+#define BA_I2C3 0xD83B0000  /* I2C3 Base Address */

+

+
+struct I2C_REG {
+	volatile unsigned short IICCR;		/* IIC controller control register*/
+	volatile unsigned short IICTCR;		/* IIC controller transfer control register*/
+	volatile unsigned short IICSR;		/* IIC controller status register*/
+	volatile unsigned short IICISR;		/* IIC controller interrupt status register*/
+	volatile unsigned short IICIMR;		/* IIC controller interrupt mask register*/
+	volatile unsigned short IICDR;		/* IIC controller data I/O buffer register*/
+	volatile unsigned short IICTR;		/* IIC controller time parameter register*/
+	volatile unsigned short IICDIV;		/* IIC controller clock divider register*/
+	volatile unsigned short IICSCR;		/* IIC slave controller control register*/
+	volatile unsigned short IICSSR;		/* IIC slave controller status register*/
+	volatile unsigned short IICSISR;	/* IIC slave controller interrupt status register*/
+	volatile unsigned short IICSIMR;	/* IIC slave controller interrupt mask register*/
+	volatile unsigned short IICSDR;		/* IIC slave controller data I/O buffer register*/
+	volatile unsigned short IICSTR;		/* IIC slave controller time parameter register*/
+};
+
+
+/*
+ *  I2C_CR_REG
+ *  I2C Controller Control
+ */
+/* Reserved [15:05] */
+/* [04:04] -- PCLK_SLE tied to Zero */
+#define I2C_CR_CPU_RDY                  0x0008
+#define I2C_CR_TX_END                   0x0004
+#define I2C_CR_TX_NEXT_NO_ACK           0x0002
+#define I2C_CR_TX_NEXT_ACK              0x0000
+#define I2C_CR_ENABLE                   0x0001
+#define I2C_SLAV_MODE_SEL BIT15
+
+/*
+ *  I2C_TCR_REG
+ *  I2C Transfer Control
+ *
+ */
+#define I2C_TCR_HS_MODE			0x02000		/* [13:13] */
+#define I2C_TCR_MODE_SEL		0x0000		/*i determine by BIT15 */
+#define I2C_TCR_STANDARD_MODE           0x0000          /* [15:15] */
+#define I2C_TCR_FAST_MODE               0x8000
+#define I2C_TCR_MODE_MASK               0x8000
+#define I2C_TCR_MASTER_WRITE            0x0000          /* [14:14] */
+#define I2C_TCR_MASTER_READ             0x4000
+/* Reserved [13:07] */
+#define I2C_TCR_SLAVE_ADDR_MASK         0x007F          /* [06:00] */
+
+/*
+ *  I2C_CSR_REG
+ *  I2C Status
+ *
+ */
+/* Reserved [15:02] */
+#define I2C_READY                       0x0002          /* [01:01] R */
+#define I2C_BUSY                        0x0000
+#define I2C_STATUS_MASK                 0x0002
+#define I2C_CSR_RCV_ACK                 0x0000          /* [00:00] R */
+#define I2C_CSR_RCV_NOT_ACK             0x0001
+#define I2C_CSR_RCV_ACK_MASK            0x0001
+
+/*
+ *  I2C_ISR_REG
+ *  I2C Interrupt Status
+ *
+ */
+/* Reserved [15:03] */
+#define I2C_ISR_SCL_TIME_OUT              0x0004          /* [02:02] R */
+#define I2C_ISR_SCL_TIME_OUT_WRITE_CLEAR  0x0004
+#define I2C_ISR_BYTE_END                  0x0002          /* [01:01] R */
+#define I2C_ISR_BYTE_END_WRITE_CLEAR      0x0002
+#define I2C_ISR_NACK_ADDR                 0x0001          /* [00:00] R */
+#define I2C_ISR_NACK_ADDR_WRITE_CLEAR     0x0001
+
+#define I2C_ISR_ALL_WRITE_CLEAR           0x0007
+/*
+ *  I2C_IMR_REG
+ *  I2C Interrupt Mask
+ *
+ */
+/* Reserved [15:03] */
+#define I2C_IMR_SCL_TIME_OUT_MASK       0x0004          /* [02:02]  */
+#define I2C_IMR_BYTE_END_MASK           0x0002          /* [01:01]  */
+#define I2C_IMR_NACK_ADDR_MASK          0x0001          /* [00:00]  */
+
+#define I2C_IMR_ALL_ENABLE              0x0007
+/*
+ *  I2C_CDR_REG
+ *  I2C Data IO
+ *
+ */
+#define I2C_CDR_DATA_READ_MASK          0xFF00          /* [15:08]  */
+#define I2C_CDR_DATA_WRITE_MASK         0x00FF          /* [07:00]  */
+
+
+/*
+ *  I2C_TR_REG
+ *  I2C Timer Parameters
+ *
+ */
+#define I2C_TR_SCL_TIME_OUT_MASK        0xFF00          /* [15:08]  */
+#define I2C_TR_FSTP_MASK                0x00FF          /* [07:00]  */
+
+#define I2C_TR_STD_VALUE                0x8064    /* standard mode*/
+#define I2C_TR_FAST_VALUE               0x8019    /* fast mode*/
+
+/*
+ *  I2C_DIV_REG  [Refer to "DS_VT8420_100.pdf" page 188]
+ *  I2C DIV
+ *
+ */
+
+#define APB_48M_I2C_DIV                 3  /*  48/(3+1) = 12*/
+#define APB_60M_I2C_DIV                 4  /*  60/(4+1) = 12*/
+#define APB_72M_I2C_DIV                 5  /*  72/(5+1) = 12*/
+#define APB_84M_I2C_DIV                 6  /*  84/(6+1) = 12*/
+#define APB_96M_I2C_DIV                 7  /*  96/(7+1) = 12*/
+#define APB_108M_I2C_DIV                8  /* 108/(8+1) = 12*/
+#define APB_120M_I2C_DIV                9  /* 120/(9+1) = 12*/
+#define APB_132M_I2C_DIV                10  /* 132/(10+1) = 12*/
+#define APB_144M_I2C_DIV                11  /* 144/(11+1) = 12*/
+#define HS_MASTER_CODE			0x0800
+
+#define I2C_SLAVE_ADDR 0x59
+#define I2C_SLAVE_MASK 0x007F
+#define I2C_SLAVE_NACK BIT12
+#define I2C_SLAVE_HS_MODE BIT14
+#define I2C_SLAVE_EN BIT15
+
+#define I2C_SISR_SCL_TIME_OUT              0x0004          /* [02:02] R */
+#define I2C_SISR_SCL_TIME_OUT_WRITE_CLEAR  0x0004
+#define I2C_SISR_BYTE_END                  0x0002          /* [01:01] R */
+#define I2C_SISR_BYTE_END_WRITE_CLEAR      0x0002
+#define I2C_SISR_DAT_REQ                      0x0001          /* [00:00] R */
+#define I2C_SISR_DAT_REQ_WRITE_CLEAR          0x0001
+
+#define I2C_SISR_ALL_WRITE_CLEAR           0x0007
+
+#define I2C_SIMR_SCL_TIME_OUT_MASK       0x0004          /* [02:02]  */
+#define I2C_SIMR_BYTE_END_MASK           0x0002          /* [01:01]  */
+#define I2C_SIMR_NACK_ADDR_MASK          0x0001          /* [00:00]  */
+
+#define I2C_SIMR_ALL_ENABLE              0x0007
+
+#define I2C_SRCV_NACK BIT0
+#define I2C_SREAD BIT1
+#define I2C_SACT BIT2
+
+#define I2C_SLAVE_WRITE_DATA_SHIFT 0
+#define I2C_SLAVE_READ_DATA_SHIFT 8
+#define I2C_SLAVE_READ_DATA_MASK 0xFF00
+#define I2C_SLAVE_WRITE_DATA_MASK 0x00FF
+
+
+
+/*---------------------------------------------------------------------------------------*/
+/* I2C Data structure*/
+/*---------------------------------------------------------------------------------------*/
+
+
+enum i2c_mode_s {
+    I2C_STANDARD_MODE = 0 ,
+    I2C_FAST_MODE     = 1 ,
+    I2C_HS_MODE		= 2,
+};
+
+/*
+unsigned char g_data[10];
+*/
+
+struct i2c_s {
+    struct I2C_REG *regs;
+    int		irq_no ;
+    enum i2c_mode_s	i2c_mode ;
+    int		isr_nack ;
+    int		isr_byte_end ;
+    int		isr_timeout ;
+
+} ;
+
+/* I2C Message - used for pure i2c transaction*/
+/**/
+/* flags*/
+#define I2C_M_RD                0x01
+#define I2C_M_WR                0x00
+
+struct i2c_msg_s {
+    unsigned short addr;        /* slave address*/
+    unsigned short flags;       /* flags*/
+    unsigned short len;         /* msg length*/
+    unsigned char *buf;        /* pointer to msg data*/
+} ;
+
+/*---------------------------------------------------------------------------------------*/
+/* Defined in the i2cif.c*/
+/*---------------------------------------------------------------------------------------*/
+int i2c_register_write(int index, unsigned char data, unsigned char address);
+
+int i2c_register_read(int index, unsigned char address);
+
+void i2c_init(int speed, int slaveaddr);
+
+int i2c_write_short(int index, unsigned short data, unsigned char address);
+
+void set_div(char value);
+
+void dump_reg(void);
+
+int delay_ms(unsigned int time);
+
+int i2c_transfer(struct i2c_msg_s *msgs, int num);
+
+void i2c1_init(int speed, int slaveaddr);
+
+int i2c1_transfer(struct i2c_msg_s *msgs, int num);
+

+void i2c2_init(int speed, int slaveaddr);

+

+int i2c2_transfer(struct i2c_msg_s *msgs, int num);

+

+void i2c3_init(int speed, int slaveaddr);

+

+int i2c3_transfer(struct i2c_msg_s *msgs, int num);

+

+int wmt_i2c_transfer(struct i2c_msg_s msgs[], int num, int adap_id);

+#endif /* __I2C_Hi__*/
diff --git a/board/wmt/include/iomux.h b/board/wmt/include/iomux.h
new file mode 100755
index 0000000..fead447
--- /dev/null
+++ b/board/wmt/include/iomux.h
@@ -0,0 +1,247 @@
+/*
+ * --------------------------------------------------------------------------
+ *
+ *       Filename:  iomux-wm8880.h
+ *
+ *    Description:  gpio table for wm8880
+ *
+ *        Version:  0.01
+ *        Created:  2013Äê04ÔÂ09ÈÕ 10ʱ16·Ö20Ãë
+ *
+ *         Author:  sammei (sammei@wondermedia.com.cn),
+ *        Company:
+ * --------------------------------------------------------------------------
+ */
+
+/*
+ * Base address:	0xd8110000
+ * register offset:
+ * 	Data Input	- 0x0000
+ * 	Gpio Enable	- 0x0040
+ * 	Output Enable	- 0x0080
+ * 	Output Data	- 0x00c0
+ * 	Pull Enable	- 0x0480
+ * 	Pull Control	- 0x04c0
+ * 	IO Strength	- 0x0800
+ */
+
+/*       GPn  bit  irq   macro-name */
+
+/* GP0 */
+WMT_PIN(0x00, 0, 0x00, WMT_PIN_GP0_GPIO0)		/* 0 */
+WMT_PIN(0x00, 1, 0x01, WMT_PIN_GP0_GPIO1)		/* 1 */
+WMT_PIN(0x00, 2, 0x02, WMT_PIN_GP0_GPIO2)		/* 2 */
+WMT_PIN(0x00, 3, 0x03, WMT_PIN_GP0_GPIO3)		/* 3 */
+WMT_PIN(0x00, 4, 0x04, WMT_PIN_GP0_GPIO4)		/* 4 */
+WMT_PIN(0x00, 5, 0x05, WMT_PIN_GP0_GPIO5)		/* 5 */
+WMT_PIN(0x00, 6, 0x06, WMT_PIN_GP0_GPIO6)		/* 6 */
+WMT_PIN(0x00, 7, 0x07, WMT_PIN_GP0_GPIO7)		/* 7 */
+
+/* GP1 */
+WMT_PIN(0x01, 0, 0x08, WMT_PIN_GP1_GPIO8)		/* 8  */
+WMT_PIN(0x01, 1, 0x09, WMT_PIN_GP1_GPIO9)		/* 9  */
+WMT_PIN(0x01, 2, 0x0a, WMT_PIN_GP1_GPIO10)		/* 10 */
+WMT_PIN(0x01, 3, 0x0b, WMT_PIN_GP1_GPIO11)		/* 11 */
+WMT_PIN(0x01, 4, 0x0c, WMT_PIN_GP1_GPIO12)		/* 12 */
+WMT_PIN(0x01, 5, 0x0d, WMT_PIN_GP1_GPIO13)		/* 13 */
+WMT_PIN(0x01, 6, 0x0e, WMT_PIN_GP1_GPIO14)		/* 14 */
+WMT_PIN(0x01, 7, 0x0f, WMT_PIN_GP1_GPIO15)		/* 15 */
+
+/* GP2 */
+WMT_PIN(0x02, 0, 0x10, WMT_PIN_GP2_GPIO16)		/* 16 */
+WMT_PIN(0x02, 1, 0x11, WMT_PIN_GP2_GPIO17)		/* 17 */
+WMT_PIN(0x02, 2, 0x12, WMT_PIN_GP2_GPIO18)		/* 18 */
+WMT_PIN(0x02, 3, 0x13, WMT_PIN_GP2_GPIO19)		/* 19 */
+
+/* GP4 */
+WMT_PIN(0x04, 0,   -1, WMT_PIN_GP4_VDOUT0)		/* 20 */
+WMT_PIN(0x04, 1,   -1, WMT_PIN_GP4_VDOUT1)		/* 21 */
+WMT_PIN(0x04, 2,   -1, WMT_PIN_GP4_VDOUT2)		/* 22 */
+WMT_PIN(0x04, 3,   -1, WMT_PIN_GP4_VDOUT3)		/* 23 */
+WMT_PIN(0x04, 4,   -1, WMT_PIN_GP4_VDOUT4)		/* 24 */
+WMT_PIN(0x04, 5,   -1, WMT_PIN_GP4_VDOUT5)		/* 25 */
+WMT_PIN(0x04, 6,   -1, WMT_PIN_GP4_VDOUT6)		/* 26 */
+WMT_PIN(0x04, 7,   -1, WMT_PIN_GP4_VDOUT7)		/* 27 */
+
+/* GP5 */
+WMT_PIN(0x05, 0,   -1, WMT_PIN_GP5_VDOUT8)		/* 28 */
+WMT_PIN(0x05, 1,   -1, WMT_PIN_GP5_VDOUT9)		/* 29 */
+WMT_PIN(0x05, 2,   -1, WMT_PIN_GP5_VDOUT10)		/* 30 */
+WMT_PIN(0x05, 3, 0x14, WMT_PIN_GP5_VDOUT11)		/* 31 */
+WMT_PIN(0x05, 4, 0x15, WMT_PIN_GP5_VDOUT12)		/* 32 */
+WMT_PIN(0x05, 5,   -1, WMT_PIN_GP5_VDOUT13)		/* 33 */
+WMT_PIN(0x05, 6,   -1, WMT_PIN_GP5_VDOUT14)		/* 34 */
+WMT_PIN(0x05, 7,   -1, WMT_PIN_GP5_VDOUT15)		/* 35 */
+
+/* GP6 */
+WMT_PIN(0x06, 0,   -1, WMT_PIN_GP6_VDOUT16)		/* 36 */
+WMT_PIN(0x06, 1,   -1, WMT_PIN_GP6_VDOUT17)		/* 37 */
+WMT_PIN(0x06, 2, 0x16, WMT_PIN_GP6_VDOUT18)		/* 38 */
+WMT_PIN(0x06, 3, 0x17, WMT_PIN_GP6_VDOUT19)		/* 39 */
+WMT_PIN(0x06, 4, 0x18, WMT_PIN_GP6_VDOUT20)		/* 40 */
+WMT_PIN(0x06, 5, 0x19, WMT_PIN_GP6_VDOUT21)		/* 41 */
+WMT_PIN(0x06, 6,   -1, WMT_PIN_GP6_VDOUT22)		/* 42 */
+WMT_PIN(0x06, 7,   -1, WMT_PIN_GP6_VDOUT23)		/* 43 */
+
+/* GP7 */
+WMT_PIN(0x07, 0,   -1, WMT_PIN_GP7_VDDEN)		/* 44 */
+WMT_PIN(0x07, 1,   -1, WMT_PIN_GP7_VDHSYNC)		/* 45 */
+WMT_PIN(0x07, 2,   -1, WMT_PIN_GP7_VDVSYNC)		/* 46 */
+WMT_PIN(0x07, 3,   -1, WMT_PIN_GP7_VDCLK)		/* 47 */
+
+/* GP8 */
+WMT_PIN(0x08, 0,   -1, WMT_PIN_GP8_VDIN0)		/* 48 */
+WMT_PIN(0x08, 1,   -1, WMT_PIN_GP8_VDIN1)		/* 49 */
+WMT_PIN(0x08, 2,   -1, WMT_PIN_GP8_VDIN2)		/* 50 */
+WMT_PIN(0x08, 3,   -1, WMT_PIN_GP8_VDIN3)		/* 51 */
+WMT_PIN(0x08, 4,   -1, WMT_PIN_GP8_VDIN4)		/* 52 */
+WMT_PIN(0x08, 5,   -1, WMT_PIN_GP8_VDIN5)		/* 53 */
+WMT_PIN(0x08, 6,   -1, WMT_PIN_GP8_VDIN6)		/* 54 */
+WMT_PIN(0x08, 7,   -1, WMT_PIN_GP8_VDIN7)		/* 55 */
+
+/* GP9 */
+WMT_PIN(0x09, 0,   -1, WMT_PIN_GP9_VHSYNC)		/* 56 */
+WMT_PIN(0x09, 1,   -1, WMT_PIN_GP9_VVSYNC)		/* 57 */
+WMT_PIN(0x09, 2,   -1, WMT_PIN_GP9_VCLK)		/* 58 */
+
+/* GP10 */
+WMT_PIN(0x0a, 0,   -1, WMT_PIN_GP10_I2SDACDAT0)		/* 59 */
+WMT_PIN(0x0a, 1,   -1, WMT_PIN_GP10_I2SDACDAT1)		/* 60 */
+WMT_PIN(0x0a, 2,   -1, WMT_PIN_GP10_I2SDACDAT2)		/* 61 */
+WMT_PIN(0x0a, 3,   -1, WMT_PIN_GP10_I2SDACDAT3)		/* 62 */
+WMT_PIN(0x0a, 4,   -1, WMT_PIN_GP10_I2SADCDAT2)		/* 63 */
+WMT_PIN(0x0a, 5,   -1, WMT_PIN_GP10_I2SDACLRC)		/* 64 */
+WMT_PIN(0x0a, 6,   -1, WMT_PIN_GP10_I2SDACBCLK)		/* 65 */
+WMT_PIN(0x0a, 7,   -1, WMT_PIN_GP10_I2SDACMCLK)		/* 66 */
+
+/* GP11 */
+WMT_PIN(0x0b, 0,   -1, WMT_PIN_GP11_I2SADCDATA0)	/* 67 */
+WMT_PIN(0x0b, 1,   -1, WMT_PIN_GP11_I2SADCDATA1)	/* 68 */
+WMT_PIN(0x0b, 2,   -1, WMT_PIN_GP11_I2SSPDIF0)		/* 69 */
+
+/* GP12 */
+WMT_PIN(0x0c, 0,   -1, WMT_PIN_GP12_SPI0CLK)		/* 70 */
+WMT_PIN(0x0c, 1,   -1, WMT_PIN_GP12_SPI0MISO)		/* 71 */
+WMT_PIN(0x0c, 2,   -1, WMT_PIN_GP12_SPI0MOSI)		/* 72 */
+WMT_PIN(0x0c, 3,   -1, WMT_PIN_GP12_SPI0SS0)		/* 73 */
+// WMT_PIN(0x0c, 4,   -1, WMT_PIN_GP12_SD018SEL)		/* 73 */
+
+/* GP13 */
+WMT_PIN(0x0d, 0,   -1, WMT_PIN_GP13_SD0CLK)		/* 74 */
+WMT_PIN(0x0d, 1,   -1, WMT_PIN_GP13_SD0CMD)		/* 75 */
+WMT_PIN(0x0d, 2,   -1, WMT_PIN_GP13_SD0WP)		/* 76 */
+WMT_PIN(0x0d, 3,   -1, WMT_PIN_GP13_SD0DATA0)		/* 77 */
+WMT_PIN(0x0d, 4,   -1, WMT_PIN_GP13_SD0DATA1)		/* 78 */
+WMT_PIN(0x0d, 5,   -1, WMT_PIN_GP13_SD0DATA2)		/* 79 */
+WMT_PIN(0x0d, 6,   -1, WMT_PIN_GP13_SD0DATA3)		/* 80 */
+WMT_PIN(0x0d, 7,   -1, WMT_PIN_GP13_SD0PWRSW)		/* 81 */
+
+/* GP14 */
+WMT_PIN(0x0e, 0,   -1, WMT_PIN_GP14_NANDALE)		/* 82 */
+WMT_PIN(0x0e, 1,   -1, WMT_PIN_GP14_NANDCLE)		/* 83 */
+WMT_PIN(0x0e, 2,   -1, WMT_PIN_GP14_NANDWE)		/* 84 */
+WMT_PIN(0x0e, 3,   -1, WMT_PIN_GP14_NANDRE)		/* 85 */
+WMT_PIN(0x0e, 4,   -1, WMT_PIN_GP14_NANDWP)		/* 86 */
+WMT_PIN(0x0e, 5,   -1, WMT_PIN_GP14_NANDWPD)		/* 87 */
+WMT_PIN(0x0e, 6,   -1, WMT_PIN_GP14_NANDRB0)		/* 88 */
+WMT_PIN(0x0e, 7,   -1, WMT_PIN_GP14_NANDRB1)		/* 89 */
+
+/* GP15 */
+WMT_PIN(0x0f, 0,   -1, WMT_PIN_GP14_NANDCE0)		/* 90 */
+WMT_PIN(0x0f, 1,   -1, WMT_PIN_GP14_NANDCE1)		/* 91 */
+WMT_PIN(0x0f, 2,   -1, WMT_PIN_GP14_NANDCE2)		/* 92 */
+WMT_PIN(0x0f, 3,   -1, WMT_PIN_GP14_NANDCE3)		/* 93 */
+WMT_PIN(0x0f, 4,   -1, WMT_PIN_GP14_NANDDQS)		/* 94 */
+
+/* GP16 */
+WMT_PIN(0x10, 0,   -1, WMT_PIN_GP16_NANDDIO0)		/* 95 */
+WMT_PIN(0x10, 1,   -1, WMT_PIN_GP16_NANDDIO1)		/* 96 */
+WMT_PIN(0x10, 2,   -1, WMT_PIN_GP16_NANDDIO2)		/* 97 */
+WMT_PIN(0x10, 3,   -1, WMT_PIN_GP16_NANDDIO3)		/* 98 */
+WMT_PIN(0x10, 4,   -1, WMT_PIN_GP16_NANDDIO4)		/* 99 */
+WMT_PIN(0x10, 5,   -1, WMT_PIN_GP16_NANDDIO5)		/* 100 */
+WMT_PIN(0x10, 6,   -1, WMT_PIN_GP16_NANDDIO6)		/* 101 */
+WMT_PIN(0x10, 7,   -1, WMT_PIN_GP16_NANDDIO7)		/* 102 */
+
+/* GP17 */
+WMT_PIN(0x11, 0,   -1, WMT_PIN_GP17_I2C0SCL)		/* 103 */
+WMT_PIN(0x11, 1,   -1, WMT_PIN_GP17_I2C0SDA)		/* 104 */
+WMT_PIN(0x11, 2,   -1, WMT_PIN_GP17_I2C1SCL)		/* 105 */
+WMT_PIN(0x11, 3,   -1, WMT_PIN_GP17_I2C1SDA)		/* 106 */
+WMT_PIN(0x11, 4,   -1, WMT_PIN_GP17_I2C2SCL)		/* 107 */
+WMT_PIN(0x11, 5,   -1, WMT_PIN_GP17_I2C2SDA)		/* 108 */
+WMT_PIN(0x11, 6,   -1, WMT_PIN_GP17_C24MOUT)		/* 109 */
+
+/* GP18 */
+WMT_PIN(0x12, 0,   -1, WMT_PIN_GP18_UART0TXD)		/* 110 */
+WMT_PIN(0x12, 1,   -1, WMT_PIN_GP18_UART0RXD)		/* 111 */
+WMT_PIN(0x12, 2,   -1, WMT_PIN_GP18_UART0RTS)		/* 112 */
+WMT_PIN(0x12, 3,   -1, WMT_PIN_GP18_UART0CTS)		/* 113 */
+WMT_PIN(0x12, 4,   -1, WMT_PIN_GP18_UART1TXD)		/* 114 */
+WMT_PIN(0x12, 5,   -1, WMT_PIN_GP18_UART1RXD)		/* 115 */
+WMT_PIN(0x12, 6,   -1, WMT_PIN_GP18_UART1RTS)		/* 116 */
+WMT_PIN(0x12, 7,   -1, WMT_PIN_GP18_UART1CTS)		/* 117 */
+
+/* GP19 */
+WMT_PIN(0x13, 0,   -1, WMT_PIN_GP19_SD2DATA0)		/* 118 */
+WMT_PIN(0x13, 1,   -1, WMT_PIN_GP19_SD2DATA1)		/* 119 */
+WMT_PIN(0x13, 2,   -1, WMT_PIN_GP19_SD2DATA2)		/* 120 */
+WMT_PIN(0x13, 3,   -1, WMT_PIN_GP19_SD2DATA3)		/* 121 */
+WMT_PIN(0x13, 4,   -1, WMT_PIN_GP19_SD2CMD)		/* 122 */
+WMT_PIN(0x13, 5,   -1, WMT_PIN_GP19_SD2CLK)		/* 123 */
+WMT_PIN(0x13, 6,   -1, WMT_PIN_GP19_SD2PWRSW)		/* 124 */
+WMT_PIN(0x13, 7,   -1, WMT_PIN_GP19_SD2WP)		/* 125 */
+
+/* GP20 */
+WMT_PIN(0x14, 0,   -1, WMT_PIN_GP20_C24MHZCLKI)		/* 126 */
+WMT_PIN(0x14, 1,   -1, WMT_PIN_GP20_PWMOUT0)		/* 127 */
+
+/* GP21 */
+WMT_PIN(0x15, 0,   -1, WMT_PIN_GP21_HDMIDCSDA)		/* 128 */
+WMT_PIN(0x15, 1,   -1, WMT_PIN_GP21_HDMIDCSCL)		/* 129 */
+WMT_PIN(0x15, 2,   -1, WMT_PIN_GP21_HDMIHPD)		/* 130 */
+
+/* GP23 */
+WMT_PIN(0x17, 0,   -1, WMT_PIN_GP23_I2C3SDA)		/* 131 */
+WMT_PIN(0x17, 1,   -1, WMT_PIN_GP23_I2C3SCL)		/* 132 */
+WMT_PIN(0x17, 2,   -1, WMT_PIN_GP23_HDMICEC)		/* 133 */
+
+/* GP24 */
+WMT_PIN(0x18, 0,   -1, WMT_PIN_GP24_SFCS0)		/* 134 */
+WMT_PIN(0x18, 1,   -1, WMT_PIN_GP24_SFCS1)		/* 135 */
+WMT_PIN(0x18, 2,   -1, WMT_PIN_GP24_SFCLK)		/* 136 */
+WMT_PIN(0x18, 3,   -1, WMT_PIN_GP24_SFDI)		/* 137 */
+WMT_PIN(0x18, 4,   -1, WMT_PIN_GP24_SFDO)		/* 138 */
+
+/* GP25 */
+
+/* Reversed */
+
+/* GP26 */
+WMT_PIN(0x1a, 0,   -1, WMT_PIN_GP26_PCM1MCLK)		/* 139 */
+WMT_PIN(0x1a, 1,   -1, WMT_PIN_GP26_PCM1CLK)		/* 140 */
+WMT_PIN(0x1a, 2,   -1, WMT_PIN_GP26_PCM1SYNC)		/* 141 */
+WMT_PIN(0x1a, 3,   -1, WMT_PIN_GP26_PCM1OUT)		/* 142 */
+WMT_PIN(0x1a, 4,   -1, WMT_PIN_GP26_PCM1IN)		/* 143 */
+
+/* GP60 */
+WMT_PIN(0x3c, 0,   -1, WMT_PIN_GP60_USBSW0)		/* 144 */
+WMT_PIN(0x3c, 1,   -1, WMT_PIN_GP60_USBATTTA0)		/* 145 */
+WMT_PIN(0x3c, 2,   -1, WMT_PIN_GP60_USB0C0)		/* 146 */
+WMT_PIN(0x3c, 3,   -1, WMT_PIN_GP60_USB0C1)		/* 147 */
+WMT_PIN(0x3c, 4,   -1, WMT_PIN_GP60_USB0C2)		/* 148 */
+
+/* GP62 */
+WMT_PIN(0x3e, 0,   -1, WMT_PIN_GP62_WAKEUP0)		/* 149 */
+WMT_PIN(0x3e, 1,   -1, WMT_PIN_GP62_CIRIN)		/* 150 */
+WMT_PIN(0x3e, 2,   -1, WMT_PIN_GP62_WAKEUP2)		/* 151 */
+WMT_PIN(0x3e, 3,   -1, WMT_PIN_GP62_WAKEUP3)		/* 152 */
+WMT_PIN(0x3e, 4,   -1, WMT_PIN_GP62_WAKEUP4)		/* 153 */
+WMT_PIN(0x3e, 5,   -1, WMT_PIN_GP62_WAKEUP5)		/* 154 */
+WMT_PIN(0x3e, 6,   -1, WMT_PIN_GP62_SUSGPIO0)		/* 155 */
+WMT_PIN(0x3e, 7,   -1, WMT_PIN_GP62_SUSGPIO1)		/* 156 */
+
+/* GP63 */
+WMT_PIN(0x3f, 2,   -1, WMT_PIN_GP63_SD0CD)		/* 157 */
+WMT_PIN(0x3f, 4,   -1, WMT_PIN_GP63_SD2CD)		/* 158 */
+
diff --git a/board/wmt/include/wmt_clk.h b/board/wmt/include/wmt_clk.h
new file mode 100755
index 0000000..6658edb
--- /dev/null
+++ b/board/wmt/include/wmt_clk.h
@@ -0,0 +1,132 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef _WMT_CLK_H_
+#define _WMT_CLK_H_
+
+/*
+ *   WMT_CLK register struct
+ *
+ */
+
+enum dev_id {
+ DEV_SDMMC0 = 0, /* PMC lower register offset PMC OFFSET + 0x250*/
+ DEV_SDMMC1 = 1,
+ DEV_SDMMC2 = 2,
+ /*DEV_SDMMC3 = 3,
+ DEV_ETHMAC = 4,*/
+ DEV_C24MOUT = 6,/*DEV_ETHPHY = 6,*/
+ DEV_RTC = 7,
+ DEV_I2C0 = 8,
+ DEV_I2C1 = 9,
+ DEV_I2C2 = 10,
+ DEV_GPIO = 11,
+ DEV_I2C3 = 12,
+ /*DEV_KEYPAD = 14,*/
+ DEV_CNMVDU = 15,/*DEV_EBM = 15,*/
+ DEV_PAXI = 16,
+ DEV_PWM = 17,
+ DEV_ADC = 18,
+ DEV_I2C4 = 19,
+ DEV_SCC = 21,
+ DEV_SYS = 22,
+ DEV_AMP = 24,
+ DEV_MALI = 26,
+ DEV_PCM0 = 27,
+ DEV_PCM1 = 28,
+ DEV_PERM = 30,
+ DEV_MBOX = 31,
+ 
+
+ DEV_DDRMC = 32, /* PMC upper register offset 0xd8130254 */
+ DEV_ARF   = 32+3,
+ DEV_ARFP  = 32+4,
+ DEV_DMA   = 32+5,
+ DEV_PDMA  = 32+6,
+ /*DEV_VDMA  = 32+7,*/
+ DEV_UHDC  = 32+9,
+ DEV_AHBB  = 32+13,
+ DEV_NAND  = 32+16,
+ /*DEV_NOR   = 32+17,*/
+ DEV_SPI0  = 32+19,
+ DEV_SPI1  = 32+20,
+ DEV_SF    = 32+23,
+ DEV_UART0 = 32+24,
+ DEV_UART1 = 32+25,
+ DEV_UART2 = 32+26,
+ DEV_UART3 = 32+27,
+ DEV_CSI0 = 32+28,/*DEV_UART4 = 32+28,*/
+ DEV_CSI1 = 32+29,/*DEV_UART5 = 32+29,*/
+
+ DEV_WMTNA   = 64,/*DEV_NA0   = 64,*/ /* PMC upper register offset 0xd8130258 */
+ /*DEV_NA0REF= 64+1,*/
+ DEV_CNMNA = 64+2,
+ DEV_JDEC  = 64+3,
+ DEV_MSVD  = 64+4,
+ DEV_VP8DEC= 64+5,
+ DEV_SAE   = 64+6,
+ DEV_HDCE  = 64+7,
+ DEV_H264  = 64+8,
+ DEV_JENC  = 64+9,
+ DEV_LVDS  = 64+14,
+ DEV_CIR   = 64+15,
+ DEV_NA12  = 64+16,
+ DEV_VPU   = 64+17,
+ DEV_VPP   = 64+18,
+ DEV_VID   = 64+19,
+ DEV_WMTVDU  = 64+20,/*DEV_VDU   = 64+20,*/
+ DEV_SCL444U = 64+21,
+ DEV_HDMII2C = 64+22,
+ DEV_HDMI  = 64+23,
+ DEV_GOVW  = 64+24,
+ DEV_GOVRHD= 64+25,
+ DEV_GE    = 64+26,
+ DEV_DISP  = 64+27,
+ DEV_DVO   = 64+29,
+ DEV_HDMILVDS = 64+30,
+ DEV_SDTV  = 64+31,
+ 
+ DEV_I2S   = 96+2, /* PMC upper register offset 0xd8130258 */
+ /*DEV_ROT,			
+ DEV_XD,*/
+
+
+ DEV_ARM, /* number >= 128 has no clk_en to enable clk */
+ DEV_AHB,
+ DEV_APB,
+ DEV_L2C,
+ DEV_L2CAXI,
+ DEV_L2CPAXI,
+ DEV_AT,
+ DEV_PERI,
+ DEV_TRACE,
+ DEV_DBG,
+};
+
+enum clk_cmd {
+CLK_DISABLE = 0,
+GET_FREQ,
+CLK_ENABLE,
+SET_DIV,
+SET_PLL,
+SET_PLLDIV
+};
+struct pll_map {
+unsigned int freq;
+unsigned int pll;
+};
+#endif /* __WMT_CLK_H__*/
diff --git a/board/wmt/include/wmt_gpio.h b/board/wmt/include/wmt_gpio.h
new file mode 100755
index 0000000..e2e150b
--- /dev/null
+++ b/board/wmt/include/wmt_gpio.h
@@ -0,0 +1,785 @@
+/*++
+linux/arch/arm/mach-wmt/include/mach/wmt_gpio.h
+
+Copyright (c) 2013  WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under the
+terms of the GNU General Public License as published by the Free Software Foundation,
+either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program.  If not, see <http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+/* Be sure that virtual mapping is defined right */
+
+#ifndef __WMT_GPIO_H
+/* To assert that only one occurrence is included */
+#define __WMT_GPIO_H
+
+/*-------------------- EXPORTED PRIVATE CONSTANTS -----------------------------*/
+
+/*-------------------- EXPORTED PRIVATE TYPES----------------------------------*/
+
+/*-------------------- EXPORTED PRIVATE VARIABLES -----------------------------*/
+#ifdef XXX_C /* allocate memory for variables only in xxx.c */
+#       define EXTERN
+#else
+#       define EXTERN   extern
+#endif /* ifdef XXX_C */
+
+
+#undef EXTERN
+
+/*--------------------- EXPORTED PRIVATE MACROS -------------------------------*/
+#define __GPIO_BASE      0xD8110000
+
+#define GIRQ_LOW                        0x00            /* Input zero generate GPIO_IRQ signal */
+#define GIRQ_HIGH                       0x01            /* Input one generate GPIO_IRQ signal */
+#define GIRQ_FALLING            0x02            /* Falling edge generate GPIO_IRQ signal */
+#define GIRQ_RISING                     0x03            /* Rising edge generate GPIO_IRQ signal */
+#define GIRQ_BOTHEDGE           0x04
+#define GIRQ_TYPEMASK           0x07
+#define GIRQ_TYPE(idx, type)    ((type & GIRQ_TYPEMASK) << (idx * 8)) /* idx must be 0-3 */
+#define GIRQ_EN_STS(idx)                ( 1 << ((idx+1)*8-1) )  /* idx must be 0-3 */
+
+#define GPIO_ID_GP0_BYTE_ADDR					(__GPIO_BASE + 0x00  )/* [0x0] */
+#define GPIO_ID_GP1_BYTE_ADDR 					(__GPIO_BASE + 0x01  )/* [0x1] */
+#define GPIO_ID_GP2_BYTE_ADDR					(__GPIO_BASE + 0x02  )/* [0x2] */
+#define GPIO_ID_GP4_VDOUT_7_0_BYTE_ADDR			(__GPIO_BASE + 0x04  )/* [0x4] */
+#define GPIO_ID_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0x05  )/* [0x5] */
+#define GPIO_ID_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0x06  )/* [0x6] */
+#define GPIO_ID_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0x07  )/* [0x7] */
+#define GPIO_ID_GP8_VDIN_BYTE_ADDR				(__GPIO_BASE + 0x08  )/* [0x8] */
+#define GPIO_ID_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0x09  )/* [0x9] */
+#define GPIO_ID_GP10_I2S_BYTE_ADDR				(__GPIO_BASE + 0x0A  )/* [0xA] */
+#define GPIO_ID_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0x0B  )/* [0xB] */
+#define GPIO_ID_GP12_SPI_BYTE_ADDR				(__GPIO_BASE + 0x0C  )/* [0xC] */
+#define GPIO_ID_GP13_SD0_BYTE_ADDR   			(__GPIO_BASE + 0x0D  )/* [0xD] */
+#define GPIO_ID_GP14_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x0E  )/* [0xE] */
+#define GPIO_ID_GP15_NAND_BYTE_ADDR				(__GPIO_BASE + 0x0F  )/* [0xF] */
+#define GPIO_ID_GP16_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x10  )/* [0x10] */
+#define GPIO_ID_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0x11  )/* [0x11] */
+#define GPIO_ID_GP18_UART_BYTE_ADDR				(__GPIO_BASE + 0x12  )/* [0x12] */
+#define GPIO_ID_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0x13  )/* [0x13] */
+#define GPIO_ID_GP20_PWM0_BYTE_ADDR       		(__GPIO_BASE + 0x14  )/* [0x14] */
+#define GPIO_ID_GP21_HDMI_BYTE_ADDR       		(__GPIO_BASE + 0x15  )/* [0x15] */
+#define GPIO_ID_GP23_I2C3_BYTE_ADDR	    	   	(__GPIO_BASE + 0x17  )/* [0x17] */
+#define GPIO_ID_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0x18  )/* [0x18] */
+#define GPIO_ID_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0x1A  )/* [0x1A] */
+#define GPIO_ID_GP60_USB_BYTE_ADDR				(__GPIO_BASE + 0x3C  )/* [0x3C] */
+#define GPIO_ID_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0x3E  )/* [0x3E] */
+#define GPIO_ID_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0x3F  )/* [0x3F] */
+#define GPIO_CTRL_GP0_BYTE_ADDR 				(__GPIO_BASE + 0x40  )/* [0x40] */
+#define GPIO_CTRL_GP1_BYTE_ADDR 				(__GPIO_BASE + 0x41  )/* [0x41] */
+#define GPIO_CTRL_GP2_BYTE_ADDR 				(__GPIO_BASE + 0x42  )/* [0x42] */
+#define GPIO_CTRL_GP4_VDOUT_7_0_BYTE_ADDR		(__GPIO_BASE + 0x44  )/* [0x44] */
+#define GPIO_CTRL_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0x45  )/* [0x45] */
+#define GPIO_CTRL_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0x46  )/* [0x46] */
+#define GPIO_CTRL_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0x47  )/* [0x47] */
+#define GPIO_CTRL_GP8_VDIN_BYTE_ADDR			(__GPIO_BASE + 0x48  )/* [0x48] */
+#define GPIO_CTRL_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0x49  )/* [0x49] */
+#define GPIO_CTRL_GP10_I2S_BYTE_ADDR			(__GPIO_BASE + 0x4A  )/* [0x4A] */
+#define GPIO_CTRL_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0x4B  )/* [0x4B] */
+#define GPIO_CTRL_GP12_SPI_BYTE_ADDR			(__GPIO_BASE + 0x4C  )/* [0x4C] */
+#define GPIO_CTRL_GP13_SD0_BYTE_ADDR       		(__GPIO_BASE + 0x4D  )/* [0x4D] */
+#define GPIO_CTRL_GP14_NAND_SD1_BYTE_ADDR		(__GPIO_BASE + 0x4E  )/* [0x4E] */
+#define GPIO_CTRL_GP15_NAND_BYTE_ADDR			(__GPIO_BASE + 0x4F  )/* [0x4F] */
+#define GPIO_CTRL_GP16_NAND_SD1_BYTE_ADDR		(__GPIO_BASE + 0x50  )/* [0x50] */
+#define GPIO_CTRL_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0x51  )/* [0x51] */
+#define GPIO_CTRL_GP18_UART_BYTE_ADDR			(__GPIO_BASE + 0x52  )/* [0x52] */
+#define GPIO_CTRL_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0x53  )/* [0x53] */
+#define GPIO_CTRL_GP20_PWM0_BYTE_ADDR       	(__GPIO_BASE + 0x54  )/* [0x54] */
+#define GPIO_CTRL_GP21_HDMI_BYTE_ADDR       	(__GPIO_BASE + 0x55  )/* [0x55] */
+#define GPIO_CTRL_GP23_I2C3_BYTE_ADDR	    	(__GPIO_BASE + 0x57  )/* [0x57] */
+#define GPIO_CTRL_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0x58  )/* [0x58] */
+#define GPIO_CTRL_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0x5A  )/* [0x5A] */
+#define GPIO_CTRL_GP60_USB_BYTE_ADDR			(__GPIO_BASE + 0x7C  )/* [0x7C] */
+#define GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0x7E  )/* [0x7E] */
+#define GPIO_CTRL_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0x7F  )/* [0x7F] */
+#define GPIO_OC_GP0_BYTE_ADDR 					(__GPIO_BASE + 0x80  )/* [0x80] */
+#define GPIO_OC_GP1_BYTE_ADDR 					(__GPIO_BASE + 0x81  )/* [0x81] */
+#define GPIO_OC_GP2_BYTE_ADDR					(__GPIO_BASE + 0x82  )/* [0x82] */
+#define GPIO_OC_GP4_VDOUT_7_0_BYTE_ADDR			(__GPIO_BASE + 0x84  )/* [0x84] */
+#define GPIO_OC_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0x85  )/* [0x85] */
+#define GPIO_OC_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0x86  )/* [0x86] */
+#define GPIO_OC_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0x87  )/* [0x87] */
+#define GPIO_OC_GP8_VDIN_BYTE_ADDR				(__GPIO_BASE + 0x88  )/* [0x88] */
+#define GPIO_OC_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0x89  )/* [0x89] */
+#define GPIO_OC_GP10_I2S_BYTE_ADDR				(__GPIO_BASE + 0x8A  )/* [0x8A] */
+#define GPIO_OC_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0x8B  )/* [0x8B] */
+#define GPIO_OC_GP12_SPI_BYTE_ADDR				(__GPIO_BASE + 0x8C  )/* [0x8C] */
+#define GPIO_OC_GP13_SD0_BYTE_ADDR   			(__GPIO_BASE + 0x8D  )/* [0x8D] */
+#define GPIO_OC_GP14_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x8E  )/* [0x8E] */
+#define GPIO_OC_GP15_NAND_BYTE_ADDR				(__GPIO_BASE + 0x8F  )/* [0x8F] */
+#define GPIO_OC_GP16_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0x90  )/* [0x90] */
+#define GPIO_OC_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0x91  )/* [0x91] */
+#define GPIO_OC_GP18_UART_BYTE_ADDR				(__GPIO_BASE + 0x92  )/* [0x92] */
+#define GPIO_OC_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0x93  )/* [0x93] */
+#define GPIO_OC_GP20_PWM0_BYTE_ADDR       		(__GPIO_BASE + 0x94  )/* [0x94] */
+#define GPIO_OC_GP21_HDMI_BYTE_ADDR       		(__GPIO_BASE + 0x95  )/* [0x95] */
+#define GPIO_OC_GP22_I2C3_BYTE_ADDR	     	  	(__GPIO_BASE + 0x96  )/* [0x96] */
+#define GPIO_OC_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0x98  )/* [0x98] */
+#define GPIO_OC_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0x9A  )/* [0x9A] */
+#define GPIO_OC_GP60_USB_BYTE_ADDR				(__GPIO_BASE + 0xBC  )/* [0xBC] */
+#define GPIO_OC_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0xBE  )/* [0xBE] */
+#define GPIO_OC_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0xBF  )/* [0xBF] */
+#define GPIO_OD_GP0_BYTE_ADDR 					(__GPIO_BASE + 0xC0  )/* [0xC0] */
+#define GPIO_OD_GP1_BYTE_ADDR 					(__GPIO_BASE + 0xC1  )/* [0xC1] */
+#define GPIO_OD_GP2_BYTE_ADDR					(__GPIO_BASE + 0xC2  )/* [0xC2] */
+#define GPIO_OD_GP4_VDOUT_7_0_BYTE_ADDR			(__GPIO_BASE + 0xC4  )/* [0xC4] */
+#define GPIO_OD_GP5_VDOUT_15_8_BYTE_ADDR		(__GPIO_BASE + 0xC5  )/* [0xC5] */
+#define GPIO_OD_GP6_VDOUT_23_16_BYTE_ADDR		(__GPIO_BASE + 0xC6  )/* [0xC6] */
+#define GPIO_OD_GP7_VD_BYTE_ADDR				(__GPIO_BASE + 0xC7  )/* [0xC7] */
+#define GPIO_OD_GP8_VDIN_BYTE_ADDR				(__GPIO_BASE + 0xC8  )/* [0xC8] */
+#define GPIO_OD_GP9_VSYNC_BYTE_ADDR 			(__GPIO_BASE + 0xC9  )/* [0xC9] */
+#define GPIO_OD_GP10_I2S_BYTE_ADDR				(__GPIO_BASE + 0xCA  )/* [0xCA] */
+#define GPIO_OD_GP11_I2S_BYTE_ADDR      		(__GPIO_BASE + 0xCB  )/* [0xCB] */
+#define GPIO_OD_GP12_SPI_BYTE_ADDR				(__GPIO_BASE + 0xCC  )/* [0xCC] */
+#define GPIO_OD_GP13_SD0_BYTE_ADDR   			(__GPIO_BASE + 0xCD  )/* [0xCD] */
+#define GPIO_OD_GP14_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0xCE  )/* [0xCE] */
+#define GPIO_OD_GP15_NAND_BYTE_ADDR				(__GPIO_BASE + 0xCF  )/* [0xCF] */
+#define GPIO_OD_GP16_NAND_SD1_BYTE_ADDR			(__GPIO_BASE + 0xD0  )/* [0xD0] */
+#define GPIO_OD_GP17_I2C_BYTE_ADDR       		(__GPIO_BASE + 0xD1  )/* [0xD1] */
+#define GPIO_OD_GP18_UART_BYTE_ADDR				(__GPIO_BASE + 0xD2  )/* [0xD2] */
+#define GPIO_OD_GP19_SD2_BYTE_ADDR   	    	(__GPIO_BASE + 0xD3  )/* [0xD3] */
+#define GPIO_OD_GP20_PWM0_BYTE_ADDR       		(__GPIO_BASE + 0xD4  )/* [0xD4] */
+#define GPIO_OD_GP21_HDMI_BYTE_ADDR       		(__GPIO_BASE + 0xD5  )/* [0xD5] */
+#define GPIO_OD_GP23_I2C3_BYTE_ADDR	       		(__GPIO_BASE + 0xD7  )/* [0xD7] */
+#define GPIO_OD_GP24_SF_BYTE_ADDR				(__GPIO_BASE + 0xD8  )/* [0xD8] */
+#define GPIO_OD_GP26_PCM_BYTE_ADDR       		(__GPIO_BASE + 0xDA  )/* [0xDA] */
+#define GPIO_OD_GP60_USB_BYTE_ADDR				(__GPIO_BASE + 0xFC  )/* [0xFC] */
+#define GPIO_OD_GP62_WAKEUP_SUS_BYTE_ADDR		(__GPIO_BASE + 0xFE  )/* [0xFE] */
+#define GPIO_OD_GP63_SD02CD_BYTE_ADDR			(__GPIO_BASE + 0xFF  )/* [0xFF] */
+#define STRAP_STATUS_ADDR					(__GPIO_BASE + 0x100  )/* [0x100 ~ 0x103] */
+#define AHB_CTRL_4BYTE_ADDR 				(__GPIO_BASE + 0x108  )/* [0x108 ~ 0x10B] */
+#define USB_OP_CTRL_4BYTE_ADDR				(__GPIO_BASE + 0x10C  )/* [0x10C ~ 0x10F] */
+#define BONDING_OPTION_4BYTE_ADDR			(__GPIO_BASE + 0x110  )/* [0x110 ~ 0x113] */
+#define PIN_SHARING_SEL_4BYTE_ADDR 			(__GPIO_BASE + 0x200  )/* [0x200 ~ 0x203] */
+#define TPIU_CLK_DATA_4BYTE_ADDR 			(__GPIO_BASE + 0x244  )/* [0x244 ~ 0x247] */
+#define GPIO0_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x300  )/* [0x300] */
+#define GPIO1_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x301  )/* [0x301] */
+#define GPIO2_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x302  )/* [0x302] */
+#define GPIO3_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x303  )/* [0x303] */
+#define GPIO4_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x304  )/* [0x304] */
+#define GPIO5_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x305  )/* [0x305] */
+#define GPIO6_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x306  )/* [0x306] */
+#define GPIO7_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x307  )/* [0x307] */
+#define GPIO8_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x308  )/* [0x308] */
+#define GPIO9_INT_REQ_TYPE_ADDR				(__GPIO_BASE + 0x309  )/* [0x309] */
+#define GPIO10_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30A  )/* [0x30A] */
+#define GPIO11_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30B  )/* [0x30B] */
+#define GPIO12_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30C  )/* [0x30C] */
+#define GPIO13_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30D  )/* [0x30D] */
+#define GPIO18_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30E  )/* [0x30E] */
+#define GPIO19_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x30F  )/* [0x30F] */
+#define VOUT20_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x310  )/* [0x310] */
+#define VOUT21_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x311  )/* [0x311] */
+#define VOUT22_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x312  )/* [0x312] */
+#define VOUT23_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x313  )/* [0x313] */
+#define GPIO20_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x314  )/* [0x314] */
+#define GPIO21_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x315  )/* [0x315] */
+#define GPIO22_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x316  )/* [0x316] */
+#define GPIO23_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x317  )/* [0x317] */
+#define GPIO24_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x318  )/* [0x318] */
+#define GPIO25_INT_REQ_TYPE_ADDR			(__GPIO_BASE + 0x319  )/* [0x319] */
+#define GPIO0_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x360  )/* [0x360] */
+#define GPIO1_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x361  )/* [0x361] */
+#define GPIO2_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x362  )/* [0x362] */
+#define GPIO3_INT_REQ_STS_ADDR				(__GPIO_BASE + 0x363  )/* [0x363] */
+#define DRV_DVO_CLK_BYTE_ADDR				(__GPIO_BASE + 0x402  )/* [0x402] */
+#define DRV_DVO_VDEN_BYTE_ADDR				(__GPIO_BASE + 0x403  )/* [0x403] */
+#define SD0_DPCTL_4BYTE_ADDR				(__GPIO_BASE + 0x404  )/* [0x404 ~ 0x407] */
+#define SD0_DNCTL_4BYTE_ADDR				(__GPIO_BASE + 0x408  )/* [0x408 ~ 0x40B] */
+#define DRV_SD0_USB_BYTE_ADDR				(__GPIO_BASE + 0x464  )/* [0x464] */	
+#define DRV_USB_SWOC0_BYTE_ADDR				(__GPIO_BASE + 0x465  )/* [0x465] */	
+#define DRV_USB_OC12_BYTE_ADDR				(__GPIO_BASE + 0x466  )/* [0x466] */
+#define DRV_USBOC3_CIR_BYTE_ADDR			(__GPIO_BASE + 0x467  )/* [0x467] */
+#define DRV_PWREN_BYTE_ADDR					(__GPIO_BASE + 0x468  )/* [0x468] */
+#define DRV_PWREN_WAKEUP0_BYTE_ADDR			(__GPIO_BASE + 0x469  )/* [0x469] */
+#define DRV_SUSGP01_BYTE_ADDR				(__GPIO_BASE + 0x46A  )/* [0x46A] */
+#define DRV_WAKEUP23_BYTE_ADDR				(__GPIO_BASE + 0x46B  )/* [0x46B] */
+#define DRV_WAKEUP45_BYTE_ADDR				(__GPIO_BASE + 0x46C  )/* [0x46C] */
+#define DRV_I2C_BYTE_ADDR					(__GPIO_BASE + 0x46D  )/* [0x46D] */
+#define DRV_HDMI_BYTE_ADDR					(__GPIO_BASE + 0x46E  )/* [0x46E] */	
+#define PULL_EN_GP0_BYTE_ADDR				(__GPIO_BASE + 0x480  )/* [0x480] */
+#define PULL_EN_GP1_BYTE_ADDR				(__GPIO_BASE + 0x481  )/* [0x481] */
+#define PULL_EN_GP2_BYTE_ADDR				(__GPIO_BASE + 0x482  )/* [0x482] */
+#define PULL_EN_GP4_VDOUT_7_0_BYTE_ADDR		(__GPIO_BASE + 0x484  )/* [0x484] */
+#define PULL_EN_GP5_VDOUT_15_8_BYTE_ADDR	(__GPIO_BASE + 0x485  )/* [0x485] */
+#define PULL_EN_GP6_VDOUT_23_16_BYTE_ADDR	(__GPIO_BASE + 0x486  )/* [0x486] */
+#define PULL_EN_GP7_VD_BYTE_ADDR     		(__GPIO_BASE + 0x487  )/* [0x487] */
+#define PULL_EN_GP8_VDIN_BYTE_ADDR   		(__GPIO_BASE + 0x488  )/* [0x488] */
+#define PULL_EN_GP9_VSYNC_BYTE_ADDR 		(__GPIO_BASE + 0x489  )/* [0x489] */
+#define PULL_EN_GP10_I2S_BYTE_ADDR 			(__GPIO_BASE + 0x48A  )/* [0x48A] */
+#define PULL_EN_GP11_I2S_BYTE_ADDR     		(__GPIO_BASE + 0x48B  )/* [0x48B] */
+#define PULL_EN_GP12_SPI_BYTE_ADDR			(__GPIO_BASE + 0x48C  )/* [0x48C] */
+#define PULL_EN_GP13_SD0_BYTE_ADDR       	(__GPIO_BASE + 0x48D  )/* [0x48D] */
+#define PULL_EN_GP14_NAND_BYTE_ADDR      	(__GPIO_BASE + 0x48E  )/* [0x48E] */
+#define PULL_EN_GP15_NAND_BYTE_ADDR			(__GPIO_BASE + 0x48F  )/* [0x48F] */
+#define PULL_EN_GP16_NANDIO_BYTE_ADDR		(__GPIO_BASE + 0x490  )/* [0x490] */
+#define PULL_EN_GP17_I2C_BYTE_ADDR			(__GPIO_BASE + 0x491  )/* [0x491] */
+#define PULL_EN_GP18_UART_BYTE_ADDR			(__GPIO_BASE + 0x492  )/* [0x492] */
+#define PULL_EN_GP19_SD2_BYTE_ADDR			(__GPIO_BASE + 0x493  )/* [0x493] */
+#define PULL_EN_GP20_PWM0_BYTE_ADDR			(__GPIO_BASE + 0x494  )/* [0x494] */
+#define PULL_EN_GP21_HDMI_BYTE_ADDR      	(__GPIO_BASE + 0x495  )/* [0x495] */
+#define PULL_EN_GP23_I2C3_BYTE_ADDR			(__GPIO_BASE + 0x497  )/* [0x497] */
+#define PULL_EN_GP24_SF_BYTE_ADDR			(__GPIO_BASE + 0x498  )/* [0x498] */
+#define PULL_EN_GP26_PCM_BYTE_ADDR			(__GPIO_BASE + 0x49A  )/* [0x49A] */
+#define PULL_EN_GP60_USB_BYTE_ADDR			(__GPIO_BASE + 0x4BC  )/* [0x4BC] */
+#define PULL_EN_GP62_WAKEUP_SUS_BYTE_ADDR	(__GPIO_BASE + 0x4BE  )/* [0x4BE] */
+#define PULL_EN_GP63_SD02_BYTE_ADDR			(__GPIO_BASE + 0x4BF  )/* [0x4BF] */
+#define PULL_CTRL_GP0_BYTE_ADDR				(__GPIO_BASE + 0x4C0  )/* [0x4C0] */
+#define PULL_CTRL_GP1_BYTE_ADDR				(__GPIO_BASE + 0x4C1  )/* [0x4C1] */
+#define PULL_CTRL_GP2_BYTE_ADDR				(__GPIO_BASE + 0x4C2  )/* [0x4C2] */
+#define PULL_CTRL_GP4_VDOUT_7_0_BYTE_ADDR	(__GPIO_BASE + 0x4C4  )/* [0x4C4] */
+#define PULL_CTRL_GP5_VDOUT_15_8_BYTE_ADDR	(__GPIO_BASE + 0x4C5  )/* [0x4C5] */
+#define PULL_CTRL_GP6_VDOUT_23_16_BYTE_ADDR	(__GPIO_BASE + 0x4C6  )/* [0x4C6] */
+#define PULL_CTRL_GP7_VD_BYTE_ADDR			(__GPIO_BASE + 0x4C7  )/* [0x4C7] */
+#define PULL_CTRL_GP8_VDIN_BYTE_ADDR		(__GPIO_BASE + 0x4C8  )/* [0x4C8] */
+#define PULL_CTRL_GP9_VSYNC_BYTE_ADDR		(__GPIO_BASE + 0x4C9  )/* [0x4C9] */
+#define PULL_CTRL_GP10_I2S_BYTE_ADDR		(__GPIO_BASE + 0x4CA  )/* [0x4CA] */
+#define PULL_CTRL_GP11_I2S_BYTE_ADDR		(__GPIO_BASE + 0x4CB  )/* [0x4CB] */
+#define PULL_CTRL_GP12_SPI_BYTE_ADDR		(__GPIO_BASE + 0x4CC  )/* [0x4CC] */
+#define PULL_CTRL_GP13_SD0_BYTE_ADDR		(__GPIO_BASE + 0x4CD  )/* [0x4CD] */
+#define PULL_CTRL_GP14_NAND_BYTE_ADDR       (__GPIO_BASE + 0x4CE  )/* [0x4CE] */
+#define PULL_CTRL_GP15_NAND_BYTE_ADDR		(__GPIO_BASE + 0x4CF  )/* [0x4CF] */
+#define PULL_CTRL_GP16_NANDIO_BYTE_ADDR		(__GPIO_BASE + 0x4D0  )/* [0x4D0] */
+#define PULL_CTRL_GP17_I2C_BYTE_ADDR     	(__GPIO_BASE + 0x4D1  )/* [0x4D1] */
+#define PULL_CTRL_GP18_UART_BYTE_ADDR     	(__GPIO_BASE + 0x4D2  )/* [0x4D2] */
+#define PULL_CTRL_GP19_SD2_BYTE_ADDR     	(__GPIO_BASE + 0x4D3  )/* [0x4D3] */
+#define PULL_CTRL_GP20_PWM0_BYTE_ADDR      	(__GPIO_BASE + 0x4D4  )/* [0x4D4] */
+#define PULL_CTRL_GP21_HDMI_BYTE_ADDR		(__GPIO_BASE + 0x4D5  )/* [0x4D5] */
+#define PULL_CTRL_GP23_I2C3_BYTE_ADDR		(__GPIO_BASE + 0x4D7  )/* [0x4D7] */
+#define PULL_CTRL_GP24_SF_BYTE_ADDR     	(__GPIO_BASE + 0x4D8  )/* [0x4D8] */
+#define PULL_CTRL_GP26_PCM_BYTE_ADDR		(__GPIO_BASE + 0x4DA  )/* [0x4DA] */
+#define PULL_CTRL_GP27_SD0_BYTE_ADDR		(__GPIO_BASE + 0x4DB  )/* [0x4DB] */
+#define PULL_CTRL_GP60_USB_BYTE_ADDR		(__GPIO_BASE + 0x4FC  )/* [0x4FC] */
+#define PULL_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR	(__GPIO_BASE + 0x4FE  )/* [0x4FE] */
+#define PULL_CTRL_GP63_SD02_BYTE_ADDR		(__GPIO_BASE + 0x4FF  )/* [0x4FF] */
+#define DRV_GPIO_7_0_4BYTE_ADDR				(__GPIO_BASE + 0x800  )/* [0x800 ~ 0x803] */
+#define DRV_GPIO_13_8_4BYTE_ADDR			(__GPIO_BASE + 0x804  )/* [0x804 ~ 0x807] */
+#define DRV_GPIO_19_14_4BYTE_ADDR			(__GPIO_BASE + 0x808  )/* [0x808 ~ 0x80B] */
+#define DRV_VDIN_3_0_4BYTE_ADDR				(__GPIO_BASE + 0x80C  )/* [0x80C ~ 0x80F] */
+#define DRV_VDIN_4_6_4BYTE_ADDR				(__GPIO_BASE + 0x810  )/* [0x810 ~ 0x813] */
+#define DRV_VDIN_SPI_4BYTE_ADDR				(__GPIO_BASE + 0x814  )/* [0x814 ~ 0x817] */
+#define DRV_SPI_NAND_4BYTE_ADDR				(__GPIO_BASE + 0x818  )/* [0x818 ~ 0x81B] */
+#define DRV_NAND_4BYTE_ADDR					(__GPIO_BASE + 0x81C  )/* [0x81C ~ 0x81F] */
+#define DRV_NANDIO_4BYTE_ADDR				(__GPIO_BASE + 0x820  )/* [0x820 ~ 0x823] */
+#define DRV_HDMI_I2C_4BYTE_ADDR				(__GPIO_BASE + 0x824  )/* [0x824 ~ 0x827] */
+#define DRV_I2C_SD0_4BYTE_ADDR				(__GPIO_BASE + 0x828  )/* [0x828 ~ 0x82B] */
+#define DRV_SD0_SD2_4BYTE_ADDR				(__GPIO_BASE + 0x82C  )/* [0x82C ~ 0x82F] */
+#define DRV_SD2_I2S_4BYTE_ADDR				(__GPIO_BASE + 0x830  )/* [0x830 ~ 0x833] */
+#define DRV_I2S_UART_4BYTE_ADDR				(__GPIO_BASE + 0x834  )/* [0x834 ~ 0x837] */
+#define DRV_UART_4BYTE_ADDR					(__GPIO_BASE + 0x838  )/* [0x838 ~ 0x83B] */
+#define DRV_SF_JTAGT_4BYTE_ADDR				(__GPIO_BASE + 0x83C  )/* [0x83C ~ 0x83F] */
+#define DRV_JTAGT_PWM_4BYTE_ADDR			(__GPIO_BASE + 0x840  )/* [0x840 ~ 0x843] */
+#define DRV_PCM_BYTE_ADDR					(__GPIO_BASE + 0x844  )/* [0x844] */
+#define DRV_SPI_BYTE_ADDR					(__GPIO_BASE + 0x84C  )/* [0x84C] */
+
+
+
+#define GPIO_ID_GP0_BYTE_REG					REG8_PTR(GPIO_ID_GP0_BYTE_ADDR )
+#define GPIO_ID_GP1_BYTE_REG 					REG8_PTR(GPIO_ID_GP1_BYTE_ADDR )
+#define GPIO_ID_GP2_BYTE_REG					REG8_PTR(GPIO_ID_GP2_BYTE_ADDR )
+#define GPIO_ID_GP4_VDOUT_7_0_BYTE_REG			REG8_PTR(GPIO_ID_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_ID_GP5_VDOUT_15_8_BYTE_REG			REG8_PTR(GPIO_ID_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_ID_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_ID_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_ID_GP7_VD_BYTE_REG					REG8_PTR(GPIO_ID_GP7_VD_BYTE_ADDR )
+#define GPIO_ID_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_ID_GP8_VDIN_BYTE_ADDR )
+#define GPIO_ID_GP9_VSYNC_BYTE_REG				REG8_PTR(GPIO_ID_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_ID_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_ID_GP10_I2S_BYTE_ADDR )
+#define GPIO_ID_GP11_I2S_BYTE_REG				REG8_PTR(GPIO_ID_GP11_I2S_BYTE_ADDR )
+#define GPIO_ID_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_ID_GP12_SPI_BYTE_ADDR )
+#define GPIO_ID_GP13_SD0_BYTE_REG   		REG8_PTR(GPIO_ID_GP13_SD0_BYTE_ADDR )
+#define GPIO_ID_GP14_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_ID_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_ID_GP15_NAND_BYTE_REG				REG8_PTR(GPIO_ID_GP15_NAND_BYTE_ADDR )
+#define GPIO_ID_GP16_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_ID_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_ID_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_ID_GP17_I2C_BYTE_ADDR )
+#define GPIO_ID_GP18_UART_BYTE_REG				REG8_PTR(GPIO_ID_GP18_UART_BYTE_ADDR )
+#define GPIO_ID_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_ID_GP19_SD2_BYTE_ADDR )
+#define GPIO_ID_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_ID_GP20_PWM0_BYTE_ADDR )
+#define GPIO_ID_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_ID_GP21_HDMI_BYTE_ADDR )
+#define GPIO_ID_GP23_I2C3_BYTE_REG	    	   	REG8_PTR(GPIO_ID_GP23_I2C3_BYTE_ADDR )
+#define GPIO_ID_GP24_SF_BYTE_REG				REG8_PTR(GPIO_ID_GP24_SF_BYTE_ADDR )
+#define GPIO_ID_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_ID_GP26_PCM_BYTE_ADDR )
+#define GPIO_ID_GP60_USB_BYTE_REG				REG8_PTR(GPIO_ID_GP60_USB_BYTE_ADDR )
+#define GPIO_ID_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_ID_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_ID_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_ID_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_CTRL_GP0_BYTE_REG 					REG8_PTR(GPIO_CTRL_GP0_BYTE_ADDR )
+#define GPIO_CTRL_GP1_BYTE_REG 					REG8_PTR(GPIO_CTRL_GP1_BYTE_ADDR )
+#define GPIO_CTRL_GP2_BYTE_REG 					REG8_PTR(GPIO_CTRL_GP2_BYTE_ADDR )
+#define GPIO_CTRL_GP4_VDOUT_7_0_BYTE_REG		REG8_PTR(GPIO_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_CTRL_GP5_VDOUT_15_8_BYTE_REG		REG8_PTR(GPIO_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_CTRL_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_CTRL_GP7_VD_BYTE_REG				REG8_PTR(GPIO_CTRL_GP7_VD_BYTE_ADDR )
+#define GPIO_CTRL_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_CTRL_GP8_VDIN_BYTE_ADDR )
+#define GPIO_CTRL_GP9_VSYNC_BYTE_REG 			REG8_PTR(GPIO_CTRL_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_CTRL_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_CTRL_GP10_I2S_BYTE_ADDR )
+#define GPIO_CTRL_GP11_I2S_BYTE_REG      		REG8_PTR(GPIO_CTRL_GP11_I2S_BYTE_ADDR )
+#define GPIO_CTRL_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_CTRL_GP12_SPI_BYTE_ADDR )
+#define GPIO_CTRL_GP13_SD0_BYTE_REG       	REG8_PTR(GPIO_CTRL_GP13_SD0_BYTE_ADDR )
+#define GPIO_CTRL_GP14_NAND_SD1_BYTE_REG		REG8_PTR(GPIO_CTRL_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_CTRL_GP15_NAND_BYTE_REG			REG8_PTR(GPIO_CTRL_GP15_NAND_BYTE_ADDR )
+#define GPIO_CTRL_GP16_NAND_SD1_BYTE_REG		REG8_PTR(GPIO_CTRL_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_CTRL_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP17_I2C_BYTE_ADDR )
+#define GPIO_CTRL_GP18_UART_BYTE_REG			REG8_PTR(GPIO_CTRL_GP18_UART_BYTE_ADDR )
+#define GPIO_CTRL_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_CTRL_GP19_SD2_BYTE_ADDR )
+#define GPIO_CTRL_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP20_PWM0_BYTE_ADDR )
+#define GPIO_CTRL_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP21_HDMI_BYTE_ADDR )
+#define GPIO_CTRL_GP23_I2C3_BYTE_REG	    	REG8_PTR(GPIO_CTRL_GP23_I2C3_BYTE_ADDR )
+#define GPIO_CTRL_GP24_SF_BYTE_REG				REG8_PTR(GPIO_CTRL_GP24_SF_BYTE_ADDR )
+#define GPIO_CTRL_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_CTRL_GP26_PCM_BYTE_ADDR )
+#define GPIO_CTRL_GP60_USB_BYTE_REG				REG8_PTR(GPIO_CTRL_GP60_USB_BYTE_ADDR )
+#define GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_CTRL_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_CTRL_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_OC_GP0_BYTE_REG 					REG8_PTR(GPIO_OC_GP0_BYTE_ADDR )
+#define GPIO_OC_GP1_BYTE_REG 					REG8_PTR(GPIO_OC_GP1_BYTE_ADDR )
+#define GPIO_OC_GP2_BYTE_REG					REG8_PTR(GPIO_OC_GP2_BYTE_ADDR )
+#define GPIO_OC_GP4_VDOUT_7_0_BYTE_REG			REG8_PTR(GPIO_OC_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_OC_GP5_VDOUT_15_8_BYTE_REG			REG8_PTR(GPIO_OC_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_OC_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_OC_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_OC_GP7_VD_BYTE_REG					REG8_PTR(GPIO_OC_GP7_VD_BYTE_ADDR )
+#define GPIO_OC_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_OC_GP8_VDIN_BYTE_ADDR )
+#define GPIO_OC_GP9_VSYNC_BYTE_REG 				REG8_PTR(GPIO_OC_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_OC_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_OC_GP10_I2S_BYTE_ADDR )
+#define GPIO_OC_GP11_I2S_BYTE_REG      			REG8_PTR(GPIO_OC_GP11_I2S_BYTE_ADDR )
+#define GPIO_OC_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_OC_GP12_SPI_BYTE_ADDR )
+#define GPIO_OC_GP13_SD0_BYTE_REG   		REG8_PTR(GPIO_OC_GP13_SD0_BYTE_ADDR )
+#define GPIO_OC_GP14_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OC_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_OC_GP15_NAND_BYTE_REG				REG8_PTR(GPIO_OC_GP15_NAND_BYTE_ADDR )
+#define GPIO_OC_GP16_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OC_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_OC_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_OC_GP17_I2C_BYTE_ADDR )
+#define GPIO_OC_GP18_UART_BYTE_REG				REG8_PTR(GPIO_OC_GP18_UART_BYTE_ADDR )
+#define GPIO_OC_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_OC_GP19_SD2_BYTE_ADDR )
+#define GPIO_OC_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_OC_GP20_PWM0_BYTE_ADDR )
+#define GPIO_OC_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_OC_GP21_HDMI_BYTE_ADDR )
+#define GPIO_OC_GP22_I2C3_BYTE_REG	     	  	REG8_PTR(GPIO_OC_GP22_I2C3_BYTE_ADDR )
+#define GPIO_OC_GP24_SF_BYTE_REG				REG8_PTR(GPIO_OC_GP24_SF_BYTE_ADDR )
+#define GPIO_OC_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_OC_GP26_PCM_BYTE_ADDR )
+#define GPIO_OC_GP60_USB_BYTE_REG				REG8_PTR(GPIO_OC_GP60_USB_BYTE_ADDR )
+#define GPIO_OC_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_OC_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_OC_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_OC_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_OD_GP0_BYTE_REG 					REG8_PTR(GPIO_OD_GP0_BYTE_ADDR )
+#define GPIO_OD_GP1_BYTE_REG 					REG8_PTR(GPIO_OD_GP1_BYTE_ADDR )
+#define GPIO_OD_GP2_BYTE_REG					REG8_PTR(GPIO_OD_GP2_BYTE_ADDR )
+#define GPIO_OD_GP4_VDOUT_7_0_BYTE_REG			REG8_PTR(GPIO_OD_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_OD_GP5_VDOUT_15_8_BYTE_REG			REG8_PTR(GPIO_OD_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_OD_GP6_VDOUT_23_16_BYTE_REG		REG8_PTR(GPIO_OD_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_OD_GP7_VD_BYTE_REG					REG8_PTR(GPIO_OD_GP7_VD_BYTE_ADDR )
+#define GPIO_OD_GP8_VDIN_BYTE_REG				REG8_PTR(GPIO_OD_GP8_VDIN_BYTE_ADDR )
+#define GPIO_OD_GP9_VSYNC_BYTE_REG 				REG8_PTR(GPIO_OD_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_OD_GP10_I2S_BYTE_REG				REG8_PTR(GPIO_OD_GP10_I2S_BYTE_ADDR )
+#define GPIO_OD_GP11_I2S_BYTE_REG      			REG8_PTR(GPIO_OD_GP11_I2S_BYTE_ADDR )
+#define GPIO_OD_GP12_SPI_BYTE_REG				REG8_PTR(GPIO_OD_GP12_SPI_BYTE_ADDR )
+#define GPIO_OD_GP13_SD0_BYTE_REG   		REG8_PTR(GPIO_OD_GP13_SD0_BYTE_ADDR )
+#define GPIO_OD_GP14_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OD_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_OD_GP15_NAND_BYTE_REG				REG8_PTR(GPIO_OD_GP15_NAND_BYTE_ADDR )
+#define GPIO_OD_GP16_NAND_SD1_BYTE_REG			REG8_PTR(GPIO_OD_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_OD_GP17_I2C_BYTE_REG       		REG8_PTR(GPIO_OD_GP17_I2C_BYTE_ADDR )
+#define GPIO_OD_GP18_UART_BYTE_REG				REG8_PTR(GPIO_OD_GP18_UART_BYTE_ADDR )
+#define GPIO_OD_GP19_SD2_BYTE_REG   	    	REG8_PTR(GPIO_OD_GP19_SD2_BYTE_ADDR )
+#define GPIO_OD_GP20_PWM0_BYTE_REG       		REG8_PTR(GPIO_OD_GP20_PWM0_BYTE_ADDR )
+#define GPIO_OD_GP21_HDMI_BYTE_REG       		REG8_PTR(GPIO_OD_GP21_HDMI_BYTE_ADDR )
+#define GPIO_OD_GP23_I2C3_BYTE_REG	       		REG8_PTR(GPIO_OD_GP23_I2C3_BYTE_ADDR )
+#define GPIO_OD_GP24_SF_BYTE_REG				REG8_PTR(GPIO_OD_GP24_SF_BYTE_ADDR )
+#define GPIO_OD_GP26_PCM_BYTE_REG       		REG8_PTR(GPIO_OD_GP26_PCM_BYTE_ADDR )
+#define GPIO_OD_GP60_USB_BYTE_REG				REG8_PTR(GPIO_OD_GP60_USB_BYTE_ADDR )
+#define GPIO_OD_GP62_WAKEUP_SUS_BYTE_REG		REG8_PTR(GPIO_OD_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_OD_GP63_SD02CD_BYTE_REG			REG8_PTR(GPIO_OD_GP63_SD02CD_BYTE_ADDR )
+#define STRAP_STATUS_REG					REG32_PTR(STRAP_STATUS_ADDR )
+#define AHB_CTRL_4BYTE_REG 					REG32_PTR(AHB_CTRL_4BYTE_ADDR )
+#define USB_OP_CTRL_4BYTE_REG				REG32_PTR(USB_OP_CTRL_4BYTE_ADDR )
+#define BONDING_OPTION_4BYTE_REG			REG32_PTR(BONDING_OPTION_4BYTE_ADDR )
+#define PIN_SHARING_SEL_4BYTE_REG 			REG32_PTR(PIN_SHARING_SEL_4BYTE_ADDR )
+#define TPIU_CLK_DATA_4BYTE_REG 			REG32_PTR(TPIU_CLK_DATA_4BYTE_ADDR )
+#define GPIO0_INT_REQ_TYPE_REG				REG8_PTR(GPIO0_INT_REQ_TYPE_ADDR )
+#define GPIO1_INT_REQ_TYPE_REG				REG8_PTR(GPIO1_INT_REQ_TYPE_ADDR )
+#define GPIO2_INT_REQ_TYPE_REG				REG8_PTR(GPIO2_INT_REQ_TYPE_ADDR )
+#define GPIO3_INT_REQ_TYPE_REG				REG8_PTR(GPIO3_INT_REQ_TYPE_ADDR )
+#define GPIO4_INT_REQ_TYPE_REG				REG8_PTR(GPIO4_INT_REQ_TYPE_ADDR )
+#define GPIO5_INT_REQ_TYPE_REG				REG8_PTR(GPIO5_INT_REQ_TYPE_ADDR )
+#define GPIO6_INT_REQ_TYPE_REG				REG8_PTR(GPIO6_INT_REQ_TYPE_ADDR )
+#define GPIO7_INT_REQ_TYPE_REG				REG8_PTR(GPIO7_INT_REQ_TYPE_ADDR )
+#define GPIO8_INT_REQ_TYPE_REG				REG8_PTR(GPIO8_INT_REQ_TYPE_ADDR )
+#define GPIO9_INT_REQ_TYPE_REG				REG8_PTR(GPIO9_INT_REQ_TYPE_ADDR )
+#define GPIO10_INT_REQ_TYPE_REG				REG8_PTR(GPIO10_INT_REQ_TYPE_ADDR )
+#define GPIO11_INT_REQ_TYPE_REG				REG8_PTR(GPIO11_INT_REQ_TYPE_ADDR )
+#define GPIO12_INT_REQ_TYPE_REG				REG8_PTR(GPIO12_INT_REQ_TYPE_ADDR )
+#define GPIO13_INT_REQ_TYPE_REG				REG8_PTR(GPIO13_INT_REQ_TYPE_ADDR )
+#define GPIO18_INT_REQ_TYPE_REG				REG8_PTR(GPIO18_INT_REQ_TYPE_ADDR )
+#define GPIO19_INT_REQ_TYPE_REG				REG8_PTR(GPIO19_INT_REQ_TYPE_ADDR )
+#define VOUT20_INT_REQ_TYPE_REG				REG8_PTR(VOUT20_INT_REQ_TYPE_ADDR )
+#define VOUT21_INT_REQ_TYPE_REG				REG8_PTR(VOUT21_INT_REQ_TYPE_ADDR )
+#define VOUT22_INT_REQ_TYPE_REG				REG8_PTR(VOUT22_INT_REQ_TYPE_ADDR )
+#define VOUT23_INT_REQ_TYPE_REG				REG8_PTR(VOUT23_INT_REQ_TYPE_ADDR )
+#define GPIO20_INT_REQ_TYPE_REG				REG8_PTR(GPIO20_INT_REQ_TYPE_ADDR )
+#define GPIO21_INT_REQ_TYPE_REG				REG8_PTR(GPIO21_INT_REQ_TYPE_ADDR )
+#define GPIO22_INT_REQ_TYPE_REG				REG8_PTR(GPIO22_INT_REQ_TYPE_ADDR )
+#define GPIO23_INT_REQ_TYPE_REG				REG8_PTR(GPIO23_INT_REQ_TYPE_ADDR )
+#define GPIO24_INT_REQ_TYPE_REG				REG8_PTR(GPIO24_INT_REQ_TYPE_ADDR )
+#define GPIO25_INT_REQ_TYPE_REG				REG8_PTR(GPIO25_INT_REQ_TYPE_ADDR )
+#define GPIO0_INT_REQ_STS_REG				REG8_PTR(GPIO0_INT_REQ_STS_ADDR )
+#define GPIO1_INT_REQ_STS_REG				REG8_PTR(GPIO1_INT_REQ_STS_ADDR )
+#define GPIO2_INT_REQ_STS_REG				REG8_PTR(GPIO2_INT_REQ_STS_ADDR )
+#define GPIO3_INT_REQ_STS_REG				REG8_PTR(GPIO3_INT_REQ_STS_ADDR )
+#define DRV_DVO_CLK_BYTE_REG				REG8_PTR(DRV_DVO_CLK_BYTE_ADDR )
+#define DRV_DVO_VDEN_BYTE_REG				REG8_PTR(DRV_DVO_VDEN_BYTE_ADDR )
+#define SD0_DPCTL_4BYTE_REG					REG32_PTR(SD0_DPCTL_4BYTE_ADDR )
+#define SD0_DNCTL_4BYTE_REG					REG32_PTR(SD0_DNCTL_4BYTE_ADDR )
+#define DRV_SD0_USB_BYTE_REG				REG8_PTR(DRV_SD0_USB_BYTE_ADDR )	
+#define DRV_USB_SWOC0_BYTE_REG				REG8_PTR(DRV_USB_SWOC0_BYTE_ADDR )
+#define DRV_USB_OC12_BYTE_REG				REG8_PTR(DRV_USB_OC12_BYTE_ADDR )
+#define DRV_USBOC3_CIR_BYTE_REG				REG8_PTR(DRV_USBOC3_CIR_BYTE_ADDR )
+#define DRV_PWREN_BYTE_REG					REG8_PTR(DRV_PWREN_BYTE_ADDR )
+#define DRV_PWREN_WAKEUP0_BYTE_REG			REG8_PTR(DRV_PWREN_WAKEUP0_BYTE_ADDR )
+#define DRV_SUSGP01_BYTE_REG				REG8_PTR(DRV_SUSGP01_BYTE_ADDR )
+#define DRV_WAKEUP23_BYTE_REG				REG8_PTR(DRV_WAKEUP23_BYTE_ADDR )
+#define DRV_WAKEUP45_BYTE_REG				REG8_PTR(DRV_WAKEUP45_BYTE_ADDR )
+#define DRV_I2C_BYTE_REG					REG8_PTR(DRV_I2C_BYTE_ADDR )
+#define DRV_HDMI_BYTE_REG					REG8_PTR(DRV_HDMI_BYTE_ADDR )	
+#define PULL_EN_GP0_BYTE_REG				REG8_PTR(PULL_EN_GP0_BYTE_ADDR )
+#define PULL_EN_GP1_BYTE_REG				REG8_PTR(PULL_EN_GP1_BYTE_ADDR )
+#define PULL_EN_GP2_BYTE_REG				REG8_PTR(PULL_EN_GP2_BYTE_ADDR )
+#define PULL_EN_GP4_VDOUT_7_0_BYTE_REG		REG8_PTR(PULL_EN_GP4_VDOUT_7_0_BYTE_ADDR )
+#define PULL_EN_GP5_VDOUT_15_8_BYTE_REG		REG8_PTR(PULL_EN_GP5_VDOUT_15_8_BYTE_ADDR )
+#define PULL_EN_GP6_VDOUT_23_16_BYTE_REG	REG8_PTR(PULL_EN_GP6_VDOUT_23_16_BYTE_ADDR )
+#define PULL_EN_GP7_VD_BYTE_REG     		REG8_PTR(PULL_EN_GP7_VD_BYTE_ADDR )
+#define PULL_EN_GP8_VDIN_BYTE_REG   		REG8_PTR(PULL_EN_GP8_VDIN_BYTE_ADDR )
+#define PULL_EN_GP9_VSYNC_BYTE_REG 			REG8_PTR(PULL_EN_GP9_VSYNC_BYTE_ADDR )
+#define PULL_EN_GP10_I2S_BYTE_REG 			REG8_PTR(PULL_EN_GP10_I2S_BYTE_ADDR )
+#define PULL_EN_GP11_I2S_BYTE_REG     		REG8_PTR(PULL_EN_GP11_I2S_BYTE_ADDR )
+#define PULL_EN_GP12_SPI_BYTE_REG			REG8_PTR(PULL_EN_GP12_SPI_BYTE_ADDR )
+#define PULL_EN_GP13_SD0_BYTE_REG       	REG8_PTR(PULL_EN_GP13_SD0_BYTE_ADDR )
+#define PULL_EN_GP14_NAND_BYTE_REG      	REG8_PTR(PULL_EN_GP14_NAND_BYTE_ADDR )
+#define PULL_EN_GP15_NAND_BYTE_REG			REG8_PTR(PULL_EN_GP15_NAND_BYTE_ADDR )
+#define PULL_EN_GP16_NANDIO_BYTE_REG		REG8_PTR(PULL_EN_GP16_NANDIO_BYTE_ADDR )
+#define PULL_EN_GP17_I2C_BYTE_REG			REG8_PTR(PULL_EN_GP17_I2C_BYTE_ADDR )
+#define PULL_EN_GP18_UART_BYTE_REG			REG8_PTR(PULL_EN_GP18_UART_BYTE_ADDR )
+#define PULL_EN_GP19_SD2_BYTE_REG			REG8_PTR(PULL_EN_GP19_SD2_BYTE_ADDR )
+#define PULL_EN_GP20_PWM0_BYTE_REG			REG8_PTR(PULL_EN_GP20_PWM0_BYTE_ADDR )
+#define PULL_EN_GP21_HDMI_BYTE_REG      	REG8_PTR(PULL_EN_GP21_HDMI_BYTE_ADDR )
+#define PULL_EN_GP23_I2C3_BYTE_REG			REG8_PTR(PULL_EN_GP23_I2C3_BYTE_ADDR )
+#define PULL_EN_GP24_SF_BYTE_REG			REG8_PTR(PULL_EN_GP24_SF_BYTE_ADDR )
+#define PULL_EN_GP26_PCM_BYTE_REG			REG8_PTR(PULL_EN_GP26_PCM_BYTE_ADDR )
+#define PULL_EN_GP60_USB_BYTE_REG			REG8_PTR(PULL_EN_GP60_USB_BYTE_ADDR )
+#define PULL_EN_GP62_WAKEUP_SUS_BYTE_REG	REG8_PTR(PULL_EN_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define PULL_EN_GP63_SD02_BYTE_REG			REG8_PTR(PULL_EN_GP63_SD02_BYTE_ADDR )
+#define PULL_CTRL_GP0_BYTE_REG				REG8_PTR(PULL_CTRL_GP0_BYTE_ADDR )
+#define PULL_CTRL_GP1_BYTE_REG				REG8_PTR(PULL_CTRL_GP1_BYTE_ADDR )
+#define PULL_CTRL_GP2_BYTE_REG				REG8_PTR(PULL_CTRL_GP2_BYTE_ADDR )
+#define PULL_CTRL_GP4_VDOUT_7_0_BYTE_REG	REG8_PTR(PULL_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
+#define PULL_CTRL_GP5_VDOUT_15_8_BYTE_REG	REG8_PTR(PULL_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
+#define PULL_CTRL_GP6_VDOUT_23_16_BYTE_REG	REG8_PTR(PULL_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
+#define PULL_CTRL_GP7_VD_BYTE_REG			REG8_PTR(PULL_CTRL_GP7_VD_BYTE_ADDR )
+#define PULL_CTRL_GP8_VDIN_BYTE_REG			REG8_PTR(PULL_CTRL_GP8_VDIN_BYTE_ADDR )
+#define PULL_CTRL_GP9_VSYNC_BYTE_REG		REG8_PTR(PULL_CTRL_GP9_VSYNC_BYTE_ADDR )
+#define PULL_CTRL_GP10_I2S_BYTE_REG			REG8_PTR(PULL_CTRL_GP10_I2S_BYTE_ADDR )
+#define PULL_CTRL_GP11_I2S_BYTE_REG			REG8_PTR(PULL_CTRL_GP11_I2S_BYTE_ADDR )
+#define PULL_CTRL_GP12_SPI_BYTE_REG			REG8_PTR(PULL_CTRL_GP12_SPI_BYTE_ADDR )
+#define PULL_CTRL_GP13_SD0_BYTE_REG			REG8_PTR(PULL_CTRL_GP13_SD0_BYTE_ADDR )
+#define PULL_CTRL_GP14_NAND_BYTE_REG       	REG8_PTR(PULL_CTRL_GP14_NAND_BYTE_ADDR )
+#define PULL_CTRL_GP15_NAND_BYTE_REG		REG8_PTR(PULL_CTRL_GP15_NAND_BYTE_ADDR )
+#define PULL_CTRL_GP16_NANDIO_BYTE_REG		REG8_PTR(PULL_CTRL_GP16_NANDIO_BYTE_ADDR )
+#define PULL_CTRL_GP17_I2C_BYTE_REG     	REG8_PTR(PULL_CTRL_GP17_I2C_BYTE_ADDR )
+#define PULL_CTRL_GP18_UART_BYTE_REG     	REG8_PTR(PULL_CTRL_GP18_UART_BYTE_ADDR )
+#define PULL_CTRL_GP19_SD2_BYTE_REG     	REG8_PTR(PULL_CTRL_GP19_SD2_BYTE_ADDR )
+#define PULL_CTRL_GP20_PWM0_BYTE_REG      	REG8_PTR(PULL_CTRL_GP20_PWM0_BYTE_ADDR )
+#define PULL_CTRL_GP21_HDMI_BYTE_REG		REG8_PTR(PULL_CTRL_GP21_HDMI_BYTE_ADDR )
+#define PULL_CTRL_GP23_I2C3_BYTE_REG		REG8_PTR(PULL_CTRL_GP23_I2C3_BYTE_ADDR )
+#define PULL_CTRL_GP24_SF_BYTE_REG     		REG8_PTR(PULL_CTRL_GP24_SF_BYTE_ADDR )
+#define PULL_CTRL_GP26_PCM_BYTE_REG			REG8_PTR(PULL_CTRL_GP26_PCM_BYTE_ADDR )
+#define PULL_CTRL_GP27_SD0_BYTE_REG			REG8_PTR(PULL_CTRL_GP27_SD0_BYTE_ADDR )
+#define PULL_CTRL_GP60_USB_BYTE_REG			REG8_PTR(PULL_CTRL_GP60_USB_BYTE_ADDR )
+#define PULL_CTRL_GP62_WAKEUP_SUS_BYTE_REG	REG8_PTR(PULL_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define PULL_CTRL_GP63_SD02_BYTE_REG		REG8_PTR(PULL_CTRL_GP63_SD02_BYTE_ADDR )
+#define DRV_GPIO_7_0_4BYTE_REG				REG32_PTR(DRV_GPIO_7_0_4BYTE_ADDR )
+#define DRV_GPIO_13_8_4BYTE_REG				REG32_PTR(DRV_GPIO_13_8_4BYTE_ADDR )
+#define DRV_GPIO_19_14_4BYTE_REG			REG32_PTR(DRV_GPIO_19_14_4BYTE_ADDR )
+#define DRV_VDIN_3_0_4BYTE_REG				REG32_PTR(DRV_VDIN_3_0_4BYTE_ADDR )
+#define DRV_VDIN_4_6_4BYTE_REG				REG32_PTR(DRV_VDIN_3_0_4BYTE_ADDR )
+#define DRV_VDIN_SPI_4BYTE_REG				REG32_PTR(DRV_VDIN_SPI_4BYTE_ADDR )
+#define DRV_SPI_NAND_4BYTE_REG				REG32_PTR(DRV_SPI_NAND_4BYTE_ADDR )
+#define DRV_NAND_4BYTE_REG					REG32_PTR(DRV_NAND_4BYTE_ADDR )
+#define DRV_NANDIO_4BYTE_REG				REG32_PTR(DRV_NANDIO_4BYTE_ADDR )
+#define DRV_HDMI_I2C_4BYTE_REG				REG32_PTR(DRV_HDMI_I2C_4BYTE_ADDR )
+#define DRV_I2C_SD0_4BYTE_REG				REG32_PTR(DRV_I2C_SD0_4BYTE_ADDR )
+#define DRV_SD0_SD2_4BYTE_REG				REG32_PTR(DRV_SD0_SD2_4BYTE_ADDR )
+#define DRV_SD2_I2S_4BYTE_REG				REG32_PTR(DRV_SD2_I2S_4BYTE_ADDR )
+#define DRV_I2S_UART_4BYTE_REG				REG32_PTR(DRV_I2S_UART_4BYTE_ADDR )
+#define DRV_UART_4BYTE_REG					REG32_PTR(DRV_UART_4BYTE_ADDR )
+#define DRV_SF_JTAGT_4BYTE_REG				REG32_PTR(DRV_SF_JTAGT_4BYTE_ADDR )
+#define DRV_JTAGT_PWM_4BYTE_REG				REG32_PTR(DRV_JTAGT_PWM_4BYTE_ADDR )
+#define DRV_PCM_BYTE_REG					REG8_PTR(DRV_PCM_BYTE_ADDR )
+#define DRV_SPI_BYTE_REG					REG8_PTR(DRV_SPI_BYTE_ADDR )
+
+#define GPIO_ID_GP0_BYTE_VAL					REG8_VAL(GPIO_ID_GP0_BYTE_ADDR )
+#define GPIO_ID_GP1_BYTE_VAL 					REG8_VAL(GPIO_ID_GP1_BYTE_ADDR )
+#define GPIO_ID_GP2_BYTE_VAL					REG8_VAL(GPIO_ID_GP2_BYTE_ADDR )
+#define GPIO_ID_GP4_VDOUT_7_0_BYTE_VAL			REG8_VAL(GPIO_ID_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_ID_GP5_VDOUT_15_8_BYTE_VAL			REG8_VAL(GPIO_ID_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_ID_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_ID_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_ID_GP7_VD_BYTE_VAL					REG8_VAL(GPIO_ID_GP7_VD_BYTE_ADDR )
+#define GPIO_ID_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_ID_GP8_VDIN_BYTE_ADDR )
+#define GPIO_ID_GP9_VSYNC_BYTE_VAL				REG8_VAL(GPIO_ID_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_ID_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_ID_GP10_I2S_BYTE_ADDR )
+#define GPIO_ID_GP11_I2S_BYTE_VAL				REG8_VAL(GPIO_ID_GP11_I2S_BYTE_ADDR )
+#define GPIO_ID_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_ID_GP12_SPI_BYTE_ADDR )
+#define GPIO_ID_GP13_SD0_BYTE_VAL   		REG8_VAL(GPIO_ID_GP13_SD0_BYTE_ADDR )
+#define GPIO_ID_GP14_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_ID_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_ID_GP15_NAND_BYTE_VAL				REG8_VAL(GPIO_ID_GP15_NAND_BYTE_ADDR )
+#define GPIO_ID_GP16_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_ID_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_ID_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_ID_GP17_I2C_BYTE_ADDR )
+#define GPIO_ID_GP18_UART_BYTE_VAL				REG8_VAL(GPIO_ID_GP18_UART_BYTE_ADDR )
+#define GPIO_ID_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_ID_GP19_SD2_BYTE_ADDR )
+#define GPIO_ID_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_ID_GP20_PWM0_BYTE_ADDR )
+#define GPIO_ID_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_ID_GP21_HDMI_BYTE_ADDR )
+#define GPIO_ID_GP23_I2C3_BYTE_VAL	    	   	REG8_VAL(GPIO_ID_GP23_I2C3_BYTE_ADDR )
+#define GPIO_ID_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_ID_GP24_SF_BYTE_ADDR )
+#define GPIO_ID_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_ID_GP26_PCM_BYTE_ADDR )
+#define GPIO_ID_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_ID_GP60_USB_BYTE_ADDR )
+#define GPIO_ID_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_ID_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_ID_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_ID_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_CTRL_GP0_BYTE_VAL 					REG8_VAL(GPIO_CTRL_GP0_BYTE_ADDR )
+#define GPIO_CTRL_GP1_BYTE_VAL 					REG8_VAL(GPIO_CTRL_GP1_BYTE_ADDR )
+#define GPIO_CTRL_GP2_BYTE_VAL 					REG8_VAL(GPIO_CTRL_GP2_BYTE_ADDR )
+#define GPIO_CTRL_GP4_VDOUT_7_0_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_CTRL_GP5_VDOUT_15_8_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_CTRL_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_CTRL_GP7_VD_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP7_VD_BYTE_ADDR )
+#define GPIO_CTRL_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP8_VDIN_BYTE_ADDR )
+#define GPIO_CTRL_GP9_VSYNC_BYTE_VAL 			REG8_VAL(GPIO_CTRL_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_CTRL_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP10_I2S_BYTE_ADDR )
+#define GPIO_CTRL_GP11_I2S_BYTE_VAL      		REG8_VAL(GPIO_CTRL_GP11_I2S_BYTE_ADDR )
+#define GPIO_CTRL_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP12_SPI_BYTE_ADDR )
+#define GPIO_CTRL_GP13_SD0_BYTE_VAL       	REG8_VAL(GPIO_CTRL_GP13_SD0_BYTE_ADDR )
+#define GPIO_CTRL_GP14_NAND_SD1_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_CTRL_GP15_NAND_BYTE_VAL			REG8_VAL(GPIO_CTRL_GP15_NAND_BYTE_ADDR )
+#define GPIO_CTRL_GP16_NAND_SD1_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_CTRL_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP17_I2C_BYTE_ADDR )
+#define GPIO_CTRL_GP18_UART_BYTE_VAL			REG8_VAL(GPIO_CTRL_GP18_UART_BYTE_ADDR )
+#define GPIO_CTRL_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_CTRL_GP19_SD2_BYTE_ADDR )
+#define GPIO_CTRL_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP20_PWM0_BYTE_ADDR )
+#define GPIO_CTRL_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP21_HDMI_BYTE_ADDR )
+#define GPIO_CTRL_GP23_I2C3_BYTE_VAL	    	REG8_VAL(GPIO_CTRL_GP23_I2C3_BYTE_ADDR )
+#define GPIO_CTRL_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP24_SF_BYTE_ADDR )
+#define GPIO_CTRL_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_CTRL_GP26_PCM_BYTE_ADDR )
+#define GPIO_CTRL_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_CTRL_GP60_USB_BYTE_ADDR )
+#define GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_CTRL_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_CTRL_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_OC_GP0_BYTE_VAL 					REG8_VAL(GPIO_OC_GP0_BYTE_ADDR )
+#define GPIO_OC_GP1_BYTE_VAL 					REG8_VAL(GPIO_OC_GP1_BYTE_ADDR )
+#define GPIO_OC_GP2_BYTE_VAL					REG8_VAL(GPIO_OC_GP2_BYTE_ADDR )
+#define GPIO_OC_GP4_VDOUT_7_0_BYTE_VAL			REG8_VAL(GPIO_OC_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_OC_GP5_VDOUT_15_8_BYTE_VAL			REG8_VAL(GPIO_OC_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_OC_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_OC_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_OC_GP7_VD_BYTE_VAL					REG8_VAL(GPIO_OC_GP7_VD_BYTE_ADDR )
+#define GPIO_OC_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_OC_GP8_VDIN_BYTE_ADDR )
+#define GPIO_OC_GP9_VSYNC_BYTE_VAL 				REG8_VAL(GPIO_OC_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_OC_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_OC_GP10_I2S_BYTE_ADDR )
+#define GPIO_OC_GP11_I2S_BYTE_VAL      			REG8_VAL(GPIO_OC_GP11_I2S_BYTE_ADDR )
+#define GPIO_OC_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_OC_GP12_SPI_BYTE_ADDR )
+#define GPIO_OC_GP13_SD0_BYTE_VAL   		REG8_VAL(GPIO_OC_GP13_SD0_BYTE_ADDR )
+#define GPIO_OC_GP14_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OC_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_OC_GP15_NAND_BYTE_VAL				REG8_VAL(GPIO_OC_GP15_NAND_BYTE_ADDR )
+#define GPIO_OC_GP16_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OC_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_OC_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_OC_GP17_I2C_BYTE_ADDR )
+#define GPIO_OC_GP18_UART_BYTE_VAL				REG8_VAL(GPIO_OC_GP18_UART_BYTE_ADDR )
+#define GPIO_OC_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_OC_GP19_SD2_BYTE_ADDR )
+#define GPIO_OC_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_OC_GP20_PWM0_BYTE_ADDR )
+#define GPIO_OC_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_OC_GP21_HDMI_BYTE_ADDR )
+#define GPIO_OC_GP22_I2C3_BYTE_VAL	     	  	REG8_VAL(GPIO_OC_GP22_I2C3_BYTE_ADDR )
+#define GPIO_OC_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_OC_GP24_SF_BYTE_ADDR )
+#define GPIO_OC_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_OC_GP26_PCM_BYTE_ADDR )
+#define GPIO_OC_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_OC_GP60_USB_BYTE_ADDR )
+#define GPIO_OC_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_OC_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_OC_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_OC_GP63_SD02CD_BYTE_ADDR )
+#define GPIO_OD_GP0_BYTE_VAL 					REG8_VAL(GPIO_OD_GP0_BYTE_ADDR )
+#define GPIO_OD_GP1_BYTE_VAL 					REG8_VAL(GPIO_OD_GP1_BYTE_ADDR )
+#define GPIO_OD_GP2_BYTE_VAL					REG8_VAL(GPIO_OD_GP2_BYTE_ADDR )
+#define GPIO_OD_GP4_VDOUT_7_0_BYTE_VAL			REG8_VAL(GPIO_OD_GP4_VDOUT_7_0_BYTE_ADDR )
+#define GPIO_OD_GP5_VDOUT_15_8_BYTE_VAL			REG8_VAL(GPIO_OD_GP5_VDOUT_15_8_BYTE_ADDR )
+#define GPIO_OD_GP6_VDOUT_23_16_BYTE_VAL		REG8_VAL(GPIO_OD_GP6_VDOUT_23_16_BYTE_ADDR )
+#define GPIO_OD_GP7_VD_BYTE_VAL					REG8_VAL(GPIO_OD_GP7_VD_BYTE_ADDR )
+#define GPIO_OD_GP8_VDIN_BYTE_VAL				REG8_VAL(GPIO_OD_GP8_VDIN_BYTE_ADDR )
+#define GPIO_OD_GP9_VSYNC_BYTE_VAL 				REG8_VAL(GPIO_OD_GP9_VSYNC_BYTE_ADDR )
+#define GPIO_OD_GP10_I2S_BYTE_VAL				REG8_VAL(GPIO_OD_GP10_I2S_BYTE_ADDR )
+#define GPIO_OD_GP11_I2S_BYTE_VAL      			REG8_VAL(GPIO_OD_GP11_I2S_BYTE_ADDR )
+#define GPIO_OD_GP12_SPI_BYTE_VAL				REG8_VAL(GPIO_OD_GP12_SPI_BYTE_ADDR )
+#define GPIO_OD_GP13_SD0_BYTE_VAL   		REG8_VAL(GPIO_OD_GP13_SD0_BYTE_ADDR )
+#define GPIO_OD_GP14_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OD_GP14_NAND_SD1_BYTE_ADDR )
+#define GPIO_OD_GP15_NAND_BYTE_VAL				REG8_VAL(GPIO_OD_GP15_NAND_BYTE_ADDR )
+#define GPIO_OD_GP16_NAND_SD1_BYTE_VAL			REG8_VAL(GPIO_OD_GP16_NAND_SD1_BYTE_ADDR )
+#define GPIO_OD_GP17_I2C_BYTE_VAL       		REG8_VAL(GPIO_OD_GP17_I2C_BYTE_ADDR )
+#define GPIO_OD_GP18_UART_BYTE_VAL				REG8_VAL(GPIO_OD_GP18_UART_BYTE_ADDR )
+#define GPIO_OD_GP19_SD2_BYTE_VAL   	    	REG8_VAL(GPIO_OD_GP19_SD2_BYTE_ADDR )
+#define GPIO_OD_GP20_PWM0_BYTE_VAL       		REG8_VAL(GPIO_OD_GP20_PWM0_BYTE_ADDR )
+#define GPIO_OD_GP21_HDMI_BYTE_VAL       		REG8_VAL(GPIO_OD_GP21_HDMI_BYTE_ADDR )
+#define GPIO_OD_GP23_I2C3_BYTE_VAL	       		REG8_VAL(GPIO_OD_GP23_I2C3_BYTE_ADDR )
+#define GPIO_OD_GP24_SF_BYTE_VAL				REG8_VAL(GPIO_OD_GP24_SF_BYTE_ADDR )
+#define GPIO_OD_GP26_PCM_BYTE_VAL       		REG8_VAL(GPIO_OD_GP26_PCM_BYTE_ADDR )
+#define GPIO_OD_GP60_USB_BYTE_VAL				REG8_VAL(GPIO_OD_GP60_USB_BYTE_ADDR )
+#define GPIO_OD_GP62_WAKEUP_SUS_BYTE_VAL		REG8_VAL(GPIO_OD_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define GPIO_OD_GP63_SD02CD_BYTE_VAL			REG8_VAL(GPIO_OD_GP63_SD02CD_BYTE_ADDR )
+#define STRAP_STATUS_VAL					REG32_VAL(STRAP_STATUS_ADDR )
+#define AHB_CTRL_4BYTE_VAL 					REG32_VAL(AHB_CTRL_4BYTE_ADDR )
+#define USB_OP_CTRL_4BYTE_VAL				REG32_VAL(USB_OP_CTRL_4BYTE_ADDR )
+#define BONDING_OPTION_4BYTE_VAL			REG32_VAL(BONDING_OPTION_4BYTE_ADDR )
+#define PIN_SHARING_SEL_4BYTE_VAL 			REG32_VAL(PIN_SHARING_SEL_4BYTE_ADDR )
+#define TPIU_CLK_DATA_4BYTE_VAL 			REG32_VAL(TPIU_CLK_DATA_4BYTE_ADDR )
+#define GPIO0_INT_REQ_TYPE_VAL				REG8_VAL(GPIO0_INT_REQ_TYPE_ADDR )
+#define GPIO1_INT_REQ_TYPE_VAL				REG8_VAL(GPIO1_INT_REQ_TYPE_ADDR )
+#define GPIO2_INT_REQ_TYPE_VAL				REG8_VAL(GPIO2_INT_REQ_TYPE_ADDR )
+#define GPIO3_INT_REQ_TYPE_VAL				REG8_VAL(GPIO3_INT_REQ_TYPE_ADDR )
+#define GPIO4_INT_REQ_TYPE_VAL				REG8_VAL(GPIO4_INT_REQ_TYPE_ADDR )
+#define GPIO5_INT_REQ_TYPE_VAL				REG8_VAL(GPIO5_INT_REQ_TYPE_ADDR )
+#define GPIO6_INT_REQ_TYPE_VAL				REG8_VAL(GPIO6_INT_REQ_TYPE_ADDR )
+#define GPIO7_INT_REQ_TYPE_VAL				REG8_VAL(GPIO7_INT_REQ_TYPE_ADDR )
+#define GPIO8_INT_REQ_TYPE_VAL				REG8_VAL(GPIO8_INT_REQ_TYPE_ADDR )
+#define GPIO9_INT_REQ_TYPE_VAL				REG8_VAL(GPIO9_INT_REQ_TYPE_ADDR )
+#define GPIO10_INT_REQ_TYPE_VAL				REG8_VAL(GPIO10_INT_REQ_TYPE_ADDR )
+#define GPIO11_INT_REQ_TYPE_VAL				REG8_VAL(GPIO11_INT_REQ_TYPE_ADDR )
+#define GPIO12_INT_REQ_TYPE_VAL				REG8_VAL(GPIO12_INT_REQ_TYPE_ADDR )
+#define GPIO13_INT_REQ_TYPE_VAL				REG8_VAL(GPIO13_INT_REQ_TYPE_ADDR )
+#define GPIO18_INT_REQ_TYPE_VAL				REG8_VAL(GPIO18_INT_REQ_TYPE_ADDR )
+#define GPIO19_INT_REQ_TYPE_VAL				REG8_VAL(GPIO19_INT_REQ_TYPE_ADDR )
+#define VOUT20_INT_REQ_TYPE_VAL				REG8_VAL(VOUT20_INT_REQ_TYPE_ADDR )
+#define VOUT21_INT_REQ_TYPE_VAL				REG8_VAL(VOUT21_INT_REQ_TYPE_ADDR )
+#define VOUT22_INT_REQ_TYPE_VAL				REG8_VAL(VOUT22_INT_REQ_TYPE_ADDR )
+#define VOUT23_INT_REQ_TYPE_VAL				REG8_VAL(VOUT23_INT_REQ_TYPE_ADDR )
+#define GPIO20_INT_REQ_TYPE_VAL				REG8_VAL(GPIO20_INT_REQ_TYPE_ADDR )
+#define GPIO21_INT_REQ_TYPE_VAL				REG8_VAL(GPIO21_INT_REQ_TYPE_ADDR )
+#define GPIO22_INT_REQ_TYPE_VAL				REG8_VAL(GPIO22_INT_REQ_TYPE_ADDR )
+#define GPIO23_INT_REQ_TYPE_VAL				REG8_VAL(GPIO23_INT_REQ_TYPE_ADDR )
+#define GPIO24_INT_REQ_TYPE_VAL				REG8_VAL(GPIO24_INT_REQ_TYPE_ADDR )
+#define GPIO25_INT_REQ_TYPE_VAL				REG8_VAL(GPIO25_INT_REQ_TYPE_ADDR )
+#define GPIO0_INT_REQ_STS_VAL				REG8_VAL(GPIO0_INT_REQ_STS_ADDR )
+#define GPIO1_INT_REQ_STS_VAL				REG8_VAL(GPIO1_INT_REQ_STS_ADDR )
+#define GPIO2_INT_REQ_STS_VAL				REG8_VAL(GPIO2_INT_REQ_STS_ADDR )
+#define GPIO3_INT_REQ_STS_VAL				REG8_VAL(GPIO3_INT_REQ_STS_ADDR )
+#define DRV_DVO_CLK_BYTE_VAL				REG8_VAL(DRV_DVO_CLK_BYTE_ADDR )
+#define DRV_DVO_VDEN_BYTE_VAL				REG8_VAL(DRV_DVO_VDEN_BYTE_ADDR )
+#define SD0_DPCTL_4BYTE_VAL					REG32_VAL(SD0_DPCTL_4BYTE_ADDR )
+#define SD0_DNCTL_4BYTE_VAL					REG32_VAL(SD0_DNCTL_4BYTE_ADDR )
+#define DRV_SD0_USB_BYTE_VAL				REG8_VAL(DRV_SD0_USB_BYTE_ADDR )	
+#define DRV_USB_SWOC0_BYTE_VAL				REG8_VAL(DRV_USB_SWOC0_BYTE_ADDR )
+#define DRV_USB_OC12_BYTE_VAL				REG8_VAL(DRV_USB_OC12_BYTE_ADDR )
+#define DRV_USBOC3_CIR_BYTE_VAL				REG8_VAL(DRV_USBOC3_CIR_BYTE_ADDR )
+#define DRV_PWREN_BYTE_VAL					REG8_VAL(DRV_PWREN_BYTE_ADDR )
+#define DRV_PWREN_WAKEUP0_BYTE_VAL			REG8_VAL(DRV_PWREN_WAKEUP0_BYTE_ADDR )
+#define DRV_SUSGP01_BYTE_VAL				REG8_VAL(DRV_SUSGP01_BYTE_ADDR )
+#define DRV_WAKEUP23_BYTE_VAL				REG8_VAL(DRV_WAKEUP23_BYTE_ADDR )
+#define DRV_WAKEUP45_BYTE_VAL				REG8_VAL(DRV_WAKEUP45_BYTE_ADDR )
+#define DRV_I2C_BYTE_VAL					REG8_VAL(DRV_I2C_BYTE_ADDR )
+#define DRV_HDMI_BYTE_VAL					REG8_VAL(DRV_HDMI_BYTE_ADDR )	
+#define PULL_EN_GP0_BYTE_VAL				REG8_VAL(PULL_EN_GP0_BYTE_ADDR )
+#define PULL_EN_GP1_BYTE_VAL				REG8_VAL(PULL_EN_GP1_BYTE_ADDR )
+#define PULL_EN_GP2_BYTE_VAL				REG8_VAL(PULL_EN_GP2_BYTE_ADDR )
+#define PULL_EN_GP4_VDOUT_7_0_BYTE_VAL		REG8_VAL(PULL_EN_GP4_VDOUT_7_0_BYTE_ADDR )
+#define PULL_EN_GP5_VDOUT_15_8_BYTE_VAL		REG8_VAL(PULL_EN_GP5_VDOUT_15_8_BYTE_ADDR )
+#define PULL_EN_GP6_VDOUT_23_16_BYTE_VAL	REG8_VAL(PULL_EN_GP6_VDOUT_23_16_BYTE_ADDR )
+#define PULL_EN_GP7_VD_BYTE_VAL     		REG8_VAL(PULL_EN_GP7_VD_BYTE_ADDR )
+#define PULL_EN_GP8_VDIN_BYTE_VAL   		REG8_VAL(PULL_EN_GP8_VDIN_BYTE_ADDR )
+#define PULL_EN_GP9_VSYNC_BYTE_VAL 			REG8_VAL(PULL_EN_GP9_VSYNC_BYTE_ADDR )
+#define PULL_EN_GP10_I2S_BYTE_VAL 			REG8_VAL(PULL_EN_GP10_I2S_BYTE_ADDR )
+#define PULL_EN_GP11_I2S_BYTE_VAL     		REG8_VAL(PULL_EN_GP11_I2S_BYTE_ADDR )
+#define PULL_EN_GP12_SPI_BYTE_VAL			REG8_VAL(PULL_EN_GP12_SPI_BYTE_ADDR )
+#define PULL_EN_GP13_SD0_BYTE_VAL       	REG8_VAL(PULL_EN_GP13_SD0_BYTE_ADDR )
+#define PULL_EN_GP14_NAND_BYTE_VAL      	REG8_VAL(PULL_EN_GP14_NAND_BYTE_ADDR )
+#define PULL_EN_GP15_NAND_BYTE_VAL			REG8_VAL(PULL_EN_GP15_NAND_BYTE_ADDR )
+#define PULL_EN_GP16_NANDIO_BYTE_VAL		REG8_VAL(PULL_EN_GP16_NANDIO_BYTE_ADDR )
+#define PULL_EN_GP17_I2C_BYTE_VAL			REG8_VAL(PULL_EN_GP17_I2C_BYTE_ADDR )
+#define PULL_EN_GP18_UART_BYTE_VAL			REG8_VAL(PULL_EN_GP18_UART_BYTE_ADDR )
+#define PULL_EN_GP19_SD2_BYTE_VAL			REG8_VAL(PULL_EN_GP19_SD2_BYTE_ADDR )
+#define PULL_EN_GP20_PWM0_BYTE_VAL			REG8_VAL(PULL_EN_GP20_PWM0_BYTE_ADDR )
+#define PULL_EN_GP21_HDMI_BYTE_VAL      	REG8_VAL(PULL_EN_GP21_HDMI_BYTE_ADDR )
+#define PULL_EN_GP23_I2C3_BYTE_VAL			REG8_VAL(PULL_EN_GP23_I2C3_BYTE_ADDR )
+#define PULL_EN_GP24_SF_BYTE_VAL			REG8_VAL(PULL_EN_GP24_SF_BYTE_ADDR )
+#define PULL_EN_GP26_PCM_BYTE_VAL			REG8_VAL(PULL_EN_GP26_PCM_BYTE_ADDR )
+#define PULL_EN_GP60_USB_BYTE_VAL			REG8_VAL(PULL_EN_GP60_USB_BYTE_ADDR )
+#define PULL_EN_GP62_WAKEUP_SUS_BYTE_VAL	REG8_VAL(PULL_EN_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define PULL_EN_GP63_SD02_BYTE_VAL			REG8_VAL(PULL_EN_GP63_SD02_BYTE_ADDR )
+#define PULL_CTRL_GP0_BYTE_VAL				REG8_VAL(PULL_CTRL_GP0_BYTE_ADDR )
+#define PULL_CTRL_GP1_BYTE_VAL				REG8_VAL(PULL_CTRL_GP1_BYTE_ADDR )
+#define PULL_CTRL_GP2_BYTE_VAL				REG8_VAL(PULL_CTRL_GP2_BYTE_ADDR )
+#define PULL_CTRL_GP4_VDOUT_7_0_BYTE_VAL	REG8_VAL(PULL_CTRL_GP4_VDOUT_7_0_BYTE_ADDR )
+#define PULL_CTRL_GP5_VDOUT_15_8_BYTE_VAL	REG8_VAL(PULL_CTRL_GP5_VDOUT_15_8_BYTE_ADDR )
+#define PULL_CTRL_GP6_VDOUT_23_16_BYTE_VAL	REG8_VAL(PULL_CTRL_GP6_VDOUT_23_16_BYTE_ADDR )
+#define PULL_CTRL_GP7_VD_BYTE_VAL			REG8_VAL(PULL_CTRL_GP7_VD_BYTE_ADDR )
+#define PULL_CTRL_GP8_VDIN_BYTE_VAL			REG8_VAL(PULL_CTRL_GP8_VDIN_BYTE_ADDR )
+#define PULL_CTRL_GP9_VSYNC_BYTE_VAL		REG8_VAL(PULL_CTRL_GP9_VSYNC_BYTE_ADDR )
+#define PULL_CTRL_GP10_I2S_BYTE_VAL			REG8_VAL(PULL_CTRL_GP10_I2S_BYTE_ADDR )
+#define PULL_CTRL_GP11_I2S_BYTE_VAL			REG8_VAL(PULL_CTRL_GP11_I2S_BYTE_ADDR )
+#define PULL_CTRL_GP12_SPI_BYTE_VAL			REG8_VAL(PULL_CTRL_GP12_SPI_BYTE_ADDR )
+#define PULL_CTRL_GP13_SD0_BYTE_VAL			REG8_VAL(PULL_CTRL_GP13_SD0_BYTE_ADDR )
+#define PULL_CTRL_GP14_NAND_BYTE_VAL       	REG8_VAL(PULL_CTRL_GP14_NAND_BYTE_ADDR )
+#define PULL_CTRL_GP15_NAND_BYTE_VAL		REG8_VAL(PULL_CTRL_GP15_NAND_BYTE_ADDR )
+#define PULL_CTRL_GP16_NANDIO_BYTE_VAL		REG8_VAL(PULL_CTRL_GP16_NANDIO_BYTE_ADDR )
+#define PULL_CTRL_GP17_I2C_BYTE_VAL     	REG8_VAL(PULL_CTRL_GP17_I2C_BYTE_ADDR )
+#define PULL_CTRL_GP18_UART_BYTE_VAL     	REG8_VAL(PULL_CTRL_GP18_UART_BYTE_ADDR )
+#define PULL_CTRL_GP19_SD2_BYTE_VAL     	REG8_VAL(PULL_CTRL_GP19_SD2_BYTE_ADDR )
+#define PULL_CTRL_GP20_PWM0_BYTE_VAL      	REG8_VAL(PULL_CTRL_GP20_PWM0_BYTE_ADDR )
+#define PULL_CTRL_GP21_HDMI_BYTE_VAL		REG8_VAL(PULL_CTRL_GP21_HDMI_BYTE_ADDR )
+#define PULL_CTRL_GP23_I2C3_BYTE_VAL		REG8_VAL(PULL_CTRL_GP23_I2C3_BYTE_ADDR )
+#define PULL_CTRL_GP24_SF_BYTE_VAL     		REG8_VAL(PULL_CTRL_GP24_SF_BYTE_ADDR )
+#define PULL_CTRL_GP26_PCM_BYTE_VAL			REG8_VAL(PULL_CTRL_GP26_PCM_BYTE_ADDR )
+#define PULL_CTRL_GP27_SD0_BYTE_VAL			REG8_VAL(PULL_CTRL_GP27_SD0_BYTE_ADDR )
+#define PULL_CTRL_GP60_USB_BYTE_VAL			REG8_VAL(PULL_CTRL_GP60_USB_BYTE_ADDR )
+#define PULL_CTRL_GP62_WAKEUP_SUS_BYTE_VAL	REG8_VAL(PULL_CTRL_GP62_WAKEUP_SUS_BYTE_ADDR )
+#define PULL_CTRL_GP63_SD02_BYTE_VAL		REG8_VAL(PULL_CTRL_GP63_SD02_BYTE_ADDR )
+#define DRV_GPIO_7_0_4BYTE_VAL				REG32_VAL(DRV_GPIO_7_0_4BYTE_ADDR )
+#define DRV_GPIO_13_8_4BYTE_VAL				REG32_VAL(DRV_GPIO_13_8_4BYTE_ADDR )
+#define DRV_GPIO_19_14_4BYTE_VAL			REG32_VAL(DRV_GPIO_19_14_4BYTE_ADDR )
+#define DRV_VDIN_3_0_4BYTE_VAL				REG32_VAL(DRV_VDIN_3_0_4BYTE_ADDR )
+#define DRV_VDIN_4_6_4BYTE_VAL				REG32_VAL(DRV_VDIN_3_0_4BYTE_ADDR )
+#define DRV_VDIN_SPI_4BYTE_VAL				REG32_VAL(DRV_VDIN_SPI_4BYTE_ADDR )
+#define DRV_SPI_NAND_4BYTE_VAL				REG32_VAL(DRV_SPI_NAND_4BYTE_ADDR )
+#define DRV_NAND_4BYTE_VAL					REG32_VAL(DRV_NAND_4BYTE_ADDR )
+#define DRV_NANDIO_4BYTE_VAL				REG32_VAL(DRV_NANDIO_4BYTE_ADDR )
+#define DRV_HDMI_I2C_4BYTE_VAL				REG32_VAL(DRV_HDMI_I2C_4BYTE_ADDR )
+#define DRV_I2C_SD0_4BYTE_VAL				REG32_VAL(DRV_I2C_SD0_4BYTE_ADDR )
+#define DRV_SD0_SD2_4BYTE_VAL				REG32_VAL(DRV_SD0_SD2_4BYTE_ADDR )
+#define DRV_SD2_I2S_4BYTE_VAL				REG32_VAL(DRV_SD2_I2S_4BYTE_ADDR )
+#define DRV_I2S_UART_4BYTE_VAL				REG32_VAL(DRV_I2S_UART_4BYTE_ADDR )
+#define DRV_UART_4BYTE_VAL					REG32_VAL(DRV_UART_4BYTE_ADDR )
+#define DRV_SF_JTAGT_4BYTE_VAL				REG32_VAL(DRV_SF_JTAGT_4BYTE_ADDR )
+#define DRV_JTAGT_PWM_4BYTE_VAL				REG32_VAL(DRV_JTAGT_PWM_4BYTE_ADDR )
+#define DRV_PCM_BYTE_VAL					REG8_VAL(DRV_PCM_BYTE_ADDR )
+#define DRV_SPI_BYTE_VAL					REG8_VAL(DRV_SPI_BYTE_ADDR )
+
+#define GPIO_STRAP_STS_VAL  		REG32_VAL(0x0100+BA_GPIO)
+
+/* [Rx300] GPIO Interrupt Request Type Register */
+#define GPIO_IRQT_LOW	  	0
+#define GPIO_IRQT_HIGH		BIT0
+#define GPIO_IRQT_FALLING	BIT1
+#define GPIO_IRQT_RISING	(BIT1 | BIT0)
+#define GPIO_IRQT_DOUBLE	BIT2
+
+/* GPIO Control Register for I2C */
+#define GPIO_I2C0_SCL	BIT0
+#define GPIO_I2C0_SDA	BIT1
+#define GPIO_I2C1_SCL	BIT2
+#define GPIO_I2C1_SDA	BIT3
+#define GPIO_I2C2_SCL	BIT4
+#define GPIO_I2C2_SDA	BIT5
+#define GPIO_I2C3_SCL	BIT0
+#define GPIO_I2C3_SDA	BIT1
+#define GPIO_I2C0_SCL_PULL_EN BIT0
+#define GPIO_I2C0_SDA_PULL_EN BIT1
+#define GPIO_I2C1_SCL_PULL_EN BIT2
+#define GPIO_I2C1_SDA_PULL_EN BIT3
+#define GPIO_I2C2_SCL_PULL_EN BIT4
+#define GPIO_I2C2_SDA_PULL_EN BIT5
+#define GPIO_I2C3_SCL_PULL_EN BIT0
+#define GPIO_I2C3_SDA_PULL_EN BIT1
+
+#endif
+/*=== END wmt_gpio.h ==========================================================*/
+
diff --git a/board/wmt/include/wmt_iomux.h b/board/wmt/include/wmt_iomux.h
new file mode 100755
index 0000000..486b752
--- /dev/null
+++ b/board/wmt/include/wmt_iomux.h
@@ -0,0 +1,45 @@
+
+#ifndef __MACH_WMT_IOMUX_H__
+#define __MACH_WMT_IOMUX_H__
+
+#include <linux/types.h>
+
+#undef	WMT_PIN
+#define WMT_PIN(__gp, __bit, __irq, __name)	__name,
+enum iomux_pins {
+	#include "iomux.h"
+	IOMUX_MAX_PIN,
+};
+
+/* use gpiolib dispatchers */
+#define gpio_get_value		__gpio_get_value
+#define gpio_set_value		__gpio_set_value
+#define gpio_cansleep		__gpio_cansleep
+
+enum gpio_pulltype {
+	GPIO_PULL_NONE = 0,
+	GPIO_PULL_UP,
+	GPIO_PULL_DOWN,
+};
+
+typedef struct _GPIO_ENV_ {
+	int gpiono;
+	int active;
+} GPIO_ENV;
+
+static inline int gpio_is_valid(int gpio)
+{
+	return (gpio >= 0 && gpio < IOMUX_MAX_PIN);
+}
+
+//extern int	gpio_request		(unsigned gpio);
+extern void	gpio_free		(unsigned gpio);
+extern int	gpio_get_value		(unsigned gpio);
+extern void	gpio_set_value		(unsigned gpio, int value);
+extern int	gpio_direction_input	(unsigned gpio);
+extern int	gpio_direction_output	(unsigned gpio, int value);
+extern int	gpio_setpull		(unsigned int gpio, enum gpio_pulltype pull);
+extern int      parse_gpio_env          (char *name, GPIO_ENV *p_env);
+
+#endif /* #ifndef __MACH_WMT_IOMUX_H__ */
+
diff --git a/board/wmt/include/wmt_pmc.h b/board/wmt/include/wmt_pmc.h
new file mode 100755
index 0000000..0892098
--- /dev/null
+++ b/board/wmt/include/wmt_pmc.h
@@ -0,0 +1,1359 @@
+/*++
+linux/include/asm-arm/arch-wmt/wmt_pmc.h
+
+Copyright (c) 2008  WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under the
+terms of the GNU General Public License as published by the Free Software Foundation,
+either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+You should have received a copy of the GNU General Public License along with
+this program.  If not, see <http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef __VT8500_PMC_H
+#define __VT8500_PMC_H
+
+#define __PMC_BASE      0xD8130000      /* 64K */
+
+/******************************************************************************
+ *
+ * VT8500 Power Management (PM) control registers.
+ *
+ * Registers Abbreviations:
+ *
+ * PMCS_REG     	PM (Current) Status Register.
+ *
+ * PMIR_REG     	PM Idle processor Request Register.
+ *
+ * PMTC_REG     	PM power-up Time Control Register.
+ *
+ * PMHV_REG     	PM Hibernation Value Register.
+ *
+ * PMHC_REG     	PM Hibernation Control Register.
+ *
+ * PMWS_REG     	PM Wake-up Status register.
+ *
+ * PMWE_REG     	PM Wake-up event Enable Register.
+ *
+ * PMWT_REG     	PM Wake-up event Type Register.
+ *
+ * HSP0_REG     	PM Hibernation Scratch Pad Register 0
+ *
+ * HSP1_REG     	PM Hibernation Scratch Pad Register 1
+ *
+ * HSP2_REG     	PM Hibernation Scratch Pad Register 2
+ *
+ * HSP3_REG     	PM Hibernation Scratch Pad Register 3
+ *
+ * PMRS_REG     	PM Reset Status Register.
+ *
+ * PMPB_REG			PM Button Control Register
+ *
+ * PMSR_REG     	PM Software Reset request Register.
+ *
+ * PMPATA_REG     	PM PATA I/Os Drive strength Register
+ *
+ * OSM0_REG     	OS Timer Match Register 0
+ *
+ * OSM1_REG     	OS Timer Match Register 1
+ *
+ * OSM2_REG     	OS Timer Match Register 2
+ *
+ * OSM3_REG     	OS Timer Match Register 3
+ *
+ * OSCR_REG     	OS Timer Count Register.
+ *
+ * OSTS_REG     	OS Timer Status Register.
+ *
+ * OSTW_REG     	OS Timer Watchdog enable Register.
+ *
+ * OSTI_REG     	OS Timer Interrupt enable Register.
+ *
+ * OSTC_REG     	OS Timer Control Register.
+ *
+ * OSTA_REG     	OS Timer Access status Register.
+ *
+ * PMMISC_REG    	PM miscellaneous (Peripherals) Clock Control Register.
+ *
+ * PMPMA_REG    	PM PLL_A Multiplier and range values Register.
+ *
+ * PMPMB_REG    	PM PLL_B Multiplier and range values Register.
+ *
+ * PMPMC_REG    	PM PLL_C Multiplier and range values Register.
+ *
+ * PMPMD_REG    	PM PLL_D Multiplier and range values Register.
+ *
+ * PMCEL_REG	  	PM	Clock Enables Lower Register
+ *
+ * PMCEU_REG	 	PM	Clock Enables Upper Register
+ *
+ * PMZD_REG    		PM ZAC2_MA clock's "P" Divisor value Register.
+ *
+ * PMZH_REG    		PM ZAC2_MA clock's High pulse is the wide pulse Register.
+ *
+ * PMAD_REG    		PM AHB clock's "A" Divisor value Register.
+ *
+ * PMMC_REG		 	PM DDR Memory Control Clock Divisor Register
+ *
+ * PMSF_REG    		PM Serial Flash controller clock's Divisor value Register.
+ *
+ * PMSFH_REG   		PM Serial flash controller clock's High pulse is the wide
+ *             		pulse Register.
+ *
+ * PMCC_REG    		PM Compact flash clock Control
+ *
+ * PMCCH_REG   		PM Compact flash controller clock's High pulse is the wide
+ *
+ * PMSDMMC_REG 		PM SD/MMC clock Control
+ *
+ * PMSDMMCH_REG   	PM SD/MMC controller clock's High pulse is the wide
+ *
+ * PMMS_REG    		PM MS&MS-pro clock Control
+ *
+ * PMMSH_REG   		PM MS&MS-pro controller clock's High pulse is the wide
+ *
+ * PMNAND_REG  		PM nand clock Control
+ *
+ * PMNANDH_REG 		PM nand controller clock's High pulse is the wide
+ *
+ * PMLPC_REG    	PM LPC memory clock Control
+ *
+ * PMLPCH_REG  		PM LPC memory controller clock's High pulse is the wide
+ *
+ * PMSPI_REG    	PM SPI clock Control
+ *
+ * PMSPIH_REG  		PM SPI controller clock's High pulse is the wide
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Address constant for each register.
+ *
+ ******************************************************************************/
+#define PMCS_ADDR       (__PMC_BASE + 0x0000)
+#define PMCSH_ADDR      (__PMC_BASE + 0x0004)
+#define PMIR_ADDR       (__PMC_BASE + 0x0008)
+#define PMTC_ADDR       (__PMC_BASE + 0x000C)
+#define PMHV_ADDR       (__PMC_BASE + 0x0010)
+#define PMHC_ADDR       (__PMC_BASE + 0x0012)
+#define PMWS_ADDR       (__PMC_BASE + 0x0014)
+#define PMCS2_ADDR			(__PMC_BASE + 0x0018)
+#define PMWE_ADDR       (__PMC_BASE + 0x001C)
+#define PMWT_ADDR       (__PMC_BASE + 0x0020)
+#define PMWTC_ADDR      (__PMC_BASE + 0x0024)
+
+#define PMCWS_ADDR      (__PMC_BASE + 0x0028)       /* Card_UDC wakeup status */
+#define PMCAD_ADDR      (__PMC_BASE + 0x002C)       /* Card attach debounce control */
+
+#define HSP0_ADDR       (__PMC_BASE + 0x0030)
+#define HSP1_ADDR       (__PMC_BASE + 0x0034)
+#define HSP2_ADDR       (__PMC_BASE + 0x0038)
+#define HSP3_ADDR       (__PMC_BASE + 0x003C)
+#define HSP4_ADDR       (__PMC_BASE + 0x0040)
+#define HSP5_ADDR       (__PMC_BASE + 0x0044)
+#define HSP6_ADDR       (__PMC_BASE + 0x0048)
+#define HSP7_ADDR       (__PMC_BASE + 0x004C)
+#define PMRS_ADDR       (__PMC_BASE + 0x0050)
+#define PMPB_ADDR       (__PMC_BASE + 0x0054)
+#define PMAXILPI_ADDR   (__PMC_BASE + 0x0058)
+#define DCDET_STS_ADDR  (__PMC_BASE + 0x005C)
+#define PMSR_ADDR       (__PMC_BASE + 0x0060)
+#define TIOUT_RST_ADDR  (__PMC_BASE + 0x0064)
+#define BROM_PD_ADDR	  (__PMC_BASE + 0x0068)
+#define CA9MP_RSTC_ADDR (__PMC_BASE + 0x006C)
+#define CA9MP_RSTS_ADDR (__PMC_BASE + 0x0070)
+
+#define PMCIS_ADDR      (__PMC_BASE + 0x0074)      /* Interrupt status from wakeup source */
+#define PMCIE_ADDR      (__PMC_BASE + 0x007C)      /* Interrupt enable from wakeup source */
+#define INT_TYPE0_ADDR    (__PMC_BASE + 0x0080)
+#define INT_TYPE1_ADDR    (__PMC_BASE + 0x0084)
+#define INT_TYPE2_ADDR    (__PMC_BASE + 0x0088)
+
+
+#define RST_VECT_MAP_ADDR (__PMC_BASE + 0x0090)      /* USB OTG operation mode select */
+#define RTCCM_ADDR      	(__PMC_BASE + 0x0094)      /* RTC Clock Exist Monitor */
+#define PMSTM_ADDR      	(__PMC_BASE + 0x0098)      /* Suspend to DRAM */
+#define WK_EVT_TYPE_ADDR	(__PMC_BASE + 0x00A0)      /* WAKE UP EVENT TYPE */
+#define WK_TRG_EN_ADDR		(__PMC_BASE + 0x00B0)
+#define INT_TRG_EN_ADDR		(__PMC_BASE + 0x00B4)
+#define CA9MPC0_ADDR			(__PMC_BASE + 0x00C0)
+#define CA9MPC1_ADDR			(__PMC_BASE + 0x00C4)
+
+#define PWRUP_SRC_ADDR			(__PMC_BASE + 0x00D0)
+
+#define OSM4_ADDR       (__PMC_BASE + 0x00F0)
+#define OSM5_ADDR       (__PMC_BASE + 0x00F4)
+#define OSM6_ADDR       (__PMC_BASE + 0x00F8)
+#define OSM7_ADDR       (__PMC_BASE + 0x00FC)
+#define OSM0_ADDR       (__PMC_BASE + 0x0100)
+#define OSM1_ADDR       (__PMC_BASE + 0x0104)
+#define OSM2_ADDR       (__PMC_BASE + 0x0108)
+#define OSM3_ADDR       (__PMC_BASE + 0x010C)
+#define OSCR_ADDR       (__PMC_BASE + 0x0110)
+#define OSTS_ADDR       (__PMC_BASE + 0x0114)
+#define OSTW_ADDR       (__PMC_BASE + 0x0118)
+#define OSTI_ADDR       (__PMC_BASE + 0x011C)
+#define OSTC_ADDR       (__PMC_BASE + 0x0120)
+#define OSTA_ADDR       (__PMC_BASE + 0x0124)
+
+#define PMMISC_ADDR     (__PMC_BASE + 0x01FC)
+
+#define PMPMA_ADDR      (__PMC_BASE + 0x0200)
+#define PMPMB_ADDR      (__PMC_BASE + 0x0204)
+#define PMPMC_ADDR      (__PMC_BASE + 0x0208)
+#define PMPMD_ADDR      (__PMC_BASE + 0x020C)
+#define PMPME_ADDR      (__PMC_BASE + 0x0210)
+#define PMPMF_ADDR      (__PMC_BASE + 0x0214)     /* PLL Audio(I2S) Control Register */
+#define PMPMG_ADDR      (__PMC_BASE + 0x0218)
+
+#define PMCEL_ADDR      (__PMC_BASE + 0x0250)
+#define PMCEU_ADDR      (__PMC_BASE + 0x0254)
+#define PMCE2_ADDR      (__PMC_BASE + 0x0258)
+#define PMCE3_ADDR      (__PMC_BASE + 0x025C)
+#define DVFSSTS_ADDR    (__PMC_BASE + 0x0260)
+#define DVFSE0_ADDR     (__PMC_BASE + 0x0280)
+#define DVFSE1_ADDR     (__PMC_BASE + 0x0284)
+#define DVFSE2_ADDR     (__PMC_BASE + 0x0288)
+#define DVFSE3_ADDR     (__PMC_BASE + 0x028C)
+#define DVFSE4_ADDR     (__PMC_BASE + 0x0290)
+#define DVFSE5_ADDR     (__PMC_BASE + 0x0294)
+#define DVFSE6_ADDR     (__PMC_BASE + 0x0298)
+#define DVFSE7_ADDR     (__PMC_BASE + 0x029C)
+#define DVFSE8_ADDR     (__PMC_BASE + 0x02A0)
+#define DVFSE9_ADDR     (__PMC_BASE + 0x02A4)
+#define DVFSE10_ADDR    (__PMC_BASE + 0x02A8)
+#define DVFSE11_ADDR    (__PMC_BASE + 0x02AC)
+#define DVFSE12_ADDR    (__PMC_BASE + 0x02B0)
+#define DVFSE13_ADDR    (__PMC_BASE + 0x02B4)
+#define DVFSE14_ADDR    (__PMC_BASE + 0x02B8)
+#define DVFSE15_ADDR    (__PMC_BASE + 0x02BC)
+
+#define PMARM_ADDR      (__PMC_BASE + 0x0300)			/* ARM */
+#define PMARMH_ADDR     (__PMC_BASE + 0x0301)
+#define PMAHB_ADDR      (__PMC_BASE + 0x0304)			/* AHB */
+#define PML2C_ADDR      (__PMC_BASE + 0x030C)			/* L2C */
+#define PML2CH_ADDR     (__PMC_BASE + 0x030D)
+#define PMMC_ADDR       (__PMC_BASE + 0x0310)
+
+#define PMSF_ADDR       (__PMC_BASE + 0x0314)     /* SF */
+#define PMSFH_ADDR      (__PMC_BASE + 0x0315)
+#define PMNAND_ADDR     (__PMC_BASE + 0x0318)     /* NAND */
+#define PMNANDH_ADDR    (__PMC_BASE + 0x0319)
+#define PMNOR_ADDR 	    (__PMC_BASE + 0x031C)     /* NOR */
+#define PMNORH_ADDR	    (__PMC_BASE + 0x031D)
+#define PMAPB0_ADDR	    (__PMC_BASE + 0x0320)     /* APB 0 */
+#define PMAPB0H_ADDR 	  (__PMC_BASE + 0x0321)
+#define PMPCM0_ADDR	    (__PMC_BASE + 0x0324)     /* PCM 0 */
+#define PMPCM1_ADDR	    (__PMC_BASE + 0x0328)     /* PCM 1 */
+#define PMSDMMC_ADDR    (__PMC_BASE + 0x0330)     /* SD/MMC 0 */
+#define PMSDMMCH_ADDR   (__PMC_BASE + 0x0331)
+#define PMSDMMC1_ADDR   (__PMC_BASE + 0x0334)    	/* SD/MMC 1 */
+#define PMSDMMC1H_ADDR  (__PMC_BASE + 0x0335)
+#define PMSDMMC2_ADDR   (__PMC_BASE + 0x0338)    	/* SD/MMC 2 */
+#define PMSDMMC2H_ADDR  (__PMC_BASE + 0x0339)
+#define PMSDMMC3_ADDR   (__PMC_BASE + 0x033C)    	/* SD/MMC 3 */
+#define PMSDMMC3H_ADDR  (__PMC_BASE + 0x033D)                   
+#define PMSPI_ADDR      (__PMC_BASE + 0x0340)     /* SPI 0 */
+#define PMSPIH_ADDR	    (__PMC_BASE + 0x0341)
+#define PMSPI1_ADDR     (__PMC_BASE + 0x0344)     /* SPI 1 */
+#define PMSPI1H_ADDR	  (__PMC_BASE + 0x0345)
+#define PMSE_ADDR  		  (__PMC_BASE + 0x0348)     /* SE */
+#define PMSEH_ADDR		  (__PMC_BASE + 0x0349)
+#define PMPWM_ADDR      (__PMC_BASE + 0x0350)     /* PWM */
+#define PMPWMH_ADDR	    (__PMC_BASE + 0x0351)
+#define PMPAXI_ADDR     (__PMC_BASE + 0x0354)     /* PAXI */
+#define PMPAXIH_ADDR	  (__PMC_BASE + 0x0355)
+#define PMWMTNA_ADDR	  (__PMC_BASE + 0x0358)     /* NA 01 */
+#define PMWMTNAH_ADDR	  (__PMC_BASE + 0x0359)
+#define PMNA12_ADDR	    (__PMC_BASE + 0x035C)     /* NA 12 */
+#define PMNA12H_ADDR	  (__PMC_BASE + 0x035D)
+#define PMCNMNA_ADDR    (__PMC_BASE + 0x0360)     /* CNM NA */
+#define PMCNMNAH_ADDR   (__PMC_BASE + 0x0361)
+#define PMWMTVDU_ADDR	  (__PMC_BASE + 0x0368)     /* WMT VDU */
+#define PMWMTVDUH_ADDR	(__PMC_BASE + 0x0369)
+#define PMHDMITV_ADDR	  (__PMC_BASE + 0x036C)     /* HDMITV */
+#define PMHDMITVH_ADDR  (__PMC_BASE + 0x036D)
+#define PMDVO_ADDR  	  (__PMC_BASE + 0x0370)     /* DVO */
+#define PMDVOH_ADDR     (__PMC_BASE + 0x0371)
+#define PMAUDIO_ADDR		(__PMC_BASE + 0x0374) 		/* AUDIO/I2S */
+#define PMAUDIOH_ADDR	  (__PMC_BASE + 0x0375)
+#define PMCSI0_ADDR			(__PMC_BASE + 0x0380) 		/* CSI0 */
+#define PMCSI0H_ADDR	  (__PMC_BASE + 0x0381)
+#define PMCSI1_ADDR			(__PMC_BASE + 0x0384) 		/* CSI1 */
+#define PMCSI1H_ADDR	  (__PMC_BASE + 0x0385)
+#define PMMALI_ADDR	 		(__PMC_BASE + 0x0388)     /* MALI */
+#define PMMALIH_ADDR	  (__PMC_BASE + 0x0389)
+#define PMCNMVDU_ADDR		(__PMC_BASE + 0x038C)     /* CNM VDU */
+#define PMCNMVDUH_ADDR  (__PMC_BASE + 0x038D)
+#define PMHDI2C_ADDR    (__PMC_BASE + 0x0390)     /* HDMII2C */
+#define PMHDI2CH_ADDR	  (__PMC_BASE + 0x0391)
+#define PMADC_ADDR		  (__PMC_BASE + 0x0394)     /* ADC */
+#define PMADCH_ADDR		  (__PMC_BASE + 0x0395)
+#define PMI2C4_ADDR	    (__PMC_BASE + 0x039C)     /* I2C 4 */
+#define PMI2C4H_ADDR	  (__PMC_BASE + 0x039D)
+#define PMI2C0_ADDR	    (__PMC_BASE + 0x03A0)     /* I2C 0 */
+#define PMI2C0H_ADDR	  (__PMC_BASE + 0x03A1)
+#define PMI2C1_ADDR	    (__PMC_BASE + 0x03A4)     /* I2C 1 */
+#define PMI2C1H_ADDR	  (__PMC_BASE + 0x03A5)
+#define PMI2C2_ADDR	    (__PMC_BASE + 0x03A8)     /* I2C 2 */
+#define PMI2C2H_ADDR	  (__PMC_BASE + 0x03A9)
+#define PMI2C3_ADDR	    (__PMC_BASE + 0x03AC)     /* I2C 3 */
+#define PMI2C3H_ADDR	  (__PMC_BASE + 0x03AD)
+#define PML2CAXI_ADDR	  (__PMC_BASE + 0x03B0)     /* L2C AXI*/
+#define PML2CAXIH_ADDR	(__PMC_BASE + 0x03B1)
+#define PMATCLK_ADDR	  (__PMC_BASE + 0x03B4)     /* AT CLK*/
+#define PMATCLKH_ADDR		(__PMC_BASE + 0x03B5)
+#define PMPERI_ADDR			(__PMC_BASE + 0x03B8)     /* PERI CLK*/
+#define PMPERIH_ADDR		(__PMC_BASE + 0x03B9)
+#define PMTRACE_ADDR		(__PMC_BASE + 0x03BC)     /* TRACE CLK*/
+#define PMTRACEH_ADDR		(__PMC_BASE + 0x03BD)
+#define PMDBGAPB_ADDR		(__PMC_BASE + 0x03D0)     /* DBG APB*/
+#define PMDBGAPBH_ADDR 	(__PMC_BASE + 0x03D1)
+#define PM24MHZ_ADDR  	(__PMC_BASE + 0x03E4)     /* 24MHZ */
+#define PM24MHZH_ADDR   (__PMC_BASE + 0x03E5)
+#define PML2CTAG_ADDR	  (__PMC_BASE + 0x03F0)     /* L2C TAG */
+#define PML2CTAGH_ADDR  (__PMC_BASE + 0x03F1)
+#define PML2CDATA_ADDR	(__PMC_BASE + 0x03F4)     /* L2C DATA */
+#define PML2CDATAH_ADDR (__PMC_BASE + 0x03F5)
+#define PMCA9PMWDOD_ADDR 	(__PMC_BASE + 0x0480)		/* WATCH DOG RESET */
+#define PMSDPS_ADDR			 	(__PMC_BASE + 0x0500)		/* SD 0~2 POWER SWITCH */
+#define PMMALIGPPWR_ADDR	(__PMC_BASE + 0x0600)		/* MALI GP Power Shut Off Control and Status Register */
+#define PMWMTVDUPWR_ADDR	(__PMC_BASE + 0x0604)		/* WMT VDU Power Shut Off Control and Status Register */
+#define PMCA9C0PWR_ADDR 	(__PMC_BASE + 0x0608)	  /* CA9 CORE 0 Power Shut Off Control and Status Register */
+#define PML2CRAMPWR_ADDR 	(__PMC_BASE + 0x060C)		/* L2CRAM Power Shut Off Control and Status Register */
+#define PMNEON0PWR_ADDR 	(__PMC_BASE + 0x0610)	  /* NEON 0 Power Shut Off Control and Status Register */
+#define PMCA9C1PWR_ADDR 	(__PMC_BASE + 0x0614)	  /* CA9 CORE 1 Power Shut Off Control and Status Register */
+#define PMNEON1PWR_ADDR 	(__PMC_BASE + 0x0618)	  /* NEON 1 Power Shut Off Control and Status Register */
+#define PMC_MPWR_ADDR   	(__PMC_BASE + 0x061C)		  /* C&M Power Shut Off Control and Status Register */
+#define PMMALIL2CPWR_ADDR	(__PMC_BASE + 0x0620)		/* MALI L2C Power Shut Off Control and Status Register */
+#define PMMALIPP0PWR_ADDR	(__PMC_BASE + 0x0624)		/* MALI PP0 Power Shut Off Control and Status Register */
+#define PMMALIPP1PWR_ADDR	(__PMC_BASE + 0x0628)		/* MALI PP1 Power Shut Off Control and Status Register */
+#define AXI2AHB_ADDR     (__PMC_BASE + 0x0650)		/* AXI TO AHB POWER control */
+#define EBMCTS_ADDR     (__PMC_BASE + 0x0700)			/* EBM control and status */
+#define EBMINTCTS_ADDR  (__PMC_BASE + 0x0704)     /* EBM interrupt control and status */
+
+/******************************************************************************
+ *
+ * Register pointer.
+ *
+ ******************************************************************************/
+#define PMCS_REG			(REG32_PTR(PMCS_ADDR))/*0x00*/
+#define PMCSH_REG			(REG32_PTR(PMCSH_ADDR))/*0x04*/
+#define PMIR_REG			(REG8_PTR(PMIR_ADDR))/*0x08*/
+#define PMTC_REG			(REG8_PTR(PMTC_ADDR))/*0x0C*/
+#define PMHV_REG			(REG16_PTR(PMHV_ADDR))/*0x10*/
+#define PMHC_REG			(REG16_PTR(PMHC_ADDR))/*0x12*/
+#define PMWS_REG			(REG32_PTR(PMWS_ADDR))/*0x14*/
+#define PMCS2_REG			(REG32_PTR(PMCS2_ADDR))/*0x18*/
+#define PMWE_REG			(REG32_PTR(PMWE_ADDR))/*0x1C*/
+#define PMWT_REG			(REG32_PTR(PMWT_ADDR))/*0x20*/
+#define PMWTC_REG			(REG32_PTR(PMWTC_ADDR))/*0x24*/
+
+#define PMCWS_REG			(REG32_PTR(PMCWS_ADDR))/*0x28*/
+#define PMCAD_REG			(REG32_PTR(PMCAD_ADDR))/*0x2C*/
+
+#define HSP0_REG			(REG32_PTR(HSP0_ADDR))/*0x30*/
+#define HSP1_REG			(REG32_PTR(HSP1_ADDR))/*0x34*/
+#define HSP2_REG			(REG32_PTR(HSP2_ADDR))/*0x38*/
+#define HSP3_REG			(REG32_PTR(HSP3_ADDR))/*0x3c*/
+#define PMRS_REG			(REG32_PTR(PMRS_ADDR))/*0x50*/
+#define PMPB_REG			(REG32_PTR(PMPB_ADDR))/*0x54*/
+#define DCDET_STS_REG	(REG32_PTR(DCDET_STS_ADDR))/*0x5c*/
+#define PMSR_REG			(REG32_PTR(PMSR_ADDR))/*0x60*/
+#define TIOUT_RST_REG		(REG32_PTR(TIOUT_RST_ADDR))/*0x64*/
+#define BROM_PD_REG			(REG32_PTR(BROM_PD_ADDR))/*0x68*/
+#define CA9MP_RSTC_REG	(REG32_PTR(CA9MP_RSTC_ADDR))/*0x6C*/
+#define CA9MP_RSTS_REG	(REG32_PTR(CA9MP_RSTS_ADDR))/*0x70*/
+
+#define PMCIS_REG				(REG32_PTR(PMCIS_ADDR))/*0x74*/
+#define PMCIE_REG				(REG32_PTR(PMCIE_ADDR))/*0x7C*/
+#define INT_TYPE0_REG		(REG32_VAL(INT_TYPE0_ADDR))/*0x80*/
+#define INT_TYPE1_REG		(REG32_VAL(INT_TYPE1_ADDR))/*0x84*/
+#define INT_TYPE2_REG		(REG32_VAL(INT_TYPE2_ADDR))/*0x88*/
+
+#define RST_VECT_MAP_REG	(REG32_PTR(RST_VECT_MAP_ADDR))/*0x90*/
+#define RTCCM_REG			(REG32_PTR(RTCCM_ADDR))/*0x94*/
+#define PMSTM_REG			(REG32_PTR(PMSTM_ADDR))/*0x98*/
+
+#define WK_EVT_TYPE_REG	(REG32_PTR(WK_EVT_TYPE_ADDR))/*0xA0*/
+#define WK_TRG_EN_REG		(REG32_PTR(WK_TRG_EN_ADDR))/*0xB0*/
+#define INT_TRG_EN_REG	(REG32_PTR(INT_TRG_EN_ADDR))/*0xB4*/
+#define CA9MPC0_REG			(REG32_PTR(CA9MPC0_ADDR))/*0xC0*/
+#define CA9MPC1_REG			(REG32_PTR(CA9MPC1_ADDR))/*0xC4*/
+#define PWRUP_SRC_REG		(REG32_PTR(PWRUP_SRC_ADDR))/*0xD0*/
+
+
+#define OSM4_REG			(REG32_PTR(OSM4_ADDR))/*0xF0*/
+#define OSM5_REG			(REG32_PTR(OSM5_ADDR))
+#define OSM6_REG			(REG32_PTR(OSM6_ADDR))
+#define OSM7_REG			(REG32_PTR(OSM7_ADDR))
+#define OSM0_REG			(REG32_PTR(OSM0_ADDR))/*0x100*/
+#define OSM1_REG			(REG32_PTR(OSM1_ADDR))
+#define OSM2_REG			(REG32_PTR(OSM2_ADDR))
+#define OSM3_REG			(REG32_PTR(OSM3_ADDR))
+#define OSCR_REG			(REG32_PTR(OSCR_ADDR))
+#define OSTS_REG			(REG32_PTR(OSTS_ADDR))
+#define OSTW_REG			(REG32_PTR(OSTW_ADDR))
+#define OSTI_REG			(REG32_PTR(OSTI_ADDR))
+#define OSTC_REG			(REG32_PTR(OSTC_ADDR))
+#define OSTA_REG			(REG32_PTR(OSTA_ADDR))/*0x124*/
+
+#define PMMISC_REG		(REG32_PTR(PMMISC_ADDR))/*0x1FC*/
+#define PMPMA_REG			(REG32_PTR(PMPMA_ADDR))/*0x200*/
+#define PMPMB_REG			(REG32_PTR(PMPMB_ADDR))
+#define PMPMC_REG			(REG32_PTR(PMPMC_ADDR))
+#define PMPMD_REG			(REG32_PTR(PMPMD_ADDR))
+#define PMPME_REG			(REG32_PTR(PMPME_ADDR))
+#define PMPMF_REG 		(REG32_PTR(PMPMF_ADDR))
+#define PMPMG_REG 		(REG32_PTR(PMPMG_ADDR))
+
+#define PMCEL_REG			(REG32_PTR(PMCEL_ADDR))/*0x250*/
+#define PMCEU_REG			(REG32_PTR(PMCEU_ADDR))
+#define PMCE2_REG			(REG32_PTR(PMCE2_ADDR))
+#define PMCE3_REG			(REG32_PTR(PMCE3_ADDR))
+#define DVFSSTS_REG   (REG32_PTR(DVFSSTS_ADDR))/*0x260*/
+#define DVFSE0_REG    (REG32_PTR(DVFSE0_ADDR))    
+#define DVFSE1_REG    (REG32_PTR(DVFSE1_ADDR))    
+#define DVFSE2_REG    (REG32_PTR(DVFSE2_ADDR))    
+#define DVFSE3_REG    (REG32_PTR(DVFSE3_ADDR))    
+#define DVFSE4_REG    (REG32_PTR(DVFSE4_ADDR))    
+#define DVFSE5_REG    (REG32_PTR(DVFSE5_ADDR))    
+#define DVFSE6_REG    (REG32_PTR(DVFSE6_ADDR))    
+#define DVFSE7_REG    (REG32_PTR(DVFSE7_ADDR))    
+#define DVFSE8_REG    (REG32_PTR(DVFSE8_ADDR))    
+#define DVFSE9_REG    (REG32_PTR(DVFSE9_ADDR))    
+#define DVFSE10_REG   (REG32_PTR(DVFSE10_ADDR))    
+#define DVFSE11_REG   (REG32_PTR(DVFSE11_ADDR))    
+#define DVFSE12_REG   (REG32_PTR(DVFSE12_ADDR))    
+#define DVFSE13_REG   (REG32_PTR(DVFSE13_ADDR))    
+#define DVFSE14_REG   (REG32_PTR(DVFSE14_ADDR))    
+#define DVFSE15_REG   (REG32_PTR(DVFSE15_ADDR))
+    
+#define PMARM_REG				(REG8_PTR(PMARM_ADDR))
+#define PMARMH_REG			(REG8_PTR(PMARMH_ADDR))
+#define PMAHB_REG				(REG8_PTR(PMAHB_ADDR))
+#define PMAHBH_REG			(REG8_PTR(PMAHBH_ADDR))
+#define PMMC_REG				(REG8_PTR(PMMC_ADDR))
+#define PML2C_REG				(REG8_PTR(PML2C_ADDR))
+#define PML2CH_REG			(REG8_PTR(PML2CH_ADDR))
+
+#define PMSF_REG				(REG8_PTR(PMSF_ADDR))
+#define PMSFH_REG				(REG8_PTR(PMSFH_ADDR))
+#define PMAPB1_REG			(REG8_PTR(PMAPB1_ADDR))
+#define PMAPB1H_REG			(REG8_PTR(PMAPB1H_ADDR))
+#define PMAPB0_REG			(REG8_PTR(PMAPB0_ADDR))
+#define PMAPB0H_REG			(REG8_PTR(PMAPB0H_ADDR))
+#define PMPCM0_REG			(REG8_PTR(PMPCM0_ADDR))
+#define PMPCM1_REG			(REG8_PTR(PMPCM1_ADDR))
+#define PMSDMMC_REG			(REG8_PTR(PMSDMMC_ADDR))
+#define PMSDMMCH_REG		(REG8_PTR(PMSDMMCH_ADDR))
+#define PMMSP_REG				(REG8_PTR(PMMSP_ADDR))
+#define PMMSPH_REG			(REG8_PTR(PMMSPH_ADDR))
+#define PMNAND_REG			(REG8_PTR(PMNAND_ADDR))
+#define PMNANDH_REG			(REG8_PTR(PMNANDH_ADDR))
+#define PMXD_REG				(REG8_PTR(PMXD_ADDR))
+#define PMXDH_REG				(REG8_PTR(PMXDH_ADDR))
+#define PMLCD_REG				(REG8_PTR(PMXD_ADDR))
+#define PMLCDH_REG			(REG8_PTR(PMXDH_ADDR))
+#define PMSPI_REG				(REG8_PTR(PMSPI_ADDR))
+#define PMSPIH_REG			(REG8_PTR(PMSPIH_ADDR))
+#define PMSPI1_REG			(REG8_PTR(PMSPI1_ADDR))
+#define PMSPI1H_REG			(REG8_PTR(PMSPI1H_ADDR))
+#define PMSE_REG				(REG8_PTR(PMSE_ADDR))
+#define PMSEH_REG				(REG8_PTR(PMSEH_ADDR))
+#define PMSDMMC1_REG		(REG8_PTR(PMSDMMC1_ADDR))
+#define PMSDMMC1H_REG		(REG8_PTR(PMSDMMCH1_ADDR))
+#define PMPWM_REG				(REG8_PTR(PMPWM_ADDR))
+#define PMPWMH_REG			(REG8_PTR(PMPWMH_ADDR))
+#define PMPAXI_REG			(REG8_PTR(PMPAXI_ADDR))
+#define PMPAXIH_REG			(REG8_PTR(PMPAXIH_ADDR))
+#define PMWMTNA_REG			(REG8_PTR(PMWMTNA_ADDR))
+#define PMWMTNAH_REG		(REG8_PTR(PMWMTNAH_ADDR))
+
+#define PMNA12_REG			(REG8_PTR(PMNA12_ADDR))
+#define PMNA12H_REG			(REG8_PTR(PMNA12H_ADDR))
+#define PMCNMNA_REG			(REG8_PTR(PMCNMNA_ADDR))
+#define PMCNMNAH_REG		(REG8_PTR(PMCNMNAH_ADDR))
+#define PMWMTVDU_REG		(REG8_PTR(PMWMTVDU_ADDR))
+#define PMWMTVDUH_REG		(REG8_PTR(PMWMTVDUH_ADDR))
+#define PMHDMITV_REG		(REG8_PTR(PMHDMITV_ADDR))
+#define PMHDMITVH_REG		(REG8_PTR(PMHDMITVH_ADDR))
+#define PMDVO_REG				(REG8_PTR(PMDVO_ADDR))
+#define PMDVOH_REG			(REG8_PTR(PMDVOH_ADDR))
+#define PMAUDIO_REG			(REG8_PTR(PMAUDIO_ADDR))
+#define PMAUDIOH_REG		(REG8_PTR(PMAUDIOH_ADDR))
+#define PMCSI0_REG			(REG8_PTR(PMCSI0_ADDR))
+#define PMCSI0H_REG			(REG8_PTR(PMCSI0H_ADDR))
+#define PMCSI1_REG			(REG8_PTR(PMCSI1_ADDR))
+#define PMCSI1H_REG			(REG8_PTR(PMCSI1H_ADDR))
+
+#define PMMALI_REG			(REG8_PTR(PMMALI_ADDR))
+#define PMMALIH_REG			(REG8_PTR(PMMALIH_ADDR))
+#define PMCNMVDU_REG		(REG8_PTR(PMCNMVDU_ADDR))
+#define PMCNMVDUH_REG		(REG8_PTR(PMCNMVDUH_ADDR))
+#define PMHDI2C_REG			(REG8_PTR(PMHDI2C_ADDR))
+#define PMHDI2CH_REG		(REG8_PTR(PMHDI2CH_ADDR))
+#define PMADC_REG				(REG8_PTR(PMADC_ADDR))
+#define PMADCH_REG			(REG8_PTR(PMADCH_ADDR))
+
+#define PMI2C4_REG			(REG8_PTR(PMI2C4_ADDR))
+#define PMI2C4H_REG			(REG8_PTR(PMI2C4H_ADDR))
+#define PMI2C0_REG			(REG8_PTR(PMI2C0_ADDR))
+#define PMI2C0H_REG			(REG8_PTR(PMI2C0H_ADDR))
+#define PMI2C1_REG			(REG8_PTR(PMI2C1_ADDR))
+#define PMI2C1H_REG			(REG8_PTR(PMI2C1H_ADDR))
+#define PMI2C2_REG			(REG8_PTR(PMI2C2_ADDR))
+#define PMI2C2H_REG			(REG8_PTR(PMI2C2H_ADDR))
+#define PMI2C3_REG			(REG8_PTR(PMI2C3_ADDR))
+#define PMI2C3H_REG			(REG8_PTR(PMI2C3H_ADDR))
+
+#define PML2CAXI_REG	(REG8_PTR(PML2CAXI_ADDR))
+#define PML2CAXIH_REG	(REG8_PTR(PML2CAXIH_ADDR))
+#define PMPERI_REG		(REG8_PTR(PMPERI_ADDR))
+#define PMPERIH_REG		(REG8_PTR(PMPERIH_ADDR))
+#define PMTRACE_REG		(REG8_PTR(PMTRACE_ADDR))
+#define PMTRACEH_REG	(REG8_PTR(PMTRACEH_ADDR))
+#define PMDBGAPB_REG	(REG8_PTR(PMDBGAPB_ADDR))
+#define PMDBGAPBH_REG	(REG8_PTR(PMDBGAPBH_ADDR))
+#define PML2CTAG_REG	(REG8_PTR(PML2CTAG_ADDR))
+#define PML2CTAGH_REG	(REG8_PTR(PML2CTAGH_ADDR))
+#define PML2CDATA_REG	(REG8_PTR(PML2CDATA_ADDR))
+#define PML2CDATAH_REG	(REG8_PTR(PML2CDATAH_ADDR))
+
+#define PMCA9PMWDOD_REG 	(REG8_PTR(PMCA9PMWDOD_ADDR))		/* WATCH DOG RESET */
+#define PMSDPS_REG			 	(REG8_PTR(PMSDPS_ADDR))					/* SD 0~2 POWER SWITCH */
+#define PMMALIGPPWR_REG		(REG8_PTR(PMMALIGPPWR_ADDR))		/* MALI GP Power Shut Off Control and Status Register */
+#define PMWMTVDUPWR_REG		(REG8_PTR(PMWMTVDUPWR_ADDR))		/* WMT VDU Power Shut Off Control and Status Register */
+#define PMCA9C0PWR_REG	 	(REG8_PTR(PMCA9C0PWR_ADDR))	  	/* CA9 CORE 0 Power Shut Off Control and Status Register */
+#define PML2CRAMPWR_REG 	(REG8_PTR(PML2CRAMPWR_ADDR))		/* L2CRAM Power Shut Off Control and Status Register */
+#define PMNEON0PWR_REG 		(REG8_PTR(PMNEON0PWR_ADDR))		  /* NEON 0 Power Shut Off Control and Status Register */
+#define PMCA9C1PWR_REG 		(REG8_PTR(PMCA9C1PWR_ADDR))		  /* CA9 CORE 1 Power Shut Off Control and Status Register */
+#define PMNEON1PWR_REG	 	(REG8_PTR(PMNEON1PWR_ADDR))		  /* NEON 1 Power Shut Off Control and Status Register */
+#define PMC_MPWR_REG	   	(REG8_PTR(PMC_MPWR_ADDR))			  /* C&M Power Shut Off Control and Status Register */
+#define PMMALIL2CPWR_REG	(REG8_PTR(PMMALIL2CPWR_ADDR))		/* MALI L2C Power Shut Off Control and Status Register */
+#define PMMALIPP0PWR_REG	(REG8_PTR(PMMALIPP0PWR_ADDR))		/* MALI PP0 Power Shut Off Control and Status Register */
+#define PMMALIPP1PWR_REG	(REG8_PTR(PMMALIPP1PWR_ADDR))		/* MALI PP1 Power Shut Off Control and Status Register */
+#define AXI2AHB_REG     	(REG8_PTR(AXI2AHB_ADDR))				/* AXI TO AHB POWER control */
+
+/******************************************************************************
+ *
+ * Register value.
+ *
+ ******************************************************************************/
+#define PMCS_VAL			(REG32_VAL(PMCS_ADDR))/*0x00*/
+#define PMCSH_VAL			(REG32_VAL(PMCSH_ADDR))/*0x04*/
+#define PMIR_VAL			(REG8_VAL(PMIR_ADDR))/*0x08*/
+#define PMTC_VAL			(REG8_VAL(PMTC_ADDR))/*0x0C*/
+#define PMHV_VAL			(REG16_VAL(PMHV_ADDR))/*0x10*/
+#define PMHC_VAL			(REG16_VAL(PMHC_ADDR))/*0x12*/
+#define PMWS_VAL			(REG32_VAL(PMWS_ADDR))/*0x14*/
+#define PMCS2_VAL			(REG32_VAL(PMCS2_ADDR))/*0x18*/
+#define PMWE_VAL			(REG32_VAL(PMWE_ADDR))/*0x1C*/
+#define PMWT_VAL			(REG32_VAL(PMWT_ADDR))/*0x20*/
+#define PMWTC_VAL			(REG32_VAL(PMWTC_ADDR))/*0x24*/
+
+#define PMCWS_VAL			(REG32_VAL(PMCWS_ADDR))/*0x28*/
+#define PMCAD_VAL			(REG32_VAL(PMCAD_ADDR))/*0x2C*/
+
+#define HSP0_VAL			(REG32_VAL(HSP0_ADDR))/*0x30*/
+#define HSP1_VAL			(REG32_VAL(HSP1_ADDR))/*0x34*/
+#define HSP2_VAL			(REG32_VAL(HSP2_ADDR))/*0x38*/
+#define HSP3_VAL			(REG32_VAL(HSP3_ADDR))/*0x3c*/
+#define HSP4_VAL			(REG32_VAL(HSP4_ADDR))/*0x40*/
+#define HSP5_VAL			(REG32_VAL(HSP5_ADDR))/*0x44*/
+#define HSP6_VAL			(REG32_VAL(HSP6_ADDR))/*0x48*/
+#define HSP7_VAL			(REG32_VAL(HSP7_ADDR))/*0x4c*/
+#define PMRS_VAL			(REG32_VAL(PMRS_ADDR))/*0x50*/
+#define PMPB_VAL			(REG32_VAL(PMPB_ADDR))/*0x54*/
+#define DCDET_STS_VAL	(REG32_VAL(DCDET_STS_ADDR))/*0x5c*/
+#define PMSR_VAL			(REG32_VAL(PMSR_ADDR))/*0x60*/
+#define TIOUT_RST_VAL		(REG32_VAL(TIOUT_RST_ADDR))/*0x64*/
+#define BROM_PD_VAL			(REG32_VAL(BROM_PD_ADDR))/*0x68*/
+#define CA9MP_RSTC_VAL	(REG32_VAL(CA9MP_RSTC_ADDR))/*0x6C*/
+#define CA9MP_RSTS_VAL	(REG32_VAL(CA9MP_RSTS_ADDR))/*0x70*/
+
+#define PMCIS_VAL				(REG32_VAL(PMCIS_ADDR))/*0x74*/
+#define PMCIE_VAL				(REG32_VAL(PMCIE_ADDR))/*0x7C*/
+#define INT_TYPE0_VAL		(REG32_VAL(INT_TYPE0_ADDR))/*0x80*/
+#define INT_TYPE1_VAL		(REG32_VAL(INT_TYPE1_ADDR))/*0x84*/
+#define INT_TYPE2_VAL		(REG32_VAL(INT_TYPE2_ADDR))/*0x88*/
+
+#define RST_VECT_MAP_VAL	(REG32_VAL(RST_VECT_MAP_ADDR))/*0x90*/
+#define RTCCM_VAL			(REG32_VAL(RTCCM_ADDR))/*0x94*/
+#define PMSTM_VAL			(REG32_VAL(PMSTM_ADDR))/*0x98*/
+
+#define WK_EVT_TYPE_VAL	(REG32_VAL(WK_EVT_TYPE_ADDR))/*0xA0*/
+#define WK_TRG_EN_VAL		(REG32_VAL(WK_TRG_EN_ADDR))/*0xB0*/
+#define INT_TRG_EN_VAL	(REG32_VAL(INT_TRG_EN_ADDR))/*0xB4*/
+#define CA9MPC0_VAL			(REG32_VAL(CA9MPC0_ADDR))/*0xC0*/
+#define CA9MPC1_VAL			(REG32_VAL(CA9MPC1_ADDR))/*0xC4*/
+#define PWRUP_SRC_VAL		(REG32_VAL(PWRUP_SRC_ADDR))/*0xD0*/
+
+#define OSM4_VAL			(REG32_VAL(OSM4_ADDR))
+#define OSM5_VAL			(REG32_VAL(OSM5_ADDR))
+#define OSM6_VAL			(REG32_VAL(OSM6_ADDR))
+#define OSM7_VAL			(REG32_VAL(OSM7_ADDR))
+#define OSM0_VAL			(REG32_VAL(OSM0_ADDR))
+#define OSM1_VAL			(REG32_VAL(OSM1_ADDR))
+#define OSM2_VAL			(REG32_VAL(OSM2_ADDR))
+#define OSM3_VAL			(REG32_VAL(OSM3_ADDR))
+#define OSCR_VAL			(REG32_VAL(OSCR_ADDR))
+#define OSTS_VAL			(REG32_VAL(OSTS_ADDR))
+#define OSTW_VAL			(REG32_VAL(OSTW_ADDR))
+#define OSTI_VAL			(REG32_VAL(OSTI_ADDR))
+#define OSTC_VAL			(REG32_VAL(OSTC_ADDR))
+#define OSTA_VAL			(REG32_VAL(OSTA_ADDR))
+
+#define PMMISC_VAL		(REG32_VAL(PMMISC_ADDR))/*0x1FC*/
+#define PMPMA_VAL			(REG32_VAL(PMPMA_ADDR))/*0x200*/
+#define PMPMB_VAL			(REG32_VAL(PMPMB_ADDR))
+#define PMPMC_VAL			(REG32_VAL(PMPMC_ADDR))
+#define PMPMD_VAL			(REG32_VAL(PMPMD_ADDR))
+#define PMPME_VAL			(REG32_VAL(PMPME_ADDR))
+#define PMPMF_VAL			(REG32_VAL(PMPMF_ADDR))
+#define PMPMG_VAL			(REG32_VAL(PMPMG_ADDR))
+
+#define PMCEL_VAL			(REG32_VAL(PMCEL_ADDR))
+#define PMCEU_VAL			(REG32_VAL(PMCEU_ADDR))
+#define PMCE2_VAL			(REG32_VAL(PMCE2_ADDR))
+#define PMCE3_VAL			(REG32_VAL(PMCE3_ADDR))
+#define DVFSSTS_VAL   (REG32_VAL(DVFSSTS_ADDR))
+#define DVFSE0_VAL    (REG32_VAL(DVFSE0_ADDR))    
+#define DVFSE1_VAL    (REG32_VAL(DVFSE1_ADDR))    
+#define DVFSE2_VAL    (REG32_VAL(DVFSE2_ADDR))    
+#define DVFSE3_VAL    (REG32_VAL(DVFSE3_ADDR))    
+#define DVFSE4_VAL    (REG32_VAL(DVFSE4_ADDR))    
+#define DVFSE5_VAL    (REG32_VAL(DVFSE5_ADDR))    
+#define DVFSE6_VAL    (REG32_VAL(DVFSE6_ADDR))    
+#define DVFSE7_VAL    (REG32_VAL(DVFSE7_ADDR))    
+#define DVFSE8_VAL    (REG32_VAL(DVFSE8_ADDR))    
+#define DVFSE9_VAL    (REG32_VAL(DVFSE9_ADDR))    
+#define DVFSE10_VAL   (REG32_VAL(DVFSE10_ADDR))    
+#define DVFSE11_VAL   (REG32_VAL(DVFSE11_ADDR))    
+#define DVFSE12_VAL   (REG32_VAL(DVFSE12_ADDR))    
+#define DVFSE13_VAL   (REG32_VAL(DVFSE13_ADDR))    
+#define DVFSE14_VAL   (REG32_VAL(DVFSE14_ADDR))    
+#define DVFSE15_VAL   (REG32_VAL(DVFSE15_ADDR))
+
+#define PMARM_VAL				(REG8_VAL(PMARM_ADDR))
+#define PMARMH_VAL			(REG8_VAL(PMARMH_ADDR))
+#define PMAHB_VAL				(REG8_VAL(PMAHB_ADDR))
+#define PMAHBH_VAL			(REG8_VAL(PMAHBH_ADDR))
+#define PMMC_VAL				(REG8_VAL(PMMC_ADDR))
+#define PML2C_VAL				(REG8_VAL(PML2C_ADDR))
+#define PML2CH_VAL			(REG8_VAL(PML2CH_ADDR))
+
+#define PMSF_VAL				(REG8_VAL(PMSF_ADDR))
+#define PMSFH_VAL				(REG8_VAL(PMSFH_ADDR))
+#define PMAPB1_VAL			(REG8_VAL(PMMAPB1_ADDR))
+#define PMAPB1H_VAL			(REG8_VAL(PMMAPB1H_ADDR))
+#define PMAPB0_VAL			(REG8_VAL(PMAPB0_ADDR))
+#define PMAPB0H_VAL			(REG8_VAL(PMAPB0H_ADDR))
+#define PMPCM0_VAL			(REG8_VAL(PMPCM0_ADDR))
+#define PMPCM0H_VAL			(REG8_VAL(PMPCM0H_ADDR))
+#define PMPCM1_VAL			(REG8_VAL(PMPCM1_ADDR))
+#define PMPCM1H_VAL			(REG8_VAL(PMPCM1H_ADDR))
+#define PMSDMMC_VAL			(REG8_VAL(PMSDMMC_ADDR))
+#define PMSDMMCH_VAL		(REG8_VAL(PMSDMMCH_ADDR))
+#define PMMSP_VAL				(REG8_VAL(PMMSP_ADDR))
+#define PMMSPH_VAL			(REG8_VAL(PMMSPH_ADDR))
+#define PMNAND_VAL			(REG8_VAL(PMNAND_ADDR))
+#define PMNANDH_VAL			(REG8_VAL(PMNANDH_ADDR))
+#define PMXD_VAL				(REG8_VAL(PMXD_ADDR))
+#define PMXDH_VAL				(REG8_VAL(PMXDH_ADDR))
+#define PMLCD_VAL				(REG8_VAL(PMLCD_ADDR))
+#define PMLCDH_VAL			(REG8_VAL(PMLCDH_ADDR))
+#define PMSPI_VAL				(REG8_VAL(PMSPI_ADDR))
+#define PMSPIH_VAL			(REG8_VAL(PMSPIH_ADDR))
+#define PMSPI1_VAL			(REG8_VAL(PMSPI1_ADDR))
+#define PMSPI1H_VAL			(REG8_VAL(PMSPI1H_ADDR))
+#define PMSE_VAL				(REG8_VAL(PMSE_ADDR))
+#define PMSEH_VAL				(REG8_VAL(PMSEH_ADDR))
+#define PMSDMMC1_VAL		(REG8_VAL(PMSDMMC1_ADDR))
+#define PMSDMMC1H_VAL		(REG8_VAL(PMSDMMCH1_ADDR))
+#define PMPWM_VAL				(REG8_VAL(PMPWM_ADDR))
+#define PMPWMH_VAL			(REG8_VAL(PMPWMH_ADDR))
+#define PMPAXI_VAL			(REG8_VAL(PMPAXI_ADDR))
+#define PMPAXIH_VAL			(REG8_VAL(PMPAXIH_ADDR))
+#define PMWMTNA_VAL			(REG8_VAL(PMWMTNA_ADDR))
+#define PMWMTNAH_VAL		(REG8_VAL(PMWMTNAH_ADDR))
+
+#define PMNA12_VAL			(REG8_VAL(PMNA12_ADDR))
+#define PMNA12H_VAL			(REG8_VAL(PMNA12H_ADDR))
+#define PMCNMNA_VAL			(REG8_VAL(PMCNMNA_ADDR))
+#define PMCNMNAH_VAL		(REG8_VAL(PMCNMNAH_ADDR))
+#define PMWMTVDU_VAL		(REG8_VAL(PMWMTVDU_ADDR))
+#define PMWMTVDUH_VAL		(REG8_VAL(PMWMTVDUH_ADDR))
+#define PMHDMITV_VAL		(REG8_VAL(PMHDMITV_ADDR))
+#define PMHDMITVH_VAL		(REG8_VAL(PMHDMITVH_ADDR))
+#define PMDVO_VAL				(REG8_VAL(PMDVO_ADDR))
+#define PMDVOH_VAL			(REG8_VAL(PMDVOH_ADDR))
+#define PMAUDIO_VAL			(REG8_VAL(PMAUDIO_ADDR))
+#define PMAUDIOH_VAL		(REG8_VAL(PMAUDIOH_ADDR))
+#define PMCSI0_VAL			(REG8_VAL(PMCSI0_ADDR))
+#define PMCSI0H_VAL			(REG8_VAL(PMCSI0H_ADDR))
+#define PMCSI1_VAL			(REG8_VAL(PMCSI1_ADDR))
+#define PMCSI1H_VAL			(REG8_VAL(PMCSI1H_ADDR))
+
+#define PMMALI_VAL			(REG8_VAL(PMMALI_ADDR))
+#define PMMALIH_VAL			(REG8_VAL(PMMALIH_ADDR))
+#define PMCNMVDU_VAL		(REG8_VAL(PMCNMVDU_ADDR))
+#define PMCNMVDUH_VAL		(REG8_VAL(PMCNMVDUH_ADDR))
+#define PMHDI2C_VAL			(REG8_VAL(PMHDI2C_ADDR))
+#define PMHDI2CH_VAL		(REG8_VAL(PMHDI2CH_ADDR))
+#define PMADC_VAL				(REG8_VAL(PMADC_ADDR))
+#define PMADCH_VAL			(REG8_VAL(PMADCH_ADDR))
+
+#define PMI2C4_VAL			(REG8_VAL(PMI2C4_ADDR))
+#define PMI2C4H_VAL			(REG8_VAL(PMI2C4H_ADDR))
+#define PMI2C0_VAL			(REG8_VAL(PMI2C0_ADDR))
+#define PMI2C0H_VAL			(REG8_VAL(PMI2C0H_ADDR))
+#define PMI2C1_VAL			(REG8_VAL(PMI2C1_ADDR))
+#define PMI2C1H_VAL			(REG8_VAL(PMI2C1H_ADDR))
+#define PMI2C2_VAL			(REG8_VAL(PMI2C2_ADDR))
+#define PMI2C2H_VAL			(REG8_VAL(PMI2C2H_ADDR))
+#define PMI2C3_VAL			(REG8_VAL(PMI2C3_ADDR))
+#define PMI2C3H_VAL			(REG8_VAL(PMI2C3H_ADDR))
+
+#define PML2CAXI_VAL		(REG8_VAL(PML2CAXI_ADDR))
+#define PML2CAXIH_VAL		(REG8_VAL(PML2CAXIH_ADDR))
+#define PMPERI_VAL			(REG8_VAL(PMPERI_ADDR))
+#define PMPERIH_VAL			(REG8_VAL(PMPERIH_ADDR))
+#define PMTRACE_VAL			(REG8_VAL(PMTRACE_ADDR))
+#define PMTRACEH_VAL		(REG8_VAL(PMTRACEH_ADDR))
+#define PMDBGAPB_VAL		(REG8_VAL(PMDBGAPB_ADDR))
+#define PMDBGAPBH_VAL		(REG8_VAL(PMDBGAPBH_ADDR))
+#define PML2CTAG_VAL		(REG8_VAL(PML2CTAG_ADDR))
+#define PML2CTAGH_VAL		(REG8_VAL(PML2CTAGH_ADDR))
+#define PML2CDATA_VAL		(REG8_VAL(PML2CDATA_ADDR))
+#define PML2CDATAH_VAL	(REG8_VAL(PML2CDATAH_ADDR))
+
+#define PMCA9PMWDOD_VAL 	(REG8_VAL(PMCA9PMWDOD_ADDR))		/* WATCH DOG RESET */
+#define PMSDPS_VAL			 	(REG8_VAL(PMSDPS_ADDR))					/* SD 0~2 POWER SWITCH */
+#define PMMALIGPPWR_VAL		(REG8_VAL(PMMALIGPPWR_ADDR))		/* MALI GP Power Shut Off Control and Status Register */
+#define PMWMTVDUPWR_VAL		(REG8_VAL(PMWMTVDUPWR_ADDR))		/* WMT VDU Power Shut Off Control and Status Register */
+#define PMCA9C0PWR_VAL	 	(REG8_VAL(PMCA9C0PWR_ADDR))	  	/* CA9 CORE 0 Power Shut Off Control and Status Register */
+#define PML2CRAMPWR_VAL 	(REG8_VAL(PML2CRAMPWR_ADDR))		/* L2CRAM Power Shut Off Control and Status Register */
+#define PMNEON0PWR_VAL 		(REG8_VAL(PMNEON0PWR_ADDR))		  /* NEON 0 Power Shut Off Control and Status Register */
+#define PMCA9C1PWR_VAL 		(REG8_VAL(PMCA9C1PWR_ADDR))		  /* CA9 CORE 1 Power Shut Off Control and Status Register */
+#define PMNEON1PWR_VAL	 	(REG8_VAL(PMNEON1PWR_ADDR))		  /* NEON 1 Power Shut Off Control and Status Register */
+#define PMC_MPWR_VAL	   	(REG8_VAL(PMC_MPWR_ADDR))			  /* C&M Power Shut Off Control and Status Register */
+#define PMMALIL2CPWR_VAL	(REG8_VAL(PMMALIL2CPWR_ADDR))		/* MALI L2C Power Shut Off Control and Status Register */
+#define PMMALIPP0PWR_VAL	(REG8_VAL(PMMALIPP0PWR_ADDR))		/* MALI PP0 Power Shut Off Control and Status Register */
+#define PMMALIPP1PWR_VAL	(REG8_VAL(PMMALIPP1PWR_ADDR))		/* MALI PP1 Power Shut Off Control and Status Register */
+#define AXI2AHB_VAL     	(REG8_VAL(AXI2AHB_ADDR))				/* AXI TO AHB POWER control */
+#define PMDSPPWR_VAL			(REG16_VAL(PMDSPPWR_ADDR))
+
+/*
+ * (URRDR) Receive Data Regiser Description
+ */
+#define URRDR_PER               0x100   /* Parity Error. This bit is the same as URISR[8] */
+#define URRDR_FER               0x200   /* Frame Error. This bit is the same as URISR[9] */
+
+/******************************************************************************
+ *
+ * PMCS_REG     PM (Current) Status Register bits definitions.
+ *
+ ******************************************************************************/
+#define PMCS_NORTC              BIT0    /* RTC Clock Logic Disabled       */
+#define PMCS_IDLE               BIT1    /* IDLE Operation Active          */
+#define PMCS_HIBER              BIT2    /* Hibernation Operation Active   */
+#define PMCS_ANY_CLK_DIV        BIT4    /* Updating Any Clock Divisor     */
+#define PMCS_ANY_PLL_MUL        BIT5    /* Updating Any PLL Multiplier    */
+#define PMCS_ZAC2               BIT8    /* Updating ZAC2_MA Clock Divisor */
+#define PMCS_AHB                BIT9    /* Updating AHB Clock Divisor     */
+#define PMCS_DSP                BIT10   /* Updating DSP Clock Divisor     */
+#define PMCS_LCD                BIT11   /* Updating LCD Clock Divisor     */
+#define PMCS_MC                 BIT12   /* Updating Memory Controller Clock Divisor */
+#define PMCS_CFC                BIT13   /* Updating Compact Flash Controller Clock Divisor */
+#define PMCS_USB                BIT14   /* Updating USB Clock Divisor     */
+#define PMCS_PCM                BIT15   /* Updating Pulse Code Modulation Clock Divisor */
+#define PMCS_PLLA               BIT16   /* Updating PLL A Multiplier Value */
+#define PMCS_PLLB               BIT17   /* Updating PLL B Multiplier Value */
+#define PMCS_PLLC               BIT18   /* Updating PLL C Multiplier Value */
+#define PMCS_SF                 BIT19   /* Updating Serial Flash Memory Cntrlr Divisor */
+#define PMCS_PATA               BIT21   /* Updating PATA Clock Divisor     */
+#define PMCS_SDMMC              BIT22   /* Updating SD/MMC Clock Divisor   */
+#define PMCS_MSC                BIT23   /* Updating MS/MSPRO Clock Divisor */
+#define PMCS_LPC                BIT24   /* Updating LPC Memory Cntrlr Clock Divisor */
+#define PMCS_NAND               BIT25   /* Updating NAND Clock Divisor     */
+#define PMCS_SPI                BIT26   /* Updating SPI Clock Divisor      */
+#define PMCS_PLLD               BIT27   /* Updating PLL D Multiplier Value */
+#define PMCS_BUSY               0xfffffffe
+
+/******************************************************************************
+ *
+ * PMIR_REG     PM Idle processor Request Register bit function.
+ *
+ ******************************************************************************/
+#define PMIR_IDLE                       /* IDLE Processor Request Bit */
+
+
+/******************************************************************************
+ *
+ * PMHC_REG     PM Hibernation Control Register bits functions.
+ *
+ ******************************************************************************/
+#define PMHC_SLEEP              0x03   /* A Power-on Hibernation Mode  */
+#define PMHC_SUSPEND            0x201   /* A Power-off Hibernation Mode */
+#define PMHC_SHUTDOWN           0x05   /* A Power-off Hibernation Mode */
+#define PMHC_25M_OSCLR          BIT8    /* 25MHz Oscillator Enable      */
+
+/******************************************************************************
+ *
+ * PMWS_REG     PM Wake-up Status register bits definitions.
+ *
+ ******************************************************************************/
+#define PMWS_WAKEMASK           0xFF    /* General Purpose Wake-up Status */
+#define PMWS_PWRBUTTON          BIT14   /* Power Button Wake-up Status    */
+#define PMWS_RTC                BIT15   /* RTC Wake-up Status             */
+
+/******************************************************************************
+ *
+ * PMWE_REG     PM Wake-up event Enable Register bits functions.
+ *
+ ******************************************************************************/
+#define PMWE_WAKEMASK           0xFF                    /* General Purpose Wake-up Enable */
+#define PMWE_WAKEUP(x)          (BIT0 << ((x) & 0x7))   /* Genaral Wake-up 0-7 Enable     */
+#define PMWE_RTC                BIT15                   /* RTC Wake-up Enable             */
+
+/******************************************************************************
+ *
+ * PMWT_REG     PM Wake-up event Type Register bits functions.
+ *
+ ******************************************************************************/
+#define PMWT_ZERO               0x00            /* Wake-up signal is a zero */
+#define PMWT_ONE                0x01            /* Wake-up signal is a one  */
+#define PMWT_FALLING            0x02            /* Wake-up signal generates a falling edge */
+#define PMWT_RISING             0x03            /* Wake-up signal generates a rising edge  */
+#define PMWT_EDGE               0x04            /* Wake-up signal generates an edge        */
+
+#define PMWT_TYPEMASK           0xFF   /* Wake-up event Type Mask                 */
+
+#define PMWT_WAKEUP0(x) (((x) & PMWT_TYPEMASK) << 0)  /* General Purpose Wake-up 0 Type bits */
+
+#define PMWT_WAKEUP1(x) (((x) & PMWT_TYPEMASK) << 4)  /* General Purpose Wake-up 1 Type bits */
+
+#define PMWT_WAKEUP2(x) (((x) & PMWT_TYPEMASK) << 8)  /* General Purpose Wake-up 2 Type bits */
+
+#define PMWT_WAKEUP3(x) (((x) & PMWT_TYPEMASK) << 12) /* General Purpose Wake-up 3 Type bits */
+
+#define PMWT_WAKEUP4(x) (((x) & PMWT_TYPEMASK) << 16) /* General Purpose Wake-up 4 Type bits */
+
+#define PMWT_WAKEUP5(x) (((x) & PMWT_TYPEMASK) << 20) /* General Purpose Wake-up 5 Type bits */
+
+#define PMWT_WAKEUP6(x) (((x) & PMWT_TYPEMASK) << 24) /* General Purpose Wake-up 6 Type bits */
+
+#define PMWT_WAKEUP7(x) (((x) & PMWT_TYPEMASK) << 28) /* General Purpose Wake-up 7 Type bits */
+
+#define PMWT_WAKEUPMASK         0x07            /* Max wakeup source number                */
+
+#define PMWT_WAKEUP(src, type)  ((type & PMWT_TYPEMASK) << ((src & PMWT_WAKEUPMASK) * 4))
+
+/******************************************************************************
+ *
+ * PMRS_REG     PM Reset Status Register bits definitions.
+ *
+ ******************************************************************************/
+#define PMRS_PMR                BIT0    /* Power Managment Reset  */
+#define PMRS_IOR                BIT1    /* I/O normal power Reset */
+#define PMRS_HBR                BIT2    /* HiBernation Reset      */
+#define PMRS_WDR                BIT3    /* WatchDog Reset         */
+#define PMRS_SWR                BIT4    /* SoftWare Reset         */
+#define PMRS_SHR                BIT5    /* Shutdown Reset         */
+#define PMRS_PGR                BIT6    /* Power good reset       */
+/* Bits 7-31: Reserved */
+
+/******************************************************************************
+ *
+ * PMPB_REG     PM Power Button Control Register
+ *
+ ******************************************************************************/
+#define PMPB_SOFTPWR            BIT0    /* Soft Power Enable      */
+#define PMPB_DEBOUNCE(x)		(((x) & 0xFF) << 16) /* PWRBTN debounce value unit ~ 32ms*/
+/* Bits 1-31: Reserved */
+
+/******************************************************************************
+ *
+ * PMSR_REG     PM Software Reset request Register bit function.
+ *
+ ******************************************************************************/
+#define PMSR_SWR                BIT0    /* SoftWare Reset request */
+/* Bits 1-31: Reserved */
+
+/******************************************************************************
+ *
+ * PMPATA_REG   PM PATA Interface Drive Strength Register (8-bit Register)
+ *
+ ******************************************************************************/
+#define PMPATA_ONETHIRD         0x00    /* One-third Drive Strength */
+#define PMPATA_ONEHALF          0x01    /* One-half Drive Strength  */
+#define PMPATA_TWOTHIRD         0x02    /* Two-third Drive Strength */
+#define PMPATA_FULL             0x03    /* Full Drive Strength      */
+#define PMSR_SWR                BIT0    /* SoftWare Reset request */
+/* Bits 2-7: Reserved */
+
+/******************************************************************************
+ *
+ * OSTS_REG     OS Timer Status Register bits definitions.
+ *
+ ******************************************************************************/
+#define OSTS_M0                 BIT0    /* OS Timer 0 Match detected */
+#define OSTS_M1                 BIT1    /* OS Timer 1 Match detected */
+#define OSTS_M2                 BIT2    /* OS Timer 2 Match detected */
+#define OSTS_M3                 BIT3    /* OS Timer 3 Match detected */
+#define OSTS_MASK               0xF
+/* Bits 4-31: Reserved */
+
+/******************************************************************************
+ *
+ * OSTW_REG     OS Timer Watchdog enable Register bit function.
+ *
+ ******************************************************************************/
+#define OSTW_WE                 BIT0    /* OS Timer Channel 0 Watchdog Enable */
+/* Bits 1-31: Reserved */
+
+/******************************************************************************
+ *
+ * OSTI_REG     OS Timer Interrupt enable Register bits functions.
+ *
+ ******************************************************************************/
+#define OSTI_E0                 BIT0    /* OS Timer Channel 0 Interrupt Enable */
+#define OSTI_E1                 BIT1    /* OS Timer Channel 0 Interrupt Enable */
+#define OSTI_E2                 BIT2    /* OS Timer Channel 0 Interrupt Enable */
+#define OSTI_E3                 BIT3    /* OS Timer Channel 0 Interrupt Enable */
+/* Bits 4-31: Reserved */
+/******************************************************************************
+ *
+ * OSTC_REG     OS Timer Control Register bits functions.
+ *
+ ******************************************************************************/
+#define OSTC_ENABLE             BIT0    /* OS Timer Enable bit             */
+#define OSTC_RDREQ              BIT1    /* OS Timer Read Count Request bit */
+/* Bits 2-31: Reserved */
+
+/******************************************************************************
+ *
+ * OSTA_REG     OS Timer Access status Register bits definitions.
+ *
+ ******************************************************************************/
+#define OSTA_MWA0               BIT0    /* OS Timer Match 0 Write Active */
+#define OSTA_MWA1               BIT1    /* OS Timer Match 1 Write Active */
+#define OSTA_MWA2               BIT2    /* OS Timer Match 2 Write Active */
+#define OSTA_MWA3               BIT3    /* OS Timer Match 3 Write Active */
+#define OSTA_CWA                BIT4    /* OS Timer Count Write Active   */
+#define OSTA_RCA                BIT5    /* OS Timer Read Count Active    */
+/* Bits 6-31: Reserved */
+
+/******************************************************************************
+ *
+ * PMMISC_REG   PM Miscellaneous Clock Controls Register
+ *
+ ******************************************************************************/
+#define PMMISC_24MHZ            BIT0    /* 24MHz Clock Source            */
+/* Bits 1-31: Reserved */
+
+/******************************************************************************
+ *
+ * Miscellaneous definitions
+ *
+ ******************************************************************************/
+#define __OST_BASE              0xD8130100      /* OS Timers base address */
+#define OST_MAX_CHANNEL         4               /* Four channels OS Timer */
+
+#if 1
+typedef struct _PMC_REG_ {
+	volatile unsigned int PM_Div_Upt0_sts; /* [Rx00-03] Device clock update status 0 Register*/
+	volatile unsigned int PM_Div_Upt1_sts; /* [Rx04-07] Device clock update status 1 Register*/
+	volatile unsigned char Idle;/* [Rx08] IDEL Processor Request Register*/
+	volatile unsigned char Resv9_0B[3];/* [Rx09 - 0B] Reserved*/
+	volatile unsigned short PU_Time_Ctrl;/* [Rx0C] Power-up Tme Control Register*/
+	volatile unsigned char Resv0E_0F[2];/* Reserved*/
+	volatile unsigned short Hib_Val;/* [Rx10 - Rx11] Hibernation Value Register*/
+	volatile unsigned short Hib_Ctrl;/* [Rx12 - Rx13] Hibernation Control Register*/
+	volatile unsigned int Wakeup_Sts;/* [Rx14-17]Wake up Status register*/
+	volatile unsigned int PM_Sts;/* [Rx18-1B] Power Management Status Register*/
+	volatile unsigned int Wakeup_Event_Enable;/* [Rx1C-1F] Wake-up Event Enable Register*/
+	volatile unsigned int Wakeup_Event_Type;/* [Rx20-23] Wake-up Event Type Register*/
+	volatile unsigned int Wakeup_CardDet_Event_Type;/* [Rx24-27] Card Detect Wake-up Event Type Register*/
+	volatile unsigned int CardDet_Sts_Int;/* [Rx28-2B] Card Detect Status And Card Detect Interrupt Register*/
+	volatile unsigned int CardReader_Debounce_Int_Type;/* [Rx2C-2F] Card Reader Attachment Debounce Control and Interrupt Type Register*/
+	volatile unsigned int Hib_Scratch0;/* [Rx30-33] Hibernate Scratch Pad Register0*/
+	volatile unsigned int Hib_Scratch1;/* [Rx34-37] Hibernate Scratch Pad Register1*/
+	volatile unsigned int Hib_Scratch2;/* [Rx38-3B] Hibernate Scratch Pad Register2*/
+	volatile unsigned int Hib_Scratch3;/* [Rx3c-3F] Hibernate Scratch Pad Register3*/
+	volatile unsigned int Hib_Scratch4;/* [Rx40-43] Hibernate Scratch Pad Register4*/
+	volatile unsigned int Hib_Scratch5;/* [Rx44-47] Hibernate Scratch Pad Register5*/
+	volatile unsigned int Hib_Scratch6;/* [Rx48-4B] Hibernate Scratch Pad Register6*/
+	volatile unsigned int Hib_Scratch7;/* [Rx4c-4F] Hibernate Scratch Pad Register7*/
+	volatile unsigned int Reset_Sts;/* [Rx50-53] Reset Status Register*/
+	volatile unsigned int PB_Control;/* [Rx54-57] Power Button Control Register;*/
+	volatile unsigned int AXI_LowPwr_Control;/* [Rx58-5B] AXI Low Power Interface Control Register;*/
+	volatile unsigned int Resv5c_5F[1];
+	volatile unsigned int SW_Reset_Req;/* [Rx60-63] Software Reset Request Register*/
+	volatile unsigned int Tout_Rstart;/* [Rx64-67] time out restart Control Register */
+	volatile unsigned int Broom_Powerdown;/* [Rx68-69] bootroom Powerdown, Cache-As-Ram, L2C RAM power force on, L2C bypass control*/
+	volatile unsigned char Resv6A_6B[0x2];
+	volatile unsigned int CA9MP_Sft_Rst_Ctrl;/* [Rx6C-6F] CA9MP soft reset control */
+	volatile unsigned int CA9MP_Sft_Rst_Sts;/* [Rx70-73] CA9MP soft reset ststus */
+	volatile unsigned int Int_Wak_Sts;/* [Rx74-77] interrupt status from wakeup source */
+	volatile unsigned int Resv78_7B[0x1];
+	volatile unsigned int Int_Wak_En;/* [Rx7C-7F] interrupt Enable from wakeup source */
+	volatile unsigned int Int_Wak_Type0;/* [Rx80-83] interrupt type0 from wakeup source */
+	volatile unsigned int Int_Wak_Type1;/* [Rx84-87] interrupt type1 from wakeup source */
+	volatile unsigned int Int_Wak_Type2;/* [Rx88-8B] interrupt type2 from wakeup source */
+	volatile unsigned int Resv8C_8F[0x1];
+	volatile unsigned int Rst_Vector_Rmap;/* [Rx90-93] Reset vector remap address register */
+	volatile unsigned int RTC_Clk_Exist_Monitor; /* [Rx94-97] RTC clock exist monitor Register */
+	volatile unsigned int Suspend_To_Dram_En; /* [Rx98-9B] suspend to DRAM enable register */
+	volatile unsigned char Resv9C_9F[0x4];
+	volatile unsigned int Wak_Event_Type; /* [RxA0-A3] wake event type for USBSW0, CIR ..*/
+	volatile unsigned int ResvA4_AC[0x3];
+	volatile unsigned int Wak_Trig_En; /* [RxB0-B3] wake triggle enable */
+	volatile unsigned int Int_Trig_En; /* [RxB4-B7] interrupt triggle enable */
+	volatile unsigned int ResvB8_BF[0x2];
+	volatile unsigned int CA9MP_Core0_Retvec; /* [RxC0-C3] CA9MP core 0 retvec register */
+	volatile unsigned int CA9MP_Core1_Retvec; /* [RxC4-C7] CA9MP core 1 retvec register */
+	volatile unsigned char PU_Src_Sts; /* [RxD0] Power up Source Status register */
+	volatile unsigned char ResvD1_EF[0x1F];
+	volatile unsigned int OS_Timer_Match4;/* [RxF0-RxF3] OS Timer Match Register4*/
+	volatile unsigned int OS_Timer_Match5;/* [RxF4-RxF7] OS Timer Match Registe5*/
+	volatile unsigned int OS_Timer_Match6;/* [RxF8-RxFB] OS Timer Match Register6*/
+	volatile unsigned int OS_Timer_Match7;/* [RxFC-RxFF] OS Timer Match Register7*/
+	volatile unsigned int OS_Timer_Match0;/* [Rx100-Rx103] OS Timer Match Register0*/
+	volatile unsigned int OS_Timer_Match1;/* [Rx104-Rx107] OS Timer Match Registe1*/
+	volatile unsigned int OS_Timer_Match2;/* [Rx108-Rx10B] OS Timer Match Register2*/
+	volatile unsigned int OS_Timer_Match3;/* [Rx10C-Rx10F] OS Timer Match Register3*/
+	volatile unsigned int OS_Timer_Count;/* [Rx110-113] OS Timer Counter Register*/
+	volatile unsigned int OS_Timer_Sts;/* [Rx114-117] OS Timer Status Register*/
+	volatile unsigned int OS_Timer_WatchDog_Enable;/* [Rx118-Rx11B]*/
+	volatile unsigned int OS_Timer_Int_Enable;/* [Rx11C-Rx11F]*/
+	volatile unsigned int OS_Timer_Ctrl;/* [Rx120-Rx123] OS Timer Control Register*/
+	volatile unsigned int OS_Timer_Access_Sts;/* [Rx124-Rx127] OS Timer Access Status Register*/
+	volatile unsigned int Resv128_1FB[0x35];
+	volatile unsigned int Misc_Clk_Ctrl;/* [Rx1FC-Rx1FF] miscellaneous clock controls register*/
+	volatile unsigned int PLLA;/* [Rx200-203] PLLA Multiplier and Range Values Register*/
+	volatile unsigned int PLLB;/* [Rx204-207] PLLB Multiplier and Range Values Register*/
+	volatile unsigned int PLLC;/* [Rx208-20B] PLLC Multiplier and Range Values Register*/
+	volatile unsigned int PLLD;/* [Rx20C-20F] PLLD Multiplier and Range Values Register*/
+	volatile unsigned int PLLE;/* [Rx210-213] PLLE Multiplier and Range Values Register*/
+	volatile unsigned int PLLF;/* [Rx214-217] PLLF Multiplier and Range Values Register*/
+	volatile unsigned int PLLG;/* [Rx218-21B] PLLG Multiplier and Range Values Register*/
+	volatile unsigned int PLL_AUD;/* [Rx21C-21F] PLL_AUD Multiplier and Range Values Register*/
+	volatile unsigned int PLL_Rdy_Sts;/* [Rx220-223] PLL Ready Status Register*/
+	volatile unsigned int Resv224_24F[0x0B];
+	volatile unsigned int Clock_Enable0;/* [Rx250-253] Clock Enable 0 Register*/
+	volatile unsigned int Clock_Enable1;/* [Rx254-257] Clock Enable 1 Register*/
+	volatile unsigned int Clock_Enable2;/* [Rx258-25B] Clock Enable 2 Register*/
+	volatile unsigned int Clock_Enable3;/* [Rx25C-25F] Clock Enable 3 Register*/
+	volatile unsigned int DVFS_Sts;/* [Rx260-263] DVFS Status Register*/
+	volatile unsigned int Resv264_27F[0x7];
+	volatile unsigned int DVFS_Entry0;/* [Rx280-283] DVFS Entry 0 Register*/
+	volatile unsigned int DVFS_Entry1;/* [Rx284-287] DVFS Entry 1 Register*/
+	volatile unsigned int DVFS_Entry2;/* [Rx288-28B] DVFS Entry 2 Register*/
+	volatile unsigned int DVFS_Entry3;/* [Rx28C-28F] DVFS Entry 3 Register*/
+	volatile unsigned int DVFS_Entry4;/* [Rx290-293] DVFS Entry 4 Register*/
+	volatile unsigned int DVFS_Entry5;/* [Rx294-297] DVFS Entry 5 Register*/
+	volatile unsigned int DVFS_Entry6;/* [Rx298-29B] DVFS Entry 6 Register*/
+	volatile unsigned int DVFS_Entry7;/* [Rx29c-29F] DVFS Entry 7 Register*/
+	volatile unsigned int DVFS_Entry8;/* [Rx2A0-2A3] DVFS Entry 8 Register*/
+	volatile unsigned int DVFS_Entry9;/* [Rx2A4-2A7] DVFS Entry 9 Register*/
+	volatile unsigned int DVFS_Entry10;/* [Rx2A8-2AB] DVFS Entry 10 Register*/
+	volatile unsigned int DVFS_Entry11;/* [Rx2AC-2AF] DVFS Entry 11 Register*/
+	volatile unsigned int DVFS_Entry12;/* [Rx2B0-2B3] DVFS Entry 12 Register*/
+	volatile unsigned int DVFS_Entry13;/* [Rx2B4-2B7] DVFS Entry 13 Register*/
+	volatile unsigned int DVFS_Entry14;/* [Rx2B8-2BB] DVFS Entry 14 Register*/
+	volatile unsigned int DVFS_Entry15;/* [Rx2BC-2BF] DVFS Entry 15 Register*/
+	volatile unsigned int Resv2C0_2FF[0x10];
+	volatile unsigned char ARM_Clock_Divisor;/* [Rx300] ARM Clock Divisor Register*/
+	/* [Rx301] ARM Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char ARM_Clock_HiPulse;
+	volatile unsigned char Resv302_303[2];
+	volatile unsigned char AHB_Clock_Divisor;/* [Rx304] AHB Clock Divisor Value Register*/
+	volatile unsigned char Resv305_30B[7];
+	volatile unsigned char L2C_Clock_Divisor;/* [Rx30C] Clock Divisor Value L2C Register*/
+	volatile unsigned char L2C_Clock_HiPulse;
+	volatile unsigned char Resv30E_30F[2];
+	/* [Rx310] DDR Memory Controller Clock Divisor Value Register*/
+	volatile unsigned char DDR_Clock_Divisor;
+	volatile unsigned char Resv311_313[3];
+	/* [Rx314] Serial Flash Memory Controller Clock Divisor Value Register*/
+	volatile unsigned char SF_Clock_Divisor;
+	volatile unsigned char SF_Clock_HiPulse;/* [Rx315]*/
+	volatile unsigned char Resv316_317[2];
+	volatile unsigned char NF_Clock_Divisor;/* [Rx318] NF Clock Divisor Value Register*/
+	volatile unsigned char NF_Clock_HiPulse;/* [Rx319]*/
+	volatile unsigned char Resv31A_31B[2];
+	volatile unsigned char NOR_Clock_Divisor;/* [Rx31C] NOR Clock Divisor Value Register*/
+	volatile unsigned char NOR_Clock_HiPulse;/* [Rx31D]*/
+	volatile unsigned char Resv31E_31F[2];
+	volatile unsigned char APB_Clock_Divisor;/* [Rx320] APB Clock Divisor Value Register*/
+	volatile unsigned char Resv321_323[3];
+	volatile unsigned char PCM0_Clock_Divisor;/* [Rx324] PCM0 Clock Divisor Value Reigster*/
+	volatile unsigned char PCM0_Clock_HiPulse;/* [Rx325]*/
+	volatile unsigned char Resv326_327[2];
+	volatile unsigned char PCM1_Clock_Divisor;/* [Rx328] PCM1 Clock Divisor Value Reigster*/
+	volatile unsigned char PCM1_Clock_HiPulse;/* [Rx329]*/
+	volatile unsigned char Resv32A_32B[2];
+	volatile unsigned char Resv32C_32F[4];
+	volatile unsigned char SD_Clock_Divisor;/* [Rx330] SD/MMC Clock Divisor Value Reigster*/
+	volatile unsigned char SD_Clock_HiPulse;/* [Rx331]*/
+	volatile unsigned char Resv332_333[2];
+	volatile unsigned char SD1_Clock_Divisor;/* [Rx334] SD/MMC1 Clock Divisor Value Reigster*/
+	volatile unsigned char SD1_Clock_HiPulse;/* [Rx335]*/
+	volatile unsigned char Resv336_337[2];
+	volatile unsigned char SD2_Clock_Divisor;/* [Rx338] SD/MMC2 Clock Divisor Value Reigster*/
+	volatile unsigned char SD2_Clock_HiPulse;/* [Rx339]*/
+	volatile unsigned char Resv33A_33B[2];
+	volatile unsigned char Resv33C_33F[4];
+	volatile unsigned char SPI0_Clock_Divisor;/* [Rx340] SPI0 Clock Divisor Value Register*/
+	/* [Rx341] SPI0 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char SPI0_Clock_HiPulse;
+	volatile unsigned char Resv342_343[2];
+	volatile unsigned char SPI1_Clock_Divisor;/* [Rx344] SPI1 Clock Divisor Value Register*/
+	/* [Rx345] SPI1 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char SPI1_Clock_HiPulse;
+	volatile unsigned char Resv346_347[2];
+	volatile unsigned char SE_Clock_Divisor;/* [Rx348] SE Clock Divisor Value Register*/
+	/* [Rx349] SE Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char SE_Clock_HiPulse;
+	volatile unsigned char Resv34A_34F[6];
+	volatile unsigned char PWM_Clock_Divisor;/* [Rx350] PWM Clock Divisor Register*/
+	volatile unsigned char PWM_Clock_HiPulse;/* [Rx351] PWM Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv352_353[2];
+	volatile unsigned char PAXI_Clock_Divisor;/* [Rx354] PAXI Clock Divisor Value Register*/
+	volatile unsigned char PAXI_Clock_HiPulse;/* [Rx355] PAXI Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv356_357[2];
+	volatile unsigned char WMT_NA_Clock_Divisor;/* [Rx358]*/
+	volatile unsigned char WMT_NA_Clock_HiPulse;/* [Rx359] WMT NA0 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv35A_35B[2];
+	volatile unsigned char NA12_Clock_Divisor;/* [Rx35C]*/
+	volatile unsigned char NA12_Clock_HiPulse;/* [Rx35D] NA12 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv35E_35F[2];
+	volatile unsigned char CNM_NA_Clock_Divisor;/* [Rx360]*/
+	volatile unsigned char CNM_NA_Clock_HiPulse;/* [Rx361] CNM NA Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv362_367[6];
+	volatile unsigned char WMT_VDU_Clock_Divisor;/* [Rx368]*/
+	volatile unsigned char WMT_VDU_Clock_HiPulse;/* [Rx369] WMT VDU Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv36A_36B[2];
+	volatile unsigned char DVOTV2_Clock_Divisor;/* [Rx36C]*/
+	volatile unsigned char DVOTV2_Clock_HiPulse;/* [Rx36D] DVOTV2 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char TV2_Encoder_En;/* [Rx36E]*/
+	volatile unsigned char Resv36F[1];
+	volatile unsigned char DVO2_Clock_Divisor;/* [Rx370]*/
+	volatile unsigned char DVO2_Clock_HiPulse;/* [Rx371] DVO2 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv372_373[2];
+	volatile unsigned char AUD_Clock_Divisor;/* [Rx374] AUD Clock Divisor Value Register*/
+	volatile unsigned char AUD_Clock_HiPulse;/* [Rx375] AUD Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv376_377[2];
+	volatile unsigned char Ring1_Clock_Divisor;/* [Rx378] Ring OSC 1st divider Register*/
+	volatile unsigned char Resv379_37B[3];
+	volatile unsigned char Ring2_Clock_Divisor;/* [Rx37C] Ring OSC 2st divider Register*/
+	volatile unsigned char Resv37D_37F[3];
+	volatile unsigned char CSI0_Clock_Divisor;/* [Rx380]*/
+	volatile unsigned char CSI0_Clock_HiPulse;/* [Rx381] CSI0 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv382_383[2];
+	volatile unsigned char CSI1_Clock_Divisor;/* [Rx384]*/
+	volatile unsigned char CSI1_Clock_HiPulse;/* [Rx385] CSI1 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv386_387[2];
+	volatile unsigned char MALI_Clock_Divisor;/* [Rx388]*/
+	volatile unsigned char MALI_Clock_HiPulse;/* [Rx389] MALI Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv38A_38B[2];
+	volatile unsigned char CNM_VDU_Clock_Divisor;/* [Rx38C]*/
+	volatile unsigned char CNM_VDU_Clock_HiPulse;/* [Rx38D] CNM VDU Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv38E_38F[2];
+	volatile unsigned char HDMI_I2C_Clock_Divisor;/* [Rx390]*/
+	volatile unsigned char HDMI_I2C_Clock_HiPulse;/* [Rx391] HDMI Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv392_393[2];
+	volatile unsigned char ADC_Clock_Divisor;/* [Rx394] ADC Clock Divisor Value Register*/
+	volatile unsigned char ADC_Clock_HiPulse;/* [Rx395]*/
+	volatile unsigned char Resv396_39F[6];
+	volatile unsigned char I2C4_Clock_Divisor;/* [Rx39C]*/
+	volatile unsigned char I2C4_Clock_HiPulse;/* [Rx39D] I2C4 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv39E_39F[2];
+	volatile unsigned char I2C0_Clock_Divisor;/* [Rx3A0]*/
+	volatile unsigned char I2C0_Clock_HiPulse;/* [Rx3A1] I2C0 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3A2_3A3[2];
+	volatile unsigned char I2C1_Clock_Divisor;/* [Rx3A4]*/
+	volatile unsigned char I2C1_Clock_HiPulse;/* [Rx3A5] I2C1 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3A6_3A7[2];
+	volatile unsigned char I2C2_Clock_Divisor;/* [Rx3A8]*/
+	volatile unsigned char I2C2_Clock_HiPulse;/* [Rx3A9] I2C2 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3AA_3AB[2];
+	volatile unsigned char I2C3_Clock_Divisor;/* [Rx3AC]*/
+	volatile unsigned char I2C3_Clock_HiPulse;/* [Rx3AD] I2C3 Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3AE_3AF[2];
+	volatile unsigned char L2C_AXI_Clock_Divisor;/* [Rx3B0]*/
+	volatile unsigned char L2C_AXI_Clock_HiPulse;/* [Rx3B1] L2C_AXI Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3B2_3B3[2];
+	volatile unsigned char ATCLK_Clock_Divisor;/* [Rx3B4]*/
+	volatile unsigned char ATCLK_Clock_HiPulse;/* [Rx3B5] ATCLK Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3B6_3B7[2];
+	volatile unsigned char PERICLK_Clock_Divisor;/* [Rx3B8]*/
+	volatile unsigned char PERICLK_Clock_HiPulse;/* [Rx3B9] PERICLK Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3BA_3BB[2];
+	volatile unsigned char TRACECLK_Clock_Divisor;/* [Rx3BC]*/
+	volatile unsigned char TRACECLK_Clock_HiPulse;/* [Rx3BD] TRACECLK Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3BE_3BF[2];
+	volatile unsigned char Resv3C0_3CF[0x10];
+	volatile unsigned char DBUG_APB_Clock_Divisor;/* [Rx3D0]*/
+	volatile unsigned char DBUG_APB_Clock_HiPulse;/* [Rx3D1] DBUG APB Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3D2_3D3[2];
+	volatile unsigned char Resv3D4_3E3[0x10];
+	volatile unsigned char Hz24M_Clock_Divisor;/* [Rx3E4]*/
+	volatile unsigned char Hz24M_Clock_HiPulse;/* [Rx3E5] 24MHZ Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3E6_3EF[10];
+	volatile unsigned char L2C_TAG_Clock_Divisor;/* [Rx3F0]*/
+	volatile unsigned char L2C_TAG_Clock_HiPulse;/* [Rx3F1] L2C_TAG Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3F2_3F3[2];
+	volatile unsigned char L2C_DATA_Clock_Divisor;/* [Rx3F4]*/
+	volatile unsigned char L2C_DATA_Clock_HiPulse;/* [Rx3F5] L2C_DATA Clock High Pulse is the Wide Pulse Register*/
+	volatile unsigned char Resv3F6_47F[0x8A];
+	volatile unsigned char CA9MP_Watchdog_Rst_Ctrl;/* [Rx480]*/
+	volatile unsigned char Resv481_4FF[0x7F];
+	volatile unsigned char PS_Control;/* [Rx500] 1.1.1.85	CARD, SD0~2 Power Switch Control Register*/
+	volatile unsigned char Resv501[0xFF];
+	volatile unsigned int MALI_GP_PWR_Shut_Off_CTRL_STS;/* [Rx600-603] mali GP power shut off control and status Register*/
+	volatile unsigned int WMT_VDU_PWR_Shut_Off_CTRL_STS;/* [Rx604-607] WMT VDU power shut off control and status Register*/
+	volatile unsigned int CA9MP_CORE0_PWR_Shut_Off_CTRL_STS;/* [Rx608-60B] CA9MP CORE0 power shut off control and status Register*/
+	volatile unsigned int L2C_DATA_PWR_Shut_Off_CTRL_STS;/* [Rx60C-60F] L2C DATA power shut off control and status Register*/
+	volatile unsigned int NEON0_PWR_Shut_Off_CTRL_STS;/* [Rx610-613] NEON0 power shut off control and status Register*/
+	volatile unsigned int CA9MP_CORE1_PWR_Shut_Off_CTRL_STS;/* [Rx614-617] CA9MP CORE1 power shut off control and status Register*/
+	volatile unsigned int NEON1_PWR_Shut_Off_CTRL_STS;/* [Rx618-61B] NEON1 power shut off control and status Register*/
+	volatile unsigned int CNM_NA_PWR_Shut_Off_CTRL_STS;/* [Rx61C-61F] C&M NA power shut off control and status Register*/
+	volatile unsigned int MALI_L2C_PWR_Shut_Off_CTRL_STS;/* [Rx620-623] mali L2C power shut off control and status Register*/
+	volatile unsigned int MALI_PP0_PWR_Shut_Off_CTRL_STS;/* [Rx624-627] mali PP0 power shut off control and status Register*/
+	volatile unsigned int MALI_PP1_PWR_Shut_Off_CTRL_STS;/* [Rx628-62B] mali PP1 power shut off control and status Register*/
+	volatile unsigned char Resv62C_64F[0x24];
+	volatile unsigned int AXI_TO_AHB_Bridge_Pwr_Ctrl;/* [Rx650-653] AXI to AHB bridge power control and status Register*/
+	volatile unsigned int PAXI_TO_AHB_Bridge_Pwr_Ctrl;/* [Rx654-657] PAXI to AHB bridge power control and status Register*/
+} PMC_REG, *PPMC_REG;
+#endif
+
+/******************************************************************************
+ *
+ * clock enable/disbale macro define
+ * CLOCKSET(CLOCK_BIT,CLOCK_SET) 
+ * example:
+ * CLOCKSET(UART3_CB,EN_C);  --> enable uart3 clock
+ * CLOCKSET(UART3_CB,DIS_C); --> disable uart3 clock
+ *
+ ******************************************************************************/
+
+#if 0
+enum CLOCK_BIT {
+	I2C1_CB			= 0,	/* I2C1 clock					*/
+	UART0_CB,					/* UART0 Clock				*/
+	UART1_CB,					/* UART1 Clock				*/
+	UART2_CB,					/* UART2 Clock				*/
+	UART3_CB,					/* UART3 Clock				*/
+	I2C0_CB,					/* I2C0 clock					*/
+	RTC_CB			= 7,	/* RTC clock					*/
+	KEYPAD_CB		= 9,	/* KEYPAD clock				*/
+	PWM_CB,						/* PWM clock					*/
+	GPIO_CB,					/* GPIO clock					*/
+	SPI0_CB,					/* SPI0 clock					*/
+	SPI1_CB,					/* SPI1 clock					*/
+	AHB1_CB			=15,	/* AHB1 clock					*/
+	I2S_CB,						/* I2S clock					*/
+	CIR_CB,						/* CIR clock					*/
+	DVO_CB,						/* DVO clock					*/
+	AC97_CB,					/* AC97 clock					*/
+	PCM_CB,						/* PCM clock					*/
+	SCC_CB,						/* SCC clock					*/
+	JDEC_CB,					/* JDEC clock					*/
+	MSCD_CB,					/* MSCD clock					*/
+	AMP_CB,						/* AMP clock					*/
+	DSP_CB,						/* DSP clock					*/
+	DISP_CB,					/* DISP clock					*/
+	VPU_CB,						/* VPU clock					*/
+	MBOX_CB,					/* MBOX clock					*/
+	GE_CB,						/* GE clock						*/
+	GOVRHD_CB,				/* GOVRHD clock				*/
+	DDR_CB			=32,	/* DDR clock					*/
+	NA0_CB,						/* NA0 clock					*/
+	NA12_CB,					/* NA12 clock					*/
+	ARF_CB,						/* ARF clock					*/
+	ARFP_CB,					/* ARFP clock					*/
+	DMA_CB,						/* DMA clock					*/
+	ROT_CB,						/* ROT clock					*/
+	UHDC_CB,					/* UHDC clock					*/
+	PERM_CB,					/* PERM clock					*/
+	PDMA_CB,					/* PDMA clock					*/
+	SMARTCARD_CB,			/* SMARTCARD clock		*/
+	IDE100_CB,				/* IDE100 clock				*/
+	IDE133_CB,				/* IDE133 clock				*/
+	AHBB_CB,					/* AHBB clock					*/
+	SDTV_CB,					/* SDTV clock					*/
+	XD_CB,						/* XD clock						*/
+	NAND_CB,					/* NAND clock					*/
+	MSP_CB,						/* MSP clock					*/
+	SD0_CB,						/* SD0 clock					*/
+	SD1_CB,						/* SD1 clock					*/
+	MAC0_CB,					/* MAC0 clock					*/
+	SYS_CB,						/* SYS clock					*/
+	TSBK_CB,					/* TSBK clock					*/
+	SF_CB,						/* SF clock						*/
+	SAE_CB,						/* SAE clock					*/
+	H264_CB,					/* H264 clock					*/
+	EPHY_CB,					/* EPHY clock					*/
+	SCL444U_CB	=60,	/* SCL444U clock			*/
+	GOVW_CB,					/* GOVW clock					*/
+	VID_CB,						/* VID clock					*/
+	VPP_CB						/* VPP clock					*/
+};
+#endif
+
+enum CLOCK_BIT {
+        IDE100_CB = 43,	
+	XD_CB     = 47					/* XD clock */		
+};
+
+enum CLOCK_SET {
+	DIS_C         = 0,   /* Disabble clock          */
+	EN_C                 /* Enable Clock            */
+};
+
+#define CLOCKDIS(x)	((x < 32) ? (PMCEL_VAL &= ~(1 << x)):(PMCEU_VAL &= ~(1 << (x-32))))
+#define CLOCKEN(x)	((x < 32) ? (PMCEL_VAL |= (1 << x)):(PMCEU_VAL |= (1 << (x-32))))
+
+#define CLOCKSET(x,op) ((op) ? CLOCKEN(x):CLOCKDIS(x))
+
+#if 0
+/*wakeup event*/
+#define PMWT_C_WAKEUP(src, type)  ((type & PMWT_TYPEMASK) << (((src - 24) & PMWT_WAKEUPMASK) * 4))
+
+enum wakeup_src_e {
+	WKS_SRC0         = 0,    /* General Purpose Wakeup Source 0          */
+	WKS_SRC1,                /* General Purpose Wakeup Source 1          */
+	WKS_SRC2,                /* General Purpose Wakeup Source 2          */
+	WKS_SRC3,                /* General Purpose Wakeup Source 3          */
+	WKS_WOL0,                 /* Wake-on-LAN                              */
+	WKS_WOL1,                /* General Purpose Wakeup Source 3          */
+	WKS_SRC6,                /* General Purpose Wakeup Source 3          */
+	WKS_SRC7,                /* General Purpose Wakeup Source 3          */
+	WKS_RTC					= 15,    /* RTC alarm interrupt as wakeup            */
+	WKS_ETH					= 17,    /* ETH interrupt as wakeup            */
+	WKS_UHC					= 20,    /* UHC interrupt as wakeup            */
+	WKS_CIR					= 22,    /* CIR interrupt as wakeupr                     */
+	WKS_UDC         		= 24,    /* UDC interrupt as wakeup            */
+	WKS_CF					= 26,    /* CF interrupt as wakeupr                     */
+	WKS_XD,										/* XD interrupt as wakeupr                     */
+	WKS_MS,										/* MS interrupt as wakeupr                     */
+	WKS_SD0,									/* SD0 interrupt as wakeupr                     */
+	WKS_SD1,									/* SD1 interrupt as wakeupr                     */
+	WKS_SC,										/* SmartCard interrupt as wakeupr                     */
+	WKS_NUM										/* Wakeup event number                     */
+};
+#endif
+
+//#define UDC_HOTPLUG_TIMER
+
+#endif /* __VT8500_PMC_H */
diff --git a/board/wmt/include/wmt_spi.h b/board/wmt/include/wmt_spi.h
new file mode 100755
index 0000000..13b0bdb
--- /dev/null
+++ b/board/wmt/include/wmt_spi.h
@@ -0,0 +1,292 @@
+/*++
+Copyright (c) 2008 WonderMedia Technologies, Inc. All Rights Reserved.
+
+This PROPRIETARY SOFTWARE is the property of WonderMedia Technologies, Inc.
+and may contain trade secrets and/or other confidential information of
+WonderMedia Technologies, Inc. This file shall not be disclosed to any third
+party, in whole or in part, without prior written consent of WonderMedia.
+
+THIS PROPRIETARY SOFTWARE AND ANY RELATED DOCUMENTATION ARE PROVIDED AS IS,
+WITH ALL FAULTS, AND WITHOUT WARRANTY OF ANY KIND EITHER EXPRESS OR IMPLIED,
+AND WonderMedia TECHNOLOGIES, INC. DISCLAIMS ALL EXPRESS OR IMPLIED WARRANTIES
+OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR
+NON-INFRINGEMENT.
+--*/
+
+#ifndef __SPI_H__
+#define __SPI_H__
+
+#define SPI_REG_BASE     0xD8240000     /* SPI Base Address */
+#define SPI_REG_BASE1    0xD8250000     /* SPI1 Base Address */
+
+#define SPI_PORT_MAX        2
+
+#define SPI_PORT_NUM        2
+
+#define AHB_FREQ          100000
+
+#define SPI_PORT_REG_BASE_OFFSET  0x10000
+
+#define SPICR           0x00
+#define SPISR           0x04
+#define SPIDFCR           0x08
+#define SPICRE              0x0C
+#define SPITXFIFO         0x10
+#define SPIRXFIFO         0x30
+#define SPISRCV_CNT    0x50
+#define SPISRCV_Add_CNT 0x54
+
+#define GPIO_SPI0_SS    BIT3
+#define GPIO_SPI0_MOSI  BIT2
+#define GPIO_SPI0_MISO  BIT1
+#define GPIO_SPI0_CLK   BIT0
+#define GPIO_SPI0_SS_PULL_EN    BIT3
+#define GPIO_SPI0_MOSI_PULL_EN  BIT2
+#define GPIO_SPI0_MISO_PULL_EN  BIT1
+#define GPIO_SPI0_CLK_PULL_EN   BIT0
+
+/**/
+/*  SPI CFG setting*/
+/**/
+
+/************ Control Register ************/
+/* Transmit Clock Driver*/
+#define SPI_CR_TCD_SHIFT    21
+#define SPI_CR_TCD_MASK     (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21)
+/* Slave Selection*/
+#define SPI_CR_SS_SHIFT     19
+#define SPI_CR_SS_MASK      (BIT20|BIT19)
+/* Transmit FIFO Byte Write Method*/
+#define SPI_CR_WM_SHIFT     18
+#define SPI_CR_WM_MASK      (BIT18)
+/* Receive FIFO Reset*/
+#define SPI_CR_RFR_SHIFT    17
+#define SPI_CR_RFR_MASK     (BIT17)
+/* Transmit FIFO Reset*/
+#define SPI_CR_TFR_SHIFT    16
+#define SPI_CR_TFR_MASK     (BIT16)
+/* DMA Request Control*/
+#define SPI_CR_DRC_SHIFT    15
+#define SPI_CR_DRC_MASK     (BIT15)
+/* Receive FIFO Threshold Selection*/
+#define SPI_CR_RFTS_SHIFT   14
+#define SPI_CR_RFTS_MASK    (BIT14)
+/* Transmit FIFO Threshold Selection*/
+#define SPI_CR_TFTS_SHIFT   13
+#define SPI_CR_TFTS_MASK    (BIT13)
+/* Transmit FIFO Under-run Interrupt*/
+#define SPI_CR_TFUI_SHIFT   12
+#define SPI_CR_TFUI_MASK    (BIT12)
+/* Transmit FIFO Empty Interrupt*/
+#define SPI_CR_TFEI_SHIFT   11
+#define SPI_CR_TFEI_MASK    (BIT11)
+/* Receive FIFO Over-run Interrupt*/
+#define SPI_CR_RFOI_SHIFT   10
+#define SPI_CR_RFOI_MASK    (BIT10)
+/* Receive FIFO Full Interrupt*/
+#define SPI_CR_RFFI_SHIFT   9
+#define SPI_CR_RFFI_MASK    (BIT9)
+/* Receive FIFO Empty Interrupt*/
+#define SPI_CR_RFEI_SHIFT   8
+#define SPI_CR_RFEI_MASK    (BIT8)
+/* Threshold IRQ/DMA Selection*/
+#define SPI_CR_TIDS_SHIFT   7
+#define SPI_CR_TIDS_MASK    (BIT7)
+/* Interrupt Enable*/
+#define SPI_CR_IE_SHIFT     6
+#define SPI_CR_IE_MASK      (BIT6)
+/* Module Enable*/
+#define SPI_CR_ME_SHIFT     5
+#define SPI_CR_ME_MASK      (BIT5)
+/* Module Fault Error Interrupt*/
+#define SPI_CR_MFEI_SHIFT   4
+#define SPI_CR_MFEI_MASK    (BIT4)
+/* Master/Slave Mode Select*/
+#define SPI_CR_MSMS_SHIFT   3
+#define SPI_CR_MSMS_MASK    (BIT3)
+/* Clock Polarity Select*/
+#define SPI_CR_CPS_SHIFT    2
+#define SPI_CR_CPS_MASK     (BIT2)
+/* Clock Phase Select*/
+#define SPI_CR_CPHS_SHIFT   1
+#define SPI_CR_CPHS_MASK    (BIT1)
+/* Module Fault Error Feature*/
+#define SPI_CR_MFEF_SHIFT   0
+#define SPI_CR_MFEF_MASK    (BIT0)
+/* SPI Control Register Reset Value*/
+#define SPI_CR_RESET_MASK   SPI_CR_MSMS_MASK
+
+/************ Status Register *************/
+/* RX FIFO Count*/
+#define SPI_SR_RFCNT_SHIFT    24
+#define SPI_SR_RFCNT_MASK   (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)
+/* TX FIFO Count*/
+#define SPI_SR_TFCNT_SHIFT    16
+#define SPI_SR_TFCNT_MASK   (BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)
+/* TX FIFO Empty Status*/
+#define SPI_SR_TFES_SHIFT   15
+#define SPI_SR_TFES_MASK    (BIT15)
+/* Receive FIFO Threshold Passed Interrupt*/
+#define SPI_SR_RFTPI_SHIFT    14
+#define SPI_SR_RFTPI_MASK   (BIT14)
+/* Transmit FIFO Threshold Passed Interrupt*/
+#define SPI_SR_TFTPI_SHIFT    13
+#define SPI_SR_TFTPI_MASK   (BIT13)
+/* Transmit FIFO Under-run Interrupt*/
+#define SPI_SR_TFUI_SHIFT   12
+#define SPI_SR_TFUI_MASK    (BIT12)
+/* Transmit FIFO Empty Interrupt*/
+#define SPI_SR_TFEI_SHIFT   11
+#define SPI_SR_TFEI_MASK    (BIT11)
+/* Receive FIFO Over-run Interrupt*/
+#define SPI_SR_RFOI_SHIFT   10
+#define SPI_SR_RFOI_MASK    (BIT10)
+/* Receive FIFO Full Interrupt*/
+#define SPI_SR_RFFI_SHIFT   9
+#define SPI_SR_RFFI_MASK    (BIT9)
+/* Receive FIFO Empty Interrupt*/
+#define SPI_SR_RFEI_SHIFT   8
+#define SPI_SR_RFEI_MASK    (BIT8)
+/* SPI Busy*/
+#define SPI_SR_BUSY_SHIFT   7
+#define SPI_SR_BUSY_MASK    (BIT7)
+/* Mode Fault Error Interrupt*/
+#define SPI_SR_MFEI_SHIFT   4
+#define SPI_SR_MFEI_MASK    (BIT4)
+
+/****** Data Format Control Register ******/
+/*Preset Counter*/
+#define SPI_SSN_PRE_COUNTER_SHIFT 28
+#define SPI_SSN_PRE_COUNTER_MASK (BIT31|BIT30|BIT29|BIT28)
+/*HOLD EN*/
+#define SPI_SSN_HOLD_EN BIT26
+/*Microwire EN*/
+#define SPI_MICROWIRE_EN BIT25
+/*RX theshold Pass Interrupt Enable*/
+#define SPI_RX_THESHOLD_INT_EN BIT24
+/* Mode Fault Delay Count*/
+#define SPI_DFCR_MFDCNT_SHIFT 16
+#define SPI_DFCR_MFDCNT_MASK  (BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)
+/* TX Drive Count*/
+#define SPI_DFCR_TDCNT_SHIFT  8
+#define SPI_DFCR_TDCNT_MASK   (BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)
+/* TX Drive Enable*/
+#define SPI_DFCR_TDE_SHIFT    7
+#define SPI_DFCR_TDE_MASK   (BIT7)
+/* TX No Data Value*/
+#define SPI_DFCR_TNDV_SHIFT   6
+#define SPI_DFCR_TNDV_MASK    (BIT6)
+/* Direct SSN Enable*/
+#define SPI_DFCR_DSE_SHIFT    5
+#define SPI_DFCR_DSE_MASK   (BIT5)
+/* Direct SSN Value*/
+#define SPI_DFCR_DSV_SHIFT    4
+#define SPI_DFCR_DSV_MASK   (BIT4)
+/* SSN Control*/
+#define SPI_DFCR_SC_SHIFT   3
+#define SPI_DFCR_SC_MASK    (BIT3)
+/* SSN Port Mode*/
+#define SPI_DFCR_SPM_SHIFT    2
+#define SPI_DFCR_SPM_MASK   (BIT2)
+/* Receive Significant Bit Order*/
+#define SPI_DFCR_RSBO_SHIFT   1
+#define SPI_DFCR_RSBO_MASK    (BIT1)
+/* Transmit Significant Bit Order*/
+#define SPI_DFCR_TSBO_SHIFT   0
+#define SPI_DFCR_TSBO_MASK    (BIT0)
+/* SPI Data Format Control Register Reset Value*/
+#define SPI_DFCR_RESET_MASK   (SPI_DFCR_DSV_MASK|SPI_DFCR_DSE_MASK)
+
+/* Clock Mode Define*/
+#define SPI_CLK_MODE_LIST           \
+	T(SPI_MODE_0),  /*  0, CLK Idles Low  + SS  activation */ \
+	T(SPI_MODE_1),  /*  1, CLK Idles Low  + CLK activation */ \
+	T(SPI_MODE_2),  /*  2, CLK Idles High + SS  activation */ \
+	T(SPI_MODE_3) /*  3, CLK Idles High + CLK activation */
+
+/* Bus Master Define*/
+#define SPI_ARBITER_LIST            \
+	T(SPI_BUS_MASTER),  /*  0 */  \
+	T(SPI_BUS_SLAVE) /*  1 */
+
+/* Bus Operate Mode Define*/
+#define SPI_OP_MODE_LIST            \
+	T(SPI_POLLING_MODE),  /*  0 */  \
+	T(SPI_IRQ_MODE),  /*  1 */  \
+	T(SPI_DMA_MODE) /*  2 */
+
+#define T(x) x
+enum {
+	SPI_CLK_MODE_LIST
+};
+
+enum {
+	SPI_ARBITER_LIST
+};
+
+enum {
+	SPI_OP_MODE_LIST
+};
+#undef T
+
+struct spi_reg_s {
+	unsigned int volatile *cr;  /* Control Register*/
+	unsigned int volatile *sr;  /* Status Register*/
+	unsigned int volatile *dfcr;  /* Data Format Control Register*/
+	unsigned int volatile *cre; /*Extended Control Register*/
+	unsigned char volatile *rfifo;  /* Read FIFO, i.e. Receive FIFO*/
+	unsigned char volatile *wfifo;  /* Write FIFO, i.e. Transfer FIFO*/
+	unsigned int volatile *srcv_cnt;
+	unsigned int volatile *srcv_add_cnt;
+} ;
+
+struct spi_info_s {
+	/* Register Data*/
+	struct spi_reg_s regs;
+	/* Private Data*/
+	unsigned int freq;          /* Bus Frequence, Unit Khz*/
+	unsigned int  clk_mode;       /* Bus Clock Mode*/
+	unsigned int  op_mode;       /* Operation Mode, polling/irq/dma*/
+	/* Use for output setting value when FIFO goes empty*/
+	unsigned char tx_drive_count;   /* Set the number of bytes to send out*/
+	unsigned char tx_drive_enable;    /* Enable/Disable TX drive*/
+	unsigned char tx_nodata_value;    /* Set output value, o => 0x0, 1 =>0xff*/
+	/* Use for SSN Control correlated with slave_select*/
+	unsigned char ssn_control;      /* Set ssn control by 1 => program or 0 => hardware*/
+	/* user for master and slave control*/
+	unsigned int arbiter;
+	unsigned char ssn_port_mode;    /* set ssn port mode. 0 => multi-master, 1 => P2P*/
+	unsigned char slave_select;     /* Set output ssn pin {a,b,c,d}*/
+
+	unsigned int rx_cnt;
+	unsigned int tx_cnt;
+
+	/* interrup and dma control*/
+	int irq_num;
+	void (*isr)(void);          /* interrupt service routine*/
+	void (*dsr)(void);          /* dma service routine*/
+} ;
+
+//struct spi_info_s SPI_INFO[SPI_PORT_NUM];
+//struct spi_info_s *SPI_PORT[SPI_PORT_NUM];
+
+/*---------------------------------------------------------------------------------------*/
+/* GPIO Public functions declaration*/
+/*---------------------------------------------------------------------------------------*/
+void spi_init(void);
+
+void spi_info_reset(int port);
+
+void spi_set_reg(int port);
+
+void spi_enable(int port);
+
+void spi_disable(int port);
+
+struct spi_info_s *spi_get_info(int port);
+
+void spi_write_then_read_data(unsigned char *wbuf, unsigned char *rbuf, int num, int clk_mode, int chip_sel);
+
+int spi_init_clock(void);
+
+#endif  /*__SPI_H__*/
diff --git a/board/wmt/lowlevel_init.S b/board/wmt/lowlevel_init.S
new file mode 100755
index 0000000..ed5c49f
--- /dev/null
+++ b/board/wmt/lowlevel_init.S
@@ -0,0 +1,62 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* some parameters for the board */
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration */
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
diff --git a/board/wmt/main.c b/board/wmt/main.c
new file mode 100755
index 0000000..3146881
--- /dev/null
+++ b/board/wmt/main.c
@@ -0,0 +1,33 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef _GLOBAL_H_
+#include "include/global.h"
+#endif
+
+#ifndef _EXTVARS_H_
+#include "include/extvars.h"
+#endif
+
+/* #define CONFIG_UBOOT_DEBUG */
+unsigned long chip_id;
+
+int wmt_post(void)
+{
+	chip_id = *(volatile unsigned long *)(0xD8120000) >> 16;
+	return 0;
+}
diff --git a/board/wmt/poweroff.c b/board/wmt/poweroff.c
new file mode 100755
index 0000000..938f852
--- /dev/null
+++ b/board/wmt/poweroff.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2011 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include "include/wmt_pmc.h"
+#include "include/common_def.h"
+
+#define PMHC_HIBERNATE 0x205
+
+void do_wmt_poweroff(void)
+{
+	/*
+	 * Set scratchpad to zero, just in case it is used as a restart
+	 * address by the bootloader. Since PB_RESUME button has been
+	 * set to be one of the wakeup sources, clean the resume address
+	 * will cause zacboot to issue a SW_RESET, for design a behavior
+	 * to let PB_RESUME button be a power on button.
+	 *
+	 * Also force to disable watchdog timer, if it has been enabled.
+	 */
+	HSP0_VAL = 0;
+	OSTW_VAL &= ~OSTW_WE;
+
+	/*
+	 * Well, I cannot power-off myself,
+	 * so try to enter power-off suspend mode.
+	 */
+	PMHC_VAL = PMHC_HIBERNATE;
+
+	/* Force ARM to idle mode*/
+	asm volatile("ldr r0, =0xD813004C\n\t"
+		     "adr r1, .Cpu1_wfi\n\t"
+		     "str r1, [r0]\n\t"
+		     "sev\n\t"
+		     "ldr r0, =0xD8018008  @SCU\n\t"
+		     "ldr r1, =0x0303\n\t"
+		     "str  r1, [r0]\n\t"
+		     "ldr  r0, =0xD8130012\n\t"
+		     "ldr  r1, =0x205\n\t"
+		     "strh r1, [r0]\n\t"
+		     "wfi\n\t"
+		     ".Cpu1_wfi:\n\t"
+		     "wfi\n\t"
+		     "b .Cpu1_wfi\n\t"
+		    );
+}
+
+U_BOOT_CMD(
+	poweroff, 1,	0,	do_wmt_poweroff,
+	"poweroff - wmt device power off. \n",
+	"- wmt device power off.\n"
+);
+
diff --git a/board/wmt/u-boot.lds b/board/wmt/u-boot.lds
new file mode 100755
index 0000000..e85d288
--- /dev/null
+++ b/board/wmt/u-boot.lds
@@ -0,0 +1,82 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Some descriptions of such software. Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+
+ 	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+ 	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+
+
+	.debug          0 : { *(.debug) }
+	.line           0 : { *(.line) }
+
+	.debug_srcinfo  0 : { *(.debug_srcinfo) }
+	.debug_sfnames  0 : { *(.debug_sfnames) }
+
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	.debug_info     0 : { *(.debug_info) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+
+}
diff --git a/board/wmt/usb_uhci.c b/board/wmt/usb_uhci.c
new file mode 100755
index 0000000..6a2fb2d
--- /dev/null
+++ b/board/wmt/usb_uhci.c
@@ -0,0 +1,1303 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+
+/**********************************************************************
+ * How it works:
+ * -------------
+ * The framelist / Transfer descriptor / Queue Heads are similar like
+ * in the linux usb_uhci.c.
+ *
+ * During initialization, the following skeleton is allocated in init_skel:
+ *
+ *         framespecific           |           common chain
+ *
+ * framelist[]
+ * [  0 ]-----> TD ---------\
+ * [  1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
+ *   ...        TD ---------/
+ * [1023]-----> TD --------/
+ *
+ *              ^^             ^^         ^^          ^^          ^^
+ *              7 TDs for      1 TD for   Start of    Start of    End Chain
+ *              INT (2-128ms)  1ms-INT    CTRL Chain  BULK Chain
+ *
+ *
+ * Since this is a bootloader, the isochronous transfer descriptor have been removed.
+ *
+ * Interrupt Transfers.
+ * --------------------
+ * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
+ * will be inserted after the appropriate (depending the interval setting) skeleton TD.
+ * If an interrupt has been detected the dev->irqhandler is called. The status and number
+ * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
+ * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
+ * the interrupt TD will be reactivated.
+ *
+ * Control Transfers
+ * -----------------
+ * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ * Bulk Transfers
+ * --------------
+ * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
+ * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
+ * the programm has to wait for completion. This does not allows asynchronous data transfer.
+ *
+ *
+ */
+
+#include <common.h>
+#include <pci.h>
+
+
+#ifdef CONFIG_USB_UHCI
+
+#include "env.h" 
+#include <usb.h>
+#include "usb_uhci.h"
+#define USB_MAX_TEMP_TD      512  /* number of temporary TDs for bulk and control transfers */
+#define USB_MAX_TEMP_INT_TD  32   /* number of temporary TDs for Interrupt transfers */
+extern struct IC_REG        *pIc0_Reg;
+extern struct IC_REG        *pIc1_Reg;
+extern void free(void*);
+extern int usb_flag;
+/*#define	USB_UHCI_DEBUG*/
+#ifdef	USB_UHCI_DEBUG
+#define	USB_UHCI_PRINTF(fmt,args...)	printf (fmt ,##args)
+static int usb_display_td(uhci_td_t *td);
+
+#else
+#define USB_UHCI_PRINTF(fmt,args...)
+#endif
+
+#define BA_UHCI_PCI     0xD8007A00  /* USB 1.1 1st UHCI USB Host Configuration Base Address */
+#define BA_UHCI_REG     0xD8007B00  /* USB 1.1 1st UHCI USB Host Register Base Address */
+#define BA_UHCI2_PCI     0xD8008C00  /* USB 1.1 2nd UHCI USB Host Configuration Base Address */
+#define BA_UHCI2_REG     0xD8008D00  /* USB 1.1 2nd UHCI USB Host Register Base Address */
+extern int wmt_read_ostc(int *val);
+unsigned int usb_base_addr = BA_UHCI_REG;       /* base address */
+extern unsigned char usb_sel;
+
+ uhci_td_t td_int[8] __attribute__((aligned(128)));        /* Interrupt Transfer descriptors */
+ uhci_qh_t qh_cntrl __attribute__((aligned(128)));         /* control Queue Head */
+ uhci_qh_t qh_bulk __attribute__((aligned(128)));          /*  bulk Queue Head */
+ uhci_qh_t qh_end __attribute__((aligned(128)));           /* end Queue Head */
+ uhci_td_t td_last __attribute__((aligned(128)));          /* last TD (linked with end chain) */
+/* temporary tds */
+ uhci_td_t tmp_td[USB_MAX_TEMP_TD] __attribute__((aligned(128)));          /* temporary bulk/control td's  */
+ uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD] __attribute__((aligned(128)));  /* temporary interrupt td's  */
+unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */
+
+static struct virt_root_hub rh;   /* struct for root hub */
+
+/**********************************************************************
+ * some forward decleration
+ */
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+						void *buffer, int transfer_len,struct devrequest *setup);
+
+/* fill a td with the approproiate data. Link, status, info and buffer
+ * are used by the USB controller itselfes, dev is used to identify the
+ * "connected" device
+ */
+void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status,
+					unsigned long info, unsigned long buffer, unsigned long dev)
+{
+	//USB_UHCI_PRINTF("%s\n",__FUNCTION__);
+
+	td->link=swap_32(link);
+	td->status=swap_32(status);
+	td->info=swap_32(info);
+	td->buffer=swap_32(buffer);
+	td->dev_ptr=dev;
+}
+
+/* fill a qh with the approproiate data. Head and element are used by the USB controller
+ * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
+ * Please note, that after completion of the td chain, the entry element is removed /
+ * marked invalid by the USB controller.
+ */
+void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element)
+{
+	//USB_UHCI_PRINTF("%s\n",__FUNCTION__);
+
+	qh->head=swap_32(head);
+	qh->element=swap_32(element);
+	qh->dev_ptr=0L;
+}
+
+/* get the status of a td->status
+ */
+unsigned long usb_uhci_td_stat(unsigned long status)
+{
+	unsigned long result=0;
+	result |= (status & TD_CTRL_NAK)      ? USB_ST_NAK_REC : 0;
+	result |= (status & TD_CTRL_STALLED)  ? USB_ST_STALLED : 0;
+	result |= (status & TD_CTRL_DBUFERR)  ? USB_ST_BUF_ERR : 0;
+	result |= (status & TD_CTRL_BABBLE)   ? USB_ST_BABBLE_DET : 0;
+	result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
+	result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
+	result |= (status & TD_CTRL_ACTIVE)   ? USB_ST_NOT_PROC : 0;
+	return result;
+}
+
+/* get the status and the transfered len of a td chain.
+ * called from the completion handler
+ */
+int usb_get_td_status(uhci_td_t *td,struct usb_device *dev)
+{
+	unsigned long temp,info;
+	unsigned long stat;
+	uhci_td_t *mytd=td;
+	USB_UHCI_PRINTF("%s\n",__FUNCTION__);
+
+	if(dev->devnum==rh.devnum)
+		return 0;
+	dev->act_len=0;
+	stat=0;
+	do {
+		temp=swap_32((unsigned long)mytd->status);
+		stat=usb_uhci_td_stat(temp);
+		info=swap_32((unsigned long)mytd->info);
+		if(((info & 0xff)!= USB_PID_SETUP) &&
+				(((info >> 21) & 0x7ff)!= 0x7ff) &&
+				(temp & 0x7FF)!=0x7ff)
+		{  /* if not setup and not null data pack */
+			dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */
+		}
+		if(stat) {           /* status no ok */
+			dev->status=stat;
+			return -1;
+		}
+		temp=swap_32((unsigned long)mytd->link);
+		mytd=(uhci_td_t *)(temp & 0xfffffff0);
+	}while((temp & 0x1)==0); /* process all TDs */
+	dev->status=stat;
+	return 0; /* Ok */
+}
+
+
+/*-------------------------------------------------------------------
+ *                         LOW LEVEL STUFF
+ *          assembles QHs und TDs for control, bulk and iso
+ *-------------------------------------------------------------------*/
+
+/* Submits a control message. That is a Setup, Data and Status transfer.
+ * Routine does not wait for completion.
+ */
+int submit_uhci_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+										int transfer_len,struct devrequest *setup)
+{
+	unsigned long destination, status;
+	int maxsze = 0x40;
+	unsigned long dataptr;
+	int len;
+	int pktsze;
+	int i=0;
+	
+	USB_UHCI_PRINTF("uhci dev:%x,pipe:%x\n",dev,pipe);
+
+	if (!maxsze) {
+		USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe);
+		return -1;
+	}
+	
+	USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze);
+	/* The "pipe" thing contains the destination in bits 8--18 */
+	destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */
+	/* 3 errors */
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+	
+	/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
+	/*  Build the TD for the control request, try forever, 8 bytes of data */
+	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev);
+#if 0
+	{
+		char *sp=(char *)setup;
+		printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
+		    sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]);
+	}
+#endif
+	dataptr = (unsigned long)buffer;
+	len=transfer_len;
+
+	/* If direction is "send", change the frame from SETUP (0x2D)
+	   to OUT (0xE1). Else change it from SETUP to IN (0x69). */
+	destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN);
+	while (len > 0) {
+		/* data stage */
+		pktsze = len;
+		i++;
+		if (pktsze > maxsze)
+			pktsze = maxsze;
+		destination ^= 1 << TD_TOKEN_TOGGLE;	/* toggle DATA0/1 */
+		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
+		tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
+
+		dataptr += pktsze;
+		len -= pktsze;
+	}
+     
+	/*  Build the final TD for control status */
+	/* It's only IN if the pipe is out AND we aren't expecting data */
+
+	destination &= ~UHCI_PID;
+	if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0))
+		destination |= USB_PID_IN;
+	else
+		destination |= USB_PID_OUT;
+	destination |= 1 << TD_TOKEN_TOGGLE;	/* End in Data1 */
+	i++;
+	status &= ~TD_CTRL_SPD;
+	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status , destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev);	
+	tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);	/* queue status td */
+	/*usb_show_td(i + 1);	*/
+	USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i);
+	/* first mark the control QH element terminated */
+	qh_cntrl.element=0xffffffffL;
+	/* set qh active */
+	qh_cntrl.dev_ptr=(unsigned long)dev;
+	/* fill in tmp_td_chain */
+	qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]);
+	//check active status
+	 usb_check_td(&tmp_td[i-1]);
+	
+	return 0;
+}
+static int usb_check_td(uhci_td_t *td)
+{
+	int start_time, end_time;
+	wmt_read_ostc(&start_time); 
+	while (((swap_32(td->status) >> 23) & 0x1) == 0x1) {
+			if (((swap_32(td->status) >> 23) & 0x1) == 0)	{
+				break;
+			}
+			wmt_read_ostc(&end_time); 
+			if ((end_time - start_time) > 2000000)
+				break;
+	}
+	return 0;
+}
+static int usb_check_bulk_td(uhci_td_t *td)
+{	
+	int start_time, end_time;
+	wmt_read_ostc(&start_time); 
+	while (((swap_32(td->status) >> 23) & 0x1) == 0x1) {
+			if (((swap_32(td->status) >> 23) & 0x1) == 0) {
+				break;
+			}
+			wmt_read_ostc(&end_time); 
+			if ((end_time - start_time) > 2000000)
+				break;
+	}	
+	return 0;
+}
+/*-------------------------------------------------------------------
+ * Prepare TDs for bulk transfers.
+ */
+int submit_uhci_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len)
+{
+	unsigned long destination, status,info;
+	unsigned long dataptr;
+	int maxsze = 0x40;
+	int len;
+	int i = 0;
+	USB_UHCI_PRINTF("%s\n",__FUNCTION__);
+	if(transfer_len < 0) {
+		printf("Negative transfer length in submit_bulk\n");
+		return -1;
+	}
+	USB_UHCI_PRINTF(" maxsze:%x\n",maxsze);
+	
+	/* The "pipe" thing contains the destination in bits 8--18. */
+	destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe);
+	/* 3 errors */
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
+	/*	((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
+	/* Build the TDs for the bulk request */
+	len = transfer_len;
+	dataptr = (unsigned long)buffer;
+	do {
+		int pktsze = len;
+		if (pktsze > maxsze)
+			pktsze = maxsze;
+		/* pktsze bytes of data  */
+		info = destination | (((pktsze - 1) & UHCI_NULL_DATA_SIZE) << 21) |
+			(usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE);
+
+		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
+
+		if (i > 0)
+			tmp_td[i-1].link = swap_32((unsigned long) & tmp_td[i]);
+		i++;
+		dataptr += pktsze;
+		len -= pktsze;
+		usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+	} while (len > 0);
+		
+	/* first mark the bulk QH element terminated */
+	qh_bulk.element = 0xffffffffL;
+	/* set qh active */
+	qh_bulk.dev_ptr = (unsigned long)dev;
+	/* fill in tmp_td_chain */
+	qh_bulk.element = swap_32((unsigned long) & tmp_td[0]);
+	//Check bulk td active status 
+	 usb_check_bulk_td(&tmp_td[i-1]);
+
+	return 0;
+}
+
+
+/* search a free interrupt td
+ */
+uhci_td_t *uhci_alloc_int_td(void)
+{
+	int i;
+	for (i = 0;i < USB_MAX_TEMP_INT_TD;i++) {
+		if (tmp_int_td[i].dev_ptr == 0) /* no device assigned -> free TD */
+			return &tmp_int_td[i];
+	}
+	return NULL;
+}
+
+#if 0
+void uhci_show_temp_int_td(void)
+{
+	int i;
+	for (i = 0;i < USB_MAX_TEMP_INT_TD;i++) {
+		if ((tmp_int_td[i].dev_ptr&0x01)!=0x1L) /* no device assigned -> free TD */
+			printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr);
+	}
+	printf("all others temp_tds are free\n");
+}
+#endif
+/*-------------------------------------------------------------------
+ * submits USB interrupt (ie. polling ;-)
+ */
+int submit_uhci_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval)
+{
+	int nint, n;
+	unsigned long status, destination;
+	unsigned long info,tmp;
+	uhci_td_t *mytd;
+	if (interval < 0 || interval >= 256)
+		return -1;
+
+	if (interval == 0)
+		nint = 0;
+	else {
+		for (nint = 0, n = 1; nint <= 8; nint++, n += n)	/* round interval down to 2^n */
+		 {
+			if(interval < n) {
+				interval = n / 2;
+				break;
+			}
+		}
+		nint--;
+	}
+
+	USB_UHCI_PRINTF("Rounded interval to %i, chain  %i\n", interval, nint);
+	mytd = uhci_alloc_int_td();
+	if(mytd == NULL) {
+		printf("No free INT TDs found\n");
+		return -1;
+	}
+	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
+/*		(urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
+*/
+
+	destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21);
+
+	info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
+	tmp = swap_32(td_int[nint].link);
+	usb_fill_td(mytd, tmp, status, info, (unsigned long)buffer, (unsigned long)dev);
+	/* Link it */
+	tmp = swap_32((unsigned long)mytd);
+	td_int[nint].link = tmp;
+
+	usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
+
+	return 0;
+}
+
+/**********************************************************************
+ * Low Level functions
+ */
+
+
+void reset_hc(void)
+{
+	USB_UHCI_PRINTF("%s\n", __FUNCTION__);
+	out16r( usb_base_addr + USBCMD, USBCMD_GRESET);
+	/* Turn off all interrupts */
+	out16r(usb_base_addr + USBINTR, 0);
+	wait_ms(50);
+	out16r( usb_base_addr + USBCMD, 0);
+	wait_ms(10);
+}
+
+int start_hc(void)
+{
+	USB_UHCI_PRINTF("%s\n",__FUNCTION__);
+	int timeout = 1000;
+	int tmp;
+	
+	out16r( usb_base_addr + USBCMD, USBCMD_HCRESET);
+	wait_ms(10);
+
+	tmp = in16r(usb_base_addr + USBCMD);
+	while (tmp & USBCMD_HCRESET) {
+		if (!(--timeout)) {
+			printf("USBCMD_HCRESET timed out!\n");
+			break;
+		}
+	}
+	
+	
+	if (usb_sel & USB_PORT_A) {
+		/*port reset*/
+		out16r(usb_base_addr + USBPORTSC1, USBPORTSC_PR );
+		wait_ms(100);
+		tmp = in16r(usb_base_addr + USBPORTSC1);		
+		tmp &= ~USBPORTSC_PR;
+		out16r(usb_base_addr + USBPORTSC1, tmp);
+		/*enable uhci port 1 */
+		out16r(usb_base_addr + USBPORTSC1, USBPORTSC_PE |USBPORTSC_CSC | USBPORTSC_PEC);
+			wait_ms(50);
+		out16r(usb_base_addr + USBPORTSC1, USBPORTSC_PE | USBPORTSC_PEC |USBPORTSC_CSC);
+		/*clear port B  connect status change*/
+		out16r(usb_base_addr + USBPORTSC2, USBPORTSC_PEC |USBPORTSC_CSC);
+		tmp = in16r(usb_base_addr + USBPORTSC1);
+		/*low speed device ,mouse not support*/
+		if (tmp & USBPORTSC_LSDA) 
+			return -1;		
+	} else if (usb_sel & USB_PORT_B) {
+		/*port reset*/
+		out16r(usb_base_addr + USBPORTSC2, USBPORTSC_PR );
+		wait_ms(100);
+		tmp = in16r(usb_base_addr + USBPORTSC2);		
+		tmp &= ~USBPORTSC_PR;
+		out16r(usb_base_addr + USBPORTSC2, tmp);
+		/*enable uhci port 2 */
+		out16r(usb_base_addr + USBPORTSC2, USBPORTSC_PE |USBPORTSC_CSC | USBPORTSC_PEC);
+			wait_ms(50);
+		out16r(usb_base_addr + USBPORTSC2, USBPORTSC_PE | USBPORTSC_PEC| USBPORTSC_CSC);
+		out16r(usb_base_addr + USBPORTSC1, USBPORTSC_PEC| USBPORTSC_CSC);
+		tmp = in16r(usb_base_addr + USBPORTSC2);
+		if (tmp & USBPORTSC_LSDA)
+			return -1;
+
+	}
+	/* Start at frame 0 */
+	out16r(usb_base_addr + USBFRNUM,0);
+	/* set Framebuffer base address */
+	out32r(usb_base_addr + USBFLBASEADD, (unsigned long)&framelist);
+	/* Run and mark it configured with a 64-byte max packet */
+	out16r(usb_base_addr + USBCMD, USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
+	return 0;
+}
+void reset_hc2(void)
+{
+	USB_UHCI_PRINTF("%s\n", __FUNCTION__);
+	out16r( usb_base_addr + USBCMD, USBCMD_GRESET);
+	/* Turn off all interrupts */
+	out16r(usb_base_addr + USBINTR, 0);
+	wait_ms(50);
+	out16r( usb_base_addr + USBCMD, 0);
+	wait_ms(10);
+}
+
+int start_hc2(void)
+{
+	USB_UHCI_PRINTF("%s\n",__FUNCTION__);
+	int timeout = 1000;
+	int tmp;
+	tmp = in16r(usb_base_addr + USBCMD);
+	while (tmp & USBCMD_HCRESET) {
+		if (!(--timeout)) {
+			printf("USBCMD_HCRESET timed out!\n");
+			break;
+		}
+	}
+	/* Start at frame 0 */
+	out16r(usb_base_addr + USBFRNUM,0);
+	/* set Framebuffer base address */
+	out32r(usb_base_addr + USBFLBASEADD,(unsigned long)&framelist);
+	if (usb_sel & USB_PORT_C) {
+		/*port reset*/
+		out16r(usb_base_addr + USBPORTSC1, USBPORTSC_PR );
+		wait_ms(100);
+		tmp = in16r(usb_base_addr + USBPORTSC1);
+		tmp &= ~USBPORTSC_PR;
+		out16r(usb_base_addr + USBPORTSC1, tmp);
+		/*enable uhci port 1 */
+		out16r(usb_base_addr + USBPORTSC1, USBPORTSC_PE |USBPORTSC_CSC | USBPORTSC_PEC);
+			wait_ms(50);
+		out16r(usb_base_addr + USBPORTSC1, USBPORTSC_PE | USBPORTSC_PEC| USBPORTSC_CSC);
+		out16r(usb_base_addr + USBPORTSC2, USBPORTSC_PEC |USBPORTSC_CSC);
+		tmp = in16r(usb_base_addr + USBPORTSC1);
+		if (tmp & USBPORTSC_LSDA)
+			return -1;
+	} else if (usb_sel & USB_PORT_D) {
+		/*port reset*/
+		out16r(usb_base_addr + USBPORTSC2, USBPORTSC_PR );
+		wait_ms(100);
+		tmp = in16r(usb_base_addr + USBPORTSC2);
+		tmp &= ~USBPORTSC_PR;
+		out16r(usb_base_addr + USBPORTSC2, tmp);
+		/*enable uhci port 2 */
+		out16r(usb_base_addr + USBPORTSC2, USBPORTSC_PE |USBPORTSC_CSC | USBPORTSC_PEC);
+			wait_ms(50);
+		out16r(usb_base_addr + USBPORTSC2, USBPORTSC_PE | USBPORTSC_PEC |USBPORTSC_CSC);
+		out16r(usb_base_addr + USBPORTSC1, USBPORTSC_PEC |USBPORTSC_CSC);
+		tmp = in16r(usb_base_addr + USBPORTSC2);
+		if (tmp & USBPORTSC_LSDA)
+			return -1;
+	}
+	
+	/* Run and mark it configured with a 64-byte max packet */
+	out16r(usb_base_addr + USBCMD, USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
+	return 0;
+}
+
+/* Initialize the skeleton
+ */
+void usb_init_skel(void)
+{
+	unsigned long temp;
+	int n;
+	USB_UHCI_PRINTF("%s\n",__FUNCTION__);
+
+	for(n = 0;n < USB_MAX_TEMP_INT_TD;n++)
+		tmp_int_td[n].dev_ptr = 0; /* no devices connected */
+	usb_fill_td(&td_last,UHCI_PTR_TERM, 0, 0, 0, 0);  
+	/* End Queue Header */
+	usb_fill_qh(&qh_end, UHCI_PTR_TERM, (unsigned long)&td_last);
+	/* Bulk Queue Header */
+	temp = (unsigned long)&qh_end;
+	usb_fill_qh(&qh_bulk,temp | UHCI_PTR_QH, UHCI_PTR_TERM);
+	/* Control Queue Header */
+	temp = (unsigned long)&qh_bulk;
+	usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH, UHCI_PTR_TERM);
+	/* 1ms Interrupt td */
+	temp = (unsigned long)&qh_cntrl;
+	usb_fill_td(&td_int[0],temp | UHCI_PTR_QH, 0, 0, 0, 0);
+	temp = (unsigned long)&td_int[0];
+	for(n = 1; n < 8; n++)
+		usb_fill_td(&td_int[n], temp, 0, 0, 0, 0);
+	for (n = 0; n < 1024; n++) {
+	/* link all framelist pointers to one of the interrupts */
+		int m, o;
+		if ((n & 127) == 127)
+			framelist[n] = swap_32((unsigned long)&td_int[0]);
+		else
+			for (o = 1, m = 2; m <= 128; o++, m += m)
+				if ((n & (m - 1)) == ((m - 1) / 2))
+						framelist[n]= swap_32((unsigned long)&td_int[o]);
+	}
+}
+
+/* check the common skeleton for completed transfers, and update the status
+ * of the "connected" device. Called from the IRQ routine.
+ */
+void usb_check_skel(void)
+{
+	struct usb_device *dev;
+	/* start with the control qh */
+	if(qh_cntrl.dev_ptr!= 0) /* it's a device assigned check if this caused IRQ */
+	{
+		dev = (struct usb_device *)qh_cntrl.dev_ptr;
+		usb_get_td_status(&tmp_td[0],dev); /* update status */
+		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+			qh_cntrl.dev_ptr = 0;
+		}
+	}
+	/* now process the bulk */
+	if(qh_bulk.dev_ptr!= 0) /* it's a device assigned check if this caused IRQ */
+	{
+		dev = (struct usb_device *)qh_bulk.dev_ptr;
+		usb_get_td_status(&tmp_td[0],dev); /* update status */
+		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
+			qh_bulk.dev_ptr = 0;
+		}
+	}
+}
+
+/* check the interrupt chain, ubdate the status of the appropriate device,
+ * call the appropriate irqhandler and reactivate the TD if the irqhandler
+ * returns with 1
+ */
+void usb_check_int_chain(void)
+{
+	int i,res;
+	unsigned long link,status;
+	struct usb_device *dev;
+	uhci_td_t *td,*prevtd;
+
+	for(i=0;i<8;i++) {
+		prevtd=&td_int[i]; /* the first previous td is the skeleton td */
+		link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
+		td=(uhci_td_t *)link; /* assign it */
+		/* all interrupt TDs are finally linked to the td_int[0].
+ 		 * so we process all until we find the td_int[0].
+		 * if int0 chain points to a QH, we're also done
+	   */
+		while(((i>0) && (link != (unsigned long)&td_int[0])) ||
+					((i==0) && !(swap_32(td->link) &  UHCI_PTR_QH)))
+		{
+			/* check if a device is assigned with this td */
+			status=swap_32(td->status);
+			if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) {
+				/* td is not active and a device is assigned -> call irqhandler */
+				dev=(struct usb_device *)td->dev_ptr;
+				dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */
+				dev->irq_status=usb_uhci_td_stat(status); /* get status */
+				res=dev->irq_handle(dev); /* call irqhandler */
+				if(res==1) {
+					/* reactivate */
+					status|=TD_CTRL_ACTIVE;
+					td->status=swap_32(status);
+					prevtd=td; /* previous td = this td */
+				}
+				else {
+					prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */
+					/* remove device pointer */
+					td->dev_ptr=0L;
+				}
+			} /* if we call the irq handler */
+			link=swap_32(td->link) & 0xfffffff0; /* next in chain */
+			td=(uhci_td_t *)link; /* assign it */
+		} /* process all td in this int chain */
+	} /* next interrupt chain */
+}
+
+
+/* usb interrupt service routine.
+ */
+void handle_usb_interrupt(void)
+{
+	unsigned short status;
+	USB_UHCI_PRINTF("%s\n",__FUNCTION__);
+
+	/*
+	 * Read the interrupt status, and write it back to clear the
+	 * interrupt cause
+	 */
+
+	status = in16r(usb_base_addr + USBSTS);
+
+	if (!status)		/* shared interrupt, not mine */
+		return;
+	if (status != 1) {
+		/* remove host controller halted state */
+		if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) {
+			out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD));
+		}
+	}
+	usb_check_int_chain(); /* call interrupt handlers for int tds */
+	usb_check_skel(); /* call completion handler for common transfer routines */
+	out16r(usb_base_addr+USBSTS,status);
+}
+
+
+
+/* init uhci
+ */
+int uhci_lowlevel_init(void)
+{
+	int status=0;
+       USB_UHCI_PRINTF("%s\n",__FUNCTION__);
+      
+	rh.devnum = 0;
+	usb_init_skel();
+			
+	if (usb_sel & USB_UHCI_1) {
+		usb_base_addr = BA_UHCI_REG;
+		USB_UHCI_PRINTF("usb_base_addr =  0x%8.8x\n", usb_base_addr);
+		reset_hc();	
+		status = start_hc();
+		if (status < 0)
+			return -1;
+	}else if  (usb_sel & USB_UHCI_2 ) {
+		usb_base_addr = BA_UHCI2_REG;
+		USB_UHCI_PRINTF("usb_base_addr =  0x%8.8x\n", usb_base_addr);
+		reset_hc2();
+		status = start_hc2();
+		if (status < 0)
+			return -1;
+	}else {
+		usb_base_addr = BA_UHCI_REG;
+		USB_UHCI_PRINTF("usb_base_addr =  0x%8.8x\n", usb_base_addr);
+		reset_hc();	
+		status = start_hc();
+		if (status < 0)
+			return -1;
+	}
+
+     	usb_flag = usb_uhci_flag;
+	return 0;
+}
+
+/* stop uhci
+ */
+int uhci_lowlevel_stop(void)
+{
+	
+	if (usb_sel & USB_UHCI_1) {
+		reset_hc();
+	}else if (usb_sel & USB_UHCI_2) {
+		reset_hc2();
+	}
+	return 0;
+}
+
+/*******************************************************************************************
+ * Virtual Root Hub
+ * Since the uhci does not have a real HUB, we simulate one ;-)
+ */
+/* #undef	USB_RH_DEBUG */
+#define	USB_RH_DEBUG 1
+#ifdef	USB_RH_DEBUG
+#define	USB_RH_PRINTF(fmt,args...)	printf (fmt ,##args)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex);
+static void usb_display_Req(unsigned short req);
+#else
+#define USB_RH_PRINTF(fmt,args...)
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {}
+static void usb_display_Req(unsigned short req) {}
+#endif
+
+static unsigned char root_hub_dev_des[] =
+{
+	0x12,			/*  __u8  bLength; */
+	0x01,			/*  __u8  bDescriptorType; Device */
+	0x00,			/*  __u16 bcdUSB; v1.0 */
+	0x01,
+	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  bDeviceSubClass; */
+	0x00,			/*  __u8  bDeviceProtocol; */
+	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,			/*  __u16 idVendor; */
+	0x00,
+	0x00,			/*  __u16 idProduct; */
+	0x00,
+	0x00,			/*  __u16 bcdDevice; */
+	0x00,
+	0x01,			/*  __u8  iManufacturer; */
+	0x00,			/*  __u8  iProduct; */
+	0x00,			/*  __u8  iSerialNumber; */
+	0x01			/*  __u8  bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static unsigned char root_hub_config_des[] =
+{
+	0x09,			/*  __u8  bLength; */
+	0x02,			/*  __u8  bDescriptorType; Configuration */
+	0x19,			/*  __u16 wTotalLength; */
+	0x00,
+	0x01,			/*  __u8  bNumInterfaces; */
+	0x01,			/*  __u8  bConfigurationValue; */
+	0x00,			/*  __u8  iConfiguration; */
+	0x40,			/*  __u8  bmAttributes;
+				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,			/*  __u8  MaxPower; */
+
+     /* interface */
+	0x09,			/*  __u8  if_bLength; */
+	0x04,			/*  __u8  if_bDescriptorType; Interface */
+	0x00,			/*  __u8  if_bInterfaceNumber; */
+	0x00,			/*  __u8  if_bAlternateSetting; */
+	0x01,			/*  __u8  if_bNumEndpoints; */
+	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  if_bInterfaceSubClass; */
+	0x00,			/*  __u8  if_bInterfaceProtocol; */
+	0x00,			/*  __u8  if_iInterface; */
+
+     /* endpoint */
+	0x07,			/*  __u8  ep_bLength; */
+	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
+	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
+	0x08,			/*  __u16 ep_wMaxPacketSize; 8 Bytes */
+	0x00,
+	0xff			/*  __u8  ep_bInterval; 255 ms */
+};
+
+
+static unsigned char root_hub_hub_des[] =
+{
+	0x09,			/*  __u8  bLength; */
+	0x29,			/*  __u8  bDescriptorType; Hub-descriptor */
+	0x02,			/*  __u8  bNbrPorts; */
+	0x00,			/* __u16  wHubCharacteristics; */
+	0x00,
+	0x01,			/*  __u8  bPwrOn2pwrGood; 2ms */
+	0x00,			/*  __u8  bHubContrCurrent; 0 mA */
+	0x00,			/*  __u8  DeviceRemovable; *** 7 Ports max *** */
+	0xff			/*  __u8  PortPwrCtrlMask; *** 7 ports max *** */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+	28,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'U',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'C',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'I',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+};
+
+
+/*
+ * Root Hub Control Pipe (interrupt Pipes are not supported)
+ */
+
+
+int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd)
+{
+	void *data = buffer;
+	int leni = transfer_len;
+	int len = 0;
+	int status = 0;
+	int stat = 0;
+	int i;
+
+	unsigned short cstatus;
+
+	unsigned short bmRType_bReq;
+	unsigned short wValue;
+	unsigned short wIndex;
+	unsigned short wLength;
+
+	if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
+		printf("Root-Hub submit IRQ: NOT implemented\n");
+#if 0
+		uhci->rh.urb = urb;
+		uhci->rh.send = 1;
+		uhci->rh.interval = urb->interval;
+		rh_init_int_timer (urb);
+#endif
+		return 0;
+	}
+	bmRType_bReq = cmd->requesttype | cmd->request << 8;
+	wValue = swap_16(cmd->value);
+	wIndex = swap_16(cmd->index);
+	wLength = swap_16(cmd->length);
+	usb_display_Req(bmRType_bReq);
+	for (i = 0; i < 8; i++)
+		rh.c_p_r[i] = 0;
+	USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x %02x %04x %04x %04x\n",
+	     dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength);
+
+	switch (bmRType_bReq) {
+		/* Request Destination:
+		   without flags: Device,
+		   RH_INTERFACE: interface,
+		   RH_ENDPOINT: endpoint,
+		   RH_CLASS means HUB here,
+		   RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
+		 */
+
+	case RH_GET_STATUS:
+		*(unsigned short *) data = swap_16(1);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_INTERFACE:
+		*(unsigned short *) data = swap_16(0);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_ENDPOINT:
+		*(unsigned short *) data = swap_16(0);
+		len=2;
+		break;
+	case RH_GET_STATUS | RH_CLASS:
+		*(unsigned long *) data = swap_32(0);
+		len=4;
+		break;	/* hub power ** */
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+
+		status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
+		cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
+			((status & USBPORTSC_PEC) >> (3 - 1)) |
+			(rh.c_p_r[wIndex - 1] << (0 + 4));
+		status = (status & USBPORTSC_CCS) |
+			((status & USBPORTSC_PE) >> (2 - 1)) |
+			((status & USBPORTSC_SUSP) >> (12 - 2)) |
+			((status & USBPORTSC_PR) >> (9 - 4)) |
+			(1 << 8) |	/* power on ** */
+			((status & USBPORTSC_LSDA) << (-8 + 9));
+
+		*(unsigned short *) data = swap_16(status);
+		*(unsigned short *) (data + 2) = swap_16(cstatus);
+		len=4;
+		break;
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		switch (wValue) {
+		case (RH_ENDPOINT_STALL):
+			len=0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		switch (wValue) {
+		case (RH_C_HUB_OVER_CURRENT):
+			len=0;	/* hub power over current ** */
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		usb_display_wValue(wValue,wIndex);
+		switch (wValue) {
+		case (RH_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) & ~USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_SUSPEND):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) & ~USBPORTSC_SUSP;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_POWER):
+			len=0;	/* port power ** */
+			break;
+		case (RH_C_PORT_CONNECTION):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_CSC;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_C_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PEC;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_C_PORT_SUSPEND):
+/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
+			len=0;
+			break;
+		case (RH_C_PORT_OVER_CURRENT):
+			len=0;
+			break;
+		case (RH_C_PORT_RESET):
+			rh.c_p_r[wIndex - 1] = 0;
+			len=0;
+			break;
+		}
+		break;
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		usb_display_wValue(wValue,wIndex);
+		switch (wValue) {
+		case (RH_PORT_SUSPEND):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_SUSP;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_RESET):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PR;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			wait_ms(10);
+			status = (status & 0xfff5) & ~USBPORTSC_PR;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			udelay(10);
+			status = (status & 0xfff5) | USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			wait_ms(10);
+			status = (status & 0xfff5) | 0xa;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		case (RH_PORT_POWER):
+			len=0;	/* port power ** */
+			break;
+		case (RH_PORT_ENABLE):
+			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
+			status = (status & 0xfff5) | USBPORTSC_PE;
+			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
+			len=0;
+			break;
+		}
+		break;
+
+	case RH_SET_ADDRESS:
+		rh.devnum = wValue;
+		len=0;
+		break;
+	case RH_GET_DESCRIPTOR:
+		switch ((wValue & 0xff00) >> 8) {
+		case (0x01):	/* device descriptor */
+			i=sizeof(root_hub_config_des);
+			status=i > wLength ? wLength : i;
+			len = leni > status ? status : leni;
+			memcpy (data, root_hub_dev_des, len);
+			break;
+		case (0x02):	/* configuration descriptor */
+			i=sizeof(root_hub_config_des);
+			status=i > wLength ? wLength : i;
+			len = leni > status ? status : leni;
+			memcpy (data, root_hub_config_des, len);
+			break;
+		case (0x03):	/*string descriptors */
+			if(wValue==0x0300) {
+				i=sizeof(root_hub_str_index0);
+				status = i > wLength ? wLength : i;
+				len = leni > status ? status : leni;
+				memcpy (data, root_hub_str_index0, len);
+				break;
+			}
+			if(wValue==0x0301) {
+				i=sizeof(root_hub_str_index1);
+				status = i > wLength ? wLength : i;
+				len = leni > status ? status : leni;
+				memcpy (data, root_hub_str_index1, len);
+				break;
+			}
+			stat = USB_ST_STALLED;
+		}
+		break;
+
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		root_hub_hub_des[2] = 2;
+		i=sizeof(root_hub_hub_des);
+		status= i > wLength ? wLength : i;
+		len = leni > status ? status : leni;
+		memcpy (data, root_hub_hub_des, len);
+		break;
+	case RH_GET_CONFIGURATION:
+		*(unsigned char *) data = 0x01;
+		len = 1;
+		break;
+	case RH_SET_CONFIGURATION:
+		len=0;
+		break;
+	default:
+		stat = USB_ST_STALLED;
+	}
+	USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat,
+	     in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2));
+	dev->act_len=len;
+	dev->status=stat;
+	return stat;
+
+}
+
+/********************************************************************************
+ * Some Debug Routines
+ */
+
+#ifdef	USB_RH_DEBUG
+
+static void usb_display_Req(unsigned short req)
+{
+	USB_RH_PRINTF("- Root-Hub Request: ");
+	switch (req) {
+	case RH_GET_STATUS:
+		USB_RH_PRINTF("Get Status ");
+		break;
+	case RH_GET_STATUS | RH_INTERFACE:
+		USB_RH_PRINTF("Get Status Interface ");
+		break;
+	case RH_GET_STATUS | RH_ENDPOINT:
+		USB_RH_PRINTF("Get Status Endpoint ");
+		break;
+	case RH_GET_STATUS | RH_CLASS:
+		USB_RH_PRINTF("Get Status Class");
+		break;	/* hub power ** */
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Get Status Class Others");
+		break;
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		USB_RH_PRINTF("Clear Feature Endpoint ");
+		break;
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		USB_RH_PRINTF("Clear Feature Class ");
+		break;
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Clear Feature Other Class ");
+		break;
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		USB_RH_PRINTF("Set Feature Other Class ");
+		break;
+	case RH_SET_ADDRESS:
+		USB_RH_PRINTF("Set Address ");
+		break;
+	case RH_GET_DESCRIPTOR:
+		USB_RH_PRINTF("Get Descriptor ");
+		break;
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		USB_RH_PRINTF("Get Descriptor Class ");
+		break;
+	case RH_GET_CONFIGURATION:
+		USB_RH_PRINTF("Get Configuration ");
+		break;
+	case RH_SET_CONFIGURATION:
+		USB_RH_PRINTF("Get Configuration ");
+		break;
+	default:
+		USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req);
+	}
+	USB_RH_PRINTF("\n");
+
+}
+
+static void usb_display_wValue(unsigned short wValue,unsigned short wIndex)
+{
+	switch (wValue) {
+		case (RH_PORT_ENABLE):
+			USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex);
+			break;
+		case (RH_PORT_SUSPEND):
+			USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex);
+			break;
+		case (RH_PORT_POWER):
+			USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex);
+			break;
+		case (RH_C_PORT_CONNECTION):
+			USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_ENABLE):
+			USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_SUSPEND):
+			USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_OVER_CURRENT):
+			USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex);
+			break;
+		case (RH_C_PORT_RESET):
+			USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex);
+			break;
+		default:
+			USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex);
+			break;
+	}
+}
+
+#endif
+
+
+#ifdef	USB_UHCI_DEBUG
+
+static int usb_display_td(uhci_td_t *td)
+{
+	unsigned long tmp;
+	int valid;
+
+	printf("TD at %p:\n",td);
+
+	tmp=swap_32(td->link);
+	printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0,
+		((tmp & 0x4)==0x4) ? "Depth" : "Breath",
+		((tmp & 0x2)==0x2) ? "QH" : "TD",
+		((tmp & 0x1)==0x1) ? "invalid" : "valid");
+	valid=((tmp & 0x1)==0x0);
+	tmp=swap_32(td->status);
+	printf("     %s %ld Errors %s %s %s \n     %s %s %s %s %s %s\n     Len 0x%lX\n",
+		(((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable",
+		((tmp>>28)&0x3),
+		(((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed",
+		(((tmp>>25)&0x1)==0x1) ? "ISO " : "",
+		(((tmp>>24)&0x1)==0x1) ? "IOC " : "",
+		(((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ",
+		(((tmp>>22)&0x1)==0x1) ? "Stalled" : "",
+		(((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "",
+		(((tmp>>20)&0x1)==0x1) ? "Babble" : "",
+		(((tmp>>19)&0x1)==0x1) ? "NAK" : "",
+		(((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "",
+		(tmp&0x7ff));
+	tmp=swap_32(td->info);
+	printf("     MaxLen 0x%lX\n",((tmp>>21)&0x7FF));
+	printf("     %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "",
+		((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF);
+	tmp=swap_32(td->buffer);
+	printf("     Buffer 0x%08lX\n",tmp);
+	printf("     DEV %08lX\n",td->dev_ptr);
+	return valid;
+}
+
+
+void usb_show_td(int max)
+{
+	int i;
+	if (max > 0) {
+		for (i = 0; i < max; i++) {
+			usb_display_td(&tmp_td[i]);
+		}
+	} else {
+		i = 0;
+		do {
+			printf("tmp_td[%d]\n", i);
+		}while(usb_display_td(&tmp_td[i++]));
+	}
+}
+
+
+
+#endif
+#endif /* CONFIG_USB_UHCI */
+
+/* EOF */
diff --git a/board/wmt/usb_uhci.h b/board/wmt/usb_uhci.h
new file mode 100755
index 0000000..ff5fcfc
--- /dev/null
+++ b/board/wmt/usb_uhci.h
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_UHCI_H_
+#define _USB_UHCI_H_
+
+#undef USB_UHCI_VEND_ID
+#define USB_UHCI_VEND_ID PCI_VENDOR_ID_VIA
+#undef USB_UHCI_DEV_ID
+#define USB_UHCI_DEV_ID 0x3038
+
+/* Command register */
+#define USBCMD		0
+#define   USBCMD_RS       0x0001	/* Run/Stop */
+#define   USBCMD_HCRESET  0x0002	/* Host reset */
+#define   USBCMD_GRESET   0x0004	/* Global reset */
+#define   USBCMD_EGSM     0x0008	/* Global Suspend Mode */
+#define   USBCMD_FGR      0x0010	/* Force Global Resume */
+#define   USBCMD_SWDBG    0x0020	/* SW Debug mode */
+#define   USBCMD_CF       0x0040	/* Config Flag (sw only) */
+#define   USBCMD_MAXP     0x0080	/* Max Packet (0 = 32, 1 = 64) */
+
+/* Status register */
+#define USBSTS		2
+#define   USBSTS_USBINT   0x0001	/* Interrupt due to IOC */
+#define   USBSTS_ERROR    0x0002	/* Interrupt due to error */
+#define   USBSTS_RD       0x0004	/* Resume Detect */
+#define   USBSTS_HSE      0x0008	/* Host System Error - basically PCI problems */
+#define   USBSTS_HCPE     0x0010	/* Host Controller Process Error - the scripts were buggy */
+#define   USBSTS_HCH      0x0020	/* HC Halted */
+
+/* Interrupt enable register */
+#define USBINTR		4
+#define   USBINTR_TIMEOUT 0x0001	/* Timeout/CRC error enable */
+#define   USBINTR_RESUME  0x0002	/* Resume interrupt enable */
+#define   USBINTR_IOC     0x0004	/* Interrupt On Complete enable */
+#define   USBINTR_SP      0x0008	/* Short packet interrupt enable */
+
+#define USBFRNUM      6
+#define USBFLBASEADD  8
+#define USBSOF        12
+
+/* USB port status and control registers */
+#define USBPORTSC1	16
+#define USBPORTSC2	18
+#define   USBPORTSC_CCS   0x0001	/* Current Connect Status ("device present") */
+#define   USBPORTSC_CSC   0x0002	/* Connect Status Change */
+#define   USBPORTSC_PE    0x0004	/* Port Enable */
+#define   USBPORTSC_PEC   0x0008	/* Port Enable Change */
+#define   USBPORTSC_LS    0x0030	/* Line Status */
+#define   USBPORTSC_RD    0x0040	/* Resume Detect */
+#define   USBPORTSC_LSDA  0x0100	/* Low Speed Device Attached */
+#define   USBPORTSC_PR    0x0200	/* Port Reset */
+#define   USBPORTSC_SUSP  0x1000	/* Suspend */
+
+/* Legacy support register */
+#define USBLEGSUP 0xc0
+#define USBLEGSUP_DEFAULT 0x2000	/* only PIRQ enable set */
+
+#define UHCI_NULL_DATA_SIZE 0x7ff	/* for UHCI controller TD */
+#define UHCI_PID            0xff	/* PID MASK */
+
+#define UHCI_PTR_BITS       0x000F
+#define UHCI_PTR_TERM       0x0001
+#define UHCI_PTR_QH         0x0002
+#define UHCI_PTR_DEPTH      0x0004
+
+/* for TD <status>: */
+#define TD_CTRL_SPD         (1 << 29)	/* Short Packet Detect */
+#define TD_CTRL_C_ERR_MASK  (3 << 27)	/* Error Counter bits */
+#define TD_CTRL_LS          (1 << 26)	/* Low Speed Device */
+#define TD_CTRL_IOS         (1 << 25)	/* Isochronous Select */
+#define TD_CTRL_IOC         (1 << 24)	/* Interrupt on Complete */
+#define TD_CTRL_ACTIVE      (1 << 23)	/* TD Active */
+#define TD_CTRL_STALLED     (1 << 22)	/* TD Stalled */
+#define TD_CTRL_DBUFERR     (1 << 21)	/* Data Buffer Error */
+#define TD_CTRL_BABBLE      (1 << 20)	/* Babble Detected */
+#define TD_CTRL_NAK         (1 << 19)	/* NAK Received */
+#define TD_CTRL_CRCTIMEO    (1 << 18)	/* CRC/Time Out Error */
+#define TD_CTRL_BITSTUFF    (1 << 17)	/* Bit Stuff Error */
+#define TD_CTRL_ACTLEN_MASK 0x7ff	/* actual length, encoded as n - 1 */
+
+#define TD_CTRL_ANY_ERROR	(TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
+				 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
+
+#define TD_TOKEN_TOGGLE		19
+
+/* ------------------------------------------------------------------------------------
+   Virtual Root HUB
+   ------------------------------------------------------------------------------------ */
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+/* Our Vendor Specific feature */
+#define RH_REMOVE_EP               0x00
+
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+
+/* Transfer descriptor structure */
+typedef struct {
+	unsigned long link;     /* next td/qh (LE)*/
+	unsigned long status;   /* status of the td */
+	unsigned long info;     /* Max Lenght / Endpoint / device address and PID */
+	unsigned long buffer;   /* pointer to data buffer (LE) */
+	unsigned long dev_ptr;  /* pointer to the assigned device (BE) */
+	unsigned long res[3];   /* reserved (TDs must be 8Byte aligned) */
+}__attribute__ ((packed)) uhci_td_t, *puhci_td_t;
+
+/* Queue Header structure */
+typedef struct {
+	unsigned long head;       /* Next QH (LE)*/
+	unsigned long element;		/* Queue element pointer (LE) */
+	unsigned long res[5];     /* reserved */
+	unsigned long dev_ptr;    /* if 0 no tds have been assigned to this qh */
+}__attribute__ ((packed)) uhci_qh_t, *puhci_qh_t;
+
+struct virt_root_hub {
+	int devnum;		            /* Address of Root Hub endpoint */
+	int numports;             /* number of ports */
+	int c_p_r[8];             /* C_PORT_RESET */
+};
+
+
+void reset_hc(void);
+int start_hc(void);
+void reset_hc2(void);
+int start_hc2(void);
+static int usb_check_td(uhci_td_t *td);
+static int usb_check_bulk_td(uhci_td_t *td);
+#define	IRQ_UHDC             43
+#define   USB_PORT_A 1
+#define   USB_PORT_B 2
+#define   USB_PORT_C 4
+#define   USB_PORT_D 8
+#define   USB_UHCI_1 0x03
+#define   USB_UHCI_2 0x0C
+#endif /* _USB_UHCI_H_ */
diff --git a/board/wmt/vt1603/snd-vt1603.c b/board/wmt/vt1603/snd-vt1603.c
new file mode 100755
index 0000000..db40142
--- /dev/null
+++ b/board/wmt/vt1603/snd-vt1603.c
@@ -0,0 +1,262 @@
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/arch/common_def.h>
+#include <asm/errno.h>
+
+#include "../include/wmt_pmc.h"
+#include "../include/wmt_spi.h"
+#include "../include/wmt_clk.h"
+#include "../include/wmt_gpio.h"
+
+#define BIT0	0x00000001
+#define BIT1	0x00000002
+#define BIT2	0x00000004
+#define BIT3	0x00000008
+#define BIT4	0x00000010
+#define BIT5	0x00000020
+#define BIT6	0x00000040
+#define BIT7	0x00000080
+#define BIT8	0x00000100
+
+#define VT1603_R00  0x00
+#define VT1603_R01  0x01
+#define VT1603_R02  0x02
+#define VT1603_R03  0x03
+#define VT1603_R04  0x04
+#define VT1603_R05  0x05
+#define VT1603_R06  0x06
+#define VT1603_R07  0x07
+#define VT1603_R08  0x08
+#define VT1603_R09  0x09
+#define VT1603_R0a  0x0a
+#define VT1603_R0b  0x0b
+#define VT1603_R0c  0x0c
+#define VT1603_R0d  0x0d
+#define VT1603_R0e  0x0e
+#define VT1603_R0f  0x0f
+#define VT1603_R10  0x10
+#define VT1603_R11  0x11
+#define VT1603_R12  0x12
+#define VT1603_R13  0x13
+#define VT1603_R15  0x15
+#define VT1603_R19  0x19
+#define VT1603_R1b  0x1b
+#define VT1603_R1c  0x1c
+#define VT1603_R1d  0x1d
+#define VT1603_R20  0x20
+#define VT1603_R21  0x21
+#define VT1603_R23  0x23
+#define VT1603_R24  0x24
+#define VT1603_R25  0x25
+#define VT1603_R28  0x28
+#define VT1603_R29  0x29
+#define VT1603_R2a  0x2a
+#define VT1603_R2b  0x2b
+#define VT1603_R2c  0x2c
+#define VT1603_R2d  0x2d
+#define VT1603_R40  0x40
+#define VT1603_R41  0x41
+#define VT1603_R42  0x42
+#define VT1603_R47  0x47
+#define VT1603_R51  0x51
+#define VT1603_R52  0x52
+#define VT1603_R53  0x53
+#define VT1603_R5f  0x5f
+#define VT1603_R60  0x60
+#define VT1603_R61  0x61
+#define VT1603_R62  0x62
+#define VT1603_R63  0x63
+#define VT1603_R64  0x64
+#define VT1603_R65  0x65
+#define VT1603_R66  0x66
+#define VT1603_R67  0x67
+#define VT1603_R68  0x68
+#define VT1603_R69  0x69
+#define VT1603_R6a  0x6a
+#define VT1603_R6b  0x6b
+#define VT1603_R6d  0x6d
+#define VT1603_R6e  0x6e
+#define VT1603_R70  0x70
+#define VT1603_R71  0x71
+#define VT1603_R72  0x72
+#define VT1603_R73  0x73
+#define VT1603_R77  0x77
+#define VT1603_R79  0x79
+#define VT1603_R7a  0x7a
+#define VT1603_R7b  0x7b
+#define VT1603_R7c  0x7c
+#define VT1603_R82  0x82
+#define VT1603_R87  0x87
+#define VT1603_R88  0x88
+#define VT1603_R8a  0x8a
+#define VT1603_R8e  0x8e
+#define VT1603_R90  0x90
+#define VT1603_R91  0x91
+#define VT1603_R92  0x92
+#define VT1603_R93  0x93
+#define VT1603_R95  0x95
+#define VT1603_R96  0x96
+#define VT1603_R97  0x97
+
+extern int wmt_getsyspara(char *varname,char *varval, int *varlen);
+
+static int vt1603_spi_write(u8 addr, const u8 data)
+{
+	u8 wbuf[3], rbuf[3];
+
+	wbuf[0] = ((addr & 0xFF) | BIT7);
+	wbuf[1] = ((addr & 0xFF) >> 7);
+	wbuf[2] = data;
+
+	spi_write_then_read_data(wbuf, rbuf, sizeof(wbuf),
+				 SPI_MODE_3, 0);
+
+	udelay(10);
+	return 0;
+}
+
+static int vt1603_spi_read(u8 addr, u8 *data)
+{
+	u8 wbuf[5] = {0};
+	u8 rbuf[5] = {0};
+
+	memset(wbuf,0,sizeof(wbuf));
+	memset(rbuf,0,sizeof(rbuf));
+
+	wbuf[0] = ((addr & 0xFF) & (~BIT7));
+	wbuf[1] = ((addr & 0xFF) >> 7);
+
+	spi_write_then_read_data(wbuf, rbuf, sizeof(wbuf),
+				 SPI_MODE_3, 0);
+
+	if (0) {
+		int i;
+		for (i = 0; i < sizeof(rbuf); i++)
+			printf("0x%02x ", rbuf[i]);
+		printf("\n");
+	}
+	data[0] = rbuf[4];
+	return 0;
+}
+
+static inline void i2s_pin_config(void)
+{
+	/* disable GPIO and Pull Down mode */
+	GPIO_CTRL_GP10_I2S_BYTE_VAL &= ~0xFF;
+	GPIO_CTRL_GP11_I2S_BYTE_VAL &= ~(BIT0 | BIT1 | BIT2);
+
+	PULL_EN_GP10_I2S_BYTE_VAL &= ~0xFF;
+	PULL_EN_GP11_I2S_BYTE_VAL &= ~(BIT0 | BIT1 | BIT2);
+
+	/* set to 2ch input, 2ch output */
+	PIN_SHARING_SEL_4BYTE_VAL &= ~(BIT13 | BIT14 | BIT15 | BIT17 | BIT19 | BIT20 | BIT22);
+	PIN_SHARING_SEL_4BYTE_VAL |= (BIT1 | BIT16 | BIT18 | BIT21);
+}
+
+static inline void i2s_clk_config(void)
+{
+	/* set to 11.288MHz */
+	auto_pll_divisor(DEV_I2S, CLK_ENABLE , 0, 0);
+	auto_pll_divisor(DEV_I2S, SET_PLLDIV, 1, 11288);
+
+	/* Enable BIT4:ARFP clock, BIT3:ARF clock */
+	PMCEU_VAL |= (BIT4 | BIT3);
+
+	/* Enable BIT2:AUD clock */
+	PMCE3_VAL |= BIT2;
+}
+
+void vt1603_snd_init(void)
+{
+	u8 data = 0;
+	int ret = 0;
+	char buf[512] = {0};
+	int buflen = 512;
+	unsigned long val = 0;
+	int need_on = 0;
+	printf("vt1603_snd_init need on!!\n");
+	if(wmt_getsyspara("wmt.vt1603.out_on", buf, &buflen) == 0) {
+		val = simple_strtoul(buf, NULL, 10);
+		
+		need_on = (int)val;
+		
+	}
+	else
+		need_on = 0;
+	if (!need_on)
+		return;
+	
+	i2s_pin_config();
+	i2s_clk_config();
+	
+	printf("vt1603_snd_init need on!!\n");	
+#if 0
+	u8 tmp = 0;
+	vt1603_spi_read(VT1603_R68, &data);
+	vt1603_spi_read(VT1603_R68, &tmp);
+	
+	int i = 0;
+	for (i=0; i<12; i++)
+	{
+		vt1603_spi_write(VT1603_R68, i);
+		vt1603_spi_read(VT1603_R68, &tmp);
+		
+		printf("write %d, read back %d\n", i, tmp);
+	}
+#endif	
+	//hp on
+	ret = vt1603_spi_read(VT1603_R68, &data);
+	data &= ~(1<<4);
+	vt1603_spi_write(VT1603_R68, data);
+	
+	printf("<<<<%s write %d,",__func__,data);
+	ret = vt1603_spi_read(VT1603_R68, &data);
+	printf("read back %d\n", data);
+	
+	ret = vt1603_spi_read(VT1603_R69, &data);
+	data |= 1<<2;
+	vt1603_spi_write(VT1603_R69, data);
+	
+	printf("<<<<%s write %d,",__func__,data);
+	ret = vt1603_spi_read(VT1603_R69, &data);
+	printf("read back %d\n", data);
+	
+	ret = vt1603_spi_read(VT1603_R69, &data);
+	data |= 1<<5;
+	vt1603_spi_write(VT1603_R69, data);
+	
+	printf("<<<<%s write %d,",__func__,data);
+	ret = vt1603_spi_read(VT1603_R69, &data);
+	printf("read back %d\n", data);
+	
+	//spk on
+	ret = vt1603_spi_read(VT1603_R25, &data);
+	data |= 1<<1;
+	vt1603_spi_write(VT1603_R25, data);
+	
+	printf("<<<<%s write %d,",__func__,data);
+	ret = vt1603_spi_read(VT1603_R25, &data);
+	printf("read back %d\n", data);
+	
+	ret = vt1603_spi_read(VT1603_R90, &data);
+	data |= 1<<5;
+	vt1603_spi_write(VT1603_R90, data);
+	
+	printf("<<<<%s write %d,",__func__,data);
+	ret = vt1603_spi_read(VT1603_R90, &data);
+	printf("read back %d\n", data);
+	
+	ret = vt1603_spi_read(VT1603_R90, &data);
+	data |= 1<<3;
+	vt1603_spi_write(VT1603_R90, data);
+	
+	printf("<<<<%s write %d,",__func__,data);
+	ret = vt1603_spi_read(VT1603_R90, &data);
+	printf("read back %d\n", data);
+	
+	
+	
+	
+}
+
diff --git a/board/wmt/wmt.c b/board/wmt/wmt.c
new file mode 100755
index 0000000..fe5778f
--- /dev/null
+++ b/board/wmt/wmt.c
@@ -0,0 +1,76 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#include <common.h>
+#if defined(CONFIG_WMT)
+#include <./configs/wmt.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+		"subs %0, %1, #1\n"
+		"bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_WMT;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+/* this speeds up your boot a quite a bit.  However to make it
+ *  work, you need make sure your kernel startup flush bug is fixed.
+ *  ... rkw ...
+ */
+	icache_enable();
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	/* currently empty */
+	return 0;
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+/* Dummy function to avoid linker complaints */
+void __aeabi_unwind_cpp_pr0(void)
+{
+}
diff --git a/board/wmt/wmt_battery/charger/g2214/g2214_charger.c b/board/wmt/wmt_battery/charger/g2214/g2214_charger.c
new file mode 100755
index 0000000..053bd7e
--- /dev/null
+++ b/board/wmt/wmt_battery/charger/g2214/g2214_charger.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (C) 2013  WonderMedia Technologies, Inc.  
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/errno.h>
+
+#include "../../../include/wmt_pmc.h"
+#include "../../../include/wmt_spi.h"
+#include "../../../include/wmt_clk.h"
+#include "../../../include/wmt_gpio.h"
+#include "../../../include/common_def.h"
+#include "../../../include/wmt_iomux.h"
+
+#include "../../wmt_battery.h"
+
+#define I2C_M_WR                0x00
+#define I2C_M_RD                0x01
+
+struct i2c_msg_s {
+	unsigned short addr;	// slave address
+	unsigned short flags;	// flags
+	unsigned short len;	// msg length
+	unsigned char *buf;	// pointer to msg data
+};
+
+#define SECURITY_KEY	0x5A	//i2c read/write 
+
+#define	G2214_I2C_SLAVE_ADDRESS	(0x12)
+
+#define REG_A0     0x00
+#define REG_A1     0x01
+#define REG_A2     0x02
+#define REG_A3     0x03
+#define REG_A4     0x04
+#define REG_A5     0x05
+#define REG_A6     0x06
+#define REG_A7     0x07
+#define REG_A8     0x08
+#define REG_A9     0x09
+#define REG_A10    0x0A
+#define REG_A11    0x0B
+#define REG_A12    0x0C
+#define REG_A13    0x0D
+
+static struct g2214_charger {
+	int		ac_online;
+	int		batt_full;
+
+	union {
+		struct {
+			unsigned int cable_type:4;
+			unsigned int current_sw_mode:1;
+			unsigned int pc_charging:1;
+		};
+		uint32_t flag;
+	};
+
+	int		iset_dcin;
+	int		iset_vbus;
+	int		vseta;
+	int		iseta_small;
+	int		iseta_large;
+	int		safety_time;
+	int		otg_power;
+} g_charger;
+
+extern int wmt_i2c_transfer(struct i2c_msg_s msgs[], int num, int adap_id);
+
+static int g2214_read(struct g2214_charger *ch, u8 reg)
+{
+	int status;
+	unsigned char ret;
+	unsigned char data[2] = {
+		reg,
+		SECURITY_KEY,
+	};
+
+	struct i2c_msg_s msg_buf1[2] = {
+		{ G2214_I2C_SLAVE_ADDRESS, I2C_M_WR, 1,	&data[0],},
+		{ G2214_I2C_SLAVE_ADDRESS, I2C_M_RD, 1,	&ret, },
+	};
+	struct i2c_msg_s msg_buf2[2] = {
+		{ G2214_I2C_SLAVE_ADDRESS, I2C_M_WR, 2, &data[0], },
+		{ G2214_I2C_SLAVE_ADDRESS, I2C_M_RD, 1, &ret, },
+	};
+
+	if (reg < 0x80) {
+		status = wmt_i2c_transfer(msg_buf1, 2, 3);
+	} else {
+		status = wmt_i2c_transfer(msg_buf2, 2, 3);
+	}
+
+	if (status > 0) {
+		return ret;
+	}
+	return (-1);
+}
+
+static int g2214_write(struct g2214_charger *ch, u8 reg, int rt_value)
+{
+	int status;
+	unsigned char data1[2];
+	struct i2c_msg_s msg_buf[1] = {
+		{
+			.addr = G2214_I2C_SLAVE_ADDRESS,
+			.flags = I2C_M_WR,
+			.len = 2,
+			.buf = data1,
+		},
+	};
+
+	data1[0] = reg;
+	data1[1] = rt_value;
+
+	status = wmt_i2c_transfer(&msg_buf[0], 1, 3);
+	if (status > 0) {
+		return (0);
+	}
+	pr_debug(" ## i2c error %s, %d\n", __func__, __LINE__);
+	return (-1);
+}
+
+static inline void g2214_enotg_config(struct g2214_charger *ch, int enable)
+{
+	int val = g2214_read(ch, REG_A8);
+	if (enable)
+		val |= BIT3;
+	else
+		val &= ~BIT3;
+	pr_debug(" ## %s, %d: REG_A8 = 0x%x\n", __func__, __LINE__, val);
+	g2214_write(ch, REG_A8, val);
+}
+
+static inline void g2214_vseta_init(struct g2214_charger *ch)
+{
+	int val, vseta;
+
+	if (ch->vseta <= 4150)
+		vseta = 0;
+	else if (ch->vseta <= 4150)
+		vseta = 1;
+	else if (ch->vseta <= 4200)
+		vseta = 2;
+	else
+		vseta = 3;
+
+	val = g2214_read(ch, REG_A8);
+	val &= ~(3 << 6);
+	val |= vseta << 6;
+	pr_debug(" ## %s, %d: REG_A8 = 0x%x\n", __func__, __LINE__, val);
+	g2214_write(ch, REG_A8, val);
+}
+
+static inline void g2214_iset_config(struct g2214_charger *ch, int large_current)
+{
+	int iset_dcin, iset_vbus, iseta, charging_current;
+
+	if (ch->iset_dcin <= 1000)
+		iset_dcin = 0;
+	else if (ch->iset_dcin <= 1500)
+		iset_dcin = 1;
+	else if (ch->iset_dcin <= 2000)
+		iset_dcin = 2;
+	else
+		iset_dcin = 3;
+
+	if (ch->iset_vbus <= 95)
+		iset_vbus = 0;
+	else if (ch->iset_vbus < 475)
+		iset_vbus = 1;
+	else if (ch->iset_vbus <= 950)
+		iset_vbus = 2;
+	else
+		iset_vbus = 3;
+
+	charging_current = (large_current) ? ch->iseta_large : ch->iseta_small;
+	if (charging_current < 300 || charging_current > 1800)
+		iseta = 2;
+	else
+		iseta = ((charging_current - 300) / 100);
+
+	pr_debug(" ## %s, %d: REG_A5 = 0x%x\n",
+		 __func__, __LINE__, iset_dcin << 6 | iset_vbus << 4 | iseta);
+	g2214_write(ch, REG_A5, iset_dcin << 6 | iset_vbus << 4 | iseta);
+}
+
+static void g2214_endpm_config(struct g2214_charger *ch, int en)
+{
+	int val = g2214_read(ch, REG_A0);
+	if (en)
+		val |= BIT3;
+	else
+		val &= ~BIT3;
+	pr_debug(" ## %s, %d: REG_A0 = 0x%x\n", __func__, __LINE__, val);
+	g2214_write(ch, REG_A0, val);
+}
+
+static void g2214_safety_time_init(struct g2214_charger *ch)
+{
+	int val;
+	int safety_time = ch->safety_time - 1;
+
+	if (safety_time < 0)
+		safety_time = 0;
+	else if (safety_time > 16)
+		safety_time = 15;
+
+	val = g2214_read(ch, REG_A6);
+	val &= (~(BIT4 | BIT5 | BIT6 | BIT7));
+	val |= (safety_time << 4);
+	pr_debug(" ## %s, %d: REG_A6 = 0x%x\n", __func__, __LINE__, val);
+	g2214_write(ch, REG_A6, val);
+}
+
+static void g2214_regs_dump(struct g2214_charger *ch)
+{
+	int reg;
+	for (reg = REG_A0; reg <= REG_A13; reg++)
+		printf(" ## reg A%d: 0x%02x\n", reg, g2214_read(ch, reg));
+}
+
+static int g2214_reg_init(struct g2214_charger *ch)
+{
+	pr_debug(" ## %s, %d\n", __func__, __LINE__);
+	g2214_write(ch, REG_A9,0xFF);
+	g2214_write(ch, REG_A11,0xFF);
+	g2214_write(ch, REG_A12,0x00);
+
+	g2214_vseta_init(ch);
+	g2214_safety_time_init(ch);
+	g2214_enotg_config(ch, 0);
+	g2214_iset_config(ch, 0);
+	g2214_endpm_config(ch, 1);
+	g2214_regs_dump(ch);
+	return 0;
+}
+
+static int parse_charger_param(void)
+{
+	static const char uboot_env[] = "wmt.charger.param";
+	enum {
+		idx_flag,	// dex
+		idx_iset_dcin,
+		idx_iset_vbus,
+		idx_vseta,
+		idx_iseta_small,
+		idx_iseta_large,
+		idx_safety_time,
+		idx_otg_power,
+		idx_max,
+	};
+	char *p, *endp;
+	long ps[idx_max];
+	int i = 0, base = 16;
+	struct g2214_charger *ch = &g_charger;
+
+	if (!(p = getenv((char *)uboot_env)))
+		return -EINVAL;
+
+	if (strncmp(p, "g2214:", 6))
+		return -EINVAL;
+	p += 6;
+
+	while (i < idx_max) {
+		ps[i++] = simple_strtoul(p, &endp, base);
+		if (*endp == '\0')
+			break;
+		p = endp + 1;
+		if (*p == '\0')
+			break;
+		base = 10;
+	}
+
+	ch->flag	= ps[idx_flag];
+	ch->iset_dcin	= ps[idx_iset_dcin];
+	ch->iset_vbus	= ps[idx_iset_vbus];
+	ch->vseta	= ps[idx_vseta];
+	ch->iseta_small	= ps[idx_iseta_small];
+	ch->iseta_large	= ps[idx_iseta_large];
+	ch->safety_time	= ps[idx_safety_time];
+	ch->otg_power	= ps[idx_otg_power];
+
+	if (ch->cable_type != CABLE_TYPE_DC &&
+	    ch->cable_type != CABLE_TYPE_USB) {
+		printf("unkonw cable type %d\n", ch->cable_type);
+		return -EINVAL;
+	}
+
+	printf("charger match g2214, %s cable, dcin %d mA, vbus %d mA, %d mV\n"
+	       "charging current %d~%d mA %d hour, %s otg power\n",
+	       (ch->cable_type == CABLE_TYPE_DC) ? "DC" : "USB",
+	       ch->iset_dcin, ch->iset_vbus, ch->vseta,
+	       ch->iseta_small, ch->iseta_large,
+	       ch->safety_time, ch->otg_power ? "switch" : "no");
+
+	return 0;
+}
+
+static int g2214_chg_init(void)
+{
+	if (parse_charger_param())
+		return -EINVAL;
+
+	return g2214_reg_init(&g_charger);
+}
+
+static enum cable_type g2214_cable_type(void)
+{
+	return g_charger.cable_type;
+}
+
+static int g2214_check_full(void)
+{
+	uint8_t a12 = g2214_read(&g_charger, REG_A12);
+	return !!(a12 & 0x10);
+}
+
+static int g2214_pc_charging(void)
+{
+	return g_charger.pc_charging;
+}
+
+static int __set_small_current(void)
+{
+	g2214_iset_config(&g_charger, 0);
+	return 0;
+}
+
+static int __set_large_current(void)
+{
+	g2214_iset_config(&g_charger, 1);
+	return 0;
+}
+
+static int do_g2214(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i;
+	for (i = 0; i <= 13; i++)
+		printf(" reg%02d 0x%02x\n", i, g2214_read(&g_charger, i));
+	return 0;
+}
+
+U_BOOT_CMD(g2214,	1,	1,	do_g2214,
+	   "g2214\n", NULL);
+
+static int g2214_event_proc(enum event_type event)
+{
+	switch (event) {
+	case POWER_EVENT_DCDET_ADAPTER:
+	case POWER_EVENT_CHARGING:
+		return __set_large_current();
+
+	case POWER_EVENT_DCDET_USBPC:
+		return __set_small_current();
+
+	case POWER_EVENT_DCDET_PLUGOUT:
+	case POWER_EVENT_DISCHARGING:
+		return __set_small_current();
+
+	case POWER_EVENT_CHARGING_FULL:
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+static void parse_default_param(void)
+{
+	struct g2214_charger *ch = &g_charger;
+	ch->flag	= 0;
+	ch->iset_dcin	= 1500;
+	ch->iset_vbus	= 1800;
+	ch->vseta	= 4200;
+	ch->iseta_small	= 400;
+	ch->iseta_large	= 800;
+	ch->safety_time	= 8;
+	ch->otg_power	= 0;
+}
+
+int is_g2214_avail(void)
+{
+	return g2214_read(&g_charger, REG_A0);
+}
+
+int g2214_pmic_init(void)
+{
+	parse_default_param();
+	g2214_reg_init(&g_charger);
+	return 0;
+}
+
+struct charger_dev g2214_charger_dev = {
+	.name		= "g2214",
+	.init		= g2214_chg_init,
+	.cable_type	= g2214_cable_type,
+	.check_full	= g2214_check_full,
+	.event_proc	= g2214_event_proc,
+	.pc_charging	= g2214_pc_charging,
+};
+
diff --git a/board/wmt/wmt_battery/charger/mp2625/mp2625_charger.c b/board/wmt/wmt_battery/charger/mp2625/mp2625_charger.c
new file mode 100755
index 0000000..e1e466f
--- /dev/null
+++ b/board/wmt/wmt_battery/charger/mp2625/mp2625_charger.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2013  WonderMedia Technologies, Inc.  
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/errno.h>
+
+#include "../../../include/wmt_iomux.h"
+#include "../../../include/common_def.h"
+
+#include "../../wmt_battery.h"
+
+struct mp2625_charger {
+	union {
+		struct {
+			unsigned int cable_type:4;
+			unsigned int current_sw_mode:1;
+			unsigned int pc_charging:1;
+		};
+		uint32_t flag;
+	};
+
+	int full_pin;
+	int full_level;
+	int current_pin;
+	int current_large_level;
+};
+
+static struct mp2625_charger charger = {
+	.full_pin		= -1,
+	.full_level		= -1,
+	.current_pin		= -1,
+	.current_large_level	= -1,
+};
+
+static inline int __set_large_current(void)
+{
+	if (gpio_is_valid(charger.current_pin))
+		return gpio_direction_output(charger.current_pin,
+					     charger.current_large_level);
+	else
+		return -EIO;
+}
+
+static inline int __set_small_current(void)
+{
+	if (gpio_is_valid(charger.current_pin))
+		return gpio_direction_output(charger.current_pin,
+					     !charger.current_large_level);
+	else
+		return -EIO;
+}
+
+static int parse_charger_param(void)
+{
+	static const char uboot_env[] = "wmt.charger.param";
+	enum {
+		idx_type,
+		idx_full,
+		idx_full_l,
+		idx_curr,
+		idx_curr_l,
+		idx_max,
+	};
+	char *p, *endp;
+	long ps[idx_max];
+	int i = 0, base = 16;
+	
+	if (!(p = getenv((char *)uboot_env))) {
+		printf("please setenv %s\n", uboot_env);
+		return -EINVAL;
+	}
+
+	if ((strncmp(p, "mp2625:", 7)))
+		return -EINVAL;
+	p += 7;
+
+	while (i < idx_max) {
+		ps[i++] = simple_strtol(p, &endp, base);
+		if (*endp == '\0')
+			break;
+		p = endp + 1;
+
+		if (*p == '\0')
+			break;
+		base = 10;
+	}
+	charger.flag			= ps[0];
+	charger.full_pin		= ps[1];
+	charger.full_level		= ps[2];
+	charger.current_pin		= ps[3];
+	charger.current_large_level	= ps[4];
+
+	printf("charger type %s, full_pin %d(%d), current_pin %d(%d)\n",
+	       (charger.cable_type == CABLE_TYPE_DC) ? "DC" : "USB",
+	       charger.full_pin, charger.full_level,
+	       charger.current_pin, charger.current_large_level);
+
+	if (gpio_is_valid(charger.full_pin))
+		gpio_direction_input(charger.full_pin);
+	__set_small_current();
+	return 0;
+}
+
+static int mp2625_chg_init(void)
+{
+	return parse_charger_param();
+}
+
+static enum cable_type mp2625_cable_type(void)
+{
+	return charger.cable_type;
+}
+
+static int mp2625_check_full(void)
+{
+	if (gpio_is_valid(charger.full_pin))
+		return (gpio_get_value(charger.full_pin) == charger.full_level);
+	else
+		return -EIO;
+}
+
+static int mp2625_pc_charging(void)
+{
+	return charger.pc_charging;
+}
+
+static int mp2625_event_proc(enum event_type event)
+{
+	switch (event) {
+	case POWER_EVENT_DCDET_ADAPTER:
+	case POWER_EVENT_CHARGING:
+		return __set_large_current();
+
+	case POWER_EVENT_DCDET_USBPC:
+		return __set_small_current();
+
+	case POWER_EVENT_DCDET_PLUGOUT:
+		return __set_small_current();
+
+	case POWER_EVENT_CHARGING_FULL:
+		return 0;
+
+	default:
+		return -EINVAL;
+	}
+}
+
+// export for extern interface.
+struct charger_dev mp2625_charger_dev = {
+	.name			= "mp2625",
+	.init			= mp2625_chg_init,
+	.cable_type		= mp2625_cable_type,
+	.check_full		= mp2625_check_full,
+	.event_proc		= mp2625_event_proc,
+	.pc_charging		= mp2625_pc_charging,
+};
+
diff --git a/board/wmt/wmt_battery/gauge/bq27541/bq_battery_i2c.c b/board/wmt/wmt_battery/gauge/bq27541/bq_battery_i2c.c
new file mode 100755
index 0000000..5a7521f
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/bq27541/bq_battery_i2c.c
@@ -0,0 +1,133 @@
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/errno.h>
+#include "../../../include/i2c.h"
+#include "../../wmt_battery.h"
+#include "bq_battery_i2c.h"
+#define I2C_BUS_ID 3
+
+static int i2c_bus = I2C_BUS_ID;
+
+static short bq_battery_read_voltage(void);
+static short bq_battery_read_current(void);
+
+static int bq_i2c_read(unsigned char reg, unsigned char *rt_value, unsigned int len)
+{
+	struct i2c_msg_s msg[1];
+	unsigned char data[2];
+	int err;
+
+	msg->addr = BQ_I2C_DEFAULT_ADDR;
+	msg->flags = 0;
+	msg->len = 1;
+	msg->buf = data;
+
+	data[0] = reg;
+	err = wmt_i2c_transfer(msg, 1, i2c_bus);
+
+	if (err >= 0) {
+		msg->len = len;
+		msg->flags = I2C_M_RD; 
+		msg->buf = rt_value;
+		err = wmt_i2c_transfer(msg, 1, i2c_bus);
+	}
+	return err;
+}
+
+static int bq_batt_init(void)
+{
+	char *env, *p;
+	char *endp;
+	p = env = getenv("wmt.battery.param");
+	if (!p)
+		return -EINVAL;
+	
+	if (prefixcmp(p, "bq27xx"))
+		return -EINVAL;
+
+	p = strchr(env, ':');
+	p++;
+	i2c_bus = simple_strtol(p, &endp, 10);
+
+	return 0;
+}
+
+static short bq_battery_read_capacity(void)
+{
+	short ret = 0;
+	unsigned char value[2] = {0};
+    bq_i2c_read(BQ_REG_NAC, value, 2);
+	ret = value[1] << 8 | value[0];
+	
+	//printf("%s %d\n",__FUNCTION__,ret);
+    return ret;	
+}
+
+static short bq_battery_read_temperature(void)
+{
+	short ret = 0;
+	unsigned char value[2] = {0};
+    bq_i2c_read(BQ_REG_TEMP, value, 2);
+	ret = (value[1] << 8 | value[0]) - 2731;
+    return ret;	
+}
+
+static unsigned short bq_battery_read_percentage(void)
+{
+	unsigned short ret = 0;
+	unsigned char value[2];
+	value[0] = 0;
+	value[1] = 0;
+    bq_i2c_read(BQ_REG_SOC, value, 2);
+	ret = value[1] << 8 | value[0];
+	printf("Current percentage: %d\%\n", ret);
+	printf("Voltage: %dmV\n", bq_battery_read_voltage());
+	printf("Current: %dmA\n", bq_battery_read_current());
+	printf("temperature: %d\n", bq_battery_read_temperature());
+	printf("capacity: %d\n", bq_battery_read_capacity());
+	
+	return ret;
+}
+
+static short bq_battery_read_voltage(void)
+{
+	short ret = 0;
+	unsigned char value[2] = {0};
+    bq_i2c_read(BQ_REG_VOLT, value, 2);
+	ret = (value[1] << 8 | value[0]) * 2;
+	
+    return ret;	
+}
+
+static short bq_battery_read_current(void)
+{
+	short ret = 0;
+	unsigned char value[2] = {0};
+    bq_i2c_read(BQ_REG_AI, value, 2);
+	ret = value[1] << 8 | value[0];
+	
+    return ret;	
+}
+
+static int bq_check_bl(void)
+{
+	int percentage = bq_battery_read_percentage();
+
+	if (percentage < 0)
+		return -1;
+	return (percentage < 3);
+}
+
+
+
+struct battery_dev bq_battery_dev = {
+		.name		= "bq27xx",
+		.is_gauge	= 1,
+		.init		= bq_batt_init,
+		.get_capacity	= bq_battery_read_percentage,
+		.get_voltage	= bq_battery_read_voltage,
+		.get_current	= bq_battery_read_current,
+		.check_batlow	= bq_check_bl,
+};
+
diff --git a/board/wmt/wmt_battery/gauge/bq27541/bq_battery_i2c.h b/board/wmt/wmt_battery/gauge/bq27541/bq_battery_i2c.h
new file mode 100644
index 0000000..e9651e8
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/bq27541/bq_battery_i2c.h
@@ -0,0 +1,11 @@
+#define BQ_REG_FCC			0x12
+#define BQ_REG_TEMP			0x06
+#define BQ_REG_SOC			0x2c
+#define BQ_REG_VOLT			0x08
+#define BQ_REG_NAC			0x0C /* Nominal available capaciy */
+#define BQ_REG_AI			0x14
+
+#define BQ_I2C_BUS                 3
+#define BQ_I2C_DEFAULT_ADDR        0x55
+
+//unsigned short bq_battery_read_percentage(void);
diff --git a/board/wmt/wmt_battery/gauge/sp2541/sp2541_battery.c b/board/wmt/wmt_battery/gauge/sp2541/sp2541_battery.c
new file mode 100755
index 0000000..00a17a9
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/sp2541/sp2541_battery.c
@@ -0,0 +1,220 @@
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/errno.h>
+#include "../../../include/i2c.h"
+#include "../../wmt_battery.h"
+#include "sp2541_battery.h"
+
+static int i2c_bus = I2C_BUS_ID;
+
+static int sp2541_read(u8 cmd, u8 reg, u8 *rt_value, unsigned int len)
+{
+	struct i2c_msg_s msg[2];
+	unsigned char data[2] = {cmd, reg};
+
+	msg[0].addr = SP2541_I2C_ADDR;
+	msg[0].flags = 0;
+	msg[0].len = 2;
+	msg[0].buf = data;
+
+	msg[1].addr = SP2541_I2C_ADDR;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = len;
+	msg[1].buf = rt_value;
+
+	return wmt_i2c_transfer(msg, 2, i2c_bus);
+}
+
+static int sp2541_write(u8 cmd, u8 reg, u8 const buf)
+{
+	struct i2c_msg_s msg;
+	char data[3] = {cmd, reg, buf};
+
+	msg.addr = SP2541_I2C_ADDR;
+	msg.flags = 0;
+	msg.len = 3;
+	msg.buf = data;
+	return wmt_i2c_transfer(&msg, 1, i2c_bus);
+}
+
+static int EEPROM_read_byte(int addr, u8 *data)
+{
+	u8 addr_hi, addr_lo, i;
+	u8 tmp = -1;
+	addr_hi = (addr >> 8) & 0xFF;
+	addr_lo = addr & 0xFF;
+	if (sp2541_write(EEPROM_WRITE_CMD, 0x00, addr_lo) < 0)
+		return -1;
+	if (sp2541_write(EEPROM_WRITE_CMD, 0x01, addr_hi) < 0)
+		return -1;
+	if (sp2541_write(EEPROM_WRITE_CMD, 0x03, 0x06) < 0)
+		return -1;
+	for (i=0; i<10; i++) {
+		sp2541_read(EEPROM_READ_CMD, 0x03, &tmp, 1);
+		if (tmp == 0)
+			break;
+	}
+	if (i == 10)
+		return -1;
+	if (sp2541_read(EEPROM_READ_CMD, 0x02, data, 1) < 0)
+		return -1;
+	return 0;
+}
+
+static int EEPROM_write_byte(int addr, u8 data)
+{
+	u8 addr_hi, addr_lo, i;
+	u8 tmp = -1;
+	addr_hi = (addr >> 8) & 0xFF;
+	addr_lo = addr & 0xFF;
+	if (sp2541_write(EEPROM_WRITE_CMD, 0x00, addr_lo) < 0)
+		return -1;
+	if (sp2541_write(EEPROM_WRITE_CMD, 0x01, addr_hi) < 0)
+		return -1;
+	if (sp2541_write(EEPROM_WRITE_CMD, 0x02, data) < 0)
+		return -1;
+	if (sp2541_write(EEPROM_WRITE_CMD, 0x03, 0x05) < 0)
+		return -1;
+	for (i=0; i<10; i++) {
+		sp2541_read(EEPROM_READ_CMD, 0x03, &tmp, 1);
+		if (tmp == 0)
+			break;
+	}
+	if (i == 10)
+		return -1;
+	return 0;
+}
+
+static int sp2541_init(void)
+{
+	char *env, *p;
+	char *endp;
+	p = env = getenv("wmt.battery.param");
+	if (!p)
+		return -EINVAL;
+	
+	if (prefixcmp(p, "sp2541"))
+		return -EINVAL;
+
+	p = strchr(env, ':');
+	p++;
+	i2c_bus = simple_strtol(p, &endp, 10);
+	if (*endp != ':')
+		return -EINVAL;
+
+	return 0;
+}
+
+static int sp2541_get_capacity(void)
+{
+	unsigned char buf[2];
+	int ret;
+
+	ret = sp2541_read(RAM_READ_CMD,	SP2541_REG_SOC, buf, 2);
+	if (ret<0) {
+		printf("error reading capacity\n");
+		return ret;
+	}
+	ret = buf[0] | buf[1] << 8;
+	printf("Current capacity: %d\%\n", ret);
+	return ret;
+}
+
+static int sp2541_get_voltage(void)
+{
+	unsigned char buf[2];
+	int ret;
+
+	ret = sp2541_read(RAM_READ_CMD,	SP2541_REG_VOLT, buf, 2);
+	if (ret<0) {
+		printf("error reading capacity\n");
+		return ret;
+	}
+	return buf[0] | buf[1] << 8;
+}
+
+static int sp2541_get_current(void)
+{
+	unsigned char buf[2];
+	int ret;
+
+	ret = sp2541_read(RAM_READ_CMD,	SP2541_REG_AI, buf, 2);
+	if (ret<0) {
+		printf("error reading capacity\n");
+		return ret;
+	}
+	return buf[0] | buf[1] << 8;
+}
+
+static int sp2541_check_bl(void)
+{
+	int capacity;
+
+	capacity = sp2541_get_capacity();
+	if (capacity < 0)
+		return -1;
+	return (capacity < 3);
+}
+
+
+struct battery_dev sp2541_battery_dev = {
+		.name		= "sp2541",
+		.is_gauge	= 1,
+		.init		= sp2541_init,
+		.get_capacity	= sp2541_get_capacity,
+		.get_voltage	= sp2541_get_voltage,
+		.get_current	= sp2541_get_current,
+		.check_batlow	= sp2541_check_bl,
+};
+
+
+static int do_sp2541(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i, j;
+	int capacity,voltage,current;
+	u8 data_buf;
+	int eeprom_data;
+	int ret;
+
+	if (sp2541_init())
+		return 0;
+	capacity = sp2541_get_capacity();
+	voltage = sp2541_get_voltage();
+	current = sp2541_get_current();
+	printf("capacity = %d\n", capacity);
+	printf("voltage = %d\n", voltage);
+	printf("current = %d\n", current);
+
+	/*for (i = 0; i < ARRAY_SIZE(default_table); i++) {
+		printf("{0x%x, %d, %x}\n", default_table[i].addr, default_table[i].len, default_table[i].data);
+		for (j = 0; j < default_table[i].len; j++) {
+			data_buf = (default_table[i].data >> (8*(default_table[i].len-j-1))) & 0xFF;
+			ret = EEPROM_write_byte(default_table[i].addr + j, data_buf);
+			if (ret<0) {
+				printf("error write eeprom.\n");
+				return 0;
+			}
+		}
+	}*/
+	for (i = 0; i < ARRAY_SIZE(default_table); i++) {
+		eeprom_data = 0;
+		for (j = 0; j < default_table[i].len; j++) {
+			ret = EEPROM_read_byte(default_table[i].addr + j, &data_buf);
+			if (ret<0) {
+				printf("error read eeprom.\n");
+				return 0;
+			}
+			eeprom_data = (eeprom_data << 8*j) | data_buf;
+		}
+		//printf("{0x%x, %d, %x}\n", default_table[i].addr, default_table[i].len, default_table[i].data);
+		printf("0x%x: %x\n", default_table[i].addr, eeprom_data);
+	}
+	return 0;
+}
+
+U_BOOT_CMD(
+	sp2541,	1,	1,	do_sp2541,
+	"sp2541\n",
+	NULL
+);
diff --git a/board/wmt/wmt_battery/gauge/sp2541/sp2541_battery.h b/board/wmt/wmt_battery/gauge/sp2541/sp2541_battery.h
new file mode 100755
index 0000000..bdb8006
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/sp2541/sp2541_battery.h
@@ -0,0 +1,110 @@
+
+#ifndef __SP2541_BATTERY_H_
+#define __SP2541_BATTERY_H_
+
+
+#define SP2541_I2C_ADDR			0x14
+#define I2C_BUS_ID 3
+
+#define RAM_READ_CMD		0x55
+#define EEPROM_READ_CMD		0xF5
+#define EEPROM_WRITE_CMD	0xFA
+
+#define SP2541_REG_VOLT			0x08
+#define SP2541_REG_AI			0x14
+#define SP2541_REG_SOC			0x2c
+
+struct eeprom_table {
+	unsigned int addr;
+	unsigned int len;
+	int data;
+};
+
+static struct eeprom_table default_table[] = {
+	{0x0120, 1, 0x0D},
+	{0x0121, 1, 0x1B},
+	{0x0122, 1, 0x0E},
+	{0x0123, 1, 0x39},
+	{0x0124, 1, 0x0E},
+	{0x0125, 1, 0x5E},
+	{0x0126, 1, 0x0E},
+	{0x0127, 1, 0x75},
+	{0x0128, 1, 0x0E},
+	{0x0129, 1, 0x93},
+	{0x012A, 1, 0x0E},
+	{0x012B, 1, 0xA9},
+	{0x012C, 1, 0x0E},
+	{0x012D, 1, 0xB3},
+	{0x012E, 1, 0x0E},
+	{0x012F, 1, 0xB7},
+	{0x0130, 1, 0x0E},
+	{0x0131, 1, 0xC2},
+	{0x0132, 1, 0x0E},
+	{0x0133, 1, 0xCF},
+	{0x0134, 1, 0x0E},
+	{0x0135, 1, 0xDF},
+	{0x0136, 1, 0x0E},
+	{0x0137, 1, 0xF5},
+	{0x0138, 1, 0x0F},
+	{0x0139, 1, 0x16},
+	{0x013A, 1, 0x0F},
+	{0x013B, 1, 0x37},
+	{0x013C, 1, 0x0F},
+	{0x013D, 1, 0x55},
+	{0x013E, 1, 0x0F},
+	{0x013F, 1, 0x79},
+	{0x0140, 1, 0x0F},
+	{0x0141, 1, 0x9A},
+	{0x0142, 1, 0x0F},
+	{0x0143, 1, 0xBF},
+	{0x0144, 1, 0x0F},
+	{0x0145, 1, 0xEB},
+	{0x0146, 1, 0x10},
+	{0x0147, 1, 0x1B},
+	{0x0148, 1, 0x10},
+	{0x0149, 1, 0x5A},
+	{0x0150, 1, 0x0C},
+	{0x0151, 1, 0x1D},
+	{0x0152, 1, 0x0D},
+	{0x0153, 1, 0x76},
+	{0x0154, 1, 0x0D},
+	{0x0155, 1, 0xC6},
+	{0x0156, 1, 0x0D},
+	{0x0157, 1, 0xE6},
+	{0x0158, 1, 0x0E},
+	{0x0159, 1, 0x04},
+	{0x015A, 1, 0x0E},
+	{0x015B, 1, 0x18},
+	{0x015C, 1, 0x0E},
+	{0x015D, 1, 0x27},
+	{0x015E, 1, 0x0E},
+	{0x015F, 1, 0x32},
+	{0x0160, 1, 0x0E},
+	{0x0161, 1, 0x3D},
+	{0x0162, 1, 0x0E},
+	{0x0163, 1, 0x4A},
+	{0x0164, 1, 0x0E},
+	{0x0165, 1, 0x5D},
+	{0x0166, 1, 0x0E},
+	{0x0167, 1, 0x70},
+	{0x0168, 1, 0x0E},
+	{0x0169, 1, 0x86},
+	{0x016A, 1, 0x0E},
+	{0x016B, 1, 0xA2},
+	{0x016C, 1, 0x0E},
+	{0x016D, 1, 0xC0},
+	{0x016E, 1, 0x0E},
+	{0x016F, 1, 0xE3},
+	{0x0170, 1, 0x0F},
+	{0x0171, 1, 0x08},
+	{0x0172, 1, 0x0F},
+	{0x0173, 1, 0x37},
+	{0x0174, 1, 0x0F},
+	{0x0175, 1, 0x65},
+	{0x0176, 1, 0x0F},
+	{0x0177, 1, 0x9C},
+	{0x0178, 1, 0x10},
+	{0x0179, 1, 0x5A},
+};
+
+#endif /* #ifndef __SP2541_BATTERY_H_ */
diff --git a/board/wmt/wmt_battery/gauge/upi/Makefile b/board/wmt/wmt_battery/gauge/upi/Makefile
new file mode 100755
index 0000000..0c082a2
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/Makefile
@@ -0,0 +1,47 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# Some descriptions of such software. Copyright (c) 2008 WonderMedia Technologies, Inc.
+#
+# This program is free software: you can redistribute it and/or modify it under the
+# terms of the GNU General Public License as published by the Free Software Foundation,
+# either version 2 of the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+# You should have received a copy of the GNU General Public License along with
+# this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+# WonderMedia Technologies, Inc.
+# 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= libbattupi.a
+
+OBJS	:= uG31xx_API_Measurement.o \
+	uG31xx_API_Otp.o uG31xx_API_System.o \
+	ug31xx_boot.o ug31xx_boot_i2c.o
+	
+#SOBJS	:= lowlevel_init.o
+
+#$(LIB):	$(OBJS) $(SOBJS)
+#	$(AR) crv $@ $^
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_20130809_184039.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_20130809_184039.h
new file mode 100755
index 0000000..06baa26
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_20130809_184039.h
@@ -0,0 +1,233 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 3000

+/// EDVF = 3500

+/// Taper Current = 150

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile[] = {

+    0x5f,0x47,0x47,0x5f,0x33,0xc9,0x00,0x00,

+    0x27,0xf8,0x45,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x6f,0x6e,0x64,

+    0x65,0x72,0x6d,0x65,0x64,0x69,0x61,0x00,

+    0x00,0x00,0x00,0x00,0x43,0x57,0x35,0x30,

+    0x30,0x2d,0x33,0x30,0x30,0x30,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x4d,

+    0x61,0x78,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x5a,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x02,0x01,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0xb8,0x0b,0xac,0x0d,0x14,0x00,

+    0x96,0x00,0x36,0x10,0x3c,0x00,0x06,0x00,

+    0x00,0x00,0x00,0x00,0xe4,0x0c,0x48,0x0d,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x01,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0xe8,0x03,0xe8,0x03,

+    0x00,0x00,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x1e,0x61,0xae,0x5c,0xce,0x57,0x94,0x52,

+    0x14,0x4d,0x6a,0x47,0xac,0x41,0xff,0x3b,

+    0x77,0x36,0x2b,0x31,0x2c,0x2c,0x85,0x27,

+    0x3d,0x23,0x58,0x1f,0xd3,0x1b,0xab,0x18,

+    0xdb,0x15,0x5c,0x13,0x27,0x11,0xe8,0x03,

+    0xbc,0x02,0xc2,0x01,0xc8,0x00,0x00,0x00,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x01,0x00,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x58,

+    0x10,0x37,0x10,0x19,0x10,0xfe,0x0f,0xe5,

+    0x0f,0xcf,0x0f,0xbb,0x0f,0xa9,0x0f,0x98,

+    0x0f,0x87,0x0f,0x75,0x0f,0x5c,0x0f,0x3e,

+    0x0f,0x24,0x0f,0xf5,0x0e,0xac,0x0d,0x68,

+    0x10,0x25,0x10,0xfb,0x0f,0xd3,0x0f,0xab,

+    0x0f,0x85,0x0f,0x62,0x0f,0x41,0x0f,0x23,

+    0x0f,0x0a,0x0f,0xf4,0x0e,0xe3,0x0e,0xd0,

+    0x0e,0xbd,0x0e,0xaa,0x0e,0x96,0x0e,0x80,

+    0x0e,0x67,0x0e,0x51,0x0e,0x2d,0x0e,0xac,

+    0x0d,0x68,0x10,0x25,0x10,0xfb,0x0f,0xd3,

+    0x0f,0xab,0x0f,0x85,0x0f,0x62,0x0f,0x41,

+    0x0f,0x23,0x0f,0x0a,0x0f,0xf4,0x0e,0xe3,

+    0x0e,0xd0,0x0e,0xbd,0x0e,0xaa,0x0e,0x96,

+    0x0e,0x80,0x0e,0x67,0x0e,0x51,0x0e,0x2d,

+    0x0e,0xac,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x64,

+    0x10,0x46,0x10,0x2b,0x10,0x11,0x10,0xfc,

+    0x0f,0xe8,0x0f,0xd6,0x0f,0xc5,0x0f,0xb5,

+    0x0f,0xa4,0x0f,0x8f,0x0f,0x73,0x0f,0x54,

+    0x0f,0x2c,0x0f,0xac,0x0d,0x68,0x10,0x1b,

+    0x10,0xf2,0x0f,0xcb,0x0f,0xa0,0x0f,0x7a,

+    0x0f,0x58,0x0f,0x38,0x0f,0x1d,0x0f,0x04,

+    0x0f,0xef,0x0e,0xde,0x0e,0xcc,0x0e,0xba,

+    0x0e,0xa9,0x0e,0x98,0x0e,0x84,0x0e,0x6d,

+    0x0e,0x57,0x0e,0x31,0x0e,0xac,0x0d,0x68,

+    0x10,0x1b,0x10,0xf2,0x0f,0xcb,0x0f,0xa0,

+    0x0f,0x7a,0x0f,0x58,0x0f,0x38,0x0f,0x1d,

+    0x0f,0x04,0x0f,0xef,0x0e,0xde,0x0e,0xcc,

+    0x0e,0xba,0x0e,0xa9,0x0e,0x98,0x0e,0x84,

+    0x0e,0x6d,0x0e,0x57,0x0e,0x31,0x0e,0xac,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x65,0x10,0x4e,0x10,0x39,

+    0x10,0x26,0x10,0x14,0x10,0x03,0x10,0xf2,

+    0x0f,0xdd,0x0f,0xc3,0x0f,0xa2,0x0f,0x69,

+    0x0f,0xac,0x0d,0x68,0x10,0x00,0x10,0xdb,

+    0x0f,0xbc,0x0f,0x92,0x0f,0x6e,0x0f,0x4e,

+    0x0f,0x30,0x0f,0x16,0x0f,0xfe,0x0e,0xe8,

+    0x0e,0xd8,0x0e,0xc5,0x0e,0xb4,0x0e,0xa3,

+    0x0e,0x93,0x0e,0x7f,0x0e,0x69,0x0e,0x4e,

+    0x0e,0x19,0x0e,0xac,0x0d,0x68,0x10,0x00,

+    0x10,0xdb,0x0f,0xbc,0x0f,0x92,0x0f,0x6e,

+    0x0f,0x4e,0x0f,0x30,0x0f,0x16,0x0f,0xfe,

+    0x0e,0xe8,0x0e,0xd8,0x0e,0xc5,0x0e,0xb4,

+    0x0e,0xa3,0x0e,0x93,0x0e,0x7f,0x0e,0x69,

+    0x0e,0x4e,0x0e,0x19,0x0e,0xac,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x49,0x10,0x06,0x10,0xac,

+    0x0d,0x68,0x10,0x2a,0x10,0xfc,0x0f,0xa3,

+    0x0f,0x59,0x0f,0x35,0x0f,0x1b,0x0f,0xff,

+    0x0e,0xe6,0x0e,0xd2,0x0e,0xc1,0x0e,0xb5,

+    0x0e,0xa9,0x0e,0x9e,0x0e,0x92,0x0e,0x81,

+    0x0e,0x6f,0x0e,0x54,0x0e,0x2f,0x0e,0xf6,

+    0x0d,0xac,0x0d,0x68,0x10,0x2a,0x10,0xfc,

+    0x0f,0xa3,0x0f,0x59,0x0f,0x35,0x0f,0x1b,

+    0x0f,0xff,0x0e,0xe6,0x0e,0xd2,0x0e,0xc1,

+    0x0e,0xb5,0x0e,0xa9,0x0e,0x9e,0x0e,0x92,

+    0x0e,0x81,0x0e,0x6f,0x0e,0x54,0x0e,0x2f,

+    0x0e,0xf6,0x0d,0xac,0x0d,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xc7,0x08,0xb5,

+    0x02,0xbc,0x01,0xb4,0x01,0xa2,0x02,0x4b,

+    0x04,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x6c,

+    0x0c,0xa2,0x03,0x6a,0x03,0x6f,0x03,0xf1,

+    0x01,0xb9,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xa4,0x0c,0x6f,0x04,0xae,0x03,0x34,

+    0x04,0x53,0x00,0x8b,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x83,0x08,0x10,0x03,0x93,

+    0x01,0xc6,0x01,0x1a,0x02,0x9e,0x05,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x6f,0x0d,0x8d,

+    0x03,0xbe,0x03,0x93,0x03,0x91,0x02,0xe3,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xd3,

+    0x0d,0x72,0x04,0x1b,0x04,0xc1,0x04,0x85,

+    0x00,0x87,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xa5,0x07,0x57,0x03,0x14,0x02,0x1e,

+    0x01,0x1c,0x01,0x1c,0x07,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x89,0x0e,0x6e,0x03,0x71,

+    0x03,0x34,0x04,0x76,0x03,0x7e,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x71,0x0f,0x39,

+    0x04,0x19,0x04,0xb1,0x05,0x6e,0x01,0xa0,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x93,

+    0x07,0x3c,0x03,0x19,0x02,0x29,0x02,0x15,

+    0x00,0x06,0x0b,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xf9,0x0e,0x9c,0x03,0x85,0x03,0x77,

+    0x03,0x61,0x04,0xe0,0x03,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x18,0x11,0x5b,0x04,0x47,

+    0x03,0xfe,0x05,0x78,0x03,0x3f,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

+

diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_cw500_20130801_103638.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_cw500_20130801_103638.h
new file mode 100755
index 0000000..672ccb8
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_cw500_20130801_103638.h
@@ -0,0 +1,232 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 4000

+/// EDVF = 3500

+/// Taper Current = 150

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile_cw500 [] = {

+    0x5f,0x47,0x47,0x5f,0xed,0xc9,0x00,0x00,

+    0xb6,0xfa,0x3a,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x6f,0x6e,0x64,

+    0x65,0x72,0x6d,0x65,0x64,0x69,0x61,0x00,

+    0x00,0x00,0x00,0x00,0x43,0x57,0x35,0x30,

+    0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x4d,

+    0x61,0x78,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x5a,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x02,0x01,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0xa0,0x0f,0xac,0x0d,0x14,0x00,

+    0x96,0x00,0x36,0x10,0x3c,0x00,0x06,0x00,

+    0x00,0x00,0x00,0x00,0xe4,0x0c,0x48,0x0d,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x01,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0xe8,0x03,0xe8,0x03,

+    0x00,0x00,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x1e,0x61,0xae,0x5c,0xce,0x57,0x94,0x52,

+    0x14,0x4d,0x6a,0x47,0xac,0x41,0xff,0x3b,

+    0x77,0x36,0x2b,0x31,0x2c,0x2c,0x85,0x27,

+    0x3d,0x23,0x58,0x1f,0xd3,0x1b,0xab,0x18,

+    0xdb,0x15,0x5c,0x13,0x27,0x11,0xe8,0x03,

+    0xbc,0x02,0xc2,0x01,0xc8,0x00,0x00,0x00,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x01,0x00,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x58,

+    0x10,0x37,0x10,0x19,0x10,0xfe,0x0f,0xe5,

+    0x0f,0xcf,0x0f,0xbb,0x0f,0xa9,0x0f,0x98,

+    0x0f,0x87,0x0f,0x75,0x0f,0x5c,0x0f,0x3e,

+    0x0f,0x24,0x0f,0xf5,0x0e,0xac,0x0d,0x68,

+    0x10,0x25,0x10,0xfb,0x0f,0xd3,0x0f,0xab,

+    0x0f,0x85,0x0f,0x62,0x0f,0x41,0x0f,0x23,

+    0x0f,0x0a,0x0f,0xf4,0x0e,0xe3,0x0e,0xd0,

+    0x0e,0xbd,0x0e,0xaa,0x0e,0x96,0x0e,0x80,

+    0x0e,0x67,0x0e,0x51,0x0e,0x2d,0x0e,0xac,

+    0x0d,0x68,0x10,0x25,0x10,0xfb,0x0f,0xd3,

+    0x0f,0xab,0x0f,0x85,0x0f,0x62,0x0f,0x41,

+    0x0f,0x23,0x0f,0x0a,0x0f,0xf4,0x0e,0xe3,

+    0x0e,0xd0,0x0e,0xbd,0x0e,0xaa,0x0e,0x96,

+    0x0e,0x80,0x0e,0x67,0x0e,0x51,0x0e,0x2d,

+    0x0e,0xac,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x64,

+    0x10,0x46,0x10,0x2b,0x10,0x11,0x10,0xfc,

+    0x0f,0xe8,0x0f,0xd6,0x0f,0xc5,0x0f,0xb5,

+    0x0f,0xa4,0x0f,0x8f,0x0f,0x73,0x0f,0x54,

+    0x0f,0x2c,0x0f,0xac,0x0d,0x68,0x10,0x1b,

+    0x10,0xf2,0x0f,0xcb,0x0f,0xa0,0x0f,0x7a,

+    0x0f,0x58,0x0f,0x38,0x0f,0x1d,0x0f,0x04,

+    0x0f,0xef,0x0e,0xde,0x0e,0xcc,0x0e,0xba,

+    0x0e,0xa9,0x0e,0x98,0x0e,0x84,0x0e,0x6d,

+    0x0e,0x57,0x0e,0x31,0x0e,0xac,0x0d,0x68,

+    0x10,0x1b,0x10,0xf2,0x0f,0xcb,0x0f,0xa0,

+    0x0f,0x7a,0x0f,0x58,0x0f,0x38,0x0f,0x1d,

+    0x0f,0x04,0x0f,0xef,0x0e,0xde,0x0e,0xcc,

+    0x0e,0xba,0x0e,0xa9,0x0e,0x98,0x0e,0x84,

+    0x0e,0x6d,0x0e,0x57,0x0e,0x31,0x0e,0xac,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x65,0x10,0x4e,0x10,0x39,

+    0x10,0x26,0x10,0x14,0x10,0x03,0x10,0xf2,

+    0x0f,0xdd,0x0f,0xc3,0x0f,0xa2,0x0f,0x69,

+    0x0f,0xac,0x0d,0x68,0x10,0x00,0x10,0xdb,

+    0x0f,0xbc,0x0f,0x92,0x0f,0x6e,0x0f,0x4e,

+    0x0f,0x30,0x0f,0x16,0x0f,0xfe,0x0e,0xe8,

+    0x0e,0xd8,0x0e,0xc5,0x0e,0xb4,0x0e,0xa3,

+    0x0e,0x93,0x0e,0x7f,0x0e,0x69,0x0e,0x4e,

+    0x0e,0x19,0x0e,0xac,0x0d,0x68,0x10,0x00,

+    0x10,0xdb,0x0f,0xbc,0x0f,0x92,0x0f,0x6e,

+    0x0f,0x4e,0x0f,0x30,0x0f,0x16,0x0f,0xfe,

+    0x0e,0xe8,0x0e,0xd8,0x0e,0xc5,0x0e,0xb4,

+    0x0e,0xa3,0x0e,0x93,0x0e,0x7f,0x0e,0x69,

+    0x0e,0x4e,0x0e,0x19,0x0e,0xac,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x49,0x10,0x06,0x10,0xac,

+    0x0d,0x68,0x10,0x2a,0x10,0xfc,0x0f,0xa3,

+    0x0f,0x59,0x0f,0x35,0x0f,0x1b,0x0f,0xff,

+    0x0e,0xe6,0x0e,0xd2,0x0e,0xc1,0x0e,0xb5,

+    0x0e,0xa9,0x0e,0x9e,0x0e,0x92,0x0e,0x81,

+    0x0e,0x6f,0x0e,0x54,0x0e,0x2f,0x0e,0xf6,

+    0x0d,0xac,0x0d,0x68,0x10,0x2a,0x10,0xfc,

+    0x0f,0xa3,0x0f,0x59,0x0f,0x35,0x0f,0x1b,

+    0x0f,0xff,0x0e,0xe6,0x0e,0xd2,0x0e,0xc1,

+    0x0e,0xb5,0x0e,0xa9,0x0e,0x9e,0x0e,0x92,

+    0x0e,0x81,0x0e,0x6f,0x0e,0x54,0x0e,0x2f,

+    0x0e,0xf6,0x0d,0xac,0x0d,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x4a,0x09,0x00,

+    0x00,0x54,0x01,0x12,0x03,0xe3,0x04,0x4b,

+    0x04,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,

+    0x0c,0xed,0x00,0x02,0x03,0xcd,0x04,0x32,

+    0x04,0xb9,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x27,0x0d,0xba,0x01,0x46,0x03,0x92,

+    0x05,0x94,0x02,0x8b,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x99,0x07,0x00,0x00,0x97,

+    0x00,0xbd,0x02,0x44,0x04,0x9e,0x05,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x86,0x0c,0x7d,

+    0x00,0xc2,0x02,0x8a,0x04,0xbb,0x04,0xe3,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xea,

+    0x0c,0x62,0x01,0x1f,0x03,0xb8,0x05,0xaf,

+    0x02,0x87,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xc1,0x04,0x00,0x00,0xed,0x00,0xe3,

+    0x00,0xf0,0x02,0x1c,0x07,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xa5,0x0b,0x17,0x00,0x4a,

+    0x02,0xf9,0x03,0x4a,0x05,0x7e,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x8e,0x0c,0xe2,

+    0x00,0xf2,0x02,0x76,0x05,0x42,0x03,0xa0,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x08,

+    0x02,0x00,0x00,0x0e,0x00,0x9e,0x00,0x5b,

+    0x01,0x06,0x0b,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x6f,0x09,0x60,0x00,0x7a,0x01,0xec,

+    0x01,0xa7,0x05,0xe0,0x03,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x8d,0x0b,0x1f,0x01,0x3c,

+    0x01,0x73,0x04,0xbe,0x04,0x3f,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_mp718_20131004_070110.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_mp718_20131004_070110.h
new file mode 100755
index 0000000..f0b23b8
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_mp718_20131004_070110.h
@@ -0,0 +1,233 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 6800

+/// EDVF = 3400

+/// Taper Current = 100

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile_mp718 [] = {

+    0x5f,0x47,0x47,0x5f,0x65,0xcb,0x00,0x00,

+    0xb6,0xd6,0x8d,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x6f,0x6e,0x64,

+    0x65,0x72,0x6d,0x65,0x64,0x69,0x61,0x00,

+    0x00,0x00,0x00,0x00,0x4d,0x37,0x31,0x38,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x57,0x6f,

+    0x6e,0x64,0x65,0x72,0x6d,0x65,0x64,0x69,

+    0x61,0x00,0x00,0x00,0x00,0x00,0x53,0x5a,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x01,0x02,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0x90,0x1a,0x48,0x0d,0x14,0x00,

+    0x64,0x00,0x36,0x10,0x3c,0x00,0x06,0x00,

+    0x00,0x00,0x00,0x00,0xe4,0x0c,0x48,0x0d,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x01,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0xe8,0x03,0xe8,0x03,

+    0x00,0x00,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x1e,0x61,0xae,0x5c,0xce,0x57,0x94,0x52,

+    0x14,0x4d,0x6a,0x47,0xac,0x41,0xff,0x3b,

+    0x77,0x36,0x2b,0x31,0x2c,0x2c,0x85,0x27,

+    0x3d,0x23,0x58,0x1f,0xd3,0x1b,0xab,0x18,

+    0xdb,0x15,0x5c,0x13,0x27,0x11,0xe8,0x03,

+    0xbc,0x02,0xc2,0x01,0xc8,0x00,0x00,0x00,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x01,0x00,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x4a,0x10,0x1b,0x10,0xf2,0x0f,0xcc,

+    0x0f,0xaa,0x0f,0x8c,0x0f,0x71,0x0f,0x58,

+    0x0f,0x3e,0x0f,0x27,0x0f,0x17,0x0f,0x09,

+    0x0f,0xfe,0x0e,0xf5,0x0e,0xe3,0x0e,0xc3,

+    0x0e,0xa0,0x0e,0x87,0x0e,0x48,0x0d,0x68,

+    0x10,0x2a,0x10,0xf6,0x0f,0xca,0x0f,0xa1,

+    0x0f,0x7c,0x0f,0x5a,0x0f,0x3b,0x0f,0x1d,

+    0x0f,0xff,0x0e,0xe5,0x0e,0xd2,0x0e,0xc3,

+    0x0e,0xb7,0x0e,0xac,0x0e,0x9d,0x0e,0x88,

+    0x0e,0x68,0x0e,0x49,0x0e,0x1b,0x0e,0x48,

+    0x0d,0x68,0x10,0x2a,0x10,0xf6,0x0f,0xca,

+    0x0f,0xa1,0x0f,0x7c,0x0f,0x5a,0x0f,0x3b,

+    0x0f,0x1d,0x0f,0xff,0x0e,0xe5,0x0e,0xd2,

+    0x0e,0xc3,0x0e,0xb7,0x0e,0xac,0x0e,0x9d,

+    0x0e,0x88,0x0e,0x68,0x0e,0x49,0x0e,0x1b,

+    0x0e,0x48,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x35,0x10,0x09,0x10,0xe3,0x0f,0xc1,

+    0x0f,0xa3,0x0f,0x89,0x0f,0x70,0x0f,0x59,

+    0x0f,0x42,0x0f,0x31,0x0f,0x23,0x0f,0x19,

+    0x0f,0x0f,0x0f,0x00,0x0f,0xe2,0x0e,0xbe,

+    0x0e,0xa3,0x0e,0x48,0x0d,0x68,0x10,0x26,

+    0x10,0xf2,0x0f,0xc4,0x0f,0x9c,0x0f,0x77,

+    0x0f,0x55,0x0f,0x35,0x0f,0x17,0x0f,0xfc,

+    0x0e,0xe5,0x0e,0xd3,0x0e,0xc5,0x0e,0xba,

+    0x0e,0xb1,0x0e,0xa5,0x0e,0x91,0x0e,0x71,

+    0x0e,0x50,0x0e,0x19,0x0e,0x48,0x0d,0x68,

+    0x10,0x26,0x10,0xf2,0x0f,0xc4,0x0f,0x9c,

+    0x0f,0x77,0x0f,0x55,0x0f,0x35,0x0f,0x17,

+    0x0f,0xfc,0x0e,0xe5,0x0e,0xd3,0x0e,0xc5,

+    0x0e,0xba,0x0e,0xb1,0x0e,0xa5,0x0e,0x91,

+    0x0e,0x71,0x0e,0x50,0x0e,0x19,0x0e,0x48,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x54,

+    0x10,0x24,0x10,0xfb,0x0f,0xd8,0x0f,0xba,

+    0x0f,0x9f,0x0f,0x87,0x0f,0x71,0x0f,0x5c,

+    0x0f,0x4a,0x0f,0x3c,0x0f,0x31,0x0f,0x26,

+    0x0f,0x19,0x0f,0xfe,0x0e,0xda,0x0e,0xbe,

+    0x0e,0x48,0x0d,0x68,0x10,0x23,0x10,0xf1,

+    0x0f,0xc1,0x0f,0x97,0x0f,0x71,0x0f,0x4e,

+    0x0f,0x2e,0x0f,0x11,0x0f,0xf8,0x0e,0xe4,

+    0x0e,0xd2,0x0e,0xc5,0x0e,0xba,0x0e,0xb1,

+    0x0e,0xa5,0x0e,0x92,0x0e,0x71,0x0e,0x50,

+    0x0e,0x0c,0x0e,0x48,0x0d,0x68,0x10,0x23,

+    0x10,0xf1,0x0f,0xc1,0x0f,0x97,0x0f,0x71,

+    0x0f,0x4e,0x0f,0x2e,0x0f,0x11,0x0f,0xf8,

+    0x0e,0xe4,0x0e,0xd2,0x0e,0xc5,0x0e,0xba,

+    0x0e,0xb1,0x0e,0xa5,0x0e,0x92,0x0e,0x71,

+    0x0e,0x50,0x0e,0x0c,0x0e,0x48,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x64,

+    0x10,0x36,0x10,0x0d,0x10,0xeb,0x0f,0xcd,

+    0x0f,0xb4,0x0f,0x9e,0x0f,0x8a,0x0f,0x79,

+    0x0f,0x6a,0x0f,0x5e,0x0f,0x53,0x0f,0x46,

+    0x0f,0x2f,0x0f,0x0b,0x0f,0xee,0x0e,0x48,

+    0x0d,0x68,0x10,0x1e,0x10,0xee,0x0f,0xc0,

+    0x0f,0x93,0x0f,0x6c,0x0f,0x47,0x0f,0x28,

+    0x0f,0x0c,0x0f,0xf5,0x0e,0xe1,0x0e,0xd3,

+    0x0e,0xc6,0x0e,0xbb,0x0e,0xb0,0x0e,0xa4,

+    0x0e,0x91,0x0e,0x74,0x0e,0x4b,0x0e,0xf5,

+    0x0d,0x48,0x0d,0x68,0x10,0x1e,0x10,0xee,

+    0x0f,0xc0,0x0f,0x93,0x0f,0x6c,0x0f,0x47,

+    0x0f,0x28,0x0f,0x0c,0x0f,0xf5,0x0e,0xe1,

+    0x0e,0xd3,0x0e,0xc6,0x0e,0xbb,0x0e,0xb0,

+    0x0e,0xa4,0x0e,0x91,0x0e,0x74,0x0e,0x4b,

+    0x0e,0xf5,0x0d,0x48,0x0d,0x68,0x10,0xa0,

+    0x0f,0xd8,0x0e,0x10,0x0e,0x48,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xa0,0x0f,0xd8,0x0e,0x10,0x0e,0x48,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xa0,0x0f,0xd8,0x0e,0x10,

+    0x0e,0x48,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xa0,0x0f,0xd8,

+    0x0e,0x10,0x0e,0x48,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xa0,

+    0x0f,0xd8,0x0e,0x10,0x0e,0x48,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xa0,0x0f,0xd8,0x0e,0x10,0x0e,0x48,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xa0,0x0f,0xd8,0x0e,0x10,

+    0x0e,0x48,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xa0,0x0f,0xd8,

+    0x0e,0x10,0x0e,0x48,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xa0,

+    0x0f,0xd8,0x0e,0x10,0x0e,0x48,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xa0,0x0f,0xd8,0x0e,0x10,0x0e,0x48,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xa0,0x0f,0xd8,0x0e,0x10,

+    0x0e,0x48,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xa0,0x0f,0xd8,

+    0x0e,0x10,0x0e,0x48,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x42,0x1a,0x70,

+    0x01,0x50,0x06,0x08,0x0d,0x78,0x05,0x20,

+    0x01,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf7,

+    0x1a,0x89,0x03,0xd3,0x07,0x7a,0x0d,0x20,

+    0x02,0xb5,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x2d,0x1b,0x75,0x04,0x57,0x08,0x39,

+    0x0d,0x27,0x01,0x9a,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xbf,0x18,0xa1,0x00,0x67,

+    0x05,0xbb,0x0a,0xfa,0x07,0xee,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x4b,0x1a,0xc2,

+    0x02,0x4f,0x07,0xab,0x0d,0x8e,0x02,0xe2,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xcb,

+    0x1a,0xee,0x03,0x17,0x08,0x63,0x0d,0x60,

+    0x01,0xa6,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x84,0x16,0x3a,0x00,0x03,0x04,0x71,

+    0x08,0xd5,0x09,0xda,0x02,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x79,0x19,0x22,0x02,0xbc,

+    0x06,0xa3,0x0d,0xf7,0x02,0x35,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x5b,0x1a,0x69,

+    0x03,0xc1,0x07,0x84,0x0d,0xad,0x01,0xc3,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x22,

+    0x12,0x0c,0x00,0x1c,0x02,0xf3,0x05,0x05,

+    0x0a,0x69,0x06,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x09,0x18,0x57,0x01,0xe5,0x05,0xc1,

+    0x0c,0x0a,0x04,0x05,0x02,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x5d,0x19,0x9a,0x02,0x1e,

+    0x07,0x67,0x0d,0x3c,0x02,0x35,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

+

diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_t73v_20131120_001204.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_t73v_20131120_001204.h
new file mode 100755
index 0000000..4a8ff93
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_t73v_20131120_001204.h
@@ -0,0 +1,233 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 3000

+/// EDVF = 3400

+/// Taper Current = 150

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile_t73v [] = {

+    0x5f,0x47,0x47,0x5f,0x00,0xc6,0x00,0x00,

+    0xd4,0x1b,0xca,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x47,0x6f,0x6f,0x64,

+    0x74,0x69,0x6d,0x65,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x54,0x37,0x33,0x56,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x4c,0x55,

+    0x53,0x54,0x59,0x2d,0x33,0x37,0x37,0x30,

+    0x31,0x30,0x30,0x50,0x4c,0x00,0x31,0x33,

+    0x31,0x30,0x31,0x36,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x02,0x01,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0xb8,0x0b,0x48,0x0d,0x14,0x00,

+    0x96,0x00,0x36,0x10,0x3c,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x74,0x0e,0xd8,0x0e,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x00,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0xe8,0x03,0xe8,0x03,

+    0x00,0x00,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x05,0x62,0x8a,0x5d,0x9c,0x58,0x4c,0x53,

+    0xb3,0x4d,0xeb,0x47,0x15,0x42,0x4b,0x3c,

+    0xc7,0x36,0x80,0x31,0x86,0x2c,0xe5,0x27,

+    0xa2,0x23,0xc0,0x1f,0x3d,0x1c,0x17,0x19,

+    0x47,0x16,0xc6,0x13,0x8e,0x11,0xe8,0x03,

+    0x84,0x03,0xee,0x02,0x58,0x02,0xc2,0x01,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x21,0x38,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x49,0x10,0x23,

+    0x10,0x01,0x10,0xe2,0x0f,0xc8,0x0f,0xb0,

+    0x0f,0x9b,0x0f,0x8a,0x0f,0x7b,0x0f,0x6e,

+    0x0f,0x63,0x0f,0x58,0x0f,0x44,0x0f,0x27,

+    0x0f,0x09,0x0f,0xd8,0x0e,0x48,0x0d,0x68,

+    0x10,0x25,0x10,0xf4,0x0f,0xc7,0x0f,0x9c,

+    0x0f,0x76,0x0f,0x53,0x0f,0x2f,0x0f,0x0e,

+    0x0f,0xf3,0x0e,0xdf,0x0e,0xce,0x0e,0xbf,

+    0x0e,0xb3,0x0e,0xa7,0x0e,0x99,0x0e,0x88,

+    0x0e,0x6f,0x0e,0x53,0x0e,0x24,0x0e,0x48,

+    0x0d,0x68,0x10,0x25,0x10,0xf4,0x0f,0xc7,

+    0x0f,0x9c,0x0f,0x76,0x0f,0x53,0x0f,0x2f,

+    0x0f,0x0e,0x0f,0xf3,0x0e,0xdf,0x0e,0xce,

+    0x0e,0xbf,0x0e,0xb3,0x0e,0xa7,0x0e,0x99,

+    0x0e,0x88,0x0e,0x6f,0x0e,0x53,0x0e,0x24,

+    0x0e,0x48,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x49,0x10,0x23,0x10,0x01,

+    0x10,0xe2,0x0f,0xc8,0x0f,0xb0,0x0f,0x9b,

+    0x0f,0x8a,0x0f,0x7b,0x0f,0x6e,0x0f,0x63,

+    0x0f,0x58,0x0f,0x44,0x0f,0x27,0x0f,0x09,

+    0x0f,0xd8,0x0e,0x48,0x0d,0x68,0x10,0x25,

+    0x10,0xf4,0x0f,0xc7,0x0f,0x9c,0x0f,0x76,

+    0x0f,0x53,0x0f,0x2f,0x0f,0x0e,0x0f,0xf3,

+    0x0e,0xdf,0x0e,0xce,0x0e,0xbf,0x0e,0xb3,

+    0x0e,0xa7,0x0e,0x99,0x0e,0x88,0x0e,0x6f,

+    0x0e,0x53,0x0e,0x24,0x0e,0x48,0x0d,0x68,

+    0x10,0x25,0x10,0xf4,0x0f,0xc7,0x0f,0x9c,

+    0x0f,0x76,0x0f,0x53,0x0f,0x2f,0x0f,0x0e,

+    0x0f,0xf3,0x0e,0xdf,0x0e,0xce,0x0e,0xbf,

+    0x0e,0xb3,0x0e,0xa7,0x0e,0x99,0x0e,0x88,

+    0x0e,0x6f,0x0e,0x53,0x0e,0x24,0x0e,0x48,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x49,0x10,0x23,0x10,0x01,0x10,0xe2,

+    0x0f,0xc8,0x0f,0xb0,0x0f,0x9b,0x0f,0x8a,

+    0x0f,0x7b,0x0f,0x6e,0x0f,0x63,0x0f,0x58,

+    0x0f,0x44,0x0f,0x27,0x0f,0x09,0x0f,0xd8,

+    0x0e,0x48,0x0d,0x68,0x10,0x25,0x10,0xf4,

+    0x0f,0xc7,0x0f,0x9c,0x0f,0x76,0x0f,0x53,

+    0x0f,0x2f,0x0f,0x0e,0x0f,0xf3,0x0e,0xdf,

+    0x0e,0xce,0x0e,0xbf,0x0e,0xb3,0x0e,0xa7,

+    0x0e,0x99,0x0e,0x88,0x0e,0x6f,0x0e,0x53,

+    0x0e,0x24,0x0e,0x48,0x0d,0x68,0x10,0x25,

+    0x10,0xf4,0x0f,0xc7,0x0f,0x9c,0x0f,0x76,

+    0x0f,0x53,0x0f,0x2f,0x0f,0x0e,0x0f,0xf3,

+    0x0e,0xdf,0x0e,0xce,0x0e,0xbf,0x0e,0xb3,

+    0x0e,0xa7,0x0e,0x99,0x0e,0x88,0x0e,0x6f,

+    0x0e,0x53,0x0e,0x24,0x0e,0x48,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x49,

+    0x10,0x23,0x10,0x01,0x10,0xe2,0x0f,0xc8,

+    0x0f,0xb0,0x0f,0x9b,0x0f,0x8a,0x0f,0x7b,

+    0x0f,0x6e,0x0f,0x63,0x0f,0x58,0x0f,0x44,

+    0x0f,0x27,0x0f,0x09,0x0f,0xd8,0x0e,0x48,

+    0x0d,0x68,0x10,0x25,0x10,0xf4,0x0f,0xc7,

+    0x0f,0x9c,0x0f,0x76,0x0f,0x53,0x0f,0x2f,

+    0x0f,0x0e,0x0f,0xf3,0x0e,0xdf,0x0e,0xce,

+    0x0e,0xbf,0x0e,0xb3,0x0e,0xa7,0x0e,0x99,

+    0x0e,0x88,0x0e,0x6f,0x0e,0x53,0x0e,0x24,

+    0x0e,0x48,0x0d,0x68,0x10,0x25,0x10,0xf4,

+    0x0f,0xc7,0x0f,0x9c,0x0f,0x76,0x0f,0x53,

+    0x0f,0x2f,0x0f,0x0e,0x0f,0xf3,0x0e,0xdf,

+    0x0e,0xce,0x0e,0xbf,0x0e,0xb3,0x0e,0xa7,

+    0x0e,0x99,0x0e,0x88,0x0e,0x6f,0x0e,0x53,

+    0x0e,0x24,0x0e,0x48,0x0d,0x68,0x10,0xa0,

+    0x0f,0xd8,0x0e,0x10,0x0e,0x48,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xa0,0x0f,0xd8,0x0e,0x10,0x0e,0x48,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xa0,0x0f,0xd8,0x0e,0x10,

+    0x0e,0x48,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xa0,0x0f,0xd8,

+    0x0e,0x10,0x0e,0x48,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xa0,

+    0x0f,0xd8,0x0e,0x10,0x0e,0x48,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xa0,0x0f,0xd8,0x0e,0x10,0x0e,0x48,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xa0,0x0f,0xd8,0x0e,0x10,

+    0x0e,0x48,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xa0,0x0f,0xd8,

+    0x0e,0x10,0x0e,0x48,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xa0,

+    0x0f,0xd8,0x0e,0x10,0x0e,0x48,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xa0,0x0f,0xd8,0x0e,0x10,0x0e,0x48,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xa0,0x0f,0xd8,0x0e,0x10,

+    0x0e,0x48,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xa0,0x0f,0xd8,

+    0x0e,0x10,0x0e,0x48,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x3b,0x0b,0x66,

+    0x00,0x7d,0x02,0xe4,0x04,0x72,0x03,0x82,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x82,

+    0x0b,0x79,0x01,0x1b,0x03,0x3b,0x06,0xb1,

+    0x00,0x4c,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x96,0x0b,0xe7,0x01,0x69,0x03,0xd9,

+    0x05,0x6c,0x00,0x41,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x3b,0x0b,0x66,0x00,0x7d,

+    0x02,0xe4,0x04,0x72,0x03,0x82,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x82,0x0b,0x79,

+    0x01,0x1b,0x03,0x3b,0x06,0xb1,0x00,0x4c,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x96,

+    0x0b,0xe7,0x01,0x69,0x03,0xd9,0x05,0x6c,

+    0x00,0x41,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x3b,0x0b,0x66,0x00,0x7d,0x02,0xe4,

+    0x04,0x72,0x03,0x82,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x82,0x0b,0x79,0x01,0x1b,

+    0x03,0x3b,0x06,0xb1,0x00,0x4c,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x96,0x0b,0xe7,

+    0x01,0x69,0x03,0xd9,0x05,0x6c,0x00,0x41,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x3b,

+    0x0b,0x66,0x00,0x7d,0x02,0xe4,0x04,0x72,

+    0x03,0x82,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x82,0x0b,0x79,0x01,0x1b,0x03,0x3b,

+    0x06,0xb1,0x00,0x4c,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x96,0x0b,0xe7,0x01,0x69,

+    0x03,0xd9,0x05,0x6c,0x00,0x41,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

+

diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms7320_20130718_200031.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms7320_20130718_200031.h
new file mode 100755
index 0000000..105e0a0
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms7320_20130718_200031.h
@@ -0,0 +1,233 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 4000

+/// EDVF = 3400

+/// Taper Current = 100

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile_wms7320 [] = {

+    0x5f,0x47,0x47,0x5f,0x6d,0xc8,0x00,0x00,

+    0x5f,0x5b,0x2a,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x6f,0x6e,0x64,

+    0x65,0x72,0x6d,0x65,0x64,0x69,0x61,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x4d,0x53,0x37,

+    0x33,0x32,0x30,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x57,0x6f,

+    0x6e,0x64,0x65,0x72,0x6d,0x65,0x64,0x69,

+    0x61,0x00,0x00,0x00,0x00,0x00,0x53,0x5a,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x01,0x02,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0xa0,0x0f,0x48,0x0d,0x14,0x00,

+    0x64,0x00,0x36,0x10,0x3c,0x00,0x06,0x00,

+    0x00,0x00,0x00,0x00,0xe4,0x0c,0x48,0x0d,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x01,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0xe8,0x03,0xe8,0x03,

+    0x00,0x00,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x1e,0x61,0xae,0x5c,0xce,0x57,0x94,0x52,

+    0x14,0x4d,0x6a,0x47,0xac,0x41,0xff,0x3b,

+    0x77,0x36,0x2b,0x31,0x2c,0x2c,0x85,0x27,

+    0x3d,0x23,0x58,0x1f,0xd3,0x1b,0xab,0x18,

+    0xdb,0x15,0x5c,0x13,0x27,0x11,0xe8,0x03,

+    0xbc,0x02,0xc2,0x01,0xc8,0x00,0x00,0x00,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x01,0x00,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x5b,

+    0x10,0x4d,0x10,0x2d,0x10,0x20,0x10,0x0f,

+    0x10,0xff,0x0f,0xe1,0x0f,0xcc,0x0f,0xb2,

+    0x0f,0x99,0x0f,0x4f,0x0f,0x48,0x0d,0x68,

+    0x10,0xdd,0x0f,0xb0,0x0f,0x85,0x0f,0x5f,

+    0x0f,0x3d,0x0f,0x1c,0x0f,0xf9,0x0e,0xcf,

+    0x0e,0xb9,0x0e,0xab,0x0e,0xa4,0x0e,0x9f,

+    0x0e,0x98,0x0e,0x8b,0x0e,0x72,0x0e,0x45,

+    0x0e,0x05,0x0e,0xc9,0x0d,0xa2,0x0d,0x48,

+    0x0d,0x68,0x10,0xdd,0x0f,0xb0,0x0f,0x85,

+    0x0f,0x5f,0x0f,0x3d,0x0f,0x1c,0x0f,0xf9,

+    0x0e,0xcf,0x0e,0xb9,0x0e,0xab,0x0e,0xa4,

+    0x0e,0x9f,0x0e,0x98,0x0e,0x8b,0x0e,0x72,

+    0x0e,0x45,0x0e,0x05,0x0e,0xc9,0x0d,0xa2,

+    0x0d,0x48,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x66,

+    0x10,0x14,0x10,0x48,0x0d,0x68,0x10,0xdd,

+    0x0f,0xb0,0x0f,0x85,0x0f,0x5f,0x0f,0x3d,

+    0x0f,0x1c,0x0f,0xf9,0x0e,0xcf,0x0e,0xb9,

+    0x0e,0xab,0x0e,0xa4,0x0e,0x9f,0x0e,0x98,

+    0x0e,0x8b,0x0e,0x72,0x0e,0x45,0x0e,0x05,

+    0x0e,0xc9,0x0d,0xa2,0x0d,0x48,0x0d,0x68,

+    0x10,0xdd,0x0f,0xb0,0x0f,0x85,0x0f,0x5f,

+    0x0f,0x3d,0x0f,0x1c,0x0f,0xf9,0x0e,0xcf,

+    0x0e,0xb9,0x0e,0xab,0x0e,0xa4,0x0e,0x9f,

+    0x0e,0x98,0x0e,0x8b,0x0e,0x72,0x0e,0x45,

+    0x0e,0x05,0x0e,0xc9,0x0d,0xa2,0x0d,0x48,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x3f,

+    0x10,0x48,0x0d,0x68,0x10,0xdd,0x0f,0xb0,

+    0x0f,0x85,0x0f,0x5f,0x0f,0x3d,0x0f,0x1c,

+    0x0f,0xf9,0x0e,0xcf,0x0e,0xb9,0x0e,0xab,

+    0x0e,0xa4,0x0e,0x9f,0x0e,0x98,0x0e,0x8b,

+    0x0e,0x72,0x0e,0x45,0x0e,0x05,0x0e,0xc9,

+    0x0d,0xa2,0x0d,0x48,0x0d,0x68,0x10,0xdd,

+    0x0f,0xb0,0x0f,0x85,0x0f,0x5f,0x0f,0x3d,

+    0x0f,0x1c,0x0f,0xf9,0x0e,0xcf,0x0e,0xb9,

+    0x0e,0xab,0x0e,0xa4,0x0e,0x9f,0x0e,0x98,

+    0x0e,0x8b,0x0e,0x72,0x0e,0x45,0x0e,0x05,

+    0x0e,0xc9,0x0d,0xa2,0x0d,0x48,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x48,

+    0x0d,0x68,0x10,0xdd,0x0f,0xb0,0x0f,0x85,

+    0x0f,0x5f,0x0f,0x3d,0x0f,0x1c,0x0f,0xf9,

+    0x0e,0xcf,0x0e,0xb9,0x0e,0xab,0x0e,0xa4,

+    0x0e,0x9f,0x0e,0x98,0x0e,0x8b,0x0e,0x72,

+    0x0e,0x45,0x0e,0x05,0x0e,0xc9,0x0d,0xa2,

+    0x0d,0x48,0x0d,0x68,0x10,0xdd,0x0f,0xb0,

+    0x0f,0x85,0x0f,0x5f,0x0f,0x3d,0x0f,0x1c,

+    0x0f,0xf9,0x0e,0xcf,0x0e,0xb9,0x0e,0xab,

+    0x0e,0xa4,0x0e,0x9f,0x0e,0x98,0x0e,0x8b,

+    0x0e,0x72,0x0e,0x45,0x0e,0x05,0x0e,0xc9,

+    0x0d,0xa2,0x0d,0x48,0x0d,0x68,0x10,0xa0,

+    0x0f,0xd8,0x0e,0x10,0x0e,0x48,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xa0,0x0f,0xd8,0x0e,0x10,0x0e,0x48,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xa0,0x0f,0xd8,0x0e,0x10,

+    0x0e,0x48,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xa0,0x0f,0xd8,

+    0x0e,0x10,0x0e,0x48,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xa0,

+    0x0f,0xd8,0x0e,0x10,0x0e,0x48,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xa0,0x0f,0xd8,0x0e,0x10,0x0e,0x48,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xa0,0x0f,0xd8,0x0e,0x10,

+    0x0e,0x48,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xa0,0x0f,0xd8,

+    0x0e,0x10,0x0e,0x48,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xa0,

+    0x0f,0xd8,0x0e,0x10,0x0e,0x48,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xa0,0x0f,0xd8,0x0e,0x10,0x0e,0x48,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xa0,0x0f,0xd8,0x0e,0x10,

+    0x0e,0x48,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xa0,0x0f,0xd8,

+    0x0e,0x10,0x0e,0x48,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xb9,0x07,0x00,

+    0x00,0x7c,0x00,0xaa,0x02,0x91,0x04,0xa2,

+    0x04,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf1,

+    0x0b,0xb2,0x00,0xde,0x02,0xcf,0x04,0x91,

+    0x03,0x9c,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xec,0x0b,0x3b,0x01,0xf1,0x02,0x7f,

+    0x05,0x3f,0x02,0x81,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xe0,0x02,0x00,0x00,0x00,

+    0x00,0x1b,0x00,0xc5,0x02,0xcf,0x0a,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xe8,0x0b,0x00,

+    0x00,0x83,0x01,0xdc,0x03,0x88,0x06,0x4f,

+    0x03,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xbe,

+    0x0d,0x43,0x00,0x72,0x03,0x24,0x07,0xe3,

+    0x02,0x85,0x01,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xe2,0x03,0x00,0x00,0x83,0x00,0xe2,

+    0x02,0x7c,0x00,0x82,0x06,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xa2,0x09,0x49,0x00,0xcc,

+    0x00,0x57,0x03,0x34,0x05,0xb6,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x8a,0x0a,0x61,

+    0x00,0xd6,0x01,0x83,0x05,0xcf,0x02,0xa8,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xb3,

+    0x00,0x00,0x00,0x00,0x00,0x29,0x00,0x89,

+    0x00,0x17,0x04,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xf4,0x04,0x00,0x00,0x58,0x01,0x7c,

+    0x00,0x20,0x03,0x1c,0x07,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xa5,0x09,0xab,0x00,0x38,

+    0x03,0x87,0x00,0x39,0x05,0x6c,0x02,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

+

diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_c7_20130725_164935.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_c7_20130725_164935.h
new file mode 100755
index 0000000..1478984
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_c7_20130725_164935.h
@@ -0,0 +1,232 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 3900

+/// EDVF = 3500

+/// Taper Current = 150

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile_wms8309_c7_3900mAh [] = {

+    0x5f,0x47,0x47,0x5f,0xbb,0xfa,0x00,0x00,

+    0x1f,0x69,0x33,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x6f,0x6e,0x64,

+    0x65,0x72,0x6d,0x65,0x64,0x69,0x61,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x4d,0x53,0x38,

+    0x33,0x30,0x39,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x4d,

+    0x61,0x78,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x5a,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x01,0x02,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0x3c,0x0f,0xac,0x0d,0x14,0x00,

+    0x96,0x00,0x36,0x10,0x3c,0x00,0x06,0x00,

+    0x00,0x00,0x00,0x00,0xe4,0x0c,0x48,0x0d,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x01,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0xe8,0x03,0xe8,0x03,

+    0x00,0x00,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x1e,0x61,0xae,0x5c,0xce,0x57,0x94,0x52,

+    0x14,0x4d,0x6a,0x47,0xac,0x41,0xff,0x3b,

+    0x77,0x36,0x2b,0x31,0x2c,0x2c,0x85,0x27,

+    0x3d,0x23,0x58,0x1f,0xd3,0x1b,0xab,0x18,

+    0xdb,0x15,0x5c,0x13,0x27,0x11,0xe8,0x03,

+    0xbc,0x02,0xc2,0x01,0xc8,0x00,0x00,0x00,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x01,0x00,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x5b,0x10,0x2f,0x10,0x03,0x10,0xde,

+    0x0f,0xbb,0x0f,0x9c,0x0f,0x7e,0x0f,0x62,

+    0x0f,0x4a,0x0f,0x36,0x0f,0x28,0x0f,0x1e,

+    0x0f,0x15,0x0f,0x0a,0x0f,0xf7,0x0e,0xdb,

+    0x0e,0xbe,0x0e,0xa4,0x0e,0xac,0x0d,0x68,

+    0x10,0x38,0x10,0x11,0x10,0xed,0x0f,0xca,

+    0x0f,0xab,0x0f,0x8a,0x0f,0x6e,0x0f,0x52,

+    0x0f,0x39,0x0f,0x22,0x0f,0x65,0x0f,0x57,

+    0x0f,0x4c,0x0f,0x40,0x0f,0x31,0x0f,0x1b,

+    0x0f,0x02,0x0f,0xea,0x0e,0xa0,0x0e,0xac,

+    0x0d,0x68,0x10,0x38,0x10,0x11,0x10,0xed,

+    0x0f,0xca,0x0f,0xab,0x0f,0x8a,0x0f,0x6e,

+    0x0f,0x52,0x0f,0x39,0x0f,0x22,0x0f,0x65,

+    0x0f,0x57,0x0f,0x4c,0x0f,0x40,0x0f,0x31,

+    0x0f,0x1b,0x0f,0x02,0x0f,0xea,0x0e,0xa0,

+    0x0e,0xac,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x4a,0x10,0x10,0x10,0xed,0x0f,0xcd,

+    0x0f,0xaf,0x0f,0x93,0x0f,0x7b,0x0f,0x65,

+    0x0f,0x52,0x0f,0x45,0x0f,0x3a,0x0f,0x31,

+    0x0f,0x27,0x0f,0x14,0x0f,0xf9,0x0e,0xdb,

+    0x0e,0xbd,0x0e,0xac,0x0d,0x68,0x10,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xac,0x0d,0x68,

+    0x10,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xac,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x34,0x10,0x0f,0x10,0xee,0x0f,0xcf,

+    0x0f,0xb4,0x0f,0x9d,0x0f,0x8a,0x0f,0x7a,

+    0x0f,0x6c,0x0f,0x5f,0x0f,0x53,0x0f,0x47,

+    0x0f,0x37,0x0f,0x1e,0x0f,0xfe,0x0e,0xd9,

+    0x0e,0xac,0x0d,0x68,0x10,0x1f,0x10,0xf3,

+    0x0f,0xc1,0x0f,0x87,0x0f,0x68,0x0f,0x46,

+    0x0f,0x25,0x0f,0x09,0x0f,0xf2,0x0e,0xde,

+    0x0e,0xd1,0x0e,0xc2,0x0e,0xb7,0x0e,0xae,

+    0x0e,0xa3,0x0e,0x92,0x0e,0x7b,0x0e,0x63,

+    0x0e,0x31,0x0e,0xac,0x0d,0x68,0x10,0x1f,

+    0x10,0xf3,0x0f,0xc1,0x0f,0x87,0x0f,0x68,

+    0x0f,0x46,0x0f,0x25,0x0f,0x09,0x0f,0xf2,

+    0x0e,0xde,0x0e,0xd1,0x0e,0xc2,0x0e,0xb7,

+    0x0e,0xae,0x0e,0xa3,0x0e,0x92,0x0e,0x7b,

+    0x0e,0x63,0x0e,0x31,0x0e,0xac,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x51,0x10,0x37,0x10,0x1d,0x10,0x05,

+    0x10,0xee,0x0f,0xdb,0x0f,0xc8,0x0f,0xb8,

+    0x0f,0xa8,0x0f,0x99,0x0f,0x8a,0x0f,0x78,

+    0x0f,0x61,0x0f,0x43,0x0f,0x12,0x0f,0xac,

+    0x0d,0x68,0x10,0x05,0x10,0xc9,0x0f,0x8a,

+    0x0f,0x67,0x0f,0x4c,0x0f,0x2d,0x0f,0x17,

+    0x0f,0xfe,0x0e,0xe8,0x0e,0xd5,0x0e,0xc5,

+    0x0e,0xb9,0x0e,0xaf,0x0e,0xa7,0x0e,0x9b,

+    0x0e,0x8b,0x0e,0x75,0x0e,0x5c,0x0e,0x1c,

+    0x0e,0xac,0x0d,0x68,0x10,0x05,0x10,0xc9,

+    0x0f,0x8a,0x0f,0x67,0x0f,0x4c,0x0f,0x2d,

+    0x0f,0x17,0x0f,0xfe,0x0e,0xe8,0x0e,0xd5,

+    0x0e,0xc5,0x0e,0xb9,0x0e,0xaf,0x0e,0xa7,

+    0x0e,0x9b,0x0e,0x8b,0x0e,0x75,0x0e,0x5c,

+    0x0e,0x1c,0x0e,0xac,0x0d,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x1c,0x0e,0x02,

+    0x01,0xef,0x02,0x18,0x05,0x12,0x05,0xd8,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x62,

+    0x0e,0xf2,0x01,0x50,0x03,0xcb,0x06,0x53,

+    0x02,0x9e,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x74,0x0e,0x4c,0x02,0x6c,0x03,0xf3,

+    0x06,0xc8,0x01,0x95,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x83,0x0d,0x85,0x00,0x83,

+    0x02,0x8e,0x04,0xec,0x05,0x24,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x20,0x0e,0xa4,

+    0x01,0x17,0x03,0x03,0x07,0x60,0x02,0xa1,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x48,

+    0x0e,0x24,0x02,0x3d,0x03,0x45,0x07,0xa0,

+    0x01,0x8f,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x76,0x0c,0x2b,0x00,0x0b,0x02,0xd2,

+    0x03,0x6c,0x06,0xd6,0x01,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xb6,0x0d,0x2c,0x01,0xed,

+    0x02,0xa8,0x06,0xf3,0x02,0xc5,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xf5,0x0d,0xd1,

+    0x01,0x12,0x03,0x4b,0x07,0xc5,0x01,0x97,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7d,

+    0x09,0x0d,0x00,0xf4,0x00,0x9d,0x02,0xde,

+    0x05,0xfe,0x03,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x95,0x0c,0x7e,0x00,0x1b,0x02,0x32,

+    0x05,0xc8,0x04,0x37,0x01,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x0f,0x0d,0xef,0x00,0xd3,

+    0x02,0x15,0x07,0x36,0x02,0xc5,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_c7_20130910_130553.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_c7_20130910_130553.h
new file mode 100755
index 0000000..224e8b6
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_c7_20130910_130553.h
@@ -0,0 +1,233 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 3000

+/// EDVF = 3500

+/// Taper Current = 150

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile_wms8309_c7_3000mAh [] = {

+    0x5f,0x47,0x47,0x5f,0x56,0xbe,0x00,0x00,

+    0x31,0x88,0x6e,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x6f,0x6e,0x64,

+    0x65,0x72,0x6d,0x65,0x64,0x69,0x61,0x00,

+    0x00,0x00,0x00,0x00,0x43,0x57,0x35,0x30,

+    0x30,0x2d,0x33,0x30,0x30,0x30,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x6d,0x4d,

+    0x61,0x78,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x53,0x5a,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x02,0x01,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0xb8,0x0b,0xac,0x0d,0x14,0x00,

+    0x96,0x00,0x36,0x10,0x3c,0x00,0x06,0x00,

+    0x00,0x00,0x00,0x00,0xe4,0x0c,0x48,0x0d,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x01,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0xe8,0x03,0xe8,0x03,

+    0x00,0x00,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x1e,0x61,0xae,0x5c,0xce,0x57,0x94,0x52,

+    0x14,0x4d,0x6a,0x47,0xac,0x41,0xff,0x3b,

+    0x77,0x36,0x2b,0x31,0x2c,0x2c,0x85,0x27,

+    0x3d,0x23,0x58,0x1f,0xd3,0x1b,0xab,0x18,

+    0xdb,0x15,0x5c,0x13,0x27,0x11,0xe8,0x03,

+    0xbc,0x02,0xc2,0x01,0xc8,0x00,0x00,0x00,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x01,0x00,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x59,0x10,0x44,0x10,0x32,0x10,0x20,

+    0x10,0x0b,0x10,0xef,0x0f,0xc8,0x0f,0x9c,

+    0x0f,0x77,0x0f,0x28,0x0f,0xac,0x0d,0x68,

+    0x10,0x0c,0x10,0xeb,0x0f,0xd5,0x0f,0xc4,

+    0x0f,0xb4,0x0f,0xa0,0x0f,0x83,0x0f,0x66,

+    0x0f,0x4d,0x0f,0x37,0x0f,0x28,0x0f,0x16,

+    0x0f,0x03,0x0f,0xea,0x0e,0xcc,0x0e,0xab,

+    0x0e,0x84,0x0e,0x5c,0x0e,0x2d,0x0e,0xac,

+    0x0d,0x68,0x10,0x0c,0x10,0xeb,0x0f,0xd5,

+    0x0f,0xc4,0x0f,0xb4,0x0f,0xa0,0x0f,0x83,

+    0x0f,0x66,0x0f,0x4d,0x0f,0x37,0x0f,0x28,

+    0x0f,0x16,0x0f,0x03,0x0f,0xea,0x0e,0xcc,

+    0x0e,0xab,0x0e,0x84,0x0e,0x5c,0x0e,0x2d,

+    0x0e,0xac,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x63,

+    0x10,0x4b,0x10,0x36,0x10,0x22,0x10,0x0d,

+    0x10,0xf5,0x0f,0xd4,0x0f,0xac,0x0f,0x84,

+    0x0f,0x3d,0x0f,0xac,0x0d,0x68,0x10,0x0a,

+    0x10,0xe9,0x0f,0xd3,0x0f,0xc1,0x0f,0xaf,

+    0x0f,0x99,0x0f,0x7d,0x0f,0x62,0x0f,0x4b,

+    0x0f,0x35,0x0f,0x24,0x0f,0x11,0x0f,0xfc,

+    0x0e,0xe5,0x0e,0xcb,0x0e,0xac,0x0e,0x86,

+    0x0e,0x61,0x0e,0x34,0x0e,0xac,0x0d,0x68,

+    0x10,0x0a,0x10,0xe9,0x0f,0xd3,0x0f,0xc1,

+    0x0f,0xaf,0x0f,0x99,0x0f,0x7d,0x0f,0x62,

+    0x0f,0x4b,0x0f,0x35,0x0f,0x24,0x0f,0x11,

+    0x0f,0xfc,0x0e,0xe5,0x0e,0xcb,0x0e,0xac,

+    0x0e,0x86,0x0e,0x61,0x0e,0x34,0x0e,0xac,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x52,0x10,0x3c,0x10,0x25,0x10,0x0e,

+    0x10,0xf2,0x0f,0xcd,0x0f,0xa3,0x0f,0x5f,

+    0x0f,0xac,0x0d,0x68,0x10,0x05,0x10,0xe5,

+    0x0f,0xcf,0x0f,0xbb,0x0f,0xa6,0x0f,0x8e,

+    0x0f,0x74,0x0f,0x5c,0x0f,0x45,0x0f,0x30,

+    0x0f,0x1f,0x0f,0x0b,0x0f,0xf5,0x0e,0xdd,

+    0x0e,0xc4,0x0e,0xa5,0x0e,0x82,0x0e,0x60,

+    0x0e,0x24,0x0e,0xac,0x0d,0x68,0x10,0x05,

+    0x10,0xe5,0x0f,0xcf,0x0f,0xbb,0x0f,0xa6,

+    0x0f,0x8e,0x0f,0x74,0x0f,0x5c,0x0f,0x45,

+    0x0f,0x30,0x0f,0x1f,0x0f,0x0b,0x0f,0xf5,

+    0x0e,0xdd,0x0e,0xc4,0x0e,0xa5,0x0e,0x82,

+    0x0e,0x60,0x0e,0x24,0x0e,0xac,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x67,0x10,0x4e,0x10,0x34,

+    0x10,0x16,0x10,0xed,0x0f,0xa6,0x0f,0xac,

+    0x0d,0x68,0x10,0xf6,0x0f,0xda,0x0f,0xc3,

+    0x0f,0xac,0x0f,0x95,0x0f,0x7c,0x0f,0x68,

+    0x0f,0x51,0x0f,0x3b,0x0f,0x26,0x0f,0x11,

+    0x0f,0xfb,0x0e,0xe3,0x0e,0xcf,0x0e,0xb5,

+    0x0e,0x99,0x0e,0x79,0x0e,0x4f,0x0e,0x0b,

+    0x0e,0xac,0x0d,0x68,0x10,0xf6,0x0f,0xda,

+    0x0f,0xc3,0x0f,0xac,0x0f,0x95,0x0f,0x7c,

+    0x0f,0x68,0x0f,0x51,0x0f,0x3b,0x0f,0x26,

+    0x0f,0x11,0x0f,0xfb,0x0e,0xe3,0x0e,0xcf,

+    0x0e,0xb5,0x0e,0x99,0x0e,0x79,0x0e,0x4f,

+    0x0e,0x0b,0x0e,0xac,0x0d,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x2a,0x09,0x00,

+    0x00,0xcf,0x00,0x51,0x04,0x0a,0x04,0x51,

+    0x02,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xed,

+    0x0a,0x7d,0x00,0x26,0x04,0x44,0x04,0x05,

+    0x02,0x9d,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x0e,0x0b,0x6c,0x01,0x7f,0x04,0xc0,

+    0x03,0x62,0x01,0x7e,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xe5,0x08,0x00,0x00,0xad,

+    0x00,0x1b,0x04,0x1c,0x04,0x85,0x02,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xe7,0x0a,0x69,

+    0x00,0x07,0x04,0x5b,0x04,0x19,0x02,0x99,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x0e,

+    0x0b,0x4d,0x01,0x7b,0x04,0xe0,0x03,0x64,

+    0x01,0x75,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x09,0x08,0x00,0x00,0x59,0x00,0x7e,

+    0x03,0x31,0x04,0x30,0x03,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x94,0x0a,0x3e,0x00,0xb1,

+    0x03,0x5a,0x04,0x4a,0x02,0xc4,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xeb,0x0a,0x05,

+    0x01,0x70,0x04,0xf7,0x03,0x7e,0x01,0x79,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xeb,

+    0x05,0x00,0x00,0x14,0x00,0xd9,0x01,0xfd,

+    0x03,0xbf,0x04,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x95,0x09,0x10,0x00,0x99,0x02,0x53,

+    0x04,0x97,0x02,0x52,0x01,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x53,0x0a,0x79,0x00,0x10,

+    0x04,0x11,0x04,0xb7,0x01,0xa0,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

+

diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_dw7_2900_20131129_194524.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_dw7_2900_20131129_194524.h
new file mode 100755
index 0000000..46aee48
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_dw7_2900_20131129_194524.h
@@ -0,0 +1,233 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 2900

+/// EDVF = 3500

+/// Taper Current = 150

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile_wms8309_dw7_2900mAh[] = {

+    0x5f,0x47,0x47,0x5f,0x32,0xc4,0x00,0x00,

+    0x54,0x0c,0xd7,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x6d,0x4d,0x61,0x78,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x44,0x57,0x37,0x2d,

+    0x32,0x39,0x30,0x30,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x56,0x4b,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x30,

+    0x35,0x35,0x39,0x35,0x50,0x4c,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x01,0x01,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0x54,0x0b,0xac,0x0d,0x14,0x00,

+    0x96,0x00,0x36,0x10,0x3c,0x00,0x06,0x00,

+    0x00,0x00,0x00,0x00,0xb8,0x0b,0x80,0x0c,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x00,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0xe8,0x03,0xe8,0x03,

+    0x00,0x00,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x05,0x62,0x8a,0x5d,0x9c,0x58,0x4c,0x53,

+    0xb3,0x4d,0xeb,0x47,0x15,0x42,0x4b,0x3c,

+    0xc7,0x36,0x80,0x31,0x86,0x2c,0xe5,0x27,

+    0xa2,0x23,0xc0,0x1f,0x3d,0x1c,0x17,0x19,

+    0x47,0x16,0xc6,0x13,0x8e,0x11,0xe8,0x03,

+    0x84,0x03,0xee,0x02,0x58,0x02,0xc2,0x01,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x21,0x38,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x5b,

+    0x10,0x39,0x10,0x1a,0x10,0xff,0x0f,0xe6,

+    0x0f,0xd0,0x0f,0xbc,0x0f,0xaa,0x0f,0x9b,

+    0x0f,0x8f,0x0f,0x81,0x0f,0x69,0x0f,0x4a,

+    0x0f,0x2e,0x0f,0x08,0x0f,0xac,0x0d,0x68,

+    0x10,0x1d,0x10,0xf1,0x0f,0xc7,0x0f,0xa0,

+    0x0f,0x7b,0x0f,0x57,0x0f,0x33,0x0f,0x11,

+    0x0f,0xf7,0x0e,0xe2,0x0e,0xd4,0x0e,0xc3,

+    0x0e,0xb4,0x0e,0xa4,0x0e,0x93,0x0e,0x7f,

+    0x0e,0x64,0x0e,0x4a,0x0e,0x30,0x0e,0xac,

+    0x0d,0x68,0x10,0x1d,0x10,0xf1,0x0f,0xc7,

+    0x0f,0xa0,0x0f,0x7b,0x0f,0x57,0x0f,0x33,

+    0x0f,0x11,0x0f,0xf7,0x0e,0xe2,0x0e,0xd4,

+    0x0e,0xc3,0x0e,0xb4,0x0e,0xa4,0x0e,0x93,

+    0x0e,0x7f,0x0e,0x64,0x0e,0x4a,0x0e,0x30,

+    0x0e,0xac,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x57,

+    0x10,0x39,0x10,0x1d,0x10,0x04,0x10,0xef,

+    0x0f,0xdc,0x0f,0xcc,0x0f,0xbd,0x0f,0xb0,

+    0x0f,0xa1,0x0f,0x8b,0x0f,0x6c,0x0f,0x4d,

+    0x0f,0x27,0x0f,0xac,0x0d,0x68,0x10,0x17,

+    0x10,0xeb,0x0f,0xc2,0x0f,0x99,0x0f,0x73,

+    0x0f,0x4e,0x0f,0x2b,0x0f,0x0d,0x0f,0xf5,

+    0x0e,0xe1,0x0e,0xd3,0x0e,0xc3,0x0e,0xb5,

+    0x0e,0xa7,0x0e,0x98,0x0e,0x86,0x0e,0x6b,

+    0x0e,0x54,0x0e,0x38,0x0e,0xac,0x0d,0x68,

+    0x10,0x17,0x10,0xeb,0x0f,0xc2,0x0f,0x99,

+    0x0f,0x73,0x0f,0x4e,0x0f,0x2b,0x0f,0x0d,

+    0x0f,0xf5,0x0e,0xe1,0x0e,0xd3,0x0e,0xc3,

+    0x0e,0xb5,0x0e,0xa7,0x0e,0x98,0x0e,0x86,

+    0x0e,0x6b,0x0e,0x54,0x0e,0x38,0x0e,0xac,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x51,0x10,0x38,0x10,0x22,0x10,0x0f,

+    0x10,0xfe,0x0f,0xee,0x0f,0xde,0x0f,0xcd,

+    0x0f,0xb9,0x0f,0x9c,0x0f,0x7b,0x0f,0x52,

+    0x0f,0xac,0x0d,0x68,0x10,0x0c,0x10,0xe1,

+    0x0f,0xb6,0x0f,0x8d,0x0f,0x67,0x0f,0x43,

+    0x0f,0x22,0x0f,0x07,0x0f,0xf0,0x0e,0xdd,

+    0x0e,0xcf,0x0e,0xbf,0x0e,0xb1,0x0e,0xa4,

+    0x0e,0x95,0x0e,0x82,0x0e,0x6a,0x0e,0x55,

+    0x0e,0x33,0x0e,0xac,0x0d,0x68,0x10,0x0c,

+    0x10,0xe1,0x0f,0xb6,0x0f,0x8d,0x0f,0x67,

+    0x0f,0x43,0x0f,0x22,0x0f,0x07,0x0f,0xf0,

+    0x0e,0xdd,0x0e,0xcf,0x0e,0xbf,0x0e,0xb1,

+    0x0e,0xa4,0x0e,0x95,0x0e,0x82,0x0e,0x6a,

+    0x0e,0x55,0x0e,0x33,0x0e,0xac,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x5b,0x10,0x49,0x10,0x34,0x10,0x1e,

+    0x10,0x01,0x10,0xe0,0x0f,0xad,0x0f,0xac,

+    0x0d,0x68,0x10,0x1c,0x10,0xb3,0x0f,0x85,

+    0x0f,0x5e,0x0f,0x3c,0x0f,0x1c,0x0f,0x01,

+    0x0f,0xeb,0x0e,0xd9,0x0e,0xc9,0x0e,0xbf,

+    0x0e,0xb3,0x0e,0xa8,0x0e,0x9c,0x0e,0x8d,

+    0x0e,0x79,0x0e,0x62,0x0e,0x49,0x0e,0x14,

+    0x0e,0xac,0x0d,0x68,0x10,0x1c,0x10,0xb3,

+    0x0f,0x85,0x0f,0x5e,0x0f,0x3c,0x0f,0x1c,

+    0x0f,0x01,0x0f,0xeb,0x0e,0xd9,0x0e,0xc9,

+    0x0e,0xbf,0x0e,0xb3,0x0e,0xa8,0x0e,0x9c,

+    0x0e,0x8d,0x0e,0x79,0x0e,0x62,0x0e,0x49,

+    0x0e,0x14,0x0e,0xac,0x0d,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xb5,0x08,0x00,

+    0x00,0x89,0x01,0x8c,0x02,0x9f,0x04,0xe0,

+    0x01,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x27,

+    0x0a,0xdf,0x00,0x58,0x02,0x28,0x04,0xc6,

+    0x02,0x76,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x3e,0x0a,0x58,0x01,0x7c,0x02,0xa9,

+    0x04,0xbf,0x01,0x63,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x0f,0x08,0x00,0x00,0x28,

+    0x01,0x5c,0x02,0x8a,0x04,0x3b,0x02,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xea,0x09,0xac,

+    0x00,0x34,0x02,0x1b,0x04,0xee,0x02,0x73,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x09,

+    0x0a,0x2f,0x01,0x5f,0x02,0xd2,0x04,0xa7,

+    0x01,0x5c,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xb5,0x06,0x00,0x00,0x9e,0x00,0x17,

+    0x02,0x00,0x04,0x49,0x03,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x9f,0x09,0x61,0x00,0x0c,

+    0x02,0xc3,0x03,0x6e,0x03,0x86,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xd4,0x09,0xee,

+    0x00,0x49,0x02,0xd0,0x04,0xcb,0x01,0x5d,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x5e,

+    0x04,0x00,0x00,0x22,0x00,0x48,0x01,0xf3,

+    0x02,0xb6,0x05,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x2c,0x09,0x88,0x00,0xf9,0x00,0x1b,

+    0x03,0x8f,0x04,0xf9,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x71,0x09,0x8d,0x00,0xd5,

+    0x01,0xcf,0x04,0x3e,0x02,0x6f,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

+

diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_dw7_4000_20131129_194502.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_dw7_4000_20131129_194502.h
new file mode 100755
index 0000000..0d96a79
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_dw7_4000_20131129_194502.h
@@ -0,0 +1,233 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 4000

+/// EDVF = 3500

+/// Taper Current = 150

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile_wms8309_dw7_4000mAh[] = {

+    0x5f,0x47,0x47,0x5f,0xda,0xc4,0x00,0x00,

+    0x3e,0x0c,0xd7,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x6d,0x4d,0x61,0x78,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x44,0x57,0x37,0x2d,

+    0x34,0x30,0x30,0x30,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x56,0x4b,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x34,0x32,

+    0x35,0x37,0x31,0x33,0x35,0x50,0x4c,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x01,0x01,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0xa0,0x0f,0xac,0x0d,0x14,0x00,

+    0x96,0x00,0x36,0x10,0x3c,0x00,0x06,0x00,

+    0x00,0x00,0x00,0x00,0xb8,0x0b,0x80,0x0c,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x00,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0x20,0x04,0x20,0x04,

+    0xd6,0xff,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x05,0x62,0x8a,0x5d,0x9c,0x58,0x4c,0x53,

+    0xb3,0x4d,0xeb,0x47,0x15,0x42,0x4b,0x3c,

+    0xc7,0x36,0x80,0x31,0x86,0x2c,0xe5,0x27,

+    0xa2,0x23,0xc0,0x1f,0x3d,0x1c,0x17,0x19,

+    0x47,0x16,0xc6,0x13,0x8e,0x11,0xe8,0x03,

+    0x84,0x03,0xee,0x02,0x58,0x02,0xc2,0x01,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x21,0x38,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x58,

+    0x10,0x37,0x10,0x19,0x10,0xfe,0x0f,0xe5,

+    0x0f,0xcf,0x0f,0xbb,0x0f,0xa9,0x0f,0x98,

+    0x0f,0x87,0x0f,0x75,0x0f,0x5c,0x0f,0x3e,

+    0x0f,0x24,0x0f,0xf5,0x0e,0xac,0x0d,0x68,

+    0x10,0x2c,0x10,0x06,0x10,0xdf,0x0f,0xba,

+    0x0f,0x9a,0x0f,0x7d,0x0f,0x67,0x0f,0x4d,

+    0x0f,0x35,0x0f,0x1d,0x0f,0x06,0x0f,0xee,

+    0x0e,0xd5,0x0e,0xc2,0x0e,0xa9,0x0e,0x8f,

+    0x0e,0x75,0x0e,0x5e,0x0e,0x29,0x0e,0xac,

+    0x0d,0x68,0x10,0x2c,0x10,0x06,0x10,0xdf,

+    0x0f,0xba,0x0f,0x9a,0x0f,0x7d,0x0f,0x67,

+    0x0f,0x4d,0x0f,0x35,0x0f,0x1d,0x0f,0x06,

+    0x0f,0xee,0x0e,0xd5,0x0e,0xc2,0x0e,0xa9,

+    0x0e,0x8f,0x0e,0x75,0x0e,0x5e,0x0e,0x29,

+    0x0e,0xac,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x64,

+    0x10,0x46,0x10,0x2b,0x10,0x11,0x10,0xfc,

+    0x0f,0xe8,0x0f,0xd6,0x0f,0xc5,0x0f,0xb5,

+    0x0f,0xa4,0x0f,0x8f,0x0f,0x73,0x0f,0x54,

+    0x0f,0x2c,0x0f,0xac,0x0d,0x68,0x10,0x25,

+    0x10,0xff,0x0f,0xd9,0x0f,0xb6,0x0f,0x95,

+    0x0f,0x76,0x0f,0x61,0x0f,0x49,0x0f,0x30,

+    0x0f,0x19,0x0f,0x02,0x0f,0xec,0x0e,0xd5,

+    0x0e,0xc3,0x0e,0xab,0x0e,0x93,0x0e,0x79,

+    0x0e,0x60,0x0e,0x29,0x0e,0xac,0x0d,0x68,

+    0x10,0x25,0x10,0xff,0x0f,0xd9,0x0f,0xb6,

+    0x0f,0x95,0x0f,0x76,0x0f,0x61,0x0f,0x49,

+    0x0f,0x30,0x0f,0x19,0x0f,0x02,0x0f,0xec,

+    0x0e,0xd5,0x0e,0xc3,0x0e,0xab,0x0e,0x93,

+    0x0e,0x79,0x0e,0x60,0x0e,0x29,0x0e,0xac,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x65,0x10,0x4e,0x10,0x39,

+    0x10,0x26,0x10,0x14,0x10,0x03,0x10,0xf2,

+    0x0f,0xdd,0x0f,0xc3,0x0f,0xa2,0x0f,0x69,

+    0x0f,0xac,0x0d,0x68,0x10,0x07,0x10,0xe4,

+    0x0f,0xc3,0x0f,0xa4,0x0f,0x85,0x0f,0x6a,

+    0x0f,0x57,0x0f,0x40,0x0f,0x2a,0x0f,0x14,

+    0x0f,0xff,0x0e,0xea,0x0e,0xd3,0x0e,0xc1,

+    0x0e,0xa9,0x0e,0x91,0x0e,0x77,0x0e,0x58,

+    0x0e,0x1a,0x0e,0xac,0x0d,0x68,0x10,0x07,

+    0x10,0xe4,0x0f,0xc3,0x0f,0xa4,0x0f,0x85,

+    0x0f,0x6a,0x0f,0x57,0x0f,0x40,0x0f,0x2a,

+    0x0f,0x14,0x0f,0xff,0x0e,0xea,0x0e,0xd3,

+    0x0e,0xc1,0x0e,0xa9,0x0e,0x91,0x0e,0x77,

+    0x0e,0x58,0x0e,0x1a,0x0e,0xac,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x49,0x10,0x06,0x10,0xac,

+    0x0d,0x68,0x10,0x37,0x10,0x1f,0x10,0x00,

+    0x10,0xe1,0x0f,0x9a,0x0f,0x4b,0x0f,0x10,

+    0x0f,0xf2,0x0e,0xdb,0x0e,0xc9,0x0e,0xbc,

+    0x0e,0xad,0x0e,0x9d,0x0e,0x8c,0x0e,0x7a,

+    0x0e,0x6b,0x0e,0x58,0x0e,0x44,0x0e,0x10,

+    0x0e,0xac,0x0d,0x68,0x10,0x37,0x10,0x1f,

+    0x10,0x00,0x10,0xe1,0x0f,0x9a,0x0f,0x4b,

+    0x0f,0x10,0x0f,0xf2,0x0e,0xdb,0x0e,0xc9,

+    0x0e,0xbc,0x0e,0xad,0x0e,0x9d,0x0e,0x8c,

+    0x0e,0x7a,0x0e,0x6b,0x0e,0x58,0x0e,0x44,

+    0x0e,0x10,0x0e,0xac,0x0d,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0x07,0x00,

+    0x00,0x4f,0x01,0xe0,0x02,0xcf,0x03,0xc2,

+    0x02,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x2b,

+    0x0a,0xe7,0x00,0xce,0x02,0xdf,0x03,0x95,

+    0x02,0xac,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x5f,0x0a,0x8b,0x01,0x42,0x03,0xe0,

+    0x03,0xb1,0x01,0x8a,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xd0,0x06,0x00,0x00,0xac,

+    0x00,0x8c,0x02,0x97,0x03,0xaa,0x03,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xd1,0x09,0x8b,

+    0x00,0x91,0x02,0xd3,0x03,0xe1,0x02,0xc7,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x1d,

+    0x0a,0x47,0x01,0x14,0x03,0xfa,0x03,0xc7,

+    0x01,0x89,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x4f,0x04,0x00,0x00,0x84,0x01,0xb6,

+    0x00,0x14,0x02,0xed,0x04,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x28,0x09,0x1a,0x00,0x29,

+    0x02,0x9a,0x03,0x4a,0x03,0x2f,0x01,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xc0,0x09,0xdb,

+    0x00,0xc3,0x02,0x07,0x04,0x19,0x02,0x9e,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x26,

+    0x02,0x00,0x00,0x93,0x00,0xa4,0x00,0xef,

+    0x00,0xdb,0x0a,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xcf,0x08,0xee,0x00,0x40,0x02,0xc6,

+    0x00,0xd9,0x04,0x16,0x03,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xa3,0x09,0x96,0x01,0x2a,

+    0x01,0x81,0x03,0x60,0x03,0xf9,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

+

diff --git a/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_wm8_20130820_110949.h b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_wm8_20130820_110949.h
new file mode 100755
index 0000000..b5dd5be
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ggb/ug31xx_ggb_data_uboot_wms8309_wm8_20130820_110949.h
@@ -0,0 +1,233 @@
+

+/* This file is auto-generated. Don't edit this file. */

+

+/// R-Sense = 20

+/// ILMD = 5000

+/// EDVF = 3500

+/// Taper Current = 200

+/// Taper Voltage = 4150

+/// Taper Time = 60

+

+char FactoryGGBXFile_wms8309_wm8 [] = {

+    0x5f,0x47,0x47,0x5f,0x1d,0xcc,0x00,0x00,

+    0xfd,0x0e,0x54,0x95,0x0e,0x00,0x00,0x00,

+    0xbd,0x06,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x4d,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x57,0x4d,0x53,0x38,

+    0x33,0x30,0x39,0x2d,0x31,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x57,0x4d,

+    0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x37,

+    0x31,0x30,0x38,0x31,0x30,0x33,0x50,0x00,

+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

+    0x01,0x01,0x02,0x00,0x01,0x01,0x00,0x00,

+    0x70,0x00,0x64,0x00,0x00,0x00,0x00,0x14,

+    0x00,0x00,0x88,0x13,0xac,0x0d,0x14,0x00,

+    0xc8,0x00,0x36,0x10,0x3c,0x00,0x06,0x00,

+    0x00,0x00,0x00,0x00,0xe4,0x0c,0x48,0x0d,

+    0x00,0x00,0x32,0x00,0x26,0x02,0xf4,0x01,

+    0x5c,0xff,0x77,0x01,0x63,0x05,0x00,0x00,

+    0x00,0x00,0x01,0x00,0xf0,0xdf,0xf4,0x67,

+    0xe8,0xcf,0xee,0x1b,0xe8,0x03,0xe8,0x03,

+    0x00,0x00,0xe8,0x03,0x00,0x00,0x10,0x27,

+    0x1e,0x61,0xae,0x5c,0xce,0x57,0x94,0x52,

+    0x14,0x4d,0x6a,0x47,0xac,0x41,0xff,0x3b,

+    0x77,0x36,0x2b,0x31,0x2c,0x2c,0x85,0x27,

+    0x3d,0x23,0x58,0x1f,0xd3,0x1b,0xab,0x18,

+    0xdb,0x15,0x5c,0x13,0x27,0x11,0xe8,0x03,

+    0xbc,0x02,0xc2,0x01,0xc8,0x00,0x00,0x00,

+    0x1e,0x00,0xe8,0x03,0xff,0x77,0x00,0x00,

+    0x00,0x00,0x01,0x00,0x00,0xEE,0xEE,0xEE,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x41,0x10,0x1a,

+    0x10,0xf8,0x0f,0xd9,0x0f,0xbe,0x0f,0xa5,

+    0x0f,0x8d,0x0f,0x77,0x0f,0x65,0x0f,0x56,

+    0x0f,0x48,0x0f,0x3b,0x0f,0x27,0x0f,0x0a,

+    0x0f,0xeb,0x0e,0xce,0x0e,0xac,0x0d,0x68,

+    0x10,0x2f,0x10,0x00,0x10,0xd3,0x0f,0xaa,

+    0x0f,0x84,0x0f,0x61,0x0f,0x3f,0x0f,0x1c,

+    0x0f,0xfe,0x0e,0xe8,0x0e,0xd9,0x0e,0xc9,

+    0x0e,0xbb,0x0e,0xad,0x0e,0x9f,0x0e,0x8c,

+    0x0e,0x70,0x0e,0x55,0x0e,0x3a,0x0e,0xac,

+    0x0d,0x68,0x10,0x2f,0x10,0x00,0x10,0xd3,

+    0x0f,0xaa,0x0f,0x84,0x0f,0x61,0x0f,0x3f,

+    0x0f,0x1c,0x0f,0xfe,0x0e,0xe8,0x0e,0xd9,

+    0x0e,0xc9,0x0e,0xbb,0x0e,0xad,0x0e,0x9f,

+    0x0e,0x8c,0x0e,0x70,0x0e,0x55,0x0e,0x3a,

+    0x0e,0xac,0x0d,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x62,0x10,0x38,0x10,0x13,

+    0x10,0xf3,0x0f,0xd7,0x0f,0xbf,0x0f,0xab,

+    0x0f,0x9a,0x0f,0x8b,0x0f,0x7e,0x0f,0x72,

+    0x0f,0x67,0x0f,0x57,0x0f,0x3c,0x0f,0x17,

+    0x0f,0xf7,0x0e,0xac,0x0d,0x68,0x10,0x20,

+    0x10,0xee,0x0f,0xc0,0x0f,0x95,0x0f,0x6e,

+    0x0f,0x4b,0x0f,0x29,0x0f,0x09,0x0f,0xef,

+    0x0e,0xdb,0x0e,0xce,0x0e,0xc1,0x0e,0xb7,

+    0x0e,0xaf,0x0e,0xa5,0x0e,0x96,0x0e,0x7b,

+    0x0e,0x59,0x0e,0x3b,0x0e,0xac,0x0d,0x68,

+    0x10,0x20,0x10,0xee,0x0f,0xc0,0x0f,0x95,

+    0x0f,0x6e,0x0f,0x4b,0x0f,0x29,0x0f,0x09,

+    0x0f,0xef,0x0e,0xdb,0x0e,0xce,0x0e,0xc1,

+    0x0e,0xb7,0x0e,0xaf,0x0e,0xa5,0x0e,0x96,

+    0x0e,0x7b,0x0e,0x59,0x0e,0x3b,0x0e,0xac,

+    0x0d,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x53,0x10,0x31,

+    0x10,0x14,0x10,0xfa,0x0f,0xe4,0x0f,0xd2,

+    0x0f,0xc1,0x0f,0xb2,0x0f,0xa4,0x0f,0x96,

+    0x0f,0x86,0x0f,0x6c,0x0f,0x48,0x0f,0x27,

+    0x0f,0xac,0x0d,0x68,0x10,0x21,0x10,0xf3,

+    0x0f,0xc8,0x0f,0x9c,0x0f,0x76,0x0f,0x51,

+    0x0f,0x2e,0x0f,0x10,0x0f,0xf8,0x0e,0xe4,

+    0x0e,0xd6,0x0e,0xc7,0x0e,0xba,0x0e,0xaf,

+    0x0e,0xa3,0x0e,0x91,0x0e,0x77,0x0e,0x62,

+    0x0e,0x3f,0x0e,0xac,0x0d,0x68,0x10,0x21,

+    0x10,0xf3,0x0f,0xc8,0x0f,0x9c,0x0f,0x76,

+    0x0f,0x51,0x0f,0x2e,0x0f,0x10,0x0f,0xf8,

+    0x0e,0xe4,0x0e,0xd6,0x0e,0xc7,0x0e,0xba,

+    0x0e,0xaf,0x0e,0xa3,0x0e,0x91,0x0e,0x77,

+    0x0e,0x62,0x0e,0x3f,0x0e,0xac,0x0d,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x68,0x10,0x68,0x10,0x68,0x10,0x68,

+    0x10,0x5d,0x10,0x51,0x10,0x42,0x10,0x31,

+    0x10,0x1f,0x10,0x0f,0x10,0xfe,0x0f,0xeb,

+    0x0f,0xd1,0x0f,0xae,0x0f,0x85,0x0f,0xac,

+    0x0d,0x68,0x10,0x25,0x10,0xed,0x0f,0xae,

+    0x0f,0x81,0x0f,0x5c,0x0f,0x3a,0x0f,0x1c,

+    0x0f,0x03,0x0f,0xee,0x0e,0xdc,0x0e,0xcf,

+    0x0e,0xc0,0x0e,0xb3,0x0e,0xa7,0x0e,0x99,

+    0x0e,0x86,0x0e,0x71,0x0e,0x56,0x0e,0x1c,

+    0x0e,0xac,0x0d,0x68,0x10,0x25,0x10,0xed,

+    0x0f,0xae,0x0f,0x81,0x0f,0x5c,0x0f,0x3a,

+    0x0f,0x1c,0x0f,0x03,0x0f,0xee,0x0e,0xdc,

+    0x0e,0xcf,0x0e,0xc0,0x0e,0xb3,0x0e,0xa7,

+    0x0e,0x99,0x0e,0x86,0x0e,0x71,0x0e,0x56,

+    0x0e,0x1c,0x0e,0xac,0x0d,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x68,0x10,0xb9,

+    0x0f,0x0a,0x0f,0x5b,0x0e,0xac,0x0d,0x00,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x68,

+    0x10,0xb9,0x0f,0x0a,0x0f,0x5b,0x0e,0xac,

+    0x0d,0x00,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x68,0x10,0xb9,0x0f,0x0a,0x0f,0x5b,

+    0x0e,0xac,0x0d,0x00,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x68,0x10,0xb9,0x0f,0x0a,

+    0x0f,0x5b,0x0e,0xac,0x0d,0x00,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xf9,0x11,0xc1,

+    0x00,0xb7,0x03,0xc5,0x05,0xba,0x07,0xa4,

+    0x01,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x0c,

+    0x13,0x48,0x02,0x75,0x04,0x96,0x08,0xb7,

+    0x03,0xbd,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x35,0x13,0xdf,0x02,0xb8,0x04,0xd9,

+    0x08,0xc4,0x02,0xa8,0x00,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x1a,0x12,0x20,0x00,0x23,

+    0x03,0x2c,0x05,0xaa,0x09,0x97,0x02,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x11,0x14,0xa2,

+    0x01,0x50,0x04,0xca,0x09,0x53,0x04,0xcb,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x4c,

+    0x14,0x5e,0x02,0xd0,0x04,0x51,0x0a,0xcc,

+    0x02,0xaa,0x00,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0x2e,0x0f,0x11,0x00,0x9b,0x02,0x7c,

+    0x04,0x05,0x08,0x05,0x04,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x35,0x12,0x48,0x01,0xec,

+    0x03,0xd7,0x07,0x28,0x05,0xec,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0x9b,0x12,0x23,

+    0x02,0x58,0x04,0x31,0x09,0xef,0x02,0xa3,

+    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x7a,

+    0x0a,0x00,0x00,0xb4,0x00,0x89,0x03,0x3d,

+    0x06,0x96,0x08,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xb9,0x10,0x73,0x01,0xae,0x01,0xe4,

+    0x05,0xb3,0x07,0xb6,0x01,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0x48,0x12,0xab,0x01,0x0d,

+    0x04,0xb1,0x08,0xde,0x03,0xdd,0x00,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,

+    0xff,0xff,0xff,0xff,0xff,

+};

+

diff --git a/board/wmt/wmt_battery/gauge/upi/global.h b/board/wmt/wmt_battery/gauge/upi/global.h
new file mode 100755
index 0000000..e328bec
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/global.h
@@ -0,0 +1,31 @@
+#ifndef _GLOBAL_H_

+#define _GLOBAL_H_

+

+#define UG31XX_DEBUG_ENABLE

+//#define UG31XX_RESET_DATABASE     ///< [AT-PM] : DEFAULT off ; 04/13/2013

+

+#if defined (uG31xx_OS_WINDOWS)

+

+  #pragma pack(push)

+  #pragma pack(1)

+

+  #ifdef  UG31XX_DEBUG_ENABLE

+    #define DEBUG_LOG 

+    #define uG31xx_NAC_LMD_ADJUST_DEBUG_ENABLE

+    #define TABLE_BACKUP_DEBUG_ENABLE

+    #define DEBUG_LOG_AT_PM

+    #define CALIBRATE_ADC_DEBUG_LOG

+  #endif  ///< end of UG31XX_DEBUG_ENABLE

+  

+  #define EXPORTS _declspec(dllexport)

+

+#elif defined(uG31xx_OS_ANDROID)

+

+  #define EXPORTS 

+

+#endif

+

+#define ENABLE_BQ27520_SW_CMD

+//#define ENABLE_NTC_CHECK

+

+#endif

diff --git a/board/wmt/wmt_battery/gauge/upi/stdafx.h b/board/wmt/wmt_battery/gauge/upi/stdafx.h
new file mode 100755
index 0000000..8db0f14
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/stdafx.h
@@ -0,0 +1,8 @@
+/**
+ * @filename stdafx.h
+ *
+ *  Dummy header file
+ *
+ * @author AllenTeng <allen_teng@upi-semi.com>
+ */
+
diff --git a/board/wmt/wmt_battery/gauge/upi/timer.h b/board/wmt/wmt_battery/gauge/upi/timer.h
new file mode 100755
index 0000000..6abd913
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/timer.h
@@ -0,0 +1,302 @@
+#ifndef _LINUX_TIMER_H
+#define _LINUX_TIMER_H
+
+#include <linux/list.h>
+#include <linux/ktime.h>
+#include <linux/stddef.h>
+#include <linux/debugobjects.h>
+#include <linux/stringify.h>
+
+struct tvec_base;
+
+struct timer_list {
+	/*
+	 * All fields that change during normal runtime grouped to the
+	 * same cacheline
+	 */
+	struct list_head entry;
+	unsigned long expires;
+	struct tvec_base *base;
+
+	void (*function)(unsigned long);
+	unsigned long data;
+
+	int slack;
+
+#ifdef CONFIG_TIMER_STATS
+	int start_pid;
+	void *start_site;
+	char start_comm[16];
+#endif
+#ifdef CONFIG_LOCKDEP
+	struct lockdep_map lockdep_map;
+#endif
+};
+
+extern struct tvec_base boot_tvec_bases;
+
+#ifdef CONFIG_LOCKDEP
+/*
+ * NB: because we have to copy the lockdep_map, setting the lockdep_map key
+ * (second argument) here is required, otherwise it could be initialised to
+ * the copy of the lockdep_map later! We use the pointer to and the string
+ * "<file>:<line>" as the key resp. the name of the lockdep_map.
+ */
+#define __TIMER_LOCKDEP_MAP_INITIALIZER(_kn)				\
+	.lockdep_map = STATIC_LOCKDEP_MAP_INIT(_kn, &_kn),
+#else
+#define __TIMER_LOCKDEP_MAP_INITIALIZER(_kn)
+#endif
+
+/*
+ * Note that all tvec_bases are 2 byte aligned and lower bit of
+ * base in timer_list is guaranteed to be zero. Use the LSB to
+ * indicate whether the timer is deferrable.
+ *
+ * A deferrable timer will work normally when the system is busy, but
+ * will not cause a CPU to come out of idle just to service it; instead,
+ * the timer will be serviced when the CPU eventually wakes up with a
+ * subsequent non-deferrable timer.
+ */
+#define TBASE_DEFERRABLE_FLAG		(0x1)
+
+#define TIMER_INITIALIZER(_function, _expires, _data) {		\
+		.entry = { .prev = TIMER_ENTRY_STATIC },	\
+		.function = (_function),			\
+		.expires = (_expires),				\
+		.data = (_data),				\
+		.base = &boot_tvec_bases,			\
+		.slack = -1,					\
+		__TIMER_LOCKDEP_MAP_INITIALIZER(		\
+			__FILE__ ":" __stringify(__LINE__))	\
+	}
+
+#define TBASE_MAKE_DEFERRED(ptr) ((struct tvec_base *)		\
+		  ((unsigned char *)(ptr) + TBASE_DEFERRABLE_FLAG))
+
+#define TIMER_DEFERRED_INITIALIZER(_function, _expires, _data) {\
+		.entry = { .prev = TIMER_ENTRY_STATIC },	\
+		.function = (_function),			\
+		.expires = (_expires),				\
+		.data = (_data),				\
+		.base = TBASE_MAKE_DEFERRED(&boot_tvec_bases),	\
+		__TIMER_LOCKDEP_MAP_INITIALIZER(		\
+			__FILE__ ":" __stringify(__LINE__))	\
+	}
+
+#define DEFINE_TIMER(_name, _function, _expires, _data)		\
+	struct timer_list _name =				\
+		TIMER_INITIALIZER(_function, _expires, _data)
+
+void init_timer_key(struct timer_list *timer,
+		    const char *name,
+		    struct lock_class_key *key);
+void init_timer_deferrable_key(struct timer_list *timer,
+			       const char *name,
+			       struct lock_class_key *key);
+
+#ifdef CONFIG_LOCKDEP
+#define init_timer(timer)						\
+	do {								\
+		static struct lock_class_key __key;			\
+		init_timer_key((timer), #timer, &__key);		\
+	} while (0)
+
+#define init_timer_deferrable(timer)					\
+	do {								\
+		static struct lock_class_key __key;			\
+		init_timer_deferrable_key((timer), #timer, &__key);	\
+	} while (0)
+
+#define init_timer_on_stack(timer)					\
+	do {								\
+		static struct lock_class_key __key;			\
+		init_timer_on_stack_key((timer), #timer, &__key);	\
+	} while (0)
+
+#define setup_timer(timer, fn, data)					\
+	do {								\
+		static struct lock_class_key __key;			\
+		setup_timer_key((timer), #timer, &__key, (fn), (data));\
+	} while (0)
+
+#define setup_timer_on_stack(timer, fn, data)				\
+	do {								\
+		static struct lock_class_key __key;			\
+		setup_timer_on_stack_key((timer), #timer, &__key,	\
+					 (fn), (data));			\
+	} while (0)
+#define setup_deferrable_timer_on_stack(timer, fn, data)		\
+	do {								\
+		static struct lock_class_key __key;			\
+		setup_deferrable_timer_on_stack_key((timer), #timer,	\
+						    &__key, (fn),	\
+						    (data));		\
+	} while (0)
+#else
+#define init_timer(timer)\
+	init_timer_key((timer), NULL, NULL)
+#define init_timer_deferrable(timer)\
+	init_timer_deferrable_key((timer), NULL, NULL)
+#define init_timer_on_stack(timer)\
+	init_timer_on_stack_key((timer), NULL, NULL)
+#define setup_timer(timer, fn, data)\
+	setup_timer_key((timer), NULL, NULL, (fn), (data))
+#define setup_timer_on_stack(timer, fn, data)\
+	setup_timer_on_stack_key((timer), NULL, NULL, (fn), (data))
+#define setup_deferrable_timer_on_stack(timer, fn, data)\
+	setup_deferrable_timer_on_stack_key((timer), NULL, NULL, (fn), (data))
+#endif
+
+#ifdef CONFIG_DEBUG_OBJECTS_TIMERS
+extern void init_timer_on_stack_key(struct timer_list *timer,
+				    const char *name,
+				    struct lock_class_key *key);
+extern void destroy_timer_on_stack(struct timer_list *timer);
+#else
+static inline void destroy_timer_on_stack(struct timer_list *timer) { }
+static inline void init_timer_on_stack_key(struct timer_list *timer,
+					   const char *name,
+					   struct lock_class_key *key)
+{
+	init_timer_key(timer, name, key);
+}
+#endif
+
+static inline void setup_timer_key(struct timer_list * timer,
+				const char *name,
+				struct lock_class_key *key,
+				void (*function)(unsigned long),
+				unsigned long data)
+{
+	timer->function = function;
+	timer->data = data;
+	init_timer_key(timer, name, key);
+}
+
+static inline void setup_timer_on_stack_key(struct timer_list *timer,
+					const char *name,
+					struct lock_class_key *key,
+					void (*function)(unsigned long),
+					unsigned long data)
+{
+	timer->function = function;
+	timer->data = data;
+	init_timer_on_stack_key(timer, name, key);
+}
+
+extern void setup_deferrable_timer_on_stack_key(struct timer_list *timer,
+						const char *name,
+						struct lock_class_key *key,
+						void (*function)(unsigned long),
+						unsigned long data);
+
+/**
+ * timer_pending - is a timer pending?
+ * @timer: the timer in question
+ *
+ * timer_pending will tell whether a given timer is currently pending,
+ * or not. Callers must ensure serialization wrt. other operations done
+ * to this timer, eg. interrupt contexts, or other CPUs on SMP.
+ *
+ * return value: 1 if the timer is pending, 0 if not.
+ */
+static inline int timer_pending(const struct timer_list * timer)
+{
+	return timer->entry.next != NULL;
+}
+
+extern void add_timer_on(struct timer_list *timer, int cpu);
+extern int del_timer(struct timer_list * timer);
+extern int mod_timer(struct timer_list *timer, unsigned long expires);
+extern int mod_timer_pending(struct timer_list *timer, unsigned long expires);
+extern int mod_timer_pinned(struct timer_list *timer, unsigned long expires);
+
+extern void set_timer_slack(struct timer_list *time, int slack_hz);
+
+#define TIMER_NOT_PINNED	0
+#define TIMER_PINNED		1
+/*
+ * The jiffies value which is added to now, when there is no timer
+ * in the timer wheel:
+ */
+#define NEXT_TIMER_MAX_DELTA	((1UL << 30) - 1)
+
+/*
+ * Return when the next timer-wheel timeout occurs (in absolute jiffies),
+ * locks the timer base and does the comparison against the given
+ * jiffie.
+ */
+extern unsigned long get_next_timer_interrupt(unsigned long now);
+
+/*
+ * Timer-statistics info:
+ */
+#ifdef CONFIG_TIMER_STATS
+
+extern int timer_stats_active;
+
+#define TIMER_STATS_FLAG_DEFERRABLE	0x1
+
+extern void init_timer_stats(void);
+
+extern void timer_stats_update_stats(void *timer, pid_t pid, void *startf,
+				     void *timerf, char *comm,
+				     unsigned int timer_flag);
+
+extern void __timer_stats_timer_set_start_info(struct timer_list *timer,
+					       void *addr);
+
+static inline void timer_stats_timer_set_start_info(struct timer_list *timer)
+{
+	if (likely(!timer_stats_active))
+		return;
+	__timer_stats_timer_set_start_info(timer, __builtin_return_address(0));
+}
+
+static inline void timer_stats_timer_clear_start_info(struct timer_list *timer)
+{
+	timer->start_site = NULL;
+}
+#else
+static inline void init_timer_stats(void)
+{
+}
+
+static inline void timer_stats_timer_set_start_info(struct timer_list *timer)
+{
+}
+
+static inline void timer_stats_timer_clear_start_info(struct timer_list *timer)
+{
+}
+#endif
+
+extern void add_timer(struct timer_list *timer);
+
+extern int try_to_del_timer_sync(struct timer_list *timer);
+
+#ifdef CONFIG_SMP
+  extern int del_timer_sync(struct timer_list *timer);
+#else
+# define del_timer_sync(t)		del_timer(t)
+#endif
+
+#define del_singleshot_timer_sync(t) del_timer_sync(t)
+
+extern void init_timers(void);
+extern void run_local_timers(void);
+struct hrtimer;
+extern enum hrtimer_restart it_real_fn(struct hrtimer *);
+
+unsigned long __round_jiffies(unsigned long j, int cpu);
+unsigned long __round_jiffies_relative(unsigned long j, int cpu);
+unsigned long round_jiffies(unsigned long j);
+unsigned long round_jiffies_relative(unsigned long j);
+
+unsigned long __round_jiffies_up(unsigned long j, int cpu);
+unsigned long __round_jiffies_up_relative(unsigned long j, int cpu);
+unsigned long round_jiffies_up(unsigned long j);
+unsigned long round_jiffies_up_relative(unsigned long j);
+
+#endif
diff --git a/board/wmt/wmt_battery/gauge/upi/typeDefine.h b/board/wmt/wmt_battery/gauge/upi/typeDefine.h
new file mode 100755
index 0000000..6b41222
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/typeDefine.h
@@ -0,0 +1,462 @@
+/// ===========================================

+/// typeDefine.h

+/// ===========================================

+

+#ifndef _TYPE_DEFINE_H_

+#define _TYPE_DEFINE_H_

+

+typedef unsigned char       _upi_u8_;

+typedef unsigned short      _upi_u16_;

+typedef unsigned int        _upi_u32_;

+typedef unsigned long long  _upi_u64_;

+typedef char                _upi_s8_;

+typedef short               _upi_s16_;

+typedef int                 _upi_s32_;

+typedef long long           _upi_s64_;

+typedef char                _upi_bool_;

+

+#define _UPI_TRUE_      (1)

+#define _UPI_FALSE_     (0)

+#define _UPI_NULL_      ((void *)0)

+

+

+#ifdef  uG31xx_OS_WINDOWS

+#pragma pack(push)

+#pragma pack(1)

+#endif

+

+#define CELL_PARAMETER_ALARM_EN_UV      (1<<0)

+#define CELL_PARAMETER_ALARM_EN_UET     (1<<1)

+#define CELL_PARAMETER_ALARM_EN_OET     (1<<2)

+

+typedef struct CELL_PARAMETER

+{

+  _upi_u16_ totalSize;     //Total struct size

+  _upi_u16_ fw_ver;            //CellParameter struct version

+

+  char customer[16];   //Customer name defined by uPI   //####2012/08/29#####

+  char project[16];    //Project name defined by uPI

+  _upi_u16_ ggb_version;       //0x0102 => 2.1

+

+  char customerSelfDef[16];  //Customer name record by customer 

+  char projectSelfDef[16];   //Project name record by customer

+  _upi_u16_ cell_type_code; 

+

+  _upi_u8_ ICType;  /*[2:0]=000 -> uG3100 [2:0]=001 -> uG3101

+                            [2:0]=010 -> uG3102 [2:0]=100 -> uG3103_2

+                            [2:0]=101 -> uG3103_3 */

+

+  _upi_u8_ gpio1; /*bit[4] cbc_en32

+                         bit[3] cbc_en21

+                         bit[2] pwm

+                         bit[1] alarm

+                         bit[0] gpio */	   

+  _upi_u8_ gpio2; /*bit[4] cbc_en32

+                        bit[3] cbc_en21

+                        bit[2] pwm

+                        bit[1] alarm

+                        bit[0] gpio */

+  _upi_u8_ gpio34;			//11/22/2011 -->reg92  

+  

+  _upi_u8_ cellNumber;

+  _upi_u8_ assignCellOneTo;

+  _upi_u8_ assignCellTwoTo;

+  _upi_u8_ assignCellThreeTo;

+

+  _upi_u16_ i2cAddress;    //I2C Address(Hex)

+  _upi_u16_ clock;

+

+  _upi_u8_ tenBitAddressMode;

+  _upi_u8_ highSpeedMode;

+  _upi_u8_ chopCtrl;		//11/22/2011 -->regC1

+  _upi_u8_ rSense;

+

+  _upi_s16_ adc1Offset;		//11/22/2011 -->reg58/59

+  _upi_u16_ ILMD;

+

+  _upi_u16_ edv1Voltage;

+  _upi_u16_ standbyCurrent;

+

+  _upi_u16_ TPCurrent;

+  _upi_u16_ TPVoltage;

+

+  _upi_u16_ TPTime;

+  _upi_u16_ offsetR;

+

+  _upi_u16_ deltaR;

+  _upi_u16_ TpBypassCurrent;			//20121029

+

+  _upi_s16_ uvAlarm;

+  _upi_s16_ uvRelease;

+

+  _upi_s16_ uetAlarm;

+  _upi_s16_ uetRelease;

+

+  _upi_s16_ oetAlarm;

+  _upi_s16_ oetRelease;

+

+  _upi_s16_ oscTuneJ;

+  _upi_s16_ oscTuneK;

+

+  _upi_u8_ maxDeltaQ;

+  _upi_u8_ timeInterval;

+  _upi_u8_ alarm_timer;		//11/22/2011  00:*5,01:*10,10:*15,11:*20

+  _upi_u8_ pwm_timer; /*[1:0]=00:32k [1:0]=01:16k

+                                [1:0]=10:8k  [1:0]=11: 4k */

+  

+  _upi_u8_ clkDivA;			//11/22/2011

+  _upi_u8_ clkDivB;			//11/22/2011	

+  _upi_u8_ alarmEnable; /*[7]:COC [6]:DOC [5]:IT [4]:ET

+                                    [3]:VP  [2]:V3  [1]:V2 [0]:V1 */

+  _upi_u8_ cbcEnable; /*[1]:CBC_EN32  [0]:CBC_EN21 */

+

+  _upi_u16_ vBat2_8V_IdealAdcCode;	//ideal ADC Code

+  _upi_u16_ vBat2_6V_IdealAdcCode;

+

+  _upi_u16_ vBat3_12V_IdealAdcCode;

+  _upi_u16_ vBat3_9V_IdealAdcCode;

+

+  _upi_s16_ adc1_pgain;

+  _upi_s16_ adc1_ngain;

+

+  _upi_s16_ adc1_pos_offset;

+  _upi_u16_ adc2_gain;

+

+  _upi_s16_ adc2_offset;

+  _upi_u16_ R;

+  

+  _upi_u16_ rtTable[ET_NUMS];

+  // SOV_TABLE %

+  _upi_u16_ SOV_TABLE[SOV_NUMS]; 

+

+  _upi_s16_ adc_d1;				//2012/06/06/update for IT25

+  _upi_s16_ adc_d2;				//2012/06/06/update for IT80

+  

+  _upi_s16_ adc_d3;       ///< [AT-PM] : Used for ADC calibration IT code ; 08/15/2012

+  _upi_s16_ adc_d4;

+  

+  _upi_s16_ adc_d5;

+  _upi_u16_ NacLmdAdjustCfg;

+

+  _upi_u8_ otp1Scale;

+#if defined(uG31xx_OS_ANDROID)

+}__attribute__((aligned(4))) CELL_PARAMETER;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+}CELL_PARAMETER;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct CELL_TABLE

+{		

+  _upi_s16_ INIT_OCV[TEMPERATURE_NUMS][OCV_TABLE_IDX_COUNT][OCV_NUMS];							//initial OCV Table,0.1C/0.2C OCV/charge table 

+  _upi_s16_ CELL_VOLTAGE_TABLE[TEMPERATURE_NUMS][C_RATE_NUMS][OCV_NUMS];		//cell behavior Model,the voltage data

+  _upi_s16_ CELL_NAC_TABLE[TEMPERATURE_NUMS][C_RATE_NUMS][OCV_NUMS];				//cell behavior Model,the deltaQ

+#if defined(uG31xx_OS_ANDROID)

+}  __attribute__((aligned(4))) CELL_TABLE;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+}CELL_TABLE;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct CELL_DATA

+{

+  CELL_PARAMETER cellParameter;

+  CELL_TABLE cellTable1;

+#if defined(uG31xx_OS_ANDROID)

+}  __attribute__((aligned(4))) CELL_DATA;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+}CELL_DATA;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+#if defined(uG31xx_OS_ANDROID)

+

+  //<ASUS-WAD+>

+  typedef struct _GGBX_FILE_HEADER

+  {

+    _upi_u32_ ggb_tag;        //'_GG_'

+    _upi_u32_ sum16;          //16 bits checksum, but store as 4 bytes

+    _upi_u64_ time_stamp;     //seconds pass since 1970 year, 00:00:00

+    _upi_u64_ length;         //size that not only include ggb content. (multi-file support)

+    _upi_u64_ num_ggb;        //number of ggb files. 

+  }  __attribute__((aligned(4))) GGBX_FILE_HEADER;

+  //<ASUS-WAD->

+

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct ADC_CHECK

+{

+	_upi_u16_ regCounter;	        //check adc counter

+	_upi_u16_ regVbat1Ave;      //check average voltage

+	_upi_u16_ lastCounter;

+  _upi_u16_ lastVBat1Ave;

+  _upi_u16_ failCounterCurrent;

+  _upi_u16_ failCounterVoltage;

+#if defined(uG31xx_OS_ANDROID)

+}  __attribute__((aligned(4))) ADC_CHECK;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+}ADC_CHECK;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct USER_REGISTER

+{

+	_upi_u8_ mode;

+	_upi_u8_ ctrl1;

+	_upi_u8_ charge_low;

+	_upi_u8_ charge_high;

+	_upi_u8_ counter_low;

+	_upi_u8_ counter_high;

+	_upi_u8_ current_low;

+  _upi_u8_ current_high;

+	_upi_u8_ vbat1_low;

+	_upi_u8_ vbat1_high;

+	_upi_u8_ intr_temper_low;

+	_upi_u8_ intr_temper_high;

+	_upi_u8_ ave_current_low;

+	_upi_u8_ ave_current_high;

+	_upi_u8_ extr_temper_low;

+	_upi_u8_ extr_temper_high;

+	_upi_u8_ rid_low;

+	_upi_u8_ rid_high;

+	_upi_u8_ alarm1_status;

+	_upi_u8_ alarm2_status;

+	_upi_u8_ intr_status;

+	_upi_u8_ alram_en;

+	_upi_u8_ ctrl2;

+#if defined(uG31xx_OS_ANDROID)

+}__attribute__((aligned(4))) USER_REGISTER;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+}USER_REGISTER;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+//2012/08/24/new add for system suspend 

+typedef struct _GG_SUSPEND_INFO{	

+	_upi_u16_     LMD;						//battery Qmax (maH)

+	_upi_u16_     NAC;						//battery NAC(maH)

+	_upi_u16_     RSOC;						//Battery Current RSOC(%)

+	_upi_u32_	currentTime;			//the time tick	

+

+#if defined(uG31xx_OS_ANDROID)

+ }__attribute__((aligned(4))) GG_SUSPEND_INFO,*PGG_SUSPEND_INFO;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+}GG_SUSPEND_INFO,*PGG_SUSPEND_INFO;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct _GG_BATTERY_INFO{	

+	_upi_u16_     LMD;				//battery Qmax (maH)

+	_upi_u16_     NAC;				//battery NAC(maH)

+	_upi_u16_     RSOC;				//Battery Current RSOC(%)

+#if defined(uG31xx_OS_ANDROID)

+ }__attribute__((aligned(4))) GG_BATTERY_INFO;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+}GG_BATTERY_INFO;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/// [AT-PM] : Used for TI bq27520 like command ; 10/11/2012

+typedef struct GG_TI_BQ27520 {

+  _upi_u16_ CntlControlStatus;

+  _upi_u16_ CntlPrevMacWrite;

+

+  _upi_s16_ AR;

+

+  _upi_u16_ Temp;

+  

+  _upi_u16_ Flags;

+  _upi_s16_ SINow;

+  _upi_s32_ SIBuf;

+  _upi_s16_ SISample;

+  _upi_u16_ SIWindow;

+

+  _upi_s16_ Mli;

+  _upi_u8_ MliDsgSoc;

+

+  _upi_u16_ AE;

+  

+  _upi_s16_ AP;

+  _upi_u16_ APStartChgE;

+  _upi_u16_ APStartDsgE;

+  _upi_u32_ APChgTime;

+  _upi_u32_ APDsgTime;

+

+  _upi_u16_ CC;

+  _upi_u16_ CCBuf;

+  _upi_u16_ CCLastNac;

+

+  _upi_u16_ Dli;

+

+  _upi_u16_ Dlb;

+  

+  _upi_s8_ FCSet;

+  _upi_s8_ FCClear;

+  _upi_u8_ Soc1Set;

+  _upi_u8_ Soc1Clear;

+  _upi_s8_ InitSI;

+  _upi_s16_ InitMaxLoadCurrent;

+  _upi_s16_ CCThreshold;

+  _upi_u32_ Opcfg;

+  _upi_u16_ Dcap;

+

+  _upi_u32_ LastTime;

+  _upi_u16_ DeltaSec;

+#if defined(uG31xx_OS_ANDROID)

+}__attribute__((aligned(4))) GG_TI_BQ27520, *PGG_TI_BQ27520;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+} GG_TI_BQ27520, *PGG_TI_BQ27520;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct GGAdcDeltaCodeMappingST {

+  _upi_s32_ Adc1V100;

+  _upi_s32_ Adc1V200;

+  _upi_s32_ Adc2V100;

+  _upi_s32_ Adc2V200;

+#if defined(uG31xx_OS_ANDROID)

+}__attribute__((aligned(4))) GGAdcDeltaCodeMappingType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+} GGAdcDeltaCodeMappingType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct TableBackupST {

+  _upi_u16_ lowerBound;

+  _upi_u8_ resolution;

+#if defined(uG31xx_OS_ANDROID)

+} __attribute__((aligned(4))) TableBackupType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+} TableBackupType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/* define the register of uG31xx */

+typedef struct _GG_USER_REG{

+	_upi_u8_ 	regMode;				      ///< [AT-PM] : 0x00 - MODE ; 04/08/2013

+	_upi_u8_ 	regCtrl1;				      ///< [AT-PM] : 0x01 - CTRL1 ; 04/08/2013

+	_upi_s16_	regCharge;				    ///< [AT-PM] : 0x02 - Charge ; 04/08/2013

+	_upi_u16_	regCounter;				    ///< [AT-PM] : 0x04 - Counter ; 04/08/2013

+	_upi_s16_	regCurrentAve;			  ///< [AT-PM] : 0x06 - Ave Current ; 04/08/2013

+	_upi_s16_	regVbat1Ave;			    ///< [AT-PM] : 0x08 - Ave VBat1 ; 04/08/2013

+	_upi_u16_	regITAve;				      ///< [AT-PM] : 0x0A - Ave IT ; 04/08/2013

+	_upi_s16_ regOffsetCurrentAve;  ///< [AT-PM] : 0x0C - Ave Offset Current ; 04/08/2013

+	_upi_u16_ regETAve;				      ///< [AT-PM] : 0x0E - Ave ET ; 04/08/2013

+	_upi_u16_ regRidAve;				    ///< [AT-PM] : 0x10 - Ave RID ; 04/08/2013

+	_upi_u8_  regAlarm1Status;      ///< [AT-PM] : 0x12 - Alarm1 Status ; 04/08/2013

+	_upi_u8_  regAlarm2Status;      ///< [AT-PM] : 0x13 - Alarm2 Status ; 04/08/2013

+	_upi_u8_  regIntrStatus;	      ///< [AT-PM] : 0x14 - INTR Status ; 04/08/2013

+	_upi_u8_  regAlarmEnable;       ///< [AT-PM] : 0x15 - Alarm EN ; 04/08/2013

+  _upi_u8_  regCtrl2;				      ///< [AT-PM] : 0x16 - CTRL2 ; 04/08/2013

+#if defined(uG31xx_OS_ANDROID)

+} __attribute__((aligned(4))) GG_USER_REG, *PGG_USER_REG;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+} GG_USER_REG, *PGG_USER_REG;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/* define the register of uG31xx */

+typedef struct _GG_USER2_REG{

+		_upi_s16_ regVbat2;				//0x40,vBat2

+		_upi_s16_ regVbat3;				//0x42,vBat3

+		_upi_s16_ regVbat1;				//0x44,vBat1 Average

+		_upi_s16_ regVbat2Ave;			//0x46,vBat2 Average

+		_upi_s16_ regVbat3Ave;			//0x48,vBat3 Average

+		_upi_u16_ regV1;					//0x4a,cell 1 Voltage

+		_upi_u16_ regV2;					//0x4c,0xcell 2 Voltage

+		_upi_u16_ regV3;					//0x4e,cell 3 Voltage

+		_upi_s16_ regIT;					//0x50

+		_upi_s16_ regET;					//0x52

+		_upi_u16_ regRID;					//0x54

+		_upi_s16_	regCurrent;				//0x56

+		_upi_s16_ regAdc1Offset;			//0x58ADC1 offset

+#if defined(uG31xx_OS_ANDROID)

+}__attribute__((aligned(4))) GG_USER2_REG, *PGG_USER2_REG;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+} GG_USER2_REG, *PGG_USER2_REG;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+#define ALARM_STATUS_UV     (1<<0)

+#define ALARM_STATUS_UET    (1<<1)

+#define ALARM_STATUS_OET    (1<<2)

+

+/* define device information */

+typedef struct _GG_DEVICE_INFO{

+

+	_upi_s16_	   oldRegCurrent;				//for skip the ADC code Error

+	_upi_s16_	   oldRegVbat1;					//for skip the ADC code Error

+

+	_upi_s16_	   vBat1_AdcCode;				//debug use

+	_upi_s16_	   vBat1_AveAdcCode;

+

+	_upi_s16_	   fwCalAveCurrent_mA;			//f/w calculate average current	

+	_upi_u32_	   lastTime;					//	

+	_upi_s16_	   chargeRegister;				//coulomb counter register  

+	_upi_u16_	   AdcCounter;					//ADC convert counter

+

+	_upi_s16_	   preChargeRegister;			//coulomb counter register  

+	_upi_s16_    aveCurrentRegister;			//2012/0711/jacky

+	_upi_u16_	   preAdcCounter;				

+	_upi_s32_	   fwChargeData_mAH;			//fw calculate maH (Q= I * T)

+

+	_upi_s32_    chargeData_mAh;				//maH calculate from charge register

+	_upi_u16_    voltage_mV;		            //total voltage

+	_upi_s16_    current_mA;			        // now current

+	_upi_s16_	   AveCurrent_mA;				// average current

+	_upi_s16_    IT;							// internal temperature

+	_upi_s16_    ET;							// external temperature

+

+	_upi_u16_	   v1_mV;						//v1   from hw register

+	_upi_u16_	   v2_mV;						//v2

+	_upi_u16_	   v3_mV;						//v3

+

+	_upi_u16_	   vBat1Average_mV;				//vbat1 	 

+	_upi_u16_	   vBat2Average_mV;		

+	_upi_u16_	   vBat3Average_mV;		

+

+	

+	_upi_u16_    vCell1_mV;					//v Cell1

+	_upi_u16_	   vCell2_mV;					//v Cell2

+	_upi_u16_	   vCell3_mV;					//v Cell3

+

+	_upi_s16_ CaliAdc1Code;				//2012/08/29/Jacky

+	_upi_s16_ CaliAdc2Code;

+

+	_upi_s16_ CoulombCounter;

+

+  _upi_s32_ CaliChargeReg;

+  _upi_u16_ Adc1ConvTime;

+

+  _upi_u8_ alarmStatus;

+#if defined(uG31xx_OS_ANDROID)

+} __attribute__((aligned(4))) GG_DEVICE_INFO, *PGG_DEVICE_INFO;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+} GG_DEVICE_INFO, *PGG_DEVICE_INFO;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+

+/* define battery capacity */

+typedef struct _GG_CAPACITY {

+	_upi_u16_     LMD;						    //battery Qmax (maH)

+	_upi_u16_     NAC;						    //battery NAC(maH)

+	_upi_u16_     RSOC;					    //Battery Current RSOC(%)

+	

+  _upi_u8_      Ready;

+#if defined(uG31xx_OS_ANDROID)

+} __attribute__((aligned(4))) GG_CAPACITY, *PGG_CAPACITY;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+}GG_CAPACITY, *PGG_CAPACITY;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct GG_MEAS_PARA_ST

+{

+  _upi_s16_ Adc1Gain;

+  _upi_s16_ Adc1Offset;

+

+  _upi_s16_ Adc2Gain;

+  _upi_s16_ Adc2Offset;

+

+  _upi_s16_ ITOffset;

+  _upi_s16_ ETOffset;

+

+  _upi_u8_ ProductType;

+#if defined(uG31xx_OS_ANDROID)

+}__attribute__((aligned(4))) GG_MEAS_PARA_TYPE;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+} GG_MEAS_PARA_TYPE;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+#endif

+

+/// ===========================================

+/// End of typeDefine.h

+/// ===========================================

diff --git a/board/wmt/wmt_battery/gauge/upi/types.h b/board/wmt/wmt_battery/gauge/upi/types.h
new file mode 100755
index 0000000..28beab9
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/types.h
@@ -0,0 +1,16 @@
+#ifndef __ASM_ARM_TYPES_H
+#define __ASM_ARM_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#endif /* __KERNEL__ */
+
+#endif
+
diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx.h b/board/wmt/wmt_battery/gauge/upi/uG31xx.h
new file mode 100755
index 0000000..67b3dfe
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx.h
@@ -0,0 +1,129 @@
+/// ===========================================

+/// uG31xx.h

+/// ===========================================

+

+#ifndef _UG31XX_H_

+#define _UG31XX_H_

+

+#define  SECURITY			1		//Security Mode enable

+#define  NORMAL				0		//Security Mode OFF

+

+#define  HIGH_SPEED			1		//HS Mode

+#define  FULL_SPEED			0		//FIL speed

+

+#define  TEN_BIT_ADDR		1		//10-bit address Mode

+#define	 SEVEN_BIT_ADDR		0		//7-bit address Mode

+

+#define  I2C_SUCESS			1		//

+#define  I2C_FAIL			0

+

+/// ===========================================================================

+/// Constant for Calibration

+/// ===========================================================================

+

+#define IT_TARGET_CODE25	  (12155)

+#define IT_TARGET_CODE80	  (14306)

+

+#define IT_CODE_25		(23171)

+#define IT_CODE_80		(27341)

+

+//constant

+//define IC type

+#define uG3100		0

+#define uG3101		1

+#define uG3102		2

+#define uG3103_2	4

+#define uG3103_3	5

+

+//constant

+//GPIO1/2 define

+#define FUN_GPIO				0x01

+#define FUN_ALARM				0x02

+#define FUN_PWM					0x04

+#define FUN_CBC_EN21			0x08

+#define FUN_CBC_EN32			0x10

+

+#define BIT_MACRO(x)		((_upi_u8_)1 << (x))

+

+#define MAX_CRATE_AVAILABLE     (20)

+					

+#define I2C_ADDRESS    0x70

+#define I2C_CLOCK      0x100

+

+//const for CELL_TABLE table

+#define TEMPERATURE_NUMS  (4)

+#define C_RATE_NUMS				(3)     ///< [AT-PM] : 0.5, 0.2, 0.1, 0.02 ; 12/17/2013

+#define OCV_NUMS				  (21)			//include the 0% & 100%

+#define SOV_NUMS				  (5)     ///< [AT-PM] : 100%, 70%, 45%, 20%, 0% ; 12/17/2012

+#define ET_NUMS           (19)      ///< [AT-PM] : -10, -5, 0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80 ; 01/25/2013

+

+#define NAC_LMD_ADJUST_CFG_NO_LMD_UPDATE_BETWEEN_10_90_EN     (1<<0)

+#define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_MASK   (15<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_00   (0<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_01   (1<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_02   (2<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_03   (3<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_04   (4<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_05   (5<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_06   (6<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_07   (7<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_08   (8<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_09   (9<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_10   (10<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_11   (11<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_12   (12<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_13   (13<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_14   (14<<1)

+  #define NAC_LMD_ADJUST_CFG_LOCK_AND_SPEED_UP_START_SOV_15   (15<<1)

+#define NAC_LMD_ADJUST_CFG_DISPLAY_CC_AS_FCC                  (1<<5)

+

+#if defined(uG31xx_OS_ANDROID)

+

+  #define GGBX_FILE_TAG 0x5F47475F // _GG_

+  #define GGBX_FACTORY_FILE_TAG 0x5F67675F // _gg_

+

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+enum C_RATE_TABLE_VALUES {

+  C_RATE_TABLE_VALUE_0 = 50,

+  C_RATE_TABLE_VALUE_1 = 20,

+  C_RATE_TABLE_VALUE_2 = 10,

+  C_RATE_TABLE_VALUE_3 = 2

+};

+

+enum OCV_TABLE_IDX {

+  OCV_TABLE_IDX_CHARGE = 0,

+  OCV_TABLE_IDX_STAND_ALONE,

+  OCV_TABLE_IDX_100MA,

+  OCV_TABLE_IDX_COUNT,

+};

+

+#if defined (uG31xx_OS_WINDOWS)

+

+  #define SleepMiniSecond(x)    Sleep(x)

+

+  #ifdef DEBUG_LOG

+

+    #define  _L(X) __L(X)

+    #define __L(X) L##X

+

+  #endif

+

+#elif defined (uG31xx_OS_ANDROID)

+

+  //#define SleepMiniSecond(x) mdelay(x)

+  #define SleepMiniSecond(x) wmt_idle_us(x*1000)

+

+

+#endif

+

+#define CONST_PERCENTAGE                  (100)

+#define TIME_CONVERT_TIME_TO_MSEC         (10)

+#define CONST_CONVERSION_COUNT_THRESHOLD  (300)

+

+#endif

+

+/// ===========================================

+/// End of uG31xx.h

+/// ===========================================

+

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_API.h b/board/wmt/wmt_battery/gauge/upi/uG31xx_API.h
new file mode 100755
index 0000000..6adcb71
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_API.h
@@ -0,0 +1,507 @@
+/// ===========================================

+/// uG31xx_API.h

+/// ===========================================

+

+#ifndef _UG31XXAPI_H_

+#define _UG31XXAPI_H_

+

+#include "uG31xx_Platform.h"

+

+#if defined (uG31xx_OS_WINDOWS)

+

+  #include <windows.h>

+

+#endif

+

+#include "global.h"

+#include "uG31xx.h"

+

+#if defined (uG31xx_OS_WINDOWS)

+

+  #include "../../uG31xx_I2C_DLL/uG3100Dll/uG31xx_I2C.h"

+  #include <assert.h>

+  

+  #ifdef DEBUG_LOG

+  

+    #include "wDebug.h"

+    

+  #endif

+  

+#elif defined (uG31xx_OS_ANDROID)

+

+  #ifdef  uG31xx_BOOT_LOADER

+

+//    #include <sys/types.h>

+//    #include <platform/timer.h>

+

+//    #define	UPI_UBOOT_DEBUG_MSG

+

+    #include "ug31xx_boot_i2c.h"

+

+  #else   ///< else of uG31xx_BOOT_LOADER

+

+    #include <linux/module.h>

+    #include <linux/delay.h>

+    #include <linux/fs.h>

+    #include <asm/uaccess.h>

+

+    #include "ug31xx_i2c.h"

+

+  #endif  ///< end of uG31xx_BOOT_LOADER

+

+#endif

+

+#include "typeDefine.h"

+#include "uG31xx_Reg_Def.h"

+#include "uG31xx_API_Otp.h"

+#include "uG31xx_API_System.h"

+#include "uG31xx_API_Measurement.h"

+#include "uG31xx_API_Capacity.h"

+#include "uG31xx_API_Backup.h"

+

+#define UG31XX_API_MAIN_VERSION     (13)

+#define UG31XX_API_OTP_VERSION      ((UG31XX_OTP_VERSION_MAIN << 16) | UG31XX_OTP_VERSION_SUB)

+#define UG31XX_API_SUB_VERSION      ((UG31XX_CAP_VERSION << 16) | (UG31XX_MEAS_VERSION << 8) | UG31XX_SYSTEM_VERSION)

+

+#define UG31XX_I2C_HIGH_SPEED_MODE    (_UPI_FALSE_)

+#define UG31XX_I2C_TEM_BITS_MODE      (_UPI_FALSE_)

+

+#ifdef  UG31XX_DEBUG_ENABLE

+

+  #if defined(uG31xx_OS_ANDROID)

+

+    #ifdef  uG31xx_BOOT_LOADER

+          

+      #define __func__        

+

+      #define UG31_LOGE(...)

+      #define UG31_LOGI(...)

+      #define UG31_LOGD(...)

+      #define UG31_LOGV(...)

+

+      extern int ug31_dprintk(int level, const char *fmt, ...);

+      

+    #else   ///< else of uG31xx_BOOT_LOADER

+    

+      #define LOG_NORMAL      (0)

+      #define LOG_ERROR       (1)

+      #define LOG_DATA        (2)

+      #define LOG_VERBOSE     (3)

+      

+      #define UG31_TAG "UG31"

+      #define UG31_LOGE(...)  ug31_printk(LOG_ERROR, "<"UG31_TAG"/E>"  __VA_ARGS__);

+      #define UG31_LOGI(...)  ug31_printk(LOG_NORMAL, "<"UG31_TAG"/I>"  __VA_ARGS__);

+      #define UG31_LOGD(...)  ug31_printk(LOG_DATA, "<"UG31_TAG"/D>"  __VA_ARGS__);

+      #define UG31_LOGV(...)  ug31_printk(LOG_VERBOSE, "<"UG31_TAG"/V>"  __VA_ARGS__);

+      

+      extern int ug31_printk(int level, const char *fmt, ...); 

+

+    #endif  ///< end of uG31xx_BOOT_LOADER

+    

+  #endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+  #if defined (uG31xx_OS_WINDOWS)

+

+    #define DEBUG_FILE      (_T("uG3105"))

+    #define __func__        (_T(__FUNCTION__))

+

+    #define UG31_LOGE(...)  wDebug::LOGE(DEBUG_FILE, 0, _T(__VA_ARGS__));

+    #define UG31_LOGI(...)  wDebug::LOGE(DEBUG_FILE, 0, _T(__VA_ARGS__));

+    #define UG31_LOGD(...)  wDebug::LOGE(DEBUG_FILE, 0, _T(__VA_ARGS__));

+    #define UG31_LOGV(...)  wDebug::LOGE(DEBUG_FILE, 0, _T(__VA_ARGS__));

+

+  #endif  ///< end of defined (uG31xx_OS_WINDOWS)

+  

+#else   ///< else of UG31XX_DEBUG_ENABLE

+

+  #define UG31_LOGE(...)

+  #define UG31_LOGI(...)

+  #define UG31_LOGD(...)

+  #define UG31_LOGV(...)

+

+#endif  ///< end of UG31XX_DEBUG_ENABLE

+

+#if defined(uG31xx_OS_ANDROID)

+

+  extern _upi_u32_ GetTickCount(void);

+  extern _upi_u32_ GetSysTickCount(void);

+  

+#endif

+

+/* data struct */

+typedef enum _GGSTATUS{

+  UG_SUCCESS                    = 0x00,

+  UG_FAIL		                    = 0x01,

+  UG_NOT_DEF                    = 0x02,

+  UG_INIT_OCV_FAIL	            = 0x03,

+  UG_READ_GGB_FAIL              = 0x04,

+  UG_ACTIVE_FAIL                = 0x05,

+  UG_INIT_SUCCESS               = 0x06,

+  UG_OTP_ISEMPTY                = 0x07,

+  UG_OTP_PRODUCT_DISMATCH       = 0x08,

+

+  UG_I2C_INIT_FAIL              = 0x10,

+  UG_I2C_READ_SUCCESS           = 0x11,

+  UG_I2C_READ_FAIL              = 0x12,

+  UG_I2C_WRITE_SUCCESS          = 0x13,

+  UG_I2C_WRITE_FAIL             = 0x14,

+

+  UG_READ_REG_SUCCESS           = 0x20,

+  UG_READ_REG_FAIL              = 0x21,

+

+  UG_READ_DEVICE_INFO_SUCCESS   = 0x22,

+  UG_READ_DEVICE_INFO_FAIL      = 0x23,

+  UG_READ_DEVICE_ALARM_SUCCESS  = 0x24,

+  UG_READ_DEVICE_ALARM_FAIL     = 0x25,

+  UG_READ_DEVICE_RID_SUCCESS	  = 0x26,

+  UG_READ_DEVICE_RID_FAIL		    = 0x27,

+  UG_READ_ADC_FAIL						  = 0x28,			//new add for filter ADC Error Code

+

+  UG_TI_CMD_OVERFLOW            = 0x30,

+

+  UG_MEAS_FAIL                  = 0x40,

+  UG_MEAS_FAIL_BATTERY_REMOVED  = 0x41,

+  UG_MEAS_FAIL_ADC_ABNORMAL     = 0x42,

+  UG_MEAS_FAIL_NTC_SHORT        = 0x43,

+

+  UG_CAP_DATA_READY             = 0x50,

+  UG_CAP_DATA_NOT_READY         = 0x51,

+}GGSTATUS;

+

+/*

+    GGSTATUS upiGG_Initial

+    Description: Initial and active uG31xx function

+    Input: .GGB(gas gauge battery) setting filename, need include complete path

+	Output: UG_INIT_SUCCESS -> initial uG31xx success

+	        UG_READ_GGB_FAIL -> read GGB file fail

+			UG_INIT_I2C_FAIL -> initial I2C to open HID fail

+			UG_ACTIVE_FAIL -> active uG31xx fail

+*/

+#if defined (uG31xx_OS_WINDOWS)

+

+  EXPORTS GGSTATUS upiGG_Initial(char **pObj, const wchar_t* GGBFilename, const wchar_t* OtpFileName, const wchar_t* BackupFileName);

+

+#endif

+

+#if defined(uG31xx_OS_ANDROID)

+

+  GGSTATUS upiGG_Initial(char **pObj, GGBX_FILE_HEADER *pGGBXBuf);

+

+#endif

+

+/*

+    GGSTATUS upiGG_CountInitQmax

+    Description:

+    Input: None

+	Output: None

+*/

+//EXPORTS void upiGG_CountInitQmax(void);

+

+/*

+    GGSTATUS upiGG_ReadDevieRegister

+    Description: Read GG_USER_REG from device to global variable and output

+    Input: Pointer of sturct GG_USER_REG 

+	Output: UG_READ_REG_SUCCESS -> read success

+	        UG_READ_REG_FAIL -> read fail

+*/

+EXPORTS GGSTATUS upiGG_ReadAllRegister(char *pObj,GG_USER_REG* pExtUserReg, GG_USER2_REG* pExtUserReg2);

+

+/*

+    GGSTATUS upiGG_ReadDeviceInfo

+    Description: Read GG_USER_REG from device and calculate GG_DEVICE_INFO, then write to global variable and output

+    Input: Pointer of struct GG_DEVICE_INFO

+	Output: UG_READ_DEVICE_INFO_SUCCESS -> calculate derive information sucess

+	        UG_READ_DEVICE_INFO_FAIL -> calculate derive information fail

+*/

+EXPORTS GGSTATUS upiGG_ReadDeviceInfo(char *pObj,GG_DEVICE_INFO* pExtDeviceInfo);

+

+/* GGSTATUS upiGG_ReadCapacity

+    Description:

+    Input:

+	Output: None

+*/

+EXPORTS void upiGG_ReadCapacity(char *pObj,GG_CAPACITY *pExtCapacity);

+

+/**

+ * @brief upiGG_GetAlarmStatus

+ *

+ *  Get alarm status

+ *

+ * @para  pAlarmStatus  address of alarm status

+ * @return  UG_READ_DEVICE_ALARM_SUCCESS if success

+ */

+EXPORTS GGSTATUS upiGG_GetAlarmStatus(char *pObj, _upi_u8_ *pAlarmStatus);

+

+/*

+new add function for System suspend & wakeup

+

+*/

+EXPORTS GGSTATUS upiGG_PreSuspend(char *pObj);

+EXPORTS GGSTATUS upiGG_Wakeup(char *pObj);

+

+/**

+ * @brief upiGG_DumpRegister

+ *

+ *  Dump whole register value

+ *

+ * @para  pBuf  address of register value buffer

+ * @return  data size

+ */

+EXPORTS _upi_u16_ upiGG_DumpRegister(char *pObj, _upi_u8_ *pBuf);

+

+/**

+ * @brief upiGG_DumpCellTable

+ *

+ *  Dump cell NAC table

+ *

+ * @para  pTable address of cell table

+ * @return  _UPI_NULL_

+ */

+EXPORTS void upiGG_DumpCellTable(char *pObj, CELL_TABLE *pTable);

+EXPORTS GGSTATUS upiGG_UnInitial(char **pObj);

+EXPORTS void upiGG_DumpParameter(char *pObj, CELL_PARAMETER *pTable);

+

+#define upiGG_PrePowerOff (upiGG_PreSuspend)

+

+#ifdef ENABLE_BQ27520_SW_CMD

+

+/**

+ * @brief upiGG_AccessMeasurementParameter

+ *

+ *  Access measurement parameter

+ *

+ * @para  read  set _UPI_TRUE_ to read data from API

+ * @para  pMeasPara pointer of GG_MEAS_PARA_TYPE

+ * @return  GGSTATUS

+ */

+EXPORTS GGSTATUS upiGG_AccessMeasurementParameter(char *pObj, _upi_bool_ read, GG_MEAS_PARA_TYPE *pMeasPara);

+

+#define UG_STD_CMD_CNTL     (0x00)

+  #define UG_STD_CMD_CNTL_CONTROL_STATUS    (0x0000)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_DLOGEN     (1<<15)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_FAS        (1<<14)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_SS         (1<<13)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_CSV        (1<<12)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_CCA        (1<<11)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_BCA        (1<<10)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_OCVCMDCOMP (1<<9)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_OCVFAIL    (1<<8)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_INITCOMP   (1<<7)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_HIBERNATE  (1<<6)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_SNOOZE     (1<<5)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_SLEEP      (1<<4)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_LDMD       (1<<3)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_RUP_DIS    (1<<2)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_VOK        (1<<1)

+    #define UG_STD_CMD_CNTL_CONTROL_STATUS_QEN        (1<<0)

+  #define UG_STD_CMD_CNTL_DEVICE_TYPE       (0x0001)

+  #define UG_STD_CMD_CNTL_FW_VERSION        (0x0002)

+  #define UG_STD_CMD_CNTL_PREV_MACWRITE     (0x0007)

+  #define UG_STD_CMD_CNTL_CHEM_ID           (0x0008)

+  #define UG_STD_CMD_CNTL_OCV_CMD           (0x000C)      ///< [AT-PM] : Not implemented ; 10/11/2012

+  #define UG_STD_CMD_CNTL_BAT_INSERT        (0x000D)

+  #define UG_STD_CMD_CNTL_BAT_REMOVE        (0x000E)

+  #define UG_STD_CMD_CNTL_SET_HIBERNATE     (0x0011)

+  #define UG_STD_CMD_CNTL_CLEAR_HIBERNATE   (0x0012)

+  #define UG_STD_CMD_CNTL_SET_SLEEP_PLUS    (0x0013)

+  #define UG_STD_CMD_CNTL_CLEAR_SLEEP_PLUS  (0x0014)

+  #define UG_STD_CMD_CNTL_FACTORY_RESTORE   (0x0015)

+  #define UG_STD_CMD_CNTL_ENABLE_DLOG       (0x0018)

+  #define UG_STD_CMD_CNTL_DISABLE_DLOG      (0x0019)

+  #define UG_STD_CMD_CNTL_DF_VERSION        (0x001F)

+  #define UG_STD_CMD_CNTL_SEALED            (0x0020)

+  #define UG_STD_CMD_CNTL_RESET             (0x0041)

+#define UG_STD_CMD_AR       (0x02)

+#define UG_STD_CMD_ARTTE    (0x04)

+#define UG_STD_CMD_TEMP     (0x06)

+#define UG_STD_CMD_VOLT     (0x08)

+#define UG_STD_CMD_FLAGS    (0x0A)

+  #define UG_STD_CMD_FLAGS_OTC            (1<<15)

+  #define UG_STD_CMD_FLAGS_OTD            (1<<14)

+  #define UG_STD_CMD_FLAGS_RSVD13         (1<<13)

+  #define UG_STD_CMD_FLAGS_RSVD12         (1<<12)

+  #define UG_STD_CMD_FLAGS_CHG_INH        (1<<11)

+  #define UG_STD_CMD_FLAGS_XCHG           (1<<10)

+  #define UG_STD_CMD_FLAGS_FC             (1<<9)

+  #define UG_STD_CMD_FLAGS_CHG            (1<<8)

+  #define UG_STD_CMD_FLAGS_RSVD7          (1<<7)

+  #define UG_STD_CMD_FLAGS_RSVD6          (1<<6)

+  #define UG_STD_CMD_FLAGS_OCV_GD         (1<<5)

+  #define UG_STD_CMD_FLAGS_WAIT_ID        (1<<4)

+  #define UG_STD_CMD_FLAGS_BAT_DET        (1<<3)

+  #define UG_STD_CMD_FLAGS_SOC1           (1<<2)

+  #define UG_STD_CMD_FLAGS_SYSDOWN        (1<<1)

+  #define UG_STD_CMD_FLAGS_DSG            (1<<0)

+#define UG_STD_CMD_NAC      (0x0C)

+#define UG_STD_CMD_FAC      (0x0E)

+#define UG_STD_CMD_RM       (0x10)

+#define UG_STD_CMD_FCC      (0x12)

+#define UG_STD_CMD_AI       (0x14)

+#define UG_STD_CMD_TTE      (0x16)

+#define UG_STD_CMD_TTF      (0x18)

+#define UG_STD_CMD_SI       (0x1A)

+#define UG_STD_CMD_STTE     (0x1C)

+#define UG_STD_CMD_MLI      (0x1E)

+#define UG_STD_CMD_MLTTE    (0x20)

+#define UG_STD_CMD_AE       (0x22)

+#define UG_STD_CMD_AP       (0x24)

+#define UG_STD_CMD_TTECP    (0x26)

+#define UG_STD_CMD_SOH      (0x28)

+  #define UG_STD_CMD_SOH_VALUE_MASK   (0x00FF)

+  #define UG_STD_CMD_SOH_STATUS_MASK  (0xFF00)

+    #define UG_STD_CMD_SOH_STATUS_NOT_VALID     (0x0000)

+    #define UG_STD_CMD_SOH_STATUS_INSTANT_READY (0x0100)

+    #define UG_STD_CMD_SOH_STATUS_INITIAL_READY (0x0200)

+    #define UG_STD_CMD_SOH_STATUS_READY         (0x0300)

+#define UG_STD_CMD_CC       (0x2A)

+#define UG_STD_CMD_SOC      (0x2C)

+#define UG_STD_CMD_NIC      (0x2E)      ///< [AT-PM] : Not implemented ; 10/11/2012

+#define UG_STD_CMD_ICR      (0x30)

+#define UG_STD_CMD_DLI      (0x32)

+#define UG_STD_CMD_DLB      (0x34)

+#define UG_STD_CMD_ITEMP    (0x36)

+#define UG_STD_CMD_OPCFG    (0x3A)

+  #define UG_STD_CMD_OPCFG_RESCAP     (1<<31)

+  #define UG_STD_CMD_OPCFG_BATG_OVR   (1<<30)

+  #define UG_STD_CMD_OPCFG_INT_BERM   (1<<29)

+  #define UG_STD_CMD_OPCFG_PFC_CFG1   (1<<28)

+  #define UG_STD_CMD_OPCFG_PFC_CFG0   (1<<27)

+  #define UG_STD_CMD_OPCFG_IWAKE      (1<<26)

+  #define UG_STD_CMD_OPCFG_RSNS1      (1<<25)

+  #define UG_STD_CMD_OPCFG_RSNS0      (1<<24)

+  #define UG_STD_CMD_OPCFG_INT_FOCV   (1<<23)

+  #define UG_STD_CMD_OPCFG_IDSELEN    (1<<22)

+  #define UG_STD_CMD_OPCFG_SLEEP      (1<<21)

+  #define UG_STD_CMD_OPCFG_RMFCC      (1<<20)

+  #define UG_STD_CMD_OPCFG_SOCI_POL   (1<<19)

+  #define UG_STD_CMD_OPCFG_BATG_POL   (1<<18)

+  #define UG_STD_CMD_OPCFG_BATL_POL   (1<<17)

+  #define UG_STD_CMD_OPCFG_TEMPS      (1<<16)

+  #define UG_STD_CMD_OPCFG_WRTEMP     (1<<15)

+  #define UG_STD_CMD_OPCFG_BIE        (1<<14)

+  #define UG_STD_CMD_OPCFG_BL_INT     (1<<13)

+  #define UG_STD_CMD_OPCFG_GNDSEL     (1<<12)

+  #define UG_STD_CMD_OPCFG_FCE        (1<<11)

+  #define UG_STD_CMD_OPCFG_DFWRINDBL  (1<<10)

+  #define UG_STD_CMD_OPCFG_RFACTSTEP  (1<<9)

+  #define UG_STD_CMD_OPCFG_INDFACRES  (1<<8)

+  #define UG_STD_CMD_OPCFG_BATGSPUEN  (1<<7)

+  #define UG_STD_CMD_OPCFG_BATGWPUEN  (1<<6)

+  #define UG_STD_CMD_OPCFG_BATLSPUEN  (1<<5)

+  #define UG_STD_CMD_OPCFG_BATLWSPUEN (1<<4)

+  #define UG_STD_CMD_OPCFG_RSVD3      (1<<3)

+  #define UG_STD_CMD_OPCFG_SLPWKCHG   (1<<2)

+  #define UG_STD_CMD_OPCFG_DELTAVOPT1 (1<<1)

+  #define UG_STD_CMD_OPCFG_DELTAVOPT0 (1<<0)

+#define UG_EXT_CMD_DCAP     (0x3C)

+

+/**

+ * @brief upiGG_FetchDataCommand

+ *

+ *  Fetch bq27520 like command

+ *

+ * @para  read  set _UPI_TRUE_ to read data from API

+ * @para  pMeasPara pointer of GG_MEAS_PARA_TYPE

+ * @return  GGSTATUS

+ */

+EXPORTS GGSTATUS upiGG_FetchDataCommand(char *pObj, _upi_u8_ CommandCode, _upi_u16_ *pData);

+

+typedef struct GG_FETCH_DATA_PARA_ST {

+  _upi_s8_ FCSet;

+  _upi_s8_ FCClear;

+  _upi_u8_ Soc1Set;

+  _upi_u8_ Soc1Clear;

+  _upi_s8_ InitSI;

+  _upi_s16_ InitMaxLoadCurrent;

+  _upi_u16_ CCThreshold;

+  _upi_u32_ Opcfg;

+  _upi_u16_ Dcap;

+#if defined(uG31xx_OS_ANDROID)

+}__attribute__((aligned(4))) GG_FETCH_DATA_PARA_TYPE;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+} GG_FETCH_DATA_PARA_TYPE;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/**

+ * @brief upiGG_FetchDataParameter

+ *

+ *  Set the parameter for bq27520 like command

+ *

+ * @para  data  parameters of GG_FETCH_DATA_PARA_TYPE

+ * @return  GGSTATUS

+ */

+EXPORTS GGSTATUS upiGG_FetchDataParameter(char *pObj, GG_FETCH_DATA_PARA_TYPE data);

+

+#endif     //endif ENABLE_BQ27520_SW_CMD

+

+typedef struct GG_FETCH_DEBUG_DATA_ST {

+  /// [AT-PM] : Driver version ; 01/30/2013

+  int versionMain;

+  int versionOtp;

+  int versionSub;

+

+  /// [AT-PM] : Capacity related ; 01/30/2013

+  int capStatus;

+  int capSelfHour;

+  int capSelfMin;

+  int capSelfSec;

+  int capSelfMilliSec;

+  int capTPTime;

+  int capDelta;

+  int capDsgCharge;

+  int capDsgChargeStart;

+  int capDsgChargeTime;

+  int capPreDsgCharge;

+  int capTableUpdateIdx;

+

+  /// [AT-PM] : Measurement related ; 01/30/2013

+  int measCodeBat1;

+  int measCodeCurrent;

+  int measCodeIT;

+  int measCodeET;

+  int measCharge;

+  int measCCOffset;

+  int measAdc1ConvertTime;

+  int measAdc1Gain;

+  int measAdc1Offset;

+  int measAdc2Gain;

+  int measAdc2Offset;

+  int measLastCounter;

+  int measLastTimeTick;

+  int measLastDeltaQ;

+  

+#if defined(uG31xx_OS_ANDROID)

+  }__attribute__((aligned(4))) GG_FETCH_DEBUG_DATA_TYPE;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+  } GG_FETCH_DEBUG_DATA_TYPE;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/**

+ * @brief upiGG_FetchDebugData

+ *

+ *  Fetch debug information data

+ *

+ * @para  pObj  address of memory buffer

+ * @para  data  address of GG_FETCH_CAP_DATA_TYPE

+ * @return  _UPI_NULL_

+ */

+EXPORTS void upiGG_FetchDebugData(char *pObj, GG_FETCH_DEBUG_DATA_TYPE *data);

+

+/**

+ * @brief upiGG_DebugSwitch

+ *

+ *  Enable/disable debug information to UART

+ *

+ * @para  Enable  set _UPI_TRUE_ to enable it

+ * @return  NULL

+ */

+EXPORTS void upiGG_DebugSwitch(_upi_bool_ enable);

+

+EXPORTS void upiGG_CheckBackupFile(char *pObj);

+

+#endif  ///< end of _UG31XXAPI_H_

+

+/// ===========================================

+/// End of uG31xx_API.h

+/// ===========================================

+

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Backup.h b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Backup.h
new file mode 100755
index 0000000..bcc4c50
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Backup.h
@@ -0,0 +1,54 @@
+/**

+ * @filename  uG31xx_API_Backup.h

+ *

+ *  Header of uG31xx_API_Backup.cpp

+ *

+ * @author  AllenTeng <allen_teng@upi-semi.com>

+ */

+

+#define BACKUP_BOOL_TRUE      (1)

+#define BACKUP_BOOL_FALSE     (0)

+

+#define BACKUP_FILE_PATH              ("/sdcard/upi_gg")

+

+enum BACKUP_FILE_STS {

+  BACKUP_FILE_STS_CHECKING = 0,

+  BACKUP_FILE_STS_NOT_EXIST,

+  BACKUP_FILE_STS_EXIST,

+  BACKUP_FILE_STS_COMPARE,

+};

+

+typedef unsigned char _backup_bool_;

+typedef unsigned char _backup_u8_;

+

+typedef struct BackupDataST {

+

+  CapacityDataType *capData;

+  SystemDataType *sysData;

+  MeasDataType *measData;

+

+  _backup_bool_ icDataAvailable;

+  _backup_u8_ backupFileSts;

+  

+  #if defined (uG31xx_OS_WINDOWS)

+    const wchar_t* backupFileName;

+  #elif defined(uG31xx_OS_ANDROID)

+    char *backupFileName;

+  #endif

+

+#if defined(uG31xx_OS_ANDROID)

+    } __attribute__ ((aligned(4))) BackupDataType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)	      

+    } BackupDataType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/**

+ * @brief UpiBackupData

+ *

+ *  Backup data from IC to system routine

+ *

+ * @para  data  address of BackupDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiBackupData(BackupDataType *data);

+

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Capacity.h b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Capacity.h
new file mode 100755
index 0000000..aa888ca
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Capacity.h
@@ -0,0 +1,132 @@
+/**

+ * @filename  uG31xx_API_Capacity.h

+ *

+ *  Header of uG31xx capacity algorithm

+ *

+ * @author  AllenTeng <allen_teng@upi-semi.com>

+ */

+

+typedef _upi_bool_            _cap_bool_;

+typedef unsigned char   _cap_u8_;

+typedef signed char     _cap_s8_;

+typedef unsigned short  _cap_u16_;

+typedef signed short    _cap_s16_;

+typedef unsigned long   _cap_u32_;

+typedef signed long     _cap_s32_;

+

+#define CAP_FC_RELEASE_RSOC     (99)

+#define UG31XX_CAP_VERSION      (36)

+#define CAP_ENCRIPT_TABLE_SIZE  (TEMPERATURE_NUMS*C_RATE_NUMS*(SOV_NUMS - 1))

+

+typedef struct CapacityDataST {

+

+  /// [AT-PM] : Data from GGB file ; 01/25/2013

+  CELL_PARAMETER *ggbParameter;

+  CELL_TABLE *ggbTable;

+  

+  /// [AT-PM] : Measurement data ; 01/25/2013

+  MeasDataType *measurement;

+

+  /// [AT-PM] : Data for table backup ; 01/31/2013

+  TableBackupType tableBackup[SOV_NUMS];

+  _cap_u8_ encriptTable[CAP_ENCRIPT_TABLE_SIZE];

+

+  /// [AT-PM] : Capacity information ; 01/25/2013

+  _cap_u16_ rm;

+  _cap_u16_ fcc;

+  _cap_u16_ fccBackup;

+  _cap_u8_ rsoc;

+

+  /// [AT-PM] : Capacity operation variables ; 01/25/2013

+  _cap_u32_ status;

+

+  _cap_u32_ selfDsgMilliSec;

+  _cap_u8_ selfDsgSec;

+  _cap_u8_ selfDsgMin;

+  _cap_u8_ selfDsgHour;

+  _cap_u8_ selfDsgResidual;

+

+  _cap_u8_ lastRsoc;

+

+  _cap_u32_ tpTime;

+

+  _cap_s32_ dsgCharge;

+  _cap_s32_ dsgChargeStart;

+  _cap_u32_ dsgChargeTime;

+  _cap_s32_ preDsgCharge;

+

+  _cap_u8_ tableUpdateIdx;

+  _cap_u32_ tableUpdateDisqTime;

+  _cap_u8_ tableUpdateDelayCnt;

+

+  _cap_s8_ parseRMResidual;

+

+  _cap_s16_ reverseCap;

+  _cap_u8_ avgCRate;  

+

+  _cap_s16_ ccRecord[SOV_NUMS];

+#if defined(uG31xx_OS_ANDROID)

+  } __attribute__ ((aligned(4))) CapacityDataType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)	      

+  } CapacityDataType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/**

+ * @brief UpiInitCapacity

+ *

+ *  Initial capacity algorithm

+ *

+ * @para  data  address of CapacityDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiInitCapacity(CapacityDataType *data);

+

+/**

+ * @brief UpiReadCapacity

+ *

+ *  Read capacity information

+ *

+ * @para  data  address of CapacityDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiReadCapacity(CapacityDataType *data);

+

+/**

+ * @brief UpiTableCapacity

+ *

+ *  Look up capacity from table

+ *

+ * @para  data  address of CapacityDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiTableCapacity(CapacityDataType *data);

+

+/**

+ * @brief UpiInitDsgCharge

+ *

+ *  Initialize data->dsgCharge value

+ *

+ * @para  data  address of CapacityDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiInitDsgCharge(CapacityDataType *data);

+

+/**

+ * @brief UpiInitNacTable

+ *

+ *  Initialize NAC table

+ *

+ * @para  data  address of CapacityDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiInitNacTable(CapacityDataType *data);

+

+/**

+ * @brief UpiSaveNacTable

+ *

+ *  Save NAC table to IC

+ *

+ * @para  data  address of CapacityDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiSaveNacTable(CapacityDataType *data);

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Measurement.c b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Measurement.c
new file mode 100755
index 0000000..903b8c1
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Measurement.c
@@ -0,0 +1,1482 @@
+/**

+ * @filename  uG31xx_API_Measurement.cpp

+ *

+ *  guG31xx measurement API

+ *

+ * @author  AllenTeng <allen_teng@upi-semi.com>

+ */

+

+#include "stdafx.h"     //windows need this??

+#include "uG31xx_API.h"

+

+//#define MEAS_FAKE_INT_TEMP

+#ifdef  MEAS_FAKE_INT_TEMP

+  #define MEAS_FAKE_INT_TEMP_OFFSET     (200)

+#endif  ///< end of MEAS_FAKE_INT_TEMP

+

+typedef struct MeasDataInternalST {

+

+  MeasDataType *info;

+  

+  _meas_s16_ adc1CodeT25V100;

+  _meas_s16_ adc1CodeT25V200;

+  _meas_s16_ adc1CodeT80V100;

+  _meas_s16_ adc1CodeT80V200;

+

+  _meas_s16_ adc2CodeT25V100;

+  _meas_s16_ adc2CodeT25V200;

+  _meas_s16_ adc2CodeT80V100;

+  _meas_s16_ adc2CodeT80V200;

+

+  _meas_u32_ currTime;

+

+  _meas_u16_ codeBat1;

+  _meas_s16_ codeCurrent;

+  _meas_u16_ codeIntTemperature;

+  _meas_u16_ codeExtTemperature;

+  _meas_s16_ codeCharge;

+  _meas_u16_ codeCounter;

+  _meas_s16_ ccOffset;

+

+#if defined(uG31xx_OS_ANDROID)

+  } __attribute__ ((aligned(4))) MeasDataInternalType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+  } MeasDataInternalType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct AdcDeltaCodeMappingST {

+  _meas_s32_ Adc1V100;

+  _meas_s32_ Adc1V200;

+  _meas_s32_ Adc2V100;

+  _meas_s32_ Adc2V200;

+#if defined(uG31xx_OS_ANDROID)

+}__attribute__((aligned(4))) AdcDeltaCodeMappingType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+} AdcDeltaCodeMappingType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+static AdcDeltaCodeMappingType AdcDeltaCodeMapping[] =

+{

+  { -12800, -25600, 1536,  0    },     ///< Index = 0

+  { -12544, -25088, 1600,  128  },     ///< Index = 1

+  { -13056, -26112, 1472, -128  },     ///< Index = 2

+  { -12288, -24576, 1664,  256  },     ///< Index = 3

+  { -13312, -26624, 1408, -256  },     ///< Index = 4

+  { -12032, -24064, 1728,  384  },     ///< Index = 5

+  { -13568, -27136, 1344, -384  },     ///< Index = 6

+  { -11776, -23552, 1792,  512  },     ///< Index = 7

+  { -13824, -27648, 1280, -512  },     ///< Index = 8

+  { -11520, -23040, 1856,  640  },     ///< Index = 9

+  { -14080, -28160, 1216, -640  },     ///< Index = 10

+  { -11264, -22528, 1920,  768  },     ///< Index = 11

+  { -14336, -28672, 1152, -768  },     ///< Index = 12

+  { -11008, -22016, 1984,  896  },     ///< Index = 13

+  { -14592, -29184, 1088, -896  },     ///< Index = 14

+  { -10752, -21504, 2048,  1024 },     ///< Index = 15

+  { -14848, -29696, 1024, -1024 },     ///< Index = 16

+  { -10496, -20992, 2112,  1152 },     ///< Index = 17

+  { -15104, -30208, 960,  -1152 },     ///< Index = 18

+  { -10240, -20480, 2176,  1280 },     ///< Index = 19

+  { -15360, -30720, 896,  -1280 },     ///< Index = 20

+  { -9984,  -19968, 2240,  1408 },     ///< Index = 21

+  { -15616, -31232, 832,  -1408 },     ///< Index = 22

+  { -9728,  -19456, 2304,  1536 },     ///< Index = 23

+  { -15872, -31744, 768,  -1536 },     ///< Index = 24

+  { -9472,  -18944, 2368,  1664 },     ///< Index = 25

+  { -16128, -32256, 704,  -1664 },     ///< Index = 26

+  { -9216,  -18432, 2432,  1792 },     ///< Index = 27

+  { -16384, -32768, 640,  -1792 },     ///< Index = 28

+  { -8960,  -17920, 2496,  1920 },     ///< Index = 29

+  { -16640, -33280, 576,  -1920 },     ///< Index = 30

+  { 0,      0,      0,     0    },     ///< Index = 31

+};

+

+#define ADC_TEMPERATURE_GAIN_CONST            (1000)

+

+#define ADC1_CODE_100MV_NEGATIVE              (0xFF00)

+#define ADC1_CODE_200MV_NEGATIVE              (0xFE00)

+#define ADC1_CP_CODE_25_100MV                 (12288)

+#define ADC1_CP_CODE_25_200MV                 (24576)

+#define ADC1_DELTA_CODE_25_100MV_SIGN_BIT     (1<<8)

+#define ADC1_DELTA_CODE_25_200MV_SIGN_BIT     (1<<9)

+#define ADC1_TEMPERATURE_GAIN_100MV           (869600)

+#define ADC1_TEMPERATURE_GAIN_200MV           (-695680)

+

+/**

+ * @brief ConvertAdc1Data

+ *

+ *  Convert ADC1 data from OTP

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void ConvertAdc1Data(MeasDataInternalType *obj)

+{

+  _meas_u16_ tmp16;

+  _meas_s32_ tmp32;

+  

+  /// [AT-PM] : Get code T25 100mV ; 01/23/2013

+  tmp16 = obj->info->otp->adc1DeltaCodeT25V100;

+  if(tmp16 & ADC1_DELTA_CODE_25_100MV_SIGN_BIT)

+  {

+    tmp16 = tmp16 & (~ADC1_DELTA_CODE_25_100MV_SIGN_BIT);

+    if(tmp16 != 0)

+    {

+      tmp16 = tmp16 + ADC1_CODE_100MV_NEGATIVE;

+    }

+  }

+  tmp16 = tmp16 + ADC1_CP_CODE_25_100MV;

+  tmp32 = (_meas_s32_)(_meas_s16_)tmp16;

+  tmp32 = tmp32 + AdcDeltaCodeMapping[obj->info->otp->indexAdc1V100T25].Adc1V100;

+  obj->adc1CodeT25V100 = (_meas_s16_)tmp32;

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[ConvertAdc1Data] adc1CodeT25V100 = %d\n", tmp32);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  

+  /// [AT-PM] : Get code T25 200mV ; 01/23/2013

+  tmp16 = obj->info->otp->adc1DeltaCodeT25V200;

+  if(tmp16 & ADC1_DELTA_CODE_25_200MV_SIGN_BIT)

+  {

+    tmp16 = tmp16 & (~ADC1_DELTA_CODE_25_200MV_SIGN_BIT);

+    if(tmp16 != 0)

+    {

+      tmp16 = tmp16 + ADC1_CODE_200MV_NEGATIVE;

+    }

+  }

+  tmp16 = tmp16 + ADC1_CP_CODE_25_200MV;

+  tmp32 = (_meas_s32_)(_meas_s16_)tmp16;

+  tmp32 = tmp32 + AdcDeltaCodeMapping[obj->info->otp->indexAdc1V200T25].Adc1V200;

+  obj->adc1CodeT25V200 = (_meas_s16_)tmp32;

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvertAdc1Data] adc1CodeT25V200 = %d\n", tmp32);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+  

+  tmp32 = (_meas_s32_)obj->info->otp->aveIT80;

+  tmp32 = (tmp32 - obj->info->otp->aveIT25)*ADC_TEMPERATURE_GAIN_CONST;

+

+  /// [AT-PM] : Get code T80 100mV ; 01/23/2013

+  obj->adc1CodeT80V100 = (_meas_s16_)(tmp32/ADC1_TEMPERATURE_GAIN_100MV + obj->adc1CodeT25V100);

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvertAdc1Data] adc1CodeT80V100 = %d\n", obj->adc1CodeT80V100);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+  

+  /// [AT-PM] : Get code T80 200mV ; 01/23/2013

+  obj->adc1CodeT80V200 = (_meas_s16_)(tmp32/ADC1_TEMPERATURE_GAIN_200MV + obj->adc1CodeT25V200);

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvertAdc1Data] adc1CodeT80V200 = %d\n", obj->adc1CodeT80V200);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+}

+

+#define ADC2_CODE_100MV_NEGATIVE              (0xFFC0)

+#define ADC2_CODE_200MV_NEGATIVE              (0xFF80)

+#define ADC2_CP_CODE_25_100MV                 (3072)

+#define ADC2_CP_CODE_25_200MV                 (6144)

+#define ADC2_DELTA_CODE_25_100MV_SIGN_BIT     (1<<6)

+#define ADC2_DELTA_CODE_25_200MV_SIGN_BIT     (1<<7)

+#define ADC2_TEMPERATURE_GAIN_100MV           (-149130)

+#define ADC2_TEMPERATURE_GAIN_200MV           (-136937)

+

+/**

+ * @brief ConvertAdc2Data

+ *

+ *  Convert ADC2 data from OTP

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void ConvertAdc2Data(MeasDataInternalType *obj)

+{

+  _meas_u16_ tmp16;

+  _meas_s32_ tmp32;

+

+  /// [AT-PM] : Get code T25 100mV ; 01/23/2013

+  tmp16 = obj->info->otp->adc2DeltaCodeT25V100;

+  if(tmp16 & ADC2_DELTA_CODE_25_100MV_SIGN_BIT)

+  {

+    tmp16 = tmp16 & (~ADC2_DELTA_CODE_25_100MV_SIGN_BIT);

+    tmp16 = tmp16 + ADC2_CODE_100MV_NEGATIVE;

+  }

+  tmp16 = tmp16 + ADC2_CP_CODE_25_100MV;

+  tmp32 = (_meas_s32_)(_meas_s16_)tmp16;

+  tmp32 = tmp32 + AdcDeltaCodeMapping[obj->info->otp->indexAdc2V100T25].Adc2V100;

+  obj->adc2CodeT25V100 = (_meas_s16_)tmp32;

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvertAdc2Data] adc2CodeT25V100 = %d\n", tmp32);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+

+  /// [AT-PM] : Get code T25 200mV ; 01/23/2013

+  tmp16 = obj->info->otp->adc2DeltaCodeT25V200;

+  if(tmp16 & ADC2_DELTA_CODE_25_200MV_SIGN_BIT)

+  {

+    tmp16 = tmp16 & (~ADC2_DELTA_CODE_25_200MV_SIGN_BIT);

+    tmp16 = tmp16 + ADC2_CODE_200MV_NEGATIVE;

+  }

+  tmp16 = tmp16 + ADC2_CP_CODE_25_200MV;

+  tmp32 = (_meas_s32_)(_meas_s16_)tmp16;

+  tmp32 = tmp32 + AdcDeltaCodeMapping[obj->info->otp->indexAdc2V200T25].Adc2V200;

+  obj->adc2CodeT25V200 = (_meas_s16_)tmp32;

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvertAdc2Data] adc2CodeT25V200 = %d\n", tmp32);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+

+  tmp32 = (_meas_s32_)obj->info->otp->aveIT80;

+  tmp32 = (tmp32 - obj->info->otp->aveIT25)*ADC_TEMPERATURE_GAIN_CONST;

+

+  /// [AT-PM] : Get code T80 100mV ; 01/23/2013

+  obj->adc2CodeT80V100 = (_meas_s16_)(tmp32/ADC2_TEMPERATURE_GAIN_100MV + obj->adc2CodeT25V100);

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvertAdc2Data] adc2CodeT80V100 = %d\n", obj->adc2CodeT80V100);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+

+  /// [AT-PM] : Get code T80 200mV ; 01/23/2013

+  obj->adc2CodeT80V200 = (_meas_s16_)(tmp32/ADC2_TEMPERATURE_GAIN_200MV + obj->adc2CodeT25V200);

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvertAdc2Data] adc2CodeT80V200 = %d\n", obj->adc2CodeT80V200);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+}

+

+/**

+ * @brief CalAdc1Factors

+ *

+ *  Calculate ADC1 gain slope and factor B

+ *  Calculate ADC1 offset slope and factor O

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void CalAdc1Factors(MeasDataInternalType *obj)

+{

+  _meas_s32_ delta25;

+  _meas_s32_ delta80;

+  _meas_s64_ tmp64;

+

+  /// [AT-PM] : Calculate gain slope and factor B ; 01/23/2013

+  delta25 = (_meas_s32_)obj->adc1CodeT25V200;

+  delta25 = delta25 - obj->adc1CodeT25V100;

+  delta80 = (_meas_s32_)obj->adc1CodeT80V200;

+  delta80 = delta80 - obj->adc1CodeT80V100;

+

+  obj->info->adc1GainSlope = delta80 - delta25;

+  obj->info->adc1GainFactorB = delta25*(obj->info->otp->aveIT80) - delta80*(obj->info->otp->aveIT25);

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[CalAdc1Factors] adc1GainSlope / adc1GainFactorB  = %d / %d\n", obj->info->adc1GainSlope, obj->info->adc1GainFactorB);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+

+  /// [AT-PM] : Calculate offset slope and factor O ; 01/23/2013

+  delta25 = (_meas_s32_)obj->adc1CodeT25V100;

+  delta25 = delta25*2 - obj->adc1CodeT25V200;

+  delta80 = (_meas_s32_)obj->adc1CodeT80V100;

+  delta80 = delta80*2 - obj->adc1CodeT80V200;

+

+  obj->info->adc1OffsetSlope = delta80 - delta25;

+  obj->info->adc1OffsetFactorO = delta25*(obj->info->otp->aveIT80) - delta80*(obj->info->otp->aveIT25);

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+		printf("[CalAdc1Factors] adc1OffsetSlope / adc1OffsetFactorO = %d / %d\n", obj->info->adc1OffsetSlope, obj->info->adc1OffsetFactorO);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+

+  /// [AT-PM] : Calculate current ADC1 gain ; 01/23/2013

+  tmp64 = (_meas_s64_)obj->info->adc1GainSlope;

+  tmp64 = tmp64*(obj->codeIntTemperature) + obj->info->adc1GainFactorB;

+  obj->info->adc1Gain = (_meas_s32_)tmp64;

+

+  /// [AT-PM] : Calculate current ADC1 offset ; 01/23/2013

+  tmp64 = (_meas_s64_)obj->info->adc1OffsetSlope;

+  tmp64 = tmp64*(obj->codeIntTemperature) + obj->info->adc1OffsetFactorO;

+  obj->info->adc1Offset = (_meas_s32_)tmp64;

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[CalAdc1Factors] adc1Gain / adc1Offset = %d / %d\n", obj->info->adc1Gain, obj->info->adc1Offset);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+}

+

+/**

+ * @brief CalAdc2Factors

+ *

+ *  Calculate ADC2 gain slope and factor B

+ *  Calculate ADC2 offset slope and factor O

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void CalAdc2Factors(MeasDataInternalType *obj)

+{

+  _meas_s32_ delta25;

+  _meas_s32_ delta80;

+  _meas_s64_ tmp64;

+

+  /// [AT-PM] : Calculate gain slope and factor B ; 01/23/2013

+  delta25 = (_meas_s32_)obj->adc2CodeT25V200;

+  delta25 = delta25 - obj->adc2CodeT25V100;

+  delta80 = (_meas_s32_)obj->adc2CodeT80V200;

+  delta80 = delta80 - obj->adc2CodeT80V100;

+

+  obj->info->adc2GainSlope = delta80 - delta25;

+  obj->info->adc2GainFactorB = delta25*(obj->info->otp->aveIT80) - delta80*(obj->info->otp->aveIT25);

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[CalAdc2Factors] adc2GainSlope / adc2GainFactorB = %d / %d\n", obj->info->adc2GainSlope, obj->info->adc2GainFactorB);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+

+  /// [AT-PM] : Calculate offset slope and factor O ; 01/23/2013

+  delta25 = (_meas_s32_)obj->adc2CodeT25V100;

+  delta25 = delta25*2 - obj->adc2CodeT25V200;

+  delta80 = (_meas_s32_)obj->adc2CodeT80V100;

+  delta80 = delta80*2 - obj->adc2CodeT80V200;

+

+  obj->info->adc2OffsetSlope = delta80 - delta25;

+  obj->info->adc2OffsetFactorO = delta25*(obj->info->otp->aveIT80) - delta80*(obj->info->otp->aveIT25);

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[CalAdc2Factors] adc2OffsetSlope / adc2OffsetFactorO = %d / %d\n", obj->info->adc2OffsetSlope, obj->info->adc2OffsetFactorO);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+

+  /// [AT-PM] : Calculate current ADC1 gain ; 01/23/2013

+  tmp64 = (_meas_s64_)obj->info->adc2GainSlope;

+  tmp64 = tmp64*(obj->codeIntTemperature) + obj->info->adc2GainFactorB;

+  obj->info->adc2Gain = (_meas_s32_)tmp64;

+

+  /// [AT-PM] : Calculate current ADC1 offset ; 01/23/2013

+  tmp64 = (_meas_s64_)obj->info->adc2OffsetSlope;

+  tmp64 = tmp64*(obj->codeIntTemperature) + obj->info->adc2OffsetFactorO;

+  obj->info->adc2Offset = (_meas_s32_)tmp64;

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[CalAdc2Factors] adc2Gain / adc2Offset = %d / %d\n", obj->info->adc2Gain, obj->info->adc2Offset);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+}

+

+#define ADC1_IDEAL_CODE_100MV     (614)

+#define ADC1_IDEAL_CODE_200MV     (1229)

+#define ADC1_IDEAL_CODE_DELTA     (ADC1_IDEAL_CODE_200MV - ADC1_IDEAL_CODE_100MV)

+

+/**

+ * @brief CalibrateAdc1Code

+ *

+ *  Calibrate ADC1 code

+ *

+ * @para  obj address of MeasDataInternalType

+ * @para  code  ADC1 code to be calibrated

+ * @return  calibrated code

+ */

+_meas_s32_ CalibrateAdc1Code(MeasDataInternalType *obj, _meas_s32_ code)

+{

+  _meas_s64_ tmp64;

+  _meas_s32_ tmp32;

+  _meas_s32_ deltaIT;

+  _meas_s32_ gain;

+  _meas_s32_ offset;

+

+  deltaIT = (_meas_s32_)obj->info->otp->aveIT80;

+  deltaIT = deltaIT - obj->info->otp->aveIT25;

+

+  /// [AT-PM] : Pre-operation to avoid 64-bit division ; 01/23/2013

+  gain = obj->info->adc1Gain;

+  offset = obj->info->adc1Offset;

+  while(1)

+  {

+    tmp64 = (_meas_s64_)code;

+    tmp64 = tmp64*deltaIT - offset;

+    tmp64 = tmp64*ADC1_IDEAL_CODE_DELTA;

+    if((tmp64 < 2147483647) && (tmp64 > -2147483647))

+    {

+      break;

+    }

+    code = code/2;

+    deltaIT = deltaIT/2;

+    gain = gain/4;

+    offset = offset/4;

+  }

+

+  tmp32 = (_meas_s32_)tmp64;

+  tmp32 = tmp32/gain;

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[CalibrateAdc1Code] %d -> %d\n", code, tmp32);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  return (tmp32);

+}

+

+#define ADC2_IDEAL_CODE_100MV     (ADC2_CP_CODE_25_100MV)

+#define ADC2_IDEAL_CODE_200MV     (ADC2_CP_CODE_25_200MV)

+#define ADC2_IDEAL_CODE_DELTA     (ADC2_IDEAL_CODE_200MV - ADC2_IDEAL_CODE_100MV)

+

+/**

+ * @brief CalibrateAdc2Code

+ *

+ *  Calibrate ADC2 code

+ *

+ * @para  obj address of MeasDataInternalType

+ * @para  code  ADC2 code to be calibrated

+ * @return  calibrated code

+ */

+_meas_s32_ CalibrateAdc2Code(MeasDataInternalType *obj, _meas_s32_ code)

+{

+  _meas_s64_ tmp64;

+  _meas_s32_ tmp32;

+  _meas_s32_ deltaIT;

+  _meas_s32_ gain;

+  _meas_s32_ offset;

+

+  deltaIT = (_meas_s32_)obj->info->otp->aveIT80;

+  deltaIT = deltaIT - obj->info->otp->aveIT25;

+

+  /// [AT-PM] : Pre-operation to avoid 64-bit division ; 01/23/2013

+  gain = obj->info->adc2Gain;

+  offset = obj->info->adc2Offset;

+  while(1)

+  {

+    tmp64 = (_meas_s64_)code;

+    tmp64 = tmp64*deltaIT - offset;

+    tmp64 = tmp64*ADC2_IDEAL_CODE_DELTA;

+    if((tmp64 < 2147483647) && (tmp64 > -2147483647))

+    {

+      break;

+    }

+    code = code/2;

+    deltaIT = deltaIT/2;

+    gain = gain/4;

+    offset = offset/4;

+  }

+

+  tmp32 = (_meas_s32_)tmp64;

+  tmp32 = tmp32/gain;

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[CalibrateAdc2Code] %d -> %d\n", code, tmp32);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+  return (tmp32);

+}

+

+#define IT_IDEAL_CODE_25      (24310)

+#define IT_IDEAL_CODE_80      (28612)

+#define IT_IDEAL_CODE_DELTA   (IT_IDEAL_CODE_80 - IT_IDEAL_CODE_25)

+

+/**

+ * @brief CalibrateITCode

+ *

+ *  Calibrate internal temperature code

+ *

+ * @para  obj address of MeasDataInternalType

+ * @para  itCode  raw IT code

+ * @return  calibrated IT code

+ */

+_meas_u16_ CalibrateITCode(MeasDataInternalType *obj, _meas_u16_ itCode)

+{

+  _meas_s32_ tmp32;

+

+  tmp32 = (_meas_s32_)itCode;

+  tmp32 = tmp32 - obj->info->otp->aveIT25;

+  tmp32 = tmp32*IT_IDEAL_CODE_DELTA;

+  tmp32 = tmp32/(obj->info->otp->aveIT80 - obj->info->otp->aveIT25);

+  tmp32 = tmp32 + IT_IDEAL_CODE_25;

+  return ((_meas_u16_)tmp32);

+}

+

+#define NORMAL_REGISTER     (NORMAL)

+

+/**

+ * @brief CalibrateChargeCode

+ *

+ *  Calibrate charge code

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void CalibrateChargeCode(MeasDataInternalType *obj)

+{

+  _meas_s32_ tmp32;

+  _meas_s64_ tmp64;

+  _meas_s32_ gain;

+  _meas_s32_ offset;

+

+  UG31_LOGI("[%s]: Raw Code = %d\n", __func__, obj->codeCharge);

+  

+  /// [AT-PM] : Calibrate charge code ; 01/23/2013

+  obj->info->codeCharge = CalibrateAdc1Code(obj, ((_meas_s32_)obj->codeCharge)*2);

+

+  /// [AT-PM] : Calculate coulomb counter offset ; 01/23/2013

+  tmp32 = obj->info->adc1Offset/(obj->info->otp->aveIT80 - obj->info->otp->aveIT25)*(-1);

+  obj->info->ccOffset = (_meas_s16_)tmp32;

+

+  UG31_LOGI("[%s]: Calibrated Code = %d, Offset = %d\n", __func__, obj->info->codeCharge, obj->info->ccOffset);

+

+  /// [AT-PM] : Set coulomb counter offset ; 01/27/2013

+  API_I2C_Write(NORMAL_REGISTER, 

+                UG31XX_I2C_HIGH_SPEED_MODE, 

+                UG31XX_I2C_TEM_BITS_MODE, 

+                REG_ADC1_OFFSET_LOW, 

+                REG_ADC1_OFFSET_HIGH - REG_ADC1_OFFSET_LOW + 1, 

+                (unsigned char *)&obj->info->ccOffset);

+

+  /// [AT-PM] : Remove the offset in calibrated charge code ; 01/23/2013

+  gain = obj->info->adc1Gain;

+  offset = obj->info->adc1Offset;

+  while(1)

+  {

+    tmp64 = (_meas_s64_)offset;

+    tmp64 = tmp64*ADC1_IDEAL_CODE_DELTA;

+    if((tmp64 < 2147483647) && (tmp64 > -2147483647))

+    {

+      break;

+    }

+    gain = gain/2;

+    offset = offset/2;

+  }

+  tmp32 = (_meas_s32_)tmp64;

+  tmp32 = tmp32/gain;

+  UG31_LOGI("[%s]: Compensation = %d x %d / %d\n", __func__, 

+            obj->info->adc1Offset, ADC1_IDEAL_CODE_DELTA, obj->info->adc1Gain);

+  obj->info->codeCharge = obj->info->codeCharge + tmp32;

+  UG31_LOGI("[%s]: Charge = %d\n", __func__, obj->info->codeCharge);

+}

+

+#define ADC2_VOLTAGE_100MV    (3000)                                    ///< [AT-PM] : Unit in mV ; 01/25/2013

+#define ADC2_VOLTAGE_200MV    (4000)                                    ///< [AT-PM] : Unit in mV ; 01/25/2013

+#define ADC2_VOLTAGE_DELTA    (ADC2_VOLTAGE_200MV - ADC2_VOLTAGE_100MV)

+

+/**

+ * @brief ConvertBat1

+ *

+ *  Convert code of BAT1

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void ConvertBat1(MeasDataInternalType *obj)

+{

+  _meas_s32_ tmp32;

+

+  /// [AT-PM] : Convert from calibrated ADC code ; 01/25/2013

+  tmp32 = (_meas_s32_)obj->info->codeBat1;

+  tmp32 = tmp32 - ADC2_IDEAL_CODE_100MV;

+  tmp32 = tmp32*ADC2_VOLTAGE_DELTA/ADC2_IDEAL_CODE_DELTA;

+  tmp32 = tmp32 + ADC2_VOLTAGE_100MV;

+

+  /// [AT-PM] : Apply board factor ; 01/25/2013

+  tmp32 = tmp32 - BOARD_FACTOR_VOLTAGE_OFFSET;

+  tmp32 = tmp32*BOARD_FACTOR_CONST/BOARD_FACTOR_VOLTAGE_GAIN;

+

+  /// [AT-PM] : Apply calibration parameter ; 01/25/2013

+  tmp32 = tmp32 - obj->info->sysData->ggbParameter->adc2_offset;

+  tmp32 = tmp32*CALIBRATION_FACTOR_CONST/obj->info->sysData->ggbParameter->adc2_gain;

+  obj->info->bat1Voltage = (_meas_u16_)tmp32;

+}

+

+#define ADC1_VOLTAGE_100MV    (-5000)                                   ///< [AT-PM] : Unit in uV ; 01/25/2013

+#define ADC1_VOLTAGE_200MV    (-10000)                                  ///< [AT-PM] : Unit in uV ; 01/25/2013

+#define ADC1_VOLTAGE_DELTA    (ADC1_VOLTAGE_200MV - ADC1_VOLTAGE_100MV)

+/**

+ * @brief ConvertCurrent

+ *

+ *  Convert code of Current

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void ConvertCurrent(MeasDataInternalType *obj)

+{

+  _meas_s32_ tmp32;

+

+  /// [AT-PM] : Convert from calibrated ADC code ; 01/25/2013

+  tmp32 = (_meas_s32_)obj->info->codeCurrent;

+  tmp32 = tmp32 - ADC1_IDEAL_CODE_100MV;

+  tmp32 = tmp32*ADC1_VOLTAGE_DELTA/ADC1_IDEAL_CODE_DELTA;

+  tmp32 = tmp32 + ADC1_VOLTAGE_100MV;

+  tmp32 = tmp32/obj->info->sysData->ggbParameter->rSense;

+

+  /// [AT-PM] : Apply board factor ; 01/25/2013

+  tmp32 = tmp32 - BOARD_FACTOR_CURR_OFFSET;

+  tmp32 = tmp32*BOARD_FACTOR_CONST/BOARD_FACTOR_CURR_GAIN;

+

+  /// [AT-PM] : Apply calibration factor ; 01/25/2013

+  tmp32 = tmp32 - obj->info->sysData->ggbParameter->adc1_pos_offset;

+  if(tmp32 > 0)

+  {

+    tmp32 = tmp32*CALIBRATION_FACTOR_CONST/obj->info->sysData->ggbParameter->adc1_pgain;

+  }

+  else

+  {

+    tmp32 = tmp32*CALIBRATION_FACTOR_CONST/obj->info->sysData->ggbParameter->adc1_ngain;

+  }

+  obj->info->curr = (_meas_s16_)tmp32;

+}

+

+#define AMBIENT_TEMPERATURE_IN_FT (220)

+#define IT_CONST                  (100)

+#define IT_GAIN                   (392)

+#define IT_OFFSET                 (11172)

+

+static _meas_s16_ FTAmbientMappingTable[] = 

+{

+  AMBIENT_TEMPERATURE_IN_FT,            ///< Index = 0

+  AMBIENT_TEMPERATURE_IN_FT + 10,       ///< Index = 1

+  AMBIENT_TEMPERATURE_IN_FT - 10,       ///< Index = 2

+  AMBIENT_TEMPERATURE_IN_FT + 20,       ///< Index = 3

+  AMBIENT_TEMPERATURE_IN_FT - 20,       ///< Index = 4

+  AMBIENT_TEMPERATURE_IN_FT + 30,       ///< Index = 5

+  AMBIENT_TEMPERATURE_IN_FT - 30,       ///< Index = 6

+  AMBIENT_TEMPERATURE_IN_FT + 40,       ///< Index = 7

+  AMBIENT_TEMPERATURE_IN_FT - 40,       ///< Index = 8

+  AMBIENT_TEMPERATURE_IN_FT + 50,       ///< Index = 9

+  AMBIENT_TEMPERATURE_IN_FT - 50,       ///< Index = 10

+  AMBIENT_TEMPERATURE_IN_FT + 60,       ///< Index = 11

+  AMBIENT_TEMPERATURE_IN_FT - 60,       ///< Index = 12

+  AMBIENT_TEMPERATURE_IN_FT + 70,       ///< Index = 13

+  AMBIENT_TEMPERATURE_IN_FT - 70,       ///< Index = 14

+  AMBIENT_TEMPERATURE_IN_FT,            ///< Index = 15

+};

+

+/**

+ * @brief ConvertIntTemperature

+ *

+ *  Convert code of internal temperature

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void ConvertIntTemperature(MeasDataInternalType *obj)

+{

+  _meas_s32_ tmp32;

+  _meas_s32_ ftIT;

+

+  /// [AT-PM] : Convert from calibrated ADC code ; 01/25/2013

+  tmp32 = (_meas_s32_)obj->info->codeIntTemperature;

+  tmp32 = tmp32/2;

+  tmp32 = tmp32 - IT_OFFSET;

+  tmp32 = tmp32*IT_CONST/IT_GAIN;

+

+  /// [AT-PM] : Apply FT information ; 01/25/2013

+  ftIT = (_meas_s32_)CalibrateITCode(obj, obj->info->otp->ftIT);

+  ftIT = ftIT/2;

+  ftIT = ftIT - IT_OFFSET;

+  ftIT = ftIT*IT_CONST/IT_GAIN;

+  tmp32 = tmp32 - (ftIT - FTAmbientMappingTable[obj->info->otp->deltaET]);

+

+  /// [AT-PM] : Apply board factor ; 01/25/2013

+  tmp32 = tmp32 - BOARD_FACTOR_INTT_OFFSET;

+

+  /// [AT-PM] : Apply calibration factor ; 01/25/2013

+  tmp32 = tmp32 - obj->info->sysData->ggbParameter->adc_d5;

+  obj->info->intTemperature = (_meas_s16_)tmp32;

+}

+

+static _meas_s16_ ExtTemperatureTable[] = {

+  -100,       ///< Index = 0

+  -50,        ///< Index = 1

+  0,          ///< Index = 2

+  50,         ///< Index = 3

+  100,        ///< Index = 4

+  150,        ///< Index = 5

+  200,        ///< Index = 6

+  250,        ///< Index = 7

+  300,        ///< Index = 8

+  350,        ///< Index = 9

+  400,        ///< Index = 10

+  450,        ///< Index = 11

+  500,        ///< Index = 12

+  550,        ///< Index = 13

+  600,        ///< Index = 14

+  650,        ///< Index = 15

+  700,        ///< Index = 16

+  750,        ///< Index = 17

+  800,        ///< Index = 18

+};

+

+/**

+ * @brief ConvertExtTemperature

+ *

+ *  Convert code of external temperature

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void ConvertExtTemperature(MeasDataInternalType *obj)

+{

+  _meas_u8_ idx;

+  _meas_s32_ tmp32;

+

+  idx = 0;

+  while(idx < ET_NUMS)

+  {

+    if(obj->info->codeExtTemperature >= obj->info->sysData->ggbParameter->rtTable[idx])

+    {

+      break;

+    }

+    idx = idx + 1;

+  }

+  

+  if(idx == 0)

+  {

+    /// [AT-PM] : Minimum measurable temperature ; 01/25/2013

+    tmp32 = (_meas_s32_)ExtTemperatureTable[0];

+  }

+  else if(idx == ET_NUMS)

+  {

+    /// [AT-PM] : Maximum measurable temperature ; 01/25/2013

+    tmp32 = (_meas_s32_)ExtTemperatureTable[ET_NUMS - 1];

+  }

+  else

+  {

+    /// [AT-PM] : Calculate external temperature ; 01/25/2013

+    tmp32 = (_meas_s32_)obj->info->codeExtTemperature;

+    tmp32 = tmp32 - obj->info->sysData->ggbParameter->rtTable[idx];

+    tmp32 = tmp32*(ExtTemperatureTable[idx - 1] - ExtTemperatureTable[idx]);

+    tmp32 = tmp32/(obj->info->sysData->ggbParameter->rtTable[idx - 1] - obj->info->sysData->ggbParameter->rtTable[idx]);

+    tmp32 = tmp32 + ExtTemperatureTable[idx];

+  }

+

+  /// [AT-PM] : Apply board factor ; 01/25/2013

+  tmp32 = tmp32 - BOARD_FACTOR_EXTT_OFFSET;

+

+  /// [AT-PM] : Apply calibration factor ; 01/25/2013

+  tmp32 = tmp32 - obj->info->sysData->ggbParameter->adc_d4;

+  obj->info->extTemperature = (_meas_s16_)tmp32;

+}

+

+#define TIME_DEFAULT_ADC1_CONVERT_TIME        (1253)

+#define MINIMUM_ADC1_COUNTER_FOR_CONVERT_TIME (10)

+#define MAXIMUM_ADC1_CONVERSION_TIME          (0xf8)

+#define MINIMUM_ADC1_CONVERSION_TIME          (0x08)

+

+/**

+ * @brief CalculateAdc1ConvertTime

+ *

+ *  Calculate ADC1 conversion time

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void CalculateAdc1ConvertTime(MeasDataInternalType *obj)

+{

+  _meas_u32_ tmp32;

+

+  UG31_LOGI("[%s]: Initial conversion time = %d\n", __func__, obj->info->adc1ConvertTime);

+  

+  /// [AT-PM] : First time to calculate ADC1 conversion time ; 01/25/2013

+  if(obj->info->adc1ConvertTime == 0)

+  {

+    obj->info->adc1ConvertTime = TIME_DEFAULT_ADC1_CONVERT_TIME;

+    obj->info->lastCounter = obj->codeCounter;    

+    return;

+  }

+

+  #ifdef  uG31xx_BOOT_LOADER

+    /// [AT-PM] : In bootloader, ADC1 converstion time is not calculated ; 02/12/2013

+    return;

+  #endif  ///< end of uG31xx_BOOT_LOADER

+  

+  /// [AT-PM] : Check counter overflow or time overflow; 01/25/2013

+  if((obj->codeCounter <= obj->info->lastCounter) || (obj->info->deltaTime == 0))

+  {

+    obj->info->lastCounter = obj->codeCounter;

+    return;

+  }

+

+  /// [AT-PM] : Limit the minimum counter ; 02/11/2013

+  tmp32 = (_meas_u32_)obj->codeCounter;

+  tmp32 = tmp32 - obj->info->lastCounter;

+  if(tmp32 < MINIMUM_ADC1_COUNTER_FOR_CONVERT_TIME)

+  {

+    obj->info->lastCounter = obj->codeCounter;

+    return;

+  }

+  

+  /// [AT-PM] : Average  ADC1 conversion time ; 01/25/2013

+  tmp32 = obj->info->deltaTime;

+  tmp32 = tmp32*TIME_CONVERT_TIME_TO_MSEC/(obj->codeCounter - obj->info->lastCounter);

+  tmp32 = tmp32 + obj->info->adc1ConvertTime;

+  tmp32 = tmp32/2;

+

+  /// [AT-PM] : Check conversion time is valid or not ; 02/13/2013

+  if((tmp32 > (MAXIMUM_ADC1_CONVERSION_TIME*TIME_CONVERT_TIME_TO_MSEC)) || 

+     (tmp32 < (MINIMUM_ADC1_CONVERSION_TIME*TIME_CONVERT_TIME_TO_MSEC)))

+  {

+    UG31_LOGI("[%s]: ***************************************************************************************\n", __func__);

+    UG31_LOGI("[%s]: ***************************************************************************************\n", __func__);

+    UG31_LOGI("[%s]:  ####  #####  ##  ##  ####  #####  ##   ##  ####  ##       ###### ###### ##   ## ######\n", __func__);

+    UG31_LOGI("[%s]: ##  ## ##  ## ### ## ##  ## ##  ## ### ### ##  ## ##       ######   ##   ### ### ##\n", __func__);

+    UG31_LOGI("[%s]: ###### #####  ###### ##  ## #####  ####### ###### ##         ##     ##   ####### ###\n", __func__);

+    UG31_LOGI("[%s]: ##  ## ##  ## ## ### ##  ## ##  ## ##   ## ##  ## ##         ##     ##   ##   ## ##\n", __func__);

+    UG31_LOGI("[%s]: ##  ## #####  ##  ##  ####  ##  ## ##   ## ##  ## ######     ##   ###### ##   ## ######\n", __func__);

+    UG31_LOGI("[%s]:\n", __func__);

+    UG31_LOGI("[%s]: Previous Time Tag    = %d\n", __func__, obj->info->lastTimeTick - obj->info->deltaTime);

+    UG31_LOGI("[%s]: Current Time Tag     = %d\n", __func__, obj->info->lastTimeTick);

+    UG31_LOGI("[%s]: Delta Time           = %d\n", __func__, obj->info->deltaTime);

+    UG31_LOGI("[%s]: Previous ADC Count   = %d\n", __func__, obj->info->lastCounter);

+    UG31_LOGI("[%s]: Current ADC Count    = %d\n", __func__, obj->codeCounter);

+    UG31_LOGI("[%s]: Delta ADC Count      = %d\n", __func__, obj->codeCounter - obj->info->lastCounter);

+    UG31_LOGI("[%s]: Old ADC Convert Time = %d\n", __func__, obj->info->adc1ConvertTime);

+    UG31_LOGI("[%s]: New ADC Convert Time = %d\n", __func__, tmp32);

+    UG31_LOGI("[%s]: ***************************************************************************************\n", __func__);

+    UG31_LOGI("[%s]: ***************************************************************************************\n", __func__);

+    tmp32 = (_meas_u32_)obj->info->adc1ConvertTime;

+  }

+  UG31_LOGI("[%s]: Conversion Time = %d ((%d - %d)/%d)\n", __func__, 

+            tmp32, obj->codeCounter, obj->info->lastCounter, obj->info->deltaTime);

+  obj->info->adc1ConvertTime = (_meas_u16_)tmp32;

+  obj->info->lastCounter = obj->codeCounter;

+}

+

+#define TIME_MSEC_TO_SEC          (1000)

+#define TIME_SEC_TO_HOUR          (3600)

+#define COULOMB_COUNTER_LSB       (4096)

+

+/**

+ * @brief ConvertCharge

+ *

+ *  Convert code of charge

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void ConvertCharge(MeasDataInternalType *obj)

+{

+  _meas_s16_ tmp16;

+  _meas_s32_ tmp32;

+  _meas_s64_ tmp64;

+

+  /// [AT-PM] : Convert from calibrated ADC code ; 01/25/2013

+  tmp16 = ADC1_IDEAL_CODE_DELTA;

+  tmp32 = (_meas_s32_)obj->info->codeCharge;

+  tmp32 = tmp32 - ADC1_IDEAL_CODE_100MV;

+  while(1)

+  {

+    tmp64 = (_meas_s64_)tmp32;

+    tmp64 = tmp64*ADC1_VOLTAGE_DELTA;

+    if((tmp64 < 2147483647) && (tmp64 > -2147483647))

+    {

+      break;

+    }

+    tmp16 = tmp16/2;

+    tmp32 = tmp32/2;

+  }

+  tmp32 = (_meas_s32_)tmp64;

+  tmp32 = tmp32/tmp16;

+  tmp32 = tmp32 + ADC1_VOLTAGE_100MV;

+  tmp32 = tmp32/obj->info->sysData->ggbParameter->rSense;

+  UG31_LOGI("[%s]: ((%d - %d) x %d / %d + %d) / %d = %d\n", __func__,

+            obj->info->codeCharge, ADC1_IDEAL_CODE_100MV, ADC1_VOLTAGE_DELTA, 

+            ADC1_IDEAL_CODE_DELTA, ADC1_VOLTAGE_100MV, obj->info->sysData->ggbParameter->rSense, tmp32);

+  /// [AT-PM] : Apply board factor ; 01/25/2013

+  tmp32 = tmp32 - BOARD_FACTOR_CURR_OFFSET;

+  tmp32 = tmp32*BOARD_FACTOR_CONST/BOARD_FACTOR_CURR_GAIN;

+  UG31_LOGI("[%s]: Board Factor (%d/%d) -> %d\n", __func__, 

+            BOARD_FACTOR_CURR_GAIN, BOARD_FACTOR_CURR_OFFSET, tmp32);

+

+  /// [AT-PM] : Apply calibration factor ; 01/25/2013

+  tmp32 = tmp32 - obj->info->sysData->ggbParameter->adc1_pos_offset;

+  if(tmp32 > 0)

+  {

+    tmp32 = tmp32*CALIBRATION_FACTOR_CONST/obj->info->sysData->ggbParameter->adc1_pgain;

+  }

+  else

+  {

+    tmp32 = tmp32*CALIBRATION_FACTOR_CONST/obj->info->sysData->ggbParameter->adc1_ngain;

+  }

+  UG31_LOGI("[%s]: Calibration Factor (%d|%d/%d) -> %d\n", __func__,

+            obj->info->sysData->ggbParameter->adc1_pgain, obj->info->sysData->ggbParameter->adc1_ngain, 

+            obj->info->sysData->ggbParameter->adc1_pos_offset, tmp32);

+

+  /// [AT-PM] : Apply time information ; 01/25/2013

+  if(obj->info->inSuspendMode == _UPI_FALSE_)

+  {

+    CalculateAdc1ConvertTime(obj);

+  }

+  tmp32 = tmp32*(obj->info->adc1ConvertTime)/TIME_MSEC_TO_SEC*COULOMB_COUNTER_LSB/TIME_SEC_TO_HOUR;

+  tmp32 = tmp32/TIME_CONVERT_TIME_TO_MSEC;

+

+  /// [AT-PM] : Update capacity information ; 01/25/2013

+  obj->info->deltaCap = (_meas_s16_)tmp32;

+  obj->info->stepCap = obj->info->deltaCap - obj->info->lastDeltaCap;

+  obj->info->lastDeltaCap = obj->info->deltaCap;

+  UG31_LOGI("[%s]: Capacity = %d (%d)\n", __func__, obj->info->deltaCap, obj->info->stepCap);

+}

+

+/**

+ * @brief TimeTick

+ *

+ *  Get the time tick and calculate delta time

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void TimeTick(MeasDataInternalType *obj)

+{

+  if(obj->info->inSuspendMode == _UPI_TRUE_)

+  {

+    /// [AT-PM] : Prevent adc conversion count overflow ; 06/11/2013

+    if(obj->codeCounter < obj->info->lastCounter)

+    {

+      return;

+    }

+    

+    /// [AT-PM] : Use conversion count to estimate delta time ; 06/11/2013

+    obj->info->deltaTime = (_meas_u32_)obj->codeCounter;

+    obj->info->deltaTime = obj->info->deltaTime - obj->info->lastCounter;

+    obj->info->deltaTime = obj->info->deltaTime*obj->info->adc1ConvertTime;

+    return;

+  }

+

+  obj->currTime = GetTickCount();

+

+  /// [AT-PM] : Prevent time tick overflow ; 01/25/2013

+  if(obj->currTime <= obj->info->lastTimeTick)

+  {

+    obj->info->deltaTime = 0;

+    obj->info->lastTimeTick = obj->currTime;

+    UG31_LOGI("[%s]: OVERFLOW -> %d < %d\n", __func__, 

+              obj->currTime, obj->info->lastTimeTick);

+    return;

+  }

+

+  /// [AT-PM] : Calculate delta time ; 01/25/2013

+  obj->info->deltaTime = obj->currTime - obj->info->lastTimeTick;

+  UG31_LOGI("[%s]: Delta Time = %d - %d = %d\n", __func__,

+            obj->currTime, obj->info->lastTimeTick, obj->info->deltaTime);

+  obj->info->lastTimeTick = obj->currTime;  

+}

+

+/**

+ * @brief ReadRegister

+ *

+ *  Read measurement registers

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void ReadRegister(MeasDataInternalType *obj)

+{

+  /// [AT-PM] : Read VBat1Ave ; 01/27/2013

+  API_I2C_Read(NORMAL_REGISTER, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_AVE_VBAT1_LOW, 

+               REG_AVE_VBAT1_HIGH - REG_AVE_VBAT1_LOW + 1, 

+               (unsigned char *)&obj->codeBat1);

+

+  /// [AT-PM] : Read CurrentAve ; 01/27/2013

+  API_I2C_Read(NORMAL_REGISTER, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_AVE_CURRENT_LOW, 

+               REG_AVE_CURRENT_HIGH - REG_AVE_CURRENT_LOW + 1, 

+               (unsigned char *)&obj->codeCurrent);

+

+  /// [AT-PM] : Read ITAve ; 01/27/2013

+  API_I2C_Read(NORMAL_REGISTER, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_AVE_IT_LOW, 

+               REG_AVE_IT_HIGH - REG_AVE_IT_LOW + 1, 

+               (unsigned char *)&obj->codeIntTemperature);

+

+  /// [AT-PM] : Read ETAve ; 01/27/2013

+  API_I2C_Read(NORMAL_REGISTER, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_AVE_ET_LOW, 

+               REG_AVE_ET_HIGH - REG_AVE_ET_LOW + 1, 

+               (unsigned char *)&obj->codeExtTemperature);

+

+  /// [AT-PM] : Read Charge ; 01/27/2013

+  API_I2C_Read(NORMAL_REGISTER, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_CHARGE_LOW, 

+               REG_CHARGE_HIGH - REG_CHARGE_LOW + 1, 

+               (unsigned char *)&obj->codeCharge);

+

+  /// [AT-PM] : Read Counter ; 01/27/2013

+  API_I2C_Read(NORMAL_REGISTER, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_COUNTER_LOW, 

+               REG_COUNTER_HIGH - REG_COUNTER_LOW + 1, 

+               (unsigned char *)&obj->codeCounter);

+

+  /// [AT-PM] : Read Offset ; 01/27/2013

+  API_I2C_Read(NORMAL_REGISTER, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_ADC1_OFFSET_LOW, 

+               REG_ADC1_OFFSET_HIGH - REG_ADC1_OFFSET_LOW + 1, 

+               (unsigned char *)&obj->ccOffset);

+}

+

+/**

+ * @brief ResetCoulombCounter

+ *

+ *  Reset coulomb counter

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  _UPI_NULL_

+ */

+void ResetCoulombCounter(MeasDataInternalType *obj)

+{

+  _meas_u8_ tmp8;

+  

+  API_I2C_Read(NORMAL_REGISTER, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_CTRL1, 

+               1,

+               &tmp8);

+  tmp8 = tmp8 | CTRL1_GG_RST;

+  API_I2C_Write(NORMAL_REGISTER, 

+                UG31XX_I2C_HIGH_SPEED_MODE, 

+                UG31XX_I2C_TEM_BITS_MODE, 

+                REG_CTRL1, 

+                1,

+                &tmp8);    

+}

+

+/**

+ * @brief RevertCalibrateAdc2Code

+ *

+ *  Revert calibrated ADC2 code

+ *

+ * @para  data  address of MeasDataType

+ * @para  caliCode  calibrated ADC2 code

+ * @return  raw ADC2 code

+ */

+_meas_s32_ RevertCalibrateAdc2Code(MeasDataType *data, _meas_s32_ caliCode)

+{

+  _meas_s64_ tmp64;

+  _meas_s32_ tmp32;

+  _meas_s32_ deltaIT;

+  _meas_s32_ gain;

+  _meas_s32_ offset;

+  _meas_s32_ constant;

+

+  /// [AT-PM] : tmp32 = ( caliCode x gain / constant + offset ) / deltaIT ; 04/08/2013

+  gain = data->adc2Gain;

+  offset = data->adc2Offset;

+  deltaIT = (_meas_s32_)data->otp->aveIT80;

+  deltaIT = deltaIT - data->otp->aveIT25;

+  constant = ADC2_IDEAL_CODE_DELTA;

+  while(1)

+  {

+    tmp64 = (_meas_s64_)caliCode;

+    tmp64 = tmp64*gain;

+    if((tmp64 < 2147483647) && (tmp64 > -2147483647))

+    {

+      break;

+    }

+    caliCode = caliCode/2;

+    gain = gain/2;

+    constant = constant/4;

+  }

+  tmp32 = (_meas_s32_)tmp64;

+  tmp32 = tmp32/constant;

+  tmp32 = tmp32 + offset;

+  tmp32 = tmp32/deltaIT;

+  return (tmp32);

+}

+

+/**

+ * @brief RevertBat1Code

+ *

+ *  Revert VBat1 code

+ *

+ * @para  data  address of MeasDataType

+ * @para  volt  voltage in mV to be reverted

+ * @return  adc2 vbat1 code

+ */

+_meas_u16_ RevertBat1Code(MeasDataType *data, _upi_s16_ volt)

+{

+  _meas_s32_ tmp32;

+

+  tmp32 = (_meas_s32_)volt;

+

+  /// [AT-PM] : Revert calibration parameter ; 04/08/2013

+  tmp32 = tmp32*data->sysData->ggbParameter->adc2_gain/CALIBRATION_FACTOR_CONST;

+  tmp32 = tmp32 + data->sysData->ggbParameter->adc2_offset;

+

+  /// [AT-PM] : Revert board factor ; 04/08/2013

+  tmp32 = tmp32*BOARD_FACTOR_VOLTAGE_GAIN/BOARD_FACTOR_CONST;

+  tmp32 = tmp32 + BOARD_FACTOR_VOLTAGE_OFFSET;

+

+  /// [AT-PM] : Revert to calibrated ADC code ; 04/08/2013

+  tmp32 = tmp32 - ADC2_VOLTAGE_100MV;

+  tmp32 = tmp32*ADC2_IDEAL_CODE_DELTA/ADC2_VOLTAGE_DELTA;

+  tmp32 = tmp32 + ADC2_IDEAL_CODE_100MV;

+

+  /// [AT-PM] : Revert to raw code ; 04/08/2013

+  tmp32 = RevertCalibrateAdc2Code(data, tmp32);

+  return ((_meas_u16_)tmp32);

+}

+

+/**

+ * @brief RevertETCode

+ *

+ *  Revert ET code

+ *

+ * @para  data  address of MeasDataType

+ * @para  et  external temperature in 0.1oC to be reverted

+ * @return  adc1 et code

+ */

+_meas_u16_ RevertETCode(MeasDataType *data, _upi_s16_ et)

+{

+  _meas_s32_ tmp32;

+  _meas_u8_ idx;

+

+  tmp32 = (_meas_s32_)et;

+

+  /// [AT-PM] : Revert calibration factor ; 04/08/2013

+  tmp32 = tmp32 + data->sysData->ggbParameter->adc_d4;

+

+  /// [AT-PM] : Revert board factor ; 04/08/2013

+  tmp32 = tmp32 + BOARD_FACTOR_EXTT_OFFSET;

+

+  /// [AT-PM] : Revert external temperature calculation ; 04/08/2013

+  idx = 0;

+  while(idx < ET_NUMS)

+  {

+    if(tmp32 < ExtTemperatureTable[idx])

+    {

+      break;

+    }

+    idx = idx + 1;

+  }

+  if(idx == 0)

+  {

+    tmp32 = (_meas_s32_)data->sysData->ggbParameter->rtTable[0];

+  }

+  else if(idx >= ET_NUMS)

+  {

+    tmp32 = (_meas_s32_)data->sysData->ggbParameter->rtTable[ET_NUMS - 1];

+  }

+  else

+  {

+    tmp32 = tmp32 - ExtTemperatureTable[idx - 1];

+    tmp32 = tmp32*(data->sysData->ggbParameter->rtTable[idx] - data->sysData->ggbParameter->rtTable[idx - 1]);

+    tmp32 = tmp32/(ExtTemperatureTable[idx] - ExtTemperatureTable[idx - 1]);

+    tmp32 = tmp32 + data->sysData->ggbParameter->rtTable[idx - 1];

+  }

+  return ((_meas_u16_)tmp32);

+}

+

+#define MAX_ET_CODE_DIFF  (200)

+#define MIN_ET_CODE_DIFF  (-200)

+

+/**

+ * @brief CalibrateETCode

+ *

+ *  Calibrate external temperature code

+ *

+ * @para  obj address of MeasDataInternalType

+ * @return  MEAS_RTN_CODE

+ */

+_meas_u16_ CalibrateETCode(MeasDataInternalType *obj)

+{

+  _meas_s16_ tmp16;

+

+  tmp16 = (_meas_s16_)obj->codeExtTemperature;

+  tmp16 = tmp16 - (obj->codeCurrent + obj->ccOffset);

+  if(obj->info->codeExtTemperature != 0)

+  {

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[CalibrateETCode]: Last = %d, Current = %d\n", obj->info->codeExtTemperature, tmp16);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+    tmp16 = tmp16 - obj->info->codeExtTemperature;

+    if(tmp16 > MAX_ET_CODE_DIFF)

+    {

+      tmp16 = MAX_ET_CODE_DIFF;

+      UG31_LOGI("[%s]: Exceed maximum ET code difference (%d > %d)\n", __func__, tmp16, MAX_ET_CODE_DIFF);

+    }

+    if(tmp16 < MIN_ET_CODE_DIFF)

+    {

+      tmp16 = MIN_ET_CODE_DIFF;

+      UG31_LOGI("[%s]: Exceed minimum ET code difference (%d < %d)\n", __func__, tmp16, MIN_ET_CODE_DIFF);

+    }

+    tmp16 = tmp16 + obj->info->codeExtTemperature;

+  }

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[CalibrateETCode]: ET code = %d\n", tmp16);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  return ((_meas_u16_)tmp16);

+}

+

+/// =============================================

+/// [AT-PM] : Extern function region

+/// =============================================

+

+/**

+ * @brief UpiResetCoulombCounter

+ *

+ *  Reset coulomb counter

+ *

+ * @para  data  address of MeasDataType

+ * @return  _UPI_NULL_

+ */

+void UpiResetCoulombCounter(MeasDataType *data)

+{

+  MeasDataInternalType *obj;

+  

+  #if defined(uG31xx_OS_ANDROID)

+    #ifdef  uG31xx_BOOT_LOADER

+      obj = (MeasDataInternalType *)malloc(sizeof(MeasDataInternalType));

+    #else   ///< else of uG31xx_BOOT_LOADER

+      obj = (MeasDataInternalType *)kmalloc(sizeof(MeasDataInternalType), GFP_KERNEL);

+    #endif  ///< end of uG31xx_BOOT_LOADER

+  #else   ///< else of defined(uG31xx_OS_ANDROID)

+	  obj = (MeasDataInternalType *)malloc(sizeof(MeasDataInternalType));

+  #endif  ///< end of defined(uG31xx_OS_ANDROID)

+  memset(obj, 0x00, sizeof(MeasDataInternalType));

+  

+  obj->info = data;

+

+  /// [AT-PM] : Get delta time ; 01/25/2013

+  TimeTick(obj);

+

+  /// [AT-PM] : Read ADC code ; 01/27/2013

+  ReadRegister(obj);

+

+  /// [AT-PM] : Reset coulomb counter ; 01/30/2013

+  ResetCoulombCounter(obj);

+

+  /// [AT-PM] : Convert ADC characteristic from OTP ; 01/23/2013

+  ConvertAdc1Data(obj);

+

+  /// [AT-PM] : Calculate ADC gain and offset ; 01/23/2013

+  CalAdc1Factors(obj);

+  

+  /// [AT-PM] : Calibrate ADC code ; 01/23/2013

+  CalibrateChargeCode(obj);

+

+  /// [AT-PM] : Convert into physical value ; 01/23/2013

+  ConvertCharge(obj);

+  data->lastDeltaCap = 0;

+

+  #if defined(uG31xx_OS_ANDROID)

+    #ifdef  uG31xx_BOOT_LOADER

+      free(obj);

+    #else   ///< else of uG31xx_BOOT_LOADER

+      kfree(obj);

+    #endif  ///< end of uG31xx_BOOT_LOADER

+  #else   ///< else of defined(uG31xx_OS_ANDROID)

+    free(obj);

+  #endif  ///< end of defined(uG31xx_OS_ANDROID)

+}

+

+#define MAXIMUM_RETRY_CNT             (10)

+#define MINIMUM_VBAT1_CODE            (ADC2_IDEAL_CODE_100MV/2)

+#define MAXIMUM_CURRENT_CODE          (ADC1_IDEAL_CODE_200MV*6)

+#define MINIMUM_CURRENT_CODE          (ADC1_IDEAL_CODE_200MV*(-6))

+#define MINIMUM_IT_CODE               (IT_IDEAL_CODE_25/2)

+#define MAXIMUM_IT_CODE               (IT_IDEAL_CODE_80*11/10)

+#define MINIMUM_ET_CODE               (1000)

+#define MAXIMUM_ET_CODE               (28000)

+#define RESET_CC_CURRENT_MAGIC_NUMBER (2)

+

+/**

+ * @brief UpiMeasurement

+ *

+ *  Measurement routine

+ *

+ * @para  data  address of MeasDataType

+ * @return  MEAS_RTN_CODE

+ */

+MEAS_RTN_CODE UpiMeasurement(MeasDataType *data)

+{

+  MeasDataInternalType *obj;

+  _meas_u8_ retry;

+  MEAS_RTN_CODE rtn;

+  _meas_s16_ standbyUpper;

+  _meas_s16_ standbyLower;

+  

+  UG31_LOGI("[%s]: Measurement version : %d\n", __func__, UG31XX_MEAS_VERSION);

+

+  #if defined(uG31xx_OS_ANDROID)

+    #ifdef  uG31xx_BOOT_LOADER

+      obj = (MeasDataInternalType *)malloc(sizeof(MeasDataInternalType));

+    #else   ///< else of uG31xx_BOOT_LOADER

+      obj = (MeasDataInternalType *)kmalloc(sizeof(MeasDataInternalType), GFP_KERNEL);

+    #endif  ///< end of uG31xx_BOOT_LOADER

+  #else   ///< else of defined(uG31xx_OS_ANDROID)

+	  obj = (MeasDataInternalType *)malloc(sizeof(MeasDataInternalType));

+  #endif  ///< end of defined(uG31xx_OS_ANDROID)

+  memset(obj, 0x00, sizeof(MeasDataInternalType));

+  

+  obj->info = data;

+  rtn = MEAS_RTN_PASS;

+

+  /// [AT-PM] : Get delta time ; 01/25/2013

+  TimeTick(obj);

+

+  /// [AT-PM] : Read ADC code ; 01/27/2013

+  retry = 0;

+  while(retry < MAXIMUM_RETRY_CNT)

+  {

+    ReadRegister(obj);

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[UpiMeasurement] Retry = %d\n", retry);

+                printf("[UpiMeasurement] VBAT1 Code = %d\n", obj->codeBat1);

+		printf("[UpiMeasurement] CURRENT Code = %d\n", obj->codeCurrent);

+		printf("[UpiMeasurement] IT Code = %d\n", obj->codeIntTemperature);

+		printf("[UpiMeasurement] ET Code = %d\n", obj->codeExtTemperature);

+		printf("[UpiMeasurement] COULOMB COUNTER Code = %d - %d\n", obj->codeCharge, obj->codeCounter);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+

+    if(obj->codeBat1 < MINIMUM_VBAT1_CODE)

+    {

+      UG31_LOGE("[%s]: Voltage code %d < %d -> Retry %d\n", __func__, 

+                obj->codeBat1, MINIMUM_VBAT1_CODE, retry);

+      rtn = MEAS_RTN_BATTERY_REMOVED;

+    }

+    else if(obj->codeCurrent < MINIMUM_CURRENT_CODE)

+    {

+      UG31_LOGE("[%s]: Current code %d < %d\n", __func__,

+                obj->codeCurrent, MINIMUM_CURRENT_CODE);

+      obj->codeCurrent = MINIMUM_CURRENT_CODE;

+      break;

+    }

+    else if(obj->codeCurrent > MAXIMUM_CURRENT_CODE)

+    {

+      UG31_LOGE("[%s]: Current code %d > %d\n", __func__,

+                obj->codeCurrent, MAXIMUM_CURRENT_CODE);

+      obj->codeCurrent = MAXIMUM_CURRENT_CODE;

+      break;

+    }

+    else if(obj->codeIntTemperature < MINIMUM_IT_CODE)

+    {

+      UG31_LOGE("[%s]: Internal Temperature code %d < %d -> Retry %d\n", __func__,

+                obj->codeIntTemperature, MINIMUM_IT_CODE, retry);

+      rtn = MEAS_RTN_ADC_ABNORMAL;

+    }

+    else if(obj->codeIntTemperature > MAXIMUM_IT_CODE)

+    {

+      UG31_LOGE("[%s]: Internal Temperature code %d > %d -> Retry %d\n", __func__,

+                obj->codeIntTemperature, MAXIMUM_IT_CODE, retry);

+      rtn = MEAS_RTN_ADC_ABNORMAL;

+    }

+    else if(obj->codeExtTemperature < MINIMUM_ET_CODE)

+    {

+      UG31_LOGE("[%s]: External Temperature code %d < %d -> Retry %d\n", __func__,

+                obj->codeExtTemperature, MINIMUM_ET_CODE, retry);

+      rtn = MEAS_RTN_NTC_SHORT;

+      #ifndef ENABLE_NTC_CHECK

+        break;

+      #endif  ///< end of ENABLE_NTC_CHECK

+    }

+    else if(obj->codeExtTemperature > MAXIMUM_ET_CODE)

+    {

+      UG31_LOGE("[%s]: External Temperature code %d > %d -> Retry %d\n", __func__,

+                obj->codeExtTemperature, MAXIMUM_ET_CODE, retry);

+      rtn = MEAS_RTN_BATTERY_REMOVED;

+      #ifndef ENABLE_NTC_CHECK

+        break;

+      #endif  ///< end of ENABLE_NTC_CHECK

+    }

+    else

+    {

+      break;

+    }

+    retry = retry + 1;

+    SleepMiniSecond(1000);

+  }

+  if(retry >= MAXIMUM_RETRY_CNT)

+  {

+    #if defined(uG31xx_OS_ANDROID)

+      #ifdef  uG31xx_BOOT_LOADER

+        free(obj);

+      #else   ///< else of uG31xx_BOOT_LOADER

+        kfree(obj);

+      #endif  ///< end of uG31xx_BOOT_LOADER

+    #else   ///< else of defined(uG31xx_OS_ANDROID)

+      free(obj);

+    #endif  ///< end of defined(uG31xx_OS_ANDROID)

+    return (rtn);

+  }

+  rtn = MEAS_RTN_PASS;

+  

+  /// [AT-PM] : Convert ADC characteristic from OTP ; 01/23/2013

+  ConvertAdc1Data(obj);

+  ConvertAdc2Data(obj);

+

+  /// [AT-PM] : Calculate ADC gain and offset ; 01/23/2013

+  CalAdc1Factors(obj);

+  CalAdc2Factors(obj);

+  

+  /// [AT-PM] : Calibrate ADC code ; 01/23/2013

+  data->codeBat1 = (_meas_u16_)CalibrateAdc2Code(obj, (_meas_s32_)obj->codeBat1);

+  UG31_LOGI("[%s]: VBat1 Code = %d -> %d\n", __func__, obj->codeBat1, data->codeBat1);

+  data->codeCurrent = (_meas_s16_)CalibrateAdc1Code(obj, (_meas_s32_)obj->codeCurrent);

+  UG31_LOGI("[%s]: Current Code = %d -> %d\n", __func__, obj->codeCurrent, data->codeCurrent);

+  CalibrateChargeCode(obj);

+  data->codeIntTemperature = CalibrateITCode(obj, obj->codeIntTemperature);

+  UG31_LOGI("[%s]: Internal Temperature Code = %d -> %d\n", __func__,

+            obj->codeIntTemperature, data->codeIntTemperature);

+  data->codeExtTemperature = CalibrateETCode(obj);

+  UG31_LOGI("[%s]: External Temperature Code = %d -> %d\n", __func__, obj->codeExtTemperature, data->codeExtTemperature);

+

+  /// [AT-PM] : Convert into physical value ; 01/23/2013

+  ConvertBat1(obj);

+  ConvertCurrent(obj);

+  ConvertIntTemperature(obj);

+  ConvertExtTemperature(obj);

+  ConvertCharge(obj);

+

+  /// [AT-PM] : Reset coulomb counter if necessary ; 01/27/2013

+  standbyUpper = (_meas_s16_)obj->info->sysData->ggbParameter->standbyCurrent;

+  standbyUpper = standbyUpper/RESET_CC_CURRENT_MAGIC_NUMBER;

+  standbyLower = standbyUpper*(-1);

+  if((obj->codeCounter > COULOMB_COUNTER_RESET_THRESHOLD_COUNTER) ||

+     (obj->codeCharge > COULOMB_COUNTER_RESET_THRESHOLD_CHARGE_CHG) ||

+     (obj->codeCharge < COULOMB_COUNTER_RESET_THREDHOLD_CHARGE_DSG) ||

+     ((obj->info->curr < standbyUpper) && 

+      (obj->info->curr > standbyLower) && 

+      (obj->codeCounter > CONST_CONVERSION_COUNT_THRESHOLD*RESET_CC_CURRENT_MAGIC_NUMBER)))

+  {

+    ResetCoulombCounter(obj);

+    data->lastDeltaCap = 0;

+  }

+

+  #ifdef  MEAS_FAKE_INT_TEMP

+    data->extTemperature = data->intTemperature;

+    data->intTemperature = MEAS_FAKE_INT_TEMP_OFFSET + data->intTemperature%100;

+  #endif  ///< end of MEAS_FAKE_INT_TEMP

+  

+  UG31_LOGI("[%s]: %d mV / %d mA / %d 0.1oC / %d 0.1oC / %d mAh\n", __func__,

+            data->bat1Voltage, data->curr, data->intTemperature, data->extTemperature, data->deltaCap);

+  #if defined(uG31xx_OS_ANDROID)

+    #ifdef  uG31xx_BOOT_LOADER

+      free(obj);

+    #else   ///< else of uG31xx_BOOT_LOADER

+      kfree(obj);

+    #endif  ///< end of uG31xx_BOOT_LOADER

+  #else   ///< else of defined(uG31xx_OS_ANDROID)

+    free(obj);

+  #endif  ///< end of defined(uG31xx_OS_ANDROID)

+  return (rtn);

+}

+

+/**

+ * @brief UpiMeasAlarmThreshold

+ *

+ *  Get alarm threshold

+ *

+ * @para  data  address of MeasDataType

+ * @return  MEAS_RTN_CODE

+ */

+MEAS_RTN_CODE UpiMeasAlarmThreshold(MeasDataType *data)

+{

+  MEAS_RTN_CODE rtn;

+  

+  rtn = MEAS_RTN_PASS;

+

+  /// [AT-PM] : Calculate UV alarm and release threshold ; 04/08/2013

+  data->sysData->uvAlarm.alarmThrd = RevertBat1Code(data, data->sysData->ggbParameter->uvAlarm);

+  data->sysData->uvAlarm.releaseThrd = RevertBat1Code(data, data->sysData->ggbParameter->uvRelease);

+  UG31_LOGI("[%s]: UV Alarm -> %d / %d\n", __func__, 

+            data->sysData->uvAlarm.alarmThrd, data->sysData->uvAlarm.releaseThrd);

+  

+  /// [AT-PM] : Calculate UET alarm and release threshold ; 04/08/2013

+  data->sysData->uetAlarm.alarmThrd = RevertETCode(data, data->sysData->ggbParameter->uetAlarm);

+  data->sysData->uetAlarm.releaseThrd = RevertETCode(data, data->sysData->ggbParameter->uetRelease);

+  UG31_LOGI("[%s]: UET Alarm -> %d / %d\n", __func__, 

+            data->sysData->uetAlarm.alarmThrd, data->sysData->uetAlarm.releaseThrd);

+  

+  /// [AT-PM] : Calculate OET alarm and release threshold ; 04/08/2013

+  data->sysData->oetAlarm.alarmThrd = RevertETCode(data, data->sysData->ggbParameter->oetAlarm);

+  data->sysData->oetAlarm.releaseThrd = RevertETCode(data, data->sysData->ggbParameter->oetRelease);

+  UG31_LOGI("[%s]: OET Alarm -> %d / %d\n", __func__, 

+            data->sysData->oetAlarm.alarmThrd, data->sysData->oetAlarm.releaseThrd);

+

+  return (rtn);

+}

+

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Measurement.h b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Measurement.h
new file mode 100755
index 0000000..482b4b5
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Measurement.h
@@ -0,0 +1,128 @@
+/**

+ * @filename  uG31xx_API_Measurement.h

+ *

+ *  Header for uG31xx measurement API

+ *

+ * @author  AllenTeng <allen_teng@upi-semi.com>

+ */

+

+typedef signed char       _meas_s8_;

+typedef unsigned char     _meas_u8_;

+typedef signed short      _meas_s16_;

+typedef unsigned short    _meas_u16_;

+typedef signed long       _meas_s32_;

+typedef unsigned long     _meas_u32_;

+typedef signed long long  _meas_s64_;

+typedef char              _meas_bool_;

+

+#define UG31XX_MEAS_VERSION     (9)

+

+#define BOARD_FACTOR_CONST          (1000)

+#define BOARD_FACTOR_VOLTAGE_GAIN   (1000)  ///< [AT-PM] : VBat1 board factor - gain ; 01/25/2013

+#define BOARD_FACTOR_VOLTAGE_OFFSET (0)     ///< [AT-PM] : VBat1 board factor - offset ; 01/25/2013

+#define BOARD_FACTOR_CURR_GAIN      (1014)  ///< [AT-PM] : Current board factor - gain ; 01/25/2013

+#define BOARD_FACTOR_CURR_OFFSET    (-7)    ///< [AT-PM] : Current board factor - offset ; 01/25/2013

+#define BOARD_FACTOR_INTT_OFFSET    (-23)   ///< [AT-PM] : Internal Temperature board factor - offset ; 01/25/2013

+#define BOARD_FACTOR_EXTT_OFFSET    (13)    ///< [AT-PM] : External Temperature board factor - offset ; 01/25/2013

+

+#define CALIBRATION_FACTOR_CONST    (1000)

+

+#define COULOMB_COUNTER_RESET_THRESHOLD_COUNTER     (10000)

+#define COULOMB_COUNTER_RESET_THRESHOLD_CHARGE_CHG  (30000)

+#define COULOMB_COUNTER_RESET_THREDHOLD_CHARGE_DSG  (-30000)

+

+typedef enum _MEAS_RTN_CODE {

+  MEAS_RTN_PASS = 0,

+  MEAS_RTN_BATTERY_REMOVED,

+  MEAS_RTN_ADC_ABNORMAL,

+  MEAS_RTN_NTC_SHORT,

+} MEAS_RTN_CODE;

+

+typedef struct MeasDataST {

+

+  /// [AT-PM] : System data ; 04/08/2013

+  SystemDataType *sysData;

+  

+  /// [AT-PM] : OTP data ; 01/23/2013

+  OtpDataType *otp;

+  

+  /// [AT-PM] : Physical value ; 01/23/2013

+  _meas_u16_ bat1Voltage;

+  _meas_s16_ curr;

+  _meas_s16_ intTemperature;

+  _meas_s16_ extTemperature;

+  _meas_s16_ deltaCap;

+  _meas_s16_ stepCap;

+  _meas_u32_ deltaTime;

+

+

+  /// [AT-PM] : ADC code ; 01/23/2013

+  _meas_u16_ codeBat1;

+  _meas_s16_ codeCurrent;

+  _meas_u16_ codeIntTemperature;

+  _meas_u16_ codeExtTemperature;

+  _meas_s32_ codeCharge;

+

+  /// [AT-PM] : Coulomb counter offset ; 01/23/2013

+  _meas_s16_ ccOffset;

+  

+  /// [AT-PM] : ADC1 characteristic ; 01/23/2013

+  _meas_u16_ adc1ConvertTime;

+  _meas_s32_ adc1Gain;

+  _meas_s32_ adc1GainSlope;

+  _meas_s32_ adc1GainFactorB;

+  _meas_s32_ adc1Offset;

+  _meas_s32_ adc1OffsetSlope;

+  _meas_s32_ adc1OffsetFactorO;

+

+  /// [AT-PM] : ADC2 characteristic ; 01/23/2013

+  _meas_s32_ adc2Gain;

+  _meas_s32_ adc2GainSlope;

+  _meas_s32_ adc2GainFactorB;

+  _meas_s32_ adc2Offset;

+  _meas_s32_ adc2OffsetSlope;

+  _meas_s32_ adc2OffsetFactorO;

+

+  /// [AT-PM] : Previous information ; 01/25/2013

+  _meas_u16_ lastCounter;

+  _meas_u32_ lastTimeTick;

+  _meas_s16_ lastDeltaCap;

+  

+  /// [AT-PM] : In suspend mode operation ; 06/11/2013

+  _meas_bool_ inSuspendMode;

+#if defined(uG31xx_OS_ANDROID)

+} __attribute__ ((aligned(4))) MeasDataType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)	      

+} MeasDataType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/**

+ * @brief UpiResetCoulombCounter

+ *

+ *  Reset coulomb counter

+ *

+ * @para  data  address of MeasDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiResetCoulombCounter(MeasDataType *data);

+

+/**

+ * @brief UpiMeasurement

+ *

+ *  Measurement routine

+ *

+ * @para  data  address of MeasDataType

+ * @return  MEAS_RTN_CODE

+ */

+extern MEAS_RTN_CODE UpiMeasurement(MeasDataType *data);

+

+/**

+ * @brief UpiMeasAlarmThreshold

+ *

+ *  Get alarm threshold

+ *

+ * @para  data  address of MeasDataType

+ * @return  MEAS_RTN_CODE

+ */

+extern MEAS_RTN_CODE UpiMeasAlarmThreshold(MeasDataType *data);

+

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Otp.c b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Otp.c
new file mode 100755
index 0000000..5ed47de
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Otp.c
@@ -0,0 +1,917 @@
+/**

+ * @filename  uG31xx_API_Otp.cpp

+ *

+ *  Convert OTP registers into readable value

+ *

+ * @author  AllenTeng <allen_teng@upi-semi.com>

+ */

+

+#include "stdafx.h"     //windows need this??

+#include "uG31xx_API.h"

+

+/// =============================================

+/// [AT-PM] : OTP register definition

+/// =============================================

+

+#define OTP1_OFFSET_E0                (0)

+  #define INDEX_ADC1_200_25_0         (1<<0)

+  #define INDEX_ADC1_200_25_1         (1<<1)

+  #define INDEX_ADC1_200_25_2         (1<<2)

+  #define INDEX_ADC1_200_25_3         (1<<3)

+  #define DELTA_VREF_0                (1<<4)

+  #define DELTA_VREF_1                (1<<5)

+  #define DELTA_VREF_2                (1<<6)

+  #define DELTA_VREF_3                (1<<7)

+  

+#define OTP1_OFFSET_E1                (OTP1_OFFSET_E0 + 1)

+  #define INDEX_ADC1_100_25_0         (1<<0)

+  #define INDEX_ADC1_100_25_1         (1<<1)

+  #define INDEX_ADC1_100_25_2         (1<<2)

+  #define INDEX_ADC1_100_25_3         (1<<3)

+  #define FT_IT_3                     (1<<4)

+  #define FT_IT_4                     (1<<5)

+  #define FT_IT_5                     (1<<6)

+  #define FT_IT_6                     (1<<7)

+

+#define OTP1_OFFSET_E2                (OTP1_OFFSET_E1 + 1)

+  #define INDEX_ADC2_200_25_0         (1<<0)

+  #define INDEX_ADC2_200_25_1         (1<<1)

+  #define INDEX_ADC2_200_25_2         (1<<2)

+  #define INDEX_ADC2_200_25_3         (1<<3)

+  #define FT_IT_7                     (1<<4)

+  #define FT_IT_8                     (1<<5)

+  #define FT_IT_9                     (1<<6)

+  #define FT_IT_10                    (1<<7)

+

+#define OTP1_OFFSET_E3                (OTP1_OFFSET_E2 + 1)

+  #define INDEX_ADC2_100_25_0         (1<<0)

+  #define INDEX_ADC2_100_25_1         (1<<1)

+  #define INDEX_ADC2_100_25_2         (1<<2)

+  #define INDEX_ADC2_100_25_3         (1<<3)

+  #define FT_IT_11                    (1<<4)

+  #define FT_IT_12                    (1<<5)

+  #define FT_IT_13                    (1<<6)

+  #define FT_IT_14                    (1<<7)

+

+#define OTP2_OFFSET_F0                (0)

+  #define OTP2_OFFSET_F0_RSVD_0       (1<<0)

+  #define OTP2_OFFSET_F0_RSVD_1       (1<<1)

+  #define OTP2_OFFSET_F0_RSVD_2       (1<<2)

+  #define PRODUCT_TYPE_0              (1<<3)

+  #define PRODUCT_TYPE_1              (1<<4)

+  #define DELTA_ET_0                  (1<<5)

+  #define INDEX_ADC2_100_25_4         (1<<6)

+  #define DELTA_ET_1                  (1<<7)

+

+#define OTP2_OFFSET_F1                (OTP2_OFFSET_F0 + 1)

+  #define OTP2_OFFSET_F1_RSVD_0       (1<<0)

+  #define OTP2_OFFSET_F1_RSVD_1       (1<<1)

+  #define OTP2_OFFSET_F1_RSVD_2       (1<<2)

+  #define OTP2_OFFSET_F1_RSVD_3       (1<<3)

+  #define OTP2_OFFSET_F1_RSVD_4       (1<<4)

+  #define OTP2_OFFSET_F1_RSVD_5       (1<<5)

+  #define OTP2_OFFSET_F1_RSVD_6       (1<<6)

+  #define OTP2_OFFSET_F1_RSVD_7       (1<<7)

+

+#define OTP2_OFFSET_F2                (OTP2_OFFSET_F1 + 1)

+  #define OTP2_OFFSET_F2_RSVD_0       (1<<0)

+  #define OTP2_OFFSET_F2_RSVD_1       (1<<1)

+  #define OTP2_OFFSET_F2_RSVD_2       (1<<2)

+  #define OTP_CELL_EN_0               (1<<3)

+  #define OTP_CELL_EN_1               (1<<4)

+  #define OTP_CELL_EN_2               (1<<5)

+  #define OTP_CELL_EN_3               (1<<6)

+  #define OTP_CELL_EN_4               (1<<7)

+

+#define OTP2_OFFSET_F3                (OTP2_OFFSET_F2 + 1)

+  #define OTP2_OFFSET_F3_RSVD_0       (1<<0)

+  #define OTP2_OFFSET_F3_RSVD_1       (1<<1)

+  #define OTP2_OFFSET_F3_RSVD_2       (1<<2)

+  #define OTP2_OFFSET_F3_RSVD_3       (1<<3)

+  #define OTP2_OFFSET_F3_RSVD_4       (1<<4)

+  #define OTP2_OFFSET_F3_RSVD_5       (1<<5)

+  #define OTP2_OFFSET_F3_RSVD_6       (1<<6)

+  #define OTP2_OFFSET_F3_RSVD_7       (1<<7)

+

+#define OTP2_OFFSET_F4                (OTP2_OFFSET_F3 + 1)

+  #define ADC1_DELTA_CODE_25_200MV_8  (1<<0)

+  #define ADC1_DELTA_CODE_25_200MV_9  (1<<1)

+  #define DEV_ADDR_0                  (1<<2)

+  #define DEV_ADDR_1                  (1<<3)

+  #define DEV_ADDR_2                  (1<<4)

+  #define DEV_ADDR_7                  (1<<5)

+  #define DEV_ADDR_8                  (1<<6)

+  #define DEV_ADDR_9                  (1<<7)

+  

+#define OTP2_OFFSET_F5                (OTP2_OFFSET_F4 + 1)

+  #define OTP2_OFFSET_F5_RSVD_0       (1<<0)

+  #define OTP2_OFFSET_F5_RSVD_1       (1<<1)

+  #define BGR_TUNE_0                  (1<<2)

+  #define BGR_TUNE_1                  (1<<3)

+  #define BGR_TUNE_2                  (1<<4)

+  #define BGR_TUNE_3                  (1<<5)

+  #define BGR_TUNE_4                  (1<<6)

+  #define BGR_TUNE_5                  (1<<7)

+

+#define OTP2_OFFSET_F6                (OTP2_OFFSET_F5 + 1)

+  #define OSC_DELTA_CODE_25_0         (1<<0)

+  #define OSC_DELTA_CODE_25_1         (1<<1)

+  #define OSC_DELTA_CODE_25_2         (1<<2)

+  #define OSC_DELTA_CODE_25_3         (1<<3)

+  #define OSC_DELTA_CODE_25_4         (1<<4)

+  #define OSC_DELTA_CODE_25_5         (1<<5)

+  #define OSC_DELTA_CODE_25_6         (1<<6)

+  #define OSC_DELTA_CODE_25_7         (1<<7)

+

+#define OTP2_OFFSET_F7                (OTP2_OFFSET_F6 + 1)

+  #define OSC_DELTA_CODE_80_0         (1<<0)

+  #define OSC_DELTA_CODE_80_1         (1<<1)

+  #define OSC_DELTA_CODE_80_2         (1<<2)

+  #define OSC_DELTA_CODE_80_3         (1<<3)

+  #define OSC_DELTA_CODE_80_4         (1<<4)

+  #define OSC_DELTA_CODE_80_5         (1<<5)

+  #define OSC_DELTA_CODE_80_6         (1<<6)

+  #define OSC_DELTA_CODE_80_7         (1<<7)

+

+#define OTP2_OFFSET_F8                (OTP2_OFFSET_F7 + 1)

+  #define ADC1_DELTA_CODE_25_200MV_0  (1<<0)

+  #define ADC1_DELTA_CODE_25_200MV_1  (1<<1)

+  #define ADC1_DELTA_CODE_25_200MV_2  (1<<2)

+  #define ADC1_DELTA_CODE_25_200MV_3  (1<<3)

+  #define ADC1_DELTA_CODE_25_200MV_4  (1<<4)

+  #define ADC1_DELTA_CODE_25_200MV_5  (1<<5)

+  #define ADC1_DELTA_CODE_25_200MV_6  (1<<6)

+  #define ADC1_DELTA_CODE_25_200MV_7  (1<<7)

+

+#define OTP2_OFFSET_F9                (OTP2_OFFSET_F8 + 1)

+  #define OTP2_OFFSET_F9_RSVD_0       (1<<0)

+  #define OTP2_OFFSET_F9_RSVD_1       (1<<1)

+  #define OTP2_OFFSET_F9_RSVD_2       (1<<2)

+  #define OTP2_OFFSET_F9_RSVD_3       (1<<3)

+  #define OTP2_OFFSET_F9_RSVD_4       (1<<4)

+  #define OTP2_OFFSET_F9_RSVD_5       (1<<5)

+  #define OTP2_OFFSET_F9_RSVD_6       (1<<6)

+  #define OTP2_OFFSET_F9_RSVD_7       (1<<7)

+

+#define OTP2_OFFSET_FA                (OTP2_OFFSET_F9 + 1)

+  #define ADC1_DELTA_CODE_25_100MV_0  (1<<0)

+  #define ADC1_DELTA_CODE_25_100MV_1  (1<<1)

+  #define ADC1_DELTA_CODE_25_100MV_2  (1<<2)

+  #define ADC1_DELTA_CODE_25_100MV_3  (1<<3)

+  #define ADC1_DELTA_CODE_25_100MV_4  (1<<4)

+  #define ADC1_DELTA_CODE_25_100MV_5  (1<<5)

+  #define ADC1_DELTA_CODE_25_100MV_6  (1<<6)

+  #define ADC1_DELTA_CODE_25_100MV_7  (1<<7)

+

+#define OTP2_OFFSET_FB                (OTP2_OFFSET_FA + 1)

+  #define OTP2_OFFSET_FB_RSVD_0       (1<<0)

+  #define OTP2_OFFSET_FB_RSVD_1       (1<<1)

+  #define OTP2_OFFSET_FB_RSVD_2       (1<<2)

+  #define OTP2_OFFSET_FB_RSVD_3       (1<<3)

+  #define OTP2_OFFSET_FB_RSVD_4       (1<<4)

+  #define OTP2_OFFSET_FB_RSVD_5       (1<<5)

+  #define OTP2_OFFSET_FB_RSVD_6       (1<<6)

+  #define OTP2_OFFSET_FB_RSVD_7       (1<<7)

+

+#define OTP2_OFFSET_FC                (OTP2_OFFSET_FB + 1)

+  #define ADC1_DELTA_CODE_25_100MV_8  (1<<0)

+  #define ADC2_DELTA_CODE_25_100MV_0  (1<<1)

+  #define ADC2_DELTA_CODE_25_100MV_1  (1<<2)

+  #define ADC2_DELTA_CODE_25_100MV_2  (1<<3)

+  #define ADC2_DELTA_CODE_25_100MV_3  (1<<4)

+  #define ADC2_DELTA_CODE_25_100MV_4  (1<<5)

+  #define ADC2_DELTA_CODE_25_100MV_5  (1<<6)

+  #define ADC2_DELTA_CODE_25_100MV_6  (1<<7)

+

+#define OTP2_OFFSET_FD                (OTP2_OFFSET_FC + 1)

+  #define OTP2_OFFSET_FD_RSVD_0       (1<<0)

+  #define OTP2_OFFSET_FD_RSVD_1       (1<<1)

+  #define OTP2_OFFSET_FD_RSVD_2       (1<<2)

+  #define OTP2_OFFSET_FD_RSVD_3       (1<<3)

+  #define OTP2_OFFSET_FD_RSVD_4       (1<<4)

+  #define OTP2_OFFSET_FD_RSVD_5       (1<<5)

+  #define OTP2_OFFSET_FD_RSVD_6       (1<<6)

+  #define OTP2_OFFSET_FD_RSVD_7       (1<<7)

+

+#define OTP2_OFFSET_FE                (OTP2_OFFSET_FD + 1)

+  #define ADC2_DELTA_CODE_25_200MV_0  (1<<0)

+  #define ADC2_DELTA_CODE_25_200MV_1  (1<<1)

+  #define ADC2_DELTA_CODE_25_200MV_2  (1<<2)

+  #define ADC2_DELTA_CODE_25_200MV_3  (1<<3)

+  #define ADC2_DELTA_CODE_25_200MV_4  (1<<4)

+  #define ADC2_DELTA_CODE_25_200MV_5  (1<<5)

+  #define ADC2_DELTA_CODE_25_200MV_6  (1<<6)

+  #define ADC2_DELTA_CODE_25_200MV_7  (1<<7)

+

+#define OTP2_OFFSET_FF                (OTP2_OFFSET_FE + 1)

+  #define OTP2_OFFSET_FF_RSVD_0       (1<<0)

+  #define OTP2_OFFSET_FF_RSVD_1       (1<<1)

+  #define OTP2_OFFSET_FF_RSVD_2       (1<<2)

+  #define OTP2_OFFSET_FF_RSVD_3       (1<<3)

+  #define OTP2_OFFSET_FF_RSVD_4       (1<<4)

+  #define OTP2_OFFSET_FF_RSVD_5       (1<<5)

+  #define OTP2_OFFSET_FF_RSVD_6       (1<<6)

+  #define OTP2_OFFSET_FF_RSVD_7       (1<<7)

+

+

+#define OTP3_OFFSET_70                (0)

+  #define DELTA_VREF_4                (1<<0)

+  #define DELTA_ET_2                  (1<<1)

+  #define DELTA_ET_3                  (1<<2)

+  #define AVE_IT_25_3                 (1<<3)

+  #define AVE_IT_25_4                 (1<<4)

+  #define AVE_IT_25_5                 (1<<5)

+  #define AVE_IT_25_6                 (1<<6)

+  #define AVE_IT_25_7                 (1<<7)

+

+#define OTP3_OFFSET_71                (OTP3_OFFSET_70 + 1)

+  #define AVE_IT_25_8                 (1<<0)

+  #define AVE_IT_25_9                 (1<<1)

+  #define AVE_IT_25_10                (1<<2)

+  #define AVE_IT_25_11                (1<<3)

+  #define AVE_IT_25_12                (1<<4)

+  #define AVE_IT_25_13                (1<<5)

+  #define AVE_IT_25_14                (1<<6)

+  #define AVE_IT_25_15                (1<<7)

+

+#define OTP3_OFFSET_72                (OTP3_OFFSET_71 + 1)

+  #define INDEX_ADC2_200_25_4         (1<<0)

+  #define INDEX_ADC1_100_25_4         (1<<1)

+  #define INDEX_ADC1_200_25_4         (1<<2)

+  #define AVE_IT_80_3                 (1<<3)

+  #define AVE_IT_80_4                 (1<<4)

+  #define AVE_IT_80_5                 (1<<5)

+  #define AVE_IT_80_6                 (1<<6)

+  #define AVE_IT_80_7                 (1<<7)

+

+#define OTP3_OFFSET_73                (OTP3_OFFSET_72 + 1)

+  #define AVE_IT_80_8                 (1<<0)

+  #define AVE_IT_80_9                 (1<<1)

+  #define AVE_IT_80_10                (1<<2)

+  #define AVE_IT_80_11                (1<<3)

+  #define AVE_IT_80_12                (1<<4)

+  #define AVE_IT_80_13                (1<<5)

+  #define AVE_IT_80_14                (1<<6)

+  #define AVE_IT_80_15                (1<<7)

+

+/// =============================================

+/// [AT-PM] : OTP register conversion routine

+/// =============================================

+

+/**

+ * @brief ConvOtp1E0

+ *

+ *  Convert OTP1 0xE0

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp1E0(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp1[OTP1_OFFSET_E0];

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[ConvOtp1E0] Initial value of indexAdc1V200T25 = %d\n");

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  obj->indexAdc1V200T25 = obj->indexAdc1V200T25 + (value & (INDEX_ADC1_200_25_0 | 

+                                                            INDEX_ADC1_200_25_1 | 

+                                                            INDEX_ADC1_200_25_2 | 

+                                                            INDEX_ADC1_200_25_3));

+

+  obj->deltaVref = obj->deltaVref + ((value & (DELTA_VREF_0| DELTA_VREF_1 | DELTA_VREF_2 | DELTA_VREF_3)) >> 4);

+}

+

+/**

+ * @brief ConvOtp1E1

+ *

+ *  Convert OTP1 0xE1

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp1E1(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp1[OTP1_OFFSET_E1];

+

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[ConvOtp1E1] Initial value of indexAdc1V100T25 = %d\n", obj->indexAdc1V100T25);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  obj->indexAdc1V100T25 = obj->indexAdc1V100T25 + (value & (INDEX_ADC1_100_25_0 | 

+                                                            INDEX_ADC1_100_25_1 | 

+                                                            INDEX_ADC1_100_25_2 | 

+                                                            INDEX_ADC1_100_25_3));

+

+  obj->ftIT = obj->ftIT + ((value & (FT_IT_3 | FT_IT_4 | FT_IT_5 | FT_IT_6)) >> 1);

+}

+

+/**

+ * @brief ConvOtp1E2

+ *

+ *  Convert OTP1 0xE2

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp1E2(OtpDataType *obj)

+{

+  _otp_u8_ value;

+  _otp_u16_ tmp;

+

+  value = obj->otp1[OTP1_OFFSET_E2];

+

+	#ifdef	UiPI_UBOOT_DEBUG_MSG

+		printf("[ConvOtp1E2] Initial value of indexAdc2V200T25 = %d\n", obj->indexAdc2V200T25);

+	#endif	///< end of UiPI_UBOOT_DEBUG_MSG

+  obj->indexAdc2V200T25 = obj->indexAdc2V200T25 + (value & (INDEX_ADC2_200_25_0 | 

+                                                            INDEX_ADC2_200_25_1 | 

+                                                            INDEX_ADC2_200_25_2 | 

+                                                            INDEX_ADC2_200_25_3));

+

+  tmp = (value & (FT_IT_7 | FT_IT_8 | FT_IT_9 | FT_IT_10));

+  obj->ftIT = obj->ftIT + (tmp << 3);

+}

+

+/**

+ * @brief ConvOtp1E3

+ *

+ *  Convert OTP1 0xE3

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp1E3(OtpDataType *obj)

+{

+  _otp_u8_ value;

+  _otp_u16_ tmp;

+

+  value = obj->otp1[OTP1_OFFSET_E3];

+

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[ConvOtp1E3] Initial value of indexAdc2V100T25 = %d\n", obj->indexAdc2V100T25);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  obj->indexAdc2V100T25 = obj->indexAdc2V100T25 + (value & (INDEX_ADC2_100_25_0 | 

+                                                            INDEX_ADC2_100_25_1 | 

+                                                            INDEX_ADC2_100_25_2 | 

+                                                            INDEX_ADC2_100_25_3));

+

+  tmp = (value & (FT_IT_11 | FT_IT_12 | FT_IT_13 | FT_IT_14));

+  obj->ftIT = obj->ftIT + (tmp << 7);

+}

+

+/**

+ * @brief ConvOtp2F0

+ *

+ *  Convert OTP2 0xF0

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F0(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp2[OTP2_OFFSET_F0];

+

+  obj->productType = (value & (PRODUCT_TYPE_0 | PRODUCT_TYPE_1)) >> 3;

+

+  obj->deltaET = obj->deltaET + ((value & DELTA_ET_0) >> 5) + ((value & DELTA_ET_1) >> 6);

+

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvOtp2F0] Initial value of indexAdc2V100T25 = %d\n", obj->indexAdc2V100T25);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+  obj->indexAdc2V100T25 = obj->indexAdc2V100T25 + ((value & INDEX_ADC2_100_25_4) >> 2);

+}

+

+/**

+ * @brief ConvOtp2F1

+ *

+ *  Convert OTP2 0xF1

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F1(OtpDataType *obj)

+{

+}

+

+/**

+ * @brief ConvOtp2F2

+ *

+ *  Convert OTP2 0xF2

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F2(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp2[OTP2_OFFSET_F2];

+

+  obj->otpCellEN = obj->otpCellEN + ((value & (OTP_CELL_EN_0 | 

+                                               OTP_CELL_EN_1 | 

+                                               OTP_CELL_EN_2 | 

+                                               OTP_CELL_EN_3 | 

+                                               OTP_CELL_EN_4)) >> 3);

+}

+

+/**

+ * @brief ConvOtp2F3

+ *

+ *  Convert OTP2 0xF3

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F3(OtpDataType *obj)

+{

+}

+

+/**

+ * @brief ConvOtp2F4

+ *

+ *  Convert OTP2 0xF4

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F4(OtpDataType *obj)

+{

+  _otp_u8_ value;

+  _otp_u16_ tmp;

+

+  value = obj->otp2[OTP2_OFFSET_F4];

+

+  tmp = value & (ADC1_DELTA_CODE_25_200MV_8| ADC1_DELTA_CODE_25_200MV_9);

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[ConvOtp2F4] Initial value of adc1DeltaCodeT25V200 = %d\n", obj->adc1DeltaCodeT25V200);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  obj->adc1DeltaCodeT25V200 = obj->adc1DeltaCodeT25V200 + (tmp << 8);

+

+  tmp = value & (DEV_ADDR_7 | DEV_ADDR_8 | DEV_ADDR_9);

+  obj->devAddr = (tmp << 2) + ((value & (DEV_ADDR_0 | DEV_ADDR_1 | DEV_ADDR_2)) >> 2);

+}

+

+/**

+ * @brief ConvOtp2F5

+ *

+ *  Convert OTP2 0xF5

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F5(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp2[OTP2_OFFSET_F5];

+

+  obj->bgrTune = obj->bgrTune + ((value & (BGR_TUNE_0 | 

+                                           BGR_TUNE_1 | 

+                                           BGR_TUNE_2 | 

+                                           BGR_TUNE_3 | 

+                                           BGR_TUNE_4 | 

+                                           BGR_TUNE_5)) >> 2);

+}

+

+/**

+ * @brief ConvOtp2F6

+ *

+ *  Convert OTP2 0xF6

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F6(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp2[OTP2_OFFSET_F6];

+

+  obj->oscDeltaCode25 = obj->oscDeltaCode25 + (value & (OSC_DELTA_CODE_25_0 | 

+                                                        OSC_DELTA_CODE_25_1 |

+                                                        OSC_DELTA_CODE_25_2 |

+                                                        OSC_DELTA_CODE_25_3 |

+                                                        OSC_DELTA_CODE_25_4 |

+                                                        OSC_DELTA_CODE_25_5 |

+                                                        OSC_DELTA_CODE_25_6 |

+                                                        OSC_DELTA_CODE_25_7));

+}

+

+/**

+ * @brief ConvOtp2F7

+ *

+ *  Convert OTP2 0xF7

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F7(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp2[OTP2_OFFSET_F7];

+

+  obj->oscDeltaCode80 = obj->oscDeltaCode80 + (value & (OSC_DELTA_CODE_80_0 | 

+                                                        OSC_DELTA_CODE_80_1 |

+                                                        OSC_DELTA_CODE_80_2 |

+                                                        OSC_DELTA_CODE_80_3 |

+                                                        OSC_DELTA_CODE_80_4 |

+                                                        OSC_DELTA_CODE_80_5 |

+                                                        OSC_DELTA_CODE_80_6 |

+                                                        OSC_DELTA_CODE_80_7));

+}

+

+/**

+ * @brief ConvOtp2F8

+ *

+ *  Convert OTP2 0xF8

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F8(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp2[OTP2_OFFSET_F8];

+

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvOtp2F8] Initial value of adc1DeltaCodeT25V200 = %d\n", obj->adc1DeltaCodeT25V200);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+  obj->adc1DeltaCodeT25V200 = obj->adc1DeltaCodeT25V200 + (value & (ADC1_DELTA_CODE_25_200MV_0 |

+                                                                    ADC1_DELTA_CODE_25_200MV_1 |

+                                                                    ADC1_DELTA_CODE_25_200MV_2 |

+                                                                    ADC1_DELTA_CODE_25_200MV_3 |

+                                                                    ADC1_DELTA_CODE_25_200MV_4 |

+                                                                    ADC1_DELTA_CODE_25_200MV_5 |

+                                                                    ADC1_DELTA_CODE_25_200MV_6 |

+                                                                    ADC1_DELTA_CODE_25_200MV_7));

+}

+

+/**

+ * @brief ConvOtp2F9

+ *

+ *  Convert OTP2 0xF9

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2F9(OtpDataType *obj)

+{

+}

+

+/**

+ * @brief ConvOtp2FA

+ *

+ *  Convert OTP2 0xFA

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2FA(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp2[OTP2_OFFSET_FA];

+

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[ConvOtp2FA] Initial value of adc1DeltaCodeT25V100 = %d\n", obj->adc1DeltaCodeT25V100);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  obj->adc1DeltaCodeT25V100 = obj->adc1DeltaCodeT25V100 + (value & (ADC1_DELTA_CODE_25_100MV_0 |

+                                                                    ADC1_DELTA_CODE_25_100MV_1 |

+                                                                    ADC1_DELTA_CODE_25_100MV_2 |

+                                                                    ADC1_DELTA_CODE_25_100MV_3 |

+                                                                    ADC1_DELTA_CODE_25_100MV_4 |

+                                                                    ADC1_DELTA_CODE_25_100MV_5 |

+                                                                    ADC1_DELTA_CODE_25_100MV_6 |

+                                                                    ADC1_DELTA_CODE_25_100MV_7));

+}

+

+/**

+ * @brief ConvOtp2FB

+ *

+ *  Convert OTP2 0xFB

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2FB(OtpDataType *obj)

+{

+}

+

+/**

+ * @brief ConvOtp2FC

+ *

+ *  Convert OTP2 0xFC

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2FC(OtpDataType *obj)

+{

+  _otp_u8_ value;

+  _otp_u16_ tmp;

+

+  value = obj->otp2[OTP2_OFFSET_FC];

+

+  tmp = value & ADC1_DELTA_CODE_25_100MV_8;

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[ConvOtp2FC] Initial value of = %d\n", obj->adc1DeltaCodeT25V100);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  obj->adc1DeltaCodeT25V100 = obj->adc1DeltaCodeT25V100 + (tmp << 8);

+  

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvOtp2FC] Initial value of = %d\n", obj->adc2DeltaCodeT25V100);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+  obj->adc2DeltaCodeT25V100 = obj->adc2DeltaCodeT25V100 + ((value & (ADC2_DELTA_CODE_25_100MV_0 |

+                                                                     ADC2_DELTA_CODE_25_100MV_1 |

+                                                                     ADC2_DELTA_CODE_25_100MV_2 |

+                                                                     ADC2_DELTA_CODE_25_100MV_3 |

+                                                                     ADC2_DELTA_CODE_25_100MV_4 |

+                                                                     ADC2_DELTA_CODE_25_100MV_5 |

+                                                                     ADC2_DELTA_CODE_25_100MV_6)) >> 1);

+}

+

+/**

+ * @brief ConvOtp2FD

+ *

+ *  Convert OTP2 0xFD

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2FD(OtpDataType *obj)

+{

+}

+

+/**

+ * @brief ConvOtp2FE

+ *

+ *  Convert OTP2 0xFE

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2FE(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp2[OTP2_OFFSET_FE];

+

+	#ifdef	UPI_UBOOT_DEBUG_MSG

+		printf("[ConvOtp2FE] Initial value of adc2DeltaCodeT25V200 = %d\n", obj->adc2DeltaCodeT25V200);

+	#endif	///< end of UPI_UBOOT_DEBUG_MSG

+  obj->adc2DeltaCodeT25V200 = obj->adc2DeltaCodeT25V200 + (value & (ADC2_DELTA_CODE_25_200MV_0 |

+                                                                    ADC2_DELTA_CODE_25_200MV_1 |

+                                                                    ADC2_DELTA_CODE_25_200MV_2 |

+                                                                    ADC2_DELTA_CODE_25_200MV_3 |

+                                                                    ADC2_DELTA_CODE_25_200MV_4 |

+                                                                    ADC2_DELTA_CODE_25_200MV_5 |

+                                                                    ADC2_DELTA_CODE_25_200MV_6 |

+                                                                    ADC2_DELTA_CODE_25_200MV_7));

+}

+

+/**

+ * @brief ConvOtp2FF

+ *

+ *  Convert OTP2 0xFF

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp2FF(OtpDataType *obj)

+{

+}

+

+/**

+ * @brief ConvOtp370

+ *

+ *  Convert OTP3 0x70

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp370(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp3[OTP3_OFFSET_70];

+

+  obj->deltaVref = obj->deltaVref + ((value & DELTA_VREF_4) << 4);

+

+  obj->deltaET = obj->deltaET + ((value & (DELTA_ET_2 | DELTA_ET_3)) << 1);

+

+  obj->aveIT25 = obj->aveIT25 + (value & (AVE_IT_25_3 | AVE_IT_25_4 | AVE_IT_25_5 | AVE_IT_25_6 | AVE_IT_25_7));

+}

+

+/**

+ * @brief ConvOtp371

+ *

+ *  Convert OTP3 0x71

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp371(OtpDataType *obj)

+{

+  _otp_u8_ value;

+  _otp_u16_ tmp;

+

+  value = obj->otp3[OTP3_OFFSET_71];

+

+  tmp = value & (AVE_IT_25_8 | 

+                 AVE_IT_25_9 | 

+                 AVE_IT_25_10 | 

+                 AVE_IT_25_11 | 

+                 AVE_IT_25_12 | 

+                 AVE_IT_25_13 | 

+                 AVE_IT_25_14 | 

+                 AVE_IT_25_15);

+  obj->aveIT25 = obj->aveIT25 + (tmp << 8);

+}

+

+/**

+ * @brief ConvOtp372

+ *

+ *  Convert OTP3 0x72

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp372(OtpDataType *obj)

+{

+  _otp_u8_ value;

+

+  value = obj->otp3[OTP3_OFFSET_72];

+

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvOtp372] Initial value of indexAdc2V200T25 = %d\n", obj->indexAdc2V200T25);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+  obj->indexAdc2V200T25 = obj->indexAdc2V200T25 + ((value & INDEX_ADC2_200_25_4) << 4);

+

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvOtp372] Initial value of indexAdc1V100T25 = %d\n", obj->indexAdc1V100T25);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+  obj->indexAdc1V100T25 = obj->indexAdc1V100T25 + ((value & INDEX_ADC1_100_25_4) << 3);

+

+        #ifdef  UPI_UBOOT_DEBUG_MSG

+                printf("[ConvOtp372] Initial value of indexAdc1V200T25 = %d\n", obj->indexAdc1V200T25);

+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG

+  obj->indexAdc1V200T25 = obj->indexAdc1V200T25 + ((value & INDEX_ADC1_200_25_4) << 2);

+

+  obj->aveIT80 = obj->aveIT80 + (value & (AVE_IT_80_3 | AVE_IT_80_4 | AVE_IT_80_5 | AVE_IT_80_6 | AVE_IT_80_7));

+}

+

+/**

+ * @brief ConvOtp373

+ *

+ *  Convert OTP3 0x73

+ *

+ * @para  obj address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void ConvOtp373(OtpDataType *obj)

+{

+  _otp_u8_ value;

+  _otp_u16_ tmp;

+

+  value = obj->otp3[OTP3_OFFSET_73];

+

+  tmp = value & (AVE_IT_80_8 | 

+                 AVE_IT_80_9 | 

+                 AVE_IT_80_10 | 

+                 AVE_IT_80_11 | 

+                 AVE_IT_80_12 | 

+                 AVE_IT_80_13 | 

+                 AVE_IT_80_14 | 

+                 AVE_IT_80_15);

+  obj->aveIT80 = obj->aveIT80 + (tmp << 8);

+}

+

+#define CONV_FUNC_PTR_NULL  (0)

+

+typedef void (*ConvFuncPtr)(OtpDataType *obj);

+

+static ConvFuncPtr ConvFuncTable[] = {

+  ConvOtp1E0,

+  ConvOtp1E1,

+  ConvOtp1E2,

+  ConvOtp1E3,

+

+  ConvOtp2F0,

+  ConvOtp2F1,

+  ConvOtp2F2,

+  ConvOtp2F3,

+  ConvOtp2F4,

+  ConvOtp2F5,

+  ConvOtp2F6,

+  ConvOtp2F7,

+  ConvOtp2F8,

+  ConvOtp2F9,

+  ConvOtp2FA,

+  ConvOtp2FB,

+  ConvOtp2FC,

+  ConvOtp2FD,

+  ConvOtp2FE,

+  ConvOtp2FF,

+

+  ConvOtp370,

+  ConvOtp371,

+  ConvOtp372,

+  ConvOtp373,

+  

+  CONV_FUNC_PTR_NULL,

+};

+

+/**

+ * @brief CheckOtpISEmpty

+ *

+ *  Check OTP is empty or not

+ *

+ * @para  data  address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void CheckOtpISEmpty(OtpDataType *data)

+{

+  _otp_u8_ idx;

+

+  /// [AT-PM] : Check OTP1 ; 01/25/2013

+  idx = 0;

+  while(idx < OTP1_SIZE)

+  {

+    if(data->otp1[idx] != 0)

+    {

+      data->empty = OTP_IS_NOT_EMPTY;

+      return;

+    }

+  }

+

+  /// [AT-PM] : Check OTP2 ; 01/25/2013

+  idx = 0;

+  while(idx < OTP2_SIZE)

+  {

+    if(data->otp2[idx] != 0)

+    {

+      data->empty = OTP_IS_NOT_EMPTY;

+      return;

+    }

+  }

+

+  /// [AT-PM] : Check OTP3 ; 01/25/2013

+  idx = 0;

+  while(idx < OTP3_SIZE)

+  {

+    if(data->otp3[idx] != 0)

+    {

+      data->empty = OTP_IS_NOT_EMPTY;

+      return;

+    }

+  }

+

+  /// [AT-PM] : Set OTP is empty ; 01/25/2013

+  data->empty = OTP_IS_EMPTY;

+}

+

+/// =============================================

+/// [AT-PM] : Extern function region

+/// =============================================

+

+/**

+ * @brief UpiConvertOtp

+ *

+ *  Convert OTP register value to readable value

+ *

+ * @para  data  address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+void UpiConvertOtp(OtpDataType *data)

+{

+  _otp_u8_ idx;

+

+  UG31_LOGI("[%s]: OTP version : %d.%02x\n", __func__, UG31XX_OTP_VERSION_MAIN, UG31XX_OTP_VERSION_SUB);

+

+  /// [AT-PM] : Set version ; 01/25/2013

+  data->versionMain = UG31XX_OTP_VERSION_MAIN;

+  data->versionSub = UG31XX_OTP_VERSION_SUB;

+  

+  /// [AT-PM] : Conversion ; 01/23/2013

+  idx = 0;

+  while(1)

+  {

+    (*ConvFuncTable[idx])(data);

+    

+    idx = idx + 1;

+    if(ConvFuncTable[idx] == CONV_FUNC_PTR_NULL)

+    {

+      break;

+    }

+  }

+

+  /// [AT-PM] : Check OTP is empty ; 01/25/2013

+  CheckOtpISEmpty(data);

+}

+

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Otp.h b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Otp.h
new file mode 100755
index 0000000..b80361f
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_Otp.h
@@ -0,0 +1,84 @@
+/**

+ * @filename  uG31xx_API_Otp.h

+ *

+ *  Header of OTP conversion module

+ *

+ * @author  AllenTeng <allen_teng@upi-semi.com>

+ */

+

+/// [AT-PM] : Product Type definition in OTP ; 01/23/2013

+enum UG31XX_PRODUCT_TYPE {

+  UG31XX_PRODUCT_TYPE_0 = 0,

+  UG31XX_PRODUCT_TYPE_1 = 1,

+  UG31XX_PRODUCT_TYPE_2 = 2,

+  UG31XX_PRODUCT_TYPE_3 = 3,

+};

+

+#define UG31XX_OTP_VERSION_MAIN (0x2013)

+#define UG31XX_OTP_VERSION_SUB  (0x0110)

+

+#define OTP_IS_EMPTY      (1)

+#define OTP_IS_NOT_EMPTY  (0)

+

+#define OTP1_SIZE         (4)

+#define OTP2_SIZE         (16)

+#define OTP3_SIZE         (4)

+

+typedef unsigned char   _otp_u8_;

+typedef unsigned short  _otp_u16_;

+

+typedef struct OtpDataST {

+

+  /// [AT-PM] : Version ; 01/23/2013

+  _otp_u16_ versionMain;

+  _otp_u16_ versionSub;

+  _otp_u8_ empty;

+  

+  /// [AT-PM] : Raw data ; 01/23/2013

+  _otp_u8_ otp1[OTP1_SIZE];

+  _otp_u8_ otp2[OTP2_SIZE];

+  _otp_u8_ otp3[OTP3_SIZE];

+

+  /// [AT-PM] : Converted value ; 01/23/2013

+  _otp_u16_ adc1DeltaCodeT25V100;

+  _otp_u16_ adc1DeltaCodeT25V200;

+  _otp_u16_ adc2DeltaCodeT25V100;

+  _otp_u16_ adc2DeltaCodeT25V200;

+  _otp_u16_ aveIT25;

+  _otp_u16_ aveIT80;

+

+  _otp_u8_ bgrTune;

+  

+  _otp_u8_ deltaET;

+  _otp_u8_ deltaVref;

+  _otp_u16_ devAddr;

+

+  _otp_u16_ ftIT;

+  

+  _otp_u8_ indexAdc1V100T25;

+  _otp_u8_ indexAdc1V200T25;

+  _otp_u8_ indexAdc2V100T25;

+  _otp_u8_ indexAdc2V200T25;

+

+  _otp_u8_ oscDeltaCode25;

+  _otp_u8_ oscDeltaCode80;

+  _otp_u8_ otpCellEN;

+  

+  _otp_u8_ productType;

+  

+#if defined(uG31xx_OS_ANDROID)

+} __attribute__ ((aligned(4))) OtpDataType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)	      

+} OtpDataType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/**

+ * @brief UpiConvertOtp

+ *

+ *  Convert OTP register value to readable value

+ *

+ * @para  data  address of OtpDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiConvertOtp(OtpDataType *data);

+

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_API_System.c b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_System.c
new file mode 100755
index 0000000..38dc9d1
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_System.c
@@ -0,0 +1,1216 @@
+/**

+ * @filename  uG31xx_API_System.cpp

+ *

+ *  uG31xx system control

+ *

+ * @author  AllenTeng <allen_teng@upi-semi.com>

+ */

+

+#include "stdafx.h"     //windows need this??

+#include "uG31xx_API.h"

+

+#if defined(uG31xx_OS_ANDROID)

+

+_upi_bool_ ReadGGBXFileToCellDataAndInitSetting(SystemDataType *obj)

+{

+  _sys_u8_ *p_start = _UPI_NULL_;

+  _sys_u8_ *p_end = _UPI_NULL_;

+  _sys_u16_ sum16=0;

+  _sys_s32_ i=0;

+

+  /*

+     * check GGBX_FILE tag

+     */

+  if(obj->ggbXBuf->ggb_tag != GGBX_FILE_TAG)

+  {

+    UG31_LOGE("[%s] GGBX file tag not correct. tag: %08X\n", __func__, obj->ggbXBuf->ggb_tag);

+    return (_UPI_FALSE_);

+  }

+

+  /*

+     * check GGBX_FILE checksum

+     */

+  p_start = (_sys_u8_ *)obj->ggbXBuf + sizeof(GGBX_FILE_HEADER);

+  p_end = p_start + obj->ggbXBuf->length - 1;

+  for (; p_start <= p_end; p_start++) 

+  {

+    sum16 += *p_start;

+  }

+

+  /* check done. prepare copy data */

+  memset(obj->ggbCellTable, 0x00, sizeof(CELL_TABLE));

+  memset(obj->ggbParameter, 0x00, sizeof(CELL_PARAMETER));

+

+  p_start = (_sys_u8_ *)obj->ggbXBuf + sizeof(GGBX_FILE_HEADER);

+  for (i=0; i<obj->ggbXBuf->num_ggb; i++)

+  {

+    /* TODO: boundary checking */

+    /* TODO: select right ggb content by sku */

+    memcpy(obj->ggbParameter, p_start, sizeof(CELL_PARAMETER)); 

+    memcpy(obj->ggbCellTable, p_start + sizeof(CELL_PARAMETER), sizeof(CELL_TABLE)); 

+    p_start += (sizeof(CELL_PARAMETER) + sizeof(CELL_TABLE));

+  }

+  return (_UPI_TRUE_);

+}

+

+#else   ///< else of defined(uG31xx_OS_ANDROID)

+

+ _upi_bool_ ReadGGBFileToCellDataAndInitSetting(SystemDataType *obj)

+{

+  FILE* stream;

+  _wfopen_s(&stream, obj->ggbFilename, _T("rb, ccs=UTF-8"));

+

+  memset(obj->ggbCellTable, 0x00, sizeof(CELL_TABLE));

+  memset(obj->ggbParameter, 0x00, sizeof(CELL_PARAMETER));

+

+  if(!stream)

+  {

+    return (_UPI_FALSE_);

+  }

+  if(fread(obj->ggbParameter, sizeof(char), sizeof(CELL_PARAMETER), stream) != sizeof(CELL_PARAMETER))

+  {

+    fclose(stream);

+    return (_UPI_FALSE_);

+  }

+  if(fread(obj->ggbCellTable, sizeof(char), sizeof(CELL_TABLE), stream) != sizeof(CELL_TABLE))

+  {

+    fclose(stream);

+    return (_UPI_FALSE_);

+  }

+

+  fclose(stream);

+

+  return (_UPI_TRUE_);

+}

+

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/**

+ * @brief GetCellNum

+ *

+ *  Get cell number from ggbParameter->ICType

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void GetCellNum(SystemDataType *data)

+{

+  _sys_u8_ cellNum[6] = {1, 1, 2, 0, 2, 3};

+

+  data->cellNum = cellNum[data->ggbParameter->ICType];

+}

+

+/**

+ * @brief SetupAdcChopFunction

+ *

+ *  Setup ADC chop function

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void SetupAdcChopFunction(SystemDataType *data)

+{

+	API_I2C_SingleWrite(SECURITY, 

+                      UG31XX_I2C_HIGH_SPEED_MODE, 

+                      UG31XX_I2C_TEM_BITS_MODE, 

+                      REG_FW_CTRL, 

+                      data->ggbParameter->chopCtrl);

+}

+

+/**

+ * @brief SetupAdc1Queue

+ *

+ *  Setup ADC1 conversion queue

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void SetupAdc1Queue(SystemDataType *data)

+{

+  _cap_u8_ adcQueue[4];

+

+  adcQueue[0] = SET_A_ET | SET_B_ET | SET_C_CURRENT | SET_D_CURRENT;

+  adcQueue[1] = SET_E_CURRENT | SET_F_CURRENT | SET_G_CURRENT | SET_H_CURRENT;

+  adcQueue[2] = SET_I_IT | SET_J_IT | SET_K_CURRENT | SET_L_CURRENT;

+  adcQueue[3] = SET_M_CURRENT | SET_N_CURRENT | SET_O_CURRENT | SET_P_CURRENT;

+

+ 	API_I2C_Write(SECURITY, 

+                UG31XX_I2C_HIGH_SPEED_MODE, 

+                UG31XX_I2C_TEM_BITS_MODE, 

+                REG_ADC_CTR_A, 

+                4, 

+                &adcQueue[0]);

+}

+

+/**

+ * @brief SetupAdc2Queue

+ *

+ *  Set ADC2 conversion queue

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void SetupAdc2Quene(SystemDataType *data)

+{

+  _sys_u8_ adc2Queue[3];

+  

+  /// [AT-PM] : Set sell type ; 01/31/2013

+  if(data->cellNum == 1)

+  {

+    adc2Queue[0] = SET_V1_VBAT1 | SET_V2_VBAT1 | SET_V3_VBAT1 | SET_V4_VBAT1;

+    adc2Queue[1] = SET_V5_VBAT1 | SET_V6_VBAT1 | SET_V7_VBAT1 | SET_V8_VBAT1;

+    adc2Queue[2] = SET_V9_VBAT1 | SET_V10_VBAT1 | SET_V11_VBAT1 | SET_V12_VBAT1;

+  }

+  else if(data->cellNum == 2)

+  {

+    adc2Queue[0] = SET_V1_VBAT1 | SET_V2_VBAT1 | SET_V3_VBAT2 | SET_V4_VBAT2;

+    adc2Queue[1] = SET_V5_VBAT1 | SET_V6_VBAT1 | SET_V7_VBAT2 | SET_V8_VBAT2;

+    adc2Queue[2] = SET_V9_VBAT1 | SET_V10_VBAT1 | SET_V11_VBAT2 | SET_V12_VBAT2;

+  }

+  else if(data->cellNum == 3)

+  {

+    adc2Queue[0] = SET_V1_VBAT1 | SET_V2_VBAT1 | SET_V3_VBAT2 | SET_V4_VBAT2;

+    adc2Queue[1] = SET_V5_VBAT3 | SET_V6_VBAT3 | SET_V7_VBAT1 | SET_V8_VBAT1;

+    adc2Queue[2] = SET_V9_VBAT2 | SET_V10_VBAT2 | SET_V11_VBAT3 | SET_V12_VBAT3;

+  }

+  else

+  {

+    /// [AT-PM] : 1-cell ; 01/31/2013

+    adc2Queue[0] = SET_V1_VBAT1 | SET_V2_VBAT1 | SET_V3_VBAT1 | SET_V4_VBAT1;

+    adc2Queue[1] = SET_V5_VBAT1 | SET_V6_VBAT1 | SET_V7_VBAT1 | SET_V8_VBAT1;

+    adc2Queue[2] = SET_V9_VBAT1 | SET_V10_VBAT1 | SET_V11_VBAT1 | SET_V12_VBAT1;

+  }

+  API_I2C_Write(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_ADC_V1, 3, &adc2Queue[0]);

+}

+

+/**

+ * @brief EnableCbc

+ *

+ *  Enable CBC function

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void EnableCbc(SystemDataType *data)

+{

+  _sys_u8_ tmp8;

+

+	API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_INTR_CTRL_B, &tmp8);

+  tmp8 = tmp8 & (~(INTR_CTRL_B_CBC_32_EN | INTR_CTRL_B_CBC_21_EN));

+  tmp8 = tmp8 | (INTR_CTRL_B_ET_EN | INTR_CTRL_B_IT_EN | INTR_CTRL_B_RID_EN);

+  tmp8 = tmp8 | (data->ggbParameter->cbcEnable << 4);

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_INTR_CTRL_B, tmp8);

+}

+

+/**

+ * @brief EnableICType

+ *

+ *  Enable IC type

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void EnableICType(SystemDataType *data)

+{

+  _sys_u8_ tmp8;

+

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_CELL_EN, &tmp8);

+  tmp8 = tmp8 & (~CELL_EN_APPLICATION);

+  tmp8 = tmp8 | (data->ggbParameter->ICType << 2);

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_CELL_EN, tmp8);

+}

+

+/**

+ * @brief ConfigGpioFunction

+ *

+ *  Configure GPIO1/2 function

+ *

+ * @para  setting GPIO1/2 setting

+ * @return  register value

+ */

+_sys_u8_ ConfigGpioFunction(_sys_u8_ setting)

+{

+	_sys_u8_ gpioSelData = 0;

+    

+	if(setting & FUN_GPIO)

+	{

+		gpioSelData = 0;

+	}

+	if(setting & FUN_ALARM)   //select Alarm function

+	{

+		gpioSelData = 1;

+	}

+	if(setting & FUN_CBC_EN21)	//cbc21 enable

+	{

+		gpioSelData = 2;

+	}if(setting & FUN_CBC_EN32)		//cbc32 Enable

+	{

+		gpioSelData = 3;

+	}

+	if(setting & FUN_PWM)  //PWM function, set PWM cycle

+	{

+		gpioSelData = 4;

+	}

+	return (gpioSelData);

+}

+

+/**

+ * @brief ConfigureGpio

+ *

+ *  Configure GPIO function

+ *

+ * @para  data  SystemDataType

+ * @return  _UPI_NULL_

+ */

+void ConfigureGpio(SystemDataType *data)

+{

+  _sys_u8_ tmp8;

+

+  API_I2C_SingleRead(SECURITY, 

+                     UG31XX_I2C_HIGH_SPEED_MODE, 

+                     UG31XX_I2C_TEM_BITS_MODE, 

+                     REG_INTR_CTRL_A, 

+                     &tmp8);

+  tmp8 = tmp8 | (ConfigGpioFunction(data->ggbParameter->gpio1) << 2);

+  tmp8 = tmp8 | (ConfigGpioFunction(data->ggbParameter->gpio2) << 5);

+  API_I2C_SingleWrite(SECURITY, 

+                      UG31XX_I2C_HIGH_SPEED_MODE, 

+                      UG31XX_I2C_TEM_BITS_MODE, 

+                      REG_INTR_CTRL_A, 

+                      tmp8);

+  API_I2C_SingleWrite(SECURITY, 

+                      UG31XX_I2C_HIGH_SPEED_MODE, 

+                      UG31XX_I2C_TEM_BITS_MODE, 

+                      REG_INTR_CTRL_D, 

+                      data->ggbParameter->gpio34);

+}

+

+#define ADC_FAIL_CRITERIA     (10)

+

+/**

+ * @brief CheckAdcStatusFail

+ *

+ *  Check ADC status is fail or not

+ *

+ * @para  pUg31xx address of SystemDataType

+ * @return  _UPI_TRUE_ if fail

+ */

+_upi_bool_ CheckAdcStatusFail(SystemDataType *data)

+{

+  API_I2C_Read(NORMAL, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_COUNTER_LOW, 

+               REG_COUNTER_HIGH - REG_COUNTER_LOW + 1, 

+               (unsigned char *)&data->adcCheckData.regCounter);

+

+  API_I2C_Read(NORMAL, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_AVE_VBAT1_LOW, 

+               REG_AVE_VBAT1_HIGH - REG_AVE_VBAT1_LOW + 1, 

+               (unsigned char *)&data->adcCheckData.regVbat1Ave);

+

+  /// [AT-PM] : Compare counter register ; 01/27/2013

+  if(data->adcCheckData.regCounter == data->adcCheckData.lastCounter)

+  {

+    data->adcCheckData.failCounterCurrent = data->adcCheckData.failCounterCurrent + 1;

+    UG31_LOGI("[%s]: Counter fixed (%d) ... %d\n", __func__,

+              data->adcCheckData.regCounter, data->adcCheckData.failCounterCurrent);

+  }

+  else

+  {

+    data->adcCheckData.failCounterCurrent = 0;

+  }

+  data->adcCheckData.lastCounter = data->adcCheckData.regCounter;

+

+  /// [AT-PM] : Compre VBat1 register ; 01/27/2013

+  if(data->adcCheckData.regVbat1Ave == data->adcCheckData.lastVBat1Ave)

+  {

+    data->adcCheckData.failCounterVoltage = data->adcCheckData.failCounterVoltage + 1;

+    UG31_LOGI("[%s]: VBat1 fixed (%d) ... %d\n", __func__,

+              data->adcCheckData.regVbat1Ave, data->adcCheckData.failCounterVoltage);

+  }

+  else

+  {

+    data->adcCheckData.failCounterVoltage = 0;

+  }

+  data->adcCheckData.lastVBat1Ave = data->adcCheckData.regVbat1Ave;

+

+  /// [AT-PM] : Check ADC fail criteria ; 01/27/2013

+  if(data->adcCheckData.failCounterCurrent > ADC_FAIL_CRITERIA)

+  {

+    data->adcCheckData.failCounterCurrent = 0;

+    return (_UPI_TRUE_);

+  }

+  if(data->adcCheckData.failCounterVoltage > ADC_FAIL_CRITERIA)

+  {

+    data->adcCheckData.failCounterVoltage = 0;

+    return (_UPI_TRUE_);

+  }

+  return (_UPI_FALSE_);

+}	

+

+/**

+ * @brief DecimateRst

+ *

+ *  Decimate reset filter of ADC

+ *

+ * @return  _UPI_NULL_

+ */

+void DecimateRst(void)

+{

+  _sys_u8_ tmp8;

+

+  tmp8 = 0x00;

+  API_I2C_Read(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_ALARM_EN, 1, &tmp8);

+  tmp8 = tmp8 & (~ALARM_EN_DECIMATE_RST);

+  API_I2C_Write(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_ALARM_EN, 1, &tmp8);

+  tmp8 = tmp8 | ALARM_EN_DECIMATE_RST;

+  API_I2C_Write(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_ALARM_EN, 1,  &tmp8);

+  UG31_LOGI("[%s]: DECIMATE_RST\n", __func__);

+}

+

+/**

+ * @brief AlarmEnable

+ *

+ *  Enable alarm

+ *

+ * @para  alarm REG_ALARM_EN bits

+ * @return  NULL

+ */

+void AlarmEnable(_sys_u8_ alarm)

+{

+  _sys_u8_ tmp8;

+  

+  API_I2C_Read(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_ALARM_EN, 1, &tmp8);

+  tmp8 = tmp8 | alarm;

+  API_I2C_Write(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_ALARM_EN, 1, &tmp8);

+}

+

+/**

+ * @brief AlarmDisable

+ *

+ *  Disable alarm

+ *

+ * @para  alarm REG_ALARM_EN bits

+ * @return  NULL

+ */

+void AlarmDisable(_sys_u8_ alarm)

+{

+  _sys_u8_ tmp8;

+  

+  API_I2C_Read(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_ALARM_EN, 1, &tmp8);

+  tmp8 = tmp8 & (~alarm);

+  API_I2C_Write(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_ALARM_EN, 1, &tmp8);

+}

+

+#define SYS_ALARM_STS_UV1     (ALARM2_STATUS_UV1_ALARM)

+#define SYS_ALARM_STS_OV1     (ALARM2_STATUS_OV1_ALARM)

+#define SYS_ALARM_STS_UV2     (ALARM2_STATUS_UV2_ALARM)

+#define SYS_ALARM_STS_OV2     (ALARM2_STATUS_OV2_ALARM)

+#define SYS_ALARM_STS_UV3     (ALARM2_STATUS_UV3_ALARM)

+#define SYS_ALARM_STS_OV3     (ALARM2_STATUS_OV3_ALARM)

+#define SYS_ALARM_STS_UET     (ALARM1_STATUS_UET_ALARM<<8)

+#define SYS_ALARM_STS_OET     (ALARM1_STATUS_OET_ALARM<<8)

+#define SYS_ALARM_STS_UIT     (ALARM1_STATUS_UIT_ALARM<<8)

+#define SYS_ALARM_STS_OIT     (ALARM1_STATUS_OIT_ALARM<<8)

+#define SYS_ALARM_STS_DOC     (ALARM1_STATUS_DOC_ALARM<<8)

+#define SYS_ALARM_STS_COC     (ALARM1_STATUS_COC_ALARM<<8)

+

+/**

+ * @brief ProcUVAlarm

+ *

+ *  UV alarm function

+ *

+ * @para  data  address of SystemDataType

+ * @return  NULL

+ */

+void ProcUVAlarm(SystemDataType *data)

+{

+  _sys_u8_ tmp8[4];

+  

+  /// [AT-PM] : Check alarm is enable or not ; 04/08/2013

+  if(!(data->ggbParameter->alarmEnable & CELL_PARAMETER_ALARM_EN_UV))

+  {

+    /// [AT-PM] : Disable UV and OV alarm ; 04/08/2013

+    AlarmDisable(ALARM_EN_V1_ALARM_EN);

+    return;

+  }

+

+  if(data->uvAlarm.state == _UPI_TRUE_)

+  {

+    /// [AT-PM] : UV alarm has been set -> Wait for OV alarm ; 04/08/2013

+    if(data->alarmSts & SYS_ALARM_STS_OV1)

+    {

+      data->uvAlarm.state = _UPI_FALSE_;

+      

+      /// [AT-PM] : Release UV alarm by disable ; 04/08/2013

+      AlarmDisable(ALARM_EN_V1_ALARM_EN);

+

+      /// [AT-PM] : UV release threshold reached -> set alarm threshold ; 04/08/2013

+      tmp8[0] = 0xff;

+      tmp8[1] = 0x7f;

+      tmp8[2] = (_sys_u8_)(data->uvAlarm.alarmThrd & 0x00ff);

+      tmp8[3] = (_sys_u8_)(data->uvAlarm.alarmThrd >> 8);      

+    }

+    else

+    {

+      /// [AT-PM] : UV state -> set release threshold ; 04/08/2013

+      tmp8[0] = (_sys_u8_)(data->uvAlarm.releaseThrd & 0x00ff);

+      tmp8[1] = (_sys_u8_)(data->uvAlarm.releaseThrd >> 8);

+      tmp8[2] = 0x00;

+      tmp8[3] = 0x00;

+    }

+  }

+  else

+  {

+    /// [AT-PM] : Normal state ; 04/08/2013

+    if(data->alarmSts & SYS_ALARM_STS_UV1)

+    {

+      data->uvAlarm.state = _UPI_TRUE_;

+      

+      /// [AT-PM] : Release UV alarm by disable ; 04/08/2013

+      AlarmDisable(ALARM_EN_V1_ALARM_EN);

+

+      /// [AT-PM] : UV alarm reached -> set release threshold ; 04/08/2013

+      tmp8[0] = (_sys_u8_)(data->uvAlarm.releaseThrd & 0x00ff);

+      tmp8[1] = (_sys_u8_)(data->uvAlarm.releaseThrd >> 8);

+      tmp8[2] = 0x00;

+      tmp8[3] = 0x00;

+    }

+    else

+    {

+      /// [AT-PM] : Normal state -> set alarm threshold ; 04/08/2013

+      tmp8[0] = 0xff;

+      tmp8[1] = 0x7f;

+      tmp8[2] = (_sys_u8_)(data->uvAlarm.alarmThrd & 0x00ff);

+      tmp8[3] = (_sys_u8_)(data->uvAlarm.alarmThrd >> 8);      

+    }

+  }

+

+  /// [AT-PM] : Set alarm threshold ; 04/08/2013

+  API_I2C_Write(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_OV1_LOW, 4, &tmp8[0]);

+  

+  /// [AT-PM] : Enable UV and OV alarm ; 04/08/2013

+  AlarmEnable(ALARM_EN_V1_ALARM_EN);

+}

+

+/**

+ * @brief ProcETAlarm

+ *

+ *  UET and OET alarm function

+ *

+ * @para  data  address of SystemDataType

+ * @return  NULL

+ */

+void ProcETAlarm(SystemDataType *data)

+{

+  _sys_u8_ tmp8[4];

+  

+  /// [AT-PM] : Check alarm is enable or not ; 04/08/2013

+  if(!(data->ggbParameter->alarmEnable & (CELL_PARAMETER_ALARM_EN_UET | CELL_PARAMETER_ALARM_EN_OET)))

+  {

+    /// [AT-PM] : Disable UV and OV alarm ; 04/08/2013

+    AlarmDisable(ALARM_EN_ET_ALARM_EN);

+    return;

+  }

+

+  if(data->uetAlarm.state == _UPI_TRUE_)

+  {

+    /// [AT-PM] : UET alarm state -> wait for OET alarm ; 04/08/2013

+    if(data->alarmSts & SYS_ALARM_STS_OET)

+    {

+      data->uetAlarm.state = _UPI_FALSE_;

+      

+      /// [AT-PM] : Release by disable ; 04/08/2013

+      AlarmDisable(ALARM_EN_ET_ALARM_EN);

+

+      /// [AT-PM] : UET release met -> set UET and OET alarm ; 04/08/2013

+      tmp8[0] = (_sys_u8_)(data->oetAlarm.alarmThrd & 0x00ff);

+      tmp8[1] = (_sys_u8_)(data->oetAlarm.alarmThrd >> 8);

+      tmp8[2] = (_sys_u8_)(data->uetAlarm.alarmThrd & 0x00ff);

+      tmp8[3] = (_sys_u8_)(data->uetAlarm.alarmThrd >> 8);

+    }

+    else

+    {

+      /// [AT-PM] : Wait OET alarm ; 04/08/2013

+      tmp8[0] = (_sys_u8_)(data->uetAlarm.releaseThrd & 0x00ff);

+      tmp8[1] = (_sys_u8_)(data->uetAlarm.releaseThrd >> 8);

+      tmp8[2] = 0x00;

+      tmp8[3] = 0x00;

+    }

+  }

+  else if(data->oetAlarm.state == _UPI_TRUE_)

+  {

+    /// [AT-PM] : OET alarm state -> wait for UET alarm ; 04/08/2013

+    if(data->alarmSts & SYS_ALARM_STS_UET)

+    {

+      data->oetAlarm.state = _UPI_FALSE_;

+      

+      /// [AT-PM] : Release by disable ; 04/08/2013

+      AlarmDisable(ALARM_EN_ET_ALARM_EN);

+

+      /// [AT-PM] : OET release met -> set UET and OET alarm ; 04/08/2013

+      tmp8[0] = (_sys_u8_)(data->oetAlarm.alarmThrd & 0x00ff);

+      tmp8[1] = (_sys_u8_)(data->oetAlarm.alarmThrd >> 8);

+      tmp8[2] = (_sys_u8_)(data->uetAlarm.alarmThrd & 0x00ff);

+      tmp8[3] = (_sys_u8_)(data->uetAlarm.alarmThrd >> 8);

+    }

+    else

+    {

+      /// [AT-PM] : Wait UET alarm ; 04/08/2013

+      tmp8[0] = 0xff;

+      tmp8[1] = 0x7f;

+      tmp8[2] = (_sys_u8_)(data->oetAlarm.releaseThrd & 0x00ff);

+      tmp8[3] = (_sys_u8_)(data->oetAlarm.releaseThrd >> 8);

+    }

+  }

+  else

+  {

+    /// [AT-PM] : Normal state ; 04/08/2013

+    if((data->alarmSts & SYS_ALARM_STS_UET) && 

+       (data->ggbParameter->alarmEnable & CELL_PARAMETER_ALARM_EN_UET))

+    {

+      data->uetAlarm.state = _UPI_TRUE_;

+      

+      /// [AT-PM] : Release by disable ; 04/08/2013

+      AlarmDisable(ALARM_EN_ET_ALARM_EN);

+

+      /// [AT-PM] : UET is set -> set UET release threshold ; 04/08/2013

+      tmp8[0] = (_sys_u8_)(data->uetAlarm.releaseThrd & 0x00ff);

+      tmp8[1] = (_sys_u8_)(data->uetAlarm.releaseThrd >> 8);

+      tmp8[2] = 0x00;

+      tmp8[3] = 0x00;

+    }

+    else if((data->alarmSts & SYS_ALARM_STS_OET) && 

+            (data->ggbParameter->alarmEnable & CELL_PARAMETER_ALARM_EN_OET))

+    {

+      data->oetAlarm.state = _UPI_TRUE_;

+      

+      /// [AT-PM] : Release by disable ; 04/08/2013

+      AlarmDisable(ALARM_EN_ET_ALARM_EN);

+      

+      /// [AT-PM] : OET is set -> set OET release threshold ; 04/08/2013

+      tmp8[0] = 0xff;

+      tmp8[1] = 0x7f;

+      tmp8[2] = (_sys_u8_)(data->oetAlarm.releaseThrd & 0x00ff);

+      tmp8[3] = (_sys_u8_)(data->oetAlarm.releaseThrd >> 8);

+    }

+    else

+    {

+      /// [AT-PM] : Set OET alarm threshold ; 04/08/2013

+      if(data->ggbParameter->alarmEnable & CELL_PARAMETER_ALARM_EN_OET)

+      {

+        tmp8[0] = (_sys_u8_)(data->oetAlarm.alarmThrd & 0x00ff);

+        tmp8[1] = (_sys_u8_)(data->oetAlarm.alarmThrd >> 8);

+      }

+      else

+      {

+        tmp8[0] = 0xff;

+        tmp8[1] = 0x7f;

+      }

+      /// [AT-PM] : Set UET alarm threshold ; 04/11/2013

+      if(data->ggbParameter->alarmEnable & CELL_PARAMETER_ALARM_EN_UET)

+      {

+        tmp8[2] = (_sys_u8_)(data->uetAlarm.alarmThrd & 0x00ff);

+        tmp8[3] = (_sys_u8_)(data->uetAlarm.alarmThrd >> 8);

+      }

+      else

+      {

+        tmp8[2] = 0x00;

+        tmp8[3] = 0x00;

+      }

+    }

+  }

+

+  /// [AT-PM] : Set alarm threshold ; 04/08/2013

+  API_I2C_Write(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_EXTR_OVER_TEMP_LOW, 4, &tmp8[0]);

+  

+  /// [AT-PM] : Enable UV and OV alarm ; 04/08/2013

+  AlarmEnable(ALARM_EN_ET_ALARM_EN);

+}

+

+/** 

+ * @brief EnableAlarm

+ *

+ *  Set UV, UET, and OET alarm functions

+ *

+ * @para  data  address of SystemDataType

+ * @return  NULL

+ */

+void EnableAlarm(SystemDataType *data)

+{

+  /// [AT-PM] : UV alarm ; 04/08/2013

+  ProcUVAlarm(data);

+  

+  /// [AT-PM] : UET and OET alarm ; 04/08/2013

+  ProcETAlarm(data);

+}

+

+/// =============================================

+/// [AT-PM] : Extern function region

+/// =============================================

+

+/**

+ * @brief UpiInitSystemData

+ *

+ *  Initialize system variables

+ *

+ * @para  data  address of SystemDataType

+ * @return  SYSTEM_RTN_CODE

+ */

+SYSTEM_RTN_CODE UpiInitSystemData(SystemDataType *data)

+{

+  /// [AT-PM] : Initialize variables ; 01/30/2013

+  data->preITAve = 0;

+  data->cellNum = 0;

+

+  /// [AT-PM] : Load GGB file ; 01/30/2013

+  UG31_LOGI("[%s]: Read GGB\n", __func__);

+  #if defined(uG31xx_OS_ANDROID)

+	  if(!ReadGGBXFileToCellDataAndInitSetting(data))

+  #else

+	  if(!ReadGGBFileToCellDataAndInitSetting(data))

+  #endif

+	{

+ 		return (SYSTEM_RTN_READ_GGB_FAIL);

+	}

+

+  /// [AT-PM] : Set cell number ; 01/31/2013

+  GetCellNum(data);

+  return (SYSTEM_RTN_PASS);

+}

+

+/**

+ * @brief UpiCheckICActive

+ *

+ *  Check IC is actived or not

+ *

+ * @return  _UPI_TRUE_ if uG31xx is not actived

+ */

+_upi_bool_ UpiCheckICActive(void)

+{

+  _upi_u8_ tmp;

+

+  if(!API_I2C_Read(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_MODE, 1, &tmp))

+  {

+    UG31_LOGI("[%s]: Get GG_RUN fail.\n", __func__);

+    return (_UPI_TRUE_);

+  }

+

+  if((tmp & MODE_GG_RUN) == GG_RUN_OPERATION_MODE)

+  {

+    UG31_LOGI("[%s]: uG31xx is actived.\n", __func__);

+    return (_UPI_FALSE_);

+  }

+  UG31_LOGI("[%s]: uG31xx is NOT actived.\n", __func__);

+  return (_UPI_TRUE_);

+}

+

+/**

+ * @brief UpiActiveUg31xx

+ *

+ *  Active uG31xx

+ *

+ * @return  SYSTEM_RTN_CODE

+ */

+SYSTEM_RTN_CODE UpiActiveUg31xx(void)

+{

+  _sys_u8_ tmp8;

+  

+  /// [AT-PM] : Reset uG31xx ; 01/31/2013

+  tmp8 = PORDET_W_SOFTRESET | IO1DATA_W_HIGH;

+	if(!API_I2C_Write(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_CTRL1, 1, &tmp8))

+  { 

+		return (SYSTEM_RTN_I2C_FAIL);

+  }

+  tmp8 = IO1DATA_W_HIGH;

+	if(!API_I2C_Write(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_CTRL1, 1, &tmp8))

+  { 

+		return (SYSTEM_RTN_I2C_FAIL);

+  }  

+

+  /// [AT-PM] : Active uG31xx ; 01/31/2013

+  tmp8 = CTRL1_GG_RST | IO1DATA_W_HIGH;

+	if(!API_I2C_Write(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_CTRL1, 1, &tmp8))

+  { 

+		return (SYSTEM_RTN_I2C_FAIL);

+  }

+  tmp8 = GG_RUN_OPERATION_MODE;

+	if(!API_I2C_Write(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_MODE, 1, &tmp8))

+  { 

+		return (SYSTEM_RTN_I2C_FAIL);

+  }

+

+  /// [AT-PM] : Delay 255mS for system stable ; 01/31/2013  

+  SleepMiniSecond(255);     //2012/08/29/Jacky, need wait 255 ms 

+  return (SYSTEM_RTN_PASS);

+}

+

+/**

+ * @brief UpiSetupAdc

+ *

+ *  Setup ADC configurations

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void UpiSetupAdc(SystemDataType *data)

+{

+  _sys_u8_ tmp8;

+  

+  /// [AT-PM] : Set ADC chop function ; 01/31/2013

+	SetupAdcChopFunction(data);

+

+  /// [AT-PM] : Set ADC1 queue ; 01/31/2013

+	SetupAdc1Queue(data);

+  

+  /// [AT-PM] : Set ADC2 queue ; 01/31/2013

+	SetupAdc2Quene(data);

+

+  /// [AT-PM] : Enable ADC ; 01/31/2013

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_INTR_CTRL_A, &tmp8);

+  tmp8 = tmp8 | (INTR_CTRL_A_ADC2_EN | INTR_CTRL_A_ADC1_EN);

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_INTR_CTRL_A, tmp8);

+

+  /// [AT-PM] : Decimate reset ; 01/31/2013

+  DecimateRst();

+  

+  /// [AT-PM] : Enable CBC function ; 01/31/2013

+  EnableCbc(data);

+}

+

+/**

+ * @brief UpiSetupSystem

+ *

+ *  Setup uG31xx system

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void UpiSetupSystem(SystemDataType *data)

+{

+  _sys_u8_ tmp8;

+  

+  /// [AT-PM] : Enable IC type ; 01/31/2013

+  EnableICType(data);

+

+  /// [AT-PM] : Configure GPIO ; 01/31/2013

+  ConfigureGpio(data);

+

+  /// [AT-PM] : Enable cell ; 01/31/2013    

+	API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_CELL_EN, &tmp8);

+	tmp8 = tmp8 | (CELL_EN1 | CELL_EN0);

+	API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_CELL_EN, tmp8);

+}

+

+#define OSC_CNT_TARG 512	//oscCntTarg[9:0]

+

+/**

+ * @brief UpiCalibrationOsc

+ *

+ *  OSC calibration

+ *    oscCnt25[9:0] = oscCntTarg[9:0] + oscDeltaCode25[7:0]

+ *    oscCnt80[9:0] = oscCntTarg[9:0] + oscDeltaCode80[7:0]

+ *    oscCnt[9:0] = m*ITcode[15:8] + C[9:0]

+ *    m = (oscCnt80[9:0]-oscCnt25[9:0])/(iTcode80[7:0]-iTcode25[7:0])

+ *    c = oscCnt25[9:0] - m*ITcode25[7:0]

+ *    write oscCnt[9:0] to register 0x97-98

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void UpiCalibrationOsc(SystemDataType *data)

+{

+  _sys_u16_ u16Temp;

+

+  _sys_u16_ oscCnt25;

+  _sys_u16_ oscCnt80;					//10 bits

+  _sys_u16_ oscDeltaCode25;

+  _sys_u16_ oscDeltaCode80;   //

+  _sys_u16_ targetOscCnt;				//target osc

+

+  _sys_u16_ varM;

+  _sys_u16_ varC;

+

+  _sys_u16_ aveIT;

+

+  /// [AT-PM] : Calculate m & C ; 01/25/2013

+  oscDeltaCode25 = (_sys_u16_)data->otpData->oscDeltaCode25;

+  oscDeltaCode80 = (_sys_u16_)data->otpData->oscDeltaCode80;

+

+  oscCnt25 = OSC_CNT_TARG + oscDeltaCode25;

+  oscCnt80 = OSC_CNT_TARG + oscDeltaCode80;

+

+  varM = (oscCnt80 - oscCnt25)/(data->otpData->aveIT80 - data->otpData->aveIT25);

+  varC = oscCnt25 - varM*(data->otpData->aveIT25);

+

+  /// [AT-PM] : Read ITAve ; 01/27/2013

+  API_I2C_Read(NORMAL, 

+               UG31XX_I2C_HIGH_SPEED_MODE, 

+               UG31XX_I2C_TEM_BITS_MODE, 

+               REG_AVE_IT_LOW, 

+               REG_AVE_IT_HIGH - REG_AVE_IT_LOW + 1, 

+               (_sys_u8_ *)&aveIT);

+

+  /// [AT-PM] : Calculate target OSC cnt ; 01/25/2013

+  targetOscCnt = varM*(aveIT/256) + varC;

+  if(targetOscCnt & 0x8000)   //check +/-

+  {

+    u16Temp = (_sys_u16_)(targetOscCnt & 0x1fff);

+    u16Temp |= 0x0200;      // minus

+  } else{

+    u16Temp = (_sys_u16_)targetOscCnt;  //positive data

+  }

+

+  /// [AT-PM] : Write to register 0x97-98 ; 01/25/2013

+  API_I2C_SingleWrite(SECURITY, 

+                      UG31XX_I2C_HIGH_SPEED_MODE, 

+                      UG31XX_I2C_TEM_BITS_MODE, 

+                      OSCTUNE_CNTB, 

+                      (_sys_u8_)(u16Temp >> 8));

+  API_I2C_SingleWrite(SECURITY, 

+                      UG31XX_I2C_HIGH_SPEED_MODE, 

+                      UG31XX_I2C_TEM_BITS_MODE, 

+                      OSCTUNE_CNTA, 

+                      (_sys_u8_)u16Temp );

+}

+

+/**

+ * @brief UpiAdcStatus

+ *

+ *  Check ADC status

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void UpiAdcStatus(SystemDataType *data)

+{

+	if(CheckAdcStatusFail(data) == _UPI_TRUE_)      //check ADC Code frozen 

+	{

+    DecimateRst();

+	}			

+}

+

+#define BACKUP_TIME_BYTE3       (REG_COC_LOW)

+#define BACKUP_TIME_BYTE2       (REG_OTP_CTRL)

+#define BACKUP_NAC_HIGH         (REG_CBC21_LOW)

+#define BACKUP_NAC_LOW          (REG_CBC21_HIGH)

+#define BACKUP_LMD_HIGH         (REG_CBC32_LOW)

+#define BACKUP_LMD_LOW          (REG_CBC32_HIGH)

+#define BACKUP_TABLE_UPDATE_IDX (REG_COC_HIGH)

+#define BACKUP_DELTA_CAP_HIGH   (REG_DOC_LOW)

+#define BACKUP_DELTA_CAP_LOW    (REG_DOC_HIGH)

+#define BACKUP_ADC1_CONV_TIME   (REG_COC_HIGH)

+

+/**

+ * @brief UpiLoadBatInfoFromIC

+ *

+ *  Load battery information from uG31xx

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void UpiLoadBatInfoFromIC(SystemDataType *data)

+{

+  _sys_u8_ *u8Ptr;

+  _sys_u8_ u8Temp;

+  _sys_u8_ u8TempHigh;

+  _sys_u32_ u32Temp;

+  _sys_u16_ u16Temp;

+

+  //Load the time tag

+  u8Ptr = (_sys_u8_ *)&data->timeTagFromIC;

+  *u8Ptr = 0;

+  *(u8Ptr + 1) = 0;

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_TIME_BYTE2, &u8Temp);   

+  *(u8Ptr + 2) = u8Temp;

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_TIME_BYTE3, &u8Temp);   

+  *(u8Ptr + 3) = u8Temp;

+

+  //Load the NAC    

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_NAC_HIGH, &u8TempHigh);   

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_NAC_LOW, &u8Temp);  

+  data->rmFromIC = (_sys_u16_)u8TempHigh;

+  data->rmFromIC = data->rmFromIC*256 + u8Temp;

+

+  // Load LMD  

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_LMD_HIGH, &u8TempHigh);   

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_LMD_LOW, &u8Temp);  

+  data->fccFromIC = (_sys_u16_)u8TempHigh;

+  data->fccFromIC = data->fccFromIC*256 + u8Temp;

+  UG31_LOGE("[%s]:timeTag =%u/%x ms,NAC = %d mAh,LMD = %dmAh\n",

+             __func__,

+             data->timeTagFromIC,

+             data->timeTagFromIC,

+             data->rmFromIC,

+             data->fccFromIC);

+

+  /// [AT-PM] : Load table update index ; 02/10/2013

+  API_I2C_SingleRead(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_TABLE_UPDATE_IDX, &u8Temp);

+  data->tableUpdateIdxFromIC = u8Temp & 0x07;

+  UG31_LOGI("[%s]: Table Update Index From IC = %d (0x%02x)\n", __func__, data->tableUpdateIdxFromIC, u8Temp);

+

+  /// [AT-PM] : Load delta capacity ; 02/10/2013

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_DELTA_CAP_HIGH, &u8TempHigh);

+  API_I2C_SingleRead(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_DELTA_CAP_LOW, &u8Temp);

+  data->deltaCapFromIC = (_sys_u16_)u8TempHigh;

+  data->deltaCapFromIC = data->deltaCapFromIC*256 + u8Temp;

+  UG31_LOGI("[%s]: Delta Capacity From IC = %d (0x%02x%02x)\n", __func__, data->deltaCapFromIC, u8TempHigh, u8Temp);

+

+  /// [AT-PM] : Load ADC1 conversion time ; 02/10/2013

+  API_I2C_SingleRead(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_ADC1_CONV_TIME, &u8Temp);

+  u16Temp = (_sys_u16_)(u8Temp & 0xf8);

+  data->adc1ConvTime = u16Temp*TIME_CONVERT_TIME_TO_MSEC;

+  UG31_LOGI("[%s]: ADC1 Conversion Time From IC = %d (0x%02x)\n", __func__, data->adc1ConvTime, u8Temp);

+

+  /// [AT-PM] : Get RSOC ; 01/31/2013

+  if(data->fccFromIC == 0)

+  {

+    data->rsocFromIC = 0;

+  }

+  else

+  {

+    u32Temp = (_sys_u32_)data->rmFromIC;
+    u32Temp = u32Temp*100 + 50;

+    u32Temp = u32Temp/data->fccFromIC;

+    data->rsocFromIC = (_sys_u8_)u32Temp;

+  }

+

+  data->rmFromICBackup = data->rmFromIC;

+  data->fccFromICBackup = data->fccFromIC;

+  data->rsocFromICBackup = data->rsocFromIC;

+}

+

+/**

+ * @brief UpiUpdateBatInfoFromIC

+ *

+ *  Update battery information from uG31xx

+ *

+ * @para  data  address of SystemDataType

+ * @para  deltaQ  delta capacity from coulomb counter

+ * @return  _UPI_NULL_

+ */

+void UpiUpdateBatInfoFromIC(SystemDataType *data, _sys_s16_ deltaQ)

+{

+  _sys_s32_ tmp32;

+  _sys_u16_ oldRM;

+

+  oldRM = data->rmFromIC;

+  

+  tmp32 = (_sys_s32_)data->rmFromIC;

+  tmp32 = tmp32 + deltaQ;

+        #ifdef  UPI_UBOOT_DEBUG_MSG
+                printf("[UpiUpdateBatInfoFromIC] RM = %d + %d = %d\n", data->rmFromIC, deltaQ, tmp32);
+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG
+  if(tmp32 < 0)

+  {

+    tmp32 = 0;

+  }

+  if(tmp32 > data->fccFromIC)

+  {

+    tmp32 = (_sys_s32_)data->fccFromIC;

+  }

+  UG31_LOGI("[%s]: RM = %d + %d = %d\n", __func__,

+            data->rmFromIC, deltaQ, tmp32);

+  data->rmFromIC = (_sys_u16_)tmp32;

+

+        #ifdef  UPI_UBOOT_DEBUG_MSG
+                printf("[UpiUpdateBatInfoFromIC] fccFromIC = %d, rsocFromIC = %d\n", data->fccFromIC, data->rsocFromIC);
+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG
+  if(data->fccFromIC == 0)

+  {

+    data->rsocFromIC = 0;

+  }

+  else

+  {

+    tmp32 = tmp32*100 + 50;
+    tmp32 = tmp32/data->fccFromIC;

+    data->rsocFromIC = (_sys_u8_)tmp32;

+

+    if(oldRM != 0)

+    {

+      /// [AT-PM] : EDVF is not reached in last log data ; 02/13/2013

+      if(data->rsocFromIC == 0)

+      {

+        /// [AT-PM] : Check EDVF threshold ; 02/13/2013

+        if(data->voltage < data->ggbParameter->edv1Voltage)

+        {

+          /// [AT-PM] : Set capacity to 0 when EDVF reached ; 02/13/2013

+          data->rmFromIC = 0;

+          data->rsocFromIC = 0;

+        }

+        else

+        {

+          /// [AT-PM] : Capacity should not be 0 before EDVF ; 02/13/2013

+          tmp32 = (_sys_s32_)data->fccFromIC;

+          tmp32 = tmp32/CONST_PERCENTAGE;

+          data->rmFromIC = (_sys_u16_)tmp32;

+          data->rsocFromIC = 1;

+        }

+        #ifdef  UPI_UBOOT_DEBUG_MSG
+                printf("[UpiUpdateBatInfoFromIC] Voltage = %d, EDVF = %d\n", data->voltage, data->ggbParameter->edv1Voltage);
+		printf("[UpiUpdateBatInfoFromIC] rmFromIC = %d, rsocFromIC = %d\n", data->rmFromIC, data->rsocFromIC);
+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG
+      }

+      else

+      {

+        /// [AT-PM] : Check EDVF threshold ; 02/13/2013

+        if(data->voltage < data->ggbParameter->edv1Voltage)

+        {

+          /// [AT-PM] : Set capacity to 1% when EDVF reached in initialization ; 02/13/2013

+          tmp32 = (_sys_s32_)data->fccFromIC;

+          tmp32 = tmp32/CONST_PERCENTAGE;

+          data->rmFromIC = (_sys_u16_)tmp32;

+          data->rsocFromIC = 1;

+        }

+        #ifdef  UPI_UBOOT_DEBUG_MSG
+                printf("[UpiUpdateBatInfoFromIC] Voltage = %d, EDVF = %d\n", data->voltage, data->ggbParameter->edv1Voltage);
+                printf("[UpiUpdateBatInfoFromIC] rmFromIC = %d, rsocFromIC = %d\n", data->rmFromIC, data->rsocFromIC);
+        #endif  ///< end of UPI_UBOOT_DEBUG_MSG
+      }

+    }

+  }

+}

+

+/**

+ * @brief UpiSaveBatInfoTOIC

+ *

+ *  Save battery information from uG31xx

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+void UpiSaveBatInfoTOIC(SystemDataType *data)

+{

+  _sys_u8_ *u8Ptr;

+  _sys_u8_ u8Temp;

+  _sys_u8_ u8Temp1;

+  _sys_u16_ u16Temp;

+

+  #if defined(uG31xx_OS_ANDROID)

+    data->timeTagFromIC = GetSysTickCount();

+  #else   ///< else of defined(uG31xx_OS_ANDROID)

+    data->timeTagFromIC = GetTickCount();

+  #endif  ///< end of defined(uG31xx_OS_ANDROID)

+  UG31_LOGE("[%s]:timeTag =%u/%x ms,NAC = %d maH,LMD = %d maH\n",

+  						__func__, 

+  						data->timeTagFromIC,

+  						data->timeTagFromIC,

+  						data->rmFromIC,

+  						data->fccFromIC);

+

+  //save the time tag

+  u8Ptr = (_sys_u8_ *)&data->timeTagFromIC;

+  u8Temp = (*(u8Ptr + 2)) & 0xf8;

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_TIME_BYTE2, u8Temp);

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_TIME_BYTE3, *(u8Ptr + 3));		

+

+   //save the NAC					

+  u8Temp = (_sys_u8_)((data->rmFromIC & 0xff00)/256);

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_NAC_HIGH, u8Temp);		

+  u8Temp = (_sys_u8_)(data->rmFromIC & 0x00ff); 

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_NAC_LOW, u8Temp);		

+  

+  // save LMD	

+  u8Temp = (_sys_u8_)((data->fccFromIC & 0xff00)/256);

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_LMD_HIGH, u8Temp);		

+  u8Temp = (_sys_u8_)(data->fccFromIC & 0x00ff); 

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_LMD_LOW, u8Temp);	

+

+  /// [AT-PM] : Save table update index ; 02/10/2013

+  API_I2C_SingleRead(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_TABLE_UPDATE_IDX, &u8Temp);

+  u8Temp = u8Temp & 0xf8;

+  u8Temp = u8Temp | (data->tableUpdateIdxFromIC & 0x07);

+  API_I2C_SingleWrite(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_TABLE_UPDATE_IDX, u8Temp);

+  UG31_LOGI("[%s]: Save Table Update Index = %d - 0x%02x\n", __func__, data->tableUpdateIdxFromIC, u8Temp);

+

+  /// [AT-PM] : Save delta capacity ; 02/10/2013

+  u16Temp = (_sys_u16_)data->deltaCapFromIC;

+  u8Temp = (_sys_u8_)(u16Temp >> 8);

+  API_I2C_SingleWrite(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_DELTA_CAP_HIGH, u8Temp);

+  u8Temp1 = (_sys_u8_)(u16Temp & 0x00ff);

+  API_I2C_SingleWrite(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_DELTA_CAP_LOW, u8Temp1);

+  UG31_LOGI("[%s]: Save Delta Capacity = %d - 0x%02x%02x\n", __func__, data->deltaCapFromIC, u8Temp, u8Temp1);

+

+  /// [AT-PM] : Save adc1 conversion time ; 02/10/2013

+  u16Temp = data->adc1ConvTime/TIME_CONVERT_TIME_TO_MSEC;

+  API_I2C_SingleRead(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_ADC1_CONV_TIME, &u8Temp);

+  u8Temp = u8Temp & 0x07;

+  u8Temp = u8Temp | (u16Temp & 0xf8);

+  API_I2C_SingleWrite(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, BACKUP_ADC1_CONV_TIME, u8Temp);

+  UG31_LOGI("[%s]: Save ADC1 Conversion Time = %d - 0x%02x\n", __func__, data->adc1ConvTime, u8Temp);  

+}

+

+/**

+ * @brief UpiInitAlarm

+ *

+ *  Initialize alarm function of uG3105

+ *

+ * @para  data  address of SystemDataType

+ * @return  NULL

+ */

+void UpiInitAlarm(SystemDataType *data)

+{

+  /// [AT-PM] : Set GPIO as alarm pin ; 04/08/2013

+  ConfigureGpio(data);

+

+  /// [AT-PM] : Set delay time ; 04/08/2013  

+  API_I2C_SingleWrite(SECURITY, 

+                      UG31XX_I2C_HIGH_SPEED_MODE, 

+                      UG31XX_I2C_TEM_BITS_MODE, 

+                      REG_TIMER, 

+                      data->ggbParameter->alarm_timer);

+  API_I2C_SingleWrite(SECURITY, 

+                      UG31XX_I2C_HIGH_SPEED_MODE, 

+                      UG31XX_I2C_TEM_BITS_MODE, 

+                      REG_CLK_DIVA, 

+                      data->ggbParameter->clkDivA);

+  API_I2C_SingleWrite(SECURITY, 

+                      UG31XX_I2C_HIGH_SPEED_MODE, 

+                      UG31XX_I2C_TEM_BITS_MODE, 

+                      REG_CLK_DIVB, 

+                      data->ggbParameter->clkDivB);

+

+  /// [AT-PM] : Enable alarm ; 04/08/2013

+  data->alarmSts = 0;

+  data->uvAlarm.state = _UPI_FALSE_;

+  data->uetAlarm.state = _UPI_FALSE_;

+  data->oetAlarm.state = _UPI_FALSE_;

+  EnableAlarm(data);

+}

+

+/**

+ * @brief UpiAlarmStatus

+ *

+ *  Get alarm status

+ *

+ * @para  data  address of SystemDataType

+ * @return  NULL

+ */

+_sys_u8_ UpiAlarmStatus(SystemDataType *data)

+{

+  _sys_u8_ sts;

+  _sys_u8_ tmp8[2];

+

+  sts = 0;

+

+  /// [AT-PM] : Read alarm status from uG3105 ; 04/08/2013

+  API_I2C_Read(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, REG_ALARM1_STATUS, 2, &tmp8[0]);

+  data->alarmSts = (_sys_u16_)tmp8[0];

+  data->alarmSts = data->alarmSts*256 + tmp8[1];

+  

+  /// [AT-PM] : Enable alarm ; 04/08/2013  

+  EnableAlarm(data);

+

+  /// [AT-PM] : Update current alarm status ; 04/08/2013

+  tmp8[0] = data->uvAlarm.state == _UPI_TRUE_ ? ALARM_STATUS_UV : 0;

+  sts = sts | tmp8[0];

+  tmp8[0] = data->uetAlarm.state == _UPI_TRUE_ ? ALARM_STATUS_UET : 0;

+  sts = sts | tmp8[0];

+  tmp8[0] = data->oetAlarm.state == _UPI_TRUE_ ? ALARM_STATUS_OET : 0;

+  sts = sts | tmp8[0];

+  return (sts);

+}

+

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_API_System.h b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_System.h
new file mode 100755
index 0000000..f1579dc
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_API_System.h
@@ -0,0 +1,211 @@
+/**

+ * @filename  uG31xx_API_System.h

+ *

+ *  Interface of ug31xx system control

+ *

+ * @author  AllenTeng <allen_teng@upi-semi.com>

+ */

+

+#define UG31XX_SYSTEM_VERSION     (6)

+

+typedef unsigned char   _sys_u8_;

+typedef signed char     _sys_s8_;

+typedef unsigned short  _sys_u16_;

+typedef signed short    _sys_s16_;

+typedef unsigned long   _sys_u32_;

+typedef signed long     _sys_s32_;

+typedef char            _sys_bool_;

+

+typedef enum _SYSTEM_RTN_CODE {

+  SYSTEM_RTN_PASS = 0,

+  SYSTEM_RTN_READ_GGB_FAIL,

+  SYSTEM_RTN_I2C_FAIL,

+} SYSTEM_RTN_CODE;

+

+typedef struct AlarmDataST {

+  _sys_u16_ alarmThrd;

+  _sys_u16_ releaseThrd;

+  _sys_bool_ state;

+#if defined(uG31xx_OS_ANDROID)

+    } __attribute__ ((aligned(4))) AlarmDataType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)	      

+    } AlarmDataType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+typedef struct SystemDataST {

+

+  #if defined (uG31xx_OS_WINDOWS)

+    const wchar_t* ggbFilename;

+    const wchar_t* otpFileName;

+    const wchar_t* backupFileName;

+  #elif defined(uG31xx_OS_ANDROID)

+    GGBX_FILE_HEADER *ggbXBuf;

+  #endif

+  

+  CELL_PARAMETER *ggbParameter;

+  CELL_TABLE *ggbCellTable;

+  OtpDataType *otpData;

+  

+  ADC_CHECK adcCheckData;			//add for adc error check 20121025/jacky

+

+  _sys_u16_ voltage;

+  

+  _sys_u16_ preITAve;

+  _sys_u8_ cellNum;

+

+  _sys_u16_ rmFromIC;

+  _sys_u16_ fccFromIC;

+  _sys_u8_ rsocFromIC;

+  _sys_u32_ timeTagFromIC;

+  _sys_u8_ tableUpdateIdxFromIC;

+  _sys_s16_ deltaCapFromIC;

+  _sys_u16_ adc1ConvTime;

+  

+  _sys_u16_ rmFromICBackup;

+  _sys_u16_ fccFromICBackup;

+  _sys_u8_ rsocFromICBackup;

+

+  AlarmDataType uvAlarm;

+  AlarmDataType oetAlarm;

+  AlarmDataType uetAlarm;

+  _sys_u16_ alarmSts;

+#if defined(uG31xx_OS_ANDROID)

+  } __attribute__ ((aligned(4))) SystemDataType;

+#else   ///< else of defined(uG31xx_OS_ANDROID)	      

+  } SystemDataType;

+#endif  ///< end of defined(uG31xx_OS_ANDROID)

+

+/**

+ * @brief UpiInitSystemData

+ *

+ *  Initialize system data

+ *

+ * @para  data  address of BootDataType

+ * @return  _UPI_NULL_

+ */

+extern SYSTEM_RTN_CODE UpiInitSystemData(SystemDataType *data);

+

+/**

+ * @brief UpiCheckICActive

+ *

+ *  Check IC is actived or not

+ *

+ * @return  _UPI_TRUE_ if uG31xx is not actived

+ */

+extern _upi_bool_ UpiCheckICActive(void);

+

+/**

+ * @brief UpiActiveUg31xx

+ *

+ *  Active uG31xx

+ *

+ * @return  SYSTEM_RTN_CODE

+ */

+extern SYSTEM_RTN_CODE UpiActiveUg31xx(void);

+

+/**

+ * @brief UpiSetupAdc

+ *

+ *  Setup ADC configurations

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiSetupAdc(SystemDataType *data);

+

+/**

+ * @brief UpiDecimateRst

+ *

+ *  Decimate reset filter of ADC

+ *

+ * @return  _UPI_NULL_

+ */

+extern void UpiDecimateRst(void);

+

+/**

+ * @brief UpiSetupSystem

+ *

+ *  Setup uG31xx system

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiSetupSystem(SystemDataType *data);

+

+/**

+ * @brief UpiCalibrationOsc

+ *

+ *  OSC calibration

+ *    oscCnt25[9:0] = oscCntTarg[9:0] + oscDeltaCode25[7:0]

+ *    oscCnt80[9:0] = oscCntTarg[9:0] + oscDeltaCode80[7:0]

+ *    oscCnt[9:0] = m*ITcode[15:8] + C[9:0]

+ *    m = (oscCnt80[9:0]-oscCnt25[9:0])/(iTcode80[7:0]-iTcode25[7:0])

+ *    c = oscCnt25[9:0] - m*ITcode25[7:0]

+ *    write oscCnt[9:0] to register 0x97-98

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiCalibrationOsc(SystemDataType *data);

+

+/**

+ * @brief UpiAdcStatus

+ *

+ *  Check ADC status

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiAdcStatus(SystemDataType *data);

+

+/**

+ * @brief UpiLoadBatInfoFromIC

+ *

+ *  Load battery information from uG31xx

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiLoadBatInfoFromIC(SystemDataType *data);

+

+/**

+ * @brief UpiUpdateBatInfoFromIC

+ *

+ *  Update battery information from uG31xx

+ *

+ * @para  data  address of SystemDataType

+ * @para  deltaQ  delta capacity from coulomb counter

+ * @return  _UPI_NULL_

+ */

+extern void UpiUpdateBatInfoFromIC(SystemDataType *data, _sys_s16_ deltaQ);

+

+/**

+ * @brief UpiSaveBatInfoTOIC

+ *

+ *  Save battery information from uG31xx

+ *

+ * @para  data  address of SystemDataType

+ * @return  _UPI_NULL_

+ */

+extern void UpiSaveBatInfoTOIC(SystemDataType *data);

+

+/**

+ * @brief UpiInitAlarm

+ *

+ *  Initialize alarm function of uG3105

+ *

+ * @para  data  address of SystemDataType

+ * @return  NULL

+ */

+extern void UpiInitAlarm(SystemDataType *data);

+

+/**

+ * @brief UpiAlarmStatus

+ *

+ *  Get alarm status

+ *

+ * @para  data  address of SystemDataType

+ * @return  NULL

+ */

+extern _sys_u8_ UpiAlarmStatus(SystemDataType *data);

+

diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_Platform.h b/board/wmt/wmt_battery/gauge/upi/uG31xx_Platform.h
new file mode 100755
index 0000000..f97ee4e
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_Platform.h
@@ -0,0 +1,21 @@
+/**
+ * @filename  uG31xx_Platform.h
+ *
+ *  Define the platform for uG31xx driver
+ *
+ * @author  AllenTeng <allen_teng@upi-semi.com>
+ */
+
+#ifndef	_UG31XX_PLATFORM_H_
+#define	_UG31XX_PLATFORM_H_
+
+//#define uG31xx_OS_WINDOWS
+#define uG31xx_OS_ANDROID
+
+#ifdef  uG31xx_OS_ANDROID
+
+  #define uG31xx_BOOT_LOADER
+  
+#endif  ///< end of uG31xx_OS_ANDROID
+
+#endif	///< end of _UG31XX_PLATFORM_H_
diff --git a/board/wmt/wmt_battery/gauge/upi/uG31xx_Reg_Def.h b/board/wmt/wmt_battery/gauge/upi/uG31xx_Reg_Def.h
new file mode 100755
index 0000000..4de941a
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/uG31xx_Reg_Def.h
@@ -0,0 +1,667 @@
+/**
+ * @filename RegDef.h
+ *
+ *  uG31xx register definition
+ *
+ * @author AllenTeng <allen.kuoliang.teng@gmail.com>
+ * @note register table release date 2012/11/05
+ */
+
+#define INTERNAL_REGISTER_GROUP_A     (0x00)
+  #define REG_MODE                    (INTERNAL_REGISTER_GROUP_A + 0)     ///< 0x00
+    #define MODE_GG_RUN               (1<<4)
+      #define GG_RUN_STANDBY_MODE     (0<<4)
+      #define GG_RUN_OPERATION_MODE   (1<<4)
+  #define REG_CTRL1                   (INTERNAL_REGISTER_GROUP_A + 1)     ///< 0x01
+    #define CTRL1_PORDET              (1<<4)
+      #define PORDET_R_NO_POR         (0<<4)
+      #define PORDET_R_POR            (1<<4)
+      #define PORDET_W_RELEASE        (0<<4)
+      #define PORDET_W_SOFTRESET      (1<<4)
+    #define CTRL1_VTM_EOC             (1<<3)
+    #define CTRL1_GG_EOC              (1<<2)
+    #define CTRL1_GG_RST              (1<<1)
+    #define CTRL1_IO1DATA             (1<<0)
+      #define IO1DATA_R_LOW           (0<<0)
+      #define IO1DATA_R_HIGH          (1<<0)
+      #define IO1DATA_W_LOW           (0<<0)
+      #define IO1DATA_W_HIGH          (1<<0)
+
+#define INTERNAL_REGISTER_GROUP_B     (0x02)
+  #define REG_CHARGE_LOW              (INTERNAL_REGISTER_GROUP_B + 0)     ///< 0x02
+  #define REG_CHARGE_HIGH             (INTERNAL_REGISTER_GROUP_B + 1)     ///< 0x03
+  #define REG_COUNTER_LOW             (INTERNAL_REGISTER_GROUP_B + 2)     ///< 0x04
+  #define REG_COUNTER_HIGH            (INTERNAL_REGISTER_GROUP_B + 3)     ///< 0x05
+  #define REG_AVE_CURRENT_LOW         (INTERNAL_REGISTER_GROUP_B + 4)     ///< 0x06
+  #define REG_AVE_CURRENT_HIGH        (INTERNAL_REGISTER_GROUP_B + 5)     ///< 0x07
+  #define REG_AVE_VBAT1_LOW           (INTERNAL_REGISTER_GROUP_B + 6)     ///< 0x08
+  #define REG_AVE_VBAT1_HIGH          (INTERNAL_REGISTER_GROUP_B + 7)     ///< 0x09
+  #define REG_AVE_IT_LOW              (INTERNAL_REGISTER_GROUP_B + 8)     ///< 0x0A
+  #define REG_AVE_IT_HIGH             (INTERNAL_REGISTER_GROUP_B + 9)     ///< 0x0B
+  #define REG_AVE_OFFSET_CURRENT_LOW  (INTERNAL_REGISTER_GROUP_B + 10)    ///< 0x0C
+  #define REG_AVE_OFFSET_CURRENT_HIGH (INTERNAL_REGISTER_GROUP_B + 11)    ///< 0x0D
+  #define REG_AVE_ET_LOW              (INTERNAL_REGISTER_GROUP_B + 12)    ///< 0x0E
+  #define REG_AVE_ET_HIGH             (INTERNAL_REGISTER_GROUP_B + 13)    ///< 0x0F
+  #define REG_AVE_RID_LOW             (INTERNAL_REGISTER_GROUP_B + 14)    ///< 0x10
+  #define REG_AVE_RID_HIGH            (INTERNAL_REGISTER_GROUP_B + 15)    ///< 0x11
+  #define REG_ALARM1_STATUS           (INTERNAL_REGISTER_GROUP_B + 16)    ///< 0x12
+    #define ALARM1_STATUS_COC_ALARM   (1<<5)
+    #define ALARM1_STATUS_DOC_ALARM   (1<<4)
+    #define ALARM1_STATUS_OIT_ALARM   (1<<3)
+    #define ALARM1_STATUS_UIT_ALARM   (1<<2)
+    #define ALARM1_STATUS_OET_ALARM   (1<<1)
+    #define ALARM1_STATUS_UET_ALARM   (1<<0)
+  #define REG_ALARM2_STATUS           (INTERNAL_REGISTER_GROUP_B + 17)    ///< 0x13
+    #define ALARM2_STATUS_OV3_ALARM   (1<<5)
+    #define ALARM2_STATUS_UV3_ALARM   (1<<4)
+    #define ALARM2_STATUS_OV2_ALARM   (1<<3)
+    #define ALARM2_STATUS_UV2_ALARM   (1<<2)
+    #define ALARM2_STATUS_OV1_ALARM   (1<<1)
+    #define ALARM2_STATUS_UV1_ALARM   (1<<0)
+  #define REG_INTR_STATUS             (INTERNAL_REGISTER_GROUP_B + 18)    ///< 0x14
+    #define INTR_STATUS_CBC_STS32     (1<<7)
+      #define CBC_STS32_ENABLE        (0<<7)
+      #define CBC_STS32_DISABLE       (1<<7)
+    #define INTR_STATUS_CBC_STS21     (1<<6)
+      #define CBC_STS21_ENABLE        (0<<6)
+      #define CBC_STS21_DISABLE       (1<<6)
+    #define INTR_STATUS_STB_STS       (1<<5)
+    #define INTR_STATUS_ET_STS        (1<<4)
+    #define INTR_STATUS_IT_STS        (1<<3)
+    #define INTR_STATUS_RID_STS       (1<<2)
+    #define INTR_STATUS_LVD_STS       (1<<1)
+    #define INTR_STATUS_AL_STS        (1<<0)
+  #define REG_ALARM_EN                (INTERNAL_REGISTER_GROUP_B + 19)    ///< 0x15
+    #define ALARM_EN_COC_ALARM_EN     (1<<7)
+    #define ALARM_EN_DOC_ALARM_EN     (1<<6)
+    #define ALARM_EN_IT_ALARM_EN      (1<<5)
+    #define ALARM_EN_ET_ALARM_EN      (1<<4)
+    #define ALARM_EN_DECIMATE_RST     (1<<3)
+    #define ALARM_EN_V3_ALARM_EN      (1<<2)
+    #define ALARM_EN_V2_ALARM_EN      (1<<1)
+    #define ALARM_EN_V1_ALARM_EN      (1<<0)
+  #define REG_CTRL2                   (INTERNAL_REGISTER_GROUP_B + 20)    ///< 0x16
+    #define CTRL2_IO4DATA             (1<<2)
+      #define IO4DATA_R_LOW           (0<<2)
+      #define IO4DATA_R_HIGH          (1<<2)
+      #define IO4DATA_W_LOW           (0<<2)
+      #define IO4DATA_W_HIGH          (1<<2)
+    #define CTRL2_IO3DATA             (1<<1)
+      #define IO3DATA_R_LOW           (0<<1)
+      #define IO3DATA_R_HIGH          (1<<1)
+      #define IO3DATA_W_LOW           (0<<1)
+      #define IO3DATA_W_HIGH          (1<<1)
+    #define CTRL2_IO2DATA             (1<<0)
+      #define IO2DATA_R_LOW           (0<<0)
+      #define IO2DATA_R_HIGH          (1<<0)
+      #define IO2DATA_W_LOW           (0<<0)
+      #define IO2DATA_W_HIGH          (1<<0)
+
+#define INTERNAL_REGISTER_GROUP_C     (0x20)
+  #define REG_RAM0                    (INTERNAL_REGISTER_GROUP_C + 0)     ///< 0x20
+  #define REG_RAM1                    (INTERNAL_REGISTER_GROUP_C + 1)     ///< 0x21
+  #define REG_RAM2                    (INTERNAL_REGISTER_GROUP_C + 2)     ///< 0x22
+  #define REG_RAM3                    (INTERNAL_REGISTER_GROUP_C + 3)     ///< 0x23
+  #define REG_RAM4                    (INTERNAL_REGISTER_GROUP_C + 4)     ///< 0x24
+  #define REG_RAM5                    (INTERNAL_REGISTER_GROUP_C + 5)     ///< 0x25
+  #define REG_RAM6                    (INTERNAL_REGISTER_GROUP_C + 6)     ///< 0x26
+  #define REG_RAM7                    (INTERNAL_REGISTER_GROUP_C + 7)     ///< 0x27
+  #define REG_RAM8                    (INTERNAL_REGISTER_GROUP_C + 8)     ///< 0x28
+  #define REG_RAM9                    (INTERNAL_REGISTER_GROUP_C + 9)     ///< 0x29
+  #define REG_RAM10                   (INTERNAL_REGISTER_GROUP_C + 10)    ///< 0x2A
+  #define REG_RAM11                   (INTERNAL_REGISTER_GROUP_C + 11)    ///< 0x2B
+  #define REG_RAM12                   (INTERNAL_REGISTER_GROUP_C + 12)    ///< 0x2C
+  #define REG_RAM13                   (INTERNAL_REGISTER_GROUP_C + 13)    ///< 0x2D
+  #define REG_RAM14                   (INTERNAL_REGISTER_GROUP_C + 14)    ///< 0x2E
+  #define REG_RAM15                   (INTERNAL_REGISTER_GROUP_C + 15)    ///< 0x2F
+  #define REG_RAM16                   (INTERNAL_REGISTER_GROUP_C + 16)    ///< 0x30
+  #define REG_RAM17                   (INTERNAL_REGISTER_GROUP_C + 17)    ///< 0x31
+  #define REG_RAM18                   (INTERNAL_REGISTER_GROUP_C + 18)    ///< 0x32
+  #define REG_RAM19                   (INTERNAL_REGISTER_GROUP_C + 19)    ///< 0x33
+  #define REG_RAM20                   (INTERNAL_REGISTER_GROUP_C + 20)    ///< 0x34
+  #define REG_RAM21                   (INTERNAL_REGISTER_GROUP_C + 21)    ///< 0x35
+  #define REG_RAM22                   (INTERNAL_REGISTER_GROUP_C + 22)    ///< 0x36
+  #define REG_RAM23                   (INTERNAL_REGISTER_GROUP_C + 23)    ///< 0x37
+  #define REG_RAM24                   (INTERNAL_REGISTER_GROUP_C + 24)    ///< 0x38
+  #define REG_RAM25                   (INTERNAL_REGISTER_GROUP_C + 25)    ///< 0x39
+  #define REG_RAM26                   (INTERNAL_REGISTER_GROUP_C + 26)    ///< 0x3A
+  #define REG_RAM27                   (INTERNAL_REGISTER_GROUP_C + 27)    ///< 0x3B
+  #define REG_RAM28                   (INTERNAL_REGISTER_GROUP_C + 28)    ///< 0x3C
+  #define REG_RAM29                   (INTERNAL_REGISTER_GROUP_C + 29)    ///< 0x3D
+  #define REG_RAM30                   (INTERNAL_REGISTER_GROUP_C + 30)    ///< 0x3E
+  #define REG_RAM31                   (INTERNAL_REGISTER_GROUP_C + 31)    ///< 0x3F
+
+#define INTERNAL_REGISTER_GROUP_D     (0x40)
+  #define REG_VBAT2_LOW               (INTERNAL_REGISTER_GROUP_D + 0)     ///< 0x40
+  #define REG_VBAT2_HIGH              (INTERNAL_REGISTER_GROUP_D + 1)     ///< 0x41
+  #define REG_VBAT3_LOW               (INTERNAL_REGISTER_GROUP_D + 2)     ///< 0x42
+  #define REG_VBAT3_HIGH              (INTERNAL_REGISTER_GROUP_D + 3)     ///< 0x43
+  #define REG_VBAT1_LOW               (INTERNAL_REGISTER_GROUP_D + 4)     ///< 0x44
+  #define REG_VBAT1_HIGH              (INTERNAL_REGISTER_GROUP_D + 5)     ///< 0x45
+  #define REG_VBAT2_AVE_LOW           (INTERNAL_REGISTER_GROUP_D + 6)     ///< 0x46
+  #define REG_VBAT2_AVE_HIGH          (INTERNAL_REGISTER_GROUP_D + 7)     ///< 0x47
+  #define REG_VBAT3_AVE_LOW           (INTERNAL_REGISTER_GROUP_D + 8)     ///< 0x48
+  #define REG_VBAT3_AVE_HIGH          (INTERNAL_REGISTER_GROUP_D + 9)     ///< 0x49
+  #define REG_V1_LOW                  (INTERNAL_REGISTER_GROUP_D + 10)    ///< 0x4A
+  #define REG_V1_HIGH                 (INTERNAL_REGISTER_GROUP_D + 11)    ///< 0x4B
+  #define REG_V2_LOW                  (INTERNAL_REGISTER_GROUP_D + 12)    ///< 0x4C
+  #define REG_V2_HIGH                 (INTERNAL_REGISTER_GROUP_D + 13)    ///< 0x4D
+  #define REG_V3_LOW                  (INTERNAL_REGISTER_GROUP_D + 14)    ///< 0x4E
+  #define REG_V3_HIGH                 (INTERNAL_REGISTER_GROUP_D + 15)    ///< 0x4F
+  #define REG_INTR_TEMPER_LOW         (INTERNAL_REGISTER_GROUP_D + 16)    ///< 0x50
+  #define REG_INTR_TEMPER_HIGH        (INTERNAL_REGISTER_GROUP_D + 17)    ///< 0x51
+  #define REG_EXTR_TEMPER_LOW         (INTERNAL_REGISTER_GROUP_D + 18)    ///< 0x52
+  #define REG_EXTR_TEMPER_HIGH        (INTERNAL_REGISTER_GROUP_D + 19)    ///< 0x53
+  #define REG_RID_LOW                 (INTERNAL_REGISTER_GROUP_D + 20)    ///< 0x54
+  #define REG_RID_HIGH                (INTERNAL_REGISTER_GROUP_D + 21)    ///< 0x55
+  #define REG_CURRENT_LOW             (INTERNAL_REGISTER_GROUP_D + 22)    ///< 0x56
+  #define REG_CURRENT_HIGH            (INTERNAL_REGISTER_GROUP_D + 23)    ///< 0x57
+  #define REG_ADC1_OFFSET_LOW         (INTERNAL_REGISTER_GROUP_D + 24)    ///< 0x58
+  #define REG_ADC1_OFFSET_HIGH        (INTERNAL_REGISTER_GROUP_D + 25)    ///< 0x59
+
+  #define OTP6_BYTE1                  (INTERNAL_REGISTER_GROUP_D + 48)    ///< 0x70
+    #define AVE_IT25_7_3              (63<<3)
+    #define DELTA_ET_3_2              (3<<1)
+    #define DELTA_VREF_4              (1<<0)
+  #define OTP6_BYTE2                  (INTERNAL_REGISTER_GROUP_D + 49)    ///< 0x71
+    #define AVE_IT25_15_8             (255<<0)
+  #define OTP6_BYTE3                  (INTERNAL_REGISTER_GROUP_D + 50)    ///< 0x72
+    #define AVE_IT80_7_3              (63<<3)
+    #define INDEX_ADC1_200_25_4       (1<<2)
+    #define INDEX_ADC1_100_25_4       (1<<1)
+    #define INDEX_ADC2_200_25_4       (1<<0)
+  #define OTP6_BYTE4                  (INTERNAL_REGISTER_GROUP_D + 51)    ///< 0x73
+    #define AVE_IT80_15_8             (255<<0)
+
+#define INTERNAL_REGISTER_GROUP_E     (0x8F)
+  #define REG_TIMER                   (INTERNAL_REGISTER_GROUP_E + 0)     ///< 0x8F
+    #define TIMER_TIMER_ITSET         (3<<6)
+      #define TIMER_ITSET_4           (0<<6)
+      #define TIMER_ITSET_9           (1<<6)
+      #define TIMER_ITSET_14          (2<<6)
+      #define TIMER_ITSET_19          (3<<6)
+    #define TIMER_TIMER_ETSET         (3<<4)
+      #define TIMER_ETSET_4           (0<<4)
+      #define TIMER_ETSET_9           (1<<4)
+      #define TIMER_ETSET_14          (2<<4)
+      #define TIMER_ETSET_19          (3<<4)
+    #define TIMER_TIMER_VSET          (3<<2)
+      #define TIMER_VSET_4            (0<<2)
+      #define TIMER_VSET_9            (1<<2)
+      #define TIMER_VSET_14           (2<<2)
+      #define TIMER_VSET_19           (3<<2)
+    #define TIMER_TIMER_CSET          (3<<0)
+      #define TIMER_CSET_4            (0<<0)
+      #define TIMER_CSET_9            (1<<0)
+      #define TIMER_CSET_14           (2<<0)
+      #define TIMER_CSET_19           (3<<0)
+  #define REG_CLK_DIVA                (INTERNAL_REGISTER_GROUP_E + 1)     ///< 0x90
+    #define CLK_DIVA_FW_CLK_CDIV      (15<<4)
+      #define FW_CLK_CDIV_31US        (0<<4)
+      #define FW_CLK_CDIV_61US        (1<<4)
+      #define FW_CLK_CDIV_122US       (2<<4)
+      #define FW_CLK_CDIV_244US       (3<<4)
+      #define FW_CLK_CDIV_488US       (4<<4)
+      #define FW_CLK_CDIV_977US       (5<<4)
+      #define FW_CLK_CDIV_2MS         (6<<4)
+      #define FW_CLK_CDIV_4MS         (7<<4)
+      #define FW_CLK_CDIV_8MS         (8<<4)
+      #define FW_CLK_CDIV_16MS        (9<<4)
+      #define FW_CLK_CDIV_31MS        (10<<4)
+      #define FW_CLK_CDIV_62MS        (11<<4)
+      #define FW_CLK_CDIV_125MS       (12<<4)
+      #define FW_CLK_CDIV_250MS       (13<<4)
+      #define FW_CLK_CDIV_500MS       (14<<4)
+      #define FW_CLK_CDIV_1S          (15<<4)
+    #define CLK_DIVA_FW_CLK_VDIV      (15<<0)
+      #define FW_CLK_VDIV_31US        (0<<0)
+      #define FW_CLK_VDIV_61US        (1<<0)
+      #define FW_CLK_VDIV_122US       (2<<0)
+      #define FW_CLK_VDIV_244US       (3<<0)
+      #define FW_CLK_VDIV_488US       (4<<0)
+      #define FW_CLK_VDIV_977US       (5<<0)
+      #define FW_CLK_VDIV_2MS         (6<<0)
+      #define FW_CLK_VDIV_4MS         (7<<0)
+      #define FW_CLK_VDIV_8MS         (8<<0)
+      #define FW_CLK_VDIV_16MS        (9<<0)
+      #define FW_CLK_VDIV_31MS        (10<<0)
+      #define FW_CLK_VDIV_62MS        (11<<0)
+      #define FW_CLK_VDIV_125MS       (12<<0)
+      #define FW_CLK_VDIV_250MS       (13<<0)
+      #define FW_CLK_VDIV_500MS       (14<<0)
+      #define FW_CLK_VDIV_1S          (15<<0)
+  #define REG_CLK_DIVB                (INTERNAL_REGISTER_GROUP_E + 2)     ///< 0x91
+    #define CLK_DIVB_FW_CLK_ETDIV     (15<<4)
+      #define FW_CLK_ETDIV_31US       (0<<4)
+      #define FW_CLK_ETDIV_61US       (1<<4)
+      #define FW_CLK_ETDIV_122US      (2<<4)
+      #define FW_CLK_ETDIV_244US      (3<<4)
+      #define FW_CLK_ETDIV_488US      (4<<4)
+      #define FW_CLK_ETDIV_977US      (5<<4)
+      #define FW_CLK_ETDIV_2MS        (6<<4)
+      #define FW_CLK_ETDIV_4MS        (7<<4)
+      #define FW_CLK_ETDIV_8MS        (8<<4)
+      #define FW_CLK_ETDIV_16MS       (9<<4)
+      #define FW_CLK_ETDIV_31MS       (10<<4)
+      #define FW_CLK_ETDIV_62MS       (11<<4)
+      #define FW_CLK_ETDIV_125MS      (12<<4)
+      #define FW_CLK_ETDIV_250MS      (13<<4)
+      #define FW_CLK_ETDIV_500MS      (14<<4)
+      #define FW_CLK_ETDIV_1S         (15<<4)
+    #define CLK_DIVB_FW_CLK_ITDIV     (15<<0)
+      #define FW_CLK_ITDIV_31US       (0<<0)
+      #define FW_CLK_ITDIV_61US       (1<<0)
+      #define FW_CLK_ITDIV_122US      (2<<0)
+      #define FW_CLK_ITDIV_244US      (3<<0)
+      #define FW_CLK_ITDIV_488US      (4<<0)
+      #define FW_CLK_ITDIV_977US      (5<<0)
+      #define FW_CLK_ITDIV_2MS        (6<<0)
+      #define FW_CLK_ITDIV_4MS        (7<<0)
+      #define FW_CLK_ITDIV_8MS        (8<<0)
+      #define FW_CLK_ITDIV_16MS       (9<<0)
+      #define FW_CLK_ITDIV_31MS       (10<<0)
+      #define FW_CLK_ITDIV_62MS       (11<<0)
+      #define FW_CLK_ITDIV_125MS      (12<<0)
+      #define FW_CLK_ITDIV_250MS      (13<<0)
+      #define FW_CLK_ITDIV_500MS      (14<<0)
+      #define FW_CLK_ITDIV_1S         (15<<0)
+  #define REG_INTR_CTRL_D             (INTERNAL_REGISTER_GROUP_E + 3)     ///< 0x92
+    #define INTR_CTRL_D_GPIO4_SEL     (7<<3)
+      #define GPIO4_SEL_GPIO1         (0<<3)
+      #define GPIO4_SEL_ALARM         (1<<3)
+      #define GPIO4_SEL_CBC_EN21      (2<<3)
+      #define GPIO4_SEL_CBC_EN32      (3<<3)
+      #define GPIO4_SEL_PWM           (4<<3)
+      #define GPIO4_SEL_ADC1_D        (6<<3)
+      #define GPIO4_SEL_ADC2_D        (7<<3)
+    #define INTR_CTRL_D_GPIO3_SEL     (7<<0)
+      #define GPIO3_SEL_GPIO1         (0<<0)
+      #define GPIO3_SEL_ALARM         (1<<0)
+      #define GPIO3_SEL_CBC_EN21      (2<<0)
+      #define GPIO3_SEL_CBC_EN32      (3<<0)
+      #define GPIO3_SEL_PWM           (4<<0)
+      #define GPIO3_SEL_ADC1_D        (6<<0)
+      #define GPIO3_SEL_ADC2_D        (7<<0)
+  #define OSCTUNE_J1                  (INTERNAL_REGISTER_GROUP_E + 4)     ///< 0x93
+    #define OSCTUNE_J_LOW             (255<<0)
+  #define OSCTUNE_J2                  (INTERNAL_REGISTER_GROUP_E + 5)     ///< 0x94
+    #define OSCTUNE_J_HIGH            (3<<0)
+  #define OSCTUNE_K1                  (INTERNAL_REGISTER_GROUP_E + 6)     ///< 0x95
+    #define OSCTUNE_K_LOW             (255<<0)
+  #define OSCTUNE_K2                  (INTERNAL_REGISTER_GROUP_E + 7)     ///< 0x96
+    #define OSCTUNE_K_HIGH            (3<<0)
+  #define OSCTUNE_CNTA                (INTERNAL_REGISTER_GROUP_E + 8)     ///< 0x97
+    #define OSCTUNE_CNT_LOW           (255<<0)
+  #define OSCTUNE_CNTB                (INTERNAL_REGISTER_GROUP_E + 9)     ///< 0x98
+    #define OSCTUNE_CNT_HIGH          (3<<0)
+  #define ADC1_TARGET_A               (INTERNAL_REGISTER_GROUP_E + 10)    ///< 0x99
+    #define TARGET_A_LOW              (255<<0)
+  #define ADC1_TARGET_B               (INTERNAL_REGISTER_GROUP_E + 11)    ///< 0x9A
+    #define TARGET_A_HIGH             (3<<0)
+  #define REG_INTR_CTRL_A             (INTERNAL_REGISTER_GROUP_E + 12)    ///< 0x9B
+    #define INTR_CTRL_A_GPIO2_SEL     (7<<5)
+      #define GPIO2_SEL_GPIO1         (0<<5)
+      #define GPIO2_SEL_ALARM         (1<<5)
+      #define GPIO2_SEL_CBC_EN21      (2<<5)
+      #define GPIO2_SEL_CBC_EN32      (3<<5)
+      #define GPIO2_SEL_PWM           (4<<5)
+    #define INTR_CTRL_A_GPIO1_SEL     (7<<2)
+      #define GPIO1_SEL_GPIO1         (0<<2)
+      #define GPIO1_SEL_ALARM         (1<<2)
+      #define GPIO1_SEL_CBC_EN21      (2<<2)
+      #define GPIO1_SEL_CBC_EN32      (3<<2)
+      #define GPIO1_SEL_PWM           (4<<2)
+      #define GPIO1_SEL_OSCOUT        (7<<2)
+    #define INTR_CTRL_A_ADC2_EN       (1<<1)
+    #define INTR_CTRL_A_ADC1_EN       (1<<0)
+  #define REG_INTR_CTRL_B             (INTERNAL_REGISTER_GROUP_E + 13)    ///< 0x9C
+    #define INTR_CTRL_B_OSC_CNT_EN    (1<<7)
+    #define INTR_CTRL_B_PWM_EN        (1<<6)
+    #define INTR_CTRL_B_CBC_32_EN     (1<<5)
+    #define INTR_CTRL_B_CBC_21_EN     (1<<4)
+    #define INTR_CTRL_B_STB_EN        (1<<3)
+    #define INTR_CTRL_B_ET_EN         (1<<2)
+    #define INTR_CTRL_B_IT_EN         (1<<1)
+    #define INTR_CTRL_B_RID_EN        (1<<0)
+  #define REG_ITNR_CTRL_C             (INTERNAL_REGISTER_GROUP_E + 14)    ///< 0x9D
+    #define INTR_CTRL_C_BGRCAL_FINISH (1<<7)
+    #define INTR_CTRL_C_FW_V_DIVIDE   (1<<6)
+    #define INTR_CTRL_C_BGRCAL_START  (1<<5)
+    #define INTR_CTRL_C_BGR_CALEN     (1<<4)
+    #define INTR_CTRL_C_PWM_SET       (3<<2)
+      #define PWM_SET_32K             (0<<2)
+      #define PWM_SET_16K             (1<<2)
+      #define PWM_SET_8K              (2<<2)
+      #define PWM_SET_4K              (3<<2)
+    #define INTR_CTRL_C_TIMER_SET     (3<<0)
+      #define TIMER_SET_OV_UV         (0<<0)
+      #define TIMER_SET_OC_UC         (1<<0)
+      #define TIMER_SET_OIT_UIT       (2<<0)
+      #define TIMER_SET_OET_UET       (3<<0)
+  #define REG_CELL_EN                 (INTERNAL_REGISTER_GROUP_E + 15)    ///< 0x9E
+    #define CELL_EN_APPLICATION       (7<<2)
+      #define APPLICATION_UG3100      (0<<2)
+      #define APPLICATION_UG3101      (1<<2)
+      #define APPLICATION_UG3102      (2<<2)
+      #define APPLICATION_UG3103_2    (4<<2)
+      #define APPLICATION_UG3103_3    (5<<2)
+    #define CELL_EN1                  (1<<1)
+    #define CELL_EN0                  (1<<0)
+
+#define INTERNAL_REGISTER_GROUP_F     (0x9F)
+  #define REG_COC_LOW                 (INTERNAL_REGISTER_GROUP_F + 0)     ///< 0x9F
+  #define REG_COC_HIGH                (INTERNAL_REGISTER_GROUP_F + 1)     ///< 0xA0
+  #define REG_DOC_LOW                 (INTERNAL_REGISTER_GROUP_F + 2)     ///< 0xA1
+  #define REG_DOC_HIGH                (INTERNAL_REGISTER_GROUP_F + 3)     ///< 0xA2
+  #define REG_UC_LOW                  (INTERNAL_REGISTER_GROUP_F + 4)     ///< 0xA3
+  #define REG_UC_HIGH                 (INTERNAL_REGISTER_GROUP_F + 5)     ///< 0xA4
+  #define REG_OV1_LOW                 (INTERNAL_REGISTER_GROUP_F + 6)     ///< 0xA5
+  #define REG_OV1_HIGH                (INTERNAL_REGISTER_GROUP_F + 7)     ///< 0xA6
+  #define REG_UV1_LOW                 (INTERNAL_REGISTER_GROUP_F + 8)     ///< 0xA7
+  #define REG_UV1_HIGH                (INTERNAL_REGISTER_GROUP_F + 9)     ///< 0xA8
+  #define REG_OV2_LOW                 (INTERNAL_REGISTER_GROUP_F + 10)    ///< 0xA9
+  #define REG_OV2_HIGH                (INTERNAL_REGISTER_GROUP_F + 11)    ///< 0xAA
+  #define REG_UV2_LOW                 (INTERNAL_REGISTER_GROUP_F + 12)    ///< 0xAB
+  #define REG_UV2_HIGH                (INTERNAL_REGISTER_GROUP_F + 13)    ///< 0xAC
+  #define REG_OV3_LOW                 (INTERNAL_REGISTER_GROUP_F + 14)    ///< 0xAD
+  #define REG_OV3_HIGH                (INTERNAL_REGISTER_GROUP_F + 15)    ///< 0xAE
+  #define REG_UV3_LOW                 (INTERNAL_REGISTER_GROUP_F + 16)    ///< 0xAF
+  #define REG_UV3_HIGH                (INTERNAL_REGISTER_GROUP_F + 17)    ///< 0xB0
+  #define REG_OVP_LOW                 (INTERNAL_REGISTER_GROUP_F + 18)    ///< 0xB1
+  #define REG_OVP_HIGH                (INTERNAL_REGISTER_GROUP_F + 19)    ///< 0xB2
+  #define REG_UVP_LOW                 (INTERNAL_REGISTER_GROUP_F + 20)    ///< 0xB3
+  #define REG_UVP_HIGH                (INTERNAL_REGISTER_GROUP_F + 21)    ///< 0xB4
+  #define REG_INTR_OVER_TEMP_LOW      (INTERNAL_REGISTER_GROUP_F + 22)    ///< 0xB5
+  #define REG_INTR_OVER_TEMP_HIGH     (INTERNAL_REGISTER_GROUP_F + 23)    ///< 0xB6
+  #define REG_INTR_UNDER_TEMP_LOW     (INTERNAL_REGISTER_GROUP_F + 24)    ///< 0xB7
+  #define REG_INTR_UNDER_TEMP_HIGH    (INTERNAL_REGISTER_GROUP_F + 25)    ///< 0xB8
+  #define REG_EXTR_OVER_TEMP_LOW      (INTERNAL_REGISTER_GROUP_F + 26)    ///< 0xB9
+  #define REG_EXTR_OVER_TEMP_HIGH     (INTERNAL_REGISTER_GROUP_F + 27)    ///< 0xBA
+  #define REG_EXTR_UNDER_TEMP_LOW     (INTERNAL_REGISTER_GROUP_F + 28)    ///< 0xBB
+  #define REG_EXTR_UNDER_TEMP_HIGH    (INTERNAL_REGISTER_GROUP_F + 29)    ///< 0xBC
+  #define REG_CBC21_LOW               (INTERNAL_REGISTER_GROUP_F + 30)    ///< 0xBD
+  #define REG_CBC21_HIGH              (INTERNAL_REGISTER_GROUP_F + 31)    ///< 0xBE
+  #define REG_CBC32_LOW               (INTERNAL_REGISTER_GROUP_F + 32)    ///< 0xBF
+  #define REG_CBC32_HIGH              (INTERNAL_REGISTER_GROUP_F + 33)    ///< 0xC0
+
+#define INTERNAL_REGISTER_GROUP_G     (0xC1)
+  #define REG_FW_CTRL                 (INTERNAL_REGISTER_GROUP_G + 0)     ///< 0xC1
+    #define FW_CTRL_CHOP2_EN          (1<<3)
+    #define FW_CTRL_CHOPPING2         (1<<2)
+    #define FW_CTRL_CHOP1_EN          (1<<1)
+    #define FW_CTRL_CHOPPING1         (1<<0)
+  #define REG_OTP_CTRL                (INTERNAL_REGISTER_GROUP_G + 1)     ///< 0xC2
+    #define OTP_CTRL_IT_CAL80         (1<<7)
+    #define OTP_CTRL_IT_CAL25         (1<<6)
+    #define OTP_CTRL_ADC2_200MV       (1<<5)
+    #define OTP_CTRL_ADC2_100MV       (1<<4)
+    #define OTP_CTRL_ADC1_200MV       (1<<3)
+    #define OTP_CTRL_ADC1_100MV       (1<<2)
+    #define OTP_CTRL_OTP_PTM          (3<<0)
+  #define REG_OTP_PPROG_ON            (INTERNAL_REGISTER_GROUP_G + 2)     ///< 0xC3
+    #define OTP_PPROG_ON_VALUE        (0xDD)
+  #define REG_OTP_PPROG_OFF           (INTERNAL_REGISTER_GROUP_G + 3)     ///< 0xC4
+    #define OTP_PPROG_OFF_VALUE       (0xDE)
+
+#define INTERNAL_REGISTER_GROUP_H     (0xC5)
+  #define REG_ADC_CTR_A               (INTERNAL_REGISTER_GROUP_H + 0)     ///< 0xC5
+    #define ADC_CTR_A_SET_A           (3<<6)
+      #define SET_A_CURRENT           (0<<6)
+      #define SET_A_ET                (1<<6)
+      #define SET_A_RID_IN            (2<<6)
+      #define SET_A_IT                (3<<6)
+    #define ADC_CTR_A_SET_B           (3<<4)
+      #define SET_B_CURRENT           (0<<4)
+      #define SET_B_ET                (1<<4)
+      #define SET_B_RID_IN            (2<<4)
+      #define SET_B_IT                (3<<4)
+    #define ADC_CTR_A_SET_C           (3<<2)
+      #define SET_C_CURRENT           (0<<2)
+      #define SET_C_ET                (1<<2)
+      #define SET_C_RID_IN            (2<<2)
+      #define SET_C_IT                (3<<2)
+    #define ADC_CTR_A_SET_D           (3<<0)
+      #define SET_D_CURRENT           (0<<0)
+      #define SET_D_ET                (1<<0)
+      #define SET_D_RID_IN            (2<<0)
+      #define SET_D_IT                (3<<0)
+  #define REG_ADC_CTR_B               (INTERNAL_REGISTER_GROUP_H + 1)     ///< 0xC6
+    #define ADC_CTR_B_SET_E           (3<<6)
+      #define SET_E_CURRENT           (0<<6)
+      #define SET_E_ET                (1<<6)
+      #define SET_E_RID_IN            (2<<6)
+      #define SET_E_IT                (3<<6)
+    #define ADC_CTR_B_SET_F           (3<<4)
+      #define SET_F_CURRENT           (0<<4)
+      #define SET_F_ET                (1<<4)
+      #define SET_F_RID_IN            (2<<4)
+      #define SET_F_IT                (3<<4)
+    #define ADC_CTR_B_SET_G           (3<<2)
+      #define SET_G_CURRENT           (0<<2)
+      #define SET_G_ET                (1<<2)
+      #define SET_G_RID_IN            (2<<2)
+      #define SET_G_IT                (3<<2)
+    #define ADC_CTR_B_SET_H           (3<<0)
+      #define SET_H_CURRENT           (0<<0)
+      #define SET_H_ET                (1<<0)
+      #define SET_H_RID_IN            (2<<0)
+      #define SET_H_IT                (3<<0)
+  #define REG_ADC_CTR_C               (INTERNAL_REGISTER_GROUP_H + 2)     ///< 0xC7
+    #define ADC_CTR_C_SET_I           (3<<6)
+      #define SET_I_CURRENT           (0<<6)
+      #define SET_I_ET                (1<<6)
+      #define SET_I_RID_IN            (2<<6)
+      #define SET_I_IT                (3<<6)
+    #define ADC_CTR_C_SET_J           (3<<4)
+      #define SET_J_CURRENT           (0<<4)
+      #define SET_J_ET                (1<<4)
+      #define SET_J_RID_IN            (2<<4)
+      #define SET_J_IT                (3<<4)
+    #define ADC_CTR_C_SET_K           (3<<2)
+      #define SET_K_CURRENT           (0<<2)
+      #define SET_K_ET                (1<<2)
+      #define SET_K_RID_IN            (2<<2)
+      #define SET_K_IT                (3<<2)
+    #define ADC_CTR_C_SET_L           (3<<0)
+      #define SET_L_CURRENT           (0<<0)
+      #define SET_L_ET                (1<<0)
+      #define SET_L_RID_IN            (2<<0)
+      #define SET_L_IT                (3<<0)
+  #define REG_ADC_CTR_D               (INTERNAL_REGISTER_GROUP_H + 3)     ///< 0xC8
+    #define ADC_CTR_D_SET_M           (3<<6)
+      #define SET_M_CURRENT           (0<<6)
+      #define SET_M_ET                (1<<6)
+      #define SET_M_RID_IN            (2<<6)
+      #define SET_M_IT                (3<<6)
+    #define ADC_CTR_D_SET_N           (3<<4)
+      #define SET_N_CURRENT           (0<<4)
+      #define SET_N_ET                (1<<4)
+      #define SET_N_RID_IN            (2<<4)
+      #define SET_N_IT                (3<<4)
+    #define ADC_CTR_D_SET_O           (3<<2)
+      #define SET_O_CURRENT           (0<<2)
+      #define SET_O_ET                (1<<2)
+      #define SET_O_RID_IN            (2<<2)
+      #define SET_O_IT                (3<<2)
+    #define ADC_CTR_D_SET_P           (3<<0)
+      #define SET_P_CURRENT           (0<<0)
+      #define SET_P_ET                (1<<0)
+      #define SET_P_RID_IN            (2<<0)
+      #define SET_P_IT                (3<<0)
+  #define REG_ADC_V1                  (INTERNAL_REGISTER_GROUP_H + 4)     ///< 0xC9
+    #define ADC_CTR_V1_SET_V1         (3<<6)
+      #define SET_V1_GND              (0<<6)
+      #define SET_V1_VBAT1            (1<<6)
+      #define SET_V1_VBAT2            (2<<6)
+      #define SET_V1_VBAT3            (3<<6)
+    #define ADC_CTR_V1_SET_V2         (3<<4)
+      #define SET_V2_GND              (0<<4)
+      #define SET_V2_VBAT1            (1<<4)
+      #define SET_V2_VBAT2            (2<<4)
+      #define SET_V2_VBAT3            (3<<4)
+    #define ADC_CTR_V1_SET_V3         (3<<2)
+      #define SET_V3_GND              (0<<2)
+      #define SET_V3_VBAT1            (1<<2)
+      #define SET_V3_VBAT2            (2<<2)
+      #define SET_V3_VBAT3            (3<<2)
+    #define ADC_CTR_V1_SET_V4         (3<<0)
+      #define SET_V4_GND              (0<<0)
+      #define SET_V4_VBAT1            (1<<0)
+      #define SET_V4_VBAT2            (2<<0)
+      #define SET_V4_VBAT3            (3<<0)
+  #define REG_ADC_V2                  (INTERNAL_REGISTER_GROUP_H + 5)     ///< 0xCA
+    #define ADC_CTR_V2_SET_V5         (3<<6)
+      #define SET_V5_GND              (0<<6)
+      #define SET_V5_VBAT1            (1<<6)
+      #define SET_V5_VBAT2            (2<<6)
+      #define SET_V5_VBAT3            (3<<6)
+    #define ADC_CTR_V2_SET_V6         (3<<4)
+      #define SET_V6_GND              (0<<4)
+      #define SET_V6_VBAT1            (1<<4)
+      #define SET_V6_VBAT2            (2<<4)
+      #define SET_V6_VBAT3            (3<<4)
+    #define ADC_CTR_V2_SET_V7         (3<<2)
+      #define SET_V7_GND              (0<<2)
+      #define SET_V7_VBAT1            (1<<2)
+      #define SET_V7_VBAT2            (2<<2)
+      #define SET_V7_VBAT3            (3<<2)
+    #define ADC_CTR_V2_SET_V8         (3<<0)
+      #define SET_V8_GND              (0<<0)
+      #define SET_V8_VBAT1            (1<<0)
+      #define SET_V8_VBAT2            (2<<0)
+      #define SET_V8_VBAT3            (3<<0)
+  #define REG_ADC_V3                  (INTERNAL_REGISTER_GROUP_H + 6)     ///< 0xCB
+    #define ADC_CTR_V3_SET_V9         (3<<6)
+      #define SET_V9_GND              (0<<6)
+      #define SET_V9_VBAT1            (1<<6)
+      #define SET_V9_VBAT2            (2<<6)
+      #define SET_V9_VBAT3            (3<<6)
+    #define ADC_CTR_V3_SET_V10        (3<<4)
+      #define SET_V10_GND             (0<<4)
+      #define SET_V10_VBAT1           (1<<4)
+      #define SET_V10_VBAT2           (2<<4)
+      #define SET_V10_VBAT3           (3<<4)
+    #define ADC_CTR_V3_SET_V11        (3<<2)
+      #define SET_V11_GND             (0<<2)
+      #define SET_V11_VBAT1           (1<<2)
+      #define SET_V11_VBAT2           (2<<2)
+      #define SET_V11_VBAT3           (3<<2)
+    #define ADC_CTR_V3_SET_V12        (3<<0)
+      #define SET_V12_GND             (0<<0)
+      #define SET_V12_VBAT1           (1<<0)
+      #define SET_V12_VBAT2           (2<<0)
+      #define SET_V12_VBAT3           (3<<0)
+
+#define INTERNAL_REGISTER_GROUP_I     (0xCC)
+  #define KCONFIG_D1                  (INTERNAL_REGISTER_GROUP_I + 0)     ///< 0xCC
+    #define KCONFIG_D_LOW             (255<<0)
+  #define KCONFIG_D2                  (INTERNAL_REGISTER_GROUP_I + 1)     ///< 0xCD
+    #define KCONFIG_D_HIGH            (255<<0)
+
+#define INTERNAL_REGISTER_GROUP_J     (0xCE)
+  #define KCONFIG_A1                  (INTERNAL_REGISTER_GROUP_J + 0)     ///< 0xCE
+    #define KCONFIG_A1_KGG1_OSC       (255<<0)
+  #define KCONFIG_A2                  (INTERNAL_REGISTER_GROUP_J + 1)     ///< 0xCF
+    #define KCONFIG_A2_KGG1_DSM2_L    (255<<0)
+  #define KCONFIG_A3                  (INTERNAL_REGISTER_GROUP_J + 2)     ///< 0xD0
+    #define KCONFIG_A3_KGG1_DSM2_M    (255<<0)
+  #define KCONFIG_A4                  (INTERNAL_REGISTER_GROUP_J + 3)     ///< 0xD1
+    #define KCONFIG_A4_KGG1_DSM2_H    (255<<0)
+  #define KCONFIG_A5                  (INTERNAL_REGISTER_GROUP_J + 4)     ///< 0xD2
+    #define KCONFIG_A5_KGG1_DSM1_L    (255<<0)
+  #define KCONFIG_A6                  (INTERNAL_REGISTER_GROUP_J + 5)     ///< 0xD3
+    #define KCONFIG_A6_KGG1_DSM1_M    (255<<0)
+  #define KCONFIG_A7                  (INTERNAL_REGISTER_GROUP_J + 6)     ///< 0xD4
+    #define KCONFIG_A7_KGG1_DSM1_H    (255<<0)
+  #define KCONFIG_A8                  (INTERNAL_REGISTER_GROUP_J + 7)     ///< 0xD5
+    #define KCONFIG_A8_KGG1_MBIAS_L   (255<<0)
+  #define KCONFIG_A9                  (INTERNAL_REGISTER_GROUP_J + 8)     ///< 0xD6
+    #define KCONFIG_A9_KGG1_MBIAS_H   (3<<0)
+
+  #define KCONFIG_H1                  (INTERNAL_REGISTER_GROUP_J + 9)     ///< 0xD7
+    #define KCONFIG_H1_KGG1_IDO_LOW   (15<<4)
+    #define KCONFIG_H1_KGG1_MBIAS     (3<<2)
+    #define KCONFIG_H1_KGG1_OSC       (3<<2)
+  #define KCONFIG_H2                  (INTERNAL_REGISTER_GROUP_J + 10)    ///< 0xD8
+    #define KCONFIG_H2_KGG1_IDO_HIGH  (255<<0)
+  #define KCONFIG_H3                  (INTERNAL_REGISTER_GROUP_J + 11)    ///< 0xD9
+    #define KCONFIG_H3_KGG1_BGAP_LOW  (63<<2)
+    #define KCONFIG_H3_KGG1_DSM2      (3<<0)
+  #define KCONFIG_H4                  (INTERNAL_REGISTER_GROUP_J + 12)    ///< 0xDA
+    #define KCONFIG_H3_KGG1_BGAP_HIGH (127<<0)
+  #define KCONFIG_H5                  (INTERNAL_REGISTER_GROUP_J + 13)    ///< 0xDB
+    #define KCONFIG_H5_WIRE_V_DIVIDE  (1<<6)
+    #define KCONFIG_H5_KGG1_BGAP_CAL  (63<<0)
+
+#define INTERNAL_REGISTER_GROUP_K     (0xDC)
+  #define KCONFIG_CAL1                (INTERNAL_REGISTER_GROUP_K + 0)     ///< 0xDC
+    #define KCONFIG_CAL1_KGG1_OSC_L   (255<<0)
+  #define KCONFIG_CAL2                (INTERNAL_REGISTER_GROUP_K + 1)     ///< 0xDD
+    #define KCONFIG_CAL2_KGG1_OSC_H   (255<<0)
+  #define KCONFIG_CAL3                (INTERNAL_REGISTER_GROUP_K + 2)     ///< 0xDE
+    #define KCONFIG_CAL3_KGG1_DSM2    (255<<0)
+  #define KCONFIG_CAL4                (INTERNAL_REGISTER_GROUP_K + 3)     ///< 0xDF
+    #define KCONFIG_CAL4_KGG1_DSM1    (255<<0)
+
+#define INTERNAL_REGISTER_GROUP_L     (0xE0)
+  #define OTP1_BYTE1                  (INTERNAL_REGISTER_GROUP_L + 0)     ///< 0xE0
+    #define DELTA_VREF_3_0            (15<<4)
+    #define INDEX_ADC1_200_25_3_0     (15<<0)
+  #define OTP1_BYTE2                  (INTERNAL_REGISTER_GROUP_L + 1)     ///< 0xE1
+    #define FT_IT_6_3                 (15<<4)
+    #define INDEX_ADC1_100_25_3_0     (15<<0)
+  #define OTP1_BYTE3                  (INTERNAL_REGISTER_GROUP_L + 2)     ///< 0xE2
+    #define FT_IT_10_7                (15<<4)
+    #define INDEX_ADC2_200_25_3_0     (15<<0)
+  #define OTP1_BYTE4                  (INTERNAL_REGISTER_GROUP_L + 3)     ///< 0xE3
+    #define FT_IT_14_11               (15<<4)
+    #define INDEX_ADC2_100_25_3_0     (15<<0)
+
+  #define OTP2_BYTE1                  (INTERNAL_REGISTER_GROUP_L + 16)    ///< 0xF0
+    #define DELTA_ET_1                (1<<7)
+    #define INDEX_ADC2_100_25_4       (1<<6)
+    #define DELTA_ET_0                (1<<5)
+    #define PRODUCT_TYPE              (3<<3)
+    #define ITDELTACODE25_10_8        (7<<0)
+  #define OTP2_BYTE2                  (INTERNAL_REGISTER_GROUP_L + 17)    ///< 0xF1
+    #define ITDELTACODE25_7_0         (255<<0)
+  #define OTP2_BYTE3                  (INTERNAL_REGISTER_GROUP_L + 18)    ///< 0xF2
+    #define OTP_CELL_EN               (31<<3)
+    #define ITDELTACODE80_10_8        (7<<0)
+  #define OTP2_BYTE4                  (INTERNAL_REGISTER_GROUP_L + 19)    ///< 0xF3
+    #define ITDELTACODE80_7_0         (255<<0)
+  
+  #define OTP3_BYTE1                  (INTERNAL_REGISTER_GROUP_L + 20)    ///< 0xF4
+    #define DEVADDR_9_0               (63<<2)
+    #define ADC1DELTACODE25_200_9     (1<<1)
+    #define ADC1DELTACODE25_200_8     (1<<0)
+  #define OTP3_BYTE2                  (INTERNAL_REGISTER_GROUP_L + 21)    ///< 0xF5
+    #define BGRTUNE_5_0               (63<<2)
+    #define ADC1DELTACODE80_200_9_8   (3<<0)
+  #define OTP3_BYTE3                  (INTERNAL_REGISTER_GROUP_L + 22)    ///< 0xF6
+    #define OSCDELTACODE25            (255<<0)
+  #define OTP3_BYTE4                  (INTERNAL_REGISTER_GROUP_L + 23)    ///< 0xF7
+    #define OSCDELTACODE80            (255<<0)
+
+  #define OTP4_BYTE1                  (INTERNAL_REGISTER_GROUP_L + 24)    ///< 0xF8
+    #define ADC1DELTACODE25_200_7_0   (255<<0)
+  #define OTP4_BYTE2                  (INTERNAL_REGISTER_GROUP_L + 25)    ///< 0xF9
+    #define ADC1DELTACODE80_200_7_0   (255<<0)
+  #define OTP4_BYTE3                  (INTERNAL_REGISTER_GROUP_L + 26)    ///< 0xFA
+    #define ADC1DELTACODE25_100_7_0   (255<<0)
+  #define OTP4_BYTE4                  (INTERNAL_REGISTER_GROUP_L + 27)    ///< 0xFB
+    #define ADC1DELTACODE80_100_7_0   (255<<0)
+
+  #define OTP5_BYTE1                  (INTERNAL_REGISTER_GROUP_L + 28)    ///< 0xFC
+    #define ADC2DELTACODE25_100_6     (1<<7)
+    #define ADC2DELTACODE25_100_5_0   (63<<1)
+    #define ADC1DELTACODE25_100_8     (1<<0)
+  #define OTP5_BYTE2                  (INTERNAL_REGISTER_GROUP_L + 29)    ///< 0xFD
+    #define ADC2DELTACODE80_100_6_0   (127<<1)
+    #define ADC1DELTACODE80_100_8     (1<<0)
+  #define OTP5_BYTE3                  (INTERNAL_REGISTER_GROUP_L + 30)    ///< 0xFE
+    #define ADC2DELTACODE25_200_7     (1<<7)
+    #define ADC2DELTACODE25_200_6_0   (127<<0)
+  #define OTP5_BYTE4                  (INTERNAL_REGISTER_GROUP_L + 31)    ///< 0xFF
+    #define ADC2DELTACODE80_200_7_0   (255<<0)
+
diff --git a/board/wmt/wmt_battery/gauge/upi/ug31xx_boot.c b/board/wmt/wmt_battery/gauge/upi/ug31xx_boot.c
new file mode 100755
index 0000000..b92ea75
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ug31xx_boot.c
@@ -0,0 +1,804 @@
+/**
+ * @filename	ug31xx_boot.c
+ *
+ *	uG31xx operation in bootloader
+ *
+ * @author	AllenTeng <allen_teng@upi-semi.com>
+ */
+
+#include <common.h>
+#ifdef CONFIG_BATT_UPI
+#include <asm/errno.h>
+//#include <app.h>
+//#include <debug.h>
+//#include <arch/arm.h>
+//#include <dev/udc.h>
+//#include <linux/string.h>
+//#include <kernel/thread.h>
+//#include <arch/ops.h>
+//#include <malloc.h>
+
+//#include <stdarg.h>
+
+#include "../../wmt_battery.h"
+
+#include "ug31xx_boot_i2c.h"
+#include "ug31xx_boot.h"
+#include "uG31xx_API.h"
+
+#define	UG31XX_BOOT_VERSION	(12)
+
+#define	UG31XX_BOOT_STATUS_FCC_IS_0		(1<<0)
+#define	UG31XX_BOOT_STATUS_IC_IS_NOT_ACTIVE	(1<<1)
+#define	UG31XX_BOOT_STATUS_WRONG_PRODUCT_TYPE	(1<<2)
+#define   DPRINTF(x,args...)	printf("UG31xx " x , ##args)
+
+extern void ug31xx_init_i2c(int i2c_dev);
+
+UG31xxDataType	ug31_data;
+
+typedef struct UG31xxDataInternalST {
+	UG31xxDataType	*info;
+
+	CELL_PARAMETER	ggbParameter;
+	CELL_TABLE	ggbCellTable;
+
+	OtpDataType 	otpData;
+	MeasDataType	measData;
+	SystemDataType	sysData;
+
+	int		tpTime;
+	int		status;
+} UG31xxDataInternalType;
+
+#undef bool
+typedef enum _bool {false, true} bool;
+
+#include "ggb/ug31xx_ggb_data_uboot_wms8309_wm8_20130820_110949.h"
+#include "ggb/ug31xx_ggb_data_uboot_wms8309_c7_20130725_164935.h"
+#include "ggb/ug31xx_ggb_data_uboot_wms8309_c7_20130910_130553.h"
+#include "ggb/ug31xx_ggb_data_uboot_wms7320_20130718_200031.h"
+#include "ggb/ug31xx_ggb_data_uboot_cw500_20130801_103638.h"
+#include "ggb/ug31xx_ggb_data_uboot_mp718_20131004_070110.h"
+#include "ggb/ug31xx_ggb_data_uboot_t73v_20131120_001204.h"
+
+enum {
+	UG31XX_ID_3105,
+	UG31XX_ID_3102,
+};
+
+static int g_ug31xx_id;
+
+struct ggb_info {
+	char *name;
+	char *data;
+};
+
+/* Extern Function */
+static struct ggb_info ggb_arrays[] = {
+	{
+		.name = "wms8309wm8",
+		.data = FactoryGGBXFile_wms8309_wm8,
+	}, {
+		.name = "wms7320",
+		.data = FactoryGGBXFile_wms7320,
+	}, {
+		.name = "wms8309c7_3900mAh",
+		.data = FactoryGGBXFile_wms8309_c7_3900mAh,
+	}, {
+		.name = "wms8309c7_3000mAh",
+		.data = FactoryGGBXFile_wms8309_c7_3000mAh,
+	}, {
+		.name = "cw500",
+		.data = FactoryGGBXFile_cw500, 
+	}, {
+		.name = "mp718",
+		.data = FactoryGGBXFile_mp718,
+	}, {
+		.name = "t73v",
+		.data = FactoryGGBXFile_t73v,
+	},
+};
+
+struct ug31xx_param {
+	int i2c_adapter;
+	int external_temperature;
+	int charge_temperature_range[2];
+	struct ggb_info *ggb;
+};
+
+static struct ug31xx_param ug31xx_param = {
+	.i2c_adapter = 1,
+	.external_temperature = 1,
+	.charge_temperature_range = { -150, 600 },
+	.ggb = &ggb_arrays[0],
+};
+
+static int parse_battery_param(void)
+{
+	enum {
+		idx_i2c,
+		idx_et,
+		idx_temp0,
+		idx_temp1,
+		idx_max
+	};
+	long ps[idx_max] = { 0, };
+	char *p, *env;
+	char *endp;
+	int i = 0;
+
+	env = p = getenv("wmt.battery.param");
+	if (!p)
+		return -EINVAL;
+
+	if (!prefixcmp(p, "ug3105"))
+		g_ug31xx_id = UG31XX_ID_3105;
+	else if (!prefixcmp(p, "ug3102"))
+		g_ug31xx_id = UG31XX_ID_3102;
+	else
+		return -EINVAL;
+
+	p += 7;		// skip "ug3105:"
+
+	while (i < idx_max) {
+		ps[i++] = simple_strtol(p, &endp, 10);
+		if (*endp == '\0')
+			break;
+		p = endp + 1;
+
+		if (*p == '\0')
+			break;
+	}
+
+	ug31xx_param.i2c_adapter = ps[idx_i2c];
+	ug31xx_param.external_temperature = ps[idx_et];
+	if (ps[idx_temp1] > ps[idx_temp0]) {
+		ug31xx_param.charge_temperature_range[0] = ps[idx_temp0];
+		ug31xx_param.charge_temperature_range[1] = ps[idx_temp1];
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ggb_arrays); i++) {
+		if (strstr(env, ggb_arrays[i].name)) {
+			ug31xx_param.ggb = &ggb_arrays[i];
+			break;
+		}
+	}
+
+	printf("%s i2c%d, ggb %s, %s, charge temperature range [%d, %d]\n",
+	       (g_ug31xx_id == UG31XX_ID_3105) ? "ug3105" : "ug3102",
+		ug31xx_param.i2c_adapter,
+		ug31xx_param.ggb->name,
+		ug31xx_param.external_temperature ? "ET" : "IT",
+		ug31xx_param.charge_temperature_range[0],
+		ug31xx_param.charge_temperature_range[1]);
+	return 0;
+}
+
+/**
+ * @brief	GetTickCount
+ *
+ *	Get tick count in milli-second
+ *
+ * @return	tick count
+ */
+_upi_u32_ GetTickCount(void)
+{
+	return (0);
+}
+
+/**
+ * @brief	GetSysTickCount
+ *
+ *	Get system tick count in milli-second
+ *
+ * @return	tick count
+ */
+_upi_u32_ GetSysTickCount(void)
+{
+	return (0);
+}
+
+/**
+ * @brief	ug31_dprintk
+ *
+ *	print debug message
+ *
+ * @para	level	debug message level
+ * @para	fmt	debug message
+ * @return	message length
+ */
+#if 0
+int ug31_dprintk(int level, const char *fmt, ...)
+{
+	va_list args;
+	int r;
+
+	va_start(args, fmt);
+	//r = dprintk(level, fmt, args);
+        r = NULL;
+	va_end(args);
+	return (r);
+}
+#endif
+
+
+#define	TP_REACH_SOC	(100)
+
+void CheckRsocBeforeTP(UG31xxDataInternalType *obj)
+{
+	int rm;
+
+	if(obj->sysData.rsocFromIC >= TP_REACH_SOC)
+	{
+		obj->sysData.rsocFromIC = TP_REACH_SOC - 1;
+
+		rm = (int)obj->sysData.rsocFromIC;
+		rm = rm*obj->sysData.fccFromIC/100;
+		obj->sysData.rmFromIC = (_sys_u16_)rm;
+		return;
+	}
+
+	if(obj->sysData.rmFromIC > obj->sysData.fccFromIC)
+	{
+		obj->sysData.rmFromIC = obj->sysData.fccFromIC;
+	}
+}
+
+/**
+ * @brief	ResetFullCharge
+ *
+ *	Reset full charge checking module
+ *
+ * @para	obj	address of UG31xxDataInternalType
+ * @return	NULL
+ */
+void ResetFullCharge(UG31xxDataInternalType *obj)
+{
+	obj->tpTime = 0;
+
+	CheckRsocBeforeTP(obj);
+}
+
+#define	TP_COUNT_INTERVAL	(5)
+
+/**
+ * @brief	FullChargeCheck
+ *
+ *	Check full charge condition
+ *
+ * @para	obj	address of UG31xxDataInternalType
+ * @return	NULL
+ */
+void FullChargeCheck(UG31xxDataInternalType *obj)
+{
+	if(obj->tpTime >= obj->ggbParameter.TPTime)
+	{
+		return;
+	}
+
+	/// [AT-PM] : Check taper voltage ; 02/01/2013
+	if(obj->measData.bat1Voltage < obj->ggbParameter.TPVoltage)
+	{
+		ResetFullCharge(obj);
+		return;
+	}
+
+	/// [AT-PM] : Check taper current ; 02/01/2013
+	if((obj->measData.curr < obj->ggbParameter.standbyCurrent) ||
+	   (obj->measData.curr > obj->ggbParameter.TPCurrent))
+	{
+		ResetFullCharge(obj);
+		return;
+	}
+
+	/// [AT-PM] : Check taper time ; 02/01/2013
+	obj->tpTime = obj->tpTime + TP_COUNT_INTERVAL;
+	if(obj->tpTime < obj->ggbParameter.TPTime)
+	{
+		CheckRsocBeforeTP(obj);
+		return;
+	}
+
+	/// [AT-PM] : Set full charge condition ; 02/01/2013
+	obj->sysData.rsocFromIC = TP_REACH_SOC;
+	obj->sysData.rmFromIC = obj->sysData.fccFromIC;
+}
+
+/**
+ * @brief	SetMemoryMapping
+ *
+ *	Set memory mapping
+ *
+ * @para	data	address of UG31xxDataType
+ * @para	obj	address of UG31xxDataInternalType pointer
+ * @return	NULL
+ */
+void SetMemoryMapping(UG31xxDataType *data, UG31xxDataInternalType **obj)
+{
+	(*obj) = (UG31xxDataInternalType *)data->buf;
+	(*obj)->info = data;
+	(*obj)->measData.sysData = &((*obj)->sysData);
+	(*obj)->measData.otp = &((*obj)->otpData);
+	(*obj)->sysData.ggbXBuf = (GGBX_FILE_HEADER *)(ug31xx_param.ggb->data);
+	(*obj)->sysData.ggbParameter = &((*obj)->ggbParameter);
+	(*obj)->sysData.ggbCellTable = &((*obj)->ggbCellTable);
+	(*obj)->sysData.otpData = &((*obj)->otpData);
+        //printf("[SetMemoryMapping] ggb_tag (%d) = %d\n", sizeof((*obj)->sysData.ggbXBuf->ggb_tag), (*obj)->sysData.ggbXBuf->ggb_tag);
+        //printf("[SetMemoryMapping] sum16 (%d) = %d\n", sizeof((*obj)->sysData.ggbXBuf->sum16), (*obj)->sysData.ggbXBuf->sum16);
+        //printf("[SetMemoryMapping] time_stamp (%d) = %d\n", sizeof((*obj)->sysData.ggbXBuf->time_stamp), (*obj)->sysData.ggbXBuf->time_stamp);
+        //printf("[SetMemoryMapping] length (%d) = %d\n", sizeof((*obj)->sysData.ggbXBuf->length), (*obj)->sysData.ggbXBuf->length);
+        //printf("[SetMemoryMapping] num_ggb (%d) = %d\n", sizeof((*obj)->sysData.ggbXBuf->num_ggb), (*obj)->sysData.ggbXBuf->num_ggb);
+}
+
+#define	CURRENT_MAGIC_NUMBER	(4)
+#define	OCV_TABLE_INDEX		(1)
+
+static int OcvTableSoc[] = {
+	100,
+	95,
+	90,
+	85,
+	80,
+	75,
+	70,
+	65,
+	60,
+	55,
+	50,
+	45,
+	40,
+	35,
+	30,
+	25,
+	20,
+	15,
+	10,
+	5,
+	0,
+};
+
+/**
+ * @brief	InitCharge
+ *
+ *	Look up initial charge from table
+ *
+ * @para	obj	address of UG31xxDataInternalType
+ * @return	NULL
+ */
+void InitCharge(UG31xxDataInternalType *obj)
+{
+	int volt;
+	int tmp;
+	int idxTemp;
+	int idxSoc;
+	int ocv;
+
+	/// [AT-PM] : FCC is equal to ILMD ; 02/24/2013
+	obj->info->fcc = (int)obj->ggbParameter.ILMD;
+
+	/// [AT-PM] : Real battery voltage ; 02/24/2013
+	volt = (int)obj->measData.bat1Voltage;
+	tmp = (int)obj->measData.curr;
+	tmp = tmp/CURRENT_MAGIC_NUMBER;
+	if(tmp > 0)
+	{
+		volt = volt - tmp;
+	}
+
+	/// [AT-PM] : Look up table ; 02/24/2013
+	idxSoc = 0;
+	while(idxSoc < OCV_NUMS)
+	{
+		idxTemp = 0;
+		ocv = 0;
+		while(idxTemp < TEMPERATURE_NUMS)
+		{
+			ocv = ocv + obj->ggbCellTable.INIT_OCV[idxTemp][OCV_TABLE_INDEX][idxSoc];
+			idxTemp = idxTemp + 1;
+		}
+		ocv = ocv/TEMPERATURE_NUMS;
+
+		if(volt >= ocv)
+		{
+			break;
+		}
+
+		idxSoc = idxSoc + 1;
+	}
+	if(idxSoc < OCV_NUMS)
+	{
+		obj->info->rsoc = OcvTableSoc[idxSoc];
+	}
+	else
+	{
+		obj->info->rsoc = 0;
+	}
+
+	/// [AT-PM] : Calculate RM ; 02/24/2013
+	tmp = obj->info->rsoc;
+	tmp = tmp*obj->info->fcc/CONST_PERCENTAGE;
+	obj->info->rm = tmp;
+}
+
+/// ===========================================================================
+/// Extern region
+/// ===========================================================================
+
+#define DEFAULT_ADC1_CONV_TIME  (1250)
+#define DEFAULT_TIME_TICK       (0xFFFFFFFF)
+
+/**
+ * @brief       UpiBootInitial
+ *
+ *      Initialize uG31xx
+ *
+ * @para        data    address of UG31xxDataType
+ * @return      UPI_BOOT_RTN
+ */
+int UpiBootInitial(UG31xxDataType *data)
+{
+	UG31xxDataInternalType *obj;
+
+	//dprintf(INFO, "[UpiBootInitial] Version = %d\n", UG31XX_BOOT_VERSION);
+	printf("[UpiBootInitial] Version = %d\n", UG31XX_BOOT_VERSION);
+
+	/// [AT-PM] : Create memory buffer ; 02/01/2013
+	data->buf = (char *)malloc(sizeof(UG31xxDataInternalType));
+	memset(data->buf, 0, sizeof(UG31xxDataInternalType));
+	obj = _UPI_NULL_;
+	SetMemoryMapping(data, &obj);
+
+	data->version = UG31XX_BOOT_VERSION;
+	obj->status = 0;
+
+	//dprintf(INFO, "[UpiBootInitial] data->ug31xx_i2c_dev = %d\n",data->ug31xx_i2c_dev);
+	/// [AT-PM] : Initial I2C device ; 02/04/2013
+	//ug31xx_init_i2c(data->ug31xx_i2c_dev);
+
+	/// [AT-PM] : Load GGB data ; 02/24/2013
+	UpiInitSystemData(&obj->sysData);
+	printf("[UPI Boot GGB]: %d (0x%04x)\n", obj->ggbCellTable.INIT_OCV[0][0][0], obj->ggbCellTable.INIT_OCV[0][0][0]);
+	printf("[UPI Boot GGB]: %d (0x%04x)\n", obj->ggbParameter.adc1_pgain, obj->ggbParameter.adc1_pgain);
+	printf("[UPI Boot GGB]: %d (0x%04x)\n", obj->ggbParameter.adc1_ngain, obj->ggbParameter.adc1_ngain);
+	printf("[UPI Boot GGB]: %d (0x%04x)\n", obj->ggbParameter.adc1_pos_offset, obj->ggbParameter.adc1_pos_offset);
+	printf("[UPI Boot GGB]: %d (0x%04x)\n", obj->ggbParameter.adc2_gain, obj->ggbParameter.adc2_gain);	
+	printf("[UPI Boot GGB]: %d (0x%04x)\n", obj->ggbParameter.adc2_offset, obj->ggbParameter.adc2_offset);
+
+	/// [AT-PM] : Get capacity information from IC ; 02/24/2013
+	UpiLoadBatInfoFromIC(&obj->sysData);
+	if(obj->sysData.fccFromIC == 0)
+	{
+		//dprintf(CRITICAL, "[UpiBootInitial] Capacity in uG31xx is invalid.\n");
+		printf("[UpiBootInitial] Capacity in uG31xx is invalid.\n");
+		obj->status = obj->status | UG31XX_BOOT_STATUS_FCC_IS_0;
+	}
+
+	/// [AT-PM] : Check IC is active or not ; 02/24/2013
+	if(UpiCheckICActive() == _UPI_TRUE_)
+	{
+		//dprintf(CRITICAL, "[UpiBootInitial] uG31xx is not actived.\n");
+		printf("[UpiBootInitial] uG31xx is not actived.\n");
+		obj->status = obj->status | UG31XX_BOOT_STATUS_IC_IS_NOT_ACTIVE;
+
+		/// [AT-PM] : Active uG31xx ; 02/24/2013
+		if(UpiActiveUg31xx() != SYSTEM_RTN_PASS)
+		{
+			return (UPI_BOOT_RTN_UG31XX_NOT_ACTIVE);
+		}
+
+		/// [AT-PM] : Initialize ADC ; 02/24/2013
+		UpiSetupAdc(&obj->sysData);
+
+		/// [AT-PM] : Initialize system ; 02/24/2013
+		UpiSetupSystem(&obj->sysData);
+	}
+
+	/// [AT-PM] : Get OTP data ; 02/24/2013
+	API_I2C_Read(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, OTP1_BYTE1, OTP1_SIZE, obj->otpData.otp1);
+       	API_I2C_Read(SECURITY, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, OTP2_BYTE1, OTP2_SIZE, obj->otpData.otp2);
+        API_I2C_Read(NORMAL, UG31XX_I2C_HIGH_SPEED_MODE, UG31XX_I2C_TEM_BITS_MODE, OTP6_BYTE1, OTP3_SIZE, obj->otpData.otp3);
+       	#ifdef  UPI_UBOOT_DEBUG_MSG
+                printf("[UpiBootInitial] %02x %02x %02x %02x\n",
+               	        obj->otpData.otp1[0], obj->otpData.otp1[1], obj->otpData.otp1[2], obj->otpData.otp1[3]);
+       	        printf("[UpiBootInitial] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
+                        obj->otpData.otp2[0], obj->otpData.otp2[1], obj->otpData.otp2[2], obj->otpData.otp2[3],
+                       	obj->otpData.otp2[4], obj->otpData.otp2[5], obj->otpData.otp2[6], obj->otpData.otp2[7],
+               	        obj->otpData.otp2[8], obj->otpData.otp2[9], obj->otpData.otp2[10], obj->otpData.otp2[11],
+       	                obj->otpData.otp2[12], obj->otpData.otp2[13], obj->otpData.otp2[14], obj->otpData.otp2[15]);
+                printf("[UpiBootInitial] %02x %02x %02x %02x\n",
+               	        obj->otpData.otp3[0], obj->otpData.otp3[1], obj->otpData.otp3[2], obj->otpData.otp3[3]);
+       	#endif  ///< end of UPI_UBOOT_DEBUG_MSG
+	UpiConvertOtp(&obj->otpData);
+	if(obj->otpData.productType != UG31XX_PRODUCT_TYPE_0)
+	{
+		//dprintf(CRITICAL, "[UpiBootInitial] uG31xx product type is not %d (%d)\n", UG31XX_PRODUCT_TYPE_0, obj->otpData.productType);
+		printf("[UpiBootInitial] uG31xx product type is not %d (%d)\n", UG31XX_PRODUCT_TYPE_0, obj->otpData.productType);
+		obj->status = obj->status | UG31XX_BOOT_STATUS_WRONG_PRODUCT_TYPE;
+		return (UPI_BOOT_RTN_INVALID_PRODUCT_TYPE);
+	}
+
+	/// [AT-PM] : Initialize UG31xxInternalDataType ; 02/24/2013
+	if(obj->status & (UG31XX_BOOT_STATUS_FCC_IS_0 | UG31XX_BOOT_STATUS_IC_IS_NOT_ACTIVE))
+	{
+		/// [AT-PM] : Data for IC not active ; 02/24/2013
+		obj->measData.lastDeltaCap = 0;
+		obj->measData.adc1ConvertTime = DEFAULT_ADC1_CONV_TIME;
+		/// [AT-PM] : Do measurement ; 02/24/2013
+		obj->measData.lastTimeTick = DEFAULT_TIME_TICK;
+		UpiMeasurement(&obj->measData);
+                data->volt = (int)obj->measData.bat1Voltage;
+                data->curr = (int)obj->measData.curr;
+                data->intTemp = (int)obj->measData.intTemperature;
+                data->extTemp = (int)obj->measData.extTemperature;
+		/// [AT-PM] : Look up initial capacity from table ; 02/24/2013
+		InitCharge(obj);
+		obj->sysData.rmFromIC = (_sys_u16_)obj->info->rm;
+		obj->sysData.fccFromIC = (_sys_u16_)obj->info->fcc;
+		obj->sysData.rsocFromIC = (_sys_u8_)obj->info->rsoc;
+		//dprintf(INFO, "[UpiBootInitial] (Lookup Table) %d / %d / %d - %d / %d = %d\n", data->volt, data->curr, data->intTemp, data->rm, data->fcc, data->rsoc);
+		printf("[UpiBootInitial] (Lookup Table) %d / %d / %d - %d / %d = %d\n", data->volt, data->curr, data->intTemp, data->rm, data->fcc, data->rsoc);
+	}
+	else
+	{
+		/// [AT-PM] : Data for IC active ; 02/24/2013
+		obj->measData.lastDeltaCap = obj->sysData.deltaCapFromIC;
+		obj->measData.adc1ConvertTime = obj->sysData.adc1ConvTime;
+		/// [AT-PM] : Do measurement ; 02/24/2013
+		obj->measData.lastTimeTick = DEFAULT_TIME_TICK;
+		UpiMeasurement(&obj->measData);
+		data->volt = (int)obj->measData.bat1Voltage;
+		data->curr = (int)obj->measData.curr;
+		data->intTemp = (int)obj->measData.intTemperature;
+		data->extTemp = (int)obj->measData.extTemperature;
+		/// [AT-PM] : Set capacity information ; 02/24/2013
+		obj->info->rm = (int)obj->sysData.rmFromIC;
+		obj->info->fcc = (int)obj->sysData.fccFromIC;
+		obj->info->rsoc = (int)obj->sysData.rsocFromIC;
+		//dprintf(INFO, "[UpiBootInitial] (Load From IC) %d / %d / %d - %d / %d = %d\n", data->volt, data->curr, data->intTemp, data->rm, data->fcc, data->rsoc);
+		printf("[UpiBootInitial] (Load From IC) %d / %d / %d - %d / %d = %d\n", data->volt, data->curr, data->intTemp, data->rm, data->fcc, data->rsoc);
+	}
+	return (UPI_BOOT_RTN_PASS);
+}
+
+/**
+ * @brief       UpiBootMain
+ *
+ *      Main function of uG31xx
+ *
+ * @para        data    address of UG31xxDataType
+ * @return      UPI_BOOT_RTN
+ */
+int UpiBootMain(UG31xxDataType *data)
+{
+	UG31xxDataInternalType *obj;
+	MEAS_RTN_CODE rtn;
+
+	//dprintf(INFO, "[UpiBootMain]\n");
+	//printf("[UpiBootMain]\n");
+	obj = _UPI_NULL_;
+	SetMemoryMapping(data, &obj);
+
+	/// [AT-PM] : Do measurement ; 02/24/2013
+	obj->measData.lastTimeTick = DEFAULT_TIME_TICK;
+	rtn = UpiMeasurement(&obj->measData);
+	if(rtn != MEAS_RTN_PASS)
+	{
+		//dprintf(INFO, "[UpiBootMain] uG31xx measurement routine fail 0x%02x\n", rtn);
+		printf("[UpiBootMain] uG31xx measurement routine fail 0x%02x\n", rtn);
+
+		data->rm = 0;
+		data->fcc = 0;
+		data->rsoc = 0;
+		return (rtn);
+	}
+
+        /// [AT-PM] : Update capacity ; 02/13/2013
+        obj->sysData.voltage = obj->measData.bat1Voltage;
+        if((obj->measData.curr < 0) && (obj->measData.stepCap > 0))
+	{
+		obj->measData.stepCap = 0;
+	}
+	else if((obj->measData.curr > 0) && (obj->measData.stepCap < 0))
+	{
+		obj->measData.stepCap = 0;
+	}
+        UpiUpdateBatInfoFromIC(&obj->sysData, obj->measData.stepCap);
+
+	/// [AT-PM] : Reset coulomb counter ; 02/24/2013
+	obj->measData.lastTimeTick = DEFAULT_TIME_TICK;
+	if(obj->measData.deltaCap > 10)
+	{
+		UpiResetCoulombCounter(&obj->measData);
+	}
+
+	//dprintf(INFO, "[UpiBootMain] %d / %d / %d\n", obj->measData.codeBat1, obj->measData.codeCurrent, obj->measData.codeIntTemperature);
+	//dprintf(INFO, "[UpiBootMain] %d - %d / %d - %d\n", obj->measData.adc1Gain, obj->measData.adc1Offset, obj->measData.adc2Gain, obj->measData.adc2Offset);
+	//dprintf(INFO, "[UpiBootMain] Voltage : %d - %d\n", obj->ggbParameter.adc2_gain, obj->ggbParameter.adc2_offset);
+	//dprintf(INFO, "[UpiBootMain] Current : %d - %d - %d\n", obj->ggbParameter.adc1_pgain, obj->ggbParameter.adc1_ngain, obj->ggbParameter.adc1_pos_offset);
+	//dprintf(INFO, "[UpiBootMain] Int. T : %d\n", obj->ggbParameter.adc_d3);
+
+	//printf("[UpiBootMain] %d / %d / %d\n", obj->measData.codeBat1, obj->measData.codeCurrent, obj->measData.codeIntTemperature);
+	//printf("[UpiBootMain] %d - %d / %d - %d\n", obj->measData.adc1Gain, obj->measData.adc1Offset, obj->measData.adc2Gain, obj->measData.adc2Offset);
+	//printf("[UpiBootMain] Voltage : %d - %d\n", obj->ggbParameter.adc2_gain, obj->ggbParameter.adc2_offset);
+	//printf("[UpiBootMain] Current : %d - %d - %d\n", obj->ggbParameter.adc1_pgain, obj->ggbParameter.adc1_ngain, obj->ggbParameter.adc1_pos_offset);
+	//printf("[UpiBootMain] Int. T : %d\n", obj->ggbParameter.adc_d3);
+
+	data->volt = (int)obj->measData.bat1Voltage;
+	data->curr = (int)obj->measData.curr;
+	data->intTemp = (int)obj->measData.intTemperature;
+	data->extTemp = (int)obj->measData.extTemperature;
+
+	/// [AT-PM] : Full charge determination ; 02/01/2013
+	FullChargeCheck(obj);
+
+	/// [AT-PM] : Refresh capacity information ; 02/24/2013
+	data->rm = (int)obj->sysData.rmFromIC;
+	data->fcc = (int)obj->sysData.fccFromIC;
+	data->rsoc = (int)obj->sysData.rsocFromIC;
+	//dprintf(INFO, "[UpiBootMain] %d / %d / %d - %d / %d = %d\n", data->volt, data->curr, data->intTemp, data->rm, data->fcc, data->rsoc);
+	//printf("[UpiBootMain] %d / %d / %d - %d / %d = %d\n", data->volt, data->curr, data->intTemp, data->rm, data->fcc, data->rsoc);
+
+	/// [AT-PM] : Save battery information back to IC ; 02/24/2013
+	if(obj->status & (UG31XX_BOOT_STATUS_FCC_IS_0 | UG31XX_BOOT_STATUS_IC_IS_NOT_ACTIVE))
+	{
+		obj->sysData.fccFromIC = 0;
+	}
+	UpiSaveBatInfoTOIC(&obj->sysData);
+	obj->sysData.fccFromIC = (_sys_u16_)data->fcc;
+#if 0
+	printf("battery volt = %d\n", data->volt);
+	printf("battery curr = %d\n", data->curr);
+	printf("battery intTemp = %d\n", data->intTemp);
+	printf("battery extTemp = %d\n", data->extTemp);
+	printf("battery rm = %d\n", data->rm);
+	printf("battery fcc = %d\n", data->fcc);
+	printf("battery rsoc = %d\n", data->rsoc);
+#endif
+	return (UPI_BOOT_RTN_PASS);
+}
+
+/**
+ * @brief       UpiBootUnInitial
+ *
+ *      Un-initialize uG31xx
+ *
+ * @para        data    address of UG31xxDataType
+ * @return      UPI_BOOT_RTN
+ */
+int UpiBootUnInitial(UG31xxDataType *data)
+{
+	printf("[UpiBootUninitial]\n");
+
+	free(data->buf);
+	return (UPI_BOOT_RTN_PASS);
+}
+
+/*
+ * WMT MCE: Use gpio3 on ug31xx as a switch to control charger.
+ */
+static void hw_charging_set(bool enable)
+{
+	if (g_ug31xx_id == UG31XX_ID_3105) {
+		API_I2C_SingleWrite(0, 0, 0, 0x16, enable ? 0x2 : 0x0);
+	} else if (g_ug31xx_id == UG31XX_ID_3102) {
+		u8 data = 0;
+		API_I2C_SingleRead(0, 0, 0 ,REG_CTRL1, &data);
+		if (enable)
+			data |= CTRL1_IO1DATA;
+		else
+			data &= ~CTRL1_IO1DATA;
+		API_I2C_SingleWrite(0, 0, 0, REG_CTRL1, data);
+	}
+}
+
+static void inline hw_charging_disable(void)
+{
+	hw_charging_set(false);
+}
+
+static void inline hw_charging_enable(void)
+{
+	hw_charging_set(true);
+}
+
+static unsigned short percentage = -1;
+
+int upi_read_percentage(void)
+{
+	UpiBootMain(&ug31_data);
+	percentage = ug31_data.rsoc;
+
+	if (g_ug31xx_id == UG31XX_ID_3105) {
+		printf("%s: percentage = %d, temperature %d\n",
+		       __FUNCTION__, percentage, ug31_data.extTemp);
+		if (ug31xx_param.external_temperature) {
+			if (ug31_data.extTemp < ug31xx_param.charge_temperature_range[0] ||
+			    ug31_data.extTemp > ug31xx_param.charge_temperature_range[1]) {
+				hw_charging_disable();
+			} else {
+				hw_charging_enable();
+			}
+			printf("%s: percentage = %d, temperature %d\n",
+			       __FUNCTION__, percentage, ug31_data.extTemp);
+		}
+	} else if (g_ug31xx_id == UG31XX_ID_3102) {
+		hw_charging_enable();
+	}
+
+	return percentage;
+}
+
+int upi_read_voltage(void)
+{
+   int volt_mV;
+
+   UpiBootMain(&ug31_data);
+   volt_mV = ug31_data.volt;
+   printf("voltage = %d mV\n", volt_mV);
+
+    return volt_mV;
+}
+
+int upi_read_current(void)
+{
+   int current;
+
+   UpiBootMain(&ug31_data);
+   current = ug31_data.curr;
+   printf("current = %d mA\n", current);
+
+    return current;
+}
+
+int upi_boot_init(void)
+{
+    int ret;
+
+    if (parse_battery_param())
+	return -EINVAL;
+
+    ug31xx_init_i2c(ug31xx_param.i2c_adapter);
+
+    ret = UpiBootInitial(&ug31_data);
+
+    hw_charging_enable();
+
+    return (ret == UPI_BOOT_RTN_PASS) ? 0 : -1;
+}
+
+static int upi_check_bl(void)
+{
+	int ret;
+
+	if (percentage < 0) {
+		upi_read_percentage();
+	}
+
+	ret = (percentage < 3);
+	printf("%s: percentage = %d, temperature %d, ret %d\n",
+	       __FUNCTION__, ug31_data.rsoc, ug31_data.extTemp, ret);
+
+	return ret;
+}
+
+struct battery_dev ug31xx_battery_dev = {
+		.name		= "ug3105",
+		.is_gauge	= 1,
+		.init		= upi_boot_init,
+		.get_capacity	= upi_read_percentage,
+		.get_voltage	= upi_read_voltage,
+		.get_current	= upi_read_current,
+		.check_batlow	= upi_check_bl,
+};
+
+struct battery_dev ug3102_battery_dev = {
+		.name		= "ug3102",
+		.is_gauge	= 1,
+		.init		= upi_boot_init,
+		.get_capacity	= upi_read_percentage,
+		.get_voltage	= upi_read_voltage,
+		.get_current	= upi_read_current,
+		.check_batlow	= upi_check_bl,
+};
+#endif
diff --git a/board/wmt/wmt_battery/gauge/upi/ug31xx_boot.h b/board/wmt/wmt_battery/gauge/upi/ug31xx_boot.h
new file mode 100755
index 0000000..730a4bf
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ug31xx_boot.h
@@ -0,0 +1,71 @@
+/**
+ * @filename	ug31xx_boot.h
+ *
+ *	uG31xx API for bootloader
+ *
+ * @author	AllenTeng <allen_teng@upi-semi.com>
+ */
+
+#ifndef	_UG31XX_BOOT_H_
+#define	_UG31XX_BOOT_H_
+
+enum UPI_BOOT_RTN {
+	UPI_BOOT_RTN_PASS = 0,
+	UPI_BOOT_RTN_UG31XX_NOT_ACTIVE,
+	UPI_BOOT_RTN_INVALID_CAPACITY,
+	UPI_BOOT_RTN_INVALID_PRODUCT_TYPE,
+};
+
+typedef struct UG31xxDataST {
+	//struct qup_i2c_dev *ug31xx_i2c_dev;
+	
+	int	version;
+
+	int	rm;		///< [AT-PM] : in unit mAh ; 02/01/2013
+	int	fcc;		///< [AT-PM] : in unit mAh ; 02/01/2013
+	int	rsoc;		///< [AT-PM] : in unit % ; 02/01/2013
+
+	int	volt;		///< [AT-PM] : in unit mV ; 02/01/2013
+	int	curr;		///< [AT-PM] : in unit mA ; 02/01/2013
+	int	intTemp;	///< [AT-PM] : in unit 0.1oC ; 02/01/2013
+	int	extTemp;	///< [AT-PM] : in unit 0.1oC ; 02/01/2013
+
+	char	*buf;
+} UG31xxDataType;
+
+/**
+ * @brief	UpiBootInitial
+ *
+ *	Initialize uG31xx
+ *
+ * @para	data	address of UG31xxDataType
+ * @return	UPI_BOOT_RTN_PASS
+ */
+extern int UpiBootInitial(UG31xxDataType *data);
+
+/**
+ * @brief	UpiBootMain
+ *
+ *	Main function of uG31xx
+ *
+ * @para	data	address of UG31xxDataType
+ * @return	UPI_BOOT_RTN_PASS
+ */
+extern int UpiBootMain(UG31xxDataType *data);
+
+/**
+ * @brief	UpiBootUnInitial
+ *
+ *	Un-initialize uG31xx
+ *
+ * @para	data	address of UG31xxDataType
+ * @return	UPI_BOOT_RTN_PASS
+ */
+extern int UpiBootUnInitial(UG31xxDataType *data);
+
+extern int upi_read_percentage(void);
+
+extern int upi_boot_init(void);
+
+#endif	///< end of _UG31XX_BOOT_H_
+
diff --git a/board/wmt/wmt_battery/gauge/upi/ug31xx_boot_i2c.c b/board/wmt/wmt_battery/gauge/upi/ug31xx_boot_i2c.c
new file mode 100755
index 0000000..800656a
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ug31xx_boot_i2c.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2012, ASUSTek, Inc. All Rights Reserved.
+ */
+
+#include <common.h>
+#ifdef CONFIG_BATT_UPI
+//#include <debug.h>
+//#include <gsbi.h>
+//#include <platform/timer.h>
+#include "ug31xx_boot_i2c.h"
+extern int wmt_i2c_transfer(struct i2c_msg_s msgs[], int num, int adap_id);
+
+//typedef unsigned char  u8;
+//typedef unsigned short u16;
+
+#define	UG31XX_I2C_SLAVE_ADDRESS	(0x70)
+
+//static struct qup_i2c_dev *ug31xx_i2c_dev = NULL;
+static int ug31xx_i2c_dev;
+
+/**
+ * @brief	ug31xx_init_i2c
+ *
+ *	Initialize I2C for uG31xx
+ *
+ * @para	ug31xx_i2c_dev	address of qup_i2c_dev
+ * @return	NULL
+ */
+//void ug31xx_init_i2c(struct qup_i2c_dev *i2c_dev)
+void ug31xx_init_i2c(int i2c_dev)
+{
+	ug31xx_i2c_dev = i2c_dev;
+}
+
+/**
+ * @brief	ug31xx_read_i2c
+ *
+ *	I2C read from uG31xx
+ *
+ * @para	ug31xx_i2c_dev	address of qup_i2c_dev
+ * @para	reg		register address
+ * @para	rt_value	address of returned value
+ * @return	0 if pass
+ */
+int ug31xx_read_i2c(u8 reg, int *rt_value)
+{
+	int status;
+	unsigned char ret;
+	unsigned char data[2] = 
+	{
+		reg,
+		SECURITY_KEY,
+	};
+	struct i2c_msg_s msg_buf1[2] = 
+	{
+		//{UG31XX_I2C_SLAVE_ADDRESS,	I2C_M_WR | I2C_M_NOSTART,	1,	&data[0],	},
+		{	UG31XX_I2C_SLAVE_ADDRESS,	I2C_M_WR,	1,	&data[0],	},
+		{	UG31XX_I2C_SLAVE_ADDRESS,	I2C_M_RD,	1,	&ret,		},
+	};
+	struct i2c_msg_s msg_buf2[2] = 
+	{
+		//{UG31XX_I2C_SLAVE_ADDRESS,	I2C_M_WR | I2C_M_NOSTART,	2,	&data[0],	},
+		{	UG31XX_I2C_SLAVE_ADDRESS,	I2C_M_WR,	2,	&data[0],	},
+		{	UG31XX_I2C_SLAVE_ADDRESS,	I2C_M_RD,	1,	&ret,		},
+	};
+
+	if(reg < 0x80)
+	{
+		//status = qup_i2c_xfer(ug31xx_i2c_dev, msg_buf1, 2);
+		status = wmt_i2c_transfer(msg_buf1, 2, ug31xx_i2c_dev);
+	}
+	else
+	{
+		//status = qup_i2c_xfer(ug31xx_i2c_dev, msg_buf2, 2);
+		status = wmt_i2c_transfer(msg_buf2, 2, ug31xx_i2c_dev);
+	}
+
+	if(status > 0)
+	{
+		*rt_value = ret;
+		return (0);
+	}
+	//dprintf(CRITICAL, "[ug31xx_read_i2c][reg=%02x] failed\n", reg);
+	printf("[ug31xx_read_i2c][reg=%02x] failed\n", reg);
+	return (-1);
+}
+
+/**
+ * @brief	ug31xx_write_i2c
+ *
+ *	I2C write to uG31xx
+ *
+ * @para	ug31xx_i2c_dev	address of qup_i2c_dev
+ * @para	reg		register address
+ * @para	rt_value	value to be written
+ * @return	0 if pass
+ */
+int ug31xx_write_i2c(u8 reg, int rt_value)
+{
+	int status;
+	unsigned char data1[2] =
+	{
+		reg,
+		rt_value,
+	};
+	unsigned char data2[3] =
+	{
+		reg,
+		SECURITY_KEY,
+		rt_value,
+	};
+	struct i2c_msg_s msg_buf[2] =
+	{
+		//{UG31XX_I2C_SLAVE_ADDRESS,I2C_M_WR | I2C_M_NOSTART,	2,	&data1[0],	},
+		//{UG31XX_I2C_SLAVE_ADDRESS,I2C_M_WR | I2C_M_NOSTART,	3,	&data2[0],	}
+		{	UG31XX_I2C_SLAVE_ADDRESS,	I2C_M_WR,	2,	&data1[0],	},
+		{	UG31XX_I2C_SLAVE_ADDRESS,	I2C_M_WR,	3,	&data2[0],	}
+	};
+
+	if(reg < 0x80)
+	{
+		//status = qup_i2c_xfer(ug31xx_i2c_dev, &msg_buf[0], 1);
+		status = wmt_i2c_transfer(&msg_buf[0], 1,ug31xx_i2c_dev);
+	}
+	else
+	{
+		//status = qup_i2c_xfer(ug31xx_i2c_dev, &msg_buf[1], 1);
+		status = wmt_i2c_transfer(&msg_buf[1], 1,ug31xx_i2c_dev);
+	}
+
+	if(status > 0)
+	{
+		return (0);
+	}
+	//dprintf(CRITICAL, "[ug31xx_write_i2c][reg=%02x] failed.\n", reg);
+	return (-1);
+}
+
+/** 
+ * @brief	_API_I2C_Write
+ *
+ *	I2C write protocol for uG31xx
+ *
+ * @para	writeAddress	register address to be written
+ * @para	writeLength	data length
+ * @para	PWriteData	address of data buffer
+ * @return	true if pass
+ */
+_i2c_bool _API_I2C_Write(u16 writeAddress, u8 writeLength, u8 *PWriteData)
+{
+  int i, ret;
+  int tmp_buf;
+
+  if (!PWriteData)
+  {
+   // dprintf(CRITICAL, "[_API_I2C_Write]Write buffer pointer error.\n");
+      printf("[_API_I2C_Write]Write buffer pointer error.\n");
+    return (_i2c_false);
+  }
+
+  for (i=0; i<writeLength; i++) {
+    tmp_buf = PWriteData[i];
+
+    ret = ug31xx_write_i2c(writeAddress+i, tmp_buf);
+    if (ret)
+    {
+      //dprintf(CRITICAL, "[_API_I2C_Write]Write data (%02x) to address (%02x) fail.\n", tmp_buf, writeAddress + i);
+      printf("[_API_I2C_Write]Write data (%02x) to address (%02x) fail.\n", tmp_buf, writeAddress + i);
+      return (_i2c_false);
+    }
+  }
+
+  return (_i2c_true);
+}
+
+/**
+ * @brief	_API_I2C_Read
+ *
+ *	I2C read protocol for uG31xx
+ * 
+ * @para	readAddress	register address to be read
+ * @para	readLength	data length
+ * @para	pReadDataBuffer	address of data buffer
+ * @return	true if pass
+ */
+_i2c_bool _API_I2C_Read(u16 readAddress, u8 readLength, u8 *pReadDataBuffer)
+{
+  int i, ret;
+
+  if (!pReadDataBuffer)
+  {
+    //dprintf(CRITICAL, "[_API_I2C_Read]Read buffer pointer error.\n");
+      printf("[_API_I2C_Read]Read buffer pointer error.\n");
+    return (_i2c_false);
+  }
+
+  for (i=0; i<readLength; i++) {
+    int tmp_buf=0;
+
+    ret = ug31xx_read_i2c(readAddress+i, &tmp_buf);
+    if (ret)
+    {
+      //dprintf(CRITICAL, "[_API_I2C_Read]Read data from address (%02x) fail.\n", readAddress + i);
+      printf("[_API_I2C_Read]Read data from address (%02x) fail.\n", readAddress + i);
+      return (_i2c_false);
+    }
+    pReadDataBuffer[i] = tmp_buf;
+  }
+
+  return (_i2c_true);
+}
+#endif
diff --git a/board/wmt/wmt_battery/gauge/upi/ug31xx_boot_i2c.h b/board/wmt/wmt_battery/gauge/upi/ug31xx_boot_i2c.h
new file mode 100755
index 0000000..c96c640
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/upi/ug31xx_boot_i2c.h
@@ -0,0 +1,75 @@
+/**
+ * @filename	ug31xx_boot_i2c.h
+ *
+ *	Interface of I2C in bootloader
+ *
+ * @author	AllenTeng <allen_teng@upi-semi.com>
+ */
+
+#ifndef	_UG31XX_BOOT_I2C_H_
+#define	_UG31XX_BOOT_I2C_H_
+
+//#include <i2c_qup.h>
+/* I2C Message - used for pure i2c transaction*/
+/**/
+/* flags*/
+#define I2C_M_RD                0x01
+#define I2C_M_WR                0x00
+unsigned short bq_battery_read_percentage(void);
+
+struct i2c_msg_s {
+    unsigned short addr;        /* slave address*/
+    unsigned short flags;       /* flags*/
+    unsigned short len;         /* msg length*/
+    unsigned char *buf;        /* pointer to msg data*/
+} ;
+
+
+#define SECURITY_KEY	0x5A	//i2c read/write 
+#define ONE_BYTE	0x1
+#define TWO_BYTE	0x0
+
+#define _i2c_bool		unsigned char
+#define _i2c_true		(1)
+#define _i2c_false	(0)
+
+//void ug31xx_init_i2c(struct qup_i2c_dev *i2c_dev);
+//void ug31xx_init_i2c(void);
+
+int ug31xx_read_i2c(unsigned char reg, int *rt_value);
+int ug31xx_write_i2c(unsigned char reg, int rt_value);
+
+_i2c_bool _API_I2C_Write(unsigned short writeAddress, unsigned char writeLength, unsigned char *PWriteData);
+_i2c_bool _API_I2C_Read(unsigned short readAddress, unsigned char readLength, unsigned char *pReadDataBuffer);
+
+static inline _i2c_bool API_I2C_Read(_i2c_bool bSecurityMode, _i2c_bool bHighSpeedMode, 
+                _i2c_bool bTenBitMode ,unsigned short readAddress, unsigned char readLength, unsigned char *pReadDataBuffer) 
+{
+        return _API_I2C_Read(readAddress, readLength, pReadDataBuffer);
+}
+
+static inline _i2c_bool API_I2C_Write(_i2c_bool bSecurityMode, _i2c_bool bHighSpeedMode, _i2c_bool bTenBitMode,
+                unsigned short writeAddress, unsigned char writeLength,  unsigned char *PWriteData) 
+{
+        return _API_I2C_Write(writeAddress, writeLength, PWriteData);
+}
+
+static inline _i2c_bool API_I2C_SingleRead(_i2c_bool bSecurityMode,_i2c_bool bHighSpeedMode, _i2c_bool bTenBitMode ,
+                unsigned short readAddress, unsigned char *ReadData) 
+{
+        return API_I2C_Read(bSecurityMode, bHighSpeedMode, bTenBitMode, readAddress, 1, ReadData);
+}
+
+static inline _i2c_bool API_I2C_SingleWrite(_i2c_bool bSecurityMode, _i2c_bool bHighSpeedMode, _i2c_bool bTenBitMode ,
+                unsigned short writeAddress, unsigned char WriteData) 
+{
+        return API_I2C_Write(bSecurityMode, bHighSpeedMode, bTenBitMode, writeAddress, 1, &WriteData);
+}
+
+static inline _i2c_bool API_I2C_Init(unsigned long clockRate, unsigned short slaveAddr)
+{
+        return _i2c_true;
+}
+
+#endif	///< end of _UG31XX_BOOT_I2C_H_
+
diff --git a/board/wmt/wmt_battery/gauge/vt1603/vt1603.h b/board/wmt/wmt_battery/gauge/vt1603/vt1603.h
new file mode 100755
index 0000000..de1dd89
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/vt1603/vt1603.h
@@ -0,0 +1,132 @@
+/*++ 
+ * linux/sound/soc/codecs/vt1603.h
+ * WonderMedia audio driver for ALSA
+ *
+ * Copyright c 2010  WonderMedia  Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License as published by 
+ * the Free Software Foundation, either version 2 of the License, or 
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, 
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+ * GNU General Public License for more details. 
+ *
+ * You should have received a copy of the GNU General Public License 
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 4F, 533, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C
+--*/
+
+#ifndef _VT1603_H
+#define _VT1603_H
+
+/* VT1603 register space */
+
+///////////vt1603//////////////////
+#define BIT0	0x00000001
+#define BIT1	0x00000002
+#define BIT2	0x00000004
+#define BIT3	0x00000008
+#define BIT4	0x00000010
+#define BIT5	0x00000020
+#define BIT6	0x00000040
+#define BIT7	0x00000080
+#define BIT8	0x00000100
+
+#define VT1603_RESET 0x15
+
+#define VT1603_R00  0x00
+#define VT1603_R01  0x01
+#define VT1603_R02  0x02
+#define VT1603_R03  0x03
+#define VT1603_R04  0x04
+#define VT1603_R05  0x05
+#define VT1603_R06  0x06
+#define VT1603_R07  0x07
+#define VT1603_R08  0x08
+#define VT1603_R09  0x09
+#define VT1603_R0a  0x0a
+#define VT1603_R0b  0x0b
+#define VT1603_R0c  0x0c
+#define VT1603_R0d  0x0d
+#define VT1603_R0e  0x0e
+#define VT1603_R0f  0x0f
+#define VT1603_R10  0x10
+#define VT1603_R11  0x11
+#define VT1603_R12  0x12
+#define VT1603_R13  0x13
+#define VT1603_R15  0x15
+#define VT1603_R19  0x19
+#define VT1603_R1b  0x1b
+#define VT1603_R1c  0x1c
+#define VT1603_R1d  0x1d
+#define VT1603_R20  0x20
+#define VT1603_R21  0x21
+#define VT1603_R23  0x23
+#define VT1603_R24  0x24
+#define VT1603_R25  0x25
+#define VT1603_R28  0x28
+#define VT1603_R29  0x29
+#define VT1603_R2a  0x2a
+#define VT1603_R2b  0x2b
+#define VT1603_R2c  0x2c
+#define VT1603_R2d  0x2d
+#define VT1603_R40  0x40
+#define VT1603_R41  0x41
+#define VT1603_R42  0x42
+#define VT1603_R47  0x47
+#define VT1603_R51  0x51
+#define VT1603_R52  0x52
+#define VT1603_R53  0x53
+#define VT1603_R5f  0x5f
+#define VT1603_R60  0x60
+#define VT1603_R61  0x61
+#define VT1603_R62  0x62
+#define VT1603_R63  0x63
+#define VT1603_R64  0x64
+#define VT1603_R65  0x65
+#define VT1603_R66  0x66
+#define VT1603_R67  0x67
+#define VT1603_R68  0x68
+#define VT1603_R69  0x69
+#define VT1603_R6a  0x6a
+#define VT1603_R6b  0x6b
+#define VT1603_R6d  0x6d
+#define VT1603_R6e  0x6e
+#define VT1603_R70  0x70
+#define VT1603_R71  0x71
+#define VT1603_R72  0x72
+#define VT1603_R73  0x73
+#define VT1603_R77  0x77
+#define VT1603_R79  0x79
+#define VT1603_R7a  0x7a
+#define VT1603_R7b  0x7b
+#define VT1603_R7c  0x7c
+#define VT1603_R82  0x82
+#define VT1603_R87  0x87
+#define VT1603_R88  0x88
+#define VT1603_R8a  0x8a
+#define VT1603_R8e  0x8e
+#define VT1603_R90  0x90
+#define VT1603_R91  0x91
+#define VT1603_R92  0x92
+#define VT1603_R93  0x93
+#define VT1603_R95  0x95
+#define VT1603_R96  0x96
+#define VT1603_R97  0x97
+
+#define VT1603_IRQ IRQ_GPIO
+
+struct vt1603_setup_data {
+	int i2c_bus;
+	unsigned short i2c_address;
+};
+
+//extern struct snd_soc_dai vt1603_dai;
+//extern struct snd_soc_codec_device soc_codec_dev_vt1603;
+
+#endif
diff --git a/board/wmt/wmt_battery/gauge/vt1603/vt1603_battery.c b/board/wmt/wmt_battery/gauge/vt1603/vt1603_battery.c
new file mode 100755
index 0000000..0c107c9
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/vt1603/vt1603_battery.c
@@ -0,0 +1,639 @@
+/*
+ * Copyright (C) 2013  WonderMedia Technologies, Inc.  
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/arch/common_def.h>
+#include <asm/errno.h>
+
+#include "../../../include/wmt_pmc.h"
+#include "../../../include/wmt_spi.h"
+#include "../../../include/wmt_clk.h"
+#include "../../../include/wmt_gpio.h"
+
+#include "../../wmt_battery.h"
+
+#include "vt1603_battery.h"
+#include "vt1603.h"
+
+#define CONFIG_VT1603_BATTERY
+
+//#define BAT_DEBUG
+
+#undef dbg
+#undef dbg_err
+#ifdef  BAT_DEBUG
+#define dbg(fmt, args...) printf("[%s]_%d: " fmt, __func__ , __LINE__, ## args)
+#else
+#define dbg(fmt, args...)
+#endif
+
+#define dbg_err(fmt, args...) printf("## VT1603A/VT1609 BAT##: " fmt,  ## args)
+
+extern int auto_pll_divisor(enum dev_id dev, enum clk_cmd cmd, int unit, int freq);
+
+static int vt1603_spi_write(u8 addr, const u8 data)
+{
+	u8 wbuf[3], rbuf[3];
+
+	wbuf[0] = ((addr & 0xFF) | BIT7);
+	wbuf[1] = ((addr & 0xFF) >> 7);
+	wbuf[2] = data;
+
+	spi_write_then_read_data(wbuf, rbuf, sizeof(wbuf),
+				 SPI_MODE_3, 0);
+
+	udelay(10);
+	return 0;
+}
+
+static int vt1603_spi_read(u8 addr, u8 *data)
+{
+	u8 wbuf[5] = {0};
+	u8 rbuf[5] = {0};
+
+	memset(wbuf,0,sizeof(wbuf));
+	memset(rbuf,0,sizeof(rbuf));
+
+	wbuf[0] = ((addr & 0xFF) & (~BIT7));
+	wbuf[1] = ((addr & 0xFF) >> 7);
+
+	spi_write_then_read_data(wbuf, rbuf, sizeof(wbuf),
+				 SPI_MODE_3, 0);
+
+	if (0) {
+		int i;
+		for (i = 0; i < sizeof(rbuf); i++)
+			printf("0x%02x ", rbuf[i]);
+		printf("\n");
+	}
+	data[0] = rbuf[4];
+	return 0;
+}
+
+/*
+ * vt1603_set_reg8 - set register value of vt1603
+ * @bat_drv: vt1603 driver data
+ * @reg: vt1603 register address
+ * @val: value register will be set
+ */
+static int vt1603_set_reg8(u8 reg, u8 val)
+{
+	int ret =0;
+
+	ret = vt1603_spi_write(reg,val);
+	if(ret < 0){
+		dbg_err("vt1603 battery write error, errno%d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * vt1603_get_reg8 - get register value of vt1603
+ * @bat_drv: vt1603 driver data
+ * @reg: vt1603 register address
+ */
+static u8 vt1603_get_reg8(u8 reg)
+{
+	u8 val = 0;
+	int ret = 0;
+
+	ret = vt1603_spi_read(reg,&val);
+	if (ret < 0){
+		dbg_err("vt1603 battery read error, errno%d\n", ret);
+		return 0;
+	}
+
+	return val;
+}
+
+
+static int vt1603_read8(u8 reg,u8* data)
+{
+	int ret = 0;
+
+	ret = vt1603_spi_read(reg,data);
+	if (ret < 0){
+		dbg_err("vt1603 battery read error, errno%d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/*
+ * vt1603_setbits - write bit1 to related register's bit
+ * @bat_drv: vt1603 battery driver data
+ * @reg: vt1603 register address
+ * @mask: bit setting mask
+ */
+static void vt1603_setbits(u8 reg, u8 mask)
+{
+	u8 tmp = vt1603_get_reg8(reg) | mask;
+	vt1603_set_reg8(reg, tmp);
+}
+
+/*
+ * vt1603_clrbits - write bit0 to related register's bit
+ * @bat_drv: vt1603 battery driver data
+ * @reg: vt1603 register address
+ * @mask:bit setting mask
+ */
+static void vt1603_clrbits(u8 reg, u8 mask)
+{
+	u8 tmp = vt1603_get_reg8(reg) & (~mask);
+	vt1603_set_reg8(reg, tmp);
+}
+
+/*
+ * vt1603_reg_dump - dubug function, for dump vt1603 related registers
+ * @bat_drv: vt1603 battery driver data
+ */
+static void __attribute__((unused)) vt1603_reg_dump(u8 addr, int len)
+{
+	u8 i;
+	for (i = addr; i < addr + len; i += 2)
+		printf("reg[%d]:0x%02X,  reg[%d]:0x%02X\n",
+		    i, vt1603_get_reg8(i),
+		    i + 1, vt1603_get_reg8(i + 1));
+}
+
+/*
+ * vt1603_get_bat_convert_data - get battery converted data
+ * @bat_drv: vt1603 battery driver data
+ */
+static int vt1603_get_bat_data(int *data)
+{
+	u8 data_l, data_h;
+
+	if (vt1603_read8(VT1603_DATL_REG, &data_l)) {
+		dbg("read VT1603_DATL_REG error!\n");
+		return -1;
+	}
+
+	if (vt1603_read8(VT1603_DATH_REG, &data_h)) {
+		dbg("red VT1603_DATH_REG error!\n");
+		return -1;
+	}
+
+	*data = ADC_DATA(data_l, data_h);
+	return 0;
+}
+
+/*
+ * vt1603_work_mode_switch - switch VT1603 to battery mode
+ * @bat_drv: vt1603 battery driver data
+ */
+static void vt1603_switch_to_bat_mode(void)
+{
+	dbg("Enter\n");
+	vt1603_set_reg8(VT1603_CR_REG, 0x00);
+	vt1603_set_reg8(VT1603_AMCR_REG, BIT0);
+	dbg("Exit\n");
+}
+
+/*
+ * vt1603_get_pen_state - get touch panel pen state from vt1603
+ *         interrup status register
+ * @bat_drv: vt1603 battery driver data
+ */
+static inline int vt1603_get_pen_state(void)
+{
+	u8 state = vt1603_get_reg8(VT1603_INTS_REG);
+	return (((state & BIT4) == 0) ? TS_PENDOWN_STATE : TS_PENUP_STATE);
+}
+
+static inline void vt1603_bat_pen_manual(void)
+{
+	vt1603_setbits(VT1603_INTCR_REG, BIT7);
+}
+
+static void vt1603_bat_power_up(void)
+{
+	if (vt1603_get_reg8(VT1603_PWC_REG) != 0x08)
+		vt1603_set_reg8(VT1603_PWC_REG, 0x08);
+
+	return ;
+}
+
+static int vt1603_bat_avg(int *data, int num)
+{
+	int i = 0;
+	int avg = 0;
+
+	if(num == 0)
+		return 0;
+
+	for (i = 0; i < num; i++)
+		avg += data[i];
+
+	return (avg / num);
+}
+
+static int vt1603_read_adc(int *value)
+{
+	int timeout, i = 0;
+	int bat_arrary[DFLT_BAT_VAL_AVG]={0};
+	int ret = 0;
+
+	dbg("Enter\n");
+
+	// enable sar-adc power and clock
+	vt1603_bat_power_up();
+	// enable pen down/up to avoid miss irq
+	vt1603_bat_pen_manual();
+	// switch vt1603 to battery detect mode
+	vt1603_switch_to_bat_mode();
+	// do conversion use battery manual mode
+	vt1603_setbits(VT1603_INTS_REG, BIT0);
+	vt1603_set_reg8(VT1603_CR_REG, BIT4);
+
+	dbg("before VT1603_INTS_REG=%x\n", vt1603_get_reg8(VT1603_INTS_REG));
+
+	for (i=0; i<DFLT_BAT_VAL_AVG; i++) {
+		timeout = 2000;
+		while(--timeout && (vt1603_get_reg8(VT1603_INTS_REG) & BIT0)==0)
+			/* wait for irq */;
+
+		if(timeout){
+			ret = vt1603_get_bat_data(&bat_arrary[i]);
+			if(ret < 0) {
+				dbg_err("vt1603 get bat adc data Failed!\n");
+				goto out;
+			}
+
+			vt1603_setbits(VT1603_INTS_REG, BIT0);
+			vt1603_set_reg8(VT1603_CR_REG, BIT4);//start manual ADC mode
+		} else {
+			dbg_err("wait adc end timeout ?!\n");
+			ret = -1;
+			goto out;
+		}
+	}
+
+	*value = vt1603_bat_avg(bat_arrary, DFLT_BAT_VAL_AVG);
+
+out:
+	vt1603_clrbits(VT1603_INTCR_REG, BIT7);
+	vt1603_setbits(VT1603_INTS_REG, BIT0 | BIT3);
+	vt1603_set_reg8(VT1603_CR_REG, BIT1);
+	dbg("Exit\n\n\n");
+	return ret;
+}
+
+/*
+ * vt1603_get_bat_info - get battery status, API for wmt_battery.c
+ */
+int vt1603_read_voltage(void)
+{
+	int volt_mV;
+	int rc;
+
+	rc = vt1603_read_adc(&volt_mV);
+	if (rc < 0) {
+		printf("vt1603 read voltage failed\n");
+		return -1;
+	}
+
+	printf("vt1603 read voltage: %d mV\n", volt_mV);
+	return volt_mV;
+}
+
+/*
+ * vt1603_ts_reset - reset vt1603, auto postition conversion mode,
+ *     do self calibration if enable
+ */
+static void vt1603_ts_reset(void)
+{
+	/* power control enable */
+	vt1603_set_reg8(VT1603_PWC_REG, 0x18);
+
+	/* clock divider */
+	vt1603_set_reg8(VT1603_CDPR_REG, 0x08);
+
+	/* clean debug register,for some 2 layer PCB machine enter debug mode unexpected */
+	vt1603_set_reg8(VT1603_DCR_REG, 0x00);
+
+
+	vt1603_set_reg8(VT1603_INTEN_REG,  BIT1);//Just Enable pendown IRQ
+
+	// auto position conversion mode and panel type config
+	/*if (ts_pdata->panel_type== PANEL_TYPE_4WIRED)
+	  vt1603_set_reg8(ts_drv, VT1603_CR_REG, BIT1);
+	  else*/
+	vt1603_set_reg8(VT1603_CR_REG, BIT1 | BIT0);
+
+	// interrupt control, pen up/down detection enable
+	vt1603_set_reg8(VT1603_INTCR_REG, 0xff);
+
+	// mask other module interrupts
+	vt1603_set_reg8(VT1603_IMASK_REG27, 0xff);
+	vt1603_set_reg8(VT1603_IMASK_REG28, 0xFF);
+	vt1603_set_reg8(VT1603_IMASK_REG29, 0xFF);
+	/* reset headphone detect irq */
+	vt1603_set_reg8(VT1603_IMASK_REG27, 0xfd);
+
+	vt1603_setbits(VT1603_IPOL_REG33, BIT5);
+
+	vt1603_set_reg8(VT1603_ISEL_REG36, 0x04);/* vt1603 gpio1 as IRQ output */
+	// clear irq
+	//vt1603_clr_ts_irq(0x0F);
+	vt1603_setbits(VT1603_INTS_REG, 0x0F);
+	dbg("ok...\n");
+
+	return;
+}
+
+static inline void i2s_pin_config(void)
+{
+	/* disable GPIO and Pull Down mode */
+	GPIO_CTRL_GP10_I2S_BYTE_VAL &= ~0xFF;
+	GPIO_CTRL_GP11_I2S_BYTE_VAL &= ~(BIT0 | BIT1 | BIT2);
+
+	PULL_EN_GP10_I2S_BYTE_VAL &= ~0xFF;
+	PULL_EN_GP11_I2S_BYTE_VAL &= ~(BIT0 | BIT1 | BIT2);
+
+	/* set to 2ch input, 2ch output */
+	PIN_SHARING_SEL_4BYTE_VAL &= ~(BIT13 | BIT14 | BIT15 | BIT17 | BIT19 | BIT20 | BIT22);
+	PIN_SHARING_SEL_4BYTE_VAL |= (BIT1 | BIT16 | BIT18 | BIT21);
+}
+
+static inline void i2s_clk_config(void)
+{
+	/* set to 11.288MHz */
+	auto_pll_divisor(DEV_I2S, CLK_ENABLE , 0, 0);
+	auto_pll_divisor(DEV_I2S, SET_PLLDIV, 1, 11288);
+
+	/* Enable BIT4:ARFP clock, BIT3:ARF clock */
+	PMCEU_VAL |= (BIT4 | BIT3);
+
+	/* Enable BIT2:AUD clock */
+	PMCE3_VAL |= BIT2;
+}
+
+static int vt1603_bat_probe(void)
+{
+	i2s_pin_config();
+	i2s_clk_config();
+
+	vt1603_ts_reset();
+
+	//vt1603_reg_dump(0xc0, 12);
+
+	return 0;
+}
+
+struct bias_data {
+	int normal;
+	int max;
+};
+
+static struct bias_data bias_adapter[10];
+
+static int parse_bias_data(void)
+{
+	char *s;
+	char *endp;
+	int i;
+
+	struct bias_data *bias = bias_adapter;
+
+	s = getenv("wmt.io.bateff.adapter");
+	if (!s) {
+		printf("no wmt.io.bateff.adapter param!\n");
+		return -EINVAL;
+	}
+
+	// parse from the valid val
+	for (i = 9; i >= 0 ; i--) {
+		bias[i].normal = simple_strtoul(s, &endp, 16);
+		if (*endp == '\0')
+			break;
+		s = endp + 1;
+		if (*s == '\0')
+			break;
+
+		bias[i].max = simple_strtoul(s, &endp, 16);
+		if (*endp == '\0')
+			break;
+		s = endp + 1;
+		if (*s == '\0')
+			break;
+	}
+
+	if ((i != 0) && (i != 5)) {
+		printf("Error to get charging u-boot argument.! i = %d\n", i);
+		return -1;
+	}
+
+	return 0;
+}
+
+static int getEffect(int adc, int usage, struct bias_data *bias, int size)
+{
+	int effect, i;
+
+	for (i = 0; i < size; i++) {
+		if (adc <= bias[i].max) {
+			effect = (bias[i].max - bias[i].normal) * usage / 100;
+			return effect;
+		}
+	}
+
+	effect = bias[size-1].max - bias[size-1].normal;
+
+	if (size > 0)
+		return effect * usage / 100;
+
+	return 0;
+}
+
+static int adc_repair(int adc_val)
+{
+	int adc_add = adc_val;
+
+	if (wmt_is_dc_plugin()) {
+		adc_add -= getEffect(adc_val, 100, bias_adapter, ARRAY_SIZE(bias_adapter));
+	}
+
+	return adc_add;
+}
+
+static int volt_grade[11];
+
+static int parse_bat_level(void)
+{
+	char *s;
+	char *endp;
+	int i = 0;
+
+	s = getenv("wmt.io.bat");
+	if (!s) {
+		printf("no wmt.io.bat param!\n");
+		return -EINVAL;
+	}
+
+	// skip 5 val
+	while ((i < 5) && (*s != '\0')) {
+		if (*s==':') {
+			i++;
+		}
+		s++;
+	}
+
+	if ((i != 5) || (!s) || (*s == '\0')) {
+		printf("wmt.io.bat param format error!\n");
+		return -1;
+	}
+
+	// parse from the valid val
+	for (i = 10; i >= 0; i--) {
+		volt_grade[i] = simple_strtoul(s, &endp, 16);
+		if (*endp == '\0')
+			break;
+		s = endp + 1;
+
+		if (*s == '\0')
+			break;
+	}
+
+	if (i) {
+		printf("parse wmt.io.bat failed!\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int adc_to_capacity(int adc_val)
+{
+	int capacity = 0;
+
+	if (adc_val <= volt_grade[0]) {
+		capacity = 0;
+	} else if (adc_val >= volt_grade[10]) {
+		capacity = 100;
+	} else {
+		int i;
+		for (i = 10; i >= 1 ; i--) {
+			if ((adc_val<=volt_grade[i])&&(adc_val>volt_grade[i-1])) {
+				capacity = ((adc_val-volt_grade[i-1]) * 10) /
+						(volt_grade[i]-volt_grade[i-1]) + (i-1)*10;
+			}
+		}
+	}
+
+	return capacity;
+}
+
+int vt1603_read_capacity(void)
+{
+	int adc0, adc1;
+	int cap0;
+	static int max_capacity = -1;
+
+	adc0 = vt1603_read_voltage();
+	if (adc0 < 0) {
+		printf("read raw adc failed\n");
+		return adc0;
+	}
+	printf("adc0 %dmV\n",adc0);
+
+	adc1 = adc_repair(adc0);
+	printf("adc1 %dmV\n",adc1);
+
+	cap0 = adc_to_capacity(adc1);
+	printf("cap0 %d\n", cap0);
+
+	// use the max capacity while charging.
+	if (!wmt_is_dc_plugin() ||
+	    max_capacity < cap0 || max_capacity > cap0 + 5)
+			max_capacity = cap0;
+
+	printf("max_capacity %d\n", max_capacity);
+	return max_capacity;
+}
+
+int vt1603_batt_init(void)
+{
+	if (parse_bias_data())
+		return -EINVAL;
+
+	if (parse_bat_level())
+		return -EINVAL;
+
+	return vt1603_bat_probe();
+}
+
+int vt1603_check_bl(void)
+{
+	int rc;
+	int volt_mV;
+	int low_mV;
+
+	rc = vt1603_read_adc(&volt_mV);
+	if (rc < 0) {
+		printf("vt1603 read voltage failed\n");
+		return -EIO;
+	}
+
+	if (wmt_is_dc_plugin())
+		low_mV = adc_repair(volt_grade[0]);
+	else {
+	/* FIXME Work around for the situation that android poweroff by
+	 * capcity 0, but uboot do not report low battery. */
+		low_mV = (volt_grade[0] + volt_grade[1]) / 2;
+	}
+
+	printf("current voltage %d, low bat %d, capacity %d\n",
+	       volt_mV, low_mV, vt1603_read_capacity());
+	return volt_mV < low_mV;
+}
+
+static int do_adc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int i;
+
+	parse_bias_data();
+	parse_bat_level();
+
+	for (i = 0; i < ARRAY_SIZE(bias_adapter); i++) {
+		printf("bias adapater [%2d]: %d -> %d (%d) mV\n",
+		       i, bias_adapter[i].normal, bias_adapter[i].max,
+		       bias_adapter[i].max - bias_adapter[i].normal);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(volt_grade); i++) {
+		printf("voltage[%2d] - %d(%dmV)\n", i, volt_grade[i], (volt_grade[i] * 1047) / 1000);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	adc,	4,	1,	do_adc,	\
+	"adc: display battery capacity\n",	\
+	"" \
+);
+
+struct battery_dev vt1603_battery_dev = {
+		.name		= "vt1603",
+		.is_gauge	= 0,
+		.init		= vt1603_batt_init,
+		.get_capacity	= vt1603_read_capacity,
+		.get_voltage	= vt1603_read_voltage,
+		.check_batlow	= vt1603_check_bl,
+};
diff --git a/board/wmt/wmt_battery/gauge/vt1603/vt1603_battery.h b/board/wmt/wmt_battery/gauge/vt1603/vt1603_battery.h
new file mode 100755
index 0000000..0c4600f
--- /dev/null
+++ b/board/wmt/wmt_battery/gauge/vt1603/vt1603_battery.h
@@ -0,0 +1,119 @@
+/*++
+	Copyright (c) 2008  WonderMedia Technologies, Inc.
+
+	This program is free software: you can redistribute it and/or modify it under the
+	terms of the GNU General Public License as published by the Free Software Foundation,
+	either version 2 of the License, or (at your option) any later version.
+
+	This program is distributed in the hope that it will be useful, but WITHOUT
+	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+	PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+	You should have received a copy of the GNU General Public License along with
+	this program.  If not, see <http://www.gnu.org/licenses/>.
+
+	WonderMedia Technologies, Inc.
+	10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef __VT1603_BAT_H__
+#define __VT1603_BAT_H__
+
+#define POLL_TOUT                  100
+#define DFLT_POLLING_BAT_INTERVAL  10
+#define VT1603_BAT_DRIVER	"vt1603_bat"
+#define ADC_DATA(low, high)	((((high) & 0x0F) << 8) + (low))
+
+/* VT1603 touch panel state  */
+#define TS_PENDOWN_STATE      0x00
+#define TS_PENUP_STATE        0x01
+
+/* vt1603 bus type config    */
+#define VT1603_MAX_SPI_CLK    (20*1000*1000)
+#define SPI_DEFAULT_CLK       (12*1000*1000)
+#define IDLE_DATA_NUM         5
+#define VT1603_SPI_FIX_CS     0x00
+#define VT1603_SPI_FAKE_CS    3 //(0x7F - 1)
+#define VT1603_SPI_BUS_0      0x00
+#define VT1603_SPI_BUS_1      0x01
+#define VT1603_REG_OP_R       0x00
+#define VT1603_REG_OP_W       0x01
+
+
+#define VT1603_I2C_FIX_ADDR   0x1A
+#define VT1603_I2C_FAKE_ADDR  0xEE
+#define VT1603_I2C_WCMD       0x00
+#define VT1603_I2C_RCMD       0x01
+#define VT1603_I2C_RWCMD      0x02
+#define VT1603_I2C_BUS_0      0x00
+#define VT1603_I2C_BUS_1      0x01
+
+
+#define BA_WAKEUP_SRC_0       BIT0
+#define BA_WAKEUP_SRC_1       BIT1
+#define BA_WAKEUP_SRC_2       BIT2
+#define BA_WAKEUP_SRC_3       BIT3
+
+#define I2C_BUS    		0
+#define SPI_BUS    		1
+#define DFLT_BAT_VAL_AVG	10
+#define VT1603_FIFO_LEN		3
+
+/* VT1603 Register address */
+#define VT1603_BTHD_REG       0x78
+#define VT1603_BCLK_REG       0x88
+#define VT1603_BAEN_REG       0x04
+
+#define VT1603_PWC_REG        0xC0
+#define VT1603_CR_REG         0xC1
+#define VT1603_CCCR_REG       0xC2
+#define VT1603_CDPR_REG       0xC3
+#define VT1603_TSPC_REG       0xC4
+#define VT1603_AMCR_REG       0xC7
+#define VT1603_INTCR_REG      0xC8
+#define VT1603_INTEN_REG      0xC9
+#define VT1603_INTS_REG       0xCA
+#define VT1603_DCR_REG        0xCB
+
+#define VT1603_TODCL_REG      0xCC
+#define VT1603_TODCH_REG      0xCD
+
+#define VT1603_DATL_REG       0xCE
+#define VT1603_DATH_REG       0xCF
+
+#define VT1603_XPL_REG        0xD0
+#define VT1603_XPH_REG        0xD1
+#define VT1603_YPL_REG        0xD2
+#define VT1603_YPH_REG        0xD3
+
+#define VT1603_BATL_REG       0xD4
+#define VT1603_BATH_REG       0xD5
+
+#define VT1603_TEMPL_REG      0xD6
+#define VT1603_TEMPH_REG      0xD7
+
+#define VT1603_ERR8_REG       0xD8
+#define VT1603_ERR7_REG       0xD9
+#define VT1603_ERR6_REG       0xDA
+#define VT1603_ERR5_REG       0xDB
+#define VT1603_ERR4_REG       0xDC
+#define VT1603_ERR3_REG       0xDD
+#define VT1603_ERR2_REG       0xDE
+#define VT1603_ERR1_REG       0xDF
+
+#define VT1603_DBG8_REG       0xE0
+#define VT1603_DBG7_REG       0xE1
+#define VT1603_DBG6_REG       0xE2
+#define VT1603_DBG5_REG       0xE3
+#define VT1603_DBG4_REG       0xE4
+#define VT1603_DBG3_REG       0xE5
+#define VT1603_DBG2_REG       0xE6
+#define VT1603_DBG1_REG       0xE7
+
+/* for VT1603 GPIO1 interrupt setting */
+#define VT1603_IMASK_REG27    27
+#define VT1603_IMASK_REG28    28
+#define VT1603_IMASK_REG29    29
+#define VT1603_IPOL_REG33     33
+#define VT1603_ISEL_REG36     36
+
+#endif  /* __VT1603_TS_H__ */
diff --git a/board/wmt/wmt_battery/wmt_battery.c b/board/wmt/wmt_battery/wmt_battery.c
new file mode 100755
index 0000000..dac30ee
--- /dev/null
+++ b/board/wmt/wmt_battery/wmt_battery.c
@@ -0,0 +1,434 @@
+/*
+ * Copyright (c) 2014  WonderMedia Technologies, Inc.  
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.  
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.  
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/errno.h>
+
+#include "../include/wmt_iomux.h"
+#include "wmt_battery.h"
+
+#define return_val_if_failed(val, expr)					\
+do {									\
+	if (!(expr)) {							\
+		printf(" %s, %d, Warnning: " #expr " failed.\n",	\
+		       __FUNCTION__, __LINE__);				\
+		return val;						\
+	}								\
+} while(0)
+
+struct battery_param {
+	struct battery_dev *bat_dev;
+};
+
+struct charger_param {
+	struct charger_dev *chg_dev;
+};
+
+static struct battery_param battery_param;
+static struct charger_param charger_param;
+
+static int full_by_hw = 0;
+
+static struct battery_dev *battery_devices[] = {
+	&vt1603_battery_dev,
+	&ug31xx_battery_dev,
+	&ug3102_battery_dev,
+	&sp2541_battery_dev,
+	&bq_battery_dev,
+	NULL,
+};
+
+static struct charger_dev *charger_devices[] = {
+	&mp2625_charger_dev,
+	&g2214_charger_dev,
+	NULL,
+};
+
+static int parse_charger_param(struct charger_param *cp)
+{
+	static const char uboot_env[] = "wmt.charger.param";
+	struct charger_dev **dev = &charger_devices[0];
+	char *env;
+	
+	if (!(env = getenv((char *)uboot_env))) {
+		printf("please setenv %s\n", uboot_env);
+		return -EINVAL;
+	}
+
+	while (*dev) {
+		if ((*dev)->name &&
+		    !strncmp((*dev)->name, env, strlen((*dev)->name)))
+			break;
+		++dev;
+	}
+
+	if (!(*dev))
+		return -EINVAL;
+
+	cp->chg_dev = *dev;
+	printf("Charger matched: %s\n", cp->chg_dev->name);
+	return 0;
+}
+
+static int parse_battery_param(struct battery_param *bp)
+{
+	static const char uboot_env[] = "wmt.battery.param";
+	struct battery_dev **dev = &battery_devices[0];
+	char *env;
+	
+	if (!(env = getenv((char *)uboot_env))) {
+		printf("please setenv %s\n", uboot_env);
+		return -EINVAL;
+	}
+
+	while (*dev) {
+		if ((*dev)->name &&
+		    !strncmp((*dev)->name, env, strlen((*dev)->name)))
+			break;
+		++dev;
+	}
+
+	if (!(*dev))
+		return -EINVAL;
+
+	bp->bat_dev = *dev;
+	printf("Battery matched: %s\n", bp->bat_dev->name);
+	return 0;
+}
+
+static int parse_battery_full_param(void)
+{
+	static const char uboot_env[] = "wmt.bat.hwfull";
+	char *env;
+	
+	if (!(env = getenv((char *)uboot_env))) {
+		full_by_hw = 0;
+		return -EINVAL;
+	}
+
+	full_by_hw = simple_strtol(env, NULL, 10);
+	printf("full_by_hw %d\n", full_by_hw);
+	return 0;
+}
+
+static struct {
+	int charging;
+	int full;
+	int led_power;
+	int led_gpio_level;
+} charger_led;
+
+static int parse_charger_led(void)
+{
+	enum {
+		idx_id,
+		idx_v1,
+		idx_v2,
+		idx_max,
+	};
+	long ps[idx_max];
+	char *p, *endp;
+	int i = 0;
+
+	// initialize as invalid gpio
+	charger_led.charging = -1;
+	charger_led.full     = -1;
+	charger_led.led_power = -1;
+
+	p = getenv("wmt.charger.led");
+	if (!p)
+		return -EINVAL;
+
+	while (i < idx_max) {
+		ps[i++] = simple_strtol(p, &endp, 10);
+		if (*endp == '\0')
+			break;
+		p = endp + 1;
+		if (*p == '\0')
+			break;
+	}
+
+	if (i != 3)
+		return -EINVAL;
+
+	switch (ps[idx_id]) {
+	case 0:
+		charger_led.led_power = ps[idx_v1];
+		charger_led.led_gpio_level = ps[idx_v2];
+		printf("charger led power: %d (%d)\n",
+		       charger_led.led_power, charger_led.led_gpio_level);
+		break;
+	case 1:
+		charger_led.charging = ps[idx_v1];
+		charger_led.full     = ps[idx_v2];
+		printf("charger led pin: charging %d, full %d\n",
+		       charger_led.charging, charger_led.full);
+		break;
+	default:
+		printf("no valid charger led found\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int wmt_power_supply_init(void)
+{
+	struct charger_param *cp = &charger_param;
+	struct battery_param *bp = &battery_param;
+	static int inited = 0;
+
+	if (inited)
+		return 0;
+	++inited;
+
+	if (parse_charger_param(cp)) {
+		pr_err("charger not found\n");
+		return -ENODEV;
+	}
+	if (cp->chg_dev->init()) {
+		pr_err("%s init failed\n", cp->chg_dev->name);
+		return -EIO;
+	}
+
+	if (parse_battery_param(bp)) {
+		pr_err("cattery not found\n");
+		return -ENODEV;
+	}
+	if (bp->bat_dev->init()) {
+		pr_err("%s init failed\n", bp->bat_dev->name);
+		return -EIO;
+	}
+
+	parse_charger_led();
+	parse_battery_full_param();
+
+	return 0;
+}
+
+int pmic_init(void)
+{
+	if (is_g2214_avail() != -1)
+		g2214_pmic_init();
+	return 0;
+}
+
+static inline void led_enable(int gpio, int enable)
+{
+	if (gpio_is_valid(gpio)) {
+		if (enable)
+			gpio_direction_output(gpio, 1);
+		else {
+			gpio_direction_output(gpio, 0);
+
+			/* walkaround for hardware bug.
+			 * set gpio to input to let led off.
+			 */
+			gpio_direction_input(gpio);
+		}
+	}
+}
+
+static inline void led_power_enable(int enable)
+{
+	int gpio = charger_led.led_power;
+
+	if (gpio_is_valid(gpio)) {
+		if (enable)
+			gpio_direction_output(gpio, charger_led.led_gpio_level);
+		else
+			gpio_direction_output(gpio, !charger_led.led_gpio_level);
+	}
+}
+
+int wmt_charger_event_callback(enum event_type event)
+{
+	struct charger_dev *dev = charger_param.chg_dev;
+
+	return_val_if_failed(-1, dev != NULL);
+	return_val_if_failed(-1, dev->event_proc);
+
+	printf(" ## %s, %d\n", __func__, event);
+
+	switch (event) {
+	case POWER_EVENT_DCDET_ADAPTER:
+	case POWER_EVENT_CHARGING:
+		led_power_enable(1);
+		if (wmt_battery_is_charging_full()) {
+			led_enable(charger_led.charging, 0);
+			led_enable(charger_led.full, 1);
+		} else {
+			led_enable(charger_led.charging, 1);
+			led_enable(charger_led.full, 0);
+		}
+		break;
+	case POWER_EVENT_DCDET_USBPC:
+		if (wmt_charger_pc_charging()) {
+			led_power_enable(1);
+			if (wmt_battery_is_charging_full()) {
+				led_enable(charger_led.charging, 0);
+				led_enable(charger_led.full, 1);
+			} else
+				led_enable(charger_led.charging, 1);
+		} else {
+			led_power_enable(0);
+			led_enable(charger_led.charging, 0);
+		}
+		led_enable(charger_led.full, 0);
+		break;
+	case POWER_EVENT_DCDET_PLUGOUT:
+	case POWER_EVENT_DISCHARGING:
+		led_power_enable(0);
+		led_enable(charger_led.charging, 0);
+		led_enable(charger_led.full, 0);
+		break;
+	case POWER_EVENT_CHARGING_FULL:
+		led_power_enable(1);
+		led_enable(charger_led.charging, 0);
+		led_enable(charger_led.full, 1);
+		break;
+	default:
+		break;
+	}
+
+	return dev->event_proc(event);
+}
+
+int wmt_charger_cable_type(void)
+{
+	struct charger_dev *dev = charger_param.chg_dev;
+
+	return_val_if_failed(-1, dev != NULL);
+	return_val_if_failed(-1, dev->cable_type);
+
+	return dev->cable_type();
+}
+
+int wmt_charger_pc_charging(void)
+{
+	struct charger_dev *dev = charger_param.chg_dev;
+
+	return_val_if_failed(-1, dev != NULL);
+
+	return (dev->pc_charging) ? dev->pc_charging() : 0;
+}
+
+int wmt_battery_get_capacity(void)
+{
+	struct battery_dev *dev = battery_param.bat_dev;
+	static unsigned int ref_full = 0;
+	int capacity;
+
+	return_val_if_failed(-1, dev != NULL);
+	return_val_if_failed(-1, dev->get_capacity);
+
+	capacity = dev->get_capacity();
+
+	if (!wmt_battery_is_gauge()) {
+
+		if (full_by_hw) {
+			if (wmt_battery_is_charging_full())
+				return capacity;
+			else if (capacity == 100)
+				return 99;
+		}
+
+		if (capacity == 100 && !wmt_battery_is_charging_full()) {
+			if (ref_full < 30 * 60) {
+				capacity = 99;
+				ref_full++;
+			} else
+				printf("ref full %d, 30 minutes, report full\n", ref_full);
+		} else
+			ref_full = 0;
+
+		printf("-> %d, ref full %d\n", capacity, ref_full);
+	}
+
+	return capacity;
+}
+
+int wmt_battery_get_voltage(void)
+{
+	struct battery_dev *dev = battery_param.bat_dev;
+
+	return_val_if_failed(-1, dev != NULL);
+	return_val_if_failed(-1, dev->get_voltage);
+
+	return dev->get_voltage();
+}
+
+int wmt_battery_get_current(void)
+{
+	struct battery_dev *dev = battery_param.bat_dev;
+
+	return_val_if_failed(-1, dev != NULL);
+	return_val_if_failed(-1, dev->get_current);
+
+	return dev->get_current();
+}
+
+int wmt_battery_is_lowlevel(void)
+{
+	struct battery_dev *dev = battery_param.bat_dev;
+
+	return_val_if_failed(-1, dev != NULL);
+	return_val_if_failed(-1, dev->check_batlow);
+
+	return dev->check_batlow();
+}
+
+int wmt_battery_is_charging_full(void)
+{
+	struct charger_dev *dev = charger_param.chg_dev;
+
+	return_val_if_failed(-1, dev != NULL);
+	return_val_if_failed(-1, dev->check_full);
+
+	if (!wmt_is_dc_plugin())
+		return -1;
+
+	return dev->check_full();
+}
+
+int wmt_battery_is_gauge(void)
+{
+	struct battery_dev *dev = battery_param.bat_dev;
+
+	return_val_if_failed(-1, dev != NULL);
+
+	return dev->is_gauge;
+}
+
+static int do_batt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	wmt_power_supply_init();
+
+	printf(" voltage %d mV\n", wmt_battery_get_voltage());
+	printf(" capacity %d\n", wmt_battery_get_capacity());
+	printf(" dinc     %d\n", wmt_is_dc_plugin());
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	batt,	1,	1,	do_batt,
+	"batt  - print Board Info structure\n",
+	NULL
+);
+
diff --git a/board/wmt/wmt_battery/wmt_battery.h b/board/wmt/wmt_battery/wmt_battery.h
new file mode 100755
index 0000000..48bc28d
--- /dev/null
+++ b/board/wmt/wmt_battery/wmt_battery.h
@@ -0,0 +1,93 @@
+#ifndef __BOARD_WMT_BATTERY_H__
+#define __BOARD_WMT_BATTERY_H__
+
+#include "../include/common_def.h"
+#include "../include/wmt_pmc.h"
+
+#define pr_debug(fmt, args...)	printf(fmt, ##args)
+#define pr_err(fmt, args...)	printf(fmt, ##args)
+
+enum cable_type {
+	CABLE_TYPE_DC,
+	CABLE_TYPE_USB,
+	CABLE_TYPE_UNKNOWN,
+};
+
+enum event_type {
+	POWER_EVENT_DCDET_ADAPTER,
+	POWER_EVENT_DCDET_USBPC,
+	POWER_EVENT_DCDET_PLUGOUT,
+	POWER_EVENT_LCDON,
+	POWER_EVENT_LCDOFF,
+	POWER_EVENT_DISCHARGING,
+	POWER_EVENT_CHARGING,
+	POWER_EVENT_CHARGING_FULL,
+	POWER_EVENT_UNKNOWN,
+};
+
+struct charger_dev {
+	const char	*name;
+	enum cable_type (*cable_type)	(void);
+	int		(*init)		(void);
+	int		(*check_full)	(void);
+	int		(*pc_charging)	(void);
+	int		(*event_proc)	(enum event_type event);
+} __attribute__((aligned(4)));
+
+struct battery_dev {
+	const char	*name;
+	int		is_gauge;
+	int		(*init)		(void);
+	int		(*get_capacity)	(void);
+	int		(*get_voltage)	(void);
+	int		(*get_current)	(void);
+	int		(*check_batlow)	(void);
+} __attribute__((aligned(4)));
+
+static inline int wmt_is_dc_plugin(void)
+{
+	return (DCDET_STS_VAL & 0x00000100) ? 1 : 0;
+}
+
+static inline int prefixcmp(const char *str, const char *prefix)
+{
+	for (; ; str++, prefix++)
+		if (!*prefix)
+			return 0;
+		else if (*str != *prefix)
+			return (unsigned char)*prefix - (unsigned char)*str;
+}
+
+extern void do_wmt_poweroff(void);
+extern int wmt_power_supply_init(void);
+
+/* use below function if wmt_power_supply_init() successed */
+
+extern int wmt_charger_small_current(void);
+extern int wmt_charger_large_current(void);
+extern int wmt_charger_cable_type(void);
+extern int wmt_charger_pc_charging(void);
+extern int wmt_charger_event_callback(enum event_type event);
+
+extern int wmt_battery_get_capacity(void);
+extern int wmt_battery_get_current(void);
+extern int wmt_battery_get_voltage(void);
+extern int wmt_battery_is_lowlevel(void);
+extern int wmt_battery_is_charging_full(void);
+extern int wmt_battery_is_gauge(void);
+
+extern struct charger_dev g2214_charger_dev;
+extern struct charger_dev mp2625_charger_dev;
+
+extern struct battery_dev vt1603_battery_dev;
+extern struct battery_dev ug31xx_battery_dev;
+extern struct battery_dev ug3102_battery_dev;
+extern struct battery_dev sp2541_battery_dev;
+extern struct battery_dev bq_battery_dev;
+
+extern int is_g2214_avail(void);
+extern int g2214_pmic_init(void);
+extern int pmic_init(void);
+
+
+#endif /* #ifndef __WMT_CHARGER_H__ */
diff --git a/board/wmt/wmt_clk.c b/board/wmt/wmt_clk.c
new file mode 100755
index 0000000..3bb41a0
--- /dev/null
+++ b/board/wmt/wmt_clk.c
@@ -0,0 +1,1367 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+
+#include <common.h>
+#include "include/wmt_clk.h"
+
+#define PMC_BASE 0xD8130000
+#define PMC_PLL 0xD8130200
+#define PMC_CLK 0xD8130250
+#define PLL_BUSY 0x7F0038
+#define MAX_DF ((1<<7) - 1)
+#define MAX_DR 1 //((1<<5) - 1)
+#define MAX_DQ ((1<<2) - 1)
+#define GET_DIVF(d) ((((d>>16)&MAX_DF)+1)*2)
+#define GET_DIVR(d) (((d>>8)&MAX_DR)+1)
+#define GET_DIVQ(d) (1<<(d&MAX_DQ))
+
+#define SRC_FREQ25 25
+#define SRC_FREQ24 24
+#define SRC_FREQ SRC_FREQ24
+/*#define debug_clk*/
+static int dev_en_count[128] = {0};
+struct pll_map pllmap[] = {//total 168
+{126,		0x00290103},{129,		0x002A0103},{132,		0x002B0103},{135,		0x002C0103},{138,		0x002D0103},
+{141,		0x002E0103},{144,		0x002F0103},{147,		0x00300103},{150,		0x00310103},{153,		0x00320103},
+{156,		0x00330103},{159,		0x00340103},{162,		0x00350103},{165,		0x00360103},{168,		0x00370103},
+{171,		0x00380103},{174,		0x00390103},{177,		0x003A0103},{180,		0x003B0103},{183,		0x003C0103},
+{186,		0x003D0103},{189,		0x003E0103},{192,		0x003F0103},{195,		0x00400103},{198,		0x00410103},
+{201,		0x00420103},{204,		0x00430103},{207,		0x00440103},{210,		0x00450103},{213,		0x00460103},
+{216,		0x00470103},{219,		0x00480103},{222,		0x00490103},{225,		0x004A0103},{228,		0x004B0103},
+{231,		0x004C0103},{234,		0x004D0103},{237,		0x004E0103},{240,		0x004F0103},{243,		0x00500103},
+{246,		0x00510103},{249,		0x00520103},{252, 	0x00290102},{258, 	0x002A0102},{264, 	0x002B0102},
+{270, 	0x002C0102},{276, 	0x002D0102},{282, 	0x002E0102},{288, 	0x002F0102},{294, 	0x00300102},
+{300, 	0x00310102},{306, 	0x00320102},{312, 	0x00330102},{318, 	0x00340102},{324, 	0x00350102},
+{330, 	0x00360102},{336, 	0x00370102},{342, 	0x00380102},{348, 	0x00390102},{354, 	0x003A0102},
+{360, 	0x003B0102},{366, 	0x003C0102},{372, 	0x003D0102},{378, 	0x003E0102},{384, 	0x003F0102},
+{390, 	0x00400102},{396, 	0x00410102},{402, 	0x00420102},{408, 	0x00430102},{414, 	0x00440102},
+{420, 	0x00450102},{426, 	0x00460102},{432, 	0x00470102},{438, 	0x00480102},{444, 	0x00490102},
+{450, 	0x004A0102},{456, 	0x004B0102},{462, 	0x004C0102},{468, 	0x004D0102},{474, 	0x004E0102},
+{480, 	0x004F0102},{486, 	0x00500102},{492, 	0x00510102},{498, 	0x00520102},{504, 	0x00290101},
+{516, 	0x002A0101},{528, 	0x002B0101},{540, 	0x002C0101},{552, 	0x002D0101},{564, 	0x002E0101},
+{576, 	0x002F0101},{588, 	0x00300101},{600, 	0x00310101},{612, 	0x00320101},{624, 	0x00330101},
+{636, 	0x00340101},{648, 	0x00350101},{660, 	0x00360101},{672, 	0x00370101},{684, 	0x00380101},
+{696, 	0x00390101},{708, 	0x003A0101},{720, 	0x003B0101},{732, 	0x003C0101},{744, 	0x003D0101},
+{756, 	0x003E0101},{768, 	0x003F0101},{780, 	0x00400101},{792, 	0x00410101},{804, 	0x00420101},
+{816, 	0x00430101},{828, 	0x00440101},{840, 	0x00450101},{852, 	0x00460101},{864, 	0x00470101},
+{876, 	0x00480101},{888, 	0x00490101},{900, 	0x004A0101},{912, 	0x004B0101},{924, 	0x004C0101},
+{936, 	0x004D0101},{948, 	0x004E0101},{960, 	0x004F0101},{972, 	0x00500101},{984, 	0x00510101},
+{996, 	0x00520101},{1008,	0x00290100},{1032,	0x002A0100},{1056,	0x002B0100},{1080,	0x002C0100},
+{1104,	0x002D0100},{1128,	0x002E0100},{1152,	0x002F0100},{1176,	0x00300100},{1200,	0x00310100},
+{1224,	0x00320100},{1248,	0x00330100},{1272,	0x00340100},{1296,	0x00350100},{1320,	0x00360100},
+{1344,	0x00370100},{1368,	0x00380100},{1392,	0x00390100},{1416,	0x003A0100},{1440,	0x003B0100},
+{1464,	0x003C0100},{1488,	0x003D0100},{1512,	0x003E0100},{1536,	0x003F0100},{1560,	0x00400100},
+{1584,	0x00410100},{1608,	0x00420100},{1632,	0x00430100},{1656,	0x00440100},{1680,	0x00450100},
+{1704,	0x00460100},{1728,	0x00470100},{1752,	0x00480100},{1776,	0x00490100},{1800,	0x004A0100},
+{1824,	0x004B0100},{1848,	0x004C0100},{1872,	0x004D0100},{1896,	0x004E0100},{1920,	0x004F0100},
+{1944,	0x00500100},{1968,	0x00510100},{1992,	0x00520100}//,2016,	0x00530100
+};
+
+//total 43+88+88+172 = 391
+struct pll_map pllmapAll[] = {
+{1008,	0x00290100},{504, 	0x00290101},{252, 	0x00290102},{126,	0x00290103},
+{1032,	0x002A0100},{516, 	0x002A0101},{258, 	0x002A0102},{129,	0x002A0103},
+{1056,	0x002B0100},{528, 	0x002B0101},{264, 	0x002B0102},{132,	0x002B0103},
+{1080,	0x002C0100},{540, 	0x002C0101},{270, 	0x002C0102},{135,	0x002C0103},
+{1104,	0x002D0100},{552, 	0x002D0101},{276, 	0x002D0102},{138,	0x002D0103},
+{1128,	0x002E0100},{564, 	0x002E0101},{282, 	0x002E0102},{141,	0x002E0103},
+{1152,	0x002F0100},{576, 	0x002F0101},{288, 	0x002F0102},{144,	0x002F0103},
+{1176,	0x00300100},{588, 	0x00300101},{294, 	0x00300102},{147,	0x00300103},
+{1200,	0x00310100},{600, 	0x00310101},{300, 	0x00310102},{150,	0x00310103},
+{1224,	0x00320100},{612, 	0x00320101},{306, 	0x00320102},{153,	0x00320103},
+{1248,	0x00330100},{624, 	0x00330101},{312, 	0x00330102},{156,	0x00330103},
+{1272,	0x00340100},{636, 	0x00340101},{318, 	0x00340102},{159,	0x00340103},
+{1296,	0x00350100},{648, 	0x00350101},{324, 	0x00350102},{162,	0x00350103},
+{1320,	0x00360100},{660, 	0x00360101},{330, 	0x00360102},{165,	0x00360103},
+{1344,	0x00370100},{672, 	0x00370101},{336, 	0x00370102},{168,	0x00370103},
+{1368,	0x00380100},{684, 	0x00380101},{342, 	0x00380102},{171,	0x00380103},
+{1392,	0x00390100},{696, 	0x00390101},{348, 	0x00390102},{174,	0x00390103},
+{1416,	0x003A0100},{708, 	0x003A0101},{354, 	0x003A0102},{177,	0x003A0103},
+{1440,	0x003B0100},{720, 	0x003B0101},{360, 	0x003B0102},{180,	0x003B0103},
+{1464,	0x003C0100},{732, 	0x003C0101},{366, 	0x003C0102},{183,	0x003C0103},
+{1488,	0x003D0100},{744, 	0x003D0101},{372, 	0x003D0102},{186,	0x003D0103},
+{1512,	0x003E0100},{756, 	0x003E0101},{378, 	0x003E0102},{189,	0x003E0103},
+{1536,	0x003F0100},{768, 	0x003F0101},{384, 	0x003F0102},{192,	0x003F0103},
+{1560,	0x00400100},{780, 	0x00400101},{390, 	0x00400102},{195,	0x00400103},
+{1584,	0x00410100},{792, 	0x00410101},{396, 	0x00410102},{198,	0x00410103},
+{1608,	0x00420100},{804, 	0x00420101},{402, 	0x00420102},{201,	0x00420103},
+{1632,	0x00430100},{816, 	0x00430101},{408, 	0x00430102},{204,	0x00430103},
+{1656,	0x00440100},{828, 	0x00440101},{414, 	0x00440102},{207,	0x00440103},
+{1680,	0x00450100},{840, 	0x00450101},{420, 	0x00450102},{210,	0x00450103},
+{1704,	0x00460100},{852, 	0x00460101},{426, 	0x00460102},{213,	0x00460103},
+{1728,	0x00470100},{864, 	0x00470101},{432, 	0x00470102},{216,	0x00470103},
+{1752,	0x00480100},{876, 	0x00480101},{438, 	0x00480102},{219,	0x00480103},
+{1776,	0x00490100},{888, 	0x00490101},{444, 	0x00490102},{222,	0x00490103},
+{1800,	0x004A0100},{900, 	0x004A0101},{450, 	0x004A0102},{225,	0x004A0103},
+{1824,	0x004B0100},{912, 	0x004B0101},{456, 	0x004B0102},{228,	0x004B0103},
+{1848,	0x004C0100},{924, 	0x004C0101},{462, 	0x004C0102},{231,	0x004C0103},
+{1872,	0x004D0100},{936, 	0x004D0101},{468, 	0x004D0102},{234,	0x004D0103},
+{1896,	0x004E0100},{948, 	0x004E0101},{474, 	0x004E0102},{237,	0x004E0103},
+{1920,	0x004F0100},{960, 	0x004F0101},{480, 	0x004F0102},{240,	0x004F0103},
+{1944,	0x00500100},{972, 	0x00500101},{486, 	0x00500102},{243,	0x00500103},
+{1968,	0x00510100},{984, 	0x00510101},{492, 	0x00510102},{246,	0x00510103},
+{1992,	0x00520100},{996, 	0x00520101},{498, 	0x00520102},{249,	0x00520103},
+{2016,	0x00530100},{1008, 	0x00530101},{504, 	0x00530102},{252,	0x00530103},
+
+
+{1008,	0x00140000},	{504, 	0x00140001},	{252, 	0x00140002},	{126,	0x00140003},
+{1056,	0x00150000},	{528, 	0x00150001},	{264, 	0x00150002},	{132,	0x00150003},
+{1104,	0x00160000},	{552, 	0x00160001},	{276, 	0x00160002},	{138,	0x00160003},
+{1152,	0x00170000},	{576, 	0x00170001},	{288, 	0x00170002},	{144,	0x00170003},
+{1200,	0x00180000},	{600, 	0x00180001},	{300, 	0x00180002},	{150,	0x00180003},
+{1248,	0x00190000},	{624, 	0x00190001},	{312, 	0x00190002},	{156,	0x00190003},
+{1296,	0x001A0000},	{648, 	0x001A0001},	{324, 	0x001A0002},	{162,	0x001A0003},
+{1344,	0x001B0000},	{672, 	0x001B0001},	{336, 	0x001B0002},	{168,	0x001B0003},
+{1392,	0x001C0000},	{696, 	0x001C0001},	{348, 	0x001C0002},	{174,	0x001C0003},
+{1440,	0x001D0000},	{720, 	0x001D0001},	{360, 	0x001D0002},	{180,	0x001D0003},
+{1488,	0x001E0000},	{744, 	0x001E0001},	{372, 	0x001E0002},	{186,	0x001E0003},
+{1536,	0x001F0000},	{768, 	0x001F0001},	{384, 	0x001F0002},	{192,	0x001F0003},
+{1584,	0x00200000},	{792, 	0x00200001},	{396, 	0x00200002},	{198,	0x00200003},
+{1632,	0x00210000},	{816, 	0x00210001},	{408, 	0x00210002},	{204,	0x00210003},
+{1680,	0x00220000},	{840, 	0x00220001},	{420, 	0x00220002},	{210,	0x00220003},
+{1728,	0x00230000},	{864, 	0x00230001},	{432, 	0x00230002},	{216,	0x00230003},
+{1776,	0x00240000},	{888, 	0x00240001},	{444, 	0x00240002},	{222,	0x00240003},
+{1824,	0x00250000},	{912, 	0x00250001},	{456, 	0x00250002},	{228,	0x00250003},
+{1872,	0x00260000},	{936, 	0x00260001},	{468, 	0x00260002},	{234,	0x00260003},
+{1920,	0x00270000},	{960, 	0x00270001},	{480, 	0x00270002},	{240,	0x00270003},
+{1968,	0x00280000},	{984, 	0x00280001},	{492, 	0x00280002},	{246,	0x00280003},
+{2016,	0x00290000},	{1008, 	0x00290001},	{504, 	0x00290002},	{252,	0x00290003},
+
+{144,	0x00020000},	
+{192,	0x00030000},
+{240,	0x00040000},
+{288,	0x00050000},	{144, 	0x00050001},
+{336,	0x00060000},	{168, 	0x00060001},
+{384,	0x00070000},	{192, 	0x00070001},
+{432,	0x00080000},	{216, 	0x00080001},
+{480,	0x00090000},	{240, 	0x00090001},
+{528,	0x000A0000},	{264, 	0x000A0001},	{132, 	0x000A0002},
+{576,	0x000B0000},	{288, 	0x000B0001},	{144, 	0x000B0002},
+{624,	0x000C0000},	{312, 	0x000C0001},	{156, 	0x000C0002},
+{672,	0x000D0000},	{336, 	0x000D0001},	{168, 	0x000D0002},
+{720,	0x000E0000},	{360, 	0x000E0001},	{180, 	0x000E0002},
+{768,	0x000F0000},	{384, 	0x000F0001},	{192, 	0x000F0002},
+{816,	0x00100000},	{408, 	0x00100001},	{204, 	0x00100002},
+{864,	0x00110000},	{432, 	0x00110001},	{216, 	0x00110002},
+{912,	0x00120000},	{456, 	0x00120001},	{228, 	0x00120002},
+{960,	0x00130000},	{480, 	0x00130001},	{240, 	0x00130002},
+
+{144,	0x00050100},
+{168,	0x00060100},
+{192,	0x00070100},
+{216,	0x00080100},
+{240,	0x00090100},
+{264,	0x000A0100},	{132, 	0x000A0101},	
+{288,	0x000B0100},	{144, 	0x000B0101},	
+{312,	0x000C0100},	{156, 	0x000C0101},	
+{336,	0x000D0100},	{168, 	0x000D0101},	
+{360,	0x000E0100},	{180, 	0x000E0101},	
+{384,	0x000F0100},	{192, 	0x000F0101},	
+{408,	0x00100100},	{204, 	0x00100101},	
+{432,	0x00110100},	{216, 	0x00110101},	
+{456,	0x00120100},	{228, 	0x00120101},	
+{480,	0x00130100},	{240, 	0x00130101},	
+{504,	0x00140100},	{252, 	0x00140101},	{126, 	0x00140102},
+{528,	0x00150100},	{264, 	0x00150101},	{132, 	0x00150102},
+{552,	0x00160100},	{276, 	0x00160101},	{138, 	0x00160102},
+{576,	0x00170100},	{288, 	0x00170101},	{144, 	0x00170102},
+{600,	0x00180100},	{300, 	0x00180101},	{150, 	0x00180102},
+{624,	0x00190100},	{312, 	0x00190101},	{156, 	0x00190102},
+{648,	0x001A0100},	{324, 	0x001A0101},	{162, 	0x001A0102},
+{672,	0x001B0100},	{336, 	0x001B0101},	{168, 	0x001B0102},
+{696,	0x001C0100},	{348, 	0x001C0101},	{174, 	0x001C0102},
+{720,	0x001D0100},	{360, 	0x001D0101},	{180, 	0x001D0102},
+{744,	0x001E0100},	{372, 	0x001E0101},	{186, 	0x001E0102},
+{768,	0x001F0100},	{384, 	0x001F0101},	{192, 	0x001F0102},
+{792,	0x00200100},	{396, 	0x00200101},	{198, 	0x00200102},
+{816,	0x00210100},	{408, 	0x00210101},	{204, 	0x00210102},
+{840,	0x00220100},	{420, 	0x00220101},	{210, 	0x00220102},
+{864,	0x00230100},	{432, 	0x00230101},	{216, 	0x00230102},
+{888,	0x00240100},	{444, 	0x00240101},	{222, 	0x00240102},
+{912,	0x00250100},	{456, 	0x00250101},	{228, 	0x00250102},
+{936,	0x00260100},	{468, 	0x00260101},	{234, 	0x00260102},
+{960,	0x00270100},	{480, 	0x00270101},	{240, 	0x00270102},
+{984,	0x00280100},	{492, 	0x00280101},	{246, 	0x00280102}
+};
+
+#ifndef ARRAYSIZE
+#define ARRAYSIZE(a)           (sizeof(a) / sizeof(a[0]))
+#endif
+
+static void check_PLL_DIV_busy(void)
+{
+	while ((*(volatile unsigned int *)(PMC_BASE+0x18))&PLL_BUSY)
+		;
+}
+#ifdef debug_clk
+static void print_refer_count(void)
+{
+	int i;
+	for (i = 0; i < 4; i++) {
+		printf("clk cnt %d ~ %d: %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d\n",i*16,(i*16)+15,
+		dev_en_count[i*16],dev_en_count[i*16+1],dev_en_count[i*16+2],dev_en_count[i*16+3],dev_en_count[i*16+4],dev_en_count[i*16+5],dev_en_count[i*16+6],dev_en_count[i*16+7],
+		dev_en_count[i*16+8],dev_en_count[i*16+9],dev_en_count[i*16+10],dev_en_count[i*16+11],dev_en_count[i*16+12],dev_en_count[i*16+13],dev_en_count[i*16+14],dev_en_count[i*16+15]);
+	}
+}
+#endif
+static int disable_dev_clk(enum dev_id dev)
+{
+	int en_count;
+
+	if (dev >= 128) {
+		printf("device dev_id > 128\n");
+		return -1;
+	}
+
+	#ifdef debug_clk
+	print_refer_count();
+	#endif
+
+	en_count = dev_en_count[dev];
+	if (en_count <= 1) {
+		dev_en_count[dev] = en_count = 0;
+		*(volatile unsigned int *)(PMC_CLK + 4*(dev/32))
+		&= ~(1 << (dev - 32*(dev/32)));
+	} else if (en_count > 1) {
+		dev_en_count[dev] = (--en_count);
+	}
+
+	#ifdef debug_clk
+	print_refer_count();
+	#endif
+
+	return en_count;
+}
+
+static int enable_dev_clk(enum dev_id dev)
+{
+	int en_count, tmp;
+
+	if (dev > 128) {
+		printf("device dev_id > 128\n");
+		return -1;
+	}
+
+	#ifdef debug_clk
+	printf("device dev_id = %d\n",dev);
+	print_refer_count();
+	#endif
+
+	en_count = dev_en_count[dev];
+	tmp = *(volatile unsigned int *)(PMC_CLK + 4*(dev/32));
+	if (en_count <= 0 || !(tmp&(1 << (dev - 32*(dev/32))))) {
+		dev_en_count[dev] = en_count = 1;
+		*(volatile unsigned int *)(PMC_CLK + 4*(dev/32))
+		|= 1 << (dev - 32*(dev/32));
+	} else
+		dev_en_count[dev] = (++en_count);
+
+	#ifdef debug_clk
+	print_refer_count();
+	#endif
+
+	return en_count;
+}
+/*
+* PLLA return 0, PLLB return 1,
+* PLLC return 2, PLLD return 3,
+* PLLE return 4, PLLF return 5,
+* PLLG return 6,
+* device not found return -1.
+* device has no divisor but has clock enable return -2.
+*/
+static int calc_pll_num(enum dev_id dev, int *div_offset)
+{
+	switch (dev) {
+		case DEV_UART0:
+		case DEV_UART1:
+		case DEV_UART2:
+		case DEV_UART3:		/*case DEV_UART4:		case DEV_UART5:*/
+		case DEV_AHBB:
+		case DEV_CIR:
+		case DEV_SYS:		/* no use */
+		case DEV_RTC:
+		case DEV_UHDC:
+		case DEV_PERM:	/* no use */
+		case DEV_PDMA:	/* no use */
+		case DEV_VID:
+		*div_offset = 0;
+		return -2;
+		case DEV_SAE:
+		*div_offset = 0x348;
+		return 1;
+		case DEV_C24MOUT:
+		*div_offset = 0x3E4;
+		return 1;
+		case DEV_I2C0:
+		*div_offset = 0x3A0;
+		return 1;
+		case DEV_I2C1:
+		*div_offset = 0x3A4;
+		return 1;
+		case DEV_I2C2:
+		*div_offset = 0x3A8;
+		return 1;
+		case DEV_I2C3:
+		*div_offset = 0x3AC;
+		return 1;
+		case DEV_I2C4:
+		*div_offset = 0x39C;
+		return 1;
+		case DEV_PWM:
+		*div_offset = 0x350;
+		return 1;
+		case DEV_SPI0:
+		*div_offset = 0x340;
+		return 1;
+		case DEV_SPI1:
+		*div_offset = 0x344;
+		return 1;
+		case DEV_HDMILVDS:
+		case DEV_SDTV:
+		case DEV_HDMI:
+		*div_offset = 0x36C;
+		return 2;
+		case DEV_DVO:
+		case DEV_LVDS:
+		*div_offset = 0x370;
+		return 6;
+		case DEV_CSI0:
+		*div_offset = 0x380;
+		return 1;
+		case DEV_CSI1:
+		*div_offset = 0x384;
+		return 1;
+		case DEV_MALI:
+		*div_offset = 0x388;
+		return 1;
+		case DEV_DDRMC:
+		*div_offset = 0x310;
+		return 3;
+		case DEV_WMTNA:
+		*div_offset = 0x358;
+		return 3;
+		case DEV_CNMNA:
+		*div_offset = 0x360;
+		return 3;
+		case DEV_WMTVDU:
+		case DEV_JENC:
+		case DEV_HDCE:
+		case DEV_H264:
+		case DEV_JDEC:
+		case DEV_MSVD:
+		case DEV_AMP:
+		case DEV_VPU:
+		case DEV_MBOX:
+		*div_offset = 0x368;
+		return 3;
+		case DEV_CNMVDU:
+		case DEV_VP8DEC:
+		*div_offset = 0x38C;
+		return 3;
+		case DEV_NA12:
+		case DEV_VPP:
+		case DEV_GE:
+		case DEV_DISP:
+		case DEV_GOVRHD:
+		case DEV_SCL444U:
+		case DEV_GOVW:
+		*div_offset = 0x35C;
+		return 1;
+		case DEV_PAXI:
+		case DEV_DMA:
+		*div_offset = 0x354;
+		return 1;
+		case DEV_L2C:
+		*div_offset = 0x30C;
+		return 0;
+		case DEV_L2CAXI:
+		*div_offset = 0x3B0;
+		return 0;
+		case DEV_AT:
+		*div_offset = 0x3B4;
+		return 0;
+		case DEV_PERI:
+		*div_offset = 0x3B8;
+		return 0;
+		case DEV_TRACE:
+		*div_offset = 0x3BC;
+		return 0;
+		case DEV_L2CPAXI:
+		*div_offset = 0x3C0;
+		return 0;
+		case DEV_DBG:
+		*div_offset = 0x3D0;
+		return 0;
+		case DEV_NAND:
+		*div_offset = 0x318;
+		return 1;
+		/*case DEV_NOR:
+		*div_offset = 0x31C;
+		return 1;*/
+		case DEV_SDMMC0:
+		*div_offset = 0x330;
+		return 1;
+		case DEV_SDMMC1:
+		*div_offset = 0x334;
+		return 1;
+		case DEV_SDMMC2:
+		*div_offset = 0x338;
+		return 1;
+		/*case DEV_SDMMC3:
+		*div_offset = 0x33C;
+		return 1;*/
+		case DEV_ADC:
+		*div_offset = 0x394;
+		return 1;
+		case DEV_HDMII2C: /* div 1~63 */
+		*div_offset = 0x390;
+		return 4;
+		case DEV_SF:
+		*div_offset = 0x314;
+		return 1;
+		case DEV_PCM0:
+		*div_offset = 0x324;
+		return 1;
+		case DEV_PCM1:
+		*div_offset = 0x328;
+		return 1;
+		case DEV_I2S:
+		case DEV_ARF:
+		case DEV_ARFP:
+		*div_offset = 0x374;
+		return 4;
+		case DEV_ARM:
+		*div_offset = 0x300;
+			return 0;
+		case DEV_AHB:
+		*div_offset = 0x304;
+			return 1;
+		case DEV_APB:
+		case DEV_SCC:
+		case DEV_GPIO:
+		*div_offset = 0x320;
+			return 1;
+		/*case DEV_ETHPHY:
+		*div_offset = 25;
+			return -2;*/
+		default:
+		return -1;
+	}
+}
+
+
+/* if the clk of the dev is not enable, then enable it or fail */
+int check_clk_enabled(enum dev_id dev, enum clk_cmd cmd) {
+	unsigned int pmc_clk_en;
+	if (dev < 128) {
+		pmc_clk_en = *(volatile unsigned int *)(PMC_CLK + 4*(dev/32));
+		if (!(pmc_clk_en & (1 << (dev - 32*(dev/32))))) {
+			/*enable_dev_clk(dev);*/
+			printf("dev[%d] clock disabled\n", dev);
+			return -1;
+		}
+	}
+	return 0;
+}
+/*
+* get only PLL frequency not including divisor of each device
+* PLL_NO : PLL number(0~6) means PLLA ~ PLLG
+* return : return the frequence in MHz.
+*/
+int get_pll_freq(int PLL_NO)
+{
+	int freq;
+	unsigned int tmp;
+
+	if (PLL_NO < 0 || PLL_NO > 6) {
+		printf("PLL NO(%d) is out of range\n", PLL_NO);
+		return -1;
+	}
+
+	tmp = *(volatile unsigned int *)(PMC_PLL + 4*PLL_NO);
+	freq = ((SRC_FREQ)*GET_DIVF(tmp)) / (GET_DIVR(tmp)*GET_DIVQ(tmp));
+
+	return freq;
+}
+
+static int get_freq(enum dev_id dev, int *divisor) {
+
+	unsigned int tmp, freq, div = 0, base = 1000000;
+	int PLL_NO, j = 0, div_addr_offs;
+
+	PLL_NO = calc_pll_num(dev, &div_addr_offs);
+	if (PLL_NO == -1) {
+		printf("device not found");
+		return -1;
+	}
+
+	if (PLL_NO == -2)
+		return div_addr_offs*1000000;
+
+	*(volatile unsigned char *)(PMC_BASE + div_addr_offs + 2) = (dev == DEV_SDTV) ? 1 : 0;
+
+	check_PLL_DIV_busy();
+
+	div = *divisor = *(volatile unsigned char *)(PMC_BASE + div_addr_offs);
+	//printf("div_addr_offs=0x%x PLL_NO=%d \n", div_addr_offs, PLL_NO);
+	tmp = *(volatile unsigned int *)(PMC_PLL + 4*PLL_NO);
+	
+	if ((dev != DEV_SDMMC0) && (dev != DEV_SDMMC1) && (dev != DEV_SDMMC2)) {
+		div = div&0x1F;
+	} else {
+		if (div & (1<<5))
+			j = 1;
+		div &= 0x1F;
+		div = div*(j?64:1)*2;
+	}
+
+	freq = (SRC_FREQ*GET_DIVF(tmp))*(base/(GET_DIVR(tmp)*GET_DIVQ(tmp)*div));
+
+	return freq;
+}
+static int get_freq_t(enum dev_id dev, int *divisor) {
+
+	unsigned int div = 0, freq = 0, base = 1000000, tmp;
+	int PLL_NO, i, j = 0, div_addr_offs;
+	#ifdef DEBUG_CLK
+	unsigned int t1 = 0, t2 = 0;
+	#endif
+
+	PLL_NO = calc_pll_num(dev, &div_addr_offs);
+	if (PLL_NO == -1) {
+		printf("device not found");
+		return -1;
+	}
+
+	if (PLL_NO == -2)
+		return div_addr_offs*1000000;
+
+	*(volatile unsigned char *)(PMC_BASE + div_addr_offs + 2) = (dev == DEV_SDTV) ? 1 : 0;
+
+	check_PLL_DIV_busy();
+
+	div = *divisor = *(volatile unsigned char *)(PMC_BASE + div_addr_offs);
+
+	if ((dev != DEV_SDMMC0) && (dev != DEV_SDMMC1) && (dev != DEV_SDMMC2)) {
+		div = div&0x1F;
+	} else {
+		if (div & (1<<5))
+			j = 1;
+		div &= 0x1F;
+		div = div*(j?64:1)*2;
+	}
+
+	#ifdef DEBUG_CLK
+	printf("div_addr_offs=0x%x PLL_NO=%d PMC_PLL=0x%x\n", div_addr_offs, PLL_NO, PMC_PLL);
+	t1 = wmt_read_oscr();
+	#endif
+	tmp = *(volatile unsigned int *)(PMC_PLL + 4*PLL_NO);
+	for (i = 0; i < ARRAYSIZE(pllmapAll); i++) {
+		if (pllmapAll[i].pll == tmp) {
+			freq = pllmapAll[i].freq;
+			#ifdef DEBUG_CLK
+			printf("********dev%d---PLL_NO=%X---get freq=%d set0x%x\n",	dev, PLL_NO+10, freq, pllmapAll[i].pll);
+			#endif
+			break;
+		}
+	}
+	if (i >= ARRAYSIZE(pllmapAll) || freq == 0) {
+		printf("gfreq : dev%d********************pll not match table**************\n", dev);
+		/*freq = (SRC_FREQ*GET_DIVF(tmp))*(base/(GET_DIVR(tmp)*GET_DIVQ(tmp)*div));*/
+		freq = ((SRC_FREQ/GET_DIVQ(tmp)) * (GET_DIVF(tmp)/GET_DIVR(tmp)) * base) / div;
+	} else {
+		freq = (freq * 15625)<<6;
+		freq = freq/div;
+	}
+
+	#ifdef DEBUG_CLK
+	t2 = wmt_read_oscr() - t1;
+	printf("************delay_time=%d\n", t2);
+	printf("get_freq cmd: freq=%d \n", freq);
+	#endif
+
+	return freq;
+}
+
+static int set_divisor(enum dev_id dev, int unit, int freq, int *divisor) {
+
+	unsigned int tmp, PLL, div = 0;
+	int PLL_NO, i, j = 0, div_addr_offs, SD_MMC = 1, ret;
+
+	if ((dev != DEV_SDMMC0) && (dev != DEV_SDMMC1) && (dev != DEV_SDMMC2))
+		SD_MMC = 0;
+	PLL_NO = calc_pll_num(dev, &div_addr_offs);
+	if (PLL_NO == -1) {
+		printf("device not found");
+		return -1;
+	}
+
+	if (PLL_NO == -2) {
+		printf("device has no divisor");
+		return -1;
+	}
+
+	*(volatile unsigned char *)(PMC_BASE + div_addr_offs + 2) = (dev == DEV_SDTV) ? 1 : 0;
+
+	check_PLL_DIV_busy();
+
+	tmp = *(volatile unsigned int *)(PMC_PLL + 4*PLL_NO);
+	PLL = (SRC_FREQ*GET_DIVF(tmp))/(GET_DIVR(tmp)*GET_DIVQ(tmp));
+
+	ret = check_clk_enabled(dev, SET_DIV);
+	if (ret)
+		return -1;
+
+	PLL *= 1000000;
+	if (unit == 1)
+		freq *= 1000;
+	else if (unit == 2)
+		freq *= 1000000;
+
+	if (SD_MMC == 0) {
+		for (i = 1; i < 33; i++) {
+			if ((i > 1 && (i%2)) && (PLL_NO == 2))
+				continue;
+			if ((PLL/i) <= ((unsigned int)freq)) {
+				*divisor = div = i;
+				break;
+			}
+		}
+	} else {
+		if ((PLL/64) >= ((unsigned int)freq))
+				j = 1;
+		for (i = 1; i < 33; i++)
+			if ((PLL/(i*(j?64:1)*2)) <= ((unsigned int)freq)) {
+				*divisor = div = i;
+				break;
+			}
+	}
+	if (div != 0 && div < 33) {
+		check_PLL_DIV_busy();
+		if (dev == DEV_WMTNA)
+			*(volatile unsigned int *)(PMC_BASE + div_addr_offs) =	(0x200 | ((div == 32) ? 0 : div));
+		else
+			*(volatile unsigned int *)(PMC_BASE + div_addr_offs)
+			=	((dev == DEV_SDTV)?0x10000:0) + (j?32:0) + ((div == 32) ? 0 : div);
+		check_PLL_DIV_busy();
+		if (SD_MMC == 1)
+			return (PLL/(div*(j?64:1)*2));
+		else
+			return (PLL/(div*(j?64:1)));
+	}
+	printf("no suitable divisor");
+	return -1;
+}
+static int set_divisor_t(enum dev_id dev, int unit, int freq, int *divisor) {
+
+	unsigned int div = 0, tmp;
+	int ret, PLL_NO, i, j = 1, div_addr_offs, SD_MMC = 1;
+	unsigned int PLL = 0, freq_target = freq;
+	if ((dev != DEV_SDMMC0) && (dev != DEV_SDMMC1) && (dev != DEV_SDMMC2))
+		SD_MMC = 0;
+
+	PLL_NO = calc_pll_num(dev, &div_addr_offs);
+	if (PLL_NO == -1) {
+		printf("device not found");
+		return -1;
+	} else if (PLL_NO == -2) {
+		printf("device has no divisor");
+		return -1;
+	}
+
+	*(volatile unsigned char *)(PMC_BASE + div_addr_offs + 2) = (dev == DEV_SDTV) ? 1 : 0;
+
+	check_PLL_DIV_busy();
+	tmp = *(volatile unsigned int *)(PMC_PLL + 4*PLL_NO);
+
+	ret = check_clk_enabled(dev, SET_DIV);
+	if (ret)
+		return -1;
+
+	if (unit == 1)
+		freq_target *= 1000;
+	else if (unit == 2)
+		freq_target *= 1000000;
+
+	for (i = 0; i < ARRAYSIZE(pllmapAll); i++) {
+		if (pllmapAll[i].pll == tmp) {
+			PLL = pllmapAll[i].freq;
+			break;
+		}
+	}
+	if (i >= ARRAYSIZE(pllmapAll) || PLL == 0) {
+		printf("set div : dev%d********************pll not match table**************\n", dev);
+		PLL = (SRC_FREQ/GET_DIVQ(tmp)) * (GET_DIVF(tmp)/GET_DIVR(tmp));
+	}
+	PLL = (PLL * 15625)<<6;
+
+	if (SD_MMC == 0) {
+		for (i = 1; i < 64; i++) {
+			if ((i > 1 && (i%2)) && (PLL_NO == 2))
+				continue;
+				freq = PLL/i;
+			if (freq <= freq_target) {
+				*divisor = div = i;
+				break;
+			}
+		}
+	} else {
+		if ((PLL>>6) >= freq_target)
+			j = 1<<6;
+		for (i = 1; i < 64; i++) {
+			freq = PLL/(i*j);
+			if (freq <= freq_target) {
+				*divisor = div = i;
+				break;
+			}
+		}
+	}
+	if (div > 32)
+		div = 32;
+	if (div != 0 && div < 33) {
+		check_PLL_DIV_busy();
+		if (dev == DEV_WMTNA)
+			*(volatile unsigned int *)(PMC_BASE + div_addr_offs) =	(0x200 | ((div == 32) ? 0 : div));
+		else
+			*(volatile unsigned int *)(PMC_BASE + div_addr_offs)
+			=	((dev == DEV_SDTV)?0x10000:0) + (j==64?32:0) + ((div == 32) ? 0 : div);
+		#ifdef DEBUG_CLK
+		printf("SETDIV********dev%d PLL_%X PLL=0x%x div%d cal_freq=%d target_freq%d\n",
+		dev, PLL_NO+10, PLL, div, freq, freq_target);
+		#endif
+		check_PLL_DIV_busy();
+		return freq;
+	}
+	printf("no suitable divisor dev0x%x div=%d treq%d\n", dev, div, freq_target);
+	return -1;
+}
+
+static int set_pll_speed(enum dev_id dev, int unit, int freq, int *divisor) {
+
+	unsigned int PLL, DIVF=1, DIVR=1, DIVQ=1;
+	unsigned int last_freq, div=1, base, base_f=1/*, filt_range, filter*/;
+	unsigned long minor, min_minor = 0xFF000000;
+	int PLL_NO, div_addr_offs, DF, DR, VD, DQ;
+
+	PLL_NO = calc_pll_num(dev, &div_addr_offs);
+	if (PLL_NO == -1) {
+		printf("device not belong to PLL A B C D E F G");
+		return -1;
+	}
+
+	if (PLL_NO == -2) {
+		printf("device not found");
+		return -1;
+	}
+
+	*(volatile unsigned char *)(PMC_BASE + div_addr_offs + 2) = (dev == DEV_SDTV) ? 1 : 0;
+
+	check_PLL_DIV_busy();
+	VD = *divisor = *(volatile unsigned char *)(PMC_BASE + div_addr_offs);
+	base = 1000000;
+	if (unit == 1)
+		base_f = 1000;
+	else if (unit == 2)
+		base_f = 1000000;
+	else if (unit != 0) {
+		printf("unit is out of range");
+		return -1;
+	}
+
+	for (DR = MAX_DR; DR >= 0; DR--) {
+		for (DQ = MAX_DQ; DQ >= 0; DQ--) {
+			for (DF = 0; DF <= MAX_DF; DF++) {
+				if (SRC_FREQ/(DR+1) < 10)
+					break;
+				if ((1000/SRC_FREQ) > ((2*(DF+1))/(DR+1)))
+					continue;
+				if ((2000/SRC_FREQ) < ((2*(DF+1))/(DR+1)))
+					break;
+				if (((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ)))) == (freq * base_f)) {
+					DIVF = DF;
+					DIVR = DR;
+					DIVQ = DQ;
+					div = VD;
+					/*printf("find the equal value\n");*/
+					goto find;
+				} else if (((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ)))) < (freq * base_f)) {
+					minor = (freq * base_f) - ((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ))));
+					//printf("minor=0x%x, min_minor=0x%x", minor, min_minor);
+					if (minor < min_minor) {
+						DIVF = DF;
+						DIVR = DR;
+						DIVQ = DQ;
+						div = VD;
+						min_minor = minor;
+					}
+				} else if (((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ)))) > (freq * base_f)) {
+					if (PLL_NO == 2) {
+						minor = ((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ)))) - (freq * base_f);
+						if (minor < min_minor) {
+							DIVF = DF;
+							DIVR = DR;
+							DIVQ = DQ;
+							div = VD;
+							min_minor = minor;
+						}
+					}
+					break;
+				}
+			}//DF
+		}//DQ
+	}//DR
+/*minimun:*/
+find:
+
+	/*filter = SRC_FREQ/(DIVR+1);
+	filt_range = check_filter(filter);*/
+	last_freq = (SRC_FREQ * 2 * (DIVF+1)) * (base / ((DIVR+1)*(1<<DIVQ)*(*divisor)));
+	/*printf("DIVF%d, DIVR%d, DIVQ%d, divisor%d freq=%dHz \n",
+	DIVF, DIVR, DIVQ, *divisor, last_freq);*/
+	PLL = (DIVF<<16) + (DIVR<<8) + DIVQ/* + (filt_range<<24)*/;
+
+	/* if the clk of the device is not enable, then enable it */
+	/*if (dev < 128) {
+		pmc_clk_en = *(volatile unsigned int *)(PMC_CLK + 4*(dev/32));
+		if (!(pmc_clk_en & (1 << (dev - 32*(dev/32)))))
+			enable_dev_clk(dev);
+	}*/
+
+	check_PLL_DIV_busy();
+	/*printf("PLL0x%x, pll addr =0x%x\n", PLL, PMC_PLL + 4*PLL_NO);*/
+	*(volatile unsigned int *)(PMC_PLL + 4*PLL_NO) = PLL;
+	check_PLL_DIV_busy();
+	return last_freq;
+
+	printf("no suitable pll");
+	return -1;
+}
+
+static int set_pll_speed_t(enum dev_id dev, int unit, int freq, int *divisor, int wait) {
+
+	unsigned int PLL, VD;
+	unsigned int minor, min_minor = 0x7F000000, set_freq = 0;
+	int PLL_NO, div_addr_offs, i;
+	unsigned int tmp_freq, tmp_PLL = 0;
+	PLL_NO = calc_pll_num(dev, &div_addr_offs);
+	if (PLL_NO == -1) {
+		printf("device not belong to PLL A B C D E");
+		return -1;
+	}
+
+	if (PLL_NO == -2) {
+		printf("device has no divisor");
+		return -1;
+	}
+
+	*(volatile unsigned char *)(PMC_BASE + div_addr_offs + 2) = (dev == DEV_SDTV) ? 1 : 0;
+
+	check_PLL_DIV_busy();
+	VD = *divisor = *(volatile unsigned char *)(PMC_BASE + div_addr_offs);
+
+	if (unit == 1)
+		freq *= 1000;
+	else if (unit == 2)
+		freq *= 1000000;
+	else if (unit != 0) {
+		printf("unit is out of range");
+		return -1;
+	}
+	
+	for (i = 0; i < ARRAYSIZE(pllmap); i++) {
+		if (pllmap[i].freq > 1150 && PLL_NO == 4)
+			continue;
+		if (pllmap[i].freq > 1250 && ((PLL_NO == 2) || (PLL_NO == 6)))
+			continue;
+		tmp_freq = ((pllmap[i].freq*15625)<<6) / VD;
+		if (tmp_freq == freq) {
+			tmp_PLL = pllmap[i].pll;
+			set_freq = tmp_freq;
+			min_minor = 0;
+			goto find;
+		} else if (tmp_freq < freq) {
+			minor = freq - tmp_freq;
+			if (minor < min_minor) {
+				tmp_PLL = pllmap[i].pll;
+				set_freq = tmp_freq;
+				min_minor = minor;
+			}
+		} else if (tmp_freq > freq) {
+			if (PLL_NO == 2) {
+				minor = tmp_freq - freq;
+				if (minor < min_minor) {
+					tmp_PLL = pllmap[i].pll;
+					set_freq = tmp_freq;
+					min_minor = minor;
+				}
+			}
+			break;
+		}
+	}
+find:
+	#ifdef DEBUG_CLK
+	if (min_minor)
+		printf("minimum minor=0x%x, unit=%d \n", (unsigned int)min_minor, unit);
+	printf("SETPLL********dev%d PLL_%X PLL=0x%x cal_freq=%d target_freq%d\n",
+	dev, PLL_NO+10, tmp_PLL, set_freq, freq);
+	#endif
+	PLL = tmp_PLL;
+	
+	check_PLL_DIV_busy();
+	*(volatile unsigned int *)(PMC_PLL + 4*PLL_NO) = PLL;
+	if (wait)
+		check_PLL_DIV_busy();
+	return set_freq;
+}
+
+static int set_pll_divisor(enum dev_id dev, int unit, int freq, int *divisor) {
+
+	unsigned int PLL, DIVF=1, DIVR=1, DIVQ=1, pmc_clk_en, old_divisor;
+	unsigned int last_freq, div=1, base, base_f=1/*, filt_range, filter*/;
+	unsigned long minor, min_minor = 0xFF000000;
+	int PLL_NO, div_addr_offs, DF, DR, VD, DQ;
+
+	PLL_NO = calc_pll_num(dev, &div_addr_offs);
+	if (PLL_NO == -1) {
+		printf("device not belong to PLL A B C D E");
+		return -1;
+	}
+
+	if (PLL_NO == -2) {
+		printf("device has no divisor");
+		return -1;
+	}
+
+	*(volatile unsigned char *)(PMC_BASE + div_addr_offs + 2) = (dev == DEV_SDTV) ? 1 : 0;
+
+	check_PLL_DIV_busy();
+
+	old_divisor = *(volatile unsigned char *)(PMC_BASE + div_addr_offs);
+
+	base = 1000000;
+	if (unit == 1)
+		base_f = 1000;
+	else if (unit == 2)
+		base_f = 1000000;
+	else if (unit != 0) {
+		printf("unit is out of range");
+		return -1;
+	}
+
+	//tmp = div * freq;
+	for (DR = MAX_DR; DR >= 0; DR--) {
+		for (DQ = MAX_DQ; DQ >= 0; DQ--) {
+			for (VD = 32; VD >= 1; VD--) {
+				if ((VD > 1 && (VD%2)) && (PLL_NO == 2))
+					continue;
+				for (DF = 0; DF <= MAX_DF; DF++) {
+					if (SRC_FREQ/(DR+1) < 10)
+						break;
+					if ((1000/SRC_FREQ) > ((2*(DF+1))/(DR+1)))
+						continue;
+					if ((2000/SRC_FREQ) < ((2*(DF+1))/(DR+1)))
+						break;
+					if (((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ)))) == (freq * base_f)) {
+						DIVF = DF;
+						DIVR = DR;
+						DIVQ = DQ;
+						div = VD;
+						/*printf("find the equal value\n");*/
+						goto find;
+					} else if (((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ)))) < (freq * base_f)) {
+						minor = (freq * base_f) - ((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ))));
+						/*if (unit == 2)
+							minor = ((SRC_FREQ * DF) - (VD * (DR*(1<<DQ)))) * base;
+						else if (unit == 1)
+							minor = (1000 * SRC_FREQ * DF) - (freq * VD * (DR*(1<<DQ)));
+						else 
+							minor = (1000 * SRC_FREQ * DF) - ((freq * VD * (DR*(1<<DQ)))/1000);*/
+						//printf("minor=0x%x, min_minor=0x%x", minor, min_minor);
+						if (minor < min_minor) {
+							DIVF = DF;
+							DIVR = DR;
+							DIVQ = DQ;
+							div = VD;
+							min_minor = minor;
+								/*if (min_minor < 1000000 && unit == 2)
+									goto minimun;
+								else if (min_minor < 1000 && unit == 1)
+								 goto minimun;
+								else if (min_minor < 20 && unit == 0)
+								 goto minimun;*/
+						}
+					} else if (((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ)))) > (freq * base_f)) {
+						if (PLL_NO == 2) {
+							minor = ((SRC_FREQ * 2 * (DF+1)) * (base/(VD * (DR+1)*(1<<DQ)))) - (freq * base_f);
+							if (minor < min_minor) {
+								DIVF = DF;
+								DIVR = DR;
+								DIVQ = DQ;
+								div = VD;
+								min_minor = minor;
+							}
+						}
+						break;
+					}
+				}//DF
+			}//VD
+		}//DQ
+	}//DR
+/*minimun:*/
+	//printf("minimum minor=0x%x, unit=%d \n", (unsigned int)min_minor, unit);
+find:
+
+	/*filter = SRC_FREQ/(DIVR+1);
+	filt_range = check_filter(filter);*/
+	*divisor = div;
+	last_freq = (SRC_FREQ * 2 * (DIVF+1)) * (base / ((DIVR+1)*(1<<DIVQ)*(*divisor)));
+	/*printf("DIVF%d, DIVR%d, DIVQ%d, divisor%d freq=%dHz \n",
+	DIVF, DIVR, DIVQ, *divisor, last_freq);*/
+	PLL = (DIVF<<16) + (DIVR<<8) + DIVQ/* + (filt_range<<24)*/;
+
+
+	/* if the clk of the device is not enable, then enable it */
+	if (dev < 128) {
+		pmc_clk_en = *(volatile unsigned int *)(PMC_CLK + 4*(dev/32));
+		if (!(pmc_clk_en & (1 << (dev - 32*(dev/32))))) {
+			/*enable_dev_clk(dev);*/
+			printf("device clock is disabled");
+			return -1;
+		}
+	}
+
+	check_PLL_DIV_busy();
+	if (old_divisor < *divisor) {
+		*(volatile unsigned int *)(PMC_BASE + div_addr_offs)
+		= ((dev == DEV_SDTV)?0x10000:0) +/*(j?32:0) + */((div == 32) ? 0 : div)/* + (div&1) ? (1<<8): 0*/;
+		check_PLL_DIV_busy();
+	}
+	//printf("PLL0x%x, pll addr =0x%x\n", PLL, PMC_PLL + 4*PLL_NO);
+	*(volatile unsigned int *)(PMC_PLL + 4*PLL_NO) = PLL;
+	check_PLL_DIV_busy();
+	/*printf("DIVF%d, DIVR%d, DIVQ%d, div%d div_addr_offs=0x%x\n",
+	DIVF, DIVR, DIVQ, div, div_addr_offs);*/
+
+	if (old_divisor > *divisor) {
+		*(volatile unsigned int *)(PMC_BASE + div_addr_offs)
+		= ((dev == DEV_SDTV)?0x10000:0) +/*(j?32:0) + */((div == 32) ? 0 : div)/* + (div&1) ? (1<<8): 0*/;
+		check_PLL_DIV_busy();
+	}
+
+	return last_freq;
+
+	printf("no suitable divisor");
+	return -1;
+}
+
+
+static int set_pll_divisor_t(enum dev_id dev, int unit, int freq, int *divisor) {
+
+	unsigned int PLL, old_divisor, div=1, set_freq = 0;
+	unsigned int minor, min_minor = 0x7F000000, tmp_freq = 0, tmp_PLL = 0, tfreq = (unsigned int)freq;
+	int i, PLL_NO, div_addr_offs, VD, ret;
+
+	PLL_NO = calc_pll_num(dev, &div_addr_offs);
+	if (PLL_NO == -1) {
+		printf("device not belong to PLL A B C D E");
+		return -1;
+	} else if (PLL_NO == -2) {
+		printf("device has no divisor");
+		return -1;
+	}
+
+	*(volatile unsigned char *)(PMC_BASE + div_addr_offs + 2) = (dev == DEV_SDTV) ? 1 : 0;
+
+	check_PLL_DIV_busy();
+	old_divisor = *(volatile unsigned char *)(PMC_BASE + div_addr_offs);
+
+	if (unit == 1)
+		tfreq *= 1000;
+	else if (unit == 2)
+		tfreq *= 1000000;
+	else if (unit != 0) {
+		printf("unit is out of range");
+		return -1;
+	}
+
+	for (i = 0; i < ARRAYSIZE(pllmap); i++) {
+		if (pllmap[i].freq > 1150 && PLL_NO == 4)
+			continue;
+		if (pllmap[i].freq > 1250 && ((PLL_NO == 2) || (PLL_NO == 6)))
+			continue;
+		for (VD = 32; VD >= 1; VD--) {
+			if ((VD > 1 && (VD == 3)) && ((PLL_NO == 2) || (PLL_NO == 6)))
+				continue;
+			tmp_freq = ((pllmap[i].freq*15625)<<6) / VD;
+			if (tmp_freq == tfreq) {
+				tmp_PLL = pllmap[i].pll;
+				set_freq = tmp_freq;
+				div = VD;
+				min_minor = 0;
+				goto find;
+			} else if (tmp_freq < tfreq) {
+				minor = tfreq - tmp_freq;
+				if (minor < min_minor) {
+					tmp_PLL = pllmap[i].pll;
+					set_freq = tmp_freq;
+					div = VD;
+					min_minor = minor;
+				}
+			} else if (tmp_freq > tfreq) {
+				if ((PLL_NO == 2) || (PLL_NO == 6)) {
+					minor = tmp_freq - tfreq;
+					if (minor < min_minor) {
+						tmp_PLL = pllmap[i].pll;
+						set_freq = tmp_freq;
+						div = VD;
+						min_minor = minor;
+					}
+				}
+				break;
+			}
+		}
+	}
+find:
+	#ifdef DEBUG_CLK
+	if (min_minor)
+		printf("minimum minor=0x%x, unit=%d \n", (unsigned int)min_minor, unit);
+	printf("SETPLLDIV********dev%d PLL_%X PLL=0x%x div%d cal_freq=%d target_freq%d\n",
+	dev, PLL_NO+10, tmp_PLL, div, set_freq, tfreq);
+	#endif
+
+	*divisor = div;
+	PLL = tmp_PLL;
+
+	ret = check_clk_enabled(dev, SET_PLLDIV);
+	if (ret)
+		return -1;
+
+	check_PLL_DIV_busy();
+	if (old_divisor < *divisor) {
+		if (dev == DEV_WMTNA)
+			*(volatile unsigned int *)(PMC_BASE + div_addr_offs) =	(0x200 | ((div == 32) ? 0 : div));
+		else
+			*(volatile unsigned int *)(PMC_BASE + div_addr_offs)
+			= ((dev == DEV_SDTV)?0x10000:0) +/*(j?32:0) + */((div == 32) ? 0 : div)/* + (div&1) ? (1<<8): 0*/;
+		check_PLL_DIV_busy();
+	}
+	*(volatile unsigned int *)(PMC_PLL + 4*PLL_NO) = PLL;
+	check_PLL_DIV_busy();
+
+	if (old_divisor > *divisor) {
+		if (dev == DEV_WMTNA)
+			*(volatile unsigned int *)(PMC_BASE + div_addr_offs) =	(0x200 | ((div == 32) ? 0 : div));
+		else
+			*(volatile unsigned int *)(PMC_BASE + div_addr_offs)
+			= ((dev == DEV_SDTV)?0x10000:0) +/*(j?32:0) + */((div == 32) ? 0 : div)/* + (div&1) ? (1<<8): 0*/;
+		check_PLL_DIV_busy();
+	}
+
+	return set_freq;
+}
+
+
+/*
+* cmd : CLK_DISABLE  : disable clock,
+*       CLK_ENABLE   : enable clock,
+*       GET_FREQ     : get device frequency, it doesn't enable or disable clock,
+*       SET_DIV      : set clock by setting divisor only(clock must be enabled by CLK_ENABLE command),
+*       SET_PLL      : set clock by setting PLL only, no matter clock is enabled or not,
+*                      this cmd can be used before CLK_ENABLE cmd to avoid a extreme speed
+*                      to be enabled when clock enable.
+*       SET_PLLDIV   : set clock by setting PLL and divisor(clock must be enabled by CLK_ENABLE command).
+* dev : Target device ID to be set the clock.
+* unit : the unit of parameter "freq", 0 = Hz, 1 = KHz, 2 = MHz.
+* freq : frequency of the target to be set when cmd is "SET_XXX".
+*
+* return : return value is different depend on cmd type,
+*				CLK_DISABLE  : return internal count which means how many drivers still enable this clock,
+*				               retrun -1 if this device has no clock enable register.
+*				               
+*				CLK_ENABLE   : return internal count which means how many drivers enable this clock,
+*				               retrun -1 if this device has no clock enable register.
+*
+*				GET_FREQ     : return device frequency in Hz when clock is enabled,
+*				               return -1 when clock is disabled.
+*
+*       SET_DIV      : return the finally calculated frequency when clock is enabled,
+*				               return -1 when clock is disabled.
+*
+*       SET_PLL      : return the finally calculated frequency no matter clock is enabled or not.
+*
+*       SET_PLLDIV   : return the finally calculated frequency when clock is enabled,
+*				               return -1 when clock is disabled.
+* Caution :
+* 1. The final clock freq maybe an approximative value,
+*    equal to or less than the setting freq.
+* 2. SET_DIV and SET_PLLDIV commands which would set divisor register must use CLK_ENABLE command
+*    first to enable device clock.
+* 3. Due to default frequency may be extremely fast when clock is enabled. use SET_PLL command can
+*    set the frequency into a reasonable value, but don't need to enable clock first.
+*/
+#define PMC_TABLE 1
+int auto_pll_divisor(enum dev_id dev, enum clk_cmd cmd, int unit, int freq)
+{
+	int last_freq, divisor, en_count;
+
+	switch (cmd) {
+		case CLK_DISABLE:
+			if (dev < 128) {
+				en_count = disable_dev_clk(dev);
+				return en_count;
+			} else {
+				printf("device has not clock enable register");
+				return -1;
+			}
+		case CLK_ENABLE:
+			if (dev < 128) {
+				en_count = enable_dev_clk(dev);
+				return en_count;
+			} else {
+				printf("device has not clock enable register");
+				return -1;
+			}
+		case GET_FREQ:
+			#ifdef PMC_TABLE
+			last_freq = get_freq_t(dev, &divisor);
+			#else
+			last_freq = get_freq(dev, &divisor);
+			#endif
+			return last_freq;
+		case SET_DIV:
+			divisor = 0;
+			#ifdef PMC_TABLE
+			last_freq = set_divisor_t(dev, unit, freq, &divisor);
+			#else
+			last_freq = set_divisor(dev, unit, freq, &divisor);
+			#endif
+			return last_freq;
+		case SET_PLL:
+			divisor = 0;
+			#ifdef PMC_TABLE
+			last_freq = set_pll_speed_t(dev, unit, freq, &divisor, 1);
+			#else
+			last_freq = set_pll_speed(dev, unit, freq, &divisor);
+			#endif
+			return last_freq;
+		case SET_PLLDIV:
+			divisor = 0;
+			#ifdef PMC_TABLE
+			last_freq = set_pll_divisor_t(dev, unit, freq, &divisor);
+			#else
+			last_freq = set_pll_divisor(dev, unit, freq, &divisor);
+			#endif
+			return last_freq;
+		default:
+		printf("clock cmd unknow");
+		return -1;
+	}
+}
+
+
+/**
+* freq = src_freq * 2 * (DIVF+1)/((DIVR+1)*(2^DIVQ))
+*
+* dev : Target device ID to be set the clock.
+* DIVF : Feedback divider value.
+* DIVR : Reference divider value.
+* DIVQ : Output divider value.
+* dev_div : Divisor belongs to each device, 0 means not changed.
+* return : The final clock freq, in Hz, will be returned when success,
+*            -1 means fail (waiting busy timeout).
+*
+* caution :
+* 1. src_freq/(DIVR+1) should great than or equal to 10,
+*/
+int manu_pll_divisor(enum dev_id dev, int DIVF, int DIVR, int DIVQ, int dev_div)
+{
+
+	unsigned int PLL, freq, pmc_clk_en, old_divisor, div;
+	int PLL_NO, div_addr_offs, j = 0, SD_MMC = 0;
+	
+	if (DIVF < 0 || DIVF > MAX_DF){
+		printf("DIVF is out of range 0 ~ 127");
+		return -1;
+	}
+	if (DIVR < 0 || DIVR > MAX_DR){
+		printf("DIVR is out of range 0 ~ 1");
+		return -1;
+	}
+	if (DIVQ < 0 || DIVQ > MAX_DQ){
+		printf("DIVQ is out of range 0 ~ 3");
+		return -1;
+	}
+	if ((800/SRC_FREQ) > ((2*(DIVF+1))/(DIVR+1))) {
+		printf("((2(DIVF+1))/(DIVR+1)) should great than (800/SRC_FREQ)");
+		return -1;
+	}
+	if ((1600/SRC_FREQ) < ((2*(DIVF+1))/(DIVR+1))) {
+		printf("((2*(DIVF+1))/(DIVR+1)) should less than (1600/SRC_FREQ)");
+		return -1;
+	}
+
+	if (dev_div > ((SD_MMC == 1)?63:31)){
+		printf("divisor is out of range 0 ~ 31");
+		return -1;
+	}
+
+	PLL_NO = calc_pll_num(dev, &div_addr_offs);
+	if (PLL_NO == -1) {
+		printf("device not found");
+		return -1;
+	}
+	old_divisor = *(volatile unsigned char *)(PMC_BASE + div_addr_offs);
+
+	if (SD_MMC == 1 && (dev_div&32))
+		j = 1; /* sdmmc has a another divider = 64 */	
+	div = dev_div&0x1F;	
+	freq = (1000 * SRC_FREQ * 2 * (DIVF+1))/((DIVR+1)*(1<<DIVQ)*div*(j?128:1));
+	freq *= 1000;
+	//printf("DIVF%d, DIVR%d, DIVQ%d, dev_div%d, freq=%dkHz\n", DIVF, DIVR, DIVQ, dev_div, freq);
+
+	PLL = (DIVF<<16) + (DIVR<<8) + DIVQ;
+
+	/* if the clk of the device is not enable, then enable it */
+	if (dev < 128) {
+		pmc_clk_en = *(volatile unsigned int *)(PMC_CLK + 4*(dev/32));
+		if (!(pmc_clk_en & (1 << (dev - 32*(dev/32)))))
+			enable_dev_clk(dev);
+	}
+
+	check_PLL_DIV_busy();
+	if (old_divisor < dev_div) {
+		*(volatile unsigned int *)(PMC_BASE + div_addr_offs)
+		= (j?32:0) + ((div == 32) ? 0 : div)/* + (div&1) ? (1<<8): 0*/;
+		check_PLL_DIV_busy();
+	}
+	*(volatile unsigned int *)(PMC_PLL + 4*PLL_NO) = PLL;
+	check_PLL_DIV_busy();
+	if (old_divisor > dev_div) {
+		*(volatile unsigned int *)(PMC_BASE + div_addr_offs)
+		= (j?32:0) + ((div == 32) ? 0 : div)/* + (div&1) ? (1<<8): 0*/;
+		check_PLL_DIV_busy();
+	}
+
+
+	//PLL = (j?32:0) + ((div == 32) ? 0 : div) /*+ (div&1) ? (1<<8): 0*/;
+	//printf("set divisor =0x%x, divider address=0x%x\n", PLL, (PMC_BASE + div_addr_offs));
+	return freq;
+}
+
+
diff --git a/board/wmt/wmt_gpio.c b/board/wmt/wmt_gpio.c
new file mode 100755
index 0000000..41ff6ed
--- /dev/null
+++ b/board/wmt/wmt_gpio.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2013 WonderMedia Technologies, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include "include/wmt_iomux.h"
+
+#undef	WMT_PIN
+#define WMT_PIN(__gp, __bit, __irq, __name)	\
+	{ .label = #__name, .regoff = __gp, .shift = __bit, .irqnum = __irq },
+
+const static struct wmt_gpio {
+	const char *label;
+	unsigned char regoff;
+	unsigned char shift;
+	int irqnum;
+} wmt_gpios[] = {
+	#include "include/iomux.h"
+};
+
+#define INVALUE_REGS		0x00
+#define ENABLE_REGS		0x40
+#define DIRECTION_REGS		0x80
+#define OUTVALUE_REGS		0xc0
+
+#define INTMASK_REGS		0x300
+#define INTSTAT_REGS		0x360
+
+#define PULLENABLE_REGS		0x480
+#define PULLCONTROL_REGS	0x4c0
+
+#define GPIO_INT_LOW_LEV	0x0
+#define GPIO_INT_HIGH_LEV	0x1
+#define GPIO_INT_FALL_EDGE	0x2
+#define GPIO_INT_RISE_EDGE	0x3
+#define GPIO_INT_BOTH_EDGE	0x4
+
+#define CHIP_GPIO_BASE		0
+#define GPIO_BASE_ADDR 		0xD8110000
+
+static unsigned long port_base = GPIO_BASE_ADDR;
+
+static inline int gpio_request(unsigned gpio)
+{
+	uint8_t regoff = wmt_gpios[gpio].regoff;
+	uint8_t shift  = wmt_gpios[gpio].shift;
+	uint8_t val;
+
+	if (!gpio_is_valid(gpio))
+		return -EINVAL;
+
+	val = __raw_readb(port_base + ENABLE_REGS + regoff);
+	val |= (1 << shift);
+	__raw_writeb(val, port_base + ENABLE_REGS + regoff);
+
+	return 0;
+}
+
+void gpio_free(unsigned gpio)
+{
+	uint8_t regoff = wmt_gpios[gpio].regoff;
+	uint8_t shift  = wmt_gpios[gpio].shift;
+	uint8_t val;
+
+	if (!gpio_is_valid(gpio))
+		return;
+
+	val = __raw_readb(port_base + ENABLE_REGS + regoff);
+	val &= ~(1 << shift);
+	__raw_writeb(val, port_base + ENABLE_REGS + regoff);
+}
+
+static void _set_gpio_direction(unsigned gpio, int dir)
+{
+	uint8_t regoff = wmt_gpios[gpio].regoff;
+	uint8_t shift  = wmt_gpios[gpio].shift;
+	uint8_t val;
+
+	val = __raw_readb(port_base + DIRECTION_REGS + regoff);
+	if (dir)
+		val |= (1 << shift);
+	else
+		val &= ~(1 << shift);
+	__raw_writeb(val, port_base + DIRECTION_REGS + regoff);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+	uint8_t regoff = wmt_gpios[gpio].regoff;
+	uint8_t shift  = wmt_gpios[gpio].shift;
+
+	if (!gpio_is_valid(gpio))
+		return -EINVAL;
+
+	return (__raw_readb(port_base + INVALUE_REGS + regoff) >> shift) & 1;
+}
+
+void gpio_set_value(unsigned gpio, int value)
+{
+	uint8_t regoff = wmt_gpios[gpio].regoff;
+	uint8_t shift  = wmt_gpios[gpio].shift;
+	uint8_t val;
+
+	if (!gpio_is_valid(gpio))
+		return;
+
+	val = __raw_readb(port_base + OUTVALUE_REGS + regoff);
+	if (value)
+		val |= (1 << shift);
+	else
+		val &= ~(1 << shift);
+	__raw_writeb(val, port_base + OUTVALUE_REGS + regoff);
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+	if (!gpio_is_valid(gpio))
+		return -EINVAL;
+
+	gpio_request(gpio);
+	_set_gpio_direction(gpio, 0);
+	return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+	if (!gpio_is_valid(gpio))
+		return -EINVAL;
+
+	gpio_request(gpio);
+	gpio_set_value(gpio, value);
+	_set_gpio_direction(gpio, 1);
+	return 0;
+}
+
+static void _set_gpio_pullenable(unsigned gpio, int enable)
+{
+	uint8_t regoff = wmt_gpios[gpio].regoff;
+	uint8_t shift  = wmt_gpios[gpio].shift;
+	uint8_t val;
+
+	val = __raw_readb(port_base + PULLENABLE_REGS + regoff);
+	if (enable)
+		val |= (1 << shift);
+	else
+		val &= ~(1 << shift);
+	__raw_writeb(val, port_base + PULLENABLE_REGS + regoff);
+
+}
+
+static void _set_gpio_pullup(unsigned gpio, int up)
+{
+	uint8_t regoff = wmt_gpios[gpio].regoff;
+	uint8_t shift  = wmt_gpios[gpio].shift;
+	uint8_t val;
+
+	val = __raw_readb(port_base + PULLCONTROL_REGS + regoff);
+	if (up)
+		val |= (1 << shift);
+	else
+		val &= ~(1 << shift);
+	__raw_writeb(val, port_base + PULLCONTROL_REGS + regoff);
+}
+
+int gpio_setpull(unsigned int gpio, enum gpio_pulltype pull)
+{
+	if (!gpio_is_valid(gpio))
+		return -EINVAL;
+
+	switch (pull) {
+	case GPIO_PULL_NONE:
+		_set_gpio_pullenable(gpio, 0);
+		break;
+	case GPIO_PULL_UP:
+		_set_gpio_pullenable(gpio, 1);
+		_set_gpio_pullup(gpio, 1);
+		break;
+	case GPIO_PULL_DOWN:
+		_set_gpio_pullenable(gpio, 1);
+		_set_gpio_pullup(gpio, 0);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/*
+* Function  : parse_gpio_env
+*
+* Parameters:
+*  name           : the env's name
+*  p_env          : the env's content
+*
+*  For example: wmt.gpio.param=7:0
+*  the env name is wmt.gpio.param
+*  the env content is 7:0
+*
+* Return:
+*  0: env is existent and env is valid
+*  -1: env isn't existent or env is invalid
+*/
+int parse_gpio_env(char *name, GPIO_ENV *p_env)
+{
+ 	enum
+	{
+		idx_gpiono,
+		idx_active,
+		idx_max
+	};
+
+	char *p;
+	long ps[idx_max] = {0};
+	char * endp;
+	int i = 0;
+
+	p = getenv(name);
+	if (!p)
+        	return -1;
+
+    	//printf("parse_gpio_env: %s\n", p);
+
+   	while (i < idx_max) {
+		ps[i++] = simple_strtoul(p, &endp, 0);
+
+        	if (*endp == '\0')
+            		break;
+        	p = endp + 1;
+
+        	if (*p == '\0')
+			break;
+	}
+
+	p_env->gpiono = ps[0];
+	p_env->active = ps[1];
+
+	if(i != 2) {
+		printf("parse_gpio_env: wrong env num in '%s =%s'\n", name, p);
+		return -1;
+	}
+
+	if(gpio_is_valid(p_env->gpiono))
+		return 0;
+	else {
+		printf("parse_gpio_env: wrong gpio no in '%s =%s'\n", name, p);
+		return -1;
+	}
+}
+
diff --git a/board/wmt/wmt_i2c.c b/board/wmt/wmt_i2c.c
new file mode 100755
index 0000000..1777f97
--- /dev/null
+++ b/board/wmt/wmt_i2c.c
@@ -0,0 +1,660 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
+ * vanbaren@cideas.com.  It was heavily influenced by LiMon, written by
+ * Neil Russell.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include "include/i2c.h"
+#include "include/wmt_clk.h"
+#include <malloc.h>
+
+#if defined(CONFIG_HARD_I2C)
+
+/* #define	DEBUG_I2C	*/
+
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#define RETRIES		0
+
+
+#define I2C_ACK		0		/* PD_SDA level to ack a byte */
+#define I2C_NOACK	1		/* PD_SDA level to noack a byte */
+
+
+#ifdef DEBUG_I2C
+#define PRINTD(fmt, args...)	do {	\
+	DECLARE_GLOBAL_DATA_PTR;	\
+	if (gd->have_console)		\
+		printf(fmt , ##args);	\
+	} while (0)
+#else
+#define PRINTD(fmt, args...)
+#endif
+
+static struct i2c_s i2c ;
+static int retry_time = 3;
+
+/*-----------------------------------------------------------------------
+ * Local functions
+ */
+
+static int i2c_do_xfer(struct i2c_msg_s msgs[], int num);
+
+#if 0
+static int write_byte(uchar byte);
+#endif
+
+static int i2c_read_msg(unsigned short slave_addr, unsigned char *buf,
+			unsigned short length, int restart, int last);
+static int i2c_write_msg(unsigned short slave_addr, unsigned char *buf,
+			unsigned short length, int restart, int last);
+#if 0
+static uchar read_byte(int);
+#endif
+
+enum i2c_mode_s i2c_xfer_mode = I2C_STANDARD_MODE;
+
+extern int auto_pll_divisor(enum dev_id dev, enum clk_cmd cmd, int unit, int freq);
+extern int wmt_delayus(int us);
+
+#define GPIO_CTRL_I2C (*(volatile char *)0xD8110051)
+#define GPIO_PAD_EN_I2C (*(volatile char *)0xD8110491)
+#define GPIO_PAD_PU_I2C (*(volatile char *)0xD81104D1)
+
+/* [Rx00] GPIO Enable Control Register for I2C */
+#define GPIO_I2C0_SDA	0x00000002
+#define GPIO_I2C0_SCL	0x00000001
+/* [Rx600] GPIO Pull up/down  Control Register for I2C */
+#define GPIO_I2C0_SCL_PULL_EN 0x00000001
+#define GPIO_I2C0_SDA_PULL_EN 0x00000002
+#define GPIO_I2C0_SCL_PULL_UP 0x00000001
+#define GPIO_I2C0_SDA_PULL_UP 0x00000002
+
+static int i2c_wait_bus_not_busy(void)
+{
+	unsigned int timeout = 30000 ;
+
+	while (1) {
+		if ((i2c.regs->IICSR & I2C_STATUS_MASK) == I2C_READY)
+			break ;
+		--timeout ;
+		if (timeout == 0)
+			break ;
+	}
+	if (timeout == 0) {
+		PRINTD("i2c_err : wait ready timeout error\n\r") ;
+		return -1 ;
+	}
+	return  0 ;
+}
+
+
+#if 0
+/*-----------------------------------------------------------------------
+ * Send 8 bits and look for an acknowledgement.
+ */
+static int write_byte(uchar data)
+{
+	unsigned int length = 1;
+	int ret ;
+	unsigned char *buf[1];
+	struct i2c_msg_s wr[1];
+
+	*buf = 0x00;
+
+	wr[0].addr  = data ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = length ;
+	wr[0].buf   = (unsigned char *)buf ;
+	ret = i2c_transfer(wr, 1);
+
+	if (ret != 1) {
+		PRINTD("%d, %s, write fail with address=0x%X\n", __LINE__, __func__, address);
+		free(buf);
+		return -1;
+	}
+
+	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+	free(buf);
+
+	return 0 ;
+}
+
+
+/*-----------------------------------------------------------------------
+ * if ack == I2C_ACK, ACK the byte so can continue reading, else
+ * send I2C_NOACK to end the read.
+ */
+static uchar read_byte(int ack)
+{
+	return 1;
+}
+#endif
+
+/*=====================================================================*/
+/*                         Public Functions                            */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Initialization
+ */
+void i2c_init(int speed, int slaveaddr)
+{
+	unsigned short tmp ;
+
+	auto_pll_divisor(DEV_I2C0, CLK_ENABLE, 0, 0);
+	auto_pll_divisor(DEV_I2C0, SET_DIV, 2, 20);
+	/**/
+	/* software initial*/
+	i2c.regs = (struct I2C_REG *)BA_I2C0;
+	i2c.irq_no      = 19;
+	/*set i2c master transfer mode*/
+	if (i2c_xfer_mode == I2C_STANDARD_MODE)
+		i2c.i2c_mode    = I2C_STANDARD_MODE ;
+	else if (i2c_xfer_mode == I2C_FAST_MODE)
+		i2c.i2c_mode    = I2C_FAST_MODE ;
+	else if (i2c_xfer_mode == I2C_HS_MODE)
+		i2c.i2c_mode    = I2C_HS_MODE ;
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+	/* Set I2C/GPIO pinmux to IIC funciton*/
+	/* Set bit[0-3] to zero*/
+	GPIO_CTRL_I2C &= ~(GPIO_I2C0_SCL | GPIO_I2C0_SDA);
+	GPIO_PAD_EN_I2C |= (GPIO_I2C0_SCL_PULL_EN |
+			GPIO_I2C0_SDA_PULL_EN);
+	GPIO_PAD_PU_I2C |= (GPIO_I2C0_SCL_PULL_UP |
+			GPIO_I2C0_SDA_PULL_UP);
+
+	/* Ensure I2C clock is enabled*/
+	/*set i2c master register */
+	i2c.regs->IICCR = 0;
+	i2c.regs->IICDIV = 12;		/* 12MHz input clk directly*/
+	i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
+	i2c.regs->IICIMR = I2C_IMR_ALL_ENABLE;
+	i2c.regs->IICCR = I2C_CR_ENABLE;
+	tmp = i2c.regs->IICSR;		/* Read clear "received ACK bit"*/
+	i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		i2c.regs->IICTR = I2C_TR_STD_VALUE ;   /* 0x8064*/
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		i2c.regs->IICTR = I2C_TR_FAST_VALUE ; /* 0x8019*/
+
+	return ;
+}
+
+/*===========================================================================*/
+/*  i2c_transfer*/
+/**/
+/*  return:*/
+/*===========================================================================*/
+int i2c_transfer(struct i2c_msg_s msgs[], int num)
+{
+	int ret ;
+	int retries ;
+	int i;
+	int delay = 1000;
+
+	retries = retry_time ;
+	for (i = retries ;  i > 0; i--) {
+		ret = i2c_do_xfer(msgs, num);
+		if (ret > 0)
+			return ret ;
+
+		PRINTD("%s:i2c_test: retrying transmission\n\r", __func__);
+		delay = 1000;
+		while (delay == 0)
+			delay--;
+	}
+	wmt_delayus(100);/*100us*/
+
+	PRINTD("i2c_err : retried %i times\n\r", retries);
+	return -1 ;
+
+}
+
+static int i2c_do_xfer(struct i2c_msg_s msgs[], int num)
+{
+	struct i2c_msg_s *pmsg = NULL;
+	int i;
+	int ret = 0 ;
+
+	ret = i2c_wait_bus_not_busy();
+	if (ret < 0)
+		return ret ;
+
+	for (i = 0; ret >= 0 && i < num; i++) {
+		int last = ((i + 1) == num);
+		int restart = (i != 0) ;
+		pmsg = &msgs[i];
+
+		if (pmsg->flags & I2C_M_RD) /* READ*/
+			ret = i2c_read_msg(pmsg->addr, pmsg->buf, pmsg->len, restart, last);
+		else /* Write*/
+			ret = i2c_write_msg(pmsg->addr, pmsg->buf, pmsg->len, restart, last);
+	}
+
+	if (ret < 0)
+		return ret;
+	else
+		return i;
+}
+/*-----------------------------------------------------------------------
+ * Probe to see if a chip is present.  Also good for checking for the
+ * completion of EEPROM writes since the chip stops responding until
+ * the write completes (typically 10mSec).
+ */
+int i2c_probe(uchar addr)
+{
+	int rc;
+
+	/* perform 1 byte read transaction */
+	/*
+	rc = write_byte(addr);
+	*/
+	rc = 1;
+
+	return rc ? 1 : 0;
+}
+
+/*===========================================================================*/
+/*  i2c_irq_handler*/
+/**/
+/*  return: NULL*/
+/*===========================================================================*/
+static void i2c_irq_handler(void)
+{
+	unsigned short isr_status ;
+
+	isr_status = i2c.regs->IICISR ;
+
+	if (isr_status & I2C_ISR_NACK_ADDR) {
+		unsigned short tmp ;
+		i2c.regs->IICISR = I2C_ISR_NACK_ADDR_WRITE_CLEAR ;
+		tmp = i2c.regs->IICSR ;  /* read clear*/
+		i2c.isr_nack = 1 ;
+		return ;
+	}
+
+	if (isr_status & I2C_ISR_BYTE_END) {
+		i2c.regs->IICISR = I2C_ISR_BYTE_END_WRITE_CLEAR ;
+		i2c.isr_byte_end = 1 ;
+		return ;
+	}
+
+	if (isr_status & I2C_ISR_SCL_TIME_OUT) {
+		i2c.regs->IICISR = I2C_ISR_SCL_TIME_OUT_WRITE_CLEAR ;
+		i2c.isr_timeout = 1 ;
+		return ;
+	} else {
+		PRINTD("i2c_err : unknown I2C ISR Handle 0x%4.4X" , isr_status) ;
+		return ;
+	}
+}
+
+/*
+ * i2c_write_msg
+ * return: 0 success
+ *         -1 fail
+ */
+static int i2c_write_msg(unsigned short slave_addr,
+			unsigned char *buf,
+			unsigned short length,
+			int restart,
+			int last)
+{
+	unsigned short tcr_value ;
+	unsigned int xfer_length ;
+	unsigned int timeout ;
+	if (length == 0)
+		return -1 ;
+	xfer_length = 0 ; /* for array index and also for checking counting*/
+
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+
+	i2c.regs->IICDR = (unsigned short)(buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK)  ;
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else {
+		tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+		i2c.regs->IICDIV = HS_MASTER_CODE;
+	}
+
+	/* SET TRANSFER MODE*/
+	i2c.regs->IICTCR = tcr_value ;
+
+	/*repeat start case*/
+	if (restart == 1)
+		i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+
+	while (1) {
+		timeout = 500000 ;
+		while (1) {
+			i2c_irq_handler();
+			if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
+				break ;
+			--timeout ;
+			if (timeout == 0)
+				break ;
+		}
+		/* fail case*/
+		if (timeout == 0) {
+			PRINTD("[%s]i2c_err : wrire software timeout error (tx)\n\r", __func__) ;
+			return -1 ;
+		}
+		if (i2c.isr_nack == 1) {
+			PRINTD("i2c_err : write NACK error (tx) \n\r") ;
+			return -1 ;
+		}
+		if (i2c.isr_timeout == 1) {
+			PRINTD("%s:i2c_err : write SCL timeout error (tx)\n\r", __func__) ;
+			return -1 ;
+		}
+
+		/* pass case*/
+		if (i2c.isr_byte_end == 1)
+			++xfer_length ;
+		i2c.isr_nack    = 0 ;
+		i2c.isr_byte_end = 0 ;
+		i2c.isr_timeout = 0 ;
+
+		if ((i2c.regs->IICSR & I2C_CSR_RCV_ACK_MASK) == I2C_CSR_RCV_NOT_ACK) {
+			PRINTD("i2c_err : write RCV NACK error\n\r") ;
+			return -1 ;
+		}
+
+
+		if (length > xfer_length) {
+			i2c.regs->IICDR = (unsigned short) (buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK) ;
+			i2c.regs->IICCR = (I2C_CR_CPU_RDY | I2C_CR_ENABLE) ;
+		} else if (length == xfer_length) { /* end tx xfer*/
+			if (last == 1) {  /* stop case*/
+				//i2c.regs->IICCR = (I2C_CR_TX_END|I2C_CR_CPU_RDY|I2C_CR_ENABLE) ;
+				wmt_delayus(2);/*2 us*/
+				i2c.regs->IICCR |= (I2C_CR_TX_END) ;
+				break ;
+			} else {  /* restart case*/
+				/* handle the restart for first write then the next is read*/
+				i2c.regs->IICCR = (I2C_CR_ENABLE) ;
+				break ;
+			}
+		} else {
+			PRINTD("i2c_err : write unknown error\n\r") ;
+			return -1 ;
+		}
+	}
+	i2c.regs->IICCR &= ~(I2C_CR_TX_END|I2C_CR_CPU_RDY) ;
+	return 0 ;
+}
+
+/*
+ * i2c_read_msg
+ * return: 0 success
+ *         -1 fail
+ */
+static int i2c_read_msg(unsigned short slave_addr,
+			unsigned char *buf,
+			unsigned short length,
+			int restart,
+			int last)
+{
+	unsigned short tcr_value ;
+	unsigned int xfer_length ;
+	unsigned int timeout ;
+
+	if (length == 0)
+		return -1 ;
+	xfer_length = 0 ;
+
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else
+		tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+
+	i2c.regs->IICTCR = tcr_value;
+
+	/*repeat start case*/
+	if (restart == 1)
+		i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+
+	if (length == 1)
+		i2c.regs->IICCR |= I2C_CR_TX_NEXT_NO_ACK; /*only 8-bit to read*/
+
+	while (1) {
+		timeout = 500000 ;
+		while (1) {
+			i2c_irq_handler();
+			if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
+				break ;
+			--timeout ;
+			if (timeout == 0)
+				break ;
+		}
+		/* fail case*/
+		if (i2c.isr_nack == 1) {
+			PRINTD("i2c_err : write NACK error (rx) \n\r") ;
+			return -1 ;
+		}
+		if (i2c.isr_timeout == 1) {
+			PRINTD("%s, i2c_err : write SCL timeout error (rx)\n\r", __func__) ;
+			return -1 ;
+		}
+		if (timeout == 0) {
+			PRINTD("[%s]i2c_err: write software timeout error (rx) \n\r", __func__) ;
+			return -1 ;
+		}
+		/* pass case*/
+		if (i2c.isr_byte_end == 1) {
+			buf[xfer_length] = (i2c.regs->IICDR >> 8) ;
+			++xfer_length ;
+		}
+		i2c.isr_nack    = 0 ;
+		i2c.isr_byte_end = 0 ;
+		i2c.isr_timeout = 0 ;
+
+		if (length > xfer_length) {
+			if ((length - 1) ==  xfer_length) /* next read is the last one*/
+				i2c.regs->IICCR |= (I2C_CR_TX_NEXT_NO_ACK | I2C_CR_CPU_RDY);
+			else
+				i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+		} else if (length == xfer_length) { /* end rx xfer*/
+			if (last == 1)  /* stop case*/
+				break ;
+			else  /* restart case*/
+				/* ??? how to handle the restart after read ?*/
+				break ;
+		} else {
+			PRINTD("i2c_err : read known error\n\r") ;
+			return -1 ;
+		}
+	}
+	PRINTD("i2c_test: read sequence completed\n\r");
+	i2c.regs->IICCR &= ~(I2C_CR_TX_NEXT_NO_ACK | I2C_CR_CPU_RDY);
+	return 0 ;
+}
+
+/*-----------------------------------------------------------------------
+ * Read bytes
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int ret;
+	unsigned char *reg_idx;
+	struct i2c_msg_s wr[1] ;
+	struct i2c_msg_s rd[1] ;
+	int i = 0;
+
+	reg_idx = calloc(alen, sizeof(unsigned char *));
+	for (i = 0; i < alen; ++i)
+		reg_idx[i] = (addr & (0xff << i*8)) >> i*8;
+
+	wr[0].addr  = chip ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = alen ;
+	wr[0].buf   = reg_idx ;
+
+	rd[0].addr  = chip ;
+	rd[0].flags = I2C_M_RD ;
+	rd[0].len   = len ;
+	rd[0].buf   = buffer  ;
+
+	if (alen > 0)
+		ret = i2c_transfer(wr, 1);
+	ret = i2c_transfer(rd, 1);
+
+	PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+
+	if (ret != 1) {
+		PRINTD("[i2c_register_read] read fail \n");
+		free(reg_idx);
+		return -1;
+	}
+
+	free(reg_idx);
+	return 0 ;
+
+}
+
+/*-----------------------------------------------------------------------
+ * Write bytes
+ */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	unsigned int length = len + alen;
+	int ret ;
+	unsigned char *buf;
+	struct i2c_msg_s wr[1];
+	unsigned int i = 0;
+	buf = calloc(length, sizeof(unsigned char *));
+
+	for (i = 0; i < length; ++i) {
+		if (i < alen)
+			*(buf + alen - i - 1) = (unsigned char) ((addr >> (i * 8)) & 0xFF);
+		else
+			*(buf + i) = *(buffer + i - alen);
+	}
+	wr[0].addr  = chip ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = length ;
+	wr[0].buf   = buf ;
+	ret = i2c_transfer(wr, 1);
+
+	if (ret != 1) {
+		PRINTD("%d, %s, write fail with address=0x%X\n", __LINE__, __func__, address);
+		free(buf);
+		return -1;
+	}
+
+	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+	free(buf);
+
+	return 0 ;
+}
+
+/*-----------------------------------------------------------------------
+ * Read a register
+ */
+uchar i2c_reg_read(uchar i2c_addr, uchar reg)
+{
+	uchar buf;
+
+	i2c_read(i2c_addr, reg, 1, &buf, 1);
+
+	return buf;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a register
+ */
+void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c_write(i2c_addr, reg, 1, &val, 1);
+}
+
+int wmt_i2c_transfer(struct i2c_msg_s msgs[], int num, int adap_id)
+{
+	int ret;
+	switch (adap_id) {
+	case 0:
+		ret = i2c_transfer(msgs, num);
+	break;
+	case 1:
+		ret = i2c1_transfer(msgs, num);
+	break;
+	case 2:
+		ret = i2c2_transfer(msgs, num);
+	break;
+	case 3:
+		ret = i2c3_transfer(msgs, num);
+	break;
+	default:
+		ret = -1;
+		printf("err:adap_id[%d] is not exist", adap_id);
+	break;
+	}
+	return ret;
+	
+}
+
+#endif	/* CONFIG_SOFT_I2C */
diff --git a/board/wmt/wmt_i2c_1.c b/board/wmt/wmt_i2c_1.c
new file mode 100755
index 0000000..6a8f008
--- /dev/null
+++ b/board/wmt/wmt_i2c_1.c
@@ -0,0 +1,636 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
+ * vanbaren@cideas.com.  It was heavily influenced by LiMon, written by
+ * Neil Russell.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include "include/i2c.h"
+#include "include/wmt_clk.h"
+#include <malloc.h>
+
+#if defined(CONFIG_HARD_I2C)
+
+/* #define	DEBUG_I2C	*/
+
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#define RETRIES		0
+
+
+#define I2C_ACK		0		/* PD_SDA level to ack a byte */
+#define I2C_NOACK	1		/* PD_SDA level to noack a byte */
+
+
+#ifdef DEBUG_I2C
+#define PRINTD(fmt, args...)	do {	\
+	DECLARE_GLOBAL_DATA_PTR;	\
+	if (gd->have_console)		\
+		printf(fmt , ##args);	\
+	} while (0)
+#else
+#define PRINTD(fmt, args...)
+#endif
+
+static struct i2c_s i2c ;
+static int retry_time = 3;
+
+/*-----------------------------------------------------------------------
+ * Local functions
+ */
+
+static int i2c_do_xfer(struct i2c_msg_s msgs[], int num);
+
+#if 0
+static int write_byte(uchar byte);
+#endif
+
+static int i2c_read_msg(unsigned short slave_addr, unsigned char *buf,
+			unsigned short length, int restart, int last);
+static int i2c_write_msg(unsigned short slave_addr, unsigned char *buf,
+			unsigned short length, int restart, int last);
+#if 0
+static uchar read_byte(int);
+#endif
+
+static enum i2c_mode_s i2c_xfer_mode = I2C_STANDARD_MODE;
+
+extern int auto_pll_divisor(enum dev_id dev, enum clk_cmd cmd, int unit, int freq);
+extern int wmt_delayus(int us);
+
+#define GPIO_CTRL_I2C (*(volatile char *)0xD8110051)
+#define GPIO_PAD_EN_I2C (*(volatile char *)0xD8110491)
+#define GPIO_PAD_PU_I2C (*(volatile char *)0xD81104D1)
+
+/* [Rx00] GPIO Enable Control Register for I2C */
+#define GPIO_I2C1_SDA	0x00000008
+#define GPIO_I2C1_SCL	0x00000004
+/* [Rx600] GPIO Pull up/down  Control Register for I2C */
+#define GPIO_I2C1_SCL_PULL_EN 0x00000008
+#define GPIO_I2C1_SDA_PULL_EN 0x00000004
+#define GPIO_I2C1_SCL_PULL_UP 0x00000004
+#define GPIO_I2C1_SDA_PULL_UP 0x00000008
+
+static int i2c_wait_bus_not_busy(void)
+{
+	unsigned int timeout = 30000 ;
+
+	while (1) {
+		if ((i2c.regs->IICSR & I2C_STATUS_MASK) == I2C_READY)
+			break ;
+		--timeout ;
+		if (timeout == 0)
+			break ;
+	}
+	if (timeout == 0) {
+		PRINTD("i2c_err : wait ready timeout error\n\r") ;
+		return -1 ;
+	}
+	return  0 ;
+}
+
+
+#if 0
+/*-----------------------------------------------------------------------
+ * Send 8 bits and look for an acknowledgement.
+ */
+static int write_byte(uchar data)
+{
+	unsigned int length = 1;
+	int ret ;
+	unsigned char *buf[1];
+	struct i2c_msg_s wr[1];
+
+	*buf = 0x00;
+
+	wr[0].addr  = data ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = length ;
+	wr[0].buf   = (unsigned char *)buf ;
+	ret = i2c_transfer(wr, 1);
+
+	if (ret != 1) {
+		PRINTD("%d, %s, write fail with address=0x%X\n", __LINE__, __func__, address);
+		free(buf);
+		return -1;
+	}
+
+	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+	free(buf);
+
+	return 0 ;
+}
+
+
+/*-----------------------------------------------------------------------
+ * if ack == I2C_ACK, ACK the byte so can continue reading, else
+ * send I2C_NOACK to end the read.
+ */
+static uchar read_byte(int ack)
+{
+	return 1;
+}
+#endif
+
+/*=====================================================================*/
+/*                         Public Functions                            */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Initialization
+ */
+void i2c1_init(int speed, int slaveaddr)
+{
+	unsigned short tmp ;
+
+	auto_pll_divisor(DEV_I2C1, CLK_ENABLE, 0, 0);
+	auto_pll_divisor(DEV_I2C1, SET_DIV, 2, 20);
+	/**/
+	/* software initial*/
+	i2c.regs = (struct I2C_REG *)BA_I2C1;
+	i2c.irq_no      = 18;
+	/*set i2c master transfer mode*/
+	if (i2c_xfer_mode == I2C_STANDARD_MODE)
+		i2c.i2c_mode    = I2C_STANDARD_MODE ;
+	else if (i2c_xfer_mode == I2C_FAST_MODE)
+		i2c.i2c_mode    = I2C_FAST_MODE ;
+	else if (i2c_xfer_mode == I2C_HS_MODE)
+		i2c.i2c_mode    = I2C_HS_MODE ;
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+	/* Set I2C/GPIO pinmux to IIC funciton*/
+	/* Set bit[0-3] to zero*/
+	GPIO_CTRL_I2C &= ~(GPIO_I2C1_SCL | GPIO_I2C1_SDA);
+	GPIO_PAD_EN_I2C |= (GPIO_I2C1_SCL_PULL_EN |
+			GPIO_I2C1_SDA_PULL_EN);
+	GPIO_PAD_PU_I2C |= (GPIO_I2C1_SCL_PULL_UP |
+			GPIO_I2C1_SDA_PULL_UP);
+
+	/* Ensure I2C clock is enabled*/
+	/*set i2c master register */
+	i2c.regs->IICCR = 0;
+	i2c.regs->IICDIV = 12;		/* 12MHz input clk directly*/
+	i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
+	i2c.regs->IICIMR = I2C_IMR_ALL_ENABLE;
+	i2c.regs->IICCR = I2C_CR_ENABLE;
+	tmp = i2c.regs->IICSR;		/* Read clear "received ACK bit"*/
+	i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		i2c.regs->IICTR = I2C_TR_STD_VALUE ;   /* 0x8064*/
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		i2c.regs->IICTR = I2C_TR_FAST_VALUE ; /* 0x8019*/
+
+	return ;
+}
+
+/*===========================================================================*/
+/*  i2c_transfer*/
+/**/
+/*  return:*/
+/*===========================================================================*/
+int i2c1_transfer(struct i2c_msg_s msgs[], int num)
+{
+	int ret ;
+	int retries ;
+	int i;
+	int delay = 1000;
+
+	retries = retry_time ;
+	for (i = retries ;  i > 0; i--) {
+		ret = i2c_do_xfer(msgs, num);
+		if (ret > 0)
+			return ret ;
+
+		PRINTD("%s:i2c_test: retrying transmission\n\r", __func__);
+		delay = 1000;
+		while (delay == 0)
+			delay--;
+	}
+	wmt_delayus(100) ;
+
+	PRINTD("i2c_err : retried %i times\n\r", retries);
+	return -1 ;
+
+}
+
+static int i2c_do_xfer(struct i2c_msg_s msgs[], int num)
+{
+	struct i2c_msg_s *pmsg = NULL;
+	int i;
+	int ret = 0 ;
+
+	ret = i2c_wait_bus_not_busy();
+	if (ret < 0)
+		return ret ;
+
+	for (i = 0; ret >= 0 && i < num; i++) {
+		int last = ((i + 1) == num);
+		int restart = (i != 0) ;
+		pmsg = &msgs[i];
+
+		if (pmsg->flags & I2C_M_RD) /* READ*/
+			ret = i2c_read_msg(pmsg->addr, pmsg->buf, pmsg->len, restart, last);
+		else /* Write*/
+			ret = i2c_write_msg(pmsg->addr, pmsg->buf, pmsg->len, restart, last);
+	}
+
+	if (ret < 0)
+		return ret;
+	else
+		return i;
+}
+/*-----------------------------------------------------------------------
+ * Probe to see if a chip is present.  Also good for checking for the
+ * completion of EEPROM writes since the chip stops responding until
+ * the write completes (typically 10mSec).
+ */
+int i2c1_probe(uchar addr)
+{
+	int rc;
+
+	/* perform 1 byte read transaction */
+	/*
+	rc = write_byte(addr);
+	*/
+	rc = 1;
+
+	return rc ? 1 : 0;
+}
+
+/*===========================================================================*/
+/*  i2c_irq_handler*/
+/**/
+/*  return: NULL*/
+/*===========================================================================*/
+static void i2c_irq_handler(void)
+{
+	unsigned short isr_status ;
+
+	isr_status = i2c.regs->IICISR ;
+
+	if (isr_status & I2C_ISR_NACK_ADDR) {
+		unsigned short tmp ;
+		i2c.regs->IICISR = I2C_ISR_NACK_ADDR_WRITE_CLEAR ;
+		tmp = i2c.regs->IICSR ;  /* read clear*/
+		i2c.isr_nack = 1 ;
+		return ;
+	}
+
+	if (isr_status & I2C_ISR_BYTE_END) {
+		i2c.regs->IICISR = I2C_ISR_BYTE_END_WRITE_CLEAR ;
+		i2c.isr_byte_end = 1 ;
+		return ;
+	}
+
+	if (isr_status & I2C_ISR_SCL_TIME_OUT) {
+		i2c.regs->IICISR = I2C_ISR_SCL_TIME_OUT_WRITE_CLEAR ;
+		i2c.isr_timeout = 1 ;
+		return ;
+	} else {
+		PRINTD("i2c_err : unknown I2C ISR Handle 0x%4.4X" , isr_status) ;
+		return ;
+	}
+}
+
+/*
+ * i2c_write_msg
+ * return: 0 success
+ *         -1 fail
+ */
+static int i2c_write_msg(unsigned short slave_addr,
+			unsigned char *buf,
+			unsigned short length,
+			int restart,
+			int last)
+{
+	unsigned short tcr_value ;
+	unsigned int xfer_length ;
+	unsigned int timeout ;
+	if (length == 0)
+		return -1 ;
+	xfer_length = 0 ; /* for array index and also for checking counting*/
+
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+
+	i2c.regs->IICDR = (unsigned short)(buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK)  ;
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else {
+		tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+		i2c.regs->IICDIV = HS_MASTER_CODE;
+	}
+
+	/* SET TRANSFER MODE*/
+	i2c.regs->IICTCR = tcr_value ;
+
+	/*repeat start case*/
+	if (restart == 1)
+		i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+
+	while (1) {
+		timeout = 500000 ;
+		while (1) {
+			i2c_irq_handler();
+			if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
+				break ;
+			--timeout ;
+			if (timeout == 0)
+				break ;
+		}
+		/* fail case*/
+		if (timeout == 0) {
+			PRINTD("[%s]i2c_err : wrire software timeout error (tx)\n\r", __func__) ;
+			return -1 ;
+		}
+		if (i2c.isr_nack == 1) {
+			PRINTD("i2c_err : write NACK error (tx) \n\r") ;
+			return -1 ;
+		}
+		if (i2c.isr_timeout == 1) {
+			PRINTD("%s:i2c_err : write SCL timeout error (tx)\n\r", __func__) ;
+			return -1 ;
+		}
+
+		/* pass case*/
+		if (i2c.isr_byte_end == 1)
+			++xfer_length ;
+		i2c.isr_nack    = 0 ;
+		i2c.isr_byte_end = 0 ;
+		i2c.isr_timeout = 0 ;
+
+		if ((i2c.regs->IICSR & I2C_CSR_RCV_ACK_MASK) == I2C_CSR_RCV_NOT_ACK) {
+			PRINTD("i2c_err : write RCV NACK error\n\r") ;
+			return -1 ;
+		}
+
+
+		if (length > xfer_length) {
+			i2c.regs->IICDR = (unsigned short) (buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK) ;
+			i2c.regs->IICCR = (I2C_CR_CPU_RDY | I2C_CR_ENABLE) ;
+		} else if (length == xfer_length) { /* end tx xfer*/
+			if (last == 1) {  /* stop case*/
+				//i2c.regs->IICCR = (I2C_CR_TX_END|I2C_CR_CPU_RDY|I2C_CR_ENABLE) ;
+				wmt_delayus(2);/*2 us*/
+				i2c.regs->IICCR |= (I2C_CR_TX_END) ;
+				break ;
+			} else {  /* restart case*/
+				/* handle the restart for first write then the next is read*/
+				i2c.regs->IICCR = (I2C_CR_ENABLE) ;
+				break ;
+			}
+		} else {
+			PRINTD("i2c_err : write unknown error\n\r") ;
+			return -1 ;
+		}
+	}
+	i2c.regs->IICCR &= ~(I2C_CR_TX_END|I2C_CR_CPU_RDY) ;
+	return 0 ;
+}
+
+/*
+ * i2c_read_msg
+ * return: 0 success
+ *         -1 fail
+ */
+static int i2c_read_msg(unsigned short slave_addr,
+			unsigned char *buf,
+			unsigned short length,
+			int restart,
+			int last)
+{
+	unsigned short tcr_value ;
+	unsigned int xfer_length ;
+	unsigned int timeout ;
+
+	if (length == 0)
+		return -1 ;
+	xfer_length = 0 ;
+
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else
+		tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+
+	i2c.regs->IICTCR = tcr_value;
+
+	/*repeat start case*/
+	if (restart == 1)
+		i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+
+	if (length == 1)
+		i2c.regs->IICCR |= I2C_CR_TX_NEXT_NO_ACK; /*only 8-bit to read*/
+
+	while (1) {
+		timeout = 500000 ;
+		while (1) {
+			i2c_irq_handler();
+			if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
+				break ;
+			--timeout ;
+			if (timeout == 0)
+				break ;
+		}
+		/* fail case*/
+		if (i2c.isr_nack == 1) {
+			PRINTD("i2c_err : write NACK error (rx) \n\r") ;
+			return -1 ;
+		}
+		if (i2c.isr_timeout == 1) {
+			PRINTD("%s, i2c_err : write SCL timeout error (rx)\n\r", __func__) ;
+			return -1 ;
+		}
+		if (timeout == 0) {
+			PRINTD("[%s]i2c_err: write software timeout error (rx) \n\r", __func__) ;
+			return -1 ;
+		}
+		/* pass case*/
+		if (i2c.isr_byte_end == 1) {
+			buf[xfer_length] = (i2c.regs->IICDR >> 8) ;
+			++xfer_length ;
+		}
+		i2c.isr_nack    = 0 ;
+		i2c.isr_byte_end = 0 ;
+		i2c.isr_timeout = 0 ;
+
+		if (length > xfer_length) {
+			if ((length - 1) ==  xfer_length) /* next read is the last one*/
+				i2c.regs->IICCR |= (I2C_CR_TX_NEXT_NO_ACK | I2C_CR_CPU_RDY);
+			else
+				i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+		} else if (length == xfer_length) { /* end rx xfer*/
+			if (last == 1)  /* stop case*/
+				break ;
+			else  /* restart case*/
+				/* ??? how to handle the restart after read ?*/
+				break ;
+		} else {
+			PRINTD("i2c_err : read known error\n\r") ;
+			return -1 ;
+		}
+	}
+	PRINTD("i2c_test: read sequence completed\n\r");
+	i2c.regs->IICCR &= ~(I2C_CR_TX_NEXT_NO_ACK | I2C_CR_CPU_RDY);
+	return 0 ;
+}
+
+/*-----------------------------------------------------------------------
+ * Read bytes
+ */
+int i2c1_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int ret;
+	unsigned char *reg_idx;
+	struct i2c_msg_s wr[1] ;
+	struct i2c_msg_s rd[1] ;
+	int i = 0;
+
+	reg_idx = calloc(alen, sizeof(unsigned char *));
+	for (i = 0; i < alen; ++i)
+		reg_idx[i] = (addr & (0xff << i*8)) >> i*8;
+
+	wr[0].addr  = chip ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = alen ;
+	wr[0].buf   = reg_idx ;
+
+	rd[0].addr  = chip ;
+	rd[0].flags = I2C_M_RD ;
+	rd[0].len   = len ;
+	rd[0].buf   = buffer  ;
+
+	if (alen > 0)
+		ret = i2c1_transfer(wr, 1);
+	ret = i2c1_transfer(rd, 1);
+
+	PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+
+	if (ret != 1) {
+		PRINTD("[i2c_register_read] read fail \n");
+		free(reg_idx);
+		return -1;
+	}
+
+	free(reg_idx);
+	return 0 ;
+
+}
+
+/*-----------------------------------------------------------------------
+ * Write bytes
+ */
+int i2c1_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	unsigned int length = len + alen;
+	int ret ;
+	unsigned char *buf;
+	struct i2c_msg_s wr[1];
+	unsigned int i = 0;
+	buf = calloc(length, sizeof(unsigned char *));
+
+	for (i = 0; i < length; ++i) {
+		if (i < alen)
+			*(buf + alen - i - 1) = (unsigned char) ((addr >> (i * 8)) & 0xFF);
+		else
+			*(buf + i) = *(buffer + i - alen);
+	}
+	wr[0].addr  = chip ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = length ;
+	wr[0].buf   = buf ;
+	ret = i2c1_transfer(wr, 1);
+
+	if (ret != 1) {
+		PRINTD("%d, %s, write fail with address=0x%X\n", __LINE__, __func__, address);
+		free(buf);
+		return -1;
+	}
+
+	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+	free(buf);
+
+	return 0 ;
+}
+
+/*-----------------------------------------------------------------------
+ * Read a register
+ */
+uchar i2c1_reg_read(uchar i2c_addr, uchar reg)
+{
+	uchar buf;
+
+	i2c1_read(i2c_addr, reg, 1, &buf, 1);
+
+	return buf;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a register
+ */
+void i2c1_reg_write(uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c1_write(i2c_addr, reg, 1, &val, 1);
+}
+
+
+#endif	/* CONFIG_SOFT_I2C */
diff --git a/board/wmt/wmt_i2c_2.c b/board/wmt/wmt_i2c_2.c
new file mode 100755
index 0000000..8279464
--- /dev/null
+++ b/board/wmt/wmt_i2c_2.c
@@ -0,0 +1,635 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
+ * vanbaren@cideas.com.  It was heavily influenced by LiMon, written by
+ * Neil Russell.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include "include/i2c.h"
+#include "include/wmt_clk.h"
+#include <malloc.h>
+
+#if defined(CONFIG_HARD_I2C)
+
+/* #define	DEBUG_I2C	*/
+
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#define RETRIES		0
+
+
+#define I2C_ACK		0		/* PD_SDA level to ack a byte */
+#define I2C_NOACK	1		/* PD_SDA level to noack a byte */
+
+
+#ifdef DEBUG_I2C
+#define PRINTD(fmt, args...)	do {	\
+	DECLARE_GLOBAL_DATA_PTR;	\
+	if (gd->have_console)		\
+		printf(fmt , ##args);	\
+	} while (0)
+#else
+#define PRINTD(fmt, args...)
+#endif
+
+static struct i2c_s i2c ;
+static int retry_time = 3;
+
+/*-----------------------------------------------------------------------
+ * Local functions
+ */
+
+static int i2c_do_xfer(struct i2c_msg_s msgs[], int num);
+
+#if 0
+static int write_byte(uchar byte);
+#endif
+
+static int i2c_read_msg(unsigned short slave_addr, unsigned char *buf,
+			unsigned short length, int restart, int last);
+static int i2c_write_msg(unsigned short slave_addr, unsigned char *buf,
+			unsigned short length, int restart, int last);
+#if 0
+static uchar read_byte(int);
+#endif
+
+static enum i2c_mode_s i2c_xfer_mode = I2C_STANDARD_MODE;
+
+extern int auto_pll_divisor(enum dev_id dev, enum clk_cmd cmd, int unit, int freq);
+extern int wmt_delayus(int us);
+
+#define GPIO_CTRL_I2C (*(volatile char *)0xD8110051)
+#define GPIO_PAD_EN_I2C (*(volatile char *)0xD8110491)
+#define GPIO_PAD_PU_I2C (*(volatile char *)0xD81104D1)
+
+#define GPIO_I2C2_SDA	0x00000020
+#define GPIO_I2C2_SCL	0x00000010
+
+#define GPIO_I2C2_SCL_PULL_EN 0x00000010
+#define GPIO_I2C2_SDA_PULL_EN 0x00000020
+#define GPIO_I2C2_SCL_PULL_UP 0x00000010
+#define GPIO_I2C2_SDA_PULL_UP 0x00000020
+
+static int i2c_wait_bus_not_busy(void)
+{
+	unsigned int timeout = 30000 ;
+
+	while (1) {
+		if ((i2c.regs->IICSR & I2C_STATUS_MASK) == I2C_READY)
+			break ;
+		--timeout ;
+		if (timeout == 0)
+			break ;
+	}
+	if (timeout == 0) {
+		PRINTD("i2c_err : wait ready timeout error\n\r") ;
+		return -1 ;
+	}
+	return  0 ;
+}
+
+
+#if 0
+/*-----------------------------------------------------------------------
+ * Send 8 bits and look for an acknowledgement.
+ */
+static int write_byte(uchar data)
+{
+	unsigned int length = 1;
+	int ret ;
+	unsigned char *buf[1];
+	struct i2c_msg_s wr[1];
+
+	*buf = 0x00;
+
+	wr[0].addr  = data ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = length ;
+	wr[0].buf   = (unsigned char *)buf ;
+	ret = i2c_transfer(wr, 1);
+
+	if (ret != 1) {
+		PRINTD("%d, %s, write fail with address=0x%X\n", __LINE__, __func__, address);
+		free(buf);
+		return -1;
+	}
+
+	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+	free(buf);
+
+	return 0 ;
+}
+
+
+/*-----------------------------------------------------------------------
+ * if ack == I2C_ACK, ACK the byte so can continue reading, else
+ * send I2C_NOACK to end the read.
+ */
+static uchar read_byte(int ack)
+{
+	return 1;
+}
+#endif
+
+/*=====================================================================*/
+/*                         Public Functions                            */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Initialization
+ */
+void i2c2_init(int speed, int slaveaddr)
+{
+	unsigned short tmp ;
+
+	auto_pll_divisor(DEV_I2C2, CLK_ENABLE, 0, 0);
+	auto_pll_divisor(DEV_I2C2, SET_DIV, 2, 20);
+	/**/
+	/* software initial*/
+	i2c.regs = (struct I2C_REG *)BA_I2C2;
+	i2c.irq_no      = 7;
+	/*set i2c master transfer mode*/
+	if (i2c_xfer_mode == I2C_STANDARD_MODE)
+		i2c.i2c_mode    = I2C_STANDARD_MODE ;
+	else if (i2c_xfer_mode == I2C_FAST_MODE)
+		i2c.i2c_mode    = I2C_FAST_MODE ;
+	else if (i2c_xfer_mode == I2C_HS_MODE)
+		i2c.i2c_mode    = I2C_HS_MODE ;
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+	/* Set I2C/GPIO pinmux to IIC funciton*/
+	/* Set bit[0-3] to zero*/
+	GPIO_CTRL_I2C &= ~(GPIO_I2C2_SCL | GPIO_I2C2_SDA);
+	GPIO_PAD_EN_I2C |= (GPIO_I2C2_SCL_PULL_EN |
+			GPIO_I2C2_SDA_PULL_EN);
+	GPIO_PAD_PU_I2C |= (GPIO_I2C2_SCL_PULL_UP |
+			GPIO_I2C2_SDA_PULL_UP);
+
+	/* Ensure I2C clock is enabled*/
+	/*set i2c master register */
+	i2c.regs->IICCR = 0;
+	i2c.regs->IICDIV = 12;		/* 12MHz input clk directly*/
+	i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
+	i2c.regs->IICIMR = I2C_IMR_ALL_ENABLE;
+	i2c.regs->IICCR = I2C_CR_ENABLE;
+	tmp = i2c.regs->IICSR;		/* Read clear "received ACK bit"*/
+	i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		i2c.regs->IICTR = I2C_TR_STD_VALUE ;   /* 0x8064*/
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		i2c.regs->IICTR = I2C_TR_FAST_VALUE ; /* 0x8019*/
+
+	return ;
+}
+
+/*===========================================================================*/
+/*  i2c_transfer*/
+/**/
+/*  return:*/
+/*===========================================================================*/
+int i2c2_transfer(struct i2c_msg_s msgs[], int num)
+{
+	int ret ;
+	int retries ;
+	int i;
+	int delay = 1000;
+
+	retries = retry_time ;
+	for (i = retries ;  i > 0; i--) {
+		ret = i2c_do_xfer(msgs, num);
+		if (ret > 0)
+			return ret ;
+
+		PRINTD("%s:i2c_test: retrying transmission\n\r", __func__);
+		delay = 1000;
+		while (delay == 0)
+			delay--;
+	}
+	wmt_delayus(100) ;
+
+	PRINTD("i2c_err : retried %i times\n\r", retries);
+	return -1 ;
+
+}
+
+static int i2c_do_xfer(struct i2c_msg_s msgs[], int num)
+{
+	struct i2c_msg_s *pmsg = NULL;
+	int i;
+	int ret = 0 ;
+
+	ret = i2c_wait_bus_not_busy();
+	if (ret < 0)
+		return ret ;
+
+	for (i = 0; ret >= 0 && i < num; i++) {
+		int last = ((i + 1) == num);
+		int restart = (i != 0) ;
+		pmsg = &msgs[i];
+
+		if (pmsg->flags & I2C_M_RD) /* READ*/
+			ret = i2c_read_msg(pmsg->addr, pmsg->buf, pmsg->len, restart, last);
+		else /* Write*/
+			ret = i2c_write_msg(pmsg->addr, pmsg->buf, pmsg->len, restart, last);
+	}
+
+	if (ret < 0)
+		return ret;
+	else
+		return i;
+}
+/*-----------------------------------------------------------------------
+ * Probe to see if a chip is present.  Also good for checking for the
+ * completion of EEPROM writes since the chip stops responding until
+ * the write completes (typically 10mSec).
+ */
+int i2c2_probe(uchar addr)
+{
+	int rc;
+
+	/* perform 1 byte read transaction */
+	/*
+	rc = write_byte(addr);
+	*/
+	rc = 1;
+
+	return rc ? 1 : 0;
+}
+
+/*===========================================================================*/
+/*  i2c_irq_handler*/
+/**/
+/*  return: NULL*/
+/*===========================================================================*/
+static void i2c_irq_handler(void)
+{
+	unsigned short isr_status ;
+
+	isr_status = i2c.regs->IICISR ;
+
+	if (isr_status & I2C_ISR_NACK_ADDR) {
+		unsigned short tmp ;
+		i2c.regs->IICISR = I2C_ISR_NACK_ADDR_WRITE_CLEAR ;
+		tmp = i2c.regs->IICSR ;  /* read clear*/
+		i2c.isr_nack = 1 ;
+		return ;
+	}
+
+	if (isr_status & I2C_ISR_BYTE_END) {
+		i2c.regs->IICISR = I2C_ISR_BYTE_END_WRITE_CLEAR ;
+		i2c.isr_byte_end = 1 ;
+		return ;
+	}
+
+	if (isr_status & I2C_ISR_SCL_TIME_OUT) {
+		i2c.regs->IICISR = I2C_ISR_SCL_TIME_OUT_WRITE_CLEAR ;
+		i2c.isr_timeout = 1 ;
+		return ;
+	} else {
+		PRINTD("i2c_err : unknown I2C ISR Handle 0x%4.4X" , isr_status) ;
+		return ;
+	}
+}
+
+/*
+ * i2c_write_msg
+ * return: 0 success
+ *         -1 fail
+ */
+static int i2c_write_msg(unsigned short slave_addr,
+			unsigned char *buf,
+			unsigned short length,
+			int restart,
+			int last)
+{
+	unsigned short tcr_value ;
+	unsigned int xfer_length ;
+	unsigned int timeout ;
+	if (length == 0)
+		return -1 ;
+	xfer_length = 0 ; /* for array index and also for checking counting*/
+
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+
+	i2c.regs->IICDR = (unsigned short)(buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK)  ;
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else {
+		tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+		i2c.regs->IICDIV = HS_MASTER_CODE;
+	}
+
+	/* SET TRANSFER MODE*/
+	i2c.regs->IICTCR = tcr_value ;
+
+	/*repeat start case*/
+	if (restart == 1)
+		i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+
+	while (1) {
+		timeout = 500000 ;
+		while (1) {
+			i2c_irq_handler();
+			if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
+				break ;
+			--timeout ;
+			if (timeout == 0)
+				break ;
+		}
+		/* fail case*/
+		if (timeout == 0) {
+			PRINTD("[%s]i2c_err : wrire software timeout error (tx)\n\r", __func__) ;
+			return -1 ;
+		}
+		if (i2c.isr_nack == 1) {
+			PRINTD("i2c_err : write NACK error (tx) \n\r") ;
+			return -1 ;
+		}
+		if (i2c.isr_timeout == 1) {
+			PRINTD("%s:i2c_err : write SCL timeout error (tx)\n\r", __func__) ;
+			return -1 ;
+		}
+
+		/* pass case*/
+		if (i2c.isr_byte_end == 1)
+			++xfer_length ;
+		i2c.isr_nack    = 0 ;
+		i2c.isr_byte_end = 0 ;
+		i2c.isr_timeout = 0 ;
+
+		if ((i2c.regs->IICSR & I2C_CSR_RCV_ACK_MASK) == I2C_CSR_RCV_NOT_ACK) {
+			PRINTD("i2c_err : write RCV NACK error\n\r") ;
+			return -1 ;
+		}
+
+
+		if (length > xfer_length) {
+			i2c.regs->IICDR = (unsigned short) (buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK) ;
+			i2c.regs->IICCR = (I2C_CR_CPU_RDY | I2C_CR_ENABLE) ;
+		} else if (length == xfer_length) { /* end tx xfer*/
+			if (last == 1) {  /* stop case*/
+				//i2c.regs->IICCR = (I2C_CR_TX_END|I2C_CR_CPU_RDY|I2C_CR_ENABLE) ;
+				wmt_delayus(2);/*2 us*/
+				i2c.regs->IICCR |= (I2C_CR_TX_END) ;
+				break ;
+			} else {  /* restart case*/
+				/* handle the restart for first write then the next is read*/
+				i2c.regs->IICCR = (I2C_CR_ENABLE) ;
+				break ;
+			}
+		} else {
+			PRINTD("i2c_err : write unknown error\n\r") ;
+			return -1 ;
+		}
+	}
+	i2c.regs->IICCR &= ~(I2C_CR_TX_END|I2C_CR_CPU_RDY) ;
+	return 0 ;
+}
+
+/*
+ * i2c_read_msg
+ * return: 0 success
+ *         -1 fail
+ */
+static int i2c_read_msg(unsigned short slave_addr,
+			unsigned char *buf,
+			unsigned short length,
+			int restart,
+			int last)
+{
+	unsigned short tcr_value ;
+	unsigned int xfer_length ;
+	unsigned int timeout ;
+
+	if (length == 0)
+		return -1 ;
+	xfer_length = 0 ;
+
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else
+		tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+
+	i2c.regs->IICTCR = tcr_value;
+
+	/*repeat start case*/
+	if (restart == 1)
+		i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+
+	if (length == 1)
+		i2c.regs->IICCR |= I2C_CR_TX_NEXT_NO_ACK; /*only 8-bit to read*/
+
+	while (1) {
+		timeout = 500000 ;
+		while (1) {
+			i2c_irq_handler();
+			if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
+				break ;
+			--timeout ;
+			if (timeout == 0)
+				break ;
+		}
+		/* fail case*/
+		if (i2c.isr_nack == 1) {
+			PRINTD("i2c_err : write NACK error (rx) \n\r") ;
+			return -1 ;
+		}
+		if (i2c.isr_timeout == 1) {
+			PRINTD("%s, i2c_err : write SCL timeout error (rx)\n\r", __func__) ;
+			return -1 ;
+		}
+		if (timeout == 0) {
+			PRINTD("[%s]i2c_err: write software timeout error (rx) \n\r", __func__) ;
+			return -1 ;
+		}
+		/* pass case*/
+		if (i2c.isr_byte_end == 1) {
+			buf[xfer_length] = (i2c.regs->IICDR >> 8) ;
+			++xfer_length ;
+		}
+		i2c.isr_nack    = 0 ;
+		i2c.isr_byte_end = 0 ;
+		i2c.isr_timeout = 0 ;
+
+		if (length > xfer_length) {
+			if ((length - 1) ==  xfer_length) /* next read is the last one*/
+				i2c.regs->IICCR |= (I2C_CR_TX_NEXT_NO_ACK | I2C_CR_CPU_RDY);
+			else
+				i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+		} else if (length == xfer_length) { /* end rx xfer*/
+			if (last == 1)  /* stop case*/
+				break ;
+			else  /* restart case*/
+				/* ??? how to handle the restart after read ?*/
+				break ;
+		} else {
+			PRINTD("i2c_err : read known error\n\r") ;
+			return -1 ;
+		}
+	}
+	PRINTD("i2c_test: read sequence completed\n\r");
+	i2c.regs->IICCR &= ~(I2C_CR_TX_NEXT_NO_ACK | I2C_CR_CPU_RDY);
+	return 0 ;
+}
+
+/*-----------------------------------------------------------------------
+ * Read bytes
+ */
+int i2c2_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int ret;
+	unsigned char *reg_idx;
+	struct i2c_msg_s wr[1] ;
+	struct i2c_msg_s rd[1] ;
+	int i = 0;
+
+	reg_idx = calloc(alen, sizeof(unsigned char *));
+	for (i = 0; i < alen; ++i)
+		reg_idx[i] = (addr & (0xff << i*8)) >> i*8;
+
+	wr[0].addr  = chip ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = alen ;
+	wr[0].buf   = reg_idx ;
+
+	rd[0].addr  = chip ;
+	rd[0].flags = I2C_M_RD ;
+	rd[0].len   = len ;
+	rd[0].buf   = buffer  ;
+
+	if (alen > 0)
+		ret = i2c2_transfer(wr, 1);
+	ret = i2c2_transfer(rd, 1);
+
+	PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+
+	if (ret != 1) {
+		PRINTD("[i2c_register_read] read fail \n");
+		free(reg_idx);
+		return -1;
+	}
+
+	free(reg_idx);
+	return 0 ;
+
+}
+
+/*-----------------------------------------------------------------------
+ * Write bytes
+ */
+int i2c2_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	unsigned int length = len + alen;
+	int ret ;
+	unsigned char *buf;
+	struct i2c_msg_s wr[1];
+	unsigned int i = 0;
+	buf = calloc(length, sizeof(unsigned char *));
+
+	for (i = 0; i < length; ++i) {
+		if (i < alen)
+			*(buf + alen - i - 1) = (unsigned char) ((addr >> (i * 8)) & 0xFF);
+		else
+			*(buf + i) = *(buffer + i - alen);
+	}
+	wr[0].addr  = chip ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = length ;
+	wr[0].buf   = buf ;
+	ret = i2c2_transfer(wr, 1);
+
+	if (ret != 1) {
+		PRINTD("%d, %s, write fail with address=0x%X\n", __LINE__, __func__, address);
+		free(buf);
+		return -1;
+	}
+
+	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+	free(buf);
+
+	return 0 ;
+}
+
+/*-----------------------------------------------------------------------
+ * Read a register
+ */
+uchar i2c2_reg_read(uchar i2c_addr, uchar reg)
+{
+	uchar buf;
+
+	i2c2_read(i2c_addr, reg, 1, &buf, 1);
+
+	return buf;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a register
+ */
+void i2c2_reg_write(uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c2_write(i2c_addr, reg, 1, &val, 1);
+}
+
+
+#endif	/* CONFIG_SOFT_I2C */
diff --git a/board/wmt/wmt_i2c_3.c b/board/wmt/wmt_i2c_3.c
new file mode 100755
index 0000000..e1bd79a
--- /dev/null
+++ b/board/wmt/wmt_i2c_3.c
@@ -0,0 +1,636 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
+ * vanbaren@cideas.com.  It was heavily influenced by LiMon, written by
+ * Neil Russell.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include "include/i2c.h"
+#include "include/wmt_clk.h"
+#include <malloc.h>
+
+#if defined(CONFIG_HARD_I2C)
+
+/* #define	DEBUG_I2C	*/
+
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#define RETRIES		0
+
+
+#define I2C_ACK		0		/* PD_SDA level to ack a byte */
+#define I2C_NOACK	1		/* PD_SDA level to noack a byte */
+
+
+#ifdef DEBUG_I2C
+#define PRINTD(fmt, args...)	do {	\
+	DECLARE_GLOBAL_DATA_PTR;	\
+	if (gd->have_console)		\
+		printf(fmt , ##args);	\
+	} while (0)
+#else
+#define PRINTD(fmt, args...)
+#endif
+
+static struct i2c_s i2c ;
+static int retry_time = 3;
+
+/*-----------------------------------------------------------------------
+ * Local functions
+ */
+
+static int i2c_do_xfer(struct i2c_msg_s msgs[], int num);
+
+#if 0
+static int write_byte(uchar byte);
+#endif
+
+static int i2c_read_msg(unsigned short slave_addr, unsigned char *buf,
+			unsigned short length, int restart, int last);
+static int i2c_write_msg(unsigned short slave_addr, unsigned char *buf,
+			unsigned short length, int restart, int last);
+#if 0
+static uchar read_byte(int);
+#endif
+
+static enum i2c_mode_s i2c_xfer_mode = I2C_STANDARD_MODE;
+
+extern int auto_pll_divisor(enum dev_id dev, enum clk_cmd cmd, int unit, int freq);
+extern int wmt_delayus(int us);
+
+#define GPIO_CTRL_I2C (*(volatile char *)0xD8110057)
+#define GPIO_PAD_EN_I2C (*(volatile char *)0xD8110497)
+#define GPIO_PAD_PU_I2C (*(volatile char *)0xD81104D7)
+
+/* [Rx00] GPIO Enable Control Register for I2C */
+#define GPIO_I2C3_SDA	0x00000002
+#define GPIO_I2C3_SCL	0x00000001
+/* [Rx600] GPIO Pull up/down  Control Register for I2C */
+#define GPIO_I2C3_SCL_PULL_EN 0x00000001
+#define GPIO_I2C3_SDA_PULL_EN 0x00000002
+#define GPIO_I2C3_SCL_PULL_UP 0x00000001
+#define GPIO_I2C3_SDA_PULL_UP 0x00000002
+
+static int i2c_wait_bus_not_busy(void)
+{
+	unsigned int timeout = 30000 ;
+
+	while (1) {
+		if ((i2c.regs->IICSR & I2C_STATUS_MASK) == I2C_READY)
+			break ;
+		--timeout ;
+		if (timeout == 0)
+			break ;
+	}
+	if (timeout == 0) {
+		PRINTD("i2c_err : wait ready timeout error\n\r") ;
+		return -1 ;
+	}
+	return  0 ;
+}
+
+
+#if 0
+/*-----------------------------------------------------------------------
+ * Send 8 bits and look for an acknowledgement.
+ */
+static int write_byte(uchar data)
+{
+	unsigned int length = 1;
+	int ret ;
+	unsigned char *buf[1];
+	struct i2c_msg_s wr[1];
+
+	*buf = 0x00;
+
+	wr[0].addr  = data ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = length ;
+	wr[0].buf   = (unsigned char *)buf ;
+	ret = i2c_transfer(wr, 1);
+
+	if (ret != 1) {
+		PRINTD("%d, %s, write fail with address=0x%X\n", __LINE__, __func__, address);
+		free(buf);
+		return -1;
+	}
+
+	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+	free(buf);
+
+	return 0 ;
+}
+
+
+/*-----------------------------------------------------------------------
+ * if ack == I2C_ACK, ACK the byte so can continue reading, else
+ * send I2C_NOACK to end the read.
+ */
+static uchar read_byte(int ack)
+{
+	return 1;
+}
+#endif
+
+/*=====================================================================*/
+/*                         Public Functions                            */
+/*=====================================================================*/
+
+/*-----------------------------------------------------------------------
+ * Initialization
+ */
+void i2c3_init(int speed, int slaveaddr)
+{
+	unsigned short tmp ;
+
+	auto_pll_divisor(DEV_I2C3, CLK_ENABLE, 0, 0);
+	auto_pll_divisor(DEV_I2C3, SET_DIV, 2, 20);
+	/**/
+	/* software initial*/
+	i2c.regs = (struct I2C_REG *)BA_I2C3;
+	i2c.irq_no      = 15;
+	/*set i2c master transfer mode*/
+	if (i2c_xfer_mode == I2C_STANDARD_MODE)
+		i2c.i2c_mode    = I2C_STANDARD_MODE ;
+	else if (i2c_xfer_mode == I2C_FAST_MODE)
+		i2c.i2c_mode    = I2C_FAST_MODE ;
+	else if (i2c_xfer_mode == I2C_HS_MODE)
+		i2c.i2c_mode    = I2C_HS_MODE ;
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+	/* Set I2C/GPIO pinmux to IIC funciton*/
+	/* Set bit[0-3] to zero*/
+	GPIO_CTRL_I2C &= ~(GPIO_I2C3_SCL | GPIO_I2C3_SDA);
+	GPIO_PAD_EN_I2C |= (GPIO_I2C3_SCL_PULL_EN |
+			GPIO_I2C3_SDA_PULL_EN);
+	GPIO_PAD_PU_I2C |= (GPIO_I2C3_SCL_PULL_UP |
+			GPIO_I2C3_SDA_PULL_UP);
+
+	/* Ensure I2C clock is enabled*/
+	/*set i2c master register */
+	i2c.regs->IICCR = 0;
+	i2c.regs->IICDIV = 12;		/* 12MHz input clk directly*/
+	i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
+	i2c.regs->IICIMR = I2C_IMR_ALL_ENABLE;
+	i2c.regs->IICCR = I2C_CR_ENABLE;
+	tmp = i2c.regs->IICSR;		/* Read clear "received ACK bit"*/
+	i2c.regs->IICISR = I2C_ISR_ALL_WRITE_CLEAR;
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		i2c.regs->IICTR = I2C_TR_STD_VALUE ;   /* 0x8064*/
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		i2c.regs->IICTR = I2C_TR_FAST_VALUE ; /* 0x8019*/
+
+	return ;
+}
+
+/*===========================================================================*/
+/*  i2c_transfer*/
+/**/
+/*  return:*/
+/*===========================================================================*/
+int i2c3_transfer(struct i2c_msg_s msgs[], int num)
+{
+	int ret ;
+	int retries ;
+	int i;
+	int delay = 1000;
+
+	retries = retry_time ;
+	for (i = retries ;  i > 0; i--) {
+		ret = i2c_do_xfer(msgs, num);
+		if (ret > 0)
+			return ret ;
+
+		PRINTD("%s:i2c_test: retrying transmission\n\r", __func__);
+		delay = 1000;
+		while (delay == 0)
+			delay--;
+	}
+	wmt_delayus(100) ;
+
+	PRINTD("i2c_err : retried %i times\n\r", retries);
+	return -1 ;
+
+}
+
+static int i2c_do_xfer(struct i2c_msg_s msgs[], int num)
+{
+	struct i2c_msg_s *pmsg = NULL;
+	int i;
+	int ret = 0 ;
+
+	ret = i2c_wait_bus_not_busy();
+	if (ret < 0)
+		return ret ;
+
+	for (i = 0; ret >= 0 && i < num; i++) {
+		int last = ((i + 1) == num);
+		int restart = (i != 0) ;
+		pmsg = &msgs[i];
+
+		if (pmsg->flags & I2C_M_RD) /* READ*/
+			ret = i2c_read_msg(pmsg->addr, pmsg->buf, pmsg->len, restart, last);
+		else /* Write*/
+			ret = i2c_write_msg(pmsg->addr, pmsg->buf, pmsg->len, restart, last);
+	}
+
+	if (ret < 0)
+		return ret;
+	else
+		return i;
+}
+/*-----------------------------------------------------------------------
+ * Probe to see if a chip is present.  Also good for checking for the
+ * completion of EEPROM writes since the chip stops responding until
+ * the write completes (typically 10mSec).
+ */
+int i2c3_probe(uchar addr)
+{
+	int rc;
+
+	/* perform 1 byte read transaction */
+	/*
+	rc = write_byte(addr);
+	*/
+	rc = 1;
+
+	return rc ? 1 : 0;
+}
+
+/*===========================================================================*/
+/*  i2c_irq_handler*/
+/**/
+/*  return: NULL*/
+/*===========================================================================*/
+static void i2c_irq_handler(void)
+{
+	unsigned short isr_status ;
+
+	isr_status = i2c.regs->IICISR ;
+
+	if (isr_status & I2C_ISR_NACK_ADDR) {
+		unsigned short tmp ;
+		i2c.regs->IICISR = I2C_ISR_NACK_ADDR_WRITE_CLEAR ;
+		tmp = i2c.regs->IICSR ;  /* read clear*/
+		i2c.isr_nack = 1 ;
+		return ;
+	}
+
+	if (isr_status & I2C_ISR_BYTE_END) {
+		i2c.regs->IICISR = I2C_ISR_BYTE_END_WRITE_CLEAR ;
+		i2c.isr_byte_end = 1 ;
+		return ;
+	}
+
+	if (isr_status & I2C_ISR_SCL_TIME_OUT) {
+		i2c.regs->IICISR = I2C_ISR_SCL_TIME_OUT_WRITE_CLEAR ;
+		i2c.isr_timeout = 1 ;
+		return ;
+	} else {
+		PRINTD("i2c_err : unknown I2C ISR Handle 0x%4.4X" , isr_status) ;
+		return ;
+	}
+}
+
+/*
+ * i2c_write_msg
+ * return: 0 success
+ *         -1 fail
+ */
+static int i2c_write_msg(unsigned short slave_addr,
+			unsigned char *buf,
+			unsigned short length,
+			int restart,
+			int last)
+{
+	unsigned short tcr_value ;
+	unsigned int xfer_length ;
+	unsigned int timeout ;
+	if (length == 0)
+		return -1 ;
+	xfer_length = 0 ; /* for array index and also for checking counting*/
+
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+
+	i2c.regs->IICDR = (unsigned short)(buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK)  ;
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else {
+		tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_WRITE |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+		i2c.regs->IICDIV = HS_MASTER_CODE;
+	}
+
+	/* SET TRANSFER MODE*/
+	i2c.regs->IICTCR = tcr_value ;
+
+	/*repeat start case*/
+	if (restart == 1)
+		i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+
+	while (1) {
+		timeout = 500000 ;
+		while (1) {
+			i2c_irq_handler();
+			if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
+				break ;
+			--timeout ;
+			if (timeout == 0)
+				break ;
+		}
+		/* fail case*/
+		if (timeout == 0) {
+			PRINTD("[%s]i2c_err : wrire software timeout error (tx)\n\r", __func__) ;
+			return -1 ;
+		}
+		if (i2c.isr_nack == 1) {
+			PRINTD("i2c_err : write NACK error (tx) \n\r") ;
+			return -1 ;
+		}
+		if (i2c.isr_timeout == 1) {
+			PRINTD("%s:i2c_err : write SCL timeout error (tx)\n\r", __func__) ;
+			return -1 ;
+		}
+
+		/* pass case*/
+		if (i2c.isr_byte_end == 1)
+			++xfer_length ;
+		i2c.isr_nack    = 0 ;
+		i2c.isr_byte_end = 0 ;
+		i2c.isr_timeout = 0 ;
+
+		if ((i2c.regs->IICSR & I2C_CSR_RCV_ACK_MASK) == I2C_CSR_RCV_NOT_ACK) {
+			PRINTD("i2c_err : write RCV NACK error\n\r") ;
+			return -1 ;
+		}
+
+
+		if (length > xfer_length) {
+			i2c.regs->IICDR = (unsigned short) (buf[xfer_length] & I2C_CDR_DATA_WRITE_MASK) ;
+			i2c.regs->IICCR = (I2C_CR_CPU_RDY | I2C_CR_ENABLE) ;
+		} else if (length == xfer_length) { /* end tx xfer*/
+			if (last == 1) {  /* stop case*/
+				//i2c.regs->IICCR = (I2C_CR_TX_END|I2C_CR_CPU_RDY|I2C_CR_ENABLE) ;
+				wmt_delayus(2);/*2 us*/
+				i2c.regs->IICCR |= (I2C_CR_TX_END) ;
+				break ;
+			} else {  /* restart case*/
+				/* handle the restart for first write then the next is read*/
+				i2c.regs->IICCR = (I2C_CR_ENABLE) ;
+				break ;
+			}
+		} else {
+			PRINTD("i2c_err : write unknown error\n\r") ;
+			return -1 ;
+		}
+	}
+	i2c.regs->IICCR &= ~(I2C_CR_TX_END|I2C_CR_CPU_RDY) ;
+	return 0 ;
+}
+
+/*
+ * i2c_read_msg
+ * return: 0 success
+ *         -1 fail
+ */
+static int i2c_read_msg(unsigned short slave_addr,
+			unsigned char *buf,
+			unsigned short length,
+			int restart,
+			int last)
+{
+	unsigned short tcr_value ;
+	unsigned int xfer_length ;
+	unsigned int timeout ;
+
+	if (length == 0)
+		return -1 ;
+	xfer_length = 0 ;
+
+	i2c.isr_nack    = 0 ;
+	i2c.isr_byte_end = 0 ;
+	i2c.isr_timeout = 0 ;
+
+	if (i2c.i2c_mode == I2C_STANDARD_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_STANDARD_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else if (i2c.i2c_mode == I2C_FAST_MODE)
+		tcr_value = (unsigned short)(I2C_TCR_FAST_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+	else
+		tcr_value = (unsigned short)(I2C_TCR_HS_MODE|I2C_TCR_MASTER_READ |\
+					  (slave_addr & I2C_TCR_SLAVE_ADDR_MASK)) ;
+
+	i2c.regs->IICTCR = tcr_value;
+
+	/*repeat start case*/
+	if (restart == 1)
+		i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+
+	if (length == 1)
+		i2c.regs->IICCR |= I2C_CR_TX_NEXT_NO_ACK; /*only 8-bit to read*/
+
+	while (1) {
+		timeout = 500000 ;
+		while (1) {
+			i2c_irq_handler();
+			if ((i2c.isr_nack == 1) || (i2c.isr_byte_end == 1) || (i2c.isr_timeout == 1))
+				break ;
+			--timeout ;
+			if (timeout == 0)
+				break ;
+		}
+		/* fail case*/
+		if (i2c.isr_nack == 1) {
+			PRINTD("i2c_err : write NACK error (rx) \n\r") ;
+			return -1 ;
+		}
+		if (i2c.isr_timeout == 1) {
+			PRINTD("%s, i2c_err : write SCL timeout error (rx)\n\r", __func__) ;
+			return -1 ;
+		}
+		if (timeout == 0) {
+			PRINTD("[%s]i2c_err: write software timeout error (rx) \n\r", __func__) ;
+			return -1 ;
+		}
+		/* pass case*/
+		if (i2c.isr_byte_end == 1) {
+			buf[xfer_length] = (i2c.regs->IICDR >> 8) ;
+			++xfer_length ;
+		}
+		i2c.isr_nack    = 0 ;
+		i2c.isr_byte_end = 0 ;
+		i2c.isr_timeout = 0 ;
+
+		if (length > xfer_length) {
+			if ((length - 1) ==  xfer_length) /* next read is the last one*/
+				i2c.regs->IICCR |= (I2C_CR_TX_NEXT_NO_ACK | I2C_CR_CPU_RDY);
+			else
+				i2c.regs->IICCR |= I2C_CR_CPU_RDY ;
+		} else if (length == xfer_length) { /* end rx xfer*/
+			if (last == 1)  /* stop case*/
+				break ;
+			else  /* restart case*/
+				/* ??? how to handle the restart after read ?*/
+				break ;
+		} else {
+			PRINTD("i2c_err : read known error\n\r") ;
+			return -1 ;
+		}
+	}
+	PRINTD("i2c_test: read sequence completed\n\r");
+	i2c.regs->IICCR &= ~(I2C_CR_TX_NEXT_NO_ACK | I2C_CR_CPU_RDY);
+	return 0 ;
+}
+
+/*-----------------------------------------------------------------------
+ * Read bytes
+ */
+int i2c3_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int ret;
+	unsigned char *reg_idx;
+	struct i2c_msg_s wr[1] ;
+	struct i2c_msg_s rd[1] ;
+	int i = 0;
+
+	reg_idx = calloc(alen, sizeof(unsigned char *));
+	for (i = 0; i < alen; ++i)
+		reg_idx[i] = (addr & (0xff << i*8)) >> i*8;
+
+	wr[0].addr  = chip ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = alen ;
+	wr[0].buf   = reg_idx ;
+
+	rd[0].addr  = chip ;
+	rd[0].flags = I2C_M_RD ;
+	rd[0].len   = len ;
+	rd[0].buf   = buffer  ;
+
+	if (alen > 0)
+		ret = i2c3_transfer(wr, 1);
+	ret = i2c3_transfer(rd, 1);
+
+	PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+
+	if (ret != 1) {
+		PRINTD("[i2c_register_read] read fail \n");
+		free(reg_idx);
+		return -1;
+	}
+
+	free(reg_idx);
+	return 0 ;
+
+}
+
+/*-----------------------------------------------------------------------
+ * Write bytes
+ */
+int i2c3_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	unsigned int length = len + alen;
+	int ret ;
+	unsigned char *buf;
+	struct i2c_msg_s wr[1];
+	unsigned int i = 0;
+	buf = calloc(length, sizeof(unsigned char *));
+
+	for (i = 0; i < length; ++i) {
+		if (i < alen)
+			*(buf + alen - i - 1) = (unsigned char) ((addr >> (i * 8)) & 0xFF);
+		else
+			*(buf + i) = *(buffer + i - alen);
+	}
+	wr[0].addr  = chip ;
+	wr[0].flags = I2C_M_WR ;
+	wr[0].len   = length ;
+	wr[0].buf   = buf ;
+	ret = i2c3_transfer(wr, 1);
+
+	if (ret != 1) {
+		PRINTD("%d, %s, write fail with address=0x%X\n", __LINE__, __func__, address);
+		free(buf);
+		return -1;
+	}
+
+	PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
+		chip, addr, alen, buffer, len);
+	free(buf);
+
+	return 0 ;
+}
+
+/*-----------------------------------------------------------------------
+ * Read a register
+ */
+uchar i2c3_reg_read(uchar i2c_addr, uchar reg)
+{
+	uchar buf;
+
+	i2c3_read(i2c_addr, reg, 1, &buf, 1);
+
+	return buf;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a register
+ */
+void i2c3_reg_write(uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c3_write(i2c_addr, reg, 1, &val, 1);
+}
+
+
+#endif	/* CONFIG_SOFT_I2C */
diff --git a/board/wmt/wmt_ost.c b/board/wmt/wmt_ost.c
new file mode 100755
index 0000000..c670947
--- /dev/null
+++ b/board/wmt/wmt_ost.c
@@ -0,0 +1,117 @@
+/*++ 
+Copyright (c) 2012 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+4F, 531, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#include <common.h>
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+typedef struct
+{
+	volatile unsigned long	ostm[4];				// [Rx100-Rx10C] OS Timer Match Register0-3
+	volatile unsigned long	ostct;					// [Rx110-113] OS Timer Counter Register
+	volatile unsigned long	osts;					// [Rx114-117] OS Timer Status Register
+	volatile unsigned long	ostwe;					// [Rx118-Rx11B]
+	volatile unsigned long	ostie;					// [Rx11C-Rx11F]
+	volatile unsigned long	ostctrl;				// [Rx120-Rx123] OS Timer Control Register
+	volatile unsigned long	ostas;					// [Rx124-Rx127] OS Timer Access Status Register
+} WMT_OST_REG;
+
+static WMT_OST_REG *pWMTOST;
+
+static int wmt_write_ostc_rdy(void)
+{
+	unsigned int sw_counter = 30000;
+	
+	while( pWMTOST->ostas & 0x10 ) {
+		if ( --sw_counter == 0 ) {
+			printf("Count Write Active Busy\n");
+			return -1;
+		}
+	}
+	return 0;
+}
+
+int wmt_init_ostimer(void)
+{
+	//printf("wmt_init_ostimer\n");
+
+	if (pWMTOST == NULL)
+		pWMTOST = (WMT_OST_REG *)0xd8130100;
+
+	if (pWMTOST->ostctrl&0x01)
+		return 0;
+
+	pWMTOST->ostctrl = 0;
+	pWMTOST->ostwe = 0;
+	
+	if (wmt_write_ostc_rdy())
+		return -1;
+
+	pWMTOST->ostct = 0;
+
+	pWMTOST->ostctrl = 1;
+	
+	return 0;
+}
+
+int wmt_read_oscr(unsigned int *val)
+{
+	unsigned int sw_counter = 300000;
+
+	if (pWMTOST == NULL) {
+		if (wmt_init_ostimer())
+			return -1;
+	}
+
+	if ( (pWMTOST->ostctrl & 0x02 ) == 0 )
+		pWMTOST->ostctrl |= 0x02;
+
+	/* Check OS Timer Count Value is Valid*/
+	while ((pWMTOST->ostas & 0x20) == 0x20) {
+		if ( --sw_counter == 0 ) { /* Need to be considered*/
+			printf("Read Count Request Fail\n");
+			break;
+		}
+	}
+	*val = (int)pWMTOST->ostct;
+	return 0;
+}
+
+int wmt_idle_us(int us)
+{
+	int count = 100;
+	unsigned int before,after;
+
+	us = us*3;	
+
+	if (wmt_read_oscr(&before))
+		return -1;
+	while (1) {
+		while(--count);
+		if (wmt_read_oscr(&after))
+			return -1;
+		if ((int)(after - before) >= us) {
+			//printf("request = %d , result = %d\n",us,(after - before));
+			break;
+		}
+		count = 100;
+	}
+	return 0;
+}
+
diff --git a/board/wmt/wmt_spi_0.c b/board/wmt/wmt_spi_0.c
new file mode 100755
index 0000000..6d6940b
--- /dev/null
+++ b/board/wmt/wmt_spi_0.c
@@ -0,0 +1,491 @@
+/*++
+Copyright (c) 2012 WonderMedia Technologies, Inc. All Rights Reserved.
+
+This PROPRIETARY SOFTWARE is the property of WonderMedia Technologies, Inc.
+and may contain trade secrets and/or other confidential information of
+WonderMedia Technologies, Inc. This file shall not be disclosed to any third
+party, in whole or in part, without prior written consent of WonderMedia.
+
+THIS PROPRIETARY SOFTWARE AND ANY RELATED DOCUMENTATION ARE PROVIDED AS IS,
+WITH ALL FAULTS, AND WITHOUT WARRANTY OF ANY KIND EITHER EXPRESS OR IMPLIED,
+AND WonderMedia TECHNOLOGIES, INC. DISCLAIMS ALL EXPRESS OR IMPLIED WARRANTIES
+OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR
+NON-INFRINGEMENT.
+--*/
+
+/*  [Description]*/
+/*    1st function will be called by post core. */
+/*    In this funciton, it will initialize the H/W and Data Structure.*/
+/*  [Arguments]*/
+/*    NONE*/
+
+#include <common.h>
+#include <spi.h>
+#include "include/common_def.h"
+#include "include/wmt_spi.h"
+#include "include/wmt_clk.h"
+#include <malloc.h>
+
+#define CTRL_GP12_SPI_byte (*(volatile char *)0xD811004C)
+#define PULL_EN_GP12_SPI_byte (*(volatile char *)0xD811048C)
+#define PULL_CTRL_GP12_SPI_byte (*(volatile char *)0xD81104CC)
+
+#define PIN_SHARING_SEL_4byte (*(volatile unsigned long *)0xD8110200)
+#define CTRL_GP18_SPI1_byte (*(volatile char *)0xD8110052)
+#define PULL_EN_GP18_SPI1_byte (*(volatile char *)0xD8110492)
+#define PULL_CTRL_GP18_SPI1_byte (*(volatile char *)0xD81104d2)
+
+static unsigned int spi_freq = 2000;
+static unsigned int spi_pllb = 0;
+extern int auto_pll_divisor(enum dev_id dev, enum clk_cmd cmd, int unit, int freq);
+
+static struct spi_info_s SPI_INFO[SPI_PORT_NUM];
+static struct spi_info_s *SPI_PORT[SPI_PORT_NUM];
+
+int spi_init_clock(void)
+{
+        auto_pll_divisor(DEV_SPI0, CLK_ENABLE, 0, 0);
+        spi_pllb = auto_pll_divisor(DEV_SPI0, SET_DIV, 2, 100)/1000;/*enable spi0 clock*/
+        auto_pll_divisor(DEV_SPI1, CLK_ENABLE, 0, 0);
+        spi_pllb = auto_pll_divisor(DEV_SPI1, SET_DIV, 2, 100)/1000;/*enable spi0 clock*/
+        return 0;
+}
+
+void spi_init(void)
+{
+	int port;
+
+	spi_init_clock();
+	memset(&SPI_INFO[0], 0x0, sizeof(SPI_INFO));
+	//memset(&SPI_INFO[0], 0x0, sizeof(struct spi_info_s));
+	//memset(&SPI_INFO[1], 0x0, sizeof(struct spi_info_s));
+
+	/*set gpio*/
+	/*spi 0*/
+	CTRL_GP12_SPI_byte &= ~(GPIO_SPI0_CLK |
+					GPIO_SPI0_MOSI|
+					GPIO_SPI0_SS|
+					GPIO_SPI0_MISO );
+
+	PULL_EN_GP12_SPI_byte |= (GPIO_SPI0_CLK_PULL_EN |
+					GPIO_SPI0_SS_PULL_EN |
+					GPIO_SPI0_MOSI_PULL_EN |
+					GPIO_SPI0_MISO_PULL_EN);
+
+	/*mosi,miso,ssn*/
+	PULL_CTRL_GP12_SPI_byte |= (BIT3 | BIT2 | BIT1);
+	/*clk*/
+	PULL_CTRL_GP12_SPI_byte &= ~(BIT0);
+
+	// spi1
+	PIN_SHARING_SEL_4byte |= BIT10;
+	CTRL_GP18_SPI1_byte &= ~(BIT7 | BIT6 | BIT3 | BIT2);
+	PULL_EN_GP18_SPI1_byte |= (BIT7 | BIT6 | BIT3 | BIT2);
+	// ss0, mosi, miso
+	PULL_CTRL_GP18_SPI1_byte |= (BIT7 | BIT3 | BIT2);
+	// clk
+	PULL_CTRL_GP18_SPI1_byte &= (BIT6);
+
+#if 0
+	/*spi0 ss2 ss3*/
+	pGpio_Reg->CTRL_GP31_byte &= ~(GPIO_C24MHZCLKI |
+					GPIO_C25MHZCLKI);
+	pGpio_Reg->PULL_EN_GP31_byte |= (GPIO_C24MHZCLKI_PULL_EN |
+					GPIO_C25MHZCLKI_PULL_EN);
+	pGpio_Reg->PULL_CTRL_GP31_byte |= (BIT2 | BIT1);
+
+	/*spi0 ss1*/	
+	/*turn off GPIO 10*/
+	pGpio_Reg->CTRL_GP1_byte &= ~(BIT2);
+	pGpio_Reg->PULL_EN_GP1_byte |= BIT2;
+	pGpio_Reg->PULL_CTRL_GP1_byte |= BIT2;
+
+	/*set to SPI0SS1 and SPI0SS3*/
+	pGpio_Reg->PIN_SHARING_SEL_4byte &= ~(BIT5 | BIT4);
+	/*set to SPI0SS2*/
+	pGpio_Reg->PIN_SHARING_SEL_4byte |= BIT12;
+#endif
+
+	/* Reset SPI*/
+	for (port = 0; port < SPI_PORT_NUM; port++) {
+		*(SPI_INFO[port].regs.cr) = (SPI_CR_RESET_MASK | SPI_CR_RFR_MASK | SPI_CR_TFR_MASK);
+		/* *sr = 0x0;*/
+		*(SPI_INFO[port].regs.sr) |= 0x00007F10;
+		/* *dfcr = SPI_DFCR_RESET_MASK;*/
+		*(SPI_INFO[port].regs.dfcr) = SPI_DFCR_RESET_MASK;
+		/* Reset SPI Property*/
+		spi_info_reset(port);
+	}
+}
+
+/*  [Description]*/
+/*    SPI property Reset.*/
+/*  [Arguments]*/
+/*    Port Number*/
+void spi_info_reset(int port)
+{
+	if (port == 0) {
+		SPI_INFO[0].regs.cr = (unsigned int volatile *)(SPI_REG_BASE + SPICR) ;
+		SPI_INFO[0].regs.sr = (unsigned int volatile *)(SPI_REG_BASE + SPISR);
+		SPI_INFO[0].regs.dfcr = (unsigned int volatile *)(SPI_REG_BASE + SPIDFCR);
+		SPI_INFO[0].regs.cre = (unsigned int volatile *)(SPI_REG_BASE + SPICRE);
+		SPI_INFO[0].regs.rfifo = (unsigned char volatile *)(SPI_REG_BASE + SPIRXFIFO);
+		SPI_INFO[0].regs.wfifo = (unsigned char volatile *)(SPI_REG_BASE + SPITXFIFO);
+		SPI_INFO[0].regs.srcv_cnt= (unsigned int volatile *)(SPI_REG_BASE + SPISRCV_CNT);
+		SPI_INFO[0].regs.srcv_add_cnt= (unsigned int volatile *)(SPI_REG_BASE + SPISRCV_Add_CNT);
+	} else if (port == 1) {
+		SPI_INFO[1].regs.cr = (unsigned int volatile *)(SPI_REG_BASE1 + SPICR) ;
+		SPI_INFO[1].regs.sr = (unsigned int volatile *)(SPI_REG_BASE1 + SPISR );
+		SPI_INFO[1].regs.dfcr = (unsigned int volatile *)(SPI_REG_BASE1 + SPIDFCR );
+		SPI_INFO[1].regs.cre = (unsigned int volatile *)(SPI_REG_BASE1 + SPICRE);
+		SPI_INFO[1].regs.rfifo = (unsigned char volatile *)(SPI_REG_BASE1 + SPIRXFIFO);
+		SPI_INFO[1].regs.wfifo = (unsigned char volatile *)(SPI_REG_BASE1 + SPITXFIFO);
+		SPI_INFO[1].regs.srcv_cnt= (unsigned int volatile *)(SPI_REG_BASE1 + SPISRCV_CNT);
+		SPI_INFO[1].regs.srcv_add_cnt= (unsigned int volatile *)(SPI_REG_BASE1 + SPISRCV_Add_CNT);
+	}
+
+	/* Setting default frequence is 1Mhz*/
+	SPI_INFO[port].freq = spi_freq; /*20000;*/
+	/* SSN Port Mode = Point to point*/
+	SPI_INFO[port].ssn_port_mode = 1;
+	/* Setting TX Drive Output Value = 0xFF*/
+	SPI_INFO[port].tx_nodata_value = 1;
+	/* SPI_INFO[port].slave_select = 1;*/
+}
+
+/*  [Description]*/
+/*    Get SPI Information.*/
+/*  [Arguments]*/
+/*    Port Number*/
+struct spi_info_s* spi_get_info(int port)
+{
+	if (port >= SPI_PORT_NUM)  /* error port number*/
+		return NULL;
+	else
+		return &SPI_INFO[port];
+}
+
+/*  [Description]*/
+/*    Map SPI Information to register setting.*/
+/*  [Arguments]*/
+/*    Port Number*/
+
+void spi_set_reg(int port)
+{
+	unsigned int  cr,sr,dfcr,cre;
+	unsigned int control = 0x0;
+	/* SSn Default is pull high,*/
+	/* otherwise it is control by program if ssn control is enable*/
+	unsigned int dataformat = SPI_DFCR_RESET_MASK;
+	unsigned int add_recv_cnt = 0;
+	unsigned int divisor = 0x0;
+	unsigned char not_sync = 0x0;
+
+
+	if (port >= SPI_PORT_MAX)  /* error port number*/
+	  return;
+
+	/*Reset Hardware*/
+	*(SPI_INFO[port].regs.cr) = SPI_CR_RESET_MASK |
+		SPI_CR_RFR_MASK |
+		SPI_CR_TFR_MASK;
+	*(SPI_INFO[port].regs.dfcr) = dataformat;
+	sr = *(SPI_INFO[port].regs.sr);
+	*(SPI_INFO[port].regs.sr) = sr;
+	*(SPI_INFO[port].regs.sr) = 0x0;
+
+	/* Set Frequence*/
+	if (SPI_INFO[port].freq != 0)
+		divisor = spi_pllb / (SPI_INFO[port].freq * 2);
+	else
+		divisor = 0;
+	control |= ((divisor << SPI_CR_TCD_SHIFT) & SPI_CR_TCD_MASK);
+
+	/* Setting output ssn signal*/
+	control |= ((SPI_INFO[port].slave_select << SPI_CR_SS_SHIFT) & SPI_CR_SS_MASK);
+
+	if (SPI_INFO[port].op_mode == SPI_DMA_MODE) {
+		/*
+		DMA Setting
+		Enable Threshold Requst.
+		Transfer/Receive Threshold is set to 8 bytes.
+		(DMA burst size must less than 8 bytes)
+		*/
+		control |= SPI_CR_DRC_MASK/*|SPI_CR_TFTS_MASK|SPI_CR_RFTS_MASK*/;
+		if (SPI_INFO[port].arbiter == SPI_BUS_MASTER)
+			control |= SPI_CR_TFTS_MASK;
+		else
+			control |= SPI_CR_RFTS_MASK;
+			/*control &= ~(SPI_CR_RFTS_MASK);*/
+
+		/* Setting TX: Under-run, Empty Interrupt request*/
+		/*  control |= SPI_CR_TFUI_MASK|SPI_CR_TFEI_MASK;*/
+		/* Setting RX: Over-run, Full, Empty Interrupt request*/
+		/*    control |= SPI_CR_RFOI_MASK|SPI_CR_RFFI_MASK|SPI_CR_RFEI_MASK;*/
+		/* Enable IRQ*/
+		/*    control |= SPI_CR_IE_MASK;*/
+	} else if (SPI_INFO[port].op_mode == SPI_IRQ_MODE) {
+		/* Interrupt Setting*/
+		/* Pass Threshold Requst to SPI interrupt.*/
+		/* Transfer/Receive Threshold is set to 8 bytes.*/
+		/*   control |= SPI_CR_TIDS_MASK; //jakie*/
+		if (SPI_INFO[port].arbiter == SPI_BUS_MASTER)
+			control |= SPI_CR_TFEI_MASK | SPI_CR_RFFI_MASK;
+		else
+			control |= SPI_CR_RFFI_MASK;
+	}
+
+	/* Setting master and slave control*/
+	if (SPI_INFO[port].arbiter == SPI_BUS_SLAVE) {
+		/* Slave Mode*/
+		control |= SPI_CR_MSMS_MASK;
+		add_recv_cnt = SPI_INFO[port].rx_cnt;
+
+		/* If work in slave mode, ssn can't be controled and port can't be Multi-Master*/
+		if ((SPI_INFO[port].ssn_control == 1) ||
+			(SPI_INFO[port].ssn_port_mode == 0))
+			not_sync = 1;
+		/* Check this, Should it set to Point to Point Mode a*/
+		/*nd should ssn be set to auto control by hardware*/
+		SPI_INFO[port].ssn_control = 0;
+		SPI_INFO[port].ssn_port_mode = 1;
+		dataformat |= SPI_DFCR_SPM_MASK;
+	}
+
+
+	/* Set Clock Mode*/
+	if ((SPI_INFO[port].clk_mode == SPI_MODE_2) ||
+		(SPI_INFO[port].clk_mode == SPI_MODE_3))
+		control |= SPI_CR_CPS_MASK;
+	if ((SPI_INFO[port].clk_mode == SPI_MODE_1) ||
+		(SPI_INFO[port].clk_mode == SPI_MODE_3))
+		control |= SPI_CR_CPHS_MASK;
+
+	/* Use for output setting value when FIFO goes empty*/
+	/* If enable TX driver Feature, Setting related register.*/
+	/* else don't care*/
+	if (SPI_INFO[port].tx_drive_enable) {
+		dataformat |= SPI_DFCR_TDE_MASK;
+		/* Setting Driver Value 0xFF*/
+		dataformat |= ((SPI_INFO[port].tx_nodata_value << SPI_DFCR_TNDV_SHIFT) & SPI_DFCR_TNDV_MASK);
+		/* Setting Driver Connt*/
+		//dataformat |= ((SPI_INFO[port].tx_drive_count << SPI_DFCR_TDCNT_SHIFT) & SPI_DFCR_TDCNT_MASK);
+		add_recv_cnt = SPI_INFO[port].tx_cnt;
+	}
+
+	/* Use for SSN Control correlated with slave_select*/
+	/* If enable SSN Control, Setting related register.*/
+	/* else pull high. (Defult setting)*/
+	if (SPI_INFO[port].ssn_control) {
+		/*  printf("*[SPI]*,P-%d Set SSn Control.\n",port);*/
+		dataformat |= SPI_DFCR_SC_MASK;
+		/* Setting SSN Pull High*/
+		dataformat |= SPI_DFCR_DSV_MASK | SPI_DFCR_DSE_MASK;
+	}
+
+	if (SPI_INFO[port].ssn_port_mode == 0)
+		/* Multi-Master Mode*/
+		/* Enable Passed Mode Fault Error Interrupt request if interrupt is enabled*/
+		control |= SPI_CR_MFEI_MASK | SPI_CR_MFEF_MASK;
+	else
+		/* otherwise, Point-to-Point mode*/
+		dataformat |= SPI_DFCR_SPM_MASK;
+
+	cr = *(SPI_INFO[port].regs.cr);
+	sr = *(SPI_INFO[port].regs.sr);
+	dfcr = *(SPI_INFO[port].regs.dfcr);
+	cre = 0x20;
+	dataformat &= ~(0xF0000000);
+	dataformat |= (0x0 << 28);
+	dataformat |= BIT8 | BIT9;
+	dataformat |= BIT27; /*enable RX overrun*/
+
+	*(SPI_INFO[port].regs.dfcr) = dataformat;
+	*(SPI_INFO[port].regs.srcv_add_cnt) = add_recv_cnt;
+	*(SPI_INFO[port].regs.sr) = 0x0;
+	*(SPI_INFO[port].regs.cr) = control;
+	*(SPI_INFO[port].regs.cre) = cre;
+	*(SPI_INFO[port].regs.cr) |= SPI_CR_RFR_MASK; /* reset FIFO*/
+	while (*(SPI_INFO[port].regs.cr) & SPI_CR_RFR_MASK)
+		;
+	*(SPI_INFO[port].regs.cr) |= SPI_CR_TFR_MASK; /* reset FIFO*/
+	while (*(SPI_INFO[port].regs.cr) & SPI_CR_TFR_MASK)
+		;
+}
+
+/*  [Description]*/
+/*    Enable SPI Module.*/
+/*  [Arguments]*/
+/*    Port Number*/
+void spi_enable(int port)
+{
+	unsigned int cr = SPI_CR_ME_MASK;
+
+	if (port >= SPI_PORT_MAX)  /* error port number*/
+		return;
+
+	if (SPI_INFO[port].op_mode == SPI_IRQ_MODE ||
+		SPI_INFO[port].op_mode == SPI_DMA_MODE)
+		cr |= SPI_CR_IE_MASK;
+
+	/* Master mode and ssn controled by programming*/
+	if ((SPI_INFO[port].arbiter == SPI_BUS_MASTER) &&
+		(SPI_INFO[port].ssn_control == 1))
+		/* Pull low ssn for enable active spi*/
+		*(SPI_INFO[port].regs.dfcr) &= ~(SPI_DFCR_DSV_MASK | SPI_DFCR_DSE_MASK);
+
+	/*  printf("*[SPI]*,P-%d Module and Interrupt Enable.\n",port);*/
+	/* Module enable*/
+	*(SPI_INFO[port].regs.cr) |= cr;
+}
+
+/*  [Description]*/
+/*    Disable SPI Module.*/
+/*  [Arguments]*/
+/*    Port Number*/
+void spi_disable(int port)
+{
+	unsigned int cr = SPI_CR_ME_MASK;
+
+	if (port >= SPI_PORT_MAX)  /* error port number*/
+		return;
+
+	if (SPI_INFO[port].op_mode == SPI_IRQ_MODE ||
+		SPI_INFO[port].op_mode == SPI_DMA_MODE)
+		cr |= SPI_CR_IE_MASK;
+
+	/* Master mode and ssn controled by programming*/
+	if ((SPI_INFO[port].arbiter == SPI_BUS_MASTER) &&
+		(SPI_INFO[port].ssn_control == 1))
+		/* Pull high ssn for enable inactive spi*/
+		*(SPI_INFO[port].regs.dfcr) |= SPI_DFCR_DSV_MASK | SPI_DFCR_DSE_MASK;
+
+	/* Module disable*/
+	*(SPI_INFO[port].regs.cr) &= ~(cr);
+	/*printf("*[SPI]*,P-%d Module and Interrupt Disable.\n",port);*/
+}
+
+/*===========================================================================*/
+/*  spi_tx_polling*/
+/**/
+/*  return:*/
+/*===========================================================================*/
+int spi_tx_polling(int portNum)
+{
+	unsigned int status;
+	int timeout_cnt = 0x20000;
+	while (timeout_cnt--) {
+		status = *(SPI_INFO[portNum].regs.sr);
+		if (status & SPI_SR_TFEI_MASK)
+			return 0;
+	}
+
+	printf("spi%d timeout\n", portNum);
+	return -1;
+}
+
+void set_spi_freq(unsigned int freq)
+{
+	spi_freq = freq;
+}
+void spi_write_then_read_data(
+			unsigned char *wbuf,
+			unsigned char *rbuf,
+			int num,
+			int clk_mode,
+			int chip_sel)
+{
+	int i = 0;
+	int transmitted_count = 0;
+	int portNum = 0;
+	SPI_INFO[portNum].clk_mode = clk_mode;
+	SPI_INFO[portNum].slave_select = chip_sel;
+	SPI_INFO[portNum].tx_cnt = num;
+	spi_set_reg(portNum);
+	while (transmitted_count + 32 < num) {
+		spi_disable(portNum);
+		for (i = transmitted_count; i < 32; ++i)
+			*SPI_INFO[portNum].regs.wfifo = wbuf[i];
+		spi_enable(portNum);
+		while (spi_tx_polling(portNum))
+			;
+		for (i = transmitted_count; i <32; ++i)
+			rbuf[i] = *SPI_INFO[portNum].regs.rfifo;
+		transmitted_count += 32;
+	}
+
+	spi_disable(portNum);
+	for (i = transmitted_count; i < num; ++i)
+		*SPI_INFO[portNum].regs.wfifo = wbuf[i];
+	spi_enable(portNum);
+	while (spi_tx_polling(portNum))
+		;
+	for (i = transmitted_count; i < num; ++i)
+		rbuf[i] = *SPI_INFO[portNum].regs.rfifo;
+
+	spi_disable(portNum);
+	return;
+}
+
+void spi1_write_then_read_data(
+			unsigned char *wbuf,
+			unsigned char *rbuf,
+			int num,
+			int clk_mode,
+			int chip_sel)
+{
+	int i = 0;
+	int transmitted_count = 0;
+	int portNum = 1;
+	SPI_INFO[portNum].clk_mode = clk_mode;
+	SPI_INFO[portNum].slave_select = chip_sel;
+	SPI_INFO[portNum].tx_cnt = num;
+	spi_set_reg(portNum);
+	while (transmitted_count + 32 < num) {
+		spi_disable(portNum);
+		for (i = transmitted_count; i < 32; ++i)
+			*SPI_INFO[portNum].regs.wfifo = wbuf[i];
+		spi_enable(portNum);
+		while (spi_tx_polling(portNum))
+			;
+		for (i = transmitted_count; i <32; ++i)
+			rbuf[i] = *SPI_INFO[portNum].regs.rfifo;
+		transmitted_count += 32;
+	}
+
+	spi_disable(portNum);
+	for (i = transmitted_count; i < num; ++i)
+		*SPI_INFO[portNum].regs.wfifo = wbuf[i];
+	spi_enable(portNum);
+	while (spi_tx_polling(portNum))
+		;
+	for (i = transmitted_count; i < num; ++i)
+		rbuf[i] = *SPI_INFO[portNum].regs.rfifo;
+
+	spi_disable(portNum);
+	return;
+}
+
+#if 0
+int loopback_test(unsigned int reg)
+{
+	unsigned char addr[3];
+	unsigned char data[3];
+	//addr[0] = ((reg & 0XFF) & (~ BIT7));
+	//addr[1] = ((reg & 0XFF) >> 7);
+	addr[0] = 0xaa;
+	addr[1] = 0x39;
+	addr[2] = 0x55;
+	data[0] = 0x00;
+	data[1] = 0x00;
+	data[2] = 0x00;
+
+	spi_write_then_read_data(addr, data, 3, 0, 0);
+
+	//data[2] &=0xff;
+	printf("value 0 = %x\n", data[0]);
+	printf("value 1 = %x\n", data[1]);
+	printf("value 2 = %x\n", data[2]);
+	return data[2];
+}
+#endif
diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile
new file mode 100755
index 0000000..7c5f0cd
--- /dev/null
+++ b/board/xaeniax/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= xaeniax.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/xaeniax/config.mk b/board/xaeniax/config.mk
new file mode 100755
index 0000000..45079a0
--- /dev/null
+++ b/board/xaeniax/config.mk
@@ -0,0 +1,2 @@
+TEXT_BASE = 0xa3FB0000
+#TEXT_BASE = 0
diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c
new file mode 100755
index 0000000..9874a14
--- /dev/null
+++ b/board/xaeniax/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW    FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S
new file mode 100755
index 0000000..fe3e712
--- /dev/null
+++ b/board/xaeniax/lowlevel_init.S
@@ -0,0 +1,424 @@
+ /*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+	.macro CPWAIT reg
+	mrc  p15,0,\reg,c2,c0,0
+	mov  \reg,\reg
+	sub  pc,pc,#4
+	.endm
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	 r10, lr
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr	r0,=GPSR0
+	ldr	r1,=CFG_GPSR0_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPSR1
+	ldr	r1,=CFG_GPSR1_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPSR2
+	ldr	r1,=CFG_GPSR2_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPCR0
+	ldr	r1,=CFG_GPCR0_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPCR1
+	ldr	r1,=CFG_GPCR1_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPCR2
+	ldr	r1,=CFG_GPCR2_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPDR0
+	ldr	r1,=CFG_GPDR0_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPDR1
+	ldr	r1,=CFG_GPDR1_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GPDR2
+	ldr	r1,=CFG_GPDR2_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR0_L
+	ldr	r1,=CFG_GAFR0_L_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR0_U
+	ldr	r1,=CFG_GAFR0_U_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR1_L
+	ldr	r1,=CFG_GAFR1_L_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR1_U
+	ldr	r1,=CFG_GAFR1_U_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR2_L
+	ldr	r1,=CFG_GAFR2_L_VAL
+	str	r1,[r0]
+
+	ldr	r0,=GAFR2_U
+	ldr	r1,=CFG_GAFR2_U_VAL
+	str	r1,[r0]
+
+	ldr	r0,=PSSR		/* enable GPIO pins */
+	ldr	r1,=CFG_PSSR_VAL
+	str	r1,[r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+mem_init:
+
+	ldr	r1,=MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr     r2,=CFG_MSC0_VAL
+	str     r2,[r1, #MSC0_OFFSET]
+	ldr     r2,[r1, #MSC0_OFFSET]	/* read back to ensure data latches */
+
+	/* MSC1: nCS(2,3)                                                   */
+	ldr     r2,=CFG_MSC1_VAL
+	str     r2,[r1, #MSC1_OFFSET]
+	ldr     r2,[r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr     r2,=CFG_MSC2_VAL
+	str     r2,[r1, #MSC2_OFFSET]
+	ldr     r2,[r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr     r2,=CFG_MECR_VAL
+	str     r2,[r1, #MECR_OFFSET]
+	ldr	r2,[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr     r2,=CFG_MCMEM0_VAL
+	str     r2,[r1, #MCMEM0_OFFSET]
+	ldr	r2,[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr     r2,=CFG_MCMEM1_VAL
+	str     r2,[r1, #MCMEM1_OFFSET]
+	ldr	r2,[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr     r2,=CFG_MCATT0_VAL
+	str     r2,[r1, #MCATT0_OFFSET]
+	ldr	r2,[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr     r2,=CFG_MCATT1_VAL
+	str     r2,[r1, #MCATT1_OFFSET]
+	ldr	r2,[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr     r2,=CFG_MCIO0_VAL
+	str     r2,[r1, #MCIO0_OFFSET]
+	ldr	r2,[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr     r2,=CFG_MCIO1_VAL
+	str     r2,[r1, #MCIO1_OFFSET]
+	ldr	r2,[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	@ get the mdrefr settings
+	ldr     r4,=CFG_MDREFR_VAL
+
+	@ write back mdrefr
+	str     r4,[r1, #MDREFR_OFFSET]
+	ldr     r4,[r1, #MDREFR_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	@ set K1RUN for bank 0
+	@
+	orr   r4,  r4,  #MDREFR_K1RUN
+
+	@ write back mdrefr
+	@
+	str     r4,  [r1, #MDREFR_OFFSET]
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+	@ deassert SLFRSH
+	@
+	bic     r4,  r4,  #MDREFR_SLFRSH
+
+	@ write back mdrefr
+	@
+	str     r4,  [r1, #MDREFR_OFFSET]
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+
+	@ assert E1PIN
+	@ if E0PIN is also used:	 #(MDREFR_E1PIN|MDREFR_E0PIN)
+	orr     r4,  r4, #(MDREFR_E1PIN)
+
+	@ write back mdrefr
+	@
+	str     r4,  [r1, #MDREFR_OFFSET]
+	ldr     r4,  [r1, #MDREFR_OFFSET]
+	nop
+	nop
+
+	/* Step 4d:							*/
+	/* fetch platform value of mdcnfg				*/
+	@
+	ldr     r2,  =CFG_MDCNFG_VAL
+
+	@ disable all sdram banks
+	@
+	bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
+	bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+
+	@ program banks 0/1 for bus width
+	@
+	bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit
+
+	@ write initial value of mdcnfg, w/o enabling sdram banks
+	@
+	str     r2,  [r1, #MDCNFG_OFFSET]
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty        */
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/* get memory controller base address                               */
+	ldr     r1,  =MEMC_BASE
+
+	@fetch current mdcnfg value
+	@
+	ldr     r3,  [r1, #MDCNFG_OFFSET]
+
+	@enable sdram bank 0 if installed (must do for any populated bank)
+	@
+	orr     r3,  r3,  #MDCNFG_DE0
+
+	@write back mdcnfg, enabling the sdram bank(s)
+	@
+	str     r3,  [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2,	=CFG_MDMRS_VAL
+	str     r2,	[r1, #MDMRS_OFFSET]
+
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2,  =ICLR
+	str     r1,  [r2]
+
+	ldr     r1,  =CFG_ICMR_VAL /* mask all interrupts at the controller */
+	ldr     r2,  =ICMR
+	str     r1,  [r2]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+	/* (hard-coding at 398.12MHz for now).                              */
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+	ldr     r1,  =CKEN
+	mov     r2,  #0
+	str     r2,  [r1]
+
+
+	/* default value						    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1,  =CCCR
+	str     r2,  [r1]
+
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+
+	ldr     r1,  =OSCC
+	mov     r2,  #OSCC_OON
+	str     r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+#endif
+
+	@ Turn on needed clocks
+	@
+test:
+	ldr     r1,  =CKEN
+	ldr     r2,  =CFG_CKEN_VAL
+	str     r2,  [r1]
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size ?*/
+	ldr	r1, =DRAM_SIZE
+	str	r8, [r1]
+
+	/* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init                                                     */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+	mov     pc, lr
diff --git a/board/xaeniax/u-boot.lds b/board/xaeniax/u-boot.lds
new file mode 100755
index 0000000..f010239
--- /dev/null
+++ b/board/xaeniax/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c
new file mode 100755
index 0000000..26fb312
--- /dev/null
+++ b/board/xaeniax/xaeniax.c
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2004
+ * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of xaeniax */
+	gd->bd->bi_arch_number = 585;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	/*	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;*/
+	/*	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;*/
+	/*	gd->bd->bi_dram[2].start = PHYS_SDRAM_3; */
+	/*	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; */
+	/*	gd->bd->bi_dram[3].start = PHYS_SDRAM_4; */
+	/*	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; */
+
+	return 0;
+}
diff --git a/board/xilinx/common/xbasic_types.c b/board/xilinx/common/xbasic_types.c
new file mode 100755
index 0000000..c3a171a
--- /dev/null
+++ b/board/xilinx/common/xbasic_types.c
@@ -0,0 +1,165 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+     *
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.c
+*
+* This file contains basic functions for Xilinx software IP.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+unsigned int XAssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+u32 XWaitInAssert = TRUE;
+
+/* The callback function to be invoked when an assert is taken */
+static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Implements assert. Currently, it calls a user-defined callback function
+* if one has been set.  Then, it potentially enters an infinite loop depending
+* on the value of the XWaitInAssert variable.
+*
+* @param    File is the name of the filename of the source
+* @param    Line is the linenumber within File
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XAssert(char *File, int Line)
+{
+	/* if the callback has been set then invoke it */
+	if (XAssertCallbackRoutine != NULL) {
+		(*XAssertCallbackRoutine) (File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (XWaitInAssert) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets up a callback function to be invoked when an assert occurs. If there
+* was already a callback installed, then it is replaced.
+*
+* @param    Routine is the callback to be invoked when an assert is taken
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void
+XAssertSetCallback(XAssertCallback Routine)
+{
+	XAssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* Null handler function. This follows the XInterruptHandler signature for
+* interrupt handlers. It can be used to assign a null handler (a stub) to an
+* interrupt controller vector table.
+*
+* @param    NullParameter is an arbitrary void pointer and not used.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XNullHandler(void *NullParameter)
+{
+}
diff --git a/board/xilinx/common/xbasic_types.h b/board/xilinx/common/xbasic_types.h
new file mode 100755
index 0000000..ef0b7c2
--- /dev/null
+++ b/board/xilinx/common/xbasic_types.h
@@ -0,0 +1,283 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+* This file contains basic types for Xilinx software IP.  These types do not
+* follow the standard naming convention with respect to using the component
+* name in front of each name because they are considered to be primitives.
+*
+* @note
+*
+* This file contains items which are architecture dependent.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rmm  12/14/01 First release
+*	rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
+*		      compiler warnings
+* 1.00a rpm  11/07/03 Added XNullHandler function as a stub interrupt handler
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H		/* prevent circular inclusions */
+#define XBASIC_TYPES_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+/** Null */
+
+#define XCOMPONENT_IS_READY	0x11111111	/* component has been initialized */
+#define XCOMPONENT_IS_STARTED	0x22222222	/* component has been started */
+
+/* the following constants and declarations are for unit test purposes and are
+ * designed to be used in test applications.
+ */
+#define XTEST_PASSED	0
+#define XTEST_FAILED	1
+
+#define XASSERT_NONE	 0
+#define XASSERT_OCCURRED 1
+
+extern unsigned int XAssertStatus;
+extern void XAssert(char *, int);
+
+/**************************** Type Definitions *******************************/
+
+/** @name Primitive types
+ * These primitive types are created for transportability.
+ * They are dependent upon the target architecture.
+ * @{
+ */
+#include <linux/types.h>
+
+typedef struct {
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+/*@}*/
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return
+*
+* The upper 32 bits of the 64 bit word.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return
+*
+* The lower 32 bits of the 64 bit word.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the XWaitInAssert boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to false,
+*	 the assert occurs.
+*
+* @return
+*
+* Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_VOID(expression)			\
+{							\
+	if (expression) {				\
+		XAssertStatus = XASSERT_NONE;		\
+	} else {					\
+		XAssert(__FILE__, __LINE__);		\
+		XAssertStatus = XASSERT_OCCURRED;	\
+		return;					\
+	}						\
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
+* that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to false,
+*	 the assert occurs.
+*
+* @return
+*
+* Returns 0 unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID(expression)		   \
+{						   \
+	if (expression) {			   \
+		XAssertStatus = XASSERT_NONE;	   \
+	} else {				   \
+		XAssert(__FILE__, __LINE__);	   \
+		XAssertStatus = XASSERT_OCCURRED;  \
+		return 0;			   \
+	}					   \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return
+*
+* Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_VOID_ALWAYS()			   \
+{						   \
+	XAssert(__FILE__, __LINE__);		   \
+	XAssertStatus = XASSERT_OCCURRED;	   \
+	return;					   \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return
+*
+* Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID_ALWAYS()		   \
+{						   \
+	XAssert(__FILE__, __LINE__);		   \
+	XAssertStatus = XASSERT_OCCURRED;	   \
+	return 0;				   \
+}
+
+#else
+
+#define XASSERT_VOID(expression)
+#define XASSERT_VOID_ALWAYS()
+#define XASSERT_NONVOID(expression)
+#define XASSERT_NONVOID_ALWAYS()
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void XAssertSetCallback(XAssertCallback Routine);
+void XNullHandler(void *NullParameter);
+
+#endif	/* end of protection macro */
diff --git a/board/xilinx/common/xbuf_descriptor.h b/board/xilinx/common/xbuf_descriptor.h
new file mode 100755
index 0000000..fdd51d5
--- /dev/null
+++ b/board/xilinx/common/xbuf_descriptor.h
@@ -0,0 +1,252 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xbuf_descriptor.h
+*
+* DESCRIPTION:
+*
+* This file contains the interface for the XBufDescriptor component.
+* The XBufDescriptor component is a passive component that only maps over
+* a buffer descriptor data structure shared by the scatter gather DMA hardware
+* and software. The component's primary purpose is to provide encapsulation of
+* the buffer descriptor processing.  See the source file xbuf_descriptor.c for
+* details.
+*
+* NOTES:
+*
+* Most of the functions of this component are implemented as macros in order
+* to optimize the processing.  The names are not all uppercase such that they
+* can be switched between macros and functions easily.
+*
+******************************************************************************/
+
+#ifndef XBUF_DESCRIPTOR_H	/* prevent circular inclusions */
+#define XBUF_DESCRIPTOR_H	/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xdma_channel_i.h"
+
+/************************** Constant Definitions *****************************/
+
+/* The following constants allow access to all fields of a buffer descriptor
+ * and are necessary at this level of visibility to allow macros to access
+ * and modify the fields of a buffer descriptor.  It is not expected that the
+ * user of a buffer descriptor would need to use these constants.
+ */
+
+#define XBD_DEVICE_STATUS_OFFSET    0
+#define XBD_CONTROL_OFFSET	    1
+#define XBD_SOURCE_OFFSET	    2
+#define XBD_DESTINATION_OFFSET	    3
+#define XBD_LENGTH_OFFSET	    4
+#define XBD_STATUS_OFFSET	    5
+#define XBD_NEXT_PTR_OFFSET	    6
+#define XBD_ID_OFFSET		    7
+#define XBD_FLAGS_OFFSET	    8
+#define XBD_RQSTED_LENGTH_OFFSET    9
+
+#define XBD_SIZE_IN_WORDS	    10
+
+/*
+ * The following constants define the bits of the flags field of a buffer
+ * descriptor
+ */
+
+#define XBD_FLAGS_LOCKED_MASK	    1UL
+
+/**************************** Type Definitions *******************************/
+
+typedef u32 XBufDescriptor[XBD_SIZE_IN_WORDS];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/* each of the following macros are named the same as functions rather than all
+ * upper case in order to allow either the macros or the functions to be
+ * used, see the source file xbuf_descriptor.c for documentation
+ */
+
+#define XBufDescriptor_Initialize(InstancePtr)			\
+{								\
+    (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = 0);   \
+    (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = 0); \
+    (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_ID_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = 0);	    \
+    (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = 0); \
+}
+
+#define XBufDescriptor_GetControl(InstancePtr)	 \
+    (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET))
+
+#define XBufDescriptor_SetControl(InstancePtr, Control)	 \
+    (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = (u32)Control)
+
+#define XBufDescriptor_IsLastControl(InstancePtr) \
+    (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) & \
+	       XDC_CONTROL_LAST_BD_MASK)
+
+#define XBufDescriptor_SetLast(InstancePtr) \
+    (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) |= XDC_CONTROL_LAST_BD_MASK)
+
+#define XBufDescriptor_GetSrcAddress(InstancePtr) \
+    ((u32 *)(*((u32 *)InstancePtr + XBD_SOURCE_OFFSET)))
+
+#define XBufDescriptor_SetSrcAddress(InstancePtr, Source) \
+    (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = (u32)Source)
+
+#define XBufDescriptor_GetDestAddress(InstancePtr) \
+    ((u32 *)(*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET)))
+
+#define XBufDescriptor_SetDestAddress(InstancePtr, Destination) \
+    (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = (u32)Destination)
+
+#define XBufDescriptor_GetLength(InstancePtr)				\
+    (u32)(*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) -	\
+	      *((u32 *)InstancePtr + XBD_LENGTH_OFFSET))
+
+#define XBufDescriptor_SetLength(InstancePtr, Length)			    \
+{									    \
+    (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = (u32)(Length));    \
+    (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = (u32)(Length));\
+}
+
+#define XBufDescriptor_GetStatus(InstancePtr)	 \
+    (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET))
+
+#define XBufDescriptor_SetStatus(InstancePtr, Status)	 \
+    (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = (u32)Status)
+
+#define XBufDescriptor_IsLastStatus(InstancePtr) \
+    (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET) & \
+	       XDC_STATUS_LAST_BD_MASK)
+
+#define XBufDescriptor_GetDeviceStatus(InstancePtr) \
+    ((u32)(*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET)))
+
+#define XBufDescriptor_SetDeviceStatus(InstancePtr, Status) \
+    (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = (u32)Status)
+
+#define XBufDescriptor_GetNextPtr(InstancePtr) \
+    (XBufDescriptor *)(*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET))
+
+#define XBufDescriptor_SetNextPtr(InstancePtr, NextPtr) \
+    (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = (u32)NextPtr)
+
+#define XBufDescriptor_GetId(InstancePtr) \
+    (u32)(*((u32 *)InstancePtr + XBD_ID_OFFSET))
+
+#define XBufDescriptor_SetId(InstancePtr, Id) \
+    (*((u32 *)InstancePtr + XBD_ID_OFFSET) = (u32)Id)
+
+#define XBufDescriptor_GetFlags(InstancePtr) \
+    (u32)(*((u32 *)InstancePtr + XBD_FLAGS_OFFSET))
+
+#define XBufDescriptor_SetFlags(InstancePtr, Flags) \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = (u32)Flags)
+
+#define XBufDescriptor_Lock(InstancePtr) \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) |= XBD_FLAGS_LOCKED_MASK)
+
+#define XBufDescriptor_Unlock(InstancePtr) \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) &= ~XBD_FLAGS_LOCKED_MASK)
+
+#define XBufDescriptor_IsLocked(InstancePtr) \
+    (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) & XBD_FLAGS_LOCKED_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/* The following prototypes are provided to allow each of the functions to
+ * be implemented as a function rather than a macro, and to provide the
+ * syntax to allow users to understand how to call the macros, they are
+ * commented out to prevent linker errors
+ *
+
+u32 XBufDescriptor_Initialize(XBufDescriptor* InstancePtr);
+
+u32 XBufDescriptor_GetControl(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetControl(XBufDescriptor* InstancePtr, u32 Control);
+
+u32 XBufDescriptor_IsLastControl(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetLast(XBufDescriptor* InstancePtr);
+
+u32 XBufDescriptor_GetLength(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetLength(XBufDescriptor* InstancePtr, u32 Length);
+
+u32 XBufDescriptor_GetStatus(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetStatus(XBufDescriptor* InstancePtr, u32 Status);
+u32 XBufDescriptor_IsLastStatus(XBufDescriptor* InstancePtr);
+
+u32 XBufDescriptor_GetDeviceStatus(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetDeviceStatus(XBufDescriptor* InstancePtr,
+				    u32 Status);
+
+u32 XBufDescriptor_GetSrcAddress(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetSrcAddress(XBufDescriptor* InstancePtr,
+				  u32 SourceAddress);
+
+u32 XBufDescriptor_GetDestAddress(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetDestAddress(XBufDescriptor* InstancePtr,
+				   u32 DestinationAddress);
+
+XBufDescriptor* XBufDescriptor_GetNextPtr(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetNextPtr(XBufDescriptor* InstancePtr,
+			       XBufDescriptor* NextPtr);
+
+u32 XBufDescriptor_GetId(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetId(XBufDescriptor* InstancePtr, u32 Id);
+
+u32 XBufDescriptor_GetFlags(XBufDescriptor* InstancePtr);
+void XBufDescriptor_SetFlags(XBufDescriptor* InstancePtr, u32 Flags);
+
+void XBufDescriptor_Lock(XBufDescriptor* InstancePtr);
+void XBufDescriptor_Unlock(XBufDescriptor* InstancePtr);
+u32 XBufDescriptor_IsLocked(XBufDescriptor* InstancePtr);
+
+void XBufDescriptor_Copy(XBufDescriptor* InstancePtr,
+			 XBufDescriptor* DestinationPtr);
+
+*/
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xdma_channel.c b/board/xilinx/common/xdma_channel.c
new file mode 100755
index 0000000..3d5fc75
--- /dev/null
+++ b/board/xilinx/common/xdma_channel.c
@@ -0,0 +1,738 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xdma_channel.c
+*
+* DESCRIPTION:
+*
+* This file contains the DMA channel component. This component supports
+* a distributed DMA design in which each device can have it's own dedicated
+* DMA channel, as opposed to a centralized DMA design. This component
+* performs processing for DMA on all devices.
+*
+* See xdma_channel.h for more information about this component.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdma_channel.h"
+#include "xbasic_types.h"
+#include "xio.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_Initialize
+*
+* DESCRIPTION:
+*
+* This function initializes a DMA channel.  This function must be called
+* prior to using a DMA channel.  Initialization of a channel includes setting
+* up the registers base address, and resetting the channel such that it's in a
+* known state.  Interrupts for the channel are disabled when the channel is
+* reset.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* BaseAddress contains the base address of the registers for the DMA channel.
+*
+* RETURN VALUE:
+*
+* XST_SUCCESS indicating initialization was successful.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress)
+{
+	/* assert to verify input arguments, don't assert base address */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+
+	/* setup the base address of the registers for the DMA channel such
+	 * that register accesses can be done
+	 */
+	InstancePtr->RegBaseAddress = BaseAddress;
+
+	/* initialize the scatter gather list such that it indicates it has not
+	 * been created yet and the DMA channel is ready to use (initialized)
+	 */
+	InstancePtr->GetPtr = NULL;
+	InstancePtr->PutPtr = NULL;
+	InstancePtr->CommitPtr = NULL;
+	InstancePtr->LastPtr = NULL;
+
+	InstancePtr->TotalDescriptorCount = 0;
+	InstancePtr->ActiveDescriptorCount = 0;
+	InstancePtr->IsReady = XCOMPONENT_IS_READY;
+
+	/* initialize the version of the component
+	 */
+	XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a");
+
+	/* reset the DMA channel such that it's in a known state and ready
+	 * and indicate the initialization occured with no errors, note that
+	 * the is ready variable must be set before this call or reset will assert
+	 */
+	XDmaChannel_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_IsReady
+*
+* DESCRIPTION:
+*
+* This function determines if a DMA channel component has been successfully
+* initialized such that it's ready to use.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* TRUE if the DMA channel component is ready, FALSE otherwise.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_IsReady(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments used by the base component */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+
+	return InstancePtr->IsReady == XCOMPONENT_IS_READY;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetVersion
+*
+* DESCRIPTION:
+*
+* This function gets the software version for the specified DMA channel
+* component.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* A pointer to the software version of the specified DMA channel.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XVersion *
+XDmaChannel_GetVersion(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return a pointer to the version of the DMA channel */
+
+	return &InstancePtr->Version;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SelfTest
+*
+* DESCRIPTION:
+*
+* This function performs a self test on the specified DMA channel.  This self
+* test is destructive as the DMA channel is reset and a register default is
+* verified.
+*
+* ARGUMENTS:
+*
+* InstancePtr is a pointer to the DMA channel to be operated on.
+*
+* RETURN VALUE:
+*
+* XST_SUCCESS is returned if the self test is successful, or one of the
+* following errors.
+*
+*	XST_DMA_RESET_REGISTER_ERROR 		Indicates the control register value
+*										after a reset was not correct
+*
+* NOTES:
+*
+* This test does not performs a DMA transfer to test the channel because the
+* DMA hardware will not currently allow a non-local memory transfer to non-local
+* memory (memory copy), but only allows a non-local memory to or from the device
+* memory (typically a FIFO).
+*
+******************************************************************************/
+
+#define XDC_CONTROL_REG_RESET_MASK  0x98000000UL	/* control reg reset value */
+
+XStatus
+XDmaChannel_SelfTest(XDmaChannel * InstancePtr)
+{
+	u32 ControlReg;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* reset the DMA channel such that it's in a known state before the test
+	 * it resets to no interrupts enabled, the desired state for the test
+	 */
+	XDmaChannel_Reset(InstancePtr);
+
+	/* this should be the first test to help prevent a lock up with the polling
+	 * loop that occurs later in the test, check the reset value of the DMA
+	 * control register to make sure it's correct, return with an error if not
+	 */
+	ControlReg = XDmaChannel_GetControl(InstancePtr);
+	if (ControlReg != XDC_CONTROL_REG_RESET_MASK) {
+		return XST_DMA_RESET_REGISTER_ERROR;
+	}
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_Reset
+*
+* DESCRIPTION:
+*
+* This function resets the DMA channel. This is a destructive operation such
+* that it should not be done while a channel is being used.  If the DMA channel
+* is transferring data into other blocks, such as a FIFO, it may be necessary
+* to reset other blocks.  This function does not modify the contents of a
+* scatter gather list for a DMA channel such that the user is responsible for
+* getting buffer descriptors from the list if necessary.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_Reset(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* reset the DMA channel such that it's in a known state, the reset
+	 * register is self clearing such that it only has to be set
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET,
+		  XDC_RESET_MASK);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetControl
+*
+* DESCRIPTION:
+*
+* This function gets the control register contents of the DMA channel.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* The control register contents of the DMA channel. One or more of the
+* following values may be contained the register.  Each of the values are
+* unique bit masks.
+*
+*	XDC_DMACR_SOURCE_INCR_MASK	Increment the source address
+*	XDC_DMACR_DEST_INCR_MASK	Increment the destination address
+*	XDC_DMACR_SOURCE_LOCAL_MASK Local source address
+*	XDC_DMACR_DEST_LOCAL_MASK	Local destination address
+*	XDC_DMACR_SG_ENABLE_MASK	Scatter gather enable
+*	XDC_DMACR_GEN_BD_INTR_MASK	Individual buffer descriptor interrupt
+*	XDC_DMACR_LAST_BD_MASK		Last buffer descriptor in a packet
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetControl(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return the contents of the DMA control register */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetControl
+*
+* DESCRIPTION:
+*
+* This function sets the control register of the specified DMA channel.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* Control contains the value to be written to the control register of the DMA
+* channel. One or more of the following values may be contained the register.
+* Each of the values are unique bit masks such that they may be ORed together
+* to enable multiple bits or inverted and ANDed to disable multiple bits.
+*
+*	XDC_DMACR_SOURCE_INCR_MASK	Increment the source address
+*	XDC_DMACR_DEST_INCR_MASK	Increment the destination address
+*	XDC_DMACR_SOURCE_LOCAL_MASK Local source address
+*	XDC_DMACR_DEST_LOCAL_MASK	Local destination address
+*	XDC_DMACR_SG_ENABLE_MASK	Scatter gather enable
+*	XDC_DMACR_GEN_BD_INTR_MASK	Individual buffer descriptor interrupt
+*	XDC_DMACR_LAST_BD_MASK		Last buffer descriptor in a packet
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control)
+{
+	/* assert to verify input arguments except the control which can't be
+	 * asserted since all values are valid
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the DMA control register to the specified value */
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, Control);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetStatus
+*
+* DESCRIPTION:
+*
+* This function gets the status register contents of the DMA channel.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* The status register contents of the DMA channel. One or more of the
+* following values may be contained the register. Each of the values are
+* unique bit masks.
+*
+*	XDC_DMASR_BUSY_MASK			The DMA channel is busy
+*	XDC_DMASR_BUS_ERROR_MASK	A bus error occurred
+*	XDC_DMASR_BUS_TIMEOUT_MASK	A bus timeout occurred
+*	XDC_DMASR_LAST_BD_MASK		The last buffer descriptor of a packet
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetStatus(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return the contents of the DMA status register */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetIntrStatus
+*
+* DESCRIPTION:
+*
+* This function sets the interrupt status register of the specified DMA channel.
+* Setting any bit of the interrupt status register will clear the bit to
+* indicate the interrupt processing has been completed. The definitions of each
+* bit in the register match the definition of the bits in the interrupt enable
+* register.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* Status contains the value to be written to the status register of the DMA
+* channel.  One or more of the following values may be contained the register.
+* Each of the values are unique bit masks such that they may be ORed together
+* to enable multiple bits or inverted and ANDed to disable multiple bits.
+*
+*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
+*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
+*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
+*	XDC_IXR_PKT_THRESHOLD_MASK 	The packet count threshold reached
+*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
+*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
+*	XDC_IXR_BD_MASK				A buffer descriptor is done
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status)
+{
+	/* assert to verify input arguments except the status which can't be
+	 * asserted since all values are valid
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the interrupt status register with the specified value such that
+	 * all bits which are set in the register are cleared effectively clearing
+	 * any active interrupts
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetIntrStatus
+*
+* DESCRIPTION:
+*
+* This function gets the interrupt status register of the specified DMA channel.
+* The interrupt status register indicates which interrupts are active
+* for the DMA channel.  If an interrupt is active, the status register must be
+* set (written) with the bit set for each interrupt which has been processed
+* in order to clear the interrupts.  The definitions of each bit in the register
+* match the definition of the bits in the interrupt enable register.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* The interrupt status register contents of the specified DMA channel.
+* One or more of the following values may be contained the register.
+* Each of the values are unique bit masks.
+*
+*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
+*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
+*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
+*	XDC_IXR_PKT_THRESHOLD_MASK 	The packet count threshold reached
+*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
+*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
+*	XDC_IXR_SG_END_MASK			Current descriptor was the end of the list
+*	XDC_IXR_BD_MASK				A buffer descriptor is done
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return the contents of the interrupt status register */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetIntrEnable
+*
+* DESCRIPTION:
+*
+* This function sets the interrupt enable register of the specified DMA
+* channel.  The interrupt enable register contains bits which enable
+* individual interrupts for the DMA channel.  The definitions of each bit
+* in the register match the definition of the bits in the interrupt status
+* register.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* Enable contains the interrupt enable register contents to be written
+* in the DMA channel. One or more of the following values may be contained
+* the register. Each of the values are unique bit masks such that they may be
+* ORed together to enable multiple bits or inverted and ANDed to disable
+* multiple bits.
+*
+*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
+*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
+*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
+*	XDC_IXR_PKT_THRESHOLD_MASK 	The packet count threshold reached
+*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
+*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
+*	XDC_IXR_SG_END_MASK			Current descriptor was the end of the list
+*	XDC_IXR_BD_MASK				A buffer descriptor is done
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable)
+{
+	/* assert to verify input arguments except the enable which can't be
+	 * asserted since all values are valid
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the interrupt enable register to the specified value */
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetIntrEnable
+*
+* DESCRIPTION:
+*
+* This function gets the interrupt enable of the DMA channel.  The
+* interrupt enable contains flags which enable individual interrupts for the
+* DMA channel. The definitions of each bit in the register match the definition
+* of the bits in the interrupt status register.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* RETURN VALUE:
+*
+* The interrupt enable of the DMA channel.  One or more of the following values
+* may be contained the register. Each of the values are unique bit masks.
+*
+*	XDC_IXR_DMA_DONE_MASK		The dma operation is done
+*	XDC_IXR_DMA_ERROR_MASK	    The dma operation had an error
+*	XDC_IXR_PKT_DONE_MASK	    A packet is complete
+*	XDC_IXR_PKT_THRESHOLD_MASK 	The packet count threshold reached
+*	XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
+*	XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
+*	XDC_IXR_BD_MASK				A buffer descriptor is done
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* return the contents of the interrupt enable register */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_Transfer
+*
+* DESCRIPTION:
+*
+* This function starts the DMA channel transferring data from a memory source
+* to a memory destination. This function only starts the operation and returns
+* before the operation may be complete.  If the interrupt is enabled, an
+* interrupt will be generated when the operation is complete, otherwise it is
+* necessary to poll the channel status to determine when it's complete.  It is
+* the responsibility of the caller to determine when the operation is complete
+* by handling the generated interrupt or polling the status.  It is also the
+* responsibility of the caller to ensure that the DMA channel is not busy with
+* another transfer before calling this function.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.
+*
+* SourcePtr contains a pointer to the source memory where the data is to
+* be tranferred from and must be 32 bit aligned.
+*
+* DestinationPtr contains a pointer to the destination memory where the data
+* is to be transferred and must be 32 bit aligned.
+*
+* ByteCount contains the number of bytes to transfer during the DMA operation.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* The DMA h/w will not currently allow a non-local memory transfer to non-local
+* memory (memory copy), but only allows a non-local memory to or from the device
+* memory (typically a FIFO).
+*
+* It is the responsibility of the caller to ensure that the cache is
+* flushed and invalidated both before and after the DMA operation completes
+* if the memory pointed to is cached. The caller must also ensure that the
+* pointers contain a physical address rather than a virtual address
+* if address translation is being used.
+*
+******************************************************************************/
+void
+XDmaChannel_Transfer(XDmaChannel * InstancePtr,
+		     u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount)
+{
+	/* assert to verify input arguments and the alignment of any arguments
+	 * which have expected alignments
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(SourcePtr != NULL);
+	XASSERT_VOID(((u32) SourcePtr & 3) == 0);
+	XASSERT_VOID(DestinationPtr != NULL);
+	XASSERT_VOID(((u32) DestinationPtr & 3) == 0);
+	XASSERT_VOID(ByteCount != 0);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* setup the source and destination address registers for the transfer */
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET,
+		  (u32) SourcePtr);
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET,
+		  (u32) DestinationPtr);
+
+	/* start the DMA transfer to copy from the source buffer to the
+	 * destination buffer by writing the length to the length register
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount);
+}
diff --git a/board/xilinx/common/xdma_channel.h b/board/xilinx/common/xdma_channel.h
new file mode 100755
index 0000000..06976c3
--- /dev/null
+++ b/board/xilinx/common/xdma_channel.h
@@ -0,0 +1,291 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xdma_channel.h
+*
+* DESCRIPTION:
+*
+* This file contains the DMA channel component implementation. This component
+* supports a distributed DMA design in which each device can have it's own
+* dedicated DMA channel, as opposed to a centralized DMA design.
+* A device which uses DMA typically contains two DMA channels, one for
+* sending data and the other for receiving data.
+*
+* This component is designed to be used as a basic building block for
+* designing a device driver. It provides registers accesses such that all
+* DMA processing can be maintained easier, but the device driver designer
+* must still understand all the details of the DMA channel.
+*
+* The DMA channel allows a CPU to minimize the CPU interaction required to move
+* data between a memory and a device.  The CPU requests the DMA channel to
+* perform a DMA operation and typically continues performing other processing
+* until the DMA operation completes.  DMA could be considered a primitive form
+* of multiprocessing such that caching and address translation can be an issue.
+*
+* Scatter Gather Operations
+*
+* The DMA channel may support scatter gather operations. A scatter gather
+* operation automates the DMA channel such that multiple buffers can be
+* sent or received with minimal software interaction with the hardware.  Buffer
+* descriptors, contained in the XBufDescriptor component, are used by the
+* scatter gather operations of the DMA channel to describe the buffers to be
+* processed.
+*
+* Scatter Gather List Operations
+*
+* A scatter gather list may be supported by each DMA channel.  The scatter
+* gather list allows buffer descriptors to be put into the list by a device
+* driver which requires scatter gather.  The hardware processes the buffer
+* descriptors which are contained in the list and modifies the buffer
+* descriptors to reflect the status of the DMA operations.  The device driver
+* is notified by interrupt that specific DMA events occur including scatter
+* gather events.  The device driver removes the completed buffer descriptors
+* from the scatter gather list to evaluate the status of each DMA operation.
+*
+* The scatter gather list is created and buffer descriptors are inserted into
+* the list.  Buffer descriptors are never removed from the list after it's
+* creation such that a put operation copies from a temporary buffer descriptor
+* to a buffer descriptor in the list.  Get operations don't copy from the list
+* to a temporary, but return a pointer to the buffer descriptor in the list.
+* A buffer descriptor in the list may be locked to prevent it from being
+* overwritten by a put operation.  This allows the device driver to get a
+* descriptor from a scatter gather list and prevent it from being overwritten
+* until the buffer associated with the buffer descriptor has been processed.
+*
+* Typical Scatter Gather Processing
+*
+* The following steps illustrate the typical processing to use the
+* scatter gather features of a DMA channel.
+*
+* 1. Create a scatter gather list for the DMA channel which puts empty buffer
+*    descriptors into the list.
+* 2. Create buffer descriptors which describe the buffers to be filled with
+* 	 receive data or the buffers which contain data to be sent.
+* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
+*    gather operations are requested.
+* 4. Commit the buffer descriptors in the list such that they are ready to be
+*    used by the DMA channel hardware.
+* 5. Start the scatter gather operations of the DMA channel.
+* 6. Process any interrupts which occur as a result of the scatter gather
+*    operations or poll the DMA channel to determine the status.
+*
+* Interrupts
+*
+* Each DMA channel has the ability to generate an interrupt.  This component
+* does not perform processing for the interrupt as this processing is typically
+* tightly coupled with the device which is using the DMA channel.  It is the
+* responsibility of the caller of DMA functions to manage the interrupt
+* including connecting to the interrupt and enabling/disabling the interrupt.
+*
+* Critical Sections
+*
+* It is the responsibility of the device driver designer to use critical
+* sections as necessary when calling functions of the DMA channel.  This
+* component does not use critical sections and it does access registers using
+* read-modify-write operations.  Calls to DMA functions from a main thread
+* and from an interrupt context could produce unpredictable behavior such that
+* the caller must provide the appropriate critical sections.
+*
+* Address Translation
+*
+* All addresses of data structures which are passed to DMA functions must
+* be physical (real) addresses as opposed to logical (virtual) addresses.
+*
+* Caching
+*
+* The memory which is passed to the function which creates the scatter gather
+* list must not be cached such that buffer descriptors are non-cached.  This
+* is necessary because the buffer descriptors are kept in a ring buffer and
+* not directly accessible to the caller of DMA functions.
+*
+* The caller of DMA functions is responsible for ensuring that any data
+* buffers which are passed to the DMA channel are cache-line aligned if
+* necessary.
+*
+* The caller of DMA functions is responsible for ensuring that any data
+* buffers which are passed to the DMA channel have been flushed from the cache.
+*
+* The caller of DMA functions is responsible for ensuring that the cache is
+* invalidated prior to using any data buffers which are the result of a DMA
+* operation.
+*
+* Memory Alignment
+*
+* The addresses of data buffers which are passed to DMA functions must be
+* 32 bit word aligned since the DMA hardware performs 32 bit word transfers.
+*
+* Mutual Exclusion
+*
+* The functions of the DMA channel are not thread safe such that the caller
+* of all DMA functions is responsible for ensuring mutual exclusion for a
+* DMA channel.  Mutual exclusion across multiple DMA channels is not
+* necessary.
+*
+* NOTES:
+*
+* Many of the provided functions which are register accessors don't provide
+* a lot of error detection. The caller is expected to understand the impact
+* of a function call based upon the current state of the DMA channel.  This
+* is done to minimize the overhead in this component.
+*
+******************************************************************************/
+
+#ifndef XDMA_CHANNEL_H		/* prevent circular inclusions */
+#define XDMA_CHANNEL_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xdma_channel_i.h"	/* constants shared with buffer descriptor */
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xversion.h"
+#include "xbuf_descriptor.h"
+
+/************************** Constant Definitions *****************************/
+
+/* the following constants provide access to the bit fields of the DMA control
+ * register (DMACR)
+ */
+#define XDC_DMACR_SOURCE_INCR_MASK	0x80000000UL	/* increment source address */
+#define XDC_DMACR_DEST_INCR_MASK	0x40000000UL	/* increment dest address */
+#define XDC_DMACR_SOURCE_LOCAL_MASK 0x20000000UL	/* local source address */
+#define XDC_DMACR_DEST_LOCAL_MASK	0x10000000UL	/* local dest address */
+#define XDC_DMACR_SG_DISABLE_MASK	0x08000000UL	/* scatter gather disable */
+#define XDC_DMACR_GEN_BD_INTR_MASK	0x04000000UL	/* descriptor interrupt */
+#define XDC_DMACR_LAST_BD_MASK		XDC_CONTROL_LAST_BD_MASK	/* last buffer */
+															 /*     descriptor  */
+
+/* the following constants provide access to the bit fields of the DMA status
+ * register (DMASR)
+ */
+#define XDC_DMASR_BUSY_MASK			0x80000000UL	/* channel is busy */
+#define XDC_DMASR_BUS_ERROR_MASK	0x40000000UL	/* bus error occurred */
+#define XDC_DMASR_BUS_TIMEOUT_MASK	0x20000000UL	/* bus timeout occurred */
+#define XDC_DMASR_LAST_BD_MASK		XDC_STATUS_LAST_BD_MASK	/* last buffer */
+														    /* descriptor  */
+#define XDC_DMASR_SG_BUSY_MASK		0x08000000UL	/* scatter gather is busy */
+
+/* the following constants provide access to the bit fields of the interrupt
+ * status register (ISR) and the interrupt enable register (IER), bit masks
+ * match for both registers such that they are named IXR
+ */
+#define XDC_IXR_DMA_DONE_MASK		0x1UL	/* dma operation done */
+#define XDC_IXR_DMA_ERROR_MASK	    0x2UL	/* dma operation error */
+#define XDC_IXR_PKT_DONE_MASK	    0x4UL	/* packet done */
+#define XDC_IXR_PKT_THRESHOLD_MASK 	0x8UL	/* packet count threshold */
+#define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL	/* packet wait bound reached */
+#define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL	/* scatter gather disable
+						   acknowledge occurred */
+#define XDC_IXR_SG_END_MASK			0x40UL	/* last buffer descriptor
+							   disabled scatter gather */
+#define XDC_IXR_BD_MASK				0x80UL	/* buffer descriptor done */
+
+/**************************** Type Definitions *******************************/
+
+/*
+ * the following structure contains data which is on a per instance basis
+ * for the XDmaChannel component
+ */
+typedef struct XDmaChannelTag {
+	XVersion Version;	/* version of the driver */
+	u32 RegBaseAddress;	/* base address of registers */
+	u32 IsReady;		/* device is initialized and ready */
+
+	XBufDescriptor *PutPtr;	/* keep track of where to put into list */
+	XBufDescriptor *GetPtr;	/* keep track of where to get from list */
+	XBufDescriptor *CommitPtr;	/* keep track of where to commit in list */
+	XBufDescriptor *LastPtr;	/* keep track of the last put in the list */
+	u32 TotalDescriptorCount;	/* total # of descriptors in the list */
+	u32 ActiveDescriptorCount;	/* # of descriptors pointing to buffers
+					   * in the buffer descriptor list */
+} XDmaChannel;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+XStatus XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress);
+u32 XDmaChannel_IsReady(XDmaChannel * InstancePtr);
+XVersion *XDmaChannel_GetVersion(XDmaChannel * InstancePtr);
+XStatus XDmaChannel_SelfTest(XDmaChannel * InstancePtr);
+void XDmaChannel_Reset(XDmaChannel * InstancePtr);
+
+/* Control functions */
+
+u32 XDmaChannel_GetControl(XDmaChannel * InstancePtr);
+void XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control);
+
+/* Status functions */
+
+u32 XDmaChannel_GetStatus(XDmaChannel * InstancePtr);
+void XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status);
+u32 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr);
+void XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable);
+u32 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr);
+
+/* DMA without scatter gather functions */
+
+void XDmaChannel_Transfer(XDmaChannel * InstancePtr,
+			  u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount);
+
+/* Scatter gather functions */
+
+XStatus XDmaChannel_SgStart(XDmaChannel * InstancePtr);
+XStatus XDmaChannel_SgStop(XDmaChannel * InstancePtr,
+			   XBufDescriptor ** BufDescriptorPtr);
+XStatus XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
+				 u32 * MemoryPtr, u32 ByteCount);
+u32 XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr);
+
+XStatus XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
+				  XBufDescriptor * BufDescriptorPtr);
+XStatus XDmaChannel_CommitPuts(XDmaChannel * InstancePtr);
+XStatus XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
+				  XBufDescriptor ** BufDescriptorPtr);
+
+/* Packet functions for interrupt collescing */
+
+u32 XDmaChannel_GetPktCount(XDmaChannel * InstancePtr);
+void XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr);
+XStatus XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold);
+u8 XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr);
+void XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound);
+u32 XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr);
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xdma_channel_i.h b/board/xilinx/common/xdma_channel_i.h
new file mode 100755
index 0000000..e9f343b
--- /dev/null
+++ b/board/xilinx/common/xdma_channel_i.h
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xdma_channel_i.h
+*
+* DESCRIPTION:
+*
+* This file contains data which is shared internal data for the DMA channel
+* component. It is also shared with the buffer descriptor component which is
+* very tightly coupled with the DMA channel component.
+*
+* NOTES:
+*
+* The last buffer descriptor constants must be located here to prevent a
+* circular dependency between the DMA channel component and the buffer
+* descriptor component.
+*
+******************************************************************************/
+
+#ifndef XDMA_CHANNEL_I_H	/* prevent circular inclusions */
+#define XDMA_CHANNEL_I_H	/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xversion.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XDC_DMA_CHANNEL_V1_00_A		"1.00a"
+
+/* the following constant provides access to the bit fields of the DMA control
+ * register (DMACR) which must be shared between the DMA channel component
+ * and the buffer descriptor component
+ */
+#define XDC_CONTROL_LAST_BD_MASK	0x02000000UL	/* last buffer descriptor */
+
+/* the following constant provides access to the bit fields of the DMA status
+ * register (DMASR) which must be shared between the DMA channel component
+ * and the buffer descriptor component
+ */
+#define XDC_STATUS_LAST_BD_MASK		0x10000000UL	/* last buffer descriptor */
+
+/* the following constants provide access to each of the registers of a DMA
+ * channel
+ */
+#define XDC_RST_REG_OFFSET	0	/* reset register */
+#define XDC_MI_REG_OFFSET	0	/* module information register */
+#define XDC_DMAC_REG_OFFSET	4	/* DMA control register */
+#define XDC_SA_REG_OFFSET	8	/* source address register */
+#define XDC_DA_REG_OFFSET	12	/* destination address register */
+#define XDC_LEN_REG_OFFSET	16	/* length register */
+#define XDC_DMAS_REG_OFFSET	20	/* DMA status register */
+#define XDC_BDA_REG_OFFSET	24	/* buffer descriptor address register */
+#define XDC_SWCR_REG_OFFSET 28	/* software control register */
+#define XDC_UPC_REG_OFFSET	32	/* unserviced packet count register */
+#define	XDC_PCT_REG_OFFSET	36	/* packet count threshold register */
+#define XDC_PWB_REG_OFFSET	40	/* packet wait bound register */
+#define XDC_IS_REG_OFFSET	44	/* interrupt status register */
+#define XDC_IE_REG_OFFSET	48	/* interrupt enable register */
+
+/* the following constant is written to the reset register to reset the
+ * DMA channel
+ */
+#define XDC_RESET_MASK				0x0000000AUL
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xdma_channel_sg.c b/board/xilinx/common/xdma_channel_sg.c
new file mode 100755
index 0000000..a8e9462
--- /dev/null
+++ b/board/xilinx/common/xdma_channel_sg.c
@@ -0,0 +1,1317 @@
+/* $Id: xdma_channel_sg.c,v 1.6 2003/02/03 19:50:33 moleres Exp $ */
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* FILENAME:
+*
+* xdma_channel_sg.c
+*
+* DESCRIPTION:
+*
+* This file contains the implementation of the XDmaChannel component which is
+* related to scatter gather operations.
+*
+* Scatter Gather Operations
+*
+* The DMA channel may support scatter gather operations. A scatter gather
+* operation automates the DMA channel such that multiple buffers can be
+* sent or received with minimal software interaction with the hardware.	 Buffer
+* descriptors, contained in the XBufDescriptor component, are used by the
+* scatter gather operations of the DMA channel to describe the buffers to be
+* processed.
+*
+* Scatter Gather List Operations
+*
+* A scatter gather list may be supported by each DMA channel.  The scatter
+* gather list allows buffer descriptors to be put into the list by a device
+* driver which requires scatter gather.	 The hardware processes the buffer
+* descriptors which are contained in the list and modifies the buffer
+* descriptors to reflect the status of the DMA operations.  The device driver
+* is notified by interrupt that specific DMA events occur including scatter
+* gather events.  The device driver removes the completed buffer descriptors
+* from the scatter gather list to evaluate the status of each DMA operation.
+*
+* The scatter gather list is created and buffer descriptors are inserted into
+* the list.  Buffer descriptors are never removed from the list after it's
+* creation such that a put operation copies from a temporary buffer descriptor
+* to a buffer descriptor in the list.  Get operations don't copy from the list
+* to a temporary, but return a pointer to the buffer descriptor in the list.
+* A buffer descriptor in the list may be locked to prevent it from being
+* overwritten by a put operation.  This allows the device driver to get a
+* descriptor from a scatter gather list and prevent it from being overwritten
+* until the buffer associated with the buffer descriptor has been processed.
+*
+* The get and put functions only operate on the list and are asynchronous from
+* the hardware which may be using the list of descriptors.  This is important
+* because there are no checks in the get and put functions to ensure that the
+* hardware has processed the descriptors.  This must be handled by the driver
+* using the DMA scatter gather channel through the use of the other functions.
+* When a scatter gather operation is started, the start function does ensure
+* that the descriptor to start has not already been processed by the hardware
+* and is not the first of a series of descriptors that have not been committed
+* yet.
+*
+* Descriptors are put into the list but not marked as ready to use by the
+* hardware until a commit operation is done.  This allows multiple descriptors
+* which may contain a single packet of information for a protocol to be
+* guaranteed not to cause any underflow conditions during transmission. The
+* hardware design only allows descriptors to cause it to stop after a descriptor
+* has been processed rather than before it is processed.  A series of
+* descriptors are put into the list followed by a commit operation, or each
+* descriptor may be commited.  A commit operation is performed by changing a
+* single descriptor, the first of the series of puts, to indicate that the
+* hardware may now use all descriptors after it.  The last descriptor in the
+* list is always set to cause the hardware to stop after it is processed.
+*
+* Typical Scatter Gather Processing
+*
+* The following steps illustrate the typical processing to use the
+* scatter gather features of a DMA channel.
+*
+* 1. Create a scatter gather list for the DMA channel which puts empty buffer
+*    descriptors into the list.
+* 2. Create buffer descriptors which describe the buffers to be filled with
+*    receive data or the buffers which contain data to be sent.
+* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
+*    gather operations are requested.
+* 4. Commit the buffer descriptors in the list such that they are ready to be
+*    used by the DMA channel hardware.
+* 5. Start the scatter gather operations of the DMA channel.
+* 6. Process any interrupts which occur as a result of the scatter gather
+*    operations or poll the DMA channel to determine the status.  This may
+*    be accomplished by getting the packet count for the channel and then
+*    getting the appropriate number of descriptors from the list for that
+*    number of packets.
+*
+* Minimizing Interrupts
+*
+* The Scatter Gather operating mode is designed to reduce the amount of CPU
+* throughput necessary to manage the hardware for devices. A key to the CPU
+* throughput is the number and rate of interrupts that the CPU must service.
+* Devices with higher data rates can cause larger numbers of interrupts and
+* higher frequency interrupts. Ideally the number of interrupts can be reduced
+* by only generating an interrupt when a specific amount of data has been
+* received from the interface. This design suffers from a lack of interrupts
+* when the amount of data received is less than the specified amount of data
+* to generate an interrupt. In order to help minimize the number of interrupts
+* which the CPU must service, an algorithm referred to as "interrupt coalescing"
+* is utilized.
+*
+* Interrupt Coalescing
+*
+* The principle of interrupt coalescing is to wait before generating an
+* interrupt until a certain number of packets have been received or sent. An
+* interrupt is also generated if a smaller number of packets have been received
+* followed by a certain period of time with no packet reception. This is a
+* trade-off of latency for bandwidth and is accomplished using several
+* mechanisms of the hardware including a counter for packets received or
+* transmitted and a packet timer. These two hardware mechanisms work in
+* combination to allow a reduction in the number of interrupts processed by the
+* CPU for packet reception.
+*
+* Unserviced Packet Count
+*
+* The purpose of the packet counter is to count the number of packets received
+* or transmitted and provide an interrupt when a specific number of packets
+* have been processed by the hardware. An interrupt is generated whenever the
+* counter is greater than or equal to the Packet Count Threshold. This counter
+* contains an accurate count of the number of packets that the hardware has
+* processed, either received or transmitted, and the software has not serviced.
+*
+* The packet counter allows the number of interrupts to be reduced by waiting
+* to generate an interrupt until enough packets are received. For packet
+* reception, packet counts of less than the number to generate an interrupt
+* would not be serviced without the addition of a packet timer. This counter is
+* continuously updated by the hardware, not latched to the value at the time
+* the interrupt occurred.
+*
+* The packet counter can be used within the interrupt service routine for the
+* device to reduce the number of interrupts. The interrupt service routine
+* loops while performing processing for each packet which has been received or
+* transmitted and decrements the counter by a specified value. At the same time,
+* the hardware is possibly continuing to receive or transmit more packets such
+* that the software may choose, based upon the value in the packet counter, to
+* remain in the interrupt service routine rather than exiting and immediately
+* returning. This feature should be used with caution as reducing the number of
+* interrupts is beneficial, but unbounded interrupt processing is not desirable.
+*
+* Since the hardware may be incrementing the packet counter simultaneously
+* with the software decrementing the counter, there is a need for atomic
+* operations. The hardware ensures that the operation is atomic such that
+* simultaneous accesses are properly handled.
+*
+* Packet Wait Bound
+*
+* The purpose of the packet wait bound is to augment the unserviced packet
+* count. Whenever there is no pending interrupt for the channel and the
+* unserviced packet count is non-zero, a timer starts counting timeout at the
+* value contained the the packet wait bound register.  If the timeout is
+* reached, an interrupt is generated such that the software may service the
+* data which was buffered.
+*
+* NOTES:
+*
+* Special Test Conditions:
+*
+* The scatter gather list processing must be thoroughly tested if changes are
+* made.	 Testing should include putting and committing single descriptors and
+* putting multiple descriptors followed by a single commit.  There are some
+* conditions in the code which handle the exception conditions.
+*
+* The Put Pointer points to the next location in the descriptor list to copy
+* in a new descriptor. The Get Pointer points to the next location in the
+* list to get a descriptor from.  The Get Pointer only allows software to
+* have a traverse the list after the hardware has finished processing some
+* number of descriptors.  The Commit Pointer points to the descriptor in the
+* list which is to be committed.  It is also used to determine that no
+* descriptor is waiting to be commited (NULL).	The Last Pointer points to
+* the last descriptor that was put into the list.  It typically points
+* to the previous descriptor to the one pointed to by the Put Pointer.
+* Comparisons are done between these pointers to determine when the following
+* special conditions exist.
+
+* Single Put And Commit
+*
+* The buffer descriptor is ready to be used by the hardware so it is important
+* for the descriptor to not appear to be waiting to be committed.  The commit
+* pointer is reset when a commit is done indicating there are no descriptors
+* waiting to be committed.  In all cases but this one, the descriptor is
+* changed to cause the hardware to go to the next descriptor after processing
+* this one.  But in this case, this is the last descriptor in the list such
+* that it must not be changed.
+*
+* 3 Or More Puts And Commit
+*
+* A series of 3 or more puts followed by a single commit is different in that
+* only the 1st descriptor put into the list is changed when the commit is done.
+* This requires each put starting on the 3rd to change the previous descriptor
+* so that it allows the hardware to continue to the next descriptor in the list.
+*
+* The 1st Put Following A Commit
+*
+* The commit caused the commit pointer to be NULL indicating that there are no
+* descriptors waiting to be committed.	It is necessary for the next put to set
+* the commit pointer so that a commit must follow the put for the hardware to
+* use the descriptor.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- ------------------------------------------------------
+* 1.00a rpm  02/03/03 Removed the XST_DMA_SG_COUNT_EXCEEDED return code
+*		      from SetPktThreshold.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xdma_channel.h"
+#include "xbasic_types.h"
+#include "xio.h"
+#include "xbuf_descriptor.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XDC_SWCR_SG_ENABLE_MASK 0x80000000UL	/* scatter gather enable */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/* the following macro copies selected fields of a buffer descriptor to another
+ * buffer descriptor, this was provided by the buffer descriptor component but
+ * was moved here since it is only used internally to this component and since
+ * it does not copy all fields
+ */
+#define CopyBufferDescriptor(InstancePtr, DestinationPtr)	   \
+{								   \
+    *((u32 *)DestinationPtr + XBD_CONTROL_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_CONTROL_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_SOURCE_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_SOURCE_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_DESTINATION_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_LENGTH_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_LENGTH_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_STATUS_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_STATUS_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_DEVICE_STATUS_OFFSET) =      \
+	*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET);      \
+    *((u32 *)DestinationPtr + XBD_ID_OFFSET) =		       \
+	*((u32 *)InstancePtr + XBD_ID_OFFSET);		       \
+    *((u32 *)DestinationPtr + XBD_FLAGS_OFFSET) =	       \
+	*((u32 *)InstancePtr + XBD_FLAGS_OFFSET);	       \
+    *((u32 *)DestinationPtr + XBD_RQSTED_LENGTH_OFFSET) =      \
+	*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET);      \
+}
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SgStart
+*
+* DESCRIPTION:
+*
+* This function starts a scatter gather operation for a scatter gather
+* DMA channel.	The first buffer descriptor in the buffer descriptor list
+* will be started with the scatter gather operation.  A scatter gather list
+* should have previously been created for the DMA channel and buffer
+* descriptors put into the scatter gather list such that there are scatter
+* operations ready to be performed.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* A status containing XST_SUCCESS if scatter gather was started successfully
+* for the DMA channel.
+*
+* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
+* been created.
+*
+* A value of XST_DMA_SG_LIST_EMPTY indicates scatter gather was not started
+* because the scatter gather list of the DMA channel does not contain any
+* buffer descriptors that are ready to be processed by the hardware.
+*
+* A value of XST_DMA_SG_IS_STARTED indicates scatter gather was not started
+* because the scatter gather was not stopped, but was already started.
+*
+* A value of XST_DMA_SG_BD_NOT_COMMITTED indicates the buffer descriptor of
+* scatter gather list which was to be started is not committed to the list.
+* This status is more likely if this function is being called from an ISR
+* and non-ISR processing is putting descriptors into the list.
+*
+* A value of XST_DMA_SG_NO_DATA indicates that the buffer descriptor of the
+* scatter gather list which was to be started had already been used by the
+* hardware for a DMA transfer that has been completed.
+*
+* NOTES:
+*
+* It is the responsibility of the caller to get all the buffer descriptors
+* after performing a stop operation and before performing a start operation.
+* If buffer descriptors are not retrieved between stop and start operations,
+* buffer descriptors may be processed by the hardware more than once.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_SgStart(XDmaChannel * InstancePtr)
+{
+	u32 Register;
+	XBufDescriptor *LastDescriptorPtr;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if a scatter gather list has not been created yet, return a status */
+
+	if (InstancePtr->TotalDescriptorCount == 0) {
+		return XST_DMA_SG_NO_LIST;
+	}
+
+	/* if the scatter gather list exists but is empty then return a status */
+
+	if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
+		return XST_DMA_SG_LIST_EMPTY;
+	}
+
+	/* if scatter gather is busy for the DMA channel, return a status because
+	 * restarting it could lose data
+	 */
+
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
+	if (Register & XDC_DMASR_SG_BUSY_MASK) {
+		return XST_DMA_SG_IS_STARTED;
+	}
+
+	/* get the address of the last buffer descriptor which the DMA hardware
+	 * finished processing
+	 */
+	LastDescriptorPtr =
+	    (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
+					XDC_BDA_REG_OFFSET);
+
+	/* setup the first buffer descriptor that will be sent when the scatter
+	 * gather channel is enabled, this is only necessary one time since
+	 * the BDA register of the channel maintains the last buffer descriptor
+	 * processed
+	 */
+	if (LastDescriptorPtr == NULL) {
+		XIo_Out32(InstancePtr->RegBaseAddress + XDC_BDA_REG_OFFSET,
+			  (u32) InstancePtr->GetPtr);
+	} else {
+		XBufDescriptor *NextDescriptorPtr;
+
+		/* get the next descriptor to be started, if the status indicates it
+		 * hasn't already been used by the h/w, then it's OK to start it,
+		 * s/w sets the status of each descriptor to busy and then h/w clears
+		 * the busy when it is complete
+		 */
+		NextDescriptorPtr =
+		    XBufDescriptor_GetNextPtr(LastDescriptorPtr);
+
+		if ((XBufDescriptor_GetStatus(NextDescriptorPtr) &
+		     XDC_DMASR_BUSY_MASK) == 0) {
+			return XST_DMA_SG_NO_DATA;
+		}
+		/* don't start the DMA SG channel if the descriptor to be processed
+		 * by h/w is to be committed by the s/w, this function can be called
+		 * such that it interrupts a thread that was putting into the list
+		 */
+		if (NextDescriptorPtr == InstancePtr->CommitPtr) {
+			return XST_DMA_SG_BD_NOT_COMMITTED;
+		}
+	}
+
+	/* start the scatter gather operation by clearing the stop bit in the
+	 * control register and setting the enable bit in the s/w control register,
+	 * both of these are necessary to cause it to start, right now the order of
+	 * these statements is important, the software control register should be
+	 * set 1st.  The other order can cause the CPU to have a loss of sync
+	 * because it cannot read/write the register while the DMA operation is
+	 * running
+	 */
+
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
+		  Register | XDC_SWCR_SG_ENABLE_MASK);
+
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
+
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET,
+		  Register & ~XDC_DMACR_SG_DISABLE_MASK);
+
+	/* indicate the DMA channel scatter gather operation was started
+	 * successfully
+	 */
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SgStop
+*
+* DESCRIPTION:
+*
+* This function stops a scatter gather operation for a scatter gather
+* DMA channel. This function starts the process of stopping a scatter
+* gather operation that is in progress and waits for the stop to be completed.
+* Since it waits for the operation to stopped before returning, this function
+* could take an amount of time relative to the size of the DMA scatter gather
+* operation which is in progress.  The scatter gather list of the DMA channel
+* is not modified by this function such that starting the scatter gather
+* channel after stopping it will cause it to resume.  This operation is
+* considered to be a graceful stop in that the scatter gather operation
+* completes the current buffer descriptor before stopping.
+*
+* If the interrupt is enabled, an interrupt will be generated when the
+* operation is stopped and the caller is responsible for handling the
+* interrupt.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* BufDescriptorPtr is also a return value which contains a pointer to the
+* buffer descriptor which the scatter gather operation completed when it
+* was stopped.
+*
+* RETURN VALUE:
+*
+* A status containing XST_SUCCESS if scatter gather was stopped successfully
+* for the DMA channel.
+*
+* A value of XST_DMA_SG_IS_STOPPED indicates scatter gather was not stoppped
+* because the scatter gather is not started, but was already stopped.
+*
+* BufDescriptorPtr contains a pointer to the buffer descriptor which was
+* completed when the operation was stopped.
+*
+* NOTES:
+*
+* This function implements a loop which polls the hardware for an infinite
+* amount of time. If the hardware is not operating correctly, this function
+* may never return.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_SgStop(XDmaChannel * InstancePtr,
+		   XBufDescriptor ** BufDescriptorPtr)
+{
+	u32 Register;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufDescriptorPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the contents of the software control register, if scatter gather is not
+	 * enabled (started), then return a status because the disable acknowledge
+	 * would not be generated
+	 */
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
+
+	if ((Register & XDC_SWCR_SG_ENABLE_MASK) == 0) {
+		return XST_DMA_SG_IS_STOPPED;
+	}
+
+	/* Ensure the interrupt status for the scatter gather is cleared such
+	 * that this function will wait til the disable has occurred, writing
+	 * a 1 to only that bit in the register will clear only it
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
+		  XDC_IXR_SG_DISABLE_ACK_MASK);
+
+	/* disable scatter gather by writing to the software control register
+	 * without modifying any other bits of the register
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
+		  Register & ~XDC_SWCR_SG_ENABLE_MASK);
+
+	/* scatter gather does not disable immediately, but after the current
+	 * buffer descriptor is complete, so wait for the DMA channel to indicate
+	 * the disable is complete
+	 */
+	do {
+		Register =
+		    XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
+	} while ((Register & XDC_IXR_SG_DISABLE_ACK_MASK) == 0);
+
+	/* Ensure the interrupt status for the scatter gather disable is cleared,
+	 * writing a 1 to only that bit in the register will clear only it
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
+		  XDC_IXR_SG_DISABLE_ACK_MASK);
+
+	/* set the specified buffer descriptor pointer to point to the buffer
+	 * descriptor that the scatter gather DMA channel was processing
+	 */
+	*BufDescriptorPtr =
+	    (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
+					XDC_BDA_REG_OFFSET);
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_CreateSgList
+*
+* DESCRIPTION:
+*
+* This function creates a scatter gather list in the DMA channel.  A scatter
+* gather list consists of a list of buffer descriptors that are available to
+* be used for scatter gather operations.  Buffer descriptors are put into the
+* list to request a scatter gather operation to be performed.
+*
+* A number of buffer descriptors are created from the specified memory and put
+* into a buffer descriptor list as empty buffer descriptors. This function must
+* be called before non-empty buffer descriptors may be put into the DMA channel
+* to request scatter gather operations.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* MemoryPtr contains a pointer to the memory which is to be used for buffer
+* descriptors and must not be cached.
+*
+* ByteCount contains the number of bytes for the specified memory to be used
+* for buffer descriptors.
+*
+* RETURN VALUE:
+*
+* A status contains XST_SUCCESS if the scatter gather list was successfully
+* created.
+*
+* A value of XST_DMA_SG_LIST_EXISTS indicates that the scatter gather list
+* was not created because the list has already been created.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
+			 u32 * MemoryPtr, u32 ByteCount)
+{
+	XBufDescriptor *BufferDescriptorPtr = (XBufDescriptor *) MemoryPtr;
+	XBufDescriptor *PreviousDescriptorPtr = NULL;
+	XBufDescriptor *StartOfListPtr = BufferDescriptorPtr;
+	u32 UsedByteCount;
+
+	/* assert to verify valid input arguments, alignment for those
+	 * arguments that have alignment restrictions, and at least enough
+	 * memory for one buffer descriptor
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(MemoryPtr != NULL);
+	XASSERT_NONVOID(((u32) MemoryPtr & 3) == 0);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(ByteCount >= sizeof (XBufDescriptor));
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if the scatter gather list has already been created, then return
+	 * with a status
+	 */
+	if (InstancePtr->TotalDescriptorCount != 0) {
+		return XST_DMA_SG_LIST_EXISTS;
+	}
+
+	/* loop thru the specified memory block and create as many buffer
+	 * descriptors as possible putting each into the list which is
+	 * implemented as a ring buffer, make sure not to use any memory which
+	 * is not large enough for a complete buffer descriptor
+	 */
+	UsedByteCount = 0;
+	while ((UsedByteCount + sizeof (XBufDescriptor)) <= ByteCount) {
+		/* setup a pointer to the next buffer descriptor in the memory and
+		 * update # of used bytes to know when all of memory is used
+		 */
+		BufferDescriptorPtr = (XBufDescriptor *) ((u32) MemoryPtr +
+							  UsedByteCount);
+
+		/* initialize the new buffer descriptor such that it doesn't contain
+		 * garbage which could be used by the DMA hardware
+		 */
+		XBufDescriptor_Initialize(BufferDescriptorPtr);
+
+		/* if this is not the first buffer descriptor to be created,
+		 * then link it to the last created buffer descriptor
+		 */
+		if (PreviousDescriptorPtr != NULL) {
+			XBufDescriptor_SetNextPtr(PreviousDescriptorPtr,
+						  BufferDescriptorPtr);
+		}
+
+		/* always keep a pointer to the last created buffer descriptor such
+		 * that they can be linked together in the ring buffer
+		 */
+		PreviousDescriptorPtr = BufferDescriptorPtr;
+
+		/* keep a count of the number of descriptors in the list to allow
+		 * error processing to be performed
+		 */
+		InstancePtr->TotalDescriptorCount++;
+
+		UsedByteCount += sizeof (XBufDescriptor);
+	}
+
+	/* connect the last buffer descriptor created and inserted in the list
+	 * to the first such that a ring buffer is created
+	 */
+	XBufDescriptor_SetNextPtr(BufferDescriptorPtr, StartOfListPtr);
+
+	/* initialize the ring buffer to indicate that there are no
+	 * buffer descriptors in the list which point to valid data buffers
+	 */
+	InstancePtr->PutPtr = BufferDescriptorPtr;
+	InstancePtr->GetPtr = BufferDescriptorPtr;
+	InstancePtr->CommitPtr = NULL;
+	InstancePtr->LastPtr = BufferDescriptorPtr;
+	InstancePtr->ActiveDescriptorCount = 0;
+
+	/* indicate the scatter gather list was successfully created */
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_IsSgListEmpty
+*
+* DESCRIPTION:
+*
+* This function determines if the scatter gather list of a DMA channel is
+* empty with regard to buffer descriptors which are pointing to buffers to be
+* used for scatter gather operations.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* A value of TRUE if the scatter gather list is empty, otherwise a value of
+* FALSE.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr)
+{
+	/* assert to verify valid input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if the number of descriptors which are being used in the list is zero
+	 * then the list is empty
+	 */
+	return (InstancePtr->ActiveDescriptorCount == 0);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_PutDescriptor
+*
+* DESCRIPTION:
+*
+* This function puts a buffer descriptor into the DMA channel scatter
+* gather list. A DMA channel maintains a list of buffer descriptors which are
+* to be processed.  This function puts the specified buffer descriptor
+* at the next location in the list.  Note that since the list is already intact,
+* the information in the parameter is copied into the list (rather than modify
+* list pointers on the fly).
+*
+* After buffer descriptors are put into the list, they must also be committed
+* by calling another function.	This allows multiple buffer descriptors which
+* span a single packet to be put into the list while preventing the hardware
+* from starting the first buffer descriptor of the packet.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* BufferDescriptorPtr is a pointer to the buffer descriptor to be put into
+* the next available location of the scatter gather list.
+*
+* RETURN VALUE:
+*
+* A status which indicates XST_SUCCESS if the buffer descriptor was
+* successfully put into the scatter gather list.
+*
+* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
+* been created.
+*
+* A value of XST_DMA_SG_LIST_FULL indicates the buffer descriptor was not
+* put into the list because the list was full.
+*
+* A value of XST_DMA_SG_BD_LOCKED indicates the buffer descriptor was not
+* put into the list because the buffer descriptor in the list which is to
+* be overwritten was locked.  A locked buffer descriptor indicates the higher
+* layered software is still using the buffer descriptor.
+*
+* NOTES:
+*
+* It is necessary to create a scatter gather list for a DMA channel before
+* putting buffer descriptors into it.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
+			  XBufDescriptor * BufferDescriptorPtr)
+{
+	u32 Control;
+
+	/* assert to verify valid input arguments and alignment for those
+	 * arguments that have alignment restrictions
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufferDescriptorPtr != NULL);
+	XASSERT_NONVOID(((u32) BufferDescriptorPtr & 3) == 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if a scatter gather list has not been created yet, return a status */
+
+	if (InstancePtr->TotalDescriptorCount == 0) {
+		return XST_DMA_SG_NO_LIST;
+	}
+
+	/* if the list is full because all descriptors are pointing to valid
+	 * buffers, then indicate an error, this code assumes no list or an
+	 * empty list is detected above
+	 */
+	if (InstancePtr->ActiveDescriptorCount ==
+	    InstancePtr->TotalDescriptorCount) {
+		return XST_DMA_SG_LIST_FULL;
+	}
+
+	/* if the buffer descriptor in the list which is to be overwritten is
+	 * locked, then don't overwrite it and return a status
+	 */
+	if (XBufDescriptor_IsLocked(InstancePtr->PutPtr)) {
+		return XST_DMA_SG_BD_LOCKED;
+	}
+
+	/* set the scatter gather stop bit in the control word of the descriptor
+	 * to cause the h/w to stop after it processes this descriptor since it
+	 * will be the last in the list
+	 */
+	Control = XBufDescriptor_GetControl(BufferDescriptorPtr);
+	XBufDescriptor_SetControl(BufferDescriptorPtr,
+				  Control | XDC_DMACR_SG_DISABLE_MASK);
+
+	/* set both statuses in the descriptor so we tell if they are updated with
+	 * the status of the transfer, the hardware should change the busy in the
+	 * DMA status to be false when it completes
+	 */
+	XBufDescriptor_SetStatus(BufferDescriptorPtr, XDC_DMASR_BUSY_MASK);
+	XBufDescriptor_SetDeviceStatus(BufferDescriptorPtr, 0);
+
+	/* copy the descriptor into the next position in the list so it's ready to
+	 * be used by the h/w, this assumes the descriptor in the list prior to this
+	 * one still has the stop bit in the control word set such that the h/w
+	 * use this one yet
+	 */
+	CopyBufferDescriptor(BufferDescriptorPtr, InstancePtr->PutPtr);
+
+	/* only the last in the list and the one to be committed have scatter gather
+	 * disabled in the control word, a commit requires only one descriptor
+	 * to be changed, when # of descriptors to commit > 2 all others except the
+	 * 1st and last have scatter gather enabled
+	 */
+	if ((InstancePtr->CommitPtr != InstancePtr->LastPtr) &&
+	    (InstancePtr->CommitPtr != NULL)) {
+		Control = XBufDescriptor_GetControl(InstancePtr->LastPtr);
+		XBufDescriptor_SetControl(InstancePtr->LastPtr,
+					  Control & ~XDC_DMACR_SG_DISABLE_MASK);
+	}
+
+	/* update the list data based upon putting a descriptor into the list,
+	 * these operations must be last
+	 */
+	InstancePtr->ActiveDescriptorCount++;
+
+	/* only update the commit pointer if it is not already active, this allows
+	 * it to be deactivated after every commit such that a single descriptor
+	 * which is committed does not appear to be waiting to be committed
+	 */
+	if (InstancePtr->CommitPtr == NULL) {
+		InstancePtr->CommitPtr = InstancePtr->LastPtr;
+	}
+
+	/* these updates MUST BE LAST after the commit pointer update in order for
+	 * the commit pointer to track the correct descriptor to be committed
+	 */
+	InstancePtr->LastPtr = InstancePtr->PutPtr;
+	InstancePtr->PutPtr = XBufDescriptor_GetNextPtr(InstancePtr->PutPtr);
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_CommitPuts
+*
+* DESCRIPTION:
+*
+* This function commits the buffer descriptors which have been put into the
+* scatter list for the DMA channel since the last commit operation was
+* performed.  This enables the calling functions to put several buffer
+* descriptors into the list (e.g.,a packet's worth) before allowing the scatter
+* gather operations to start.  This prevents the DMA channel hardware from
+* starting to use the buffer descriptors in the list before they are ready
+* to be used (multiple buffer descriptors for a single packet).
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* A status indicating XST_SUCCESS if the buffer descriptors of the list were
+* successfully committed.
+*
+* A value of XST_DMA_SG_NOTHING_TO_COMMIT indicates that the buffer descriptors
+* were not committed because there was nothing to commit in the list.  All the
+* buffer descriptors which are in the list are commited.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_CommitPuts(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if the buffer descriptor to be committed is already committed or
+	 * the list is empty (none have been put in), then indicate an error
+	 */
+	if ((InstancePtr->CommitPtr == NULL) ||
+	    XDmaChannel_IsSgListEmpty(InstancePtr)) {
+		return XST_DMA_SG_NOTHING_TO_COMMIT;
+	}
+
+	/* last descriptor in the list must have scatter gather disabled so the end
+	 * of the list is hit by h/w, if descriptor to commit is not last in list,
+	 * commit descriptors by enabling scatter gather in the descriptor
+	 */
+	if (InstancePtr->CommitPtr != InstancePtr->LastPtr) {
+		u32 Control;
+
+		Control = XBufDescriptor_GetControl(InstancePtr->CommitPtr);
+		XBufDescriptor_SetControl(InstancePtr->CommitPtr, Control &
+					  ~XDC_DMACR_SG_DISABLE_MASK);
+	}
+	/* Update the commit pointer to indicate that there is nothing to be
+	 * committed, this state is used by start processing to know that the
+	 * buffer descriptor to start is not waiting to be committed
+	 */
+	InstancePtr->CommitPtr = NULL;
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetDescriptor
+*
+* DESCRIPTION:
+*
+* This function gets a buffer descriptor from the scatter gather list of the
+* DMA channel. The buffer descriptor is retrieved from the scatter gather list
+* and the scatter gather list is updated to not include the retrieved buffer
+* descriptor.  This is typically done after a scatter gather operation
+* completes indicating that a data buffer has been successfully sent or data
+* has been received into the data buffer. The purpose of this function is to
+* allow the device using the scatter gather operation to get the results of the
+* operation.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* BufDescriptorPtr is a pointer to a pointer to the buffer descriptor which
+* was retrieved from the list.	The buffer descriptor is not really removed
+* from the list, but it is changed to a state such that the hardware will not
+* use it again until it is put into the scatter gather list of the DMA channel.
+*
+* RETURN VALUE:
+*
+* A status indicating XST_SUCCESS if a buffer descriptor was retrieved from
+* the scatter gather list of the DMA channel.
+*
+* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
+* been created.
+*
+* A value of XST_DMA_SG_LIST_EMPTY indicates no buffer descriptor was
+* retrieved from the list because there are no buffer descriptors to be
+* processed in the list.
+*
+* BufDescriptorPtr is updated to point to the buffer descriptor which was
+* retrieved from the list if the status indicates success.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
+			  XBufDescriptor ** BufDescriptorPtr)
+{
+	u32 Control;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufDescriptorPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if a scatter gather list has not been created yet, return a status */
+
+	if (InstancePtr->TotalDescriptorCount == 0) {
+		return XST_DMA_SG_NO_LIST;
+	}
+
+	/* if the buffer descriptor list is empty, then indicate an error */
+
+	if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
+		return XST_DMA_SG_LIST_EMPTY;
+	}
+
+	/* retrieve the next buffer descriptor which is ready to be processed from
+	 * the buffer descriptor list for the DMA channel, set the control word
+	 * such that hardware will stop after the descriptor has been processed
+	 */
+	Control = XBufDescriptor_GetControl(InstancePtr->GetPtr);
+	XBufDescriptor_SetControl(InstancePtr->GetPtr,
+				  Control | XDC_DMACR_SG_DISABLE_MASK);
+
+	/* set the input argument, which is also an output, to point to the
+	 * buffer descriptor which is to be retrieved from the list
+	 */
+	*BufDescriptorPtr = InstancePtr->GetPtr;
+
+	/* update the pointer of the DMA channel to reflect the buffer descriptor
+	 * was retrieved from the list by setting it to the next buffer descriptor
+	 * in the list and indicate one less descriptor in the list now
+	 */
+	InstancePtr->GetPtr = XBufDescriptor_GetNextPtr(InstancePtr->GetPtr);
+	InstancePtr->ActiveDescriptorCount--;
+
+	return XST_SUCCESS;
+}
+
+/*********************** Interrupt Collescing Functions **********************/
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetPktCount
+*
+* DESCRIPTION:
+*
+* This function returns the value of the unserviced packet count register of
+* the DMA channel.  This count represents the number of packets that have been
+* sent or received by the hardware, but not processed by software.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* The unserviced packet counter register contents for the DMA channel.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetPktCount(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the unserviced packet count from the register and return it */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_DecrementPktCount
+*
+* DESCRIPTION:
+*
+* This function decrements the value of the unserviced packet count register.
+* This informs the hardware that the software has processed a packet.  The
+* unserviced packet count register may only be decremented by one in the
+* hardware.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr)
+{
+	u32 Register;
+
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* if the unserviced packet count register can be decremented (rather
+	 * than rolling over) decrement it by writing a 1 to the register,
+	 * this is the only valid write to the register as it serves as an
+	 * acknowledge that a packet was handled by the software
+	 */
+	Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
+	if (Register > 0) {
+		XIo_Out32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET,
+			  1UL);
+	}
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetPktThreshold
+*
+* DESCRIPTION:
+*
+* This function sets the value of the packet count threshold register of the
+* DMA channel.	It reflects the number of packets that must be sent or
+* received before generating an interrupt.  This value helps implement
+* a concept called "interrupt coalescing", which is used to reduce the number
+* of interrupts from devices with high data rates.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* Threshold is the value that is written to the threshold register of the
+* DMA channel.
+*
+* RETURN VALUE:
+*
+* A status containing XST_SUCCESS if the packet count threshold was
+* successfully set.
+*
+* NOTES:
+*
+* The packet threshold could be set to larger than the number of descriptors
+* allocated to the DMA channel. In this case, the wait bound will take over
+* and always indicate data arrival. There was a check in this function that
+* returned an error if the treshold was larger than the number of descriptors,
+* but that was removed because users would then have to set the threshold
+* only after they set descriptor space, which is an order dependency that
+* caused confustion.
+*
+******************************************************************************/
+XStatus
+XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold)
+{
+	/* assert to verify input arguments, don't assert the threshold since
+	 * it's range is unknown
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the packet count threshold in the register such that an interrupt
+	 * may be generated, if enabled, when the packet count threshold is
+	 * reached or exceeded
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET,
+		  (u32) Threshold);
+
+	/* indicate the packet count threshold was successfully set */
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetPktThreshold
+*
+* DESCRIPTION:
+*
+* This function gets the value of the packet count threshold register of the
+* DMA channel.	This value reflects the number of packets that must be sent or
+* received before generating an interrupt.  This value helps implement a concept
+* called "interrupt coalescing", which is used to reduce the number of
+* interrupts from devices with high data rates.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* The packet threshold register contents for the DMA channel and is a value in
+* the range 0 - 1023.  A value of 0 indicates the packet wait bound timer is
+* disabled.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u8
+XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the packet count threshold from the register and return it,
+	 * since only 8 bits are used, cast it to return only those bits */
+
+	return (u8) XIo_In32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_SetPktWaitBound
+*
+* DESCRIPTION:
+*
+* This function sets the value of the packet wait bound register of the
+* DMA channel.	This value reflects the timer value used to trigger an
+* interrupt when not enough packets have been received to reach the packet
+* count threshold.
+*
+* The timer is in millisecond units with +/- 33% accuracy.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* WaitBound is the value, in milliseconds, to be stored in the wait bound
+* register of the DMA channel and is a value in the range 0  - 1023.  A value
+* of 0 disables the packet wait bound timer.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+void
+XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(WaitBound < 1024);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* set the packet wait bound in the register such that interrupt may be
+	 * generated, if enabled, when packets have not been handled for a specific
+	 * amount of time
+	 */
+	XIo_Out32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET, WaitBound);
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XDmaChannel_GetPktWaitBound
+*
+* DESCRIPTION:
+*
+* This function gets the value of the packet wait bound register of the
+* DMA channel.	This value contains the timer value used to trigger an
+* interrupt when not enough packets have been received to reach the packet
+* count threshold.
+*
+* The timer is in millisecond units with +/- 33% accuracy.
+*
+* ARGUMENTS:
+*
+* InstancePtr contains a pointer to the DMA channel to operate on.  The DMA
+* channel should be configured to use scatter gather in order for this function
+* to be called.
+*
+* RETURN VALUE:
+*
+* The packet wait bound register contents for the DMA channel.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+u32
+XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the packet wait bound from the register and return it */
+
+	return XIo_In32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET);
+}
diff --git a/board/xilinx/common/xio.h b/board/xilinx/common/xio.h
new file mode 100755
index 0000000..5bb09c8
--- /dev/null
+++ b/board/xilinx/common/xio.h
@@ -0,0 +1,81 @@
+/*
+ * xio.h
+ *
+ * Defines XIo functions for Xilinx OCP in terms of Linux primitives
+ *
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+ *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef XIO_H
+#define XIO_H
+
+#include "xbasic_types.h"
+#include <asm/io.h>
+
+typedef u32 XIo_Address;
+
+extern inline u8
+XIo_In8(XIo_Address InAddress)
+{
+	return (u8) in_8((volatile unsigned char *) InAddress);
+}
+extern inline u16
+XIo_In16(XIo_Address InAddress)
+{
+	return (u16) in_be16((volatile unsigned short *) InAddress);
+}
+extern inline u32
+XIo_In32(XIo_Address InAddress)
+{
+	return (u32) in_be32((volatile unsigned *) InAddress);
+}
+extern inline void
+XIo_Out8(XIo_Address OutAddress, u8 Value)
+{
+	out_8((volatile unsigned char *) OutAddress, Value);
+}
+extern inline void
+XIo_Out16(XIo_Address OutAddress, u16 Value)
+{
+	out_be16((volatile unsigned short *) OutAddress, Value);
+}
+extern inline void
+XIo_Out32(XIo_Address OutAddress, u32 Value)
+{
+	out_be32((volatile unsigned *) OutAddress, Value);
+}
+
+#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s)))
+#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s)))
+#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s)))
+#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s)))
+
+#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s)))
+#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s)))
+#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s)))
+#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s)))
+
+#endif				/* XIO_H */
diff --git a/board/xilinx/common/xipif_v1_23_b.c b/board/xilinx/common/xipif_v1_23_b.c
new file mode 100755
index 0000000..c7311ab
--- /dev/null
+++ b/board/xilinx/common/xipif_v1_23_b.c
@@ -0,0 +1,331 @@
+/* $Id: xipif_v1_23_b.c,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
+/******************************************************************************
+*
+*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*       FOR A PARTICULAR PURPOSE.
+*
+*       (c) Copyright 2002 Xilinx Inc.
+*       All rights reserved.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* FILENAME:
+*
+* xipif.c
+*
+* DESCRIPTION:
+*
+* This file contains the implementation of the XIpIf component. The
+* XIpIf component encapsulates the IPIF, which is the standard interface
+* that IP must adhere to when connecting to a bus.  The purpose of this
+* component is to encapsulate the IPIF processing such that maintainability
+* is increased.  This component does not provide a lot of abstraction from
+* from the details of the IPIF as it is considered a building block for
+* device drivers.  A device driver designer must be familiar with the
+* details of the IPIF hardware to use this component.
+*
+* The IPIF hardware provides a building block for all hardware devices such
+* that each device does not need to reimplement these building blocks. The
+* IPIF contains other building blocks, such as FIFOs and DMA channels, which
+* are also common to many devices.  These blocks are implemented as separate
+* hardware blocks and instantiated within the IPIF.  The primary hardware of
+* the IPIF which is implemented by this software component is the interrupt
+* architecture.  Since there are many blocks of a device which may generate
+* interrupts, all the interrupt processing is contained in the common part
+* of the device, the IPIF.  This interrupt processing is for the device level
+* only and does not include any processing for the interrupt controller.
+*
+* A device is a mechanism such as an Ethernet MAC.  The device is made
+* up of several parts which include an IPIF and the IP.  The IPIF contains most
+* of the device infrastructure which is common to all devices, such as
+* interrupt processing, DMA channels, and FIFOs.  The infrastructure may also
+* be referred to as IPIF internal blocks since they are part of the IPIF and
+* are separate blocks that can be selected based upon the needs of the device.
+* The IP of the device is the logic that is unique to the device and interfaces
+* to the IPIF of the device.
+*
+* In general, there are two levels of registers within the IPIF.  The first
+* level, referred to as the device level, contains registers which are for the
+* entire device.  The second level, referred to as the IP level, contains
+* registers which are specific to the IP of the device.  The two levels of
+* registers are designed to be hierarchical such that the device level is
+* is a more general register set above the more specific registers of the IP.
+* The IP level of registers provides functionality which is typically common
+* across all devices and allows IP designers to focus on the unique aspects
+* of the IP.
+*
+* The interrupt registers of the IPIF are parameterizable such that the only
+* the number of bits necessary for the device are implemented. The functions
+* of this component do not attempt to validate that the passed in arguments are
+* valid based upon the number of implemented bits.  This is necessary to
+* maintain the level of performance required for the common components.  Bits
+* of the registers are assigned starting at the least significant bit of the
+* registers.
+*
+* Critical Sections
+*
+* It is the responsibility of the device driver designer to use critical
+* sections as necessary when calling functions of the IPIF.  This component
+* does not use critical sections and it does access registers using
+* read-modify-write operations.  Calls to IPIF functions from a main thread
+* and from an interrupt context could produce unpredictable behavior such that
+* the caller must provide the appropriate critical sections.
+*
+* Mutual Exclusion
+*
+* The functions of the IPIF are not thread safe such that the caller of all
+* functions is responsible for ensuring mutual exclusion for an IPIF.  Mutual
+* exclusion across multiple IPIF components is not necessary.
+*
+* NOTES:
+*
+* None.
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.23b jhl  02/27/01 Repartioned to reduce size
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xipif_v1_23_b.h"
+#include "xio.h"
+
+/************************** Constant Definitions *****************************/
+
+/* the following constant is used to generate bit masks for register testing
+ * in the self test functions, it defines the starting bit mask that is to be
+ * shifted from the LSB to MSB in creating a register test mask
+ */
+#define XIIF_V123B_FIRST_BIT_MASK     1UL
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static XStatus IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth);
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* XIpIf_SelfTest
+*
+* DESCRIPTION:
+*
+* This function performs a self test on the specified IPIF component.  Many
+* of the registers in the IPIF are tested to ensure proper operation.  This
+* function is destructive because the IPIF is reset at the start of the test
+* and at the end of the test to ensure predictable results.  The IPIF reset
+* also resets the entire device that uses the IPIF.  This function exits with
+* all interrupts for the device disabled.
+*
+* ARGUMENTS:
+*
+* InstancePtr points to the XIpIf to operate on.
+*
+* DeviceRegistersWidth contains the number of bits in the device interrupt
+* registers. The hardware is parameterizable such that only the number of bits
+* necessary to support a device are implemented.  This value must be between 0
+* and 32 with 0 indicating there are no device interrupt registers used.
+*
+* IpRegistersWidth contains the number of bits in the IP interrupt registers
+* of the device.  The hardware is parameterizable such that only the number of
+* bits necessary to support a device are implemented.  This value must be
+* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
+*
+* RETURN VALUE:
+*
+* A value of XST_SUCCESS indicates the test was successful with no errors.
+* Any one of the following error values may also be returned.
+*
+*   XST_IPIF_RESET_REGISTER_ERROR       The value of a register at reset was
+*                                       not valid
+*   XST_IPIF_IP_STATUS_ERROR            A write to the IP interrupt status
+*                                       register did not read back correctly
+*   XST_IPIF_IP_ACK_ERROR               One or more bits in the IP interrupt
+*                                       status register did not reset when acked
+*   XST_IPIF_IP_ENABLE_ERROR            The IP interrupt enable register
+*                                       did not read back correctly based upon
+*                                       what was written to it
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+
+/* the following constant defines the maximum number of bits which may be
+ * used in the registers at the device and IP levels, this is based upon the
+ * number of bits available in the registers
+ */
+#define XIIF_V123B_MAX_REG_BIT_COUNT 32
+
+XStatus
+XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth)
+{
+	XStatus Status;
+
+	/* assert to verify arguments are valid */
+
+	XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT);
+
+	/* reset the IPIF such that it's in a known state before the test
+	 * and interrupts are globally disabled
+	 */
+	XIIF_V123B_RESET(RegBaseAddress);
+
+	/* perform the self test on the IP interrupt registers, if
+	 * it is not successful exit with the status
+	 */
+	Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	/* reset the IPIF such that it's in a known state before exiting test */
+
+	XIIF_V123B_RESET(RegBaseAddress);
+
+	/* reaching this point means there were no errors, return success */
+
+	return XST_SUCCESS;
+}
+
+/******************************************************************************
+*
+* FUNCTION:
+*
+* IpIntrSelfTest
+*
+* DESCRIPTION:
+*
+* Perform a self test on the IP interrupt registers of the IPIF. This
+* function modifies registers of the IPIF such that they are not guaranteed
+* to be in the same state when it returns.  Any bits in the IP interrupt
+* status register which are set are assumed to be set by default after a reset
+* and are not tested in the test.
+*
+* ARGUMENTS:
+*
+* InstancePtr points to the XIpIf to operate on.
+*
+* IpRegistersWidth contains the number of bits in the IP interrupt registers
+* of the device.  The hardware is parameterizable such that only the number of
+* bits necessary to support a device are implemented.  This value must be
+* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
+*
+* RETURN VALUE:
+*
+* A status indicating XST_SUCCESS if the test was successful.  Otherwise, one
+* of the following values is returned.
+*
+*   XST_IPIF_RESET_REGISTER_ERROR       The value of a register at reset was
+*                                       not valid
+*   XST_IPIF_IP_STATUS_ERROR            A write to the IP interrupt status
+*                                       register did not read back correctly
+*   XST_IPIF_IP_ACK_ERROR               One or more bits in the IP status
+*                                       register did not reset when acked
+*   XST_IPIF_IP_ENABLE_ERROR            The IP interrupt enable register
+*                                       did not read back correctly based upon
+*                                       what was written to it
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+static XStatus
+IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth)
+{
+	/* ensure that the IP interrupt interrupt enable register is  zero
+	 * as it should be at reset, the interrupt status is dependent upon the
+	 * IP such that it's reset value is not known
+	 */
+	if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
+		return XST_IPIF_RESET_REGISTER_ERROR;
+	}
+
+	/* if there are any used IP interrupts, then test all of the interrupt
+	 * bits in all testable registers
+	 */
+	if (IpRegistersWidth > 0) {
+		u32 BitCount;
+		u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK;
+		u32 Mask = XIIF_V123B_FIRST_BIT_MASK;	/* bits assigned MSB to LSB */
+		u32 InterruptStatus;
+
+		/* generate the register masks to be used for IP register tests, the
+		 * number of bits supported by the hardware is parameterizable such
+		 * that only that number of bits are implemented in the registers, the
+		 * bits are allocated starting at the MSB of the registers
+		 */
+		for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) {
+			Mask = Mask << 1;
+			IpInterruptMask |= Mask;
+		}
+
+		/* get the current IP interrupt status register contents, any bits
+		 * already set must default to 1 at reset in the device and these
+		 * bits can't be tested in the following test, remove these bits from
+		 * the mask that was generated for the test
+		 */
+		InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
+		IpInterruptMask &= ~InterruptStatus;
+
+		/* set the bits in the device status register and verify them by reading
+		 * the register again, all bits of the register are latched
+		 */
+		XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
+		InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
+		if ((InterruptStatus & IpInterruptMask) != IpInterruptMask)
+		{
+			return XST_IPIF_IP_STATUS_ERROR;
+		}
+
+		/* test to ensure that the bits set in the IP interrupt status register
+		 * can be cleared by acknowledging them in the IP interrupt status
+		 * register then read it again and verify it was cleared
+		 */
+		XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
+		InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
+		if ((InterruptStatus & IpInterruptMask) != 0) {
+			return XST_IPIF_IP_ACK_ERROR;
+		}
+
+		/* set the IP interrupt enable set register and then read the IP
+		 * interrupt enable register and verify the interrupts were enabled
+		 */
+		XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask);
+		if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) {
+			return XST_IPIF_IP_ENABLE_ERROR;
+		}
+
+		/* clear the IP interrupt enable register and then read the
+		 * IP interrupt enable register and verify the interrupts were disabled
+		 */
+		XIIF_V123B_WRITE_IIER(RegBaseAddress, 0);
+		if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
+			return XST_IPIF_IP_ENABLE_ERROR;
+		}
+	}
+	return XST_SUCCESS;
+}
diff --git a/board/xilinx/common/xipif_v1_23_b.h b/board/xilinx/common/xipif_v1_23_b.h
new file mode 100755
index 0000000..3ce1fff
--- /dev/null
+++ b/board/xilinx/common/xipif_v1_23_b.h
@@ -0,0 +1,746 @@
+/* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
+/******************************************************************************
+*
+*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*	FOR A PARTICULAR PURPOSE.
+*
+*	(c) Copyright 2002 Xilinx Inc.
+*	All rights reserved.
+*
+******************************************************************************/
+/******************************************************************************
+*
+* FILENAME:
+*
+* xipif.h
+*
+* DESCRIPTION:
+*
+* The XIpIf component encapsulates the IPIF, which is the standard interface
+* that IP must adhere to when connecting to a bus.  The purpose of this
+* component is to encapsulate the IPIF processing such that maintainability
+* is increased.	 This component does not provide a lot of abstraction from
+* from the details of the IPIF as it is considered a building block for
+* device drivers.  A device driver designer must be familiar with the
+* details of the IPIF hardware to use this component.
+*
+* The IPIF hardware provides a building block for all hardware devices such
+* that each device does not need to reimplement these building blocks. The
+* IPIF contains other building blocks, such as FIFOs and DMA channels, which
+* are also common to many devices.  These blocks are implemented as separate
+* hardware blocks and instantiated within the IPIF.  The primary hardware of
+* the IPIF which is implemented by this software component is the interrupt
+* architecture.	 Since there are many blocks of a device which may generate
+* interrupts, all the interrupt processing is contained in the common part
+* of the device, the IPIF.  This interrupt processing is for the device level
+* only and does not include any processing for the interrupt controller.
+*
+* A device is a mechanism such as an Ethernet MAC.  The device is made
+* up of several parts which include an IPIF and the IP.	 The IPIF contains most
+* of the device infrastructure which is common to all devices, such as
+* interrupt processing, DMA channels, and FIFOs.  The infrastructure may also
+* be referred to as IPIF internal blocks since they are part of the IPIF and
+* are separate blocks that can be selected based upon the needs of the device.
+* The IP of the device is the logic that is unique to the device and interfaces
+* to the IPIF of the device.
+*
+* In general, there are two levels of registers within the IPIF.  The first
+* level, referred to as the device level, contains registers which are for the
+* entire device.  The second level, referred to as the IP level, contains
+* registers which are specific to the IP of the device.	 The two levels of
+* registers are designed to be hierarchical such that the device level is
+* is a more general register set above the more specific registers of the IP.
+* The IP level of registers provides functionality which is typically common
+* across all devices and allows IP designers to focus on the unique aspects
+* of the IP.
+*
+* Critical Sections
+*
+* It is the responsibility of the device driver designer to use critical
+* sections as necessary when calling functions of the IPIF.  This component
+* does not use critical sections and it does access registers using
+* read-modify-write operations.	 Calls to IPIF functions from a main thread
+* and from an interrupt context could produce unpredictable behavior such that
+* the caller must provide the appropriate critical sections.
+*
+* Mutual Exclusion
+*
+* The functions of the IPIF are not thread safe such that the caller of all
+* functions is responsible for ensuring mutual exclusion for an IPIF.  Mutual
+* exclusion across multiple IPIF components is not necessary.
+*
+* NOTES:
+*
+* None.
+*
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.23b jhl  02/27/01 Repartioned to minimize size
+*
+******************************************************************************/
+
+#ifndef XIPIF_H			/* prevent circular inclusions */
+#define XIPIF_H			/* by using protection macros */
+
+/***************************** Include Files *********************************/
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xversion.h"
+
+/************************** Constant Definitions *****************************/
+
+/* the following constants define the register offsets for the registers of the
+ * IPIF, there are some holes in the memory map for reserved addresses to allow
+ * other registers to be added and still match the memory map of the interrupt
+ * controller registers
+ */
+#define XIIF_V123B_DISR_OFFSET	   0UL	/* device interrupt status register */
+#define XIIF_V123B_DIPR_OFFSET	   4UL	/* device interrupt pending register */
+#define XIIF_V123B_DIER_OFFSET	   8UL	/* device interrupt enable register */
+#define XIIF_V123B_DIIR_OFFSET	   24UL /* device interrupt ID register */
+#define XIIF_V123B_DGIER_OFFSET	   28UL /* device global interrupt enable reg */
+#define XIIF_V123B_IISR_OFFSET	   32UL /* IP interrupt status register */
+#define XIIF_V123B_IIER_OFFSET	   40UL /* IP interrupt enable register */
+#define XIIF_V123B_RESETR_OFFSET   64UL /* reset register */
+
+#define XIIF_V123B_RESET_MASK		  0xAUL
+
+/* the following constant is used for the device global interrupt enable
+ * register, to enable all interrupts for the device, this is the only bit
+ * in the register
+ */
+#define XIIF_V123B_GINTR_ENABLE_MASK	  0x80000000UL
+
+/* the following constants contain the masks to identify each internal IPIF
+ * condition in the device registers of the IPIF, interrupts are assigned
+ * in the register from LSB to the MSB
+ */
+#define XIIF_V123B_ERROR_MASK		  1UL	/* LSB of the register */
+
+/* The following constants contain interrupt IDs which identify each internal
+ * IPIF condition, this value must correlate with the mask constant for the
+ * error
+ */
+#define XIIF_V123B_ERROR_INTERRUPT_ID	  0	/* interrupt bit #, (LSB = 0) */
+#define XIIF_V123B_NO_INTERRUPT_ID	  128	/* no interrupts are pending */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_RESET
+*
+* DESCRIPTION:
+*
+* Reset the IPIF component and hardware.  This is a destructive operation that
+* could cause the loss of data since resetting the IPIF of a device also
+* resets the device using the IPIF and any blocks, such as FIFOs or DMA
+* channels, within the IPIF.  All registers of the IPIF will contain their
+* reset value when this function returns.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+
+/* the following constant is used in the reset register to cause the IPIF to
+ * reset
+ */
+#define XIIF_V123B_RESET(RegBaseAddress) \
+    XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_WRITE_DISR
+*
+* DESCRIPTION:
+*
+* This function sets the device interrupt status register to the value.
+* This register indicates the status of interrupt sources for a device
+* which contains the IPIF.  The status is independent of whether interrupts
+* are enabled and could be used for polling a device at a higher level rather
+* than a more detailed level.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device which contains the IPIF.  With the exception of some internal IPIF
+* conditions, the contents of this register are not latched but indicate
+* the live status of the interrupt sources within the device.  Writing any of
+* the non-latched bits of the register will have no effect on the register.
+*
+* For the latched bits of this register only, setting a bit which is zero
+* within this register causes an interrupt to generated.  The device global
+* interrupt enable register and the device interrupt enable register must be set
+* appropriately to allow an interrupt to be passed out of the device. The
+* interrupt is cleared by writing to this register with the bits to be
+* cleared set to a one and all others to zero.	This register implements a
+* toggle on write functionality meaning any bits which are set in the value
+* written cause the bits in the register to change to the opposite state.
+*
+* This function writes the specified value to the register such that
+* some bits may be set and others cleared.  It is the caller's responsibility
+* to get the value of the register prior to setting the value to prevent a
+* destructive behavior.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* Status contains the value to be written to the interrupt status register of
+* the device.  The only bits which can be written are the latched bits which
+* contain the internal IPIF conditions.	 The following values may be used to
+* set the status register or clear an interrupt condition.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status))
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_DISR
+*
+* DESCRIPTION:
+*
+* This function gets the device interrupt status register contents.
+* This register indicates the status of interrupt sources for a device
+* which contains the IPIF.  The status is independent of whether interrupts
+* are enabled and could be used for polling a device at a higher level.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device which contains the IPIF.  With the exception of some internal IPIF
+* conditions, the contents of this register are not latched but indicate
+* the live status of the interrupt sources within the device.
+*
+* For only the latched bits of this register, the interrupt may be cleared by
+* writing to these bits in the status register.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* A status which contains the value read from the interrupt status register of
+* the device. The bit definitions are specific to the device with
+* the exception of the latched internal IPIF condition bits. The following
+* values may be used to detect internal IPIF conditions in the status.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_DISR(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_WRITE_DIER
+*
+* DESCRIPTION:
+*
+* This function sets the device interrupt enable register contents.
+* This register controls which interrupt sources of the device are allowed to
+* generate an interrupt.  The device global interrupt enable register must also
+* be set appropriately for an interrupt to be passed out of the device.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device which contains the IPIF.  Setting a bit in this register enables that
+* interrupt source to generate an interrupt.  Clearing a bit in this register
+* disables interrupt generation for that interrupt source.
+*
+* This function writes only the specified value to the register such that
+* some interrupts source may be enabled and others disabled.  It is the
+* caller's responsibility to get the value of the interrupt enable register
+* prior to setting the value to prevent an destructive behavior.
+*
+* An interrupt source may not be enabled to generate an interrupt, but can
+* still be polled in the interrupt status register.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* Enable contains the value to be written to the interrupt enable register
+* of the device.  The bit definitions are specific to the device with
+* the exception of the internal IPIF conditions. The following
+* values may be used to enable the internal IPIF conditions interrupts.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress,
+*					  u32 Enable)
+*
+******************************************************************************/
+#define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable))
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_DIER
+*
+* DESCRIPTION:
+*
+* This function gets the device interrupt enable register contents.
+* This register controls which interrupt sources of the device
+* are allowed to generate an interrupt.	 The device global interrupt enable
+* register and the device interrupt enable register must also be set
+* appropriately for an interrupt to be passed out of the device.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device which contains the IPIF.  Setting a bit in this register enables that
+* interrupt source to generate an interrupt if the global enable is set
+* appropriately.  Clearing a bit in this register disables interrupt generation
+* for that interrupt source regardless of the global interrupt enable.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* The value read from the interrupt enable register of the device.  The bit
+* definitions are specific to the device with the exception of the internal
+* IPIF conditions. The following values may be used to determine from the
+* value if the internal IPIF conditions interrupts are enabled.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_DIER(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_DIPR
+*
+* DESCRIPTION:
+*
+* This function gets the device interrupt pending register contents.
+* This register indicates the pending interrupt sources, those that are waiting
+* to be serviced by the software, for a device which contains the IPIF.
+* An interrupt must be enabled in the interrupt enable register of the IPIF to
+* be pending.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* the device which contains the IPIF.  With the exception of some internal IPIF
+* conditions, the contents of this register are not latched since the condition
+* is latched in the IP interrupt status register, by an internal block of the
+* IPIF such as a FIFO or DMA channel, or by the IP of the device.  This register
+* is read only and is not latched, but it is necessary to acknowledge (clear)
+* the interrupt condition by performing the appropriate processing for the IP
+* or block within the IPIF.
+*
+* This register can be thought of as the contents of the interrupt status
+* register ANDed with the contents of the interrupt enable register.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* The value read from the interrupt pending register of the device.  The bit
+* definitions are specific to the device with the exception of the latched
+* internal IPIF condition bits. The following values may be used to detect
+* internal IPIF conditions in the value.
+*
+*   XIIF_V123B_ERROR_MASK     Indicates a device error in the IPIF
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_DIPR(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_DIIR
+*
+* DESCRIPTION:
+*
+* This function gets the device interrupt ID for the highest priority interrupt
+* which is pending from the interrupt ID register. This function provides
+* priority resolution such that faster interrupt processing is possible.
+* Without priority resolution, it is necessary for the software to read the
+* interrupt pending register and then check each interrupt source to determine
+* if an interrupt is pending.  Priority resolution becomes more important as the
+* number of interrupt sources becomes larger.
+*
+* Interrupt priorities are based upon the bit position of the interrupt in the
+* interrupt pending register with bit 0 being the highest priority. The
+* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the
+* highest priority. The interrupt ID register is live rather than latched such
+* that multiple calls to this function may not yield the same results.	A
+* special value, outside of the interrupt priority range of 0 - 31, is
+* contained in the register which indicates that no interrupt is pending.  This
+* may be useful for allowing software to continue processing interrupts in a
+* loop until there are no longer any interrupts pending.
+*
+* The interrupt ID is designed to allow a function pointer table to be used
+* in the software such that the interrupt ID is used as an index into that
+* table.  The function pointer table could contain an instance pointer, such
+* as to DMA channel, and a function pointer to the function which handles
+* that interrupt.  This design requires the interrupt processing of the device
+* driver to be partitioned into smaller more granular pieces based upon
+* hardware used by the device, such as DMA channels and FIFOs.
+*
+* It is not mandatory that this function be used by the device driver software.
+* It may choose to read the pending register and resolve the pending interrupt
+* priorities on it's own.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* An interrupt ID, 0 - 31, which identifies the highest priority interrupt
+* which is pending.  A value of XIIF_NO_INTERRUPT_ID indicates that there is
+* no interrupt pending. The following values may be used to identify the
+* interrupt ID for the internal IPIF interrupts.
+*
+*   XIIF_V123B_ERROR_INTERRUPT_ID     Indicates a device error in the IPIF
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_DIIR(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_GLOBAL_INTR_DISABLE
+*
+* DESCRIPTION:
+*
+* This function disables all interrupts for the device by writing to the global
+* interrupt enable register.  This register provides the ability to disable
+* interrupts without any modifications to the interrupt enable register such
+* that it is minimal effort to restore the interrupts to the previous enabled
+* state.  The corresponding function, XIpIf_GlobalIntrEnable, is provided to
+* restore the interrupts to the previous enabled state.	 This function is
+* designed to be used in critical sections of device drivers such that it is
+* not necessary to disable other device interrupts.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_GINTR_ENABLE
+*
+* DESCRIPTION:
+*
+* This function writes to the global interrupt enable register to enable
+* interrupts from the device.  This register provides the ability to enable
+* interrupts without any modifications to the interrupt enable register such
+* that it is minimal effort to restore the interrupts to the previous enabled
+* state.  This function does not enable individual interrupts as the interrupt
+* enable register must be set appropriately.  This function is designed to be
+* used in critical sections of device drivers such that it is not necessary to
+* disable other device interrupts.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress)		  \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \
+	       XIIF_V123B_GINTR_ENABLE_MASK)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_IS_GINTR_ENABLED
+*
+* DESCRIPTION:
+*
+* This function determines if interrupts are enabled at the global level by
+* reading the gloabl interrupt register. This register provides the ability to
+* disable interrupts without any modifications to the interrupt enable register
+* such that it is minimal effort to restore the interrupts to the previous
+* enabled state.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress)		\
+    (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) ==	\
+	      XIIF_V123B_GINTR_ENABLE_MASK)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_WRITE_IISR
+*
+* DESCRIPTION:
+*
+* This function sets the IP interrupt status register to the specified value.
+* This register indicates the status of interrupt sources for the IP of the
+* device.  The IP is defined as the part of the device that connects to the
+* IPIF.	 The status is independent of whether interrupts are enabled such that
+* the status register may also be polled when interrupts are not enabled.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* IP.  All bits of this register are latched. Setting a bit which is zero
+* within this register causes an interrupt to be generated.  The device global
+* interrupt enable register and the device interrupt enable register must be set
+* appropriately to allow an interrupt to be passed out of the device. The
+* interrupt is cleared by writing to this register with the bits to be
+* cleared set to a one and all others to zero.	This register implements a
+* toggle on write functionality meaning any bits which are set in the value
+* written cause the bits in the register to change to the opposite state.
+*
+* This function writes only the specified value to the register such that
+* some status bits may be set and others cleared.  It is the caller's
+* responsibility to get the value of the register prior to setting the value
+* to prevent an destructive behavior.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* Status contains the value to be written to the IP interrupt status
+* register.  The bit definitions are specific to the device IP.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status))
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_IISR
+*
+* DESCRIPTION:
+*
+* This function gets the contents of the IP interrupt status register.
+* This register indicates the status of interrupt sources for the IP of the
+* device.  The IP is defined as the part of the device that connects to the
+* IPIF. The status is independent of whether interrupts are enabled such
+* that the status register may also be polled when interrupts are not enabled.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* device.  All bits of this register are latched.  Writing a 1 to a bit within
+* this register causes an interrupt to be generated if enabled in the interrupt
+* enable register and the global interrupt enable is set.  Since the status is
+* latched, each status bit must be acknowledged in order for the bit in the
+* status register to be updated.  Each bit can be acknowledged by writing a
+* 0 to the bit in the status register.
+
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* A status which contains the value read from the IP interrupt status register.
+* The bit definitions are specific to the device IP.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_READ_IISR(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET)
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_WRITE_IIER
+*
+* DESCRIPTION:
+*
+* This function sets the IP interrupt enable register contents.	 This register
+* controls which interrupt sources of the IP are allowed to generate an
+* interrupt.  The global interrupt enable register and the device interrupt
+* enable register must also be set appropriately for an interrupt to be
+* passed out of the device containing the IPIF and the IP.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* IP.  Setting a bit in this register enables the interrupt source to generate
+* an interrupt.	 Clearing a bit in this register disables interrupt generation
+* for that interrupt source.
+*
+* This function writes only the specified value to the register such that
+* some interrupt sources may be enabled and others disabled.  It is the
+* caller's responsibility to get the value of the interrupt enable register
+* prior to setting the value to prevent an destructive behavior.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* Enable contains the value to be written to the IP interrupt enable register.
+* The bit definitions are specific to the device IP.
+*
+* RETURN VALUE:
+*
+* None.
+*
+* NOTES:
+*
+* None.
+*
+******************************************************************************/
+#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \
+    XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable))
+
+/******************************************************************************
+*
+* MACRO:
+*
+* XIIF_V123B_READ_IIER
+*
+* DESCRIPTION:
+*
+*
+* This function gets the IP interrupt enable register contents.	 This register
+* controls which interrupt sources of the IP are allowed to generate an
+* interrupt.  The global interrupt enable register and the device interrupt
+* enable register must also be set appropriately for an interrupt to be
+* passed out of the device containing the IPIF and the IP.
+*
+* Each bit of the register correlates to a specific interrupt source within the
+* IP.  Setting a bit in this register enables the interrupt source to generate
+* an interrupt.	 Clearing a bit in this register disables interrupt generation
+* for that interrupt source.
+*
+* ARGUMENTS:
+*
+* RegBaseAddress contains the base address of the IPIF registers.
+*
+* RETURN VALUE:
+*
+* The contents read from the IP interrupt enable register.  The bit definitions
+* are specific to the device IP.
+*
+* NOTES:
+*
+* Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress)
+*
+******************************************************************************/
+#define XIIF_V123B_READ_IIER(RegBaseAddress) \
+    XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization Functions
+ */
+XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth);
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.c b/board/xilinx/common/xpacket_fifo_v1_00_b.c
new file mode 100755
index 0000000..ae2d6d4
--- /dev/null
+++ b/board/xilinx/common/xpacket_fifo_v1_00_b.c
@@ -0,0 +1,448 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/*
+*
+* @file xpacket_fifo_v1_00_b.c
+*
+* Contains functions for the XPacketFifoV100b component. See xpacket_fifo_v1_00_b.h
+* for more information about the component.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm 03/26/02  First release
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xio.h"
+#include "xstatus.h"
+#include "xpacket_fifo_v1_00_b.h"
+
+/************************** Constant Definitions *****************************/
+
+/* width of a FIFO word */
+
+#define XPF_FIFO_WIDTH_BYTE_COUNT       4UL
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************* Variable Definitions ******************************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a packet FIFO.  Initialization resets the
+* FIFO such that it's empty and ready to use.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+* @param RegBaseAddress contains the base address of the registers for
+*        the packet FIFO.
+* @param DataBaseAddress contains the base address of the data for
+*        the packet FIFO.
+*
+* @return
+*
+* Always returns XST_SUCCESS.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
+			    u32 RegBaseAddress, u32 DataBaseAddress)
+{
+	/* assert to verify input argument are valid */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+
+	/* initialize the component variables to the specified state */
+
+	InstancePtr->RegBaseAddress = RegBaseAddress;
+	InstancePtr->DataBaseAddress = DataBaseAddress;
+	InstancePtr->IsReady = XCOMPONENT_IS_READY;
+
+	/* reset the FIFO such that it's empty and ready to use and indicate the
+	 * initialization was successful, note that the is ready variable must be
+	 * set prior to calling the reset function to prevent an assert
+	 */
+	XPF_V100B_RESET(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* This function performs a self-test on the specified packet FIFO.  The self
+* test resets the FIFO and reads a register to determine if it is the correct
+* reset value.  This test is destructive in that any data in the FIFO will
+* be lost.
+*
+* @param InstancePtr is a pointer to the packet FIFO to be operated on.
+*
+* @param FifoType specifies the type of FIFO, read or write, for the self test.
+*        The FIFO type is specified by the values XPF_READ_FIFO_TYPE or
+*        XPF_WRITE_FIFO_TYPE.
+*
+* @return
+*
+* XST_SUCCESS is returned if the selftest is successful, or
+* XST_PFIFO_BAD_REG_VALUE indicating that the value readback from the
+* occupancy/vacancy count register after a reset does not match the
+* specified reset value.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType)
+{
+	u32 Register;
+
+	/* assert to verify valid input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID((FifoType == XPF_READ_FIFO_TYPE) ||
+			(FifoType == XPF_WRITE_FIFO_TYPE));
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* reset the fifo and then check to make sure the occupancy/vacancy
+	 * register contents are correct for a reset condition
+	 */
+	XPF_V100B_RESET(InstancePtr);
+
+	Register = XIo_In32(InstancePtr->RegBaseAddress +
+			    XPF_COUNT_STATUS_REG_OFFSET);
+
+	/* check the value of the register to ensure that it's correct for the
+	 * specified FIFO type since both FIFO types reset to empty, but a bit
+	 * in the register changes definition based upon FIFO type
+	 */
+
+	if (FifoType == XPF_READ_FIFO_TYPE) {
+		/* check the regiser value for a read FIFO which should be empty */
+
+		if (Register != XPF_EMPTY_FULL_MASK) {
+			return XST_PFIFO_BAD_REG_VALUE;
+		}
+	} else {
+		/* check the register value for a write FIFO which should not be full
+		 * on reset
+		 */
+		if ((Register & XPF_EMPTY_FULL_MASK) != 0) {
+			return XST_PFIFO_BAD_REG_VALUE;
+		}
+	}
+
+	/* the test was successful */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* Read data from a FIFO and puts it into a specified buffer. The packet FIFO is
+* currently 32 bits wide such that an input buffer which is a series of bytes
+* is filled from the FIFO a word at a time. If the requested byte count is not
+* a multiple of 32 bit words, it is necessary for this function to format the
+* remaining 32 bit word from the FIFO into a series of bytes in the buffer.
+* There may be up to 3 extra bytes which must be extracted from the last word
+* of the FIFO and put into the buffer.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+* @param BufferPtr points to the memory buffer to write the data into. This
+*        buffer must be 32 bit aligned or an alignment exception could be
+*        generated. Since this buffer is a byte buffer, the data is assumed to
+*        be endian independent.
+* @param ByteCount contains the number of bytes to read from the FIFO. This
+*        number of bytes must be present in the FIFO or an error will be
+*        returned.
+*
+* @return
+*
+* XST_SUCCESS indicates the operation was successful.  If the number of
+* bytes specified by the byte count is not present in the FIFO
+* XST_PFIFO_LACK_OF_DATA is returned.
+*
+* If the function was successful, the specified buffer is modified to contain
+* the bytes which were removed from the FIFO.
+*
+* @note
+*
+* Note that the exact number of bytes which are present in the FIFO is
+* not known by this function.  It can only check for a number of 32 bit
+* words such that if the byte count specified is incorrect, but is still
+* possible based on the number of words in the FIFO, up to 3 garbage bytes
+* may be present at the end of the buffer.
+* <br><br>
+* This function assumes that if the device consuming data from the FIFO is
+* a byte device, the order of the bytes to be consumed is from the most
+* significant byte to the least significant byte of a 32 bit word removed
+* from the FIFO.
+*
+******************************************************************************/
+XStatus
+XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
+		      u8 * BufferPtr, u32 ByteCount)
+{
+	u32 FifoCount;
+	u32 WordCount;
+	u32 ExtraByteCount;
+	u32 *WordBuffer = (u32 *) BufferPtr;
+
+	/* assert to verify valid input arguments including 32 bit alignment of
+	 * the buffer pointer
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufferPtr != NULL);
+	XASSERT_NONVOID(((u32) BufferPtr &
+			 (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the count of how many 32 bit words are in the FIFO, if there aren't
+	 * enought words to satisfy the request, return an error
+	 */
+
+	FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
+			     XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+
+	if ((FifoCount * XPF_FIFO_WIDTH_BYTE_COUNT) < ByteCount) {
+		return XST_PFIFO_LACK_OF_DATA;
+	}
+
+	/* calculate the number of words to read from the FIFO before the word
+	 * containing the extra bytes, and calculate the number of extra bytes
+	 * the extra bytes are defined as those at the end of the buffer when
+	 * the buffer does not end on a 32 bit boundary
+	 */
+	WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
+	ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
+
+	/* Read the 32 bit words from the FIFO for all the buffer except the
+	 * last word which contains the extra bytes, the following code assumes
+	 * that the buffer is 32 bit aligned, otherwise an alignment exception could
+	 * be generated
+	 */
+	for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
+		WordBuffer[FifoCount] = XIo_In32(InstancePtr->DataBaseAddress);
+	}
+
+	/* if there are extra bytes to handle, read the last word from the FIFO
+	 * and insert the extra bytes into the buffer
+	 */
+	if (ExtraByteCount > 0) {
+		u32 LastWord;
+		u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
+
+		/* get the last word from the FIFO for the extra bytes */
+
+		LastWord = XIo_In32(InstancePtr->DataBaseAddress);
+
+		/* one extra byte in the last word, put the byte into the next location
+		 * of the buffer, bytes in a word of the FIFO are ordered from most
+		 * significant byte to least
+		 */
+		if (ExtraByteCount == 1) {
+			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
+		}
+
+		/* two extra bytes in the last word, put each byte into the next two
+		 * locations of the buffer
+		 */
+		else if (ExtraByteCount == 2) {
+			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
+			ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
+		}
+		/* three extra bytes in the last word, put each byte into the next three
+		 * locations of the buffer
+		 */
+		else if (ExtraByteCount == 3) {
+			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
+			ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
+			ExtraBytesBuffer[2] = (u8) (LastWord >> 8);
+		}
+	}
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+*
+* Write data into a packet FIFO. The packet FIFO is currently 32 bits wide
+* such that an input buffer which is a series of bytes must be written into the
+* FIFO a word at a time. If the buffer is not a multiple of 32 bit words, it is
+* necessary for this function to format the remaining bytes into a single 32
+* bit word to be inserted into the FIFO. This is necessary to avoid any
+* accesses past the end of the buffer.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+* @param BufferPtr points to the memory buffer that data is to be read from
+*        and written into the FIFO. Since this buffer is a byte buffer, the data
+*        is assumed to be endian independent. This buffer must be 32 bit aligned
+*        or an alignment exception could be generated.
+* @param ByteCount contains the number of bytes to read from the buffer and to
+*        write to the FIFO.
+*
+* @return
+*
+* XST_SUCCESS is returned if the operation succeeded.  If there is not enough
+* room in the FIFO to hold the specified bytes, XST_PFIFO_NO_ROOM is
+* returned.
+*
+* @note
+*
+* This function assumes that if the device inserting data into the FIFO is
+* a byte device, the order of the bytes in each 32 bit word is from the most
+* significant byte to the least significant byte.
+*
+******************************************************************************/
+XStatus
+XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
+		       u8 * BufferPtr, u32 ByteCount)
+{
+	u32 FifoCount;
+	u32 WordCount;
+	u32 ExtraByteCount;
+	u32 *WordBuffer = (u32 *) BufferPtr;
+
+	/* assert to verify valid input arguments including 32 bit alignment of
+	 * the buffer pointer
+	 */
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufferPtr != NULL);
+	XASSERT_NONVOID(((u32) BufferPtr &
+			 (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/* get the count of how many words may be inserted into the FIFO */
+
+	FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
+			     XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
+
+	/* Calculate the number of 32 bit words required to insert the specified
+	 * number of bytes in the FIFO and determine the number of extra bytes
+	 * if the buffer length is not a multiple of 32 bit words
+	 */
+
+	WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
+	ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
+
+	/* take into account the extra bytes in the total word count */
+
+	if (ExtraByteCount > 0) {
+		WordCount++;
+	}
+
+	/* if there's not enough room in the FIFO to hold the specified
+	 * number of bytes, then indicate an error,
+	 */
+	if (FifoCount < WordCount) {
+		return XST_PFIFO_NO_ROOM;
+	}
+
+	/* readjust the word count to not take into account the extra bytes */
+
+	if (ExtraByteCount > 0) {
+		WordCount--;
+	}
+
+	/* Write all the bytes of the buffer which can be written as 32 bit
+	 * words into the FIFO, waiting to handle the extra bytes seperately
+	 */
+	for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
+		XIo_Out32(InstancePtr->DataBaseAddress, WordBuffer[FifoCount]);
+	}
+
+	/* if there are extra bytes to handle, extract them from the buffer
+	 * and create a 32 bit word and write it to the FIFO
+	 */
+	if (ExtraByteCount > 0) {
+		u32 LastWord = 0;
+		u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
+
+		/* one extra byte in the buffer, put the byte into the last word
+		 * to be inserted into the FIFO, perform this processing inline rather
+		 * than in a loop to help performance
+		 */
+		if (ExtraByteCount == 1) {
+			LastWord = ExtraBytesBuffer[0] << 24;
+		}
+
+		/* two extra bytes in the buffer, put each byte into the last word
+		 * to be inserted into the FIFO
+		 */
+		else if (ExtraByteCount == 2) {
+			LastWord = ExtraBytesBuffer[0] << 24 |
+			    ExtraBytesBuffer[1] << 16;
+		}
+
+		/* three extra bytes in the buffer, put each byte into the last word
+		 * to be inserted into the FIFO
+		 */
+		else if (ExtraByteCount == 3) {
+			LastWord = ExtraBytesBuffer[0] << 24 |
+			    ExtraBytesBuffer[1] << 16 |
+			    ExtraBytesBuffer[2] << 8;
+		}
+
+		/* write the last 32 bit word to the FIFO and return with no errors */
+
+		XIo_Out32(InstancePtr->DataBaseAddress, LastWord);
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.h b/board/xilinx/common/xpacket_fifo_v1_00_b.h
new file mode 100755
index 0000000..1cda0e8
--- /dev/null
+++ b/board/xilinx/common/xpacket_fifo_v1_00_b.h
@@ -0,0 +1,306 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/*
+*
+* @file xpacket_fifo_v1_00_b.h
+*
+* This component is a common component because it's primary purpose is to
+* prevent code duplication in drivers. A driver which must handle a packet
+* FIFO uses this component rather than directly manipulating a packet FIFO.
+*
+* A FIFO is a device which has dual port memory such that one user may be
+* inserting data into the FIFO while another is consuming data from the FIFO.
+* A packet FIFO is designed for use with packet protocols such as Ethernet and
+* ATM.  It is typically only used with devices when DMA and/or Scatter Gather
+* is used.  It differs from a nonpacket FIFO in that it does not provide any
+* interrupts for thresholds of the FIFO such that it is less useful without
+* DMA.
+*
+* @note
+*
+* This component has the capability to generate an interrupt when an error
+* condition occurs.  It is the user's responsibility to provide the interrupt
+* processing to handle the interrupt. This component provides the ability to
+* determine if that interrupt is active, a deadlock condition, and the ability
+* to reset the FIFO to clear the condition. In this condition, the device which
+* is using the FIFO should also be reset to prevent other problems. This error
+* condition could occur as a normal part of operation if the size of the FIFO
+* is not setup correctly.  See the hardware IP specification for more details.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm 03/26/02  First release
+* </pre>
+*
+*****************************************************************************/
+#ifndef XPACKET_FIFO_H		/* prevent circular inclusions */
+#define XPACKET_FIFO_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * These constants specify the FIFO type and are mutually exclusive
+ */
+#define XPF_READ_FIFO_TYPE      0	/* a read FIFO */
+#define XPF_WRITE_FIFO_TYPE     1	/* a write FIFO */
+
+/*
+ * These constants define the offsets to each of the registers from the
+ * register base address, each of the constants are a number of bytes
+ */
+#define XPF_RESET_REG_OFFSET            0UL
+#define XPF_MODULE_INFO_REG_OFFSET      0UL
+#define XPF_COUNT_STATUS_REG_OFFSET     4UL
+
+/*
+ * This constant is used with the Reset Register
+ */
+#define XPF_RESET_FIFO_MASK             0x0000000A
+
+/*
+ * These constants are used with the Occupancy/Vacancy Count Register. This
+ * register also contains FIFO status
+ */
+#define XPF_COUNT_MASK                  0x0000FFFF
+#define XPF_DEADLOCK_MASK               0x20000000
+#define XPF_ALMOST_EMPTY_FULL_MASK      0x40000000
+#define XPF_EMPTY_FULL_MASK             0x80000000
+
+/**************************** Type Definitions *******************************/
+
+/*
+ * The XPacketFifo driver instance data. The driver is required to allocate a
+ * variable of this type for every packet FIFO in the device.
+ */
+typedef struct {
+	u32 RegBaseAddress;	/* Base address of registers */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 DataBaseAddress;	/* Base address of data for FIFOs */
+} XPacketFifoV100b;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/*
+*
+* Reset the specified packet FIFO.  Resetting a FIFO will cause any data
+* contained in the FIFO to be lost.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* Signature: void XPF_V100B_RESET(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_RESET(InstancePtr) \
+    XIo_Out32((InstancePtr)->RegBaseAddress + XPF_RESET_REG_OFFSET, XPF_RESET_FIFO_MASK);
+
+/*****************************************************************************/
+/*
+*
+* Get the occupancy count for a read packet FIFO and the vacancy count for a
+* write packet FIFO. These counts indicate the number of 32-bit words
+* contained (occupancy) in the FIFO or the number of 32-bit words available
+* to write (vacancy) in the FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* The occupancy or vacancy count for the specified packet FIFO.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_GET_COUNT(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_GET_COUNT(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_COUNT_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is almost empty. Almost empty is
+* defined for a read FIFO when there is only one data word in the FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is almost empty, FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_IS_ALMOST_EMPTY(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_ALMOST_EMPTY(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_ALMOST_EMPTY_FULL_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is almost full. Almost full is
+* defined for a write FIFO when there is only one available data word in the
+* FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is almost full, FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_IS_ALMOST_FULL(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_ALMOST_FULL(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_ALMOST_EMPTY_FULL_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is empty. This applies only to a
+* read FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is empty, FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_IS_EMPTY(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_EMPTY(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_EMPTY_FULL_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is full. This applies only to a
+* write FIFO.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is full, FALSE otherwise.
+*
+* @note
+*
+* Signature: u32 XPF_V100B_IS_FULL(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_FULL(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_EMPTY_FULL_MASK)
+
+/*****************************************************************************/
+/*
+*
+* Determine if the specified packet FIFO is deadlocked.  This condition occurs
+* when the FIFO is full and empty at the same time and is caused by a packet
+* being written to the FIFO which exceeds the total data capacity of the FIFO.
+* It occurs because of the mark/restore features of the packet FIFO which allow
+* retransmission of a packet. The software should reset the FIFO and any devices
+* using the FIFO when this condition occurs.
+*
+* @param InstancePtr contains a pointer to the FIFO to operate on.
+*
+* @return
+*
+* TRUE if the packet FIFO is deadlocked, FALSE otherwise.
+*
+* @note
+*
+* This component has the capability to generate an interrupt when an error
+* condition occurs.  It is the user's responsibility to provide the interrupt
+* processing to handle the interrupt. This function provides the ability to
+* determine if a deadlock condition, and the ability to reset the FIFO to
+* clear the condition.
+*
+* In this condition, the device which is using the FIFO should also be reset
+* to prevent other problems. This error condition could occur as a normal part
+* of operation if the size of the FIFO is not setup correctly.
+*
+* Signature: u32 XPF_V100B_IS_DEADLOCKED(XPacketFifoV100b *InstancePtr)
+*
+******************************************************************************/
+#define XPF_V100B_IS_DEADLOCKED(InstancePtr) \
+    (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
+    XPF_DEADLOCK_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/* Standard functions */
+
+XStatus XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
+				    u32 RegBaseAddress, u32 DataBaseAddress);
+XStatus XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType);
+
+/* Data functions */
+
+XStatus XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
+			      u8 * ReadBufferPtr, u32 ByteCount);
+XStatus XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
+			       u8 * WriteBufferPtr, u32 ByteCount);
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xstatus.h b/board/xilinx/common/xstatus.h
new file mode 100755
index 0000000..ffda4d7
--- /dev/null
+++ b/board/xilinx/common/xstatus.h
@@ -0,0 +1,347 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called XStatus.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						 * registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						 * the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						 * interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						 * have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						 * already started i.e.
+						 * sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						 * already stopped i.e.
+						 * sub channel */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Adapter is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid adapter init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * The status typedef.
+ */
+typedef u32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/common/xversion.c b/board/xilinx/common/xversion.c
new file mode 100755
index 0000000..c8a6915
--- /dev/null
+++ b/board/xilinx/common/xversion.c
@@ -0,0 +1,350 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* This file contains the implementation of the XVersion component. This
+* component represents a version ID.  It is encapsulated within a component
+* so that it's type and implementation can change without affecting users of
+* it.
+*
+* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
+* X is the major revision, YY is the minor revision, and Z is the
+* compatability revision.
+*
+* Packed versions are also utilized for the configuration ROM such that
+* memory is minimized. A packed version consumes only 16 bits and is
+* formatted as follows.
+*
+* <pre>
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+</pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xversion.h"
+
+/************************** Constant Definitions *****************************/
+
+/* the following constants define the masks and shift values to allow the
+ * revisions to be packed and unpacked, a packed version is packed into a 16
+ * bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the
+ * major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability
+ * revision
+ */
+#define XVE_MAJOR_SHIFT_VALUE       12
+#define XVE_MINOR_ONLY_MASK         0x0FE0
+#define XVE_MINOR_SHIFT_VALUE       5
+#define XVE_COMP_ONLY_MASK          0x001F
+
+/* the following constants define the specific characters of a version string
+ * for each character of the revision, a version string is in the following
+ * format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor
+ * revision (00 - 99), and Z is the compatability revision (a - z)
+ */
+#define XVE_MAJOR_CHAR      0	/* major revision 0 - 9 */
+#define XVE_MINOR_TENS_CHAR 2	/* minor revision tens 0 - 9 */
+#define XVE_MINOR_ONES_CHAR 3	/* minor revision ones 0 - 9 */
+#define XVE_COMP_CHAR       4	/* compatability revision a - z */
+#define XVE_END_STRING_CHAR 5
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static u32 IsVersionStringValid(s8 * StringPtr);
+
+/*****************************************************************************
+*
+* Unpacks a packed version into the specified version. Versions are packed
+* into the configuration ROM to reduce the amount storage. A packed version
+* is a binary format as oppossed to a non-packed version which is implemented
+* as a string.
+*
+* @param    InstancePtr points to the version to unpack the packed version into.
+* @param    PackedVersion contains the packed version to unpack.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion)
+{
+	/* not implemented yet since CROM related */
+}
+
+/*****************************************************************************
+*
+* Packs a version into the specified packed version. Versions are packed into
+* the configuration ROM to reduce the amount storage.
+*
+* @param    InstancePtr points to the version to pack.
+* @param    PackedVersionPtr points to the packed version which will receive
+*           the new packed version.
+*
+* @return
+*
+* A status, XST_SUCCESS, indicating the packing was accomplished
+* successfully, or an error, XST_INVALID_VERSION, indicating the specified
+* input version was not valid such that the pack did not occur
+* <br><br>
+* The packed version pointed to by PackedVersionPtr is modified with the new
+* packed version if the status indicates success.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersionPtr)
+{
+	/* not implemented yet since CROM related */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************
+*
+* Determines if two versions are equal.
+*
+* @param    InstancePtr points to the first version to be compared.
+* @param    VersionPtr points to a second version to be compared.
+*
+* @return
+*
+* TRUE if the versions are equal, FALSE otherwise.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+u32
+XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr)
+{
+	u8 *Version1 = (u8 *) InstancePtr;
+	u8 *Version2 = (u8 *) VersionPtr;
+	int Index;
+
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(VersionPtr != NULL);
+
+	/* check each byte of the versions to see if they are the same,
+	 * return at any point a byte differs between them
+	 */
+	for (Index = 0; Index < sizeof (XVersion); Index++) {
+		if (Version1[Index] != Version2[Index]) {
+			return FALSE;
+		}
+	}
+
+	/* No byte was found to be different between the versions, so indicate
+	 * the versions are equal
+	 */
+	return TRUE;
+}
+
+/*****************************************************************************
+*
+* Converts a version to a null terminated string.
+*
+* @param    InstancePtr points to the version to convert.
+* @param    StringPtr points to the string which will be the result of the
+*           conversion. This does not need to point to a null terminated
+*           string as an input, but must point to storage which is an adequate
+*           amount to hold the result string.
+*
+* @return
+*
+* The null terminated string is inserted at the location pointed to by
+* StringPtr if the status indicates success.
+*
+* @note
+*
+* It is necessary for the caller to have already allocated the storage to
+* contain the string.  The amount of memory necessary for the string is
+* specified in the version header file.
+*
+******************************************************************************/
+void
+XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(StringPtr != NULL);
+
+	/* since version is implemented as a string, just copy the specified
+	 * input into the specified output
+	 */
+	XVersion_Copy(InstancePtr, (XVersion *) StringPtr);
+}
+
+/*****************************************************************************
+*
+* Initializes a version from a null terminated string. Since the string may not
+* be a format which is compatible with the version, an error could occur.
+*
+* @param    InstancePtr points to the version which is to be initialized.
+* @param    StringPtr points to a null terminated string which will be
+*           converted to a version.  The format of the string must match the
+*           version string format which is X.YYX where X = 0 - 9, YY = 00 - 99,
+*           Z = a - z.
+*
+* @return
+*
+* A status, XST_SUCCESS, indicating the conversion was accomplished
+* successfully, or XST_INVALID_VERSION indicating the version string format
+* was not valid.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr)
+{
+	/* assert to verify input arguments */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(StringPtr != NULL);
+
+	/* if the version string specified is not valid, return an error */
+
+	if (!IsVersionStringValid(StringPtr)) {
+		return XST_INVALID_VERSION;
+	}
+
+	/* copy the specified string into the specified version and indicate the
+	 * conversion was successful
+	 */
+	XVersion_Copy((XVersion *) StringPtr, InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************
+*
+* Copies the contents of a version to another version.
+*
+* @param    InstancePtr points to the version which is the source of data for
+*           the copy operation.
+* @param    VersionPtr points to another version which is the destination of
+*           the copy operation.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr)
+{
+	u8 *Source = (u8 *) InstancePtr;
+	u8 *Destination = (u8 *) VersionPtr;
+	int Index;
+
+	/* assert to verify input arguments */
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(VersionPtr != NULL);
+
+	/* copy each byte of the source version to the destination version */
+
+	for (Index = 0; Index < sizeof (XVersion); Index++) {
+		Destination[Index] = Source[Index];
+	}
+}
+
+/*****************************************************************************
+*
+* Determines if the specified version is valid.
+*
+* @param    StringPtr points to the string to be validated.
+*
+* @return
+*
+* TRUE if the version string is a valid format, FALSE otherwise.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static u32
+IsVersionStringValid(s8 * StringPtr)
+{
+	/* if the input string is not a valid format, "X.YYZ" where X = 0 - 9,
+	 * YY = 00 - 99, and Z = a - z, then indicate it's not valid
+	 */
+	if ((StringPtr[XVE_MAJOR_CHAR] < '0') ||
+	    (StringPtr[XVE_MAJOR_CHAR] > '9') ||
+	    (StringPtr[XVE_MINOR_TENS_CHAR] < '0') ||
+	    (StringPtr[XVE_MINOR_TENS_CHAR] > '9') ||
+	    (StringPtr[XVE_MINOR_ONES_CHAR] < '0') ||
+	    (StringPtr[XVE_MINOR_ONES_CHAR] > '9') ||
+	    (StringPtr[XVE_COMP_CHAR] < 'a') ||
+	    (StringPtr[XVE_COMP_CHAR] > 'z')) {
+		return FALSE;
+	}
+
+	return TRUE;
+}
diff --git a/board/xilinx/common/xversion.h b/board/xilinx/common/xversion.h
new file mode 100755
index 0000000..17f9da7
--- /dev/null
+++ b/board/xilinx/common/xversion.h
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* This file contains the interface for the XVersion component. This
+* component represents a version ID.  It is encapsulated within a component
+* so that it's type and implementation can change without affecting users of
+* it.
+*
+* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
+* X is the major revision, YY is the minor revision, and Z is the
+* compatability revision.
+*
+* Packed versions are also utilized for the configuration ROM such that
+* memory is minimized. A packed version consumes only 16 bits and is
+* formatted as follows.
+*
+* <pre>
+* Revision                  Range       Bit Positions
+*
+* Major Revision            0 - 9       Bits 15 - 12
+* Minor Revision            0 - 99      Bits 11 - 5
+* Compatability Revision    a - z       Bits 4 - 0
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XVERSION_H		/* prevent circular inclusions */
+#define XVERSION_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+typedef s8 XVersion[6];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+void XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion);
+
+XStatus XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersion);
+
+u32 XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr);
+
+void XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr);
+
+XStatus XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr);
+
+void XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr);
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/ml300/Makefile b/board/xilinx/ml300/Makefile
new file mode 100755
index 0000000..880c494
--- /dev/null
+++ b/board/xilinx/ml300/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+CFLAGS   += -I../ml300 -I../common -I../xilinx_enet -I../xilinx_iic
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o \
+	  serial.o \
+	  ../xilinx_enet/emac_adapter.o  ../xilinx_enet/xemac.o \
+	  ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
+	  ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
+	  ../xilinx_enet/xemac_intr_dma.o ../xilinx_iic/iic_adapter.o \
+	  ../xilinx_iic/xiic_l.o ../common/xipif_v1_23_b.o \
+	  ../common/xbasic_types.o ../common/xdma_channel.o \
+	  ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
+	  ../common/xversion.o \
+
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/xilinx/ml300/config.mk b/board/xilinx/ml300/config.mk
new file mode 100755
index 0000000..57ddb2f
--- /dev/null
+++ b/board/xilinx/ml300/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# esd ADCIOP boards
+#
+
+#TEXT_BASE = 0xFFFE0000
+TEXT_BASE = 0x04000000
diff --git a/board/xilinx/ml300/init.S b/board/xilinx/ml300/init.S
new file mode 100755
index 0000000..f753df8
--- /dev/null
+++ b/board/xilinx/ml300/init.S
@@ -0,0 +1,48 @@
+/*
+ * init.S: Stubs for U-Boot initialization
+ *
+ *     Author: Xilinx, Inc.
+ *
+ *
+ *     This program is free software; you can redistribute it and/or modify it
+ *     under the terms of the GNU General Public License as published by the
+ *     Free Software Foundation; either version 2 of the License, or (at your
+ *     option) any later version.
+ *
+ *
+ *     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+ *     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+ *     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+ *     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+ *     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+ *     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+ *     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+ *     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+ *     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+ *     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ *     FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *     Xilinx hardware products are not intended for use in life support
+ *     appliances, devices, or systems. Use in such applications is
+ *     expressly prohibited.
+ *
+ *
+ *     (c) Copyright 2002-2004 Xilinx Inc.
+ *     All rights reserved.
+ *
+ *
+ *     You should have received a copy of the GNU General Public License along
+ *     with this program; if not, write to the Free Software Foundation, Inc.,
+ *     675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ */
+
+	.globl ext_bus_cntlr_init
+ext_bus_cntlr_init:
+	blr
+
+	.globl sdram_init
+sdram_init:
+	blr
diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c
new file mode 100755
index 0000000..dad562f
--- /dev/null
+++ b/board/xilinx/ml300/ml300.c
@@ -0,0 +1,128 @@
+/*
+ * ml300.c: U-Boot platform support for Xilinx ML300 board
+ *
+ *     Author: Xilinx, Inc.
+ *
+ *
+ *     This program is free software; you can redistribute it and/or modify it
+ *     under the terms of the GNU General Public License as published by the
+ *     Free Software Foundation; either version 2 of the License, or (at your
+ *     option) any later version.
+ *
+ *
+ *     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+ *     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+ *     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+ *     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+ *     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+ *     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+ *     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+ *     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+ *     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+ *     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ *     FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *     Xilinx hardware products are not intended for use in life support
+ *     appliances, devices, or systems. Use in such applications is
+ *     expressly prohibited.
+ *
+ *
+ *     (c) Copyright 2002-2004 Xilinx Inc.
+ *     All rights reserved.
+ *
+ *
+ *     You should have received a copy of the GNU General Public License along
+ *     with this program; if not, write to the Free Software Foundation, Inc.,
+ *     675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include "xparameters.h"
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+extern void convert_env(void);
+#endif
+
+int
+board_pre_init(void)
+{
+	return 0;
+}
+
+int
+checkboard(void)
+{
+	char tmp[64];		/* long enough for environment variables */
+	char *s, *e;
+	int i = getenv_r("L", tmp, sizeof (tmp));
+
+	if (i < 0) {
+		printf("### No HW ID - assuming ML300");
+	} else {
+		for (e = tmp; *e; ++e) {
+			if (*e == ' ')
+				break;
+		}
+
+		printf("### Board Serial# is ");
+
+		for (s = tmp; s < e; ++s) {
+			putc(*s);
+		}
+
+	}
+	putc('\n');
+
+	return (0);
+}
+
+long int
+initdram(int board_type)
+{
+	return 128 * 1024 * 1024;
+}
+
+int
+testdram(void)
+{
+	printf("test: xxx MB - ok\n");
+
+	return (0);
+}
+
+/* implement functions originally in cpu/ppc4xx/speed.c */
+void
+get_sys_info(sys_info_t * sysInfo)
+{
+	sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+
+	/* only correct if the PLB and OPB run at the same frequency */
+	sysInfo->freqPLB = XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+	sysInfo->freqPCI = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 3;
+}
+
+ulong
+get_PCI_freq(void)
+{
+	ulong val;
+	PPC405_SYS_INFO sys_info;
+
+	get_sys_info(&sys_info);
+	val = sys_info.freqPCI;
+	return val;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+
+int
+misc_init_r()
+{
+	/* convert env name and value to u-boot standard */
+	convert_env();
+	return 0;
+}
+
+#endif
diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c
new file mode 100755
index 0000000..19bcc6f
--- /dev/null
+++ b/board/xilinx/ml300/serial.c
@@ -0,0 +1,155 @@
+/*
+ *     Author: Xilinx, Inc.
+ *
+ *
+ *     This program is free software; you can redistribute it and/or modify it
+ *     under the terms of the GNU General Public License as published by the
+ *     Free Software Foundation; either version 2 of the License, or (at your
+ *     option) any later version.
+ *
+ *
+ *     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+ *     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+ *     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+ *     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+ *     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+ *     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+ *     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+ *     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+ *     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+ *     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ *     FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *     Xilinx hardware products are not intended for use in life support
+ *     appliances, devices, or systems. Use in such applications is
+ *     expressly prohibited.
+ *
+ *
+ *     (c) Copyright 2002-2004 Xilinx Inc.
+ *     All rights reserved.
+ *
+ *
+ *     You should have received a copy of the GNU General Public License along
+ *     with this program; if not, write to the Free Software Foundation, Inc.,
+ *     675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <asm/u-boot.h>
+#include <asm/processor.h>
+#include <common.h>
+#include <command.h>
+#include <configs/ml300.h>
+#include "xparameters.h"
+
+#define USE_CHAN1 \
+	((defined XPAR_UARTNS550_0_BASEADDR) && (defined CFG_INIT_CHAN1))
+#define USE_CHAN2 \
+	((defined XPAR_UARTNS550_1_BASEADDR) && (defined CFG_INIT_CHAN2))
+
+#if USE_CHAN1
+#include <ns16550.h>
+#endif
+
+#if USE_CHAN1
+const NS16550_t COM_PORTS[] = { (NS16550_t) (XPAR_UARTNS550_0_BASEADDR + 3)
+#if USE_CHAN2
+	    , (NS16550_t) (XPAR_UARTNS550_1_BASEADDR + 3)
+#endif
+};
+#endif
+
+int
+serial_init(void)
+{
+#if USE_CHAN1
+	DECLARE_GLOBAL_DATA_PTR;
+	int clock_divisor;
+
+	clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate;
+	(void) NS16550_init(COM_PORTS[0], clock_divisor);
+#if USE_CHAN2
+	clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate;
+	(void) NS16550_init(COM_PORTS[1], clock_divisor);
+#endif
+#endif
+	return 0;
+
+}
+
+void
+serial_putc(const char c)
+{
+	if (c == '\n')
+		NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r');
+
+	NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c);
+}
+
+int
+serial_getc(void)
+{
+	return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]);
+}
+
+int
+serial_tstc(void)
+{
+	return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]);
+}
+
+void
+serial_setbrg(void)
+{
+#if USE_CHAN1
+	DECLARE_GLOBAL_DATA_PTR;
+	int clock_divisor;
+
+	clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate;
+	NS16550_reinit(COM_PORTS[0], clock_divisor);
+#if USE_CHAN2
+	clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate;
+	NS16550_reinit(COM_PORTS[1], clock_divisor);
+#endif
+#endif
+}
+
+void
+serial_puts(const char *s)
+{
+	while (*s) {
+		serial_putc(*s++);
+	}
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+void
+kgdb_serial_init(void)
+{
+}
+
+void
+putDebugChar(int c)
+{
+	serial_putc(c);
+}
+
+void
+putDebugStr(const char *str)
+{
+	serial_puts(str);
+}
+
+int
+getDebugChar(void)
+{
+	return serial_getc();
+}
+
+void
+kgdb_interruptible(int yes)
+{
+	return;
+}
+#endif				/* CFG_CMD_KGDB */
diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes
new file mode 100755
index 0000000..9daf147
--- /dev/null
+++ b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes
@@ -0,0 +1,55 @@
+#!/bin/bash
+
+if [ $# -ne 1 ]
+then
+    echo "usage: Ltypes filename" >&2
+    exit 2
+fi
+
+FILE="$1"
+#TMPFILE='mktemp "${FILE}.XXXXXX"' || exit 1
+TMPFILE=${FILE}.`date "+%s"`
+touch $TMPFILE || exit 1
+
+# Change all the Xilinx types to Linux types and put the result into a temp file
+sed	\
+	-e 's/\bXTRUE\b/TRUE/g' \
+	-e 's/\bXFALSE\b/FALSE/g' \
+	-e 's/\bXNULL\b/NULL/g' \
+	-e 's/"xenv.h"/<asm\/delay.h>/g' \
+	-e 's/\bXENV_USLEEP\b/udelay/g' \
+	-e 's/\bXuint8\b/u8/g' \
+	-e 's/\bXuint16\b/u16/g' \
+	-e 's/\bXuint32\b/u32/g' \
+	-e 's/\bXint8\b/s8/g' \
+	-e 's/\bXint16\b/s16/g' \
+	-e 's/\bXint32\b/s32/g' \
+	-e 's/\bXboolean\b/u32/g' \
+	"${FILE}" > "${TMPFILE}"
+
+# Overlay the original file with the temp file
+mv "${TMPFILE}" "${FILE}"
+
+# Are we doing xbasic_types.h?
+if [ "${FILE##*/}" = xbasic_types.h ]
+then
+    # Remember as you're reading this that we've already gone through the prior
+    # sed script.  We need to do some other things to xbasic_types.h:
+    #   1) Add ifndefs around TRUE and FALSE defines
+    #   2) Remove definition of NULL as NULL
+    #   3) Replace most of the primitive types section with a #include
+    sed \
+	-e '/u32 true/,/#define false/Ic\
+#ifndef TRUE\
+#define TRUE 1\
+#endif\
+#ifndef FALSE\
+#define FALSE 0\
+#endif' \
+	-e '/#define[[:space:]][[:space:]]*NULL[[:space:]][[:space:]]*NULL/d' \
+	-e '/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*char[[:space:]][[:space:]]*u8/,/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*long[[:space:]][[:space:]]*u32.*boolean/c\
+#include <linux/types.h>' \
+	"${FILE}" > "${TMPFILE}"
+
+    mv "${TMPFILE}" "${FILE}"
+fi
diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld
new file mode 100755
index 0000000..5169241
--- /dev/null
+++ b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld
@@ -0,0 +1,52 @@
+# (c) Copyright 2004 Xilinx Inc.
+#     Author: Xilinx, Inc.
+#
+#
+#     This program is free software; you can redistribute it and/or modify it
+#     under the terms of the GNU General Public License as published by the
+#     Free Software Foundation; either version 2 of the License, or (at your
+#     option) any later version.
+#
+#
+#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+#     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+#     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+#     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+#     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+#     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+#     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+#     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+#     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+#     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+#     FITNESS FOR A PARTICULAR PURPOSE.
+#
+#
+#     Xilinx hardware products are not intended for use in life support
+#     appliances, devices, or systems. Use in such applications is
+#     expressly prohibited.
+#
+#
+#     (c) Copyright 2002-2004 Xilinx Inc.
+#     All rights reserved.
+#
+#
+#     You should have received a copy of the GNU General Public License along
+#     with this program; if not, write to the Free Software Foundation, Inc.,
+#     675 Mass Ave, Cambridge, MA 02139, USA.
+
+OPTION psf_version = 2.1;
+
+BEGIN LIBRARY uboot OPTION DRC = uboot_drc;
+
+BEGIN ARRAY connected_periphs PROPERTY desc = "Peripherals connected to U-Boot";
+PROPERTY size = 0;
+PARAM name = periph_name, desc = "Name of Peripheral connected", type = string;
+END ARRAY
+    PARAMETER name = TARGET_DIR, desc = "Target Directory for U-Boot BSP", type = string;
+
+# location of persistent storage in the IIC EEPROM (defaults are set for ML300)
+PARAMETER name = IIC_PERSISTENT_BASEADDR, desc = "Start of persistent storage block in the EEPROM address space", type = int, default = 1024;
+PARAMETER name = IIC_PERSISTENT_HIGHADDR, desc = "End of persistent storage block in the EEPROM address space", type = int, default = 2047;
+PARAMETER name = IIC_PERSISTENT_EEPROMADDR, desc = "Address of the EEPROM on the IIC bus", type = int, default = 0xA0;
+
+END LIBRARY
diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl
new file mode 100755
index 0000000..9d44f44
--- /dev/null
+++ b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl
@@ -0,0 +1,325 @@
+#
+#      Author: Xilinx, Inc.
+#      
+#      
+#      This program is free software; you can redistribute it and/or modify it
+#      under the terms of the GNU General Public License as published by the
+#      Free Software Foundation; either version 2 of the License, or (at your
+#      option) any later version.
+#      
+#      
+#      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+#      COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+#      ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+#      XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+#      FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+#      ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+#      XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+#      THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+#      WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+#      CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+#      FITNESS FOR A PARTICULAR PURPOSE.
+#      
+#      
+#      Xilinx hardware products are not intended for use in life support
+#      appliances, devices, or systems. Use in such applications is
+#      expressly prohibited.
+#      
+#      
+#      (c) Copyright 2002-2004 Xilinx Inc.
+#      All rights reserved.
+#      
+#      
+#      You should have received a copy of the GNU General Public License along
+#      with this program; if not, write to the Free Software Foundation, Inc.,
+#      675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Globals
+lappend drvlist
+set ltypes "../../../sw_services/uboot_v1_00_a/data/Ltypes"
+
+proc uboot_drc {lib_handle} {
+    puts "U-Boot DRC..."
+}
+
+proc generate {libname} {
+    
+    global drvlist
+    
+    # Get list of peripherals connected to uboot
+    set conn_periphs [xget_handle $libname "ARRAY" "connected_periphs"]
+    #lappend drvlist
+    if {[string compare -nocase $conn_periphs ""] != 0} {
+	set conn_periphs_elems [xget_handle $conn_periphs "ELEMENTS" "*"]
+	# For each periph
+	foreach periph_elem $conn_periphs_elems {
+	    set periph [xget_value $periph_elem "PARAMETER" "periph_name"]
+	    # 1. Get driver
+	    set drv [xget_swhandle $periph]
+	    set posn [lsearch -exact $drvlist $drv]
+	    if {$posn == -1} {
+		lappend drvlist $drv
+	    }
+	}
+	
+	set file_handle [xopen_include_file "xparameters.h"]
+	puts $file_handle "\n/******************************************************************/\n"
+	puts $file_handle "/* U-Boot Redefines */"
+	puts $file_handle "\n/******************************************************************/\n"
+	close $file_handle
+	
+	foreach drv $drvlist {
+	    set drvname [xget_value $drv "NAME"]
+	    
+	    #Redefines xparameters.h
+	    if {[string compare -nocase $drvname "uartns550"] == 0} {
+		xredefine_uartns550 $drv "xparameters.h"
+	    }  elseif {[string compare -nocase $drvname "emac"] == 0} {
+		xredefine_emac $drv "xparameters.h"
+	    }  elseif {[string compare -nocase $drvname "iic"] == 0} {
+		xredefine_iic $drv "xparameters.h"
+	    }
+	}
+    }
+    
+    # define core_clock
+    xredefine_params $libname "xparameters.h" "CORE_CLOCK_FREQ_HZ"
+
+    # define the values for the persistent storage in IIC
+    xredefine_params $libname "xparameters.h" "IIC_PERSISTENT_BASEADDR" "IIC_PERSISTENT_HIGHADDR" "IIC_PERSISTENT_EEPROMADDR"
+
+}
+
+proc xget_corefreq {} {
+    set processor [xget_processor] 
+    set name [xget_value $processor "NAME"]
+    puts "procname : $name"
+    set processor_driver [xget_swhandle [xget_value $processor "NAME"]]
+    puts "procdrv : $processor_driver"
+    if {[string compare -nocase $processor_driver ""] != 0} {
+	set arg "CORE_CLOCK_FREQ_HZ"
+	#set retval [xget_value $processor_driver "PARAMETER" $arg]
+	set retval [xget_dname [xget_value $processor_driver "NAME"] $arg]
+	return $retval
+    }
+}
+
+# procedure that adds # defines to xparameters.h as XPAR_argument
+proc xredefine_params {handle file_name args} {
+    
+    puts "xredfine ..."
+    # Open include file
+    set file_handle [xopen_include_file $file_name]
+    puts "args : $args"
+
+    foreach arg $args {
+	if {[string compare -nocase $arg "CORE_CLOCK_FREQ_HZ"] == 0} {
+	    set value [xget_corefreq]
+	    puts "corefreq : $value"
+	} else {
+	    set value [xget_value $handle "PARAMETER" $arg]
+	    puts "value : $value"
+	}
+	
+	if {$value != ""} {
+	    set value [xformat_addr_string $value $arg]
+
+	    if {[string compare -nocase $arg "IIC_PERSISTENT_BASEADDR"] == 0} {
+		set name "PERSISTENT_0_IIC_0_BASEADDR"
+	    } elseif {[string compare -nocase $arg "IIC_PERSISTENT_HIGHADDR"] == 0} {
+		set name "PERSISTENT_0_IIC_0_HIGHADDR"
+	    } elseif {[string compare -nocase $arg "IIC_PERSISTENT_EEPROMADDR"] == 0} {
+		set name "PERSISTENT_0_IIC_0_EEPROMADDR"
+	    } else {
+		set name [string toupper $arg]
+	    }
+	    set name [format "XPAR_%s" $name]
+	    puts $file_handle "#define $name $value"
+	}
+    }
+
+    puts $file_handle "\n/******************************************************************/\n"
+    close $file_handle
+}
+
+# uart redefines...
+proc xredefine_uartns550 {drvhandle file_name} {
+    
+    xredefine_include_file $drvhandle $file_name "uartns550" "C_BASEADDR" "C_HIGHADDR" "CLOCK_HZ" "DEVICE_ID"
+    
+}
+
+proc xredefine_emac {drvhandle file_name} {
+    
+    xredefine_include_file $drvhandle $file_name "emac" "C_BASEADDR" "C_HIGHADDR" "C_DMA_PRESENT" "C_MII_EXIST" "C_ERR_COUNT_EXIST" "DEVICE_ID"
+    
+}
+
+proc xredefine_iic {drvhandle file_name} {
+    xredefine_include_file $drvhandle $file_name "iic" "C_BASEADDR" "C_HIGHADDR" "C_TEN_BIT_ADR" "DEVICE_ID"
+
+}
+
+#######################
+
+proc xredefine_include_file {drv_handle file_name drv_string args} {
+    
+    # Open include file
+    set file_handle [xopen_include_file $file_name]
+    
+    # Get all peripherals connected to this driver
+    set periphs [xget_periphs $drv_handle] 
+    
+    set pname [format "XPAR_%s_" [string toupper $drv_string]]
+    
+    # Print all parameters for all peripherals
+    set device_id 0
+    set sub_periphs 1
+    foreach periph $periphs {
+	puts "$periph : $drv_string : $sub_periphs"
+
+	for {set i 0} {$i < $sub_periphs} {incr i} {
+	    foreach arg $args {
+		set name "${pname}${device_id}_"
+	    
+		if {[string compare -nocase "CLOCK_HZ" $arg] == 0} {
+		    set xdrv_string [format "%s%s" "X" $drv_string]
+		    set value [xget_dname $xdrv_string $arg]
+		    set name "${name}CLOCK_FREQ_HZ"
+		} else {
+		    if {[string match C_* $arg]} {
+			set name [format "%s%s" $name [string range $arg 2 end]]
+		    } else {
+			set name "${name}${arg}"
+		    }
+		    set value [xget_name $periph $arg]
+		}
+
+		if {[string compare -nocase "uartns550" $drv_string] == 0} {
+		    if {[string compare -nocase "C_BASEADDR" $arg] == 0} {
+			set value [format "(%s%s%s)" $value "+" "0x1000"]
+		    }
+		}
+
+		puts $file_handle "#define $name $value"
+		if {[string compare -nocase "DEVICE_ID" $arg] == 0} {
+		    incr device_id
+		}
+	    }
+	}
+    }		
+    puts $file_handle "\n/******************************************************************/\n"
+    close $file_handle
+}
+
+##################################################
+# procedure post_generate
+# This generates the drivers directory for uboot
+# and runs the ltypes script
+##################################################
+
+proc post_generate {lib_handle} {
+    
+    global drvlist
+    
+    # Create U-Boot tree structure
+    set pwd [pwd]
+    set common_dir "uboot/board/xilinx/common"
+    set xilinx_enet_dir "uboot/board/xilinx/xilinx_enet"
+    set ml300_dir  "uboot/board/xilinx/ml300"
+    
+    exec bash -c "mkdir -p $common_dir $xilinx_enet_dir $ml300_dir"
+    
+    # Copy files for xilinx_ocp
+    xcopy_commonfiles
+
+    foreach drv $drvlist {
+	set drvname [xget_value $drv "NAME"]
+	set ver [xget_value $drv "PARAMETER" "DRIVER_VER"]
+	set ver [string map {. _} $ver]
+	set dirname [format "%s_v%s" $drvname $ver]
+	
+	if {[string compare -nocase $drvname "emac"] == 0} {
+	    xcopy_emac $drv $dirname
+	} elseif {[string compare -nocase $drvname "iic"] == 0} {
+	    xcopy_iic $drv $dirname
+	}
+    }
+    
+    # Call Ltypes Script here
+    set uboot "uboot"
+    xltype_file $uboot
+
+    # Move xparameters.h around
+    exec bash -c "cp ../../include/xparameters.h $ml300_dir"
+
+    # copy the whole U-Boot BSP to its final destination
+    set value [xget_value $lib_handle "PARAMETER" TARGET_DIR]
+    puts "TARGET_DIR : $value"
+
+    if {$value != ""} {
+        if {[file isdirectory $value] == 0} {
+            exec bash -c "mkdir -p $value"
+        }
+        exec bash -c "cp -Rp uboot/* $value"
+    }
+}
+
+proc xcopy_commonfiles {} {
+
+    global drvlist
+
+    set common_dir "uboot/board/xilinx/common"
+    
+    foreach drv $drvlist {
+	set depends [xget_value $drv "OPTION" "DEPENDS"]
+	foreach dep $depends {
+	    puts "dep : $dep"
+	    if {[file isdirectory "../$dep"] == 1} {
+		exec bash -c "cp -f ../$dep/src/*.c $common_dir"
+		exec bash -c "cp -f ../$dep/src/*.h $common_dir"
+	    }
+	}
+    }
+    
+}
+
+proc xcopy_emac {drv_handle dirname} {
+    set emac "board/xilinx/xilinx_enet"
+    xcopy_dir $dirname $emac
+}
+
+proc xcopy_iic {drv_handle dirname} {
+    set iic "board/xilinx/xilinx_iic"
+    xcopy_dir $dirname $iic
+}
+
+proc xcopy_dir {srcdir dstdir} {
+    
+    set dstdirname [format "%s%s" "uboot/" $dstdir]
+    if {[file isdirectory "../$srcdir"] == 1} {
+	# Copy files from src to dst
+	exec bash -c "mkdir -p $dstdirname"
+	exec bash -c "cp -f ../$srcdir/src/*.c $dstdirname"
+	exec bash -c "cp -f ../$srcdir/src/*.h $dstdirname"
+    } else {
+	puts "$srcdir does not exist ..."
+    }
+}
+
+
+proc xltype_file {filename} {
+
+    global ltypes
+
+    puts $filename
+
+    if {[file isdirectory $filename]} {
+	foreach entry [glob -nocomplain [file join $filename *]] {
+	    xltype_file $entry
+	}
+    } else {
+	exec bash -c "$ltypes $filename"
+    }
+    
+}
diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds
new file mode 100755
index 0000000..b6d748e
--- /dev/null
+++ b/board/xilinx/ml300/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+/*
+    cpu/ppc4xx/start.o	(.text)
+    board/xilinx/ml300/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/4xx_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+*/
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/xilinx/ml300/u-boot.lds.debug b/board/xilinx/ml300/u-boot.lds.debug
new file mode 100755
index 0000000..1608f8c
--- /dev/null
+++ b/board/xilinx/ml300/u-boot.lds.debug
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/xilinx/ml300/xparameters.h b/board/xilinx/ml300/xparameters.h
new file mode 100755
index 0000000..2c56737
--- /dev/null
+++ b/board/xilinx/ml300/xparameters.h
@@ -0,0 +1,196 @@
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by libgen.
+* Version: Xilinx EDK 6.2 EDK_Gm.11
+* DO NOT EDIT.
+*
+* Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
+*
+* Description: Driver parameters
+*
+*******************************************************************/
+
+/******************************************************************/
+
+/* U-Boot Redefines */
+
+/******************************************************************/
+
+#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
+#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
+#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
+#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
+#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
+#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
+#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
+
+/******************************************************************/
+
+#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
+#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
+#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
+#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
+
+/******************************************************************/
+
+#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
+#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
+#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
+#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
+#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
+#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
+
+/******************************************************************/
+
+#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
+
+/******************************************************************/
+
+#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
+#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
+#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
+
+/******************************************************************/
+
+#define XPAR_XPCI_NUM_INSTANCES 1
+#define XPAR_XPCI_CLOCK_HZ 33333333
+#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
+#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
+#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
+#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
+#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
+#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
+#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
+#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
+#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
+#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
+
+/******************************************************************/
+
+#define XPAR_XEMAC_NUM_INSTANCES 1
+#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
+#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
+#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
+#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
+#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
+#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
+
+/******************************************************************/
+
+#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
+#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
+#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
+#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
+#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
+#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
+#define XPAR_XGPIO_NUM_INSTANCES 2
+
+/******************************************************************/
+
+#define XPAR_XIIC_NUM_INSTANCES 1
+#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
+#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
+#define XPAR_OPB_IIC_0_DEVICE_ID 0
+#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
+
+/******************************************************************/
+
+#define XPAR_XUARTNS550_NUM_INSTANCES 2
+#define XPAR_XUARTNS550_CLOCK_HZ 100000000
+#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
+#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
+#define XPAR_OPB_UART16550_0_DEVICE_ID 0
+#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
+#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
+#define XPAR_OPB_UART16550_1_DEVICE_ID 1
+
+/******************************************************************/
+
+#define XPAR_XSPI_NUM_INSTANCES 1
+#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
+#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
+#define XPAR_OPB_SPI_0_DEVICE_ID 0
+#define XPAR_OPB_SPI_0_FIFO_EXIST 1
+#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
+#define XPAR_OPB_SPI_0_NUM_SS_BITS 1
+
+/******************************************************************/
+
+#define XPAR_XPS2_NUM_INSTANCES 2
+#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
+#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
+#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
+#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
+#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
+#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
+
+/******************************************************************/
+
+#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
+#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
+#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
+#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
+
+/******************************************************************/
+
+#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
+#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
+#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
+#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
+#define XPAR_PLB_DDR_0_BASEADDR 0x00000000
+#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
+
+/******************************************************************/
+
+#define XPAR_XINTC_HAS_IPR 1
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
+#define XPAR_XINTC_USE_DCR 0
+#define XPAR_XINTC_NUM_INSTANCES 1
+#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
+#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
+#define XPAR_DCR_INTC_0_DEVICE_ID 0
+#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
+
+/******************************************************************/
+
+#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
+#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
+#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
+#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
+#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
+#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
+#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
+#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
+#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
+#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
+#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
+#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
+#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
+#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
+#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
+#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
+#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
+#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
+
+/******************************************************************/
+
+#define XPAR_XTFT_NUM_INSTANCES 1
+#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
+#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
+#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
+
+/******************************************************************/
+
+#define XPAR_XSYSACE_MEM_WIDTH 8
+#define XPAR_XSYSACE_NUM_INSTANCES 1
+#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
+#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
+#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
+#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
+
+/******************************************************************/
+
+#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
+
+/******************************************************************/
diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c
new file mode 100755
index 0000000..1076345
--- /dev/null
+++ b/board/xilinx/xilinx_enet/emac_adapter.c
@@ -0,0 +1,158 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+
+#include <common.h>
+#include <net.h>
+#include <configs/ml300.h>
+#include "xparameters.h"
+#include "xemac.h"
+
+#if defined(XPAR_EMAC_0_DEVICE_ID)
+/*
+ * ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
+ * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
+ */
+
+#define ENET_MAX_MTU           PKTSIZE
+#define ENET_MAX_MTU_ALIGNED   PKTSIZE_ALIGN
+#define ENET_ADDR_LENGTH       6
+
+static XEmac Emac;
+static char etherrxbuff[PKTSIZE_ALIGN];	/* Receive buffer */
+
+/* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/
+#ifdef CFG_ENV_IS_NOWHERE
+static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
+#endif
+
+static int initialized = 0;
+
+void
+eth_halt(void)
+{
+	if (initialized)
+		(void) XEmac_Stop(&Emac);
+}
+
+int
+eth_init(bd_t * bis)
+{
+	u32 Options;
+	XStatus Result;
+
+#ifdef DEBUG
+	printf("EMAC Initialization Started\n\r");
+#endif
+
+	Result = XEmac_Initialize(&Emac, XPAR_EMAC_0_DEVICE_ID);
+	if (Result != XST_SUCCESS) {
+		return 0;
+	}
+
+	/* make sure the Emac is stopped before it is started */
+	(void) XEmac_Stop(&Emac);
+
+#ifdef CFG_ENV_IS_NOWHERE
+	memcpy(bis->bi_enetaddr, EMACAddr, 6);
+#endif
+
+	Result = XEmac_SetMacAddress(&Emac, bis->bi_enetaddr);
+	if (Result != XST_SUCCESS) {
+		return 0;
+	}
+
+	Options =
+	    (XEM_POLLED_OPTION | XEM_UNICAST_OPTION | XEM_BROADCAST_OPTION |
+	     XEM_FDUPLEX_OPTION | XEM_INSERT_FCS_OPTION |
+	     XEM_INSERT_PAD_OPTION);
+	Result = XEmac_SetOptions(&Emac, Options);
+	if (Result != XST_SUCCESS) {
+		return 0;
+	}
+
+	Result = XEmac_Start(&Emac);
+	if (Result != XST_SUCCESS) {
+		return 0;
+	}
+#ifdef DEBUG
+	printf("EMAC Initialization complete\n\r");
+#endif
+
+	initialized = 1;
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------------+
++-----------------------------------------------------------------------------*/
+int
+eth_send(volatile void *ptr, int len)
+{
+	XStatus Result;
+
+	if (len > ENET_MAX_MTU)
+		len = ENET_MAX_MTU;
+
+	Result = XEmac_PollSend(&Emac, (u8 *) ptr, len);
+	if (Result == XST_SUCCESS) {
+		return (1);
+	} else {
+		printf("Error while sending frame\n\r");
+		return (0);
+	}
+
+}
+
+int
+eth_rx(void)
+{
+	u32 RecvFrameLength;
+	XStatus Result;
+
+	RecvFrameLength = PKTSIZE;
+	Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
+	if (Result == XST_SUCCESS) {
+		NetReceive((uchar)etherrxbuff, RecvFrameLength);
+		return (1);
+	} else {
+		return (0);
+	}
+}
+
+#endif
diff --git a/board/xilinx/xilinx_enet/xemac.c b/board/xilinx/xilinx_enet/xemac.c
new file mode 100755
index 0000000..48b4ede
--- /dev/null
+++ b/board/xilinx/xilinx_enet/xemac.c
@@ -0,0 +1,844 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac.c
+*
+* The XEmac driver. Functions in this file are the minimum required functions
+* for this driver. See xemac.h for a detailed description of the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00b rpm  07/23/02 Removed the PHY reset from Initialize()
+* 1.00b rmm  09/23/02 Removed commented code in Initialize(). Recycled as
+*                     XEmac_mPhyReset macro in xemac_l.h.
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* 1.00c rpm  12/12/02 Changed location of IsStarted assignment in XEmac_Start
+*                     to be sure the flag is set before the device and
+*                     interrupts are enabled.
+* 1.00c rpm  02/03/03 SelfTest was not clearing polled mode. Take driver out
+*                     of polled mode in XEmac_Reset() to fix this problem.
+* 1.00c rmm  05/13/03 Fixed diab compiler warnings relating to asserts.
+* </pre>
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+#include "xipif_v1_23_b.h"	/* Uses v1.23b of the IPIF */
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static XStatus ConfigureDma(XEmac * InstancePtr);
+static XStatus ConfigureFifo(XEmac * InstancePtr);
+static void StubFifoHandler(void *CallBackRef);
+static void StubErrorHandler(void *CallBackRef, XStatus ErrorCode);
+static void StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr,
+			  u32 NumBds);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Initialize a specific XEmac instance/driver.  The initialization entails:
+* - Initialize fields of the XEmac structure
+* - Clear the Ethernet statistics for this device
+* - Initialize the IPIF component with its register base address
+* - Configure the FIFO components with their register base addresses.
+* - If the device is configured with DMA, configure the DMA channel components
+*   with their register base addresses. At some later time, memory pools for
+*   the scatter-gather descriptor lists may be passed to the driver.
+* - Reset the Ethernet MAC
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param DeviceId is the unique id of the device controlled by this XEmac
+*        instance.  Passing in a device id associates the generic XEmac
+*        instance to a specific device, as chosen by the caller or application
+*        developer.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+* - XST_DEVICE_IS_STARTED if the device has already been started
+* - XST_DEVICE_NOT_FOUND if device configuration information was not found for
+*   a device with the supplied device ID.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId)
+{
+	XStatus Result;
+	XEmac_Config *ConfigPtr;	/* configuration information */
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a status
+	 * indicating it is started.  This allows the user to stop the device
+	 * and reinitialize, but prevents a user from inadvertently initializing
+	 */
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Lookup the device configuration in the temporary CROM table. Use this
+	 * configuration info down below when initializing this component.
+	 */
+	ConfigPtr = XEmac_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		return XST_DEVICE_NOT_FOUND;
+	}
+
+	/*
+	 * Set some default values
+	 */
+	InstancePtr->IsReady = 0;
+	InstancePtr->IsStarted = 0;
+	InstancePtr->IpIfDmaConfig = ConfigPtr->IpIfDmaConfig;
+	InstancePtr->HasMii = ConfigPtr->HasMii;
+	InstancePtr->HasMulticastHash = FALSE;
+
+	/* Always default polled to false, let user configure this mode */
+	InstancePtr->IsPolled = FALSE;
+	InstancePtr->FifoRecvHandler = StubFifoHandler;
+	InstancePtr->FifoSendHandler = StubFifoHandler;
+	InstancePtr->ErrorHandler = StubErrorHandler;
+	InstancePtr->SgRecvHandler = StubSgHandler;
+	InstancePtr->SgSendHandler = StubSgHandler;
+
+	/*
+	 * Clear the statistics for this driver
+	 */
+	XEmac_mClearStruct((u8 *) & InstancePtr->Stats, sizeof (XEmac_Stats));
+
+	/*
+	 * Initialize the device register base addresses
+	 */
+	InstancePtr->BaseAddress = ConfigPtr->BaseAddress;
+
+	/*
+	 * Configure the send and receive FIFOs in the MAC
+	 */
+	Result = ConfigureFifo(InstancePtr);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	/*
+	 * If the device is configured for DMA, configure the send and receive DMA
+	 * channels in the MAC.
+	 */
+	if (XEmac_mIsDma(InstancePtr)) {
+		Result = ConfigureDma(InstancePtr);
+		if (Result != XST_SUCCESS) {
+			return Result;
+		}
+	}
+
+	/*
+	 * Indicate the component is now ready to use. Note that this is done before
+	 * we reset the device and the PHY below, which may seem a bit odd. The
+	 * choice was made to move it here rather than remove the asserts in various
+	 * functions (e.g., Reset() and all functions that it calls).  Applications
+	 * that use multiple threads, one to initialize the XEmac driver and one
+	 * waiting on the IsReady condition could have a problem with this sequence.
+	 */
+	InstancePtr->IsReady = XCOMPONENT_IS_READY;
+
+	/*
+	 * Reset the MAC to get it into its initial state. It is expected that
+	 * device configuration by the user will take place after this
+	 * initialization is done, but before the device is started.
+	 */
+	XEmac_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Start the Ethernet controller as follows:
+*   - If not in polled mode
+*       - Set the internal interrupt enable registers appropriately
+*       - Enable interrupts within the device itself. Note that connection of
+*         the driver's interrupt handler to the interrupt source (typically
+*         done using the interrupt controller component) is done by the higher
+*         layer software.
+*       - If the device is configured with scatter-gather DMA, start the DMA
+*         channels if the descriptor lists are not empty
+*   - Enable the transmitter
+*   - Enable the receiver
+*
+* The PHY is enabled after driver initialization. We assume the upper layer
+* software has configured it and the EMAC appropriately before this function
+* is called.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* - XST_SUCCESS if the device was started successfully
+* - XST_NO_CALLBACK if a callback function has not yet been registered using
+*   the SetxxxHandler function. This is required if in interrupt mode.
+* - XST_DEVICE_IS_STARTED if the device is already started
+* - XST_DMA_SG_NO_LIST if configured for scatter-gather DMA and a descriptor
+*   list has not yet been created for the send or receive channel.
+*
+* @note
+*
+* The driver tries to match the hardware configuration. So if the hardware
+* is configured with scatter-gather DMA, the driver expects to start the
+* scatter-gather channels and expects that the user has set up the buffer
+* descriptor lists already. If the user expects to use the driver in a mode
+* different than how the hardware is configured, the user should modify the
+* configuration table to reflect the mode to be used. Modifying the config
+* table is a workaround for now until we get some experience with how users
+* are intending to use the hardware in its different configurations. For
+* example, if the hardware is built with scatter-gather DMA but the user is
+* intending to use only simple DMA, the user either needs to modify the config
+* table as a workaround or rebuild the hardware with only simple DMA.
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and SetOptions functions. So if one task might be setting device
+* options while another is trying to start the device, the user is required to
+* provide protection of this shared data (typically using a semaphore).
+*
+******************************************************************************/
+XStatus
+XEmac_Start(XEmac * InstancePtr)
+{
+	u32 ControlReg;
+	XStatus Result;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * If it is already started, return a status indicating so
+	 */
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * If not polled, enable interrupts
+	 */
+	if (!InstancePtr->IsPolled) {
+		/*
+		 * Verify that the callbacks have been registered, then enable
+		 * interrupts
+		 */
+		if (XEmac_mIsSgDma(InstancePtr)) {
+			if ((InstancePtr->SgRecvHandler == StubSgHandler) ||
+			    (InstancePtr->SgSendHandler == StubSgHandler)) {
+				return XST_NO_CALLBACK;
+			}
+
+			/* Enable IPIF interrupts */
+			XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
+					      XEM_IPIF_DMA_DFT_MASK |
+					      XIIF_V123B_ERROR_MASK);
+			XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress,
+					      XEM_EIR_DFT_SG_MASK);
+
+			/* Enable scatter-gather DMA interrupts */
+			XDmaChannel_SetIntrEnable(&InstancePtr->RecvChannel,
+						  XEM_DMA_SG_INTR_MASK);
+			XDmaChannel_SetIntrEnable(&InstancePtr->SendChannel,
+						  XEM_DMA_SG_INTR_MASK);
+		} else {
+			if ((InstancePtr->FifoRecvHandler == StubFifoHandler) ||
+			    (InstancePtr->FifoSendHandler == StubFifoHandler)) {
+				return XST_NO_CALLBACK;
+			}
+
+			/* Enable IPIF interrupts (used by simple DMA also) */
+			XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
+					      XEM_IPIF_FIFO_DFT_MASK |
+					      XIIF_V123B_ERROR_MASK);
+			XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress,
+					      XEM_EIR_DFT_FIFO_MASK);
+		}
+
+		/* Enable the global IPIF interrupt output */
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+	}
+
+	/*
+	 * Indicate that the device is started before we enable the transmitter
+	 * or receiver. This needs to be done before because as soon as the
+	 * receiver is enabled we may get an interrupt, and there are functions
+	 * in the interrupt handling path that rely on the IsStarted flag.
+	 */
+	InstancePtr->IsStarted = XCOMPONENT_IS_STARTED;
+
+	/*
+	 * Enable the transmitter, and receiver (do a read/modify/write to preserve
+	 * current settings). There is no critical section here since this register
+	 * is not modified during interrupt context.
+	 */
+	ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
+	ControlReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
+	ControlReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+
+	XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg);
+
+	/*
+	 * If configured with scatter-gather DMA and not polled, restart the
+	 * DMA channels in case there are buffers ready to be sent or received into.
+	 * The DMA SgStart function uses data that can be modified during interrupt
+	 * context, so a critical section is required here.
+	 */
+	if ((XEmac_mIsSgDma(InstancePtr)) && (!InstancePtr->IsPolled)) {
+		XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+
+		/*
+		 * The only error we care about is if the list has not yet been
+		 * created, or on receive, if no buffer descriptors have been
+		 * added yet (the list is empty). Other errors are benign at this point.
+		 */
+		Result = XDmaChannel_SgStart(&InstancePtr->RecvChannel);
+		if ((Result == XST_DMA_SG_NO_LIST)
+		    || (Result == XST_DMA_SG_LIST_EMPTY)) {
+			XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+			return Result;
+		}
+
+		Result = XDmaChannel_SgStart(&InstancePtr->SendChannel);
+		if (Result == XST_DMA_SG_NO_LIST) {
+			XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+			return Result;
+		}
+
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Stop the Ethernet MAC as follows:
+*   - If the device is configured with scatter-gather DMA, stop the DMA
+*     channels (wait for acknowledgment of stop)
+*   - Disable the transmitter and receiver
+*   - Disable interrupts if not in polled mode (the higher layer software is
+*     responsible for disabling interrupts at the interrupt controller)
+*
+* The PHY is left enabled after a Stop is called.
+*
+* If the device is configured for scatter-gather DMA, the DMA engine stops at
+* the next buffer descriptor in its list. The remaining descriptors in the list
+* are not removed, so anything in the list will be transmitted or received when
+* the device is restarted. The side effect of doing this is that the last
+* buffer descriptor processed by the DMA engine before stopping may not be the
+* last descriptor in the Ethernet frame. So when the device is restarted, a
+* partial frame (i.e., a bad frame) may be transmitted/received. This is only a
+* concern if a frame can span multiple buffer descriptors, which is dependent
+* on the size of the network buffers.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* - XST_SUCCESS if the device was stopped successfully
+* - XST_DEVICE_IS_STOPPED if the device is already stopped
+*
+* @note
+*
+* This function makes use of internal resources that are shared between the
+* Start, Stop, and SetOptions functions. So if one task might be setting device
+* options while another is trying to start the device, the user is required to
+* provide protection of this shared data (typically using a semaphore).
+*
+******************************************************************************/
+XStatus
+XEmac_Stop(XEmac * InstancePtr)
+{
+	u32 ControlReg;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * If the device is already stopped, do nothing but return a status
+	 * indicating so
+	 */
+	if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STOPPED;
+	}
+
+	/*
+	 * If configured for scatter-gather DMA, stop the DMA channels. Ignore
+	 * the XST_DMA_SG_IS_STOPPED return code. There is a critical section
+	 * here between SgStart and SgStop, and SgStart can be called in interrupt
+	 * context, so disable interrupts while calling SgStop.
+	 */
+	if (XEmac_mIsSgDma(InstancePtr)) {
+		XBufDescriptor *BdTemp;	/* temporary descriptor pointer */
+
+		XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+
+		(void) XDmaChannel_SgStop(&InstancePtr->SendChannel, &BdTemp);
+		(void) XDmaChannel_SgStop(&InstancePtr->RecvChannel, &BdTemp);
+
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+	}
+
+	/*
+	 * Disable the transmitter and receiver. There is no critical section
+	 * here since this register is not modified during interrupt context.
+	 */
+	ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
+	ControlReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+	XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg);
+
+	/*
+	 * If not in polled mode, disable interrupts for IPIF (includes MAC and
+	 * DMAs)
+	 */
+	if (!InstancePtr->IsPolled) {
+		XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+	}
+
+	InstancePtr->IsStarted = 0;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Reset the Ethernet MAC. This is a graceful reset in that the device is stopped
+* first. Resets the DMA channels, the FIFOs, the transmitter, and the receiver.
+* The PHY is not reset. Any frames in the scatter-gather descriptor lists will
+* remain in the lists. The side effect of doing this is that after a reset and
+* following a restart of the device, frames that were in the list before the
+* reset may be transmitted or received. Reset must only be called after the
+* driver has been initialized.
+*
+* The driver is also taken out of polled mode if polled mode was set. The user
+* is responsbile for re-configuring the driver into polled mode after the
+* reset if desired.
+*
+* The configuration after this reset is as follows:
+*   - Half duplex
+*   - Disabled transmitter and receiver
+*   - Enabled PHY (the PHY is not reset)
+*   - MAC transmitter does pad insertion, FCS insertion, and source address
+*     overwrite.
+*   - MAC receiver does not strip padding or FCS
+*   - Interframe Gap as recommended by IEEE Std. 802.3 (96 bit times)
+*   - Unicast addressing enabled
+*   - Broadcast addressing enabled
+*   - Multicast addressing disabled (addresses are preserved)
+*   - Promiscuous addressing disabled
+*   - Default packet threshold and packet wait bound register values for
+*     scatter-gather DMA operation
+*   - MAC address of all zeros
+*   - Non-polled mode
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the MAC after the reset. Note that the PHY is not reset. PHY
+* control is left to the upper layer software. Note also that driver statistics
+* are not cleared on reset. It is up to the upper layer software to clear the
+* statistics if needed.
+*
+* When a reset is required due to an internal error, the driver notifies the
+* upper layer software of this need through the ErrorHandler callback and
+* specific status codes.  The upper layer software is responsible for calling
+* this Reset function and then re-configuring the device.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+* @internal
+*
+* The reset is accomplished by setting the IPIF reset register.  This takes
+* care of resetting all hardware blocks, including the MAC.
+*
+******************************************************************************/
+void
+XEmac_Reset(XEmac * InstancePtr)
+{
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Stop the device first
+	 */
+	(void) XEmac_Stop(InstancePtr);
+
+	/*
+	 * Take the driver out of polled mode
+	 */
+	InstancePtr->IsPolled = FALSE;
+
+	/*
+	 * Reset the entire IPIF at once.  If we choose someday to reset each
+	 * hardware block separately, the reset should occur in the direction of
+	 * data flow. For example, for the send direction the reset order is DMA
+	 * first, then FIFO, then the MAC transmitter.
+	 */
+	XIIF_V123B_RESET(InstancePtr->BaseAddress);
+
+	if (XEmac_mIsSgDma(InstancePtr)) {
+		/*
+		 * After reset, configure the scatter-gather DMA packet threshold and
+		 * packet wait bound registers to default values. Ignore the return
+		 * values of these functions since they only return error if the device
+		 * is not stopped.
+		 */
+		(void) XEmac_SetPktThreshold(InstancePtr, XEM_SEND,
+					     XEM_SGDMA_DFT_THRESHOLD);
+		(void) XEmac_SetPktThreshold(InstancePtr, XEM_RECV,
+					     XEM_SGDMA_DFT_THRESHOLD);
+		(void) XEmac_SetPktWaitBound(InstancePtr, XEM_SEND,
+					     XEM_SGDMA_DFT_WAITBOUND);
+		(void) XEmac_SetPktWaitBound(InstancePtr, XEM_RECV,
+					     XEM_SGDMA_DFT_WAITBOUND);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the MAC address for this driver/device.  The address is a 48-bit value.
+* The device must be stopped before calling this function.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param AddressPtr is a pointer to a 6-byte MAC address.
+*
+* @return
+*
+* - XST_SUCCESS if the MAC address was set successfully
+* - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr)
+{
+	u32 MacAddr = 0;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(AddressPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * The device must be stopped before setting the MAC address
+	 */
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Set the device station address high and low registers
+	 */
+	MacAddr = (AddressPtr[0] << 8) | AddressPtr[1];
+	XIo_Out32(InstancePtr->BaseAddress + XEM_SAH_OFFSET, MacAddr);
+
+	MacAddr = (AddressPtr[2] << 24) | (AddressPtr[3] << 16) |
+	    (AddressPtr[4] << 8) | AddressPtr[5];
+
+	XIo_Out32(InstancePtr->BaseAddress + XEM_SAL_OFFSET, MacAddr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the MAC address for this driver/device.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BufferPtr is an output parameter, and is a pointer to a buffer into
+*        which the current MAC address will be copied. The buffer must be at
+*        least 6 bytes.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr)
+{
+	u32 MacAddrHi;
+	u32 MacAddrLo;
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(BufferPtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	MacAddrHi = XIo_In32(InstancePtr->BaseAddress + XEM_SAH_OFFSET);
+	MacAddrLo = XIo_In32(InstancePtr->BaseAddress + XEM_SAL_OFFSET);
+
+	BufferPtr[0] = (u8) (MacAddrHi >> 8);
+	BufferPtr[1] = (u8) MacAddrHi;
+	BufferPtr[2] = (u8) (MacAddrLo >> 24);
+	BufferPtr[3] = (u8) (MacAddrLo >> 16);
+	BufferPtr[4] = (u8) (MacAddrLo >> 8);
+	BufferPtr[5] = (u8) MacAddrLo;
+}
+
+/******************************************************************************/
+/**
+*
+* Configure DMA capabilities.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* - XST_SUCCESS  if successful initialization of DMA
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static XStatus
+ConfigureDma(XEmac * InstancePtr)
+{
+	XStatus Result;
+
+	/*
+	 * Initialize the DMA channels with their base addresses. We assume
+	 * scatter-gather DMA is the only possible configuration. Descriptor space
+	 * will need to be set later by the upper layer.
+	 */
+	Result = XDmaChannel_Initialize(&InstancePtr->RecvChannel,
+					InstancePtr->BaseAddress +
+					XEM_DMA_RECV_OFFSET);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	Result = XDmaChannel_Initialize(&InstancePtr->SendChannel,
+					InstancePtr->BaseAddress +
+					XEM_DMA_SEND_OFFSET);
+
+	return Result;
+}
+
+/******************************************************************************/
+/**
+*
+* Configure the send and receive FIFO components with their base addresses
+* and interrupt masks.  Currently the base addresses are defined constants.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* XST_SUCCESS if successful initialization of the packet FIFOs
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static XStatus
+ConfigureFifo(XEmac * InstancePtr)
+{
+	XStatus Result;
+
+	/*
+	 * Return status from the packet FIFOs initialization is ignored since
+	 * they always return success.
+	 */
+	Result = XPacketFifoV100b_Initialize(&InstancePtr->RecvFifo,
+					     InstancePtr->BaseAddress +
+					     XEM_PFIFO_RXREG_OFFSET,
+					     InstancePtr->BaseAddress +
+					     XEM_PFIFO_RXDATA_OFFSET);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	Result = XPacketFifoV100b_Initialize(&InstancePtr->SendFifo,
+					     InstancePtr->BaseAddress +
+					     XEM_PFIFO_TXREG_OFFSET,
+					     InstancePtr->BaseAddress +
+					     XEM_PFIFO_TXDATA_OFFSET);
+	return Result;
+}
+
+/******************************************************************************/
+/**
+*
+* This is a stub for the scatter-gather send and recv callbacks. The stub
+* is here in case the upper layers forget to set the handlers.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param BdPtr is a pointer to the first buffer descriptor in a list
+* @param NumBds is the number of descriptors in the list.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+StubSgHandler(void *CallBackRef, XBufDescriptor * BdPtr, u32 NumBds)
+{
+	XASSERT_VOID_ALWAYS();
+}
+
+/******************************************************************************/
+/**
+*
+* This is a stub for the non-DMA send and recv callbacks.  The stub is here in
+* case the upper layers forget to set the handlers.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+StubFifoHandler(void *CallBackRef)
+{
+	XASSERT_VOID_ALWAYS();
+}
+
+/******************************************************************************/
+/**
+*
+* This is a stub for the asynchronous error callback.  The stub is here in
+* case the upper layers forget to set the handler.
+*
+* @param CallBackRef is a pointer to the upper layer callback reference
+* @param ErrorCode is the Xilinx error code, indicating the cause of the error
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+StubErrorHandler(void *CallBackRef, XStatus ErrorCode)
+{
+	XASSERT_VOID_ALWAYS();
+}
+
+/*****************************************************************************/
+/**
+*
+* Lookup the device configuration based on the unique device ID.  The table
+* EmacConfigTable contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+*
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XEmac_Config *
+XEmac_LookupConfig(u16 DeviceId)
+{
+	XEmac_Config *CfgPtr = NULL;
+	int i;
+
+	for (i = 0; i < XPAR_XEMAC_NUM_INSTANCES; i++) {
+		if (XEmac_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XEmac_ConfigTable[i];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/board/xilinx/xilinx_enet/xemac.h b/board/xilinx/xilinx_enet/xemac.h
new file mode 100755
index 0000000..ed704bf
--- /dev/null
+++ b/board/xilinx/xilinx_enet/xemac.h
@@ -0,0 +1,673 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac.h
+*
+* The Xilinx Ethernet driver component.	 This component supports the Xilinx
+* Ethernet 10/100 MAC (EMAC).
+*
+* The Xilinx Ethernet 10/100 MAC supports the following features:
+*   - Simple and scatter-gather DMA operations, as well as simple memory
+*     mapped direct I/O interface (FIFOs).
+*   - Media Independent Interface (MII) for connection to external
+*     10/100 Mbps PHY transceivers.
+*   - MII management control reads and writes with MII PHYs
+*   - Independent internal transmit and receive FIFOs
+*   - CSMA/CD compliant operations for half-duplex modes
+*   - Programmable PHY reset signal
+*   - Unicast, broadcast, and promiscuous address filtering (no multicast yet)
+*   - Internal loopback
+*   - Automatic source address insertion or overwrite (programmable)
+*   - Automatic FCS insertion and stripping (programmable)
+*   - Automatic pad insertion and stripping (programmable)
+*   - Pause frame (flow control) detection in full-duplex mode
+*   - Programmable interframe gap
+*   - VLAN frame support.
+*   - Pause frame support
+*
+* The device driver supports all the features listed above.
+*
+* <b>Driver Description</b>
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the EMAC. The driver handles transmission and reception of
+* Ethernet frames, as well as configuration of the controller. It does not
+* handle protocol stack functionality such as Link Layer Control (LLC) or the
+* Address Resolution Protocol (ARP). The protocol stack that makes use of the
+* driver handles this functionality. This implies that the driver is simply a
+* pass-through mechanism between a protocol stack and the EMAC. A single device
+* driver can support multiple EMACs.
+*
+* The driver is designed for a zero-copy buffer scheme. That is, the driver will
+* not copy buffers. This avoids potential throughput bottlenecks within the
+* driver.
+*
+* Since the driver is a simple pass-through mechanism between a protocol stack
+* and the EMAC, no assembly or disassembly of Ethernet frames is done at the
+* driver-level. This assumes that the protocol stack passes a correctly
+* formatted Ethernet frame to the driver for transmission, and that the driver
+* does not validate the contents of an incoming frame
+*
+* <b>PHY Communication</b>
+*
+* The driver provides rudimentary read and write functions to allow the higher
+* layer software to access the PHY. The EMAC provides MII registers for the
+* driver to access. This management interface can be parameterized away in the
+* FPGA implementation process. If this is the case, the PHY read and write
+* functions of the driver return XST_NO_FEATURE.
+*
+* External loopback is usually supported at the PHY. It is up to the user to
+* turn external loopback on or off at the PHY. The driver simply provides pass-
+* through functions for configuring the PHY. The driver does not read, write,
+* or reset the PHY on its own. All control of the PHY must be done by the user.
+*
+* <b>Asynchronous Callbacks</b>
+*
+* The driver services interrupts and passes Ethernet frames to the higher layer
+* software through asynchronous callback functions. When using the driver
+* directly (i.e., not with the RTOS protocol stack), the higher layer
+* software must register its callback functions during initialization. The
+* driver requires callback functions for received frames, for confirmation of
+* transmitted frames, and for asynchronous errors.
+*
+* <b>Interrupts</b>
+*
+* The driver has no dependencies on the interrupt controller. The driver
+* provides two interrupt handlers.  XEmac_IntrHandlerDma() handles interrupts
+* when the EMAC is configured with scatter-gather DMA.	XEmac_IntrHandlerFifo()
+* handles interrupts when the EMAC is configured for direct FIFO I/O or simple
+* DMA.	Either of these routines can be connected to the system interrupt
+* controller by the user.
+*
+* <b>Interrupt Frequency</b>
+*
+* When the EMAC is configured with scatter-gather DMA, the frequency of
+* interrupts can be controlled with the interrupt coalescing features of the
+* scatter-gather DMA engine. The frequency of interrupts can be adjusted using
+* the driver API functions for setting the packet count threshold and the packet
+* wait bound values.
+*
+* The scatter-gather DMA engine only interrupts when the packet count threshold
+* is reached, instead of interrupting for each packet. A packet is a generic
+* term used by the scatter-gather DMA engine, and is equivalent to an Ethernet
+* frame in our case.
+*
+* The packet wait bound is a timer value used during interrupt coalescing to
+* trigger an interrupt when not enough packets have been received to reach the
+* packet count threshold.
+*
+* These values can be tuned by the user to meet their needs. If there appear to
+* be interrupt latency problems or delays in packet arrival that are longer than
+* might be expected, the user should verify that the packet count threshold is
+* set low enough to receive interrupts before the wait bound timer goes off.
+*
+* <b>Device Reset</b>
+*
+* Some errors that can occur in the device require a device reset. These errors
+* are listed in the XEmac_SetErrorHandler() function header. The user's error
+* handler is responsible for resetting the device and re-configuring it based on
+* its needs (the driver does not save the current configuration). When
+* integrating into an RTOS, these reset and re-configure obligations are
+* taken care of by the Xilinx adapter software if it exists for that RTOS.
+*
+* <b>Device Configuration</b>
+*
+* The device can be configured in various ways during the FPGA implementation
+* process.  Configuration parameters are stored in the xemac_g.c files.
+* A table is defined where each entry contains configuration information
+* for an EMAC device.  This information includes such things as the base address
+* of the memory-mapped device, the base addresses of IPIF, DMA, and FIFO modules
+* within the device, and whether the device has DMA, counter registers,
+* multicast support, MII support, and flow control.
+*
+* The driver tries to use the features built into the device. So if, for
+* example, the hardware is configured with scatter-gather DMA, the driver
+* expects to start the scatter-gather channels and expects that the user has set
+* up the buffer descriptor lists already. If the user expects to use the driver
+* in a mode different than how the hardware is configured, the user should
+* modify the configuration table to reflect the mode to be used. Modifying the
+* configuration table is a workaround for now until we get some experience with
+* how users are intending to use the hardware in its different configurations.
+* For example, if the hardware is built with scatter-gather DMA but the user is
+* intending to use only simple DMA, the user either needs to modify the config
+* table as a workaround or rebuild the hardware with only simple DMA. The
+* recommendation at this point is to build the hardware with the features you
+* intend to use. If you're inclined to modify the table, do so before the call
+* to XEmac_Initialize().  Here is a snippet of code that changes a device to
+* simple DMA (the hardware needs to have DMA for this to work of course):
+* <pre>
+*	 XEmac_Config *ConfigPtr;
+*
+*	 ConfigPtr = XEmac_LookupConfig(DeviceId);
+*	 ConfigPtr->IpIfDmaConfig = XEM_CFG_SIMPLE_DMA;
+* </pre>
+*
+* <b>Simple DMA</b>
+*
+* Simple DMA is supported through the FIFO functions, FifoSend and FifoRecv, of
+* the driver (i.e., there is no separate interface for it). The driver makes use
+* of the DMA engine for a simple DMA transfer if the device is configured with
+* DMA, otherwise it uses the FIFOs directly. While the simple DMA interface is
+* therefore transparent to the user, the caching of network buffers is not.
+* If the device is configured with DMA and the FIFO interface is used, the user
+* must ensure that the network buffers are not cached or are cache coherent,
+* since DMA will be used to transfer to and from the Emac device. If the device
+* is configured with DMA and the user really wants to use the FIFOs directly,
+* the user should rebuild the hardware without DMA. If unable to do this, there
+* is a workaround (described above in Device Configuration) to modify the
+* configuration table of the driver to fake the driver into thinking the device
+* has no DMA. A code snippet follows:
+* <pre>
+*	 XEmac_Config *ConfigPtr;
+*
+*	 ConfigPtr = XEmac_LookupConfig(DeviceId);
+*	 ConfigPtr->IpIfDmaConfig = XEM_CFG_NO_DMA;
+* </pre>
+*
+* <b>Asserts</b>
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* <b>Building the driver</b>
+*
+* The XEmac driver is composed of several source files. Why so many?  This
+* allows the user to build and link only those parts of the driver that are
+* necessary. Since the EMAC hardware can be configured in various ways (e.g.,
+* with or without DMA), the driver too can be built with varying features.
+* For the most part, this means that besides always linking in xemac.c, you
+* link in only the driver functionality you want. Some of the choices you have
+* are polled vs. interrupt, interrupt with FIFOs only vs. interrupt with DMA,
+* self-test diagnostics, and driver statistics. Note that currently the DMA code
+* must be linked in, even if you don't have DMA in the device.
+*
+* @note
+*
+* Xilinx drivers are typically composed of two components, one is the driver
+* and the other is the adapter.	 The driver is independent of OS and processor
+* and is intended to be highly portable.  The adapter is OS-specific and
+* facilitates communication between the driver and an OS.
+* <br><br>
+* This driver is intended to be RTOS and processor independent.	 It works
+* with physical addresses only.	 Any needs for dynamic memory management,
+* threads or thread mutual exclusion, virtual memory, or cache control must
+* be satisfied by the layer above this driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00b rpm  10/08/02 Replaced HasSgDma boolean with IpifDmaConfig enumerated
+*		      configuration parameter
+* 1.00c rpm  12/05/02 New version includes support for simple DMA and the delay
+*		      argument to SgSend
+* 1.00c rpm  02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
+*		      from SetPktThreshold in the internal DMA driver. Also
+*		      avoided compiler warnings by initializing Result in the
+*		      DMA interrupt service routines.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMAC_H			/* prevent circular inclusions */
+#define XEMAC_H			/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xpacket_fifo_v1_00_b.h"	/* Uses v1.00b of Packet Fifo */
+#include "xdma_channel.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * Device information
+ */
+#define XEM_DEVICE_NAME	    "xemac"
+#define XEM_DEVICE_DESC	    "Xilinx Ethernet 10/100 MAC"
+
+/** @name Configuration options
+ *
+ * Device configuration options (see the XEmac_SetOptions() and
+ * XEmac_GetOptions() for information on how to use these options)
+ * @{
+ */
+/**
+ * <pre>
+ *   XEM_BROADCAST_OPTION	 Broadcast addressing on or off (default is on)
+ *   XEM_UNICAST_OPTION		 Unicast addressing on or off (default is on)
+ *   XEM_PROMISC_OPTION		 Promiscuous addressing on or off (default is off)
+ *   XEM_FDUPLEX_OPTION		 Full duplex on or off (default is off)
+ *   XEM_POLLED_OPTION		 Polled mode on or off (default is off)
+ *   XEM_LOOPBACK_OPTION	 Internal loopback on or off (default is off)
+ *   XEM_FLOW_CONTROL_OPTION	 Interpret pause frames in full duplex mode
+ *				 (default is off)
+ *   XEM_INSERT_PAD_OPTION	 Pad short frames on transmit (default is on)
+ *   XEM_INSERT_FCS_OPTION	 Insert FCS (CRC) on transmit (default is on)
+ *   XEM_INSERT_ADDR_OPTION	 Insert source address on transmit (default is on)
+ *   XEM_OVWRT_ADDR_OPTION	 Overwrite source address on transmit. This is
+ *				 only used if source address insertion is on.
+ *				 (default is on)
+ *   XEM_STRIP_PAD_FCS_OPTION	 Strip FCS and padding from received frames
+ *				 (default is off)
+  * </pre>
+ */
+#define XEM_UNICAST_OPTION	  0x00000001UL
+#define XEM_BROADCAST_OPTION	  0x00000002UL
+#define XEM_PROMISC_OPTION	  0x00000004UL
+#define XEM_FDUPLEX_OPTION	  0x00000008UL
+#define XEM_POLLED_OPTION	  0x00000010UL
+#define XEM_LOOPBACK_OPTION	  0x00000020UL
+#define XEM_FLOW_CONTROL_OPTION	  0x00000080UL
+#define XEM_INSERT_PAD_OPTION	  0x00000100UL
+#define XEM_INSERT_FCS_OPTION	  0x00000200UL
+#define XEM_INSERT_ADDR_OPTION	  0x00000400UL
+#define XEM_OVWRT_ADDR_OPTION	  0x00000800UL
+#define XEM_STRIP_PAD_FCS_OPTION  0x00002000UL
+/*@}*/
+/*
+ * Not supported yet:
+ *   XEM_MULTICAST_OPTION	 Multicast addressing on or off (default is off)
+ */
+/* NOT SUPPORTED YET... */
+#define XEM_MULTICAST_OPTION	  0x00000040UL
+
+/*
+ * Some default values for interrupt coalescing within the scatter-gather
+ * DMA engine.
+ */
+#define XEM_SGDMA_DFT_THRESHOLD	    1	/* Default pkt threshold */
+#define XEM_SGDMA_MAX_THRESHOLD	    255 /* Maximum pkt theshold */
+#define XEM_SGDMA_DFT_WAITBOUND	    5	/* Default pkt wait bound (msec) */
+#define XEM_SGDMA_MAX_WAITBOUND	    1023	/* Maximum pkt wait bound (msec) */
+
+/*
+ * Direction identifiers. These are used for setting values like packet
+ * thresholds and wait bound for specific channels
+ */
+#define XEM_SEND    1
+#define XEM_RECV    2
+
+/*
+ * Arguments to SgSend function to indicate whether to hold off starting
+ * the scatter-gather engine.
+ */
+#define XEM_SGDMA_NODELAY     0 /* start SG DMA immediately */
+#define XEM_SGDMA_DELAY	      1 /* do not start SG DMA */
+
+/*
+ * Constants to determine the configuration of the hardware device. They are
+ * used to allow the driver to verify it can operate with the hardware.
+ */
+#define XEM_CFG_NO_IPIF		    0	/* Not supported by the driver */
+#define XEM_CFG_NO_DMA		    1	/* No DMA */
+#define XEM_CFG_SIMPLE_DMA	    2	/* Simple DMA */
+#define XEM_CFG_DMA_SG		    3	/* DMA scatter gather */
+
+/*
+ * The next few constants help upper layers determine the size of memory
+ * pools used for Ethernet buffers and descriptor lists.
+ */
+#define XEM_MAC_ADDR_SIZE   6	/* six-byte MAC address */
+#define XEM_MTU		    1500	/* max size of Ethernet frame */
+#define XEM_HDR_SIZE	    14	/* size of Ethernet header */
+#define XEM_HDR_VLAN_SIZE   18	/* size of Ethernet header with VLAN */
+#define XEM_TRL_SIZE	    4	/* size of Ethernet trailer (FCS) */
+#define XEM_MAX_FRAME_SIZE  (XEM_MTU + XEM_HDR_SIZE + XEM_TRL_SIZE)
+#define XEM_MAX_VLAN_FRAME_SIZE	 (XEM_MTU + XEM_HDR_VLAN_SIZE + XEM_TRL_SIZE)
+
+/*
+ * Define a default number of send and receive buffers
+ */
+#define XEM_MIN_RECV_BUFS   32	/* minimum # of recv buffers */
+#define XEM_DFT_RECV_BUFS   64	/* default # of recv buffers */
+
+#define XEM_MIN_SEND_BUFS   16	/* minimum # of send buffers */
+#define XEM_DFT_SEND_BUFS   32	/* default # of send buffers */
+
+#define XEM_MIN_BUFFERS	    (XEM_MIN_RECV_BUFS + XEM_MIN_SEND_BUFS)
+#define XEM_DFT_BUFFERS	    (XEM_DFT_RECV_BUFS + XEM_DFT_SEND_BUFS)
+
+/*
+ * Define the number of send and receive buffer descriptors, used for
+ * scatter-gather DMA
+ */
+#define XEM_MIN_RECV_DESC   16	/* minimum # of recv descriptors */
+#define XEM_DFT_RECV_DESC   32	/* default # of recv descriptors */
+
+#define XEM_MIN_SEND_DESC   8	/* minimum # of send descriptors */
+#define XEM_DFT_SEND_DESC   16	/* default # of send descriptors */
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * Ethernet statistics (see XEmac_GetStats() and XEmac_ClearStats())
+ */
+typedef struct {
+	u32 XmitFrames;		 /**< Number of frames transmitted */
+	u32 XmitBytes;		 /**< Number of bytes transmitted */
+	u32 XmitLateCollisionErrors;
+				 /**< Number of transmission failures
+					  due to late collisions */
+	u32 XmitExcessDeferral;	 /**< Number of transmission failures
+					  due o excess collision deferrals */
+	u32 XmitOverrunErrors;	 /**< Number of transmit overrun errors */
+	u32 XmitUnderrunErrors;	 /**< Number of transmit underrun errors */
+	u32 RecvFrames;		 /**< Number of frames received */
+	u32 RecvBytes;		 /**< Number of bytes received */
+	u32 RecvFcsErrors;	 /**< Number of frames discarded due
+					  to FCS errors */
+	u32 RecvAlignmentErrors; /**< Number of frames received with
+					  alignment errors */
+	u32 RecvOverrunErrors;	 /**< Number of frames discarded due
+					  to overrun errors */
+	u32 RecvUnderrunErrors;	 /**< Number of recv underrun errors */
+	u32 RecvMissedFrameErrors;
+				 /**< Number of frames missed by MAC */
+	u32 RecvCollisionErrors; /**< Number of frames discarded due
+					  to collisions */
+	u32 RecvLengthFieldErrors;
+				 /**< Number of frames discarded with
+					  invalid length field */
+	u32 RecvShortErrors;	 /**< Number of short frames discarded */
+	u32 RecvLongErrors;	 /**< Number of long frames discarded */
+	u32 DmaErrors;		 /**< Number of DMA errors since init */
+	u32 FifoErrors;		 /**< Number of FIFO errors since init */
+	u32 RecvInterrupts;	 /**< Number of receive interrupts */
+	u32 XmitInterrupts;	 /**< Number of transmit interrupts */
+	u32 EmacInterrupts;	 /**< Number of MAC (device) interrupts */
+	u32 TotalIntrs;		 /**< Total interrupts */
+} XEmac_Stats;
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;	    /**< Unique ID  of device */
+	u32 BaseAddress;    /**< Register base address */
+	u32 HasCounters;   /**< Does device have counters? */
+	u8 IpIfDmaConfig;   /**< IPIF/DMA hardware configuration */
+	u32 HasMii;	   /**< Does device support MII? */
+
+} XEmac_Config;
+
+/** @name Typedefs for callbacks
+ * Callback functions.
+ * @{
+ */
+/**
+ * Callback when data is sent or received with scatter-gather DMA.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ *	  when setting the callback functions, and passed back to the upper
+ *	  layer when the callback is invoked.
+ * @param BdPtr is a pointer to the first buffer descriptor in a list of
+ *	  buffer descriptors.
+ * @param NumBds is the number of buffer descriptors in the list pointed
+ *	  to by BdPtr.
+ */
+typedef void (*XEmac_SgHandler) (void *CallBackRef, XBufDescriptor * BdPtr,
+				 u32 NumBds);
+
+/**
+ * Callback when data is sent or received with direct FIFO communication or
+ * simple DMA. The user typically defines two callacks, one for send and one
+ * for receive.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ *	  when setting the callback functions, and passed back to the upper
+ *	  layer when the callback is invoked.
+ */
+typedef void (*XEmac_FifoHandler) (void *CallBackRef);
+
+/**
+ * Callback when an asynchronous error occurs.
+ *
+ * @param CallBackRef is a callback reference passed in by the upper layer
+ *	  when setting the callback functions, and passed back to the upper
+ *	  layer when the callback is invoked.
+ * @param ErrorCode is a Xilinx error code defined in xstatus.h.  Also see
+ *	  XEmac_SetErrorHandler() for a description of possible errors.
+ */
+typedef void (*XEmac_ErrorHandler) (void *CallBackRef, XStatus ErrorCode);
+/*@}*/
+
+/**
+ * The XEmac driver instance data. The user is required to allocate a
+ * variable of this type for every EMAC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	u32 BaseAddress;	/* Base address (of IPIF) */
+	u32 IsStarted;		/* Device is currently started */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 IsPolled;		/* Device is in polled mode */
+	u8 IpIfDmaConfig;	/* IPIF/DMA hardware configuration */
+	u32 HasMii;		/* Does device support MII? */
+	u32 HasMulticastHash;	/* Does device support multicast hash table? */
+
+	XEmac_Stats Stats;
+	XPacketFifoV100b RecvFifo;	/* FIFO used to receive frames */
+	XPacketFifoV100b SendFifo;	/* FIFO used to send frames */
+
+	/*
+	 * Callbacks
+	 */
+	XEmac_FifoHandler FifoRecvHandler;	/* for non-DMA/simple DMA interrupts */
+	void *FifoRecvRef;
+	XEmac_FifoHandler FifoSendHandler;	/* for non-DMA/simple DMA interrupts */
+	void *FifoSendRef;
+	XEmac_ErrorHandler ErrorHandler;	/* for asynchronous errors */
+	void *ErrorRef;
+
+	XDmaChannel RecvChannel;	/* DMA receive channel driver */
+	XDmaChannel SendChannel;	/* DMA send channel driver */
+
+	XEmac_SgHandler SgRecvHandler;	/* callback for scatter-gather DMA */
+	void *SgRecvRef;
+	XEmac_SgHandler SgSendHandler;	/* callback for scatter-gather DMA */
+	void *SgSendRef;
+} XEmac;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* This macro determines if the device is currently configured for
+* scatter-gather DMA.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured for scatter-gather DMA, or FALSE
+* if it is not.
+*
+* @note
+*
+* Signature: u32 XEmac_mIsSgDma(XEmac *InstancePtr)
+*
+******************************************************************************/
+#define XEmac_mIsSgDma(InstancePtr) \
+	    ((InstancePtr)->IpIfDmaConfig == XEM_CFG_DMA_SG)
+
+/*****************************************************************************/
+/**
+*
+* This macro determines if the device is currently configured for simple DMA.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured for simple DMA, or FALSE otherwise
+*
+* @note
+*
+* Signature: u32 XEmac_mIsSimpleDma(XEmac *InstancePtr)
+*
+******************************************************************************/
+#define XEmac_mIsSimpleDma(InstancePtr) \
+	    ((InstancePtr)->IpIfDmaConfig == XEM_CFG_SIMPLE_DMA)
+
+/*****************************************************************************/
+/**
+*
+* This macro determines if the device is currently configured with DMA (either
+* simple DMA or scatter-gather DMA)
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Boolean TRUE if the device is configured with DMA, or FALSE otherwise
+*
+* @note
+*
+* Signature: u32 XEmac_mIsDma(XEmac *InstancePtr)
+*
+******************************************************************************/
+#define XEmac_mIsDma(InstancePtr) \
+	    (XEmac_mIsSimpleDma(InstancePtr) || XEmac_mIsSgDma(InstancePtr))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xemac.c
+ */
+XStatus XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId);
+XStatus XEmac_Start(XEmac * InstancePtr);
+XStatus XEmac_Stop(XEmac * InstancePtr);
+void XEmac_Reset(XEmac * InstancePtr);
+XEmac_Config *XEmac_LookupConfig(u16 DeviceId);
+
+/*
+ * Diagnostic functions in xemac_selftest.c
+ */
+XStatus XEmac_SelfTest(XEmac * InstancePtr);
+
+/*
+ * Polled functions in xemac_polled.c
+ */
+XStatus XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
+XStatus XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
+
+/*
+ * Interrupts with scatter-gather DMA functions in xemac_intr_dma.c
+ */
+XStatus XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay);
+XStatus XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr);
+XStatus XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold);
+XStatus XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction,
+			      u8 * ThreshPtr);
+XStatus XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction,
+			      u32 TimerValue);
+XStatus XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction,
+			      u32 * WaitPtr);
+XStatus XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr,
+			     u32 ByteCount);
+XStatus XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr,
+			     u32 ByteCount);
+void XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef,
+			    XEmac_SgHandler FuncPtr);
+void XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef,
+			    XEmac_SgHandler FuncPtr);
+
+void XEmac_IntrHandlerDma(void *InstancePtr);	/* interrupt handler */
+
+/*
+ * Interrupts with direct FIFO functions in xemac_intr_fifo.c. Also used
+ * for simple DMA.
+ */
+XStatus XEmac_FifoSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
+XStatus XEmac_FifoRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
+void XEmac_SetFifoRecvHandler(XEmac * InstancePtr, void *CallBackRef,
+			      XEmac_FifoHandler FuncPtr);
+void XEmac_SetFifoSendHandler(XEmac * InstancePtr, void *CallBackRef,
+			      XEmac_FifoHandler FuncPtr);
+
+void XEmac_IntrHandlerFifo(void *InstancePtr);	/* interrupt handler */
+
+/*
+ * General interrupt-related functions in xemac_intr.c
+ */
+void XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
+			   XEmac_ErrorHandler FuncPtr);
+
+/*
+ * MAC configuration in xemac_options.c
+ */
+XStatus XEmac_SetOptions(XEmac * InstancePtr, u32 OptionFlag);
+u32 XEmac_GetOptions(XEmac * InstancePtr);
+XStatus XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr);
+void XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr);
+XStatus XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2);
+void XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr);
+
+/*
+ * Multicast functions in xemac_multicast.c (not supported by EMAC yet)
+ */
+XStatus XEmac_MulticastAdd(XEmac * InstancePtr, u8 * AddressPtr);
+XStatus XEmac_MulticastClear(XEmac * InstancePtr);
+
+/*
+ * PHY configuration in xemac_phy.c
+ */
+XStatus XEmac_PhyRead(XEmac * InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 * PhyDataPtr);
+XStatus XEmac_PhyWrite(XEmac * InstancePtr, u32 PhyAddress,
+		       u32 RegisterNum, u16 PhyData);
+
+/*
+ * Statistics in xemac_stats.c
+ */
+void XEmac_GetStats(XEmac * InstancePtr, XEmac_Stats * StatsPtr);
+void XEmac_ClearStats(XEmac * InstancePtr);
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/xilinx_enet/xemac_g.c b/board/xilinx/xilinx_enet/xemac_g.c
new file mode 100755
index 0000000..9340f91
--- /dev/null
+++ b/board/xilinx/xilinx_enet/xemac_g.c
@@ -0,0 +1,60 @@
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by libgen.
+* Version: Xilinx EDK 6.1.2 EDK_G.14
+* DO NOT EDIT.
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemac.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmac_Config XEmac_ConfigTable[] = {
+	{
+	 XPAR_OPB_ETHERNET_0_DEVICE_ID,
+	 XPAR_OPB_ETHERNET_0_BASEADDR,
+	 XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST,
+	 XPAR_OPB_ETHERNET_0_DMA_PRESENT,
+	 XPAR_OPB_ETHERNET_0_MII_EXIST}
+};
diff --git a/board/xilinx/xilinx_enet/xemac_i.h b/board/xilinx/xilinx_enet/xemac_i.h
new file mode 100755
index 0000000..9c160f3
--- /dev/null
+++ b/board/xilinx/xilinx_enet/xemac_i.h
@@ -0,0 +1,207 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_i.h
+*
+* This header file contains internal identifiers, which are those shared
+* between XEmac components.  The identifiers in this file are not intended for
+* use external to the driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00b rpm  04/29/02 Moved register definitions to xemac_l.h
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMAC_I_H		/* prevent circular inclusions */
+#define XEMAC_I_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xemac.h"
+#include "xemac_l.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * Default buffer descriptor control word masks. The default send BD control
+ * is set for incrementing the source address by one for each byte transferred,
+ * and specify that the destination address (FIFO) is local to the device. The
+ * default receive BD control is set for incrementing the destination address
+ * by one for each byte transferred, and specify that the source address is
+ * local to the device.
+ */
+#define XEM_DFT_SEND_BD_MASK	(XDC_DMACR_SOURCE_INCR_MASK | \
+				 XDC_DMACR_DEST_LOCAL_MASK)
+#define XEM_DFT_RECV_BD_MASK	(XDC_DMACR_DEST_INCR_MASK |  \
+				 XDC_DMACR_SOURCE_LOCAL_MASK)
+
+/*
+ * Masks for the IPIF Device Interrupt enable and status registers.
+ */
+#define XEM_IPIF_EMAC_MASK	0x00000004UL	/* MAC interrupt */
+#define XEM_IPIF_SEND_DMA_MASK	0x00000008UL	/* Send DMA interrupt */
+#define XEM_IPIF_RECV_DMA_MASK	0x00000010UL	/* Receive DMA interrupt */
+#define XEM_IPIF_RECV_FIFO_MASK 0x00000020UL	/* Receive FIFO interrupt */
+#define XEM_IPIF_SEND_FIFO_MASK 0x00000040UL	/* Send FIFO interrupt */
+
+/*
+ * Default IPIF Device Interrupt mask when configured for DMA
+ */
+#define XEM_IPIF_DMA_DFT_MASK	(XEM_IPIF_SEND_DMA_MASK |   \
+				 XEM_IPIF_RECV_DMA_MASK |   \
+				 XEM_IPIF_EMAC_MASK |	    \
+				 XEM_IPIF_SEND_FIFO_MASK |  \
+				 XEM_IPIF_RECV_FIFO_MASK)
+
+/*
+ * Default IPIF Device Interrupt mask when configured without DMA
+ */
+#define XEM_IPIF_FIFO_DFT_MASK	(XEM_IPIF_EMAC_MASK |	    \
+				 XEM_IPIF_SEND_FIFO_MASK |  \
+				 XEM_IPIF_RECV_FIFO_MASK)
+
+#define XEM_IPIF_DMA_DEV_INTR_COUNT   7 /* Number of interrupt sources */
+#define XEM_IPIF_FIFO_DEV_INTR_COUNT  5 /* Number of interrupt sources */
+#define XEM_IPIF_DEVICE_INTR_COUNT  7	/* Number of interrupt sources */
+#define XEM_IPIF_IP_INTR_COUNT	    22	/* Number of MAC interrupts */
+
+/* a mask for all transmit interrupts, used in polled mode */
+#define XEM_EIR_XMIT_ALL_MASK	(XEM_EIR_XMIT_DONE_MASK |	    \
+				 XEM_EIR_XMIT_ERROR_MASK |	    \
+				 XEM_EIR_XMIT_SFIFO_EMPTY_MASK |    \
+				 XEM_EIR_XMIT_LFIFO_FULL_MASK)
+
+/* a mask for all receive interrupts, used in polled mode */
+#define XEM_EIR_RECV_ALL_MASK	(XEM_EIR_RECV_DONE_MASK |	    \
+				 XEM_EIR_RECV_ERROR_MASK |	    \
+				 XEM_EIR_RECV_LFIFO_EMPTY_MASK |    \
+				 XEM_EIR_RECV_LFIFO_OVER_MASK |	    \
+				 XEM_EIR_RECV_LFIFO_UNDER_MASK |    \
+				 XEM_EIR_RECV_DFIFO_OVER_MASK |	    \
+				 XEM_EIR_RECV_MISSED_FRAME_MASK |   \
+				 XEM_EIR_RECV_COLLISION_MASK |	    \
+				 XEM_EIR_RECV_FCS_ERROR_MASK |	    \
+				 XEM_EIR_RECV_LEN_ERROR_MASK |	    \
+				 XEM_EIR_RECV_SHORT_ERROR_MASK |    \
+				 XEM_EIR_RECV_LONG_ERROR_MASK |	    \
+				 XEM_EIR_RECV_ALIGN_ERROR_MASK)
+
+/* a default interrupt mask for scatter-gather DMA operation */
+#define XEM_EIR_DFT_SG_MASK    (XEM_EIR_RECV_ERROR_MASK |	    \
+				XEM_EIR_RECV_LFIFO_OVER_MASK |	    \
+				XEM_EIR_RECV_LFIFO_UNDER_MASK |	    \
+				XEM_EIR_XMIT_SFIFO_OVER_MASK |	    \
+				XEM_EIR_XMIT_SFIFO_UNDER_MASK |	    \
+				XEM_EIR_XMIT_LFIFO_OVER_MASK |	    \
+				XEM_EIR_XMIT_LFIFO_UNDER_MASK |	    \
+				XEM_EIR_RECV_DFIFO_OVER_MASK |	    \
+				XEM_EIR_RECV_MISSED_FRAME_MASK |    \
+				XEM_EIR_RECV_COLLISION_MASK |	    \
+				XEM_EIR_RECV_FCS_ERROR_MASK |	    \
+				XEM_EIR_RECV_LEN_ERROR_MASK |	    \
+				XEM_EIR_RECV_SHORT_ERROR_MASK |	    \
+				XEM_EIR_RECV_LONG_ERROR_MASK |	    \
+				XEM_EIR_RECV_ALIGN_ERROR_MASK)
+
+/* a default interrupt mask for non-DMA operation (direct FIFOs) */
+#define XEM_EIR_DFT_FIFO_MASK  (XEM_EIR_XMIT_DONE_MASK |	    \
+				XEM_EIR_RECV_DONE_MASK |	    \
+				XEM_EIR_DFT_SG_MASK)
+
+/*
+ * Mask for the DMA interrupt enable and status registers when configured
+ * for scatter-gather DMA.
+ */
+#define XEM_DMA_SG_INTR_MASK	(XDC_IXR_DMA_ERROR_MASK	 |	\
+				 XDC_IXR_PKT_THRESHOLD_MASK |	\
+				 XDC_IXR_PKT_WAIT_BOUND_MASK |	\
+				 XDC_IXR_SG_END_MASK)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/*
+*
+* Clears a structure of given size, in bytes, by setting each byte to 0.
+*
+* @param StructPtr is a pointer to the structure to be cleared.
+* @param NumBytes is the number of bytes in the structure.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* Signature: void XEmac_mClearStruct(u8 *StructPtr, unsigned int NumBytes)
+*
+******************************************************************************/
+#define XEmac_mClearStruct(StructPtr, NumBytes)	    \
+{						    \
+    int i;					    \
+    u8 *BytePtr = (u8 *)(StructPtr);	    \
+    for (i=0; i < (unsigned int)(NumBytes); i++)    \
+    {						    \
+	*BytePtr++ = 0;				    \
+    }						    \
+}
+
+/************************** Variable Definitions *****************************/
+
+extern XEmac_Config XEmac_ConfigTable[];
+
+/************************** Function Prototypes ******************************/
+
+void XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus);
+void XEmac_CheckFifoRecvError(XEmac * InstancePtr);
+void XEmac_CheckFifoSendError(XEmac * InstancePtr);
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/xilinx_enet/xemac_intr.c b/board/xilinx/xilinx_enet/xemac_intr.c
new file mode 100755
index 0000000..b9a2621
--- /dev/null
+++ b/board/xilinx/xilinx_enet/xemac_intr.c
@@ -0,0 +1,402 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_intr.c
+*
+* This file contains general interrupt-related functions of the XEmac driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* 1.00c rpm  03/31/03 Added comment to indicate that no Receive Length FIFO
+*                     overrun interrupts occur in v1.00l and later of the EMAC
+*                     device. This avoids the need to reset the device on
+*                     receive overruns.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+#include "xipif_v1_23_b.h"	/* Uses v1.23b of the IPIF */
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Set the callback function for handling asynchronous errors.  The upper layer
+* software should call this function during initialization.
+*
+* The error callback is invoked by the driver within interrupt context, so it
+* needs to do its job quickly. If there are potentially slow operations within
+* the callback, these should be done at task-level.
+*
+* The Xilinx errors that must be handled by the callback are:
+* - XST_DMA_ERROR indicates an unrecoverable DMA error occurred. This is
+*   typically a bus error or bus timeout. The handler must reset and
+*   re-configure the device.
+* - XST_FIFO_ERROR indicates an unrecoverable FIFO error occurred. This is a
+*   deadlock condition in the packet FIFO. The handler must reset and
+*   re-configure the device.
+* - XST_RESET_ERROR indicates an unrecoverable MAC error occurred, usually an
+*   overrun or underrun. The handler must reset and re-configure the device.
+* - XST_DMA_SG_NO_LIST indicates an attempt was made to access a scatter-gather
+*   DMA list that has not yet been created.
+* - XST_DMA_SG_LIST_EMPTY indicates the driver tried to get a descriptor from
+*   the receive descriptor list, but the list was empty.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param CallBackRef is a reference pointer to be passed back to the adapter in
+*        the callback. This helps the adapter correlate the callback to a
+*        particular driver.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
+		      XEmac_ErrorHandler FuncPtr)
+{
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(FuncPtr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	InstancePtr->ErrorHandler = FuncPtr;
+	InstancePtr->ErrorRef = CallBackRef;
+}
+
+/****************************************************************************/
+/*
+*
+* Check the interrupt status bits of the Ethernet MAC for errors. Errors
+* currently handled are:
+* - Receive length FIFO overrun. Indicates data was lost due to the receive
+*   length FIFO becoming full during the reception of a packet. Only a device
+*   reset clears this condition.
+* - Receive length FIFO underrun. An attempt to read an empty FIFO. Only a
+*   device reset clears this condition.
+* - Transmit status FIFO overrun. Indicates data was lost due to the transmit
+*   status FIFO becoming full following the transmission of a packet. Only a
+*   device reset clears this condition.
+* - Transmit status FIFO underrun. An attempt to read an empty FIFO. Only a
+*   device reset clears this condition.
+* - Transmit length FIFO overrun. Indicates data was lost due to the transmit
+*   length FIFO becoming full following the transmission of a packet. Only a
+*   device reset clears this condition.
+* - Transmit length FIFO underrun. An attempt to read an empty FIFO. Only a
+*   device reset clears this condition.
+* - Receive data FIFO overrun. Indicates data was lost due to the receive data
+*   FIFO becoming full during the reception of a packet.
+* - Receive data errors:
+*   - Receive missed frame error. Valid data was lost by the MAC.
+*   - Receive collision error. Data was lost by the MAC due to a collision.
+*   - Receive FCS error.  Data was dicarded by the MAC due to FCS error.
+*   - Receive length field error. Data was dicarded by the MAC due to an invalid
+*     length field in the packet.
+*   - Receive short error. Data was dicarded by the MAC because a packet was
+*     shorter than allowed.
+*   - Receive long error. Data was dicarded by the MAC because a packet was
+*     longer than allowed.
+*   - Receive alignment error. Data was truncated by the MAC because its length
+*     was not byte-aligned.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param IntrStatus is the contents of the interrupt status register to be checked
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* This function is intended for internal use only.
+*
+******************************************************************************/
+void
+XEmac_CheckEmacError(XEmac * InstancePtr, u32 IntrStatus)
+{
+	u32 ResetError = FALSE;
+
+	/*
+	 * First check for receive fifo overrun/underrun errors. Most require a
+	 * reset by the user to clear, but the data FIFO overrun error does not.
+	 */
+	if (IntrStatus & XEM_EIR_RECV_DFIFO_OVER_MASK) {
+		InstancePtr->Stats.RecvOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+	}
+
+	if (IntrStatus & XEM_EIR_RECV_LFIFO_OVER_MASK) {
+		/*
+		 * Receive Length FIFO overrun interrupts no longer occur in v1.00l
+		 * and later of the EMAC device. Frames are just dropped by the EMAC
+		 * if the length FIFO is full. The user would notice the Receive Missed
+		 * Frame count incrementing without any other errors being reported.
+		 * This code is left here for backward compatibility with v1.00k and
+		 * older EMAC devices.
+		 */
+		InstancePtr->Stats.RecvOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		ResetError = TRUE;	/* requires a reset */
+	}
+
+	if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
+		InstancePtr->Stats.RecvUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		ResetError = TRUE;	/* requires a reset */
+	}
+
+	/*
+	 * Now check for general receive errors. Get the latest count where
+	 * available, otherwise just bump the statistic so we know the interrupt
+	 * occurred.
+	 */
+	if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
+		if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
+			/*
+			 * Caused by length FIFO or data FIFO overruns on receive side
+			 */
+			InstancePtr->Stats.RecvMissedFrameErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RMFC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
+			InstancePtr->Stats.RecvCollisionErrors =
+			    XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
+			InstancePtr->Stats.RecvFcsErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RFCSEC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
+			InstancePtr->Stats.RecvLengthFieldErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
+			InstancePtr->Stats.RecvShortErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
+			InstancePtr->Stats.RecvLongErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
+			InstancePtr->Stats.RecvAlignmentErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RAEC_OFFSET);
+		}
+
+		/*
+		 * Bump recv interrupts stats only if not scatter-gather DMA (this
+		 * stat gets bumped elsewhere in that case)
+		 */
+		if (!XEmac_mIsSgDma(InstancePtr)) {
+			InstancePtr->Stats.RecvInterrupts++;	/* TODO: double bump? */
+		}
+
+	}
+
+	/*
+	 * Check for transmit errors. These apply to both DMA and non-DMA modes
+	 * of operation. The entire device should be reset after overruns or
+	 * underruns.
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+			  XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+		InstancePtr->Stats.XmitOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		ResetError = TRUE;
+	}
+
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+			  XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+		InstancePtr->Stats.XmitUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		ResetError = TRUE;
+	}
+
+	if (ResetError) {
+		/*
+		 * If a reset error occurred, disable the EMAC interrupts since the
+		 * reset-causing interrupt(s) is latched in the EMAC - meaning it will
+		 * keep occurring until the device is reset. In order to give the higher
+		 * layer software time to reset the device, we have to disable the
+		 * overrun/underrun interrupts until that happens. We trust that the
+		 * higher layer resets the device. We are able to get away with disabling
+		 * all EMAC interrupts since the only interrupts it generates are for
+		 * error conditions, and we don't care about any more errors right now.
+		 */
+		XIIF_V123B_WRITE_IIER(InstancePtr->BaseAddress, 0);
+
+		/*
+		 * Invoke the error handler callback, which should result in a reset
+		 * of the device by the upper layer software.
+		 */
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+					  XST_RESET_ERROR);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Check the receive packet FIFO for errors. FIFO error interrupts are:
+* - Deadlock.  See the XPacketFifo component for a description of deadlock on a
+*   FIFO.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Although the function returns void, it can return an asynchronous error to the
+* application through the error handler.  It can return XST_FIFO_ERROR if a FIFO
+* error occurred.
+*
+* @note
+*
+* This function is intended for internal use only.
+*
+******************************************************************************/
+void
+XEmac_CheckFifoRecvError(XEmac * InstancePtr)
+{
+	/*
+	 * Although the deadlock is currently the only interrupt from a packet
+	 * FIFO, make sure it is deadlocked before taking action. There is no
+	 * need to clear this interrupt since it requires a reset of the device.
+	 */
+	if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) {
+		u32 IntrEnable;
+
+		InstancePtr->Stats.FifoErrors++;
+
+		/*
+		 * Invoke the error callback function, which should result in a reset
+		 * of the device by the upper layer software. We first need to disable
+		 * the FIFO interrupt, since otherwise the upper layer thread that
+		 * handles the reset may never run because this interrupt condition
+		 * doesn't go away until a reset occurs (there is no way to ack it).
+		 */
+		IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
+		XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
+				      IntrEnable & ~XEM_IPIF_RECV_FIFO_MASK);
+
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+					  XST_FIFO_ERROR);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Check the send packet FIFO for errors. FIFO error interrupts are:
+* - Deadlock. See the XPacketFifo component for a description of deadlock on a
+*   FIFO.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Although the function returns void, it can return an asynchronous error to the
+* application through the error handler.  It can return XST_FIFO_ERROR if a FIFO
+* error occurred.
+*
+* @note
+*
+* This function is intended for internal use only.
+*
+******************************************************************************/
+void
+XEmac_CheckFifoSendError(XEmac * InstancePtr)
+{
+	/*
+	 * Although the deadlock is currently the only interrupt from a packet
+	 * FIFO, make sure it is deadlocked before taking action. There is no
+	 * need to clear this interrupt since it requires a reset of the device.
+	 */
+	if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) {
+		u32 IntrEnable;
+
+		InstancePtr->Stats.FifoErrors++;
+
+		/*
+		 * Invoke the error callback function, which should result in a reset
+		 * of the device by the upper layer software. We first need to disable
+		 * the FIFO interrupt, since otherwise the upper layer thread that
+		 * handles the reset may never run because this interrupt condition
+		 * doesn't go away until a reset occurs (there is no way to ack it).
+		 */
+		IntrEnable = XIIF_V123B_READ_DIER(InstancePtr->BaseAddress);
+		XIIF_V123B_WRITE_DIER(InstancePtr->BaseAddress,
+				      IntrEnable & ~XEM_IPIF_SEND_FIFO_MASK);
+
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+					  XST_FIFO_ERROR);
+	}
+}
diff --git a/board/xilinx/xilinx_enet/xemac_intr_dma.c b/board/xilinx/xilinx_enet/xemac_intr_dma.c
new file mode 100755
index 0000000..567abb4
--- /dev/null
+++ b/board/xilinx/xilinx_enet/xemac_intr_dma.c
@@ -0,0 +1,1344 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_intr_dma.c
+*
+* Contains functions used in interrupt mode when configured with scatter-gather
+* DMA.
+*
+* The interrupt handler, XEmac_IntrHandlerDma(), must be connected by the user
+* to the interrupt controller.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA and the delay
+*                     argument to SgSend
+* 1.00c rpm  02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
+*                     from SetPktThreshold in the internal DMA driver. Also
+*                     avoided compiler warnings by initializing Result in the
+*                     interrupt service routines.
+* 1.00c rpm  03/26/03 Fixed a problem in the interrupt service routines where
+*                     the interrupt status was toggled clear after a call to
+*                     ErrorHandler, but if ErrorHandler reset the device the
+*                     toggle actually asserted the interrupt because the
+*                     reset had cleared it.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+#include "xbuf_descriptor.h"
+#include "xdma_channel.h"
+#include "xipif_v1_23_b.h"	/* Uses v1.23b of the IPIF */
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static void HandleDmaRecvIntr(XEmac * InstancePtr);
+static void HandleDmaSendIntr(XEmac * InstancePtr);
+static void HandleEmacDmaIntr(XEmac * InstancePtr);
+
+/*****************************************************************************/
+/**
+*
+* Send an Ethernet frame using scatter-gather DMA. The caller attaches the
+* frame to one or more buffer descriptors, then calls this function once for
+* each descriptor. The caller is responsible for allocating and setting up the
+* descriptor. An entire Ethernet frame may or may not be contained within one
+* descriptor.  This function simply inserts the descriptor into the scatter-
+* gather engine's transmit list. The caller is responsible for providing mutual
+* exclusion to guarantee that a frame is contiguous in the transmit list. The
+* buffer attached to the descriptor must be word-aligned.
+*
+* The driver updates the descriptor with the device control register before
+* being inserted into the transmit list.  If this is the last descriptor in
+* the frame, the inserts are committed, which means the descriptors for this
+* frame are now available for transmission.
+*
+* It is assumed that the upper layer software supplies a correctly formatted
+* Ethernet frame, including the destination and source addresses, the
+* type/length field, and the data field.  It is also assumed that upper layer
+* software does not append FCS at the end of the frame.
+*
+* The buffer attached to the descriptor must be word-aligned on the front end.
+*
+* This call is non-blocking.  Notification of error or successful transmission
+* is done asynchronously through the send or error callback function.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BdPtr is the address of a descriptor to be inserted into the transmit
+*        ring.
+* @param Delay indicates whether to start the scatter-gather DMA channel
+*        immediately, or whether to wait. This allows the user to build up a
+*        list of more than one descriptor before starting the transmission of
+*        the packets, which allows the application to keep up with DMA and have
+*        a constant stream of frames being transmitted. Use XEM_SGDMA_NODELAY or
+*        XEM_SGDMA_DELAY, defined in xemac.h, as the value of this argument. If
+*        the user chooses to delay and build a list, the user must call this
+*        function with the XEM_SGDMA_NODELAY option or call XEmac_Start() to
+*        kick off the tranmissions.
+*
+* @return
+*
+* - XST_SUCCESS if the buffer was successfull sent
+* - XST_DEVICE_IS_STOPPED if the Ethernet MAC has not been started yet
+* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode
+* - XST_DMA_SG_LIST_FULL if the descriptor list for the DMA channel is full
+* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into
+*   the list because a locked descriptor exists at the insert point
+* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the
+*   list, the DMA channel believes there are no new descriptors to commit. If
+*   this is ever encountered, there is likely a thread mutual exclusion problem
+*   on transmit.
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* @internal
+*
+* A status that should never be returned from this function, although
+* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device
+* requires a list to be created, and this function requires the device to be
+* started.
+*
+******************************************************************************/
+XStatus
+XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay)
+{
+	XStatus Result;
+	u32 BdControl;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BdPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure the device is configured for scatter-gather DMA, then be sure
+	 * it is started.
+	 */
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	/*
+	 * Set some descriptor control word defaults (source address increment
+	 * and local destination address) and the destination address
+	 * (the FIFO).  These are the same for every transmit descriptor.
+	 */
+	BdControl = XBufDescriptor_GetControl(BdPtr);
+	XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_SEND_BD_MASK);
+
+	XBufDescriptor_SetDestAddress(BdPtr,
+				      InstancePtr->BaseAddress +
+				      XEM_PFIFO_TXDATA_OFFSET);
+
+	/*
+	 * Put the descriptor in the send list. The DMA component accesses data
+	 * here that can also be modified in interrupt context, so a critical
+	 * section is required.
+	 */
+	XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+
+	Result = XDmaChannel_PutDescriptor(&InstancePtr->SendChannel, BdPtr);
+	if (Result != XST_SUCCESS) {
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+		return Result;
+	}
+
+	/*
+	 * If this is the last buffer in the frame, commit the inserts and start
+	 * the DMA engine if necessary
+	 */
+	if (XBufDescriptor_IsLastControl(BdPtr)) {
+		Result = XDmaChannel_CommitPuts(&InstancePtr->SendChannel);
+		if (Result != XST_SUCCESS) {
+			XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+			return Result;
+		}
+
+		if (Delay == XEM_SGDMA_NODELAY) {
+			/*
+			 * Start the DMA channel. Ignore the return status since we know the
+			 * list exists and has at least one entry and we don't care if the
+			 * channel is already started.  The DMA component accesses data here
+			 * that can be modified at interrupt or task levels, so a critical
+			 * section is required.
+			 */
+			(void) XDmaChannel_SgStart(&InstancePtr->SendChannel);
+		}
+	}
+
+	XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Add a descriptor, with an attached empty buffer, into the receive descriptor
+* list. The buffer attached to the descriptor must be word-aligned. This is
+* used by the upper layer software during initialization when first setting up
+* the receive descriptors, and also during reception of frames to replace
+* filled buffers with empty buffers. This function can be called when the
+* device is started or stopped. Note that it does start the scatter-gather DMA
+* engine.  Although this is not necessary during initialization, it is not a
+* problem during initialization because the MAC receiver is not yet started.
+*
+* The buffer attached to the descriptor must be word-aligned on both the front
+* end and the back end.
+*
+* Notification of received frames are done asynchronously through the receive
+* callback function.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BdPtr is a pointer to the buffer descriptor that will be added to the
+*        descriptor list.
+*
+* @return
+*
+* - XST_SUCCESS if a descriptor was successfully returned to the driver
+* - XST_NOT_SGDMA if the device is not in scatter-gather DMA mode
+* - XST_DMA_SG_LIST_FULL if the receive descriptor list is full
+* - XST_DMA_SG_BD_LOCKED if the DMA channel cannot insert the descriptor into
+*   the list because a locked descriptor exists at the insert point.
+* - XST_DMA_SG_NOTHING_TO_COMMIT if even after inserting a descriptor into the
+*   list, the DMA channel believes there are no new descriptors to commit.
+*
+* @internal
+*
+* A status that should never be returned from this function, although
+* the code is set up to handle it, is XST_DMA_SG_NO_LIST. Starting the device
+* requires a list to be created, and this function requires the device to be
+* started.
+*
+******************************************************************************/
+XStatus
+XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr)
+{
+	XStatus Result;
+	u32 BdControl;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BdPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure the device is configured for scatter-gather DMA
+	 */
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	/*
+	 * Set some descriptor control word defaults (destination address increment
+	 * and local source address) and the source address (the FIFO). These are
+	 * the same for every receive descriptor.
+	 */
+	BdControl = XBufDescriptor_GetControl(BdPtr);
+	XBufDescriptor_SetControl(BdPtr, BdControl | XEM_DFT_RECV_BD_MASK);
+	XBufDescriptor_SetSrcAddress(BdPtr,
+				     InstancePtr->BaseAddress +
+				     XEM_PFIFO_RXDATA_OFFSET);
+
+	/*
+	 * Put the descriptor into the channel's descriptor list and commit.
+	 * Although this function is likely called within interrupt context, there
+	 * is the possibility that the upper layer software queues it to a task.
+	 * In this case, a critical section is needed here to protect shared data
+	 * in the DMA component.
+	 */
+	XIIF_V123B_GINTR_DISABLE(InstancePtr->BaseAddress);
+
+	Result = XDmaChannel_PutDescriptor(&InstancePtr->RecvChannel, BdPtr);
+	if (Result != XST_SUCCESS) {
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+		return Result;
+	}
+
+	Result = XDmaChannel_CommitPuts(&InstancePtr->RecvChannel);
+	if (Result != XST_SUCCESS) {
+		XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+		return Result;
+	}
+
+	/*
+	 * Start the DMA channel. Ignore the return status since we know the list
+	 * exists and has at least one entry and we don't care if the channel is
+	 * already started. The DMA component accesses data here that can be
+	 * modified at interrupt or task levels, so a critical section is required.
+	 */
+	(void) XDmaChannel_SgStart(&InstancePtr->RecvChannel);
+
+	XIIF_V123B_GINTR_ENABLE(InstancePtr->BaseAddress);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for the Ethernet driver when configured with scatter-
+* gather DMA.
+*
+* Get the interrupt status from the IpIf to determine the source of the
+* interrupt.  The source can be: MAC, Recv Packet FIFO, Send Packet FIFO, Recv
+* DMA channel, or Send DMA channel. The packet FIFOs only interrupt during
+* "deadlock" conditions.
+*
+* @param InstancePtr is a pointer to the XEmac instance that just interrupted.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_IntrHandlerDma(void *InstancePtr)
+{
+	u32 IntrStatus;
+	XEmac *EmacPtr = (XEmac *) InstancePtr;
+
+	EmacPtr->Stats.TotalIntrs++;
+
+	/*
+	 * Get the interrupt status from the IPIF. There is no clearing of
+	 * interrupts in the IPIF. Interrupts must be cleared at the source.
+	 */
+	IntrStatus = XIIF_V123B_READ_DIPR(EmacPtr->BaseAddress);
+
+	/*
+	 * See which type of interrupt is being requested, and service it
+	 */
+	if (IntrStatus & XEM_IPIF_RECV_DMA_MASK) {	/* Receive DMA interrupt */
+		EmacPtr->Stats.RecvInterrupts++;
+		HandleDmaRecvIntr(EmacPtr);
+	}
+
+	if (IntrStatus & XEM_IPIF_SEND_DMA_MASK) {	/* Send DMA interrupt */
+		EmacPtr->Stats.XmitInterrupts++;
+		HandleDmaSendIntr(EmacPtr);
+	}
+
+	if (IntrStatus & XEM_IPIF_EMAC_MASK) {	/* MAC interrupt */
+		EmacPtr->Stats.EmacInterrupts++;
+		HandleEmacDmaIntr(EmacPtr);
+	}
+
+	if (IntrStatus & XEM_IPIF_RECV_FIFO_MASK) {	/* Receive FIFO interrupt */
+		EmacPtr->Stats.RecvInterrupts++;
+		XEmac_CheckFifoRecvError(EmacPtr);
+	}
+
+	if (IntrStatus & XEM_IPIF_SEND_FIFO_MASK) {	/* Send FIFO interrupt */
+		EmacPtr->Stats.XmitInterrupts++;
+		XEmac_CheckFifoSendError(EmacPtr);
+	}
+
+	if (IntrStatus & XIIF_V123B_ERROR_MASK) {
+		/*
+		 * An error occurred internal to the IPIF. This is more of a debug and
+		 * integration issue rather than a production error. Don't do anything
+		 * other than clear it, which provides a spot for software to trap
+		 * on the interrupt and begin debugging.
+		 */
+		XIIF_V123B_WRITE_DISR(EmacPtr->BaseAddress,
+				      XIIF_V123B_ERROR_MASK);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the packet count threshold for this device. The device must be stopped
+* before setting the threshold. The packet count threshold is used for interrupt
+* coalescing, which reduces the frequency of interrupts from the device to the
+* processor. In this case, the scatter-gather DMA engine only interrupts when
+* the packet count threshold is reached, instead of interrupting for each packet.
+* A packet is a generic term used by the scatter-gather DMA engine, and is
+* equivalent to an Ethernet frame in our case.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Direction indicates the channel, send or receive, from which the
+*        threshold register is read.
+* @param Threshold is the value of the packet threshold count used during
+*        interrupt coalescing. A value of 0 disables the use of packet threshold
+*        by the hardware.
+*
+* @return
+*
+* - XST_SUCCESS if the threshold was successfully set
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_DEVICE_IS_STARTED if the device has not been stopped
+* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
+*   asserts would also catch this error.
+*
+* @note
+*
+* The packet threshold could be set to larger than the number of descriptors
+* allocated to the DMA channel. In this case, the wait bound will take over
+* and always indicate data arrival. There was a check in this function that
+* returned an error if the treshold was larger than the number of descriptors,
+* but that was removed because users would then have to set the threshold
+* only after they set descriptor space, which is an order dependency that
+* caused confustion.
+*
+******************************************************************************/
+XStatus
+XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure device is configured for scatter-gather DMA and has been stopped
+	 */
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Based on the direction, set the packet threshold in the
+	 * corresponding DMA channel component.  Default to the receive
+	 * channel threshold register (if an invalid Direction is passed).
+	 */
+	switch (Direction) {
+	case XEM_SEND:
+		return XDmaChannel_SetPktThreshold(&InstancePtr->SendChannel,
+						   Threshold);
+
+	case XEM_RECV:
+		return XDmaChannel_SetPktThreshold(&InstancePtr->RecvChannel,
+						   Threshold);
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the value of the packet count threshold for this driver/device. The packet
+* count threshold is used for interrupt coalescing, which reduces the frequency
+* of interrupts from the device to the processor. In this case, the
+* scatter-gather DMA engine only interrupts when the packet count threshold is
+* reached, instead of interrupting for each packet. A packet is a generic term
+* used by the scatter-gather DMA engine, and is equivalent to an Ethernet frame
+* in our case.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Direction indicates the channel, send or receive, from which the
+*        threshold register is read.
+* @param ThreshPtr is a pointer to the byte into which the current value of the
+*        packet threshold register will be copied. An output parameter. A value
+*        of 0 indicates the use of packet threshold by the hardware is disabled.
+*
+* @return
+*
+* - XST_SUCCESS if the packet threshold was retrieved successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
+*   asserts would also catch this error.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 * ThreshPtr)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
+	XASSERT_NONVOID(ThreshPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	/*
+	 * Based on the direction, return the packet threshold set in the
+	 * corresponding DMA channel component.  Default to the value in
+	 * the receive channel threshold register (if an invalid Direction
+	 * is passed).
+	 */
+	switch (Direction) {
+	case XEM_SEND:
+		*ThreshPtr =
+		    XDmaChannel_GetPktThreshold(&InstancePtr->SendChannel);
+		break;
+
+	case XEM_RECV:
+		*ThreshPtr =
+		    XDmaChannel_GetPktThreshold(&InstancePtr->RecvChannel);
+		break;
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the packet wait bound timer for this driver/device. The device must be
+* stopped before setting the timer value. The packet wait bound is used during
+* interrupt coalescing to trigger an interrupt when not enough packets have been
+* received to reach the packet count threshold. A packet is a generic term used
+* by the scatter-gather DMA engine, and is equivalent to an Ethernet frame in
+* our case. The timer is in milliseconds.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Direction indicates the channel, send or receive, from which the
+*        threshold register is read.
+* @param TimerValue is the value of the packet wait bound used during interrupt
+*        coalescing. It is in milliseconds in the range 0  - 1023. A value of 0
+*        disables the packet wait bound timer.
+*
+* @return
+*
+* - XST_SUCCESS if the packet wait bound was set successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_DEVICE_IS_STARTED if the device has not been stopped
+* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
+*   asserts would also catch this error.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 TimerValue)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
+	XASSERT_NONVOID(TimerValue <= XEM_SGDMA_MAX_WAITBOUND);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure device is configured for scatter-gather DMA and has been stopped
+	 */
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Based on the direction, set the packet wait bound in the
+	 * corresponding DMA channel component.  Default to the receive
+	 * channel wait bound register (if an invalid Direction is passed).
+	 */
+	switch (Direction) {
+	case XEM_SEND:
+		XDmaChannel_SetPktWaitBound(&InstancePtr->SendChannel,
+					    TimerValue);
+		break;
+
+	case XEM_RECV:
+		XDmaChannel_SetPktWaitBound(&InstancePtr->RecvChannel,
+					    TimerValue);
+		break;
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the packet wait bound timer for this driver/device. The packet wait bound
+* is used during interrupt coalescing to trigger an interrupt when not enough
+* packets have been received to reach the packet count threshold. A packet is a
+* generic term used by the scatter-gather DMA engine, and is equivalent to an
+* Ethernet frame in our case. The timer is in milliseconds.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Direction indicates the channel, send or receive, from which the
+*        threshold register is read.
+* @param WaitPtr is a pointer to the byte into which the current value of the
+*        packet wait bound register will be copied. An output parameter. Units
+*        are in milliseconds in the range 0  - 1023. A value of 0 indicates the
+*        packet wait bound timer is disabled.
+*
+* @return
+*
+* - XST_SUCCESS if the packet wait bound was retrieved successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_INVALID_PARAM if the Direction parameter is invalid. Turning on
+*   asserts would also catch this error.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction, u32 * WaitPtr)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Direction == XEM_SEND || Direction == XEM_RECV);
+	XASSERT_NONVOID(WaitPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	/*
+	 * Based on the direction, return the packet wait bound set in the
+	 * corresponding DMA channel component.  Default to the value in
+	 * the receive channel wait bound register (if an invalid Direction
+	 * is passed).
+	 */
+	switch (Direction) {
+	case XEM_SEND:
+		*WaitPtr =
+		    XDmaChannel_GetPktWaitBound(&InstancePtr->SendChannel);
+		break;
+
+	case XEM_RECV:
+		*WaitPtr =
+		    XDmaChannel_GetPktWaitBound(&InstancePtr->RecvChannel);
+		break;
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Give the driver the memory space to be used for the scatter-gather DMA
+* receive descriptor list. This function should only be called once, during
+* initialization of the Ethernet driver. The memory space must be big enough
+* to hold some number of descriptors, depending on the needs of the system.
+* The xemac.h file defines minimum and default numbers of descriptors
+* which can be used to allocate this memory space.
+*
+* The memory space must be word-aligned. An assert will occur if asserts are
+* turned on and the memory is not word-aligned.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param MemoryPtr is a pointer to the word-aligned memory.
+* @param ByteCount is the length, in bytes, of the memory space.
+*
+* @return
+*
+* - XST_SUCCESS if the space was initialized successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_DMA_SG_LIST_EXISTS if this list space has already been created
+*
+* @note
+*
+* If the device is configured for scatter-gather DMA, this function must be
+* called AFTER the XEmac_Initialize() function because the DMA channel
+* components must be initialized before the memory space is set.
+*
+******************************************************************************/
+XStatus
+XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(MemoryPtr != NULL);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	return XDmaChannel_CreateSgList(&InstancePtr->RecvChannel, MemoryPtr,
+					ByteCount);
+}
+
+/*****************************************************************************/
+/**
+*
+* Give the driver the memory space to be used for the scatter-gather DMA
+* transmit descriptor list. This function should only be called once, during
+* initialization of the Ethernet driver. The memory space must be big enough
+* to hold some number of descriptors, depending on the needs of the system.
+* The xemac.h file defines minimum and default numbers of descriptors
+* which can be used to allocate this memory space.
+*
+* The memory space must be word-aligned. An assert will occur if asserts are
+* turned on and the memory is not word-aligned.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param MemoryPtr is a pointer to the word-aligned memory.
+* @param ByteCount is the length, in bytes, of the memory space.
+*
+* @return
+*
+* - XST_SUCCESS if the space was initialized successfully
+* - XST_NOT_SGDMA if the MAC is not configured for scatter-gather DMA
+* - XST_DMA_SG_LIST_EXISTS if this list space has already been created
+*
+* @note
+*
+* If the device is configured for scatter-gather DMA, this function must be
+* called AFTER the XEmac_Initialize() function because the DMA channel
+* components must be initialized before the memory space is set.
+*
+******************************************************************************/
+XStatus
+XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr, u32 ByteCount)
+{
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(MemoryPtr != NULL);
+	XASSERT_NONVOID(ByteCount != 0);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (!XEmac_mIsSgDma(InstancePtr)) {
+		return XST_NOT_SGDMA;
+	}
+
+	return XDmaChannel_CreateSgList(&InstancePtr->SendChannel, MemoryPtr,
+					ByteCount);
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the callback function for handling received frames in scatter-gather DMA
+* mode.  The upper layer software should call this function during
+* initialization.  The callback is called once per frame received. The head of
+* a descriptor list is passed in along with the number of descriptors in the
+* list. Before leaving the callback, the upper layer software should attach a
+* new buffer to each descriptor in the list.
+*
+* The callback is invoked by the driver within interrupt context, so it needs
+* to do its job quickly. Sending the received frame up the protocol stack
+* should be done at task-level. If there are other potentially slow operations
+* within the callback, these too should be done at task-level.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param CallBackRef is a reference pointer to be passed back to the adapter in
+*        the callback. This helps the adapter correlate the callback to a
+*        particular driver.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef,
+		       XEmac_SgHandler FuncPtr)
+{
+	/*
+	 * Asserted IsDmaSg here instead of run-time check because there is really
+	 * no ill-effects of setting these when not configured for scatter-gather.
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(FuncPtr != NULL);
+	XASSERT_VOID(XEmac_mIsSgDma(InstancePtr));
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	InstancePtr->SgRecvHandler = FuncPtr;
+	InstancePtr->SgRecvRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the callback function for handling confirmation of transmitted frames in
+* scatter-gather DMA mode.  The upper layer software should call this function
+* during initialization.  The callback is called once per frame sent. The head
+* of a descriptor list is passed in along with the number of descriptors in
+* the list. The callback is responsible for freeing buffers attached to these
+* descriptors.
+*
+* The callback is invoked by the driver within interrupt context, so it needs
+* to do its job quickly. If there are potentially slow operations within the
+* callback, these should be done at task-level.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param CallBackRef is a reference pointer to be passed back to the adapter in
+*        the callback. This helps the adapter correlate the callback to a
+*        particular driver.
+* @param FuncPtr is the pointer to the callback function.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+void
+XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef,
+		       XEmac_SgHandler FuncPtr)
+{
+	/*
+	 * Asserted IsDmaSg here instead of run-time check because there is really
+	 * no ill-effects of setting these when not configured for scatter-gather.
+	 */
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(FuncPtr != NULL);
+	XASSERT_VOID(XEmac_mIsSgDma(InstancePtr));
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	InstancePtr->SgSendHandler = FuncPtr;
+	InstancePtr->SgSendRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/*
+*
+* Handle an interrupt from the DMA receive channel. DMA interrupts are:
+*
+* - DMA error. DMA encountered a bus error or timeout. This is a fatal error
+*   that requires reset of the channel.  The driver calls the error handler
+*   of the upper layer software with an error code indicating the device should
+*   be reset.
+* - Packet count threshold reached.  For scatter-gather operations, indicates
+*   the threshold for the number of packets not serviced by software has been
+*   reached. The driver behaves as follows:
+*       - Get the value of the packet counter, which tells us how many packets
+*         are ready to be serviced
+*       - For each packet
+*           - For each descriptor, remove it from the scatter-gather list
+*           - Check for the last descriptor in the frame, and if set
+*               - Bump frame statistics
+*               - Call the scatter-gather receive callback function
+*               - Decrement the packet counter by one
+*       Note that there are no receive errors reported in the status word of
+*       the buffer descriptor.  If receive errors occur, the MAC drops the
+*       packet, and we only find out about the errors through various error
+*       count registers.
+* - Packet wait bound reached.  For scatter-gather, indicates the time to wait
+*   for the next packet has expired.  The driver follows the same logic as when
+*   the packet count threshold interrupt is received.
+* - Scatter-gather end acknowledge.  Hardware has reached the end of the
+*   descriptor list.  The driver follows the same logic as when the packet count
+*   threshold interrupt is received. In addition, the driver restarts the DMA
+*   scatter-gather channel in case there are newly inserted descriptors.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Although the function returns void, there are asynchronous errors that can
+* be generated (by calling the ErrorHandler) from this function.  These are:
+* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from the
+*   DMA channel, but there was not one ready for software.
+* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a fatal
+*   error that requires reset.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+HandleDmaRecvIntr(XEmac * InstancePtr)
+{
+	u32 IntrStatus;
+
+	/*
+	 * Read the interrupt status
+	 */
+	IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->RecvChannel);
+
+	/*
+	 * For packet threshold or wait bound interrupts, process desciptors. Also
+	 * process descriptors on a SG end acknowledgement, which means the end of
+	 * the descriptor list has been reached by the hardware. For receive, this
+	 * is potentially trouble since it means the descriptor list is full,
+	 * unless software can process enough packets quickly enough so the
+	 * hardware has room to put new packets.
+	 */
+	if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK |
+			  XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) {
+		XStatus Result = XST_SUCCESS;
+		u32 NumFrames;
+		u32 NumProcessed;
+		u32 NumBuffers;
+		u32 NumBytes;
+		u32 IsLast;
+		XBufDescriptor *FirstBdPtr;
+		XBufDescriptor *BdPtr;
+
+		/*
+		 * Get the number of unserviced packets
+		 */
+		NumFrames = XDmaChannel_GetPktCount(&InstancePtr->RecvChannel);
+
+		for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) {
+			IsLast = FALSE;
+			FirstBdPtr = NULL;
+			NumBuffers = 0;
+			NumBytes = 0;
+
+			/*
+			 * For each packet, get the descriptor from the list. On the
+			 * last one in the frame, make the callback to the upper layer.
+			 */
+			while (!IsLast) {
+				Result =
+				    XDmaChannel_GetDescriptor(&InstancePtr->
+							      RecvChannel,
+							      &BdPtr);
+				if (Result != XST_SUCCESS) {
+					/*
+					 * An error getting a buffer descriptor from the list.
+					 * This should not happen, but if it does, report it to
+					 * the error callback and break out of the loops to service
+					 * other interrupts.
+					 */
+					InstancePtr->ErrorHandler(InstancePtr->
+								  ErrorRef,
+								  Result);
+					break;
+				}
+
+				/*
+				 * Keep a pointer to the first descriptor in the list, as it
+				 * will be passed to the upper layers in a bit. By the fact
+				 * that we received this packet means no errors occurred, so
+				 * no need to check the device status word for errors.
+				 */
+				if (FirstBdPtr == NULL) {
+					FirstBdPtr = BdPtr;
+				}
+
+				NumBytes += XBufDescriptor_GetLength(BdPtr);
+
+				/*
+				 * Check to see if this is the last descriptor in the frame,
+				 * and if so, set the IsLast flag to get out of the loop.
+				 */
+				if (XBufDescriptor_IsLastStatus(BdPtr)) {
+					IsLast = TRUE;
+				}
+
+				/*
+				 * Bump the number of buffers in this packet
+				 */
+				NumBuffers++;
+
+			}	/* end while loop */
+
+			/*
+			 * Check for error that occurred inside the while loop, and break
+			 * out of the for loop if there was one so other interrupts can
+			 * be serviced.
+			 */
+			if (Result != XST_SUCCESS) {
+				break;
+			}
+
+			InstancePtr->Stats.RecvFrames++;
+			InstancePtr->Stats.RecvBytes += NumBytes;
+
+			/*
+			 * Make the callback to the upper layers, passing it the first
+			 * descriptor in the packet and the number of descriptors in the
+			 * packet.
+			 */
+			InstancePtr->SgRecvHandler(InstancePtr->SgRecvRef,
+						   FirstBdPtr, NumBuffers);
+
+			/*
+			 * Decrement the packet count register to reflect the fact we
+			 * just processed a packet
+			 */
+			XDmaChannel_DecrementPktCount(&InstancePtr->
+						      RecvChannel);
+
+		}		/* end for loop */
+
+		/*
+		 * If the interrupt was an end-ack, check the descriptor list again to
+		 * see if it is empty. If not, go ahead and restart the scatter-gather
+		 * channel. This is to fix a possible race condition where, on receive,
+		 * the driver attempted to start a scatter-gather channel that was
+		 * already started, which resulted in no action from the XDmaChannel
+		 * component. But, just after the XDmaChannel component saw that the
+		 * hardware was already started, the hardware stopped because it
+		 * reached the end of the list.  In that case, this interrupt is
+		 * generated and we can restart the hardware here.
+		 */
+		if (IntrStatus & XDC_IXR_SG_END_MASK) {
+			/*
+			 * Ignore the return status since we know the list exists and we
+			 * don't care if the list is empty or the channel is already started.
+			 */
+			(void) XDmaChannel_SgStart(&InstancePtr->RecvChannel);
+		}
+	}
+
+	/*
+	 * All interrupts are handled (except the error below) so acknowledge
+	 * (clear) the interrupts by writing the value read above back to the status
+	 * register. The packet count interrupt must be acknowledged after the
+	 * decrement, otherwise it will come right back. We clear the interrupts
+	 * before we handle the error interrupt because the ErrorHandler should
+	 * result in a reset, which clears the interrupt status register. So we
+	 * don't want to toggle the interrupt back on by writing the interrupt
+	 * status register with an old value after a reset.
+	 */
+	XDmaChannel_SetIntrStatus(&InstancePtr->RecvChannel, IntrStatus);
+
+	/*
+	 * Check for DMA errors and call the error callback function if an error
+	 * occurred (DMA bus or timeout error), which should result in a reset of
+	 * the device by the upper layer software.
+	 */
+	if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) {
+		InstancePtr->Stats.DmaErrors++;
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Handle an interrupt from the DMA send channel. DMA interrupts are:
+*
+* - DMA error. DMA encountered a bus error or timeout. This is a fatal error
+*   that requires reset of the channel.  The driver calls the error handler
+*   of the upper layer software with an error code indicating the device should
+*   be reset.
+* - Packet count threshold reached.  For scatter-gather operations, indicates
+*   the threshold for the number of packets not serviced by software has been
+*   reached. The driver behaves as follows:
+*       - Get the value of the packet counter, which tells us how many packets
+*         are ready to be serviced
+*       - For each packet
+*           - For each descriptor, remove it from the scatter-gather list
+*           - Check for the last descriptor in the frame, and if set
+*               - Bump frame statistics
+*               - Call the scatter-gather receive callback function
+*               - Decrement the packet counter by one
+*       Note that there are no receive errors reported in the status word of
+*       the buffer descriptor.  If receive errors occur, the MAC drops the
+*       packet, and we only find out about the errors through various error
+*       count registers.
+* - Packet wait bound reached.  For scatter-gather, indicates the time to wait
+*   for the next packet has expired.  The driver follows the same logic as when
+*   the packet count threshold interrupt is received.
+* - Scatter-gather end acknowledge.  Hardware has reached the end of the
+*   descriptor list.  The driver follows the same logic as when the packet count
+*   threshold interrupt is received. In addition, the driver restarts the DMA
+*   scatter-gather channel in case there are newly inserted descriptors.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* Although the function returns void, there are asynchronous errors
+* that can be generated from this function.  These are:
+* - XST_DMA_SG_LIST_EMPTY indicates we tried to get a buffer descriptor from
+*   the DMA channel, but there was not one ready for software.
+* - XST_DMA_ERROR indicates a DMA bus error or timeout occurred. This is a
+*   fatal error that requires reset.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+HandleDmaSendIntr(XEmac * InstancePtr)
+{
+	u32 IntrStatus;
+
+	/*
+	 * Read the interrupt status
+	 */
+	IntrStatus = XDmaChannel_GetIntrStatus(&InstancePtr->SendChannel);
+
+	/*
+	 * For packet threshold or wait bound interrupt, process descriptors. Also
+	 * process descriptors on a SG end acknowledgement, which means the end of
+	 * the descriptor list has been reached by the hardware. For transmit,
+	 * this is a normal condition during times of light traffic.  In fact, the
+	 * wait bound interrupt may be masked for transmit since the end-ack would
+	 * always occur before the wait bound expires.
+	 */
+	if (IntrStatus & (XDC_IXR_PKT_THRESHOLD_MASK |
+			  XDC_IXR_PKT_WAIT_BOUND_MASK | XDC_IXR_SG_END_MASK)) {
+		XStatus Result = XST_SUCCESS;
+		u32 NumFrames;
+		u32 NumProcessed;
+		u32 NumBuffers;
+		u32 NumBytes;
+		u32 IsLast;
+		XBufDescriptor *FirstBdPtr;
+		XBufDescriptor *BdPtr;
+
+		/*
+		 * Get the number of unserviced packets
+		 */
+		NumFrames = XDmaChannel_GetPktCount(&InstancePtr->SendChannel);
+
+		for (NumProcessed = 0; NumProcessed < NumFrames; NumProcessed++) {
+			IsLast = FALSE;
+			FirstBdPtr = NULL;
+			NumBuffers = 0;
+			NumBytes = 0;
+
+			/*
+			 * For each frame, traverse the descriptor list and look for
+			 * errors. On the last one in the frame, make the callback.
+			 */
+			while (!IsLast) {
+				Result =
+				    XDmaChannel_GetDescriptor(&InstancePtr->
+							      SendChannel,
+							      &BdPtr);
+				if (Result != XST_SUCCESS) {
+					/*
+					 * An error getting a buffer descriptor from the list.
+					 * This should not happen, but if it does, report it to
+					 * the error callback and break out of the loops to service
+					 * other interrupts
+					 */
+					InstancePtr->ErrorHandler(InstancePtr->
+								  ErrorRef,
+								  Result);
+					break;
+				}
+
+				/*
+				 * Keep a pointer to the first descriptor in the list and
+				 * check the device status for errors. The device status is
+				 * only available in the first descriptor of a packet.
+				 */
+				if (FirstBdPtr == NULL) {
+					u32 XmitStatus;
+
+					FirstBdPtr = BdPtr;
+
+					XmitStatus =
+					    XBufDescriptor_GetDeviceStatus
+					    (BdPtr);
+					if (XmitStatus &
+					    XEM_TSR_EXCESS_DEFERRAL_MASK) {
+						InstancePtr->Stats.
+						    XmitExcessDeferral++;
+					}
+
+					if (XmitStatus &
+					    XEM_TSR_LATE_COLLISION_MASK) {
+						InstancePtr->Stats.
+						    XmitLateCollisionErrors++;
+					}
+				}
+
+				NumBytes += XBufDescriptor_GetLength(BdPtr);
+
+				/*
+				 * Check to see if this is the last descriptor in the frame,
+				 * and if so, set the IsLast flag to get out of the loop. The
+				 * transmit channel must check the last bit in the control
+				 * word, not the status word (the DMA engine does not update
+				 * the last bit in the status word for the transmit direction).
+				 */
+				if (XBufDescriptor_IsLastControl(BdPtr)) {
+					IsLast = TRUE;
+				}
+
+				/*
+				 * Bump the number of buffers in this packet
+				 */
+				NumBuffers++;
+
+			}	/* end while loop */
+
+			/*
+			 * Check for error that occurred inside the while loop, and break
+			 * out of the for loop if there was one so other interrupts can
+			 * be serviced.
+			 */
+			if (Result != XST_SUCCESS) {
+				break;
+			}
+
+			InstancePtr->Stats.XmitFrames++;
+			InstancePtr->Stats.XmitBytes += NumBytes;
+
+			/*
+			 * Make the callback to the upper layers, passing it the first
+			 * descriptor in the packet and the number of descriptors in the
+			 * packet.
+			 */
+			InstancePtr->SgSendHandler(InstancePtr->SgSendRef,
+						   FirstBdPtr, NumBuffers);
+
+			/*
+			 * Decrement the packet count register to reflect the fact we
+			 * just processed a packet
+			 */
+			XDmaChannel_DecrementPktCount(&InstancePtr->
+						      SendChannel);
+
+		}		/* end for loop */
+
+		/*
+		 * If the interrupt was an end-ack, check the descriptor list again to
+		 * see if it is empty. If not, go ahead and restart the scatter-gather
+		 * channel. This is to fix a possible race condition where, on transmit,
+		 * the driver attempted to start a scatter-gather channel that was
+		 * already started, which resulted in no action from the XDmaChannel
+		 * component. But, just after the XDmaChannel component saw that the
+		 * hardware was already started, the hardware stopped because it
+		 * reached the end of the list.  In that case, this interrupt is
+		 * generated and we can restart the hardware here.
+		 */
+		if (IntrStatus & XDC_IXR_SG_END_MASK) {
+			/*
+			 * Ignore the return status since we know the list exists and we
+			 * don't care if the list is empty or the channel is already started.
+			 */
+			(void) XDmaChannel_SgStart(&InstancePtr->SendChannel);
+		}
+	}
+
+	/*
+	 * All interrupts are handled (except the error below) so acknowledge
+	 * (clear) the interrupts by writing the value read above back to the status
+	 * register. The packet count interrupt must be acknowledged after the
+	 * decrement, otherwise it will come right back. We clear the interrupts
+	 * before we handle the error interrupt because the ErrorHandler should
+	 * result in a reset, which clears the interrupt status register. So we
+	 * don't want to toggle the interrupt back on by writing the interrupt
+	 * status register with an old value after a reset.
+	 */
+	XDmaChannel_SetIntrStatus(&InstancePtr->SendChannel, IntrStatus);
+
+	/*
+	 * Check for DMA errors and call the error callback function if an error
+	 * occurred (DMA bus or timeout error), which should result in a reset of
+	 * the device by the upper layer software.
+	 */
+	if (IntrStatus & XDC_IXR_DMA_ERROR_MASK) {
+		InstancePtr->Stats.DmaErrors++;
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XST_DMA_ERROR);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Handle an interrupt from the Ethernet MAC when configured with scatter-gather
+* DMA. The only interrupts handled in this case are errors.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+static void
+HandleEmacDmaIntr(XEmac * InstancePtr)
+{
+	u32 IntrStatus;
+
+	/*
+	 * When configured with DMA, the EMAC generates interrupts only when errors
+	 * occur. We clear the interrupts immediately so that any latched status
+	 * interrupt bits will reflect the true status of the device, and so any
+	 * pulsed interrupts (non-status) generated during the Isr will not be lost.
+	 */
+	IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+	XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, IntrStatus);
+
+	/*
+	 * Check the MAC for errors
+	 */
+	XEmac_CheckEmacError(InstancePtr, IntrStatus);
+}
diff --git a/board/xilinx/xilinx_enet/xemac_l.h b/board/xilinx/xilinx_enet/xemac_l.h
new file mode 100755
index 0000000..a463937
--- /dev/null
+++ b/board/xilinx/xilinx_enet/xemac_l.h
@@ -0,0 +1,462 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_l.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  High-level driver functions
+* are defined in xemac.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm  04/26/02 First release
+* 1.00b rmm  09/23/02 Added XEmac_mPhyReset macro
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XEMAC_L_H		/* prevent circular inclusions */
+#define XEMAC_L_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xio.h"
+
+/************************** Constant Definitions *****************************/
+
+/* Offset of the MAC registers from the IPIF base address */
+#define XEM_REG_OFFSET	   0x1100UL
+
+/*
+ * Register offsets for the Ethernet MAC. Each register is 32 bits.
+ */
+#define XEM_EMIR_OFFSET	  (XEM_REG_OFFSET + 0x0)	/* EMAC Module ID */
+#define XEM_ECR_OFFSET	  (XEM_REG_OFFSET + 0x4)	/* MAC Control */
+#define XEM_IFGP_OFFSET	  (XEM_REG_OFFSET + 0x8)	/* Interframe Gap */
+#define XEM_SAH_OFFSET	  (XEM_REG_OFFSET + 0xC)	/* Station addr, high */
+#define XEM_SAL_OFFSET	  (XEM_REG_OFFSET + 0x10)	/* Station addr, low */
+#define XEM_MGTCR_OFFSET  (XEM_REG_OFFSET + 0x14)	/* MII mgmt control */
+#define XEM_MGTDR_OFFSET  (XEM_REG_OFFSET + 0x18)	/* MII mgmt data */
+#define XEM_RPLR_OFFSET	  (XEM_REG_OFFSET + 0x1C)	/* Rx packet length */
+#define XEM_TPLR_OFFSET	  (XEM_REG_OFFSET + 0x20)	/* Tx packet length */
+#define XEM_TSR_OFFSET	  (XEM_REG_OFFSET + 0x24)	/* Tx status */
+#define XEM_RMFC_OFFSET	  (XEM_REG_OFFSET + 0x28)	/* Rx missed frames */
+#define XEM_RCC_OFFSET	  (XEM_REG_OFFSET + 0x2C)	/* Rx collisions */
+#define XEM_RFCSEC_OFFSET (XEM_REG_OFFSET + 0x30)	/* Rx FCS errors */
+#define XEM_RAEC_OFFSET	  (XEM_REG_OFFSET + 0x34)	/* Rx alignment errors */
+#define XEM_TEDC_OFFSET	  (XEM_REG_OFFSET + 0x38)	/* Transmit excess
+							 * deferral cnt */
+
+/*
+ * Register offsets for the IPIF components
+ */
+#define XEM_ISR_OFFSET		 0x20UL /* Interrupt status */
+
+#define XEM_DMA_OFFSET		 0x2300UL
+#define XEM_DMA_SEND_OFFSET	 (XEM_DMA_OFFSET + 0x0) /* DMA send channel */
+#define XEM_DMA_RECV_OFFSET	 (XEM_DMA_OFFSET + 0x40)	/* DMA recv channel */
+
+#define XEM_PFIFO_OFFSET	 0x2000UL
+#define XEM_PFIFO_TXREG_OFFSET	 (XEM_PFIFO_OFFSET + 0x0)	/* Tx registers */
+#define XEM_PFIFO_RXREG_OFFSET	 (XEM_PFIFO_OFFSET + 0x10)	/* Rx registers */
+#define XEM_PFIFO_TXDATA_OFFSET	 (XEM_PFIFO_OFFSET + 0x100)	/* Tx keyhole */
+#define XEM_PFIFO_RXDATA_OFFSET	 (XEM_PFIFO_OFFSET + 0x200)	/* Rx keyhole */
+
+/*
+ * EMAC Module Identification Register (EMIR)
+ */
+#define XEM_EMIR_VERSION_MASK	 0xFFFF0000UL	/* Device version */
+#define XEM_EMIR_TYPE_MASK	 0x0000FF00UL	/* Device type */
+
+/*
+ * EMAC Control Register (ECR)
+ */
+#define XEM_ECR_FULL_DUPLEX_MASK	 0x80000000UL	/* Full duplex mode */
+#define XEM_ECR_XMIT_RESET_MASK		 0x40000000UL	/* Reset transmitter */
+#define XEM_ECR_XMIT_ENABLE_MASK	 0x20000000UL	/* Enable transmitter */
+#define XEM_ECR_RECV_RESET_MASK		 0x10000000UL	/* Reset receiver */
+#define XEM_ECR_RECV_ENABLE_MASK	 0x08000000UL	/* Enable receiver */
+#define XEM_ECR_PHY_ENABLE_MASK		 0x04000000UL	/* Enable PHY */
+#define XEM_ECR_XMIT_PAD_ENABLE_MASK	 0x02000000UL	/* Enable xmit pad insert */
+#define XEM_ECR_XMIT_FCS_ENABLE_MASK	 0x01000000UL	/* Enable xmit FCS insert */
+#define XEM_ECR_XMIT_ADDR_INSERT_MASK	 0x00800000UL	/* Enable xmit source addr
+							 * insertion */
+#define XEM_ECR_XMIT_ERROR_INSERT_MASK	 0x00400000UL	/* Insert xmit error */
+#define XEM_ECR_XMIT_ADDR_OVWRT_MASK	 0x00200000UL	/* Enable xmit source addr
+							 * overwrite */
+#define XEM_ECR_LOOPBACK_MASK		 0x00100000UL	/* Enable internal
+							 * loopback */
+#define XEM_ECR_RECV_STRIP_ENABLE_MASK	 0x00080000UL	/* Enable recv pad/fcs strip */
+#define XEM_ECR_UNICAST_ENABLE_MASK	 0x00020000UL	/* Enable unicast addr */
+#define XEM_ECR_MULTI_ENABLE_MASK	 0x00010000UL	/* Enable multicast addr */
+#define XEM_ECR_BROAD_ENABLE_MASK	 0x00008000UL	/* Enable broadcast addr */
+#define XEM_ECR_PROMISC_ENABLE_MASK	 0x00004000UL	/* Enable promiscuous mode */
+#define XEM_ECR_RECV_ALL_MASK		 0x00002000UL	/* Receive all frames */
+#define XEM_ECR_RESERVED2_MASK		 0x00001000UL	/* Reserved */
+#define XEM_ECR_MULTI_HASH_ENABLE_MASK	 0x00000800UL	/* Enable multicast hash */
+#define XEM_ECR_PAUSE_FRAME_MASK	 0x00000400UL	/* Interpret pause frames */
+#define XEM_ECR_CLEAR_HASH_MASK		 0x00000200UL	/* Clear hash table */
+#define XEM_ECR_ADD_HASH_ADDR_MASK	 0x00000100UL	/* Add hash table address */
+
+/*
+ * Interframe Gap Register (IFGR)
+ */
+#define XEM_IFGP_PART1_MASK	    0xF8000000UL	/* Interframe Gap Part1 */
+#define XEM_IFGP_PART1_SHIFT	    27
+#define XEM_IFGP_PART2_MASK	    0x07C00000UL	/* Interframe Gap Part2 */
+#define XEM_IFGP_PART2_SHIFT	    22
+
+/*
+ * Station Address High Register (SAH)
+ */
+#define XEM_SAH_ADDR_MASK	    0x0000FFFFUL	/* Station address high bytes */
+
+/*
+ * Station Address Low Register (SAL)
+ */
+#define XEM_SAL_ADDR_MASK	    0xFFFFFFFFUL	/* Station address low bytes */
+
+/*
+ * MII Management Control Register (MGTCR)
+ */
+#define XEM_MGTCR_START_MASK	    0x80000000UL	/* Start/Busy */
+#define XEM_MGTCR_RW_NOT_MASK	    0x40000000UL	/* Read/Write Not (direction) */
+#define XEM_MGTCR_PHY_ADDR_MASK	    0x3E000000UL	/* PHY address */
+#define XEM_MGTCR_PHY_ADDR_SHIFT    25	/* PHY address shift */
+#define XEM_MGTCR_REG_ADDR_MASK	    0x01F00000UL	/* Register address */
+#define XEM_MGTCR_REG_ADDR_SHIFT    20	/* Register addr shift */
+#define XEM_MGTCR_MII_ENABLE_MASK   0x00080000UL	/* Enable MII from EMAC */
+#define XEM_MGTCR_RD_ERROR_MASK	    0x00040000UL	/* MII mgmt read error */
+
+/*
+ * MII Management Data Register (MGTDR)
+ */
+#define XEM_MGTDR_DATA_MASK	    0x0000FFFFUL	/* MII data */
+
+/*
+ * Receive Packet Length Register (RPLR)
+ */
+#define XEM_RPLR_LENGTH_MASK	    0x0000FFFFUL	/* Receive packet length */
+
+/*
+ * Transmit Packet Length Register (TPLR)
+ */
+#define XEM_TPLR_LENGTH_MASK	    0x0000FFFFUL	/* Transmit packet length */
+
+/*
+ * Transmit Status Register (TSR)
+ */
+#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL	/* Transmit excess deferral */
+#define XEM_TSR_FIFO_UNDERRUN_MASK   0x40000000UL	/* Packet FIFO underrun */
+#define XEM_TSR_ATTEMPTS_MASK	     0x3E000000UL	/* Transmission attempts */
+#define XEM_TSR_LATE_COLLISION_MASK  0x01000000UL	/* Transmit late collision */
+
+/*
+ * Receive Missed Frame Count (RMFC)
+ */
+#define XEM_RMFC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * Receive Collision Count (RCC)
+ */
+#define XEM_RCC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * Receive FCS Error Count (RFCSEC)
+ */
+#define XEM_RFCSEC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * Receive Alignment Error Count (RALN)
+ */
+#define XEM_RAEC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * Transmit Excess Deferral Count (TEDC)
+ */
+#define XEM_TEDC_DATA_MASK	    0x0000FFFFUL
+
+/*
+ * EMAC Interrupt Registers (Status and Enable) masks. These registers are
+ * part of the IPIF IP Interrupt registers
+ */
+#define XEM_EIR_XMIT_DONE_MASK	       0x00000001UL	/* Xmit complete */
+#define XEM_EIR_RECV_DONE_MASK	       0x00000002UL	/* Recv complete */
+#define XEM_EIR_XMIT_ERROR_MASK	       0x00000004UL	/* Xmit error */
+#define XEM_EIR_RECV_ERROR_MASK	       0x00000008UL	/* Recv error */
+#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK  0x00000010UL	/* Xmit status fifo empty */
+#define XEM_EIR_RECV_LFIFO_EMPTY_MASK  0x00000020UL	/* Recv length fifo empty */
+#define XEM_EIR_XMIT_LFIFO_FULL_MASK   0x00000040UL	/* Xmit length fifo full */
+#define XEM_EIR_RECV_LFIFO_OVER_MASK   0x00000080UL	/* Recv length fifo
+							 * overrun */
+#define XEM_EIR_RECV_LFIFO_UNDER_MASK  0x00000100UL	/* Recv length fifo
+							 * underrun */
+#define XEM_EIR_XMIT_SFIFO_OVER_MASK   0x00000200UL	/* Xmit status fifo
+							 * overrun */
+#define XEM_EIR_XMIT_SFIFO_UNDER_MASK  0x00000400UL	/* Transmit status fifo
+							 * underrun */
+#define XEM_EIR_XMIT_LFIFO_OVER_MASK   0x00000800UL	/* Transmit length fifo
+							 * overrun */
+#define XEM_EIR_XMIT_LFIFO_UNDER_MASK  0x00001000UL	/* Transmit length fifo
+							 * underrun */
+#define XEM_EIR_XMIT_PAUSE_MASK	       0x00002000UL	/* Transmit pause pkt
+							 * received */
+#define XEM_EIR_RECV_DFIFO_OVER_MASK   0x00004000UL	/* Receive data fifo
+							 * overrun */
+#define XEM_EIR_RECV_MISSED_FRAME_MASK 0x00008000UL	/* Receive missed frame
+							 * error */
+#define XEM_EIR_RECV_COLLISION_MASK    0x00010000UL	/* Receive collision
+							 * error */
+#define XEM_EIR_RECV_FCS_ERROR_MASK    0x00020000UL	/* Receive FCS error */
+#define XEM_EIR_RECV_LEN_ERROR_MASK    0x00040000UL	/* Receive length field
+							 * error */
+#define XEM_EIR_RECV_SHORT_ERROR_MASK  0x00080000UL	/* Receive short frame
+							 * error */
+#define XEM_EIR_RECV_LONG_ERROR_MASK   0x00100000UL	/* Receive long frame
+							 * error */
+#define XEM_EIR_RECV_ALIGN_ERROR_MASK  0x00200000UL	/* Receive alignment
+							 * error */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************
+*
+* Low-level driver macros and functions. The list below provides signatures
+* to help the user use the macros.
+*
+* u32 XEmac_mReadReg(u32 BaseAddress, int RegOffset)
+* void XEmac_mWriteReg(u32 BaseAddress, int RegOffset, u32 Mask)
+*
+* void XEmac_mSetControlReg(u32 BaseAddress, u32 Mask)
+* void XEmac_mSetMacAddress(u32 BaseAddress, u8 *AddressPtr)
+*
+* void XEmac_mEnable(u32 BaseAddress)
+* void XEmac_mDisable(u32 BaseAddress)
+*
+* u32 XEmac_mIsTxDone(u32 BaseAddress)
+* u32 XEmac_mIsRxEmpty(u32 BaseAddress)
+*
+* void XEmac_SendFrame(u32 BaseAddress, u8 *FramePtr, int Size)
+* int XEmac_RecvFrame(u32 BaseAddress, u8 *FramePtr)
+*
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mReadReg(BaseAddress, RegOffset) \
+		    XIo_In32((BaseAddress) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mWriteReg(BaseAddress, RegOffset, Data) \
+		    XIo_Out32((BaseAddress) + (RegOffset), (Data))
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the control register. Use the XEM_ECR_* constants
+* defined above to create the bit-mask to be written to the register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    Mask is the 16-bit value to write to the control register
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mSetControlReg(BaseAddress, Mask) \
+		    XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, (Mask))
+
+/****************************************************************************/
+/**
+*
+* Set the station address of the EMAC device.
+*
+* @param    BaseAddress is the base address of the device
+* @param    AddressPtr is a pointer to a 6-byte MAC address
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mSetMacAddress(BaseAddress, AddressPtr)		    \
+{								    \
+    u32 MacAddr;						\
+								    \
+    MacAddr = ((AddressPtr)[0] << 8) | (AddressPtr)[1];		    \
+    XIo_Out32((BaseAddress) + XEM_SAH_OFFSET, MacAddr);		    \
+								    \
+    MacAddr = ((AddressPtr)[2] << 24) | ((AddressPtr)[3] << 16) |   \
+	      ((AddressPtr)[4] << 8) | (AddressPtr)[5];		    \
+								    \
+    XIo_Out32((BaseAddress) + XEM_SAL_OFFSET, MacAddr);		    \
+}
+
+/****************************************************************************/
+/**
+*
+* Enable the transmitter and receiver. Preserve the contents of the control
+* register.
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mEnable(BaseAddress) \
+{ \
+    u32 Control; \
+    Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
+    Control &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); \
+    Control |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); \
+    XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
+}
+
+/****************************************************************************/
+/**
+*
+* Disable the transmitter and receiver. Preserve the contents of the control
+* register.
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mDisable(BaseAddress) \
+		XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, \
+		    XIo_In32((BaseAddress) + XEM_ECR_OFFSET) & \
+		    ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Check to see if the transmission is complete.
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   TRUE if it is done, or FALSE if it is not.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mIsTxDone(BaseAddress) \
+	     (XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_XMIT_DONE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Check to see if the receive FIFO is empty.
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   TRUE if it is empty, or FALSE if it is not.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mIsRxEmpty(BaseAddress) \
+	  (!(XIo_In32((BaseAddress) + XEM_ISR_OFFSET) & XEM_EIR_RECV_DONE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Reset MII compliant PHY
+*
+* @param    BaseAddress is the base address of the device
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XEmac_mPhyReset(BaseAddress) \
+{ \
+    u32 Control;				    \
+    Control = XIo_In32((BaseAddress) + XEM_ECR_OFFSET); \
+    Control &= ~XEM_ECR_PHY_ENABLE_MASK;		\
+    XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
+    Control |= XEM_ECR_PHY_ENABLE_MASK;			\
+    XIo_Out32((BaseAddress) + XEM_ECR_OFFSET, Control); \
+}
+
+/************************** Function Prototypes ******************************/
+
+void XEmac_SendFrame(u32 BaseAddress, u8 * FramePtr, int Size);
+int XEmac_RecvFrame(u32 BaseAddress, u8 * FramePtr);
+
+#endif				/* end of protection macro */
diff --git a/board/xilinx/xilinx_enet/xemac_options.c b/board/xilinx/xilinx_enet/xemac_options.c
new file mode 100755
index 0000000..1f225f8
--- /dev/null
+++ b/board/xilinx/xilinx_enet/xemac_options.c
@@ -0,0 +1,318 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_options.c
+*
+* Functions in this file handle configuration of the XEmac driver.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XEM_MAX_IFG         32	/* Maximum Interframe gap value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * A table of options and masks. This table maps the user-visible options with
+ * the control register masks. It is used in Set/GetOptions as an alternative
+ * to a series of if/else pairs. Note that the polled options does not have a
+ * corresponding entry in the control register, so it does not exist in the
+ * table.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionMap;
+
+static OptionMap OptionsTable[] = {
+	{XEM_UNICAST_OPTION, XEM_ECR_UNICAST_ENABLE_MASK},
+	{XEM_BROADCAST_OPTION, XEM_ECR_BROAD_ENABLE_MASK},
+	{XEM_PROMISC_OPTION, XEM_ECR_PROMISC_ENABLE_MASK},
+	{XEM_FDUPLEX_OPTION, XEM_ECR_FULL_DUPLEX_MASK},
+	{XEM_LOOPBACK_OPTION, XEM_ECR_LOOPBACK_MASK},
+	{XEM_MULTICAST_OPTION, XEM_ECR_MULTI_ENABLE_MASK},
+	{XEM_FLOW_CONTROL_OPTION, XEM_ECR_PAUSE_FRAME_MASK},
+	{XEM_INSERT_PAD_OPTION, XEM_ECR_XMIT_PAD_ENABLE_MASK},
+	{XEM_INSERT_FCS_OPTION, XEM_ECR_XMIT_FCS_ENABLE_MASK},
+	{XEM_INSERT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_INSERT_MASK},
+	{XEM_OVWRT_ADDR_OPTION, XEM_ECR_XMIT_ADDR_OVWRT_MASK},
+	{XEM_STRIP_PAD_FCS_OPTION, XEM_ECR_RECV_STRIP_ENABLE_MASK}
+};
+
+#define XEM_NUM_OPTIONS     (sizeof(OptionsTable) / sizeof(OptionMap))
+
+/*****************************************************************************/
+/**
+*
+* Set Ethernet driver/device options.  The device must be stopped before
+* calling this function.  The options are contained within a bit-mask with each
+* bit representing an option (i.e., you can OR the options together). A one (1)
+* in the bit-mask turns an option on, and a zero (0) turns the option off.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param OptionsFlag is a bit-mask representing the Ethernet options to turn on
+*        or off. See xemac.h for a description of the available options.
+*
+* @return
+*
+* - XST_SUCCESS if the options were set successfully
+* - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+*
+* @note
+*
+* This function is not thread-safe and makes use of internal resources that are
+* shared between the Start, Stop, and SetOptions functions, so if one task
+* might be setting device options while another is trying to start the device,
+* protection of this shared data (typically using a semaphore) is required.
+*
+******************************************************************************/
+XStatus
+XEmac_SetOptions(XEmac * InstancePtr, u32 OptionsFlag)
+{
+	u32 ControlReg;
+	int Index;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) {
+		if (OptionsFlag & OptionsTable[Index].Option) {
+			ControlReg |= OptionsTable[Index].Mask;	/* turn it on */
+		} else {
+			ControlReg &= ~OptionsTable[Index].Mask;	/* turn it off */
+		}
+	}
+
+	/*
+	 * TODO: need to validate addr-overwrite only if addr-insert?
+	 */
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIo_Out32(InstancePtr->BaseAddress + XEM_ECR_OFFSET, ControlReg);
+
+	/*
+	 * Check the polled option
+	 */
+	if (OptionsFlag & XEM_POLLED_OPTION) {
+		InstancePtr->IsPolled = TRUE;
+	} else {
+		InstancePtr->IsPolled = FALSE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get Ethernet driver/device options. The 32-bit value returned is a bit-mask
+* representing the options.  A one (1) in the bit-mask means the option is on,
+* and a zero (0) means the option is off.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+*
+* @return
+*
+* The 32-bit value of the Ethernet options. The value is a bit-mask
+* representing all options that are currently enabled. See xemac.h for a
+* description of the available options.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+u32
+XEmac_GetOptions(XEmac * InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ControlReg;
+	int Index;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Get the control register to determine which options are currently set.
+	 */
+	ControlReg = XIo_In32(InstancePtr->BaseAddress + XEM_ECR_OFFSET);
+
+	/*
+	 * Loop through the options table to determine which options are set
+	 */
+	for (Index = 0; Index < XEM_NUM_OPTIONS; Index++) {
+		if (ControlReg & OptionsTable[Index].Mask) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	if (InstancePtr->IsPolled) {
+		OptionsFlag |= XEM_POLLED_OPTION;
+	}
+
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* Set the Interframe Gap (IFG), which is the time the MAC delays between
+* transmitting frames.  There are two parts required.  The total interframe gap
+* is the total of the two parts.  The values provided for the Part1 and Part2
+* parameters are multiplied by 4 to obtain the bit-time interval. The first
+* part should be the first 2/3 of the total interframe gap. The MAC will reset
+* the interframe gap timer if carrier sense becomes true during the period
+* defined by interframe gap Part1. Part1 may be shorter than 2/3 the total and
+* can be as small as zero. The second part should be the last 1/3 of the total
+* interframe gap, but can be as large as the total interframe gap. The MAC
+* will not reset the interframe gap timer if carrier sense becomes true during
+* the period defined by interframe gap Part2.
+*
+* The device must be stopped before setting the interframe gap.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Part1 is the interframe gap part 1 (which will be multiplied by 4 to
+*        get the bit-time interval).
+* @param Part2 is the interframe gap part 2 (which will be multiplied by 4 to
+*        get the bit-time interval).
+*
+* @return
+*
+* - XST_SUCCESS if the interframe gap was set successfully
+* - XST_DEVICE_IS_STARTED if the device has not been stopped
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+XStatus
+XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2)
+{
+	u32 Ifg;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(Part1 < XEM_MAX_IFG);
+	XASSERT_NONVOID(Part2 < XEM_MAX_IFG);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure device has been stopped
+	 */
+	if (InstancePtr->IsStarted == XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	Ifg = Part1 << XEM_IFGP_PART1_SHIFT;
+	Ifg |= (Part2 << XEM_IFGP_PART2_SHIFT);
+	XIo_Out32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET, Ifg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Get the interframe gap, parts 1 and 2. See the description of interframe gap
+* above in XEmac_SetInterframeGap().
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param Part1Ptr is a pointer to an 8-bit buffer into which the interframe gap
+*        part 1 value will be copied.
+* @param Part2Ptr is a pointer to an 8-bit buffer into which the interframe gap
+*        part 2 value will be copied.
+*
+* @return
+*
+* None. The values of the interframe gap parts are copied into the
+* output parameters.
+*
+******************************************************************************/
+void
+XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr)
+{
+	u32 Ifg;
+
+	XASSERT_VOID(InstancePtr != NULL);
+	XASSERT_VOID(Part1Ptr != NULL);
+	XASSERT_VOID(Part2Ptr != NULL);
+	XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	Ifg = XIo_In32(InstancePtr->BaseAddress + XEM_IFGP_OFFSET);
+	*Part1Ptr = (Ifg & XEM_IFGP_PART1_MASK) >> XEM_IFGP_PART1_SHIFT;
+	*Part2Ptr = (Ifg & XEM_IFGP_PART2_MASK) >> XEM_IFGP_PART2_SHIFT;
+}
diff --git a/board/xilinx/xilinx_enet/xemac_polled.c b/board/xilinx/xilinx_enet/xemac_polled.c
new file mode 100755
index 0000000..23768bc
--- /dev/null
+++ b/board/xilinx/xilinx_enet/xemac_polled.c
@@ -0,0 +1,482 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemac_polled.c
+*
+* Contains functions used when the driver is in polled mode. Use the
+* XEmac_SetOptions() function to put the driver into polled mode.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rpm  07/31/01 First release
+* 1.00b rpm  02/20/02 Repartitioned files and functions
+* 1.00c rpm  12/05/02 New version includes support for simple DMA
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xbasic_types.h"
+#include "xemac_i.h"
+#include "xio.h"
+#include "xipif_v1_23_b.h"	/* Uses v1.23b of the IPIF */
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Send an Ethernet frame in polled mode.  The device/driver must be in polled
+* mode before calling this function. The driver writes the frame directly to
+* the MAC's packet FIFO, then enters a loop checking the device status for
+* completion or error. Statistics are updated if an error occurs. The buffer
+* to be sent must be word-aligned.
+*
+* It is assumed that the upper layer software supplies a correctly formatted
+* Ethernet frame, including the destination and source addresses, the
+* type/length field, and the data field.  It is also assumed that upper layer
+* software does not append FCS at the end of the frame.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BufPtr is a pointer to a word-aligned buffer containing the Ethernet
+*        frame to be sent.
+* @param ByteCount is the size of the Ethernet frame.
+*
+* @return
+*
+* - XST_SUCCESS if the frame was sent successfully
+* - XST_DEVICE_IS_STOPPED if the device has not yet been started
+* - XST_NOT_POLLED if the device is not in polled mode
+* - XST_FIFO_NO_ROOM if there is no room in the EMAC's length FIFO for this frame
+* - XST_FIFO_ERROR if the FIFO was overrun or underrun. This error is critical
+*   and requires the caller to reset the device.
+* - XST_EMAC_COLLISION if the send failed due to excess deferral or late
+*   collision
+*
+* @note
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that transmission is
+* done). If this is of concern to the user, the user should provide protection
+* from this problem - perhaps by using a different timer thread to monitor the
+* PollSend thread. On a 10Mbps MAC, it takes about 1.21 msecs to transmit a
+* maximum size Ethernet frame (1518 bytes). On a 100Mbps MAC, it takes about
+* 121 usecs to transmit a maximum size Ethernet frame.
+*
+* @internal
+*
+* The EMAC uses FIFOs behind its length and status registers. For this reason,
+* it is important to keep the length, status, and data FIFOs in sync when
+* reading or writing to them.
+*
+******************************************************************************/
+XStatus
+XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount)
+{
+	u32 IntrStatus;
+	u32 XmitStatus;
+	XStatus Result;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufPtr != NULL);
+	XASSERT_NONVOID(ByteCount > XEM_HDR_SIZE);	/* send at least 1 byte */
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure the device is configured for polled mode and it is started
+	 */
+	if (!InstancePtr->IsPolled) {
+		return XST_NOT_POLLED;
+	}
+
+	if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STOPPED;
+	}
+
+	/*
+	 * Check for overruns and underruns for the transmit status and length
+	 * FIFOs and make sure the send packet FIFO is not deadlocked. Any of these
+	 * conditions is bad enough that we do not want to continue. The upper layer
+	 * software should reset the device to resolve the error.
+	 */
+	IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+
+	/*
+	 * Overrun errors
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+			  XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+		InstancePtr->Stats.XmitOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Underrun errors
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+			  XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+		InstancePtr->Stats.XmitUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->SendFifo)) {
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Before writing to the data FIFO, make sure the length FIFO is not
+	 * full.  The data FIFO might not be full yet even though the length FIFO
+	 * is. This avoids an overrun condition on the length FIFO and keeps the
+	 * FIFOs in sync.
+	 */
+	if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
+		/*
+		 * Clear the latched LFIFO_FULL bit so next time around the most
+		 * current status is represented
+		 */
+		XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
+				      XEM_EIR_XMIT_LFIFO_FULL_MASK);
+		return XST_FIFO_NO_ROOM;
+	}
+
+	/*
+	 * This is a non-blocking write. The packet FIFO returns an error if there
+	 * is not enough room in the FIFO for this frame.
+	 */
+	Result =
+	    XPacketFifoV100b_Write(&InstancePtr->SendFifo, BufPtr, ByteCount);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	/*
+	 * Loop on the MAC's status to wait for any pause to complete.
+	 */
+	IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+
+	while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
+		IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+		/*
+		   * Clear the pause status from the transmit status register
+		 */
+		XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
+				      IntrStatus & XEM_EIR_XMIT_PAUSE_MASK);
+	}
+
+	/*
+	 * Set the MAC's transmit packet length register to tell it to transmit
+	 */
+	XIo_Out32(InstancePtr->BaseAddress + XEM_TPLR_OFFSET, ByteCount);
+
+	/*
+	 * Loop on the MAC's status to wait for the transmit to complete. The
+	 * transmit status is in the FIFO when the XMIT_DONE bit is set.
+	 */
+	do {
+		IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+	}
+	while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0);
+
+	XmitStatus = XIo_In32(InstancePtr->BaseAddress + XEM_TSR_OFFSET);
+
+	InstancePtr->Stats.XmitFrames++;
+	InstancePtr->Stats.XmitBytes += ByteCount;
+
+	/*
+	 * Check for various errors, bump statistics, and return an error status.
+	 */
+
+	/*
+	 * Overrun errors
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+			  XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
+		InstancePtr->Stats.XmitOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Underrun errors
+	 */
+	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+			  XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
+		InstancePtr->Stats.XmitUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Clear the interrupt status register of transmit statuses
+	 */
+	XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
+			      IntrStatus & XEM_EIR_XMIT_ALL_MASK);
+
+	/*
+	 * Collision errors are stored in the transmit status register
+	 * instead of the interrupt status register
+	 */
+	if (XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) {
+		InstancePtr->Stats.XmitExcessDeferral++;
+		return XST_EMAC_COLLISION_ERROR;
+	}
+
+	if (XmitStatus & XEM_TSR_LATE_COLLISION_MASK) {
+		InstancePtr->Stats.XmitLateCollisionErrors++;
+		return XST_EMAC_COLLISION_ERROR;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Receive an Ethernet frame in polled mode. The device/driver must be in polled
+* mode before calling this function. The driver receives the frame directly
+* from the MAC's packet FIFO. This is a non-blocking receive, in that if there
+* is no frame ready to be received at the device, the function returns with an
+* error. The MAC's error status is not checked, so statistics are not updated
+* for polled receive. The buffer into which the frame will be received must be
+* word-aligned.
+*
+* @param InstancePtr is a pointer to the XEmac instance to be worked on.
+* @param BufPtr is a pointer to a word-aligned buffer into which the received
+*        Ethernet frame will be copied.
+* @param ByteCountPtr is both an input and an output parameter. It is a pointer
+*        to a 32-bit word that contains the size of the buffer on entry into the
+*        function and the size the received frame on return from the function.
+*
+* @return
+*
+* - XST_SUCCESS if the frame was sent successfully
+* - XST_DEVICE_IS_STOPPED if the device has not yet been started
+* - XST_NOT_POLLED if the device is not in polled mode
+* - XST_NO_DATA if there is no frame to be received from the FIFO
+* - XST_BUFFER_TOO_SMALL if the buffer to receive the frame is too small for
+*   the frame waiting in the FIFO.
+*
+* @note
+*
+* Input buffer must be big enough to hold the largest Ethernet frame. Buffer
+* must also be 32-bit aligned.
+*
+* @internal
+*
+* The EMAC uses FIFOs behind its length and status registers. For this reason,
+* it is important to keep the length, status, and data FIFOs in sync when
+* reading or writing to them.
+*
+******************************************************************************/
+XStatus
+XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr)
+{
+	XStatus Result;
+	u32 PktLength;
+	u32 IntrStatus;
+
+	XASSERT_NONVOID(InstancePtr != NULL);
+	XASSERT_NONVOID(BufPtr != NULL);
+	XASSERT_NONVOID(ByteCountPtr != NULL);
+	XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
+
+	/*
+	 * Be sure the device is configured for polled mode and it is started
+	 */
+	if (!InstancePtr->IsPolled) {
+		return XST_NOT_POLLED;
+	}
+
+	if (InstancePtr->IsStarted != XCOMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STOPPED;
+	}
+
+	/*
+	 * Make sure the buffer is big enough to hold the maximum frame size.
+	 * We need to do this because as soon as we read the MAC's packet length
+	 * register, which is actually a FIFO, we remove that length from the
+	 * FIFO.  We do not want to read the length FIFO without also reading the
+	 * data FIFO since this would get the FIFOs out of sync.  So we have to
+	 * make this restriction.
+	 */
+	if (*ByteCountPtr < XEM_MAX_FRAME_SIZE) {
+		return XST_BUFFER_TOO_SMALL;
+	}
+
+	/*
+	 * First check for packet FIFO deadlock and return an error if it has
+	 * occurred. A reset by the caller is necessary to correct this problem.
+	 */
+	if (XPF_V100B_IS_DEADLOCKED(&InstancePtr->RecvFifo)) {
+		InstancePtr->Stats.FifoErrors++;
+		return XST_FIFO_ERROR;
+	}
+
+	/*
+	 * Get the interrupt status to know what happened (whether an error occurred
+	 * and/or whether frames have been received successfully). When clearing the
+	 * intr status register, clear only statuses that pertain to receive.
+	 */
+	IntrStatus = XIIF_V123B_READ_IISR(InstancePtr->BaseAddress);
+	XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress,
+			      IntrStatus & XEM_EIR_RECV_ALL_MASK);
+
+	/*
+	 * Check receive errors and bump statistics so the caller will have a clue
+	 * as to why data may not have been received. We continue on if an error
+	 * occurred since there still may be frames that were received successfully.
+	 */
+	if (IntrStatus & (XEM_EIR_RECV_LFIFO_OVER_MASK |
+			  XEM_EIR_RECV_DFIFO_OVER_MASK)) {
+		InstancePtr->Stats.RecvOverrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+	}
+
+	if (IntrStatus & XEM_EIR_RECV_LFIFO_UNDER_MASK) {
+		InstancePtr->Stats.RecvUnderrunErrors++;
+		InstancePtr->Stats.FifoErrors++;
+	}
+
+	/*
+	 * General receive errors
+	 */
+	if (IntrStatus & XEM_EIR_RECV_ERROR_MASK) {
+		if (IntrStatus & XEM_EIR_RECV_MISSED_FRAME_MASK) {
+			InstancePtr->Stats.RecvMissedFrameErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RMFC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_COLLISION_MASK) {
+			InstancePtr->Stats.RecvCollisionErrors =
+			    XIo_In32(InstancePtr->BaseAddress + XEM_RCC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_FCS_ERROR_MASK) {
+			InstancePtr->Stats.RecvFcsErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RFCSEC_OFFSET);
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_LEN_ERROR_MASK) {
+			InstancePtr->Stats.RecvLengthFieldErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_SHORT_ERROR_MASK) {
+			InstancePtr->Stats.RecvShortErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_LONG_ERROR_MASK) {
+			InstancePtr->Stats.RecvLongErrors++;
+		}
+
+		if (IntrStatus & XEM_EIR_RECV_ALIGN_ERROR_MASK) {
+			InstancePtr->Stats.RecvAlignmentErrors =
+			    XIo_In32(InstancePtr->BaseAddress +
+				     XEM_RAEC_OFFSET);
+		}
+	}
+
+	/*
+	 * Before reading from the length FIFO, make sure the length FIFO is not
+	 * empty. We could cause an underrun error if we try to read from an
+	 * empty FIFO.
+	 */
+	if ((IntrStatus & XEM_EIR_RECV_DONE_MASK) == 0) {
+		return XST_NO_DATA;
+	}
+
+	/*
+	 * Determine, from the MAC, the length of the next packet available
+	 * in the data FIFO (there should be a non-zero length here)
+	 */
+	PktLength = XIo_In32(InstancePtr->BaseAddress + XEM_RPLR_OFFSET);
+	if (PktLength == 0) {
+		return XST_NO_DATA;
+	}
+
+	/*
+	 * Write the RECV_DONE bit in the status register to clear it. This bit
+	 * indicates the RPLR is non-empty, and we know it's set at this point.
+	 * We clear it so that subsequent entry into this routine will reflect the
+	 * current status. This is done because the non-empty bit is latched in the
+	 * IPIF, which means it may indicate a non-empty condition even though
+	 * there is something in the FIFO.
+	 */
+	XIIF_V123B_WRITE_IISR(InstancePtr->BaseAddress, XEM_EIR_RECV_DONE_MASK);
+
+	/*
+	 * We assume that the MAC never has a length bigger than the largest
+	 * Ethernet frame, so no need to make another check here.
+	 */
+
+	/*
+	 * This is a non-blocking read. The FIFO returns an error if there is
+	 * not at least the requested amount of data in the FIFO.
+	 */
+	Result =
+	    XPacketFifoV100b_Read(&InstancePtr->RecvFifo, BufPtr, PktLength);
+	if (Result != XST_SUCCESS) {
+		return Result;
+	}
+
+	InstancePtr->Stats.RecvFrames++;
+	InstancePtr->Stats.RecvBytes += PktLength;
+
+	*ByteCountPtr = PktLength;
+
+	return XST_SUCCESS;
+}
diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c
new file mode 100755
index 0000000..f3ecba7
--- /dev/null
+++ b/board/xilinx/xilinx_iic/iic_adapter.c
@@ -0,0 +1,530 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2004 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+
+#include <common.h>
+#include <environment.h>
+#include <net.h>
+#include <configs/ml300.h>
+#include "xparameters.h"
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#include <i2c.h>
+#include "xiic_l.h"
+
+#define IIC_DELAY     5000
+
+static u8 envStep = 0;		/* 0 means crc has not been read */
+const u8 hex[] = "0123456789ABCDEF"; /* lookup table for ML300 CRC */
+
+/************************************************************************
+ * Use Xilinx provided driver to send data to EEPROM using iic bus.
+ */
+static void
+send(u32 adr, u8 * data, u32 len)
+{
+	u8 sendBuf[34];		/* first 2-bit is address and others are data */
+	u32 pos, wlen;
+	u32 ret;
+
+	wlen = 32;
+	for (pos = 0; pos < len; pos += 32) {
+		if ((len - pos) < 32)
+			wlen = len - pos;
+
+		/* Put address and data bits together */
+		sendBuf[0] = (u8) ((adr + pos) >> 8);
+		sendBuf[1] = (u8) (adr + pos);
+		memcpy(&sendBuf[2], &data[pos], wlen);
+
+		/* Send to EEPROM through iic bus */
+		ret = XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1,
+				sendBuf, wlen + 2);
+
+		udelay(IIC_DELAY);
+	}
+}
+
+/************************************************************************
+ * Use Xilinx provided driver to read data from EEPROM using the iic bus.
+ */
+static void
+receive(u32 adr, u8 * data, u32 len)
+{
+	u8 address[2];
+	u32 ret;
+
+	address[0] = (u8) (adr >> 8);
+	address[1] = (u8) adr;
+
+	/* Provide EEPROM address */
+	ret =
+	    XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, address,
+		      2);
+	/* Receive data from EEPROM */
+	ret =
+	    XIic_Recv(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, data, len);
+}
+
+/************************************************************************
+ * Convert a hexadecimal string to its equivalent integer value.
+ */
+static u8
+axtoi(u8 * hexStg)
+{
+	u8 n;			/* position in string */
+	u8 m;			/* position in digit[] to shift */
+	u8 count;		/* loop index */
+	u8 intValue;		/* integer value of hex string */
+	u8 digit[2];		/* hold values to convert */
+
+	for (n = 0; n < 2; n++) {
+		if (hexStg[n] == '\0')
+			break;
+		if (hexStg[n] > 0x29 && hexStg[n] < 0x40)
+			digit[n] = hexStg[n] & 0x0f;
+		else if (hexStg[n] >= 'a' && hexStg[n] <= 'f')
+			digit[n] = (hexStg[n] & 0x0f) + 9;
+		else if (hexStg[n] >= 'A' && hexStg[n] <= 'F')
+			digit[n] = (hexStg[n] & 0x0f) + 9;
+		else
+			break;
+	}
+
+	intValue = 0;
+	count = n;
+	m = n - 1;
+	n = 0;
+	while (n < count) {
+		intValue = intValue | (digit[n] << (m << 2));
+		m--;		/* adjust the position to set */
+		n++;		/* next digit to process */
+	}
+
+	return (intValue);
+}
+
+/************************************************************************
+ * Convert an integer string to its equivalent value.
+ */
+static u8
+atoi(uchar * string)
+{
+	u8 res = 0;
+	while (*string >= '0' && *string <= '9') {
+		res *= 10;
+		res += *string - '0';
+		string++;
+	}
+
+	return res;
+}
+
+/************************************************************************
+ * Key-value pairs are separated by "=" sign.
+ */
+static void
+findKey(uchar * buffer, int *loc, u8 len)
+{
+	u32 i;
+
+	for (i = 0; i < len; i++)
+		if (buffer[i] == '=') {
+			*loc = i;
+			return;
+		}
+
+	/* return -1 is no "=" sign found */
+	*loc = -1;
+}
+
+/************************************************************************
+ * Compute a new ML300 CRC when user calls the saveenv command.
+ * Also update EEPROM with new CRC value.
+ */
+static u8
+update_crc(u32 len, uchar * data)
+{
+	uchar temp[6] = { 'C', '=', 0x00, 0x00, 0x00, 0x00 };
+	u32 crc;		/* new crc value */
+	u32 i;
+
+	crc = 0;
+
+	/* calculate new CRC */
+	for (i = 0; i < len; i++)
+		crc += data[i];
+
+	/* CRC includes key for check sum */
+	crc += 'C' + '=';
+
+	/* compose new CRC to be updated */
+	temp[2] = hex[(crc >> 4) & 0xf];
+	temp[3] = hex[crc & 0xf];
+
+	/* check to see if env size exceeded */
+	if (len + 6 > ENV_SIZE) {
+		printf("ERROR: not enough space to store CRC on EEPROM");
+		return 1;
+	}
+
+	memcpy(data + len, temp, 6);
+	return 0;
+}
+
+/************************************************************************
+ * Read out ML300 CRC and compare it with a runtime calculated ML300 CRC.
+ * If equal, then pass back a u-boot CRC value, otherwise pass back
+ * junk to indicate CRC error.
+*/
+static void
+read_crc(uchar * buffer, int len)
+{
+	u32 addr, n;
+	u32 crc;		/* runtime crc */
+	u8 old[2] = { 0xff, 0xff };	/* current CRC in EEPROM */
+	u8 stop;		/* indication of end of env data */
+	u8 pre;			/* previous EEPROM data bit */
+	int i, loc;
+
+	addr = CFG_ENV_OFFSET;	/* start from first env address */
+	n = 0;
+	pre = 1;
+	stop = 1;
+	crc = 0;
+
+	/* calculate runtime CRC according to ML300 and read back
+	   old CRC stored in the EEPROM */
+	while (n < CFG_ENV_SIZE) {
+		receive(addr, buffer, len);
+
+		/* found two null chars, end of env */
+		if ((pre || buffer[0]) == 0)
+			break;
+
+		findKey(buffer, &loc, len);
+
+		/* found old check sum, read and store old CRC */
+		if ((loc == 0 && pre == 'C')
+		    || (loc > 0 && buffer[loc - 1] == 'C'))
+			receive(addr + loc + 1, old, 2);
+
+		pre = buffer[len - 1];
+
+		/* calculate runtime ML300 CRC */
+		crc += buffer[0];
+		i = 1;
+		do {
+			crc += buffer[i];
+			stop = buffer[i] || buffer[i - 1];
+			i++;
+		} while (stop && (i < len));
+
+		if (stop == 0)
+			break;
+
+		n += len;
+		addr += len;
+	}
+
+	/* exclude old CRC from runtime calculation */
+	crc -= (old[0] + old[1]);
+
+	/* match CRC values, send back u-boot CRC */
+	if ((old[0] == hex[(crc >> 4) & 0xf])
+	    && (old[1] == hex[crc & 0xf])) {
+		crc = 0;
+		n = 0;
+		addr =
+		    CFG_ENV_OFFSET - offsetof(env_t, crc) + offsetof(env_t,
+								     data);
+		/* calculate u-boot crc */
+		while (n < ENV_SIZE) {
+			receive(addr, buffer, len);
+			crc = crc32(crc, buffer, len);
+			n += len;
+			addr += len;
+		}
+
+		memcpy(buffer, &crc, 4);
+	}
+}
+
+/************************************************************************
+ * Convert IP address to hexadecimals.
+ */
+static void
+ip_ml300(uchar * s, uchar * res)
+{
+	char temp[2];
+	u8 i;
+
+	res[0] = 0x00;
+
+	for (i = 0; i < 4; i++) {
+		sprintf(temp, "%02x", atoi(s));
+		s = (uchar *)strchr((char *)s, '.') + 1;
+		strcat((char *)res, temp);
+	}
+}
+
+/************************************************************************
+ * Change 0xff (255), a dummy null char to 0x00.
+ */
+static void
+change_null(uchar * s)
+{
+	if (s != NULL) {
+		change_null((uchar *)strchr((char *)s + 1, 255));
+		*(strchr((char *)s, 255)) = '\0';
+	}
+}
+
+/************************************************************************
+ * Update environment variable name and values to u-boot standard.
+ */
+void
+convert_env(void)
+{
+	char *s;		/* pointer to env value */
+	char temp[20];		/* temp storage for addresses */
+
+	/* E -> ethaddr */
+	s = getenv("E");
+	if (s != NULL) {
+		sprintf(temp, "%c%c.%c%c.%c%c.%c%c.%c%c.%c%c",
+			s[0], s[1],  s[ 2], s[ 3],
+			s[4], s[5],  s[ 6], s[ 7],
+			s[8], s[9],  s[10], s[11] );
+		setenv("ethaddr", temp);
+		setenv("E", NULL);
+	}
+
+	/* L -> serial# */
+	s = getenv("L");
+	if (s != NULL) {
+		setenv("serial#", s);
+		setenv("L", NULL);
+	}
+
+	/* I -> ipaddr */
+	s = getenv("I");
+	if (s != NULL) {
+		sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
+			axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
+		setenv("ipaddr", temp);
+		setenv("I", NULL);
+	}
+
+	/* S -> serverip */
+	s = getenv("S");
+	if (s != NULL) {
+		sprintf(temp, "%d.%d.%d.%d", axtoi((u8 *)s), axtoi((u8 *)(s + 2)),
+			axtoi((u8 *)(s + 4)), axtoi((u8 *)(s + 6)));
+		setenv("serverip", temp);
+		setenv("S", NULL);
+	}
+
+	/* A -> bootargs */
+	s = getenv("A");
+	if (s != NULL) {
+		setenv("bootargs", s);
+		setenv("A", NULL);
+	}
+
+	/* F -> bootfile */
+	s = getenv("F");
+	if (s != NULL) {
+		setenv("bootfile", s);
+		setenv("F", NULL);
+	}
+
+	/* M -> bootcmd */
+	s = getenv("M");
+	if (s != NULL) {
+		setenv("bootcmd", s);
+		setenv("M", NULL);
+	}
+
+	/* Don't include C (CRC) */
+	setenv("C", NULL);
+}
+
+/************************************************************************
+ * Save user modified environment values back to EEPROM.
+ */
+static void
+save_env(void)
+{
+	char eprom[ENV_SIZE];	/* buffer to be written back to EEPROM */
+	char *s, temp[20];
+	char ff[] = { 0xff, 0x00 };	/* dummy null value */
+	u32 len;		/* length of env to be written to EEPROM */
+
+	eprom[0] = 0x00;
+
+	/* ethaddr -> E */
+	s = getenv("ethaddr");
+	if (s != NULL) {
+		strcat(eprom, "E=");
+		sprintf(temp, "%c%c%c%c%c%c%c%c%c%c%c%c",
+			*s, *(s + 1), *(s + 3), *(s + 4), *(s + 6), *(s + 7),
+			*(s + 9), *(s + 10), *(s + 12), *(s + 13), *(s + 15),
+			*(s + 16));
+		strcat(eprom, temp);
+		strcat(eprom, ff);
+	}
+
+	/* serial# -> L */
+	s = getenv("serial#");
+	if (s != NULL) {
+		strcat(eprom, "L=");
+		strcat(eprom, s);
+		strcat(eprom, ff);
+	}
+
+	/* ipaddr -> I */
+	s = getenv("ipaddr");
+	if (s != NULL) {
+		strcat(eprom, "I=");
+		ip_ml300((uchar *)s, (uchar *)temp);
+		strcat(eprom, temp);
+		strcat(eprom, ff);
+	}
+
+	/* serverip -> S */
+	s = getenv("serverip");
+	if (s != NULL) {
+		strcat(eprom, "S=");
+		ip_ml300((uchar *)s, (uchar *)temp);
+		strcat(eprom, temp);
+		strcat(eprom, ff);
+	}
+
+	/* bootargs -> A */
+	s = getenv("bootargs");
+	if (s != NULL) {
+		strcat(eprom, "A=");
+		strcat(eprom, s);
+		strcat(eprom, ff);
+	}
+
+	/* bootfile -> F */
+	s = getenv("bootfile");
+	if (s != NULL) {
+		strcat(eprom, "F=");
+		strcat(eprom, s);
+		strcat(eprom, ff);
+	}
+
+	/* bootcmd -> M */
+	s = getenv("bootcmd");
+	if (s != NULL) {
+		strcat(eprom, "M=");
+		strcat(eprom, s);
+		strcat(eprom, ff);
+	}
+
+	len = strlen(eprom);	/* find env length without crc */
+	change_null((uchar *)eprom);	/* change 0xff to 0x00 */
+
+	/* update EEPROM env values if there is enough space */
+	if (update_crc(len, (uchar *)eprom) == 0)
+		send(CFG_ENV_OFFSET, (uchar *)eprom, len + 6);
+}
+
+/************************************************************************
+ * U-boot call for EEPROM read associated activities.
+ */
+int
+i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+
+	if (envStep == 0) {
+		/* first read call is for crc */
+		read_crc(buffer, len);
+		++envStep;
+		return 0;
+	} else if (envStep == 1) {
+		/* then read out EEPROM content for runtime u-boot CRC calculation */
+		receive(addr, buffer, len);
+
+		if (addr + len - CFG_ENV_OFFSET == CFG_ENV_SIZE)
+			/* end of runtime crc read */
+			++envStep;
+		return 0;
+	}
+
+	if (len < 2) {
+		/* when call getenv_r */
+		receive(addr, buffer, len);
+	} else if (addr + len < CFG_ENV_OFFSET + CFG_ENV_SIZE) {
+		/* calling env_relocate(), but don't read out
+		   crc value from EEPROM */
+		receive(addr, buffer + 4, len);
+	} else {
+		receive(addr, buffer + 4, len - 4);
+	}
+
+	return 0;
+
+}
+
+/************************************************************************
+ * U-boot call for EEPROM write acativities.
+ */
+int
+i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
+{
+	/* save env on last page write called by u-boot */
+	if (addr + len >= CFG_ENV_OFFSET + CFG_ENV_SIZE)
+		save_env();
+
+	return 0;
+}
+
+/************************************************************************
+ * Dummy function.
+ */
+int
+i2c_probe(uchar chip)
+{
+	return 1;
+}
+
+#endif
diff --git a/board/xilinx/xilinx_iic/xiic_l.c b/board/xilinx/xilinx_iic/xiic_l.c
new file mode 100755
index 0000000..6b78163
--- /dev/null
+++ b/board/xilinx/xilinx_iic/xiic_l.c
@@ -0,0 +1,484 @@
+/* $Id: xiic_l.c,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
+/******************************************************************************
+*
+*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*	FOR A PARTICULAR PURPOSE.
+*
+*	(c) Copyright 2002 Xilinx Inc.
+*	All rights reserved.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiic_l.c
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- --- -------  -----------------------------------------------
+* 1.01b jhl 5/13/02  First release
+* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup of the
+*		     interrupt status mask was not being done in the loop such
+*		     that a read would sometimes fail on the last byte because
+*		     the transmit error which should have been ignored was
+*		     being used.  This would leave an extra byte in the FIFO
+*		     and the bus throttled such that the next operation would
+*		     also fail.	 Also updated the receive function to not
+*		     disable the device after the last byte until after the
+*		     bus transitions to not busy which is more consistent
+*		     with the expected behavior.
+* 1.01c ecm 12/05/02 new rev
+* </pre>
+*
+****************************************************************************/
+
+/***************************** Include Files *******************************/
+
+#include "xbasic_types.h"
+#include "xio.h"
+#include "xipif_v1_23_b.h"
+#include "xiic_l.h"
+
+/************************** Constant Definitions ***************************/
+
+/**************************** Type Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *******************/
+
+
+/******************************************************************************
+*
+* This macro clears the specified interrupt in the IPIF interrupt status
+* register.  It is non-destructive in that the register is read and only the
+* interrupt specified is cleared.  Clearing an interrupt acknowledges it.
+*
+* @param    BaseAddress contains the IPIF registers base address.
+*
+* @param    InterruptMask contains the interrupts to be disabled
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* Signature: void XIic_mClearIisr(u32 BaseAddress,
+*				  u32 InterruptMask);
+*
+******************************************************************************/
+#define XIic_mClearIisr(BaseAddress, InterruptMask)		    \
+    XIIF_V123B_WRITE_IISR((BaseAddress),			    \
+	XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask))
+
+/******************************************************************************
+*
+* This macro sends the address for a 7 bit address during both read and write
+* operations. It takes care of the details to format the address correctly.
+* This macro is designed to be called internally to the drivers.
+*
+* @param    SlaveAddress contains the address of the slave to send to.
+*
+* @param    Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
+*
+* @return
+*
+* None.
+*
+* @note
+*
+* Signature: void XIic_mSend7BitAddr(u16 SlaveAddress, u8 Operation);
+*
+******************************************************************************/
+#define XIic_mSend7BitAddress(BaseAddress, SlaveAddress, Operation)	    \
+{									    \
+    u8 LocalAddr = (u8)(SlaveAddress << 1);			    \
+    LocalAddr = (LocalAddr & 0xFE) | (Operation);			    \
+    XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr);		    \
+}
+
+/************************** Function Prototypes ****************************/
+
+static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr,
+			  unsigned ByteCount);
+static unsigned SendData (u32 BaseAddress, u8 * BufferPtr,
+			  unsigned ByteCount);
+
+/************************** Variable Definitions **************************/
+
+
+/****************************************************************************/
+/**
+* Receive data as a master on the IIC bus.  This function receives the data
+* using polled I/O and blocks until the data has been received.	 It only
+* supports 7 bit addressing and non-repeated start modes of operation.	The
+* user is responsible for ensuring the bus is not busy if multiple masters
+* are present on the bus.
+*
+* @param    BaseAddress contains the base address of the IIC device.
+* @param    Address contains the 7 bit IIC address of the device to send the
+*	    specified data to.
+* @param    BufferPtr points to the data to be sent.
+* @param    ByteCount is the number of bytes to be sent.
+*
+* @return
+*
+* The number of bytes received.
+*
+* @note
+*
+* None
+*
+******************************************************************************/
+unsigned XIic_Recv (u32 BaseAddress, u8 Address,
+		    u8 * BufferPtr, unsigned ByteCount)
+{
+	u8 CntlReg;
+	unsigned RemainingByteCount;
+
+	/* Tx error is enabled incase the address (7 or 10) has no device to answer
+	 * with Ack. When only one byte of data, must set NO ACK before address goes
+	 * out therefore Tx error must not be enabled as it will go off immediately
+	 * and the Rx full interrupt will be checked.  If full, then the one byte
+	 * was received and the Tx error will be disabled without sending an error
+	 * callback msg.
+	 */
+	XIic_mClearIisr (BaseAddress,
+			 XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK |
+			 XIIC_INTR_ARB_LOST_MASK);
+
+	/* Set receive FIFO occupancy depth for 1 byte (zero based)
+	 */
+	XIo_Out8 (BaseAddress + XIIC_RFD_REG_OFFSET, 0);
+
+	/* 7 bit slave address, send the address for a read operation
+	 * and set the state to indicate the address has been sent
+	 */
+	XIic_mSend7BitAddress (BaseAddress, Address, XIIC_READ_OPERATION);
+
+	/* MSMS gets set after putting data in FIFO. Start the master receive
+	 * operation by setting CR Bits MSMS to Master, if the buffer is only one
+	 * byte, then it should not be acknowledged to indicate the end of data
+	 */
+	CntlReg = XIIC_CR_MSMS_MASK | XIIC_CR_ENABLE_DEVICE_MASK;
+	if (ByteCount == 1) {
+		CntlReg |= XIIC_CR_NO_ACK_MASK;
+	}
+
+	/* Write out the control register to start receiving data and call the
+	 * function to receive each byte into the buffer
+	 */
+	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, CntlReg);
+
+	/* Clear the latched interrupt status for the bus not busy bit which must
+	 * be done while the bus is busy
+	 */
+	XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
+
+	/* Try to receive the data from the IIC bus */
+
+	RemainingByteCount = RecvData (BaseAddress, BufferPtr, ByteCount);
+	/*
+	 * The receive is complete, disable the IIC device and return the number of
+	 * bytes that was received
+	 */
+	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
+
+	/* Return the number of bytes that was received */
+
+	return ByteCount - RemainingByteCount;
+}
+
+/******************************************************************************
+*
+* Receive the specified data from the device that has been previously addressed
+* on the IIC bus.  This function assumes that the 7 bit address has been sent
+* and it should wait for the transmit of the address to complete.
+*
+* @param    BaseAddress contains the base address of the IIC device.
+* @param    BufferPtr points to the buffer to hold the data that is received.
+* @param    ByteCount is the number of bytes to be received.
+*
+* @return
+*
+* The number of bytes remaining to be received.
+*
+* @note
+*
+* This function does not take advantage of the receive FIFO because it is
+* designed for minimal code space and complexity.  It contains loops that
+* that could cause the function not to return if the hardware is not working.
+*
+* This function assumes that the calling function will disable the IIC device
+* after this function returns.
+*
+******************************************************************************/
+static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
+{
+	u8 CntlReg;
+	u32 IntrStatusMask;
+	u32 IntrStatus;
+
+	/* Attempt to receive the specified number of bytes on the IIC bus */
+
+	while (ByteCount > 0) {
+		/* Setup the mask to use for checking errors because when receiving one
+		 * byte OR the last byte of a multibyte message an error naturally
+		 * occurs when the no ack is done to tell the slave the last byte
+		 */
+		if (ByteCount == 1) {
+			IntrStatusMask =
+				XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK;
+		} else {
+			IntrStatusMask =
+				XIIC_INTR_ARB_LOST_MASK |
+				XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK;
+		}
+
+		/* Wait for the previous transmit and the 1st receive to complete
+		 * by checking the interrupt status register of the IPIF
+		 */
+		while (1) {
+			IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
+			if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
+				break;
+			}
+			/* Check the transmit error after the receive full because when
+			 * sending only one byte transmit error will occur because of the
+			 * no ack to indicate the end of the data
+			 */
+			if (IntrStatus & IntrStatusMask) {
+				return ByteCount;
+			}
+		}
+
+		CntlReg = XIo_In8 (BaseAddress + XIIC_CR_REG_OFFSET);
+
+		/* Special conditions exist for the last two bytes so check for them
+		 * Note that the control register must be setup for these conditions
+		 * before the data byte which was already received is read from the
+		 * receive FIFO (while the bus is throttled
+		 */
+		if (ByteCount == 1) {
+			/* For the last data byte, it has already been read and no ack
+			 * has been done, so clear MSMS while leaving the device enabled
+			 * so it can get off the IIC bus appropriately with a stop.
+			 */
+			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
+				  XIIC_CR_ENABLE_DEVICE_MASK);
+		}
+
+		/* Before the last byte is received, set NOACK to tell the slave IIC
+		 * device that it is the end, this must be done before reading the byte
+		 * from the FIFO
+		 */
+		if (ByteCount == 2) {
+			/* Write control reg with NO ACK allowing last byte to
+			 * have the No ack set to indicate to slave last byte read.
+			 */
+			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
+				  CntlReg | XIIC_CR_NO_ACK_MASK);
+		}
+
+		/* Read in data from the FIFO and unthrottle the bus such that the
+		 * next byte is read from the IIC bus
+		 */
+		*BufferPtr++ = XIo_In8 (BaseAddress + XIIC_DRR_REG_OFFSET);
+
+		/* Clear the latched interrupt status so that it will be updated with
+		 * the new state when it changes, this must be done after the receive
+		 * register is read
+		 */
+		XIic_mClearIisr (BaseAddress, XIIC_INTR_RX_FULL_MASK |
+				 XIIC_INTR_TX_ERROR_MASK |
+				 XIIC_INTR_ARB_LOST_MASK);
+		ByteCount--;
+	}
+
+	/* Wait for the bus to transition to not busy before returning, the IIC
+	 * device cannot be disabled until this occurs.	 It should transition as
+	 * the MSMS bit of the control register was cleared before the last byte
+	 * was read from the FIFO.
+	 */
+	while (1) {
+		if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
+			break;
+		}
+	}
+
+	return ByteCount;
+}
+
+/****************************************************************************/
+/**
+* Send data as a master on the IIC bus.	 This function sends the data
+* using polled I/O and blocks until the data has been sent.  It only supports
+* 7 bit addressing and non-repeated start modes of operation.  The user is
+* responsible for ensuring the bus is not busy if multiple masters are present
+* on the bus.
+*
+* @param    BaseAddress contains the base address of the IIC device.
+* @param    Address contains the 7 bit IIC address of the device to send the
+*	    specified data to.
+* @param    BufferPtr points to the data to be sent.
+* @param    ByteCount is the number of bytes to be sent.
+*
+* @return
+*
+* The number of bytes sent.
+*
+* @note
+*
+* None
+*
+******************************************************************************/
+unsigned XIic_Send (u32 BaseAddress, u8 Address,
+		    u8 * BufferPtr, unsigned ByteCount)
+{
+	unsigned RemainingByteCount;
+
+	/* Put the address into the FIFO to be sent and indicate that the operation
+	 * to be performed on the bus is a write operation
+	 */
+	XIic_mSend7BitAddress (BaseAddress, Address, XIIC_WRITE_OPERATION);
+
+	/* Clear the latched interrupt status so that it will be updated with the
+	 * new state when it changes, this must be done after the address is put
+	 * in the FIFO
+	 */
+	XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
+			 XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK);
+
+	/* MSMS must be set after putting data into transmit FIFO, indicate the
+	 * direction is transmit, this device is master and enable the IIC device
+	 */
+	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
+		  XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK |
+		  XIIC_CR_ENABLE_DEVICE_MASK);
+
+	/* Clear the latched interrupt
+	 * status for the bus not busy bit which must be done while the bus is busy
+	 */
+	XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
+
+	/* Send the specified data to the device on the IIC bus specified by the
+	 * the address
+	 */
+	RemainingByteCount = SendData (BaseAddress, BufferPtr, ByteCount);
+
+	/*
+	 * The send is complete, disable the IIC device and return the number of
+	 * bytes that was sent
+	 */
+	XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
+
+	return ByteCount - RemainingByteCount;
+}
+
+/******************************************************************************
+*
+* Send the specified buffer to the device that has been previously addressed
+* on the IIC bus.  This function assumes that the 7 bit address has been sent
+* and it should wait for the transmit of the address to complete.
+*
+* @param    BaseAddress contains the base address of the IIC device.
+* @param    BufferPtr points to the data to be sent.
+* @param    ByteCount is the number of bytes to be sent.
+*
+* @return
+*
+* The number of bytes remaining to be sent.
+*
+* @note
+*
+* This function does not take advantage of the transmit FIFO because it is
+* designed for minimal code space and complexity.  It contains loops that
+* that could cause the function not to return if the hardware is not working.
+*
+******************************************************************************/
+static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
+{
+	u32 IntrStatus;
+
+	/* Send the specified number of bytes in the specified buffer by polling
+	 * the device registers and blocking until complete
+	 */
+	while (ByteCount > 0) {
+		/* Wait for the transmit to be empty before sending any more data
+		 * by polling the interrupt status register
+		 */
+		while (1) {
+			IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
+
+			if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
+					  XIIC_INTR_ARB_LOST_MASK |
+					  XIIC_INTR_BNB_MASK)) {
+				return ByteCount;
+			}
+
+			if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
+				break;
+			}
+		}
+		/* If there is more than one byte to send then put the next byte to send
+		 * into the transmit FIFO
+		 */
+		if (ByteCount > 1) {
+			XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
+				  *BufferPtr++);
+		} else {
+			/* Set the stop condition before sending the last byte of data so that
+			 * the stop condition will be generated immediately following the data
+			 * This is done by clearing the MSMS bit in the control register.
+			 */
+			XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
+				  XIIC_CR_ENABLE_DEVICE_MASK |
+				  XIIC_CR_DIR_IS_TX_MASK);
+
+			/* Put the last byte to send in the transmit FIFO */
+
+			XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
+				  *BufferPtr++);
+		}
+
+		/* Clear the latched interrupt status register and this must be done after
+		 * the transmit FIFO has been written to or it won't clear
+		 */
+		XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK);
+
+		/* Update the byte count to reflect the byte sent and clear the latched
+		 * interrupt status so it will be updated for the new state
+		 */
+		ByteCount--;
+	}
+
+	/* Wait for the bus to transition to not busy before returning, the IIC
+	 * device cannot be disabled until this occurs.
+	 * Note that this is different from a receive operation because the stop
+	 * condition causes the bus to go not busy.
+	 */
+	while (1) {
+		if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
+			break;
+		}
+	}
+
+	return ByteCount;
+}
diff --git a/board/xilinx/xilinx_iic/xiic_l.h b/board/xilinx/xilinx_iic/xiic_l.h
new file mode 100755
index 0000000..a2c4c49
--- /dev/null
+++ b/board/xilinx/xilinx_iic/xiic_l.h
@@ -0,0 +1,150 @@
+/* $Id: xiic_l.h,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
+/*****************************************************************************
+*
+*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*	FOR A PARTICULAR PURPOSE.
+*
+*	(c) Copyright 2002 Xilinx Inc.
+*	All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xiic_l.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  High-level driver functions
+* are defined in xiic.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b jhl  05/07/02 First release
+* 1.01c ecm  12/05/02 new rev
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XIIC_L_H /* prevent circular inclusions */
+#define XIIC_L_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xbasic_types.h"
+
+/************************** Constant Definitions ****************************/
+
+#define XIIC_MSB_OFFSET		       3
+
+#define XIIC_REG_OFFSET 0x100 + XIIC_MSB_OFFSET
+
+/*
+ * Register offsets in bytes from RegisterBase. Three is added to the
+ * base offset to access LSB (IBM style) of the word
+ */
+#define XIIC_CR_REG_OFFSET   0x00+XIIC_REG_OFFSET   /* Control Register	  */
+#define XIIC_SR_REG_OFFSET   0x04+XIIC_REG_OFFSET   /* Status Register	  */
+#define XIIC_DTR_REG_OFFSET  0x08+XIIC_REG_OFFSET   /* Data Tx Register	  */
+#define XIIC_DRR_REG_OFFSET  0x0C+XIIC_REG_OFFSET   /* Data Rx Register	  */
+#define XIIC_ADR_REG_OFFSET  0x10+XIIC_REG_OFFSET   /* Address Register	  */
+#define XIIC_TFO_REG_OFFSET  0x14+XIIC_REG_OFFSET   /* Tx FIFO Occupancy  */
+#define XIIC_RFO_REG_OFFSET  0x18+XIIC_REG_OFFSET   /* Rx FIFO Occupancy  */
+#define XIIC_TBA_REG_OFFSET  0x1C+XIIC_REG_OFFSET   /* 10 Bit Address reg */
+#define XIIC_RFD_REG_OFFSET  0x20+XIIC_REG_OFFSET   /* Rx FIFO Depth reg  */
+
+/* Control Register masks */
+
+#define XIIC_CR_ENABLE_DEVICE_MASK	  0x01	/* Device enable = 1	  */
+#define XIIC_CR_TX_FIFO_RESET_MASK	  0x02	/* Transmit FIFO reset=1  */
+#define XIIC_CR_MSMS_MASK		  0x04	/* Master starts Txing=1  */
+#define XIIC_CR_DIR_IS_TX_MASK		  0x08	/* Dir of tx. Txing=1	  */
+#define XIIC_CR_NO_ACK_MASK		  0x10	/* Tx Ack. NO ack = 1	  */
+#define XIIC_CR_REPEATED_START_MASK	  0x20	/* Repeated start = 1	  */
+#define XIIC_CR_GENERAL_CALL_MASK	  0x40	/* Gen Call enabled = 1	  */
+
+/* Status Register masks */
+
+#define XIIC_SR_GEN_CALL_MASK		  0x01	/* 1=a mstr issued a GC	  */
+#define XIIC_SR_ADDR_AS_SLAVE_MASK	  0x02	/* 1=when addr as slave	  */
+#define XIIC_SR_BUS_BUSY_MASK		  0x04	/* 1 = bus is busy	  */
+#define XIIC_SR_MSTR_RDING_SLAVE_MASK	  0x08	/* 1=Dir: mstr <-- slave  */
+#define XIIC_SR_TX_FIFO_FULL_MASK	  0x10	/* 1 = Tx FIFO full	  */
+#define XIIC_SR_RX_FIFO_FULL_MASK	  0x20	/* 1 = Rx FIFO full	  */
+#define XIIC_SR_RX_FIFO_EMPTY_MASK	  0x40	/* 1 = Rx FIFO empty	  */
+
+/* IPIF Interrupt Status Register masks	   Interrupt occurs when...	  */
+
+#define XIIC_INTR_ARB_LOST_MASK		  0x01	/* 1 = arbitration lost	  */
+#define XIIC_INTR_TX_ERROR_MASK		  0x02	/* 1=Tx error/msg complete*/
+#define XIIC_INTR_TX_EMPTY_MASK		  0x04	/* 1 = Tx FIFO/reg empty  */
+#define XIIC_INTR_RX_FULL_MASK		  0x08	/* 1=Rx FIFO/reg=OCY level*/
+#define XIIC_INTR_BNB_MASK		  0x10	/* 1 = Bus not busy	  */
+#define XIIC_INTR_AAS_MASK		  0x20	/* 1 = when addr as slave */
+#define XIIC_INTR_NAAS_MASK		  0x40	/* 1 = not addr as slave  */
+#define XIIC_INTR_TX_HALF_MASK		  0x80	/* 1 = TX FIFO half empty */
+
+/* IPIF Device Interrupt Register masks */
+
+#define XIIC_IPIF_IIC_MASK	    0x00000004UL    /* 1=inter enabled */
+#define XIIC_IPIF_ERROR_MASK	    0x00000001UL    /* 1=inter enabled */
+#define XIIC_IPIF_INTER_ENABLE_MASK  (XIIC_IPIF_IIC_MASK |  \
+				      XIIC_IPIF_ERROR_MASK)
+
+#define XIIC_TX_ADDR_SENT	      0x00
+#define XIIC_TX_ADDR_MSTR_RECV_MASK   0x02
+
+/* The following constants specify the depth of the FIFOs */
+
+#define IIC_RX_FIFO_DEPTH	  16   /* Rx fifo capacity		 */
+#define IIC_TX_FIFO_DEPTH	  16   /* Tx fifo capacity		 */
+
+/* The following constants specify groups of interrupts that are typically
+ * enabled or disables at the same time
+ */
+#define XIIC_TX_INTERRUPTS					    \
+	    (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK |    \
+	     XIIC_INTR_TX_HALF_MASK)
+
+#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
+
+/* The following constants are used with the following macros to specify the
+ * operation, a read or write operation.
+ */
+#define XIIC_READ_OPERATION  1
+#define XIIC_WRITE_OPERATION 0
+
+/* The following constants are used with the transmit FIFO fill function to
+ * specify the role which the IIC device is acting as, a master or a slave.
+ */
+#define XIIC_MASTER_ROLE     1
+#define XIIC_SLAVE_ROLE	     0
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+unsigned XIic_Recv(u32 BaseAddress, u8 Address,
+		   u8 *BufferPtr, unsigned ByteCount);
+
+unsigned XIic_Send(u32 BaseAddress, u8 Address,
+		   u8 *BufferPtr, unsigned ByteCount);
+
+#endif		  /* end of protection macro */
diff --git a/board/xm250/Makefile b/board/xm250/Makefile
new file mode 100755
index 0000000..1b0a3f0
--- /dev/null
+++ b/board/xm250/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= xm250.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/xm250/config.mk b/board/xm250/config.mk
new file mode 100755
index 0000000..8ce0c48
--- /dev/null
+++ b/board/xm250/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MicroSys XM250 board:
+#
+
+
+# This is the address where U-Boot lives in flash:
+#TEXT_BASE = 0
+
+# FIXME: armboot does only work correctly when being compiled
+# for the addresses _after_ relocation to RAM!! Otherwhise the
+# .bss segment is assumed in flash...
+TEXT_BASE = 0xA3F80000
diff --git a/board/xm250/flash.c b/board/xm250/flash.c
new file mode 100755
index 0000000..aab47a0
--- /dev/null
+++ b/board/xm250/flash.c
@@ -0,0 +1,536 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+/* Intel-compatible flash ID */
+#define INTEL_COMPAT  0x00890089
+#define INTEL_ALT     0x00B000B0
+
+/* Intel-compatible flash commands */
+#define INTEL_PROGRAM 0x00100010
+#define INTEL_ERASE   0x00200020
+#define INTEL_CLEAR   0x00500050
+#define INTEL_LOCKBIT 0x00600060
+#define INTEL_PROTECT 0x00010001
+#define INTEL_STATUS  0x00700070
+#define INTEL_READID  0x00900090
+#define INTEL_CONFIRM 0x00D000D0
+#define INTEL_RESET   0xFFFFFFFF
+
+/* Intel-compatible flash status bits */
+#define INTEL_FINISHED 0x00800080
+#define INTEL_OK       0x00800080
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 32 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Set/Clear sector's lock bit, returns:
+ * 0 - OK
+ * 1 - Error (timeout, voltage problems, etc.)
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int i;
+	int rc = 0;
+	vu_long *addr = (vu_long *)(info->start[sector]);
+	int flag = disable_interrupts();
+
+	*addr = INTEL_CLEAR;	/* Clear status register */
+	if (prot) {			/* Set sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+		*addr = INTEL_PROTECT;	/* set */
+	}
+	else {				/* Clear sector lock bit */
+		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
+		*addr = INTEL_CONFIRM;	/* clear */
+	}
+
+	reset_timer_masked ();
+
+	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
+		if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) {
+			printf("Flash lock bit operation timed out\n");
+			rc = 1;
+			break;
+		}
+	}
+
+	if (*addr != INTEL_OK) {
+		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
+		       (uint)addr, (uint)*addr);
+		rc = 1;
+	}
+
+	if (!rc)
+		info->protect[sector] = prot;
+
+	/*
+	 * Clear lock bit command clears all sectors lock bits, so
+	 * we have to restore lock bits of protected sectors.
+	 */
+	if (!prot)
+	{
+		for (i = 0; i < info->sector_count; i++)
+		{
+			if (info->protect[i])
+			{
+				reset_timer_masked ();
+				addr = (vu_long *)(info->start[i]);
+				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
+				*addr = INTEL_PROTECT;	/* set */
+				while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
+				{
+					if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT)
+					{
+						printf("Flash lock bit operation timed out\n");
+						rc = 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+
+	if (flag)
+		enable_interrupts();
+
+	*addr = INTEL_RESET;		/* Reset to read array mode */
+
+	return rc;
+}
diff --git a/board/xm250/lowlevel_init.S b/board/xm250/lowlevel_init.S
new file mode 100755
index 0000000..2ebd395
--- /dev/null
+++ b/board/xm250/lowlevel_init.S
@@ -0,0 +1,519 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+	.macro CPWAIT reg
+	mrc	p15,0,\reg,c2,c0,0
+	mov	\reg,\reg
+	sub	pc,pc,#4
+	.endm
+/*
+	.macro SET_LED val
+	ldr	r6, =CRADLE_LED_CLR_REG
+	ldr	r7, =0
+	str	r7, [r6]
+	ldr	r6, =CRADLE_LED_SET_REG
+	ldr	r7, =\val
+	str	r7, [r6]
+	.endm
+*/
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov	r10, lr
+
+	/* Set up GPIO pins first */
+
+	ldr	r0,   =GPSR0
+	ldr	r1,   =CFG_GPSR0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPSR1
+	ldr	r1,   =CFG_GPSR1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPSR2
+	ldr	r1,   =CFG_GPSR2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPCR0
+	ldr	r1,   =CFG_GPCR0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPCR1
+	ldr	r1,   =CFG_GPCR1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPCR2
+	ldr	r1,   =CFG_GPCR2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GRER0
+	ldr	r1,   =CFG_GRER0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GRER1
+	ldr	r1,   =CFG_GRER1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GRER2
+	ldr	r1,   =CFG_GRER2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GFER0
+	ldr	r1,   =CFG_GFER0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GFER1
+	ldr	r1,   =CFG_GFER1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GFER2
+	ldr	r1,   =CFG_GFER2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPDR0
+	ldr	r1,   =CFG_GPDR0_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPDR1
+	ldr	r1,   =CFG_GPDR1_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GPDR2
+	ldr	r1,   =CFG_GPDR2_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR0_L
+	ldr	r1,   =CFG_GAFR0_L_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR0_U
+	ldr	r1,   =CFG_GAFR0_U_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR1_L
+	ldr	r1,   =CFG_GAFR1_L_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR1_U
+	ldr	r1,   =CFG_GAFR1_U_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR2_L
+	ldr	r1,   =CFG_GAFR2_L_VAL
+	str	r1,   [r0]
+
+	ldr	r0,   =GAFR2_U
+	ldr	r1,   =CFG_GAFR2_U_VAL
+	str	r1,   [r0]
+
+	/* enable GPIO pins */
+	ldr	r0,   =PSSR
+	ldr	r1,   =CFG_PSSR_VAL
+	str	r1,   [r0]
+
+	/* SET_LED 1 */
+
+	ldr	r3, =MSC1		/* low - bank 2 Lubbock Registers / SRAM */
+	ldr	r2, =CFG_MSC1_VAL	/* high - bank 3 Ethernet Controller */
+	str	r2, [r3]		/* need to set MSC1 before trying to write to the HEX LEDs */
+	ldr	r2, [r3]		/* need to read it back to make sure the value latches (see MSC section of manual) */
+
+
+/*********************************************************************
+ *  Initlialize Memory Controller
+ *
+ *  See PXA250 Operating System Developer's Guide
+ *
+ *  pause for 200 uSecs- allow internal clocks to settle
+ *  *Note: only need this if hard reset... doing it anyway for now
+ */
+
+	@ Step 1
+	@ ---- Wait 200 usec
+	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+	/* SET_LED 2 */
+
+mem_init:
+	@ get memory controller base address
+	ldr	r1,  =MEMC_BASE
+
+
+@****************************************************************************
+@  Step 2
+@
+
+	@ Step 2a
+	@ write msc0, read back to ensure data latches
+	@
+	ldr	r2,   =CFG_MSC0_VAL
+	str	r2,   [r1, #MSC0_OFFSET]
+	ldr	r2,   [r1, #MSC0_OFFSET]
+
+	@ write msc1
+	ldr	r2,  =CFG_MSC1_VAL
+	str	r2,  [r1, #MSC1_OFFSET]
+	ldr	r2,  [r1, #MSC1_OFFSET]
+
+	@ write msc2
+	ldr	r2,  =CFG_MSC2_VAL
+	str	r2,  [r1, #MSC2_OFFSET]
+	ldr	r2,  [r1, #MSC2_OFFSET]
+
+	@ Step 2b
+	@ write mecr
+	ldr	r2,  =CFG_MECR_VAL
+	str	r2,  [r1, #MECR_OFFSET]
+
+	@ write mcmem0
+	ldr	r2,  =CFG_MCMEM0_VAL
+	str	r2,  [r1, #MCMEM0_OFFSET]
+
+	@ write mcmem1
+	ldr	r2,  =CFG_MCMEM1_VAL
+	str	r2,  [r1, #MCMEM1_OFFSET]
+
+	@ write mcatt0
+	ldr	r2,  =CFG_MCATT0_VAL
+	str	r2,  [r1, #MCATT0_OFFSET]
+
+	@ write mcatt1
+	ldr	r2,  =CFG_MCATT1_VAL
+	str	r2,  [r1, #MCATT1_OFFSET]
+
+	@ write mcio0
+	ldr	r2,  =CFG_MCIO0_VAL
+	str	r2,  [r1, #MCIO0_OFFSET]
+
+	@ write mcio1
+	ldr	r2,  =CFG_MCIO1_VAL
+	str	r2,  [r1, #MCIO1_OFFSET]
+
+	/*SET_LED 3 */
+
+	@ Step 2c
+	@ fly-by-dma is defeatured on this part
+	@ write flycnfg
+	@ldr	r2,  =CFG_FLYCNFG_VAL
+	@str	r2,  [r1, #FLYCNFG_OFFSET]
+
+/* FIXME Does this sequence really make sense */
+#ifdef REDBOOT_WAY
+	@ Step 2d
+	@ get the mdrefr settings
+	ldr	r3,  =CFG_MDREFR_VAL
+
+	@ extract DRI field (we need a valid DRI field)
+	@
+	ldr	r2,  =0xFFF
+
+	@ valid DRI field in r3
+	@
+	and	r3,  r3,  r2
+
+	@ get the reset state of MDREFR
+	@
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	@ clear the DRI field
+	@
+	bic	r4,  r4,  r2
+
+	@ insert the valid DRI field loaded above
+	@
+	orr	r4,  r4,  r3
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@ *Note: preserve the mdrefr value in r4 *
+
+	/*SET_LED 4 */
+
+@****************************************************************************
+@  Step 3
+@
+@ NO SRAM
+
+	mov   pc, r10
+
+
+@****************************************************************************
+@  Step 4
+@
+
+	@ Assumes previous mdrefr value in r4, if not then read current mdrefr
+
+	@ clear the free-running clock bits
+	@ (clear K0Free, K1Free, K2Free
+	@
+	bic	r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
+
+	@ set K0RUN for CPLD clock
+	@
+	orr	r4,  r4, #0x00002000
+
+	@ set K1RUN if bank 0 installed
+	@
+	orr	r4,  r4, #0x00010000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	@ deassert SLFRSH
+	@
+	bic	r4,  r4,  #0x00400000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@ assert E1PIN
+	@
+	orr	r4,  r4,  #0x00008000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+	nop
+	nop
+#else
+	@ Step 2d
+	@ get the mdrefr settings
+	ldr	r4,  =CFG_MDREFR_VAL
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@  Step 4
+
+	@ set K0RUN for FLASH clock
+	@
+	orr	r4,  r4, #0x00002000
+
+	@ set K1RUN for bank DRAM 0
+	@
+	orr	r4,  r4, #0x00010000
+
+	@ set K2RUN for bank PLD
+	@
+	orr	r4,  r4, #0x00040000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	@ deassert SLFRSH
+	@
+	bic	r4,  r4,  #0x00400000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+
+	@ assert E1PIN
+	@
+	orr	r4,  r4,  #0x00008000
+
+	@ write back mdrefr
+	@
+	str	r4,  [r1, #MDREFR_OFFSET]
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+	nop
+	nop
+#endif
+
+	@ Step 4d
+	@ fetch platform value of mdcnfg
+	@
+	ldr	r2,  =CFG_MDCNFG_VAL
+
+	@ disable all sdram banks
+	@
+	bic	r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
+	bic	r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+
+	@ program banks 0/1 for bus width
+	@
+	bic	r2,  r2,  #MDCNFG_DWID0		@0=32-bit
+
+	@ write initial value of mdcnfg, w/o enabling sdram banks
+	@
+	str	r2,  [r1, #MDCNFG_OFFSET]
+
+	@ Step 4e
+	@ pause for 200 uSecs
+	@
+	ldr	r3, =OSCR	@ reset the OS Timer Count to zero
+	mov	r2, #0
+	str	r2, [r3]
+	ldr	r4, =0x300	@ really 0x2E1 is about 200usec, so 0x300 should be plenty
+1:
+	ldr	r2, [r3]
+	cmp	r4, r2
+	bgt	1b
+
+	/*SET_LED 5 */
+
+	/* Why is this here??? */
+	mov	r0, #0x78		@turn everything off
+	mcr	p15, 0, r0, c1, c0, 0	@(caches off, MMU off, etc.)
+
+	@ Step 4f
+	@ Access memory *not yet enabled* for CBR refresh cycles (8)
+	@ - CBR is generated for all banks
+
+	ldr	r2, =CFG_DRAM_BASE
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+	str	r2, [r2]
+
+	@ Step 4g
+	@get memory controller base address
+	@
+	ldr	r1,  =MEMC_BASE
+
+	@fetch current mdcnfg value
+	@
+	ldr	r3,  [r1, #MDCNFG_OFFSET]
+
+	@enable sdram bank 0 if installed (must do for any populated bank)
+	@
+	orr	r3,  r3,  #MDCNFG_DE0
+
+	@write back mdcnfg, enabling the sdram bank(s)
+	@
+	str	r3,  [r1, #MDCNFG_OFFSET]
+
+	@ Step 4h
+	@ write mdmrs
+	@
+	ldr	r2,  =CFG_MDMRS_VAL
+	str	r2,  [r1, #MDMRS_OFFSET]
+
+	@ Done Memory Init
+
+	/*SET_LED 6 */
+
+	@********************************************************************
+	@ Disable (mask) all interrupts at the interrupt controller
+	@
+
+	@ clear the interrupt level register (use IRQ, not FIQ)
+	@
+	mov	r1, #0
+	ldr	r2,  =ICLR
+	str	r1,  [r2]
+
+	@ Set interrupt mask register
+	@
+	ldr	r1,  =CFG_ICMR_VAL
+	ldr	r2,  =ICMR
+	str	r1,  [r2]
+
+	@ ********************************************************************
+	@ Disable the peripheral clocks, and set the core clock
+	@
+
+	@ Turn Off ALL on-chip peripheral clocks for re-configuration
+	@
+	ldr	r1,  =CKEN
+	mov	r2,  #0
+	str	r2,  [r1]
+
+	@ set core clocks
+	@
+	ldr	r2,  =CFG_CCCR_VAL
+	ldr	r1,  =CCCR
+	str	r2,  [r1]
+
+#ifdef ENABLE32KHZ
+	@ enable the 32Khz oscillator for RTC and PowerManager
+	@
+	ldr	r1,  =OSCC
+	mov	r2,  #OSCC_OON
+	str	r2,  [r1]
+
+	@ NOTE:	 spin here until OSCC.OOK get set,
+	@	 meaning the PLL has settled.
+	@
+60:
+	ldr	r2, [r1]
+	ands	r2, r2, #1
+	beq	60b
+#endif
+
+	@ Turn on needed clocks
+	@
+	ldr	r1,  =CKEN
+	ldr	r2,  =CFG_CKEN_VAL
+	str	r2,  [r1]
+
+	/*SET_LED 7 */
+
+/* Is this needed???? */
+#define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0	/* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0	/* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0	/* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0	/* dcsr */
+
+#endif
+
+	/*SET_LED 8 */
+
+	mov	pc, r10
+
+@ End lowlevel_init
diff --git a/board/xm250/u-boot.lds b/board/xm250/u-boot.lds
new file mode 100755
index 0000000..db83875
--- /dev/null
+++ b/board/xm250/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c
new file mode 100755
index 0000000..ef5e9da
--- /dev/null
+++ b/board/xm250/xm250.c
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+/* local prototypes */
+
+inline void sleep (int i);
+
+inline void
+/**********************************************************/
+sleep (int i)
+/**********************************************************/
+{
+	while (i--) {
+		udelay (1000000);
+	}
+}
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+/**********************************************************/
+board_post_init (void)
+/**********************************************************/
+{
+	return (0);
+}
+
+int
+/**********************************************************/
+board_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	/* arch number of MicroSys XM250 */
+	gd->bd->bi_arch_number = MACH_TYPE_XM250;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int
+/**********************************************************/
+dram_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
+
+	return (0);
+}
diff --git a/board/xpedite1k/Makefile b/board/xpedite1k/Makefile
new file mode 100755
index 0000000..c5c0915
--- /dev/null
+++ b/board/xpedite1k/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+OBJS +=flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/xpedite1k/config.mk b/board/xpedite1k/config.mk
new file mode 100755
index 0000000..e42b273
--- /dev/null
+++ b/board/xpedite1k/config.mk
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2002-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# XES XPedite1000 PPC440GX
+#
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0x07FD0000
+else
+TEXT_BASE = 0xFFF80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/xpedite1k/flash.c b/board/xpedite1k/flash.c
new file mode 100755
index 0000000..ce5d4e1
--- /dev/null
+++ b/board/xpedite1k/flash.c
@@ -0,0 +1,607 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
+ * Add support for Am29F016D and dynamic switch setting.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Modified 4/5/2001
+ * Wait for completion of each sector erase command issued
+ * 4/5/2001
+ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
+ */
+
+/*
+ * Ported to XPedite1000, 1/2 mb boot flash only
+ * Travis B. Sawyer, <travis.sawyer@sandburst.com>
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+
+
+#undef DEBUG
+#ifdef DEBUG
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif /* DEBUG */
+
+#define BOOT_SMALL_FLASH	32		/* 00100000 */
+#define FLASH_ONBD_N		2		/* 00000010 */
+#define FLASH_SRAM_SEL		1		/* 00000001 */
+
+#define BOOT_SMALL_FLASH_VAL	4
+#define FLASH_ONBD_N_VAL	2
+#define FLASH_SRAM_SEL_VAL	1
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+	{0xfff80000},	/* 0:000: configuraton 3 */
+	{0xfff90000},	/* 1:001: configuraton 4 */
+	{0xfffa0000},	/* 2:010: configuraton 7 */
+	{0xfffb0000},	/* 3:011: configuraton 8 */
+	{0xfffc0000},	/* 4:100: configuraton 1 */
+	{0xfffd0000},	/* 5:101: configuraton 2 */
+	{0xfffe0000},	/* 6:110: configuraton 5 */
+	{0xffff0000}	/* 7:111: configuraton 6 */
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+
+
+#ifdef CONFIG_XPEDITE1K
+#define ADDR0		0x5555
+#define ADDR1		0x2aaa
+#define FLASH_WORD_SIZE unsigned char
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0) {
+			continue;
+		}
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size(
+			(vu_long *)flash_addr_table[index][i], &flash_info[i]);
+		flash_info[i].size = size_b[i];
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, size_b[i], size_b[i]<<20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMD016:	printf ("AM29F016D (16 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM040:	printf ("AM29F040 (512 Kbit, uniform sector size)\n");
+		break;
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	 /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		{
+			if (*flash++ != 0xffffffff)
+			{
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+			printf (" %08lX%s%s",
+				info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   "
+				);
+			}
+		printf ("\n");
+		return;
+	}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+
+	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr );
+
+	/* Write auto select command: read Manufacturer ID */
+	udelay(10000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+	udelay(1000);
+	addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+	udelay(1000);
+	addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
+	udelay(1000);
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[2];
+#else
+	value = addr2[0];
+#endif
+
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+#ifdef CONFIG_ADCIOP
+	value = addr2[0];			/* device ID		*/
+	debug ("\ndev_code=%x\n", value);
+#else
+	value = addr2[1];			/* device ID		*/
+#endif
+
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+	case (FLASH_WORD_SIZE)AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000; /* => 512 kb */
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+		    (info->flash_id  == FLASH_AM040) ||
+		    (info->flash_id  == FLASH_AMD016)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = addr2[4] & 1;
+#else
+		addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[2] & 1;
+#endif
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+#if 0 /* test-only */
+#ifdef CONFIG_ADCIOP
+		addr2 = (volatile unsigned char *)info->start[0];
+		addr2[ADDR0] = 0xAA;
+		addr2[ADDR1] = 0x55;
+		addr2[ADDR0] = 0xF0;  /* reset bank */
+#else
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+#endif
+#else /* test-only */
+		addr2 = (FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+#endif /* test-only */
+	}
+
+	return (info->size);
+}
+
+int wait_for_DQ7(flash_info_t *info, int sect)
+{
+	ulong start, now, last;
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]);
+
+	start = get_timer (0);
+	last  = start;
+	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {  /* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	int i;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+			addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
+			printf("Erasing sector %p\n", addr2);
+
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00500050;	 /* block erase */
+				for (i=0; i<50; i++)
+					udelay(1000);  /* wait 1 ms */
+			} else {
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
+				addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+				addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (FLASH_WORD_SIZE)0x00300030;	 /* sector erase */
+			}
+			l_sect = sect;
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+#if 0
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+	wait_for_DQ7(info, l_sect);
+
+DONE:
+#endif
+	/* reset to read mode */
+	addr = (FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
+	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile FLASH_WORD_SIZE *) dest) &
+	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+		return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts ();
+
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
+		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts ();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
diff --git a/board/xpedite1k/init.S b/board/xpedite1k/init.S
new file mode 100755
index 0000000..6cb20e4
--- /dev/null
+++ b/board/xpedite1k/init.S
@@ -0,0 +1,96 @@
+/*
+*  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbtab_end
diff --git a/board/xpedite1k/u-boot.lds b/board/xpedite1k/u-boot.lds
new file mode 100755
index 0000000..0f08637
--- /dev/null
+++ b/board/xpedite1k/u-boot.lds
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/xpedite1k/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/xpedite1k/u-boot.lds.debug b/board/xpedite1k/u-boot.lds.debug
new file mode 100755
index 0000000..5066326
--- /dev/null
+++ b/board/xpedite1k/u-boot.lds.debug
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/xpedite1k/init.o (.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+    lib_ppc/extable.o	(.text)
+    lib_generic/zlib.o		(.text)
+
+/*    common/environment.o(.text) */
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c
new file mode 100755
index 0000000..bb36c96
--- /dev/null
+++ b/board/xpedite1k/xpedite1k.c
@@ -0,0 +1,351 @@
+/*
+ *  Copyright (C) 2003 Travis B. Sawyer	 <travis.sawyer@sandburst.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+
+#define BOOT_SMALL_FLASH	32	/* 00100000 */
+#define FLASH_ONBD_N		2	/* 00000010 */
+#define FLASH_SRAM_SEL		1	/* 00000001 */
+
+long int fixed_sdram (void);
+
+int board_early_init_f(void)
+{
+	unsigned long sdrreg;
+	/* TBS:	 Setup the GPIO access for the user LEDs */
+	mfsdr(sdr_pfc0, sdrreg);
+	mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
+	out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
+	LED0_OFF();
+	LED1_OFF();
+	LED2_OFF();
+	LED3_OFF();
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+
+	/* set the bus controller */
+	mtebc (pb0ap, 0x04055200);	/* FLASH/SRAM */
+	mtebc (pb0cr, 0xfff18000);	/* BAS=0xfff 1MB R/W 8-bit */
+	mtebc (pb1ap, 0x04055200);	/* FLASH/SRAM */
+	mtebc (pb1cr, 0xfe098000);	/* BAS=0xff8 16MB R/W 8-bit */
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+	mtdcr (uic0er, 0x00000000);	/* disable all */
+	mtdcr (uic0cr, 0x00000003);	/* SMI & UIC1 crit are critical */
+	mtdcr (uic0pr, 0xfffffe00);	/* per ref-board manual */
+	mtdcr (uic0tr, 0x01c00000);	/* per ref-board manual */
+	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+	mtdcr (uic1er, 0x00000000);	/* disable all */
+	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic1pr, 0xffffc0ff);	/* per ref-board manual */
+	mtdcr (uic1tr, 0x00ff8000);	/* per ref-board manual */
+	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic1sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+	mtdcr (uic2er, 0x00000000);	/* disable all */
+	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
+	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
+	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
+	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr (uic2sr, 0xffffffff);	/* clear all */
+
+	mtdcr (uicb0sr, 0xfc000000); /* clear all */
+	mtdcr (uicb0er, 0x00000000); /* disable all */
+	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
+	mtdcr (uicb0pr, 0xfc000000); /* */
+	mtdcr (uicb0tr, 0x00000000); /* */
+	mtdcr (uicb0vr, 0x00000001); /* */
+
+	LED0_ON();
+
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf ("Board: XES XPedite1000 440GX\n");
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram (0);
+#else
+	dram_size = fixed_sdram ();
+#endif
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) 0x00000000;
+	uint *pend = (uint *) 0x08000000;
+	uint *p;
+
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ *
+ *  Assumes:	128 MB, non-ECC, non-registered
+ *		PLB @ 133 MHz
+ *
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+	uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)		*/
+	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0		*/
+	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)		*/
+	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0			*/
+	mtsdram (mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0	*/
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram (mem_tr0, 0x410a4012);	/* WR=2	 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
+	/* RA=10 RD=3			    */
+	mtsdram (mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
+	mtsdram (mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB	    */
+	mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
+	udelay (400);			/* Delay 200 usecs (min)	    */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit	    */
+	for (;;) {
+		mfsdram (mem_mcsts, reg);
+		if (reg & 0x80000000)
+			break;
+	}
+
+	return (128 * 1024 * 1024);	/* 128 MB			    */
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller * hose )
+{
+	unsigned long strap;
+	/* See if we're supposed to setup the pci */
+	mfsdr(sdr_sdstp1, strap);
+	if ((strap & 0x00010000) == 0) {
+		return (0);
+	}
+
+#if defined(CFG_PCI_FORCE_PCI_CONV)
+	/* Setup System Device Register PCIX0_XCR */
+	mfsdr(sdr_xcr, strap);
+	strap &= 0x0f000000;
+	mtsdr(sdr_xcr, strap);
+#endif
+	return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller * hose )
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/*--------------------------------------------------------------------------+
+	 * Disable everything
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0SA, 0 ); /* disable */
+	out32r( PCIX0_PIM1SA, 0 ); /* disable */
+	out32r( PCIX0_PIM2SA, 0 ); /* disable */
+	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
+
+	/*--------------------------------------------------------------------------+
+	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
+	 * options to not support sizes such as 128/256 MB.
+	 *--------------------------------------------------------------------------*/
+	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAH, 0 );
+	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+
+	out32r( PCIX0_BAR0, 0 );
+
+	/*--------------------------------------------------------------------------+
+	 * Program the board's subsystem id/vendor id
+	 *--------------------------------------------------------------------------*/
+	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+
+	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	return ((in32(CFG_GPIO_BASE + 0x1C) & 0x00000800) == 0);
+}
+#endif /* defined(CONFIG_PCI) */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+
+	return (ctrlc());
+}
+
+void post_word_store (ulong a)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(CFG_POST_WORD_ADDR);
+
+	*save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+	volatile ulong *save_addr =
+		(volatile ulong *)(CFG_POST_WORD_ADDR);
+
+	return *save_addr;
+}
+#endif
+
+/*-----------------------------------------------------------------------------
+ * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM
+ *-----------------------------------------------------------------------------
+ */
+static int enetaddr_num = 0;
+void board_get_enetaddr (uchar * enet)
+{
+	int i;
+	unsigned char buff[0x100], *cp;
+
+	/* Initialize I2C					*/
+	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+	/* Read 256 bytes in EEPROM				*/
+	i2c_read (0x50, 0, 1, buff, 0x100);
+
+	if (enetaddr_num == 0) {
+		cp = &buff[0xF4];
+		enetaddr_num = 1;
+	}
+	else
+		cp = &buff[0xFA];
+
+	for (i = 0; i < 6; i++,cp++)
+		enet[i] = *cp;
+
+	printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
+		enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
+
+}
diff --git a/board/xsengine/Makefile b/board/xsengine/Makefile
new file mode 100755
index 0000000..ed1464a
--- /dev/null
+++ b/board/xsengine/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= xsengine.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/xsengine/config.mk b/board/xsengine/config.mk
new file mode 100755
index 0000000..148c519
--- /dev/null
+++ b/board/xsengine/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xA3F80000
diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c
new file mode 100755
index 0000000..2b9afc7
--- /dev/null
+++ b/board/xsengine/flash.c
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define SWAP(x)               __swab32(x)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Functions */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors */
+	flash_protect ( FLAG_PROTECT_SET,CFG_FLASH_BASE,CFG_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
+	flash_protect ( FLAG_PROTECT_SET,CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
+				break;
+	case FLASH_S29GL064M:	printf ("S29GL064M (64Mbit, top boot sector size)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		debug ("Manufacturer: AMD\n");
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		debug ("Manufacturer: FUJITSU\n");
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		debug ("Manufacturer: *** unknown ***\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+
+	case AMD_ID_MIRROR:
+		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
+			addr[14], addr[15]);
+		switch(addr[14]) {
+		case AMD_ID_LV640U_2:
+			if (addr[15] != AMD_ID_LV640U_3) {
+				debug ("Chip: AMLV640U -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV640U\n");
+				info->flash_id += FLASH_AMLV640U;
+				info->sector_count = 128;
+				info->size = 0x01000000;
+			}
+			break;				/* => 16 MB	*/
+		case AMD_ID_GL064MT_2:
+			if (addr[15] != AMD_ID_GL064MT_3) {
+				debug ("Chip: S29GL064M-R3 -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: S29GL064M-R3\n");
+				info->flash_id += FLASH_S29GL064M;
+				info->sector_count = 128;
+				info->size = 0x01000000;
+			}
+			break;				/* => 16 MB	*/
+		default:
+			debug ("Chip: *** unknown ***\n");
+			info->flash_id = FLASH_UNKNOWN;
+			break;
+		}
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	switch (value) {
+	case AMD_ID_MIRROR:
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		/* only known types here - no default */
+		case FLASH_AMLV128U:
+		case FLASH_AMLV640U:
+		case FLASH_AMLV320U:
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				base += 0x20000;
+			}
+			break;
+		case FLASH_AMLV320B:
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				/*
+				 * The first 8 sectors are 8 kB,
+				 * all the other ones  are 64 kB
+				 */
+				base += (i < 8)
+					?  2 * ( 8 << 10)
+					:  2 * (64 << 10);
+			}
+			break;
+		}
+		break;
+
+	default:
+		return (0);
+		break;
+	}
+
+#if 0
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+#endif
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 100000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S
new file mode 100755
index 0000000..309faab
--- /dev/null
+++ b/board/xsengine/lowlevel_init.S
@@ -0,0 +1,221 @@
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+.globl lowlevel_init
+lowlevel_init:
+
+   mov      r10, lr
+
+/* ---- GPIO INITIALISATION ---- */
+/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
+
+   /* General purpose set registers */
+   ldr      r0,   =GPSR0
+   ldr      r1,   =CFG_GPSR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPSR1
+   ldr      r1,   =CFG_GPSR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPSR2
+   ldr      r1,   =CFG_GPSR2_VAL
+   str      r1,   [r0]
+
+   /* General purpose clear registers */
+   ldr      r0,   =GPCR0
+   ldr      r1,   =CFG_GPCR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPCR1
+   ldr      r1,   =CFG_GPCR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPCR2
+   ldr      r1,   =CFG_GPCR2_VAL
+   str      r1,   [r0]
+
+   /* General rising edge registers */
+   ldr      r0,   =GRER0
+   ldr      r1,   =CFG_GRER0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GRER1
+   ldr      r1,   =CFG_GRER1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GRER2
+   ldr      r1,   =CFG_GRER2_VAL
+   str      r1,   [r0]
+
+   /* General falling edge registers */
+   ldr      r0,   =GFER0
+   ldr      r1,   =CFG_GFER0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GFER1
+   ldr      r1,   =CFG_GFER1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GFER2
+   ldr      r1,   =CFG_GFER2_VAL
+   str      r1,   [r0]
+
+   /* General edge detect registers */
+   ldr      r0,   =GPDR0
+   ldr      r1,   =CFG_GPDR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR1
+   ldr      r1,   =CFG_GPDR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR2
+   ldr      r1,   =CFG_GPDR2_VAL
+   str      r1,   [r0]
+
+   /* General alternate function registers */
+   ldr      r0,   =GAFR0_L		/* [0:15] */
+   ldr      r1,   =CFG_GAFR0_L_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR0_U		/* [31:16] */
+   ldr      r1,   =CFG_GAFR0_U_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR1_L		/* [47:32] */
+   ldr      r1,   =CFG_GAFR1_L_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR1_U		/* [63:48] */
+   ldr      r1,   =CFG_GAFR1_U_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR2_L		/* [79:64] */
+   ldr      r1,   =CFG_GAFR2_L_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR2_U		/* [80] */
+   ldr      r1,   =CFG_GAFR2_U_VAL
+   str      r1,   [r0]
+
+   /* General purpose direction registers */
+   ldr      r0,   =GPDR0
+   ldr      r1,   =CFG_GPDR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR1
+   ldr      r1,   =CFG_GPDR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR2
+   ldr      r1,   =CFG_GPDR2_VAL
+   str      r1,   [r0]
+
+   /* Power manager sleep status */
+   ldr      r0,   =PSSR
+   ldr      r1,   =CFG_PSSR_VAL
+   str      r1,   [r0]
+
+/* ---- MEMORY INITIALISATION ---- */
+/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
+/* pause for 200 uSecs- allow internal clocks to settle */
+   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
+   mov r2, #0
+   str r2, [r3]
+   ldr r4, =0x300  	/* really 0x2E1 is about 200usec, so 0x300 should be plenty */
+1:
+   ldr r2, [r3]
+   cmp r4, r2
+   bgt 1b
+
+mem_init:
+/* get memory controller base address */
+   ldr     r1,  =MEMC_BASE
+
+/* ---- FLASH INITIALISATION ---- */
+/* Write MSC0 and read back to ensure data change is accepted by cpu */
+   ldr     r2,   =CFG_MSC0_VAL
+   str     r2,   [r1, #MSC0_OFFSET]
+   ldr     r2,   [r1, #MSC0_OFFSET]
+
+/* ---- SDRAM INITIALISATION ---- */
+/* get the MDREFR settings */
+   ldr     r2,  =CFG_MDREFR_VAL
+   str     r2,  [r1, #MDREFR_OFFSET]
+
+/* fetch platform value of MDCNFG */
+   ldr     r2,  =CFG_MDCNFG_VAL
+
+/* disable all sdram banks */
+   bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
+   bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+
+/* write initial value of MDCNFG, w/o enabling sdram banks */
+   str     r2,  [r1, #MDCNFG_OFFSET]
+
+/* pause for 200 uSecs */
+   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
+   mov r2, #0
+   str r2, [r3]
+   ldr r4, =0x300  	/* about 200 usec */
+1:
+   ldr r2, [r3]
+   cmp r4, r2
+   bgt 1b
+
+/* Access memory *not yet enabled* for CBR refresh cycles (8) */
+/* CBR is generated for all banks */
+
+   ldr     r2, =CFG_DRAM_BASE
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+
+/* get memory controller base address */
+   ldr     r2,  =MEMC_BASE
+
+/* Enable SDRAM bank 0 in MDCNFG register */
+   ldr     r2,  [r1, #MDCNFG_OFFSET]
+   orr     r2,  r2,  #MDCNFG_DE0
+   str     r2,  [r1, #MDCNFG_OFFSET]
+
+/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
+   ldr     r2,  =CFG_MDMRS_VAL
+   str     r2,  [r1, #MDMRS_OFFSET]
+
+/* ---- INTERRUPT INITIALISATION ---- */
+/* Disable (mask) all interrupts at the interrupt controller */
+/* clear the interrupt level register (use IRQ, not FIQ) */
+   mov     r1, #0
+   ldr     r2,  =ICLR
+   str     r1,  [r2]
+
+/* Set interrupt mask register */
+   ldr     r1,  =CFG_ICMR_VAL
+   ldr     r2,  =ICMR
+   str     r1,  [r2]
+
+/* ---- CLOCK INITIALISATION ---- */
+/* Disable the peripheral clocks, and set the core clock */
+
+/* Turn Off ALL on-chip peripheral clocks for re-configuration */
+   ldr     r1,  =CKEN
+   mov     r2,  #0
+   str     r2,  [r1]
+
+/* set core clocks */
+   ldr     r2,  =CFG_CCCR_VAL
+   ldr     r1,  =CCCR
+   str     r2,  [r1]
+
+#ifdef ENABLE32KHZ
+/* enable the 32Khz oscillator for RTC and PowerManager */
+   ldr     r1,  =OSCC
+   mov     r2,  #OSCC_OON
+   str     r2,  [r1]
+
+/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL has settled. */
+60:
+   ldr     r2, [r1]
+   ands    r2, r2, #1
+   beq     60b
+#endif
+
+/* Turn on needed clocks */
+   ldr     r1,  =CKEN
+   ldr     r2,  =CFG_CKEN_VAL
+   str     r2,  [r1]
+
+   mov   pc, r10
diff --git a/board/xsengine/u-boot.lds b/board/xsengine/u-boot.lds
new file mode 100755
index 0000000..db83875
--- /dev/null
+++ b/board/xsengine/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c
new file mode 100755
index 0000000..a9919db
--- /dev/null
+++ b/board/xsengine/xsengine.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number */
+	gd->bd->bi_arch_number = MACH_TYPE_XSENGINE;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_post_init (void)
+{
+	setenv ("stdout", "serial");
+	setenv ("stderr", "serial");
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile
new file mode 100755
index 0000000..8b10993
--- /dev/null
+++ b/board/zpc1900/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/zpc1900/config.mk b/board/zpc1900/config.mk
new file mode 100755
index 0000000..1072dc7
--- /dev/null
+++ b/board/zpc1900/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# ZPC.1900 board
+#
+
+TEXT_BASE = 0xFFE00000
diff --git a/board/zpc1900/u-boot.lds b/board/zpc1900/u-boot.lds
new file mode 100755
index 0000000..18c4b46
--- /dev/null
+++ b/board/zpc1900/u-boot.lds
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c
new file mode 100755
index 0000000..6d16a0d
--- /dev/null
+++ b/board/zpc1900/zpc1900.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB  */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB  */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC  */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   0,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   0,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   0,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   0,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   0,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER  */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV  */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN  */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER  */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL    */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS    */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN  */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN CLSN */
+	/* PC28 */ {   0,   0,   0,   0,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC21 */ {   0,   0,   0,   0,   0,   0   }, /* PC21 */
+	/* PC20 */ {   0,   0,   0,   0,   0,   0   }, /* PC20 */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Rx Clock (CLK13) */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RENA */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* LXT972 MDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* LXT972 MDIO */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD  */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD  */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   0,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+#ifdef CFG_NVRAM_ACCESS_ROUTINE
+void *nvram_read(void *dest, long src, size_t count)
+{
+	return memcpy(dest, (const void *)src, count);
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+	vu_char     *p1 = (vu_char *)(CFG_EEPROM + 0x1555);
+	vu_char     *p2 = (vu_char *)(CFG_EEPROM + 0x0AAA);
+	vu_char     *d = (vu_char *)dest;
+	const uchar *s = (const uchar *)src;
+
+	/* Unprotect the EEPROM */
+	*p1 = 0xAA;
+	*p2 = 0x55;
+	*p1 = 0x80;
+	*p1 = 0xAA;
+	*p2 = 0x55;
+	*p1 = 0x20;
+	udelay(10000);
+
+	/* Write the data to the EEPROM */
+	while (count--) {
+		*d++ = *s++;
+		while (*(d - 1) != *(s - 1))
+			/* wait */;
+	}
+
+	/* Protect the EEPROM */
+	*p1 = 0xAA;
+	*p2 = 0x55;
+	*p1 = 0xA0;
+	udelay(10000);
+}
+#endif /* CFG_NVRAM_ACCESS_ROUTINE */
+
+long int initdram(int board_type)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	vu_char *ramaddr;
+	uchar c = 0xFF;
+	long int msize = CFG_SDRAM_SIZE;
+	uint psdmr = CFG_PSDMR;
+	int i;
+
+	if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
+		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+		immap->im_siu_conf.sc_siumcr =
+			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
+			| SIUMCR_LBPC01;
+	}
+
+#ifndef CFG_RAMBOOT
+	immap->im_siu_conf.sc_ppc_acr  = 0x03;
+	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifdef CFG_LSDRAM_BASE
+	/*
+	  Initialise local bus SDRAM only if the pins
+	  are configured as local bus pins and not as PCI.
+	*/
+	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
+		memctl->memc_lsrt  = CFG_LSRT;
+		memctl->memc_or4   = 0xFFC01480;
+		memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
+		ramaddr = (vu_char *)CFG_LSDRAM_BASE;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
+		for (i = 0; i < 8; i++)
+			*ramaddr = c;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_MRW;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_RFEN;
+	}
+#endif /* CFG_LSDRAM_BASE */
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or2  = 0xFC0028C0;
+	memctl->memc_br2  = CFG_SDRAM_BASE | 0x00000041;
+	/*
+	 * The mode data for Mode Register Write command must appear on
+	 * the address lines during a mode-set cycle. It is driven by
+	 * the memory controller, in single PowerQUICC II mode,
+	 * according to PSDMR[CL] and PSDMR[BL] fields. In
+	 * 60x-compatible mode, software must drive the correct value on
+	 * the address lines. BL=0 because for 64-bit port size burst
+	 * length must be 4.
+	 */
+	ramaddr = (vu_char *)(CFG_SDRAM_BASE |
+			      ((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+	*ramaddr = c;
+#endif /* CFG_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
+	return 0;
+}